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9f6c9258 DK |
1 | /* bnx2x_cmn.h: Broadcom Everest network driver. |
2 | * | |
85b26ea1 | 3 | * Copyright (c) 2007-2012 Broadcom Corporation |
9f6c9258 DK |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> | |
10 | * Written by: Eliezer Tamir | |
11 | * Based on code from Michael Chan's bnx2 driver | |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
13 | * Slowpath and fastpath rework by Vladislav Zolotarov | |
14 | * Statistics and Link management by Yitchak Gertner | |
15 | * | |
16 | */ | |
17 | #ifndef BNX2X_CMN_H | |
18 | #define BNX2X_CMN_H | |
19 | ||
20 | #include <linux/types.h> | |
619c5cb6 | 21 | #include <linux/pci.h> |
9f6c9258 | 22 | #include <linux/netdevice.h> |
614c76df | 23 | #include <linux/etherdevice.h> |
9f6c9258 DK |
24 | |
25 | ||
26 | #include "bnx2x.h" | |
27 | ||
619c5cb6 VZ |
28 | /* This is used as a replacement for an MCP if it's not present */ |
29 | extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ | |
30 | ||
d6214d7a | 31 | extern int num_queues; |
0e8d2ec5 | 32 | extern int int_mode; |
9f6c9258 | 33 | |
b3b83c3f DK |
34 | /************************ Macros ********************************/ |
35 | #define BNX2X_PCI_FREE(x, y, size) \ | |
36 | do { \ | |
37 | if (x) { \ | |
38 | dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ | |
39 | x = NULL; \ | |
40 | y = 0; \ | |
41 | } \ | |
42 | } while (0) | |
43 | ||
44 | #define BNX2X_FREE(x) \ | |
45 | do { \ | |
46 | if (x) { \ | |
47 | kfree((void *)x); \ | |
48 | x = NULL; \ | |
49 | } \ | |
50 | } while (0) | |
51 | ||
52 | #define BNX2X_PCI_ALLOC(x, y, size) \ | |
53 | do { \ | |
54 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ | |
55 | if (x == NULL) \ | |
56 | goto alloc_mem_err; \ | |
57 | memset((void *)x, 0, size); \ | |
58 | } while (0) | |
59 | ||
60 | #define BNX2X_ALLOC(x, size) \ | |
61 | do { \ | |
62 | x = kzalloc(size, GFP_KERNEL); \ | |
63 | if (x == NULL) \ | |
64 | goto alloc_mem_err; \ | |
65 | } while (0) | |
66 | ||
9f6c9258 DK |
67 | /*********************** Interfaces **************************** |
68 | * Functions that need to be implemented by each driver version | |
69 | */ | |
619c5cb6 VZ |
70 | /* Init */ |
71 | ||
72 | /** | |
73 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
74 | * | |
75 | * @bp: driver handle | |
76 | * @unload_mode: requested function's unload mode | |
77 | * | |
78 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
79 | */ | |
80 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); | |
81 | ||
82 | /** | |
83 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
84 | * | |
85 | * @bp: driver handle | |
86 | */ | |
87 | void bnx2x_send_unload_done(struct bnx2x *bp); | |
88 | ||
89 | /** | |
96305234 | 90 | * bnx2x_config_rss_pf - configure RSS parameters in a PF. |
619c5cb6 VZ |
91 | * |
92 | * @bp: driver handle | |
96305234 | 93 | * @rss_obj RSS object to use |
619c5cb6 VZ |
94 | * @ind_table: indirection table to configure |
95 | * @config_hash: re-configure RSS hash keys configuration | |
96 | */ | |
96305234 | 97 | int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, |
5d317c6a | 98 | bool config_hash); |
619c5cb6 VZ |
99 | |
100 | /** | |
101 | * bnx2x__init_func_obj - init function object | |
102 | * | |
103 | * @bp: driver handle | |
104 | * | |
105 | * Initializes the Function Object with the appropriate | |
106 | * parameters which include a function slow path driver | |
107 | * interface. | |
108 | */ | |
109 | void bnx2x__init_func_obj(struct bnx2x *bp); | |
110 | ||
111 | /** | |
112 | * bnx2x_setup_queue - setup eth queue. | |
113 | * | |
114 | * @bp: driver handle | |
115 | * @fp: pointer to the fastpath structure | |
116 | * @leading: boolean | |
117 | * | |
118 | */ | |
119 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
120 | bool leading); | |
121 | ||
122 | /** | |
123 | * bnx2x_setup_leading - bring up a leading eth queue. | |
124 | * | |
125 | * @bp: driver handle | |
126 | */ | |
127 | int bnx2x_setup_leading(struct bnx2x *bp); | |
128 | ||
129 | /** | |
130 | * bnx2x_fw_command - send the MCP a request | |
131 | * | |
132 | * @bp: driver handle | |
133 | * @command: request | |
134 | * @param: request's parameter | |
135 | * | |
136 | * block until there is a reply | |
137 | */ | |
138 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); | |
9f6c9258 DK |
139 | |
140 | /** | |
e8920674 | 141 | * bnx2x_initial_phy_init - initialize link parameters structure variables. |
9f6c9258 | 142 | * |
e8920674 DK |
143 | * @bp: driver handle |
144 | * @load_mode: current mode | |
9f6c9258 DK |
145 | */ |
146 | u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); | |
147 | ||
148 | /** | |
e8920674 | 149 | * bnx2x_link_set - configure hw according to link parameters structure. |
9f6c9258 | 150 | * |
e8920674 | 151 | * @bp: driver handle |
9f6c9258 DK |
152 | */ |
153 | void bnx2x_link_set(struct bnx2x *bp); | |
154 | ||
155 | /** | |
e8920674 | 156 | * bnx2x_link_test - query link status. |
9f6c9258 | 157 | * |
e8920674 DK |
158 | * @bp: driver handle |
159 | * @is_serdes: bool | |
9f6c9258 | 160 | * |
e8920674 | 161 | * Returns 0 if link is UP. |
9f6c9258 | 162 | */ |
a22f0788 | 163 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); |
9f6c9258 | 164 | |
619c5cb6 VZ |
165 | /** |
166 | * bnx2x_drv_pulse - write driver pulse to shmem | |
167 | * | |
168 | * @bp: driver handle | |
169 | * | |
170 | * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox | |
171 | * in the shmem. | |
172 | */ | |
173 | void bnx2x_drv_pulse(struct bnx2x *bp); | |
174 | ||
175 | /** | |
176 | * bnx2x_igu_ack_sb - update IGU with current SB value | |
177 | * | |
178 | * @bp: driver handle | |
179 | * @igu_sb_id: SB id | |
180 | * @segment: SB segment | |
181 | * @index: SB index | |
182 | * @op: SB operation | |
183 | * @update: is HW update required | |
184 | */ | |
185 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, | |
186 | u16 index, u8 op, u8 update); | |
187 | ||
c9ee9206 VZ |
188 | /* Disable transactions from chip to host */ |
189 | void bnx2x_pf_disable(struct bnx2x *bp); | |
190 | ||
9f6c9258 | 191 | /** |
e8920674 | 192 | * bnx2x__link_status_update - handles link status change. |
9f6c9258 | 193 | * |
e8920674 | 194 | * @bp: driver handle |
9f6c9258 DK |
195 | */ |
196 | void bnx2x__link_status_update(struct bnx2x *bp); | |
197 | ||
f85582f8 | 198 | /** |
e8920674 | 199 | * bnx2x_link_report - report link status to upper layer. |
f85582f8 | 200 | * |
e8920674 | 201 | * @bp: driver handle |
f85582f8 DK |
202 | */ |
203 | void bnx2x_link_report(struct bnx2x *bp); | |
204 | ||
2ae17f66 VZ |
205 | /* None-atomic version of bnx2x_link_report() */ |
206 | void __bnx2x_link_report(struct bnx2x *bp); | |
207 | ||
0793f83f | 208 | /** |
e8920674 | 209 | * bnx2x_get_mf_speed - calculate MF speed. |
0793f83f | 210 | * |
e8920674 | 211 | * @bp: driver handle |
0793f83f | 212 | * |
e8920674 | 213 | * Takes into account current linespeed and MF configuration. |
0793f83f DK |
214 | */ |
215 | u16 bnx2x_get_mf_speed(struct bnx2x *bp); | |
216 | ||
9f6c9258 | 217 | /** |
e8920674 | 218 | * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler |
9f6c9258 | 219 | * |
e8920674 DK |
220 | * @irq: irq number |
221 | * @dev_instance: private instance | |
9f6c9258 DK |
222 | */ |
223 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); | |
224 | ||
225 | /** | |
e8920674 | 226 | * bnx2x_interrupt - non MSI-X interrupt handler |
9f6c9258 | 227 | * |
e8920674 DK |
228 | * @irq: irq number |
229 | * @dev_instance: private instance | |
9f6c9258 DK |
230 | */ |
231 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); | |
232 | #ifdef BCM_CNIC | |
233 | ||
234 | /** | |
e8920674 | 235 | * bnx2x_cnic_notify - send command to cnic driver |
9f6c9258 | 236 | * |
e8920674 DK |
237 | * @bp: driver handle |
238 | * @cmd: command | |
9f6c9258 DK |
239 | */ |
240 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); | |
241 | ||
242 | /** | |
e8920674 | 243 | * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information |
9f6c9258 | 244 | * |
e8920674 | 245 | * @bp: driver handle |
9f6c9258 DK |
246 | */ |
247 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); | |
37ae41a9 MS |
248 | |
249 | /** | |
250 | * bnx2x_setup_cnic_info - provides cnic with updated info | |
251 | * | |
252 | * @bp: driver handle | |
253 | */ | |
254 | void bnx2x_setup_cnic_info(struct bnx2x *bp); | |
255 | ||
9f6c9258 DK |
256 | #endif |
257 | ||
258 | /** | |
e8920674 | 259 | * bnx2x_int_enable - enable HW interrupts. |
9f6c9258 | 260 | * |
e8920674 | 261 | * @bp: driver handle |
9f6c9258 DK |
262 | */ |
263 | void bnx2x_int_enable(struct bnx2x *bp); | |
264 | ||
265 | /** | |
e8920674 DK |
266 | * bnx2x_int_disable_sync - disable interrupts. |
267 | * | |
268 | * @bp: driver handle | |
269 | * @disable_hw: true, disable HW interrupts. | |
9f6c9258 | 270 | * |
e8920674 DK |
271 | * This function ensures that there are no |
272 | * ISRs or SP DPCs (sp_task) are running after it returns. | |
9f6c9258 DK |
273 | */ |
274 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); | |
275 | ||
9f6c9258 | 276 | /** |
e8920674 DK |
277 | * bnx2x_nic_init - init driver internals. |
278 | * | |
279 | * @bp: driver handle | |
280 | * @load_code: COMMON, PORT or FUNCTION | |
281 | * | |
282 | * Initializes: | |
9f6c9258 DK |
283 | * - rings |
284 | * - status blocks | |
285 | * - etc. | |
9f6c9258 DK |
286 | */ |
287 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code); | |
288 | ||
289 | /** | |
e8920674 | 290 | * bnx2x_alloc_mem - allocate driver's memory. |
9f6c9258 | 291 | * |
e8920674 | 292 | * @bp: driver handle |
9f6c9258 DK |
293 | */ |
294 | int bnx2x_alloc_mem(struct bnx2x *bp); | |
295 | ||
296 | /** | |
e8920674 | 297 | * bnx2x_free_mem - release driver's memory. |
9f6c9258 | 298 | * |
e8920674 | 299 | * @bp: driver handle |
9f6c9258 DK |
300 | */ |
301 | void bnx2x_free_mem(struct bnx2x *bp); | |
302 | ||
9f6c9258 | 303 | /** |
e8920674 | 304 | * bnx2x_set_num_queues - set number of queues according to mode. |
9f6c9258 | 305 | * |
e8920674 | 306 | * @bp: driver handle |
9f6c9258 | 307 | */ |
d6214d7a | 308 | void bnx2x_set_num_queues(struct bnx2x *bp); |
9f6c9258 DK |
309 | |
310 | /** | |
e8920674 DK |
311 | * bnx2x_chip_cleanup - cleanup chip internals. |
312 | * | |
313 | * @bp: driver handle | |
314 | * @unload_mode: COMMON, PORT, FUNCTION | |
315 | * | |
9f6c9258 | 316 | * - Cleanup MAC configuration. |
e8920674 | 317 | * - Closes clients. |
9f6c9258 | 318 | * - etc. |
9f6c9258 DK |
319 | */ |
320 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode); | |
321 | ||
322 | /** | |
e8920674 | 323 | * bnx2x_acquire_hw_lock - acquire HW lock. |
9f6c9258 | 324 | * |
e8920674 DK |
325 | * @bp: driver handle |
326 | * @resource: resource bit which was locked | |
9f6c9258 DK |
327 | */ |
328 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); | |
329 | ||
330 | /** | |
e8920674 | 331 | * bnx2x_release_hw_lock - release HW lock. |
9f6c9258 | 332 | * |
e8920674 DK |
333 | * @bp: driver handle |
334 | * @resource: resource bit which was locked | |
9f6c9258 DK |
335 | */ |
336 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); | |
337 | ||
c9ee9206 VZ |
338 | /** |
339 | * bnx2x_release_leader_lock - release recovery leader lock | |
340 | * | |
341 | * @bp: driver handle | |
342 | */ | |
343 | int bnx2x_release_leader_lock(struct bnx2x *bp); | |
344 | ||
9f6c9258 | 345 | /** |
e8920674 DK |
346 | * bnx2x_set_eth_mac - configure eth MAC address in the HW |
347 | * | |
348 | * @bp: driver handle | |
349 | * @set: set or clear | |
9f6c9258 | 350 | * |
e8920674 | 351 | * Configures according to the value in netdev->dev_addr. |
9f6c9258 | 352 | */ |
619c5cb6 | 353 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); |
9f6c9258 | 354 | |
ec6ba945 | 355 | /** |
619c5cb6 | 356 | * bnx2x_set_rx_mode - set MAC filtering configurations. |
ec6ba945 | 357 | * |
619c5cb6 | 358 | * @dev: netdevice |
ec6ba945 | 359 | * |
619c5cb6 VZ |
360 | * called with netif_tx_lock from dev_mcast.c |
361 | * If bp->state is OPEN, should be called with | |
362 | * netif_addr_lock_bh() | |
ec6ba945 | 363 | */ |
619c5cb6 | 364 | void bnx2x_set_rx_mode(struct net_device *dev); |
ec6ba945 VZ |
365 | |
366 | /** | |
619c5cb6 | 367 | * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. |
ec6ba945 | 368 | * |
e8920674 | 369 | * @bp: driver handle |
619c5cb6 VZ |
370 | * |
371 | * If bp->state is OPEN, should be called with | |
372 | * netif_addr_lock_bh(). | |
ec6ba945 | 373 | */ |
619c5cb6 | 374 | void bnx2x_set_storm_rx_mode(struct bnx2x *bp); |
ec6ba945 | 375 | |
9f6c9258 | 376 | /** |
619c5cb6 | 377 | * bnx2x_set_q_rx_mode - configures rx_mode for a single queue. |
9f6c9258 | 378 | * |
619c5cb6 VZ |
379 | * @bp: driver handle |
380 | * @cl_id: client id | |
381 | * @rx_mode_flags: rx mode configuration | |
382 | * @rx_accept_flags: rx accept configuration | |
383 | * @tx_accept_flags: tx accept configuration (tx switch) | |
384 | * @ramrod_flags: ramrod configuration | |
9f6c9258 | 385 | */ |
619c5cb6 VZ |
386 | void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, |
387 | unsigned long rx_mode_flags, | |
388 | unsigned long rx_accept_flags, | |
389 | unsigned long tx_accept_flags, | |
390 | unsigned long ramrod_flags); | |
9f6c9258 | 391 | |
9f6c9258 | 392 | /* Parity errors related */ |
889b9af3 AE |
393 | void bnx2x_set_pf_load(struct bnx2x *bp); |
394 | bool bnx2x_clear_pf_load(struct bnx2x *bp); | |
c9ee9206 VZ |
395 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); |
396 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); | |
397 | void bnx2x_set_reset_in_progress(struct bnx2x *bp); | |
398 | void bnx2x_set_reset_global(struct bnx2x *bp); | |
9f6c9258 DK |
399 | void bnx2x_disable_close_the_gate(struct bnx2x *bp); |
400 | ||
9f6c9258 | 401 | /** |
e8920674 | 402 | * bnx2x_sp_event - handle ramrods completion. |
9f6c9258 | 403 | * |
e8920674 DK |
404 | * @fp: fastpath handle for the event |
405 | * @rr_cqe: eth_rx_cqe | |
9f6c9258 | 406 | */ |
f85582f8 | 407 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); |
9f6c9258 | 408 | |
523224a3 | 409 | /** |
e8920674 | 410 | * bnx2x_ilt_set_info - prepare ILT configurations. |
523224a3 | 411 | * |
e8920674 | 412 | * @bp: driver handle |
523224a3 DK |
413 | */ |
414 | void bnx2x_ilt_set_info(struct bnx2x *bp); | |
9f6c9258 | 415 | |
e4901dde | 416 | /** |
e8920674 | 417 | * bnx2x_dcbx_init - initialize dcbx protocol. |
e4901dde | 418 | * |
e8920674 | 419 | * @bp: driver handle |
e4901dde | 420 | */ |
9876879f | 421 | void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem); |
e4901dde | 422 | |
f85582f8 | 423 | /** |
e8920674 | 424 | * bnx2x_set_power_state - set power state to the requested value. |
f85582f8 | 425 | * |
e8920674 DK |
426 | * @bp: driver handle |
427 | * @state: required state D0 or D3hot | |
f85582f8 | 428 | * |
e8920674 | 429 | * Currently only D0 and D3hot are supported. |
f85582f8 DK |
430 | */ |
431 | int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); | |
432 | ||
e3835b99 | 433 | /** |
e8920674 | 434 | * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. |
e3835b99 | 435 | * |
e8920674 DK |
436 | * @bp: driver handle |
437 | * @value: new value | |
e3835b99 DK |
438 | */ |
439 | void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); | |
619c5cb6 VZ |
440 | /* Error handling */ |
441 | void bnx2x_panic_dump(struct bnx2x *bp); | |
e3835b99 | 442 | |
7a25cc73 DK |
443 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); |
444 | ||
452427b0 YM |
445 | /* validate currect fw is loaded */ |
446 | bool bnx2x_test_firmware_version(struct bnx2x *bp, bool is_err); | |
447 | ||
f85582f8 DK |
448 | /* dev_close main block */ |
449 | int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode); | |
450 | ||
451 | /* dev_open main block */ | |
452 | int bnx2x_nic_load(struct bnx2x *bp, int load_mode); | |
453 | ||
454 | /* hard_xmit callback */ | |
455 | netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
456 | ||
6383c0b3 AE |
457 | /* setup_tc callback */ |
458 | int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); | |
459 | ||
8307fa3e VZ |
460 | /* select_queue callback */ |
461 | u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); | |
462 | ||
a9fccec7 DK |
463 | /* reload helper */ |
464 | int bnx2x_reload_if_running(struct net_device *dev); | |
465 | ||
f85582f8 DK |
466 | int bnx2x_change_mac_addr(struct net_device *dev, void *p); |
467 | ||
468 | /* NAPI poll Rx part */ | |
469 | int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); | |
470 | ||
619c5cb6 VZ |
471 | void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
472 | u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod); | |
473 | ||
f85582f8 | 474 | /* NAPI poll Tx part */ |
6383c0b3 | 475 | int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); |
f85582f8 DK |
476 | |
477 | /* suspend/resume callbacks */ | |
478 | int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); | |
479 | int bnx2x_resume(struct pci_dev *pdev); | |
480 | ||
481 | /* Release IRQ vectors */ | |
482 | void bnx2x_free_irq(struct bnx2x *bp); | |
483 | ||
b3b83c3f DK |
484 | void bnx2x_free_fp_mem(struct bnx2x *bp); |
485 | int bnx2x_alloc_fp_mem(struct bnx2x *bp); | |
f85582f8 DK |
486 | void bnx2x_init_rx_rings(struct bnx2x *bp); |
487 | void bnx2x_free_skbs(struct bnx2x *bp); | |
488 | void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); | |
489 | void bnx2x_netif_start(struct bnx2x *bp); | |
490 | ||
d6214d7a | 491 | /** |
e8920674 | 492 | * bnx2x_enable_msix - set msix configuration. |
d6214d7a | 493 | * |
e8920674 | 494 | * @bp: driver handle |
d6214d7a | 495 | * |
e8920674 DK |
496 | * fills msix_table, requests vectors, updates num_queues |
497 | * according to number of available vectors. | |
d6214d7a | 498 | */ |
0e8d2ec5 | 499 | int bnx2x_enable_msix(struct bnx2x *bp); |
d6214d7a DK |
500 | |
501 | /** | |
e8920674 | 502 | * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly |
d6214d7a | 503 | * |
e8920674 | 504 | * @bp: driver handle |
d6214d7a DK |
505 | */ |
506 | int bnx2x_enable_msi(struct bnx2x *bp); | |
507 | ||
d6214d7a | 508 | /** |
e8920674 | 509 | * bnx2x_poll - NAPI callback |
d6214d7a | 510 | * |
e8920674 DK |
511 | * @napi: napi structure |
512 | * @budget: | |
d6214d7a | 513 | * |
d6214d7a DK |
514 | */ |
515 | int bnx2x_poll(struct napi_struct *napi, int budget); | |
f85582f8 DK |
516 | |
517 | /** | |
e8920674 | 518 | * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure |
f85582f8 | 519 | * |
e8920674 | 520 | * @bp: driver handle |
f85582f8 DK |
521 | */ |
522 | int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp); | |
e8920674 DK |
523 | |
524 | /** | |
525 | * bnx2x_free_mem_bp - release memories outsize main driver structure | |
526 | * | |
527 | * @bp: driver handle | |
528 | */ | |
f85582f8 DK |
529 | void bnx2x_free_mem_bp(struct bnx2x *bp); |
530 | ||
531 | /** | |
e8920674 | 532 | * bnx2x_change_mtu - change mtu netdev callback |
f85582f8 | 533 | * |
e8920674 DK |
534 | * @dev: net device |
535 | * @new_mtu: requested mtu | |
f85582f8 | 536 | * |
f85582f8 DK |
537 | */ |
538 | int bnx2x_change_mtu(struct net_device *dev, int new_mtu); | |
539 | ||
3857e3ee | 540 | #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) |
bf61ee14 VZ |
541 | /** |
542 | * bnx2x_fcoe_get_wwn - return the requested WWN value for this port | |
543 | * | |
544 | * @dev: net_device | |
545 | * @wwn: output buffer | |
546 | * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) | |
547 | * | |
548 | */ | |
549 | int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); | |
550 | #endif | |
621b4d66 | 551 | |
c8f44aff | 552 | netdev_features_t bnx2x_fix_features(struct net_device *dev, |
621b4d66 | 553 | netdev_features_t features); |
c8f44aff | 554 | int bnx2x_set_features(struct net_device *dev, netdev_features_t features); |
66371c44 | 555 | |
f85582f8 | 556 | /** |
e8920674 | 557 | * bnx2x_tx_timeout - tx timeout netdev callback |
f85582f8 | 558 | * |
e8920674 | 559 | * @dev: net device |
f85582f8 DK |
560 | */ |
561 | void bnx2x_tx_timeout(struct net_device *dev); | |
562 | ||
619c5cb6 VZ |
563 | /*********************** Inlines **********************************/ |
564 | /*********************** Fast path ********************************/ | |
9f6c9258 DK |
565 | static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) |
566 | { | |
9f6c9258 | 567 | barrier(); /* status block is written to by the chip */ |
523224a3 | 568 | fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; |
9f6c9258 DK |
569 | } |
570 | ||
619c5cb6 VZ |
571 | static inline void bnx2x_update_rx_prod_gen(struct bnx2x *bp, |
572 | struct bnx2x_fastpath *fp, u16 bd_prod, | |
573 | u16 rx_comp_prod, u16 rx_sge_prod, u32 start) | |
9f6c9258 DK |
574 | { |
575 | struct ustorm_eth_rx_producers rx_prods = {0}; | |
619c5cb6 | 576 | u32 i; |
9f6c9258 DK |
577 | |
578 | /* Update producers */ | |
579 | rx_prods.bd_prod = bd_prod; | |
580 | rx_prods.cqe_prod = rx_comp_prod; | |
581 | rx_prods.sge_prod = rx_sge_prod; | |
582 | ||
583 | /* | |
584 | * Make sure that the BD and SGE data is updated before updating the | |
585 | * producers since FW might read the BD/SGE right after the producer | |
586 | * is updated. | |
587 | * This is only applicable for weak-ordered memory model archs such | |
588 | * as IA-64. The following barrier is also mandatory since FW will | |
589 | * assumes BDs must have buffers. | |
590 | */ | |
591 | wmb(); | |
592 | ||
619c5cb6 VZ |
593 | for (i = 0; i < sizeof(rx_prods)/4; i++) |
594 | REG_WR(bp, start + i*4, ((u32 *)&rx_prods)[i]); | |
9f6c9258 DK |
595 | |
596 | mmiowb(); /* keep prod updates ordered */ | |
597 | ||
598 | DP(NETIF_MSG_RX_STATUS, | |
599 | "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", | |
600 | fp->index, bd_prod, rx_comp_prod, rx_sge_prod); | |
601 | } | |
602 | ||
f2e0899f DK |
603 | static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, |
604 | u8 segment, u16 index, u8 op, | |
605 | u8 update, u32 igu_addr) | |
606 | { | |
607 | struct igu_regular cmd_data = {0}; | |
608 | ||
609 | cmd_data.sb_id_and_flags = | |
610 | ((index << IGU_REGULAR_SB_INDEX_SHIFT) | | |
611 | (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | | |
612 | (update << IGU_REGULAR_BUPDATE_SHIFT) | | |
613 | (op << IGU_REGULAR_ENABLE_INT_SHIFT)); | |
614 | ||
51c1a580 | 615 | DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", |
f2e0899f DK |
616 | cmd_data.sb_id_and_flags, igu_addr); |
617 | REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); | |
618 | ||
619 | /* Make sure that ACK is written */ | |
620 | mmiowb(); | |
621 | barrier(); | |
622 | } | |
623 | ||
f2e0899f DK |
624 | static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, |
625 | u8 storm, u16 index, u8 op, u8 update) | |
9f6c9258 DK |
626 | { |
627 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
628 | COMMAND_REG_INT_ACK); | |
629 | struct igu_ack_register igu_ack; | |
630 | ||
631 | igu_ack.status_block_index = index; | |
632 | igu_ack.sb_id_and_flags = | |
633 | ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | | |
634 | (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | | |
635 | (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | | |
636 | (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); | |
637 | ||
9f6c9258 DK |
638 | REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); |
639 | ||
640 | /* Make sure that ACK is written */ | |
641 | mmiowb(); | |
642 | barrier(); | |
643 | } | |
f2e0899f | 644 | |
f2e0899f DK |
645 | static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, |
646 | u16 index, u8 op, u8 update) | |
647 | { | |
648 | if (bp->common.int_block == INT_BLOCK_HC) | |
649 | bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); | |
650 | else { | |
651 | u8 segment; | |
652 | ||
653 | if (CHIP_INT_MODE_IS_BC(bp)) | |
654 | segment = storm; | |
655 | else if (igu_sb_id != bp->igu_dsb_id) | |
656 | segment = IGU_SEG_ACCESS_DEF; | |
657 | else if (storm == ATTENTION_ID) | |
658 | segment = IGU_SEG_ACCESS_ATTN; | |
659 | else | |
660 | segment = IGU_SEG_ACCESS_DEF; | |
661 | bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); | |
662 | } | |
663 | } | |
664 | ||
665 | static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) | |
9f6c9258 DK |
666 | { |
667 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
668 | COMMAND_REG_SIMD_MASK); | |
669 | u32 result = REG_RD(bp, hc_addr); | |
670 | ||
f2e0899f | 671 | barrier(); |
9f6c9258 DK |
672 | return result; |
673 | } | |
674 | ||
f2e0899f DK |
675 | static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) |
676 | { | |
677 | u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); | |
678 | u32 result = REG_RD(bp, igu_addr); | |
679 | ||
51c1a580 | 680 | DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", |
f2e0899f DK |
681 | result, igu_addr); |
682 | ||
683 | barrier(); | |
684 | return result; | |
685 | } | |
686 | ||
687 | static inline u16 bnx2x_ack_int(struct bnx2x *bp) | |
688 | { | |
689 | barrier(); | |
690 | if (bp->common.int_block == INT_BLOCK_HC) | |
691 | return bnx2x_hc_ack_int(bp); | |
692 | else | |
693 | return bnx2x_igu_ack_int(bp); | |
694 | } | |
695 | ||
6383c0b3 | 696 | static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) |
9f6c9258 DK |
697 | { |
698 | /* Tell compiler that consumer and producer can change */ | |
699 | barrier(); | |
6383c0b3 | 700 | return txdata->tx_pkt_prod != txdata->tx_pkt_cons; |
9f6c9258 DK |
701 | } |
702 | ||
6383c0b3 AE |
703 | static inline u16 bnx2x_tx_avail(struct bnx2x *bp, |
704 | struct bnx2x_fp_txdata *txdata) | |
9f6c9258 DK |
705 | { |
706 | s16 used; | |
707 | u16 prod; | |
708 | u16 cons; | |
709 | ||
6383c0b3 AE |
710 | prod = txdata->tx_bd_prod; |
711 | cons = txdata->tx_bd_cons; | |
9f6c9258 DK |
712 | |
713 | /* NUM_TX_RINGS = number of "next-page" entries | |
714 | It will be used as a threshold */ | |
715 | used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS; | |
716 | ||
717 | #ifdef BNX2X_STOP_ON_ERROR | |
718 | WARN_ON(used < 0); | |
6383c0b3 AE |
719 | WARN_ON(used > bp->tx_ring_size); |
720 | WARN_ON((bp->tx_ring_size - used) > MAX_TX_AVAIL); | |
9f6c9258 DK |
721 | #endif |
722 | ||
6383c0b3 | 723 | return (s16)(bp->tx_ring_size) - used; |
9f6c9258 DK |
724 | } |
725 | ||
6383c0b3 | 726 | static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) |
9f6c9258 DK |
727 | { |
728 | u16 hw_cons; | |
729 | ||
730 | /* Tell compiler that status block fields can change */ | |
731 | barrier(); | |
6383c0b3 AE |
732 | hw_cons = le16_to_cpu(*txdata->tx_cons_sb); |
733 | return hw_cons != txdata->tx_pkt_cons; | |
734 | } | |
735 | ||
736 | static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) | |
737 | { | |
738 | u8 cos; | |
739 | for_each_cos_in_tx_queue(fp, cos) | |
65565884 | 740 | if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) |
6383c0b3 AE |
741 | return true; |
742 | return false; | |
9f6c9258 DK |
743 | } |
744 | ||
523224a3 DK |
745 | static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) |
746 | { | |
747 | u16 rx_cons_sb; | |
748 | ||
749 | /* Tell compiler that status block fields can change */ | |
750 | barrier(); | |
751 | rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); | |
752 | if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) | |
753 | rx_cons_sb++; | |
754 | return (fp->rx_comp_cons != rx_cons_sb); | |
755 | } | |
f85582f8 | 756 | |
f2e0899f | 757 | /** |
619c5cb6 | 758 | * bnx2x_tx_disable - disables tx from stack point of view |
f2e0899f | 759 | * |
e8920674 | 760 | * @bp: driver handle |
f2e0899f DK |
761 | */ |
762 | static inline void bnx2x_tx_disable(struct bnx2x *bp) | |
763 | { | |
764 | netif_tx_disable(bp->dev); | |
765 | netif_carrier_off(bp->dev); | |
766 | } | |
767 | ||
9f6c9258 DK |
768 | static inline void bnx2x_free_rx_sge(struct bnx2x *bp, |
769 | struct bnx2x_fastpath *fp, u16 index) | |
770 | { | |
771 | struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; | |
772 | struct page *page = sw_buf->page; | |
773 | struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; | |
774 | ||
775 | /* Skip "next page" elements */ | |
776 | if (!page) | |
777 | return; | |
778 | ||
779 | dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), | |
4bca60f4 | 780 | SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); |
9f6c9258 DK |
781 | __free_pages(page, PAGES_PER_SGE_SHIFT); |
782 | ||
783 | sw_buf->page = NULL; | |
784 | sge->addr_hi = 0; | |
785 | sge->addr_lo = 0; | |
786 | } | |
787 | ||
d6214d7a DK |
788 | static inline void bnx2x_add_all_napi(struct bnx2x *bp) |
789 | { | |
790 | int i; | |
523224a3 | 791 | |
0e8d2ec5 MS |
792 | bp->num_napi_queues = bp->num_queues; |
793 | ||
d6214d7a | 794 | /* Add NAPI objects */ |
0e8d2ec5 | 795 | for_each_napi_rx_queue(bp, i) |
d6214d7a DK |
796 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), |
797 | bnx2x_poll, BNX2X_NAPI_WEIGHT); | |
798 | } | |
523224a3 | 799 | |
d6214d7a DK |
800 | static inline void bnx2x_del_all_napi(struct bnx2x *bp) |
801 | { | |
802 | int i; | |
803 | ||
0e8d2ec5 | 804 | for_each_napi_rx_queue(bp, i) |
d6214d7a DK |
805 | netif_napi_del(&bnx2x_fp(bp, i, napi)); |
806 | } | |
523224a3 | 807 | |
0e8d2ec5 MS |
808 | void bnx2x_set_int_mode(struct bnx2x *bp); |
809 | ||
d6214d7a DK |
810 | static inline void bnx2x_disable_msi(struct bnx2x *bp) |
811 | { | |
812 | if (bp->flags & USING_MSIX_FLAG) { | |
813 | pci_disable_msix(bp->pdev); | |
30a5de77 | 814 | bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); |
d6214d7a DK |
815 | } else if (bp->flags & USING_MSI_FLAG) { |
816 | pci_disable_msi(bp->pdev); | |
817 | bp->flags &= ~USING_MSI_FLAG; | |
818 | } | |
819 | } | |
820 | ||
821 | static inline int bnx2x_calc_num_queues(struct bnx2x *bp) | |
822 | { | |
823 | return num_queues ? | |
824 | min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : | |
825 | min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp)); | |
826 | } | |
523224a3 DK |
827 | |
828 | static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) | |
9f6c9258 | 829 | { |
523224a3 | 830 | int i, j; |
9f6c9258 | 831 | |
523224a3 DK |
832 | for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { |
833 | int idx = RX_SGE_CNT * i - 1; | |
834 | ||
835 | for (j = 0; j < 2; j++) { | |
619c5cb6 | 836 | BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); |
523224a3 DK |
837 | idx--; |
838 | } | |
839 | } | |
840 | } | |
841 | ||
842 | static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) | |
843 | { | |
844 | /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ | |
b3637827 | 845 | memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); |
523224a3 DK |
846 | |
847 | /* Clear the two last indices in the page to 1: | |
848 | these are the indices that correspond to the "next" element, | |
849 | hence will never be indicated and should be removed from | |
850 | the calculations. */ | |
851 | bnx2x_clear_sge_mask_next_elems(fp); | |
9f6c9258 DK |
852 | } |
853 | ||
e52fcb24 | 854 | /* note that we are not allocating a new buffer, |
9f6c9258 DK |
855 | * we are just moving one from cons to prod |
856 | * we are not creating a new mapping, | |
857 | * so there is no need to check for dma_mapping_error(). | |
858 | */ | |
e52fcb24 | 859 | static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, |
749a8503 | 860 | u16 cons, u16 prod) |
9f6c9258 | 861 | { |
9f6c9258 DK |
862 | struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; |
863 | struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; | |
864 | struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; | |
865 | struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; | |
866 | ||
9f6c9258 DK |
867 | dma_unmap_addr_set(prod_rx_buf, mapping, |
868 | dma_unmap_addr(cons_rx_buf, mapping)); | |
e52fcb24 | 869 | prod_rx_buf->data = cons_rx_buf->data; |
9f6c9258 DK |
870 | *prod_bd = *cons_bd; |
871 | } | |
f85582f8 | 872 | |
619c5cb6 VZ |
873 | /************************* Init ******************************************/ |
874 | ||
b475d78f YM |
875 | /* returns func by VN for current port */ |
876 | static inline int func_by_vn(struct bnx2x *bp, int vn) | |
877 | { | |
878 | return 2 * vn + BP_PORT(bp); | |
879 | } | |
880 | ||
5d317c6a | 881 | static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash) |
96305234 | 882 | { |
5d317c6a | 883 | return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, config_hash); |
96305234 DK |
884 | } |
885 | ||
619c5cb6 VZ |
886 | /** |
887 | * bnx2x_func_start - init function | |
888 | * | |
889 | * @bp: driver handle | |
890 | * | |
891 | * Must be called before sending CLIENT_SETUP for the first client. | |
892 | */ | |
893 | static inline int bnx2x_func_start(struct bnx2x *bp) | |
894 | { | |
3b603066 | 895 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 VZ |
896 | struct bnx2x_func_start_params *start_params = |
897 | &func_params.params.start; | |
898 | ||
899 | /* Prepare parameters for function state transitions */ | |
900 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
901 | ||
902 | func_params.f_obj = &bp->func_obj; | |
903 | func_params.cmd = BNX2X_F_CMD_START; | |
904 | ||
905 | /* Function parameters */ | |
906 | start_params->mf_mode = bp->mf_mode; | |
907 | start_params->sd_vlan_tag = bp->mf_ov; | |
8d7b0278 AE |
908 | |
909 | if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) | |
6383c0b3 | 910 | start_params->network_cos_mode = STATIC_COS; |
8d7b0278 AE |
911 | else /* CHIP_IS_E1X */ |
912 | start_params->network_cos_mode = FW_WRR; | |
619c5cb6 VZ |
913 | |
914 | return bnx2x_func_state_change(bp, &func_params); | |
915 | } | |
916 | ||
917 | ||
918 | /** | |
919 | * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format | |
920 | * | |
921 | * @fw_hi: pointer to upper part | |
922 | * @fw_mid: pointer to middle part | |
923 | * @fw_lo: pointer to lower part | |
924 | * @mac: pointer to MAC address | |
925 | */ | |
926 | static inline void bnx2x_set_fw_mac_addr(u16 *fw_hi, u16 *fw_mid, u16 *fw_lo, | |
927 | u8 *mac) | |
928 | { | |
929 | ((u8 *)fw_hi)[0] = mac[1]; | |
930 | ((u8 *)fw_hi)[1] = mac[0]; | |
931 | ((u8 *)fw_mid)[0] = mac[3]; | |
932 | ((u8 *)fw_mid)[1] = mac[2]; | |
933 | ((u8 *)fw_lo)[0] = mac[5]; | |
934 | ((u8 *)fw_lo)[1] = mac[4]; | |
935 | } | |
936 | ||
523224a3 DK |
937 | static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, |
938 | struct bnx2x_fastpath *fp, int last) | |
9f6c9258 | 939 | { |
523224a3 | 940 | int i; |
9f6c9258 | 941 | |
b3b83c3f DK |
942 | if (fp->disable_tpa) |
943 | return; | |
944 | ||
523224a3 DK |
945 | for (i = 0; i < last; i++) |
946 | bnx2x_free_rx_sge(bp, fp, i); | |
9f6c9258 DK |
947 | } |
948 | ||
523224a3 | 949 | static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) |
9f6c9258 | 950 | { |
523224a3 | 951 | int i; |
9f6c9258 | 952 | |
523224a3 DK |
953 | for (i = 1; i <= NUM_RX_RINGS; i++) { |
954 | struct eth_rx_bd *rx_bd; | |
955 | ||
956 | rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; | |
957 | rx_bd->addr_hi = | |
958 | cpu_to_le32(U64_HI(fp->rx_desc_mapping + | |
959 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
960 | rx_bd->addr_lo = | |
961 | cpu_to_le32(U64_LO(fp->rx_desc_mapping + | |
962 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
963 | } | |
9f6c9258 DK |
964 | } |
965 | ||
619c5cb6 VZ |
966 | /* Statistics ID are global per chip/path, while Client IDs for E1x are per |
967 | * port. | |
968 | */ | |
969 | static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) | |
970 | { | |
de5c3741 YM |
971 | struct bnx2x *bp = fp->bp; |
972 | if (!CHIP_IS_E1x(bp)) { | |
973 | #ifdef BCM_CNIC | |
974 | /* there are special statistics counters for FCoE 136..140 */ | |
975 | if (IS_FCOE_FP(fp)) | |
976 | return bp->cnic_base_cl_id + (bp->pf_num >> 1); | |
977 | #endif | |
619c5cb6 | 978 | return fp->cl_id; |
de5c3741 YM |
979 | } |
980 | return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; | |
619c5cb6 VZ |
981 | } |
982 | ||
983 | static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, | |
984 | bnx2x_obj_type obj_type) | |
985 | { | |
986 | struct bnx2x *bp = fp->bp; | |
987 | ||
988 | /* Configure classification DBs */ | |
15192a8c BW |
989 | bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id, |
990 | fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), | |
619c5cb6 VZ |
991 | bnx2x_sp_mapping(bp, mac_rdata), |
992 | BNX2X_FILTER_MAC_PENDING, | |
993 | &bp->sp_state, obj_type, | |
994 | &bp->macs_pool); | |
995 | } | |
996 | ||
997 | /** | |
998 | * bnx2x_get_path_func_num - get number of active functions | |
999 | * | |
1000 | * @bp: driver handle | |
1001 | * | |
1002 | * Calculates the number of active (not hidden) functions on the | |
1003 | * current path. | |
1004 | */ | |
1005 | static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) | |
1006 | { | |
1007 | u8 func_num = 0, i; | |
1008 | ||
1009 | /* 57710 has only one function per-port */ | |
1010 | if (CHIP_IS_E1(bp)) | |
1011 | return 1; | |
1012 | ||
1013 | /* Calculate a number of functions enabled on the current | |
1014 | * PATH/PORT. | |
1015 | */ | |
1016 | if (CHIP_REV_IS_SLOW(bp)) { | |
1017 | if (IS_MF(bp)) | |
1018 | func_num = 4; | |
1019 | else | |
1020 | func_num = 2; | |
1021 | } else { | |
1022 | for (i = 0; i < E1H_FUNC_MAX / 2; i++) { | |
1023 | u32 func_config = | |
1024 | MF_CFG_RD(bp, | |
1025 | func_mf_config[BP_PORT(bp) + 2 * i]. | |
1026 | config); | |
1027 | func_num += | |
1028 | ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); | |
1029 | } | |
1030 | } | |
1031 | ||
1032 | WARN_ON(!func_num); | |
1033 | ||
1034 | return func_num; | |
1035 | } | |
1036 | ||
1037 | static inline void bnx2x_init_bp_objs(struct bnx2x *bp) | |
1038 | { | |
1039 | /* RX_MODE controlling object */ | |
1040 | bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); | |
1041 | ||
1042 | /* multicast configuration controlling object */ | |
1043 | bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, | |
1044 | BP_FUNC(bp), BP_FUNC(bp), | |
1045 | bnx2x_sp(bp, mcast_rdata), | |
1046 | bnx2x_sp_mapping(bp, mcast_rdata), | |
1047 | BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, | |
1048 | BNX2X_OBJ_TYPE_RX); | |
1049 | ||
1050 | /* Setup CAM credit pools */ | |
1051 | bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), | |
1052 | bnx2x_get_path_func_num(bp)); | |
1053 | ||
1054 | /* RSS configuration object */ | |
1055 | bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, | |
1056 | bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), | |
1057 | bnx2x_sp(bp, rss_rdata), | |
1058 | bnx2x_sp_mapping(bp, rss_rdata), | |
1059 | BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, | |
1060 | BNX2X_OBJ_TYPE_RX); | |
1061 | } | |
1062 | ||
1063 | static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) | |
1064 | { | |
1065 | if (CHIP_IS_E1x(fp->bp)) | |
1066 | return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; | |
1067 | else | |
1068 | return fp->cl_id; | |
1069 | } | |
1070 | ||
1071 | static inline u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) | |
1072 | { | |
1073 | struct bnx2x *bp = fp->bp; | |
1074 | ||
1075 | if (!CHIP_IS_E1x(bp)) | |
1076 | return USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); | |
1077 | else | |
1078 | return USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); | |
1079 | } | |
1080 | ||
6383c0b3 | 1081 | static inline void bnx2x_init_txdata(struct bnx2x *bp, |
65565884 MS |
1082 | struct bnx2x_fp_txdata *txdata, u32 cid, |
1083 | int txq_index, __le16 *tx_cons_sb, | |
1084 | struct bnx2x_fastpath *fp) | |
6383c0b3 AE |
1085 | { |
1086 | txdata->cid = cid; | |
1087 | txdata->txq_index = txq_index; | |
1088 | txdata->tx_cons_sb = tx_cons_sb; | |
65565884 | 1089 | txdata->parent_fp = fp; |
6383c0b3 | 1090 | |
51c1a580 | 1091 | DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", |
6383c0b3 AE |
1092 | txdata->cid, txdata->txq_index); |
1093 | } | |
619c5cb6 | 1094 | |
ec6ba945 | 1095 | #ifdef BCM_CNIC |
619c5cb6 VZ |
1096 | static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) |
1097 | { | |
1098 | return bp->cnic_base_cl_id + cl_idx + | |
134d0f97 | 1099 | (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; |
619c5cb6 VZ |
1100 | } |
1101 | ||
1102 | static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) | |
1103 | { | |
1104 | ||
1105 | /* the 'first' id is allocated for the cnic */ | |
1106 | return bp->base_fw_ndsb; | |
1107 | } | |
1108 | ||
1109 | static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) | |
1110 | { | |
1111 | return bp->igu_base_sb; | |
1112 | } | |
1113 | ||
1114 | ||
ec6ba945 VZ |
1115 | static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) |
1116 | { | |
619c5cb6 VZ |
1117 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); |
1118 | unsigned long q_type = 0; | |
1119 | ||
f233cafe | 1120 | bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); |
619c5cb6 VZ |
1121 | bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, |
1122 | BNX2X_FCOE_ETH_CL_ID_IDX); | |
37ae41a9 | 1123 | bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); |
ec6ba945 VZ |
1124 | bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; |
1125 | bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; | |
ec6ba945 | 1126 | bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; |
65565884 MS |
1127 | bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), |
1128 | fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, | |
1129 | fp); | |
6383c0b3 | 1130 | |
51c1a580 | 1131 | DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); |
6383c0b3 | 1132 | |
ec6ba945 | 1133 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 | 1134 | bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); |
ec6ba945 | 1135 | /* init shortcut */ |
619c5cb6 VZ |
1136 | bnx2x_fcoe(bp, ustorm_rx_prods_offset) = |
1137 | bnx2x_rx_ustorm_prods_offset(fp); | |
1138 | ||
1139 | /* Configure Queue State object */ | |
1140 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
1141 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
1142 | |
1143 | /* No multi-CoS for FCoE L2 client */ | |
1144 | BUG_ON(fp->max_cos != 1); | |
1145 | ||
15192a8c BW |
1146 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, |
1147 | &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6383c0b3 | 1148 | bnx2x_sp_mapping(bp, q_rdata), q_type); |
619c5cb6 | 1149 | |
51c1a580 MS |
1150 | DP(NETIF_MSG_IFUP, |
1151 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", | |
619c5cb6 VZ |
1152 | fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, |
1153 | fp->igu_sb_id); | |
ec6ba945 VZ |
1154 | } |
1155 | #endif | |
523224a3 | 1156 | |
619c5cb6 | 1157 | static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, |
6383c0b3 | 1158 | struct bnx2x_fp_txdata *txdata) |
619c5cb6 VZ |
1159 | { |
1160 | int cnt = 1000; | |
1161 | ||
6383c0b3 | 1162 | while (bnx2x_has_tx_work_unload(txdata)) { |
619c5cb6 | 1163 | if (!cnt) { |
51c1a580 | 1164 | BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", |
6383c0b3 AE |
1165 | txdata->txq_index, txdata->tx_pkt_prod, |
1166 | txdata->tx_pkt_cons); | |
619c5cb6 VZ |
1167 | #ifdef BNX2X_STOP_ON_ERROR |
1168 | bnx2x_panic(); | |
1169 | return -EBUSY; | |
1170 | #else | |
1171 | break; | |
1172 | #endif | |
1173 | } | |
1174 | cnt--; | |
1175 | usleep_range(1000, 1000); | |
1176 | } | |
1177 | ||
1178 | return 0; | |
1179 | } | |
1180 | ||
1ac9e428 YR |
1181 | int bnx2x_get_link_cfg_idx(struct bnx2x *bp); |
1182 | ||
523224a3 DK |
1183 | static inline void __storm_memset_struct(struct bnx2x *bp, |
1184 | u32 addr, size_t size, u32 *data) | |
1185 | { | |
1186 | int i; | |
1187 | for (i = 0; i < size/4; i++) | |
1188 | REG_WR(bp, addr + (i * 4), data[i]); | |
1189 | } | |
1190 | ||
619c5cb6 VZ |
1191 | /** |
1192 | * bnx2x_wait_sp_comp - wait for the outstanding SP commands. | |
1193 | * | |
1194 | * @bp: driver handle | |
1195 | * @mask: bits that need to be cleared | |
1196 | */ | |
1197 | static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) | |
1198 | { | |
1199 | int tout = 5000; /* Wait for 5 secs tops */ | |
1200 | ||
1201 | while (tout--) { | |
1202 | smp_mb(); | |
1203 | netif_addr_lock_bh(bp->dev); | |
1204 | if (!(bp->sp_state & mask)) { | |
1205 | netif_addr_unlock_bh(bp->dev); | |
1206 | return true; | |
1207 | } | |
1208 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1209 | |
619c5cb6 VZ |
1210 | usleep_range(1000, 1000); |
1211 | } | |
1212 | ||
1213 | smp_mb(); | |
1214 | ||
1215 | netif_addr_lock_bh(bp->dev); | |
1216 | if (bp->sp_state & mask) { | |
51c1a580 MS |
1217 | BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n", |
1218 | bp->sp_state, mask); | |
619c5cb6 VZ |
1219 | netif_addr_unlock_bh(bp->dev); |
1220 | return false; | |
1221 | } | |
1222 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1223 | |
619c5cb6 | 1224 | return true; |
523224a3 | 1225 | } |
f85582f8 | 1226 | |
619c5cb6 VZ |
1227 | /** |
1228 | * bnx2x_set_ctx_validation - set CDU context validation values | |
1229 | * | |
1230 | * @bp: driver handle | |
1231 | * @cxt: context of the connection on the host memory | |
1232 | * @cid: SW CID of the connection to be configured | |
1233 | */ | |
1234 | void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, | |
1235 | u32 cid); | |
1236 | ||
1237 | void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, | |
1238 | u8 sb_index, u8 disable, u16 usec); | |
9f6c9258 DK |
1239 | void bnx2x_acquire_phy_lock(struct bnx2x *bp); |
1240 | void bnx2x_release_phy_lock(struct bnx2x *bp); | |
1241 | ||
faa6fcbb | 1242 | /** |
e8920674 | 1243 | * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. |
faa6fcbb | 1244 | * |
e8920674 DK |
1245 | * @bp: driver handle |
1246 | * @mf_cfg: MF configuration | |
faa6fcbb | 1247 | * |
faa6fcbb DK |
1248 | */ |
1249 | static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) | |
1250 | { | |
1251 | u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> | |
1252 | FUNC_MF_CFG_MAX_BW_SHIFT; | |
1253 | if (!max_cfg) { | |
51c1a580 | 1254 | DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, |
96b0accb | 1255 | "Max BW configured to 0 - using 100 instead\n"); |
faa6fcbb DK |
1256 | max_cfg = 100; |
1257 | } | |
1258 | return max_cfg; | |
1259 | } | |
1260 | ||
621b4d66 DK |
1261 | /* checks if HW supports GRO for given MTU */ |
1262 | static inline bool bnx2x_mtu_allows_gro(int mtu) | |
1263 | { | |
1264 | /* gro frags per page */ | |
1265 | int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); | |
1266 | ||
1267 | /* | |
1268 | * 1. number of frags should not grow above MAX_SKB_FRAGS | |
1269 | * 2. frag must fit the page | |
1270 | */ | |
1271 | return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; | |
1272 | } | |
3b603066 | 1273 | #ifdef BCM_CNIC |
b306f5ed DK |
1274 | /** |
1275 | * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. | |
1276 | * | |
1277 | * @bp: driver handle | |
1278 | * | |
1279 | */ | |
1280 | void bnx2x_get_iscsi_info(struct bnx2x *bp); | |
3b603066 | 1281 | #endif |
00253a8c DK |
1282 | |
1283 | /** | |
1284 | * bnx2x_link_sync_notify - send notification to other functions. | |
1285 | * | |
1286 | * @bp: driver handle | |
1287 | * | |
1288 | */ | |
1289 | static inline void bnx2x_link_sync_notify(struct bnx2x *bp) | |
1290 | { | |
1291 | int func; | |
1292 | int vn; | |
1293 | ||
1294 | /* Set the attention towards other drivers on the same port */ | |
1295 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
1296 | if (vn == BP_VN(bp)) | |
1297 | continue; | |
1298 | ||
1299 | func = func_by_vn(bp, vn); | |
1300 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + | |
1301 | (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); | |
1302 | } | |
1303 | } | |
1304 | ||
1305 | /** | |
1306 | * bnx2x_update_drv_flags - update flags in shmem | |
1307 | * | |
1308 | * @bp: driver handle | |
1309 | * @flags: flags to update | |
1310 | * @set: set or clear | |
1311 | * | |
1312 | */ | |
1313 | static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) | |
1314 | { | |
1315 | if (SHMEM2_HAS(bp, drv_flags)) { | |
1316 | u32 drv_flags; | |
f16da43b | 1317 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); |
00253a8c DK |
1318 | drv_flags = SHMEM2_RD(bp, drv_flags); |
1319 | ||
1320 | if (set) | |
1321 | SET_FLAGS(drv_flags, flags); | |
1322 | else | |
1323 | RESET_FLAGS(drv_flags, flags); | |
1324 | ||
1325 | SHMEM2_WR(bp, drv_flags, drv_flags); | |
51c1a580 | 1326 | DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); |
f16da43b | 1327 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); |
00253a8c DK |
1328 | } |
1329 | } | |
1330 | ||
614c76df DK |
1331 | static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) |
1332 | { | |
1333 | if (is_valid_ether_addr(addr)) | |
1334 | return true; | |
1335 | #ifdef BCM_CNIC | |
a3348722 BW |
1336 | if (is_zero_ether_addr(addr) && |
1337 | (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) | |
614c76df DK |
1338 | return true; |
1339 | #endif | |
1340 | return false; | |
1341 | } | |
1342 | ||
9f6c9258 | 1343 | #endif /* BNX2X_CMN_H */ |