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9f6c9258 DK |
1 | /* bnx2x_cmn.h: Broadcom Everest network driver. |
2 | * | |
85b26ea1 | 3 | * Copyright (c) 2007-2012 Broadcom Corporation |
9f6c9258 DK |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> | |
10 | * Written by: Eliezer Tamir | |
11 | * Based on code from Michael Chan's bnx2 driver | |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
13 | * Slowpath and fastpath rework by Vladislav Zolotarov | |
14 | * Statistics and Link management by Yitchak Gertner | |
15 | * | |
16 | */ | |
17 | #ifndef BNX2X_CMN_H | |
18 | #define BNX2X_CMN_H | |
19 | ||
20 | #include <linux/types.h> | |
619c5cb6 | 21 | #include <linux/pci.h> |
9f6c9258 | 22 | #include <linux/netdevice.h> |
614c76df | 23 | #include <linux/etherdevice.h> |
9f6c9258 DK |
24 | |
25 | ||
26 | #include "bnx2x.h" | |
27 | ||
619c5cb6 VZ |
28 | /* This is used as a replacement for an MCP if it's not present */ |
29 | extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ | |
30 | ||
d6214d7a | 31 | extern int num_queues; |
9f6c9258 | 32 | |
b3b83c3f DK |
33 | /************************ Macros ********************************/ |
34 | #define BNX2X_PCI_FREE(x, y, size) \ | |
35 | do { \ | |
36 | if (x) { \ | |
37 | dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ | |
38 | x = NULL; \ | |
39 | y = 0; \ | |
40 | } \ | |
41 | } while (0) | |
42 | ||
43 | #define BNX2X_FREE(x) \ | |
44 | do { \ | |
45 | if (x) { \ | |
46 | kfree((void *)x); \ | |
47 | x = NULL; \ | |
48 | } \ | |
49 | } while (0) | |
50 | ||
51 | #define BNX2X_PCI_ALLOC(x, y, size) \ | |
52 | do { \ | |
53 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ | |
54 | if (x == NULL) \ | |
55 | goto alloc_mem_err; \ | |
56 | memset((void *)x, 0, size); \ | |
57 | } while (0) | |
58 | ||
59 | #define BNX2X_ALLOC(x, size) \ | |
60 | do { \ | |
61 | x = kzalloc(size, GFP_KERNEL); \ | |
62 | if (x == NULL) \ | |
63 | goto alloc_mem_err; \ | |
64 | } while (0) | |
65 | ||
9f6c9258 DK |
66 | /*********************** Interfaces **************************** |
67 | * Functions that need to be implemented by each driver version | |
68 | */ | |
619c5cb6 VZ |
69 | /* Init */ |
70 | ||
71 | /** | |
72 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
73 | * | |
74 | * @bp: driver handle | |
75 | * @unload_mode: requested function's unload mode | |
76 | * | |
77 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
78 | */ | |
79 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); | |
80 | ||
81 | /** | |
82 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
83 | * | |
84 | * @bp: driver handle | |
85 | */ | |
86 | void bnx2x_send_unload_done(struct bnx2x *bp); | |
87 | ||
88 | /** | |
96305234 | 89 | * bnx2x_config_rss_pf - configure RSS parameters in a PF. |
619c5cb6 VZ |
90 | * |
91 | * @bp: driver handle | |
96305234 | 92 | * @rss_obj RSS object to use |
619c5cb6 VZ |
93 | * @ind_table: indirection table to configure |
94 | * @config_hash: re-configure RSS hash keys configuration | |
95 | */ | |
96305234 | 96 | int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, |
5d317c6a | 97 | bool config_hash); |
619c5cb6 VZ |
98 | |
99 | /** | |
100 | * bnx2x__init_func_obj - init function object | |
101 | * | |
102 | * @bp: driver handle | |
103 | * | |
104 | * Initializes the Function Object with the appropriate | |
105 | * parameters which include a function slow path driver | |
106 | * interface. | |
107 | */ | |
108 | void bnx2x__init_func_obj(struct bnx2x *bp); | |
109 | ||
110 | /** | |
111 | * bnx2x_setup_queue - setup eth queue. | |
112 | * | |
113 | * @bp: driver handle | |
114 | * @fp: pointer to the fastpath structure | |
115 | * @leading: boolean | |
116 | * | |
117 | */ | |
118 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
119 | bool leading); | |
120 | ||
121 | /** | |
122 | * bnx2x_setup_leading - bring up a leading eth queue. | |
123 | * | |
124 | * @bp: driver handle | |
125 | */ | |
126 | int bnx2x_setup_leading(struct bnx2x *bp); | |
127 | ||
128 | /** | |
129 | * bnx2x_fw_command - send the MCP a request | |
130 | * | |
131 | * @bp: driver handle | |
132 | * @command: request | |
133 | * @param: request's parameter | |
134 | * | |
135 | * block until there is a reply | |
136 | */ | |
137 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); | |
9f6c9258 DK |
138 | |
139 | /** | |
e8920674 | 140 | * bnx2x_initial_phy_init - initialize link parameters structure variables. |
9f6c9258 | 141 | * |
e8920674 DK |
142 | * @bp: driver handle |
143 | * @load_mode: current mode | |
9f6c9258 DK |
144 | */ |
145 | u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); | |
146 | ||
147 | /** | |
e8920674 | 148 | * bnx2x_link_set - configure hw according to link parameters structure. |
9f6c9258 | 149 | * |
e8920674 | 150 | * @bp: driver handle |
9f6c9258 DK |
151 | */ |
152 | void bnx2x_link_set(struct bnx2x *bp); | |
153 | ||
154 | /** | |
e8920674 | 155 | * bnx2x_link_test - query link status. |
9f6c9258 | 156 | * |
e8920674 DK |
157 | * @bp: driver handle |
158 | * @is_serdes: bool | |
9f6c9258 | 159 | * |
e8920674 | 160 | * Returns 0 if link is UP. |
9f6c9258 | 161 | */ |
a22f0788 | 162 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); |
9f6c9258 | 163 | |
619c5cb6 VZ |
164 | /** |
165 | * bnx2x_drv_pulse - write driver pulse to shmem | |
166 | * | |
167 | * @bp: driver handle | |
168 | * | |
169 | * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox | |
170 | * in the shmem. | |
171 | */ | |
172 | void bnx2x_drv_pulse(struct bnx2x *bp); | |
173 | ||
174 | /** | |
175 | * bnx2x_igu_ack_sb - update IGU with current SB value | |
176 | * | |
177 | * @bp: driver handle | |
178 | * @igu_sb_id: SB id | |
179 | * @segment: SB segment | |
180 | * @index: SB index | |
181 | * @op: SB operation | |
182 | * @update: is HW update required | |
183 | */ | |
184 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, | |
185 | u16 index, u8 op, u8 update); | |
186 | ||
c9ee9206 VZ |
187 | /* Disable transactions from chip to host */ |
188 | void bnx2x_pf_disable(struct bnx2x *bp); | |
189 | ||
9f6c9258 | 190 | /** |
e8920674 | 191 | * bnx2x__link_status_update - handles link status change. |
9f6c9258 | 192 | * |
e8920674 | 193 | * @bp: driver handle |
9f6c9258 DK |
194 | */ |
195 | void bnx2x__link_status_update(struct bnx2x *bp); | |
196 | ||
f85582f8 | 197 | /** |
e8920674 | 198 | * bnx2x_link_report - report link status to upper layer. |
f85582f8 | 199 | * |
e8920674 | 200 | * @bp: driver handle |
f85582f8 DK |
201 | */ |
202 | void bnx2x_link_report(struct bnx2x *bp); | |
203 | ||
2ae17f66 VZ |
204 | /* None-atomic version of bnx2x_link_report() */ |
205 | void __bnx2x_link_report(struct bnx2x *bp); | |
206 | ||
0793f83f | 207 | /** |
e8920674 | 208 | * bnx2x_get_mf_speed - calculate MF speed. |
0793f83f | 209 | * |
e8920674 | 210 | * @bp: driver handle |
0793f83f | 211 | * |
e8920674 | 212 | * Takes into account current linespeed and MF configuration. |
0793f83f DK |
213 | */ |
214 | u16 bnx2x_get_mf_speed(struct bnx2x *bp); | |
215 | ||
9f6c9258 | 216 | /** |
e8920674 | 217 | * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler |
9f6c9258 | 218 | * |
e8920674 DK |
219 | * @irq: irq number |
220 | * @dev_instance: private instance | |
9f6c9258 DK |
221 | */ |
222 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); | |
223 | ||
224 | /** | |
e8920674 | 225 | * bnx2x_interrupt - non MSI-X interrupt handler |
9f6c9258 | 226 | * |
e8920674 DK |
227 | * @irq: irq number |
228 | * @dev_instance: private instance | |
9f6c9258 DK |
229 | */ |
230 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); | |
231 | #ifdef BCM_CNIC | |
232 | ||
233 | /** | |
e8920674 | 234 | * bnx2x_cnic_notify - send command to cnic driver |
9f6c9258 | 235 | * |
e8920674 DK |
236 | * @bp: driver handle |
237 | * @cmd: command | |
9f6c9258 DK |
238 | */ |
239 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); | |
240 | ||
241 | /** | |
e8920674 | 242 | * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information |
9f6c9258 | 243 | * |
e8920674 | 244 | * @bp: driver handle |
9f6c9258 DK |
245 | */ |
246 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); | |
37ae41a9 MS |
247 | |
248 | /** | |
249 | * bnx2x_setup_cnic_info - provides cnic with updated info | |
250 | * | |
251 | * @bp: driver handle | |
252 | */ | |
253 | void bnx2x_setup_cnic_info(struct bnx2x *bp); | |
254 | ||
9f6c9258 DK |
255 | #endif |
256 | ||
257 | /** | |
e8920674 | 258 | * bnx2x_int_enable - enable HW interrupts. |
9f6c9258 | 259 | * |
e8920674 | 260 | * @bp: driver handle |
9f6c9258 DK |
261 | */ |
262 | void bnx2x_int_enable(struct bnx2x *bp); | |
263 | ||
264 | /** | |
e8920674 DK |
265 | * bnx2x_int_disable_sync - disable interrupts. |
266 | * | |
267 | * @bp: driver handle | |
268 | * @disable_hw: true, disable HW interrupts. | |
9f6c9258 | 269 | * |
e8920674 DK |
270 | * This function ensures that there are no |
271 | * ISRs or SP DPCs (sp_task) are running after it returns. | |
9f6c9258 DK |
272 | */ |
273 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); | |
274 | ||
9f6c9258 | 275 | /** |
e8920674 DK |
276 | * bnx2x_nic_init - init driver internals. |
277 | * | |
278 | * @bp: driver handle | |
279 | * @load_code: COMMON, PORT or FUNCTION | |
280 | * | |
281 | * Initializes: | |
9f6c9258 DK |
282 | * - rings |
283 | * - status blocks | |
284 | * - etc. | |
9f6c9258 DK |
285 | */ |
286 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code); | |
287 | ||
288 | /** | |
e8920674 | 289 | * bnx2x_alloc_mem - allocate driver's memory. |
9f6c9258 | 290 | * |
e8920674 | 291 | * @bp: driver handle |
9f6c9258 DK |
292 | */ |
293 | int bnx2x_alloc_mem(struct bnx2x *bp); | |
294 | ||
295 | /** | |
e8920674 | 296 | * bnx2x_free_mem - release driver's memory. |
9f6c9258 | 297 | * |
e8920674 | 298 | * @bp: driver handle |
9f6c9258 DK |
299 | */ |
300 | void bnx2x_free_mem(struct bnx2x *bp); | |
301 | ||
9f6c9258 | 302 | /** |
e8920674 | 303 | * bnx2x_set_num_queues - set number of queues according to mode. |
9f6c9258 | 304 | * |
e8920674 | 305 | * @bp: driver handle |
9f6c9258 | 306 | */ |
d6214d7a | 307 | void bnx2x_set_num_queues(struct bnx2x *bp); |
9f6c9258 DK |
308 | |
309 | /** | |
e8920674 DK |
310 | * bnx2x_chip_cleanup - cleanup chip internals. |
311 | * | |
312 | * @bp: driver handle | |
313 | * @unload_mode: COMMON, PORT, FUNCTION | |
314 | * | |
9f6c9258 | 315 | * - Cleanup MAC configuration. |
e8920674 | 316 | * - Closes clients. |
9f6c9258 | 317 | * - etc. |
9f6c9258 DK |
318 | */ |
319 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode); | |
320 | ||
321 | /** | |
e8920674 | 322 | * bnx2x_acquire_hw_lock - acquire HW lock. |
9f6c9258 | 323 | * |
e8920674 DK |
324 | * @bp: driver handle |
325 | * @resource: resource bit which was locked | |
9f6c9258 DK |
326 | */ |
327 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); | |
328 | ||
329 | /** | |
e8920674 | 330 | * bnx2x_release_hw_lock - release HW lock. |
9f6c9258 | 331 | * |
e8920674 DK |
332 | * @bp: driver handle |
333 | * @resource: resource bit which was locked | |
9f6c9258 DK |
334 | */ |
335 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); | |
336 | ||
c9ee9206 VZ |
337 | /** |
338 | * bnx2x_release_leader_lock - release recovery leader lock | |
339 | * | |
340 | * @bp: driver handle | |
341 | */ | |
342 | int bnx2x_release_leader_lock(struct bnx2x *bp); | |
343 | ||
9f6c9258 | 344 | /** |
e8920674 DK |
345 | * bnx2x_set_eth_mac - configure eth MAC address in the HW |
346 | * | |
347 | * @bp: driver handle | |
348 | * @set: set or clear | |
9f6c9258 | 349 | * |
e8920674 | 350 | * Configures according to the value in netdev->dev_addr. |
9f6c9258 | 351 | */ |
619c5cb6 | 352 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); |
9f6c9258 | 353 | |
ec6ba945 | 354 | /** |
619c5cb6 | 355 | * bnx2x_set_rx_mode - set MAC filtering configurations. |
ec6ba945 | 356 | * |
619c5cb6 | 357 | * @dev: netdevice |
ec6ba945 | 358 | * |
619c5cb6 VZ |
359 | * called with netif_tx_lock from dev_mcast.c |
360 | * If bp->state is OPEN, should be called with | |
361 | * netif_addr_lock_bh() | |
ec6ba945 | 362 | */ |
619c5cb6 | 363 | void bnx2x_set_rx_mode(struct net_device *dev); |
ec6ba945 VZ |
364 | |
365 | /** | |
619c5cb6 | 366 | * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. |
ec6ba945 | 367 | * |
e8920674 | 368 | * @bp: driver handle |
619c5cb6 VZ |
369 | * |
370 | * If bp->state is OPEN, should be called with | |
371 | * netif_addr_lock_bh(). | |
ec6ba945 | 372 | */ |
619c5cb6 | 373 | void bnx2x_set_storm_rx_mode(struct bnx2x *bp); |
ec6ba945 | 374 | |
9f6c9258 | 375 | /** |
619c5cb6 | 376 | * bnx2x_set_q_rx_mode - configures rx_mode for a single queue. |
9f6c9258 | 377 | * |
619c5cb6 VZ |
378 | * @bp: driver handle |
379 | * @cl_id: client id | |
380 | * @rx_mode_flags: rx mode configuration | |
381 | * @rx_accept_flags: rx accept configuration | |
382 | * @tx_accept_flags: tx accept configuration (tx switch) | |
383 | * @ramrod_flags: ramrod configuration | |
9f6c9258 | 384 | */ |
619c5cb6 VZ |
385 | void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, |
386 | unsigned long rx_mode_flags, | |
387 | unsigned long rx_accept_flags, | |
388 | unsigned long tx_accept_flags, | |
389 | unsigned long ramrod_flags); | |
9f6c9258 | 390 | |
9f6c9258 | 391 | /* Parity errors related */ |
889b9af3 AE |
392 | void bnx2x_set_pf_load(struct bnx2x *bp); |
393 | bool bnx2x_clear_pf_load(struct bnx2x *bp); | |
c9ee9206 VZ |
394 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); |
395 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); | |
396 | void bnx2x_set_reset_in_progress(struct bnx2x *bp); | |
397 | void bnx2x_set_reset_global(struct bnx2x *bp); | |
9f6c9258 DK |
398 | void bnx2x_disable_close_the_gate(struct bnx2x *bp); |
399 | ||
9f6c9258 | 400 | /** |
e8920674 | 401 | * bnx2x_sp_event - handle ramrods completion. |
9f6c9258 | 402 | * |
e8920674 DK |
403 | * @fp: fastpath handle for the event |
404 | * @rr_cqe: eth_rx_cqe | |
9f6c9258 | 405 | */ |
f85582f8 | 406 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); |
9f6c9258 | 407 | |
523224a3 | 408 | /** |
e8920674 | 409 | * bnx2x_ilt_set_info - prepare ILT configurations. |
523224a3 | 410 | * |
e8920674 | 411 | * @bp: driver handle |
523224a3 DK |
412 | */ |
413 | void bnx2x_ilt_set_info(struct bnx2x *bp); | |
9f6c9258 | 414 | |
e4901dde | 415 | /** |
e8920674 | 416 | * bnx2x_dcbx_init - initialize dcbx protocol. |
e4901dde | 417 | * |
e8920674 | 418 | * @bp: driver handle |
e4901dde VZ |
419 | */ |
420 | void bnx2x_dcbx_init(struct bnx2x *bp); | |
421 | ||
f85582f8 | 422 | /** |
e8920674 | 423 | * bnx2x_set_power_state - set power state to the requested value. |
f85582f8 | 424 | * |
e8920674 DK |
425 | * @bp: driver handle |
426 | * @state: required state D0 or D3hot | |
f85582f8 | 427 | * |
e8920674 | 428 | * Currently only D0 and D3hot are supported. |
f85582f8 DK |
429 | */ |
430 | int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); | |
431 | ||
e3835b99 | 432 | /** |
e8920674 | 433 | * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. |
e3835b99 | 434 | * |
e8920674 DK |
435 | * @bp: driver handle |
436 | * @value: new value | |
e3835b99 DK |
437 | */ |
438 | void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); | |
619c5cb6 VZ |
439 | /* Error handling */ |
440 | void bnx2x_panic_dump(struct bnx2x *bp); | |
e3835b99 | 441 | |
7a25cc73 DK |
442 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); |
443 | ||
452427b0 YM |
444 | /* validate currect fw is loaded */ |
445 | bool bnx2x_test_firmware_version(struct bnx2x *bp, bool is_err); | |
446 | ||
f85582f8 DK |
447 | /* dev_close main block */ |
448 | int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode); | |
449 | ||
450 | /* dev_open main block */ | |
451 | int bnx2x_nic_load(struct bnx2x *bp, int load_mode); | |
452 | ||
453 | /* hard_xmit callback */ | |
454 | netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
455 | ||
6383c0b3 AE |
456 | /* setup_tc callback */ |
457 | int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); | |
458 | ||
8307fa3e VZ |
459 | /* select_queue callback */ |
460 | u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); | |
461 | ||
a9fccec7 DK |
462 | /* reload helper */ |
463 | int bnx2x_reload_if_running(struct net_device *dev); | |
464 | ||
f85582f8 DK |
465 | int bnx2x_change_mac_addr(struct net_device *dev, void *p); |
466 | ||
467 | /* NAPI poll Rx part */ | |
468 | int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); | |
469 | ||
619c5cb6 VZ |
470 | void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
471 | u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod); | |
472 | ||
f85582f8 | 473 | /* NAPI poll Tx part */ |
6383c0b3 | 474 | int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); |
f85582f8 DK |
475 | |
476 | /* suspend/resume callbacks */ | |
477 | int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); | |
478 | int bnx2x_resume(struct pci_dev *pdev); | |
479 | ||
480 | /* Release IRQ vectors */ | |
481 | void bnx2x_free_irq(struct bnx2x *bp); | |
482 | ||
b3b83c3f DK |
483 | void bnx2x_free_fp_mem(struct bnx2x *bp); |
484 | int bnx2x_alloc_fp_mem(struct bnx2x *bp); | |
f85582f8 DK |
485 | void bnx2x_init_rx_rings(struct bnx2x *bp); |
486 | void bnx2x_free_skbs(struct bnx2x *bp); | |
487 | void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); | |
488 | void bnx2x_netif_start(struct bnx2x *bp); | |
489 | ||
d6214d7a | 490 | /** |
e8920674 | 491 | * bnx2x_enable_msix - set msix configuration. |
d6214d7a | 492 | * |
e8920674 | 493 | * @bp: driver handle |
d6214d7a | 494 | * |
e8920674 DK |
495 | * fills msix_table, requests vectors, updates num_queues |
496 | * according to number of available vectors. | |
d6214d7a | 497 | */ |
30a5de77 | 498 | int __devinit bnx2x_enable_msix(struct bnx2x *bp); |
d6214d7a DK |
499 | |
500 | /** | |
e8920674 | 501 | * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly |
d6214d7a | 502 | * |
e8920674 | 503 | * @bp: driver handle |
d6214d7a DK |
504 | */ |
505 | int bnx2x_enable_msi(struct bnx2x *bp); | |
506 | ||
d6214d7a | 507 | /** |
e8920674 | 508 | * bnx2x_poll - NAPI callback |
d6214d7a | 509 | * |
e8920674 DK |
510 | * @napi: napi structure |
511 | * @budget: | |
d6214d7a | 512 | * |
d6214d7a DK |
513 | */ |
514 | int bnx2x_poll(struct napi_struct *napi, int budget); | |
f85582f8 DK |
515 | |
516 | /** | |
e8920674 | 517 | * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure |
f85582f8 | 518 | * |
e8920674 | 519 | * @bp: driver handle |
f85582f8 DK |
520 | */ |
521 | int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp); | |
e8920674 DK |
522 | |
523 | /** | |
524 | * bnx2x_free_mem_bp - release memories outsize main driver structure | |
525 | * | |
526 | * @bp: driver handle | |
527 | */ | |
f85582f8 DK |
528 | void bnx2x_free_mem_bp(struct bnx2x *bp); |
529 | ||
530 | /** | |
e8920674 | 531 | * bnx2x_change_mtu - change mtu netdev callback |
f85582f8 | 532 | * |
e8920674 DK |
533 | * @dev: net device |
534 | * @new_mtu: requested mtu | |
f85582f8 | 535 | * |
f85582f8 DK |
536 | */ |
537 | int bnx2x_change_mtu(struct net_device *dev, int new_mtu); | |
538 | ||
3857e3ee | 539 | #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) |
bf61ee14 VZ |
540 | /** |
541 | * bnx2x_fcoe_get_wwn - return the requested WWN value for this port | |
542 | * | |
543 | * @dev: net_device | |
544 | * @wwn: output buffer | |
545 | * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) | |
546 | * | |
547 | */ | |
548 | int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); | |
549 | #endif | |
621b4d66 | 550 | |
c8f44aff | 551 | netdev_features_t bnx2x_fix_features(struct net_device *dev, |
621b4d66 | 552 | netdev_features_t features); |
c8f44aff | 553 | int bnx2x_set_features(struct net_device *dev, netdev_features_t features); |
66371c44 | 554 | |
f85582f8 | 555 | /** |
e8920674 | 556 | * bnx2x_tx_timeout - tx timeout netdev callback |
f85582f8 | 557 | * |
e8920674 | 558 | * @dev: net device |
f85582f8 DK |
559 | */ |
560 | void bnx2x_tx_timeout(struct net_device *dev); | |
561 | ||
619c5cb6 VZ |
562 | /*********************** Inlines **********************************/ |
563 | /*********************** Fast path ********************************/ | |
9f6c9258 DK |
564 | static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) |
565 | { | |
9f6c9258 | 566 | barrier(); /* status block is written to by the chip */ |
523224a3 | 567 | fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; |
9f6c9258 DK |
568 | } |
569 | ||
619c5cb6 VZ |
570 | static inline void bnx2x_update_rx_prod_gen(struct bnx2x *bp, |
571 | struct bnx2x_fastpath *fp, u16 bd_prod, | |
572 | u16 rx_comp_prod, u16 rx_sge_prod, u32 start) | |
9f6c9258 DK |
573 | { |
574 | struct ustorm_eth_rx_producers rx_prods = {0}; | |
619c5cb6 | 575 | u32 i; |
9f6c9258 DK |
576 | |
577 | /* Update producers */ | |
578 | rx_prods.bd_prod = bd_prod; | |
579 | rx_prods.cqe_prod = rx_comp_prod; | |
580 | rx_prods.sge_prod = rx_sge_prod; | |
581 | ||
582 | /* | |
583 | * Make sure that the BD and SGE data is updated before updating the | |
584 | * producers since FW might read the BD/SGE right after the producer | |
585 | * is updated. | |
586 | * This is only applicable for weak-ordered memory model archs such | |
587 | * as IA-64. The following barrier is also mandatory since FW will | |
588 | * assumes BDs must have buffers. | |
589 | */ | |
590 | wmb(); | |
591 | ||
619c5cb6 VZ |
592 | for (i = 0; i < sizeof(rx_prods)/4; i++) |
593 | REG_WR(bp, start + i*4, ((u32 *)&rx_prods)[i]); | |
9f6c9258 DK |
594 | |
595 | mmiowb(); /* keep prod updates ordered */ | |
596 | ||
597 | DP(NETIF_MSG_RX_STATUS, | |
598 | "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", | |
599 | fp->index, bd_prod, rx_comp_prod, rx_sge_prod); | |
600 | } | |
601 | ||
f2e0899f DK |
602 | static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, |
603 | u8 segment, u16 index, u8 op, | |
604 | u8 update, u32 igu_addr) | |
605 | { | |
606 | struct igu_regular cmd_data = {0}; | |
607 | ||
608 | cmd_data.sb_id_and_flags = | |
609 | ((index << IGU_REGULAR_SB_INDEX_SHIFT) | | |
610 | (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | | |
611 | (update << IGU_REGULAR_BUPDATE_SHIFT) | | |
612 | (op << IGU_REGULAR_ENABLE_INT_SHIFT)); | |
613 | ||
51c1a580 | 614 | DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", |
f2e0899f DK |
615 | cmd_data.sb_id_and_flags, igu_addr); |
616 | REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); | |
617 | ||
618 | /* Make sure that ACK is written */ | |
619 | mmiowb(); | |
620 | barrier(); | |
621 | } | |
622 | ||
f2e0899f DK |
623 | static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, |
624 | u8 storm, u16 index, u8 op, u8 update) | |
9f6c9258 DK |
625 | { |
626 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
627 | COMMAND_REG_INT_ACK); | |
628 | struct igu_ack_register igu_ack; | |
629 | ||
630 | igu_ack.status_block_index = index; | |
631 | igu_ack.sb_id_and_flags = | |
632 | ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | | |
633 | (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | | |
634 | (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | | |
635 | (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); | |
636 | ||
9f6c9258 DK |
637 | REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); |
638 | ||
639 | /* Make sure that ACK is written */ | |
640 | mmiowb(); | |
641 | barrier(); | |
642 | } | |
f2e0899f | 643 | |
f2e0899f DK |
644 | static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, |
645 | u16 index, u8 op, u8 update) | |
646 | { | |
647 | if (bp->common.int_block == INT_BLOCK_HC) | |
648 | bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); | |
649 | else { | |
650 | u8 segment; | |
651 | ||
652 | if (CHIP_INT_MODE_IS_BC(bp)) | |
653 | segment = storm; | |
654 | else if (igu_sb_id != bp->igu_dsb_id) | |
655 | segment = IGU_SEG_ACCESS_DEF; | |
656 | else if (storm == ATTENTION_ID) | |
657 | segment = IGU_SEG_ACCESS_ATTN; | |
658 | else | |
659 | segment = IGU_SEG_ACCESS_DEF; | |
660 | bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); | |
661 | } | |
662 | } | |
663 | ||
664 | static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) | |
9f6c9258 DK |
665 | { |
666 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
667 | COMMAND_REG_SIMD_MASK); | |
668 | u32 result = REG_RD(bp, hc_addr); | |
669 | ||
f2e0899f | 670 | barrier(); |
9f6c9258 DK |
671 | return result; |
672 | } | |
673 | ||
f2e0899f DK |
674 | static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) |
675 | { | |
676 | u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); | |
677 | u32 result = REG_RD(bp, igu_addr); | |
678 | ||
51c1a580 | 679 | DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", |
f2e0899f DK |
680 | result, igu_addr); |
681 | ||
682 | barrier(); | |
683 | return result; | |
684 | } | |
685 | ||
686 | static inline u16 bnx2x_ack_int(struct bnx2x *bp) | |
687 | { | |
688 | barrier(); | |
689 | if (bp->common.int_block == INT_BLOCK_HC) | |
690 | return bnx2x_hc_ack_int(bp); | |
691 | else | |
692 | return bnx2x_igu_ack_int(bp); | |
693 | } | |
694 | ||
6383c0b3 | 695 | static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) |
9f6c9258 DK |
696 | { |
697 | /* Tell compiler that consumer and producer can change */ | |
698 | barrier(); | |
6383c0b3 | 699 | return txdata->tx_pkt_prod != txdata->tx_pkt_cons; |
9f6c9258 DK |
700 | } |
701 | ||
6383c0b3 AE |
702 | static inline u16 bnx2x_tx_avail(struct bnx2x *bp, |
703 | struct bnx2x_fp_txdata *txdata) | |
9f6c9258 DK |
704 | { |
705 | s16 used; | |
706 | u16 prod; | |
707 | u16 cons; | |
708 | ||
6383c0b3 AE |
709 | prod = txdata->tx_bd_prod; |
710 | cons = txdata->tx_bd_cons; | |
9f6c9258 DK |
711 | |
712 | /* NUM_TX_RINGS = number of "next-page" entries | |
713 | It will be used as a threshold */ | |
714 | used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS; | |
715 | ||
716 | #ifdef BNX2X_STOP_ON_ERROR | |
717 | WARN_ON(used < 0); | |
6383c0b3 AE |
718 | WARN_ON(used > bp->tx_ring_size); |
719 | WARN_ON((bp->tx_ring_size - used) > MAX_TX_AVAIL); | |
9f6c9258 DK |
720 | #endif |
721 | ||
6383c0b3 | 722 | return (s16)(bp->tx_ring_size) - used; |
9f6c9258 DK |
723 | } |
724 | ||
6383c0b3 | 725 | static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) |
9f6c9258 DK |
726 | { |
727 | u16 hw_cons; | |
728 | ||
729 | /* Tell compiler that status block fields can change */ | |
730 | barrier(); | |
6383c0b3 AE |
731 | hw_cons = le16_to_cpu(*txdata->tx_cons_sb); |
732 | return hw_cons != txdata->tx_pkt_cons; | |
733 | } | |
734 | ||
735 | static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) | |
736 | { | |
737 | u8 cos; | |
738 | for_each_cos_in_tx_queue(fp, cos) | |
65565884 | 739 | if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) |
6383c0b3 AE |
740 | return true; |
741 | return false; | |
9f6c9258 DK |
742 | } |
743 | ||
523224a3 DK |
744 | static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) |
745 | { | |
746 | u16 rx_cons_sb; | |
747 | ||
748 | /* Tell compiler that status block fields can change */ | |
749 | barrier(); | |
750 | rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); | |
751 | if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) | |
752 | rx_cons_sb++; | |
753 | return (fp->rx_comp_cons != rx_cons_sb); | |
754 | } | |
f85582f8 | 755 | |
f2e0899f | 756 | /** |
619c5cb6 | 757 | * bnx2x_tx_disable - disables tx from stack point of view |
f2e0899f | 758 | * |
e8920674 | 759 | * @bp: driver handle |
f2e0899f DK |
760 | */ |
761 | static inline void bnx2x_tx_disable(struct bnx2x *bp) | |
762 | { | |
763 | netif_tx_disable(bp->dev); | |
764 | netif_carrier_off(bp->dev); | |
765 | } | |
766 | ||
9f6c9258 DK |
767 | static inline void bnx2x_free_rx_sge(struct bnx2x *bp, |
768 | struct bnx2x_fastpath *fp, u16 index) | |
769 | { | |
770 | struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; | |
771 | struct page *page = sw_buf->page; | |
772 | struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; | |
773 | ||
774 | /* Skip "next page" elements */ | |
775 | if (!page) | |
776 | return; | |
777 | ||
778 | dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), | |
4bca60f4 | 779 | SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); |
9f6c9258 DK |
780 | __free_pages(page, PAGES_PER_SGE_SHIFT); |
781 | ||
782 | sw_buf->page = NULL; | |
783 | sge->addr_hi = 0; | |
784 | sge->addr_lo = 0; | |
785 | } | |
786 | ||
d6214d7a DK |
787 | static inline void bnx2x_add_all_napi(struct bnx2x *bp) |
788 | { | |
789 | int i; | |
523224a3 | 790 | |
d6214d7a | 791 | /* Add NAPI objects */ |
619c5cb6 | 792 | for_each_rx_queue(bp, i) |
d6214d7a DK |
793 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), |
794 | bnx2x_poll, BNX2X_NAPI_WEIGHT); | |
795 | } | |
523224a3 | 796 | |
d6214d7a DK |
797 | static inline void bnx2x_del_all_napi(struct bnx2x *bp) |
798 | { | |
799 | int i; | |
800 | ||
619c5cb6 | 801 | for_each_rx_queue(bp, i) |
d6214d7a DK |
802 | netif_napi_del(&bnx2x_fp(bp, i, napi)); |
803 | } | |
523224a3 | 804 | |
d6214d7a DK |
805 | static inline void bnx2x_disable_msi(struct bnx2x *bp) |
806 | { | |
807 | if (bp->flags & USING_MSIX_FLAG) { | |
808 | pci_disable_msix(bp->pdev); | |
30a5de77 | 809 | bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); |
d6214d7a DK |
810 | } else if (bp->flags & USING_MSI_FLAG) { |
811 | pci_disable_msi(bp->pdev); | |
812 | bp->flags &= ~USING_MSI_FLAG; | |
813 | } | |
814 | } | |
815 | ||
816 | static inline int bnx2x_calc_num_queues(struct bnx2x *bp) | |
817 | { | |
818 | return num_queues ? | |
819 | min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : | |
820 | min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp)); | |
821 | } | |
523224a3 DK |
822 | |
823 | static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) | |
9f6c9258 | 824 | { |
523224a3 | 825 | int i, j; |
9f6c9258 | 826 | |
523224a3 DK |
827 | for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { |
828 | int idx = RX_SGE_CNT * i - 1; | |
829 | ||
830 | for (j = 0; j < 2; j++) { | |
619c5cb6 | 831 | BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); |
523224a3 DK |
832 | idx--; |
833 | } | |
834 | } | |
835 | } | |
836 | ||
837 | static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) | |
838 | { | |
839 | /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ | |
b3637827 | 840 | memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); |
523224a3 DK |
841 | |
842 | /* Clear the two last indices in the page to 1: | |
843 | these are the indices that correspond to the "next" element, | |
844 | hence will never be indicated and should be removed from | |
845 | the calculations. */ | |
846 | bnx2x_clear_sge_mask_next_elems(fp); | |
9f6c9258 DK |
847 | } |
848 | ||
e52fcb24 | 849 | /* note that we are not allocating a new buffer, |
9f6c9258 DK |
850 | * we are just moving one from cons to prod |
851 | * we are not creating a new mapping, | |
852 | * so there is no need to check for dma_mapping_error(). | |
853 | */ | |
e52fcb24 | 854 | static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, |
749a8503 | 855 | u16 cons, u16 prod) |
9f6c9258 | 856 | { |
9f6c9258 DK |
857 | struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; |
858 | struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; | |
859 | struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; | |
860 | struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; | |
861 | ||
9f6c9258 DK |
862 | dma_unmap_addr_set(prod_rx_buf, mapping, |
863 | dma_unmap_addr(cons_rx_buf, mapping)); | |
e52fcb24 | 864 | prod_rx_buf->data = cons_rx_buf->data; |
9f6c9258 DK |
865 | *prod_bd = *cons_bd; |
866 | } | |
f85582f8 | 867 | |
619c5cb6 VZ |
868 | /************************* Init ******************************************/ |
869 | ||
b475d78f YM |
870 | /* returns func by VN for current port */ |
871 | static inline int func_by_vn(struct bnx2x *bp, int vn) | |
872 | { | |
873 | return 2 * vn + BP_PORT(bp); | |
874 | } | |
875 | ||
5d317c6a | 876 | static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash) |
96305234 | 877 | { |
5d317c6a | 878 | return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, config_hash); |
96305234 DK |
879 | } |
880 | ||
619c5cb6 VZ |
881 | /** |
882 | * bnx2x_func_start - init function | |
883 | * | |
884 | * @bp: driver handle | |
885 | * | |
886 | * Must be called before sending CLIENT_SETUP for the first client. | |
887 | */ | |
888 | static inline int bnx2x_func_start(struct bnx2x *bp) | |
889 | { | |
3b603066 | 890 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 VZ |
891 | struct bnx2x_func_start_params *start_params = |
892 | &func_params.params.start; | |
893 | ||
894 | /* Prepare parameters for function state transitions */ | |
895 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
896 | ||
897 | func_params.f_obj = &bp->func_obj; | |
898 | func_params.cmd = BNX2X_F_CMD_START; | |
899 | ||
900 | /* Function parameters */ | |
901 | start_params->mf_mode = bp->mf_mode; | |
902 | start_params->sd_vlan_tag = bp->mf_ov; | |
8d7b0278 AE |
903 | |
904 | if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) | |
6383c0b3 | 905 | start_params->network_cos_mode = STATIC_COS; |
8d7b0278 AE |
906 | else /* CHIP_IS_E1X */ |
907 | start_params->network_cos_mode = FW_WRR; | |
619c5cb6 VZ |
908 | |
909 | return bnx2x_func_state_change(bp, &func_params); | |
910 | } | |
911 | ||
912 | ||
913 | /** | |
914 | * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format | |
915 | * | |
916 | * @fw_hi: pointer to upper part | |
917 | * @fw_mid: pointer to middle part | |
918 | * @fw_lo: pointer to lower part | |
919 | * @mac: pointer to MAC address | |
920 | */ | |
921 | static inline void bnx2x_set_fw_mac_addr(u16 *fw_hi, u16 *fw_mid, u16 *fw_lo, | |
922 | u8 *mac) | |
923 | { | |
924 | ((u8 *)fw_hi)[0] = mac[1]; | |
925 | ((u8 *)fw_hi)[1] = mac[0]; | |
926 | ((u8 *)fw_mid)[0] = mac[3]; | |
927 | ((u8 *)fw_mid)[1] = mac[2]; | |
928 | ((u8 *)fw_lo)[0] = mac[5]; | |
929 | ((u8 *)fw_lo)[1] = mac[4]; | |
930 | } | |
931 | ||
523224a3 DK |
932 | static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, |
933 | struct bnx2x_fastpath *fp, int last) | |
9f6c9258 | 934 | { |
523224a3 | 935 | int i; |
9f6c9258 | 936 | |
b3b83c3f DK |
937 | if (fp->disable_tpa) |
938 | return; | |
939 | ||
523224a3 DK |
940 | for (i = 0; i < last; i++) |
941 | bnx2x_free_rx_sge(bp, fp, i); | |
9f6c9258 DK |
942 | } |
943 | ||
523224a3 | 944 | static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) |
9f6c9258 | 945 | { |
523224a3 | 946 | int i; |
9f6c9258 | 947 | |
523224a3 DK |
948 | for (i = 1; i <= NUM_RX_RINGS; i++) { |
949 | struct eth_rx_bd *rx_bd; | |
950 | ||
951 | rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; | |
952 | rx_bd->addr_hi = | |
953 | cpu_to_le32(U64_HI(fp->rx_desc_mapping + | |
954 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
955 | rx_bd->addr_lo = | |
956 | cpu_to_le32(U64_LO(fp->rx_desc_mapping + | |
957 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
958 | } | |
9f6c9258 DK |
959 | } |
960 | ||
619c5cb6 VZ |
961 | /* Statistics ID are global per chip/path, while Client IDs for E1x are per |
962 | * port. | |
963 | */ | |
964 | static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) | |
965 | { | |
de5c3741 YM |
966 | struct bnx2x *bp = fp->bp; |
967 | if (!CHIP_IS_E1x(bp)) { | |
968 | #ifdef BCM_CNIC | |
969 | /* there are special statistics counters for FCoE 136..140 */ | |
970 | if (IS_FCOE_FP(fp)) | |
971 | return bp->cnic_base_cl_id + (bp->pf_num >> 1); | |
972 | #endif | |
619c5cb6 | 973 | return fp->cl_id; |
de5c3741 YM |
974 | } |
975 | return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; | |
619c5cb6 VZ |
976 | } |
977 | ||
978 | static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, | |
979 | bnx2x_obj_type obj_type) | |
980 | { | |
981 | struct bnx2x *bp = fp->bp; | |
982 | ||
983 | /* Configure classification DBs */ | |
984 | bnx2x_init_mac_obj(bp, &fp->mac_obj, fp->cl_id, fp->cid, | |
985 | BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), | |
986 | bnx2x_sp_mapping(bp, mac_rdata), | |
987 | BNX2X_FILTER_MAC_PENDING, | |
988 | &bp->sp_state, obj_type, | |
989 | &bp->macs_pool); | |
990 | } | |
991 | ||
992 | /** | |
993 | * bnx2x_get_path_func_num - get number of active functions | |
994 | * | |
995 | * @bp: driver handle | |
996 | * | |
997 | * Calculates the number of active (not hidden) functions on the | |
998 | * current path. | |
999 | */ | |
1000 | static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) | |
1001 | { | |
1002 | u8 func_num = 0, i; | |
1003 | ||
1004 | /* 57710 has only one function per-port */ | |
1005 | if (CHIP_IS_E1(bp)) | |
1006 | return 1; | |
1007 | ||
1008 | /* Calculate a number of functions enabled on the current | |
1009 | * PATH/PORT. | |
1010 | */ | |
1011 | if (CHIP_REV_IS_SLOW(bp)) { | |
1012 | if (IS_MF(bp)) | |
1013 | func_num = 4; | |
1014 | else | |
1015 | func_num = 2; | |
1016 | } else { | |
1017 | for (i = 0; i < E1H_FUNC_MAX / 2; i++) { | |
1018 | u32 func_config = | |
1019 | MF_CFG_RD(bp, | |
1020 | func_mf_config[BP_PORT(bp) + 2 * i]. | |
1021 | config); | |
1022 | func_num += | |
1023 | ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); | |
1024 | } | |
1025 | } | |
1026 | ||
1027 | WARN_ON(!func_num); | |
1028 | ||
1029 | return func_num; | |
1030 | } | |
1031 | ||
1032 | static inline void bnx2x_init_bp_objs(struct bnx2x *bp) | |
1033 | { | |
1034 | /* RX_MODE controlling object */ | |
1035 | bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); | |
1036 | ||
1037 | /* multicast configuration controlling object */ | |
1038 | bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, | |
1039 | BP_FUNC(bp), BP_FUNC(bp), | |
1040 | bnx2x_sp(bp, mcast_rdata), | |
1041 | bnx2x_sp_mapping(bp, mcast_rdata), | |
1042 | BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, | |
1043 | BNX2X_OBJ_TYPE_RX); | |
1044 | ||
1045 | /* Setup CAM credit pools */ | |
1046 | bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), | |
1047 | bnx2x_get_path_func_num(bp)); | |
1048 | ||
1049 | /* RSS configuration object */ | |
1050 | bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, | |
1051 | bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), | |
1052 | bnx2x_sp(bp, rss_rdata), | |
1053 | bnx2x_sp_mapping(bp, rss_rdata), | |
1054 | BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, | |
1055 | BNX2X_OBJ_TYPE_RX); | |
1056 | } | |
1057 | ||
1058 | static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) | |
1059 | { | |
1060 | if (CHIP_IS_E1x(fp->bp)) | |
1061 | return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; | |
1062 | else | |
1063 | return fp->cl_id; | |
1064 | } | |
1065 | ||
1066 | static inline u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) | |
1067 | { | |
1068 | struct bnx2x *bp = fp->bp; | |
1069 | ||
1070 | if (!CHIP_IS_E1x(bp)) | |
1071 | return USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); | |
1072 | else | |
1073 | return USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); | |
1074 | } | |
1075 | ||
6383c0b3 | 1076 | static inline void bnx2x_init_txdata(struct bnx2x *bp, |
65565884 MS |
1077 | struct bnx2x_fp_txdata *txdata, u32 cid, |
1078 | int txq_index, __le16 *tx_cons_sb, | |
1079 | struct bnx2x_fastpath *fp) | |
6383c0b3 AE |
1080 | { |
1081 | txdata->cid = cid; | |
1082 | txdata->txq_index = txq_index; | |
1083 | txdata->tx_cons_sb = tx_cons_sb; | |
65565884 | 1084 | txdata->parent_fp = fp; |
6383c0b3 | 1085 | |
51c1a580 | 1086 | DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", |
6383c0b3 AE |
1087 | txdata->cid, txdata->txq_index); |
1088 | } | |
619c5cb6 | 1089 | |
ec6ba945 | 1090 | #ifdef BCM_CNIC |
619c5cb6 VZ |
1091 | static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) |
1092 | { | |
1093 | return bp->cnic_base_cl_id + cl_idx + | |
134d0f97 | 1094 | (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; |
619c5cb6 VZ |
1095 | } |
1096 | ||
1097 | static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) | |
1098 | { | |
1099 | ||
1100 | /* the 'first' id is allocated for the cnic */ | |
1101 | return bp->base_fw_ndsb; | |
1102 | } | |
1103 | ||
1104 | static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) | |
1105 | { | |
1106 | return bp->igu_base_sb; | |
1107 | } | |
1108 | ||
1109 | ||
ec6ba945 VZ |
1110 | static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) |
1111 | { | |
619c5cb6 VZ |
1112 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); |
1113 | unsigned long q_type = 0; | |
1114 | ||
f233cafe | 1115 | bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); |
619c5cb6 VZ |
1116 | bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, |
1117 | BNX2X_FCOE_ETH_CL_ID_IDX); | |
37ae41a9 | 1118 | bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); |
ec6ba945 VZ |
1119 | bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; |
1120 | bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; | |
ec6ba945 | 1121 | bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; |
65565884 MS |
1122 | bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), |
1123 | fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, | |
1124 | fp); | |
6383c0b3 | 1125 | |
51c1a580 | 1126 | DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); |
6383c0b3 | 1127 | |
ec6ba945 | 1128 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 | 1129 | bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); |
ec6ba945 | 1130 | /* init shortcut */ |
619c5cb6 VZ |
1131 | bnx2x_fcoe(bp, ustorm_rx_prods_offset) = |
1132 | bnx2x_rx_ustorm_prods_offset(fp); | |
1133 | ||
1134 | /* Configure Queue State object */ | |
1135 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
1136 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
1137 | |
1138 | /* No multi-CoS for FCoE L2 client */ | |
1139 | BUG_ON(fp->max_cos != 1); | |
1140 | ||
1141 | bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, &fp->cid, 1, | |
1142 | BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
1143 | bnx2x_sp_mapping(bp, q_rdata), q_type); | |
619c5cb6 | 1144 | |
51c1a580 MS |
1145 | DP(NETIF_MSG_IFUP, |
1146 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", | |
619c5cb6 VZ |
1147 | fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, |
1148 | fp->igu_sb_id); | |
ec6ba945 VZ |
1149 | } |
1150 | #endif | |
523224a3 | 1151 | |
619c5cb6 | 1152 | static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, |
6383c0b3 | 1153 | struct bnx2x_fp_txdata *txdata) |
619c5cb6 VZ |
1154 | { |
1155 | int cnt = 1000; | |
1156 | ||
6383c0b3 | 1157 | while (bnx2x_has_tx_work_unload(txdata)) { |
619c5cb6 | 1158 | if (!cnt) { |
51c1a580 | 1159 | BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", |
6383c0b3 AE |
1160 | txdata->txq_index, txdata->tx_pkt_prod, |
1161 | txdata->tx_pkt_cons); | |
619c5cb6 VZ |
1162 | #ifdef BNX2X_STOP_ON_ERROR |
1163 | bnx2x_panic(); | |
1164 | return -EBUSY; | |
1165 | #else | |
1166 | break; | |
1167 | #endif | |
1168 | } | |
1169 | cnt--; | |
1170 | usleep_range(1000, 1000); | |
1171 | } | |
1172 | ||
1173 | return 0; | |
1174 | } | |
1175 | ||
1ac9e428 YR |
1176 | int bnx2x_get_link_cfg_idx(struct bnx2x *bp); |
1177 | ||
523224a3 DK |
1178 | static inline void __storm_memset_struct(struct bnx2x *bp, |
1179 | u32 addr, size_t size, u32 *data) | |
1180 | { | |
1181 | int i; | |
1182 | for (i = 0; i < size/4; i++) | |
1183 | REG_WR(bp, addr + (i * 4), data[i]); | |
1184 | } | |
1185 | ||
619c5cb6 VZ |
1186 | /** |
1187 | * bnx2x_wait_sp_comp - wait for the outstanding SP commands. | |
1188 | * | |
1189 | * @bp: driver handle | |
1190 | * @mask: bits that need to be cleared | |
1191 | */ | |
1192 | static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) | |
1193 | { | |
1194 | int tout = 5000; /* Wait for 5 secs tops */ | |
1195 | ||
1196 | while (tout--) { | |
1197 | smp_mb(); | |
1198 | netif_addr_lock_bh(bp->dev); | |
1199 | if (!(bp->sp_state & mask)) { | |
1200 | netif_addr_unlock_bh(bp->dev); | |
1201 | return true; | |
1202 | } | |
1203 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1204 | |
619c5cb6 VZ |
1205 | usleep_range(1000, 1000); |
1206 | } | |
1207 | ||
1208 | smp_mb(); | |
1209 | ||
1210 | netif_addr_lock_bh(bp->dev); | |
1211 | if (bp->sp_state & mask) { | |
51c1a580 MS |
1212 | BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n", |
1213 | bp->sp_state, mask); | |
619c5cb6 VZ |
1214 | netif_addr_unlock_bh(bp->dev); |
1215 | return false; | |
1216 | } | |
1217 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1218 | |
619c5cb6 | 1219 | return true; |
523224a3 | 1220 | } |
f85582f8 | 1221 | |
619c5cb6 VZ |
1222 | /** |
1223 | * bnx2x_set_ctx_validation - set CDU context validation values | |
1224 | * | |
1225 | * @bp: driver handle | |
1226 | * @cxt: context of the connection on the host memory | |
1227 | * @cid: SW CID of the connection to be configured | |
1228 | */ | |
1229 | void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, | |
1230 | u32 cid); | |
1231 | ||
1232 | void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, | |
1233 | u8 sb_index, u8 disable, u16 usec); | |
9f6c9258 DK |
1234 | void bnx2x_acquire_phy_lock(struct bnx2x *bp); |
1235 | void bnx2x_release_phy_lock(struct bnx2x *bp); | |
1236 | ||
faa6fcbb | 1237 | /** |
e8920674 | 1238 | * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. |
faa6fcbb | 1239 | * |
e8920674 DK |
1240 | * @bp: driver handle |
1241 | * @mf_cfg: MF configuration | |
faa6fcbb | 1242 | * |
faa6fcbb DK |
1243 | */ |
1244 | static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) | |
1245 | { | |
1246 | u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> | |
1247 | FUNC_MF_CFG_MAX_BW_SHIFT; | |
1248 | if (!max_cfg) { | |
51c1a580 | 1249 | DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, |
96b0accb | 1250 | "Max BW configured to 0 - using 100 instead\n"); |
faa6fcbb DK |
1251 | max_cfg = 100; |
1252 | } | |
1253 | return max_cfg; | |
1254 | } | |
1255 | ||
621b4d66 DK |
1256 | /* checks if HW supports GRO for given MTU */ |
1257 | static inline bool bnx2x_mtu_allows_gro(int mtu) | |
1258 | { | |
1259 | /* gro frags per page */ | |
1260 | int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); | |
1261 | ||
1262 | /* | |
1263 | * 1. number of frags should not grow above MAX_SKB_FRAGS | |
1264 | * 2. frag must fit the page | |
1265 | */ | |
1266 | return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; | |
1267 | } | |
3b603066 | 1268 | #ifdef BCM_CNIC |
b306f5ed DK |
1269 | /** |
1270 | * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. | |
1271 | * | |
1272 | * @bp: driver handle | |
1273 | * | |
1274 | */ | |
1275 | void bnx2x_get_iscsi_info(struct bnx2x *bp); | |
3b603066 | 1276 | #endif |
00253a8c DK |
1277 | |
1278 | /** | |
1279 | * bnx2x_link_sync_notify - send notification to other functions. | |
1280 | * | |
1281 | * @bp: driver handle | |
1282 | * | |
1283 | */ | |
1284 | static inline void bnx2x_link_sync_notify(struct bnx2x *bp) | |
1285 | { | |
1286 | int func; | |
1287 | int vn; | |
1288 | ||
1289 | /* Set the attention towards other drivers on the same port */ | |
1290 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
1291 | if (vn == BP_VN(bp)) | |
1292 | continue; | |
1293 | ||
1294 | func = func_by_vn(bp, vn); | |
1295 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + | |
1296 | (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); | |
1297 | } | |
1298 | } | |
1299 | ||
1300 | /** | |
1301 | * bnx2x_update_drv_flags - update flags in shmem | |
1302 | * | |
1303 | * @bp: driver handle | |
1304 | * @flags: flags to update | |
1305 | * @set: set or clear | |
1306 | * | |
1307 | */ | |
1308 | static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) | |
1309 | { | |
1310 | if (SHMEM2_HAS(bp, drv_flags)) { | |
1311 | u32 drv_flags; | |
f16da43b | 1312 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); |
00253a8c DK |
1313 | drv_flags = SHMEM2_RD(bp, drv_flags); |
1314 | ||
1315 | if (set) | |
1316 | SET_FLAGS(drv_flags, flags); | |
1317 | else | |
1318 | RESET_FLAGS(drv_flags, flags); | |
1319 | ||
1320 | SHMEM2_WR(bp, drv_flags, drv_flags); | |
51c1a580 | 1321 | DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); |
f16da43b | 1322 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); |
00253a8c DK |
1323 | } |
1324 | } | |
1325 | ||
614c76df DK |
1326 | static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) |
1327 | { | |
1328 | if (is_valid_ether_addr(addr)) | |
1329 | return true; | |
1330 | #ifdef BCM_CNIC | |
a3348722 BW |
1331 | if (is_zero_ether_addr(addr) && |
1332 | (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) | |
614c76df DK |
1333 | return true; |
1334 | #endif | |
1335 | return false; | |
1336 | } | |
1337 | ||
9f6c9258 | 1338 | #endif /* BNX2X_CMN_H */ |