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bnx2x: removed code re-checking memory base after device open
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
85b26ea1 3 * Copyright (c) 2007-2012 Broadcom Corporation
de0c62db
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
f1deab50
JP		 17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
de0c62db
DK		 20#include <linux/ethtool.h>
21#include <linux/netdevice.h>
22#include <linux/types.h>
23#include <linux/sched.h>
24#include <linux/crc32.h>
25
26
27#include "bnx2x.h"
28#include "bnx2x_cmn.h"
29#include "bnx2x_dump.h"
4a33bc03 30#include "bnx2x_init.h"
042181f5 31#include "bnx2x_sp.h"
de0c62db 32
ec6ba945
VZ		 33/* Note: in the format strings below %s is replaced by the queue-name which is
34 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
35 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
36 */
37#define MAX_QUEUE_NAME_LEN 4
38static const struct {
39 long offset;
40 int size;
41 char string[ETH_GSTRING_LEN];
42} bnx2x_q_stats_arr[] = {
43/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
ec6ba945
VZ		 44 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
45 8, "[%s]: rx_ucast_packets" },
46 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
47 8, "[%s]: rx_mcast_packets" },
48 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
49 8, "[%s]: rx_bcast_packets" },
50 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
51 { Q_STATS_OFFSET32(rx_err_discard_pkt),
52 4, "[%s]: rx_phy_ip_err_discards"},
53 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
54 4, "[%s]: rx_skb_alloc_discard" },
55 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
56
619c5cb6
VZ		 57 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
58/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
ec6ba945
VZ		 59 8, "[%s]: tx_ucast_packets" },
60 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
61 8, "[%s]: tx_mcast_packets" },
62 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
619c5cb6
VZ		 63 8, "[%s]: tx_bcast_packets" },
64 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
65 8, "[%s]: tpa_aggregations" },
66 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
67 8, "[%s]: tpa_aggregated_frames"},
68 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
ec6ba945
VZ		 69};
70
71#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
72
73static const struct {
74 long offset;
75 int size;
76 u32 flags;
77#define STATS_FLAGS_PORT 1
78#define STATS_FLAGS_FUNC 2
79#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
80 char string[ETH_GSTRING_LEN];
81} bnx2x_stats_arr[] = {
82/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
83 8, STATS_FLAGS_BOTH, "rx_bytes" },
84 { STATS_OFFSET32(error_bytes_received_hi),
85 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
86 { STATS_OFFSET32(total_unicast_packets_received_hi),
87 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
88 { STATS_OFFSET32(total_multicast_packets_received_hi),
89 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
90 { STATS_OFFSET32(total_broadcast_packets_received_hi),
91 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
92 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
93 8, STATS_FLAGS_PORT, "rx_crc_errors" },
94 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
95 8, STATS_FLAGS_PORT, "rx_align_errors" },
96 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
97 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
98 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
99 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
100/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
101 8, STATS_FLAGS_PORT, "rx_fragments" },
102 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
103 8, STATS_FLAGS_PORT, "rx_jabbers" },
104 { STATS_OFFSET32(no_buff_discard_hi),
105 8, STATS_FLAGS_BOTH, "rx_discards" },
106 { STATS_OFFSET32(mac_filter_discard),
107 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
619c5cb6
VZ		 108 { STATS_OFFSET32(mf_tag_discard),
109 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
0e898dd7
BW		 110 { STATS_OFFSET32(pfc_frames_received_hi),
111 8, STATS_FLAGS_PORT, "pfc_frames_received" },
112 { STATS_OFFSET32(pfc_frames_sent_hi),
113 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
ec6ba945
VZ		 114 { STATS_OFFSET32(brb_drop_hi),
115 8, STATS_FLAGS_PORT, "rx_brb_discard" },
116 { STATS_OFFSET32(brb_truncate_hi),
117 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
118 { STATS_OFFSET32(pause_frames_received_hi),
119 8, STATS_FLAGS_PORT, "rx_pause_frames" },
120 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
121 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
122 { STATS_OFFSET32(nig_timer_max),
123 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
124/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
125 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
126 { STATS_OFFSET32(rx_skb_alloc_failed),
127 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
128 { STATS_OFFSET32(hw_csum_err),
129 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
130
131 { STATS_OFFSET32(total_bytes_transmitted_hi),
132 8, STATS_FLAGS_BOTH, "tx_bytes" },
133 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
134 8, STATS_FLAGS_PORT, "tx_error_bytes" },
135 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
136 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
137 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
138 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
139 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
140 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
141 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
142 8, STATS_FLAGS_PORT, "tx_mac_errors" },
143 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
144 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
145/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
146 8, STATS_FLAGS_PORT, "tx_single_collisions" },
147 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
148 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
149 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
150 8, STATS_FLAGS_PORT, "tx_deferred" },
151 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
152 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
153 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
154 8, STATS_FLAGS_PORT, "tx_late_collisions" },
155 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
156 8, STATS_FLAGS_PORT, "tx_total_collisions" },
157 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
158 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
159 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
160 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
161 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
162 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
163 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
164 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
165/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
166 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
167 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
168 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
169 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
170 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
171 { STATS_OFFSET32(pause_frames_sent_hi),
619c5cb6
VZ		 172 8, STATS_FLAGS_PORT, "tx_pause_frames" },
173 { STATS_OFFSET32(total_tpa_aggregations_hi),
174 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
175 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
176 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
177 { STATS_OFFSET32(total_tpa_bytes_hi),
7a752993
AE		 178 8, STATS_FLAGS_FUNC, "tpa_bytes"},
179 { STATS_OFFSET32(recoverable_error),
180 4, STATS_FLAGS_FUNC, "recoverable_errors" },
181 { STATS_OFFSET32(unrecoverable_error),
182 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
ec6ba945
VZ		 183};
184
185#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
1ac9e428
YR		 186static int bnx2x_get_port_type(struct bnx2x *bp)
187{
188 int port_type;
189 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
190 switch (bp->link_params.phy[phy_idx].media_type) {
191 case ETH_PHY_SFP_FIBER:
192 case ETH_PHY_XFP_FIBER:
193 case ETH_PHY_KR:
194 case ETH_PHY_CX4:
195 port_type = PORT_FIBRE;
196 break;
197 case ETH_PHY_DA_TWINAX:
198 port_type = PORT_DA;
199 break;
200 case ETH_PHY_BASE_T:
201 port_type = PORT_TP;
202 break;
203 case ETH_PHY_NOT_PRESENT:
204 port_type = PORT_NONE;
205 break;
206 case ETH_PHY_UNSPECIFIED:
207 default:
208 port_type = PORT_OTHER;
209 break;
210 }
211 return port_type;
212}
ec6ba945 213
de0c62db
DK		 214static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
215{
216 struct bnx2x *bp = netdev_priv(dev);
a22f0788 217 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
b3337e4c 218
a22f0788
YR		 219 /* Dual Media boards present all available port types */
220 cmd->supported = bp->port.supported[cfg_idx] |
221 (bp->port.supported[cfg_idx ^ 1] &
222 (SUPPORTED_TP | SUPPORTED_FIBRE));
223 cmd->advertising = bp->port.advertising[cfg_idx];
de0c62db
DK		 224
225 if ((bp->state == BNX2X_STATE_OPEN) &&
226 !(bp->flags & MF_FUNC_DIS) &&
227 (bp->link_vars.link_up)) {
b3337e4c 228 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
de0c62db 229 cmd->duplex = bp->link_vars.duplex;
de0c62db 230 } else {
b3337e4c
DD		 231 ethtool_cmd_speed_set(
232 cmd, bp->link_params.req_line_speed[cfg_idx]);
a22f0788 233 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
de0c62db 234 }
f2e0899f 235
0793f83f 236 if (IS_MF(bp))
b3337e4c 237 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
de0c62db 238
1ac9e428 239 cmd->port = bnx2x_get_port_type(bp);
a22f0788 240
de0c62db
DK		 241 cmd->phy_address = bp->mdio.prtad;
242 cmd->transceiver = XCVR_INTERNAL;
243
a22f0788 244 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 245 cmd->autoneg = AUTONEG_ENABLE;
246 else
247 cmd->autoneg = AUTONEG_DISABLE;
248
9e7e8399
MY		 249 /* Publish LP advertised speeds and FC */
250 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
251 u32 status = bp->link_vars.link_status;
252
253 cmd->lp_advertising |= ADVERTISED_Autoneg;
254 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
255 cmd->lp_advertising |= ADVERTISED_Pause;
256 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
257 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
258
259 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
260 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
261 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
262 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
263 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
264 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
265 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
266 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
267 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
268 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
269 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
270 cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
271 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
272 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
273 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
274 cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
275 }
276
de0c62db
DK		 277 cmd->maxtxpkt = 0;
278 cmd->maxrxpkt = 0;
279
280 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
f1deab50
JP		 281 " supported 0x%x advertising 0x%x speed %u\n"
282 " duplex %d port %d phy_address %d transceiver %d\n"
283 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 284 cmd->cmd, cmd->supported, cmd->advertising,
285 ethtool_cmd_speed(cmd),
de0c62db
DK		 286 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
287 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
288
289 return 0;
290}
291
292static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
293{
294 struct bnx2x *bp = netdev_priv(dev);
a22f0788 295 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
0793f83f 296 u32 speed;
de0c62db 297
0793f83f 298 if (IS_MF_SD(bp))
de0c62db
DK		 299 return 0;
300
301 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
b3337e4c 302 " supported 0x%x advertising 0x%x speed %u\n"
0793f83f
DK		 303 " duplex %d port %d phy_address %d transceiver %d\n"
304 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 305 cmd->cmd, cmd->supported, cmd->advertising,
306 ethtool_cmd_speed(cmd),
de0c62db
DK		 307 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
308 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
309
b3337e4c 310 speed = ethtool_cmd_speed(cmd);
0793f83f
DK		 311
312 if (IS_MF_SI(bp)) {
e3835b99 313 u32 part;
0793f83f
DK		 314 u32 line_speed = bp->link_vars.line_speed;
315
316 /* use 10G if no link detected */
317 if (!line_speed)
318 line_speed = 10000;
319
320 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
321 BNX2X_DEV_INFO("To set speed BC %X or higher "
322 "is required, please upgrade BC\n",
323 REQ_BC_VER_4_SET_MF_BW);
324 return -EINVAL;
325 }
e3835b99 326
faa6fcbb 327 part = (speed * 100) / line_speed;
e3835b99 328
faa6fcbb
DK		 329 if (line_speed < speed || !part) {
330 BNX2X_DEV_INFO("Speed setting should be in a range "
331 "from 1%% to 100%% "
332 "of actual line speed\n");
0793f83f
DK		 333 return -EINVAL;
334 }
0793f83f 335
e3835b99
DK		 336 if (bp->state != BNX2X_STATE_OPEN)
337 /* store value for following "load" */
338 bp->pending_max = part;
339 else
340 bnx2x_update_max_mf_config(bp, part);
0793f83f 341
0793f83f
DK		 342 return 0;
343 }
344
a22f0788
YR		 345 cfg_idx = bnx2x_get_link_cfg_idx(bp);
346 old_multi_phy_config = bp->link_params.multi_phy_config;
347 switch (cmd->port) {
348 case PORT_TP:
349 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
350 break; /* no port change */
351
352 if (!(bp->port.supported[0] & SUPPORTED_TP ||
353 bp->port.supported[1] & SUPPORTED_TP)) {
354 DP(NETIF_MSG_LINK, "Unsupported port type\n");
355 return -EINVAL;
356 }
357 bp->link_params.multi_phy_config &=
358 ~PORT_HW_CFG_PHY_SELECTION_MASK;
359 if (bp->link_params.multi_phy_config &
360 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
361 bp->link_params.multi_phy_config |=
362 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
363 else
364 bp->link_params.multi_phy_config |=
365 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
366 break;
367 case PORT_FIBRE:
bfdb5823 368 case PORT_DA:
a22f0788
YR		 369 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
370 break; /* no port change */
371
372 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
373 bp->port.supported[1] & SUPPORTED_FIBRE)) {
374 DP(NETIF_MSG_LINK, "Unsupported port type\n");
375 return -EINVAL;
376 }
377 bp->link_params.multi_phy_config &=
378 ~PORT_HW_CFG_PHY_SELECTION_MASK;
379 if (bp->link_params.multi_phy_config &
380 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
381 bp->link_params.multi_phy_config |=
382 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
383 else
384 bp->link_params.multi_phy_config |=
385 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
386 break;
387 default:
388 DP(NETIF_MSG_LINK, "Unsupported port type\n");
389 return -EINVAL;
390 }
2f751a80 391 /* Save new config in case command complete successully */
a22f0788
YR		 392 new_multi_phy_config = bp->link_params.multi_phy_config;
393 /* Get the new cfg_idx */
394 cfg_idx = bnx2x_get_link_cfg_idx(bp);
395 /* Restore old config in case command failed */
396 bp->link_params.multi_phy_config = old_multi_phy_config;
397 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
398
de0c62db 399 if (cmd->autoneg == AUTONEG_ENABLE) {
75318327
YR		 400 u32 an_supported_speed = bp->port.supported[cfg_idx];
401 if (bp->link_params.phy[EXT_PHY1].type ==
402 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
403 an_supported_speed |= (SUPPORTED_100baseT_Half |
404 SUPPORTED_100baseT_Full);
a22f0788 405 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
de0c62db
DK		 406 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
407 return -EINVAL;
408 }
409
410 /* advertise the requested speed and duplex if supported */
75318327 411 if (cmd->advertising & ~an_supported_speed) {
8d661637
YR		 412 DP(NETIF_MSG_LINK, "Advertisement parameters "
413 "are not supported\n");
414 return -EINVAL;
415 }
de0c62db 416
a22f0788 417 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
8d661637
YR		 418 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
419 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
de0c62db 420 cmd->advertising);
8d661637
YR		 421 if (cmd->advertising) {
422
423 bp->link_params.speed_cap_mask[cfg_idx] = 0;
424 if (cmd->advertising & ADVERTISED_10baseT_Half) {
425 bp->link_params.speed_cap_mask[cfg_idx] |=
426 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
427 }
428 if (cmd->advertising & ADVERTISED_10baseT_Full)
429 bp->link_params.speed_cap_mask[cfg_idx] |=
430 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
de0c62db 431
8d661637
YR		 432 if (cmd->advertising & ADVERTISED_100baseT_Full)
433 bp->link_params.speed_cap_mask[cfg_idx] |=
434 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
435
436 if (cmd->advertising & ADVERTISED_100baseT_Half) {
437 bp->link_params.speed_cap_mask[cfg_idx] |=
438 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
439 }
440 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
441 bp->link_params.speed_cap_mask[cfg_idx] |=
442 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
443 }
444 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
445 ADVERTISED_1000baseKX_Full))
446 bp->link_params.speed_cap_mask[cfg_idx] |=
447 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
448
449 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
450 ADVERTISED_10000baseKX4_Full |
451 ADVERTISED_10000baseKR_Full))
452 bp->link_params.speed_cap_mask[cfg_idx] |=
453 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
454 }
de0c62db
DK		 455 } else { /* forced speed */
456 /* advertise the requested speed and duplex if supported */
a22f0788 457 switch (speed) {
de0c62db
DK		 458 case SPEED_10:
459 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 460 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 461 SUPPORTED_10baseT_Full)) {
462 DP(NETIF_MSG_LINK,
463 "10M full not supported\n");
464 return -EINVAL;
465 }
466
467 advertising = (ADVERTISED_10baseT_Full |
468 ADVERTISED_TP);
469 } else {
a22f0788 470 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 471 SUPPORTED_10baseT_Half)) {
472 DP(NETIF_MSG_LINK,
473 "10M half not supported\n");
474 return -EINVAL;
475 }
476
477 advertising = (ADVERTISED_10baseT_Half |
478 ADVERTISED_TP);
479 }
480 break;
481
482 case SPEED_100:
483 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 484 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 485 SUPPORTED_100baseT_Full)) {
486 DP(NETIF_MSG_LINK,
487 "100M full not supported\n");
488 return -EINVAL;
489 }
490
491 advertising = (ADVERTISED_100baseT_Full |
492 ADVERTISED_TP);
493 } else {
a22f0788 494 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 495 SUPPORTED_100baseT_Half)) {
496 DP(NETIF_MSG_LINK,
497 "100M half not supported\n");
498 return -EINVAL;
499 }
500
501 advertising = (ADVERTISED_100baseT_Half |
502 ADVERTISED_TP);
503 }
504 break;
505
506 case SPEED_1000:
507 if (cmd->duplex != DUPLEX_FULL) {
508 DP(NETIF_MSG_LINK, "1G half not supported\n");
509 return -EINVAL;
510 }
511
a22f0788
YR		 512 if (!(bp->port.supported[cfg_idx] &
513 SUPPORTED_1000baseT_Full)) {
de0c62db
DK		 514 DP(NETIF_MSG_LINK, "1G full not supported\n");
515 return -EINVAL;
516 }
517
518 advertising = (ADVERTISED_1000baseT_Full |
519 ADVERTISED_TP);
520 break;
521
522 case SPEED_2500:
523 if (cmd->duplex != DUPLEX_FULL) {
524 DP(NETIF_MSG_LINK,
525 "2.5G half not supported\n");
526 return -EINVAL;
527 }
528
a22f0788
YR		 529 if (!(bp->port.supported[cfg_idx]
530 & SUPPORTED_2500baseX_Full)) {
de0c62db
DK		 531 DP(NETIF_MSG_LINK,
532 "2.5G full not supported\n");
533 return -EINVAL;
534 }
535
536 advertising = (ADVERTISED_2500baseX_Full |
537 ADVERTISED_TP);
538 break;
539
540 case SPEED_10000:
541 if (cmd->duplex != DUPLEX_FULL) {
542 DP(NETIF_MSG_LINK, "10G half not supported\n");
543 return -EINVAL;
544 }
545
a22f0788
YR		 546 if (!(bp->port.supported[cfg_idx]
547 & SUPPORTED_10000baseT_Full)) {
de0c62db
DK		 548 DP(NETIF_MSG_LINK, "10G full not supported\n");
549 return -EINVAL;
550 }
551
552 advertising = (ADVERTISED_10000baseT_Full |
553 ADVERTISED_FIBRE);
554 break;
555
556 default:
b3337e4c 557 DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed);
de0c62db
DK		 558 return -EINVAL;
559 }
560
a22f0788
YR		 561 bp->link_params.req_line_speed[cfg_idx] = speed;
562 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
563 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 564 }
565
566 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
f1deab50 567 " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 568 bp->link_params.req_line_speed[cfg_idx],
569 bp->link_params.req_duplex[cfg_idx],
570 bp->port.advertising[cfg_idx]);
de0c62db 571
a22f0788
YR		 572 /* Set new config */
573 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 574 if (netif_running(dev)) {
575 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
576 bnx2x_link_set(bp);
577 }
578
579 return 0;
580}
581
582#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
583#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
f2e0899f 584#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
0fea29c1
VZ		 585#define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
586#define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
587
588static inline bool bnx2x_is_reg_online(struct bnx2x *bp,
589 const struct reg_addr *reg_info)
590{
591 if (CHIP_IS_E1(bp))
592 return IS_E1_ONLINE(reg_info->info);
593 else if (CHIP_IS_E1H(bp))
594 return IS_E1H_ONLINE(reg_info->info);
595 else if (CHIP_IS_E2(bp))
596 return IS_E2_ONLINE(reg_info->info);
597 else if (CHIP_IS_E3A0(bp))
598 return IS_E3_ONLINE(reg_info->info);
599 else if (CHIP_IS_E3B0(bp))
600 return IS_E3B0_ONLINE(reg_info->info);
601 else
602 return false;
603}
604
605/******* Paged registers info selectors ********/
606static inline const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
607{
608 if (CHIP_IS_E2(bp))
609 return page_vals_e2;
610 else if (CHIP_IS_E3(bp))
611 return page_vals_e3;
612 else
613 return NULL;
614}
615
616static inline u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
617{
618 if (CHIP_IS_E2(bp))
619 return PAGE_MODE_VALUES_E2;
620 else if (CHIP_IS_E3(bp))
621 return PAGE_MODE_VALUES_E3;
622 else
623 return 0;
624}
625
626static inline const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
627{
628 if (CHIP_IS_E2(bp))
629 return page_write_regs_e2;
630 else if (CHIP_IS_E3(bp))
631 return page_write_regs_e3;
632 else
633 return NULL;
634}
635
636static inline u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
637{
638 if (CHIP_IS_E2(bp))
639 return PAGE_WRITE_REGS_E2;
640 else if (CHIP_IS_E3(bp))
641 return PAGE_WRITE_REGS_E3;
642 else
643 return 0;
644}
645
646static inline const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
647{
648 if (CHIP_IS_E2(bp))
649 return page_read_regs_e2;
650 else if (CHIP_IS_E3(bp))
651 return page_read_regs_e3;
652 else
653 return NULL;
654}
655
656static inline u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
657{
658 if (CHIP_IS_E2(bp))
659 return PAGE_READ_REGS_E2;
660 else if (CHIP_IS_E3(bp))
661 return PAGE_READ_REGS_E3;
662 else
663 return 0;
664}
665
666static inline int __bnx2x_get_regs_len(struct bnx2x *bp)
667{
668 int num_pages = __bnx2x_get_page_reg_num(bp);
669 int page_write_num = __bnx2x_get_page_write_num(bp);
670 const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
671 int page_read_num = __bnx2x_get_page_read_num(bp);
672 int regdump_len = 0;
673 int i, j, k;
674
675 for (i = 0; i < REGS_COUNT; i++)
676 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
677 regdump_len += reg_addrs[i].size;
678
679 for (i = 0; i < num_pages; i++)
680 for (j = 0; j < page_write_num; j++)
681 for (k = 0; k < page_read_num; k++)
682 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
683 regdump_len += page_read_addr[k].size;
684
685 return regdump_len;
686}
de0c62db
DK		 687
688static int bnx2x_get_regs_len(struct net_device *dev)
689{
690 struct bnx2x *bp = netdev_priv(dev);
691 int regdump_len = 0;
de0c62db 692
0fea29c1 693 regdump_len = __bnx2x_get_regs_len(bp);
de0c62db
DK		 694 regdump_len *= 4;
695 regdump_len += sizeof(struct dump_hdr);
696
697 return regdump_len;
698}
699
0fea29c1
VZ		 700/**
701 * bnx2x_read_pages_regs - read "paged" registers
702 *
703 * @bp device handle
704 * @p output buffer
705 *
706 * Reads "paged" memories: memories that may only be read by first writing to a
707 * specific address ("write address") and then reading from a specific address
708 * ("read address"). There may be more than one write address per "page" and
709 * more than one read address per write address.
710 */
711static inline void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
f2e0899f
DK		 712{
713 u32 i, j, k, n;
0fea29c1
VZ		 714 /* addresses of the paged registers */
715 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
716 /* number of paged registers */
717 int num_pages = __bnx2x_get_page_reg_num(bp);
718 /* write addresses */
719 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
720 /* number of write addresses */
721 int write_num = __bnx2x_get_page_write_num(bp);
722 /* read addresses info */
723 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
724 /* number of read addresses */
725 int read_num = __bnx2x_get_page_read_num(bp);
726
727 for (i = 0; i < num_pages; i++) {
728 for (j = 0; j < write_num; j++) {
729 REG_WR(bp, write_addr[j], page_addr[i]);
730 for (k = 0; k < read_num; k++)
731 if (bnx2x_is_reg_online(bp, &read_addr[k]))
f2e0899f 732 for (n = 0; n <
0fea29c1 733 read_addr[k].size; n++)
f2e0899f 734 *p++ = REG_RD(bp,
0fea29c1 735 read_addr[k].addr + n*4);
f2e0899f
DK		 736 }
737 }
738}
739
0fea29c1
VZ		 740static inline void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
741{
742 u32 i, j;
743
744 /* Read the regular registers */
745 for (i = 0; i < REGS_COUNT; i++)
746 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
747 for (j = 0; j < reg_addrs[i].size; j++)
748 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
749
750 /* Read "paged" registes */
751 bnx2x_read_pages_regs(bp, p);
752}
753
de0c62db
DK		 754static void bnx2x_get_regs(struct net_device *dev,
755 struct ethtool_regs *regs, void *_p)
756{
0fea29c1 757 u32 *p = _p;
de0c62db
DK		 758 struct bnx2x *bp = netdev_priv(dev);
759 struct dump_hdr dump_hdr = {0};
760
761 regs->version = 0;
762 memset(p, 0, regs->len);
763
764 if (!netif_running(bp->dev))
765 return;
766
4a33bc03
VZ		 767 /* Disable parity attentions as long as following dump may
768 * cause false alarms by reading never written registers. We
769 * will re-enable parity attentions right after the dump.
770 */
771 bnx2x_disable_blocks_parity(bp);
772
de0c62db
DK		 773 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
774 dump_hdr.dump_sign = dump_sign_all;
775 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
776 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
777 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
778 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
f2e0899f
DK		 779
780 if (CHIP_IS_E1(bp))
781 dump_hdr.info = RI_E1_ONLINE;
782 else if (CHIP_IS_E1H(bp))
783 dump_hdr.info = RI_E1H_ONLINE;
619c5cb6 784 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 785 dump_hdr.info = RI_E2_ONLINE |
786 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
de0c62db
DK		 787
788 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
789 p += dump_hdr.hdr_size + 1;
790
0fea29c1
VZ		 791 /* Actually read the registers */
792 __bnx2x_get_regs(bp, p);
793
4a33bc03
VZ		 794 /* Re-enable parity attentions */
795 bnx2x_clear_blocks_parity(bp);
c9ee9206 796 bnx2x_enable_blocks_parity(bp);
de0c62db
DK		 797}
798
de0c62db
DK		 799static void bnx2x_get_drvinfo(struct net_device *dev,
800 struct ethtool_drvinfo *info)
801{
802 struct bnx2x *bp = netdev_priv(dev);
803 u8 phy_fw_ver[PHY_FW_VER_LEN];
804
68aad78c
RJ		 805 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
806 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
de0c62db
DK		 807
808 phy_fw_ver[0] = '\0';
809 if (bp->port.pmf) {
810 bnx2x_acquire_phy_lock(bp);
811 bnx2x_get_ext_phy_fw_version(&bp->link_params,
812 (bp->state != BNX2X_STATE_CLOSED),
813 phy_fw_ver, PHY_FW_VER_LEN);
814 bnx2x_release_phy_lock(bp);
815 }
816
68aad78c 817 strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version));
de0c62db
DK		 818 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
819 "bc %d.%d.%d%s%s",
820 (bp->common.bc_ver & 0xff0000) >> 16,
821 (bp->common.bc_ver & 0xff00) >> 8,
822 (bp->common.bc_ver & 0xff),
823 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
68aad78c 824 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
de0c62db
DK		 825 info->n_stats = BNX2X_NUM_STATS;
826 info->testinfo_len = BNX2X_NUM_TESTS;
827 info->eedump_len = bp->common.flash_size;
828 info->regdump_len = bnx2x_get_regs_len(dev);
829}
830
831static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
832{
833 struct bnx2x *bp = netdev_priv(dev);
834
835 if (bp->flags & NO_WOL_FLAG) {
836 wol->supported = 0;
837 wol->wolopts = 0;
838 } else {
839 wol->supported = WAKE_MAGIC;
840 if (bp->wol)
841 wol->wolopts = WAKE_MAGIC;
842 else
843 wol->wolopts = 0;
844 }
845 memset(&wol->sopass, 0, sizeof(wol->sopass));
846}
847
848static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
849{
850 struct bnx2x *bp = netdev_priv(dev);
851
852 if (wol->wolopts & ~WAKE_MAGIC)
853 return -EINVAL;
854
855 if (wol->wolopts & WAKE_MAGIC) {
856 if (bp->flags & NO_WOL_FLAG)
857 return -EINVAL;
858
859 bp->wol = 1;
860 } else
861 bp->wol = 0;
862
863 return 0;
864}
865
866static u32 bnx2x_get_msglevel(struct net_device *dev)
867{
868 struct bnx2x *bp = netdev_priv(dev);
869
870 return bp->msg_enable;
871}
872
873static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
874{
875 struct bnx2x *bp = netdev_priv(dev);
876
7a25cc73
DK		 877 if (capable(CAP_NET_ADMIN)) {
878 /* dump MCP trace */
879 if (level & BNX2X_MSG_MCP)
880 bnx2x_fw_dump_lvl(bp, KERN_INFO);
de0c62db 881 bp->msg_enable = level;
7a25cc73 882 }
de0c62db
DK		 883}
884
885static int bnx2x_nway_reset(struct net_device *dev)
886{
887 struct bnx2x *bp = netdev_priv(dev);
888
889 if (!bp->port.pmf)
890 return 0;
891
892 if (netif_running(dev)) {
893 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
894 bnx2x_link_set(bp);
895 }
896
897 return 0;
898}
899
900static u32 bnx2x_get_link(struct net_device *dev)
901{
902 struct bnx2x *bp = netdev_priv(dev);
903
f2e0899f 904 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 905 return 0;
906
907 return bp->link_vars.link_up;
908}
909
910static int bnx2x_get_eeprom_len(struct net_device *dev)
911{
912 struct bnx2x *bp = netdev_priv(dev);
913
914 return bp->common.flash_size;
915}
916
f16da43b
AE		 917/* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
918 * we done things the other way around, if two pfs from the same port would
919 * attempt to access nvram at the same time, we could run into a scenario such
920 * as:
921 * pf A takes the port lock.
922 * pf B succeeds in taking the same lock since they are from the same port.
923 * pf A takes the per pf misc lock. Performs eeprom access.
924 * pf A finishes. Unlocks the per pf misc lock.
925 * Pf B takes the lock and proceeds to perform it's own access.
926 * pf A unlocks the per port lock, while pf B is still working (!).
927 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
928 * acess corrupted by pf B).*
929 */
de0c62db
DK		 930static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
931{
932 int port = BP_PORT(bp);
933 int count, i;
f16da43b
AE		 934 u32 val;
935
936 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
937 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 938
939 /* adjust timeout for emulation/FPGA */
754a2f52 940 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 941 if (CHIP_REV_IS_SLOW(bp))
942 count *= 100;
943
944 /* request access to nvram interface */
945 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
946 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
947
948 for (i = 0; i < count*10; i++) {
949 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
950 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
951 break;
952
953 udelay(5);
954 }
955
956 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
957 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
958 return -EBUSY;
959 }
960
961 return 0;
962}
963
964static int bnx2x_release_nvram_lock(struct bnx2x *bp)
965{
966 int port = BP_PORT(bp);
967 int count, i;
f16da43b 968 u32 val;
de0c62db
DK		 969
970 /* adjust timeout for emulation/FPGA */
754a2f52 971 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 972 if (CHIP_REV_IS_SLOW(bp))
973 count *= 100;
974
975 /* relinquish nvram interface */
976 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
977 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
978
979 for (i = 0; i < count*10; i++) {
980 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
981 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
982 break;
983
984 udelay(5);
985 }
986
987 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
988 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
989 return -EBUSY;
990 }
991
f16da43b
AE		 992 /* release HW lock: protect against other PFs in PF Direct Assignment */
993 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 994 return 0;
995}
996
997static void bnx2x_enable_nvram_access(struct bnx2x *bp)
998{
999 u32 val;
1000
1001 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1002
1003 /* enable both bits, even on read */
1004 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1005 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1006 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1007}
1008
1009static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1010{
1011 u32 val;
1012
1013 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1014
1015 /* disable both bits, even after read */
1016 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1017 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1018 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1019}
1020
1021static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1022 u32 cmd_flags)
1023{
1024 int count, i, rc;
1025 u32 val;
1026
1027 /* build the command word */
1028 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1029
1030 /* need to clear DONE bit separately */
1031 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1032
1033 /* address of the NVRAM to read from */
1034 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1035 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1036
1037 /* issue a read command */
1038 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1039
1040 /* adjust timeout for emulation/FPGA */
754a2f52 1041 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1042 if (CHIP_REV_IS_SLOW(bp))
1043 count *= 100;
1044
1045 /* wait for completion */
1046 *ret_val = 0;
1047 rc = -EBUSY;
1048 for (i = 0; i < count; i++) {
1049 udelay(5);
1050 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1051
1052 if (val & MCPR_NVM_COMMAND_DONE) {
1053 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1054 /* we read nvram data in cpu order
1055 * but ethtool sees it as an array of bytes
1056 * converting to big-endian will do the work */
1057 *ret_val = cpu_to_be32(val);
1058 rc = 0;
1059 break;
1060 }
1061 }
1062
1063 return rc;
1064}
1065
1066static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1067 int buf_size)
1068{
1069 int rc;
1070 u32 cmd_flags;
1071 __be32 val;
1072
1073 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1074 DP(BNX2X_MSG_NVM,
1075 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1076 offset, buf_size);
1077 return -EINVAL;
1078 }
1079
1080 if (offset + buf_size > bp->common.flash_size) {
1081 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1082 " buf_size (0x%x) > flash_size (0x%x)\n",
1083 offset, buf_size, bp->common.flash_size);
1084 return -EINVAL;
1085 }
1086
1087 /* request access to nvram interface */
1088 rc = bnx2x_acquire_nvram_lock(bp);
1089 if (rc)
1090 return rc;
1091
1092 /* enable access to nvram interface */
1093 bnx2x_enable_nvram_access(bp);
1094
1095 /* read the first word(s) */
1096 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1097 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1098 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1099 memcpy(ret_buf, &val, 4);
1100
1101 /* advance to the next dword */
1102 offset += sizeof(u32);
1103 ret_buf += sizeof(u32);
1104 buf_size -= sizeof(u32);
1105 cmd_flags = 0;
1106 }
1107
1108 if (rc == 0) {
1109 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1110 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1111 memcpy(ret_buf, &val, 4);
1112 }
1113
1114 /* disable access to nvram interface */
1115 bnx2x_disable_nvram_access(bp);
1116 bnx2x_release_nvram_lock(bp);
1117
1118 return rc;
1119}
1120
1121static int bnx2x_get_eeprom(struct net_device *dev,
1122 struct ethtool_eeprom *eeprom, u8 *eebuf)
1123{
1124 struct bnx2x *bp = netdev_priv(dev);
1125 int rc;
1126
1127 if (!netif_running(dev))
1128 return -EAGAIN;
1129
1130 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1131 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1132 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1133 eeprom->len, eeprom->len);
1134
1135 /* parameters already validated in ethtool_get_eeprom */
1136
1137 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1138
1139 return rc;
1140}
1141
1142static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1143 u32 cmd_flags)
1144{
1145 int count, i, rc;
1146
1147 /* build the command word */
1148 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1149
1150 /* need to clear DONE bit separately */
1151 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1152
1153 /* write the data */
1154 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1155
1156 /* address of the NVRAM to write to */
1157 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1158 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1159
1160 /* issue the write command */
1161 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1162
1163 /* adjust timeout for emulation/FPGA */
754a2f52 1164 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1165 if (CHIP_REV_IS_SLOW(bp))
1166 count *= 100;
1167
1168 /* wait for completion */
1169 rc = -EBUSY;
1170 for (i = 0; i < count; i++) {
1171 udelay(5);
1172 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1173 if (val & MCPR_NVM_COMMAND_DONE) {
1174 rc = 0;
1175 break;
1176 }
1177 }
1178
1179 return rc;
1180}
1181
1182#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1183
1184static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1185 int buf_size)
1186{
1187 int rc;
1188 u32 cmd_flags;
1189 u32 align_offset;
1190 __be32 val;
1191
1192 if (offset + buf_size > bp->common.flash_size) {
1193 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1194 " buf_size (0x%x) > flash_size (0x%x)\n",
1195 offset, buf_size, bp->common.flash_size);
1196 return -EINVAL;
1197 }
1198
1199 /* request access to nvram interface */
1200 rc = bnx2x_acquire_nvram_lock(bp);
1201 if (rc)
1202 return rc;
1203
1204 /* enable access to nvram interface */
1205 bnx2x_enable_nvram_access(bp);
1206
1207 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1208 align_offset = (offset & ~0x03);
1209 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1210
1211 if (rc == 0) {
1212 val &= ~(0xff << BYTE_OFFSET(offset));
1213 val |= (*data_buf << BYTE_OFFSET(offset));
1214
1215 /* nvram data is returned as an array of bytes
1216 * convert it back to cpu order */
1217 val = be32_to_cpu(val);
1218
1219 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1220 cmd_flags);
1221 }
1222
1223 /* disable access to nvram interface */
1224 bnx2x_disable_nvram_access(bp);
1225 bnx2x_release_nvram_lock(bp);
1226
1227 return rc;
1228}
1229
1230static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1231 int buf_size)
1232{
1233 int rc;
1234 u32 cmd_flags;
1235 u32 val;
1236 u32 written_so_far;
1237
1238 if (buf_size == 1) /* ethtool */
1239 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1240
1241 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1242 DP(BNX2X_MSG_NVM,
1243 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1244 offset, buf_size);
1245 return -EINVAL;
1246 }
1247
1248 if (offset + buf_size > bp->common.flash_size) {
1249 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1250 " buf_size (0x%x) > flash_size (0x%x)\n",
1251 offset, buf_size, bp->common.flash_size);
1252 return -EINVAL;
1253 }
1254
1255 /* request access to nvram interface */
1256 rc = bnx2x_acquire_nvram_lock(bp);
1257 if (rc)
1258 return rc;
1259
1260 /* enable access to nvram interface */
1261 bnx2x_enable_nvram_access(bp);
1262
1263 written_so_far = 0;
1264 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1265 while ((written_so_far < buf_size) && (rc == 0)) {
1266 if (written_so_far == (buf_size - sizeof(u32)))
1267 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1268 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db 1269 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1270 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db
DK		 1271 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1272
1273 memcpy(&val, data_buf, 4);
1274
1275 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1276
1277 /* advance to the next dword */
1278 offset += sizeof(u32);
1279 data_buf += sizeof(u32);
1280 written_so_far += sizeof(u32);
1281 cmd_flags = 0;
1282 }
1283
1284 /* disable access to nvram interface */
1285 bnx2x_disable_nvram_access(bp);
1286 bnx2x_release_nvram_lock(bp);
1287
1288 return rc;
1289}
1290
1291static int bnx2x_set_eeprom(struct net_device *dev,
1292 struct ethtool_eeprom *eeprom, u8 *eebuf)
1293{
1294 struct bnx2x *bp = netdev_priv(dev);
1295 int port = BP_PORT(bp);
1296 int rc = 0;
e10bc84d 1297 u32 ext_phy_config;
de0c62db
DK		 1298 if (!netif_running(dev))
1299 return -EAGAIN;
1300
1301 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1302 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1303 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1304 eeprom->len, eeprom->len);
1305
1306 /* parameters already validated in ethtool_set_eeprom */
1307
1308 /* PHY eeprom can be accessed only by the PMF */
1309 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1310 !bp->port.pmf)
1311 return -EINVAL;
1312
e10bc84d
YR		 1313 ext_phy_config =
1314 SHMEM_RD(bp,
1315 dev_info.port_hw_config[port].external_phy_config);
1316
de0c62db
DK		 1317 if (eeprom->magic == 0x50485950) {
1318 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1319 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1320
1321 bnx2x_acquire_phy_lock(bp);
1322 rc |= bnx2x_link_reset(&bp->link_params,
1323 &bp->link_vars, 0);
e10bc84d 1324 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1325 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1326 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1327 MISC_REGISTERS_GPIO_HIGH, port);
1328 bnx2x_release_phy_lock(bp);
1329 bnx2x_link_report(bp);
1330
1331 } else if (eeprom->magic == 0x50485952) {
1332 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1333 if (bp->state == BNX2X_STATE_OPEN) {
1334 bnx2x_acquire_phy_lock(bp);
1335 rc |= bnx2x_link_reset(&bp->link_params,
1336 &bp->link_vars, 1);
1337
1338 rc |= bnx2x_phy_init(&bp->link_params,
1339 &bp->link_vars);
1340 bnx2x_release_phy_lock(bp);
1341 bnx2x_calc_fc_adv(bp);
1342 }
1343 } else if (eeprom->magic == 0x53985943) {
1344 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1345 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1346 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1347
1348 /* DSP Remove Download Mode */
1349 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1350 MISC_REGISTERS_GPIO_LOW, port);
1351
1352 bnx2x_acquire_phy_lock(bp);
1353
e10bc84d
YR		 1354 bnx2x_sfx7101_sp_sw_reset(bp,
1355 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1356
1357 /* wait 0.5 sec to allow it to run */
1358 msleep(500);
1359 bnx2x_ext_phy_hw_reset(bp, port);
1360 msleep(500);
1361 bnx2x_release_phy_lock(bp);
1362 }
1363 } else
1364 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1365
1366 return rc;
1367}
f85582f8 1368
de0c62db
DK		 1369static int bnx2x_get_coalesce(struct net_device *dev,
1370 struct ethtool_coalesce *coal)
1371{
1372 struct bnx2x *bp = netdev_priv(dev);
1373
1374 memset(coal, 0, sizeof(struct ethtool_coalesce));
1375
1376 coal->rx_coalesce_usecs = bp->rx_ticks;
1377 coal->tx_coalesce_usecs = bp->tx_ticks;
1378
1379 return 0;
1380}
1381
1382static int bnx2x_set_coalesce(struct net_device *dev,
1383 struct ethtool_coalesce *coal)
1384{
1385 struct bnx2x *bp = netdev_priv(dev);
1386
1387 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1388 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1389 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1390
1391 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1392 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1393 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1394
1395 if (netif_running(dev))
1396 bnx2x_update_coalesce(bp);
1397
1398 return 0;
1399}
1400
1401static void bnx2x_get_ringparam(struct net_device *dev,
1402 struct ethtool_ringparam *ering)
1403{
1404 struct bnx2x *bp = netdev_priv(dev);
1405
1406 ering->rx_max_pending = MAX_RX_AVAIL;
de0c62db 1407
25141580
DK		 1408 if (bp->rx_ring_size)
1409 ering->rx_pending = bp->rx_ring_size;
1410 else
c2188952 1411 ering->rx_pending = MAX_RX_AVAIL;
25141580 1412
de0c62db
DK		 1413 ering->tx_max_pending = MAX_TX_AVAIL;
1414 ering->tx_pending = bp->tx_ring_size;
1415}
1416
1417static int bnx2x_set_ringparam(struct net_device *dev,
1418 struct ethtool_ringparam *ering)
1419{
1420 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 1421
1422 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
7a752993
AE		 1423 netdev_err(dev, "Handling parity error recovery. "
1424 "Try again later\n");
de0c62db
DK		 1425 return -EAGAIN;
1426 }
1427
1428 if ((ering->rx_pending > MAX_RX_AVAIL) ||
b3b83c3f
DK		 1429 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1430 MIN_RX_SIZE_TPA)) ||
de0c62db
DK		 1431 (ering->tx_pending > MAX_TX_AVAIL) ||
1432 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1433 return -EINVAL;
1434
1435 bp->rx_ring_size = ering->rx_pending;
1436 bp->tx_ring_size = ering->tx_pending;
1437
a9fccec7 1438 return bnx2x_reload_if_running(dev);
de0c62db
DK		 1439}
1440
1441static void bnx2x_get_pauseparam(struct net_device *dev,
1442 struct ethtool_pauseparam *epause)
1443{
1444 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1445 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
9e7e8399
MY		 1446 int cfg_reg;
1447
a22f0788
YR		 1448 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1449 BNX2X_FLOW_CTRL_AUTO);
de0c62db 1450
9e7e8399
MY		 1451 if (!epause->autoneg)
1452 cfg_reg = bp->link_vars.flow_ctrl;
1453 else
1454 cfg_reg = bp->link_params.req_fc_auto_adv;
1455
1456 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
de0c62db 1457 BNX2X_FLOW_CTRL_RX);
9e7e8399 1458 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
de0c62db
DK		 1459 BNX2X_FLOW_CTRL_TX);
1460
1461 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
f1deab50 1462 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1463 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1464}
1465
1466static int bnx2x_set_pauseparam(struct net_device *dev,
1467 struct ethtool_pauseparam *epause)
1468{
1469 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1470 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1471 if (IS_MF(bp))
de0c62db
DK		 1472 return 0;
1473
1474 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
f1deab50 1475 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1476 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1477
a22f0788 1478 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1479
1480 if (epause->rx_pause)
a22f0788 1481 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1482
1483 if (epause->tx_pause)
a22f0788 1484 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1485
a22f0788
YR		 1486 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1487 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1488
1489 if (epause->autoneg) {
a22f0788 1490 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
de0c62db
DK		 1491 DP(NETIF_MSG_LINK, "autoneg not supported\n");
1492 return -EINVAL;
1493 }
1494
a22f0788
YR		 1495 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1496 bp->link_params.req_flow_ctrl[cfg_idx] =
1497 BNX2X_FLOW_CTRL_AUTO;
1498 }
de0c62db
DK		 1499 }
1500
1501 DP(NETIF_MSG_LINK,
a22f0788 1502 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1503
1504 if (netif_running(dev)) {
1505 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1506 bnx2x_link_set(bp);
1507 }
1508
1509 return 0;
1510}
1511
de0c62db
DK		 1512static const struct {
1513 char string[ETH_GSTRING_LEN];
1514} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1515 { "register_test (offline)" },
1516 { "memory_test (offline)" },
1517 { "loopback_test (offline)" },
1518 { "nvram_test (online)" },
1519 { "interrupt_test (online)" },
1520 { "link_test (online)" },
1521 { "idle check (online)" }
1522};
1523
619c5cb6
VZ		 1524enum {
1525 BNX2X_CHIP_E1_OFST = 0,
1526 BNX2X_CHIP_E1H_OFST,
1527 BNX2X_CHIP_E2_OFST,
1528 BNX2X_CHIP_E3_OFST,
1529 BNX2X_CHIP_E3B0_OFST,
1530 BNX2X_CHIP_MAX_OFST
1531};
1532
1533#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1534#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1535#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1536#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1537#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1538
1539#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1540#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1541
de0c62db
DK		 1542static int bnx2x_test_registers(struct bnx2x *bp)
1543{
1544 int idx, i, rc = -ENODEV;
619c5cb6 1545 u32 wr_val = 0, hw;
de0c62db
DK		 1546 int port = BP_PORT(bp);
1547 static const struct {
619c5cb6 1548 u32 hw;
de0c62db
DK		 1549 u32 offset0;
1550 u32 offset1;
1551 u32 mask;
1552 } reg_tbl[] = {
619c5cb6
VZ		 1553/* 0 */ { BNX2X_CHIP_MASK_ALL,
1554 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1555 { BNX2X_CHIP_MASK_ALL,
1556 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1557 { BNX2X_CHIP_MASK_E1X,
1558 HC_REG_AGG_INT_0, 4, 0x000003ff },
1559 { BNX2X_CHIP_MASK_ALL,
1560 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1561 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1562 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1563 { BNX2X_CHIP_MASK_E3B0,
1564 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
1565 { BNX2X_CHIP_MASK_ALL,
1566 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1567 { BNX2X_CHIP_MASK_ALL,
1568 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1569 { BNX2X_CHIP_MASK_ALL,
1570 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1571 { BNX2X_CHIP_MASK_ALL,
1572 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1573/* 10 */ { BNX2X_CHIP_MASK_ALL,
1574 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1575 { BNX2X_CHIP_MASK_ALL,
1576 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1577 { BNX2X_CHIP_MASK_ALL,
1578 QM_REG_CONNNUM_0, 4, 0x000fffff },
1579 { BNX2X_CHIP_MASK_ALL,
1580 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1581 { BNX2X_CHIP_MASK_ALL,
1582 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1583 { BNX2X_CHIP_MASK_ALL,
1584 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1585 { BNX2X_CHIP_MASK_ALL,
1586 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1587 { BNX2X_CHIP_MASK_ALL,
1588 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1589 { BNX2X_CHIP_MASK_ALL,
1590 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1591 { BNX2X_CHIP_MASK_ALL,
1592 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1593/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1594 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1595 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1596 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1597 { BNX2X_CHIP_MASK_ALL,
1598 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1599 { BNX2X_CHIP_MASK_ALL,
1600 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1601 { BNX2X_CHIP_MASK_ALL,
1602 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1603 { BNX2X_CHIP_MASK_ALL,
1604 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1605 { BNX2X_CHIP_MASK_ALL,
1606 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1607 { BNX2X_CHIP_MASK_ALL,
1608 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1609 { BNX2X_CHIP_MASK_ALL,
1610 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1611 { BNX2X_CHIP_MASK_ALL,
1612 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1613/* 30 */ { BNX2X_CHIP_MASK_ALL,
1614 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1615 { BNX2X_CHIP_MASK_ALL,
1616 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1617 { BNX2X_CHIP_MASK_ALL,
1618 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1619 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1620 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1621 { BNX2X_CHIP_MASK_ALL,
1622 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1623 { BNX2X_CHIP_MASK_ALL,
1624 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1625 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1626 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1627 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1628 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1629
1630 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
de0c62db
DK		 1631 };
1632
1633 if (!netif_running(bp->dev))
1634 return rc;
1635
619c5cb6
VZ		 1636 if (CHIP_IS_E1(bp))
1637 hw = BNX2X_CHIP_MASK_E1;
1638 else if (CHIP_IS_E1H(bp))
1639 hw = BNX2X_CHIP_MASK_E1H;
1640 else if (CHIP_IS_E2(bp))
1641 hw = BNX2X_CHIP_MASK_E2;
1642 else if (CHIP_IS_E3B0(bp))
1643 hw = BNX2X_CHIP_MASK_E3B0;
1644 else /* e3 A0 */
1645 hw = BNX2X_CHIP_MASK_E3;
1646
de0c62db
DK		 1647 /* Repeat the test twice:
1648 First by writing 0x00000000, second by writing 0xffffffff */
1649 for (idx = 0; idx < 2; idx++) {
1650
1651 switch (idx) {
1652 case 0:
1653 wr_val = 0;
1654 break;
1655 case 1:
1656 wr_val = 0xffffffff;
1657 break;
1658 }
1659
1660 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1661 u32 offset, mask, save_val, val;
619c5cb6 1662 if (!(hw & reg_tbl[i].hw))
f2e0899f 1663 continue;
de0c62db
DK		 1664
1665 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1666 mask = reg_tbl[i].mask;
1667
1668 save_val = REG_RD(bp, offset);
1669
ec6ba945 1670 REG_WR(bp, offset, wr_val & mask);
f85582f8 1671
de0c62db
DK		 1672 val = REG_RD(bp, offset);
1673
1674 /* Restore the original register's value */
1675 REG_WR(bp, offset, save_val);
1676
1677 /* verify value is as expected */
1678 if ((val & mask) != (wr_val & mask)) {
619c5cb6 1679 DP(NETIF_MSG_HW,
de0c62db
DK		 1680 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1681 offset, val, wr_val, mask);
1682 goto test_reg_exit;
1683 }
1684 }
1685 }
1686
1687 rc = 0;
1688
1689test_reg_exit:
1690 return rc;
1691}
1692
1693static int bnx2x_test_memory(struct bnx2x *bp)
1694{
1695 int i, j, rc = -ENODEV;
619c5cb6 1696 u32 val, index;
de0c62db
DK		 1697 static const struct {
1698 u32 offset;
1699 int size;
1700 } mem_tbl[] = {
1701 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1702 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1703 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1704 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1705 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1706 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1707 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1708
1709 { 0xffffffff, 0 }
1710 };
619c5cb6 1711
de0c62db
DK		 1712 static const struct {
1713 char *name;
1714 u32 offset;
619c5cb6 1715 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
de0c62db 1716 } prty_tbl[] = {
619c5cb6
VZ		 1717 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
1718 {0x3ffc0, 0, 0, 0} },
1719 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
1720 {0x2, 0x2, 0, 0} },
1721 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1722 {0, 0, 0, 0} },
1723 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
1724 {0x3ffc0, 0, 0, 0} },
1725 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
1726 {0x3ffc0, 0, 0, 0} },
1727 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
1728 {0x3ffc1, 0, 0, 0} },
1729
1730 { NULL, 0xffffffff, {0, 0, 0, 0} }
de0c62db
DK		 1731 };
1732
1733 if (!netif_running(bp->dev))
1734 return rc;
1735
619c5cb6
VZ		 1736 if (CHIP_IS_E1(bp))
1737 index = BNX2X_CHIP_E1_OFST;
1738 else if (CHIP_IS_E1H(bp))
1739 index = BNX2X_CHIP_E1H_OFST;
1740 else if (CHIP_IS_E2(bp))
1741 index = BNX2X_CHIP_E2_OFST;
1742 else /* e3 */
1743 index = BNX2X_CHIP_E3_OFST;
1744
f2e0899f
DK		 1745 /* pre-Check the parity status */
1746 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1747 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1748 if (val & ~(prty_tbl[i].hw_mask[index])) {
f2e0899f
DK		 1749 DP(NETIF_MSG_HW,
1750 "%s is 0x%x\n", prty_tbl[i].name, val);
1751 goto test_mem_exit;
1752 }
1753 }
1754
de0c62db
DK		 1755 /* Go through all the memories */
1756 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1757 for (j = 0; j < mem_tbl[i].size; j++)
1758 REG_RD(bp, mem_tbl[i].offset + j*4);
1759
1760 /* Check the parity status */
1761 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1762 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1763 if (val & ~(prty_tbl[i].hw_mask[index])) {
de0c62db
DK		 1764 DP(NETIF_MSG_HW,
1765 "%s is 0x%x\n", prty_tbl[i].name, val);
1766 goto test_mem_exit;
1767 }
1768 }
1769
1770 rc = 0;
1771
1772test_mem_exit:
1773 return rc;
1774}
1775
a22f0788 1776static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 1777{
f2e0899f 1778 int cnt = 1400;
de0c62db 1779
619c5cb6 1780 if (link_up) {
a22f0788 1781 while (bnx2x_link_test(bp, is_serdes) && cnt--)
619c5cb6
VZ		 1782 msleep(20);
1783
1784 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
1785 DP(NETIF_MSG_LINK, "Timeout waiting for link up\n");
1786 }
de0c62db
DK		 1787}
1788
619c5cb6 1789static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
de0c62db
DK		 1790{
1791 unsigned int pkt_size, num_pkts, i;
1792 struct sk_buff *skb;
1793 unsigned char *packet;
1794 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1795 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
6383c0b3 1796 struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0];
de0c62db
DK		 1797 u16 tx_start_idx, tx_idx;
1798 u16 rx_start_idx, rx_idx;
b0700b1e 1799 u16 pkt_prod, bd_prod;
de0c62db
DK		 1800 struct sw_tx_bd *tx_buf;
1801 struct eth_tx_start_bd *tx_start_bd;
f2e0899f
DK		 1802 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1803 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
de0c62db
DK		 1804 dma_addr_t mapping;
1805 union eth_rx_cqe *cqe;
619c5cb6 1806 u8 cqe_fp_flags, cqe_fp_type;
de0c62db
DK		 1807 struct sw_rx_bd *rx_buf;
1808 u16 len;
1809 int rc = -ENODEV;
e52fcb24 1810 u8 *data;
73dbb5e1 1811 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txdata->txq_index);
de0c62db
DK		 1812
1813 /* check the loopback mode */
1814 switch (loopback_mode) {
1815 case BNX2X_PHY_LOOPBACK:
de6eae1f 1816 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
de0c62db
DK		 1817 return -EINVAL;
1818 break;
1819 case BNX2X_MAC_LOOPBACK:
32911333
YR		 1820 if (CHIP_IS_E3(bp)) {
1821 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1822 if (bp->port.supported[cfg_idx] &
1823 (SUPPORTED_10000baseT_Full |
1824 SUPPORTED_20000baseMLD2_Full |
1825 SUPPORTED_20000baseKR2_Full))
1826 bp->link_params.loopback_mode = LOOPBACK_XMAC;
1827 else
1828 bp->link_params.loopback_mode = LOOPBACK_UMAC;
1829 } else
1830 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1831
de0c62db
DK		 1832 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1833 break;
1834 default:
1835 return -EINVAL;
1836 }
1837
1838 /* prepare the loopback packet */
1839 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1840 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 1841 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db
DK		 1842 if (!skb) {
1843 rc = -ENOMEM;
1844 goto test_loopback_exit;
1845 }
1846 packet = skb_put(skb, pkt_size);
1847 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1848 memset(packet + ETH_ALEN, 0, ETH_ALEN);
1849 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1850 for (i = ETH_HLEN; i < pkt_size; i++)
1851 packet[i] = (unsigned char) (i & 0xff);
619c5cb6
VZ		 1852 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1853 skb_headlen(skb), DMA_TO_DEVICE);
1854 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1855 rc = -ENOMEM;
1856 dev_kfree_skb(skb);
1857 BNX2X_ERR("Unable to map SKB\n");
1858 goto test_loopback_exit;
1859 }
de0c62db
DK		 1860
1861 /* send the loopback packet */
1862 num_pkts = 0;
6383c0b3 1863 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 1864 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1865
73dbb5e1
DK		 1866 netdev_tx_sent_queue(txq, skb->len);
1867
6383c0b3
AE		 1868 pkt_prod = txdata->tx_pkt_prod++;
1869 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
1870 tx_buf->first_bd = txdata->tx_bd_prod;
de0c62db
DK		 1871 tx_buf->skb = skb;
1872 tx_buf->flags = 0;
1873
6383c0b3
AE		 1874 bd_prod = TX_BD(txdata->tx_bd_prod);
1875 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
de0c62db
DK		 1876 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1877 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1878 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1879 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 1880 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 1881 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 1882 SET_FLAG(tx_start_bd->general_data,
1883 ETH_TX_START_BD_ETH_ADDR_TYPE,
1884 UNICAST_ADDRESS);
1885 SET_FLAG(tx_start_bd->general_data,
1886 ETH_TX_START_BD_HDR_NBDS,
1887 1);
de0c62db
DK		 1888
1889 /* turn on parsing and get a BD */
1890 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 1891
6383c0b3
AE		 1892 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
1893 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
de0c62db 1894
f2e0899f 1895 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
523224a3 1896 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
de0c62db
DK		 1897
1898 wmb();
1899
6383c0b3 1900 txdata->tx_db.data.prod += 2;
de0c62db 1901 barrier();
6383c0b3 1902 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
de0c62db
DK		 1903
1904 mmiowb();
619c5cb6 1905 barrier();
de0c62db
DK		 1906
1907 num_pkts++;
6383c0b3 1908 txdata->tx_bd_prod += 2; /* start + pbd */
de0c62db
DK		 1909
1910 udelay(100);
1911
6383c0b3 1912 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 1913 if (tx_idx != tx_start_idx + num_pkts)
1914 goto test_loopback_exit;
1915
f2e0899f
DK		 1916 /* Unlike HC IGU won't generate an interrupt for status block
1917 * updates that have been performed while interrupts were
1918 * disabled.
1919 */
e1210d12
ED		 1920 if (bp->common.int_block == INT_BLOCK_IGU) {
1921 /* Disable local BHes to prevent a dead-lock situation between
1922 * sch_direct_xmit() and bnx2x_run_loopback() (calling
1923 * bnx2x_tx_int()), as both are taking netif_tx_lock().
1924 */
1925 local_bh_disable();
6383c0b3 1926 bnx2x_tx_int(bp, txdata);
e1210d12
ED		 1927 local_bh_enable();
1928 }
f2e0899f 1929
de0c62db
DK		 1930 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1931 if (rx_idx != rx_start_idx + num_pkts)
1932 goto test_loopback_exit;
1933
b0700b1e 1934 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
de0c62db 1935 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
619c5cb6
VZ		 1936 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1937 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
de0c62db
DK		 1938 goto test_loopback_rx_exit;
1939
1940 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1941 if (len != pkt_size)
1942 goto test_loopback_rx_exit;
1943
1944 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
9924cafc 1945 dma_sync_single_for_cpu(&bp->pdev->dev,
619c5cb6
VZ		 1946 dma_unmap_addr(rx_buf, mapping),
1947 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
e52fcb24 1948 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
de0c62db 1949 for (i = ETH_HLEN; i < pkt_size; i++)
e52fcb24 1950 if (*(data + i) != (unsigned char) (i & 0xff))
de0c62db
DK		 1951 goto test_loopback_rx_exit;
1952
1953 rc = 0;
1954
1955test_loopback_rx_exit:
1956
1957 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1958 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1959 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1960 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1961
1962 /* Update producers */
1963 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1964 fp_rx->rx_sge_prod);
1965
1966test_loopback_exit:
1967 bp->link_params.loopback_mode = LOOPBACK_NONE;
1968
1969 return rc;
1970}
1971
619c5cb6 1972static int bnx2x_test_loopback(struct bnx2x *bp)
de0c62db
DK		 1973{
1974 int rc = 0, res;
1975
1976 if (BP_NOMCP(bp))
1977 return rc;
1978
1979 if (!netif_running(bp->dev))
1980 return BNX2X_LOOPBACK_FAILED;
1981
1982 bnx2x_netif_stop(bp, 1);
1983 bnx2x_acquire_phy_lock(bp);
1984
619c5cb6 1985 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
de0c62db
DK		 1986 if (res) {
1987 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
1988 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1989 }
1990
619c5cb6 1991 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
de0c62db
DK		 1992 if (res) {
1993 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
1994 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1995 }
1996
1997 bnx2x_release_phy_lock(bp);
1998 bnx2x_netif_start(bp);
1999
2000 return rc;
2001}
2002
2003#define CRC32_RESIDUAL 0xdebb20e3
2004
2005static int bnx2x_test_nvram(struct bnx2x *bp)
2006{
2007 static const struct {
2008 int offset;
2009 int size;
2010 } nvram_tbl[] = {
2011 { 0, 0x14 }, /* bootstrap */
2012 { 0x14, 0xec }, /* dir */
2013 { 0x100, 0x350 }, /* manuf_info */
2014 { 0x450, 0xf0 }, /* feature_info */
2015 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 2016 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 2017 { 0, 0 }
2018 };
afa13b4b
MY		 2019 __be32 *buf;
2020 u8 *data;
de0c62db
DK		 2021 int i, rc;
2022 u32 magic, crc;
2023
2024 if (BP_NOMCP(bp))
2025 return 0;
2026
afa13b4b
MY		 2027 buf = kmalloc(0x350, GFP_KERNEL);
2028 if (!buf) {
2029 DP(NETIF_MSG_PROBE, "kmalloc failed\n");
2030 rc = -ENOMEM;
2031 goto test_nvram_exit;
2032 }
2033 data = (u8 *)buf;
2034
de0c62db
DK		 2035 rc = bnx2x_nvram_read(bp, 0, data, 4);
2036 if (rc) {
2037 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
2038 goto test_nvram_exit;
2039 }
2040
2041 magic = be32_to_cpu(buf[0]);
2042 if (magic != 0x669955aa) {
2043 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
2044 rc = -ENODEV;
2045 goto test_nvram_exit;
2046 }
2047
2048 for (i = 0; nvram_tbl[i].size; i++) {
2049
2050 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2051 nvram_tbl[i].size);
2052 if (rc) {
2053 DP(NETIF_MSG_PROBE,
2054 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2055 goto test_nvram_exit;
2056 }
2057
2058 crc = ether_crc_le(nvram_tbl[i].size, data);
2059 if (crc != CRC32_RESIDUAL) {
2060 DP(NETIF_MSG_PROBE,
2061 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
2062 rc = -ENODEV;
2063 goto test_nvram_exit;
2064 }
2065 }
2066
2067test_nvram_exit:
afa13b4b 2068 kfree(buf);
de0c62db
DK		 2069 return rc;
2070}
2071
619c5cb6 2072/* Send an EMPTY ramrod on the first queue */
de0c62db
DK		 2073static int bnx2x_test_intr(struct bnx2x *bp)
2074{
619c5cb6 2075 struct bnx2x_queue_state_params params = {0};
de0c62db
DK		 2076
2077 if (!netif_running(bp->dev))
2078 return -ENODEV;
2079
619c5cb6
VZ		 2080 params.q_obj = &bp->fp->q_obj;
2081 params.cmd = BNX2X_Q_CMD_EMPTY;
de0c62db 2082
619c5cb6
VZ		 2083 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2084
2085 return bnx2x_queue_state_change(bp, &params);
de0c62db
DK		 2086}
2087
2088static void bnx2x_self_test(struct net_device *dev,
2089 struct ethtool_test *etest, u64 *buf)
2090{
2091 struct bnx2x *bp = netdev_priv(dev);
a22f0788 2092 u8 is_serdes;
de0c62db 2093 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
7a752993
AE		 2094 netdev_err(bp->dev, "Handling parity error recovery. "
2095 "Try again later\n");
de0c62db
DK		 2096 etest->flags |= ETH_TEST_FL_FAILED;
2097 return;
2098 }
2099
2100 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
2101
2102 if (!netif_running(dev))
2103 return;
2104
2105 /* offline tests are not supported in MF mode */
fb3bff17 2106 if (IS_MF(bp))
de0c62db 2107 etest->flags &= ~ETH_TEST_FL_OFFLINE;
a22f0788 2108 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
de0c62db
DK		 2109
2110 if (etest->flags & ETH_TEST_FL_OFFLINE) {
2111 int port = BP_PORT(bp);
2112 u32 val;
2113 u8 link_up;
2114
2115 /* save current value of input enable for TX port IF */
2116 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2117 /* disable input for TX port IF */
2118 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2119
a22f0788
YR		 2120 link_up = bp->link_vars.link_up;
2121
de0c62db
DK		 2122 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2123 bnx2x_nic_load(bp, LOAD_DIAG);
2124 /* wait until link state is restored */
619c5cb6 2125 bnx2x_wait_for_link(bp, 1, is_serdes);
de0c62db
DK		 2126
2127 if (bnx2x_test_registers(bp) != 0) {
2128 buf[0] = 1;
2129 etest->flags |= ETH_TEST_FL_FAILED;
2130 }
2131 if (bnx2x_test_memory(bp) != 0) {
2132 buf[1] = 1;
2133 etest->flags |= ETH_TEST_FL_FAILED;
2134 }
f85582f8 2135
619c5cb6 2136 buf[2] = bnx2x_test_loopback(bp);
de0c62db
DK		 2137 if (buf[2] != 0)
2138 etest->flags |= ETH_TEST_FL_FAILED;
2139
2140 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2141
2142 /* restore input for TX port IF */
2143 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2144
2145 bnx2x_nic_load(bp, LOAD_NORMAL);
2146 /* wait until link state is restored */
a22f0788 2147 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 2148 }
2149 if (bnx2x_test_nvram(bp) != 0) {
2150 buf[3] = 1;
2151 etest->flags |= ETH_TEST_FL_FAILED;
2152 }
2153 if (bnx2x_test_intr(bp) != 0) {
2154 buf[4] = 1;
2155 etest->flags |= ETH_TEST_FL_FAILED;
2156 }
633ac363
DK		 2157
2158 if (bnx2x_link_test(bp, is_serdes) != 0) {
2159 buf[5] = 1;
2160 etest->flags |= ETH_TEST_FL_FAILED;
2161 }
de0c62db
DK		 2162
2163#ifdef BNX2X_EXTRA_DEBUG
2164 bnx2x_panic_dump(bp);
2165#endif
2166}
2167
de0c62db
DK		 2168#define IS_PORT_STAT(i) \
2169 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2170#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 2171#define IS_MF_MODE_STAT(bp) \
2172 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db 2173
619c5cb6
VZ		 2174/* ethtool statistics are displayed for all regular ethernet queues and the
2175 * fcoe L2 queue if not disabled
2176 */
2177static inline int bnx2x_num_stat_queues(struct bnx2x *bp)
2178{
2179 return BNX2X_NUM_ETH_QUEUES(bp);
2180}
2181
de0c62db
DK		 2182static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2183{
2184 struct bnx2x *bp = netdev_priv(dev);
2185 int i, num_stats;
2186
2187 switch (stringset) {
2188 case ETH_SS_STATS:
2189 if (is_multi(bp)) {
619c5cb6 2190 num_stats = bnx2x_num_stat_queues(bp) *
d5e83632
YM		 2191 BNX2X_NUM_Q_STATS;
2192 } else
2193 num_stats = 0;
2194 if (IS_MF_MODE_STAT(bp)) {
2195 for (i = 0; i < BNX2X_NUM_STATS; i++)
2196 if (IS_FUNC_STAT(i))
2197 num_stats++;
2198 } else
2199 num_stats += BNX2X_NUM_STATS;
2200
de0c62db
DK		 2201 return num_stats;
2202
2203 case ETH_SS_TEST:
2204 return BNX2X_NUM_TESTS;
2205
2206 default:
2207 return -EINVAL;
2208 }
2209}
2210
2211static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2212{
2213 struct bnx2x *bp = netdev_priv(dev);
2214 int i, j, k;
ec6ba945 2215 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 2216
2217 switch (stringset) {
2218 case ETH_SS_STATS:
d5e83632 2219 k = 0;
de0c62db 2220 if (is_multi(bp)) {
619c5cb6 2221 for_each_eth_queue(bp, i) {
ec6ba945 2222 memset(queue_name, 0, sizeof(queue_name));
619c5cb6 2223 sprintf(queue_name, "%d", i);
de0c62db 2224 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 2225 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2226 ETH_GSTRING_LEN,
2227 bnx2x_q_stats_arr[j].string,
2228 queue_name);
de0c62db
DK		 2229 k += BNX2X_NUM_Q_STATS;
2230 }
de0c62db 2231 }
d5e83632
YM		 2232
2233
2234 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2235 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2236 continue;
2237 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2238 bnx2x_stats_arr[i].string);
2239 j++;
2240 }
2241
de0c62db
DK		 2242 break;
2243
2244 case ETH_SS_TEST:
2245 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
2246 break;
2247 }
2248}
2249
2250static void bnx2x_get_ethtool_stats(struct net_device *dev,
2251 struct ethtool_stats *stats, u64 *buf)
2252{
2253 struct bnx2x *bp = netdev_priv(dev);
2254 u32 *hw_stats, *offset;
d5e83632 2255 int i, j, k = 0;
de0c62db
DK		 2256
2257 if (is_multi(bp)) {
619c5cb6 2258 for_each_eth_queue(bp, i) {
de0c62db
DK		 2259 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2260 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2261 if (bnx2x_q_stats_arr[j].size == 0) {
2262 /* skip this counter */
2263 buf[k + j] = 0;
2264 continue;
2265 }
2266 offset = (hw_stats +
2267 bnx2x_q_stats_arr[j].offset);
2268 if (bnx2x_q_stats_arr[j].size == 4) {
2269 /* 4-byte counter */
2270 buf[k + j] = (u64) *offset;
2271 continue;
2272 }
2273 /* 8-byte counter */
2274 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2275 }
2276 k += BNX2X_NUM_Q_STATS;
2277 }
d5e83632
YM		 2278 }
2279
2280 hw_stats = (u32 *)&bp->eth_stats;
2281 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2282 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2283 continue;
2284 if (bnx2x_stats_arr[i].size == 0) {
2285 /* skip this counter */
2286 buf[k + j] = 0;
2287 j++;
2288 continue;
de0c62db 2289 }
d5e83632
YM		 2290 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2291 if (bnx2x_stats_arr[i].size == 4) {
2292 /* 4-byte counter */
2293 buf[k + j] = (u64) *offset;
de0c62db 2294 j++;
d5e83632 2295 continue;
de0c62db 2296 }
d5e83632
YM		 2297 /* 8-byte counter */
2298 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2299 j++;
de0c62db
DK		 2300 }
2301}
2302
32d36134 2303static int bnx2x_set_phys_id(struct net_device *dev,
2304 enum ethtool_phys_id_state state)
de0c62db
DK		 2305{
2306 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 2307
2308 if (!netif_running(dev))
32d36134 2309 return -EAGAIN;
de0c62db
DK		 2310
2311 if (!bp->port.pmf)
32d36134 2312 return -EOPNOTSUPP;
de0c62db 2313
32d36134 2314 switch (state) {
2315 case ETHTOOL_ID_ACTIVE:
fce55922 2316 return 1; /* cycle on/off once per second */
de0c62db 2317
32d36134 2318 case ETHTOOL_ID_ON:
2319 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2320 LED_MODE_ON, SPEED_1000);
32d36134 2321 break;
de0c62db 2322
32d36134 2323 case ETHTOOL_ID_OFF:
2324 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2325 LED_MODE_FRONT_PANEL_OFF, 0);
de0c62db 2326
32d36134 2327 break;
2328
2329 case ETHTOOL_ID_INACTIVE:
e1943424
DM		 2330 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2331 LED_MODE_OPER,
2332 bp->link_vars.line_speed);
32d36134 2333 }
de0c62db
DK		 2334
2335 return 0;
2336}
2337
ab532cf3 2338static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 2339 u32 *rules __always_unused)
ab532cf3
TH		 2340{
2341 struct bnx2x *bp = netdev_priv(dev);
2342
2343 switch (info->cmd) {
2344 case ETHTOOL_GRXRINGS:
2345 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2346 return 0;
2347
2348 default:
2349 return -EOPNOTSUPP;
2350 }
2351}
2352
7850f63f
BH		 2353static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
2354{
2355 struct bnx2x *bp = netdev_priv(dev);
2356
2357 return (bp->multi_mode == ETH_RSS_MODE_DISABLED ?
2358 0 : T_ETH_INDIRECTION_TABLE_SIZE);
2359}
2360
2361static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
ab532cf3
TH		 2362{
2363 struct bnx2x *bp = netdev_priv(dev);
619c5cb6
VZ		 2364 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2365 size_t i;
ab532cf3 2366
619c5cb6
VZ		 2367 /* Get the current configuration of the RSS indirection table */
2368 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2369
2370 /*
2371 * We can't use a memcpy() as an internal storage of an
2372 * indirection table is a u8 array while indir->ring_index
2373 * points to an array of u32.
2374 *
2375 * Indirection table contains the FW Client IDs, so we need to
2376 * align the returned table to the Client ID of the leading RSS
2377 * queue.
2378 */
7850f63f
BH		 2379 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
2380 indir[i] = ind_table[i] - bp->fp->cl_id;
619c5cb6 2381
ab532cf3
TH		 2382 return 0;
2383}
2384
7850f63f 2385static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
ab532cf3
TH		 2386{
2387 struct bnx2x *bp = netdev_priv(dev);
2388 size_t i;
619c5cb6 2389 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
619c5cb6
VZ		 2390
2391 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
619c5cb6
VZ		 2392 /*
2393 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2394 * as an internal storage of an indirection table is a u8 array
2395 * while indir->ring_index points to an array of u32.
2396 *
2397 * Indirection table contains the FW Client IDs, so we need to
2398 * align the received table to the Client ID of the leading RSS
2399 * queue
2400 */
7850f63f 2401 ind_table[i] = indir[i] + bp->fp->cl_id;
619c5cb6 2402 }
ab532cf3 2403
619c5cb6 2404 return bnx2x_config_rss_pf(bp, ind_table, false);
ab532cf3
TH		 2405}
2406
de0c62db
DK		 2407static const struct ethtool_ops bnx2x_ethtool_ops = {
2408 .get_settings = bnx2x_get_settings,
2409 .set_settings = bnx2x_set_settings,
2410 .get_drvinfo = bnx2x_get_drvinfo,
2411 .get_regs_len = bnx2x_get_regs_len,
2412 .get_regs = bnx2x_get_regs,
2413 .get_wol = bnx2x_get_wol,
2414 .set_wol = bnx2x_set_wol,
2415 .get_msglevel = bnx2x_get_msglevel,
2416 .set_msglevel = bnx2x_set_msglevel,
2417 .nway_reset = bnx2x_nway_reset,
2418 .get_link = bnx2x_get_link,
2419 .get_eeprom_len = bnx2x_get_eeprom_len,
2420 .get_eeprom = bnx2x_get_eeprom,
2421 .set_eeprom = bnx2x_set_eeprom,
2422 .get_coalesce = bnx2x_get_coalesce,
2423 .set_coalesce = bnx2x_set_coalesce,
2424 .get_ringparam = bnx2x_get_ringparam,
2425 .set_ringparam = bnx2x_set_ringparam,
2426 .get_pauseparam = bnx2x_get_pauseparam,
2427 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 2428 .self_test = bnx2x_self_test,
2429 .get_sset_count = bnx2x_get_sset_count,
2430 .get_strings = bnx2x_get_strings,
32d36134 2431 .set_phys_id = bnx2x_set_phys_id,
de0c62db 2432 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3 2433 .get_rxnfc = bnx2x_get_rxnfc,
7850f63f 2434 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
ab532cf3
TH		 2435 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2436 .set_rxfh_indir = bnx2x_set_rxfh_indir,
de0c62db
DK		 2437};
2438
2439void bnx2x_set_ethtool_ops(struct net_device *netdev)
2440{
2441 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2442}
Linux kernel - Deliverables
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