Commit | Line | Data |
---|---|---|
34f80b04 | 1 | /* bnx2x_main.c: Broadcom Everest network driver. |
a2fbb9ea | 2 | * |
85b26ea1 | 3 | * Copyright (c) 2007-2012 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
ca00392c | 13 | * Slowpath and fastpath rework by Vladislav Zolotarov |
c14423fe | 14 | * Statistics and Link management by Yitchak Gertner |
a2fbb9ea ET |
15 | * |
16 | */ | |
17 | ||
f1deab50 JP |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
19 | ||
a2fbb9ea ET |
20 | #include <linux/module.h> |
21 | #include <linux/moduleparam.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/device.h> /* for dev_info() */ | |
24 | #include <linux/timer.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/slab.h> | |
a2fbb9ea ET |
28 | #include <linux/interrupt.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/bitops.h> | |
36 | #include <linux/irq.h> | |
37 | #include <linux/delay.h> | |
38 | #include <asm/byteorder.h> | |
39 | #include <linux/time.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/mii.h> | |
0c6671b0 | 42 | #include <linux/if_vlan.h> |
a2fbb9ea | 43 | #include <net/ip.h> |
619c5cb6 | 44 | #include <net/ipv6.h> |
a2fbb9ea ET |
45 | #include <net/tcp.h> |
46 | #include <net/checksum.h> | |
34f80b04 | 47 | #include <net/ip6_checksum.h> |
a2fbb9ea ET |
48 | #include <linux/workqueue.h> |
49 | #include <linux/crc32.h> | |
34f80b04 | 50 | #include <linux/crc32c.h> |
a2fbb9ea ET |
51 | #include <linux/prefetch.h> |
52 | #include <linux/zlib.h> | |
a2fbb9ea | 53 | #include <linux/io.h> |
452427b0 | 54 | #include <linux/semaphore.h> |
45229b42 | 55 | #include <linux/stringify.h> |
7ab24bfd | 56 | #include <linux/vmalloc.h> |
a2fbb9ea | 57 | |
a2fbb9ea ET |
58 | #include "bnx2x.h" |
59 | #include "bnx2x_init.h" | |
94a78b79 | 60 | #include "bnx2x_init_ops.h" |
9f6c9258 | 61 | #include "bnx2x_cmn.h" |
e4901dde | 62 | #include "bnx2x_dcb.h" |
042181f5 | 63 | #include "bnx2x_sp.h" |
a2fbb9ea | 64 | |
94a78b79 VZ |
65 | #include <linux/firmware.h> |
66 | #include "bnx2x_fw_file_hdr.h" | |
67 | /* FW files */ | |
45229b42 BH |
68 | #define FW_FILE_VERSION \ |
69 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ | |
70 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ | |
71 | __stringify(BCM_5710_FW_REVISION_VERSION) "." \ | |
72 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) | |
560131f3 DK |
73 | #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" |
74 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" | |
f2e0899f | 75 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
94a78b79 | 76 | |
2e499d3c BW |
77 | #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN) |
78 | ||
34f80b04 EG |
79 | /* Time in jiffies before concluding the transmitter is hung */ |
80 | #define TX_TIMEOUT (5*HZ) | |
a2fbb9ea | 81 | |
53a10565 | 82 | static char version[] __devinitdata = |
619c5cb6 | 83 | "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " |
a2fbb9ea ET |
84 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
85 | ||
24e3fcef | 86 | MODULE_AUTHOR("Eliezer Tamir"); |
f2e0899f | 87 | MODULE_DESCRIPTION("Broadcom NetXtreme II " |
619c5cb6 VZ |
88 | "BCM57710/57711/57711E/" |
89 | "57712/57712_MF/57800/57800_MF/57810/57810_MF/" | |
90 | "57840/57840_MF Driver"); | |
a2fbb9ea ET |
91 | MODULE_LICENSE("GPL"); |
92 | MODULE_VERSION(DRV_MODULE_VERSION); | |
45229b42 BH |
93 | MODULE_FIRMWARE(FW_FILE_NAME_E1); |
94 | MODULE_FIRMWARE(FW_FILE_NAME_E1H); | |
f2e0899f | 95 | MODULE_FIRMWARE(FW_FILE_NAME_E2); |
a2fbb9ea | 96 | |
ca00392c | 97 | |
d6214d7a | 98 | int num_queues; |
54b9ddaa | 99 | module_param(num_queues, int, 0); |
96305234 DK |
100 | MODULE_PARM_DESC(num_queues, |
101 | " Set number of queues (default is as a number of CPUs)"); | |
555f6c78 | 102 | |
19680c48 | 103 | static int disable_tpa; |
19680c48 | 104 | module_param(disable_tpa, int, 0); |
9898f86d | 105 | MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); |
8badd27a | 106 | |
9ee3d37b DK |
107 | #define INT_MODE_INTx 1 |
108 | #define INT_MODE_MSI 2 | |
0e8d2ec5 | 109 | int int_mode; |
8badd27a | 110 | module_param(int_mode, int, 0); |
619c5cb6 | 111 | MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " |
cdaa7cb8 | 112 | "(1 INT#x; 2 MSI)"); |
8badd27a | 113 | |
a18f5128 EG |
114 | static int dropless_fc; |
115 | module_param(dropless_fc, int, 0); | |
116 | MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); | |
117 | ||
8d5726c4 EG |
118 | static int mrrs = -1; |
119 | module_param(mrrs, int, 0); | |
120 | MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); | |
121 | ||
9898f86d | 122 | static int debug; |
a2fbb9ea | 123 | module_param(debug, int, 0); |
9898f86d EG |
124 | MODULE_PARM_DESC(debug, " Default debug msglevel"); |
125 | ||
a2fbb9ea | 126 | |
619c5cb6 VZ |
127 | |
128 | struct workqueue_struct *bnx2x_wq; | |
ec6ba945 | 129 | |
a2fbb9ea ET |
130 | enum bnx2x_board_type { |
131 | BCM57710 = 0, | |
619c5cb6 VZ |
132 | BCM57711, |
133 | BCM57711E, | |
134 | BCM57712, | |
135 | BCM57712_MF, | |
136 | BCM57800, | |
137 | BCM57800_MF, | |
138 | BCM57810, | |
139 | BCM57810_MF, | |
140 | BCM57840, | |
7e8e02df BW |
141 | BCM57840_MF, |
142 | BCM57811, | |
143 | BCM57811_MF | |
a2fbb9ea ET |
144 | }; |
145 | ||
34f80b04 | 146 | /* indexed by board_type, above */ |
53a10565 | 147 | static struct { |
a2fbb9ea ET |
148 | char *name; |
149 | } board_info[] __devinitdata = { | |
619c5cb6 VZ |
150 | { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, |
151 | { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, | |
152 | { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, | |
153 | { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, | |
154 | { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, | |
155 | { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, | |
156 | { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, | |
157 | { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, | |
158 | { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, | |
159 | { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, | |
7e8e02df BW |
160 | { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"}, |
161 | { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet"}, | |
162 | { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function"}, | |
a2fbb9ea ET |
163 | }; |
164 | ||
619c5cb6 VZ |
165 | #ifndef PCI_DEVICE_ID_NX2_57710 |
166 | #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 | |
167 | #endif | |
168 | #ifndef PCI_DEVICE_ID_NX2_57711 | |
169 | #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 | |
170 | #endif | |
171 | #ifndef PCI_DEVICE_ID_NX2_57711E | |
172 | #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E | |
173 | #endif | |
174 | #ifndef PCI_DEVICE_ID_NX2_57712 | |
175 | #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 | |
176 | #endif | |
177 | #ifndef PCI_DEVICE_ID_NX2_57712_MF | |
178 | #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF | |
179 | #endif | |
180 | #ifndef PCI_DEVICE_ID_NX2_57800 | |
181 | #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 | |
182 | #endif | |
183 | #ifndef PCI_DEVICE_ID_NX2_57800_MF | |
184 | #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF | |
185 | #endif | |
186 | #ifndef PCI_DEVICE_ID_NX2_57810 | |
187 | #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 | |
188 | #endif | |
189 | #ifndef PCI_DEVICE_ID_NX2_57810_MF | |
190 | #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF | |
191 | #endif | |
192 | #ifndef PCI_DEVICE_ID_NX2_57840 | |
193 | #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 | |
194 | #endif | |
195 | #ifndef PCI_DEVICE_ID_NX2_57840_MF | |
196 | #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF | |
197 | #endif | |
7e8e02df BW |
198 | #ifndef PCI_DEVICE_ID_NX2_57811 |
199 | #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 | |
200 | #endif | |
201 | #ifndef PCI_DEVICE_ID_NX2_57811_MF | |
202 | #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF | |
203 | #endif | |
a3aa1884 | 204 | static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { |
e4ed7113 EG |
205 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, |
206 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, | |
207 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, | |
f2e0899f | 208 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, |
619c5cb6 VZ |
209 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, |
210 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, | |
211 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, | |
212 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, | |
213 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, | |
214 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, | |
215 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, | |
7e8e02df BW |
216 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, |
217 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, | |
a2fbb9ea ET |
218 | { 0 } |
219 | }; | |
220 | ||
221 | MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); | |
222 | ||
452427b0 YM |
223 | /* Global resources for unloading a previously loaded device */ |
224 | #define BNX2X_PREV_WAIT_NEEDED 1 | |
225 | static DEFINE_SEMAPHORE(bnx2x_prev_sem); | |
226 | static LIST_HEAD(bnx2x_prev_list); | |
a2fbb9ea ET |
227 | /**************************************************************************** |
228 | * General service functions | |
229 | ****************************************************************************/ | |
230 | ||
1191cb83 | 231 | static void __storm_memset_dma_mapping(struct bnx2x *bp, |
619c5cb6 VZ |
232 | u32 addr, dma_addr_t mapping) |
233 | { | |
234 | REG_WR(bp, addr, U64_LO(mapping)); | |
235 | REG_WR(bp, addr + 4, U64_HI(mapping)); | |
236 | } | |
237 | ||
1191cb83 ED |
238 | static void storm_memset_spq_addr(struct bnx2x *bp, |
239 | dma_addr_t mapping, u16 abs_fid) | |
619c5cb6 VZ |
240 | { |
241 | u32 addr = XSEM_REG_FAST_MEMORY + | |
242 | XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); | |
243 | ||
244 | __storm_memset_dma_mapping(bp, addr, mapping); | |
245 | } | |
246 | ||
1191cb83 ED |
247 | static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, |
248 | u16 pf_id) | |
523224a3 | 249 | { |
619c5cb6 VZ |
250 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), |
251 | pf_id); | |
252 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), | |
253 | pf_id); | |
254 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), | |
255 | pf_id); | |
256 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), | |
257 | pf_id); | |
523224a3 DK |
258 | } |
259 | ||
1191cb83 ED |
260 | static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, |
261 | u8 enable) | |
619c5cb6 VZ |
262 | { |
263 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), | |
264 | enable); | |
265 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), | |
266 | enable); | |
267 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), | |
268 | enable); | |
269 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), | |
270 | enable); | |
271 | } | |
523224a3 | 272 | |
1191cb83 ED |
273 | static void storm_memset_eq_data(struct bnx2x *bp, |
274 | struct event_ring_data *eq_data, | |
523224a3 DK |
275 | u16 pfid) |
276 | { | |
277 | size_t size = sizeof(struct event_ring_data); | |
278 | ||
279 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); | |
280 | ||
281 | __storm_memset_struct(bp, addr, size, (u32 *)eq_data); | |
282 | } | |
283 | ||
1191cb83 ED |
284 | static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, |
285 | u16 pfid) | |
523224a3 DK |
286 | { |
287 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); | |
288 | REG_WR16(bp, addr, eq_prod); | |
289 | } | |
290 | ||
a2fbb9ea ET |
291 | /* used only at init |
292 | * locking is done by mcp | |
293 | */ | |
8d96286a | 294 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) |
a2fbb9ea ET |
295 | { |
296 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
297 | pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); | |
298 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
299 | PCICFG_VENDOR_ID_OFFSET); | |
300 | } | |
301 | ||
a2fbb9ea ET |
302 | static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) |
303 | { | |
304 | u32 val; | |
305 | ||
306 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
307 | pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); | |
308 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
309 | PCICFG_VENDOR_ID_OFFSET); | |
310 | ||
311 | return val; | |
312 | } | |
a2fbb9ea | 313 | |
f2e0899f DK |
314 | #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" |
315 | #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" | |
316 | #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" | |
317 | #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" | |
318 | #define DMAE_DP_DST_NONE "dst_addr [none]" | |
319 | ||
f2e0899f | 320 | |
a2fbb9ea | 321 | /* copy command into DMAE command memory and set DMAE command go */ |
6c719d00 | 322 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) |
a2fbb9ea ET |
323 | { |
324 | u32 cmd_offset; | |
325 | int i; | |
326 | ||
327 | cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); | |
328 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { | |
329 | REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
a2fbb9ea ET |
330 | } |
331 | REG_WR(bp, dmae_reg_go_c[idx], 1); | |
332 | } | |
333 | ||
f2e0899f | 334 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) |
a2fbb9ea | 335 | { |
f2e0899f DK |
336 | return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | |
337 | DMAE_CMD_C_ENABLE); | |
338 | } | |
ad8d3948 | 339 | |
f2e0899f DK |
340 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) |
341 | { | |
342 | return opcode & ~DMAE_CMD_SRC_RESET; | |
343 | } | |
ad8d3948 | 344 | |
f2e0899f DK |
345 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
346 | bool with_comp, u8 comp_type) | |
347 | { | |
348 | u32 opcode = 0; | |
349 | ||
350 | opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | | |
351 | (dst_type << DMAE_COMMAND_DST_SHIFT)); | |
ad8d3948 | 352 | |
f2e0899f DK |
353 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
354 | ||
355 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); | |
3395a033 DK |
356 | opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | |
357 | (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); | |
f2e0899f | 358 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); |
a2fbb9ea | 359 | |
a2fbb9ea | 360 | #ifdef __BIG_ENDIAN |
f2e0899f | 361 | opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; |
a2fbb9ea | 362 | #else |
f2e0899f | 363 | opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; |
a2fbb9ea | 364 | #endif |
f2e0899f DK |
365 | if (with_comp) |
366 | opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); | |
367 | return opcode; | |
368 | } | |
369 | ||
8d96286a | 370 | static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, |
371 | struct dmae_command *dmae, | |
372 | u8 src_type, u8 dst_type) | |
f2e0899f DK |
373 | { |
374 | memset(dmae, 0, sizeof(struct dmae_command)); | |
375 | ||
376 | /* set the opcode */ | |
377 | dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, | |
378 | true, DMAE_COMP_PCI); | |
379 | ||
380 | /* fill in the completion parameters */ | |
381 | dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); | |
382 | dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); | |
383 | dmae->comp_val = DMAE_COMP_VAL; | |
384 | } | |
385 | ||
386 | /* issue a dmae command over the init-channel and wailt for completion */ | |
8d96286a | 387 | static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, |
388 | struct dmae_command *dmae) | |
f2e0899f DK |
389 | { |
390 | u32 *wb_comp = bnx2x_sp(bp, wb_comp); | |
5e374b5a | 391 | int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; |
f2e0899f DK |
392 | int rc = 0; |
393 | ||
619c5cb6 VZ |
394 | /* |
395 | * Lock the dmae channel. Disable BHs to prevent a dead-lock | |
396 | * as long as this code is called both from syscall context and | |
397 | * from ndo_set_rx_mode() flow that may be called from BH. | |
398 | */ | |
6e30dd4e | 399 | spin_lock_bh(&bp->dmae_lock); |
5ff7b6d4 | 400 | |
f2e0899f | 401 | /* reset completion */ |
a2fbb9ea ET |
402 | *wb_comp = 0; |
403 | ||
f2e0899f DK |
404 | /* post the command on the channel used for initializations */ |
405 | bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); | |
a2fbb9ea | 406 | |
f2e0899f | 407 | /* wait for completion */ |
a2fbb9ea | 408 | udelay(5); |
f2e0899f | 409 | while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { |
ad8d3948 | 410 | |
95c6c616 AE |
411 | if (!cnt || |
412 | (bp->recovery_state != BNX2X_RECOVERY_DONE && | |
413 | bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
c3eefaf6 | 414 | BNX2X_ERR("DMAE timeout!\n"); |
f2e0899f DK |
415 | rc = DMAE_TIMEOUT; |
416 | goto unlock; | |
a2fbb9ea | 417 | } |
ad8d3948 | 418 | cnt--; |
f2e0899f | 419 | udelay(50); |
a2fbb9ea | 420 | } |
f2e0899f DK |
421 | if (*wb_comp & DMAE_PCI_ERR_FLAG) { |
422 | BNX2X_ERR("DMAE PCI error!\n"); | |
423 | rc = DMAE_PCI_ERROR; | |
424 | } | |
425 | ||
f2e0899f | 426 | unlock: |
6e30dd4e | 427 | spin_unlock_bh(&bp->dmae_lock); |
f2e0899f DK |
428 | return rc; |
429 | } | |
430 | ||
431 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
432 | u32 len32) | |
433 | { | |
434 | struct dmae_command dmae; | |
435 | ||
436 | if (!bp->dmae_ready) { | |
437 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
438 | ||
127a425e AE |
439 | if (CHIP_IS_E1(bp)) |
440 | bnx2x_init_ind_wr(bp, dst_addr, data, len32); | |
441 | else | |
442 | bnx2x_init_str_wr(bp, dst_addr, data, len32); | |
f2e0899f DK |
443 | return; |
444 | } | |
445 | ||
446 | /* set opcode and fixed command fields */ | |
447 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); | |
448 | ||
449 | /* fill in addresses and len */ | |
450 | dmae.src_addr_lo = U64_LO(dma_addr); | |
451 | dmae.src_addr_hi = U64_HI(dma_addr); | |
452 | dmae.dst_addr_lo = dst_addr >> 2; | |
453 | dmae.dst_addr_hi = 0; | |
454 | dmae.len = len32; | |
455 | ||
f2e0899f DK |
456 | /* issue the command and wait for completion */ |
457 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
a2fbb9ea ET |
458 | } |
459 | ||
c18487ee | 460 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) |
a2fbb9ea | 461 | { |
5ff7b6d4 | 462 | struct dmae_command dmae; |
ad8d3948 EG |
463 | |
464 | if (!bp->dmae_ready) { | |
465 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
466 | int i; | |
467 | ||
51c1a580 | 468 | if (CHIP_IS_E1(bp)) |
127a425e AE |
469 | for (i = 0; i < len32; i++) |
470 | data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); | |
51c1a580 | 471 | else |
127a425e AE |
472 | for (i = 0; i < len32; i++) |
473 | data[i] = REG_RD(bp, src_addr + i*4); | |
474 | ||
ad8d3948 EG |
475 | return; |
476 | } | |
477 | ||
f2e0899f DK |
478 | /* set opcode and fixed command fields */ |
479 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); | |
a2fbb9ea | 480 | |
f2e0899f | 481 | /* fill in addresses and len */ |
5ff7b6d4 EG |
482 | dmae.src_addr_lo = src_addr >> 2; |
483 | dmae.src_addr_hi = 0; | |
484 | dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); | |
485 | dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); | |
486 | dmae.len = len32; | |
ad8d3948 | 487 | |
f2e0899f DK |
488 | /* issue the command and wait for completion */ |
489 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
ad8d3948 EG |
490 | } |
491 | ||
8d96286a | 492 | static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
493 | u32 addr, u32 len) | |
573f2035 | 494 | { |
02e3c6cb | 495 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); |
573f2035 EG |
496 | int offset = 0; |
497 | ||
02e3c6cb | 498 | while (len > dmae_wr_max) { |
573f2035 | 499 | bnx2x_write_dmae(bp, phys_addr + offset, |
02e3c6cb VZ |
500 | addr + offset, dmae_wr_max); |
501 | offset += dmae_wr_max * 4; | |
502 | len -= dmae_wr_max; | |
573f2035 EG |
503 | } |
504 | ||
505 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); | |
506 | } | |
507 | ||
a2fbb9ea ET |
508 | static int bnx2x_mc_assert(struct bnx2x *bp) |
509 | { | |
a2fbb9ea | 510 | char last_idx; |
34f80b04 EG |
511 | int i, rc = 0; |
512 | u32 row0, row1, row2, row3; | |
513 | ||
514 | /* XSTORM */ | |
515 | last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + | |
516 | XSTORM_ASSERT_LIST_INDEX_OFFSET); | |
517 | if (last_idx) | |
518 | BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
519 | ||
520 | /* print the asserts */ | |
521 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
522 | ||
523 | row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
524 | XSTORM_ASSERT_LIST_OFFSET(i)); | |
525 | row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
526 | XSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
527 | row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
528 | XSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
529 | row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
530 | XSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
531 | ||
532 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 533 | BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
534 | i, row3, row2, row1, row0); |
535 | rc++; | |
536 | } else { | |
537 | break; | |
538 | } | |
539 | } | |
540 | ||
541 | /* TSTORM */ | |
542 | last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + | |
543 | TSTORM_ASSERT_LIST_INDEX_OFFSET); | |
544 | if (last_idx) | |
545 | BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
546 | ||
547 | /* print the asserts */ | |
548 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
549 | ||
550 | row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
551 | TSTORM_ASSERT_LIST_OFFSET(i)); | |
552 | row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
553 | TSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
554 | row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
555 | TSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
556 | row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
557 | TSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
558 | ||
559 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 560 | BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
561 | i, row3, row2, row1, row0); |
562 | rc++; | |
563 | } else { | |
564 | break; | |
565 | } | |
566 | } | |
567 | ||
568 | /* CSTORM */ | |
569 | last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + | |
570 | CSTORM_ASSERT_LIST_INDEX_OFFSET); | |
571 | if (last_idx) | |
572 | BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
573 | ||
574 | /* print the asserts */ | |
575 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
576 | ||
577 | row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
578 | CSTORM_ASSERT_LIST_OFFSET(i)); | |
579 | row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
580 | CSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
581 | row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
582 | CSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
583 | row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
584 | CSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
585 | ||
586 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 587 | BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
588 | i, row3, row2, row1, row0); |
589 | rc++; | |
590 | } else { | |
591 | break; | |
592 | } | |
593 | } | |
594 | ||
595 | /* USTORM */ | |
596 | last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + | |
597 | USTORM_ASSERT_LIST_INDEX_OFFSET); | |
598 | if (last_idx) | |
599 | BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
600 | ||
601 | /* print the asserts */ | |
602 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
603 | ||
604 | row0 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
605 | USTORM_ASSERT_LIST_OFFSET(i)); | |
606 | row1 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
607 | USTORM_ASSERT_LIST_OFFSET(i) + 4); | |
608 | row2 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
609 | USTORM_ASSERT_LIST_OFFSET(i) + 8); | |
610 | row3 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
611 | USTORM_ASSERT_LIST_OFFSET(i) + 12); | |
612 | ||
613 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 614 | BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
615 | i, row3, row2, row1, row0); |
616 | rc++; | |
617 | } else { | |
618 | break; | |
a2fbb9ea ET |
619 | } |
620 | } | |
34f80b04 | 621 | |
a2fbb9ea ET |
622 | return rc; |
623 | } | |
c14423fe | 624 | |
7a25cc73 | 625 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) |
a2fbb9ea | 626 | { |
7a25cc73 | 627 | u32 addr, val; |
a2fbb9ea | 628 | u32 mark, offset; |
4781bfad | 629 | __be32 data[9]; |
a2fbb9ea | 630 | int word; |
f2e0899f | 631 | u32 trace_shmem_base; |
2145a920 VZ |
632 | if (BP_NOMCP(bp)) { |
633 | BNX2X_ERR("NO MCP - can not dump\n"); | |
634 | return; | |
635 | } | |
7a25cc73 DK |
636 | netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", |
637 | (bp->common.bc_ver & 0xff0000) >> 16, | |
638 | (bp->common.bc_ver & 0xff00) >> 8, | |
639 | (bp->common.bc_ver & 0xff)); | |
640 | ||
641 | val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); | |
642 | if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) | |
51c1a580 | 643 | BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); |
cdaa7cb8 | 644 | |
f2e0899f DK |
645 | if (BP_PATH(bp) == 0) |
646 | trace_shmem_base = bp->common.shmem_base; | |
647 | else | |
648 | trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); | |
de128804 DK |
649 | addr = trace_shmem_base - 0x800; |
650 | ||
651 | /* validate TRCB signature */ | |
652 | mark = REG_RD(bp, addr); | |
653 | if (mark != MFW_TRACE_SIGNATURE) { | |
654 | BNX2X_ERR("Trace buffer signature is missing."); | |
655 | return ; | |
656 | } | |
657 | ||
658 | /* read cyclic buffer pointer */ | |
659 | addr += 4; | |
cdaa7cb8 | 660 | mark = REG_RD(bp, addr); |
f2e0899f DK |
661 | mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) |
662 | + ((mark + 0x3) & ~0x3) - 0x08000000; | |
7a25cc73 | 663 | printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); |
a2fbb9ea | 664 | |
7a25cc73 | 665 | printk("%s", lvl); |
f2e0899f | 666 | for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { |
a2fbb9ea | 667 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 668 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 669 | data[8] = 0x0; |
7995c64e | 670 | pr_cont("%s", (char *)data); |
a2fbb9ea | 671 | } |
cdaa7cb8 | 672 | for (offset = addr + 4; offset <= mark; offset += 0x8*4) { |
a2fbb9ea | 673 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 674 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 675 | data[8] = 0x0; |
7995c64e | 676 | pr_cont("%s", (char *)data); |
a2fbb9ea | 677 | } |
7a25cc73 DK |
678 | printk("%s" "end of fw dump\n", lvl); |
679 | } | |
680 | ||
1191cb83 | 681 | static void bnx2x_fw_dump(struct bnx2x *bp) |
7a25cc73 DK |
682 | { |
683 | bnx2x_fw_dump_lvl(bp, KERN_ERR); | |
a2fbb9ea ET |
684 | } |
685 | ||
6c719d00 | 686 | void bnx2x_panic_dump(struct bnx2x *bp) |
a2fbb9ea ET |
687 | { |
688 | int i; | |
523224a3 DK |
689 | u16 j; |
690 | struct hc_sp_status_block_data sp_sb_data; | |
691 | int func = BP_FUNC(bp); | |
692 | #ifdef BNX2X_STOP_ON_ERROR | |
693 | u16 start = 0, end = 0; | |
6383c0b3 | 694 | u8 cos; |
523224a3 | 695 | #endif |
a2fbb9ea | 696 | |
66e855f3 | 697 | bp->stats_state = STATS_STATE_DISABLED; |
7a752993 | 698 | bp->eth_stats.unrecoverable_error++; |
66e855f3 YG |
699 | DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); |
700 | ||
a2fbb9ea ET |
701 | BNX2X_ERR("begin crash dump -----------------\n"); |
702 | ||
8440d2b6 EG |
703 | /* Indices */ |
704 | /* Common */ | |
51c1a580 | 705 | BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", |
619c5cb6 VZ |
706 | bp->def_idx, bp->def_att_idx, bp->attn_state, |
707 | bp->spq_prod_idx, bp->stats_counter); | |
523224a3 DK |
708 | BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", |
709 | bp->def_status_blk->atten_status_block.attn_bits, | |
710 | bp->def_status_blk->atten_status_block.attn_bits_ack, | |
711 | bp->def_status_blk->atten_status_block.status_block_id, | |
712 | bp->def_status_blk->atten_status_block.attn_bits_index); | |
713 | BNX2X_ERR(" def ("); | |
714 | for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) | |
715 | pr_cont("0x%x%s", | |
f1deab50 JP |
716 | bp->def_status_blk->sp_sb.index_values[i], |
717 | (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); | |
523224a3 DK |
718 | |
719 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
720 | *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
721 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
722 | i*sizeof(u32)); | |
723 | ||
f1deab50 | 724 | pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", |
523224a3 DK |
725 | sp_sb_data.igu_sb_id, |
726 | sp_sb_data.igu_seg_id, | |
727 | sp_sb_data.p_func.pf_id, | |
728 | sp_sb_data.p_func.vnic_id, | |
729 | sp_sb_data.p_func.vf_id, | |
619c5cb6 VZ |
730 | sp_sb_data.p_func.vf_valid, |
731 | sp_sb_data.state); | |
523224a3 | 732 | |
8440d2b6 | 733 | |
ec6ba945 | 734 | for_each_eth_queue(bp, i) { |
a2fbb9ea | 735 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
523224a3 | 736 | int loop; |
f2e0899f | 737 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
738 | struct hc_status_block_data_e1x sb_data_e1x; |
739 | struct hc_status_block_sm *hc_sm_p = | |
619c5cb6 VZ |
740 | CHIP_IS_E1x(bp) ? |
741 | sb_data_e1x.common.state_machine : | |
742 | sb_data_e2.common.state_machine; | |
523224a3 | 743 | struct hc_index_data *hc_index_p = |
619c5cb6 VZ |
744 | CHIP_IS_E1x(bp) ? |
745 | sb_data_e1x.index_data : | |
746 | sb_data_e2.index_data; | |
6383c0b3 | 747 | u8 data_size, cos; |
523224a3 | 748 | u32 *sb_data_p; |
6383c0b3 | 749 | struct bnx2x_fp_txdata txdata; |
523224a3 DK |
750 | |
751 | /* Rx */ | |
51c1a580 | 752 | BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", |
8440d2b6 | 753 | i, fp->rx_bd_prod, fp->rx_bd_cons, |
523224a3 | 754 | fp->rx_comp_prod, |
66e855f3 | 755 | fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); |
51c1a580 | 756 | BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", |
8440d2b6 | 757 | fp->rx_sge_prod, fp->last_max_sge, |
523224a3 | 758 | le16_to_cpu(fp->fp_hc_idx)); |
a2fbb9ea | 759 | |
523224a3 | 760 | /* Tx */ |
6383c0b3 AE |
761 | for_each_cos_in_tx_queue(fp, cos) |
762 | { | |
65565884 | 763 | txdata = *fp->txdata_ptr[cos]; |
51c1a580 | 764 | BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", |
6383c0b3 AE |
765 | i, txdata.tx_pkt_prod, |
766 | txdata.tx_pkt_cons, txdata.tx_bd_prod, | |
767 | txdata.tx_bd_cons, | |
768 | le16_to_cpu(*txdata.tx_cons_sb)); | |
769 | } | |
523224a3 | 770 | |
619c5cb6 VZ |
771 | loop = CHIP_IS_E1x(bp) ? |
772 | HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; | |
523224a3 DK |
773 | |
774 | /* host sb data */ | |
775 | ||
ec6ba945 VZ |
776 | #ifdef BCM_CNIC |
777 | if (IS_FCOE_FP(fp)) | |
778 | continue; | |
779 | #endif | |
523224a3 DK |
780 | BNX2X_ERR(" run indexes ("); |
781 | for (j = 0; j < HC_SB_MAX_SM; j++) | |
782 | pr_cont("0x%x%s", | |
783 | fp->sb_running_index[j], | |
784 | (j == HC_SB_MAX_SM - 1) ? ")" : " "); | |
785 | ||
786 | BNX2X_ERR(" indexes ("); | |
787 | for (j = 0; j < loop; j++) | |
788 | pr_cont("0x%x%s", | |
789 | fp->sb_index_values[j], | |
790 | (j == loop - 1) ? ")" : " "); | |
791 | /* fw sb data */ | |
619c5cb6 VZ |
792 | data_size = CHIP_IS_E1x(bp) ? |
793 | sizeof(struct hc_status_block_data_e1x) : | |
794 | sizeof(struct hc_status_block_data_e2); | |
523224a3 | 795 | data_size /= sizeof(u32); |
619c5cb6 VZ |
796 | sb_data_p = CHIP_IS_E1x(bp) ? |
797 | (u32 *)&sb_data_e1x : | |
798 | (u32 *)&sb_data_e2; | |
523224a3 DK |
799 | /* copy sb data in here */ |
800 | for (j = 0; j < data_size; j++) | |
801 | *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
802 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + | |
803 | j * sizeof(u32)); | |
804 | ||
619c5cb6 | 805 | if (!CHIP_IS_E1x(bp)) { |
51c1a580 | 806 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
807 | sb_data_e2.common.p_func.pf_id, |
808 | sb_data_e2.common.p_func.vf_id, | |
809 | sb_data_e2.common.p_func.vf_valid, | |
810 | sb_data_e2.common.p_func.vnic_id, | |
619c5cb6 VZ |
811 | sb_data_e2.common.same_igu_sb_1b, |
812 | sb_data_e2.common.state); | |
f2e0899f | 813 | } else { |
51c1a580 | 814 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
815 | sb_data_e1x.common.p_func.pf_id, |
816 | sb_data_e1x.common.p_func.vf_id, | |
817 | sb_data_e1x.common.p_func.vf_valid, | |
818 | sb_data_e1x.common.p_func.vnic_id, | |
619c5cb6 VZ |
819 | sb_data_e1x.common.same_igu_sb_1b, |
820 | sb_data_e1x.common.state); | |
f2e0899f | 821 | } |
523224a3 DK |
822 | |
823 | /* SB_SMs data */ | |
824 | for (j = 0; j < HC_SB_MAX_SM; j++) { | |
51c1a580 MS |
825 | pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", |
826 | j, hc_sm_p[j].__flags, | |
827 | hc_sm_p[j].igu_sb_id, | |
828 | hc_sm_p[j].igu_seg_id, | |
829 | hc_sm_p[j].time_to_expire, | |
830 | hc_sm_p[j].timer_value); | |
523224a3 DK |
831 | } |
832 | ||
833 | /* Indecies data */ | |
834 | for (j = 0; j < loop; j++) { | |
51c1a580 | 835 | pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, |
523224a3 DK |
836 | hc_index_p[j].flags, |
837 | hc_index_p[j].timeout); | |
838 | } | |
8440d2b6 | 839 | } |
a2fbb9ea | 840 | |
523224a3 | 841 | #ifdef BNX2X_STOP_ON_ERROR |
8440d2b6 EG |
842 | /* Rings */ |
843 | /* Rx */ | |
ec6ba945 | 844 | for_each_rx_queue(bp, i) { |
8440d2b6 | 845 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea ET |
846 | |
847 | start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); | |
848 | end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); | |
8440d2b6 | 849 | for (j = start; j != end; j = RX_BD(j + 1)) { |
a2fbb9ea ET |
850 | u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; |
851 | struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; | |
852 | ||
c3eefaf6 | 853 | BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", |
44151acb | 854 | i, j, rx_bd[1], rx_bd[0], sw_bd->data); |
a2fbb9ea ET |
855 | } |
856 | ||
3196a88a EG |
857 | start = RX_SGE(fp->rx_sge_prod); |
858 | end = RX_SGE(fp->last_max_sge); | |
8440d2b6 | 859 | for (j = start; j != end; j = RX_SGE(j + 1)) { |
7a9b2557 VZ |
860 | u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; |
861 | struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; | |
862 | ||
c3eefaf6 EG |
863 | BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", |
864 | i, j, rx_sge[1], rx_sge[0], sw_page->page); | |
7a9b2557 VZ |
865 | } |
866 | ||
a2fbb9ea ET |
867 | start = RCQ_BD(fp->rx_comp_cons - 10); |
868 | end = RCQ_BD(fp->rx_comp_cons + 503); | |
8440d2b6 | 869 | for (j = start; j != end; j = RCQ_BD(j + 1)) { |
a2fbb9ea ET |
870 | u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; |
871 | ||
c3eefaf6 EG |
872 | BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", |
873 | i, j, cqe[0], cqe[1], cqe[2], cqe[3]); | |
a2fbb9ea ET |
874 | } |
875 | } | |
876 | ||
8440d2b6 | 877 | /* Tx */ |
ec6ba945 | 878 | for_each_tx_queue(bp, i) { |
8440d2b6 | 879 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
6383c0b3 | 880 | for_each_cos_in_tx_queue(fp, cos) { |
65565884 | 881 | struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; |
6383c0b3 AE |
882 | |
883 | start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); | |
884 | end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); | |
885 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
886 | struct sw_tx_bd *sw_bd = | |
887 | &txdata->tx_buf_ring[j]; | |
888 | ||
51c1a580 | 889 | BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", |
6383c0b3 AE |
890 | i, cos, j, sw_bd->skb, |
891 | sw_bd->first_bd); | |
892 | } | |
8440d2b6 | 893 | |
6383c0b3 AE |
894 | start = TX_BD(txdata->tx_bd_cons - 10); |
895 | end = TX_BD(txdata->tx_bd_cons + 254); | |
896 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
897 | u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; | |
8440d2b6 | 898 | |
51c1a580 | 899 | BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", |
6383c0b3 AE |
900 | i, cos, j, tx_bd[0], tx_bd[1], |
901 | tx_bd[2], tx_bd[3]); | |
902 | } | |
8440d2b6 EG |
903 | } |
904 | } | |
523224a3 | 905 | #endif |
34f80b04 | 906 | bnx2x_fw_dump(bp); |
a2fbb9ea ET |
907 | bnx2x_mc_assert(bp); |
908 | BNX2X_ERR("end crash dump -----------------\n"); | |
a2fbb9ea ET |
909 | } |
910 | ||
619c5cb6 VZ |
911 | /* |
912 | * FLR Support for E2 | |
913 | * | |
914 | * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW | |
915 | * initialization. | |
916 | */ | |
917 | #define FLR_WAIT_USEC 10000 /* 10 miliseconds */ | |
89db4ad8 AE |
918 | #define FLR_WAIT_INTERVAL 50 /* usec */ |
919 | #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ | |
619c5cb6 VZ |
920 | |
921 | struct pbf_pN_buf_regs { | |
922 | int pN; | |
923 | u32 init_crd; | |
924 | u32 crd; | |
925 | u32 crd_freed; | |
926 | }; | |
927 | ||
928 | struct pbf_pN_cmd_regs { | |
929 | int pN; | |
930 | u32 lines_occup; | |
931 | u32 lines_freed; | |
932 | }; | |
933 | ||
934 | static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, | |
935 | struct pbf_pN_buf_regs *regs, | |
936 | u32 poll_count) | |
937 | { | |
938 | u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; | |
939 | u32 cur_cnt = poll_count; | |
940 | ||
941 | crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); | |
942 | crd = crd_start = REG_RD(bp, regs->crd); | |
943 | init_crd = REG_RD(bp, regs->init_crd); | |
944 | ||
945 | DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); | |
946 | DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); | |
947 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); | |
948 | ||
949 | while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < | |
950 | (init_crd - crd_start))) { | |
951 | if (cur_cnt--) { | |
89db4ad8 | 952 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
953 | crd = REG_RD(bp, regs->crd); |
954 | crd_freed = REG_RD(bp, regs->crd_freed); | |
955 | } else { | |
956 | DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", | |
957 | regs->pN); | |
958 | DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", | |
959 | regs->pN, crd); | |
960 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", | |
961 | regs->pN, crd_freed); | |
962 | break; | |
963 | } | |
964 | } | |
965 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", | |
89db4ad8 | 966 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
967 | } |
968 | ||
969 | static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, | |
970 | struct pbf_pN_cmd_regs *regs, | |
971 | u32 poll_count) | |
972 | { | |
973 | u32 occup, to_free, freed, freed_start; | |
974 | u32 cur_cnt = poll_count; | |
975 | ||
976 | occup = to_free = REG_RD(bp, regs->lines_occup); | |
977 | freed = freed_start = REG_RD(bp, regs->lines_freed); | |
978 | ||
979 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); | |
980 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); | |
981 | ||
982 | while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { | |
983 | if (cur_cnt--) { | |
89db4ad8 | 984 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
985 | occup = REG_RD(bp, regs->lines_occup); |
986 | freed = REG_RD(bp, regs->lines_freed); | |
987 | } else { | |
988 | DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", | |
989 | regs->pN); | |
990 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", | |
991 | regs->pN, occup); | |
992 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", | |
993 | regs->pN, freed); | |
994 | break; | |
995 | } | |
996 | } | |
997 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", | |
89db4ad8 | 998 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
999 | } |
1000 | ||
1191cb83 ED |
1001 | static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, |
1002 | u32 expected, u32 poll_count) | |
619c5cb6 VZ |
1003 | { |
1004 | u32 cur_cnt = poll_count; | |
1005 | u32 val; | |
1006 | ||
1007 | while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) | |
89db4ad8 | 1008 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1009 | |
1010 | return val; | |
1011 | } | |
1012 | ||
1191cb83 ED |
1013 | static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, |
1014 | char *msg, u32 poll_cnt) | |
619c5cb6 VZ |
1015 | { |
1016 | u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); | |
1017 | if (val != 0) { | |
1018 | BNX2X_ERR("%s usage count=%d\n", msg, val); | |
1019 | return 1; | |
1020 | } | |
1021 | return 0; | |
1022 | } | |
1023 | ||
1024 | static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) | |
1025 | { | |
1026 | /* adjust polling timeout */ | |
1027 | if (CHIP_REV_IS_EMUL(bp)) | |
1028 | return FLR_POLL_CNT * 2000; | |
1029 | ||
1030 | if (CHIP_REV_IS_FPGA(bp)) | |
1031 | return FLR_POLL_CNT * 120; | |
1032 | ||
1033 | return FLR_POLL_CNT; | |
1034 | } | |
1035 | ||
1036 | static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) | |
1037 | { | |
1038 | struct pbf_pN_cmd_regs cmd_regs[] = { | |
1039 | {0, (CHIP_IS_E3B0(bp)) ? | |
1040 | PBF_REG_TQ_OCCUPANCY_Q0 : | |
1041 | PBF_REG_P0_TQ_OCCUPANCY, | |
1042 | (CHIP_IS_E3B0(bp)) ? | |
1043 | PBF_REG_TQ_LINES_FREED_CNT_Q0 : | |
1044 | PBF_REG_P0_TQ_LINES_FREED_CNT}, | |
1045 | {1, (CHIP_IS_E3B0(bp)) ? | |
1046 | PBF_REG_TQ_OCCUPANCY_Q1 : | |
1047 | PBF_REG_P1_TQ_OCCUPANCY, | |
1048 | (CHIP_IS_E3B0(bp)) ? | |
1049 | PBF_REG_TQ_LINES_FREED_CNT_Q1 : | |
1050 | PBF_REG_P1_TQ_LINES_FREED_CNT}, | |
1051 | {4, (CHIP_IS_E3B0(bp)) ? | |
1052 | PBF_REG_TQ_OCCUPANCY_LB_Q : | |
1053 | PBF_REG_P4_TQ_OCCUPANCY, | |
1054 | (CHIP_IS_E3B0(bp)) ? | |
1055 | PBF_REG_TQ_LINES_FREED_CNT_LB_Q : | |
1056 | PBF_REG_P4_TQ_LINES_FREED_CNT} | |
1057 | }; | |
1058 | ||
1059 | struct pbf_pN_buf_regs buf_regs[] = { | |
1060 | {0, (CHIP_IS_E3B0(bp)) ? | |
1061 | PBF_REG_INIT_CRD_Q0 : | |
1062 | PBF_REG_P0_INIT_CRD , | |
1063 | (CHIP_IS_E3B0(bp)) ? | |
1064 | PBF_REG_CREDIT_Q0 : | |
1065 | PBF_REG_P0_CREDIT, | |
1066 | (CHIP_IS_E3B0(bp)) ? | |
1067 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : | |
1068 | PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, | |
1069 | {1, (CHIP_IS_E3B0(bp)) ? | |
1070 | PBF_REG_INIT_CRD_Q1 : | |
1071 | PBF_REG_P1_INIT_CRD, | |
1072 | (CHIP_IS_E3B0(bp)) ? | |
1073 | PBF_REG_CREDIT_Q1 : | |
1074 | PBF_REG_P1_CREDIT, | |
1075 | (CHIP_IS_E3B0(bp)) ? | |
1076 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : | |
1077 | PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, | |
1078 | {4, (CHIP_IS_E3B0(bp)) ? | |
1079 | PBF_REG_INIT_CRD_LB_Q : | |
1080 | PBF_REG_P4_INIT_CRD, | |
1081 | (CHIP_IS_E3B0(bp)) ? | |
1082 | PBF_REG_CREDIT_LB_Q : | |
1083 | PBF_REG_P4_CREDIT, | |
1084 | (CHIP_IS_E3B0(bp)) ? | |
1085 | PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : | |
1086 | PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, | |
1087 | }; | |
1088 | ||
1089 | int i; | |
1090 | ||
1091 | /* Verify the command queues are flushed P0, P1, P4 */ | |
1092 | for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) | |
1093 | bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); | |
1094 | ||
1095 | ||
1096 | /* Verify the transmission buffers are flushed P0, P1, P4 */ | |
1097 | for (i = 0; i < ARRAY_SIZE(buf_regs); i++) | |
1098 | bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); | |
1099 | } | |
1100 | ||
1101 | #define OP_GEN_PARAM(param) \ | |
1102 | (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) | |
1103 | ||
1104 | #define OP_GEN_TYPE(type) \ | |
1105 | (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) | |
1106 | ||
1107 | #define OP_GEN_AGG_VECT(index) \ | |
1108 | (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) | |
1109 | ||
1110 | ||
1191cb83 | 1111 | static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, |
619c5cb6 VZ |
1112 | u32 poll_cnt) |
1113 | { | |
1114 | struct sdm_op_gen op_gen = {0}; | |
1115 | ||
1116 | u32 comp_addr = BAR_CSTRORM_INTMEM + | |
1117 | CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); | |
1118 | int ret = 0; | |
1119 | ||
1120 | if (REG_RD(bp, comp_addr)) { | |
89db4ad8 | 1121 | BNX2X_ERR("Cleanup complete was not 0 before sending\n"); |
619c5cb6 VZ |
1122 | return 1; |
1123 | } | |
1124 | ||
1125 | op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); | |
1126 | op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); | |
1127 | op_gen.command |= OP_GEN_AGG_VECT(clnup_func); | |
1128 | op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; | |
1129 | ||
89db4ad8 | 1130 | DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); |
619c5cb6 VZ |
1131 | REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); |
1132 | ||
1133 | if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { | |
1134 | BNX2X_ERR("FW final cleanup did not succeed\n"); | |
51c1a580 MS |
1135 | DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", |
1136 | (REG_RD(bp, comp_addr))); | |
619c5cb6 VZ |
1137 | ret = 1; |
1138 | } | |
1139 | /* Zero completion for nxt FLR */ | |
1140 | REG_WR(bp, comp_addr, 0); | |
1141 | ||
1142 | return ret; | |
1143 | } | |
1144 | ||
1191cb83 | 1145 | static u8 bnx2x_is_pcie_pending(struct pci_dev *dev) |
619c5cb6 VZ |
1146 | { |
1147 | int pos; | |
1148 | u16 status; | |
1149 | ||
77c98e6a | 1150 | pos = pci_pcie_cap(dev); |
619c5cb6 VZ |
1151 | if (!pos) |
1152 | return false; | |
1153 | ||
1154 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); | |
1155 | return status & PCI_EXP_DEVSTA_TRPND; | |
1156 | } | |
1157 | ||
1158 | /* PF FLR specific routines | |
1159 | */ | |
1160 | static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) | |
1161 | { | |
1162 | ||
1163 | /* wait for CFC PF usage-counter to zero (includes all the VFs) */ | |
1164 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1165 | CFC_REG_NUM_LCIDS_INSIDE_PF, | |
1166 | "CFC PF usage counter timed out", | |
1167 | poll_cnt)) | |
1168 | return 1; | |
1169 | ||
1170 | ||
1171 | /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ | |
1172 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1173 | DORQ_REG_PF_USAGE_CNT, | |
1174 | "DQ PF usage counter timed out", | |
1175 | poll_cnt)) | |
1176 | return 1; | |
1177 | ||
1178 | /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ | |
1179 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1180 | QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), | |
1181 | "QM PF usage counter timed out", | |
1182 | poll_cnt)) | |
1183 | return 1; | |
1184 | ||
1185 | /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ | |
1186 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1187 | TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), | |
1188 | "Timers VNIC usage counter timed out", | |
1189 | poll_cnt)) | |
1190 | return 1; | |
1191 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1192 | TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), | |
1193 | "Timers NUM_SCANS usage counter timed out", | |
1194 | poll_cnt)) | |
1195 | return 1; | |
1196 | ||
1197 | /* Wait DMAE PF usage counter to zero */ | |
1198 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1199 | dmae_reg_go_c[INIT_DMAE_C(bp)], | |
1200 | "DMAE dommand register timed out", | |
1201 | poll_cnt)) | |
1202 | return 1; | |
1203 | ||
1204 | return 0; | |
1205 | } | |
1206 | ||
1207 | static void bnx2x_hw_enable_status(struct bnx2x *bp) | |
1208 | { | |
1209 | u32 val; | |
1210 | ||
1211 | val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); | |
1212 | DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); | |
1213 | ||
1214 | val = REG_RD(bp, PBF_REG_DISABLE_PF); | |
1215 | DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); | |
1216 | ||
1217 | val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); | |
1218 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); | |
1219 | ||
1220 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); | |
1221 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); | |
1222 | ||
1223 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); | |
1224 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); | |
1225 | ||
1226 | val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); | |
1227 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); | |
1228 | ||
1229 | val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); | |
1230 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); | |
1231 | ||
1232 | val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
1233 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", | |
1234 | val); | |
1235 | } | |
1236 | ||
1237 | static int bnx2x_pf_flr_clnup(struct bnx2x *bp) | |
1238 | { | |
1239 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); | |
1240 | ||
1241 | DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); | |
1242 | ||
1243 | /* Re-enable PF target read access */ | |
1244 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
1245 | ||
1246 | /* Poll HW usage counters */ | |
89db4ad8 | 1247 | DP(BNX2X_MSG_SP, "Polling usage counters\n"); |
619c5cb6 VZ |
1248 | if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) |
1249 | return -EBUSY; | |
1250 | ||
1251 | /* Zero the igu 'trailing edge' and 'leading edge' */ | |
1252 | ||
1253 | /* Send the FW cleanup command */ | |
1254 | if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) | |
1255 | return -EBUSY; | |
1256 | ||
1257 | /* ATC cleanup */ | |
1258 | ||
1259 | /* Verify TX hw is flushed */ | |
1260 | bnx2x_tx_hw_flushed(bp, poll_cnt); | |
1261 | ||
1262 | /* Wait 100ms (not adjusted according to platform) */ | |
1263 | msleep(100); | |
1264 | ||
1265 | /* Verify no pending pci transactions */ | |
1266 | if (bnx2x_is_pcie_pending(bp->pdev)) | |
1267 | BNX2X_ERR("PCIE Transactions still pending\n"); | |
1268 | ||
1269 | /* Debug */ | |
1270 | bnx2x_hw_enable_status(bp); | |
1271 | ||
1272 | /* | |
1273 | * Master enable - Due to WB DMAE writes performed before this | |
1274 | * register is re-initialized as part of the regular function init | |
1275 | */ | |
1276 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
1277 | ||
1278 | return 0; | |
1279 | } | |
1280 | ||
f2e0899f | 1281 | static void bnx2x_hc_int_enable(struct bnx2x *bp) |
a2fbb9ea | 1282 | { |
34f80b04 | 1283 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1284 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1285 | u32 val = REG_RD(bp, addr); | |
69c326b3 DK |
1286 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1287 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1288 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
a2fbb9ea ET |
1289 | |
1290 | if (msix) { | |
8badd27a EG |
1291 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
1292 | HC_CONFIG_0_REG_INT_LINE_EN_0); | |
a2fbb9ea ET |
1293 | val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
1294 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
69c326b3 DK |
1295 | if (single_msix) |
1296 | val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; | |
8badd27a EG |
1297 | } else if (msi) { |
1298 | val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; | |
1299 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1300 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1301 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1302 | } else { |
1303 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
615f8fd9 | 1304 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
a2fbb9ea ET |
1305 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
1306 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
615f8fd9 | 1307 | |
a0fd065c | 1308 | if (!CHIP_IS_E1(bp)) { |
51c1a580 MS |
1309 | DP(NETIF_MSG_IFUP, |
1310 | "write %x to HC %d (addr 0x%x)\n", val, port, addr); | |
615f8fd9 | 1311 | |
a0fd065c | 1312 | REG_WR(bp, addr, val); |
615f8fd9 | 1313 | |
a0fd065c DK |
1314 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
1315 | } | |
a2fbb9ea ET |
1316 | } |
1317 | ||
a0fd065c DK |
1318 | if (CHIP_IS_E1(bp)) |
1319 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); | |
1320 | ||
51c1a580 MS |
1321 | DP(NETIF_MSG_IFUP, |
1322 | "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, | |
1323 | (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
a2fbb9ea ET |
1324 | |
1325 | REG_WR(bp, addr, val); | |
37dbbf32 EG |
1326 | /* |
1327 | * Ensure that HC_CONFIG is written before leading/trailing edge config | |
1328 | */ | |
1329 | mmiowb(); | |
1330 | barrier(); | |
34f80b04 | 1331 | |
f2e0899f | 1332 | if (!CHIP_IS_E1(bp)) { |
34f80b04 | 1333 | /* init leading/trailing edge */ |
fb3bff17 | 1334 | if (IS_MF(bp)) { |
3395a033 | 1335 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
34f80b04 | 1336 | if (bp->port.pmf) |
4acac6a5 EG |
1337 | /* enable nig and gpio3 attention */ |
1338 | val |= 0x1100; | |
34f80b04 EG |
1339 | } else |
1340 | val = 0xffff; | |
1341 | ||
1342 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
1343 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
1344 | } | |
37dbbf32 EG |
1345 | |
1346 | /* Make sure that interrupts are indeed enabled from here on */ | |
1347 | mmiowb(); | |
a2fbb9ea ET |
1348 | } |
1349 | ||
f2e0899f DK |
1350 | static void bnx2x_igu_int_enable(struct bnx2x *bp) |
1351 | { | |
1352 | u32 val; | |
30a5de77 DK |
1353 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1354 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1355 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
f2e0899f DK |
1356 | |
1357 | val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1358 | ||
1359 | if (msix) { | |
1360 | val &= ~(IGU_PF_CONF_INT_LINE_EN | | |
1361 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1362 | val |= (IGU_PF_CONF_FUNC_EN | | |
1363 | IGU_PF_CONF_MSI_MSIX_EN | | |
1364 | IGU_PF_CONF_ATTN_BIT_EN); | |
30a5de77 DK |
1365 | |
1366 | if (single_msix) | |
1367 | val |= IGU_PF_CONF_SINGLE_ISR_EN; | |
f2e0899f DK |
1368 | } else if (msi) { |
1369 | val &= ~IGU_PF_CONF_INT_LINE_EN; | |
1370 | val |= (IGU_PF_CONF_FUNC_EN | | |
1371 | IGU_PF_CONF_MSI_MSIX_EN | | |
1372 | IGU_PF_CONF_ATTN_BIT_EN | | |
1373 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1374 | } else { | |
1375 | val &= ~IGU_PF_CONF_MSI_MSIX_EN; | |
1376 | val |= (IGU_PF_CONF_FUNC_EN | | |
1377 | IGU_PF_CONF_INT_LINE_EN | | |
1378 | IGU_PF_CONF_ATTN_BIT_EN | | |
1379 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1380 | } | |
1381 | ||
51c1a580 | 1382 | DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", |
f2e0899f DK |
1383 | val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); |
1384 | ||
1385 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1386 | ||
79a8557a YM |
1387 | if (val & IGU_PF_CONF_INT_LINE_EN) |
1388 | pci_intx(bp->pdev, true); | |
1389 | ||
f2e0899f DK |
1390 | barrier(); |
1391 | ||
1392 | /* init leading/trailing edge */ | |
1393 | if (IS_MF(bp)) { | |
3395a033 | 1394 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
1395 | if (bp->port.pmf) |
1396 | /* enable nig and gpio3 attention */ | |
1397 | val |= 0x1100; | |
1398 | } else | |
1399 | val = 0xffff; | |
1400 | ||
1401 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); | |
1402 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
1403 | ||
1404 | /* Make sure that interrupts are indeed enabled from here on */ | |
1405 | mmiowb(); | |
1406 | } | |
1407 | ||
1408 | void bnx2x_int_enable(struct bnx2x *bp) | |
1409 | { | |
1410 | if (bp->common.int_block == INT_BLOCK_HC) | |
1411 | bnx2x_hc_int_enable(bp); | |
1412 | else | |
1413 | bnx2x_igu_int_enable(bp); | |
1414 | } | |
1415 | ||
1416 | static void bnx2x_hc_int_disable(struct bnx2x *bp) | |
a2fbb9ea | 1417 | { |
34f80b04 | 1418 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1419 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1420 | u32 val = REG_RD(bp, addr); | |
1421 | ||
a0fd065c DK |
1422 | /* |
1423 | * in E1 we must use only PCI configuration space to disable | |
1424 | * MSI/MSIX capablility | |
1425 | * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block | |
1426 | */ | |
1427 | if (CHIP_IS_E1(bp)) { | |
1428 | /* Since IGU_PF_CONF_MSI_MSIX_EN still always on | |
1429 | * Use mask register to prevent from HC sending interrupts | |
1430 | * after we exit the function | |
1431 | */ | |
1432 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0); | |
1433 | ||
1434 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1435 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1436 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
1437 | } else | |
1438 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1439 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1440 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1441 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea | 1442 | |
51c1a580 MS |
1443 | DP(NETIF_MSG_IFDOWN, |
1444 | "write %x to HC %d (addr 0x%x)\n", | |
a2fbb9ea ET |
1445 | val, port, addr); |
1446 | ||
8badd27a EG |
1447 | /* flush all outstanding writes */ |
1448 | mmiowb(); | |
1449 | ||
a2fbb9ea ET |
1450 | REG_WR(bp, addr, val); |
1451 | if (REG_RD(bp, addr) != val) | |
1452 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1453 | } | |
1454 | ||
f2e0899f DK |
1455 | static void bnx2x_igu_int_disable(struct bnx2x *bp) |
1456 | { | |
1457 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1458 | ||
1459 | val &= ~(IGU_PF_CONF_MSI_MSIX_EN | | |
1460 | IGU_PF_CONF_INT_LINE_EN | | |
1461 | IGU_PF_CONF_ATTN_BIT_EN); | |
1462 | ||
51c1a580 | 1463 | DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); |
f2e0899f DK |
1464 | |
1465 | /* flush all outstanding writes */ | |
1466 | mmiowb(); | |
1467 | ||
1468 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1469 | if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) | |
1470 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1471 | } | |
1472 | ||
6383c0b3 | 1473 | void bnx2x_int_disable(struct bnx2x *bp) |
f2e0899f DK |
1474 | { |
1475 | if (bp->common.int_block == INT_BLOCK_HC) | |
1476 | bnx2x_hc_int_disable(bp); | |
1477 | else | |
1478 | bnx2x_igu_int_disable(bp); | |
1479 | } | |
1480 | ||
9f6c9258 | 1481 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) |
a2fbb9ea | 1482 | { |
a2fbb9ea | 1483 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
8badd27a | 1484 | int i, offset; |
a2fbb9ea | 1485 | |
f8ef6e44 YG |
1486 | if (disable_hw) |
1487 | /* prevent the HW from sending interrupts */ | |
1488 | bnx2x_int_disable(bp); | |
a2fbb9ea ET |
1489 | |
1490 | /* make sure all ISRs are done */ | |
1491 | if (msix) { | |
8badd27a EG |
1492 | synchronize_irq(bp->msix_table[0].vector); |
1493 | offset = 1; | |
37b091ba MC |
1494 | #ifdef BCM_CNIC |
1495 | offset++; | |
1496 | #endif | |
ec6ba945 | 1497 | for_each_eth_queue(bp, i) |
754a2f52 | 1498 | synchronize_irq(bp->msix_table[offset++].vector); |
a2fbb9ea ET |
1499 | } else |
1500 | synchronize_irq(bp->pdev->irq); | |
1501 | ||
1502 | /* make sure sp_task is not running */ | |
1cf167f2 | 1503 | cancel_delayed_work(&bp->sp_task); |
3deb8167 | 1504 | cancel_delayed_work(&bp->period_task); |
1cf167f2 | 1505 | flush_workqueue(bnx2x_wq); |
a2fbb9ea ET |
1506 | } |
1507 | ||
34f80b04 | 1508 | /* fast path */ |
a2fbb9ea ET |
1509 | |
1510 | /* | |
34f80b04 | 1511 | * General service functions |
a2fbb9ea ET |
1512 | */ |
1513 | ||
72fd0718 VZ |
1514 | /* Return true if succeeded to acquire the lock */ |
1515 | static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) | |
1516 | { | |
1517 | u32 lock_status; | |
1518 | u32 resource_bit = (1 << resource); | |
1519 | int func = BP_FUNC(bp); | |
1520 | u32 hw_lock_control_reg; | |
1521 | ||
51c1a580 MS |
1522 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1523 | "Trying to take a lock on resource %d\n", resource); | |
72fd0718 VZ |
1524 | |
1525 | /* Validating that the resource is within range */ | |
1526 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1527 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
72fd0718 VZ |
1528 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
1529 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
0fdf4d09 | 1530 | return false; |
72fd0718 VZ |
1531 | } |
1532 | ||
1533 | if (func <= 5) | |
1534 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1535 | else | |
1536 | hw_lock_control_reg = | |
1537 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1538 | ||
1539 | /* Try to acquire the lock */ | |
1540 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); | |
1541 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
1542 | if (lock_status & resource_bit) | |
1543 | return true; | |
1544 | ||
51c1a580 MS |
1545 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1546 | "Failed to get a lock on resource %d\n", resource); | |
72fd0718 VZ |
1547 | return false; |
1548 | } | |
1549 | ||
c9ee9206 VZ |
1550 | /** |
1551 | * bnx2x_get_leader_lock_resource - get the recovery leader resource id | |
1552 | * | |
1553 | * @bp: driver handle | |
1554 | * | |
1555 | * Returns the recovery leader resource id according to the engine this function | |
1556 | * belongs to. Currently only only 2 engines is supported. | |
1557 | */ | |
1191cb83 | 1558 | static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) |
c9ee9206 VZ |
1559 | { |
1560 | if (BP_PATH(bp)) | |
1561 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; | |
1562 | else | |
1563 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; | |
1564 | } | |
1565 | ||
1566 | /** | |
1567 | * bnx2x_trylock_leader_lock- try to aquire a leader lock. | |
1568 | * | |
1569 | * @bp: driver handle | |
1570 | * | |
1191cb83 | 1571 | * Tries to aquire a leader lock for current engine. |
c9ee9206 | 1572 | */ |
1191cb83 | 1573 | static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) |
c9ee9206 VZ |
1574 | { |
1575 | return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1576 | } | |
1577 | ||
993ac7b5 | 1578 | #ifdef BCM_CNIC |
619c5cb6 | 1579 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); |
993ac7b5 | 1580 | #endif |
3196a88a | 1581 | |
619c5cb6 | 1582 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) |
a2fbb9ea ET |
1583 | { |
1584 | struct bnx2x *bp = fp->bp; | |
1585 | int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
1586 | int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
619c5cb6 | 1587 | enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; |
15192a8c | 1588 | struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a2fbb9ea | 1589 | |
34f80b04 | 1590 | DP(BNX2X_MSG_SP, |
a2fbb9ea | 1591 | "fp %d cid %d got ramrod #%d state is %x type is %d\n", |
0626b899 | 1592 | fp->index, cid, command, bp->state, |
34f80b04 | 1593 | rr_cqe->ramrod_cqe.ramrod_type); |
a2fbb9ea | 1594 | |
619c5cb6 VZ |
1595 | switch (command) { |
1596 | case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): | |
d6cae238 | 1597 | DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); |
619c5cb6 VZ |
1598 | drv_cmd = BNX2X_Q_CMD_UPDATE; |
1599 | break; | |
d6cae238 | 1600 | |
619c5cb6 | 1601 | case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): |
d6cae238 | 1602 | DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); |
619c5cb6 | 1603 | drv_cmd = BNX2X_Q_CMD_SETUP; |
a2fbb9ea ET |
1604 | break; |
1605 | ||
6383c0b3 | 1606 | case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): |
51c1a580 | 1607 | DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); |
6383c0b3 AE |
1608 | drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; |
1609 | break; | |
1610 | ||
619c5cb6 | 1611 | case (RAMROD_CMD_ID_ETH_HALT): |
d6cae238 | 1612 | DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); |
619c5cb6 | 1613 | drv_cmd = BNX2X_Q_CMD_HALT; |
a2fbb9ea ET |
1614 | break; |
1615 | ||
619c5cb6 | 1616 | case (RAMROD_CMD_ID_ETH_TERMINATE): |
d6cae238 | 1617 | DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); |
619c5cb6 | 1618 | drv_cmd = BNX2X_Q_CMD_TERMINATE; |
a2fbb9ea ET |
1619 | break; |
1620 | ||
619c5cb6 | 1621 | case (RAMROD_CMD_ID_ETH_EMPTY): |
d6cae238 | 1622 | DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); |
619c5cb6 | 1623 | drv_cmd = BNX2X_Q_CMD_EMPTY; |
993ac7b5 | 1624 | break; |
619c5cb6 VZ |
1625 | |
1626 | default: | |
1627 | BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", | |
1628 | command, fp->index); | |
1629 | return; | |
523224a3 | 1630 | } |
3196a88a | 1631 | |
619c5cb6 VZ |
1632 | if ((drv_cmd != BNX2X_Q_CMD_MAX) && |
1633 | q_obj->complete_cmd(bp, q_obj, drv_cmd)) | |
1634 | /* q_obj->complete_cmd() failure means that this was | |
1635 | * an unexpected completion. | |
1636 | * | |
1637 | * In this case we don't want to increase the bp->spq_left | |
1638 | * because apparently we haven't sent this command the first | |
1639 | * place. | |
1640 | */ | |
1641 | #ifdef BNX2X_STOP_ON_ERROR | |
1642 | bnx2x_panic(); | |
1643 | #else | |
1644 | return; | |
1645 | #endif | |
1646 | ||
8fe23fbd | 1647 | smp_mb__before_atomic_inc(); |
6e30dd4e | 1648 | atomic_inc(&bp->cq_spq_left); |
619c5cb6 VZ |
1649 | /* push the change in bp->spq_left and towards the memory */ |
1650 | smp_mb__after_atomic_inc(); | |
49d66772 | 1651 | |
d6cae238 VZ |
1652 | DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); |
1653 | ||
a3348722 BW |
1654 | if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && |
1655 | (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { | |
1656 | /* if Q update ramrod is completed for last Q in AFEX vif set | |
1657 | * flow, then ACK MCP at the end | |
1658 | * | |
1659 | * mark pending ACK to MCP bit. | |
1660 | * prevent case that both bits are cleared. | |
1661 | * At the end of load/unload driver checks that | |
1662 | * sp_state is cleaerd, and this order prevents | |
1663 | * races | |
1664 | */ | |
1665 | smp_mb__before_clear_bit(); | |
1666 | set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); | |
1667 | wmb(); | |
1668 | clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
1669 | smp_mb__after_clear_bit(); | |
1670 | ||
1671 | /* schedule workqueue to send ack to MCP */ | |
1672 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); | |
1673 | } | |
1674 | ||
523224a3 | 1675 | return; |
a2fbb9ea ET |
1676 | } |
1677 | ||
619c5cb6 VZ |
1678 | void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
1679 | u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) | |
1680 | { | |
1681 | u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; | |
1682 | ||
1683 | bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, | |
1684 | start); | |
1685 | } | |
1686 | ||
9f6c9258 | 1687 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) |
a2fbb9ea | 1688 | { |
555f6c78 | 1689 | struct bnx2x *bp = netdev_priv(dev_instance); |
a2fbb9ea | 1690 | u16 status = bnx2x_ack_int(bp); |
34f80b04 | 1691 | u16 mask; |
ca00392c | 1692 | int i; |
6383c0b3 | 1693 | u8 cos; |
a2fbb9ea | 1694 | |
34f80b04 | 1695 | /* Return here if interrupt is shared and it's not for us */ |
a2fbb9ea ET |
1696 | if (unlikely(status == 0)) { |
1697 | DP(NETIF_MSG_INTR, "not our interrupt!\n"); | |
1698 | return IRQ_NONE; | |
1699 | } | |
f5372251 | 1700 | DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); |
a2fbb9ea | 1701 | |
3196a88a EG |
1702 | #ifdef BNX2X_STOP_ON_ERROR |
1703 | if (unlikely(bp->panic)) | |
1704 | return IRQ_HANDLED; | |
1705 | #endif | |
1706 | ||
ec6ba945 | 1707 | for_each_eth_queue(bp, i) { |
ca00392c | 1708 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1709 | |
6383c0b3 | 1710 | mask = 0x2 << (fp->index + CNIC_PRESENT); |
ca00392c | 1711 | if (status & mask) { |
619c5cb6 | 1712 | /* Handle Rx or Tx according to SB id */ |
54b9ddaa | 1713 | prefetch(fp->rx_cons_sb); |
6383c0b3 | 1714 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 1715 | prefetch(fp->txdata_ptr[cos]->tx_cons_sb); |
523224a3 | 1716 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
54b9ddaa | 1717 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); |
ca00392c EG |
1718 | status &= ~mask; |
1719 | } | |
a2fbb9ea ET |
1720 | } |
1721 | ||
993ac7b5 | 1722 | #ifdef BCM_CNIC |
523224a3 | 1723 | mask = 0x2; |
993ac7b5 MC |
1724 | if (status & (mask | 0x1)) { |
1725 | struct cnic_ops *c_ops = NULL; | |
1726 | ||
619c5cb6 VZ |
1727 | if (likely(bp->state == BNX2X_STATE_OPEN)) { |
1728 | rcu_read_lock(); | |
1729 | c_ops = rcu_dereference(bp->cnic_ops); | |
1730 | if (c_ops) | |
1731 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
1732 | rcu_read_unlock(); | |
1733 | } | |
993ac7b5 MC |
1734 | |
1735 | status &= ~mask; | |
1736 | } | |
1737 | #endif | |
a2fbb9ea | 1738 | |
34f80b04 | 1739 | if (unlikely(status & 0x1)) { |
1cf167f2 | 1740 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
a2fbb9ea ET |
1741 | |
1742 | status &= ~0x1; | |
1743 | if (!status) | |
1744 | return IRQ_HANDLED; | |
1745 | } | |
1746 | ||
cdaa7cb8 VZ |
1747 | if (unlikely(status)) |
1748 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
34f80b04 | 1749 | status); |
a2fbb9ea | 1750 | |
c18487ee | 1751 | return IRQ_HANDLED; |
a2fbb9ea ET |
1752 | } |
1753 | ||
c18487ee YR |
1754 | /* Link */ |
1755 | ||
1756 | /* | |
1757 | * General service functions | |
1758 | */ | |
a2fbb9ea | 1759 | |
9f6c9258 | 1760 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1761 | { |
1762 | u32 lock_status; | |
1763 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1764 | int func = BP_FUNC(bp); |
1765 | u32 hw_lock_control_reg; | |
c18487ee | 1766 | int cnt; |
a2fbb9ea | 1767 | |
c18487ee YR |
1768 | /* Validating that the resource is within range */ |
1769 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1770 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1771 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1772 | return -EINVAL; | |
1773 | } | |
a2fbb9ea | 1774 | |
4a37fb66 YG |
1775 | if (func <= 5) { |
1776 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1777 | } else { | |
1778 | hw_lock_control_reg = | |
1779 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1780 | } | |
1781 | ||
c18487ee | 1782 | /* Validating that the resource is not already taken */ |
4a37fb66 | 1783 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 1784 | if (lock_status & resource_bit) { |
51c1a580 | 1785 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", |
c18487ee YR |
1786 | lock_status, resource_bit); |
1787 | return -EEXIST; | |
1788 | } | |
a2fbb9ea | 1789 | |
46230476 EG |
1790 | /* Try for 5 second every 5ms */ |
1791 | for (cnt = 0; cnt < 1000; cnt++) { | |
c18487ee | 1792 | /* Try to acquire the lock */ |
4a37fb66 YG |
1793 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
1794 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
c18487ee YR |
1795 | if (lock_status & resource_bit) |
1796 | return 0; | |
a2fbb9ea | 1797 | |
c18487ee | 1798 | msleep(5); |
a2fbb9ea | 1799 | } |
51c1a580 | 1800 | BNX2X_ERR("Timeout\n"); |
c18487ee YR |
1801 | return -EAGAIN; |
1802 | } | |
a2fbb9ea | 1803 | |
c9ee9206 VZ |
1804 | int bnx2x_release_leader_lock(struct bnx2x *bp) |
1805 | { | |
1806 | return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1807 | } | |
1808 | ||
9f6c9258 | 1809 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1810 | { |
1811 | u32 lock_status; | |
1812 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1813 | int func = BP_FUNC(bp); |
1814 | u32 hw_lock_control_reg; | |
a2fbb9ea | 1815 | |
c18487ee YR |
1816 | /* Validating that the resource is within range */ |
1817 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1818 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1819 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1820 | return -EINVAL; | |
1821 | } | |
1822 | ||
4a37fb66 YG |
1823 | if (func <= 5) { |
1824 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1825 | } else { | |
1826 | hw_lock_control_reg = | |
1827 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1828 | } | |
1829 | ||
c18487ee | 1830 | /* Validating that the resource is currently taken */ |
4a37fb66 | 1831 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 1832 | if (!(lock_status & resource_bit)) { |
51c1a580 | 1833 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n", |
c18487ee YR |
1834 | lock_status, resource_bit); |
1835 | return -EFAULT; | |
a2fbb9ea ET |
1836 | } |
1837 | ||
9f6c9258 DK |
1838 | REG_WR(bp, hw_lock_control_reg, resource_bit); |
1839 | return 0; | |
c18487ee | 1840 | } |
a2fbb9ea | 1841 | |
9f6c9258 | 1842 | |
4acac6a5 EG |
1843 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) |
1844 | { | |
1845 | /* The GPIO should be swapped if swap register is set and active */ | |
1846 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
1847 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
1848 | int gpio_shift = gpio_num + | |
1849 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1850 | u32 gpio_mask = (1 << gpio_shift); | |
1851 | u32 gpio_reg; | |
1852 | int value; | |
1853 | ||
1854 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
1855 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1856 | return -EINVAL; | |
1857 | } | |
1858 | ||
1859 | /* read GPIO value */ | |
1860 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1861 | ||
1862 | /* get the requested pin value */ | |
1863 | if ((gpio_reg & gpio_mask) == gpio_mask) | |
1864 | value = 1; | |
1865 | else | |
1866 | value = 0; | |
1867 | ||
1868 | DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); | |
1869 | ||
1870 | return value; | |
1871 | } | |
1872 | ||
17de50b7 | 1873 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
c18487ee YR |
1874 | { |
1875 | /* The GPIO should be swapped if swap register is set and active */ | |
1876 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
17de50b7 | 1877 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
c18487ee YR |
1878 | int gpio_shift = gpio_num + |
1879 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1880 | u32 gpio_mask = (1 << gpio_shift); | |
1881 | u32 gpio_reg; | |
a2fbb9ea | 1882 | |
c18487ee YR |
1883 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
1884 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1885 | return -EINVAL; | |
1886 | } | |
a2fbb9ea | 1887 | |
4a37fb66 | 1888 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
c18487ee YR |
1889 | /* read GPIO and mask except the float bits */ |
1890 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); | |
a2fbb9ea | 1891 | |
c18487ee YR |
1892 | switch (mode) { |
1893 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
51c1a580 MS |
1894 | DP(NETIF_MSG_LINK, |
1895 | "Set GPIO %d (shift %d) -> output low\n", | |
c18487ee YR |
1896 | gpio_num, gpio_shift); |
1897 | /* clear FLOAT and set CLR */ | |
1898 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1899 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); | |
1900 | break; | |
a2fbb9ea | 1901 | |
c18487ee | 1902 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
51c1a580 MS |
1903 | DP(NETIF_MSG_LINK, |
1904 | "Set GPIO %d (shift %d) -> output high\n", | |
c18487ee YR |
1905 | gpio_num, gpio_shift); |
1906 | /* clear FLOAT and set SET */ | |
1907 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1908 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); | |
1909 | break; | |
a2fbb9ea | 1910 | |
17de50b7 | 1911 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
51c1a580 MS |
1912 | DP(NETIF_MSG_LINK, |
1913 | "Set GPIO %d (shift %d) -> input\n", | |
c18487ee YR |
1914 | gpio_num, gpio_shift); |
1915 | /* set FLOAT */ | |
1916 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1917 | break; | |
a2fbb9ea | 1918 | |
c18487ee YR |
1919 | default: |
1920 | break; | |
a2fbb9ea ET |
1921 | } |
1922 | ||
c18487ee | 1923 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
4a37fb66 | 1924 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
f1410647 | 1925 | |
c18487ee | 1926 | return 0; |
a2fbb9ea ET |
1927 | } |
1928 | ||
0d40f0d4 YR |
1929 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) |
1930 | { | |
1931 | u32 gpio_reg = 0; | |
1932 | int rc = 0; | |
1933 | ||
1934 | /* Any port swapping should be handled by caller. */ | |
1935 | ||
1936 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1937 | /* read GPIO and mask except the float bits */ | |
1938 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1939 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1940 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); | |
1941 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); | |
1942 | ||
1943 | switch (mode) { | |
1944 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
1945 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); | |
1946 | /* set CLR */ | |
1947 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); | |
1948 | break; | |
1949 | ||
1950 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: | |
1951 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); | |
1952 | /* set SET */ | |
1953 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); | |
1954 | break; | |
1955 | ||
1956 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: | |
1957 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); | |
1958 | /* set FLOAT */ | |
1959 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1960 | break; | |
1961 | ||
1962 | default: | |
1963 | BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); | |
1964 | rc = -EINVAL; | |
1965 | break; | |
1966 | } | |
1967 | ||
1968 | if (rc == 0) | |
1969 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); | |
1970 | ||
1971 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1972 | ||
1973 | return rc; | |
1974 | } | |
1975 | ||
4acac6a5 EG |
1976 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
1977 | { | |
1978 | /* The GPIO should be swapped if swap register is set and active */ | |
1979 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
1980 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
1981 | int gpio_shift = gpio_num + | |
1982 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1983 | u32 gpio_mask = (1 << gpio_shift); | |
1984 | u32 gpio_reg; | |
1985 | ||
1986 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
1987 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1988 | return -EINVAL; | |
1989 | } | |
1990 | ||
1991 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1992 | /* read GPIO int */ | |
1993 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); | |
1994 | ||
1995 | switch (mode) { | |
1996 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: | |
51c1a580 MS |
1997 | DP(NETIF_MSG_LINK, |
1998 | "Clear GPIO INT %d (shift %d) -> output low\n", | |
1999 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2000 | /* clear SET and set CLR */ |
2001 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2002 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2003 | break; | |
2004 | ||
2005 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: | |
51c1a580 MS |
2006 | DP(NETIF_MSG_LINK, |
2007 | "Set GPIO INT %d (shift %d) -> output high\n", | |
2008 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2009 | /* clear CLR and set SET */ |
2010 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2011 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2012 | break; | |
2013 | ||
2014 | default: | |
2015 | break; | |
2016 | } | |
2017 | ||
2018 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); | |
2019 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2020 | ||
2021 | return 0; | |
2022 | } | |
2023 | ||
c18487ee | 2024 | static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) |
a2fbb9ea | 2025 | { |
c18487ee YR |
2026 | u32 spio_mask = (1 << spio_num); |
2027 | u32 spio_reg; | |
a2fbb9ea | 2028 | |
c18487ee YR |
2029 | if ((spio_num < MISC_REGISTERS_SPIO_4) || |
2030 | (spio_num > MISC_REGISTERS_SPIO_7)) { | |
2031 | BNX2X_ERR("Invalid SPIO %d\n", spio_num); | |
2032 | return -EINVAL; | |
a2fbb9ea ET |
2033 | } |
2034 | ||
4a37fb66 | 2035 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee YR |
2036 | /* read SPIO and mask except the float bits */ |
2037 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); | |
a2fbb9ea | 2038 | |
c18487ee | 2039 | switch (mode) { |
6378c025 | 2040 | case MISC_REGISTERS_SPIO_OUTPUT_LOW: |
51c1a580 | 2041 | DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num); |
c18487ee YR |
2042 | /* clear FLOAT and set CLR */ |
2043 | spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2044 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); | |
2045 | break; | |
a2fbb9ea | 2046 | |
6378c025 | 2047 | case MISC_REGISTERS_SPIO_OUTPUT_HIGH: |
51c1a580 | 2048 | DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num); |
c18487ee YR |
2049 | /* clear FLOAT and set SET */ |
2050 | spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2051 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); | |
2052 | break; | |
a2fbb9ea | 2053 | |
c18487ee | 2054 | case MISC_REGISTERS_SPIO_INPUT_HI_Z: |
51c1a580 | 2055 | DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num); |
c18487ee YR |
2056 | /* set FLOAT */ |
2057 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2058 | break; | |
a2fbb9ea | 2059 | |
c18487ee YR |
2060 | default: |
2061 | break; | |
a2fbb9ea ET |
2062 | } |
2063 | ||
c18487ee | 2064 | REG_WR(bp, MISC_REG_SPIO, spio_reg); |
4a37fb66 | 2065 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2066 | |
a2fbb9ea ET |
2067 | return 0; |
2068 | } | |
2069 | ||
9f6c9258 | 2070 | void bnx2x_calc_fc_adv(struct bnx2x *bp) |
a2fbb9ea | 2071 | { |
a22f0788 | 2072 | u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
ad33ea3a EG |
2073 | switch (bp->link_vars.ieee_fc & |
2074 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { | |
c18487ee | 2075 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: |
a22f0788 | 2076 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2077 | ADVERTISED_Pause); |
c18487ee | 2078 | break; |
356e2385 | 2079 | |
c18487ee | 2080 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: |
a22f0788 | 2081 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | |
f85582f8 | 2082 | ADVERTISED_Pause); |
c18487ee | 2083 | break; |
356e2385 | 2084 | |
c18487ee | 2085 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: |
a22f0788 | 2086 | bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; |
c18487ee | 2087 | break; |
356e2385 | 2088 | |
c18487ee | 2089 | default: |
a22f0788 | 2090 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2091 | ADVERTISED_Pause); |
c18487ee YR |
2092 | break; |
2093 | } | |
2094 | } | |
f1410647 | 2095 | |
9f6c9258 | 2096 | u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) |
c18487ee | 2097 | { |
19680c48 EG |
2098 | if (!BP_NOMCP(bp)) { |
2099 | u8 rc; | |
a22f0788 YR |
2100 | int cfx_idx = bnx2x_get_link_cfg_idx(bp); |
2101 | u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; | |
1cb0c788 YR |
2102 | /* |
2103 | * Initialize link parameters structure variables | |
2104 | * It is recommended to turn off RX FC for jumbo frames | |
2105 | * for better performance | |
2106 | */ | |
2107 | if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) | |
c0700f90 | 2108 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; |
8c99e7b0 | 2109 | else |
c0700f90 | 2110 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; |
a2fbb9ea | 2111 | |
4a37fb66 | 2112 | bnx2x_acquire_phy_lock(bp); |
b5bf9068 | 2113 | |
a22f0788 | 2114 | if (load_mode == LOAD_DIAG) { |
1cb0c788 YR |
2115 | struct link_params *lp = &bp->link_params; |
2116 | lp->loopback_mode = LOOPBACK_XGXS; | |
2117 | /* do PHY loopback at 10G speed, if possible */ | |
2118 | if (lp->req_line_speed[cfx_idx] < SPEED_10000) { | |
2119 | if (lp->speed_cap_mask[cfx_idx] & | |
2120 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
2121 | lp->req_line_speed[cfx_idx] = | |
2122 | SPEED_10000; | |
2123 | else | |
2124 | lp->req_line_speed[cfx_idx] = | |
2125 | SPEED_1000; | |
2126 | } | |
a22f0788 | 2127 | } |
b5bf9068 | 2128 | |
8970b2e4 MS |
2129 | if (load_mode == LOAD_LOOPBACK_EXT) { |
2130 | struct link_params *lp = &bp->link_params; | |
2131 | lp->loopback_mode = LOOPBACK_EXT; | |
2132 | } | |
2133 | ||
19680c48 | 2134 | rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
b5bf9068 | 2135 | |
4a37fb66 | 2136 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2137 | |
3c96c68b EG |
2138 | bnx2x_calc_fc_adv(bp); |
2139 | ||
b5bf9068 EG |
2140 | if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { |
2141 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
19680c48 | 2142 | bnx2x_link_report(bp); |
3deb8167 YR |
2143 | } else |
2144 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
a22f0788 | 2145 | bp->link_params.req_line_speed[cfx_idx] = req_line_speed; |
19680c48 EG |
2146 | return rc; |
2147 | } | |
f5372251 | 2148 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
19680c48 | 2149 | return -EINVAL; |
a2fbb9ea ET |
2150 | } |
2151 | ||
9f6c9258 | 2152 | void bnx2x_link_set(struct bnx2x *bp) |
a2fbb9ea | 2153 | { |
19680c48 | 2154 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2155 | bnx2x_acquire_phy_lock(bp); |
54c2fb78 | 2156 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); |
19680c48 | 2157 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2158 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2159 | |
19680c48 EG |
2160 | bnx2x_calc_fc_adv(bp); |
2161 | } else | |
f5372251 | 2162 | BNX2X_ERR("Bootcode is missing - can not set link\n"); |
c18487ee | 2163 | } |
a2fbb9ea | 2164 | |
c18487ee YR |
2165 | static void bnx2x__link_reset(struct bnx2x *bp) |
2166 | { | |
19680c48 | 2167 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2168 | bnx2x_acquire_phy_lock(bp); |
589abe3a | 2169 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); |
4a37fb66 | 2170 | bnx2x_release_phy_lock(bp); |
19680c48 | 2171 | } else |
f5372251 | 2172 | BNX2X_ERR("Bootcode is missing - can not reset link\n"); |
c18487ee | 2173 | } |
a2fbb9ea | 2174 | |
a22f0788 | 2175 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) |
c18487ee | 2176 | { |
2145a920 | 2177 | u8 rc = 0; |
a2fbb9ea | 2178 | |
2145a920 VZ |
2179 | if (!BP_NOMCP(bp)) { |
2180 | bnx2x_acquire_phy_lock(bp); | |
a22f0788 YR |
2181 | rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, |
2182 | is_serdes); | |
2145a920 VZ |
2183 | bnx2x_release_phy_lock(bp); |
2184 | } else | |
2185 | BNX2X_ERR("Bootcode is missing - can not test link\n"); | |
a2fbb9ea | 2186 | |
c18487ee YR |
2187 | return rc; |
2188 | } | |
a2fbb9ea | 2189 | |
34f80b04 | 2190 | |
2691d51d EG |
2191 | /* Calculates the sum of vn_min_rates. |
2192 | It's needed for further normalizing of the min_rates. | |
2193 | Returns: | |
2194 | sum of vn_min_rates. | |
2195 | or | |
2196 | 0 - if all the min_rates are 0. | |
2197 | In the later case fainess algorithm should be deactivated. | |
2198 | If not all min_rates are zero then those that are zeroes will be set to 1. | |
2199 | */ | |
b475d78f YM |
2200 | static void bnx2x_calc_vn_min(struct bnx2x *bp, |
2201 | struct cmng_init_input *input) | |
2691d51d EG |
2202 | { |
2203 | int all_zero = 1; | |
2691d51d EG |
2204 | int vn; |
2205 | ||
3395a033 | 2206 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
f2e0899f | 2207 | u32 vn_cfg = bp->mf_config[vn]; |
2691d51d EG |
2208 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2209 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
2210 | ||
2211 | /* Skip hidden vns */ | |
2212 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) | |
b475d78f | 2213 | vn_min_rate = 0; |
2691d51d | 2214 | /* If min rate is zero - set it to 1 */ |
b475d78f | 2215 | else if (!vn_min_rate) |
2691d51d EG |
2216 | vn_min_rate = DEF_MIN_RATE; |
2217 | else | |
2218 | all_zero = 0; | |
2219 | ||
b475d78f | 2220 | input->vnic_min_rate[vn] = vn_min_rate; |
2691d51d EG |
2221 | } |
2222 | ||
30ae438b DK |
2223 | /* if ETS or all min rates are zeros - disable fairness */ |
2224 | if (BNX2X_IS_ETS_ENABLED(bp)) { | |
b475d78f | 2225 | input->flags.cmng_enables &= |
30ae438b DK |
2226 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2227 | DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); | |
2228 | } else if (all_zero) { | |
b475d78f | 2229 | input->flags.cmng_enables &= |
b015e3d1 | 2230 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
b475d78f YM |
2231 | DP(NETIF_MSG_IFUP, |
2232 | "All MIN values are zeroes fairness will be disabled\n"); | |
b015e3d1 | 2233 | } else |
b475d78f | 2234 | input->flags.cmng_enables |= |
b015e3d1 | 2235 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2691d51d EG |
2236 | } |
2237 | ||
b475d78f YM |
2238 | static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, |
2239 | struct cmng_init_input *input) | |
34f80b04 | 2240 | { |
b475d78f | 2241 | u16 vn_max_rate; |
f2e0899f | 2242 | u32 vn_cfg = bp->mf_config[vn]; |
34f80b04 | 2243 | |
b475d78f | 2244 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) |
34f80b04 | 2245 | vn_max_rate = 0; |
b475d78f | 2246 | else { |
faa6fcbb DK |
2247 | u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); |
2248 | ||
b475d78f | 2249 | if (IS_MF_SI(bp)) { |
faa6fcbb DK |
2250 | /* maxCfg in percents of linkspeed */ |
2251 | vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; | |
b475d78f | 2252 | } else /* SD modes */ |
faa6fcbb DK |
2253 | /* maxCfg is absolute in 100Mb units */ |
2254 | vn_max_rate = maxCfg * 100; | |
34f80b04 | 2255 | } |
f85582f8 | 2256 | |
b475d78f | 2257 | DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); |
34f80b04 | 2258 | |
b475d78f | 2259 | input->vnic_max_rate[vn] = vn_max_rate; |
34f80b04 | 2260 | } |
f85582f8 | 2261 | |
b475d78f | 2262 | |
523224a3 DK |
2263 | static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) |
2264 | { | |
2265 | if (CHIP_REV_IS_SLOW(bp)) | |
2266 | return CMNG_FNS_NONE; | |
fb3bff17 | 2267 | if (IS_MF(bp)) |
523224a3 DK |
2268 | return CMNG_FNS_MINMAX; |
2269 | ||
2270 | return CMNG_FNS_NONE; | |
2271 | } | |
2272 | ||
2ae17f66 | 2273 | void bnx2x_read_mf_cfg(struct bnx2x *bp) |
523224a3 | 2274 | { |
0793f83f | 2275 | int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); |
523224a3 DK |
2276 | |
2277 | if (BP_NOMCP(bp)) | |
2278 | return; /* what should be the default bvalue in this case */ | |
2279 | ||
0793f83f DK |
2280 | /* For 2 port configuration the absolute function number formula |
2281 | * is: | |
2282 | * abs_func = 2 * vn + BP_PORT + BP_PATH | |
2283 | * | |
2284 | * and there are 4 functions per port | |
2285 | * | |
2286 | * For 4 port configuration it is | |
2287 | * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH | |
2288 | * | |
2289 | * and there are 2 functions per port | |
2290 | */ | |
3395a033 | 2291 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
0793f83f DK |
2292 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
2293 | ||
2294 | if (func >= E1H_FUNC_MAX) | |
2295 | break; | |
2296 | ||
f2e0899f | 2297 | bp->mf_config[vn] = |
523224a3 DK |
2298 | MF_CFG_RD(bp, func_mf_config[func].config); |
2299 | } | |
a3348722 BW |
2300 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
2301 | DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); | |
2302 | bp->flags |= MF_FUNC_DIS; | |
2303 | } else { | |
2304 | DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); | |
2305 | bp->flags &= ~MF_FUNC_DIS; | |
2306 | } | |
523224a3 DK |
2307 | } |
2308 | ||
2309 | static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |
2310 | { | |
b475d78f YM |
2311 | struct cmng_init_input input; |
2312 | memset(&input, 0, sizeof(struct cmng_init_input)); | |
2313 | ||
2314 | input.port_rate = bp->link_vars.line_speed; | |
523224a3 DK |
2315 | |
2316 | if (cmng_type == CMNG_FNS_MINMAX) { | |
2317 | int vn; | |
2318 | ||
523224a3 DK |
2319 | /* read mf conf from shmem */ |
2320 | if (read_cfg) | |
2321 | bnx2x_read_mf_cfg(bp); | |
2322 | ||
523224a3 | 2323 | /* vn_weight_sum and enable fairness if not 0 */ |
b475d78f | 2324 | bnx2x_calc_vn_min(bp, &input); |
523224a3 DK |
2325 | |
2326 | /* calculate and set min-max rate for each vn */ | |
c4154f25 | 2327 | if (bp->port.pmf) |
3395a033 | 2328 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) |
b475d78f | 2329 | bnx2x_calc_vn_max(bp, vn, &input); |
523224a3 DK |
2330 | |
2331 | /* always enable rate shaping and fairness */ | |
b475d78f | 2332 | input.flags.cmng_enables |= |
523224a3 | 2333 | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; |
b475d78f YM |
2334 | |
2335 | bnx2x_init_cmng(&input, &bp->cmng); | |
523224a3 DK |
2336 | return; |
2337 | } | |
2338 | ||
2339 | /* rate shaping and fairness are disabled */ | |
2340 | DP(NETIF_MSG_IFUP, | |
2341 | "rate shaping and fairness are disabled\n"); | |
2342 | } | |
34f80b04 | 2343 | |
1191cb83 ED |
2344 | static void storm_memset_cmng(struct bnx2x *bp, |
2345 | struct cmng_init *cmng, | |
2346 | u8 port) | |
2347 | { | |
2348 | int vn; | |
2349 | size_t size = sizeof(struct cmng_struct_per_port); | |
2350 | ||
2351 | u32 addr = BAR_XSTRORM_INTMEM + | |
2352 | XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); | |
2353 | ||
2354 | __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); | |
2355 | ||
2356 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
2357 | int func = func_by_vn(bp, vn); | |
2358 | ||
2359 | addr = BAR_XSTRORM_INTMEM + | |
2360 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); | |
2361 | size = sizeof(struct rate_shaping_vars_per_vn); | |
2362 | __storm_memset_struct(bp, addr, size, | |
2363 | (u32 *)&cmng->vnic.vnic_max_rate[vn]); | |
2364 | ||
2365 | addr = BAR_XSTRORM_INTMEM + | |
2366 | XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); | |
2367 | size = sizeof(struct fairness_vars_per_vn); | |
2368 | __storm_memset_struct(bp, addr, size, | |
2369 | (u32 *)&cmng->vnic.vnic_min_rate[vn]); | |
2370 | } | |
2371 | } | |
2372 | ||
c18487ee YR |
2373 | /* This function is called upon link interrupt */ |
2374 | static void bnx2x_link_attn(struct bnx2x *bp) | |
2375 | { | |
bb2a0f7a YG |
2376 | /* Make sure that we are synced with the current statistics */ |
2377 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2378 | ||
c18487ee | 2379 | bnx2x_link_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2380 | |
bb2a0f7a YG |
2381 | if (bp->link_vars.link_up) { |
2382 | ||
1c06328c | 2383 | /* dropless flow control */ |
f2e0899f | 2384 | if (!CHIP_IS_E1(bp) && bp->dropless_fc) { |
1c06328c EG |
2385 | int port = BP_PORT(bp); |
2386 | u32 pause_enabled = 0; | |
2387 | ||
2388 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
2389 | pause_enabled = 1; | |
2390 | ||
2391 | REG_WR(bp, BAR_USTRORM_INTMEM + | |
ca00392c | 2392 | USTORM_ETH_PAUSE_ENABLED_OFFSET(port), |
1c06328c EG |
2393 | pause_enabled); |
2394 | } | |
2395 | ||
619c5cb6 | 2396 | if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { |
bb2a0f7a YG |
2397 | struct host_port_stats *pstats; |
2398 | ||
2399 | pstats = bnx2x_sp(bp, port_stats); | |
619c5cb6 | 2400 | /* reset old mac stats */ |
bb2a0f7a YG |
2401 | memset(&(pstats->mac_stx[0]), 0, |
2402 | sizeof(struct mac_stx)); | |
2403 | } | |
f34d28ea | 2404 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a YG |
2405 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
2406 | } | |
2407 | ||
f2e0899f DK |
2408 | if (bp->link_vars.link_up && bp->link_vars.line_speed) { |
2409 | int cmng_fns = bnx2x_get_cmng_fns_mode(bp); | |
8a1c38d1 | 2410 | |
f2e0899f DK |
2411 | if (cmng_fns != CMNG_FNS_NONE) { |
2412 | bnx2x_cmng_fns_init(bp, false, cmng_fns); | |
2413 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2414 | } else | |
2415 | /* rate shaping and fairness are disabled */ | |
2416 | DP(NETIF_MSG_IFUP, | |
2417 | "single function mode without fairness\n"); | |
34f80b04 | 2418 | } |
9fdc3e95 | 2419 | |
2ae17f66 VZ |
2420 | __bnx2x_link_report(bp); |
2421 | ||
9fdc3e95 DK |
2422 | if (IS_MF(bp)) |
2423 | bnx2x_link_sync_notify(bp); | |
c18487ee | 2424 | } |
a2fbb9ea | 2425 | |
9f6c9258 | 2426 | void bnx2x__link_status_update(struct bnx2x *bp) |
c18487ee | 2427 | { |
2ae17f66 | 2428 | if (bp->state != BNX2X_STATE_OPEN) |
c18487ee | 2429 | return; |
a2fbb9ea | 2430 | |
00253a8c DK |
2431 | /* read updated dcb configuration */ |
2432 | bnx2x_dcbx_pmf_update(bp); | |
2433 | ||
c18487ee | 2434 | bnx2x_link_status_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2435 | |
bb2a0f7a YG |
2436 | if (bp->link_vars.link_up) |
2437 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
2438 | else | |
2439 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2440 | ||
c18487ee YR |
2441 | /* indicate link status */ |
2442 | bnx2x_link_report(bp); | |
a2fbb9ea | 2443 | } |
a2fbb9ea | 2444 | |
a3348722 BW |
2445 | static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, |
2446 | u16 vlan_val, u8 allowed_prio) | |
2447 | { | |
2448 | struct bnx2x_func_state_params func_params = {0}; | |
2449 | struct bnx2x_func_afex_update_params *f_update_params = | |
2450 | &func_params.params.afex_update; | |
2451 | ||
2452 | func_params.f_obj = &bp->func_obj; | |
2453 | func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; | |
2454 | ||
2455 | /* no need to wait for RAMROD completion, so don't | |
2456 | * set RAMROD_COMP_WAIT flag | |
2457 | */ | |
2458 | ||
2459 | f_update_params->vif_id = vifid; | |
2460 | f_update_params->afex_default_vlan = vlan_val; | |
2461 | f_update_params->allowed_priorities = allowed_prio; | |
2462 | ||
2463 | /* if ramrod can not be sent, response to MCP immediately */ | |
2464 | if (bnx2x_func_state_change(bp, &func_params) < 0) | |
2465 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
2466 | ||
2467 | return 0; | |
2468 | } | |
2469 | ||
2470 | static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, | |
2471 | u16 vif_index, u8 func_bit_map) | |
2472 | { | |
2473 | struct bnx2x_func_state_params func_params = {0}; | |
2474 | struct bnx2x_func_afex_viflists_params *update_params = | |
2475 | &func_params.params.afex_viflists; | |
2476 | int rc; | |
2477 | u32 drv_msg_code; | |
2478 | ||
2479 | /* validate only LIST_SET and LIST_GET are received from switch */ | |
2480 | if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) | |
2481 | BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", | |
2482 | cmd_type); | |
2483 | ||
2484 | func_params.f_obj = &bp->func_obj; | |
2485 | func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; | |
2486 | ||
2487 | /* set parameters according to cmd_type */ | |
2488 | update_params->afex_vif_list_command = cmd_type; | |
2489 | update_params->vif_list_index = cpu_to_le16(vif_index); | |
2490 | update_params->func_bit_map = | |
2491 | (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; | |
2492 | update_params->func_to_clear = 0; | |
2493 | drv_msg_code = | |
2494 | (cmd_type == VIF_LIST_RULE_GET) ? | |
2495 | DRV_MSG_CODE_AFEX_LISTGET_ACK : | |
2496 | DRV_MSG_CODE_AFEX_LISTSET_ACK; | |
2497 | ||
2498 | /* if ramrod can not be sent, respond to MCP immediately for | |
2499 | * SET and GET requests (other are not triggered from MCP) | |
2500 | */ | |
2501 | rc = bnx2x_func_state_change(bp, &func_params); | |
2502 | if (rc < 0) | |
2503 | bnx2x_fw_command(bp, drv_msg_code, 0); | |
2504 | ||
2505 | return 0; | |
2506 | } | |
2507 | ||
2508 | static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) | |
2509 | { | |
2510 | struct afex_stats afex_stats; | |
2511 | u32 func = BP_ABS_FUNC(bp); | |
2512 | u32 mf_config; | |
2513 | u16 vlan_val; | |
2514 | u32 vlan_prio; | |
2515 | u16 vif_id; | |
2516 | u8 allowed_prio; | |
2517 | u8 vlan_mode; | |
2518 | u32 addr_to_write, vifid, addrs, stats_type, i; | |
2519 | ||
2520 | if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { | |
2521 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2522 | DP(BNX2X_MSG_MCP, | |
2523 | "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); | |
2524 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); | |
2525 | } | |
2526 | ||
2527 | if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { | |
2528 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2529 | addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); | |
2530 | DP(BNX2X_MSG_MCP, | |
2531 | "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", | |
2532 | vifid, addrs); | |
2533 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, | |
2534 | addrs); | |
2535 | } | |
2536 | ||
2537 | if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { | |
2538 | addr_to_write = SHMEM2_RD(bp, | |
2539 | afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); | |
2540 | stats_type = SHMEM2_RD(bp, | |
2541 | afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2542 | ||
2543 | DP(BNX2X_MSG_MCP, | |
2544 | "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", | |
2545 | addr_to_write); | |
2546 | ||
2547 | bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); | |
2548 | ||
2549 | /* write response to scratchpad, for MCP */ | |
2550 | for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) | |
2551 | REG_WR(bp, addr_to_write + i*sizeof(u32), | |
2552 | *(((u32 *)(&afex_stats))+i)); | |
2553 | ||
2554 | /* send ack message to MCP */ | |
2555 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); | |
2556 | } | |
2557 | ||
2558 | if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { | |
2559 | mf_config = MF_CFG_RD(bp, func_mf_config[func].config); | |
2560 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2561 | DP(BNX2X_MSG_MCP, | |
2562 | "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", | |
2563 | mf_config); | |
2564 | ||
2565 | /* if VIF_SET is "enabled" */ | |
2566 | if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { | |
2567 | /* set rate limit directly to internal RAM */ | |
2568 | struct cmng_init_input cmng_input; | |
2569 | struct rate_shaping_vars_per_vn m_rs_vn; | |
2570 | size_t size = sizeof(struct rate_shaping_vars_per_vn); | |
2571 | u32 addr = BAR_XSTRORM_INTMEM + | |
2572 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); | |
2573 | ||
2574 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2575 | ||
2576 | bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); | |
2577 | m_rs_vn.vn_counter.rate = | |
2578 | cmng_input.vnic_max_rate[BP_VN(bp)]; | |
2579 | m_rs_vn.vn_counter.quota = | |
2580 | (m_rs_vn.vn_counter.rate * | |
2581 | RS_PERIODIC_TIMEOUT_USEC) / 8; | |
2582 | ||
2583 | __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); | |
2584 | ||
2585 | /* read relevant values from mf_cfg struct in shmem */ | |
2586 | vif_id = | |
2587 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2588 | FUNC_MF_CFG_E1HOV_TAG_MASK) >> | |
2589 | FUNC_MF_CFG_E1HOV_TAG_SHIFT; | |
2590 | vlan_val = | |
2591 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2592 | FUNC_MF_CFG_AFEX_VLAN_MASK) >> | |
2593 | FUNC_MF_CFG_AFEX_VLAN_SHIFT; | |
2594 | vlan_prio = (mf_config & | |
2595 | FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> | |
2596 | FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; | |
2597 | vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); | |
2598 | vlan_mode = | |
2599 | (MF_CFG_RD(bp, | |
2600 | func_mf_config[func].afex_config) & | |
2601 | FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> | |
2602 | FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; | |
2603 | allowed_prio = | |
2604 | (MF_CFG_RD(bp, | |
2605 | func_mf_config[func].afex_config) & | |
2606 | FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> | |
2607 | FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; | |
2608 | ||
2609 | /* send ramrod to FW, return in case of failure */ | |
2610 | if (bnx2x_afex_func_update(bp, vif_id, vlan_val, | |
2611 | allowed_prio)) | |
2612 | return; | |
2613 | ||
2614 | bp->afex_def_vlan_tag = vlan_val; | |
2615 | bp->afex_vlan_mode = vlan_mode; | |
2616 | } else { | |
2617 | /* notify link down because BP->flags is disabled */ | |
2618 | bnx2x_link_report(bp); | |
2619 | ||
2620 | /* send INVALID VIF ramrod to FW */ | |
2621 | bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); | |
2622 | ||
2623 | /* Reset the default afex VLAN */ | |
2624 | bp->afex_def_vlan_tag = -1; | |
2625 | } | |
2626 | } | |
2627 | } | |
2628 | ||
34f80b04 EG |
2629 | static void bnx2x_pmf_update(struct bnx2x *bp) |
2630 | { | |
2631 | int port = BP_PORT(bp); | |
2632 | u32 val; | |
2633 | ||
2634 | bp->port.pmf = 1; | |
51c1a580 | 2635 | DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); |
34f80b04 | 2636 | |
3deb8167 YR |
2637 | /* |
2638 | * We need the mb() to ensure the ordering between the writing to | |
2639 | * bp->port.pmf here and reading it from the bnx2x_periodic_task(). | |
2640 | */ | |
2641 | smp_mb(); | |
2642 | ||
2643 | /* queue a periodic task */ | |
2644 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
2645 | ||
ef01854e DK |
2646 | bnx2x_dcbx_pmf_update(bp); |
2647 | ||
34f80b04 | 2648 | /* enable nig attention */ |
3395a033 | 2649 | val = (0xff0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
2650 | if (bp->common.int_block == INT_BLOCK_HC) { |
2651 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
2652 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
619c5cb6 | 2653 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2654 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
2655 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
2656 | } | |
bb2a0f7a YG |
2657 | |
2658 | bnx2x_stats_handle(bp, STATS_EVENT_PMF); | |
34f80b04 EG |
2659 | } |
2660 | ||
c18487ee | 2661 | /* end of Link */ |
a2fbb9ea ET |
2662 | |
2663 | /* slow path */ | |
2664 | ||
2665 | /* | |
2666 | * General service functions | |
2667 | */ | |
2668 | ||
2691d51d | 2669 | /* send the MCP a request, block until there is a reply */ |
a22f0788 | 2670 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) |
2691d51d | 2671 | { |
f2e0899f | 2672 | int mb_idx = BP_FW_MB_IDX(bp); |
a5971d43 | 2673 | u32 seq; |
2691d51d EG |
2674 | u32 rc = 0; |
2675 | u32 cnt = 1; | |
2676 | u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; | |
2677 | ||
c4ff7cbf | 2678 | mutex_lock(&bp->fw_mb_mutex); |
a5971d43 | 2679 | seq = ++bp->fw_seq; |
f2e0899f DK |
2680 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); |
2681 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); | |
2682 | ||
754a2f52 DK |
2683 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", |
2684 | (command | seq), param); | |
2691d51d EG |
2685 | |
2686 | do { | |
2687 | /* let the FW do it's magic ... */ | |
2688 | msleep(delay); | |
2689 | ||
f2e0899f | 2690 | rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); |
2691d51d | 2691 | |
c4ff7cbf EG |
2692 | /* Give the FW up to 5 second (500*10ms) */ |
2693 | } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); | |
2691d51d EG |
2694 | |
2695 | DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", | |
2696 | cnt*delay, rc, seq); | |
2697 | ||
2698 | /* is this a reply to our command? */ | |
2699 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) | |
2700 | rc &= FW_MSG_CODE_MASK; | |
2701 | else { | |
2702 | /* FW BUG! */ | |
2703 | BNX2X_ERR("FW failed to respond!\n"); | |
2704 | bnx2x_fw_dump(bp); | |
2705 | rc = 0; | |
2706 | } | |
c4ff7cbf | 2707 | mutex_unlock(&bp->fw_mb_mutex); |
2691d51d EG |
2708 | |
2709 | return rc; | |
2710 | } | |
2711 | ||
ec6ba945 | 2712 | |
1191cb83 ED |
2713 | static void storm_memset_func_cfg(struct bnx2x *bp, |
2714 | struct tstorm_eth_function_common_config *tcfg, | |
2715 | u16 abs_fid) | |
2716 | { | |
2717 | size_t size = sizeof(struct tstorm_eth_function_common_config); | |
2718 | ||
2719 | u32 addr = BAR_TSTRORM_INTMEM + | |
2720 | TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); | |
2721 | ||
2722 | __storm_memset_struct(bp, addr, size, (u32 *)tcfg); | |
2723 | } | |
2724 | ||
619c5cb6 VZ |
2725 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) |
2726 | { | |
2727 | if (CHIP_IS_E1x(bp)) { | |
2728 | struct tstorm_eth_function_common_config tcfg = {0}; | |
2729 | ||
2730 | storm_memset_func_cfg(bp, &tcfg, p->func_id); | |
2731 | } | |
2732 | ||
2733 | /* Enable the function in the FW */ | |
2734 | storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); | |
2735 | storm_memset_func_en(bp, p->func_id, 1); | |
2736 | ||
2737 | /* spq */ | |
2738 | if (p->func_flgs & FUNC_FLG_SPQ) { | |
2739 | storm_memset_spq_addr(bp, p->spq_map, p->func_id); | |
2740 | REG_WR(bp, XSEM_REG_FAST_MEMORY + | |
2741 | XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); | |
2742 | } | |
2743 | } | |
2744 | ||
6383c0b3 AE |
2745 | /** |
2746 | * bnx2x_get_tx_only_flags - Return common flags | |
2747 | * | |
2748 | * @bp device handle | |
2749 | * @fp queue handle | |
2750 | * @zero_stats TRUE if statistics zeroing is needed | |
2751 | * | |
2752 | * Return the flags that are common for the Tx-only and not normal connections. | |
2753 | */ | |
1191cb83 ED |
2754 | static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, |
2755 | struct bnx2x_fastpath *fp, | |
2756 | bool zero_stats) | |
28912902 | 2757 | { |
619c5cb6 VZ |
2758 | unsigned long flags = 0; |
2759 | ||
2760 | /* PF driver will always initialize the Queue to an ACTIVE state */ | |
2761 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); | |
28912902 | 2762 | |
6383c0b3 AE |
2763 | /* tx only connections collect statistics (on the same index as the |
2764 | * parent connection). The statistics are zeroed when the parent | |
2765 | * connection is initialized. | |
2766 | */ | |
50f0a562 BW |
2767 | |
2768 | __set_bit(BNX2X_Q_FLG_STATS, &flags); | |
2769 | if (zero_stats) | |
2770 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); | |
2771 | ||
6383c0b3 AE |
2772 | |
2773 | return flags; | |
2774 | } | |
2775 | ||
1191cb83 ED |
2776 | static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, |
2777 | struct bnx2x_fastpath *fp, | |
2778 | bool leading) | |
6383c0b3 AE |
2779 | { |
2780 | unsigned long flags = 0; | |
2781 | ||
619c5cb6 VZ |
2782 | /* calculate other queue flags */ |
2783 | if (IS_MF_SD(bp)) | |
2784 | __set_bit(BNX2X_Q_FLG_OV, &flags); | |
28912902 | 2785 | |
a3348722 | 2786 | if (IS_FCOE_FP(fp)) { |
619c5cb6 | 2787 | __set_bit(BNX2X_Q_FLG_FCOE, &flags); |
a3348722 BW |
2788 | /* For FCoE - force usage of default priority (for afex) */ |
2789 | __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); | |
2790 | } | |
523224a3 | 2791 | |
f5219d8e | 2792 | if (!fp->disable_tpa) { |
619c5cb6 | 2793 | __set_bit(BNX2X_Q_FLG_TPA, &flags); |
f5219d8e | 2794 | __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); |
621b4d66 DK |
2795 | if (fp->mode == TPA_MODE_GRO) |
2796 | __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); | |
f5219d8e | 2797 | } |
619c5cb6 | 2798 | |
619c5cb6 VZ |
2799 | if (leading) { |
2800 | __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); | |
2801 | __set_bit(BNX2X_Q_FLG_MCAST, &flags); | |
2802 | } | |
523224a3 | 2803 | |
619c5cb6 VZ |
2804 | /* Always set HW VLAN stripping */ |
2805 | __set_bit(BNX2X_Q_FLG_VLAN, &flags); | |
523224a3 | 2806 | |
a3348722 BW |
2807 | /* configure silent vlan removal */ |
2808 | if (IS_MF_AFEX(bp)) | |
2809 | __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); | |
2810 | ||
6383c0b3 AE |
2811 | |
2812 | return flags | bnx2x_get_common_flags(bp, fp, true); | |
523224a3 DK |
2813 | } |
2814 | ||
619c5cb6 | 2815 | static void bnx2x_pf_q_prep_general(struct bnx2x *bp, |
6383c0b3 AE |
2816 | struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, |
2817 | u8 cos) | |
619c5cb6 VZ |
2818 | { |
2819 | gen_init->stat_id = bnx2x_stats_id(fp); | |
2820 | gen_init->spcl_id = fp->cl_id; | |
2821 | ||
2822 | /* Always use mini-jumbo MTU for FCoE L2 ring */ | |
2823 | if (IS_FCOE_FP(fp)) | |
2824 | gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; | |
2825 | else | |
2826 | gen_init->mtu = bp->dev->mtu; | |
6383c0b3 AE |
2827 | |
2828 | gen_init->cos = cos; | |
619c5cb6 VZ |
2829 | } |
2830 | ||
2831 | static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |
523224a3 | 2832 | struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, |
619c5cb6 | 2833 | struct bnx2x_rxq_setup_params *rxq_init) |
523224a3 | 2834 | { |
619c5cb6 | 2835 | u8 max_sge = 0; |
523224a3 DK |
2836 | u16 sge_sz = 0; |
2837 | u16 tpa_agg_size = 0; | |
2838 | ||
523224a3 | 2839 | if (!fp->disable_tpa) { |
dfacf138 DK |
2840 | pause->sge_th_lo = SGE_TH_LO(bp); |
2841 | pause->sge_th_hi = SGE_TH_HI(bp); | |
2842 | ||
2843 | /* validate SGE ring has enough to cross high threshold */ | |
2844 | WARN_ON(bp->dropless_fc && | |
2845 | pause->sge_th_hi + FW_PREFETCH_CNT > | |
2846 | MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); | |
2847 | ||
523224a3 DK |
2848 | tpa_agg_size = min_t(u32, |
2849 | (min_t(u32, 8, MAX_SKB_FRAGS) * | |
2850 | SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); | |
2851 | max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> | |
2852 | SGE_PAGE_SHIFT; | |
2853 | max_sge = ((max_sge + PAGES_PER_SGE - 1) & | |
2854 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; | |
2855 | sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, | |
2856 | 0xffff); | |
2857 | } | |
2858 | ||
2859 | /* pause - not for e1 */ | |
2860 | if (!CHIP_IS_E1(bp)) { | |
dfacf138 DK |
2861 | pause->bd_th_lo = BD_TH_LO(bp); |
2862 | pause->bd_th_hi = BD_TH_HI(bp); | |
2863 | ||
2864 | pause->rcq_th_lo = RCQ_TH_LO(bp); | |
2865 | pause->rcq_th_hi = RCQ_TH_HI(bp); | |
2866 | /* | |
2867 | * validate that rings have enough entries to cross | |
2868 | * high thresholds | |
2869 | */ | |
2870 | WARN_ON(bp->dropless_fc && | |
2871 | pause->bd_th_hi + FW_PREFETCH_CNT > | |
2872 | bp->rx_ring_size); | |
2873 | WARN_ON(bp->dropless_fc && | |
2874 | pause->rcq_th_hi + FW_PREFETCH_CNT > | |
2875 | NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); | |
619c5cb6 | 2876 | |
523224a3 DK |
2877 | pause->pri_map = 1; |
2878 | } | |
2879 | ||
2880 | /* rxq setup */ | |
523224a3 DK |
2881 | rxq_init->dscr_map = fp->rx_desc_mapping; |
2882 | rxq_init->sge_map = fp->rx_sge_mapping; | |
2883 | rxq_init->rcq_map = fp->rx_comp_mapping; | |
2884 | rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; | |
a8c94b91 | 2885 | |
619c5cb6 VZ |
2886 | /* This should be a maximum number of data bytes that may be |
2887 | * placed on the BD (not including paddings). | |
2888 | */ | |
e52fcb24 ED |
2889 | rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - |
2890 | BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; | |
a8c94b91 | 2891 | |
523224a3 | 2892 | rxq_init->cl_qzone_id = fp->cl_qzone_id; |
523224a3 DK |
2893 | rxq_init->tpa_agg_sz = tpa_agg_size; |
2894 | rxq_init->sge_buf_sz = sge_sz; | |
2895 | rxq_init->max_sges_pkt = max_sge; | |
619c5cb6 | 2896 | rxq_init->rss_engine_id = BP_FUNC(bp); |
259afa1f | 2897 | rxq_init->mcast_engine_id = BP_FUNC(bp); |
619c5cb6 VZ |
2898 | |
2899 | /* Maximum number or simultaneous TPA aggregation for this Queue. | |
2900 | * | |
2901 | * For PF Clients it should be the maximum avaliable number. | |
2902 | * VF driver(s) may want to define it to a smaller value. | |
2903 | */ | |
dfacf138 | 2904 | rxq_init->max_tpa_queues = MAX_AGG_QS(bp); |
619c5cb6 | 2905 | |
523224a3 DK |
2906 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
2907 | rxq_init->fw_sb_id = fp->fw_sb_id; | |
2908 | ||
ec6ba945 VZ |
2909 | if (IS_FCOE_FP(fp)) |
2910 | rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; | |
2911 | else | |
6383c0b3 | 2912 | rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
a3348722 BW |
2913 | /* configure silent vlan removal |
2914 | * if multi function mode is afex, then mask default vlan | |
2915 | */ | |
2916 | if (IS_MF_AFEX(bp)) { | |
2917 | rxq_init->silent_removal_value = bp->afex_def_vlan_tag; | |
2918 | rxq_init->silent_removal_mask = VLAN_VID_MASK; | |
2919 | } | |
523224a3 DK |
2920 | } |
2921 | ||
619c5cb6 | 2922 | static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, |
6383c0b3 AE |
2923 | struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, |
2924 | u8 cos) | |
523224a3 | 2925 | { |
65565884 | 2926 | txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; |
6383c0b3 | 2927 | txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; |
523224a3 DK |
2928 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; |
2929 | txq_init->fw_sb_id = fp->fw_sb_id; | |
ec6ba945 | 2930 | |
619c5cb6 VZ |
2931 | /* |
2932 | * set the tss leading client id for TX classfication == | |
2933 | * leading RSS client id | |
2934 | */ | |
2935 | txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); | |
2936 | ||
ec6ba945 VZ |
2937 | if (IS_FCOE_FP(fp)) { |
2938 | txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; | |
2939 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; | |
2940 | } | |
523224a3 DK |
2941 | } |
2942 | ||
8d96286a | 2943 | static void bnx2x_pf_init(struct bnx2x *bp) |
523224a3 DK |
2944 | { |
2945 | struct bnx2x_func_init_params func_init = {0}; | |
523224a3 DK |
2946 | struct event_ring_data eq_data = { {0} }; |
2947 | u16 flags; | |
2948 | ||
619c5cb6 | 2949 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2950 | /* reset IGU PF statistics: MSIX + ATTN */ |
2951 | /* PF */ | |
2952 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
2953 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
2954 | (CHIP_MODE_IS_4_PORT(bp) ? | |
2955 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
2956 | /* ATTN */ | |
2957 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
2958 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
2959 | BNX2X_IGU_STAS_MSG_PF_CNT*4 + | |
2960 | (CHIP_MODE_IS_4_PORT(bp) ? | |
2961 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
2962 | } | |
2963 | ||
523224a3 DK |
2964 | /* function setup flags */ |
2965 | flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); | |
2966 | ||
619c5cb6 VZ |
2967 | /* This flag is relevant for E1x only. |
2968 | * E2 doesn't have a TPA configuration in a function level. | |
523224a3 | 2969 | */ |
619c5cb6 | 2970 | flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; |
523224a3 DK |
2971 | |
2972 | func_init.func_flgs = flags; | |
2973 | func_init.pf_id = BP_FUNC(bp); | |
2974 | func_init.func_id = BP_FUNC(bp); | |
523224a3 DK |
2975 | func_init.spq_map = bp->spq_mapping; |
2976 | func_init.spq_prod = bp->spq_prod_idx; | |
2977 | ||
2978 | bnx2x_func_init(bp, &func_init); | |
2979 | ||
2980 | memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); | |
2981 | ||
2982 | /* | |
619c5cb6 VZ |
2983 | * Congestion management values depend on the link rate |
2984 | * There is no active link so initial link rate is set to 10 Gbps. | |
2985 | * When the link comes up The congestion management values are | |
2986 | * re-calculated according to the actual link rate. | |
2987 | */ | |
523224a3 DK |
2988 | bp->link_vars.line_speed = SPEED_10000; |
2989 | bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); | |
2990 | ||
2991 | /* Only the PMF sets the HW */ | |
2992 | if (bp->port.pmf) | |
2993 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2994 | ||
523224a3 DK |
2995 | /* init Event Queue */ |
2996 | eq_data.base_addr.hi = U64_HI(bp->eq_mapping); | |
2997 | eq_data.base_addr.lo = U64_LO(bp->eq_mapping); | |
2998 | eq_data.producer = bp->eq_prod; | |
2999 | eq_data.index_id = HC_SP_INDEX_EQ_CONS; | |
3000 | eq_data.sb_id = DEF_SB_ID; | |
3001 | storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); | |
3002 | } | |
3003 | ||
3004 | ||
3005 | static void bnx2x_e1h_disable(struct bnx2x *bp) | |
3006 | { | |
3007 | int port = BP_PORT(bp); | |
3008 | ||
619c5cb6 | 3009 | bnx2x_tx_disable(bp); |
523224a3 DK |
3010 | |
3011 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
523224a3 DK |
3012 | } |
3013 | ||
3014 | static void bnx2x_e1h_enable(struct bnx2x *bp) | |
3015 | { | |
3016 | int port = BP_PORT(bp); | |
3017 | ||
3018 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); | |
3019 | ||
3020 | /* Tx queue should be only reenabled */ | |
3021 | netif_tx_wake_all_queues(bp->dev); | |
3022 | ||
3023 | /* | |
3024 | * Should not call netif_carrier_on since it will be called if the link | |
3025 | * is up when checking for link state | |
3026 | */ | |
3027 | } | |
3028 | ||
1d187b34 BW |
3029 | #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 |
3030 | ||
3031 | static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) | |
3032 | { | |
3033 | struct eth_stats_info *ether_stat = | |
3034 | &bp->slowpath->drv_info_to_mcp.ether_stat; | |
3035 | ||
3036 | /* leave last char as NULL */ | |
3037 | memcpy(ether_stat->version, DRV_MODULE_VERSION, | |
3038 | ETH_STAT_INFO_VERSION_LEN - 1); | |
3039 | ||
15192a8c BW |
3040 | bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj, |
3041 | DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, | |
3042 | ether_stat->mac_local); | |
1d187b34 BW |
3043 | |
3044 | ether_stat->mtu_size = bp->dev->mtu; | |
3045 | ||
3046 | if (bp->dev->features & NETIF_F_RXCSUM) | |
3047 | ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; | |
3048 | if (bp->dev->features & NETIF_F_TSO) | |
3049 | ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; | |
3050 | ether_stat->feature_flags |= bp->common.boot_mode; | |
3051 | ||
3052 | ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; | |
3053 | ||
3054 | ether_stat->txq_size = bp->tx_ring_size; | |
3055 | ether_stat->rxq_size = bp->rx_ring_size; | |
3056 | } | |
3057 | ||
3058 | static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) | |
3059 | { | |
f2fd5c34 | 3060 | #ifdef BCM_CNIC |
1d187b34 BW |
3061 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; |
3062 | struct fcoe_stats_info *fcoe_stat = | |
3063 | &bp->slowpath->drv_info_to_mcp.fcoe_stat; | |
3064 | ||
2e499d3c BW |
3065 | memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT, |
3066 | bp->fip_mac, ETH_ALEN); | |
1d187b34 BW |
3067 | |
3068 | fcoe_stat->qos_priority = | |
3069 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; | |
3070 | ||
3071 | /* insert FCoE stats from ramrod response */ | |
3072 | if (!NO_FCOE(bp)) { | |
3073 | struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = | |
65565884 | 3074 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3075 | tstorm_queue_statistics; |
3076 | ||
3077 | struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = | |
65565884 | 3078 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3079 | xstorm_queue_statistics; |
3080 | ||
3081 | struct fcoe_statistics_params *fw_fcoe_stat = | |
3082 | &bp->fw_stats_data->fcoe; | |
3083 | ||
3084 | ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo, | |
3085 | fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); | |
3086 | ||
3087 | ADD_64(fcoe_stat->rx_bytes_hi, | |
3088 | fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, | |
3089 | fcoe_stat->rx_bytes_lo, | |
3090 | fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); | |
3091 | ||
3092 | ADD_64(fcoe_stat->rx_bytes_hi, | |
3093 | fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, | |
3094 | fcoe_stat->rx_bytes_lo, | |
3095 | fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); | |
3096 | ||
3097 | ADD_64(fcoe_stat->rx_bytes_hi, | |
3098 | fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, | |
3099 | fcoe_stat->rx_bytes_lo, | |
3100 | fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); | |
3101 | ||
3102 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
3103 | fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); | |
3104 | ||
3105 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
3106 | fcoe_q_tstorm_stats->rcv_ucast_pkts); | |
3107 | ||
3108 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
3109 | fcoe_q_tstorm_stats->rcv_bcast_pkts); | |
3110 | ||
3111 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
f33f1fcc | 3112 | fcoe_q_tstorm_stats->rcv_mcast_pkts); |
1d187b34 BW |
3113 | |
3114 | ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo, | |
3115 | fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); | |
3116 | ||
3117 | ADD_64(fcoe_stat->tx_bytes_hi, | |
3118 | fcoe_q_xstorm_stats->ucast_bytes_sent.hi, | |
3119 | fcoe_stat->tx_bytes_lo, | |
3120 | fcoe_q_xstorm_stats->ucast_bytes_sent.lo); | |
3121 | ||
3122 | ADD_64(fcoe_stat->tx_bytes_hi, | |
3123 | fcoe_q_xstorm_stats->bcast_bytes_sent.hi, | |
3124 | fcoe_stat->tx_bytes_lo, | |
3125 | fcoe_q_xstorm_stats->bcast_bytes_sent.lo); | |
3126 | ||
3127 | ADD_64(fcoe_stat->tx_bytes_hi, | |
3128 | fcoe_q_xstorm_stats->mcast_bytes_sent.hi, | |
3129 | fcoe_stat->tx_bytes_lo, | |
3130 | fcoe_q_xstorm_stats->mcast_bytes_sent.lo); | |
3131 | ||
3132 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3133 | fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); | |
3134 | ||
3135 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3136 | fcoe_q_xstorm_stats->ucast_pkts_sent); | |
3137 | ||
3138 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3139 | fcoe_q_xstorm_stats->bcast_pkts_sent); | |
3140 | ||
3141 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3142 | fcoe_q_xstorm_stats->mcast_pkts_sent); | |
3143 | } | |
3144 | ||
1d187b34 BW |
3145 | /* ask L5 driver to add data to the struct */ |
3146 | bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); | |
3147 | #endif | |
3148 | } | |
3149 | ||
3150 | static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) | |
3151 | { | |
f2fd5c34 | 3152 | #ifdef BCM_CNIC |
1d187b34 BW |
3153 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; |
3154 | struct iscsi_stats_info *iscsi_stat = | |
3155 | &bp->slowpath->drv_info_to_mcp.iscsi_stat; | |
3156 | ||
2e499d3c BW |
3157 | memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT, |
3158 | bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); | |
1d187b34 BW |
3159 | |
3160 | iscsi_stat->qos_priority = | |
3161 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; | |
3162 | ||
1d187b34 BW |
3163 | /* ask L5 driver to add data to the struct */ |
3164 | bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); | |
3165 | #endif | |
3166 | } | |
3167 | ||
0793f83f DK |
3168 | /* called due to MCP event (on pmf): |
3169 | * reread new bandwidth configuration | |
3170 | * configure FW | |
3171 | * notify others function about the change | |
3172 | */ | |
1191cb83 | 3173 | static void bnx2x_config_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3174 | { |
3175 | if (bp->link_vars.link_up) { | |
3176 | bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); | |
3177 | bnx2x_link_sync_notify(bp); | |
3178 | } | |
3179 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3180 | } | |
3181 | ||
1191cb83 | 3182 | static void bnx2x_set_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3183 | { |
3184 | bnx2x_config_mf_bw(bp); | |
3185 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); | |
3186 | } | |
3187 | ||
c8c60d88 YM |
3188 | static void bnx2x_handle_eee_event(struct bnx2x *bp) |
3189 | { | |
3190 | DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); | |
3191 | bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); | |
3192 | } | |
3193 | ||
1d187b34 BW |
3194 | static void bnx2x_handle_drv_info_req(struct bnx2x *bp) |
3195 | { | |
3196 | enum drv_info_opcode op_code; | |
3197 | u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); | |
3198 | ||
3199 | /* if drv_info version supported by MFW doesn't match - send NACK */ | |
3200 | if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { | |
3201 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3202 | return; | |
3203 | } | |
3204 | ||
3205 | op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> | |
3206 | DRV_INFO_CONTROL_OP_CODE_SHIFT; | |
3207 | ||
3208 | memset(&bp->slowpath->drv_info_to_mcp, 0, | |
3209 | sizeof(union drv_info_to_mcp)); | |
3210 | ||
3211 | switch (op_code) { | |
3212 | case ETH_STATS_OPCODE: | |
3213 | bnx2x_drv_info_ether_stat(bp); | |
3214 | break; | |
3215 | case FCOE_STATS_OPCODE: | |
3216 | bnx2x_drv_info_fcoe_stat(bp); | |
3217 | break; | |
3218 | case ISCSI_STATS_OPCODE: | |
3219 | bnx2x_drv_info_iscsi_stat(bp); | |
3220 | break; | |
3221 | default: | |
3222 | /* if op code isn't supported - send NACK */ | |
3223 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3224 | return; | |
3225 | } | |
3226 | ||
3227 | /* if we got drv_info attn from MFW then these fields are defined in | |
3228 | * shmem2 for sure | |
3229 | */ | |
3230 | SHMEM2_WR(bp, drv_info_host_addr_lo, | |
3231 | U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3232 | SHMEM2_WR(bp, drv_info_host_addr_hi, | |
3233 | U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3234 | ||
3235 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); | |
3236 | } | |
3237 | ||
523224a3 DK |
3238 | static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) |
3239 | { | |
3240 | DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); | |
3241 | ||
3242 | if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { | |
3243 | ||
3244 | /* | |
3245 | * This is the only place besides the function initialization | |
3246 | * where the bp->flags can change so it is done without any | |
3247 | * locks | |
3248 | */ | |
f2e0899f | 3249 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
51c1a580 | 3250 | DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); |
523224a3 DK |
3251 | bp->flags |= MF_FUNC_DIS; |
3252 | ||
3253 | bnx2x_e1h_disable(bp); | |
3254 | } else { | |
51c1a580 | 3255 | DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); |
523224a3 DK |
3256 | bp->flags &= ~MF_FUNC_DIS; |
3257 | ||
3258 | bnx2x_e1h_enable(bp); | |
3259 | } | |
3260 | dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; | |
3261 | } | |
3262 | if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { | |
0793f83f | 3263 | bnx2x_config_mf_bw(bp); |
523224a3 DK |
3264 | dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; |
3265 | } | |
3266 | ||
3267 | /* Report results to MCP */ | |
3268 | if (dcc_event) | |
3269 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); | |
3270 | else | |
3271 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); | |
3272 | } | |
3273 | ||
3274 | /* must be called under the spq lock */ | |
1191cb83 | 3275 | static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) |
523224a3 DK |
3276 | { |
3277 | struct eth_spe *next_spe = bp->spq_prod_bd; | |
3278 | ||
3279 | if (bp->spq_prod_bd == bp->spq_last_bd) { | |
3280 | bp->spq_prod_bd = bp->spq; | |
3281 | bp->spq_prod_idx = 0; | |
51c1a580 | 3282 | DP(BNX2X_MSG_SP, "end of spq\n"); |
523224a3 DK |
3283 | } else { |
3284 | bp->spq_prod_bd++; | |
3285 | bp->spq_prod_idx++; | |
3286 | } | |
3287 | return next_spe; | |
3288 | } | |
3289 | ||
3290 | /* must be called under the spq lock */ | |
1191cb83 | 3291 | static void bnx2x_sp_prod_update(struct bnx2x *bp) |
28912902 MC |
3292 | { |
3293 | int func = BP_FUNC(bp); | |
3294 | ||
53e51e2f VZ |
3295 | /* |
3296 | * Make sure that BD data is updated before writing the producer: | |
3297 | * BD data is written to the memory, the producer is read from the | |
3298 | * memory, thus we need a full memory barrier to ensure the ordering. | |
3299 | */ | |
3300 | mb(); | |
28912902 | 3301 | |
523224a3 | 3302 | REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), |
f85582f8 | 3303 | bp->spq_prod_idx); |
28912902 MC |
3304 | mmiowb(); |
3305 | } | |
3306 | ||
619c5cb6 VZ |
3307 | /** |
3308 | * bnx2x_is_contextless_ramrod - check if the current command ends on EQ | |
3309 | * | |
3310 | * @cmd: command to check | |
3311 | * @cmd_type: command type | |
3312 | */ | |
1191cb83 | 3313 | static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) |
619c5cb6 VZ |
3314 | { |
3315 | if ((cmd_type == NONE_CONNECTION_TYPE) || | |
6383c0b3 | 3316 | (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || |
619c5cb6 VZ |
3317 | (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || |
3318 | (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || | |
3319 | (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || | |
3320 | (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || | |
3321 | (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) | |
3322 | return true; | |
3323 | else | |
3324 | return false; | |
3325 | ||
3326 | } | |
3327 | ||
3328 | ||
3329 | /** | |
3330 | * bnx2x_sp_post - place a single command on an SP ring | |
3331 | * | |
3332 | * @bp: driver handle | |
3333 | * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) | |
3334 | * @cid: SW CID the command is related to | |
3335 | * @data_hi: command private data address (high 32 bits) | |
3336 | * @data_lo: command private data address (low 32 bits) | |
3337 | * @cmd_type: command type (e.g. NONE, ETH) | |
3338 | * | |
3339 | * SP data is handled as if it's always an address pair, thus data fields are | |
3340 | * not swapped to little endian in upper functions. Instead this function swaps | |
3341 | * data as if it's two u32 fields. | |
3342 | */ | |
9f6c9258 | 3343 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
619c5cb6 | 3344 | u32 data_hi, u32 data_lo, int cmd_type) |
a2fbb9ea | 3345 | { |
28912902 | 3346 | struct eth_spe *spe; |
523224a3 | 3347 | u16 type; |
619c5cb6 | 3348 | bool common = bnx2x_is_contextless_ramrod(command, cmd_type); |
a2fbb9ea | 3349 | |
a2fbb9ea | 3350 | #ifdef BNX2X_STOP_ON_ERROR |
51c1a580 MS |
3351 | if (unlikely(bp->panic)) { |
3352 | BNX2X_ERR("Can't post SP when there is panic\n"); | |
a2fbb9ea | 3353 | return -EIO; |
51c1a580 | 3354 | } |
a2fbb9ea ET |
3355 | #endif |
3356 | ||
34f80b04 | 3357 | spin_lock_bh(&bp->spq_lock); |
a2fbb9ea | 3358 | |
6e30dd4e VZ |
3359 | if (common) { |
3360 | if (!atomic_read(&bp->eq_spq_left)) { | |
3361 | BNX2X_ERR("BUG! EQ ring full!\n"); | |
3362 | spin_unlock_bh(&bp->spq_lock); | |
3363 | bnx2x_panic(); | |
3364 | return -EBUSY; | |
3365 | } | |
3366 | } else if (!atomic_read(&bp->cq_spq_left)) { | |
3367 | BNX2X_ERR("BUG! SPQ ring full!\n"); | |
3368 | spin_unlock_bh(&bp->spq_lock); | |
3369 | bnx2x_panic(); | |
3370 | return -EBUSY; | |
a2fbb9ea | 3371 | } |
f1410647 | 3372 | |
28912902 MC |
3373 | spe = bnx2x_sp_get_next(bp); |
3374 | ||
a2fbb9ea | 3375 | /* CID needs port number to be encoded int it */ |
28912902 | 3376 | spe->hdr.conn_and_cmd_data = |
cdaa7cb8 VZ |
3377 | cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | |
3378 | HW_CID(bp, cid)); | |
523224a3 | 3379 | |
619c5cb6 | 3380 | type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; |
a2fbb9ea | 3381 | |
523224a3 DK |
3382 | type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & |
3383 | SPE_HDR_FUNCTION_ID); | |
a2fbb9ea | 3384 | |
523224a3 DK |
3385 | spe->hdr.type = cpu_to_le16(type); |
3386 | ||
3387 | spe->data.update_data_addr.hi = cpu_to_le32(data_hi); | |
3388 | spe->data.update_data_addr.lo = cpu_to_le32(data_lo); | |
3389 | ||
d6cae238 VZ |
3390 | /* |
3391 | * It's ok if the actual decrement is issued towards the memory | |
3392 | * somewhere between the spin_lock and spin_unlock. Thus no | |
3393 | * more explict memory barrier is needed. | |
3394 | */ | |
3395 | if (common) | |
3396 | atomic_dec(&bp->eq_spq_left); | |
3397 | else | |
3398 | atomic_dec(&bp->cq_spq_left); | |
6e30dd4e | 3399 | |
a2fbb9ea | 3400 | |
51c1a580 MS |
3401 | DP(BNX2X_MSG_SP, |
3402 | "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", | |
cdaa7cb8 VZ |
3403 | bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), |
3404 | (u32)(U64_LO(bp->spq_mapping) + | |
d6cae238 | 3405 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, |
6e30dd4e VZ |
3406 | HW_CID(bp, cid), data_hi, data_lo, type, |
3407 | atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); | |
cdaa7cb8 | 3408 | |
28912902 | 3409 | bnx2x_sp_prod_update(bp); |
34f80b04 | 3410 | spin_unlock_bh(&bp->spq_lock); |
a2fbb9ea ET |
3411 | return 0; |
3412 | } | |
3413 | ||
3414 | /* acquire split MCP access lock register */ | |
4a37fb66 | 3415 | static int bnx2x_acquire_alr(struct bnx2x *bp) |
a2fbb9ea | 3416 | { |
72fd0718 | 3417 | u32 j, val; |
34f80b04 | 3418 | int rc = 0; |
a2fbb9ea ET |
3419 | |
3420 | might_sleep(); | |
72fd0718 | 3421 | for (j = 0; j < 1000; j++) { |
a2fbb9ea ET |
3422 | val = (1UL << 31); |
3423 | REG_WR(bp, GRCBASE_MCP + 0x9c, val); | |
3424 | val = REG_RD(bp, GRCBASE_MCP + 0x9c); | |
3425 | if (val & (1L << 31)) | |
3426 | break; | |
3427 | ||
3428 | msleep(5); | |
3429 | } | |
a2fbb9ea | 3430 | if (!(val & (1L << 31))) { |
19680c48 | 3431 | BNX2X_ERR("Cannot acquire MCP access lock register\n"); |
a2fbb9ea ET |
3432 | rc = -EBUSY; |
3433 | } | |
3434 | ||
3435 | return rc; | |
3436 | } | |
3437 | ||
4a37fb66 YG |
3438 | /* release split MCP access lock register */ |
3439 | static void bnx2x_release_alr(struct bnx2x *bp) | |
a2fbb9ea | 3440 | { |
72fd0718 | 3441 | REG_WR(bp, GRCBASE_MCP + 0x9c, 0); |
a2fbb9ea ET |
3442 | } |
3443 | ||
523224a3 DK |
3444 | #define BNX2X_DEF_SB_ATT_IDX 0x0001 |
3445 | #define BNX2X_DEF_SB_IDX 0x0002 | |
3446 | ||
1191cb83 | 3447 | static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) |
a2fbb9ea | 3448 | { |
523224a3 | 3449 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
a2fbb9ea ET |
3450 | u16 rc = 0; |
3451 | ||
3452 | barrier(); /* status block is written to by the chip */ | |
a2fbb9ea ET |
3453 | if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { |
3454 | bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; | |
523224a3 | 3455 | rc |= BNX2X_DEF_SB_ATT_IDX; |
a2fbb9ea | 3456 | } |
523224a3 DK |
3457 | |
3458 | if (bp->def_idx != def_sb->sp_sb.running_index) { | |
3459 | bp->def_idx = def_sb->sp_sb.running_index; | |
3460 | rc |= BNX2X_DEF_SB_IDX; | |
a2fbb9ea | 3461 | } |
523224a3 DK |
3462 | |
3463 | /* Do not reorder: indecies reading should complete before handling */ | |
3464 | barrier(); | |
a2fbb9ea ET |
3465 | return rc; |
3466 | } | |
3467 | ||
3468 | /* | |
3469 | * slow path service functions | |
3470 | */ | |
3471 | ||
3472 | static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |
3473 | { | |
34f80b04 | 3474 | int port = BP_PORT(bp); |
a2fbb9ea ET |
3475 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
3476 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
877e9aa4 ET |
3477 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
3478 | NIG_REG_MASK_INTERRUPT_PORT0; | |
3fcaf2e5 | 3479 | u32 aeu_mask; |
87942b46 | 3480 | u32 nig_mask = 0; |
f2e0899f | 3481 | u32 reg_addr; |
a2fbb9ea | 3482 | |
a2fbb9ea ET |
3483 | if (bp->attn_state & asserted) |
3484 | BNX2X_ERR("IGU ERROR\n"); | |
3485 | ||
3fcaf2e5 EG |
3486 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
3487 | aeu_mask = REG_RD(bp, aeu_addr); | |
3488 | ||
a2fbb9ea | 3489 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
3fcaf2e5 | 3490 | aeu_mask, asserted); |
72fd0718 | 3491 | aeu_mask &= ~(asserted & 0x3ff); |
3fcaf2e5 | 3492 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 3493 | |
3fcaf2e5 EG |
3494 | REG_WR(bp, aeu_addr, aeu_mask); |
3495 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea | 3496 | |
3fcaf2e5 | 3497 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
a2fbb9ea | 3498 | bp->attn_state |= asserted; |
3fcaf2e5 | 3499 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
a2fbb9ea ET |
3500 | |
3501 | if (asserted & ATTN_HARD_WIRED_MASK) { | |
3502 | if (asserted & ATTN_NIG_FOR_FUNC) { | |
a2fbb9ea | 3503 | |
a5e9a7cf EG |
3504 | bnx2x_acquire_phy_lock(bp); |
3505 | ||
877e9aa4 | 3506 | /* save nig interrupt mask */ |
87942b46 | 3507 | nig_mask = REG_RD(bp, nig_int_mask_addr); |
a2fbb9ea | 3508 | |
361c391e YR |
3509 | /* If nig_mask is not set, no need to call the update |
3510 | * function. | |
3511 | */ | |
3512 | if (nig_mask) { | |
3513 | REG_WR(bp, nig_int_mask_addr, 0); | |
3514 | ||
3515 | bnx2x_link_attn(bp); | |
3516 | } | |
a2fbb9ea ET |
3517 | |
3518 | /* handle unicore attn? */ | |
3519 | } | |
3520 | if (asserted & ATTN_SW_TIMER_4_FUNC) | |
3521 | DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); | |
3522 | ||
3523 | if (asserted & GPIO_2_FUNC) | |
3524 | DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); | |
3525 | ||
3526 | if (asserted & GPIO_3_FUNC) | |
3527 | DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); | |
3528 | ||
3529 | if (asserted & GPIO_4_FUNC) | |
3530 | DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); | |
3531 | ||
3532 | if (port == 0) { | |
3533 | if (asserted & ATTN_GENERAL_ATTN_1) { | |
3534 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); | |
3535 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); | |
3536 | } | |
3537 | if (asserted & ATTN_GENERAL_ATTN_2) { | |
3538 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); | |
3539 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); | |
3540 | } | |
3541 | if (asserted & ATTN_GENERAL_ATTN_3) { | |
3542 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); | |
3543 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); | |
3544 | } | |
3545 | } else { | |
3546 | if (asserted & ATTN_GENERAL_ATTN_4) { | |
3547 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); | |
3548 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); | |
3549 | } | |
3550 | if (asserted & ATTN_GENERAL_ATTN_5) { | |
3551 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); | |
3552 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); | |
3553 | } | |
3554 | if (asserted & ATTN_GENERAL_ATTN_6) { | |
3555 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); | |
3556 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); | |
3557 | } | |
3558 | } | |
3559 | ||
3560 | } /* if hardwired */ | |
3561 | ||
f2e0899f DK |
3562 | if (bp->common.int_block == INT_BLOCK_HC) |
3563 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
3564 | COMMAND_REG_ATTN_BITS_SET); | |
3565 | else | |
3566 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); | |
3567 | ||
3568 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, | |
3569 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
3570 | REG_WR(bp, reg_addr, asserted); | |
a2fbb9ea ET |
3571 | |
3572 | /* now set back the mask */ | |
a5e9a7cf | 3573 | if (asserted & ATTN_NIG_FOR_FUNC) { |
87942b46 | 3574 | REG_WR(bp, nig_int_mask_addr, nig_mask); |
a5e9a7cf EG |
3575 | bnx2x_release_phy_lock(bp); |
3576 | } | |
a2fbb9ea ET |
3577 | } |
3578 | ||
1191cb83 | 3579 | static void bnx2x_fan_failure(struct bnx2x *bp) |
fd4ef40d EG |
3580 | { |
3581 | int port = BP_PORT(bp); | |
b7737c9b | 3582 | u32 ext_phy_config; |
fd4ef40d | 3583 | /* mark the failure */ |
b7737c9b YR |
3584 | ext_phy_config = |
3585 | SHMEM_RD(bp, | |
3586 | dev_info.port_hw_config[port].external_phy_config); | |
3587 | ||
3588 | ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | |
3589 | ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; | |
fd4ef40d | 3590 | SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, |
b7737c9b | 3591 | ext_phy_config); |
fd4ef40d EG |
3592 | |
3593 | /* log the failure */ | |
51c1a580 MS |
3594 | netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" |
3595 | "Please contact OEM Support for assistance\n"); | |
8304859a AE |
3596 | |
3597 | /* | |
3598 | * Scheudle device reset (unload) | |
3599 | * This is due to some boards consuming sufficient power when driver is | |
3600 | * up to overheat if fan fails. | |
3601 | */ | |
3602 | smp_mb__before_clear_bit(); | |
3603 | set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); | |
3604 | smp_mb__after_clear_bit(); | |
3605 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
3606 | ||
fd4ef40d | 3607 | } |
ab6ad5a4 | 3608 | |
1191cb83 | 3609 | static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
a2fbb9ea | 3610 | { |
34f80b04 | 3611 | int port = BP_PORT(bp); |
877e9aa4 | 3612 | int reg_offset; |
d90d96ba | 3613 | u32 val; |
877e9aa4 | 3614 | |
34f80b04 EG |
3615 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
3616 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
877e9aa4 | 3617 | |
34f80b04 | 3618 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { |
877e9aa4 ET |
3619 | |
3620 | val = REG_RD(bp, reg_offset); | |
3621 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; | |
3622 | REG_WR(bp, reg_offset, val); | |
3623 | ||
3624 | BNX2X_ERR("SPIO5 hw attention\n"); | |
3625 | ||
fd4ef40d | 3626 | /* Fan failure attention */ |
d90d96ba | 3627 | bnx2x_hw_reset_phy(&bp->link_params); |
fd4ef40d | 3628 | bnx2x_fan_failure(bp); |
877e9aa4 | 3629 | } |
34f80b04 | 3630 | |
3deb8167 | 3631 | if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { |
589abe3a EG |
3632 | bnx2x_acquire_phy_lock(bp); |
3633 | bnx2x_handle_module_detect_int(&bp->link_params); | |
3634 | bnx2x_release_phy_lock(bp); | |
3635 | } | |
3636 | ||
34f80b04 EG |
3637 | if (attn & HW_INTERRUT_ASSERT_SET_0) { |
3638 | ||
3639 | val = REG_RD(bp, reg_offset); | |
3640 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); | |
3641 | REG_WR(bp, reg_offset, val); | |
3642 | ||
3643 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", | |
0fc5d009 | 3644 | (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); |
34f80b04 EG |
3645 | bnx2x_panic(); |
3646 | } | |
877e9aa4 ET |
3647 | } |
3648 | ||
1191cb83 | 3649 | static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
3650 | { |
3651 | u32 val; | |
3652 | ||
0626b899 | 3653 | if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { |
877e9aa4 ET |
3654 | |
3655 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | |
3656 | BNX2X_ERR("DB hw attention 0x%x\n", val); | |
3657 | /* DORQ discard attention */ | |
3658 | if (val & 0x2) | |
3659 | BNX2X_ERR("FATAL error from DORQ\n"); | |
3660 | } | |
34f80b04 EG |
3661 | |
3662 | if (attn & HW_INTERRUT_ASSERT_SET_1) { | |
3663 | ||
3664 | int port = BP_PORT(bp); | |
3665 | int reg_offset; | |
3666 | ||
3667 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : | |
3668 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); | |
3669 | ||
3670 | val = REG_RD(bp, reg_offset); | |
3671 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); | |
3672 | REG_WR(bp, reg_offset, val); | |
3673 | ||
3674 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", | |
0fc5d009 | 3675 | (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); |
34f80b04 EG |
3676 | bnx2x_panic(); |
3677 | } | |
877e9aa4 ET |
3678 | } |
3679 | ||
1191cb83 | 3680 | static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
3681 | { |
3682 | u32 val; | |
3683 | ||
3684 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | |
3685 | ||
3686 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | |
3687 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | |
3688 | /* CFC error attention */ | |
3689 | if (val & 0x2) | |
3690 | BNX2X_ERR("FATAL error from CFC\n"); | |
3691 | } | |
3692 | ||
3693 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | |
877e9aa4 | 3694 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); |
619c5cb6 | 3695 | BNX2X_ERR("PXP hw attention-0 0x%x\n", val); |
877e9aa4 ET |
3696 | /* RQ_USDMDP_FIFO_OVERFLOW */ |
3697 | if (val & 0x18000) | |
3698 | BNX2X_ERR("FATAL error from PXP\n"); | |
619c5cb6 VZ |
3699 | |
3700 | if (!CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
3701 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); |
3702 | BNX2X_ERR("PXP hw attention-1 0x%x\n", val); | |
3703 | } | |
877e9aa4 | 3704 | } |
34f80b04 EG |
3705 | |
3706 | if (attn & HW_INTERRUT_ASSERT_SET_2) { | |
3707 | ||
3708 | int port = BP_PORT(bp); | |
3709 | int reg_offset; | |
3710 | ||
3711 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : | |
3712 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); | |
3713 | ||
3714 | val = REG_RD(bp, reg_offset); | |
3715 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); | |
3716 | REG_WR(bp, reg_offset, val); | |
3717 | ||
3718 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", | |
0fc5d009 | 3719 | (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); |
34f80b04 EG |
3720 | bnx2x_panic(); |
3721 | } | |
877e9aa4 ET |
3722 | } |
3723 | ||
1191cb83 | 3724 | static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) |
877e9aa4 | 3725 | { |
34f80b04 EG |
3726 | u32 val; |
3727 | ||
877e9aa4 ET |
3728 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { |
3729 | ||
34f80b04 EG |
3730 | if (attn & BNX2X_PMF_LINK_ASSERT) { |
3731 | int func = BP_FUNC(bp); | |
3732 | ||
3733 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
a3348722 | 3734 | bnx2x_read_mf_cfg(bp); |
f2e0899f DK |
3735 | bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, |
3736 | func_mf_config[BP_ABS_FUNC(bp)].config); | |
3737 | val = SHMEM_RD(bp, | |
3738 | func_mb[BP_FW_MB_IDX(bp)].drv_status); | |
2691d51d EG |
3739 | if (val & DRV_STATUS_DCC_EVENT_MASK) |
3740 | bnx2x_dcc_event(bp, | |
3741 | (val & DRV_STATUS_DCC_EVENT_MASK)); | |
0793f83f DK |
3742 | |
3743 | if (val & DRV_STATUS_SET_MF_BW) | |
3744 | bnx2x_set_mf_bw(bp); | |
3745 | ||
1d187b34 BW |
3746 | if (val & DRV_STATUS_DRV_INFO_REQ) |
3747 | bnx2x_handle_drv_info_req(bp); | |
2691d51d | 3748 | if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) |
34f80b04 EG |
3749 | bnx2x_pmf_update(bp); |
3750 | ||
e4901dde | 3751 | if (bp->port.pmf && |
785b9b1a SR |
3752 | (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && |
3753 | bp->dcbx_enabled > 0) | |
e4901dde VZ |
3754 | /* start dcbx state machine */ |
3755 | bnx2x_dcbx_set_params(bp, | |
3756 | BNX2X_DCBX_STATE_NEG_RECEIVED); | |
a3348722 BW |
3757 | if (val & DRV_STATUS_AFEX_EVENT_MASK) |
3758 | bnx2x_handle_afex_cmd(bp, | |
3759 | val & DRV_STATUS_AFEX_EVENT_MASK); | |
c8c60d88 YM |
3760 | if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) |
3761 | bnx2x_handle_eee_event(bp); | |
3deb8167 YR |
3762 | if (bp->link_vars.periodic_flags & |
3763 | PERIODIC_FLAGS_LINK_EVENT) { | |
3764 | /* sync with link */ | |
3765 | bnx2x_acquire_phy_lock(bp); | |
3766 | bp->link_vars.periodic_flags &= | |
3767 | ~PERIODIC_FLAGS_LINK_EVENT; | |
3768 | bnx2x_release_phy_lock(bp); | |
3769 | if (IS_MF(bp)) | |
3770 | bnx2x_link_sync_notify(bp); | |
3771 | bnx2x_link_report(bp); | |
3772 | } | |
3773 | /* Always call it here: bnx2x_link_report() will | |
3774 | * prevent the link indication duplication. | |
3775 | */ | |
3776 | bnx2x__link_status_update(bp); | |
34f80b04 | 3777 | } else if (attn & BNX2X_MC_ASSERT_BITS) { |
877e9aa4 ET |
3778 | |
3779 | BNX2X_ERR("MC assert!\n"); | |
d6cae238 | 3780 | bnx2x_mc_assert(bp); |
877e9aa4 ET |
3781 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); |
3782 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); | |
3783 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); | |
3784 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); | |
3785 | bnx2x_panic(); | |
3786 | ||
3787 | } else if (attn & BNX2X_MCP_ASSERT) { | |
3788 | ||
3789 | BNX2X_ERR("MCP assert!\n"); | |
3790 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); | |
34f80b04 | 3791 | bnx2x_fw_dump(bp); |
877e9aa4 ET |
3792 | |
3793 | } else | |
3794 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); | |
3795 | } | |
3796 | ||
3797 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { | |
34f80b04 EG |
3798 | BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); |
3799 | if (attn & BNX2X_GRC_TIMEOUT) { | |
f2e0899f DK |
3800 | val = CHIP_IS_E1(bp) ? 0 : |
3801 | REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); | |
34f80b04 EG |
3802 | BNX2X_ERR("GRC time-out 0x%08x\n", val); |
3803 | } | |
3804 | if (attn & BNX2X_GRC_RSV) { | |
f2e0899f DK |
3805 | val = CHIP_IS_E1(bp) ? 0 : |
3806 | REG_RD(bp, MISC_REG_GRC_RSV_ATTN); | |
34f80b04 EG |
3807 | BNX2X_ERR("GRC reserved 0x%08x\n", val); |
3808 | } | |
877e9aa4 | 3809 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); |
877e9aa4 ET |
3810 | } |
3811 | } | |
3812 | ||
c9ee9206 VZ |
3813 | /* |
3814 | * Bits map: | |
3815 | * 0-7 - Engine0 load counter. | |
3816 | * 8-15 - Engine1 load counter. | |
3817 | * 16 - Engine0 RESET_IN_PROGRESS bit. | |
3818 | * 17 - Engine1 RESET_IN_PROGRESS bit. | |
3819 | * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function | |
3820 | * on the engine | |
3821 | * 19 - Engine1 ONE_IS_LOADED. | |
3822 | * 20 - Chip reset flow bit. When set none-leader must wait for both engines | |
3823 | * leader to complete (check for both RESET_IN_PROGRESS bits and not for | |
3824 | * just the one belonging to its engine). | |
3825 | * | |
3826 | */ | |
3827 | #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 | |
3828 | ||
3829 | #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff | |
3830 | #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 | |
3831 | #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 | |
3832 | #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 | |
3833 | #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 | |
3834 | #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 | |
3835 | #define BNX2X_GLOBAL_RESET_BIT 0x00040000 | |
3836 | ||
3837 | /* | |
3838 | * Set the GLOBAL_RESET bit. | |
3839 | * | |
3840 | * Should be run under rtnl lock | |
3841 | */ | |
3842 | void bnx2x_set_reset_global(struct bnx2x *bp) | |
3843 | { | |
f16da43b AE |
3844 | u32 val; |
3845 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
3846 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 3847 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); |
f16da43b | 3848 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 VZ |
3849 | } |
3850 | ||
3851 | /* | |
3852 | * Clear the GLOBAL_RESET bit. | |
3853 | * | |
3854 | * Should be run under rtnl lock | |
3855 | */ | |
1191cb83 | 3856 | static void bnx2x_clear_reset_global(struct bnx2x *bp) |
c9ee9206 | 3857 | { |
f16da43b AE |
3858 | u32 val; |
3859 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
3860 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 3861 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); |
f16da43b | 3862 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 | 3863 | } |
f85582f8 | 3864 | |
72fd0718 | 3865 | /* |
c9ee9206 VZ |
3866 | * Checks the GLOBAL_RESET bit. |
3867 | * | |
72fd0718 VZ |
3868 | * should be run under rtnl lock |
3869 | */ | |
1191cb83 | 3870 | static bool bnx2x_reset_is_global(struct bnx2x *bp) |
c9ee9206 VZ |
3871 | { |
3872 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3873 | ||
3874 | DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); | |
3875 | return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; | |
3876 | } | |
3877 | ||
3878 | /* | |
3879 | * Clear RESET_IN_PROGRESS bit for the current engine. | |
3880 | * | |
3881 | * Should be run under rtnl lock | |
3882 | */ | |
1191cb83 | 3883 | static void bnx2x_set_reset_done(struct bnx2x *bp) |
72fd0718 | 3884 | { |
f16da43b | 3885 | u32 val; |
c9ee9206 VZ |
3886 | u32 bit = BP_PATH(bp) ? |
3887 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
3888 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3889 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
3890 | |
3891 | /* Clear the bit */ | |
3892 | val &= ~bit; | |
3893 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
3894 | |
3895 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
72fd0718 VZ |
3896 | } |
3897 | ||
3898 | /* | |
c9ee9206 VZ |
3899 | * Set RESET_IN_PROGRESS for the current engine. |
3900 | * | |
72fd0718 VZ |
3901 | * should be run under rtnl lock |
3902 | */ | |
c9ee9206 | 3903 | void bnx2x_set_reset_in_progress(struct bnx2x *bp) |
72fd0718 | 3904 | { |
f16da43b | 3905 | u32 val; |
c9ee9206 VZ |
3906 | u32 bit = BP_PATH(bp) ? |
3907 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
3908 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3909 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
3910 | |
3911 | /* Set the bit */ | |
3912 | val |= bit; | |
3913 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 3914 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
3915 | } |
3916 | ||
3917 | /* | |
c9ee9206 | 3918 | * Checks the RESET_IN_PROGRESS bit for the given engine. |
72fd0718 VZ |
3919 | * should be run under rtnl lock |
3920 | */ | |
c9ee9206 | 3921 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) |
72fd0718 | 3922 | { |
c9ee9206 VZ |
3923 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3924 | u32 bit = engine ? | |
3925 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
3926 | ||
3927 | /* return false if bit is set */ | |
3928 | return (val & bit) ? false : true; | |
72fd0718 VZ |
3929 | } |
3930 | ||
3931 | /* | |
889b9af3 | 3932 | * set pf load for the current pf. |
c9ee9206 | 3933 | * |
72fd0718 VZ |
3934 | * should be run under rtnl lock |
3935 | */ | |
889b9af3 | 3936 | void bnx2x_set_pf_load(struct bnx2x *bp) |
72fd0718 | 3937 | { |
f16da43b | 3938 | u32 val1, val; |
c9ee9206 VZ |
3939 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
3940 | BNX2X_PATH0_LOAD_CNT_MASK; | |
3941 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3942 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 3943 | |
f16da43b AE |
3944 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3945 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3946 | ||
51c1a580 | 3947 | DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 3948 | |
c9ee9206 VZ |
3949 | /* get the current counter value */ |
3950 | val1 = (val & mask) >> shift; | |
3951 | ||
889b9af3 AE |
3952 | /* set bit of that PF */ |
3953 | val1 |= (1 << bp->pf_num); | |
c9ee9206 VZ |
3954 | |
3955 | /* clear the old value */ | |
3956 | val &= ~mask; | |
3957 | ||
3958 | /* set the new one */ | |
3959 | val |= ((val1 << shift) & mask); | |
3960 | ||
3961 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 3962 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
3963 | } |
3964 | ||
c9ee9206 | 3965 | /** |
889b9af3 | 3966 | * bnx2x_clear_pf_load - clear pf load mark |
c9ee9206 VZ |
3967 | * |
3968 | * @bp: driver handle | |
3969 | * | |
3970 | * Should be run under rtnl lock. | |
3971 | * Decrements the load counter for the current engine. Returns | |
889b9af3 | 3972 | * whether other functions are still loaded |
72fd0718 | 3973 | */ |
889b9af3 | 3974 | bool bnx2x_clear_pf_load(struct bnx2x *bp) |
72fd0718 | 3975 | { |
f16da43b | 3976 | u32 val1, val; |
c9ee9206 VZ |
3977 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
3978 | BNX2X_PATH0_LOAD_CNT_MASK; | |
3979 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3980 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 3981 | |
f16da43b AE |
3982 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3983 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
51c1a580 | 3984 | DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 3985 | |
c9ee9206 VZ |
3986 | /* get the current counter value */ |
3987 | val1 = (val & mask) >> shift; | |
3988 | ||
889b9af3 AE |
3989 | /* clear bit of that PF */ |
3990 | val1 &= ~(1 << bp->pf_num); | |
c9ee9206 VZ |
3991 | |
3992 | /* clear the old value */ | |
3993 | val &= ~mask; | |
3994 | ||
3995 | /* set the new one */ | |
3996 | val |= ((val1 << shift) & mask); | |
3997 | ||
3998 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
3999 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4000 | return val1 != 0; | |
72fd0718 VZ |
4001 | } |
4002 | ||
4003 | /* | |
889b9af3 | 4004 | * Read the load status for the current engine. |
c9ee9206 | 4005 | * |
72fd0718 VZ |
4006 | * should be run under rtnl lock |
4007 | */ | |
1191cb83 | 4008 | static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) |
72fd0718 | 4009 | { |
c9ee9206 VZ |
4010 | u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : |
4011 | BNX2X_PATH0_LOAD_CNT_MASK); | |
4012 | u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4013 | BNX2X_PATH0_LOAD_CNT_SHIFT); | |
4014 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4015 | ||
51c1a580 | 4016 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); |
c9ee9206 VZ |
4017 | |
4018 | val = (val & mask) >> shift; | |
4019 | ||
51c1a580 MS |
4020 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", |
4021 | engine, val); | |
c9ee9206 | 4022 | |
889b9af3 | 4023 | return val != 0; |
72fd0718 VZ |
4024 | } |
4025 | ||
c9ee9206 | 4026 | /* |
889b9af3 | 4027 | * Reset the load status for the current engine. |
c9ee9206 | 4028 | */ |
1191cb83 | 4029 | static void bnx2x_clear_load_status(struct bnx2x *bp) |
72fd0718 | 4030 | { |
f16da43b | 4031 | u32 val; |
c9ee9206 | 4032 | u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
f16da43b AE |
4033 | BNX2X_PATH0_LOAD_CNT_MASK); |
4034 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
4035 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 4036 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); |
f16da43b | 4037 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4038 | } |
4039 | ||
1191cb83 | 4040 | static void _print_next_block(int idx, const char *blk) |
72fd0718 | 4041 | { |
f1deab50 | 4042 | pr_cont("%s%s", idx ? ", " : "", blk); |
72fd0718 VZ |
4043 | } |
4044 | ||
1191cb83 ED |
4045 | static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, |
4046 | bool print) | |
72fd0718 VZ |
4047 | { |
4048 | int i = 0; | |
4049 | u32 cur_bit = 0; | |
4050 | for (i = 0; sig; i++) { | |
4051 | cur_bit = ((u32)0x1 << i); | |
4052 | if (sig & cur_bit) { | |
4053 | switch (cur_bit) { | |
4054 | case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: | |
c9ee9206 VZ |
4055 | if (print) |
4056 | _print_next_block(par_num++, "BRB"); | |
72fd0718 VZ |
4057 | break; |
4058 | case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: | |
c9ee9206 VZ |
4059 | if (print) |
4060 | _print_next_block(par_num++, "PARSER"); | |
72fd0718 VZ |
4061 | break; |
4062 | case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: | |
c9ee9206 VZ |
4063 | if (print) |
4064 | _print_next_block(par_num++, "TSDM"); | |
72fd0718 VZ |
4065 | break; |
4066 | case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: | |
c9ee9206 VZ |
4067 | if (print) |
4068 | _print_next_block(par_num++, | |
4069 | "SEARCHER"); | |
4070 | break; | |
4071 | case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: | |
4072 | if (print) | |
4073 | _print_next_block(par_num++, "TCM"); | |
72fd0718 VZ |
4074 | break; |
4075 | case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
4076 | if (print) |
4077 | _print_next_block(par_num++, "TSEMI"); | |
4078 | break; | |
4079 | case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: | |
4080 | if (print) | |
4081 | _print_next_block(par_num++, "XPB"); | |
72fd0718 VZ |
4082 | break; |
4083 | } | |
4084 | ||
4085 | /* Clear the bit */ | |
4086 | sig &= ~cur_bit; | |
4087 | } | |
4088 | } | |
4089 | ||
4090 | return par_num; | |
4091 | } | |
4092 | ||
1191cb83 ED |
4093 | static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, |
4094 | bool *global, bool print) | |
72fd0718 VZ |
4095 | { |
4096 | int i = 0; | |
4097 | u32 cur_bit = 0; | |
4098 | for (i = 0; sig; i++) { | |
4099 | cur_bit = ((u32)0x1 << i); | |
4100 | if (sig & cur_bit) { | |
4101 | switch (cur_bit) { | |
c9ee9206 VZ |
4102 | case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: |
4103 | if (print) | |
4104 | _print_next_block(par_num++, "PBF"); | |
72fd0718 VZ |
4105 | break; |
4106 | case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: | |
c9ee9206 VZ |
4107 | if (print) |
4108 | _print_next_block(par_num++, "QM"); | |
4109 | break; | |
4110 | case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: | |
4111 | if (print) | |
4112 | _print_next_block(par_num++, "TM"); | |
72fd0718 VZ |
4113 | break; |
4114 | case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: | |
c9ee9206 VZ |
4115 | if (print) |
4116 | _print_next_block(par_num++, "XSDM"); | |
4117 | break; | |
4118 | case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: | |
4119 | if (print) | |
4120 | _print_next_block(par_num++, "XCM"); | |
72fd0718 VZ |
4121 | break; |
4122 | case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
4123 | if (print) |
4124 | _print_next_block(par_num++, "XSEMI"); | |
72fd0718 VZ |
4125 | break; |
4126 | case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: | |
c9ee9206 VZ |
4127 | if (print) |
4128 | _print_next_block(par_num++, | |
4129 | "DOORBELLQ"); | |
4130 | break; | |
4131 | case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: | |
4132 | if (print) | |
4133 | _print_next_block(par_num++, "NIG"); | |
72fd0718 VZ |
4134 | break; |
4135 | case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: | |
c9ee9206 VZ |
4136 | if (print) |
4137 | _print_next_block(par_num++, | |
4138 | "VAUX PCI CORE"); | |
4139 | *global = true; | |
72fd0718 VZ |
4140 | break; |
4141 | case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: | |
c9ee9206 VZ |
4142 | if (print) |
4143 | _print_next_block(par_num++, "DEBUG"); | |
72fd0718 VZ |
4144 | break; |
4145 | case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: | |
c9ee9206 VZ |
4146 | if (print) |
4147 | _print_next_block(par_num++, "USDM"); | |
72fd0718 | 4148 | break; |
8736c826 VZ |
4149 | case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: |
4150 | if (print) | |
4151 | _print_next_block(par_num++, "UCM"); | |
4152 | break; | |
72fd0718 | 4153 | case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: |
c9ee9206 VZ |
4154 | if (print) |
4155 | _print_next_block(par_num++, "USEMI"); | |
72fd0718 VZ |
4156 | break; |
4157 | case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: | |
c9ee9206 VZ |
4158 | if (print) |
4159 | _print_next_block(par_num++, "UPB"); | |
72fd0718 VZ |
4160 | break; |
4161 | case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: | |
c9ee9206 VZ |
4162 | if (print) |
4163 | _print_next_block(par_num++, "CSDM"); | |
72fd0718 | 4164 | break; |
8736c826 VZ |
4165 | case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: |
4166 | if (print) | |
4167 | _print_next_block(par_num++, "CCM"); | |
4168 | break; | |
72fd0718 VZ |
4169 | } |
4170 | ||
4171 | /* Clear the bit */ | |
4172 | sig &= ~cur_bit; | |
4173 | } | |
4174 | } | |
4175 | ||
4176 | return par_num; | |
4177 | } | |
4178 | ||
1191cb83 ED |
4179 | static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, |
4180 | bool print) | |
72fd0718 VZ |
4181 | { |
4182 | int i = 0; | |
4183 | u32 cur_bit = 0; | |
4184 | for (i = 0; sig; i++) { | |
4185 | cur_bit = ((u32)0x1 << i); | |
4186 | if (sig & cur_bit) { | |
4187 | switch (cur_bit) { | |
4188 | case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
4189 | if (print) |
4190 | _print_next_block(par_num++, "CSEMI"); | |
72fd0718 VZ |
4191 | break; |
4192 | case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: | |
c9ee9206 VZ |
4193 | if (print) |
4194 | _print_next_block(par_num++, "PXP"); | |
72fd0718 VZ |
4195 | break; |
4196 | case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: | |
c9ee9206 VZ |
4197 | if (print) |
4198 | _print_next_block(par_num++, | |
72fd0718 VZ |
4199 | "PXPPCICLOCKCLIENT"); |
4200 | break; | |
4201 | case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: | |
c9ee9206 VZ |
4202 | if (print) |
4203 | _print_next_block(par_num++, "CFC"); | |
72fd0718 VZ |
4204 | break; |
4205 | case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: | |
c9ee9206 VZ |
4206 | if (print) |
4207 | _print_next_block(par_num++, "CDU"); | |
4208 | break; | |
4209 | case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: | |
4210 | if (print) | |
4211 | _print_next_block(par_num++, "DMAE"); | |
72fd0718 VZ |
4212 | break; |
4213 | case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: | |
c9ee9206 VZ |
4214 | if (print) |
4215 | _print_next_block(par_num++, "IGU"); | |
72fd0718 VZ |
4216 | break; |
4217 | case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: | |
c9ee9206 VZ |
4218 | if (print) |
4219 | _print_next_block(par_num++, "MISC"); | |
72fd0718 VZ |
4220 | break; |
4221 | } | |
4222 | ||
4223 | /* Clear the bit */ | |
4224 | sig &= ~cur_bit; | |
4225 | } | |
4226 | } | |
4227 | ||
4228 | return par_num; | |
4229 | } | |
4230 | ||
1191cb83 ED |
4231 | static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, |
4232 | bool *global, bool print) | |
72fd0718 VZ |
4233 | { |
4234 | int i = 0; | |
4235 | u32 cur_bit = 0; | |
4236 | for (i = 0; sig; i++) { | |
4237 | cur_bit = ((u32)0x1 << i); | |
4238 | if (sig & cur_bit) { | |
4239 | switch (cur_bit) { | |
4240 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: | |
c9ee9206 VZ |
4241 | if (print) |
4242 | _print_next_block(par_num++, "MCP ROM"); | |
4243 | *global = true; | |
72fd0718 VZ |
4244 | break; |
4245 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: | |
c9ee9206 VZ |
4246 | if (print) |
4247 | _print_next_block(par_num++, | |
4248 | "MCP UMP RX"); | |
4249 | *global = true; | |
72fd0718 VZ |
4250 | break; |
4251 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: | |
c9ee9206 VZ |
4252 | if (print) |
4253 | _print_next_block(par_num++, | |
4254 | "MCP UMP TX"); | |
4255 | *global = true; | |
72fd0718 VZ |
4256 | break; |
4257 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: | |
c9ee9206 VZ |
4258 | if (print) |
4259 | _print_next_block(par_num++, | |
4260 | "MCP SCPAD"); | |
4261 | *global = true; | |
72fd0718 VZ |
4262 | break; |
4263 | } | |
4264 | ||
4265 | /* Clear the bit */ | |
4266 | sig &= ~cur_bit; | |
4267 | } | |
4268 | } | |
4269 | ||
4270 | return par_num; | |
4271 | } | |
4272 | ||
1191cb83 ED |
4273 | static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, |
4274 | bool print) | |
8736c826 VZ |
4275 | { |
4276 | int i = 0; | |
4277 | u32 cur_bit = 0; | |
4278 | for (i = 0; sig; i++) { | |
4279 | cur_bit = ((u32)0x1 << i); | |
4280 | if (sig & cur_bit) { | |
4281 | switch (cur_bit) { | |
4282 | case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: | |
4283 | if (print) | |
4284 | _print_next_block(par_num++, "PGLUE_B"); | |
4285 | break; | |
4286 | case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: | |
4287 | if (print) | |
4288 | _print_next_block(par_num++, "ATC"); | |
4289 | break; | |
4290 | } | |
4291 | ||
4292 | /* Clear the bit */ | |
4293 | sig &= ~cur_bit; | |
4294 | } | |
4295 | } | |
4296 | ||
4297 | return par_num; | |
4298 | } | |
4299 | ||
1191cb83 ED |
4300 | static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, |
4301 | u32 *sig) | |
72fd0718 | 4302 | { |
8736c826 VZ |
4303 | if ((sig[0] & HW_PRTY_ASSERT_SET_0) || |
4304 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
4305 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
4306 | (sig[3] & HW_PRTY_ASSERT_SET_3) || | |
4307 | (sig[4] & HW_PRTY_ASSERT_SET_4)) { | |
72fd0718 | 4308 | int par_num = 0; |
51c1a580 MS |
4309 | DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" |
4310 | "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", | |
8736c826 VZ |
4311 | sig[0] & HW_PRTY_ASSERT_SET_0, |
4312 | sig[1] & HW_PRTY_ASSERT_SET_1, | |
4313 | sig[2] & HW_PRTY_ASSERT_SET_2, | |
4314 | sig[3] & HW_PRTY_ASSERT_SET_3, | |
4315 | sig[4] & HW_PRTY_ASSERT_SET_4); | |
c9ee9206 VZ |
4316 | if (print) |
4317 | netdev_err(bp->dev, | |
4318 | "Parity errors detected in blocks: "); | |
4319 | par_num = bnx2x_check_blocks_with_parity0( | |
8736c826 | 4320 | sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); |
c9ee9206 | 4321 | par_num = bnx2x_check_blocks_with_parity1( |
8736c826 | 4322 | sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); |
c9ee9206 | 4323 | par_num = bnx2x_check_blocks_with_parity2( |
8736c826 | 4324 | sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); |
c9ee9206 | 4325 | par_num = bnx2x_check_blocks_with_parity3( |
8736c826 VZ |
4326 | sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); |
4327 | par_num = bnx2x_check_blocks_with_parity4( | |
4328 | sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); | |
4329 | ||
c9ee9206 VZ |
4330 | if (print) |
4331 | pr_cont("\n"); | |
8736c826 | 4332 | |
72fd0718 VZ |
4333 | return true; |
4334 | } else | |
4335 | return false; | |
4336 | } | |
4337 | ||
c9ee9206 VZ |
4338 | /** |
4339 | * bnx2x_chk_parity_attn - checks for parity attentions. | |
4340 | * | |
4341 | * @bp: driver handle | |
4342 | * @global: true if there was a global attention | |
4343 | * @print: show parity attention in syslog | |
4344 | */ | |
4345 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) | |
877e9aa4 | 4346 | { |
8736c826 | 4347 | struct attn_route attn = { {0} }; |
72fd0718 VZ |
4348 | int port = BP_PORT(bp); |
4349 | ||
4350 | attn.sig[0] = REG_RD(bp, | |
4351 | MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + | |
4352 | port*4); | |
4353 | attn.sig[1] = REG_RD(bp, | |
4354 | MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + | |
4355 | port*4); | |
4356 | attn.sig[2] = REG_RD(bp, | |
4357 | MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + | |
4358 | port*4); | |
4359 | attn.sig[3] = REG_RD(bp, | |
4360 | MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + | |
4361 | port*4); | |
4362 | ||
8736c826 VZ |
4363 | if (!CHIP_IS_E1x(bp)) |
4364 | attn.sig[4] = REG_RD(bp, | |
4365 | MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + | |
4366 | port*4); | |
4367 | ||
4368 | return bnx2x_parity_attn(bp, global, print, attn.sig); | |
72fd0718 VZ |
4369 | } |
4370 | ||
f2e0899f | 4371 | |
1191cb83 | 4372 | static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) |
f2e0899f DK |
4373 | { |
4374 | u32 val; | |
4375 | if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { | |
4376 | ||
4377 | val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); | |
4378 | BNX2X_ERR("PGLUE hw attention 0x%x\n", val); | |
4379 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) | |
51c1a580 | 4380 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); |
f2e0899f | 4381 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) |
51c1a580 | 4382 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); |
f2e0899f | 4383 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) |
51c1a580 | 4384 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); |
f2e0899f | 4385 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) |
51c1a580 | 4386 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); |
f2e0899f DK |
4387 | if (val & |
4388 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) | |
51c1a580 | 4389 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); |
f2e0899f DK |
4390 | if (val & |
4391 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) | |
51c1a580 | 4392 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); |
f2e0899f | 4393 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) |
51c1a580 | 4394 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); |
f2e0899f | 4395 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) |
51c1a580 | 4396 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); |
f2e0899f | 4397 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) |
51c1a580 | 4398 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); |
f2e0899f DK |
4399 | } |
4400 | if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { | |
4401 | val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); | |
4402 | BNX2X_ERR("ATC hw attention 0x%x\n", val); | |
4403 | if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) | |
4404 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); | |
4405 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) | |
51c1a580 | 4406 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); |
f2e0899f | 4407 | if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) |
51c1a580 | 4408 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); |
f2e0899f | 4409 | if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) |
51c1a580 | 4410 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); |
f2e0899f DK |
4411 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) |
4412 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); | |
4413 | if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) | |
51c1a580 | 4414 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); |
f2e0899f DK |
4415 | } |
4416 | ||
4417 | if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4418 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { | |
4419 | BNX2X_ERR("FATAL parity attention set4 0x%x\n", | |
4420 | (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4421 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); | |
4422 | } | |
4423 | ||
4424 | } | |
4425 | ||
72fd0718 VZ |
4426 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) |
4427 | { | |
4428 | struct attn_route attn, *group_mask; | |
34f80b04 | 4429 | int port = BP_PORT(bp); |
877e9aa4 | 4430 | int index; |
a2fbb9ea ET |
4431 | u32 reg_addr; |
4432 | u32 val; | |
3fcaf2e5 | 4433 | u32 aeu_mask; |
c9ee9206 | 4434 | bool global = false; |
a2fbb9ea ET |
4435 | |
4436 | /* need to take HW lock because MCP or other port might also | |
4437 | try to handle this event */ | |
4a37fb66 | 4438 | bnx2x_acquire_alr(bp); |
a2fbb9ea | 4439 | |
c9ee9206 VZ |
4440 | if (bnx2x_chk_parity_attn(bp, &global, true)) { |
4441 | #ifndef BNX2X_STOP_ON_ERROR | |
72fd0718 | 4442 | bp->recovery_state = BNX2X_RECOVERY_INIT; |
7be08a72 | 4443 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
72fd0718 VZ |
4444 | /* Disable HW interrupts */ |
4445 | bnx2x_int_disable(bp); | |
72fd0718 VZ |
4446 | /* In case of parity errors don't handle attentions so that |
4447 | * other function would "see" parity errors. | |
4448 | */ | |
c9ee9206 VZ |
4449 | #else |
4450 | bnx2x_panic(); | |
4451 | #endif | |
4452 | bnx2x_release_alr(bp); | |
72fd0718 VZ |
4453 | return; |
4454 | } | |
4455 | ||
a2fbb9ea ET |
4456 | attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); |
4457 | attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); | |
4458 | attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); | |
4459 | attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); | |
619c5cb6 | 4460 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
4461 | attn.sig[4] = |
4462 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); | |
4463 | else | |
4464 | attn.sig[4] = 0; | |
4465 | ||
4466 | DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", | |
4467 | attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); | |
a2fbb9ea ET |
4468 | |
4469 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { | |
4470 | if (deasserted & (1 << index)) { | |
72fd0718 | 4471 | group_mask = &bp->attn_group[index]; |
a2fbb9ea | 4472 | |
51c1a580 | 4473 | DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", |
f2e0899f DK |
4474 | index, |
4475 | group_mask->sig[0], group_mask->sig[1], | |
4476 | group_mask->sig[2], group_mask->sig[3], | |
4477 | group_mask->sig[4]); | |
a2fbb9ea | 4478 | |
f2e0899f DK |
4479 | bnx2x_attn_int_deasserted4(bp, |
4480 | attn.sig[4] & group_mask->sig[4]); | |
877e9aa4 | 4481 | bnx2x_attn_int_deasserted3(bp, |
72fd0718 | 4482 | attn.sig[3] & group_mask->sig[3]); |
877e9aa4 | 4483 | bnx2x_attn_int_deasserted1(bp, |
72fd0718 | 4484 | attn.sig[1] & group_mask->sig[1]); |
877e9aa4 | 4485 | bnx2x_attn_int_deasserted2(bp, |
72fd0718 | 4486 | attn.sig[2] & group_mask->sig[2]); |
877e9aa4 | 4487 | bnx2x_attn_int_deasserted0(bp, |
72fd0718 | 4488 | attn.sig[0] & group_mask->sig[0]); |
a2fbb9ea ET |
4489 | } |
4490 | } | |
4491 | ||
4a37fb66 | 4492 | bnx2x_release_alr(bp); |
a2fbb9ea | 4493 | |
f2e0899f DK |
4494 | if (bp->common.int_block == INT_BLOCK_HC) |
4495 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
4496 | COMMAND_REG_ATTN_BITS_CLR); | |
4497 | else | |
4498 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); | |
a2fbb9ea ET |
4499 | |
4500 | val = ~deasserted; | |
f2e0899f DK |
4501 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, |
4502 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
5c862848 | 4503 | REG_WR(bp, reg_addr, val); |
a2fbb9ea | 4504 | |
a2fbb9ea | 4505 | if (~bp->attn_state & deasserted) |
3fcaf2e5 | 4506 | BNX2X_ERR("IGU ERROR\n"); |
a2fbb9ea ET |
4507 | |
4508 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
4509 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
4510 | ||
3fcaf2e5 EG |
4511 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
4512 | aeu_mask = REG_RD(bp, reg_addr); | |
4513 | ||
4514 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", | |
4515 | aeu_mask, deasserted); | |
72fd0718 | 4516 | aeu_mask |= (deasserted & 0x3ff); |
3fcaf2e5 | 4517 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 4518 | |
3fcaf2e5 EG |
4519 | REG_WR(bp, reg_addr, aeu_mask); |
4520 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea ET |
4521 | |
4522 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | |
4523 | bp->attn_state &= ~deasserted; | |
4524 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); | |
4525 | } | |
4526 | ||
4527 | static void bnx2x_attn_int(struct bnx2x *bp) | |
4528 | { | |
4529 | /* read local copy of bits */ | |
68d59484 EG |
4530 | u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. |
4531 | attn_bits); | |
4532 | u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. | |
4533 | attn_bits_ack); | |
a2fbb9ea ET |
4534 | u32 attn_state = bp->attn_state; |
4535 | ||
4536 | /* look for changed bits */ | |
4537 | u32 asserted = attn_bits & ~attn_ack & ~attn_state; | |
4538 | u32 deasserted = ~attn_bits & attn_ack & attn_state; | |
4539 | ||
4540 | DP(NETIF_MSG_HW, | |
4541 | "attn_bits %x attn_ack %x asserted %x deasserted %x\n", | |
4542 | attn_bits, attn_ack, asserted, deasserted); | |
4543 | ||
4544 | if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) | |
34f80b04 | 4545 | BNX2X_ERR("BAD attention state\n"); |
a2fbb9ea ET |
4546 | |
4547 | /* handle bits that were raised */ | |
4548 | if (asserted) | |
4549 | bnx2x_attn_int_asserted(bp, asserted); | |
4550 | ||
4551 | if (deasserted) | |
4552 | bnx2x_attn_int_deasserted(bp, deasserted); | |
4553 | } | |
4554 | ||
619c5cb6 VZ |
4555 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, |
4556 | u16 index, u8 op, u8 update) | |
4557 | { | |
4558 | u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
4559 | ||
4560 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, | |
4561 | igu_addr); | |
4562 | } | |
4563 | ||
1191cb83 | 4564 | static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) |
523224a3 DK |
4565 | { |
4566 | /* No memory barriers */ | |
4567 | storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); | |
4568 | mmiowb(); /* keep prod updates ordered */ | |
4569 | } | |
4570 | ||
4571 | #ifdef BCM_CNIC | |
4572 | static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, | |
4573 | union event_ring_elem *elem) | |
4574 | { | |
619c5cb6 VZ |
4575 | u8 err = elem->message.error; |
4576 | ||
523224a3 | 4577 | if (!bp->cnic_eth_dev.starting_cid || |
c3a8ce61 VZ |
4578 | (cid < bp->cnic_eth_dev.starting_cid && |
4579 | cid != bp->cnic_eth_dev.iscsi_l2_cid)) | |
523224a3 DK |
4580 | return 1; |
4581 | ||
4582 | DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); | |
4583 | ||
619c5cb6 VZ |
4584 | if (unlikely(err)) { |
4585 | ||
523224a3 DK |
4586 | BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", |
4587 | cid); | |
4588 | bnx2x_panic_dump(bp); | |
4589 | } | |
619c5cb6 | 4590 | bnx2x_cnic_cfc_comp(bp, cid, err); |
523224a3 DK |
4591 | return 0; |
4592 | } | |
4593 | #endif | |
4594 | ||
1191cb83 | 4595 | static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
4596 | { |
4597 | struct bnx2x_mcast_ramrod_params rparam; | |
4598 | int rc; | |
4599 | ||
4600 | memset(&rparam, 0, sizeof(rparam)); | |
4601 | ||
4602 | rparam.mcast_obj = &bp->mcast_obj; | |
4603 | ||
4604 | netif_addr_lock_bh(bp->dev); | |
4605 | ||
4606 | /* Clear pending state for the last command */ | |
4607 | bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); | |
4608 | ||
4609 | /* If there are pending mcast commands - send them */ | |
4610 | if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { | |
4611 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
4612 | if (rc < 0) | |
4613 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", | |
4614 | rc); | |
4615 | } | |
4616 | ||
4617 | netif_addr_unlock_bh(bp->dev); | |
4618 | } | |
4619 | ||
1191cb83 ED |
4620 | static void bnx2x_handle_classification_eqe(struct bnx2x *bp, |
4621 | union event_ring_elem *elem) | |
619c5cb6 VZ |
4622 | { |
4623 | unsigned long ramrod_flags = 0; | |
4624 | int rc = 0; | |
4625 | u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; | |
4626 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; | |
4627 | ||
4628 | /* Always push next commands out, don't wait here */ | |
4629 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
4630 | ||
4631 | switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { | |
4632 | case BNX2X_FILTER_MAC_PENDING: | |
51c1a580 | 4633 | DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); |
619c5cb6 | 4634 | #ifdef BCM_CNIC |
37ae41a9 | 4635 | if (cid == BNX2X_ISCSI_ETH_CID(bp)) |
619c5cb6 VZ |
4636 | vlan_mac_obj = &bp->iscsi_l2_mac_obj; |
4637 | else | |
4638 | #endif | |
15192a8c | 4639 | vlan_mac_obj = &bp->sp_objs[cid].mac_obj; |
619c5cb6 VZ |
4640 | |
4641 | break; | |
619c5cb6 | 4642 | case BNX2X_FILTER_MCAST_PENDING: |
51c1a580 | 4643 | DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); |
619c5cb6 VZ |
4644 | /* This is only relevant for 57710 where multicast MACs are |
4645 | * configured as unicast MACs using the same ramrod. | |
4646 | */ | |
4647 | bnx2x_handle_mcast_eqe(bp); | |
4648 | return; | |
4649 | default: | |
4650 | BNX2X_ERR("Unsupported classification command: %d\n", | |
4651 | elem->message.data.eth_event.echo); | |
4652 | return; | |
4653 | } | |
4654 | ||
4655 | rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); | |
4656 | ||
4657 | if (rc < 0) | |
4658 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); | |
4659 | else if (rc > 0) | |
4660 | DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); | |
4661 | ||
4662 | } | |
4663 | ||
4664 | #ifdef BCM_CNIC | |
4665 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); | |
4666 | #endif | |
4667 | ||
1191cb83 | 4668 | static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
4669 | { |
4670 | netif_addr_lock_bh(bp->dev); | |
4671 | ||
4672 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
4673 | ||
4674 | /* Send rx_mode command again if was requested */ | |
4675 | if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) | |
4676 | bnx2x_set_storm_rx_mode(bp); | |
4677 | #ifdef BCM_CNIC | |
4678 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, | |
4679 | &bp->sp_state)) | |
4680 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
4681 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, | |
4682 | &bp->sp_state)) | |
4683 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
4684 | #endif | |
4685 | ||
4686 | netif_addr_unlock_bh(bp->dev); | |
4687 | } | |
4688 | ||
1191cb83 | 4689 | static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, |
a3348722 BW |
4690 | union event_ring_elem *elem) |
4691 | { | |
4692 | if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { | |
4693 | DP(BNX2X_MSG_SP, | |
4694 | "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", | |
4695 | elem->message.data.vif_list_event.func_bit_map); | |
4696 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, | |
4697 | elem->message.data.vif_list_event.func_bit_map); | |
4698 | } else if (elem->message.data.vif_list_event.echo == | |
4699 | VIF_LIST_RULE_SET) { | |
4700 | DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); | |
4701 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); | |
4702 | } | |
4703 | } | |
4704 | ||
4705 | /* called with rtnl_lock */ | |
1191cb83 | 4706 | static void bnx2x_after_function_update(struct bnx2x *bp) |
a3348722 BW |
4707 | { |
4708 | int q, rc; | |
4709 | struct bnx2x_fastpath *fp; | |
4710 | struct bnx2x_queue_state_params queue_params = {NULL}; | |
4711 | struct bnx2x_queue_update_params *q_update_params = | |
4712 | &queue_params.params.update; | |
4713 | ||
4714 | /* Send Q update command with afex vlan removal values for all Qs */ | |
4715 | queue_params.cmd = BNX2X_Q_CMD_UPDATE; | |
4716 | ||
4717 | /* set silent vlan removal values according to vlan mode */ | |
4718 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, | |
4719 | &q_update_params->update_flags); | |
4720 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, | |
4721 | &q_update_params->update_flags); | |
4722 | __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
4723 | ||
4724 | /* in access mode mark mask and value are 0 to strip all vlans */ | |
4725 | if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { | |
4726 | q_update_params->silent_removal_value = 0; | |
4727 | q_update_params->silent_removal_mask = 0; | |
4728 | } else { | |
4729 | q_update_params->silent_removal_value = | |
4730 | (bp->afex_def_vlan_tag & VLAN_VID_MASK); | |
4731 | q_update_params->silent_removal_mask = VLAN_VID_MASK; | |
4732 | } | |
4733 | ||
4734 | for_each_eth_queue(bp, q) { | |
4735 | /* Set the appropriate Queue object */ | |
4736 | fp = &bp->fp[q]; | |
15192a8c | 4737 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
4738 | |
4739 | /* send the ramrod */ | |
4740 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
4741 | if (rc < 0) | |
4742 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
4743 | q); | |
4744 | } | |
4745 | ||
4746 | #ifdef BCM_CNIC | |
4747 | if (!NO_FCOE(bp)) { | |
65565884 | 4748 | fp = &bp->fp[FCOE_IDX(bp)]; |
15192a8c | 4749 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
4750 | |
4751 | /* clear pending completion bit */ | |
4752 | __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
4753 | ||
4754 | /* mark latest Q bit */ | |
4755 | smp_mb__before_clear_bit(); | |
4756 | set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
4757 | smp_mb__after_clear_bit(); | |
4758 | ||
4759 | /* send Q update ramrod for FCoE Q */ | |
4760 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
4761 | if (rc < 0) | |
4762 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
4763 | q); | |
4764 | } else { | |
4765 | /* If no FCoE ring - ACK MCP now */ | |
4766 | bnx2x_link_report(bp); | |
4767 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
4768 | } | |
4769 | #else | |
4770 | /* If no FCoE ring - ACK MCP now */ | |
4771 | bnx2x_link_report(bp); | |
4772 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
4773 | #endif /* BCM_CNIC */ | |
4774 | } | |
4775 | ||
1191cb83 | 4776 | static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( |
619c5cb6 VZ |
4777 | struct bnx2x *bp, u32 cid) |
4778 | { | |
94f05b0f | 4779 | DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); |
619c5cb6 | 4780 | #ifdef BCM_CNIC |
37ae41a9 | 4781 | if (cid == BNX2X_FCOE_ETH_CID(bp)) |
15192a8c | 4782 | return &bnx2x_fcoe_sp_obj(bp, q_obj); |
619c5cb6 VZ |
4783 | else |
4784 | #endif | |
15192a8c | 4785 | return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; |
619c5cb6 VZ |
4786 | } |
4787 | ||
523224a3 DK |
4788 | static void bnx2x_eq_int(struct bnx2x *bp) |
4789 | { | |
4790 | u16 hw_cons, sw_cons, sw_prod; | |
4791 | union event_ring_elem *elem; | |
4792 | u32 cid; | |
4793 | u8 opcode; | |
4794 | int spqe_cnt = 0; | |
619c5cb6 VZ |
4795 | struct bnx2x_queue_sp_obj *q_obj; |
4796 | struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; | |
4797 | struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; | |
523224a3 DK |
4798 | |
4799 | hw_cons = le16_to_cpu(*bp->eq_cons_sb); | |
4800 | ||
4801 | /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. | |
4802 | * when we get the the next-page we nned to adjust so the loop | |
4803 | * condition below will be met. The next element is the size of a | |
4804 | * regular element and hence incrementing by 1 | |
4805 | */ | |
4806 | if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) | |
4807 | hw_cons++; | |
4808 | ||
25985edc | 4809 | /* This function may never run in parallel with itself for a |
523224a3 DK |
4810 | * specific bp, thus there is no need in "paired" read memory |
4811 | * barrier here. | |
4812 | */ | |
4813 | sw_cons = bp->eq_cons; | |
4814 | sw_prod = bp->eq_prod; | |
4815 | ||
d6cae238 | 4816 | DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", |
6e30dd4e | 4817 | hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); |
523224a3 DK |
4818 | |
4819 | for (; sw_cons != hw_cons; | |
4820 | sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { | |
4821 | ||
4822 | ||
4823 | elem = &bp->eq_ring[EQ_DESC(sw_cons)]; | |
4824 | ||
4825 | cid = SW_CID(elem->message.data.cfc_del_event.cid); | |
4826 | opcode = elem->message.opcode; | |
4827 | ||
4828 | ||
4829 | /* handle eq element */ | |
4830 | switch (opcode) { | |
4831 | case EVENT_RING_OPCODE_STAT_QUERY: | |
51c1a580 MS |
4832 | DP(BNX2X_MSG_SP | BNX2X_MSG_STATS, |
4833 | "got statistics comp event %d\n", | |
619c5cb6 | 4834 | bp->stats_comp++); |
523224a3 | 4835 | /* nothing to do with stats comp */ |
d6cae238 | 4836 | goto next_spqe; |
523224a3 DK |
4837 | |
4838 | case EVENT_RING_OPCODE_CFC_DEL: | |
4839 | /* handle according to cid range */ | |
4840 | /* | |
4841 | * we may want to verify here that the bp state is | |
4842 | * HALTING | |
4843 | */ | |
d6cae238 | 4844 | DP(BNX2X_MSG_SP, |
523224a3 DK |
4845 | "got delete ramrod for MULTI[%d]\n", cid); |
4846 | #ifdef BCM_CNIC | |
4847 | if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) | |
4848 | goto next_spqe; | |
4849 | #endif | |
619c5cb6 VZ |
4850 | q_obj = bnx2x_cid_to_q_obj(bp, cid); |
4851 | ||
4852 | if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) | |
4853 | break; | |
4854 | ||
4855 | ||
523224a3 DK |
4856 | |
4857 | goto next_spqe; | |
e4901dde VZ |
4858 | |
4859 | case EVENT_RING_OPCODE_STOP_TRAFFIC: | |
51c1a580 | 4860 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); |
6debea87 DK |
4861 | if (f_obj->complete_cmd(bp, f_obj, |
4862 | BNX2X_F_CMD_TX_STOP)) | |
4863 | break; | |
e4901dde VZ |
4864 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); |
4865 | goto next_spqe; | |
619c5cb6 | 4866 | |
e4901dde | 4867 | case EVENT_RING_OPCODE_START_TRAFFIC: |
51c1a580 | 4868 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); |
6debea87 DK |
4869 | if (f_obj->complete_cmd(bp, f_obj, |
4870 | BNX2X_F_CMD_TX_START)) | |
4871 | break; | |
e4901dde VZ |
4872 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); |
4873 | goto next_spqe; | |
a3348722 BW |
4874 | case EVENT_RING_OPCODE_FUNCTION_UPDATE: |
4875 | DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, | |
4876 | "AFEX: ramrod completed FUNCTION_UPDATE\n"); | |
4877 | f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_AFEX_UPDATE); | |
4878 | ||
4879 | /* We will perform the Queues update from sp_rtnl task | |
4880 | * as all Queue SP operations should run under | |
4881 | * rtnl_lock. | |
4882 | */ | |
4883 | smp_mb__before_clear_bit(); | |
4884 | set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, | |
4885 | &bp->sp_rtnl_state); | |
4886 | smp_mb__after_clear_bit(); | |
4887 | ||
4888 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
4889 | goto next_spqe; | |
4890 | ||
4891 | case EVENT_RING_OPCODE_AFEX_VIF_LISTS: | |
4892 | f_obj->complete_cmd(bp, f_obj, | |
4893 | BNX2X_F_CMD_AFEX_VIFLISTS); | |
4894 | bnx2x_after_afex_vif_lists(bp, elem); | |
4895 | goto next_spqe; | |
619c5cb6 | 4896 | case EVENT_RING_OPCODE_FUNCTION_START: |
51c1a580 MS |
4897 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
4898 | "got FUNC_START ramrod\n"); | |
619c5cb6 VZ |
4899 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) |
4900 | break; | |
4901 | ||
4902 | goto next_spqe; | |
4903 | ||
4904 | case EVENT_RING_OPCODE_FUNCTION_STOP: | |
51c1a580 MS |
4905 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
4906 | "got FUNC_STOP ramrod\n"); | |
619c5cb6 VZ |
4907 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) |
4908 | break; | |
4909 | ||
4910 | goto next_spqe; | |
523224a3 DK |
4911 | } |
4912 | ||
4913 | switch (opcode | bp->state) { | |
619c5cb6 VZ |
4914 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
4915 | BNX2X_STATE_OPEN): | |
4916 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | | |
523224a3 | 4917 | BNX2X_STATE_OPENING_WAIT4_PORT): |
619c5cb6 VZ |
4918 | cid = elem->message.data.eth_event.echo & |
4919 | BNX2X_SWCID_MASK; | |
d6cae238 | 4920 | DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", |
619c5cb6 VZ |
4921 | cid); |
4922 | rss_raw->clear_pending(rss_raw); | |
523224a3 DK |
4923 | break; |
4924 | ||
619c5cb6 VZ |
4925 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): |
4926 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): | |
4927 | case (EVENT_RING_OPCODE_SET_MAC | | |
523224a3 | 4928 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
619c5cb6 VZ |
4929 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
4930 | BNX2X_STATE_OPEN): | |
4931 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
4932 | BNX2X_STATE_DIAG): | |
4933 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
4934 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 4935 | DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); |
619c5cb6 | 4936 | bnx2x_handle_classification_eqe(bp, elem); |
523224a3 DK |
4937 | break; |
4938 | ||
619c5cb6 VZ |
4939 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
4940 | BNX2X_STATE_OPEN): | |
4941 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
4942 | BNX2X_STATE_DIAG): | |
4943 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
4944 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 4945 | DP(BNX2X_MSG_SP, "got mcast ramrod\n"); |
619c5cb6 | 4946 | bnx2x_handle_mcast_eqe(bp); |
523224a3 DK |
4947 | break; |
4948 | ||
619c5cb6 VZ |
4949 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
4950 | BNX2X_STATE_OPEN): | |
4951 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
4952 | BNX2X_STATE_DIAG): | |
4953 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
523224a3 | 4954 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
d6cae238 | 4955 | DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); |
619c5cb6 | 4956 | bnx2x_handle_rx_mode_eqe(bp); |
523224a3 DK |
4957 | break; |
4958 | default: | |
4959 | /* unknown event log error and continue */ | |
619c5cb6 VZ |
4960 | BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", |
4961 | elem->message.opcode, bp->state); | |
523224a3 DK |
4962 | } |
4963 | next_spqe: | |
4964 | spqe_cnt++; | |
4965 | } /* for */ | |
4966 | ||
8fe23fbd | 4967 | smp_mb__before_atomic_inc(); |
6e30dd4e | 4968 | atomic_add(spqe_cnt, &bp->eq_spq_left); |
523224a3 DK |
4969 | |
4970 | bp->eq_cons = sw_cons; | |
4971 | bp->eq_prod = sw_prod; | |
4972 | /* Make sure that above mem writes were issued towards the memory */ | |
4973 | smp_wmb(); | |
4974 | ||
4975 | /* update producer */ | |
4976 | bnx2x_update_eq_prod(bp, bp->eq_prod); | |
4977 | } | |
4978 | ||
a2fbb9ea ET |
4979 | static void bnx2x_sp_task(struct work_struct *work) |
4980 | { | |
1cf167f2 | 4981 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); |
a2fbb9ea ET |
4982 | u16 status; |
4983 | ||
a2fbb9ea | 4984 | status = bnx2x_update_dsb_idx(bp); |
34f80b04 EG |
4985 | /* if (status == 0) */ |
4986 | /* BNX2X_ERR("spurious slowpath interrupt!\n"); */ | |
a2fbb9ea | 4987 | |
51c1a580 | 4988 | DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status); |
a2fbb9ea | 4989 | |
877e9aa4 | 4990 | /* HW attentions */ |
523224a3 | 4991 | if (status & BNX2X_DEF_SB_ATT_IDX) { |
a2fbb9ea | 4992 | bnx2x_attn_int(bp); |
523224a3 | 4993 | status &= ~BNX2X_DEF_SB_ATT_IDX; |
cdaa7cb8 VZ |
4994 | } |
4995 | ||
523224a3 DK |
4996 | /* SP events: STAT_QUERY and others */ |
4997 | if (status & BNX2X_DEF_SB_IDX) { | |
ec6ba945 VZ |
4998 | #ifdef BCM_CNIC |
4999 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
523224a3 | 5000 | |
ec6ba945 | 5001 | if ((!NO_FCOE(bp)) && |
019dbb4c VZ |
5002 | (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { |
5003 | /* | |
5004 | * Prevent local bottom-halves from running as | |
5005 | * we are going to change the local NAPI list. | |
5006 | */ | |
5007 | local_bh_disable(); | |
ec6ba945 | 5008 | napi_schedule(&bnx2x_fcoe(bp, napi)); |
019dbb4c VZ |
5009 | local_bh_enable(); |
5010 | } | |
ec6ba945 | 5011 | #endif |
523224a3 DK |
5012 | /* Handle EQ completions */ |
5013 | bnx2x_eq_int(bp); | |
5014 | ||
5015 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, | |
5016 | le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); | |
5017 | ||
5018 | status &= ~BNX2X_DEF_SB_IDX; | |
cdaa7cb8 VZ |
5019 | } |
5020 | ||
5021 | if (unlikely(status)) | |
51c1a580 | 5022 | DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n", |
cdaa7cb8 | 5023 | status); |
a2fbb9ea | 5024 | |
523224a3 DK |
5025 | bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, |
5026 | le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); | |
a3348722 BW |
5027 | |
5028 | /* afex - poll to check if VIFSET_ACK should be sent to MFW */ | |
5029 | if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, | |
5030 | &bp->sp_state)) { | |
5031 | bnx2x_link_report(bp); | |
5032 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
5033 | } | |
a2fbb9ea ET |
5034 | } |
5035 | ||
9f6c9258 | 5036 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
a2fbb9ea ET |
5037 | { |
5038 | struct net_device *dev = dev_instance; | |
5039 | struct bnx2x *bp = netdev_priv(dev); | |
5040 | ||
523224a3 DK |
5041 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, |
5042 | IGU_INT_DISABLE, 0); | |
a2fbb9ea ET |
5043 | |
5044 | #ifdef BNX2X_STOP_ON_ERROR | |
5045 | if (unlikely(bp->panic)) | |
5046 | return IRQ_HANDLED; | |
5047 | #endif | |
5048 | ||
993ac7b5 MC |
5049 | #ifdef BCM_CNIC |
5050 | { | |
5051 | struct cnic_ops *c_ops; | |
5052 | ||
5053 | rcu_read_lock(); | |
5054 | c_ops = rcu_dereference(bp->cnic_ops); | |
5055 | if (c_ops) | |
5056 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
5057 | rcu_read_unlock(); | |
5058 | } | |
5059 | #endif | |
1cf167f2 | 5060 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
a2fbb9ea ET |
5061 | |
5062 | return IRQ_HANDLED; | |
5063 | } | |
5064 | ||
5065 | /* end of slow path */ | |
5066 | ||
619c5cb6 VZ |
5067 | |
5068 | void bnx2x_drv_pulse(struct bnx2x *bp) | |
5069 | { | |
5070 | SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, | |
5071 | bp->fw_drv_pulse_wr_seq); | |
5072 | } | |
5073 | ||
5074 | ||
a2fbb9ea ET |
5075 | static void bnx2x_timer(unsigned long data) |
5076 | { | |
5077 | struct bnx2x *bp = (struct bnx2x *) data; | |
5078 | ||
5079 | if (!netif_running(bp->dev)) | |
5080 | return; | |
5081 | ||
34f80b04 | 5082 | if (!BP_NOMCP(bp)) { |
f2e0899f | 5083 | int mb_idx = BP_FW_MB_IDX(bp); |
a2fbb9ea ET |
5084 | u32 drv_pulse; |
5085 | u32 mcp_pulse; | |
5086 | ||
5087 | ++bp->fw_drv_pulse_wr_seq; | |
5088 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; | |
5089 | /* TBD - add SYSTEM_TIME */ | |
5090 | drv_pulse = bp->fw_drv_pulse_wr_seq; | |
619c5cb6 | 5091 | bnx2x_drv_pulse(bp); |
a2fbb9ea | 5092 | |
f2e0899f | 5093 | mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & |
a2fbb9ea ET |
5094 | MCP_PULSE_SEQ_MASK); |
5095 | /* The delta between driver pulse and mcp response | |
5096 | * should be 1 (before mcp response) or 0 (after mcp response) | |
5097 | */ | |
5098 | if ((drv_pulse != mcp_pulse) && | |
5099 | (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { | |
5100 | /* someone lost a heartbeat... */ | |
5101 | BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", | |
5102 | drv_pulse, mcp_pulse); | |
5103 | } | |
5104 | } | |
5105 | ||
f34d28ea | 5106 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a | 5107 | bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); |
a2fbb9ea | 5108 | |
a2fbb9ea ET |
5109 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
5110 | } | |
5111 | ||
5112 | /* end of Statistics */ | |
5113 | ||
5114 | /* nic init */ | |
5115 | ||
5116 | /* | |
5117 | * nic init service functions | |
5118 | */ | |
5119 | ||
1191cb83 | 5120 | static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
a2fbb9ea | 5121 | { |
523224a3 DK |
5122 | u32 i; |
5123 | if (!(len%4) && !(addr%4)) | |
5124 | for (i = 0; i < len; i += 4) | |
5125 | REG_WR(bp, addr + i, fill); | |
5126 | else | |
5127 | for (i = 0; i < len; i++) | |
5128 | REG_WR8(bp, addr + i, fill); | |
34f80b04 | 5129 | |
34f80b04 EG |
5130 | } |
5131 | ||
523224a3 | 5132 | /* helper: writes FP SP data to FW - data_size in dwords */ |
1191cb83 ED |
5133 | static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, |
5134 | int fw_sb_id, | |
5135 | u32 *sb_data_p, | |
5136 | u32 data_size) | |
34f80b04 | 5137 | { |
a2fbb9ea | 5138 | int index; |
523224a3 DK |
5139 | for (index = 0; index < data_size; index++) |
5140 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5141 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + | |
5142 | sizeof(u32)*index, | |
5143 | *(sb_data_p + index)); | |
5144 | } | |
a2fbb9ea | 5145 | |
1191cb83 | 5146 | static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) |
523224a3 DK |
5147 | { |
5148 | u32 *sb_data_p; | |
5149 | u32 data_size = 0; | |
f2e0899f | 5150 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 | 5151 | struct hc_status_block_data_e1x sb_data_e1x; |
a2fbb9ea | 5152 | |
523224a3 | 5153 | /* disable the function first */ |
619c5cb6 | 5154 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5155 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5156 | sb_data_e2.common.state = SB_DISABLED; |
f2e0899f DK |
5157 | sb_data_e2.common.p_func.vf_valid = false; |
5158 | sb_data_p = (u32 *)&sb_data_e2; | |
5159 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
5160 | } else { | |
5161 | memset(&sb_data_e1x, 0, | |
5162 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5163 | sb_data_e1x.common.state = SB_DISABLED; |
f2e0899f DK |
5164 | sb_data_e1x.common.p_func.vf_valid = false; |
5165 | sb_data_p = (u32 *)&sb_data_e1x; | |
5166 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
5167 | } | |
523224a3 | 5168 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
a2fbb9ea | 5169 | |
523224a3 DK |
5170 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
5171 | CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, | |
5172 | CSTORM_STATUS_BLOCK_SIZE); | |
5173 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5174 | CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, | |
5175 | CSTORM_SYNC_BLOCK_SIZE); | |
5176 | } | |
34f80b04 | 5177 | |
523224a3 | 5178 | /* helper: writes SP SB data to FW */ |
1191cb83 | 5179 | static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, |
523224a3 DK |
5180 | struct hc_sp_status_block_data *sp_sb_data) |
5181 | { | |
5182 | int func = BP_FUNC(bp); | |
5183 | int i; | |
5184 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
5185 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5186 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
5187 | i*sizeof(u32), | |
5188 | *((u32 *)sp_sb_data + i)); | |
34f80b04 EG |
5189 | } |
5190 | ||
1191cb83 | 5191 | static void bnx2x_zero_sp_sb(struct bnx2x *bp) |
34f80b04 EG |
5192 | { |
5193 | int func = BP_FUNC(bp); | |
523224a3 DK |
5194 | struct hc_sp_status_block_data sp_sb_data; |
5195 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
a2fbb9ea | 5196 | |
619c5cb6 | 5197 | sp_sb_data.state = SB_DISABLED; |
523224a3 DK |
5198 | sp_sb_data.p_func.vf_valid = false; |
5199 | ||
5200 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); | |
5201 | ||
5202 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5203 | CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, | |
5204 | CSTORM_SP_STATUS_BLOCK_SIZE); | |
5205 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5206 | CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, | |
5207 | CSTORM_SP_SYNC_BLOCK_SIZE); | |
5208 | ||
5209 | } | |
5210 | ||
5211 | ||
1191cb83 | 5212 | static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, |
523224a3 DK |
5213 | int igu_sb_id, int igu_seg_id) |
5214 | { | |
5215 | hc_sm->igu_sb_id = igu_sb_id; | |
5216 | hc_sm->igu_seg_id = igu_seg_id; | |
5217 | hc_sm->timer_value = 0xFF; | |
5218 | hc_sm->time_to_expire = 0xFFFFFFFF; | |
a2fbb9ea ET |
5219 | } |
5220 | ||
150966ad AE |
5221 | |
5222 | /* allocates state machine ids. */ | |
1191cb83 | 5223 | static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) |
150966ad AE |
5224 | { |
5225 | /* zero out state machine indices */ | |
5226 | /* rx indices */ | |
5227 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5228 | ||
5229 | /* tx indices */ | |
5230 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5231 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; | |
5232 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; | |
5233 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; | |
5234 | ||
5235 | /* map indices */ | |
5236 | /* rx indices */ | |
5237 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= | |
5238 | SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5239 | ||
5240 | /* tx indices */ | |
5241 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= | |
5242 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5243 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= | |
5244 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5245 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= | |
5246 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5247 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= | |
5248 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5249 | } | |
5250 | ||
8d96286a | 5251 | static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
523224a3 | 5252 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
a2fbb9ea | 5253 | { |
523224a3 DK |
5254 | int igu_seg_id; |
5255 | ||
f2e0899f | 5256 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
5257 | struct hc_status_block_data_e1x sb_data_e1x; |
5258 | struct hc_status_block_sm *hc_sm_p; | |
523224a3 DK |
5259 | int data_size; |
5260 | u32 *sb_data_p; | |
5261 | ||
f2e0899f DK |
5262 | if (CHIP_INT_MODE_IS_BC(bp)) |
5263 | igu_seg_id = HC_SEG_ACCESS_NORM; | |
5264 | else | |
5265 | igu_seg_id = IGU_SEG_ACCESS_NORM; | |
523224a3 DK |
5266 | |
5267 | bnx2x_zero_fp_sb(bp, fw_sb_id); | |
5268 | ||
619c5cb6 | 5269 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5270 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5271 | sb_data_e2.common.state = SB_ENABLED; |
f2e0899f DK |
5272 | sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); |
5273 | sb_data_e2.common.p_func.vf_id = vfid; | |
5274 | sb_data_e2.common.p_func.vf_valid = vf_valid; | |
5275 | sb_data_e2.common.p_func.vnic_id = BP_VN(bp); | |
5276 | sb_data_e2.common.same_igu_sb_1b = true; | |
5277 | sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); | |
5278 | sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); | |
5279 | hc_sm_p = sb_data_e2.common.state_machine; | |
f2e0899f DK |
5280 | sb_data_p = (u32 *)&sb_data_e2; |
5281 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
150966ad | 5282 | bnx2x_map_sb_state_machines(sb_data_e2.index_data); |
f2e0899f DK |
5283 | } else { |
5284 | memset(&sb_data_e1x, 0, | |
5285 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5286 | sb_data_e1x.common.state = SB_ENABLED; |
f2e0899f DK |
5287 | sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); |
5288 | sb_data_e1x.common.p_func.vf_id = 0xff; | |
5289 | sb_data_e1x.common.p_func.vf_valid = false; | |
5290 | sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); | |
5291 | sb_data_e1x.common.same_igu_sb_1b = true; | |
5292 | sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); | |
5293 | sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); | |
5294 | hc_sm_p = sb_data_e1x.common.state_machine; | |
f2e0899f DK |
5295 | sb_data_p = (u32 *)&sb_data_e1x; |
5296 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
150966ad | 5297 | bnx2x_map_sb_state_machines(sb_data_e1x.index_data); |
f2e0899f | 5298 | } |
523224a3 DK |
5299 | |
5300 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], | |
5301 | igu_sb_id, igu_seg_id); | |
5302 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], | |
5303 | igu_sb_id, igu_seg_id); | |
5304 | ||
51c1a580 | 5305 | DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); |
523224a3 DK |
5306 | |
5307 | /* write indecies to HW */ | |
5308 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); | |
5309 | } | |
5310 | ||
619c5cb6 | 5311 | static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, |
523224a3 DK |
5312 | u16 tx_usec, u16 rx_usec) |
5313 | { | |
6383c0b3 | 5314 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, |
523224a3 | 5315 | false, rx_usec); |
6383c0b3 AE |
5316 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
5317 | HC_INDEX_ETH_TX_CQ_CONS_COS0, false, | |
5318 | tx_usec); | |
5319 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5320 | HC_INDEX_ETH_TX_CQ_CONS_COS1, false, | |
5321 | tx_usec); | |
5322 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5323 | HC_INDEX_ETH_TX_CQ_CONS_COS2, false, | |
5324 | tx_usec); | |
523224a3 | 5325 | } |
f2e0899f | 5326 | |
523224a3 DK |
5327 | static void bnx2x_init_def_sb(struct bnx2x *bp) |
5328 | { | |
5329 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
5330 | dma_addr_t mapping = bp->def_status_blk_mapping; | |
5331 | int igu_sp_sb_index; | |
5332 | int igu_seg_id; | |
34f80b04 EG |
5333 | int port = BP_PORT(bp); |
5334 | int func = BP_FUNC(bp); | |
f2eaeb58 | 5335 | int reg_offset, reg_offset_en5; |
a2fbb9ea | 5336 | u64 section; |
523224a3 DK |
5337 | int index; |
5338 | struct hc_sp_status_block_data sp_sb_data; | |
5339 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
5340 | ||
f2e0899f DK |
5341 | if (CHIP_INT_MODE_IS_BC(bp)) { |
5342 | igu_sp_sb_index = DEF_SB_IGU_ID; | |
5343 | igu_seg_id = HC_SEG_ACCESS_DEF; | |
5344 | } else { | |
5345 | igu_sp_sb_index = bp->igu_dsb_id; | |
5346 | igu_seg_id = IGU_SEG_ACCESS_DEF; | |
5347 | } | |
a2fbb9ea ET |
5348 | |
5349 | /* ATTN */ | |
523224a3 | 5350 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
a2fbb9ea | 5351 | atten_status_block); |
523224a3 | 5352 | def_sb->atten_status_block.status_block_id = igu_sp_sb_index; |
a2fbb9ea | 5353 | |
49d66772 ET |
5354 | bp->attn_state = 0; |
5355 | ||
a2fbb9ea ET |
5356 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
5357 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
f2eaeb58 DK |
5358 | reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : |
5359 | MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); | |
34f80b04 | 5360 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
523224a3 DK |
5361 | int sindex; |
5362 | /* take care of sig[0]..sig[4] */ | |
5363 | for (sindex = 0; sindex < 4; sindex++) | |
5364 | bp->attn_group[index].sig[sindex] = | |
5365 | REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); | |
f2e0899f | 5366 | |
619c5cb6 | 5367 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5368 | /* |
5369 | * enable5 is separate from the rest of the registers, | |
5370 | * and therefore the address skip is 4 | |
5371 | * and not 16 between the different groups | |
5372 | */ | |
5373 | bp->attn_group[index].sig[4] = REG_RD(bp, | |
f2eaeb58 | 5374 | reg_offset_en5 + 0x4*index); |
f2e0899f DK |
5375 | else |
5376 | bp->attn_group[index].sig[4] = 0; | |
a2fbb9ea ET |
5377 | } |
5378 | ||
f2e0899f DK |
5379 | if (bp->common.int_block == INT_BLOCK_HC) { |
5380 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : | |
5381 | HC_REG_ATTN_MSG0_ADDR_L); | |
5382 | ||
5383 | REG_WR(bp, reg_offset, U64_LO(section)); | |
5384 | REG_WR(bp, reg_offset + 4, U64_HI(section)); | |
619c5cb6 | 5385 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5386 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); |
5387 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); | |
5388 | } | |
a2fbb9ea | 5389 | |
523224a3 DK |
5390 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
5391 | sp_sb); | |
a2fbb9ea | 5392 | |
523224a3 | 5393 | bnx2x_zero_sp_sb(bp); |
a2fbb9ea | 5394 | |
619c5cb6 | 5395 | sp_sb_data.state = SB_ENABLED; |
523224a3 DK |
5396 | sp_sb_data.host_sb_addr.lo = U64_LO(section); |
5397 | sp_sb_data.host_sb_addr.hi = U64_HI(section); | |
5398 | sp_sb_data.igu_sb_id = igu_sp_sb_index; | |
5399 | sp_sb_data.igu_seg_id = igu_seg_id; | |
5400 | sp_sb_data.p_func.pf_id = func; | |
f2e0899f | 5401 | sp_sb_data.p_func.vnic_id = BP_VN(bp); |
523224a3 | 5402 | sp_sb_data.p_func.vf_id = 0xff; |
a2fbb9ea | 5403 | |
523224a3 | 5404 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
49d66772 | 5405 | |
523224a3 | 5406 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); |
a2fbb9ea ET |
5407 | } |
5408 | ||
9f6c9258 | 5409 | void bnx2x_update_coalesce(struct bnx2x *bp) |
a2fbb9ea | 5410 | { |
a2fbb9ea ET |
5411 | int i; |
5412 | ||
ec6ba945 | 5413 | for_each_eth_queue(bp, i) |
523224a3 | 5414 | bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, |
423cfa7e | 5415 | bp->tx_ticks, bp->rx_ticks); |
a2fbb9ea ET |
5416 | } |
5417 | ||
a2fbb9ea ET |
5418 | static void bnx2x_init_sp_ring(struct bnx2x *bp) |
5419 | { | |
a2fbb9ea | 5420 | spin_lock_init(&bp->spq_lock); |
6e30dd4e | 5421 | atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); |
a2fbb9ea | 5422 | |
a2fbb9ea | 5423 | bp->spq_prod_idx = 0; |
a2fbb9ea ET |
5424 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
5425 | bp->spq_prod_bd = bp->spq; | |
5426 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; | |
a2fbb9ea ET |
5427 | } |
5428 | ||
523224a3 | 5429 | static void bnx2x_init_eq_ring(struct bnx2x *bp) |
a2fbb9ea ET |
5430 | { |
5431 | int i; | |
523224a3 DK |
5432 | for (i = 1; i <= NUM_EQ_PAGES; i++) { |
5433 | union event_ring_elem *elem = | |
5434 | &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; | |
a2fbb9ea | 5435 | |
523224a3 DK |
5436 | elem->next_page.addr.hi = |
5437 | cpu_to_le32(U64_HI(bp->eq_mapping + | |
5438 | BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); | |
5439 | elem->next_page.addr.lo = | |
5440 | cpu_to_le32(U64_LO(bp->eq_mapping + | |
5441 | BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); | |
a2fbb9ea | 5442 | } |
523224a3 DK |
5443 | bp->eq_cons = 0; |
5444 | bp->eq_prod = NUM_EQ_DESC; | |
5445 | bp->eq_cons_sb = BNX2X_EQ_INDEX; | |
6e30dd4e VZ |
5446 | /* we want a warning message before it gets rought... */ |
5447 | atomic_set(&bp->eq_spq_left, | |
5448 | min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); | |
a2fbb9ea ET |
5449 | } |
5450 | ||
619c5cb6 VZ |
5451 | |
5452 | /* called with netif_addr_lock_bh() */ | |
5453 | void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, | |
5454 | unsigned long rx_mode_flags, | |
5455 | unsigned long rx_accept_flags, | |
5456 | unsigned long tx_accept_flags, | |
5457 | unsigned long ramrod_flags) | |
ab532cf3 | 5458 | { |
619c5cb6 VZ |
5459 | struct bnx2x_rx_mode_ramrod_params ramrod_param; |
5460 | int rc; | |
5461 | ||
5462 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
5463 | ||
5464 | /* Prepare ramrod parameters */ | |
5465 | ramrod_param.cid = 0; | |
5466 | ramrod_param.cl_id = cl_id; | |
5467 | ramrod_param.rx_mode_obj = &bp->rx_mode_obj; | |
5468 | ramrod_param.func_id = BP_FUNC(bp); | |
ab532cf3 | 5469 | |
619c5cb6 VZ |
5470 | ramrod_param.pstate = &bp->sp_state; |
5471 | ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; | |
ab532cf3 | 5472 | |
619c5cb6 VZ |
5473 | ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); |
5474 | ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); | |
5475 | ||
5476 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
5477 | ||
5478 | ramrod_param.ramrod_flags = ramrod_flags; | |
5479 | ramrod_param.rx_mode_flags = rx_mode_flags; | |
5480 | ||
5481 | ramrod_param.rx_accept_flags = rx_accept_flags; | |
5482 | ramrod_param.tx_accept_flags = tx_accept_flags; | |
5483 | ||
5484 | rc = bnx2x_config_rx_mode(bp, &ramrod_param); | |
5485 | if (rc < 0) { | |
5486 | BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); | |
5487 | return; | |
5488 | } | |
a2fbb9ea ET |
5489 | } |
5490 | ||
619c5cb6 VZ |
5491 | /* called with netif_addr_lock_bh() */ |
5492 | void bnx2x_set_storm_rx_mode(struct bnx2x *bp) | |
471de716 | 5493 | { |
619c5cb6 VZ |
5494 | unsigned long rx_mode_flags = 0, ramrod_flags = 0; |
5495 | unsigned long rx_accept_flags = 0, tx_accept_flags = 0; | |
471de716 | 5496 | |
619c5cb6 VZ |
5497 | #ifdef BCM_CNIC |
5498 | if (!NO_FCOE(bp)) | |
5499 | ||
5500 | /* Configure rx_mode of FCoE Queue */ | |
5501 | __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); | |
5502 | #endif | |
5503 | ||
5504 | switch (bp->rx_mode) { | |
5505 | case BNX2X_RX_MODE_NONE: | |
5506 | /* | |
5507 | * 'drop all' supersedes any accept flags that may have been | |
5508 | * passed to the function. | |
5509 | */ | |
5510 | break; | |
5511 | case BNX2X_RX_MODE_NORMAL: | |
5512 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5513 | __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); | |
5514 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5515 | ||
5516 | /* internal switching mode */ | |
5517 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5518 | __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); | |
5519 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5520 | ||
5521 | break; | |
5522 | case BNX2X_RX_MODE_ALLMULTI: | |
5523 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5524 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5525 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5526 | ||
5527 | /* internal switching mode */ | |
5528 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5529 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5530 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5531 | ||
5532 | break; | |
5533 | case BNX2X_RX_MODE_PROMISC: | |
5534 | /* According to deffinition of SI mode, iface in promisc mode | |
5535 | * should receive matched and unmatched (in resolution of port) | |
5536 | * unicast packets. | |
5537 | */ | |
5538 | __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); | |
5539 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5540 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5541 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5542 | ||
5543 | /* internal switching mode */ | |
5544 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5545 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5546 | ||
5547 | if (IS_MF_SI(bp)) | |
5548 | __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); | |
5549 | else | |
5550 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5551 | ||
5552 | break; | |
5553 | default: | |
5554 | BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); | |
5555 | return; | |
5556 | } | |
de832a55 | 5557 | |
619c5cb6 VZ |
5558 | if (bp->rx_mode != BNX2X_RX_MODE_NONE) { |
5559 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); | |
5560 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); | |
34f80b04 EG |
5561 | } |
5562 | ||
619c5cb6 VZ |
5563 | __set_bit(RAMROD_RX, &ramrod_flags); |
5564 | __set_bit(RAMROD_TX, &ramrod_flags); | |
5565 | ||
5566 | bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, | |
5567 | tx_accept_flags, ramrod_flags); | |
5568 | } | |
5569 | ||
5570 | static void bnx2x_init_internal_common(struct bnx2x *bp) | |
5571 | { | |
5572 | int i; | |
5573 | ||
0793f83f DK |
5574 | if (IS_MF_SI(bp)) |
5575 | /* | |
5576 | * In switch independent mode, the TSTORM needs to accept | |
5577 | * packets that failed classification, since approximate match | |
5578 | * mac addresses aren't written to NIG LLH | |
5579 | */ | |
5580 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5581 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); | |
619c5cb6 VZ |
5582 | else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ |
5583 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5584 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); | |
0793f83f | 5585 | |
523224a3 DK |
5586 | /* Zero this manually as its initialization is |
5587 | currently missing in the initTool */ | |
5588 | for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) | |
ca00392c | 5589 | REG_WR(bp, BAR_USTRORM_INTMEM + |
523224a3 | 5590 | USTORM_AGG_DATA_OFFSET + i * 4, 0); |
619c5cb6 | 5591 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5592 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, |
5593 | CHIP_INT_MODE_IS_BC(bp) ? | |
5594 | HC_IGU_BC_MODE : HC_IGU_NBC_MODE); | |
5595 | } | |
523224a3 | 5596 | } |
8a1c38d1 | 5597 | |
471de716 EG |
5598 | static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) |
5599 | { | |
5600 | switch (load_code) { | |
5601 | case FW_MSG_CODE_DRV_LOAD_COMMON: | |
f2e0899f | 5602 | case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: |
471de716 EG |
5603 | bnx2x_init_internal_common(bp); |
5604 | /* no break */ | |
5605 | ||
5606 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
619c5cb6 | 5607 | /* nothing to do */ |
471de716 EG |
5608 | /* no break */ |
5609 | ||
5610 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
523224a3 DK |
5611 | /* internal memory per function is |
5612 | initialized inside bnx2x_pf_init */ | |
471de716 EG |
5613 | break; |
5614 | ||
5615 | default: | |
5616 | BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); | |
5617 | break; | |
5618 | } | |
5619 | } | |
5620 | ||
619c5cb6 | 5621 | static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) |
523224a3 | 5622 | { |
6383c0b3 | 5623 | return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; |
619c5cb6 | 5624 | } |
523224a3 | 5625 | |
619c5cb6 VZ |
5626 | static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) |
5627 | { | |
6383c0b3 | 5628 | return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; |
619c5cb6 VZ |
5629 | } |
5630 | ||
1191cb83 | 5631 | static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) |
619c5cb6 VZ |
5632 | { |
5633 | if (CHIP_IS_E1x(fp->bp)) | |
5634 | return BP_L_ID(fp->bp) + fp->index; | |
5635 | else /* We want Client ID to be the same as IGU SB ID for 57712 */ | |
5636 | return bnx2x_fp_igu_sb_id(fp); | |
5637 | } | |
5638 | ||
6383c0b3 | 5639 | static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) |
619c5cb6 VZ |
5640 | { |
5641 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; | |
6383c0b3 | 5642 | u8 cos; |
619c5cb6 | 5643 | unsigned long q_type = 0; |
6383c0b3 | 5644 | u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; |
f233cafe | 5645 | fp->rx_queue = fp_idx; |
b3b83c3f | 5646 | fp->cid = fp_idx; |
619c5cb6 VZ |
5647 | fp->cl_id = bnx2x_fp_cl_id(fp); |
5648 | fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); | |
5649 | fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); | |
523224a3 | 5650 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 VZ |
5651 | fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); |
5652 | ||
523224a3 | 5653 | /* init shortcut */ |
619c5cb6 | 5654 | fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); |
7a752993 | 5655 | |
523224a3 DK |
5656 | /* Setup SB indicies */ |
5657 | fp->rx_cons_sb = BNX2X_RX_SB_INDEX; | |
523224a3 | 5658 | |
619c5cb6 VZ |
5659 | /* Configure Queue State object */ |
5660 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
5661 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
5662 | |
5663 | BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); | |
5664 | ||
5665 | /* init tx data */ | |
5666 | for_each_cos_in_tx_queue(fp, cos) { | |
65565884 MS |
5667 | bnx2x_init_txdata(bp, fp->txdata_ptr[cos], |
5668 | CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), | |
5669 | FP_COS_TO_TXQ(fp, cos, bp), | |
5670 | BNX2X_TX_SB_INDEX_BASE + cos, fp); | |
5671 | cids[cos] = fp->txdata_ptr[cos]->cid; | |
6383c0b3 AE |
5672 | } |
5673 | ||
15192a8c BW |
5674 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, |
5675 | fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6383c0b3 | 5676 | bnx2x_sp_mapping(bp, q_rdata), q_type); |
619c5cb6 VZ |
5677 | |
5678 | /** | |
5679 | * Configure classification DBs: Always enable Tx switching | |
5680 | */ | |
5681 | bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); | |
5682 | ||
51c1a580 | 5683 | DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", |
619c5cb6 | 5684 | fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, |
523224a3 DK |
5685 | fp->igu_sb_id); |
5686 | bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, | |
5687 | fp->fw_sb_id, fp->igu_sb_id); | |
5688 | ||
5689 | bnx2x_update_fpsb_idx(fp); | |
5690 | } | |
5691 | ||
1191cb83 ED |
5692 | static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) |
5693 | { | |
5694 | int i; | |
5695 | ||
5696 | for (i = 1; i <= NUM_TX_RINGS; i++) { | |
5697 | struct eth_tx_next_bd *tx_next_bd = | |
5698 | &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; | |
5699 | ||
5700 | tx_next_bd->addr_hi = | |
5701 | cpu_to_le32(U64_HI(txdata->tx_desc_mapping + | |
5702 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
5703 | tx_next_bd->addr_lo = | |
5704 | cpu_to_le32(U64_LO(txdata->tx_desc_mapping + | |
5705 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
5706 | } | |
5707 | ||
5708 | SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); | |
5709 | txdata->tx_db.data.zero_fill1 = 0; | |
5710 | txdata->tx_db.data.prod = 0; | |
5711 | ||
5712 | txdata->tx_pkt_prod = 0; | |
5713 | txdata->tx_pkt_cons = 0; | |
5714 | txdata->tx_bd_prod = 0; | |
5715 | txdata->tx_bd_cons = 0; | |
5716 | txdata->tx_pkt = 0; | |
5717 | } | |
5718 | ||
5719 | static void bnx2x_init_tx_rings(struct bnx2x *bp) | |
5720 | { | |
5721 | int i; | |
5722 | u8 cos; | |
5723 | ||
5724 | for_each_tx_queue(bp, i) | |
5725 | for_each_cos_in_tx_queue(&bp->fp[i], cos) | |
65565884 | 5726 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); |
1191cb83 ED |
5727 | } |
5728 | ||
9f6c9258 | 5729 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) |
a2fbb9ea ET |
5730 | { |
5731 | int i; | |
5732 | ||
ec6ba945 | 5733 | for_each_eth_queue(bp, i) |
6383c0b3 | 5734 | bnx2x_init_eth_fp(bp, i); |
37b091ba | 5735 | #ifdef BCM_CNIC |
ec6ba945 VZ |
5736 | if (!NO_FCOE(bp)) |
5737 | bnx2x_init_fcoe_fp(bp); | |
523224a3 DK |
5738 | |
5739 | bnx2x_init_sb(bp, bp->cnic_sb_mapping, | |
5740 | BNX2X_VF_ID_INVALID, false, | |
619c5cb6 | 5741 | bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); |
523224a3 | 5742 | |
37b091ba | 5743 | #endif |
a2fbb9ea | 5744 | |
020c7e3f YR |
5745 | /* Initialize MOD_ABS interrupts */ |
5746 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, | |
5747 | bp->common.shmem_base, bp->common.shmem2_base, | |
5748 | BP_PORT(bp)); | |
16119785 EG |
5749 | /* ensure status block indices were read */ |
5750 | rmb(); | |
5751 | ||
523224a3 | 5752 | bnx2x_init_def_sb(bp); |
5c862848 | 5753 | bnx2x_update_dsb_idx(bp); |
a2fbb9ea | 5754 | bnx2x_init_rx_rings(bp); |
523224a3 | 5755 | bnx2x_init_tx_rings(bp); |
a2fbb9ea | 5756 | bnx2x_init_sp_ring(bp); |
523224a3 | 5757 | bnx2x_init_eq_ring(bp); |
471de716 | 5758 | bnx2x_init_internal(bp, load_code); |
523224a3 | 5759 | bnx2x_pf_init(bp); |
0ef00459 EG |
5760 | bnx2x_stats_init(bp); |
5761 | ||
0ef00459 EG |
5762 | /* flush all before enabling interrupts */ |
5763 | mb(); | |
5764 | mmiowb(); | |
5765 | ||
615f8fd9 | 5766 | bnx2x_int_enable(bp); |
eb8da205 EG |
5767 | |
5768 | /* Check for SPIO5 */ | |
5769 | bnx2x_attn_int_deasserted0(bp, | |
5770 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & | |
5771 | AEU_INPUTS_ATTN_BITS_SPIO5); | |
a2fbb9ea ET |
5772 | } |
5773 | ||
5774 | /* end of nic init */ | |
5775 | ||
5776 | /* | |
5777 | * gzip service functions | |
5778 | */ | |
5779 | ||
5780 | static int bnx2x_gunzip_init(struct bnx2x *bp) | |
5781 | { | |
1a983142 FT |
5782 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
5783 | &bp->gunzip_mapping, GFP_KERNEL); | |
a2fbb9ea ET |
5784 | if (bp->gunzip_buf == NULL) |
5785 | goto gunzip_nomem1; | |
5786 | ||
5787 | bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); | |
5788 | if (bp->strm == NULL) | |
5789 | goto gunzip_nomem2; | |
5790 | ||
7ab24bfd | 5791 | bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); |
a2fbb9ea ET |
5792 | if (bp->strm->workspace == NULL) |
5793 | goto gunzip_nomem3; | |
5794 | ||
5795 | return 0; | |
5796 | ||
5797 | gunzip_nomem3: | |
5798 | kfree(bp->strm); | |
5799 | bp->strm = NULL; | |
5800 | ||
5801 | gunzip_nomem2: | |
1a983142 FT |
5802 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
5803 | bp->gunzip_mapping); | |
a2fbb9ea ET |
5804 | bp->gunzip_buf = NULL; |
5805 | ||
5806 | gunzip_nomem1: | |
51c1a580 | 5807 | BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); |
a2fbb9ea ET |
5808 | return -ENOMEM; |
5809 | } | |
5810 | ||
5811 | static void bnx2x_gunzip_end(struct bnx2x *bp) | |
5812 | { | |
b3b83c3f | 5813 | if (bp->strm) { |
7ab24bfd | 5814 | vfree(bp->strm->workspace); |
b3b83c3f DK |
5815 | kfree(bp->strm); |
5816 | bp->strm = NULL; | |
5817 | } | |
a2fbb9ea ET |
5818 | |
5819 | if (bp->gunzip_buf) { | |
1a983142 FT |
5820 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
5821 | bp->gunzip_mapping); | |
a2fbb9ea ET |
5822 | bp->gunzip_buf = NULL; |
5823 | } | |
5824 | } | |
5825 | ||
94a78b79 | 5826 | static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) |
a2fbb9ea ET |
5827 | { |
5828 | int n, rc; | |
5829 | ||
5830 | /* check gzip header */ | |
94a78b79 VZ |
5831 | if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { |
5832 | BNX2X_ERR("Bad gzip header\n"); | |
a2fbb9ea | 5833 | return -EINVAL; |
94a78b79 | 5834 | } |
a2fbb9ea ET |
5835 | |
5836 | n = 10; | |
5837 | ||
34f80b04 | 5838 | #define FNAME 0x8 |
a2fbb9ea ET |
5839 | |
5840 | if (zbuf[3] & FNAME) | |
5841 | while ((zbuf[n++] != 0) && (n < len)); | |
5842 | ||
94a78b79 | 5843 | bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; |
a2fbb9ea ET |
5844 | bp->strm->avail_in = len - n; |
5845 | bp->strm->next_out = bp->gunzip_buf; | |
5846 | bp->strm->avail_out = FW_BUF_SIZE; | |
5847 | ||
5848 | rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); | |
5849 | if (rc != Z_OK) | |
5850 | return rc; | |
5851 | ||
5852 | rc = zlib_inflate(bp->strm, Z_FINISH); | |
5853 | if ((rc != Z_OK) && (rc != Z_STREAM_END)) | |
7995c64e JP |
5854 | netdev_err(bp->dev, "Firmware decompression error: %s\n", |
5855 | bp->strm->msg); | |
a2fbb9ea ET |
5856 | |
5857 | bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); | |
5858 | if (bp->gunzip_outlen & 0x3) | |
51c1a580 MS |
5859 | netdev_err(bp->dev, |
5860 | "Firmware decompression error: gunzip_outlen (%d) not aligned\n", | |
cdaa7cb8 | 5861 | bp->gunzip_outlen); |
a2fbb9ea ET |
5862 | bp->gunzip_outlen >>= 2; |
5863 | ||
5864 | zlib_inflateEnd(bp->strm); | |
5865 | ||
5866 | if (rc == Z_STREAM_END) | |
5867 | return 0; | |
5868 | ||
5869 | return rc; | |
5870 | } | |
5871 | ||
5872 | /* nic load/unload */ | |
5873 | ||
5874 | /* | |
34f80b04 | 5875 | * General service functions |
a2fbb9ea ET |
5876 | */ |
5877 | ||
5878 | /* send a NIG loopback debug packet */ | |
5879 | static void bnx2x_lb_pckt(struct bnx2x *bp) | |
5880 | { | |
a2fbb9ea | 5881 | u32 wb_write[3]; |
a2fbb9ea ET |
5882 | |
5883 | /* Ethernet source and destination addresses */ | |
a2fbb9ea ET |
5884 | wb_write[0] = 0x55555555; |
5885 | wb_write[1] = 0x55555555; | |
34f80b04 | 5886 | wb_write[2] = 0x20; /* SOP */ |
a2fbb9ea | 5887 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
5888 | |
5889 | /* NON-IP protocol */ | |
a2fbb9ea ET |
5890 | wb_write[0] = 0x09000000; |
5891 | wb_write[1] = 0x55555555; | |
34f80b04 | 5892 | wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ |
a2fbb9ea | 5893 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
5894 | } |
5895 | ||
5896 | /* some of the internal memories | |
5897 | * are not directly readable from the driver | |
5898 | * to test them we send debug packets | |
5899 | */ | |
5900 | static int bnx2x_int_mem_test(struct bnx2x *bp) | |
5901 | { | |
5902 | int factor; | |
5903 | int count, i; | |
5904 | u32 val = 0; | |
5905 | ||
ad8d3948 | 5906 | if (CHIP_REV_IS_FPGA(bp)) |
a2fbb9ea | 5907 | factor = 120; |
ad8d3948 EG |
5908 | else if (CHIP_REV_IS_EMUL(bp)) |
5909 | factor = 200; | |
5910 | else | |
a2fbb9ea | 5911 | factor = 1; |
a2fbb9ea | 5912 | |
a2fbb9ea ET |
5913 | /* Disable inputs of parser neighbor blocks */ |
5914 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
5915 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
5916 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 5917 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
5918 | |
5919 | /* Write 0 to parser credits for CFC search request */ | |
5920 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
5921 | ||
5922 | /* send Ethernet packet */ | |
5923 | bnx2x_lb_pckt(bp); | |
5924 | ||
5925 | /* TODO do i reset NIG statistic? */ | |
5926 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
5927 | count = 1000 * factor; | |
5928 | while (count) { | |
34f80b04 | 5929 | |
a2fbb9ea ET |
5930 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
5931 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
5932 | if (val == 0x10) |
5933 | break; | |
5934 | ||
5935 | msleep(10); | |
5936 | count--; | |
5937 | } | |
5938 | if (val != 0x10) { | |
5939 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
5940 | return -1; | |
5941 | } | |
5942 | ||
5943 | /* Wait until PRS register shows 1 packet */ | |
5944 | count = 1000 * factor; | |
5945 | while (count) { | |
5946 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
a2fbb9ea ET |
5947 | if (val == 1) |
5948 | break; | |
5949 | ||
5950 | msleep(10); | |
5951 | count--; | |
5952 | } | |
5953 | if (val != 0x1) { | |
5954 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5955 | return -2; | |
5956 | } | |
5957 | ||
5958 | /* Reset and init BRB, PRS */ | |
34f80b04 | 5959 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
a2fbb9ea | 5960 | msleep(50); |
34f80b04 | 5961 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
a2fbb9ea | 5962 | msleep(50); |
619c5cb6 VZ |
5963 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
5964 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
a2fbb9ea ET |
5965 | |
5966 | DP(NETIF_MSG_HW, "part2\n"); | |
5967 | ||
5968 | /* Disable inputs of parser neighbor blocks */ | |
5969 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
5970 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
5971 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 5972 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
5973 | |
5974 | /* Write 0 to parser credits for CFC search request */ | |
5975 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
5976 | ||
5977 | /* send 10 Ethernet packets */ | |
5978 | for (i = 0; i < 10; i++) | |
5979 | bnx2x_lb_pckt(bp); | |
5980 | ||
5981 | /* Wait until NIG register shows 10 + 1 | |
5982 | packets of size 11*0x10 = 0xb0 */ | |
5983 | count = 1000 * factor; | |
5984 | while (count) { | |
34f80b04 | 5985 | |
a2fbb9ea ET |
5986 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
5987 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
5988 | if (val == 0xb0) |
5989 | break; | |
5990 | ||
5991 | msleep(10); | |
5992 | count--; | |
5993 | } | |
5994 | if (val != 0xb0) { | |
5995 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
5996 | return -3; | |
5997 | } | |
5998 | ||
5999 | /* Wait until PRS register shows 2 packets */ | |
6000 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6001 | if (val != 2) | |
6002 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6003 | ||
6004 | /* Write 1 to parser credits for CFC search request */ | |
6005 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); | |
6006 | ||
6007 | /* Wait until PRS register shows 3 packets */ | |
6008 | msleep(10 * factor); | |
6009 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6010 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6011 | if (val != 3) | |
6012 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6013 | ||
6014 | /* clear NIG EOP FIFO */ | |
6015 | for (i = 0; i < 11; i++) | |
6016 | REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); | |
6017 | val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); | |
6018 | if (val != 1) { | |
6019 | BNX2X_ERR("clear of NIG failed\n"); | |
6020 | return -4; | |
6021 | } | |
6022 | ||
6023 | /* Reset and init BRB, PRS, NIG */ | |
6024 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); | |
6025 | msleep(50); | |
6026 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); | |
6027 | msleep(50); | |
619c5cb6 VZ |
6028 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6029 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
37b091ba | 6030 | #ifndef BCM_CNIC |
a2fbb9ea ET |
6031 | /* set NIC mode */ |
6032 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
6033 | #endif | |
6034 | ||
6035 | /* Enable inputs of parser neighbor blocks */ | |
6036 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); | |
6037 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); | |
6038 | REG_WR(bp, CFC_REG_DEBUG0, 0x0); | |
3196a88a | 6039 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); |
a2fbb9ea ET |
6040 | |
6041 | DP(NETIF_MSG_HW, "done\n"); | |
6042 | ||
6043 | return 0; /* OK */ | |
6044 | } | |
6045 | ||
4a33bc03 | 6046 | static void bnx2x_enable_blocks_attention(struct bnx2x *bp) |
a2fbb9ea ET |
6047 | { |
6048 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
619c5cb6 | 6049 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6050 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); |
6051 | else | |
6052 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); | |
a2fbb9ea ET |
6053 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
6054 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
f2e0899f DK |
6055 | /* |
6056 | * mask read length error interrupts in brb for parser | |
6057 | * (parsing unit and 'checksum and crc' unit) | |
6058 | * these errors are legal (PU reads fixed length and CAC can cause | |
6059 | * read length error on truncated packets) | |
6060 | */ | |
6061 | REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); | |
a2fbb9ea ET |
6062 | REG_WR(bp, QM_REG_QM_INT_MASK, 0); |
6063 | REG_WR(bp, TM_REG_TM_INT_MASK, 0); | |
6064 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); | |
6065 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); | |
6066 | REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); | |
34f80b04 EG |
6067 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ |
6068 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6069 | REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); |
6070 | REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); | |
6071 | REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); | |
34f80b04 EG |
6072 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ |
6073 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6074 | REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); |
6075 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); | |
6076 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); | |
6077 | REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); | |
34f80b04 EG |
6078 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ |
6079 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ | |
f85582f8 | 6080 | |
34f80b04 EG |
6081 | if (CHIP_REV_IS_FPGA(bp)) |
6082 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); | |
619c5cb6 | 6083 | else if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6084 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, |
6085 | (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | |
6086 | | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | |
6087 | | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN | |
6088 | | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | |
6089 | | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); | |
34f80b04 EG |
6090 | else |
6091 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); | |
a2fbb9ea ET |
6092 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); |
6093 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); | |
6094 | REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); | |
34f80b04 | 6095 | /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ |
619c5cb6 VZ |
6096 | |
6097 | if (!CHIP_IS_E1x(bp)) | |
6098 | /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ | |
6099 | REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); | |
6100 | ||
a2fbb9ea ET |
6101 | REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); |
6102 | REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); | |
34f80b04 | 6103 | /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ |
4a33bc03 | 6104 | REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ |
a2fbb9ea ET |
6105 | } |
6106 | ||
81f75bbf EG |
6107 | static void bnx2x_reset_common(struct bnx2x *bp) |
6108 | { | |
619c5cb6 VZ |
6109 | u32 val = 0x1400; |
6110 | ||
81f75bbf EG |
6111 | /* reset_common */ |
6112 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6113 | 0xd3ffff7f); | |
619c5cb6 VZ |
6114 | |
6115 | if (CHIP_IS_E3(bp)) { | |
6116 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6117 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6118 | } | |
6119 | ||
6120 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); | |
6121 | } | |
6122 | ||
6123 | static void bnx2x_setup_dmae(struct bnx2x *bp) | |
6124 | { | |
6125 | bp->dmae_ready = 0; | |
6126 | spin_lock_init(&bp->dmae_lock); | |
81f75bbf EG |
6127 | } |
6128 | ||
573f2035 EG |
6129 | static void bnx2x_init_pxp(struct bnx2x *bp) |
6130 | { | |
6131 | u16 devctl; | |
6132 | int r_order, w_order; | |
6133 | ||
6134 | pci_read_config_word(bp->pdev, | |
b6c2f86e | 6135 | pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); |
573f2035 EG |
6136 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
6137 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | |
6138 | if (bp->mrrs == -1) | |
6139 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
6140 | else { | |
6141 | DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); | |
6142 | r_order = bp->mrrs; | |
6143 | } | |
6144 | ||
6145 | bnx2x_init_pxp_arb(bp, r_order, w_order); | |
6146 | } | |
fd4ef40d EG |
6147 | |
6148 | static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) | |
6149 | { | |
2145a920 | 6150 | int is_required; |
fd4ef40d | 6151 | u32 val; |
2145a920 | 6152 | int port; |
fd4ef40d | 6153 | |
2145a920 VZ |
6154 | if (BP_NOMCP(bp)) |
6155 | return; | |
6156 | ||
6157 | is_required = 0; | |
fd4ef40d EG |
6158 | val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
6159 | SHARED_HW_CFG_FAN_FAILURE_MASK; | |
6160 | ||
6161 | if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) | |
6162 | is_required = 1; | |
6163 | ||
6164 | /* | |
6165 | * The fan failure mechanism is usually related to the PHY type since | |
6166 | * the power consumption of the board is affected by the PHY. Currently, | |
6167 | * fan is required for most designs with SFX7101, BCM8727 and BCM8481. | |
6168 | */ | |
6169 | else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) | |
6170 | for (port = PORT_0; port < PORT_MAX; port++) { | |
fd4ef40d | 6171 | is_required |= |
d90d96ba YR |
6172 | bnx2x_fan_failure_det_req( |
6173 | bp, | |
6174 | bp->common.shmem_base, | |
a22f0788 | 6175 | bp->common.shmem2_base, |
d90d96ba | 6176 | port); |
fd4ef40d EG |
6177 | } |
6178 | ||
6179 | DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); | |
6180 | ||
6181 | if (is_required == 0) | |
6182 | return; | |
6183 | ||
6184 | /* Fan failure is indicated by SPIO 5 */ | |
6185 | bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, | |
6186 | MISC_REGISTERS_SPIO_INPUT_HI_Z); | |
6187 | ||
6188 | /* set to active low mode */ | |
6189 | val = REG_RD(bp, MISC_REG_SPIO_INT); | |
6190 | val |= ((1 << MISC_REGISTERS_SPIO_5) << | |
cdaa7cb8 | 6191 | MISC_REGISTERS_SPIO_INT_OLD_SET_POS); |
fd4ef40d EG |
6192 | REG_WR(bp, MISC_REG_SPIO_INT, val); |
6193 | ||
6194 | /* enable interrupt to signal the IGU */ | |
6195 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
6196 | val |= (1 << MISC_REGISTERS_SPIO_5); | |
6197 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); | |
6198 | } | |
6199 | ||
f2e0899f DK |
6200 | static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) |
6201 | { | |
6202 | u32 offset = 0; | |
6203 | ||
6204 | if (CHIP_IS_E1(bp)) | |
6205 | return; | |
6206 | if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) | |
6207 | return; | |
6208 | ||
6209 | switch (BP_ABS_FUNC(bp)) { | |
6210 | case 0: | |
6211 | offset = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
6212 | break; | |
6213 | case 1: | |
6214 | offset = PXP2_REG_PGL_PRETEND_FUNC_F1; | |
6215 | break; | |
6216 | case 2: | |
6217 | offset = PXP2_REG_PGL_PRETEND_FUNC_F2; | |
6218 | break; | |
6219 | case 3: | |
6220 | offset = PXP2_REG_PGL_PRETEND_FUNC_F3; | |
6221 | break; | |
6222 | case 4: | |
6223 | offset = PXP2_REG_PGL_PRETEND_FUNC_F4; | |
6224 | break; | |
6225 | case 5: | |
6226 | offset = PXP2_REG_PGL_PRETEND_FUNC_F5; | |
6227 | break; | |
6228 | case 6: | |
6229 | offset = PXP2_REG_PGL_PRETEND_FUNC_F6; | |
6230 | break; | |
6231 | case 7: | |
6232 | offset = PXP2_REG_PGL_PRETEND_FUNC_F7; | |
6233 | break; | |
6234 | default: | |
6235 | return; | |
6236 | } | |
6237 | ||
6238 | REG_WR(bp, offset, pretend_func_num); | |
6239 | REG_RD(bp, offset); | |
6240 | DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); | |
6241 | } | |
6242 | ||
c9ee9206 | 6243 | void bnx2x_pf_disable(struct bnx2x *bp) |
f2e0899f DK |
6244 | { |
6245 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
6246 | val &= ~IGU_PF_CONF_FUNC_EN; | |
6247 | ||
6248 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
6249 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6250 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); | |
6251 | } | |
6252 | ||
1191cb83 | 6253 | static void bnx2x__common_init_phy(struct bnx2x *bp) |
619c5cb6 VZ |
6254 | { |
6255 | u32 shmem_base[2], shmem2_base[2]; | |
6256 | shmem_base[0] = bp->common.shmem_base; | |
6257 | shmem2_base[0] = bp->common.shmem2_base; | |
6258 | if (!CHIP_IS_E1x(bp)) { | |
6259 | shmem_base[1] = | |
6260 | SHMEM2_RD(bp, other_shmem_base_addr); | |
6261 | shmem2_base[1] = | |
6262 | SHMEM2_RD(bp, other_shmem2_base_addr); | |
6263 | } | |
6264 | bnx2x_acquire_phy_lock(bp); | |
6265 | bnx2x_common_init_phy(bp, shmem_base, shmem2_base, | |
6266 | bp->common.chip_id); | |
6267 | bnx2x_release_phy_lock(bp); | |
6268 | } | |
6269 | ||
6270 | /** | |
6271 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. | |
6272 | * | |
6273 | * @bp: driver handle | |
6274 | */ | |
6275 | static int bnx2x_init_hw_common(struct bnx2x *bp) | |
a2fbb9ea | 6276 | { |
619c5cb6 | 6277 | u32 val; |
a2fbb9ea | 6278 | |
51c1a580 | 6279 | DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); |
a2fbb9ea | 6280 | |
2031bd3a DK |
6281 | /* |
6282 | * take the UNDI lock to protect undi_unload flow from accessing | |
6283 | * registers while we're resetting the chip | |
6284 | */ | |
7a06a122 | 6285 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 6286 | |
81f75bbf | 6287 | bnx2x_reset_common(bp); |
34f80b04 | 6288 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
a2fbb9ea | 6289 | |
619c5cb6 VZ |
6290 | val = 0xfffc; |
6291 | if (CHIP_IS_E3(bp)) { | |
6292 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6293 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6294 | } | |
6295 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); | |
6296 | ||
7a06a122 | 6297 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 6298 | |
619c5cb6 | 6299 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); |
a2fbb9ea | 6300 | |
619c5cb6 VZ |
6301 | if (!CHIP_IS_E1x(bp)) { |
6302 | u8 abs_func_id; | |
f2e0899f DK |
6303 | |
6304 | /** | |
6305 | * 4-port mode or 2-port mode we need to turn of master-enable | |
6306 | * for everyone, after that, turn it back on for self. | |
6307 | * so, we disregard multi-function or not, and always disable | |
6308 | * for all functions on the given path, this means 0,2,4,6 for | |
6309 | * path 0 and 1,3,5,7 for path 1 | |
6310 | */ | |
619c5cb6 VZ |
6311 | for (abs_func_id = BP_PATH(bp); |
6312 | abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { | |
6313 | if (abs_func_id == BP_ABS_FUNC(bp)) { | |
f2e0899f DK |
6314 | REG_WR(bp, |
6315 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, | |
6316 | 1); | |
6317 | continue; | |
6318 | } | |
6319 | ||
619c5cb6 | 6320 | bnx2x_pretend_func(bp, abs_func_id); |
f2e0899f DK |
6321 | /* clear pf enable */ |
6322 | bnx2x_pf_disable(bp); | |
6323 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
6324 | } | |
6325 | } | |
a2fbb9ea | 6326 | |
619c5cb6 | 6327 | bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); |
34f80b04 EG |
6328 | if (CHIP_IS_E1(bp)) { |
6329 | /* enable HW interrupt from PXP on USDM overflow | |
6330 | bit 16 on INT_MASK_0 */ | |
6331 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
6332 | } | |
a2fbb9ea | 6333 | |
619c5cb6 | 6334 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
34f80b04 | 6335 | bnx2x_init_pxp(bp); |
a2fbb9ea ET |
6336 | |
6337 | #ifdef __BIG_ENDIAN | |
34f80b04 EG |
6338 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); |
6339 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); | |
6340 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); | |
6341 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); | |
6342 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); | |
8badd27a EG |
6343 | /* make sure this value is 0 */ |
6344 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | |
34f80b04 EG |
6345 | |
6346 | /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ | |
6347 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); | |
6348 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); | |
6349 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); | |
6350 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); | |
a2fbb9ea ET |
6351 | #endif |
6352 | ||
523224a3 DK |
6353 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
6354 | ||
34f80b04 EG |
6355 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
6356 | REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); | |
a2fbb9ea | 6357 | |
34f80b04 EG |
6358 | /* let the HW do it's magic ... */ |
6359 | msleep(100); | |
6360 | /* finish PXP init */ | |
6361 | val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); | |
6362 | if (val != 1) { | |
6363 | BNX2X_ERR("PXP2 CFG failed\n"); | |
6364 | return -EBUSY; | |
6365 | } | |
6366 | val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); | |
6367 | if (val != 1) { | |
6368 | BNX2X_ERR("PXP2 RD_INIT failed\n"); | |
6369 | return -EBUSY; | |
6370 | } | |
a2fbb9ea | 6371 | |
f2e0899f DK |
6372 | /* Timers bug workaround E2 only. We need to set the entire ILT to |
6373 | * have entries with value "0" and valid bit on. | |
6374 | * This needs to be done by the first PF that is loaded in a path | |
6375 | * (i.e. common phase) | |
6376 | */ | |
619c5cb6 VZ |
6377 | if (!CHIP_IS_E1x(bp)) { |
6378 | /* In E2 there is a bug in the timers block that can cause function 6 / 7 | |
6379 | * (i.e. vnic3) to start even if it is marked as "scan-off". | |
6380 | * This occurs when a different function (func2,3) is being marked | |
6381 | * as "scan-off". Real-life scenario for example: if a driver is being | |
6382 | * load-unloaded while func6,7 are down. This will cause the timer to access | |
6383 | * the ilt, translate to a logical address and send a request to read/write. | |
6384 | * Since the ilt for the function that is down is not valid, this will cause | |
6385 | * a translation error which is unrecoverable. | |
6386 | * The Workaround is intended to make sure that when this happens nothing fatal | |
6387 | * will occur. The workaround: | |
6388 | * 1. First PF driver which loads on a path will: | |
6389 | * a. After taking the chip out of reset, by using pretend, | |
6390 | * it will write "0" to the following registers of | |
6391 | * the other vnics. | |
6392 | * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6393 | * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); | |
6394 | * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); | |
6395 | * And for itself it will write '1' to | |
6396 | * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable | |
6397 | * dmae-operations (writing to pram for example.) | |
6398 | * note: can be done for only function 6,7 but cleaner this | |
6399 | * way. | |
6400 | * b. Write zero+valid to the entire ILT. | |
6401 | * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of | |
6402 | * VNIC3 (of that port). The range allocated will be the | |
6403 | * entire ILT. This is needed to prevent ILT range error. | |
6404 | * 2. Any PF driver load flow: | |
6405 | * a. ILT update with the physical addresses of the allocated | |
6406 | * logical pages. | |
6407 | * b. Wait 20msec. - note that this timeout is needed to make | |
6408 | * sure there are no requests in one of the PXP internal | |
6409 | * queues with "old" ILT addresses. | |
6410 | * c. PF enable in the PGLC. | |
6411 | * d. Clear the was_error of the PF in the PGLC. (could have | |
6412 | * occured while driver was down) | |
6413 | * e. PF enable in the CFC (WEAK + STRONG) | |
6414 | * f. Timers scan enable | |
6415 | * 3. PF driver unload flow: | |
6416 | * a. Clear the Timers scan_en. | |
6417 | * b. Polling for scan_on=0 for that PF. | |
6418 | * c. Clear the PF enable bit in the PXP. | |
6419 | * d. Clear the PF enable in the CFC (WEAK + STRONG) | |
6420 | * e. Write zero+valid to all ILT entries (The valid bit must | |
6421 | * stay set) | |
6422 | * f. If this is VNIC 3 of a port then also init | |
6423 | * first_timers_ilt_entry to zero and last_timers_ilt_entry | |
6424 | * to the last enrty in the ILT. | |
6425 | * | |
6426 | * Notes: | |
6427 | * Currently the PF error in the PGLC is non recoverable. | |
6428 | * In the future the there will be a recovery routine for this error. | |
6429 | * Currently attention is masked. | |
6430 | * Having an MCP lock on the load/unload process does not guarantee that | |
6431 | * there is no Timer disable during Func6/7 enable. This is because the | |
6432 | * Timers scan is currently being cleared by the MCP on FLR. | |
6433 | * Step 2.d can be done only for PF6/7 and the driver can also check if | |
6434 | * there is error before clearing it. But the flow above is simpler and | |
6435 | * more general. | |
6436 | * All ILT entries are written by zero+valid and not just PF6/7 | |
6437 | * ILT entries since in the future the ILT entries allocation for | |
6438 | * PF-s might be dynamic. | |
6439 | */ | |
f2e0899f DK |
6440 | struct ilt_client_info ilt_cli; |
6441 | struct bnx2x_ilt ilt; | |
6442 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
6443 | memset(&ilt, 0, sizeof(struct bnx2x_ilt)); | |
6444 | ||
b595076a | 6445 | /* initialize dummy TM client */ |
f2e0899f DK |
6446 | ilt_cli.start = 0; |
6447 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
6448 | ilt_cli.client_num = ILT_CLIENT_TM; | |
6449 | ||
6450 | /* Step 1: set zeroes to all ilt page entries with valid bit on | |
6451 | * Step 2: set the timers first/last ilt entry to point | |
6452 | * to the entire range to prevent ILT range error for 3rd/4th | |
619c5cb6 | 6453 | * vnic (this code assumes existance of the vnic) |
f2e0899f DK |
6454 | * |
6455 | * both steps performed by call to bnx2x_ilt_client_init_op() | |
6456 | * with dummy TM client | |
6457 | * | |
6458 | * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT | |
6459 | * and his brother are split registers | |
6460 | */ | |
6461 | bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); | |
6462 | bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); | |
6463 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
6464 | ||
6465 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); | |
6466 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); | |
6467 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); | |
6468 | } | |
6469 | ||
6470 | ||
34f80b04 EG |
6471 | REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); |
6472 | REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); | |
a2fbb9ea | 6473 | |
619c5cb6 | 6474 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6475 | int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : |
6476 | (CHIP_REV_IS_FPGA(bp) ? 400 : 0); | |
619c5cb6 | 6477 | bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); |
f2e0899f | 6478 | |
619c5cb6 | 6479 | bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); |
f2e0899f DK |
6480 | |
6481 | /* let the HW do it's magic ... */ | |
6482 | do { | |
6483 | msleep(200); | |
6484 | val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); | |
6485 | } while (factor-- && (val != 1)); | |
6486 | ||
6487 | if (val != 1) { | |
6488 | BNX2X_ERR("ATC_INIT failed\n"); | |
6489 | return -EBUSY; | |
6490 | } | |
6491 | } | |
6492 | ||
619c5cb6 | 6493 | bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); |
a2fbb9ea | 6494 | |
34f80b04 EG |
6495 | /* clean the DMAE memory */ |
6496 | bp->dmae_ready = 1; | |
619c5cb6 VZ |
6497 | bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); |
6498 | ||
6499 | bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); | |
6500 | ||
6501 | bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); | |
6502 | ||
6503 | bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); | |
a2fbb9ea | 6504 | |
619c5cb6 | 6505 | bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); |
a2fbb9ea | 6506 | |
34f80b04 EG |
6507 | bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); |
6508 | bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); | |
6509 | bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); | |
6510 | bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); | |
6511 | ||
619c5cb6 | 6512 | bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); |
37b091ba | 6513 | |
f85582f8 | 6514 | |
523224a3 DK |
6515 | /* QM queues pointers table */ |
6516 | bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); | |
6517 | ||
34f80b04 EG |
6518 | /* soft reset pulse */ |
6519 | REG_WR(bp, QM_REG_SOFT_RESET, 1); | |
6520 | REG_WR(bp, QM_REG_SOFT_RESET, 0); | |
a2fbb9ea | 6521 | |
37b091ba | 6522 | #ifdef BCM_CNIC |
619c5cb6 | 6523 | bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); |
a2fbb9ea | 6524 | #endif |
a2fbb9ea | 6525 | |
619c5cb6 | 6526 | bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); |
523224a3 | 6527 | REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); |
619c5cb6 | 6528 | if (!CHIP_REV_IS_SLOW(bp)) |
34f80b04 EG |
6529 | /* enable hw interrupt from doorbell Q */ |
6530 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); | |
a2fbb9ea | 6531 | |
619c5cb6 | 6532 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
f2e0899f | 6533 | |
619c5cb6 | 6534 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
26c8fa4d | 6535 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
619c5cb6 | 6536 | |
f2e0899f | 6537 | if (!CHIP_IS_E1(bp)) |
619c5cb6 | 6538 | REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); |
f85582f8 | 6539 | |
a3348722 BW |
6540 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { |
6541 | if (IS_MF_AFEX(bp)) { | |
6542 | /* configure that VNTag and VLAN headers must be | |
6543 | * received in afex mode | |
6544 | */ | |
6545 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); | |
6546 | REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); | |
6547 | REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); | |
6548 | REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); | |
6549 | REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); | |
6550 | } else { | |
6551 | /* Bit-map indicating which L2 hdrs may appear | |
6552 | * after the basic Ethernet header | |
6553 | */ | |
6554 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, | |
6555 | bp->path_has_ovlan ? 7 : 6); | |
6556 | } | |
6557 | } | |
a2fbb9ea | 6558 | |
619c5cb6 VZ |
6559 | bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); |
6560 | bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); | |
6561 | bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); | |
6562 | bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); | |
a2fbb9ea | 6563 | |
619c5cb6 VZ |
6564 | if (!CHIP_IS_E1x(bp)) { |
6565 | /* reset VFC memories */ | |
6566 | REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6567 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6568 | VFC_MEMORIES_RST_REG_RAM_RST); | |
6569 | REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6570 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6571 | VFC_MEMORIES_RST_REG_RAM_RST); | |
a2fbb9ea | 6572 | |
619c5cb6 VZ |
6573 | msleep(20); |
6574 | } | |
a2fbb9ea | 6575 | |
619c5cb6 VZ |
6576 | bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); |
6577 | bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); | |
6578 | bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); | |
6579 | bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); | |
f2e0899f | 6580 | |
34f80b04 EG |
6581 | /* sync semi rtc */ |
6582 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6583 | 0x80000000); | |
6584 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
6585 | 0x80000000); | |
a2fbb9ea | 6586 | |
619c5cb6 VZ |
6587 | bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); |
6588 | bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); | |
6589 | bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); | |
a2fbb9ea | 6590 | |
a3348722 BW |
6591 | if (!CHIP_IS_E1x(bp)) { |
6592 | if (IS_MF_AFEX(bp)) { | |
6593 | /* configure that VNTag and VLAN headers must be | |
6594 | * sent in afex mode | |
6595 | */ | |
6596 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); | |
6597 | REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); | |
6598 | REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); | |
6599 | REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); | |
6600 | REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); | |
6601 | } else { | |
6602 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, | |
6603 | bp->path_has_ovlan ? 7 : 6); | |
6604 | } | |
6605 | } | |
f2e0899f | 6606 | |
34f80b04 | 6607 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
f85582f8 | 6608 | |
619c5cb6 VZ |
6609 | bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); |
6610 | ||
37b091ba MC |
6611 | #ifdef BCM_CNIC |
6612 | REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); | |
6613 | REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); | |
6614 | REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); | |
6615 | REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); | |
6616 | REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); | |
6617 | REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); | |
6618 | REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); | |
6619 | REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); | |
6620 | REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); | |
6621 | REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); | |
6622 | #endif | |
34f80b04 | 6623 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
a2fbb9ea | 6624 | |
34f80b04 EG |
6625 | if (sizeof(union cdu_context) != 1024) |
6626 | /* we currently assume that a context is 1024 bytes */ | |
51c1a580 MS |
6627 | dev_alert(&bp->pdev->dev, |
6628 | "please adjust the size of cdu_context(%ld)\n", | |
6629 | (long)sizeof(union cdu_context)); | |
a2fbb9ea | 6630 | |
619c5cb6 | 6631 | bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); |
34f80b04 EG |
6632 | val = (4 << 24) + (0 << 12) + 1024; |
6633 | REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); | |
a2fbb9ea | 6634 | |
619c5cb6 | 6635 | bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); |
34f80b04 | 6636 | REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); |
8d9c5f34 EG |
6637 | /* enable context validation interrupt from CFC */ |
6638 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
6639 | ||
6640 | /* set the thresholds to prevent CFC/CDU race */ | |
6641 | REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); | |
a2fbb9ea | 6642 | |
619c5cb6 | 6643 | bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); |
f2e0899f | 6644 | |
619c5cb6 | 6645 | if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) |
f2e0899f DK |
6646 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); |
6647 | ||
619c5cb6 VZ |
6648 | bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); |
6649 | bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); | |
a2fbb9ea | 6650 | |
34f80b04 EG |
6651 | /* Reset PCIE errors for debug */ |
6652 | REG_WR(bp, 0x2814, 0xffffffff); | |
6653 | REG_WR(bp, 0x3820, 0xffffffff); | |
a2fbb9ea | 6654 | |
619c5cb6 | 6655 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6656 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, |
6657 | (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | | |
6658 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); | |
6659 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, | |
6660 | (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | | |
6661 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | | |
6662 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); | |
6663 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, | |
6664 | (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | | |
6665 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | | |
6666 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); | |
6667 | } | |
6668 | ||
619c5cb6 | 6669 | bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); |
f2e0899f | 6670 | if (!CHIP_IS_E1(bp)) { |
619c5cb6 VZ |
6671 | /* in E3 this done in per-port section */ |
6672 | if (!CHIP_IS_E3(bp)) | |
6673 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
f2e0899f | 6674 | } |
619c5cb6 VZ |
6675 | if (CHIP_IS_E1H(bp)) |
6676 | /* not applicable for E2 (and above ...) */ | |
6677 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); | |
34f80b04 EG |
6678 | |
6679 | if (CHIP_REV_IS_SLOW(bp)) | |
6680 | msleep(200); | |
6681 | ||
6682 | /* finish CFC init */ | |
6683 | val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); | |
6684 | if (val != 1) { | |
6685 | BNX2X_ERR("CFC LL_INIT failed\n"); | |
6686 | return -EBUSY; | |
6687 | } | |
6688 | val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); | |
6689 | if (val != 1) { | |
6690 | BNX2X_ERR("CFC AC_INIT failed\n"); | |
6691 | return -EBUSY; | |
6692 | } | |
6693 | val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); | |
6694 | if (val != 1) { | |
6695 | BNX2X_ERR("CFC CAM_INIT failed\n"); | |
6696 | return -EBUSY; | |
6697 | } | |
6698 | REG_WR(bp, CFC_REG_DEBUG0, 0); | |
f1410647 | 6699 | |
f2e0899f DK |
6700 | if (CHIP_IS_E1(bp)) { |
6701 | /* read NIG statistic | |
6702 | to see if this is our first up since powerup */ | |
6703 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); | |
6704 | val = *bnx2x_sp(bp, wb_data[0]); | |
34f80b04 | 6705 | |
f2e0899f DK |
6706 | /* do internal memory self test */ |
6707 | if ((val == 0) && bnx2x_int_mem_test(bp)) { | |
6708 | BNX2X_ERR("internal mem self test failed\n"); | |
6709 | return -EBUSY; | |
6710 | } | |
34f80b04 EG |
6711 | } |
6712 | ||
fd4ef40d EG |
6713 | bnx2x_setup_fan_failure_detection(bp); |
6714 | ||
34f80b04 EG |
6715 | /* clear PXP2 attentions */ |
6716 | REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); | |
a2fbb9ea | 6717 | |
4a33bc03 | 6718 | bnx2x_enable_blocks_attention(bp); |
c9ee9206 | 6719 | bnx2x_enable_blocks_parity(bp); |
a2fbb9ea | 6720 | |
6bbca910 | 6721 | if (!BP_NOMCP(bp)) { |
619c5cb6 VZ |
6722 | if (CHIP_IS_E1x(bp)) |
6723 | bnx2x__common_init_phy(bp); | |
6bbca910 YR |
6724 | } else |
6725 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); | |
6726 | ||
34f80b04 EG |
6727 | return 0; |
6728 | } | |
a2fbb9ea | 6729 | |
619c5cb6 VZ |
6730 | /** |
6731 | * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. | |
6732 | * | |
6733 | * @bp: driver handle | |
6734 | */ | |
6735 | static int bnx2x_init_hw_common_chip(struct bnx2x *bp) | |
6736 | { | |
6737 | int rc = bnx2x_init_hw_common(bp); | |
6738 | ||
6739 | if (rc) | |
6740 | return rc; | |
6741 | ||
6742 | /* In E2 2-PORT mode, same ext phy is used for the two paths */ | |
6743 | if (!BP_NOMCP(bp)) | |
6744 | bnx2x__common_init_phy(bp); | |
6745 | ||
6746 | return 0; | |
6747 | } | |
6748 | ||
523224a3 | 6749 | static int bnx2x_init_hw_port(struct bnx2x *bp) |
34f80b04 EG |
6750 | { |
6751 | int port = BP_PORT(bp); | |
619c5cb6 | 6752 | int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; |
1c06328c | 6753 | u32 low, high; |
34f80b04 | 6754 | u32 val; |
a2fbb9ea | 6755 | |
619c5cb6 VZ |
6756 | bnx2x__link_reset(bp); |
6757 | ||
51c1a580 | 6758 | DP(NETIF_MSG_HW, "starting port init port %d\n", port); |
34f80b04 EG |
6759 | |
6760 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); | |
a2fbb9ea | 6761 | |
619c5cb6 VZ |
6762 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
6763 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); | |
6764 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
ca00392c | 6765 | |
f2e0899f DK |
6766 | /* Timers bug workaround: disables the pf_master bit in pglue at |
6767 | * common phase, we need to enable it here before any dmae access are | |
6768 | * attempted. Therefore we manually added the enable-master to the | |
6769 | * port phase (it also happens in the function phase) | |
6770 | */ | |
619c5cb6 | 6771 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6772 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
6773 | ||
619c5cb6 VZ |
6774 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
6775 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
6776 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); | |
6777 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
6778 | ||
6779 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
6780 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
6781 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
6782 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
a2fbb9ea | 6783 | |
523224a3 DK |
6784 | /* QM cid (connection) count */ |
6785 | bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); | |
a2fbb9ea | 6786 | |
523224a3 | 6787 | #ifdef BCM_CNIC |
619c5cb6 | 6788 | bnx2x_init_block(bp, BLOCK_TM, init_phase); |
37b091ba MC |
6789 | REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); |
6790 | REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); | |
a2fbb9ea | 6791 | #endif |
cdaa7cb8 | 6792 | |
619c5cb6 | 6793 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
f2e0899f DK |
6794 | |
6795 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { | |
619c5cb6 VZ |
6796 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
6797 | ||
6798 | if (IS_MF(bp)) | |
6799 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | |
6800 | else if (bp->dev->mtu > 4096) { | |
6801 | if (bp->flags & ONE_PORT_FLAG) | |
6802 | low = 160; | |
6803 | else { | |
6804 | val = bp->dev->mtu; | |
6805 | /* (24*1024 + val*4)/256 */ | |
6806 | low = 96 + (val/64) + | |
6807 | ((val % 64) ? 1 : 0); | |
6808 | } | |
6809 | } else | |
6810 | low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); | |
6811 | high = low + 56; /* 14*1024/256 */ | |
f2e0899f DK |
6812 | REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); |
6813 | REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); | |
1c06328c | 6814 | } |
1c06328c | 6815 | |
619c5cb6 VZ |
6816 | if (CHIP_MODE_IS_4_PORT(bp)) |
6817 | REG_WR(bp, (BP_PORT(bp) ? | |
6818 | BRB1_REG_MAC_GUARANTIED_1 : | |
6819 | BRB1_REG_MAC_GUARANTIED_0), 40); | |
1c06328c | 6820 | |
ca00392c | 6821 | |
619c5cb6 | 6822 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
a3348722 BW |
6823 | if (CHIP_IS_E3B0(bp)) { |
6824 | if (IS_MF_AFEX(bp)) { | |
6825 | /* configure headers for AFEX mode */ | |
6826 | REG_WR(bp, BP_PORT(bp) ? | |
6827 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
6828 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); | |
6829 | REG_WR(bp, BP_PORT(bp) ? | |
6830 | PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : | |
6831 | PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); | |
6832 | REG_WR(bp, BP_PORT(bp) ? | |
6833 | PRS_REG_MUST_HAVE_HDRS_PORT_1 : | |
6834 | PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); | |
6835 | } else { | |
6836 | /* Ovlan exists only if we are in multi-function + | |
6837 | * switch-dependent mode, in switch-independent there | |
6838 | * is no ovlan headers | |
6839 | */ | |
6840 | REG_WR(bp, BP_PORT(bp) ? | |
6841 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
6842 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, | |
6843 | (bp->path_has_ovlan ? 7 : 6)); | |
6844 | } | |
6845 | } | |
356e2385 | 6846 | |
619c5cb6 VZ |
6847 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
6848 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
6849 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
6850 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
356e2385 | 6851 | |
619c5cb6 VZ |
6852 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
6853 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
6854 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
6855 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
34f80b04 | 6856 | |
619c5cb6 VZ |
6857 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
6858 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
a2fbb9ea | 6859 | |
619c5cb6 VZ |
6860 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
6861 | ||
6862 | if (CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
6863 | /* configure PBF to work without PAUSE mtu 9000 */ |
6864 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); | |
a2fbb9ea | 6865 | |
f2e0899f DK |
6866 | /* update threshold */ |
6867 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); | |
6868 | /* update init credit */ | |
6869 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); | |
a2fbb9ea | 6870 | |
f2e0899f DK |
6871 | /* probe changes */ |
6872 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); | |
6873 | udelay(50); | |
6874 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); | |
6875 | } | |
a2fbb9ea | 6876 | |
37b091ba | 6877 | #ifdef BCM_CNIC |
619c5cb6 | 6878 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); |
a2fbb9ea | 6879 | #endif |
619c5cb6 VZ |
6880 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
6881 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); | |
34f80b04 EG |
6882 | |
6883 | if (CHIP_IS_E1(bp)) { | |
6884 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
6885 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
6886 | } | |
619c5cb6 | 6887 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
34f80b04 | 6888 | |
619c5cb6 | 6889 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 6890 | |
619c5cb6 | 6891 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
34f80b04 EG |
6892 | /* init aeu_mask_attn_func_0/1: |
6893 | * - SF mode: bits 3-7 are masked. only bits 0-2 are in use | |
6894 | * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF | |
6895 | * bits 4-7 are used for "per vn group attention" */ | |
e4901dde VZ |
6896 | val = IS_MF(bp) ? 0xF7 : 0x7; |
6897 | /* Enable DCBX attention for all but E1 */ | |
6898 | val |= CHIP_IS_E1(bp) ? 0 : 0x10; | |
6899 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); | |
34f80b04 | 6900 | |
619c5cb6 VZ |
6901 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
6902 | ||
6903 | if (!CHIP_IS_E1x(bp)) { | |
6904 | /* Bit-map indicating which L2 hdrs may appear after the | |
6905 | * basic Ethernet header | |
6906 | */ | |
a3348722 BW |
6907 | if (IS_MF_AFEX(bp)) |
6908 | REG_WR(bp, BP_PORT(bp) ? | |
6909 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
6910 | NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); | |
6911 | else | |
6912 | REG_WR(bp, BP_PORT(bp) ? | |
6913 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
6914 | NIG_REG_P0_HDRS_AFTER_BASIC, | |
6915 | IS_MF_SD(bp) ? 7 : 6); | |
619c5cb6 VZ |
6916 | |
6917 | if (CHIP_IS_E3(bp)) | |
6918 | REG_WR(bp, BP_PORT(bp) ? | |
6919 | NIG_REG_LLH1_MF_MODE : | |
6920 | NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
6921 | } | |
6922 | if (!CHIP_IS_E3(bp)) | |
6923 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); | |
34f80b04 | 6924 | |
f2e0899f | 6925 | if (!CHIP_IS_E1(bp)) { |
fb3bff17 | 6926 | /* 0x2 disable mf_ov, 0x1 enable */ |
34f80b04 | 6927 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
0793f83f | 6928 | (IS_MF_SD(bp) ? 0x1 : 0x2)); |
34f80b04 | 6929 | |
619c5cb6 | 6930 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6931 | val = 0; |
6932 | switch (bp->mf_mode) { | |
6933 | case MULTI_FUNCTION_SD: | |
6934 | val = 1; | |
6935 | break; | |
6936 | case MULTI_FUNCTION_SI: | |
a3348722 | 6937 | case MULTI_FUNCTION_AFEX: |
f2e0899f DK |
6938 | val = 2; |
6939 | break; | |
6940 | } | |
6941 | ||
6942 | REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : | |
6943 | NIG_REG_LLH0_CLS_TYPE), val); | |
6944 | } | |
1c06328c EG |
6945 | { |
6946 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); | |
6947 | REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); | |
6948 | REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); | |
6949 | } | |
34f80b04 EG |
6950 | } |
6951 | ||
619c5cb6 VZ |
6952 | |
6953 | /* If SPIO5 is set to generate interrupts, enable it for this port */ | |
6954 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
6955 | if (val & (1 << MISC_REGISTERS_SPIO_5)) { | |
4d295db0 EG |
6956 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
6957 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
6958 | val = REG_RD(bp, reg_addr); | |
f1410647 | 6959 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
4d295db0 | 6960 | REG_WR(bp, reg_addr, val); |
f1410647 | 6961 | } |
a2fbb9ea | 6962 | |
34f80b04 EG |
6963 | return 0; |
6964 | } | |
6965 | ||
34f80b04 EG |
6966 | static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) |
6967 | { | |
6968 | int reg; | |
32d68de1 | 6969 | u32 wb_write[2]; |
34f80b04 | 6970 | |
f2e0899f | 6971 | if (CHIP_IS_E1(bp)) |
34f80b04 | 6972 | reg = PXP2_REG_RQ_ONCHIP_AT + index*8; |
f2e0899f DK |
6973 | else |
6974 | reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; | |
34f80b04 | 6975 | |
32d68de1 YM |
6976 | wb_write[0] = ONCHIP_ADDR1(addr); |
6977 | wb_write[1] = ONCHIP_ADDR2(addr); | |
6978 | REG_WR_DMAE(bp, reg, wb_write, 2); | |
34f80b04 EG |
6979 | } |
6980 | ||
1191cb83 ED |
6981 | static void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, |
6982 | u8 idu_sb_id, bool is_Pf) | |
6983 | { | |
6984 | u32 data, ctl, cnt = 100; | |
6985 | u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; | |
6986 | u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; | |
6987 | u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; | |
6988 | u32 sb_bit = 1 << (idu_sb_id%32); | |
6989 | u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; | |
6990 | u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; | |
6991 | ||
6992 | /* Not supported in BC mode */ | |
6993 | if (CHIP_INT_MODE_IS_BC(bp)) | |
6994 | return; | |
6995 | ||
6996 | data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup | |
6997 | << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | | |
6998 | IGU_REGULAR_CLEANUP_SET | | |
6999 | IGU_REGULAR_BCLEANUP; | |
7000 | ||
7001 | ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | | |
7002 | func_encode << IGU_CTRL_REG_FID_SHIFT | | |
7003 | IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; | |
7004 | ||
7005 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7006 | data, igu_addr_data); | |
7007 | REG_WR(bp, igu_addr_data, data); | |
7008 | mmiowb(); | |
7009 | barrier(); | |
7010 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7011 | ctl, igu_addr_ctl); | |
7012 | REG_WR(bp, igu_addr_ctl, ctl); | |
7013 | mmiowb(); | |
7014 | barrier(); | |
7015 | ||
7016 | /* wait for clean up to finish */ | |
7017 | while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) | |
7018 | msleep(20); | |
7019 | ||
7020 | ||
7021 | if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { | |
7022 | DP(NETIF_MSG_HW, | |
7023 | "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n", | |
7024 | idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); | |
7025 | } | |
7026 | } | |
7027 | ||
7028 | static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) | |
f2e0899f | 7029 | { |
619c5cb6 | 7030 | bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); |
f2e0899f DK |
7031 | } |
7032 | ||
1191cb83 | 7033 | static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) |
f2e0899f DK |
7034 | { |
7035 | u32 i, base = FUNC_ILT_BASE(func); | |
7036 | for (i = base; i < base + ILT_PER_FUNC; i++) | |
7037 | bnx2x_ilt_wr(bp, i, 0); | |
7038 | } | |
7039 | ||
523224a3 | 7040 | static int bnx2x_init_hw_func(struct bnx2x *bp) |
34f80b04 EG |
7041 | { |
7042 | int port = BP_PORT(bp); | |
7043 | int func = BP_FUNC(bp); | |
619c5cb6 | 7044 | int init_phase = PHASE_PF0 + func; |
523224a3 DK |
7045 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
7046 | u16 cdu_ilt_start; | |
8badd27a | 7047 | u32 addr, val; |
f4a66897 | 7048 | u32 main_mem_base, main_mem_size, main_mem_prty_clr; |
89db4ad8 | 7049 | int i, main_mem_width, rc; |
34f80b04 | 7050 | |
51c1a580 | 7051 | DP(NETIF_MSG_HW, "starting func init func %d\n", func); |
34f80b04 | 7052 | |
619c5cb6 | 7053 | /* FLR cleanup - hmmm */ |
89db4ad8 AE |
7054 | if (!CHIP_IS_E1x(bp)) { |
7055 | rc = bnx2x_pf_flr_clnup(bp); | |
7056 | if (rc) | |
7057 | return rc; | |
7058 | } | |
619c5cb6 | 7059 | |
8badd27a | 7060 | /* set MSI reconfigure capability */ |
f2e0899f DK |
7061 | if (bp->common.int_block == INT_BLOCK_HC) { |
7062 | addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); | |
7063 | val = REG_RD(bp, addr); | |
7064 | val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; | |
7065 | REG_WR(bp, addr, val); | |
7066 | } | |
8badd27a | 7067 | |
619c5cb6 VZ |
7068 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
7069 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
7070 | ||
523224a3 DK |
7071 | ilt = BP_ILT(bp); |
7072 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
37b091ba | 7073 | |
523224a3 | 7074 | for (i = 0; i < L2_ILT_LINES(bp); i++) { |
a052997e | 7075 | ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; |
523224a3 | 7076 | ilt->lines[cdu_ilt_start + i].page_mapping = |
a052997e MS |
7077 | bp->context[i].cxt_mapping; |
7078 | ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; | |
37b091ba | 7079 | } |
523224a3 | 7080 | bnx2x_ilt_init_op(bp, INITOP_SET); |
f85582f8 | 7081 | |
523224a3 DK |
7082 | #ifdef BCM_CNIC |
7083 | bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); | |
37b091ba | 7084 | |
523224a3 DK |
7085 | /* T1 hash bits value determines the T1 number of entries */ |
7086 | REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); | |
7087 | #endif | |
37b091ba | 7088 | |
523224a3 DK |
7089 | #ifndef BCM_CNIC |
7090 | /* set NIC mode */ | |
7091 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
7092 | #endif /* BCM_CNIC */ | |
37b091ba | 7093 | |
619c5cb6 | 7094 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7095 | u32 pf_conf = IGU_PF_CONF_FUNC_EN; |
7096 | ||
7097 | /* Turn on a single ISR mode in IGU if driver is going to use | |
7098 | * INT#x or MSI | |
7099 | */ | |
7100 | if (!(bp->flags & USING_MSIX_FLAG)) | |
7101 | pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; | |
7102 | /* | |
7103 | * Timers workaround bug: function init part. | |
7104 | * Need to wait 20msec after initializing ILT, | |
7105 | * needed to make sure there are no requests in | |
7106 | * one of the PXP internal queues with "old" ILT addresses | |
7107 | */ | |
7108 | msleep(20); | |
7109 | /* | |
7110 | * Master enable - Due to WB DMAE writes performed before this | |
7111 | * register is re-initialized as part of the regular function | |
7112 | * init | |
7113 | */ | |
7114 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
7115 | /* Enable the function in IGU */ | |
7116 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); | |
7117 | } | |
7118 | ||
523224a3 | 7119 | bp->dmae_ready = 1; |
34f80b04 | 7120 | |
619c5cb6 | 7121 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
523224a3 | 7122 | |
619c5cb6 | 7123 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7124 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); |
7125 | ||
619c5cb6 VZ |
7126 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
7127 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
7128 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); | |
7129 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
7130 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); | |
7131 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
7132 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
7133 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
7134 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
7135 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); | |
7136 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
7137 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
7138 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
7139 | ||
7140 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
7141 | REG_WR(bp, QM_REG_PF_EN, 1); |
7142 | ||
619c5cb6 VZ |
7143 | if (!CHIP_IS_E1x(bp)) { |
7144 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7145 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7146 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7147 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7148 | } | |
7149 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
7150 | ||
7151 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
7152 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); | |
7153 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); | |
7154 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); | |
7155 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); | |
7156 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
7157 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
7158 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
7159 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); | |
7160 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
7161 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); | |
7162 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
7163 | REG_WR(bp, PBF_REG_DISABLE_PF, 0); |
7164 | ||
619c5cb6 | 7165 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
523224a3 | 7166 | |
619c5cb6 | 7167 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
34f80b04 | 7168 | |
619c5cb6 | 7169 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7170 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); |
7171 | ||
fb3bff17 | 7172 | if (IS_MF(bp)) { |
34f80b04 | 7173 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); |
fb3bff17 | 7174 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); |
34f80b04 EG |
7175 | } |
7176 | ||
619c5cb6 | 7177 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
523224a3 | 7178 | |
34f80b04 | 7179 | /* HC init per function */ |
f2e0899f DK |
7180 | if (bp->common.int_block == INT_BLOCK_HC) { |
7181 | if (CHIP_IS_E1H(bp)) { | |
7182 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
7183 | ||
7184 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7185 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7186 | } | |
619c5cb6 | 7187 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
f2e0899f DK |
7188 | |
7189 | } else { | |
7190 | int num_segs, sb_idx, prod_offset; | |
7191 | ||
34f80b04 EG |
7192 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
7193 | ||
619c5cb6 | 7194 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7195 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
7196 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
7197 | } | |
7198 | ||
619c5cb6 | 7199 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 7200 | |
619c5cb6 | 7201 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7202 | int dsb_idx = 0; |
7203 | /** | |
7204 | * Producer memory: | |
7205 | * E2 mode: address 0-135 match to the mapping memory; | |
7206 | * 136 - PF0 default prod; 137 - PF1 default prod; | |
7207 | * 138 - PF2 default prod; 139 - PF3 default prod; | |
7208 | * 140 - PF0 attn prod; 141 - PF1 attn prod; | |
7209 | * 142 - PF2 attn prod; 143 - PF3 attn prod; | |
7210 | * 144-147 reserved. | |
7211 | * | |
7212 | * E1.5 mode - In backward compatible mode; | |
7213 | * for non default SB; each even line in the memory | |
7214 | * holds the U producer and each odd line hold | |
7215 | * the C producer. The first 128 producers are for | |
7216 | * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 | |
7217 | * producers are for the DSB for each PF. | |
7218 | * Each PF has five segments: (the order inside each | |
7219 | * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; | |
7220 | * 132-135 C prods; 136-139 X prods; 140-143 T prods; | |
7221 | * 144-147 attn prods; | |
7222 | */ | |
7223 | /* non-default-status-blocks */ | |
7224 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
7225 | IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; | |
7226 | for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { | |
7227 | prod_offset = (bp->igu_base_sb + sb_idx) * | |
7228 | num_segs; | |
7229 | ||
7230 | for (i = 0; i < num_segs; i++) { | |
7231 | addr = IGU_REG_PROD_CONS_MEMORY + | |
7232 | (prod_offset + i) * 4; | |
7233 | REG_WR(bp, addr, 0); | |
7234 | } | |
7235 | /* send consumer update with value 0 */ | |
7236 | bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, | |
7237 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7238 | bnx2x_igu_clear_sb(bp, | |
7239 | bp->igu_base_sb + sb_idx); | |
7240 | } | |
7241 | ||
7242 | /* default-status-blocks */ | |
7243 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
7244 | IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; | |
7245 | ||
7246 | if (CHIP_MODE_IS_4_PORT(bp)) | |
7247 | dsb_idx = BP_FUNC(bp); | |
7248 | else | |
3395a033 | 7249 | dsb_idx = BP_VN(bp); |
f2e0899f DK |
7250 | |
7251 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? | |
7252 | IGU_BC_BASE_DSB_PROD + dsb_idx : | |
7253 | IGU_NORM_BASE_DSB_PROD + dsb_idx); | |
7254 | ||
3395a033 DK |
7255 | /* |
7256 | * igu prods come in chunks of E1HVN_MAX (4) - | |
7257 | * does not matters what is the current chip mode | |
7258 | */ | |
f2e0899f DK |
7259 | for (i = 0; i < (num_segs * E1HVN_MAX); |
7260 | i += E1HVN_MAX) { | |
7261 | addr = IGU_REG_PROD_CONS_MEMORY + | |
7262 | (prod_offset + i)*4; | |
7263 | REG_WR(bp, addr, 0); | |
7264 | } | |
7265 | /* send consumer update with 0 */ | |
7266 | if (CHIP_INT_MODE_IS_BC(bp)) { | |
7267 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7268 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7269 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7270 | CSTORM_ID, 0, IGU_INT_NOP, 1); | |
7271 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7272 | XSTORM_ID, 0, IGU_INT_NOP, 1); | |
7273 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7274 | TSTORM_ID, 0, IGU_INT_NOP, 1); | |
7275 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7276 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
7277 | } else { | |
7278 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7279 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7280 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7281 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
7282 | } | |
7283 | bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); | |
7284 | ||
7285 | /* !!! these should become driver const once | |
7286 | rf-tool supports split-68 const */ | |
7287 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); | |
7288 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); | |
7289 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); | |
7290 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); | |
7291 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); | |
7292 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); | |
7293 | } | |
34f80b04 | 7294 | } |
34f80b04 | 7295 | |
c14423fe | 7296 | /* Reset PCIE errors for debug */ |
a2fbb9ea ET |
7297 | REG_WR(bp, 0x2114, 0xffffffff); |
7298 | REG_WR(bp, 0x2120, 0xffffffff); | |
523224a3 | 7299 | |
f4a66897 VZ |
7300 | if (CHIP_IS_E1x(bp)) { |
7301 | main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ | |
7302 | main_mem_base = HC_REG_MAIN_MEMORY + | |
7303 | BP_PORT(bp) * (main_mem_size * 4); | |
7304 | main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; | |
7305 | main_mem_width = 8; | |
7306 | ||
7307 | val = REG_RD(bp, main_mem_prty_clr); | |
7308 | if (val) | |
51c1a580 MS |
7309 | DP(NETIF_MSG_HW, |
7310 | "Hmmm... Parity errors in HC block during function init (0x%x)!\n", | |
7311 | val); | |
f4a66897 VZ |
7312 | |
7313 | /* Clear "false" parity errors in MSI-X table */ | |
7314 | for (i = main_mem_base; | |
7315 | i < main_mem_base + main_mem_size * 4; | |
7316 | i += main_mem_width) { | |
7317 | bnx2x_read_dmae(bp, i, main_mem_width / 4); | |
7318 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), | |
7319 | i, main_mem_width / 4); | |
7320 | } | |
7321 | /* Clear HC parity attention */ | |
7322 | REG_RD(bp, main_mem_prty_clr); | |
7323 | } | |
7324 | ||
619c5cb6 VZ |
7325 | #ifdef BNX2X_STOP_ON_ERROR |
7326 | /* Enable STORMs SP logging */ | |
7327 | REG_WR8(bp, BAR_USTRORM_INTMEM + | |
7328 | USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7329 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
7330 | TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7331 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
7332 | CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7333 | REG_WR8(bp, BAR_XSTRORM_INTMEM + | |
7334 | XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7335 | #endif | |
7336 | ||
b7737c9b | 7337 | bnx2x_phy_probe(&bp->link_params); |
f85582f8 | 7338 | |
34f80b04 EG |
7339 | return 0; |
7340 | } | |
7341 | ||
a2fbb9ea | 7342 | |
9f6c9258 | 7343 | void bnx2x_free_mem(struct bnx2x *bp) |
a2fbb9ea | 7344 | { |
a052997e MS |
7345 | int i; |
7346 | ||
a2fbb9ea | 7347 | /* fastpath */ |
b3b83c3f | 7348 | bnx2x_free_fp_mem(bp); |
a2fbb9ea ET |
7349 | /* end of fastpath */ |
7350 | ||
7351 | BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, | |
523224a3 | 7352 | sizeof(struct host_sp_status_block)); |
a2fbb9ea | 7353 | |
619c5cb6 VZ |
7354 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, |
7355 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
7356 | ||
a2fbb9ea | 7357 | BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, |
34f80b04 | 7358 | sizeof(struct bnx2x_slowpath)); |
a2fbb9ea | 7359 | |
a052997e MS |
7360 | for (i = 0; i < L2_ILT_LINES(bp); i++) |
7361 | BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, | |
7362 | bp->context[i].size); | |
523224a3 DK |
7363 | bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); |
7364 | ||
7365 | BNX2X_FREE(bp->ilt->lines); | |
f85582f8 | 7366 | |
37b091ba | 7367 | #ifdef BCM_CNIC |
619c5cb6 | 7368 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7369 | BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, |
7370 | sizeof(struct host_hc_status_block_e2)); | |
7371 | else | |
7372 | BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, | |
7373 | sizeof(struct host_hc_status_block_e1x)); | |
f85582f8 | 7374 | |
523224a3 | 7375 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); |
a2fbb9ea | 7376 | #endif |
f85582f8 | 7377 | |
7a9b2557 | 7378 | BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); |
a2fbb9ea | 7379 | |
523224a3 DK |
7380 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
7381 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
619c5cb6 VZ |
7382 | } |
7383 | ||
1191cb83 | 7384 | static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) |
619c5cb6 VZ |
7385 | { |
7386 | int num_groups; | |
50f0a562 | 7387 | int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1; |
619c5cb6 | 7388 | |
50f0a562 BW |
7389 | /* number of queues for statistics is number of eth queues + FCoE */ |
7390 | u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats; | |
619c5cb6 VZ |
7391 | |
7392 | /* Total number of FW statistics requests = | |
50f0a562 BW |
7393 | * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats + |
7394 | * num of queues | |
7395 | */ | |
7396 | bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats; | |
523224a3 | 7397 | |
619c5cb6 VZ |
7398 | |
7399 | /* Request is built from stats_query_header and an array of | |
7400 | * stats_query_cmd_group each of which contains | |
7401 | * STATS_QUERY_CMD_COUNT rules. The real number or requests is | |
7402 | * configured in the stats_query_header. | |
7403 | */ | |
50f0a562 BW |
7404 | num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) + |
7405 | (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0); | |
619c5cb6 VZ |
7406 | |
7407 | bp->fw_stats_req_sz = sizeof(struct stats_query_header) + | |
7408 | num_groups * sizeof(struct stats_query_cmd_group); | |
7409 | ||
7410 | /* Data for statistics requests + stats_conter | |
7411 | * | |
7412 | * stats_counter holds per-STORM counters that are incremented | |
7413 | * when STORM has finished with the current request. | |
50f0a562 BW |
7414 | * |
7415 | * memory for FCoE offloaded statistics are counted anyway, | |
7416 | * even if they will not be sent. | |
619c5cb6 VZ |
7417 | */ |
7418 | bp->fw_stats_data_sz = sizeof(struct per_port_stats) + | |
7419 | sizeof(struct per_pf_stats) + | |
50f0a562 | 7420 | sizeof(struct fcoe_statistics_params) + |
619c5cb6 VZ |
7421 | sizeof(struct per_queue_stats) * num_queue_stats + |
7422 | sizeof(struct stats_counter); | |
7423 | ||
7424 | BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, | |
7425 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
7426 | ||
7427 | /* Set shortcuts */ | |
7428 | bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; | |
7429 | bp->fw_stats_req_mapping = bp->fw_stats_mapping; | |
7430 | ||
7431 | bp->fw_stats_data = (struct bnx2x_fw_stats_data *) | |
7432 | ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); | |
7433 | ||
7434 | bp->fw_stats_data_mapping = bp->fw_stats_mapping + | |
7435 | bp->fw_stats_req_sz; | |
7436 | return 0; | |
7437 | ||
7438 | alloc_mem_err: | |
7439 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, | |
7440 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
51c1a580 | 7441 | BNX2X_ERR("Can't allocate memory\n"); |
619c5cb6 | 7442 | return -ENOMEM; |
a2fbb9ea ET |
7443 | } |
7444 | ||
f2e0899f | 7445 | |
9f6c9258 | 7446 | int bnx2x_alloc_mem(struct bnx2x *bp) |
a2fbb9ea | 7447 | { |
a052997e MS |
7448 | int i, allocated, context_size; |
7449 | ||
523224a3 | 7450 | #ifdef BCM_CNIC |
619c5cb6 VZ |
7451 | if (!CHIP_IS_E1x(bp)) |
7452 | /* size = the status block + ramrod buffers */ | |
f2e0899f DK |
7453 | BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, |
7454 | sizeof(struct host_hc_status_block_e2)); | |
7455 | else | |
7456 | BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, | |
7457 | sizeof(struct host_hc_status_block_e1x)); | |
8badd27a | 7458 | |
523224a3 DK |
7459 | /* allocate searcher T2 table */ |
7460 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); | |
7461 | #endif | |
a2fbb9ea | 7462 | |
8badd27a | 7463 | |
523224a3 DK |
7464 | BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, |
7465 | sizeof(struct host_sp_status_block)); | |
a2fbb9ea | 7466 | |
523224a3 DK |
7467 | BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, |
7468 | sizeof(struct bnx2x_slowpath)); | |
a2fbb9ea | 7469 | |
82fa848c MY |
7470 | #ifdef BCM_CNIC |
7471 | /* write address to which L5 should insert its values */ | |
7472 | bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp; | |
7473 | #endif | |
7474 | ||
619c5cb6 VZ |
7475 | /* Allocated memory for FW statistics */ |
7476 | if (bnx2x_alloc_fw_stats_mem(bp)) | |
7477 | goto alloc_mem_err; | |
7478 | ||
a052997e MS |
7479 | /* Allocate memory for CDU context: |
7480 | * This memory is allocated separately and not in the generic ILT | |
7481 | * functions because CDU differs in few aspects: | |
7482 | * 1. There are multiple entities allocating memory for context - | |
7483 | * 'regular' driver, CNIC and SRIOV driver. Each separately controls | |
7484 | * its own ILT lines. | |
7485 | * 2. Since CDU page-size is not a single 4KB page (which is the case | |
7486 | * for the other ILT clients), to be efficient we want to support | |
7487 | * allocation of sub-page-size in the last entry. | |
7488 | * 3. Context pointers are used by the driver to pass to FW / update | |
7489 | * the context (for the other ILT clients the pointers are used just to | |
7490 | * free the memory during unload). | |
7491 | */ | |
7492 | context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); | |
65abd74d | 7493 | |
a052997e MS |
7494 | for (i = 0, allocated = 0; allocated < context_size; i++) { |
7495 | bp->context[i].size = min(CDU_ILT_PAGE_SZ, | |
7496 | (context_size - allocated)); | |
7497 | BNX2X_PCI_ALLOC(bp->context[i].vcxt, | |
7498 | &bp->context[i].cxt_mapping, | |
7499 | bp->context[i].size); | |
7500 | allocated += bp->context[i].size; | |
7501 | } | |
523224a3 | 7502 | BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); |
65abd74d | 7503 | |
523224a3 DK |
7504 | if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) |
7505 | goto alloc_mem_err; | |
65abd74d | 7506 | |
9f6c9258 DK |
7507 | /* Slow path ring */ |
7508 | BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); | |
65abd74d | 7509 | |
523224a3 DK |
7510 | /* EQ */ |
7511 | BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, | |
7512 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
ab532cf3 | 7513 | |
b3b83c3f DK |
7514 | |
7515 | /* fastpath */ | |
7516 | /* need to be done at the end, since it's self adjusting to amount | |
7517 | * of memory available for RSS queues | |
7518 | */ | |
7519 | if (bnx2x_alloc_fp_mem(bp)) | |
7520 | goto alloc_mem_err; | |
9f6c9258 | 7521 | return 0; |
e1510706 | 7522 | |
9f6c9258 DK |
7523 | alloc_mem_err: |
7524 | bnx2x_free_mem(bp); | |
51c1a580 | 7525 | BNX2X_ERR("Can't allocate memory\n"); |
9f6c9258 | 7526 | return -ENOMEM; |
65abd74d YG |
7527 | } |
7528 | ||
a2fbb9ea ET |
7529 | /* |
7530 | * Init service functions | |
7531 | */ | |
a2fbb9ea | 7532 | |
619c5cb6 VZ |
7533 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, |
7534 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
7535 | int mac_type, unsigned long *ramrod_flags) | |
a2fbb9ea | 7536 | { |
619c5cb6 VZ |
7537 | int rc; |
7538 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
a2fbb9ea | 7539 | |
619c5cb6 | 7540 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
a2fbb9ea | 7541 | |
619c5cb6 VZ |
7542 | /* Fill general parameters */ |
7543 | ramrod_param.vlan_mac_obj = obj; | |
7544 | ramrod_param.ramrod_flags = *ramrod_flags; | |
a2fbb9ea | 7545 | |
619c5cb6 VZ |
7546 | /* Fill a user request section if needed */ |
7547 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
7548 | memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); | |
a2fbb9ea | 7549 | |
619c5cb6 | 7550 | __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); |
e3553b29 | 7551 | |
619c5cb6 VZ |
7552 | /* Set the command: ADD or DEL */ |
7553 | if (set) | |
7554 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
7555 | else | |
7556 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
a2fbb9ea ET |
7557 | } |
7558 | ||
619c5cb6 VZ |
7559 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
7560 | if (rc < 0) | |
7561 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); | |
7562 | return rc; | |
a2fbb9ea ET |
7563 | } |
7564 | ||
619c5cb6 VZ |
7565 | int bnx2x_del_all_macs(struct bnx2x *bp, |
7566 | struct bnx2x_vlan_mac_obj *mac_obj, | |
7567 | int mac_type, bool wait_for_comp) | |
e665bfda | 7568 | { |
619c5cb6 VZ |
7569 | int rc; |
7570 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | |
0793f83f | 7571 | |
619c5cb6 VZ |
7572 | /* Wait for completion of requested */ |
7573 | if (wait_for_comp) | |
7574 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
0793f83f | 7575 | |
619c5cb6 VZ |
7576 | /* Set the mac type of addresses we want to clear */ |
7577 | __set_bit(mac_type, &vlan_mac_flags); | |
0793f83f | 7578 | |
619c5cb6 VZ |
7579 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); |
7580 | if (rc < 0) | |
7581 | BNX2X_ERR("Failed to delete MACs: %d\n", rc); | |
0793f83f | 7582 | |
619c5cb6 | 7583 | return rc; |
0793f83f DK |
7584 | } |
7585 | ||
619c5cb6 | 7586 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
523224a3 | 7587 | { |
619c5cb6 | 7588 | unsigned long ramrod_flags = 0; |
e665bfda | 7589 | |
614c76df | 7590 | #ifdef BCM_CNIC |
a3348722 BW |
7591 | if (is_zero_ether_addr(bp->dev->dev_addr) && |
7592 | (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) { | |
51c1a580 MS |
7593 | DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN, |
7594 | "Ignoring Zero MAC for STORAGE SD mode\n"); | |
614c76df DK |
7595 | return 0; |
7596 | } | |
7597 | #endif | |
7598 | ||
619c5cb6 | 7599 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
0793f83f | 7600 | |
619c5cb6 VZ |
7601 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); |
7602 | /* Eth MAC is set on RSS leading client (fp[0]) */ | |
15192a8c BW |
7603 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj, |
7604 | set, BNX2X_ETH_MAC, &ramrod_flags); | |
e665bfda | 7605 | } |
6e30dd4e | 7606 | |
619c5cb6 | 7607 | int bnx2x_setup_leading(struct bnx2x *bp) |
ec6ba945 | 7608 | { |
619c5cb6 | 7609 | return bnx2x_setup_queue(bp, &bp->fp[0], 1); |
993ac7b5 | 7610 | } |
a2fbb9ea | 7611 | |
d6214d7a | 7612 | /** |
e8920674 | 7613 | * bnx2x_set_int_mode - configure interrupt mode |
d6214d7a | 7614 | * |
e8920674 | 7615 | * @bp: driver handle |
d6214d7a | 7616 | * |
e8920674 | 7617 | * In case of MSI-X it will also try to enable MSI-X. |
d6214d7a | 7618 | */ |
0e8d2ec5 | 7619 | void bnx2x_set_int_mode(struct bnx2x *bp) |
ca00392c | 7620 | { |
9ee3d37b | 7621 | switch (int_mode) { |
d6214d7a DK |
7622 | case INT_MODE_MSI: |
7623 | bnx2x_enable_msi(bp); | |
7624 | /* falling through... */ | |
7625 | case INT_MODE_INTx: | |
6383c0b3 | 7626 | bp->num_queues = 1 + NON_ETH_CONTEXT_USE; |
51c1a580 | 7627 | BNX2X_DEV_INFO("set number of queues to 1\n"); |
ca00392c | 7628 | break; |
d6214d7a | 7629 | default: |
d6214d7a DK |
7630 | /* if we can't use MSI-X we only need one fp, |
7631 | * so try to enable MSI-X with the requested number of fp's | |
7632 | * and fallback to MSI or legacy INTx with one fp | |
7633 | */ | |
30a5de77 DK |
7634 | if (bnx2x_enable_msix(bp) || |
7635 | bp->flags & USING_SINGLE_MSIX_FLAG) { | |
7636 | /* failed to enable multiple MSI-X */ | |
7637 | BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", | |
51c1a580 MS |
7638 | bp->num_queues, 1 + NON_ETH_CONTEXT_USE); |
7639 | ||
6383c0b3 | 7640 | bp->num_queues = 1 + NON_ETH_CONTEXT_USE; |
d6214d7a | 7641 | |
9ee3d37b | 7642 | /* Try to enable MSI */ |
30a5de77 DK |
7643 | if (!(bp->flags & USING_SINGLE_MSIX_FLAG) && |
7644 | !(bp->flags & DISABLE_MSI_FLAG)) | |
d6214d7a DK |
7645 | bnx2x_enable_msi(bp); |
7646 | } | |
9f6c9258 DK |
7647 | break; |
7648 | } | |
a2fbb9ea ET |
7649 | } |
7650 | ||
c2bff63f DK |
7651 | /* must be called prioir to any HW initializations */ |
7652 | static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) | |
7653 | { | |
7654 | return L2_ILT_LINES(bp); | |
7655 | } | |
7656 | ||
523224a3 DK |
7657 | void bnx2x_ilt_set_info(struct bnx2x *bp) |
7658 | { | |
7659 | struct ilt_client_info *ilt_client; | |
7660 | struct bnx2x_ilt *ilt = BP_ILT(bp); | |
7661 | u16 line = 0; | |
7662 | ||
7663 | ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); | |
7664 | DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); | |
7665 | ||
7666 | /* CDU */ | |
7667 | ilt_client = &ilt->clients[ILT_CLIENT_CDU]; | |
7668 | ilt_client->client_num = ILT_CLIENT_CDU; | |
7669 | ilt_client->page_size = CDU_ILT_PAGE_SZ; | |
7670 | ilt_client->flags = ILT_CLIENT_SKIP_MEM; | |
7671 | ilt_client->start = line; | |
619c5cb6 | 7672 | line += bnx2x_cid_ilt_lines(bp); |
523224a3 DK |
7673 | #ifdef BCM_CNIC |
7674 | line += CNIC_ILT_LINES; | |
7675 | #endif | |
7676 | ilt_client->end = line - 1; | |
7677 | ||
51c1a580 | 7678 | DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", |
523224a3 DK |
7679 | ilt_client->start, |
7680 | ilt_client->end, | |
7681 | ilt_client->page_size, | |
7682 | ilt_client->flags, | |
7683 | ilog2(ilt_client->page_size >> 12)); | |
7684 | ||
7685 | /* QM */ | |
7686 | if (QM_INIT(bp->qm_cid_count)) { | |
7687 | ilt_client = &ilt->clients[ILT_CLIENT_QM]; | |
7688 | ilt_client->client_num = ILT_CLIENT_QM; | |
7689 | ilt_client->page_size = QM_ILT_PAGE_SZ; | |
7690 | ilt_client->flags = 0; | |
7691 | ilt_client->start = line; | |
7692 | ||
7693 | /* 4 bytes for each cid */ | |
7694 | line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, | |
7695 | QM_ILT_PAGE_SZ); | |
7696 | ||
7697 | ilt_client->end = line - 1; | |
7698 | ||
51c1a580 MS |
7699 | DP(NETIF_MSG_IFUP, |
7700 | "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
7701 | ilt_client->start, |
7702 | ilt_client->end, | |
7703 | ilt_client->page_size, | |
7704 | ilt_client->flags, | |
7705 | ilog2(ilt_client->page_size >> 12)); | |
7706 | ||
7707 | } | |
7708 | /* SRC */ | |
7709 | ilt_client = &ilt->clients[ILT_CLIENT_SRC]; | |
7710 | #ifdef BCM_CNIC | |
7711 | ilt_client->client_num = ILT_CLIENT_SRC; | |
7712 | ilt_client->page_size = SRC_ILT_PAGE_SZ; | |
7713 | ilt_client->flags = 0; | |
7714 | ilt_client->start = line; | |
7715 | line += SRC_ILT_LINES; | |
7716 | ilt_client->end = line - 1; | |
7717 | ||
51c1a580 MS |
7718 | DP(NETIF_MSG_IFUP, |
7719 | "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
7720 | ilt_client->start, |
7721 | ilt_client->end, | |
7722 | ilt_client->page_size, | |
7723 | ilt_client->flags, | |
7724 | ilog2(ilt_client->page_size >> 12)); | |
7725 | ||
7726 | #else | |
7727 | ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); | |
7728 | #endif | |
9f6c9258 | 7729 | |
523224a3 DK |
7730 | /* TM */ |
7731 | ilt_client = &ilt->clients[ILT_CLIENT_TM]; | |
7732 | #ifdef BCM_CNIC | |
7733 | ilt_client->client_num = ILT_CLIENT_TM; | |
7734 | ilt_client->page_size = TM_ILT_PAGE_SZ; | |
7735 | ilt_client->flags = 0; | |
7736 | ilt_client->start = line; | |
7737 | line += TM_ILT_LINES; | |
7738 | ilt_client->end = line - 1; | |
7739 | ||
51c1a580 MS |
7740 | DP(NETIF_MSG_IFUP, |
7741 | "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
7742 | ilt_client->start, |
7743 | ilt_client->end, | |
7744 | ilt_client->page_size, | |
7745 | ilt_client->flags, | |
7746 | ilog2(ilt_client->page_size >> 12)); | |
9f6c9258 | 7747 | |
523224a3 DK |
7748 | #else |
7749 | ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); | |
7750 | #endif | |
619c5cb6 | 7751 | BUG_ON(line > ILT_MAX_LINES); |
523224a3 | 7752 | } |
f85582f8 | 7753 | |
619c5cb6 VZ |
7754 | /** |
7755 | * bnx2x_pf_q_prep_init - prepare INIT transition parameters | |
7756 | * | |
7757 | * @bp: driver handle | |
7758 | * @fp: pointer to fastpath | |
7759 | * @init_params: pointer to parameters structure | |
7760 | * | |
7761 | * parameters configured: | |
7762 | * - HC configuration | |
7763 | * - Queue's CDU context | |
7764 | */ | |
1191cb83 | 7765 | static void bnx2x_pf_q_prep_init(struct bnx2x *bp, |
619c5cb6 | 7766 | struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) |
a2fbb9ea | 7767 | { |
6383c0b3 AE |
7768 | |
7769 | u8 cos; | |
a052997e MS |
7770 | int cxt_index, cxt_offset; |
7771 | ||
619c5cb6 VZ |
7772 | /* FCoE Queue uses Default SB, thus has no HC capabilities */ |
7773 | if (!IS_FCOE_FP(fp)) { | |
7774 | __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); | |
7775 | __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); | |
7776 | ||
7777 | /* If HC is supporterd, enable host coalescing in the transition | |
7778 | * to INIT state. | |
7779 | */ | |
7780 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); | |
7781 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); | |
7782 | ||
7783 | /* HC rate */ | |
7784 | init_params->rx.hc_rate = bp->rx_ticks ? | |
7785 | (1000000 / bp->rx_ticks) : 0; | |
7786 | init_params->tx.hc_rate = bp->tx_ticks ? | |
7787 | (1000000 / bp->tx_ticks) : 0; | |
7788 | ||
7789 | /* FW SB ID */ | |
7790 | init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = | |
7791 | fp->fw_sb_id; | |
7792 | ||
7793 | /* | |
7794 | * CQ index among the SB indices: FCoE clients uses the default | |
7795 | * SB, therefore it's different. | |
7796 | */ | |
6383c0b3 AE |
7797 | init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
7798 | init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; | |
619c5cb6 VZ |
7799 | } |
7800 | ||
6383c0b3 AE |
7801 | /* set maximum number of COSs supported by this queue */ |
7802 | init_params->max_cos = fp->max_cos; | |
7803 | ||
51c1a580 | 7804 | DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", |
6383c0b3 AE |
7805 | fp->index, init_params->max_cos); |
7806 | ||
7807 | /* set the context pointers queue object */ | |
a052997e | 7808 | for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { |
65565884 MS |
7809 | cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; |
7810 | cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * | |
a052997e | 7811 | ILT_PAGE_CIDS); |
6383c0b3 | 7812 | init_params->cxts[cos] = |
a052997e MS |
7813 | &bp->context[cxt_index].vcxt[cxt_offset].eth; |
7814 | } | |
619c5cb6 VZ |
7815 | } |
7816 | ||
6383c0b3 AE |
7817 | int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
7818 | struct bnx2x_queue_state_params *q_params, | |
7819 | struct bnx2x_queue_setup_tx_only_params *tx_only_params, | |
7820 | int tx_index, bool leading) | |
7821 | { | |
7822 | memset(tx_only_params, 0, sizeof(*tx_only_params)); | |
7823 | ||
7824 | /* Set the command */ | |
7825 | q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
7826 | ||
7827 | /* Set tx-only QUEUE flags: don't zero statistics */ | |
7828 | tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); | |
7829 | ||
7830 | /* choose the index of the cid to send the slow path on */ | |
7831 | tx_only_params->cid_index = tx_index; | |
7832 | ||
7833 | /* Set general TX_ONLY_SETUP parameters */ | |
7834 | bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); | |
7835 | ||
7836 | /* Set Tx TX_ONLY_SETUP parameters */ | |
7837 | bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); | |
7838 | ||
51c1a580 MS |
7839 | DP(NETIF_MSG_IFUP, |
7840 | "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", | |
6383c0b3 AE |
7841 | tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], |
7842 | q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, | |
7843 | tx_only_params->gen_params.spcl_id, tx_only_params->flags); | |
7844 | ||
7845 | /* send the ramrod */ | |
7846 | return bnx2x_queue_state_change(bp, q_params); | |
7847 | } | |
7848 | ||
7849 | ||
619c5cb6 VZ |
7850 | /** |
7851 | * bnx2x_setup_queue - setup queue | |
7852 | * | |
7853 | * @bp: driver handle | |
7854 | * @fp: pointer to fastpath | |
7855 | * @leading: is leading | |
7856 | * | |
7857 | * This function performs 2 steps in a Queue state machine | |
7858 | * actually: 1) RESET->INIT 2) INIT->SETUP | |
7859 | */ | |
7860 | ||
7861 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
7862 | bool leading) | |
7863 | { | |
3b603066 | 7864 | struct bnx2x_queue_state_params q_params = {NULL}; |
619c5cb6 VZ |
7865 | struct bnx2x_queue_setup_params *setup_params = |
7866 | &q_params.params.setup; | |
6383c0b3 AE |
7867 | struct bnx2x_queue_setup_tx_only_params *tx_only_params = |
7868 | &q_params.params.tx_only; | |
a2fbb9ea | 7869 | int rc; |
6383c0b3 AE |
7870 | u8 tx_index; |
7871 | ||
51c1a580 | 7872 | DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); |
a2fbb9ea | 7873 | |
ec6ba945 VZ |
7874 | /* reset IGU state skip FCoE L2 queue */ |
7875 | if (!IS_FCOE_FP(fp)) | |
7876 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, | |
523224a3 | 7877 | IGU_INT_ENABLE, 0); |
a2fbb9ea | 7878 | |
15192a8c | 7879 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
7880 | /* We want to wait for completion in this context */ |
7881 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 7882 | |
619c5cb6 VZ |
7883 | /* Prepare the INIT parameters */ |
7884 | bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); | |
ec6ba945 | 7885 | |
619c5cb6 VZ |
7886 | /* Set the command */ |
7887 | q_params.cmd = BNX2X_Q_CMD_INIT; | |
7888 | ||
7889 | /* Change the state to INIT */ | |
7890 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7891 | if (rc) { | |
6383c0b3 | 7892 | BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); |
619c5cb6 VZ |
7893 | return rc; |
7894 | } | |
ec6ba945 | 7895 | |
51c1a580 | 7896 | DP(NETIF_MSG_IFUP, "init complete\n"); |
6383c0b3 AE |
7897 | |
7898 | ||
619c5cb6 VZ |
7899 | /* Now move the Queue to the SETUP state... */ |
7900 | memset(setup_params, 0, sizeof(*setup_params)); | |
a2fbb9ea | 7901 | |
619c5cb6 VZ |
7902 | /* Set QUEUE flags */ |
7903 | setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); | |
523224a3 | 7904 | |
619c5cb6 | 7905 | /* Set general SETUP parameters */ |
6383c0b3 AE |
7906 | bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, |
7907 | FIRST_TX_COS_INDEX); | |
619c5cb6 | 7908 | |
6383c0b3 | 7909 | bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, |
619c5cb6 VZ |
7910 | &setup_params->rxq_params); |
7911 | ||
6383c0b3 AE |
7912 | bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, |
7913 | FIRST_TX_COS_INDEX); | |
619c5cb6 VZ |
7914 | |
7915 | /* Set the command */ | |
7916 | q_params.cmd = BNX2X_Q_CMD_SETUP; | |
7917 | ||
7918 | /* Change the state to SETUP */ | |
7919 | rc = bnx2x_queue_state_change(bp, &q_params); | |
6383c0b3 AE |
7920 | if (rc) { |
7921 | BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); | |
7922 | return rc; | |
7923 | } | |
7924 | ||
7925 | /* loop through the relevant tx-only indices */ | |
7926 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
7927 | tx_index < fp->max_cos; | |
7928 | tx_index++) { | |
7929 | ||
7930 | /* prepare and send tx-only ramrod*/ | |
7931 | rc = bnx2x_setup_tx_only(bp, fp, &q_params, | |
7932 | tx_only_params, tx_index, leading); | |
7933 | if (rc) { | |
7934 | BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", | |
7935 | fp->index, tx_index); | |
7936 | return rc; | |
7937 | } | |
7938 | } | |
523224a3 | 7939 | |
34f80b04 | 7940 | return rc; |
a2fbb9ea ET |
7941 | } |
7942 | ||
619c5cb6 | 7943 | static int bnx2x_stop_queue(struct bnx2x *bp, int index) |
a2fbb9ea | 7944 | { |
619c5cb6 | 7945 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
6383c0b3 | 7946 | struct bnx2x_fp_txdata *txdata; |
3b603066 | 7947 | struct bnx2x_queue_state_params q_params = {NULL}; |
6383c0b3 AE |
7948 | int rc, tx_index; |
7949 | ||
51c1a580 | 7950 | DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); |
a2fbb9ea | 7951 | |
15192a8c | 7952 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
7953 | /* We want to wait for completion in this context */ |
7954 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 7955 | |
6383c0b3 AE |
7956 | |
7957 | /* close tx-only connections */ | |
7958 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
7959 | tx_index < fp->max_cos; | |
7960 | tx_index++){ | |
7961 | ||
7962 | /* ascertain this is a normal queue*/ | |
65565884 | 7963 | txdata = fp->txdata_ptr[tx_index]; |
6383c0b3 | 7964 | |
51c1a580 | 7965 | DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", |
6383c0b3 AE |
7966 | txdata->txq_index); |
7967 | ||
7968 | /* send halt terminate on tx-only connection */ | |
7969 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; | |
7970 | memset(&q_params.params.terminate, 0, | |
7971 | sizeof(q_params.params.terminate)); | |
7972 | q_params.params.terminate.cid_index = tx_index; | |
7973 | ||
7974 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7975 | if (rc) | |
7976 | return rc; | |
7977 | ||
7978 | /* send halt terminate on tx-only connection */ | |
7979 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; | |
7980 | memset(&q_params.params.cfc_del, 0, | |
7981 | sizeof(q_params.params.cfc_del)); | |
7982 | q_params.params.cfc_del.cid_index = tx_index; | |
7983 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7984 | if (rc) | |
7985 | return rc; | |
7986 | } | |
7987 | /* Stop the primary connection: */ | |
7988 | /* ...halt the connection */ | |
619c5cb6 VZ |
7989 | q_params.cmd = BNX2X_Q_CMD_HALT; |
7990 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7991 | if (rc) | |
da5a662a | 7992 | return rc; |
a2fbb9ea | 7993 | |
6383c0b3 | 7994 | /* ...terminate the connection */ |
619c5cb6 | 7995 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
6383c0b3 AE |
7996 | memset(&q_params.params.terminate, 0, |
7997 | sizeof(q_params.params.terminate)); | |
7998 | q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 VZ |
7999 | rc = bnx2x_queue_state_change(bp, &q_params); |
8000 | if (rc) | |
523224a3 | 8001 | return rc; |
6383c0b3 | 8002 | /* ...delete cfc entry */ |
619c5cb6 | 8003 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
6383c0b3 AE |
8004 | memset(&q_params.params.cfc_del, 0, |
8005 | sizeof(q_params.params.cfc_del)); | |
8006 | q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 | 8007 | return bnx2x_queue_state_change(bp, &q_params); |
523224a3 DK |
8008 | } |
8009 | ||
8010 | ||
34f80b04 EG |
8011 | static void bnx2x_reset_func(struct bnx2x *bp) |
8012 | { | |
8013 | int port = BP_PORT(bp); | |
8014 | int func = BP_FUNC(bp); | |
f2e0899f | 8015 | int i; |
523224a3 DK |
8016 | |
8017 | /* Disable the function in the FW */ | |
8018 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); | |
8019 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); | |
8020 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); | |
8021 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); | |
8022 | ||
8023 | /* FP SBs */ | |
ec6ba945 | 8024 | for_each_eth_queue(bp, i) { |
523224a3 | 8025 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
619c5cb6 | 8026 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
8027 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), |
8028 | SB_DISABLED); | |
523224a3 DK |
8029 | } |
8030 | ||
619c5cb6 VZ |
8031 | #ifdef BCM_CNIC |
8032 | /* CNIC SB */ | |
8033 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
8034 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), | |
8035 | SB_DISABLED); | |
8036 | #endif | |
523224a3 | 8037 | /* SP SB */ |
619c5cb6 | 8038 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
8039 | CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), |
8040 | SB_DISABLED); | |
523224a3 DK |
8041 | |
8042 | for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) | |
8043 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), | |
8044 | 0); | |
34f80b04 EG |
8045 | |
8046 | /* Configure IGU */ | |
f2e0899f DK |
8047 | if (bp->common.int_block == INT_BLOCK_HC) { |
8048 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
8049 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
8050 | } else { | |
8051 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); | |
8052 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
8053 | } | |
34f80b04 | 8054 | |
37b091ba MC |
8055 | #ifdef BCM_CNIC |
8056 | /* Disable Timer scan */ | |
8057 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); | |
8058 | /* | |
8059 | * Wait for at least 10ms and up to 2 second for the timers scan to | |
8060 | * complete | |
8061 | */ | |
8062 | for (i = 0; i < 200; i++) { | |
8063 | msleep(10); | |
8064 | if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) | |
8065 | break; | |
8066 | } | |
8067 | #endif | |
34f80b04 | 8068 | /* Clear ILT */ |
f2e0899f DK |
8069 | bnx2x_clear_func_ilt(bp, func); |
8070 | ||
8071 | /* Timers workaround bug for E2: if this is vnic-3, | |
8072 | * we need to set the entire ilt range for this timers. | |
8073 | */ | |
619c5cb6 | 8074 | if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { |
f2e0899f DK |
8075 | struct ilt_client_info ilt_cli; |
8076 | /* use dummy TM client */ | |
8077 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
8078 | ilt_cli.start = 0; | |
8079 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
8080 | ilt_cli.client_num = ILT_CLIENT_TM; | |
8081 | ||
8082 | bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); | |
8083 | } | |
8084 | ||
8085 | /* this assumes that reset_port() called before reset_func()*/ | |
619c5cb6 | 8086 | if (!CHIP_IS_E1x(bp)) |
f2e0899f | 8087 | bnx2x_pf_disable(bp); |
523224a3 DK |
8088 | |
8089 | bp->dmae_ready = 0; | |
34f80b04 EG |
8090 | } |
8091 | ||
8092 | static void bnx2x_reset_port(struct bnx2x *bp) | |
8093 | { | |
8094 | int port = BP_PORT(bp); | |
8095 | u32 val; | |
8096 | ||
619c5cb6 VZ |
8097 | /* Reset physical Link */ |
8098 | bnx2x__link_reset(bp); | |
8099 | ||
34f80b04 EG |
8100 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
8101 | ||
8102 | /* Do not rcv packets to BRB */ | |
8103 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); | |
8104 | /* Do not direct rcv packets that are not for MCP to the BRB */ | |
8105 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
8106 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
8107 | ||
8108 | /* Configure AEU */ | |
8109 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); | |
8110 | ||
8111 | msleep(100); | |
8112 | /* Check for BRB port occupancy */ | |
8113 | val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); | |
8114 | if (val) | |
8115 | DP(NETIF_MSG_IFDOWN, | |
33471629 | 8116 | "BRB1 is not empty %d blocks are occupied\n", val); |
34f80b04 EG |
8117 | |
8118 | /* TODO: Close Doorbell port? */ | |
8119 | } | |
8120 | ||
1191cb83 | 8121 | static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) |
34f80b04 | 8122 | { |
3b603066 | 8123 | struct bnx2x_func_state_params func_params = {NULL}; |
34f80b04 | 8124 | |
619c5cb6 VZ |
8125 | /* Prepare parameters for function state transitions */ |
8126 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
34f80b04 | 8127 | |
619c5cb6 VZ |
8128 | func_params.f_obj = &bp->func_obj; |
8129 | func_params.cmd = BNX2X_F_CMD_HW_RESET; | |
34f80b04 | 8130 | |
619c5cb6 | 8131 | func_params.params.hw_init.load_phase = load_code; |
49d66772 | 8132 | |
619c5cb6 | 8133 | return bnx2x_func_state_change(bp, &func_params); |
34f80b04 EG |
8134 | } |
8135 | ||
1191cb83 | 8136 | static int bnx2x_func_stop(struct bnx2x *bp) |
ec6ba945 | 8137 | { |
3b603066 | 8138 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 | 8139 | int rc; |
228241eb | 8140 | |
619c5cb6 VZ |
8141 | /* Prepare parameters for function state transitions */ |
8142 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
8143 | func_params.f_obj = &bp->func_obj; | |
8144 | func_params.cmd = BNX2X_F_CMD_STOP; | |
da5a662a | 8145 | |
619c5cb6 VZ |
8146 | /* |
8147 | * Try to stop the function the 'good way'. If fails (in case | |
8148 | * of a parity error during bnx2x_chip_cleanup()) and we are | |
8149 | * not in a debug mode, perform a state transaction in order to | |
8150 | * enable further HW_RESET transaction. | |
8151 | */ | |
8152 | rc = bnx2x_func_state_change(bp, &func_params); | |
8153 | if (rc) { | |
34f80b04 | 8154 | #ifdef BNX2X_STOP_ON_ERROR |
619c5cb6 | 8155 | return rc; |
34f80b04 | 8156 | #else |
51c1a580 | 8157 | BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); |
619c5cb6 VZ |
8158 | __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); |
8159 | return bnx2x_func_state_change(bp, &func_params); | |
34f80b04 | 8160 | #endif |
228241eb | 8161 | } |
a2fbb9ea | 8162 | |
619c5cb6 VZ |
8163 | return 0; |
8164 | } | |
523224a3 | 8165 | |
619c5cb6 VZ |
8166 | /** |
8167 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
8168 | * | |
8169 | * @bp: driver handle | |
8170 | * @unload_mode: requested function's unload mode | |
8171 | * | |
8172 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
8173 | */ | |
8174 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) | |
8175 | { | |
8176 | u32 reset_code = 0; | |
8177 | int port = BP_PORT(bp); | |
3101c2bc | 8178 | |
619c5cb6 | 8179 | /* Select the UNLOAD request mode */ |
65abd74d YG |
8180 | if (unload_mode == UNLOAD_NORMAL) |
8181 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
8182 | ||
7d0446c2 | 8183 | else if (bp->flags & NO_WOL_FLAG) |
65abd74d | 8184 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
65abd74d | 8185 | |
7d0446c2 | 8186 | else if (bp->wol) { |
65abd74d YG |
8187 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
8188 | u8 *mac_addr = bp->dev->dev_addr; | |
8189 | u32 val; | |
f9977903 DK |
8190 | u16 pmc; |
8191 | ||
65abd74d | 8192 | /* The mac address is written to entries 1-4 to |
f9977903 DK |
8193 | * preserve entry 0 which is used by the PMF |
8194 | */ | |
3395a033 | 8195 | u8 entry = (BP_VN(bp) + 1)*8; |
65abd74d YG |
8196 | |
8197 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
8198 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); | |
8199 | ||
8200 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | |
8201 | (mac_addr[4] << 8) | mac_addr[5]; | |
8202 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); | |
8203 | ||
f9977903 DK |
8204 | /* Enable the PME and clear the status */ |
8205 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); | |
8206 | pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; | |
8207 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); | |
8208 | ||
65abd74d YG |
8209 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; |
8210 | ||
8211 | } else | |
8212 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
da5a662a | 8213 | |
619c5cb6 VZ |
8214 | /* Send the request to the MCP */ |
8215 | if (!BP_NOMCP(bp)) | |
8216 | reset_code = bnx2x_fw_command(bp, reset_code, 0); | |
8217 | else { | |
8218 | int path = BP_PATH(bp); | |
8219 | ||
51c1a580 | 8220 | DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", |
619c5cb6 VZ |
8221 | path, load_count[path][0], load_count[path][1], |
8222 | load_count[path][2]); | |
8223 | load_count[path][0]--; | |
8224 | load_count[path][1 + port]--; | |
51c1a580 | 8225 | DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", |
619c5cb6 VZ |
8226 | path, load_count[path][0], load_count[path][1], |
8227 | load_count[path][2]); | |
8228 | if (load_count[path][0] == 0) | |
8229 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; | |
8230 | else if (load_count[path][1 + port] == 0) | |
8231 | reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; | |
8232 | else | |
8233 | reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; | |
8234 | } | |
8235 | ||
8236 | return reset_code; | |
8237 | } | |
8238 | ||
8239 | /** | |
8240 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
8241 | * | |
8242 | * @bp: driver handle | |
8243 | */ | |
8244 | void bnx2x_send_unload_done(struct bnx2x *bp) | |
8245 | { | |
8246 | /* Report UNLOAD_DONE to MCP */ | |
8247 | if (!BP_NOMCP(bp)) | |
8248 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
8249 | } | |
8250 | ||
1191cb83 | 8251 | static int bnx2x_func_wait_started(struct bnx2x *bp) |
6debea87 DK |
8252 | { |
8253 | int tout = 50; | |
8254 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
8255 | ||
8256 | if (!bp->port.pmf) | |
8257 | return 0; | |
8258 | ||
8259 | /* | |
8260 | * (assumption: No Attention from MCP at this stage) | |
8261 | * PMF probably in the middle of TXdisable/enable transaction | |
8262 | * 1. Sync IRS for default SB | |
8263 | * 2. Sync SP queue - this guarantes us that attention handling started | |
8264 | * 3. Wait, that TXdisable/enable transaction completes | |
8265 | * | |
8266 | * 1+2 guranty that if DCBx attention was scheduled it already changed | |
8267 | * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy | |
8268 | * received complettion for the transaction the state is TX_STOPPED. | |
8269 | * State will return to STARTED after completion of TX_STOPPED-->STARTED | |
8270 | * transaction. | |
8271 | */ | |
8272 | ||
8273 | /* make sure default SB ISR is done */ | |
8274 | if (msix) | |
8275 | synchronize_irq(bp->msix_table[0].vector); | |
8276 | else | |
8277 | synchronize_irq(bp->pdev->irq); | |
8278 | ||
8279 | flush_workqueue(bnx2x_wq); | |
8280 | ||
8281 | while (bnx2x_func_get_state(bp, &bp->func_obj) != | |
8282 | BNX2X_F_STATE_STARTED && tout--) | |
8283 | msleep(20); | |
8284 | ||
8285 | if (bnx2x_func_get_state(bp, &bp->func_obj) != | |
8286 | BNX2X_F_STATE_STARTED) { | |
8287 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 8288 | BNX2X_ERR("Wrong function state\n"); |
6debea87 DK |
8289 | return -EBUSY; |
8290 | #else | |
8291 | /* | |
8292 | * Failed to complete the transaction in a "good way" | |
8293 | * Force both transactions with CLR bit | |
8294 | */ | |
3b603066 | 8295 | struct bnx2x_func_state_params func_params = {NULL}; |
6debea87 | 8296 | |
51c1a580 MS |
8297 | DP(NETIF_MSG_IFDOWN, |
8298 | "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n"); | |
6debea87 DK |
8299 | |
8300 | func_params.f_obj = &bp->func_obj; | |
8301 | __set_bit(RAMROD_DRV_CLR_ONLY, | |
8302 | &func_params.ramrod_flags); | |
8303 | ||
8304 | /* STARTED-->TX_ST0PPED */ | |
8305 | func_params.cmd = BNX2X_F_CMD_TX_STOP; | |
8306 | bnx2x_func_state_change(bp, &func_params); | |
8307 | ||
8308 | /* TX_ST0PPED-->STARTED */ | |
8309 | func_params.cmd = BNX2X_F_CMD_TX_START; | |
8310 | return bnx2x_func_state_change(bp, &func_params); | |
8311 | #endif | |
8312 | } | |
8313 | ||
8314 | return 0; | |
8315 | } | |
8316 | ||
619c5cb6 VZ |
8317 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) |
8318 | { | |
8319 | int port = BP_PORT(bp); | |
6383c0b3 AE |
8320 | int i, rc = 0; |
8321 | u8 cos; | |
3b603066 | 8322 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 VZ |
8323 | u32 reset_code; |
8324 | ||
8325 | /* Wait until tx fastpath tasks complete */ | |
8326 | for_each_tx_queue(bp, i) { | |
8327 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
8328 | ||
6383c0b3 | 8329 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 8330 | rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); |
619c5cb6 VZ |
8331 | #ifdef BNX2X_STOP_ON_ERROR |
8332 | if (rc) | |
8333 | return; | |
8334 | #endif | |
8335 | } | |
8336 | ||
8337 | /* Give HW time to discard old tx messages */ | |
8338 | usleep_range(1000, 1000); | |
8339 | ||
8340 | /* Clean all ETH MACs */ | |
15192a8c BW |
8341 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, |
8342 | false); | |
619c5cb6 VZ |
8343 | if (rc < 0) |
8344 | BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); | |
8345 | ||
8346 | /* Clean up UC list */ | |
15192a8c | 8347 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, |
619c5cb6 VZ |
8348 | true); |
8349 | if (rc < 0) | |
51c1a580 MS |
8350 | BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", |
8351 | rc); | |
619c5cb6 VZ |
8352 | |
8353 | /* Disable LLH */ | |
8354 | if (!CHIP_IS_E1(bp)) | |
8355 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
8356 | ||
8357 | /* Set "drop all" (stop Rx). | |
8358 | * We need to take a netif_addr_lock() here in order to prevent | |
8359 | * a race between the completion code and this code. | |
8360 | */ | |
8361 | netif_addr_lock_bh(bp->dev); | |
8362 | /* Schedule the rx_mode command */ | |
8363 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
8364 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
8365 | else | |
8366 | bnx2x_set_storm_rx_mode(bp); | |
8367 | ||
8368 | /* Cleanup multicast configuration */ | |
8369 | rparam.mcast_obj = &bp->mcast_obj; | |
8370 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
8371 | if (rc < 0) | |
8372 | BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); | |
8373 | ||
8374 | netif_addr_unlock_bh(bp->dev); | |
8375 | ||
8376 | ||
6debea87 DK |
8377 | |
8378 | /* | |
8379 | * Send the UNLOAD_REQUEST to the MCP. This will return if | |
8380 | * this function should perform FUNC, PORT or COMMON HW | |
8381 | * reset. | |
8382 | */ | |
8383 | reset_code = bnx2x_send_unload_req(bp, unload_mode); | |
8384 | ||
8385 | /* | |
8386 | * (assumption: No Attention from MCP at this stage) | |
8387 | * PMF probably in the middle of TXdisable/enable transaction | |
8388 | */ | |
8389 | rc = bnx2x_func_wait_started(bp); | |
8390 | if (rc) { | |
8391 | BNX2X_ERR("bnx2x_func_wait_started failed\n"); | |
8392 | #ifdef BNX2X_STOP_ON_ERROR | |
8393 | return; | |
8394 | #endif | |
8395 | } | |
8396 | ||
34f80b04 | 8397 | /* Close multi and leading connections |
619c5cb6 VZ |
8398 | * Completions for ramrods are collected in a synchronous way |
8399 | */ | |
523224a3 | 8400 | for_each_queue(bp, i) |
619c5cb6 | 8401 | if (bnx2x_stop_queue(bp, i)) |
523224a3 DK |
8402 | #ifdef BNX2X_STOP_ON_ERROR |
8403 | return; | |
8404 | #else | |
228241eb | 8405 | goto unload_error; |
523224a3 | 8406 | #endif |
619c5cb6 VZ |
8407 | /* If SP settings didn't get completed so far - something |
8408 | * very wrong has happen. | |
8409 | */ | |
8410 | if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) | |
8411 | BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); | |
a2fbb9ea | 8412 | |
619c5cb6 VZ |
8413 | #ifndef BNX2X_STOP_ON_ERROR |
8414 | unload_error: | |
8415 | #endif | |
523224a3 | 8416 | rc = bnx2x_func_stop(bp); |
da5a662a | 8417 | if (rc) { |
523224a3 | 8418 | BNX2X_ERR("Function stop failed!\n"); |
da5a662a | 8419 | #ifdef BNX2X_STOP_ON_ERROR |
523224a3 | 8420 | return; |
523224a3 | 8421 | #endif |
34f80b04 | 8422 | } |
a2fbb9ea | 8423 | |
523224a3 DK |
8424 | /* Disable HW interrupts, NAPI */ |
8425 | bnx2x_netif_stop(bp, 1); | |
8426 | ||
8427 | /* Release IRQs */ | |
d6214d7a | 8428 | bnx2x_free_irq(bp); |
523224a3 | 8429 | |
a2fbb9ea | 8430 | /* Reset the chip */ |
619c5cb6 VZ |
8431 | rc = bnx2x_reset_hw(bp, reset_code); |
8432 | if (rc) | |
8433 | BNX2X_ERR("HW_RESET failed\n"); | |
a2fbb9ea | 8434 | |
356e2385 | 8435 | |
619c5cb6 VZ |
8436 | /* Report UNLOAD_DONE to MCP */ |
8437 | bnx2x_send_unload_done(bp); | |
72fd0718 VZ |
8438 | } |
8439 | ||
9f6c9258 | 8440 | void bnx2x_disable_close_the_gate(struct bnx2x *bp) |
72fd0718 VZ |
8441 | { |
8442 | u32 val; | |
8443 | ||
51c1a580 | 8444 | DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); |
72fd0718 VZ |
8445 | |
8446 | if (CHIP_IS_E1(bp)) { | |
8447 | int port = BP_PORT(bp); | |
8448 | u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
8449 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
8450 | ||
8451 | val = REG_RD(bp, addr); | |
8452 | val &= ~(0x300); | |
8453 | REG_WR(bp, addr, val); | |
619c5cb6 | 8454 | } else { |
72fd0718 VZ |
8455 | val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); |
8456 | val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | | |
8457 | MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); | |
8458 | REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); | |
8459 | } | |
8460 | } | |
8461 | ||
72fd0718 VZ |
8462 | /* Close gates #2, #3 and #4: */ |
8463 | static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) | |
8464 | { | |
c9ee9206 | 8465 | u32 val; |
72fd0718 VZ |
8466 | |
8467 | /* Gates #2 and #4a are closed/opened for "not E1" only */ | |
8468 | if (!CHIP_IS_E1(bp)) { | |
8469 | /* #4 */ | |
c9ee9206 | 8470 | REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); |
72fd0718 | 8471 | /* #2 */ |
c9ee9206 | 8472 | REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); |
72fd0718 VZ |
8473 | } |
8474 | ||
8475 | /* #3 */ | |
c9ee9206 VZ |
8476 | if (CHIP_IS_E1x(bp)) { |
8477 | /* Prevent interrupts from HC on both ports */ | |
8478 | val = REG_RD(bp, HC_REG_CONFIG_1); | |
8479 | REG_WR(bp, HC_REG_CONFIG_1, | |
8480 | (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : | |
8481 | (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); | |
8482 | ||
8483 | val = REG_RD(bp, HC_REG_CONFIG_0); | |
8484 | REG_WR(bp, HC_REG_CONFIG_0, | |
8485 | (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : | |
8486 | (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); | |
8487 | } else { | |
8488 | /* Prevent incomming interrupts in IGU */ | |
8489 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); | |
8490 | ||
8491 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, | |
8492 | (!close) ? | |
8493 | (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : | |
8494 | (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); | |
8495 | } | |
72fd0718 | 8496 | |
51c1a580 | 8497 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", |
72fd0718 VZ |
8498 | close ? "closing" : "opening"); |
8499 | mmiowb(); | |
8500 | } | |
8501 | ||
8502 | #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ | |
8503 | ||
8504 | static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) | |
8505 | { | |
8506 | /* Do some magic... */ | |
8507 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); | |
8508 | *magic_val = val & SHARED_MF_CLP_MAGIC; | |
8509 | MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); | |
8510 | } | |
8511 | ||
e8920674 DK |
8512 | /** |
8513 | * bnx2x_clp_reset_done - restore the value of the `magic' bit. | |
72fd0718 | 8514 | * |
e8920674 DK |
8515 | * @bp: driver handle |
8516 | * @magic_val: old value of the `magic' bit. | |
72fd0718 VZ |
8517 | */ |
8518 | static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) | |
8519 | { | |
8520 | /* Restore the `magic' bit value... */ | |
72fd0718 VZ |
8521 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
8522 | MF_CFG_WR(bp, shared_mf_config.clp_mb, | |
8523 | (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); | |
8524 | } | |
8525 | ||
f85582f8 | 8526 | /** |
e8920674 | 8527 | * bnx2x_reset_mcp_prep - prepare for MCP reset. |
72fd0718 | 8528 | * |
e8920674 DK |
8529 | * @bp: driver handle |
8530 | * @magic_val: old value of 'magic' bit. | |
8531 | * | |
8532 | * Takes care of CLP configurations. | |
72fd0718 VZ |
8533 | */ |
8534 | static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) | |
8535 | { | |
8536 | u32 shmem; | |
8537 | u32 validity_offset; | |
8538 | ||
51c1a580 | 8539 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); |
72fd0718 VZ |
8540 | |
8541 | /* Set `magic' bit in order to save MF config */ | |
8542 | if (!CHIP_IS_E1(bp)) | |
8543 | bnx2x_clp_reset_prep(bp, magic_val); | |
8544 | ||
8545 | /* Get shmem offset */ | |
8546 | shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
8547 | validity_offset = offsetof(struct shmem_region, validity_map[0]); | |
8548 | ||
8549 | /* Clear validity map flags */ | |
8550 | if (shmem > 0) | |
8551 | REG_WR(bp, shmem + validity_offset, 0); | |
8552 | } | |
8553 | ||
8554 | #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ | |
8555 | #define MCP_ONE_TIMEOUT 100 /* 100 ms */ | |
8556 | ||
e8920674 DK |
8557 | /** |
8558 | * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT | |
72fd0718 | 8559 | * |
e8920674 | 8560 | * @bp: driver handle |
72fd0718 | 8561 | */ |
1191cb83 | 8562 | static void bnx2x_mcp_wait_one(struct bnx2x *bp) |
72fd0718 VZ |
8563 | { |
8564 | /* special handling for emulation and FPGA, | |
8565 | wait 10 times longer */ | |
8566 | if (CHIP_REV_IS_SLOW(bp)) | |
8567 | msleep(MCP_ONE_TIMEOUT*10); | |
8568 | else | |
8569 | msleep(MCP_ONE_TIMEOUT); | |
8570 | } | |
8571 | ||
1b6e2ceb DK |
8572 | /* |
8573 | * initializes bp->common.shmem_base and waits for validity signature to appear | |
8574 | */ | |
8575 | static int bnx2x_init_shmem(struct bnx2x *bp) | |
72fd0718 | 8576 | { |
1b6e2ceb DK |
8577 | int cnt = 0; |
8578 | u32 val = 0; | |
72fd0718 | 8579 | |
1b6e2ceb DK |
8580 | do { |
8581 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
8582 | if (bp->common.shmem_base) { | |
8583 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
8584 | if (val & SHR_MEM_VALIDITY_MB) | |
8585 | return 0; | |
8586 | } | |
72fd0718 | 8587 | |
1b6e2ceb | 8588 | bnx2x_mcp_wait_one(bp); |
72fd0718 | 8589 | |
1b6e2ceb | 8590 | } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); |
72fd0718 | 8591 | |
1b6e2ceb | 8592 | BNX2X_ERR("BAD MCP validity signature\n"); |
72fd0718 | 8593 | |
1b6e2ceb DK |
8594 | return -ENODEV; |
8595 | } | |
72fd0718 | 8596 | |
1b6e2ceb DK |
8597 | static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) |
8598 | { | |
8599 | int rc = bnx2x_init_shmem(bp); | |
72fd0718 | 8600 | |
72fd0718 VZ |
8601 | /* Restore the `magic' bit value */ |
8602 | if (!CHIP_IS_E1(bp)) | |
8603 | bnx2x_clp_reset_done(bp, magic_val); | |
8604 | ||
8605 | return rc; | |
8606 | } | |
8607 | ||
8608 | static void bnx2x_pxp_prep(struct bnx2x *bp) | |
8609 | { | |
8610 | if (!CHIP_IS_E1(bp)) { | |
8611 | REG_WR(bp, PXP2_REG_RD_START_INIT, 0); | |
8612 | REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); | |
72fd0718 VZ |
8613 | mmiowb(); |
8614 | } | |
8615 | } | |
8616 | ||
8617 | /* | |
8618 | * Reset the whole chip except for: | |
8619 | * - PCIE core | |
8620 | * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by | |
8621 | * one reset bit) | |
8622 | * - IGU | |
8623 | * - MISC (including AEU) | |
8624 | * - GRC | |
8625 | * - RBCN, RBCP | |
8626 | */ | |
c9ee9206 | 8627 | static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) |
72fd0718 VZ |
8628 | { |
8629 | u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; | |
8736c826 | 8630 | u32 global_bits2, stay_reset2; |
c9ee9206 VZ |
8631 | |
8632 | /* | |
8633 | * Bits that have to be set in reset_mask2 if we want to reset 'global' | |
8634 | * (per chip) blocks. | |
8635 | */ | |
8636 | global_bits2 = | |
8637 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | | |
8638 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; | |
72fd0718 | 8639 | |
8736c826 | 8640 | /* Don't reset the following blocks */ |
72fd0718 VZ |
8641 | not_reset_mask1 = |
8642 | MISC_REGISTERS_RESET_REG_1_RST_HC | | |
8643 | MISC_REGISTERS_RESET_REG_1_RST_PXPV | | |
8644 | MISC_REGISTERS_RESET_REG_1_RST_PXP; | |
8645 | ||
8646 | not_reset_mask2 = | |
c9ee9206 | 8647 | MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | |
72fd0718 VZ |
8648 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | |
8649 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | | |
8650 | MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | | |
8651 | MISC_REGISTERS_RESET_REG_2_RST_RBCN | | |
8652 | MISC_REGISTERS_RESET_REG_2_RST_GRC | | |
8653 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | | |
8736c826 VZ |
8654 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | |
8655 | MISC_REGISTERS_RESET_REG_2_RST_ATC | | |
8656 | MISC_REGISTERS_RESET_REG_2_PGLC; | |
72fd0718 | 8657 | |
8736c826 VZ |
8658 | /* |
8659 | * Keep the following blocks in reset: | |
8660 | * - all xxMACs are handled by the bnx2x_link code. | |
8661 | */ | |
8662 | stay_reset2 = | |
8663 | MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | | |
8664 | MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | | |
8665 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | | |
8666 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | | |
8667 | MISC_REGISTERS_RESET_REG_2_UMAC0 | | |
8668 | MISC_REGISTERS_RESET_REG_2_UMAC1 | | |
8669 | MISC_REGISTERS_RESET_REG_2_XMAC | | |
8670 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; | |
8671 | ||
8672 | /* Full reset masks according to the chip */ | |
72fd0718 VZ |
8673 | reset_mask1 = 0xffffffff; |
8674 | ||
8675 | if (CHIP_IS_E1(bp)) | |
8676 | reset_mask2 = 0xffff; | |
8736c826 | 8677 | else if (CHIP_IS_E1H(bp)) |
72fd0718 | 8678 | reset_mask2 = 0x1ffff; |
8736c826 VZ |
8679 | else if (CHIP_IS_E2(bp)) |
8680 | reset_mask2 = 0xfffff; | |
8681 | else /* CHIP_IS_E3 */ | |
8682 | reset_mask2 = 0x3ffffff; | |
c9ee9206 VZ |
8683 | |
8684 | /* Don't reset global blocks unless we need to */ | |
8685 | if (!global) | |
8686 | reset_mask2 &= ~global_bits2; | |
8687 | ||
8688 | /* | |
8689 | * In case of attention in the QM, we need to reset PXP | |
8690 | * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM | |
8691 | * because otherwise QM reset would release 'close the gates' shortly | |
8692 | * before resetting the PXP, then the PSWRQ would send a write | |
8693 | * request to PGLUE. Then when PXP is reset, PGLUE would try to | |
8694 | * read the payload data from PSWWR, but PSWWR would not | |
8695 | * respond. The write queue in PGLUE would stuck, dmae commands | |
8696 | * would not return. Therefore it's important to reset the second | |
8697 | * reset register (containing the | |
8698 | * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the | |
8699 | * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM | |
8700 | * bit). | |
8701 | */ | |
72fd0718 VZ |
8702 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
8703 | reset_mask2 & (~not_reset_mask2)); | |
8704 | ||
c9ee9206 VZ |
8705 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
8706 | reset_mask1 & (~not_reset_mask1)); | |
8707 | ||
72fd0718 VZ |
8708 | barrier(); |
8709 | mmiowb(); | |
8710 | ||
8736c826 VZ |
8711 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
8712 | reset_mask2 & (~stay_reset2)); | |
8713 | ||
8714 | barrier(); | |
8715 | mmiowb(); | |
8716 | ||
c9ee9206 | 8717 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); |
72fd0718 VZ |
8718 | mmiowb(); |
8719 | } | |
8720 | ||
c9ee9206 VZ |
8721 | /** |
8722 | * bnx2x_er_poll_igu_vq - poll for pending writes bit. | |
8723 | * It should get cleared in no more than 1s. | |
8724 | * | |
8725 | * @bp: driver handle | |
8726 | * | |
8727 | * It should get cleared in no more than 1s. Returns 0 if | |
8728 | * pending writes bit gets cleared. | |
8729 | */ | |
8730 | static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) | |
8731 | { | |
8732 | u32 cnt = 1000; | |
8733 | u32 pend_bits = 0; | |
8734 | ||
8735 | do { | |
8736 | pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); | |
8737 | ||
8738 | if (pend_bits == 0) | |
8739 | break; | |
8740 | ||
8741 | usleep_range(1000, 1000); | |
8742 | } while (cnt-- > 0); | |
8743 | ||
8744 | if (cnt <= 0) { | |
8745 | BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", | |
8746 | pend_bits); | |
8747 | return -EBUSY; | |
8748 | } | |
8749 | ||
8750 | return 0; | |
8751 | } | |
8752 | ||
8753 | static int bnx2x_process_kill(struct bnx2x *bp, bool global) | |
72fd0718 VZ |
8754 | { |
8755 | int cnt = 1000; | |
8756 | u32 val = 0; | |
8757 | u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; | |
8758 | ||
8759 | ||
8760 | /* Empty the Tetris buffer, wait for 1s */ | |
8761 | do { | |
8762 | sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); | |
8763 | blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); | |
8764 | port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); | |
8765 | port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); | |
8766 | pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); | |
8767 | if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && | |
8768 | ((port_is_idle_0 & 0x1) == 0x1) && | |
8769 | ((port_is_idle_1 & 0x1) == 0x1) && | |
8770 | (pgl_exp_rom2 == 0xffffffff)) | |
8771 | break; | |
c9ee9206 | 8772 | usleep_range(1000, 1000); |
72fd0718 VZ |
8773 | } while (cnt-- > 0); |
8774 | ||
8775 | if (cnt <= 0) { | |
51c1a580 MS |
8776 | BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); |
8777 | BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", | |
72fd0718 VZ |
8778 | sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, |
8779 | pgl_exp_rom2); | |
8780 | return -EAGAIN; | |
8781 | } | |
8782 | ||
8783 | barrier(); | |
8784 | ||
8785 | /* Close gates #2, #3 and #4 */ | |
8786 | bnx2x_set_234_gates(bp, true); | |
8787 | ||
c9ee9206 VZ |
8788 | /* Poll for IGU VQs for 57712 and newer chips */ |
8789 | if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) | |
8790 | return -EAGAIN; | |
8791 | ||
8792 | ||
72fd0718 VZ |
8793 | /* TBD: Indicate that "process kill" is in progress to MCP */ |
8794 | ||
8795 | /* Clear "unprepared" bit */ | |
8796 | REG_WR(bp, MISC_REG_UNPREPARED, 0); | |
8797 | barrier(); | |
8798 | ||
8799 | /* Make sure all is written to the chip before the reset */ | |
8800 | mmiowb(); | |
8801 | ||
8802 | /* Wait for 1ms to empty GLUE and PCI-E core queues, | |
8803 | * PSWHST, GRC and PSWRD Tetris buffer. | |
8804 | */ | |
c9ee9206 | 8805 | usleep_range(1000, 1000); |
72fd0718 VZ |
8806 | |
8807 | /* Prepare to chip reset: */ | |
8808 | /* MCP */ | |
c9ee9206 VZ |
8809 | if (global) |
8810 | bnx2x_reset_mcp_prep(bp, &val); | |
72fd0718 VZ |
8811 | |
8812 | /* PXP */ | |
8813 | bnx2x_pxp_prep(bp); | |
8814 | barrier(); | |
8815 | ||
8816 | /* reset the chip */ | |
c9ee9206 | 8817 | bnx2x_process_kill_chip_reset(bp, global); |
72fd0718 VZ |
8818 | barrier(); |
8819 | ||
8820 | /* Recover after reset: */ | |
8821 | /* MCP */ | |
c9ee9206 | 8822 | if (global && bnx2x_reset_mcp_comp(bp, val)) |
72fd0718 VZ |
8823 | return -EAGAIN; |
8824 | ||
c9ee9206 VZ |
8825 | /* TBD: Add resetting the NO_MCP mode DB here */ |
8826 | ||
72fd0718 VZ |
8827 | /* PXP */ |
8828 | bnx2x_pxp_prep(bp); | |
8829 | ||
8830 | /* Open the gates #2, #3 and #4 */ | |
8831 | bnx2x_set_234_gates(bp, false); | |
8832 | ||
8833 | /* TBD: IGU/AEU preparation bring back the AEU/IGU to a | |
8834 | * reset state, re-enable attentions. */ | |
8835 | ||
a2fbb9ea ET |
8836 | return 0; |
8837 | } | |
8838 | ||
c9ee9206 | 8839 | int bnx2x_leader_reset(struct bnx2x *bp) |
72fd0718 VZ |
8840 | { |
8841 | int rc = 0; | |
c9ee9206 | 8842 | bool global = bnx2x_reset_is_global(bp); |
95c6c616 AE |
8843 | u32 load_code; |
8844 | ||
8845 | /* if not going to reset MCP - load "fake" driver to reset HW while | |
8846 | * driver is owner of the HW | |
8847 | */ | |
8848 | if (!global && !BP_NOMCP(bp)) { | |
8849 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0); | |
8850 | if (!load_code) { | |
8851 | BNX2X_ERR("MCP response failure, aborting\n"); | |
8852 | rc = -EAGAIN; | |
8853 | goto exit_leader_reset; | |
8854 | } | |
8855 | if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && | |
8856 | (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { | |
8857 | BNX2X_ERR("MCP unexpected resp, aborting\n"); | |
8858 | rc = -EAGAIN; | |
8859 | goto exit_leader_reset2; | |
8860 | } | |
8861 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); | |
8862 | if (!load_code) { | |
8863 | BNX2X_ERR("MCP response failure, aborting\n"); | |
8864 | rc = -EAGAIN; | |
8865 | goto exit_leader_reset2; | |
8866 | } | |
8867 | } | |
c9ee9206 | 8868 | |
72fd0718 | 8869 | /* Try to recover after the failure */ |
c9ee9206 | 8870 | if (bnx2x_process_kill(bp, global)) { |
51c1a580 MS |
8871 | BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", |
8872 | BP_PATH(bp)); | |
72fd0718 | 8873 | rc = -EAGAIN; |
95c6c616 | 8874 | goto exit_leader_reset2; |
72fd0718 VZ |
8875 | } |
8876 | ||
c9ee9206 VZ |
8877 | /* |
8878 | * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver | |
8879 | * state. | |
8880 | */ | |
72fd0718 | 8881 | bnx2x_set_reset_done(bp); |
c9ee9206 VZ |
8882 | if (global) |
8883 | bnx2x_clear_reset_global(bp); | |
72fd0718 | 8884 | |
95c6c616 AE |
8885 | exit_leader_reset2: |
8886 | /* unload "fake driver" if it was loaded */ | |
8887 | if (!global && !BP_NOMCP(bp)) { | |
8888 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); | |
8889 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
8890 | } | |
72fd0718 VZ |
8891 | exit_leader_reset: |
8892 | bp->is_leader = 0; | |
c9ee9206 VZ |
8893 | bnx2x_release_leader_lock(bp); |
8894 | smp_mb(); | |
72fd0718 VZ |
8895 | return rc; |
8896 | } | |
8897 | ||
1191cb83 | 8898 | static void bnx2x_recovery_failed(struct bnx2x *bp) |
c9ee9206 VZ |
8899 | { |
8900 | netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); | |
8901 | ||
8902 | /* Disconnect this device */ | |
8903 | netif_device_detach(bp->dev); | |
8904 | ||
8905 | /* | |
8906 | * Block ifup for all function on this engine until "process kill" | |
8907 | * or power cycle. | |
8908 | */ | |
8909 | bnx2x_set_reset_in_progress(bp); | |
8910 | ||
8911 | /* Shut down the power */ | |
8912 | bnx2x_set_power_state(bp, PCI_D3hot); | |
8913 | ||
8914 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
8915 | ||
8916 | smp_mb(); | |
8917 | } | |
8918 | ||
8919 | /* | |
8920 | * Assumption: runs under rtnl lock. This together with the fact | |
6383c0b3 | 8921 | * that it's called only from bnx2x_sp_rtnl() ensure that it |
72fd0718 VZ |
8922 | * will never be called when netif_running(bp->dev) is false. |
8923 | */ | |
8924 | static void bnx2x_parity_recover(struct bnx2x *bp) | |
8925 | { | |
c9ee9206 | 8926 | bool global = false; |
7a752993 | 8927 | u32 error_recovered, error_unrecovered; |
95c6c616 | 8928 | bool is_parity; |
c9ee9206 | 8929 | |
72fd0718 VZ |
8930 | DP(NETIF_MSG_HW, "Handling parity\n"); |
8931 | while (1) { | |
8932 | switch (bp->recovery_state) { | |
8933 | case BNX2X_RECOVERY_INIT: | |
8934 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); | |
95c6c616 AE |
8935 | is_parity = bnx2x_chk_parity_attn(bp, &global, false); |
8936 | WARN_ON(!is_parity); | |
c9ee9206 | 8937 | |
72fd0718 | 8938 | /* Try to get a LEADER_LOCK HW lock */ |
c9ee9206 VZ |
8939 | if (bnx2x_trylock_leader_lock(bp)) { |
8940 | bnx2x_set_reset_in_progress(bp); | |
8941 | /* | |
8942 | * Check if there is a global attention and if | |
8943 | * there was a global attention, set the global | |
8944 | * reset bit. | |
8945 | */ | |
8946 | ||
8947 | if (global) | |
8948 | bnx2x_set_reset_global(bp); | |
8949 | ||
72fd0718 | 8950 | bp->is_leader = 1; |
c9ee9206 | 8951 | } |
72fd0718 VZ |
8952 | |
8953 | /* Stop the driver */ | |
8954 | /* If interface has been removed - break */ | |
8955 | if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) | |
8956 | return; | |
8957 | ||
8958 | bp->recovery_state = BNX2X_RECOVERY_WAIT; | |
c9ee9206 | 8959 | |
c9ee9206 VZ |
8960 | /* Ensure "is_leader", MCP command sequence and |
8961 | * "recovery_state" update values are seen on other | |
8962 | * CPUs. | |
72fd0718 | 8963 | */ |
c9ee9206 | 8964 | smp_mb(); |
72fd0718 VZ |
8965 | break; |
8966 | ||
8967 | case BNX2X_RECOVERY_WAIT: | |
8968 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); | |
8969 | if (bp->is_leader) { | |
c9ee9206 | 8970 | int other_engine = BP_PATH(bp) ? 0 : 1; |
889b9af3 AE |
8971 | bool other_load_status = |
8972 | bnx2x_get_load_status(bp, other_engine); | |
8973 | bool load_status = | |
8974 | bnx2x_get_load_status(bp, BP_PATH(bp)); | |
c9ee9206 VZ |
8975 | global = bnx2x_reset_is_global(bp); |
8976 | ||
8977 | /* | |
8978 | * In case of a parity in a global block, let | |
8979 | * the first leader that performs a | |
8980 | * leader_reset() reset the global blocks in | |
8981 | * order to clear global attentions. Otherwise | |
8982 | * the the gates will remain closed for that | |
8983 | * engine. | |
8984 | */ | |
889b9af3 AE |
8985 | if (load_status || |
8986 | (global && other_load_status)) { | |
72fd0718 VZ |
8987 | /* Wait until all other functions get |
8988 | * down. | |
8989 | */ | |
7be08a72 | 8990 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
8991 | HZ/10); |
8992 | return; | |
8993 | } else { | |
8994 | /* If all other functions got down - | |
8995 | * try to bring the chip back to | |
8996 | * normal. In any case it's an exit | |
8997 | * point for a leader. | |
8998 | */ | |
c9ee9206 VZ |
8999 | if (bnx2x_leader_reset(bp)) { |
9000 | bnx2x_recovery_failed(bp); | |
72fd0718 VZ |
9001 | return; |
9002 | } | |
9003 | ||
c9ee9206 VZ |
9004 | /* If we are here, means that the |
9005 | * leader has succeeded and doesn't | |
9006 | * want to be a leader any more. Try | |
9007 | * to continue as a none-leader. | |
9008 | */ | |
9009 | break; | |
72fd0718 VZ |
9010 | } |
9011 | } else { /* non-leader */ | |
c9ee9206 | 9012 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { |
72fd0718 VZ |
9013 | /* Try to get a LEADER_LOCK HW lock as |
9014 | * long as a former leader may have | |
9015 | * been unloaded by the user or | |
9016 | * released a leadership by another | |
9017 | * reason. | |
9018 | */ | |
c9ee9206 | 9019 | if (bnx2x_trylock_leader_lock(bp)) { |
72fd0718 VZ |
9020 | /* I'm a leader now! Restart a |
9021 | * switch case. | |
9022 | */ | |
9023 | bp->is_leader = 1; | |
9024 | break; | |
9025 | } | |
9026 | ||
7be08a72 | 9027 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
9028 | HZ/10); |
9029 | return; | |
9030 | ||
c9ee9206 VZ |
9031 | } else { |
9032 | /* | |
9033 | * If there was a global attention, wait | |
9034 | * for it to be cleared. | |
9035 | */ | |
9036 | if (bnx2x_reset_is_global(bp)) { | |
9037 | schedule_delayed_work( | |
7be08a72 AE |
9038 | &bp->sp_rtnl_task, |
9039 | HZ/10); | |
c9ee9206 VZ |
9040 | return; |
9041 | } | |
9042 | ||
7a752993 AE |
9043 | error_recovered = |
9044 | bp->eth_stats.recoverable_error; | |
9045 | error_unrecovered = | |
9046 | bp->eth_stats.unrecoverable_error; | |
95c6c616 AE |
9047 | bp->recovery_state = |
9048 | BNX2X_RECOVERY_NIC_LOADING; | |
9049 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) { | |
7a752993 | 9050 | error_unrecovered++; |
95c6c616 | 9051 | netdev_err(bp->dev, |
51c1a580 | 9052 | "Recovery failed. Power cycle needed\n"); |
95c6c616 AE |
9053 | /* Disconnect this device */ |
9054 | netif_device_detach(bp->dev); | |
9055 | /* Shut down the power */ | |
9056 | bnx2x_set_power_state( | |
9057 | bp, PCI_D3hot); | |
9058 | smp_mb(); | |
9059 | } else { | |
c9ee9206 VZ |
9060 | bp->recovery_state = |
9061 | BNX2X_RECOVERY_DONE; | |
7a752993 | 9062 | error_recovered++; |
c9ee9206 VZ |
9063 | smp_mb(); |
9064 | } | |
7a752993 AE |
9065 | bp->eth_stats.recoverable_error = |
9066 | error_recovered; | |
9067 | bp->eth_stats.unrecoverable_error = | |
9068 | error_unrecovered; | |
c9ee9206 | 9069 | |
72fd0718 VZ |
9070 | return; |
9071 | } | |
9072 | } | |
9073 | default: | |
9074 | return; | |
9075 | } | |
9076 | } | |
9077 | } | |
9078 | ||
56ad3152 MS |
9079 | static int bnx2x_close(struct net_device *dev); |
9080 | ||
72fd0718 VZ |
9081 | /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is |
9082 | * scheduled on a general queue in order to prevent a dead lock. | |
9083 | */ | |
7be08a72 | 9084 | static void bnx2x_sp_rtnl_task(struct work_struct *work) |
34f80b04 | 9085 | { |
7be08a72 | 9086 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); |
34f80b04 EG |
9087 | |
9088 | rtnl_lock(); | |
9089 | ||
9090 | if (!netif_running(bp->dev)) | |
7be08a72 AE |
9091 | goto sp_rtnl_exit; |
9092 | ||
9093 | /* if stop on error is defined no recovery flows should be executed */ | |
9094 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 9095 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" |
7be08a72 | 9096 | "you will need to reboot when done\n"); |
b1fb8740 | 9097 | goto sp_rtnl_not_reset; |
7be08a72 | 9098 | #endif |
34f80b04 | 9099 | |
7be08a72 AE |
9100 | if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { |
9101 | /* | |
b1fb8740 VZ |
9102 | * Clear all pending SP commands as we are going to reset the |
9103 | * function anyway. | |
7be08a72 | 9104 | */ |
b1fb8740 VZ |
9105 | bp->sp_rtnl_state = 0; |
9106 | smp_mb(); | |
9107 | ||
72fd0718 | 9108 | bnx2x_parity_recover(bp); |
b1fb8740 VZ |
9109 | |
9110 | goto sp_rtnl_exit; | |
9111 | } | |
9112 | ||
9113 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { | |
9114 | /* | |
9115 | * Clear all pending SP commands as we are going to reset the | |
9116 | * function anyway. | |
9117 | */ | |
9118 | bp->sp_rtnl_state = 0; | |
9119 | smp_mb(); | |
9120 | ||
72fd0718 VZ |
9121 | bnx2x_nic_unload(bp, UNLOAD_NORMAL); |
9122 | bnx2x_nic_load(bp, LOAD_NORMAL); | |
b1fb8740 VZ |
9123 | |
9124 | goto sp_rtnl_exit; | |
72fd0718 | 9125 | } |
b1fb8740 VZ |
9126 | #ifdef BNX2X_STOP_ON_ERROR |
9127 | sp_rtnl_not_reset: | |
9128 | #endif | |
9129 | if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) | |
9130 | bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); | |
a3348722 BW |
9131 | if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) |
9132 | bnx2x_after_function_update(bp); | |
8304859a AE |
9133 | /* |
9134 | * in case of fan failure we need to reset id if the "stop on error" | |
9135 | * debug flag is set, since we trying to prevent permanent overheating | |
9136 | * damage | |
9137 | */ | |
9138 | if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { | |
51c1a580 | 9139 | DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); |
8304859a AE |
9140 | netif_device_detach(bp->dev); |
9141 | bnx2x_close(bp->dev); | |
9142 | } | |
9143 | ||
7be08a72 | 9144 | sp_rtnl_exit: |
34f80b04 EG |
9145 | rtnl_unlock(); |
9146 | } | |
9147 | ||
a2fbb9ea ET |
9148 | /* end of nic load/unload */ |
9149 | ||
3deb8167 YR |
9150 | static void bnx2x_period_task(struct work_struct *work) |
9151 | { | |
9152 | struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); | |
9153 | ||
9154 | if (!netif_running(bp->dev)) | |
9155 | goto period_task_exit; | |
9156 | ||
9157 | if (CHIP_REV_IS_SLOW(bp)) { | |
9158 | BNX2X_ERR("period task called on emulation, ignoring\n"); | |
9159 | goto period_task_exit; | |
9160 | } | |
9161 | ||
9162 | bnx2x_acquire_phy_lock(bp); | |
9163 | /* | |
9164 | * The barrier is needed to ensure the ordering between the writing to | |
9165 | * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and | |
9166 | * the reading here. | |
9167 | */ | |
9168 | smp_mb(); | |
9169 | if (bp->port.pmf) { | |
9170 | bnx2x_period_func(&bp->link_params, &bp->link_vars); | |
9171 | ||
9172 | /* Re-queue task in 1 sec */ | |
9173 | queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); | |
9174 | } | |
9175 | ||
9176 | bnx2x_release_phy_lock(bp); | |
9177 | period_task_exit: | |
9178 | return; | |
9179 | } | |
9180 | ||
a2fbb9ea ET |
9181 | /* |
9182 | * Init service functions | |
9183 | */ | |
9184 | ||
8d96286a | 9185 | static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) |
f2e0899f DK |
9186 | { |
9187 | u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
9188 | u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; | |
9189 | return base + (BP_ABS_FUNC(bp)) * stride; | |
f1ef27ef EG |
9190 | } |
9191 | ||
f2e0899f | 9192 | static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) |
f1ef27ef | 9193 | { |
f2e0899f | 9194 | u32 reg = bnx2x_get_pretend_reg(bp); |
f1ef27ef EG |
9195 | |
9196 | /* Flush all outstanding writes */ | |
9197 | mmiowb(); | |
9198 | ||
9199 | /* Pretend to be function 0 */ | |
9200 | REG_WR(bp, reg, 0); | |
f2e0899f | 9201 | REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ |
f1ef27ef EG |
9202 | |
9203 | /* From now we are in the "like-E1" mode */ | |
9204 | bnx2x_int_disable(bp); | |
9205 | ||
9206 | /* Flush all outstanding writes */ | |
9207 | mmiowb(); | |
9208 | ||
f2e0899f DK |
9209 | /* Restore the original function */ |
9210 | REG_WR(bp, reg, BP_ABS_FUNC(bp)); | |
9211 | REG_RD(bp, reg); | |
f1ef27ef EG |
9212 | } |
9213 | ||
f2e0899f | 9214 | static inline void bnx2x_undi_int_disable(struct bnx2x *bp) |
f1ef27ef | 9215 | { |
f2e0899f | 9216 | if (CHIP_IS_E1(bp)) |
f1ef27ef | 9217 | bnx2x_int_disable(bp); |
f2e0899f DK |
9218 | else |
9219 | bnx2x_undi_int_disable_e1h(bp); | |
f1ef27ef EG |
9220 | } |
9221 | ||
452427b0 | 9222 | static void __devinit bnx2x_prev_unload_close_mac(struct bnx2x *bp) |
34f80b04 | 9223 | { |
452427b0 YM |
9224 | u32 val, base_addr, offset, mask, reset_reg; |
9225 | bool mac_stopped = false; | |
9226 | u8 port = BP_PORT(bp); | |
34f80b04 | 9227 | |
452427b0 | 9228 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); |
f16da43b | 9229 | |
452427b0 YM |
9230 | if (!CHIP_IS_E3(bp)) { |
9231 | val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); | |
9232 | mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; | |
9233 | if ((mask & reset_reg) && val) { | |
9234 | u32 wb_data[2]; | |
9235 | BNX2X_DEV_INFO("Disable bmac Rx\n"); | |
9236 | base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM | |
9237 | : NIG_REG_INGRESS_BMAC0_MEM; | |
9238 | offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL | |
9239 | : BIGMAC_REGISTER_BMAC_CONTROL; | |
7a06a122 | 9240 | |
452427b0 YM |
9241 | /* |
9242 | * use rd/wr since we cannot use dmae. This is safe | |
9243 | * since MCP won't access the bus due to the request | |
9244 | * to unload, and no function on the path can be | |
9245 | * loaded at this time. | |
9246 | */ | |
9247 | wb_data[0] = REG_RD(bp, base_addr + offset); | |
9248 | wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); | |
9249 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; | |
9250 | REG_WR(bp, base_addr + offset, wb_data[0]); | |
9251 | REG_WR(bp, base_addr + offset + 0x4, wb_data[1]); | |
9252 | ||
9253 | } | |
9254 | BNX2X_DEV_INFO("Disable emac Rx\n"); | |
9255 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0); | |
9256 | ||
9257 | mac_stopped = true; | |
9258 | } else { | |
9259 | if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { | |
9260 | BNX2X_DEV_INFO("Disable xmac Rx\n"); | |
9261 | base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
9262 | val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); | |
9263 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
9264 | val & ~(1 << 1)); | |
9265 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
9266 | val | (1 << 1)); | |
9267 | REG_WR(bp, base_addr + XMAC_REG_CTRL, 0); | |
9268 | mac_stopped = true; | |
9269 | } | |
9270 | mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; | |
9271 | if (mask & reset_reg) { | |
9272 | BNX2X_DEV_INFO("Disable umac Rx\n"); | |
9273 | base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
9274 | REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0); | |
9275 | mac_stopped = true; | |
9276 | } | |
9277 | } | |
9278 | ||
9279 | if (mac_stopped) | |
9280 | msleep(20); | |
9281 | ||
9282 | } | |
9283 | ||
9284 | #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) | |
9285 | #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) | |
9286 | #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) | |
9287 | #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) | |
9288 | ||
9289 | static void __devinit bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, | |
9290 | u8 inc) | |
9291 | { | |
9292 | u16 rcq, bd; | |
9293 | u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port)); | |
9294 | ||
9295 | rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; | |
9296 | bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; | |
9297 | ||
9298 | tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); | |
9299 | REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg); | |
9300 | ||
9301 | BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n", | |
9302 | port, bd, rcq); | |
9303 | } | |
9304 | ||
9305 | static int __devinit bnx2x_prev_mcp_done(struct bnx2x *bp) | |
9306 | { | |
9307 | u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
9308 | if (!rc) { | |
9309 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9310 | return -EBUSY; | |
9311 | } | |
9312 | ||
9313 | return 0; | |
9314 | } | |
9315 | ||
9316 | static bool __devinit bnx2x_prev_is_path_marked(struct bnx2x *bp) | |
9317 | { | |
9318 | struct bnx2x_prev_path_list *tmp_list; | |
9319 | int rc = false; | |
9320 | ||
9321 | if (down_trylock(&bnx2x_prev_sem)) | |
9322 | return false; | |
9323 | ||
9324 | list_for_each_entry(tmp_list, &bnx2x_prev_list, list) { | |
9325 | if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && | |
9326 | bp->pdev->bus->number == tmp_list->bus && | |
9327 | BP_PATH(bp) == tmp_list->path) { | |
9328 | rc = true; | |
9329 | BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", | |
9330 | BP_PATH(bp)); | |
9331 | break; | |
9332 | } | |
9333 | } | |
9334 | ||
9335 | up(&bnx2x_prev_sem); | |
9336 | ||
9337 | return rc; | |
9338 | } | |
9339 | ||
9340 | static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp) | |
9341 | { | |
9342 | struct bnx2x_prev_path_list *tmp_list; | |
9343 | int rc; | |
9344 | ||
9345 | tmp_list = (struct bnx2x_prev_path_list *) | |
9346 | kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); | |
9347 | if (!tmp_list) { | |
9348 | BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); | |
9349 | return -ENOMEM; | |
9350 | } | |
9351 | ||
9352 | tmp_list->bus = bp->pdev->bus->number; | |
9353 | tmp_list->slot = PCI_SLOT(bp->pdev->devfn); | |
9354 | tmp_list->path = BP_PATH(bp); | |
9355 | ||
9356 | rc = down_interruptible(&bnx2x_prev_sem); | |
9357 | if (rc) { | |
9358 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
9359 | kfree(tmp_list); | |
9360 | } else { | |
9361 | BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n", | |
9362 | BP_PATH(bp)); | |
9363 | list_add(&tmp_list->list, &bnx2x_prev_list); | |
9364 | up(&bnx2x_prev_sem); | |
9365 | } | |
9366 | ||
9367 | return rc; | |
9368 | } | |
9369 | ||
9370 | static bool __devinit bnx2x_can_flr(struct bnx2x *bp) | |
9371 | { | |
9372 | int pos; | |
9373 | u32 cap; | |
9374 | struct pci_dev *dev = bp->pdev; | |
9375 | ||
9376 | pos = pci_pcie_cap(dev); | |
9377 | if (!pos) | |
9378 | return false; | |
9379 | ||
9380 | pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap); | |
9381 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | |
9382 | return false; | |
9383 | ||
9384 | return true; | |
9385 | } | |
9386 | ||
9387 | static int __devinit bnx2x_do_flr(struct bnx2x *bp) | |
9388 | { | |
9389 | int i, pos; | |
9390 | u16 status; | |
9391 | struct pci_dev *dev = bp->pdev; | |
9392 | ||
9393 | /* probe the capability first */ | |
9394 | if (bnx2x_can_flr(bp)) | |
9395 | return -ENOTTY; | |
9396 | ||
9397 | pos = pci_pcie_cap(dev); | |
9398 | if (!pos) | |
9399 | return -ENOTTY; | |
9400 | ||
9401 | /* Wait for Transaction Pending bit clean */ | |
9402 | for (i = 0; i < 4; i++) { | |
9403 | if (i) | |
9404 | msleep((1 << (i - 1)) * 100); | |
9405 | ||
9406 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); | |
9407 | if (!(status & PCI_EXP_DEVSTA_TRPND)) | |
9408 | goto clear; | |
9409 | } | |
9410 | ||
9411 | dev_err(&dev->dev, | |
9412 | "transaction is not cleared; proceeding with reset anyway\n"); | |
9413 | ||
9414 | clear: | |
9415 | if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { | |
9416 | BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", | |
9417 | bp->common.bc_ver); | |
9418 | return -EINVAL; | |
9419 | } | |
9420 | ||
9421 | bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); | |
9422 | ||
9423 | return 0; | |
9424 | } | |
9425 | ||
9426 | static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp) | |
9427 | { | |
9428 | int rc; | |
9429 | ||
9430 | BNX2X_DEV_INFO("Uncommon unload Flow\n"); | |
9431 | ||
9432 | /* Test if previous unload process was already finished for this path */ | |
9433 | if (bnx2x_prev_is_path_marked(bp)) | |
9434 | return bnx2x_prev_mcp_done(bp); | |
9435 | ||
9436 | /* If function has FLR capabilities, and existing FW version matches | |
9437 | * the one required, then FLR will be sufficient to clean any residue | |
9438 | * left by previous driver | |
9439 | */ | |
9440 | if (bnx2x_test_firmware_version(bp, false) && bnx2x_can_flr(bp)) | |
9441 | return bnx2x_do_flr(bp); | |
9442 | ||
9443 | /* Close the MCP request, return failure*/ | |
9444 | rc = bnx2x_prev_mcp_done(bp); | |
9445 | if (!rc) | |
9446 | rc = BNX2X_PREV_WAIT_NEEDED; | |
9447 | ||
9448 | return rc; | |
9449 | } | |
9450 | ||
9451 | static int __devinit bnx2x_prev_unload_common(struct bnx2x *bp) | |
9452 | { | |
9453 | u32 reset_reg, tmp_reg = 0, rc; | |
9454 | /* It is possible a previous function received 'common' answer, | |
9455 | * but hasn't loaded yet, therefore creating a scenario of | |
9456 | * multiple functions receiving 'common' on the same path. | |
9457 | */ | |
9458 | BNX2X_DEV_INFO("Common unload Flow\n"); | |
9459 | ||
9460 | if (bnx2x_prev_is_path_marked(bp)) | |
9461 | return bnx2x_prev_mcp_done(bp); | |
9462 | ||
9463 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); | |
9464 | ||
9465 | /* Reset should be performed after BRB is emptied */ | |
9466 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { | |
9467 | u32 timer_count = 1000; | |
9468 | bool prev_undi = false; | |
9469 | ||
9470 | /* Close the MAC Rx to prevent BRB from filling up */ | |
9471 | bnx2x_prev_unload_close_mac(bp); | |
9472 | ||
9473 | /* Check if the UNDI driver was previously loaded | |
34f80b04 EG |
9474 | * UNDI driver initializes CID offset for normal bell to 0x7 |
9475 | */ | |
452427b0 YM |
9476 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); |
9477 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { | |
9478 | tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST); | |
9479 | if (tmp_reg == 0x7) { | |
9480 | BNX2X_DEV_INFO("UNDI previously loaded\n"); | |
9481 | prev_undi = true; | |
9482 | /* clear the UNDI indication */ | |
9483 | REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); | |
34f80b04 | 9484 | } |
452427b0 YM |
9485 | } |
9486 | /* wait until BRB is empty */ | |
9487 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); | |
9488 | while (timer_count) { | |
9489 | u32 prev_brb = tmp_reg; | |
34f80b04 | 9490 | |
452427b0 YM |
9491 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); |
9492 | if (!tmp_reg) | |
9493 | break; | |
619c5cb6 | 9494 | |
452427b0 | 9495 | BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); |
619c5cb6 | 9496 | |
452427b0 YM |
9497 | /* reset timer as long as BRB actually gets emptied */ |
9498 | if (prev_brb > tmp_reg) | |
9499 | timer_count = 1000; | |
9500 | else | |
9501 | timer_count--; | |
da5a662a | 9502 | |
452427b0 YM |
9503 | /* If UNDI resides in memory, manually increment it */ |
9504 | if (prev_undi) | |
9505 | bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1); | |
da5a662a | 9506 | |
452427b0 | 9507 | udelay(10); |
7a06a122 | 9508 | } |
452427b0 YM |
9509 | |
9510 | if (!timer_count) | |
9511 | BNX2X_ERR("Failed to empty BRB, hope for the best\n"); | |
9512 | ||
34f80b04 | 9513 | } |
f16da43b | 9514 | |
452427b0 YM |
9515 | /* No packets are in the pipeline, path is ready for reset */ |
9516 | bnx2x_reset_common(bp); | |
9517 | ||
9518 | rc = bnx2x_prev_mark_path(bp); | |
9519 | if (rc) { | |
9520 | bnx2x_prev_mcp_done(bp); | |
9521 | return rc; | |
9522 | } | |
9523 | ||
9524 | return bnx2x_prev_mcp_done(bp); | |
9525 | } | |
9526 | ||
24f06716 AE |
9527 | /* previous driver DMAE transaction may have occurred when pre-boot stage ended |
9528 | * and boot began, or when kdump kernel was loaded. Either case would invalidate | |
9529 | * the addresses of the transaction, resulting in was-error bit set in the pci | |
9530 | * causing all hw-to-host pcie transactions to timeout. If this happened we want | |
9531 | * to clear the interrupt which detected this from the pglueb and the was done | |
9532 | * bit | |
9533 | */ | |
9534 | static void __devinit bnx2x_prev_interrupted_dmae(struct bnx2x *bp) | |
9535 | { | |
9536 | u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS); | |
9537 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) { | |
9538 | BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing"); | |
9539 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << BP_FUNC(bp)); | |
9540 | } | |
9541 | } | |
9542 | ||
452427b0 YM |
9543 | static int __devinit bnx2x_prev_unload(struct bnx2x *bp) |
9544 | { | |
9545 | int time_counter = 10; | |
9546 | u32 rc, fw, hw_lock_reg, hw_lock_val; | |
9547 | BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); | |
9548 | ||
24f06716 AE |
9549 | /* clear hw from errors which may have resulted from an interrupted |
9550 | * dmae transaction. | |
9551 | */ | |
9552 | bnx2x_prev_interrupted_dmae(bp); | |
9553 | ||
9554 | /* Release previously held locks */ | |
452427b0 YM |
9555 | hw_lock_reg = (BP_FUNC(bp) <= 5) ? |
9556 | (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : | |
9557 | (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); | |
9558 | ||
9559 | hw_lock_val = (REG_RD(bp, hw_lock_reg)); | |
9560 | if (hw_lock_val) { | |
9561 | if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { | |
9562 | BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); | |
9563 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
9564 | (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); | |
9565 | } | |
9566 | ||
9567 | BNX2X_DEV_INFO("Release Previously held hw lock\n"); | |
9568 | REG_WR(bp, hw_lock_reg, 0xffffffff); | |
9569 | } else | |
9570 | BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); | |
9571 | ||
9572 | if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { | |
9573 | BNX2X_DEV_INFO("Release previously held alr\n"); | |
9574 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); | |
9575 | } | |
9576 | ||
9577 | ||
9578 | do { | |
9579 | /* Lock MCP using an unload request */ | |
9580 | fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); | |
9581 | if (!fw) { | |
9582 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9583 | rc = -EBUSY; | |
9584 | break; | |
9585 | } | |
9586 | ||
9587 | if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) { | |
9588 | rc = bnx2x_prev_unload_common(bp); | |
9589 | break; | |
9590 | } | |
9591 | ||
9592 | /* non-common reply from MCP night require looping */ | |
9593 | rc = bnx2x_prev_unload_uncommon(bp); | |
9594 | if (rc != BNX2X_PREV_WAIT_NEEDED) | |
9595 | break; | |
9596 | ||
9597 | msleep(20); | |
9598 | } while (--time_counter); | |
9599 | ||
9600 | if (!time_counter || rc) { | |
9601 | BNX2X_ERR("Failed unloading previous driver, aborting\n"); | |
9602 | rc = -EBUSY; | |
9603 | } | |
9604 | ||
9605 | BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); | |
9606 | ||
9607 | return rc; | |
34f80b04 EG |
9608 | } |
9609 | ||
9610 | static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) | |
9611 | { | |
1d187b34 | 9612 | u32 val, val2, val3, val4, id, boot_mode; |
72ce58c3 | 9613 | u16 pmc; |
34f80b04 EG |
9614 | |
9615 | /* Get the chip revision id and number. */ | |
9616 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | |
9617 | val = REG_RD(bp, MISC_REG_CHIP_NUM); | |
9618 | id = ((val & 0xffff) << 16); | |
9619 | val = REG_RD(bp, MISC_REG_CHIP_REV); | |
9620 | id |= ((val & 0xf) << 12); | |
9621 | val = REG_RD(bp, MISC_REG_CHIP_METAL); | |
9622 | id |= ((val & 0xff) << 4); | |
5a40e08e | 9623 | val = REG_RD(bp, MISC_REG_BOND_ID); |
34f80b04 EG |
9624 | id |= (val & 0xf); |
9625 | bp->common.chip_id = id; | |
523224a3 | 9626 | |
7e8e02df BW |
9627 | /* force 57811 according to MISC register */ |
9628 | if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { | |
9629 | if (CHIP_IS_57810(bp)) | |
9630 | bp->common.chip_id = (CHIP_NUM_57811 << 16) | | |
9631 | (bp->common.chip_id & 0x0000FFFF); | |
9632 | else if (CHIP_IS_57810_MF(bp)) | |
9633 | bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | | |
9634 | (bp->common.chip_id & 0x0000FFFF); | |
9635 | bp->common.chip_id |= 0x1; | |
9636 | } | |
9637 | ||
523224a3 DK |
9638 | /* Set doorbell size */ |
9639 | bp->db_size = (1 << BNX2X_DB_SHIFT); | |
9640 | ||
619c5cb6 | 9641 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
9642 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
9643 | if ((val & 1) == 0) | |
9644 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
9645 | else | |
9646 | val = (val >> 1) & 1; | |
9647 | BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : | |
9648 | "2_PORT_MODE"); | |
9649 | bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : | |
9650 | CHIP_2_PORT_MODE; | |
9651 | ||
9652 | if (CHIP_MODE_IS_4_PORT(bp)) | |
9653 | bp->pfid = (bp->pf_num >> 1); /* 0..3 */ | |
9654 | else | |
9655 | bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ | |
9656 | } else { | |
9657 | bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ | |
9658 | bp->pfid = bp->pf_num; /* 0..7 */ | |
9659 | } | |
9660 | ||
51c1a580 MS |
9661 | BNX2X_DEV_INFO("pf_id: %x", bp->pfid); |
9662 | ||
f2e0899f DK |
9663 | bp->link_params.chip_id = bp->common.chip_id; |
9664 | BNX2X_DEV_INFO("chip ID is 0x%x\n", id); | |
523224a3 | 9665 | |
1c06328c EG |
9666 | val = (REG_RD(bp, 0x2874) & 0x55); |
9667 | if ((bp->common.chip_id & 0x1) || | |
9668 | (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { | |
9669 | bp->flags |= ONE_PORT_FLAG; | |
9670 | BNX2X_DEV_INFO("single port device\n"); | |
9671 | } | |
9672 | ||
34f80b04 | 9673 | val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); |
754a2f52 | 9674 | bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << |
34f80b04 EG |
9675 | (val & MCPR_NVM_CFG4_FLASH_SIZE)); |
9676 | BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", | |
9677 | bp->common.flash_size, bp->common.flash_size); | |
9678 | ||
1b6e2ceb DK |
9679 | bnx2x_init_shmem(bp); |
9680 | ||
619c5cb6 VZ |
9681 | |
9682 | ||
f2e0899f DK |
9683 | bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? |
9684 | MISC_REG_GENERIC_CR_1 : | |
9685 | MISC_REG_GENERIC_CR_0)); | |
1b6e2ceb | 9686 | |
34f80b04 | 9687 | bp->link_params.shmem_base = bp->common.shmem_base; |
a22f0788 | 9688 | bp->link_params.shmem2_base = bp->common.shmem2_base; |
2691d51d EG |
9689 | BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", |
9690 | bp->common.shmem_base, bp->common.shmem2_base); | |
34f80b04 | 9691 | |
f2e0899f | 9692 | if (!bp->common.shmem_base) { |
34f80b04 EG |
9693 | BNX2X_DEV_INFO("MCP not active\n"); |
9694 | bp->flags |= NO_MCP_FLAG; | |
9695 | return; | |
9696 | } | |
9697 | ||
34f80b04 | 9698 | bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
35b19ba5 | 9699 | BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); |
34f80b04 EG |
9700 | |
9701 | bp->link_params.hw_led_mode = ((bp->common.hw_config & | |
9702 | SHARED_HW_CFG_LED_MODE_MASK) >> | |
9703 | SHARED_HW_CFG_LED_MODE_SHIFT); | |
9704 | ||
c2c8b03e EG |
9705 | bp->link_params.feature_config_flags = 0; |
9706 | val = SHMEM_RD(bp, dev_info.shared_feature_config.config); | |
9707 | if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) | |
9708 | bp->link_params.feature_config_flags |= | |
9709 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
9710 | else | |
9711 | bp->link_params.feature_config_flags &= | |
9712 | ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
9713 | ||
34f80b04 EG |
9714 | val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; |
9715 | bp->common.bc_ver = val; | |
9716 | BNX2X_DEV_INFO("bc_ver %X\n", val); | |
9717 | if (val < BNX2X_BC_VER) { | |
9718 | /* for now only warn | |
9719 | * later we might need to enforce this */ | |
51c1a580 MS |
9720 | BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", |
9721 | BNX2X_BC_VER, val); | |
34f80b04 | 9722 | } |
4d295db0 | 9723 | bp->link_params.feature_config_flags |= |
a22f0788 | 9724 | (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? |
f85582f8 DK |
9725 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; |
9726 | ||
a22f0788 YR |
9727 | bp->link_params.feature_config_flags |= |
9728 | (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? | |
9729 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; | |
a3348722 BW |
9730 | bp->link_params.feature_config_flags |= |
9731 | (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? | |
9732 | FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; | |
85242eea YR |
9733 | bp->link_params.feature_config_flags |= |
9734 | (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? | |
9735 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; | |
0e898dd7 BW |
9736 | bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? |
9737 | BC_SUPPORTS_PFC_STATS : 0; | |
85242eea | 9738 | |
2e499d3c BW |
9739 | bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? |
9740 | BC_SUPPORTS_FCOE_FEATURES : 0; | |
9741 | ||
9876879f BW |
9742 | bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? |
9743 | BC_SUPPORTS_DCBX_MSG_NON_PMF : 0; | |
1d187b34 BW |
9744 | boot_mode = SHMEM_RD(bp, |
9745 | dev_info.port_feature_config[BP_PORT(bp)].mba_config) & | |
9746 | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; | |
9747 | switch (boot_mode) { | |
9748 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: | |
9749 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; | |
9750 | break; | |
9751 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: | |
9752 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; | |
9753 | break; | |
9754 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: | |
9755 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; | |
9756 | break; | |
9757 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: | |
9758 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; | |
9759 | break; | |
9760 | } | |
9761 | ||
f9a3ebbe DK |
9762 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); |
9763 | bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; | |
9764 | ||
72ce58c3 | 9765 | BNX2X_DEV_INFO("%sWoL capable\n", |
f5372251 | 9766 | (bp->flags & NO_WOL_FLAG) ? "not " : ""); |
34f80b04 EG |
9767 | |
9768 | val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); | |
9769 | val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); | |
9770 | val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); | |
9771 | val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); | |
9772 | ||
cdaa7cb8 VZ |
9773 | dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", |
9774 | val, val2, val3, val4); | |
34f80b04 EG |
9775 | } |
9776 | ||
f2e0899f DK |
9777 | #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) |
9778 | #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) | |
9779 | ||
9780 | static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) | |
9781 | { | |
9782 | int pfid = BP_FUNC(bp); | |
f2e0899f DK |
9783 | int igu_sb_id; |
9784 | u32 val; | |
6383c0b3 | 9785 | u8 fid, igu_sb_cnt = 0; |
f2e0899f DK |
9786 | |
9787 | bp->igu_base_sb = 0xff; | |
f2e0899f | 9788 | if (CHIP_INT_MODE_IS_BC(bp)) { |
3395a033 | 9789 | int vn = BP_VN(bp); |
6383c0b3 | 9790 | igu_sb_cnt = bp->igu_sb_cnt; |
f2e0899f DK |
9791 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
9792 | FP_SB_MAX_E1x; | |
9793 | ||
9794 | bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + | |
9795 | (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); | |
9796 | ||
9797 | return; | |
9798 | } | |
9799 | ||
9800 | /* IGU in normal mode - read CAM */ | |
9801 | for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; | |
9802 | igu_sb_id++) { | |
9803 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); | |
9804 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) | |
9805 | continue; | |
9806 | fid = IGU_FID(val); | |
9807 | if ((fid & IGU_FID_ENCODE_IS_PF)) { | |
9808 | if ((fid & IGU_FID_PF_NUM_MASK) != pfid) | |
9809 | continue; | |
9810 | if (IGU_VEC(val) == 0) | |
9811 | /* default status block */ | |
9812 | bp->igu_dsb_id = igu_sb_id; | |
9813 | else { | |
9814 | if (bp->igu_base_sb == 0xff) | |
9815 | bp->igu_base_sb = igu_sb_id; | |
6383c0b3 | 9816 | igu_sb_cnt++; |
f2e0899f DK |
9817 | } |
9818 | } | |
9819 | } | |
619c5cb6 | 9820 | |
6383c0b3 AE |
9821 | #ifdef CONFIG_PCI_MSI |
9822 | /* | |
9823 | * It's expected that number of CAM entries for this functions is equal | |
9824 | * to the number evaluated based on the MSI-X table size. We want a | |
9825 | * harsh warning if these values are different! | |
619c5cb6 | 9826 | */ |
6383c0b3 AE |
9827 | WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); |
9828 | #endif | |
619c5cb6 | 9829 | |
6383c0b3 | 9830 | if (igu_sb_cnt == 0) |
f2e0899f DK |
9831 | BNX2X_ERR("CAM configuration error\n"); |
9832 | } | |
9833 | ||
34f80b04 EG |
9834 | static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, |
9835 | u32 switch_cfg) | |
a2fbb9ea | 9836 | { |
a22f0788 YR |
9837 | int cfg_size = 0, idx, port = BP_PORT(bp); |
9838 | ||
9839 | /* Aggregation of supported attributes of all external phys */ | |
9840 | bp->port.supported[0] = 0; | |
9841 | bp->port.supported[1] = 0; | |
b7737c9b YR |
9842 | switch (bp->link_params.num_phys) { |
9843 | case 1: | |
a22f0788 YR |
9844 | bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; |
9845 | cfg_size = 1; | |
9846 | break; | |
b7737c9b | 9847 | case 2: |
a22f0788 YR |
9848 | bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; |
9849 | cfg_size = 1; | |
9850 | break; | |
9851 | case 3: | |
9852 | if (bp->link_params.multi_phy_config & | |
9853 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { | |
9854 | bp->port.supported[1] = | |
9855 | bp->link_params.phy[EXT_PHY1].supported; | |
9856 | bp->port.supported[0] = | |
9857 | bp->link_params.phy[EXT_PHY2].supported; | |
9858 | } else { | |
9859 | bp->port.supported[0] = | |
9860 | bp->link_params.phy[EXT_PHY1].supported; | |
9861 | bp->port.supported[1] = | |
9862 | bp->link_params.phy[EXT_PHY2].supported; | |
9863 | } | |
9864 | cfg_size = 2; | |
9865 | break; | |
b7737c9b | 9866 | } |
a2fbb9ea | 9867 | |
a22f0788 | 9868 | if (!(bp->port.supported[0] || bp->port.supported[1])) { |
51c1a580 | 9869 | BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", |
b7737c9b | 9870 | SHMEM_RD(bp, |
a22f0788 YR |
9871 | dev_info.port_hw_config[port].external_phy_config), |
9872 | SHMEM_RD(bp, | |
9873 | dev_info.port_hw_config[port].external_phy_config2)); | |
a2fbb9ea | 9874 | return; |
f85582f8 | 9875 | } |
a2fbb9ea | 9876 | |
619c5cb6 VZ |
9877 | if (CHIP_IS_E3(bp)) |
9878 | bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); | |
9879 | else { | |
9880 | switch (switch_cfg) { | |
9881 | case SWITCH_CFG_1G: | |
9882 | bp->port.phy_addr = REG_RD( | |
9883 | bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); | |
9884 | break; | |
9885 | case SWITCH_CFG_10G: | |
9886 | bp->port.phy_addr = REG_RD( | |
9887 | bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); | |
9888 | break; | |
9889 | default: | |
9890 | BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", | |
9891 | bp->port.link_config[0]); | |
9892 | return; | |
9893 | } | |
a2fbb9ea | 9894 | } |
619c5cb6 | 9895 | BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); |
a22f0788 YR |
9896 | /* mask what we support according to speed_cap_mask per configuration */ |
9897 | for (idx = 0; idx < cfg_size; idx++) { | |
9898 | if (!(bp->link_params.speed_cap_mask[idx] & | |
c18487ee | 9899 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) |
a22f0788 | 9900 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; |
a2fbb9ea | 9901 | |
a22f0788 | 9902 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9903 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) |
a22f0788 | 9904 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; |
a2fbb9ea | 9905 | |
a22f0788 | 9906 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9907 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) |
a22f0788 | 9908 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; |
a2fbb9ea | 9909 | |
a22f0788 | 9910 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9911 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) |
a22f0788 | 9912 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; |
a2fbb9ea | 9913 | |
a22f0788 | 9914 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9915 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) |
a22f0788 | 9916 | bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | |
f85582f8 | 9917 | SUPPORTED_1000baseT_Full); |
a2fbb9ea | 9918 | |
a22f0788 | 9919 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9920 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
a22f0788 | 9921 | bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; |
a2fbb9ea | 9922 | |
a22f0788 | 9923 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9924 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
a22f0788 YR |
9925 | bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; |
9926 | ||
9927 | } | |
a2fbb9ea | 9928 | |
a22f0788 YR |
9929 | BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], |
9930 | bp->port.supported[1]); | |
a2fbb9ea ET |
9931 | } |
9932 | ||
34f80b04 | 9933 | static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) |
a2fbb9ea | 9934 | { |
a22f0788 YR |
9935 | u32 link_config, idx, cfg_size = 0; |
9936 | bp->port.advertising[0] = 0; | |
9937 | bp->port.advertising[1] = 0; | |
9938 | switch (bp->link_params.num_phys) { | |
9939 | case 1: | |
9940 | case 2: | |
9941 | cfg_size = 1; | |
9942 | break; | |
9943 | case 3: | |
9944 | cfg_size = 2; | |
9945 | break; | |
9946 | } | |
9947 | for (idx = 0; idx < cfg_size; idx++) { | |
9948 | bp->link_params.req_duplex[idx] = DUPLEX_FULL; | |
9949 | link_config = bp->port.link_config[idx]; | |
9950 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
f85582f8 | 9951 | case PORT_FEATURE_LINK_SPEED_AUTO: |
a22f0788 YR |
9952 | if (bp->port.supported[idx] & SUPPORTED_Autoneg) { |
9953 | bp->link_params.req_line_speed[idx] = | |
9954 | SPEED_AUTO_NEG; | |
9955 | bp->port.advertising[idx] |= | |
9956 | bp->port.supported[idx]; | |
10bd1f24 MY |
9957 | if (bp->link_params.phy[EXT_PHY1].type == |
9958 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | |
9959 | bp->port.advertising[idx] |= | |
9960 | (SUPPORTED_100baseT_Half | | |
9961 | SUPPORTED_100baseT_Full); | |
f85582f8 DK |
9962 | } else { |
9963 | /* force 10G, no AN */ | |
a22f0788 YR |
9964 | bp->link_params.req_line_speed[idx] = |
9965 | SPEED_10000; | |
9966 | bp->port.advertising[idx] |= | |
9967 | (ADVERTISED_10000baseT_Full | | |
f85582f8 | 9968 | ADVERTISED_FIBRE); |
a22f0788 | 9969 | continue; |
f85582f8 DK |
9970 | } |
9971 | break; | |
a2fbb9ea | 9972 | |
f85582f8 | 9973 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
a22f0788 YR |
9974 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { |
9975 | bp->link_params.req_line_speed[idx] = | |
9976 | SPEED_10; | |
9977 | bp->port.advertising[idx] |= | |
9978 | (ADVERTISED_10baseT_Full | | |
f85582f8 DK |
9979 | ADVERTISED_TP); |
9980 | } else { | |
51c1a580 | 9981 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 | 9982 | link_config, |
a22f0788 | 9983 | bp->link_params.speed_cap_mask[idx]); |
f85582f8 DK |
9984 | return; |
9985 | } | |
9986 | break; | |
a2fbb9ea | 9987 | |
f85582f8 | 9988 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
a22f0788 YR |
9989 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { |
9990 | bp->link_params.req_line_speed[idx] = | |
9991 | SPEED_10; | |
9992 | bp->link_params.req_duplex[idx] = | |
9993 | DUPLEX_HALF; | |
9994 | bp->port.advertising[idx] |= | |
9995 | (ADVERTISED_10baseT_Half | | |
f85582f8 DK |
9996 | ADVERTISED_TP); |
9997 | } else { | |
51c1a580 | 9998 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
9999 | link_config, |
10000 | bp->link_params.speed_cap_mask[idx]); | |
10001 | return; | |
10002 | } | |
10003 | break; | |
a2fbb9ea | 10004 | |
f85582f8 DK |
10005 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
10006 | if (bp->port.supported[idx] & | |
10007 | SUPPORTED_100baseT_Full) { | |
a22f0788 YR |
10008 | bp->link_params.req_line_speed[idx] = |
10009 | SPEED_100; | |
10010 | bp->port.advertising[idx] |= | |
10011 | (ADVERTISED_100baseT_Full | | |
f85582f8 DK |
10012 | ADVERTISED_TP); |
10013 | } else { | |
51c1a580 | 10014 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
10015 | link_config, |
10016 | bp->link_params.speed_cap_mask[idx]); | |
10017 | return; | |
10018 | } | |
10019 | break; | |
a2fbb9ea | 10020 | |
f85582f8 DK |
10021 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
10022 | if (bp->port.supported[idx] & | |
10023 | SUPPORTED_100baseT_Half) { | |
10024 | bp->link_params.req_line_speed[idx] = | |
10025 | SPEED_100; | |
10026 | bp->link_params.req_duplex[idx] = | |
10027 | DUPLEX_HALF; | |
a22f0788 YR |
10028 | bp->port.advertising[idx] |= |
10029 | (ADVERTISED_100baseT_Half | | |
f85582f8 DK |
10030 | ADVERTISED_TP); |
10031 | } else { | |
51c1a580 | 10032 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
10033 | link_config, |
10034 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
10035 | return; |
10036 | } | |
10037 | break; | |
a2fbb9ea | 10038 | |
f85582f8 | 10039 | case PORT_FEATURE_LINK_SPEED_1G: |
a22f0788 YR |
10040 | if (bp->port.supported[idx] & |
10041 | SUPPORTED_1000baseT_Full) { | |
10042 | bp->link_params.req_line_speed[idx] = | |
10043 | SPEED_1000; | |
10044 | bp->port.advertising[idx] |= | |
10045 | (ADVERTISED_1000baseT_Full | | |
f85582f8 DK |
10046 | ADVERTISED_TP); |
10047 | } else { | |
51c1a580 | 10048 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
10049 | link_config, |
10050 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
10051 | return; |
10052 | } | |
10053 | break; | |
a2fbb9ea | 10054 | |
f85582f8 | 10055 | case PORT_FEATURE_LINK_SPEED_2_5G: |
a22f0788 YR |
10056 | if (bp->port.supported[idx] & |
10057 | SUPPORTED_2500baseX_Full) { | |
10058 | bp->link_params.req_line_speed[idx] = | |
10059 | SPEED_2500; | |
10060 | bp->port.advertising[idx] |= | |
10061 | (ADVERTISED_2500baseX_Full | | |
34f80b04 | 10062 | ADVERTISED_TP); |
f85582f8 | 10063 | } else { |
51c1a580 | 10064 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 10065 | link_config, |
f85582f8 DK |
10066 | bp->link_params.speed_cap_mask[idx]); |
10067 | return; | |
10068 | } | |
10069 | break; | |
a2fbb9ea | 10070 | |
f85582f8 | 10071 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
a22f0788 YR |
10072 | if (bp->port.supported[idx] & |
10073 | SUPPORTED_10000baseT_Full) { | |
10074 | bp->link_params.req_line_speed[idx] = | |
10075 | SPEED_10000; | |
10076 | bp->port.advertising[idx] |= | |
10077 | (ADVERTISED_10000baseT_Full | | |
34f80b04 | 10078 | ADVERTISED_FIBRE); |
f85582f8 | 10079 | } else { |
51c1a580 | 10080 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 10081 | link_config, |
f85582f8 DK |
10082 | bp->link_params.speed_cap_mask[idx]); |
10083 | return; | |
10084 | } | |
10085 | break; | |
3c9ada22 YR |
10086 | case PORT_FEATURE_LINK_SPEED_20G: |
10087 | bp->link_params.req_line_speed[idx] = SPEED_20000; | |
a2fbb9ea | 10088 | |
3c9ada22 | 10089 | break; |
f85582f8 | 10090 | default: |
51c1a580 | 10091 | BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", |
754a2f52 | 10092 | link_config); |
f85582f8 DK |
10093 | bp->link_params.req_line_speed[idx] = |
10094 | SPEED_AUTO_NEG; | |
10095 | bp->port.advertising[idx] = | |
10096 | bp->port.supported[idx]; | |
10097 | break; | |
10098 | } | |
a2fbb9ea | 10099 | |
a22f0788 | 10100 | bp->link_params.req_flow_ctrl[idx] = (link_config & |
34f80b04 | 10101 | PORT_FEATURE_FLOW_CONTROL_MASK); |
a22f0788 YR |
10102 | if ((bp->link_params.req_flow_ctrl[idx] == |
10103 | BNX2X_FLOW_CTRL_AUTO) && | |
10104 | !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { | |
10105 | bp->link_params.req_flow_ctrl[idx] = | |
10106 | BNX2X_FLOW_CTRL_NONE; | |
10107 | } | |
a2fbb9ea | 10108 | |
51c1a580 | 10109 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", |
a22f0788 YR |
10110 | bp->link_params.req_line_speed[idx], |
10111 | bp->link_params.req_duplex[idx], | |
10112 | bp->link_params.req_flow_ctrl[idx], | |
10113 | bp->port.advertising[idx]); | |
10114 | } | |
a2fbb9ea ET |
10115 | } |
10116 | ||
e665bfda MC |
10117 | static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) |
10118 | { | |
10119 | mac_hi = cpu_to_be16(mac_hi); | |
10120 | mac_lo = cpu_to_be32(mac_lo); | |
10121 | memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); | |
10122 | memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); | |
10123 | } | |
10124 | ||
34f80b04 | 10125 | static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) |
a2fbb9ea | 10126 | { |
34f80b04 | 10127 | int port = BP_PORT(bp); |
589abe3a | 10128 | u32 config; |
c8c60d88 | 10129 | u32 ext_phy_type, ext_phy_config, eee_mode; |
a2fbb9ea | 10130 | |
c18487ee | 10131 | bp->link_params.bp = bp; |
34f80b04 | 10132 | bp->link_params.port = port; |
c18487ee | 10133 | |
c18487ee | 10134 | bp->link_params.lane_config = |
a2fbb9ea | 10135 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
4d295db0 | 10136 | |
a22f0788 | 10137 | bp->link_params.speed_cap_mask[0] = |
a2fbb9ea ET |
10138 | SHMEM_RD(bp, |
10139 | dev_info.port_hw_config[port].speed_capability_mask); | |
a22f0788 YR |
10140 | bp->link_params.speed_cap_mask[1] = |
10141 | SHMEM_RD(bp, | |
10142 | dev_info.port_hw_config[port].speed_capability_mask2); | |
10143 | bp->port.link_config[0] = | |
a2fbb9ea ET |
10144 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
10145 | ||
a22f0788 YR |
10146 | bp->port.link_config[1] = |
10147 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); | |
c2c8b03e | 10148 | |
a22f0788 YR |
10149 | bp->link_params.multi_phy_config = |
10150 | SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); | |
3ce2c3f9 EG |
10151 | /* If the device is capable of WoL, set the default state according |
10152 | * to the HW | |
10153 | */ | |
4d295db0 | 10154 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); |
3ce2c3f9 EG |
10155 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
10156 | (config & PORT_FEATURE_WOL_ENABLED)); | |
10157 | ||
51c1a580 | 10158 | BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", |
c18487ee | 10159 | bp->link_params.lane_config, |
a22f0788 YR |
10160 | bp->link_params.speed_cap_mask[0], |
10161 | bp->port.link_config[0]); | |
a2fbb9ea | 10162 | |
a22f0788 | 10163 | bp->link_params.switch_cfg = (bp->port.link_config[0] & |
f85582f8 | 10164 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
b7737c9b | 10165 | bnx2x_phy_probe(&bp->link_params); |
c18487ee | 10166 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
a2fbb9ea ET |
10167 | |
10168 | bnx2x_link_settings_requested(bp); | |
10169 | ||
01cd4528 EG |
10170 | /* |
10171 | * If connected directly, work with the internal PHY, otherwise, work | |
10172 | * with the external PHY | |
10173 | */ | |
b7737c9b YR |
10174 | ext_phy_config = |
10175 | SHMEM_RD(bp, | |
10176 | dev_info.port_hw_config[port].external_phy_config); | |
10177 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
01cd4528 | 10178 | if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
b7737c9b | 10179 | bp->mdio.prtad = bp->port.phy_addr; |
01cd4528 EG |
10180 | |
10181 | else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && | |
10182 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
10183 | bp->mdio.prtad = | |
b7737c9b | 10184 | XGXS_EXT_PHY_ADDR(ext_phy_config); |
5866df6d YR |
10185 | |
10186 | /* | |
10187 | * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) | |
10188 | * In MF mode, it is set to cover self test cases | |
10189 | */ | |
10190 | if (IS_MF(bp)) | |
10191 | bp->port.need_hw_lock = 1; | |
10192 | else | |
10193 | bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, | |
10194 | bp->common.shmem_base, | |
10195 | bp->common.shmem2_base); | |
c8c60d88 YM |
10196 | |
10197 | /* Configure link feature according to nvram value */ | |
10198 | eee_mode = (((SHMEM_RD(bp, dev_info. | |
10199 | port_feature_config[port].eee_power_mode)) & | |
10200 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> | |
10201 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); | |
10202 | if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { | |
10203 | bp->link_params.eee_mode = EEE_MODE_ADV_LPI | | |
10204 | EEE_MODE_ENABLE_LPI | | |
10205 | EEE_MODE_OUTPUT_TIME; | |
10206 | } else { | |
10207 | bp->link_params.eee_mode = 0; | |
10208 | } | |
0793f83f | 10209 | } |
01cd4528 | 10210 | |
b306f5ed | 10211 | void bnx2x_get_iscsi_info(struct bnx2x *bp) |
2ba45142 | 10212 | { |
9e62e912 | 10213 | u32 no_flags = NO_ISCSI_FLAG; |
7185bb33 | 10214 | #ifdef BCM_CNIC |
bf61ee14 | 10215 | int port = BP_PORT(bp); |
bf61ee14 | 10216 | |
2ba45142 | 10217 | u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
bf61ee14 | 10218 | drv_lic_key[port].max_iscsi_conn); |
2ba45142 | 10219 | |
b306f5ed | 10220 | /* Get the number of maximum allowed iSCSI connections */ |
2ba45142 VZ |
10221 | bp->cnic_eth_dev.max_iscsi_conn = |
10222 | (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> | |
10223 | BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; | |
10224 | ||
b306f5ed DK |
10225 | BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", |
10226 | bp->cnic_eth_dev.max_iscsi_conn); | |
10227 | ||
10228 | /* | |
10229 | * If maximum allowed number of connections is zero - | |
10230 | * disable the feature. | |
10231 | */ | |
10232 | if (!bp->cnic_eth_dev.max_iscsi_conn) | |
9e62e912 | 10233 | bp->flags |= no_flags; |
7185bb33 | 10234 | #else |
9e62e912 | 10235 | bp->flags |= no_flags; |
7185bb33 | 10236 | #endif |
b306f5ed DK |
10237 | } |
10238 | ||
9e62e912 DK |
10239 | #ifdef BCM_CNIC |
10240 | static void __devinit bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) | |
10241 | { | |
10242 | /* Port info */ | |
10243 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
10244 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); | |
10245 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
10246 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); | |
10247 | ||
10248 | /* Node info */ | |
10249 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
10250 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); | |
10251 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
10252 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); | |
10253 | } | |
10254 | #endif | |
b306f5ed DK |
10255 | static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp) |
10256 | { | |
7185bb33 | 10257 | #ifdef BCM_CNIC |
b306f5ed DK |
10258 | int port = BP_PORT(bp); |
10259 | int func = BP_ABS_FUNC(bp); | |
10260 | ||
10261 | u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, | |
10262 | drv_lic_key[port].max_fcoe_conn); | |
10263 | ||
10264 | /* Get the number of maximum allowed FCoE connections */ | |
2ba45142 VZ |
10265 | bp->cnic_eth_dev.max_fcoe_conn = |
10266 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> | |
10267 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; | |
10268 | ||
bf61ee14 VZ |
10269 | /* Read the WWN: */ |
10270 | if (!IS_MF(bp)) { | |
10271 | /* Port info */ | |
10272 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
10273 | SHMEM_RD(bp, | |
10274 | dev_info.port_hw_config[port]. | |
10275 | fcoe_wwn_port_name_upper); | |
10276 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
10277 | SHMEM_RD(bp, | |
10278 | dev_info.port_hw_config[port]. | |
10279 | fcoe_wwn_port_name_lower); | |
10280 | ||
10281 | /* Node info */ | |
10282 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
10283 | SHMEM_RD(bp, | |
10284 | dev_info.port_hw_config[port]. | |
10285 | fcoe_wwn_node_name_upper); | |
10286 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
10287 | SHMEM_RD(bp, | |
10288 | dev_info.port_hw_config[port]. | |
10289 | fcoe_wwn_node_name_lower); | |
10290 | } else if (!IS_MF_SD(bp)) { | |
10291 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); | |
10292 | ||
10293 | /* | |
10294 | * Read the WWN info only if the FCoE feature is enabled for | |
10295 | * this function. | |
10296 | */ | |
9e62e912 DK |
10297 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) |
10298 | bnx2x_get_ext_wwn_info(bp, func); | |
10299 | ||
10300 | } else if (IS_MF_FCOE_SD(bp)) | |
10301 | bnx2x_get_ext_wwn_info(bp, func); | |
bf61ee14 | 10302 | |
b306f5ed | 10303 | BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); |
2ba45142 | 10304 | |
bf61ee14 VZ |
10305 | /* |
10306 | * If maximum allowed number of connections is zero - | |
2ba45142 VZ |
10307 | * disable the feature. |
10308 | */ | |
2ba45142 VZ |
10309 | if (!bp->cnic_eth_dev.max_fcoe_conn) |
10310 | bp->flags |= NO_FCOE_FLAG; | |
7185bb33 DK |
10311 | #else |
10312 | bp->flags |= NO_FCOE_FLAG; | |
10313 | #endif | |
2ba45142 | 10314 | } |
b306f5ed DK |
10315 | |
10316 | static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) | |
10317 | { | |
10318 | /* | |
10319 | * iSCSI may be dynamically disabled but reading | |
10320 | * info here we will decrease memory usage by driver | |
10321 | * if the feature is disabled for good | |
10322 | */ | |
10323 | bnx2x_get_iscsi_info(bp); | |
10324 | bnx2x_get_fcoe_info(bp); | |
10325 | } | |
2ba45142 | 10326 | |
0793f83f DK |
10327 | static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) |
10328 | { | |
10329 | u32 val, val2; | |
10330 | int func = BP_ABS_FUNC(bp); | |
10331 | int port = BP_PORT(bp); | |
2ba45142 VZ |
10332 | #ifdef BCM_CNIC |
10333 | u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; | |
10334 | u8 *fip_mac = bp->fip_mac; | |
10335 | #endif | |
0793f83f | 10336 | |
619c5cb6 VZ |
10337 | /* Zero primary MAC configuration */ |
10338 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
10339 | ||
0793f83f DK |
10340 | if (BP_NOMCP(bp)) { |
10341 | BNX2X_ERROR("warning: random MAC workaround active\n"); | |
7ce5d222 | 10342 | eth_hw_addr_random(bp->dev); |
0793f83f DK |
10343 | } else if (IS_MF(bp)) { |
10344 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
10345 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); | |
10346 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && | |
10347 | (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) | |
10348 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
37b091ba MC |
10349 | |
10350 | #ifdef BCM_CNIC | |
614c76df DK |
10351 | /* |
10352 | * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or | |
2ba45142 | 10353 | * FCoE MAC then the appropriate feature should be disabled. |
9e62e912 DK |
10354 | * |
10355 | * In non SD mode features configuration comes from | |
10356 | * struct func_ext_config. | |
2ba45142 | 10357 | */ |
9e62e912 | 10358 | if (!IS_MF_SD(bp)) { |
0793f83f DK |
10359 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); |
10360 | if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { | |
10361 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
10362 | iscsi_mac_addr_upper); | |
10363 | val = MF_CFG_RD(bp, func_ext_config[func]. | |
10364 | iscsi_mac_addr_lower); | |
2ba45142 | 10365 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
0f9dad10 JP |
10366 | BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", |
10367 | iscsi_mac); | |
2ba45142 VZ |
10368 | } else |
10369 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; | |
10370 | ||
10371 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
10372 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
10373 | fcoe_mac_addr_upper); | |
10374 | val = MF_CFG_RD(bp, func_ext_config[func]. | |
10375 | fcoe_mac_addr_lower); | |
2ba45142 | 10376 | bnx2x_set_mac_buf(fip_mac, val, val2); |
614c76df | 10377 | BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n", |
0f9dad10 | 10378 | fip_mac); |
2ba45142 | 10379 | |
2ba45142 VZ |
10380 | } else |
10381 | bp->flags |= NO_FCOE_FLAG; | |
a3348722 BW |
10382 | |
10383 | bp->mf_ext_config = cfg; | |
10384 | ||
9e62e912 DK |
10385 | } else { /* SD MODE */ |
10386 | if (IS_MF_STORAGE_SD(bp)) { | |
10387 | if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { | |
10388 | /* use primary mac as iscsi mac */ | |
10389 | memcpy(iscsi_mac, bp->dev->dev_addr, | |
10390 | ETH_ALEN); | |
10391 | ||
10392 | BNX2X_DEV_INFO("SD ISCSI MODE\n"); | |
10393 | BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", | |
10394 | iscsi_mac); | |
10395 | } else { /* FCoE */ | |
10396 | memcpy(fip_mac, bp->dev->dev_addr, | |
10397 | ETH_ALEN); | |
10398 | BNX2X_DEV_INFO("SD FCoE MODE\n"); | |
10399 | BNX2X_DEV_INFO("Read FIP MAC: %pM\n", | |
10400 | fip_mac); | |
10401 | } | |
614c76df DK |
10402 | /* Zero primary MAC configuration */ |
10403 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
614c76df | 10404 | } |
0793f83f | 10405 | } |
a3348722 BW |
10406 | |
10407 | if (IS_MF_FCOE_AFEX(bp)) | |
10408 | /* use FIP MAC as primary MAC */ | |
10409 | memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); | |
10410 | ||
37b091ba | 10411 | #endif |
0793f83f DK |
10412 | } else { |
10413 | /* in SF read MACs from port configuration */ | |
10414 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
10415 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
10416 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
10417 | ||
10418 | #ifdef BCM_CNIC | |
10419 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
10420 | iscsi_mac_upper); | |
10421 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
10422 | iscsi_mac_lower); | |
2ba45142 | 10423 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
c03bd39c VZ |
10424 | |
10425 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
10426 | fcoe_fip_mac_upper); | |
10427 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
10428 | fcoe_fip_mac_lower); | |
10429 | bnx2x_set_mac_buf(fip_mac, val, val2); | |
0793f83f DK |
10430 | #endif |
10431 | } | |
10432 | ||
10433 | memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); | |
10434 | memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); | |
10435 | ||
ec6ba945 | 10436 | #ifdef BCM_CNIC |
426b9241 DK |
10437 | /* Disable iSCSI if MAC configuration is |
10438 | * invalid. | |
10439 | */ | |
10440 | if (!is_valid_ether_addr(iscsi_mac)) { | |
10441 | bp->flags |= NO_ISCSI_FLAG; | |
10442 | memset(iscsi_mac, 0, ETH_ALEN); | |
10443 | } | |
10444 | ||
10445 | /* Disable FCoE if MAC configuration is | |
10446 | * invalid. | |
10447 | */ | |
10448 | if (!is_valid_ether_addr(fip_mac)) { | |
10449 | bp->flags |= NO_FCOE_FLAG; | |
10450 | memset(bp->fip_mac, 0, ETH_ALEN); | |
10451 | } | |
ec6ba945 | 10452 | #endif |
619c5cb6 | 10453 | |
614c76df | 10454 | if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) |
619c5cb6 | 10455 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
10456 | "bad Ethernet MAC address configuration: %pM\n" |
10457 | "change it manually before bringing up the appropriate network interface\n", | |
0f9dad10 | 10458 | bp->dev->dev_addr); |
51c1a580 MS |
10459 | |
10460 | ||
34f80b04 EG |
10461 | } |
10462 | ||
10463 | static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) | |
10464 | { | |
0793f83f | 10465 | int /*abs*/func = BP_ABS_FUNC(bp); |
b8ee8328 | 10466 | int vn; |
0793f83f | 10467 | u32 val = 0; |
34f80b04 | 10468 | int rc = 0; |
a2fbb9ea | 10469 | |
34f80b04 | 10470 | bnx2x_get_common_hwinfo(bp); |
a2fbb9ea | 10471 | |
6383c0b3 AE |
10472 | /* |
10473 | * initialize IGU parameters | |
10474 | */ | |
f2e0899f DK |
10475 | if (CHIP_IS_E1x(bp)) { |
10476 | bp->common.int_block = INT_BLOCK_HC; | |
10477 | ||
10478 | bp->igu_dsb_id = DEF_SB_IGU_ID; | |
10479 | bp->igu_base_sb = 0; | |
f2e0899f DK |
10480 | } else { |
10481 | bp->common.int_block = INT_BLOCK_IGU; | |
7a06a122 DK |
10482 | |
10483 | /* do not allow device reset during IGU info preocessing */ | |
10484 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); | |
10485 | ||
f2e0899f | 10486 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
619c5cb6 VZ |
10487 | |
10488 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { | |
10489 | int tout = 5000; | |
10490 | ||
10491 | BNX2X_DEV_INFO("FORCING Normal Mode\n"); | |
10492 | ||
10493 | val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); | |
10494 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); | |
10495 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); | |
10496 | ||
10497 | while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
10498 | tout--; | |
10499 | usleep_range(1000, 1000); | |
10500 | } | |
10501 | ||
10502 | if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
10503 | dev_err(&bp->pdev->dev, | |
10504 | "FORCING Normal Mode failed!!!\n"); | |
10505 | return -EPERM; | |
10506 | } | |
10507 | } | |
10508 | ||
f2e0899f | 10509 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
619c5cb6 | 10510 | BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); |
f2e0899f DK |
10511 | bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; |
10512 | } else | |
619c5cb6 | 10513 | BNX2X_DEV_INFO("IGU Normal Mode\n"); |
523224a3 | 10514 | |
f2e0899f DK |
10515 | bnx2x_get_igu_cam_info(bp); |
10516 | ||
7a06a122 | 10517 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
f2e0899f | 10518 | } |
619c5cb6 VZ |
10519 | |
10520 | /* | |
10521 | * set base FW non-default (fast path) status block id, this value is | |
10522 | * used to initialize the fw_sb_id saved on the fp/queue structure to | |
10523 | * determine the id used by the FW. | |
10524 | */ | |
10525 | if (CHIP_IS_E1x(bp)) | |
10526 | bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); | |
10527 | else /* | |
10528 | * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of | |
10529 | * the same queue are indicated on the same IGU SB). So we prefer | |
10530 | * FW and IGU SBs to be the same value. | |
10531 | */ | |
10532 | bp->base_fw_ndsb = bp->igu_base_sb; | |
10533 | ||
10534 | BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" | |
10535 | "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, | |
10536 | bp->igu_sb_cnt, bp->base_fw_ndsb); | |
f2e0899f DK |
10537 | |
10538 | /* | |
10539 | * Initialize MF configuration | |
10540 | */ | |
523224a3 | 10541 | |
fb3bff17 DK |
10542 | bp->mf_ov = 0; |
10543 | bp->mf_mode = 0; | |
3395a033 | 10544 | vn = BP_VN(bp); |
0793f83f | 10545 | |
f2e0899f | 10546 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
619c5cb6 VZ |
10547 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
10548 | bp->common.shmem2_base, SHMEM2_RD(bp, size), | |
10549 | (u32)offsetof(struct shmem2_region, mf_cfg_addr)); | |
10550 | ||
f2e0899f DK |
10551 | if (SHMEM2_HAS(bp, mf_cfg_addr)) |
10552 | bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); | |
10553 | else | |
10554 | bp->common.mf_cfg_base = bp->common.shmem_base + | |
523224a3 DK |
10555 | offsetof(struct shmem_region, func_mb) + |
10556 | E1H_FUNC_MAX * sizeof(struct drv_func_mb); | |
0793f83f DK |
10557 | /* |
10558 | * get mf configuration: | |
25985edc | 10559 | * 1. existence of MF configuration |
0793f83f DK |
10560 | * 2. MAC address must be legal (check only upper bytes) |
10561 | * for Switch-Independent mode; | |
10562 | * OVLAN must be legal for Switch-Dependent mode | |
10563 | * 3. SF_MODE configures specific MF mode | |
10564 | */ | |
10565 | if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
10566 | /* get mf configuration */ | |
10567 | val = SHMEM_RD(bp, | |
10568 | dev_info.shared_feature_config.config); | |
10569 | val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; | |
10570 | ||
10571 | switch (val) { | |
10572 | case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: | |
10573 | val = MF_CFG_RD(bp, func_mf_config[func]. | |
10574 | mac_upper); | |
10575 | /* check for legal mac (upper bytes)*/ | |
10576 | if (val != 0xffff) { | |
10577 | bp->mf_mode = MULTI_FUNCTION_SI; | |
10578 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
10579 | func_mf_config[func].config); | |
10580 | } else | |
51c1a580 | 10581 | BNX2X_DEV_INFO("illegal MAC address for SI\n"); |
0793f83f | 10582 | break; |
a3348722 BW |
10583 | case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: |
10584 | if ((!CHIP_IS_E1x(bp)) && | |
10585 | (MF_CFG_RD(bp, func_mf_config[func]. | |
10586 | mac_upper) != 0xffff) && | |
10587 | (SHMEM2_HAS(bp, | |
10588 | afex_driver_support))) { | |
10589 | bp->mf_mode = MULTI_FUNCTION_AFEX; | |
10590 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
10591 | func_mf_config[func].config); | |
10592 | } else { | |
10593 | BNX2X_DEV_INFO("can not configure afex mode\n"); | |
10594 | } | |
10595 | break; | |
0793f83f DK |
10596 | case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: |
10597 | /* get OV configuration */ | |
10598 | val = MF_CFG_RD(bp, | |
10599 | func_mf_config[FUNC_0].e1hov_tag); | |
10600 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; | |
10601 | ||
10602 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
10603 | bp->mf_mode = MULTI_FUNCTION_SD; | |
10604 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
10605 | func_mf_config[func].config); | |
10606 | } else | |
754a2f52 | 10607 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
0793f83f DK |
10608 | break; |
10609 | default: | |
10610 | /* Unknown configuration: reset mf_config */ | |
10611 | bp->mf_config[vn] = 0; | |
51c1a580 | 10612 | BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); |
0793f83f DK |
10613 | } |
10614 | } | |
a2fbb9ea | 10615 | |
2691d51d | 10616 | BNX2X_DEV_INFO("%s function mode\n", |
fb3bff17 | 10617 | IS_MF(bp) ? "multi" : "single"); |
2691d51d | 10618 | |
0793f83f DK |
10619 | switch (bp->mf_mode) { |
10620 | case MULTI_FUNCTION_SD: | |
10621 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
10622 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2691d51d | 10623 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
fb3bff17 | 10624 | bp->mf_ov = val; |
619c5cb6 VZ |
10625 | bp->path_has_ovlan = true; |
10626 | ||
51c1a580 MS |
10627 | BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", |
10628 | func, bp->mf_ov, bp->mf_ov); | |
2691d51d | 10629 | } else { |
619c5cb6 | 10630 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
10631 | "No valid MF OV for func %d, aborting\n", |
10632 | func); | |
619c5cb6 | 10633 | return -EPERM; |
34f80b04 | 10634 | } |
0793f83f | 10635 | break; |
a3348722 BW |
10636 | case MULTI_FUNCTION_AFEX: |
10637 | BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); | |
10638 | break; | |
0793f83f | 10639 | case MULTI_FUNCTION_SI: |
51c1a580 MS |
10640 | BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", |
10641 | func); | |
0793f83f DK |
10642 | break; |
10643 | default: | |
10644 | if (vn) { | |
619c5cb6 | 10645 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
10646 | "VN %d is in a single function mode, aborting\n", |
10647 | vn); | |
619c5cb6 | 10648 | return -EPERM; |
2691d51d | 10649 | } |
0793f83f | 10650 | break; |
34f80b04 | 10651 | } |
0793f83f | 10652 | |
619c5cb6 VZ |
10653 | /* check if other port on the path needs ovlan: |
10654 | * Since MF configuration is shared between ports | |
10655 | * Possible mixed modes are only | |
10656 | * {SF, SI} {SF, SD} {SD, SF} {SI, SF} | |
10657 | */ | |
10658 | if (CHIP_MODE_IS_4_PORT(bp) && | |
10659 | !bp->path_has_ovlan && | |
10660 | !IS_MF(bp) && | |
10661 | bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
10662 | u8 other_port = !BP_PORT(bp); | |
10663 | u8 other_func = BP_PATH(bp) + 2*other_port; | |
10664 | val = MF_CFG_RD(bp, | |
10665 | func_mf_config[other_func].e1hov_tag); | |
10666 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) | |
10667 | bp->path_has_ovlan = true; | |
10668 | } | |
34f80b04 | 10669 | } |
a2fbb9ea | 10670 | |
f2e0899f DK |
10671 | /* adjust igu_sb_cnt to MF for E1x */ |
10672 | if (CHIP_IS_E1x(bp) && IS_MF(bp)) | |
523224a3 DK |
10673 | bp->igu_sb_cnt /= E1HVN_MAX; |
10674 | ||
619c5cb6 VZ |
10675 | /* port info */ |
10676 | bnx2x_get_port_hwinfo(bp); | |
f2e0899f | 10677 | |
0793f83f DK |
10678 | /* Get MAC addresses */ |
10679 | bnx2x_get_mac_hwinfo(bp); | |
a2fbb9ea | 10680 | |
2ba45142 | 10681 | bnx2x_get_cnic_info(bp); |
2ba45142 | 10682 | |
34f80b04 EG |
10683 | return rc; |
10684 | } | |
10685 | ||
34f24c7f VZ |
10686 | static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) |
10687 | { | |
10688 | int cnt, i, block_end, rodi; | |
fcdf95cb | 10689 | char vpd_start[BNX2X_VPD_LEN+1]; |
34f24c7f VZ |
10690 | char str_id_reg[VENDOR_ID_LEN+1]; |
10691 | char str_id_cap[VENDOR_ID_LEN+1]; | |
fcdf95cb BW |
10692 | char *vpd_data; |
10693 | char *vpd_extended_data = NULL; | |
34f24c7f VZ |
10694 | u8 len; |
10695 | ||
fcdf95cb | 10696 | cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); |
34f24c7f VZ |
10697 | memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); |
10698 | ||
10699 | if (cnt < BNX2X_VPD_LEN) | |
10700 | goto out_not_found; | |
10701 | ||
fcdf95cb BW |
10702 | /* VPD RO tag should be first tag after identifier string, hence |
10703 | * we should be able to find it in first BNX2X_VPD_LEN chars | |
10704 | */ | |
10705 | i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, | |
34f24c7f VZ |
10706 | PCI_VPD_LRDT_RO_DATA); |
10707 | if (i < 0) | |
10708 | goto out_not_found; | |
10709 | ||
34f24c7f | 10710 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + |
fcdf95cb | 10711 | pci_vpd_lrdt_size(&vpd_start[i]); |
34f24c7f VZ |
10712 | |
10713 | i += PCI_VPD_LRDT_TAG_SIZE; | |
10714 | ||
fcdf95cb BW |
10715 | if (block_end > BNX2X_VPD_LEN) { |
10716 | vpd_extended_data = kmalloc(block_end, GFP_KERNEL); | |
10717 | if (vpd_extended_data == NULL) | |
10718 | goto out_not_found; | |
10719 | ||
10720 | /* read rest of vpd image into vpd_extended_data */ | |
10721 | memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); | |
10722 | cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, | |
10723 | block_end - BNX2X_VPD_LEN, | |
10724 | vpd_extended_data + BNX2X_VPD_LEN); | |
10725 | if (cnt < (block_end - BNX2X_VPD_LEN)) | |
10726 | goto out_not_found; | |
10727 | vpd_data = vpd_extended_data; | |
10728 | } else | |
10729 | vpd_data = vpd_start; | |
10730 | ||
10731 | /* now vpd_data holds full vpd content in both cases */ | |
34f24c7f VZ |
10732 | |
10733 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
10734 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
10735 | if (rodi < 0) | |
10736 | goto out_not_found; | |
10737 | ||
10738 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
10739 | ||
10740 | if (len != VENDOR_ID_LEN) | |
10741 | goto out_not_found; | |
10742 | ||
10743 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
10744 | ||
10745 | /* vendor specific info */ | |
10746 | snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); | |
10747 | snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); | |
10748 | if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || | |
10749 | !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { | |
10750 | ||
10751 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
10752 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
10753 | if (rodi >= 0) { | |
10754 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
10755 | ||
10756 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
10757 | ||
10758 | if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { | |
10759 | memcpy(bp->fw_ver, &vpd_data[rodi], len); | |
10760 | bp->fw_ver[len] = ' '; | |
10761 | } | |
10762 | } | |
fcdf95cb | 10763 | kfree(vpd_extended_data); |
34f24c7f VZ |
10764 | return; |
10765 | } | |
10766 | out_not_found: | |
fcdf95cb | 10767 | kfree(vpd_extended_data); |
34f24c7f VZ |
10768 | return; |
10769 | } | |
10770 | ||
619c5cb6 VZ |
10771 | static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) |
10772 | { | |
10773 | u32 flags = 0; | |
10774 | ||
10775 | if (CHIP_REV_IS_FPGA(bp)) | |
10776 | SET_FLAGS(flags, MODE_FPGA); | |
10777 | else if (CHIP_REV_IS_EMUL(bp)) | |
10778 | SET_FLAGS(flags, MODE_EMUL); | |
10779 | else | |
10780 | SET_FLAGS(flags, MODE_ASIC); | |
10781 | ||
10782 | if (CHIP_MODE_IS_4_PORT(bp)) | |
10783 | SET_FLAGS(flags, MODE_PORT4); | |
10784 | else | |
10785 | SET_FLAGS(flags, MODE_PORT2); | |
10786 | ||
10787 | if (CHIP_IS_E2(bp)) | |
10788 | SET_FLAGS(flags, MODE_E2); | |
10789 | else if (CHIP_IS_E3(bp)) { | |
10790 | SET_FLAGS(flags, MODE_E3); | |
10791 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
10792 | SET_FLAGS(flags, MODE_E3_A0); | |
6383c0b3 AE |
10793 | else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ |
10794 | SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); | |
619c5cb6 VZ |
10795 | } |
10796 | ||
10797 | if (IS_MF(bp)) { | |
10798 | SET_FLAGS(flags, MODE_MF); | |
10799 | switch (bp->mf_mode) { | |
10800 | case MULTI_FUNCTION_SD: | |
10801 | SET_FLAGS(flags, MODE_MF_SD); | |
10802 | break; | |
10803 | case MULTI_FUNCTION_SI: | |
10804 | SET_FLAGS(flags, MODE_MF_SI); | |
10805 | break; | |
a3348722 BW |
10806 | case MULTI_FUNCTION_AFEX: |
10807 | SET_FLAGS(flags, MODE_MF_AFEX); | |
10808 | break; | |
619c5cb6 VZ |
10809 | } |
10810 | } else | |
10811 | SET_FLAGS(flags, MODE_SF); | |
10812 | ||
10813 | #if defined(__LITTLE_ENDIAN) | |
10814 | SET_FLAGS(flags, MODE_LITTLE_ENDIAN); | |
10815 | #else /*(__BIG_ENDIAN)*/ | |
10816 | SET_FLAGS(flags, MODE_BIG_ENDIAN); | |
10817 | #endif | |
10818 | INIT_MODE_FLAGS(bp) = flags; | |
10819 | } | |
10820 | ||
34f80b04 EG |
10821 | static int __devinit bnx2x_init_bp(struct bnx2x *bp) |
10822 | { | |
f2e0899f | 10823 | int func; |
34f80b04 EG |
10824 | int rc; |
10825 | ||
34f80b04 | 10826 | mutex_init(&bp->port.phy_mutex); |
c4ff7cbf | 10827 | mutex_init(&bp->fw_mb_mutex); |
bb7e95c8 | 10828 | spin_lock_init(&bp->stats_lock); |
993ac7b5 MC |
10829 | #ifdef BCM_CNIC |
10830 | mutex_init(&bp->cnic_mutex); | |
10831 | #endif | |
a2fbb9ea | 10832 | |
1cf167f2 | 10833 | INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); |
7be08a72 | 10834 | INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); |
3deb8167 | 10835 | INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); |
34f80b04 | 10836 | rc = bnx2x_get_hwinfo(bp); |
619c5cb6 VZ |
10837 | if (rc) |
10838 | return rc; | |
34f80b04 | 10839 | |
619c5cb6 VZ |
10840 | bnx2x_set_modes_bitmap(bp); |
10841 | ||
10842 | rc = bnx2x_alloc_mem_bp(bp); | |
10843 | if (rc) | |
10844 | return rc; | |
523224a3 | 10845 | |
34f24c7f | 10846 | bnx2x_read_fwinfo(bp); |
f2e0899f DK |
10847 | |
10848 | func = BP_FUNC(bp); | |
10849 | ||
34f80b04 | 10850 | /* need to reset chip if undi was active */ |
452427b0 YM |
10851 | if (!BP_NOMCP(bp)) { |
10852 | /* init fw_seq */ | |
10853 | bp->fw_seq = | |
10854 | SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
10855 | DRV_MSG_SEQ_NUMBER_MASK; | |
10856 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | |
10857 | ||
10858 | bnx2x_prev_unload(bp); | |
10859 | } | |
10860 | ||
34f80b04 EG |
10861 | |
10862 | if (CHIP_REV_IS_FPGA(bp)) | |
cdaa7cb8 | 10863 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
34f80b04 EG |
10864 | |
10865 | if (BP_NOMCP(bp) && (func == 0)) | |
51c1a580 | 10866 | dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); |
34f80b04 | 10867 | |
614c76df DK |
10868 | bp->disable_tpa = disable_tpa; |
10869 | ||
10870 | #ifdef BCM_CNIC | |
a3348722 | 10871 | bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp); |
614c76df DK |
10872 | #endif |
10873 | ||
7a9b2557 | 10874 | /* Set TPA flags */ |
614c76df | 10875 | if (bp->disable_tpa) { |
621b4d66 | 10876 | bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
7a9b2557 VZ |
10877 | bp->dev->features &= ~NETIF_F_LRO; |
10878 | } else { | |
621b4d66 | 10879 | bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
7a9b2557 VZ |
10880 | bp->dev->features |= NETIF_F_LRO; |
10881 | } | |
10882 | ||
a18f5128 EG |
10883 | if (CHIP_IS_E1(bp)) |
10884 | bp->dropless_fc = 0; | |
10885 | else | |
10886 | bp->dropless_fc = dropless_fc; | |
10887 | ||
8d5726c4 | 10888 | bp->mrrs = mrrs; |
7a9b2557 | 10889 | |
a3348722 | 10890 | bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; |
34f80b04 | 10891 | |
7d323bfd | 10892 | /* make sure that the numbers are in the right granularity */ |
523224a3 DK |
10893 | bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; |
10894 | bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; | |
34f80b04 | 10895 | |
fc543637 | 10896 | bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; |
34f80b04 EG |
10897 | |
10898 | init_timer(&bp->timer); | |
10899 | bp->timer.expires = jiffies + bp->current_interval; | |
10900 | bp->timer.data = (unsigned long) bp; | |
10901 | bp->timer.function = bnx2x_timer; | |
10902 | ||
785b9b1a | 10903 | bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); |
e4901dde VZ |
10904 | bnx2x_dcbx_init_params(bp); |
10905 | ||
619c5cb6 VZ |
10906 | #ifdef BCM_CNIC |
10907 | if (CHIP_IS_E1x(bp)) | |
10908 | bp->cnic_base_cl_id = FP_SB_MAX_E1x; | |
10909 | else | |
10910 | bp->cnic_base_cl_id = FP_SB_MAX_E2; | |
10911 | #endif | |
10912 | ||
6383c0b3 AE |
10913 | /* multiple tx priority */ |
10914 | if (CHIP_IS_E1x(bp)) | |
10915 | bp->max_cos = BNX2X_MULTI_TX_COS_E1X; | |
10916 | if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) | |
10917 | bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; | |
10918 | if (CHIP_IS_E3B0(bp)) | |
10919 | bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; | |
10920 | ||
34f80b04 | 10921 | return rc; |
a2fbb9ea ET |
10922 | } |
10923 | ||
a2fbb9ea | 10924 | |
de0c62db DK |
10925 | /**************************************************************************** |
10926 | * General service functions | |
10927 | ****************************************************************************/ | |
a2fbb9ea | 10928 | |
619c5cb6 VZ |
10929 | /* |
10930 | * net_device service functions | |
10931 | */ | |
10932 | ||
bb2a0f7a | 10933 | /* called with rtnl_lock */ |
a2fbb9ea ET |
10934 | static int bnx2x_open(struct net_device *dev) |
10935 | { | |
10936 | struct bnx2x *bp = netdev_priv(dev); | |
c9ee9206 VZ |
10937 | bool global = false; |
10938 | int other_engine = BP_PATH(bp) ? 0 : 1; | |
889b9af3 | 10939 | bool other_load_status, load_status; |
a2fbb9ea | 10940 | |
1355b704 MY |
10941 | bp->stats_init = true; |
10942 | ||
6eccabb3 EG |
10943 | netif_carrier_off(dev); |
10944 | ||
a2fbb9ea ET |
10945 | bnx2x_set_power_state(bp, PCI_D0); |
10946 | ||
889b9af3 AE |
10947 | other_load_status = bnx2x_get_load_status(bp, other_engine); |
10948 | load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); | |
c9ee9206 VZ |
10949 | |
10950 | /* | |
10951 | * If parity had happen during the unload, then attentions | |
10952 | * and/or RECOVERY_IN_PROGRES may still be set. In this case we | |
10953 | * want the first function loaded on the current engine to | |
10954 | * complete the recovery. | |
10955 | */ | |
10956 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || | |
10957 | bnx2x_chk_parity_attn(bp, &global, true)) | |
72fd0718 | 10958 | do { |
c9ee9206 VZ |
10959 | /* |
10960 | * If there are attentions and they are in a global | |
10961 | * blocks, set the GLOBAL_RESET bit regardless whether | |
10962 | * it will be this function that will complete the | |
10963 | * recovery or not. | |
72fd0718 | 10964 | */ |
c9ee9206 VZ |
10965 | if (global) |
10966 | bnx2x_set_reset_global(bp); | |
72fd0718 | 10967 | |
c9ee9206 VZ |
10968 | /* |
10969 | * Only the first function on the current engine should | |
10970 | * try to recover in open. In case of attentions in | |
10971 | * global blocks only the first in the chip should try | |
10972 | * to recover. | |
72fd0718 | 10973 | */ |
889b9af3 AE |
10974 | if ((!load_status && |
10975 | (!global || !other_load_status)) && | |
c9ee9206 VZ |
10976 | bnx2x_trylock_leader_lock(bp) && |
10977 | !bnx2x_leader_reset(bp)) { | |
10978 | netdev_info(bp->dev, "Recovered in open\n"); | |
72fd0718 VZ |
10979 | break; |
10980 | } | |
10981 | ||
c9ee9206 | 10982 | /* recovery has failed... */ |
72fd0718 | 10983 | bnx2x_set_power_state(bp, PCI_D3hot); |
c9ee9206 | 10984 | bp->recovery_state = BNX2X_RECOVERY_FAILED; |
72fd0718 | 10985 | |
51c1a580 MS |
10986 | BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" |
10987 | "If you still see this message after a few retries then power cycle is required.\n"); | |
72fd0718 VZ |
10988 | |
10989 | return -EAGAIN; | |
10990 | } while (0); | |
72fd0718 VZ |
10991 | |
10992 | bp->recovery_state = BNX2X_RECOVERY_DONE; | |
bb2a0f7a | 10993 | return bnx2x_nic_load(bp, LOAD_OPEN); |
a2fbb9ea ET |
10994 | } |
10995 | ||
bb2a0f7a | 10996 | /* called with rtnl_lock */ |
56ad3152 | 10997 | static int bnx2x_close(struct net_device *dev) |
a2fbb9ea | 10998 | { |
a2fbb9ea ET |
10999 | struct bnx2x *bp = netdev_priv(dev); |
11000 | ||
11001 | /* Unload the driver, release IRQs */ | |
bb2a0f7a | 11002 | bnx2x_nic_unload(bp, UNLOAD_CLOSE); |
c9ee9206 VZ |
11003 | |
11004 | /* Power off */ | |
d3dbfee0 | 11005 | bnx2x_set_power_state(bp, PCI_D3hot); |
a2fbb9ea ET |
11006 | |
11007 | return 0; | |
11008 | } | |
11009 | ||
1191cb83 ED |
11010 | static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, |
11011 | struct bnx2x_mcast_ramrod_params *p) | |
6e30dd4e | 11012 | { |
619c5cb6 VZ |
11013 | int mc_count = netdev_mc_count(bp->dev); |
11014 | struct bnx2x_mcast_list_elem *mc_mac = | |
11015 | kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); | |
11016 | struct netdev_hw_addr *ha; | |
6e30dd4e | 11017 | |
619c5cb6 VZ |
11018 | if (!mc_mac) |
11019 | return -ENOMEM; | |
6e30dd4e | 11020 | |
619c5cb6 | 11021 | INIT_LIST_HEAD(&p->mcast_list); |
6e30dd4e | 11022 | |
619c5cb6 VZ |
11023 | netdev_for_each_mc_addr(ha, bp->dev) { |
11024 | mc_mac->mac = bnx2x_mc_addr(ha); | |
11025 | list_add_tail(&mc_mac->link, &p->mcast_list); | |
11026 | mc_mac++; | |
6e30dd4e | 11027 | } |
619c5cb6 VZ |
11028 | |
11029 | p->mcast_list_len = mc_count; | |
11030 | ||
11031 | return 0; | |
6e30dd4e VZ |
11032 | } |
11033 | ||
1191cb83 | 11034 | static void bnx2x_free_mcast_macs_list( |
619c5cb6 VZ |
11035 | struct bnx2x_mcast_ramrod_params *p) |
11036 | { | |
11037 | struct bnx2x_mcast_list_elem *mc_mac = | |
11038 | list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, | |
11039 | link); | |
11040 | ||
11041 | WARN_ON(!mc_mac); | |
11042 | kfree(mc_mac); | |
11043 | } | |
11044 | ||
11045 | /** | |
11046 | * bnx2x_set_uc_list - configure a new unicast MACs list. | |
11047 | * | |
11048 | * @bp: driver handle | |
6e30dd4e | 11049 | * |
619c5cb6 | 11050 | * We will use zero (0) as a MAC type for these MACs. |
6e30dd4e | 11051 | */ |
1191cb83 | 11052 | static int bnx2x_set_uc_list(struct bnx2x *bp) |
6e30dd4e | 11053 | { |
619c5cb6 | 11054 | int rc; |
6e30dd4e | 11055 | struct net_device *dev = bp->dev; |
6e30dd4e | 11056 | struct netdev_hw_addr *ha; |
15192a8c | 11057 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; |
619c5cb6 | 11058 | unsigned long ramrod_flags = 0; |
6e30dd4e | 11059 | |
619c5cb6 VZ |
11060 | /* First schedule a cleanup up of old configuration */ |
11061 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); | |
11062 | if (rc < 0) { | |
11063 | BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); | |
11064 | return rc; | |
11065 | } | |
6e30dd4e VZ |
11066 | |
11067 | netdev_for_each_uc_addr(ha, dev) { | |
619c5cb6 VZ |
11068 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
11069 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
11070 | if (rc < 0) { | |
11071 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", | |
11072 | rc); | |
11073 | return rc; | |
6e30dd4e VZ |
11074 | } |
11075 | } | |
11076 | ||
619c5cb6 VZ |
11077 | /* Execute the pending commands */ |
11078 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
11079 | return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, | |
11080 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
6e30dd4e VZ |
11081 | } |
11082 | ||
1191cb83 | 11083 | static int bnx2x_set_mc_list(struct bnx2x *bp) |
6e30dd4e | 11084 | { |
619c5cb6 | 11085 | struct net_device *dev = bp->dev; |
3b603066 | 11086 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 | 11087 | int rc = 0; |
6e30dd4e | 11088 | |
619c5cb6 | 11089 | rparam.mcast_obj = &bp->mcast_obj; |
6e30dd4e | 11090 | |
619c5cb6 VZ |
11091 | /* first, clear all configured multicast MACs */ |
11092 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
11093 | if (rc < 0) { | |
51c1a580 | 11094 | BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); |
619c5cb6 VZ |
11095 | return rc; |
11096 | } | |
6e30dd4e | 11097 | |
619c5cb6 VZ |
11098 | /* then, configure a new MACs list */ |
11099 | if (netdev_mc_count(dev)) { | |
11100 | rc = bnx2x_init_mcast_macs_list(bp, &rparam); | |
11101 | if (rc) { | |
51c1a580 MS |
11102 | BNX2X_ERR("Failed to create multicast MACs list: %d\n", |
11103 | rc); | |
619c5cb6 VZ |
11104 | return rc; |
11105 | } | |
6e30dd4e | 11106 | |
619c5cb6 VZ |
11107 | /* Now add the new MACs */ |
11108 | rc = bnx2x_config_mcast(bp, &rparam, | |
11109 | BNX2X_MCAST_CMD_ADD); | |
11110 | if (rc < 0) | |
51c1a580 MS |
11111 | BNX2X_ERR("Failed to set a new multicast configuration: %d\n", |
11112 | rc); | |
6e30dd4e | 11113 | |
619c5cb6 VZ |
11114 | bnx2x_free_mcast_macs_list(&rparam); |
11115 | } | |
6e30dd4e | 11116 | |
619c5cb6 | 11117 | return rc; |
6e30dd4e VZ |
11118 | } |
11119 | ||
6e30dd4e | 11120 | |
619c5cb6 | 11121 | /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ |
9f6c9258 | 11122 | void bnx2x_set_rx_mode(struct net_device *dev) |
34f80b04 EG |
11123 | { |
11124 | struct bnx2x *bp = netdev_priv(dev); | |
11125 | u32 rx_mode = BNX2X_RX_MODE_NORMAL; | |
34f80b04 EG |
11126 | |
11127 | if (bp->state != BNX2X_STATE_OPEN) { | |
11128 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); | |
11129 | return; | |
11130 | } | |
11131 | ||
619c5cb6 | 11132 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); |
34f80b04 EG |
11133 | |
11134 | if (dev->flags & IFF_PROMISC) | |
11135 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
619c5cb6 VZ |
11136 | else if ((dev->flags & IFF_ALLMULTI) || |
11137 | ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && | |
11138 | CHIP_IS_E1(bp))) | |
34f80b04 | 11139 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
6e30dd4e VZ |
11140 | else { |
11141 | /* some multicasts */ | |
619c5cb6 | 11142 | if (bnx2x_set_mc_list(bp) < 0) |
6e30dd4e | 11143 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
34f80b04 | 11144 | |
619c5cb6 | 11145 | if (bnx2x_set_uc_list(bp) < 0) |
6e30dd4e | 11146 | rx_mode = BNX2X_RX_MODE_PROMISC; |
34f80b04 EG |
11147 | } |
11148 | ||
11149 | bp->rx_mode = rx_mode; | |
614c76df DK |
11150 | #ifdef BCM_CNIC |
11151 | /* handle ISCSI SD mode */ | |
11152 | if (IS_MF_ISCSI_SD(bp)) | |
11153 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
11154 | #endif | |
619c5cb6 VZ |
11155 | |
11156 | /* Schedule the rx_mode command */ | |
11157 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { | |
11158 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
11159 | return; | |
11160 | } | |
11161 | ||
34f80b04 EG |
11162 | bnx2x_set_storm_rx_mode(bp); |
11163 | } | |
11164 | ||
c18487ee | 11165 | /* called with rtnl_lock */ |
01cd4528 EG |
11166 | static int bnx2x_mdio_read(struct net_device *netdev, int prtad, |
11167 | int devad, u16 addr) | |
a2fbb9ea | 11168 | { |
01cd4528 EG |
11169 | struct bnx2x *bp = netdev_priv(netdev); |
11170 | u16 value; | |
11171 | int rc; | |
a2fbb9ea | 11172 | |
01cd4528 EG |
11173 | DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", |
11174 | prtad, devad, addr); | |
a2fbb9ea | 11175 | |
01cd4528 EG |
11176 | /* The HW expects different devad if CL22 is used */ |
11177 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
c18487ee | 11178 | |
01cd4528 | 11179 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 11180 | rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); |
01cd4528 EG |
11181 | bnx2x_release_phy_lock(bp); |
11182 | DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); | |
a2fbb9ea | 11183 | |
01cd4528 EG |
11184 | if (!rc) |
11185 | rc = value; | |
11186 | return rc; | |
11187 | } | |
a2fbb9ea | 11188 | |
01cd4528 EG |
11189 | /* called with rtnl_lock */ |
11190 | static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, | |
11191 | u16 addr, u16 value) | |
11192 | { | |
11193 | struct bnx2x *bp = netdev_priv(netdev); | |
01cd4528 EG |
11194 | int rc; |
11195 | ||
51c1a580 MS |
11196 | DP(NETIF_MSG_LINK, |
11197 | "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", | |
11198 | prtad, devad, addr, value); | |
01cd4528 | 11199 | |
01cd4528 EG |
11200 | /* The HW expects different devad if CL22 is used */ |
11201 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
a2fbb9ea | 11202 | |
01cd4528 | 11203 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 11204 | rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); |
01cd4528 EG |
11205 | bnx2x_release_phy_lock(bp); |
11206 | return rc; | |
11207 | } | |
c18487ee | 11208 | |
01cd4528 EG |
11209 | /* called with rtnl_lock */ |
11210 | static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
11211 | { | |
11212 | struct bnx2x *bp = netdev_priv(dev); | |
11213 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
a2fbb9ea | 11214 | |
01cd4528 EG |
11215 | DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", |
11216 | mdio->phy_id, mdio->reg_num, mdio->val_in); | |
a2fbb9ea | 11217 | |
01cd4528 EG |
11218 | if (!netif_running(dev)) |
11219 | return -EAGAIN; | |
11220 | ||
11221 | return mdio_mii_ioctl(&bp->mdio, mdio, cmd); | |
a2fbb9ea ET |
11222 | } |
11223 | ||
257ddbda | 11224 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a2fbb9ea ET |
11225 | static void poll_bnx2x(struct net_device *dev) |
11226 | { | |
11227 | struct bnx2x *bp = netdev_priv(dev); | |
11228 | ||
11229 | disable_irq(bp->pdev->irq); | |
11230 | bnx2x_interrupt(bp->pdev->irq, dev); | |
11231 | enable_irq(bp->pdev->irq); | |
11232 | } | |
11233 | #endif | |
11234 | ||
614c76df DK |
11235 | static int bnx2x_validate_addr(struct net_device *dev) |
11236 | { | |
11237 | struct bnx2x *bp = netdev_priv(dev); | |
11238 | ||
51c1a580 MS |
11239 | if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) { |
11240 | BNX2X_ERR("Non-valid Ethernet address\n"); | |
614c76df | 11241 | return -EADDRNOTAVAIL; |
51c1a580 | 11242 | } |
614c76df DK |
11243 | return 0; |
11244 | } | |
11245 | ||
c64213cd SH |
11246 | static const struct net_device_ops bnx2x_netdev_ops = { |
11247 | .ndo_open = bnx2x_open, | |
11248 | .ndo_stop = bnx2x_close, | |
11249 | .ndo_start_xmit = bnx2x_start_xmit, | |
8307fa3e | 11250 | .ndo_select_queue = bnx2x_select_queue, |
6e30dd4e | 11251 | .ndo_set_rx_mode = bnx2x_set_rx_mode, |
c64213cd | 11252 | .ndo_set_mac_address = bnx2x_change_mac_addr, |
614c76df | 11253 | .ndo_validate_addr = bnx2x_validate_addr, |
c64213cd SH |
11254 | .ndo_do_ioctl = bnx2x_ioctl, |
11255 | .ndo_change_mtu = bnx2x_change_mtu, | |
66371c44 MM |
11256 | .ndo_fix_features = bnx2x_fix_features, |
11257 | .ndo_set_features = bnx2x_set_features, | |
c64213cd | 11258 | .ndo_tx_timeout = bnx2x_tx_timeout, |
257ddbda | 11259 | #ifdef CONFIG_NET_POLL_CONTROLLER |
c64213cd SH |
11260 | .ndo_poll_controller = poll_bnx2x, |
11261 | #endif | |
6383c0b3 AE |
11262 | .ndo_setup_tc = bnx2x_setup_tc, |
11263 | ||
bf61ee14 VZ |
11264 | #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) |
11265 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, | |
11266 | #endif | |
c64213cd SH |
11267 | }; |
11268 | ||
1191cb83 | 11269 | static int bnx2x_set_coherency_mask(struct bnx2x *bp) |
619c5cb6 VZ |
11270 | { |
11271 | struct device *dev = &bp->pdev->dev; | |
11272 | ||
11273 | if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { | |
11274 | bp->flags |= USING_DAC_FLAG; | |
11275 | if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { | |
51c1a580 | 11276 | dev_err(dev, "dma_set_coherent_mask failed, aborting\n"); |
619c5cb6 VZ |
11277 | return -EIO; |
11278 | } | |
11279 | } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { | |
11280 | dev_err(dev, "System does not support DMA, aborting\n"); | |
11281 | return -EIO; | |
11282 | } | |
11283 | ||
11284 | return 0; | |
11285 | } | |
11286 | ||
34f80b04 | 11287 | static int __devinit bnx2x_init_dev(struct pci_dev *pdev, |
619c5cb6 VZ |
11288 | struct net_device *dev, |
11289 | unsigned long board_type) | |
a2fbb9ea ET |
11290 | { |
11291 | struct bnx2x *bp; | |
11292 | int rc; | |
c22610d0 | 11293 | u32 pci_cfg_dword; |
65087cfe AE |
11294 | bool chip_is_e1x = (board_type == BCM57710 || |
11295 | board_type == BCM57711 || | |
11296 | board_type == BCM57711E); | |
a2fbb9ea ET |
11297 | |
11298 | SET_NETDEV_DEV(dev, &pdev->dev); | |
11299 | bp = netdev_priv(dev); | |
11300 | ||
34f80b04 EG |
11301 | bp->dev = dev; |
11302 | bp->pdev = pdev; | |
a2fbb9ea | 11303 | bp->flags = 0; |
a2fbb9ea ET |
11304 | |
11305 | rc = pci_enable_device(pdev); | |
11306 | if (rc) { | |
cdaa7cb8 VZ |
11307 | dev_err(&bp->pdev->dev, |
11308 | "Cannot enable PCI device, aborting\n"); | |
a2fbb9ea ET |
11309 | goto err_out; |
11310 | } | |
11311 | ||
11312 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
11313 | dev_err(&bp->pdev->dev, |
11314 | "Cannot find PCI device base address, aborting\n"); | |
a2fbb9ea ET |
11315 | rc = -ENODEV; |
11316 | goto err_out_disable; | |
11317 | } | |
11318 | ||
11319 | if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
11320 | dev_err(&bp->pdev->dev, "Cannot find second PCI device" |
11321 | " base address, aborting\n"); | |
a2fbb9ea ET |
11322 | rc = -ENODEV; |
11323 | goto err_out_disable; | |
11324 | } | |
11325 | ||
34f80b04 EG |
11326 | if (atomic_read(&pdev->enable_cnt) == 1) { |
11327 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
11328 | if (rc) { | |
cdaa7cb8 VZ |
11329 | dev_err(&bp->pdev->dev, |
11330 | "Cannot obtain PCI resources, aborting\n"); | |
34f80b04 EG |
11331 | goto err_out_disable; |
11332 | } | |
a2fbb9ea | 11333 | |
34f80b04 EG |
11334 | pci_set_master(pdev); |
11335 | pci_save_state(pdev); | |
11336 | } | |
a2fbb9ea ET |
11337 | |
11338 | bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
11339 | if (bp->pm_cap == 0) { | |
cdaa7cb8 VZ |
11340 | dev_err(&bp->pdev->dev, |
11341 | "Cannot find power management capability, aborting\n"); | |
a2fbb9ea ET |
11342 | rc = -EIO; |
11343 | goto err_out_release; | |
11344 | } | |
11345 | ||
77c98e6a | 11346 | if (!pci_is_pcie(pdev)) { |
51c1a580 | 11347 | dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); |
a2fbb9ea ET |
11348 | rc = -EIO; |
11349 | goto err_out_release; | |
11350 | } | |
11351 | ||
619c5cb6 VZ |
11352 | rc = bnx2x_set_coherency_mask(bp); |
11353 | if (rc) | |
a2fbb9ea | 11354 | goto err_out_release; |
a2fbb9ea | 11355 | |
34f80b04 EG |
11356 | dev->mem_start = pci_resource_start(pdev, 0); |
11357 | dev->base_addr = dev->mem_start; | |
11358 | dev->mem_end = pci_resource_end(pdev, 0); | |
a2fbb9ea ET |
11359 | |
11360 | dev->irq = pdev->irq; | |
11361 | ||
275f165f | 11362 | bp->regview = pci_ioremap_bar(pdev, 0); |
a2fbb9ea | 11363 | if (!bp->regview) { |
cdaa7cb8 VZ |
11364 | dev_err(&bp->pdev->dev, |
11365 | "Cannot map register space, aborting\n"); | |
a2fbb9ea ET |
11366 | rc = -ENOMEM; |
11367 | goto err_out_release; | |
11368 | } | |
11369 | ||
c22610d0 AE |
11370 | /* In E1/E1H use pci device function given by kernel. |
11371 | * In E2/E3 read physical function from ME register since these chips | |
11372 | * support Physical Device Assignment where kernel BDF maybe arbitrary | |
11373 | * (depending on hypervisor). | |
11374 | */ | |
11375 | if (chip_is_e1x) | |
11376 | bp->pf_num = PCI_FUNC(pdev->devfn); | |
11377 | else {/* chip is E2/3*/ | |
11378 | pci_read_config_dword(bp->pdev, | |
11379 | PCICFG_ME_REGISTER, &pci_cfg_dword); | |
11380 | bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> | |
11381 | ME_REG_ABS_PF_NUM_SHIFT); | |
11382 | } | |
51c1a580 | 11383 | BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); |
c22610d0 | 11384 | |
a2fbb9ea ET |
11385 | bnx2x_set_power_state(bp, PCI_D0); |
11386 | ||
34f80b04 EG |
11387 | /* clean indirect addresses */ |
11388 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
11389 | PCICFG_VENDOR_ID_OFFSET); | |
a5c53dbc DK |
11390 | /* |
11391 | * Clean the following indirect addresses for all functions since it | |
9f0096a1 DK |
11392 | * is not used by the driver. |
11393 | */ | |
11394 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); | |
11395 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); | |
11396 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); | |
11397 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); | |
a5c53dbc | 11398 | |
65087cfe | 11399 | if (chip_is_e1x) { |
a5c53dbc DK |
11400 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); |
11401 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); | |
11402 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); | |
11403 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); | |
11404 | } | |
a2fbb9ea | 11405 | |
2189400b | 11406 | /* |
619c5cb6 | 11407 | * Enable internal target-read (in case we are probed after PF FLR). |
2189400b | 11408 | * Must be done prior to any BAR read access. Only for 57712 and up |
619c5cb6 | 11409 | */ |
65087cfe | 11410 | if (!chip_is_e1x) |
2189400b | 11411 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); |
619c5cb6 | 11412 | |
72fd0718 | 11413 | /* Reset the load counter */ |
889b9af3 | 11414 | bnx2x_clear_load_status(bp); |
72fd0718 | 11415 | |
34f80b04 | 11416 | dev->watchdog_timeo = TX_TIMEOUT; |
a2fbb9ea | 11417 | |
c64213cd | 11418 | dev->netdev_ops = &bnx2x_netdev_ops; |
de0c62db | 11419 | bnx2x_set_ethtool_ops(dev); |
5316bc0b | 11420 | |
01789349 JP |
11421 | dev->priv_flags |= IFF_UNICAST_FLT; |
11422 | ||
66371c44 | 11423 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
621b4d66 DK |
11424 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | |
11425 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | | |
11426 | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; | |
66371c44 MM |
11427 | |
11428 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
11429 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; | |
11430 | ||
11431 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; | |
5316bc0b | 11432 | if (bp->flags & USING_DAC_FLAG) |
66371c44 | 11433 | dev->features |= NETIF_F_HIGHDMA; |
a2fbb9ea | 11434 | |
538dd2e3 MB |
11435 | /* Add Loopback capability to the device */ |
11436 | dev->hw_features |= NETIF_F_LOOPBACK; | |
11437 | ||
98507672 | 11438 | #ifdef BCM_DCBNL |
785b9b1a SR |
11439 | dev->dcbnl_ops = &bnx2x_dcbnl_ops; |
11440 | #endif | |
11441 | ||
01cd4528 EG |
11442 | /* get_port_hwinfo() will set prtad and mmds properly */ |
11443 | bp->mdio.prtad = MDIO_PRTAD_NONE; | |
11444 | bp->mdio.mmds = 0; | |
11445 | bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
11446 | bp->mdio.dev = dev; | |
11447 | bp->mdio.mdio_read = bnx2x_mdio_read; | |
11448 | bp->mdio.mdio_write = bnx2x_mdio_write; | |
11449 | ||
a2fbb9ea ET |
11450 | return 0; |
11451 | ||
a2fbb9ea | 11452 | err_out_release: |
34f80b04 EG |
11453 | if (atomic_read(&pdev->enable_cnt) == 1) |
11454 | pci_release_regions(pdev); | |
a2fbb9ea ET |
11455 | |
11456 | err_out_disable: | |
11457 | pci_disable_device(pdev); | |
11458 | pci_set_drvdata(pdev, NULL); | |
11459 | ||
11460 | err_out: | |
11461 | return rc; | |
11462 | } | |
11463 | ||
37f9ce62 EG |
11464 | static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, |
11465 | int *width, int *speed) | |
25047950 ET |
11466 | { |
11467 | u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); | |
11468 | ||
37f9ce62 | 11469 | *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; |
25047950 | 11470 | |
37f9ce62 EG |
11471 | /* return value of 1=2.5GHz 2=5GHz */ |
11472 | *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; | |
25047950 | 11473 | } |
37f9ce62 | 11474 | |
6891dd25 | 11475 | static int bnx2x_check_firmware(struct bnx2x *bp) |
94a78b79 | 11476 | { |
37f9ce62 | 11477 | const struct firmware *firmware = bp->firmware; |
94a78b79 VZ |
11478 | struct bnx2x_fw_file_hdr *fw_hdr; |
11479 | struct bnx2x_fw_file_section *sections; | |
94a78b79 | 11480 | u32 offset, len, num_ops; |
37f9ce62 | 11481 | u16 *ops_offsets; |
94a78b79 | 11482 | int i; |
37f9ce62 | 11483 | const u8 *fw_ver; |
94a78b79 | 11484 | |
51c1a580 MS |
11485 | if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { |
11486 | BNX2X_ERR("Wrong FW size\n"); | |
94a78b79 | 11487 | return -EINVAL; |
51c1a580 | 11488 | } |
94a78b79 VZ |
11489 | |
11490 | fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; | |
11491 | sections = (struct bnx2x_fw_file_section *)fw_hdr; | |
11492 | ||
11493 | /* Make sure none of the offsets and sizes make us read beyond | |
11494 | * the end of the firmware data */ | |
11495 | for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { | |
11496 | offset = be32_to_cpu(sections[i].offset); | |
11497 | len = be32_to_cpu(sections[i].len); | |
11498 | if (offset + len > firmware->size) { | |
51c1a580 | 11499 | BNX2X_ERR("Section %d length is out of bounds\n", i); |
94a78b79 VZ |
11500 | return -EINVAL; |
11501 | } | |
11502 | } | |
11503 | ||
11504 | /* Likewise for the init_ops offsets */ | |
11505 | offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); | |
11506 | ops_offsets = (u16 *)(firmware->data + offset); | |
11507 | num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); | |
11508 | ||
11509 | for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { | |
11510 | if (be16_to_cpu(ops_offsets[i]) > num_ops) { | |
51c1a580 | 11511 | BNX2X_ERR("Section offset %d is out of bounds\n", i); |
94a78b79 VZ |
11512 | return -EINVAL; |
11513 | } | |
11514 | } | |
11515 | ||
11516 | /* Check FW version */ | |
11517 | offset = be32_to_cpu(fw_hdr->fw_version.offset); | |
11518 | fw_ver = firmware->data + offset; | |
11519 | if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || | |
11520 | (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || | |
11521 | (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || | |
11522 | (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { | |
51c1a580 MS |
11523 | BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", |
11524 | fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], | |
11525 | BCM_5710_FW_MAJOR_VERSION, | |
94a78b79 VZ |
11526 | BCM_5710_FW_MINOR_VERSION, |
11527 | BCM_5710_FW_REVISION_VERSION, | |
11528 | BCM_5710_FW_ENGINEERING_VERSION); | |
ab6ad5a4 | 11529 | return -EINVAL; |
94a78b79 VZ |
11530 | } |
11531 | ||
11532 | return 0; | |
11533 | } | |
11534 | ||
1191cb83 | 11535 | static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 11536 | { |
ab6ad5a4 EG |
11537 | const __be32 *source = (const __be32 *)_source; |
11538 | u32 *target = (u32 *)_target; | |
94a78b79 | 11539 | u32 i; |
94a78b79 VZ |
11540 | |
11541 | for (i = 0; i < n/4; i++) | |
11542 | target[i] = be32_to_cpu(source[i]); | |
11543 | } | |
11544 | ||
11545 | /* | |
11546 | Ops array is stored in the following format: | |
11547 | {op(8bit), offset(24bit, big endian), data(32bit, big endian)} | |
11548 | */ | |
1191cb83 | 11549 | static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 11550 | { |
ab6ad5a4 EG |
11551 | const __be32 *source = (const __be32 *)_source; |
11552 | struct raw_op *target = (struct raw_op *)_target; | |
94a78b79 | 11553 | u32 i, j, tmp; |
94a78b79 | 11554 | |
ab6ad5a4 | 11555 | for (i = 0, j = 0; i < n/8; i++, j += 2) { |
94a78b79 VZ |
11556 | tmp = be32_to_cpu(source[j]); |
11557 | target[i].op = (tmp >> 24) & 0xff; | |
cdaa7cb8 VZ |
11558 | target[i].offset = tmp & 0xffffff; |
11559 | target[i].raw_data = be32_to_cpu(source[j + 1]); | |
94a78b79 VZ |
11560 | } |
11561 | } | |
ab6ad5a4 | 11562 | |
1aa8b471 | 11563 | /* IRO array is stored in the following format: |
523224a3 DK |
11564 | * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } |
11565 | */ | |
1191cb83 | 11566 | static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) |
523224a3 DK |
11567 | { |
11568 | const __be32 *source = (const __be32 *)_source; | |
11569 | struct iro *target = (struct iro *)_target; | |
11570 | u32 i, j, tmp; | |
11571 | ||
11572 | for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { | |
11573 | target[i].base = be32_to_cpu(source[j]); | |
11574 | j++; | |
11575 | tmp = be32_to_cpu(source[j]); | |
11576 | target[i].m1 = (tmp >> 16) & 0xffff; | |
11577 | target[i].m2 = tmp & 0xffff; | |
11578 | j++; | |
11579 | tmp = be32_to_cpu(source[j]); | |
11580 | target[i].m3 = (tmp >> 16) & 0xffff; | |
11581 | target[i].size = tmp & 0xffff; | |
11582 | j++; | |
11583 | } | |
11584 | } | |
11585 | ||
1191cb83 | 11586 | static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 11587 | { |
ab6ad5a4 EG |
11588 | const __be16 *source = (const __be16 *)_source; |
11589 | u16 *target = (u16 *)_target; | |
94a78b79 | 11590 | u32 i; |
94a78b79 VZ |
11591 | |
11592 | for (i = 0; i < n/2; i++) | |
11593 | target[i] = be16_to_cpu(source[i]); | |
11594 | } | |
11595 | ||
7995c64e JP |
11596 | #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ |
11597 | do { \ | |
11598 | u32 len = be32_to_cpu(fw_hdr->arr.len); \ | |
11599 | bp->arr = kmalloc(len, GFP_KERNEL); \ | |
e404decb | 11600 | if (!bp->arr) \ |
7995c64e | 11601 | goto lbl; \ |
7995c64e JP |
11602 | func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ |
11603 | (u8 *)bp->arr, len); \ | |
11604 | } while (0) | |
94a78b79 | 11605 | |
3b603066 | 11606 | static int bnx2x_init_firmware(struct bnx2x *bp) |
94a78b79 | 11607 | { |
c0ea452e | 11608 | const char *fw_file_name; |
94a78b79 | 11609 | struct bnx2x_fw_file_hdr *fw_hdr; |
45229b42 | 11610 | int rc; |
94a78b79 | 11611 | |
c0ea452e MS |
11612 | if (bp->firmware) |
11613 | return 0; | |
94a78b79 | 11614 | |
c0ea452e MS |
11615 | if (CHIP_IS_E1(bp)) |
11616 | fw_file_name = FW_FILE_NAME_E1; | |
11617 | else if (CHIP_IS_E1H(bp)) | |
11618 | fw_file_name = FW_FILE_NAME_E1H; | |
11619 | else if (!CHIP_IS_E1x(bp)) | |
11620 | fw_file_name = FW_FILE_NAME_E2; | |
11621 | else { | |
11622 | BNX2X_ERR("Unsupported chip revision\n"); | |
11623 | return -EINVAL; | |
11624 | } | |
11625 | BNX2X_DEV_INFO("Loading %s\n", fw_file_name); | |
94a78b79 | 11626 | |
c0ea452e MS |
11627 | rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); |
11628 | if (rc) { | |
11629 | BNX2X_ERR("Can't load firmware file %s\n", | |
11630 | fw_file_name); | |
11631 | goto request_firmware_exit; | |
11632 | } | |
eb2afd4a | 11633 | |
c0ea452e MS |
11634 | rc = bnx2x_check_firmware(bp); |
11635 | if (rc) { | |
11636 | BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); | |
11637 | goto request_firmware_exit; | |
94a78b79 VZ |
11638 | } |
11639 | ||
11640 | fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; | |
11641 | ||
11642 | /* Initialize the pointers to the init arrays */ | |
11643 | /* Blob */ | |
11644 | BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); | |
11645 | ||
11646 | /* Opcodes */ | |
11647 | BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); | |
11648 | ||
11649 | /* Offsets */ | |
ab6ad5a4 EG |
11650 | BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, |
11651 | be16_to_cpu_n); | |
94a78b79 VZ |
11652 | |
11653 | /* STORMs firmware */ | |
573f2035 EG |
11654 | INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
11655 | be32_to_cpu(fw_hdr->tsem_int_table_data.offset); | |
11656 | INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + | |
11657 | be32_to_cpu(fw_hdr->tsem_pram_data.offset); | |
11658 | INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
11659 | be32_to_cpu(fw_hdr->usem_int_table_data.offset); | |
11660 | INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + | |
11661 | be32_to_cpu(fw_hdr->usem_pram_data.offset); | |
11662 | INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
11663 | be32_to_cpu(fw_hdr->xsem_int_table_data.offset); | |
11664 | INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + | |
11665 | be32_to_cpu(fw_hdr->xsem_pram_data.offset); | |
11666 | INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
11667 | be32_to_cpu(fw_hdr->csem_int_table_data.offset); | |
11668 | INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + | |
11669 | be32_to_cpu(fw_hdr->csem_pram_data.offset); | |
523224a3 DK |
11670 | /* IRO */ |
11671 | BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); | |
94a78b79 VZ |
11672 | |
11673 | return 0; | |
ab6ad5a4 | 11674 | |
523224a3 DK |
11675 | iro_alloc_err: |
11676 | kfree(bp->init_ops_offsets); | |
94a78b79 VZ |
11677 | init_offsets_alloc_err: |
11678 | kfree(bp->init_ops); | |
11679 | init_ops_alloc_err: | |
11680 | kfree(bp->init_data); | |
11681 | request_firmware_exit: | |
11682 | release_firmware(bp->firmware); | |
127d0a19 | 11683 | bp->firmware = NULL; |
94a78b79 VZ |
11684 | |
11685 | return rc; | |
11686 | } | |
11687 | ||
619c5cb6 VZ |
11688 | static void bnx2x_release_firmware(struct bnx2x *bp) |
11689 | { | |
11690 | kfree(bp->init_ops_offsets); | |
11691 | kfree(bp->init_ops); | |
11692 | kfree(bp->init_data); | |
11693 | release_firmware(bp->firmware); | |
eb2afd4a | 11694 | bp->firmware = NULL; |
619c5cb6 VZ |
11695 | } |
11696 | ||
11697 | ||
11698 | static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { | |
11699 | .init_hw_cmn_chip = bnx2x_init_hw_common_chip, | |
11700 | .init_hw_cmn = bnx2x_init_hw_common, | |
11701 | .init_hw_port = bnx2x_init_hw_port, | |
11702 | .init_hw_func = bnx2x_init_hw_func, | |
11703 | ||
11704 | .reset_hw_cmn = bnx2x_reset_common, | |
11705 | .reset_hw_port = bnx2x_reset_port, | |
11706 | .reset_hw_func = bnx2x_reset_func, | |
11707 | ||
11708 | .gunzip_init = bnx2x_gunzip_init, | |
11709 | .gunzip_end = bnx2x_gunzip_end, | |
11710 | ||
11711 | .init_fw = bnx2x_init_firmware, | |
11712 | .release_fw = bnx2x_release_firmware, | |
11713 | }; | |
11714 | ||
11715 | void bnx2x__init_func_obj(struct bnx2x *bp) | |
11716 | { | |
11717 | /* Prepare DMAE related driver resources */ | |
11718 | bnx2x_setup_dmae(bp); | |
11719 | ||
11720 | bnx2x_init_func_obj(bp, &bp->func_obj, | |
11721 | bnx2x_sp(bp, func_rdata), | |
11722 | bnx2x_sp_mapping(bp, func_rdata), | |
a3348722 BW |
11723 | bnx2x_sp(bp, func_afex_rdata), |
11724 | bnx2x_sp_mapping(bp, func_afex_rdata), | |
619c5cb6 VZ |
11725 | &bnx2x_func_sp_drv); |
11726 | } | |
11727 | ||
11728 | /* must be called after sriov-enable */ | |
1191cb83 | 11729 | static int bnx2x_set_qm_cid_count(struct bnx2x *bp) |
523224a3 | 11730 | { |
37ae41a9 | 11731 | int cid_count = BNX2X_L2_MAX_CID(bp); |
94a78b79 | 11732 | |
523224a3 DK |
11733 | #ifdef BCM_CNIC |
11734 | cid_count += CNIC_CID_MAX; | |
11735 | #endif | |
11736 | return roundup(cid_count, QM_CID_ROUND); | |
11737 | } | |
f85582f8 | 11738 | |
619c5cb6 | 11739 | /** |
6383c0b3 | 11740 | * bnx2x_get_num_none_def_sbs - return the number of none default SBs |
619c5cb6 VZ |
11741 | * |
11742 | * @dev: pci device | |
11743 | * | |
11744 | */ | |
1191cb83 | 11745 | static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) |
619c5cb6 VZ |
11746 | { |
11747 | int pos; | |
11748 | u16 control; | |
11749 | ||
11750 | pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); | |
6383c0b3 AE |
11751 | |
11752 | /* | |
11753 | * If MSI-X is not supported - return number of SBs needed to support | |
11754 | * one fast path queue: one FP queue + SB for CNIC | |
11755 | */ | |
619c5cb6 | 11756 | if (!pos) |
6383c0b3 | 11757 | return 1 + CNIC_PRESENT; |
619c5cb6 | 11758 | |
6383c0b3 AE |
11759 | /* |
11760 | * The value in the PCI configuration space is the index of the last | |
11761 | * entry, namely one less than the actual size of the table, which is | |
11762 | * exactly what we want to return from this function: number of all SBs | |
11763 | * without the default SB. | |
11764 | */ | |
619c5cb6 | 11765 | pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); |
6383c0b3 | 11766 | return control & PCI_MSIX_FLAGS_QSIZE; |
619c5cb6 VZ |
11767 | } |
11768 | ||
a2fbb9ea ET |
11769 | static int __devinit bnx2x_init_one(struct pci_dev *pdev, |
11770 | const struct pci_device_id *ent) | |
11771 | { | |
a2fbb9ea ET |
11772 | struct net_device *dev = NULL; |
11773 | struct bnx2x *bp; | |
37f9ce62 | 11774 | int pcie_width, pcie_speed; |
6383c0b3 | 11775 | int rc, max_non_def_sbs; |
65565884 | 11776 | int rx_count, tx_count, rss_count, doorbell_size; |
6383c0b3 AE |
11777 | /* |
11778 | * An estimated maximum supported CoS number according to the chip | |
11779 | * version. | |
11780 | * We will try to roughly estimate the maximum number of CoSes this chip | |
11781 | * may support in order to minimize the memory allocated for Tx | |
11782 | * netdev_queue's. This number will be accurately calculated during the | |
11783 | * initialization of bp->max_cos based on the chip versions AND chip | |
11784 | * revision in the bnx2x_init_bp(). | |
11785 | */ | |
11786 | u8 max_cos_est = 0; | |
523224a3 | 11787 | |
f2e0899f DK |
11788 | switch (ent->driver_data) { |
11789 | case BCM57710: | |
11790 | case BCM57711: | |
11791 | case BCM57711E: | |
6383c0b3 AE |
11792 | max_cos_est = BNX2X_MULTI_TX_COS_E1X; |
11793 | break; | |
11794 | ||
f2e0899f | 11795 | case BCM57712: |
619c5cb6 | 11796 | case BCM57712_MF: |
6383c0b3 AE |
11797 | max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; |
11798 | break; | |
11799 | ||
619c5cb6 VZ |
11800 | case BCM57800: |
11801 | case BCM57800_MF: | |
11802 | case BCM57810: | |
11803 | case BCM57810_MF: | |
11804 | case BCM57840: | |
11805 | case BCM57840_MF: | |
7e8e02df BW |
11806 | case BCM57811: |
11807 | case BCM57811_MF: | |
6383c0b3 | 11808 | max_cos_est = BNX2X_MULTI_TX_COS_E3B0; |
f2e0899f | 11809 | break; |
a2fbb9ea | 11810 | |
f2e0899f DK |
11811 | default: |
11812 | pr_err("Unknown board_type (%ld), aborting\n", | |
11813 | ent->driver_data); | |
870634b0 | 11814 | return -ENODEV; |
f2e0899f DK |
11815 | } |
11816 | ||
6383c0b3 AE |
11817 | max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); |
11818 | ||
6383c0b3 AE |
11819 | WARN_ON(!max_non_def_sbs); |
11820 | ||
11821 | /* Maximum number of RSS queues: one IGU SB goes to CNIC */ | |
11822 | rss_count = max_non_def_sbs - CNIC_PRESENT; | |
11823 | ||
11824 | /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ | |
11825 | rx_count = rss_count + FCOE_PRESENT; | |
11826 | ||
11827 | /* | |
11828 | * Maximum number of netdev Tx queues: | |
37ae41a9 | 11829 | * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 |
6383c0b3 | 11830 | */ |
37ae41a9 | 11831 | tx_count = rss_count * max_cos_est + FCOE_PRESENT; |
f85582f8 | 11832 | |
a2fbb9ea | 11833 | /* dev zeroed in init_etherdev */ |
6383c0b3 | 11834 | dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); |
41de8d4c | 11835 | if (!dev) |
a2fbb9ea ET |
11836 | return -ENOMEM; |
11837 | ||
a2fbb9ea | 11838 | bp = netdev_priv(dev); |
a2fbb9ea | 11839 | |
6383c0b3 AE |
11840 | bp->igu_sb_cnt = max_non_def_sbs; |
11841 | bp->msg_enable = debug; | |
11842 | pci_set_drvdata(pdev, dev); | |
523224a3 | 11843 | |
619c5cb6 | 11844 | rc = bnx2x_init_dev(pdev, dev, ent->driver_data); |
a2fbb9ea ET |
11845 | if (rc < 0) { |
11846 | free_netdev(dev); | |
11847 | return rc; | |
11848 | } | |
11849 | ||
51c1a580 | 11850 | BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs); |
619c5cb6 | 11851 | |
60aa0509 MS |
11852 | BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", |
11853 | tx_count, rx_count); | |
11854 | ||
34f80b04 | 11855 | rc = bnx2x_init_bp(bp); |
693fc0d1 EG |
11856 | if (rc) |
11857 | goto init_one_exit; | |
11858 | ||
6383c0b3 AE |
11859 | /* |
11860 | * Map doorbels here as we need the real value of bp->max_cos which | |
11861 | * is initialized in bnx2x_init_bp(). | |
11862 | */ | |
37ae41a9 MS |
11863 | doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); |
11864 | if (doorbell_size > pci_resource_len(pdev, 2)) { | |
11865 | dev_err(&bp->pdev->dev, | |
11866 | "Cannot map doorbells, bar size too small, aborting\n"); | |
11867 | rc = -ENOMEM; | |
11868 | goto init_one_exit; | |
11869 | } | |
6383c0b3 | 11870 | bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), |
37ae41a9 | 11871 | doorbell_size); |
6383c0b3 AE |
11872 | if (!bp->doorbells) { |
11873 | dev_err(&bp->pdev->dev, | |
11874 | "Cannot map doorbell space, aborting\n"); | |
11875 | rc = -ENOMEM; | |
11876 | goto init_one_exit; | |
11877 | } | |
11878 | ||
523224a3 | 11879 | /* calc qm_cid_count */ |
6383c0b3 | 11880 | bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); |
523224a3 | 11881 | |
ec6ba945 | 11882 | #ifdef BCM_CNIC |
62ac0dc9 DK |
11883 | /* disable FCOE L2 queue for E1x */ |
11884 | if (CHIP_IS_E1x(bp)) | |
ec6ba945 VZ |
11885 | bp->flags |= NO_FCOE_FLAG; |
11886 | ||
11887 | #endif | |
11888 | ||
0e8d2ec5 MS |
11889 | |
11890 | /* Set bp->num_queues for MSI-X mode*/ | |
11891 | bnx2x_set_num_queues(bp); | |
11892 | ||
25985edc | 11893 | /* Configure interrupt mode: try to enable MSI-X/MSI if |
0e8d2ec5 | 11894 | * needed. |
d6214d7a DK |
11895 | */ |
11896 | bnx2x_set_int_mode(bp); | |
11897 | ||
11898 | /* Add all NAPI objects */ | |
11899 | bnx2x_add_all_napi(bp); | |
11900 | ||
b340007f VZ |
11901 | rc = register_netdev(dev); |
11902 | if (rc) { | |
11903 | dev_err(&pdev->dev, "Cannot register net device\n"); | |
11904 | goto init_one_exit; | |
11905 | } | |
11906 | ||
ec6ba945 VZ |
11907 | #ifdef BCM_CNIC |
11908 | if (!NO_FCOE(bp)) { | |
11909 | /* Add storage MAC address */ | |
11910 | rtnl_lock(); | |
11911 | dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
11912 | rtnl_unlock(); | |
11913 | } | |
11914 | #endif | |
11915 | ||
37f9ce62 | 11916 | bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); |
d6214d7a | 11917 | |
51c1a580 MS |
11918 | BNX2X_DEV_INFO( |
11919 | "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", | |
94f05b0f JP |
11920 | board_info[ent->driver_data].name, |
11921 | (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), | |
11922 | pcie_width, | |
11923 | ((!CHIP_IS_E2(bp) && pcie_speed == 2) || | |
11924 | (CHIP_IS_E2(bp) && pcie_speed == 1)) ? | |
11925 | "5GHz (Gen2)" : "2.5GHz", | |
11926 | dev->base_addr, bp->pdev->irq, dev->dev_addr); | |
c016201c | 11927 | |
a2fbb9ea | 11928 | return 0; |
34f80b04 EG |
11929 | |
11930 | init_one_exit: | |
11931 | if (bp->regview) | |
11932 | iounmap(bp->regview); | |
11933 | ||
11934 | if (bp->doorbells) | |
11935 | iounmap(bp->doorbells); | |
11936 | ||
11937 | free_netdev(dev); | |
11938 | ||
11939 | if (atomic_read(&pdev->enable_cnt) == 1) | |
11940 | pci_release_regions(pdev); | |
11941 | ||
11942 | pci_disable_device(pdev); | |
11943 | pci_set_drvdata(pdev, NULL); | |
11944 | ||
11945 | return rc; | |
a2fbb9ea ET |
11946 | } |
11947 | ||
11948 | static void __devexit bnx2x_remove_one(struct pci_dev *pdev) | |
11949 | { | |
11950 | struct net_device *dev = pci_get_drvdata(pdev); | |
228241eb ET |
11951 | struct bnx2x *bp; |
11952 | ||
11953 | if (!dev) { | |
cdaa7cb8 | 11954 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); |
228241eb ET |
11955 | return; |
11956 | } | |
228241eb | 11957 | bp = netdev_priv(dev); |
a2fbb9ea | 11958 | |
ec6ba945 VZ |
11959 | #ifdef BCM_CNIC |
11960 | /* Delete storage MAC address */ | |
11961 | if (!NO_FCOE(bp)) { | |
11962 | rtnl_lock(); | |
11963 | dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
11964 | rtnl_unlock(); | |
11965 | } | |
11966 | #endif | |
11967 | ||
98507672 SR |
11968 | #ifdef BCM_DCBNL |
11969 | /* Delete app tlvs from dcbnl */ | |
11970 | bnx2x_dcbnl_update_applist(bp, true); | |
11971 | #endif | |
11972 | ||
a2fbb9ea ET |
11973 | unregister_netdev(dev); |
11974 | ||
d6214d7a DK |
11975 | /* Delete all NAPI objects */ |
11976 | bnx2x_del_all_napi(bp); | |
11977 | ||
084d6cbb VZ |
11978 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
11979 | bnx2x_set_power_state(bp, PCI_D0); | |
11980 | ||
d6214d7a DK |
11981 | /* Disable MSI/MSI-X */ |
11982 | bnx2x_disable_msi(bp); | |
f85582f8 | 11983 | |
084d6cbb VZ |
11984 | /* Power off */ |
11985 | bnx2x_set_power_state(bp, PCI_D3hot); | |
11986 | ||
72fd0718 | 11987 | /* Make sure RESET task is not scheduled before continuing */ |
7be08a72 | 11988 | cancel_delayed_work_sync(&bp->sp_rtnl_task); |
72fd0718 | 11989 | |
a2fbb9ea ET |
11990 | if (bp->regview) |
11991 | iounmap(bp->regview); | |
11992 | ||
11993 | if (bp->doorbells) | |
11994 | iounmap(bp->doorbells); | |
11995 | ||
eb2afd4a DK |
11996 | bnx2x_release_firmware(bp); |
11997 | ||
523224a3 DK |
11998 | bnx2x_free_mem_bp(bp); |
11999 | ||
a2fbb9ea | 12000 | free_netdev(dev); |
34f80b04 EG |
12001 | |
12002 | if (atomic_read(&pdev->enable_cnt) == 1) | |
12003 | pci_release_regions(pdev); | |
12004 | ||
a2fbb9ea ET |
12005 | pci_disable_device(pdev); |
12006 | pci_set_drvdata(pdev, NULL); | |
12007 | } | |
12008 | ||
f8ef6e44 YG |
12009 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
12010 | { | |
12011 | int i; | |
12012 | ||
12013 | bp->state = BNX2X_STATE_ERROR; | |
12014 | ||
12015 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
12016 | ||
619c5cb6 VZ |
12017 | #ifdef BCM_CNIC |
12018 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); | |
12019 | #endif | |
12020 | /* Stop Tx */ | |
12021 | bnx2x_tx_disable(bp); | |
12022 | ||
f8ef6e44 YG |
12023 | bnx2x_netif_stop(bp, 0); |
12024 | ||
12025 | del_timer_sync(&bp->timer); | |
619c5cb6 VZ |
12026 | |
12027 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
f8ef6e44 YG |
12028 | |
12029 | /* Release IRQs */ | |
d6214d7a | 12030 | bnx2x_free_irq(bp); |
f8ef6e44 | 12031 | |
f8ef6e44 YG |
12032 | /* Free SKBs, SGEs, TPA pool and driver internals */ |
12033 | bnx2x_free_skbs(bp); | |
523224a3 | 12034 | |
ec6ba945 | 12035 | for_each_rx_queue(bp, i) |
f8ef6e44 | 12036 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); |
d6214d7a | 12037 | |
f8ef6e44 YG |
12038 | bnx2x_free_mem(bp); |
12039 | ||
12040 | bp->state = BNX2X_STATE_CLOSED; | |
12041 | ||
619c5cb6 VZ |
12042 | netif_carrier_off(bp->dev); |
12043 | ||
f8ef6e44 YG |
12044 | return 0; |
12045 | } | |
12046 | ||
12047 | static void bnx2x_eeh_recover(struct bnx2x *bp) | |
12048 | { | |
12049 | u32 val; | |
12050 | ||
12051 | mutex_init(&bp->port.phy_mutex); | |
12052 | ||
f8ef6e44 YG |
12053 | |
12054 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
12055 | if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
12056 | != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
12057 | BNX2X_ERR("BAD MCP validity signature\n"); | |
f8ef6e44 YG |
12058 | } |
12059 | ||
493adb1f WX |
12060 | /** |
12061 | * bnx2x_io_error_detected - called when PCI error is detected | |
12062 | * @pdev: Pointer to PCI device | |
12063 | * @state: The current pci connection state | |
12064 | * | |
12065 | * This function is called after a PCI bus error affecting | |
12066 | * this device has been detected. | |
12067 | */ | |
12068 | static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, | |
12069 | pci_channel_state_t state) | |
12070 | { | |
12071 | struct net_device *dev = pci_get_drvdata(pdev); | |
12072 | struct bnx2x *bp = netdev_priv(dev); | |
12073 | ||
12074 | rtnl_lock(); | |
12075 | ||
12076 | netif_device_detach(dev); | |
12077 | ||
07ce50e4 DN |
12078 | if (state == pci_channel_io_perm_failure) { |
12079 | rtnl_unlock(); | |
12080 | return PCI_ERS_RESULT_DISCONNECT; | |
12081 | } | |
12082 | ||
493adb1f | 12083 | if (netif_running(dev)) |
f8ef6e44 | 12084 | bnx2x_eeh_nic_unload(bp); |
493adb1f WX |
12085 | |
12086 | pci_disable_device(pdev); | |
12087 | ||
12088 | rtnl_unlock(); | |
12089 | ||
12090 | /* Request a slot reset */ | |
12091 | return PCI_ERS_RESULT_NEED_RESET; | |
12092 | } | |
12093 | ||
12094 | /** | |
12095 | * bnx2x_io_slot_reset - called after the PCI bus has been reset | |
12096 | * @pdev: Pointer to PCI device | |
12097 | * | |
12098 | * Restart the card from scratch, as if from a cold-boot. | |
12099 | */ | |
12100 | static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) | |
12101 | { | |
12102 | struct net_device *dev = pci_get_drvdata(pdev); | |
12103 | struct bnx2x *bp = netdev_priv(dev); | |
12104 | ||
12105 | rtnl_lock(); | |
12106 | ||
12107 | if (pci_enable_device(pdev)) { | |
12108 | dev_err(&pdev->dev, | |
12109 | "Cannot re-enable PCI device after reset\n"); | |
12110 | rtnl_unlock(); | |
12111 | return PCI_ERS_RESULT_DISCONNECT; | |
12112 | } | |
12113 | ||
12114 | pci_set_master(pdev); | |
12115 | pci_restore_state(pdev); | |
12116 | ||
12117 | if (netif_running(dev)) | |
12118 | bnx2x_set_power_state(bp, PCI_D0); | |
12119 | ||
12120 | rtnl_unlock(); | |
12121 | ||
12122 | return PCI_ERS_RESULT_RECOVERED; | |
12123 | } | |
12124 | ||
12125 | /** | |
12126 | * bnx2x_io_resume - called when traffic can start flowing again | |
12127 | * @pdev: Pointer to PCI device | |
12128 | * | |
12129 | * This callback is called when the error recovery driver tells us that | |
12130 | * its OK to resume normal operation. | |
12131 | */ | |
12132 | static void bnx2x_io_resume(struct pci_dev *pdev) | |
12133 | { | |
12134 | struct net_device *dev = pci_get_drvdata(pdev); | |
12135 | struct bnx2x *bp = netdev_priv(dev); | |
12136 | ||
72fd0718 | 12137 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
51c1a580 | 12138 | netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); |
72fd0718 VZ |
12139 | return; |
12140 | } | |
12141 | ||
493adb1f WX |
12142 | rtnl_lock(); |
12143 | ||
f8ef6e44 YG |
12144 | bnx2x_eeh_recover(bp); |
12145 | ||
493adb1f | 12146 | if (netif_running(dev)) |
f8ef6e44 | 12147 | bnx2x_nic_load(bp, LOAD_NORMAL); |
493adb1f WX |
12148 | |
12149 | netif_device_attach(dev); | |
12150 | ||
12151 | rtnl_unlock(); | |
12152 | } | |
12153 | ||
12154 | static struct pci_error_handlers bnx2x_err_handler = { | |
12155 | .error_detected = bnx2x_io_error_detected, | |
356e2385 EG |
12156 | .slot_reset = bnx2x_io_slot_reset, |
12157 | .resume = bnx2x_io_resume, | |
493adb1f WX |
12158 | }; |
12159 | ||
a2fbb9ea | 12160 | static struct pci_driver bnx2x_pci_driver = { |
493adb1f WX |
12161 | .name = DRV_MODULE_NAME, |
12162 | .id_table = bnx2x_pci_tbl, | |
12163 | .probe = bnx2x_init_one, | |
12164 | .remove = __devexit_p(bnx2x_remove_one), | |
12165 | .suspend = bnx2x_suspend, | |
12166 | .resume = bnx2x_resume, | |
12167 | .err_handler = &bnx2x_err_handler, | |
a2fbb9ea ET |
12168 | }; |
12169 | ||
12170 | static int __init bnx2x_init(void) | |
12171 | { | |
dd21ca6d SG |
12172 | int ret; |
12173 | ||
7995c64e | 12174 | pr_info("%s", version); |
938cf541 | 12175 | |
1cf167f2 EG |
12176 | bnx2x_wq = create_singlethread_workqueue("bnx2x"); |
12177 | if (bnx2x_wq == NULL) { | |
7995c64e | 12178 | pr_err("Cannot create workqueue\n"); |
1cf167f2 EG |
12179 | return -ENOMEM; |
12180 | } | |
12181 | ||
dd21ca6d SG |
12182 | ret = pci_register_driver(&bnx2x_pci_driver); |
12183 | if (ret) { | |
7995c64e | 12184 | pr_err("Cannot register driver\n"); |
dd21ca6d SG |
12185 | destroy_workqueue(bnx2x_wq); |
12186 | } | |
12187 | return ret; | |
a2fbb9ea ET |
12188 | } |
12189 | ||
12190 | static void __exit bnx2x_cleanup(void) | |
12191 | { | |
452427b0 | 12192 | struct list_head *pos, *q; |
a2fbb9ea | 12193 | pci_unregister_driver(&bnx2x_pci_driver); |
1cf167f2 EG |
12194 | |
12195 | destroy_workqueue(bnx2x_wq); | |
452427b0 YM |
12196 | |
12197 | /* Free globablly allocated resources */ | |
12198 | list_for_each_safe(pos, q, &bnx2x_prev_list) { | |
12199 | struct bnx2x_prev_path_list *tmp = | |
12200 | list_entry(pos, struct bnx2x_prev_path_list, list); | |
12201 | list_del(pos); | |
12202 | kfree(tmp); | |
12203 | } | |
a2fbb9ea ET |
12204 | } |
12205 | ||
3deb8167 YR |
12206 | void bnx2x_notify_link_changed(struct bnx2x *bp) |
12207 | { | |
12208 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); | |
12209 | } | |
12210 | ||
a2fbb9ea ET |
12211 | module_init(bnx2x_init); |
12212 | module_exit(bnx2x_cleanup); | |
12213 | ||
993ac7b5 | 12214 | #ifdef BCM_CNIC |
619c5cb6 VZ |
12215 | /** |
12216 | * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). | |
12217 | * | |
12218 | * @bp: driver handle | |
12219 | * @set: set or clear the CAM entry | |
12220 | * | |
12221 | * This function will wait until the ramdord completion returns. | |
12222 | * Return 0 if success, -ENODEV if ramrod doesn't return. | |
12223 | */ | |
1191cb83 | 12224 | static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) |
619c5cb6 VZ |
12225 | { |
12226 | unsigned long ramrod_flags = 0; | |
12227 | ||
12228 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
12229 | return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, | |
12230 | &bp->iscsi_l2_mac_obj, true, | |
12231 | BNX2X_ISCSI_ETH_MAC, &ramrod_flags); | |
12232 | } | |
993ac7b5 MC |
12233 | |
12234 | /* count denotes the number of new completions we have seen */ | |
12235 | static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) | |
12236 | { | |
12237 | struct eth_spe *spe; | |
a052997e | 12238 | int cxt_index, cxt_offset; |
993ac7b5 MC |
12239 | |
12240 | #ifdef BNX2X_STOP_ON_ERROR | |
12241 | if (unlikely(bp->panic)) | |
12242 | return; | |
12243 | #endif | |
12244 | ||
12245 | spin_lock_bh(&bp->spq_lock); | |
c2bff63f | 12246 | BUG_ON(bp->cnic_spq_pending < count); |
993ac7b5 MC |
12247 | bp->cnic_spq_pending -= count; |
12248 | ||
993ac7b5 | 12249 | |
c2bff63f DK |
12250 | for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { |
12251 | u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) | |
12252 | & SPE_HDR_CONN_TYPE) >> | |
12253 | SPE_HDR_CONN_TYPE_SHIFT; | |
619c5cb6 VZ |
12254 | u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) |
12255 | >> SPE_HDR_CMD_ID_SHIFT) & 0xff; | |
c2bff63f DK |
12256 | |
12257 | /* Set validation for iSCSI L2 client before sending SETUP | |
12258 | * ramrod | |
12259 | */ | |
12260 | if (type == ETH_CONNECTION_TYPE) { | |
a052997e | 12261 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) { |
37ae41a9 | 12262 | cxt_index = BNX2X_ISCSI_ETH_CID(bp) / |
a052997e | 12263 | ILT_PAGE_CIDS; |
37ae41a9 | 12264 | cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - |
a052997e MS |
12265 | (cxt_index * ILT_PAGE_CIDS); |
12266 | bnx2x_set_ctx_validation(bp, | |
12267 | &bp->context[cxt_index]. | |
12268 | vcxt[cxt_offset].eth, | |
37ae41a9 | 12269 | BNX2X_ISCSI_ETH_CID(bp)); |
a052997e | 12270 | } |
c2bff63f DK |
12271 | } |
12272 | ||
619c5cb6 VZ |
12273 | /* |
12274 | * There may be not more than 8 L2, not more than 8 L5 SPEs | |
12275 | * and in the air. We also check that number of outstanding | |
6e30dd4e VZ |
12276 | * COMMON ramrods is not more than the EQ and SPQ can |
12277 | * accommodate. | |
c2bff63f | 12278 | */ |
6e30dd4e VZ |
12279 | if (type == ETH_CONNECTION_TYPE) { |
12280 | if (!atomic_read(&bp->cq_spq_left)) | |
12281 | break; | |
12282 | else | |
12283 | atomic_dec(&bp->cq_spq_left); | |
12284 | } else if (type == NONE_CONNECTION_TYPE) { | |
12285 | if (!atomic_read(&bp->eq_spq_left)) | |
c2bff63f DK |
12286 | break; |
12287 | else | |
6e30dd4e | 12288 | atomic_dec(&bp->eq_spq_left); |
ec6ba945 VZ |
12289 | } else if ((type == ISCSI_CONNECTION_TYPE) || |
12290 | (type == FCOE_CONNECTION_TYPE)) { | |
c2bff63f DK |
12291 | if (bp->cnic_spq_pending >= |
12292 | bp->cnic_eth_dev.max_kwqe_pending) | |
12293 | break; | |
12294 | else | |
12295 | bp->cnic_spq_pending++; | |
12296 | } else { | |
12297 | BNX2X_ERR("Unknown SPE type: %d\n", type); | |
12298 | bnx2x_panic(); | |
993ac7b5 | 12299 | break; |
c2bff63f | 12300 | } |
993ac7b5 MC |
12301 | |
12302 | spe = bnx2x_sp_get_next(bp); | |
12303 | *spe = *bp->cnic_kwq_cons; | |
12304 | ||
51c1a580 | 12305 | DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", |
993ac7b5 MC |
12306 | bp->cnic_spq_pending, bp->cnic_kwq_pending, count); |
12307 | ||
12308 | if (bp->cnic_kwq_cons == bp->cnic_kwq_last) | |
12309 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
12310 | else | |
12311 | bp->cnic_kwq_cons++; | |
12312 | } | |
12313 | bnx2x_sp_prod_update(bp); | |
12314 | spin_unlock_bh(&bp->spq_lock); | |
12315 | } | |
12316 | ||
12317 | static int bnx2x_cnic_sp_queue(struct net_device *dev, | |
12318 | struct kwqe_16 *kwqes[], u32 count) | |
12319 | { | |
12320 | struct bnx2x *bp = netdev_priv(dev); | |
12321 | int i; | |
12322 | ||
12323 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 MS |
12324 | if (unlikely(bp->panic)) { |
12325 | BNX2X_ERR("Can't post to SP queue while panic\n"); | |
993ac7b5 | 12326 | return -EIO; |
51c1a580 | 12327 | } |
993ac7b5 MC |
12328 | #endif |
12329 | ||
95c6c616 AE |
12330 | if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && |
12331 | (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
51c1a580 | 12332 | BNX2X_ERR("Handling parity error recovery. Try again later\n"); |
95c6c616 AE |
12333 | return -EAGAIN; |
12334 | } | |
12335 | ||
993ac7b5 MC |
12336 | spin_lock_bh(&bp->spq_lock); |
12337 | ||
12338 | for (i = 0; i < count; i++) { | |
12339 | struct eth_spe *spe = (struct eth_spe *)kwqes[i]; | |
12340 | ||
12341 | if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) | |
12342 | break; | |
12343 | ||
12344 | *bp->cnic_kwq_prod = *spe; | |
12345 | ||
12346 | bp->cnic_kwq_pending++; | |
12347 | ||
51c1a580 | 12348 | DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", |
993ac7b5 | 12349 | spe->hdr.conn_and_cmd_data, spe->hdr.type, |
523224a3 DK |
12350 | spe->data.update_data_addr.hi, |
12351 | spe->data.update_data_addr.lo, | |
993ac7b5 MC |
12352 | bp->cnic_kwq_pending); |
12353 | ||
12354 | if (bp->cnic_kwq_prod == bp->cnic_kwq_last) | |
12355 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
12356 | else | |
12357 | bp->cnic_kwq_prod++; | |
12358 | } | |
12359 | ||
12360 | spin_unlock_bh(&bp->spq_lock); | |
12361 | ||
12362 | if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) | |
12363 | bnx2x_cnic_sp_post(bp, 0); | |
12364 | ||
12365 | return i; | |
12366 | } | |
12367 | ||
12368 | static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
12369 | { | |
12370 | struct cnic_ops *c_ops; | |
12371 | int rc = 0; | |
12372 | ||
12373 | mutex_lock(&bp->cnic_mutex); | |
13707f9e ED |
12374 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
12375 | lockdep_is_held(&bp->cnic_mutex)); | |
993ac7b5 MC |
12376 | if (c_ops) |
12377 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
12378 | mutex_unlock(&bp->cnic_mutex); | |
12379 | ||
12380 | return rc; | |
12381 | } | |
12382 | ||
12383 | static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
12384 | { | |
12385 | struct cnic_ops *c_ops; | |
12386 | int rc = 0; | |
12387 | ||
12388 | rcu_read_lock(); | |
12389 | c_ops = rcu_dereference(bp->cnic_ops); | |
12390 | if (c_ops) | |
12391 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
12392 | rcu_read_unlock(); | |
12393 | ||
12394 | return rc; | |
12395 | } | |
12396 | ||
12397 | /* | |
12398 | * for commands that have no data | |
12399 | */ | |
9f6c9258 | 12400 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) |
993ac7b5 MC |
12401 | { |
12402 | struct cnic_ctl_info ctl = {0}; | |
12403 | ||
12404 | ctl.cmd = cmd; | |
12405 | ||
12406 | return bnx2x_cnic_ctl_send(bp, &ctl); | |
12407 | } | |
12408 | ||
619c5cb6 | 12409 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) |
993ac7b5 | 12410 | { |
619c5cb6 | 12411 | struct cnic_ctl_info ctl = {0}; |
993ac7b5 MC |
12412 | |
12413 | /* first we tell CNIC and only then we count this as a completion */ | |
12414 | ctl.cmd = CNIC_CTL_COMPLETION_CMD; | |
12415 | ctl.data.comp.cid = cid; | |
619c5cb6 | 12416 | ctl.data.comp.error = err; |
993ac7b5 MC |
12417 | |
12418 | bnx2x_cnic_ctl_send_bh(bp, &ctl); | |
c2bff63f | 12419 | bnx2x_cnic_sp_post(bp, 0); |
993ac7b5 MC |
12420 | } |
12421 | ||
619c5cb6 VZ |
12422 | |
12423 | /* Called with netif_addr_lock_bh() taken. | |
12424 | * Sets an rx_mode config for an iSCSI ETH client. | |
12425 | * Doesn't block. | |
12426 | * Completion should be checked outside. | |
12427 | */ | |
12428 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) | |
12429 | { | |
12430 | unsigned long accept_flags = 0, ramrod_flags = 0; | |
12431 | u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
12432 | int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; | |
12433 | ||
12434 | if (start) { | |
12435 | /* Start accepting on iSCSI L2 ring. Accept all multicasts | |
12436 | * because it's the only way for UIO Queue to accept | |
12437 | * multicasts (in non-promiscuous mode only one Queue per | |
12438 | * function will receive multicast packets (leading in our | |
12439 | * case). | |
12440 | */ | |
12441 | __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); | |
12442 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); | |
12443 | __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); | |
12444 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
12445 | ||
12446 | /* Clear STOP_PENDING bit if START is requested */ | |
12447 | clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); | |
12448 | ||
12449 | sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; | |
12450 | } else | |
12451 | /* Clear START_PENDING bit if STOP is requested */ | |
12452 | clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); | |
12453 | ||
12454 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
12455 | set_bit(sched_state, &bp->sp_state); | |
12456 | else { | |
12457 | __set_bit(RAMROD_RX, &ramrod_flags); | |
12458 | bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, | |
12459 | ramrod_flags); | |
12460 | } | |
12461 | } | |
12462 | ||
12463 | ||
993ac7b5 MC |
12464 | static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) |
12465 | { | |
12466 | struct bnx2x *bp = netdev_priv(dev); | |
12467 | int rc = 0; | |
12468 | ||
12469 | switch (ctl->cmd) { | |
12470 | case DRV_CTL_CTXTBL_WR_CMD: { | |
12471 | u32 index = ctl->data.io.offset; | |
12472 | dma_addr_t addr = ctl->data.io.dma_addr; | |
12473 | ||
12474 | bnx2x_ilt_wr(bp, index, addr); | |
12475 | break; | |
12476 | } | |
12477 | ||
c2bff63f DK |
12478 | case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { |
12479 | int count = ctl->data.credit.credit_count; | |
993ac7b5 MC |
12480 | |
12481 | bnx2x_cnic_sp_post(bp, count); | |
12482 | break; | |
12483 | } | |
12484 | ||
12485 | /* rtnl_lock is held. */ | |
12486 | case DRV_CTL_START_L2_CMD: { | |
619c5cb6 VZ |
12487 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
12488 | unsigned long sp_bits = 0; | |
12489 | ||
12490 | /* Configure the iSCSI classification object */ | |
12491 | bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, | |
12492 | cp->iscsi_l2_client_id, | |
12493 | cp->iscsi_l2_cid, BP_FUNC(bp), | |
12494 | bnx2x_sp(bp, mac_rdata), | |
12495 | bnx2x_sp_mapping(bp, mac_rdata), | |
12496 | BNX2X_FILTER_MAC_PENDING, | |
12497 | &bp->sp_state, BNX2X_OBJ_TYPE_RX, | |
12498 | &bp->macs_pool); | |
ec6ba945 | 12499 | |
523224a3 | 12500 | /* Set iSCSI MAC address */ |
619c5cb6 VZ |
12501 | rc = bnx2x_set_iscsi_eth_mac_addr(bp); |
12502 | if (rc) | |
12503 | break; | |
523224a3 DK |
12504 | |
12505 | mmiowb(); | |
12506 | barrier(); | |
12507 | ||
619c5cb6 VZ |
12508 | /* Start accepting on iSCSI L2 ring */ |
12509 | ||
12510 | netif_addr_lock_bh(dev); | |
12511 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
12512 | netif_addr_unlock_bh(dev); | |
12513 | ||
12514 | /* bits to wait on */ | |
12515 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
12516 | __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); | |
12517 | ||
12518 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
12519 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 | 12520 | |
993ac7b5 MC |
12521 | break; |
12522 | } | |
12523 | ||
12524 | /* rtnl_lock is held. */ | |
12525 | case DRV_CTL_STOP_L2_CMD: { | |
619c5cb6 | 12526 | unsigned long sp_bits = 0; |
993ac7b5 | 12527 | |
523224a3 | 12528 | /* Stop accepting on iSCSI L2 ring */ |
619c5cb6 VZ |
12529 | netif_addr_lock_bh(dev); |
12530 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
12531 | netif_addr_unlock_bh(dev); | |
12532 | ||
12533 | /* bits to wait on */ | |
12534 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
12535 | __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); | |
12536 | ||
12537 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
12538 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 DK |
12539 | |
12540 | mmiowb(); | |
12541 | barrier(); | |
12542 | ||
12543 | /* Unset iSCSI L2 MAC */ | |
619c5cb6 VZ |
12544 | rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, |
12545 | BNX2X_ISCSI_ETH_MAC, true); | |
993ac7b5 MC |
12546 | break; |
12547 | } | |
c2bff63f DK |
12548 | case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { |
12549 | int count = ctl->data.credit.credit_count; | |
12550 | ||
12551 | smp_mb__before_atomic_inc(); | |
6e30dd4e | 12552 | atomic_add(count, &bp->cq_spq_left); |
c2bff63f DK |
12553 | smp_mb__after_atomic_inc(); |
12554 | break; | |
12555 | } | |
1d187b34 | 12556 | case DRV_CTL_ULP_REGISTER_CMD: { |
2e499d3c | 12557 | int ulp_type = ctl->data.register_data.ulp_type; |
1d187b34 BW |
12558 | |
12559 | if (CHIP_IS_E3(bp)) { | |
12560 | int idx = BP_FW_MB_IDX(bp); | |
2e499d3c BW |
12561 | u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); |
12562 | int path = BP_PATH(bp); | |
12563 | int port = BP_PORT(bp); | |
12564 | int i; | |
12565 | u32 scratch_offset; | |
12566 | u32 *host_addr; | |
1d187b34 | 12567 | |
2e499d3c | 12568 | /* first write capability to shmem2 */ |
1d187b34 BW |
12569 | if (ulp_type == CNIC_ULP_ISCSI) |
12570 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
12571 | else if (ulp_type == CNIC_ULP_FCOE) | |
12572 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
12573 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
2e499d3c BW |
12574 | |
12575 | if ((ulp_type != CNIC_ULP_FCOE) || | |
12576 | (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || | |
12577 | (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) | |
12578 | break; | |
12579 | ||
12580 | /* if reached here - should write fcoe capabilities */ | |
12581 | scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); | |
12582 | if (!scratch_offset) | |
12583 | break; | |
12584 | scratch_offset += offsetof(struct glob_ncsi_oem_data, | |
12585 | fcoe_features[path][port]); | |
12586 | host_addr = (u32 *) &(ctl->data.register_data. | |
12587 | fcoe_features); | |
12588 | for (i = 0; i < sizeof(struct fcoe_capabilities); | |
12589 | i += 4) | |
12590 | REG_WR(bp, scratch_offset + i, | |
12591 | *(host_addr + i/4)); | |
1d187b34 BW |
12592 | } |
12593 | break; | |
12594 | } | |
2e499d3c | 12595 | |
1d187b34 BW |
12596 | case DRV_CTL_ULP_UNREGISTER_CMD: { |
12597 | int ulp_type = ctl->data.ulp_type; | |
12598 | ||
12599 | if (CHIP_IS_E3(bp)) { | |
12600 | int idx = BP_FW_MB_IDX(bp); | |
12601 | u32 cap; | |
12602 | ||
12603 | cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); | |
12604 | if (ulp_type == CNIC_ULP_ISCSI) | |
12605 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
12606 | else if (ulp_type == CNIC_ULP_FCOE) | |
12607 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
12608 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
12609 | } | |
12610 | break; | |
12611 | } | |
993ac7b5 MC |
12612 | |
12613 | default: | |
12614 | BNX2X_ERR("unknown command %x\n", ctl->cmd); | |
12615 | rc = -EINVAL; | |
12616 | } | |
12617 | ||
12618 | return rc; | |
12619 | } | |
12620 | ||
9f6c9258 | 12621 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) |
993ac7b5 MC |
12622 | { |
12623 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12624 | ||
12625 | if (bp->flags & USING_MSIX_FLAG) { | |
12626 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
12627 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
12628 | cp->irq_arr[0].vector = bp->msix_table[1].vector; | |
12629 | } else { | |
12630 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
12631 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
12632 | } | |
619c5cb6 | 12633 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
12634 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; |
12635 | else | |
12636 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; | |
12637 | ||
619c5cb6 VZ |
12638 | cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); |
12639 | cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); | |
993ac7b5 MC |
12640 | cp->irq_arr[1].status_blk = bp->def_status_blk; |
12641 | cp->irq_arr[1].status_blk_num = DEF_SB_ID; | |
523224a3 | 12642 | cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; |
993ac7b5 MC |
12643 | |
12644 | cp->num_irq = 2; | |
12645 | } | |
12646 | ||
37ae41a9 MS |
12647 | void bnx2x_setup_cnic_info(struct bnx2x *bp) |
12648 | { | |
12649 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12650 | ||
12651 | ||
12652 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + | |
12653 | bnx2x_cid_ilt_lines(bp); | |
12654 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; | |
12655 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); | |
12656 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); | |
12657 | ||
12658 | if (NO_ISCSI_OOO(bp)) | |
12659 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
12660 | } | |
12661 | ||
993ac7b5 MC |
12662 | static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, |
12663 | void *data) | |
12664 | { | |
12665 | struct bnx2x *bp = netdev_priv(dev); | |
12666 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12667 | ||
51c1a580 MS |
12668 | if (ops == NULL) { |
12669 | BNX2X_ERR("NULL ops received\n"); | |
993ac7b5 | 12670 | return -EINVAL; |
51c1a580 | 12671 | } |
993ac7b5 | 12672 | |
993ac7b5 MC |
12673 | bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); |
12674 | if (!bp->cnic_kwq) | |
12675 | return -ENOMEM; | |
12676 | ||
12677 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
12678 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
12679 | bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; | |
12680 | ||
12681 | bp->cnic_spq_pending = 0; | |
12682 | bp->cnic_kwq_pending = 0; | |
12683 | ||
12684 | bp->cnic_data = data; | |
12685 | ||
12686 | cp->num_irq = 0; | |
619c5cb6 | 12687 | cp->drv_state |= CNIC_DRV_STATE_REGD; |
523224a3 | 12688 | cp->iro_arr = bp->iro_arr; |
993ac7b5 | 12689 | |
993ac7b5 | 12690 | bnx2x_setup_cnic_irq_info(bp); |
c2bff63f | 12691 | |
993ac7b5 MC |
12692 | rcu_assign_pointer(bp->cnic_ops, ops); |
12693 | ||
12694 | return 0; | |
12695 | } | |
12696 | ||
12697 | static int bnx2x_unregister_cnic(struct net_device *dev) | |
12698 | { | |
12699 | struct bnx2x *bp = netdev_priv(dev); | |
12700 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12701 | ||
12702 | mutex_lock(&bp->cnic_mutex); | |
993ac7b5 | 12703 | cp->drv_state = 0; |
2cfa5a04 | 12704 | RCU_INIT_POINTER(bp->cnic_ops, NULL); |
993ac7b5 MC |
12705 | mutex_unlock(&bp->cnic_mutex); |
12706 | synchronize_rcu(); | |
12707 | kfree(bp->cnic_kwq); | |
12708 | bp->cnic_kwq = NULL; | |
12709 | ||
12710 | return 0; | |
12711 | } | |
12712 | ||
12713 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) | |
12714 | { | |
12715 | struct bnx2x *bp = netdev_priv(dev); | |
12716 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12717 | ||
2ba45142 VZ |
12718 | /* If both iSCSI and FCoE are disabled - return NULL in |
12719 | * order to indicate CNIC that it should not try to work | |
12720 | * with this device. | |
12721 | */ | |
12722 | if (NO_ISCSI(bp) && NO_FCOE(bp)) | |
12723 | return NULL; | |
12724 | ||
993ac7b5 MC |
12725 | cp->drv_owner = THIS_MODULE; |
12726 | cp->chip_id = CHIP_ID(bp); | |
12727 | cp->pdev = bp->pdev; | |
12728 | cp->io_base = bp->regview; | |
12729 | cp->io_base2 = bp->doorbells; | |
12730 | cp->max_kwqe_pending = 8; | |
523224a3 | 12731 | cp->ctx_blk_size = CDU_ILT_PAGE_SZ; |
c2bff63f DK |
12732 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
12733 | bnx2x_cid_ilt_lines(bp); | |
993ac7b5 | 12734 | cp->ctx_tbl_len = CNIC_ILT_LINES; |
c2bff63f | 12735 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
993ac7b5 MC |
12736 | cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; |
12737 | cp->drv_ctl = bnx2x_drv_ctl; | |
12738 | cp->drv_register_cnic = bnx2x_register_cnic; | |
12739 | cp->drv_unregister_cnic = bnx2x_unregister_cnic; | |
37ae41a9 | 12740 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); |
619c5cb6 VZ |
12741 | cp->iscsi_l2_client_id = |
12742 | bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
37ae41a9 | 12743 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); |
c2bff63f | 12744 | |
2ba45142 VZ |
12745 | if (NO_ISCSI_OOO(bp)) |
12746 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
12747 | ||
12748 | if (NO_ISCSI(bp)) | |
12749 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; | |
12750 | ||
12751 | if (NO_FCOE(bp)) | |
12752 | cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; | |
12753 | ||
51c1a580 MS |
12754 | BNX2X_DEV_INFO( |
12755 | "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", | |
c2bff63f DK |
12756 | cp->ctx_blk_size, |
12757 | cp->ctx_tbl_offset, | |
12758 | cp->ctx_tbl_len, | |
12759 | cp->starting_cid); | |
993ac7b5 MC |
12760 | return cp; |
12761 | } | |
12762 | EXPORT_SYMBOL(bnx2x_cnic_probe); | |
12763 | ||
12764 | #endif /* BCM_CNIC */ | |
94a78b79 | 12765 |