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bnx2x: Changes with storage & MAC macros
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
08f6dd89 9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
24e3fcef 10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
f1deab50
JP		 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
a2fbb9ea
ET		 20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/device.h> /* for dev_info() */
24#include <linux/timer.h>
25#include <linux/errno.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
a2fbb9ea
ET		 28#include <linux/interrupt.h>
29#include <linux/pci.h>
33d8e6a5 30#include <linux/aer.h>
a2fbb9ea
ET		 31#include <linux/init.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/dma-mapping.h>
36#include <linux/bitops.h>
37#include <linux/irq.h>
38#include <linux/delay.h>
39#include <asm/byteorder.h>
40#include <linux/time.h>
41#include <linux/ethtool.h>
42#include <linux/mii.h>
0c6671b0 43#include <linux/if_vlan.h>
c9931896 44#include <linux/crash_dump.h>
a2fbb9ea 45#include <net/ip.h>
619c5cb6 46#include <net/ipv6.h>
a2fbb9ea
ET		 47#include <net/tcp.h>
48#include <net/checksum.h>
34f80b04 49#include <net/ip6_checksum.h>
a2fbb9ea
ET		 50#include <linux/workqueue.h>
51#include <linux/crc32.h>
34f80b04 52#include <linux/crc32c.h>
a2fbb9ea
ET		 53#include <linux/prefetch.h>
54#include <linux/zlib.h>
a2fbb9ea 55#include <linux/io.h>
452427b0 56#include <linux/semaphore.h>
45229b42 57#include <linux/stringify.h>
7ab24bfd 58#include <linux/vmalloc.h>
a2fbb9ea 59
a2fbb9ea
ET		 60#include "bnx2x.h"
61#include "bnx2x_init.h"
94a78b79 62#include "bnx2x_init_ops.h"
9f6c9258 63#include "bnx2x_cmn.h"
1ab4434c 64#include "bnx2x_vfpf.h"
e4901dde 65#include "bnx2x_dcb.h"
042181f5 66#include "bnx2x_sp.h"
94a78b79
VZ		 67#include <linux/firmware.h>
68#include "bnx2x_fw_file_hdr.h"
69/* FW files */
45229b42
BH		 70#define FW_FILE_VERSION \
71 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
72 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
73 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
74 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 75#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
76#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 77#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 78
34f80b04
EG		 79/* Time in jiffies before concluding the transmitter is hung */
80#define TX_TIMEOUT (5*HZ)
a2fbb9ea 81
0329aba1 82static char version[] =
619c5cb6 83 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 84 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
85
24e3fcef 86MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 87MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 88 "BCM57710/57711/57711E/"
89 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
90 "57840/57840_MF Driver");
a2fbb9ea
ET		 91MODULE_LICENSE("GPL");
92MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 93MODULE_FIRMWARE(FW_FILE_NAME_E1);
94MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 95MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 96
a8f47eb7 97int bnx2x_num_queues;
1c8bb760 98module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
96305234
DK		 99MODULE_PARM_DESC(num_queues,
100 " Set number of queues (default is as a number of CPUs)");
555f6c78 101
19680c48 102static int disable_tpa;
1c8bb760 103module_param(disable_tpa, int, S_IRUGO);
9898f86d 104MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 105
a8f47eb7 106static int int_mode;
1c8bb760 107module_param(int_mode, int, S_IRUGO);
619c5cb6 108MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 109 "(1 INT#x; 2 MSI)");
8badd27a 110
a18f5128 111static int dropless_fc;
1c8bb760 112module_param(dropless_fc, int, S_IRUGO);
a18f5128
EG		 113MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
114
8d5726c4 115static int mrrs = -1;
1c8bb760 116module_param(mrrs, int, S_IRUGO);
8d5726c4
EG		 117MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118
9898f86d 119static int debug;
1c8bb760 120module_param(debug, int, S_IRUGO);
9898f86d
EG		 121MODULE_PARM_DESC(debug, " Default debug msglevel");
122
370d4a26
YM		 123static struct workqueue_struct *bnx2x_wq;
124struct workqueue_struct *bnx2x_iov_wq;
ec6ba945 125
1ef1d45a
BW		 126struct bnx2x_mac_vals {
127 u32 xmac_addr;
128 u32 xmac_val;
129 u32 emac_addr;
130 u32 emac_val;
131 u32 umac_addr;
132 u32 umac_val;
133 u32 bmac_addr;
134 u32 bmac_val[2];
135};
136
a2fbb9ea
ET		 137enum bnx2x_board_type {
138 BCM57710 = 0,
619c5cb6
VZ		 139 BCM57711,
140 BCM57711E,
141 BCM57712,
142 BCM57712_MF,
1ab4434c 143 BCM57712_VF,
619c5cb6
VZ		 144 BCM57800,
145 BCM57800_MF,
1ab4434c 146 BCM57800_VF,
619c5cb6
VZ		 147 BCM57810,
148 BCM57810_MF,
1ab4434c 149 BCM57810_VF,
c3def943
YM		 150 BCM57840_4_10,
151 BCM57840_2_20,
7e8e02df 152 BCM57840_MF,
1ab4434c 153 BCM57840_VF,
7e8e02df 154 BCM57811,
1ab4434c
AE		 155 BCM57811_MF,
156 BCM57840_O,
157 BCM57840_MFO,
158 BCM57811_VF
a2fbb9ea
ET		 159};
160
34f80b04 161/* indexed by board_type, above */
53a10565 162static struct {
a2fbb9ea 163 char *name;
0329aba1 164} board_info[] = {
1ab4434c
AE		 165 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
166 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
167 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
168 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
169 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
170 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
171 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
172 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
173 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
174 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
175 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
176 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
177 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
178 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
179 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
180 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
181 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
182 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
183 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
184 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
185 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
a2fbb9ea
ET		 186};
187
619c5cb6
VZ		 188#ifndef PCI_DEVICE_ID_NX2_57710
189#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
190#endif
191#ifndef PCI_DEVICE_ID_NX2_57711
192#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
193#endif
194#ifndef PCI_DEVICE_ID_NX2_57711E
195#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
196#endif
197#ifndef PCI_DEVICE_ID_NX2_57712
198#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
199#endif
200#ifndef PCI_DEVICE_ID_NX2_57712_MF
201#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
202#endif
8395be5e
AE		 203#ifndef PCI_DEVICE_ID_NX2_57712_VF
204#define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
205#endif
619c5cb6
VZ		 206#ifndef PCI_DEVICE_ID_NX2_57800
207#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
208#endif
209#ifndef PCI_DEVICE_ID_NX2_57800_MF
210#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
211#endif
8395be5e
AE		 212#ifndef PCI_DEVICE_ID_NX2_57800_VF
213#define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
214#endif
619c5cb6
VZ		 215#ifndef PCI_DEVICE_ID_NX2_57810
216#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
217#endif
218#ifndef PCI_DEVICE_ID_NX2_57810_MF
219#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
220#endif
c3def943
YM		 221#ifndef PCI_DEVICE_ID_NX2_57840_O
222#define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
223#endif
8395be5e
AE		 224#ifndef PCI_DEVICE_ID_NX2_57810_VF
225#define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
226#endif
c3def943
YM		 227#ifndef PCI_DEVICE_ID_NX2_57840_4_10
228#define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
229#endif
230#ifndef PCI_DEVICE_ID_NX2_57840_2_20
231#define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
232#endif
233#ifndef PCI_DEVICE_ID_NX2_57840_MFO
234#define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
619c5cb6
VZ		 235#endif
236#ifndef PCI_DEVICE_ID_NX2_57840_MF
237#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
238#endif
8395be5e
AE		 239#ifndef PCI_DEVICE_ID_NX2_57840_VF
240#define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
241#endif
7e8e02df
BW		 242#ifndef PCI_DEVICE_ID_NX2_57811
243#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
244#endif
245#ifndef PCI_DEVICE_ID_NX2_57811_MF
246#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
247#endif
8395be5e
AE		 248#ifndef PCI_DEVICE_ID_NX2_57811_VF
249#define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
250#endif
251
9baa3c34 252static const struct pci_device_id bnx2x_pci_tbl[] = {
e4ed7113
EG		 253 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
254 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6 257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
8395be5e 258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
619c5cb6
VZ		 259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
8395be5e 261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
619c5cb6
VZ		 262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
c3def943
YM		 264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
8395be5e 267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
c3def943 268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
619c5cb6 269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
8395be5e 270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
7e8e02df
BW		 271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
8395be5e 273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
a2fbb9ea
ET		 274 { 0 }
275};
276
277MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
278
452427b0
YM		 279/* Global resources for unloading a previously loaded device */
280#define BNX2X_PREV_WAIT_NEEDED 1
281static DEFINE_SEMAPHORE(bnx2x_prev_sem);
282static LIST_HEAD(bnx2x_prev_list);
a8f47eb7 283
284/* Forward declaration */
285static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
286static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
287static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
288
a2fbb9ea
ET		 289/****************************************************************************
290* General service functions
291****************************************************************************/
292
eeed018c
MK		 293static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
294
1191cb83 295static void __storm_memset_dma_mapping(struct bnx2x *bp,
619c5cb6
VZ		 296 u32 addr, dma_addr_t mapping)
297{
298 REG_WR(bp, addr, U64_LO(mapping));
299 REG_WR(bp, addr + 4, U64_HI(mapping));
300}
301
1191cb83
ED		 302static void storm_memset_spq_addr(struct bnx2x *bp,
303 dma_addr_t mapping, u16 abs_fid)
619c5cb6
VZ		 304{
305 u32 addr = XSEM_REG_FAST_MEMORY +
306 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
307
308 __storm_memset_dma_mapping(bp, addr, mapping);
309}
310
1191cb83
ED		 311static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
312 u16 pf_id)
523224a3 313{
619c5cb6
VZ		 314 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
315 pf_id);
316 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
317 pf_id);
318 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
319 pf_id);
320 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
321 pf_id);
523224a3
DK		 322}
323
1191cb83
ED		 324static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
325 u8 enable)
619c5cb6
VZ		 326{
327 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
328 enable);
329 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
330 enable);
331 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
332 enable);
333 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
334 enable);
335}
523224a3 336
1191cb83
ED		 337static void storm_memset_eq_data(struct bnx2x *bp,
338 struct event_ring_data *eq_data,
523224a3
DK		 339 u16 pfid)
340{
341 size_t size = sizeof(struct event_ring_data);
342
343 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
344
345 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
346}
347
1191cb83
ED		 348static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
349 u16 pfid)
523224a3
DK		 350{
351 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
352 REG_WR16(bp, addr, eq_prod);
353}
354
a2fbb9ea
ET		 355/* used only at init
356 * locking is done by mcp
357 */
8d96286a 358static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 359{
360 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
361 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
362 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
363 PCICFG_VENDOR_ID_OFFSET);
364}
365
a2fbb9ea
ET		 366static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
367{
368 u32 val;
369
370 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
371 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
372 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
373 PCICFG_VENDOR_ID_OFFSET);
374
375 return val;
376}
a2fbb9ea 377
f2e0899f
DK		 378#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
379#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
380#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
381#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
382#define DMAE_DP_DST_NONE "dst_addr [none]"
383
6bf07b8e
YM		 384static void bnx2x_dp_dmae(struct bnx2x *bp,
385 struct dmae_command *dmae, int msglvl)
fd1fc79d
AE		 386{
387 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
6bf07b8e 388 int i;
fd1fc79d
AE		 389
390 switch (dmae->opcode & DMAE_COMMAND_DST) {
391 case DMAE_CMD_DST_PCI:
392 if (src_type == DMAE_CMD_SRC_PCI)
393 DP(msglvl, "DMAE: opcode 0x%08x\n"
394 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
395 "comp_addr [%x:%08x], comp_val 0x%08x\n",
396 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
397 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
398 dmae->comp_addr_hi, dmae->comp_addr_lo,
399 dmae->comp_val);
400 else
401 DP(msglvl, "DMAE: opcode 0x%08x\n"
402 "src [%08x], len [%d*4], dst [%x:%08x]\n"
403 "comp_addr [%x:%08x], comp_val 0x%08x\n",
404 dmae->opcode, dmae->src_addr_lo >> 2,
405 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
406 dmae->comp_addr_hi, dmae->comp_addr_lo,
407 dmae->comp_val);
408 break;
409 case DMAE_CMD_DST_GRC:
410 if (src_type == DMAE_CMD_SRC_PCI)
411 DP(msglvl, "DMAE: opcode 0x%08x\n"
412 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
413 "comp_addr [%x:%08x], comp_val 0x%08x\n",
414 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
415 dmae->len, dmae->dst_addr_lo >> 2,
416 dmae->comp_addr_hi, dmae->comp_addr_lo,
417 dmae->comp_val);
418 else
419 DP(msglvl, "DMAE: opcode 0x%08x\n"
420 "src [%08x], len [%d*4], dst [%08x]\n"
421 "comp_addr [%x:%08x], comp_val 0x%08x\n",
422 dmae->opcode, dmae->src_addr_lo >> 2,
423 dmae->len, dmae->dst_addr_lo >> 2,
424 dmae->comp_addr_hi, dmae->comp_addr_lo,
425 dmae->comp_val);
426 break;
427 default:
428 if (src_type == DMAE_CMD_SRC_PCI)
429 DP(msglvl, "DMAE: opcode 0x%08x\n"
430 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
431 "comp_addr [%x:%08x] comp_val 0x%08x\n",
432 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
433 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
434 dmae->comp_val);
435 else
436 DP(msglvl, "DMAE: opcode 0x%08x\n"
437 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
438 "comp_addr [%x:%08x] comp_val 0x%08x\n",
439 dmae->opcode, dmae->src_addr_lo >> 2,
440 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
441 dmae->comp_val);
442 break;
443 }
6bf07b8e
YM		 444
445 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
446 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
447 i, *(((u32 *)dmae) + i));
fd1fc79d 448}
f2e0899f 449
a2fbb9ea 450/* copy command into DMAE command memory and set DMAE command go */
6c719d00 451void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 452{
453 u32 cmd_offset;
454 int i;
455
456 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
457 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
458 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 459 }
460 REG_WR(bp, dmae_reg_go_c[idx], 1);
461}
462
f2e0899f 463u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 464{
f2e0899f
DK		 465 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
466 DMAE_CMD_C_ENABLE);
467}
ad8d3948 468
f2e0899f
DK		 469u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
470{
471 return opcode & ~DMAE_CMD_SRC_RESET;
472}
ad8d3948 473
f2e0899f
DK		 474u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
475 bool with_comp, u8 comp_type)
476{
477 u32 opcode = 0;
478
479 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
480 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 481
f2e0899f
DK		 482 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
483
484 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 485 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
486 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 487 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 488
a2fbb9ea 489#ifdef __BIG_ENDIAN
f2e0899f 490 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 491#else
f2e0899f 492 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 493#endif
f2e0899f
DK		 494 if (with_comp)
495 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
496 return opcode;
497}
498
fd1fc79d 499void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
8d96286a 500 struct dmae_command *dmae,
501 u8 src_type, u8 dst_type)
f2e0899f
DK		 502{
503 memset(dmae, 0, sizeof(struct dmae_command));
504
505 /* set the opcode */
506 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
507 true, DMAE_COMP_PCI);
508
509 /* fill in the completion parameters */
510 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
511 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
512 dmae->comp_val = DMAE_COMP_VAL;
513}
514
fd1fc79d 515/* issue a dmae command over the init-channel and wait for completion */
32316a46
AE		 516int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
517 u32 *comp)
f2e0899f 518{
5e374b5a 519 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 520 int rc = 0;
521
6bf07b8e
YM		 522 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
523
524 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
619c5cb6
VZ		 525 * as long as this code is called both from syscall context and
526 * from ndo_set_rx_mode() flow that may be called from BH.
527 */
eeed018c 528
6e30dd4e 529 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 530
f2e0899f 531 /* reset completion */
32316a46 532 *comp = 0;
a2fbb9ea 533
f2e0899f
DK		 534 /* post the command on the channel used for initializations */
535 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 536
f2e0899f 537 /* wait for completion */
a2fbb9ea 538 udelay(5);
32316a46 539 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948 540
95c6c616
AE		 541 if (!cnt ||
542 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
543 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
c3eefaf6 544 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 545 rc = DMAE_TIMEOUT;
546 goto unlock;
a2fbb9ea 547 }
ad8d3948 548 cnt--;
f2e0899f 549 udelay(50);
a2fbb9ea 550 }
32316a46 551 if (*comp & DMAE_PCI_ERR_FLAG) {
f2e0899f
DK		 552 BNX2X_ERR("DMAE PCI error!\n");
553 rc = DMAE_PCI_ERROR;
554 }
555
f2e0899f 556unlock:
eeed018c 557
6e30dd4e 558 spin_unlock_bh(&bp->dmae_lock);
eeed018c 559
f2e0899f
DK		 560 return rc;
561}
562
563void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
564 u32 len32)
565{
6bf07b8e 566 int rc;
f2e0899f
DK		 567 struct dmae_command dmae;
568
569 if (!bp->dmae_ready) {
570 u32 *data = bnx2x_sp(bp, wb_data[0]);
571
127a425e
AE		 572 if (CHIP_IS_E1(bp))
573 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
574 else
575 bnx2x_init_str_wr(bp, dst_addr, data, len32);
f2e0899f
DK		 576 return;
577 }
578
579 /* set opcode and fixed command fields */
580 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
581
582 /* fill in addresses and len */
583 dmae.src_addr_lo = U64_LO(dma_addr);
584 dmae.src_addr_hi = U64_HI(dma_addr);
585 dmae.dst_addr_lo = dst_addr >> 2;
586 dmae.dst_addr_hi = 0;
587 dmae.len = len32;
588
f2e0899f 589 /* issue the command and wait for completion */
32316a46 590 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 591 if (rc) {
592 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 593#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 594 bnx2x_panic();
9dcd9acd 595#endif
6bf07b8e 596 }
a2fbb9ea
ET		 597}
598
c18487ee 599void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 600{
6bf07b8e 601 int rc;
5ff7b6d4 602 struct dmae_command dmae;
ad8d3948
EG		 603
604 if (!bp->dmae_ready) {
605 u32 *data = bnx2x_sp(bp, wb_data[0]);
606 int i;
607
51c1a580 608 if (CHIP_IS_E1(bp))
127a425e
AE		 609 for (i = 0; i < len32; i++)
610 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
51c1a580 611 else
127a425e
AE		 612 for (i = 0; i < len32; i++)
613 data[i] = REG_RD(bp, src_addr + i*4);
614
ad8d3948
EG		 615 return;
616 }
617
f2e0899f
DK		 618 /* set opcode and fixed command fields */
619 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 620
f2e0899f 621 /* fill in addresses and len */
5ff7b6d4
EG		 622 dmae.src_addr_lo = src_addr >> 2;
623 dmae.src_addr_hi = 0;
624 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
625 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
626 dmae.len = len32;
ad8d3948 627
f2e0899f 628 /* issue the command and wait for completion */
32316a46 629 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 630 if (rc) {
631 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 632#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 633 bnx2x_panic();
9dcd9acd 634#endif
c957d09f 635 }
ad8d3948
EG		 636}
637
8d96286a 638static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
639 u32 addr, u32 len)
573f2035 640{
02e3c6cb 641 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 642 int offset = 0;
643
02e3c6cb 644 while (len > dmae_wr_max) {
573f2035 645 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 646 addr + offset, dmae_wr_max);
647 offset += dmae_wr_max * 4;
648 len -= dmae_wr_max;
573f2035
EG		 649 }
650
651 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
652}
653
97539f1e
AE		 654enum storms {
655 XSTORM,
656 TSTORM,
657 CSTORM,
658 USTORM,
659 MAX_STORMS
660};
34f80b04 661
97539f1e
AE		 662#define STORMS_NUM 4
663#define REGS_IN_ENTRY 4
34f80b04 664
97539f1e
AE		 665static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
666 enum storms storm,
667 int entry)
668{
669 switch (storm) {
670 case XSTORM:
671 return XSTORM_ASSERT_LIST_OFFSET(entry);
672 case TSTORM:
673 return TSTORM_ASSERT_LIST_OFFSET(entry);
674 case CSTORM:
675 return CSTORM_ASSERT_LIST_OFFSET(entry);
676 case USTORM:
677 return USTORM_ASSERT_LIST_OFFSET(entry);
678 case MAX_STORMS:
679 default:
680 BNX2X_ERR("unknown storm\n");
34f80b04 681 }
97539f1e
AE		 682 return -EINVAL;
683}
34f80b04 684
97539f1e
AE		 685static int bnx2x_mc_assert(struct bnx2x *bp)
686{
687 char last_idx;
688 int i, j, rc = 0;
689 enum storms storm;
690 u32 regs[REGS_IN_ENTRY];
691 u32 bar_storm_intmem[STORMS_NUM] = {
692 BAR_XSTRORM_INTMEM,
693 BAR_TSTRORM_INTMEM,
694 BAR_CSTRORM_INTMEM,
695 BAR_USTRORM_INTMEM
696 };
697 u32 storm_assert_list_index[STORMS_NUM] = {
698 XSTORM_ASSERT_LIST_INDEX_OFFSET,
699 TSTORM_ASSERT_LIST_INDEX_OFFSET,
700 CSTORM_ASSERT_LIST_INDEX_OFFSET,
701 USTORM_ASSERT_LIST_INDEX_OFFSET
702 };
703 char *storms_string[STORMS_NUM] = {
704 "XSTORM",
705 "TSTORM",
706 "CSTORM",
707 "USTORM"
708 };
709
710 for (storm = XSTORM; storm < MAX_STORMS; storm++) {
711 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
712 storm_assert_list_index[storm]);
713 if (last_idx)
714 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
715 storms_string[storm], last_idx);
716
717 /* print the asserts */
718 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
719 /* read a single assert entry */
720 for (j = 0; j < REGS_IN_ENTRY; j++)
721 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
722 bnx2x_get_assert_list_entry(bp,
723 storm,
724 i) +
725 sizeof(u32) * j);
726
727 /* log entry if it contains a valid assert */
728 if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
729 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
730 storms_string[storm], i, regs[3],
731 regs[2], regs[1], regs[0]);
732 rc++;
733 } else {
734 break;
735 }
a2fbb9ea
ET		 736 }
737 }
34f80b04 738
97539f1e
AE		 739 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
740 CHIP_IS_E1(bp) ? "everest1" :
741 CHIP_IS_E1H(bp) ? "everest1h" :
742 CHIP_IS_E2(bp) ? "everest2" : "everest3",
743 BCM_5710_FW_MAJOR_VERSION,
744 BCM_5710_FW_MINOR_VERSION,
745 BCM_5710_FW_REVISION_VERSION);
746
a2fbb9ea
ET		 747 return rc;
748}
c14423fe 749
1a6974b2
YM		 750#define MCPR_TRACE_BUFFER_SIZE (0x800)
751#define SCRATCH_BUFFER_SIZE(bp) \
752 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
753
7a25cc73 754void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 755{
7a25cc73 756 u32 addr, val;
a2fbb9ea 757 u32 mark, offset;
4781bfad 758 __be32 data[9];
a2fbb9ea 759 int word;
f2e0899f 760 u32 trace_shmem_base;
2145a920
VZ		 761 if (BP_NOMCP(bp)) {
762 BNX2X_ERR("NO MCP - can not dump\n");
763 return;
764 }
7a25cc73
DK		 765 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
766 (bp->common.bc_ver & 0xff0000) >> 16,
767 (bp->common.bc_ver & 0xff00) >> 8,
768 (bp->common.bc_ver & 0xff));
769
770 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
771 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
51c1a580 772 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 773
f2e0899f
DK		 774 if (BP_PATH(bp) == 0)
775 trace_shmem_base = bp->common.shmem_base;
776 else
777 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
1a6974b2
YM		 778
779 /* sanity */
780 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
781 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
782 SCRATCH_BUFFER_SIZE(bp)) {
783 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
784 trace_shmem_base);
785 return;
786 }
787
788 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
de128804
DK		 789
790 /* validate TRCB signature */
791 mark = REG_RD(bp, addr);
792 if (mark != MFW_TRACE_SIGNATURE) {
793 BNX2X_ERR("Trace buffer signature is missing.");
794 return ;
795 }
796
797 /* read cyclic buffer pointer */
798 addr += 4;
cdaa7cb8 799 mark = REG_RD(bp, addr);
1a6974b2
YM		 800 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
801 if (mark >= trace_shmem_base || mark < addr + 4) {
802 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
803 return;
804 }
7a25cc73 805 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 806
7a25cc73 807 printk("%s", lvl);
2de67439
YM		 808
809 /* dump buffer after the mark */
1a6974b2 810 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 811 for (word = 0; word < 8; word++)
cdaa7cb8 812 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 813 data[8] = 0x0;
7995c64e 814 pr_cont("%s", (char *)data);
a2fbb9ea 815 }
2de67439
YM		 816
817 /* dump buffer before the mark */
cdaa7cb8 818 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 819 for (word = 0; word < 8; word++)
cdaa7cb8 820 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 821 data[8] = 0x0;
7995c64e 822 pr_cont("%s", (char *)data);
a2fbb9ea 823 }
7a25cc73
DK		 824 printk("%s" "end of fw dump\n", lvl);
825}
826
1191cb83 827static void bnx2x_fw_dump(struct bnx2x *bp)
7a25cc73
DK		 828{
829 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 830}
831
823e1d90
YM		 832static void bnx2x_hc_int_disable(struct bnx2x *bp)
833{
834 int port = BP_PORT(bp);
835 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
836 u32 val = REG_RD(bp, addr);
837
838 /* in E1 we must use only PCI configuration space to disable
16a5fd92
YM		 839 * MSI/MSIX capability
840 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
823e1d90
YM		 841 */
842 if (CHIP_IS_E1(bp)) {
843 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
844 * Use mask register to prevent from HC sending interrupts
845 * after we exit the function
846 */
847 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
848
849 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
850 HC_CONFIG_0_REG_INT_LINE_EN_0 |
851 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
852 } else
853 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
854 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
855 HC_CONFIG_0_REG_INT_LINE_EN_0 |
856 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
857
858 DP(NETIF_MSG_IFDOWN,
859 "write %x to HC %d (addr 0x%x)\n",
860 val, port, addr);
861
862 /* flush all outstanding writes */
863 mmiowb();
864
865 REG_WR(bp, addr, val);
866 if (REG_RD(bp, addr) != val)
6bf07b8e 867 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 868}
869
870static void bnx2x_igu_int_disable(struct bnx2x *bp)
871{
872 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
873
874 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
875 IGU_PF_CONF_INT_LINE_EN |
876 IGU_PF_CONF_ATTN_BIT_EN);
877
878 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
879
880 /* flush all outstanding writes */
881 mmiowb();
882
883 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
884 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
6bf07b8e 885 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 886}
887
888static void bnx2x_int_disable(struct bnx2x *bp)
889{
890 if (bp->common.int_block == INT_BLOCK_HC)
891 bnx2x_hc_int_disable(bp);
892 else
893 bnx2x_igu_int_disable(bp);
894}
895
896void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
a2fbb9ea
ET		 897{
898 int i;
523224a3
DK		 899 u16 j;
900 struct hc_sp_status_block_data sp_sb_data;
901 int func = BP_FUNC(bp);
902#ifdef BNX2X_STOP_ON_ERROR
903 u16 start = 0, end = 0;
6383c0b3 904 u8 cos;
523224a3 905#endif
0155a27c 906 if (IS_PF(bp) && disable_int)
823e1d90 907 bnx2x_int_disable(bp);
a2fbb9ea 908
66e855f3 909 bp->stats_state = STATS_STATE_DISABLED;
7a752993 910 bp->eth_stats.unrecoverable_error++;
66e855f3
YG		 911 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
912
a2fbb9ea
ET		 913 BNX2X_ERR("begin crash dump -----------------\n");
914
8440d2b6
EG		 915 /* Indices */
916 /* Common */
0155a27c
YM		 917 if (IS_PF(bp)) {
918 struct host_sp_status_block *def_sb = bp->def_status_blk;
919 int data_size, cstorm_offset;
920
921 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
922 bp->def_idx, bp->def_att_idx, bp->attn_state,
923 bp->spq_prod_idx, bp->stats_counter);
924 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
925 def_sb->atten_status_block.attn_bits,
926 def_sb->atten_status_block.attn_bits_ack,
927 def_sb->atten_status_block.status_block_id,
928 def_sb->atten_status_block.attn_bits_index);
929 BNX2X_ERR(" def (");
930 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
931 pr_cont("0x%x%s",
932 def_sb->sp_sb.index_values[i],
933 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
934
935 data_size = sizeof(struct hc_sp_status_block_data) /
936 sizeof(u32);
937 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
938 for (i = 0; i < data_size; i++)
939 *((u32 *)&sp_sb_data + i) =
940 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
941 i * sizeof(u32));
942
943 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
944 sp_sb_data.igu_sb_id,
945 sp_sb_data.igu_seg_id,
946 sp_sb_data.p_func.pf_id,
947 sp_sb_data.p_func.vnic_id,
948 sp_sb_data.p_func.vf_id,
949 sp_sb_data.p_func.vf_valid,
950 sp_sb_data.state);
951 }
523224a3 952
ec6ba945 953 for_each_eth_queue(bp, i) {
a2fbb9ea 954 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 955 int loop;
f2e0899f 956 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 957 struct hc_status_block_data_e1x sb_data_e1x;
958 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 959 CHIP_IS_E1x(bp) ?
960 sb_data_e1x.common.state_machine :
961 sb_data_e2.common.state_machine;
523224a3 962 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 963 CHIP_IS_E1x(bp) ?
964 sb_data_e1x.index_data :
965 sb_data_e2.index_data;
6383c0b3 966 u8 data_size, cos;
523224a3 967 u32 *sb_data_p;
6383c0b3 968 struct bnx2x_fp_txdata txdata;
523224a3 969
e2611998
YM		 970 if (!bp->fp)
971 break;
972
973 if (!fp->rx_cons_sb)
974 continue;
975
523224a3 976 /* Rx */
51c1a580 977 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 978 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 979 fp->rx_comp_prod,
66e855f3 980 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
51c1a580 981 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
8440d2b6 982 fp->rx_sge_prod, fp->last_max_sge,
523224a3 983 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 984
523224a3 985 /* Tx */
6383c0b3
AE		 986 for_each_cos_in_tx_queue(fp, cos)
987 {
1fc3de94 988 if (!fp->txdata_ptr[cos])
e2611998
YM		 989 break;
990
65565884 991 txdata = *fp->txdata_ptr[cos];
e2611998
YM		 992
993 if (!txdata.tx_cons_sb)
994 continue;
995
51c1a580 996 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
6383c0b3
AE		 997 i, txdata.tx_pkt_prod,
998 txdata.tx_pkt_cons, txdata.tx_bd_prod,
999 txdata.tx_bd_cons,
1000 le16_to_cpu(*txdata.tx_cons_sb));
1001 }
523224a3 1002
619c5cb6
VZ		 1003 loop = CHIP_IS_E1x(bp) ?
1004 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 1005
1006 /* host sb data */
1007
ec6ba945
VZ		 1008 if (IS_FCOE_FP(fp))
1009 continue;
55c11941 1010
523224a3
DK		 1011 BNX2X_ERR(" run indexes (");
1012 for (j = 0; j < HC_SB_MAX_SM; j++)
1013 pr_cont("0x%x%s",
1014 fp->sb_running_index[j],
1015 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1016
1017 BNX2X_ERR(" indexes (");
1018 for (j = 0; j < loop; j++)
1019 pr_cont("0x%x%s",
1020 fp->sb_index_values[j],
1021 (j == loop - 1) ? ")" : " ");
0155a27c
YM		 1022
1023 /* VF cannot access FW refelection for status block */
1024 if (IS_VF(bp))
1025 continue;
1026
523224a3 1027 /* fw sb data */
619c5cb6
VZ		 1028 data_size = CHIP_IS_E1x(bp) ?
1029 sizeof(struct hc_status_block_data_e1x) :
1030 sizeof(struct hc_status_block_data_e2);
523224a3 1031 data_size /= sizeof(u32);
619c5cb6
VZ		 1032 sb_data_p = CHIP_IS_E1x(bp) ?
1033 (u32 *)&sb_data_e1x :
1034 (u32 *)&sb_data_e2;
523224a3
DK		 1035 /* copy sb data in here */
1036 for (j = 0; j < data_size; j++)
1037 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1038 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1039 j * sizeof(u32));
1040
619c5cb6 1041 if (!CHIP_IS_E1x(bp)) {
51c1a580 1042 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1043 sb_data_e2.common.p_func.pf_id,
1044 sb_data_e2.common.p_func.vf_id,
1045 sb_data_e2.common.p_func.vf_valid,
1046 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 1047 sb_data_e2.common.same_igu_sb_1b,
1048 sb_data_e2.common.state);
f2e0899f 1049 } else {
51c1a580 1050 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1051 sb_data_e1x.common.p_func.pf_id,
1052 sb_data_e1x.common.p_func.vf_id,
1053 sb_data_e1x.common.p_func.vf_valid,
1054 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 1055 sb_data_e1x.common.same_igu_sb_1b,
1056 sb_data_e1x.common.state);
f2e0899f 1057 }
523224a3
DK		 1058
1059 /* SB_SMs data */
1060 for (j = 0; j < HC_SB_MAX_SM; j++) {
51c1a580
MS		 1061 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1062 j, hc_sm_p[j].__flags,
1063 hc_sm_p[j].igu_sb_id,
1064 hc_sm_p[j].igu_seg_id,
1065 hc_sm_p[j].time_to_expire,
1066 hc_sm_p[j].timer_value);
523224a3
DK		 1067 }
1068
16a5fd92 1069 /* Indices data */
523224a3 1070 for (j = 0; j < loop; j++) {
51c1a580 1071 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
523224a3
DK		 1072 hc_index_p[j].flags,
1073 hc_index_p[j].timeout);
1074 }
8440d2b6 1075 }
a2fbb9ea 1076
523224a3 1077#ifdef BNX2X_STOP_ON_ERROR
0155a27c
YM		 1078 if (IS_PF(bp)) {
1079 /* event queue */
1080 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1081 for (i = 0; i < NUM_EQ_DESC; i++) {
1082 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1083
1084 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1085 i, bp->eq_ring[i].message.opcode,
1086 bp->eq_ring[i].message.error);
1087 BNX2X_ERR("data: %x %x %x\n",
1088 data[0], data[1], data[2]);
1089 }
04c46736
YM		 1090 }
1091
8440d2b6
EG		 1092 /* Rings */
1093 /* Rx */
55c11941 1094 for_each_valid_rx_queue(bp, i) {
8440d2b6 1095 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1096
e2611998
YM		 1097 if (!bp->fp)
1098 break;
1099
1100 if (!fp->rx_cons_sb)
1101 continue;
1102
a2fbb9ea
ET		 1103 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1104 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 1105 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 1106 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1107 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1108
c3eefaf6 1109 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
44151acb 1110 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
a2fbb9ea
ET		 1111 }
1112
3196a88a
EG		 1113 start = RX_SGE(fp->rx_sge_prod);
1114 end = RX_SGE(fp->last_max_sge);
8440d2b6 1115 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 1116 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1117 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1118
c3eefaf6
EG		 1119 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1120 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 1121 }
1122
a2fbb9ea
ET		 1123 start = RCQ_BD(fp->rx_comp_cons - 10);
1124 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 1125 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 1126 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1127
c3eefaf6
EG		 1128 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1129 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 1130 }
1131 }
1132
8440d2b6 1133 /* Tx */
55c11941 1134 for_each_valid_tx_queue(bp, i) {
8440d2b6 1135 struct bnx2x_fastpath *fp = &bp->fp[i];
e2611998
YM		 1136
1137 if (!bp->fp)
1138 break;
1139
6383c0b3 1140 for_each_cos_in_tx_queue(fp, cos) {
65565884 1141 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
6383c0b3 1142
1fc3de94 1143 if (!fp->txdata_ptr[cos])
e2611998
YM		 1144 break;
1145
ea36475a 1146 if (!txdata->tx_cons_sb)
e2611998
YM		 1147 continue;
1148
6383c0b3
AE		 1149 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1150 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1151 for (j = start; j != end; j = TX_BD(j + 1)) {
1152 struct sw_tx_bd *sw_bd =
1153 &txdata->tx_buf_ring[j];
1154
51c1a580 1155 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
6383c0b3
AE		 1156 i, cos, j, sw_bd->skb,
1157 sw_bd->first_bd);
1158 }
8440d2b6 1159
6383c0b3
AE		 1160 start = TX_BD(txdata->tx_bd_cons - 10);
1161 end = TX_BD(txdata->tx_bd_cons + 254);
1162 for (j = start; j != end; j = TX_BD(j + 1)) {
1163 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 1164
51c1a580 1165 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
6383c0b3
AE		 1166 i, cos, j, tx_bd[0], tx_bd[1],
1167 tx_bd[2], tx_bd[3]);
1168 }
8440d2b6
EG		 1169 }
1170 }
523224a3 1171#endif
0155a27c
YM		 1172 if (IS_PF(bp)) {
1173 bnx2x_fw_dump(bp);
1174 bnx2x_mc_assert(bp);
1175 }
a2fbb9ea 1176 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1177}
1178
619c5cb6
VZ		 1179/*
1180 * FLR Support for E2
1181 *
1182 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1183 * initialization.
1184 */
16a5fd92 1185#define FLR_WAIT_USEC 10000 /* 10 milliseconds */
89db4ad8
AE		 1186#define FLR_WAIT_INTERVAL 50 /* usec */
1187#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
619c5cb6
VZ		 1188
1189struct pbf_pN_buf_regs {
1190 int pN;
1191 u32 init_crd;
1192 u32 crd;
1193 u32 crd_freed;
1194};
1195
1196struct pbf_pN_cmd_regs {
1197 int pN;
1198 u32 lines_occup;
1199 u32 lines_freed;
1200};
1201
1202static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1203 struct pbf_pN_buf_regs *regs,
1204 u32 poll_count)
1205{
1206 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1207 u32 cur_cnt = poll_count;
1208
1209 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1210 crd = crd_start = REG_RD(bp, regs->crd);
1211 init_crd = REG_RD(bp, regs->init_crd);
1212
1213 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1214 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1215 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1216
1217 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1218 (init_crd - crd_start))) {
1219 if (cur_cnt--) {
89db4ad8 1220 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1221 crd = REG_RD(bp, regs->crd);
1222 crd_freed = REG_RD(bp, regs->crd_freed);
1223 } else {
1224 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1225 regs->pN);
1226 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1227 regs->pN, crd);
1228 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1229 regs->pN, crd_freed);
1230 break;
1231 }
1232 }
1233 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
89db4ad8 1234 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1235}
1236
1237static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1238 struct pbf_pN_cmd_regs *regs,
1239 u32 poll_count)
1240{
1241 u32 occup, to_free, freed, freed_start;
1242 u32 cur_cnt = poll_count;
1243
1244 occup = to_free = REG_RD(bp, regs->lines_occup);
1245 freed = freed_start = REG_RD(bp, regs->lines_freed);
1246
1247 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1248 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1249
1250 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1251 if (cur_cnt--) {
89db4ad8 1252 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1253 occup = REG_RD(bp, regs->lines_occup);
1254 freed = REG_RD(bp, regs->lines_freed);
1255 } else {
1256 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1257 regs->pN);
1258 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1259 regs->pN, occup);
1260 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1261 regs->pN, freed);
1262 break;
1263 }
1264 }
1265 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
89db4ad8 1266 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1267}
1268
1191cb83
ED		 1269static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1270 u32 expected, u32 poll_count)
619c5cb6
VZ		 1271{
1272 u32 cur_cnt = poll_count;
1273 u32 val;
1274
1275 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
89db4ad8 1276 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1277
1278 return val;
1279}
1280
d16132ce
AE		 1281int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1282 char *msg, u32 poll_cnt)
619c5cb6
VZ		 1283{
1284 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1285 if (val != 0) {
1286 BNX2X_ERR("%s usage count=%d\n", msg, val);
1287 return 1;
1288 }
1289 return 0;
1290}
1291
d16132ce
AE		 1292/* Common routines with VF FLR cleanup */
1293u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
619c5cb6
VZ		 1294{
1295 /* adjust polling timeout */
1296 if (CHIP_REV_IS_EMUL(bp))
1297 return FLR_POLL_CNT * 2000;
1298
1299 if (CHIP_REV_IS_FPGA(bp))
1300 return FLR_POLL_CNT * 120;
1301
1302 return FLR_POLL_CNT;
1303}
1304
d16132ce 1305void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
619c5cb6
VZ		 1306{
1307 struct pbf_pN_cmd_regs cmd_regs[] = {
1308 {0, (CHIP_IS_E3B0(bp)) ?
1309 PBF_REG_TQ_OCCUPANCY_Q0 :
1310 PBF_REG_P0_TQ_OCCUPANCY,
1311 (CHIP_IS_E3B0(bp)) ?
1312 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1313 PBF_REG_P0_TQ_LINES_FREED_CNT},
1314 {1, (CHIP_IS_E3B0(bp)) ?
1315 PBF_REG_TQ_OCCUPANCY_Q1 :
1316 PBF_REG_P1_TQ_OCCUPANCY,
1317 (CHIP_IS_E3B0(bp)) ?
1318 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1319 PBF_REG_P1_TQ_LINES_FREED_CNT},
1320 {4, (CHIP_IS_E3B0(bp)) ?
1321 PBF_REG_TQ_OCCUPANCY_LB_Q :
1322 PBF_REG_P4_TQ_OCCUPANCY,
1323 (CHIP_IS_E3B0(bp)) ?
1324 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1325 PBF_REG_P4_TQ_LINES_FREED_CNT}
1326 };
1327
1328 struct pbf_pN_buf_regs buf_regs[] = {
1329 {0, (CHIP_IS_E3B0(bp)) ?
1330 PBF_REG_INIT_CRD_Q0 :
1331 PBF_REG_P0_INIT_CRD ,
1332 (CHIP_IS_E3B0(bp)) ?
1333 PBF_REG_CREDIT_Q0 :
1334 PBF_REG_P0_CREDIT,
1335 (CHIP_IS_E3B0(bp)) ?
1336 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1337 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1338 {1, (CHIP_IS_E3B0(bp)) ?
1339 PBF_REG_INIT_CRD_Q1 :
1340 PBF_REG_P1_INIT_CRD,
1341 (CHIP_IS_E3B0(bp)) ?
1342 PBF_REG_CREDIT_Q1 :
1343 PBF_REG_P1_CREDIT,
1344 (CHIP_IS_E3B0(bp)) ?
1345 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1346 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1347 {4, (CHIP_IS_E3B0(bp)) ?
1348 PBF_REG_INIT_CRD_LB_Q :
1349 PBF_REG_P4_INIT_CRD,
1350 (CHIP_IS_E3B0(bp)) ?
1351 PBF_REG_CREDIT_LB_Q :
1352 PBF_REG_P4_CREDIT,
1353 (CHIP_IS_E3B0(bp)) ?
1354 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1355 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1356 };
1357
1358 int i;
1359
1360 /* Verify the command queues are flushed P0, P1, P4 */
1361 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1362 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1363
619c5cb6
VZ		 1364 /* Verify the transmission buffers are flushed P0, P1, P4 */
1365 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1366 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1367}
1368
1369#define OP_GEN_PARAM(param) \
1370 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1371
1372#define OP_GEN_TYPE(type) \
1373 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1374
1375#define OP_GEN_AGG_VECT(index) \
1376 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1377
d16132ce 1378int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
619c5cb6 1379{
86564c3f 1380 u32 op_gen_command = 0;
619c5cb6
VZ		 1381 u32 comp_addr = BAR_CSTRORM_INTMEM +
1382 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1383 int ret = 0;
1384
1385 if (REG_RD(bp, comp_addr)) {
89db4ad8 1386 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
619c5cb6
VZ		 1387 return 1;
1388 }
1389
86564c3f
YM		 1390 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1391 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1392 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1393 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
619c5cb6 1394
89db4ad8 1395 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
86564c3f 1396 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
619c5cb6
VZ		 1397
1398 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1399 BNX2X_ERR("FW final cleanup did not succeed\n");
51c1a580
MS		 1400 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1401 (REG_RD(bp, comp_addr)));
d16132ce
AE		 1402 bnx2x_panic();
1403 return 1;
619c5cb6 1404 }
16a5fd92 1405 /* Zero completion for next FLR */
619c5cb6
VZ		 1406 REG_WR(bp, comp_addr, 0);
1407
1408 return ret;
1409}
1410
b56e9670 1411u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
619c5cb6 1412{
619c5cb6
VZ		 1413 u16 status;
1414
2a80eebc 1415 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
619c5cb6
VZ		 1416 return status & PCI_EXP_DEVSTA_TRPND;
1417}
1418
1419/* PF FLR specific routines
1420*/
1421static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1422{
619c5cb6
VZ		 1423 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1424 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1425 CFC_REG_NUM_LCIDS_INSIDE_PF,
1426 "CFC PF usage counter timed out",
1427 poll_cnt))
1428 return 1;
1429
619c5cb6
VZ		 1430 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1431 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1432 DORQ_REG_PF_USAGE_CNT,
1433 "DQ PF usage counter timed out",
1434 poll_cnt))
1435 return 1;
1436
1437 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1438 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1439 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1440 "QM PF usage counter timed out",
1441 poll_cnt))
1442 return 1;
1443
1444 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1445 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1446 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1447 "Timers VNIC usage counter timed out",
1448 poll_cnt))
1449 return 1;
1450 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1451 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1452 "Timers NUM_SCANS usage counter timed out",
1453 poll_cnt))
1454 return 1;
1455
1456 /* Wait DMAE PF usage counter to zero */
1457 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1458 dmae_reg_go_c[INIT_DMAE_C(bp)],
6bf07b8e 1459 "DMAE command register timed out",
619c5cb6
VZ		 1460 poll_cnt))
1461 return 1;
1462
1463 return 0;
1464}
1465
1466static void bnx2x_hw_enable_status(struct bnx2x *bp)
1467{
1468 u32 val;
1469
1470 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1471 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1472
1473 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1474 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1475
1476 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1477 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1478
1479 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1480 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1481
1482 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1483 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1484
1485 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1486 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1487
1488 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1489 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1490
1491 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1492 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1493 val);
1494}
1495
1496static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1497{
1498 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1499
1500 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1501
1502 /* Re-enable PF target read access */
1503 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1504
1505 /* Poll HW usage counters */
89db4ad8 1506 DP(BNX2X_MSG_SP, "Polling usage counters\n");
619c5cb6
VZ		 1507 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1508 return -EBUSY;
1509
1510 /* Zero the igu 'trailing edge' and 'leading edge' */
1511
1512 /* Send the FW cleanup command */
1513 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1514 return -EBUSY;
1515
1516 /* ATC cleanup */
1517
1518 /* Verify TX hw is flushed */
1519 bnx2x_tx_hw_flushed(bp, poll_cnt);
1520
1521 /* Wait 100ms (not adjusted according to platform) */
1522 msleep(100);
1523
1524 /* Verify no pending pci transactions */
1525 if (bnx2x_is_pcie_pending(bp->pdev))
1526 BNX2X_ERR("PCIE Transactions still pending\n");
1527
1528 /* Debug */
1529 bnx2x_hw_enable_status(bp);
1530
1531 /*
1532 * Master enable - Due to WB DMAE writes performed before this
1533 * register is re-initialized as part of the regular function init
1534 */
1535 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1536
1537 return 0;
1538}
1539
f2e0899f 1540static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1541{
34f80b04 1542 int port = BP_PORT(bp);
a2fbb9ea
ET		 1543 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1544 u32 val = REG_RD(bp, addr);
69c326b3
DK		 1545 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1546 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1547 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
a2fbb9ea
ET		 1548
1549 if (msix) {
8badd27a
EG		 1550 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1551 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1552 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1553 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
69c326b3
DK		 1554 if (single_msix)
1555 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
8badd27a
EG		 1556 } else if (msi) {
1557 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1558 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1559 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1560 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1561 } else {
1562 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1563 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1564 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1565 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1566
a0fd065c 1567 if (!CHIP_IS_E1(bp)) {
51c1a580
MS		 1568 DP(NETIF_MSG_IFUP,
1569 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
615f8fd9 1570
a0fd065c 1571 REG_WR(bp, addr, val);
615f8fd9 1572
a0fd065c
DK		 1573 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1574 }
a2fbb9ea
ET		 1575 }
1576
a0fd065c
DK		 1577 if (CHIP_IS_E1(bp))
1578 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1579
51c1a580
MS		 1580 DP(NETIF_MSG_IFUP,
1581 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1582 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1583
1584 REG_WR(bp, addr, val);
37dbbf32
EG		 1585 /*
1586 * Ensure that HC_CONFIG is written before leading/trailing edge config
1587 */
1588 mmiowb();
1589 barrier();
34f80b04 1590
f2e0899f 1591 if (!CHIP_IS_E1(bp)) {
34f80b04 1592 /* init leading/trailing edge */
fb3bff17 1593 if (IS_MF(bp)) {
3395a033 1594 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1595 if (bp->port.pmf)
4acac6a5
EG		 1596 /* enable nig and gpio3 attention */
1597 val |= 0x1100;
34f80b04
EG		 1598 } else
1599 val = 0xffff;
1600
1601 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1602 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1603 }
37dbbf32
EG		 1604
1605 /* Make sure that interrupts are indeed enabled from here on */
1606 mmiowb();
a2fbb9ea
ET		 1607}
1608
f2e0899f
DK		 1609static void bnx2x_igu_int_enable(struct bnx2x *bp)
1610{
1611 u32 val;
30a5de77
DK		 1612 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1613 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1614 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
f2e0899f
DK		 1615
1616 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1617
1618 if (msix) {
1619 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1620 IGU_PF_CONF_SINGLE_ISR_EN);
ebe61d80 1621 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f 1622 IGU_PF_CONF_ATTN_BIT_EN);
30a5de77
DK		 1623
1624 if (single_msix)
1625 val |= IGU_PF_CONF_SINGLE_ISR_EN;
f2e0899f
DK		 1626 } else if (msi) {
1627 val &= ~IGU_PF_CONF_INT_LINE_EN;
ebe61d80 1628 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f
DK		 1629 IGU_PF_CONF_ATTN_BIT_EN |
1630 IGU_PF_CONF_SINGLE_ISR_EN);
1631 } else {
1632 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
ebe61d80 1633 val |= (IGU_PF_CONF_INT_LINE_EN |
f2e0899f
DK		 1634 IGU_PF_CONF_ATTN_BIT_EN |
1635 IGU_PF_CONF_SINGLE_ISR_EN);
1636 }
1637
ebe61d80
YM		 1638 /* Clean previous status - need to configure igu prior to ack*/
1639 if ((!msix) || single_msix) {
1640 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1641 bnx2x_ack_int(bp);
1642 }
1643
1644 val |= IGU_PF_CONF_FUNC_EN;
1645
51c1a580 1646 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
f2e0899f
DK		 1647 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1648
1649 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1650
79a8557a
YM		 1651 if (val & IGU_PF_CONF_INT_LINE_EN)
1652 pci_intx(bp->pdev, true);
1653
f2e0899f
DK		 1654 barrier();
1655
1656 /* init leading/trailing edge */
1657 if (IS_MF(bp)) {
3395a033 1658 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1659 if (bp->port.pmf)
1660 /* enable nig and gpio3 attention */
1661 val |= 0x1100;
1662 } else
1663 val = 0xffff;
1664
1665 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1666 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1667
1668 /* Make sure that interrupts are indeed enabled from here on */
1669 mmiowb();
1670}
1671
1672void bnx2x_int_enable(struct bnx2x *bp)
1673{
1674 if (bp->common.int_block == INT_BLOCK_HC)
1675 bnx2x_hc_int_enable(bp);
1676 else
1677 bnx2x_igu_int_enable(bp);
1678}
1679
9f6c9258 1680void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1681{
a2fbb9ea 1682 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1683 int i, offset;
a2fbb9ea 1684
f8ef6e44
YG		 1685 if (disable_hw)
1686 /* prevent the HW from sending interrupts */
1687 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1688
1689 /* make sure all ISRs are done */
1690 if (msix) {
8badd27a
EG		 1691 synchronize_irq(bp->msix_table[0].vector);
1692 offset = 1;
55c11941
MS		 1693 if (CNIC_SUPPORT(bp))
1694 offset++;
ec6ba945 1695 for_each_eth_queue(bp, i)
754a2f52 1696 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1697 } else
1698 synchronize_irq(bp->pdev->irq);
1699
1700 /* make sure sp_task is not running */
1cf167f2 1701 cancel_delayed_work(&bp->sp_task);
3deb8167 1702 cancel_delayed_work(&bp->period_task);
1cf167f2 1703 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1704}
1705
34f80b04 1706/* fast path */
a2fbb9ea
ET		 1707
1708/*
34f80b04 1709 * General service functions
a2fbb9ea
ET		 1710 */
1711
72fd0718
VZ		 1712/* Return true if succeeded to acquire the lock */
1713static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1714{
1715 u32 lock_status;
1716 u32 resource_bit = (1 << resource);
1717 int func = BP_FUNC(bp);
1718 u32 hw_lock_control_reg;
1719
51c1a580
MS		 1720 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1721 "Trying to take a lock on resource %d\n", resource);
72fd0718
VZ		 1722
1723 /* Validating that the resource is within range */
1724 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1725 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
72fd0718
VZ		 1726 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1727 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1728 return false;
72fd0718
VZ		 1729 }
1730
1731 if (func <= 5)
1732 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1733 else
1734 hw_lock_control_reg =
1735 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1736
1737 /* Try to acquire the lock */
1738 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1739 lock_status = REG_RD(bp, hw_lock_control_reg);
1740 if (lock_status & resource_bit)
1741 return true;
1742
51c1a580
MS		 1743 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1744 "Failed to get a lock on resource %d\n", resource);
72fd0718
VZ		 1745 return false;
1746}
1747
c9ee9206
VZ		 1748/**
1749 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1750 *
1751 * @bp: driver handle
1752 *
1753 * Returns the recovery leader resource id according to the engine this function
1754 * belongs to. Currently only only 2 engines is supported.
1755 */
1191cb83 1756static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
c9ee9206
VZ		 1757{
1758 if (BP_PATH(bp))
1759 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1760 else
1761 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1762}
1763
1764/**
2de67439 1765 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
c9ee9206
VZ		 1766 *
1767 * @bp: driver handle
1768 *
2de67439 1769 * Tries to acquire a leader lock for current engine.
c9ee9206 1770 */
1191cb83 1771static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
c9ee9206
VZ		 1772{
1773 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1774}
1775
619c5cb6 1776static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
55c11941 1777
fd1fc79d
AE		 1778/* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1779static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1780{
1781 /* Set the interrupt occurred bit for the sp-task to recognize it
1782 * must ack the interrupt and transition according to the IGU
1783 * state machine.
1784 */
1785 atomic_set(&bp->interrupt_occurred, 1);
1786
1787 /* The sp_task must execute only after this bit
1788 * is set, otherwise we will get out of sync and miss all
1789 * further interrupts. Hence, the barrier.
1790 */
1791 smp_wmb();
1792
1793 /* schedule sp_task to workqueue */
1794 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1795}
3196a88a 1796
619c5cb6 1797void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1798{
1799 struct bnx2x *bp = fp->bp;
1800 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1801 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6 1802 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
15192a8c 1803 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a2fbb9ea 1804
34f80b04 1805 DP(BNX2X_MSG_SP,
a2fbb9ea 1806 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1807 fp->index, cid, command, bp->state,
34f80b04 1808 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1809
fd1fc79d
AE		 1810 /* If cid is within VF range, replace the slowpath object with the
1811 * one corresponding to this VF
1812 */
1813 if (cid >= BNX2X_FIRST_VF_CID &&
1814 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1815 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1816
619c5cb6
VZ		 1817 switch (command) {
1818 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1819 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1820 drv_cmd = BNX2X_Q_CMD_UPDATE;
1821 break;
d6cae238 1822
619c5cb6 1823 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1824 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1825 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1826 break;
1827
6383c0b3 1828 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
51c1a580 1829 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
6383c0b3
AE		 1830 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1831 break;
1832
619c5cb6 1833 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1834 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1835 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1836 break;
1837
619c5cb6 1838 case (RAMROD_CMD_ID_ETH_TERMINATE):
6bf07b8e 1839 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
619c5cb6 1840 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1841 break;
1842
619c5cb6 1843 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1844 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1845 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1846 break;
619c5cb6 1847
14a94ebd
MK		 1848 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1849 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1850 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1851 break;
1852
619c5cb6
VZ		 1853 default:
1854 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1855 command, fp->index);
1856 return;
523224a3 1857 }
3196a88a 1858
619c5cb6
VZ		 1859 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1860 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1861 /* q_obj->complete_cmd() failure means that this was
1862 * an unexpected completion.
1863 *
1864 * In this case we don't want to increase the bp->spq_left
1865 * because apparently we haven't sent this command the first
1866 * place.
1867 */
1868#ifdef BNX2X_STOP_ON_ERROR
1869 bnx2x_panic();
1870#else
1871 return;
1872#endif
1873
4e857c58 1874 smp_mb__before_atomic();
6e30dd4e 1875 atomic_inc(&bp->cq_spq_left);
619c5cb6 1876 /* push the change in bp->spq_left and towards the memory */
4e857c58 1877 smp_mb__after_atomic();
49d66772 1878
d6cae238
VZ		 1879 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1880
a3348722
BW		 1881 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1882 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1883 /* if Q update ramrod is completed for last Q in AFEX vif set
1884 * flow, then ACK MCP at the end
1885 *
1886 * mark pending ACK to MCP bit.
1887 * prevent case that both bits are cleared.
1888 * At the end of load/unload driver checks that
2de67439 1889 * sp_state is cleared, and this order prevents
a3348722
BW		 1890 * races
1891 */
4e857c58 1892 smp_mb__before_atomic();
a3348722
BW		 1893 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1894 wmb();
1895 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4e857c58 1896 smp_mb__after_atomic();
a3348722 1897
fd1fc79d
AE		 1898 /* schedule the sp task as mcp ack is required */
1899 bnx2x_schedule_sp_task(bp);
a3348722
BW		 1900 }
1901
523224a3 1902 return;
a2fbb9ea
ET		 1903}
1904
9f6c9258 1905irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1906{
555f6c78 1907 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1908 u16 status = bnx2x_ack_int(bp);
34f80b04 1909 u16 mask;
ca00392c 1910 int i;
6383c0b3 1911 u8 cos;
a2fbb9ea 1912
34f80b04 1913 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1914 if (unlikely(status == 0)) {
1915 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1916 return IRQ_NONE;
1917 }
f5372251 1918 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1919
3196a88a
EG		 1920#ifdef BNX2X_STOP_ON_ERROR
1921 if (unlikely(bp->panic))
1922 return IRQ_HANDLED;
1923#endif
1924
ec6ba945 1925 for_each_eth_queue(bp, i) {
ca00392c 1926 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1927
55c11941 1928 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
ca00392c 1929 if (status & mask) {
619c5cb6 1930 /* Handle Rx or Tx according to SB id */
6383c0b3 1931 for_each_cos_in_tx_queue(fp, cos)
65565884 1932 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
523224a3 1933 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1934 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1935 status &= ~mask;
1936 }
a2fbb9ea
ET		 1937 }
1938
55c11941
MS		 1939 if (CNIC_SUPPORT(bp)) {
1940 mask = 0x2;
1941 if (status & (mask | 0x1)) {
1942 struct cnic_ops *c_ops = NULL;
993ac7b5 1943
ad9b4359
MC		 1944 rcu_read_lock();
1945 c_ops = rcu_dereference(bp->cnic_ops);
1946 if (c_ops && (bp->cnic_eth_dev.drv_state &
1947 CNIC_DRV_STATE_HANDLES_IRQ))
1948 c_ops->cnic_handler(bp->cnic_data, NULL);
1949 rcu_read_unlock();
993ac7b5 1950
55c11941
MS		 1951 status &= ~mask;
1952 }
993ac7b5 1953 }
a2fbb9ea 1954
34f80b04 1955 if (unlikely(status & 0x1)) {
fd1fc79d
AE		 1956
1957 /* schedule sp task to perform default status block work, ack
1958 * attentions and enable interrupts.
1959 */
1960 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 1961
1962 status &= ~0x1;
1963 if (!status)
1964 return IRQ_HANDLED;
1965 }
1966
cdaa7cb8
VZ		 1967 if (unlikely(status))
1968 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1969 status);
a2fbb9ea 1970
c18487ee 1971 return IRQ_HANDLED;
a2fbb9ea
ET		 1972}
1973
c18487ee
YR		 1974/* Link */
1975
1976/*
1977 * General service functions
1978 */
a2fbb9ea 1979
9f6c9258 1980int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1981{
1982 u32 lock_status;
1983 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1984 int func = BP_FUNC(bp);
1985 u32 hw_lock_control_reg;
c18487ee 1986 int cnt;
a2fbb9ea 1987
c18487ee
YR		 1988 /* Validating that the resource is within range */
1989 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1990 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 1991 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1992 return -EINVAL;
1993 }
a2fbb9ea 1994
4a37fb66
YG		 1995 if (func <= 5) {
1996 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1997 } else {
1998 hw_lock_control_reg =
1999 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2000 }
2001
c18487ee 2002 /* Validating that the resource is not already taken */
4a37fb66 2003 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2004 if (lock_status & resource_bit) {
51c1a580 2005 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
c18487ee
YR		 2006 lock_status, resource_bit);
2007 return -EEXIST;
2008 }
a2fbb9ea 2009
46230476
EG		 2010 /* Try for 5 second every 5ms */
2011 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 2012 /* Try to acquire the lock */
4a37fb66
YG		 2013 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2014 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 2015 if (lock_status & resource_bit)
2016 return 0;
a2fbb9ea 2017
639d65b8 2018 usleep_range(5000, 10000);
a2fbb9ea 2019 }
51c1a580 2020 BNX2X_ERR("Timeout\n");
c18487ee
YR		 2021 return -EAGAIN;
2022}
a2fbb9ea 2023
c9ee9206
VZ		 2024int bnx2x_release_leader_lock(struct bnx2x *bp)
2025{
2026 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2027}
2028
9f6c9258 2029int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 2030{
2031 u32 lock_status;
2032 u32 resource_bit = (1 << resource);
4a37fb66
YG		 2033 int func = BP_FUNC(bp);
2034 u32 hw_lock_control_reg;
a2fbb9ea 2035
c18487ee
YR		 2036 /* Validating that the resource is within range */
2037 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 2038 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 2039 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2040 return -EINVAL;
2041 }
2042
4a37fb66
YG		 2043 if (func <= 5) {
2044 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2045 } else {
2046 hw_lock_control_reg =
2047 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2048 }
2049
c18487ee 2050 /* Validating that the resource is currently taken */
4a37fb66 2051 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2052 if (!(lock_status & resource_bit)) {
6bf07b8e
YM		 2053 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2054 lock_status, resource_bit);
c18487ee 2055 return -EFAULT;
a2fbb9ea
ET		 2056 }
2057
9f6c9258
DK		 2058 REG_WR(bp, hw_lock_control_reg, resource_bit);
2059 return 0;
c18487ee 2060}
a2fbb9ea 2061
4acac6a5
EG		 2062int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2063{
2064 /* The GPIO should be swapped if swap register is set and active */
2065 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2066 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2067 int gpio_shift = gpio_num +
2068 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2069 u32 gpio_mask = (1 << gpio_shift);
2070 u32 gpio_reg;
2071 int value;
2072
2073 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2074 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2075 return -EINVAL;
2076 }
2077
2078 /* read GPIO value */
2079 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2080
2081 /* get the requested pin value */
2082 if ((gpio_reg & gpio_mask) == gpio_mask)
2083 value = 1;
2084 else
2085 value = 0;
2086
4acac6a5
EG		 2087 return value;
2088}
2089
17de50b7 2090int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 2091{
2092 /* The GPIO should be swapped if swap register is set and active */
2093 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 2094 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 2095 int gpio_shift = gpio_num +
2096 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2097 u32 gpio_mask = (1 << gpio_shift);
2098 u32 gpio_reg;
a2fbb9ea 2099
c18487ee
YR		 2100 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2101 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2102 return -EINVAL;
2103 }
a2fbb9ea 2104
4a37fb66 2105 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 2106 /* read GPIO and mask except the float bits */
2107 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 2108
c18487ee
YR		 2109 switch (mode) {
2110 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
51c1a580
MS		 2111 DP(NETIF_MSG_LINK,
2112 "Set GPIO %d (shift %d) -> output low\n",
c18487ee
YR		 2113 gpio_num, gpio_shift);
2114 /* clear FLOAT and set CLR */
2115 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2116 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2117 break;
a2fbb9ea 2118
c18487ee 2119 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
51c1a580
MS		 2120 DP(NETIF_MSG_LINK,
2121 "Set GPIO %d (shift %d) -> output high\n",
c18487ee
YR		 2122 gpio_num, gpio_shift);
2123 /* clear FLOAT and set SET */
2124 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2125 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2126 break;
a2fbb9ea 2127
17de50b7 2128 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
51c1a580
MS		 2129 DP(NETIF_MSG_LINK,
2130 "Set GPIO %d (shift %d) -> input\n",
c18487ee
YR		 2131 gpio_num, gpio_shift);
2132 /* set FLOAT */
2133 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2134 break;
a2fbb9ea 2135
c18487ee
YR		 2136 default:
2137 break;
a2fbb9ea
ET		 2138 }
2139
c18487ee 2140 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 2141 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 2142
c18487ee 2143 return 0;
a2fbb9ea
ET		 2144}
2145
0d40f0d4
YR		 2146int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2147{
2148 u32 gpio_reg = 0;
2149 int rc = 0;
2150
2151 /* Any port swapping should be handled by caller. */
2152
2153 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2154 /* read GPIO and mask except the float bits */
2155 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2156 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2157 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2158 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2159
2160 switch (mode) {
2161 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2162 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2163 /* set CLR */
2164 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2165 break;
2166
2167 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2168 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2169 /* set SET */
2170 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2171 break;
2172
2173 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2174 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2175 /* set FLOAT */
2176 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2177 break;
2178
2179 default:
2180 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2181 rc = -EINVAL;
2182 break;
2183 }
2184
2185 if (rc == 0)
2186 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2187
2188 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2189
2190 return rc;
2191}
2192
4acac6a5
EG		 2193int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2194{
2195 /* The GPIO should be swapped if swap register is set and active */
2196 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2197 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2198 int gpio_shift = gpio_num +
2199 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2200 u32 gpio_mask = (1 << gpio_shift);
2201 u32 gpio_reg;
2202
2203 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2204 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2205 return -EINVAL;
2206 }
2207
2208 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2209 /* read GPIO int */
2210 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2211
2212 switch (mode) {
2213 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
51c1a580
MS		 2214 DP(NETIF_MSG_LINK,
2215 "Clear GPIO INT %d (shift %d) -> output low\n",
2216 gpio_num, gpio_shift);
4acac6a5
EG		 2217 /* clear SET and set CLR */
2218 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2219 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2220 break;
2221
2222 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
51c1a580
MS		 2223 DP(NETIF_MSG_LINK,
2224 "Set GPIO INT %d (shift %d) -> output high\n",
2225 gpio_num, gpio_shift);
4acac6a5
EG		 2226 /* clear CLR and set SET */
2227 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2228 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2229 break;
2230
2231 default:
2232 break;
2233 }
2234
2235 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2236 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2237
2238 return 0;
2239}
2240
d6d99a3f 2241static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
a2fbb9ea 2242{
c18487ee 2243 u32 spio_reg;
a2fbb9ea 2244
d6d99a3f
YM		 2245 /* Only 2 SPIOs are configurable */
2246 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2247 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
c18487ee 2248 return -EINVAL;
a2fbb9ea
ET		 2249 }
2250
4a37fb66 2251 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2252 /* read SPIO and mask except the float bits */
d6d99a3f 2253 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
a2fbb9ea 2254
c18487ee 2255 switch (mode) {
d6d99a3f
YM		 2256 case MISC_SPIO_OUTPUT_LOW:
2257 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
c18487ee 2258 /* clear FLOAT and set CLR */
d6d99a3f
YM		 2259 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2260 spio_reg |= (spio << MISC_SPIO_CLR_POS);
c18487ee 2261 break;
a2fbb9ea 2262
d6d99a3f
YM		 2263 case MISC_SPIO_OUTPUT_HIGH:
2264 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
c18487ee 2265 /* clear FLOAT and set SET */
d6d99a3f
YM		 2266 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2267 spio_reg |= (spio << MISC_SPIO_SET_POS);
c18487ee 2268 break;
a2fbb9ea 2269
d6d99a3f
YM		 2270 case MISC_SPIO_INPUT_HI_Z:
2271 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
c18487ee 2272 /* set FLOAT */
d6d99a3f 2273 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
c18487ee 2274 break;
a2fbb9ea 2275
c18487ee
YR		 2276 default:
2277 break;
a2fbb9ea
ET		 2278 }
2279
c18487ee 2280 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2281 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2282
a2fbb9ea
ET		 2283 return 0;
2284}
2285
9f6c9258 2286void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2287{
a22f0788 2288 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2289 switch (bp->link_vars.ieee_fc &
2290 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2291 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2292 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2293 ADVERTISED_Pause);
c18487ee 2294 break;
356e2385 2295
c18487ee 2296 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2297 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2298 ADVERTISED_Pause);
c18487ee 2299 break;
356e2385 2300
c18487ee 2301 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2302 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2303 break;
356e2385 2304
c18487ee 2305 default:
a22f0788 2306 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2307 ADVERTISED_Pause);
c18487ee
YR		 2308 break;
2309 }
2310}
f1410647 2311
cd1dfce2 2312static void bnx2x_set_requested_fc(struct bnx2x *bp)
c18487ee 2313{
cd1dfce2
YM		 2314 /* Initialize link parameters structure variables
2315 * It is recommended to turn off RX FC for jumbo frames
2316 * for better performance
2317 */
2318 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2319 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2320 else
2321 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2322}
a2fbb9ea 2323
9156b30b
DK		 2324static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2325{
2326 u32 pause_enabled = 0;
2327
2328 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2329 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2330 pause_enabled = 1;
2331
2332 REG_WR(bp, BAR_USTRORM_INTMEM +
2333 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2334 pause_enabled);
2335 }
2336
2337 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2338 pause_enabled ? "enabled" : "disabled");
2339}
2340
cd1dfce2
YM		 2341int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2342{
2343 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2344 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2345
2346 if (!BP_NOMCP(bp)) {
2347 bnx2x_set_requested_fc(bp);
4a37fb66 2348 bnx2x_acquire_phy_lock(bp);
b5bf9068 2349
a22f0788 2350 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2351 struct link_params *lp = &bp->link_params;
2352 lp->loopback_mode = LOOPBACK_XGXS;
2353 /* do PHY loopback at 10G speed, if possible */
2354 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2355 if (lp->speed_cap_mask[cfx_idx] &
2356 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2357 lp->req_line_speed[cfx_idx] =
2358 SPEED_10000;
2359 else
2360 lp->req_line_speed[cfx_idx] =
2361 SPEED_1000;
2362 }
a22f0788 2363 }
b5bf9068 2364
8970b2e4
MS		 2365 if (load_mode == LOAD_LOOPBACK_EXT) {
2366 struct link_params *lp = &bp->link_params;
2367 lp->loopback_mode = LOOPBACK_EXT;
2368 }
2369
19680c48 2370 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2371
4a37fb66 2372 bnx2x_release_phy_lock(bp);
a2fbb9ea 2373
9156b30b
DK		 2374 bnx2x_init_dropless_fc(bp);
2375
3c96c68b
EG		 2376 bnx2x_calc_fc_adv(bp);
2377
cd1dfce2 2378 if (bp->link_vars.link_up) {
b5bf9068 2379 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2380 bnx2x_link_report(bp);
cd1dfce2
YM		 2381 }
2382 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2383 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2384 return rc;
2385 }
f5372251 2386 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2387 return -EINVAL;
a2fbb9ea
ET		 2388}
2389
9f6c9258 2390void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2391{
19680c48 2392 if (!BP_NOMCP(bp)) {
4a37fb66 2393 bnx2x_acquire_phy_lock(bp);
19680c48 2394 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2395 bnx2x_release_phy_lock(bp);
a2fbb9ea 2396
9156b30b
DK		 2397 bnx2x_init_dropless_fc(bp);
2398
19680c48
EG		 2399 bnx2x_calc_fc_adv(bp);
2400 } else
f5372251 2401 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2402}
a2fbb9ea 2403
c18487ee
YR		 2404static void bnx2x__link_reset(struct bnx2x *bp)
2405{
19680c48 2406 if (!BP_NOMCP(bp)) {
4a37fb66 2407 bnx2x_acquire_phy_lock(bp);
5d07d868 2408 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
4a37fb66 2409 bnx2x_release_phy_lock(bp);
19680c48 2410 } else
f5372251 2411 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2412}
a2fbb9ea 2413
5d07d868
YM		 2414void bnx2x_force_link_reset(struct bnx2x *bp)
2415{
2416 bnx2x_acquire_phy_lock(bp);
2417 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2418 bnx2x_release_phy_lock(bp);
2419}
2420
a22f0788 2421u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2422{
2145a920 2423 u8 rc = 0;
a2fbb9ea 2424
2145a920
VZ		 2425 if (!BP_NOMCP(bp)) {
2426 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2427 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2428 is_serdes);
2145a920
VZ		 2429 bnx2x_release_phy_lock(bp);
2430 } else
2431 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2432
c18487ee
YR		 2433 return rc;
2434}
a2fbb9ea 2435
2691d51d
EG		 2436/* Calculates the sum of vn_min_rates.
2437 It's needed for further normalizing of the min_rates.
2438 Returns:
2439 sum of vn_min_rates.
2440 or
2441 0 - if all the min_rates are 0.
16a5fd92 2442 In the later case fairness algorithm should be deactivated.
2691d51d
EG		 2443 If not all min_rates are zero then those that are zeroes will be set to 1.
2444 */
b475d78f
YM		 2445static void bnx2x_calc_vn_min(struct bnx2x *bp,
2446 struct cmng_init_input *input)
2691d51d
EG		 2447{
2448 int all_zero = 1;
2691d51d
EG		 2449 int vn;
2450
3395a033 2451 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2452 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2453 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2454 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2455
2456 /* Skip hidden vns */
2457 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
b475d78f 2458 vn_min_rate = 0;
2691d51d 2459 /* If min rate is zero - set it to 1 */
b475d78f 2460 else if (!vn_min_rate)
2691d51d
EG		 2461 vn_min_rate = DEF_MIN_RATE;
2462 else
2463 all_zero = 0;
2464
b475d78f 2465 input->vnic_min_rate[vn] = vn_min_rate;
2691d51d
EG		 2466 }
2467
30ae438b
DK		 2468 /* if ETS or all min rates are zeros - disable fairness */
2469 if (BNX2X_IS_ETS_ENABLED(bp)) {
b475d78f 2470 input->flags.cmng_enables &=
30ae438b
DK		 2471 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2472 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2473 } else if (all_zero) {
b475d78f 2474 input->flags.cmng_enables &=
b015e3d1 2475 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
b475d78f
YM		 2476 DP(NETIF_MSG_IFUP,
2477 "All MIN values are zeroes fairness will be disabled\n");
b015e3d1 2478 } else
b475d78f 2479 input->flags.cmng_enables |=
b015e3d1 2480 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2481}
2482
b475d78f
YM		 2483static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2484 struct cmng_init_input *input)
34f80b04 2485{
b475d78f 2486 u16 vn_max_rate;
f2e0899f 2487 u32 vn_cfg = bp->mf_config[vn];
34f80b04 2488
b475d78f 2489 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
34f80b04 2490 vn_max_rate = 0;
b475d78f 2491 else {
faa6fcbb
DK		 2492 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2493
b475d78f 2494 if (IS_MF_SI(bp)) {
faa6fcbb
DK		 2495 /* maxCfg in percents of linkspeed */
2496 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
b475d78f 2497 } else /* SD modes */
faa6fcbb
DK		 2498 /* maxCfg is absolute in 100Mb units */
2499 vn_max_rate = maxCfg * 100;
34f80b04 2500 }
f85582f8 2501
b475d78f 2502 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
34f80b04 2503
b475d78f 2504 input->vnic_max_rate[vn] = vn_max_rate;
34f80b04 2505}
f85582f8 2506
523224a3
DK		 2507static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2508{
2509 if (CHIP_REV_IS_SLOW(bp))
2510 return CMNG_FNS_NONE;
fb3bff17 2511 if (IS_MF(bp))
523224a3
DK		 2512 return CMNG_FNS_MINMAX;
2513
2514 return CMNG_FNS_NONE;
2515}
2516
2ae17f66 2517void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2518{
0793f83f 2519 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2520
2521 if (BP_NOMCP(bp))
16a5fd92 2522 return; /* what should be the default value in this case */
523224a3 2523
0793f83f
DK		 2524 /* For 2 port configuration the absolute function number formula
2525 * is:
2526 * abs_func = 2 * vn + BP_PORT + BP_PATH
2527 *
2528 * and there are 4 functions per port
2529 *
2530 * For 4 port configuration it is
2531 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2532 *
2533 * and there are 2 functions per port
2534 */
3395a033 2535 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2536 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2537
2538 if (func >= E1H_FUNC_MAX)
2539 break;
2540
f2e0899f 2541 bp->mf_config[vn] =
523224a3
DK		 2542 MF_CFG_RD(bp, func_mf_config[func].config);
2543 }
a3348722
BW		 2544 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2545 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2546 bp->flags |= MF_FUNC_DIS;
2547 } else {
2548 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2549 bp->flags &= ~MF_FUNC_DIS;
2550 }
523224a3
DK		 2551}
2552
2553static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2554{
b475d78f
YM		 2555 struct cmng_init_input input;
2556 memset(&input, 0, sizeof(struct cmng_init_input));
2557
2558 input.port_rate = bp->link_vars.line_speed;
523224a3 2559
568e2426 2560 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
523224a3
DK		 2561 int vn;
2562
523224a3
DK		 2563 /* read mf conf from shmem */
2564 if (read_cfg)
2565 bnx2x_read_mf_cfg(bp);
2566
523224a3 2567 /* vn_weight_sum and enable fairness if not 0 */
b475d78f 2568 bnx2x_calc_vn_min(bp, &input);
523224a3
DK		 2569
2570 /* calculate and set min-max rate for each vn */
c4154f25 2571 if (bp->port.pmf)
3395a033 2572 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
b475d78f 2573 bnx2x_calc_vn_max(bp, vn, &input);
523224a3
DK		 2574
2575 /* always enable rate shaping and fairness */
b475d78f 2576 input.flags.cmng_enables |=
523224a3 2577 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
b475d78f
YM		 2578
2579 bnx2x_init_cmng(&input, &bp->cmng);
523224a3
DK		 2580 return;
2581 }
2582
2583 /* rate shaping and fairness are disabled */
2584 DP(NETIF_MSG_IFUP,
2585 "rate shaping and fairness are disabled\n");
2586}
34f80b04 2587
1191cb83
ED		 2588static void storm_memset_cmng(struct bnx2x *bp,
2589 struct cmng_init *cmng,
2590 u8 port)
2591{
2592 int vn;
2593 size_t size = sizeof(struct cmng_struct_per_port);
2594
2595 u32 addr = BAR_XSTRORM_INTMEM +
2596 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2597
2598 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2599
2600 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2601 int func = func_by_vn(bp, vn);
2602
2603 addr = BAR_XSTRORM_INTMEM +
2604 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2605 size = sizeof(struct rate_shaping_vars_per_vn);
2606 __storm_memset_struct(bp, addr, size,
2607 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2608
2609 addr = BAR_XSTRORM_INTMEM +
2610 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2611 size = sizeof(struct fairness_vars_per_vn);
2612 __storm_memset_struct(bp, addr, size,
2613 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2614 }
2615}
2616
568e2426
DK		 2617/* init cmng mode in HW according to local configuration */
2618void bnx2x_set_local_cmng(struct bnx2x *bp)
2619{
2620 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2621
2622 if (cmng_fns != CMNG_FNS_NONE) {
2623 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2624 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2625 } else {
2626 /* rate shaping and fairness are disabled */
2627 DP(NETIF_MSG_IFUP,
2628 "single function mode without fairness\n");
2629 }
2630}
2631
c18487ee
YR		 2632/* This function is called upon link interrupt */
2633static void bnx2x_link_attn(struct bnx2x *bp)
2634{
bb2a0f7a
YG		 2635 /* Make sure that we are synced with the current statistics */
2636 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2637
c18487ee 2638 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2639
9156b30b 2640 bnx2x_init_dropless_fc(bp);
1c06328c 2641
9156b30b 2642 if (bp->link_vars.link_up) {
1c06328c 2643
619c5cb6 2644 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2645 struct host_port_stats *pstats;
2646
2647 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2648 /* reset old mac stats */
bb2a0f7a
YG		 2649 memset(&(pstats->mac_stx[0]), 0,
2650 sizeof(struct mac_stx));
2651 }
f34d28ea 2652 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2653 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2654 }
2655
568e2426
DK		 2656 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2657 bnx2x_set_local_cmng(bp);
9fdc3e95 2658
2ae17f66
VZ		 2659 __bnx2x_link_report(bp);
2660
9fdc3e95
DK		 2661 if (IS_MF(bp))
2662 bnx2x_link_sync_notify(bp);
c18487ee 2663}
a2fbb9ea 2664
9f6c9258 2665void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2666{
2ae17f66 2667 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2668 return;
a2fbb9ea 2669
00253a8c 2670 /* read updated dcb configuration */
ad5afc89
AE		 2671 if (IS_PF(bp)) {
2672 bnx2x_dcbx_pmf_update(bp);
2673 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2674 if (bp->link_vars.link_up)
2675 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2676 else
2677 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2678 /* indicate link status */
2679 bnx2x_link_report(bp);
a2fbb9ea 2680
ad5afc89
AE		 2681 } else { /* VF */
2682 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2683 SUPPORTED_10baseT_Full |
2684 SUPPORTED_100baseT_Half |
2685 SUPPORTED_100baseT_Full |
2686 SUPPORTED_1000baseT_Full |
2687 SUPPORTED_2500baseX_Full |
2688 SUPPORTED_10000baseT_Full |
2689 SUPPORTED_TP |
2690 SUPPORTED_FIBRE |
2691 SUPPORTED_Autoneg |
2692 SUPPORTED_Pause |
2693 SUPPORTED_Asym_Pause);
2694 bp->port.advertising[0] = bp->port.supported[0];
2695
2696 bp->link_params.bp = bp;
2697 bp->link_params.port = BP_PORT(bp);
2698 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2699 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2700 bp->link_params.req_line_speed[0] = SPEED_10000;
2701 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2702 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2703 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2704 bp->link_vars.line_speed = SPEED_10000;
2705 bp->link_vars.link_status =
2706 (LINK_STATUS_LINK_UP |
2707 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2708 bp->link_vars.link_up = 1;
2709 bp->link_vars.duplex = DUPLEX_FULL;
2710 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2711 __bnx2x_link_report(bp);
6495d15a
DK		 2712
2713 bnx2x_sample_bulletin(bp);
2714
2715 /* if bulletin board did not have an update for link status
2716 * __bnx2x_link_report will report current status
2717 * but it will NOT duplicate report in case of already reported
2718 * during sampling bulletin board.
2719 */
bb2a0f7a 2720 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
ad5afc89 2721 }
a2fbb9ea 2722}
a2fbb9ea 2723
a3348722
BW		 2724static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2725 u16 vlan_val, u8 allowed_prio)
2726{
86564c3f 2727 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2728 struct bnx2x_func_afex_update_params *f_update_params =
2729 &func_params.params.afex_update;
2730
2731 func_params.f_obj = &bp->func_obj;
2732 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2733
2734 /* no need to wait for RAMROD completion, so don't
2735 * set RAMROD_COMP_WAIT flag
2736 */
2737
2738 f_update_params->vif_id = vifid;
2739 f_update_params->afex_default_vlan = vlan_val;
2740 f_update_params->allowed_priorities = allowed_prio;
2741
2742 /* if ramrod can not be sent, response to MCP immediately */
2743 if (bnx2x_func_state_change(bp, &func_params) < 0)
2744 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2745
2746 return 0;
2747}
2748
2749static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2750 u16 vif_index, u8 func_bit_map)
2751{
86564c3f 2752 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2753 struct bnx2x_func_afex_viflists_params *update_params =
2754 &func_params.params.afex_viflists;
2755 int rc;
2756 u32 drv_msg_code;
2757
2758 /* validate only LIST_SET and LIST_GET are received from switch */
2759 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2760 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2761 cmd_type);
2762
2763 func_params.f_obj = &bp->func_obj;
2764 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2765
2766 /* set parameters according to cmd_type */
2767 update_params->afex_vif_list_command = cmd_type;
86564c3f 2768 update_params->vif_list_index = vif_index;
a3348722
BW		 2769 update_params->func_bit_map =
2770 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2771 update_params->func_to_clear = 0;
2772 drv_msg_code =
2773 (cmd_type == VIF_LIST_RULE_GET) ?
2774 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2775 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2776
2777 /* if ramrod can not be sent, respond to MCP immediately for
2778 * SET and GET requests (other are not triggered from MCP)
2779 */
2780 rc = bnx2x_func_state_change(bp, &func_params);
2781 if (rc < 0)
2782 bnx2x_fw_command(bp, drv_msg_code, 0);
2783
2784 return 0;
2785}
2786
2787static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2788{
2789 struct afex_stats afex_stats;
2790 u32 func = BP_ABS_FUNC(bp);
2791 u32 mf_config;
2792 u16 vlan_val;
2793 u32 vlan_prio;
2794 u16 vif_id;
2795 u8 allowed_prio;
2796 u8 vlan_mode;
2797 u32 addr_to_write, vifid, addrs, stats_type, i;
2798
2799 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2800 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2801 DP(BNX2X_MSG_MCP,
2802 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2803 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2804 }
2805
2806 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2807 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2808 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2809 DP(BNX2X_MSG_MCP,
2810 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2811 vifid, addrs);
2812 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2813 addrs);
2814 }
2815
2816 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2817 addr_to_write = SHMEM2_RD(bp,
2818 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2819 stats_type = SHMEM2_RD(bp,
2820 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2821
2822 DP(BNX2X_MSG_MCP,
2823 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2824 addr_to_write);
2825
2826 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2827
2828 /* write response to scratchpad, for MCP */
2829 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2830 REG_WR(bp, addr_to_write + i*sizeof(u32),
2831 *(((u32 *)(&afex_stats))+i));
2832
2833 /* send ack message to MCP */
2834 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2835 }
2836
2837 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2838 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2839 bp->mf_config[BP_VN(bp)] = mf_config;
2840 DP(BNX2X_MSG_MCP,
2841 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2842 mf_config);
2843
2844 /* if VIF_SET is "enabled" */
2845 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2846 /* set rate limit directly to internal RAM */
2847 struct cmng_init_input cmng_input;
2848 struct rate_shaping_vars_per_vn m_rs_vn;
2849 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2850 u32 addr = BAR_XSTRORM_INTMEM +
2851 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2852
2853 bp->mf_config[BP_VN(bp)] = mf_config;
2854
2855 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2856 m_rs_vn.vn_counter.rate =
2857 cmng_input.vnic_max_rate[BP_VN(bp)];
2858 m_rs_vn.vn_counter.quota =
2859 (m_rs_vn.vn_counter.rate *
2860 RS_PERIODIC_TIMEOUT_USEC) / 8;
2861
2862 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2863
2864 /* read relevant values from mf_cfg struct in shmem */
2865 vif_id =
2866 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2867 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2868 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2869 vlan_val =
2870 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2871 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2872 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2873 vlan_prio = (mf_config &
2874 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2875 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2876 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2877 vlan_mode =
2878 (MF_CFG_RD(bp,
2879 func_mf_config[func].afex_config) &
2880 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2881 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2882 allowed_prio =
2883 (MF_CFG_RD(bp,
2884 func_mf_config[func].afex_config) &
2885 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2886 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2887
2888 /* send ramrod to FW, return in case of failure */
2889 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2890 allowed_prio))
2891 return;
2892
2893 bp->afex_def_vlan_tag = vlan_val;
2894 bp->afex_vlan_mode = vlan_mode;
2895 } else {
2896 /* notify link down because BP->flags is disabled */
2897 bnx2x_link_report(bp);
2898
2899 /* send INVALID VIF ramrod to FW */
2900 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2901
2902 /* Reset the default afex VLAN */
2903 bp->afex_def_vlan_tag = -1;
2904 }
2905 }
2906}
2907
34f80b04
EG		 2908static void bnx2x_pmf_update(struct bnx2x *bp)
2909{
2910 int port = BP_PORT(bp);
2911 u32 val;
2912
2913 bp->port.pmf = 1;
51c1a580 2914 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
34f80b04 2915
3deb8167
YR		 2916 /*
2917 * We need the mb() to ensure the ordering between the writing to
2918 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2919 */
2920 smp_mb();
2921
2922 /* queue a periodic task */
2923 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2924
ef01854e
DK		 2925 bnx2x_dcbx_pmf_update(bp);
2926
34f80b04 2927 /* enable nig attention */
3395a033 2928 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2929 if (bp->common.int_block == INT_BLOCK_HC) {
2930 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2931 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2932 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2933 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2934 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2935 }
bb2a0f7a
YG		 2936
2937 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2938}
2939
c18487ee 2940/* end of Link */
a2fbb9ea
ET		 2941
2942/* slow path */
2943
2944/*
2945 * General service functions
2946 */
2947
2691d51d 2948/* send the MCP a request, block until there is a reply */
a22f0788 2949u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2950{
f2e0899f 2951 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2952 u32 seq;
2691d51d
EG		 2953 u32 rc = 0;
2954 u32 cnt = 1;
2955 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2956
c4ff7cbf 2957 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2958 seq = ++bp->fw_seq;
f2e0899f
DK		 2959 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2960 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2961
754a2f52
DK		 2962 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2963 (command | seq), param);
2691d51d
EG		 2964
2965 do {
2966 /* let the FW do it's magic ... */
2967 msleep(delay);
2968
f2e0899f 2969 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2970
c4ff7cbf
EG		 2971 /* Give the FW up to 5 second (500*10ms) */
2972 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2973
2974 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2975 cnt*delay, rc, seq);
2976
2977 /* is this a reply to our command? */
2978 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2979 rc &= FW_MSG_CODE_MASK;
2980 else {
2981 /* FW BUG! */
2982 BNX2X_ERR("FW failed to respond!\n");
2983 bnx2x_fw_dump(bp);
2984 rc = 0;
2985 }
c4ff7cbf 2986 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2987
2988 return rc;
2989}
2990
1191cb83
ED		 2991static void storm_memset_func_cfg(struct bnx2x *bp,
2992 struct tstorm_eth_function_common_config *tcfg,
2993 u16 abs_fid)
2994{
2995 size_t size = sizeof(struct tstorm_eth_function_common_config);
2996
2997 u32 addr = BAR_TSTRORM_INTMEM +
2998 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2999
3000 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3001}
3002
619c5cb6
VZ		 3003void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3004{
3005 if (CHIP_IS_E1x(bp)) {
3006 struct tstorm_eth_function_common_config tcfg = {0};
3007
3008 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3009 }
3010
3011 /* Enable the function in the FW */
3012 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3013 storm_memset_func_en(bp, p->func_id, 1);
3014
3015 /* spq */
3016 if (p->func_flgs & FUNC_FLG_SPQ) {
3017 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3018 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3019 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3020 }
3021}
3022
6383c0b3 3023/**
16a5fd92 3024 * bnx2x_get_common_flags - Return common flags
6383c0b3
AE		 3025 *
3026 * @bp device handle
3027 * @fp queue handle
3028 * @zero_stats TRUE if statistics zeroing is needed
3029 *
3030 * Return the flags that are common for the Tx-only and not normal connections.
3031 */
1191cb83
ED		 3032static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3033 struct bnx2x_fastpath *fp,
3034 bool zero_stats)
28912902 3035{
619c5cb6
VZ		 3036 unsigned long flags = 0;
3037
3038 /* PF driver will always initialize the Queue to an ACTIVE state */
3039 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 3040
6383c0b3 3041 /* tx only connections collect statistics (on the same index as the
91226790
DK		 3042 * parent connection). The statistics are zeroed when the parent
3043 * connection is initialized.
6383c0b3 3044 */
50f0a562
BW		 3045
3046 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3047 if (zero_stats)
3048 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3049
c14db202
YM		 3050 if (bp->flags & TX_SWITCHING)
3051 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3052
91226790 3053 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
e287a75c 3054 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
6383c0b3 3055
823e1d90
YM		 3056#ifdef BNX2X_STOP_ON_ERROR
3057 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3058#endif
3059
6383c0b3
AE		 3060 return flags;
3061}
3062
1191cb83
ED		 3063static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3064 struct bnx2x_fastpath *fp,
3065 bool leading)
6383c0b3
AE		 3066{
3067 unsigned long flags = 0;
3068
619c5cb6
VZ		 3069 /* calculate other queue flags */
3070 if (IS_MF_SD(bp))
3071 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 3072
a3348722 3073 if (IS_FCOE_FP(fp)) {
619c5cb6 3074 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
a3348722
BW		 3075 /* For FCoE - force usage of default priority (for afex) */
3076 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3077 }
523224a3 3078
f5219d8e 3079 if (!fp->disable_tpa) {
619c5cb6 3080 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e 3081 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
621b4d66
DK		 3082 if (fp->mode == TPA_MODE_GRO)
3083 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
f5219d8e 3084 }
619c5cb6 3085
619c5cb6
VZ		 3086 if (leading) {
3087 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3088 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3089 }
523224a3 3090
619c5cb6
VZ		 3091 /* Always set HW VLAN stripping */
3092 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 3093
a3348722
BW		 3094 /* configure silent vlan removal */
3095 if (IS_MF_AFEX(bp))
3096 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3097
6383c0b3 3098 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 3099}
3100
619c5cb6 3101static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 3102 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3103 u8 cos)
619c5cb6
VZ		 3104{
3105 gen_init->stat_id = bnx2x_stats_id(fp);
3106 gen_init->spcl_id = fp->cl_id;
3107
3108 /* Always use mini-jumbo MTU for FCoE L2 ring */
3109 if (IS_FCOE_FP(fp))
3110 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3111 else
3112 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 3113
3114 gen_init->cos = cos;
619c5cb6
VZ		 3115}
3116
3117static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 3118 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 3119 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 3120{
619c5cb6 3121 u8 max_sge = 0;
523224a3
DK		 3122 u16 sge_sz = 0;
3123 u16 tpa_agg_size = 0;
3124
523224a3 3125 if (!fp->disable_tpa) {
dfacf138
DK		 3126 pause->sge_th_lo = SGE_TH_LO(bp);
3127 pause->sge_th_hi = SGE_TH_HI(bp);
3128
3129 /* validate SGE ring has enough to cross high threshold */
3130 WARN_ON(bp->dropless_fc &&
3131 pause->sge_th_hi + FW_PREFETCH_CNT >
3132 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3133
924d75ab 3134 tpa_agg_size = TPA_AGG_SIZE;
523224a3
DK		 3135 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3136 SGE_PAGE_SHIFT;
3137 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3138 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
924d75ab 3139 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
523224a3
DK		 3140 }
3141
3142 /* pause - not for e1 */
3143 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 3144 pause->bd_th_lo = BD_TH_LO(bp);
3145 pause->bd_th_hi = BD_TH_HI(bp);
3146
3147 pause->rcq_th_lo = RCQ_TH_LO(bp);
3148 pause->rcq_th_hi = RCQ_TH_HI(bp);
3149 /*
3150 * validate that rings have enough entries to cross
3151 * high thresholds
3152 */
3153 WARN_ON(bp->dropless_fc &&
3154 pause->bd_th_hi + FW_PREFETCH_CNT >
3155 bp->rx_ring_size);
3156 WARN_ON(bp->dropless_fc &&
3157 pause->rcq_th_hi + FW_PREFETCH_CNT >
3158 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 3159
523224a3
DK		 3160 pause->pri_map = 1;
3161 }
3162
3163 /* rxq setup */
523224a3
DK		 3164 rxq_init->dscr_map = fp->rx_desc_mapping;
3165 rxq_init->sge_map = fp->rx_sge_mapping;
3166 rxq_init->rcq_map = fp->rx_comp_mapping;
3167 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 3168
619c5cb6
VZ		 3169 /* This should be a maximum number of data bytes that may be
3170 * placed on the BD (not including paddings).
3171 */
e52fcb24 3172 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3cdeec22 3173 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 3174
523224a3 3175 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 3176 rxq_init->tpa_agg_sz = tpa_agg_size;
3177 rxq_init->sge_buf_sz = sge_sz;
3178 rxq_init->max_sges_pkt = max_sge;
619c5cb6 3179 rxq_init->rss_engine_id = BP_FUNC(bp);
259afa1f 3180 rxq_init->mcast_engine_id = BP_FUNC(bp);
619c5cb6
VZ		 3181
3182 /* Maximum number or simultaneous TPA aggregation for this Queue.
3183 *
2de67439 3184 * For PF Clients it should be the maximum available number.
619c5cb6
VZ		 3185 * VF driver(s) may want to define it to a smaller value.
3186 */
dfacf138 3187 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 3188
523224a3
DK		 3189 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3190 rxq_init->fw_sb_id = fp->fw_sb_id;
3191
ec6ba945
VZ		 3192 if (IS_FCOE_FP(fp))
3193 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3194 else
6383c0b3 3195 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
a3348722
BW		 3196 /* configure silent vlan removal
3197 * if multi function mode is afex, then mask default vlan
3198 */
3199 if (IS_MF_AFEX(bp)) {
3200 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3201 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3202 }
523224a3
DK		 3203}
3204
619c5cb6 3205static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 3206 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3207 u8 cos)
523224a3 3208{
65565884 3209 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
6383c0b3 3210 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 3211 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3212 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 3213
619c5cb6 3214 /*
16a5fd92 3215 * set the tss leading client id for TX classification ==
619c5cb6
VZ		 3216 * leading RSS client id
3217 */
3218 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3219
ec6ba945
VZ		 3220 if (IS_FCOE_FP(fp)) {
3221 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3222 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3223 }
523224a3
DK		 3224}
3225
8d96286a 3226static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 3227{
3228 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 3229 struct event_ring_data eq_data = { {0} };
3230 u16 flags;
3231
619c5cb6 3232 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3233 /* reset IGU PF statistics: MSIX + ATTN */
3234 /* PF */
3235 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3236 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3237 (CHIP_MODE_IS_4_PORT(bp) ?
3238 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3239 /* ATTN */
3240 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3241 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3242 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3243 (CHIP_MODE_IS_4_PORT(bp) ?
3244 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3245 }
3246
523224a3
DK		 3247 /* function setup flags */
3248 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3249
619c5cb6
VZ		 3250 /* This flag is relevant for E1x only.
3251 * E2 doesn't have a TPA configuration in a function level.
523224a3 3252 */
619c5cb6 3253 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 3254
3255 func_init.func_flgs = flags;
3256 func_init.pf_id = BP_FUNC(bp);
3257 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 3258 func_init.spq_map = bp->spq_mapping;
3259 func_init.spq_prod = bp->spq_prod_idx;
3260
3261 bnx2x_func_init(bp, &func_init);
3262
3263 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3264
3265 /*
619c5cb6
VZ		 3266 * Congestion management values depend on the link rate
3267 * There is no active link so initial link rate is set to 10 Gbps.
3268 * When the link comes up The congestion management values are
3269 * re-calculated according to the actual link rate.
3270 */
523224a3
DK		 3271 bp->link_vars.line_speed = SPEED_10000;
3272 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3273
3274 /* Only the PMF sets the HW */
3275 if (bp->port.pmf)
3276 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3277
86564c3f 3278 /* init Event Queue - PCI bus guarantees correct endianity*/
523224a3
DK		 3279 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3280 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3281 eq_data.producer = bp->eq_prod;
3282 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3283 eq_data.sb_id = DEF_SB_ID;
3284 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3285}
3286
523224a3
DK		 3287static void bnx2x_e1h_disable(struct bnx2x *bp)
3288{
3289 int port = BP_PORT(bp);
3290
619c5cb6 3291 bnx2x_tx_disable(bp);
523224a3
DK		 3292
3293 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 3294}
3295
3296static void bnx2x_e1h_enable(struct bnx2x *bp)
3297{
3298 int port = BP_PORT(bp);
3299
3300 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3301
16a5fd92 3302 /* Tx queue should be only re-enabled */
523224a3
DK		 3303 netif_tx_wake_all_queues(bp->dev);
3304
3305 /*
3306 * Should not call netif_carrier_on since it will be called if the link
3307 * is up when checking for link state
3308 */
3309}
3310
1d187b34
BW		 3311#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3312
3313static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3314{
3315 struct eth_stats_info *ether_stat =
3316 &bp->slowpath->drv_info_to_mcp.ether_stat;
3ec9f9ca
AE		 3317 struct bnx2x_vlan_mac_obj *mac_obj =
3318 &bp->sp_objs->mac_obj;
3319 int i;
1d187b34 3320
786fdf0b
DC		 3321 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3322 ETH_STAT_INFO_VERSION_LEN);
1d187b34 3323
3ec9f9ca
AE		 3324 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3325 * mac_local field in ether_stat struct. The base address is offset by 2
3326 * bytes to account for the field being 8 bytes but a mac address is
3327 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3328 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3329 * allocated by the ether_stat struct, so the macs will land in their
3330 * proper positions.
3331 */
3332 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3333 memset(ether_stat->mac_local + i, 0,
3334 sizeof(ether_stat->mac_local[0]));
3335 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3336 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3337 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3338 ETH_ALEN);
1d187b34 3339 ether_stat->mtu_size = bp->dev->mtu;
1d187b34
BW		 3340 if (bp->dev->features & NETIF_F_RXCSUM)
3341 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3342 if (bp->dev->features & NETIF_F_TSO)
3343 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3344 ether_stat->feature_flags |= bp->common.boot_mode;
3345
3346 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3347
3348 ether_stat->txq_size = bp->tx_ring_size;
3349 ether_stat->rxq_size = bp->rx_ring_size;
0c757dee 3350
fcf93a0a 3351#ifdef CONFIG_BNX2X_SRIOV
0c757dee 3352 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
fcf93a0a 3353#endif
1d187b34
BW		 3354}
3355
3356static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3357{
3358 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3359 struct fcoe_stats_info *fcoe_stat =
3360 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3361
55c11941
MS		 3362 if (!CNIC_LOADED(bp))
3363 return;
3364
3ec9f9ca 3365 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
1d187b34
BW		 3366
3367 fcoe_stat->qos_priority =
3368 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3369
3370 /* insert FCoE stats from ramrod response */
3371 if (!NO_FCOE(bp)) {
3372 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
65565884 3373 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3374 tstorm_queue_statistics;
3375
3376 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
65565884 3377 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3378 xstorm_queue_statistics;
3379
3380 struct fcoe_statistics_params *fw_fcoe_stat =
3381 &bp->fw_stats_data->fcoe;
3382
86564c3f
YM		 3383 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3384 fcoe_stat->rx_bytes_lo,
3385 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
1d187b34 3386
86564c3f
YM		 3387 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3388 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3389 fcoe_stat->rx_bytes_lo,
3390 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
1d187b34 3391
86564c3f
YM		 3392 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3393 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3394 fcoe_stat->rx_bytes_lo,
3395 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
1d187b34 3396
86564c3f
YM		 3397 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3398 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3399 fcoe_stat->rx_bytes_lo,
3400 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
1d187b34 3401
86564c3f
YM		 3402 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3403 fcoe_stat->rx_frames_lo,
3404 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
1d187b34 3405
86564c3f
YM		 3406 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3407 fcoe_stat->rx_frames_lo,
3408 fcoe_q_tstorm_stats->rcv_ucast_pkts);
1d187b34 3409
86564c3f
YM		 3410 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3411 fcoe_stat->rx_frames_lo,
3412 fcoe_q_tstorm_stats->rcv_bcast_pkts);
1d187b34 3413
86564c3f
YM		 3414 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3415 fcoe_stat->rx_frames_lo,
3416 fcoe_q_tstorm_stats->rcv_mcast_pkts);
1d187b34 3417
86564c3f
YM		 3418 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3419 fcoe_stat->tx_bytes_lo,
3420 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
1d187b34 3421
86564c3f
YM		 3422 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3423 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3424 fcoe_stat->tx_bytes_lo,
3425 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
1d187b34 3426
86564c3f
YM		 3427 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3428 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3429 fcoe_stat->tx_bytes_lo,
3430 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
1d187b34 3431
86564c3f
YM		 3432 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3433 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3434 fcoe_stat->tx_bytes_lo,
3435 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
1d187b34 3436
86564c3f
YM		 3437 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3438 fcoe_stat->tx_frames_lo,
3439 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
1d187b34 3440
86564c3f
YM		 3441 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3442 fcoe_stat->tx_frames_lo,
3443 fcoe_q_xstorm_stats->ucast_pkts_sent);
1d187b34 3444
86564c3f
YM		 3445 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3446 fcoe_stat->tx_frames_lo,
3447 fcoe_q_xstorm_stats->bcast_pkts_sent);
1d187b34 3448
86564c3f
YM		 3449 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3450 fcoe_stat->tx_frames_lo,
3451 fcoe_q_xstorm_stats->mcast_pkts_sent);
1d187b34
BW		 3452 }
3453
1d187b34
BW		 3454 /* ask L5 driver to add data to the struct */
3455 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
1d187b34
BW		 3456}
3457
3458static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3459{
3460 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3461 struct iscsi_stats_info *iscsi_stat =
3462 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3463
55c11941
MS		 3464 if (!CNIC_LOADED(bp))
3465 return;
3466
3ec9f9ca
AE		 3467 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3468 ETH_ALEN);
1d187b34
BW		 3469
3470 iscsi_stat->qos_priority =
3471 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3472
1d187b34
BW		 3473 /* ask L5 driver to add data to the struct */
3474 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
1d187b34
BW		 3475}
3476
0793f83f
DK		 3477/* called due to MCP event (on pmf):
3478 * reread new bandwidth configuration
3479 * configure FW
3480 * notify others function about the change
3481 */
1191cb83 3482static void bnx2x_config_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3483{
3484 if (bp->link_vars.link_up) {
3485 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3486 bnx2x_link_sync_notify(bp);
3487 }
3488 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3489}
3490
1191cb83 3491static void bnx2x_set_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3492{
3493 bnx2x_config_mf_bw(bp);
3494 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3495}
3496
c8c60d88
YM		 3497static void bnx2x_handle_eee_event(struct bnx2x *bp)
3498{
3499 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3500 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3501}
3502
42f8277f
YM		 3503#define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3504#define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3505
1d187b34
BW		 3506static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3507{
3508 enum drv_info_opcode op_code;
3509 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
42f8277f
YM		 3510 bool release = false;
3511 int wait;
1d187b34
BW		 3512
3513 /* if drv_info version supported by MFW doesn't match - send NACK */
3514 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3515 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3516 return;
3517 }
3518
3519 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3520 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3521
42f8277f
YM		 3522 /* Must prevent other flows from accessing drv_info_to_mcp */
3523 mutex_lock(&bp->drv_info_mutex);
3524
1d187b34
BW		 3525 memset(&bp->slowpath->drv_info_to_mcp, 0,
3526 sizeof(union drv_info_to_mcp));
3527
3528 switch (op_code) {
3529 case ETH_STATS_OPCODE:
3530 bnx2x_drv_info_ether_stat(bp);
3531 break;
3532 case FCOE_STATS_OPCODE:
3533 bnx2x_drv_info_fcoe_stat(bp);
3534 break;
3535 case ISCSI_STATS_OPCODE:
3536 bnx2x_drv_info_iscsi_stat(bp);
3537 break;
3538 default:
3539 /* if op code isn't supported - send NACK */
3540 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
42f8277f 3541 goto out;
1d187b34
BW		 3542 }
3543
3544 /* if we got drv_info attn from MFW then these fields are defined in
3545 * shmem2 for sure
3546 */
3547 SHMEM2_WR(bp, drv_info_host_addr_lo,
3548 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3549 SHMEM2_WR(bp, drv_info_host_addr_hi,
3550 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3551
3552 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
42f8277f
YM		 3553
3554 /* Since possible management wants both this and get_driver_version
3555 * need to wait until management notifies us it finished utilizing
3556 * the buffer.
3557 */
3558 if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3559 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3560 } else if (!bp->drv_info_mng_owner) {
3561 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3562
3563 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3564 u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3565
3566 /* Management is done; need to clear indication */
3567 if (indication & bit) {
3568 SHMEM2_WR(bp, mfw_drv_indication,
3569 indication & ~bit);
3570 release = true;
3571 break;
3572 }
3573
3574 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3575 }
3576 }
3577 if (!release) {
3578 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3579 bp->drv_info_mng_owner = true;
3580 }
3581
3582out:
3583 mutex_unlock(&bp->drv_info_mutex);
3584}
3585
3586static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3587{
3588 u8 vals[4];
3589 int i = 0;
3590
3591 if (bnx2x_format) {
3592 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3593 &vals[0], &vals[1], &vals[2], &vals[3]);
3594 if (i > 0)
3595 vals[0] -= '0';
3596 } else {
3597 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3598 &vals[0], &vals[1], &vals[2], &vals[3]);
3599 }
3600
3601 while (i < 4)
3602 vals[i++] = 0;
3603
3604 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3605}
3606
3607void bnx2x_update_mng_version(struct bnx2x *bp)
3608{
3609 u32 iscsiver = DRV_VER_NOT_LOADED;
3610 u32 fcoever = DRV_VER_NOT_LOADED;
3611 u32 ethver = DRV_VER_NOT_LOADED;
3612 int idx = BP_FW_MB_IDX(bp);
3613 u8 *version;
3614
3615 if (!SHMEM2_HAS(bp, func_os_drv_ver))
3616 return;
3617
3618 mutex_lock(&bp->drv_info_mutex);
3619 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3620 if (bp->drv_info_mng_owner)
3621 goto out;
3622
3623 if (bp->state != BNX2X_STATE_OPEN)
3624 goto out;
3625
3626 /* Parse ethernet driver version */
3627 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3628 if (!CNIC_LOADED(bp))
3629 goto out;
3630
3631 /* Try getting storage driver version via cnic */
3632 memset(&bp->slowpath->drv_info_to_mcp, 0,
3633 sizeof(union drv_info_to_mcp));
3634 bnx2x_drv_info_iscsi_stat(bp);
3635 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3636 iscsiver = bnx2x_update_mng_version_utility(version, false);
3637
3638 memset(&bp->slowpath->drv_info_to_mcp, 0,
3639 sizeof(union drv_info_to_mcp));
3640 bnx2x_drv_info_fcoe_stat(bp);
3641 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3642 fcoever = bnx2x_update_mng_version_utility(version, false);
3643
3644out:
3645 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3646 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3647 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3648
3649 mutex_unlock(&bp->drv_info_mutex);
3650
3651 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3652 ethver, iscsiver, fcoever);
1d187b34
BW		 3653}
3654
523224a3
DK		 3655static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3656{
3657 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3658
3659 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3660
3661 /*
3662 * This is the only place besides the function initialization
3663 * where the bp->flags can change so it is done without any
3664 * locks
3665 */
f2e0899f 3666 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
51c1a580 3667 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
523224a3
DK		 3668 bp->flags |= MF_FUNC_DIS;
3669
3670 bnx2x_e1h_disable(bp);
3671 } else {
51c1a580 3672 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
523224a3
DK		 3673 bp->flags &= ~MF_FUNC_DIS;
3674
3675 bnx2x_e1h_enable(bp);
3676 }
3677 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3678 }
3679 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 3680 bnx2x_config_mf_bw(bp);
523224a3
DK		 3681 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3682 }
3683
3684 /* Report results to MCP */
3685 if (dcc_event)
3686 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3687 else
3688 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3689}
3690
3691/* must be called under the spq lock */
1191cb83 3692static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
523224a3
DK		 3693{
3694 struct eth_spe *next_spe = bp->spq_prod_bd;
3695
3696 if (bp->spq_prod_bd == bp->spq_last_bd) {
3697 bp->spq_prod_bd = bp->spq;
3698 bp->spq_prod_idx = 0;
51c1a580 3699 DP(BNX2X_MSG_SP, "end of spq\n");
523224a3
DK		 3700 } else {
3701 bp->spq_prod_bd++;
3702 bp->spq_prod_idx++;
3703 }
3704 return next_spe;
3705}
3706
3707/* must be called under the spq lock */
1191cb83 3708static void bnx2x_sp_prod_update(struct bnx2x *bp)
28912902
MC		 3709{
3710 int func = BP_FUNC(bp);
3711
53e51e2f
VZ		 3712 /*
3713 * Make sure that BD data is updated before writing the producer:
3714 * BD data is written to the memory, the producer is read from the
3715 * memory, thus we need a full memory barrier to ensure the ordering.
3716 */
3717 mb();
28912902 3718
523224a3 3719 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3720 bp->spq_prod_idx);
28912902
MC		 3721 mmiowb();
3722}
3723
619c5cb6
VZ		 3724/**
3725 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3726 *
3727 * @cmd: command to check
3728 * @cmd_type: command type
3729 */
1191cb83 3730static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
619c5cb6
VZ		 3731{
3732 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3733 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3734 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3735 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3736 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3737 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3738 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3739 return true;
3740 else
3741 return false;
619c5cb6
VZ		 3742}
3743
619c5cb6
VZ		 3744/**
3745 * bnx2x_sp_post - place a single command on an SP ring
3746 *
3747 * @bp: driver handle
3748 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3749 * @cid: SW CID the command is related to
3750 * @data_hi: command private data address (high 32 bits)
3751 * @data_lo: command private data address (low 32 bits)
3752 * @cmd_type: command type (e.g. NONE, ETH)
3753 *
3754 * SP data is handled as if it's always an address pair, thus data fields are
3755 * not swapped to little endian in upper functions. Instead this function swaps
3756 * data as if it's two u32 fields.
3757 */
9f6c9258 3758int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3759 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3760{
28912902 3761 struct eth_spe *spe;
523224a3 3762 u16 type;
619c5cb6 3763 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3764
a2fbb9ea 3765#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 3766 if (unlikely(bp->panic)) {
3767 BNX2X_ERR("Can't post SP when there is panic\n");
a2fbb9ea 3768 return -EIO;
51c1a580 3769 }
a2fbb9ea
ET		 3770#endif
3771
34f80b04 3772 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3773
6e30dd4e
VZ		 3774 if (common) {
3775 if (!atomic_read(&bp->eq_spq_left)) {
3776 BNX2X_ERR("BUG! EQ ring full!\n");
3777 spin_unlock_bh(&bp->spq_lock);
3778 bnx2x_panic();
3779 return -EBUSY;
3780 }
3781 } else if (!atomic_read(&bp->cq_spq_left)) {
3782 BNX2X_ERR("BUG! SPQ ring full!\n");
3783 spin_unlock_bh(&bp->spq_lock);
3784 bnx2x_panic();
3785 return -EBUSY;
a2fbb9ea 3786 }
f1410647 3787
28912902
MC		 3788 spe = bnx2x_sp_get_next(bp);
3789
a2fbb9ea 3790 /* CID needs port number to be encoded int it */
28912902 3791 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3792 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3793 HW_CID(bp, cid));
523224a3 3794
14a94ebd
MK		 3795 /* In some cases, type may already contain the func-id
3796 * mainly in SRIOV related use cases, so we add it here only
3797 * if it's not already set.
3798 */
3799 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3800 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3801 SPE_HDR_CONN_TYPE;
3802 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3803 SPE_HDR_FUNCTION_ID);
3804 } else {
3805 type = cmd_type;
3806 }
a2fbb9ea 3807
523224a3
DK		 3808 spe->hdr.type = cpu_to_le16(type);
3809
3810 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3811 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3812
d6cae238
VZ		 3813 /*
3814 * It's ok if the actual decrement is issued towards the memory
3815 * somewhere between the spin_lock and spin_unlock. Thus no
16a5fd92 3816 * more explicit memory barrier is needed.
d6cae238
VZ		 3817 */
3818 if (common)
3819 atomic_dec(&bp->eq_spq_left);
3820 else
3821 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3822
51c1a580
MS		 3823 DP(BNX2X_MSG_SP,
3824 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3825 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3826 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3827 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3828 HW_CID(bp, cid), data_hi, data_lo, type,
3829 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3830
28912902 3831 bnx2x_sp_prod_update(bp);
34f80b04 3832 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3833 return 0;
3834}
3835
3836/* acquire split MCP access lock register */
4a37fb66 3837static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3838{
72fd0718 3839 u32 j, val;
34f80b04 3840 int rc = 0;
a2fbb9ea
ET		 3841
3842 might_sleep();
72fd0718 3843 for (j = 0; j < 1000; j++) {
3cdeec22
YM		 3844 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3845 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3846 if (val & MCPR_ACCESS_LOCK_LOCK)
a2fbb9ea
ET		 3847 break;
3848
639d65b8 3849 usleep_range(5000, 10000);
a2fbb9ea 3850 }
3cdeec22 3851 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
19680c48 3852 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3853 rc = -EBUSY;
3854 }
3855
3856 return rc;
3857}
3858
4a37fb66
YG		 3859/* release split MCP access lock register */
3860static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3861{
3cdeec22 3862 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
a2fbb9ea
ET		 3863}
3864
523224a3
DK		 3865#define BNX2X_DEF_SB_ATT_IDX 0x0001
3866#define BNX2X_DEF_SB_IDX 0x0002
3867
1191cb83 3868static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
a2fbb9ea 3869{
523224a3 3870 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3871 u16 rc = 0;
3872
3873 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3874 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3875 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3876 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3877 }
523224a3
DK		 3878
3879 if (bp->def_idx != def_sb->sp_sb.running_index) {
3880 bp->def_idx = def_sb->sp_sb.running_index;
3881 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3882 }
523224a3 3883
16a5fd92 3884 /* Do not reorder: indices reading should complete before handling */
523224a3 3885 barrier();
a2fbb9ea
ET		 3886 return rc;
3887}
3888
3889/*
3890 * slow path service functions
3891 */
3892
3893static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3894{
34f80b04 3895 int port = BP_PORT(bp);
a2fbb9ea
ET		 3896 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3897 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3898 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3899 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3900 u32 aeu_mask;
87942b46 3901 u32 nig_mask = 0;
f2e0899f 3902 u32 reg_addr;
a2fbb9ea 3903
a2fbb9ea
ET		 3904 if (bp->attn_state & asserted)
3905 BNX2X_ERR("IGU ERROR\n");
3906
3fcaf2e5
EG		 3907 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3908 aeu_mask = REG_RD(bp, aeu_addr);
3909
a2fbb9ea 3910 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3911 aeu_mask, asserted);
72fd0718 3912 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3913 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3914
3fcaf2e5
EG		 3915 REG_WR(bp, aeu_addr, aeu_mask);
3916 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3917
3fcaf2e5 3918 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3919 bp->attn_state |= asserted;
3fcaf2e5 3920 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3921
3922 if (asserted & ATTN_HARD_WIRED_MASK) {
3923 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3924
a5e9a7cf
EG		 3925 bnx2x_acquire_phy_lock(bp);
3926
877e9aa4 3927 /* save nig interrupt mask */
87942b46 3928 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3929
361c391e
YR		 3930 /* If nig_mask is not set, no need to call the update
3931 * function.
3932 */
3933 if (nig_mask) {
3934 REG_WR(bp, nig_int_mask_addr, 0);
3935
3936 bnx2x_link_attn(bp);
3937 }
a2fbb9ea
ET		 3938
3939 /* handle unicore attn? */
3940 }
3941 if (asserted & ATTN_SW_TIMER_4_FUNC)
3942 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3943
3944 if (asserted & GPIO_2_FUNC)
3945 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3946
3947 if (asserted & GPIO_3_FUNC)
3948 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3949
3950 if (asserted & GPIO_4_FUNC)
3951 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3952
3953 if (port == 0) {
3954 if (asserted & ATTN_GENERAL_ATTN_1) {
3955 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3956 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3957 }
3958 if (asserted & ATTN_GENERAL_ATTN_2) {
3959 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3960 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3961 }
3962 if (asserted & ATTN_GENERAL_ATTN_3) {
3963 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3964 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3965 }
3966 } else {
3967 if (asserted & ATTN_GENERAL_ATTN_4) {
3968 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3969 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3970 }
3971 if (asserted & ATTN_GENERAL_ATTN_5) {
3972 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3973 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3974 }
3975 if (asserted & ATTN_GENERAL_ATTN_6) {
3976 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3977 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3978 }
3979 }
3980
3981 } /* if hardwired */
3982
f2e0899f
DK		 3983 if (bp->common.int_block == INT_BLOCK_HC)
3984 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3985 COMMAND_REG_ATTN_BITS_SET);
3986 else
3987 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3988
3989 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3990 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3991 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3992
3993 /* now set back the mask */
a5e9a7cf 3994 if (asserted & ATTN_NIG_FOR_FUNC) {
27c1151c
YR		 3995 /* Verify that IGU ack through BAR was written before restoring
3996 * NIG mask. This loop should exit after 2-3 iterations max.
3997 */
3998 if (bp->common.int_block != INT_BLOCK_HC) {
3999 u32 cnt = 0, igu_acked;
4000 do {
4001 igu_acked = REG_RD(bp,
4002 IGU_REG_ATTENTION_ACK_BITS);
4003 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4004 (++cnt < MAX_IGU_ATTN_ACK_TO));
4005 if (!igu_acked)
4006 DP(NETIF_MSG_HW,
4007 "Failed to verify IGU ack on time\n");
4008 barrier();
4009 }
87942b46 4010 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 4011 bnx2x_release_phy_lock(bp);
4012 }
a2fbb9ea
ET		 4013}
4014
1191cb83 4015static void bnx2x_fan_failure(struct bnx2x *bp)
fd4ef40d
EG		 4016{
4017 int port = BP_PORT(bp);
b7737c9b 4018 u32 ext_phy_config;
fd4ef40d 4019 /* mark the failure */
b7737c9b
YR		 4020 ext_phy_config =
4021 SHMEM_RD(bp,
4022 dev_info.port_hw_config[port].external_phy_config);
4023
4024 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4025 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 4026 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 4027 ext_phy_config);
fd4ef40d
EG		 4028
4029 /* log the failure */
51c1a580
MS		 4030 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4031 "Please contact OEM Support for assistance\n");
8304859a 4032
16a5fd92 4033 /* Schedule device reset (unload)
8304859a
AE		 4034 * This is due to some boards consuming sufficient power when driver is
4035 * up to overheat if fan fails.
4036 */
230bb0f3 4037 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
fd4ef40d 4038}
ab6ad5a4 4039
1191cb83 4040static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 4041{
34f80b04 4042 int port = BP_PORT(bp);
877e9aa4 4043 int reg_offset;
d90d96ba 4044 u32 val;
877e9aa4 4045
34f80b04
EG		 4046 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4047 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 4048
34f80b04 4049 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 4050
4051 val = REG_RD(bp, reg_offset);
4052 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4053 REG_WR(bp, reg_offset, val);
4054
4055 BNX2X_ERR("SPIO5 hw attention\n");
4056
fd4ef40d 4057 /* Fan failure attention */
d90d96ba 4058 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 4059 bnx2x_fan_failure(bp);
877e9aa4 4060 }
34f80b04 4061
3deb8167 4062 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 4063 bnx2x_acquire_phy_lock(bp);
4064 bnx2x_handle_module_detect_int(&bp->link_params);
4065 bnx2x_release_phy_lock(bp);
4066 }
4067
34f80b04
EG		 4068 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4069
4070 val = REG_RD(bp, reg_offset);
4071 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4072 REG_WR(bp, reg_offset, val);
4073
4074 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 4075 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 4076 bnx2x_panic();
4077 }
877e9aa4
ET		 4078}
4079
1191cb83 4080static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4081{
4082 u32 val;
4083
0626b899 4084 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 4085
4086 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4087 BNX2X_ERR("DB hw attention 0x%x\n", val);
4088 /* DORQ discard attention */
4089 if (val & 0x2)
4090 BNX2X_ERR("FATAL error from DORQ\n");
4091 }
34f80b04
EG		 4092
4093 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4094
4095 int port = BP_PORT(bp);
4096 int reg_offset;
4097
4098 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4099 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4100
4101 val = REG_RD(bp, reg_offset);
4102 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4103 REG_WR(bp, reg_offset, val);
4104
4105 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 4106 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 4107 bnx2x_panic();
4108 }
877e9aa4
ET		 4109}
4110
1191cb83 4111static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4112{
4113 u32 val;
4114
4115 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4116
4117 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4118 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4119 /* CFC error attention */
4120 if (val & 0x2)
4121 BNX2X_ERR("FATAL error from CFC\n");
4122 }
4123
4124 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 4125 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 4126 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 4127 /* RQ_USDMDP_FIFO_OVERFLOW */
4128 if (val & 0x18000)
4129 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 4130
4131 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4132 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4133 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4134 }
877e9aa4 4135 }
34f80b04
EG		 4136
4137 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4138
4139 int port = BP_PORT(bp);
4140 int reg_offset;
4141
4142 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4143 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4144
4145 val = REG_RD(bp, reg_offset);
4146 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4147 REG_WR(bp, reg_offset, val);
4148
4149 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 4150 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 4151 bnx2x_panic();
4152 }
877e9aa4
ET		 4153}
4154
1191cb83 4155static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
877e9aa4 4156{
34f80b04
EG		 4157 u32 val;
4158
877e9aa4
ET		 4159 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4160
34f80b04
EG		 4161 if (attn & BNX2X_PMF_LINK_ASSERT) {
4162 int func = BP_FUNC(bp);
4163
4164 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
a3348722 4165 bnx2x_read_mf_cfg(bp);
f2e0899f
DK		 4166 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4167 func_mf_config[BP_ABS_FUNC(bp)].config);
4168 val = SHMEM_RD(bp,
4169 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 4170 if (val & DRV_STATUS_DCC_EVENT_MASK)
4171 bnx2x_dcc_event(bp,
4172 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 4173
4174 if (val & DRV_STATUS_SET_MF_BW)
4175 bnx2x_set_mf_bw(bp);
4176
1d187b34
BW		 4177 if (val & DRV_STATUS_DRV_INFO_REQ)
4178 bnx2x_handle_drv_info_req(bp);
d16132ce
AE		 4179
4180 if (val & DRV_STATUS_VF_DISABLED)
370d4a26
YM		 4181 bnx2x_schedule_iov_task(bp,
4182 BNX2X_IOV_HANDLE_FLR);
d16132ce 4183
2691d51d 4184 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 4185 bnx2x_pmf_update(bp);
4186
e4901dde 4187 if (bp->port.pmf &&
785b9b1a
SR		 4188 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4189 bp->dcbx_enabled > 0)
e4901dde
VZ		 4190 /* start dcbx state machine */
4191 bnx2x_dcbx_set_params(bp,
4192 BNX2X_DCBX_STATE_NEG_RECEIVED);
a3348722
BW		 4193 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4194 bnx2x_handle_afex_cmd(bp,
4195 val & DRV_STATUS_AFEX_EVENT_MASK);
c8c60d88
YM		 4196 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4197 bnx2x_handle_eee_event(bp);
3deb8167
YR		 4198 if (bp->link_vars.periodic_flags &
4199 PERIODIC_FLAGS_LINK_EVENT) {
4200 /* sync with link */
4201 bnx2x_acquire_phy_lock(bp);
4202 bp->link_vars.periodic_flags &=
4203 ~PERIODIC_FLAGS_LINK_EVENT;
4204 bnx2x_release_phy_lock(bp);
4205 if (IS_MF(bp))
4206 bnx2x_link_sync_notify(bp);
4207 bnx2x_link_report(bp);
4208 }
4209 /* Always call it here: bnx2x_link_report() will
4210 * prevent the link indication duplication.
4211 */
4212 bnx2x__link_status_update(bp);
34f80b04 4213 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 4214
4215 BNX2X_ERR("MC assert!\n");
d6cae238 4216 bnx2x_mc_assert(bp);
877e9aa4
ET		 4217 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4218 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4219 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4220 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4221 bnx2x_panic();
4222
4223 } else if (attn & BNX2X_MCP_ASSERT) {
4224
4225 BNX2X_ERR("MCP assert!\n");
4226 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 4227 bnx2x_fw_dump(bp);
877e9aa4
ET		 4228
4229 } else
4230 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4231 }
4232
4233 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 4234 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4235 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 4236 val = CHIP_IS_E1(bp) ? 0 :
4237 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 4238 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4239 }
4240 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 4241 val = CHIP_IS_E1(bp) ? 0 :
4242 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 4243 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4244 }
877e9aa4 4245 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 4246 }
4247}
4248
c9ee9206
VZ		 4249/*
4250 * Bits map:
4251 * 0-7 - Engine0 load counter.
4252 * 8-15 - Engine1 load counter.
4253 * 16 - Engine0 RESET_IN_PROGRESS bit.
4254 * 17 - Engine1 RESET_IN_PROGRESS bit.
4255 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4256 * on the engine
4257 * 19 - Engine1 ONE_IS_LOADED.
4258 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4259 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4260 * just the one belonging to its engine).
4261 *
4262 */
4263#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4264
4265#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4266#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4267#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4268#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4269#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4270#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4271#define BNX2X_GLOBAL_RESET_BIT 0x00040000
4272
4273/*
4274 * Set the GLOBAL_RESET bit.
4275 *
4276 * Should be run under rtnl lock
4277 */
4278void bnx2x_set_reset_global(struct bnx2x *bp)
4279{
f16da43b
AE		 4280 u32 val;
4281 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4282 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4283 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
f16da43b 4284 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206
VZ		 4285}
4286
4287/*
4288 * Clear the GLOBAL_RESET bit.
4289 *
4290 * Should be run under rtnl lock
4291 */
1191cb83 4292static void bnx2x_clear_reset_global(struct bnx2x *bp)
c9ee9206 4293{
f16da43b
AE		 4294 u32 val;
4295 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4296 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4297 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
f16da43b 4298 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206 4299}
f85582f8 4300
72fd0718 4301/*
c9ee9206
VZ		 4302 * Checks the GLOBAL_RESET bit.
4303 *
72fd0718
VZ		 4304 * should be run under rtnl lock
4305 */
1191cb83 4306static bool bnx2x_reset_is_global(struct bnx2x *bp)
c9ee9206 4307{
3cdeec22 4308 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4309
4310 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4311 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4312}
4313
4314/*
4315 * Clear RESET_IN_PROGRESS bit for the current engine.
4316 *
4317 * Should be run under rtnl lock
4318 */
1191cb83 4319static void bnx2x_set_reset_done(struct bnx2x *bp)
72fd0718 4320{
f16da43b 4321 u32 val;
c9ee9206
VZ		 4322 u32 bit = BP_PATH(bp) ?
4323 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4324 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4325 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4326
4327 /* Clear the bit */
4328 val &= ~bit;
4329 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4330
4331 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4332}
4333
4334/*
c9ee9206
VZ		 4335 * Set RESET_IN_PROGRESS for the current engine.
4336 *
72fd0718
VZ		 4337 * should be run under rtnl lock
4338 */
c9ee9206 4339void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 4340{
f16da43b 4341 u32 val;
c9ee9206
VZ		 4342 u32 bit = BP_PATH(bp) ?
4343 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4344 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4345 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4346
4347 /* Set the bit */
4348 val |= bit;
4349 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4350 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4351}
4352
4353/*
c9ee9206 4354 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 4355 * should be run under rtnl lock
4356 */
c9ee9206 4357bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 4358{
3cdeec22 4359 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4360 u32 bit = engine ?
4361 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4362
4363 /* return false if bit is set */
4364 return (val & bit) ? false : true;
72fd0718
VZ		 4365}
4366
4367/*
889b9af3 4368 * set pf load for the current pf.
c9ee9206 4369 *
72fd0718
VZ		 4370 * should be run under rtnl lock
4371 */
889b9af3 4372void bnx2x_set_pf_load(struct bnx2x *bp)
72fd0718 4373{
f16da43b 4374 u32 val1, val;
c9ee9206
VZ		 4375 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4376 BNX2X_PATH0_LOAD_CNT_MASK;
4377 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4378 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4379
f16da43b
AE		 4380 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4381 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4382
51c1a580 4383 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4384
c9ee9206
VZ		 4385 /* get the current counter value */
4386 val1 = (val & mask) >> shift;
4387
889b9af3
AE		 4388 /* set bit of that PF */
4389 val1 |= (1 << bp->pf_num);
c9ee9206
VZ		 4390
4391 /* clear the old value */
4392 val &= ~mask;
4393
4394 /* set the new one */
4395 val |= ((val1 << shift) & mask);
4396
4397 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4398 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4399}
4400
c9ee9206 4401/**
889b9af3 4402 * bnx2x_clear_pf_load - clear pf load mark
c9ee9206
VZ		 4403 *
4404 * @bp: driver handle
4405 *
4406 * Should be run under rtnl lock.
4407 * Decrements the load counter for the current engine. Returns
889b9af3 4408 * whether other functions are still loaded
72fd0718 4409 */
889b9af3 4410bool bnx2x_clear_pf_load(struct bnx2x *bp)
72fd0718 4411{
f16da43b 4412 u32 val1, val;
c9ee9206
VZ		 4413 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4414 BNX2X_PATH0_LOAD_CNT_MASK;
4415 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4416 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4417
f16da43b
AE		 4418 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4419 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
51c1a580 4420 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4421
c9ee9206
VZ		 4422 /* get the current counter value */
4423 val1 = (val & mask) >> shift;
4424
889b9af3
AE		 4425 /* clear bit of that PF */
4426 val1 &= ~(1 << bp->pf_num);
c9ee9206
VZ		 4427
4428 /* clear the old value */
4429 val &= ~mask;
4430
4431 /* set the new one */
4432 val |= ((val1 << shift) & mask);
4433
4434 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4435 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4436 return val1 != 0;
72fd0718
VZ		 4437}
4438
4439/*
889b9af3 4440 * Read the load status for the current engine.
c9ee9206 4441 *
72fd0718
VZ		 4442 * should be run under rtnl lock
4443 */
1191cb83 4444static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
72fd0718 4445{
c9ee9206
VZ		 4446 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4447 BNX2X_PATH0_LOAD_CNT_MASK);
4448 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4449 BNX2X_PATH0_LOAD_CNT_SHIFT);
4450 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4451
51c1a580 4452 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
c9ee9206
VZ		 4453
4454 val = (val & mask) >> shift;
4455
51c1a580
MS		 4456 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4457 engine, val);
c9ee9206 4458
889b9af3 4459 return val != 0;
72fd0718
VZ		 4460}
4461
6bf07b8e
YM		 4462static void _print_parity(struct bnx2x *bp, u32 reg)
4463{
4464 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4465}
4466
1191cb83 4467static void _print_next_block(int idx, const char *blk)
72fd0718 4468{
f1deab50 4469 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 4470}
4471
4293b9f5
DK		 4472static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4473 int *par_num, bool print)
72fd0718 4474{
4293b9f5
DK		 4475 u32 cur_bit;
4476 bool res;
4477 int i;
4478
4479 res = false;
4480
72fd0718 4481 for (i = 0; sig; i++) {
4293b9f5 4482 cur_bit = (0x1UL << i);
72fd0718 4483 if (sig & cur_bit) {
4293b9f5
DK		 4484 res |= true; /* Each bit is real error! */
4485
4486 if (print) {
4487 switch (cur_bit) {
4488 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4489 _print_next_block((*par_num)++, "BRB");
6bf07b8e
YM		 4490 _print_parity(bp,
4491 BRB1_REG_BRB1_PRTY_STS);
4293b9f5
DK		 4492 break;
4493 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4494 _print_next_block((*par_num)++,
4495 "PARSER");
6bf07b8e 4496 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4293b9f5
DK		 4497 break;
4498 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4499 _print_next_block((*par_num)++, "TSDM");
6bf07b8e
YM		 4500 _print_parity(bp,
4501 TSDM_REG_TSDM_PRTY_STS);
4293b9f5
DK		 4502 break;
4503 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4504 _print_next_block((*par_num)++,
c9ee9206 4505 "SEARCHER");
6bf07b8e 4506 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4293b9f5
DK		 4507 break;
4508 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4509 _print_next_block((*par_num)++, "TCM");
4510 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4511 break;
4512 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4513 _print_next_block((*par_num)++,
4514 "TSEMI");
6bf07b8e
YM		 4515 _print_parity(bp,
4516 TSEM_REG_TSEM_PRTY_STS_0);
4517 _print_parity(bp,
4518 TSEM_REG_TSEM_PRTY_STS_1);
4293b9f5
DK		 4519 break;
4520 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4521 _print_next_block((*par_num)++, "XPB");
6bf07b8e
YM		 4522 _print_parity(bp, GRCBASE_XPB +
4523 PB_REG_PB_PRTY_STS);
4293b9f5 4524 break;
6bf07b8e 4525 }
72fd0718
VZ		 4526 }
4527
4528 /* Clear the bit */
4529 sig &= ~cur_bit;
4530 }
4531 }
4532
4293b9f5 4533 return res;
72fd0718
VZ		 4534}
4535
4293b9f5
DK		 4536static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4537 int *par_num, bool *global,
6bf07b8e 4538 bool print)
72fd0718 4539{
4293b9f5
DK		 4540 u32 cur_bit;
4541 bool res;
4542 int i;
4543
4544 res = false;
4545
72fd0718 4546 for (i = 0; sig; i++) {
4293b9f5 4547 cur_bit = (0x1UL << i);
72fd0718 4548 if (sig & cur_bit) {
4293b9f5 4549 res |= true; /* Each bit is real error! */
72fd0718 4550 switch (cur_bit) {
c9ee9206 4551 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
6bf07b8e 4552 if (print) {
4293b9f5 4553 _print_next_block((*par_num)++, "PBF");
6bf07b8e
YM		 4554 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4555 }
72fd0718
VZ		 4556 break;
4557 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
6bf07b8e 4558 if (print) {
4293b9f5 4559 _print_next_block((*par_num)++, "QM");
6bf07b8e
YM		 4560 _print_parity(bp, QM_REG_QM_PRTY_STS);
4561 }
c9ee9206
VZ		 4562 break;
4563 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
6bf07b8e 4564 if (print) {
4293b9f5 4565 _print_next_block((*par_num)++, "TM");
6bf07b8e
YM		 4566 _print_parity(bp, TM_REG_TM_PRTY_STS);
4567 }
72fd0718
VZ		 4568 break;
4569 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
6bf07b8e 4570 if (print) {
4293b9f5 4571 _print_next_block((*par_num)++, "XSDM");
6bf07b8e
YM		 4572 _print_parity(bp,
4573 XSDM_REG_XSDM_PRTY_STS);
4574 }
c9ee9206
VZ		 4575 break;
4576 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
6bf07b8e 4577 if (print) {
4293b9f5 4578 _print_next_block((*par_num)++, "XCM");
6bf07b8e
YM		 4579 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4580 }
72fd0718
VZ		 4581 break;
4582 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
6bf07b8e 4583 if (print) {
4293b9f5
DK		 4584 _print_next_block((*par_num)++,
4585 "XSEMI");
6bf07b8e
YM		 4586 _print_parity(bp,
4587 XSEM_REG_XSEM_PRTY_STS_0);
4588 _print_parity(bp,
4589 XSEM_REG_XSEM_PRTY_STS_1);
4590 }
72fd0718
VZ		 4591 break;
4592 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
6bf07b8e 4593 if (print) {
4293b9f5 4594 _print_next_block((*par_num)++,
c9ee9206 4595 "DOORBELLQ");
6bf07b8e
YM		 4596 _print_parity(bp,
4597 DORQ_REG_DORQ_PRTY_STS);
4598 }
c9ee9206
VZ		 4599 break;
4600 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
6bf07b8e 4601 if (print) {
4293b9f5 4602 _print_next_block((*par_num)++, "NIG");
6bf07b8e
YM		 4603 if (CHIP_IS_E1x(bp)) {
4604 _print_parity(bp,
4605 NIG_REG_NIG_PRTY_STS);
4606 } else {
4607 _print_parity(bp,
4608 NIG_REG_NIG_PRTY_STS_0);
4609 _print_parity(bp,
4610 NIG_REG_NIG_PRTY_STS_1);
4611 }
4612 }
72fd0718
VZ		 4613 break;
4614 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206 4615 if (print)
4293b9f5 4616 _print_next_block((*par_num)++,
c9ee9206
VZ		 4617 "VAUX PCI CORE");
4618 *global = true;
72fd0718
VZ		 4619 break;
4620 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
6bf07b8e 4621 if (print) {
4293b9f5
DK		 4622 _print_next_block((*par_num)++,
4623 "DEBUG");
6bf07b8e
YM		 4624 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4625 }
72fd0718
VZ		 4626 break;
4627 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
6bf07b8e 4628 if (print) {
4293b9f5 4629 _print_next_block((*par_num)++, "USDM");
6bf07b8e
YM		 4630 _print_parity(bp,
4631 USDM_REG_USDM_PRTY_STS);
4632 }
72fd0718 4633 break;
8736c826 4634 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
6bf07b8e 4635 if (print) {
4293b9f5 4636 _print_next_block((*par_num)++, "UCM");
6bf07b8e
YM		 4637 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4638 }
8736c826 4639 break;
72fd0718 4640 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
6bf07b8e 4641 if (print) {
4293b9f5
DK		 4642 _print_next_block((*par_num)++,
4643 "USEMI");
6bf07b8e
YM		 4644 _print_parity(bp,
4645 USEM_REG_USEM_PRTY_STS_0);
4646 _print_parity(bp,
4647 USEM_REG_USEM_PRTY_STS_1);
4648 }
72fd0718
VZ		 4649 break;
4650 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
6bf07b8e 4651 if (print) {
4293b9f5 4652 _print_next_block((*par_num)++, "UPB");
6bf07b8e
YM		 4653 _print_parity(bp, GRCBASE_UPB +
4654 PB_REG_PB_PRTY_STS);
4655 }
72fd0718
VZ		 4656 break;
4657 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
6bf07b8e 4658 if (print) {
4293b9f5 4659 _print_next_block((*par_num)++, "CSDM");
6bf07b8e
YM		 4660 _print_parity(bp,
4661 CSDM_REG_CSDM_PRTY_STS);
4662 }
72fd0718 4663 break;
8736c826 4664 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
6bf07b8e 4665 if (print) {
4293b9f5 4666 _print_next_block((*par_num)++, "CCM");
6bf07b8e
YM		 4667 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4668 }
8736c826 4669 break;
72fd0718
VZ		 4670 }
4671
4672 /* Clear the bit */
4673 sig &= ~cur_bit;
4674 }
4675 }
4676
4293b9f5 4677 return res;
72fd0718
VZ		 4678}
4679
4293b9f5
DK		 4680static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4681 int *par_num, bool print)
72fd0718 4682{
4293b9f5
DK		 4683 u32 cur_bit;
4684 bool res;
4685 int i;
4686
4687 res = false;
4688
72fd0718 4689 for (i = 0; sig; i++) {
4293b9f5 4690 cur_bit = (0x1UL << i);
72fd0718 4691 if (sig & cur_bit) {
0c23ad37 4692 res = true; /* Each bit is real error! */
4293b9f5
DK		 4693 if (print) {
4694 switch (cur_bit) {
4695 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4696 _print_next_block((*par_num)++,
4697 "CSEMI");
6bf07b8e
YM		 4698 _print_parity(bp,
4699 CSEM_REG_CSEM_PRTY_STS_0);
4700 _print_parity(bp,
4701 CSEM_REG_CSEM_PRTY_STS_1);
4293b9f5
DK		 4702 break;
4703 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4704 _print_next_block((*par_num)++, "PXP");
6bf07b8e
YM		 4705 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4706 _print_parity(bp,
4707 PXP2_REG_PXP2_PRTY_STS_0);
4708 _print_parity(bp,
4709 PXP2_REG_PXP2_PRTY_STS_1);
4293b9f5
DK		 4710 break;
4711 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4712 _print_next_block((*par_num)++,
4713 "PXPPCICLOCKCLIENT");
4714 break;
4715 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4716 _print_next_block((*par_num)++, "CFC");
6bf07b8e
YM		 4717 _print_parity(bp,
4718 CFC_REG_CFC_PRTY_STS);
4293b9f5
DK		 4719 break;
4720 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4721 _print_next_block((*par_num)++, "CDU");
6bf07b8e 4722 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4293b9f5
DK		 4723 break;
4724 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4725 _print_next_block((*par_num)++, "DMAE");
6bf07b8e
YM		 4726 _print_parity(bp,
4727 DMAE_REG_DMAE_PRTY_STS);
4293b9f5
DK		 4728 break;
4729 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4730 _print_next_block((*par_num)++, "IGU");
6bf07b8e
YM		 4731 if (CHIP_IS_E1x(bp))
4732 _print_parity(bp,
4733 HC_REG_HC_PRTY_STS);
4734 else
4735 _print_parity(bp,
4736 IGU_REG_IGU_PRTY_STS);
4293b9f5
DK		 4737 break;
4738 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4739 _print_next_block((*par_num)++, "MISC");
6bf07b8e
YM		 4740 _print_parity(bp,
4741 MISC_REG_MISC_PRTY_STS);
4293b9f5 4742 break;
6bf07b8e 4743 }
72fd0718
VZ		 4744 }
4745
4746 /* Clear the bit */
4747 sig &= ~cur_bit;
4748 }
4749 }
4750
4293b9f5 4751 return res;
72fd0718
VZ		 4752}
4753
4293b9f5
DK		 4754static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4755 int *par_num, bool *global,
4756 bool print)
72fd0718 4757{
4293b9f5
DK		 4758 bool res = false;
4759 u32 cur_bit;
4760 int i;
4761
72fd0718 4762 for (i = 0; sig; i++) {
4293b9f5 4763 cur_bit = (0x1UL << i);
72fd0718
VZ		 4764 if (sig & cur_bit) {
4765 switch (cur_bit) {
4766 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206 4767 if (print)
4293b9f5
DK		 4768 _print_next_block((*par_num)++,
4769 "MCP ROM");
c9ee9206 4770 *global = true;
0c23ad37 4771 res = true;
72fd0718
VZ		 4772 break;
4773 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206 4774 if (print)
4293b9f5 4775 _print_next_block((*par_num)++,
c9ee9206
VZ		 4776 "MCP UMP RX");
4777 *global = true;
0c23ad37 4778 res = true;
72fd0718
VZ		 4779 break;
4780 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206 4781 if (print)
4293b9f5 4782 _print_next_block((*par_num)++,
c9ee9206
VZ		 4783 "MCP UMP TX");
4784 *global = true;
0c23ad37 4785 res = true;
72fd0718
VZ		 4786 break;
4787 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206 4788 if (print)
4293b9f5 4789 _print_next_block((*par_num)++,
c9ee9206 4790 "MCP SCPAD");
4293b9f5
DK		 4791 /* clear latched SCPAD PATIRY from MCP */
4792 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4793 1UL << 10);
72fd0718
VZ		 4794 break;
4795 }
4796
4797 /* Clear the bit */
4798 sig &= ~cur_bit;
4799 }
4800 }
4801
4293b9f5 4802 return res;
72fd0718
VZ		 4803}
4804
4293b9f5
DK		 4805static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4806 int *par_num, bool print)
8736c826 4807{
4293b9f5
DK		 4808 u32 cur_bit;
4809 bool res;
4810 int i;
4811
4812 res = false;
4813
8736c826 4814 for (i = 0; sig; i++) {
4293b9f5 4815 cur_bit = (0x1UL << i);
8736c826 4816 if (sig & cur_bit) {
0c23ad37 4817 res = true; /* Each bit is real error! */
4293b9f5
DK		 4818 if (print) {
4819 switch (cur_bit) {
4820 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4821 _print_next_block((*par_num)++,
4822 "PGLUE_B");
6bf07b8e 4823 _print_parity(bp,
4293b9f5
DK		 4824 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4825 break;
4826 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4827 _print_next_block((*par_num)++, "ATC");
6bf07b8e
YM		 4828 _print_parity(bp,
4829 ATC_REG_ATC_PRTY_STS);
4293b9f5 4830 break;
6bf07b8e 4831 }
8736c826 4832 }
8736c826
VZ		 4833 /* Clear the bit */
4834 sig &= ~cur_bit;
4835 }
4836 }
4837
4293b9f5 4838 return res;
8736c826
VZ		 4839}
4840
1191cb83
ED		 4841static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4842 u32 *sig)
72fd0718 4843{
4293b9f5
DK		 4844 bool res = false;
4845
8736c826
VZ		 4846 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4847 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4848 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4849 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4850 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718 4851 int par_num = 0;
51c1a580
MS		 4852 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4853 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
8736c826
VZ		 4854 sig[0] & HW_PRTY_ASSERT_SET_0,
4855 sig[1] & HW_PRTY_ASSERT_SET_1,
4856 sig[2] & HW_PRTY_ASSERT_SET_2,
4857 sig[3] & HW_PRTY_ASSERT_SET_3,
4858 sig[4] & HW_PRTY_ASSERT_SET_4);
c9ee9206
VZ		 4859 if (print)
4860 netdev_err(bp->dev,
4861 "Parity errors detected in blocks: ");
4293b9f5
DK		 4862 res |= bnx2x_check_blocks_with_parity0(bp,
4863 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4864 res |= bnx2x_check_blocks_with_parity1(bp,
4865 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4866 res |= bnx2x_check_blocks_with_parity2(bp,
4867 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4868 res |= bnx2x_check_blocks_with_parity3(bp,
4869 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4870 res |= bnx2x_check_blocks_with_parity4(bp,
4871 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
8736c826 4872
c9ee9206
VZ		 4873 if (print)
4874 pr_cont("\n");
4293b9f5 4875 }
8736c826 4876
4293b9f5 4877 return res;
72fd0718
VZ		 4878}
4879
c9ee9206
VZ		 4880/**
4881 * bnx2x_chk_parity_attn - checks for parity attentions.
4882 *
4883 * @bp: driver handle
4884 * @global: true if there was a global attention
4885 * @print: show parity attention in syslog
4886 */
4887bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 4888{
8736c826 4889 struct attn_route attn = { {0} };
72fd0718
VZ		 4890 int port = BP_PORT(bp);
4891
4892 attn.sig[0] = REG_RD(bp,
4893 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4894 port*4);
4895 attn.sig[1] = REG_RD(bp,
4896 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4897 port*4);
4898 attn.sig[2] = REG_RD(bp,
4899 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4900 port*4);
4901 attn.sig[3] = REG_RD(bp,
4902 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4903 port*4);
0a5ccb75
YM		 4904 /* Since MCP attentions can't be disabled inside the block, we need to
4905 * read AEU registers to see whether they're currently disabled
4906 */
4907 attn.sig[3] &= ((REG_RD(bp,
4908 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4909 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4910 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4911 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
72fd0718 4912
8736c826
VZ		 4913 if (!CHIP_IS_E1x(bp))
4914 attn.sig[4] = REG_RD(bp,
4915 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4916 port*4);
4917
4918 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 4919}
4920
1191cb83 4921static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
f2e0899f
DK		 4922{
4923 u32 val;
4924 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4925
4926 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4927 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4928 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
51c1a580 4929 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
f2e0899f 4930 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
51c1a580 4931 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
f2e0899f 4932 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
51c1a580 4933 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
f2e0899f 4934 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
51c1a580 4935 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
f2e0899f
DK		 4936 if (val &
4937 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
51c1a580 4938 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
f2e0899f
DK		 4939 if (val &
4940 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
51c1a580 4941 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
f2e0899f 4942 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
51c1a580 4943 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
f2e0899f 4944 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
51c1a580 4945 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
f2e0899f 4946 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
51c1a580 4947 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
f2e0899f
DK		 4948 }
4949 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4950 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4951 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4952 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4953 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4954 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
51c1a580 4955 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
f2e0899f 4956 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
51c1a580 4957 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
f2e0899f 4958 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
51c1a580 4959 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
f2e0899f
DK		 4960 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4961 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4962 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
51c1a580 4963 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
f2e0899f
DK		 4964 }
4965
4966 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4967 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4968 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4969 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4970 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4971 }
f2e0899f
DK		 4972}
4973
72fd0718
VZ		 4974static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4975{
4976 struct attn_route attn, *group_mask;
34f80b04 4977 int port = BP_PORT(bp);
877e9aa4 4978 int index;
a2fbb9ea
ET		 4979 u32 reg_addr;
4980 u32 val;
3fcaf2e5 4981 u32 aeu_mask;
c9ee9206 4982 bool global = false;
a2fbb9ea
ET		 4983
4984 /* need to take HW lock because MCP or other port might also
4985 try to handle this event */
4a37fb66 4986 bnx2x_acquire_alr(bp);
a2fbb9ea 4987
c9ee9206
VZ		 4988 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4989#ifndef BNX2X_STOP_ON_ERROR
72fd0718 4990 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 4991 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 4992 /* Disable HW interrupts */
4993 bnx2x_int_disable(bp);
72fd0718
VZ		 4994 /* In case of parity errors don't handle attentions so that
4995 * other function would "see" parity errors.
4996 */
c9ee9206
VZ		 4997#else
4998 bnx2x_panic();
4999#endif
5000 bnx2x_release_alr(bp);
72fd0718
VZ		 5001 return;
5002 }
5003
a2fbb9ea
ET		 5004 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5005 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5006 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5007 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 5008 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5009 attn.sig[4] =
5010 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5011 else
5012 attn.sig[4] = 0;
5013
5014 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5015 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 5016
5017 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5018 if (deasserted & (1 << index)) {
72fd0718 5019 group_mask = &bp->attn_group[index];
a2fbb9ea 5020
51c1a580 5021 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
f2e0899f
DK		 5022 index,
5023 group_mask->sig[0], group_mask->sig[1],
5024 group_mask->sig[2], group_mask->sig[3],
5025 group_mask->sig[4]);
a2fbb9ea 5026
f2e0899f
DK		 5027 bnx2x_attn_int_deasserted4(bp,
5028 attn.sig[4] & group_mask->sig[4]);
877e9aa4 5029 bnx2x_attn_int_deasserted3(bp,
72fd0718 5030 attn.sig[3] & group_mask->sig[3]);
877e9aa4 5031 bnx2x_attn_int_deasserted1(bp,
72fd0718 5032 attn.sig[1] & group_mask->sig[1]);
877e9aa4 5033 bnx2x_attn_int_deasserted2(bp,
72fd0718 5034 attn.sig[2] & group_mask->sig[2]);
877e9aa4 5035 bnx2x_attn_int_deasserted0(bp,
72fd0718 5036 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 5037 }
5038 }
5039
4a37fb66 5040 bnx2x_release_alr(bp);
a2fbb9ea 5041
f2e0899f
DK		 5042 if (bp->common.int_block == INT_BLOCK_HC)
5043 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5044 COMMAND_REG_ATTN_BITS_CLR);
5045 else
5046 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 5047
5048 val = ~deasserted;
f2e0899f
DK		 5049 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5050 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 5051 REG_WR(bp, reg_addr, val);
a2fbb9ea 5052
a2fbb9ea 5053 if (~bp->attn_state & deasserted)
3fcaf2e5 5054 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 5055
5056 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5057 MISC_REG_AEU_MASK_ATTN_FUNC_0;
5058
3fcaf2e5
EG		 5059 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5060 aeu_mask = REG_RD(bp, reg_addr);
5061
5062 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
5063 aeu_mask, deasserted);
72fd0718 5064 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 5065 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 5066
3fcaf2e5
EG		 5067 REG_WR(bp, reg_addr, aeu_mask);
5068 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 5069
5070 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5071 bp->attn_state &= ~deasserted;
5072 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5073}
5074
5075static void bnx2x_attn_int(struct bnx2x *bp)
5076{
5077 /* read local copy of bits */
68d59484
EG		 5078 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5079 attn_bits);
5080 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5081 attn_bits_ack);
a2fbb9ea
ET		 5082 u32 attn_state = bp->attn_state;
5083
5084 /* look for changed bits */
5085 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
5086 u32 deasserted = ~attn_bits & attn_ack & attn_state;
5087
5088 DP(NETIF_MSG_HW,
5089 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5090 attn_bits, attn_ack, asserted, deasserted);
5091
5092 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 5093 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 5094
5095 /* handle bits that were raised */
5096 if (asserted)
5097 bnx2x_attn_int_asserted(bp, asserted);
5098
5099 if (deasserted)
5100 bnx2x_attn_int_deasserted(bp, deasserted);
5101}
5102
619c5cb6
VZ		 5103void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5104 u16 index, u8 op, u8 update)
5105{
dc1ba591
AE		 5106 u32 igu_addr = bp->igu_base_addr;
5107 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
619c5cb6
VZ		 5108 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5109 igu_addr);
5110}
5111
1191cb83 5112static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
523224a3
DK		 5113{
5114 /* No memory barriers */
5115 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5116 mmiowb(); /* keep prod updates ordered */
5117}
5118
523224a3
DK		 5119static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5120 union event_ring_elem *elem)
5121{
619c5cb6
VZ		 5122 u8 err = elem->message.error;
5123
523224a3 5124 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 5125 (cid < bp->cnic_eth_dev.starting_cid &&
5126 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 5127 return 1;
5128
5129 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5130
619c5cb6
VZ		 5131 if (unlikely(err)) {
5132
523224a3
DK		 5133 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5134 cid);
823e1d90 5135 bnx2x_panic_dump(bp, false);
523224a3 5136 }
619c5cb6 5137 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 5138 return 0;
5139}
523224a3 5140
1191cb83 5141static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5142{
5143 struct bnx2x_mcast_ramrod_params rparam;
5144 int rc;
5145
5146 memset(&rparam, 0, sizeof(rparam));
5147
5148 rparam.mcast_obj = &bp->mcast_obj;
5149
5150 netif_addr_lock_bh(bp->dev);
5151
5152 /* Clear pending state for the last command */
5153 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5154
5155 /* If there are pending mcast commands - send them */
5156 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5157 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5158 if (rc < 0)
5159 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5160 rc);
5161 }
5162
5163 netif_addr_unlock_bh(bp->dev);
5164}
5165
1191cb83
ED		 5166static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5167 union event_ring_elem *elem)
619c5cb6
VZ		 5168{
5169 unsigned long ramrod_flags = 0;
5170 int rc = 0;
5171 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5172 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5173
5174 /* Always push next commands out, don't wait here */
5175 __set_bit(RAMROD_CONT, &ramrod_flags);
5176
86564c3f
YM		 5177 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5178 >> BNX2X_SWCID_SHIFT) {
619c5cb6 5179 case BNX2X_FILTER_MAC_PENDING:
51c1a580 5180 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
55c11941 5181 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
619c5cb6
VZ		 5182 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5183 else
15192a8c 5184 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
619c5cb6
VZ		 5185
5186 break;
619c5cb6 5187 case BNX2X_FILTER_MCAST_PENDING:
51c1a580 5188 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
619c5cb6
VZ		 5189 /* This is only relevant for 57710 where multicast MACs are
5190 * configured as unicast MACs using the same ramrod.
5191 */
5192 bnx2x_handle_mcast_eqe(bp);
5193 return;
5194 default:
5195 BNX2X_ERR("Unsupported classification command: %d\n",
5196 elem->message.data.eth_event.echo);
5197 return;
5198 }
5199
5200 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5201
5202 if (rc < 0)
5203 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5204 else if (rc > 0)
5205 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
619c5cb6
VZ		 5206}
5207
619c5cb6 5208static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
619c5cb6 5209
1191cb83 5210static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5211{
5212 netif_addr_lock_bh(bp->dev);
5213
5214 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5215
5216 /* Send rx_mode command again if was requested */
5217 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5218 bnx2x_set_storm_rx_mode(bp);
619c5cb6
VZ		 5219 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5220 &bp->sp_state))
5221 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5222 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5223 &bp->sp_state))
5224 bnx2x_set_iscsi_eth_rx_mode(bp, false);
619c5cb6
VZ		 5225
5226 netif_addr_unlock_bh(bp->dev);
5227}
5228
1191cb83 5229static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
a3348722
BW		 5230 union event_ring_elem *elem)
5231{
5232 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5233 DP(BNX2X_MSG_SP,
5234 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5235 elem->message.data.vif_list_event.func_bit_map);
5236 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5237 elem->message.data.vif_list_event.func_bit_map);
5238 } else if (elem->message.data.vif_list_event.echo ==
5239 VIF_LIST_RULE_SET) {
5240 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5241 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5242 }
5243}
5244
5245/* called with rtnl_lock */
1191cb83 5246static void bnx2x_after_function_update(struct bnx2x *bp)
a3348722
BW		 5247{
5248 int q, rc;
5249 struct bnx2x_fastpath *fp;
5250 struct bnx2x_queue_state_params queue_params = {NULL};
5251 struct bnx2x_queue_update_params *q_update_params =
5252 &queue_params.params.update;
5253
2de67439 5254 /* Send Q update command with afex vlan removal values for all Qs */
a3348722
BW		 5255 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5256
5257 /* set silent vlan removal values according to vlan mode */
5258 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5259 &q_update_params->update_flags);
5260 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5261 &q_update_params->update_flags);
5262 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5263
5264 /* in access mode mark mask and value are 0 to strip all vlans */
5265 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5266 q_update_params->silent_removal_value = 0;
5267 q_update_params->silent_removal_mask = 0;
5268 } else {
5269 q_update_params->silent_removal_value =
5270 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5271 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5272 }
5273
5274 for_each_eth_queue(bp, q) {
5275 /* Set the appropriate Queue object */
5276 fp = &bp->fp[q];
15192a8c 5277 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5278
5279 /* send the ramrod */
5280 rc = bnx2x_queue_state_change(bp, &queue_params);
5281 if (rc < 0)
5282 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5283 q);
5284 }
5285
fea75645 5286 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
65565884 5287 fp = &bp->fp[FCOE_IDX(bp)];
15192a8c 5288 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5289
5290 /* clear pending completion bit */
5291 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5292
5293 /* mark latest Q bit */
4e857c58 5294 smp_mb__before_atomic();
a3348722 5295 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4e857c58 5296 smp_mb__after_atomic();
a3348722
BW		 5297
5298 /* send Q update ramrod for FCoE Q */
5299 rc = bnx2x_queue_state_change(bp, &queue_params);
5300 if (rc < 0)
5301 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5302 q);
5303 } else {
5304 /* If no FCoE ring - ACK MCP now */
5305 bnx2x_link_report(bp);
5306 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5307 }
a3348722
BW		 5308}
5309
1191cb83 5310static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
619c5cb6
VZ		 5311 struct bnx2x *bp, u32 cid)
5312{
94f05b0f 5313 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
55c11941
MS		 5314
5315 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
15192a8c 5316 return &bnx2x_fcoe_sp_obj(bp, q_obj);
619c5cb6 5317 else
15192a8c 5318 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
619c5cb6
VZ		 5319}
5320
523224a3
DK		 5321static void bnx2x_eq_int(struct bnx2x *bp)
5322{
5323 u16 hw_cons, sw_cons, sw_prod;
5324 union event_ring_elem *elem;
55c11941 5325 u8 echo;
523224a3
DK		 5326 u32 cid;
5327 u8 opcode;
fd1fc79d 5328 int rc, spqe_cnt = 0;
619c5cb6
VZ		 5329 struct bnx2x_queue_sp_obj *q_obj;
5330 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5331 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 5332
5333 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5334
5335 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
16a5fd92 5336 * when we get the next-page we need to adjust so the loop
523224a3
DK		 5337 * condition below will be met. The next element is the size of a
5338 * regular element and hence incrementing by 1
5339 */
5340 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5341 hw_cons++;
5342
25985edc 5343 /* This function may never run in parallel with itself for a
523224a3
DK		 5344 * specific bp, thus there is no need in "paired" read memory
5345 * barrier here.
5346 */
5347 sw_cons = bp->eq_cons;
5348 sw_prod = bp->eq_prod;
5349
d6cae238 5350 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 5351 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 5352
5353 for (; sw_cons != hw_cons;
5354 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5355
523224a3
DK		 5356 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5357
fd1fc79d
AE		 5358 rc = bnx2x_iov_eq_sp_event(bp, elem);
5359 if (!rc) {
5360 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5361 rc);
5362 goto next_spqe;
5363 }
523224a3 5364
86564c3f
YM		 5365 /* elem CID originates from FW; actually LE */
5366 cid = SW_CID((__force __le32)
5367 elem->message.data.cfc_del_event.cid);
5368 opcode = elem->message.opcode;
523224a3
DK		 5369
5370 /* handle eq element */
5371 switch (opcode) {
fd1fc79d 5372 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
370d4a26
YM		 5373 bnx2x_vf_mbx_schedule(bp,
5374 &elem->message.data.vf_pf_event);
fd1fc79d
AE		 5375 continue;
5376
523224a3 5377 case EVENT_RING_OPCODE_STAT_QUERY:
76ca70fa
YM		 5378 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5379 "got statistics comp event %d\n",
5380 bp->stats_comp++);
523224a3 5381 /* nothing to do with stats comp */
d6cae238 5382 goto next_spqe;
523224a3
DK		 5383
5384 case EVENT_RING_OPCODE_CFC_DEL:
5385 /* handle according to cid range */
5386 /*
5387 * we may want to verify here that the bp state is
5388 * HALTING
5389 */
d6cae238 5390 DP(BNX2X_MSG_SP,
523224a3 5391 "got delete ramrod for MULTI[%d]\n", cid);
55c11941
MS		 5392
5393 if (CNIC_LOADED(bp) &&
5394 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
523224a3 5395 goto next_spqe;
55c11941 5396
619c5cb6
VZ		 5397 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5398
5399 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5400 break;
5401
523224a3 5402 goto next_spqe;
e4901dde
VZ		 5403
5404 case EVENT_RING_OPCODE_STOP_TRAFFIC:
51c1a580 5405 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
6ffa39f2 5406 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
6debea87
DK		 5407 if (f_obj->complete_cmd(bp, f_obj,
5408 BNX2X_F_CMD_TX_STOP))
5409 break;
e4901dde 5410 goto next_spqe;
619c5cb6 5411
e4901dde 5412 case EVENT_RING_OPCODE_START_TRAFFIC:
51c1a580 5413 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
6ffa39f2 5414 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
6debea87
DK		 5415 if (f_obj->complete_cmd(bp, f_obj,
5416 BNX2X_F_CMD_TX_START))
5417 break;
e4901dde 5418 goto next_spqe;
55c11941 5419
a3348722 5420 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
55c11941
MS		 5421 echo = elem->message.data.function_update_event.echo;
5422 if (echo == SWITCH_UPDATE) {
5423 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5424 "got FUNC_SWITCH_UPDATE ramrod\n");
5425 if (f_obj->complete_cmd(
5426 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5427 break;
a3348722 5428
55c11941 5429 } else {
230bb0f3
YM		 5430 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5431
55c11941
MS		 5432 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5433 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5434 f_obj->complete_cmd(bp, f_obj,
5435 BNX2X_F_CMD_AFEX_UPDATE);
5436
5437 /* We will perform the Queues update from
5438 * sp_rtnl task as all Queue SP operations
5439 * should run under rtnl_lock.
5440 */
230bb0f3 5441 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
55c11941 5442 }
a3348722 5443
a3348722
BW		 5444 goto next_spqe;
5445
5446 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5447 f_obj->complete_cmd(bp, f_obj,
5448 BNX2X_F_CMD_AFEX_VIFLISTS);
5449 bnx2x_after_afex_vif_lists(bp, elem);
5450 goto next_spqe;
619c5cb6 5451 case EVENT_RING_OPCODE_FUNCTION_START:
51c1a580
MS		 5452 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5453 "got FUNC_START ramrod\n");
619c5cb6
VZ		 5454 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5455 break;
5456
5457 goto next_spqe;
5458
5459 case EVENT_RING_OPCODE_FUNCTION_STOP:
51c1a580
MS		 5460 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5461 "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 5462 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5463 break;
5464
5465 goto next_spqe;
eeed018c
MK		 5466
5467 case EVENT_RING_OPCODE_SET_TIMESYNC:
5468 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5469 "got set_timesync ramrod completion\n");
5470 if (f_obj->complete_cmd(bp, f_obj,
5471 BNX2X_F_CMD_SET_TIMESYNC))
5472 break;
5473 goto next_spqe;
523224a3
DK		 5474 }
5475
5476 switch (opcode | bp->state) {
619c5cb6
VZ		 5477 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5478 BNX2X_STATE_OPEN):
5479 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 5480 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 5481 cid = elem->message.data.eth_event.echo &
5482 BNX2X_SWCID_MASK;
d6cae238 5483 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
619c5cb6
VZ		 5484 cid);
5485 rss_raw->clear_pending(rss_raw);
523224a3
DK		 5486 break;
5487
619c5cb6
VZ		 5488 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5489 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5490 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 5491 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 5492 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5493 BNX2X_STATE_OPEN):
5494 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5495 BNX2X_STATE_DIAG):
5496 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5497 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5498 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
619c5cb6 5499 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 5500 break;
5501
619c5cb6
VZ		 5502 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5503 BNX2X_STATE_OPEN):
5504 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5505 BNX2X_STATE_DIAG):
5506 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5507 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5508 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 5509 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 5510 break;
5511
619c5cb6
VZ		 5512 case (EVENT_RING_OPCODE_FILTERS_RULES |
5513 BNX2X_STATE_OPEN):
5514 case (EVENT_RING_OPCODE_FILTERS_RULES |
5515 BNX2X_STATE_DIAG):
5516 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 5517 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5518 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 5519 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 5520 break;
5521 default:
5522 /* unknown event log error and continue */
619c5cb6
VZ		 5523 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5524 elem->message.opcode, bp->state);
523224a3
DK		 5525 }
5526next_spqe:
5527 spqe_cnt++;
5528 } /* for */
5529
4e857c58 5530 smp_mb__before_atomic();
6e30dd4e 5531 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 5532
5533 bp->eq_cons = sw_cons;
5534 bp->eq_prod = sw_prod;
5535 /* Make sure that above mem writes were issued towards the memory */
5536 smp_wmb();
5537
5538 /* update producer */
5539 bnx2x_update_eq_prod(bp, bp->eq_prod);
5540}
5541
a2fbb9ea
ET		 5542static void bnx2x_sp_task(struct work_struct *work)
5543{
1cf167f2 5544 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea 5545
fd1fc79d 5546 DP(BNX2X_MSG_SP, "sp task invoked\n");
a2fbb9ea 5547
16a5fd92 5548 /* make sure the atomic interrupt_occurred has been written */
fd1fc79d
AE		 5549 smp_rmb();
5550 if (atomic_read(&bp->interrupt_occurred)) {
a2fbb9ea 5551
fd1fc79d
AE		 5552 /* what work needs to be performed? */
5553 u16 status = bnx2x_update_dsb_idx(bp);
cdaa7cb8 5554
fd1fc79d
AE		 5555 DP(BNX2X_MSG_SP, "status %x\n", status);
5556 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5557 atomic_set(&bp->interrupt_occurred, 0);
5558
5559 /* HW attentions */
5560 if (status & BNX2X_DEF_SB_ATT_IDX) {
5561 bnx2x_attn_int(bp);
5562 status &= ~BNX2X_DEF_SB_ATT_IDX;
5563 }
5564
5565 /* SP events: STAT_QUERY and others */
5566 if (status & BNX2X_DEF_SB_IDX) {
5567 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 5568
55c11941 5569 if (FCOE_INIT(bp) &&
fd1fc79d
AE		 5570 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5571 /* Prevent local bottom-halves from running as
5572 * we are going to change the local NAPI list.
5573 */
5574 local_bh_disable();
5575 napi_schedule(&bnx2x_fcoe(bp, napi));
5576 local_bh_enable();
5577 }
5578
5579 /* Handle EQ completions */
5580 bnx2x_eq_int(bp);
5581 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5582 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5583
5584 status &= ~BNX2X_DEF_SB_IDX;
019dbb4c 5585 }
55c11941 5586
fd1fc79d
AE		 5587 /* if status is non zero then perhaps something went wrong */
5588 if (unlikely(status))
5589 DP(BNX2X_MSG_SP,
5590 "got an unknown interrupt! (status 0x%x)\n", status);
523224a3 5591
fd1fc79d
AE		 5592 /* ack status block only if something was actually handled */
5593 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5594 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
cdaa7cb8
VZ		 5595 }
5596
a3348722
BW		 5597 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5598 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5599 &bp->sp_state)) {
5600 bnx2x_link_report(bp);
5601 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5602 }
a2fbb9ea
ET		 5603}
5604
9f6c9258 5605irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 5606{
5607 struct net_device *dev = dev_instance;
5608 struct bnx2x *bp = netdev_priv(dev);
5609
523224a3
DK		 5610 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5611 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 5612
5613#ifdef BNX2X_STOP_ON_ERROR
5614 if (unlikely(bp->panic))
5615 return IRQ_HANDLED;
5616#endif
5617
55c11941 5618 if (CNIC_LOADED(bp)) {
993ac7b5
MC		 5619 struct cnic_ops *c_ops;
5620
5621 rcu_read_lock();
5622 c_ops = rcu_dereference(bp->cnic_ops);
5623 if (c_ops)
5624 c_ops->cnic_handler(bp->cnic_data, NULL);
5625 rcu_read_unlock();
5626 }
55c11941 5627
fd1fc79d
AE		 5628 /* schedule sp task to perform default status block work, ack
5629 * attentions and enable interrupts.
5630 */
5631 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 5632
5633 return IRQ_HANDLED;
5634}
5635
5636/* end of slow path */
5637
619c5cb6
VZ		 5638void bnx2x_drv_pulse(struct bnx2x *bp)
5639{
5640 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5641 bp->fw_drv_pulse_wr_seq);
5642}
5643
a2fbb9ea
ET		 5644static void bnx2x_timer(unsigned long data)
5645{
5646 struct bnx2x *bp = (struct bnx2x *) data;
5647
5648 if (!netif_running(bp->dev))
5649 return;
5650
67c431a5
AE		 5651 if (IS_PF(bp) &&
5652 !BP_NOMCP(bp)) {
f2e0899f 5653 int mb_idx = BP_FW_MB_IDX(bp);
4c868664
EG		 5654 u16 drv_pulse;
5655 u16 mcp_pulse;
a2fbb9ea
ET		 5656
5657 ++bp->fw_drv_pulse_wr_seq;
5658 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
a2fbb9ea 5659 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 5660 bnx2x_drv_pulse(bp);
a2fbb9ea 5661
f2e0899f 5662 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 5663 MCP_PULSE_SEQ_MASK);
5664 /* The delta between driver pulse and mcp response
4c868664
EG		 5665 * should not get too big. If the MFW is more than 5 pulses
5666 * behind, we should worry about it enough to generate an error
5667 * log.
a2fbb9ea 5668 */
4c868664
EG		 5669 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5670 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
a2fbb9ea 5671 drv_pulse, mcp_pulse);
a2fbb9ea
ET		 5672 }
5673
f34d28ea 5674 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 5675 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 5676
abc5a021 5677 /* sample pf vf bulletin board for new posts from pf */
37173488
YM		 5678 if (IS_VF(bp))
5679 bnx2x_timer_sriov(bp);
78c3bcc5 5680
a2fbb9ea
ET		 5681 mod_timer(&bp->timer, jiffies + bp->current_interval);
5682}
5683
5684/* end of Statistics */
5685
5686/* nic init */
5687
5688/*
5689 * nic init service functions
5690 */
5691
1191cb83 5692static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 5693{
523224a3
DK		 5694 u32 i;
5695 if (!(len%4) && !(addr%4))
5696 for (i = 0; i < len; i += 4)
5697 REG_WR(bp, addr + i, fill);
5698 else
5699 for (i = 0; i < len; i++)
5700 REG_WR8(bp, addr + i, fill);
34f80b04
EG		 5701}
5702
523224a3 5703/* helper: writes FP SP data to FW - data_size in dwords */
1191cb83
ED		 5704static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5705 int fw_sb_id,
5706 u32 *sb_data_p,
5707 u32 data_size)
34f80b04 5708{
a2fbb9ea 5709 int index;
523224a3
DK		 5710 for (index = 0; index < data_size; index++)
5711 REG_WR(bp, BAR_CSTRORM_INTMEM +
5712 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5713 sizeof(u32)*index,
5714 *(sb_data_p + index));
5715}
a2fbb9ea 5716
1191cb83 5717static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
523224a3
DK		 5718{
5719 u32 *sb_data_p;
5720 u32 data_size = 0;
f2e0899f 5721 struct hc_status_block_data_e2 sb_data_e2;
523224a3 5722 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 5723
523224a3 5724 /* disable the function first */
619c5cb6 5725 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5726 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5727 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 5728 sb_data_e2.common.p_func.vf_valid = false;
5729 sb_data_p = (u32 *)&sb_data_e2;
5730 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5731 } else {
5732 memset(&sb_data_e1x, 0,
5733 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5734 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 5735 sb_data_e1x.common.p_func.vf_valid = false;
5736 sb_data_p = (u32 *)&sb_data_e1x;
5737 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5738 }
523224a3 5739 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 5740
523224a3
DK		 5741 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5742 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5743 CSTORM_STATUS_BLOCK_SIZE);
5744 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5745 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5746 CSTORM_SYNC_BLOCK_SIZE);
5747}
34f80b04 5748
523224a3 5749/* helper: writes SP SB data to FW */
1191cb83 5750static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
523224a3
DK		 5751 struct hc_sp_status_block_data *sp_sb_data)
5752{
5753 int func = BP_FUNC(bp);
5754 int i;
5755 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5756 REG_WR(bp, BAR_CSTRORM_INTMEM +
5757 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5758 i*sizeof(u32),
5759 *((u32 *)sp_sb_data + i));
34f80b04
EG		 5760}
5761
1191cb83 5762static void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 5763{
5764 int func = BP_FUNC(bp);
523224a3
DK		 5765 struct hc_sp_status_block_data sp_sb_data;
5766 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 5767
619c5cb6 5768 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 5769 sp_sb_data.p_func.vf_valid = false;
5770
5771 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5772
5773 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5774 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5775 CSTORM_SP_STATUS_BLOCK_SIZE);
5776 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5777 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5778 CSTORM_SP_SYNC_BLOCK_SIZE);
523224a3
DK		 5779}
5780
1191cb83 5781static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
523224a3
DK		 5782 int igu_sb_id, int igu_seg_id)
5783{
5784 hc_sm->igu_sb_id = igu_sb_id;
5785 hc_sm->igu_seg_id = igu_seg_id;
5786 hc_sm->timer_value = 0xFF;
5787 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 5788}
5789
150966ad 5790/* allocates state machine ids. */
1191cb83 5791static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
150966ad
AE		 5792{
5793 /* zero out state machine indices */
5794 /* rx indices */
5795 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5796
5797 /* tx indices */
5798 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5799 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5800 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5801 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5802
5803 /* map indices */
5804 /* rx indices */
5805 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5806 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5807
5808 /* tx indices */
5809 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5810 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5811 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5812 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5813 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5814 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5815 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5816 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5817}
5818
b93288d5 5819void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 5820 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 5821{
523224a3
DK		 5822 int igu_seg_id;
5823
f2e0899f 5824 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 5825 struct hc_status_block_data_e1x sb_data_e1x;
5826 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 5827 int data_size;
5828 u32 *sb_data_p;
5829
f2e0899f
DK		 5830 if (CHIP_INT_MODE_IS_BC(bp))
5831 igu_seg_id = HC_SEG_ACCESS_NORM;
5832 else
5833 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 5834
5835 bnx2x_zero_fp_sb(bp, fw_sb_id);
5836
619c5cb6 5837 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5838 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5839 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 5840 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5841 sb_data_e2.common.p_func.vf_id = vfid;
5842 sb_data_e2.common.p_func.vf_valid = vf_valid;
5843 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5844 sb_data_e2.common.same_igu_sb_1b = true;
5845 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5846 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5847 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 5848 sb_data_p = (u32 *)&sb_data_e2;
5849 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 5850 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 5851 } else {
5852 memset(&sb_data_e1x, 0,
5853 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5854 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 5855 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5856 sb_data_e1x.common.p_func.vf_id = 0xff;
5857 sb_data_e1x.common.p_func.vf_valid = false;
5858 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5859 sb_data_e1x.common.same_igu_sb_1b = true;
5860 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5861 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5862 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 5863 sb_data_p = (u32 *)&sb_data_e1x;
5864 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 5865 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 5866 }
523224a3
DK		 5867
5868 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5869 igu_sb_id, igu_seg_id);
5870 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5871 igu_sb_id, igu_seg_id);
5872
51c1a580 5873 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
523224a3 5874
86564c3f 5875 /* write indices to HW - PCI guarantees endianity of regpairs */
523224a3
DK		 5876 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5877}
5878
619c5cb6 5879static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 5880 u16 tx_usec, u16 rx_usec)
5881{
6383c0b3 5882 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 5883 false, rx_usec);
6383c0b3
AE		 5884 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5885 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5886 tx_usec);
5887 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5888 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5889 tx_usec);
5890 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5891 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5892 tx_usec);
523224a3 5893}
f2e0899f 5894
523224a3
DK		 5895static void bnx2x_init_def_sb(struct bnx2x *bp)
5896{
5897 struct host_sp_status_block *def_sb = bp->def_status_blk;
5898 dma_addr_t mapping = bp->def_status_blk_mapping;
5899 int igu_sp_sb_index;
5900 int igu_seg_id;
34f80b04
EG		 5901 int port = BP_PORT(bp);
5902 int func = BP_FUNC(bp);
f2eaeb58 5903 int reg_offset, reg_offset_en5;
a2fbb9ea 5904 u64 section;
523224a3
DK		 5905 int index;
5906 struct hc_sp_status_block_data sp_sb_data;
5907 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5908
f2e0899f
DK		 5909 if (CHIP_INT_MODE_IS_BC(bp)) {
5910 igu_sp_sb_index = DEF_SB_IGU_ID;
5911 igu_seg_id = HC_SEG_ACCESS_DEF;
5912 } else {
5913 igu_sp_sb_index = bp->igu_dsb_id;
5914 igu_seg_id = IGU_SEG_ACCESS_DEF;
5915 }
a2fbb9ea
ET		 5916
5917 /* ATTN */
523224a3 5918 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 5919 atten_status_block);
523224a3 5920 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 5921
49d66772
ET		 5922 bp->attn_state = 0;
5923
a2fbb9ea
ET		 5924 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5925 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 5926 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5927 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 5928 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 5929 int sindex;
5930 /* take care of sig[0]..sig[4] */
5931 for (sindex = 0; sindex < 4; sindex++)
5932 bp->attn_group[index].sig[sindex] =
5933 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 5934
619c5cb6 5935 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5936 /*
5937 * enable5 is separate from the rest of the registers,
5938 * and therefore the address skip is 4
5939 * and not 16 between the different groups
5940 */
5941 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 5942 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 5943 else
5944 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 5945 }
5946
f2e0899f
DK		 5947 if (bp->common.int_block == INT_BLOCK_HC) {
5948 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5949 HC_REG_ATTN_MSG0_ADDR_L);
5950
5951 REG_WR(bp, reg_offset, U64_LO(section));
5952 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 5953 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5954 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5955 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5956 }
a2fbb9ea 5957
523224a3
DK		 5958 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5959 sp_sb);
a2fbb9ea 5960
523224a3 5961 bnx2x_zero_sp_sb(bp);
a2fbb9ea 5962
86564c3f 5963 /* PCI guarantees endianity of regpairs */
619c5cb6 5964 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 5965 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5966 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5967 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5968 sp_sb_data.igu_seg_id = igu_seg_id;
5969 sp_sb_data.p_func.pf_id = func;
f2e0899f 5970 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 5971 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 5972
523224a3 5973 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 5974
523224a3 5975 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 5976}
5977
9f6c9258 5978void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 5979{
a2fbb9ea
ET		 5980 int i;
5981
ec6ba945 5982 for_each_eth_queue(bp, i)
523224a3 5983 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 5984 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 5985}
5986
a2fbb9ea
ET		 5987static void bnx2x_init_sp_ring(struct bnx2x *bp)
5988{
a2fbb9ea 5989 spin_lock_init(&bp->spq_lock);
6e30dd4e 5990 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 5991
a2fbb9ea 5992 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 5993 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5994 bp->spq_prod_bd = bp->spq;
5995 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 5996}
5997
523224a3 5998static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 5999{
6000 int i;
523224a3
DK		 6001 for (i = 1; i <= NUM_EQ_PAGES; i++) {
6002 union event_ring_elem *elem =
6003 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 6004
523224a3
DK		 6005 elem->next_page.addr.hi =
6006 cpu_to_le32(U64_HI(bp->eq_mapping +
6007 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6008 elem->next_page.addr.lo =
6009 cpu_to_le32(U64_LO(bp->eq_mapping +
6010 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 6011 }
523224a3
DK		 6012 bp->eq_cons = 0;
6013 bp->eq_prod = NUM_EQ_DESC;
6014 bp->eq_cons_sb = BNX2X_EQ_INDEX;
16a5fd92 6015 /* we want a warning message before it gets wrought... */
6e30dd4e
VZ		 6016 atomic_set(&bp->eq_spq_left,
6017 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 6018}
6019
619c5cb6 6020/* called with netif_addr_lock_bh() */
a8f47eb7 6021static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6022 unsigned long rx_mode_flags,
6023 unsigned long rx_accept_flags,
6024 unsigned long tx_accept_flags,
6025 unsigned long ramrod_flags)
ab532cf3 6026{
619c5cb6
VZ		 6027 struct bnx2x_rx_mode_ramrod_params ramrod_param;
6028 int rc;
6029
6030 memset(&ramrod_param, 0, sizeof(ramrod_param));
6031
6032 /* Prepare ramrod parameters */
6033 ramrod_param.cid = 0;
6034 ramrod_param.cl_id = cl_id;
6035 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6036 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 6037
619c5cb6
VZ		 6038 ramrod_param.pstate = &bp->sp_state;
6039 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 6040
619c5cb6
VZ		 6041 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6042 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6043
6044 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6045
6046 ramrod_param.ramrod_flags = ramrod_flags;
6047 ramrod_param.rx_mode_flags = rx_mode_flags;
6048
6049 ramrod_param.rx_accept_flags = rx_accept_flags;
6050 ramrod_param.tx_accept_flags = tx_accept_flags;
6051
6052 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6053 if (rc < 0) {
6054 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
924d75ab 6055 return rc;
619c5cb6 6056 }
924d75ab
YM		 6057
6058 return 0;
a2fbb9ea
ET		 6059}
6060
86564c3f
YM		 6061static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6062 unsigned long *rx_accept_flags,
6063 unsigned long *tx_accept_flags)
471de716 6064{
924d75ab
YM		 6065 /* Clear the flags first */
6066 *rx_accept_flags = 0;
6067 *tx_accept_flags = 0;
619c5cb6 6068
924d75ab 6069 switch (rx_mode) {
619c5cb6
VZ		 6070 case BNX2X_RX_MODE_NONE:
6071 /*
6072 * 'drop all' supersedes any accept flags that may have been
6073 * passed to the function.
6074 */
6075 break;
6076 case BNX2X_RX_MODE_NORMAL:
924d75ab
YM		 6077 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6078 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6079 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6080
6081 /* internal switching mode */
924d75ab
YM		 6082 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6083 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6084 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6085
6086 break;
6087 case BNX2X_RX_MODE_ALLMULTI:
924d75ab
YM		 6088 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6089 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6090 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6091
6092 /* internal switching mode */
924d75ab
YM		 6093 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6094 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6095 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6096
6097 break;
6098 case BNX2X_RX_MODE_PROMISC:
16a5fd92 6099 /* According to definition of SI mode, iface in promisc mode
619c5cb6
VZ		 6100 * should receive matched and unmatched (in resolution of port)
6101 * unicast packets.
6102 */
924d75ab
YM		 6103 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6104 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6105 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6106 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6107
6108 /* internal switching mode */
924d75ab
YM		 6109 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6110 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6111
6112 if (IS_MF_SI(bp))
924d75ab 6113 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
619c5cb6 6114 else
924d75ab 6115 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
619c5cb6
VZ		 6116
6117 break;
6118 default:
924d75ab
YM		 6119 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6120 return -EINVAL;
619c5cb6 6121 }
de832a55 6122
924d75ab 6123 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
0c23ad37 6124 if (rx_mode != BNX2X_RX_MODE_NONE) {
924d75ab
YM		 6125 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6126 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
34f80b04
EG		 6127 }
6128
924d75ab
YM		 6129 return 0;
6130}
6131
6132/* called with netif_addr_lock_bh() */
a8f47eb7 6133static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
924d75ab
YM		 6134{
6135 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6136 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6137 int rc;
6138
6139 if (!NO_FCOE(bp))
6140 /* Configure rx_mode of FCoE Queue */
6141 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6142
6143 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6144 &tx_accept_flags);
6145 if (rc)
6146 return rc;
6147
619c5cb6
VZ		 6148 __set_bit(RAMROD_RX, &ramrod_flags);
6149 __set_bit(RAMROD_TX, &ramrod_flags);
6150
924d75ab
YM		 6151 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6152 rx_accept_flags, tx_accept_flags,
6153 ramrod_flags);
619c5cb6
VZ		 6154}
6155
6156static void bnx2x_init_internal_common(struct bnx2x *bp)
6157{
6158 int i;
6159
523224a3
DK		 6160 /* Zero this manually as its initialization is
6161 currently missing in the initTool */
6162 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 6163 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 6164 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 6165 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6166 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6167 CHIP_INT_MODE_IS_BC(bp) ?
6168 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6169 }
523224a3 6170}
8a1c38d1 6171
471de716
EG		 6172static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6173{
6174 switch (load_code) {
6175 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 6176 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 6177 bnx2x_init_internal_common(bp);
6178 /* no break */
6179
6180 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 6181 /* nothing to do */
471de716
EG		 6182 /* no break */
6183
6184 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 6185 /* internal memory per function is
6186 initialized inside bnx2x_pf_init */
471de716
EG		 6187 break;
6188
6189 default:
6190 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6191 break;
6192 }
6193}
6194
619c5cb6 6195static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 6196{
55c11941 6197 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6 6198}
523224a3 6199
619c5cb6
VZ		 6200static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6201{
55c11941 6202 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6
VZ		 6203}
6204
1191cb83 6205static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
619c5cb6
VZ		 6206{
6207 if (CHIP_IS_E1x(fp->bp))
6208 return BP_L_ID(fp->bp) + fp->index;
6209 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6210 return bnx2x_fp_igu_sb_id(fp);
6211}
6212
6383c0b3 6213static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 6214{
6215 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 6216 u8 cos;
619c5cb6 6217 unsigned long q_type = 0;
6383c0b3 6218 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 6219 fp->rx_queue = fp_idx;
b3b83c3f 6220 fp->cid = fp_idx;
619c5cb6
VZ		 6221 fp->cl_id = bnx2x_fp_cl_id(fp);
6222 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6223 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 6224 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 6225 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6226
523224a3 6227 /* init shortcut */
619c5cb6 6228 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
7a752993 6229
16a5fd92 6230 /* Setup SB indices */
523224a3 6231 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 6232
619c5cb6
VZ		 6233 /* Configure Queue State object */
6234 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6235 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 6236
6237 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6238
6239 /* init tx data */
6240 for_each_cos_in_tx_queue(fp, cos) {
65565884
MS		 6241 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6242 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6243 FP_COS_TO_TXQ(fp, cos, bp),
6244 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6245 cids[cos] = fp->txdata_ptr[cos]->cid;
6383c0b3
AE		 6246 }
6247
ad5afc89
AE		 6248 /* nothing more for vf to do here */
6249 if (IS_VF(bp))
6250 return;
6251
6252 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6253 fp->fw_sb_id, fp->igu_sb_id);
6254 bnx2x_update_fpsb_idx(fp);
15192a8c
BW		 6255 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6256 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6383c0b3 6257 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 6258
6259 /**
6260 * Configure classification DBs: Always enable Tx switching
6261 */
6262 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6263
ad5afc89
AE		 6264 DP(NETIF_MSG_IFUP,
6265 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6266 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6267 fp->igu_sb_id);
523224a3
DK		 6268}
6269
1191cb83
ED		 6270static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6271{
6272 int i;
6273
6274 for (i = 1; i <= NUM_TX_RINGS; i++) {
6275 struct eth_tx_next_bd *tx_next_bd =
6276 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6277
6278 tx_next_bd->addr_hi =
6279 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6280 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6281 tx_next_bd->addr_lo =
6282 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6283 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6284 }
6285
639d65b8
YM		 6286 *txdata->tx_cons_sb = cpu_to_le16(0);
6287
1191cb83
ED		 6288 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6289 txdata->tx_db.data.zero_fill1 = 0;
6290 txdata->tx_db.data.prod = 0;
6291
6292 txdata->tx_pkt_prod = 0;
6293 txdata->tx_pkt_cons = 0;
6294 txdata->tx_bd_prod = 0;
6295 txdata->tx_bd_cons = 0;
6296 txdata->tx_pkt = 0;
6297}
6298
55c11941
MS		 6299static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6300{
6301 int i;
6302
6303 for_each_tx_queue_cnic(bp, i)
6304 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6305}
d76a6111 6306
1191cb83
ED		 6307static void bnx2x_init_tx_rings(struct bnx2x *bp)
6308{
6309 int i;
6310 u8 cos;
6311
55c11941 6312 for_each_eth_queue(bp, i)
1191cb83 6313 for_each_cos_in_tx_queue(&bp->fp[i], cos)
65565884 6314 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
1191cb83
ED		 6315}
6316
a8f47eb7 6317static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6318{
6319 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6320 unsigned long q_type = 0;
6321
6322 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6323 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6324 BNX2X_FCOE_ETH_CL_ID_IDX);
6325 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6326 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6327 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6328 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6329 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6330 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6331 fp);
6332
6333 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6334
6335 /* qZone id equals to FW (per path) client id */
6336 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6337 /* init shortcut */
6338 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6339 bnx2x_rx_ustorm_prods_offset(fp);
6340
6341 /* Configure Queue State object */
6342 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6343 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6344
6345 /* No multi-CoS for FCoE L2 client */
6346 BUG_ON(fp->max_cos != 1);
6347
6348 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6349 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6350 bnx2x_sp_mapping(bp, q_rdata), q_type);
6351
6352 DP(NETIF_MSG_IFUP,
6353 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6354 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6355 fp->igu_sb_id);
6356}
6357
55c11941 6358void bnx2x_nic_init_cnic(struct bnx2x *bp)
a2fbb9ea 6359{
ec6ba945
VZ		 6360 if (!NO_FCOE(bp))
6361 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 6362
6363 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6364 BNX2X_VF_ID_INVALID, false,
619c5cb6 6365 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 6366
55c11941
MS		 6367 /* ensure status block indices were read */
6368 rmb();
6369 bnx2x_init_rx_rings_cnic(bp);
6370 bnx2x_init_tx_rings_cnic(bp);
6371
6372 /* flush all */
6373 mb();
6374 mmiowb();
6375}
a2fbb9ea 6376
ecf01c22 6377void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
55c11941
MS		 6378{
6379 int i;
6380
ecf01c22 6381 /* Setup NIC internals and enable interrupts */
55c11941
MS		 6382 for_each_eth_queue(bp, i)
6383 bnx2x_init_eth_fp(bp, i);
ad5afc89
AE		 6384
6385 /* ensure status block indices were read */
6386 rmb();
6387 bnx2x_init_rx_rings(bp);
6388 bnx2x_init_tx_rings(bp);
6389
ecf01c22
YM		 6390 if (IS_PF(bp)) {
6391 /* Initialize MOD_ABS interrupts */
6392 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6393 bp->common.shmem_base,
6394 bp->common.shmem2_base, BP_PORT(bp));
ad5afc89 6395
ecf01c22
YM		 6396 /* initialize the default status block and sp ring */
6397 bnx2x_init_def_sb(bp);
6398 bnx2x_update_dsb_idx(bp);
6399 bnx2x_init_sp_ring(bp);
3cdeec22
YM		 6400 } else {
6401 bnx2x_memset_stats(bp);
ecf01c22
YM		 6402 }
6403}
16119785 6404
ecf01c22
YM		 6405void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6406{
523224a3 6407 bnx2x_init_eq_ring(bp);
471de716 6408 bnx2x_init_internal(bp, load_code);
523224a3 6409 bnx2x_pf_init(bp);
0ef00459
EG		 6410 bnx2x_stats_init(bp);
6411
0ef00459
EG		 6412 /* flush all before enabling interrupts */
6413 mb();
6414 mmiowb();
6415
615f8fd9 6416 bnx2x_int_enable(bp);
eb8da205
EG		 6417
6418 /* Check for SPIO5 */
6419 bnx2x_attn_int_deasserted0(bp,
6420 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6421 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 6422}
6423
ecf01c22 6424/* gzip service functions */
a2fbb9ea
ET		 6425static int bnx2x_gunzip_init(struct bnx2x *bp)
6426{
1a983142
FT		 6427 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6428 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 6429 if (bp->gunzip_buf == NULL)
6430 goto gunzip_nomem1;
6431
6432 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6433 if (bp->strm == NULL)
6434 goto gunzip_nomem2;
6435
7ab24bfd 6436 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 6437 if (bp->strm->workspace == NULL)
6438 goto gunzip_nomem3;
6439
6440 return 0;
6441
6442gunzip_nomem3:
6443 kfree(bp->strm);
6444 bp->strm = NULL;
6445
6446gunzip_nomem2:
1a983142
FT		 6447 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6448 bp->gunzip_mapping);
a2fbb9ea
ET		 6449 bp->gunzip_buf = NULL;
6450
6451gunzip_nomem1:
51c1a580 6452 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
a2fbb9ea
ET		 6453 return -ENOMEM;
6454}
6455
6456static void bnx2x_gunzip_end(struct bnx2x *bp)
6457{
b3b83c3f 6458 if (bp->strm) {
7ab24bfd 6459 vfree(bp->strm->workspace);
b3b83c3f
DK		 6460 kfree(bp->strm);
6461 bp->strm = NULL;
6462 }
a2fbb9ea
ET		 6463
6464 if (bp->gunzip_buf) {
1a983142
FT		 6465 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6466 bp->gunzip_mapping);
a2fbb9ea
ET		 6467 bp->gunzip_buf = NULL;
6468 }
6469}
6470
94a78b79 6471static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 6472{
6473 int n, rc;
6474
6475 /* check gzip header */
94a78b79
VZ		 6476 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6477 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 6478 return -EINVAL;
94a78b79 6479 }
a2fbb9ea
ET		 6480
6481 n = 10;
6482
34f80b04 6483#define FNAME 0x8
a2fbb9ea
ET		 6484
6485 if (zbuf[3] & FNAME)
6486 while ((zbuf[n++] != 0) && (n < len));
6487
94a78b79 6488 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 6489 bp->strm->avail_in = len - n;
6490 bp->strm->next_out = bp->gunzip_buf;
6491 bp->strm->avail_out = FW_BUF_SIZE;
6492
6493 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6494 if (rc != Z_OK)
6495 return rc;
6496
6497 rc = zlib_inflate(bp->strm, Z_FINISH);
6498 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 6499 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6500 bp->strm->msg);
a2fbb9ea
ET		 6501
6502 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6503 if (bp->gunzip_outlen & 0x3)
51c1a580
MS		 6504 netdev_err(bp->dev,
6505 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
cdaa7cb8 6506 bp->gunzip_outlen);
a2fbb9ea
ET		 6507 bp->gunzip_outlen >>= 2;
6508
6509 zlib_inflateEnd(bp->strm);
6510
6511 if (rc == Z_STREAM_END)
6512 return 0;
6513
6514 return rc;
6515}
6516
6517/* nic load/unload */
6518
6519/*
34f80b04 6520 * General service functions
a2fbb9ea
ET		 6521 */
6522
6523/* send a NIG loopback debug packet */
6524static void bnx2x_lb_pckt(struct bnx2x *bp)
6525{
a2fbb9ea 6526 u32 wb_write[3];
a2fbb9ea
ET		 6527
6528 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 6529 wb_write[0] = 0x55555555;
6530 wb_write[1] = 0x55555555;
34f80b04 6531 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 6532 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6533
6534 /* NON-IP protocol */
a2fbb9ea
ET		 6535 wb_write[0] = 0x09000000;
6536 wb_write[1] = 0x55555555;
34f80b04 6537 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 6538 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6539}
6540
6541/* some of the internal memories
6542 * are not directly readable from the driver
6543 * to test them we send debug packets
6544 */
6545static int bnx2x_int_mem_test(struct bnx2x *bp)
6546{
6547 int factor;
6548 int count, i;
6549 u32 val = 0;
6550
ad8d3948 6551 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 6552 factor = 120;
ad8d3948
EG		 6553 else if (CHIP_REV_IS_EMUL(bp))
6554 factor = 200;
6555 else
a2fbb9ea 6556 factor = 1;
a2fbb9ea 6557
a2fbb9ea
ET		 6558 /* Disable inputs of parser neighbor blocks */
6559 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6560 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6561 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6562 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6563
6564 /* Write 0 to parser credits for CFC search request */
6565 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6566
6567 /* send Ethernet packet */
6568 bnx2x_lb_pckt(bp);
6569
6570 /* TODO do i reset NIG statistic? */
6571 /* Wait until NIG register shows 1 packet of size 0x10 */
6572 count = 1000 * factor;
6573 while (count) {
34f80b04 6574
a2fbb9ea
ET		 6575 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6576 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6577 if (val == 0x10)
6578 break;
6579
639d65b8 6580 usleep_range(10000, 20000);
a2fbb9ea
ET		 6581 count--;
6582 }
6583 if (val != 0x10) {
6584 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6585 return -1;
6586 }
6587
6588 /* Wait until PRS register shows 1 packet */
6589 count = 1000 * factor;
6590 while (count) {
6591 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 6592 if (val == 1)
6593 break;
6594
639d65b8 6595 usleep_range(10000, 20000);
a2fbb9ea
ET		 6596 count--;
6597 }
6598 if (val != 0x1) {
6599 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6600 return -2;
6601 }
6602
6603 /* Reset and init BRB, PRS */
34f80b04 6604 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 6605 msleep(50);
34f80b04 6606 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 6607 msleep(50);
619c5cb6
VZ		 6608 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6609 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 6610
6611 DP(NETIF_MSG_HW, "part2\n");
6612
6613 /* Disable inputs of parser neighbor blocks */
6614 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6615 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6616 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6617 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6618
6619 /* Write 0 to parser credits for CFC search request */
6620 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6621
6622 /* send 10 Ethernet packets */
6623 for (i = 0; i < 10; i++)
6624 bnx2x_lb_pckt(bp);
6625
6626 /* Wait until NIG register shows 10 + 1
6627 packets of size 11*0x10 = 0xb0 */
6628 count = 1000 * factor;
6629 while (count) {
34f80b04 6630
a2fbb9ea
ET		 6631 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6632 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6633 if (val == 0xb0)
6634 break;
6635
639d65b8 6636 usleep_range(10000, 20000);
a2fbb9ea
ET		 6637 count--;
6638 }
6639 if (val != 0xb0) {
6640 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6641 return -3;
6642 }
6643
6644 /* Wait until PRS register shows 2 packets */
6645 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6646 if (val != 2)
6647 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6648
6649 /* Write 1 to parser credits for CFC search request */
6650 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6651
6652 /* Wait until PRS register shows 3 packets */
6653 msleep(10 * factor);
6654 /* Wait until NIG register shows 1 packet of size 0x10 */
6655 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6656 if (val != 3)
6657 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6658
6659 /* clear NIG EOP FIFO */
6660 for (i = 0; i < 11; i++)
6661 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6662 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6663 if (val != 1) {
6664 BNX2X_ERR("clear of NIG failed\n");
6665 return -4;
6666 }
6667
6668 /* Reset and init BRB, PRS, NIG */
6669 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6670 msleep(50);
6671 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6672 msleep(50);
619c5cb6
VZ		 6673 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6674 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
55c11941
MS		 6675 if (!CNIC_SUPPORT(bp))
6676 /* set NIC mode */
6677 REG_WR(bp, PRS_REG_NIC_MODE, 1);
a2fbb9ea
ET		 6678
6679 /* Enable inputs of parser neighbor blocks */
6680 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6681 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6682 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 6683 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 6684
6685 DP(NETIF_MSG_HW, "done\n");
6686
6687 return 0; /* OK */
6688}
6689
4a33bc03 6690static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea 6691{
b343d002
YM		 6692 u32 val;
6693
a2fbb9ea 6694 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 6695 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6696 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6697 else
6698 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 6699 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6700 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 6701 /*
6702 * mask read length error interrupts in brb for parser
6703 * (parsing unit and 'checksum and crc' unit)
6704 * these errors are legal (PU reads fixed length and CAC can cause
6705 * read length error on truncated packets)
6706 */
6707 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 6708 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6709 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6710 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6711 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6712 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 6713/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6714/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6715 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6716 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6717 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 6718/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6719/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6720 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6721 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6722 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6723 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 6724/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6725/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 6726
b343d002
YM		 6727 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6728 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6729 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6730 if (!CHIP_IS_E1x(bp))
6731 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6732 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6733 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6734
a2fbb9ea
ET		 6735 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6736 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6737 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 6738/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 6739
6740 if (!CHIP_IS_E1x(bp))
6741 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6742 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6743
a2fbb9ea
ET		 6744 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6745 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 6746/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 6747 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 6748}
6749
81f75bbf
EG		 6750static void bnx2x_reset_common(struct bnx2x *bp)
6751{
619c5cb6
VZ		 6752 u32 val = 0x1400;
6753
81f75bbf
EG		 6754 /* reset_common */
6755 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6756 0xd3ffff7f);
619c5cb6
VZ		 6757
6758 if (CHIP_IS_E3(bp)) {
6759 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6760 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6761 }
6762
6763 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6764}
6765
6766static void bnx2x_setup_dmae(struct bnx2x *bp)
6767{
6768 bp->dmae_ready = 0;
6769 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 6770}
6771
573f2035
EG		 6772static void bnx2x_init_pxp(struct bnx2x *bp)
6773{
6774 u16 devctl;
6775 int r_order, w_order;
6776
2a80eebc 6777 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 6778 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6779 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6780 if (bp->mrrs == -1)
6781 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6782 else {
6783 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6784 r_order = bp->mrrs;
6785 }
6786
6787 bnx2x_init_pxp_arb(bp, r_order, w_order);
6788}
fd4ef40d
EG		 6789
6790static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6791{
2145a920 6792 int is_required;
fd4ef40d 6793 u32 val;
2145a920 6794 int port;
fd4ef40d 6795
2145a920
VZ		 6796 if (BP_NOMCP(bp))
6797 return;
6798
6799 is_required = 0;
fd4ef40d
EG		 6800 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6801 SHARED_HW_CFG_FAN_FAILURE_MASK;
6802
6803 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6804 is_required = 1;
6805
6806 /*
6807 * The fan failure mechanism is usually related to the PHY type since
6808 * the power consumption of the board is affected by the PHY. Currently,
6809 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6810 */
6811 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6812 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 6813 is_required |=
d90d96ba
YR		 6814 bnx2x_fan_failure_det_req(
6815 bp,
6816 bp->common.shmem_base,
a22f0788 6817 bp->common.shmem2_base,
d90d96ba 6818 port);
fd4ef40d
EG		 6819 }
6820
6821 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6822
6823 if (is_required == 0)
6824 return;
6825
6826 /* Fan failure is indicated by SPIO 5 */
d6d99a3f 6827 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
fd4ef40d
EG		 6828
6829 /* set to active low mode */
6830 val = REG_RD(bp, MISC_REG_SPIO_INT);
d6d99a3f 6831 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 6832 REG_WR(bp, MISC_REG_SPIO_INT, val);
6833
6834 /* enable interrupt to signal the IGU */
6835 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 6836 val |= MISC_SPIO_SPIO5;
fd4ef40d
EG		 6837 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6838}
6839
c9ee9206 6840void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 6841{
6842 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6843 val &= ~IGU_PF_CONF_FUNC_EN;
6844
6845 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6846 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6847 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6848}
6849
1191cb83 6850static void bnx2x__common_init_phy(struct bnx2x *bp)
619c5cb6
VZ		 6851{
6852 u32 shmem_base[2], shmem2_base[2];
b884d95b
YR		 6853 /* Avoid common init in case MFW supports LFA */
6854 if (SHMEM2_RD(bp, size) >
6855 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6856 return;
619c5cb6
VZ		 6857 shmem_base[0] = bp->common.shmem_base;
6858 shmem2_base[0] = bp->common.shmem2_base;
6859 if (!CHIP_IS_E1x(bp)) {
6860 shmem_base[1] =
6861 SHMEM2_RD(bp, other_shmem_base_addr);
6862 shmem2_base[1] =
6863 SHMEM2_RD(bp, other_shmem2_base_addr);
6864 }
6865 bnx2x_acquire_phy_lock(bp);
6866 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6867 bp->common.chip_id);
6868 bnx2x_release_phy_lock(bp);
6869}
6870
04860eb7
MC		 6871static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6872{
6873 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6874 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
6875 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
6876 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
6877 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
6878
6879 /* make sure this value is 0 */
6880 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6881
6882 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
6883 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
6884 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
6885 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
6886}
6887
6888static void bnx2x_set_endianity(struct bnx2x *bp)
6889{
6890#ifdef __BIG_ENDIAN
6891 bnx2x_config_endianity(bp, 1);
6892#else
6893 bnx2x_config_endianity(bp, 0);
6894#endif
6895}
6896
6897static void bnx2x_reset_endianity(struct bnx2x *bp)
6898{
6899 bnx2x_config_endianity(bp, 0);
6900}
6901
619c5cb6
VZ		 6902/**
6903 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6904 *
6905 * @bp: driver handle
6906 */
6907static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 6908{
619c5cb6 6909 u32 val;
a2fbb9ea 6910
51c1a580 6911 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 6912
2031bd3a 6913 /*
2de67439 6914 * take the RESET lock to protect undi_unload flow from accessing
2031bd3a
DK		 6915 * registers while we're resetting the chip
6916 */
7a06a122 6917 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6918
81f75bbf 6919 bnx2x_reset_common(bp);
34f80b04 6920 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 6921
619c5cb6
VZ		 6922 val = 0xfffc;
6923 if (CHIP_IS_E3(bp)) {
6924 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6925 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6926 }
6927 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6928
7a06a122 6929 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6930
619c5cb6 6931 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 6932
619c5cb6
VZ		 6933 if (!CHIP_IS_E1x(bp)) {
6934 u8 abs_func_id;
f2e0899f
DK		 6935
6936 /**
6937 * 4-port mode or 2-port mode we need to turn of master-enable
6938 * for everyone, after that, turn it back on for self.
6939 * so, we disregard multi-function or not, and always disable
6940 * for all functions on the given path, this means 0,2,4,6 for
6941 * path 0 and 1,3,5,7 for path 1
6942 */
619c5cb6
VZ		 6943 for (abs_func_id = BP_PATH(bp);
6944 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6945 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 6946 REG_WR(bp,
6947 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6948 1);
6949 continue;
6950 }
6951
619c5cb6 6952 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 6953 /* clear pf enable */
6954 bnx2x_pf_disable(bp);
6955 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6956 }
6957 }
a2fbb9ea 6958
619c5cb6 6959 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 6960 if (CHIP_IS_E1(bp)) {
6961 /* enable HW interrupt from PXP on USDM overflow
6962 bit 16 on INT_MASK_0 */
6963 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6964 }
a2fbb9ea 6965
619c5cb6 6966 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 6967 bnx2x_init_pxp(bp);
04860eb7 6968 bnx2x_set_endianity(bp);
523224a3
DK		 6969 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6970
34f80b04
EG		 6971 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6972 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 6973
34f80b04
EG		 6974 /* let the HW do it's magic ... */
6975 msleep(100);
6976 /* finish PXP init */
6977 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6978 if (val != 1) {
6979 BNX2X_ERR("PXP2 CFG failed\n");
6980 return -EBUSY;
6981 }
6982 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6983 if (val != 1) {
6984 BNX2X_ERR("PXP2 RD_INIT failed\n");
6985 return -EBUSY;
6986 }
a2fbb9ea 6987
f2e0899f
DK		 6988 /* Timers bug workaround E2 only. We need to set the entire ILT to
6989 * have entries with value "0" and valid bit on.
6990 * This needs to be done by the first PF that is loaded in a path
6991 * (i.e. common phase)
6992 */
619c5cb6
VZ		 6993 if (!CHIP_IS_E1x(bp)) {
6994/* In E2 there is a bug in the timers block that can cause function 6 / 7
6995 * (i.e. vnic3) to start even if it is marked as "scan-off".
6996 * This occurs when a different function (func2,3) is being marked
6997 * as "scan-off". Real-life scenario for example: if a driver is being
6998 * load-unloaded while func6,7 are down. This will cause the timer to access
6999 * the ilt, translate to a logical address and send a request to read/write.
7000 * Since the ilt for the function that is down is not valid, this will cause
7001 * a translation error which is unrecoverable.
7002 * The Workaround is intended to make sure that when this happens nothing fatal
7003 * will occur. The workaround:
7004 * 1. First PF driver which loads on a path will:
7005 * a. After taking the chip out of reset, by using pretend,
7006 * it will write "0" to the following registers of
7007 * the other vnics.
7008 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7009 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7010 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7011 * And for itself it will write '1' to
7012 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7013 * dmae-operations (writing to pram for example.)
7014 * note: can be done for only function 6,7 but cleaner this
7015 * way.
7016 * b. Write zero+valid to the entire ILT.
7017 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
7018 * VNIC3 (of that port). The range allocated will be the
7019 * entire ILT. This is needed to prevent ILT range error.
7020 * 2. Any PF driver load flow:
7021 * a. ILT update with the physical addresses of the allocated
7022 * logical pages.
7023 * b. Wait 20msec. - note that this timeout is needed to make
7024 * sure there are no requests in one of the PXP internal
7025 * queues with "old" ILT addresses.
7026 * c. PF enable in the PGLC.
7027 * d. Clear the was_error of the PF in the PGLC. (could have
2de67439 7028 * occurred while driver was down)
619c5cb6
VZ		 7029 * e. PF enable in the CFC (WEAK + STRONG)
7030 * f. Timers scan enable
7031 * 3. PF driver unload flow:
7032 * a. Clear the Timers scan_en.
7033 * b. Polling for scan_on=0 for that PF.
7034 * c. Clear the PF enable bit in the PXP.
7035 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7036 * e. Write zero+valid to all ILT entries (The valid bit must
7037 * stay set)
7038 * f. If this is VNIC 3 of a port then also init
7039 * first_timers_ilt_entry to zero and last_timers_ilt_entry
16a5fd92 7040 * to the last entry in the ILT.
619c5cb6
VZ		 7041 *
7042 * Notes:
7043 * Currently the PF error in the PGLC is non recoverable.
7044 * In the future the there will be a recovery routine for this error.
7045 * Currently attention is masked.
7046 * Having an MCP lock on the load/unload process does not guarantee that
7047 * there is no Timer disable during Func6/7 enable. This is because the
7048 * Timers scan is currently being cleared by the MCP on FLR.
7049 * Step 2.d can be done only for PF6/7 and the driver can also check if
7050 * there is error before clearing it. But the flow above is simpler and
7051 * more general.
7052 * All ILT entries are written by zero+valid and not just PF6/7
7053 * ILT entries since in the future the ILT entries allocation for
7054 * PF-s might be dynamic.
7055 */
f2e0899f
DK		 7056 struct ilt_client_info ilt_cli;
7057 struct bnx2x_ilt ilt;
7058 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7059 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7060
b595076a 7061 /* initialize dummy TM client */
f2e0899f
DK		 7062 ilt_cli.start = 0;
7063 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7064 ilt_cli.client_num = ILT_CLIENT_TM;
7065
7066 /* Step 1: set zeroes to all ilt page entries with valid bit on
7067 * Step 2: set the timers first/last ilt entry to point
7068 * to the entire range to prevent ILT range error for 3rd/4th
2de67439 7069 * vnic (this code assumes existence of the vnic)
f2e0899f
DK		 7070 *
7071 * both steps performed by call to bnx2x_ilt_client_init_op()
7072 * with dummy TM client
7073 *
7074 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7075 * and his brother are split registers
7076 */
7077 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7078 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7079 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7080
7081 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7082 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7083 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7084 }
7085
34f80b04
EG		 7086 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7087 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 7088
619c5cb6 7089 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7090 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7091 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 7092 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 7093
619c5cb6 7094 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 7095
7096 /* let the HW do it's magic ... */
7097 do {
7098 msleep(200);
7099 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7100 } while (factor-- && (val != 1));
7101
7102 if (val != 1) {
7103 BNX2X_ERR("ATC_INIT failed\n");
7104 return -EBUSY;
7105 }
7106 }
7107
619c5cb6 7108 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 7109
b56e9670
AE		 7110 bnx2x_iov_init_dmae(bp);
7111
34f80b04
EG		 7112 /* clean the DMAE memory */
7113 bp->dmae_ready = 1;
619c5cb6
VZ		 7114 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7115
7116 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7117
7118 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7119
7120 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 7121
619c5cb6 7122 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 7123
34f80b04
EG		 7124 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7125 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7126 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7127 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7128
619c5cb6 7129 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 7130
523224a3
DK		 7131 /* QM queues pointers table */
7132 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7133
34f80b04
EG		 7134 /* soft reset pulse */
7135 REG_WR(bp, QM_REG_SOFT_RESET, 1);
7136 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 7137
55c11941
MS		 7138 if (CNIC_SUPPORT(bp))
7139 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 7140
619c5cb6 7141 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
b9871bcf 7142
619c5cb6 7143 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 7144 /* enable hw interrupt from doorbell Q */
7145 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 7146
619c5cb6 7147 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 7148
619c5cb6 7149 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 7150 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 7151
f2e0899f 7152 if (!CHIP_IS_E1(bp))
619c5cb6 7153 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 7154
a3348722
BW		 7155 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7156 if (IS_MF_AFEX(bp)) {
7157 /* configure that VNTag and VLAN headers must be
7158 * received in afex mode
7159 */
7160 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7161 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7162 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7163 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7164 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7165 } else {
7166 /* Bit-map indicating which L2 hdrs may appear
7167 * after the basic Ethernet header
7168 */
7169 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7170 bp->path_has_ovlan ? 7 : 6);
7171 }
7172 }
a2fbb9ea 7173
619c5cb6
VZ		 7174 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7175 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7176 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7177 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 7178
619c5cb6
VZ		 7179 if (!CHIP_IS_E1x(bp)) {
7180 /* reset VFC memories */
7181 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7182 VFC_MEMORIES_RST_REG_CAM_RST |
7183 VFC_MEMORIES_RST_REG_RAM_RST);
7184 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7185 VFC_MEMORIES_RST_REG_CAM_RST |
7186 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 7187
619c5cb6
VZ		 7188 msleep(20);
7189 }
a2fbb9ea 7190
619c5cb6
VZ		 7191 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7192 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7193 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7194 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 7195
34f80b04
EG		 7196 /* sync semi rtc */
7197 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7198 0x80000000);
7199 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7200 0x80000000);
a2fbb9ea 7201
619c5cb6
VZ		 7202 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7203 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7204 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 7205
a3348722
BW		 7206 if (!CHIP_IS_E1x(bp)) {
7207 if (IS_MF_AFEX(bp)) {
7208 /* configure that VNTag and VLAN headers must be
7209 * sent in afex mode
7210 */
7211 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7212 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7213 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7214 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7215 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7216 } else {
7217 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7218 bp->path_has_ovlan ? 7 : 6);
7219 }
7220 }
f2e0899f 7221
34f80b04 7222 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 7223
619c5cb6
VZ		 7224 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7225
55c11941
MS		 7226 if (CNIC_SUPPORT(bp)) {
7227 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7228 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7229 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7230 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7231 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7232 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7233 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7234 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7235 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7236 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7237 }
34f80b04 7238 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 7239
34f80b04
EG		 7240 if (sizeof(union cdu_context) != 1024)
7241 /* we currently assume that a context is 1024 bytes */
51c1a580
MS		 7242 dev_alert(&bp->pdev->dev,
7243 "please adjust the size of cdu_context(%ld)\n",
7244 (long)sizeof(union cdu_context));
a2fbb9ea 7245
619c5cb6 7246 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 7247 val = (4 << 24) + (0 << 12) + 1024;
7248 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 7249
619c5cb6 7250 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 7251 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 7252 /* enable context validation interrupt from CFC */
7253 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7254
7255 /* set the thresholds to prevent CFC/CDU race */
7256 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 7257
619c5cb6 7258 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 7259
619c5cb6 7260 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 7261 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7262
619c5cb6
VZ		 7263 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7264 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 7265
34f80b04
EG		 7266 /* Reset PCIE errors for debug */
7267 REG_WR(bp, 0x2814, 0xffffffff);
7268 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 7269
619c5cb6 7270 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7271 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7272 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7273 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7274 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7275 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7276 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7277 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7278 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7279 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7280 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7281 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7282 }
7283
619c5cb6 7284 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 7285 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 7286 /* in E3 this done in per-port section */
7287 if (!CHIP_IS_E3(bp))
7288 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 7289 }
619c5cb6
VZ		 7290 if (CHIP_IS_E1H(bp))
7291 /* not applicable for E2 (and above ...) */
7292 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 7293
7294 if (CHIP_REV_IS_SLOW(bp))
7295 msleep(200);
7296
7297 /* finish CFC init */
7298 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7299 if (val != 1) {
7300 BNX2X_ERR("CFC LL_INIT failed\n");
7301 return -EBUSY;
7302 }
7303 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7304 if (val != 1) {
7305 BNX2X_ERR("CFC AC_INIT failed\n");
7306 return -EBUSY;
7307 }
7308 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7309 if (val != 1) {
7310 BNX2X_ERR("CFC CAM_INIT failed\n");
7311 return -EBUSY;
7312 }
7313 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 7314
f2e0899f
DK		 7315 if (CHIP_IS_E1(bp)) {
7316 /* read NIG statistic
7317 to see if this is our first up since powerup */
7318 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7319 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 7320
f2e0899f
DK		 7321 /* do internal memory self test */
7322 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7323 BNX2X_ERR("internal mem self test failed\n");
7324 return -EBUSY;
7325 }
34f80b04
EG		 7326 }
7327
fd4ef40d
EG		 7328 bnx2x_setup_fan_failure_detection(bp);
7329
34f80b04
EG		 7330 /* clear PXP2 attentions */
7331 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 7332
4a33bc03 7333 bnx2x_enable_blocks_attention(bp);
c9ee9206 7334 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 7335
6bbca910 7336 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 7337 if (CHIP_IS_E1x(bp))
7338 bnx2x__common_init_phy(bp);
6bbca910
YR		 7339 } else
7340 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7341
34f80b04
EG		 7342 return 0;
7343}
a2fbb9ea 7344
619c5cb6
VZ		 7345/**
7346 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7347 *
7348 * @bp: driver handle
7349 */
7350static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7351{
7352 int rc = bnx2x_init_hw_common(bp);
7353
7354 if (rc)
7355 return rc;
7356
7357 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7358 if (!BP_NOMCP(bp))
7359 bnx2x__common_init_phy(bp);
7360
7361 return 0;
7362}
7363
523224a3 7364static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 7365{
7366 int port = BP_PORT(bp);
619c5cb6 7367 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 7368 u32 low, high;
4293b9f5 7369 u32 val, reg;
a2fbb9ea 7370
51c1a580 7371 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
34f80b04
EG		 7372
7373 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 7374
619c5cb6
VZ		 7375 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7376 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7377 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 7378
f2e0899f
DK		 7379 /* Timers bug workaround: disables the pf_master bit in pglue at
7380 * common phase, we need to enable it here before any dmae access are
7381 * attempted. Therefore we manually added the enable-master to the
7382 * port phase (it also happens in the function phase)
7383 */
619c5cb6 7384 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7385 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7386
619c5cb6
VZ		 7387 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7388 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7389 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7390 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7391
7392 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7393 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7394 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7395 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 7396
523224a3
DK		 7397 /* QM cid (connection) count */
7398 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 7399
55c11941
MS		 7400 if (CNIC_SUPPORT(bp)) {
7401 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7402 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7403 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7404 }
cdaa7cb8 7405
619c5cb6 7406 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f 7407
2b674047
DK		 7408 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7409
f2e0899f 7410 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 7411
7412 if (IS_MF(bp))
7413 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7414 else if (bp->dev->mtu > 4096) {
7415 if (bp->flags & ONE_PORT_FLAG)
7416 low = 160;
7417 else {
7418 val = bp->dev->mtu;
7419 /* (24*1024 + val*4)/256 */
7420 low = 96 + (val/64) +
7421 ((val % 64) ? 1 : 0);
7422 }
7423 } else
7424 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7425 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 7426 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7427 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 7428 }
1c06328c 7429
619c5cb6
VZ		 7430 if (CHIP_MODE_IS_4_PORT(bp))
7431 REG_WR(bp, (BP_PORT(bp) ?
7432 BRB1_REG_MAC_GUARANTIED_1 :
7433 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 7434
619c5cb6 7435 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
a3348722
BW		 7436 if (CHIP_IS_E3B0(bp)) {
7437 if (IS_MF_AFEX(bp)) {
7438 /* configure headers for AFEX mode */
7439 REG_WR(bp, BP_PORT(bp) ?
7440 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7441 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7442 REG_WR(bp, BP_PORT(bp) ?
7443 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7444 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7445 REG_WR(bp, BP_PORT(bp) ?
7446 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7447 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7448 } else {
7449 /* Ovlan exists only if we are in multi-function +
7450 * switch-dependent mode, in switch-independent there
7451 * is no ovlan headers
7452 */
7453 REG_WR(bp, BP_PORT(bp) ?
7454 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7455 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7456 (bp->path_has_ovlan ? 7 : 6));
7457 }
7458 }
356e2385 7459
619c5cb6
VZ		 7460 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7461 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7462 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7463 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 7464
619c5cb6
VZ		 7465 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7466 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7467 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7468 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 7469
619c5cb6
VZ		 7470 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7471 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 7472
619c5cb6
VZ		 7473 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7474
7475 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7476 /* configure PBF to work without PAUSE mtu 9000 */
7477 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 7478
f2e0899f
DK		 7479 /* update threshold */
7480 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7481 /* update init credit */
7482 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 7483
f2e0899f
DK		 7484 /* probe changes */
7485 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7486 udelay(50);
7487 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7488 }
a2fbb9ea 7489
55c11941
MS		 7490 if (CNIC_SUPPORT(bp))
7491 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7492
619c5cb6
VZ		 7493 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7494 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 7495
7496 if (CHIP_IS_E1(bp)) {
7497 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7498 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7499 }
619c5cb6 7500 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 7501
619c5cb6 7502 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7503
619c5cb6 7504 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04 7505 /* init aeu_mask_attn_func_0/1:
16a5fd92
YM		 7506 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7507 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
34f80b04 7508 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 7509 val = IS_MF(bp) ? 0xF7 : 0x7;
7510 /* Enable DCBX attention for all but E1 */
7511 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7512 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 7513
4293b9f5
DK		 7514 /* SCPAD_PARITY should NOT trigger close the gates */
7515 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7516 REG_WR(bp, reg,
7517 REG_RD(bp, reg) &
7518 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7519
7520 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7521 REG_WR(bp, reg,
7522 REG_RD(bp, reg) &
7523 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7524
619c5cb6
VZ		 7525 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7526
7527 if (!CHIP_IS_E1x(bp)) {
7528 /* Bit-map indicating which L2 hdrs may appear after the
7529 * basic Ethernet header
7530 */
a3348722
BW		 7531 if (IS_MF_AFEX(bp))
7532 REG_WR(bp, BP_PORT(bp) ?
7533 NIG_REG_P1_HDRS_AFTER_BASIC :
7534 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7535 else
7536 REG_WR(bp, BP_PORT(bp) ?
7537 NIG_REG_P1_HDRS_AFTER_BASIC :
7538 NIG_REG_P0_HDRS_AFTER_BASIC,
7539 IS_MF_SD(bp) ? 7 : 6);
619c5cb6
VZ		 7540
7541 if (CHIP_IS_E3(bp))
7542 REG_WR(bp, BP_PORT(bp) ?
7543 NIG_REG_LLH1_MF_MODE :
7544 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7545 }
7546 if (!CHIP_IS_E3(bp))
7547 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 7548
f2e0899f 7549 if (!CHIP_IS_E1(bp)) {
fb3bff17 7550 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 7551 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 7552 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 7553
619c5cb6 7554 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7555 val = 0;
7556 switch (bp->mf_mode) {
7557 case MULTI_FUNCTION_SD:
7558 val = 1;
7559 break;
7560 case MULTI_FUNCTION_SI:
a3348722 7561 case MULTI_FUNCTION_AFEX:
f2e0899f
DK		 7562 val = 2;
7563 break;
7564 }
7565
7566 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7567 NIG_REG_LLH0_CLS_TYPE), val);
7568 }
1c06328c
EG		 7569 {
7570 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7571 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7572 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7573 }
34f80b04
EG		 7574 }
7575
619c5cb6
VZ		 7576 /* If SPIO5 is set to generate interrupts, enable it for this port */
7577 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 7578 if (val & MISC_SPIO_SPIO5) {
4d295db0
EG		 7579 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7580 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7581 val = REG_RD(bp, reg_addr);
f1410647 7582 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 7583 REG_WR(bp, reg_addr, val);
f1410647 7584 }
a2fbb9ea 7585
34f80b04
EG		 7586 return 0;
7587}
7588
34f80b04
EG		 7589static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7590{
7591 int reg;
32d68de1 7592 u32 wb_write[2];
34f80b04 7593
f2e0899f 7594 if (CHIP_IS_E1(bp))
34f80b04 7595 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 7596 else
7597 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04 7598
32d68de1
YM		 7599 wb_write[0] = ONCHIP_ADDR1(addr);
7600 wb_write[1] = ONCHIP_ADDR2(addr);
7601 REG_WR_DMAE(bp, reg, wb_write, 2);
34f80b04
EG		 7602}
7603
b56e9670 7604void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
1191cb83
ED		 7605{
7606 u32 data, ctl, cnt = 100;
7607 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7608 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7609 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7610 u32 sb_bit = 1 << (idu_sb_id%32);
b56e9670 7611 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
1191cb83
ED		 7612 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7613
7614 /* Not supported in BC mode */
7615 if (CHIP_INT_MODE_IS_BC(bp))
7616 return;
7617
7618 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7619 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7620 IGU_REGULAR_CLEANUP_SET |
7621 IGU_REGULAR_BCLEANUP;
7622
7623 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7624 func_encode << IGU_CTRL_REG_FID_SHIFT |
7625 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7626
7627 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7628 data, igu_addr_data);
7629 REG_WR(bp, igu_addr_data, data);
7630 mmiowb();
7631 barrier();
7632 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7633 ctl, igu_addr_ctl);
7634 REG_WR(bp, igu_addr_ctl, ctl);
7635 mmiowb();
7636 barrier();
7637
7638 /* wait for clean up to finish */
7639 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7640 msleep(20);
7641
1191cb83
ED		 7642 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7643 DP(NETIF_MSG_HW,
7644 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7645 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7646 }
7647}
7648
7649static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
f2e0899f 7650{
619c5cb6 7651 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 7652}
7653
1191cb83 7654static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
f2e0899f
DK		 7655{
7656 u32 i, base = FUNC_ILT_BASE(func);
7657 for (i = base; i < base + ILT_PER_FUNC; i++)
7658 bnx2x_ilt_wr(bp, i, 0);
7659}
7660
910cc727 7661static void bnx2x_init_searcher(struct bnx2x *bp)
55c11941
MS		 7662{
7663 int port = BP_PORT(bp);
7664 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7665 /* T1 hash bits value determines the T1 number of entries */
7666 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7667}
7668
7669static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7670{
7671 int rc;
7672 struct bnx2x_func_state_params func_params = {NULL};
7673 struct bnx2x_func_switch_update_params *switch_update_params =
7674 &func_params.params.switch_update;
7675
7676 /* Prepare parameters for function state transitions */
7677 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7678 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7679
7680 func_params.f_obj = &bp->func_obj;
7681 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7682
7683 /* Function parameters */
e42780b6
DK		 7684 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7685 &switch_update_params->changes);
7686 if (suspend)
7687 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7688 &switch_update_params->changes);
55c11941
MS		 7689
7690 rc = bnx2x_func_state_change(bp, &func_params);
7691
7692 return rc;
7693}
7694
910cc727 7695static int bnx2x_reset_nic_mode(struct bnx2x *bp)
55c11941
MS		 7696{
7697 int rc, i, port = BP_PORT(bp);
7698 int vlan_en = 0, mac_en[NUM_MACS];
7699
55c11941
MS		 7700 /* Close input from network */
7701 if (bp->mf_mode == SINGLE_FUNCTION) {
7702 bnx2x_set_rx_filter(&bp->link_params, 0);
7703 } else {
7704 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7705 NIG_REG_LLH0_FUNC_EN);
7706 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7707 NIG_REG_LLH0_FUNC_EN, 0);
7708 for (i = 0; i < NUM_MACS; i++) {
7709 mac_en[i] = REG_RD(bp, port ?
7710 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7711 4 * i) :
7712 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7713 4 * i));
7714 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7715 4 * i) :
7716 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7717 }
7718 }
7719
7720 /* Close BMC to host */
7721 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7722 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7723
7724 /* Suspend Tx switching to the PF. Completion of this ramrod
7725 * further guarantees that all the packets of that PF / child
7726 * VFs in BRB were processed by the Parser, so it is safe to
7727 * change the NIC_MODE register.
7728 */
7729 rc = bnx2x_func_switch_update(bp, 1);
7730 if (rc) {
7731 BNX2X_ERR("Can't suspend tx-switching!\n");
7732 return rc;
7733 }
7734
7735 /* Change NIC_MODE register */
7736 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7737
7738 /* Open input from network */
7739 if (bp->mf_mode == SINGLE_FUNCTION) {
7740 bnx2x_set_rx_filter(&bp->link_params, 1);
7741 } else {
7742 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7743 NIG_REG_LLH0_FUNC_EN, vlan_en);
7744 for (i = 0; i < NUM_MACS; i++) {
7745 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7746 4 * i) :
7747 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7748 mac_en[i]);
7749 }
7750 }
7751
7752 /* Enable BMC to host */
7753 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7754 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7755
7756 /* Resume Tx switching to the PF */
7757 rc = bnx2x_func_switch_update(bp, 0);
7758 if (rc) {
7759 BNX2X_ERR("Can't resume tx-switching!\n");
7760 return rc;
7761 }
7762
7763 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7764 return 0;
7765}
7766
7767int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7768{
7769 int rc;
7770
7771 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7772
7773 if (CONFIGURE_NIC_MODE(bp)) {
16a5fd92 7774 /* Configure searcher as part of function hw init */
55c11941
MS		 7775 bnx2x_init_searcher(bp);
7776
7777 /* Reset NIC mode */
7778 rc = bnx2x_reset_nic_mode(bp);
7779 if (rc)
7780 BNX2X_ERR("Can't change NIC mode!\n");
7781 return rc;
7782 }
7783
7784 return 0;
7785}
7786
523224a3 7787static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 7788{
7789 int port = BP_PORT(bp);
7790 int func = BP_FUNC(bp);
619c5cb6 7791 int init_phase = PHASE_PF0 + func;
523224a3
DK		 7792 struct bnx2x_ilt *ilt = BP_ILT(bp);
7793 u16 cdu_ilt_start;
8badd27a 7794 u32 addr, val;
f4a66897 7795 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
89db4ad8 7796 int i, main_mem_width, rc;
34f80b04 7797
51c1a580 7798 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
34f80b04 7799
619c5cb6 7800 /* FLR cleanup - hmmm */
89db4ad8
AE		 7801 if (!CHIP_IS_E1x(bp)) {
7802 rc = bnx2x_pf_flr_clnup(bp);
04c46736
YM		 7803 if (rc) {
7804 bnx2x_fw_dump(bp);
89db4ad8 7805 return rc;
04c46736 7806 }
89db4ad8 7807 }
619c5cb6 7808
8badd27a 7809 /* set MSI reconfigure capability */
f2e0899f
DK		 7810 if (bp->common.int_block == INT_BLOCK_HC) {
7811 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7812 val = REG_RD(bp, addr);
7813 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7814 REG_WR(bp, addr, val);
7815 }
8badd27a 7816
619c5cb6
VZ		 7817 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7818 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7819
523224a3
DK		 7820 ilt = BP_ILT(bp);
7821 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 7822
290ca2bb
AE		 7823 if (IS_SRIOV(bp))
7824 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7825 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7826
7827 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7828 * those of the VFs, so start line should be reset
7829 */
7830 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
523224a3 7831 for (i = 0; i < L2_ILT_LINES(bp); i++) {
a052997e 7832 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
523224a3 7833 ilt->lines[cdu_ilt_start + i].page_mapping =
a052997e
MS		 7834 bp->context[i].cxt_mapping;
7835 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
37b091ba 7836 }
290ca2bb 7837
523224a3 7838 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 7839
55c11941
MS		 7840 if (!CONFIGURE_NIC_MODE(bp)) {
7841 bnx2x_init_searcher(bp);
7842 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7843 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7844 } else {
7845 /* Set NIC mode */
7846 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6bf07b8e 7847 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
55c11941 7848 }
37b091ba 7849
619c5cb6 7850 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7851 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7852
7853 /* Turn on a single ISR mode in IGU if driver is going to use
7854 * INT#x or MSI
7855 */
7856 if (!(bp->flags & USING_MSIX_FLAG))
7857 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7858 /*
7859 * Timers workaround bug: function init part.
7860 * Need to wait 20msec after initializing ILT,
7861 * needed to make sure there are no requests in
7862 * one of the PXP internal queues with "old" ILT addresses
7863 */
7864 msleep(20);
7865 /*
7866 * Master enable - Due to WB DMAE writes performed before this
7867 * register is re-initialized as part of the regular function
7868 * init
7869 */
7870 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7871 /* Enable the function in IGU */
7872 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7873 }
7874
523224a3 7875 bp->dmae_ready = 1;
34f80b04 7876
619c5cb6 7877 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 7878
619c5cb6 7879 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7880 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7881
619c5cb6
VZ		 7882 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7883 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7884 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7885 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7886 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7887 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7888 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7889 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7890 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7891 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7892 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7893 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7894 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7895
7896 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7897 REG_WR(bp, QM_REG_PF_EN, 1);
7898
619c5cb6
VZ		 7899 if (!CHIP_IS_E1x(bp)) {
7900 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7901 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7902 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7903 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7904 }
7905 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7906
7907 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7908 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
c19d65c9 7909 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
b56e9670
AE		 7910
7911 bnx2x_iov_init_dq(bp);
7912
619c5cb6
VZ		 7913 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7914 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7915 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7916 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7917 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7918 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7919 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7920 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7921 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7922 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7923 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7924
619c5cb6 7925 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 7926
619c5cb6 7927 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 7928
619c5cb6 7929 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7930 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7931
fb3bff17 7932 if (IS_MF(bp)) {
34f80b04 7933 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 7934 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 7935 }
7936
619c5cb6 7937 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 7938
34f80b04 7939 /* HC init per function */
f2e0899f
DK		 7940 if (bp->common.int_block == INT_BLOCK_HC) {
7941 if (CHIP_IS_E1H(bp)) {
7942 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7943
7944 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7945 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7946 }
619c5cb6 7947 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 7948
7949 } else {
7950 int num_segs, sb_idx, prod_offset;
7951
34f80b04
EG		 7952 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7953
619c5cb6 7954 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7955 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7956 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7957 }
7958
619c5cb6 7959 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7960
619c5cb6 7961 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7962 int dsb_idx = 0;
7963 /**
7964 * Producer memory:
7965 * E2 mode: address 0-135 match to the mapping memory;
7966 * 136 - PF0 default prod; 137 - PF1 default prod;
7967 * 138 - PF2 default prod; 139 - PF3 default prod;
7968 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7969 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7970 * 144-147 reserved.
7971 *
7972 * E1.5 mode - In backward compatible mode;
7973 * for non default SB; each even line in the memory
7974 * holds the U producer and each odd line hold
7975 * the C producer. The first 128 producers are for
7976 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7977 * producers are for the DSB for each PF.
7978 * Each PF has five segments: (the order inside each
7979 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7980 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7981 * 144-147 attn prods;
7982 */
7983 /* non-default-status-blocks */
7984 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7985 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7986 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7987 prod_offset = (bp->igu_base_sb + sb_idx) *
7988 num_segs;
7989
7990 for (i = 0; i < num_segs; i++) {
7991 addr = IGU_REG_PROD_CONS_MEMORY +
7992 (prod_offset + i) * 4;
7993 REG_WR(bp, addr, 0);
7994 }
7995 /* send consumer update with value 0 */
7996 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7997 USTORM_ID, 0, IGU_INT_NOP, 1);
7998 bnx2x_igu_clear_sb(bp,
7999 bp->igu_base_sb + sb_idx);
8000 }
8001
8002 /* default-status-blocks */
8003 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8004 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8005
8006 if (CHIP_MODE_IS_4_PORT(bp))
8007 dsb_idx = BP_FUNC(bp);
8008 else
3395a033 8009 dsb_idx = BP_VN(bp);
f2e0899f
DK		 8010
8011 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8012 IGU_BC_BASE_DSB_PROD + dsb_idx :
8013 IGU_NORM_BASE_DSB_PROD + dsb_idx);
8014
3395a033
DK		 8015 /*
8016 * igu prods come in chunks of E1HVN_MAX (4) -
8017 * does not matters what is the current chip mode
8018 */
f2e0899f
DK		 8019 for (i = 0; i < (num_segs * E1HVN_MAX);
8020 i += E1HVN_MAX) {
8021 addr = IGU_REG_PROD_CONS_MEMORY +
8022 (prod_offset + i)*4;
8023 REG_WR(bp, addr, 0);
8024 }
8025 /* send consumer update with 0 */
8026 if (CHIP_INT_MODE_IS_BC(bp)) {
8027 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8028 USTORM_ID, 0, IGU_INT_NOP, 1);
8029 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8030 CSTORM_ID, 0, IGU_INT_NOP, 1);
8031 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8032 XSTORM_ID, 0, IGU_INT_NOP, 1);
8033 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8034 TSTORM_ID, 0, IGU_INT_NOP, 1);
8035 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8036 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8037 } else {
8038 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8039 USTORM_ID, 0, IGU_INT_NOP, 1);
8040 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8041 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8042 }
8043 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8044
16a5fd92 8045 /* !!! These should become driver const once
f2e0899f
DK		 8046 rf-tool supports split-68 const */
8047 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8048 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8049 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8050 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8051 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8052 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8053 }
34f80b04 8054 }
34f80b04 8055
c14423fe 8056 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 8057 REG_WR(bp, 0x2114, 0xffffffff);
8058 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 8059
f4a66897
VZ		 8060 if (CHIP_IS_E1x(bp)) {
8061 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8062 main_mem_base = HC_REG_MAIN_MEMORY +
8063 BP_PORT(bp) * (main_mem_size * 4);
8064 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8065 main_mem_width = 8;
8066
8067 val = REG_RD(bp, main_mem_prty_clr);
8068 if (val)
51c1a580
MS		 8069 DP(NETIF_MSG_HW,
8070 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8071 val);
f4a66897
VZ		 8072
8073 /* Clear "false" parity errors in MSI-X table */
8074 for (i = main_mem_base;
8075 i < main_mem_base + main_mem_size * 4;
8076 i += main_mem_width) {
8077 bnx2x_read_dmae(bp, i, main_mem_width / 4);
8078 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8079 i, main_mem_width / 4);
8080 }
8081 /* Clear HC parity attention */
8082 REG_RD(bp, main_mem_prty_clr);
8083 }
8084
619c5cb6
VZ		 8085#ifdef BNX2X_STOP_ON_ERROR
8086 /* Enable STORMs SP logging */
8087 REG_WR8(bp, BAR_USTRORM_INTMEM +
8088 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8089 REG_WR8(bp, BAR_TSTRORM_INTMEM +
8090 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8091 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8092 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8093 REG_WR8(bp, BAR_XSTRORM_INTMEM +
8094 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8095#endif
8096
b7737c9b 8097 bnx2x_phy_probe(&bp->link_params);
f85582f8 8098
34f80b04
EG		 8099 return 0;
8100}
8101
55c11941
MS		 8102void bnx2x_free_mem_cnic(struct bnx2x *bp)
8103{
8104 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8105
8106 if (!CHIP_IS_E1x(bp))
8107 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8108 sizeof(struct host_hc_status_block_e2));
8109 else
8110 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8111 sizeof(struct host_hc_status_block_e1x));
8112
8113 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8114}
8115
9f6c9258 8116void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 8117{
a052997e
MS		 8118 int i;
8119
619c5cb6
VZ		 8120 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8121 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8122
b4cddbd6
AE		 8123 if (IS_VF(bp))
8124 return;
8125
8126 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8127 sizeof(struct host_sp_status_block));
8128
a2fbb9ea 8129 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 8130 sizeof(struct bnx2x_slowpath));
a2fbb9ea 8131
a052997e
MS		 8132 for (i = 0; i < L2_ILT_LINES(bp); i++)
8133 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8134 bp->context[i].size);
523224a3
DK		 8135 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8136
8137 BNX2X_FREE(bp->ilt->lines);
f85582f8 8138
7a9b2557 8139 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 8140
523224a3
DK		 8141 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8142 BCM_PAGE_SIZE * NUM_EQ_PAGES);
580d9d08 8143
05952246
YM		 8144 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8145
580d9d08 8146 bnx2x_iov_free_mem(bp);
619c5cb6
VZ		 8147}
8148
55c11941 8149int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
a2fbb9ea 8150{
cd2b0389 8151 if (!CHIP_IS_E1x(bp)) {
619c5cb6 8152 /* size = the status block + ramrod buffers */
cd2b0389
JP		 8153 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8154 sizeof(struct host_hc_status_block_e2));
8155 if (!bp->cnic_sb.e2_sb)
8156 goto alloc_mem_err;
8157 } else {
8158 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8159 sizeof(struct host_hc_status_block_e1x));
8160 if (!bp->cnic_sb.e1x_sb)
8161 goto alloc_mem_err;
8162 }
8badd27a 8163
cd2b0389 8164 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
16a5fd92 8165 /* allocate searcher T2 table, as it wasn't allocated before */
cd2b0389
JP		 8166 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8167 if (!bp->t2)
8168 goto alloc_mem_err;
8169 }
55c11941
MS		 8170
8171 /* write address to which L5 should insert its values */
8172 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8173 &bp->slowpath->drv_info_to_mcp;
8174
8175 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8176 goto alloc_mem_err;
8177
8178 return 0;
8179
8180alloc_mem_err:
8181 bnx2x_free_mem_cnic(bp);
8182 BNX2X_ERR("Can't allocate memory\n");
8183 return -ENOMEM;
8184}
8185
8186int bnx2x_alloc_mem(struct bnx2x *bp)
8187{
8188 int i, allocated, context_size;
a2fbb9ea 8189
cd2b0389 8190 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
55c11941 8191 /* allocate searcher T2 table */
cd2b0389
JP		 8192 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8193 if (!bp->t2)
8194 goto alloc_mem_err;
8195 }
8badd27a 8196
cd2b0389
JP		 8197 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8198 sizeof(struct host_sp_status_block));
8199 if (!bp->def_status_blk)
8200 goto alloc_mem_err;
a2fbb9ea 8201
cd2b0389
JP		 8202 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8203 sizeof(struct bnx2x_slowpath));
8204 if (!bp->slowpath)
8205 goto alloc_mem_err;
a2fbb9ea 8206
a052997e
MS		 8207 /* Allocate memory for CDU context:
8208 * This memory is allocated separately and not in the generic ILT
8209 * functions because CDU differs in few aspects:
8210 * 1. There are multiple entities allocating memory for context -
8211 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8212 * its own ILT lines.
8213 * 2. Since CDU page-size is not a single 4KB page (which is the case
8214 * for the other ILT clients), to be efficient we want to support
8215 * allocation of sub-page-size in the last entry.
8216 * 3. Context pointers are used by the driver to pass to FW / update
8217 * the context (for the other ILT clients the pointers are used just to
8218 * free the memory during unload).
8219 */
8220 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
65abd74d 8221
a052997e
MS		 8222 for (i = 0, allocated = 0; allocated < context_size; i++) {
8223 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8224 (context_size - allocated));
cd2b0389
JP		 8225 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8226 bp->context[i].size);
8227 if (!bp->context[i].vcxt)
8228 goto alloc_mem_err;
a052997e
MS		 8229 allocated += bp->context[i].size;
8230 }
cd2b0389
JP		 8231 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8232 GFP_KERNEL);
8233 if (!bp->ilt->lines)
8234 goto alloc_mem_err;
65abd74d 8235
523224a3
DK		 8236 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8237 goto alloc_mem_err;
65abd74d 8238
67c431a5
AE		 8239 if (bnx2x_iov_alloc_mem(bp))
8240 goto alloc_mem_err;
8241
9f6c9258 8242 /* Slow path ring */
cd2b0389
JP		 8243 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8244 if (!bp->spq)
8245 goto alloc_mem_err;
65abd74d 8246
523224a3 8247 /* EQ */
cd2b0389
JP		 8248 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8249 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8250 if (!bp->eq_ring)
8251 goto alloc_mem_err;
ab532cf3 8252
9f6c9258 8253 return 0;
e1510706 8254
9f6c9258
DK		 8255alloc_mem_err:
8256 bnx2x_free_mem(bp);
51c1a580 8257 BNX2X_ERR("Can't allocate memory\n");
9f6c9258 8258 return -ENOMEM;
65abd74d
YG		 8259}
8260
a2fbb9ea
ET		 8261/*
8262 * Init service functions
8263 */
a2fbb9ea 8264
619c5cb6
VZ		 8265int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8266 struct bnx2x_vlan_mac_obj *obj, bool set,
8267 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 8268{
619c5cb6
VZ		 8269 int rc;
8270 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 8271
619c5cb6 8272 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 8273
619c5cb6
VZ		 8274 /* Fill general parameters */
8275 ramrod_param.vlan_mac_obj = obj;
8276 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 8277
619c5cb6
VZ		 8278 /* Fill a user request section if needed */
8279 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8280 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 8281
619c5cb6 8282 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 8283
619c5cb6
VZ		 8284 /* Set the command: ADD or DEL */
8285 if (set)
8286 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8287 else
8288 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 8289 }
8290
619c5cb6 8291 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7b5342d9
YM		 8292
8293 if (rc == -EEXIST) {
8294 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8295 /* do not treat adding same MAC as error */
8296 rc = 0;
8297 } else if (rc < 0)
619c5cb6 8298 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7b5342d9 8299
619c5cb6 8300 return rc;
a2fbb9ea
ET		 8301}
8302
619c5cb6
VZ		 8303int bnx2x_del_all_macs(struct bnx2x *bp,
8304 struct bnx2x_vlan_mac_obj *mac_obj,
8305 int mac_type, bool wait_for_comp)
e665bfda 8306{
619c5cb6
VZ		 8307 int rc;
8308 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 8309
619c5cb6
VZ		 8310 /* Wait for completion of requested */
8311 if (wait_for_comp)
8312 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 8313
619c5cb6
VZ		 8314 /* Set the mac type of addresses we want to clear */
8315 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 8316
619c5cb6
VZ		 8317 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8318 if (rc < 0)
8319 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 8320
619c5cb6 8321 return rc;
0793f83f
DK		 8322}
8323
619c5cb6 8324int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 8325{
f8f4f61a
DK		 8326 if (IS_PF(bp)) {
8327 unsigned long ramrod_flags = 0;
0793f83f 8328
f8f4f61a
DK		 8329 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8330 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8331 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8332 &bp->sp_objs->mac_obj, set,
8333 BNX2X_ETH_MAC, &ramrod_flags);
8334 } else { /* vf */
8335 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8336 bp->fp->index, true);
8337 }
e665bfda 8338}
6e30dd4e 8339
619c5cb6 8340int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 8341{
60cad4e6
AE		 8342 if (IS_PF(bp))
8343 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8344 else /* VF */
8345 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
993ac7b5 8346}
a2fbb9ea 8347
d6214d7a 8348/**
e8920674 8349 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 8350 *
e8920674 8351 * @bp: driver handle
d6214d7a 8352 *
e8920674 8353 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 8354 */
1ab4434c 8355int bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 8356{
1ab4434c
AE		 8357 int rc = 0;
8358
60cad4e6
AE		 8359 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8360 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
1ab4434c 8361 return -EINVAL;
60cad4e6 8362 }
1ab4434c 8363
9ee3d37b 8364 switch (int_mode) {
1ab4434c
AE		 8365 case BNX2X_INT_MODE_MSIX:
8366 /* attempt to enable msix */
8367 rc = bnx2x_enable_msix(bp);
8368
8369 /* msix attained */
8370 if (!rc)
8371 return 0;
8372
8373 /* vfs use only msix */
8374 if (rc && IS_VF(bp))
8375 return rc;
8376
8377 /* failed to enable multiple MSI-X */
8378 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8379 bp->num_queues,
8380 1 + bp->num_cnic_queues);
8381
8382 /* falling through... */
8383 case BNX2X_INT_MODE_MSI:
d6214d7a 8384 bnx2x_enable_msi(bp);
1ab4434c 8385
d6214d7a 8386 /* falling through... */
1ab4434c 8387 case BNX2X_INT_MODE_INTX:
55c11941
MS		 8388 bp->num_ethernet_queues = 1;
8389 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
51c1a580 8390 BNX2X_DEV_INFO("set number of queues to 1\n");
ca00392c 8391 break;
d6214d7a 8392 default:
1ab4434c
AE		 8393 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8394 return -EINVAL;
9f6c9258 8395 }
1ab4434c 8396 return 0;
a2fbb9ea
ET		 8397}
8398
1ab4434c 8399/* must be called prior to any HW initializations */
c2bff63f
DK		 8400static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8401{
290ca2bb
AE		 8402 if (IS_SRIOV(bp))
8403 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
c2bff63f
DK		 8404 return L2_ILT_LINES(bp);
8405}
8406
523224a3
DK		 8407void bnx2x_ilt_set_info(struct bnx2x *bp)
8408{
8409 struct ilt_client_info *ilt_client;
8410 struct bnx2x_ilt *ilt = BP_ILT(bp);
8411 u16 line = 0;
8412
8413 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8414 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8415
8416 /* CDU */
8417 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8418 ilt_client->client_num = ILT_CLIENT_CDU;
8419 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8420 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8421 ilt_client->start = line;
619c5cb6 8422 line += bnx2x_cid_ilt_lines(bp);
55c11941
MS		 8423
8424 if (CNIC_SUPPORT(bp))
8425 line += CNIC_ILT_LINES;
523224a3
DK		 8426 ilt_client->end = line - 1;
8427
51c1a580 8428 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8429 ilt_client->start,
8430 ilt_client->end,
8431 ilt_client->page_size,
8432 ilt_client->flags,
8433 ilog2(ilt_client->page_size >> 12));
8434
8435 /* QM */
8436 if (QM_INIT(bp->qm_cid_count)) {
8437 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8438 ilt_client->client_num = ILT_CLIENT_QM;
8439 ilt_client->page_size = QM_ILT_PAGE_SZ;
8440 ilt_client->flags = 0;
8441 ilt_client->start = line;
8442
8443 /* 4 bytes for each cid */
8444 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8445 QM_ILT_PAGE_SZ);
8446
8447 ilt_client->end = line - 1;
8448
51c1a580
MS		 8449 DP(NETIF_MSG_IFUP,
8450 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8451 ilt_client->start,
8452 ilt_client->end,
8453 ilt_client->page_size,
8454 ilt_client->flags,
8455 ilog2(ilt_client->page_size >> 12));
523224a3 8456 }
523224a3 8457
55c11941
MS		 8458 if (CNIC_SUPPORT(bp)) {
8459 /* SRC */
8460 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8461 ilt_client->client_num = ILT_CLIENT_SRC;
8462 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8463 ilt_client->flags = 0;
8464 ilt_client->start = line;
8465 line += SRC_ILT_LINES;
8466 ilt_client->end = line - 1;
523224a3 8467
55c11941
MS		 8468 DP(NETIF_MSG_IFUP,
8469 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8470 ilt_client->start,
8471 ilt_client->end,
8472 ilt_client->page_size,
8473 ilt_client->flags,
8474 ilog2(ilt_client->page_size >> 12));
9f6c9258 8475
55c11941
MS		 8476 /* TM */
8477 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8478 ilt_client->client_num = ILT_CLIENT_TM;
8479 ilt_client->page_size = TM_ILT_PAGE_SZ;
8480 ilt_client->flags = 0;
8481 ilt_client->start = line;
8482 line += TM_ILT_LINES;
8483 ilt_client->end = line - 1;
523224a3 8484
55c11941
MS		 8485 DP(NETIF_MSG_IFUP,
8486 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8487 ilt_client->start,
8488 ilt_client->end,
8489 ilt_client->page_size,
8490 ilt_client->flags,
8491 ilog2(ilt_client->page_size >> 12));
8492 }
9f6c9258 8493
619c5cb6 8494 BUG_ON(line > ILT_MAX_LINES);
523224a3 8495}
f85582f8 8496
619c5cb6
VZ		 8497/**
8498 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8499 *
8500 * @bp: driver handle
8501 * @fp: pointer to fastpath
8502 * @init_params: pointer to parameters structure
8503 *
8504 * parameters configured:
8505 * - HC configuration
8506 * - Queue's CDU context
8507 */
1191cb83 8508static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
619c5cb6 8509 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 8510{
6383c0b3 8511 u8 cos;
a052997e
MS		 8512 int cxt_index, cxt_offset;
8513
619c5cb6
VZ		 8514 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8515 if (!IS_FCOE_FP(fp)) {
8516 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8517 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8518
16a5fd92 8519 /* If HC is supported, enable host coalescing in the transition
619c5cb6
VZ		 8520 * to INIT state.
8521 */
8522 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8523 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8524
8525 /* HC rate */
8526 init_params->rx.hc_rate = bp->rx_ticks ?
8527 (1000000 / bp->rx_ticks) : 0;
8528 init_params->tx.hc_rate = bp->tx_ticks ?
8529 (1000000 / bp->tx_ticks) : 0;
8530
8531 /* FW SB ID */
8532 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8533 fp->fw_sb_id;
8534
8535 /*
8536 * CQ index among the SB indices: FCoE clients uses the default
8537 * SB, therefore it's different.
8538 */
6383c0b3
AE		 8539 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8540 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 8541 }
8542
6383c0b3
AE		 8543 /* set maximum number of COSs supported by this queue */
8544 init_params->max_cos = fp->max_cos;
8545
51c1a580 8546 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 8547 fp->index, init_params->max_cos);
8548
8549 /* set the context pointers queue object */
a052997e 8550 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
65565884
MS		 8551 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8552 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
a052997e 8553 ILT_PAGE_CIDS);
6383c0b3 8554 init_params->cxts[cos] =
a052997e
MS		 8555 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8556 }
619c5cb6
VZ		 8557}
8558
910cc727 8559static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6383c0b3
AE		 8560 struct bnx2x_queue_state_params *q_params,
8561 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8562 int tx_index, bool leading)
8563{
8564 memset(tx_only_params, 0, sizeof(*tx_only_params));
8565
8566 /* Set the command */
8567 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8568
8569 /* Set tx-only QUEUE flags: don't zero statistics */
8570 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8571
8572 /* choose the index of the cid to send the slow path on */
8573 tx_only_params->cid_index = tx_index;
8574
8575 /* Set general TX_ONLY_SETUP parameters */
8576 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8577
8578 /* Set Tx TX_ONLY_SETUP parameters */
8579 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8580
51c1a580
MS		 8581 DP(NETIF_MSG_IFUP,
8582 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 8583 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8584 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8585 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8586
8587 /* send the ramrod */
8588 return bnx2x_queue_state_change(bp, q_params);
8589}
8590
619c5cb6
VZ		 8591/**
8592 * bnx2x_setup_queue - setup queue
8593 *
8594 * @bp: driver handle
8595 * @fp: pointer to fastpath
8596 * @leading: is leading
8597 *
8598 * This function performs 2 steps in a Queue state machine
8599 * actually: 1) RESET->INIT 2) INIT->SETUP
8600 */
8601
8602int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8603 bool leading)
8604{
3b603066 8605 struct bnx2x_queue_state_params q_params = {NULL};
619c5cb6
VZ		 8606 struct bnx2x_queue_setup_params *setup_params =
8607 &q_params.params.setup;
6383c0b3
AE		 8608 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8609 &q_params.params.tx_only;
a2fbb9ea 8610 int rc;
6383c0b3
AE		 8611 u8 tx_index;
8612
51c1a580 8613 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
a2fbb9ea 8614
ec6ba945
VZ		 8615 /* reset IGU state skip FCoE L2 queue */
8616 if (!IS_FCOE_FP(fp))
8617 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 8618 IGU_INT_ENABLE, 0);
a2fbb9ea 8619
15192a8c 8620 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8621 /* We want to wait for completion in this context */
8622 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8623
619c5cb6
VZ		 8624 /* Prepare the INIT parameters */
8625 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 8626
619c5cb6
VZ		 8627 /* Set the command */
8628 q_params.cmd = BNX2X_Q_CMD_INIT;
8629
8630 /* Change the state to INIT */
8631 rc = bnx2x_queue_state_change(bp, &q_params);
8632 if (rc) {
6383c0b3 8633 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 8634 return rc;
8635 }
ec6ba945 8636
51c1a580 8637 DP(NETIF_MSG_IFUP, "init complete\n");
6383c0b3 8638
619c5cb6
VZ		 8639 /* Now move the Queue to the SETUP state... */
8640 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 8641
619c5cb6
VZ		 8642 /* Set QUEUE flags */
8643 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 8644
619c5cb6 8645 /* Set general SETUP parameters */
6383c0b3
AE		 8646 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8647 FIRST_TX_COS_INDEX);
619c5cb6 8648
6383c0b3 8649 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 8650 &setup_params->rxq_params);
8651
6383c0b3
AE		 8652 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8653 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 8654
8655 /* Set the command */
8656 q_params.cmd = BNX2X_Q_CMD_SETUP;
8657
55c11941
MS		 8658 if (IS_FCOE_FP(fp))
8659 bp->fcoe_init = true;
8660
619c5cb6
VZ		 8661 /* Change the state to SETUP */
8662 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 8663 if (rc) {
8664 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8665 return rc;
8666 }
8667
8668 /* loop through the relevant tx-only indices */
8669 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8670 tx_index < fp->max_cos;
8671 tx_index++) {
8672
8673 /* prepare and send tx-only ramrod*/
8674 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8675 tx_only_params, tx_index, leading);
8676 if (rc) {
8677 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8678 fp->index, tx_index);
8679 return rc;
8680 }
8681 }
523224a3 8682
34f80b04 8683 return rc;
a2fbb9ea
ET		 8684}
8685
619c5cb6 8686static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 8687{
619c5cb6 8688 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 8689 struct bnx2x_fp_txdata *txdata;
3b603066 8690 struct bnx2x_queue_state_params q_params = {NULL};
6383c0b3
AE		 8691 int rc, tx_index;
8692
51c1a580 8693 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 8694
15192a8c 8695 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8696 /* We want to wait for completion in this context */
8697 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8698
6383c0b3
AE		 8699 /* close tx-only connections */
8700 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8701 tx_index < fp->max_cos;
8702 tx_index++){
8703
8704 /* ascertain this is a normal queue*/
65565884 8705 txdata = fp->txdata_ptr[tx_index];
6383c0b3 8706
51c1a580 8707 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
6383c0b3
AE		 8708 txdata->txq_index);
8709
8710 /* send halt terminate on tx-only connection */
8711 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8712 memset(&q_params.params.terminate, 0,
8713 sizeof(q_params.params.terminate));
8714 q_params.params.terminate.cid_index = tx_index;
8715
8716 rc = bnx2x_queue_state_change(bp, &q_params);
8717 if (rc)
8718 return rc;
8719
8720 /* send halt terminate on tx-only connection */
8721 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8722 memset(&q_params.params.cfc_del, 0,
8723 sizeof(q_params.params.cfc_del));
8724 q_params.params.cfc_del.cid_index = tx_index;
8725 rc = bnx2x_queue_state_change(bp, &q_params);
8726 if (rc)
8727 return rc;
8728 }
8729 /* Stop the primary connection: */
8730 /* ...halt the connection */
619c5cb6
VZ		 8731 q_params.cmd = BNX2X_Q_CMD_HALT;
8732 rc = bnx2x_queue_state_change(bp, &q_params);
8733 if (rc)
da5a662a 8734 return rc;
a2fbb9ea 8735
6383c0b3 8736 /* ...terminate the connection */
619c5cb6 8737 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 8738 memset(&q_params.params.terminate, 0,
8739 sizeof(q_params.params.terminate));
8740 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 8741 rc = bnx2x_queue_state_change(bp, &q_params);
8742 if (rc)
523224a3 8743 return rc;
6383c0b3 8744 /* ...delete cfc entry */
619c5cb6 8745 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 8746 memset(&q_params.params.cfc_del, 0,
8747 sizeof(q_params.params.cfc_del));
8748 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 8749 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 8750}
8751
34f80b04
EG		 8752static void bnx2x_reset_func(struct bnx2x *bp)
8753{
8754 int port = BP_PORT(bp);
8755 int func = BP_FUNC(bp);
f2e0899f 8756 int i;
523224a3
DK		 8757
8758 /* Disable the function in the FW */
8759 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8760 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8761 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8762 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8763
8764 /* FP SBs */
ec6ba945 8765 for_each_eth_queue(bp, i) {
523224a3 8766 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 8767 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 8768 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8769 SB_DISABLED);
523224a3
DK		 8770 }
8771
55c11941
MS		 8772 if (CNIC_LOADED(bp))
8773 /* CNIC SB */
8774 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8775 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8776 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8777
523224a3 8778 /* SP SB */
619c5cb6 8779 REG_WR8(bp, BAR_CSTRORM_INTMEM +
2de67439
YM		 8780 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8781 SB_DISABLED);
523224a3
DK		 8782
8783 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8784 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8785 0);
34f80b04
EG		 8786
8787 /* Configure IGU */
f2e0899f
DK		 8788 if (bp->common.int_block == INT_BLOCK_HC) {
8789 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8790 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8791 } else {
8792 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8793 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8794 }
34f80b04 8795
55c11941
MS		 8796 if (CNIC_LOADED(bp)) {
8797 /* Disable Timer scan */
8798 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8799 /*
8800 * Wait for at least 10ms and up to 2 second for the timers
8801 * scan to complete
8802 */
8803 for (i = 0; i < 200; i++) {
639d65b8 8804 usleep_range(10000, 20000);
55c11941
MS		 8805 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8806 break;
8807 }
37b091ba 8808 }
34f80b04 8809 /* Clear ILT */
f2e0899f
DK		 8810 bnx2x_clear_func_ilt(bp, func);
8811
8812 /* Timers workaround bug for E2: if this is vnic-3,
8813 * we need to set the entire ilt range for this timers.
8814 */
619c5cb6 8815 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 8816 struct ilt_client_info ilt_cli;
8817 /* use dummy TM client */
8818 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8819 ilt_cli.start = 0;
8820 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8821 ilt_cli.client_num = ILT_CLIENT_TM;
8822
8823 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8824 }
8825
8826 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 8827 if (!CHIP_IS_E1x(bp))
f2e0899f 8828 bnx2x_pf_disable(bp);
523224a3
DK		 8829
8830 bp->dmae_ready = 0;
34f80b04
EG		 8831}
8832
8833static void bnx2x_reset_port(struct bnx2x *bp)
8834{
8835 int port = BP_PORT(bp);
8836 u32 val;
8837
619c5cb6
VZ		 8838 /* Reset physical Link */
8839 bnx2x__link_reset(bp);
8840
34f80b04
EG		 8841 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8842
8843 /* Do not rcv packets to BRB */
8844 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8845 /* Do not direct rcv packets that are not for MCP to the BRB */
8846 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8847 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8848
8849 /* Configure AEU */
8850 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8851
8852 msleep(100);
8853 /* Check for BRB port occupancy */
8854 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8855 if (val)
8856 DP(NETIF_MSG_IFDOWN,
33471629 8857 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 8858
8859 /* TODO: Close Doorbell port? */
8860}
8861
1191cb83 8862static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 8863{
3b603066 8864 struct bnx2x_func_state_params func_params = {NULL};
34f80b04 8865
619c5cb6
VZ		 8866 /* Prepare parameters for function state transitions */
8867 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 8868
619c5cb6
VZ		 8869 func_params.f_obj = &bp->func_obj;
8870 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 8871
619c5cb6 8872 func_params.params.hw_init.load_phase = load_code;
49d66772 8873
619c5cb6 8874 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 8875}
8876
1191cb83 8877static int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 8878{
3b603066 8879 struct bnx2x_func_state_params func_params = {NULL};
619c5cb6 8880 int rc;
228241eb 8881
619c5cb6
VZ		 8882 /* Prepare parameters for function state transitions */
8883 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8884 func_params.f_obj = &bp->func_obj;
8885 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 8886
619c5cb6
VZ		 8887 /*
8888 * Try to stop the function the 'good way'. If fails (in case
8889 * of a parity error during bnx2x_chip_cleanup()) and we are
8890 * not in a debug mode, perform a state transaction in order to
8891 * enable further HW_RESET transaction.
8892 */
8893 rc = bnx2x_func_state_change(bp, &func_params);
8894 if (rc) {
34f80b04 8895#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 8896 return rc;
34f80b04 8897#else
51c1a580 8898 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
619c5cb6
VZ		 8899 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8900 return bnx2x_func_state_change(bp, &func_params);
34f80b04 8901#endif
228241eb 8902 }
a2fbb9ea 8903
619c5cb6
VZ		 8904 return 0;
8905}
523224a3 8906
619c5cb6
VZ		 8907/**
8908 * bnx2x_send_unload_req - request unload mode from the MCP.
8909 *
8910 * @bp: driver handle
8911 * @unload_mode: requested function's unload mode
8912 *
8913 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8914 */
8915u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8916{
8917 u32 reset_code = 0;
8918 int port = BP_PORT(bp);
3101c2bc 8919
619c5cb6 8920 /* Select the UNLOAD request mode */
65abd74d
YG		 8921 if (unload_mode == UNLOAD_NORMAL)
8922 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8923
7d0446c2 8924 else if (bp->flags & NO_WOL_FLAG)
65abd74d 8925 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 8926
7d0446c2 8927 else if (bp->wol) {
65abd74d
YG		 8928 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8929 u8 *mac_addr = bp->dev->dev_addr;
29ed74c3 8930 struct pci_dev *pdev = bp->pdev;
65abd74d 8931 u32 val;
f9977903
DK		 8932 u16 pmc;
8933
65abd74d 8934 /* The mac address is written to entries 1-4 to
f9977903
DK		 8935 * preserve entry 0 which is used by the PMF
8936 */
3395a033 8937 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 8938
8939 val = (mac_addr[0] << 8) | mac_addr[1];
8940 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8941
8942 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8943 (mac_addr[4] << 8) | mac_addr[5];
8944 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8945
f9977903 8946 /* Enable the PME and clear the status */
29ed74c3 8947 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
f9977903 8948 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
29ed74c3 8949 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
f9977903 8950
65abd74d
YG		 8951 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8952
8953 } else
8954 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 8955
619c5cb6
VZ		 8956 /* Send the request to the MCP */
8957 if (!BP_NOMCP(bp))
8958 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8959 else {
8960 int path = BP_PATH(bp);
8961
51c1a580 8962 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
a8f47eb7 8963 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8964 bnx2x_load_count[path][2]);
8965 bnx2x_load_count[path][0]--;
8966 bnx2x_load_count[path][1 + port]--;
51c1a580 8967 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
a8f47eb7 8968 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8969 bnx2x_load_count[path][2]);
8970 if (bnx2x_load_count[path][0] == 0)
619c5cb6 8971 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
a8f47eb7 8972 else if (bnx2x_load_count[path][1 + port] == 0)
619c5cb6
VZ		 8973 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8974 else
8975 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8976 }
8977
8978 return reset_code;
8979}
8980
8981/**
8982 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8983 *
8984 * @bp: driver handle
5d07d868 8985 * @keep_link: true iff link should be kept up
619c5cb6 8986 */
5d07d868 8987void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
619c5cb6 8988{
5d07d868
YM		 8989 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8990
619c5cb6
VZ		 8991 /* Report UNLOAD_DONE to MCP */
8992 if (!BP_NOMCP(bp))
5d07d868 8993 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
619c5cb6
VZ		 8994}
8995
1191cb83 8996static int bnx2x_func_wait_started(struct bnx2x *bp)
6debea87
DK		 8997{
8998 int tout = 50;
8999 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9000
9001 if (!bp->port.pmf)
9002 return 0;
9003
9004 /*
9005 * (assumption: No Attention from MCP at this stage)
16a5fd92 9006 * PMF probably in the middle of TX disable/enable transaction
6debea87 9007 * 1. Sync IRS for default SB
16a5fd92
YM		 9008 * 2. Sync SP queue - this guarantees us that attention handling started
9009 * 3. Wait, that TX disable/enable transaction completes
6debea87 9010 *
16a5fd92
YM		 9011 * 1+2 guarantee that if DCBx attention was scheduled it already changed
9012 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9013 * received completion for the transaction the state is TX_STOPPED.
6debea87
DK		 9014 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9015 * transaction.
9016 */
9017
9018 /* make sure default SB ISR is done */
9019 if (msix)
9020 synchronize_irq(bp->msix_table[0].vector);
9021 else
9022 synchronize_irq(bp->pdev->irq);
9023
9024 flush_workqueue(bnx2x_wq);
370d4a26 9025 flush_workqueue(bnx2x_iov_wq);
6debea87
DK		 9026
9027 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9028 BNX2X_F_STATE_STARTED && tout--)
9029 msleep(20);
9030
9031 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9032 BNX2X_F_STATE_STARTED) {
9033#ifdef BNX2X_STOP_ON_ERROR
51c1a580 9034 BNX2X_ERR("Wrong function state\n");
6debea87
DK		 9035 return -EBUSY;
9036#else
9037 /*
9038 * Failed to complete the transaction in a "good way"
9039 * Force both transactions with CLR bit
9040 */
3b603066 9041 struct bnx2x_func_state_params func_params = {NULL};
6debea87 9042
51c1a580 9043 DP(NETIF_MSG_IFDOWN,
0c23ad37 9044 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
6debea87
DK		 9045
9046 func_params.f_obj = &bp->func_obj;
9047 __set_bit(RAMROD_DRV_CLR_ONLY,
9048 &func_params.ramrod_flags);
9049
9050 /* STARTED-->TX_ST0PPED */
9051 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9052 bnx2x_func_state_change(bp, &func_params);
9053
9054 /* TX_ST0PPED-->STARTED */
9055 func_params.cmd = BNX2X_F_CMD_TX_START;
9056 return bnx2x_func_state_change(bp, &func_params);
9057#endif
9058 }
9059
9060 return 0;
9061}
9062
eeed018c
MK		 9063static void bnx2x_disable_ptp(struct bnx2x *bp)
9064{
9065 int port = BP_PORT(bp);
9066
9067 /* Disable sending PTP packets to host */
9068 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9069 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9070
9071 /* Reset PTP event detection rules */
9072 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9073 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9074 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9075 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9076 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9077 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9078 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9079 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9080
9081 /* Disable the PTP feature */
9082 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9083 NIG_REG_P0_PTP_EN, 0x0);
9084}
9085
9086/* Called during unload, to stop PTP-related stuff */
9087void bnx2x_stop_ptp(struct bnx2x *bp)
9088{
9089 /* Cancel PTP work queue. Should be done after the Tx queues are
9090 * drained to prevent additional scheduling.
9091 */
9092 cancel_work_sync(&bp->ptp_task);
9093
9094 if (bp->ptp_tx_skb) {
9095 dev_kfree_skb_any(bp->ptp_tx_skb);
9096 bp->ptp_tx_skb = NULL;
9097 }
9098
9099 /* Disable PTP in HW */
9100 bnx2x_disable_ptp(bp);
9101
9102 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9103}
9104
5d07d868 9105void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
619c5cb6
VZ		 9106{
9107 int port = BP_PORT(bp);
6383c0b3
AE		 9108 int i, rc = 0;
9109 u8 cos;
3b603066 9110 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6
VZ		 9111 u32 reset_code;
9112
9113 /* Wait until tx fastpath tasks complete */
9114 for_each_tx_queue(bp, i) {
9115 struct bnx2x_fastpath *fp = &bp->fp[i];
9116
6383c0b3 9117 for_each_cos_in_tx_queue(fp, cos)
65565884 9118 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
619c5cb6
VZ		 9119#ifdef BNX2X_STOP_ON_ERROR
9120 if (rc)
9121 return;
9122#endif
9123 }
9124
9125 /* Give HW time to discard old tx messages */
0926d499 9126 usleep_range(1000, 2000);
619c5cb6
VZ		 9127
9128 /* Clean all ETH MACs */
15192a8c
BW		 9129 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9130 false);
619c5cb6
VZ		 9131 if (rc < 0)
9132 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9133
9134 /* Clean up UC list */
15192a8c 9135 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
619c5cb6
VZ		 9136 true);
9137 if (rc < 0)
51c1a580
MS		 9138 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9139 rc);
619c5cb6
VZ		 9140
9141 /* Disable LLH */
9142 if (!CHIP_IS_E1(bp))
9143 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9144
9145 /* Set "drop all" (stop Rx).
9146 * We need to take a netif_addr_lock() here in order to prevent
9147 * a race between the completion code and this code.
9148 */
9149 netif_addr_lock_bh(bp->dev);
9150 /* Schedule the rx_mode command */
9151 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9152 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9153 else
9154 bnx2x_set_storm_rx_mode(bp);
9155
9156 /* Cleanup multicast configuration */
9157 rparam.mcast_obj = &bp->mcast_obj;
9158 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9159 if (rc < 0)
9160 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9161
9162 netif_addr_unlock_bh(bp->dev);
9163
f1929b01 9164 bnx2x_iov_chip_cleanup(bp);
619c5cb6 9165
6debea87
DK		 9166 /*
9167 * Send the UNLOAD_REQUEST to the MCP. This will return if
9168 * this function should perform FUNC, PORT or COMMON HW
9169 * reset.
9170 */
9171 reset_code = bnx2x_send_unload_req(bp, unload_mode);
9172
9173 /*
9174 * (assumption: No Attention from MCP at this stage)
16a5fd92 9175 * PMF probably in the middle of TX disable/enable transaction
6debea87
DK		 9176 */
9177 rc = bnx2x_func_wait_started(bp);
9178 if (rc) {
9179 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9180#ifdef BNX2X_STOP_ON_ERROR
9181 return;
9182#endif
9183 }
9184
34f80b04 9185 /* Close multi and leading connections
619c5cb6
VZ		 9186 * Completions for ramrods are collected in a synchronous way
9187 */
55c11941 9188 for_each_eth_queue(bp, i)
619c5cb6 9189 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 9190#ifdef BNX2X_STOP_ON_ERROR
9191 return;
9192#else
228241eb 9193 goto unload_error;
523224a3 9194#endif
55c11941
MS		 9195
9196 if (CNIC_LOADED(bp)) {
9197 for_each_cnic_queue(bp, i)
9198 if (bnx2x_stop_queue(bp, i))
9199#ifdef BNX2X_STOP_ON_ERROR
9200 return;
9201#else
9202 goto unload_error;
9203#endif
9204 }
9205
619c5cb6
VZ		 9206 /* If SP settings didn't get completed so far - something
9207 * very wrong has happen.
9208 */
9209 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9210 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 9211
619c5cb6
VZ		 9212#ifndef BNX2X_STOP_ON_ERROR
9213unload_error:
9214#endif
523224a3 9215 rc = bnx2x_func_stop(bp);
da5a662a 9216 if (rc) {
523224a3 9217 BNX2X_ERR("Function stop failed!\n");
da5a662a 9218#ifdef BNX2X_STOP_ON_ERROR
523224a3 9219 return;
523224a3 9220#endif
34f80b04 9221 }
a2fbb9ea 9222
eeed018c
MK		 9223 /* stop_ptp should be after the Tx queues are drained to prevent
9224 * scheduling to the cancelled PTP work queue. It should also be after
9225 * function stop ramrod is sent, since as part of this ramrod FW access
9226 * PTP registers.
9227 */
9228 bnx2x_stop_ptp(bp);
9229
523224a3
DK		 9230 /* Disable HW interrupts, NAPI */
9231 bnx2x_netif_stop(bp, 1);
26614ba5
MS		 9232 /* Delete all NAPI objects */
9233 bnx2x_del_all_napi(bp);
55c11941
MS		 9234 if (CNIC_LOADED(bp))
9235 bnx2x_del_all_napi_cnic(bp);
523224a3
DK		 9236
9237 /* Release IRQs */
d6214d7a 9238 bnx2x_free_irq(bp);
523224a3 9239
a2fbb9ea 9240 /* Reset the chip */
619c5cb6
VZ		 9241 rc = bnx2x_reset_hw(bp, reset_code);
9242 if (rc)
9243 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 9244
619c5cb6 9245 /* Report UNLOAD_DONE to MCP */
5d07d868 9246 bnx2x_send_unload_done(bp, keep_link);
72fd0718
VZ		 9247}
9248
9f6c9258 9249void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 9250{
9251 u32 val;
9252
51c1a580 9253 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
72fd0718
VZ		 9254
9255 if (CHIP_IS_E1(bp)) {
9256 int port = BP_PORT(bp);
9257 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9258 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9259
9260 val = REG_RD(bp, addr);
9261 val &= ~(0x300);
9262 REG_WR(bp, addr, val);
619c5cb6 9263 } else {
72fd0718
VZ		 9264 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9265 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9266 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9267 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9268 }
9269}
9270
72fd0718
VZ		 9271/* Close gates #2, #3 and #4: */
9272static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9273{
c9ee9206 9274 u32 val;
72fd0718
VZ		 9275
9276 /* Gates #2 and #4a are closed/opened for "not E1" only */
9277 if (!CHIP_IS_E1(bp)) {
9278 /* #4 */
c9ee9206 9279 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 9280 /* #2 */
c9ee9206 9281 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 9282 }
9283
9284 /* #3 */
c9ee9206
VZ		 9285 if (CHIP_IS_E1x(bp)) {
9286 /* Prevent interrupts from HC on both ports */
9287 val = REG_RD(bp, HC_REG_CONFIG_1);
9288 REG_WR(bp, HC_REG_CONFIG_1,
9289 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9290 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9291
9292 val = REG_RD(bp, HC_REG_CONFIG_0);
9293 REG_WR(bp, HC_REG_CONFIG_0,
9294 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9295 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9296 } else {
d82603c6 9297 /* Prevent incoming interrupts in IGU */
c9ee9206
VZ		 9298 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9299
9300 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9301 (!close) ?
9302 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9303 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9304 }
72fd0718 9305
51c1a580 9306 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
72fd0718
VZ		 9307 close ? "closing" : "opening");
9308 mmiowb();
9309}
9310
9311#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9312
9313static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9314{
9315 /* Do some magic... */
9316 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9317 *magic_val = val & SHARED_MF_CLP_MAGIC;
9318 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9319}
9320
e8920674
DK		 9321/**
9322 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 9323 *
e8920674
DK		 9324 * @bp: driver handle
9325 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 9326 */
9327static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9328{
9329 /* Restore the `magic' bit value... */
72fd0718
VZ		 9330 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9331 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9332 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9333}
9334
f85582f8 9335/**
e8920674 9336 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 9337 *
e8920674
DK		 9338 * @bp: driver handle
9339 * @magic_val: old value of 'magic' bit.
9340 *
9341 * Takes care of CLP configurations.
72fd0718
VZ		 9342 */
9343static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9344{
9345 u32 shmem;
9346 u32 validity_offset;
9347
51c1a580 9348 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
72fd0718
VZ		 9349
9350 /* Set `magic' bit in order to save MF config */
9351 if (!CHIP_IS_E1(bp))
9352 bnx2x_clp_reset_prep(bp, magic_val);
9353
9354 /* Get shmem offset */
9355 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
c55e771b
BW		 9356 validity_offset =
9357 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
72fd0718
VZ		 9358
9359 /* Clear validity map flags */
9360 if (shmem > 0)
9361 REG_WR(bp, shmem + validity_offset, 0);
9362}
9363
9364#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9365#define MCP_ONE_TIMEOUT 100 /* 100 ms */
9366
e8920674
DK		 9367/**
9368 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 9369 *
e8920674 9370 * @bp: driver handle
72fd0718 9371 */
1191cb83 9372static void bnx2x_mcp_wait_one(struct bnx2x *bp)
72fd0718
VZ		 9373{
9374 /* special handling for emulation and FPGA,
9375 wait 10 times longer */
9376 if (CHIP_REV_IS_SLOW(bp))
9377 msleep(MCP_ONE_TIMEOUT*10);
9378 else
9379 msleep(MCP_ONE_TIMEOUT);
9380}
9381
1b6e2ceb
DK		 9382/*
9383 * initializes bp->common.shmem_base and waits for validity signature to appear
9384 */
9385static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 9386{
1b6e2ceb
DK		 9387 int cnt = 0;
9388 u32 val = 0;
72fd0718 9389
1b6e2ceb
DK		 9390 do {
9391 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9392 if (bp->common.shmem_base) {
9393 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9394 if (val & SHR_MEM_VALIDITY_MB)
9395 return 0;
9396 }
72fd0718 9397
1b6e2ceb 9398 bnx2x_mcp_wait_one(bp);
72fd0718 9399
1b6e2ceb 9400 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 9401
1b6e2ceb 9402 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 9403
1b6e2ceb
DK		 9404 return -ENODEV;
9405}
72fd0718 9406
1b6e2ceb
DK		 9407static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9408{
9409 int rc = bnx2x_init_shmem(bp);
72fd0718 9410
72fd0718
VZ		 9411 /* Restore the `magic' bit value */
9412 if (!CHIP_IS_E1(bp))
9413 bnx2x_clp_reset_done(bp, magic_val);
9414
9415 return rc;
9416}
9417
9418static void bnx2x_pxp_prep(struct bnx2x *bp)
9419{
9420 if (!CHIP_IS_E1(bp)) {
9421 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9422 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 9423 mmiowb();
9424 }
9425}
9426
9427/*
9428 * Reset the whole chip except for:
9429 * - PCIE core
9430 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9431 * one reset bit)
9432 * - IGU
9433 * - MISC (including AEU)
9434 * - GRC
9435 * - RBCN, RBCP
9436 */
c9ee9206 9437static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 9438{
9439 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 9440 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 9441
9442 /*
9443 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9444 * (per chip) blocks.
9445 */
9446 global_bits2 =
9447 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9448 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 9449
c55e771b
BW		 9450 /* Don't reset the following blocks.
9451 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9452 * reset, as in 4 port device they might still be owned
9453 * by the MCP (there is only one leader per path).
9454 */
72fd0718
VZ		 9455 not_reset_mask1 =
9456 MISC_REGISTERS_RESET_REG_1_RST_HC |
9457 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9458 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9459
9460 not_reset_mask2 =
c9ee9206 9461 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 9462 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9463 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9464 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9465 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9466 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9467 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 9468 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9469 MISC_REGISTERS_RESET_REG_2_RST_ATC |
c55e771b
BW		 9470 MISC_REGISTERS_RESET_REG_2_PGLC |
9471 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9472 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9473 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9474 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9475 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9476 MISC_REGISTERS_RESET_REG_2_UMAC1;
72fd0718 9477
8736c826
VZ		 9478 /*
9479 * Keep the following blocks in reset:
9480 * - all xxMACs are handled by the bnx2x_link code.
9481 */
9482 stay_reset2 =
8736c826
VZ		 9483 MISC_REGISTERS_RESET_REG_2_XMAC |
9484 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9485
9486 /* Full reset masks according to the chip */
72fd0718
VZ		 9487 reset_mask1 = 0xffffffff;
9488
9489 if (CHIP_IS_E1(bp))
9490 reset_mask2 = 0xffff;
8736c826 9491 else if (CHIP_IS_E1H(bp))
72fd0718 9492 reset_mask2 = 0x1ffff;
8736c826
VZ		 9493 else if (CHIP_IS_E2(bp))
9494 reset_mask2 = 0xfffff;
9495 else /* CHIP_IS_E3 */
9496 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 9497
9498 /* Don't reset global blocks unless we need to */
9499 if (!global)
9500 reset_mask2 &= ~global_bits2;
9501
9502 /*
9503 * In case of attention in the QM, we need to reset PXP
9504 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9505 * because otherwise QM reset would release 'close the gates' shortly
9506 * before resetting the PXP, then the PSWRQ would send a write
9507 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9508 * read the payload data from PSWWR, but PSWWR would not
9509 * respond. The write queue in PGLUE would stuck, dmae commands
9510 * would not return. Therefore it's important to reset the second
9511 * reset register (containing the
9512 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9513 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9514 * bit).
9515 */
72fd0718
VZ		 9516 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9517 reset_mask2 & (~not_reset_mask2));
9518
c9ee9206
VZ		 9519 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9520 reset_mask1 & (~not_reset_mask1));
9521
72fd0718
VZ		 9522 barrier();
9523 mmiowb();
9524
8736c826
VZ		 9525 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9526 reset_mask2 & (~stay_reset2));
9527
9528 barrier();
9529 mmiowb();
9530
c9ee9206 9531 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 9532 mmiowb();
9533}
9534
c9ee9206
VZ		 9535/**
9536 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9537 * It should get cleared in no more than 1s.
9538 *
9539 * @bp: driver handle
9540 *
9541 * It should get cleared in no more than 1s. Returns 0 if
9542 * pending writes bit gets cleared.
9543 */
9544static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9545{
9546 u32 cnt = 1000;
9547 u32 pend_bits = 0;
9548
9549 do {
9550 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9551
9552 if (pend_bits == 0)
9553 break;
9554
0926d499 9555 usleep_range(1000, 2000);
c9ee9206
VZ		 9556 } while (cnt-- > 0);
9557
9558 if (cnt <= 0) {
9559 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9560 pend_bits);
9561 return -EBUSY;
9562 }
9563
9564 return 0;
9565}
9566
9567static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 9568{
9569 int cnt = 1000;
9570 u32 val = 0;
9571 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
2de67439 9572 u32 tags_63_32 = 0;
72fd0718
VZ		 9573
9574 /* Empty the Tetris buffer, wait for 1s */
9575 do {
9576 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9577 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9578 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9579 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9580 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
c55e771b
BW		 9581 if (CHIP_IS_E3(bp))
9582 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9583
72fd0718
VZ		 9584 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9585 ((port_is_idle_0 & 0x1) == 0x1) &&
9586 ((port_is_idle_1 & 0x1) == 0x1) &&
c55e771b
BW		 9587 (pgl_exp_rom2 == 0xffffffff) &&
9588 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
72fd0718 9589 break;
0926d499 9590 usleep_range(1000, 2000);
72fd0718
VZ		 9591 } while (cnt-- > 0);
9592
9593 if (cnt <= 0) {
51c1a580
MS		 9594 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9595 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
72fd0718
VZ		 9596 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9597 pgl_exp_rom2);
9598 return -EAGAIN;
9599 }
9600
9601 barrier();
9602
9603 /* Close gates #2, #3 and #4 */
9604 bnx2x_set_234_gates(bp, true);
9605
c9ee9206
VZ		 9606 /* Poll for IGU VQs for 57712 and newer chips */
9607 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9608 return -EAGAIN;
9609
72fd0718
VZ		 9610 /* TBD: Indicate that "process kill" is in progress to MCP */
9611
9612 /* Clear "unprepared" bit */
9613 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9614 barrier();
9615
9616 /* Make sure all is written to the chip before the reset */
9617 mmiowb();
9618
9619 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9620 * PSWHST, GRC and PSWRD Tetris buffer.
9621 */
0926d499 9622 usleep_range(1000, 2000);
72fd0718
VZ		 9623
9624 /* Prepare to chip reset: */
9625 /* MCP */
c9ee9206
VZ		 9626 if (global)
9627 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 9628
9629 /* PXP */
9630 bnx2x_pxp_prep(bp);
9631 barrier();
9632
9633 /* reset the chip */
c9ee9206 9634 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 9635 barrier();
9636
9dcd9acd
DK		 9637 /* clear errors in PGB */
9638 if (!CHIP_IS_E1x(bp))
9639 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9640
72fd0718
VZ		 9641 /* Recover after reset: */
9642 /* MCP */
c9ee9206 9643 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 9644 return -EAGAIN;
9645
c9ee9206
VZ		 9646 /* TBD: Add resetting the NO_MCP mode DB here */
9647
72fd0718
VZ		 9648 /* Open the gates #2, #3 and #4 */
9649 bnx2x_set_234_gates(bp, false);
9650
9651 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9652 * reset state, re-enable attentions. */
9653
a2fbb9ea
ET		 9654 return 0;
9655}
9656
910cc727 9657static int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 9658{
9659 int rc = 0;
c9ee9206 9660 bool global = bnx2x_reset_is_global(bp);
95c6c616
AE		 9661 u32 load_code;
9662
9663 /* if not going to reset MCP - load "fake" driver to reset HW while
9664 * driver is owner of the HW
9665 */
9666 if (!global && !BP_NOMCP(bp)) {
5d07d868
YM		 9667 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9668 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
95c6c616
AE		 9669 if (!load_code) {
9670 BNX2X_ERR("MCP response failure, aborting\n");
9671 rc = -EAGAIN;
9672 goto exit_leader_reset;
9673 }
9674 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9675 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9676 BNX2X_ERR("MCP unexpected resp, aborting\n");
9677 rc = -EAGAIN;
9678 goto exit_leader_reset2;
9679 }
9680 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9681 if (!load_code) {
9682 BNX2X_ERR("MCP response failure, aborting\n");
9683 rc = -EAGAIN;
9684 goto exit_leader_reset2;
9685 }
9686 }
c9ee9206 9687
72fd0718 9688 /* Try to recover after the failure */
c9ee9206 9689 if (bnx2x_process_kill(bp, global)) {
51c1a580
MS		 9690 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9691 BP_PATH(bp));
72fd0718 9692 rc = -EAGAIN;
95c6c616 9693 goto exit_leader_reset2;
72fd0718
VZ		 9694 }
9695
c9ee9206
VZ		 9696 /*
9697 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9698 * state.
9699 */
72fd0718 9700 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 9701 if (global)
9702 bnx2x_clear_reset_global(bp);
72fd0718 9703
95c6c616
AE		 9704exit_leader_reset2:
9705 /* unload "fake driver" if it was loaded */
9706 if (!global && !BP_NOMCP(bp)) {
9707 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9708 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9709 }
72fd0718
VZ		 9710exit_leader_reset:
9711 bp->is_leader = 0;
c9ee9206
VZ		 9712 bnx2x_release_leader_lock(bp);
9713 smp_mb();
72fd0718
VZ		 9714 return rc;
9715}
9716
1191cb83 9717static void bnx2x_recovery_failed(struct bnx2x *bp)
c9ee9206
VZ		 9718{
9719 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9720
9721 /* Disconnect this device */
9722 netif_device_detach(bp->dev);
9723
9724 /*
9725 * Block ifup for all function on this engine until "process kill"
9726 * or power cycle.
9727 */
9728 bnx2x_set_reset_in_progress(bp);
9729
9730 /* Shut down the power */
9731 bnx2x_set_power_state(bp, PCI_D3hot);
9732
9733 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9734
9735 smp_mb();
9736}
9737
9738/*
9739 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 9740 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 9741 * will never be called when netif_running(bp->dev) is false.
9742 */
9743static void bnx2x_parity_recover(struct bnx2x *bp)
9744{
c9ee9206 9745 bool global = false;
7a752993 9746 u32 error_recovered, error_unrecovered;
95c6c616 9747 bool is_parity;
c9ee9206 9748
72fd0718
VZ		 9749 DP(NETIF_MSG_HW, "Handling parity\n");
9750 while (1) {
9751 switch (bp->recovery_state) {
9752 case BNX2X_RECOVERY_INIT:
9753 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
95c6c616
AE		 9754 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9755 WARN_ON(!is_parity);
c9ee9206 9756
72fd0718 9757 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 9758 if (bnx2x_trylock_leader_lock(bp)) {
9759 bnx2x_set_reset_in_progress(bp);
9760 /*
9761 * Check if there is a global attention and if
9762 * there was a global attention, set the global
9763 * reset bit.
9764 */
9765
9766 if (global)
9767 bnx2x_set_reset_global(bp);
9768
72fd0718 9769 bp->is_leader = 1;
c9ee9206 9770 }
72fd0718
VZ		 9771
9772 /* Stop the driver */
9773 /* If interface has been removed - break */
5d07d868 9774 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
72fd0718
VZ		 9775 return;
9776
9777 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206 9778
c9ee9206
VZ		 9779 /* Ensure "is_leader", MCP command sequence and
9780 * "recovery_state" update values are seen on other
9781 * CPUs.
72fd0718 9782 */
c9ee9206 9783 smp_mb();
72fd0718
VZ		 9784 break;
9785
9786 case BNX2X_RECOVERY_WAIT:
9787 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9788 if (bp->is_leader) {
c9ee9206 9789 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3
AE		 9790 bool other_load_status =
9791 bnx2x_get_load_status(bp, other_engine);
9792 bool load_status =
9793 bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 9794 global = bnx2x_reset_is_global(bp);
9795
9796 /*
9797 * In case of a parity in a global block, let
9798 * the first leader that performs a
9799 * leader_reset() reset the global blocks in
9800 * order to clear global attentions. Otherwise
16a5fd92 9801 * the gates will remain closed for that
c9ee9206
VZ		 9802 * engine.
9803 */
889b9af3
AE		 9804 if (load_status ||
9805 (global && other_load_status)) {
72fd0718
VZ		 9806 /* Wait until all other functions get
9807 * down.
9808 */
7be08a72 9809 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9810 HZ/10);
9811 return;
9812 } else {
9813 /* If all other functions got down -
9814 * try to bring the chip back to
9815 * normal. In any case it's an exit
9816 * point for a leader.
9817 */
c9ee9206
VZ		 9818 if (bnx2x_leader_reset(bp)) {
9819 bnx2x_recovery_failed(bp);
72fd0718
VZ		 9820 return;
9821 }
9822
c9ee9206
VZ		 9823 /* If we are here, means that the
9824 * leader has succeeded and doesn't
9825 * want to be a leader any more. Try
9826 * to continue as a none-leader.
9827 */
9828 break;
72fd0718
VZ		 9829 }
9830 } else { /* non-leader */
c9ee9206 9831 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 9832 /* Try to get a LEADER_LOCK HW lock as
9833 * long as a former leader may have
9834 * been unloaded by the user or
9835 * released a leadership by another
9836 * reason.
9837 */
c9ee9206 9838 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 9839 /* I'm a leader now! Restart a
9840 * switch case.
9841 */
9842 bp->is_leader = 1;
9843 break;
9844 }
9845
7be08a72 9846 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9847 HZ/10);
9848 return;
9849
c9ee9206
VZ		 9850 } else {
9851 /*
9852 * If there was a global attention, wait
9853 * for it to be cleared.
9854 */
9855 if (bnx2x_reset_is_global(bp)) {
9856 schedule_delayed_work(
7be08a72
AE		 9857 &bp->sp_rtnl_task,
9858 HZ/10);
c9ee9206
VZ		 9859 return;
9860 }
9861
7a752993
AE		 9862 error_recovered =
9863 bp->eth_stats.recoverable_error;
9864 error_unrecovered =
9865 bp->eth_stats.unrecoverable_error;
95c6c616
AE		 9866 bp->recovery_state =
9867 BNX2X_RECOVERY_NIC_LOADING;
9868 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
7a752993 9869 error_unrecovered++;
95c6c616 9870 netdev_err(bp->dev,
51c1a580 9871 "Recovery failed. Power cycle needed\n");
95c6c616
AE		 9872 /* Disconnect this device */
9873 netif_device_detach(bp->dev);
9874 /* Shut down the power */
9875 bnx2x_set_power_state(
9876 bp, PCI_D3hot);
9877 smp_mb();
9878 } else {
c9ee9206
VZ		 9879 bp->recovery_state =
9880 BNX2X_RECOVERY_DONE;
7a752993 9881 error_recovered++;
c9ee9206
VZ		 9882 smp_mb();
9883 }
7a752993
AE		 9884 bp->eth_stats.recoverable_error =
9885 error_recovered;
9886 bp->eth_stats.unrecoverable_error =
9887 error_unrecovered;
c9ee9206 9888
72fd0718
VZ		 9889 return;
9890 }
9891 }
9892 default:
9893 return;
9894 }
9895 }
9896}
9897
56ad3152
MS		 9898static int bnx2x_close(struct net_device *dev);
9899
72fd0718
VZ		 9900/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9901 * scheduled on a general queue in order to prevent a dead lock.
9902 */
7be08a72 9903static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 9904{
7be08a72 9905 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 9906
9907 rtnl_lock();
9908
8395be5e
AE		 9909 if (!netif_running(bp->dev)) {
9910 rtnl_unlock();
9911 return;
9912 }
7be08a72 9913
6bf07b8e 9914 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
7be08a72 9915#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e
YM		 9916 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9917 "you will need to reboot when done\n");
9918 goto sp_rtnl_not_reset;
7be08a72 9919#endif
7be08a72 9920 /*
b1fb8740
VZ		 9921 * Clear all pending SP commands as we are going to reset the
9922 * function anyway.
7be08a72 9923 */
b1fb8740
VZ		 9924 bp->sp_rtnl_state = 0;
9925 smp_mb();
9926
72fd0718 9927 bnx2x_parity_recover(bp);
b1fb8740 9928
8395be5e
AE		 9929 rtnl_unlock();
9930 return;
b1fb8740
VZ		 9931 }
9932
9933 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
6bf07b8e
YM		 9934#ifdef BNX2X_STOP_ON_ERROR
9935 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9936 "you will need to reboot when done\n");
9937 goto sp_rtnl_not_reset;
9938#endif
9939
b1fb8740
VZ		 9940 /*
9941 * Clear all pending SP commands as we are going to reset the
9942 * function anyway.
9943 */
9944 bp->sp_rtnl_state = 0;
9945 smp_mb();
9946
5d07d868 9947 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
72fd0718 9948 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740 9949
8395be5e
AE		 9950 rtnl_unlock();
9951 return;
72fd0718 9952 }
b1fb8740
VZ		 9953#ifdef BNX2X_STOP_ON_ERROR
9954sp_rtnl_not_reset:
9955#endif
9956 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9957 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
a3348722
BW		 9958 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9959 bnx2x_after_function_update(bp);
8304859a
AE		 9960 /*
9961 * in case of fan failure we need to reset id if the "stop on error"
9962 * debug flag is set, since we trying to prevent permanent overheating
9963 * damage
9964 */
9965 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
51c1a580 9966 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
8304859a
AE		 9967 netif_device_detach(bp->dev);
9968 bnx2x_close(bp->dev);
8395be5e
AE		 9969 rtnl_unlock();
9970 return;
8304859a
AE		 9971 }
9972
381ac16b
AE		 9973 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9974 DP(BNX2X_MSG_SP,
9975 "sending set mcast vf pf channel message from rtnl sp-task\n");
9976 bnx2x_vfpf_set_mcast(bp->dev);
9977 }
78c3bcc5
AE		 9978 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9979 &bp->sp_rtnl_state)){
9980 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9981 bnx2x_tx_disable(bp);
9982 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9983 }
9984 }
381ac16b 9985
8b09be5f
YM		 9986 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
9987 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
9988 bnx2x_set_rx_mode_inner(bp);
381ac16b
AE		 9989 }
9990
3ec9f9ca
AE		 9991 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9992 &bp->sp_rtnl_state))
9993 bnx2x_pf_set_vfs_vlan(bp);
9994
6ffa39f2 9995 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
07b4eb3b 9996 bnx2x_dcbx_stop_hw_tx(bp);
07b4eb3b 9997 bnx2x_dcbx_resume_hw_tx(bp);
6ffa39f2 9998 }
07b4eb3b 9999
42f8277f
YM		 10000 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10001 &bp->sp_rtnl_state))
10002 bnx2x_update_mng_version(bp);
10003
8395be5e
AE		 10004 /* work which needs rtnl lock not-taken (as it takes the lock itself and
10005 * can be called from other contexts as well)
10006 */
34f80b04 10007 rtnl_unlock();
8395be5e 10008
6411280a 10009 /* enable SR-IOV if applicable */
8395be5e 10010 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
3c76feff
AE		 10011 &bp->sp_rtnl_state)) {
10012 bnx2x_disable_sriov(bp);
6411280a 10013 bnx2x_enable_sriov(bp);
3c76feff 10014 }
34f80b04
EG		 10015}
10016
3deb8167
YR		 10017static void bnx2x_period_task(struct work_struct *work)
10018{
10019 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10020
10021 if (!netif_running(bp->dev))
10022 goto period_task_exit;
10023
10024 if (CHIP_REV_IS_SLOW(bp)) {
10025 BNX2X_ERR("period task called on emulation, ignoring\n");
10026 goto period_task_exit;
10027 }
10028
10029 bnx2x_acquire_phy_lock(bp);
10030 /*
10031 * The barrier is needed to ensure the ordering between the writing to
10032 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10033 * the reading here.
10034 */
10035 smp_mb();
10036 if (bp->port.pmf) {
10037 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10038
10039 /* Re-queue task in 1 sec */
10040 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10041 }
10042
10043 bnx2x_release_phy_lock(bp);
10044period_task_exit:
10045 return;
10046}
10047
a2fbb9ea
ET		 10048/*
10049 * Init service functions
10050 */
10051
a8f47eb7 10052static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 10053{
10054 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10055 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10056 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 10057}
10058
1ef1d45a
BW		 10059static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10060 struct bnx2x_mac_vals *vals)
34f80b04 10061{
452427b0
YM		 10062 u32 val, base_addr, offset, mask, reset_reg;
10063 bool mac_stopped = false;
10064 u8 port = BP_PORT(bp);
34f80b04 10065
1ef1d45a
BW		 10066 /* reset addresses as they also mark which values were changed */
10067 vals->bmac_addr = 0;
10068 vals->umac_addr = 0;
10069 vals->xmac_addr = 0;
10070 vals->emac_addr = 0;
10071
452427b0 10072 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
f16da43b 10073
452427b0
YM		 10074 if (!CHIP_IS_E3(bp)) {
10075 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10076 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10077 if ((mask & reset_reg) && val) {
10078 u32 wb_data[2];
10079 BNX2X_DEV_INFO("Disable bmac Rx\n");
10080 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10081 : NIG_REG_INGRESS_BMAC0_MEM;
10082 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10083 : BIGMAC_REGISTER_BMAC_CONTROL;
7a06a122 10084
452427b0
YM		 10085 /*
10086 * use rd/wr since we cannot use dmae. This is safe
10087 * since MCP won't access the bus due to the request
10088 * to unload, and no function on the path can be
10089 * loaded at this time.
10090 */
10091 wb_data[0] = REG_RD(bp, base_addr + offset);
10092 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
1ef1d45a
BW		 10093 vals->bmac_addr = base_addr + offset;
10094 vals->bmac_val[0] = wb_data[0];
10095 vals->bmac_val[1] = wb_data[1];
452427b0 10096 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1ef1d45a
BW		 10097 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10098 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
452427b0
YM		 10099 }
10100 BNX2X_DEV_INFO("Disable emac Rx\n");
1ef1d45a
BW		 10101 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10102 vals->emac_val = REG_RD(bp, vals->emac_addr);
10103 REG_WR(bp, vals->emac_addr, 0);
452427b0
YM		 10104 mac_stopped = true;
10105 } else {
10106 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10107 BNX2X_DEV_INFO("Disable xmac Rx\n");
10108 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10109 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10110 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10111 val & ~(1 << 1));
10112 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10113 val | (1 << 1));
1ef1d45a
BW		 10114 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10115 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10116 REG_WR(bp, vals->xmac_addr, 0);
452427b0
YM		 10117 mac_stopped = true;
10118 }
10119 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10120 if (mask & reset_reg) {
10121 BNX2X_DEV_INFO("Disable umac Rx\n");
10122 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1ef1d45a
BW		 10123 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
10124 vals->umac_val = REG_RD(bp, vals->umac_addr);
10125 REG_WR(bp, vals->umac_addr, 0);
452427b0
YM		 10126 mac_stopped = true;
10127 }
10128 }
10129
10130 if (mac_stopped)
10131 msleep(20);
452427b0
YM		 10132}
10133
10134#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
7c3afd85
YM		 10135#define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10136 0x1848 + ((f) << 4))
452427b0
YM		 10137#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10138#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10139#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10140
91ebb929
YM		 10141#define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10142#define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10143#define BCM_5710_UNDI_FW_MF_VERS (0x05)
b17b0ca1
YM		 10144
10145static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10146{
10147 /* UNDI marks its presence in DORQ -
10148 * it initializes CID offset for normal bell to 0x7
10149 */
10150 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10151 MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10152 return false;
10153
10154 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10155 BNX2X_DEV_INFO("UNDI previously loaded\n");
10156 return true;
10157 }
10158
10159 return false;
10160}
10161
7c3afd85 10162static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
452427b0
YM		 10163{
10164 u16 rcq, bd;
7c3afd85 10165 u32 addr, tmp_reg;
452427b0 10166
7c3afd85
YM		 10167 if (BP_FUNC(bp) < 2)
10168 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10169 else
10170 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10171
10172 tmp_reg = REG_RD(bp, addr);
452427b0
YM		 10173 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10174 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10175
10176 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
7c3afd85 10177 REG_WR(bp, addr, tmp_reg);
452427b0 10178
7c3afd85
YM		 10179 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10180 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
452427b0
YM		 10181}
10182
0329aba1 10183static int bnx2x_prev_mcp_done(struct bnx2x *bp)
452427b0 10184{
5d07d868
YM		 10185 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10186 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
452427b0
YM		 10187 if (!rc) {
10188 BNX2X_ERR("MCP response failure, aborting\n");
10189 return -EBUSY;
10190 }
10191
10192 return 0;
10193}
10194
c63da990
BW		 10195static struct bnx2x_prev_path_list *
10196 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10197{
10198 struct bnx2x_prev_path_list *tmp_list;
10199
10200 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10201 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10202 bp->pdev->bus->number == tmp_list->bus &&
10203 BP_PATH(bp) == tmp_list->path)
10204 return tmp_list;
10205
10206 return NULL;
10207}
10208
7fa6f340
YM		 10209static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10210{
10211 struct bnx2x_prev_path_list *tmp_list;
10212 int rc;
10213
10214 rc = down_interruptible(&bnx2x_prev_sem);
10215 if (rc) {
10216 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10217 return rc;
10218 }
10219
10220 tmp_list = bnx2x_prev_path_get_entry(bp);
10221 if (tmp_list) {
10222 tmp_list->aer = 1;
10223 rc = 0;
10224 } else {
10225 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10226 BP_PATH(bp));
10227 }
10228
10229 up(&bnx2x_prev_sem);
10230
10231 return rc;
10232}
10233
0329aba1 10234static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
452427b0
YM		 10235{
10236 struct bnx2x_prev_path_list *tmp_list;
b85d717c 10237 bool rc = false;
452427b0
YM		 10238
10239 if (down_trylock(&bnx2x_prev_sem))
10240 return false;
10241
7fa6f340
YM		 10242 tmp_list = bnx2x_prev_path_get_entry(bp);
10243 if (tmp_list) {
10244 if (tmp_list->aer) {
10245 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10246 BP_PATH(bp));
10247 } else {
452427b0
YM		 10248 rc = true;
10249 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10250 BP_PATH(bp));
452427b0
YM		 10251 }
10252 }
10253
10254 up(&bnx2x_prev_sem);
10255
10256 return rc;
10257}
10258
178135c1
DK		 10259bool bnx2x_port_after_undi(struct bnx2x *bp)
10260{
10261 struct bnx2x_prev_path_list *entry;
10262 bool val;
10263
10264 down(&bnx2x_prev_sem);
10265
10266 entry = bnx2x_prev_path_get_entry(bp);
10267 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10268
10269 up(&bnx2x_prev_sem);
10270
10271 return val;
10272}
10273
c63da990 10274static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
452427b0
YM		 10275{
10276 struct bnx2x_prev_path_list *tmp_list;
10277 int rc;
10278
7fa6f340
YM		 10279 rc = down_interruptible(&bnx2x_prev_sem);
10280 if (rc) {
10281 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10282 return rc;
10283 }
10284
10285 /* Check whether the entry for this path already exists */
10286 tmp_list = bnx2x_prev_path_get_entry(bp);
10287 if (tmp_list) {
10288 if (!tmp_list->aer) {
10289 BNX2X_ERR("Re-Marking the path.\n");
10290 } else {
10291 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10292 BP_PATH(bp));
10293 tmp_list->aer = 0;
10294 }
10295 up(&bnx2x_prev_sem);
10296 return 0;
10297 }
10298 up(&bnx2x_prev_sem);
10299
10300 /* Create an entry for this path and add it */
ea4b3857 10301 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
452427b0
YM		 10302 if (!tmp_list) {
10303 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10304 return -ENOMEM;
10305 }
10306
10307 tmp_list->bus = bp->pdev->bus->number;
10308 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10309 tmp_list->path = BP_PATH(bp);
7fa6f340 10310 tmp_list->aer = 0;
c63da990 10311 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
452427b0
YM		 10312
10313 rc = down_interruptible(&bnx2x_prev_sem);
10314 if (rc) {
10315 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10316 kfree(tmp_list);
10317 } else {
7fa6f340
YM		 10318 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10319 BP_PATH(bp));
452427b0
YM		 10320 list_add(&tmp_list->list, &bnx2x_prev_list);
10321 up(&bnx2x_prev_sem);
10322 }
10323
10324 return rc;
10325}
10326
0329aba1 10327static int bnx2x_do_flr(struct bnx2x *bp)
452427b0 10328{
452427b0
YM		 10329 struct pci_dev *dev = bp->pdev;
10330
8eee694c
YM		 10331 if (CHIP_IS_E1x(bp)) {
10332 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10333 return -EINVAL;
10334 }
10335
10336 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10337 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10338 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10339 bp->common.bc_ver);
10340 return -EINVAL;
10341 }
452427b0 10342
8903b9eb
CL		 10343 if (!pci_wait_for_pending_transaction(dev))
10344 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
452427b0 10345
8eee694c 10346 BNX2X_DEV_INFO("Initiating FLR\n");
452427b0
YM		 10347 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10348
10349 return 0;
10350}
10351
0329aba1 10352static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
452427b0
YM		 10353{
10354 int rc;
10355
10356 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10357
10358 /* Test if previous unload process was already finished for this path */
10359 if (bnx2x_prev_is_path_marked(bp))
10360 return bnx2x_prev_mcp_done(bp);
10361
04c46736
YM		 10362 BNX2X_DEV_INFO("Path is unmarked\n");
10363
b17b0ca1
YM		 10364 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10365 if (bnx2x_prev_is_after_undi(bp))
10366 goto out;
10367
452427b0
YM		 10368 /* If function has FLR capabilities, and existing FW version matches
10369 * the one required, then FLR will be sufficient to clean any residue
10370 * left by previous driver
10371 */
91ebb929 10372 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
8eee694c
YM		 10373
10374 if (!rc) {
10375 /* fw version is good */
10376 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10377 rc = bnx2x_do_flr(bp);
10378 }
10379
10380 if (!rc) {
10381 /* FLR was performed */
10382 BNX2X_DEV_INFO("FLR successful\n");
10383 return 0;
10384 }
10385
10386 BNX2X_DEV_INFO("Could not FLR\n");
452427b0 10387
b17b0ca1 10388out:
452427b0
YM		 10389 /* Close the MCP request, return failure*/
10390 rc = bnx2x_prev_mcp_done(bp);
10391 if (!rc)
10392 rc = BNX2X_PREV_WAIT_NEEDED;
10393
10394 return rc;
10395}
10396
0329aba1 10397static int bnx2x_prev_unload_common(struct bnx2x *bp)
452427b0
YM		 10398{
10399 u32 reset_reg, tmp_reg = 0, rc;
c63da990 10400 bool prev_undi = false;
1ef1d45a
BW		 10401 struct bnx2x_mac_vals mac_vals;
10402
452427b0
YM		 10403 /* It is possible a previous function received 'common' answer,
10404 * but hasn't loaded yet, therefore creating a scenario of
10405 * multiple functions receiving 'common' on the same path.
10406 */
10407 BNX2X_DEV_INFO("Common unload Flow\n");
10408
1ef1d45a
BW		 10409 memset(&mac_vals, 0, sizeof(mac_vals));
10410
452427b0
YM		 10411 if (bnx2x_prev_is_path_marked(bp))
10412 return bnx2x_prev_mcp_done(bp);
10413
10414 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10415
10416 /* Reset should be performed after BRB is emptied */
10417 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10418 u32 timer_count = 1000;
452427b0
YM		 10419
10420 /* Close the MAC Rx to prevent BRB from filling up */
1ef1d45a
BW		 10421 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10422
10423 /* close LLH filters towards the BRB */
10424 bnx2x_set_rx_filter(&bp->link_params, 0);
452427b0 10425
b17b0ca1
YM		 10426 /* Check if the UNDI driver was previously loaded */
10427 if (bnx2x_prev_is_after_undi(bp)) {
10428 prev_undi = true;
10429 /* clear the UNDI indication */
10430 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10431 /* clear possible idle check errors */
10432 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
452427b0 10433 }
d46f7c4d
DK		 10434 if (!CHIP_IS_E1x(bp))
10435 /* block FW from writing to host */
10436 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10437
452427b0
YM		 10438 /* wait until BRB is empty */
10439 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10440 while (timer_count) {
10441 u32 prev_brb = tmp_reg;
34f80b04 10442
452427b0
YM		 10443 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10444 if (!tmp_reg)
10445 break;
619c5cb6 10446
452427b0 10447 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
619c5cb6 10448
452427b0
YM		 10449 /* reset timer as long as BRB actually gets emptied */
10450 if (prev_brb > tmp_reg)
10451 timer_count = 1000;
10452 else
10453 timer_count--;
da5a662a 10454
7c3afd85
YM		 10455 /* If UNDI resides in memory, manually increment it */
10456 if (prev_undi)
10457 bnx2x_prev_unload_undi_inc(bp, 1);
10458
452427b0 10459 udelay(10);
7a06a122 10460 }
452427b0
YM		 10461
10462 if (!timer_count)
10463 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
34f80b04 10464 }
f16da43b 10465
452427b0
YM		 10466 /* No packets are in the pipeline, path is ready for reset */
10467 bnx2x_reset_common(bp);
10468
1ef1d45a
BW		 10469 if (mac_vals.xmac_addr)
10470 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10471 if (mac_vals.umac_addr)
10472 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10473 if (mac_vals.emac_addr)
10474 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10475 if (mac_vals.bmac_addr) {
10476 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10477 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10478 }
10479
c63da990 10480 rc = bnx2x_prev_mark_path(bp, prev_undi);
452427b0
YM		 10481 if (rc) {
10482 bnx2x_prev_mcp_done(bp);
10483 return rc;
10484 }
10485
10486 return bnx2x_prev_mcp_done(bp);
10487}
10488
24f06716
AE		 10489/* previous driver DMAE transaction may have occurred when pre-boot stage ended
10490 * and boot began, or when kdump kernel was loaded. Either case would invalidate
10491 * the addresses of the transaction, resulting in was-error bit set in the pci
10492 * causing all hw-to-host pcie transactions to timeout. If this happened we want
10493 * to clear the interrupt which detected this from the pglueb and the was done
10494 * bit
10495 */
0329aba1 10496static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
24f06716 10497{
4a25417c
AE		 10498 if (!CHIP_IS_E1x(bp)) {
10499 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10500 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
04c46736
YM		 10501 DP(BNX2X_MSG_SP,
10502 "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
4a25417c
AE		 10503 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10504 1 << BP_FUNC(bp));
10505 }
24f06716
AE		 10506 }
10507}
10508
0329aba1 10509static int bnx2x_prev_unload(struct bnx2x *bp)
452427b0
YM		 10510{
10511 int time_counter = 10;
10512 u32 rc, fw, hw_lock_reg, hw_lock_val;
10513 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10514
24f06716
AE		 10515 /* clear hw from errors which may have resulted from an interrupted
10516 * dmae transaction.
10517 */
10518 bnx2x_prev_interrupted_dmae(bp);
10519
10520 /* Release previously held locks */
452427b0
YM		 10521 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10522 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10523 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10524
3cdeec22 10525 hw_lock_val = REG_RD(bp, hw_lock_reg);
452427b0
YM		 10526 if (hw_lock_val) {
10527 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10528 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10529 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10530 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10531 }
10532
10533 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10534 REG_WR(bp, hw_lock_reg, 0xffffffff);
10535 } else
10536 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10537
10538 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10539 BNX2X_DEV_INFO("Release previously held alr\n");
3cdeec22 10540 bnx2x_release_alr(bp);
452427b0
YM		 10541 }
10542
452427b0 10543 do {
7fa6f340 10544 int aer = 0;
452427b0
YM		 10545 /* Lock MCP using an unload request */
10546 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10547 if (!fw) {
10548 BNX2X_ERR("MCP response failure, aborting\n");
10549 rc = -EBUSY;
10550 break;
10551 }
10552
7fa6f340
YM		 10553 rc = down_interruptible(&bnx2x_prev_sem);
10554 if (rc) {
10555 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10556 rc);
10557 } else {
10558 /* If Path is marked by EEH, ignore unload status */
10559 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10560 bnx2x_prev_path_get_entry(bp)->aer);
60cde81f 10561 up(&bnx2x_prev_sem);
7fa6f340 10562 }
7fa6f340
YM		 10563
10564 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
452427b0
YM		 10565 rc = bnx2x_prev_unload_common(bp);
10566 break;
10567 }
10568
16a5fd92 10569 /* non-common reply from MCP might require looping */
452427b0
YM		 10570 rc = bnx2x_prev_unload_uncommon(bp);
10571 if (rc != BNX2X_PREV_WAIT_NEEDED)
10572 break;
10573
10574 msleep(20);
10575 } while (--time_counter);
10576
10577 if (!time_counter || rc) {
91ebb929
YM		 10578 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10579 rc = -EPROBE_DEFER;
452427b0
YM		 10580 }
10581
c63da990 10582 /* Mark function if its port was used to boot from SAN */
178135c1 10583 if (bnx2x_port_after_undi(bp))
c63da990
BW		 10584 bp->link_params.feature_config_flags |=
10585 FEATURE_CONFIG_BOOT_FROM_SAN;
10586
452427b0
YM		 10587 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10588
10589 return rc;
34f80b04
EG		 10590}
10591
0329aba1 10592static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
34f80b04 10593{
1d187b34 10594 u32 val, val2, val3, val4, id, boot_mode;
72ce58c3 10595 u16 pmc;
34f80b04
EG		 10596
10597 /* Get the chip revision id and number. */
10598 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10599 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10600 id = ((val & 0xffff) << 16);
10601 val = REG_RD(bp, MISC_REG_CHIP_REV);
10602 id |= ((val & 0xf) << 12);
f22fdf25
YM		 10603
10604 /* Metal is read from PCI regs, but we can't access >=0x400 from
10605 * the configuration space (so we need to reg_rd)
10606 */
10607 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10608 id |= (((val >> 24) & 0xf) << 4);
5a40e08e 10609 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 10610 id |= (val & 0xf);
10611 bp->common.chip_id = id;
523224a3 10612
7e8e02df
BW		 10613 /* force 57811 according to MISC register */
10614 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10615 if (CHIP_IS_57810(bp))
10616 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10617 (bp->common.chip_id & 0x0000FFFF);
10618 else if (CHIP_IS_57810_MF(bp))
10619 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10620 (bp->common.chip_id & 0x0000FFFF);
10621 bp->common.chip_id |= 0x1;
10622 }
10623
523224a3
DK		 10624 /* Set doorbell size */
10625 bp->db_size = (1 << BNX2X_DB_SHIFT);
10626
619c5cb6 10627 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 10628 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10629 if ((val & 1) == 0)
10630 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10631 else
10632 val = (val >> 1) & 1;
10633 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10634 "2_PORT_MODE");
10635 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10636 CHIP_2_PORT_MODE;
10637
10638 if (CHIP_MODE_IS_4_PORT(bp))
10639 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10640 else
10641 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10642 } else {
10643 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10644 bp->pfid = bp->pf_num; /* 0..7 */
10645 }
10646
51c1a580
MS		 10647 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10648
f2e0899f
DK		 10649 bp->link_params.chip_id = bp->common.chip_id;
10650 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 10651
1c06328c
EG		 10652 val = (REG_RD(bp, 0x2874) & 0x55);
10653 if ((bp->common.chip_id & 0x1) ||
10654 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10655 bp->flags |= ONE_PORT_FLAG;
10656 BNX2X_DEV_INFO("single port device\n");
10657 }
10658
34f80b04 10659 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 10660 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 10661 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10662 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10663 bp->common.flash_size, bp->common.flash_size);
10664
1b6e2ceb
DK		 10665 bnx2x_init_shmem(bp);
10666
f2e0899f
DK		 10667 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10668 MISC_REG_GENERIC_CR_1 :
10669 MISC_REG_GENERIC_CR_0));
1b6e2ceb 10670
34f80b04 10671 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 10672 bp->link_params.shmem2_base = bp->common.shmem2_base;
b884d95b
YR		 10673 if (SHMEM2_RD(bp, size) >
10674 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10675 bp->link_params.lfa_base =
10676 REG_RD(bp, bp->common.shmem2_base +
10677 (u32)offsetof(struct shmem2_region,
10678 lfa_host_addr[BP_PORT(bp)]));
10679 else
10680 bp->link_params.lfa_base = 0;
2691d51d
EG		 10681 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10682 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 10683
f2e0899f 10684 if (!bp->common.shmem_base) {
34f80b04
EG		 10685 BNX2X_DEV_INFO("MCP not active\n");
10686 bp->flags |= NO_MCP_FLAG;
10687 return;
10688 }
10689
34f80b04 10690 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 10691 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 10692
10693 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10694 SHARED_HW_CFG_LED_MODE_MASK) >>
10695 SHARED_HW_CFG_LED_MODE_SHIFT);
10696
c2c8b03e
EG		 10697 bp->link_params.feature_config_flags = 0;
10698 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10699 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10700 bp->link_params.feature_config_flags |=
10701 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10702 else
10703 bp->link_params.feature_config_flags &=
10704 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10705
34f80b04
EG		 10706 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10707 bp->common.bc_ver = val;
10708 BNX2X_DEV_INFO("bc_ver %X\n", val);
10709 if (val < BNX2X_BC_VER) {
10710 /* for now only warn
10711 * later we might need to enforce this */
51c1a580
MS		 10712 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10713 BNX2X_BC_VER, val);
34f80b04 10714 }
4d295db0 10715 bp->link_params.feature_config_flags |=
a22f0788 10716 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 10717 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10718
a22f0788
YR		 10719 bp->link_params.feature_config_flags |=
10720 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10721 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
a3348722
BW		 10722 bp->link_params.feature_config_flags |=
10723 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10724 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
85242eea
YR		 10725 bp->link_params.feature_config_flags |=
10726 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10727 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
55386fe8
YR		 10728
10729 bp->link_params.feature_config_flags |=
10730 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10731 FEATURE_CONFIG_MT_SUPPORT : 0;
10732
0e898dd7
BW		 10733 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10734 BC_SUPPORTS_PFC_STATS : 0;
85242eea 10735
2e499d3c
BW		 10736 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10737 BC_SUPPORTS_FCOE_FEATURES : 0;
10738
9876879f
BW		 10739 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10740 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
a6d3a5ba
BW		 10741
10742 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10743 BC_SUPPORTS_RMMOD_CMD : 0;
10744
1d187b34
BW		 10745 boot_mode = SHMEM_RD(bp,
10746 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10747 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10748 switch (boot_mode) {
10749 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10750 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10751 break;
10752 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10753 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10754 break;
10755 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10756 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10757 break;
10758 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10759 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10760 break;
10761 }
10762
29ed74c3 10763 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
f9a3ebbe
DK		 10764 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10765
72ce58c3 10766 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 10767 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 10768
10769 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10770 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10771 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10772 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10773
cdaa7cb8
VZ		 10774 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10775 val, val2, val3, val4);
34f80b04
EG		 10776}
10777
f2e0899f
DK		 10778#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10779#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10780
0329aba1 10781static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
f2e0899f
DK		 10782{
10783 int pfid = BP_FUNC(bp);
f2e0899f
DK		 10784 int igu_sb_id;
10785 u32 val;
6383c0b3 10786 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 10787
10788 bp->igu_base_sb = 0xff;
f2e0899f 10789 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 10790 int vn = BP_VN(bp);
6383c0b3 10791 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 10792 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10793 FP_SB_MAX_E1x;
10794
10795 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10796 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10797
9b341bb1 10798 return 0;
f2e0899f
DK		 10799 }
10800
10801 /* IGU in normal mode - read CAM */
10802 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10803 igu_sb_id++) {
10804 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10805 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10806 continue;
10807 fid = IGU_FID(val);
10808 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10809 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10810 continue;
10811 if (IGU_VEC(val) == 0)
10812 /* default status block */
10813 bp->igu_dsb_id = igu_sb_id;
10814 else {
10815 if (bp->igu_base_sb == 0xff)
10816 bp->igu_base_sb = igu_sb_id;
6383c0b3 10817 igu_sb_cnt++;
f2e0899f
DK		 10818 }
10819 }
10820 }
619c5cb6 10821
6383c0b3 10822#ifdef CONFIG_PCI_MSI
185d4c8b
AE		 10823 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10824 * optional that number of CAM entries will not be equal to the value
10825 * advertised in PCI.
10826 * Driver should use the minimal value of both as the actual status
10827 * block count
619c5cb6 10828 */
185d4c8b 10829 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
6383c0b3 10830#endif
619c5cb6 10831
9b341bb1 10832 if (igu_sb_cnt == 0) {
f2e0899f 10833 BNX2X_ERR("CAM configuration error\n");
9b341bb1
BW		 10834 return -EINVAL;
10835 }
10836
10837 return 0;
f2e0899f
DK		 10838}
10839
1dd06ae8 10840static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
a2fbb9ea 10841{
a22f0788
YR		 10842 int cfg_size = 0, idx, port = BP_PORT(bp);
10843
10844 /* Aggregation of supported attributes of all external phys */
10845 bp->port.supported[0] = 0;
10846 bp->port.supported[1] = 0;
b7737c9b
YR		 10847 switch (bp->link_params.num_phys) {
10848 case 1:
a22f0788
YR		 10849 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10850 cfg_size = 1;
10851 break;
b7737c9b 10852 case 2:
a22f0788
YR		 10853 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10854 cfg_size = 1;
10855 break;
10856 case 3:
10857 if (bp->link_params.multi_phy_config &
10858 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10859 bp->port.supported[1] =
10860 bp->link_params.phy[EXT_PHY1].supported;
10861 bp->port.supported[0] =
10862 bp->link_params.phy[EXT_PHY2].supported;
10863 } else {
10864 bp->port.supported[0] =
10865 bp->link_params.phy[EXT_PHY1].supported;
10866 bp->port.supported[1] =
10867 bp->link_params.phy[EXT_PHY2].supported;
10868 }
10869 cfg_size = 2;
10870 break;
b7737c9b 10871 }
a2fbb9ea 10872
a22f0788 10873 if (!(bp->port.supported[0] || bp->port.supported[1])) {
51c1a580 10874 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 10875 SHMEM_RD(bp,
a22f0788
YR		 10876 dev_info.port_hw_config[port].external_phy_config),
10877 SHMEM_RD(bp,
10878 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 10879 return;
f85582f8 10880 }
a2fbb9ea 10881
619c5cb6
VZ		 10882 if (CHIP_IS_E3(bp))
10883 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10884 else {
10885 switch (switch_cfg) {
10886 case SWITCH_CFG_1G:
10887 bp->port.phy_addr = REG_RD(
10888 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10889 break;
10890 case SWITCH_CFG_10G:
10891 bp->port.phy_addr = REG_RD(
10892 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10893 break;
10894 default:
10895 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10896 bp->port.link_config[0]);
10897 return;
10898 }
a2fbb9ea 10899 }
619c5cb6 10900 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 10901 /* mask what we support according to speed_cap_mask per configuration */
10902 for (idx = 0; idx < cfg_size; idx++) {
10903 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10904 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 10905 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 10906
a22f0788 10907 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10908 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 10909 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 10910
a22f0788 10911 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10912 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 10913 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 10914
a22f0788 10915 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10916 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 10917 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 10918
a22f0788 10919 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10920 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 10921 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 10922 SUPPORTED_1000baseT_Full);
a2fbb9ea 10923
a22f0788 10924 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10925 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 10926 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 10927
a22f0788 10928 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10929 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788 10930 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
b8e0d884
YR		 10931
10932 if (!(bp->link_params.speed_cap_mask[idx] &
10933 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10934 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
a22f0788 10935 }
a2fbb9ea 10936
a22f0788
YR		 10937 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10938 bp->port.supported[1]);
a2fbb9ea
ET		 10939}
10940
0329aba1 10941static void bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 10942{
a22f0788
YR		 10943 u32 link_config, idx, cfg_size = 0;
10944 bp->port.advertising[0] = 0;
10945 bp->port.advertising[1] = 0;
10946 switch (bp->link_params.num_phys) {
10947 case 1:
10948 case 2:
10949 cfg_size = 1;
10950 break;
10951 case 3:
10952 cfg_size = 2;
10953 break;
10954 }
10955 for (idx = 0; idx < cfg_size; idx++) {
10956 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10957 link_config = bp->port.link_config[idx];
10958 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 10959 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 10960 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10961 bp->link_params.req_line_speed[idx] =
10962 SPEED_AUTO_NEG;
10963 bp->port.advertising[idx] |=
10964 bp->port.supported[idx];
10bd1f24
MY		 10965 if (bp->link_params.phy[EXT_PHY1].type ==
10966 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10967 bp->port.advertising[idx] |=
10968 (SUPPORTED_100baseT_Half |
10969 SUPPORTED_100baseT_Full);
f85582f8
DK		 10970 } else {
10971 /* force 10G, no AN */
a22f0788
YR		 10972 bp->link_params.req_line_speed[idx] =
10973 SPEED_10000;
10974 bp->port.advertising[idx] |=
10975 (ADVERTISED_10000baseT_Full |
f85582f8 10976 ADVERTISED_FIBRE);
a22f0788 10977 continue;
f85582f8
DK		 10978 }
10979 break;
a2fbb9ea 10980
f85582f8 10981 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 10982 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10983 bp->link_params.req_line_speed[idx] =
10984 SPEED_10;
10985 bp->port.advertising[idx] |=
10986 (ADVERTISED_10baseT_Full |
f85582f8
DK		 10987 ADVERTISED_TP);
10988 } else {
51c1a580 10989 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8 10990 link_config,
a22f0788 10991 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 10992 return;
10993 }
10994 break;
a2fbb9ea 10995
f85582f8 10996 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 10997 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10998 bp->link_params.req_line_speed[idx] =
10999 SPEED_10;
11000 bp->link_params.req_duplex[idx] =
11001 DUPLEX_HALF;
11002 bp->port.advertising[idx] |=
11003 (ADVERTISED_10baseT_Half |
f85582f8
DK		 11004 ADVERTISED_TP);
11005 } else {
51c1a580 11006 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 11007 link_config,
11008 bp->link_params.speed_cap_mask[idx]);
11009 return;
11010 }
11011 break;
a2fbb9ea 11012
f85582f8
DK		 11013 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11014 if (bp->port.supported[idx] &
11015 SUPPORTED_100baseT_Full) {
a22f0788
YR		 11016 bp->link_params.req_line_speed[idx] =
11017 SPEED_100;
11018 bp->port.advertising[idx] |=
11019 (ADVERTISED_100baseT_Full |
f85582f8
DK		 11020 ADVERTISED_TP);
11021 } else {
51c1a580 11022 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 11023 link_config,
11024 bp->link_params.speed_cap_mask[idx]);
11025 return;
11026 }
11027 break;
a2fbb9ea 11028
f85582f8
DK		 11029 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11030 if (bp->port.supported[idx] &
11031 SUPPORTED_100baseT_Half) {
11032 bp->link_params.req_line_speed[idx] =
11033 SPEED_100;
11034 bp->link_params.req_duplex[idx] =
11035 DUPLEX_HALF;
a22f0788
YR		 11036 bp->port.advertising[idx] |=
11037 (ADVERTISED_100baseT_Half |
f85582f8
DK		 11038 ADVERTISED_TP);
11039 } else {
51c1a580 11040 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11041 link_config,
11042 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11043 return;
11044 }
11045 break;
a2fbb9ea 11046
f85582f8 11047 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 11048 if (bp->port.supported[idx] &
11049 SUPPORTED_1000baseT_Full) {
11050 bp->link_params.req_line_speed[idx] =
11051 SPEED_1000;
11052 bp->port.advertising[idx] |=
11053 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 11054 ADVERTISED_TP);
11055 } else {
51c1a580 11056 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11057 link_config,
11058 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11059 return;
11060 }
11061 break;
a2fbb9ea 11062
f85582f8 11063 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 11064 if (bp->port.supported[idx] &
11065 SUPPORTED_2500baseX_Full) {
11066 bp->link_params.req_line_speed[idx] =
11067 SPEED_2500;
11068 bp->port.advertising[idx] |=
11069 (ADVERTISED_2500baseX_Full |
34f80b04 11070 ADVERTISED_TP);
f85582f8 11071 } else {
51c1a580 11072 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11073 link_config,
f85582f8
DK		 11074 bp->link_params.speed_cap_mask[idx]);
11075 return;
11076 }
11077 break;
a2fbb9ea 11078
f85582f8 11079 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 11080 if (bp->port.supported[idx] &
11081 SUPPORTED_10000baseT_Full) {
11082 bp->link_params.req_line_speed[idx] =
11083 SPEED_10000;
11084 bp->port.advertising[idx] |=
11085 (ADVERTISED_10000baseT_Full |
34f80b04 11086 ADVERTISED_FIBRE);
f85582f8 11087 } else {
51c1a580 11088 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11089 link_config,
f85582f8
DK		 11090 bp->link_params.speed_cap_mask[idx]);
11091 return;
11092 }
11093 break;
3c9ada22
YR		 11094 case PORT_FEATURE_LINK_SPEED_20G:
11095 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 11096
3c9ada22 11097 break;
f85582f8 11098 default:
51c1a580 11099 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
754a2f52 11100 link_config);
f85582f8
DK		 11101 bp->link_params.req_line_speed[idx] =
11102 SPEED_AUTO_NEG;
11103 bp->port.advertising[idx] =
11104 bp->port.supported[idx];
11105 break;
11106 }
a2fbb9ea 11107
a22f0788 11108 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 11109 PORT_FEATURE_FLOW_CONTROL_MASK);
cd1dfce2
YM		 11110 if (bp->link_params.req_flow_ctrl[idx] ==
11111 BNX2X_FLOW_CTRL_AUTO) {
11112 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11113 bp->link_params.req_flow_ctrl[idx] =
11114 BNX2X_FLOW_CTRL_NONE;
11115 else
11116 bnx2x_set_requested_fc(bp);
a22f0788 11117 }
a2fbb9ea 11118
51c1a580 11119 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
a22f0788
YR		 11120 bp->link_params.req_line_speed[idx],
11121 bp->link_params.req_duplex[idx],
11122 bp->link_params.req_flow_ctrl[idx],
11123 bp->port.advertising[idx]);
11124 }
a2fbb9ea
ET		 11125}
11126
0329aba1 11127static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
e665bfda 11128{
86564c3f
YM		 11129 __be16 mac_hi_be = cpu_to_be16(mac_hi);
11130 __be32 mac_lo_be = cpu_to_be32(mac_lo);
11131 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11132 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
e665bfda
MC		 11133}
11134
0329aba1 11135static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 11136{
34f80b04 11137 int port = BP_PORT(bp);
589abe3a 11138 u32 config;
c8c60d88 11139 u32 ext_phy_type, ext_phy_config, eee_mode;
a2fbb9ea 11140
c18487ee 11141 bp->link_params.bp = bp;
34f80b04 11142 bp->link_params.port = port;
c18487ee 11143
c18487ee 11144 bp->link_params.lane_config =
a2fbb9ea 11145 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 11146
a22f0788 11147 bp->link_params.speed_cap_mask[0] =
a2fbb9ea 11148 SHMEM_RD(bp,
b0261926
YR		 11149 dev_info.port_hw_config[port].speed_capability_mask) &
11150 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788
YR		 11151 bp->link_params.speed_cap_mask[1] =
11152 SHMEM_RD(bp,
b0261926
YR		 11153 dev_info.port_hw_config[port].speed_capability_mask2) &
11154 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788 11155 bp->port.link_config[0] =
a2fbb9ea
ET		 11156 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11157
a22f0788
YR		 11158 bp->port.link_config[1] =
11159 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 11160
a22f0788
YR		 11161 bp->link_params.multi_phy_config =
11162 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 11163 /* If the device is capable of WoL, set the default state according
11164 * to the HW
11165 */
4d295db0 11166 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 11167 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11168 (config & PORT_FEATURE_WOL_ENABLED));
11169
4ba7699b
YM		 11170 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11171 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11172 bp->flags |= NO_ISCSI_FLAG;
11173 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11174 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11175 bp->flags |= NO_FCOE_FLAG;
11176
51c1a580 11177 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 11178 bp->link_params.lane_config,
a22f0788
YR		 11179 bp->link_params.speed_cap_mask[0],
11180 bp->port.link_config[0]);
a2fbb9ea 11181
a22f0788 11182 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 11183 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 11184 bnx2x_phy_probe(&bp->link_params);
c18487ee 11185 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 11186
11187 bnx2x_link_settings_requested(bp);
11188
01cd4528
EG		 11189 /*
11190 * If connected directly, work with the internal PHY, otherwise, work
11191 * with the external PHY
11192 */
b7737c9b
YR		 11193 ext_phy_config =
11194 SHMEM_RD(bp,
11195 dev_info.port_hw_config[port].external_phy_config);
11196 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 11197 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 11198 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 11199
11200 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11201 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11202 bp->mdio.prtad =
b7737c9b 11203 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d 11204
c8c60d88
YM		 11205 /* Configure link feature according to nvram value */
11206 eee_mode = (((SHMEM_RD(bp, dev_info.
11207 port_feature_config[port].eee_power_mode)) &
11208 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11209 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11210 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11211 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11212 EEE_MODE_ENABLE_LPI |
11213 EEE_MODE_OUTPUT_TIME;
11214 } else {
11215 bp->link_params.eee_mode = 0;
11216 }
0793f83f 11217}
01cd4528 11218
b306f5ed 11219void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 11220{
9e62e912 11221 u32 no_flags = NO_ISCSI_FLAG;
bf61ee14 11222 int port = BP_PORT(bp);
2ba45142 11223 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 11224 drv_lic_key[port].max_iscsi_conn);
2ba45142 11225
55c11941
MS		 11226 if (!CNIC_SUPPORT(bp)) {
11227 bp->flags |= no_flags;
11228 return;
11229 }
11230
b306f5ed 11231 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 11232 bp->cnic_eth_dev.max_iscsi_conn =
11233 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11234 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11235
b306f5ed
DK		 11236 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11237 bp->cnic_eth_dev.max_iscsi_conn);
11238
11239 /*
11240 * If maximum allowed number of connections is zero -
11241 * disable the feature.
11242 */
11243 if (!bp->cnic_eth_dev.max_iscsi_conn)
9e62e912 11244 bp->flags |= no_flags;
b306f5ed
DK		 11245}
11246
0329aba1 11247static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
9e62e912
DK		 11248{
11249 /* Port info */
11250 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11251 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11252 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11253 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11254
11255 /* Node info */
11256 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11257 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11258 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11259 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11260}
86800194
DK		 11261
11262static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11263{
11264 u8 count = 0;
11265
11266 if (IS_MF(bp)) {
11267 u8 fid;
11268
11269 /* iterate over absolute function ids for this path: */
11270 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11271 if (IS_MF_SD(bp)) {
11272 u32 cfg = MF_CFG_RD(bp,
11273 func_mf_config[fid].config);
11274
11275 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11276 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11277 FUNC_MF_CFG_PROTOCOL_FCOE))
11278 count++;
11279 } else {
11280 u32 cfg = MF_CFG_RD(bp,
11281 func_ext_config[fid].
11282 func_cfg);
11283
11284 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11285 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11286 count++;
11287 }
11288 }
11289 } else { /* SF */
11290 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11291
11292 for (port = 0; port < port_cnt; port++) {
11293 u32 lic = SHMEM_RD(bp,
11294 drv_lic_key[port].max_fcoe_conn) ^
11295 FW_ENCODE_32BIT_PATTERN;
11296 if (lic)
11297 count++;
11298 }
11299 }
11300
11301 return count;
11302}
11303
0329aba1 11304static void bnx2x_get_fcoe_info(struct bnx2x *bp)
b306f5ed
DK		 11305{
11306 int port = BP_PORT(bp);
11307 int func = BP_ABS_FUNC(bp);
b306f5ed
DK		 11308 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11309 drv_lic_key[port].max_fcoe_conn);
86800194 11310 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
b306f5ed 11311
55c11941
MS		 11312 if (!CNIC_SUPPORT(bp)) {
11313 bp->flags |= NO_FCOE_FLAG;
11314 return;
11315 }
11316
b306f5ed 11317 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 11318 bp->cnic_eth_dev.max_fcoe_conn =
11319 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11320 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11321
0eb43b4b
BPG		 11322 /* Calculate the number of maximum allowed FCoE tasks */
11323 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
86800194
DK		 11324
11325 /* check if FCoE resources must be shared between different functions */
11326 if (num_fcoe_func)
11327 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
0eb43b4b 11328
bf61ee14
VZ		 11329 /* Read the WWN: */
11330 if (!IS_MF(bp)) {
11331 /* Port info */
11332 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11333 SHMEM_RD(bp,
2de67439 11334 dev_info.port_hw_config[port].
bf61ee14
VZ		 11335 fcoe_wwn_port_name_upper);
11336 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11337 SHMEM_RD(bp,
2de67439 11338 dev_info.port_hw_config[port].
bf61ee14
VZ		 11339 fcoe_wwn_port_name_lower);
11340
11341 /* Node info */
11342 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11343 SHMEM_RD(bp,
2de67439 11344 dev_info.port_hw_config[port].
bf61ee14
VZ		 11345 fcoe_wwn_node_name_upper);
11346 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11347 SHMEM_RD(bp,
2de67439 11348 dev_info.port_hw_config[port].
bf61ee14
VZ		 11349 fcoe_wwn_node_name_lower);
11350 } else if (!IS_MF_SD(bp)) {
2e98ffc2 11351 /* Read the WWN info only if the FCoE feature is enabled for
bf61ee14
VZ		 11352 * this function.
11353 */
2e98ffc2
DK		 11354 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11355 bnx2x_get_ext_wwn_info(bp, func);
11356 } else {
11357 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
9e62e912 11358 bnx2x_get_ext_wwn_info(bp, func);
382e513a 11359 }
bf61ee14 11360
b306f5ed 11361 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 11362
bf61ee14
VZ		 11363 /*
11364 * If maximum allowed number of connections is zero -
2ba45142
VZ		 11365 * disable the feature.
11366 */
2ba45142
VZ		 11367 if (!bp->cnic_eth_dev.max_fcoe_conn)
11368 bp->flags |= NO_FCOE_FLAG;
11369}
b306f5ed 11370
0329aba1 11371static void bnx2x_get_cnic_info(struct bnx2x *bp)
b306f5ed
DK		 11372{
11373 /*
11374 * iSCSI may be dynamically disabled but reading
11375 * info here we will decrease memory usage by driver
11376 * if the feature is disabled for good
11377 */
11378 bnx2x_get_iscsi_info(bp);
11379 bnx2x_get_fcoe_info(bp);
11380}
2ba45142 11381
0329aba1 11382static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
0793f83f
DK		 11383{
11384 u32 val, val2;
11385 int func = BP_ABS_FUNC(bp);
11386 int port = BP_PORT(bp);
2ba45142
VZ		 11387 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11388 u8 *fip_mac = bp->fip_mac;
0793f83f 11389
55c11941
MS		 11390 if (IS_MF(bp)) {
11391 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142 11392 * FCoE MAC then the appropriate feature should be disabled.
55c11941
MS		 11393 * In non SD mode features configuration comes from struct
11394 * func_ext_config.
2ba45142 11395 */
2e98ffc2 11396 if (!IS_MF_SD(bp)) {
0793f83f
DK		 11397 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11398 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11399 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11400 iscsi_mac_addr_upper);
0793f83f 11401 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11402 iscsi_mac_addr_lower);
2ba45142 11403 bnx2x_set_mac_buf(iscsi_mac, val, val2);
55c11941
MS		 11404 BNX2X_DEV_INFO
11405 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11406 } else {
2ba45142 11407 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
55c11941 11408 }
2ba45142
VZ		 11409
11410 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11411 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11412 fcoe_mac_addr_upper);
2ba45142 11413 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11414 fcoe_mac_addr_lower);
2ba45142 11415 bnx2x_set_mac_buf(fip_mac, val, val2);
55c11941
MS		 11416 BNX2X_DEV_INFO
11417 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11418 } else {
2ba45142 11419 bp->flags |= NO_FCOE_FLAG;
55c11941 11420 }
a3348722
BW		 11421
11422 bp->mf_ext_config = cfg;
11423
9e62e912 11424 } else { /* SD MODE */
55c11941
MS		 11425 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11426 /* use primary mac as iscsi mac */
11427 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11428
11429 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11430 BNX2X_DEV_INFO
11431 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11432 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11433 /* use primary mac as fip mac */
11434 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11435 BNX2X_DEV_INFO("SD FCoE MODE\n");
11436 BNX2X_DEV_INFO
11437 ("Read FIP MAC: %pM\n", fip_mac);
614c76df 11438 }
0793f83f 11439 }
a3348722 11440
82594f8f
YM		 11441 /* If this is a storage-only interface, use SAN mac as
11442 * primary MAC. Notice that for SD this is already the case,
11443 * as the SAN mac was copied from the primary MAC.
11444 */
11445 if (IS_MF_FCOE_AFEX(bp))
a3348722 11446 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
0793f83f 11447 } else {
0793f83f 11448 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11449 iscsi_mac_upper);
0793f83f 11450 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11451 iscsi_mac_lower);
2ba45142 11452 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 11453
11454 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11455 fcoe_fip_mac_upper);
c03bd39c 11456 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11457 fcoe_fip_mac_lower);
c03bd39c 11458 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 11459 }
11460
55c11941 11461 /* Disable iSCSI OOO if MAC configuration is invalid. */
426b9241 11462 if (!is_valid_ether_addr(iscsi_mac)) {
55c11941 11463 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
426b9241
DK		 11464 memset(iscsi_mac, 0, ETH_ALEN);
11465 }
11466
55c11941 11467 /* Disable FCoE if MAC configuration is invalid. */
426b9241
DK		 11468 if (!is_valid_ether_addr(fip_mac)) {
11469 bp->flags |= NO_FCOE_FLAG;
11470 memset(bp->fip_mac, 0, ETH_ALEN);
11471 }
55c11941
MS		 11472}
11473
0329aba1 11474static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
55c11941
MS		 11475{
11476 u32 val, val2;
11477 int func = BP_ABS_FUNC(bp);
11478 int port = BP_PORT(bp);
11479
11480 /* Zero primary MAC configuration */
11481 memset(bp->dev->dev_addr, 0, ETH_ALEN);
11482
11483 if (BP_NOMCP(bp)) {
11484 BNX2X_ERROR("warning: random MAC workaround active\n");
11485 eth_hw_addr_random(bp->dev);
11486 } else if (IS_MF(bp)) {
11487 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11488 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11489 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11490 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11491 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11492
11493 if (CNIC_SUPPORT(bp))
11494 bnx2x_get_cnic_mac_hwinfo(bp);
11495 } else {
11496 /* in SF read MACs from port configuration */
11497 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11498 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11499 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11500
11501 if (CNIC_SUPPORT(bp))
11502 bnx2x_get_cnic_mac_hwinfo(bp);
11503 }
11504
3d7d562c
YM		 11505 if (!BP_NOMCP(bp)) {
11506 /* Read physical port identifier from shmem */
11507 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11508 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11509 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11510 bp->flags |= HAS_PHYS_PORT_ID;
11511 }
11512
55c11941 11513 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
619c5cb6 11514
2e98ffc2 11515 if (!is_valid_ether_addr(bp->dev->dev_addr))
619c5cb6 11516 dev_err(&bp->pdev->dev,
51c1a580
MS		 11517 "bad Ethernet MAC address configuration: %pM\n"
11518 "change it manually before bringing up the appropriate network interface\n",
0f9dad10 11519 bp->dev->dev_addr);
7964211d 11520}
51c1a580 11521
0329aba1 11522static bool bnx2x_get_dropless_info(struct bnx2x *bp)
7964211d
YM		 11523{
11524 int tmp;
11525 u32 cfg;
51c1a580 11526
aeeddb8b
YM		 11527 if (IS_VF(bp))
11528 return 0;
11529
7964211d
YM		 11530 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11531 /* Take function: tmp = func */
11532 tmp = BP_ABS_FUNC(bp);
11533 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11534 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11535 } else {
11536 /* Take port: tmp = port */
11537 tmp = BP_PORT(bp);
11538 cfg = SHMEM_RD(bp,
11539 dev_info.port_hw_config[tmp].generic_features);
11540 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11541 }
11542 return cfg;
34f80b04
EG		 11543}
11544
0329aba1 11545static int bnx2x_get_hwinfo(struct bnx2x *bp)
34f80b04 11546{
0793f83f 11547 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 11548 int vn;
0793f83f 11549 u32 val = 0;
34f80b04 11550 int rc = 0;
a2fbb9ea 11551
34f80b04 11552 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 11553
6383c0b3
AE		 11554 /*
11555 * initialize IGU parameters
11556 */
f2e0899f
DK		 11557 if (CHIP_IS_E1x(bp)) {
11558 bp->common.int_block = INT_BLOCK_HC;
11559
11560 bp->igu_dsb_id = DEF_SB_IGU_ID;
11561 bp->igu_base_sb = 0;
f2e0899f
DK		 11562 } else {
11563 bp->common.int_block = INT_BLOCK_IGU;
7a06a122 11564
16a5fd92 11565 /* do not allow device reset during IGU info processing */
7a06a122
DK		 11566 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11567
f2e0899f 11568 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 11569
11570 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11571 int tout = 5000;
11572
11573 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11574
11575 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11576 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11577 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11578
11579 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11580 tout--;
0926d499 11581 usleep_range(1000, 2000);
619c5cb6
VZ		 11582 }
11583
11584 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11585 dev_err(&bp->pdev->dev,
11586 "FORCING Normal Mode failed!!!\n");
9b341bb1
BW		 11587 bnx2x_release_hw_lock(bp,
11588 HW_LOCK_RESOURCE_RESET);
619c5cb6
VZ		 11589 return -EPERM;
11590 }
11591 }
11592
f2e0899f 11593 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 11594 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 11595 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11596 } else
619c5cb6 11597 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 11598
9b341bb1 11599 rc = bnx2x_get_igu_cam_info(bp);
7a06a122 11600 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9b341bb1
BW		 11601 if (rc)
11602 return rc;
f2e0899f 11603 }
619c5cb6
VZ		 11604
11605 /*
11606 * set base FW non-default (fast path) status block id, this value is
11607 * used to initialize the fw_sb_id saved on the fp/queue structure to
11608 * determine the id used by the FW.
11609 */
11610 if (CHIP_IS_E1x(bp))
11611 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11612 else /*
11613 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11614 * the same queue are indicated on the same IGU SB). So we prefer
11615 * FW and IGU SBs to be the same value.
11616 */
11617 bp->base_fw_ndsb = bp->igu_base_sb;
11618
11619 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11620 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11621 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 11622
11623 /*
11624 * Initialize MF configuration
11625 */
523224a3 11626
fb3bff17
DK		 11627 bp->mf_ov = 0;
11628 bp->mf_mode = 0;
3395a033 11629 vn = BP_VN(bp);
0793f83f 11630
f2e0899f 11631 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 11632 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11633 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11634 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11635
f2e0899f
DK		 11636 if (SHMEM2_HAS(bp, mf_cfg_addr))
11637 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11638 else
11639 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 11640 offsetof(struct shmem_region, func_mb) +
11641 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 11642 /*
11643 * get mf configuration:
16a5fd92 11644 * 1. Existence of MF configuration
0793f83f
DK		 11645 * 2. MAC address must be legal (check only upper bytes)
11646 * for Switch-Independent mode;
11647 * OVLAN must be legal for Switch-Dependent mode
11648 * 3. SF_MODE configures specific MF mode
11649 */
11650 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11651 /* get mf configuration */
11652 val = SHMEM_RD(bp,
11653 dev_info.shared_feature_config.config);
11654 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11655
11656 switch (val) {
11657 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11658 val = MF_CFG_RD(bp, func_mf_config[func].
11659 mac_upper);
11660 /* check for legal mac (upper bytes)*/
11661 if (val != 0xffff) {
11662 bp->mf_mode = MULTI_FUNCTION_SI;
11663 bp->mf_config[vn] = MF_CFG_RD(bp,
11664 func_mf_config[func].config);
11665 } else
51c1a580 11666 BNX2X_DEV_INFO("illegal MAC address for SI\n");
0793f83f 11667 break;
a3348722
BW		 11668 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11669 if ((!CHIP_IS_E1x(bp)) &&
11670 (MF_CFG_RD(bp, func_mf_config[func].
11671 mac_upper) != 0xffff) &&
11672 (SHMEM2_HAS(bp,
11673 afex_driver_support))) {
11674 bp->mf_mode = MULTI_FUNCTION_AFEX;
11675 bp->mf_config[vn] = MF_CFG_RD(bp,
11676 func_mf_config[func].config);
11677 } else {
11678 BNX2X_DEV_INFO("can not configure afex mode\n");
11679 }
11680 break;
0793f83f
DK		 11681 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11682 /* get OV configuration */
11683 val = MF_CFG_RD(bp,
11684 func_mf_config[FUNC_0].e1hov_tag);
11685 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11686
11687 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11688 bp->mf_mode = MULTI_FUNCTION_SD;
11689 bp->mf_config[vn] = MF_CFG_RD(bp,
11690 func_mf_config[func].config);
11691 } else
754a2f52 11692 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f 11693 break;
3786b942
AE		 11694 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11695 bp->mf_config[vn] = 0;
11696 break;
0793f83f
DK		 11697 default:
11698 /* Unknown configuration: reset mf_config */
11699 bp->mf_config[vn] = 0;
51c1a580 11700 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
0793f83f
DK		 11701 }
11702 }
a2fbb9ea 11703
2691d51d 11704 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 11705 IS_MF(bp) ? "multi" : "single");
2691d51d 11706
0793f83f
DK		 11707 switch (bp->mf_mode) {
11708 case MULTI_FUNCTION_SD:
11709 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11710 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 11711 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 11712 bp->mf_ov = val;
619c5cb6
VZ		 11713 bp->path_has_ovlan = true;
11714
51c1a580
MS		 11715 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11716 func, bp->mf_ov, bp->mf_ov);
2691d51d 11717 } else {
619c5cb6 11718 dev_err(&bp->pdev->dev,
51c1a580
MS		 11719 "No valid MF OV for func %d, aborting\n",
11720 func);
619c5cb6 11721 return -EPERM;
34f80b04 11722 }
0793f83f 11723 break;
a3348722
BW		 11724 case MULTI_FUNCTION_AFEX:
11725 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11726 break;
0793f83f 11727 case MULTI_FUNCTION_SI:
51c1a580
MS		 11728 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11729 func);
0793f83f
DK		 11730 break;
11731 default:
11732 if (vn) {
619c5cb6 11733 dev_err(&bp->pdev->dev,
51c1a580
MS		 11734 "VN %d is in a single function mode, aborting\n",
11735 vn);
619c5cb6 11736 return -EPERM;
2691d51d 11737 }
0793f83f 11738 break;
34f80b04 11739 }
0793f83f 11740
619c5cb6
VZ		 11741 /* check if other port on the path needs ovlan:
11742 * Since MF configuration is shared between ports
11743 * Possible mixed modes are only
11744 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11745 */
11746 if (CHIP_MODE_IS_4_PORT(bp) &&
11747 !bp->path_has_ovlan &&
11748 !IS_MF(bp) &&
11749 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11750 u8 other_port = !BP_PORT(bp);
11751 u8 other_func = BP_PATH(bp) + 2*other_port;
11752 val = MF_CFG_RD(bp,
11753 func_mf_config[other_func].e1hov_tag);
11754 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11755 bp->path_has_ovlan = true;
11756 }
34f80b04 11757 }
a2fbb9ea 11758
e848582c
DK		 11759 /* adjust igu_sb_cnt to MF for E1H */
11760 if (CHIP_IS_E1H(bp) && IS_MF(bp))
11761 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
523224a3 11762
619c5cb6
VZ		 11763 /* port info */
11764 bnx2x_get_port_hwinfo(bp);
f2e0899f 11765
0793f83f
DK		 11766 /* Get MAC addresses */
11767 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 11768
2ba45142 11769 bnx2x_get_cnic_info(bp);
2ba45142 11770
34f80b04
EG		 11771 return rc;
11772}
11773
0329aba1 11774static void bnx2x_read_fwinfo(struct bnx2x *bp)
34f24c7f
VZ		 11775{
11776 int cnt, i, block_end, rodi;
fcdf95cb 11777 char vpd_start[BNX2X_VPD_LEN+1];
34f24c7f
VZ		 11778 char str_id_reg[VENDOR_ID_LEN+1];
11779 char str_id_cap[VENDOR_ID_LEN+1];
fcdf95cb
BW		 11780 char *vpd_data;
11781 char *vpd_extended_data = NULL;
34f24c7f
VZ		 11782 u8 len;
11783
fcdf95cb 11784 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
34f24c7f
VZ		 11785 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11786
11787 if (cnt < BNX2X_VPD_LEN)
11788 goto out_not_found;
11789
fcdf95cb
BW		 11790 /* VPD RO tag should be first tag after identifier string, hence
11791 * we should be able to find it in first BNX2X_VPD_LEN chars
11792 */
11793 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
34f24c7f
VZ		 11794 PCI_VPD_LRDT_RO_DATA);
11795 if (i < 0)
11796 goto out_not_found;
11797
34f24c7f 11798 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
fcdf95cb 11799 pci_vpd_lrdt_size(&vpd_start[i]);
34f24c7f
VZ		 11800
11801 i += PCI_VPD_LRDT_TAG_SIZE;
11802
fcdf95cb
BW		 11803 if (block_end > BNX2X_VPD_LEN) {
11804 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11805 if (vpd_extended_data == NULL)
11806 goto out_not_found;
11807
11808 /* read rest of vpd image into vpd_extended_data */
11809 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11810 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11811 block_end - BNX2X_VPD_LEN,
11812 vpd_extended_data + BNX2X_VPD_LEN);
11813 if (cnt < (block_end - BNX2X_VPD_LEN))
11814 goto out_not_found;
11815 vpd_data = vpd_extended_data;
11816 } else
11817 vpd_data = vpd_start;
11818
11819 /* now vpd_data holds full vpd content in both cases */
34f24c7f
VZ		 11820
11821 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11822 PCI_VPD_RO_KEYWORD_MFR_ID);
11823 if (rodi < 0)
11824 goto out_not_found;
11825
11826 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11827
11828 if (len != VENDOR_ID_LEN)
11829 goto out_not_found;
11830
11831 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11832
11833 /* vendor specific info */
11834 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11835 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11836 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11837 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11838
11839 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11840 PCI_VPD_RO_KEYWORD_VENDOR0);
11841 if (rodi >= 0) {
11842 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11843
11844 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11845
11846 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11847 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11848 bp->fw_ver[len] = ' ';
11849 }
11850 }
fcdf95cb 11851 kfree(vpd_extended_data);
34f24c7f
VZ		 11852 return;
11853 }
11854out_not_found:
fcdf95cb 11855 kfree(vpd_extended_data);
34f24c7f
VZ		 11856 return;
11857}
11858
0329aba1 11859static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
619c5cb6
VZ		 11860{
11861 u32 flags = 0;
11862
11863 if (CHIP_REV_IS_FPGA(bp))
11864 SET_FLAGS(flags, MODE_FPGA);
11865 else if (CHIP_REV_IS_EMUL(bp))
11866 SET_FLAGS(flags, MODE_EMUL);
11867 else
11868 SET_FLAGS(flags, MODE_ASIC);
11869
11870 if (CHIP_MODE_IS_4_PORT(bp))
11871 SET_FLAGS(flags, MODE_PORT4);
11872 else
11873 SET_FLAGS(flags, MODE_PORT2);
11874
11875 if (CHIP_IS_E2(bp))
11876 SET_FLAGS(flags, MODE_E2);
11877 else if (CHIP_IS_E3(bp)) {
11878 SET_FLAGS(flags, MODE_E3);
11879 if (CHIP_REV(bp) == CHIP_REV_Ax)
11880 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 11881 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11882 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 11883 }
11884
11885 if (IS_MF(bp)) {
11886 SET_FLAGS(flags, MODE_MF);
11887 switch (bp->mf_mode) {
11888 case MULTI_FUNCTION_SD:
11889 SET_FLAGS(flags, MODE_MF_SD);
11890 break;
11891 case MULTI_FUNCTION_SI:
11892 SET_FLAGS(flags, MODE_MF_SI);
11893 break;
a3348722
BW		 11894 case MULTI_FUNCTION_AFEX:
11895 SET_FLAGS(flags, MODE_MF_AFEX);
11896 break;
619c5cb6
VZ		 11897 }
11898 } else
11899 SET_FLAGS(flags, MODE_SF);
11900
11901#if defined(__LITTLE_ENDIAN)
11902 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11903#else /*(__BIG_ENDIAN)*/
11904 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11905#endif
11906 INIT_MODE_FLAGS(bp) = flags;
11907}
11908
0329aba1 11909static int bnx2x_init_bp(struct bnx2x *bp)
34f80b04 11910{
f2e0899f 11911 int func;
34f80b04
EG		 11912 int rc;
11913
34f80b04 11914 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 11915 mutex_init(&bp->fw_mb_mutex);
42f8277f
YM		 11916 mutex_init(&bp->drv_info_mutex);
11917 bp->drv_info_mng_owner = false;
bb7e95c8 11918 spin_lock_init(&bp->stats_lock);
507393eb 11919 sema_init(&bp->stats_sema, 1);
55c11941 11920
1cf167f2 11921 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 11922 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 11923 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
370d4a26 11924 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
1ab4434c
AE		 11925 if (IS_PF(bp)) {
11926 rc = bnx2x_get_hwinfo(bp);
11927 if (rc)
11928 return rc;
11929 } else {
e09b74d0 11930 eth_zero_addr(bp->dev->dev_addr);
1ab4434c 11931 }
34f80b04 11932
619c5cb6
VZ		 11933 bnx2x_set_modes_bitmap(bp);
11934
11935 rc = bnx2x_alloc_mem_bp(bp);
11936 if (rc)
11937 return rc;
523224a3 11938
34f24c7f 11939 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 11940
11941 func = BP_FUNC(bp);
11942
34f80b04 11943 /* need to reset chip if undi was active */
1ab4434c 11944 if (IS_PF(bp) && !BP_NOMCP(bp)) {
452427b0
YM		 11945 /* init fw_seq */
11946 bp->fw_seq =
11947 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11948 DRV_MSG_SEQ_NUMBER_MASK;
11949 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11950
91ebb929
YM		 11951 rc = bnx2x_prev_unload(bp);
11952 if (rc) {
11953 bnx2x_free_mem_bp(bp);
11954 return rc;
11955 }
452427b0
YM		 11956 }
11957
34f80b04 11958 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 11959 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 11960
11961 if (BP_NOMCP(bp) && (func == 0))
51c1a580 11962 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
34f80b04 11963
614c76df 11964 bp->disable_tpa = disable_tpa;
2e98ffc2 11965 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
94d9de3c 11966 /* Reduce memory usage in kdump environment by disabling TPA */
c9931896 11967 bp->disable_tpa |= is_kdump_kernel();
614c76df 11968
7a9b2557 11969 /* Set TPA flags */
614c76df 11970 if (bp->disable_tpa) {
621b4d66 11971 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 11972 bp->dev->features &= ~NETIF_F_LRO;
11973 } else {
621b4d66 11974 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 11975 bp->dev->features |= NETIF_F_LRO;
11976 }
11977
a18f5128
EG		 11978 if (CHIP_IS_E1(bp))
11979 bp->dropless_fc = 0;
11980 else
7964211d 11981 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
a18f5128 11982
8d5726c4 11983 bp->mrrs = mrrs;
7a9b2557 11984
2e98ffc2 11985 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
1ab4434c
AE		 11986 if (IS_VF(bp))
11987 bp->rx_ring_size = MAX_RX_AVAIL;
34f80b04 11988
7d323bfd 11989 /* make sure that the numbers are in the right granularity */
523224a3
DK		 11990 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11991 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 11992
fc543637 11993 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
34f80b04
EG		 11994
11995 init_timer(&bp->timer);
11996 bp->timer.expires = jiffies + bp->current_interval;
11997 bp->timer.data = (unsigned long) bp;
11998 bp->timer.function = bnx2x_timer;
11999
0370cf90
BW		 12000 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12001 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12002 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12003 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12004 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12005 bnx2x_dcbx_init_params(bp);
12006 } else {
12007 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12008 }
e4901dde 12009
619c5cb6
VZ		 12010 if (CHIP_IS_E1x(bp))
12011 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12012 else
12013 bp->cnic_base_cl_id = FP_SB_MAX_E2;
619c5cb6 12014
6383c0b3 12015 /* multiple tx priority */
1ab4434c
AE		 12016 if (IS_VF(bp))
12017 bp->max_cos = 1;
12018 else if (CHIP_IS_E1x(bp))
6383c0b3 12019 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
1ab4434c 12020 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
6383c0b3 12021 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
1ab4434c 12022 else if (CHIP_IS_E3B0(bp))
6383c0b3 12023 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
1ab4434c
AE		 12024 else
12025 BNX2X_ERR("unknown chip %x revision %x\n",
12026 CHIP_NUM(bp), CHIP_REV(bp));
12027 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
6383c0b3 12028
55c11941
MS		 12029 /* We need at least one default status block for slow-path events,
12030 * second status block for the L2 queue, and a third status block for
16a5fd92 12031 * CNIC if supported.
55c11941 12032 */
60cad4e6
AE		 12033 if (IS_VF(bp))
12034 bp->min_msix_vec_cnt = 1;
12035 else if (CNIC_SUPPORT(bp))
55c11941 12036 bp->min_msix_vec_cnt = 3;
60cad4e6 12037 else /* PF w/o cnic */
55c11941
MS		 12038 bp->min_msix_vec_cnt = 2;
12039 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12040
5bb680d6
MS		 12041 bp->dump_preset_idx = 1;
12042
eeed018c
MK		 12043 if (CHIP_IS_E3B0(bp))
12044 bp->flags |= PTP_SUPPORTED;
12045
34f80b04 12046 return rc;
a2fbb9ea
ET		 12047}
12048
de0c62db
DK		 12049/****************************************************************************
12050* General service functions
12051****************************************************************************/
a2fbb9ea 12052
619c5cb6
VZ		 12053/*
12054 * net_device service functions
12055 */
12056
bb2a0f7a 12057/* called with rtnl_lock */
a2fbb9ea
ET		 12058static int bnx2x_open(struct net_device *dev)
12059{
12060 struct bnx2x *bp = netdev_priv(dev);
8395be5e 12061 int rc;
a2fbb9ea 12062
1355b704
MY		 12063 bp->stats_init = true;
12064
6eccabb3
EG		 12065 netif_carrier_off(dev);
12066
a2fbb9ea
ET		 12067 bnx2x_set_power_state(bp, PCI_D0);
12068
ad5afc89 12069 /* If parity had happen during the unload, then attentions
c9ee9206
VZ		 12070 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12071 * want the first function loaded on the current engine to
12072 * complete the recovery.
ad5afc89 12073 * Parity recovery is only relevant for PF driver.
c9ee9206 12074 */
ad5afc89 12075 if (IS_PF(bp)) {
1a6974b2
YM		 12076 int other_engine = BP_PATH(bp) ? 0 : 1;
12077 bool other_load_status, load_status;
12078 bool global = false;
12079
ad5afc89
AE		 12080 other_load_status = bnx2x_get_load_status(bp, other_engine);
12081 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12082 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12083 bnx2x_chk_parity_attn(bp, &global, true)) {
12084 do {
12085 /* If there are attentions and they are in a
12086 * global blocks, set the GLOBAL_RESET bit
12087 * regardless whether it will be this function
12088 * that will complete the recovery or not.
12089 */
12090 if (global)
12091 bnx2x_set_reset_global(bp);
72fd0718 12092
ad5afc89
AE		 12093 /* Only the first function on the current
12094 * engine should try to recover in open. In case
12095 * of attentions in global blocks only the first
12096 * in the chip should try to recover.
12097 */
12098 if ((!load_status &&
12099 (!global || !other_load_status)) &&
12100 bnx2x_trylock_leader_lock(bp) &&
12101 !bnx2x_leader_reset(bp)) {
12102 netdev_info(bp->dev,
12103 "Recovered in open\n");
12104 break;
12105 }
72fd0718 12106
ad5afc89
AE		 12107 /* recovery has failed... */
12108 bnx2x_set_power_state(bp, PCI_D3hot);
12109 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 12110
ad5afc89
AE		 12111 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12112 "If you still see this message after a few retries then power cycle is required.\n");
72fd0718 12113
ad5afc89
AE		 12114 return -EAGAIN;
12115 } while (0);
12116 }
12117 }
72fd0718
VZ		 12118
12119 bp->recovery_state = BNX2X_RECOVERY_DONE;
8395be5e
AE		 12120 rc = bnx2x_nic_load(bp, LOAD_OPEN);
12121 if (rc)
12122 return rc;
9a8130bc 12123 return 0;
a2fbb9ea
ET		 12124}
12125
bb2a0f7a 12126/* called with rtnl_lock */
56ad3152 12127static int bnx2x_close(struct net_device *dev)
a2fbb9ea 12128{
a2fbb9ea
ET		 12129 struct bnx2x *bp = netdev_priv(dev);
12130
12131 /* Unload the driver, release IRQs */
5d07d868 12132 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
c9ee9206 12133
a2fbb9ea
ET		 12134 return 0;
12135}
12136
1191cb83
ED		 12137static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12138 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 12139{
619c5cb6
VZ		 12140 int mc_count = netdev_mc_count(bp->dev);
12141 struct bnx2x_mcast_list_elem *mc_mac =
cd2b0389 12142 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
619c5cb6 12143 struct netdev_hw_addr *ha;
6e30dd4e 12144
619c5cb6
VZ		 12145 if (!mc_mac)
12146 return -ENOMEM;
6e30dd4e 12147
619c5cb6 12148 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 12149
619c5cb6
VZ		 12150 netdev_for_each_mc_addr(ha, bp->dev) {
12151 mc_mac->mac = bnx2x_mc_addr(ha);
12152 list_add_tail(&mc_mac->link, &p->mcast_list);
12153 mc_mac++;
6e30dd4e 12154 }
619c5cb6
VZ		 12155
12156 p->mcast_list_len = mc_count;
12157
12158 return 0;
6e30dd4e
VZ		 12159}
12160
1191cb83 12161static void bnx2x_free_mcast_macs_list(
619c5cb6
VZ		 12162 struct bnx2x_mcast_ramrod_params *p)
12163{
12164 struct bnx2x_mcast_list_elem *mc_mac =
12165 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12166 link);
12167
12168 WARN_ON(!mc_mac);
12169 kfree(mc_mac);
12170}
12171
12172/**
12173 * bnx2x_set_uc_list - configure a new unicast MACs list.
12174 *
12175 * @bp: driver handle
6e30dd4e 12176 *
619c5cb6 12177 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 12178 */
1191cb83 12179static int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 12180{
619c5cb6 12181 int rc;
6e30dd4e 12182 struct net_device *dev = bp->dev;
6e30dd4e 12183 struct netdev_hw_addr *ha;
15192a8c 12184 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
619c5cb6 12185 unsigned long ramrod_flags = 0;
6e30dd4e 12186
619c5cb6
VZ		 12187 /* First schedule a cleanup up of old configuration */
12188 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12189 if (rc < 0) {
12190 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12191 return rc;
12192 }
6e30dd4e
VZ		 12193
12194 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 12195 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12196 BNX2X_UC_LIST_MAC, &ramrod_flags);
7b5342d9
YM		 12197 if (rc == -EEXIST) {
12198 DP(BNX2X_MSG_SP,
12199 "Failed to schedule ADD operations: %d\n", rc);
12200 /* do not treat adding same MAC as error */
12201 rc = 0;
12202
12203 } else if (rc < 0) {
12204
619c5cb6
VZ		 12205 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12206 rc);
12207 return rc;
6e30dd4e
VZ		 12208 }
12209 }
12210
619c5cb6
VZ		 12211 /* Execute the pending commands */
12212 __set_bit(RAMROD_CONT, &ramrod_flags);
12213 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12214 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 12215}
12216
1191cb83 12217static int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 12218{
619c5cb6 12219 struct net_device *dev = bp->dev;
3b603066 12220 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6 12221 int rc = 0;
6e30dd4e 12222
619c5cb6 12223 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 12224
619c5cb6
VZ		 12225 /* first, clear all configured multicast MACs */
12226 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12227 if (rc < 0) {
51c1a580 12228 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
619c5cb6
VZ		 12229 return rc;
12230 }
6e30dd4e 12231
619c5cb6
VZ		 12232 /* then, configure a new MACs list */
12233 if (netdev_mc_count(dev)) {
12234 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12235 if (rc) {
51c1a580
MS		 12236 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12237 rc);
619c5cb6
VZ		 12238 return rc;
12239 }
6e30dd4e 12240
619c5cb6
VZ		 12241 /* Now add the new MACs */
12242 rc = bnx2x_config_mcast(bp, &rparam,
12243 BNX2X_MCAST_CMD_ADD);
12244 if (rc < 0)
51c1a580
MS		 12245 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12246 rc);
6e30dd4e 12247
619c5cb6
VZ		 12248 bnx2x_free_mcast_macs_list(&rparam);
12249 }
6e30dd4e 12250
619c5cb6 12251 return rc;
6e30dd4e
VZ		 12252}
12253
619c5cb6 12254/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
a8f47eb7 12255static void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 12256{
12257 struct bnx2x *bp = netdev_priv(dev);
34f80b04
EG		 12258
12259 if (bp->state != BNX2X_STATE_OPEN) {
12260 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12261 return;
8b09be5f
YM		 12262 } else {
12263 /* Schedule an SP task to handle rest of change */
230bb0f3
YM		 12264 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12265 NETIF_MSG_IFUP);
34f80b04 12266 }
8b09be5f
YM		 12267}
12268
12269void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12270{
12271 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04 12272
619c5cb6 12273 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04 12274
8b09be5f
YM		 12275 netif_addr_lock_bh(bp->dev);
12276
12277 if (bp->dev->flags & IFF_PROMISC) {
34f80b04 12278 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f
YM		 12279 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12280 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12281 CHIP_IS_E1(bp))) {
34f80b04 12282 rx_mode = BNX2X_RX_MODE_ALLMULTI;
8b09be5f 12283 } else {
381ac16b
AE		 12284 if (IS_PF(bp)) {
12285 /* some multicasts */
12286 if (bnx2x_set_mc_list(bp) < 0)
12287 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 12288
8b09be5f
YM		 12289 /* release bh lock, as bnx2x_set_uc_list might sleep */
12290 netif_addr_unlock_bh(bp->dev);
381ac16b
AE		 12291 if (bnx2x_set_uc_list(bp) < 0)
12292 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f 12293 netif_addr_lock_bh(bp->dev);
381ac16b
AE		 12294 } else {
12295 /* configuring mcast to a vf involves sleeping (when we
8b09be5f 12296 * wait for the pf's response).
381ac16b 12297 */
230bb0f3
YM		 12298 bnx2x_schedule_sp_rtnl(bp,
12299 BNX2X_SP_RTNL_VFPF_MCAST, 0);
381ac16b 12300 }
34f80b04
EG		 12301 }
12302
12303 bp->rx_mode = rx_mode;
614c76df 12304 /* handle ISCSI SD mode */
2e98ffc2 12305 if (IS_MF_ISCSI_ONLY(bp))
614c76df 12306 bp->rx_mode = BNX2X_RX_MODE_NONE;
619c5cb6
VZ		 12307
12308 /* Schedule the rx_mode command */
12309 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12310 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8b09be5f 12311 netif_addr_unlock_bh(bp->dev);
619c5cb6
VZ		 12312 return;
12313 }
12314
381ac16b
AE		 12315 if (IS_PF(bp)) {
12316 bnx2x_set_storm_rx_mode(bp);
8b09be5f 12317 netif_addr_unlock_bh(bp->dev);
381ac16b 12318 } else {
8b09be5f
YM		 12319 /* VF will need to request the PF to make this change, and so
12320 * the VF needs to release the bottom-half lock prior to the
12321 * request (as it will likely require sleep on the VF side)
381ac16b 12322 */
8b09be5f
YM		 12323 netif_addr_unlock_bh(bp->dev);
12324 bnx2x_vfpf_storm_rx_mode(bp);
381ac16b 12325 }
34f80b04
EG		 12326}
12327
c18487ee 12328/* called with rtnl_lock */
01cd4528
EG		 12329static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12330 int devad, u16 addr)
a2fbb9ea 12331{
01cd4528
EG		 12332 struct bnx2x *bp = netdev_priv(netdev);
12333 u16 value;
12334 int rc;
a2fbb9ea 12335
01cd4528
EG		 12336 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12337 prtad, devad, addr);
a2fbb9ea 12338
01cd4528
EG		 12339 /* The HW expects different devad if CL22 is used */
12340 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 12341
01cd4528 12342 bnx2x_acquire_phy_lock(bp);
e10bc84d 12343 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 12344 bnx2x_release_phy_lock(bp);
12345 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 12346
01cd4528
EG		 12347 if (!rc)
12348 rc = value;
12349 return rc;
12350}
a2fbb9ea 12351
01cd4528
EG		 12352/* called with rtnl_lock */
12353static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12354 u16 addr, u16 value)
12355{
12356 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 12357 int rc;
12358
51c1a580
MS		 12359 DP(NETIF_MSG_LINK,
12360 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12361 prtad, devad, addr, value);
01cd4528 12362
01cd4528
EG		 12363 /* The HW expects different devad if CL22 is used */
12364 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 12365
01cd4528 12366 bnx2x_acquire_phy_lock(bp);
e10bc84d 12367 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 12368 bnx2x_release_phy_lock(bp);
12369 return rc;
12370}
c18487ee 12371
01cd4528
EG		 12372/* called with rtnl_lock */
12373static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12374{
12375 struct bnx2x *bp = netdev_priv(dev);
12376 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 12377
01cd4528
EG		 12378 if (!netif_running(dev))
12379 return -EAGAIN;
12380
eeed018c
MK		 12381 switch (cmd) {
12382 case SIOCSHWTSTAMP:
12383 return bnx2x_hwtstamp_ioctl(bp, ifr);
12384 default:
12385 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12386 mdio->phy_id, mdio->reg_num, mdio->val_in);
12387 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12388 }
a2fbb9ea
ET		 12389}
12390
257ddbda 12391#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 12392static void poll_bnx2x(struct net_device *dev)
12393{
12394 struct bnx2x *bp = netdev_priv(dev);
14a15d61 12395 int i;
a2fbb9ea 12396
14a15d61
MS		 12397 for_each_eth_queue(bp, i) {
12398 struct bnx2x_fastpath *fp = &bp->fp[i];
12399 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12400 }
a2fbb9ea
ET		 12401}
12402#endif
12403
614c76df
DK		 12404static int bnx2x_validate_addr(struct net_device *dev)
12405{
12406 struct bnx2x *bp = netdev_priv(dev);
12407
e09b74d0
AE		 12408 /* query the bulletin board for mac address configured by the PF */
12409 if (IS_VF(bp))
12410 bnx2x_sample_bulletin(bp);
12411
2e98ffc2 12412 if (!is_valid_ether_addr(dev->dev_addr)) {
51c1a580 12413 BNX2X_ERR("Non-valid Ethernet address\n");
614c76df 12414 return -EADDRNOTAVAIL;
51c1a580 12415 }
614c76df
DK		 12416 return 0;
12417}
12418
3d7d562c
YM		 12419static int bnx2x_get_phys_port_id(struct net_device *netdev,
12420 struct netdev_phys_port_id *ppid)
12421{
12422 struct bnx2x *bp = netdev_priv(netdev);
12423
12424 if (!(bp->flags & HAS_PHYS_PORT_ID))
12425 return -EOPNOTSUPP;
12426
12427 ppid->id_len = sizeof(bp->phys_port_id);
12428 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12429
12430 return 0;
12431}
12432
c64213cd
SH		 12433static const struct net_device_ops bnx2x_netdev_ops = {
12434 .ndo_open = bnx2x_open,
12435 .ndo_stop = bnx2x_close,
12436 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 12437 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 12438 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 12439 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 12440 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 12441 .ndo_do_ioctl = bnx2x_ioctl,
12442 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 12443 .ndo_fix_features = bnx2x_fix_features,
12444 .ndo_set_features = bnx2x_set_features,
c64213cd 12445 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 12446#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 12447 .ndo_poll_controller = poll_bnx2x,
12448#endif
6383c0b3 12449 .ndo_setup_tc = bnx2x_setup_tc,
6411280a 12450#ifdef CONFIG_BNX2X_SRIOV
abc5a021 12451 .ndo_set_vf_mac = bnx2x_set_vf_mac,
3cdeec22 12452 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
3ec9f9ca 12453 .ndo_get_vf_config = bnx2x_get_vf_config,
6411280a 12454#endif
55c11941 12455#ifdef NETDEV_FCOE_WWNN
bf61ee14
VZ		 12456 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
12457#endif
8f20aa57 12458
e0d1095a 12459#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 12460 .ndo_busy_poll = bnx2x_low_latency_recv,
8f20aa57 12461#endif
3d7d562c 12462 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
6495d15a 12463 .ndo_set_vf_link_state = bnx2x_set_vf_link_state,
c64213cd
SH		 12464};
12465
1191cb83 12466static int bnx2x_set_coherency_mask(struct bnx2x *bp)
619c5cb6
VZ		 12467{
12468 struct device *dev = &bp->pdev->dev;
12469
8ceafbfa
LT		 12470 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12471 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
619c5cb6
VZ		 12472 dev_err(dev, "System does not support DMA, aborting\n");
12473 return -EIO;
12474 }
12475
12476 return 0;
12477}
12478
33d8e6a5
YM		 12479static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12480{
12481 if (bp->flags & AER_ENABLED) {
12482 pci_disable_pcie_error_reporting(bp->pdev);
12483 bp->flags &= ~AER_ENABLED;
12484 }
12485}
12486
1ab4434c
AE		 12487static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12488 struct net_device *dev, unsigned long board_type)
a2fbb9ea 12489{
a2fbb9ea 12490 int rc;
c22610d0 12491 u32 pci_cfg_dword;
65087cfe
AE		 12492 bool chip_is_e1x = (board_type == BCM57710 ||
12493 board_type == BCM57711 ||
12494 board_type == BCM57711E);
a2fbb9ea
ET		 12495
12496 SET_NETDEV_DEV(dev, &pdev->dev);
a2fbb9ea 12497
34f80b04
EG		 12498 bp->dev = dev;
12499 bp->pdev = pdev;
a2fbb9ea
ET		 12500
12501 rc = pci_enable_device(pdev);
12502 if (rc) {
cdaa7cb8
VZ		 12503 dev_err(&bp->pdev->dev,
12504 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 12505 goto err_out;
12506 }
12507
12508 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 12509 dev_err(&bp->pdev->dev,
12510 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 12511 rc = -ENODEV;
12512 goto err_out_disable;
12513 }
12514
1ab4434c
AE		 12515 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12516 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
a2fbb9ea
ET		 12517 rc = -ENODEV;
12518 goto err_out_disable;
12519 }
12520
092a5fc9
YR		 12521 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12522 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12523 PCICFG_REVESION_ID_ERROR_VAL) {
12524 pr_err("PCI device error, probably due to fan failure, aborting\n");
12525 rc = -ENODEV;
12526 goto err_out_disable;
12527 }
12528
34f80b04
EG		 12529 if (atomic_read(&pdev->enable_cnt) == 1) {
12530 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12531 if (rc) {
cdaa7cb8
VZ		 12532 dev_err(&bp->pdev->dev,
12533 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 12534 goto err_out_disable;
12535 }
a2fbb9ea 12536
34f80b04
EG		 12537 pci_set_master(pdev);
12538 pci_save_state(pdev);
12539 }
a2fbb9ea 12540
1ab4434c 12541 if (IS_PF(bp)) {
29ed74c3 12542 if (!pdev->pm_cap) {
1ab4434c
AE		 12543 dev_err(&bp->pdev->dev,
12544 "Cannot find power management capability, aborting\n");
12545 rc = -EIO;
12546 goto err_out_release;
12547 }
a2fbb9ea
ET		 12548 }
12549
77c98e6a 12550 if (!pci_is_pcie(pdev)) {
51c1a580 12551 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 12552 rc = -EIO;
12553 goto err_out_release;
12554 }
12555
619c5cb6
VZ		 12556 rc = bnx2x_set_coherency_mask(bp);
12557 if (rc)
a2fbb9ea 12558 goto err_out_release;
a2fbb9ea 12559
34f80b04
EG		 12560 dev->mem_start = pci_resource_start(pdev, 0);
12561 dev->base_addr = dev->mem_start;
12562 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 12563
12564 dev->irq = pdev->irq;
12565
275f165f 12566 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 12567 if (!bp->regview) {
cdaa7cb8
VZ		 12568 dev_err(&bp->pdev->dev,
12569 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 12570 rc = -ENOMEM;
12571 goto err_out_release;
12572 }
12573
c22610d0
AE		 12574 /* In E1/E1H use pci device function given by kernel.
12575 * In E2/E3 read physical function from ME register since these chips
12576 * support Physical Device Assignment where kernel BDF maybe arbitrary
12577 * (depending on hypervisor).
12578 */
2de67439 12579 if (chip_is_e1x) {
c22610d0 12580 bp->pf_num = PCI_FUNC(pdev->devfn);
2de67439
YM		 12581 } else {
12582 /* chip is E2/3*/
c22610d0
AE		 12583 pci_read_config_dword(bp->pdev,
12584 PCICFG_ME_REGISTER, &pci_cfg_dword);
12585 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
2de67439 12586 ME_REG_ABS_PF_NUM_SHIFT);
c22610d0 12587 }
51c1a580 12588 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
c22610d0 12589
34f80b04
EG		 12590 /* clean indirect addresses */
12591 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12592 PCICFG_VENDOR_ID_OFFSET);
33d8e6a5
YM		 12593
12594 /* AER (Advanced Error reporting) configuration */
12595 rc = pci_enable_pcie_error_reporting(pdev);
12596 if (!rc)
12597 bp->flags |= AER_ENABLED;
12598 else
12599 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12600
a5c53dbc
DK		 12601 /*
12602 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 12603 * is not used by the driver.
12604 */
1ab4434c
AE		 12605 if (IS_PF(bp)) {
12606 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12607 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12608 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12609 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12610
12611 if (chip_is_e1x) {
12612 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12613 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12614 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12615 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12616 }
a5c53dbc 12617
1ab4434c
AE		 12618 /* Enable internal target-read (in case we are probed after PF
12619 * FLR). Must be done prior to any BAR read access. Only for
12620 * 57712 and up
12621 */
12622 if (!chip_is_e1x)
12623 REG_WR(bp,
12624 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
a5c53dbc 12625 }
a2fbb9ea 12626
34f80b04 12627 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 12628
c64213cd 12629 dev->netdev_ops = &bnx2x_netdev_ops;
005a07ba 12630 bnx2x_set_ethtool_ops(bp, dev);
5316bc0b 12631
01789349
JP		 12632 dev->priv_flags |= IFF_UNICAST_FLT;
12633
66371c44 12634 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
621b4d66
DK		 12635 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12636 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
f646968f 12637 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
a848ade4 12638 if (!CHIP_IS_E1x(bp)) {
117401ee 12639 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
2e3bd6a4 12640 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
a848ade4
DK		 12641 dev->hw_enc_features =
12642 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12643 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
117401ee 12644 NETIF_F_GSO_IPIP |
2e3bd6a4 12645 NETIF_F_GSO_SIT |
65bc0cfe 12646 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
a848ade4 12647 }
66371c44
MM		 12648
12649 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12650 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12651
f646968f 12652 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
edd31476 12653 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 12654
538dd2e3
MB		 12655 /* Add Loopback capability to the device */
12656 dev->hw_features |= NETIF_F_LOOPBACK;
12657
98507672 12658#ifdef BCM_DCBNL
785b9b1a
SR		 12659 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12660#endif
12661
01cd4528
EG		 12662 /* get_port_hwinfo() will set prtad and mmds properly */
12663 bp->mdio.prtad = MDIO_PRTAD_NONE;
12664 bp->mdio.mmds = 0;
12665 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12666 bp->mdio.dev = dev;
12667 bp->mdio.mdio_read = bnx2x_mdio_read;
12668 bp->mdio.mdio_write = bnx2x_mdio_write;
12669
a2fbb9ea
ET		 12670 return 0;
12671
a2fbb9ea 12672err_out_release:
34f80b04
EG		 12673 if (atomic_read(&pdev->enable_cnt) == 1)
12674 pci_release_regions(pdev);
a2fbb9ea
ET		 12675
12676err_out_disable:
12677 pci_disable_device(pdev);
a2fbb9ea
ET		 12678
12679err_out:
12680 return rc;
12681}
12682
6891dd25 12683static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 12684{
37f9ce62 12685 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 12686 struct bnx2x_fw_file_hdr *fw_hdr;
12687 struct bnx2x_fw_file_section *sections;
94a78b79 12688 u32 offset, len, num_ops;
86564c3f 12689 __be16 *ops_offsets;
94a78b79 12690 int i;
37f9ce62 12691 const u8 *fw_ver;
94a78b79 12692
51c1a580
MS		 12693 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12694 BNX2X_ERR("Wrong FW size\n");
94a78b79 12695 return -EINVAL;
51c1a580 12696 }
94a78b79
VZ		 12697
12698 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12699 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12700
12701 /* Make sure none of the offsets and sizes make us read beyond
12702 * the end of the firmware data */
12703 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12704 offset = be32_to_cpu(sections[i].offset);
12705 len = be32_to_cpu(sections[i].len);
12706 if (offset + len > firmware->size) {
51c1a580 12707 BNX2X_ERR("Section %d length is out of bounds\n", i);
94a78b79
VZ		 12708 return -EINVAL;
12709 }
12710 }
12711
12712 /* Likewise for the init_ops offsets */
12713 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
86564c3f 12714 ops_offsets = (__force __be16 *)(firmware->data + offset);
94a78b79
VZ		 12715 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12716
12717 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12718 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
51c1a580 12719 BNX2X_ERR("Section offset %d is out of bounds\n", i);
94a78b79
VZ		 12720 return -EINVAL;
12721 }
12722 }
12723
12724 /* Check FW version */
12725 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12726 fw_ver = firmware->data + offset;
12727 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12728 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12729 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12730 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
51c1a580
MS		 12731 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12732 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12733 BCM_5710_FW_MAJOR_VERSION,
94a78b79
VZ		 12734 BCM_5710_FW_MINOR_VERSION,
12735 BCM_5710_FW_REVISION_VERSION,
12736 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 12737 return -EINVAL;
94a78b79
VZ		 12738 }
12739
12740 return 0;
12741}
12742
1191cb83 12743static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 12744{
ab6ad5a4
EG		 12745 const __be32 *source = (const __be32 *)_source;
12746 u32 *target = (u32 *)_target;
94a78b79 12747 u32 i;
94a78b79
VZ		 12748
12749 for (i = 0; i < n/4; i++)
12750 target[i] = be32_to_cpu(source[i]);
12751}
12752
12753/*
12754 Ops array is stored in the following format:
12755 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12756 */
1191cb83 12757static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 12758{
ab6ad5a4
EG		 12759 const __be32 *source = (const __be32 *)_source;
12760 struct raw_op *target = (struct raw_op *)_target;
94a78b79 12761 u32 i, j, tmp;
94a78b79 12762
ab6ad5a4 12763 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 12764 tmp = be32_to_cpu(source[j]);
12765 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 12766 target[i].offset = tmp & 0xffffff;
12767 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 12768 }
12769}
ab6ad5a4 12770
1aa8b471 12771/* IRO array is stored in the following format:
523224a3
DK		 12772 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12773 */
1191cb83 12774static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
523224a3
DK		 12775{
12776 const __be32 *source = (const __be32 *)_source;
12777 struct iro *target = (struct iro *)_target;
12778 u32 i, j, tmp;
12779
12780 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12781 target[i].base = be32_to_cpu(source[j]);
12782 j++;
12783 tmp = be32_to_cpu(source[j]);
12784 target[i].m1 = (tmp >> 16) & 0xffff;
12785 target[i].m2 = tmp & 0xffff;
12786 j++;
12787 tmp = be32_to_cpu(source[j]);
12788 target[i].m3 = (tmp >> 16) & 0xffff;
12789 target[i].size = tmp & 0xffff;
12790 j++;
12791 }
12792}
12793
1191cb83 12794static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 12795{
ab6ad5a4
EG		 12796 const __be16 *source = (const __be16 *)_source;
12797 u16 *target = (u16 *)_target;
94a78b79 12798 u32 i;
94a78b79
VZ		 12799
12800 for (i = 0; i < n/2; i++)
12801 target[i] = be16_to_cpu(source[i]);
12802}
12803
7995c64e
JP		 12804#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12805do { \
12806 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12807 bp->arr = kmalloc(len, GFP_KERNEL); \
e404decb 12808 if (!bp->arr) \
7995c64e 12809 goto lbl; \
7995c64e
JP		 12810 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12811 (u8 *)bp->arr, len); \
12812} while (0)
94a78b79 12813
3b603066 12814static int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 12815{
c0ea452e 12816 const char *fw_file_name;
94a78b79 12817 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 12818 int rc;
94a78b79 12819
c0ea452e
MS		 12820 if (bp->firmware)
12821 return 0;
94a78b79 12822
c0ea452e
MS		 12823 if (CHIP_IS_E1(bp))
12824 fw_file_name = FW_FILE_NAME_E1;
12825 else if (CHIP_IS_E1H(bp))
12826 fw_file_name = FW_FILE_NAME_E1H;
12827 else if (!CHIP_IS_E1x(bp))
12828 fw_file_name = FW_FILE_NAME_E2;
12829 else {
12830 BNX2X_ERR("Unsupported chip revision\n");
12831 return -EINVAL;
12832 }
12833 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 12834
c0ea452e
MS		 12835 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12836 if (rc) {
12837 BNX2X_ERR("Can't load firmware file %s\n",
12838 fw_file_name);
12839 goto request_firmware_exit;
12840 }
eb2afd4a 12841
c0ea452e
MS		 12842 rc = bnx2x_check_firmware(bp);
12843 if (rc) {
12844 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12845 goto request_firmware_exit;
94a78b79
VZ		 12846 }
12847
12848 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12849
12850 /* Initialize the pointers to the init arrays */
12851 /* Blob */
12852 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12853
12854 /* Opcodes */
12855 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12856
12857 /* Offsets */
ab6ad5a4
EG		 12858 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12859 be16_to_cpu_n);
94a78b79
VZ		 12860
12861 /* STORMs firmware */
573f2035
EG		 12862 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12863 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12864 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12865 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12866 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12867 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12868 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12869 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12870 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12871 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12872 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12873 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12874 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12875 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12876 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12877 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 12878 /* IRO */
12879 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 12880
12881 return 0;
ab6ad5a4 12882
523224a3
DK		 12883iro_alloc_err:
12884 kfree(bp->init_ops_offsets);
94a78b79
VZ		 12885init_offsets_alloc_err:
12886 kfree(bp->init_ops);
12887init_ops_alloc_err:
12888 kfree(bp->init_data);
12889request_firmware_exit:
12890 release_firmware(bp->firmware);
127d0a19 12891 bp->firmware = NULL;
94a78b79
VZ		 12892
12893 return rc;
12894}
12895
619c5cb6
VZ		 12896static void bnx2x_release_firmware(struct bnx2x *bp)
12897{
12898 kfree(bp->init_ops_offsets);
12899 kfree(bp->init_ops);
12900 kfree(bp->init_data);
12901 release_firmware(bp->firmware);
eb2afd4a 12902 bp->firmware = NULL;
619c5cb6
VZ		 12903}
12904
619c5cb6
VZ		 12905static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12906 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12907 .init_hw_cmn = bnx2x_init_hw_common,
12908 .init_hw_port = bnx2x_init_hw_port,
12909 .init_hw_func = bnx2x_init_hw_func,
12910
12911 .reset_hw_cmn = bnx2x_reset_common,
12912 .reset_hw_port = bnx2x_reset_port,
12913 .reset_hw_func = bnx2x_reset_func,
12914
12915 .gunzip_init = bnx2x_gunzip_init,
12916 .gunzip_end = bnx2x_gunzip_end,
12917
12918 .init_fw = bnx2x_init_firmware,
12919 .release_fw = bnx2x_release_firmware,
12920};
12921
12922void bnx2x__init_func_obj(struct bnx2x *bp)
12923{
12924 /* Prepare DMAE related driver resources */
12925 bnx2x_setup_dmae(bp);
12926
12927 bnx2x_init_func_obj(bp, &bp->func_obj,
12928 bnx2x_sp(bp, func_rdata),
12929 bnx2x_sp_mapping(bp, func_rdata),
a3348722
BW		 12930 bnx2x_sp(bp, func_afex_rdata),
12931 bnx2x_sp_mapping(bp, func_afex_rdata),
619c5cb6
VZ		 12932 &bnx2x_func_sp_drv);
12933}
12934
12935/* must be called after sriov-enable */
1191cb83 12936static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 12937{
37ae41a9 12938 int cid_count = BNX2X_L2_MAX_CID(bp);
94a78b79 12939
290ca2bb
AE		 12940 if (IS_SRIOV(bp))
12941 cid_count += BNX2X_VF_CIDS;
12942
55c11941
MS		 12943 if (CNIC_SUPPORT(bp))
12944 cid_count += CNIC_CID_MAX;
290ca2bb 12945
523224a3
DK		 12946 return roundup(cid_count, QM_CID_ROUND);
12947}
f85582f8 12948
619c5cb6 12949/**
6383c0b3 12950 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 12951 *
12952 * @dev: pci device
12953 *
12954 */
60cad4e6 12955static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
619c5cb6 12956{
ae2104be 12957 int index;
1ab4434c 12958 u16 control = 0;
619c5cb6 12959
6383c0b3
AE		 12960 /*
12961 * If MSI-X is not supported - return number of SBs needed to support
12962 * one fast path queue: one FP queue + SB for CNIC
12963 */
ae2104be 12964 if (!pdev->msix_cap) {
1ab4434c 12965 dev_info(&pdev->dev, "no msix capability found\n");
55c11941 12966 return 1 + cnic_cnt;
1ab4434c
AE		 12967 }
12968 dev_info(&pdev->dev, "msix capability found\n");
619c5cb6 12969
6383c0b3
AE		 12970 /*
12971 * The value in the PCI configuration space is the index of the last
12972 * entry, namely one less than the actual size of the table, which is
12973 * exactly what we want to return from this function: number of all SBs
12974 * without the default SB.
1ab4434c 12975 * For VFs there is no default SB, then we return (index+1).
6383c0b3 12976 */
73413ffa 12977 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
619c5cb6 12978
1ab4434c 12979 index = control & PCI_MSIX_FLAGS_QSIZE;
4bd9b0ff 12980
60cad4e6 12981 return index;
1ab4434c 12982}
523224a3 12983
1ab4434c
AE		 12984static int set_max_cos_est(int chip_id)
12985{
12986 switch (chip_id) {
f2e0899f
DK		 12987 case BCM57710:
12988 case BCM57711:
12989 case BCM57711E:
1ab4434c 12990 return BNX2X_MULTI_TX_COS_E1X;
f2e0899f 12991 case BCM57712:
619c5cb6 12992 case BCM57712_MF:
1ab4434c 12993 return BNX2X_MULTI_TX_COS_E2_E3A0;
619c5cb6
VZ		 12994 case BCM57800:
12995 case BCM57800_MF:
12996 case BCM57810:
12997 case BCM57810_MF:
c3def943
YM		 12998 case BCM57840_4_10:
12999 case BCM57840_2_20:
1ab4434c 13000 case BCM57840_O:
c3def943 13001 case BCM57840_MFO:
619c5cb6 13002 case BCM57840_MF:
7e8e02df
BW		 13003 case BCM57811:
13004 case BCM57811_MF:
1ab4434c 13005 return BNX2X_MULTI_TX_COS_E3B0;
b1239723
YM		 13006 case BCM57712_VF:
13007 case BCM57800_VF:
13008 case BCM57810_VF:
13009 case BCM57840_VF:
13010 case BCM57811_VF:
1ab4434c 13011 return 1;
f2e0899f 13012 default:
1ab4434c 13013 pr_err("Unknown board_type (%d), aborting\n", chip_id);
870634b0 13014 return -ENODEV;
f2e0899f 13015 }
1ab4434c 13016}
f2e0899f 13017
1ab4434c
AE		 13018static int set_is_vf(int chip_id)
13019{
13020 switch (chip_id) {
13021 case BCM57712_VF:
13022 case BCM57800_VF:
13023 case BCM57810_VF:
13024 case BCM57840_VF:
13025 case BCM57811_VF:
13026 return true;
13027 default:
13028 return false;
13029 }
13030}
6383c0b3 13031
eeed018c
MK		 13032/* nig_tsgen registers relative address */
13033#define tsgen_ctrl 0x0
13034#define tsgen_freecount 0x10
13035#define tsgen_synctime_t0 0x20
13036#define tsgen_offset_t0 0x28
13037#define tsgen_drift_t0 0x30
13038#define tsgen_synctime_t1 0x58
13039#define tsgen_offset_t1 0x60
13040#define tsgen_drift_t1 0x68
13041
13042/* FW workaround for setting drift */
13043static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13044 int best_val, int best_period)
13045{
13046 struct bnx2x_func_state_params func_params = {NULL};
13047 struct bnx2x_func_set_timesync_params *set_timesync_params =
13048 &func_params.params.set_timesync;
13049
13050 /* Prepare parameters for function state transitions */
13051 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13052 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13053
13054 func_params.f_obj = &bp->func_obj;
13055 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13056
13057 /* Function parameters */
13058 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13059 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13060 set_timesync_params->add_sub_drift_adjust_value =
13061 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13062 set_timesync_params->drift_adjust_value = best_val;
13063 set_timesync_params->drift_adjust_period = best_period;
13064
13065 return bnx2x_func_state_change(bp, &func_params);
13066}
13067
13068static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13069{
13070 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13071 int rc;
13072 int drift_dir = 1;
13073 int val, period, period1, period2, dif, dif1, dif2;
13074 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13075
13076 DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13077
13078 if (!netif_running(bp->dev)) {
13079 DP(BNX2X_MSG_PTP,
13080 "PTP adjfreq called while the interface is down\n");
13081 return -EFAULT;
13082 }
13083
13084 if (ppb < 0) {
13085 ppb = -ppb;
13086 drift_dir = 0;
13087 }
13088
13089 if (ppb == 0) {
13090 best_val = 1;
13091 best_period = 0x1FFFFFF;
13092 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13093 best_val = 31;
13094 best_period = 1;
13095 } else {
13096 /* Changed not to allow val = 8, 16, 24 as these values
13097 * are not supported in workaround.
13098 */
13099 for (val = 0; val <= 31; val++) {
13100 if ((val & 0x7) == 0)
13101 continue;
13102 period1 = val * 1000000 / ppb;
13103 period2 = period1 + 1;
13104 if (period1 != 0)
13105 dif1 = ppb - (val * 1000000 / period1);
13106 else
13107 dif1 = BNX2X_MAX_PHC_DRIFT;
13108 if (dif1 < 0)
13109 dif1 = -dif1;
13110 dif2 = ppb - (val * 1000000 / period2);
13111 if (dif2 < 0)
13112 dif2 = -dif2;
13113 dif = (dif1 < dif2) ? dif1 : dif2;
13114 period = (dif1 < dif2) ? period1 : period2;
13115 if (dif < best_dif) {
13116 best_dif = dif;
13117 best_val = val;
13118 best_period = period;
13119 }
13120 }
13121 }
13122
13123 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13124 best_period);
13125 if (rc) {
13126 BNX2X_ERR("Failed to set drift\n");
13127 return -EFAULT;
13128 }
13129
13130 DP(BNX2X_MSG_PTP, "Configrued val = %d, period = %d\n", best_val,
13131 best_period);
13132
13133 return 0;
13134}
13135
13136static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13137{
13138 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13139 u64 now;
13140
13141 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13142
13143 now = timecounter_read(&bp->timecounter);
13144 now += delta;
13145 /* Re-init the timecounter */
13146 timecounter_init(&bp->timecounter, &bp->cyclecounter, now);
13147
13148 return 0;
13149}
13150
13151static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
13152{
13153 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13154 u64 ns;
13155 u32 remainder;
13156
13157 ns = timecounter_read(&bp->timecounter);
13158
13159 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13160
13161 ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
13162 ts->tv_nsec = remainder;
13163
13164 return 0;
13165}
13166
13167static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13168 const struct timespec *ts)
13169{
13170 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13171 u64 ns;
13172
13173 ns = ts->tv_sec * 1000000000ULL;
13174 ns += ts->tv_nsec;
13175
13176 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13177
13178 /* Re-init the timecounter */
13179 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13180
13181 return 0;
13182}
13183
13184/* Enable (or disable) ancillary features of the phc subsystem */
13185static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13186 struct ptp_clock_request *rq, int on)
13187{
13188 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13189
13190 BNX2X_ERR("PHC ancillary features are not supported\n");
13191 return -ENOTSUPP;
13192}
13193
13194void bnx2x_register_phc(struct bnx2x *bp)
13195{
13196 /* Fill the ptp_clock_info struct and register PTP clock*/
13197 bp->ptp_clock_info.owner = THIS_MODULE;
13198 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13199 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13200 bp->ptp_clock_info.n_alarm = 0;
13201 bp->ptp_clock_info.n_ext_ts = 0;
13202 bp->ptp_clock_info.n_per_out = 0;
13203 bp->ptp_clock_info.pps = 0;
13204 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13205 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13206 bp->ptp_clock_info.gettime = bnx2x_ptp_gettime;
13207 bp->ptp_clock_info.settime = bnx2x_ptp_settime;
13208 bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13209
13210 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13211 if (IS_ERR(bp->ptp_clock)) {
13212 bp->ptp_clock = NULL;
13213 BNX2X_ERR("PTP clock registeration failed\n");
13214 }
13215}
13216
1ab4434c
AE		 13217static int bnx2x_init_one(struct pci_dev *pdev,
13218 const struct pci_device_id *ent)
13219{
13220 struct net_device *dev = NULL;
13221 struct bnx2x *bp;
b91e1a1a
YM		 13222 enum pcie_link_width pcie_width;
13223 enum pci_bus_speed pcie_speed;
1ab4434c
AE		 13224 int rc, max_non_def_sbs;
13225 int rx_count, tx_count, rss_count, doorbell_size;
13226 int max_cos_est;
13227 bool is_vf;
13228 int cnic_cnt;
13229
13230 /* An estimated maximum supported CoS number according to the chip
13231 * version.
13232 * We will try to roughly estimate the maximum number of CoSes this chip
13233 * may support in order to minimize the memory allocated for Tx
13234 * netdev_queue's. This number will be accurately calculated during the
13235 * initialization of bp->max_cos based on the chip versions AND chip
13236 * revision in the bnx2x_init_bp().
13237 */
13238 max_cos_est = set_max_cos_est(ent->driver_data);
13239 if (max_cos_est < 0)
13240 return max_cos_est;
13241 is_vf = set_is_vf(ent->driver_data);
13242 cnic_cnt = is_vf ? 0 : 1;
13243
60cad4e6
AE		 13244 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13245
13246 /* add another SB for VF as it has no default SB */
13247 max_non_def_sbs += is_vf ? 1 : 0;
6383c0b3
AE		 13248
13249 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
60cad4e6 13250 rss_count = max_non_def_sbs - cnic_cnt;
1ab4434c
AE		 13251
13252 if (rss_count < 1)
13253 return -EINVAL;
6383c0b3
AE		 13254
13255 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
55c11941 13256 rx_count = rss_count + cnic_cnt;
6383c0b3 13257
1ab4434c 13258 /* Maximum number of netdev Tx queues:
37ae41a9 13259 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
6383c0b3 13260 */
55c11941 13261 tx_count = rss_count * max_cos_est + cnic_cnt;
f85582f8 13262
a2fbb9ea 13263 /* dev zeroed in init_etherdev */
6383c0b3 13264 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
41de8d4c 13265 if (!dev)
a2fbb9ea
ET		 13266 return -ENOMEM;
13267
a2fbb9ea 13268 bp = netdev_priv(dev);
a2fbb9ea 13269
1ab4434c
AE		 13270 bp->flags = 0;
13271 if (is_vf)
13272 bp->flags |= IS_VF_FLAG;
13273
6383c0b3 13274 bp->igu_sb_cnt = max_non_def_sbs;
1ab4434c 13275 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
6383c0b3 13276 bp->msg_enable = debug;
55c11941 13277 bp->cnic_support = cnic_cnt;
4bd9b0ff 13278 bp->cnic_probe = bnx2x_cnic_probe;
55c11941 13279
6383c0b3 13280 pci_set_drvdata(pdev, dev);
523224a3 13281
1ab4434c 13282 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
a2fbb9ea
ET		 13283 if (rc < 0) {
13284 free_netdev(dev);
13285 return rc;
13286 }
13287
1ab4434c
AE		 13288 BNX2X_DEV_INFO("This is a %s function\n",
13289 IS_PF(bp) ? "physical" : "virtual");
55c11941 13290 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
1ab4434c 13291 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
60aa0509 13292 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
2de67439 13293 tx_count, rx_count);
60aa0509 13294
34f80b04 13295 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 13296 if (rc)
13297 goto init_one_exit;
13298
1ab4434c
AE		 13299 /* Map doorbells here as we need the real value of bp->max_cos which
13300 * is initialized in bnx2x_init_bp() to determine the number of
13301 * l2 connections.
6383c0b3 13302 */
1ab4434c 13303 if (IS_VF(bp)) {
1d6f3cd8 13304 bp->doorbells = bnx2x_vf_doorbells(bp);
6411280a
AE		 13305 rc = bnx2x_vf_pci_alloc(bp);
13306 if (rc)
13307 goto init_one_exit;
1ab4434c
AE		 13308 } else {
13309 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13310 if (doorbell_size > pci_resource_len(pdev, 2)) {
13311 dev_err(&bp->pdev->dev,
13312 "Cannot map doorbells, bar size too small, aborting\n");
13313 rc = -ENOMEM;
13314 goto init_one_exit;
13315 }
13316 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13317 doorbell_size);
37ae41a9 13318 }
6383c0b3
AE		 13319 if (!bp->doorbells) {
13320 dev_err(&bp->pdev->dev,
13321 "Cannot map doorbell space, aborting\n");
13322 rc = -ENOMEM;
13323 goto init_one_exit;
13324 }
13325
be1f1ffa
AE		 13326 if (IS_VF(bp)) {
13327 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13328 if (rc)
13329 goto init_one_exit;
13330 }
13331
3c76feff
AE		 13332 /* Enable SRIOV if capability found in configuration space */
13333 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
290ca2bb
AE		 13334 if (rc)
13335 goto init_one_exit;
13336
523224a3 13337 /* calc qm_cid_count */
6383c0b3 13338 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
1ab4434c 13339 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
523224a3 13340
55c11941 13341 /* disable FCOE L2 queue for E1x*/
62ac0dc9 13342 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 13343 bp->flags |= NO_FCOE_FLAG;
13344
0e8d2ec5
MS		 13345 /* Set bp->num_queues for MSI-X mode*/
13346 bnx2x_set_num_queues(bp);
13347
25985edc 13348 /* Configure interrupt mode: try to enable MSI-X/MSI if
0e8d2ec5 13349 * needed.
d6214d7a 13350 */
1ab4434c
AE		 13351 rc = bnx2x_set_int_mode(bp);
13352 if (rc) {
13353 dev_err(&pdev->dev, "Cannot set interrupts\n");
13354 goto init_one_exit;
13355 }
04c46736 13356 BNX2X_DEV_INFO("set interrupts successfully\n");
d6214d7a 13357
1ab4434c 13358 /* register the net device */
b340007f
VZ		 13359 rc = register_netdev(dev);
13360 if (rc) {
13361 dev_err(&pdev->dev, "Cannot register net device\n");
13362 goto init_one_exit;
13363 }
1ab4434c 13364 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
b340007f 13365
ec6ba945
VZ		 13366 if (!NO_FCOE(bp)) {
13367 /* Add storage MAC address */
13368 rtnl_lock();
13369 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13370 rtnl_unlock();
13371 }
b91e1a1a
YM		 13372 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13373 pcie_speed == PCI_SPEED_UNKNOWN ||
13374 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13375 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13376 else
13377 BNX2X_DEV_INFO(
13378 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
ca1ee4b2
DK		 13379 board_info[ent->driver_data].name,
13380 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13381 pcie_width,
b91e1a1a
YM		 13382 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13383 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13384 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
ca1ee4b2
DK		 13385 "Unknown",
13386 dev->base_addr, bp->pdev->irq, dev->dev_addr);
c016201c 13387
eeed018c
MK		 13388 bnx2x_register_phc(bp);
13389
a2fbb9ea 13390 return 0;
34f80b04
EG		 13391
13392init_one_exit:
33d8e6a5
YM		 13393 bnx2x_disable_pcie_error_reporting(bp);
13394
34f80b04
EG		 13395 if (bp->regview)
13396 iounmap(bp->regview);
13397
1ab4434c 13398 if (IS_PF(bp) && bp->doorbells)
34f80b04
EG		 13399 iounmap(bp->doorbells);
13400
13401 free_netdev(dev);
13402
13403 if (atomic_read(&pdev->enable_cnt) == 1)
13404 pci_release_regions(pdev);
13405
13406 pci_disable_device(pdev);
34f80b04
EG		 13407
13408 return rc;
a2fbb9ea
ET		 13409}
13410
b030ed2f
YM		 13411static void __bnx2x_remove(struct pci_dev *pdev,
13412 struct net_device *dev,
13413 struct bnx2x *bp,
13414 bool remove_netdev)
a2fbb9ea 13415{
eeed018c
MK		 13416 if (bp->ptp_clock) {
13417 ptp_clock_unregister(bp->ptp_clock);
13418 bp->ptp_clock = NULL;
13419 }
13420
ec6ba945
VZ		 13421 /* Delete storage MAC address */
13422 if (!NO_FCOE(bp)) {
13423 rtnl_lock();
13424 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13425 rtnl_unlock();
13426 }
ec6ba945 13427
98507672
SR		 13428#ifdef BCM_DCBNL
13429 /* Delete app tlvs from dcbnl */
13430 bnx2x_dcbnl_update_applist(bp, true);
13431#endif
13432
a6d3a5ba
BW		 13433 if (IS_PF(bp) &&
13434 !BP_NOMCP(bp) &&
13435 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13436 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13437
b030ed2f
YM		 13438 /* Close the interface - either directly or implicitly */
13439 if (remove_netdev) {
13440 unregister_netdev(dev);
13441 } else {
13442 rtnl_lock();
6ef5a92c 13443 dev_close(dev);
b030ed2f
YM		 13444 rtnl_unlock();
13445 }
a2fbb9ea 13446
78c3bcc5
AE		 13447 bnx2x_iov_remove_one(bp);
13448
084d6cbb 13449 /* Power on: we can't let PCI layer write to us while we are in D3 */
04860eb7 13450 if (IS_PF(bp)) {
1ab4434c 13451 bnx2x_set_power_state(bp, PCI_D0);
084d6cbb 13452
04860eb7
MC		 13453 /* Set endianity registers to reset values in case next driver
13454 * boots in different endianty environment.
13455 */
13456 bnx2x_reset_endianity(bp);
13457 }
13458
d6214d7a
DK		 13459 /* Disable MSI/MSI-X */
13460 bnx2x_disable_msi(bp);
f85582f8 13461
084d6cbb 13462 /* Power off */
1ab4434c
AE		 13463 if (IS_PF(bp))
13464 bnx2x_set_power_state(bp, PCI_D3hot);
084d6cbb 13465
72fd0718 13466 /* Make sure RESET task is not scheduled before continuing */
7be08a72 13467 cancel_delayed_work_sync(&bp->sp_rtnl_task);
290ca2bb 13468
4513f925
AE		 13469 /* send message via vfpf channel to release the resources of this vf */
13470 if (IS_VF(bp))
13471 bnx2x_vfpf_release(bp);
72fd0718 13472
b030ed2f
YM		 13473 /* Assumes no further PCIe PM changes will occur */
13474 if (system_state == SYSTEM_POWER_OFF) {
13475 pci_wake_from_d3(pdev, bp->wol);
13476 pci_set_power_state(pdev, PCI_D3hot);
13477 }
13478
33d8e6a5 13479 bnx2x_disable_pcie_error_reporting(bp);
d9aee591
YM		 13480 if (remove_netdev) {
13481 if (bp->regview)
13482 iounmap(bp->regview);
33d8e6a5 13483
d9aee591
YM		 13484 /* For vfs, doorbells are part of the regview and were unmapped
13485 * along with it. FW is only loaded by PF.
13486 */
13487 if (IS_PF(bp)) {
13488 if (bp->doorbells)
13489 iounmap(bp->doorbells);
eb2afd4a 13490
d9aee591 13491 bnx2x_release_firmware(bp);
e2a367f8
YM		 13492 } else {
13493 bnx2x_vf_pci_dealloc(bp);
d9aee591
YM		 13494 }
13495 bnx2x_free_mem_bp(bp);
523224a3 13496
b030ed2f 13497 free_netdev(dev);
34f80b04 13498
d9aee591
YM		 13499 if (atomic_read(&pdev->enable_cnt) == 1)
13500 pci_release_regions(pdev);
34f80b04 13501
5f6db130
YM		 13502 pci_disable_device(pdev);
13503 }
a2fbb9ea
ET		 13504}
13505
b030ed2f
YM		 13506static void bnx2x_remove_one(struct pci_dev *pdev)
13507{
13508 struct net_device *dev = pci_get_drvdata(pdev);
13509 struct bnx2x *bp;
13510
13511 if (!dev) {
13512 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13513 return;
13514 }
13515 bp = netdev_priv(dev);
13516
13517 __bnx2x_remove(pdev, dev, bp, true);
13518}
13519
f8ef6e44
YG		 13520static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13521{
7fa6f340 13522 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
f8ef6e44
YG		 13523
13524 bp->rx_mode = BNX2X_RX_MODE_NONE;
13525
55c11941
MS		 13526 if (CNIC_LOADED(bp))
13527 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13528
619c5cb6
VZ		 13529 /* Stop Tx */
13530 bnx2x_tx_disable(bp);
26614ba5
MS		 13531 /* Delete all NAPI objects */
13532 bnx2x_del_all_napi(bp);
55c11941
MS		 13533 if (CNIC_LOADED(bp))
13534 bnx2x_del_all_napi_cnic(bp);
7fa6f340 13535 netdev_reset_tc(bp->dev);
f8ef6e44
YG		 13536
13537 del_timer_sync(&bp->timer);
0c0e6341 13538 cancel_delayed_work_sync(&bp->sp_task);
13539 cancel_delayed_work_sync(&bp->period_task);
619c5cb6 13540
7fa6f340
YM		 13541 spin_lock_bh(&bp->stats_lock);
13542 bp->stats_state = STATS_STATE_DISABLED;
13543 spin_unlock_bh(&bp->stats_lock);
f8ef6e44 13544
7fa6f340 13545 bnx2x_save_statistics(bp);
f8ef6e44 13546
619c5cb6
VZ		 13547 netif_carrier_off(bp->dev);
13548
f8ef6e44
YG		 13549 return 0;
13550}
13551
493adb1f
WX		 13552/**
13553 * bnx2x_io_error_detected - called when PCI error is detected
13554 * @pdev: Pointer to PCI device
13555 * @state: The current pci connection state
13556 *
13557 * This function is called after a PCI bus error affecting
13558 * this device has been detected.
13559 */
13560static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13561 pci_channel_state_t state)
13562{
13563 struct net_device *dev = pci_get_drvdata(pdev);
13564 struct bnx2x *bp = netdev_priv(dev);
13565
13566 rtnl_lock();
13567
7fa6f340
YM		 13568 BNX2X_ERR("IO error detected\n");
13569
493adb1f
WX		 13570 netif_device_detach(dev);
13571
07ce50e4
DN		 13572 if (state == pci_channel_io_perm_failure) {
13573 rtnl_unlock();
13574 return PCI_ERS_RESULT_DISCONNECT;
13575 }
13576
493adb1f 13577 if (netif_running(dev))
f8ef6e44 13578 bnx2x_eeh_nic_unload(bp);
493adb1f 13579
7fa6f340
YM		 13580 bnx2x_prev_path_mark_eeh(bp);
13581
493adb1f
WX		 13582 pci_disable_device(pdev);
13583
13584 rtnl_unlock();
13585
13586 /* Request a slot reset */
13587 return PCI_ERS_RESULT_NEED_RESET;
13588}
13589
13590/**
13591 * bnx2x_io_slot_reset - called after the PCI bus has been reset
13592 * @pdev: Pointer to PCI device
13593 *
13594 * Restart the card from scratch, as if from a cold-boot.
13595 */
13596static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13597{
13598 struct net_device *dev = pci_get_drvdata(pdev);
13599 struct bnx2x *bp = netdev_priv(dev);
7fa6f340 13600 int i;
493adb1f
WX		 13601
13602 rtnl_lock();
7fa6f340 13603 BNX2X_ERR("IO slot reset initializing...\n");
493adb1f
WX		 13604 if (pci_enable_device(pdev)) {
13605 dev_err(&pdev->dev,
13606 "Cannot re-enable PCI device after reset\n");
13607 rtnl_unlock();
13608 return PCI_ERS_RESULT_DISCONNECT;
13609 }
13610
13611 pci_set_master(pdev);
13612 pci_restore_state(pdev);
70632d0a 13613 pci_save_state(pdev);
493adb1f
WX		 13614
13615 if (netif_running(dev))
13616 bnx2x_set_power_state(bp, PCI_D0);
13617
7fa6f340
YM		 13618 if (netif_running(dev)) {
13619 BNX2X_ERR("IO slot reset --> driver unload\n");
e68072ef
YM		 13620
13621 /* MCP should have been reset; Need to wait for validity */
13622 bnx2x_init_shmem(bp);
13623
7fa6f340
YM		 13624 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13625 u32 v;
13626
13627 v = SHMEM2_RD(bp,
13628 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13629 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13630 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13631 }
13632 bnx2x_drain_tx_queues(bp);
13633 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13634 bnx2x_netif_stop(bp, 1);
13635 bnx2x_free_irq(bp);
13636
13637 /* Report UNLOAD_DONE to MCP */
13638 bnx2x_send_unload_done(bp, true);
13639
13640 bp->sp_state = 0;
13641 bp->port.pmf = 0;
13642
13643 bnx2x_prev_unload(bp);
13644
16a5fd92 13645 /* We should have reseted the engine, so It's fair to
7fa6f340
YM		 13646 * assume the FW will no longer write to the bnx2x driver.
13647 */
13648 bnx2x_squeeze_objects(bp);
13649 bnx2x_free_skbs(bp);
13650 for_each_rx_queue(bp, i)
13651 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13652 bnx2x_free_fp_mem(bp);
13653 bnx2x_free_mem(bp);
13654
13655 bp->state = BNX2X_STATE_CLOSED;
13656 }
13657
493adb1f
WX		 13658 rtnl_unlock();
13659
33d8e6a5
YM		 13660 /* If AER, perform cleanup of the PCIe registers */
13661 if (bp->flags & AER_ENABLED) {
13662 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13663 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13664 else
13665 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13666 }
13667
493adb1f
WX		 13668 return PCI_ERS_RESULT_RECOVERED;
13669}
13670
13671/**
13672 * bnx2x_io_resume - called when traffic can start flowing again
13673 * @pdev: Pointer to PCI device
13674 *
13675 * This callback is called when the error recovery driver tells us that
13676 * its OK to resume normal operation.
13677 */
13678static void bnx2x_io_resume(struct pci_dev *pdev)
13679{
13680 struct net_device *dev = pci_get_drvdata(pdev);
13681 struct bnx2x *bp = netdev_priv(dev);
13682
72fd0718 13683 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580 13684 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
72fd0718
VZ		 13685 return;
13686 }
13687
493adb1f
WX		 13688 rtnl_lock();
13689
7fa6f340
YM		 13690 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13691 DRV_MSG_SEQ_NUMBER_MASK;
13692
493adb1f 13693 if (netif_running(dev))
f8ef6e44 13694 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 13695
13696 netif_device_attach(dev);
13697
13698 rtnl_unlock();
13699}
13700
3646f0e5 13701static const struct pci_error_handlers bnx2x_err_handler = {
493adb1f 13702 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 13703 .slot_reset = bnx2x_io_slot_reset,
13704 .resume = bnx2x_io_resume,
493adb1f
WX		 13705};
13706
b030ed2f
YM		 13707static void bnx2x_shutdown(struct pci_dev *pdev)
13708{
13709 struct net_device *dev = pci_get_drvdata(pdev);
13710 struct bnx2x *bp;
13711
13712 if (!dev)
13713 return;
13714
13715 bp = netdev_priv(dev);
13716 if (!bp)
13717 return;
13718
13719 rtnl_lock();
13720 netif_device_detach(dev);
13721 rtnl_unlock();
13722
13723 /* Don't remove the netdevice, as there are scenarios which will cause
13724 * the kernel to hang, e.g., when trying to remove bnx2i while the
13725 * rootfs is mounted from SAN.
13726 */
13727 __bnx2x_remove(pdev, dev, bp, false);
13728}
13729
a2fbb9ea 13730static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 13731 .name = DRV_MODULE_NAME,
13732 .id_table = bnx2x_pci_tbl,
13733 .probe = bnx2x_init_one,
0329aba1 13734 .remove = bnx2x_remove_one,
493adb1f
WX		 13735 .suspend = bnx2x_suspend,
13736 .resume = bnx2x_resume,
13737 .err_handler = &bnx2x_err_handler,
3c76feff
AE		 13738#ifdef CONFIG_BNX2X_SRIOV
13739 .sriov_configure = bnx2x_sriov_configure,
13740#endif
b030ed2f 13741 .shutdown = bnx2x_shutdown,
a2fbb9ea
ET		 13742};
13743
13744static int __init bnx2x_init(void)
13745{
dd21ca6d
SG		 13746 int ret;
13747
7995c64e 13748 pr_info("%s", version);
938cf541 13749
1cf167f2
EG		 13750 bnx2x_wq = create_singlethread_workqueue("bnx2x");
13751 if (bnx2x_wq == NULL) {
7995c64e 13752 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 13753 return -ENOMEM;
13754 }
370d4a26
YM		 13755 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
13756 if (!bnx2x_iov_wq) {
13757 pr_err("Cannot create iov workqueue\n");
13758 destroy_workqueue(bnx2x_wq);
13759 return -ENOMEM;
13760 }
1cf167f2 13761
dd21ca6d
SG		 13762 ret = pci_register_driver(&bnx2x_pci_driver);
13763 if (ret) {
7995c64e 13764 pr_err("Cannot register driver\n");
dd21ca6d 13765 destroy_workqueue(bnx2x_wq);
370d4a26 13766 destroy_workqueue(bnx2x_iov_wq);
dd21ca6d
SG		 13767 }
13768 return ret;
a2fbb9ea
ET		 13769}
13770
13771static void __exit bnx2x_cleanup(void)
13772{
452427b0 13773 struct list_head *pos, *q;
d76a6111 13774
a2fbb9ea 13775 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 13776
13777 destroy_workqueue(bnx2x_wq);
370d4a26 13778 destroy_workqueue(bnx2x_iov_wq);
452427b0 13779
16a5fd92 13780 /* Free globally allocated resources */
452427b0
YM		 13781 list_for_each_safe(pos, q, &bnx2x_prev_list) {
13782 struct bnx2x_prev_path_list *tmp =
13783 list_entry(pos, struct bnx2x_prev_path_list, list);
13784 list_del(pos);
13785 kfree(tmp);
13786 }
a2fbb9ea
ET		 13787}
13788
3deb8167
YR		 13789void bnx2x_notify_link_changed(struct bnx2x *bp)
13790{
13791 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13792}
13793
a2fbb9ea
ET		 13794module_init(bnx2x_init);
13795module_exit(bnx2x_cleanup);
13796
619c5cb6
VZ		 13797/**
13798 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13799 *
13800 * @bp: driver handle
13801 * @set: set or clear the CAM entry
13802 *
16a5fd92 13803 * This function will wait until the ramrod completion returns.
619c5cb6
VZ		 13804 * Return 0 if success, -ENODEV if ramrod doesn't return.
13805 */
1191cb83 13806static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
619c5cb6
VZ		 13807{
13808 unsigned long ramrod_flags = 0;
13809
13810 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13811 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13812 &bp->iscsi_l2_mac_obj, true,
13813 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13814}
993ac7b5
MC		 13815
13816/* count denotes the number of new completions we have seen */
13817static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13818{
13819 struct eth_spe *spe;
a052997e 13820 int cxt_index, cxt_offset;
993ac7b5
MC		 13821
13822#ifdef BNX2X_STOP_ON_ERROR
13823 if (unlikely(bp->panic))
13824 return;
13825#endif
13826
13827 spin_lock_bh(&bp->spq_lock);
c2bff63f 13828 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 13829 bp->cnic_spq_pending -= count;
13830
c2bff63f
DK		 13831 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13832 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13833 & SPE_HDR_CONN_TYPE) >>
13834 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 13835 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13836 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 13837
13838 /* Set validation for iSCSI L2 client before sending SETUP
13839 * ramrod
13840 */
13841 if (type == ETH_CONNECTION_TYPE) {
a052997e 13842 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
37ae41a9 13843 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
a052997e 13844 ILT_PAGE_CIDS;
37ae41a9 13845 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
a052997e
MS		 13846 (cxt_index * ILT_PAGE_CIDS);
13847 bnx2x_set_ctx_validation(bp,
13848 &bp->context[cxt_index].
13849 vcxt[cxt_offset].eth,
37ae41a9 13850 BNX2X_ISCSI_ETH_CID(bp));
a052997e 13851 }
c2bff63f
DK		 13852 }
13853
619c5cb6
VZ		 13854 /*
13855 * There may be not more than 8 L2, not more than 8 L5 SPEs
13856 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 13857 * COMMON ramrods is not more than the EQ and SPQ can
13858 * accommodate.
c2bff63f 13859 */
6e30dd4e
VZ		 13860 if (type == ETH_CONNECTION_TYPE) {
13861 if (!atomic_read(&bp->cq_spq_left))
13862 break;
13863 else
13864 atomic_dec(&bp->cq_spq_left);
13865 } else if (type == NONE_CONNECTION_TYPE) {
13866 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 13867 break;
13868 else
6e30dd4e 13869 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 13870 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13871 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 13872 if (bp->cnic_spq_pending >=
13873 bp->cnic_eth_dev.max_kwqe_pending)
13874 break;
13875 else
13876 bp->cnic_spq_pending++;
13877 } else {
13878 BNX2X_ERR("Unknown SPE type: %d\n", type);
13879 bnx2x_panic();
993ac7b5 13880 break;
c2bff63f 13881 }
993ac7b5
MC		 13882
13883 spe = bnx2x_sp_get_next(bp);
13884 *spe = *bp->cnic_kwq_cons;
13885
51c1a580 13886 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
993ac7b5
MC		 13887 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13888
13889 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13890 bp->cnic_kwq_cons = bp->cnic_kwq;
13891 else
13892 bp->cnic_kwq_cons++;
13893 }
13894 bnx2x_sp_prod_update(bp);
13895 spin_unlock_bh(&bp->spq_lock);
13896}
13897
13898static int bnx2x_cnic_sp_queue(struct net_device *dev,
13899 struct kwqe_16 *kwqes[], u32 count)
13900{
13901 struct bnx2x *bp = netdev_priv(dev);
13902 int i;
13903
13904#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 13905 if (unlikely(bp->panic)) {
13906 BNX2X_ERR("Can't post to SP queue while panic\n");
993ac7b5 13907 return -EIO;
51c1a580 13908 }
993ac7b5
MC		 13909#endif
13910
95c6c616
AE		 13911 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13912 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
51c1a580 13913 BNX2X_ERR("Handling parity error recovery. Try again later\n");
95c6c616
AE		 13914 return -EAGAIN;
13915 }
13916
993ac7b5
MC		 13917 spin_lock_bh(&bp->spq_lock);
13918
13919 for (i = 0; i < count; i++) {
13920 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13921
13922 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13923 break;
13924
13925 *bp->cnic_kwq_prod = *spe;
13926
13927 bp->cnic_kwq_pending++;
13928
51c1a580 13929 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
993ac7b5 13930 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 13931 spe->data.update_data_addr.hi,
13932 spe->data.update_data_addr.lo,
993ac7b5
MC		 13933 bp->cnic_kwq_pending);
13934
13935 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13936 bp->cnic_kwq_prod = bp->cnic_kwq;
13937 else
13938 bp->cnic_kwq_prod++;
13939 }
13940
13941 spin_unlock_bh(&bp->spq_lock);
13942
13943 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13944 bnx2x_cnic_sp_post(bp, 0);
13945
13946 return i;
13947}
13948
13949static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13950{
13951 struct cnic_ops *c_ops;
13952 int rc = 0;
13953
13954 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 13955 c_ops = rcu_dereference_protected(bp->cnic_ops,
13956 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 13957 if (c_ops)
13958 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13959 mutex_unlock(&bp->cnic_mutex);
13960
13961 return rc;
13962}
13963
13964static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13965{
13966 struct cnic_ops *c_ops;
13967 int rc = 0;
13968
13969 rcu_read_lock();
13970 c_ops = rcu_dereference(bp->cnic_ops);
13971 if (c_ops)
13972 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13973 rcu_read_unlock();
13974
13975 return rc;
13976}
13977
13978/*
13979 * for commands that have no data
13980 */
9f6c9258 13981int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 13982{
13983 struct cnic_ctl_info ctl = {0};
13984
13985 ctl.cmd = cmd;
13986
13987 return bnx2x_cnic_ctl_send(bp, &ctl);
13988}
13989
619c5cb6 13990static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 13991{
619c5cb6 13992 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 13993
13994 /* first we tell CNIC and only then we count this as a completion */
13995 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13996 ctl.data.comp.cid = cid;
619c5cb6 13997 ctl.data.comp.error = err;
993ac7b5
MC		 13998
13999 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 14000 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 14001}
14002
619c5cb6
VZ		 14003/* Called with netif_addr_lock_bh() taken.
14004 * Sets an rx_mode config for an iSCSI ETH client.
14005 * Doesn't block.
14006 * Completion should be checked outside.
14007 */
14008static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14009{
14010 unsigned long accept_flags = 0, ramrod_flags = 0;
14011 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14012 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14013
14014 if (start) {
14015 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14016 * because it's the only way for UIO Queue to accept
14017 * multicasts (in non-promiscuous mode only one Queue per
14018 * function will receive multicast packets (leading in our
14019 * case).
14020 */
14021 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14022 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14023 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14024 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14025
14026 /* Clear STOP_PENDING bit if START is requested */
14027 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14028
14029 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14030 } else
14031 /* Clear START_PENDING bit if STOP is requested */
14032 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14033
14034 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14035 set_bit(sched_state, &bp->sp_state);
14036 else {
14037 __set_bit(RAMROD_RX, &ramrod_flags);
14038 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14039 ramrod_flags);
14040 }
14041}
14042
993ac7b5
MC		 14043static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14044{
14045 struct bnx2x *bp = netdev_priv(dev);
14046 int rc = 0;
14047
14048 switch (ctl->cmd) {
14049 case DRV_CTL_CTXTBL_WR_CMD: {
14050 u32 index = ctl->data.io.offset;
14051 dma_addr_t addr = ctl->data.io.dma_addr;
14052
14053 bnx2x_ilt_wr(bp, index, addr);
14054 break;
14055 }
14056
c2bff63f
DK		 14057 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14058 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 14059
14060 bnx2x_cnic_sp_post(bp, count);
14061 break;
14062 }
14063
14064 /* rtnl_lock is held. */
14065 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 14066 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14067 unsigned long sp_bits = 0;
14068
14069 /* Configure the iSCSI classification object */
14070 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14071 cp->iscsi_l2_client_id,
14072 cp->iscsi_l2_cid, BP_FUNC(bp),
14073 bnx2x_sp(bp, mac_rdata),
14074 bnx2x_sp_mapping(bp, mac_rdata),
14075 BNX2X_FILTER_MAC_PENDING,
14076 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14077 &bp->macs_pool);
ec6ba945 14078
523224a3 14079 /* Set iSCSI MAC address */
619c5cb6
VZ		 14080 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14081 if (rc)
14082 break;
523224a3
DK		 14083
14084 mmiowb();
14085 barrier();
14086
619c5cb6
VZ		 14087 /* Start accepting on iSCSI L2 ring */
14088
14089 netif_addr_lock_bh(dev);
14090 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14091 netif_addr_unlock_bh(dev);
14092
14093 /* bits to wait on */
14094 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14095 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14096
14097 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14098 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 14099
993ac7b5
MC		 14100 break;
14101 }
14102
14103 /* rtnl_lock is held. */
14104 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 14105 unsigned long sp_bits = 0;
993ac7b5 14106
523224a3 14107 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 14108 netif_addr_lock_bh(dev);
14109 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14110 netif_addr_unlock_bh(dev);
14111
14112 /* bits to wait on */
14113 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14114 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14115
14116 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14117 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 14118
14119 mmiowb();
14120 barrier();
14121
14122 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 14123 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14124 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 14125 break;
14126 }
c2bff63f
DK		 14127 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14128 int count = ctl->data.credit.credit_count;
14129
4e857c58 14130 smp_mb__before_atomic();
6e30dd4e 14131 atomic_add(count, &bp->cq_spq_left);
4e857c58 14132 smp_mb__after_atomic();
c2bff63f
DK		 14133 break;
14134 }
1d187b34 14135 case DRV_CTL_ULP_REGISTER_CMD: {
2e499d3c 14136 int ulp_type = ctl->data.register_data.ulp_type;
1d187b34
BW		 14137
14138 if (CHIP_IS_E3(bp)) {
14139 int idx = BP_FW_MB_IDX(bp);
2e499d3c
BW		 14140 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14141 int path = BP_PATH(bp);
14142 int port = BP_PORT(bp);
14143 int i;
14144 u32 scratch_offset;
14145 u32 *host_addr;
1d187b34 14146
2e499d3c 14147 /* first write capability to shmem2 */
1d187b34
BW		 14148 if (ulp_type == CNIC_ULP_ISCSI)
14149 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14150 else if (ulp_type == CNIC_ULP_FCOE)
14151 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14152 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
2e499d3c
BW		 14153
14154 if ((ulp_type != CNIC_ULP_FCOE) ||
14155 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14156 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
14157 break;
14158
14159 /* if reached here - should write fcoe capabilities */
14160 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14161 if (!scratch_offset)
14162 break;
14163 scratch_offset += offsetof(struct glob_ncsi_oem_data,
14164 fcoe_features[path][port]);
14165 host_addr = (u32 *) &(ctl->data.register_data.
14166 fcoe_features);
14167 for (i = 0; i < sizeof(struct fcoe_capabilities);
14168 i += 4)
14169 REG_WR(bp, scratch_offset + i,
14170 *(host_addr + i/4));
1d187b34 14171 }
42f8277f 14172 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 14173 break;
14174 }
2e499d3c 14175
1d187b34
BW		 14176 case DRV_CTL_ULP_UNREGISTER_CMD: {
14177 int ulp_type = ctl->data.ulp_type;
14178
14179 if (CHIP_IS_E3(bp)) {
14180 int idx = BP_FW_MB_IDX(bp);
14181 u32 cap;
14182
14183 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14184 if (ulp_type == CNIC_ULP_ISCSI)
14185 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14186 else if (ulp_type == CNIC_ULP_FCOE)
14187 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14188 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14189 }
42f8277f 14190 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 14191 break;
14192 }
993ac7b5
MC		 14193
14194 default:
14195 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14196 rc = -EINVAL;
14197 }
14198
14199 return rc;
14200}
14201
9f6c9258 14202void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 14203{
14204 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14205
14206 if (bp->flags & USING_MSIX_FLAG) {
14207 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14208 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14209 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14210 } else {
14211 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14212 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14213 }
619c5cb6 14214 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 14215 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14216 else
14217 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14218
619c5cb6
VZ		 14219 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
14220 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 14221 cp->irq_arr[1].status_blk = bp->def_status_blk;
14222 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 14223 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 14224
14225 cp->num_irq = 2;
14226}
14227
37ae41a9
MS		 14228void bnx2x_setup_cnic_info(struct bnx2x *bp)
14229{
14230 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14231
37ae41a9
MS		 14232 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14233 bnx2x_cid_ilt_lines(bp);
14234 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14235 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14236 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14237
f78afb35
MC		 14238 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14239 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14240 cp->iscsi_l2_cid);
14241
37ae41a9
MS		 14242 if (NO_ISCSI_OOO(bp))
14243 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14244}
14245
993ac7b5
MC		 14246static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14247 void *data)
14248{
14249 struct bnx2x *bp = netdev_priv(dev);
14250 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
55c11941
MS		 14251 int rc;
14252
14253 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
993ac7b5 14254
51c1a580
MS		 14255 if (ops == NULL) {
14256 BNX2X_ERR("NULL ops received\n");
993ac7b5 14257 return -EINVAL;
51c1a580 14258 }
993ac7b5 14259
55c11941
MS		 14260 if (!CNIC_SUPPORT(bp)) {
14261 BNX2X_ERR("Can't register CNIC when not supported\n");
14262 return -EOPNOTSUPP;
14263 }
14264
14265 if (!CNIC_LOADED(bp)) {
14266 rc = bnx2x_load_cnic(bp);
14267 if (rc) {
14268 BNX2X_ERR("CNIC-related load failed\n");
14269 return rc;
14270 }
55c11941
MS		 14271 }
14272
14273 bp->cnic_enabled = true;
14274
993ac7b5
MC		 14275 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14276 if (!bp->cnic_kwq)
14277 return -ENOMEM;
14278
14279 bp->cnic_kwq_cons = bp->cnic_kwq;
14280 bp->cnic_kwq_prod = bp->cnic_kwq;
14281 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14282
14283 bp->cnic_spq_pending = 0;
14284 bp->cnic_kwq_pending = 0;
14285
14286 bp->cnic_data = data;
14287
14288 cp->num_irq = 0;
619c5cb6 14289 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 14290 cp->iro_arr = bp->iro_arr;
993ac7b5 14291
993ac7b5 14292 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 14293
993ac7b5
MC		 14294 rcu_assign_pointer(bp->cnic_ops, ops);
14295
42f8277f
YM		 14296 /* Schedule driver to read CNIC driver versions */
14297 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14298
993ac7b5
MC		 14299 return 0;
14300}
14301
14302static int bnx2x_unregister_cnic(struct net_device *dev)
14303{
14304 struct bnx2x *bp = netdev_priv(dev);
14305 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14306
14307 mutex_lock(&bp->cnic_mutex);
993ac7b5 14308 cp->drv_state = 0;
2cfa5a04 14309 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 14310 mutex_unlock(&bp->cnic_mutex);
14311 synchronize_rcu();
fea75645 14312 bp->cnic_enabled = false;
993ac7b5
MC		 14313 kfree(bp->cnic_kwq);
14314 bp->cnic_kwq = NULL;
14315
14316 return 0;
14317}
14318
a8f47eb7 14319static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
993ac7b5
MC		 14320{
14321 struct bnx2x *bp = netdev_priv(dev);
14322 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14323
2ba45142
VZ		 14324 /* If both iSCSI and FCoE are disabled - return NULL in
14325 * order to indicate CNIC that it should not try to work
14326 * with this device.
14327 */
14328 if (NO_ISCSI(bp) && NO_FCOE(bp))
14329 return NULL;
14330
993ac7b5
MC		 14331 cp->drv_owner = THIS_MODULE;
14332 cp->chip_id = CHIP_ID(bp);
14333 cp->pdev = bp->pdev;
14334 cp->io_base = bp->regview;
14335 cp->io_base2 = bp->doorbells;
14336 cp->max_kwqe_pending = 8;
523224a3 14337 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 14338 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14339 bnx2x_cid_ilt_lines(bp);
993ac7b5 14340 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 14341 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 14342 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14343 cp->drv_ctl = bnx2x_drv_ctl;
14344 cp->drv_register_cnic = bnx2x_register_cnic;
14345 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
37ae41a9 14346 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
619c5cb6
VZ		 14347 cp->iscsi_l2_client_id =
14348 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
37ae41a9 14349 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
c2bff63f 14350
2ba45142
VZ		 14351 if (NO_ISCSI_OOO(bp))
14352 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14353
14354 if (NO_ISCSI(bp))
14355 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14356
14357 if (NO_FCOE(bp))
14358 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14359
51c1a580
MS		 14360 BNX2X_DEV_INFO(
14361 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
c2bff63f
DK		 14362 cp->ctx_blk_size,
14363 cp->ctx_tbl_offset,
14364 cp->ctx_tbl_len,
14365 cp->starting_cid);
993ac7b5
MC		 14366 return cp;
14367}
993ac7b5 14368
a8f47eb7 14369static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
9b176b6b 14370{
6411280a
AE		 14371 struct bnx2x *bp = fp->bp;
14372 u32 offset = BAR_USTRORM_INTMEM;
abc5a021 14373
6411280a
AE		 14374 if (IS_VF(bp))
14375 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14376 else if (!CHIP_IS_E1x(bp))
14377 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14378 else
14379 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
8d9ac297 14380
6411280a 14381 return offset;
8d9ac297 14382}
381ac16b 14383
6411280a
AE		 14384/* called only on E1H or E2.
14385 * When pretending to be PF, the pretend value is the function number 0...7
14386 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14387 * combination
14388 */
14389int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
381ac16b 14390{
6411280a 14391 u32 pretend_reg;
381ac16b 14392
23826850 14393 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
6411280a 14394 return -1;
381ac16b 14395
6411280a
AE		 14396 /* get my own pretend register */
14397 pretend_reg = bnx2x_get_pretend_reg(bp);
14398 REG_WR(bp, pretend_reg, pretend_func_val);
14399 REG_RD(bp, pretend_reg);
381ac16b
AE		 14400 return 0;
14401}
eeed018c
MK		 14402
14403static void bnx2x_ptp_task(struct work_struct *work)
14404{
14405 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
14406 int port = BP_PORT(bp);
14407 u32 val_seq;
14408 u64 timestamp, ns;
14409 struct skb_shared_hwtstamps shhwtstamps;
14410
14411 /* Read Tx timestamp registers */
14412 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14413 NIG_REG_P0_TLLH_PTP_BUF_SEQID);
14414 if (val_seq & 0x10000) {
14415 /* There is a valid timestamp value */
14416 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
14417 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
14418 timestamp <<= 32;
14419 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
14420 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
14421 /* Reset timestamp register to allow new timestamp */
14422 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14423 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14424 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14425
14426 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
14427 shhwtstamps.hwtstamp = ns_to_ktime(ns);
14428 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
14429 dev_kfree_skb_any(bp->ptp_tx_skb);
14430 bp->ptp_tx_skb = NULL;
14431
14432 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
14433 timestamp, ns);
14434 } else {
14435 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
14436 /* Reschedule to keep checking for a valid timestamp value */
14437 schedule_work(&bp->ptp_task);
14438 }
14439}
14440
14441void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
14442{
14443 int port = BP_PORT(bp);
14444 u64 timestamp, ns;
14445
14446 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
14447 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
14448 timestamp <<= 32;
14449 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
14450 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
14451
14452 /* Reset timestamp register to allow new timestamp */
14453 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14454 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14455
14456 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14457
14458 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
14459
14460 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
14461 timestamp, ns);
14462}
14463
14464/* Read the PHC */
14465static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
14466{
14467 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
14468 int port = BP_PORT(bp);
14469 u32 wb_data[2];
14470 u64 phc_cycles;
14471
14472 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
14473 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
14474 phc_cycles = wb_data[1];
14475 phc_cycles = (phc_cycles << 32) + wb_data[0];
14476
14477 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
14478
14479 return phc_cycles;
14480}
14481
14482static void bnx2x_init_cyclecounter(struct bnx2x *bp)
14483{
14484 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
14485 bp->cyclecounter.read = bnx2x_cyclecounter_read;
14486 bp->cyclecounter.mask = CLOCKSOURCE_MASK(64);
14487 bp->cyclecounter.shift = 1;
14488 bp->cyclecounter.mult = 1;
14489}
14490
14491static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
14492{
14493 struct bnx2x_func_state_params func_params = {NULL};
14494 struct bnx2x_func_set_timesync_params *set_timesync_params =
14495 &func_params.params.set_timesync;
14496
14497 /* Prepare parameters for function state transitions */
14498 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
14499 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
14500
14501 func_params.f_obj = &bp->func_obj;
14502 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
14503
14504 /* Function parameters */
14505 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
14506 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
14507
14508 return bnx2x_func_state_change(bp, &func_params);
14509}
14510
14511int bnx2x_enable_ptp_packets(struct bnx2x *bp)
14512{
14513 struct bnx2x_queue_state_params q_params;
14514 int rc, i;
14515
14516 /* send queue update ramrod to enable PTP packets */
14517 memset(&q_params, 0, sizeof(q_params));
14518 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
14519 q_params.cmd = BNX2X_Q_CMD_UPDATE;
14520 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
14521 &q_params.params.update.update_flags);
14522 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
14523 &q_params.params.update.update_flags);
14524
14525 /* send the ramrod on all the queues of the PF */
14526 for_each_eth_queue(bp, i) {
14527 struct bnx2x_fastpath *fp = &bp->fp[i];
14528
14529 /* Set the appropriate Queue object */
14530 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
14531
14532 /* Update the Queue state */
14533 rc = bnx2x_queue_state_change(bp, &q_params);
14534 if (rc) {
14535 BNX2X_ERR("Failed to enable PTP packets\n");
14536 return rc;
14537 }
14538 }
14539
14540 return 0;
14541}
14542
14543int bnx2x_configure_ptp_filters(struct bnx2x *bp)
14544{
14545 int port = BP_PORT(bp);
14546 int rc;
14547
14548 if (!bp->hwtstamp_ioctl_called)
14549 return 0;
14550
14551 switch (bp->tx_type) {
14552 case HWTSTAMP_TX_ON:
14553 bp->flags |= TX_TIMESTAMPING_EN;
14554 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14555 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
14556 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14557 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
14558 break;
14559 case HWTSTAMP_TX_ONESTEP_SYNC:
14560 BNX2X_ERR("One-step timestamping is not supported\n");
14561 return -ERANGE;
14562 }
14563
14564 switch (bp->rx_filter) {
14565 case HWTSTAMP_FILTER_NONE:
14566 break;
14567 case HWTSTAMP_FILTER_ALL:
14568 case HWTSTAMP_FILTER_SOME:
14569 bp->rx_filter = HWTSTAMP_FILTER_NONE;
14570 break;
14571 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
14572 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
14573 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
14574 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
14575 /* Initialize PTP detection for UDP/IPv4 events */
14576 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14577 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
14578 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14579 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
14580 break;
14581 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
14582 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
14583 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
14584 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
14585 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
14586 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14587 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
14588 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14589 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
14590 break;
14591 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
14592 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
14593 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
14594 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
14595 /* Initialize PTP detection L2 events */
14596 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14597 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
14598 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14599 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
14600
14601 break;
14602 case HWTSTAMP_FILTER_PTP_V2_EVENT:
14603 case HWTSTAMP_FILTER_PTP_V2_SYNC:
14604 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
14605 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
14606 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
14607 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14608 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
14609 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14610 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
14611 break;
14612 }
14613
14614 /* Indicate to FW that this PF expects recorded PTP packets */
14615 rc = bnx2x_enable_ptp_packets(bp);
14616 if (rc)
14617 return rc;
14618
14619 /* Enable sending PTP packets to host */
14620 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14621 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
14622
14623 return 0;
14624}
14625
14626static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
14627{
14628 struct hwtstamp_config config;
14629 int rc;
14630
14631 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
14632
14633 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
14634 return -EFAULT;
14635
14636 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
14637 config.tx_type, config.rx_filter);
14638
14639 if (config.flags) {
14640 BNX2X_ERR("config.flags is reserved for future use\n");
14641 return -EINVAL;
14642 }
14643
14644 bp->hwtstamp_ioctl_called = 1;
14645 bp->tx_type = config.tx_type;
14646 bp->rx_filter = config.rx_filter;
14647
14648 rc = bnx2x_configure_ptp_filters(bp);
14649 if (rc)
14650 return rc;
14651
14652 config.rx_filter = bp->rx_filter;
14653
14654 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
14655 -EFAULT : 0;
14656}
14657
14658/* Configrues HW for PTP */
14659static int bnx2x_configure_ptp(struct bnx2x *bp)
14660{
14661 int rc, port = BP_PORT(bp);
14662 u32 wb_data[2];
14663
14664 /* Reset PTP event detection rules - will be configured in the IOCTL */
14665 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14666 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
14667 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14668 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
14669 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14670 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
14671 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14672 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
14673
14674 /* Disable PTP packets to host - will be configured in the IOCTL*/
14675 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14676 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
14677
14678 /* Enable the PTP feature */
14679 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
14680 NIG_REG_P0_PTP_EN, 0x3F);
14681
14682 /* Enable the free-running counter */
14683 wb_data[0] = 0;
14684 wb_data[1] = 0;
14685 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
14686
14687 /* Reset drift register (offset register is not reset) */
14688 rc = bnx2x_send_reset_timesync_ramrod(bp);
14689 if (rc) {
14690 BNX2X_ERR("Failed to reset PHC drift register\n");
14691 return -EFAULT;
14692 }
14693
14694 /* Reset possibly old timestamps */
14695 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14696 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14697 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14698 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14699
14700 return 0;
14701}
14702
14703/* Called during load, to initialize PTP-related stuff */
14704void bnx2x_init_ptp(struct bnx2x *bp)
14705{
14706 int rc;
14707
14708 /* Configure PTP in HW */
14709 rc = bnx2x_configure_ptp(bp);
14710 if (rc) {
14711 BNX2X_ERR("Stopping PTP initialization\n");
14712 return;
14713 }
14714
14715 /* Init work queue for Tx timestamping */
14716 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
14717
14718 /* Init cyclecounter and timecounter. This is done only in the first
14719 * load. If done in every load, PTP application will fail when doing
14720 * unload / load (e.g. MTU change) while it is running.
14721 */
14722 if (!bp->timecounter_init_done) {
14723 bnx2x_init_cyclecounter(bp);
14724 timecounter_init(&bp->timecounter, &bp->cyclecounter,
14725 ktime_to_ns(ktime_get_real()));
14726 bp->timecounter_init_done = 1;
14727 }
14728
14729 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
14730}
Linux kernel - Deliverables
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