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bnx2x: Make BP_VF more robust
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
08f6dd89 9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
24e3fcef 10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
f1deab50
JP		 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
a2fbb9ea
ET		 20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/device.h> /* for dev_info() */
24#include <linux/timer.h>
25#include <linux/errno.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
a2fbb9ea
ET		 28#include <linux/interrupt.h>
29#include <linux/pci.h>
33d8e6a5 30#include <linux/aer.h>
a2fbb9ea
ET		 31#include <linux/init.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/dma-mapping.h>
36#include <linux/bitops.h>
37#include <linux/irq.h>
38#include <linux/delay.h>
39#include <asm/byteorder.h>
40#include <linux/time.h>
41#include <linux/ethtool.h>
42#include <linux/mii.h>
0c6671b0 43#include <linux/if_vlan.h>
a2fbb9ea 44#include <net/ip.h>
619c5cb6 45#include <net/ipv6.h>
a2fbb9ea
ET		 46#include <net/tcp.h>
47#include <net/checksum.h>
34f80b04 48#include <net/ip6_checksum.h>
a2fbb9ea
ET		 49#include <linux/workqueue.h>
50#include <linux/crc32.h>
34f80b04 51#include <linux/crc32c.h>
a2fbb9ea
ET		 52#include <linux/prefetch.h>
53#include <linux/zlib.h>
a2fbb9ea 54#include <linux/io.h>
452427b0 55#include <linux/semaphore.h>
45229b42 56#include <linux/stringify.h>
7ab24bfd 57#include <linux/vmalloc.h>
a2fbb9ea 58
a2fbb9ea
ET		 59#include "bnx2x.h"
60#include "bnx2x_init.h"
94a78b79 61#include "bnx2x_init_ops.h"
9f6c9258 62#include "bnx2x_cmn.h"
1ab4434c 63#include "bnx2x_vfpf.h"
e4901dde 64#include "bnx2x_dcb.h"
042181f5 65#include "bnx2x_sp.h"
94a78b79
VZ		 66#include <linux/firmware.h>
67#include "bnx2x_fw_file_hdr.h"
68/* FW files */
45229b42
BH		 69#define FW_FILE_VERSION \
70 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
71 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
72 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
73 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 74#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
75#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 76#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 77
34f80b04
EG		 78/* Time in jiffies before concluding the transmitter is hung */
79#define TX_TIMEOUT (5*HZ)
a2fbb9ea 80
0329aba1 81static char version[] =
619c5cb6 82 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 83 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
84
24e3fcef 85MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 86MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 87 "BCM57710/57711/57711E/"
88 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
89 "57840/57840_MF Driver");
a2fbb9ea
ET		 90MODULE_LICENSE("GPL");
91MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 92MODULE_FIRMWARE(FW_FILE_NAME_E1);
93MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 94MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 95
a8f47eb7 96int bnx2x_num_queues;
1c8bb760 97module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
96305234
DK		 98MODULE_PARM_DESC(num_queues,
99 " Set number of queues (default is as a number of CPUs)");
555f6c78 100
19680c48 101static int disable_tpa;
1c8bb760 102module_param(disable_tpa, int, S_IRUGO);
9898f86d 103MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 104
a8f47eb7 105static int int_mode;
1c8bb760 106module_param(int_mode, int, S_IRUGO);
619c5cb6 107MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 108 "(1 INT#x; 2 MSI)");
8badd27a 109
a18f5128 110static int dropless_fc;
1c8bb760 111module_param(dropless_fc, int, S_IRUGO);
a18f5128
EG		 112MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
113
8d5726c4 114static int mrrs = -1;
1c8bb760 115module_param(mrrs, int, S_IRUGO);
8d5726c4
EG		 116MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
117
9898f86d 118static int debug;
1c8bb760 119module_param(debug, int, S_IRUGO);
9898f86d
EG		 120MODULE_PARM_DESC(debug, " Default debug msglevel");
121
370d4a26
YM		 122static struct workqueue_struct *bnx2x_wq;
123struct workqueue_struct *bnx2x_iov_wq;
ec6ba945 124
1ef1d45a
BW		 125struct bnx2x_mac_vals {
126 u32 xmac_addr;
127 u32 xmac_val;
128 u32 emac_addr;
129 u32 emac_val;
130 u32 umac_addr;
131 u32 umac_val;
132 u32 bmac_addr;
133 u32 bmac_val[2];
134};
135
a2fbb9ea
ET		 136enum bnx2x_board_type {
137 BCM57710 = 0,
619c5cb6
VZ		 138 BCM57711,
139 BCM57711E,
140 BCM57712,
141 BCM57712_MF,
1ab4434c 142 BCM57712_VF,
619c5cb6
VZ		 143 BCM57800,
144 BCM57800_MF,
1ab4434c 145 BCM57800_VF,
619c5cb6
VZ		 146 BCM57810,
147 BCM57810_MF,
1ab4434c 148 BCM57810_VF,
c3def943
YM		 149 BCM57840_4_10,
150 BCM57840_2_20,
7e8e02df 151 BCM57840_MF,
1ab4434c 152 BCM57840_VF,
7e8e02df 153 BCM57811,
1ab4434c
AE		 154 BCM57811_MF,
155 BCM57840_O,
156 BCM57840_MFO,
157 BCM57811_VF
a2fbb9ea
ET		 158};
159
34f80b04 160/* indexed by board_type, above */
53a10565 161static struct {
a2fbb9ea 162 char *name;
0329aba1 163} board_info[] = {
1ab4434c
AE		 164 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
165 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
166 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
167 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
168 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
169 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
170 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
171 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
172 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
173 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
174 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
175 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
176 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
177 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
178 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
179 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
180 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
181 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
182 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
183 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
184 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
a2fbb9ea
ET		 185};
186
619c5cb6
VZ		 187#ifndef PCI_DEVICE_ID_NX2_57710
188#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
189#endif
190#ifndef PCI_DEVICE_ID_NX2_57711
191#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
192#endif
193#ifndef PCI_DEVICE_ID_NX2_57711E
194#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
195#endif
196#ifndef PCI_DEVICE_ID_NX2_57712
197#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
198#endif
199#ifndef PCI_DEVICE_ID_NX2_57712_MF
200#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
201#endif
8395be5e
AE		 202#ifndef PCI_DEVICE_ID_NX2_57712_VF
203#define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
204#endif
619c5cb6
VZ		 205#ifndef PCI_DEVICE_ID_NX2_57800
206#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
207#endif
208#ifndef PCI_DEVICE_ID_NX2_57800_MF
209#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
210#endif
8395be5e
AE		 211#ifndef PCI_DEVICE_ID_NX2_57800_VF
212#define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
213#endif
619c5cb6
VZ		 214#ifndef PCI_DEVICE_ID_NX2_57810
215#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
216#endif
217#ifndef PCI_DEVICE_ID_NX2_57810_MF
218#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
219#endif
c3def943
YM		 220#ifndef PCI_DEVICE_ID_NX2_57840_O
221#define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
222#endif
8395be5e
AE		 223#ifndef PCI_DEVICE_ID_NX2_57810_VF
224#define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
225#endif
c3def943
YM		 226#ifndef PCI_DEVICE_ID_NX2_57840_4_10
227#define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
228#endif
229#ifndef PCI_DEVICE_ID_NX2_57840_2_20
230#define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
231#endif
232#ifndef PCI_DEVICE_ID_NX2_57840_MFO
233#define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
619c5cb6
VZ		 234#endif
235#ifndef PCI_DEVICE_ID_NX2_57840_MF
236#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
237#endif
8395be5e
AE		 238#ifndef PCI_DEVICE_ID_NX2_57840_VF
239#define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
240#endif
7e8e02df
BW		 241#ifndef PCI_DEVICE_ID_NX2_57811
242#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
243#endif
244#ifndef PCI_DEVICE_ID_NX2_57811_MF
245#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
246#endif
8395be5e
AE		 247#ifndef PCI_DEVICE_ID_NX2_57811_VF
248#define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
249#endif
250
9baa3c34 251static const struct pci_device_id bnx2x_pci_tbl[] = {
e4ed7113
EG		 252 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
253 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
254 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6 256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
8395be5e 257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
619c5cb6
VZ		 258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
8395be5e 260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
619c5cb6
VZ		 261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
c3def943
YM		 263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
8395be5e 266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
c3def943 267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
619c5cb6 268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
8395be5e 269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
7e8e02df
BW		 270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
8395be5e 272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
a2fbb9ea
ET		 273 { 0 }
274};
275
276MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
277
452427b0
YM		 278/* Global resources for unloading a previously loaded device */
279#define BNX2X_PREV_WAIT_NEEDED 1
280static DEFINE_SEMAPHORE(bnx2x_prev_sem);
281static LIST_HEAD(bnx2x_prev_list);
a8f47eb7 282
283/* Forward declaration */
284static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
285static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
286static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
287
a2fbb9ea
ET		 288/****************************************************************************
289* General service functions
290****************************************************************************/
291
eeed018c
MK		 292static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
293
1191cb83 294static void __storm_memset_dma_mapping(struct bnx2x *bp,
619c5cb6
VZ		 295 u32 addr, dma_addr_t mapping)
296{
297 REG_WR(bp, addr, U64_LO(mapping));
298 REG_WR(bp, addr + 4, U64_HI(mapping));
299}
300
1191cb83
ED		 301static void storm_memset_spq_addr(struct bnx2x *bp,
302 dma_addr_t mapping, u16 abs_fid)
619c5cb6
VZ		 303{
304 u32 addr = XSEM_REG_FAST_MEMORY +
305 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
306
307 __storm_memset_dma_mapping(bp, addr, mapping);
308}
309
1191cb83
ED		 310static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
311 u16 pf_id)
523224a3 312{
619c5cb6
VZ		 313 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
314 pf_id);
315 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
316 pf_id);
317 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
318 pf_id);
319 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
320 pf_id);
523224a3
DK		 321}
322
1191cb83
ED		 323static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
324 u8 enable)
619c5cb6
VZ		 325{
326 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
327 enable);
328 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
329 enable);
330 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
331 enable);
332 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
333 enable);
334}
523224a3 335
1191cb83
ED		 336static void storm_memset_eq_data(struct bnx2x *bp,
337 struct event_ring_data *eq_data,
523224a3
DK		 338 u16 pfid)
339{
340 size_t size = sizeof(struct event_ring_data);
341
342 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
343
344 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
345}
346
1191cb83
ED		 347static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
348 u16 pfid)
523224a3
DK		 349{
350 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
351 REG_WR16(bp, addr, eq_prod);
352}
353
a2fbb9ea
ET		 354/* used only at init
355 * locking is done by mcp
356 */
8d96286a 357static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 358{
359 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
360 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
361 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
362 PCICFG_VENDOR_ID_OFFSET);
363}
364
a2fbb9ea
ET		 365static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
366{
367 u32 val;
368
369 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
370 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
371 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
372 PCICFG_VENDOR_ID_OFFSET);
373
374 return val;
375}
a2fbb9ea 376
f2e0899f
DK		 377#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
378#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
379#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
380#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
381#define DMAE_DP_DST_NONE "dst_addr [none]"
382
6bf07b8e
YM		 383static void bnx2x_dp_dmae(struct bnx2x *bp,
384 struct dmae_command *dmae, int msglvl)
fd1fc79d
AE		 385{
386 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
6bf07b8e 387 int i;
fd1fc79d
AE		 388
389 switch (dmae->opcode & DMAE_COMMAND_DST) {
390 case DMAE_CMD_DST_PCI:
391 if (src_type == DMAE_CMD_SRC_PCI)
392 DP(msglvl, "DMAE: opcode 0x%08x\n"
393 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
394 "comp_addr [%x:%08x], comp_val 0x%08x\n",
395 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
396 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
397 dmae->comp_addr_hi, dmae->comp_addr_lo,
398 dmae->comp_val);
399 else
400 DP(msglvl, "DMAE: opcode 0x%08x\n"
401 "src [%08x], len [%d*4], dst [%x:%08x]\n"
402 "comp_addr [%x:%08x], comp_val 0x%08x\n",
403 dmae->opcode, dmae->src_addr_lo >> 2,
404 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
405 dmae->comp_addr_hi, dmae->comp_addr_lo,
406 dmae->comp_val);
407 break;
408 case DMAE_CMD_DST_GRC:
409 if (src_type == DMAE_CMD_SRC_PCI)
410 DP(msglvl, "DMAE: opcode 0x%08x\n"
411 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
412 "comp_addr [%x:%08x], comp_val 0x%08x\n",
413 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
414 dmae->len, dmae->dst_addr_lo >> 2,
415 dmae->comp_addr_hi, dmae->comp_addr_lo,
416 dmae->comp_val);
417 else
418 DP(msglvl, "DMAE: opcode 0x%08x\n"
419 "src [%08x], len [%d*4], dst [%08x]\n"
420 "comp_addr [%x:%08x], comp_val 0x%08x\n",
421 dmae->opcode, dmae->src_addr_lo >> 2,
422 dmae->len, dmae->dst_addr_lo >> 2,
423 dmae->comp_addr_hi, dmae->comp_addr_lo,
424 dmae->comp_val);
425 break;
426 default:
427 if (src_type == DMAE_CMD_SRC_PCI)
428 DP(msglvl, "DMAE: opcode 0x%08x\n"
429 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
430 "comp_addr [%x:%08x] comp_val 0x%08x\n",
431 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
432 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
433 dmae->comp_val);
434 else
435 DP(msglvl, "DMAE: opcode 0x%08x\n"
436 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
437 "comp_addr [%x:%08x] comp_val 0x%08x\n",
438 dmae->opcode, dmae->src_addr_lo >> 2,
439 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
440 dmae->comp_val);
441 break;
442 }
6bf07b8e
YM		 443
444 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
445 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
446 i, *(((u32 *)dmae) + i));
fd1fc79d 447}
f2e0899f 448
a2fbb9ea 449/* copy command into DMAE command memory and set DMAE command go */
6c719d00 450void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 451{
452 u32 cmd_offset;
453 int i;
454
455 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
456 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
457 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 458 }
459 REG_WR(bp, dmae_reg_go_c[idx], 1);
460}
461
f2e0899f 462u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 463{
f2e0899f
DK		 464 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
465 DMAE_CMD_C_ENABLE);
466}
ad8d3948 467
f2e0899f
DK		 468u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
469{
470 return opcode & ~DMAE_CMD_SRC_RESET;
471}
ad8d3948 472
f2e0899f
DK		 473u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
474 bool with_comp, u8 comp_type)
475{
476 u32 opcode = 0;
477
478 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
479 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 480
f2e0899f
DK		 481 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
482
483 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 484 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
485 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 486 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 487
a2fbb9ea 488#ifdef __BIG_ENDIAN
f2e0899f 489 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 490#else
f2e0899f 491 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 492#endif
f2e0899f
DK		 493 if (with_comp)
494 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
495 return opcode;
496}
497
fd1fc79d 498void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
8d96286a 499 struct dmae_command *dmae,
500 u8 src_type, u8 dst_type)
f2e0899f
DK		 501{
502 memset(dmae, 0, sizeof(struct dmae_command));
503
504 /* set the opcode */
505 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
506 true, DMAE_COMP_PCI);
507
508 /* fill in the completion parameters */
509 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
510 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
511 dmae->comp_val = DMAE_COMP_VAL;
512}
513
fd1fc79d 514/* issue a dmae command over the init-channel and wait for completion */
32316a46
AE		 515int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
516 u32 *comp)
f2e0899f 517{
5e374b5a 518 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 519 int rc = 0;
520
6bf07b8e
YM		 521 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
522
523 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
619c5cb6
VZ		 524 * as long as this code is called both from syscall context and
525 * from ndo_set_rx_mode() flow that may be called from BH.
526 */
eeed018c 527
6e30dd4e 528 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 529
f2e0899f 530 /* reset completion */
32316a46 531 *comp = 0;
a2fbb9ea 532
f2e0899f
DK		 533 /* post the command on the channel used for initializations */
534 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 535
f2e0899f 536 /* wait for completion */
a2fbb9ea 537 udelay(5);
32316a46 538 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948 539
95c6c616
AE		 540 if (!cnt ||
541 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
542 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
c3eefaf6 543 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 544 rc = DMAE_TIMEOUT;
545 goto unlock;
a2fbb9ea 546 }
ad8d3948 547 cnt--;
f2e0899f 548 udelay(50);
a2fbb9ea 549 }
32316a46 550 if (*comp & DMAE_PCI_ERR_FLAG) {
f2e0899f
DK		 551 BNX2X_ERR("DMAE PCI error!\n");
552 rc = DMAE_PCI_ERROR;
553 }
554
f2e0899f 555unlock:
eeed018c 556
6e30dd4e 557 spin_unlock_bh(&bp->dmae_lock);
eeed018c 558
f2e0899f
DK		 559 return rc;
560}
561
562void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
563 u32 len32)
564{
6bf07b8e 565 int rc;
f2e0899f
DK		 566 struct dmae_command dmae;
567
568 if (!bp->dmae_ready) {
569 u32 *data = bnx2x_sp(bp, wb_data[0]);
570
127a425e
AE		 571 if (CHIP_IS_E1(bp))
572 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
573 else
574 bnx2x_init_str_wr(bp, dst_addr, data, len32);
f2e0899f
DK		 575 return;
576 }
577
578 /* set opcode and fixed command fields */
579 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
580
581 /* fill in addresses and len */
582 dmae.src_addr_lo = U64_LO(dma_addr);
583 dmae.src_addr_hi = U64_HI(dma_addr);
584 dmae.dst_addr_lo = dst_addr >> 2;
585 dmae.dst_addr_hi = 0;
586 dmae.len = len32;
587
f2e0899f 588 /* issue the command and wait for completion */
32316a46 589 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 590 if (rc) {
591 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 592#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 593 bnx2x_panic();
9dcd9acd 594#endif
6bf07b8e 595 }
a2fbb9ea
ET		 596}
597
c18487ee 598void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 599{
6bf07b8e 600 int rc;
5ff7b6d4 601 struct dmae_command dmae;
ad8d3948
EG		 602
603 if (!bp->dmae_ready) {
604 u32 *data = bnx2x_sp(bp, wb_data[0]);
605 int i;
606
51c1a580 607 if (CHIP_IS_E1(bp))
127a425e
AE		 608 for (i = 0; i < len32; i++)
609 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
51c1a580 610 else
127a425e
AE		 611 for (i = 0; i < len32; i++)
612 data[i] = REG_RD(bp, src_addr + i*4);
613
ad8d3948
EG		 614 return;
615 }
616
f2e0899f
DK		 617 /* set opcode and fixed command fields */
618 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 619
f2e0899f 620 /* fill in addresses and len */
5ff7b6d4
EG		 621 dmae.src_addr_lo = src_addr >> 2;
622 dmae.src_addr_hi = 0;
623 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
624 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
625 dmae.len = len32;
ad8d3948 626
f2e0899f 627 /* issue the command and wait for completion */
32316a46 628 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 629 if (rc) {
630 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 631#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 632 bnx2x_panic();
9dcd9acd 633#endif
c957d09f 634 }
ad8d3948
EG		 635}
636
8d96286a 637static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
638 u32 addr, u32 len)
573f2035 639{
02e3c6cb 640 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 641 int offset = 0;
642
02e3c6cb 643 while (len > dmae_wr_max) {
573f2035 644 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 645 addr + offset, dmae_wr_max);
646 offset += dmae_wr_max * 4;
647 len -= dmae_wr_max;
573f2035
EG		 648 }
649
650 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
651}
652
a2fbb9ea
ET		 653static int bnx2x_mc_assert(struct bnx2x *bp)
654{
a2fbb9ea 655 char last_idx;
34f80b04
EG		 656 int i, rc = 0;
657 u32 row0, row1, row2, row3;
658
659 /* XSTORM */
660 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
661 XSTORM_ASSERT_LIST_INDEX_OFFSET);
662 if (last_idx)
663 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
664
665 /* print the asserts */
666 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
667
668 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
669 XSTORM_ASSERT_LIST_OFFSET(i));
670 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
671 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
672 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
673 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
674 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
675 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
676
677 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 678 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 679 i, row3, row2, row1, row0);
680 rc++;
681 } else {
682 break;
683 }
684 }
685
686 /* TSTORM */
687 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
688 TSTORM_ASSERT_LIST_INDEX_OFFSET);
689 if (last_idx)
690 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
691
692 /* print the asserts */
693 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
694
695 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
696 TSTORM_ASSERT_LIST_OFFSET(i));
697 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
698 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
699 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
700 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
701 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
702 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
703
704 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 705 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 706 i, row3, row2, row1, row0);
707 rc++;
708 } else {
709 break;
710 }
711 }
712
713 /* CSTORM */
714 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
715 CSTORM_ASSERT_LIST_INDEX_OFFSET);
716 if (last_idx)
717 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
718
719 /* print the asserts */
720 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
721
722 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
723 CSTORM_ASSERT_LIST_OFFSET(i));
724 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
725 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
726 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
727 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
728 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
729 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
730
731 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 732 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 733 i, row3, row2, row1, row0);
734 rc++;
735 } else {
736 break;
737 }
738 }
739
740 /* USTORM */
741 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
742 USTORM_ASSERT_LIST_INDEX_OFFSET);
743 if (last_idx)
744 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
745
746 /* print the asserts */
747 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
748
749 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
750 USTORM_ASSERT_LIST_OFFSET(i));
751 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
752 USTORM_ASSERT_LIST_OFFSET(i) + 4);
753 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
754 USTORM_ASSERT_LIST_OFFSET(i) + 8);
755 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
756 USTORM_ASSERT_LIST_OFFSET(i) + 12);
757
758 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 759 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 760 i, row3, row2, row1, row0);
761 rc++;
762 } else {
763 break;
a2fbb9ea
ET		 764 }
765 }
34f80b04 766
a2fbb9ea
ET		 767 return rc;
768}
c14423fe 769
1a6974b2
YM		 770#define MCPR_TRACE_BUFFER_SIZE (0x800)
771#define SCRATCH_BUFFER_SIZE(bp) \
772 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
773
7a25cc73 774void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 775{
7a25cc73 776 u32 addr, val;
a2fbb9ea 777 u32 mark, offset;
4781bfad 778 __be32 data[9];
a2fbb9ea 779 int word;
f2e0899f 780 u32 trace_shmem_base;
2145a920
VZ		 781 if (BP_NOMCP(bp)) {
782 BNX2X_ERR("NO MCP - can not dump\n");
783 return;
784 }
7a25cc73
DK		 785 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
786 (bp->common.bc_ver & 0xff0000) >> 16,
787 (bp->common.bc_ver & 0xff00) >> 8,
788 (bp->common.bc_ver & 0xff));
789
790 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
791 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
51c1a580 792 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 793
f2e0899f
DK		 794 if (BP_PATH(bp) == 0)
795 trace_shmem_base = bp->common.shmem_base;
796 else
797 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
1a6974b2
YM		 798
799 /* sanity */
800 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
801 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
802 SCRATCH_BUFFER_SIZE(bp)) {
803 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
804 trace_shmem_base);
805 return;
806 }
807
808 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
de128804
DK		 809
810 /* validate TRCB signature */
811 mark = REG_RD(bp, addr);
812 if (mark != MFW_TRACE_SIGNATURE) {
813 BNX2X_ERR("Trace buffer signature is missing.");
814 return ;
815 }
816
817 /* read cyclic buffer pointer */
818 addr += 4;
cdaa7cb8 819 mark = REG_RD(bp, addr);
1a6974b2
YM		 820 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
821 if (mark >= trace_shmem_base || mark < addr + 4) {
822 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
823 return;
824 }
7a25cc73 825 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 826
7a25cc73 827 printk("%s", lvl);
2de67439
YM		 828
829 /* dump buffer after the mark */
1a6974b2 830 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 831 for (word = 0; word < 8; word++)
cdaa7cb8 832 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 833 data[8] = 0x0;
7995c64e 834 pr_cont("%s", (char *)data);
a2fbb9ea 835 }
2de67439
YM		 836
837 /* dump buffer before the mark */
cdaa7cb8 838 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 839 for (word = 0; word < 8; word++)
cdaa7cb8 840 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 841 data[8] = 0x0;
7995c64e 842 pr_cont("%s", (char *)data);
a2fbb9ea 843 }
7a25cc73
DK		 844 printk("%s" "end of fw dump\n", lvl);
845}
846
1191cb83 847static void bnx2x_fw_dump(struct bnx2x *bp)
7a25cc73
DK		 848{
849 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 850}
851
823e1d90
YM		 852static void bnx2x_hc_int_disable(struct bnx2x *bp)
853{
854 int port = BP_PORT(bp);
855 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
856 u32 val = REG_RD(bp, addr);
857
858 /* in E1 we must use only PCI configuration space to disable
16a5fd92
YM		 859 * MSI/MSIX capability
860 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
823e1d90
YM		 861 */
862 if (CHIP_IS_E1(bp)) {
863 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
864 * Use mask register to prevent from HC sending interrupts
865 * after we exit the function
866 */
867 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
868
869 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
870 HC_CONFIG_0_REG_INT_LINE_EN_0 |
871 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
872 } else
873 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
874 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
875 HC_CONFIG_0_REG_INT_LINE_EN_0 |
876 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
877
878 DP(NETIF_MSG_IFDOWN,
879 "write %x to HC %d (addr 0x%x)\n",
880 val, port, addr);
881
882 /* flush all outstanding writes */
883 mmiowb();
884
885 REG_WR(bp, addr, val);
886 if (REG_RD(bp, addr) != val)
6bf07b8e 887 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 888}
889
890static void bnx2x_igu_int_disable(struct bnx2x *bp)
891{
892 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
893
894 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
895 IGU_PF_CONF_INT_LINE_EN |
896 IGU_PF_CONF_ATTN_BIT_EN);
897
898 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
899
900 /* flush all outstanding writes */
901 mmiowb();
902
903 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
904 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
6bf07b8e 905 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 906}
907
908static void bnx2x_int_disable(struct bnx2x *bp)
909{
910 if (bp->common.int_block == INT_BLOCK_HC)
911 bnx2x_hc_int_disable(bp);
912 else
913 bnx2x_igu_int_disable(bp);
914}
915
916void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
a2fbb9ea
ET		 917{
918 int i;
523224a3
DK		 919 u16 j;
920 struct hc_sp_status_block_data sp_sb_data;
921 int func = BP_FUNC(bp);
922#ifdef BNX2X_STOP_ON_ERROR
923 u16 start = 0, end = 0;
6383c0b3 924 u8 cos;
523224a3 925#endif
0155a27c 926 if (IS_PF(bp) && disable_int)
823e1d90 927 bnx2x_int_disable(bp);
a2fbb9ea 928
66e855f3 929 bp->stats_state = STATS_STATE_DISABLED;
7a752993 930 bp->eth_stats.unrecoverable_error++;
66e855f3
YG		 931 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
932
a2fbb9ea
ET		 933 BNX2X_ERR("begin crash dump -----------------\n");
934
8440d2b6
EG		 935 /* Indices */
936 /* Common */
0155a27c
YM		 937 if (IS_PF(bp)) {
938 struct host_sp_status_block *def_sb = bp->def_status_blk;
939 int data_size, cstorm_offset;
940
941 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
942 bp->def_idx, bp->def_att_idx, bp->attn_state,
943 bp->spq_prod_idx, bp->stats_counter);
944 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
945 def_sb->atten_status_block.attn_bits,
946 def_sb->atten_status_block.attn_bits_ack,
947 def_sb->atten_status_block.status_block_id,
948 def_sb->atten_status_block.attn_bits_index);
949 BNX2X_ERR(" def (");
950 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
951 pr_cont("0x%x%s",
952 def_sb->sp_sb.index_values[i],
953 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
954
955 data_size = sizeof(struct hc_sp_status_block_data) /
956 sizeof(u32);
957 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
958 for (i = 0; i < data_size; i++)
959 *((u32 *)&sp_sb_data + i) =
960 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
961 i * sizeof(u32));
962
963 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
964 sp_sb_data.igu_sb_id,
965 sp_sb_data.igu_seg_id,
966 sp_sb_data.p_func.pf_id,
967 sp_sb_data.p_func.vnic_id,
968 sp_sb_data.p_func.vf_id,
969 sp_sb_data.p_func.vf_valid,
970 sp_sb_data.state);
971 }
523224a3 972
ec6ba945 973 for_each_eth_queue(bp, i) {
a2fbb9ea 974 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 975 int loop;
f2e0899f 976 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 977 struct hc_status_block_data_e1x sb_data_e1x;
978 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 979 CHIP_IS_E1x(bp) ?
980 sb_data_e1x.common.state_machine :
981 sb_data_e2.common.state_machine;
523224a3 982 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 983 CHIP_IS_E1x(bp) ?
984 sb_data_e1x.index_data :
985 sb_data_e2.index_data;
6383c0b3 986 u8 data_size, cos;
523224a3 987 u32 *sb_data_p;
6383c0b3 988 struct bnx2x_fp_txdata txdata;
523224a3 989
e2611998
YM		 990 if (!bp->fp)
991 break;
992
993 if (!fp->rx_cons_sb)
994 continue;
995
523224a3 996 /* Rx */
51c1a580 997 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 998 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 999 fp->rx_comp_prod,
66e855f3 1000 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
51c1a580 1001 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
8440d2b6 1002 fp->rx_sge_prod, fp->last_max_sge,
523224a3 1003 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 1004
523224a3 1005 /* Tx */
6383c0b3
AE		 1006 for_each_cos_in_tx_queue(fp, cos)
1007 {
e2611998
YM		 1008 if (!fp->txdata_ptr)
1009 break;
1010
65565884 1011 txdata = *fp->txdata_ptr[cos];
e2611998
YM		 1012
1013 if (!txdata.tx_cons_sb)
1014 continue;
1015
51c1a580 1016 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
6383c0b3
AE		 1017 i, txdata.tx_pkt_prod,
1018 txdata.tx_pkt_cons, txdata.tx_bd_prod,
1019 txdata.tx_bd_cons,
1020 le16_to_cpu(*txdata.tx_cons_sb));
1021 }
523224a3 1022
619c5cb6
VZ		 1023 loop = CHIP_IS_E1x(bp) ?
1024 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 1025
1026 /* host sb data */
1027
ec6ba945
VZ		 1028 if (IS_FCOE_FP(fp))
1029 continue;
55c11941 1030
523224a3
DK		 1031 BNX2X_ERR(" run indexes (");
1032 for (j = 0; j < HC_SB_MAX_SM; j++)
1033 pr_cont("0x%x%s",
1034 fp->sb_running_index[j],
1035 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1036
1037 BNX2X_ERR(" indexes (");
1038 for (j = 0; j < loop; j++)
1039 pr_cont("0x%x%s",
1040 fp->sb_index_values[j],
1041 (j == loop - 1) ? ")" : " ");
0155a27c
YM		 1042
1043 /* VF cannot access FW refelection for status block */
1044 if (IS_VF(bp))
1045 continue;
1046
523224a3 1047 /* fw sb data */
619c5cb6
VZ		 1048 data_size = CHIP_IS_E1x(bp) ?
1049 sizeof(struct hc_status_block_data_e1x) :
1050 sizeof(struct hc_status_block_data_e2);
523224a3 1051 data_size /= sizeof(u32);
619c5cb6
VZ		 1052 sb_data_p = CHIP_IS_E1x(bp) ?
1053 (u32 *)&sb_data_e1x :
1054 (u32 *)&sb_data_e2;
523224a3
DK		 1055 /* copy sb data in here */
1056 for (j = 0; j < data_size; j++)
1057 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1058 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1059 j * sizeof(u32));
1060
619c5cb6 1061 if (!CHIP_IS_E1x(bp)) {
51c1a580 1062 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1063 sb_data_e2.common.p_func.pf_id,
1064 sb_data_e2.common.p_func.vf_id,
1065 sb_data_e2.common.p_func.vf_valid,
1066 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 1067 sb_data_e2.common.same_igu_sb_1b,
1068 sb_data_e2.common.state);
f2e0899f 1069 } else {
51c1a580 1070 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1071 sb_data_e1x.common.p_func.pf_id,
1072 sb_data_e1x.common.p_func.vf_id,
1073 sb_data_e1x.common.p_func.vf_valid,
1074 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 1075 sb_data_e1x.common.same_igu_sb_1b,
1076 sb_data_e1x.common.state);
f2e0899f 1077 }
523224a3
DK		 1078
1079 /* SB_SMs data */
1080 for (j = 0; j < HC_SB_MAX_SM; j++) {
51c1a580
MS		 1081 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1082 j, hc_sm_p[j].__flags,
1083 hc_sm_p[j].igu_sb_id,
1084 hc_sm_p[j].igu_seg_id,
1085 hc_sm_p[j].time_to_expire,
1086 hc_sm_p[j].timer_value);
523224a3
DK		 1087 }
1088
16a5fd92 1089 /* Indices data */
523224a3 1090 for (j = 0; j < loop; j++) {
51c1a580 1091 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
523224a3
DK		 1092 hc_index_p[j].flags,
1093 hc_index_p[j].timeout);
1094 }
8440d2b6 1095 }
a2fbb9ea 1096
523224a3 1097#ifdef BNX2X_STOP_ON_ERROR
0155a27c
YM		 1098 if (IS_PF(bp)) {
1099 /* event queue */
1100 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1101 for (i = 0; i < NUM_EQ_DESC; i++) {
1102 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1103
1104 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1105 i, bp->eq_ring[i].message.opcode,
1106 bp->eq_ring[i].message.error);
1107 BNX2X_ERR("data: %x %x %x\n",
1108 data[0], data[1], data[2]);
1109 }
04c46736
YM		 1110 }
1111
8440d2b6
EG		 1112 /* Rings */
1113 /* Rx */
55c11941 1114 for_each_valid_rx_queue(bp, i) {
8440d2b6 1115 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1116
e2611998
YM		 1117 if (!bp->fp)
1118 break;
1119
1120 if (!fp->rx_cons_sb)
1121 continue;
1122
a2fbb9ea
ET		 1123 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1124 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 1125 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 1126 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1127 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1128
c3eefaf6 1129 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
44151acb 1130 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
a2fbb9ea
ET		 1131 }
1132
3196a88a
EG		 1133 start = RX_SGE(fp->rx_sge_prod);
1134 end = RX_SGE(fp->last_max_sge);
8440d2b6 1135 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 1136 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1137 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1138
c3eefaf6
EG		 1139 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1140 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 1141 }
1142
a2fbb9ea
ET		 1143 start = RCQ_BD(fp->rx_comp_cons - 10);
1144 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 1145 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 1146 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1147
c3eefaf6
EG		 1148 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1149 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 1150 }
1151 }
1152
8440d2b6 1153 /* Tx */
55c11941 1154 for_each_valid_tx_queue(bp, i) {
8440d2b6 1155 struct bnx2x_fastpath *fp = &bp->fp[i];
e2611998
YM		 1156
1157 if (!bp->fp)
1158 break;
1159
6383c0b3 1160 for_each_cos_in_tx_queue(fp, cos) {
65565884 1161 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
6383c0b3 1162
e2611998
YM		 1163 if (!fp->txdata_ptr)
1164 break;
1165
1166 if (!txdata.tx_cons_sb)
1167 continue;
1168
6383c0b3
AE		 1169 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1170 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1171 for (j = start; j != end; j = TX_BD(j + 1)) {
1172 struct sw_tx_bd *sw_bd =
1173 &txdata->tx_buf_ring[j];
1174
51c1a580 1175 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
6383c0b3
AE		 1176 i, cos, j, sw_bd->skb,
1177 sw_bd->first_bd);
1178 }
8440d2b6 1179
6383c0b3
AE		 1180 start = TX_BD(txdata->tx_bd_cons - 10);
1181 end = TX_BD(txdata->tx_bd_cons + 254);
1182 for (j = start; j != end; j = TX_BD(j + 1)) {
1183 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 1184
51c1a580 1185 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
6383c0b3
AE		 1186 i, cos, j, tx_bd[0], tx_bd[1],
1187 tx_bd[2], tx_bd[3]);
1188 }
8440d2b6
EG		 1189 }
1190 }
523224a3 1191#endif
0155a27c
YM		 1192 if (IS_PF(bp)) {
1193 bnx2x_fw_dump(bp);
1194 bnx2x_mc_assert(bp);
1195 }
a2fbb9ea 1196 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1197}
1198
619c5cb6
VZ		 1199/*
1200 * FLR Support for E2
1201 *
1202 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1203 * initialization.
1204 */
16a5fd92 1205#define FLR_WAIT_USEC 10000 /* 10 milliseconds */
89db4ad8
AE		 1206#define FLR_WAIT_INTERVAL 50 /* usec */
1207#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
619c5cb6
VZ		 1208
1209struct pbf_pN_buf_regs {
1210 int pN;
1211 u32 init_crd;
1212 u32 crd;
1213 u32 crd_freed;
1214};
1215
1216struct pbf_pN_cmd_regs {
1217 int pN;
1218 u32 lines_occup;
1219 u32 lines_freed;
1220};
1221
1222static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1223 struct pbf_pN_buf_regs *regs,
1224 u32 poll_count)
1225{
1226 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1227 u32 cur_cnt = poll_count;
1228
1229 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1230 crd = crd_start = REG_RD(bp, regs->crd);
1231 init_crd = REG_RD(bp, regs->init_crd);
1232
1233 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1234 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1235 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1236
1237 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1238 (init_crd - crd_start))) {
1239 if (cur_cnt--) {
89db4ad8 1240 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1241 crd = REG_RD(bp, regs->crd);
1242 crd_freed = REG_RD(bp, regs->crd_freed);
1243 } else {
1244 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1245 regs->pN);
1246 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1247 regs->pN, crd);
1248 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1249 regs->pN, crd_freed);
1250 break;
1251 }
1252 }
1253 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
89db4ad8 1254 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1255}
1256
1257static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1258 struct pbf_pN_cmd_regs *regs,
1259 u32 poll_count)
1260{
1261 u32 occup, to_free, freed, freed_start;
1262 u32 cur_cnt = poll_count;
1263
1264 occup = to_free = REG_RD(bp, regs->lines_occup);
1265 freed = freed_start = REG_RD(bp, regs->lines_freed);
1266
1267 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1268 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1269
1270 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1271 if (cur_cnt--) {
89db4ad8 1272 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1273 occup = REG_RD(bp, regs->lines_occup);
1274 freed = REG_RD(bp, regs->lines_freed);
1275 } else {
1276 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1277 regs->pN);
1278 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1279 regs->pN, occup);
1280 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1281 regs->pN, freed);
1282 break;
1283 }
1284 }
1285 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
89db4ad8 1286 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1287}
1288
1191cb83
ED		 1289static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1290 u32 expected, u32 poll_count)
619c5cb6
VZ		 1291{
1292 u32 cur_cnt = poll_count;
1293 u32 val;
1294
1295 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
89db4ad8 1296 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1297
1298 return val;
1299}
1300
d16132ce
AE		 1301int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1302 char *msg, u32 poll_cnt)
619c5cb6
VZ		 1303{
1304 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1305 if (val != 0) {
1306 BNX2X_ERR("%s usage count=%d\n", msg, val);
1307 return 1;
1308 }
1309 return 0;
1310}
1311
d16132ce
AE		 1312/* Common routines with VF FLR cleanup */
1313u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
619c5cb6
VZ		 1314{
1315 /* adjust polling timeout */
1316 if (CHIP_REV_IS_EMUL(bp))
1317 return FLR_POLL_CNT * 2000;
1318
1319 if (CHIP_REV_IS_FPGA(bp))
1320 return FLR_POLL_CNT * 120;
1321
1322 return FLR_POLL_CNT;
1323}
1324
d16132ce 1325void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
619c5cb6
VZ		 1326{
1327 struct pbf_pN_cmd_regs cmd_regs[] = {
1328 {0, (CHIP_IS_E3B0(bp)) ?
1329 PBF_REG_TQ_OCCUPANCY_Q0 :
1330 PBF_REG_P0_TQ_OCCUPANCY,
1331 (CHIP_IS_E3B0(bp)) ?
1332 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1333 PBF_REG_P0_TQ_LINES_FREED_CNT},
1334 {1, (CHIP_IS_E3B0(bp)) ?
1335 PBF_REG_TQ_OCCUPANCY_Q1 :
1336 PBF_REG_P1_TQ_OCCUPANCY,
1337 (CHIP_IS_E3B0(bp)) ?
1338 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1339 PBF_REG_P1_TQ_LINES_FREED_CNT},
1340 {4, (CHIP_IS_E3B0(bp)) ?
1341 PBF_REG_TQ_OCCUPANCY_LB_Q :
1342 PBF_REG_P4_TQ_OCCUPANCY,
1343 (CHIP_IS_E3B0(bp)) ?
1344 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1345 PBF_REG_P4_TQ_LINES_FREED_CNT}
1346 };
1347
1348 struct pbf_pN_buf_regs buf_regs[] = {
1349 {0, (CHIP_IS_E3B0(bp)) ?
1350 PBF_REG_INIT_CRD_Q0 :
1351 PBF_REG_P0_INIT_CRD ,
1352 (CHIP_IS_E3B0(bp)) ?
1353 PBF_REG_CREDIT_Q0 :
1354 PBF_REG_P0_CREDIT,
1355 (CHIP_IS_E3B0(bp)) ?
1356 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1357 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1358 {1, (CHIP_IS_E3B0(bp)) ?
1359 PBF_REG_INIT_CRD_Q1 :
1360 PBF_REG_P1_INIT_CRD,
1361 (CHIP_IS_E3B0(bp)) ?
1362 PBF_REG_CREDIT_Q1 :
1363 PBF_REG_P1_CREDIT,
1364 (CHIP_IS_E3B0(bp)) ?
1365 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1366 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1367 {4, (CHIP_IS_E3B0(bp)) ?
1368 PBF_REG_INIT_CRD_LB_Q :
1369 PBF_REG_P4_INIT_CRD,
1370 (CHIP_IS_E3B0(bp)) ?
1371 PBF_REG_CREDIT_LB_Q :
1372 PBF_REG_P4_CREDIT,
1373 (CHIP_IS_E3B0(bp)) ?
1374 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1375 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1376 };
1377
1378 int i;
1379
1380 /* Verify the command queues are flushed P0, P1, P4 */
1381 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1382 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1383
619c5cb6
VZ		 1384 /* Verify the transmission buffers are flushed P0, P1, P4 */
1385 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1386 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1387}
1388
1389#define OP_GEN_PARAM(param) \
1390 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1391
1392#define OP_GEN_TYPE(type) \
1393 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1394
1395#define OP_GEN_AGG_VECT(index) \
1396 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1397
d16132ce 1398int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
619c5cb6 1399{
86564c3f 1400 u32 op_gen_command = 0;
619c5cb6
VZ		 1401 u32 comp_addr = BAR_CSTRORM_INTMEM +
1402 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1403 int ret = 0;
1404
1405 if (REG_RD(bp, comp_addr)) {
89db4ad8 1406 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
619c5cb6
VZ		 1407 return 1;
1408 }
1409
86564c3f
YM		 1410 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1411 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1412 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1413 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
619c5cb6 1414
89db4ad8 1415 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
86564c3f 1416 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
619c5cb6
VZ		 1417
1418 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1419 BNX2X_ERR("FW final cleanup did not succeed\n");
51c1a580
MS		 1420 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1421 (REG_RD(bp, comp_addr)));
d16132ce
AE		 1422 bnx2x_panic();
1423 return 1;
619c5cb6 1424 }
16a5fd92 1425 /* Zero completion for next FLR */
619c5cb6
VZ		 1426 REG_WR(bp, comp_addr, 0);
1427
1428 return ret;
1429}
1430
b56e9670 1431u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
619c5cb6 1432{
619c5cb6
VZ		 1433 u16 status;
1434
2a80eebc 1435 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
619c5cb6
VZ		 1436 return status & PCI_EXP_DEVSTA_TRPND;
1437}
1438
1439/* PF FLR specific routines
1440*/
1441static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1442{
619c5cb6
VZ		 1443 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1444 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1445 CFC_REG_NUM_LCIDS_INSIDE_PF,
1446 "CFC PF usage counter timed out",
1447 poll_cnt))
1448 return 1;
1449
619c5cb6
VZ		 1450 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1451 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1452 DORQ_REG_PF_USAGE_CNT,
1453 "DQ PF usage counter timed out",
1454 poll_cnt))
1455 return 1;
1456
1457 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1458 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1459 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1460 "QM PF usage counter timed out",
1461 poll_cnt))
1462 return 1;
1463
1464 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1465 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1466 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1467 "Timers VNIC usage counter timed out",
1468 poll_cnt))
1469 return 1;
1470 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1471 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1472 "Timers NUM_SCANS usage counter timed out",
1473 poll_cnt))
1474 return 1;
1475
1476 /* Wait DMAE PF usage counter to zero */
1477 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1478 dmae_reg_go_c[INIT_DMAE_C(bp)],
6bf07b8e 1479 "DMAE command register timed out",
619c5cb6
VZ		 1480 poll_cnt))
1481 return 1;
1482
1483 return 0;
1484}
1485
1486static void bnx2x_hw_enable_status(struct bnx2x *bp)
1487{
1488 u32 val;
1489
1490 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1491 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1492
1493 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1494 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1495
1496 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1497 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1498
1499 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1500 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1501
1502 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1503 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1504
1505 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1506 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1507
1508 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1509 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1510
1511 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1512 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1513 val);
1514}
1515
1516static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1517{
1518 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1519
1520 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1521
1522 /* Re-enable PF target read access */
1523 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1524
1525 /* Poll HW usage counters */
89db4ad8 1526 DP(BNX2X_MSG_SP, "Polling usage counters\n");
619c5cb6
VZ		 1527 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1528 return -EBUSY;
1529
1530 /* Zero the igu 'trailing edge' and 'leading edge' */
1531
1532 /* Send the FW cleanup command */
1533 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1534 return -EBUSY;
1535
1536 /* ATC cleanup */
1537
1538 /* Verify TX hw is flushed */
1539 bnx2x_tx_hw_flushed(bp, poll_cnt);
1540
1541 /* Wait 100ms (not adjusted according to platform) */
1542 msleep(100);
1543
1544 /* Verify no pending pci transactions */
1545 if (bnx2x_is_pcie_pending(bp->pdev))
1546 BNX2X_ERR("PCIE Transactions still pending\n");
1547
1548 /* Debug */
1549 bnx2x_hw_enable_status(bp);
1550
1551 /*
1552 * Master enable - Due to WB DMAE writes performed before this
1553 * register is re-initialized as part of the regular function init
1554 */
1555 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1556
1557 return 0;
1558}
1559
f2e0899f 1560static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1561{
34f80b04 1562 int port = BP_PORT(bp);
a2fbb9ea
ET		 1563 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1564 u32 val = REG_RD(bp, addr);
69c326b3
DK		 1565 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1566 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1567 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
a2fbb9ea
ET		 1568
1569 if (msix) {
8badd27a
EG		 1570 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1571 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1572 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1573 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
69c326b3
DK		 1574 if (single_msix)
1575 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
8badd27a
EG		 1576 } else if (msi) {
1577 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1578 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1579 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1580 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1581 } else {
1582 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1583 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1584 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1585 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1586
a0fd065c 1587 if (!CHIP_IS_E1(bp)) {
51c1a580
MS		 1588 DP(NETIF_MSG_IFUP,
1589 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
615f8fd9 1590
a0fd065c 1591 REG_WR(bp, addr, val);
615f8fd9 1592
a0fd065c
DK		 1593 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1594 }
a2fbb9ea
ET		 1595 }
1596
a0fd065c
DK		 1597 if (CHIP_IS_E1(bp))
1598 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1599
51c1a580
MS		 1600 DP(NETIF_MSG_IFUP,
1601 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1602 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1603
1604 REG_WR(bp, addr, val);
37dbbf32
EG		 1605 /*
1606 * Ensure that HC_CONFIG is written before leading/trailing edge config
1607 */
1608 mmiowb();
1609 barrier();
34f80b04 1610
f2e0899f 1611 if (!CHIP_IS_E1(bp)) {
34f80b04 1612 /* init leading/trailing edge */
fb3bff17 1613 if (IS_MF(bp)) {
3395a033 1614 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1615 if (bp->port.pmf)
4acac6a5
EG		 1616 /* enable nig and gpio3 attention */
1617 val |= 0x1100;
34f80b04
EG		 1618 } else
1619 val = 0xffff;
1620
1621 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1622 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1623 }
37dbbf32
EG		 1624
1625 /* Make sure that interrupts are indeed enabled from here on */
1626 mmiowb();
a2fbb9ea
ET		 1627}
1628
f2e0899f
DK		 1629static void bnx2x_igu_int_enable(struct bnx2x *bp)
1630{
1631 u32 val;
30a5de77
DK		 1632 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1633 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1634 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
f2e0899f
DK		 1635
1636 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1637
1638 if (msix) {
1639 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1640 IGU_PF_CONF_SINGLE_ISR_EN);
ebe61d80 1641 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f 1642 IGU_PF_CONF_ATTN_BIT_EN);
30a5de77
DK		 1643
1644 if (single_msix)
1645 val |= IGU_PF_CONF_SINGLE_ISR_EN;
f2e0899f
DK		 1646 } else if (msi) {
1647 val &= ~IGU_PF_CONF_INT_LINE_EN;
ebe61d80 1648 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f
DK		 1649 IGU_PF_CONF_ATTN_BIT_EN |
1650 IGU_PF_CONF_SINGLE_ISR_EN);
1651 } else {
1652 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
ebe61d80 1653 val |= (IGU_PF_CONF_INT_LINE_EN |
f2e0899f
DK		 1654 IGU_PF_CONF_ATTN_BIT_EN |
1655 IGU_PF_CONF_SINGLE_ISR_EN);
1656 }
1657
ebe61d80
YM		 1658 /* Clean previous status - need to configure igu prior to ack*/
1659 if ((!msix) || single_msix) {
1660 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1661 bnx2x_ack_int(bp);
1662 }
1663
1664 val |= IGU_PF_CONF_FUNC_EN;
1665
51c1a580 1666 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
f2e0899f
DK		 1667 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1668
1669 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1670
79a8557a
YM		 1671 if (val & IGU_PF_CONF_INT_LINE_EN)
1672 pci_intx(bp->pdev, true);
1673
f2e0899f
DK		 1674 barrier();
1675
1676 /* init leading/trailing edge */
1677 if (IS_MF(bp)) {
3395a033 1678 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1679 if (bp->port.pmf)
1680 /* enable nig and gpio3 attention */
1681 val |= 0x1100;
1682 } else
1683 val = 0xffff;
1684
1685 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1686 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1687
1688 /* Make sure that interrupts are indeed enabled from here on */
1689 mmiowb();
1690}
1691
1692void bnx2x_int_enable(struct bnx2x *bp)
1693{
1694 if (bp->common.int_block == INT_BLOCK_HC)
1695 bnx2x_hc_int_enable(bp);
1696 else
1697 bnx2x_igu_int_enable(bp);
1698}
1699
9f6c9258 1700void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1701{
a2fbb9ea 1702 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1703 int i, offset;
a2fbb9ea 1704
f8ef6e44
YG		 1705 if (disable_hw)
1706 /* prevent the HW from sending interrupts */
1707 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1708
1709 /* make sure all ISRs are done */
1710 if (msix) {
8badd27a
EG		 1711 synchronize_irq(bp->msix_table[0].vector);
1712 offset = 1;
55c11941
MS		 1713 if (CNIC_SUPPORT(bp))
1714 offset++;
ec6ba945 1715 for_each_eth_queue(bp, i)
754a2f52 1716 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1717 } else
1718 synchronize_irq(bp->pdev->irq);
1719
1720 /* make sure sp_task is not running */
1cf167f2 1721 cancel_delayed_work(&bp->sp_task);
3deb8167 1722 cancel_delayed_work(&bp->period_task);
1cf167f2 1723 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1724}
1725
34f80b04 1726/* fast path */
a2fbb9ea
ET		 1727
1728/*
34f80b04 1729 * General service functions
a2fbb9ea
ET		 1730 */
1731
72fd0718
VZ		 1732/* Return true if succeeded to acquire the lock */
1733static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1734{
1735 u32 lock_status;
1736 u32 resource_bit = (1 << resource);
1737 int func = BP_FUNC(bp);
1738 u32 hw_lock_control_reg;
1739
51c1a580
MS		 1740 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1741 "Trying to take a lock on resource %d\n", resource);
72fd0718
VZ		 1742
1743 /* Validating that the resource is within range */
1744 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1745 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
72fd0718
VZ		 1746 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1747 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1748 return false;
72fd0718
VZ		 1749 }
1750
1751 if (func <= 5)
1752 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1753 else
1754 hw_lock_control_reg =
1755 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1756
1757 /* Try to acquire the lock */
1758 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1759 lock_status = REG_RD(bp, hw_lock_control_reg);
1760 if (lock_status & resource_bit)
1761 return true;
1762
51c1a580
MS		 1763 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1764 "Failed to get a lock on resource %d\n", resource);
72fd0718
VZ		 1765 return false;
1766}
1767
c9ee9206
VZ		 1768/**
1769 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1770 *
1771 * @bp: driver handle
1772 *
1773 * Returns the recovery leader resource id according to the engine this function
1774 * belongs to. Currently only only 2 engines is supported.
1775 */
1191cb83 1776static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
c9ee9206
VZ		 1777{
1778 if (BP_PATH(bp))
1779 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1780 else
1781 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1782}
1783
1784/**
2de67439 1785 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
c9ee9206
VZ		 1786 *
1787 * @bp: driver handle
1788 *
2de67439 1789 * Tries to acquire a leader lock for current engine.
c9ee9206 1790 */
1191cb83 1791static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
c9ee9206
VZ		 1792{
1793 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1794}
1795
619c5cb6 1796static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
55c11941 1797
fd1fc79d
AE		 1798/* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1799static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1800{
1801 /* Set the interrupt occurred bit for the sp-task to recognize it
1802 * must ack the interrupt and transition according to the IGU
1803 * state machine.
1804 */
1805 atomic_set(&bp->interrupt_occurred, 1);
1806
1807 /* The sp_task must execute only after this bit
1808 * is set, otherwise we will get out of sync and miss all
1809 * further interrupts. Hence, the barrier.
1810 */
1811 smp_wmb();
1812
1813 /* schedule sp_task to workqueue */
1814 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1815}
3196a88a 1816
619c5cb6 1817void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1818{
1819 struct bnx2x *bp = fp->bp;
1820 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1821 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6 1822 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
15192a8c 1823 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a2fbb9ea 1824
34f80b04 1825 DP(BNX2X_MSG_SP,
a2fbb9ea 1826 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1827 fp->index, cid, command, bp->state,
34f80b04 1828 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1829
fd1fc79d
AE		 1830 /* If cid is within VF range, replace the slowpath object with the
1831 * one corresponding to this VF
1832 */
1833 if (cid >= BNX2X_FIRST_VF_CID &&
1834 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1835 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1836
619c5cb6
VZ		 1837 switch (command) {
1838 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1839 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1840 drv_cmd = BNX2X_Q_CMD_UPDATE;
1841 break;
d6cae238 1842
619c5cb6 1843 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1844 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1845 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1846 break;
1847
6383c0b3 1848 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
51c1a580 1849 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
6383c0b3
AE		 1850 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1851 break;
1852
619c5cb6 1853 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1854 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1855 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1856 break;
1857
619c5cb6 1858 case (RAMROD_CMD_ID_ETH_TERMINATE):
6bf07b8e 1859 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
619c5cb6 1860 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1861 break;
1862
619c5cb6 1863 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1864 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1865 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1866 break;
619c5cb6 1867
14a94ebd
MK		 1868 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1869 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1870 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1871 break;
1872
619c5cb6
VZ		 1873 default:
1874 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1875 command, fp->index);
1876 return;
523224a3 1877 }
3196a88a 1878
619c5cb6
VZ		 1879 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1880 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1881 /* q_obj->complete_cmd() failure means that this was
1882 * an unexpected completion.
1883 *
1884 * In this case we don't want to increase the bp->spq_left
1885 * because apparently we haven't sent this command the first
1886 * place.
1887 */
1888#ifdef BNX2X_STOP_ON_ERROR
1889 bnx2x_panic();
1890#else
1891 return;
1892#endif
1893
4e857c58 1894 smp_mb__before_atomic();
6e30dd4e 1895 atomic_inc(&bp->cq_spq_left);
619c5cb6 1896 /* push the change in bp->spq_left and towards the memory */
4e857c58 1897 smp_mb__after_atomic();
49d66772 1898
d6cae238
VZ		 1899 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1900
a3348722
BW		 1901 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1902 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1903 /* if Q update ramrod is completed for last Q in AFEX vif set
1904 * flow, then ACK MCP at the end
1905 *
1906 * mark pending ACK to MCP bit.
1907 * prevent case that both bits are cleared.
1908 * At the end of load/unload driver checks that
2de67439 1909 * sp_state is cleared, and this order prevents
a3348722
BW		 1910 * races
1911 */
4e857c58 1912 smp_mb__before_atomic();
a3348722
BW		 1913 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1914 wmb();
1915 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4e857c58 1916 smp_mb__after_atomic();
a3348722 1917
fd1fc79d
AE		 1918 /* schedule the sp task as mcp ack is required */
1919 bnx2x_schedule_sp_task(bp);
a3348722
BW		 1920 }
1921
523224a3 1922 return;
a2fbb9ea
ET		 1923}
1924
9f6c9258 1925irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1926{
555f6c78 1927 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1928 u16 status = bnx2x_ack_int(bp);
34f80b04 1929 u16 mask;
ca00392c 1930 int i;
6383c0b3 1931 u8 cos;
a2fbb9ea 1932
34f80b04 1933 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1934 if (unlikely(status == 0)) {
1935 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1936 return IRQ_NONE;
1937 }
f5372251 1938 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1939
3196a88a
EG		 1940#ifdef BNX2X_STOP_ON_ERROR
1941 if (unlikely(bp->panic))
1942 return IRQ_HANDLED;
1943#endif
1944
ec6ba945 1945 for_each_eth_queue(bp, i) {
ca00392c 1946 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1947
55c11941 1948 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
ca00392c 1949 if (status & mask) {
619c5cb6 1950 /* Handle Rx or Tx according to SB id */
6383c0b3 1951 for_each_cos_in_tx_queue(fp, cos)
65565884 1952 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
523224a3 1953 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1954 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1955 status &= ~mask;
1956 }
a2fbb9ea
ET		 1957 }
1958
55c11941
MS		 1959 if (CNIC_SUPPORT(bp)) {
1960 mask = 0x2;
1961 if (status & (mask | 0x1)) {
1962 struct cnic_ops *c_ops = NULL;
993ac7b5 1963
ad9b4359
MC		 1964 rcu_read_lock();
1965 c_ops = rcu_dereference(bp->cnic_ops);
1966 if (c_ops && (bp->cnic_eth_dev.drv_state &
1967 CNIC_DRV_STATE_HANDLES_IRQ))
1968 c_ops->cnic_handler(bp->cnic_data, NULL);
1969 rcu_read_unlock();
993ac7b5 1970
55c11941
MS		 1971 status &= ~mask;
1972 }
993ac7b5 1973 }
a2fbb9ea 1974
34f80b04 1975 if (unlikely(status & 0x1)) {
fd1fc79d
AE		 1976
1977 /* schedule sp task to perform default status block work, ack
1978 * attentions and enable interrupts.
1979 */
1980 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 1981
1982 status &= ~0x1;
1983 if (!status)
1984 return IRQ_HANDLED;
1985 }
1986
cdaa7cb8
VZ		 1987 if (unlikely(status))
1988 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1989 status);
a2fbb9ea 1990
c18487ee 1991 return IRQ_HANDLED;
a2fbb9ea
ET		 1992}
1993
c18487ee
YR		 1994/* Link */
1995
1996/*
1997 * General service functions
1998 */
a2fbb9ea 1999
9f6c9258 2000int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 2001{
2002 u32 lock_status;
2003 u32 resource_bit = (1 << resource);
4a37fb66
YG		 2004 int func = BP_FUNC(bp);
2005 u32 hw_lock_control_reg;
c18487ee 2006 int cnt;
a2fbb9ea 2007
c18487ee
YR		 2008 /* Validating that the resource is within range */
2009 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 2010 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 2011 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2012 return -EINVAL;
2013 }
a2fbb9ea 2014
4a37fb66
YG		 2015 if (func <= 5) {
2016 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2017 } else {
2018 hw_lock_control_reg =
2019 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2020 }
2021
c18487ee 2022 /* Validating that the resource is not already taken */
4a37fb66 2023 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2024 if (lock_status & resource_bit) {
51c1a580 2025 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
c18487ee
YR		 2026 lock_status, resource_bit);
2027 return -EEXIST;
2028 }
a2fbb9ea 2029
46230476
EG		 2030 /* Try for 5 second every 5ms */
2031 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 2032 /* Try to acquire the lock */
4a37fb66
YG		 2033 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2034 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 2035 if (lock_status & resource_bit)
2036 return 0;
a2fbb9ea 2037
639d65b8 2038 usleep_range(5000, 10000);
a2fbb9ea 2039 }
51c1a580 2040 BNX2X_ERR("Timeout\n");
c18487ee
YR		 2041 return -EAGAIN;
2042}
a2fbb9ea 2043
c9ee9206
VZ		 2044int bnx2x_release_leader_lock(struct bnx2x *bp)
2045{
2046 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2047}
2048
9f6c9258 2049int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 2050{
2051 u32 lock_status;
2052 u32 resource_bit = (1 << resource);
4a37fb66
YG		 2053 int func = BP_FUNC(bp);
2054 u32 hw_lock_control_reg;
a2fbb9ea 2055
c18487ee
YR		 2056 /* Validating that the resource is within range */
2057 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 2058 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 2059 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2060 return -EINVAL;
2061 }
2062
4a37fb66
YG		 2063 if (func <= 5) {
2064 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2065 } else {
2066 hw_lock_control_reg =
2067 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2068 }
2069
c18487ee 2070 /* Validating that the resource is currently taken */
4a37fb66 2071 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2072 if (!(lock_status & resource_bit)) {
6bf07b8e
YM		 2073 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2074 lock_status, resource_bit);
c18487ee 2075 return -EFAULT;
a2fbb9ea
ET		 2076 }
2077
9f6c9258
DK		 2078 REG_WR(bp, hw_lock_control_reg, resource_bit);
2079 return 0;
c18487ee 2080}
a2fbb9ea 2081
4acac6a5
EG		 2082int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2083{
2084 /* The GPIO should be swapped if swap register is set and active */
2085 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2086 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2087 int gpio_shift = gpio_num +
2088 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2089 u32 gpio_mask = (1 << gpio_shift);
2090 u32 gpio_reg;
2091 int value;
2092
2093 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2094 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2095 return -EINVAL;
2096 }
2097
2098 /* read GPIO value */
2099 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2100
2101 /* get the requested pin value */
2102 if ((gpio_reg & gpio_mask) == gpio_mask)
2103 value = 1;
2104 else
2105 value = 0;
2106
4acac6a5
EG		 2107 return value;
2108}
2109
17de50b7 2110int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 2111{
2112 /* The GPIO should be swapped if swap register is set and active */
2113 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 2114 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 2115 int gpio_shift = gpio_num +
2116 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2117 u32 gpio_mask = (1 << gpio_shift);
2118 u32 gpio_reg;
a2fbb9ea 2119
c18487ee
YR		 2120 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2121 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2122 return -EINVAL;
2123 }
a2fbb9ea 2124
4a37fb66 2125 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 2126 /* read GPIO and mask except the float bits */
2127 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 2128
c18487ee
YR		 2129 switch (mode) {
2130 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
51c1a580
MS		 2131 DP(NETIF_MSG_LINK,
2132 "Set GPIO %d (shift %d) -> output low\n",
c18487ee
YR		 2133 gpio_num, gpio_shift);
2134 /* clear FLOAT and set CLR */
2135 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2136 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2137 break;
a2fbb9ea 2138
c18487ee 2139 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
51c1a580
MS		 2140 DP(NETIF_MSG_LINK,
2141 "Set GPIO %d (shift %d) -> output high\n",
c18487ee
YR		 2142 gpio_num, gpio_shift);
2143 /* clear FLOAT and set SET */
2144 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2145 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2146 break;
a2fbb9ea 2147
17de50b7 2148 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
51c1a580
MS		 2149 DP(NETIF_MSG_LINK,
2150 "Set GPIO %d (shift %d) -> input\n",
c18487ee
YR		 2151 gpio_num, gpio_shift);
2152 /* set FLOAT */
2153 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2154 break;
a2fbb9ea 2155
c18487ee
YR		 2156 default:
2157 break;
a2fbb9ea
ET		 2158 }
2159
c18487ee 2160 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 2161 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 2162
c18487ee 2163 return 0;
a2fbb9ea
ET		 2164}
2165
0d40f0d4
YR		 2166int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2167{
2168 u32 gpio_reg = 0;
2169 int rc = 0;
2170
2171 /* Any port swapping should be handled by caller. */
2172
2173 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2174 /* read GPIO and mask except the float bits */
2175 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2176 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2177 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2178 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2179
2180 switch (mode) {
2181 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2182 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2183 /* set CLR */
2184 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2185 break;
2186
2187 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2188 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2189 /* set SET */
2190 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2191 break;
2192
2193 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2194 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2195 /* set FLOAT */
2196 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2197 break;
2198
2199 default:
2200 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2201 rc = -EINVAL;
2202 break;
2203 }
2204
2205 if (rc == 0)
2206 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2207
2208 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2209
2210 return rc;
2211}
2212
4acac6a5
EG		 2213int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2214{
2215 /* The GPIO should be swapped if swap register is set and active */
2216 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2217 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2218 int gpio_shift = gpio_num +
2219 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2220 u32 gpio_mask = (1 << gpio_shift);
2221 u32 gpio_reg;
2222
2223 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2224 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2225 return -EINVAL;
2226 }
2227
2228 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2229 /* read GPIO int */
2230 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2231
2232 switch (mode) {
2233 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
51c1a580
MS		 2234 DP(NETIF_MSG_LINK,
2235 "Clear GPIO INT %d (shift %d) -> output low\n",
2236 gpio_num, gpio_shift);
4acac6a5
EG		 2237 /* clear SET and set CLR */
2238 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2239 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2240 break;
2241
2242 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
51c1a580
MS		 2243 DP(NETIF_MSG_LINK,
2244 "Set GPIO INT %d (shift %d) -> output high\n",
2245 gpio_num, gpio_shift);
4acac6a5
EG		 2246 /* clear CLR and set SET */
2247 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2248 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2249 break;
2250
2251 default:
2252 break;
2253 }
2254
2255 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2256 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2257
2258 return 0;
2259}
2260
d6d99a3f 2261static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
a2fbb9ea 2262{
c18487ee 2263 u32 spio_reg;
a2fbb9ea 2264
d6d99a3f
YM		 2265 /* Only 2 SPIOs are configurable */
2266 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2267 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
c18487ee 2268 return -EINVAL;
a2fbb9ea
ET		 2269 }
2270
4a37fb66 2271 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2272 /* read SPIO and mask except the float bits */
d6d99a3f 2273 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
a2fbb9ea 2274
c18487ee 2275 switch (mode) {
d6d99a3f
YM		 2276 case MISC_SPIO_OUTPUT_LOW:
2277 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
c18487ee 2278 /* clear FLOAT and set CLR */
d6d99a3f
YM		 2279 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2280 spio_reg |= (spio << MISC_SPIO_CLR_POS);
c18487ee 2281 break;
a2fbb9ea 2282
d6d99a3f
YM		 2283 case MISC_SPIO_OUTPUT_HIGH:
2284 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
c18487ee 2285 /* clear FLOAT and set SET */
d6d99a3f
YM		 2286 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2287 spio_reg |= (spio << MISC_SPIO_SET_POS);
c18487ee 2288 break;
a2fbb9ea 2289
d6d99a3f
YM		 2290 case MISC_SPIO_INPUT_HI_Z:
2291 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
c18487ee 2292 /* set FLOAT */
d6d99a3f 2293 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
c18487ee 2294 break;
a2fbb9ea 2295
c18487ee
YR		 2296 default:
2297 break;
a2fbb9ea
ET		 2298 }
2299
c18487ee 2300 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2301 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2302
a2fbb9ea
ET		 2303 return 0;
2304}
2305
9f6c9258 2306void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2307{
a22f0788 2308 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2309 switch (bp->link_vars.ieee_fc &
2310 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2311 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2312 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2313 ADVERTISED_Pause);
c18487ee 2314 break;
356e2385 2315
c18487ee 2316 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2317 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2318 ADVERTISED_Pause);
c18487ee 2319 break;
356e2385 2320
c18487ee 2321 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2322 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2323 break;
356e2385 2324
c18487ee 2325 default:
a22f0788 2326 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2327 ADVERTISED_Pause);
c18487ee
YR		 2328 break;
2329 }
2330}
f1410647 2331
cd1dfce2 2332static void bnx2x_set_requested_fc(struct bnx2x *bp)
c18487ee 2333{
cd1dfce2
YM		 2334 /* Initialize link parameters structure variables
2335 * It is recommended to turn off RX FC for jumbo frames
2336 * for better performance
2337 */
2338 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2339 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2340 else
2341 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2342}
a2fbb9ea 2343
9156b30b
DK		 2344static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2345{
2346 u32 pause_enabled = 0;
2347
2348 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2349 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2350 pause_enabled = 1;
2351
2352 REG_WR(bp, BAR_USTRORM_INTMEM +
2353 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2354 pause_enabled);
2355 }
2356
2357 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2358 pause_enabled ? "enabled" : "disabled");
2359}
2360
cd1dfce2
YM		 2361int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2362{
2363 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2364 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2365
2366 if (!BP_NOMCP(bp)) {
2367 bnx2x_set_requested_fc(bp);
4a37fb66 2368 bnx2x_acquire_phy_lock(bp);
b5bf9068 2369
a22f0788 2370 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2371 struct link_params *lp = &bp->link_params;
2372 lp->loopback_mode = LOOPBACK_XGXS;
2373 /* do PHY loopback at 10G speed, if possible */
2374 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2375 if (lp->speed_cap_mask[cfx_idx] &
2376 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2377 lp->req_line_speed[cfx_idx] =
2378 SPEED_10000;
2379 else
2380 lp->req_line_speed[cfx_idx] =
2381 SPEED_1000;
2382 }
a22f0788 2383 }
b5bf9068 2384
8970b2e4
MS		 2385 if (load_mode == LOAD_LOOPBACK_EXT) {
2386 struct link_params *lp = &bp->link_params;
2387 lp->loopback_mode = LOOPBACK_EXT;
2388 }
2389
19680c48 2390 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2391
4a37fb66 2392 bnx2x_release_phy_lock(bp);
a2fbb9ea 2393
9156b30b
DK		 2394 bnx2x_init_dropless_fc(bp);
2395
3c96c68b
EG		 2396 bnx2x_calc_fc_adv(bp);
2397
cd1dfce2 2398 if (bp->link_vars.link_up) {
b5bf9068 2399 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2400 bnx2x_link_report(bp);
cd1dfce2
YM		 2401 }
2402 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2403 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2404 return rc;
2405 }
f5372251 2406 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2407 return -EINVAL;
a2fbb9ea
ET		 2408}
2409
9f6c9258 2410void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2411{
19680c48 2412 if (!BP_NOMCP(bp)) {
4a37fb66 2413 bnx2x_acquire_phy_lock(bp);
19680c48 2414 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2415 bnx2x_release_phy_lock(bp);
a2fbb9ea 2416
9156b30b
DK		 2417 bnx2x_init_dropless_fc(bp);
2418
19680c48
EG		 2419 bnx2x_calc_fc_adv(bp);
2420 } else
f5372251 2421 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2422}
a2fbb9ea 2423
c18487ee
YR		 2424static void bnx2x__link_reset(struct bnx2x *bp)
2425{
19680c48 2426 if (!BP_NOMCP(bp)) {
4a37fb66 2427 bnx2x_acquire_phy_lock(bp);
5d07d868 2428 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
4a37fb66 2429 bnx2x_release_phy_lock(bp);
19680c48 2430 } else
f5372251 2431 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2432}
a2fbb9ea 2433
5d07d868
YM		 2434void bnx2x_force_link_reset(struct bnx2x *bp)
2435{
2436 bnx2x_acquire_phy_lock(bp);
2437 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2438 bnx2x_release_phy_lock(bp);
2439}
2440
a22f0788 2441u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2442{
2145a920 2443 u8 rc = 0;
a2fbb9ea 2444
2145a920
VZ		 2445 if (!BP_NOMCP(bp)) {
2446 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2447 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2448 is_serdes);
2145a920
VZ		 2449 bnx2x_release_phy_lock(bp);
2450 } else
2451 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2452
c18487ee
YR		 2453 return rc;
2454}
a2fbb9ea 2455
2691d51d
EG		 2456/* Calculates the sum of vn_min_rates.
2457 It's needed for further normalizing of the min_rates.
2458 Returns:
2459 sum of vn_min_rates.
2460 or
2461 0 - if all the min_rates are 0.
16a5fd92 2462 In the later case fairness algorithm should be deactivated.
2691d51d
EG		 2463 If not all min_rates are zero then those that are zeroes will be set to 1.
2464 */
b475d78f
YM		 2465static void bnx2x_calc_vn_min(struct bnx2x *bp,
2466 struct cmng_init_input *input)
2691d51d
EG		 2467{
2468 int all_zero = 1;
2691d51d
EG		 2469 int vn;
2470
3395a033 2471 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2472 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2473 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2474 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2475
2476 /* Skip hidden vns */
2477 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
b475d78f 2478 vn_min_rate = 0;
2691d51d 2479 /* If min rate is zero - set it to 1 */
b475d78f 2480 else if (!vn_min_rate)
2691d51d
EG		 2481 vn_min_rate = DEF_MIN_RATE;
2482 else
2483 all_zero = 0;
2484
b475d78f 2485 input->vnic_min_rate[vn] = vn_min_rate;
2691d51d
EG		 2486 }
2487
30ae438b
DK		 2488 /* if ETS or all min rates are zeros - disable fairness */
2489 if (BNX2X_IS_ETS_ENABLED(bp)) {
b475d78f 2490 input->flags.cmng_enables &=
30ae438b
DK		 2491 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2492 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2493 } else if (all_zero) {
b475d78f 2494 input->flags.cmng_enables &=
b015e3d1 2495 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
b475d78f
YM		 2496 DP(NETIF_MSG_IFUP,
2497 "All MIN values are zeroes fairness will be disabled\n");
b015e3d1 2498 } else
b475d78f 2499 input->flags.cmng_enables |=
b015e3d1 2500 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2501}
2502
b475d78f
YM		 2503static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2504 struct cmng_init_input *input)
34f80b04 2505{
b475d78f 2506 u16 vn_max_rate;
f2e0899f 2507 u32 vn_cfg = bp->mf_config[vn];
34f80b04 2508
b475d78f 2509 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
34f80b04 2510 vn_max_rate = 0;
b475d78f 2511 else {
faa6fcbb
DK		 2512 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2513
b475d78f 2514 if (IS_MF_SI(bp)) {
faa6fcbb
DK		 2515 /* maxCfg in percents of linkspeed */
2516 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
b475d78f 2517 } else /* SD modes */
faa6fcbb
DK		 2518 /* maxCfg is absolute in 100Mb units */
2519 vn_max_rate = maxCfg * 100;
34f80b04 2520 }
f85582f8 2521
b475d78f 2522 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
34f80b04 2523
b475d78f 2524 input->vnic_max_rate[vn] = vn_max_rate;
34f80b04 2525}
f85582f8 2526
523224a3
DK		 2527static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2528{
2529 if (CHIP_REV_IS_SLOW(bp))
2530 return CMNG_FNS_NONE;
fb3bff17 2531 if (IS_MF(bp))
523224a3
DK		 2532 return CMNG_FNS_MINMAX;
2533
2534 return CMNG_FNS_NONE;
2535}
2536
2ae17f66 2537void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2538{
0793f83f 2539 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2540
2541 if (BP_NOMCP(bp))
16a5fd92 2542 return; /* what should be the default value in this case */
523224a3 2543
0793f83f
DK		 2544 /* For 2 port configuration the absolute function number formula
2545 * is:
2546 * abs_func = 2 * vn + BP_PORT + BP_PATH
2547 *
2548 * and there are 4 functions per port
2549 *
2550 * For 4 port configuration it is
2551 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2552 *
2553 * and there are 2 functions per port
2554 */
3395a033 2555 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2556 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2557
2558 if (func >= E1H_FUNC_MAX)
2559 break;
2560
f2e0899f 2561 bp->mf_config[vn] =
523224a3
DK		 2562 MF_CFG_RD(bp, func_mf_config[func].config);
2563 }
a3348722
BW		 2564 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2565 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2566 bp->flags |= MF_FUNC_DIS;
2567 } else {
2568 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2569 bp->flags &= ~MF_FUNC_DIS;
2570 }
523224a3
DK		 2571}
2572
2573static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2574{
b475d78f
YM		 2575 struct cmng_init_input input;
2576 memset(&input, 0, sizeof(struct cmng_init_input));
2577
2578 input.port_rate = bp->link_vars.line_speed;
523224a3 2579
568e2426 2580 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
523224a3
DK		 2581 int vn;
2582
523224a3
DK		 2583 /* read mf conf from shmem */
2584 if (read_cfg)
2585 bnx2x_read_mf_cfg(bp);
2586
523224a3 2587 /* vn_weight_sum and enable fairness if not 0 */
b475d78f 2588 bnx2x_calc_vn_min(bp, &input);
523224a3
DK		 2589
2590 /* calculate and set min-max rate for each vn */
c4154f25 2591 if (bp->port.pmf)
3395a033 2592 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
b475d78f 2593 bnx2x_calc_vn_max(bp, vn, &input);
523224a3
DK		 2594
2595 /* always enable rate shaping and fairness */
b475d78f 2596 input.flags.cmng_enables |=
523224a3 2597 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
b475d78f
YM		 2598
2599 bnx2x_init_cmng(&input, &bp->cmng);
523224a3
DK		 2600 return;
2601 }
2602
2603 /* rate shaping and fairness are disabled */
2604 DP(NETIF_MSG_IFUP,
2605 "rate shaping and fairness are disabled\n");
2606}
34f80b04 2607
1191cb83
ED		 2608static void storm_memset_cmng(struct bnx2x *bp,
2609 struct cmng_init *cmng,
2610 u8 port)
2611{
2612 int vn;
2613 size_t size = sizeof(struct cmng_struct_per_port);
2614
2615 u32 addr = BAR_XSTRORM_INTMEM +
2616 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2617
2618 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2619
2620 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2621 int func = func_by_vn(bp, vn);
2622
2623 addr = BAR_XSTRORM_INTMEM +
2624 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2625 size = sizeof(struct rate_shaping_vars_per_vn);
2626 __storm_memset_struct(bp, addr, size,
2627 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2628
2629 addr = BAR_XSTRORM_INTMEM +
2630 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2631 size = sizeof(struct fairness_vars_per_vn);
2632 __storm_memset_struct(bp, addr, size,
2633 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2634 }
2635}
2636
568e2426
DK		 2637/* init cmng mode in HW according to local configuration */
2638void bnx2x_set_local_cmng(struct bnx2x *bp)
2639{
2640 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2641
2642 if (cmng_fns != CMNG_FNS_NONE) {
2643 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2644 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2645 } else {
2646 /* rate shaping and fairness are disabled */
2647 DP(NETIF_MSG_IFUP,
2648 "single function mode without fairness\n");
2649 }
2650}
2651
c18487ee
YR		 2652/* This function is called upon link interrupt */
2653static void bnx2x_link_attn(struct bnx2x *bp)
2654{
bb2a0f7a
YG		 2655 /* Make sure that we are synced with the current statistics */
2656 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2657
c18487ee 2658 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2659
9156b30b 2660 bnx2x_init_dropless_fc(bp);
1c06328c 2661
9156b30b 2662 if (bp->link_vars.link_up) {
1c06328c 2663
619c5cb6 2664 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2665 struct host_port_stats *pstats;
2666
2667 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2668 /* reset old mac stats */
bb2a0f7a
YG		 2669 memset(&(pstats->mac_stx[0]), 0,
2670 sizeof(struct mac_stx));
2671 }
f34d28ea 2672 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2673 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2674 }
2675
568e2426
DK		 2676 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2677 bnx2x_set_local_cmng(bp);
9fdc3e95 2678
2ae17f66
VZ		 2679 __bnx2x_link_report(bp);
2680
9fdc3e95
DK		 2681 if (IS_MF(bp))
2682 bnx2x_link_sync_notify(bp);
c18487ee 2683}
a2fbb9ea 2684
9f6c9258 2685void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2686{
2ae17f66 2687 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2688 return;
a2fbb9ea 2689
00253a8c 2690 /* read updated dcb configuration */
ad5afc89
AE		 2691 if (IS_PF(bp)) {
2692 bnx2x_dcbx_pmf_update(bp);
2693 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2694 if (bp->link_vars.link_up)
2695 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2696 else
2697 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2698 /* indicate link status */
2699 bnx2x_link_report(bp);
a2fbb9ea 2700
ad5afc89
AE		 2701 } else { /* VF */
2702 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2703 SUPPORTED_10baseT_Full |
2704 SUPPORTED_100baseT_Half |
2705 SUPPORTED_100baseT_Full |
2706 SUPPORTED_1000baseT_Full |
2707 SUPPORTED_2500baseX_Full |
2708 SUPPORTED_10000baseT_Full |
2709 SUPPORTED_TP |
2710 SUPPORTED_FIBRE |
2711 SUPPORTED_Autoneg |
2712 SUPPORTED_Pause |
2713 SUPPORTED_Asym_Pause);
2714 bp->port.advertising[0] = bp->port.supported[0];
2715
2716 bp->link_params.bp = bp;
2717 bp->link_params.port = BP_PORT(bp);
2718 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2719 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2720 bp->link_params.req_line_speed[0] = SPEED_10000;
2721 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2722 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2723 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2724 bp->link_vars.line_speed = SPEED_10000;
2725 bp->link_vars.link_status =
2726 (LINK_STATUS_LINK_UP |
2727 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2728 bp->link_vars.link_up = 1;
2729 bp->link_vars.duplex = DUPLEX_FULL;
2730 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2731 __bnx2x_link_report(bp);
6495d15a
DK		 2732
2733 bnx2x_sample_bulletin(bp);
2734
2735 /* if bulletin board did not have an update for link status
2736 * __bnx2x_link_report will report current status
2737 * but it will NOT duplicate report in case of already reported
2738 * during sampling bulletin board.
2739 */
bb2a0f7a 2740 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
ad5afc89 2741 }
a2fbb9ea 2742}
a2fbb9ea 2743
a3348722
BW		 2744static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2745 u16 vlan_val, u8 allowed_prio)
2746{
86564c3f 2747 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2748 struct bnx2x_func_afex_update_params *f_update_params =
2749 &func_params.params.afex_update;
2750
2751 func_params.f_obj = &bp->func_obj;
2752 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2753
2754 /* no need to wait for RAMROD completion, so don't
2755 * set RAMROD_COMP_WAIT flag
2756 */
2757
2758 f_update_params->vif_id = vifid;
2759 f_update_params->afex_default_vlan = vlan_val;
2760 f_update_params->allowed_priorities = allowed_prio;
2761
2762 /* if ramrod can not be sent, response to MCP immediately */
2763 if (bnx2x_func_state_change(bp, &func_params) < 0)
2764 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2765
2766 return 0;
2767}
2768
2769static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2770 u16 vif_index, u8 func_bit_map)
2771{
86564c3f 2772 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2773 struct bnx2x_func_afex_viflists_params *update_params =
2774 &func_params.params.afex_viflists;
2775 int rc;
2776 u32 drv_msg_code;
2777
2778 /* validate only LIST_SET and LIST_GET are received from switch */
2779 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2780 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2781 cmd_type);
2782
2783 func_params.f_obj = &bp->func_obj;
2784 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2785
2786 /* set parameters according to cmd_type */
2787 update_params->afex_vif_list_command = cmd_type;
86564c3f 2788 update_params->vif_list_index = vif_index;
a3348722
BW		 2789 update_params->func_bit_map =
2790 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2791 update_params->func_to_clear = 0;
2792 drv_msg_code =
2793 (cmd_type == VIF_LIST_RULE_GET) ?
2794 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2795 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2796
2797 /* if ramrod can not be sent, respond to MCP immediately for
2798 * SET and GET requests (other are not triggered from MCP)
2799 */
2800 rc = bnx2x_func_state_change(bp, &func_params);
2801 if (rc < 0)
2802 bnx2x_fw_command(bp, drv_msg_code, 0);
2803
2804 return 0;
2805}
2806
2807static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2808{
2809 struct afex_stats afex_stats;
2810 u32 func = BP_ABS_FUNC(bp);
2811 u32 mf_config;
2812 u16 vlan_val;
2813 u32 vlan_prio;
2814 u16 vif_id;
2815 u8 allowed_prio;
2816 u8 vlan_mode;
2817 u32 addr_to_write, vifid, addrs, stats_type, i;
2818
2819 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2820 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2821 DP(BNX2X_MSG_MCP,
2822 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2823 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2824 }
2825
2826 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2827 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2828 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2829 DP(BNX2X_MSG_MCP,
2830 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2831 vifid, addrs);
2832 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2833 addrs);
2834 }
2835
2836 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2837 addr_to_write = SHMEM2_RD(bp,
2838 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2839 stats_type = SHMEM2_RD(bp,
2840 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2841
2842 DP(BNX2X_MSG_MCP,
2843 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2844 addr_to_write);
2845
2846 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2847
2848 /* write response to scratchpad, for MCP */
2849 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2850 REG_WR(bp, addr_to_write + i*sizeof(u32),
2851 *(((u32 *)(&afex_stats))+i));
2852
2853 /* send ack message to MCP */
2854 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2855 }
2856
2857 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2858 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2859 bp->mf_config[BP_VN(bp)] = mf_config;
2860 DP(BNX2X_MSG_MCP,
2861 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2862 mf_config);
2863
2864 /* if VIF_SET is "enabled" */
2865 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2866 /* set rate limit directly to internal RAM */
2867 struct cmng_init_input cmng_input;
2868 struct rate_shaping_vars_per_vn m_rs_vn;
2869 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2870 u32 addr = BAR_XSTRORM_INTMEM +
2871 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2872
2873 bp->mf_config[BP_VN(bp)] = mf_config;
2874
2875 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2876 m_rs_vn.vn_counter.rate =
2877 cmng_input.vnic_max_rate[BP_VN(bp)];
2878 m_rs_vn.vn_counter.quota =
2879 (m_rs_vn.vn_counter.rate *
2880 RS_PERIODIC_TIMEOUT_USEC) / 8;
2881
2882 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2883
2884 /* read relevant values from mf_cfg struct in shmem */
2885 vif_id =
2886 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2887 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2888 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2889 vlan_val =
2890 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2891 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2892 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2893 vlan_prio = (mf_config &
2894 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2895 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2896 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2897 vlan_mode =
2898 (MF_CFG_RD(bp,
2899 func_mf_config[func].afex_config) &
2900 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2901 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2902 allowed_prio =
2903 (MF_CFG_RD(bp,
2904 func_mf_config[func].afex_config) &
2905 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2906 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2907
2908 /* send ramrod to FW, return in case of failure */
2909 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2910 allowed_prio))
2911 return;
2912
2913 bp->afex_def_vlan_tag = vlan_val;
2914 bp->afex_vlan_mode = vlan_mode;
2915 } else {
2916 /* notify link down because BP->flags is disabled */
2917 bnx2x_link_report(bp);
2918
2919 /* send INVALID VIF ramrod to FW */
2920 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2921
2922 /* Reset the default afex VLAN */
2923 bp->afex_def_vlan_tag = -1;
2924 }
2925 }
2926}
2927
34f80b04
EG		 2928static void bnx2x_pmf_update(struct bnx2x *bp)
2929{
2930 int port = BP_PORT(bp);
2931 u32 val;
2932
2933 bp->port.pmf = 1;
51c1a580 2934 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
34f80b04 2935
3deb8167
YR		 2936 /*
2937 * We need the mb() to ensure the ordering between the writing to
2938 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2939 */
2940 smp_mb();
2941
2942 /* queue a periodic task */
2943 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2944
ef01854e
DK		 2945 bnx2x_dcbx_pmf_update(bp);
2946
34f80b04 2947 /* enable nig attention */
3395a033 2948 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2949 if (bp->common.int_block == INT_BLOCK_HC) {
2950 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2951 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2952 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2953 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2954 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2955 }
bb2a0f7a
YG		 2956
2957 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2958}
2959
c18487ee 2960/* end of Link */
a2fbb9ea
ET		 2961
2962/* slow path */
2963
2964/*
2965 * General service functions
2966 */
2967
2691d51d 2968/* send the MCP a request, block until there is a reply */
a22f0788 2969u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2970{
f2e0899f 2971 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2972 u32 seq;
2691d51d
EG		 2973 u32 rc = 0;
2974 u32 cnt = 1;
2975 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2976
c4ff7cbf 2977 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2978 seq = ++bp->fw_seq;
f2e0899f
DK		 2979 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2980 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2981
754a2f52
DK		 2982 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2983 (command | seq), param);
2691d51d
EG		 2984
2985 do {
2986 /* let the FW do it's magic ... */
2987 msleep(delay);
2988
f2e0899f 2989 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2990
c4ff7cbf
EG		 2991 /* Give the FW up to 5 second (500*10ms) */
2992 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2993
2994 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2995 cnt*delay, rc, seq);
2996
2997 /* is this a reply to our command? */
2998 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2999 rc &= FW_MSG_CODE_MASK;
3000 else {
3001 /* FW BUG! */
3002 BNX2X_ERR("FW failed to respond!\n");
3003 bnx2x_fw_dump(bp);
3004 rc = 0;
3005 }
c4ff7cbf 3006 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 3007
3008 return rc;
3009}
3010
1191cb83
ED		 3011static void storm_memset_func_cfg(struct bnx2x *bp,
3012 struct tstorm_eth_function_common_config *tcfg,
3013 u16 abs_fid)
3014{
3015 size_t size = sizeof(struct tstorm_eth_function_common_config);
3016
3017 u32 addr = BAR_TSTRORM_INTMEM +
3018 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3019
3020 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3021}
3022
619c5cb6
VZ		 3023void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3024{
3025 if (CHIP_IS_E1x(bp)) {
3026 struct tstorm_eth_function_common_config tcfg = {0};
3027
3028 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3029 }
3030
3031 /* Enable the function in the FW */
3032 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3033 storm_memset_func_en(bp, p->func_id, 1);
3034
3035 /* spq */
3036 if (p->func_flgs & FUNC_FLG_SPQ) {
3037 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3038 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3039 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3040 }
3041}
3042
6383c0b3 3043/**
16a5fd92 3044 * bnx2x_get_common_flags - Return common flags
6383c0b3
AE		 3045 *
3046 * @bp device handle
3047 * @fp queue handle
3048 * @zero_stats TRUE if statistics zeroing is needed
3049 *
3050 * Return the flags that are common for the Tx-only and not normal connections.
3051 */
1191cb83
ED		 3052static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3053 struct bnx2x_fastpath *fp,
3054 bool zero_stats)
28912902 3055{
619c5cb6
VZ		 3056 unsigned long flags = 0;
3057
3058 /* PF driver will always initialize the Queue to an ACTIVE state */
3059 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 3060
6383c0b3 3061 /* tx only connections collect statistics (on the same index as the
91226790
DK		 3062 * parent connection). The statistics are zeroed when the parent
3063 * connection is initialized.
6383c0b3 3064 */
50f0a562
BW		 3065
3066 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3067 if (zero_stats)
3068 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3069
c14db202
YM		 3070 if (bp->flags & TX_SWITCHING)
3071 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3072
91226790 3073 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
e287a75c 3074 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
6383c0b3 3075
823e1d90
YM		 3076#ifdef BNX2X_STOP_ON_ERROR
3077 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3078#endif
3079
6383c0b3
AE		 3080 return flags;
3081}
3082
1191cb83
ED		 3083static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3084 struct bnx2x_fastpath *fp,
3085 bool leading)
6383c0b3
AE		 3086{
3087 unsigned long flags = 0;
3088
619c5cb6
VZ		 3089 /* calculate other queue flags */
3090 if (IS_MF_SD(bp))
3091 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 3092
a3348722 3093 if (IS_FCOE_FP(fp)) {
619c5cb6 3094 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
a3348722
BW		 3095 /* For FCoE - force usage of default priority (for afex) */
3096 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3097 }
523224a3 3098
f5219d8e 3099 if (!fp->disable_tpa) {
619c5cb6 3100 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e 3101 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
621b4d66
DK		 3102 if (fp->mode == TPA_MODE_GRO)
3103 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
f5219d8e 3104 }
619c5cb6 3105
619c5cb6
VZ		 3106 if (leading) {
3107 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3108 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3109 }
523224a3 3110
619c5cb6
VZ		 3111 /* Always set HW VLAN stripping */
3112 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 3113
a3348722
BW		 3114 /* configure silent vlan removal */
3115 if (IS_MF_AFEX(bp))
3116 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3117
6383c0b3 3118 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 3119}
3120
619c5cb6 3121static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 3122 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3123 u8 cos)
619c5cb6
VZ		 3124{
3125 gen_init->stat_id = bnx2x_stats_id(fp);
3126 gen_init->spcl_id = fp->cl_id;
3127
3128 /* Always use mini-jumbo MTU for FCoE L2 ring */
3129 if (IS_FCOE_FP(fp))
3130 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3131 else
3132 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 3133
3134 gen_init->cos = cos;
619c5cb6
VZ		 3135}
3136
3137static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 3138 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 3139 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 3140{
619c5cb6 3141 u8 max_sge = 0;
523224a3
DK		 3142 u16 sge_sz = 0;
3143 u16 tpa_agg_size = 0;
3144
523224a3 3145 if (!fp->disable_tpa) {
dfacf138
DK		 3146 pause->sge_th_lo = SGE_TH_LO(bp);
3147 pause->sge_th_hi = SGE_TH_HI(bp);
3148
3149 /* validate SGE ring has enough to cross high threshold */
3150 WARN_ON(bp->dropless_fc &&
3151 pause->sge_th_hi + FW_PREFETCH_CNT >
3152 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3153
924d75ab 3154 tpa_agg_size = TPA_AGG_SIZE;
523224a3
DK		 3155 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3156 SGE_PAGE_SHIFT;
3157 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3158 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
924d75ab 3159 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
523224a3
DK		 3160 }
3161
3162 /* pause - not for e1 */
3163 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 3164 pause->bd_th_lo = BD_TH_LO(bp);
3165 pause->bd_th_hi = BD_TH_HI(bp);
3166
3167 pause->rcq_th_lo = RCQ_TH_LO(bp);
3168 pause->rcq_th_hi = RCQ_TH_HI(bp);
3169 /*
3170 * validate that rings have enough entries to cross
3171 * high thresholds
3172 */
3173 WARN_ON(bp->dropless_fc &&
3174 pause->bd_th_hi + FW_PREFETCH_CNT >
3175 bp->rx_ring_size);
3176 WARN_ON(bp->dropless_fc &&
3177 pause->rcq_th_hi + FW_PREFETCH_CNT >
3178 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 3179
523224a3
DK		 3180 pause->pri_map = 1;
3181 }
3182
3183 /* rxq setup */
523224a3
DK		 3184 rxq_init->dscr_map = fp->rx_desc_mapping;
3185 rxq_init->sge_map = fp->rx_sge_mapping;
3186 rxq_init->rcq_map = fp->rx_comp_mapping;
3187 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 3188
619c5cb6
VZ		 3189 /* This should be a maximum number of data bytes that may be
3190 * placed on the BD (not including paddings).
3191 */
e52fcb24 3192 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3cdeec22 3193 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 3194
523224a3 3195 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 3196 rxq_init->tpa_agg_sz = tpa_agg_size;
3197 rxq_init->sge_buf_sz = sge_sz;
3198 rxq_init->max_sges_pkt = max_sge;
619c5cb6 3199 rxq_init->rss_engine_id = BP_FUNC(bp);
259afa1f 3200 rxq_init->mcast_engine_id = BP_FUNC(bp);
619c5cb6
VZ		 3201
3202 /* Maximum number or simultaneous TPA aggregation for this Queue.
3203 *
2de67439 3204 * For PF Clients it should be the maximum available number.
619c5cb6
VZ		 3205 * VF driver(s) may want to define it to a smaller value.
3206 */
dfacf138 3207 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 3208
523224a3
DK		 3209 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3210 rxq_init->fw_sb_id = fp->fw_sb_id;
3211
ec6ba945
VZ		 3212 if (IS_FCOE_FP(fp))
3213 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3214 else
6383c0b3 3215 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
a3348722
BW		 3216 /* configure silent vlan removal
3217 * if multi function mode is afex, then mask default vlan
3218 */
3219 if (IS_MF_AFEX(bp)) {
3220 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3221 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3222 }
523224a3
DK		 3223}
3224
619c5cb6 3225static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 3226 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3227 u8 cos)
523224a3 3228{
65565884 3229 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
6383c0b3 3230 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 3231 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3232 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 3233
619c5cb6 3234 /*
16a5fd92 3235 * set the tss leading client id for TX classification ==
619c5cb6
VZ		 3236 * leading RSS client id
3237 */
3238 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3239
ec6ba945
VZ		 3240 if (IS_FCOE_FP(fp)) {
3241 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3242 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3243 }
523224a3
DK		 3244}
3245
8d96286a 3246static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 3247{
3248 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 3249 struct event_ring_data eq_data = { {0} };
3250 u16 flags;
3251
619c5cb6 3252 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3253 /* reset IGU PF statistics: MSIX + ATTN */
3254 /* PF */
3255 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3256 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3257 (CHIP_MODE_IS_4_PORT(bp) ?
3258 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3259 /* ATTN */
3260 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3261 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3262 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3263 (CHIP_MODE_IS_4_PORT(bp) ?
3264 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3265 }
3266
523224a3
DK		 3267 /* function setup flags */
3268 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3269
619c5cb6
VZ		 3270 /* This flag is relevant for E1x only.
3271 * E2 doesn't have a TPA configuration in a function level.
523224a3 3272 */
619c5cb6 3273 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 3274
3275 func_init.func_flgs = flags;
3276 func_init.pf_id = BP_FUNC(bp);
3277 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 3278 func_init.spq_map = bp->spq_mapping;
3279 func_init.spq_prod = bp->spq_prod_idx;
3280
3281 bnx2x_func_init(bp, &func_init);
3282
3283 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3284
3285 /*
619c5cb6
VZ		 3286 * Congestion management values depend on the link rate
3287 * There is no active link so initial link rate is set to 10 Gbps.
3288 * When the link comes up The congestion management values are
3289 * re-calculated according to the actual link rate.
3290 */
523224a3
DK		 3291 bp->link_vars.line_speed = SPEED_10000;
3292 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3293
3294 /* Only the PMF sets the HW */
3295 if (bp->port.pmf)
3296 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3297
86564c3f 3298 /* init Event Queue - PCI bus guarantees correct endianity*/
523224a3
DK		 3299 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3300 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3301 eq_data.producer = bp->eq_prod;
3302 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3303 eq_data.sb_id = DEF_SB_ID;
3304 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3305}
3306
523224a3
DK		 3307static void bnx2x_e1h_disable(struct bnx2x *bp)
3308{
3309 int port = BP_PORT(bp);
3310
619c5cb6 3311 bnx2x_tx_disable(bp);
523224a3
DK		 3312
3313 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 3314}
3315
3316static void bnx2x_e1h_enable(struct bnx2x *bp)
3317{
3318 int port = BP_PORT(bp);
3319
3320 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3321
16a5fd92 3322 /* Tx queue should be only re-enabled */
523224a3
DK		 3323 netif_tx_wake_all_queues(bp->dev);
3324
3325 /*
3326 * Should not call netif_carrier_on since it will be called if the link
3327 * is up when checking for link state
3328 */
3329}
3330
1d187b34
BW		 3331#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3332
3333static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3334{
3335 struct eth_stats_info *ether_stat =
3336 &bp->slowpath->drv_info_to_mcp.ether_stat;
3ec9f9ca
AE		 3337 struct bnx2x_vlan_mac_obj *mac_obj =
3338 &bp->sp_objs->mac_obj;
3339 int i;
1d187b34 3340
786fdf0b
DC		 3341 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3342 ETH_STAT_INFO_VERSION_LEN);
1d187b34 3343
3ec9f9ca
AE		 3344 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3345 * mac_local field in ether_stat struct. The base address is offset by 2
3346 * bytes to account for the field being 8 bytes but a mac address is
3347 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3348 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3349 * allocated by the ether_stat struct, so the macs will land in their
3350 * proper positions.
3351 */
3352 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3353 memset(ether_stat->mac_local + i, 0,
3354 sizeof(ether_stat->mac_local[0]));
3355 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3356 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3357 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3358 ETH_ALEN);
1d187b34 3359 ether_stat->mtu_size = bp->dev->mtu;
1d187b34
BW		 3360 if (bp->dev->features & NETIF_F_RXCSUM)
3361 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3362 if (bp->dev->features & NETIF_F_TSO)
3363 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3364 ether_stat->feature_flags |= bp->common.boot_mode;
3365
3366 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3367
3368 ether_stat->txq_size = bp->tx_ring_size;
3369 ether_stat->rxq_size = bp->rx_ring_size;
0c757dee 3370
fcf93a0a 3371#ifdef CONFIG_BNX2X_SRIOV
0c757dee 3372 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
fcf93a0a 3373#endif
1d187b34
BW		 3374}
3375
3376static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3377{
3378 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3379 struct fcoe_stats_info *fcoe_stat =
3380 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3381
55c11941
MS		 3382 if (!CNIC_LOADED(bp))
3383 return;
3384
3ec9f9ca 3385 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
1d187b34
BW		 3386
3387 fcoe_stat->qos_priority =
3388 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3389
3390 /* insert FCoE stats from ramrod response */
3391 if (!NO_FCOE(bp)) {
3392 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
65565884 3393 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3394 tstorm_queue_statistics;
3395
3396 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
65565884 3397 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3398 xstorm_queue_statistics;
3399
3400 struct fcoe_statistics_params *fw_fcoe_stat =
3401 &bp->fw_stats_data->fcoe;
3402
86564c3f
YM		 3403 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3404 fcoe_stat->rx_bytes_lo,
3405 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
1d187b34 3406
86564c3f
YM		 3407 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3408 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3409 fcoe_stat->rx_bytes_lo,
3410 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
1d187b34 3411
86564c3f
YM		 3412 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3413 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3414 fcoe_stat->rx_bytes_lo,
3415 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
1d187b34 3416
86564c3f
YM		 3417 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3418 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3419 fcoe_stat->rx_bytes_lo,
3420 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
1d187b34 3421
86564c3f
YM		 3422 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3423 fcoe_stat->rx_frames_lo,
3424 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
1d187b34 3425
86564c3f
YM		 3426 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3427 fcoe_stat->rx_frames_lo,
3428 fcoe_q_tstorm_stats->rcv_ucast_pkts);
1d187b34 3429
86564c3f
YM		 3430 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3431 fcoe_stat->rx_frames_lo,
3432 fcoe_q_tstorm_stats->rcv_bcast_pkts);
1d187b34 3433
86564c3f
YM		 3434 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3435 fcoe_stat->rx_frames_lo,
3436 fcoe_q_tstorm_stats->rcv_mcast_pkts);
1d187b34 3437
86564c3f
YM		 3438 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3439 fcoe_stat->tx_bytes_lo,
3440 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
1d187b34 3441
86564c3f
YM		 3442 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3443 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3444 fcoe_stat->tx_bytes_lo,
3445 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
1d187b34 3446
86564c3f
YM		 3447 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3448 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3449 fcoe_stat->tx_bytes_lo,
3450 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
1d187b34 3451
86564c3f
YM		 3452 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3453 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3454 fcoe_stat->tx_bytes_lo,
3455 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
1d187b34 3456
86564c3f
YM		 3457 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3458 fcoe_stat->tx_frames_lo,
3459 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
1d187b34 3460
86564c3f
YM		 3461 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3462 fcoe_stat->tx_frames_lo,
3463 fcoe_q_xstorm_stats->ucast_pkts_sent);
1d187b34 3464
86564c3f
YM		 3465 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3466 fcoe_stat->tx_frames_lo,
3467 fcoe_q_xstorm_stats->bcast_pkts_sent);
1d187b34 3468
86564c3f
YM		 3469 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3470 fcoe_stat->tx_frames_lo,
3471 fcoe_q_xstorm_stats->mcast_pkts_sent);
1d187b34
BW		 3472 }
3473
1d187b34
BW		 3474 /* ask L5 driver to add data to the struct */
3475 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
1d187b34
BW		 3476}
3477
3478static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3479{
3480 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3481 struct iscsi_stats_info *iscsi_stat =
3482 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3483
55c11941
MS		 3484 if (!CNIC_LOADED(bp))
3485 return;
3486
3ec9f9ca
AE		 3487 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3488 ETH_ALEN);
1d187b34
BW		 3489
3490 iscsi_stat->qos_priority =
3491 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3492
1d187b34
BW		 3493 /* ask L5 driver to add data to the struct */
3494 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
1d187b34
BW		 3495}
3496
0793f83f
DK		 3497/* called due to MCP event (on pmf):
3498 * reread new bandwidth configuration
3499 * configure FW
3500 * notify others function about the change
3501 */
1191cb83 3502static void bnx2x_config_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3503{
3504 if (bp->link_vars.link_up) {
3505 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3506 bnx2x_link_sync_notify(bp);
3507 }
3508 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3509}
3510
1191cb83 3511static void bnx2x_set_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3512{
3513 bnx2x_config_mf_bw(bp);
3514 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3515}
3516
c8c60d88
YM		 3517static void bnx2x_handle_eee_event(struct bnx2x *bp)
3518{
3519 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3520 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3521}
3522
42f8277f
YM		 3523#define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3524#define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3525
1d187b34
BW		 3526static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3527{
3528 enum drv_info_opcode op_code;
3529 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
42f8277f
YM		 3530 bool release = false;
3531 int wait;
1d187b34
BW		 3532
3533 /* if drv_info version supported by MFW doesn't match - send NACK */
3534 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3535 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3536 return;
3537 }
3538
3539 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3540 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3541
42f8277f
YM		 3542 /* Must prevent other flows from accessing drv_info_to_mcp */
3543 mutex_lock(&bp->drv_info_mutex);
3544
1d187b34
BW		 3545 memset(&bp->slowpath->drv_info_to_mcp, 0,
3546 sizeof(union drv_info_to_mcp));
3547
3548 switch (op_code) {
3549 case ETH_STATS_OPCODE:
3550 bnx2x_drv_info_ether_stat(bp);
3551 break;
3552 case FCOE_STATS_OPCODE:
3553 bnx2x_drv_info_fcoe_stat(bp);
3554 break;
3555 case ISCSI_STATS_OPCODE:
3556 bnx2x_drv_info_iscsi_stat(bp);
3557 break;
3558 default:
3559 /* if op code isn't supported - send NACK */
3560 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
42f8277f 3561 goto out;
1d187b34
BW		 3562 }
3563
3564 /* if we got drv_info attn from MFW then these fields are defined in
3565 * shmem2 for sure
3566 */
3567 SHMEM2_WR(bp, drv_info_host_addr_lo,
3568 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3569 SHMEM2_WR(bp, drv_info_host_addr_hi,
3570 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3571
3572 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
42f8277f
YM		 3573
3574 /* Since possible management wants both this and get_driver_version
3575 * need to wait until management notifies us it finished utilizing
3576 * the buffer.
3577 */
3578 if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3579 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3580 } else if (!bp->drv_info_mng_owner) {
3581 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3582
3583 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3584 u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3585
3586 /* Management is done; need to clear indication */
3587 if (indication & bit) {
3588 SHMEM2_WR(bp, mfw_drv_indication,
3589 indication & ~bit);
3590 release = true;
3591 break;
3592 }
3593
3594 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3595 }
3596 }
3597 if (!release) {
3598 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3599 bp->drv_info_mng_owner = true;
3600 }
3601
3602out:
3603 mutex_unlock(&bp->drv_info_mutex);
3604}
3605
3606static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3607{
3608 u8 vals[4];
3609 int i = 0;
3610
3611 if (bnx2x_format) {
3612 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3613 &vals[0], &vals[1], &vals[2], &vals[3]);
3614 if (i > 0)
3615 vals[0] -= '0';
3616 } else {
3617 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3618 &vals[0], &vals[1], &vals[2], &vals[3]);
3619 }
3620
3621 while (i < 4)
3622 vals[i++] = 0;
3623
3624 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3625}
3626
3627void bnx2x_update_mng_version(struct bnx2x *bp)
3628{
3629 u32 iscsiver = DRV_VER_NOT_LOADED;
3630 u32 fcoever = DRV_VER_NOT_LOADED;
3631 u32 ethver = DRV_VER_NOT_LOADED;
3632 int idx = BP_FW_MB_IDX(bp);
3633 u8 *version;
3634
3635 if (!SHMEM2_HAS(bp, func_os_drv_ver))
3636 return;
3637
3638 mutex_lock(&bp->drv_info_mutex);
3639 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3640 if (bp->drv_info_mng_owner)
3641 goto out;
3642
3643 if (bp->state != BNX2X_STATE_OPEN)
3644 goto out;
3645
3646 /* Parse ethernet driver version */
3647 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3648 if (!CNIC_LOADED(bp))
3649 goto out;
3650
3651 /* Try getting storage driver version via cnic */
3652 memset(&bp->slowpath->drv_info_to_mcp, 0,
3653 sizeof(union drv_info_to_mcp));
3654 bnx2x_drv_info_iscsi_stat(bp);
3655 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3656 iscsiver = bnx2x_update_mng_version_utility(version, false);
3657
3658 memset(&bp->slowpath->drv_info_to_mcp, 0,
3659 sizeof(union drv_info_to_mcp));
3660 bnx2x_drv_info_fcoe_stat(bp);
3661 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3662 fcoever = bnx2x_update_mng_version_utility(version, false);
3663
3664out:
3665 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3666 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3667 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3668
3669 mutex_unlock(&bp->drv_info_mutex);
3670
3671 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3672 ethver, iscsiver, fcoever);
1d187b34
BW		 3673}
3674
523224a3
DK		 3675static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3676{
3677 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3678
3679 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3680
3681 /*
3682 * This is the only place besides the function initialization
3683 * where the bp->flags can change so it is done without any
3684 * locks
3685 */
f2e0899f 3686 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
51c1a580 3687 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
523224a3
DK		 3688 bp->flags |= MF_FUNC_DIS;
3689
3690 bnx2x_e1h_disable(bp);
3691 } else {
51c1a580 3692 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
523224a3
DK		 3693 bp->flags &= ~MF_FUNC_DIS;
3694
3695 bnx2x_e1h_enable(bp);
3696 }
3697 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3698 }
3699 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 3700 bnx2x_config_mf_bw(bp);
523224a3
DK		 3701 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3702 }
3703
3704 /* Report results to MCP */
3705 if (dcc_event)
3706 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3707 else
3708 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3709}
3710
3711/* must be called under the spq lock */
1191cb83 3712static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
523224a3
DK		 3713{
3714 struct eth_spe *next_spe = bp->spq_prod_bd;
3715
3716 if (bp->spq_prod_bd == bp->spq_last_bd) {
3717 bp->spq_prod_bd = bp->spq;
3718 bp->spq_prod_idx = 0;
51c1a580 3719 DP(BNX2X_MSG_SP, "end of spq\n");
523224a3
DK		 3720 } else {
3721 bp->spq_prod_bd++;
3722 bp->spq_prod_idx++;
3723 }
3724 return next_spe;
3725}
3726
3727/* must be called under the spq lock */
1191cb83 3728static void bnx2x_sp_prod_update(struct bnx2x *bp)
28912902
MC		 3729{
3730 int func = BP_FUNC(bp);
3731
53e51e2f
VZ		 3732 /*
3733 * Make sure that BD data is updated before writing the producer:
3734 * BD data is written to the memory, the producer is read from the
3735 * memory, thus we need a full memory barrier to ensure the ordering.
3736 */
3737 mb();
28912902 3738
523224a3 3739 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3740 bp->spq_prod_idx);
28912902
MC		 3741 mmiowb();
3742}
3743
619c5cb6
VZ		 3744/**
3745 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3746 *
3747 * @cmd: command to check
3748 * @cmd_type: command type
3749 */
1191cb83 3750static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
619c5cb6
VZ		 3751{
3752 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3753 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3754 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3755 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3756 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3757 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3758 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3759 return true;
3760 else
3761 return false;
619c5cb6
VZ		 3762}
3763
619c5cb6
VZ		 3764/**
3765 * bnx2x_sp_post - place a single command on an SP ring
3766 *
3767 * @bp: driver handle
3768 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3769 * @cid: SW CID the command is related to
3770 * @data_hi: command private data address (high 32 bits)
3771 * @data_lo: command private data address (low 32 bits)
3772 * @cmd_type: command type (e.g. NONE, ETH)
3773 *
3774 * SP data is handled as if it's always an address pair, thus data fields are
3775 * not swapped to little endian in upper functions. Instead this function swaps
3776 * data as if it's two u32 fields.
3777 */
9f6c9258 3778int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3779 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3780{
28912902 3781 struct eth_spe *spe;
523224a3 3782 u16 type;
619c5cb6 3783 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3784
a2fbb9ea 3785#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 3786 if (unlikely(bp->panic)) {
3787 BNX2X_ERR("Can't post SP when there is panic\n");
a2fbb9ea 3788 return -EIO;
51c1a580 3789 }
a2fbb9ea
ET		 3790#endif
3791
34f80b04 3792 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3793
6e30dd4e
VZ		 3794 if (common) {
3795 if (!atomic_read(&bp->eq_spq_left)) {
3796 BNX2X_ERR("BUG! EQ ring full!\n");
3797 spin_unlock_bh(&bp->spq_lock);
3798 bnx2x_panic();
3799 return -EBUSY;
3800 }
3801 } else if (!atomic_read(&bp->cq_spq_left)) {
3802 BNX2X_ERR("BUG! SPQ ring full!\n");
3803 spin_unlock_bh(&bp->spq_lock);
3804 bnx2x_panic();
3805 return -EBUSY;
a2fbb9ea 3806 }
f1410647 3807
28912902
MC		 3808 spe = bnx2x_sp_get_next(bp);
3809
a2fbb9ea 3810 /* CID needs port number to be encoded int it */
28912902 3811 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3812 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3813 HW_CID(bp, cid));
523224a3 3814
14a94ebd
MK		 3815 /* In some cases, type may already contain the func-id
3816 * mainly in SRIOV related use cases, so we add it here only
3817 * if it's not already set.
3818 */
3819 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3820 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3821 SPE_HDR_CONN_TYPE;
3822 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3823 SPE_HDR_FUNCTION_ID);
3824 } else {
3825 type = cmd_type;
3826 }
a2fbb9ea 3827
523224a3
DK		 3828 spe->hdr.type = cpu_to_le16(type);
3829
3830 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3831 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3832
d6cae238
VZ		 3833 /*
3834 * It's ok if the actual decrement is issued towards the memory
3835 * somewhere between the spin_lock and spin_unlock. Thus no
16a5fd92 3836 * more explicit memory barrier is needed.
d6cae238
VZ		 3837 */
3838 if (common)
3839 atomic_dec(&bp->eq_spq_left);
3840 else
3841 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3842
51c1a580
MS		 3843 DP(BNX2X_MSG_SP,
3844 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3845 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3846 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3847 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3848 HW_CID(bp, cid), data_hi, data_lo, type,
3849 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3850
28912902 3851 bnx2x_sp_prod_update(bp);
34f80b04 3852 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3853 return 0;
3854}
3855
3856/* acquire split MCP access lock register */
4a37fb66 3857static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3858{
72fd0718 3859 u32 j, val;
34f80b04 3860 int rc = 0;
a2fbb9ea
ET		 3861
3862 might_sleep();
72fd0718 3863 for (j = 0; j < 1000; j++) {
3cdeec22
YM		 3864 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3865 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3866 if (val & MCPR_ACCESS_LOCK_LOCK)
a2fbb9ea
ET		 3867 break;
3868
639d65b8 3869 usleep_range(5000, 10000);
a2fbb9ea 3870 }
3cdeec22 3871 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
19680c48 3872 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3873 rc = -EBUSY;
3874 }
3875
3876 return rc;
3877}
3878
4a37fb66
YG		 3879/* release split MCP access lock register */
3880static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3881{
3cdeec22 3882 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
a2fbb9ea
ET		 3883}
3884
523224a3
DK		 3885#define BNX2X_DEF_SB_ATT_IDX 0x0001
3886#define BNX2X_DEF_SB_IDX 0x0002
3887
1191cb83 3888static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
a2fbb9ea 3889{
523224a3 3890 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3891 u16 rc = 0;
3892
3893 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3894 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3895 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3896 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3897 }
523224a3
DK		 3898
3899 if (bp->def_idx != def_sb->sp_sb.running_index) {
3900 bp->def_idx = def_sb->sp_sb.running_index;
3901 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3902 }
523224a3 3903
16a5fd92 3904 /* Do not reorder: indices reading should complete before handling */
523224a3 3905 barrier();
a2fbb9ea
ET		 3906 return rc;
3907}
3908
3909/*
3910 * slow path service functions
3911 */
3912
3913static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3914{
34f80b04 3915 int port = BP_PORT(bp);
a2fbb9ea
ET		 3916 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3917 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3918 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3919 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3920 u32 aeu_mask;
87942b46 3921 u32 nig_mask = 0;
f2e0899f 3922 u32 reg_addr;
a2fbb9ea 3923
a2fbb9ea
ET		 3924 if (bp->attn_state & asserted)
3925 BNX2X_ERR("IGU ERROR\n");
3926
3fcaf2e5
EG		 3927 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3928 aeu_mask = REG_RD(bp, aeu_addr);
3929
a2fbb9ea 3930 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3931 aeu_mask, asserted);
72fd0718 3932 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3933 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3934
3fcaf2e5
EG		 3935 REG_WR(bp, aeu_addr, aeu_mask);
3936 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3937
3fcaf2e5 3938 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3939 bp->attn_state |= asserted;
3fcaf2e5 3940 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3941
3942 if (asserted & ATTN_HARD_WIRED_MASK) {
3943 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3944
a5e9a7cf
EG		 3945 bnx2x_acquire_phy_lock(bp);
3946
877e9aa4 3947 /* save nig interrupt mask */
87942b46 3948 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3949
361c391e
YR		 3950 /* If nig_mask is not set, no need to call the update
3951 * function.
3952 */
3953 if (nig_mask) {
3954 REG_WR(bp, nig_int_mask_addr, 0);
3955
3956 bnx2x_link_attn(bp);
3957 }
a2fbb9ea
ET		 3958
3959 /* handle unicore attn? */
3960 }
3961 if (asserted & ATTN_SW_TIMER_4_FUNC)
3962 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3963
3964 if (asserted & GPIO_2_FUNC)
3965 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3966
3967 if (asserted & GPIO_3_FUNC)
3968 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3969
3970 if (asserted & GPIO_4_FUNC)
3971 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3972
3973 if (port == 0) {
3974 if (asserted & ATTN_GENERAL_ATTN_1) {
3975 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3976 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3977 }
3978 if (asserted & ATTN_GENERAL_ATTN_2) {
3979 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3980 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3981 }
3982 if (asserted & ATTN_GENERAL_ATTN_3) {
3983 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3984 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3985 }
3986 } else {
3987 if (asserted & ATTN_GENERAL_ATTN_4) {
3988 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3989 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3990 }
3991 if (asserted & ATTN_GENERAL_ATTN_5) {
3992 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3993 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3994 }
3995 if (asserted & ATTN_GENERAL_ATTN_6) {
3996 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3997 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3998 }
3999 }
4000
4001 } /* if hardwired */
4002
f2e0899f
DK		 4003 if (bp->common.int_block == INT_BLOCK_HC)
4004 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4005 COMMAND_REG_ATTN_BITS_SET);
4006 else
4007 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4008
4009 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4010 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4011 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 4012
4013 /* now set back the mask */
a5e9a7cf 4014 if (asserted & ATTN_NIG_FOR_FUNC) {
27c1151c
YR		 4015 /* Verify that IGU ack through BAR was written before restoring
4016 * NIG mask. This loop should exit after 2-3 iterations max.
4017 */
4018 if (bp->common.int_block != INT_BLOCK_HC) {
4019 u32 cnt = 0, igu_acked;
4020 do {
4021 igu_acked = REG_RD(bp,
4022 IGU_REG_ATTENTION_ACK_BITS);
4023 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4024 (++cnt < MAX_IGU_ATTN_ACK_TO));
4025 if (!igu_acked)
4026 DP(NETIF_MSG_HW,
4027 "Failed to verify IGU ack on time\n");
4028 barrier();
4029 }
87942b46 4030 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 4031 bnx2x_release_phy_lock(bp);
4032 }
a2fbb9ea
ET		 4033}
4034
1191cb83 4035static void bnx2x_fan_failure(struct bnx2x *bp)
fd4ef40d
EG		 4036{
4037 int port = BP_PORT(bp);
b7737c9b 4038 u32 ext_phy_config;
fd4ef40d 4039 /* mark the failure */
b7737c9b
YR		 4040 ext_phy_config =
4041 SHMEM_RD(bp,
4042 dev_info.port_hw_config[port].external_phy_config);
4043
4044 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4045 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 4046 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 4047 ext_phy_config);
fd4ef40d
EG		 4048
4049 /* log the failure */
51c1a580
MS		 4050 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4051 "Please contact OEM Support for assistance\n");
8304859a 4052
16a5fd92 4053 /* Schedule device reset (unload)
8304859a
AE		 4054 * This is due to some boards consuming sufficient power when driver is
4055 * up to overheat if fan fails.
4056 */
230bb0f3 4057 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
fd4ef40d 4058}
ab6ad5a4 4059
1191cb83 4060static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 4061{
34f80b04 4062 int port = BP_PORT(bp);
877e9aa4 4063 int reg_offset;
d90d96ba 4064 u32 val;
877e9aa4 4065
34f80b04
EG		 4066 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4067 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 4068
34f80b04 4069 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 4070
4071 val = REG_RD(bp, reg_offset);
4072 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4073 REG_WR(bp, reg_offset, val);
4074
4075 BNX2X_ERR("SPIO5 hw attention\n");
4076
fd4ef40d 4077 /* Fan failure attention */
d90d96ba 4078 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 4079 bnx2x_fan_failure(bp);
877e9aa4 4080 }
34f80b04 4081
3deb8167 4082 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 4083 bnx2x_acquire_phy_lock(bp);
4084 bnx2x_handle_module_detect_int(&bp->link_params);
4085 bnx2x_release_phy_lock(bp);
4086 }
4087
34f80b04
EG		 4088 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4089
4090 val = REG_RD(bp, reg_offset);
4091 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4092 REG_WR(bp, reg_offset, val);
4093
4094 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 4095 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 4096 bnx2x_panic();
4097 }
877e9aa4
ET		 4098}
4099
1191cb83 4100static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4101{
4102 u32 val;
4103
0626b899 4104 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 4105
4106 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4107 BNX2X_ERR("DB hw attention 0x%x\n", val);
4108 /* DORQ discard attention */
4109 if (val & 0x2)
4110 BNX2X_ERR("FATAL error from DORQ\n");
4111 }
34f80b04
EG		 4112
4113 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4114
4115 int port = BP_PORT(bp);
4116 int reg_offset;
4117
4118 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4119 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4120
4121 val = REG_RD(bp, reg_offset);
4122 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4123 REG_WR(bp, reg_offset, val);
4124
4125 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 4126 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 4127 bnx2x_panic();
4128 }
877e9aa4
ET		 4129}
4130
1191cb83 4131static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4132{
4133 u32 val;
4134
4135 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4136
4137 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4138 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4139 /* CFC error attention */
4140 if (val & 0x2)
4141 BNX2X_ERR("FATAL error from CFC\n");
4142 }
4143
4144 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 4145 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 4146 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 4147 /* RQ_USDMDP_FIFO_OVERFLOW */
4148 if (val & 0x18000)
4149 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 4150
4151 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4152 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4153 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4154 }
877e9aa4 4155 }
34f80b04
EG		 4156
4157 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4158
4159 int port = BP_PORT(bp);
4160 int reg_offset;
4161
4162 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4163 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4164
4165 val = REG_RD(bp, reg_offset);
4166 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4167 REG_WR(bp, reg_offset, val);
4168
4169 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 4170 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 4171 bnx2x_panic();
4172 }
877e9aa4
ET		 4173}
4174
1191cb83 4175static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
877e9aa4 4176{
34f80b04
EG		 4177 u32 val;
4178
877e9aa4
ET		 4179 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4180
34f80b04
EG		 4181 if (attn & BNX2X_PMF_LINK_ASSERT) {
4182 int func = BP_FUNC(bp);
4183
4184 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
a3348722 4185 bnx2x_read_mf_cfg(bp);
f2e0899f
DK		 4186 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4187 func_mf_config[BP_ABS_FUNC(bp)].config);
4188 val = SHMEM_RD(bp,
4189 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 4190 if (val & DRV_STATUS_DCC_EVENT_MASK)
4191 bnx2x_dcc_event(bp,
4192 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 4193
4194 if (val & DRV_STATUS_SET_MF_BW)
4195 bnx2x_set_mf_bw(bp);
4196
1d187b34
BW		 4197 if (val & DRV_STATUS_DRV_INFO_REQ)
4198 bnx2x_handle_drv_info_req(bp);
d16132ce
AE		 4199
4200 if (val & DRV_STATUS_VF_DISABLED)
370d4a26
YM		 4201 bnx2x_schedule_iov_task(bp,
4202 BNX2X_IOV_HANDLE_FLR);
d16132ce 4203
2691d51d 4204 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 4205 bnx2x_pmf_update(bp);
4206
e4901dde 4207 if (bp->port.pmf &&
785b9b1a
SR		 4208 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4209 bp->dcbx_enabled > 0)
e4901dde
VZ		 4210 /* start dcbx state machine */
4211 bnx2x_dcbx_set_params(bp,
4212 BNX2X_DCBX_STATE_NEG_RECEIVED);
a3348722
BW		 4213 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4214 bnx2x_handle_afex_cmd(bp,
4215 val & DRV_STATUS_AFEX_EVENT_MASK);
c8c60d88
YM		 4216 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4217 bnx2x_handle_eee_event(bp);
3deb8167
YR		 4218 if (bp->link_vars.periodic_flags &
4219 PERIODIC_FLAGS_LINK_EVENT) {
4220 /* sync with link */
4221 bnx2x_acquire_phy_lock(bp);
4222 bp->link_vars.periodic_flags &=
4223 ~PERIODIC_FLAGS_LINK_EVENT;
4224 bnx2x_release_phy_lock(bp);
4225 if (IS_MF(bp))
4226 bnx2x_link_sync_notify(bp);
4227 bnx2x_link_report(bp);
4228 }
4229 /* Always call it here: bnx2x_link_report() will
4230 * prevent the link indication duplication.
4231 */
4232 bnx2x__link_status_update(bp);
34f80b04 4233 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 4234
4235 BNX2X_ERR("MC assert!\n");
d6cae238 4236 bnx2x_mc_assert(bp);
877e9aa4
ET		 4237 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4238 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4239 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4240 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4241 bnx2x_panic();
4242
4243 } else if (attn & BNX2X_MCP_ASSERT) {
4244
4245 BNX2X_ERR("MCP assert!\n");
4246 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 4247 bnx2x_fw_dump(bp);
877e9aa4
ET		 4248
4249 } else
4250 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4251 }
4252
4253 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 4254 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4255 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 4256 val = CHIP_IS_E1(bp) ? 0 :
4257 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 4258 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4259 }
4260 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 4261 val = CHIP_IS_E1(bp) ? 0 :
4262 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 4263 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4264 }
877e9aa4 4265 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 4266 }
4267}
4268
c9ee9206
VZ		 4269/*
4270 * Bits map:
4271 * 0-7 - Engine0 load counter.
4272 * 8-15 - Engine1 load counter.
4273 * 16 - Engine0 RESET_IN_PROGRESS bit.
4274 * 17 - Engine1 RESET_IN_PROGRESS bit.
4275 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4276 * on the engine
4277 * 19 - Engine1 ONE_IS_LOADED.
4278 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4279 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4280 * just the one belonging to its engine).
4281 *
4282 */
4283#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4284
4285#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4286#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4287#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4288#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4289#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4290#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4291#define BNX2X_GLOBAL_RESET_BIT 0x00040000
4292
4293/*
4294 * Set the GLOBAL_RESET bit.
4295 *
4296 * Should be run under rtnl lock
4297 */
4298void bnx2x_set_reset_global(struct bnx2x *bp)
4299{
f16da43b
AE		 4300 u32 val;
4301 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4302 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4303 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
f16da43b 4304 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206
VZ		 4305}
4306
4307/*
4308 * Clear the GLOBAL_RESET bit.
4309 *
4310 * Should be run under rtnl lock
4311 */
1191cb83 4312static void bnx2x_clear_reset_global(struct bnx2x *bp)
c9ee9206 4313{
f16da43b
AE		 4314 u32 val;
4315 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4316 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4317 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
f16da43b 4318 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206 4319}
f85582f8 4320
72fd0718 4321/*
c9ee9206
VZ		 4322 * Checks the GLOBAL_RESET bit.
4323 *
72fd0718
VZ		 4324 * should be run under rtnl lock
4325 */
1191cb83 4326static bool bnx2x_reset_is_global(struct bnx2x *bp)
c9ee9206 4327{
3cdeec22 4328 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4329
4330 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4331 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4332}
4333
4334/*
4335 * Clear RESET_IN_PROGRESS bit for the current engine.
4336 *
4337 * Should be run under rtnl lock
4338 */
1191cb83 4339static void bnx2x_set_reset_done(struct bnx2x *bp)
72fd0718 4340{
f16da43b 4341 u32 val;
c9ee9206
VZ		 4342 u32 bit = BP_PATH(bp) ?
4343 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4344 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4345 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4346
4347 /* Clear the bit */
4348 val &= ~bit;
4349 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4350
4351 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4352}
4353
4354/*
c9ee9206
VZ		 4355 * Set RESET_IN_PROGRESS for the current engine.
4356 *
72fd0718
VZ		 4357 * should be run under rtnl lock
4358 */
c9ee9206 4359void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 4360{
f16da43b 4361 u32 val;
c9ee9206
VZ		 4362 u32 bit = BP_PATH(bp) ?
4363 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4364 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4365 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4366
4367 /* Set the bit */
4368 val |= bit;
4369 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4370 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4371}
4372
4373/*
c9ee9206 4374 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 4375 * should be run under rtnl lock
4376 */
c9ee9206 4377bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 4378{
3cdeec22 4379 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4380 u32 bit = engine ?
4381 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4382
4383 /* return false if bit is set */
4384 return (val & bit) ? false : true;
72fd0718
VZ		 4385}
4386
4387/*
889b9af3 4388 * set pf load for the current pf.
c9ee9206 4389 *
72fd0718
VZ		 4390 * should be run under rtnl lock
4391 */
889b9af3 4392void bnx2x_set_pf_load(struct bnx2x *bp)
72fd0718 4393{
f16da43b 4394 u32 val1, val;
c9ee9206
VZ		 4395 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4396 BNX2X_PATH0_LOAD_CNT_MASK;
4397 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4398 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4399
f16da43b
AE		 4400 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4401 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4402
51c1a580 4403 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4404
c9ee9206
VZ		 4405 /* get the current counter value */
4406 val1 = (val & mask) >> shift;
4407
889b9af3
AE		 4408 /* set bit of that PF */
4409 val1 |= (1 << bp->pf_num);
c9ee9206
VZ		 4410
4411 /* clear the old value */
4412 val &= ~mask;
4413
4414 /* set the new one */
4415 val |= ((val1 << shift) & mask);
4416
4417 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4418 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4419}
4420
c9ee9206 4421/**
889b9af3 4422 * bnx2x_clear_pf_load - clear pf load mark
c9ee9206
VZ		 4423 *
4424 * @bp: driver handle
4425 *
4426 * Should be run under rtnl lock.
4427 * Decrements the load counter for the current engine. Returns
889b9af3 4428 * whether other functions are still loaded
72fd0718 4429 */
889b9af3 4430bool bnx2x_clear_pf_load(struct bnx2x *bp)
72fd0718 4431{
f16da43b 4432 u32 val1, val;
c9ee9206
VZ		 4433 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4434 BNX2X_PATH0_LOAD_CNT_MASK;
4435 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4436 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4437
f16da43b
AE		 4438 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4439 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
51c1a580 4440 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4441
c9ee9206
VZ		 4442 /* get the current counter value */
4443 val1 = (val & mask) >> shift;
4444
889b9af3
AE		 4445 /* clear bit of that PF */
4446 val1 &= ~(1 << bp->pf_num);
c9ee9206
VZ		 4447
4448 /* clear the old value */
4449 val &= ~mask;
4450
4451 /* set the new one */
4452 val |= ((val1 << shift) & mask);
4453
4454 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4455 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4456 return val1 != 0;
72fd0718
VZ		 4457}
4458
4459/*
889b9af3 4460 * Read the load status for the current engine.
c9ee9206 4461 *
72fd0718
VZ		 4462 * should be run under rtnl lock
4463 */
1191cb83 4464static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
72fd0718 4465{
c9ee9206
VZ		 4466 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4467 BNX2X_PATH0_LOAD_CNT_MASK);
4468 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4469 BNX2X_PATH0_LOAD_CNT_SHIFT);
4470 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4471
51c1a580 4472 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
c9ee9206
VZ		 4473
4474 val = (val & mask) >> shift;
4475
51c1a580
MS		 4476 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4477 engine, val);
c9ee9206 4478
889b9af3 4479 return val != 0;
72fd0718
VZ		 4480}
4481
6bf07b8e
YM		 4482static void _print_parity(struct bnx2x *bp, u32 reg)
4483{
4484 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4485}
4486
1191cb83 4487static void _print_next_block(int idx, const char *blk)
72fd0718 4488{
f1deab50 4489 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 4490}
4491
4293b9f5
DK		 4492static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4493 int *par_num, bool print)
72fd0718 4494{
4293b9f5
DK		 4495 u32 cur_bit;
4496 bool res;
4497 int i;
4498
4499 res = false;
4500
72fd0718 4501 for (i = 0; sig; i++) {
4293b9f5 4502 cur_bit = (0x1UL << i);
72fd0718 4503 if (sig & cur_bit) {
4293b9f5
DK		 4504 res |= true; /* Each bit is real error! */
4505
4506 if (print) {
4507 switch (cur_bit) {
4508 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4509 _print_next_block((*par_num)++, "BRB");
6bf07b8e
YM		 4510 _print_parity(bp,
4511 BRB1_REG_BRB1_PRTY_STS);
4293b9f5
DK		 4512 break;
4513 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4514 _print_next_block((*par_num)++,
4515 "PARSER");
6bf07b8e 4516 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4293b9f5
DK		 4517 break;
4518 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4519 _print_next_block((*par_num)++, "TSDM");
6bf07b8e
YM		 4520 _print_parity(bp,
4521 TSDM_REG_TSDM_PRTY_STS);
4293b9f5
DK		 4522 break;
4523 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4524 _print_next_block((*par_num)++,
c9ee9206 4525 "SEARCHER");
6bf07b8e 4526 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4293b9f5
DK		 4527 break;
4528 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4529 _print_next_block((*par_num)++, "TCM");
4530 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4531 break;
4532 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4533 _print_next_block((*par_num)++,
4534 "TSEMI");
6bf07b8e
YM		 4535 _print_parity(bp,
4536 TSEM_REG_TSEM_PRTY_STS_0);
4537 _print_parity(bp,
4538 TSEM_REG_TSEM_PRTY_STS_1);
4293b9f5
DK		 4539 break;
4540 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4541 _print_next_block((*par_num)++, "XPB");
6bf07b8e
YM		 4542 _print_parity(bp, GRCBASE_XPB +
4543 PB_REG_PB_PRTY_STS);
4293b9f5 4544 break;
6bf07b8e 4545 }
72fd0718
VZ		 4546 }
4547
4548 /* Clear the bit */
4549 sig &= ~cur_bit;
4550 }
4551 }
4552
4293b9f5 4553 return res;
72fd0718
VZ		 4554}
4555
4293b9f5
DK		 4556static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4557 int *par_num, bool *global,
6bf07b8e 4558 bool print)
72fd0718 4559{
4293b9f5
DK		 4560 u32 cur_bit;
4561 bool res;
4562 int i;
4563
4564 res = false;
4565
72fd0718 4566 for (i = 0; sig; i++) {
4293b9f5 4567 cur_bit = (0x1UL << i);
72fd0718 4568 if (sig & cur_bit) {
4293b9f5 4569 res |= true; /* Each bit is real error! */
72fd0718 4570 switch (cur_bit) {
c9ee9206 4571 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
6bf07b8e 4572 if (print) {
4293b9f5 4573 _print_next_block((*par_num)++, "PBF");
6bf07b8e
YM		 4574 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4575 }
72fd0718
VZ		 4576 break;
4577 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
6bf07b8e 4578 if (print) {
4293b9f5 4579 _print_next_block((*par_num)++, "QM");
6bf07b8e
YM		 4580 _print_parity(bp, QM_REG_QM_PRTY_STS);
4581 }
c9ee9206
VZ		 4582 break;
4583 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
6bf07b8e 4584 if (print) {
4293b9f5 4585 _print_next_block((*par_num)++, "TM");
6bf07b8e
YM		 4586 _print_parity(bp, TM_REG_TM_PRTY_STS);
4587 }
72fd0718
VZ		 4588 break;
4589 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
6bf07b8e 4590 if (print) {
4293b9f5 4591 _print_next_block((*par_num)++, "XSDM");
6bf07b8e
YM		 4592 _print_parity(bp,
4593 XSDM_REG_XSDM_PRTY_STS);
4594 }
c9ee9206
VZ		 4595 break;
4596 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
6bf07b8e 4597 if (print) {
4293b9f5 4598 _print_next_block((*par_num)++, "XCM");
6bf07b8e
YM		 4599 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4600 }
72fd0718
VZ		 4601 break;
4602 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
6bf07b8e 4603 if (print) {
4293b9f5
DK		 4604 _print_next_block((*par_num)++,
4605 "XSEMI");
6bf07b8e
YM		 4606 _print_parity(bp,
4607 XSEM_REG_XSEM_PRTY_STS_0);
4608 _print_parity(bp,
4609 XSEM_REG_XSEM_PRTY_STS_1);
4610 }
72fd0718
VZ		 4611 break;
4612 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
6bf07b8e 4613 if (print) {
4293b9f5 4614 _print_next_block((*par_num)++,
c9ee9206 4615 "DOORBELLQ");
6bf07b8e
YM		 4616 _print_parity(bp,
4617 DORQ_REG_DORQ_PRTY_STS);
4618 }
c9ee9206
VZ		 4619 break;
4620 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
6bf07b8e 4621 if (print) {
4293b9f5 4622 _print_next_block((*par_num)++, "NIG");
6bf07b8e
YM		 4623 if (CHIP_IS_E1x(bp)) {
4624 _print_parity(bp,
4625 NIG_REG_NIG_PRTY_STS);
4626 } else {
4627 _print_parity(bp,
4628 NIG_REG_NIG_PRTY_STS_0);
4629 _print_parity(bp,
4630 NIG_REG_NIG_PRTY_STS_1);
4631 }
4632 }
72fd0718
VZ		 4633 break;
4634 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206 4635 if (print)
4293b9f5 4636 _print_next_block((*par_num)++,
c9ee9206
VZ		 4637 "VAUX PCI CORE");
4638 *global = true;
72fd0718
VZ		 4639 break;
4640 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
6bf07b8e 4641 if (print) {
4293b9f5
DK		 4642 _print_next_block((*par_num)++,
4643 "DEBUG");
6bf07b8e
YM		 4644 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4645 }
72fd0718
VZ		 4646 break;
4647 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
6bf07b8e 4648 if (print) {
4293b9f5 4649 _print_next_block((*par_num)++, "USDM");
6bf07b8e
YM		 4650 _print_parity(bp,
4651 USDM_REG_USDM_PRTY_STS);
4652 }
72fd0718 4653 break;
8736c826 4654 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
6bf07b8e 4655 if (print) {
4293b9f5 4656 _print_next_block((*par_num)++, "UCM");
6bf07b8e
YM		 4657 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4658 }
8736c826 4659 break;
72fd0718 4660 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
6bf07b8e 4661 if (print) {
4293b9f5
DK		 4662 _print_next_block((*par_num)++,
4663 "USEMI");
6bf07b8e
YM		 4664 _print_parity(bp,
4665 USEM_REG_USEM_PRTY_STS_0);
4666 _print_parity(bp,
4667 USEM_REG_USEM_PRTY_STS_1);
4668 }
72fd0718
VZ		 4669 break;
4670 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
6bf07b8e 4671 if (print) {
4293b9f5 4672 _print_next_block((*par_num)++, "UPB");
6bf07b8e
YM		 4673 _print_parity(bp, GRCBASE_UPB +
4674 PB_REG_PB_PRTY_STS);
4675 }
72fd0718
VZ		 4676 break;
4677 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
6bf07b8e 4678 if (print) {
4293b9f5 4679 _print_next_block((*par_num)++, "CSDM");
6bf07b8e
YM		 4680 _print_parity(bp,
4681 CSDM_REG_CSDM_PRTY_STS);
4682 }
72fd0718 4683 break;
8736c826 4684 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
6bf07b8e 4685 if (print) {
4293b9f5 4686 _print_next_block((*par_num)++, "CCM");
6bf07b8e
YM		 4687 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4688 }
8736c826 4689 break;
72fd0718
VZ		 4690 }
4691
4692 /* Clear the bit */
4693 sig &= ~cur_bit;
4694 }
4695 }
4696
4293b9f5 4697 return res;
72fd0718
VZ		 4698}
4699
4293b9f5
DK		 4700static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4701 int *par_num, bool print)
72fd0718 4702{
4293b9f5
DK		 4703 u32 cur_bit;
4704 bool res;
4705 int i;
4706
4707 res = false;
4708
72fd0718 4709 for (i = 0; sig; i++) {
4293b9f5 4710 cur_bit = (0x1UL << i);
72fd0718 4711 if (sig & cur_bit) {
0c23ad37 4712 res = true; /* Each bit is real error! */
4293b9f5
DK		 4713 if (print) {
4714 switch (cur_bit) {
4715 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4716 _print_next_block((*par_num)++,
4717 "CSEMI");
6bf07b8e
YM		 4718 _print_parity(bp,
4719 CSEM_REG_CSEM_PRTY_STS_0);
4720 _print_parity(bp,
4721 CSEM_REG_CSEM_PRTY_STS_1);
4293b9f5
DK		 4722 break;
4723 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4724 _print_next_block((*par_num)++, "PXP");
6bf07b8e
YM		 4725 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4726 _print_parity(bp,
4727 PXP2_REG_PXP2_PRTY_STS_0);
4728 _print_parity(bp,
4729 PXP2_REG_PXP2_PRTY_STS_1);
4293b9f5
DK		 4730 break;
4731 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4732 _print_next_block((*par_num)++,
4733 "PXPPCICLOCKCLIENT");
4734 break;
4735 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4736 _print_next_block((*par_num)++, "CFC");
6bf07b8e
YM		 4737 _print_parity(bp,
4738 CFC_REG_CFC_PRTY_STS);
4293b9f5
DK		 4739 break;
4740 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4741 _print_next_block((*par_num)++, "CDU");
6bf07b8e 4742 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4293b9f5
DK		 4743 break;
4744 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4745 _print_next_block((*par_num)++, "DMAE");
6bf07b8e
YM		 4746 _print_parity(bp,
4747 DMAE_REG_DMAE_PRTY_STS);
4293b9f5
DK		 4748 break;
4749 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4750 _print_next_block((*par_num)++, "IGU");
6bf07b8e
YM		 4751 if (CHIP_IS_E1x(bp))
4752 _print_parity(bp,
4753 HC_REG_HC_PRTY_STS);
4754 else
4755 _print_parity(bp,
4756 IGU_REG_IGU_PRTY_STS);
4293b9f5
DK		 4757 break;
4758 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4759 _print_next_block((*par_num)++, "MISC");
6bf07b8e
YM		 4760 _print_parity(bp,
4761 MISC_REG_MISC_PRTY_STS);
4293b9f5 4762 break;
6bf07b8e 4763 }
72fd0718
VZ		 4764 }
4765
4766 /* Clear the bit */
4767 sig &= ~cur_bit;
4768 }
4769 }
4770
4293b9f5 4771 return res;
72fd0718
VZ		 4772}
4773
4293b9f5
DK		 4774static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4775 int *par_num, bool *global,
4776 bool print)
72fd0718 4777{
4293b9f5
DK		 4778 bool res = false;
4779 u32 cur_bit;
4780 int i;
4781
72fd0718 4782 for (i = 0; sig; i++) {
4293b9f5 4783 cur_bit = (0x1UL << i);
72fd0718
VZ		 4784 if (sig & cur_bit) {
4785 switch (cur_bit) {
4786 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206 4787 if (print)
4293b9f5
DK		 4788 _print_next_block((*par_num)++,
4789 "MCP ROM");
c9ee9206 4790 *global = true;
0c23ad37 4791 res = true;
72fd0718
VZ		 4792 break;
4793 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206 4794 if (print)
4293b9f5 4795 _print_next_block((*par_num)++,
c9ee9206
VZ		 4796 "MCP UMP RX");
4797 *global = true;
0c23ad37 4798 res = true;
72fd0718
VZ		 4799 break;
4800 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206 4801 if (print)
4293b9f5 4802 _print_next_block((*par_num)++,
c9ee9206
VZ		 4803 "MCP UMP TX");
4804 *global = true;
0c23ad37 4805 res = true;
72fd0718
VZ		 4806 break;
4807 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206 4808 if (print)
4293b9f5 4809 _print_next_block((*par_num)++,
c9ee9206 4810 "MCP SCPAD");
4293b9f5
DK		 4811 /* clear latched SCPAD PATIRY from MCP */
4812 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4813 1UL << 10);
72fd0718
VZ		 4814 break;
4815 }
4816
4817 /* Clear the bit */
4818 sig &= ~cur_bit;
4819 }
4820 }
4821
4293b9f5 4822 return res;
72fd0718
VZ		 4823}
4824
4293b9f5
DK		 4825static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4826 int *par_num, bool print)
8736c826 4827{
4293b9f5
DK		 4828 u32 cur_bit;
4829 bool res;
4830 int i;
4831
4832 res = false;
4833
8736c826 4834 for (i = 0; sig; i++) {
4293b9f5 4835 cur_bit = (0x1UL << i);
8736c826 4836 if (sig & cur_bit) {
0c23ad37 4837 res = true; /* Each bit is real error! */
4293b9f5
DK		 4838 if (print) {
4839 switch (cur_bit) {
4840 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4841 _print_next_block((*par_num)++,
4842 "PGLUE_B");
6bf07b8e 4843 _print_parity(bp,
4293b9f5
DK		 4844 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4845 break;
4846 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4847 _print_next_block((*par_num)++, "ATC");
6bf07b8e
YM		 4848 _print_parity(bp,
4849 ATC_REG_ATC_PRTY_STS);
4293b9f5 4850 break;
6bf07b8e 4851 }
8736c826 4852 }
8736c826
VZ		 4853 /* Clear the bit */
4854 sig &= ~cur_bit;
4855 }
4856 }
4857
4293b9f5 4858 return res;
8736c826
VZ		 4859}
4860
1191cb83
ED		 4861static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4862 u32 *sig)
72fd0718 4863{
4293b9f5
DK		 4864 bool res = false;
4865
8736c826
VZ		 4866 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4867 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4868 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4869 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4870 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718 4871 int par_num = 0;
51c1a580
MS		 4872 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4873 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
8736c826
VZ		 4874 sig[0] & HW_PRTY_ASSERT_SET_0,
4875 sig[1] & HW_PRTY_ASSERT_SET_1,
4876 sig[2] & HW_PRTY_ASSERT_SET_2,
4877 sig[3] & HW_PRTY_ASSERT_SET_3,
4878 sig[4] & HW_PRTY_ASSERT_SET_4);
c9ee9206
VZ		 4879 if (print)
4880 netdev_err(bp->dev,
4881 "Parity errors detected in blocks: ");
4293b9f5
DK		 4882 res |= bnx2x_check_blocks_with_parity0(bp,
4883 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4884 res |= bnx2x_check_blocks_with_parity1(bp,
4885 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4886 res |= bnx2x_check_blocks_with_parity2(bp,
4887 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4888 res |= bnx2x_check_blocks_with_parity3(bp,
4889 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4890 res |= bnx2x_check_blocks_with_parity4(bp,
4891 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
8736c826 4892
c9ee9206
VZ		 4893 if (print)
4894 pr_cont("\n");
4293b9f5 4895 }
8736c826 4896
4293b9f5 4897 return res;
72fd0718
VZ		 4898}
4899
c9ee9206
VZ		 4900/**
4901 * bnx2x_chk_parity_attn - checks for parity attentions.
4902 *
4903 * @bp: driver handle
4904 * @global: true if there was a global attention
4905 * @print: show parity attention in syslog
4906 */
4907bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 4908{
8736c826 4909 struct attn_route attn = { {0} };
72fd0718
VZ		 4910 int port = BP_PORT(bp);
4911
4912 attn.sig[0] = REG_RD(bp,
4913 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4914 port*4);
4915 attn.sig[1] = REG_RD(bp,
4916 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4917 port*4);
4918 attn.sig[2] = REG_RD(bp,
4919 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4920 port*4);
4921 attn.sig[3] = REG_RD(bp,
4922 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4923 port*4);
0a5ccb75
YM		 4924 /* Since MCP attentions can't be disabled inside the block, we need to
4925 * read AEU registers to see whether they're currently disabled
4926 */
4927 attn.sig[3] &= ((REG_RD(bp,
4928 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4929 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4930 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4931 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
72fd0718 4932
8736c826
VZ		 4933 if (!CHIP_IS_E1x(bp))
4934 attn.sig[4] = REG_RD(bp,
4935 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4936 port*4);
4937
4938 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 4939}
4940
1191cb83 4941static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
f2e0899f
DK		 4942{
4943 u32 val;
4944 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4945
4946 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4947 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4948 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
51c1a580 4949 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
f2e0899f 4950 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
51c1a580 4951 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
f2e0899f 4952 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
51c1a580 4953 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
f2e0899f 4954 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
51c1a580 4955 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
f2e0899f
DK		 4956 if (val &
4957 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
51c1a580 4958 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
f2e0899f
DK		 4959 if (val &
4960 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
51c1a580 4961 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
f2e0899f 4962 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
51c1a580 4963 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
f2e0899f 4964 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
51c1a580 4965 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
f2e0899f 4966 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
51c1a580 4967 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
f2e0899f
DK		 4968 }
4969 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4970 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4971 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4972 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4973 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4974 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
51c1a580 4975 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
f2e0899f 4976 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
51c1a580 4977 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
f2e0899f 4978 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
51c1a580 4979 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
f2e0899f
DK		 4980 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4981 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4982 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
51c1a580 4983 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
f2e0899f
DK		 4984 }
4985
4986 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4987 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4988 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4989 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4990 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4991 }
f2e0899f
DK		 4992}
4993
72fd0718
VZ		 4994static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4995{
4996 struct attn_route attn, *group_mask;
34f80b04 4997 int port = BP_PORT(bp);
877e9aa4 4998 int index;
a2fbb9ea
ET		 4999 u32 reg_addr;
5000 u32 val;
3fcaf2e5 5001 u32 aeu_mask;
c9ee9206 5002 bool global = false;
a2fbb9ea
ET		 5003
5004 /* need to take HW lock because MCP or other port might also
5005 try to handle this event */
4a37fb66 5006 bnx2x_acquire_alr(bp);
a2fbb9ea 5007
c9ee9206
VZ		 5008 if (bnx2x_chk_parity_attn(bp, &global, true)) {
5009#ifndef BNX2X_STOP_ON_ERROR
72fd0718 5010 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 5011 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 5012 /* Disable HW interrupts */
5013 bnx2x_int_disable(bp);
72fd0718
VZ		 5014 /* In case of parity errors don't handle attentions so that
5015 * other function would "see" parity errors.
5016 */
c9ee9206
VZ		 5017#else
5018 bnx2x_panic();
5019#endif
5020 bnx2x_release_alr(bp);
72fd0718
VZ		 5021 return;
5022 }
5023
a2fbb9ea
ET		 5024 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5025 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5026 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5027 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 5028 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5029 attn.sig[4] =
5030 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5031 else
5032 attn.sig[4] = 0;
5033
5034 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5035 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 5036
5037 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5038 if (deasserted & (1 << index)) {
72fd0718 5039 group_mask = &bp->attn_group[index];
a2fbb9ea 5040
51c1a580 5041 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
f2e0899f
DK		 5042 index,
5043 group_mask->sig[0], group_mask->sig[1],
5044 group_mask->sig[2], group_mask->sig[3],
5045 group_mask->sig[4]);
a2fbb9ea 5046
f2e0899f
DK		 5047 bnx2x_attn_int_deasserted4(bp,
5048 attn.sig[4] & group_mask->sig[4]);
877e9aa4 5049 bnx2x_attn_int_deasserted3(bp,
72fd0718 5050 attn.sig[3] & group_mask->sig[3]);
877e9aa4 5051 bnx2x_attn_int_deasserted1(bp,
72fd0718 5052 attn.sig[1] & group_mask->sig[1]);
877e9aa4 5053 bnx2x_attn_int_deasserted2(bp,
72fd0718 5054 attn.sig[2] & group_mask->sig[2]);
877e9aa4 5055 bnx2x_attn_int_deasserted0(bp,
72fd0718 5056 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 5057 }
5058 }
5059
4a37fb66 5060 bnx2x_release_alr(bp);
a2fbb9ea 5061
f2e0899f
DK		 5062 if (bp->common.int_block == INT_BLOCK_HC)
5063 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5064 COMMAND_REG_ATTN_BITS_CLR);
5065 else
5066 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 5067
5068 val = ~deasserted;
f2e0899f
DK		 5069 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5070 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 5071 REG_WR(bp, reg_addr, val);
a2fbb9ea 5072
a2fbb9ea 5073 if (~bp->attn_state & deasserted)
3fcaf2e5 5074 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 5075
5076 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5077 MISC_REG_AEU_MASK_ATTN_FUNC_0;
5078
3fcaf2e5
EG		 5079 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5080 aeu_mask = REG_RD(bp, reg_addr);
5081
5082 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
5083 aeu_mask, deasserted);
72fd0718 5084 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 5085 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 5086
3fcaf2e5
EG		 5087 REG_WR(bp, reg_addr, aeu_mask);
5088 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 5089
5090 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5091 bp->attn_state &= ~deasserted;
5092 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5093}
5094
5095static void bnx2x_attn_int(struct bnx2x *bp)
5096{
5097 /* read local copy of bits */
68d59484
EG		 5098 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5099 attn_bits);
5100 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5101 attn_bits_ack);
a2fbb9ea
ET		 5102 u32 attn_state = bp->attn_state;
5103
5104 /* look for changed bits */
5105 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
5106 u32 deasserted = ~attn_bits & attn_ack & attn_state;
5107
5108 DP(NETIF_MSG_HW,
5109 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5110 attn_bits, attn_ack, asserted, deasserted);
5111
5112 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 5113 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 5114
5115 /* handle bits that were raised */
5116 if (asserted)
5117 bnx2x_attn_int_asserted(bp, asserted);
5118
5119 if (deasserted)
5120 bnx2x_attn_int_deasserted(bp, deasserted);
5121}
5122
619c5cb6
VZ		 5123void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5124 u16 index, u8 op, u8 update)
5125{
dc1ba591
AE		 5126 u32 igu_addr = bp->igu_base_addr;
5127 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
619c5cb6
VZ		 5128 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5129 igu_addr);
5130}
5131
1191cb83 5132static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
523224a3
DK		 5133{
5134 /* No memory barriers */
5135 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5136 mmiowb(); /* keep prod updates ordered */
5137}
5138
523224a3
DK		 5139static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5140 union event_ring_elem *elem)
5141{
619c5cb6
VZ		 5142 u8 err = elem->message.error;
5143
523224a3 5144 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 5145 (cid < bp->cnic_eth_dev.starting_cid &&
5146 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 5147 return 1;
5148
5149 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5150
619c5cb6
VZ		 5151 if (unlikely(err)) {
5152
523224a3
DK		 5153 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5154 cid);
823e1d90 5155 bnx2x_panic_dump(bp, false);
523224a3 5156 }
619c5cb6 5157 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 5158 return 0;
5159}
523224a3 5160
1191cb83 5161static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5162{
5163 struct bnx2x_mcast_ramrod_params rparam;
5164 int rc;
5165
5166 memset(&rparam, 0, sizeof(rparam));
5167
5168 rparam.mcast_obj = &bp->mcast_obj;
5169
5170 netif_addr_lock_bh(bp->dev);
5171
5172 /* Clear pending state for the last command */
5173 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5174
5175 /* If there are pending mcast commands - send them */
5176 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5177 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5178 if (rc < 0)
5179 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5180 rc);
5181 }
5182
5183 netif_addr_unlock_bh(bp->dev);
5184}
5185
1191cb83
ED		 5186static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5187 union event_ring_elem *elem)
619c5cb6
VZ		 5188{
5189 unsigned long ramrod_flags = 0;
5190 int rc = 0;
5191 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5192 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5193
5194 /* Always push next commands out, don't wait here */
5195 __set_bit(RAMROD_CONT, &ramrod_flags);
5196
86564c3f
YM		 5197 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5198 >> BNX2X_SWCID_SHIFT) {
619c5cb6 5199 case BNX2X_FILTER_MAC_PENDING:
51c1a580 5200 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
55c11941 5201 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
619c5cb6
VZ		 5202 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5203 else
15192a8c 5204 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
619c5cb6
VZ		 5205
5206 break;
619c5cb6 5207 case BNX2X_FILTER_MCAST_PENDING:
51c1a580 5208 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
619c5cb6
VZ		 5209 /* This is only relevant for 57710 where multicast MACs are
5210 * configured as unicast MACs using the same ramrod.
5211 */
5212 bnx2x_handle_mcast_eqe(bp);
5213 return;
5214 default:
5215 BNX2X_ERR("Unsupported classification command: %d\n",
5216 elem->message.data.eth_event.echo);
5217 return;
5218 }
5219
5220 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5221
5222 if (rc < 0)
5223 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5224 else if (rc > 0)
5225 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
619c5cb6
VZ		 5226}
5227
619c5cb6 5228static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
619c5cb6 5229
1191cb83 5230static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5231{
5232 netif_addr_lock_bh(bp->dev);
5233
5234 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5235
5236 /* Send rx_mode command again if was requested */
5237 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5238 bnx2x_set_storm_rx_mode(bp);
619c5cb6
VZ		 5239 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5240 &bp->sp_state))
5241 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5242 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5243 &bp->sp_state))
5244 bnx2x_set_iscsi_eth_rx_mode(bp, false);
619c5cb6
VZ		 5245
5246 netif_addr_unlock_bh(bp->dev);
5247}
5248
1191cb83 5249static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
a3348722
BW		 5250 union event_ring_elem *elem)
5251{
5252 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5253 DP(BNX2X_MSG_SP,
5254 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5255 elem->message.data.vif_list_event.func_bit_map);
5256 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5257 elem->message.data.vif_list_event.func_bit_map);
5258 } else if (elem->message.data.vif_list_event.echo ==
5259 VIF_LIST_RULE_SET) {
5260 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5261 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5262 }
5263}
5264
5265/* called with rtnl_lock */
1191cb83 5266static void bnx2x_after_function_update(struct bnx2x *bp)
a3348722
BW		 5267{
5268 int q, rc;
5269 struct bnx2x_fastpath *fp;
5270 struct bnx2x_queue_state_params queue_params = {NULL};
5271 struct bnx2x_queue_update_params *q_update_params =
5272 &queue_params.params.update;
5273
2de67439 5274 /* Send Q update command with afex vlan removal values for all Qs */
a3348722
BW		 5275 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5276
5277 /* set silent vlan removal values according to vlan mode */
5278 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5279 &q_update_params->update_flags);
5280 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5281 &q_update_params->update_flags);
5282 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5283
5284 /* in access mode mark mask and value are 0 to strip all vlans */
5285 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5286 q_update_params->silent_removal_value = 0;
5287 q_update_params->silent_removal_mask = 0;
5288 } else {
5289 q_update_params->silent_removal_value =
5290 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5291 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5292 }
5293
5294 for_each_eth_queue(bp, q) {
5295 /* Set the appropriate Queue object */
5296 fp = &bp->fp[q];
15192a8c 5297 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5298
5299 /* send the ramrod */
5300 rc = bnx2x_queue_state_change(bp, &queue_params);
5301 if (rc < 0)
5302 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5303 q);
5304 }
5305
fea75645 5306 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
65565884 5307 fp = &bp->fp[FCOE_IDX(bp)];
15192a8c 5308 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5309
5310 /* clear pending completion bit */
5311 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5312
5313 /* mark latest Q bit */
4e857c58 5314 smp_mb__before_atomic();
a3348722 5315 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4e857c58 5316 smp_mb__after_atomic();
a3348722
BW		 5317
5318 /* send Q update ramrod for FCoE Q */
5319 rc = bnx2x_queue_state_change(bp, &queue_params);
5320 if (rc < 0)
5321 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5322 q);
5323 } else {
5324 /* If no FCoE ring - ACK MCP now */
5325 bnx2x_link_report(bp);
5326 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5327 }
a3348722
BW		 5328}
5329
1191cb83 5330static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
619c5cb6
VZ		 5331 struct bnx2x *bp, u32 cid)
5332{
94f05b0f 5333 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
55c11941
MS		 5334
5335 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
15192a8c 5336 return &bnx2x_fcoe_sp_obj(bp, q_obj);
619c5cb6 5337 else
15192a8c 5338 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
619c5cb6
VZ		 5339}
5340
523224a3
DK		 5341static void bnx2x_eq_int(struct bnx2x *bp)
5342{
5343 u16 hw_cons, sw_cons, sw_prod;
5344 union event_ring_elem *elem;
55c11941 5345 u8 echo;
523224a3
DK		 5346 u32 cid;
5347 u8 opcode;
fd1fc79d 5348 int rc, spqe_cnt = 0;
619c5cb6
VZ		 5349 struct bnx2x_queue_sp_obj *q_obj;
5350 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5351 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 5352
5353 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5354
5355 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
16a5fd92 5356 * when we get the next-page we need to adjust so the loop
523224a3
DK		 5357 * condition below will be met. The next element is the size of a
5358 * regular element and hence incrementing by 1
5359 */
5360 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5361 hw_cons++;
5362
25985edc 5363 /* This function may never run in parallel with itself for a
523224a3
DK		 5364 * specific bp, thus there is no need in "paired" read memory
5365 * barrier here.
5366 */
5367 sw_cons = bp->eq_cons;
5368 sw_prod = bp->eq_prod;
5369
d6cae238 5370 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 5371 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 5372
5373 for (; sw_cons != hw_cons;
5374 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5375
523224a3
DK		 5376 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5377
fd1fc79d
AE		 5378 rc = bnx2x_iov_eq_sp_event(bp, elem);
5379 if (!rc) {
5380 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5381 rc);
5382 goto next_spqe;
5383 }
523224a3 5384
86564c3f
YM		 5385 /* elem CID originates from FW; actually LE */
5386 cid = SW_CID((__force __le32)
5387 elem->message.data.cfc_del_event.cid);
5388 opcode = elem->message.opcode;
523224a3
DK		 5389
5390 /* handle eq element */
5391 switch (opcode) {
fd1fc79d 5392 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
370d4a26
YM		 5393 bnx2x_vf_mbx_schedule(bp,
5394 &elem->message.data.vf_pf_event);
fd1fc79d
AE		 5395 continue;
5396
523224a3 5397 case EVENT_RING_OPCODE_STAT_QUERY:
76ca70fa
YM		 5398 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5399 "got statistics comp event %d\n",
5400 bp->stats_comp++);
523224a3 5401 /* nothing to do with stats comp */
d6cae238 5402 goto next_spqe;
523224a3
DK		 5403
5404 case EVENT_RING_OPCODE_CFC_DEL:
5405 /* handle according to cid range */
5406 /*
5407 * we may want to verify here that the bp state is
5408 * HALTING
5409 */
d6cae238 5410 DP(BNX2X_MSG_SP,
523224a3 5411 "got delete ramrod for MULTI[%d]\n", cid);
55c11941
MS		 5412
5413 if (CNIC_LOADED(bp) &&
5414 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
523224a3 5415 goto next_spqe;
55c11941 5416
619c5cb6
VZ		 5417 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5418
5419 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5420 break;
5421
523224a3 5422 goto next_spqe;
e4901dde
VZ		 5423
5424 case EVENT_RING_OPCODE_STOP_TRAFFIC:
51c1a580 5425 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
6ffa39f2 5426 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
6debea87
DK		 5427 if (f_obj->complete_cmd(bp, f_obj,
5428 BNX2X_F_CMD_TX_STOP))
5429 break;
e4901dde 5430 goto next_spqe;
619c5cb6 5431
e4901dde 5432 case EVENT_RING_OPCODE_START_TRAFFIC:
51c1a580 5433 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
6ffa39f2 5434 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
6debea87
DK		 5435 if (f_obj->complete_cmd(bp, f_obj,
5436 BNX2X_F_CMD_TX_START))
5437 break;
e4901dde 5438 goto next_spqe;
55c11941 5439
a3348722 5440 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
55c11941
MS		 5441 echo = elem->message.data.function_update_event.echo;
5442 if (echo == SWITCH_UPDATE) {
5443 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5444 "got FUNC_SWITCH_UPDATE ramrod\n");
5445 if (f_obj->complete_cmd(
5446 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5447 break;
a3348722 5448
55c11941 5449 } else {
230bb0f3
YM		 5450 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5451
55c11941
MS		 5452 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5453 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5454 f_obj->complete_cmd(bp, f_obj,
5455 BNX2X_F_CMD_AFEX_UPDATE);
5456
5457 /* We will perform the Queues update from
5458 * sp_rtnl task as all Queue SP operations
5459 * should run under rtnl_lock.
5460 */
230bb0f3 5461 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
55c11941 5462 }
a3348722 5463
a3348722
BW		 5464 goto next_spqe;
5465
5466 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5467 f_obj->complete_cmd(bp, f_obj,
5468 BNX2X_F_CMD_AFEX_VIFLISTS);
5469 bnx2x_after_afex_vif_lists(bp, elem);
5470 goto next_spqe;
619c5cb6 5471 case EVENT_RING_OPCODE_FUNCTION_START:
51c1a580
MS		 5472 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5473 "got FUNC_START ramrod\n");
619c5cb6
VZ		 5474 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5475 break;
5476
5477 goto next_spqe;
5478
5479 case EVENT_RING_OPCODE_FUNCTION_STOP:
51c1a580
MS		 5480 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5481 "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 5482 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5483 break;
5484
5485 goto next_spqe;
eeed018c
MK		 5486
5487 case EVENT_RING_OPCODE_SET_TIMESYNC:
5488 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5489 "got set_timesync ramrod completion\n");
5490 if (f_obj->complete_cmd(bp, f_obj,
5491 BNX2X_F_CMD_SET_TIMESYNC))
5492 break;
5493 goto next_spqe;
523224a3
DK		 5494 }
5495
5496 switch (opcode | bp->state) {
619c5cb6
VZ		 5497 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5498 BNX2X_STATE_OPEN):
5499 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 5500 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 5501 cid = elem->message.data.eth_event.echo &
5502 BNX2X_SWCID_MASK;
d6cae238 5503 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
619c5cb6
VZ		 5504 cid);
5505 rss_raw->clear_pending(rss_raw);
523224a3
DK		 5506 break;
5507
619c5cb6
VZ		 5508 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5509 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5510 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 5511 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 5512 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5513 BNX2X_STATE_OPEN):
5514 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5515 BNX2X_STATE_DIAG):
5516 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5517 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5518 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
619c5cb6 5519 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 5520 break;
5521
619c5cb6
VZ		 5522 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5523 BNX2X_STATE_OPEN):
5524 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5525 BNX2X_STATE_DIAG):
5526 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5527 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5528 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 5529 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 5530 break;
5531
619c5cb6
VZ		 5532 case (EVENT_RING_OPCODE_FILTERS_RULES |
5533 BNX2X_STATE_OPEN):
5534 case (EVENT_RING_OPCODE_FILTERS_RULES |
5535 BNX2X_STATE_DIAG):
5536 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 5537 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5538 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 5539 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 5540 break;
5541 default:
5542 /* unknown event log error and continue */
619c5cb6
VZ		 5543 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5544 elem->message.opcode, bp->state);
523224a3
DK		 5545 }
5546next_spqe:
5547 spqe_cnt++;
5548 } /* for */
5549
4e857c58 5550 smp_mb__before_atomic();
6e30dd4e 5551 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 5552
5553 bp->eq_cons = sw_cons;
5554 bp->eq_prod = sw_prod;
5555 /* Make sure that above mem writes were issued towards the memory */
5556 smp_wmb();
5557
5558 /* update producer */
5559 bnx2x_update_eq_prod(bp, bp->eq_prod);
5560}
5561
a2fbb9ea
ET		 5562static void bnx2x_sp_task(struct work_struct *work)
5563{
1cf167f2 5564 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea 5565
fd1fc79d 5566 DP(BNX2X_MSG_SP, "sp task invoked\n");
a2fbb9ea 5567
16a5fd92 5568 /* make sure the atomic interrupt_occurred has been written */
fd1fc79d
AE		 5569 smp_rmb();
5570 if (atomic_read(&bp->interrupt_occurred)) {
a2fbb9ea 5571
fd1fc79d
AE		 5572 /* what work needs to be performed? */
5573 u16 status = bnx2x_update_dsb_idx(bp);
cdaa7cb8 5574
fd1fc79d
AE		 5575 DP(BNX2X_MSG_SP, "status %x\n", status);
5576 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5577 atomic_set(&bp->interrupt_occurred, 0);
5578
5579 /* HW attentions */
5580 if (status & BNX2X_DEF_SB_ATT_IDX) {
5581 bnx2x_attn_int(bp);
5582 status &= ~BNX2X_DEF_SB_ATT_IDX;
5583 }
5584
5585 /* SP events: STAT_QUERY and others */
5586 if (status & BNX2X_DEF_SB_IDX) {
5587 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 5588
55c11941 5589 if (FCOE_INIT(bp) &&
fd1fc79d
AE		 5590 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5591 /* Prevent local bottom-halves from running as
5592 * we are going to change the local NAPI list.
5593 */
5594 local_bh_disable();
5595 napi_schedule(&bnx2x_fcoe(bp, napi));
5596 local_bh_enable();
5597 }
5598
5599 /* Handle EQ completions */
5600 bnx2x_eq_int(bp);
5601 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5602 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5603
5604 status &= ~BNX2X_DEF_SB_IDX;
019dbb4c 5605 }
55c11941 5606
fd1fc79d
AE		 5607 /* if status is non zero then perhaps something went wrong */
5608 if (unlikely(status))
5609 DP(BNX2X_MSG_SP,
5610 "got an unknown interrupt! (status 0x%x)\n", status);
523224a3 5611
fd1fc79d
AE		 5612 /* ack status block only if something was actually handled */
5613 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5614 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
cdaa7cb8
VZ		 5615 }
5616
a3348722
BW		 5617 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5618 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5619 &bp->sp_state)) {
5620 bnx2x_link_report(bp);
5621 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5622 }
a2fbb9ea
ET		 5623}
5624
9f6c9258 5625irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 5626{
5627 struct net_device *dev = dev_instance;
5628 struct bnx2x *bp = netdev_priv(dev);
5629
523224a3
DK		 5630 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5631 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 5632
5633#ifdef BNX2X_STOP_ON_ERROR
5634 if (unlikely(bp->panic))
5635 return IRQ_HANDLED;
5636#endif
5637
55c11941 5638 if (CNIC_LOADED(bp)) {
993ac7b5
MC		 5639 struct cnic_ops *c_ops;
5640
5641 rcu_read_lock();
5642 c_ops = rcu_dereference(bp->cnic_ops);
5643 if (c_ops)
5644 c_ops->cnic_handler(bp->cnic_data, NULL);
5645 rcu_read_unlock();
5646 }
55c11941 5647
fd1fc79d
AE		 5648 /* schedule sp task to perform default status block work, ack
5649 * attentions and enable interrupts.
5650 */
5651 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 5652
5653 return IRQ_HANDLED;
5654}
5655
5656/* end of slow path */
5657
619c5cb6
VZ		 5658void bnx2x_drv_pulse(struct bnx2x *bp)
5659{
5660 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5661 bp->fw_drv_pulse_wr_seq);
5662}
5663
a2fbb9ea
ET		 5664static void bnx2x_timer(unsigned long data)
5665{
5666 struct bnx2x *bp = (struct bnx2x *) data;
5667
5668 if (!netif_running(bp->dev))
5669 return;
5670
67c431a5
AE		 5671 if (IS_PF(bp) &&
5672 !BP_NOMCP(bp)) {
f2e0899f 5673 int mb_idx = BP_FW_MB_IDX(bp);
4c868664
EG		 5674 u16 drv_pulse;
5675 u16 mcp_pulse;
a2fbb9ea
ET		 5676
5677 ++bp->fw_drv_pulse_wr_seq;
5678 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
a2fbb9ea 5679 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 5680 bnx2x_drv_pulse(bp);
a2fbb9ea 5681
f2e0899f 5682 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 5683 MCP_PULSE_SEQ_MASK);
5684 /* The delta between driver pulse and mcp response
4c868664
EG		 5685 * should not get too big. If the MFW is more than 5 pulses
5686 * behind, we should worry about it enough to generate an error
5687 * log.
a2fbb9ea 5688 */
4c868664
EG		 5689 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5690 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
a2fbb9ea 5691 drv_pulse, mcp_pulse);
a2fbb9ea
ET		 5692 }
5693
f34d28ea 5694 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 5695 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 5696
abc5a021 5697 /* sample pf vf bulletin board for new posts from pf */
37173488
YM		 5698 if (IS_VF(bp))
5699 bnx2x_timer_sriov(bp);
78c3bcc5 5700
a2fbb9ea
ET		 5701 mod_timer(&bp->timer, jiffies + bp->current_interval);
5702}
5703
5704/* end of Statistics */
5705
5706/* nic init */
5707
5708/*
5709 * nic init service functions
5710 */
5711
1191cb83 5712static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 5713{
523224a3
DK		 5714 u32 i;
5715 if (!(len%4) && !(addr%4))
5716 for (i = 0; i < len; i += 4)
5717 REG_WR(bp, addr + i, fill);
5718 else
5719 for (i = 0; i < len; i++)
5720 REG_WR8(bp, addr + i, fill);
34f80b04
EG		 5721}
5722
523224a3 5723/* helper: writes FP SP data to FW - data_size in dwords */
1191cb83
ED		 5724static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5725 int fw_sb_id,
5726 u32 *sb_data_p,
5727 u32 data_size)
34f80b04 5728{
a2fbb9ea 5729 int index;
523224a3
DK		 5730 for (index = 0; index < data_size; index++)
5731 REG_WR(bp, BAR_CSTRORM_INTMEM +
5732 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5733 sizeof(u32)*index,
5734 *(sb_data_p + index));
5735}
a2fbb9ea 5736
1191cb83 5737static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
523224a3
DK		 5738{
5739 u32 *sb_data_p;
5740 u32 data_size = 0;
f2e0899f 5741 struct hc_status_block_data_e2 sb_data_e2;
523224a3 5742 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 5743
523224a3 5744 /* disable the function first */
619c5cb6 5745 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5746 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5747 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 5748 sb_data_e2.common.p_func.vf_valid = false;
5749 sb_data_p = (u32 *)&sb_data_e2;
5750 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5751 } else {
5752 memset(&sb_data_e1x, 0,
5753 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5754 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 5755 sb_data_e1x.common.p_func.vf_valid = false;
5756 sb_data_p = (u32 *)&sb_data_e1x;
5757 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5758 }
523224a3 5759 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 5760
523224a3
DK		 5761 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5762 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5763 CSTORM_STATUS_BLOCK_SIZE);
5764 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5765 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5766 CSTORM_SYNC_BLOCK_SIZE);
5767}
34f80b04 5768
523224a3 5769/* helper: writes SP SB data to FW */
1191cb83 5770static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
523224a3
DK		 5771 struct hc_sp_status_block_data *sp_sb_data)
5772{
5773 int func = BP_FUNC(bp);
5774 int i;
5775 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5776 REG_WR(bp, BAR_CSTRORM_INTMEM +
5777 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5778 i*sizeof(u32),
5779 *((u32 *)sp_sb_data + i));
34f80b04
EG		 5780}
5781
1191cb83 5782static void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 5783{
5784 int func = BP_FUNC(bp);
523224a3
DK		 5785 struct hc_sp_status_block_data sp_sb_data;
5786 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 5787
619c5cb6 5788 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 5789 sp_sb_data.p_func.vf_valid = false;
5790
5791 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5792
5793 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5794 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5795 CSTORM_SP_STATUS_BLOCK_SIZE);
5796 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5797 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5798 CSTORM_SP_SYNC_BLOCK_SIZE);
523224a3
DK		 5799}
5800
1191cb83 5801static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
523224a3
DK		 5802 int igu_sb_id, int igu_seg_id)
5803{
5804 hc_sm->igu_sb_id = igu_sb_id;
5805 hc_sm->igu_seg_id = igu_seg_id;
5806 hc_sm->timer_value = 0xFF;
5807 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 5808}
5809
150966ad 5810/* allocates state machine ids. */
1191cb83 5811static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
150966ad
AE		 5812{
5813 /* zero out state machine indices */
5814 /* rx indices */
5815 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5816
5817 /* tx indices */
5818 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5819 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5820 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5821 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5822
5823 /* map indices */
5824 /* rx indices */
5825 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5826 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5827
5828 /* tx indices */
5829 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5830 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5831 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5832 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5833 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5834 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5835 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5836 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5837}
5838
b93288d5 5839void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 5840 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 5841{
523224a3
DK		 5842 int igu_seg_id;
5843
f2e0899f 5844 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 5845 struct hc_status_block_data_e1x sb_data_e1x;
5846 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 5847 int data_size;
5848 u32 *sb_data_p;
5849
f2e0899f
DK		 5850 if (CHIP_INT_MODE_IS_BC(bp))
5851 igu_seg_id = HC_SEG_ACCESS_NORM;
5852 else
5853 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 5854
5855 bnx2x_zero_fp_sb(bp, fw_sb_id);
5856
619c5cb6 5857 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5858 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5859 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 5860 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5861 sb_data_e2.common.p_func.vf_id = vfid;
5862 sb_data_e2.common.p_func.vf_valid = vf_valid;
5863 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5864 sb_data_e2.common.same_igu_sb_1b = true;
5865 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5866 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5867 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 5868 sb_data_p = (u32 *)&sb_data_e2;
5869 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 5870 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 5871 } else {
5872 memset(&sb_data_e1x, 0,
5873 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5874 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 5875 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5876 sb_data_e1x.common.p_func.vf_id = 0xff;
5877 sb_data_e1x.common.p_func.vf_valid = false;
5878 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5879 sb_data_e1x.common.same_igu_sb_1b = true;
5880 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5881 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5882 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 5883 sb_data_p = (u32 *)&sb_data_e1x;
5884 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 5885 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 5886 }
523224a3
DK		 5887
5888 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5889 igu_sb_id, igu_seg_id);
5890 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5891 igu_sb_id, igu_seg_id);
5892
51c1a580 5893 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
523224a3 5894
86564c3f 5895 /* write indices to HW - PCI guarantees endianity of regpairs */
523224a3
DK		 5896 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5897}
5898
619c5cb6 5899static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 5900 u16 tx_usec, u16 rx_usec)
5901{
6383c0b3 5902 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 5903 false, rx_usec);
6383c0b3
AE		 5904 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5905 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5906 tx_usec);
5907 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5908 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5909 tx_usec);
5910 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5911 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5912 tx_usec);
523224a3 5913}
f2e0899f 5914
523224a3
DK		 5915static void bnx2x_init_def_sb(struct bnx2x *bp)
5916{
5917 struct host_sp_status_block *def_sb = bp->def_status_blk;
5918 dma_addr_t mapping = bp->def_status_blk_mapping;
5919 int igu_sp_sb_index;
5920 int igu_seg_id;
34f80b04
EG		 5921 int port = BP_PORT(bp);
5922 int func = BP_FUNC(bp);
f2eaeb58 5923 int reg_offset, reg_offset_en5;
a2fbb9ea 5924 u64 section;
523224a3
DK		 5925 int index;
5926 struct hc_sp_status_block_data sp_sb_data;
5927 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5928
f2e0899f
DK		 5929 if (CHIP_INT_MODE_IS_BC(bp)) {
5930 igu_sp_sb_index = DEF_SB_IGU_ID;
5931 igu_seg_id = HC_SEG_ACCESS_DEF;
5932 } else {
5933 igu_sp_sb_index = bp->igu_dsb_id;
5934 igu_seg_id = IGU_SEG_ACCESS_DEF;
5935 }
a2fbb9ea
ET		 5936
5937 /* ATTN */
523224a3 5938 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 5939 atten_status_block);
523224a3 5940 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 5941
49d66772
ET		 5942 bp->attn_state = 0;
5943
a2fbb9ea
ET		 5944 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5945 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 5946 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5947 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 5948 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 5949 int sindex;
5950 /* take care of sig[0]..sig[4] */
5951 for (sindex = 0; sindex < 4; sindex++)
5952 bp->attn_group[index].sig[sindex] =
5953 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 5954
619c5cb6 5955 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5956 /*
5957 * enable5 is separate from the rest of the registers,
5958 * and therefore the address skip is 4
5959 * and not 16 between the different groups
5960 */
5961 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 5962 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 5963 else
5964 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 5965 }
5966
f2e0899f
DK		 5967 if (bp->common.int_block == INT_BLOCK_HC) {
5968 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5969 HC_REG_ATTN_MSG0_ADDR_L);
5970
5971 REG_WR(bp, reg_offset, U64_LO(section));
5972 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 5973 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5974 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5975 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5976 }
a2fbb9ea 5977
523224a3
DK		 5978 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5979 sp_sb);
a2fbb9ea 5980
523224a3 5981 bnx2x_zero_sp_sb(bp);
a2fbb9ea 5982
86564c3f 5983 /* PCI guarantees endianity of regpairs */
619c5cb6 5984 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 5985 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5986 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5987 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5988 sp_sb_data.igu_seg_id = igu_seg_id;
5989 sp_sb_data.p_func.pf_id = func;
f2e0899f 5990 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 5991 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 5992
523224a3 5993 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 5994
523224a3 5995 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 5996}
5997
9f6c9258 5998void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 5999{
a2fbb9ea
ET		 6000 int i;
6001
ec6ba945 6002 for_each_eth_queue(bp, i)
523224a3 6003 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 6004 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 6005}
6006
a2fbb9ea
ET		 6007static void bnx2x_init_sp_ring(struct bnx2x *bp)
6008{
a2fbb9ea 6009 spin_lock_init(&bp->spq_lock);
6e30dd4e 6010 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 6011
a2fbb9ea 6012 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 6013 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6014 bp->spq_prod_bd = bp->spq;
6015 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 6016}
6017
523224a3 6018static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 6019{
6020 int i;
523224a3
DK		 6021 for (i = 1; i <= NUM_EQ_PAGES; i++) {
6022 union event_ring_elem *elem =
6023 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 6024
523224a3
DK		 6025 elem->next_page.addr.hi =
6026 cpu_to_le32(U64_HI(bp->eq_mapping +
6027 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6028 elem->next_page.addr.lo =
6029 cpu_to_le32(U64_LO(bp->eq_mapping +
6030 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 6031 }
523224a3
DK		 6032 bp->eq_cons = 0;
6033 bp->eq_prod = NUM_EQ_DESC;
6034 bp->eq_cons_sb = BNX2X_EQ_INDEX;
16a5fd92 6035 /* we want a warning message before it gets wrought... */
6e30dd4e
VZ		 6036 atomic_set(&bp->eq_spq_left,
6037 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 6038}
6039
619c5cb6 6040/* called with netif_addr_lock_bh() */
a8f47eb7 6041static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6042 unsigned long rx_mode_flags,
6043 unsigned long rx_accept_flags,
6044 unsigned long tx_accept_flags,
6045 unsigned long ramrod_flags)
ab532cf3 6046{
619c5cb6
VZ		 6047 struct bnx2x_rx_mode_ramrod_params ramrod_param;
6048 int rc;
6049
6050 memset(&ramrod_param, 0, sizeof(ramrod_param));
6051
6052 /* Prepare ramrod parameters */
6053 ramrod_param.cid = 0;
6054 ramrod_param.cl_id = cl_id;
6055 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6056 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 6057
619c5cb6
VZ		 6058 ramrod_param.pstate = &bp->sp_state;
6059 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 6060
619c5cb6
VZ		 6061 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6062 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6063
6064 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6065
6066 ramrod_param.ramrod_flags = ramrod_flags;
6067 ramrod_param.rx_mode_flags = rx_mode_flags;
6068
6069 ramrod_param.rx_accept_flags = rx_accept_flags;
6070 ramrod_param.tx_accept_flags = tx_accept_flags;
6071
6072 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6073 if (rc < 0) {
6074 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
924d75ab 6075 return rc;
619c5cb6 6076 }
924d75ab
YM		 6077
6078 return 0;
a2fbb9ea
ET		 6079}
6080
86564c3f
YM		 6081static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6082 unsigned long *rx_accept_flags,
6083 unsigned long *tx_accept_flags)
471de716 6084{
924d75ab
YM		 6085 /* Clear the flags first */
6086 *rx_accept_flags = 0;
6087 *tx_accept_flags = 0;
619c5cb6 6088
924d75ab 6089 switch (rx_mode) {
619c5cb6
VZ		 6090 case BNX2X_RX_MODE_NONE:
6091 /*
6092 * 'drop all' supersedes any accept flags that may have been
6093 * passed to the function.
6094 */
6095 break;
6096 case BNX2X_RX_MODE_NORMAL:
924d75ab
YM		 6097 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6098 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6099 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6100
6101 /* internal switching mode */
924d75ab
YM		 6102 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6103 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6104 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6105
6106 break;
6107 case BNX2X_RX_MODE_ALLMULTI:
924d75ab
YM		 6108 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6109 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6110 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6111
6112 /* internal switching mode */
924d75ab
YM		 6113 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6114 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6115 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6116
6117 break;
6118 case BNX2X_RX_MODE_PROMISC:
16a5fd92 6119 /* According to definition of SI mode, iface in promisc mode
619c5cb6
VZ		 6120 * should receive matched and unmatched (in resolution of port)
6121 * unicast packets.
6122 */
924d75ab
YM		 6123 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6124 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6125 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6126 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6127
6128 /* internal switching mode */
924d75ab
YM		 6129 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6130 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6131
6132 if (IS_MF_SI(bp))
924d75ab 6133 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
619c5cb6 6134 else
924d75ab 6135 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
619c5cb6
VZ		 6136
6137 break;
6138 default:
924d75ab
YM		 6139 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6140 return -EINVAL;
619c5cb6 6141 }
de832a55 6142
924d75ab 6143 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
0c23ad37 6144 if (rx_mode != BNX2X_RX_MODE_NONE) {
924d75ab
YM		 6145 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6146 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
34f80b04
EG		 6147 }
6148
924d75ab
YM		 6149 return 0;
6150}
6151
6152/* called with netif_addr_lock_bh() */
a8f47eb7 6153static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
924d75ab
YM		 6154{
6155 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6156 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6157 int rc;
6158
6159 if (!NO_FCOE(bp))
6160 /* Configure rx_mode of FCoE Queue */
6161 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6162
6163 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6164 &tx_accept_flags);
6165 if (rc)
6166 return rc;
6167
619c5cb6
VZ		 6168 __set_bit(RAMROD_RX, &ramrod_flags);
6169 __set_bit(RAMROD_TX, &ramrod_flags);
6170
924d75ab
YM		 6171 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6172 rx_accept_flags, tx_accept_flags,
6173 ramrod_flags);
619c5cb6
VZ		 6174}
6175
6176static void bnx2x_init_internal_common(struct bnx2x *bp)
6177{
6178 int i;
6179
523224a3
DK		 6180 /* Zero this manually as its initialization is
6181 currently missing in the initTool */
6182 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 6183 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 6184 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 6185 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6186 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6187 CHIP_INT_MODE_IS_BC(bp) ?
6188 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6189 }
523224a3 6190}
8a1c38d1 6191
471de716
EG		 6192static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6193{
6194 switch (load_code) {
6195 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 6196 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 6197 bnx2x_init_internal_common(bp);
6198 /* no break */
6199
6200 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 6201 /* nothing to do */
471de716
EG		 6202 /* no break */
6203
6204 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 6205 /* internal memory per function is
6206 initialized inside bnx2x_pf_init */
471de716
EG		 6207 break;
6208
6209 default:
6210 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6211 break;
6212 }
6213}
6214
619c5cb6 6215static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 6216{
55c11941 6217 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6 6218}
523224a3 6219
619c5cb6
VZ		 6220static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6221{
55c11941 6222 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6
VZ		 6223}
6224
1191cb83 6225static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
619c5cb6
VZ		 6226{
6227 if (CHIP_IS_E1x(fp->bp))
6228 return BP_L_ID(fp->bp) + fp->index;
6229 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6230 return bnx2x_fp_igu_sb_id(fp);
6231}
6232
6383c0b3 6233static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 6234{
6235 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 6236 u8 cos;
619c5cb6 6237 unsigned long q_type = 0;
6383c0b3 6238 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 6239 fp->rx_queue = fp_idx;
b3b83c3f 6240 fp->cid = fp_idx;
619c5cb6
VZ		 6241 fp->cl_id = bnx2x_fp_cl_id(fp);
6242 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6243 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 6244 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 6245 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6246
523224a3 6247 /* init shortcut */
619c5cb6 6248 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
7a752993 6249
16a5fd92 6250 /* Setup SB indices */
523224a3 6251 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 6252
619c5cb6
VZ		 6253 /* Configure Queue State object */
6254 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6255 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 6256
6257 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6258
6259 /* init tx data */
6260 for_each_cos_in_tx_queue(fp, cos) {
65565884
MS		 6261 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6262 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6263 FP_COS_TO_TXQ(fp, cos, bp),
6264 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6265 cids[cos] = fp->txdata_ptr[cos]->cid;
6383c0b3
AE		 6266 }
6267
ad5afc89
AE		 6268 /* nothing more for vf to do here */
6269 if (IS_VF(bp))
6270 return;
6271
6272 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6273 fp->fw_sb_id, fp->igu_sb_id);
6274 bnx2x_update_fpsb_idx(fp);
15192a8c
BW		 6275 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6276 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6383c0b3 6277 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 6278
6279 /**
6280 * Configure classification DBs: Always enable Tx switching
6281 */
6282 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6283
ad5afc89
AE		 6284 DP(NETIF_MSG_IFUP,
6285 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6286 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6287 fp->igu_sb_id);
523224a3
DK		 6288}
6289
1191cb83
ED		 6290static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6291{
6292 int i;
6293
6294 for (i = 1; i <= NUM_TX_RINGS; i++) {
6295 struct eth_tx_next_bd *tx_next_bd =
6296 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6297
6298 tx_next_bd->addr_hi =
6299 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6300 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6301 tx_next_bd->addr_lo =
6302 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6303 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6304 }
6305
639d65b8
YM		 6306 *txdata->tx_cons_sb = cpu_to_le16(0);
6307
1191cb83
ED		 6308 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6309 txdata->tx_db.data.zero_fill1 = 0;
6310 txdata->tx_db.data.prod = 0;
6311
6312 txdata->tx_pkt_prod = 0;
6313 txdata->tx_pkt_cons = 0;
6314 txdata->tx_bd_prod = 0;
6315 txdata->tx_bd_cons = 0;
6316 txdata->tx_pkt = 0;
6317}
6318
55c11941
MS		 6319static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6320{
6321 int i;
6322
6323 for_each_tx_queue_cnic(bp, i)
6324 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6325}
d76a6111 6326
1191cb83
ED		 6327static void bnx2x_init_tx_rings(struct bnx2x *bp)
6328{
6329 int i;
6330 u8 cos;
6331
55c11941 6332 for_each_eth_queue(bp, i)
1191cb83 6333 for_each_cos_in_tx_queue(&bp->fp[i], cos)
65565884 6334 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
1191cb83
ED		 6335}
6336
a8f47eb7 6337static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6338{
6339 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6340 unsigned long q_type = 0;
6341
6342 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6343 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6344 BNX2X_FCOE_ETH_CL_ID_IDX);
6345 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6346 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6347 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6348 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6349 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6350 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6351 fp);
6352
6353 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6354
6355 /* qZone id equals to FW (per path) client id */
6356 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6357 /* init shortcut */
6358 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6359 bnx2x_rx_ustorm_prods_offset(fp);
6360
6361 /* Configure Queue State object */
6362 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6363 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6364
6365 /* No multi-CoS for FCoE L2 client */
6366 BUG_ON(fp->max_cos != 1);
6367
6368 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6369 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6370 bnx2x_sp_mapping(bp, q_rdata), q_type);
6371
6372 DP(NETIF_MSG_IFUP,
6373 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6374 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6375 fp->igu_sb_id);
6376}
6377
55c11941 6378void bnx2x_nic_init_cnic(struct bnx2x *bp)
a2fbb9ea 6379{
ec6ba945
VZ		 6380 if (!NO_FCOE(bp))
6381 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 6382
6383 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6384 BNX2X_VF_ID_INVALID, false,
619c5cb6 6385 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 6386
55c11941
MS		 6387 /* ensure status block indices were read */
6388 rmb();
6389 bnx2x_init_rx_rings_cnic(bp);
6390 bnx2x_init_tx_rings_cnic(bp);
6391
6392 /* flush all */
6393 mb();
6394 mmiowb();
6395}
a2fbb9ea 6396
ecf01c22 6397void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
55c11941
MS		 6398{
6399 int i;
6400
ecf01c22 6401 /* Setup NIC internals and enable interrupts */
55c11941
MS		 6402 for_each_eth_queue(bp, i)
6403 bnx2x_init_eth_fp(bp, i);
ad5afc89
AE		 6404
6405 /* ensure status block indices were read */
6406 rmb();
6407 bnx2x_init_rx_rings(bp);
6408 bnx2x_init_tx_rings(bp);
6409
ecf01c22
YM		 6410 if (IS_PF(bp)) {
6411 /* Initialize MOD_ABS interrupts */
6412 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6413 bp->common.shmem_base,
6414 bp->common.shmem2_base, BP_PORT(bp));
ad5afc89 6415
ecf01c22
YM		 6416 /* initialize the default status block and sp ring */
6417 bnx2x_init_def_sb(bp);
6418 bnx2x_update_dsb_idx(bp);
6419 bnx2x_init_sp_ring(bp);
3cdeec22
YM		 6420 } else {
6421 bnx2x_memset_stats(bp);
ecf01c22
YM		 6422 }
6423}
16119785 6424
ecf01c22
YM		 6425void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6426{
523224a3 6427 bnx2x_init_eq_ring(bp);
471de716 6428 bnx2x_init_internal(bp, load_code);
523224a3 6429 bnx2x_pf_init(bp);
0ef00459
EG		 6430 bnx2x_stats_init(bp);
6431
0ef00459
EG		 6432 /* flush all before enabling interrupts */
6433 mb();
6434 mmiowb();
6435
615f8fd9 6436 bnx2x_int_enable(bp);
eb8da205
EG		 6437
6438 /* Check for SPIO5 */
6439 bnx2x_attn_int_deasserted0(bp,
6440 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6441 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 6442}
6443
ecf01c22 6444/* gzip service functions */
a2fbb9ea
ET		 6445static int bnx2x_gunzip_init(struct bnx2x *bp)
6446{
1a983142
FT		 6447 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6448 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 6449 if (bp->gunzip_buf == NULL)
6450 goto gunzip_nomem1;
6451
6452 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6453 if (bp->strm == NULL)
6454 goto gunzip_nomem2;
6455
7ab24bfd 6456 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 6457 if (bp->strm->workspace == NULL)
6458 goto gunzip_nomem3;
6459
6460 return 0;
6461
6462gunzip_nomem3:
6463 kfree(bp->strm);
6464 bp->strm = NULL;
6465
6466gunzip_nomem2:
1a983142
FT		 6467 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6468 bp->gunzip_mapping);
a2fbb9ea
ET		 6469 bp->gunzip_buf = NULL;
6470
6471gunzip_nomem1:
51c1a580 6472 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
a2fbb9ea
ET		 6473 return -ENOMEM;
6474}
6475
6476static void bnx2x_gunzip_end(struct bnx2x *bp)
6477{
b3b83c3f 6478 if (bp->strm) {
7ab24bfd 6479 vfree(bp->strm->workspace);
b3b83c3f
DK		 6480 kfree(bp->strm);
6481 bp->strm = NULL;
6482 }
a2fbb9ea
ET		 6483
6484 if (bp->gunzip_buf) {
1a983142
FT		 6485 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6486 bp->gunzip_mapping);
a2fbb9ea
ET		 6487 bp->gunzip_buf = NULL;
6488 }
6489}
6490
94a78b79 6491static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 6492{
6493 int n, rc;
6494
6495 /* check gzip header */
94a78b79
VZ		 6496 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6497 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 6498 return -EINVAL;
94a78b79 6499 }
a2fbb9ea
ET		 6500
6501 n = 10;
6502
34f80b04 6503#define FNAME 0x8
a2fbb9ea
ET		 6504
6505 if (zbuf[3] & FNAME)
6506 while ((zbuf[n++] != 0) && (n < len));
6507
94a78b79 6508 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 6509 bp->strm->avail_in = len - n;
6510 bp->strm->next_out = bp->gunzip_buf;
6511 bp->strm->avail_out = FW_BUF_SIZE;
6512
6513 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6514 if (rc != Z_OK)
6515 return rc;
6516
6517 rc = zlib_inflate(bp->strm, Z_FINISH);
6518 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 6519 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6520 bp->strm->msg);
a2fbb9ea
ET		 6521
6522 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6523 if (bp->gunzip_outlen & 0x3)
51c1a580
MS		 6524 netdev_err(bp->dev,
6525 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
cdaa7cb8 6526 bp->gunzip_outlen);
a2fbb9ea
ET		 6527 bp->gunzip_outlen >>= 2;
6528
6529 zlib_inflateEnd(bp->strm);
6530
6531 if (rc == Z_STREAM_END)
6532 return 0;
6533
6534 return rc;
6535}
6536
6537/* nic load/unload */
6538
6539/*
34f80b04 6540 * General service functions
a2fbb9ea
ET		 6541 */
6542
6543/* send a NIG loopback debug packet */
6544static void bnx2x_lb_pckt(struct bnx2x *bp)
6545{
a2fbb9ea 6546 u32 wb_write[3];
a2fbb9ea
ET		 6547
6548 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 6549 wb_write[0] = 0x55555555;
6550 wb_write[1] = 0x55555555;
34f80b04 6551 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 6552 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6553
6554 /* NON-IP protocol */
a2fbb9ea
ET		 6555 wb_write[0] = 0x09000000;
6556 wb_write[1] = 0x55555555;
34f80b04 6557 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 6558 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6559}
6560
6561/* some of the internal memories
6562 * are not directly readable from the driver
6563 * to test them we send debug packets
6564 */
6565static int bnx2x_int_mem_test(struct bnx2x *bp)
6566{
6567 int factor;
6568 int count, i;
6569 u32 val = 0;
6570
ad8d3948 6571 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 6572 factor = 120;
ad8d3948
EG		 6573 else if (CHIP_REV_IS_EMUL(bp))
6574 factor = 200;
6575 else
a2fbb9ea 6576 factor = 1;
a2fbb9ea 6577
a2fbb9ea
ET		 6578 /* Disable inputs of parser neighbor blocks */
6579 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6580 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6581 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6582 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6583
6584 /* Write 0 to parser credits for CFC search request */
6585 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6586
6587 /* send Ethernet packet */
6588 bnx2x_lb_pckt(bp);
6589
6590 /* TODO do i reset NIG statistic? */
6591 /* Wait until NIG register shows 1 packet of size 0x10 */
6592 count = 1000 * factor;
6593 while (count) {
34f80b04 6594
a2fbb9ea
ET		 6595 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6596 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6597 if (val == 0x10)
6598 break;
6599
639d65b8 6600 usleep_range(10000, 20000);
a2fbb9ea
ET		 6601 count--;
6602 }
6603 if (val != 0x10) {
6604 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6605 return -1;
6606 }
6607
6608 /* Wait until PRS register shows 1 packet */
6609 count = 1000 * factor;
6610 while (count) {
6611 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 6612 if (val == 1)
6613 break;
6614
639d65b8 6615 usleep_range(10000, 20000);
a2fbb9ea
ET		 6616 count--;
6617 }
6618 if (val != 0x1) {
6619 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6620 return -2;
6621 }
6622
6623 /* Reset and init BRB, PRS */
34f80b04 6624 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 6625 msleep(50);
34f80b04 6626 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 6627 msleep(50);
619c5cb6
VZ		 6628 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6629 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 6630
6631 DP(NETIF_MSG_HW, "part2\n");
6632
6633 /* Disable inputs of parser neighbor blocks */
6634 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6635 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6636 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6637 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6638
6639 /* Write 0 to parser credits for CFC search request */
6640 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6641
6642 /* send 10 Ethernet packets */
6643 for (i = 0; i < 10; i++)
6644 bnx2x_lb_pckt(bp);
6645
6646 /* Wait until NIG register shows 10 + 1
6647 packets of size 11*0x10 = 0xb0 */
6648 count = 1000 * factor;
6649 while (count) {
34f80b04 6650
a2fbb9ea
ET		 6651 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6652 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6653 if (val == 0xb0)
6654 break;
6655
639d65b8 6656 usleep_range(10000, 20000);
a2fbb9ea
ET		 6657 count--;
6658 }
6659 if (val != 0xb0) {
6660 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6661 return -3;
6662 }
6663
6664 /* Wait until PRS register shows 2 packets */
6665 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6666 if (val != 2)
6667 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6668
6669 /* Write 1 to parser credits for CFC search request */
6670 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6671
6672 /* Wait until PRS register shows 3 packets */
6673 msleep(10 * factor);
6674 /* Wait until NIG register shows 1 packet of size 0x10 */
6675 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6676 if (val != 3)
6677 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6678
6679 /* clear NIG EOP FIFO */
6680 for (i = 0; i < 11; i++)
6681 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6682 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6683 if (val != 1) {
6684 BNX2X_ERR("clear of NIG failed\n");
6685 return -4;
6686 }
6687
6688 /* Reset and init BRB, PRS, NIG */
6689 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6690 msleep(50);
6691 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6692 msleep(50);
619c5cb6
VZ		 6693 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6694 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
55c11941
MS		 6695 if (!CNIC_SUPPORT(bp))
6696 /* set NIC mode */
6697 REG_WR(bp, PRS_REG_NIC_MODE, 1);
a2fbb9ea
ET		 6698
6699 /* Enable inputs of parser neighbor blocks */
6700 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6701 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6702 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 6703 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 6704
6705 DP(NETIF_MSG_HW, "done\n");
6706
6707 return 0; /* OK */
6708}
6709
4a33bc03 6710static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea 6711{
b343d002
YM		 6712 u32 val;
6713
a2fbb9ea 6714 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 6715 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6716 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6717 else
6718 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 6719 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6720 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 6721 /*
6722 * mask read length error interrupts in brb for parser
6723 * (parsing unit and 'checksum and crc' unit)
6724 * these errors are legal (PU reads fixed length and CAC can cause
6725 * read length error on truncated packets)
6726 */
6727 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 6728 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6729 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6730 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6731 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6732 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 6733/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6734/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6735 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6736 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6737 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 6738/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6739/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6740 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6741 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6742 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6743 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 6744/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6745/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 6746
b343d002
YM		 6747 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6748 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6749 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6750 if (!CHIP_IS_E1x(bp))
6751 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6752 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6753 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6754
a2fbb9ea
ET		 6755 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6756 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6757 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 6758/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 6759
6760 if (!CHIP_IS_E1x(bp))
6761 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6762 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6763
a2fbb9ea
ET		 6764 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6765 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 6766/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 6767 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 6768}
6769
81f75bbf
EG		 6770static void bnx2x_reset_common(struct bnx2x *bp)
6771{
619c5cb6
VZ		 6772 u32 val = 0x1400;
6773
81f75bbf
EG		 6774 /* reset_common */
6775 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6776 0xd3ffff7f);
619c5cb6
VZ		 6777
6778 if (CHIP_IS_E3(bp)) {
6779 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6780 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6781 }
6782
6783 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6784}
6785
6786static void bnx2x_setup_dmae(struct bnx2x *bp)
6787{
6788 bp->dmae_ready = 0;
6789 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 6790}
6791
573f2035
EG		 6792static void bnx2x_init_pxp(struct bnx2x *bp)
6793{
6794 u16 devctl;
6795 int r_order, w_order;
6796
2a80eebc 6797 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 6798 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6799 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6800 if (bp->mrrs == -1)
6801 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6802 else {
6803 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6804 r_order = bp->mrrs;
6805 }
6806
6807 bnx2x_init_pxp_arb(bp, r_order, w_order);
6808}
fd4ef40d
EG		 6809
6810static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6811{
2145a920 6812 int is_required;
fd4ef40d 6813 u32 val;
2145a920 6814 int port;
fd4ef40d 6815
2145a920
VZ		 6816 if (BP_NOMCP(bp))
6817 return;
6818
6819 is_required = 0;
fd4ef40d
EG		 6820 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6821 SHARED_HW_CFG_FAN_FAILURE_MASK;
6822
6823 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6824 is_required = 1;
6825
6826 /*
6827 * The fan failure mechanism is usually related to the PHY type since
6828 * the power consumption of the board is affected by the PHY. Currently,
6829 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6830 */
6831 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6832 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 6833 is_required |=
d90d96ba
YR		 6834 bnx2x_fan_failure_det_req(
6835 bp,
6836 bp->common.shmem_base,
a22f0788 6837 bp->common.shmem2_base,
d90d96ba 6838 port);
fd4ef40d
EG		 6839 }
6840
6841 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6842
6843 if (is_required == 0)
6844 return;
6845
6846 /* Fan failure is indicated by SPIO 5 */
d6d99a3f 6847 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
fd4ef40d
EG		 6848
6849 /* set to active low mode */
6850 val = REG_RD(bp, MISC_REG_SPIO_INT);
d6d99a3f 6851 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 6852 REG_WR(bp, MISC_REG_SPIO_INT, val);
6853
6854 /* enable interrupt to signal the IGU */
6855 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 6856 val |= MISC_SPIO_SPIO5;
fd4ef40d
EG		 6857 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6858}
6859
c9ee9206 6860void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 6861{
6862 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6863 val &= ~IGU_PF_CONF_FUNC_EN;
6864
6865 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6866 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6867 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6868}
6869
1191cb83 6870static void bnx2x__common_init_phy(struct bnx2x *bp)
619c5cb6
VZ		 6871{
6872 u32 shmem_base[2], shmem2_base[2];
b884d95b
YR		 6873 /* Avoid common init in case MFW supports LFA */
6874 if (SHMEM2_RD(bp, size) >
6875 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6876 return;
619c5cb6
VZ		 6877 shmem_base[0] = bp->common.shmem_base;
6878 shmem2_base[0] = bp->common.shmem2_base;
6879 if (!CHIP_IS_E1x(bp)) {
6880 shmem_base[1] =
6881 SHMEM2_RD(bp, other_shmem_base_addr);
6882 shmem2_base[1] =
6883 SHMEM2_RD(bp, other_shmem2_base_addr);
6884 }
6885 bnx2x_acquire_phy_lock(bp);
6886 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6887 bp->common.chip_id);
6888 bnx2x_release_phy_lock(bp);
6889}
6890
6891/**
6892 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6893 *
6894 * @bp: driver handle
6895 */
6896static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 6897{
619c5cb6 6898 u32 val;
a2fbb9ea 6899
51c1a580 6900 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 6901
2031bd3a 6902 /*
2de67439 6903 * take the RESET lock to protect undi_unload flow from accessing
2031bd3a
DK		 6904 * registers while we're resetting the chip
6905 */
7a06a122 6906 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6907
81f75bbf 6908 bnx2x_reset_common(bp);
34f80b04 6909 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 6910
619c5cb6
VZ		 6911 val = 0xfffc;
6912 if (CHIP_IS_E3(bp)) {
6913 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6914 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6915 }
6916 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6917
7a06a122 6918 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6919
619c5cb6 6920 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 6921
619c5cb6
VZ		 6922 if (!CHIP_IS_E1x(bp)) {
6923 u8 abs_func_id;
f2e0899f
DK		 6924
6925 /**
6926 * 4-port mode or 2-port mode we need to turn of master-enable
6927 * for everyone, after that, turn it back on for self.
6928 * so, we disregard multi-function or not, and always disable
6929 * for all functions on the given path, this means 0,2,4,6 for
6930 * path 0 and 1,3,5,7 for path 1
6931 */
619c5cb6
VZ		 6932 for (abs_func_id = BP_PATH(bp);
6933 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6934 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 6935 REG_WR(bp,
6936 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6937 1);
6938 continue;
6939 }
6940
619c5cb6 6941 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 6942 /* clear pf enable */
6943 bnx2x_pf_disable(bp);
6944 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6945 }
6946 }
a2fbb9ea 6947
619c5cb6 6948 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 6949 if (CHIP_IS_E1(bp)) {
6950 /* enable HW interrupt from PXP on USDM overflow
6951 bit 16 on INT_MASK_0 */
6952 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6953 }
a2fbb9ea 6954
619c5cb6 6955 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 6956 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 6957
6958#ifdef __BIG_ENDIAN
34f80b04
EG		 6959 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6960 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6961 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6962 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6963 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 6964 /* make sure this value is 0 */
6965 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 6966
6967/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6968 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6969 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6970 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6971 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 6972#endif
6973
523224a3
DK		 6974 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6975
34f80b04
EG		 6976 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6977 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 6978
34f80b04
EG		 6979 /* let the HW do it's magic ... */
6980 msleep(100);
6981 /* finish PXP init */
6982 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6983 if (val != 1) {
6984 BNX2X_ERR("PXP2 CFG failed\n");
6985 return -EBUSY;
6986 }
6987 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6988 if (val != 1) {
6989 BNX2X_ERR("PXP2 RD_INIT failed\n");
6990 return -EBUSY;
6991 }
a2fbb9ea 6992
f2e0899f
DK		 6993 /* Timers bug workaround E2 only. We need to set the entire ILT to
6994 * have entries with value "0" and valid bit on.
6995 * This needs to be done by the first PF that is loaded in a path
6996 * (i.e. common phase)
6997 */
619c5cb6
VZ		 6998 if (!CHIP_IS_E1x(bp)) {
6999/* In E2 there is a bug in the timers block that can cause function 6 / 7
7000 * (i.e. vnic3) to start even if it is marked as "scan-off".
7001 * This occurs when a different function (func2,3) is being marked
7002 * as "scan-off". Real-life scenario for example: if a driver is being
7003 * load-unloaded while func6,7 are down. This will cause the timer to access
7004 * the ilt, translate to a logical address and send a request to read/write.
7005 * Since the ilt for the function that is down is not valid, this will cause
7006 * a translation error which is unrecoverable.
7007 * The Workaround is intended to make sure that when this happens nothing fatal
7008 * will occur. The workaround:
7009 * 1. First PF driver which loads on a path will:
7010 * a. After taking the chip out of reset, by using pretend,
7011 * it will write "0" to the following registers of
7012 * the other vnics.
7013 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7014 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7015 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7016 * And for itself it will write '1' to
7017 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7018 * dmae-operations (writing to pram for example.)
7019 * note: can be done for only function 6,7 but cleaner this
7020 * way.
7021 * b. Write zero+valid to the entire ILT.
7022 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
7023 * VNIC3 (of that port). The range allocated will be the
7024 * entire ILT. This is needed to prevent ILT range error.
7025 * 2. Any PF driver load flow:
7026 * a. ILT update with the physical addresses of the allocated
7027 * logical pages.
7028 * b. Wait 20msec. - note that this timeout is needed to make
7029 * sure there are no requests in one of the PXP internal
7030 * queues with "old" ILT addresses.
7031 * c. PF enable in the PGLC.
7032 * d. Clear the was_error of the PF in the PGLC. (could have
2de67439 7033 * occurred while driver was down)
619c5cb6
VZ		 7034 * e. PF enable in the CFC (WEAK + STRONG)
7035 * f. Timers scan enable
7036 * 3. PF driver unload flow:
7037 * a. Clear the Timers scan_en.
7038 * b. Polling for scan_on=0 for that PF.
7039 * c. Clear the PF enable bit in the PXP.
7040 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7041 * e. Write zero+valid to all ILT entries (The valid bit must
7042 * stay set)
7043 * f. If this is VNIC 3 of a port then also init
7044 * first_timers_ilt_entry to zero and last_timers_ilt_entry
16a5fd92 7045 * to the last entry in the ILT.
619c5cb6
VZ		 7046 *
7047 * Notes:
7048 * Currently the PF error in the PGLC is non recoverable.
7049 * In the future the there will be a recovery routine for this error.
7050 * Currently attention is masked.
7051 * Having an MCP lock on the load/unload process does not guarantee that
7052 * there is no Timer disable during Func6/7 enable. This is because the
7053 * Timers scan is currently being cleared by the MCP on FLR.
7054 * Step 2.d can be done only for PF6/7 and the driver can also check if
7055 * there is error before clearing it. But the flow above is simpler and
7056 * more general.
7057 * All ILT entries are written by zero+valid and not just PF6/7
7058 * ILT entries since in the future the ILT entries allocation for
7059 * PF-s might be dynamic.
7060 */
f2e0899f
DK		 7061 struct ilt_client_info ilt_cli;
7062 struct bnx2x_ilt ilt;
7063 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7064 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7065
b595076a 7066 /* initialize dummy TM client */
f2e0899f
DK		 7067 ilt_cli.start = 0;
7068 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7069 ilt_cli.client_num = ILT_CLIENT_TM;
7070
7071 /* Step 1: set zeroes to all ilt page entries with valid bit on
7072 * Step 2: set the timers first/last ilt entry to point
7073 * to the entire range to prevent ILT range error for 3rd/4th
2de67439 7074 * vnic (this code assumes existence of the vnic)
f2e0899f
DK		 7075 *
7076 * both steps performed by call to bnx2x_ilt_client_init_op()
7077 * with dummy TM client
7078 *
7079 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7080 * and his brother are split registers
7081 */
7082 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7083 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7084 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7085
7086 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7087 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7088 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7089 }
7090
34f80b04
EG		 7091 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7092 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 7093
619c5cb6 7094 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7095 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7096 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 7097 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 7098
619c5cb6 7099 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 7100
7101 /* let the HW do it's magic ... */
7102 do {
7103 msleep(200);
7104 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7105 } while (factor-- && (val != 1));
7106
7107 if (val != 1) {
7108 BNX2X_ERR("ATC_INIT failed\n");
7109 return -EBUSY;
7110 }
7111 }
7112
619c5cb6 7113 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 7114
b56e9670
AE		 7115 bnx2x_iov_init_dmae(bp);
7116
34f80b04
EG		 7117 /* clean the DMAE memory */
7118 bp->dmae_ready = 1;
619c5cb6
VZ		 7119 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7120
7121 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7122
7123 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7124
7125 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 7126
619c5cb6 7127 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 7128
34f80b04
EG		 7129 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7130 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7131 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7132 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7133
619c5cb6 7134 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 7135
523224a3
DK		 7136 /* QM queues pointers table */
7137 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7138
34f80b04
EG		 7139 /* soft reset pulse */
7140 REG_WR(bp, QM_REG_SOFT_RESET, 1);
7141 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 7142
55c11941
MS		 7143 if (CNIC_SUPPORT(bp))
7144 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 7145
619c5cb6 7146 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
b9871bcf 7147
619c5cb6 7148 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 7149 /* enable hw interrupt from doorbell Q */
7150 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 7151
619c5cb6 7152 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 7153
619c5cb6 7154 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 7155 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 7156
f2e0899f 7157 if (!CHIP_IS_E1(bp))
619c5cb6 7158 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 7159
a3348722
BW		 7160 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7161 if (IS_MF_AFEX(bp)) {
7162 /* configure that VNTag and VLAN headers must be
7163 * received in afex mode
7164 */
7165 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7166 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7167 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7168 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7169 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7170 } else {
7171 /* Bit-map indicating which L2 hdrs may appear
7172 * after the basic Ethernet header
7173 */
7174 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7175 bp->path_has_ovlan ? 7 : 6);
7176 }
7177 }
a2fbb9ea 7178
619c5cb6
VZ		 7179 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7180 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7181 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7182 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 7183
619c5cb6
VZ		 7184 if (!CHIP_IS_E1x(bp)) {
7185 /* reset VFC memories */
7186 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7187 VFC_MEMORIES_RST_REG_CAM_RST |
7188 VFC_MEMORIES_RST_REG_RAM_RST);
7189 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7190 VFC_MEMORIES_RST_REG_CAM_RST |
7191 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 7192
619c5cb6
VZ		 7193 msleep(20);
7194 }
a2fbb9ea 7195
619c5cb6
VZ		 7196 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7197 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7198 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7199 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 7200
34f80b04
EG		 7201 /* sync semi rtc */
7202 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7203 0x80000000);
7204 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7205 0x80000000);
a2fbb9ea 7206
619c5cb6
VZ		 7207 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7208 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7209 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 7210
a3348722
BW		 7211 if (!CHIP_IS_E1x(bp)) {
7212 if (IS_MF_AFEX(bp)) {
7213 /* configure that VNTag and VLAN headers must be
7214 * sent in afex mode
7215 */
7216 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7217 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7218 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7219 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7220 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7221 } else {
7222 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7223 bp->path_has_ovlan ? 7 : 6);
7224 }
7225 }
f2e0899f 7226
34f80b04 7227 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 7228
619c5cb6
VZ		 7229 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7230
55c11941
MS		 7231 if (CNIC_SUPPORT(bp)) {
7232 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7233 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7234 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7235 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7236 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7237 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7238 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7239 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7240 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7241 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7242 }
34f80b04 7243 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 7244
34f80b04
EG		 7245 if (sizeof(union cdu_context) != 1024)
7246 /* we currently assume that a context is 1024 bytes */
51c1a580
MS		 7247 dev_alert(&bp->pdev->dev,
7248 "please adjust the size of cdu_context(%ld)\n",
7249 (long)sizeof(union cdu_context));
a2fbb9ea 7250
619c5cb6 7251 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 7252 val = (4 << 24) + (0 << 12) + 1024;
7253 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 7254
619c5cb6 7255 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 7256 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 7257 /* enable context validation interrupt from CFC */
7258 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7259
7260 /* set the thresholds to prevent CFC/CDU race */
7261 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 7262
619c5cb6 7263 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 7264
619c5cb6 7265 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 7266 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7267
619c5cb6
VZ		 7268 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7269 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 7270
34f80b04
EG		 7271 /* Reset PCIE errors for debug */
7272 REG_WR(bp, 0x2814, 0xffffffff);
7273 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 7274
619c5cb6 7275 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7276 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7277 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7278 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7279 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7280 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7281 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7282 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7283 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7284 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7285 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7286 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7287 }
7288
619c5cb6 7289 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 7290 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 7291 /* in E3 this done in per-port section */
7292 if (!CHIP_IS_E3(bp))
7293 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 7294 }
619c5cb6
VZ		 7295 if (CHIP_IS_E1H(bp))
7296 /* not applicable for E2 (and above ...) */
7297 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 7298
7299 if (CHIP_REV_IS_SLOW(bp))
7300 msleep(200);
7301
7302 /* finish CFC init */
7303 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7304 if (val != 1) {
7305 BNX2X_ERR("CFC LL_INIT failed\n");
7306 return -EBUSY;
7307 }
7308 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7309 if (val != 1) {
7310 BNX2X_ERR("CFC AC_INIT failed\n");
7311 return -EBUSY;
7312 }
7313 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7314 if (val != 1) {
7315 BNX2X_ERR("CFC CAM_INIT failed\n");
7316 return -EBUSY;
7317 }
7318 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 7319
f2e0899f
DK		 7320 if (CHIP_IS_E1(bp)) {
7321 /* read NIG statistic
7322 to see if this is our first up since powerup */
7323 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7324 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 7325
f2e0899f
DK		 7326 /* do internal memory self test */
7327 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7328 BNX2X_ERR("internal mem self test failed\n");
7329 return -EBUSY;
7330 }
34f80b04
EG		 7331 }
7332
fd4ef40d
EG		 7333 bnx2x_setup_fan_failure_detection(bp);
7334
34f80b04
EG		 7335 /* clear PXP2 attentions */
7336 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 7337
4a33bc03 7338 bnx2x_enable_blocks_attention(bp);
c9ee9206 7339 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 7340
6bbca910 7341 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 7342 if (CHIP_IS_E1x(bp))
7343 bnx2x__common_init_phy(bp);
6bbca910
YR		 7344 } else
7345 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7346
34f80b04
EG		 7347 return 0;
7348}
a2fbb9ea 7349
619c5cb6
VZ		 7350/**
7351 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7352 *
7353 * @bp: driver handle
7354 */
7355static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7356{
7357 int rc = bnx2x_init_hw_common(bp);
7358
7359 if (rc)
7360 return rc;
7361
7362 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7363 if (!BP_NOMCP(bp))
7364 bnx2x__common_init_phy(bp);
7365
7366 return 0;
7367}
7368
523224a3 7369static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 7370{
7371 int port = BP_PORT(bp);
619c5cb6 7372 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 7373 u32 low, high;
4293b9f5 7374 u32 val, reg;
a2fbb9ea 7375
51c1a580 7376 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
34f80b04
EG		 7377
7378 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 7379
619c5cb6
VZ		 7380 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7381 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7382 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 7383
f2e0899f
DK		 7384 /* Timers bug workaround: disables the pf_master bit in pglue at
7385 * common phase, we need to enable it here before any dmae access are
7386 * attempted. Therefore we manually added the enable-master to the
7387 * port phase (it also happens in the function phase)
7388 */
619c5cb6 7389 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7390 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7391
619c5cb6
VZ		 7392 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7393 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7394 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7395 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7396
7397 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7398 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7399 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7400 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 7401
523224a3
DK		 7402 /* QM cid (connection) count */
7403 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 7404
55c11941
MS		 7405 if (CNIC_SUPPORT(bp)) {
7406 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7407 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7408 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7409 }
cdaa7cb8 7410
619c5cb6 7411 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f 7412
2b674047
DK		 7413 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7414
f2e0899f 7415 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 7416
7417 if (IS_MF(bp))
7418 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7419 else if (bp->dev->mtu > 4096) {
7420 if (bp->flags & ONE_PORT_FLAG)
7421 low = 160;
7422 else {
7423 val = bp->dev->mtu;
7424 /* (24*1024 + val*4)/256 */
7425 low = 96 + (val/64) +
7426 ((val % 64) ? 1 : 0);
7427 }
7428 } else
7429 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7430 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 7431 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7432 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 7433 }
1c06328c 7434
619c5cb6
VZ		 7435 if (CHIP_MODE_IS_4_PORT(bp))
7436 REG_WR(bp, (BP_PORT(bp) ?
7437 BRB1_REG_MAC_GUARANTIED_1 :
7438 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 7439
619c5cb6 7440 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
a3348722
BW		 7441 if (CHIP_IS_E3B0(bp)) {
7442 if (IS_MF_AFEX(bp)) {
7443 /* configure headers for AFEX mode */
7444 REG_WR(bp, BP_PORT(bp) ?
7445 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7446 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7447 REG_WR(bp, BP_PORT(bp) ?
7448 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7449 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7450 REG_WR(bp, BP_PORT(bp) ?
7451 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7452 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7453 } else {
7454 /* Ovlan exists only if we are in multi-function +
7455 * switch-dependent mode, in switch-independent there
7456 * is no ovlan headers
7457 */
7458 REG_WR(bp, BP_PORT(bp) ?
7459 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7460 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7461 (bp->path_has_ovlan ? 7 : 6));
7462 }
7463 }
356e2385 7464
619c5cb6
VZ		 7465 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7466 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7467 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7468 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 7469
619c5cb6
VZ		 7470 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7471 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7472 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7473 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 7474
619c5cb6
VZ		 7475 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7476 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 7477
619c5cb6
VZ		 7478 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7479
7480 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7481 /* configure PBF to work without PAUSE mtu 9000 */
7482 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 7483
f2e0899f
DK		 7484 /* update threshold */
7485 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7486 /* update init credit */
7487 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 7488
f2e0899f
DK		 7489 /* probe changes */
7490 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7491 udelay(50);
7492 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7493 }
a2fbb9ea 7494
55c11941
MS		 7495 if (CNIC_SUPPORT(bp))
7496 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7497
619c5cb6
VZ		 7498 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7499 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 7500
7501 if (CHIP_IS_E1(bp)) {
7502 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7503 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7504 }
619c5cb6 7505 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 7506
619c5cb6 7507 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7508
619c5cb6 7509 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04 7510 /* init aeu_mask_attn_func_0/1:
16a5fd92
YM		 7511 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7512 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
34f80b04 7513 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 7514 val = IS_MF(bp) ? 0xF7 : 0x7;
7515 /* Enable DCBX attention for all but E1 */
7516 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7517 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 7518
4293b9f5
DK		 7519 /* SCPAD_PARITY should NOT trigger close the gates */
7520 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7521 REG_WR(bp, reg,
7522 REG_RD(bp, reg) &
7523 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7524
7525 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7526 REG_WR(bp, reg,
7527 REG_RD(bp, reg) &
7528 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7529
619c5cb6
VZ		 7530 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7531
7532 if (!CHIP_IS_E1x(bp)) {
7533 /* Bit-map indicating which L2 hdrs may appear after the
7534 * basic Ethernet header
7535 */
a3348722
BW		 7536 if (IS_MF_AFEX(bp))
7537 REG_WR(bp, BP_PORT(bp) ?
7538 NIG_REG_P1_HDRS_AFTER_BASIC :
7539 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7540 else
7541 REG_WR(bp, BP_PORT(bp) ?
7542 NIG_REG_P1_HDRS_AFTER_BASIC :
7543 NIG_REG_P0_HDRS_AFTER_BASIC,
7544 IS_MF_SD(bp) ? 7 : 6);
619c5cb6
VZ		 7545
7546 if (CHIP_IS_E3(bp))
7547 REG_WR(bp, BP_PORT(bp) ?
7548 NIG_REG_LLH1_MF_MODE :
7549 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7550 }
7551 if (!CHIP_IS_E3(bp))
7552 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 7553
f2e0899f 7554 if (!CHIP_IS_E1(bp)) {
fb3bff17 7555 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 7556 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 7557 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 7558
619c5cb6 7559 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7560 val = 0;
7561 switch (bp->mf_mode) {
7562 case MULTI_FUNCTION_SD:
7563 val = 1;
7564 break;
7565 case MULTI_FUNCTION_SI:
a3348722 7566 case MULTI_FUNCTION_AFEX:
f2e0899f
DK		 7567 val = 2;
7568 break;
7569 }
7570
7571 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7572 NIG_REG_LLH0_CLS_TYPE), val);
7573 }
1c06328c
EG		 7574 {
7575 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7576 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7577 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7578 }
34f80b04
EG		 7579 }
7580
619c5cb6
VZ		 7581 /* If SPIO5 is set to generate interrupts, enable it for this port */
7582 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 7583 if (val & MISC_SPIO_SPIO5) {
4d295db0
EG		 7584 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7585 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7586 val = REG_RD(bp, reg_addr);
f1410647 7587 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 7588 REG_WR(bp, reg_addr, val);
f1410647 7589 }
a2fbb9ea 7590
34f80b04
EG		 7591 return 0;
7592}
7593
34f80b04
EG		 7594static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7595{
7596 int reg;
32d68de1 7597 u32 wb_write[2];
34f80b04 7598
f2e0899f 7599 if (CHIP_IS_E1(bp))
34f80b04 7600 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 7601 else
7602 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04 7603
32d68de1
YM		 7604 wb_write[0] = ONCHIP_ADDR1(addr);
7605 wb_write[1] = ONCHIP_ADDR2(addr);
7606 REG_WR_DMAE(bp, reg, wb_write, 2);
34f80b04
EG		 7607}
7608
b56e9670 7609void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
1191cb83
ED		 7610{
7611 u32 data, ctl, cnt = 100;
7612 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7613 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7614 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7615 u32 sb_bit = 1 << (idu_sb_id%32);
b56e9670 7616 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
1191cb83
ED		 7617 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7618
7619 /* Not supported in BC mode */
7620 if (CHIP_INT_MODE_IS_BC(bp))
7621 return;
7622
7623 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7624 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7625 IGU_REGULAR_CLEANUP_SET |
7626 IGU_REGULAR_BCLEANUP;
7627
7628 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7629 func_encode << IGU_CTRL_REG_FID_SHIFT |
7630 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7631
7632 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7633 data, igu_addr_data);
7634 REG_WR(bp, igu_addr_data, data);
7635 mmiowb();
7636 barrier();
7637 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7638 ctl, igu_addr_ctl);
7639 REG_WR(bp, igu_addr_ctl, ctl);
7640 mmiowb();
7641 barrier();
7642
7643 /* wait for clean up to finish */
7644 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7645 msleep(20);
7646
1191cb83
ED		 7647 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7648 DP(NETIF_MSG_HW,
7649 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7650 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7651 }
7652}
7653
7654static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
f2e0899f 7655{
619c5cb6 7656 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 7657}
7658
1191cb83 7659static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
f2e0899f
DK		 7660{
7661 u32 i, base = FUNC_ILT_BASE(func);
7662 for (i = base; i < base + ILT_PER_FUNC; i++)
7663 bnx2x_ilt_wr(bp, i, 0);
7664}
7665
910cc727 7666static void bnx2x_init_searcher(struct bnx2x *bp)
55c11941
MS		 7667{
7668 int port = BP_PORT(bp);
7669 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7670 /* T1 hash bits value determines the T1 number of entries */
7671 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7672}
7673
7674static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7675{
7676 int rc;
7677 struct bnx2x_func_state_params func_params = {NULL};
7678 struct bnx2x_func_switch_update_params *switch_update_params =
7679 &func_params.params.switch_update;
7680
7681 /* Prepare parameters for function state transitions */
7682 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7683 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7684
7685 func_params.f_obj = &bp->func_obj;
7686 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7687
7688 /* Function parameters */
e42780b6
DK		 7689 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7690 &switch_update_params->changes);
7691 if (suspend)
7692 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7693 &switch_update_params->changes);
55c11941
MS		 7694
7695 rc = bnx2x_func_state_change(bp, &func_params);
7696
7697 return rc;
7698}
7699
910cc727 7700static int bnx2x_reset_nic_mode(struct bnx2x *bp)
55c11941
MS		 7701{
7702 int rc, i, port = BP_PORT(bp);
7703 int vlan_en = 0, mac_en[NUM_MACS];
7704
55c11941
MS		 7705 /* Close input from network */
7706 if (bp->mf_mode == SINGLE_FUNCTION) {
7707 bnx2x_set_rx_filter(&bp->link_params, 0);
7708 } else {
7709 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7710 NIG_REG_LLH0_FUNC_EN);
7711 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7712 NIG_REG_LLH0_FUNC_EN, 0);
7713 for (i = 0; i < NUM_MACS; i++) {
7714 mac_en[i] = REG_RD(bp, port ?
7715 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7716 4 * i) :
7717 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7718 4 * i));
7719 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7720 4 * i) :
7721 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7722 }
7723 }
7724
7725 /* Close BMC to host */
7726 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7727 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7728
7729 /* Suspend Tx switching to the PF. Completion of this ramrod
7730 * further guarantees that all the packets of that PF / child
7731 * VFs in BRB were processed by the Parser, so it is safe to
7732 * change the NIC_MODE register.
7733 */
7734 rc = bnx2x_func_switch_update(bp, 1);
7735 if (rc) {
7736 BNX2X_ERR("Can't suspend tx-switching!\n");
7737 return rc;
7738 }
7739
7740 /* Change NIC_MODE register */
7741 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7742
7743 /* Open input from network */
7744 if (bp->mf_mode == SINGLE_FUNCTION) {
7745 bnx2x_set_rx_filter(&bp->link_params, 1);
7746 } else {
7747 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7748 NIG_REG_LLH0_FUNC_EN, vlan_en);
7749 for (i = 0; i < NUM_MACS; i++) {
7750 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7751 4 * i) :
7752 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7753 mac_en[i]);
7754 }
7755 }
7756
7757 /* Enable BMC to host */
7758 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7759 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7760
7761 /* Resume Tx switching to the PF */
7762 rc = bnx2x_func_switch_update(bp, 0);
7763 if (rc) {
7764 BNX2X_ERR("Can't resume tx-switching!\n");
7765 return rc;
7766 }
7767
7768 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7769 return 0;
7770}
7771
7772int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7773{
7774 int rc;
7775
7776 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7777
7778 if (CONFIGURE_NIC_MODE(bp)) {
16a5fd92 7779 /* Configure searcher as part of function hw init */
55c11941
MS		 7780 bnx2x_init_searcher(bp);
7781
7782 /* Reset NIC mode */
7783 rc = bnx2x_reset_nic_mode(bp);
7784 if (rc)
7785 BNX2X_ERR("Can't change NIC mode!\n");
7786 return rc;
7787 }
7788
7789 return 0;
7790}
7791
523224a3 7792static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 7793{
7794 int port = BP_PORT(bp);
7795 int func = BP_FUNC(bp);
619c5cb6 7796 int init_phase = PHASE_PF0 + func;
523224a3
DK		 7797 struct bnx2x_ilt *ilt = BP_ILT(bp);
7798 u16 cdu_ilt_start;
8badd27a 7799 u32 addr, val;
f4a66897 7800 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
89db4ad8 7801 int i, main_mem_width, rc;
34f80b04 7802
51c1a580 7803 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
34f80b04 7804
619c5cb6 7805 /* FLR cleanup - hmmm */
89db4ad8
AE		 7806 if (!CHIP_IS_E1x(bp)) {
7807 rc = bnx2x_pf_flr_clnup(bp);
04c46736
YM		 7808 if (rc) {
7809 bnx2x_fw_dump(bp);
89db4ad8 7810 return rc;
04c46736 7811 }
89db4ad8 7812 }
619c5cb6 7813
8badd27a 7814 /* set MSI reconfigure capability */
f2e0899f
DK		 7815 if (bp->common.int_block == INT_BLOCK_HC) {
7816 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7817 val = REG_RD(bp, addr);
7818 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7819 REG_WR(bp, addr, val);
7820 }
8badd27a 7821
619c5cb6
VZ		 7822 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7823 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7824
523224a3
DK		 7825 ilt = BP_ILT(bp);
7826 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 7827
290ca2bb
AE		 7828 if (IS_SRIOV(bp))
7829 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7830 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7831
7832 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7833 * those of the VFs, so start line should be reset
7834 */
7835 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
523224a3 7836 for (i = 0; i < L2_ILT_LINES(bp); i++) {
a052997e 7837 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
523224a3 7838 ilt->lines[cdu_ilt_start + i].page_mapping =
a052997e
MS		 7839 bp->context[i].cxt_mapping;
7840 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
37b091ba 7841 }
290ca2bb 7842
523224a3 7843 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 7844
55c11941
MS		 7845 if (!CONFIGURE_NIC_MODE(bp)) {
7846 bnx2x_init_searcher(bp);
7847 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7848 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7849 } else {
7850 /* Set NIC mode */
7851 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6bf07b8e 7852 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
55c11941 7853 }
37b091ba 7854
619c5cb6 7855 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7856 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7857
7858 /* Turn on a single ISR mode in IGU if driver is going to use
7859 * INT#x or MSI
7860 */
7861 if (!(bp->flags & USING_MSIX_FLAG))
7862 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7863 /*
7864 * Timers workaround bug: function init part.
7865 * Need to wait 20msec after initializing ILT,
7866 * needed to make sure there are no requests in
7867 * one of the PXP internal queues with "old" ILT addresses
7868 */
7869 msleep(20);
7870 /*
7871 * Master enable - Due to WB DMAE writes performed before this
7872 * register is re-initialized as part of the regular function
7873 * init
7874 */
7875 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7876 /* Enable the function in IGU */
7877 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7878 }
7879
523224a3 7880 bp->dmae_ready = 1;
34f80b04 7881
619c5cb6 7882 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 7883
619c5cb6 7884 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7885 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7886
619c5cb6
VZ		 7887 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7888 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7889 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7890 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7891 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7892 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7893 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7894 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7895 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7896 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7897 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7898 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7899 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7900
7901 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7902 REG_WR(bp, QM_REG_PF_EN, 1);
7903
619c5cb6
VZ		 7904 if (!CHIP_IS_E1x(bp)) {
7905 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7906 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7907 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7908 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7909 }
7910 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7911
7912 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7913 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
c19d65c9 7914 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
b56e9670
AE		 7915
7916 bnx2x_iov_init_dq(bp);
7917
619c5cb6
VZ		 7918 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7919 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7920 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7921 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7922 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7923 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7924 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7925 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7926 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7927 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7928 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7929
619c5cb6 7930 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 7931
619c5cb6 7932 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 7933
619c5cb6 7934 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7935 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7936
fb3bff17 7937 if (IS_MF(bp)) {
34f80b04 7938 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 7939 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 7940 }
7941
619c5cb6 7942 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 7943
34f80b04 7944 /* HC init per function */
f2e0899f
DK		 7945 if (bp->common.int_block == INT_BLOCK_HC) {
7946 if (CHIP_IS_E1H(bp)) {
7947 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7948
7949 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7950 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7951 }
619c5cb6 7952 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 7953
7954 } else {
7955 int num_segs, sb_idx, prod_offset;
7956
34f80b04
EG		 7957 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7958
619c5cb6 7959 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7960 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7961 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7962 }
7963
619c5cb6 7964 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7965
619c5cb6 7966 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7967 int dsb_idx = 0;
7968 /**
7969 * Producer memory:
7970 * E2 mode: address 0-135 match to the mapping memory;
7971 * 136 - PF0 default prod; 137 - PF1 default prod;
7972 * 138 - PF2 default prod; 139 - PF3 default prod;
7973 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7974 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7975 * 144-147 reserved.
7976 *
7977 * E1.5 mode - In backward compatible mode;
7978 * for non default SB; each even line in the memory
7979 * holds the U producer and each odd line hold
7980 * the C producer. The first 128 producers are for
7981 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7982 * producers are for the DSB for each PF.
7983 * Each PF has five segments: (the order inside each
7984 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7985 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7986 * 144-147 attn prods;
7987 */
7988 /* non-default-status-blocks */
7989 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7990 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7991 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7992 prod_offset = (bp->igu_base_sb + sb_idx) *
7993 num_segs;
7994
7995 for (i = 0; i < num_segs; i++) {
7996 addr = IGU_REG_PROD_CONS_MEMORY +
7997 (prod_offset + i) * 4;
7998 REG_WR(bp, addr, 0);
7999 }
8000 /* send consumer update with value 0 */
8001 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8002 USTORM_ID, 0, IGU_INT_NOP, 1);
8003 bnx2x_igu_clear_sb(bp,
8004 bp->igu_base_sb + sb_idx);
8005 }
8006
8007 /* default-status-blocks */
8008 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8009 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8010
8011 if (CHIP_MODE_IS_4_PORT(bp))
8012 dsb_idx = BP_FUNC(bp);
8013 else
3395a033 8014 dsb_idx = BP_VN(bp);
f2e0899f
DK		 8015
8016 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8017 IGU_BC_BASE_DSB_PROD + dsb_idx :
8018 IGU_NORM_BASE_DSB_PROD + dsb_idx);
8019
3395a033
DK		 8020 /*
8021 * igu prods come in chunks of E1HVN_MAX (4) -
8022 * does not matters what is the current chip mode
8023 */
f2e0899f
DK		 8024 for (i = 0; i < (num_segs * E1HVN_MAX);
8025 i += E1HVN_MAX) {
8026 addr = IGU_REG_PROD_CONS_MEMORY +
8027 (prod_offset + i)*4;
8028 REG_WR(bp, addr, 0);
8029 }
8030 /* send consumer update with 0 */
8031 if (CHIP_INT_MODE_IS_BC(bp)) {
8032 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8033 USTORM_ID, 0, IGU_INT_NOP, 1);
8034 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8035 CSTORM_ID, 0, IGU_INT_NOP, 1);
8036 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8037 XSTORM_ID, 0, IGU_INT_NOP, 1);
8038 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8039 TSTORM_ID, 0, IGU_INT_NOP, 1);
8040 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8041 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8042 } else {
8043 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8044 USTORM_ID, 0, IGU_INT_NOP, 1);
8045 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8046 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8047 }
8048 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8049
16a5fd92 8050 /* !!! These should become driver const once
f2e0899f
DK		 8051 rf-tool supports split-68 const */
8052 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8053 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8054 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8055 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8056 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8057 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8058 }
34f80b04 8059 }
34f80b04 8060
c14423fe 8061 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 8062 REG_WR(bp, 0x2114, 0xffffffff);
8063 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 8064
f4a66897
VZ		 8065 if (CHIP_IS_E1x(bp)) {
8066 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8067 main_mem_base = HC_REG_MAIN_MEMORY +
8068 BP_PORT(bp) * (main_mem_size * 4);
8069 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8070 main_mem_width = 8;
8071
8072 val = REG_RD(bp, main_mem_prty_clr);
8073 if (val)
51c1a580
MS		 8074 DP(NETIF_MSG_HW,
8075 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8076 val);
f4a66897
VZ		 8077
8078 /* Clear "false" parity errors in MSI-X table */
8079 for (i = main_mem_base;
8080 i < main_mem_base + main_mem_size * 4;
8081 i += main_mem_width) {
8082 bnx2x_read_dmae(bp, i, main_mem_width / 4);
8083 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8084 i, main_mem_width / 4);
8085 }
8086 /* Clear HC parity attention */
8087 REG_RD(bp, main_mem_prty_clr);
8088 }
8089
619c5cb6
VZ		 8090#ifdef BNX2X_STOP_ON_ERROR
8091 /* Enable STORMs SP logging */
8092 REG_WR8(bp, BAR_USTRORM_INTMEM +
8093 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8094 REG_WR8(bp, BAR_TSTRORM_INTMEM +
8095 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8096 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8097 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8098 REG_WR8(bp, BAR_XSTRORM_INTMEM +
8099 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8100#endif
8101
b7737c9b 8102 bnx2x_phy_probe(&bp->link_params);
f85582f8 8103
34f80b04
EG		 8104 return 0;
8105}
8106
55c11941
MS		 8107void bnx2x_free_mem_cnic(struct bnx2x *bp)
8108{
8109 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8110
8111 if (!CHIP_IS_E1x(bp))
8112 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8113 sizeof(struct host_hc_status_block_e2));
8114 else
8115 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8116 sizeof(struct host_hc_status_block_e1x));
8117
8118 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8119}
8120
9f6c9258 8121void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 8122{
a052997e
MS		 8123 int i;
8124
619c5cb6
VZ		 8125 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8126 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8127
b4cddbd6
AE		 8128 if (IS_VF(bp))
8129 return;
8130
8131 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8132 sizeof(struct host_sp_status_block));
8133
a2fbb9ea 8134 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 8135 sizeof(struct bnx2x_slowpath));
a2fbb9ea 8136
a052997e
MS		 8137 for (i = 0; i < L2_ILT_LINES(bp); i++)
8138 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8139 bp->context[i].size);
523224a3
DK		 8140 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8141
8142 BNX2X_FREE(bp->ilt->lines);
f85582f8 8143
7a9b2557 8144 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 8145
523224a3
DK		 8146 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8147 BCM_PAGE_SIZE * NUM_EQ_PAGES);
580d9d08 8148
05952246
YM		 8149 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8150
580d9d08 8151 bnx2x_iov_free_mem(bp);
619c5cb6
VZ		 8152}
8153
55c11941 8154int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
a2fbb9ea 8155{
cd2b0389 8156 if (!CHIP_IS_E1x(bp)) {
619c5cb6 8157 /* size = the status block + ramrod buffers */
cd2b0389
JP		 8158 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8159 sizeof(struct host_hc_status_block_e2));
8160 if (!bp->cnic_sb.e2_sb)
8161 goto alloc_mem_err;
8162 } else {
8163 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8164 sizeof(struct host_hc_status_block_e1x));
8165 if (!bp->cnic_sb.e1x_sb)
8166 goto alloc_mem_err;
8167 }
8badd27a 8168
cd2b0389 8169 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
16a5fd92 8170 /* allocate searcher T2 table, as it wasn't allocated before */
cd2b0389
JP		 8171 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8172 if (!bp->t2)
8173 goto alloc_mem_err;
8174 }
55c11941
MS		 8175
8176 /* write address to which L5 should insert its values */
8177 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8178 &bp->slowpath->drv_info_to_mcp;
8179
8180 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8181 goto alloc_mem_err;
8182
8183 return 0;
8184
8185alloc_mem_err:
8186 bnx2x_free_mem_cnic(bp);
8187 BNX2X_ERR("Can't allocate memory\n");
8188 return -ENOMEM;
8189}
8190
8191int bnx2x_alloc_mem(struct bnx2x *bp)
8192{
8193 int i, allocated, context_size;
a2fbb9ea 8194
cd2b0389 8195 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
55c11941 8196 /* allocate searcher T2 table */
cd2b0389
JP		 8197 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8198 if (!bp->t2)
8199 goto alloc_mem_err;
8200 }
8badd27a 8201
cd2b0389
JP		 8202 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8203 sizeof(struct host_sp_status_block));
8204 if (!bp->def_status_blk)
8205 goto alloc_mem_err;
a2fbb9ea 8206
cd2b0389
JP		 8207 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8208 sizeof(struct bnx2x_slowpath));
8209 if (!bp->slowpath)
8210 goto alloc_mem_err;
a2fbb9ea 8211
a052997e
MS		 8212 /* Allocate memory for CDU context:
8213 * This memory is allocated separately and not in the generic ILT
8214 * functions because CDU differs in few aspects:
8215 * 1. There are multiple entities allocating memory for context -
8216 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8217 * its own ILT lines.
8218 * 2. Since CDU page-size is not a single 4KB page (which is the case
8219 * for the other ILT clients), to be efficient we want to support
8220 * allocation of sub-page-size in the last entry.
8221 * 3. Context pointers are used by the driver to pass to FW / update
8222 * the context (for the other ILT clients the pointers are used just to
8223 * free the memory during unload).
8224 */
8225 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
65abd74d 8226
a052997e
MS		 8227 for (i = 0, allocated = 0; allocated < context_size; i++) {
8228 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8229 (context_size - allocated));
cd2b0389
JP		 8230 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8231 bp->context[i].size);
8232 if (!bp->context[i].vcxt)
8233 goto alloc_mem_err;
a052997e
MS		 8234 allocated += bp->context[i].size;
8235 }
cd2b0389
JP		 8236 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8237 GFP_KERNEL);
8238 if (!bp->ilt->lines)
8239 goto alloc_mem_err;
65abd74d 8240
523224a3
DK		 8241 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8242 goto alloc_mem_err;
65abd74d 8243
67c431a5
AE		 8244 if (bnx2x_iov_alloc_mem(bp))
8245 goto alloc_mem_err;
8246
9f6c9258 8247 /* Slow path ring */
cd2b0389
JP		 8248 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8249 if (!bp->spq)
8250 goto alloc_mem_err;
65abd74d 8251
523224a3 8252 /* EQ */
cd2b0389
JP		 8253 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8254 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8255 if (!bp->eq_ring)
8256 goto alloc_mem_err;
ab532cf3 8257
9f6c9258 8258 return 0;
e1510706 8259
9f6c9258
DK		 8260alloc_mem_err:
8261 bnx2x_free_mem(bp);
51c1a580 8262 BNX2X_ERR("Can't allocate memory\n");
9f6c9258 8263 return -ENOMEM;
65abd74d
YG		 8264}
8265
a2fbb9ea
ET		 8266/*
8267 * Init service functions
8268 */
a2fbb9ea 8269
619c5cb6
VZ		 8270int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8271 struct bnx2x_vlan_mac_obj *obj, bool set,
8272 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 8273{
619c5cb6
VZ		 8274 int rc;
8275 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 8276
619c5cb6 8277 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 8278
619c5cb6
VZ		 8279 /* Fill general parameters */
8280 ramrod_param.vlan_mac_obj = obj;
8281 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 8282
619c5cb6
VZ		 8283 /* Fill a user request section if needed */
8284 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8285 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 8286
619c5cb6 8287 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 8288
619c5cb6
VZ		 8289 /* Set the command: ADD or DEL */
8290 if (set)
8291 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8292 else
8293 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 8294 }
8295
619c5cb6 8296 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7b5342d9
YM		 8297
8298 if (rc == -EEXIST) {
8299 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8300 /* do not treat adding same MAC as error */
8301 rc = 0;
8302 } else if (rc < 0)
619c5cb6 8303 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7b5342d9 8304
619c5cb6 8305 return rc;
a2fbb9ea
ET		 8306}
8307
619c5cb6
VZ		 8308int bnx2x_del_all_macs(struct bnx2x *bp,
8309 struct bnx2x_vlan_mac_obj *mac_obj,
8310 int mac_type, bool wait_for_comp)
e665bfda 8311{
619c5cb6
VZ		 8312 int rc;
8313 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 8314
619c5cb6
VZ		 8315 /* Wait for completion of requested */
8316 if (wait_for_comp)
8317 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 8318
619c5cb6
VZ		 8319 /* Set the mac type of addresses we want to clear */
8320 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 8321
619c5cb6
VZ		 8322 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8323 if (rc < 0)
8324 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 8325
619c5cb6 8326 return rc;
0793f83f
DK		 8327}
8328
619c5cb6 8329int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 8330{
a3348722
BW		 8331 if (is_zero_ether_addr(bp->dev->dev_addr) &&
8332 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
51c1a580
MS		 8333 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8334 "Ignoring Zero MAC for STORAGE SD mode\n");
614c76df
DK		 8335 return 0;
8336 }
614c76df 8337
f8f4f61a
DK		 8338 if (IS_PF(bp)) {
8339 unsigned long ramrod_flags = 0;
0793f83f 8340
f8f4f61a
DK		 8341 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8342 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8343 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8344 &bp->sp_objs->mac_obj, set,
8345 BNX2X_ETH_MAC, &ramrod_flags);
8346 } else { /* vf */
8347 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8348 bp->fp->index, true);
8349 }
e665bfda 8350}
6e30dd4e 8351
619c5cb6 8352int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 8353{
60cad4e6
AE		 8354 if (IS_PF(bp))
8355 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8356 else /* VF */
8357 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
993ac7b5 8358}
a2fbb9ea 8359
d6214d7a 8360/**
e8920674 8361 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 8362 *
e8920674 8363 * @bp: driver handle
d6214d7a 8364 *
e8920674 8365 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 8366 */
1ab4434c 8367int bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 8368{
1ab4434c
AE		 8369 int rc = 0;
8370
60cad4e6
AE		 8371 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8372 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
1ab4434c 8373 return -EINVAL;
60cad4e6 8374 }
1ab4434c 8375
9ee3d37b 8376 switch (int_mode) {
1ab4434c
AE		 8377 case BNX2X_INT_MODE_MSIX:
8378 /* attempt to enable msix */
8379 rc = bnx2x_enable_msix(bp);
8380
8381 /* msix attained */
8382 if (!rc)
8383 return 0;
8384
8385 /* vfs use only msix */
8386 if (rc && IS_VF(bp))
8387 return rc;
8388
8389 /* failed to enable multiple MSI-X */
8390 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8391 bp->num_queues,
8392 1 + bp->num_cnic_queues);
8393
8394 /* falling through... */
8395 case BNX2X_INT_MODE_MSI:
d6214d7a 8396 bnx2x_enable_msi(bp);
1ab4434c 8397
d6214d7a 8398 /* falling through... */
1ab4434c 8399 case BNX2X_INT_MODE_INTX:
55c11941
MS		 8400 bp->num_ethernet_queues = 1;
8401 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
51c1a580 8402 BNX2X_DEV_INFO("set number of queues to 1\n");
ca00392c 8403 break;
d6214d7a 8404 default:
1ab4434c
AE		 8405 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8406 return -EINVAL;
9f6c9258 8407 }
1ab4434c 8408 return 0;
a2fbb9ea
ET		 8409}
8410
1ab4434c 8411/* must be called prior to any HW initializations */
c2bff63f
DK		 8412static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8413{
290ca2bb
AE		 8414 if (IS_SRIOV(bp))
8415 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
c2bff63f
DK		 8416 return L2_ILT_LINES(bp);
8417}
8418
523224a3
DK		 8419void bnx2x_ilt_set_info(struct bnx2x *bp)
8420{
8421 struct ilt_client_info *ilt_client;
8422 struct bnx2x_ilt *ilt = BP_ILT(bp);
8423 u16 line = 0;
8424
8425 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8426 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8427
8428 /* CDU */
8429 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8430 ilt_client->client_num = ILT_CLIENT_CDU;
8431 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8432 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8433 ilt_client->start = line;
619c5cb6 8434 line += bnx2x_cid_ilt_lines(bp);
55c11941
MS		 8435
8436 if (CNIC_SUPPORT(bp))
8437 line += CNIC_ILT_LINES;
523224a3
DK		 8438 ilt_client->end = line - 1;
8439
51c1a580 8440 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8441 ilt_client->start,
8442 ilt_client->end,
8443 ilt_client->page_size,
8444 ilt_client->flags,
8445 ilog2(ilt_client->page_size >> 12));
8446
8447 /* QM */
8448 if (QM_INIT(bp->qm_cid_count)) {
8449 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8450 ilt_client->client_num = ILT_CLIENT_QM;
8451 ilt_client->page_size = QM_ILT_PAGE_SZ;
8452 ilt_client->flags = 0;
8453 ilt_client->start = line;
8454
8455 /* 4 bytes for each cid */
8456 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8457 QM_ILT_PAGE_SZ);
8458
8459 ilt_client->end = line - 1;
8460
51c1a580
MS		 8461 DP(NETIF_MSG_IFUP,
8462 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8463 ilt_client->start,
8464 ilt_client->end,
8465 ilt_client->page_size,
8466 ilt_client->flags,
8467 ilog2(ilt_client->page_size >> 12));
523224a3 8468 }
523224a3 8469
55c11941
MS		 8470 if (CNIC_SUPPORT(bp)) {
8471 /* SRC */
8472 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8473 ilt_client->client_num = ILT_CLIENT_SRC;
8474 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8475 ilt_client->flags = 0;
8476 ilt_client->start = line;
8477 line += SRC_ILT_LINES;
8478 ilt_client->end = line - 1;
523224a3 8479
55c11941
MS		 8480 DP(NETIF_MSG_IFUP,
8481 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8482 ilt_client->start,
8483 ilt_client->end,
8484 ilt_client->page_size,
8485 ilt_client->flags,
8486 ilog2(ilt_client->page_size >> 12));
9f6c9258 8487
55c11941
MS		 8488 /* TM */
8489 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8490 ilt_client->client_num = ILT_CLIENT_TM;
8491 ilt_client->page_size = TM_ILT_PAGE_SZ;
8492 ilt_client->flags = 0;
8493 ilt_client->start = line;
8494 line += TM_ILT_LINES;
8495 ilt_client->end = line - 1;
523224a3 8496
55c11941
MS		 8497 DP(NETIF_MSG_IFUP,
8498 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8499 ilt_client->start,
8500 ilt_client->end,
8501 ilt_client->page_size,
8502 ilt_client->flags,
8503 ilog2(ilt_client->page_size >> 12));
8504 }
9f6c9258 8505
619c5cb6 8506 BUG_ON(line > ILT_MAX_LINES);
523224a3 8507}
f85582f8 8508
619c5cb6
VZ		 8509/**
8510 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8511 *
8512 * @bp: driver handle
8513 * @fp: pointer to fastpath
8514 * @init_params: pointer to parameters structure
8515 *
8516 * parameters configured:
8517 * - HC configuration
8518 * - Queue's CDU context
8519 */
1191cb83 8520static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
619c5cb6 8521 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 8522{
6383c0b3 8523 u8 cos;
a052997e
MS		 8524 int cxt_index, cxt_offset;
8525
619c5cb6
VZ		 8526 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8527 if (!IS_FCOE_FP(fp)) {
8528 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8529 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8530
16a5fd92 8531 /* If HC is supported, enable host coalescing in the transition
619c5cb6
VZ		 8532 * to INIT state.
8533 */
8534 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8535 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8536
8537 /* HC rate */
8538 init_params->rx.hc_rate = bp->rx_ticks ?
8539 (1000000 / bp->rx_ticks) : 0;
8540 init_params->tx.hc_rate = bp->tx_ticks ?
8541 (1000000 / bp->tx_ticks) : 0;
8542
8543 /* FW SB ID */
8544 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8545 fp->fw_sb_id;
8546
8547 /*
8548 * CQ index among the SB indices: FCoE clients uses the default
8549 * SB, therefore it's different.
8550 */
6383c0b3
AE		 8551 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8552 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 8553 }
8554
6383c0b3
AE		 8555 /* set maximum number of COSs supported by this queue */
8556 init_params->max_cos = fp->max_cos;
8557
51c1a580 8558 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 8559 fp->index, init_params->max_cos);
8560
8561 /* set the context pointers queue object */
a052997e 8562 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
65565884
MS		 8563 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8564 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
a052997e 8565 ILT_PAGE_CIDS);
6383c0b3 8566 init_params->cxts[cos] =
a052997e
MS		 8567 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8568 }
619c5cb6
VZ		 8569}
8570
910cc727 8571static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6383c0b3
AE		 8572 struct bnx2x_queue_state_params *q_params,
8573 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8574 int tx_index, bool leading)
8575{
8576 memset(tx_only_params, 0, sizeof(*tx_only_params));
8577
8578 /* Set the command */
8579 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8580
8581 /* Set tx-only QUEUE flags: don't zero statistics */
8582 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8583
8584 /* choose the index of the cid to send the slow path on */
8585 tx_only_params->cid_index = tx_index;
8586
8587 /* Set general TX_ONLY_SETUP parameters */
8588 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8589
8590 /* Set Tx TX_ONLY_SETUP parameters */
8591 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8592
51c1a580
MS		 8593 DP(NETIF_MSG_IFUP,
8594 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 8595 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8596 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8597 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8598
8599 /* send the ramrod */
8600 return bnx2x_queue_state_change(bp, q_params);
8601}
8602
619c5cb6
VZ		 8603/**
8604 * bnx2x_setup_queue - setup queue
8605 *
8606 * @bp: driver handle
8607 * @fp: pointer to fastpath
8608 * @leading: is leading
8609 *
8610 * This function performs 2 steps in a Queue state machine
8611 * actually: 1) RESET->INIT 2) INIT->SETUP
8612 */
8613
8614int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8615 bool leading)
8616{
3b603066 8617 struct bnx2x_queue_state_params q_params = {NULL};
619c5cb6
VZ		 8618 struct bnx2x_queue_setup_params *setup_params =
8619 &q_params.params.setup;
6383c0b3
AE		 8620 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8621 &q_params.params.tx_only;
a2fbb9ea 8622 int rc;
6383c0b3
AE		 8623 u8 tx_index;
8624
51c1a580 8625 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
a2fbb9ea 8626
ec6ba945
VZ		 8627 /* reset IGU state skip FCoE L2 queue */
8628 if (!IS_FCOE_FP(fp))
8629 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 8630 IGU_INT_ENABLE, 0);
a2fbb9ea 8631
15192a8c 8632 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8633 /* We want to wait for completion in this context */
8634 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8635
619c5cb6
VZ		 8636 /* Prepare the INIT parameters */
8637 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 8638
619c5cb6
VZ		 8639 /* Set the command */
8640 q_params.cmd = BNX2X_Q_CMD_INIT;
8641
8642 /* Change the state to INIT */
8643 rc = bnx2x_queue_state_change(bp, &q_params);
8644 if (rc) {
6383c0b3 8645 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 8646 return rc;
8647 }
ec6ba945 8648
51c1a580 8649 DP(NETIF_MSG_IFUP, "init complete\n");
6383c0b3 8650
619c5cb6
VZ		 8651 /* Now move the Queue to the SETUP state... */
8652 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 8653
619c5cb6
VZ		 8654 /* Set QUEUE flags */
8655 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 8656
619c5cb6 8657 /* Set general SETUP parameters */
6383c0b3
AE		 8658 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8659 FIRST_TX_COS_INDEX);
619c5cb6 8660
6383c0b3 8661 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 8662 &setup_params->rxq_params);
8663
6383c0b3
AE		 8664 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8665 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 8666
8667 /* Set the command */
8668 q_params.cmd = BNX2X_Q_CMD_SETUP;
8669
55c11941
MS		 8670 if (IS_FCOE_FP(fp))
8671 bp->fcoe_init = true;
8672
619c5cb6
VZ		 8673 /* Change the state to SETUP */
8674 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 8675 if (rc) {
8676 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8677 return rc;
8678 }
8679
8680 /* loop through the relevant tx-only indices */
8681 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8682 tx_index < fp->max_cos;
8683 tx_index++) {
8684
8685 /* prepare and send tx-only ramrod*/
8686 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8687 tx_only_params, tx_index, leading);
8688 if (rc) {
8689 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8690 fp->index, tx_index);
8691 return rc;
8692 }
8693 }
523224a3 8694
34f80b04 8695 return rc;
a2fbb9ea
ET		 8696}
8697
619c5cb6 8698static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 8699{
619c5cb6 8700 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 8701 struct bnx2x_fp_txdata *txdata;
3b603066 8702 struct bnx2x_queue_state_params q_params = {NULL};
6383c0b3
AE		 8703 int rc, tx_index;
8704
51c1a580 8705 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 8706
15192a8c 8707 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8708 /* We want to wait for completion in this context */
8709 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8710
6383c0b3
AE		 8711 /* close tx-only connections */
8712 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8713 tx_index < fp->max_cos;
8714 tx_index++){
8715
8716 /* ascertain this is a normal queue*/
65565884 8717 txdata = fp->txdata_ptr[tx_index];
6383c0b3 8718
51c1a580 8719 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
6383c0b3
AE		 8720 txdata->txq_index);
8721
8722 /* send halt terminate on tx-only connection */
8723 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8724 memset(&q_params.params.terminate, 0,
8725 sizeof(q_params.params.terminate));
8726 q_params.params.terminate.cid_index = tx_index;
8727
8728 rc = bnx2x_queue_state_change(bp, &q_params);
8729 if (rc)
8730 return rc;
8731
8732 /* send halt terminate on tx-only connection */
8733 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8734 memset(&q_params.params.cfc_del, 0,
8735 sizeof(q_params.params.cfc_del));
8736 q_params.params.cfc_del.cid_index = tx_index;
8737 rc = bnx2x_queue_state_change(bp, &q_params);
8738 if (rc)
8739 return rc;
8740 }
8741 /* Stop the primary connection: */
8742 /* ...halt the connection */
619c5cb6
VZ		 8743 q_params.cmd = BNX2X_Q_CMD_HALT;
8744 rc = bnx2x_queue_state_change(bp, &q_params);
8745 if (rc)
da5a662a 8746 return rc;
a2fbb9ea 8747
6383c0b3 8748 /* ...terminate the connection */
619c5cb6 8749 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 8750 memset(&q_params.params.terminate, 0,
8751 sizeof(q_params.params.terminate));
8752 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 8753 rc = bnx2x_queue_state_change(bp, &q_params);
8754 if (rc)
523224a3 8755 return rc;
6383c0b3 8756 /* ...delete cfc entry */
619c5cb6 8757 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 8758 memset(&q_params.params.cfc_del, 0,
8759 sizeof(q_params.params.cfc_del));
8760 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 8761 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 8762}
8763
34f80b04
EG		 8764static void bnx2x_reset_func(struct bnx2x *bp)
8765{
8766 int port = BP_PORT(bp);
8767 int func = BP_FUNC(bp);
f2e0899f 8768 int i;
523224a3
DK		 8769
8770 /* Disable the function in the FW */
8771 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8772 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8773 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8774 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8775
8776 /* FP SBs */
ec6ba945 8777 for_each_eth_queue(bp, i) {
523224a3 8778 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 8779 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 8780 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8781 SB_DISABLED);
523224a3
DK		 8782 }
8783
55c11941
MS		 8784 if (CNIC_LOADED(bp))
8785 /* CNIC SB */
8786 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8787 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8788 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8789
523224a3 8790 /* SP SB */
619c5cb6 8791 REG_WR8(bp, BAR_CSTRORM_INTMEM +
2de67439
YM		 8792 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8793 SB_DISABLED);
523224a3
DK		 8794
8795 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8796 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8797 0);
34f80b04
EG		 8798
8799 /* Configure IGU */
f2e0899f
DK		 8800 if (bp->common.int_block == INT_BLOCK_HC) {
8801 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8802 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8803 } else {
8804 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8805 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8806 }
34f80b04 8807
55c11941
MS		 8808 if (CNIC_LOADED(bp)) {
8809 /* Disable Timer scan */
8810 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8811 /*
8812 * Wait for at least 10ms and up to 2 second for the timers
8813 * scan to complete
8814 */
8815 for (i = 0; i < 200; i++) {
639d65b8 8816 usleep_range(10000, 20000);
55c11941
MS		 8817 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8818 break;
8819 }
37b091ba 8820 }
34f80b04 8821 /* Clear ILT */
f2e0899f
DK		 8822 bnx2x_clear_func_ilt(bp, func);
8823
8824 /* Timers workaround bug for E2: if this is vnic-3,
8825 * we need to set the entire ilt range for this timers.
8826 */
619c5cb6 8827 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 8828 struct ilt_client_info ilt_cli;
8829 /* use dummy TM client */
8830 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8831 ilt_cli.start = 0;
8832 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8833 ilt_cli.client_num = ILT_CLIENT_TM;
8834
8835 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8836 }
8837
8838 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 8839 if (!CHIP_IS_E1x(bp))
f2e0899f 8840 bnx2x_pf_disable(bp);
523224a3
DK		 8841
8842 bp->dmae_ready = 0;
34f80b04
EG		 8843}
8844
8845static void bnx2x_reset_port(struct bnx2x *bp)
8846{
8847 int port = BP_PORT(bp);
8848 u32 val;
8849
619c5cb6
VZ		 8850 /* Reset physical Link */
8851 bnx2x__link_reset(bp);
8852
34f80b04
EG		 8853 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8854
8855 /* Do not rcv packets to BRB */
8856 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8857 /* Do not direct rcv packets that are not for MCP to the BRB */
8858 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8859 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8860
8861 /* Configure AEU */
8862 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8863
8864 msleep(100);
8865 /* Check for BRB port occupancy */
8866 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8867 if (val)
8868 DP(NETIF_MSG_IFDOWN,
33471629 8869 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 8870
8871 /* TODO: Close Doorbell port? */
8872}
8873
1191cb83 8874static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 8875{
3b603066 8876 struct bnx2x_func_state_params func_params = {NULL};
34f80b04 8877
619c5cb6
VZ		 8878 /* Prepare parameters for function state transitions */
8879 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 8880
619c5cb6
VZ		 8881 func_params.f_obj = &bp->func_obj;
8882 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 8883
619c5cb6 8884 func_params.params.hw_init.load_phase = load_code;
49d66772 8885
619c5cb6 8886 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 8887}
8888
1191cb83 8889static int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 8890{
3b603066 8891 struct bnx2x_func_state_params func_params = {NULL};
619c5cb6 8892 int rc;
228241eb 8893
619c5cb6
VZ		 8894 /* Prepare parameters for function state transitions */
8895 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8896 func_params.f_obj = &bp->func_obj;
8897 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 8898
619c5cb6
VZ		 8899 /*
8900 * Try to stop the function the 'good way'. If fails (in case
8901 * of a parity error during bnx2x_chip_cleanup()) and we are
8902 * not in a debug mode, perform a state transaction in order to
8903 * enable further HW_RESET transaction.
8904 */
8905 rc = bnx2x_func_state_change(bp, &func_params);
8906 if (rc) {
34f80b04 8907#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 8908 return rc;
34f80b04 8909#else
51c1a580 8910 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
619c5cb6
VZ		 8911 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8912 return bnx2x_func_state_change(bp, &func_params);
34f80b04 8913#endif
228241eb 8914 }
a2fbb9ea 8915
619c5cb6
VZ		 8916 return 0;
8917}
523224a3 8918
619c5cb6
VZ		 8919/**
8920 * bnx2x_send_unload_req - request unload mode from the MCP.
8921 *
8922 * @bp: driver handle
8923 * @unload_mode: requested function's unload mode
8924 *
8925 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8926 */
8927u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8928{
8929 u32 reset_code = 0;
8930 int port = BP_PORT(bp);
3101c2bc 8931
619c5cb6 8932 /* Select the UNLOAD request mode */
65abd74d
YG		 8933 if (unload_mode == UNLOAD_NORMAL)
8934 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8935
7d0446c2 8936 else if (bp->flags & NO_WOL_FLAG)
65abd74d 8937 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 8938
7d0446c2 8939 else if (bp->wol) {
65abd74d
YG		 8940 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8941 u8 *mac_addr = bp->dev->dev_addr;
29ed74c3 8942 struct pci_dev *pdev = bp->pdev;
65abd74d 8943 u32 val;
f9977903
DK		 8944 u16 pmc;
8945
65abd74d 8946 /* The mac address is written to entries 1-4 to
f9977903
DK		 8947 * preserve entry 0 which is used by the PMF
8948 */
3395a033 8949 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 8950
8951 val = (mac_addr[0] << 8) | mac_addr[1];
8952 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8953
8954 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8955 (mac_addr[4] << 8) | mac_addr[5];
8956 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8957
f9977903 8958 /* Enable the PME and clear the status */
29ed74c3 8959 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
f9977903 8960 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
29ed74c3 8961 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
f9977903 8962
65abd74d
YG		 8963 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8964
8965 } else
8966 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 8967
619c5cb6
VZ		 8968 /* Send the request to the MCP */
8969 if (!BP_NOMCP(bp))
8970 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8971 else {
8972 int path = BP_PATH(bp);
8973
51c1a580 8974 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
a8f47eb7 8975 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8976 bnx2x_load_count[path][2]);
8977 bnx2x_load_count[path][0]--;
8978 bnx2x_load_count[path][1 + port]--;
51c1a580 8979 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
a8f47eb7 8980 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8981 bnx2x_load_count[path][2]);
8982 if (bnx2x_load_count[path][0] == 0)
619c5cb6 8983 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
a8f47eb7 8984 else if (bnx2x_load_count[path][1 + port] == 0)
619c5cb6
VZ		 8985 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8986 else
8987 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8988 }
8989
8990 return reset_code;
8991}
8992
8993/**
8994 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8995 *
8996 * @bp: driver handle
5d07d868 8997 * @keep_link: true iff link should be kept up
619c5cb6 8998 */
5d07d868 8999void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
619c5cb6 9000{
5d07d868
YM		 9001 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9002
619c5cb6
VZ		 9003 /* Report UNLOAD_DONE to MCP */
9004 if (!BP_NOMCP(bp))
5d07d868 9005 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
619c5cb6
VZ		 9006}
9007
1191cb83 9008static int bnx2x_func_wait_started(struct bnx2x *bp)
6debea87
DK		 9009{
9010 int tout = 50;
9011 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9012
9013 if (!bp->port.pmf)
9014 return 0;
9015
9016 /*
9017 * (assumption: No Attention from MCP at this stage)
16a5fd92 9018 * PMF probably in the middle of TX disable/enable transaction
6debea87 9019 * 1. Sync IRS for default SB
16a5fd92
YM		 9020 * 2. Sync SP queue - this guarantees us that attention handling started
9021 * 3. Wait, that TX disable/enable transaction completes
6debea87 9022 *
16a5fd92
YM		 9023 * 1+2 guarantee that if DCBx attention was scheduled it already changed
9024 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9025 * received completion for the transaction the state is TX_STOPPED.
6debea87
DK		 9026 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9027 * transaction.
9028 */
9029
9030 /* make sure default SB ISR is done */
9031 if (msix)
9032 synchronize_irq(bp->msix_table[0].vector);
9033 else
9034 synchronize_irq(bp->pdev->irq);
9035
9036 flush_workqueue(bnx2x_wq);
370d4a26 9037 flush_workqueue(bnx2x_iov_wq);
6debea87
DK		 9038
9039 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9040 BNX2X_F_STATE_STARTED && tout--)
9041 msleep(20);
9042
9043 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9044 BNX2X_F_STATE_STARTED) {
9045#ifdef BNX2X_STOP_ON_ERROR
51c1a580 9046 BNX2X_ERR("Wrong function state\n");
6debea87
DK		 9047 return -EBUSY;
9048#else
9049 /*
9050 * Failed to complete the transaction in a "good way"
9051 * Force both transactions with CLR bit
9052 */
3b603066 9053 struct bnx2x_func_state_params func_params = {NULL};
6debea87 9054
51c1a580 9055 DP(NETIF_MSG_IFDOWN,
0c23ad37 9056 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
6debea87
DK		 9057
9058 func_params.f_obj = &bp->func_obj;
9059 __set_bit(RAMROD_DRV_CLR_ONLY,
9060 &func_params.ramrod_flags);
9061
9062 /* STARTED-->TX_ST0PPED */
9063 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9064 bnx2x_func_state_change(bp, &func_params);
9065
9066 /* TX_ST0PPED-->STARTED */
9067 func_params.cmd = BNX2X_F_CMD_TX_START;
9068 return bnx2x_func_state_change(bp, &func_params);
9069#endif
9070 }
9071
9072 return 0;
9073}
9074
eeed018c
MK		 9075static void bnx2x_disable_ptp(struct bnx2x *bp)
9076{
9077 int port = BP_PORT(bp);
9078
9079 /* Disable sending PTP packets to host */
9080 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9081 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9082
9083 /* Reset PTP event detection rules */
9084 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9085 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9086 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9087 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9088 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9089 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9090 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9091 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9092
9093 /* Disable the PTP feature */
9094 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9095 NIG_REG_P0_PTP_EN, 0x0);
9096}
9097
9098/* Called during unload, to stop PTP-related stuff */
9099void bnx2x_stop_ptp(struct bnx2x *bp)
9100{
9101 /* Cancel PTP work queue. Should be done after the Tx queues are
9102 * drained to prevent additional scheduling.
9103 */
9104 cancel_work_sync(&bp->ptp_task);
9105
9106 if (bp->ptp_tx_skb) {
9107 dev_kfree_skb_any(bp->ptp_tx_skb);
9108 bp->ptp_tx_skb = NULL;
9109 }
9110
9111 /* Disable PTP in HW */
9112 bnx2x_disable_ptp(bp);
9113
9114 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9115}
9116
5d07d868 9117void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
619c5cb6
VZ		 9118{
9119 int port = BP_PORT(bp);
6383c0b3
AE		 9120 int i, rc = 0;
9121 u8 cos;
3b603066 9122 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6
VZ		 9123 u32 reset_code;
9124
9125 /* Wait until tx fastpath tasks complete */
9126 for_each_tx_queue(bp, i) {
9127 struct bnx2x_fastpath *fp = &bp->fp[i];
9128
6383c0b3 9129 for_each_cos_in_tx_queue(fp, cos)
65565884 9130 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
619c5cb6
VZ		 9131#ifdef BNX2X_STOP_ON_ERROR
9132 if (rc)
9133 return;
9134#endif
9135 }
9136
9137 /* Give HW time to discard old tx messages */
0926d499 9138 usleep_range(1000, 2000);
619c5cb6
VZ		 9139
9140 /* Clean all ETH MACs */
15192a8c
BW		 9141 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9142 false);
619c5cb6
VZ		 9143 if (rc < 0)
9144 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9145
9146 /* Clean up UC list */
15192a8c 9147 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
619c5cb6
VZ		 9148 true);
9149 if (rc < 0)
51c1a580
MS		 9150 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9151 rc);
619c5cb6
VZ		 9152
9153 /* Disable LLH */
9154 if (!CHIP_IS_E1(bp))
9155 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9156
9157 /* Set "drop all" (stop Rx).
9158 * We need to take a netif_addr_lock() here in order to prevent
9159 * a race between the completion code and this code.
9160 */
9161 netif_addr_lock_bh(bp->dev);
9162 /* Schedule the rx_mode command */
9163 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9164 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9165 else
9166 bnx2x_set_storm_rx_mode(bp);
9167
9168 /* Cleanup multicast configuration */
9169 rparam.mcast_obj = &bp->mcast_obj;
9170 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9171 if (rc < 0)
9172 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9173
9174 netif_addr_unlock_bh(bp->dev);
9175
f1929b01 9176 bnx2x_iov_chip_cleanup(bp);
619c5cb6 9177
6debea87
DK		 9178 /*
9179 * Send the UNLOAD_REQUEST to the MCP. This will return if
9180 * this function should perform FUNC, PORT or COMMON HW
9181 * reset.
9182 */
9183 reset_code = bnx2x_send_unload_req(bp, unload_mode);
9184
9185 /*
9186 * (assumption: No Attention from MCP at this stage)
16a5fd92 9187 * PMF probably in the middle of TX disable/enable transaction
6debea87
DK		 9188 */
9189 rc = bnx2x_func_wait_started(bp);
9190 if (rc) {
9191 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9192#ifdef BNX2X_STOP_ON_ERROR
9193 return;
9194#endif
9195 }
9196
34f80b04 9197 /* Close multi and leading connections
619c5cb6
VZ		 9198 * Completions for ramrods are collected in a synchronous way
9199 */
55c11941 9200 for_each_eth_queue(bp, i)
619c5cb6 9201 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 9202#ifdef BNX2X_STOP_ON_ERROR
9203 return;
9204#else
228241eb 9205 goto unload_error;
523224a3 9206#endif
55c11941
MS		 9207
9208 if (CNIC_LOADED(bp)) {
9209 for_each_cnic_queue(bp, i)
9210 if (bnx2x_stop_queue(bp, i))
9211#ifdef BNX2X_STOP_ON_ERROR
9212 return;
9213#else
9214 goto unload_error;
9215#endif
9216 }
9217
619c5cb6
VZ		 9218 /* If SP settings didn't get completed so far - something
9219 * very wrong has happen.
9220 */
9221 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9222 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 9223
619c5cb6
VZ		 9224#ifndef BNX2X_STOP_ON_ERROR
9225unload_error:
9226#endif
523224a3 9227 rc = bnx2x_func_stop(bp);
da5a662a 9228 if (rc) {
523224a3 9229 BNX2X_ERR("Function stop failed!\n");
da5a662a 9230#ifdef BNX2X_STOP_ON_ERROR
523224a3 9231 return;
523224a3 9232#endif
34f80b04 9233 }
a2fbb9ea 9234
eeed018c
MK		 9235 /* stop_ptp should be after the Tx queues are drained to prevent
9236 * scheduling to the cancelled PTP work queue. It should also be after
9237 * function stop ramrod is sent, since as part of this ramrod FW access
9238 * PTP registers.
9239 */
9240 bnx2x_stop_ptp(bp);
9241
523224a3
DK		 9242 /* Disable HW interrupts, NAPI */
9243 bnx2x_netif_stop(bp, 1);
26614ba5
MS		 9244 /* Delete all NAPI objects */
9245 bnx2x_del_all_napi(bp);
55c11941
MS		 9246 if (CNIC_LOADED(bp))
9247 bnx2x_del_all_napi_cnic(bp);
523224a3
DK		 9248
9249 /* Release IRQs */
d6214d7a 9250 bnx2x_free_irq(bp);
523224a3 9251
a2fbb9ea 9252 /* Reset the chip */
619c5cb6
VZ		 9253 rc = bnx2x_reset_hw(bp, reset_code);
9254 if (rc)
9255 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 9256
619c5cb6 9257 /* Report UNLOAD_DONE to MCP */
5d07d868 9258 bnx2x_send_unload_done(bp, keep_link);
72fd0718
VZ		 9259}
9260
9f6c9258 9261void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 9262{
9263 u32 val;
9264
51c1a580 9265 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
72fd0718
VZ		 9266
9267 if (CHIP_IS_E1(bp)) {
9268 int port = BP_PORT(bp);
9269 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9270 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9271
9272 val = REG_RD(bp, addr);
9273 val &= ~(0x300);
9274 REG_WR(bp, addr, val);
619c5cb6 9275 } else {
72fd0718
VZ		 9276 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9277 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9278 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9279 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9280 }
9281}
9282
72fd0718
VZ		 9283/* Close gates #2, #3 and #4: */
9284static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9285{
c9ee9206 9286 u32 val;
72fd0718
VZ		 9287
9288 /* Gates #2 and #4a are closed/opened for "not E1" only */
9289 if (!CHIP_IS_E1(bp)) {
9290 /* #4 */
c9ee9206 9291 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 9292 /* #2 */
c9ee9206 9293 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 9294 }
9295
9296 /* #3 */
c9ee9206
VZ		 9297 if (CHIP_IS_E1x(bp)) {
9298 /* Prevent interrupts from HC on both ports */
9299 val = REG_RD(bp, HC_REG_CONFIG_1);
9300 REG_WR(bp, HC_REG_CONFIG_1,
9301 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9302 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9303
9304 val = REG_RD(bp, HC_REG_CONFIG_0);
9305 REG_WR(bp, HC_REG_CONFIG_0,
9306 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9307 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9308 } else {
d82603c6 9309 /* Prevent incoming interrupts in IGU */
c9ee9206
VZ		 9310 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9311
9312 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9313 (!close) ?
9314 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9315 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9316 }
72fd0718 9317
51c1a580 9318 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
72fd0718
VZ		 9319 close ? "closing" : "opening");
9320 mmiowb();
9321}
9322
9323#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9324
9325static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9326{
9327 /* Do some magic... */
9328 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9329 *magic_val = val & SHARED_MF_CLP_MAGIC;
9330 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9331}
9332
e8920674
DK		 9333/**
9334 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 9335 *
e8920674
DK		 9336 * @bp: driver handle
9337 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 9338 */
9339static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9340{
9341 /* Restore the `magic' bit value... */
72fd0718
VZ		 9342 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9343 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9344 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9345}
9346
f85582f8 9347/**
e8920674 9348 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 9349 *
e8920674
DK		 9350 * @bp: driver handle
9351 * @magic_val: old value of 'magic' bit.
9352 *
9353 * Takes care of CLP configurations.
72fd0718
VZ		 9354 */
9355static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9356{
9357 u32 shmem;
9358 u32 validity_offset;
9359
51c1a580 9360 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
72fd0718
VZ		 9361
9362 /* Set `magic' bit in order to save MF config */
9363 if (!CHIP_IS_E1(bp))
9364 bnx2x_clp_reset_prep(bp, magic_val);
9365
9366 /* Get shmem offset */
9367 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
c55e771b
BW		 9368 validity_offset =
9369 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
72fd0718
VZ		 9370
9371 /* Clear validity map flags */
9372 if (shmem > 0)
9373 REG_WR(bp, shmem + validity_offset, 0);
9374}
9375
9376#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9377#define MCP_ONE_TIMEOUT 100 /* 100 ms */
9378
e8920674
DK		 9379/**
9380 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 9381 *
e8920674 9382 * @bp: driver handle
72fd0718 9383 */
1191cb83 9384static void bnx2x_mcp_wait_one(struct bnx2x *bp)
72fd0718
VZ		 9385{
9386 /* special handling for emulation and FPGA,
9387 wait 10 times longer */
9388 if (CHIP_REV_IS_SLOW(bp))
9389 msleep(MCP_ONE_TIMEOUT*10);
9390 else
9391 msleep(MCP_ONE_TIMEOUT);
9392}
9393
1b6e2ceb
DK		 9394/*
9395 * initializes bp->common.shmem_base and waits for validity signature to appear
9396 */
9397static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 9398{
1b6e2ceb
DK		 9399 int cnt = 0;
9400 u32 val = 0;
72fd0718 9401
1b6e2ceb
DK		 9402 do {
9403 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9404 if (bp->common.shmem_base) {
9405 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9406 if (val & SHR_MEM_VALIDITY_MB)
9407 return 0;
9408 }
72fd0718 9409
1b6e2ceb 9410 bnx2x_mcp_wait_one(bp);
72fd0718 9411
1b6e2ceb 9412 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 9413
1b6e2ceb 9414 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 9415
1b6e2ceb
DK		 9416 return -ENODEV;
9417}
72fd0718 9418
1b6e2ceb
DK		 9419static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9420{
9421 int rc = bnx2x_init_shmem(bp);
72fd0718 9422
72fd0718
VZ		 9423 /* Restore the `magic' bit value */
9424 if (!CHIP_IS_E1(bp))
9425 bnx2x_clp_reset_done(bp, magic_val);
9426
9427 return rc;
9428}
9429
9430static void bnx2x_pxp_prep(struct bnx2x *bp)
9431{
9432 if (!CHIP_IS_E1(bp)) {
9433 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9434 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 9435 mmiowb();
9436 }
9437}
9438
9439/*
9440 * Reset the whole chip except for:
9441 * - PCIE core
9442 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9443 * one reset bit)
9444 * - IGU
9445 * - MISC (including AEU)
9446 * - GRC
9447 * - RBCN, RBCP
9448 */
c9ee9206 9449static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 9450{
9451 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 9452 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 9453
9454 /*
9455 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9456 * (per chip) blocks.
9457 */
9458 global_bits2 =
9459 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9460 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 9461
c55e771b
BW		 9462 /* Don't reset the following blocks.
9463 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9464 * reset, as in 4 port device they might still be owned
9465 * by the MCP (there is only one leader per path).
9466 */
72fd0718
VZ		 9467 not_reset_mask1 =
9468 MISC_REGISTERS_RESET_REG_1_RST_HC |
9469 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9470 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9471
9472 not_reset_mask2 =
c9ee9206 9473 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 9474 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9475 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9476 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9477 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9478 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9479 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 9480 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9481 MISC_REGISTERS_RESET_REG_2_RST_ATC |
c55e771b
BW		 9482 MISC_REGISTERS_RESET_REG_2_PGLC |
9483 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9484 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9485 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9486 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9487 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9488 MISC_REGISTERS_RESET_REG_2_UMAC1;
72fd0718 9489
8736c826
VZ		 9490 /*
9491 * Keep the following blocks in reset:
9492 * - all xxMACs are handled by the bnx2x_link code.
9493 */
9494 stay_reset2 =
8736c826
VZ		 9495 MISC_REGISTERS_RESET_REG_2_XMAC |
9496 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9497
9498 /* Full reset masks according to the chip */
72fd0718
VZ		 9499 reset_mask1 = 0xffffffff;
9500
9501 if (CHIP_IS_E1(bp))
9502 reset_mask2 = 0xffff;
8736c826 9503 else if (CHIP_IS_E1H(bp))
72fd0718 9504 reset_mask2 = 0x1ffff;
8736c826
VZ		 9505 else if (CHIP_IS_E2(bp))
9506 reset_mask2 = 0xfffff;
9507 else /* CHIP_IS_E3 */
9508 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 9509
9510 /* Don't reset global blocks unless we need to */
9511 if (!global)
9512 reset_mask2 &= ~global_bits2;
9513
9514 /*
9515 * In case of attention in the QM, we need to reset PXP
9516 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9517 * because otherwise QM reset would release 'close the gates' shortly
9518 * before resetting the PXP, then the PSWRQ would send a write
9519 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9520 * read the payload data from PSWWR, but PSWWR would not
9521 * respond. The write queue in PGLUE would stuck, dmae commands
9522 * would not return. Therefore it's important to reset the second
9523 * reset register (containing the
9524 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9525 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9526 * bit).
9527 */
72fd0718
VZ		 9528 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9529 reset_mask2 & (~not_reset_mask2));
9530
c9ee9206
VZ		 9531 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9532 reset_mask1 & (~not_reset_mask1));
9533
72fd0718
VZ		 9534 barrier();
9535 mmiowb();
9536
8736c826
VZ		 9537 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9538 reset_mask2 & (~stay_reset2));
9539
9540 barrier();
9541 mmiowb();
9542
c9ee9206 9543 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 9544 mmiowb();
9545}
9546
c9ee9206
VZ		 9547/**
9548 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9549 * It should get cleared in no more than 1s.
9550 *
9551 * @bp: driver handle
9552 *
9553 * It should get cleared in no more than 1s. Returns 0 if
9554 * pending writes bit gets cleared.
9555 */
9556static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9557{
9558 u32 cnt = 1000;
9559 u32 pend_bits = 0;
9560
9561 do {
9562 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9563
9564 if (pend_bits == 0)
9565 break;
9566
0926d499 9567 usleep_range(1000, 2000);
c9ee9206
VZ		 9568 } while (cnt-- > 0);
9569
9570 if (cnt <= 0) {
9571 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9572 pend_bits);
9573 return -EBUSY;
9574 }
9575
9576 return 0;
9577}
9578
9579static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 9580{
9581 int cnt = 1000;
9582 u32 val = 0;
9583 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
2de67439 9584 u32 tags_63_32 = 0;
72fd0718
VZ		 9585
9586 /* Empty the Tetris buffer, wait for 1s */
9587 do {
9588 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9589 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9590 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9591 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9592 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
c55e771b
BW		 9593 if (CHIP_IS_E3(bp))
9594 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9595
72fd0718
VZ		 9596 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9597 ((port_is_idle_0 & 0x1) == 0x1) &&
9598 ((port_is_idle_1 & 0x1) == 0x1) &&
c55e771b
BW		 9599 (pgl_exp_rom2 == 0xffffffff) &&
9600 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
72fd0718 9601 break;
0926d499 9602 usleep_range(1000, 2000);
72fd0718
VZ		 9603 } while (cnt-- > 0);
9604
9605 if (cnt <= 0) {
51c1a580
MS		 9606 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9607 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
72fd0718
VZ		 9608 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9609 pgl_exp_rom2);
9610 return -EAGAIN;
9611 }
9612
9613 barrier();
9614
9615 /* Close gates #2, #3 and #4 */
9616 bnx2x_set_234_gates(bp, true);
9617
c9ee9206
VZ		 9618 /* Poll for IGU VQs for 57712 and newer chips */
9619 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9620 return -EAGAIN;
9621
72fd0718
VZ		 9622 /* TBD: Indicate that "process kill" is in progress to MCP */
9623
9624 /* Clear "unprepared" bit */
9625 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9626 barrier();
9627
9628 /* Make sure all is written to the chip before the reset */
9629 mmiowb();
9630
9631 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9632 * PSWHST, GRC and PSWRD Tetris buffer.
9633 */
0926d499 9634 usleep_range(1000, 2000);
72fd0718
VZ		 9635
9636 /* Prepare to chip reset: */
9637 /* MCP */
c9ee9206
VZ		 9638 if (global)
9639 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 9640
9641 /* PXP */
9642 bnx2x_pxp_prep(bp);
9643 barrier();
9644
9645 /* reset the chip */
c9ee9206 9646 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 9647 barrier();
9648
9dcd9acd
DK		 9649 /* clear errors in PGB */
9650 if (!CHIP_IS_E1x(bp))
9651 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9652
72fd0718
VZ		 9653 /* Recover after reset: */
9654 /* MCP */
c9ee9206 9655 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 9656 return -EAGAIN;
9657
c9ee9206
VZ		 9658 /* TBD: Add resetting the NO_MCP mode DB here */
9659
72fd0718
VZ		 9660 /* Open the gates #2, #3 and #4 */
9661 bnx2x_set_234_gates(bp, false);
9662
9663 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9664 * reset state, re-enable attentions. */
9665
a2fbb9ea
ET		 9666 return 0;
9667}
9668
910cc727 9669static int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 9670{
9671 int rc = 0;
c9ee9206 9672 bool global = bnx2x_reset_is_global(bp);
95c6c616
AE		 9673 u32 load_code;
9674
9675 /* if not going to reset MCP - load "fake" driver to reset HW while
9676 * driver is owner of the HW
9677 */
9678 if (!global && !BP_NOMCP(bp)) {
5d07d868
YM		 9679 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9680 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
95c6c616
AE		 9681 if (!load_code) {
9682 BNX2X_ERR("MCP response failure, aborting\n");
9683 rc = -EAGAIN;
9684 goto exit_leader_reset;
9685 }
9686 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9687 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9688 BNX2X_ERR("MCP unexpected resp, aborting\n");
9689 rc = -EAGAIN;
9690 goto exit_leader_reset2;
9691 }
9692 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9693 if (!load_code) {
9694 BNX2X_ERR("MCP response failure, aborting\n");
9695 rc = -EAGAIN;
9696 goto exit_leader_reset2;
9697 }
9698 }
c9ee9206 9699
72fd0718 9700 /* Try to recover after the failure */
c9ee9206 9701 if (bnx2x_process_kill(bp, global)) {
51c1a580
MS		 9702 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9703 BP_PATH(bp));
72fd0718 9704 rc = -EAGAIN;
95c6c616 9705 goto exit_leader_reset2;
72fd0718
VZ		 9706 }
9707
c9ee9206
VZ		 9708 /*
9709 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9710 * state.
9711 */
72fd0718 9712 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 9713 if (global)
9714 bnx2x_clear_reset_global(bp);
72fd0718 9715
95c6c616
AE		 9716exit_leader_reset2:
9717 /* unload "fake driver" if it was loaded */
9718 if (!global && !BP_NOMCP(bp)) {
9719 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9720 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9721 }
72fd0718
VZ		 9722exit_leader_reset:
9723 bp->is_leader = 0;
c9ee9206
VZ		 9724 bnx2x_release_leader_lock(bp);
9725 smp_mb();
72fd0718
VZ		 9726 return rc;
9727}
9728
1191cb83 9729static void bnx2x_recovery_failed(struct bnx2x *bp)
c9ee9206
VZ		 9730{
9731 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9732
9733 /* Disconnect this device */
9734 netif_device_detach(bp->dev);
9735
9736 /*
9737 * Block ifup for all function on this engine until "process kill"
9738 * or power cycle.
9739 */
9740 bnx2x_set_reset_in_progress(bp);
9741
9742 /* Shut down the power */
9743 bnx2x_set_power_state(bp, PCI_D3hot);
9744
9745 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9746
9747 smp_mb();
9748}
9749
9750/*
9751 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 9752 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 9753 * will never be called when netif_running(bp->dev) is false.
9754 */
9755static void bnx2x_parity_recover(struct bnx2x *bp)
9756{
c9ee9206 9757 bool global = false;
7a752993 9758 u32 error_recovered, error_unrecovered;
95c6c616 9759 bool is_parity;
c9ee9206 9760
72fd0718
VZ		 9761 DP(NETIF_MSG_HW, "Handling parity\n");
9762 while (1) {
9763 switch (bp->recovery_state) {
9764 case BNX2X_RECOVERY_INIT:
9765 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
95c6c616
AE		 9766 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9767 WARN_ON(!is_parity);
c9ee9206 9768
72fd0718 9769 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 9770 if (bnx2x_trylock_leader_lock(bp)) {
9771 bnx2x_set_reset_in_progress(bp);
9772 /*
9773 * Check if there is a global attention and if
9774 * there was a global attention, set the global
9775 * reset bit.
9776 */
9777
9778 if (global)
9779 bnx2x_set_reset_global(bp);
9780
72fd0718 9781 bp->is_leader = 1;
c9ee9206 9782 }
72fd0718
VZ		 9783
9784 /* Stop the driver */
9785 /* If interface has been removed - break */
5d07d868 9786 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
72fd0718
VZ		 9787 return;
9788
9789 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206 9790
c9ee9206
VZ		 9791 /* Ensure "is_leader", MCP command sequence and
9792 * "recovery_state" update values are seen on other
9793 * CPUs.
72fd0718 9794 */
c9ee9206 9795 smp_mb();
72fd0718
VZ		 9796 break;
9797
9798 case BNX2X_RECOVERY_WAIT:
9799 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9800 if (bp->is_leader) {
c9ee9206 9801 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3
AE		 9802 bool other_load_status =
9803 bnx2x_get_load_status(bp, other_engine);
9804 bool load_status =
9805 bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 9806 global = bnx2x_reset_is_global(bp);
9807
9808 /*
9809 * In case of a parity in a global block, let
9810 * the first leader that performs a
9811 * leader_reset() reset the global blocks in
9812 * order to clear global attentions. Otherwise
16a5fd92 9813 * the gates will remain closed for that
c9ee9206
VZ		 9814 * engine.
9815 */
889b9af3
AE		 9816 if (load_status ||
9817 (global && other_load_status)) {
72fd0718
VZ		 9818 /* Wait until all other functions get
9819 * down.
9820 */
7be08a72 9821 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9822 HZ/10);
9823 return;
9824 } else {
9825 /* If all other functions got down -
9826 * try to bring the chip back to
9827 * normal. In any case it's an exit
9828 * point for a leader.
9829 */
c9ee9206
VZ		 9830 if (bnx2x_leader_reset(bp)) {
9831 bnx2x_recovery_failed(bp);
72fd0718
VZ		 9832 return;
9833 }
9834
c9ee9206
VZ		 9835 /* If we are here, means that the
9836 * leader has succeeded and doesn't
9837 * want to be a leader any more. Try
9838 * to continue as a none-leader.
9839 */
9840 break;
72fd0718
VZ		 9841 }
9842 } else { /* non-leader */
c9ee9206 9843 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 9844 /* Try to get a LEADER_LOCK HW lock as
9845 * long as a former leader may have
9846 * been unloaded by the user or
9847 * released a leadership by another
9848 * reason.
9849 */
c9ee9206 9850 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 9851 /* I'm a leader now! Restart a
9852 * switch case.
9853 */
9854 bp->is_leader = 1;
9855 break;
9856 }
9857
7be08a72 9858 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9859 HZ/10);
9860 return;
9861
c9ee9206
VZ		 9862 } else {
9863 /*
9864 * If there was a global attention, wait
9865 * for it to be cleared.
9866 */
9867 if (bnx2x_reset_is_global(bp)) {
9868 schedule_delayed_work(
7be08a72
AE		 9869 &bp->sp_rtnl_task,
9870 HZ/10);
c9ee9206
VZ		 9871 return;
9872 }
9873
7a752993
AE		 9874 error_recovered =
9875 bp->eth_stats.recoverable_error;
9876 error_unrecovered =
9877 bp->eth_stats.unrecoverable_error;
95c6c616
AE		 9878 bp->recovery_state =
9879 BNX2X_RECOVERY_NIC_LOADING;
9880 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
7a752993 9881 error_unrecovered++;
95c6c616 9882 netdev_err(bp->dev,
51c1a580 9883 "Recovery failed. Power cycle needed\n");
95c6c616
AE		 9884 /* Disconnect this device */
9885 netif_device_detach(bp->dev);
9886 /* Shut down the power */
9887 bnx2x_set_power_state(
9888 bp, PCI_D3hot);
9889 smp_mb();
9890 } else {
c9ee9206
VZ		 9891 bp->recovery_state =
9892 BNX2X_RECOVERY_DONE;
7a752993 9893 error_recovered++;
c9ee9206
VZ		 9894 smp_mb();
9895 }
7a752993
AE		 9896 bp->eth_stats.recoverable_error =
9897 error_recovered;
9898 bp->eth_stats.unrecoverable_error =
9899 error_unrecovered;
c9ee9206 9900
72fd0718
VZ		 9901 return;
9902 }
9903 }
9904 default:
9905 return;
9906 }
9907 }
9908}
9909
56ad3152
MS		 9910static int bnx2x_close(struct net_device *dev);
9911
72fd0718
VZ		 9912/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9913 * scheduled on a general queue in order to prevent a dead lock.
9914 */
7be08a72 9915static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 9916{
7be08a72 9917 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 9918
9919 rtnl_lock();
9920
8395be5e
AE		 9921 if (!netif_running(bp->dev)) {
9922 rtnl_unlock();
9923 return;
9924 }
7be08a72 9925
6bf07b8e 9926 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
7be08a72 9927#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e
YM		 9928 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9929 "you will need to reboot when done\n");
9930 goto sp_rtnl_not_reset;
7be08a72 9931#endif
7be08a72 9932 /*
b1fb8740
VZ		 9933 * Clear all pending SP commands as we are going to reset the
9934 * function anyway.
7be08a72 9935 */
b1fb8740
VZ		 9936 bp->sp_rtnl_state = 0;
9937 smp_mb();
9938
72fd0718 9939 bnx2x_parity_recover(bp);
b1fb8740 9940
8395be5e
AE		 9941 rtnl_unlock();
9942 return;
b1fb8740
VZ		 9943 }
9944
9945 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
6bf07b8e
YM		 9946#ifdef BNX2X_STOP_ON_ERROR
9947 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9948 "you will need to reboot when done\n");
9949 goto sp_rtnl_not_reset;
9950#endif
9951
b1fb8740
VZ		 9952 /*
9953 * Clear all pending SP commands as we are going to reset the
9954 * function anyway.
9955 */
9956 bp->sp_rtnl_state = 0;
9957 smp_mb();
9958
5d07d868 9959 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
72fd0718 9960 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740 9961
8395be5e
AE		 9962 rtnl_unlock();
9963 return;
72fd0718 9964 }
b1fb8740
VZ		 9965#ifdef BNX2X_STOP_ON_ERROR
9966sp_rtnl_not_reset:
9967#endif
9968 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9969 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
a3348722
BW		 9970 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9971 bnx2x_after_function_update(bp);
8304859a
AE		 9972 /*
9973 * in case of fan failure we need to reset id if the "stop on error"
9974 * debug flag is set, since we trying to prevent permanent overheating
9975 * damage
9976 */
9977 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
51c1a580 9978 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
8304859a
AE		 9979 netif_device_detach(bp->dev);
9980 bnx2x_close(bp->dev);
8395be5e
AE		 9981 rtnl_unlock();
9982 return;
8304859a
AE		 9983 }
9984
381ac16b
AE		 9985 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9986 DP(BNX2X_MSG_SP,
9987 "sending set mcast vf pf channel message from rtnl sp-task\n");
9988 bnx2x_vfpf_set_mcast(bp->dev);
9989 }
78c3bcc5
AE		 9990 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9991 &bp->sp_rtnl_state)){
9992 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9993 bnx2x_tx_disable(bp);
9994 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9995 }
9996 }
381ac16b 9997
8b09be5f
YM		 9998 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
9999 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10000 bnx2x_set_rx_mode_inner(bp);
381ac16b
AE		 10001 }
10002
3ec9f9ca
AE		 10003 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10004 &bp->sp_rtnl_state))
10005 bnx2x_pf_set_vfs_vlan(bp);
10006
6ffa39f2 10007 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
07b4eb3b 10008 bnx2x_dcbx_stop_hw_tx(bp);
07b4eb3b 10009 bnx2x_dcbx_resume_hw_tx(bp);
6ffa39f2 10010 }
07b4eb3b 10011
42f8277f
YM		 10012 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10013 &bp->sp_rtnl_state))
10014 bnx2x_update_mng_version(bp);
10015
8395be5e
AE		 10016 /* work which needs rtnl lock not-taken (as it takes the lock itself and
10017 * can be called from other contexts as well)
10018 */
34f80b04 10019 rtnl_unlock();
8395be5e 10020
6411280a 10021 /* enable SR-IOV if applicable */
8395be5e 10022 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
3c76feff
AE		 10023 &bp->sp_rtnl_state)) {
10024 bnx2x_disable_sriov(bp);
6411280a 10025 bnx2x_enable_sriov(bp);
3c76feff 10026 }
34f80b04
EG		 10027}
10028
3deb8167
YR		 10029static void bnx2x_period_task(struct work_struct *work)
10030{
10031 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10032
10033 if (!netif_running(bp->dev))
10034 goto period_task_exit;
10035
10036 if (CHIP_REV_IS_SLOW(bp)) {
10037 BNX2X_ERR("period task called on emulation, ignoring\n");
10038 goto period_task_exit;
10039 }
10040
10041 bnx2x_acquire_phy_lock(bp);
10042 /*
10043 * The barrier is needed to ensure the ordering between the writing to
10044 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10045 * the reading here.
10046 */
10047 smp_mb();
10048 if (bp->port.pmf) {
10049 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10050
10051 /* Re-queue task in 1 sec */
10052 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10053 }
10054
10055 bnx2x_release_phy_lock(bp);
10056period_task_exit:
10057 return;
10058}
10059
a2fbb9ea
ET		 10060/*
10061 * Init service functions
10062 */
10063
a8f47eb7 10064static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 10065{
10066 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10067 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10068 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 10069}
10070
1ef1d45a
BW		 10071static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10072 struct bnx2x_mac_vals *vals)
34f80b04 10073{
452427b0
YM		 10074 u32 val, base_addr, offset, mask, reset_reg;
10075 bool mac_stopped = false;
10076 u8 port = BP_PORT(bp);
34f80b04 10077
1ef1d45a
BW		 10078 /* reset addresses as they also mark which values were changed */
10079 vals->bmac_addr = 0;
10080 vals->umac_addr = 0;
10081 vals->xmac_addr = 0;
10082 vals->emac_addr = 0;
10083
452427b0 10084 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
f16da43b 10085
452427b0
YM		 10086 if (!CHIP_IS_E3(bp)) {
10087 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10088 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10089 if ((mask & reset_reg) && val) {
10090 u32 wb_data[2];
10091 BNX2X_DEV_INFO("Disable bmac Rx\n");
10092 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10093 : NIG_REG_INGRESS_BMAC0_MEM;
10094 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10095 : BIGMAC_REGISTER_BMAC_CONTROL;
7a06a122 10096
452427b0
YM		 10097 /*
10098 * use rd/wr since we cannot use dmae. This is safe
10099 * since MCP won't access the bus due to the request
10100 * to unload, and no function on the path can be
10101 * loaded at this time.
10102 */
10103 wb_data[0] = REG_RD(bp, base_addr + offset);
10104 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
1ef1d45a
BW		 10105 vals->bmac_addr = base_addr + offset;
10106 vals->bmac_val[0] = wb_data[0];
10107 vals->bmac_val[1] = wb_data[1];
452427b0 10108 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1ef1d45a
BW		 10109 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10110 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
452427b0
YM		 10111 }
10112 BNX2X_DEV_INFO("Disable emac Rx\n");
1ef1d45a
BW		 10113 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10114 vals->emac_val = REG_RD(bp, vals->emac_addr);
10115 REG_WR(bp, vals->emac_addr, 0);
452427b0
YM		 10116 mac_stopped = true;
10117 } else {
10118 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10119 BNX2X_DEV_INFO("Disable xmac Rx\n");
10120 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10121 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10122 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10123 val & ~(1 << 1));
10124 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10125 val | (1 << 1));
1ef1d45a
BW		 10126 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10127 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10128 REG_WR(bp, vals->xmac_addr, 0);
452427b0
YM		 10129 mac_stopped = true;
10130 }
10131 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10132 if (mask & reset_reg) {
10133 BNX2X_DEV_INFO("Disable umac Rx\n");
10134 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1ef1d45a
BW		 10135 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
10136 vals->umac_val = REG_RD(bp, vals->umac_addr);
10137 REG_WR(bp, vals->umac_addr, 0);
452427b0
YM		 10138 mac_stopped = true;
10139 }
10140 }
10141
10142 if (mac_stopped)
10143 msleep(20);
452427b0
YM		 10144}
10145
10146#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10147#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10148#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10149#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10150
91ebb929
YM		 10151#define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10152#define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10153#define BCM_5710_UNDI_FW_MF_VERS (0x05)
de682941
YM		 10154#define BNX2X_PREV_UNDI_MF_PORT(p) (BAR_TSTRORM_INTMEM + 0x150c + ((p) << 4))
10155#define BNX2X_PREV_UNDI_MF_FUNC(f) (BAR_TSTRORM_INTMEM + 0x184c + ((f) << 4))
b17b0ca1
YM		 10156
10157static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10158{
10159 /* UNDI marks its presence in DORQ -
10160 * it initializes CID offset for normal bell to 0x7
10161 */
10162 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10163 MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10164 return false;
10165
10166 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10167 BNX2X_DEV_INFO("UNDI previously loaded\n");
10168 return true;
10169 }
10170
10171 return false;
10172}
10173
91ebb929
YM		 10174static bool bnx2x_prev_unload_undi_fw_supports_mf(struct bnx2x *bp)
10175{
10176 u8 major, minor, version;
10177 u32 fw;
10178
10179 /* Must check that FW is loaded */
10180 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10181 MISC_REGISTERS_RESET_REG_1_RST_XSEM)) {
10182 BNX2X_DEV_INFO("XSEM is reset - UNDI MF FW is not loaded\n");
10183 return false;
10184 }
10185
10186 /* Read Currently loaded FW version */
10187 fw = REG_RD(bp, XSEM_REG_PRAM);
10188 major = fw & 0xff;
10189 minor = (fw >> 0x8) & 0xff;
10190 version = (fw >> 0x10) & 0xff;
10191 BNX2X_DEV_INFO("Loaded FW: 0x%08x: Major 0x%02x Minor 0x%02x Version 0x%02x\n",
10192 fw, major, minor, version);
10193
10194 if (major > BCM_5710_UNDI_FW_MF_MAJOR)
10195 return true;
10196
10197 if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
10198 (minor > BCM_5710_UNDI_FW_MF_MINOR))
10199 return true;
10200
10201 if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
10202 (minor == BCM_5710_UNDI_FW_MF_MINOR) &&
10203 (version >= BCM_5710_UNDI_FW_MF_VERS))
10204 return true;
10205
10206 return false;
10207}
10208
10209static void bnx2x_prev_unload_undi_mf(struct bnx2x *bp)
10210{
10211 int i;
10212
10213 /* Due to legacy (FW) code, the first function on each engine has a
10214 * different offset macro from the rest of the functions.
10215 * Setting this for all 8 functions is harmless regardless of whether
10216 * this is actually a multi-function device.
10217 */
10218 for (i = 0; i < 2; i++)
10219 REG_WR(bp, BNX2X_PREV_UNDI_MF_PORT(i), 1);
10220
10221 for (i = 2; i < 8; i++)
10222 REG_WR(bp, BNX2X_PREV_UNDI_MF_FUNC(i - 2), 1);
10223
10224 BNX2X_DEV_INFO("UNDI FW (MF) set to discard\n");
10225}
10226
1dd06ae8 10227static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
452427b0
YM		 10228{
10229 u16 rcq, bd;
10230 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
10231
10232 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10233 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10234
10235 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10236 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
10237
10238 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10239 port, bd, rcq);
10240}
10241
0329aba1 10242static int bnx2x_prev_mcp_done(struct bnx2x *bp)
452427b0 10243{
5d07d868
YM		 10244 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10245 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
452427b0
YM		 10246 if (!rc) {
10247 BNX2X_ERR("MCP response failure, aborting\n");
10248 return -EBUSY;
10249 }
10250
10251 return 0;
10252}
10253
c63da990
BW		 10254static struct bnx2x_prev_path_list *
10255 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10256{
10257 struct bnx2x_prev_path_list *tmp_list;
10258
10259 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10260 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10261 bp->pdev->bus->number == tmp_list->bus &&
10262 BP_PATH(bp) == tmp_list->path)
10263 return tmp_list;
10264
10265 return NULL;
10266}
10267
7fa6f340
YM		 10268static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10269{
10270 struct bnx2x_prev_path_list *tmp_list;
10271 int rc;
10272
10273 rc = down_interruptible(&bnx2x_prev_sem);
10274 if (rc) {
10275 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10276 return rc;
10277 }
10278
10279 tmp_list = bnx2x_prev_path_get_entry(bp);
10280 if (tmp_list) {
10281 tmp_list->aer = 1;
10282 rc = 0;
10283 } else {
10284 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10285 BP_PATH(bp));
10286 }
10287
10288 up(&bnx2x_prev_sem);
10289
10290 return rc;
10291}
10292
0329aba1 10293static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
452427b0
YM		 10294{
10295 struct bnx2x_prev_path_list *tmp_list;
b85d717c 10296 bool rc = false;
452427b0
YM		 10297
10298 if (down_trylock(&bnx2x_prev_sem))
10299 return false;
10300
7fa6f340
YM		 10301 tmp_list = bnx2x_prev_path_get_entry(bp);
10302 if (tmp_list) {
10303 if (tmp_list->aer) {
10304 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10305 BP_PATH(bp));
10306 } else {
452427b0
YM		 10307 rc = true;
10308 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10309 BP_PATH(bp));
452427b0
YM		 10310 }
10311 }
10312
10313 up(&bnx2x_prev_sem);
10314
10315 return rc;
10316}
10317
178135c1
DK		 10318bool bnx2x_port_after_undi(struct bnx2x *bp)
10319{
10320 struct bnx2x_prev_path_list *entry;
10321 bool val;
10322
10323 down(&bnx2x_prev_sem);
10324
10325 entry = bnx2x_prev_path_get_entry(bp);
10326 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10327
10328 up(&bnx2x_prev_sem);
10329
10330 return val;
10331}
10332
c63da990 10333static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
452427b0
YM		 10334{
10335 struct bnx2x_prev_path_list *tmp_list;
10336 int rc;
10337
7fa6f340
YM		 10338 rc = down_interruptible(&bnx2x_prev_sem);
10339 if (rc) {
10340 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10341 return rc;
10342 }
10343
10344 /* Check whether the entry for this path already exists */
10345 tmp_list = bnx2x_prev_path_get_entry(bp);
10346 if (tmp_list) {
10347 if (!tmp_list->aer) {
10348 BNX2X_ERR("Re-Marking the path.\n");
10349 } else {
10350 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10351 BP_PATH(bp));
10352 tmp_list->aer = 0;
10353 }
10354 up(&bnx2x_prev_sem);
10355 return 0;
10356 }
10357 up(&bnx2x_prev_sem);
10358
10359 /* Create an entry for this path and add it */
ea4b3857 10360 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
452427b0
YM		 10361 if (!tmp_list) {
10362 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10363 return -ENOMEM;
10364 }
10365
10366 tmp_list->bus = bp->pdev->bus->number;
10367 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10368 tmp_list->path = BP_PATH(bp);
7fa6f340 10369 tmp_list->aer = 0;
c63da990 10370 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
452427b0
YM		 10371
10372 rc = down_interruptible(&bnx2x_prev_sem);
10373 if (rc) {
10374 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10375 kfree(tmp_list);
10376 } else {
7fa6f340
YM		 10377 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10378 BP_PATH(bp));
452427b0
YM		 10379 list_add(&tmp_list->list, &bnx2x_prev_list);
10380 up(&bnx2x_prev_sem);
10381 }
10382
10383 return rc;
10384}
10385
0329aba1 10386static int bnx2x_do_flr(struct bnx2x *bp)
452427b0 10387{
452427b0
YM		 10388 struct pci_dev *dev = bp->pdev;
10389
8eee694c
YM		 10390 if (CHIP_IS_E1x(bp)) {
10391 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10392 return -EINVAL;
10393 }
10394
10395 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10396 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10397 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10398 bp->common.bc_ver);
10399 return -EINVAL;
10400 }
452427b0 10401
8903b9eb
CL		 10402 if (!pci_wait_for_pending_transaction(dev))
10403 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
452427b0 10404
8eee694c 10405 BNX2X_DEV_INFO("Initiating FLR\n");
452427b0
YM		 10406 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10407
10408 return 0;
10409}
10410
0329aba1 10411static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
452427b0
YM		 10412{
10413 int rc;
10414
10415 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10416
10417 /* Test if previous unload process was already finished for this path */
10418 if (bnx2x_prev_is_path_marked(bp))
10419 return bnx2x_prev_mcp_done(bp);
10420
04c46736
YM		 10421 BNX2X_DEV_INFO("Path is unmarked\n");
10422
b17b0ca1
YM		 10423 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10424 if (bnx2x_prev_is_after_undi(bp))
10425 goto out;
10426
452427b0
YM		 10427 /* If function has FLR capabilities, and existing FW version matches
10428 * the one required, then FLR will be sufficient to clean any residue
10429 * left by previous driver
10430 */
91ebb929 10431 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
8eee694c
YM		 10432
10433 if (!rc) {
10434 /* fw version is good */
10435 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10436 rc = bnx2x_do_flr(bp);
10437 }
10438
10439 if (!rc) {
10440 /* FLR was performed */
10441 BNX2X_DEV_INFO("FLR successful\n");
10442 return 0;
10443 }
10444
10445 BNX2X_DEV_INFO("Could not FLR\n");
452427b0 10446
b17b0ca1 10447out:
452427b0
YM		 10448 /* Close the MCP request, return failure*/
10449 rc = bnx2x_prev_mcp_done(bp);
10450 if (!rc)
10451 rc = BNX2X_PREV_WAIT_NEEDED;
10452
10453 return rc;
10454}
10455
0329aba1 10456static int bnx2x_prev_unload_common(struct bnx2x *bp)
452427b0
YM		 10457{
10458 u32 reset_reg, tmp_reg = 0, rc;
c63da990 10459 bool prev_undi = false;
1ef1d45a
BW		 10460 struct bnx2x_mac_vals mac_vals;
10461
452427b0
YM		 10462 /* It is possible a previous function received 'common' answer,
10463 * but hasn't loaded yet, therefore creating a scenario of
10464 * multiple functions receiving 'common' on the same path.
10465 */
10466 BNX2X_DEV_INFO("Common unload Flow\n");
10467
1ef1d45a
BW		 10468 memset(&mac_vals, 0, sizeof(mac_vals));
10469
452427b0
YM		 10470 if (bnx2x_prev_is_path_marked(bp))
10471 return bnx2x_prev_mcp_done(bp);
10472
10473 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10474
10475 /* Reset should be performed after BRB is emptied */
10476 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10477 u32 timer_count = 1000;
de682941 10478 bool need_write = true;
452427b0
YM		 10479
10480 /* Close the MAC Rx to prevent BRB from filling up */
1ef1d45a
BW		 10481 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10482
10483 /* close LLH filters towards the BRB */
10484 bnx2x_set_rx_filter(&bp->link_params, 0);
452427b0 10485
b17b0ca1
YM		 10486 /* Check if the UNDI driver was previously loaded */
10487 if (bnx2x_prev_is_after_undi(bp)) {
10488 prev_undi = true;
10489 /* clear the UNDI indication */
10490 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10491 /* clear possible idle check errors */
10492 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
452427b0 10493 }
d46f7c4d
DK		 10494 if (!CHIP_IS_E1x(bp))
10495 /* block FW from writing to host */
10496 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10497
452427b0
YM		 10498 /* wait until BRB is empty */
10499 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10500 while (timer_count) {
10501 u32 prev_brb = tmp_reg;
34f80b04 10502
452427b0
YM		 10503 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10504 if (!tmp_reg)
10505 break;
619c5cb6 10506
452427b0 10507 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
619c5cb6 10508
452427b0
YM		 10509 /* reset timer as long as BRB actually gets emptied */
10510 if (prev_brb > tmp_reg)
10511 timer_count = 1000;
10512 else
10513 timer_count--;
da5a662a 10514
91ebb929
YM		 10515 /* New UNDI FW supports MF and contains better
10516 * cleaning methods - might be redundant but harmless.
10517 */
10518 if (bnx2x_prev_unload_undi_fw_supports_mf(bp)) {
de682941
YM		 10519 if (need_write) {
10520 bnx2x_prev_unload_undi_mf(bp);
10521 need_write = false;
10522 }
91ebb929
YM		 10523 } else if (prev_undi) {
10524 /* If UNDI resides in memory,
10525 * manually increment it
10526 */
452427b0 10527 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
91ebb929 10528 }
452427b0 10529 udelay(10);
7a06a122 10530 }
452427b0
YM		 10531
10532 if (!timer_count)
10533 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
34f80b04 10534 }
f16da43b 10535
452427b0
YM		 10536 /* No packets are in the pipeline, path is ready for reset */
10537 bnx2x_reset_common(bp);
10538
1ef1d45a
BW		 10539 if (mac_vals.xmac_addr)
10540 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10541 if (mac_vals.umac_addr)
10542 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10543 if (mac_vals.emac_addr)
10544 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10545 if (mac_vals.bmac_addr) {
10546 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10547 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10548 }
10549
c63da990 10550 rc = bnx2x_prev_mark_path(bp, prev_undi);
452427b0
YM		 10551 if (rc) {
10552 bnx2x_prev_mcp_done(bp);
10553 return rc;
10554 }
10555
10556 return bnx2x_prev_mcp_done(bp);
10557}
10558
24f06716
AE		 10559/* previous driver DMAE transaction may have occurred when pre-boot stage ended
10560 * and boot began, or when kdump kernel was loaded. Either case would invalidate
10561 * the addresses of the transaction, resulting in was-error bit set in the pci
10562 * causing all hw-to-host pcie transactions to timeout. If this happened we want
10563 * to clear the interrupt which detected this from the pglueb and the was done
10564 * bit
10565 */
0329aba1 10566static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
24f06716 10567{
4a25417c
AE		 10568 if (!CHIP_IS_E1x(bp)) {
10569 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10570 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
04c46736
YM		 10571 DP(BNX2X_MSG_SP,
10572 "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
4a25417c
AE		 10573 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10574 1 << BP_FUNC(bp));
10575 }
24f06716
AE		 10576 }
10577}
10578
0329aba1 10579static int bnx2x_prev_unload(struct bnx2x *bp)
452427b0
YM		 10580{
10581 int time_counter = 10;
10582 u32 rc, fw, hw_lock_reg, hw_lock_val;
10583 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10584
24f06716
AE		 10585 /* clear hw from errors which may have resulted from an interrupted
10586 * dmae transaction.
10587 */
10588 bnx2x_prev_interrupted_dmae(bp);
10589
10590 /* Release previously held locks */
452427b0
YM		 10591 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10592 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10593 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10594
3cdeec22 10595 hw_lock_val = REG_RD(bp, hw_lock_reg);
452427b0
YM		 10596 if (hw_lock_val) {
10597 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10598 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10599 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10600 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10601 }
10602
10603 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10604 REG_WR(bp, hw_lock_reg, 0xffffffff);
10605 } else
10606 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10607
10608 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10609 BNX2X_DEV_INFO("Release previously held alr\n");
3cdeec22 10610 bnx2x_release_alr(bp);
452427b0
YM		 10611 }
10612
452427b0 10613 do {
7fa6f340 10614 int aer = 0;
452427b0
YM		 10615 /* Lock MCP using an unload request */
10616 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10617 if (!fw) {
10618 BNX2X_ERR("MCP response failure, aborting\n");
10619 rc = -EBUSY;
10620 break;
10621 }
10622
7fa6f340
YM		 10623 rc = down_interruptible(&bnx2x_prev_sem);
10624 if (rc) {
10625 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10626 rc);
10627 } else {
10628 /* If Path is marked by EEH, ignore unload status */
10629 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10630 bnx2x_prev_path_get_entry(bp)->aer);
60cde81f 10631 up(&bnx2x_prev_sem);
7fa6f340 10632 }
7fa6f340
YM		 10633
10634 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
452427b0
YM		 10635 rc = bnx2x_prev_unload_common(bp);
10636 break;
10637 }
10638
16a5fd92 10639 /* non-common reply from MCP might require looping */
452427b0
YM		 10640 rc = bnx2x_prev_unload_uncommon(bp);
10641 if (rc != BNX2X_PREV_WAIT_NEEDED)
10642 break;
10643
10644 msleep(20);
10645 } while (--time_counter);
10646
10647 if (!time_counter || rc) {
91ebb929
YM		 10648 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10649 rc = -EPROBE_DEFER;
452427b0
YM		 10650 }
10651
c63da990 10652 /* Mark function if its port was used to boot from SAN */
178135c1 10653 if (bnx2x_port_after_undi(bp))
c63da990
BW		 10654 bp->link_params.feature_config_flags |=
10655 FEATURE_CONFIG_BOOT_FROM_SAN;
10656
452427b0
YM		 10657 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10658
10659 return rc;
34f80b04
EG		 10660}
10661
0329aba1 10662static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
34f80b04 10663{
1d187b34 10664 u32 val, val2, val3, val4, id, boot_mode;
72ce58c3 10665 u16 pmc;
34f80b04
EG		 10666
10667 /* Get the chip revision id and number. */
10668 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10669 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10670 id = ((val & 0xffff) << 16);
10671 val = REG_RD(bp, MISC_REG_CHIP_REV);
10672 id |= ((val & 0xf) << 12);
f22fdf25
YM		 10673
10674 /* Metal is read from PCI regs, but we can't access >=0x400 from
10675 * the configuration space (so we need to reg_rd)
10676 */
10677 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10678 id |= (((val >> 24) & 0xf) << 4);
5a40e08e 10679 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 10680 id |= (val & 0xf);
10681 bp->common.chip_id = id;
523224a3 10682
7e8e02df
BW		 10683 /* force 57811 according to MISC register */
10684 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10685 if (CHIP_IS_57810(bp))
10686 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10687 (bp->common.chip_id & 0x0000FFFF);
10688 else if (CHIP_IS_57810_MF(bp))
10689 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10690 (bp->common.chip_id & 0x0000FFFF);
10691 bp->common.chip_id |= 0x1;
10692 }
10693
523224a3
DK		 10694 /* Set doorbell size */
10695 bp->db_size = (1 << BNX2X_DB_SHIFT);
10696
619c5cb6 10697 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 10698 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10699 if ((val & 1) == 0)
10700 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10701 else
10702 val = (val >> 1) & 1;
10703 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10704 "2_PORT_MODE");
10705 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10706 CHIP_2_PORT_MODE;
10707
10708 if (CHIP_MODE_IS_4_PORT(bp))
10709 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10710 else
10711 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10712 } else {
10713 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10714 bp->pfid = bp->pf_num; /* 0..7 */
10715 }
10716
51c1a580
MS		 10717 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10718
f2e0899f
DK		 10719 bp->link_params.chip_id = bp->common.chip_id;
10720 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 10721
1c06328c
EG		 10722 val = (REG_RD(bp, 0x2874) & 0x55);
10723 if ((bp->common.chip_id & 0x1) ||
10724 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10725 bp->flags |= ONE_PORT_FLAG;
10726 BNX2X_DEV_INFO("single port device\n");
10727 }
10728
34f80b04 10729 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 10730 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 10731 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10732 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10733 bp->common.flash_size, bp->common.flash_size);
10734
1b6e2ceb
DK		 10735 bnx2x_init_shmem(bp);
10736
f2e0899f
DK		 10737 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10738 MISC_REG_GENERIC_CR_1 :
10739 MISC_REG_GENERIC_CR_0));
1b6e2ceb 10740
34f80b04 10741 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 10742 bp->link_params.shmem2_base = bp->common.shmem2_base;
b884d95b
YR		 10743 if (SHMEM2_RD(bp, size) >
10744 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10745 bp->link_params.lfa_base =
10746 REG_RD(bp, bp->common.shmem2_base +
10747 (u32)offsetof(struct shmem2_region,
10748 lfa_host_addr[BP_PORT(bp)]));
10749 else
10750 bp->link_params.lfa_base = 0;
2691d51d
EG		 10751 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10752 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 10753
f2e0899f 10754 if (!bp->common.shmem_base) {
34f80b04
EG		 10755 BNX2X_DEV_INFO("MCP not active\n");
10756 bp->flags |= NO_MCP_FLAG;
10757 return;
10758 }
10759
34f80b04 10760 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 10761 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 10762
10763 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10764 SHARED_HW_CFG_LED_MODE_MASK) >>
10765 SHARED_HW_CFG_LED_MODE_SHIFT);
10766
c2c8b03e
EG		 10767 bp->link_params.feature_config_flags = 0;
10768 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10769 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10770 bp->link_params.feature_config_flags |=
10771 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10772 else
10773 bp->link_params.feature_config_flags &=
10774 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10775
34f80b04
EG		 10776 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10777 bp->common.bc_ver = val;
10778 BNX2X_DEV_INFO("bc_ver %X\n", val);
10779 if (val < BNX2X_BC_VER) {
10780 /* for now only warn
10781 * later we might need to enforce this */
51c1a580
MS		 10782 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10783 BNX2X_BC_VER, val);
34f80b04 10784 }
4d295db0 10785 bp->link_params.feature_config_flags |=
a22f0788 10786 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 10787 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10788
a22f0788
YR		 10789 bp->link_params.feature_config_flags |=
10790 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10791 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
a3348722
BW		 10792 bp->link_params.feature_config_flags |=
10793 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10794 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
85242eea
YR		 10795 bp->link_params.feature_config_flags |=
10796 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10797 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
55386fe8
YR		 10798
10799 bp->link_params.feature_config_flags |=
10800 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10801 FEATURE_CONFIG_MT_SUPPORT : 0;
10802
0e898dd7
BW		 10803 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10804 BC_SUPPORTS_PFC_STATS : 0;
85242eea 10805
2e499d3c
BW		 10806 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10807 BC_SUPPORTS_FCOE_FEATURES : 0;
10808
9876879f
BW		 10809 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10810 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
a6d3a5ba
BW		 10811
10812 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10813 BC_SUPPORTS_RMMOD_CMD : 0;
10814
1d187b34
BW		 10815 boot_mode = SHMEM_RD(bp,
10816 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10817 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10818 switch (boot_mode) {
10819 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10820 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10821 break;
10822 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10823 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10824 break;
10825 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10826 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10827 break;
10828 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10829 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10830 break;
10831 }
10832
29ed74c3 10833 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
f9a3ebbe
DK		 10834 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10835
72ce58c3 10836 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 10837 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 10838
10839 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10840 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10841 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10842 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10843
cdaa7cb8
VZ		 10844 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10845 val, val2, val3, val4);
34f80b04
EG		 10846}
10847
f2e0899f
DK		 10848#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10849#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10850
0329aba1 10851static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
f2e0899f
DK		 10852{
10853 int pfid = BP_FUNC(bp);
f2e0899f
DK		 10854 int igu_sb_id;
10855 u32 val;
6383c0b3 10856 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 10857
10858 bp->igu_base_sb = 0xff;
f2e0899f 10859 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 10860 int vn = BP_VN(bp);
6383c0b3 10861 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 10862 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10863 FP_SB_MAX_E1x;
10864
10865 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10866 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10867
9b341bb1 10868 return 0;
f2e0899f
DK		 10869 }
10870
10871 /* IGU in normal mode - read CAM */
10872 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10873 igu_sb_id++) {
10874 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10875 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10876 continue;
10877 fid = IGU_FID(val);
10878 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10879 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10880 continue;
10881 if (IGU_VEC(val) == 0)
10882 /* default status block */
10883 bp->igu_dsb_id = igu_sb_id;
10884 else {
10885 if (bp->igu_base_sb == 0xff)
10886 bp->igu_base_sb = igu_sb_id;
6383c0b3 10887 igu_sb_cnt++;
f2e0899f
DK		 10888 }
10889 }
10890 }
619c5cb6 10891
6383c0b3 10892#ifdef CONFIG_PCI_MSI
185d4c8b
AE		 10893 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10894 * optional that number of CAM entries will not be equal to the value
10895 * advertised in PCI.
10896 * Driver should use the minimal value of both as the actual status
10897 * block count
619c5cb6 10898 */
185d4c8b 10899 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
6383c0b3 10900#endif
619c5cb6 10901
9b341bb1 10902 if (igu_sb_cnt == 0) {
f2e0899f 10903 BNX2X_ERR("CAM configuration error\n");
9b341bb1
BW		 10904 return -EINVAL;
10905 }
10906
10907 return 0;
f2e0899f
DK		 10908}
10909
1dd06ae8 10910static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
a2fbb9ea 10911{
a22f0788
YR		 10912 int cfg_size = 0, idx, port = BP_PORT(bp);
10913
10914 /* Aggregation of supported attributes of all external phys */
10915 bp->port.supported[0] = 0;
10916 bp->port.supported[1] = 0;
b7737c9b
YR		 10917 switch (bp->link_params.num_phys) {
10918 case 1:
a22f0788
YR		 10919 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10920 cfg_size = 1;
10921 break;
b7737c9b 10922 case 2:
a22f0788
YR		 10923 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10924 cfg_size = 1;
10925 break;
10926 case 3:
10927 if (bp->link_params.multi_phy_config &
10928 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10929 bp->port.supported[1] =
10930 bp->link_params.phy[EXT_PHY1].supported;
10931 bp->port.supported[0] =
10932 bp->link_params.phy[EXT_PHY2].supported;
10933 } else {
10934 bp->port.supported[0] =
10935 bp->link_params.phy[EXT_PHY1].supported;
10936 bp->port.supported[1] =
10937 bp->link_params.phy[EXT_PHY2].supported;
10938 }
10939 cfg_size = 2;
10940 break;
b7737c9b 10941 }
a2fbb9ea 10942
a22f0788 10943 if (!(bp->port.supported[0] || bp->port.supported[1])) {
51c1a580 10944 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 10945 SHMEM_RD(bp,
a22f0788
YR		 10946 dev_info.port_hw_config[port].external_phy_config),
10947 SHMEM_RD(bp,
10948 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 10949 return;
f85582f8 10950 }
a2fbb9ea 10951
619c5cb6
VZ		 10952 if (CHIP_IS_E3(bp))
10953 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10954 else {
10955 switch (switch_cfg) {
10956 case SWITCH_CFG_1G:
10957 bp->port.phy_addr = REG_RD(
10958 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10959 break;
10960 case SWITCH_CFG_10G:
10961 bp->port.phy_addr = REG_RD(
10962 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10963 break;
10964 default:
10965 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10966 bp->port.link_config[0]);
10967 return;
10968 }
a2fbb9ea 10969 }
619c5cb6 10970 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 10971 /* mask what we support according to speed_cap_mask per configuration */
10972 for (idx = 0; idx < cfg_size; idx++) {
10973 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10974 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 10975 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 10976
a22f0788 10977 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10978 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 10979 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 10980
a22f0788 10981 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10982 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 10983 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 10984
a22f0788 10985 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10986 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 10987 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 10988
a22f0788 10989 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10990 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 10991 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 10992 SUPPORTED_1000baseT_Full);
a2fbb9ea 10993
a22f0788 10994 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10995 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 10996 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 10997
a22f0788 10998 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10999 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788 11000 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
b8e0d884
YR		 11001
11002 if (!(bp->link_params.speed_cap_mask[idx] &
11003 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11004 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
a22f0788 11005 }
a2fbb9ea 11006
a22f0788
YR		 11007 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11008 bp->port.supported[1]);
a2fbb9ea
ET		 11009}
11010
0329aba1 11011static void bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 11012{
a22f0788
YR		 11013 u32 link_config, idx, cfg_size = 0;
11014 bp->port.advertising[0] = 0;
11015 bp->port.advertising[1] = 0;
11016 switch (bp->link_params.num_phys) {
11017 case 1:
11018 case 2:
11019 cfg_size = 1;
11020 break;
11021 case 3:
11022 cfg_size = 2;
11023 break;
11024 }
11025 for (idx = 0; idx < cfg_size; idx++) {
11026 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11027 link_config = bp->port.link_config[idx];
11028 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 11029 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 11030 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11031 bp->link_params.req_line_speed[idx] =
11032 SPEED_AUTO_NEG;
11033 bp->port.advertising[idx] |=
11034 bp->port.supported[idx];
10bd1f24
MY		 11035 if (bp->link_params.phy[EXT_PHY1].type ==
11036 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11037 bp->port.advertising[idx] |=
11038 (SUPPORTED_100baseT_Half |
11039 SUPPORTED_100baseT_Full);
f85582f8
DK		 11040 } else {
11041 /* force 10G, no AN */
a22f0788
YR		 11042 bp->link_params.req_line_speed[idx] =
11043 SPEED_10000;
11044 bp->port.advertising[idx] |=
11045 (ADVERTISED_10000baseT_Full |
f85582f8 11046 ADVERTISED_FIBRE);
a22f0788 11047 continue;
f85582f8
DK		 11048 }
11049 break;
a2fbb9ea 11050
f85582f8 11051 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 11052 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11053 bp->link_params.req_line_speed[idx] =
11054 SPEED_10;
11055 bp->port.advertising[idx] |=
11056 (ADVERTISED_10baseT_Full |
f85582f8
DK		 11057 ADVERTISED_TP);
11058 } else {
51c1a580 11059 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8 11060 link_config,
a22f0788 11061 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11062 return;
11063 }
11064 break;
a2fbb9ea 11065
f85582f8 11066 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 11067 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11068 bp->link_params.req_line_speed[idx] =
11069 SPEED_10;
11070 bp->link_params.req_duplex[idx] =
11071 DUPLEX_HALF;
11072 bp->port.advertising[idx] |=
11073 (ADVERTISED_10baseT_Half |
f85582f8
DK		 11074 ADVERTISED_TP);
11075 } else {
51c1a580 11076 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 11077 link_config,
11078 bp->link_params.speed_cap_mask[idx]);
11079 return;
11080 }
11081 break;
a2fbb9ea 11082
f85582f8
DK		 11083 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11084 if (bp->port.supported[idx] &
11085 SUPPORTED_100baseT_Full) {
a22f0788
YR		 11086 bp->link_params.req_line_speed[idx] =
11087 SPEED_100;
11088 bp->port.advertising[idx] |=
11089 (ADVERTISED_100baseT_Full |
f85582f8
DK		 11090 ADVERTISED_TP);
11091 } else {
51c1a580 11092 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 11093 link_config,
11094 bp->link_params.speed_cap_mask[idx]);
11095 return;
11096 }
11097 break;
a2fbb9ea 11098
f85582f8
DK		 11099 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11100 if (bp->port.supported[idx] &
11101 SUPPORTED_100baseT_Half) {
11102 bp->link_params.req_line_speed[idx] =
11103 SPEED_100;
11104 bp->link_params.req_duplex[idx] =
11105 DUPLEX_HALF;
a22f0788
YR		 11106 bp->port.advertising[idx] |=
11107 (ADVERTISED_100baseT_Half |
f85582f8
DK		 11108 ADVERTISED_TP);
11109 } else {
51c1a580 11110 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11111 link_config,
11112 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11113 return;
11114 }
11115 break;
a2fbb9ea 11116
f85582f8 11117 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 11118 if (bp->port.supported[idx] &
11119 SUPPORTED_1000baseT_Full) {
11120 bp->link_params.req_line_speed[idx] =
11121 SPEED_1000;
11122 bp->port.advertising[idx] |=
11123 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 11124 ADVERTISED_TP);
11125 } else {
51c1a580 11126 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11127 link_config,
11128 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11129 return;
11130 }
11131 break;
a2fbb9ea 11132
f85582f8 11133 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 11134 if (bp->port.supported[idx] &
11135 SUPPORTED_2500baseX_Full) {
11136 bp->link_params.req_line_speed[idx] =
11137 SPEED_2500;
11138 bp->port.advertising[idx] |=
11139 (ADVERTISED_2500baseX_Full |
34f80b04 11140 ADVERTISED_TP);
f85582f8 11141 } else {
51c1a580 11142 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11143 link_config,
f85582f8
DK		 11144 bp->link_params.speed_cap_mask[idx]);
11145 return;
11146 }
11147 break;
a2fbb9ea 11148
f85582f8 11149 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 11150 if (bp->port.supported[idx] &
11151 SUPPORTED_10000baseT_Full) {
11152 bp->link_params.req_line_speed[idx] =
11153 SPEED_10000;
11154 bp->port.advertising[idx] |=
11155 (ADVERTISED_10000baseT_Full |
34f80b04 11156 ADVERTISED_FIBRE);
f85582f8 11157 } else {
51c1a580 11158 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11159 link_config,
f85582f8
DK		 11160 bp->link_params.speed_cap_mask[idx]);
11161 return;
11162 }
11163 break;
3c9ada22
YR		 11164 case PORT_FEATURE_LINK_SPEED_20G:
11165 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 11166
3c9ada22 11167 break;
f85582f8 11168 default:
51c1a580 11169 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
754a2f52 11170 link_config);
f85582f8
DK		 11171 bp->link_params.req_line_speed[idx] =
11172 SPEED_AUTO_NEG;
11173 bp->port.advertising[idx] =
11174 bp->port.supported[idx];
11175 break;
11176 }
a2fbb9ea 11177
a22f0788 11178 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 11179 PORT_FEATURE_FLOW_CONTROL_MASK);
cd1dfce2
YM		 11180 if (bp->link_params.req_flow_ctrl[idx] ==
11181 BNX2X_FLOW_CTRL_AUTO) {
11182 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11183 bp->link_params.req_flow_ctrl[idx] =
11184 BNX2X_FLOW_CTRL_NONE;
11185 else
11186 bnx2x_set_requested_fc(bp);
a22f0788 11187 }
a2fbb9ea 11188
51c1a580 11189 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
a22f0788
YR		 11190 bp->link_params.req_line_speed[idx],
11191 bp->link_params.req_duplex[idx],
11192 bp->link_params.req_flow_ctrl[idx],
11193 bp->port.advertising[idx]);
11194 }
a2fbb9ea
ET		 11195}
11196
0329aba1 11197static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
e665bfda 11198{
86564c3f
YM		 11199 __be16 mac_hi_be = cpu_to_be16(mac_hi);
11200 __be32 mac_lo_be = cpu_to_be32(mac_lo);
11201 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11202 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
e665bfda
MC		 11203}
11204
0329aba1 11205static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 11206{
34f80b04 11207 int port = BP_PORT(bp);
589abe3a 11208 u32 config;
c8c60d88 11209 u32 ext_phy_type, ext_phy_config, eee_mode;
a2fbb9ea 11210
c18487ee 11211 bp->link_params.bp = bp;
34f80b04 11212 bp->link_params.port = port;
c18487ee 11213
c18487ee 11214 bp->link_params.lane_config =
a2fbb9ea 11215 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 11216
a22f0788 11217 bp->link_params.speed_cap_mask[0] =
a2fbb9ea 11218 SHMEM_RD(bp,
b0261926
YR		 11219 dev_info.port_hw_config[port].speed_capability_mask) &
11220 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788
YR		 11221 bp->link_params.speed_cap_mask[1] =
11222 SHMEM_RD(bp,
b0261926
YR		 11223 dev_info.port_hw_config[port].speed_capability_mask2) &
11224 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788 11225 bp->port.link_config[0] =
a2fbb9ea
ET		 11226 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11227
a22f0788
YR		 11228 bp->port.link_config[1] =
11229 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 11230
a22f0788
YR		 11231 bp->link_params.multi_phy_config =
11232 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 11233 /* If the device is capable of WoL, set the default state according
11234 * to the HW
11235 */
4d295db0 11236 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 11237 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11238 (config & PORT_FEATURE_WOL_ENABLED));
11239
4ba7699b
YM		 11240 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11241 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11242 bp->flags |= NO_ISCSI_FLAG;
11243 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11244 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11245 bp->flags |= NO_FCOE_FLAG;
11246
51c1a580 11247 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 11248 bp->link_params.lane_config,
a22f0788
YR		 11249 bp->link_params.speed_cap_mask[0],
11250 bp->port.link_config[0]);
a2fbb9ea 11251
a22f0788 11252 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 11253 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 11254 bnx2x_phy_probe(&bp->link_params);
c18487ee 11255 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 11256
11257 bnx2x_link_settings_requested(bp);
11258
01cd4528
EG		 11259 /*
11260 * If connected directly, work with the internal PHY, otherwise, work
11261 * with the external PHY
11262 */
b7737c9b
YR		 11263 ext_phy_config =
11264 SHMEM_RD(bp,
11265 dev_info.port_hw_config[port].external_phy_config);
11266 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 11267 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 11268 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 11269
11270 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11271 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11272 bp->mdio.prtad =
b7737c9b 11273 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d 11274
c8c60d88
YM		 11275 /* Configure link feature according to nvram value */
11276 eee_mode = (((SHMEM_RD(bp, dev_info.
11277 port_feature_config[port].eee_power_mode)) &
11278 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11279 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11280 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11281 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11282 EEE_MODE_ENABLE_LPI |
11283 EEE_MODE_OUTPUT_TIME;
11284 } else {
11285 bp->link_params.eee_mode = 0;
11286 }
0793f83f 11287}
01cd4528 11288
b306f5ed 11289void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 11290{
9e62e912 11291 u32 no_flags = NO_ISCSI_FLAG;
bf61ee14 11292 int port = BP_PORT(bp);
2ba45142 11293 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 11294 drv_lic_key[port].max_iscsi_conn);
2ba45142 11295
55c11941
MS		 11296 if (!CNIC_SUPPORT(bp)) {
11297 bp->flags |= no_flags;
11298 return;
11299 }
11300
b306f5ed 11301 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 11302 bp->cnic_eth_dev.max_iscsi_conn =
11303 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11304 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11305
b306f5ed
DK		 11306 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11307 bp->cnic_eth_dev.max_iscsi_conn);
11308
11309 /*
11310 * If maximum allowed number of connections is zero -
11311 * disable the feature.
11312 */
11313 if (!bp->cnic_eth_dev.max_iscsi_conn)
9e62e912 11314 bp->flags |= no_flags;
b306f5ed
DK		 11315}
11316
0329aba1 11317static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
9e62e912
DK		 11318{
11319 /* Port info */
11320 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11321 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11322 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11323 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11324
11325 /* Node info */
11326 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11327 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11328 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11329 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11330}
86800194
DK		 11331
11332static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11333{
11334 u8 count = 0;
11335
11336 if (IS_MF(bp)) {
11337 u8 fid;
11338
11339 /* iterate over absolute function ids for this path: */
11340 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11341 if (IS_MF_SD(bp)) {
11342 u32 cfg = MF_CFG_RD(bp,
11343 func_mf_config[fid].config);
11344
11345 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11346 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11347 FUNC_MF_CFG_PROTOCOL_FCOE))
11348 count++;
11349 } else {
11350 u32 cfg = MF_CFG_RD(bp,
11351 func_ext_config[fid].
11352 func_cfg);
11353
11354 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11355 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11356 count++;
11357 }
11358 }
11359 } else { /* SF */
11360 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11361
11362 for (port = 0; port < port_cnt; port++) {
11363 u32 lic = SHMEM_RD(bp,
11364 drv_lic_key[port].max_fcoe_conn) ^
11365 FW_ENCODE_32BIT_PATTERN;
11366 if (lic)
11367 count++;
11368 }
11369 }
11370
11371 return count;
11372}
11373
0329aba1 11374static void bnx2x_get_fcoe_info(struct bnx2x *bp)
b306f5ed
DK		 11375{
11376 int port = BP_PORT(bp);
11377 int func = BP_ABS_FUNC(bp);
b306f5ed
DK		 11378 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11379 drv_lic_key[port].max_fcoe_conn);
86800194 11380 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
b306f5ed 11381
55c11941
MS		 11382 if (!CNIC_SUPPORT(bp)) {
11383 bp->flags |= NO_FCOE_FLAG;
11384 return;
11385 }
11386
b306f5ed 11387 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 11388 bp->cnic_eth_dev.max_fcoe_conn =
11389 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11390 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11391
0eb43b4b
BPG		 11392 /* Calculate the number of maximum allowed FCoE tasks */
11393 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
86800194
DK		 11394
11395 /* check if FCoE resources must be shared between different functions */
11396 if (num_fcoe_func)
11397 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
0eb43b4b 11398
bf61ee14
VZ		 11399 /* Read the WWN: */
11400 if (!IS_MF(bp)) {
11401 /* Port info */
11402 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11403 SHMEM_RD(bp,
2de67439 11404 dev_info.port_hw_config[port].
bf61ee14
VZ		 11405 fcoe_wwn_port_name_upper);
11406 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11407 SHMEM_RD(bp,
2de67439 11408 dev_info.port_hw_config[port].
bf61ee14
VZ		 11409 fcoe_wwn_port_name_lower);
11410
11411 /* Node info */
11412 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11413 SHMEM_RD(bp,
2de67439 11414 dev_info.port_hw_config[port].
bf61ee14
VZ		 11415 fcoe_wwn_node_name_upper);
11416 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11417 SHMEM_RD(bp,
2de67439 11418 dev_info.port_hw_config[port].
bf61ee14
VZ		 11419 fcoe_wwn_node_name_lower);
11420 } else if (!IS_MF_SD(bp)) {
bf61ee14
VZ		 11421 /*
11422 * Read the WWN info only if the FCoE feature is enabled for
11423 * this function.
11424 */
7b5342d9 11425 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
9e62e912
DK		 11426 bnx2x_get_ext_wwn_info(bp, func);
11427
382e513a 11428 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
9e62e912 11429 bnx2x_get_ext_wwn_info(bp, func);
382e513a 11430 }
bf61ee14 11431
b306f5ed 11432 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 11433
bf61ee14
VZ		 11434 /*
11435 * If maximum allowed number of connections is zero -
2ba45142
VZ		 11436 * disable the feature.
11437 */
2ba45142
VZ		 11438 if (!bp->cnic_eth_dev.max_fcoe_conn)
11439 bp->flags |= NO_FCOE_FLAG;
11440}
b306f5ed 11441
0329aba1 11442static void bnx2x_get_cnic_info(struct bnx2x *bp)
b306f5ed
DK		 11443{
11444 /*
11445 * iSCSI may be dynamically disabled but reading
11446 * info here we will decrease memory usage by driver
11447 * if the feature is disabled for good
11448 */
11449 bnx2x_get_iscsi_info(bp);
11450 bnx2x_get_fcoe_info(bp);
11451}
2ba45142 11452
0329aba1 11453static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
0793f83f
DK		 11454{
11455 u32 val, val2;
11456 int func = BP_ABS_FUNC(bp);
11457 int port = BP_PORT(bp);
2ba45142
VZ		 11458 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11459 u8 *fip_mac = bp->fip_mac;
0793f83f 11460
55c11941
MS		 11461 if (IS_MF(bp)) {
11462 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142 11463 * FCoE MAC then the appropriate feature should be disabled.
55c11941
MS		 11464 * In non SD mode features configuration comes from struct
11465 * func_ext_config.
2ba45142 11466 */
55c11941 11467 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
0793f83f
DK		 11468 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11469 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11470 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11471 iscsi_mac_addr_upper);
0793f83f 11472 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11473 iscsi_mac_addr_lower);
2ba45142 11474 bnx2x_set_mac_buf(iscsi_mac, val, val2);
55c11941
MS		 11475 BNX2X_DEV_INFO
11476 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11477 } else {
2ba45142 11478 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
55c11941 11479 }
2ba45142
VZ		 11480
11481 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11482 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11483 fcoe_mac_addr_upper);
2ba45142 11484 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11485 fcoe_mac_addr_lower);
2ba45142 11486 bnx2x_set_mac_buf(fip_mac, val, val2);
55c11941
MS		 11487 BNX2X_DEV_INFO
11488 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11489 } else {
2ba45142 11490 bp->flags |= NO_FCOE_FLAG;
55c11941 11491 }
a3348722
BW		 11492
11493 bp->mf_ext_config = cfg;
11494
9e62e912 11495 } else { /* SD MODE */
55c11941
MS		 11496 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11497 /* use primary mac as iscsi mac */
11498 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11499
11500 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11501 BNX2X_DEV_INFO
11502 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11503 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11504 /* use primary mac as fip mac */
11505 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11506 BNX2X_DEV_INFO("SD FCoE MODE\n");
11507 BNX2X_DEV_INFO
11508 ("Read FIP MAC: %pM\n", fip_mac);
614c76df 11509 }
0793f83f 11510 }
a3348722 11511
82594f8f
YM		 11512 /* If this is a storage-only interface, use SAN mac as
11513 * primary MAC. Notice that for SD this is already the case,
11514 * as the SAN mac was copied from the primary MAC.
11515 */
11516 if (IS_MF_FCOE_AFEX(bp))
a3348722 11517 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
0793f83f 11518 } else {
0793f83f 11519 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11520 iscsi_mac_upper);
0793f83f 11521 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11522 iscsi_mac_lower);
2ba45142 11523 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 11524
11525 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11526 fcoe_fip_mac_upper);
c03bd39c 11527 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11528 fcoe_fip_mac_lower);
c03bd39c 11529 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 11530 }
11531
55c11941 11532 /* Disable iSCSI OOO if MAC configuration is invalid. */
426b9241 11533 if (!is_valid_ether_addr(iscsi_mac)) {
55c11941 11534 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
426b9241
DK		 11535 memset(iscsi_mac, 0, ETH_ALEN);
11536 }
11537
55c11941 11538 /* Disable FCoE if MAC configuration is invalid. */
426b9241
DK		 11539 if (!is_valid_ether_addr(fip_mac)) {
11540 bp->flags |= NO_FCOE_FLAG;
11541 memset(bp->fip_mac, 0, ETH_ALEN);
11542 }
55c11941
MS		 11543}
11544
0329aba1 11545static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
55c11941
MS		 11546{
11547 u32 val, val2;
11548 int func = BP_ABS_FUNC(bp);
11549 int port = BP_PORT(bp);
11550
11551 /* Zero primary MAC configuration */
11552 memset(bp->dev->dev_addr, 0, ETH_ALEN);
11553
11554 if (BP_NOMCP(bp)) {
11555 BNX2X_ERROR("warning: random MAC workaround active\n");
11556 eth_hw_addr_random(bp->dev);
11557 } else if (IS_MF(bp)) {
11558 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11559 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11560 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11561 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11562 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11563
11564 if (CNIC_SUPPORT(bp))
11565 bnx2x_get_cnic_mac_hwinfo(bp);
11566 } else {
11567 /* in SF read MACs from port configuration */
11568 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11569 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11570 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11571
11572 if (CNIC_SUPPORT(bp))
11573 bnx2x_get_cnic_mac_hwinfo(bp);
11574 }
11575
3d7d562c
YM		 11576 if (!BP_NOMCP(bp)) {
11577 /* Read physical port identifier from shmem */
11578 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11579 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11580 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11581 bp->flags |= HAS_PHYS_PORT_ID;
11582 }
11583
55c11941 11584 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
619c5cb6 11585
614c76df 11586 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
619c5cb6 11587 dev_err(&bp->pdev->dev,
51c1a580
MS		 11588 "bad Ethernet MAC address configuration: %pM\n"
11589 "change it manually before bringing up the appropriate network interface\n",
0f9dad10 11590 bp->dev->dev_addr);
7964211d 11591}
51c1a580 11592
0329aba1 11593static bool bnx2x_get_dropless_info(struct bnx2x *bp)
7964211d
YM		 11594{
11595 int tmp;
11596 u32 cfg;
51c1a580 11597
aeeddb8b
YM		 11598 if (IS_VF(bp))
11599 return 0;
11600
7964211d
YM		 11601 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11602 /* Take function: tmp = func */
11603 tmp = BP_ABS_FUNC(bp);
11604 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11605 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11606 } else {
11607 /* Take port: tmp = port */
11608 tmp = BP_PORT(bp);
11609 cfg = SHMEM_RD(bp,
11610 dev_info.port_hw_config[tmp].generic_features);
11611 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11612 }
11613 return cfg;
34f80b04
EG		 11614}
11615
0329aba1 11616static int bnx2x_get_hwinfo(struct bnx2x *bp)
34f80b04 11617{
0793f83f 11618 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 11619 int vn;
0793f83f 11620 u32 val = 0;
34f80b04 11621 int rc = 0;
a2fbb9ea 11622
34f80b04 11623 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 11624
6383c0b3
AE		 11625 /*
11626 * initialize IGU parameters
11627 */
f2e0899f
DK		 11628 if (CHIP_IS_E1x(bp)) {
11629 bp->common.int_block = INT_BLOCK_HC;
11630
11631 bp->igu_dsb_id = DEF_SB_IGU_ID;
11632 bp->igu_base_sb = 0;
f2e0899f
DK		 11633 } else {
11634 bp->common.int_block = INT_BLOCK_IGU;
7a06a122 11635
16a5fd92 11636 /* do not allow device reset during IGU info processing */
7a06a122
DK		 11637 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11638
f2e0899f 11639 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 11640
11641 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11642 int tout = 5000;
11643
11644 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11645
11646 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11647 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11648 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11649
11650 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11651 tout--;
0926d499 11652 usleep_range(1000, 2000);
619c5cb6
VZ		 11653 }
11654
11655 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11656 dev_err(&bp->pdev->dev,
11657 "FORCING Normal Mode failed!!!\n");
9b341bb1
BW		 11658 bnx2x_release_hw_lock(bp,
11659 HW_LOCK_RESOURCE_RESET);
619c5cb6
VZ		 11660 return -EPERM;
11661 }
11662 }
11663
f2e0899f 11664 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 11665 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 11666 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11667 } else
619c5cb6 11668 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 11669
9b341bb1 11670 rc = bnx2x_get_igu_cam_info(bp);
7a06a122 11671 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9b341bb1
BW		 11672 if (rc)
11673 return rc;
f2e0899f 11674 }
619c5cb6
VZ		 11675
11676 /*
11677 * set base FW non-default (fast path) status block id, this value is
11678 * used to initialize the fw_sb_id saved on the fp/queue structure to
11679 * determine the id used by the FW.
11680 */
11681 if (CHIP_IS_E1x(bp))
11682 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11683 else /*
11684 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11685 * the same queue are indicated on the same IGU SB). So we prefer
11686 * FW and IGU SBs to be the same value.
11687 */
11688 bp->base_fw_ndsb = bp->igu_base_sb;
11689
11690 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11691 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11692 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 11693
11694 /*
11695 * Initialize MF configuration
11696 */
523224a3 11697
fb3bff17
DK		 11698 bp->mf_ov = 0;
11699 bp->mf_mode = 0;
3395a033 11700 vn = BP_VN(bp);
0793f83f 11701
f2e0899f 11702 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 11703 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11704 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11705 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11706
f2e0899f
DK		 11707 if (SHMEM2_HAS(bp, mf_cfg_addr))
11708 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11709 else
11710 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 11711 offsetof(struct shmem_region, func_mb) +
11712 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 11713 /*
11714 * get mf configuration:
16a5fd92 11715 * 1. Existence of MF configuration
0793f83f
DK		 11716 * 2. MAC address must be legal (check only upper bytes)
11717 * for Switch-Independent mode;
11718 * OVLAN must be legal for Switch-Dependent mode
11719 * 3. SF_MODE configures specific MF mode
11720 */
11721 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11722 /* get mf configuration */
11723 val = SHMEM_RD(bp,
11724 dev_info.shared_feature_config.config);
11725 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11726
11727 switch (val) {
11728 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11729 val = MF_CFG_RD(bp, func_mf_config[func].
11730 mac_upper);
11731 /* check for legal mac (upper bytes)*/
11732 if (val != 0xffff) {
11733 bp->mf_mode = MULTI_FUNCTION_SI;
11734 bp->mf_config[vn] = MF_CFG_RD(bp,
11735 func_mf_config[func].config);
11736 } else
51c1a580 11737 BNX2X_DEV_INFO("illegal MAC address for SI\n");
0793f83f 11738 break;
a3348722
BW		 11739 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11740 if ((!CHIP_IS_E1x(bp)) &&
11741 (MF_CFG_RD(bp, func_mf_config[func].
11742 mac_upper) != 0xffff) &&
11743 (SHMEM2_HAS(bp,
11744 afex_driver_support))) {
11745 bp->mf_mode = MULTI_FUNCTION_AFEX;
11746 bp->mf_config[vn] = MF_CFG_RD(bp,
11747 func_mf_config[func].config);
11748 } else {
11749 BNX2X_DEV_INFO("can not configure afex mode\n");
11750 }
11751 break;
0793f83f
DK		 11752 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11753 /* get OV configuration */
11754 val = MF_CFG_RD(bp,
11755 func_mf_config[FUNC_0].e1hov_tag);
11756 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11757
11758 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11759 bp->mf_mode = MULTI_FUNCTION_SD;
11760 bp->mf_config[vn] = MF_CFG_RD(bp,
11761 func_mf_config[func].config);
11762 } else
754a2f52 11763 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f 11764 break;
3786b942
AE		 11765 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11766 bp->mf_config[vn] = 0;
11767 break;
0793f83f
DK		 11768 default:
11769 /* Unknown configuration: reset mf_config */
11770 bp->mf_config[vn] = 0;
51c1a580 11771 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
0793f83f
DK		 11772 }
11773 }
a2fbb9ea 11774
2691d51d 11775 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 11776 IS_MF(bp) ? "multi" : "single");
2691d51d 11777
0793f83f
DK		 11778 switch (bp->mf_mode) {
11779 case MULTI_FUNCTION_SD:
11780 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11781 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 11782 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 11783 bp->mf_ov = val;
619c5cb6
VZ		 11784 bp->path_has_ovlan = true;
11785
51c1a580
MS		 11786 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11787 func, bp->mf_ov, bp->mf_ov);
2691d51d 11788 } else {
619c5cb6 11789 dev_err(&bp->pdev->dev,
51c1a580
MS		 11790 "No valid MF OV for func %d, aborting\n",
11791 func);
619c5cb6 11792 return -EPERM;
34f80b04 11793 }
0793f83f 11794 break;
a3348722
BW		 11795 case MULTI_FUNCTION_AFEX:
11796 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11797 break;
0793f83f 11798 case MULTI_FUNCTION_SI:
51c1a580
MS		 11799 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11800 func);
0793f83f
DK		 11801 break;
11802 default:
11803 if (vn) {
619c5cb6 11804 dev_err(&bp->pdev->dev,
51c1a580
MS		 11805 "VN %d is in a single function mode, aborting\n",
11806 vn);
619c5cb6 11807 return -EPERM;
2691d51d 11808 }
0793f83f 11809 break;
34f80b04 11810 }
0793f83f 11811
619c5cb6
VZ		 11812 /* check if other port on the path needs ovlan:
11813 * Since MF configuration is shared between ports
11814 * Possible mixed modes are only
11815 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11816 */
11817 if (CHIP_MODE_IS_4_PORT(bp) &&
11818 !bp->path_has_ovlan &&
11819 !IS_MF(bp) &&
11820 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11821 u8 other_port = !BP_PORT(bp);
11822 u8 other_func = BP_PATH(bp) + 2*other_port;
11823 val = MF_CFG_RD(bp,
11824 func_mf_config[other_func].e1hov_tag);
11825 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11826 bp->path_has_ovlan = true;
11827 }
34f80b04 11828 }
a2fbb9ea 11829
e848582c
DK		 11830 /* adjust igu_sb_cnt to MF for E1H */
11831 if (CHIP_IS_E1H(bp) && IS_MF(bp))
11832 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
523224a3 11833
619c5cb6
VZ		 11834 /* port info */
11835 bnx2x_get_port_hwinfo(bp);
f2e0899f 11836
0793f83f
DK		 11837 /* Get MAC addresses */
11838 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 11839
2ba45142 11840 bnx2x_get_cnic_info(bp);
2ba45142 11841
34f80b04
EG		 11842 return rc;
11843}
11844
0329aba1 11845static void bnx2x_read_fwinfo(struct bnx2x *bp)
34f24c7f
VZ		 11846{
11847 int cnt, i, block_end, rodi;
fcdf95cb 11848 char vpd_start[BNX2X_VPD_LEN+1];
34f24c7f
VZ		 11849 char str_id_reg[VENDOR_ID_LEN+1];
11850 char str_id_cap[VENDOR_ID_LEN+1];
fcdf95cb
BW		 11851 char *vpd_data;
11852 char *vpd_extended_data = NULL;
34f24c7f
VZ		 11853 u8 len;
11854
fcdf95cb 11855 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
34f24c7f
VZ		 11856 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11857
11858 if (cnt < BNX2X_VPD_LEN)
11859 goto out_not_found;
11860
fcdf95cb
BW		 11861 /* VPD RO tag should be first tag after identifier string, hence
11862 * we should be able to find it in first BNX2X_VPD_LEN chars
11863 */
11864 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
34f24c7f
VZ		 11865 PCI_VPD_LRDT_RO_DATA);
11866 if (i < 0)
11867 goto out_not_found;
11868
34f24c7f 11869 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
fcdf95cb 11870 pci_vpd_lrdt_size(&vpd_start[i]);
34f24c7f
VZ		 11871
11872 i += PCI_VPD_LRDT_TAG_SIZE;
11873
fcdf95cb
BW		 11874 if (block_end > BNX2X_VPD_LEN) {
11875 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11876 if (vpd_extended_data == NULL)
11877 goto out_not_found;
11878
11879 /* read rest of vpd image into vpd_extended_data */
11880 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11881 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11882 block_end - BNX2X_VPD_LEN,
11883 vpd_extended_data + BNX2X_VPD_LEN);
11884 if (cnt < (block_end - BNX2X_VPD_LEN))
11885 goto out_not_found;
11886 vpd_data = vpd_extended_data;
11887 } else
11888 vpd_data = vpd_start;
11889
11890 /* now vpd_data holds full vpd content in both cases */
34f24c7f
VZ		 11891
11892 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11893 PCI_VPD_RO_KEYWORD_MFR_ID);
11894 if (rodi < 0)
11895 goto out_not_found;
11896
11897 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11898
11899 if (len != VENDOR_ID_LEN)
11900 goto out_not_found;
11901
11902 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11903
11904 /* vendor specific info */
11905 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11906 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11907 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11908 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11909
11910 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11911 PCI_VPD_RO_KEYWORD_VENDOR0);
11912 if (rodi >= 0) {
11913 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11914
11915 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11916
11917 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11918 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11919 bp->fw_ver[len] = ' ';
11920 }
11921 }
fcdf95cb 11922 kfree(vpd_extended_data);
34f24c7f
VZ		 11923 return;
11924 }
11925out_not_found:
fcdf95cb 11926 kfree(vpd_extended_data);
34f24c7f
VZ		 11927 return;
11928}
11929
0329aba1 11930static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
619c5cb6
VZ		 11931{
11932 u32 flags = 0;
11933
11934 if (CHIP_REV_IS_FPGA(bp))
11935 SET_FLAGS(flags, MODE_FPGA);
11936 else if (CHIP_REV_IS_EMUL(bp))
11937 SET_FLAGS(flags, MODE_EMUL);
11938 else
11939 SET_FLAGS(flags, MODE_ASIC);
11940
11941 if (CHIP_MODE_IS_4_PORT(bp))
11942 SET_FLAGS(flags, MODE_PORT4);
11943 else
11944 SET_FLAGS(flags, MODE_PORT2);
11945
11946 if (CHIP_IS_E2(bp))
11947 SET_FLAGS(flags, MODE_E2);
11948 else if (CHIP_IS_E3(bp)) {
11949 SET_FLAGS(flags, MODE_E3);
11950 if (CHIP_REV(bp) == CHIP_REV_Ax)
11951 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 11952 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11953 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 11954 }
11955
11956 if (IS_MF(bp)) {
11957 SET_FLAGS(flags, MODE_MF);
11958 switch (bp->mf_mode) {
11959 case MULTI_FUNCTION_SD:
11960 SET_FLAGS(flags, MODE_MF_SD);
11961 break;
11962 case MULTI_FUNCTION_SI:
11963 SET_FLAGS(flags, MODE_MF_SI);
11964 break;
a3348722
BW		 11965 case MULTI_FUNCTION_AFEX:
11966 SET_FLAGS(flags, MODE_MF_AFEX);
11967 break;
619c5cb6
VZ		 11968 }
11969 } else
11970 SET_FLAGS(flags, MODE_SF);
11971
11972#if defined(__LITTLE_ENDIAN)
11973 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11974#else /*(__BIG_ENDIAN)*/
11975 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11976#endif
11977 INIT_MODE_FLAGS(bp) = flags;
11978}
11979
0329aba1 11980static int bnx2x_init_bp(struct bnx2x *bp)
34f80b04 11981{
f2e0899f 11982 int func;
34f80b04
EG		 11983 int rc;
11984
34f80b04 11985 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 11986 mutex_init(&bp->fw_mb_mutex);
42f8277f
YM		 11987 mutex_init(&bp->drv_info_mutex);
11988 bp->drv_info_mng_owner = false;
bb7e95c8 11989 spin_lock_init(&bp->stats_lock);
507393eb 11990 sema_init(&bp->stats_sema, 1);
55c11941 11991
1cf167f2 11992 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 11993 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 11994 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
370d4a26 11995 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
1ab4434c
AE		 11996 if (IS_PF(bp)) {
11997 rc = bnx2x_get_hwinfo(bp);
11998 if (rc)
11999 return rc;
12000 } else {
e09b74d0 12001 eth_zero_addr(bp->dev->dev_addr);
1ab4434c 12002 }
34f80b04 12003
619c5cb6
VZ		 12004 bnx2x_set_modes_bitmap(bp);
12005
12006 rc = bnx2x_alloc_mem_bp(bp);
12007 if (rc)
12008 return rc;
523224a3 12009
34f24c7f 12010 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 12011
12012 func = BP_FUNC(bp);
12013
34f80b04 12014 /* need to reset chip if undi was active */
1ab4434c 12015 if (IS_PF(bp) && !BP_NOMCP(bp)) {
452427b0
YM		 12016 /* init fw_seq */
12017 bp->fw_seq =
12018 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12019 DRV_MSG_SEQ_NUMBER_MASK;
12020 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12021
91ebb929
YM		 12022 rc = bnx2x_prev_unload(bp);
12023 if (rc) {
12024 bnx2x_free_mem_bp(bp);
12025 return rc;
12026 }
452427b0
YM		 12027 }
12028
34f80b04 12029 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 12030 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 12031
12032 if (BP_NOMCP(bp) && (func == 0))
51c1a580 12033 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
34f80b04 12034
614c76df 12035 bp->disable_tpa = disable_tpa;
a3348722 12036 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
94d9de3c
MS		 12037 /* Reduce memory usage in kdump environment by disabling TPA */
12038 bp->disable_tpa |= reset_devices;
614c76df 12039
7a9b2557 12040 /* Set TPA flags */
614c76df 12041 if (bp->disable_tpa) {
621b4d66 12042 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 12043 bp->dev->features &= ~NETIF_F_LRO;
12044 } else {
621b4d66 12045 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 12046 bp->dev->features |= NETIF_F_LRO;
12047 }
12048
a18f5128
EG		 12049 if (CHIP_IS_E1(bp))
12050 bp->dropless_fc = 0;
12051 else
7964211d 12052 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
a18f5128 12053
8d5726c4 12054 bp->mrrs = mrrs;
7a9b2557 12055
a3348722 12056 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1ab4434c
AE		 12057 if (IS_VF(bp))
12058 bp->rx_ring_size = MAX_RX_AVAIL;
34f80b04 12059
7d323bfd 12060 /* make sure that the numbers are in the right granularity */
523224a3
DK		 12061 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12062 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 12063
fc543637 12064 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
34f80b04
EG		 12065
12066 init_timer(&bp->timer);
12067 bp->timer.expires = jiffies + bp->current_interval;
12068 bp->timer.data = (unsigned long) bp;
12069 bp->timer.function = bnx2x_timer;
12070
0370cf90
BW		 12071 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12072 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12073 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12074 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12075 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12076 bnx2x_dcbx_init_params(bp);
12077 } else {
12078 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12079 }
e4901dde 12080
619c5cb6
VZ		 12081 if (CHIP_IS_E1x(bp))
12082 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12083 else
12084 bp->cnic_base_cl_id = FP_SB_MAX_E2;
619c5cb6 12085
6383c0b3 12086 /* multiple tx priority */
1ab4434c
AE		 12087 if (IS_VF(bp))
12088 bp->max_cos = 1;
12089 else if (CHIP_IS_E1x(bp))
6383c0b3 12090 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
1ab4434c 12091 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
6383c0b3 12092 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
1ab4434c 12093 else if (CHIP_IS_E3B0(bp))
6383c0b3 12094 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
1ab4434c
AE		 12095 else
12096 BNX2X_ERR("unknown chip %x revision %x\n",
12097 CHIP_NUM(bp), CHIP_REV(bp));
12098 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
6383c0b3 12099
55c11941
MS		 12100 /* We need at least one default status block for slow-path events,
12101 * second status block for the L2 queue, and a third status block for
16a5fd92 12102 * CNIC if supported.
55c11941 12103 */
60cad4e6
AE		 12104 if (IS_VF(bp))
12105 bp->min_msix_vec_cnt = 1;
12106 else if (CNIC_SUPPORT(bp))
55c11941 12107 bp->min_msix_vec_cnt = 3;
60cad4e6 12108 else /* PF w/o cnic */
55c11941
MS		 12109 bp->min_msix_vec_cnt = 2;
12110 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12111
5bb680d6
MS		 12112 bp->dump_preset_idx = 1;
12113
eeed018c
MK		 12114 if (CHIP_IS_E3B0(bp))
12115 bp->flags |= PTP_SUPPORTED;
12116
34f80b04 12117 return rc;
a2fbb9ea
ET		 12118}
12119
de0c62db
DK		 12120/****************************************************************************
12121* General service functions
12122****************************************************************************/
a2fbb9ea 12123
619c5cb6
VZ		 12124/*
12125 * net_device service functions
12126 */
12127
bb2a0f7a 12128/* called with rtnl_lock */
a2fbb9ea
ET		 12129static int bnx2x_open(struct net_device *dev)
12130{
12131 struct bnx2x *bp = netdev_priv(dev);
8395be5e 12132 int rc;
a2fbb9ea 12133
1355b704
MY		 12134 bp->stats_init = true;
12135
6eccabb3
EG		 12136 netif_carrier_off(dev);
12137
a2fbb9ea
ET		 12138 bnx2x_set_power_state(bp, PCI_D0);
12139
ad5afc89 12140 /* If parity had happen during the unload, then attentions
c9ee9206
VZ		 12141 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12142 * want the first function loaded on the current engine to
12143 * complete the recovery.
ad5afc89 12144 * Parity recovery is only relevant for PF driver.
c9ee9206 12145 */
ad5afc89 12146 if (IS_PF(bp)) {
1a6974b2
YM		 12147 int other_engine = BP_PATH(bp) ? 0 : 1;
12148 bool other_load_status, load_status;
12149 bool global = false;
12150
ad5afc89
AE		 12151 other_load_status = bnx2x_get_load_status(bp, other_engine);
12152 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12153 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12154 bnx2x_chk_parity_attn(bp, &global, true)) {
12155 do {
12156 /* If there are attentions and they are in a
12157 * global blocks, set the GLOBAL_RESET bit
12158 * regardless whether it will be this function
12159 * that will complete the recovery or not.
12160 */
12161 if (global)
12162 bnx2x_set_reset_global(bp);
72fd0718 12163
ad5afc89
AE		 12164 /* Only the first function on the current
12165 * engine should try to recover in open. In case
12166 * of attentions in global blocks only the first
12167 * in the chip should try to recover.
12168 */
12169 if ((!load_status &&
12170 (!global || !other_load_status)) &&
12171 bnx2x_trylock_leader_lock(bp) &&
12172 !bnx2x_leader_reset(bp)) {
12173 netdev_info(bp->dev,
12174 "Recovered in open\n");
12175 break;
12176 }
72fd0718 12177
ad5afc89
AE		 12178 /* recovery has failed... */
12179 bnx2x_set_power_state(bp, PCI_D3hot);
12180 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 12181
ad5afc89
AE		 12182 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12183 "If you still see this message after a few retries then power cycle is required.\n");
72fd0718 12184
ad5afc89
AE		 12185 return -EAGAIN;
12186 } while (0);
12187 }
12188 }
72fd0718
VZ		 12189
12190 bp->recovery_state = BNX2X_RECOVERY_DONE;
8395be5e
AE		 12191 rc = bnx2x_nic_load(bp, LOAD_OPEN);
12192 if (rc)
12193 return rc;
9a8130bc 12194 return 0;
a2fbb9ea
ET		 12195}
12196
bb2a0f7a 12197/* called with rtnl_lock */
56ad3152 12198static int bnx2x_close(struct net_device *dev)
a2fbb9ea 12199{
a2fbb9ea
ET		 12200 struct bnx2x *bp = netdev_priv(dev);
12201
12202 /* Unload the driver, release IRQs */
5d07d868 12203 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
c9ee9206 12204
a2fbb9ea
ET		 12205 return 0;
12206}
12207
1191cb83
ED		 12208static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12209 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 12210{
619c5cb6
VZ		 12211 int mc_count = netdev_mc_count(bp->dev);
12212 struct bnx2x_mcast_list_elem *mc_mac =
cd2b0389 12213 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
619c5cb6 12214 struct netdev_hw_addr *ha;
6e30dd4e 12215
619c5cb6
VZ		 12216 if (!mc_mac)
12217 return -ENOMEM;
6e30dd4e 12218
619c5cb6 12219 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 12220
619c5cb6
VZ		 12221 netdev_for_each_mc_addr(ha, bp->dev) {
12222 mc_mac->mac = bnx2x_mc_addr(ha);
12223 list_add_tail(&mc_mac->link, &p->mcast_list);
12224 mc_mac++;
6e30dd4e 12225 }
619c5cb6
VZ		 12226
12227 p->mcast_list_len = mc_count;
12228
12229 return 0;
6e30dd4e
VZ		 12230}
12231
1191cb83 12232static void bnx2x_free_mcast_macs_list(
619c5cb6
VZ		 12233 struct bnx2x_mcast_ramrod_params *p)
12234{
12235 struct bnx2x_mcast_list_elem *mc_mac =
12236 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12237 link);
12238
12239 WARN_ON(!mc_mac);
12240 kfree(mc_mac);
12241}
12242
12243/**
12244 * bnx2x_set_uc_list - configure a new unicast MACs list.
12245 *
12246 * @bp: driver handle
6e30dd4e 12247 *
619c5cb6 12248 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 12249 */
1191cb83 12250static int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 12251{
619c5cb6 12252 int rc;
6e30dd4e 12253 struct net_device *dev = bp->dev;
6e30dd4e 12254 struct netdev_hw_addr *ha;
15192a8c 12255 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
619c5cb6 12256 unsigned long ramrod_flags = 0;
6e30dd4e 12257
619c5cb6
VZ		 12258 /* First schedule a cleanup up of old configuration */
12259 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12260 if (rc < 0) {
12261 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12262 return rc;
12263 }
6e30dd4e
VZ		 12264
12265 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 12266 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12267 BNX2X_UC_LIST_MAC, &ramrod_flags);
7b5342d9
YM		 12268 if (rc == -EEXIST) {
12269 DP(BNX2X_MSG_SP,
12270 "Failed to schedule ADD operations: %d\n", rc);
12271 /* do not treat adding same MAC as error */
12272 rc = 0;
12273
12274 } else if (rc < 0) {
12275
619c5cb6
VZ		 12276 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12277 rc);
12278 return rc;
6e30dd4e
VZ		 12279 }
12280 }
12281
619c5cb6
VZ		 12282 /* Execute the pending commands */
12283 __set_bit(RAMROD_CONT, &ramrod_flags);
12284 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12285 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 12286}
12287
1191cb83 12288static int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 12289{
619c5cb6 12290 struct net_device *dev = bp->dev;
3b603066 12291 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6 12292 int rc = 0;
6e30dd4e 12293
619c5cb6 12294 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 12295
619c5cb6
VZ		 12296 /* first, clear all configured multicast MACs */
12297 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12298 if (rc < 0) {
51c1a580 12299 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
619c5cb6
VZ		 12300 return rc;
12301 }
6e30dd4e 12302
619c5cb6
VZ		 12303 /* then, configure a new MACs list */
12304 if (netdev_mc_count(dev)) {
12305 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12306 if (rc) {
51c1a580
MS		 12307 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12308 rc);
619c5cb6
VZ		 12309 return rc;
12310 }
6e30dd4e 12311
619c5cb6
VZ		 12312 /* Now add the new MACs */
12313 rc = bnx2x_config_mcast(bp, &rparam,
12314 BNX2X_MCAST_CMD_ADD);
12315 if (rc < 0)
51c1a580
MS		 12316 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12317 rc);
6e30dd4e 12318
619c5cb6
VZ		 12319 bnx2x_free_mcast_macs_list(&rparam);
12320 }
6e30dd4e 12321
619c5cb6 12322 return rc;
6e30dd4e
VZ		 12323}
12324
619c5cb6 12325/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
a8f47eb7 12326static void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 12327{
12328 struct bnx2x *bp = netdev_priv(dev);
34f80b04
EG		 12329
12330 if (bp->state != BNX2X_STATE_OPEN) {
12331 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12332 return;
8b09be5f
YM		 12333 } else {
12334 /* Schedule an SP task to handle rest of change */
230bb0f3
YM		 12335 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12336 NETIF_MSG_IFUP);
34f80b04 12337 }
8b09be5f
YM		 12338}
12339
12340void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12341{
12342 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04 12343
619c5cb6 12344 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04 12345
8b09be5f
YM		 12346 netif_addr_lock_bh(bp->dev);
12347
12348 if (bp->dev->flags & IFF_PROMISC) {
34f80b04 12349 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f
YM		 12350 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12351 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12352 CHIP_IS_E1(bp))) {
34f80b04 12353 rx_mode = BNX2X_RX_MODE_ALLMULTI;
8b09be5f 12354 } else {
381ac16b
AE		 12355 if (IS_PF(bp)) {
12356 /* some multicasts */
12357 if (bnx2x_set_mc_list(bp) < 0)
12358 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 12359
8b09be5f
YM		 12360 /* release bh lock, as bnx2x_set_uc_list might sleep */
12361 netif_addr_unlock_bh(bp->dev);
381ac16b
AE		 12362 if (bnx2x_set_uc_list(bp) < 0)
12363 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f 12364 netif_addr_lock_bh(bp->dev);
381ac16b
AE		 12365 } else {
12366 /* configuring mcast to a vf involves sleeping (when we
8b09be5f 12367 * wait for the pf's response).
381ac16b 12368 */
230bb0f3
YM		 12369 bnx2x_schedule_sp_rtnl(bp,
12370 BNX2X_SP_RTNL_VFPF_MCAST, 0);
381ac16b 12371 }
34f80b04
EG		 12372 }
12373
12374 bp->rx_mode = rx_mode;
614c76df
DK		 12375 /* handle ISCSI SD mode */
12376 if (IS_MF_ISCSI_SD(bp))
12377 bp->rx_mode = BNX2X_RX_MODE_NONE;
619c5cb6
VZ		 12378
12379 /* Schedule the rx_mode command */
12380 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12381 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8b09be5f 12382 netif_addr_unlock_bh(bp->dev);
619c5cb6
VZ		 12383 return;
12384 }
12385
381ac16b
AE		 12386 if (IS_PF(bp)) {
12387 bnx2x_set_storm_rx_mode(bp);
8b09be5f 12388 netif_addr_unlock_bh(bp->dev);
381ac16b 12389 } else {
8b09be5f
YM		 12390 /* VF will need to request the PF to make this change, and so
12391 * the VF needs to release the bottom-half lock prior to the
12392 * request (as it will likely require sleep on the VF side)
381ac16b 12393 */
8b09be5f
YM		 12394 netif_addr_unlock_bh(bp->dev);
12395 bnx2x_vfpf_storm_rx_mode(bp);
381ac16b 12396 }
34f80b04
EG		 12397}
12398
c18487ee 12399/* called with rtnl_lock */
01cd4528
EG		 12400static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12401 int devad, u16 addr)
a2fbb9ea 12402{
01cd4528
EG		 12403 struct bnx2x *bp = netdev_priv(netdev);
12404 u16 value;
12405 int rc;
a2fbb9ea 12406
01cd4528
EG		 12407 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12408 prtad, devad, addr);
a2fbb9ea 12409
01cd4528
EG		 12410 /* The HW expects different devad if CL22 is used */
12411 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 12412
01cd4528 12413 bnx2x_acquire_phy_lock(bp);
e10bc84d 12414 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 12415 bnx2x_release_phy_lock(bp);
12416 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 12417
01cd4528
EG		 12418 if (!rc)
12419 rc = value;
12420 return rc;
12421}
a2fbb9ea 12422
01cd4528
EG		 12423/* called with rtnl_lock */
12424static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12425 u16 addr, u16 value)
12426{
12427 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 12428 int rc;
12429
51c1a580
MS		 12430 DP(NETIF_MSG_LINK,
12431 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12432 prtad, devad, addr, value);
01cd4528 12433
01cd4528
EG		 12434 /* The HW expects different devad if CL22 is used */
12435 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 12436
01cd4528 12437 bnx2x_acquire_phy_lock(bp);
e10bc84d 12438 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 12439 bnx2x_release_phy_lock(bp);
12440 return rc;
12441}
c18487ee 12442
01cd4528
EG		 12443/* called with rtnl_lock */
12444static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12445{
12446 struct bnx2x *bp = netdev_priv(dev);
12447 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 12448
01cd4528
EG		 12449 if (!netif_running(dev))
12450 return -EAGAIN;
12451
eeed018c
MK		 12452 switch (cmd) {
12453 case SIOCSHWTSTAMP:
12454 return bnx2x_hwtstamp_ioctl(bp, ifr);
12455 default:
12456 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12457 mdio->phy_id, mdio->reg_num, mdio->val_in);
12458 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12459 }
a2fbb9ea
ET		 12460}
12461
257ddbda 12462#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 12463static void poll_bnx2x(struct net_device *dev)
12464{
12465 struct bnx2x *bp = netdev_priv(dev);
14a15d61 12466 int i;
a2fbb9ea 12467
14a15d61
MS		 12468 for_each_eth_queue(bp, i) {
12469 struct bnx2x_fastpath *fp = &bp->fp[i];
12470 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12471 }
a2fbb9ea
ET		 12472}
12473#endif
12474
614c76df
DK		 12475static int bnx2x_validate_addr(struct net_device *dev)
12476{
12477 struct bnx2x *bp = netdev_priv(dev);
12478
e09b74d0
AE		 12479 /* query the bulletin board for mac address configured by the PF */
12480 if (IS_VF(bp))
12481 bnx2x_sample_bulletin(bp);
12482
51c1a580
MS		 12483 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
12484 BNX2X_ERR("Non-valid Ethernet address\n");
614c76df 12485 return -EADDRNOTAVAIL;
51c1a580 12486 }
614c76df
DK		 12487 return 0;
12488}
12489
3d7d562c
YM		 12490static int bnx2x_get_phys_port_id(struct net_device *netdev,
12491 struct netdev_phys_port_id *ppid)
12492{
12493 struct bnx2x *bp = netdev_priv(netdev);
12494
12495 if (!(bp->flags & HAS_PHYS_PORT_ID))
12496 return -EOPNOTSUPP;
12497
12498 ppid->id_len = sizeof(bp->phys_port_id);
12499 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12500
12501 return 0;
12502}
12503
c64213cd
SH		 12504static const struct net_device_ops bnx2x_netdev_ops = {
12505 .ndo_open = bnx2x_open,
12506 .ndo_stop = bnx2x_close,
12507 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 12508 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 12509 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 12510 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 12511 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 12512 .ndo_do_ioctl = bnx2x_ioctl,
12513 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 12514 .ndo_fix_features = bnx2x_fix_features,
12515 .ndo_set_features = bnx2x_set_features,
c64213cd 12516 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 12517#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 12518 .ndo_poll_controller = poll_bnx2x,
12519#endif
6383c0b3 12520 .ndo_setup_tc = bnx2x_setup_tc,
6411280a 12521#ifdef CONFIG_BNX2X_SRIOV
abc5a021 12522 .ndo_set_vf_mac = bnx2x_set_vf_mac,
3cdeec22 12523 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
3ec9f9ca 12524 .ndo_get_vf_config = bnx2x_get_vf_config,
6411280a 12525#endif
55c11941 12526#ifdef NETDEV_FCOE_WWNN
bf61ee14
VZ		 12527 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
12528#endif
8f20aa57 12529
e0d1095a 12530#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 12531 .ndo_busy_poll = bnx2x_low_latency_recv,
8f20aa57 12532#endif
3d7d562c 12533 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
6495d15a 12534 .ndo_set_vf_link_state = bnx2x_set_vf_link_state,
c64213cd
SH		 12535};
12536
1191cb83 12537static int bnx2x_set_coherency_mask(struct bnx2x *bp)
619c5cb6
VZ		 12538{
12539 struct device *dev = &bp->pdev->dev;
12540
8ceafbfa
LT		 12541 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12542 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
619c5cb6
VZ		 12543 dev_err(dev, "System does not support DMA, aborting\n");
12544 return -EIO;
12545 }
12546
12547 return 0;
12548}
12549
33d8e6a5
YM		 12550static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12551{
12552 if (bp->flags & AER_ENABLED) {
12553 pci_disable_pcie_error_reporting(bp->pdev);
12554 bp->flags &= ~AER_ENABLED;
12555 }
12556}
12557
1ab4434c
AE		 12558static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12559 struct net_device *dev, unsigned long board_type)
a2fbb9ea 12560{
a2fbb9ea 12561 int rc;
c22610d0 12562 u32 pci_cfg_dword;
65087cfe
AE		 12563 bool chip_is_e1x = (board_type == BCM57710 ||
12564 board_type == BCM57711 ||
12565 board_type == BCM57711E);
a2fbb9ea
ET		 12566
12567 SET_NETDEV_DEV(dev, &pdev->dev);
a2fbb9ea 12568
34f80b04
EG		 12569 bp->dev = dev;
12570 bp->pdev = pdev;
a2fbb9ea
ET		 12571
12572 rc = pci_enable_device(pdev);
12573 if (rc) {
cdaa7cb8
VZ		 12574 dev_err(&bp->pdev->dev,
12575 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 12576 goto err_out;
12577 }
12578
12579 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 12580 dev_err(&bp->pdev->dev,
12581 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 12582 rc = -ENODEV;
12583 goto err_out_disable;
12584 }
12585
1ab4434c
AE		 12586 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12587 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
a2fbb9ea
ET		 12588 rc = -ENODEV;
12589 goto err_out_disable;
12590 }
12591
092a5fc9
YR		 12592 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12593 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12594 PCICFG_REVESION_ID_ERROR_VAL) {
12595 pr_err("PCI device error, probably due to fan failure, aborting\n");
12596 rc = -ENODEV;
12597 goto err_out_disable;
12598 }
12599
34f80b04
EG		 12600 if (atomic_read(&pdev->enable_cnt) == 1) {
12601 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12602 if (rc) {
cdaa7cb8
VZ		 12603 dev_err(&bp->pdev->dev,
12604 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 12605 goto err_out_disable;
12606 }
a2fbb9ea 12607
34f80b04
EG		 12608 pci_set_master(pdev);
12609 pci_save_state(pdev);
12610 }
a2fbb9ea 12611
1ab4434c 12612 if (IS_PF(bp)) {
29ed74c3 12613 if (!pdev->pm_cap) {
1ab4434c
AE		 12614 dev_err(&bp->pdev->dev,
12615 "Cannot find power management capability, aborting\n");
12616 rc = -EIO;
12617 goto err_out_release;
12618 }
a2fbb9ea
ET		 12619 }
12620
77c98e6a 12621 if (!pci_is_pcie(pdev)) {
51c1a580 12622 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 12623 rc = -EIO;
12624 goto err_out_release;
12625 }
12626
619c5cb6
VZ		 12627 rc = bnx2x_set_coherency_mask(bp);
12628 if (rc)
a2fbb9ea 12629 goto err_out_release;
a2fbb9ea 12630
34f80b04
EG		 12631 dev->mem_start = pci_resource_start(pdev, 0);
12632 dev->base_addr = dev->mem_start;
12633 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 12634
12635 dev->irq = pdev->irq;
12636
275f165f 12637 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 12638 if (!bp->regview) {
cdaa7cb8
VZ		 12639 dev_err(&bp->pdev->dev,
12640 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 12641 rc = -ENOMEM;
12642 goto err_out_release;
12643 }
12644
c22610d0
AE		 12645 /* In E1/E1H use pci device function given by kernel.
12646 * In E2/E3 read physical function from ME register since these chips
12647 * support Physical Device Assignment where kernel BDF maybe arbitrary
12648 * (depending on hypervisor).
12649 */
2de67439 12650 if (chip_is_e1x) {
c22610d0 12651 bp->pf_num = PCI_FUNC(pdev->devfn);
2de67439
YM		 12652 } else {
12653 /* chip is E2/3*/
c22610d0
AE		 12654 pci_read_config_dword(bp->pdev,
12655 PCICFG_ME_REGISTER, &pci_cfg_dword);
12656 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
2de67439 12657 ME_REG_ABS_PF_NUM_SHIFT);
c22610d0 12658 }
51c1a580 12659 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
c22610d0 12660
34f80b04
EG		 12661 /* clean indirect addresses */
12662 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12663 PCICFG_VENDOR_ID_OFFSET);
33d8e6a5
YM		 12664
12665 /* AER (Advanced Error reporting) configuration */
12666 rc = pci_enable_pcie_error_reporting(pdev);
12667 if (!rc)
12668 bp->flags |= AER_ENABLED;
12669 else
12670 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12671
a5c53dbc
DK		 12672 /*
12673 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 12674 * is not used by the driver.
12675 */
1ab4434c
AE		 12676 if (IS_PF(bp)) {
12677 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12678 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12679 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12680 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12681
12682 if (chip_is_e1x) {
12683 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12684 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12685 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12686 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12687 }
a5c53dbc 12688
1ab4434c
AE		 12689 /* Enable internal target-read (in case we are probed after PF
12690 * FLR). Must be done prior to any BAR read access. Only for
12691 * 57712 and up
12692 */
12693 if (!chip_is_e1x)
12694 REG_WR(bp,
12695 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
a5c53dbc 12696 }
a2fbb9ea 12697
34f80b04 12698 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 12699
c64213cd 12700 dev->netdev_ops = &bnx2x_netdev_ops;
005a07ba 12701 bnx2x_set_ethtool_ops(bp, dev);
5316bc0b 12702
01789349
JP		 12703 dev->priv_flags |= IFF_UNICAST_FLT;
12704
66371c44 12705 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
621b4d66
DK		 12706 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12707 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
f646968f 12708 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
a848ade4 12709 if (!CHIP_IS_E1x(bp)) {
117401ee 12710 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
2e3bd6a4 12711 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
a848ade4
DK		 12712 dev->hw_enc_features =
12713 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12714 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
117401ee 12715 NETIF_F_GSO_IPIP |
2e3bd6a4 12716 NETIF_F_GSO_SIT |
65bc0cfe 12717 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
a848ade4 12718 }
66371c44
MM		 12719
12720 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12721 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12722
f646968f 12723 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
edd31476 12724 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 12725
538dd2e3
MB		 12726 /* Add Loopback capability to the device */
12727 dev->hw_features |= NETIF_F_LOOPBACK;
12728
98507672 12729#ifdef BCM_DCBNL
785b9b1a
SR		 12730 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12731#endif
12732
01cd4528
EG		 12733 /* get_port_hwinfo() will set prtad and mmds properly */
12734 bp->mdio.prtad = MDIO_PRTAD_NONE;
12735 bp->mdio.mmds = 0;
12736 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12737 bp->mdio.dev = dev;
12738 bp->mdio.mdio_read = bnx2x_mdio_read;
12739 bp->mdio.mdio_write = bnx2x_mdio_write;
12740
a2fbb9ea
ET		 12741 return 0;
12742
a2fbb9ea 12743err_out_release:
34f80b04
EG		 12744 if (atomic_read(&pdev->enable_cnt) == 1)
12745 pci_release_regions(pdev);
a2fbb9ea
ET		 12746
12747err_out_disable:
12748 pci_disable_device(pdev);
a2fbb9ea
ET		 12749
12750err_out:
12751 return rc;
12752}
12753
6891dd25 12754static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 12755{
37f9ce62 12756 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 12757 struct bnx2x_fw_file_hdr *fw_hdr;
12758 struct bnx2x_fw_file_section *sections;
94a78b79 12759 u32 offset, len, num_ops;
86564c3f 12760 __be16 *ops_offsets;
94a78b79 12761 int i;
37f9ce62 12762 const u8 *fw_ver;
94a78b79 12763
51c1a580
MS		 12764 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12765 BNX2X_ERR("Wrong FW size\n");
94a78b79 12766 return -EINVAL;
51c1a580 12767 }
94a78b79
VZ		 12768
12769 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12770 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12771
12772 /* Make sure none of the offsets and sizes make us read beyond
12773 * the end of the firmware data */
12774 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12775 offset = be32_to_cpu(sections[i].offset);
12776 len = be32_to_cpu(sections[i].len);
12777 if (offset + len > firmware->size) {
51c1a580 12778 BNX2X_ERR("Section %d length is out of bounds\n", i);
94a78b79
VZ		 12779 return -EINVAL;
12780 }
12781 }
12782
12783 /* Likewise for the init_ops offsets */
12784 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
86564c3f 12785 ops_offsets = (__force __be16 *)(firmware->data + offset);
94a78b79
VZ		 12786 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12787
12788 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12789 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
51c1a580 12790 BNX2X_ERR("Section offset %d is out of bounds\n", i);
94a78b79
VZ		 12791 return -EINVAL;
12792 }
12793 }
12794
12795 /* Check FW version */
12796 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12797 fw_ver = firmware->data + offset;
12798 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12799 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12800 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12801 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
51c1a580
MS		 12802 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12803 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12804 BCM_5710_FW_MAJOR_VERSION,
94a78b79
VZ		 12805 BCM_5710_FW_MINOR_VERSION,
12806 BCM_5710_FW_REVISION_VERSION,
12807 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 12808 return -EINVAL;
94a78b79
VZ		 12809 }
12810
12811 return 0;
12812}
12813
1191cb83 12814static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 12815{
ab6ad5a4
EG		 12816 const __be32 *source = (const __be32 *)_source;
12817 u32 *target = (u32 *)_target;
94a78b79 12818 u32 i;
94a78b79
VZ		 12819
12820 for (i = 0; i < n/4; i++)
12821 target[i] = be32_to_cpu(source[i]);
12822}
12823
12824/*
12825 Ops array is stored in the following format:
12826 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12827 */
1191cb83 12828static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 12829{
ab6ad5a4
EG		 12830 const __be32 *source = (const __be32 *)_source;
12831 struct raw_op *target = (struct raw_op *)_target;
94a78b79 12832 u32 i, j, tmp;
94a78b79 12833
ab6ad5a4 12834 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 12835 tmp = be32_to_cpu(source[j]);
12836 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 12837 target[i].offset = tmp & 0xffffff;
12838 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 12839 }
12840}
ab6ad5a4 12841
1aa8b471 12842/* IRO array is stored in the following format:
523224a3
DK		 12843 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12844 */
1191cb83 12845static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
523224a3
DK		 12846{
12847 const __be32 *source = (const __be32 *)_source;
12848 struct iro *target = (struct iro *)_target;
12849 u32 i, j, tmp;
12850
12851 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12852 target[i].base = be32_to_cpu(source[j]);
12853 j++;
12854 tmp = be32_to_cpu(source[j]);
12855 target[i].m1 = (tmp >> 16) & 0xffff;
12856 target[i].m2 = tmp & 0xffff;
12857 j++;
12858 tmp = be32_to_cpu(source[j]);
12859 target[i].m3 = (tmp >> 16) & 0xffff;
12860 target[i].size = tmp & 0xffff;
12861 j++;
12862 }
12863}
12864
1191cb83 12865static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 12866{
ab6ad5a4
EG		 12867 const __be16 *source = (const __be16 *)_source;
12868 u16 *target = (u16 *)_target;
94a78b79 12869 u32 i;
94a78b79
VZ		 12870
12871 for (i = 0; i < n/2; i++)
12872 target[i] = be16_to_cpu(source[i]);
12873}
12874
7995c64e
JP		 12875#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12876do { \
12877 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12878 bp->arr = kmalloc(len, GFP_KERNEL); \
e404decb 12879 if (!bp->arr) \
7995c64e 12880 goto lbl; \
7995c64e
JP		 12881 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12882 (u8 *)bp->arr, len); \
12883} while (0)
94a78b79 12884
3b603066 12885static int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 12886{
c0ea452e 12887 const char *fw_file_name;
94a78b79 12888 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 12889 int rc;
94a78b79 12890
c0ea452e
MS		 12891 if (bp->firmware)
12892 return 0;
94a78b79 12893
c0ea452e
MS		 12894 if (CHIP_IS_E1(bp))
12895 fw_file_name = FW_FILE_NAME_E1;
12896 else if (CHIP_IS_E1H(bp))
12897 fw_file_name = FW_FILE_NAME_E1H;
12898 else if (!CHIP_IS_E1x(bp))
12899 fw_file_name = FW_FILE_NAME_E2;
12900 else {
12901 BNX2X_ERR("Unsupported chip revision\n");
12902 return -EINVAL;
12903 }
12904 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 12905
c0ea452e
MS		 12906 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12907 if (rc) {
12908 BNX2X_ERR("Can't load firmware file %s\n",
12909 fw_file_name);
12910 goto request_firmware_exit;
12911 }
eb2afd4a 12912
c0ea452e
MS		 12913 rc = bnx2x_check_firmware(bp);
12914 if (rc) {
12915 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12916 goto request_firmware_exit;
94a78b79
VZ		 12917 }
12918
12919 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12920
12921 /* Initialize the pointers to the init arrays */
12922 /* Blob */
12923 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12924
12925 /* Opcodes */
12926 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12927
12928 /* Offsets */
ab6ad5a4
EG		 12929 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12930 be16_to_cpu_n);
94a78b79
VZ		 12931
12932 /* STORMs firmware */
573f2035
EG		 12933 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12934 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12935 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12936 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12937 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12938 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12939 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12940 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12941 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12942 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12943 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12944 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12945 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12946 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12947 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12948 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 12949 /* IRO */
12950 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 12951
12952 return 0;
ab6ad5a4 12953
523224a3
DK		 12954iro_alloc_err:
12955 kfree(bp->init_ops_offsets);
94a78b79
VZ		 12956init_offsets_alloc_err:
12957 kfree(bp->init_ops);
12958init_ops_alloc_err:
12959 kfree(bp->init_data);
12960request_firmware_exit:
12961 release_firmware(bp->firmware);
127d0a19 12962 bp->firmware = NULL;
94a78b79
VZ		 12963
12964 return rc;
12965}
12966
619c5cb6
VZ		 12967static void bnx2x_release_firmware(struct bnx2x *bp)
12968{
12969 kfree(bp->init_ops_offsets);
12970 kfree(bp->init_ops);
12971 kfree(bp->init_data);
12972 release_firmware(bp->firmware);
eb2afd4a 12973 bp->firmware = NULL;
619c5cb6
VZ		 12974}
12975
619c5cb6
VZ		 12976static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12977 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12978 .init_hw_cmn = bnx2x_init_hw_common,
12979 .init_hw_port = bnx2x_init_hw_port,
12980 .init_hw_func = bnx2x_init_hw_func,
12981
12982 .reset_hw_cmn = bnx2x_reset_common,
12983 .reset_hw_port = bnx2x_reset_port,
12984 .reset_hw_func = bnx2x_reset_func,
12985
12986 .gunzip_init = bnx2x_gunzip_init,
12987 .gunzip_end = bnx2x_gunzip_end,
12988
12989 .init_fw = bnx2x_init_firmware,
12990 .release_fw = bnx2x_release_firmware,
12991};
12992
12993void bnx2x__init_func_obj(struct bnx2x *bp)
12994{
12995 /* Prepare DMAE related driver resources */
12996 bnx2x_setup_dmae(bp);
12997
12998 bnx2x_init_func_obj(bp, &bp->func_obj,
12999 bnx2x_sp(bp, func_rdata),
13000 bnx2x_sp_mapping(bp, func_rdata),
a3348722
BW		 13001 bnx2x_sp(bp, func_afex_rdata),
13002 bnx2x_sp_mapping(bp, func_afex_rdata),
619c5cb6
VZ		 13003 &bnx2x_func_sp_drv);
13004}
13005
13006/* must be called after sriov-enable */
1191cb83 13007static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 13008{
37ae41a9 13009 int cid_count = BNX2X_L2_MAX_CID(bp);
94a78b79 13010
290ca2bb
AE		 13011 if (IS_SRIOV(bp))
13012 cid_count += BNX2X_VF_CIDS;
13013
55c11941
MS		 13014 if (CNIC_SUPPORT(bp))
13015 cid_count += CNIC_CID_MAX;
290ca2bb 13016
523224a3
DK		 13017 return roundup(cid_count, QM_CID_ROUND);
13018}
f85582f8 13019
619c5cb6 13020/**
6383c0b3 13021 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 13022 *
13023 * @dev: pci device
13024 *
13025 */
60cad4e6 13026static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
619c5cb6 13027{
ae2104be 13028 int index;
1ab4434c 13029 u16 control = 0;
619c5cb6 13030
6383c0b3
AE		 13031 /*
13032 * If MSI-X is not supported - return number of SBs needed to support
13033 * one fast path queue: one FP queue + SB for CNIC
13034 */
ae2104be 13035 if (!pdev->msix_cap) {
1ab4434c 13036 dev_info(&pdev->dev, "no msix capability found\n");
55c11941 13037 return 1 + cnic_cnt;
1ab4434c
AE		 13038 }
13039 dev_info(&pdev->dev, "msix capability found\n");
619c5cb6 13040
6383c0b3
AE		 13041 /*
13042 * The value in the PCI configuration space is the index of the last
13043 * entry, namely one less than the actual size of the table, which is
13044 * exactly what we want to return from this function: number of all SBs
13045 * without the default SB.
1ab4434c 13046 * For VFs there is no default SB, then we return (index+1).
6383c0b3 13047 */
73413ffa 13048 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
619c5cb6 13049
1ab4434c 13050 index = control & PCI_MSIX_FLAGS_QSIZE;
4bd9b0ff 13051
60cad4e6 13052 return index;
1ab4434c 13053}
523224a3 13054
1ab4434c
AE		 13055static int set_max_cos_est(int chip_id)
13056{
13057 switch (chip_id) {
f2e0899f
DK		 13058 case BCM57710:
13059 case BCM57711:
13060 case BCM57711E:
1ab4434c 13061 return BNX2X_MULTI_TX_COS_E1X;
f2e0899f 13062 case BCM57712:
619c5cb6 13063 case BCM57712_MF:
1ab4434c 13064 return BNX2X_MULTI_TX_COS_E2_E3A0;
619c5cb6
VZ		 13065 case BCM57800:
13066 case BCM57800_MF:
13067 case BCM57810:
13068 case BCM57810_MF:
c3def943
YM		 13069 case BCM57840_4_10:
13070 case BCM57840_2_20:
1ab4434c 13071 case BCM57840_O:
c3def943 13072 case BCM57840_MFO:
619c5cb6 13073 case BCM57840_MF:
7e8e02df
BW		 13074 case BCM57811:
13075 case BCM57811_MF:
1ab4434c 13076 return BNX2X_MULTI_TX_COS_E3B0;
b1239723
YM		 13077 case BCM57712_VF:
13078 case BCM57800_VF:
13079 case BCM57810_VF:
13080 case BCM57840_VF:
13081 case BCM57811_VF:
1ab4434c 13082 return 1;
f2e0899f 13083 default:
1ab4434c 13084 pr_err("Unknown board_type (%d), aborting\n", chip_id);
870634b0 13085 return -ENODEV;
f2e0899f 13086 }
1ab4434c 13087}
f2e0899f 13088
1ab4434c
AE		 13089static int set_is_vf(int chip_id)
13090{
13091 switch (chip_id) {
13092 case BCM57712_VF:
13093 case BCM57800_VF:
13094 case BCM57810_VF:
13095 case BCM57840_VF:
13096 case BCM57811_VF:
13097 return true;
13098 default:
13099 return false;
13100 }
13101}
6383c0b3 13102
eeed018c
MK		 13103/* nig_tsgen registers relative address */
13104#define tsgen_ctrl 0x0
13105#define tsgen_freecount 0x10
13106#define tsgen_synctime_t0 0x20
13107#define tsgen_offset_t0 0x28
13108#define tsgen_drift_t0 0x30
13109#define tsgen_synctime_t1 0x58
13110#define tsgen_offset_t1 0x60
13111#define tsgen_drift_t1 0x68
13112
13113/* FW workaround for setting drift */
13114static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13115 int best_val, int best_period)
13116{
13117 struct bnx2x_func_state_params func_params = {NULL};
13118 struct bnx2x_func_set_timesync_params *set_timesync_params =
13119 &func_params.params.set_timesync;
13120
13121 /* Prepare parameters for function state transitions */
13122 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13123 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13124
13125 func_params.f_obj = &bp->func_obj;
13126 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13127
13128 /* Function parameters */
13129 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13130 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13131 set_timesync_params->add_sub_drift_adjust_value =
13132 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13133 set_timesync_params->drift_adjust_value = best_val;
13134 set_timesync_params->drift_adjust_period = best_period;
13135
13136 return bnx2x_func_state_change(bp, &func_params);
13137}
13138
13139static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13140{
13141 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13142 int rc;
13143 int drift_dir = 1;
13144 int val, period, period1, period2, dif, dif1, dif2;
13145 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13146
13147 DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13148
13149 if (!netif_running(bp->dev)) {
13150 DP(BNX2X_MSG_PTP,
13151 "PTP adjfreq called while the interface is down\n");
13152 return -EFAULT;
13153 }
13154
13155 if (ppb < 0) {
13156 ppb = -ppb;
13157 drift_dir = 0;
13158 }
13159
13160 if (ppb == 0) {
13161 best_val = 1;
13162 best_period = 0x1FFFFFF;
13163 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13164 best_val = 31;
13165 best_period = 1;
13166 } else {
13167 /* Changed not to allow val = 8, 16, 24 as these values
13168 * are not supported in workaround.
13169 */
13170 for (val = 0; val <= 31; val++) {
13171 if ((val & 0x7) == 0)
13172 continue;
13173 period1 = val * 1000000 / ppb;
13174 period2 = period1 + 1;
13175 if (period1 != 0)
13176 dif1 = ppb - (val * 1000000 / period1);
13177 else
13178 dif1 = BNX2X_MAX_PHC_DRIFT;
13179 if (dif1 < 0)
13180 dif1 = -dif1;
13181 dif2 = ppb - (val * 1000000 / period2);
13182 if (dif2 < 0)
13183 dif2 = -dif2;
13184 dif = (dif1 < dif2) ? dif1 : dif2;
13185 period = (dif1 < dif2) ? period1 : period2;
13186 if (dif < best_dif) {
13187 best_dif = dif;
13188 best_val = val;
13189 best_period = period;
13190 }
13191 }
13192 }
13193
13194 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13195 best_period);
13196 if (rc) {
13197 BNX2X_ERR("Failed to set drift\n");
13198 return -EFAULT;
13199 }
13200
13201 DP(BNX2X_MSG_PTP, "Configrued val = %d, period = %d\n", best_val,
13202 best_period);
13203
13204 return 0;
13205}
13206
13207static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13208{
13209 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13210 u64 now;
13211
13212 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13213
13214 now = timecounter_read(&bp->timecounter);
13215 now += delta;
13216 /* Re-init the timecounter */
13217 timecounter_init(&bp->timecounter, &bp->cyclecounter, now);
13218
13219 return 0;
13220}
13221
13222static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
13223{
13224 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13225 u64 ns;
13226 u32 remainder;
13227
13228 ns = timecounter_read(&bp->timecounter);
13229
13230 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13231
13232 ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
13233 ts->tv_nsec = remainder;
13234
13235 return 0;
13236}
13237
13238static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13239 const struct timespec *ts)
13240{
13241 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13242 u64 ns;
13243
13244 ns = ts->tv_sec * 1000000000ULL;
13245 ns += ts->tv_nsec;
13246
13247 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13248
13249 /* Re-init the timecounter */
13250 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13251
13252 return 0;
13253}
13254
13255/* Enable (or disable) ancillary features of the phc subsystem */
13256static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13257 struct ptp_clock_request *rq, int on)
13258{
13259 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13260
13261 BNX2X_ERR("PHC ancillary features are not supported\n");
13262 return -ENOTSUPP;
13263}
13264
13265void bnx2x_register_phc(struct bnx2x *bp)
13266{
13267 /* Fill the ptp_clock_info struct and register PTP clock*/
13268 bp->ptp_clock_info.owner = THIS_MODULE;
13269 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13270 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13271 bp->ptp_clock_info.n_alarm = 0;
13272 bp->ptp_clock_info.n_ext_ts = 0;
13273 bp->ptp_clock_info.n_per_out = 0;
13274 bp->ptp_clock_info.pps = 0;
13275 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13276 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13277 bp->ptp_clock_info.gettime = bnx2x_ptp_gettime;
13278 bp->ptp_clock_info.settime = bnx2x_ptp_settime;
13279 bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13280
13281 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13282 if (IS_ERR(bp->ptp_clock)) {
13283 bp->ptp_clock = NULL;
13284 BNX2X_ERR("PTP clock registeration failed\n");
13285 }
13286}
13287
1ab4434c
AE		 13288static int bnx2x_init_one(struct pci_dev *pdev,
13289 const struct pci_device_id *ent)
13290{
13291 struct net_device *dev = NULL;
13292 struct bnx2x *bp;
b91e1a1a
YM		 13293 enum pcie_link_width pcie_width;
13294 enum pci_bus_speed pcie_speed;
1ab4434c
AE		 13295 int rc, max_non_def_sbs;
13296 int rx_count, tx_count, rss_count, doorbell_size;
13297 int max_cos_est;
13298 bool is_vf;
13299 int cnic_cnt;
13300
13301 /* An estimated maximum supported CoS number according to the chip
13302 * version.
13303 * We will try to roughly estimate the maximum number of CoSes this chip
13304 * may support in order to minimize the memory allocated for Tx
13305 * netdev_queue's. This number will be accurately calculated during the
13306 * initialization of bp->max_cos based on the chip versions AND chip
13307 * revision in the bnx2x_init_bp().
13308 */
13309 max_cos_est = set_max_cos_est(ent->driver_data);
13310 if (max_cos_est < 0)
13311 return max_cos_est;
13312 is_vf = set_is_vf(ent->driver_data);
13313 cnic_cnt = is_vf ? 0 : 1;
13314
60cad4e6
AE		 13315 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13316
13317 /* add another SB for VF as it has no default SB */
13318 max_non_def_sbs += is_vf ? 1 : 0;
6383c0b3
AE		 13319
13320 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
60cad4e6 13321 rss_count = max_non_def_sbs - cnic_cnt;
1ab4434c
AE		 13322
13323 if (rss_count < 1)
13324 return -EINVAL;
6383c0b3
AE		 13325
13326 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
55c11941 13327 rx_count = rss_count + cnic_cnt;
6383c0b3 13328
1ab4434c 13329 /* Maximum number of netdev Tx queues:
37ae41a9 13330 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
6383c0b3 13331 */
55c11941 13332 tx_count = rss_count * max_cos_est + cnic_cnt;
f85582f8 13333
a2fbb9ea 13334 /* dev zeroed in init_etherdev */
6383c0b3 13335 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
41de8d4c 13336 if (!dev)
a2fbb9ea
ET		 13337 return -ENOMEM;
13338
a2fbb9ea 13339 bp = netdev_priv(dev);
a2fbb9ea 13340
1ab4434c
AE		 13341 bp->flags = 0;
13342 if (is_vf)
13343 bp->flags |= IS_VF_FLAG;
13344
6383c0b3 13345 bp->igu_sb_cnt = max_non_def_sbs;
1ab4434c 13346 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
6383c0b3 13347 bp->msg_enable = debug;
55c11941 13348 bp->cnic_support = cnic_cnt;
4bd9b0ff 13349 bp->cnic_probe = bnx2x_cnic_probe;
55c11941 13350
6383c0b3 13351 pci_set_drvdata(pdev, dev);
523224a3 13352
1ab4434c 13353 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
a2fbb9ea
ET		 13354 if (rc < 0) {
13355 free_netdev(dev);
13356 return rc;
13357 }
13358
1ab4434c
AE		 13359 BNX2X_DEV_INFO("This is a %s function\n",
13360 IS_PF(bp) ? "physical" : "virtual");
55c11941 13361 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
1ab4434c 13362 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
60aa0509 13363 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
2de67439 13364 tx_count, rx_count);
60aa0509 13365
34f80b04 13366 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 13367 if (rc)
13368 goto init_one_exit;
13369
1ab4434c
AE		 13370 /* Map doorbells here as we need the real value of bp->max_cos which
13371 * is initialized in bnx2x_init_bp() to determine the number of
13372 * l2 connections.
6383c0b3 13373 */
1ab4434c 13374 if (IS_VF(bp)) {
1d6f3cd8 13375 bp->doorbells = bnx2x_vf_doorbells(bp);
6411280a
AE		 13376 rc = bnx2x_vf_pci_alloc(bp);
13377 if (rc)
13378 goto init_one_exit;
1ab4434c
AE		 13379 } else {
13380 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13381 if (doorbell_size > pci_resource_len(pdev, 2)) {
13382 dev_err(&bp->pdev->dev,
13383 "Cannot map doorbells, bar size too small, aborting\n");
13384 rc = -ENOMEM;
13385 goto init_one_exit;
13386 }
13387 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13388 doorbell_size);
37ae41a9 13389 }
6383c0b3
AE		 13390 if (!bp->doorbells) {
13391 dev_err(&bp->pdev->dev,
13392 "Cannot map doorbell space, aborting\n");
13393 rc = -ENOMEM;
13394 goto init_one_exit;
13395 }
13396
be1f1ffa
AE		 13397 if (IS_VF(bp)) {
13398 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13399 if (rc)
13400 goto init_one_exit;
13401 }
13402
3c76feff
AE		 13403 /* Enable SRIOV if capability found in configuration space */
13404 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
290ca2bb
AE		 13405 if (rc)
13406 goto init_one_exit;
13407
523224a3 13408 /* calc qm_cid_count */
6383c0b3 13409 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
1ab4434c 13410 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
523224a3 13411
55c11941 13412 /* disable FCOE L2 queue for E1x*/
62ac0dc9 13413 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 13414 bp->flags |= NO_FCOE_FLAG;
13415
0e8d2ec5
MS		 13416 /* Set bp->num_queues for MSI-X mode*/
13417 bnx2x_set_num_queues(bp);
13418
25985edc 13419 /* Configure interrupt mode: try to enable MSI-X/MSI if
0e8d2ec5 13420 * needed.
d6214d7a 13421 */
1ab4434c
AE		 13422 rc = bnx2x_set_int_mode(bp);
13423 if (rc) {
13424 dev_err(&pdev->dev, "Cannot set interrupts\n");
13425 goto init_one_exit;
13426 }
04c46736 13427 BNX2X_DEV_INFO("set interrupts successfully\n");
d6214d7a 13428
1ab4434c 13429 /* register the net device */
b340007f
VZ		 13430 rc = register_netdev(dev);
13431 if (rc) {
13432 dev_err(&pdev->dev, "Cannot register net device\n");
13433 goto init_one_exit;
13434 }
1ab4434c 13435 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
b340007f 13436
ec6ba945
VZ		 13437 if (!NO_FCOE(bp)) {
13438 /* Add storage MAC address */
13439 rtnl_lock();
13440 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13441 rtnl_unlock();
13442 }
b91e1a1a
YM		 13443 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13444 pcie_speed == PCI_SPEED_UNKNOWN ||
13445 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13446 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13447 else
13448 BNX2X_DEV_INFO(
13449 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
ca1ee4b2
DK		 13450 board_info[ent->driver_data].name,
13451 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13452 pcie_width,
b91e1a1a
YM		 13453 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13454 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13455 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
ca1ee4b2
DK		 13456 "Unknown",
13457 dev->base_addr, bp->pdev->irq, dev->dev_addr);
c016201c 13458
eeed018c
MK		 13459 bnx2x_register_phc(bp);
13460
a2fbb9ea 13461 return 0;
34f80b04
EG		 13462
13463init_one_exit:
33d8e6a5
YM		 13464 bnx2x_disable_pcie_error_reporting(bp);
13465
34f80b04
EG		 13466 if (bp->regview)
13467 iounmap(bp->regview);
13468
1ab4434c 13469 if (IS_PF(bp) && bp->doorbells)
34f80b04
EG		 13470 iounmap(bp->doorbells);
13471
13472 free_netdev(dev);
13473
13474 if (atomic_read(&pdev->enable_cnt) == 1)
13475 pci_release_regions(pdev);
13476
13477 pci_disable_device(pdev);
34f80b04
EG		 13478
13479 return rc;
a2fbb9ea
ET		 13480}
13481
b030ed2f
YM		 13482static void __bnx2x_remove(struct pci_dev *pdev,
13483 struct net_device *dev,
13484 struct bnx2x *bp,
13485 bool remove_netdev)
a2fbb9ea 13486{
eeed018c
MK		 13487 if (bp->ptp_clock) {
13488 ptp_clock_unregister(bp->ptp_clock);
13489 bp->ptp_clock = NULL;
13490 }
13491
ec6ba945
VZ		 13492 /* Delete storage MAC address */
13493 if (!NO_FCOE(bp)) {
13494 rtnl_lock();
13495 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13496 rtnl_unlock();
13497 }
ec6ba945 13498
98507672
SR		 13499#ifdef BCM_DCBNL
13500 /* Delete app tlvs from dcbnl */
13501 bnx2x_dcbnl_update_applist(bp, true);
13502#endif
13503
a6d3a5ba
BW		 13504 if (IS_PF(bp) &&
13505 !BP_NOMCP(bp) &&
13506 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13507 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13508
b030ed2f
YM		 13509 /* Close the interface - either directly or implicitly */
13510 if (remove_netdev) {
13511 unregister_netdev(dev);
13512 } else {
13513 rtnl_lock();
6ef5a92c 13514 dev_close(dev);
b030ed2f
YM		 13515 rtnl_unlock();
13516 }
a2fbb9ea 13517
78c3bcc5
AE		 13518 bnx2x_iov_remove_one(bp);
13519
084d6cbb 13520 /* Power on: we can't let PCI layer write to us while we are in D3 */
1ab4434c
AE		 13521 if (IS_PF(bp))
13522 bnx2x_set_power_state(bp, PCI_D0);
084d6cbb 13523
d6214d7a
DK		 13524 /* Disable MSI/MSI-X */
13525 bnx2x_disable_msi(bp);
f85582f8 13526
084d6cbb 13527 /* Power off */
1ab4434c
AE		 13528 if (IS_PF(bp))
13529 bnx2x_set_power_state(bp, PCI_D3hot);
084d6cbb 13530
72fd0718 13531 /* Make sure RESET task is not scheduled before continuing */
7be08a72 13532 cancel_delayed_work_sync(&bp->sp_rtnl_task);
290ca2bb 13533
4513f925
AE		 13534 /* send message via vfpf channel to release the resources of this vf */
13535 if (IS_VF(bp))
13536 bnx2x_vfpf_release(bp);
72fd0718 13537
b030ed2f
YM		 13538 /* Assumes no further PCIe PM changes will occur */
13539 if (system_state == SYSTEM_POWER_OFF) {
13540 pci_wake_from_d3(pdev, bp->wol);
13541 pci_set_power_state(pdev, PCI_D3hot);
13542 }
13543
33d8e6a5 13544 bnx2x_disable_pcie_error_reporting(bp);
d9aee591
YM		 13545 if (remove_netdev) {
13546 if (bp->regview)
13547 iounmap(bp->regview);
33d8e6a5 13548
d9aee591
YM		 13549 /* For vfs, doorbells are part of the regview and were unmapped
13550 * along with it. FW is only loaded by PF.
13551 */
13552 if (IS_PF(bp)) {
13553 if (bp->doorbells)
13554 iounmap(bp->doorbells);
eb2afd4a 13555
d9aee591 13556 bnx2x_release_firmware(bp);
e2a367f8
YM		 13557 } else {
13558 bnx2x_vf_pci_dealloc(bp);
d9aee591
YM		 13559 }
13560 bnx2x_free_mem_bp(bp);
523224a3 13561
b030ed2f 13562 free_netdev(dev);
34f80b04 13563
d9aee591
YM		 13564 if (atomic_read(&pdev->enable_cnt) == 1)
13565 pci_release_regions(pdev);
34f80b04 13566
5f6db130
YM		 13567 pci_disable_device(pdev);
13568 }
a2fbb9ea
ET		 13569}
13570
b030ed2f
YM		 13571static void bnx2x_remove_one(struct pci_dev *pdev)
13572{
13573 struct net_device *dev = pci_get_drvdata(pdev);
13574 struct bnx2x *bp;
13575
13576 if (!dev) {
13577 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13578 return;
13579 }
13580 bp = netdev_priv(dev);
13581
13582 __bnx2x_remove(pdev, dev, bp, true);
13583}
13584
f8ef6e44
YG		 13585static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13586{
7fa6f340 13587 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
f8ef6e44
YG		 13588
13589 bp->rx_mode = BNX2X_RX_MODE_NONE;
13590
55c11941
MS		 13591 if (CNIC_LOADED(bp))
13592 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13593
619c5cb6
VZ		 13594 /* Stop Tx */
13595 bnx2x_tx_disable(bp);
26614ba5
MS		 13596 /* Delete all NAPI objects */
13597 bnx2x_del_all_napi(bp);
55c11941
MS		 13598 if (CNIC_LOADED(bp))
13599 bnx2x_del_all_napi_cnic(bp);
7fa6f340 13600 netdev_reset_tc(bp->dev);
f8ef6e44
YG		 13601
13602 del_timer_sync(&bp->timer);
0c0e6341 13603 cancel_delayed_work_sync(&bp->sp_task);
13604 cancel_delayed_work_sync(&bp->period_task);
619c5cb6 13605
7fa6f340
YM		 13606 spin_lock_bh(&bp->stats_lock);
13607 bp->stats_state = STATS_STATE_DISABLED;
13608 spin_unlock_bh(&bp->stats_lock);
f8ef6e44 13609
7fa6f340 13610 bnx2x_save_statistics(bp);
f8ef6e44 13611
619c5cb6
VZ		 13612 netif_carrier_off(bp->dev);
13613
f8ef6e44
YG		 13614 return 0;
13615}
13616
493adb1f
WX		 13617/**
13618 * bnx2x_io_error_detected - called when PCI error is detected
13619 * @pdev: Pointer to PCI device
13620 * @state: The current pci connection state
13621 *
13622 * This function is called after a PCI bus error affecting
13623 * this device has been detected.
13624 */
13625static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13626 pci_channel_state_t state)
13627{
13628 struct net_device *dev = pci_get_drvdata(pdev);
13629 struct bnx2x *bp = netdev_priv(dev);
13630
13631 rtnl_lock();
13632
7fa6f340
YM		 13633 BNX2X_ERR("IO error detected\n");
13634
493adb1f
WX		 13635 netif_device_detach(dev);
13636
07ce50e4
DN		 13637 if (state == pci_channel_io_perm_failure) {
13638 rtnl_unlock();
13639 return PCI_ERS_RESULT_DISCONNECT;
13640 }
13641
493adb1f 13642 if (netif_running(dev))
f8ef6e44 13643 bnx2x_eeh_nic_unload(bp);
493adb1f 13644
7fa6f340
YM		 13645 bnx2x_prev_path_mark_eeh(bp);
13646
493adb1f
WX		 13647 pci_disable_device(pdev);
13648
13649 rtnl_unlock();
13650
13651 /* Request a slot reset */
13652 return PCI_ERS_RESULT_NEED_RESET;
13653}
13654
13655/**
13656 * bnx2x_io_slot_reset - called after the PCI bus has been reset
13657 * @pdev: Pointer to PCI device
13658 *
13659 * Restart the card from scratch, as if from a cold-boot.
13660 */
13661static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13662{
13663 struct net_device *dev = pci_get_drvdata(pdev);
13664 struct bnx2x *bp = netdev_priv(dev);
7fa6f340 13665 int i;
493adb1f
WX		 13666
13667 rtnl_lock();
7fa6f340 13668 BNX2X_ERR("IO slot reset initializing...\n");
493adb1f
WX		 13669 if (pci_enable_device(pdev)) {
13670 dev_err(&pdev->dev,
13671 "Cannot re-enable PCI device after reset\n");
13672 rtnl_unlock();
13673 return PCI_ERS_RESULT_DISCONNECT;
13674 }
13675
13676 pci_set_master(pdev);
13677 pci_restore_state(pdev);
70632d0a 13678 pci_save_state(pdev);
493adb1f
WX		 13679
13680 if (netif_running(dev))
13681 bnx2x_set_power_state(bp, PCI_D0);
13682
7fa6f340
YM		 13683 if (netif_running(dev)) {
13684 BNX2X_ERR("IO slot reset --> driver unload\n");
e68072ef
YM		 13685
13686 /* MCP should have been reset; Need to wait for validity */
13687 bnx2x_init_shmem(bp);
13688
7fa6f340
YM		 13689 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13690 u32 v;
13691
13692 v = SHMEM2_RD(bp,
13693 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13694 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13695 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13696 }
13697 bnx2x_drain_tx_queues(bp);
13698 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13699 bnx2x_netif_stop(bp, 1);
13700 bnx2x_free_irq(bp);
13701
13702 /* Report UNLOAD_DONE to MCP */
13703 bnx2x_send_unload_done(bp, true);
13704
13705 bp->sp_state = 0;
13706 bp->port.pmf = 0;
13707
13708 bnx2x_prev_unload(bp);
13709
16a5fd92 13710 /* We should have reseted the engine, so It's fair to
7fa6f340
YM		 13711 * assume the FW will no longer write to the bnx2x driver.
13712 */
13713 bnx2x_squeeze_objects(bp);
13714 bnx2x_free_skbs(bp);
13715 for_each_rx_queue(bp, i)
13716 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13717 bnx2x_free_fp_mem(bp);
13718 bnx2x_free_mem(bp);
13719
13720 bp->state = BNX2X_STATE_CLOSED;
13721 }
13722
493adb1f
WX		 13723 rtnl_unlock();
13724
33d8e6a5
YM		 13725 /* If AER, perform cleanup of the PCIe registers */
13726 if (bp->flags & AER_ENABLED) {
13727 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13728 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13729 else
13730 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13731 }
13732
493adb1f
WX		 13733 return PCI_ERS_RESULT_RECOVERED;
13734}
13735
13736/**
13737 * bnx2x_io_resume - called when traffic can start flowing again
13738 * @pdev: Pointer to PCI device
13739 *
13740 * This callback is called when the error recovery driver tells us that
13741 * its OK to resume normal operation.
13742 */
13743static void bnx2x_io_resume(struct pci_dev *pdev)
13744{
13745 struct net_device *dev = pci_get_drvdata(pdev);
13746 struct bnx2x *bp = netdev_priv(dev);
13747
72fd0718 13748 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580 13749 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
72fd0718
VZ		 13750 return;
13751 }
13752
493adb1f
WX		 13753 rtnl_lock();
13754
7fa6f340
YM		 13755 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13756 DRV_MSG_SEQ_NUMBER_MASK;
13757
493adb1f 13758 if (netif_running(dev))
f8ef6e44 13759 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 13760
13761 netif_device_attach(dev);
13762
13763 rtnl_unlock();
13764}
13765
3646f0e5 13766static const struct pci_error_handlers bnx2x_err_handler = {
493adb1f 13767 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 13768 .slot_reset = bnx2x_io_slot_reset,
13769 .resume = bnx2x_io_resume,
493adb1f
WX		 13770};
13771
b030ed2f
YM		 13772static void bnx2x_shutdown(struct pci_dev *pdev)
13773{
13774 struct net_device *dev = pci_get_drvdata(pdev);
13775 struct bnx2x *bp;
13776
13777 if (!dev)
13778 return;
13779
13780 bp = netdev_priv(dev);
13781 if (!bp)
13782 return;
13783
13784 rtnl_lock();
13785 netif_device_detach(dev);
13786 rtnl_unlock();
13787
13788 /* Don't remove the netdevice, as there are scenarios which will cause
13789 * the kernel to hang, e.g., when trying to remove bnx2i while the
13790 * rootfs is mounted from SAN.
13791 */
13792 __bnx2x_remove(pdev, dev, bp, false);
13793}
13794
a2fbb9ea 13795static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 13796 .name = DRV_MODULE_NAME,
13797 .id_table = bnx2x_pci_tbl,
13798 .probe = bnx2x_init_one,
0329aba1 13799 .remove = bnx2x_remove_one,
493adb1f
WX		 13800 .suspend = bnx2x_suspend,
13801 .resume = bnx2x_resume,
13802 .err_handler = &bnx2x_err_handler,
3c76feff
AE		 13803#ifdef CONFIG_BNX2X_SRIOV
13804 .sriov_configure = bnx2x_sriov_configure,
13805#endif
b030ed2f 13806 .shutdown = bnx2x_shutdown,
a2fbb9ea
ET		 13807};
13808
13809static int __init bnx2x_init(void)
13810{
dd21ca6d
SG		 13811 int ret;
13812
7995c64e 13813 pr_info("%s", version);
938cf541 13814
1cf167f2
EG		 13815 bnx2x_wq = create_singlethread_workqueue("bnx2x");
13816 if (bnx2x_wq == NULL) {
7995c64e 13817 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 13818 return -ENOMEM;
13819 }
370d4a26
YM		 13820 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
13821 if (!bnx2x_iov_wq) {
13822 pr_err("Cannot create iov workqueue\n");
13823 destroy_workqueue(bnx2x_wq);
13824 return -ENOMEM;
13825 }
1cf167f2 13826
dd21ca6d
SG		 13827 ret = pci_register_driver(&bnx2x_pci_driver);
13828 if (ret) {
7995c64e 13829 pr_err("Cannot register driver\n");
dd21ca6d 13830 destroy_workqueue(bnx2x_wq);
370d4a26 13831 destroy_workqueue(bnx2x_iov_wq);
dd21ca6d
SG		 13832 }
13833 return ret;
a2fbb9ea
ET		 13834}
13835
13836static void __exit bnx2x_cleanup(void)
13837{
452427b0 13838 struct list_head *pos, *q;
d76a6111 13839
a2fbb9ea 13840 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 13841
13842 destroy_workqueue(bnx2x_wq);
370d4a26 13843 destroy_workqueue(bnx2x_iov_wq);
452427b0 13844
16a5fd92 13845 /* Free globally allocated resources */
452427b0
YM		 13846 list_for_each_safe(pos, q, &bnx2x_prev_list) {
13847 struct bnx2x_prev_path_list *tmp =
13848 list_entry(pos, struct bnx2x_prev_path_list, list);
13849 list_del(pos);
13850 kfree(tmp);
13851 }
a2fbb9ea
ET		 13852}
13853
3deb8167
YR		 13854void bnx2x_notify_link_changed(struct bnx2x *bp)
13855{
13856 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13857}
13858
a2fbb9ea
ET		 13859module_init(bnx2x_init);
13860module_exit(bnx2x_cleanup);
13861
619c5cb6
VZ		 13862/**
13863 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13864 *
13865 * @bp: driver handle
13866 * @set: set or clear the CAM entry
13867 *
16a5fd92 13868 * This function will wait until the ramrod completion returns.
619c5cb6
VZ		 13869 * Return 0 if success, -ENODEV if ramrod doesn't return.
13870 */
1191cb83 13871static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
619c5cb6
VZ		 13872{
13873 unsigned long ramrod_flags = 0;
13874
13875 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13876 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13877 &bp->iscsi_l2_mac_obj, true,
13878 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13879}
993ac7b5
MC		 13880
13881/* count denotes the number of new completions we have seen */
13882static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13883{
13884 struct eth_spe *spe;
a052997e 13885 int cxt_index, cxt_offset;
993ac7b5
MC		 13886
13887#ifdef BNX2X_STOP_ON_ERROR
13888 if (unlikely(bp->panic))
13889 return;
13890#endif
13891
13892 spin_lock_bh(&bp->spq_lock);
c2bff63f 13893 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 13894 bp->cnic_spq_pending -= count;
13895
c2bff63f
DK		 13896 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13897 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13898 & SPE_HDR_CONN_TYPE) >>
13899 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 13900 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13901 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 13902
13903 /* Set validation for iSCSI L2 client before sending SETUP
13904 * ramrod
13905 */
13906 if (type == ETH_CONNECTION_TYPE) {
a052997e 13907 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
37ae41a9 13908 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
a052997e 13909 ILT_PAGE_CIDS;
37ae41a9 13910 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
a052997e
MS		 13911 (cxt_index * ILT_PAGE_CIDS);
13912 bnx2x_set_ctx_validation(bp,
13913 &bp->context[cxt_index].
13914 vcxt[cxt_offset].eth,
37ae41a9 13915 BNX2X_ISCSI_ETH_CID(bp));
a052997e 13916 }
c2bff63f
DK		 13917 }
13918
619c5cb6
VZ		 13919 /*
13920 * There may be not more than 8 L2, not more than 8 L5 SPEs
13921 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 13922 * COMMON ramrods is not more than the EQ and SPQ can
13923 * accommodate.
c2bff63f 13924 */
6e30dd4e
VZ		 13925 if (type == ETH_CONNECTION_TYPE) {
13926 if (!atomic_read(&bp->cq_spq_left))
13927 break;
13928 else
13929 atomic_dec(&bp->cq_spq_left);
13930 } else if (type == NONE_CONNECTION_TYPE) {
13931 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 13932 break;
13933 else
6e30dd4e 13934 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 13935 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13936 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 13937 if (bp->cnic_spq_pending >=
13938 bp->cnic_eth_dev.max_kwqe_pending)
13939 break;
13940 else
13941 bp->cnic_spq_pending++;
13942 } else {
13943 BNX2X_ERR("Unknown SPE type: %d\n", type);
13944 bnx2x_panic();
993ac7b5 13945 break;
c2bff63f 13946 }
993ac7b5
MC		 13947
13948 spe = bnx2x_sp_get_next(bp);
13949 *spe = *bp->cnic_kwq_cons;
13950
51c1a580 13951 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
993ac7b5
MC		 13952 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13953
13954 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13955 bp->cnic_kwq_cons = bp->cnic_kwq;
13956 else
13957 bp->cnic_kwq_cons++;
13958 }
13959 bnx2x_sp_prod_update(bp);
13960 spin_unlock_bh(&bp->spq_lock);
13961}
13962
13963static int bnx2x_cnic_sp_queue(struct net_device *dev,
13964 struct kwqe_16 *kwqes[], u32 count)
13965{
13966 struct bnx2x *bp = netdev_priv(dev);
13967 int i;
13968
13969#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 13970 if (unlikely(bp->panic)) {
13971 BNX2X_ERR("Can't post to SP queue while panic\n");
993ac7b5 13972 return -EIO;
51c1a580 13973 }
993ac7b5
MC		 13974#endif
13975
95c6c616
AE		 13976 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13977 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
51c1a580 13978 BNX2X_ERR("Handling parity error recovery. Try again later\n");
95c6c616
AE		 13979 return -EAGAIN;
13980 }
13981
993ac7b5
MC		 13982 spin_lock_bh(&bp->spq_lock);
13983
13984 for (i = 0; i < count; i++) {
13985 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13986
13987 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13988 break;
13989
13990 *bp->cnic_kwq_prod = *spe;
13991
13992 bp->cnic_kwq_pending++;
13993
51c1a580 13994 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
993ac7b5 13995 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 13996 spe->data.update_data_addr.hi,
13997 spe->data.update_data_addr.lo,
993ac7b5
MC		 13998 bp->cnic_kwq_pending);
13999
14000 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14001 bp->cnic_kwq_prod = bp->cnic_kwq;
14002 else
14003 bp->cnic_kwq_prod++;
14004 }
14005
14006 spin_unlock_bh(&bp->spq_lock);
14007
14008 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14009 bnx2x_cnic_sp_post(bp, 0);
14010
14011 return i;
14012}
14013
14014static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14015{
14016 struct cnic_ops *c_ops;
14017 int rc = 0;
14018
14019 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 14020 c_ops = rcu_dereference_protected(bp->cnic_ops,
14021 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 14022 if (c_ops)
14023 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14024 mutex_unlock(&bp->cnic_mutex);
14025
14026 return rc;
14027}
14028
14029static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14030{
14031 struct cnic_ops *c_ops;
14032 int rc = 0;
14033
14034 rcu_read_lock();
14035 c_ops = rcu_dereference(bp->cnic_ops);
14036 if (c_ops)
14037 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14038 rcu_read_unlock();
14039
14040 return rc;
14041}
14042
14043/*
14044 * for commands that have no data
14045 */
9f6c9258 14046int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 14047{
14048 struct cnic_ctl_info ctl = {0};
14049
14050 ctl.cmd = cmd;
14051
14052 return bnx2x_cnic_ctl_send(bp, &ctl);
14053}
14054
619c5cb6 14055static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 14056{
619c5cb6 14057 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 14058
14059 /* first we tell CNIC and only then we count this as a completion */
14060 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14061 ctl.data.comp.cid = cid;
619c5cb6 14062 ctl.data.comp.error = err;
993ac7b5
MC		 14063
14064 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 14065 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 14066}
14067
619c5cb6
VZ		 14068/* Called with netif_addr_lock_bh() taken.
14069 * Sets an rx_mode config for an iSCSI ETH client.
14070 * Doesn't block.
14071 * Completion should be checked outside.
14072 */
14073static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14074{
14075 unsigned long accept_flags = 0, ramrod_flags = 0;
14076 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14077 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14078
14079 if (start) {
14080 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14081 * because it's the only way for UIO Queue to accept
14082 * multicasts (in non-promiscuous mode only one Queue per
14083 * function will receive multicast packets (leading in our
14084 * case).
14085 */
14086 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14087 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14088 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14089 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14090
14091 /* Clear STOP_PENDING bit if START is requested */
14092 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14093
14094 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14095 } else
14096 /* Clear START_PENDING bit if STOP is requested */
14097 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14098
14099 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14100 set_bit(sched_state, &bp->sp_state);
14101 else {
14102 __set_bit(RAMROD_RX, &ramrod_flags);
14103 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14104 ramrod_flags);
14105 }
14106}
14107
993ac7b5
MC		 14108static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14109{
14110 struct bnx2x *bp = netdev_priv(dev);
14111 int rc = 0;
14112
14113 switch (ctl->cmd) {
14114 case DRV_CTL_CTXTBL_WR_CMD: {
14115 u32 index = ctl->data.io.offset;
14116 dma_addr_t addr = ctl->data.io.dma_addr;
14117
14118 bnx2x_ilt_wr(bp, index, addr);
14119 break;
14120 }
14121
c2bff63f
DK		 14122 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14123 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 14124
14125 bnx2x_cnic_sp_post(bp, count);
14126 break;
14127 }
14128
14129 /* rtnl_lock is held. */
14130 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 14131 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14132 unsigned long sp_bits = 0;
14133
14134 /* Configure the iSCSI classification object */
14135 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14136 cp->iscsi_l2_client_id,
14137 cp->iscsi_l2_cid, BP_FUNC(bp),
14138 bnx2x_sp(bp, mac_rdata),
14139 bnx2x_sp_mapping(bp, mac_rdata),
14140 BNX2X_FILTER_MAC_PENDING,
14141 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14142 &bp->macs_pool);
ec6ba945 14143
523224a3 14144 /* Set iSCSI MAC address */
619c5cb6
VZ		 14145 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14146 if (rc)
14147 break;
523224a3
DK		 14148
14149 mmiowb();
14150 barrier();
14151
619c5cb6
VZ		 14152 /* Start accepting on iSCSI L2 ring */
14153
14154 netif_addr_lock_bh(dev);
14155 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14156 netif_addr_unlock_bh(dev);
14157
14158 /* bits to wait on */
14159 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14160 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14161
14162 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14163 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 14164
993ac7b5
MC		 14165 break;
14166 }
14167
14168 /* rtnl_lock is held. */
14169 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 14170 unsigned long sp_bits = 0;
993ac7b5 14171
523224a3 14172 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 14173 netif_addr_lock_bh(dev);
14174 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14175 netif_addr_unlock_bh(dev);
14176
14177 /* bits to wait on */
14178 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14179 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14180
14181 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14182 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 14183
14184 mmiowb();
14185 barrier();
14186
14187 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 14188 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14189 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 14190 break;
14191 }
c2bff63f
DK		 14192 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14193 int count = ctl->data.credit.credit_count;
14194
4e857c58 14195 smp_mb__before_atomic();
6e30dd4e 14196 atomic_add(count, &bp->cq_spq_left);
4e857c58 14197 smp_mb__after_atomic();
c2bff63f
DK		 14198 break;
14199 }
1d187b34 14200 case DRV_CTL_ULP_REGISTER_CMD: {
2e499d3c 14201 int ulp_type = ctl->data.register_data.ulp_type;
1d187b34
BW		 14202
14203 if (CHIP_IS_E3(bp)) {
14204 int idx = BP_FW_MB_IDX(bp);
2e499d3c
BW		 14205 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14206 int path = BP_PATH(bp);
14207 int port = BP_PORT(bp);
14208 int i;
14209 u32 scratch_offset;
14210 u32 *host_addr;
1d187b34 14211
2e499d3c 14212 /* first write capability to shmem2 */
1d187b34
BW		 14213 if (ulp_type == CNIC_ULP_ISCSI)
14214 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14215 else if (ulp_type == CNIC_ULP_FCOE)
14216 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14217 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
2e499d3c
BW		 14218
14219 if ((ulp_type != CNIC_ULP_FCOE) ||
14220 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14221 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
14222 break;
14223
14224 /* if reached here - should write fcoe capabilities */
14225 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14226 if (!scratch_offset)
14227 break;
14228 scratch_offset += offsetof(struct glob_ncsi_oem_data,
14229 fcoe_features[path][port]);
14230 host_addr = (u32 *) &(ctl->data.register_data.
14231 fcoe_features);
14232 for (i = 0; i < sizeof(struct fcoe_capabilities);
14233 i += 4)
14234 REG_WR(bp, scratch_offset + i,
14235 *(host_addr + i/4));
1d187b34 14236 }
42f8277f 14237 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 14238 break;
14239 }
2e499d3c 14240
1d187b34
BW		 14241 case DRV_CTL_ULP_UNREGISTER_CMD: {
14242 int ulp_type = ctl->data.ulp_type;
14243
14244 if (CHIP_IS_E3(bp)) {
14245 int idx = BP_FW_MB_IDX(bp);
14246 u32 cap;
14247
14248 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14249 if (ulp_type == CNIC_ULP_ISCSI)
14250 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14251 else if (ulp_type == CNIC_ULP_FCOE)
14252 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14253 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14254 }
42f8277f 14255 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 14256 break;
14257 }
993ac7b5
MC		 14258
14259 default:
14260 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14261 rc = -EINVAL;
14262 }
14263
14264 return rc;
14265}
14266
9f6c9258 14267void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 14268{
14269 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14270
14271 if (bp->flags & USING_MSIX_FLAG) {
14272 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14273 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14274 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14275 } else {
14276 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14277 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14278 }
619c5cb6 14279 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 14280 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14281 else
14282 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14283
619c5cb6
VZ		 14284 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
14285 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 14286 cp->irq_arr[1].status_blk = bp->def_status_blk;
14287 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 14288 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 14289
14290 cp->num_irq = 2;
14291}
14292
37ae41a9
MS		 14293void bnx2x_setup_cnic_info(struct bnx2x *bp)
14294{
14295 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14296
37ae41a9
MS		 14297 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14298 bnx2x_cid_ilt_lines(bp);
14299 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14300 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14301 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14302
f78afb35
MC		 14303 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14304 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14305 cp->iscsi_l2_cid);
14306
37ae41a9
MS		 14307 if (NO_ISCSI_OOO(bp))
14308 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14309}
14310
993ac7b5
MC		 14311static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14312 void *data)
14313{
14314 struct bnx2x *bp = netdev_priv(dev);
14315 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
55c11941
MS		 14316 int rc;
14317
14318 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
993ac7b5 14319
51c1a580
MS		 14320 if (ops == NULL) {
14321 BNX2X_ERR("NULL ops received\n");
993ac7b5 14322 return -EINVAL;
51c1a580 14323 }
993ac7b5 14324
55c11941
MS		 14325 if (!CNIC_SUPPORT(bp)) {
14326 BNX2X_ERR("Can't register CNIC when not supported\n");
14327 return -EOPNOTSUPP;
14328 }
14329
14330 if (!CNIC_LOADED(bp)) {
14331 rc = bnx2x_load_cnic(bp);
14332 if (rc) {
14333 BNX2X_ERR("CNIC-related load failed\n");
14334 return rc;
14335 }
55c11941
MS		 14336 }
14337
14338 bp->cnic_enabled = true;
14339
993ac7b5
MC		 14340 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14341 if (!bp->cnic_kwq)
14342 return -ENOMEM;
14343
14344 bp->cnic_kwq_cons = bp->cnic_kwq;
14345 bp->cnic_kwq_prod = bp->cnic_kwq;
14346 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14347
14348 bp->cnic_spq_pending = 0;
14349 bp->cnic_kwq_pending = 0;
14350
14351 bp->cnic_data = data;
14352
14353 cp->num_irq = 0;
619c5cb6 14354 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 14355 cp->iro_arr = bp->iro_arr;
993ac7b5 14356
993ac7b5 14357 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 14358
993ac7b5
MC		 14359 rcu_assign_pointer(bp->cnic_ops, ops);
14360
42f8277f
YM		 14361 /* Schedule driver to read CNIC driver versions */
14362 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14363
993ac7b5
MC		 14364 return 0;
14365}
14366
14367static int bnx2x_unregister_cnic(struct net_device *dev)
14368{
14369 struct bnx2x *bp = netdev_priv(dev);
14370 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14371
14372 mutex_lock(&bp->cnic_mutex);
993ac7b5 14373 cp->drv_state = 0;
2cfa5a04 14374 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 14375 mutex_unlock(&bp->cnic_mutex);
14376 synchronize_rcu();
fea75645 14377 bp->cnic_enabled = false;
993ac7b5
MC		 14378 kfree(bp->cnic_kwq);
14379 bp->cnic_kwq = NULL;
14380
14381 return 0;
14382}
14383
a8f47eb7 14384static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
993ac7b5
MC		 14385{
14386 struct bnx2x *bp = netdev_priv(dev);
14387 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14388
2ba45142
VZ		 14389 /* If both iSCSI and FCoE are disabled - return NULL in
14390 * order to indicate CNIC that it should not try to work
14391 * with this device.
14392 */
14393 if (NO_ISCSI(bp) && NO_FCOE(bp))
14394 return NULL;
14395
993ac7b5
MC		 14396 cp->drv_owner = THIS_MODULE;
14397 cp->chip_id = CHIP_ID(bp);
14398 cp->pdev = bp->pdev;
14399 cp->io_base = bp->regview;
14400 cp->io_base2 = bp->doorbells;
14401 cp->max_kwqe_pending = 8;
523224a3 14402 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 14403 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14404 bnx2x_cid_ilt_lines(bp);
993ac7b5 14405 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 14406 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 14407 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14408 cp->drv_ctl = bnx2x_drv_ctl;
14409 cp->drv_register_cnic = bnx2x_register_cnic;
14410 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
37ae41a9 14411 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
619c5cb6
VZ		 14412 cp->iscsi_l2_client_id =
14413 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
37ae41a9 14414 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
c2bff63f 14415
2ba45142
VZ		 14416 if (NO_ISCSI_OOO(bp))
14417 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14418
14419 if (NO_ISCSI(bp))
14420 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14421
14422 if (NO_FCOE(bp))
14423 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14424
51c1a580
MS		 14425 BNX2X_DEV_INFO(
14426 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
c2bff63f
DK		 14427 cp->ctx_blk_size,
14428 cp->ctx_tbl_offset,
14429 cp->ctx_tbl_len,
14430 cp->starting_cid);
993ac7b5
MC		 14431 return cp;
14432}
993ac7b5 14433
a8f47eb7 14434static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
9b176b6b 14435{
6411280a
AE		 14436 struct bnx2x *bp = fp->bp;
14437 u32 offset = BAR_USTRORM_INTMEM;
abc5a021 14438
6411280a
AE		 14439 if (IS_VF(bp))
14440 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14441 else if (!CHIP_IS_E1x(bp))
14442 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14443 else
14444 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
8d9ac297 14445
6411280a 14446 return offset;
8d9ac297 14447}
381ac16b 14448
6411280a
AE		 14449/* called only on E1H or E2.
14450 * When pretending to be PF, the pretend value is the function number 0...7
14451 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14452 * combination
14453 */
14454int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
381ac16b 14455{
6411280a 14456 u32 pretend_reg;
381ac16b 14457
23826850 14458 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
6411280a 14459 return -1;
381ac16b 14460
6411280a
AE		 14461 /* get my own pretend register */
14462 pretend_reg = bnx2x_get_pretend_reg(bp);
14463 REG_WR(bp, pretend_reg, pretend_func_val);
14464 REG_RD(bp, pretend_reg);
381ac16b
AE		 14465 return 0;
14466}
eeed018c
MK		 14467
14468static void bnx2x_ptp_task(struct work_struct *work)
14469{
14470 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
14471 int port = BP_PORT(bp);
14472 u32 val_seq;
14473 u64 timestamp, ns;
14474 struct skb_shared_hwtstamps shhwtstamps;
14475
14476 /* Read Tx timestamp registers */
14477 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14478 NIG_REG_P0_TLLH_PTP_BUF_SEQID);
14479 if (val_seq & 0x10000) {
14480 /* There is a valid timestamp value */
14481 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
14482 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
14483 timestamp <<= 32;
14484 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
14485 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
14486 /* Reset timestamp register to allow new timestamp */
14487 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14488 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14489 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14490
14491 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
14492 shhwtstamps.hwtstamp = ns_to_ktime(ns);
14493 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
14494 dev_kfree_skb_any(bp->ptp_tx_skb);
14495 bp->ptp_tx_skb = NULL;
14496
14497 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
14498 timestamp, ns);
14499 } else {
14500 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
14501 /* Reschedule to keep checking for a valid timestamp value */
14502 schedule_work(&bp->ptp_task);
14503 }
14504}
14505
14506void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
14507{
14508 int port = BP_PORT(bp);
14509 u64 timestamp, ns;
14510
14511 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
14512 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
14513 timestamp <<= 32;
14514 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
14515 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
14516
14517 /* Reset timestamp register to allow new timestamp */
14518 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14519 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14520
14521 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14522
14523 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
14524
14525 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
14526 timestamp, ns);
14527}
14528
14529/* Read the PHC */
14530static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
14531{
14532 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
14533 int port = BP_PORT(bp);
14534 u32 wb_data[2];
14535 u64 phc_cycles;
14536
14537 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
14538 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
14539 phc_cycles = wb_data[1];
14540 phc_cycles = (phc_cycles << 32) + wb_data[0];
14541
14542 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
14543
14544 return phc_cycles;
14545}
14546
14547static void bnx2x_init_cyclecounter(struct bnx2x *bp)
14548{
14549 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
14550 bp->cyclecounter.read = bnx2x_cyclecounter_read;
14551 bp->cyclecounter.mask = CLOCKSOURCE_MASK(64);
14552 bp->cyclecounter.shift = 1;
14553 bp->cyclecounter.mult = 1;
14554}
14555
14556static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
14557{
14558 struct bnx2x_func_state_params func_params = {NULL};
14559 struct bnx2x_func_set_timesync_params *set_timesync_params =
14560 &func_params.params.set_timesync;
14561
14562 /* Prepare parameters for function state transitions */
14563 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
14564 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
14565
14566 func_params.f_obj = &bp->func_obj;
14567 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
14568
14569 /* Function parameters */
14570 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
14571 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
14572
14573 return bnx2x_func_state_change(bp, &func_params);
14574}
14575
14576int bnx2x_enable_ptp_packets(struct bnx2x *bp)
14577{
14578 struct bnx2x_queue_state_params q_params;
14579 int rc, i;
14580
14581 /* send queue update ramrod to enable PTP packets */
14582 memset(&q_params, 0, sizeof(q_params));
14583 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
14584 q_params.cmd = BNX2X_Q_CMD_UPDATE;
14585 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
14586 &q_params.params.update.update_flags);
14587 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
14588 &q_params.params.update.update_flags);
14589
14590 /* send the ramrod on all the queues of the PF */
14591 for_each_eth_queue(bp, i) {
14592 struct bnx2x_fastpath *fp = &bp->fp[i];
14593
14594 /* Set the appropriate Queue object */
14595 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
14596
14597 /* Update the Queue state */
14598 rc = bnx2x_queue_state_change(bp, &q_params);
14599 if (rc) {
14600 BNX2X_ERR("Failed to enable PTP packets\n");
14601 return rc;
14602 }
14603 }
14604
14605 return 0;
14606}
14607
14608int bnx2x_configure_ptp_filters(struct bnx2x *bp)
14609{
14610 int port = BP_PORT(bp);
14611 int rc;
14612
14613 if (!bp->hwtstamp_ioctl_called)
14614 return 0;
14615
14616 switch (bp->tx_type) {
14617 case HWTSTAMP_TX_ON:
14618 bp->flags |= TX_TIMESTAMPING_EN;
14619 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14620 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
14621 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14622 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
14623 break;
14624 case HWTSTAMP_TX_ONESTEP_SYNC:
14625 BNX2X_ERR("One-step timestamping is not supported\n");
14626 return -ERANGE;
14627 }
14628
14629 switch (bp->rx_filter) {
14630 case HWTSTAMP_FILTER_NONE:
14631 break;
14632 case HWTSTAMP_FILTER_ALL:
14633 case HWTSTAMP_FILTER_SOME:
14634 bp->rx_filter = HWTSTAMP_FILTER_NONE;
14635 break;
14636 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
14637 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
14638 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
14639 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
14640 /* Initialize PTP detection for UDP/IPv4 events */
14641 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14642 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
14643 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14644 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
14645 break;
14646 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
14647 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
14648 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
14649 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
14650 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
14651 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14652 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
14653 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14654 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
14655 break;
14656 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
14657 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
14658 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
14659 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
14660 /* Initialize PTP detection L2 events */
14661 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14662 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
14663 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14664 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
14665
14666 break;
14667 case HWTSTAMP_FILTER_PTP_V2_EVENT:
14668 case HWTSTAMP_FILTER_PTP_V2_SYNC:
14669 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
14670 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
14671 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
14672 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14673 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
14674 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14675 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
14676 break;
14677 }
14678
14679 /* Indicate to FW that this PF expects recorded PTP packets */
14680 rc = bnx2x_enable_ptp_packets(bp);
14681 if (rc)
14682 return rc;
14683
14684 /* Enable sending PTP packets to host */
14685 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14686 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
14687
14688 return 0;
14689}
14690
14691static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
14692{
14693 struct hwtstamp_config config;
14694 int rc;
14695
14696 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
14697
14698 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
14699 return -EFAULT;
14700
14701 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
14702 config.tx_type, config.rx_filter);
14703
14704 if (config.flags) {
14705 BNX2X_ERR("config.flags is reserved for future use\n");
14706 return -EINVAL;
14707 }
14708
14709 bp->hwtstamp_ioctl_called = 1;
14710 bp->tx_type = config.tx_type;
14711 bp->rx_filter = config.rx_filter;
14712
14713 rc = bnx2x_configure_ptp_filters(bp);
14714 if (rc)
14715 return rc;
14716
14717 config.rx_filter = bp->rx_filter;
14718
14719 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
14720 -EFAULT : 0;
14721}
14722
14723/* Configrues HW for PTP */
14724static int bnx2x_configure_ptp(struct bnx2x *bp)
14725{
14726 int rc, port = BP_PORT(bp);
14727 u32 wb_data[2];
14728
14729 /* Reset PTP event detection rules - will be configured in the IOCTL */
14730 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14731 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
14732 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14733 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
14734 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14735 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
14736 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14737 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
14738
14739 /* Disable PTP packets to host - will be configured in the IOCTL*/
14740 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14741 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
14742
14743 /* Enable the PTP feature */
14744 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
14745 NIG_REG_P0_PTP_EN, 0x3F);
14746
14747 /* Enable the free-running counter */
14748 wb_data[0] = 0;
14749 wb_data[1] = 0;
14750 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
14751
14752 /* Reset drift register (offset register is not reset) */
14753 rc = bnx2x_send_reset_timesync_ramrod(bp);
14754 if (rc) {
14755 BNX2X_ERR("Failed to reset PHC drift register\n");
14756 return -EFAULT;
14757 }
14758
14759 /* Reset possibly old timestamps */
14760 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14761 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14762 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14763 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14764
14765 return 0;
14766}
14767
14768/* Called during load, to initialize PTP-related stuff */
14769void bnx2x_init_ptp(struct bnx2x *bp)
14770{
14771 int rc;
14772
14773 /* Configure PTP in HW */
14774 rc = bnx2x_configure_ptp(bp);
14775 if (rc) {
14776 BNX2X_ERR("Stopping PTP initialization\n");
14777 return;
14778 }
14779
14780 /* Init work queue for Tx timestamping */
14781 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
14782
14783 /* Init cyclecounter and timecounter. This is done only in the first
14784 * load. If done in every load, PTP application will fail when doing
14785 * unload / load (e.g. MTU change) while it is running.
14786 */
14787 if (!bp->timecounter_init_done) {
14788 bnx2x_init_cyclecounter(bp);
14789 timecounter_init(&bp->timecounter, &bp->cyclecounter,
14790 ktime_to_ns(ktime_get_real()));
14791 bp->timecounter_init_done = 1;
14792 }
14793
14794 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
14795}
Linux kernel - Deliverables
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