Commit | Line | Data |
---|---|---|
34f80b04 | 1 | /* bnx2x_main.c: Broadcom Everest network driver. |
a2fbb9ea | 2 | * |
85b26ea1 | 3 | * Copyright (c) 2007-2012 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
ca00392c | 13 | * Slowpath and fastpath rework by Vladislav Zolotarov |
c14423fe | 14 | * Statistics and Link management by Yitchak Gertner |
a2fbb9ea ET |
15 | * |
16 | */ | |
17 | ||
f1deab50 JP |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
19 | ||
a2fbb9ea ET |
20 | #include <linux/module.h> |
21 | #include <linux/moduleparam.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/device.h> /* for dev_info() */ | |
24 | #include <linux/timer.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/slab.h> | |
a2fbb9ea ET |
28 | #include <linux/interrupt.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/bitops.h> | |
36 | #include <linux/irq.h> | |
37 | #include <linux/delay.h> | |
38 | #include <asm/byteorder.h> | |
39 | #include <linux/time.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/mii.h> | |
0c6671b0 | 42 | #include <linux/if_vlan.h> |
a2fbb9ea | 43 | #include <net/ip.h> |
619c5cb6 | 44 | #include <net/ipv6.h> |
a2fbb9ea ET |
45 | #include <net/tcp.h> |
46 | #include <net/checksum.h> | |
34f80b04 | 47 | #include <net/ip6_checksum.h> |
a2fbb9ea ET |
48 | #include <linux/workqueue.h> |
49 | #include <linux/crc32.h> | |
34f80b04 | 50 | #include <linux/crc32c.h> |
a2fbb9ea ET |
51 | #include <linux/prefetch.h> |
52 | #include <linux/zlib.h> | |
a2fbb9ea | 53 | #include <linux/io.h> |
452427b0 | 54 | #include <linux/semaphore.h> |
45229b42 | 55 | #include <linux/stringify.h> |
7ab24bfd | 56 | #include <linux/vmalloc.h> |
a2fbb9ea | 57 | |
a2fbb9ea ET |
58 | #include "bnx2x.h" |
59 | #include "bnx2x_init.h" | |
94a78b79 | 60 | #include "bnx2x_init_ops.h" |
9f6c9258 | 61 | #include "bnx2x_cmn.h" |
e4901dde | 62 | #include "bnx2x_dcb.h" |
042181f5 | 63 | #include "bnx2x_sp.h" |
a2fbb9ea | 64 | |
94a78b79 VZ |
65 | #include <linux/firmware.h> |
66 | #include "bnx2x_fw_file_hdr.h" | |
67 | /* FW files */ | |
45229b42 BH |
68 | #define FW_FILE_VERSION \ |
69 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ | |
70 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ | |
71 | __stringify(BCM_5710_FW_REVISION_VERSION) "." \ | |
72 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) | |
560131f3 DK |
73 | #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" |
74 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" | |
f2e0899f | 75 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
94a78b79 | 76 | |
34f80b04 EG |
77 | /* Time in jiffies before concluding the transmitter is hung */ |
78 | #define TX_TIMEOUT (5*HZ) | |
a2fbb9ea | 79 | |
53a10565 | 80 | static char version[] __devinitdata = |
619c5cb6 | 81 | "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " |
a2fbb9ea ET |
82 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
83 | ||
24e3fcef | 84 | MODULE_AUTHOR("Eliezer Tamir"); |
f2e0899f | 85 | MODULE_DESCRIPTION("Broadcom NetXtreme II " |
619c5cb6 VZ |
86 | "BCM57710/57711/57711E/" |
87 | "57712/57712_MF/57800/57800_MF/57810/57810_MF/" | |
88 | "57840/57840_MF Driver"); | |
a2fbb9ea ET |
89 | MODULE_LICENSE("GPL"); |
90 | MODULE_VERSION(DRV_MODULE_VERSION); | |
45229b42 BH |
91 | MODULE_FIRMWARE(FW_FILE_NAME_E1); |
92 | MODULE_FIRMWARE(FW_FILE_NAME_E1H); | |
f2e0899f | 93 | MODULE_FIRMWARE(FW_FILE_NAME_E2); |
a2fbb9ea | 94 | |
555f6c78 EG |
95 | static int multi_mode = 1; |
96 | module_param(multi_mode, int, 0); | |
ca00392c EG |
97 | MODULE_PARM_DESC(multi_mode, " Multi queue mode " |
98 | "(0 Disable; 1 Enable (default))"); | |
99 | ||
d6214d7a | 100 | int num_queues; |
54b9ddaa VZ |
101 | module_param(num_queues, int, 0); |
102 | MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" | |
103 | " (default is as a number of CPUs)"); | |
555f6c78 | 104 | |
19680c48 | 105 | static int disable_tpa; |
19680c48 | 106 | module_param(disable_tpa, int, 0); |
9898f86d | 107 | MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); |
8badd27a | 108 | |
9ee3d37b DK |
109 | #define INT_MODE_INTx 1 |
110 | #define INT_MODE_MSI 2 | |
8badd27a EG |
111 | static int int_mode; |
112 | module_param(int_mode, int, 0); | |
619c5cb6 | 113 | MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " |
cdaa7cb8 | 114 | "(1 INT#x; 2 MSI)"); |
8badd27a | 115 | |
a18f5128 EG |
116 | static int dropless_fc; |
117 | module_param(dropless_fc, int, 0); | |
118 | MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); | |
119 | ||
8d5726c4 EG |
120 | static int mrrs = -1; |
121 | module_param(mrrs, int, 0); | |
122 | MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); | |
123 | ||
9898f86d | 124 | static int debug; |
a2fbb9ea | 125 | module_param(debug, int, 0); |
9898f86d EG |
126 | MODULE_PARM_DESC(debug, " Default debug msglevel"); |
127 | ||
a2fbb9ea | 128 | |
619c5cb6 VZ |
129 | |
130 | struct workqueue_struct *bnx2x_wq; | |
ec6ba945 | 131 | |
a2fbb9ea ET |
132 | enum bnx2x_board_type { |
133 | BCM57710 = 0, | |
619c5cb6 VZ |
134 | BCM57711, |
135 | BCM57711E, | |
136 | BCM57712, | |
137 | BCM57712_MF, | |
138 | BCM57800, | |
139 | BCM57800_MF, | |
140 | BCM57810, | |
141 | BCM57810_MF, | |
142 | BCM57840, | |
7e8e02df BW |
143 | BCM57840_MF, |
144 | BCM57811, | |
145 | BCM57811_MF | |
a2fbb9ea ET |
146 | }; |
147 | ||
34f80b04 | 148 | /* indexed by board_type, above */ |
53a10565 | 149 | static struct { |
a2fbb9ea ET |
150 | char *name; |
151 | } board_info[] __devinitdata = { | |
619c5cb6 VZ |
152 | { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, |
153 | { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, | |
154 | { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, | |
155 | { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, | |
156 | { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, | |
157 | { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, | |
158 | { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, | |
159 | { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, | |
160 | { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, | |
161 | { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, | |
7e8e02df BW |
162 | { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"}, |
163 | { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet"}, | |
164 | { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function"}, | |
a2fbb9ea ET |
165 | }; |
166 | ||
619c5cb6 VZ |
167 | #ifndef PCI_DEVICE_ID_NX2_57710 |
168 | #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 | |
169 | #endif | |
170 | #ifndef PCI_DEVICE_ID_NX2_57711 | |
171 | #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 | |
172 | #endif | |
173 | #ifndef PCI_DEVICE_ID_NX2_57711E | |
174 | #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E | |
175 | #endif | |
176 | #ifndef PCI_DEVICE_ID_NX2_57712 | |
177 | #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 | |
178 | #endif | |
179 | #ifndef PCI_DEVICE_ID_NX2_57712_MF | |
180 | #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF | |
181 | #endif | |
182 | #ifndef PCI_DEVICE_ID_NX2_57800 | |
183 | #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 | |
184 | #endif | |
185 | #ifndef PCI_DEVICE_ID_NX2_57800_MF | |
186 | #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF | |
187 | #endif | |
188 | #ifndef PCI_DEVICE_ID_NX2_57810 | |
189 | #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 | |
190 | #endif | |
191 | #ifndef PCI_DEVICE_ID_NX2_57810_MF | |
192 | #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF | |
193 | #endif | |
194 | #ifndef PCI_DEVICE_ID_NX2_57840 | |
195 | #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 | |
196 | #endif | |
197 | #ifndef PCI_DEVICE_ID_NX2_57840_MF | |
198 | #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF | |
199 | #endif | |
7e8e02df BW |
200 | #ifndef PCI_DEVICE_ID_NX2_57811 |
201 | #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 | |
202 | #endif | |
203 | #ifndef PCI_DEVICE_ID_NX2_57811_MF | |
204 | #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF | |
205 | #endif | |
a3aa1884 | 206 | static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { |
e4ed7113 EG |
207 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, |
208 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, | |
209 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, | |
f2e0899f | 210 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, |
619c5cb6 VZ |
211 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, |
212 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, | |
213 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, | |
214 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, | |
215 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, | |
216 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, | |
217 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, | |
7e8e02df BW |
218 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, |
219 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, | |
a2fbb9ea ET |
220 | { 0 } |
221 | }; | |
222 | ||
223 | MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); | |
224 | ||
452427b0 YM |
225 | /* Global resources for unloading a previously loaded device */ |
226 | #define BNX2X_PREV_WAIT_NEEDED 1 | |
227 | static DEFINE_SEMAPHORE(bnx2x_prev_sem); | |
228 | static LIST_HEAD(bnx2x_prev_list); | |
a2fbb9ea ET |
229 | /**************************************************************************** |
230 | * General service functions | |
231 | ****************************************************************************/ | |
232 | ||
619c5cb6 VZ |
233 | static inline void __storm_memset_dma_mapping(struct bnx2x *bp, |
234 | u32 addr, dma_addr_t mapping) | |
235 | { | |
236 | REG_WR(bp, addr, U64_LO(mapping)); | |
237 | REG_WR(bp, addr + 4, U64_HI(mapping)); | |
238 | } | |
239 | ||
240 | static inline void storm_memset_spq_addr(struct bnx2x *bp, | |
241 | dma_addr_t mapping, u16 abs_fid) | |
242 | { | |
243 | u32 addr = XSEM_REG_FAST_MEMORY + | |
244 | XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); | |
245 | ||
246 | __storm_memset_dma_mapping(bp, addr, mapping); | |
247 | } | |
248 | ||
249 | static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, | |
250 | u16 pf_id) | |
523224a3 | 251 | { |
619c5cb6 VZ |
252 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), |
253 | pf_id); | |
254 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), | |
255 | pf_id); | |
256 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), | |
257 | pf_id); | |
258 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), | |
259 | pf_id); | |
523224a3 DK |
260 | } |
261 | ||
619c5cb6 VZ |
262 | static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, |
263 | u8 enable) | |
264 | { | |
265 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), | |
266 | enable); | |
267 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), | |
268 | enable); | |
269 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), | |
270 | enable); | |
271 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), | |
272 | enable); | |
273 | } | |
523224a3 DK |
274 | |
275 | static inline void storm_memset_eq_data(struct bnx2x *bp, | |
276 | struct event_ring_data *eq_data, | |
277 | u16 pfid) | |
278 | { | |
279 | size_t size = sizeof(struct event_ring_data); | |
280 | ||
281 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); | |
282 | ||
283 | __storm_memset_struct(bp, addr, size, (u32 *)eq_data); | |
284 | } | |
285 | ||
286 | static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, | |
287 | u16 pfid) | |
288 | { | |
289 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); | |
290 | REG_WR16(bp, addr, eq_prod); | |
291 | } | |
292 | ||
a2fbb9ea ET |
293 | /* used only at init |
294 | * locking is done by mcp | |
295 | */ | |
8d96286a | 296 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) |
a2fbb9ea ET |
297 | { |
298 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
299 | pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); | |
300 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
301 | PCICFG_VENDOR_ID_OFFSET); | |
302 | } | |
303 | ||
a2fbb9ea ET |
304 | static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) |
305 | { | |
306 | u32 val; | |
307 | ||
308 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
309 | pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); | |
310 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
311 | PCICFG_VENDOR_ID_OFFSET); | |
312 | ||
313 | return val; | |
314 | } | |
a2fbb9ea | 315 | |
f2e0899f DK |
316 | #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" |
317 | #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" | |
318 | #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" | |
319 | #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" | |
320 | #define DMAE_DP_DST_NONE "dst_addr [none]" | |
321 | ||
f2e0899f | 322 | |
a2fbb9ea | 323 | /* copy command into DMAE command memory and set DMAE command go */ |
6c719d00 | 324 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) |
a2fbb9ea ET |
325 | { |
326 | u32 cmd_offset; | |
327 | int i; | |
328 | ||
329 | cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); | |
330 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { | |
331 | REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
a2fbb9ea ET |
332 | } |
333 | REG_WR(bp, dmae_reg_go_c[idx], 1); | |
334 | } | |
335 | ||
f2e0899f | 336 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) |
a2fbb9ea | 337 | { |
f2e0899f DK |
338 | return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | |
339 | DMAE_CMD_C_ENABLE); | |
340 | } | |
ad8d3948 | 341 | |
f2e0899f DK |
342 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) |
343 | { | |
344 | return opcode & ~DMAE_CMD_SRC_RESET; | |
345 | } | |
ad8d3948 | 346 | |
f2e0899f DK |
347 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
348 | bool with_comp, u8 comp_type) | |
349 | { | |
350 | u32 opcode = 0; | |
351 | ||
352 | opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | | |
353 | (dst_type << DMAE_COMMAND_DST_SHIFT)); | |
ad8d3948 | 354 | |
f2e0899f DK |
355 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
356 | ||
357 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); | |
3395a033 DK |
358 | opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | |
359 | (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); | |
f2e0899f | 360 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); |
a2fbb9ea | 361 | |
a2fbb9ea | 362 | #ifdef __BIG_ENDIAN |
f2e0899f | 363 | opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; |
a2fbb9ea | 364 | #else |
f2e0899f | 365 | opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; |
a2fbb9ea | 366 | #endif |
f2e0899f DK |
367 | if (with_comp) |
368 | opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); | |
369 | return opcode; | |
370 | } | |
371 | ||
8d96286a | 372 | static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, |
373 | struct dmae_command *dmae, | |
374 | u8 src_type, u8 dst_type) | |
f2e0899f DK |
375 | { |
376 | memset(dmae, 0, sizeof(struct dmae_command)); | |
377 | ||
378 | /* set the opcode */ | |
379 | dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, | |
380 | true, DMAE_COMP_PCI); | |
381 | ||
382 | /* fill in the completion parameters */ | |
383 | dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); | |
384 | dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); | |
385 | dmae->comp_val = DMAE_COMP_VAL; | |
386 | } | |
387 | ||
388 | /* issue a dmae command over the init-channel and wailt for completion */ | |
8d96286a | 389 | static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, |
390 | struct dmae_command *dmae) | |
f2e0899f DK |
391 | { |
392 | u32 *wb_comp = bnx2x_sp(bp, wb_comp); | |
5e374b5a | 393 | int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; |
f2e0899f DK |
394 | int rc = 0; |
395 | ||
619c5cb6 VZ |
396 | /* |
397 | * Lock the dmae channel. Disable BHs to prevent a dead-lock | |
398 | * as long as this code is called both from syscall context and | |
399 | * from ndo_set_rx_mode() flow that may be called from BH. | |
400 | */ | |
6e30dd4e | 401 | spin_lock_bh(&bp->dmae_lock); |
5ff7b6d4 | 402 | |
f2e0899f | 403 | /* reset completion */ |
a2fbb9ea ET |
404 | *wb_comp = 0; |
405 | ||
f2e0899f DK |
406 | /* post the command on the channel used for initializations */ |
407 | bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); | |
a2fbb9ea | 408 | |
f2e0899f | 409 | /* wait for completion */ |
a2fbb9ea | 410 | udelay(5); |
f2e0899f | 411 | while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { |
ad8d3948 | 412 | |
95c6c616 AE |
413 | if (!cnt || |
414 | (bp->recovery_state != BNX2X_RECOVERY_DONE && | |
415 | bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
c3eefaf6 | 416 | BNX2X_ERR("DMAE timeout!\n"); |
f2e0899f DK |
417 | rc = DMAE_TIMEOUT; |
418 | goto unlock; | |
a2fbb9ea | 419 | } |
ad8d3948 | 420 | cnt--; |
f2e0899f | 421 | udelay(50); |
a2fbb9ea | 422 | } |
f2e0899f DK |
423 | if (*wb_comp & DMAE_PCI_ERR_FLAG) { |
424 | BNX2X_ERR("DMAE PCI error!\n"); | |
425 | rc = DMAE_PCI_ERROR; | |
426 | } | |
427 | ||
f2e0899f | 428 | unlock: |
6e30dd4e | 429 | spin_unlock_bh(&bp->dmae_lock); |
f2e0899f DK |
430 | return rc; |
431 | } | |
432 | ||
433 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
434 | u32 len32) | |
435 | { | |
436 | struct dmae_command dmae; | |
437 | ||
438 | if (!bp->dmae_ready) { | |
439 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
440 | ||
127a425e AE |
441 | if (CHIP_IS_E1(bp)) |
442 | bnx2x_init_ind_wr(bp, dst_addr, data, len32); | |
443 | else | |
444 | bnx2x_init_str_wr(bp, dst_addr, data, len32); | |
f2e0899f DK |
445 | return; |
446 | } | |
447 | ||
448 | /* set opcode and fixed command fields */ | |
449 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); | |
450 | ||
451 | /* fill in addresses and len */ | |
452 | dmae.src_addr_lo = U64_LO(dma_addr); | |
453 | dmae.src_addr_hi = U64_HI(dma_addr); | |
454 | dmae.dst_addr_lo = dst_addr >> 2; | |
455 | dmae.dst_addr_hi = 0; | |
456 | dmae.len = len32; | |
457 | ||
f2e0899f DK |
458 | /* issue the command and wait for completion */ |
459 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
a2fbb9ea ET |
460 | } |
461 | ||
c18487ee | 462 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) |
a2fbb9ea | 463 | { |
5ff7b6d4 | 464 | struct dmae_command dmae; |
ad8d3948 EG |
465 | |
466 | if (!bp->dmae_ready) { | |
467 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
468 | int i; | |
469 | ||
51c1a580 | 470 | if (CHIP_IS_E1(bp)) |
127a425e AE |
471 | for (i = 0; i < len32; i++) |
472 | data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); | |
51c1a580 | 473 | else |
127a425e AE |
474 | for (i = 0; i < len32; i++) |
475 | data[i] = REG_RD(bp, src_addr + i*4); | |
476 | ||
ad8d3948 EG |
477 | return; |
478 | } | |
479 | ||
f2e0899f DK |
480 | /* set opcode and fixed command fields */ |
481 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); | |
a2fbb9ea | 482 | |
f2e0899f | 483 | /* fill in addresses and len */ |
5ff7b6d4 EG |
484 | dmae.src_addr_lo = src_addr >> 2; |
485 | dmae.src_addr_hi = 0; | |
486 | dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); | |
487 | dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); | |
488 | dmae.len = len32; | |
ad8d3948 | 489 | |
f2e0899f DK |
490 | /* issue the command and wait for completion */ |
491 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
ad8d3948 EG |
492 | } |
493 | ||
8d96286a | 494 | static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
495 | u32 addr, u32 len) | |
573f2035 | 496 | { |
02e3c6cb | 497 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); |
573f2035 EG |
498 | int offset = 0; |
499 | ||
02e3c6cb | 500 | while (len > dmae_wr_max) { |
573f2035 | 501 | bnx2x_write_dmae(bp, phys_addr + offset, |
02e3c6cb VZ |
502 | addr + offset, dmae_wr_max); |
503 | offset += dmae_wr_max * 4; | |
504 | len -= dmae_wr_max; | |
573f2035 EG |
505 | } |
506 | ||
507 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); | |
508 | } | |
509 | ||
a2fbb9ea ET |
510 | static int bnx2x_mc_assert(struct bnx2x *bp) |
511 | { | |
a2fbb9ea | 512 | char last_idx; |
34f80b04 EG |
513 | int i, rc = 0; |
514 | u32 row0, row1, row2, row3; | |
515 | ||
516 | /* XSTORM */ | |
517 | last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + | |
518 | XSTORM_ASSERT_LIST_INDEX_OFFSET); | |
519 | if (last_idx) | |
520 | BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
521 | ||
522 | /* print the asserts */ | |
523 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
524 | ||
525 | row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
526 | XSTORM_ASSERT_LIST_OFFSET(i)); | |
527 | row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
528 | XSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
529 | row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
530 | XSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
531 | row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
532 | XSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
533 | ||
534 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 535 | BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
536 | i, row3, row2, row1, row0); |
537 | rc++; | |
538 | } else { | |
539 | break; | |
540 | } | |
541 | } | |
542 | ||
543 | /* TSTORM */ | |
544 | last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + | |
545 | TSTORM_ASSERT_LIST_INDEX_OFFSET); | |
546 | if (last_idx) | |
547 | BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
548 | ||
549 | /* print the asserts */ | |
550 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
551 | ||
552 | row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
553 | TSTORM_ASSERT_LIST_OFFSET(i)); | |
554 | row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
555 | TSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
556 | row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
557 | TSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
558 | row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
559 | TSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
560 | ||
561 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 562 | BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
563 | i, row3, row2, row1, row0); |
564 | rc++; | |
565 | } else { | |
566 | break; | |
567 | } | |
568 | } | |
569 | ||
570 | /* CSTORM */ | |
571 | last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + | |
572 | CSTORM_ASSERT_LIST_INDEX_OFFSET); | |
573 | if (last_idx) | |
574 | BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
575 | ||
576 | /* print the asserts */ | |
577 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
578 | ||
579 | row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
580 | CSTORM_ASSERT_LIST_OFFSET(i)); | |
581 | row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
582 | CSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
583 | row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
584 | CSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
585 | row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
586 | CSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
587 | ||
588 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 589 | BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
590 | i, row3, row2, row1, row0); |
591 | rc++; | |
592 | } else { | |
593 | break; | |
594 | } | |
595 | } | |
596 | ||
597 | /* USTORM */ | |
598 | last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + | |
599 | USTORM_ASSERT_LIST_INDEX_OFFSET); | |
600 | if (last_idx) | |
601 | BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
602 | ||
603 | /* print the asserts */ | |
604 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
605 | ||
606 | row0 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
607 | USTORM_ASSERT_LIST_OFFSET(i)); | |
608 | row1 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
609 | USTORM_ASSERT_LIST_OFFSET(i) + 4); | |
610 | row2 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
611 | USTORM_ASSERT_LIST_OFFSET(i) + 8); | |
612 | row3 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
613 | USTORM_ASSERT_LIST_OFFSET(i) + 12); | |
614 | ||
615 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 616 | BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
617 | i, row3, row2, row1, row0); |
618 | rc++; | |
619 | } else { | |
620 | break; | |
a2fbb9ea ET |
621 | } |
622 | } | |
34f80b04 | 623 | |
a2fbb9ea ET |
624 | return rc; |
625 | } | |
c14423fe | 626 | |
7a25cc73 | 627 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) |
a2fbb9ea | 628 | { |
7a25cc73 | 629 | u32 addr, val; |
a2fbb9ea | 630 | u32 mark, offset; |
4781bfad | 631 | __be32 data[9]; |
a2fbb9ea | 632 | int word; |
f2e0899f | 633 | u32 trace_shmem_base; |
2145a920 VZ |
634 | if (BP_NOMCP(bp)) { |
635 | BNX2X_ERR("NO MCP - can not dump\n"); | |
636 | return; | |
637 | } | |
7a25cc73 DK |
638 | netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", |
639 | (bp->common.bc_ver & 0xff0000) >> 16, | |
640 | (bp->common.bc_ver & 0xff00) >> 8, | |
641 | (bp->common.bc_ver & 0xff)); | |
642 | ||
643 | val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); | |
644 | if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) | |
51c1a580 | 645 | BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); |
cdaa7cb8 | 646 | |
f2e0899f DK |
647 | if (BP_PATH(bp) == 0) |
648 | trace_shmem_base = bp->common.shmem_base; | |
649 | else | |
650 | trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); | |
de128804 DK |
651 | addr = trace_shmem_base - 0x800; |
652 | ||
653 | /* validate TRCB signature */ | |
654 | mark = REG_RD(bp, addr); | |
655 | if (mark != MFW_TRACE_SIGNATURE) { | |
656 | BNX2X_ERR("Trace buffer signature is missing."); | |
657 | return ; | |
658 | } | |
659 | ||
660 | /* read cyclic buffer pointer */ | |
661 | addr += 4; | |
cdaa7cb8 | 662 | mark = REG_RD(bp, addr); |
f2e0899f DK |
663 | mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) |
664 | + ((mark + 0x3) & ~0x3) - 0x08000000; | |
7a25cc73 | 665 | printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); |
a2fbb9ea | 666 | |
7a25cc73 | 667 | printk("%s", lvl); |
f2e0899f | 668 | for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { |
a2fbb9ea | 669 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 670 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 671 | data[8] = 0x0; |
7995c64e | 672 | pr_cont("%s", (char *)data); |
a2fbb9ea | 673 | } |
cdaa7cb8 | 674 | for (offset = addr + 4; offset <= mark; offset += 0x8*4) { |
a2fbb9ea | 675 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 676 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 677 | data[8] = 0x0; |
7995c64e | 678 | pr_cont("%s", (char *)data); |
a2fbb9ea | 679 | } |
7a25cc73 DK |
680 | printk("%s" "end of fw dump\n", lvl); |
681 | } | |
682 | ||
683 | static inline void bnx2x_fw_dump(struct bnx2x *bp) | |
684 | { | |
685 | bnx2x_fw_dump_lvl(bp, KERN_ERR); | |
a2fbb9ea ET |
686 | } |
687 | ||
6c719d00 | 688 | void bnx2x_panic_dump(struct bnx2x *bp) |
a2fbb9ea ET |
689 | { |
690 | int i; | |
523224a3 DK |
691 | u16 j; |
692 | struct hc_sp_status_block_data sp_sb_data; | |
693 | int func = BP_FUNC(bp); | |
694 | #ifdef BNX2X_STOP_ON_ERROR | |
695 | u16 start = 0, end = 0; | |
6383c0b3 | 696 | u8 cos; |
523224a3 | 697 | #endif |
a2fbb9ea | 698 | |
66e855f3 | 699 | bp->stats_state = STATS_STATE_DISABLED; |
7a752993 | 700 | bp->eth_stats.unrecoverable_error++; |
66e855f3 YG |
701 | DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); |
702 | ||
a2fbb9ea ET |
703 | BNX2X_ERR("begin crash dump -----------------\n"); |
704 | ||
8440d2b6 EG |
705 | /* Indices */ |
706 | /* Common */ | |
51c1a580 | 707 | BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", |
619c5cb6 VZ |
708 | bp->def_idx, bp->def_att_idx, bp->attn_state, |
709 | bp->spq_prod_idx, bp->stats_counter); | |
523224a3 DK |
710 | BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", |
711 | bp->def_status_blk->atten_status_block.attn_bits, | |
712 | bp->def_status_blk->atten_status_block.attn_bits_ack, | |
713 | bp->def_status_blk->atten_status_block.status_block_id, | |
714 | bp->def_status_blk->atten_status_block.attn_bits_index); | |
715 | BNX2X_ERR(" def ("); | |
716 | for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) | |
717 | pr_cont("0x%x%s", | |
f1deab50 JP |
718 | bp->def_status_blk->sp_sb.index_values[i], |
719 | (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); | |
523224a3 DK |
720 | |
721 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
722 | *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
723 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
724 | i*sizeof(u32)); | |
725 | ||
f1deab50 | 726 | pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", |
523224a3 DK |
727 | sp_sb_data.igu_sb_id, |
728 | sp_sb_data.igu_seg_id, | |
729 | sp_sb_data.p_func.pf_id, | |
730 | sp_sb_data.p_func.vnic_id, | |
731 | sp_sb_data.p_func.vf_id, | |
619c5cb6 VZ |
732 | sp_sb_data.p_func.vf_valid, |
733 | sp_sb_data.state); | |
523224a3 | 734 | |
8440d2b6 | 735 | |
ec6ba945 | 736 | for_each_eth_queue(bp, i) { |
a2fbb9ea | 737 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
523224a3 | 738 | int loop; |
f2e0899f | 739 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
740 | struct hc_status_block_data_e1x sb_data_e1x; |
741 | struct hc_status_block_sm *hc_sm_p = | |
619c5cb6 VZ |
742 | CHIP_IS_E1x(bp) ? |
743 | sb_data_e1x.common.state_machine : | |
744 | sb_data_e2.common.state_machine; | |
523224a3 | 745 | struct hc_index_data *hc_index_p = |
619c5cb6 VZ |
746 | CHIP_IS_E1x(bp) ? |
747 | sb_data_e1x.index_data : | |
748 | sb_data_e2.index_data; | |
6383c0b3 | 749 | u8 data_size, cos; |
523224a3 | 750 | u32 *sb_data_p; |
6383c0b3 | 751 | struct bnx2x_fp_txdata txdata; |
523224a3 DK |
752 | |
753 | /* Rx */ | |
51c1a580 | 754 | BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", |
8440d2b6 | 755 | i, fp->rx_bd_prod, fp->rx_bd_cons, |
523224a3 | 756 | fp->rx_comp_prod, |
66e855f3 | 757 | fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); |
51c1a580 | 758 | BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", |
8440d2b6 | 759 | fp->rx_sge_prod, fp->last_max_sge, |
523224a3 | 760 | le16_to_cpu(fp->fp_hc_idx)); |
a2fbb9ea | 761 | |
523224a3 | 762 | /* Tx */ |
6383c0b3 AE |
763 | for_each_cos_in_tx_queue(fp, cos) |
764 | { | |
765 | txdata = fp->txdata[cos]; | |
51c1a580 | 766 | BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", |
6383c0b3 AE |
767 | i, txdata.tx_pkt_prod, |
768 | txdata.tx_pkt_cons, txdata.tx_bd_prod, | |
769 | txdata.tx_bd_cons, | |
770 | le16_to_cpu(*txdata.tx_cons_sb)); | |
771 | } | |
523224a3 | 772 | |
619c5cb6 VZ |
773 | loop = CHIP_IS_E1x(bp) ? |
774 | HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; | |
523224a3 DK |
775 | |
776 | /* host sb data */ | |
777 | ||
ec6ba945 VZ |
778 | #ifdef BCM_CNIC |
779 | if (IS_FCOE_FP(fp)) | |
780 | continue; | |
781 | #endif | |
523224a3 DK |
782 | BNX2X_ERR(" run indexes ("); |
783 | for (j = 0; j < HC_SB_MAX_SM; j++) | |
784 | pr_cont("0x%x%s", | |
785 | fp->sb_running_index[j], | |
786 | (j == HC_SB_MAX_SM - 1) ? ")" : " "); | |
787 | ||
788 | BNX2X_ERR(" indexes ("); | |
789 | for (j = 0; j < loop; j++) | |
790 | pr_cont("0x%x%s", | |
791 | fp->sb_index_values[j], | |
792 | (j == loop - 1) ? ")" : " "); | |
793 | /* fw sb data */ | |
619c5cb6 VZ |
794 | data_size = CHIP_IS_E1x(bp) ? |
795 | sizeof(struct hc_status_block_data_e1x) : | |
796 | sizeof(struct hc_status_block_data_e2); | |
523224a3 | 797 | data_size /= sizeof(u32); |
619c5cb6 VZ |
798 | sb_data_p = CHIP_IS_E1x(bp) ? |
799 | (u32 *)&sb_data_e1x : | |
800 | (u32 *)&sb_data_e2; | |
523224a3 DK |
801 | /* copy sb data in here */ |
802 | for (j = 0; j < data_size; j++) | |
803 | *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
804 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + | |
805 | j * sizeof(u32)); | |
806 | ||
619c5cb6 | 807 | if (!CHIP_IS_E1x(bp)) { |
51c1a580 | 808 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
809 | sb_data_e2.common.p_func.pf_id, |
810 | sb_data_e2.common.p_func.vf_id, | |
811 | sb_data_e2.common.p_func.vf_valid, | |
812 | sb_data_e2.common.p_func.vnic_id, | |
619c5cb6 VZ |
813 | sb_data_e2.common.same_igu_sb_1b, |
814 | sb_data_e2.common.state); | |
f2e0899f | 815 | } else { |
51c1a580 | 816 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
817 | sb_data_e1x.common.p_func.pf_id, |
818 | sb_data_e1x.common.p_func.vf_id, | |
819 | sb_data_e1x.common.p_func.vf_valid, | |
820 | sb_data_e1x.common.p_func.vnic_id, | |
619c5cb6 VZ |
821 | sb_data_e1x.common.same_igu_sb_1b, |
822 | sb_data_e1x.common.state); | |
f2e0899f | 823 | } |
523224a3 DK |
824 | |
825 | /* SB_SMs data */ | |
826 | for (j = 0; j < HC_SB_MAX_SM; j++) { | |
51c1a580 MS |
827 | pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", |
828 | j, hc_sm_p[j].__flags, | |
829 | hc_sm_p[j].igu_sb_id, | |
830 | hc_sm_p[j].igu_seg_id, | |
831 | hc_sm_p[j].time_to_expire, | |
832 | hc_sm_p[j].timer_value); | |
523224a3 DK |
833 | } |
834 | ||
835 | /* Indecies data */ | |
836 | for (j = 0; j < loop; j++) { | |
51c1a580 | 837 | pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, |
523224a3 DK |
838 | hc_index_p[j].flags, |
839 | hc_index_p[j].timeout); | |
840 | } | |
8440d2b6 | 841 | } |
a2fbb9ea | 842 | |
523224a3 | 843 | #ifdef BNX2X_STOP_ON_ERROR |
8440d2b6 EG |
844 | /* Rings */ |
845 | /* Rx */ | |
ec6ba945 | 846 | for_each_rx_queue(bp, i) { |
8440d2b6 | 847 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea ET |
848 | |
849 | start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); | |
850 | end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); | |
8440d2b6 | 851 | for (j = start; j != end; j = RX_BD(j + 1)) { |
a2fbb9ea ET |
852 | u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; |
853 | struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; | |
854 | ||
c3eefaf6 | 855 | BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", |
44151acb | 856 | i, j, rx_bd[1], rx_bd[0], sw_bd->data); |
a2fbb9ea ET |
857 | } |
858 | ||
3196a88a EG |
859 | start = RX_SGE(fp->rx_sge_prod); |
860 | end = RX_SGE(fp->last_max_sge); | |
8440d2b6 | 861 | for (j = start; j != end; j = RX_SGE(j + 1)) { |
7a9b2557 VZ |
862 | u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; |
863 | struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; | |
864 | ||
c3eefaf6 EG |
865 | BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", |
866 | i, j, rx_sge[1], rx_sge[0], sw_page->page); | |
7a9b2557 VZ |
867 | } |
868 | ||
a2fbb9ea ET |
869 | start = RCQ_BD(fp->rx_comp_cons - 10); |
870 | end = RCQ_BD(fp->rx_comp_cons + 503); | |
8440d2b6 | 871 | for (j = start; j != end; j = RCQ_BD(j + 1)) { |
a2fbb9ea ET |
872 | u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; |
873 | ||
c3eefaf6 EG |
874 | BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", |
875 | i, j, cqe[0], cqe[1], cqe[2], cqe[3]); | |
a2fbb9ea ET |
876 | } |
877 | } | |
878 | ||
8440d2b6 | 879 | /* Tx */ |
ec6ba945 | 880 | for_each_tx_queue(bp, i) { |
8440d2b6 | 881 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
6383c0b3 AE |
882 | for_each_cos_in_tx_queue(fp, cos) { |
883 | struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; | |
884 | ||
885 | start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); | |
886 | end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); | |
887 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
888 | struct sw_tx_bd *sw_bd = | |
889 | &txdata->tx_buf_ring[j]; | |
890 | ||
51c1a580 | 891 | BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", |
6383c0b3 AE |
892 | i, cos, j, sw_bd->skb, |
893 | sw_bd->first_bd); | |
894 | } | |
8440d2b6 | 895 | |
6383c0b3 AE |
896 | start = TX_BD(txdata->tx_bd_cons - 10); |
897 | end = TX_BD(txdata->tx_bd_cons + 254); | |
898 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
899 | u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; | |
8440d2b6 | 900 | |
51c1a580 | 901 | BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", |
6383c0b3 AE |
902 | i, cos, j, tx_bd[0], tx_bd[1], |
903 | tx_bd[2], tx_bd[3]); | |
904 | } | |
8440d2b6 EG |
905 | } |
906 | } | |
523224a3 | 907 | #endif |
34f80b04 | 908 | bnx2x_fw_dump(bp); |
a2fbb9ea ET |
909 | bnx2x_mc_assert(bp); |
910 | BNX2X_ERR("end crash dump -----------------\n"); | |
a2fbb9ea ET |
911 | } |
912 | ||
619c5cb6 VZ |
913 | /* |
914 | * FLR Support for E2 | |
915 | * | |
916 | * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW | |
917 | * initialization. | |
918 | */ | |
919 | #define FLR_WAIT_USEC 10000 /* 10 miliseconds */ | |
89db4ad8 AE |
920 | #define FLR_WAIT_INTERVAL 50 /* usec */ |
921 | #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ | |
619c5cb6 VZ |
922 | |
923 | struct pbf_pN_buf_regs { | |
924 | int pN; | |
925 | u32 init_crd; | |
926 | u32 crd; | |
927 | u32 crd_freed; | |
928 | }; | |
929 | ||
930 | struct pbf_pN_cmd_regs { | |
931 | int pN; | |
932 | u32 lines_occup; | |
933 | u32 lines_freed; | |
934 | }; | |
935 | ||
936 | static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, | |
937 | struct pbf_pN_buf_regs *regs, | |
938 | u32 poll_count) | |
939 | { | |
940 | u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; | |
941 | u32 cur_cnt = poll_count; | |
942 | ||
943 | crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); | |
944 | crd = crd_start = REG_RD(bp, regs->crd); | |
945 | init_crd = REG_RD(bp, regs->init_crd); | |
946 | ||
947 | DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); | |
948 | DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); | |
949 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); | |
950 | ||
951 | while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < | |
952 | (init_crd - crd_start))) { | |
953 | if (cur_cnt--) { | |
89db4ad8 | 954 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
955 | crd = REG_RD(bp, regs->crd); |
956 | crd_freed = REG_RD(bp, regs->crd_freed); | |
957 | } else { | |
958 | DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", | |
959 | regs->pN); | |
960 | DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", | |
961 | regs->pN, crd); | |
962 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", | |
963 | regs->pN, crd_freed); | |
964 | break; | |
965 | } | |
966 | } | |
967 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", | |
89db4ad8 | 968 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
969 | } |
970 | ||
971 | static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, | |
972 | struct pbf_pN_cmd_regs *regs, | |
973 | u32 poll_count) | |
974 | { | |
975 | u32 occup, to_free, freed, freed_start; | |
976 | u32 cur_cnt = poll_count; | |
977 | ||
978 | occup = to_free = REG_RD(bp, regs->lines_occup); | |
979 | freed = freed_start = REG_RD(bp, regs->lines_freed); | |
980 | ||
981 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); | |
982 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); | |
983 | ||
984 | while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { | |
985 | if (cur_cnt--) { | |
89db4ad8 | 986 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
987 | occup = REG_RD(bp, regs->lines_occup); |
988 | freed = REG_RD(bp, regs->lines_freed); | |
989 | } else { | |
990 | DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", | |
991 | regs->pN); | |
992 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", | |
993 | regs->pN, occup); | |
994 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", | |
995 | regs->pN, freed); | |
996 | break; | |
997 | } | |
998 | } | |
999 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", | |
89db4ad8 | 1000 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
1001 | } |
1002 | ||
1003 | static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, | |
1004 | u32 expected, u32 poll_count) | |
1005 | { | |
1006 | u32 cur_cnt = poll_count; | |
1007 | u32 val; | |
1008 | ||
1009 | while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) | |
89db4ad8 | 1010 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1011 | |
1012 | return val; | |
1013 | } | |
1014 | ||
1015 | static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, | |
1016 | char *msg, u32 poll_cnt) | |
1017 | { | |
1018 | u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); | |
1019 | if (val != 0) { | |
1020 | BNX2X_ERR("%s usage count=%d\n", msg, val); | |
1021 | return 1; | |
1022 | } | |
1023 | return 0; | |
1024 | } | |
1025 | ||
1026 | static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) | |
1027 | { | |
1028 | /* adjust polling timeout */ | |
1029 | if (CHIP_REV_IS_EMUL(bp)) | |
1030 | return FLR_POLL_CNT * 2000; | |
1031 | ||
1032 | if (CHIP_REV_IS_FPGA(bp)) | |
1033 | return FLR_POLL_CNT * 120; | |
1034 | ||
1035 | return FLR_POLL_CNT; | |
1036 | } | |
1037 | ||
1038 | static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) | |
1039 | { | |
1040 | struct pbf_pN_cmd_regs cmd_regs[] = { | |
1041 | {0, (CHIP_IS_E3B0(bp)) ? | |
1042 | PBF_REG_TQ_OCCUPANCY_Q0 : | |
1043 | PBF_REG_P0_TQ_OCCUPANCY, | |
1044 | (CHIP_IS_E3B0(bp)) ? | |
1045 | PBF_REG_TQ_LINES_FREED_CNT_Q0 : | |
1046 | PBF_REG_P0_TQ_LINES_FREED_CNT}, | |
1047 | {1, (CHIP_IS_E3B0(bp)) ? | |
1048 | PBF_REG_TQ_OCCUPANCY_Q1 : | |
1049 | PBF_REG_P1_TQ_OCCUPANCY, | |
1050 | (CHIP_IS_E3B0(bp)) ? | |
1051 | PBF_REG_TQ_LINES_FREED_CNT_Q1 : | |
1052 | PBF_REG_P1_TQ_LINES_FREED_CNT}, | |
1053 | {4, (CHIP_IS_E3B0(bp)) ? | |
1054 | PBF_REG_TQ_OCCUPANCY_LB_Q : | |
1055 | PBF_REG_P4_TQ_OCCUPANCY, | |
1056 | (CHIP_IS_E3B0(bp)) ? | |
1057 | PBF_REG_TQ_LINES_FREED_CNT_LB_Q : | |
1058 | PBF_REG_P4_TQ_LINES_FREED_CNT} | |
1059 | }; | |
1060 | ||
1061 | struct pbf_pN_buf_regs buf_regs[] = { | |
1062 | {0, (CHIP_IS_E3B0(bp)) ? | |
1063 | PBF_REG_INIT_CRD_Q0 : | |
1064 | PBF_REG_P0_INIT_CRD , | |
1065 | (CHIP_IS_E3B0(bp)) ? | |
1066 | PBF_REG_CREDIT_Q0 : | |
1067 | PBF_REG_P0_CREDIT, | |
1068 | (CHIP_IS_E3B0(bp)) ? | |
1069 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : | |
1070 | PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, | |
1071 | {1, (CHIP_IS_E3B0(bp)) ? | |
1072 | PBF_REG_INIT_CRD_Q1 : | |
1073 | PBF_REG_P1_INIT_CRD, | |
1074 | (CHIP_IS_E3B0(bp)) ? | |
1075 | PBF_REG_CREDIT_Q1 : | |
1076 | PBF_REG_P1_CREDIT, | |
1077 | (CHIP_IS_E3B0(bp)) ? | |
1078 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : | |
1079 | PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, | |
1080 | {4, (CHIP_IS_E3B0(bp)) ? | |
1081 | PBF_REG_INIT_CRD_LB_Q : | |
1082 | PBF_REG_P4_INIT_CRD, | |
1083 | (CHIP_IS_E3B0(bp)) ? | |
1084 | PBF_REG_CREDIT_LB_Q : | |
1085 | PBF_REG_P4_CREDIT, | |
1086 | (CHIP_IS_E3B0(bp)) ? | |
1087 | PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : | |
1088 | PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, | |
1089 | }; | |
1090 | ||
1091 | int i; | |
1092 | ||
1093 | /* Verify the command queues are flushed P0, P1, P4 */ | |
1094 | for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) | |
1095 | bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); | |
1096 | ||
1097 | ||
1098 | /* Verify the transmission buffers are flushed P0, P1, P4 */ | |
1099 | for (i = 0; i < ARRAY_SIZE(buf_regs); i++) | |
1100 | bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); | |
1101 | } | |
1102 | ||
1103 | #define OP_GEN_PARAM(param) \ | |
1104 | (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) | |
1105 | ||
1106 | #define OP_GEN_TYPE(type) \ | |
1107 | (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) | |
1108 | ||
1109 | #define OP_GEN_AGG_VECT(index) \ | |
1110 | (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) | |
1111 | ||
1112 | ||
1113 | static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, | |
1114 | u32 poll_cnt) | |
1115 | { | |
1116 | struct sdm_op_gen op_gen = {0}; | |
1117 | ||
1118 | u32 comp_addr = BAR_CSTRORM_INTMEM + | |
1119 | CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); | |
1120 | int ret = 0; | |
1121 | ||
1122 | if (REG_RD(bp, comp_addr)) { | |
89db4ad8 | 1123 | BNX2X_ERR("Cleanup complete was not 0 before sending\n"); |
619c5cb6 VZ |
1124 | return 1; |
1125 | } | |
1126 | ||
1127 | op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); | |
1128 | op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); | |
1129 | op_gen.command |= OP_GEN_AGG_VECT(clnup_func); | |
1130 | op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; | |
1131 | ||
89db4ad8 | 1132 | DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); |
619c5cb6 VZ |
1133 | REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); |
1134 | ||
1135 | if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { | |
1136 | BNX2X_ERR("FW final cleanup did not succeed\n"); | |
51c1a580 MS |
1137 | DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", |
1138 | (REG_RD(bp, comp_addr))); | |
619c5cb6 VZ |
1139 | ret = 1; |
1140 | } | |
1141 | /* Zero completion for nxt FLR */ | |
1142 | REG_WR(bp, comp_addr, 0); | |
1143 | ||
1144 | return ret; | |
1145 | } | |
1146 | ||
1147 | static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) | |
1148 | { | |
1149 | int pos; | |
1150 | u16 status; | |
1151 | ||
77c98e6a | 1152 | pos = pci_pcie_cap(dev); |
619c5cb6 VZ |
1153 | if (!pos) |
1154 | return false; | |
1155 | ||
1156 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); | |
1157 | return status & PCI_EXP_DEVSTA_TRPND; | |
1158 | } | |
1159 | ||
1160 | /* PF FLR specific routines | |
1161 | */ | |
1162 | static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) | |
1163 | { | |
1164 | ||
1165 | /* wait for CFC PF usage-counter to zero (includes all the VFs) */ | |
1166 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1167 | CFC_REG_NUM_LCIDS_INSIDE_PF, | |
1168 | "CFC PF usage counter timed out", | |
1169 | poll_cnt)) | |
1170 | return 1; | |
1171 | ||
1172 | ||
1173 | /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ | |
1174 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1175 | DORQ_REG_PF_USAGE_CNT, | |
1176 | "DQ PF usage counter timed out", | |
1177 | poll_cnt)) | |
1178 | return 1; | |
1179 | ||
1180 | /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ | |
1181 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1182 | QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), | |
1183 | "QM PF usage counter timed out", | |
1184 | poll_cnt)) | |
1185 | return 1; | |
1186 | ||
1187 | /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ | |
1188 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1189 | TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), | |
1190 | "Timers VNIC usage counter timed out", | |
1191 | poll_cnt)) | |
1192 | return 1; | |
1193 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1194 | TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), | |
1195 | "Timers NUM_SCANS usage counter timed out", | |
1196 | poll_cnt)) | |
1197 | return 1; | |
1198 | ||
1199 | /* Wait DMAE PF usage counter to zero */ | |
1200 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1201 | dmae_reg_go_c[INIT_DMAE_C(bp)], | |
1202 | "DMAE dommand register timed out", | |
1203 | poll_cnt)) | |
1204 | return 1; | |
1205 | ||
1206 | return 0; | |
1207 | } | |
1208 | ||
1209 | static void bnx2x_hw_enable_status(struct bnx2x *bp) | |
1210 | { | |
1211 | u32 val; | |
1212 | ||
1213 | val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); | |
1214 | DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); | |
1215 | ||
1216 | val = REG_RD(bp, PBF_REG_DISABLE_PF); | |
1217 | DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); | |
1218 | ||
1219 | val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); | |
1220 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); | |
1221 | ||
1222 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); | |
1223 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); | |
1224 | ||
1225 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); | |
1226 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); | |
1227 | ||
1228 | val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); | |
1229 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); | |
1230 | ||
1231 | val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); | |
1232 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); | |
1233 | ||
1234 | val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
1235 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", | |
1236 | val); | |
1237 | } | |
1238 | ||
1239 | static int bnx2x_pf_flr_clnup(struct bnx2x *bp) | |
1240 | { | |
1241 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); | |
1242 | ||
1243 | DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); | |
1244 | ||
1245 | /* Re-enable PF target read access */ | |
1246 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
1247 | ||
1248 | /* Poll HW usage counters */ | |
89db4ad8 | 1249 | DP(BNX2X_MSG_SP, "Polling usage counters\n"); |
619c5cb6 VZ |
1250 | if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) |
1251 | return -EBUSY; | |
1252 | ||
1253 | /* Zero the igu 'trailing edge' and 'leading edge' */ | |
1254 | ||
1255 | /* Send the FW cleanup command */ | |
1256 | if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) | |
1257 | return -EBUSY; | |
1258 | ||
1259 | /* ATC cleanup */ | |
1260 | ||
1261 | /* Verify TX hw is flushed */ | |
1262 | bnx2x_tx_hw_flushed(bp, poll_cnt); | |
1263 | ||
1264 | /* Wait 100ms (not adjusted according to platform) */ | |
1265 | msleep(100); | |
1266 | ||
1267 | /* Verify no pending pci transactions */ | |
1268 | if (bnx2x_is_pcie_pending(bp->pdev)) | |
1269 | BNX2X_ERR("PCIE Transactions still pending\n"); | |
1270 | ||
1271 | /* Debug */ | |
1272 | bnx2x_hw_enable_status(bp); | |
1273 | ||
1274 | /* | |
1275 | * Master enable - Due to WB DMAE writes performed before this | |
1276 | * register is re-initialized as part of the regular function init | |
1277 | */ | |
1278 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
1279 | ||
1280 | return 0; | |
1281 | } | |
1282 | ||
f2e0899f | 1283 | static void bnx2x_hc_int_enable(struct bnx2x *bp) |
a2fbb9ea | 1284 | { |
34f80b04 | 1285 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1286 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1287 | u32 val = REG_RD(bp, addr); | |
1288 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
8badd27a | 1289 | int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; |
a2fbb9ea ET |
1290 | |
1291 | if (msix) { | |
8badd27a EG |
1292 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
1293 | HC_CONFIG_0_REG_INT_LINE_EN_0); | |
a2fbb9ea ET |
1294 | val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
1295 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
8badd27a EG |
1296 | } else if (msi) { |
1297 | val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; | |
1298 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1299 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1300 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1301 | } else { |
1302 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
615f8fd9 | 1303 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
a2fbb9ea ET |
1304 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
1305 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
615f8fd9 | 1306 | |
a0fd065c | 1307 | if (!CHIP_IS_E1(bp)) { |
51c1a580 MS |
1308 | DP(NETIF_MSG_IFUP, |
1309 | "write %x to HC %d (addr 0x%x)\n", val, port, addr); | |
615f8fd9 | 1310 | |
a0fd065c | 1311 | REG_WR(bp, addr, val); |
615f8fd9 | 1312 | |
a0fd065c DK |
1313 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
1314 | } | |
a2fbb9ea ET |
1315 | } |
1316 | ||
a0fd065c DK |
1317 | if (CHIP_IS_E1(bp)) |
1318 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); | |
1319 | ||
51c1a580 MS |
1320 | DP(NETIF_MSG_IFUP, |
1321 | "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, | |
1322 | (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
a2fbb9ea ET |
1323 | |
1324 | REG_WR(bp, addr, val); | |
37dbbf32 EG |
1325 | /* |
1326 | * Ensure that HC_CONFIG is written before leading/trailing edge config | |
1327 | */ | |
1328 | mmiowb(); | |
1329 | barrier(); | |
34f80b04 | 1330 | |
f2e0899f | 1331 | if (!CHIP_IS_E1(bp)) { |
34f80b04 | 1332 | /* init leading/trailing edge */ |
fb3bff17 | 1333 | if (IS_MF(bp)) { |
3395a033 | 1334 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
34f80b04 | 1335 | if (bp->port.pmf) |
4acac6a5 EG |
1336 | /* enable nig and gpio3 attention */ |
1337 | val |= 0x1100; | |
34f80b04 EG |
1338 | } else |
1339 | val = 0xffff; | |
1340 | ||
1341 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
1342 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
1343 | } | |
37dbbf32 EG |
1344 | |
1345 | /* Make sure that interrupts are indeed enabled from here on */ | |
1346 | mmiowb(); | |
a2fbb9ea ET |
1347 | } |
1348 | ||
f2e0899f DK |
1349 | static void bnx2x_igu_int_enable(struct bnx2x *bp) |
1350 | { | |
1351 | u32 val; | |
30a5de77 DK |
1352 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1353 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1354 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
f2e0899f DK |
1355 | |
1356 | val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1357 | ||
1358 | if (msix) { | |
1359 | val &= ~(IGU_PF_CONF_INT_LINE_EN | | |
1360 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1361 | val |= (IGU_PF_CONF_FUNC_EN | | |
1362 | IGU_PF_CONF_MSI_MSIX_EN | | |
1363 | IGU_PF_CONF_ATTN_BIT_EN); | |
30a5de77 DK |
1364 | |
1365 | if (single_msix) | |
1366 | val |= IGU_PF_CONF_SINGLE_ISR_EN; | |
f2e0899f DK |
1367 | } else if (msi) { |
1368 | val &= ~IGU_PF_CONF_INT_LINE_EN; | |
1369 | val |= (IGU_PF_CONF_FUNC_EN | | |
1370 | IGU_PF_CONF_MSI_MSIX_EN | | |
1371 | IGU_PF_CONF_ATTN_BIT_EN | | |
1372 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1373 | } else { | |
1374 | val &= ~IGU_PF_CONF_MSI_MSIX_EN; | |
1375 | val |= (IGU_PF_CONF_FUNC_EN | | |
1376 | IGU_PF_CONF_INT_LINE_EN | | |
1377 | IGU_PF_CONF_ATTN_BIT_EN | | |
1378 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1379 | } | |
1380 | ||
51c1a580 | 1381 | DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", |
f2e0899f DK |
1382 | val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); |
1383 | ||
1384 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1385 | ||
79a8557a YM |
1386 | if (val & IGU_PF_CONF_INT_LINE_EN) |
1387 | pci_intx(bp->pdev, true); | |
1388 | ||
f2e0899f DK |
1389 | barrier(); |
1390 | ||
1391 | /* init leading/trailing edge */ | |
1392 | if (IS_MF(bp)) { | |
3395a033 | 1393 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
1394 | if (bp->port.pmf) |
1395 | /* enable nig and gpio3 attention */ | |
1396 | val |= 0x1100; | |
1397 | } else | |
1398 | val = 0xffff; | |
1399 | ||
1400 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); | |
1401 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
1402 | ||
1403 | /* Make sure that interrupts are indeed enabled from here on */ | |
1404 | mmiowb(); | |
1405 | } | |
1406 | ||
1407 | void bnx2x_int_enable(struct bnx2x *bp) | |
1408 | { | |
1409 | if (bp->common.int_block == INT_BLOCK_HC) | |
1410 | bnx2x_hc_int_enable(bp); | |
1411 | else | |
1412 | bnx2x_igu_int_enable(bp); | |
1413 | } | |
1414 | ||
1415 | static void bnx2x_hc_int_disable(struct bnx2x *bp) | |
a2fbb9ea | 1416 | { |
34f80b04 | 1417 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1418 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1419 | u32 val = REG_RD(bp, addr); | |
1420 | ||
a0fd065c DK |
1421 | /* |
1422 | * in E1 we must use only PCI configuration space to disable | |
1423 | * MSI/MSIX capablility | |
1424 | * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block | |
1425 | */ | |
1426 | if (CHIP_IS_E1(bp)) { | |
1427 | /* Since IGU_PF_CONF_MSI_MSIX_EN still always on | |
1428 | * Use mask register to prevent from HC sending interrupts | |
1429 | * after we exit the function | |
1430 | */ | |
1431 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0); | |
1432 | ||
1433 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1434 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1435 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
1436 | } else | |
1437 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1438 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1439 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1440 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea | 1441 | |
51c1a580 MS |
1442 | DP(NETIF_MSG_IFDOWN, |
1443 | "write %x to HC %d (addr 0x%x)\n", | |
a2fbb9ea ET |
1444 | val, port, addr); |
1445 | ||
8badd27a EG |
1446 | /* flush all outstanding writes */ |
1447 | mmiowb(); | |
1448 | ||
a2fbb9ea ET |
1449 | REG_WR(bp, addr, val); |
1450 | if (REG_RD(bp, addr) != val) | |
1451 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1452 | } | |
1453 | ||
f2e0899f DK |
1454 | static void bnx2x_igu_int_disable(struct bnx2x *bp) |
1455 | { | |
1456 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1457 | ||
1458 | val &= ~(IGU_PF_CONF_MSI_MSIX_EN | | |
1459 | IGU_PF_CONF_INT_LINE_EN | | |
1460 | IGU_PF_CONF_ATTN_BIT_EN); | |
1461 | ||
51c1a580 | 1462 | DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); |
f2e0899f DK |
1463 | |
1464 | /* flush all outstanding writes */ | |
1465 | mmiowb(); | |
1466 | ||
1467 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1468 | if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) | |
1469 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1470 | } | |
1471 | ||
6383c0b3 | 1472 | void bnx2x_int_disable(struct bnx2x *bp) |
f2e0899f DK |
1473 | { |
1474 | if (bp->common.int_block == INT_BLOCK_HC) | |
1475 | bnx2x_hc_int_disable(bp); | |
1476 | else | |
1477 | bnx2x_igu_int_disable(bp); | |
1478 | } | |
1479 | ||
9f6c9258 | 1480 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) |
a2fbb9ea | 1481 | { |
a2fbb9ea | 1482 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
8badd27a | 1483 | int i, offset; |
a2fbb9ea | 1484 | |
f8ef6e44 YG |
1485 | if (disable_hw) |
1486 | /* prevent the HW from sending interrupts */ | |
1487 | bnx2x_int_disable(bp); | |
a2fbb9ea ET |
1488 | |
1489 | /* make sure all ISRs are done */ | |
1490 | if (msix) { | |
8badd27a EG |
1491 | synchronize_irq(bp->msix_table[0].vector); |
1492 | offset = 1; | |
37b091ba MC |
1493 | #ifdef BCM_CNIC |
1494 | offset++; | |
1495 | #endif | |
ec6ba945 | 1496 | for_each_eth_queue(bp, i) |
754a2f52 | 1497 | synchronize_irq(bp->msix_table[offset++].vector); |
a2fbb9ea ET |
1498 | } else |
1499 | synchronize_irq(bp->pdev->irq); | |
1500 | ||
1501 | /* make sure sp_task is not running */ | |
1cf167f2 | 1502 | cancel_delayed_work(&bp->sp_task); |
3deb8167 | 1503 | cancel_delayed_work(&bp->period_task); |
1cf167f2 | 1504 | flush_workqueue(bnx2x_wq); |
a2fbb9ea ET |
1505 | } |
1506 | ||
34f80b04 | 1507 | /* fast path */ |
a2fbb9ea ET |
1508 | |
1509 | /* | |
34f80b04 | 1510 | * General service functions |
a2fbb9ea ET |
1511 | */ |
1512 | ||
72fd0718 VZ |
1513 | /* Return true if succeeded to acquire the lock */ |
1514 | static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) | |
1515 | { | |
1516 | u32 lock_status; | |
1517 | u32 resource_bit = (1 << resource); | |
1518 | int func = BP_FUNC(bp); | |
1519 | u32 hw_lock_control_reg; | |
1520 | ||
51c1a580 MS |
1521 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1522 | "Trying to take a lock on resource %d\n", resource); | |
72fd0718 VZ |
1523 | |
1524 | /* Validating that the resource is within range */ | |
1525 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1526 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
72fd0718 VZ |
1527 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
1528 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
0fdf4d09 | 1529 | return false; |
72fd0718 VZ |
1530 | } |
1531 | ||
1532 | if (func <= 5) | |
1533 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1534 | else | |
1535 | hw_lock_control_reg = | |
1536 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1537 | ||
1538 | /* Try to acquire the lock */ | |
1539 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); | |
1540 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
1541 | if (lock_status & resource_bit) | |
1542 | return true; | |
1543 | ||
51c1a580 MS |
1544 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1545 | "Failed to get a lock on resource %d\n", resource); | |
72fd0718 VZ |
1546 | return false; |
1547 | } | |
1548 | ||
c9ee9206 VZ |
1549 | /** |
1550 | * bnx2x_get_leader_lock_resource - get the recovery leader resource id | |
1551 | * | |
1552 | * @bp: driver handle | |
1553 | * | |
1554 | * Returns the recovery leader resource id according to the engine this function | |
1555 | * belongs to. Currently only only 2 engines is supported. | |
1556 | */ | |
1557 | static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) | |
1558 | { | |
1559 | if (BP_PATH(bp)) | |
1560 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; | |
1561 | else | |
1562 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; | |
1563 | } | |
1564 | ||
1565 | /** | |
1566 | * bnx2x_trylock_leader_lock- try to aquire a leader lock. | |
1567 | * | |
1568 | * @bp: driver handle | |
1569 | * | |
1570 | * Tries to aquire a leader lock for cuurent engine. | |
1571 | */ | |
1572 | static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) | |
1573 | { | |
1574 | return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1575 | } | |
1576 | ||
993ac7b5 | 1577 | #ifdef BCM_CNIC |
619c5cb6 | 1578 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); |
993ac7b5 | 1579 | #endif |
3196a88a | 1580 | |
619c5cb6 | 1581 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) |
a2fbb9ea ET |
1582 | { |
1583 | struct bnx2x *bp = fp->bp; | |
1584 | int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
1585 | int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
619c5cb6 VZ |
1586 | enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; |
1587 | struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; | |
a2fbb9ea | 1588 | |
34f80b04 | 1589 | DP(BNX2X_MSG_SP, |
a2fbb9ea | 1590 | "fp %d cid %d got ramrod #%d state is %x type is %d\n", |
0626b899 | 1591 | fp->index, cid, command, bp->state, |
34f80b04 | 1592 | rr_cqe->ramrod_cqe.ramrod_type); |
a2fbb9ea | 1593 | |
619c5cb6 VZ |
1594 | switch (command) { |
1595 | case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): | |
d6cae238 | 1596 | DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); |
619c5cb6 VZ |
1597 | drv_cmd = BNX2X_Q_CMD_UPDATE; |
1598 | break; | |
d6cae238 | 1599 | |
619c5cb6 | 1600 | case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): |
d6cae238 | 1601 | DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); |
619c5cb6 | 1602 | drv_cmd = BNX2X_Q_CMD_SETUP; |
a2fbb9ea ET |
1603 | break; |
1604 | ||
6383c0b3 | 1605 | case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): |
51c1a580 | 1606 | DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); |
6383c0b3 AE |
1607 | drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; |
1608 | break; | |
1609 | ||
619c5cb6 | 1610 | case (RAMROD_CMD_ID_ETH_HALT): |
d6cae238 | 1611 | DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); |
619c5cb6 | 1612 | drv_cmd = BNX2X_Q_CMD_HALT; |
a2fbb9ea ET |
1613 | break; |
1614 | ||
619c5cb6 | 1615 | case (RAMROD_CMD_ID_ETH_TERMINATE): |
d6cae238 | 1616 | DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); |
619c5cb6 | 1617 | drv_cmd = BNX2X_Q_CMD_TERMINATE; |
a2fbb9ea ET |
1618 | break; |
1619 | ||
619c5cb6 | 1620 | case (RAMROD_CMD_ID_ETH_EMPTY): |
d6cae238 | 1621 | DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); |
619c5cb6 | 1622 | drv_cmd = BNX2X_Q_CMD_EMPTY; |
993ac7b5 | 1623 | break; |
619c5cb6 VZ |
1624 | |
1625 | default: | |
1626 | BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", | |
1627 | command, fp->index); | |
1628 | return; | |
523224a3 | 1629 | } |
3196a88a | 1630 | |
619c5cb6 VZ |
1631 | if ((drv_cmd != BNX2X_Q_CMD_MAX) && |
1632 | q_obj->complete_cmd(bp, q_obj, drv_cmd)) | |
1633 | /* q_obj->complete_cmd() failure means that this was | |
1634 | * an unexpected completion. | |
1635 | * | |
1636 | * In this case we don't want to increase the bp->spq_left | |
1637 | * because apparently we haven't sent this command the first | |
1638 | * place. | |
1639 | */ | |
1640 | #ifdef BNX2X_STOP_ON_ERROR | |
1641 | bnx2x_panic(); | |
1642 | #else | |
1643 | return; | |
1644 | #endif | |
1645 | ||
8fe23fbd | 1646 | smp_mb__before_atomic_inc(); |
6e30dd4e | 1647 | atomic_inc(&bp->cq_spq_left); |
619c5cb6 VZ |
1648 | /* push the change in bp->spq_left and towards the memory */ |
1649 | smp_mb__after_atomic_inc(); | |
49d66772 | 1650 | |
d6cae238 VZ |
1651 | DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); |
1652 | ||
523224a3 | 1653 | return; |
a2fbb9ea ET |
1654 | } |
1655 | ||
619c5cb6 VZ |
1656 | void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
1657 | u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) | |
1658 | { | |
1659 | u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; | |
1660 | ||
1661 | bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, | |
1662 | start); | |
1663 | } | |
1664 | ||
9f6c9258 | 1665 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) |
a2fbb9ea | 1666 | { |
555f6c78 | 1667 | struct bnx2x *bp = netdev_priv(dev_instance); |
a2fbb9ea | 1668 | u16 status = bnx2x_ack_int(bp); |
34f80b04 | 1669 | u16 mask; |
ca00392c | 1670 | int i; |
6383c0b3 | 1671 | u8 cos; |
a2fbb9ea | 1672 | |
34f80b04 | 1673 | /* Return here if interrupt is shared and it's not for us */ |
a2fbb9ea ET |
1674 | if (unlikely(status == 0)) { |
1675 | DP(NETIF_MSG_INTR, "not our interrupt!\n"); | |
1676 | return IRQ_NONE; | |
1677 | } | |
f5372251 | 1678 | DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); |
a2fbb9ea | 1679 | |
3196a88a EG |
1680 | #ifdef BNX2X_STOP_ON_ERROR |
1681 | if (unlikely(bp->panic)) | |
1682 | return IRQ_HANDLED; | |
1683 | #endif | |
1684 | ||
ec6ba945 | 1685 | for_each_eth_queue(bp, i) { |
ca00392c | 1686 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1687 | |
6383c0b3 | 1688 | mask = 0x2 << (fp->index + CNIC_PRESENT); |
ca00392c | 1689 | if (status & mask) { |
619c5cb6 | 1690 | /* Handle Rx or Tx according to SB id */ |
54b9ddaa | 1691 | prefetch(fp->rx_cons_sb); |
6383c0b3 AE |
1692 | for_each_cos_in_tx_queue(fp, cos) |
1693 | prefetch(fp->txdata[cos].tx_cons_sb); | |
523224a3 | 1694 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
54b9ddaa | 1695 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); |
ca00392c EG |
1696 | status &= ~mask; |
1697 | } | |
a2fbb9ea ET |
1698 | } |
1699 | ||
993ac7b5 | 1700 | #ifdef BCM_CNIC |
523224a3 | 1701 | mask = 0x2; |
993ac7b5 MC |
1702 | if (status & (mask | 0x1)) { |
1703 | struct cnic_ops *c_ops = NULL; | |
1704 | ||
619c5cb6 VZ |
1705 | if (likely(bp->state == BNX2X_STATE_OPEN)) { |
1706 | rcu_read_lock(); | |
1707 | c_ops = rcu_dereference(bp->cnic_ops); | |
1708 | if (c_ops) | |
1709 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
1710 | rcu_read_unlock(); | |
1711 | } | |
993ac7b5 MC |
1712 | |
1713 | status &= ~mask; | |
1714 | } | |
1715 | #endif | |
a2fbb9ea | 1716 | |
34f80b04 | 1717 | if (unlikely(status & 0x1)) { |
1cf167f2 | 1718 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
a2fbb9ea ET |
1719 | |
1720 | status &= ~0x1; | |
1721 | if (!status) | |
1722 | return IRQ_HANDLED; | |
1723 | } | |
1724 | ||
cdaa7cb8 VZ |
1725 | if (unlikely(status)) |
1726 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
34f80b04 | 1727 | status); |
a2fbb9ea | 1728 | |
c18487ee | 1729 | return IRQ_HANDLED; |
a2fbb9ea ET |
1730 | } |
1731 | ||
c18487ee YR |
1732 | /* Link */ |
1733 | ||
1734 | /* | |
1735 | * General service functions | |
1736 | */ | |
a2fbb9ea | 1737 | |
9f6c9258 | 1738 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1739 | { |
1740 | u32 lock_status; | |
1741 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1742 | int func = BP_FUNC(bp); |
1743 | u32 hw_lock_control_reg; | |
c18487ee | 1744 | int cnt; |
a2fbb9ea | 1745 | |
c18487ee YR |
1746 | /* Validating that the resource is within range */ |
1747 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1748 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1749 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1750 | return -EINVAL; | |
1751 | } | |
a2fbb9ea | 1752 | |
4a37fb66 YG |
1753 | if (func <= 5) { |
1754 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1755 | } else { | |
1756 | hw_lock_control_reg = | |
1757 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1758 | } | |
1759 | ||
c18487ee | 1760 | /* Validating that the resource is not already taken */ |
4a37fb66 | 1761 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 1762 | if (lock_status & resource_bit) { |
51c1a580 | 1763 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", |
c18487ee YR |
1764 | lock_status, resource_bit); |
1765 | return -EEXIST; | |
1766 | } | |
a2fbb9ea | 1767 | |
46230476 EG |
1768 | /* Try for 5 second every 5ms */ |
1769 | for (cnt = 0; cnt < 1000; cnt++) { | |
c18487ee | 1770 | /* Try to acquire the lock */ |
4a37fb66 YG |
1771 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
1772 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
c18487ee YR |
1773 | if (lock_status & resource_bit) |
1774 | return 0; | |
a2fbb9ea | 1775 | |
c18487ee | 1776 | msleep(5); |
a2fbb9ea | 1777 | } |
51c1a580 | 1778 | BNX2X_ERR("Timeout\n"); |
c18487ee YR |
1779 | return -EAGAIN; |
1780 | } | |
a2fbb9ea | 1781 | |
c9ee9206 VZ |
1782 | int bnx2x_release_leader_lock(struct bnx2x *bp) |
1783 | { | |
1784 | return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1785 | } | |
1786 | ||
9f6c9258 | 1787 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1788 | { |
1789 | u32 lock_status; | |
1790 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1791 | int func = BP_FUNC(bp); |
1792 | u32 hw_lock_control_reg; | |
a2fbb9ea | 1793 | |
c18487ee YR |
1794 | /* Validating that the resource is within range */ |
1795 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1796 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1797 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1798 | return -EINVAL; | |
1799 | } | |
1800 | ||
4a37fb66 YG |
1801 | if (func <= 5) { |
1802 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1803 | } else { | |
1804 | hw_lock_control_reg = | |
1805 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1806 | } | |
1807 | ||
c18487ee | 1808 | /* Validating that the resource is currently taken */ |
4a37fb66 | 1809 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 1810 | if (!(lock_status & resource_bit)) { |
51c1a580 | 1811 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n", |
c18487ee YR |
1812 | lock_status, resource_bit); |
1813 | return -EFAULT; | |
a2fbb9ea ET |
1814 | } |
1815 | ||
9f6c9258 DK |
1816 | REG_WR(bp, hw_lock_control_reg, resource_bit); |
1817 | return 0; | |
c18487ee | 1818 | } |
a2fbb9ea | 1819 | |
9f6c9258 | 1820 | |
4acac6a5 EG |
1821 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) |
1822 | { | |
1823 | /* The GPIO should be swapped if swap register is set and active */ | |
1824 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
1825 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
1826 | int gpio_shift = gpio_num + | |
1827 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1828 | u32 gpio_mask = (1 << gpio_shift); | |
1829 | u32 gpio_reg; | |
1830 | int value; | |
1831 | ||
1832 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
1833 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1834 | return -EINVAL; | |
1835 | } | |
1836 | ||
1837 | /* read GPIO value */ | |
1838 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1839 | ||
1840 | /* get the requested pin value */ | |
1841 | if ((gpio_reg & gpio_mask) == gpio_mask) | |
1842 | value = 1; | |
1843 | else | |
1844 | value = 0; | |
1845 | ||
1846 | DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); | |
1847 | ||
1848 | return value; | |
1849 | } | |
1850 | ||
17de50b7 | 1851 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
c18487ee YR |
1852 | { |
1853 | /* The GPIO should be swapped if swap register is set and active */ | |
1854 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
17de50b7 | 1855 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
c18487ee YR |
1856 | int gpio_shift = gpio_num + |
1857 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1858 | u32 gpio_mask = (1 << gpio_shift); | |
1859 | u32 gpio_reg; | |
a2fbb9ea | 1860 | |
c18487ee YR |
1861 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
1862 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1863 | return -EINVAL; | |
1864 | } | |
a2fbb9ea | 1865 | |
4a37fb66 | 1866 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
c18487ee YR |
1867 | /* read GPIO and mask except the float bits */ |
1868 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); | |
a2fbb9ea | 1869 | |
c18487ee YR |
1870 | switch (mode) { |
1871 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
51c1a580 MS |
1872 | DP(NETIF_MSG_LINK, |
1873 | "Set GPIO %d (shift %d) -> output low\n", | |
c18487ee YR |
1874 | gpio_num, gpio_shift); |
1875 | /* clear FLOAT and set CLR */ | |
1876 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1877 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); | |
1878 | break; | |
a2fbb9ea | 1879 | |
c18487ee | 1880 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
51c1a580 MS |
1881 | DP(NETIF_MSG_LINK, |
1882 | "Set GPIO %d (shift %d) -> output high\n", | |
c18487ee YR |
1883 | gpio_num, gpio_shift); |
1884 | /* clear FLOAT and set SET */ | |
1885 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1886 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); | |
1887 | break; | |
a2fbb9ea | 1888 | |
17de50b7 | 1889 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
51c1a580 MS |
1890 | DP(NETIF_MSG_LINK, |
1891 | "Set GPIO %d (shift %d) -> input\n", | |
c18487ee YR |
1892 | gpio_num, gpio_shift); |
1893 | /* set FLOAT */ | |
1894 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1895 | break; | |
a2fbb9ea | 1896 | |
c18487ee YR |
1897 | default: |
1898 | break; | |
a2fbb9ea ET |
1899 | } |
1900 | ||
c18487ee | 1901 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
4a37fb66 | 1902 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
f1410647 | 1903 | |
c18487ee | 1904 | return 0; |
a2fbb9ea ET |
1905 | } |
1906 | ||
0d40f0d4 YR |
1907 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) |
1908 | { | |
1909 | u32 gpio_reg = 0; | |
1910 | int rc = 0; | |
1911 | ||
1912 | /* Any port swapping should be handled by caller. */ | |
1913 | ||
1914 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1915 | /* read GPIO and mask except the float bits */ | |
1916 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1917 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1918 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); | |
1919 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); | |
1920 | ||
1921 | switch (mode) { | |
1922 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
1923 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); | |
1924 | /* set CLR */ | |
1925 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); | |
1926 | break; | |
1927 | ||
1928 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: | |
1929 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); | |
1930 | /* set SET */ | |
1931 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); | |
1932 | break; | |
1933 | ||
1934 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: | |
1935 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); | |
1936 | /* set FLOAT */ | |
1937 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1938 | break; | |
1939 | ||
1940 | default: | |
1941 | BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); | |
1942 | rc = -EINVAL; | |
1943 | break; | |
1944 | } | |
1945 | ||
1946 | if (rc == 0) | |
1947 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); | |
1948 | ||
1949 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1950 | ||
1951 | return rc; | |
1952 | } | |
1953 | ||
4acac6a5 EG |
1954 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
1955 | { | |
1956 | /* The GPIO should be swapped if swap register is set and active */ | |
1957 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
1958 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
1959 | int gpio_shift = gpio_num + | |
1960 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1961 | u32 gpio_mask = (1 << gpio_shift); | |
1962 | u32 gpio_reg; | |
1963 | ||
1964 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
1965 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1966 | return -EINVAL; | |
1967 | } | |
1968 | ||
1969 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1970 | /* read GPIO int */ | |
1971 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); | |
1972 | ||
1973 | switch (mode) { | |
1974 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: | |
51c1a580 MS |
1975 | DP(NETIF_MSG_LINK, |
1976 | "Clear GPIO INT %d (shift %d) -> output low\n", | |
1977 | gpio_num, gpio_shift); | |
4acac6a5 EG |
1978 | /* clear SET and set CLR */ |
1979 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
1980 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
1981 | break; | |
1982 | ||
1983 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: | |
51c1a580 MS |
1984 | DP(NETIF_MSG_LINK, |
1985 | "Set GPIO INT %d (shift %d) -> output high\n", | |
1986 | gpio_num, gpio_shift); | |
4acac6a5 EG |
1987 | /* clear CLR and set SET */ |
1988 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
1989 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
1990 | break; | |
1991 | ||
1992 | default: | |
1993 | break; | |
1994 | } | |
1995 | ||
1996 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); | |
1997 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1998 | ||
1999 | return 0; | |
2000 | } | |
2001 | ||
c18487ee | 2002 | static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) |
a2fbb9ea | 2003 | { |
c18487ee YR |
2004 | u32 spio_mask = (1 << spio_num); |
2005 | u32 spio_reg; | |
a2fbb9ea | 2006 | |
c18487ee YR |
2007 | if ((spio_num < MISC_REGISTERS_SPIO_4) || |
2008 | (spio_num > MISC_REGISTERS_SPIO_7)) { | |
2009 | BNX2X_ERR("Invalid SPIO %d\n", spio_num); | |
2010 | return -EINVAL; | |
a2fbb9ea ET |
2011 | } |
2012 | ||
4a37fb66 | 2013 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee YR |
2014 | /* read SPIO and mask except the float bits */ |
2015 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); | |
a2fbb9ea | 2016 | |
c18487ee | 2017 | switch (mode) { |
6378c025 | 2018 | case MISC_REGISTERS_SPIO_OUTPUT_LOW: |
51c1a580 | 2019 | DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num); |
c18487ee YR |
2020 | /* clear FLOAT and set CLR */ |
2021 | spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2022 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); | |
2023 | break; | |
a2fbb9ea | 2024 | |
6378c025 | 2025 | case MISC_REGISTERS_SPIO_OUTPUT_HIGH: |
51c1a580 | 2026 | DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num); |
c18487ee YR |
2027 | /* clear FLOAT and set SET */ |
2028 | spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2029 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); | |
2030 | break; | |
a2fbb9ea | 2031 | |
c18487ee | 2032 | case MISC_REGISTERS_SPIO_INPUT_HI_Z: |
51c1a580 | 2033 | DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num); |
c18487ee YR |
2034 | /* set FLOAT */ |
2035 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2036 | break; | |
a2fbb9ea | 2037 | |
c18487ee YR |
2038 | default: |
2039 | break; | |
a2fbb9ea ET |
2040 | } |
2041 | ||
c18487ee | 2042 | REG_WR(bp, MISC_REG_SPIO, spio_reg); |
4a37fb66 | 2043 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2044 | |
a2fbb9ea ET |
2045 | return 0; |
2046 | } | |
2047 | ||
9f6c9258 | 2048 | void bnx2x_calc_fc_adv(struct bnx2x *bp) |
a2fbb9ea | 2049 | { |
a22f0788 | 2050 | u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
ad33ea3a EG |
2051 | switch (bp->link_vars.ieee_fc & |
2052 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { | |
c18487ee | 2053 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: |
a22f0788 | 2054 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2055 | ADVERTISED_Pause); |
c18487ee | 2056 | break; |
356e2385 | 2057 | |
c18487ee | 2058 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: |
a22f0788 | 2059 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | |
f85582f8 | 2060 | ADVERTISED_Pause); |
c18487ee | 2061 | break; |
356e2385 | 2062 | |
c18487ee | 2063 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: |
a22f0788 | 2064 | bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; |
c18487ee | 2065 | break; |
356e2385 | 2066 | |
c18487ee | 2067 | default: |
a22f0788 | 2068 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2069 | ADVERTISED_Pause); |
c18487ee YR |
2070 | break; |
2071 | } | |
2072 | } | |
f1410647 | 2073 | |
9f6c9258 | 2074 | u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) |
c18487ee | 2075 | { |
19680c48 EG |
2076 | if (!BP_NOMCP(bp)) { |
2077 | u8 rc; | |
a22f0788 YR |
2078 | int cfx_idx = bnx2x_get_link_cfg_idx(bp); |
2079 | u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; | |
1cb0c788 YR |
2080 | /* |
2081 | * Initialize link parameters structure variables | |
2082 | * It is recommended to turn off RX FC for jumbo frames | |
2083 | * for better performance | |
2084 | */ | |
2085 | if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) | |
c0700f90 | 2086 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; |
8c99e7b0 | 2087 | else |
c0700f90 | 2088 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; |
a2fbb9ea | 2089 | |
4a37fb66 | 2090 | bnx2x_acquire_phy_lock(bp); |
b5bf9068 | 2091 | |
a22f0788 | 2092 | if (load_mode == LOAD_DIAG) { |
1cb0c788 YR |
2093 | struct link_params *lp = &bp->link_params; |
2094 | lp->loopback_mode = LOOPBACK_XGXS; | |
2095 | /* do PHY loopback at 10G speed, if possible */ | |
2096 | if (lp->req_line_speed[cfx_idx] < SPEED_10000) { | |
2097 | if (lp->speed_cap_mask[cfx_idx] & | |
2098 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
2099 | lp->req_line_speed[cfx_idx] = | |
2100 | SPEED_10000; | |
2101 | else | |
2102 | lp->req_line_speed[cfx_idx] = | |
2103 | SPEED_1000; | |
2104 | } | |
a22f0788 | 2105 | } |
b5bf9068 | 2106 | |
19680c48 | 2107 | rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
b5bf9068 | 2108 | |
4a37fb66 | 2109 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2110 | |
3c96c68b EG |
2111 | bnx2x_calc_fc_adv(bp); |
2112 | ||
b5bf9068 EG |
2113 | if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { |
2114 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
19680c48 | 2115 | bnx2x_link_report(bp); |
3deb8167 YR |
2116 | } else |
2117 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
a22f0788 | 2118 | bp->link_params.req_line_speed[cfx_idx] = req_line_speed; |
19680c48 EG |
2119 | return rc; |
2120 | } | |
f5372251 | 2121 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
19680c48 | 2122 | return -EINVAL; |
a2fbb9ea ET |
2123 | } |
2124 | ||
9f6c9258 | 2125 | void bnx2x_link_set(struct bnx2x *bp) |
a2fbb9ea | 2126 | { |
19680c48 | 2127 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2128 | bnx2x_acquire_phy_lock(bp); |
54c2fb78 | 2129 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); |
19680c48 | 2130 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2131 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2132 | |
19680c48 EG |
2133 | bnx2x_calc_fc_adv(bp); |
2134 | } else | |
f5372251 | 2135 | BNX2X_ERR("Bootcode is missing - can not set link\n"); |
c18487ee | 2136 | } |
a2fbb9ea | 2137 | |
c18487ee YR |
2138 | static void bnx2x__link_reset(struct bnx2x *bp) |
2139 | { | |
19680c48 | 2140 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2141 | bnx2x_acquire_phy_lock(bp); |
589abe3a | 2142 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); |
4a37fb66 | 2143 | bnx2x_release_phy_lock(bp); |
19680c48 | 2144 | } else |
f5372251 | 2145 | BNX2X_ERR("Bootcode is missing - can not reset link\n"); |
c18487ee | 2146 | } |
a2fbb9ea | 2147 | |
a22f0788 | 2148 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) |
c18487ee | 2149 | { |
2145a920 | 2150 | u8 rc = 0; |
a2fbb9ea | 2151 | |
2145a920 VZ |
2152 | if (!BP_NOMCP(bp)) { |
2153 | bnx2x_acquire_phy_lock(bp); | |
a22f0788 YR |
2154 | rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, |
2155 | is_serdes); | |
2145a920 VZ |
2156 | bnx2x_release_phy_lock(bp); |
2157 | } else | |
2158 | BNX2X_ERR("Bootcode is missing - can not test link\n"); | |
a2fbb9ea | 2159 | |
c18487ee YR |
2160 | return rc; |
2161 | } | |
a2fbb9ea | 2162 | |
8a1c38d1 | 2163 | static void bnx2x_init_port_minmax(struct bnx2x *bp) |
34f80b04 | 2164 | { |
8a1c38d1 EG |
2165 | u32 r_param = bp->link_vars.line_speed / 8; |
2166 | u32 fair_periodic_timeout_usec; | |
2167 | u32 t_fair; | |
34f80b04 | 2168 | |
8a1c38d1 EG |
2169 | memset(&(bp->cmng.rs_vars), 0, |
2170 | sizeof(struct rate_shaping_vars_per_port)); | |
2171 | memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); | |
34f80b04 | 2172 | |
8a1c38d1 EG |
2173 | /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ |
2174 | bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; | |
34f80b04 | 2175 | |
8a1c38d1 EG |
2176 | /* this is the threshold below which no timer arming will occur |
2177 | 1.25 coefficient is for the threshold to be a little bigger | |
2178 | than the real time, to compensate for timer in-accuracy */ | |
2179 | bp->cmng.rs_vars.rs_threshold = | |
34f80b04 EG |
2180 | (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; |
2181 | ||
8a1c38d1 EG |
2182 | /* resolution of fairness timer */ |
2183 | fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; | |
2184 | /* for 10G it is 1000usec. for 1G it is 10000usec. */ | |
2185 | t_fair = T_FAIR_COEF / bp->link_vars.line_speed; | |
34f80b04 | 2186 | |
8a1c38d1 EG |
2187 | /* this is the threshold below which we won't arm the timer anymore */ |
2188 | bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; | |
34f80b04 | 2189 | |
8a1c38d1 EG |
2190 | /* we multiply by 1e3/8 to get bytes/msec. |
2191 | We don't want the credits to pass a credit | |
2192 | of the t_fair*FAIR_MEM (algorithm resolution) */ | |
2193 | bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; | |
2194 | /* since each tick is 4 usec */ | |
2195 | bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; | |
34f80b04 EG |
2196 | } |
2197 | ||
2691d51d EG |
2198 | /* Calculates the sum of vn_min_rates. |
2199 | It's needed for further normalizing of the min_rates. | |
2200 | Returns: | |
2201 | sum of vn_min_rates. | |
2202 | or | |
2203 | 0 - if all the min_rates are 0. | |
2204 | In the later case fainess algorithm should be deactivated. | |
2205 | If not all min_rates are zero then those that are zeroes will be set to 1. | |
2206 | */ | |
2207 | static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) | |
2208 | { | |
2209 | int all_zero = 1; | |
2691d51d EG |
2210 | int vn; |
2211 | ||
2212 | bp->vn_weight_sum = 0; | |
3395a033 | 2213 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
f2e0899f | 2214 | u32 vn_cfg = bp->mf_config[vn]; |
2691d51d EG |
2215 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2216 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
2217 | ||
2218 | /* Skip hidden vns */ | |
2219 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) | |
2220 | continue; | |
2221 | ||
2222 | /* If min rate is zero - set it to 1 */ | |
2223 | if (!vn_min_rate) | |
2224 | vn_min_rate = DEF_MIN_RATE; | |
2225 | else | |
2226 | all_zero = 0; | |
2227 | ||
2228 | bp->vn_weight_sum += vn_min_rate; | |
2229 | } | |
2230 | ||
30ae438b DK |
2231 | /* if ETS or all min rates are zeros - disable fairness */ |
2232 | if (BNX2X_IS_ETS_ENABLED(bp)) { | |
2233 | bp->cmng.flags.cmng_enables &= | |
2234 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; | |
2235 | DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); | |
2236 | } else if (all_zero) { | |
b015e3d1 EG |
2237 | bp->cmng.flags.cmng_enables &= |
2238 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; | |
2239 | DP(NETIF_MSG_IFUP, "All MIN values are zeroes" | |
2240 | " fairness will be disabled\n"); | |
2241 | } else | |
2242 | bp->cmng.flags.cmng_enables |= | |
2243 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; | |
2691d51d EG |
2244 | } |
2245 | ||
f2e0899f | 2246 | static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) |
34f80b04 EG |
2247 | { |
2248 | struct rate_shaping_vars_per_vn m_rs_vn; | |
2249 | struct fairness_vars_per_vn m_fair_vn; | |
f2e0899f | 2250 | u32 vn_cfg = bp->mf_config[vn]; |
3395a033 | 2251 | int func = func_by_vn(bp, vn); |
34f80b04 EG |
2252 | u16 vn_min_rate, vn_max_rate; |
2253 | int i; | |
2254 | ||
2255 | /* If function is hidden - set min and max to zeroes */ | |
2256 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { | |
2257 | vn_min_rate = 0; | |
2258 | vn_max_rate = 0; | |
2259 | ||
2260 | } else { | |
faa6fcbb DK |
2261 | u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); |
2262 | ||
34f80b04 EG |
2263 | vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2264 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
faa6fcbb DK |
2265 | /* If fairness is enabled (not all min rates are zeroes) and |
2266 | if current min rate is zero - set it to 1. | |
2267 | This is a requirement of the algorithm. */ | |
f2e0899f | 2268 | if (bp->vn_weight_sum && (vn_min_rate == 0)) |
34f80b04 | 2269 | vn_min_rate = DEF_MIN_RATE; |
faa6fcbb DK |
2270 | |
2271 | if (IS_MF_SI(bp)) | |
2272 | /* maxCfg in percents of linkspeed */ | |
2273 | vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; | |
2274 | else | |
2275 | /* maxCfg is absolute in 100Mb units */ | |
2276 | vn_max_rate = maxCfg * 100; | |
34f80b04 | 2277 | } |
f85582f8 | 2278 | |
8a1c38d1 | 2279 | DP(NETIF_MSG_IFUP, |
b015e3d1 | 2280 | "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", |
8a1c38d1 | 2281 | func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); |
34f80b04 EG |
2282 | |
2283 | memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); | |
2284 | memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); | |
2285 | ||
2286 | /* global vn counter - maximal Mbps for this vn */ | |
2287 | m_rs_vn.vn_counter.rate = vn_max_rate; | |
2288 | ||
2289 | /* quota - number of bytes transmitted in this period */ | |
2290 | m_rs_vn.vn_counter.quota = | |
2291 | (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; | |
2292 | ||
8a1c38d1 | 2293 | if (bp->vn_weight_sum) { |
34f80b04 EG |
2294 | /* credit for each period of the fairness algorithm: |
2295 | number of bytes in T_FAIR (the vn share the port rate). | |
8a1c38d1 EG |
2296 | vn_weight_sum should not be larger than 10000, thus |
2297 | T_FAIR_COEF / (8 * vn_weight_sum) will always be greater | |
2298 | than zero */ | |
34f80b04 | 2299 | m_fair_vn.vn_credit_delta = |
cdaa7cb8 VZ |
2300 | max_t(u32, (vn_min_rate * (T_FAIR_COEF / |
2301 | (8 * bp->vn_weight_sum))), | |
ff80ee02 DK |
2302 | (bp->cmng.fair_vars.fair_threshold + |
2303 | MIN_ABOVE_THRESH)); | |
cdaa7cb8 | 2304 | DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", |
34f80b04 EG |
2305 | m_fair_vn.vn_credit_delta); |
2306 | } | |
2307 | ||
34f80b04 EG |
2308 | /* Store it to internal memory */ |
2309 | for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) | |
2310 | REG_WR(bp, BAR_XSTRORM_INTMEM + | |
2311 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4, | |
2312 | ((u32 *)(&m_rs_vn))[i]); | |
2313 | ||
2314 | for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) | |
2315 | REG_WR(bp, BAR_XSTRORM_INTMEM + | |
2316 | XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, | |
2317 | ((u32 *)(&m_fair_vn))[i]); | |
2318 | } | |
f85582f8 | 2319 | |
523224a3 DK |
2320 | static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) |
2321 | { | |
2322 | if (CHIP_REV_IS_SLOW(bp)) | |
2323 | return CMNG_FNS_NONE; | |
fb3bff17 | 2324 | if (IS_MF(bp)) |
523224a3 DK |
2325 | return CMNG_FNS_MINMAX; |
2326 | ||
2327 | return CMNG_FNS_NONE; | |
2328 | } | |
2329 | ||
2ae17f66 | 2330 | void bnx2x_read_mf_cfg(struct bnx2x *bp) |
523224a3 | 2331 | { |
0793f83f | 2332 | int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); |
523224a3 DK |
2333 | |
2334 | if (BP_NOMCP(bp)) | |
2335 | return; /* what should be the default bvalue in this case */ | |
2336 | ||
0793f83f DK |
2337 | /* For 2 port configuration the absolute function number formula |
2338 | * is: | |
2339 | * abs_func = 2 * vn + BP_PORT + BP_PATH | |
2340 | * | |
2341 | * and there are 4 functions per port | |
2342 | * | |
2343 | * For 4 port configuration it is | |
2344 | * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH | |
2345 | * | |
2346 | * and there are 2 functions per port | |
2347 | */ | |
3395a033 | 2348 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
0793f83f DK |
2349 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
2350 | ||
2351 | if (func >= E1H_FUNC_MAX) | |
2352 | break; | |
2353 | ||
f2e0899f | 2354 | bp->mf_config[vn] = |
523224a3 DK |
2355 | MF_CFG_RD(bp, func_mf_config[func].config); |
2356 | } | |
2357 | } | |
2358 | ||
2359 | static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |
2360 | { | |
2361 | ||
2362 | if (cmng_type == CMNG_FNS_MINMAX) { | |
2363 | int vn; | |
2364 | ||
2365 | /* clear cmng_enables */ | |
2366 | bp->cmng.flags.cmng_enables = 0; | |
2367 | ||
2368 | /* read mf conf from shmem */ | |
2369 | if (read_cfg) | |
2370 | bnx2x_read_mf_cfg(bp); | |
2371 | ||
2372 | /* Init rate shaping and fairness contexts */ | |
2373 | bnx2x_init_port_minmax(bp); | |
2374 | ||
2375 | /* vn_weight_sum and enable fairness if not 0 */ | |
2376 | bnx2x_calc_vn_weight_sum(bp); | |
2377 | ||
2378 | /* calculate and set min-max rate for each vn */ | |
c4154f25 | 2379 | if (bp->port.pmf) |
3395a033 | 2380 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) |
c4154f25 | 2381 | bnx2x_init_vn_minmax(bp, vn); |
523224a3 DK |
2382 | |
2383 | /* always enable rate shaping and fairness */ | |
2384 | bp->cmng.flags.cmng_enables |= | |
2385 | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; | |
2386 | if (!bp->vn_weight_sum) | |
2387 | DP(NETIF_MSG_IFUP, "All MIN values are zeroes" | |
2388 | " fairness will be disabled\n"); | |
2389 | return; | |
2390 | } | |
2391 | ||
2392 | /* rate shaping and fairness are disabled */ | |
2393 | DP(NETIF_MSG_IFUP, | |
2394 | "rate shaping and fairness are disabled\n"); | |
2395 | } | |
34f80b04 | 2396 | |
c18487ee YR |
2397 | /* This function is called upon link interrupt */ |
2398 | static void bnx2x_link_attn(struct bnx2x *bp) | |
2399 | { | |
bb2a0f7a YG |
2400 | /* Make sure that we are synced with the current statistics */ |
2401 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2402 | ||
c18487ee | 2403 | bnx2x_link_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2404 | |
bb2a0f7a YG |
2405 | if (bp->link_vars.link_up) { |
2406 | ||
1c06328c | 2407 | /* dropless flow control */ |
f2e0899f | 2408 | if (!CHIP_IS_E1(bp) && bp->dropless_fc) { |
1c06328c EG |
2409 | int port = BP_PORT(bp); |
2410 | u32 pause_enabled = 0; | |
2411 | ||
2412 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
2413 | pause_enabled = 1; | |
2414 | ||
2415 | REG_WR(bp, BAR_USTRORM_INTMEM + | |
ca00392c | 2416 | USTORM_ETH_PAUSE_ENABLED_OFFSET(port), |
1c06328c EG |
2417 | pause_enabled); |
2418 | } | |
2419 | ||
619c5cb6 | 2420 | if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { |
bb2a0f7a YG |
2421 | struct host_port_stats *pstats; |
2422 | ||
2423 | pstats = bnx2x_sp(bp, port_stats); | |
619c5cb6 | 2424 | /* reset old mac stats */ |
bb2a0f7a YG |
2425 | memset(&(pstats->mac_stx[0]), 0, |
2426 | sizeof(struct mac_stx)); | |
2427 | } | |
f34d28ea | 2428 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a YG |
2429 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
2430 | } | |
2431 | ||
f2e0899f DK |
2432 | if (bp->link_vars.link_up && bp->link_vars.line_speed) { |
2433 | int cmng_fns = bnx2x_get_cmng_fns_mode(bp); | |
8a1c38d1 | 2434 | |
f2e0899f DK |
2435 | if (cmng_fns != CMNG_FNS_NONE) { |
2436 | bnx2x_cmng_fns_init(bp, false, cmng_fns); | |
2437 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2438 | } else | |
2439 | /* rate shaping and fairness are disabled */ | |
2440 | DP(NETIF_MSG_IFUP, | |
2441 | "single function mode without fairness\n"); | |
34f80b04 | 2442 | } |
9fdc3e95 | 2443 | |
2ae17f66 VZ |
2444 | __bnx2x_link_report(bp); |
2445 | ||
9fdc3e95 DK |
2446 | if (IS_MF(bp)) |
2447 | bnx2x_link_sync_notify(bp); | |
c18487ee | 2448 | } |
a2fbb9ea | 2449 | |
9f6c9258 | 2450 | void bnx2x__link_status_update(struct bnx2x *bp) |
c18487ee | 2451 | { |
2ae17f66 | 2452 | if (bp->state != BNX2X_STATE_OPEN) |
c18487ee | 2453 | return; |
a2fbb9ea | 2454 | |
00253a8c DK |
2455 | /* read updated dcb configuration */ |
2456 | bnx2x_dcbx_pmf_update(bp); | |
2457 | ||
c18487ee | 2458 | bnx2x_link_status_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2459 | |
bb2a0f7a YG |
2460 | if (bp->link_vars.link_up) |
2461 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
2462 | else | |
2463 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2464 | ||
c18487ee YR |
2465 | /* indicate link status */ |
2466 | bnx2x_link_report(bp); | |
a2fbb9ea | 2467 | } |
a2fbb9ea | 2468 | |
34f80b04 EG |
2469 | static void bnx2x_pmf_update(struct bnx2x *bp) |
2470 | { | |
2471 | int port = BP_PORT(bp); | |
2472 | u32 val; | |
2473 | ||
2474 | bp->port.pmf = 1; | |
51c1a580 | 2475 | DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); |
34f80b04 | 2476 | |
3deb8167 YR |
2477 | /* |
2478 | * We need the mb() to ensure the ordering between the writing to | |
2479 | * bp->port.pmf here and reading it from the bnx2x_periodic_task(). | |
2480 | */ | |
2481 | smp_mb(); | |
2482 | ||
2483 | /* queue a periodic task */ | |
2484 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
2485 | ||
ef01854e DK |
2486 | bnx2x_dcbx_pmf_update(bp); |
2487 | ||
34f80b04 | 2488 | /* enable nig attention */ |
3395a033 | 2489 | val = (0xff0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
2490 | if (bp->common.int_block == INT_BLOCK_HC) { |
2491 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
2492 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
619c5cb6 | 2493 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2494 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
2495 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
2496 | } | |
bb2a0f7a YG |
2497 | |
2498 | bnx2x_stats_handle(bp, STATS_EVENT_PMF); | |
34f80b04 EG |
2499 | } |
2500 | ||
c18487ee | 2501 | /* end of Link */ |
a2fbb9ea ET |
2502 | |
2503 | /* slow path */ | |
2504 | ||
2505 | /* | |
2506 | * General service functions | |
2507 | */ | |
2508 | ||
2691d51d | 2509 | /* send the MCP a request, block until there is a reply */ |
a22f0788 | 2510 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) |
2691d51d | 2511 | { |
f2e0899f | 2512 | int mb_idx = BP_FW_MB_IDX(bp); |
a5971d43 | 2513 | u32 seq; |
2691d51d EG |
2514 | u32 rc = 0; |
2515 | u32 cnt = 1; | |
2516 | u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; | |
2517 | ||
c4ff7cbf | 2518 | mutex_lock(&bp->fw_mb_mutex); |
a5971d43 | 2519 | seq = ++bp->fw_seq; |
f2e0899f DK |
2520 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); |
2521 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); | |
2522 | ||
754a2f52 DK |
2523 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", |
2524 | (command | seq), param); | |
2691d51d EG |
2525 | |
2526 | do { | |
2527 | /* let the FW do it's magic ... */ | |
2528 | msleep(delay); | |
2529 | ||
f2e0899f | 2530 | rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); |
2691d51d | 2531 | |
c4ff7cbf EG |
2532 | /* Give the FW up to 5 second (500*10ms) */ |
2533 | } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); | |
2691d51d EG |
2534 | |
2535 | DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", | |
2536 | cnt*delay, rc, seq); | |
2537 | ||
2538 | /* is this a reply to our command? */ | |
2539 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) | |
2540 | rc &= FW_MSG_CODE_MASK; | |
2541 | else { | |
2542 | /* FW BUG! */ | |
2543 | BNX2X_ERR("FW failed to respond!\n"); | |
2544 | bnx2x_fw_dump(bp); | |
2545 | rc = 0; | |
2546 | } | |
c4ff7cbf | 2547 | mutex_unlock(&bp->fw_mb_mutex); |
2691d51d EG |
2548 | |
2549 | return rc; | |
2550 | } | |
2551 | ||
ec6ba945 | 2552 | |
619c5cb6 VZ |
2553 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) |
2554 | { | |
2555 | if (CHIP_IS_E1x(bp)) { | |
2556 | struct tstorm_eth_function_common_config tcfg = {0}; | |
2557 | ||
2558 | storm_memset_func_cfg(bp, &tcfg, p->func_id); | |
2559 | } | |
2560 | ||
2561 | /* Enable the function in the FW */ | |
2562 | storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); | |
2563 | storm_memset_func_en(bp, p->func_id, 1); | |
2564 | ||
2565 | /* spq */ | |
2566 | if (p->func_flgs & FUNC_FLG_SPQ) { | |
2567 | storm_memset_spq_addr(bp, p->spq_map, p->func_id); | |
2568 | REG_WR(bp, XSEM_REG_FAST_MEMORY + | |
2569 | XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); | |
2570 | } | |
2571 | } | |
2572 | ||
6383c0b3 AE |
2573 | /** |
2574 | * bnx2x_get_tx_only_flags - Return common flags | |
2575 | * | |
2576 | * @bp device handle | |
2577 | * @fp queue handle | |
2578 | * @zero_stats TRUE if statistics zeroing is needed | |
2579 | * | |
2580 | * Return the flags that are common for the Tx-only and not normal connections. | |
2581 | */ | |
2582 | static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, | |
2583 | struct bnx2x_fastpath *fp, | |
2584 | bool zero_stats) | |
28912902 | 2585 | { |
619c5cb6 VZ |
2586 | unsigned long flags = 0; |
2587 | ||
2588 | /* PF driver will always initialize the Queue to an ACTIVE state */ | |
2589 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); | |
28912902 | 2590 | |
6383c0b3 AE |
2591 | /* tx only connections collect statistics (on the same index as the |
2592 | * parent connection). The statistics are zeroed when the parent | |
2593 | * connection is initialized. | |
2594 | */ | |
50f0a562 BW |
2595 | |
2596 | __set_bit(BNX2X_Q_FLG_STATS, &flags); | |
2597 | if (zero_stats) | |
2598 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); | |
2599 | ||
6383c0b3 AE |
2600 | |
2601 | return flags; | |
2602 | } | |
2603 | ||
2604 | static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, | |
2605 | struct bnx2x_fastpath *fp, | |
2606 | bool leading) | |
2607 | { | |
2608 | unsigned long flags = 0; | |
2609 | ||
619c5cb6 VZ |
2610 | /* calculate other queue flags */ |
2611 | if (IS_MF_SD(bp)) | |
2612 | __set_bit(BNX2X_Q_FLG_OV, &flags); | |
28912902 | 2613 | |
619c5cb6 VZ |
2614 | if (IS_FCOE_FP(fp)) |
2615 | __set_bit(BNX2X_Q_FLG_FCOE, &flags); | |
523224a3 | 2616 | |
f5219d8e | 2617 | if (!fp->disable_tpa) { |
619c5cb6 | 2618 | __set_bit(BNX2X_Q_FLG_TPA, &flags); |
f5219d8e | 2619 | __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); |
621b4d66 DK |
2620 | if (fp->mode == TPA_MODE_GRO) |
2621 | __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); | |
f5219d8e | 2622 | } |
619c5cb6 | 2623 | |
619c5cb6 VZ |
2624 | if (leading) { |
2625 | __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); | |
2626 | __set_bit(BNX2X_Q_FLG_MCAST, &flags); | |
2627 | } | |
523224a3 | 2628 | |
619c5cb6 VZ |
2629 | /* Always set HW VLAN stripping */ |
2630 | __set_bit(BNX2X_Q_FLG_VLAN, &flags); | |
523224a3 | 2631 | |
6383c0b3 AE |
2632 | |
2633 | return flags | bnx2x_get_common_flags(bp, fp, true); | |
523224a3 DK |
2634 | } |
2635 | ||
619c5cb6 | 2636 | static void bnx2x_pf_q_prep_general(struct bnx2x *bp, |
6383c0b3 AE |
2637 | struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, |
2638 | u8 cos) | |
619c5cb6 VZ |
2639 | { |
2640 | gen_init->stat_id = bnx2x_stats_id(fp); | |
2641 | gen_init->spcl_id = fp->cl_id; | |
2642 | ||
2643 | /* Always use mini-jumbo MTU for FCoE L2 ring */ | |
2644 | if (IS_FCOE_FP(fp)) | |
2645 | gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; | |
2646 | else | |
2647 | gen_init->mtu = bp->dev->mtu; | |
6383c0b3 AE |
2648 | |
2649 | gen_init->cos = cos; | |
619c5cb6 VZ |
2650 | } |
2651 | ||
2652 | static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |
523224a3 | 2653 | struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, |
619c5cb6 | 2654 | struct bnx2x_rxq_setup_params *rxq_init) |
523224a3 | 2655 | { |
619c5cb6 | 2656 | u8 max_sge = 0; |
523224a3 DK |
2657 | u16 sge_sz = 0; |
2658 | u16 tpa_agg_size = 0; | |
2659 | ||
523224a3 | 2660 | if (!fp->disable_tpa) { |
dfacf138 DK |
2661 | pause->sge_th_lo = SGE_TH_LO(bp); |
2662 | pause->sge_th_hi = SGE_TH_HI(bp); | |
2663 | ||
2664 | /* validate SGE ring has enough to cross high threshold */ | |
2665 | WARN_ON(bp->dropless_fc && | |
2666 | pause->sge_th_hi + FW_PREFETCH_CNT > | |
2667 | MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); | |
2668 | ||
523224a3 DK |
2669 | tpa_agg_size = min_t(u32, |
2670 | (min_t(u32, 8, MAX_SKB_FRAGS) * | |
2671 | SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); | |
2672 | max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> | |
2673 | SGE_PAGE_SHIFT; | |
2674 | max_sge = ((max_sge + PAGES_PER_SGE - 1) & | |
2675 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; | |
2676 | sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, | |
2677 | 0xffff); | |
2678 | } | |
2679 | ||
2680 | /* pause - not for e1 */ | |
2681 | if (!CHIP_IS_E1(bp)) { | |
dfacf138 DK |
2682 | pause->bd_th_lo = BD_TH_LO(bp); |
2683 | pause->bd_th_hi = BD_TH_HI(bp); | |
2684 | ||
2685 | pause->rcq_th_lo = RCQ_TH_LO(bp); | |
2686 | pause->rcq_th_hi = RCQ_TH_HI(bp); | |
2687 | /* | |
2688 | * validate that rings have enough entries to cross | |
2689 | * high thresholds | |
2690 | */ | |
2691 | WARN_ON(bp->dropless_fc && | |
2692 | pause->bd_th_hi + FW_PREFETCH_CNT > | |
2693 | bp->rx_ring_size); | |
2694 | WARN_ON(bp->dropless_fc && | |
2695 | pause->rcq_th_hi + FW_PREFETCH_CNT > | |
2696 | NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); | |
619c5cb6 | 2697 | |
523224a3 DK |
2698 | pause->pri_map = 1; |
2699 | } | |
2700 | ||
2701 | /* rxq setup */ | |
523224a3 DK |
2702 | rxq_init->dscr_map = fp->rx_desc_mapping; |
2703 | rxq_init->sge_map = fp->rx_sge_mapping; | |
2704 | rxq_init->rcq_map = fp->rx_comp_mapping; | |
2705 | rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; | |
a8c94b91 | 2706 | |
619c5cb6 VZ |
2707 | /* This should be a maximum number of data bytes that may be |
2708 | * placed on the BD (not including paddings). | |
2709 | */ | |
e52fcb24 ED |
2710 | rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - |
2711 | BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; | |
a8c94b91 | 2712 | |
523224a3 | 2713 | rxq_init->cl_qzone_id = fp->cl_qzone_id; |
523224a3 DK |
2714 | rxq_init->tpa_agg_sz = tpa_agg_size; |
2715 | rxq_init->sge_buf_sz = sge_sz; | |
2716 | rxq_init->max_sges_pkt = max_sge; | |
619c5cb6 | 2717 | rxq_init->rss_engine_id = BP_FUNC(bp); |
259afa1f | 2718 | rxq_init->mcast_engine_id = BP_FUNC(bp); |
619c5cb6 VZ |
2719 | |
2720 | /* Maximum number or simultaneous TPA aggregation for this Queue. | |
2721 | * | |
2722 | * For PF Clients it should be the maximum avaliable number. | |
2723 | * VF driver(s) may want to define it to a smaller value. | |
2724 | */ | |
dfacf138 | 2725 | rxq_init->max_tpa_queues = MAX_AGG_QS(bp); |
619c5cb6 | 2726 | |
523224a3 DK |
2727 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
2728 | rxq_init->fw_sb_id = fp->fw_sb_id; | |
2729 | ||
ec6ba945 VZ |
2730 | if (IS_FCOE_FP(fp)) |
2731 | rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; | |
2732 | else | |
6383c0b3 | 2733 | rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
523224a3 DK |
2734 | } |
2735 | ||
619c5cb6 | 2736 | static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, |
6383c0b3 AE |
2737 | struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, |
2738 | u8 cos) | |
523224a3 | 2739 | { |
6383c0b3 AE |
2740 | txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; |
2741 | txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; | |
523224a3 DK |
2742 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; |
2743 | txq_init->fw_sb_id = fp->fw_sb_id; | |
ec6ba945 | 2744 | |
619c5cb6 VZ |
2745 | /* |
2746 | * set the tss leading client id for TX classfication == | |
2747 | * leading RSS client id | |
2748 | */ | |
2749 | txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); | |
2750 | ||
ec6ba945 VZ |
2751 | if (IS_FCOE_FP(fp)) { |
2752 | txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; | |
2753 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; | |
2754 | } | |
523224a3 DK |
2755 | } |
2756 | ||
8d96286a | 2757 | static void bnx2x_pf_init(struct bnx2x *bp) |
523224a3 DK |
2758 | { |
2759 | struct bnx2x_func_init_params func_init = {0}; | |
523224a3 DK |
2760 | struct event_ring_data eq_data = { {0} }; |
2761 | u16 flags; | |
2762 | ||
619c5cb6 | 2763 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2764 | /* reset IGU PF statistics: MSIX + ATTN */ |
2765 | /* PF */ | |
2766 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
2767 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
2768 | (CHIP_MODE_IS_4_PORT(bp) ? | |
2769 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
2770 | /* ATTN */ | |
2771 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
2772 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
2773 | BNX2X_IGU_STAS_MSG_PF_CNT*4 + | |
2774 | (CHIP_MODE_IS_4_PORT(bp) ? | |
2775 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
2776 | } | |
2777 | ||
523224a3 DK |
2778 | /* function setup flags */ |
2779 | flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); | |
2780 | ||
619c5cb6 VZ |
2781 | /* This flag is relevant for E1x only. |
2782 | * E2 doesn't have a TPA configuration in a function level. | |
523224a3 | 2783 | */ |
619c5cb6 | 2784 | flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; |
523224a3 DK |
2785 | |
2786 | func_init.func_flgs = flags; | |
2787 | func_init.pf_id = BP_FUNC(bp); | |
2788 | func_init.func_id = BP_FUNC(bp); | |
523224a3 DK |
2789 | func_init.spq_map = bp->spq_mapping; |
2790 | func_init.spq_prod = bp->spq_prod_idx; | |
2791 | ||
2792 | bnx2x_func_init(bp, &func_init); | |
2793 | ||
2794 | memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); | |
2795 | ||
2796 | /* | |
619c5cb6 VZ |
2797 | * Congestion management values depend on the link rate |
2798 | * There is no active link so initial link rate is set to 10 Gbps. | |
2799 | * When the link comes up The congestion management values are | |
2800 | * re-calculated according to the actual link rate. | |
2801 | */ | |
523224a3 DK |
2802 | bp->link_vars.line_speed = SPEED_10000; |
2803 | bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); | |
2804 | ||
2805 | /* Only the PMF sets the HW */ | |
2806 | if (bp->port.pmf) | |
2807 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2808 | ||
523224a3 DK |
2809 | /* init Event Queue */ |
2810 | eq_data.base_addr.hi = U64_HI(bp->eq_mapping); | |
2811 | eq_data.base_addr.lo = U64_LO(bp->eq_mapping); | |
2812 | eq_data.producer = bp->eq_prod; | |
2813 | eq_data.index_id = HC_SP_INDEX_EQ_CONS; | |
2814 | eq_data.sb_id = DEF_SB_ID; | |
2815 | storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); | |
2816 | } | |
2817 | ||
2818 | ||
2819 | static void bnx2x_e1h_disable(struct bnx2x *bp) | |
2820 | { | |
2821 | int port = BP_PORT(bp); | |
2822 | ||
619c5cb6 | 2823 | bnx2x_tx_disable(bp); |
523224a3 DK |
2824 | |
2825 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
523224a3 DK |
2826 | } |
2827 | ||
2828 | static void bnx2x_e1h_enable(struct bnx2x *bp) | |
2829 | { | |
2830 | int port = BP_PORT(bp); | |
2831 | ||
2832 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); | |
2833 | ||
2834 | /* Tx queue should be only reenabled */ | |
2835 | netif_tx_wake_all_queues(bp->dev); | |
2836 | ||
2837 | /* | |
2838 | * Should not call netif_carrier_on since it will be called if the link | |
2839 | * is up when checking for link state | |
2840 | */ | |
2841 | } | |
2842 | ||
1d187b34 BW |
2843 | #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 |
2844 | ||
2845 | static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) | |
2846 | { | |
2847 | struct eth_stats_info *ether_stat = | |
2848 | &bp->slowpath->drv_info_to_mcp.ether_stat; | |
2849 | ||
2850 | /* leave last char as NULL */ | |
2851 | memcpy(ether_stat->version, DRV_MODULE_VERSION, | |
2852 | ETH_STAT_INFO_VERSION_LEN - 1); | |
2853 | ||
2854 | bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj, | |
2855 | DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, | |
2856 | ether_stat->mac_local); | |
2857 | ||
2858 | ether_stat->mtu_size = bp->dev->mtu; | |
2859 | ||
2860 | if (bp->dev->features & NETIF_F_RXCSUM) | |
2861 | ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; | |
2862 | if (bp->dev->features & NETIF_F_TSO) | |
2863 | ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; | |
2864 | ether_stat->feature_flags |= bp->common.boot_mode; | |
2865 | ||
2866 | ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; | |
2867 | ||
2868 | ether_stat->txq_size = bp->tx_ring_size; | |
2869 | ether_stat->rxq_size = bp->rx_ring_size; | |
2870 | } | |
2871 | ||
2872 | static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) | |
2873 | { | |
f2fd5c34 | 2874 | #ifdef BCM_CNIC |
1d187b34 BW |
2875 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; |
2876 | struct fcoe_stats_info *fcoe_stat = | |
2877 | &bp->slowpath->drv_info_to_mcp.fcoe_stat; | |
2878 | ||
2879 | memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN); | |
2880 | ||
2881 | fcoe_stat->qos_priority = | |
2882 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; | |
2883 | ||
2884 | /* insert FCoE stats from ramrod response */ | |
2885 | if (!NO_FCOE(bp)) { | |
2886 | struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = | |
2887 | &bp->fw_stats_data->queue_stats[FCOE_IDX]. | |
2888 | tstorm_queue_statistics; | |
2889 | ||
2890 | struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = | |
2891 | &bp->fw_stats_data->queue_stats[FCOE_IDX]. | |
2892 | xstorm_queue_statistics; | |
2893 | ||
2894 | struct fcoe_statistics_params *fw_fcoe_stat = | |
2895 | &bp->fw_stats_data->fcoe; | |
2896 | ||
2897 | ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo, | |
2898 | fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); | |
2899 | ||
2900 | ADD_64(fcoe_stat->rx_bytes_hi, | |
2901 | fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, | |
2902 | fcoe_stat->rx_bytes_lo, | |
2903 | fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); | |
2904 | ||
2905 | ADD_64(fcoe_stat->rx_bytes_hi, | |
2906 | fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, | |
2907 | fcoe_stat->rx_bytes_lo, | |
2908 | fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); | |
2909 | ||
2910 | ADD_64(fcoe_stat->rx_bytes_hi, | |
2911 | fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, | |
2912 | fcoe_stat->rx_bytes_lo, | |
2913 | fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); | |
2914 | ||
2915 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
2916 | fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); | |
2917 | ||
2918 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
2919 | fcoe_q_tstorm_stats->rcv_ucast_pkts); | |
2920 | ||
2921 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
2922 | fcoe_q_tstorm_stats->rcv_bcast_pkts); | |
2923 | ||
2924 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
f33f1fcc | 2925 | fcoe_q_tstorm_stats->rcv_mcast_pkts); |
1d187b34 BW |
2926 | |
2927 | ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo, | |
2928 | fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); | |
2929 | ||
2930 | ADD_64(fcoe_stat->tx_bytes_hi, | |
2931 | fcoe_q_xstorm_stats->ucast_bytes_sent.hi, | |
2932 | fcoe_stat->tx_bytes_lo, | |
2933 | fcoe_q_xstorm_stats->ucast_bytes_sent.lo); | |
2934 | ||
2935 | ADD_64(fcoe_stat->tx_bytes_hi, | |
2936 | fcoe_q_xstorm_stats->bcast_bytes_sent.hi, | |
2937 | fcoe_stat->tx_bytes_lo, | |
2938 | fcoe_q_xstorm_stats->bcast_bytes_sent.lo); | |
2939 | ||
2940 | ADD_64(fcoe_stat->tx_bytes_hi, | |
2941 | fcoe_q_xstorm_stats->mcast_bytes_sent.hi, | |
2942 | fcoe_stat->tx_bytes_lo, | |
2943 | fcoe_q_xstorm_stats->mcast_bytes_sent.lo); | |
2944 | ||
2945 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
2946 | fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); | |
2947 | ||
2948 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
2949 | fcoe_q_xstorm_stats->ucast_pkts_sent); | |
2950 | ||
2951 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
2952 | fcoe_q_xstorm_stats->bcast_pkts_sent); | |
2953 | ||
2954 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
2955 | fcoe_q_xstorm_stats->mcast_pkts_sent); | |
2956 | } | |
2957 | ||
1d187b34 BW |
2958 | /* ask L5 driver to add data to the struct */ |
2959 | bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); | |
2960 | #endif | |
2961 | } | |
2962 | ||
2963 | static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) | |
2964 | { | |
f2fd5c34 | 2965 | #ifdef BCM_CNIC |
1d187b34 BW |
2966 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; |
2967 | struct iscsi_stats_info *iscsi_stat = | |
2968 | &bp->slowpath->drv_info_to_mcp.iscsi_stat; | |
2969 | ||
2970 | memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); | |
2971 | ||
2972 | iscsi_stat->qos_priority = | |
2973 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; | |
2974 | ||
1d187b34 BW |
2975 | /* ask L5 driver to add data to the struct */ |
2976 | bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); | |
2977 | #endif | |
2978 | } | |
2979 | ||
0793f83f DK |
2980 | /* called due to MCP event (on pmf): |
2981 | * reread new bandwidth configuration | |
2982 | * configure FW | |
2983 | * notify others function about the change | |
2984 | */ | |
2985 | static inline void bnx2x_config_mf_bw(struct bnx2x *bp) | |
2986 | { | |
2987 | if (bp->link_vars.link_up) { | |
2988 | bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); | |
2989 | bnx2x_link_sync_notify(bp); | |
2990 | } | |
2991 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2992 | } | |
2993 | ||
2994 | static inline void bnx2x_set_mf_bw(struct bnx2x *bp) | |
2995 | { | |
2996 | bnx2x_config_mf_bw(bp); | |
2997 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); | |
2998 | } | |
2999 | ||
1d187b34 BW |
3000 | static void bnx2x_handle_drv_info_req(struct bnx2x *bp) |
3001 | { | |
3002 | enum drv_info_opcode op_code; | |
3003 | u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); | |
3004 | ||
3005 | /* if drv_info version supported by MFW doesn't match - send NACK */ | |
3006 | if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { | |
3007 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3008 | return; | |
3009 | } | |
3010 | ||
3011 | op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> | |
3012 | DRV_INFO_CONTROL_OP_CODE_SHIFT; | |
3013 | ||
3014 | memset(&bp->slowpath->drv_info_to_mcp, 0, | |
3015 | sizeof(union drv_info_to_mcp)); | |
3016 | ||
3017 | switch (op_code) { | |
3018 | case ETH_STATS_OPCODE: | |
3019 | bnx2x_drv_info_ether_stat(bp); | |
3020 | break; | |
3021 | case FCOE_STATS_OPCODE: | |
3022 | bnx2x_drv_info_fcoe_stat(bp); | |
3023 | break; | |
3024 | case ISCSI_STATS_OPCODE: | |
3025 | bnx2x_drv_info_iscsi_stat(bp); | |
3026 | break; | |
3027 | default: | |
3028 | /* if op code isn't supported - send NACK */ | |
3029 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3030 | return; | |
3031 | } | |
3032 | ||
3033 | /* if we got drv_info attn from MFW then these fields are defined in | |
3034 | * shmem2 for sure | |
3035 | */ | |
3036 | SHMEM2_WR(bp, drv_info_host_addr_lo, | |
3037 | U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3038 | SHMEM2_WR(bp, drv_info_host_addr_hi, | |
3039 | U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3040 | ||
3041 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); | |
3042 | } | |
3043 | ||
523224a3 DK |
3044 | static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) |
3045 | { | |
3046 | DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); | |
3047 | ||
3048 | if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { | |
3049 | ||
3050 | /* | |
3051 | * This is the only place besides the function initialization | |
3052 | * where the bp->flags can change so it is done without any | |
3053 | * locks | |
3054 | */ | |
f2e0899f | 3055 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
51c1a580 | 3056 | DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); |
523224a3 DK |
3057 | bp->flags |= MF_FUNC_DIS; |
3058 | ||
3059 | bnx2x_e1h_disable(bp); | |
3060 | } else { | |
51c1a580 | 3061 | DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); |
523224a3 DK |
3062 | bp->flags &= ~MF_FUNC_DIS; |
3063 | ||
3064 | bnx2x_e1h_enable(bp); | |
3065 | } | |
3066 | dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; | |
3067 | } | |
3068 | if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { | |
0793f83f | 3069 | bnx2x_config_mf_bw(bp); |
523224a3 DK |
3070 | dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; |
3071 | } | |
3072 | ||
3073 | /* Report results to MCP */ | |
3074 | if (dcc_event) | |
3075 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); | |
3076 | else | |
3077 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); | |
3078 | } | |
3079 | ||
3080 | /* must be called under the spq lock */ | |
3081 | static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) | |
3082 | { | |
3083 | struct eth_spe *next_spe = bp->spq_prod_bd; | |
3084 | ||
3085 | if (bp->spq_prod_bd == bp->spq_last_bd) { | |
3086 | bp->spq_prod_bd = bp->spq; | |
3087 | bp->spq_prod_idx = 0; | |
51c1a580 | 3088 | DP(BNX2X_MSG_SP, "end of spq\n"); |
523224a3 DK |
3089 | } else { |
3090 | bp->spq_prod_bd++; | |
3091 | bp->spq_prod_idx++; | |
3092 | } | |
3093 | return next_spe; | |
3094 | } | |
3095 | ||
3096 | /* must be called under the spq lock */ | |
28912902 MC |
3097 | static inline void bnx2x_sp_prod_update(struct bnx2x *bp) |
3098 | { | |
3099 | int func = BP_FUNC(bp); | |
3100 | ||
53e51e2f VZ |
3101 | /* |
3102 | * Make sure that BD data is updated before writing the producer: | |
3103 | * BD data is written to the memory, the producer is read from the | |
3104 | * memory, thus we need a full memory barrier to ensure the ordering. | |
3105 | */ | |
3106 | mb(); | |
28912902 | 3107 | |
523224a3 | 3108 | REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), |
f85582f8 | 3109 | bp->spq_prod_idx); |
28912902 MC |
3110 | mmiowb(); |
3111 | } | |
3112 | ||
619c5cb6 VZ |
3113 | /** |
3114 | * bnx2x_is_contextless_ramrod - check if the current command ends on EQ | |
3115 | * | |
3116 | * @cmd: command to check | |
3117 | * @cmd_type: command type | |
3118 | */ | |
3119 | static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) | |
3120 | { | |
3121 | if ((cmd_type == NONE_CONNECTION_TYPE) || | |
6383c0b3 | 3122 | (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || |
619c5cb6 VZ |
3123 | (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || |
3124 | (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || | |
3125 | (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || | |
3126 | (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || | |
3127 | (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) | |
3128 | return true; | |
3129 | else | |
3130 | return false; | |
3131 | ||
3132 | } | |
3133 | ||
3134 | ||
3135 | /** | |
3136 | * bnx2x_sp_post - place a single command on an SP ring | |
3137 | * | |
3138 | * @bp: driver handle | |
3139 | * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) | |
3140 | * @cid: SW CID the command is related to | |
3141 | * @data_hi: command private data address (high 32 bits) | |
3142 | * @data_lo: command private data address (low 32 bits) | |
3143 | * @cmd_type: command type (e.g. NONE, ETH) | |
3144 | * | |
3145 | * SP data is handled as if it's always an address pair, thus data fields are | |
3146 | * not swapped to little endian in upper functions. Instead this function swaps | |
3147 | * data as if it's two u32 fields. | |
3148 | */ | |
9f6c9258 | 3149 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
619c5cb6 | 3150 | u32 data_hi, u32 data_lo, int cmd_type) |
a2fbb9ea | 3151 | { |
28912902 | 3152 | struct eth_spe *spe; |
523224a3 | 3153 | u16 type; |
619c5cb6 | 3154 | bool common = bnx2x_is_contextless_ramrod(command, cmd_type); |
a2fbb9ea | 3155 | |
a2fbb9ea | 3156 | #ifdef BNX2X_STOP_ON_ERROR |
51c1a580 MS |
3157 | if (unlikely(bp->panic)) { |
3158 | BNX2X_ERR("Can't post SP when there is panic\n"); | |
a2fbb9ea | 3159 | return -EIO; |
51c1a580 | 3160 | } |
a2fbb9ea ET |
3161 | #endif |
3162 | ||
34f80b04 | 3163 | spin_lock_bh(&bp->spq_lock); |
a2fbb9ea | 3164 | |
6e30dd4e VZ |
3165 | if (common) { |
3166 | if (!atomic_read(&bp->eq_spq_left)) { | |
3167 | BNX2X_ERR("BUG! EQ ring full!\n"); | |
3168 | spin_unlock_bh(&bp->spq_lock); | |
3169 | bnx2x_panic(); | |
3170 | return -EBUSY; | |
3171 | } | |
3172 | } else if (!atomic_read(&bp->cq_spq_left)) { | |
3173 | BNX2X_ERR("BUG! SPQ ring full!\n"); | |
3174 | spin_unlock_bh(&bp->spq_lock); | |
3175 | bnx2x_panic(); | |
3176 | return -EBUSY; | |
a2fbb9ea | 3177 | } |
f1410647 | 3178 | |
28912902 MC |
3179 | spe = bnx2x_sp_get_next(bp); |
3180 | ||
a2fbb9ea | 3181 | /* CID needs port number to be encoded int it */ |
28912902 | 3182 | spe->hdr.conn_and_cmd_data = |
cdaa7cb8 VZ |
3183 | cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | |
3184 | HW_CID(bp, cid)); | |
523224a3 | 3185 | |
619c5cb6 | 3186 | type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; |
a2fbb9ea | 3187 | |
523224a3 DK |
3188 | type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & |
3189 | SPE_HDR_FUNCTION_ID); | |
a2fbb9ea | 3190 | |
523224a3 DK |
3191 | spe->hdr.type = cpu_to_le16(type); |
3192 | ||
3193 | spe->data.update_data_addr.hi = cpu_to_le32(data_hi); | |
3194 | spe->data.update_data_addr.lo = cpu_to_le32(data_lo); | |
3195 | ||
d6cae238 VZ |
3196 | /* |
3197 | * It's ok if the actual decrement is issued towards the memory | |
3198 | * somewhere between the spin_lock and spin_unlock. Thus no | |
3199 | * more explict memory barrier is needed. | |
3200 | */ | |
3201 | if (common) | |
3202 | atomic_dec(&bp->eq_spq_left); | |
3203 | else | |
3204 | atomic_dec(&bp->cq_spq_left); | |
6e30dd4e | 3205 | |
a2fbb9ea | 3206 | |
51c1a580 MS |
3207 | DP(BNX2X_MSG_SP, |
3208 | "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", | |
cdaa7cb8 VZ |
3209 | bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), |
3210 | (u32)(U64_LO(bp->spq_mapping) + | |
d6cae238 | 3211 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, |
6e30dd4e VZ |
3212 | HW_CID(bp, cid), data_hi, data_lo, type, |
3213 | atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); | |
cdaa7cb8 | 3214 | |
28912902 | 3215 | bnx2x_sp_prod_update(bp); |
34f80b04 | 3216 | spin_unlock_bh(&bp->spq_lock); |
a2fbb9ea ET |
3217 | return 0; |
3218 | } | |
3219 | ||
3220 | /* acquire split MCP access lock register */ | |
4a37fb66 | 3221 | static int bnx2x_acquire_alr(struct bnx2x *bp) |
a2fbb9ea | 3222 | { |
72fd0718 | 3223 | u32 j, val; |
34f80b04 | 3224 | int rc = 0; |
a2fbb9ea ET |
3225 | |
3226 | might_sleep(); | |
72fd0718 | 3227 | for (j = 0; j < 1000; j++) { |
a2fbb9ea ET |
3228 | val = (1UL << 31); |
3229 | REG_WR(bp, GRCBASE_MCP + 0x9c, val); | |
3230 | val = REG_RD(bp, GRCBASE_MCP + 0x9c); | |
3231 | if (val & (1L << 31)) | |
3232 | break; | |
3233 | ||
3234 | msleep(5); | |
3235 | } | |
a2fbb9ea | 3236 | if (!(val & (1L << 31))) { |
19680c48 | 3237 | BNX2X_ERR("Cannot acquire MCP access lock register\n"); |
a2fbb9ea ET |
3238 | rc = -EBUSY; |
3239 | } | |
3240 | ||
3241 | return rc; | |
3242 | } | |
3243 | ||
4a37fb66 YG |
3244 | /* release split MCP access lock register */ |
3245 | static void bnx2x_release_alr(struct bnx2x *bp) | |
a2fbb9ea | 3246 | { |
72fd0718 | 3247 | REG_WR(bp, GRCBASE_MCP + 0x9c, 0); |
a2fbb9ea ET |
3248 | } |
3249 | ||
523224a3 DK |
3250 | #define BNX2X_DEF_SB_ATT_IDX 0x0001 |
3251 | #define BNX2X_DEF_SB_IDX 0x0002 | |
3252 | ||
a2fbb9ea ET |
3253 | static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) |
3254 | { | |
523224a3 | 3255 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
a2fbb9ea ET |
3256 | u16 rc = 0; |
3257 | ||
3258 | barrier(); /* status block is written to by the chip */ | |
a2fbb9ea ET |
3259 | if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { |
3260 | bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; | |
523224a3 | 3261 | rc |= BNX2X_DEF_SB_ATT_IDX; |
a2fbb9ea | 3262 | } |
523224a3 DK |
3263 | |
3264 | if (bp->def_idx != def_sb->sp_sb.running_index) { | |
3265 | bp->def_idx = def_sb->sp_sb.running_index; | |
3266 | rc |= BNX2X_DEF_SB_IDX; | |
a2fbb9ea | 3267 | } |
523224a3 DK |
3268 | |
3269 | /* Do not reorder: indecies reading should complete before handling */ | |
3270 | barrier(); | |
a2fbb9ea ET |
3271 | return rc; |
3272 | } | |
3273 | ||
3274 | /* | |
3275 | * slow path service functions | |
3276 | */ | |
3277 | ||
3278 | static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |
3279 | { | |
34f80b04 | 3280 | int port = BP_PORT(bp); |
a2fbb9ea ET |
3281 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
3282 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
877e9aa4 ET |
3283 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
3284 | NIG_REG_MASK_INTERRUPT_PORT0; | |
3fcaf2e5 | 3285 | u32 aeu_mask; |
87942b46 | 3286 | u32 nig_mask = 0; |
f2e0899f | 3287 | u32 reg_addr; |
a2fbb9ea | 3288 | |
a2fbb9ea ET |
3289 | if (bp->attn_state & asserted) |
3290 | BNX2X_ERR("IGU ERROR\n"); | |
3291 | ||
3fcaf2e5 EG |
3292 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
3293 | aeu_mask = REG_RD(bp, aeu_addr); | |
3294 | ||
a2fbb9ea | 3295 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
3fcaf2e5 | 3296 | aeu_mask, asserted); |
72fd0718 | 3297 | aeu_mask &= ~(asserted & 0x3ff); |
3fcaf2e5 | 3298 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 3299 | |
3fcaf2e5 EG |
3300 | REG_WR(bp, aeu_addr, aeu_mask); |
3301 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea | 3302 | |
3fcaf2e5 | 3303 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
a2fbb9ea | 3304 | bp->attn_state |= asserted; |
3fcaf2e5 | 3305 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
a2fbb9ea ET |
3306 | |
3307 | if (asserted & ATTN_HARD_WIRED_MASK) { | |
3308 | if (asserted & ATTN_NIG_FOR_FUNC) { | |
a2fbb9ea | 3309 | |
a5e9a7cf EG |
3310 | bnx2x_acquire_phy_lock(bp); |
3311 | ||
877e9aa4 | 3312 | /* save nig interrupt mask */ |
87942b46 | 3313 | nig_mask = REG_RD(bp, nig_int_mask_addr); |
a2fbb9ea | 3314 | |
361c391e YR |
3315 | /* If nig_mask is not set, no need to call the update |
3316 | * function. | |
3317 | */ | |
3318 | if (nig_mask) { | |
3319 | REG_WR(bp, nig_int_mask_addr, 0); | |
3320 | ||
3321 | bnx2x_link_attn(bp); | |
3322 | } | |
a2fbb9ea ET |
3323 | |
3324 | /* handle unicore attn? */ | |
3325 | } | |
3326 | if (asserted & ATTN_SW_TIMER_4_FUNC) | |
3327 | DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); | |
3328 | ||
3329 | if (asserted & GPIO_2_FUNC) | |
3330 | DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); | |
3331 | ||
3332 | if (asserted & GPIO_3_FUNC) | |
3333 | DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); | |
3334 | ||
3335 | if (asserted & GPIO_4_FUNC) | |
3336 | DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); | |
3337 | ||
3338 | if (port == 0) { | |
3339 | if (asserted & ATTN_GENERAL_ATTN_1) { | |
3340 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); | |
3341 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); | |
3342 | } | |
3343 | if (asserted & ATTN_GENERAL_ATTN_2) { | |
3344 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); | |
3345 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); | |
3346 | } | |
3347 | if (asserted & ATTN_GENERAL_ATTN_3) { | |
3348 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); | |
3349 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); | |
3350 | } | |
3351 | } else { | |
3352 | if (asserted & ATTN_GENERAL_ATTN_4) { | |
3353 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); | |
3354 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); | |
3355 | } | |
3356 | if (asserted & ATTN_GENERAL_ATTN_5) { | |
3357 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); | |
3358 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); | |
3359 | } | |
3360 | if (asserted & ATTN_GENERAL_ATTN_6) { | |
3361 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); | |
3362 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); | |
3363 | } | |
3364 | } | |
3365 | ||
3366 | } /* if hardwired */ | |
3367 | ||
f2e0899f DK |
3368 | if (bp->common.int_block == INT_BLOCK_HC) |
3369 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
3370 | COMMAND_REG_ATTN_BITS_SET); | |
3371 | else | |
3372 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); | |
3373 | ||
3374 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, | |
3375 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
3376 | REG_WR(bp, reg_addr, asserted); | |
a2fbb9ea ET |
3377 | |
3378 | /* now set back the mask */ | |
a5e9a7cf | 3379 | if (asserted & ATTN_NIG_FOR_FUNC) { |
87942b46 | 3380 | REG_WR(bp, nig_int_mask_addr, nig_mask); |
a5e9a7cf EG |
3381 | bnx2x_release_phy_lock(bp); |
3382 | } | |
a2fbb9ea ET |
3383 | } |
3384 | ||
fd4ef40d EG |
3385 | static inline void bnx2x_fan_failure(struct bnx2x *bp) |
3386 | { | |
3387 | int port = BP_PORT(bp); | |
b7737c9b | 3388 | u32 ext_phy_config; |
fd4ef40d | 3389 | /* mark the failure */ |
b7737c9b YR |
3390 | ext_phy_config = |
3391 | SHMEM_RD(bp, | |
3392 | dev_info.port_hw_config[port].external_phy_config); | |
3393 | ||
3394 | ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | |
3395 | ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; | |
fd4ef40d | 3396 | SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, |
b7737c9b | 3397 | ext_phy_config); |
fd4ef40d EG |
3398 | |
3399 | /* log the failure */ | |
51c1a580 MS |
3400 | netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" |
3401 | "Please contact OEM Support for assistance\n"); | |
8304859a AE |
3402 | |
3403 | /* | |
3404 | * Scheudle device reset (unload) | |
3405 | * This is due to some boards consuming sufficient power when driver is | |
3406 | * up to overheat if fan fails. | |
3407 | */ | |
3408 | smp_mb__before_clear_bit(); | |
3409 | set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); | |
3410 | smp_mb__after_clear_bit(); | |
3411 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
3412 | ||
fd4ef40d | 3413 | } |
ab6ad5a4 | 3414 | |
877e9aa4 | 3415 | static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
a2fbb9ea | 3416 | { |
34f80b04 | 3417 | int port = BP_PORT(bp); |
877e9aa4 | 3418 | int reg_offset; |
d90d96ba | 3419 | u32 val; |
877e9aa4 | 3420 | |
34f80b04 EG |
3421 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
3422 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
877e9aa4 | 3423 | |
34f80b04 | 3424 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { |
877e9aa4 ET |
3425 | |
3426 | val = REG_RD(bp, reg_offset); | |
3427 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; | |
3428 | REG_WR(bp, reg_offset, val); | |
3429 | ||
3430 | BNX2X_ERR("SPIO5 hw attention\n"); | |
3431 | ||
fd4ef40d | 3432 | /* Fan failure attention */ |
d90d96ba | 3433 | bnx2x_hw_reset_phy(&bp->link_params); |
fd4ef40d | 3434 | bnx2x_fan_failure(bp); |
877e9aa4 | 3435 | } |
34f80b04 | 3436 | |
3deb8167 | 3437 | if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { |
589abe3a EG |
3438 | bnx2x_acquire_phy_lock(bp); |
3439 | bnx2x_handle_module_detect_int(&bp->link_params); | |
3440 | bnx2x_release_phy_lock(bp); | |
3441 | } | |
3442 | ||
34f80b04 EG |
3443 | if (attn & HW_INTERRUT_ASSERT_SET_0) { |
3444 | ||
3445 | val = REG_RD(bp, reg_offset); | |
3446 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); | |
3447 | REG_WR(bp, reg_offset, val); | |
3448 | ||
3449 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", | |
0fc5d009 | 3450 | (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); |
34f80b04 EG |
3451 | bnx2x_panic(); |
3452 | } | |
877e9aa4 ET |
3453 | } |
3454 | ||
3455 | static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) | |
3456 | { | |
3457 | u32 val; | |
3458 | ||
0626b899 | 3459 | if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { |
877e9aa4 ET |
3460 | |
3461 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | |
3462 | BNX2X_ERR("DB hw attention 0x%x\n", val); | |
3463 | /* DORQ discard attention */ | |
3464 | if (val & 0x2) | |
3465 | BNX2X_ERR("FATAL error from DORQ\n"); | |
3466 | } | |
34f80b04 EG |
3467 | |
3468 | if (attn & HW_INTERRUT_ASSERT_SET_1) { | |
3469 | ||
3470 | int port = BP_PORT(bp); | |
3471 | int reg_offset; | |
3472 | ||
3473 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : | |
3474 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); | |
3475 | ||
3476 | val = REG_RD(bp, reg_offset); | |
3477 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); | |
3478 | REG_WR(bp, reg_offset, val); | |
3479 | ||
3480 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", | |
0fc5d009 | 3481 | (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); |
34f80b04 EG |
3482 | bnx2x_panic(); |
3483 | } | |
877e9aa4 ET |
3484 | } |
3485 | ||
3486 | static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) | |
3487 | { | |
3488 | u32 val; | |
3489 | ||
3490 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | |
3491 | ||
3492 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | |
3493 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | |
3494 | /* CFC error attention */ | |
3495 | if (val & 0x2) | |
3496 | BNX2X_ERR("FATAL error from CFC\n"); | |
3497 | } | |
3498 | ||
3499 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | |
877e9aa4 | 3500 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); |
619c5cb6 | 3501 | BNX2X_ERR("PXP hw attention-0 0x%x\n", val); |
877e9aa4 ET |
3502 | /* RQ_USDMDP_FIFO_OVERFLOW */ |
3503 | if (val & 0x18000) | |
3504 | BNX2X_ERR("FATAL error from PXP\n"); | |
619c5cb6 VZ |
3505 | |
3506 | if (!CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
3507 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); |
3508 | BNX2X_ERR("PXP hw attention-1 0x%x\n", val); | |
3509 | } | |
877e9aa4 | 3510 | } |
34f80b04 EG |
3511 | |
3512 | if (attn & HW_INTERRUT_ASSERT_SET_2) { | |
3513 | ||
3514 | int port = BP_PORT(bp); | |
3515 | int reg_offset; | |
3516 | ||
3517 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : | |
3518 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); | |
3519 | ||
3520 | val = REG_RD(bp, reg_offset); | |
3521 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); | |
3522 | REG_WR(bp, reg_offset, val); | |
3523 | ||
3524 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", | |
0fc5d009 | 3525 | (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); |
34f80b04 EG |
3526 | bnx2x_panic(); |
3527 | } | |
877e9aa4 ET |
3528 | } |
3529 | ||
3530 | static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) | |
3531 | { | |
34f80b04 EG |
3532 | u32 val; |
3533 | ||
877e9aa4 ET |
3534 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { |
3535 | ||
34f80b04 EG |
3536 | if (attn & BNX2X_PMF_LINK_ASSERT) { |
3537 | int func = BP_FUNC(bp); | |
3538 | ||
3539 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
f2e0899f DK |
3540 | bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, |
3541 | func_mf_config[BP_ABS_FUNC(bp)].config); | |
3542 | val = SHMEM_RD(bp, | |
3543 | func_mb[BP_FW_MB_IDX(bp)].drv_status); | |
2691d51d EG |
3544 | if (val & DRV_STATUS_DCC_EVENT_MASK) |
3545 | bnx2x_dcc_event(bp, | |
3546 | (val & DRV_STATUS_DCC_EVENT_MASK)); | |
0793f83f DK |
3547 | |
3548 | if (val & DRV_STATUS_SET_MF_BW) | |
3549 | bnx2x_set_mf_bw(bp); | |
3550 | ||
1d187b34 BW |
3551 | if (val & DRV_STATUS_DRV_INFO_REQ) |
3552 | bnx2x_handle_drv_info_req(bp); | |
2691d51d | 3553 | if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) |
34f80b04 EG |
3554 | bnx2x_pmf_update(bp); |
3555 | ||
e4901dde | 3556 | if (bp->port.pmf && |
785b9b1a SR |
3557 | (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && |
3558 | bp->dcbx_enabled > 0) | |
e4901dde VZ |
3559 | /* start dcbx state machine */ |
3560 | bnx2x_dcbx_set_params(bp, | |
3561 | BNX2X_DCBX_STATE_NEG_RECEIVED); | |
3deb8167 YR |
3562 | if (bp->link_vars.periodic_flags & |
3563 | PERIODIC_FLAGS_LINK_EVENT) { | |
3564 | /* sync with link */ | |
3565 | bnx2x_acquire_phy_lock(bp); | |
3566 | bp->link_vars.periodic_flags &= | |
3567 | ~PERIODIC_FLAGS_LINK_EVENT; | |
3568 | bnx2x_release_phy_lock(bp); | |
3569 | if (IS_MF(bp)) | |
3570 | bnx2x_link_sync_notify(bp); | |
3571 | bnx2x_link_report(bp); | |
3572 | } | |
3573 | /* Always call it here: bnx2x_link_report() will | |
3574 | * prevent the link indication duplication. | |
3575 | */ | |
3576 | bnx2x__link_status_update(bp); | |
34f80b04 | 3577 | } else if (attn & BNX2X_MC_ASSERT_BITS) { |
877e9aa4 ET |
3578 | |
3579 | BNX2X_ERR("MC assert!\n"); | |
d6cae238 | 3580 | bnx2x_mc_assert(bp); |
877e9aa4 ET |
3581 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); |
3582 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); | |
3583 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); | |
3584 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); | |
3585 | bnx2x_panic(); | |
3586 | ||
3587 | } else if (attn & BNX2X_MCP_ASSERT) { | |
3588 | ||
3589 | BNX2X_ERR("MCP assert!\n"); | |
3590 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); | |
34f80b04 | 3591 | bnx2x_fw_dump(bp); |
877e9aa4 ET |
3592 | |
3593 | } else | |
3594 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); | |
3595 | } | |
3596 | ||
3597 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { | |
34f80b04 EG |
3598 | BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); |
3599 | if (attn & BNX2X_GRC_TIMEOUT) { | |
f2e0899f DK |
3600 | val = CHIP_IS_E1(bp) ? 0 : |
3601 | REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); | |
34f80b04 EG |
3602 | BNX2X_ERR("GRC time-out 0x%08x\n", val); |
3603 | } | |
3604 | if (attn & BNX2X_GRC_RSV) { | |
f2e0899f DK |
3605 | val = CHIP_IS_E1(bp) ? 0 : |
3606 | REG_RD(bp, MISC_REG_GRC_RSV_ATTN); | |
34f80b04 EG |
3607 | BNX2X_ERR("GRC reserved 0x%08x\n", val); |
3608 | } | |
877e9aa4 | 3609 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); |
877e9aa4 ET |
3610 | } |
3611 | } | |
3612 | ||
c9ee9206 VZ |
3613 | /* |
3614 | * Bits map: | |
3615 | * 0-7 - Engine0 load counter. | |
3616 | * 8-15 - Engine1 load counter. | |
3617 | * 16 - Engine0 RESET_IN_PROGRESS bit. | |
3618 | * 17 - Engine1 RESET_IN_PROGRESS bit. | |
3619 | * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function | |
3620 | * on the engine | |
3621 | * 19 - Engine1 ONE_IS_LOADED. | |
3622 | * 20 - Chip reset flow bit. When set none-leader must wait for both engines | |
3623 | * leader to complete (check for both RESET_IN_PROGRESS bits and not for | |
3624 | * just the one belonging to its engine). | |
3625 | * | |
3626 | */ | |
3627 | #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 | |
3628 | ||
3629 | #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff | |
3630 | #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 | |
3631 | #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 | |
3632 | #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 | |
3633 | #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 | |
3634 | #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 | |
3635 | #define BNX2X_GLOBAL_RESET_BIT 0x00040000 | |
3636 | ||
3637 | /* | |
3638 | * Set the GLOBAL_RESET bit. | |
3639 | * | |
3640 | * Should be run under rtnl lock | |
3641 | */ | |
3642 | void bnx2x_set_reset_global(struct bnx2x *bp) | |
3643 | { | |
f16da43b AE |
3644 | u32 val; |
3645 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
3646 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 3647 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); |
f16da43b | 3648 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 VZ |
3649 | } |
3650 | ||
3651 | /* | |
3652 | * Clear the GLOBAL_RESET bit. | |
3653 | * | |
3654 | * Should be run under rtnl lock | |
3655 | */ | |
3656 | static inline void bnx2x_clear_reset_global(struct bnx2x *bp) | |
3657 | { | |
f16da43b AE |
3658 | u32 val; |
3659 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
3660 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 3661 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); |
f16da43b | 3662 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 | 3663 | } |
f85582f8 | 3664 | |
72fd0718 | 3665 | /* |
c9ee9206 VZ |
3666 | * Checks the GLOBAL_RESET bit. |
3667 | * | |
72fd0718 VZ |
3668 | * should be run under rtnl lock |
3669 | */ | |
c9ee9206 VZ |
3670 | static inline bool bnx2x_reset_is_global(struct bnx2x *bp) |
3671 | { | |
3672 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3673 | ||
3674 | DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); | |
3675 | return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; | |
3676 | } | |
3677 | ||
3678 | /* | |
3679 | * Clear RESET_IN_PROGRESS bit for the current engine. | |
3680 | * | |
3681 | * Should be run under rtnl lock | |
3682 | */ | |
72fd0718 VZ |
3683 | static inline void bnx2x_set_reset_done(struct bnx2x *bp) |
3684 | { | |
f16da43b | 3685 | u32 val; |
c9ee9206 VZ |
3686 | u32 bit = BP_PATH(bp) ? |
3687 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
3688 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3689 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
3690 | |
3691 | /* Clear the bit */ | |
3692 | val &= ~bit; | |
3693 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
3694 | |
3695 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
72fd0718 VZ |
3696 | } |
3697 | ||
3698 | /* | |
c9ee9206 VZ |
3699 | * Set RESET_IN_PROGRESS for the current engine. |
3700 | * | |
72fd0718 VZ |
3701 | * should be run under rtnl lock |
3702 | */ | |
c9ee9206 | 3703 | void bnx2x_set_reset_in_progress(struct bnx2x *bp) |
72fd0718 | 3704 | { |
f16da43b | 3705 | u32 val; |
c9ee9206 VZ |
3706 | u32 bit = BP_PATH(bp) ? |
3707 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
3708 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3709 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
3710 | |
3711 | /* Set the bit */ | |
3712 | val |= bit; | |
3713 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 3714 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
3715 | } |
3716 | ||
3717 | /* | |
c9ee9206 | 3718 | * Checks the RESET_IN_PROGRESS bit for the given engine. |
72fd0718 VZ |
3719 | * should be run under rtnl lock |
3720 | */ | |
c9ee9206 | 3721 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) |
72fd0718 | 3722 | { |
c9ee9206 VZ |
3723 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3724 | u32 bit = engine ? | |
3725 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
3726 | ||
3727 | /* return false if bit is set */ | |
3728 | return (val & bit) ? false : true; | |
72fd0718 VZ |
3729 | } |
3730 | ||
3731 | /* | |
889b9af3 | 3732 | * set pf load for the current pf. |
c9ee9206 | 3733 | * |
72fd0718 VZ |
3734 | * should be run under rtnl lock |
3735 | */ | |
889b9af3 | 3736 | void bnx2x_set_pf_load(struct bnx2x *bp) |
72fd0718 | 3737 | { |
f16da43b | 3738 | u32 val1, val; |
c9ee9206 VZ |
3739 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
3740 | BNX2X_PATH0_LOAD_CNT_MASK; | |
3741 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3742 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 3743 | |
f16da43b AE |
3744 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3745 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3746 | ||
51c1a580 | 3747 | DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 3748 | |
c9ee9206 VZ |
3749 | /* get the current counter value */ |
3750 | val1 = (val & mask) >> shift; | |
3751 | ||
889b9af3 AE |
3752 | /* set bit of that PF */ |
3753 | val1 |= (1 << bp->pf_num); | |
c9ee9206 VZ |
3754 | |
3755 | /* clear the old value */ | |
3756 | val &= ~mask; | |
3757 | ||
3758 | /* set the new one */ | |
3759 | val |= ((val1 << shift) & mask); | |
3760 | ||
3761 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 3762 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
3763 | } |
3764 | ||
c9ee9206 | 3765 | /** |
889b9af3 | 3766 | * bnx2x_clear_pf_load - clear pf load mark |
c9ee9206 VZ |
3767 | * |
3768 | * @bp: driver handle | |
3769 | * | |
3770 | * Should be run under rtnl lock. | |
3771 | * Decrements the load counter for the current engine. Returns | |
889b9af3 | 3772 | * whether other functions are still loaded |
72fd0718 | 3773 | */ |
889b9af3 | 3774 | bool bnx2x_clear_pf_load(struct bnx2x *bp) |
72fd0718 | 3775 | { |
f16da43b | 3776 | u32 val1, val; |
c9ee9206 VZ |
3777 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
3778 | BNX2X_PATH0_LOAD_CNT_MASK; | |
3779 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3780 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 3781 | |
f16da43b AE |
3782 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3783 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
51c1a580 | 3784 | DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 3785 | |
c9ee9206 VZ |
3786 | /* get the current counter value */ |
3787 | val1 = (val & mask) >> shift; | |
3788 | ||
889b9af3 AE |
3789 | /* clear bit of that PF */ |
3790 | val1 &= ~(1 << bp->pf_num); | |
c9ee9206 VZ |
3791 | |
3792 | /* clear the old value */ | |
3793 | val &= ~mask; | |
3794 | ||
3795 | /* set the new one */ | |
3796 | val |= ((val1 << shift) & mask); | |
3797 | ||
3798 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
3799 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3800 | return val1 != 0; | |
72fd0718 VZ |
3801 | } |
3802 | ||
3803 | /* | |
889b9af3 | 3804 | * Read the load status for the current engine. |
c9ee9206 | 3805 | * |
72fd0718 VZ |
3806 | * should be run under rtnl lock |
3807 | */ | |
889b9af3 | 3808 | static inline bool bnx2x_get_load_status(struct bnx2x *bp, int engine) |
72fd0718 | 3809 | { |
c9ee9206 VZ |
3810 | u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : |
3811 | BNX2X_PATH0_LOAD_CNT_MASK); | |
3812 | u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3813 | BNX2X_PATH0_LOAD_CNT_SHIFT); | |
3814 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3815 | ||
51c1a580 | 3816 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); |
c9ee9206 VZ |
3817 | |
3818 | val = (val & mask) >> shift; | |
3819 | ||
51c1a580 MS |
3820 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", |
3821 | engine, val); | |
c9ee9206 | 3822 | |
889b9af3 | 3823 | return val != 0; |
72fd0718 VZ |
3824 | } |
3825 | ||
c9ee9206 | 3826 | /* |
889b9af3 | 3827 | * Reset the load status for the current engine. |
c9ee9206 | 3828 | */ |
889b9af3 | 3829 | static inline void bnx2x_clear_load_status(struct bnx2x *bp) |
72fd0718 | 3830 | { |
f16da43b | 3831 | u32 val; |
c9ee9206 | 3832 | u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
f16da43b AE |
3833 | BNX2X_PATH0_LOAD_CNT_MASK); |
3834 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
3835 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 3836 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); |
f16da43b | 3837 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
3838 | } |
3839 | ||
3840 | static inline void _print_next_block(int idx, const char *blk) | |
3841 | { | |
f1deab50 | 3842 | pr_cont("%s%s", idx ? ", " : "", blk); |
72fd0718 VZ |
3843 | } |
3844 | ||
c9ee9206 VZ |
3845 | static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, |
3846 | bool print) | |
72fd0718 VZ |
3847 | { |
3848 | int i = 0; | |
3849 | u32 cur_bit = 0; | |
3850 | for (i = 0; sig; i++) { | |
3851 | cur_bit = ((u32)0x1 << i); | |
3852 | if (sig & cur_bit) { | |
3853 | switch (cur_bit) { | |
3854 | case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: | |
c9ee9206 VZ |
3855 | if (print) |
3856 | _print_next_block(par_num++, "BRB"); | |
72fd0718 VZ |
3857 | break; |
3858 | case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: | |
c9ee9206 VZ |
3859 | if (print) |
3860 | _print_next_block(par_num++, "PARSER"); | |
72fd0718 VZ |
3861 | break; |
3862 | case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: | |
c9ee9206 VZ |
3863 | if (print) |
3864 | _print_next_block(par_num++, "TSDM"); | |
72fd0718 VZ |
3865 | break; |
3866 | case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: | |
c9ee9206 VZ |
3867 | if (print) |
3868 | _print_next_block(par_num++, | |
3869 | "SEARCHER"); | |
3870 | break; | |
3871 | case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: | |
3872 | if (print) | |
3873 | _print_next_block(par_num++, "TCM"); | |
72fd0718 VZ |
3874 | break; |
3875 | case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
3876 | if (print) |
3877 | _print_next_block(par_num++, "TSEMI"); | |
3878 | break; | |
3879 | case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: | |
3880 | if (print) | |
3881 | _print_next_block(par_num++, "XPB"); | |
72fd0718 VZ |
3882 | break; |
3883 | } | |
3884 | ||
3885 | /* Clear the bit */ | |
3886 | sig &= ~cur_bit; | |
3887 | } | |
3888 | } | |
3889 | ||
3890 | return par_num; | |
3891 | } | |
3892 | ||
c9ee9206 VZ |
3893 | static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, |
3894 | bool *global, bool print) | |
72fd0718 VZ |
3895 | { |
3896 | int i = 0; | |
3897 | u32 cur_bit = 0; | |
3898 | for (i = 0; sig; i++) { | |
3899 | cur_bit = ((u32)0x1 << i); | |
3900 | if (sig & cur_bit) { | |
3901 | switch (cur_bit) { | |
c9ee9206 VZ |
3902 | case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: |
3903 | if (print) | |
3904 | _print_next_block(par_num++, "PBF"); | |
72fd0718 VZ |
3905 | break; |
3906 | case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: | |
c9ee9206 VZ |
3907 | if (print) |
3908 | _print_next_block(par_num++, "QM"); | |
3909 | break; | |
3910 | case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: | |
3911 | if (print) | |
3912 | _print_next_block(par_num++, "TM"); | |
72fd0718 VZ |
3913 | break; |
3914 | case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: | |
c9ee9206 VZ |
3915 | if (print) |
3916 | _print_next_block(par_num++, "XSDM"); | |
3917 | break; | |
3918 | case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: | |
3919 | if (print) | |
3920 | _print_next_block(par_num++, "XCM"); | |
72fd0718 VZ |
3921 | break; |
3922 | case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
3923 | if (print) |
3924 | _print_next_block(par_num++, "XSEMI"); | |
72fd0718 VZ |
3925 | break; |
3926 | case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: | |
c9ee9206 VZ |
3927 | if (print) |
3928 | _print_next_block(par_num++, | |
3929 | "DOORBELLQ"); | |
3930 | break; | |
3931 | case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: | |
3932 | if (print) | |
3933 | _print_next_block(par_num++, "NIG"); | |
72fd0718 VZ |
3934 | break; |
3935 | case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: | |
c9ee9206 VZ |
3936 | if (print) |
3937 | _print_next_block(par_num++, | |
3938 | "VAUX PCI CORE"); | |
3939 | *global = true; | |
72fd0718 VZ |
3940 | break; |
3941 | case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: | |
c9ee9206 VZ |
3942 | if (print) |
3943 | _print_next_block(par_num++, "DEBUG"); | |
72fd0718 VZ |
3944 | break; |
3945 | case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: | |
c9ee9206 VZ |
3946 | if (print) |
3947 | _print_next_block(par_num++, "USDM"); | |
72fd0718 | 3948 | break; |
8736c826 VZ |
3949 | case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: |
3950 | if (print) | |
3951 | _print_next_block(par_num++, "UCM"); | |
3952 | break; | |
72fd0718 | 3953 | case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: |
c9ee9206 VZ |
3954 | if (print) |
3955 | _print_next_block(par_num++, "USEMI"); | |
72fd0718 VZ |
3956 | break; |
3957 | case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: | |
c9ee9206 VZ |
3958 | if (print) |
3959 | _print_next_block(par_num++, "UPB"); | |
72fd0718 VZ |
3960 | break; |
3961 | case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: | |
c9ee9206 VZ |
3962 | if (print) |
3963 | _print_next_block(par_num++, "CSDM"); | |
72fd0718 | 3964 | break; |
8736c826 VZ |
3965 | case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: |
3966 | if (print) | |
3967 | _print_next_block(par_num++, "CCM"); | |
3968 | break; | |
72fd0718 VZ |
3969 | } |
3970 | ||
3971 | /* Clear the bit */ | |
3972 | sig &= ~cur_bit; | |
3973 | } | |
3974 | } | |
3975 | ||
3976 | return par_num; | |
3977 | } | |
3978 | ||
c9ee9206 VZ |
3979 | static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, |
3980 | bool print) | |
72fd0718 VZ |
3981 | { |
3982 | int i = 0; | |
3983 | u32 cur_bit = 0; | |
3984 | for (i = 0; sig; i++) { | |
3985 | cur_bit = ((u32)0x1 << i); | |
3986 | if (sig & cur_bit) { | |
3987 | switch (cur_bit) { | |
3988 | case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
3989 | if (print) |
3990 | _print_next_block(par_num++, "CSEMI"); | |
72fd0718 VZ |
3991 | break; |
3992 | case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: | |
c9ee9206 VZ |
3993 | if (print) |
3994 | _print_next_block(par_num++, "PXP"); | |
72fd0718 VZ |
3995 | break; |
3996 | case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: | |
c9ee9206 VZ |
3997 | if (print) |
3998 | _print_next_block(par_num++, | |
72fd0718 VZ |
3999 | "PXPPCICLOCKCLIENT"); |
4000 | break; | |
4001 | case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: | |
c9ee9206 VZ |
4002 | if (print) |
4003 | _print_next_block(par_num++, "CFC"); | |
72fd0718 VZ |
4004 | break; |
4005 | case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: | |
c9ee9206 VZ |
4006 | if (print) |
4007 | _print_next_block(par_num++, "CDU"); | |
4008 | break; | |
4009 | case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: | |
4010 | if (print) | |
4011 | _print_next_block(par_num++, "DMAE"); | |
72fd0718 VZ |
4012 | break; |
4013 | case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: | |
c9ee9206 VZ |
4014 | if (print) |
4015 | _print_next_block(par_num++, "IGU"); | |
72fd0718 VZ |
4016 | break; |
4017 | case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: | |
c9ee9206 VZ |
4018 | if (print) |
4019 | _print_next_block(par_num++, "MISC"); | |
72fd0718 VZ |
4020 | break; |
4021 | } | |
4022 | ||
4023 | /* Clear the bit */ | |
4024 | sig &= ~cur_bit; | |
4025 | } | |
4026 | } | |
4027 | ||
4028 | return par_num; | |
4029 | } | |
4030 | ||
c9ee9206 VZ |
4031 | static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, |
4032 | bool *global, bool print) | |
72fd0718 VZ |
4033 | { |
4034 | int i = 0; | |
4035 | u32 cur_bit = 0; | |
4036 | for (i = 0; sig; i++) { | |
4037 | cur_bit = ((u32)0x1 << i); | |
4038 | if (sig & cur_bit) { | |
4039 | switch (cur_bit) { | |
4040 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: | |
c9ee9206 VZ |
4041 | if (print) |
4042 | _print_next_block(par_num++, "MCP ROM"); | |
4043 | *global = true; | |
72fd0718 VZ |
4044 | break; |
4045 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: | |
c9ee9206 VZ |
4046 | if (print) |
4047 | _print_next_block(par_num++, | |
4048 | "MCP UMP RX"); | |
4049 | *global = true; | |
72fd0718 VZ |
4050 | break; |
4051 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: | |
c9ee9206 VZ |
4052 | if (print) |
4053 | _print_next_block(par_num++, | |
4054 | "MCP UMP TX"); | |
4055 | *global = true; | |
72fd0718 VZ |
4056 | break; |
4057 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: | |
c9ee9206 VZ |
4058 | if (print) |
4059 | _print_next_block(par_num++, | |
4060 | "MCP SCPAD"); | |
4061 | *global = true; | |
72fd0718 VZ |
4062 | break; |
4063 | } | |
4064 | ||
4065 | /* Clear the bit */ | |
4066 | sig &= ~cur_bit; | |
4067 | } | |
4068 | } | |
4069 | ||
4070 | return par_num; | |
4071 | } | |
4072 | ||
8736c826 VZ |
4073 | static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, |
4074 | bool print) | |
4075 | { | |
4076 | int i = 0; | |
4077 | u32 cur_bit = 0; | |
4078 | for (i = 0; sig; i++) { | |
4079 | cur_bit = ((u32)0x1 << i); | |
4080 | if (sig & cur_bit) { | |
4081 | switch (cur_bit) { | |
4082 | case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: | |
4083 | if (print) | |
4084 | _print_next_block(par_num++, "PGLUE_B"); | |
4085 | break; | |
4086 | case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: | |
4087 | if (print) | |
4088 | _print_next_block(par_num++, "ATC"); | |
4089 | break; | |
4090 | } | |
4091 | ||
4092 | /* Clear the bit */ | |
4093 | sig &= ~cur_bit; | |
4094 | } | |
4095 | } | |
4096 | ||
4097 | return par_num; | |
4098 | } | |
4099 | ||
c9ee9206 | 4100 | static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, |
8736c826 | 4101 | u32 *sig) |
72fd0718 | 4102 | { |
8736c826 VZ |
4103 | if ((sig[0] & HW_PRTY_ASSERT_SET_0) || |
4104 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
4105 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
4106 | (sig[3] & HW_PRTY_ASSERT_SET_3) || | |
4107 | (sig[4] & HW_PRTY_ASSERT_SET_4)) { | |
72fd0718 | 4108 | int par_num = 0; |
51c1a580 MS |
4109 | DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" |
4110 | "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", | |
8736c826 VZ |
4111 | sig[0] & HW_PRTY_ASSERT_SET_0, |
4112 | sig[1] & HW_PRTY_ASSERT_SET_1, | |
4113 | sig[2] & HW_PRTY_ASSERT_SET_2, | |
4114 | sig[3] & HW_PRTY_ASSERT_SET_3, | |
4115 | sig[4] & HW_PRTY_ASSERT_SET_4); | |
c9ee9206 VZ |
4116 | if (print) |
4117 | netdev_err(bp->dev, | |
4118 | "Parity errors detected in blocks: "); | |
4119 | par_num = bnx2x_check_blocks_with_parity0( | |
8736c826 | 4120 | sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); |
c9ee9206 | 4121 | par_num = bnx2x_check_blocks_with_parity1( |
8736c826 | 4122 | sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); |
c9ee9206 | 4123 | par_num = bnx2x_check_blocks_with_parity2( |
8736c826 | 4124 | sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); |
c9ee9206 | 4125 | par_num = bnx2x_check_blocks_with_parity3( |
8736c826 VZ |
4126 | sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); |
4127 | par_num = bnx2x_check_blocks_with_parity4( | |
4128 | sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); | |
4129 | ||
c9ee9206 VZ |
4130 | if (print) |
4131 | pr_cont("\n"); | |
8736c826 | 4132 | |
72fd0718 VZ |
4133 | return true; |
4134 | } else | |
4135 | return false; | |
4136 | } | |
4137 | ||
c9ee9206 VZ |
4138 | /** |
4139 | * bnx2x_chk_parity_attn - checks for parity attentions. | |
4140 | * | |
4141 | * @bp: driver handle | |
4142 | * @global: true if there was a global attention | |
4143 | * @print: show parity attention in syslog | |
4144 | */ | |
4145 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) | |
877e9aa4 | 4146 | { |
8736c826 | 4147 | struct attn_route attn = { {0} }; |
72fd0718 VZ |
4148 | int port = BP_PORT(bp); |
4149 | ||
4150 | attn.sig[0] = REG_RD(bp, | |
4151 | MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + | |
4152 | port*4); | |
4153 | attn.sig[1] = REG_RD(bp, | |
4154 | MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + | |
4155 | port*4); | |
4156 | attn.sig[2] = REG_RD(bp, | |
4157 | MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + | |
4158 | port*4); | |
4159 | attn.sig[3] = REG_RD(bp, | |
4160 | MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + | |
4161 | port*4); | |
4162 | ||
8736c826 VZ |
4163 | if (!CHIP_IS_E1x(bp)) |
4164 | attn.sig[4] = REG_RD(bp, | |
4165 | MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + | |
4166 | port*4); | |
4167 | ||
4168 | return bnx2x_parity_attn(bp, global, print, attn.sig); | |
72fd0718 VZ |
4169 | } |
4170 | ||
f2e0899f DK |
4171 | |
4172 | static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) | |
4173 | { | |
4174 | u32 val; | |
4175 | if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { | |
4176 | ||
4177 | val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); | |
4178 | BNX2X_ERR("PGLUE hw attention 0x%x\n", val); | |
4179 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) | |
51c1a580 | 4180 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); |
f2e0899f | 4181 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) |
51c1a580 | 4182 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); |
f2e0899f | 4183 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) |
51c1a580 | 4184 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); |
f2e0899f | 4185 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) |
51c1a580 | 4186 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); |
f2e0899f DK |
4187 | if (val & |
4188 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) | |
51c1a580 | 4189 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); |
f2e0899f DK |
4190 | if (val & |
4191 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) | |
51c1a580 | 4192 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); |
f2e0899f | 4193 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) |
51c1a580 | 4194 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); |
f2e0899f | 4195 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) |
51c1a580 | 4196 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); |
f2e0899f | 4197 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) |
51c1a580 | 4198 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); |
f2e0899f DK |
4199 | } |
4200 | if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { | |
4201 | val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); | |
4202 | BNX2X_ERR("ATC hw attention 0x%x\n", val); | |
4203 | if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) | |
4204 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); | |
4205 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) | |
51c1a580 | 4206 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); |
f2e0899f | 4207 | if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) |
51c1a580 | 4208 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); |
f2e0899f | 4209 | if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) |
51c1a580 | 4210 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); |
f2e0899f DK |
4211 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) |
4212 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); | |
4213 | if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) | |
51c1a580 | 4214 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); |
f2e0899f DK |
4215 | } |
4216 | ||
4217 | if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4218 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { | |
4219 | BNX2X_ERR("FATAL parity attention set4 0x%x\n", | |
4220 | (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4221 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); | |
4222 | } | |
4223 | ||
4224 | } | |
4225 | ||
72fd0718 VZ |
4226 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) |
4227 | { | |
4228 | struct attn_route attn, *group_mask; | |
34f80b04 | 4229 | int port = BP_PORT(bp); |
877e9aa4 | 4230 | int index; |
a2fbb9ea ET |
4231 | u32 reg_addr; |
4232 | u32 val; | |
3fcaf2e5 | 4233 | u32 aeu_mask; |
c9ee9206 | 4234 | bool global = false; |
a2fbb9ea ET |
4235 | |
4236 | /* need to take HW lock because MCP or other port might also | |
4237 | try to handle this event */ | |
4a37fb66 | 4238 | bnx2x_acquire_alr(bp); |
a2fbb9ea | 4239 | |
c9ee9206 VZ |
4240 | if (bnx2x_chk_parity_attn(bp, &global, true)) { |
4241 | #ifndef BNX2X_STOP_ON_ERROR | |
72fd0718 | 4242 | bp->recovery_state = BNX2X_RECOVERY_INIT; |
7be08a72 | 4243 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
72fd0718 VZ |
4244 | /* Disable HW interrupts */ |
4245 | bnx2x_int_disable(bp); | |
72fd0718 VZ |
4246 | /* In case of parity errors don't handle attentions so that |
4247 | * other function would "see" parity errors. | |
4248 | */ | |
c9ee9206 VZ |
4249 | #else |
4250 | bnx2x_panic(); | |
4251 | #endif | |
4252 | bnx2x_release_alr(bp); | |
72fd0718 VZ |
4253 | return; |
4254 | } | |
4255 | ||
a2fbb9ea ET |
4256 | attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); |
4257 | attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); | |
4258 | attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); | |
4259 | attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); | |
619c5cb6 | 4260 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
4261 | attn.sig[4] = |
4262 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); | |
4263 | else | |
4264 | attn.sig[4] = 0; | |
4265 | ||
4266 | DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", | |
4267 | attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); | |
a2fbb9ea ET |
4268 | |
4269 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { | |
4270 | if (deasserted & (1 << index)) { | |
72fd0718 | 4271 | group_mask = &bp->attn_group[index]; |
a2fbb9ea | 4272 | |
51c1a580 | 4273 | DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", |
f2e0899f DK |
4274 | index, |
4275 | group_mask->sig[0], group_mask->sig[1], | |
4276 | group_mask->sig[2], group_mask->sig[3], | |
4277 | group_mask->sig[4]); | |
a2fbb9ea | 4278 | |
f2e0899f DK |
4279 | bnx2x_attn_int_deasserted4(bp, |
4280 | attn.sig[4] & group_mask->sig[4]); | |
877e9aa4 | 4281 | bnx2x_attn_int_deasserted3(bp, |
72fd0718 | 4282 | attn.sig[3] & group_mask->sig[3]); |
877e9aa4 | 4283 | bnx2x_attn_int_deasserted1(bp, |
72fd0718 | 4284 | attn.sig[1] & group_mask->sig[1]); |
877e9aa4 | 4285 | bnx2x_attn_int_deasserted2(bp, |
72fd0718 | 4286 | attn.sig[2] & group_mask->sig[2]); |
877e9aa4 | 4287 | bnx2x_attn_int_deasserted0(bp, |
72fd0718 | 4288 | attn.sig[0] & group_mask->sig[0]); |
a2fbb9ea ET |
4289 | } |
4290 | } | |
4291 | ||
4a37fb66 | 4292 | bnx2x_release_alr(bp); |
a2fbb9ea | 4293 | |
f2e0899f DK |
4294 | if (bp->common.int_block == INT_BLOCK_HC) |
4295 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
4296 | COMMAND_REG_ATTN_BITS_CLR); | |
4297 | else | |
4298 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); | |
a2fbb9ea ET |
4299 | |
4300 | val = ~deasserted; | |
f2e0899f DK |
4301 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, |
4302 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
5c862848 | 4303 | REG_WR(bp, reg_addr, val); |
a2fbb9ea | 4304 | |
a2fbb9ea | 4305 | if (~bp->attn_state & deasserted) |
3fcaf2e5 | 4306 | BNX2X_ERR("IGU ERROR\n"); |
a2fbb9ea ET |
4307 | |
4308 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
4309 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
4310 | ||
3fcaf2e5 EG |
4311 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
4312 | aeu_mask = REG_RD(bp, reg_addr); | |
4313 | ||
4314 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", | |
4315 | aeu_mask, deasserted); | |
72fd0718 | 4316 | aeu_mask |= (deasserted & 0x3ff); |
3fcaf2e5 | 4317 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 4318 | |
3fcaf2e5 EG |
4319 | REG_WR(bp, reg_addr, aeu_mask); |
4320 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea ET |
4321 | |
4322 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | |
4323 | bp->attn_state &= ~deasserted; | |
4324 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); | |
4325 | } | |
4326 | ||
4327 | static void bnx2x_attn_int(struct bnx2x *bp) | |
4328 | { | |
4329 | /* read local copy of bits */ | |
68d59484 EG |
4330 | u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. |
4331 | attn_bits); | |
4332 | u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. | |
4333 | attn_bits_ack); | |
a2fbb9ea ET |
4334 | u32 attn_state = bp->attn_state; |
4335 | ||
4336 | /* look for changed bits */ | |
4337 | u32 asserted = attn_bits & ~attn_ack & ~attn_state; | |
4338 | u32 deasserted = ~attn_bits & attn_ack & attn_state; | |
4339 | ||
4340 | DP(NETIF_MSG_HW, | |
4341 | "attn_bits %x attn_ack %x asserted %x deasserted %x\n", | |
4342 | attn_bits, attn_ack, asserted, deasserted); | |
4343 | ||
4344 | if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) | |
34f80b04 | 4345 | BNX2X_ERR("BAD attention state\n"); |
a2fbb9ea ET |
4346 | |
4347 | /* handle bits that were raised */ | |
4348 | if (asserted) | |
4349 | bnx2x_attn_int_asserted(bp, asserted); | |
4350 | ||
4351 | if (deasserted) | |
4352 | bnx2x_attn_int_deasserted(bp, deasserted); | |
4353 | } | |
4354 | ||
619c5cb6 VZ |
4355 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, |
4356 | u16 index, u8 op, u8 update) | |
4357 | { | |
4358 | u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
4359 | ||
4360 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, | |
4361 | igu_addr); | |
4362 | } | |
4363 | ||
523224a3 DK |
4364 | static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) |
4365 | { | |
4366 | /* No memory barriers */ | |
4367 | storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); | |
4368 | mmiowb(); /* keep prod updates ordered */ | |
4369 | } | |
4370 | ||
4371 | #ifdef BCM_CNIC | |
4372 | static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, | |
4373 | union event_ring_elem *elem) | |
4374 | { | |
619c5cb6 VZ |
4375 | u8 err = elem->message.error; |
4376 | ||
523224a3 | 4377 | if (!bp->cnic_eth_dev.starting_cid || |
c3a8ce61 VZ |
4378 | (cid < bp->cnic_eth_dev.starting_cid && |
4379 | cid != bp->cnic_eth_dev.iscsi_l2_cid)) | |
523224a3 DK |
4380 | return 1; |
4381 | ||
4382 | DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); | |
4383 | ||
619c5cb6 VZ |
4384 | if (unlikely(err)) { |
4385 | ||
523224a3 DK |
4386 | BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", |
4387 | cid); | |
4388 | bnx2x_panic_dump(bp); | |
4389 | } | |
619c5cb6 | 4390 | bnx2x_cnic_cfc_comp(bp, cid, err); |
523224a3 DK |
4391 | return 0; |
4392 | } | |
4393 | #endif | |
4394 | ||
619c5cb6 VZ |
4395 | static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) |
4396 | { | |
4397 | struct bnx2x_mcast_ramrod_params rparam; | |
4398 | int rc; | |
4399 | ||
4400 | memset(&rparam, 0, sizeof(rparam)); | |
4401 | ||
4402 | rparam.mcast_obj = &bp->mcast_obj; | |
4403 | ||
4404 | netif_addr_lock_bh(bp->dev); | |
4405 | ||
4406 | /* Clear pending state for the last command */ | |
4407 | bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); | |
4408 | ||
4409 | /* If there are pending mcast commands - send them */ | |
4410 | if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { | |
4411 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
4412 | if (rc < 0) | |
4413 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", | |
4414 | rc); | |
4415 | } | |
4416 | ||
4417 | netif_addr_unlock_bh(bp->dev); | |
4418 | } | |
4419 | ||
4420 | static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, | |
4421 | union event_ring_elem *elem) | |
4422 | { | |
4423 | unsigned long ramrod_flags = 0; | |
4424 | int rc = 0; | |
4425 | u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; | |
4426 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; | |
4427 | ||
4428 | /* Always push next commands out, don't wait here */ | |
4429 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
4430 | ||
4431 | switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { | |
4432 | case BNX2X_FILTER_MAC_PENDING: | |
51c1a580 | 4433 | DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); |
619c5cb6 VZ |
4434 | #ifdef BCM_CNIC |
4435 | if (cid == BNX2X_ISCSI_ETH_CID) | |
4436 | vlan_mac_obj = &bp->iscsi_l2_mac_obj; | |
4437 | else | |
4438 | #endif | |
4439 | vlan_mac_obj = &bp->fp[cid].mac_obj; | |
4440 | ||
4441 | break; | |
619c5cb6 | 4442 | case BNX2X_FILTER_MCAST_PENDING: |
51c1a580 | 4443 | DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); |
619c5cb6 VZ |
4444 | /* This is only relevant for 57710 where multicast MACs are |
4445 | * configured as unicast MACs using the same ramrod. | |
4446 | */ | |
4447 | bnx2x_handle_mcast_eqe(bp); | |
4448 | return; | |
4449 | default: | |
4450 | BNX2X_ERR("Unsupported classification command: %d\n", | |
4451 | elem->message.data.eth_event.echo); | |
4452 | return; | |
4453 | } | |
4454 | ||
4455 | rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); | |
4456 | ||
4457 | if (rc < 0) | |
4458 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); | |
4459 | else if (rc > 0) | |
4460 | DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); | |
4461 | ||
4462 | } | |
4463 | ||
4464 | #ifdef BCM_CNIC | |
4465 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); | |
4466 | #endif | |
4467 | ||
4468 | static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) | |
4469 | { | |
4470 | netif_addr_lock_bh(bp->dev); | |
4471 | ||
4472 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
4473 | ||
4474 | /* Send rx_mode command again if was requested */ | |
4475 | if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) | |
4476 | bnx2x_set_storm_rx_mode(bp); | |
4477 | #ifdef BCM_CNIC | |
4478 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, | |
4479 | &bp->sp_state)) | |
4480 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
4481 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, | |
4482 | &bp->sp_state)) | |
4483 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
4484 | #endif | |
4485 | ||
4486 | netif_addr_unlock_bh(bp->dev); | |
4487 | } | |
4488 | ||
4489 | static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( | |
4490 | struct bnx2x *bp, u32 cid) | |
4491 | { | |
94f05b0f | 4492 | DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); |
619c5cb6 VZ |
4493 | #ifdef BCM_CNIC |
4494 | if (cid == BNX2X_FCOE_ETH_CID) | |
4495 | return &bnx2x_fcoe(bp, q_obj); | |
4496 | else | |
4497 | #endif | |
6383c0b3 | 4498 | return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); |
619c5cb6 VZ |
4499 | } |
4500 | ||
523224a3 DK |
4501 | static void bnx2x_eq_int(struct bnx2x *bp) |
4502 | { | |
4503 | u16 hw_cons, sw_cons, sw_prod; | |
4504 | union event_ring_elem *elem; | |
4505 | u32 cid; | |
4506 | u8 opcode; | |
4507 | int spqe_cnt = 0; | |
619c5cb6 VZ |
4508 | struct bnx2x_queue_sp_obj *q_obj; |
4509 | struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; | |
4510 | struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; | |
523224a3 DK |
4511 | |
4512 | hw_cons = le16_to_cpu(*bp->eq_cons_sb); | |
4513 | ||
4514 | /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. | |
4515 | * when we get the the next-page we nned to adjust so the loop | |
4516 | * condition below will be met. The next element is the size of a | |
4517 | * regular element and hence incrementing by 1 | |
4518 | */ | |
4519 | if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) | |
4520 | hw_cons++; | |
4521 | ||
25985edc | 4522 | /* This function may never run in parallel with itself for a |
523224a3 DK |
4523 | * specific bp, thus there is no need in "paired" read memory |
4524 | * barrier here. | |
4525 | */ | |
4526 | sw_cons = bp->eq_cons; | |
4527 | sw_prod = bp->eq_prod; | |
4528 | ||
d6cae238 | 4529 | DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", |
6e30dd4e | 4530 | hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); |
523224a3 DK |
4531 | |
4532 | for (; sw_cons != hw_cons; | |
4533 | sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { | |
4534 | ||
4535 | ||
4536 | elem = &bp->eq_ring[EQ_DESC(sw_cons)]; | |
4537 | ||
4538 | cid = SW_CID(elem->message.data.cfc_del_event.cid); | |
4539 | opcode = elem->message.opcode; | |
4540 | ||
4541 | ||
4542 | /* handle eq element */ | |
4543 | switch (opcode) { | |
4544 | case EVENT_RING_OPCODE_STAT_QUERY: | |
51c1a580 MS |
4545 | DP(BNX2X_MSG_SP | BNX2X_MSG_STATS, |
4546 | "got statistics comp event %d\n", | |
619c5cb6 | 4547 | bp->stats_comp++); |
523224a3 | 4548 | /* nothing to do with stats comp */ |
d6cae238 | 4549 | goto next_spqe; |
523224a3 DK |
4550 | |
4551 | case EVENT_RING_OPCODE_CFC_DEL: | |
4552 | /* handle according to cid range */ | |
4553 | /* | |
4554 | * we may want to verify here that the bp state is | |
4555 | * HALTING | |
4556 | */ | |
d6cae238 | 4557 | DP(BNX2X_MSG_SP, |
523224a3 DK |
4558 | "got delete ramrod for MULTI[%d]\n", cid); |
4559 | #ifdef BCM_CNIC | |
4560 | if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) | |
4561 | goto next_spqe; | |
4562 | #endif | |
619c5cb6 VZ |
4563 | q_obj = bnx2x_cid_to_q_obj(bp, cid); |
4564 | ||
4565 | if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) | |
4566 | break; | |
4567 | ||
4568 | ||
523224a3 DK |
4569 | |
4570 | goto next_spqe; | |
e4901dde VZ |
4571 | |
4572 | case EVENT_RING_OPCODE_STOP_TRAFFIC: | |
51c1a580 | 4573 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); |
6debea87 DK |
4574 | if (f_obj->complete_cmd(bp, f_obj, |
4575 | BNX2X_F_CMD_TX_STOP)) | |
4576 | break; | |
e4901dde VZ |
4577 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); |
4578 | goto next_spqe; | |
619c5cb6 | 4579 | |
e4901dde | 4580 | case EVENT_RING_OPCODE_START_TRAFFIC: |
51c1a580 | 4581 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); |
6debea87 DK |
4582 | if (f_obj->complete_cmd(bp, f_obj, |
4583 | BNX2X_F_CMD_TX_START)) | |
4584 | break; | |
e4901dde VZ |
4585 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); |
4586 | goto next_spqe; | |
619c5cb6 | 4587 | case EVENT_RING_OPCODE_FUNCTION_START: |
51c1a580 MS |
4588 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
4589 | "got FUNC_START ramrod\n"); | |
619c5cb6 VZ |
4590 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) |
4591 | break; | |
4592 | ||
4593 | goto next_spqe; | |
4594 | ||
4595 | case EVENT_RING_OPCODE_FUNCTION_STOP: | |
51c1a580 MS |
4596 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
4597 | "got FUNC_STOP ramrod\n"); | |
619c5cb6 VZ |
4598 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) |
4599 | break; | |
4600 | ||
4601 | goto next_spqe; | |
523224a3 DK |
4602 | } |
4603 | ||
4604 | switch (opcode | bp->state) { | |
619c5cb6 VZ |
4605 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
4606 | BNX2X_STATE_OPEN): | |
4607 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | | |
523224a3 | 4608 | BNX2X_STATE_OPENING_WAIT4_PORT): |
619c5cb6 VZ |
4609 | cid = elem->message.data.eth_event.echo & |
4610 | BNX2X_SWCID_MASK; | |
d6cae238 | 4611 | DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", |
619c5cb6 VZ |
4612 | cid); |
4613 | rss_raw->clear_pending(rss_raw); | |
523224a3 DK |
4614 | break; |
4615 | ||
619c5cb6 VZ |
4616 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): |
4617 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): | |
4618 | case (EVENT_RING_OPCODE_SET_MAC | | |
523224a3 | 4619 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
619c5cb6 VZ |
4620 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
4621 | BNX2X_STATE_OPEN): | |
4622 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
4623 | BNX2X_STATE_DIAG): | |
4624 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
4625 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 4626 | DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); |
619c5cb6 | 4627 | bnx2x_handle_classification_eqe(bp, elem); |
523224a3 DK |
4628 | break; |
4629 | ||
619c5cb6 VZ |
4630 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
4631 | BNX2X_STATE_OPEN): | |
4632 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
4633 | BNX2X_STATE_DIAG): | |
4634 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
4635 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 4636 | DP(BNX2X_MSG_SP, "got mcast ramrod\n"); |
619c5cb6 | 4637 | bnx2x_handle_mcast_eqe(bp); |
523224a3 DK |
4638 | break; |
4639 | ||
619c5cb6 VZ |
4640 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
4641 | BNX2X_STATE_OPEN): | |
4642 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
4643 | BNX2X_STATE_DIAG): | |
4644 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
523224a3 | 4645 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
d6cae238 | 4646 | DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); |
619c5cb6 | 4647 | bnx2x_handle_rx_mode_eqe(bp); |
523224a3 DK |
4648 | break; |
4649 | default: | |
4650 | /* unknown event log error and continue */ | |
619c5cb6 VZ |
4651 | BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", |
4652 | elem->message.opcode, bp->state); | |
523224a3 DK |
4653 | } |
4654 | next_spqe: | |
4655 | spqe_cnt++; | |
4656 | } /* for */ | |
4657 | ||
8fe23fbd | 4658 | smp_mb__before_atomic_inc(); |
6e30dd4e | 4659 | atomic_add(spqe_cnt, &bp->eq_spq_left); |
523224a3 DK |
4660 | |
4661 | bp->eq_cons = sw_cons; | |
4662 | bp->eq_prod = sw_prod; | |
4663 | /* Make sure that above mem writes were issued towards the memory */ | |
4664 | smp_wmb(); | |
4665 | ||
4666 | /* update producer */ | |
4667 | bnx2x_update_eq_prod(bp, bp->eq_prod); | |
4668 | } | |
4669 | ||
a2fbb9ea ET |
4670 | static void bnx2x_sp_task(struct work_struct *work) |
4671 | { | |
1cf167f2 | 4672 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); |
a2fbb9ea ET |
4673 | u16 status; |
4674 | ||
a2fbb9ea | 4675 | status = bnx2x_update_dsb_idx(bp); |
34f80b04 EG |
4676 | /* if (status == 0) */ |
4677 | /* BNX2X_ERR("spurious slowpath interrupt!\n"); */ | |
a2fbb9ea | 4678 | |
51c1a580 | 4679 | DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status); |
a2fbb9ea | 4680 | |
877e9aa4 | 4681 | /* HW attentions */ |
523224a3 | 4682 | if (status & BNX2X_DEF_SB_ATT_IDX) { |
a2fbb9ea | 4683 | bnx2x_attn_int(bp); |
523224a3 | 4684 | status &= ~BNX2X_DEF_SB_ATT_IDX; |
cdaa7cb8 VZ |
4685 | } |
4686 | ||
523224a3 DK |
4687 | /* SP events: STAT_QUERY and others */ |
4688 | if (status & BNX2X_DEF_SB_IDX) { | |
ec6ba945 VZ |
4689 | #ifdef BCM_CNIC |
4690 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
523224a3 | 4691 | |
ec6ba945 | 4692 | if ((!NO_FCOE(bp)) && |
019dbb4c VZ |
4693 | (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { |
4694 | /* | |
4695 | * Prevent local bottom-halves from running as | |
4696 | * we are going to change the local NAPI list. | |
4697 | */ | |
4698 | local_bh_disable(); | |
ec6ba945 | 4699 | napi_schedule(&bnx2x_fcoe(bp, napi)); |
019dbb4c VZ |
4700 | local_bh_enable(); |
4701 | } | |
ec6ba945 | 4702 | #endif |
523224a3 DK |
4703 | /* Handle EQ completions */ |
4704 | bnx2x_eq_int(bp); | |
4705 | ||
4706 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, | |
4707 | le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); | |
4708 | ||
4709 | status &= ~BNX2X_DEF_SB_IDX; | |
cdaa7cb8 VZ |
4710 | } |
4711 | ||
4712 | if (unlikely(status)) | |
51c1a580 | 4713 | DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n", |
cdaa7cb8 | 4714 | status); |
a2fbb9ea | 4715 | |
523224a3 DK |
4716 | bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, |
4717 | le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); | |
a2fbb9ea ET |
4718 | } |
4719 | ||
9f6c9258 | 4720 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
a2fbb9ea ET |
4721 | { |
4722 | struct net_device *dev = dev_instance; | |
4723 | struct bnx2x *bp = netdev_priv(dev); | |
4724 | ||
523224a3 DK |
4725 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, |
4726 | IGU_INT_DISABLE, 0); | |
a2fbb9ea ET |
4727 | |
4728 | #ifdef BNX2X_STOP_ON_ERROR | |
4729 | if (unlikely(bp->panic)) | |
4730 | return IRQ_HANDLED; | |
4731 | #endif | |
4732 | ||
993ac7b5 MC |
4733 | #ifdef BCM_CNIC |
4734 | { | |
4735 | struct cnic_ops *c_ops; | |
4736 | ||
4737 | rcu_read_lock(); | |
4738 | c_ops = rcu_dereference(bp->cnic_ops); | |
4739 | if (c_ops) | |
4740 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
4741 | rcu_read_unlock(); | |
4742 | } | |
4743 | #endif | |
1cf167f2 | 4744 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
a2fbb9ea ET |
4745 | |
4746 | return IRQ_HANDLED; | |
4747 | } | |
4748 | ||
4749 | /* end of slow path */ | |
4750 | ||
619c5cb6 VZ |
4751 | |
4752 | void bnx2x_drv_pulse(struct bnx2x *bp) | |
4753 | { | |
4754 | SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, | |
4755 | bp->fw_drv_pulse_wr_seq); | |
4756 | } | |
4757 | ||
4758 | ||
a2fbb9ea ET |
4759 | static void bnx2x_timer(unsigned long data) |
4760 | { | |
4761 | struct bnx2x *bp = (struct bnx2x *) data; | |
4762 | ||
4763 | if (!netif_running(bp->dev)) | |
4764 | return; | |
4765 | ||
34f80b04 | 4766 | if (!BP_NOMCP(bp)) { |
f2e0899f | 4767 | int mb_idx = BP_FW_MB_IDX(bp); |
a2fbb9ea ET |
4768 | u32 drv_pulse; |
4769 | u32 mcp_pulse; | |
4770 | ||
4771 | ++bp->fw_drv_pulse_wr_seq; | |
4772 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; | |
4773 | /* TBD - add SYSTEM_TIME */ | |
4774 | drv_pulse = bp->fw_drv_pulse_wr_seq; | |
619c5cb6 | 4775 | bnx2x_drv_pulse(bp); |
a2fbb9ea | 4776 | |
f2e0899f | 4777 | mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & |
a2fbb9ea ET |
4778 | MCP_PULSE_SEQ_MASK); |
4779 | /* The delta between driver pulse and mcp response | |
4780 | * should be 1 (before mcp response) or 0 (after mcp response) | |
4781 | */ | |
4782 | if ((drv_pulse != mcp_pulse) && | |
4783 | (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { | |
4784 | /* someone lost a heartbeat... */ | |
4785 | BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", | |
4786 | drv_pulse, mcp_pulse); | |
4787 | } | |
4788 | } | |
4789 | ||
f34d28ea | 4790 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a | 4791 | bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); |
a2fbb9ea | 4792 | |
a2fbb9ea ET |
4793 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
4794 | } | |
4795 | ||
4796 | /* end of Statistics */ | |
4797 | ||
4798 | /* nic init */ | |
4799 | ||
4800 | /* | |
4801 | * nic init service functions | |
4802 | */ | |
4803 | ||
523224a3 | 4804 | static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
a2fbb9ea | 4805 | { |
523224a3 DK |
4806 | u32 i; |
4807 | if (!(len%4) && !(addr%4)) | |
4808 | for (i = 0; i < len; i += 4) | |
4809 | REG_WR(bp, addr + i, fill); | |
4810 | else | |
4811 | for (i = 0; i < len; i++) | |
4812 | REG_WR8(bp, addr + i, fill); | |
34f80b04 | 4813 | |
34f80b04 EG |
4814 | } |
4815 | ||
523224a3 DK |
4816 | /* helper: writes FP SP data to FW - data_size in dwords */ |
4817 | static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, | |
4818 | int fw_sb_id, | |
4819 | u32 *sb_data_p, | |
4820 | u32 data_size) | |
34f80b04 | 4821 | { |
a2fbb9ea | 4822 | int index; |
523224a3 DK |
4823 | for (index = 0; index < data_size; index++) |
4824 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
4825 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + | |
4826 | sizeof(u32)*index, | |
4827 | *(sb_data_p + index)); | |
4828 | } | |
a2fbb9ea | 4829 | |
523224a3 DK |
4830 | static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) |
4831 | { | |
4832 | u32 *sb_data_p; | |
4833 | u32 data_size = 0; | |
f2e0899f | 4834 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 | 4835 | struct hc_status_block_data_e1x sb_data_e1x; |
a2fbb9ea | 4836 | |
523224a3 | 4837 | /* disable the function first */ |
619c5cb6 | 4838 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 4839 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 4840 | sb_data_e2.common.state = SB_DISABLED; |
f2e0899f DK |
4841 | sb_data_e2.common.p_func.vf_valid = false; |
4842 | sb_data_p = (u32 *)&sb_data_e2; | |
4843 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
4844 | } else { | |
4845 | memset(&sb_data_e1x, 0, | |
4846 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 4847 | sb_data_e1x.common.state = SB_DISABLED; |
f2e0899f DK |
4848 | sb_data_e1x.common.p_func.vf_valid = false; |
4849 | sb_data_p = (u32 *)&sb_data_e1x; | |
4850 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
4851 | } | |
523224a3 | 4852 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
a2fbb9ea | 4853 | |
523224a3 DK |
4854 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
4855 | CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, | |
4856 | CSTORM_STATUS_BLOCK_SIZE); | |
4857 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
4858 | CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, | |
4859 | CSTORM_SYNC_BLOCK_SIZE); | |
4860 | } | |
34f80b04 | 4861 | |
523224a3 DK |
4862 | /* helper: writes SP SB data to FW */ |
4863 | static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, | |
4864 | struct hc_sp_status_block_data *sp_sb_data) | |
4865 | { | |
4866 | int func = BP_FUNC(bp); | |
4867 | int i; | |
4868 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
4869 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
4870 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
4871 | i*sizeof(u32), | |
4872 | *((u32 *)sp_sb_data + i)); | |
34f80b04 EG |
4873 | } |
4874 | ||
523224a3 | 4875 | static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) |
34f80b04 EG |
4876 | { |
4877 | int func = BP_FUNC(bp); | |
523224a3 DK |
4878 | struct hc_sp_status_block_data sp_sb_data; |
4879 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
a2fbb9ea | 4880 | |
619c5cb6 | 4881 | sp_sb_data.state = SB_DISABLED; |
523224a3 DK |
4882 | sp_sb_data.p_func.vf_valid = false; |
4883 | ||
4884 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); | |
4885 | ||
4886 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
4887 | CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, | |
4888 | CSTORM_SP_STATUS_BLOCK_SIZE); | |
4889 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
4890 | CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, | |
4891 | CSTORM_SP_SYNC_BLOCK_SIZE); | |
4892 | ||
4893 | } | |
4894 | ||
4895 | ||
4896 | static inline | |
4897 | void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, | |
4898 | int igu_sb_id, int igu_seg_id) | |
4899 | { | |
4900 | hc_sm->igu_sb_id = igu_sb_id; | |
4901 | hc_sm->igu_seg_id = igu_seg_id; | |
4902 | hc_sm->timer_value = 0xFF; | |
4903 | hc_sm->time_to_expire = 0xFFFFFFFF; | |
a2fbb9ea ET |
4904 | } |
4905 | ||
150966ad AE |
4906 | |
4907 | /* allocates state machine ids. */ | |
4908 | static inline | |
4909 | void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) | |
4910 | { | |
4911 | /* zero out state machine indices */ | |
4912 | /* rx indices */ | |
4913 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
4914 | ||
4915 | /* tx indices */ | |
4916 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
4917 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; | |
4918 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; | |
4919 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; | |
4920 | ||
4921 | /* map indices */ | |
4922 | /* rx indices */ | |
4923 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= | |
4924 | SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
4925 | ||
4926 | /* tx indices */ | |
4927 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= | |
4928 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
4929 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= | |
4930 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
4931 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= | |
4932 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
4933 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= | |
4934 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
4935 | } | |
4936 | ||
8d96286a | 4937 | static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
523224a3 | 4938 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
a2fbb9ea | 4939 | { |
523224a3 DK |
4940 | int igu_seg_id; |
4941 | ||
f2e0899f | 4942 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
4943 | struct hc_status_block_data_e1x sb_data_e1x; |
4944 | struct hc_status_block_sm *hc_sm_p; | |
523224a3 DK |
4945 | int data_size; |
4946 | u32 *sb_data_p; | |
4947 | ||
f2e0899f DK |
4948 | if (CHIP_INT_MODE_IS_BC(bp)) |
4949 | igu_seg_id = HC_SEG_ACCESS_NORM; | |
4950 | else | |
4951 | igu_seg_id = IGU_SEG_ACCESS_NORM; | |
523224a3 DK |
4952 | |
4953 | bnx2x_zero_fp_sb(bp, fw_sb_id); | |
4954 | ||
619c5cb6 | 4955 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 4956 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 4957 | sb_data_e2.common.state = SB_ENABLED; |
f2e0899f DK |
4958 | sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); |
4959 | sb_data_e2.common.p_func.vf_id = vfid; | |
4960 | sb_data_e2.common.p_func.vf_valid = vf_valid; | |
4961 | sb_data_e2.common.p_func.vnic_id = BP_VN(bp); | |
4962 | sb_data_e2.common.same_igu_sb_1b = true; | |
4963 | sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); | |
4964 | sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); | |
4965 | hc_sm_p = sb_data_e2.common.state_machine; | |
f2e0899f DK |
4966 | sb_data_p = (u32 *)&sb_data_e2; |
4967 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
150966ad | 4968 | bnx2x_map_sb_state_machines(sb_data_e2.index_data); |
f2e0899f DK |
4969 | } else { |
4970 | memset(&sb_data_e1x, 0, | |
4971 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 4972 | sb_data_e1x.common.state = SB_ENABLED; |
f2e0899f DK |
4973 | sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); |
4974 | sb_data_e1x.common.p_func.vf_id = 0xff; | |
4975 | sb_data_e1x.common.p_func.vf_valid = false; | |
4976 | sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); | |
4977 | sb_data_e1x.common.same_igu_sb_1b = true; | |
4978 | sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); | |
4979 | sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); | |
4980 | hc_sm_p = sb_data_e1x.common.state_machine; | |
f2e0899f DK |
4981 | sb_data_p = (u32 *)&sb_data_e1x; |
4982 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
150966ad | 4983 | bnx2x_map_sb_state_machines(sb_data_e1x.index_data); |
f2e0899f | 4984 | } |
523224a3 DK |
4985 | |
4986 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], | |
4987 | igu_sb_id, igu_seg_id); | |
4988 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], | |
4989 | igu_sb_id, igu_seg_id); | |
4990 | ||
51c1a580 | 4991 | DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); |
523224a3 DK |
4992 | |
4993 | /* write indecies to HW */ | |
4994 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); | |
4995 | } | |
4996 | ||
619c5cb6 | 4997 | static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, |
523224a3 DK |
4998 | u16 tx_usec, u16 rx_usec) |
4999 | { | |
6383c0b3 | 5000 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, |
523224a3 | 5001 | false, rx_usec); |
6383c0b3 AE |
5002 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
5003 | HC_INDEX_ETH_TX_CQ_CONS_COS0, false, | |
5004 | tx_usec); | |
5005 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5006 | HC_INDEX_ETH_TX_CQ_CONS_COS1, false, | |
5007 | tx_usec); | |
5008 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5009 | HC_INDEX_ETH_TX_CQ_CONS_COS2, false, | |
5010 | tx_usec); | |
523224a3 | 5011 | } |
f2e0899f | 5012 | |
523224a3 DK |
5013 | static void bnx2x_init_def_sb(struct bnx2x *bp) |
5014 | { | |
5015 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
5016 | dma_addr_t mapping = bp->def_status_blk_mapping; | |
5017 | int igu_sp_sb_index; | |
5018 | int igu_seg_id; | |
34f80b04 EG |
5019 | int port = BP_PORT(bp); |
5020 | int func = BP_FUNC(bp); | |
f2eaeb58 | 5021 | int reg_offset, reg_offset_en5; |
a2fbb9ea | 5022 | u64 section; |
523224a3 DK |
5023 | int index; |
5024 | struct hc_sp_status_block_data sp_sb_data; | |
5025 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
5026 | ||
f2e0899f DK |
5027 | if (CHIP_INT_MODE_IS_BC(bp)) { |
5028 | igu_sp_sb_index = DEF_SB_IGU_ID; | |
5029 | igu_seg_id = HC_SEG_ACCESS_DEF; | |
5030 | } else { | |
5031 | igu_sp_sb_index = bp->igu_dsb_id; | |
5032 | igu_seg_id = IGU_SEG_ACCESS_DEF; | |
5033 | } | |
a2fbb9ea ET |
5034 | |
5035 | /* ATTN */ | |
523224a3 | 5036 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
a2fbb9ea | 5037 | atten_status_block); |
523224a3 | 5038 | def_sb->atten_status_block.status_block_id = igu_sp_sb_index; |
a2fbb9ea | 5039 | |
49d66772 ET |
5040 | bp->attn_state = 0; |
5041 | ||
a2fbb9ea ET |
5042 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
5043 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
f2eaeb58 DK |
5044 | reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : |
5045 | MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); | |
34f80b04 | 5046 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
523224a3 DK |
5047 | int sindex; |
5048 | /* take care of sig[0]..sig[4] */ | |
5049 | for (sindex = 0; sindex < 4; sindex++) | |
5050 | bp->attn_group[index].sig[sindex] = | |
5051 | REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); | |
f2e0899f | 5052 | |
619c5cb6 | 5053 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5054 | /* |
5055 | * enable5 is separate from the rest of the registers, | |
5056 | * and therefore the address skip is 4 | |
5057 | * and not 16 between the different groups | |
5058 | */ | |
5059 | bp->attn_group[index].sig[4] = REG_RD(bp, | |
f2eaeb58 | 5060 | reg_offset_en5 + 0x4*index); |
f2e0899f DK |
5061 | else |
5062 | bp->attn_group[index].sig[4] = 0; | |
a2fbb9ea ET |
5063 | } |
5064 | ||
f2e0899f DK |
5065 | if (bp->common.int_block == INT_BLOCK_HC) { |
5066 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : | |
5067 | HC_REG_ATTN_MSG0_ADDR_L); | |
5068 | ||
5069 | REG_WR(bp, reg_offset, U64_LO(section)); | |
5070 | REG_WR(bp, reg_offset + 4, U64_HI(section)); | |
619c5cb6 | 5071 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5072 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); |
5073 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); | |
5074 | } | |
a2fbb9ea | 5075 | |
523224a3 DK |
5076 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
5077 | sp_sb); | |
a2fbb9ea | 5078 | |
523224a3 | 5079 | bnx2x_zero_sp_sb(bp); |
a2fbb9ea | 5080 | |
619c5cb6 | 5081 | sp_sb_data.state = SB_ENABLED; |
523224a3 DK |
5082 | sp_sb_data.host_sb_addr.lo = U64_LO(section); |
5083 | sp_sb_data.host_sb_addr.hi = U64_HI(section); | |
5084 | sp_sb_data.igu_sb_id = igu_sp_sb_index; | |
5085 | sp_sb_data.igu_seg_id = igu_seg_id; | |
5086 | sp_sb_data.p_func.pf_id = func; | |
f2e0899f | 5087 | sp_sb_data.p_func.vnic_id = BP_VN(bp); |
523224a3 | 5088 | sp_sb_data.p_func.vf_id = 0xff; |
a2fbb9ea | 5089 | |
523224a3 | 5090 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
49d66772 | 5091 | |
523224a3 | 5092 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); |
a2fbb9ea ET |
5093 | } |
5094 | ||
9f6c9258 | 5095 | void bnx2x_update_coalesce(struct bnx2x *bp) |
a2fbb9ea | 5096 | { |
a2fbb9ea ET |
5097 | int i; |
5098 | ||
ec6ba945 | 5099 | for_each_eth_queue(bp, i) |
523224a3 | 5100 | bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, |
423cfa7e | 5101 | bp->tx_ticks, bp->rx_ticks); |
a2fbb9ea ET |
5102 | } |
5103 | ||
a2fbb9ea ET |
5104 | static void bnx2x_init_sp_ring(struct bnx2x *bp) |
5105 | { | |
a2fbb9ea | 5106 | spin_lock_init(&bp->spq_lock); |
6e30dd4e | 5107 | atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); |
a2fbb9ea | 5108 | |
a2fbb9ea | 5109 | bp->spq_prod_idx = 0; |
a2fbb9ea ET |
5110 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
5111 | bp->spq_prod_bd = bp->spq; | |
5112 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; | |
a2fbb9ea ET |
5113 | } |
5114 | ||
523224a3 | 5115 | static void bnx2x_init_eq_ring(struct bnx2x *bp) |
a2fbb9ea ET |
5116 | { |
5117 | int i; | |
523224a3 DK |
5118 | for (i = 1; i <= NUM_EQ_PAGES; i++) { |
5119 | union event_ring_elem *elem = | |
5120 | &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; | |
a2fbb9ea | 5121 | |
523224a3 DK |
5122 | elem->next_page.addr.hi = |
5123 | cpu_to_le32(U64_HI(bp->eq_mapping + | |
5124 | BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); | |
5125 | elem->next_page.addr.lo = | |
5126 | cpu_to_le32(U64_LO(bp->eq_mapping + | |
5127 | BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); | |
a2fbb9ea | 5128 | } |
523224a3 DK |
5129 | bp->eq_cons = 0; |
5130 | bp->eq_prod = NUM_EQ_DESC; | |
5131 | bp->eq_cons_sb = BNX2X_EQ_INDEX; | |
6e30dd4e VZ |
5132 | /* we want a warning message before it gets rought... */ |
5133 | atomic_set(&bp->eq_spq_left, | |
5134 | min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); | |
a2fbb9ea ET |
5135 | } |
5136 | ||
619c5cb6 VZ |
5137 | |
5138 | /* called with netif_addr_lock_bh() */ | |
5139 | void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, | |
5140 | unsigned long rx_mode_flags, | |
5141 | unsigned long rx_accept_flags, | |
5142 | unsigned long tx_accept_flags, | |
5143 | unsigned long ramrod_flags) | |
ab532cf3 | 5144 | { |
619c5cb6 VZ |
5145 | struct bnx2x_rx_mode_ramrod_params ramrod_param; |
5146 | int rc; | |
5147 | ||
5148 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
5149 | ||
5150 | /* Prepare ramrod parameters */ | |
5151 | ramrod_param.cid = 0; | |
5152 | ramrod_param.cl_id = cl_id; | |
5153 | ramrod_param.rx_mode_obj = &bp->rx_mode_obj; | |
5154 | ramrod_param.func_id = BP_FUNC(bp); | |
ab532cf3 | 5155 | |
619c5cb6 VZ |
5156 | ramrod_param.pstate = &bp->sp_state; |
5157 | ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; | |
ab532cf3 | 5158 | |
619c5cb6 VZ |
5159 | ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); |
5160 | ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); | |
5161 | ||
5162 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
5163 | ||
5164 | ramrod_param.ramrod_flags = ramrod_flags; | |
5165 | ramrod_param.rx_mode_flags = rx_mode_flags; | |
5166 | ||
5167 | ramrod_param.rx_accept_flags = rx_accept_flags; | |
5168 | ramrod_param.tx_accept_flags = tx_accept_flags; | |
5169 | ||
5170 | rc = bnx2x_config_rx_mode(bp, &ramrod_param); | |
5171 | if (rc < 0) { | |
5172 | BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); | |
5173 | return; | |
5174 | } | |
a2fbb9ea ET |
5175 | } |
5176 | ||
619c5cb6 VZ |
5177 | /* called with netif_addr_lock_bh() */ |
5178 | void bnx2x_set_storm_rx_mode(struct bnx2x *bp) | |
471de716 | 5179 | { |
619c5cb6 VZ |
5180 | unsigned long rx_mode_flags = 0, ramrod_flags = 0; |
5181 | unsigned long rx_accept_flags = 0, tx_accept_flags = 0; | |
471de716 | 5182 | |
619c5cb6 VZ |
5183 | #ifdef BCM_CNIC |
5184 | if (!NO_FCOE(bp)) | |
5185 | ||
5186 | /* Configure rx_mode of FCoE Queue */ | |
5187 | __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); | |
5188 | #endif | |
5189 | ||
5190 | switch (bp->rx_mode) { | |
5191 | case BNX2X_RX_MODE_NONE: | |
5192 | /* | |
5193 | * 'drop all' supersedes any accept flags that may have been | |
5194 | * passed to the function. | |
5195 | */ | |
5196 | break; | |
5197 | case BNX2X_RX_MODE_NORMAL: | |
5198 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5199 | __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); | |
5200 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5201 | ||
5202 | /* internal switching mode */ | |
5203 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5204 | __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); | |
5205 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5206 | ||
5207 | break; | |
5208 | case BNX2X_RX_MODE_ALLMULTI: | |
5209 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5210 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5211 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5212 | ||
5213 | /* internal switching mode */ | |
5214 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5215 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5216 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5217 | ||
5218 | break; | |
5219 | case BNX2X_RX_MODE_PROMISC: | |
5220 | /* According to deffinition of SI mode, iface in promisc mode | |
5221 | * should receive matched and unmatched (in resolution of port) | |
5222 | * unicast packets. | |
5223 | */ | |
5224 | __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); | |
5225 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5226 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5227 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5228 | ||
5229 | /* internal switching mode */ | |
5230 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5231 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5232 | ||
5233 | if (IS_MF_SI(bp)) | |
5234 | __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); | |
5235 | else | |
5236 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5237 | ||
5238 | break; | |
5239 | default: | |
5240 | BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); | |
5241 | return; | |
5242 | } | |
de832a55 | 5243 | |
619c5cb6 VZ |
5244 | if (bp->rx_mode != BNX2X_RX_MODE_NONE) { |
5245 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); | |
5246 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); | |
34f80b04 EG |
5247 | } |
5248 | ||
619c5cb6 VZ |
5249 | __set_bit(RAMROD_RX, &ramrod_flags); |
5250 | __set_bit(RAMROD_TX, &ramrod_flags); | |
5251 | ||
5252 | bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, | |
5253 | tx_accept_flags, ramrod_flags); | |
5254 | } | |
5255 | ||
5256 | static void bnx2x_init_internal_common(struct bnx2x *bp) | |
5257 | { | |
5258 | int i; | |
5259 | ||
0793f83f DK |
5260 | if (IS_MF_SI(bp)) |
5261 | /* | |
5262 | * In switch independent mode, the TSTORM needs to accept | |
5263 | * packets that failed classification, since approximate match | |
5264 | * mac addresses aren't written to NIG LLH | |
5265 | */ | |
5266 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5267 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); | |
619c5cb6 VZ |
5268 | else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ |
5269 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5270 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); | |
0793f83f | 5271 | |
523224a3 DK |
5272 | /* Zero this manually as its initialization is |
5273 | currently missing in the initTool */ | |
5274 | for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) | |
ca00392c | 5275 | REG_WR(bp, BAR_USTRORM_INTMEM + |
523224a3 | 5276 | USTORM_AGG_DATA_OFFSET + i * 4, 0); |
619c5cb6 | 5277 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5278 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, |
5279 | CHIP_INT_MODE_IS_BC(bp) ? | |
5280 | HC_IGU_BC_MODE : HC_IGU_NBC_MODE); | |
5281 | } | |
523224a3 | 5282 | } |
8a1c38d1 | 5283 | |
471de716 EG |
5284 | static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) |
5285 | { | |
5286 | switch (load_code) { | |
5287 | case FW_MSG_CODE_DRV_LOAD_COMMON: | |
f2e0899f | 5288 | case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: |
471de716 EG |
5289 | bnx2x_init_internal_common(bp); |
5290 | /* no break */ | |
5291 | ||
5292 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
619c5cb6 | 5293 | /* nothing to do */ |
471de716 EG |
5294 | /* no break */ |
5295 | ||
5296 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
523224a3 DK |
5297 | /* internal memory per function is |
5298 | initialized inside bnx2x_pf_init */ | |
471de716 EG |
5299 | break; |
5300 | ||
5301 | default: | |
5302 | BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); | |
5303 | break; | |
5304 | } | |
5305 | } | |
5306 | ||
619c5cb6 | 5307 | static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) |
523224a3 | 5308 | { |
6383c0b3 | 5309 | return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; |
619c5cb6 | 5310 | } |
523224a3 | 5311 | |
619c5cb6 VZ |
5312 | static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) |
5313 | { | |
6383c0b3 | 5314 | return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; |
619c5cb6 VZ |
5315 | } |
5316 | ||
5317 | static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) | |
5318 | { | |
5319 | if (CHIP_IS_E1x(fp->bp)) | |
5320 | return BP_L_ID(fp->bp) + fp->index; | |
5321 | else /* We want Client ID to be the same as IGU SB ID for 57712 */ | |
5322 | return bnx2x_fp_igu_sb_id(fp); | |
5323 | } | |
5324 | ||
6383c0b3 | 5325 | static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) |
619c5cb6 VZ |
5326 | { |
5327 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; | |
6383c0b3 | 5328 | u8 cos; |
619c5cb6 | 5329 | unsigned long q_type = 0; |
6383c0b3 | 5330 | u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; |
f233cafe | 5331 | fp->rx_queue = fp_idx; |
b3b83c3f | 5332 | fp->cid = fp_idx; |
619c5cb6 VZ |
5333 | fp->cl_id = bnx2x_fp_cl_id(fp); |
5334 | fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); | |
5335 | fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); | |
523224a3 | 5336 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 VZ |
5337 | fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); |
5338 | ||
523224a3 | 5339 | /* init shortcut */ |
619c5cb6 | 5340 | fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); |
7a752993 | 5341 | |
523224a3 DK |
5342 | /* Setup SB indicies */ |
5343 | fp->rx_cons_sb = BNX2X_RX_SB_INDEX; | |
523224a3 | 5344 | |
619c5cb6 VZ |
5345 | /* Configure Queue State object */ |
5346 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
5347 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
5348 | |
5349 | BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); | |
5350 | ||
5351 | /* init tx data */ | |
5352 | for_each_cos_in_tx_queue(fp, cos) { | |
5353 | bnx2x_init_txdata(bp, &fp->txdata[cos], | |
5354 | CID_COS_TO_TX_ONLY_CID(fp->cid, cos), | |
5355 | FP_COS_TO_TXQ(fp, cos), | |
5356 | BNX2X_TX_SB_INDEX_BASE + cos); | |
5357 | cids[cos] = fp->txdata[cos].cid; | |
5358 | } | |
5359 | ||
5360 | bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, | |
5361 | BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
5362 | bnx2x_sp_mapping(bp, q_rdata), q_type); | |
619c5cb6 VZ |
5363 | |
5364 | /** | |
5365 | * Configure classification DBs: Always enable Tx switching | |
5366 | */ | |
5367 | bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); | |
5368 | ||
51c1a580 | 5369 | DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", |
619c5cb6 | 5370 | fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, |
523224a3 DK |
5371 | fp->igu_sb_id); |
5372 | bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, | |
5373 | fp->fw_sb_id, fp->igu_sb_id); | |
5374 | ||
5375 | bnx2x_update_fpsb_idx(fp); | |
5376 | } | |
5377 | ||
9f6c9258 | 5378 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) |
a2fbb9ea ET |
5379 | { |
5380 | int i; | |
5381 | ||
ec6ba945 | 5382 | for_each_eth_queue(bp, i) |
6383c0b3 | 5383 | bnx2x_init_eth_fp(bp, i); |
37b091ba | 5384 | #ifdef BCM_CNIC |
ec6ba945 VZ |
5385 | if (!NO_FCOE(bp)) |
5386 | bnx2x_init_fcoe_fp(bp); | |
523224a3 DK |
5387 | |
5388 | bnx2x_init_sb(bp, bp->cnic_sb_mapping, | |
5389 | BNX2X_VF_ID_INVALID, false, | |
619c5cb6 | 5390 | bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); |
523224a3 | 5391 | |
37b091ba | 5392 | #endif |
a2fbb9ea | 5393 | |
020c7e3f YR |
5394 | /* Initialize MOD_ABS interrupts */ |
5395 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, | |
5396 | bp->common.shmem_base, bp->common.shmem2_base, | |
5397 | BP_PORT(bp)); | |
16119785 EG |
5398 | /* ensure status block indices were read */ |
5399 | rmb(); | |
5400 | ||
523224a3 | 5401 | bnx2x_init_def_sb(bp); |
5c862848 | 5402 | bnx2x_update_dsb_idx(bp); |
a2fbb9ea | 5403 | bnx2x_init_rx_rings(bp); |
523224a3 | 5404 | bnx2x_init_tx_rings(bp); |
a2fbb9ea | 5405 | bnx2x_init_sp_ring(bp); |
523224a3 | 5406 | bnx2x_init_eq_ring(bp); |
471de716 | 5407 | bnx2x_init_internal(bp, load_code); |
523224a3 | 5408 | bnx2x_pf_init(bp); |
0ef00459 EG |
5409 | bnx2x_stats_init(bp); |
5410 | ||
0ef00459 EG |
5411 | /* flush all before enabling interrupts */ |
5412 | mb(); | |
5413 | mmiowb(); | |
5414 | ||
615f8fd9 | 5415 | bnx2x_int_enable(bp); |
eb8da205 EG |
5416 | |
5417 | /* Check for SPIO5 */ | |
5418 | bnx2x_attn_int_deasserted0(bp, | |
5419 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & | |
5420 | AEU_INPUTS_ATTN_BITS_SPIO5); | |
a2fbb9ea ET |
5421 | } |
5422 | ||
5423 | /* end of nic init */ | |
5424 | ||
5425 | /* | |
5426 | * gzip service functions | |
5427 | */ | |
5428 | ||
5429 | static int bnx2x_gunzip_init(struct bnx2x *bp) | |
5430 | { | |
1a983142 FT |
5431 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
5432 | &bp->gunzip_mapping, GFP_KERNEL); | |
a2fbb9ea ET |
5433 | if (bp->gunzip_buf == NULL) |
5434 | goto gunzip_nomem1; | |
5435 | ||
5436 | bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); | |
5437 | if (bp->strm == NULL) | |
5438 | goto gunzip_nomem2; | |
5439 | ||
7ab24bfd | 5440 | bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); |
a2fbb9ea ET |
5441 | if (bp->strm->workspace == NULL) |
5442 | goto gunzip_nomem3; | |
5443 | ||
5444 | return 0; | |
5445 | ||
5446 | gunzip_nomem3: | |
5447 | kfree(bp->strm); | |
5448 | bp->strm = NULL; | |
5449 | ||
5450 | gunzip_nomem2: | |
1a983142 FT |
5451 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
5452 | bp->gunzip_mapping); | |
a2fbb9ea ET |
5453 | bp->gunzip_buf = NULL; |
5454 | ||
5455 | gunzip_nomem1: | |
51c1a580 | 5456 | BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); |
a2fbb9ea ET |
5457 | return -ENOMEM; |
5458 | } | |
5459 | ||
5460 | static void bnx2x_gunzip_end(struct bnx2x *bp) | |
5461 | { | |
b3b83c3f | 5462 | if (bp->strm) { |
7ab24bfd | 5463 | vfree(bp->strm->workspace); |
b3b83c3f DK |
5464 | kfree(bp->strm); |
5465 | bp->strm = NULL; | |
5466 | } | |
a2fbb9ea ET |
5467 | |
5468 | if (bp->gunzip_buf) { | |
1a983142 FT |
5469 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
5470 | bp->gunzip_mapping); | |
a2fbb9ea ET |
5471 | bp->gunzip_buf = NULL; |
5472 | } | |
5473 | } | |
5474 | ||
94a78b79 | 5475 | static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) |
a2fbb9ea ET |
5476 | { |
5477 | int n, rc; | |
5478 | ||
5479 | /* check gzip header */ | |
94a78b79 VZ |
5480 | if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { |
5481 | BNX2X_ERR("Bad gzip header\n"); | |
a2fbb9ea | 5482 | return -EINVAL; |
94a78b79 | 5483 | } |
a2fbb9ea ET |
5484 | |
5485 | n = 10; | |
5486 | ||
34f80b04 | 5487 | #define FNAME 0x8 |
a2fbb9ea ET |
5488 | |
5489 | if (zbuf[3] & FNAME) | |
5490 | while ((zbuf[n++] != 0) && (n < len)); | |
5491 | ||
94a78b79 | 5492 | bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; |
a2fbb9ea ET |
5493 | bp->strm->avail_in = len - n; |
5494 | bp->strm->next_out = bp->gunzip_buf; | |
5495 | bp->strm->avail_out = FW_BUF_SIZE; | |
5496 | ||
5497 | rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); | |
5498 | if (rc != Z_OK) | |
5499 | return rc; | |
5500 | ||
5501 | rc = zlib_inflate(bp->strm, Z_FINISH); | |
5502 | if ((rc != Z_OK) && (rc != Z_STREAM_END)) | |
7995c64e JP |
5503 | netdev_err(bp->dev, "Firmware decompression error: %s\n", |
5504 | bp->strm->msg); | |
a2fbb9ea ET |
5505 | |
5506 | bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); | |
5507 | if (bp->gunzip_outlen & 0x3) | |
51c1a580 MS |
5508 | netdev_err(bp->dev, |
5509 | "Firmware decompression error: gunzip_outlen (%d) not aligned\n", | |
cdaa7cb8 | 5510 | bp->gunzip_outlen); |
a2fbb9ea ET |
5511 | bp->gunzip_outlen >>= 2; |
5512 | ||
5513 | zlib_inflateEnd(bp->strm); | |
5514 | ||
5515 | if (rc == Z_STREAM_END) | |
5516 | return 0; | |
5517 | ||
5518 | return rc; | |
5519 | } | |
5520 | ||
5521 | /* nic load/unload */ | |
5522 | ||
5523 | /* | |
34f80b04 | 5524 | * General service functions |
a2fbb9ea ET |
5525 | */ |
5526 | ||
5527 | /* send a NIG loopback debug packet */ | |
5528 | static void bnx2x_lb_pckt(struct bnx2x *bp) | |
5529 | { | |
a2fbb9ea | 5530 | u32 wb_write[3]; |
a2fbb9ea ET |
5531 | |
5532 | /* Ethernet source and destination addresses */ | |
a2fbb9ea ET |
5533 | wb_write[0] = 0x55555555; |
5534 | wb_write[1] = 0x55555555; | |
34f80b04 | 5535 | wb_write[2] = 0x20; /* SOP */ |
a2fbb9ea | 5536 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
5537 | |
5538 | /* NON-IP protocol */ | |
a2fbb9ea ET |
5539 | wb_write[0] = 0x09000000; |
5540 | wb_write[1] = 0x55555555; | |
34f80b04 | 5541 | wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ |
a2fbb9ea | 5542 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
5543 | } |
5544 | ||
5545 | /* some of the internal memories | |
5546 | * are not directly readable from the driver | |
5547 | * to test them we send debug packets | |
5548 | */ | |
5549 | static int bnx2x_int_mem_test(struct bnx2x *bp) | |
5550 | { | |
5551 | int factor; | |
5552 | int count, i; | |
5553 | u32 val = 0; | |
5554 | ||
ad8d3948 | 5555 | if (CHIP_REV_IS_FPGA(bp)) |
a2fbb9ea | 5556 | factor = 120; |
ad8d3948 EG |
5557 | else if (CHIP_REV_IS_EMUL(bp)) |
5558 | factor = 200; | |
5559 | else | |
a2fbb9ea | 5560 | factor = 1; |
a2fbb9ea | 5561 | |
a2fbb9ea ET |
5562 | /* Disable inputs of parser neighbor blocks */ |
5563 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
5564 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
5565 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 5566 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
5567 | |
5568 | /* Write 0 to parser credits for CFC search request */ | |
5569 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
5570 | ||
5571 | /* send Ethernet packet */ | |
5572 | bnx2x_lb_pckt(bp); | |
5573 | ||
5574 | /* TODO do i reset NIG statistic? */ | |
5575 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
5576 | count = 1000 * factor; | |
5577 | while (count) { | |
34f80b04 | 5578 | |
a2fbb9ea ET |
5579 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
5580 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
5581 | if (val == 0x10) |
5582 | break; | |
5583 | ||
5584 | msleep(10); | |
5585 | count--; | |
5586 | } | |
5587 | if (val != 0x10) { | |
5588 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
5589 | return -1; | |
5590 | } | |
5591 | ||
5592 | /* Wait until PRS register shows 1 packet */ | |
5593 | count = 1000 * factor; | |
5594 | while (count) { | |
5595 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
a2fbb9ea ET |
5596 | if (val == 1) |
5597 | break; | |
5598 | ||
5599 | msleep(10); | |
5600 | count--; | |
5601 | } | |
5602 | if (val != 0x1) { | |
5603 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5604 | return -2; | |
5605 | } | |
5606 | ||
5607 | /* Reset and init BRB, PRS */ | |
34f80b04 | 5608 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
a2fbb9ea | 5609 | msleep(50); |
34f80b04 | 5610 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
a2fbb9ea | 5611 | msleep(50); |
619c5cb6 VZ |
5612 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
5613 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
a2fbb9ea ET |
5614 | |
5615 | DP(NETIF_MSG_HW, "part2\n"); | |
5616 | ||
5617 | /* Disable inputs of parser neighbor blocks */ | |
5618 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
5619 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
5620 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 5621 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
5622 | |
5623 | /* Write 0 to parser credits for CFC search request */ | |
5624 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
5625 | ||
5626 | /* send 10 Ethernet packets */ | |
5627 | for (i = 0; i < 10; i++) | |
5628 | bnx2x_lb_pckt(bp); | |
5629 | ||
5630 | /* Wait until NIG register shows 10 + 1 | |
5631 | packets of size 11*0x10 = 0xb0 */ | |
5632 | count = 1000 * factor; | |
5633 | while (count) { | |
34f80b04 | 5634 | |
a2fbb9ea ET |
5635 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
5636 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
5637 | if (val == 0xb0) |
5638 | break; | |
5639 | ||
5640 | msleep(10); | |
5641 | count--; | |
5642 | } | |
5643 | if (val != 0xb0) { | |
5644 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
5645 | return -3; | |
5646 | } | |
5647 | ||
5648 | /* Wait until PRS register shows 2 packets */ | |
5649 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
5650 | if (val != 2) | |
5651 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5652 | ||
5653 | /* Write 1 to parser credits for CFC search request */ | |
5654 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); | |
5655 | ||
5656 | /* Wait until PRS register shows 3 packets */ | |
5657 | msleep(10 * factor); | |
5658 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
5659 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
5660 | if (val != 3) | |
5661 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5662 | ||
5663 | /* clear NIG EOP FIFO */ | |
5664 | for (i = 0; i < 11; i++) | |
5665 | REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); | |
5666 | val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); | |
5667 | if (val != 1) { | |
5668 | BNX2X_ERR("clear of NIG failed\n"); | |
5669 | return -4; | |
5670 | } | |
5671 | ||
5672 | /* Reset and init BRB, PRS, NIG */ | |
5673 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); | |
5674 | msleep(50); | |
5675 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); | |
5676 | msleep(50); | |
619c5cb6 VZ |
5677 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
5678 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
37b091ba | 5679 | #ifndef BCM_CNIC |
a2fbb9ea ET |
5680 | /* set NIC mode */ |
5681 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
5682 | #endif | |
5683 | ||
5684 | /* Enable inputs of parser neighbor blocks */ | |
5685 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); | |
5686 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); | |
5687 | REG_WR(bp, CFC_REG_DEBUG0, 0x0); | |
3196a88a | 5688 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); |
a2fbb9ea ET |
5689 | |
5690 | DP(NETIF_MSG_HW, "done\n"); | |
5691 | ||
5692 | return 0; /* OK */ | |
5693 | } | |
5694 | ||
4a33bc03 | 5695 | static void bnx2x_enable_blocks_attention(struct bnx2x *bp) |
a2fbb9ea ET |
5696 | { |
5697 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
619c5cb6 | 5698 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5699 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); |
5700 | else | |
5701 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); | |
a2fbb9ea ET |
5702 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
5703 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
f2e0899f DK |
5704 | /* |
5705 | * mask read length error interrupts in brb for parser | |
5706 | * (parsing unit and 'checksum and crc' unit) | |
5707 | * these errors are legal (PU reads fixed length and CAC can cause | |
5708 | * read length error on truncated packets) | |
5709 | */ | |
5710 | REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); | |
a2fbb9ea ET |
5711 | REG_WR(bp, QM_REG_QM_INT_MASK, 0); |
5712 | REG_WR(bp, TM_REG_TM_INT_MASK, 0); | |
5713 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); | |
5714 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); | |
5715 | REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); | |
34f80b04 EG |
5716 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ |
5717 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
5718 | REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); |
5719 | REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); | |
5720 | REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); | |
34f80b04 EG |
5721 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ |
5722 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
5723 | REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); |
5724 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); | |
5725 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); | |
5726 | REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); | |
34f80b04 EG |
5727 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ |
5728 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ | |
f85582f8 | 5729 | |
34f80b04 EG |
5730 | if (CHIP_REV_IS_FPGA(bp)) |
5731 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); | |
619c5cb6 | 5732 | else if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5733 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, |
5734 | (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | |
5735 | | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | |
5736 | | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN | |
5737 | | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | |
5738 | | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); | |
34f80b04 EG |
5739 | else |
5740 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); | |
a2fbb9ea ET |
5741 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); |
5742 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); | |
5743 | REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); | |
34f80b04 | 5744 | /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ |
619c5cb6 VZ |
5745 | |
5746 | if (!CHIP_IS_E1x(bp)) | |
5747 | /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ | |
5748 | REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); | |
5749 | ||
a2fbb9ea ET |
5750 | REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); |
5751 | REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); | |
34f80b04 | 5752 | /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ |
4a33bc03 | 5753 | REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ |
a2fbb9ea ET |
5754 | } |
5755 | ||
81f75bbf EG |
5756 | static void bnx2x_reset_common(struct bnx2x *bp) |
5757 | { | |
619c5cb6 VZ |
5758 | u32 val = 0x1400; |
5759 | ||
81f75bbf EG |
5760 | /* reset_common */ |
5761 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
5762 | 0xd3ffff7f); | |
619c5cb6 VZ |
5763 | |
5764 | if (CHIP_IS_E3(bp)) { | |
5765 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
5766 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
5767 | } | |
5768 | ||
5769 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); | |
5770 | } | |
5771 | ||
5772 | static void bnx2x_setup_dmae(struct bnx2x *bp) | |
5773 | { | |
5774 | bp->dmae_ready = 0; | |
5775 | spin_lock_init(&bp->dmae_lock); | |
81f75bbf EG |
5776 | } |
5777 | ||
573f2035 EG |
5778 | static void bnx2x_init_pxp(struct bnx2x *bp) |
5779 | { | |
5780 | u16 devctl; | |
5781 | int r_order, w_order; | |
5782 | ||
5783 | pci_read_config_word(bp->pdev, | |
b6c2f86e | 5784 | pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); |
573f2035 EG |
5785 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
5786 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | |
5787 | if (bp->mrrs == -1) | |
5788 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
5789 | else { | |
5790 | DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); | |
5791 | r_order = bp->mrrs; | |
5792 | } | |
5793 | ||
5794 | bnx2x_init_pxp_arb(bp, r_order, w_order); | |
5795 | } | |
fd4ef40d EG |
5796 | |
5797 | static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) | |
5798 | { | |
2145a920 | 5799 | int is_required; |
fd4ef40d | 5800 | u32 val; |
2145a920 | 5801 | int port; |
fd4ef40d | 5802 | |
2145a920 VZ |
5803 | if (BP_NOMCP(bp)) |
5804 | return; | |
5805 | ||
5806 | is_required = 0; | |
fd4ef40d EG |
5807 | val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
5808 | SHARED_HW_CFG_FAN_FAILURE_MASK; | |
5809 | ||
5810 | if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) | |
5811 | is_required = 1; | |
5812 | ||
5813 | /* | |
5814 | * The fan failure mechanism is usually related to the PHY type since | |
5815 | * the power consumption of the board is affected by the PHY. Currently, | |
5816 | * fan is required for most designs with SFX7101, BCM8727 and BCM8481. | |
5817 | */ | |
5818 | else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) | |
5819 | for (port = PORT_0; port < PORT_MAX; port++) { | |
fd4ef40d | 5820 | is_required |= |
d90d96ba YR |
5821 | bnx2x_fan_failure_det_req( |
5822 | bp, | |
5823 | bp->common.shmem_base, | |
a22f0788 | 5824 | bp->common.shmem2_base, |
d90d96ba | 5825 | port); |
fd4ef40d EG |
5826 | } |
5827 | ||
5828 | DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); | |
5829 | ||
5830 | if (is_required == 0) | |
5831 | return; | |
5832 | ||
5833 | /* Fan failure is indicated by SPIO 5 */ | |
5834 | bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, | |
5835 | MISC_REGISTERS_SPIO_INPUT_HI_Z); | |
5836 | ||
5837 | /* set to active low mode */ | |
5838 | val = REG_RD(bp, MISC_REG_SPIO_INT); | |
5839 | val |= ((1 << MISC_REGISTERS_SPIO_5) << | |
cdaa7cb8 | 5840 | MISC_REGISTERS_SPIO_INT_OLD_SET_POS); |
fd4ef40d EG |
5841 | REG_WR(bp, MISC_REG_SPIO_INT, val); |
5842 | ||
5843 | /* enable interrupt to signal the IGU */ | |
5844 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
5845 | val |= (1 << MISC_REGISTERS_SPIO_5); | |
5846 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); | |
5847 | } | |
5848 | ||
f2e0899f DK |
5849 | static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) |
5850 | { | |
5851 | u32 offset = 0; | |
5852 | ||
5853 | if (CHIP_IS_E1(bp)) | |
5854 | return; | |
5855 | if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) | |
5856 | return; | |
5857 | ||
5858 | switch (BP_ABS_FUNC(bp)) { | |
5859 | case 0: | |
5860 | offset = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
5861 | break; | |
5862 | case 1: | |
5863 | offset = PXP2_REG_PGL_PRETEND_FUNC_F1; | |
5864 | break; | |
5865 | case 2: | |
5866 | offset = PXP2_REG_PGL_PRETEND_FUNC_F2; | |
5867 | break; | |
5868 | case 3: | |
5869 | offset = PXP2_REG_PGL_PRETEND_FUNC_F3; | |
5870 | break; | |
5871 | case 4: | |
5872 | offset = PXP2_REG_PGL_PRETEND_FUNC_F4; | |
5873 | break; | |
5874 | case 5: | |
5875 | offset = PXP2_REG_PGL_PRETEND_FUNC_F5; | |
5876 | break; | |
5877 | case 6: | |
5878 | offset = PXP2_REG_PGL_PRETEND_FUNC_F6; | |
5879 | break; | |
5880 | case 7: | |
5881 | offset = PXP2_REG_PGL_PRETEND_FUNC_F7; | |
5882 | break; | |
5883 | default: | |
5884 | return; | |
5885 | } | |
5886 | ||
5887 | REG_WR(bp, offset, pretend_func_num); | |
5888 | REG_RD(bp, offset); | |
5889 | DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); | |
5890 | } | |
5891 | ||
c9ee9206 | 5892 | void bnx2x_pf_disable(struct bnx2x *bp) |
f2e0899f DK |
5893 | { |
5894 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
5895 | val &= ~IGU_PF_CONF_FUNC_EN; | |
5896 | ||
5897 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
5898 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
5899 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); | |
5900 | } | |
5901 | ||
619c5cb6 VZ |
5902 | static inline void bnx2x__common_init_phy(struct bnx2x *bp) |
5903 | { | |
5904 | u32 shmem_base[2], shmem2_base[2]; | |
5905 | shmem_base[0] = bp->common.shmem_base; | |
5906 | shmem2_base[0] = bp->common.shmem2_base; | |
5907 | if (!CHIP_IS_E1x(bp)) { | |
5908 | shmem_base[1] = | |
5909 | SHMEM2_RD(bp, other_shmem_base_addr); | |
5910 | shmem2_base[1] = | |
5911 | SHMEM2_RD(bp, other_shmem2_base_addr); | |
5912 | } | |
5913 | bnx2x_acquire_phy_lock(bp); | |
5914 | bnx2x_common_init_phy(bp, shmem_base, shmem2_base, | |
5915 | bp->common.chip_id); | |
5916 | bnx2x_release_phy_lock(bp); | |
5917 | } | |
5918 | ||
5919 | /** | |
5920 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. | |
5921 | * | |
5922 | * @bp: driver handle | |
5923 | */ | |
5924 | static int bnx2x_init_hw_common(struct bnx2x *bp) | |
a2fbb9ea | 5925 | { |
619c5cb6 | 5926 | u32 val; |
a2fbb9ea | 5927 | |
51c1a580 | 5928 | DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); |
a2fbb9ea | 5929 | |
2031bd3a DK |
5930 | /* |
5931 | * take the UNDI lock to protect undi_unload flow from accessing | |
5932 | * registers while we're resetting the chip | |
5933 | */ | |
7a06a122 | 5934 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 5935 | |
81f75bbf | 5936 | bnx2x_reset_common(bp); |
34f80b04 | 5937 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
a2fbb9ea | 5938 | |
619c5cb6 VZ |
5939 | val = 0xfffc; |
5940 | if (CHIP_IS_E3(bp)) { | |
5941 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
5942 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
5943 | } | |
5944 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); | |
5945 | ||
7a06a122 | 5946 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 5947 | |
619c5cb6 | 5948 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); |
a2fbb9ea | 5949 | |
619c5cb6 VZ |
5950 | if (!CHIP_IS_E1x(bp)) { |
5951 | u8 abs_func_id; | |
f2e0899f DK |
5952 | |
5953 | /** | |
5954 | * 4-port mode or 2-port mode we need to turn of master-enable | |
5955 | * for everyone, after that, turn it back on for self. | |
5956 | * so, we disregard multi-function or not, and always disable | |
5957 | * for all functions on the given path, this means 0,2,4,6 for | |
5958 | * path 0 and 1,3,5,7 for path 1 | |
5959 | */ | |
619c5cb6 VZ |
5960 | for (abs_func_id = BP_PATH(bp); |
5961 | abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { | |
5962 | if (abs_func_id == BP_ABS_FUNC(bp)) { | |
f2e0899f DK |
5963 | REG_WR(bp, |
5964 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, | |
5965 | 1); | |
5966 | continue; | |
5967 | } | |
5968 | ||
619c5cb6 | 5969 | bnx2x_pretend_func(bp, abs_func_id); |
f2e0899f DK |
5970 | /* clear pf enable */ |
5971 | bnx2x_pf_disable(bp); | |
5972 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
5973 | } | |
5974 | } | |
a2fbb9ea | 5975 | |
619c5cb6 | 5976 | bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); |
34f80b04 EG |
5977 | if (CHIP_IS_E1(bp)) { |
5978 | /* enable HW interrupt from PXP on USDM overflow | |
5979 | bit 16 on INT_MASK_0 */ | |
5980 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
5981 | } | |
a2fbb9ea | 5982 | |
619c5cb6 | 5983 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
34f80b04 | 5984 | bnx2x_init_pxp(bp); |
a2fbb9ea ET |
5985 | |
5986 | #ifdef __BIG_ENDIAN | |
34f80b04 EG |
5987 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); |
5988 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); | |
5989 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); | |
5990 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); | |
5991 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); | |
8badd27a EG |
5992 | /* make sure this value is 0 */ |
5993 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | |
34f80b04 EG |
5994 | |
5995 | /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ | |
5996 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); | |
5997 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); | |
5998 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); | |
5999 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); | |
a2fbb9ea ET |
6000 | #endif |
6001 | ||
523224a3 DK |
6002 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
6003 | ||
34f80b04 EG |
6004 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
6005 | REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); | |
a2fbb9ea | 6006 | |
34f80b04 EG |
6007 | /* let the HW do it's magic ... */ |
6008 | msleep(100); | |
6009 | /* finish PXP init */ | |
6010 | val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); | |
6011 | if (val != 1) { | |
6012 | BNX2X_ERR("PXP2 CFG failed\n"); | |
6013 | return -EBUSY; | |
6014 | } | |
6015 | val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); | |
6016 | if (val != 1) { | |
6017 | BNX2X_ERR("PXP2 RD_INIT failed\n"); | |
6018 | return -EBUSY; | |
6019 | } | |
a2fbb9ea | 6020 | |
f2e0899f DK |
6021 | /* Timers bug workaround E2 only. We need to set the entire ILT to |
6022 | * have entries with value "0" and valid bit on. | |
6023 | * This needs to be done by the first PF that is loaded in a path | |
6024 | * (i.e. common phase) | |
6025 | */ | |
619c5cb6 VZ |
6026 | if (!CHIP_IS_E1x(bp)) { |
6027 | /* In E2 there is a bug in the timers block that can cause function 6 / 7 | |
6028 | * (i.e. vnic3) to start even if it is marked as "scan-off". | |
6029 | * This occurs when a different function (func2,3) is being marked | |
6030 | * as "scan-off". Real-life scenario for example: if a driver is being | |
6031 | * load-unloaded while func6,7 are down. This will cause the timer to access | |
6032 | * the ilt, translate to a logical address and send a request to read/write. | |
6033 | * Since the ilt for the function that is down is not valid, this will cause | |
6034 | * a translation error which is unrecoverable. | |
6035 | * The Workaround is intended to make sure that when this happens nothing fatal | |
6036 | * will occur. The workaround: | |
6037 | * 1. First PF driver which loads on a path will: | |
6038 | * a. After taking the chip out of reset, by using pretend, | |
6039 | * it will write "0" to the following registers of | |
6040 | * the other vnics. | |
6041 | * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6042 | * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); | |
6043 | * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); | |
6044 | * And for itself it will write '1' to | |
6045 | * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable | |
6046 | * dmae-operations (writing to pram for example.) | |
6047 | * note: can be done for only function 6,7 but cleaner this | |
6048 | * way. | |
6049 | * b. Write zero+valid to the entire ILT. | |
6050 | * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of | |
6051 | * VNIC3 (of that port). The range allocated will be the | |
6052 | * entire ILT. This is needed to prevent ILT range error. | |
6053 | * 2. Any PF driver load flow: | |
6054 | * a. ILT update with the physical addresses of the allocated | |
6055 | * logical pages. | |
6056 | * b. Wait 20msec. - note that this timeout is needed to make | |
6057 | * sure there are no requests in one of the PXP internal | |
6058 | * queues with "old" ILT addresses. | |
6059 | * c. PF enable in the PGLC. | |
6060 | * d. Clear the was_error of the PF in the PGLC. (could have | |
6061 | * occured while driver was down) | |
6062 | * e. PF enable in the CFC (WEAK + STRONG) | |
6063 | * f. Timers scan enable | |
6064 | * 3. PF driver unload flow: | |
6065 | * a. Clear the Timers scan_en. | |
6066 | * b. Polling for scan_on=0 for that PF. | |
6067 | * c. Clear the PF enable bit in the PXP. | |
6068 | * d. Clear the PF enable in the CFC (WEAK + STRONG) | |
6069 | * e. Write zero+valid to all ILT entries (The valid bit must | |
6070 | * stay set) | |
6071 | * f. If this is VNIC 3 of a port then also init | |
6072 | * first_timers_ilt_entry to zero and last_timers_ilt_entry | |
6073 | * to the last enrty in the ILT. | |
6074 | * | |
6075 | * Notes: | |
6076 | * Currently the PF error in the PGLC is non recoverable. | |
6077 | * In the future the there will be a recovery routine for this error. | |
6078 | * Currently attention is masked. | |
6079 | * Having an MCP lock on the load/unload process does not guarantee that | |
6080 | * there is no Timer disable during Func6/7 enable. This is because the | |
6081 | * Timers scan is currently being cleared by the MCP on FLR. | |
6082 | * Step 2.d can be done only for PF6/7 and the driver can also check if | |
6083 | * there is error before clearing it. But the flow above is simpler and | |
6084 | * more general. | |
6085 | * All ILT entries are written by zero+valid and not just PF6/7 | |
6086 | * ILT entries since in the future the ILT entries allocation for | |
6087 | * PF-s might be dynamic. | |
6088 | */ | |
f2e0899f DK |
6089 | struct ilt_client_info ilt_cli; |
6090 | struct bnx2x_ilt ilt; | |
6091 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
6092 | memset(&ilt, 0, sizeof(struct bnx2x_ilt)); | |
6093 | ||
b595076a | 6094 | /* initialize dummy TM client */ |
f2e0899f DK |
6095 | ilt_cli.start = 0; |
6096 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
6097 | ilt_cli.client_num = ILT_CLIENT_TM; | |
6098 | ||
6099 | /* Step 1: set zeroes to all ilt page entries with valid bit on | |
6100 | * Step 2: set the timers first/last ilt entry to point | |
6101 | * to the entire range to prevent ILT range error for 3rd/4th | |
619c5cb6 | 6102 | * vnic (this code assumes existance of the vnic) |
f2e0899f DK |
6103 | * |
6104 | * both steps performed by call to bnx2x_ilt_client_init_op() | |
6105 | * with dummy TM client | |
6106 | * | |
6107 | * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT | |
6108 | * and his brother are split registers | |
6109 | */ | |
6110 | bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); | |
6111 | bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); | |
6112 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
6113 | ||
6114 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); | |
6115 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); | |
6116 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); | |
6117 | } | |
6118 | ||
6119 | ||
34f80b04 EG |
6120 | REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); |
6121 | REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); | |
a2fbb9ea | 6122 | |
619c5cb6 | 6123 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6124 | int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : |
6125 | (CHIP_REV_IS_FPGA(bp) ? 400 : 0); | |
619c5cb6 | 6126 | bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); |
f2e0899f | 6127 | |
619c5cb6 | 6128 | bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); |
f2e0899f DK |
6129 | |
6130 | /* let the HW do it's magic ... */ | |
6131 | do { | |
6132 | msleep(200); | |
6133 | val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); | |
6134 | } while (factor-- && (val != 1)); | |
6135 | ||
6136 | if (val != 1) { | |
6137 | BNX2X_ERR("ATC_INIT failed\n"); | |
6138 | return -EBUSY; | |
6139 | } | |
6140 | } | |
6141 | ||
619c5cb6 | 6142 | bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); |
a2fbb9ea | 6143 | |
34f80b04 EG |
6144 | /* clean the DMAE memory */ |
6145 | bp->dmae_ready = 1; | |
619c5cb6 VZ |
6146 | bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); |
6147 | ||
6148 | bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); | |
6149 | ||
6150 | bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); | |
6151 | ||
6152 | bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); | |
a2fbb9ea | 6153 | |
619c5cb6 | 6154 | bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); |
a2fbb9ea | 6155 | |
34f80b04 EG |
6156 | bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); |
6157 | bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); | |
6158 | bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); | |
6159 | bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); | |
6160 | ||
619c5cb6 | 6161 | bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); |
37b091ba | 6162 | |
f85582f8 | 6163 | |
523224a3 DK |
6164 | /* QM queues pointers table */ |
6165 | bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); | |
6166 | ||
34f80b04 EG |
6167 | /* soft reset pulse */ |
6168 | REG_WR(bp, QM_REG_SOFT_RESET, 1); | |
6169 | REG_WR(bp, QM_REG_SOFT_RESET, 0); | |
a2fbb9ea | 6170 | |
37b091ba | 6171 | #ifdef BCM_CNIC |
619c5cb6 | 6172 | bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); |
a2fbb9ea | 6173 | #endif |
a2fbb9ea | 6174 | |
619c5cb6 | 6175 | bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); |
523224a3 | 6176 | REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); |
619c5cb6 | 6177 | if (!CHIP_REV_IS_SLOW(bp)) |
34f80b04 EG |
6178 | /* enable hw interrupt from doorbell Q */ |
6179 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); | |
a2fbb9ea | 6180 | |
619c5cb6 | 6181 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
f2e0899f | 6182 | |
619c5cb6 | 6183 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
26c8fa4d | 6184 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
619c5cb6 | 6185 | |
f2e0899f | 6186 | if (!CHIP_IS_E1(bp)) |
619c5cb6 | 6187 | REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); |
f85582f8 | 6188 | |
619c5cb6 VZ |
6189 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) |
6190 | /* Bit-map indicating which L2 hdrs may appear | |
6191 | * after the basic Ethernet header | |
6192 | */ | |
6193 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, | |
6194 | bp->path_has_ovlan ? 7 : 6); | |
a2fbb9ea | 6195 | |
619c5cb6 VZ |
6196 | bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); |
6197 | bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); | |
6198 | bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); | |
6199 | bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); | |
a2fbb9ea | 6200 | |
619c5cb6 VZ |
6201 | if (!CHIP_IS_E1x(bp)) { |
6202 | /* reset VFC memories */ | |
6203 | REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6204 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6205 | VFC_MEMORIES_RST_REG_RAM_RST); | |
6206 | REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6207 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6208 | VFC_MEMORIES_RST_REG_RAM_RST); | |
a2fbb9ea | 6209 | |
619c5cb6 VZ |
6210 | msleep(20); |
6211 | } | |
a2fbb9ea | 6212 | |
619c5cb6 VZ |
6213 | bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); |
6214 | bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); | |
6215 | bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); | |
6216 | bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); | |
f2e0899f | 6217 | |
34f80b04 EG |
6218 | /* sync semi rtc */ |
6219 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6220 | 0x80000000); | |
6221 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
6222 | 0x80000000); | |
a2fbb9ea | 6223 | |
619c5cb6 VZ |
6224 | bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); |
6225 | bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); | |
6226 | bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); | |
a2fbb9ea | 6227 | |
619c5cb6 VZ |
6228 | if (!CHIP_IS_E1x(bp)) |
6229 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, | |
6230 | bp->path_has_ovlan ? 7 : 6); | |
f2e0899f | 6231 | |
34f80b04 | 6232 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
f85582f8 | 6233 | |
619c5cb6 VZ |
6234 | bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); |
6235 | ||
37b091ba MC |
6236 | #ifdef BCM_CNIC |
6237 | REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); | |
6238 | REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); | |
6239 | REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); | |
6240 | REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); | |
6241 | REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); | |
6242 | REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); | |
6243 | REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); | |
6244 | REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); | |
6245 | REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); | |
6246 | REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); | |
6247 | #endif | |
34f80b04 | 6248 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
a2fbb9ea | 6249 | |
34f80b04 EG |
6250 | if (sizeof(union cdu_context) != 1024) |
6251 | /* we currently assume that a context is 1024 bytes */ | |
51c1a580 MS |
6252 | dev_alert(&bp->pdev->dev, |
6253 | "please adjust the size of cdu_context(%ld)\n", | |
6254 | (long)sizeof(union cdu_context)); | |
a2fbb9ea | 6255 | |
619c5cb6 | 6256 | bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); |
34f80b04 EG |
6257 | val = (4 << 24) + (0 << 12) + 1024; |
6258 | REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); | |
a2fbb9ea | 6259 | |
619c5cb6 | 6260 | bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); |
34f80b04 | 6261 | REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); |
8d9c5f34 EG |
6262 | /* enable context validation interrupt from CFC */ |
6263 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
6264 | ||
6265 | /* set the thresholds to prevent CFC/CDU race */ | |
6266 | REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); | |
a2fbb9ea | 6267 | |
619c5cb6 | 6268 | bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); |
f2e0899f | 6269 | |
619c5cb6 | 6270 | if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) |
f2e0899f DK |
6271 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); |
6272 | ||
619c5cb6 VZ |
6273 | bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); |
6274 | bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); | |
a2fbb9ea | 6275 | |
34f80b04 EG |
6276 | /* Reset PCIE errors for debug */ |
6277 | REG_WR(bp, 0x2814, 0xffffffff); | |
6278 | REG_WR(bp, 0x3820, 0xffffffff); | |
a2fbb9ea | 6279 | |
619c5cb6 | 6280 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6281 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, |
6282 | (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | | |
6283 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); | |
6284 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, | |
6285 | (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | | |
6286 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | | |
6287 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); | |
6288 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, | |
6289 | (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | | |
6290 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | | |
6291 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); | |
6292 | } | |
6293 | ||
619c5cb6 | 6294 | bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); |
f2e0899f | 6295 | if (!CHIP_IS_E1(bp)) { |
619c5cb6 VZ |
6296 | /* in E3 this done in per-port section */ |
6297 | if (!CHIP_IS_E3(bp)) | |
6298 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
f2e0899f | 6299 | } |
619c5cb6 VZ |
6300 | if (CHIP_IS_E1H(bp)) |
6301 | /* not applicable for E2 (and above ...) */ | |
6302 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); | |
34f80b04 EG |
6303 | |
6304 | if (CHIP_REV_IS_SLOW(bp)) | |
6305 | msleep(200); | |
6306 | ||
6307 | /* finish CFC init */ | |
6308 | val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); | |
6309 | if (val != 1) { | |
6310 | BNX2X_ERR("CFC LL_INIT failed\n"); | |
6311 | return -EBUSY; | |
6312 | } | |
6313 | val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); | |
6314 | if (val != 1) { | |
6315 | BNX2X_ERR("CFC AC_INIT failed\n"); | |
6316 | return -EBUSY; | |
6317 | } | |
6318 | val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); | |
6319 | if (val != 1) { | |
6320 | BNX2X_ERR("CFC CAM_INIT failed\n"); | |
6321 | return -EBUSY; | |
6322 | } | |
6323 | REG_WR(bp, CFC_REG_DEBUG0, 0); | |
f1410647 | 6324 | |
f2e0899f DK |
6325 | if (CHIP_IS_E1(bp)) { |
6326 | /* read NIG statistic | |
6327 | to see if this is our first up since powerup */ | |
6328 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); | |
6329 | val = *bnx2x_sp(bp, wb_data[0]); | |
34f80b04 | 6330 | |
f2e0899f DK |
6331 | /* do internal memory self test */ |
6332 | if ((val == 0) && bnx2x_int_mem_test(bp)) { | |
6333 | BNX2X_ERR("internal mem self test failed\n"); | |
6334 | return -EBUSY; | |
6335 | } | |
34f80b04 EG |
6336 | } |
6337 | ||
fd4ef40d EG |
6338 | bnx2x_setup_fan_failure_detection(bp); |
6339 | ||
34f80b04 EG |
6340 | /* clear PXP2 attentions */ |
6341 | REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); | |
a2fbb9ea | 6342 | |
4a33bc03 | 6343 | bnx2x_enable_blocks_attention(bp); |
c9ee9206 | 6344 | bnx2x_enable_blocks_parity(bp); |
a2fbb9ea | 6345 | |
6bbca910 | 6346 | if (!BP_NOMCP(bp)) { |
619c5cb6 VZ |
6347 | if (CHIP_IS_E1x(bp)) |
6348 | bnx2x__common_init_phy(bp); | |
6bbca910 YR |
6349 | } else |
6350 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); | |
6351 | ||
34f80b04 EG |
6352 | return 0; |
6353 | } | |
a2fbb9ea | 6354 | |
619c5cb6 VZ |
6355 | /** |
6356 | * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. | |
6357 | * | |
6358 | * @bp: driver handle | |
6359 | */ | |
6360 | static int bnx2x_init_hw_common_chip(struct bnx2x *bp) | |
6361 | { | |
6362 | int rc = bnx2x_init_hw_common(bp); | |
6363 | ||
6364 | if (rc) | |
6365 | return rc; | |
6366 | ||
6367 | /* In E2 2-PORT mode, same ext phy is used for the two paths */ | |
6368 | if (!BP_NOMCP(bp)) | |
6369 | bnx2x__common_init_phy(bp); | |
6370 | ||
6371 | return 0; | |
6372 | } | |
6373 | ||
523224a3 | 6374 | static int bnx2x_init_hw_port(struct bnx2x *bp) |
34f80b04 EG |
6375 | { |
6376 | int port = BP_PORT(bp); | |
619c5cb6 | 6377 | int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; |
1c06328c | 6378 | u32 low, high; |
34f80b04 | 6379 | u32 val; |
a2fbb9ea | 6380 | |
619c5cb6 VZ |
6381 | bnx2x__link_reset(bp); |
6382 | ||
51c1a580 | 6383 | DP(NETIF_MSG_HW, "starting port init port %d\n", port); |
34f80b04 EG |
6384 | |
6385 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); | |
a2fbb9ea | 6386 | |
619c5cb6 VZ |
6387 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
6388 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); | |
6389 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
ca00392c | 6390 | |
f2e0899f DK |
6391 | /* Timers bug workaround: disables the pf_master bit in pglue at |
6392 | * common phase, we need to enable it here before any dmae access are | |
6393 | * attempted. Therefore we manually added the enable-master to the | |
6394 | * port phase (it also happens in the function phase) | |
6395 | */ | |
619c5cb6 | 6396 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6397 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
6398 | ||
619c5cb6 VZ |
6399 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
6400 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
6401 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); | |
6402 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
6403 | ||
6404 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
6405 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
6406 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
6407 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
a2fbb9ea | 6408 | |
523224a3 DK |
6409 | /* QM cid (connection) count */ |
6410 | bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); | |
a2fbb9ea | 6411 | |
523224a3 | 6412 | #ifdef BCM_CNIC |
619c5cb6 | 6413 | bnx2x_init_block(bp, BLOCK_TM, init_phase); |
37b091ba MC |
6414 | REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); |
6415 | REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); | |
a2fbb9ea | 6416 | #endif |
cdaa7cb8 | 6417 | |
619c5cb6 | 6418 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
f2e0899f DK |
6419 | |
6420 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { | |
619c5cb6 VZ |
6421 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
6422 | ||
6423 | if (IS_MF(bp)) | |
6424 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | |
6425 | else if (bp->dev->mtu > 4096) { | |
6426 | if (bp->flags & ONE_PORT_FLAG) | |
6427 | low = 160; | |
6428 | else { | |
6429 | val = bp->dev->mtu; | |
6430 | /* (24*1024 + val*4)/256 */ | |
6431 | low = 96 + (val/64) + | |
6432 | ((val % 64) ? 1 : 0); | |
6433 | } | |
6434 | } else | |
6435 | low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); | |
6436 | high = low + 56; /* 14*1024/256 */ | |
f2e0899f DK |
6437 | REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); |
6438 | REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); | |
1c06328c | 6439 | } |
1c06328c | 6440 | |
619c5cb6 VZ |
6441 | if (CHIP_MODE_IS_4_PORT(bp)) |
6442 | REG_WR(bp, (BP_PORT(bp) ? | |
6443 | BRB1_REG_MAC_GUARANTIED_1 : | |
6444 | BRB1_REG_MAC_GUARANTIED_0), 40); | |
1c06328c | 6445 | |
ca00392c | 6446 | |
619c5cb6 VZ |
6447 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
6448 | if (CHIP_IS_E3B0(bp)) | |
6449 | /* Ovlan exists only if we are in multi-function + | |
6450 | * switch-dependent mode, in switch-independent there | |
6451 | * is no ovlan headers | |
6452 | */ | |
6453 | REG_WR(bp, BP_PORT(bp) ? | |
6454 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
6455 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, | |
6456 | (bp->path_has_ovlan ? 7 : 6)); | |
356e2385 | 6457 | |
619c5cb6 VZ |
6458 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
6459 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
6460 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
6461 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
356e2385 | 6462 | |
619c5cb6 VZ |
6463 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
6464 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
6465 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
6466 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
34f80b04 | 6467 | |
619c5cb6 VZ |
6468 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
6469 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
a2fbb9ea | 6470 | |
619c5cb6 VZ |
6471 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
6472 | ||
6473 | if (CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
6474 | /* configure PBF to work without PAUSE mtu 9000 */ |
6475 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); | |
a2fbb9ea | 6476 | |
f2e0899f DK |
6477 | /* update threshold */ |
6478 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); | |
6479 | /* update init credit */ | |
6480 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); | |
a2fbb9ea | 6481 | |
f2e0899f DK |
6482 | /* probe changes */ |
6483 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); | |
6484 | udelay(50); | |
6485 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); | |
6486 | } | |
a2fbb9ea | 6487 | |
37b091ba | 6488 | #ifdef BCM_CNIC |
619c5cb6 | 6489 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); |
a2fbb9ea | 6490 | #endif |
619c5cb6 VZ |
6491 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
6492 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); | |
34f80b04 EG |
6493 | |
6494 | if (CHIP_IS_E1(bp)) { | |
6495 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
6496 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
6497 | } | |
619c5cb6 | 6498 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
34f80b04 | 6499 | |
619c5cb6 | 6500 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 6501 | |
619c5cb6 | 6502 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
34f80b04 EG |
6503 | /* init aeu_mask_attn_func_0/1: |
6504 | * - SF mode: bits 3-7 are masked. only bits 0-2 are in use | |
6505 | * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF | |
6506 | * bits 4-7 are used for "per vn group attention" */ | |
e4901dde VZ |
6507 | val = IS_MF(bp) ? 0xF7 : 0x7; |
6508 | /* Enable DCBX attention for all but E1 */ | |
6509 | val |= CHIP_IS_E1(bp) ? 0 : 0x10; | |
6510 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); | |
34f80b04 | 6511 | |
619c5cb6 VZ |
6512 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
6513 | ||
6514 | if (!CHIP_IS_E1x(bp)) { | |
6515 | /* Bit-map indicating which L2 hdrs may appear after the | |
6516 | * basic Ethernet header | |
6517 | */ | |
6518 | REG_WR(bp, BP_PORT(bp) ? | |
6519 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
6520 | NIG_REG_P0_HDRS_AFTER_BASIC, | |
6521 | IS_MF_SD(bp) ? 7 : 6); | |
6522 | ||
6523 | if (CHIP_IS_E3(bp)) | |
6524 | REG_WR(bp, BP_PORT(bp) ? | |
6525 | NIG_REG_LLH1_MF_MODE : | |
6526 | NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
6527 | } | |
6528 | if (!CHIP_IS_E3(bp)) | |
6529 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); | |
34f80b04 | 6530 | |
f2e0899f | 6531 | if (!CHIP_IS_E1(bp)) { |
fb3bff17 | 6532 | /* 0x2 disable mf_ov, 0x1 enable */ |
34f80b04 | 6533 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
0793f83f | 6534 | (IS_MF_SD(bp) ? 0x1 : 0x2)); |
34f80b04 | 6535 | |
619c5cb6 | 6536 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6537 | val = 0; |
6538 | switch (bp->mf_mode) { | |
6539 | case MULTI_FUNCTION_SD: | |
6540 | val = 1; | |
6541 | break; | |
6542 | case MULTI_FUNCTION_SI: | |
6543 | val = 2; | |
6544 | break; | |
6545 | } | |
6546 | ||
6547 | REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : | |
6548 | NIG_REG_LLH0_CLS_TYPE), val); | |
6549 | } | |
1c06328c EG |
6550 | { |
6551 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); | |
6552 | REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); | |
6553 | REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); | |
6554 | } | |
34f80b04 EG |
6555 | } |
6556 | ||
619c5cb6 VZ |
6557 | |
6558 | /* If SPIO5 is set to generate interrupts, enable it for this port */ | |
6559 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
6560 | if (val & (1 << MISC_REGISTERS_SPIO_5)) { | |
4d295db0 EG |
6561 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
6562 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
6563 | val = REG_RD(bp, reg_addr); | |
f1410647 | 6564 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
4d295db0 | 6565 | REG_WR(bp, reg_addr, val); |
f1410647 | 6566 | } |
a2fbb9ea | 6567 | |
34f80b04 EG |
6568 | return 0; |
6569 | } | |
6570 | ||
34f80b04 EG |
6571 | static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) |
6572 | { | |
6573 | int reg; | |
32d68de1 | 6574 | u32 wb_write[2]; |
34f80b04 | 6575 | |
f2e0899f | 6576 | if (CHIP_IS_E1(bp)) |
34f80b04 | 6577 | reg = PXP2_REG_RQ_ONCHIP_AT + index*8; |
f2e0899f DK |
6578 | else |
6579 | reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; | |
34f80b04 | 6580 | |
32d68de1 YM |
6581 | wb_write[0] = ONCHIP_ADDR1(addr); |
6582 | wb_write[1] = ONCHIP_ADDR2(addr); | |
6583 | REG_WR_DMAE(bp, reg, wb_write, 2); | |
34f80b04 EG |
6584 | } |
6585 | ||
f2e0899f DK |
6586 | static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) |
6587 | { | |
619c5cb6 | 6588 | bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); |
f2e0899f DK |
6589 | } |
6590 | ||
6591 | static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) | |
6592 | { | |
6593 | u32 i, base = FUNC_ILT_BASE(func); | |
6594 | for (i = base; i < base + ILT_PER_FUNC; i++) | |
6595 | bnx2x_ilt_wr(bp, i, 0); | |
6596 | } | |
6597 | ||
523224a3 | 6598 | static int bnx2x_init_hw_func(struct bnx2x *bp) |
34f80b04 EG |
6599 | { |
6600 | int port = BP_PORT(bp); | |
6601 | int func = BP_FUNC(bp); | |
619c5cb6 | 6602 | int init_phase = PHASE_PF0 + func; |
523224a3 DK |
6603 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
6604 | u16 cdu_ilt_start; | |
8badd27a | 6605 | u32 addr, val; |
f4a66897 | 6606 | u32 main_mem_base, main_mem_size, main_mem_prty_clr; |
89db4ad8 | 6607 | int i, main_mem_width, rc; |
34f80b04 | 6608 | |
51c1a580 | 6609 | DP(NETIF_MSG_HW, "starting func init func %d\n", func); |
34f80b04 | 6610 | |
619c5cb6 | 6611 | /* FLR cleanup - hmmm */ |
89db4ad8 AE |
6612 | if (!CHIP_IS_E1x(bp)) { |
6613 | rc = bnx2x_pf_flr_clnup(bp); | |
6614 | if (rc) | |
6615 | return rc; | |
6616 | } | |
619c5cb6 | 6617 | |
8badd27a | 6618 | /* set MSI reconfigure capability */ |
f2e0899f DK |
6619 | if (bp->common.int_block == INT_BLOCK_HC) { |
6620 | addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); | |
6621 | val = REG_RD(bp, addr); | |
6622 | val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; | |
6623 | REG_WR(bp, addr, val); | |
6624 | } | |
8badd27a | 6625 | |
619c5cb6 VZ |
6626 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
6627 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
6628 | ||
523224a3 DK |
6629 | ilt = BP_ILT(bp); |
6630 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
37b091ba | 6631 | |
523224a3 DK |
6632 | for (i = 0; i < L2_ILT_LINES(bp); i++) { |
6633 | ilt->lines[cdu_ilt_start + i].page = | |
6634 | bp->context.vcxt + (ILT_PAGE_CIDS * i); | |
6635 | ilt->lines[cdu_ilt_start + i].page_mapping = | |
6636 | bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); | |
6637 | /* cdu ilt pages are allocated manually so there's no need to | |
6638 | set the size */ | |
37b091ba | 6639 | } |
523224a3 | 6640 | bnx2x_ilt_init_op(bp, INITOP_SET); |
f85582f8 | 6641 | |
523224a3 DK |
6642 | #ifdef BCM_CNIC |
6643 | bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); | |
37b091ba | 6644 | |
523224a3 DK |
6645 | /* T1 hash bits value determines the T1 number of entries */ |
6646 | REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); | |
6647 | #endif | |
37b091ba | 6648 | |
523224a3 DK |
6649 | #ifndef BCM_CNIC |
6650 | /* set NIC mode */ | |
6651 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
6652 | #endif /* BCM_CNIC */ | |
37b091ba | 6653 | |
619c5cb6 | 6654 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6655 | u32 pf_conf = IGU_PF_CONF_FUNC_EN; |
6656 | ||
6657 | /* Turn on a single ISR mode in IGU if driver is going to use | |
6658 | * INT#x or MSI | |
6659 | */ | |
6660 | if (!(bp->flags & USING_MSIX_FLAG)) | |
6661 | pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; | |
6662 | /* | |
6663 | * Timers workaround bug: function init part. | |
6664 | * Need to wait 20msec after initializing ILT, | |
6665 | * needed to make sure there are no requests in | |
6666 | * one of the PXP internal queues with "old" ILT addresses | |
6667 | */ | |
6668 | msleep(20); | |
6669 | /* | |
6670 | * Master enable - Due to WB DMAE writes performed before this | |
6671 | * register is re-initialized as part of the regular function | |
6672 | * init | |
6673 | */ | |
6674 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
6675 | /* Enable the function in IGU */ | |
6676 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); | |
6677 | } | |
6678 | ||
523224a3 | 6679 | bp->dmae_ready = 1; |
34f80b04 | 6680 | |
619c5cb6 | 6681 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
523224a3 | 6682 | |
619c5cb6 | 6683 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6684 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); |
6685 | ||
619c5cb6 VZ |
6686 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
6687 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
6688 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); | |
6689 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
6690 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); | |
6691 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
6692 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
6693 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
6694 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
6695 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); | |
6696 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
6697 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
6698 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
6699 | ||
6700 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
6701 | REG_WR(bp, QM_REG_PF_EN, 1); |
6702 | ||
619c5cb6 VZ |
6703 | if (!CHIP_IS_E1x(bp)) { |
6704 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
6705 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
6706 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
6707 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
6708 | } | |
6709 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
6710 | ||
6711 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
6712 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); | |
6713 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); | |
6714 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); | |
6715 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); | |
6716 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
6717 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
6718 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
6719 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); | |
6720 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
6721 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); | |
6722 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
6723 | REG_WR(bp, PBF_REG_DISABLE_PF, 0); |
6724 | ||
619c5cb6 | 6725 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
523224a3 | 6726 | |
619c5cb6 | 6727 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
34f80b04 | 6728 | |
619c5cb6 | 6729 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6730 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); |
6731 | ||
fb3bff17 | 6732 | if (IS_MF(bp)) { |
34f80b04 | 6733 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); |
fb3bff17 | 6734 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); |
34f80b04 EG |
6735 | } |
6736 | ||
619c5cb6 | 6737 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
523224a3 | 6738 | |
34f80b04 | 6739 | /* HC init per function */ |
f2e0899f DK |
6740 | if (bp->common.int_block == INT_BLOCK_HC) { |
6741 | if (CHIP_IS_E1H(bp)) { | |
6742 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
6743 | ||
6744 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
6745 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
6746 | } | |
619c5cb6 | 6747 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
f2e0899f DK |
6748 | |
6749 | } else { | |
6750 | int num_segs, sb_idx, prod_offset; | |
6751 | ||
34f80b04 EG |
6752 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
6753 | ||
619c5cb6 | 6754 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6755 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
6756 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
6757 | } | |
6758 | ||
619c5cb6 | 6759 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 6760 | |
619c5cb6 | 6761 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6762 | int dsb_idx = 0; |
6763 | /** | |
6764 | * Producer memory: | |
6765 | * E2 mode: address 0-135 match to the mapping memory; | |
6766 | * 136 - PF0 default prod; 137 - PF1 default prod; | |
6767 | * 138 - PF2 default prod; 139 - PF3 default prod; | |
6768 | * 140 - PF0 attn prod; 141 - PF1 attn prod; | |
6769 | * 142 - PF2 attn prod; 143 - PF3 attn prod; | |
6770 | * 144-147 reserved. | |
6771 | * | |
6772 | * E1.5 mode - In backward compatible mode; | |
6773 | * for non default SB; each even line in the memory | |
6774 | * holds the U producer and each odd line hold | |
6775 | * the C producer. The first 128 producers are for | |
6776 | * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 | |
6777 | * producers are for the DSB for each PF. | |
6778 | * Each PF has five segments: (the order inside each | |
6779 | * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; | |
6780 | * 132-135 C prods; 136-139 X prods; 140-143 T prods; | |
6781 | * 144-147 attn prods; | |
6782 | */ | |
6783 | /* non-default-status-blocks */ | |
6784 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
6785 | IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; | |
6786 | for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { | |
6787 | prod_offset = (bp->igu_base_sb + sb_idx) * | |
6788 | num_segs; | |
6789 | ||
6790 | for (i = 0; i < num_segs; i++) { | |
6791 | addr = IGU_REG_PROD_CONS_MEMORY + | |
6792 | (prod_offset + i) * 4; | |
6793 | REG_WR(bp, addr, 0); | |
6794 | } | |
6795 | /* send consumer update with value 0 */ | |
6796 | bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, | |
6797 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
6798 | bnx2x_igu_clear_sb(bp, | |
6799 | bp->igu_base_sb + sb_idx); | |
6800 | } | |
6801 | ||
6802 | /* default-status-blocks */ | |
6803 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
6804 | IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; | |
6805 | ||
6806 | if (CHIP_MODE_IS_4_PORT(bp)) | |
6807 | dsb_idx = BP_FUNC(bp); | |
6808 | else | |
3395a033 | 6809 | dsb_idx = BP_VN(bp); |
f2e0899f DK |
6810 | |
6811 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? | |
6812 | IGU_BC_BASE_DSB_PROD + dsb_idx : | |
6813 | IGU_NORM_BASE_DSB_PROD + dsb_idx); | |
6814 | ||
3395a033 DK |
6815 | /* |
6816 | * igu prods come in chunks of E1HVN_MAX (4) - | |
6817 | * does not matters what is the current chip mode | |
6818 | */ | |
f2e0899f DK |
6819 | for (i = 0; i < (num_segs * E1HVN_MAX); |
6820 | i += E1HVN_MAX) { | |
6821 | addr = IGU_REG_PROD_CONS_MEMORY + | |
6822 | (prod_offset + i)*4; | |
6823 | REG_WR(bp, addr, 0); | |
6824 | } | |
6825 | /* send consumer update with 0 */ | |
6826 | if (CHIP_INT_MODE_IS_BC(bp)) { | |
6827 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6828 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
6829 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6830 | CSTORM_ID, 0, IGU_INT_NOP, 1); | |
6831 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6832 | XSTORM_ID, 0, IGU_INT_NOP, 1); | |
6833 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6834 | TSTORM_ID, 0, IGU_INT_NOP, 1); | |
6835 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6836 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
6837 | } else { | |
6838 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6839 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
6840 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6841 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
6842 | } | |
6843 | bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); | |
6844 | ||
6845 | /* !!! these should become driver const once | |
6846 | rf-tool supports split-68 const */ | |
6847 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); | |
6848 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); | |
6849 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); | |
6850 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); | |
6851 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); | |
6852 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); | |
6853 | } | |
34f80b04 | 6854 | } |
34f80b04 | 6855 | |
c14423fe | 6856 | /* Reset PCIE errors for debug */ |
a2fbb9ea ET |
6857 | REG_WR(bp, 0x2114, 0xffffffff); |
6858 | REG_WR(bp, 0x2120, 0xffffffff); | |
523224a3 | 6859 | |
f4a66897 VZ |
6860 | if (CHIP_IS_E1x(bp)) { |
6861 | main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ | |
6862 | main_mem_base = HC_REG_MAIN_MEMORY + | |
6863 | BP_PORT(bp) * (main_mem_size * 4); | |
6864 | main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; | |
6865 | main_mem_width = 8; | |
6866 | ||
6867 | val = REG_RD(bp, main_mem_prty_clr); | |
6868 | if (val) | |
51c1a580 MS |
6869 | DP(NETIF_MSG_HW, |
6870 | "Hmmm... Parity errors in HC block during function init (0x%x)!\n", | |
6871 | val); | |
f4a66897 VZ |
6872 | |
6873 | /* Clear "false" parity errors in MSI-X table */ | |
6874 | for (i = main_mem_base; | |
6875 | i < main_mem_base + main_mem_size * 4; | |
6876 | i += main_mem_width) { | |
6877 | bnx2x_read_dmae(bp, i, main_mem_width / 4); | |
6878 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), | |
6879 | i, main_mem_width / 4); | |
6880 | } | |
6881 | /* Clear HC parity attention */ | |
6882 | REG_RD(bp, main_mem_prty_clr); | |
6883 | } | |
6884 | ||
619c5cb6 VZ |
6885 | #ifdef BNX2X_STOP_ON_ERROR |
6886 | /* Enable STORMs SP logging */ | |
6887 | REG_WR8(bp, BAR_USTRORM_INTMEM + | |
6888 | USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
6889 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
6890 | TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
6891 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
6892 | CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
6893 | REG_WR8(bp, BAR_XSTRORM_INTMEM + | |
6894 | XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
6895 | #endif | |
6896 | ||
b7737c9b | 6897 | bnx2x_phy_probe(&bp->link_params); |
f85582f8 | 6898 | |
34f80b04 EG |
6899 | return 0; |
6900 | } | |
6901 | ||
a2fbb9ea | 6902 | |
9f6c9258 | 6903 | void bnx2x_free_mem(struct bnx2x *bp) |
a2fbb9ea | 6904 | { |
a2fbb9ea | 6905 | /* fastpath */ |
b3b83c3f | 6906 | bnx2x_free_fp_mem(bp); |
a2fbb9ea ET |
6907 | /* end of fastpath */ |
6908 | ||
6909 | BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, | |
523224a3 | 6910 | sizeof(struct host_sp_status_block)); |
a2fbb9ea | 6911 | |
619c5cb6 VZ |
6912 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, |
6913 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
6914 | ||
a2fbb9ea | 6915 | BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, |
34f80b04 | 6916 | sizeof(struct bnx2x_slowpath)); |
a2fbb9ea | 6917 | |
523224a3 DK |
6918 | BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, |
6919 | bp->context.size); | |
6920 | ||
6921 | bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); | |
6922 | ||
6923 | BNX2X_FREE(bp->ilt->lines); | |
f85582f8 | 6924 | |
37b091ba | 6925 | #ifdef BCM_CNIC |
619c5cb6 | 6926 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6927 | BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, |
6928 | sizeof(struct host_hc_status_block_e2)); | |
6929 | else | |
6930 | BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, | |
6931 | sizeof(struct host_hc_status_block_e1x)); | |
f85582f8 | 6932 | |
523224a3 | 6933 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); |
a2fbb9ea | 6934 | #endif |
f85582f8 | 6935 | |
7a9b2557 | 6936 | BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); |
a2fbb9ea | 6937 | |
523224a3 DK |
6938 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
6939 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
619c5cb6 VZ |
6940 | } |
6941 | ||
6942 | static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) | |
6943 | { | |
6944 | int num_groups; | |
50f0a562 | 6945 | int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1; |
619c5cb6 | 6946 | |
50f0a562 BW |
6947 | /* number of queues for statistics is number of eth queues + FCoE */ |
6948 | u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats; | |
619c5cb6 VZ |
6949 | |
6950 | /* Total number of FW statistics requests = | |
50f0a562 BW |
6951 | * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats + |
6952 | * num of queues | |
6953 | */ | |
6954 | bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats; | |
523224a3 | 6955 | |
619c5cb6 VZ |
6956 | |
6957 | /* Request is built from stats_query_header and an array of | |
6958 | * stats_query_cmd_group each of which contains | |
6959 | * STATS_QUERY_CMD_COUNT rules. The real number or requests is | |
6960 | * configured in the stats_query_header. | |
6961 | */ | |
50f0a562 BW |
6962 | num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) + |
6963 | (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0); | |
619c5cb6 VZ |
6964 | |
6965 | bp->fw_stats_req_sz = sizeof(struct stats_query_header) + | |
6966 | num_groups * sizeof(struct stats_query_cmd_group); | |
6967 | ||
6968 | /* Data for statistics requests + stats_conter | |
6969 | * | |
6970 | * stats_counter holds per-STORM counters that are incremented | |
6971 | * when STORM has finished with the current request. | |
50f0a562 BW |
6972 | * |
6973 | * memory for FCoE offloaded statistics are counted anyway, | |
6974 | * even if they will not be sent. | |
619c5cb6 VZ |
6975 | */ |
6976 | bp->fw_stats_data_sz = sizeof(struct per_port_stats) + | |
6977 | sizeof(struct per_pf_stats) + | |
50f0a562 | 6978 | sizeof(struct fcoe_statistics_params) + |
619c5cb6 VZ |
6979 | sizeof(struct per_queue_stats) * num_queue_stats + |
6980 | sizeof(struct stats_counter); | |
6981 | ||
6982 | BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, | |
6983 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
6984 | ||
6985 | /* Set shortcuts */ | |
6986 | bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; | |
6987 | bp->fw_stats_req_mapping = bp->fw_stats_mapping; | |
6988 | ||
6989 | bp->fw_stats_data = (struct bnx2x_fw_stats_data *) | |
6990 | ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); | |
6991 | ||
6992 | bp->fw_stats_data_mapping = bp->fw_stats_mapping + | |
6993 | bp->fw_stats_req_sz; | |
6994 | return 0; | |
6995 | ||
6996 | alloc_mem_err: | |
6997 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, | |
6998 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
51c1a580 | 6999 | BNX2X_ERR("Can't allocate memory\n"); |
619c5cb6 | 7000 | return -ENOMEM; |
a2fbb9ea ET |
7001 | } |
7002 | ||
f2e0899f | 7003 | |
9f6c9258 | 7004 | int bnx2x_alloc_mem(struct bnx2x *bp) |
a2fbb9ea | 7005 | { |
523224a3 | 7006 | #ifdef BCM_CNIC |
619c5cb6 VZ |
7007 | if (!CHIP_IS_E1x(bp)) |
7008 | /* size = the status block + ramrod buffers */ | |
f2e0899f DK |
7009 | BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, |
7010 | sizeof(struct host_hc_status_block_e2)); | |
7011 | else | |
7012 | BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, | |
7013 | sizeof(struct host_hc_status_block_e1x)); | |
8badd27a | 7014 | |
523224a3 DK |
7015 | /* allocate searcher T2 table */ |
7016 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); | |
7017 | #endif | |
a2fbb9ea | 7018 | |
8badd27a | 7019 | |
523224a3 DK |
7020 | BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, |
7021 | sizeof(struct host_sp_status_block)); | |
a2fbb9ea | 7022 | |
523224a3 DK |
7023 | BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, |
7024 | sizeof(struct bnx2x_slowpath)); | |
a2fbb9ea | 7025 | |
82fa848c MY |
7026 | #ifdef BCM_CNIC |
7027 | /* write address to which L5 should insert its values */ | |
7028 | bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp; | |
7029 | #endif | |
7030 | ||
619c5cb6 VZ |
7031 | /* Allocated memory for FW statistics */ |
7032 | if (bnx2x_alloc_fw_stats_mem(bp)) | |
7033 | goto alloc_mem_err; | |
7034 | ||
6383c0b3 | 7035 | bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); |
f85582f8 | 7036 | |
523224a3 DK |
7037 | BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, |
7038 | bp->context.size); | |
65abd74d | 7039 | |
523224a3 | 7040 | BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); |
65abd74d | 7041 | |
523224a3 DK |
7042 | if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) |
7043 | goto alloc_mem_err; | |
65abd74d | 7044 | |
9f6c9258 DK |
7045 | /* Slow path ring */ |
7046 | BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); | |
65abd74d | 7047 | |
523224a3 DK |
7048 | /* EQ */ |
7049 | BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, | |
7050 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
ab532cf3 | 7051 | |
b3b83c3f DK |
7052 | |
7053 | /* fastpath */ | |
7054 | /* need to be done at the end, since it's self adjusting to amount | |
7055 | * of memory available for RSS queues | |
7056 | */ | |
7057 | if (bnx2x_alloc_fp_mem(bp)) | |
7058 | goto alloc_mem_err; | |
9f6c9258 | 7059 | return 0; |
e1510706 | 7060 | |
9f6c9258 DK |
7061 | alloc_mem_err: |
7062 | bnx2x_free_mem(bp); | |
51c1a580 | 7063 | BNX2X_ERR("Can't allocate memory\n"); |
9f6c9258 | 7064 | return -ENOMEM; |
65abd74d YG |
7065 | } |
7066 | ||
a2fbb9ea ET |
7067 | /* |
7068 | * Init service functions | |
7069 | */ | |
a2fbb9ea | 7070 | |
619c5cb6 VZ |
7071 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, |
7072 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
7073 | int mac_type, unsigned long *ramrod_flags) | |
a2fbb9ea | 7074 | { |
619c5cb6 VZ |
7075 | int rc; |
7076 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
a2fbb9ea | 7077 | |
619c5cb6 | 7078 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
a2fbb9ea | 7079 | |
619c5cb6 VZ |
7080 | /* Fill general parameters */ |
7081 | ramrod_param.vlan_mac_obj = obj; | |
7082 | ramrod_param.ramrod_flags = *ramrod_flags; | |
a2fbb9ea | 7083 | |
619c5cb6 VZ |
7084 | /* Fill a user request section if needed */ |
7085 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
7086 | memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); | |
a2fbb9ea | 7087 | |
619c5cb6 | 7088 | __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); |
e3553b29 | 7089 | |
619c5cb6 VZ |
7090 | /* Set the command: ADD or DEL */ |
7091 | if (set) | |
7092 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
7093 | else | |
7094 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
a2fbb9ea ET |
7095 | } |
7096 | ||
619c5cb6 VZ |
7097 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
7098 | if (rc < 0) | |
7099 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); | |
7100 | return rc; | |
a2fbb9ea ET |
7101 | } |
7102 | ||
619c5cb6 VZ |
7103 | int bnx2x_del_all_macs(struct bnx2x *bp, |
7104 | struct bnx2x_vlan_mac_obj *mac_obj, | |
7105 | int mac_type, bool wait_for_comp) | |
e665bfda | 7106 | { |
619c5cb6 VZ |
7107 | int rc; |
7108 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | |
0793f83f | 7109 | |
619c5cb6 VZ |
7110 | /* Wait for completion of requested */ |
7111 | if (wait_for_comp) | |
7112 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
0793f83f | 7113 | |
619c5cb6 VZ |
7114 | /* Set the mac type of addresses we want to clear */ |
7115 | __set_bit(mac_type, &vlan_mac_flags); | |
0793f83f | 7116 | |
619c5cb6 VZ |
7117 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); |
7118 | if (rc < 0) | |
7119 | BNX2X_ERR("Failed to delete MACs: %d\n", rc); | |
0793f83f | 7120 | |
619c5cb6 | 7121 | return rc; |
0793f83f DK |
7122 | } |
7123 | ||
619c5cb6 | 7124 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
523224a3 | 7125 | { |
619c5cb6 | 7126 | unsigned long ramrod_flags = 0; |
e665bfda | 7127 | |
614c76df | 7128 | #ifdef BCM_CNIC |
9e62e912 | 7129 | if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_STORAGE_SD(bp)) { |
51c1a580 MS |
7130 | DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN, |
7131 | "Ignoring Zero MAC for STORAGE SD mode\n"); | |
614c76df DK |
7132 | return 0; |
7133 | } | |
7134 | #endif | |
7135 | ||
619c5cb6 | 7136 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
0793f83f | 7137 | |
619c5cb6 VZ |
7138 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); |
7139 | /* Eth MAC is set on RSS leading client (fp[0]) */ | |
7140 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, | |
7141 | BNX2X_ETH_MAC, &ramrod_flags); | |
e665bfda | 7142 | } |
6e30dd4e | 7143 | |
619c5cb6 | 7144 | int bnx2x_setup_leading(struct bnx2x *bp) |
ec6ba945 | 7145 | { |
619c5cb6 | 7146 | return bnx2x_setup_queue(bp, &bp->fp[0], 1); |
993ac7b5 | 7147 | } |
a2fbb9ea | 7148 | |
d6214d7a | 7149 | /** |
e8920674 | 7150 | * bnx2x_set_int_mode - configure interrupt mode |
d6214d7a | 7151 | * |
e8920674 | 7152 | * @bp: driver handle |
d6214d7a | 7153 | * |
e8920674 | 7154 | * In case of MSI-X it will also try to enable MSI-X. |
d6214d7a | 7155 | */ |
9ee3d37b | 7156 | static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) |
ca00392c | 7157 | { |
9ee3d37b | 7158 | switch (int_mode) { |
d6214d7a DK |
7159 | case INT_MODE_MSI: |
7160 | bnx2x_enable_msi(bp); | |
7161 | /* falling through... */ | |
7162 | case INT_MODE_INTx: | |
6383c0b3 | 7163 | bp->num_queues = 1 + NON_ETH_CONTEXT_USE; |
51c1a580 | 7164 | BNX2X_DEV_INFO("set number of queues to 1\n"); |
ca00392c | 7165 | break; |
d6214d7a | 7166 | default: |
30a5de77 | 7167 | /* Set number of queues for MSI-X mode */ |
d6214d7a | 7168 | bnx2x_set_num_queues(bp); |
ca00392c | 7169 | |
51c1a580 | 7170 | BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); |
ca00392c | 7171 | |
d6214d7a DK |
7172 | /* if we can't use MSI-X we only need one fp, |
7173 | * so try to enable MSI-X with the requested number of fp's | |
7174 | * and fallback to MSI or legacy INTx with one fp | |
7175 | */ | |
30a5de77 DK |
7176 | if (bnx2x_enable_msix(bp) || |
7177 | bp->flags & USING_SINGLE_MSIX_FLAG) { | |
7178 | /* failed to enable multiple MSI-X */ | |
7179 | BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", | |
51c1a580 MS |
7180 | bp->num_queues, 1 + NON_ETH_CONTEXT_USE); |
7181 | ||
6383c0b3 | 7182 | bp->num_queues = 1 + NON_ETH_CONTEXT_USE; |
d6214d7a | 7183 | |
9ee3d37b | 7184 | /* Try to enable MSI */ |
30a5de77 DK |
7185 | if (!(bp->flags & USING_SINGLE_MSIX_FLAG) && |
7186 | !(bp->flags & DISABLE_MSI_FLAG)) | |
d6214d7a DK |
7187 | bnx2x_enable_msi(bp); |
7188 | } | |
9f6c9258 DK |
7189 | break; |
7190 | } | |
a2fbb9ea ET |
7191 | } |
7192 | ||
c2bff63f DK |
7193 | /* must be called prioir to any HW initializations */ |
7194 | static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) | |
7195 | { | |
7196 | return L2_ILT_LINES(bp); | |
7197 | } | |
7198 | ||
523224a3 DK |
7199 | void bnx2x_ilt_set_info(struct bnx2x *bp) |
7200 | { | |
7201 | struct ilt_client_info *ilt_client; | |
7202 | struct bnx2x_ilt *ilt = BP_ILT(bp); | |
7203 | u16 line = 0; | |
7204 | ||
7205 | ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); | |
7206 | DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); | |
7207 | ||
7208 | /* CDU */ | |
7209 | ilt_client = &ilt->clients[ILT_CLIENT_CDU]; | |
7210 | ilt_client->client_num = ILT_CLIENT_CDU; | |
7211 | ilt_client->page_size = CDU_ILT_PAGE_SZ; | |
7212 | ilt_client->flags = ILT_CLIENT_SKIP_MEM; | |
7213 | ilt_client->start = line; | |
619c5cb6 | 7214 | line += bnx2x_cid_ilt_lines(bp); |
523224a3 DK |
7215 | #ifdef BCM_CNIC |
7216 | line += CNIC_ILT_LINES; | |
7217 | #endif | |
7218 | ilt_client->end = line - 1; | |
7219 | ||
51c1a580 | 7220 | DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", |
523224a3 DK |
7221 | ilt_client->start, |
7222 | ilt_client->end, | |
7223 | ilt_client->page_size, | |
7224 | ilt_client->flags, | |
7225 | ilog2(ilt_client->page_size >> 12)); | |
7226 | ||
7227 | /* QM */ | |
7228 | if (QM_INIT(bp->qm_cid_count)) { | |
7229 | ilt_client = &ilt->clients[ILT_CLIENT_QM]; | |
7230 | ilt_client->client_num = ILT_CLIENT_QM; | |
7231 | ilt_client->page_size = QM_ILT_PAGE_SZ; | |
7232 | ilt_client->flags = 0; | |
7233 | ilt_client->start = line; | |
7234 | ||
7235 | /* 4 bytes for each cid */ | |
7236 | line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, | |
7237 | QM_ILT_PAGE_SZ); | |
7238 | ||
7239 | ilt_client->end = line - 1; | |
7240 | ||
51c1a580 MS |
7241 | DP(NETIF_MSG_IFUP, |
7242 | "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
7243 | ilt_client->start, |
7244 | ilt_client->end, | |
7245 | ilt_client->page_size, | |
7246 | ilt_client->flags, | |
7247 | ilog2(ilt_client->page_size >> 12)); | |
7248 | ||
7249 | } | |
7250 | /* SRC */ | |
7251 | ilt_client = &ilt->clients[ILT_CLIENT_SRC]; | |
7252 | #ifdef BCM_CNIC | |
7253 | ilt_client->client_num = ILT_CLIENT_SRC; | |
7254 | ilt_client->page_size = SRC_ILT_PAGE_SZ; | |
7255 | ilt_client->flags = 0; | |
7256 | ilt_client->start = line; | |
7257 | line += SRC_ILT_LINES; | |
7258 | ilt_client->end = line - 1; | |
7259 | ||
51c1a580 MS |
7260 | DP(NETIF_MSG_IFUP, |
7261 | "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
7262 | ilt_client->start, |
7263 | ilt_client->end, | |
7264 | ilt_client->page_size, | |
7265 | ilt_client->flags, | |
7266 | ilog2(ilt_client->page_size >> 12)); | |
7267 | ||
7268 | #else | |
7269 | ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); | |
7270 | #endif | |
9f6c9258 | 7271 | |
523224a3 DK |
7272 | /* TM */ |
7273 | ilt_client = &ilt->clients[ILT_CLIENT_TM]; | |
7274 | #ifdef BCM_CNIC | |
7275 | ilt_client->client_num = ILT_CLIENT_TM; | |
7276 | ilt_client->page_size = TM_ILT_PAGE_SZ; | |
7277 | ilt_client->flags = 0; | |
7278 | ilt_client->start = line; | |
7279 | line += TM_ILT_LINES; | |
7280 | ilt_client->end = line - 1; | |
7281 | ||
51c1a580 MS |
7282 | DP(NETIF_MSG_IFUP, |
7283 | "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
7284 | ilt_client->start, |
7285 | ilt_client->end, | |
7286 | ilt_client->page_size, | |
7287 | ilt_client->flags, | |
7288 | ilog2(ilt_client->page_size >> 12)); | |
9f6c9258 | 7289 | |
523224a3 DK |
7290 | #else |
7291 | ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); | |
7292 | #endif | |
619c5cb6 | 7293 | BUG_ON(line > ILT_MAX_LINES); |
523224a3 | 7294 | } |
f85582f8 | 7295 | |
619c5cb6 VZ |
7296 | /** |
7297 | * bnx2x_pf_q_prep_init - prepare INIT transition parameters | |
7298 | * | |
7299 | * @bp: driver handle | |
7300 | * @fp: pointer to fastpath | |
7301 | * @init_params: pointer to parameters structure | |
7302 | * | |
7303 | * parameters configured: | |
7304 | * - HC configuration | |
7305 | * - Queue's CDU context | |
7306 | */ | |
7307 | static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, | |
7308 | struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) | |
a2fbb9ea | 7309 | { |
6383c0b3 AE |
7310 | |
7311 | u8 cos; | |
619c5cb6 VZ |
7312 | /* FCoE Queue uses Default SB, thus has no HC capabilities */ |
7313 | if (!IS_FCOE_FP(fp)) { | |
7314 | __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); | |
7315 | __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); | |
7316 | ||
7317 | /* If HC is supporterd, enable host coalescing in the transition | |
7318 | * to INIT state. | |
7319 | */ | |
7320 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); | |
7321 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); | |
7322 | ||
7323 | /* HC rate */ | |
7324 | init_params->rx.hc_rate = bp->rx_ticks ? | |
7325 | (1000000 / bp->rx_ticks) : 0; | |
7326 | init_params->tx.hc_rate = bp->tx_ticks ? | |
7327 | (1000000 / bp->tx_ticks) : 0; | |
7328 | ||
7329 | /* FW SB ID */ | |
7330 | init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = | |
7331 | fp->fw_sb_id; | |
7332 | ||
7333 | /* | |
7334 | * CQ index among the SB indices: FCoE clients uses the default | |
7335 | * SB, therefore it's different. | |
7336 | */ | |
6383c0b3 AE |
7337 | init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
7338 | init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; | |
619c5cb6 VZ |
7339 | } |
7340 | ||
6383c0b3 AE |
7341 | /* set maximum number of COSs supported by this queue */ |
7342 | init_params->max_cos = fp->max_cos; | |
7343 | ||
51c1a580 | 7344 | DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", |
6383c0b3 AE |
7345 | fp->index, init_params->max_cos); |
7346 | ||
7347 | /* set the context pointers queue object */ | |
7348 | for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) | |
7349 | init_params->cxts[cos] = | |
7350 | &bp->context.vcxt[fp->txdata[cos].cid].eth; | |
619c5cb6 VZ |
7351 | } |
7352 | ||
6383c0b3 AE |
7353 | int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
7354 | struct bnx2x_queue_state_params *q_params, | |
7355 | struct bnx2x_queue_setup_tx_only_params *tx_only_params, | |
7356 | int tx_index, bool leading) | |
7357 | { | |
7358 | memset(tx_only_params, 0, sizeof(*tx_only_params)); | |
7359 | ||
7360 | /* Set the command */ | |
7361 | q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
7362 | ||
7363 | /* Set tx-only QUEUE flags: don't zero statistics */ | |
7364 | tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); | |
7365 | ||
7366 | /* choose the index of the cid to send the slow path on */ | |
7367 | tx_only_params->cid_index = tx_index; | |
7368 | ||
7369 | /* Set general TX_ONLY_SETUP parameters */ | |
7370 | bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); | |
7371 | ||
7372 | /* Set Tx TX_ONLY_SETUP parameters */ | |
7373 | bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); | |
7374 | ||
51c1a580 MS |
7375 | DP(NETIF_MSG_IFUP, |
7376 | "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", | |
6383c0b3 AE |
7377 | tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], |
7378 | q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, | |
7379 | tx_only_params->gen_params.spcl_id, tx_only_params->flags); | |
7380 | ||
7381 | /* send the ramrod */ | |
7382 | return bnx2x_queue_state_change(bp, q_params); | |
7383 | } | |
7384 | ||
7385 | ||
619c5cb6 VZ |
7386 | /** |
7387 | * bnx2x_setup_queue - setup queue | |
7388 | * | |
7389 | * @bp: driver handle | |
7390 | * @fp: pointer to fastpath | |
7391 | * @leading: is leading | |
7392 | * | |
7393 | * This function performs 2 steps in a Queue state machine | |
7394 | * actually: 1) RESET->INIT 2) INIT->SETUP | |
7395 | */ | |
7396 | ||
7397 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
7398 | bool leading) | |
7399 | { | |
3b603066 | 7400 | struct bnx2x_queue_state_params q_params = {NULL}; |
619c5cb6 VZ |
7401 | struct bnx2x_queue_setup_params *setup_params = |
7402 | &q_params.params.setup; | |
6383c0b3 AE |
7403 | struct bnx2x_queue_setup_tx_only_params *tx_only_params = |
7404 | &q_params.params.tx_only; | |
a2fbb9ea | 7405 | int rc; |
6383c0b3 AE |
7406 | u8 tx_index; |
7407 | ||
51c1a580 | 7408 | DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); |
a2fbb9ea | 7409 | |
ec6ba945 VZ |
7410 | /* reset IGU state skip FCoE L2 queue */ |
7411 | if (!IS_FCOE_FP(fp)) | |
7412 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, | |
523224a3 | 7413 | IGU_INT_ENABLE, 0); |
a2fbb9ea | 7414 | |
619c5cb6 VZ |
7415 | q_params.q_obj = &fp->q_obj; |
7416 | /* We want to wait for completion in this context */ | |
7417 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 7418 | |
619c5cb6 VZ |
7419 | /* Prepare the INIT parameters */ |
7420 | bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); | |
ec6ba945 | 7421 | |
619c5cb6 VZ |
7422 | /* Set the command */ |
7423 | q_params.cmd = BNX2X_Q_CMD_INIT; | |
7424 | ||
7425 | /* Change the state to INIT */ | |
7426 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7427 | if (rc) { | |
6383c0b3 | 7428 | BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); |
619c5cb6 VZ |
7429 | return rc; |
7430 | } | |
ec6ba945 | 7431 | |
51c1a580 | 7432 | DP(NETIF_MSG_IFUP, "init complete\n"); |
6383c0b3 AE |
7433 | |
7434 | ||
619c5cb6 VZ |
7435 | /* Now move the Queue to the SETUP state... */ |
7436 | memset(setup_params, 0, sizeof(*setup_params)); | |
a2fbb9ea | 7437 | |
619c5cb6 VZ |
7438 | /* Set QUEUE flags */ |
7439 | setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); | |
523224a3 | 7440 | |
619c5cb6 | 7441 | /* Set general SETUP parameters */ |
6383c0b3 AE |
7442 | bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, |
7443 | FIRST_TX_COS_INDEX); | |
619c5cb6 | 7444 | |
6383c0b3 | 7445 | bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, |
619c5cb6 VZ |
7446 | &setup_params->rxq_params); |
7447 | ||
6383c0b3 AE |
7448 | bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, |
7449 | FIRST_TX_COS_INDEX); | |
619c5cb6 VZ |
7450 | |
7451 | /* Set the command */ | |
7452 | q_params.cmd = BNX2X_Q_CMD_SETUP; | |
7453 | ||
7454 | /* Change the state to SETUP */ | |
7455 | rc = bnx2x_queue_state_change(bp, &q_params); | |
6383c0b3 AE |
7456 | if (rc) { |
7457 | BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); | |
7458 | return rc; | |
7459 | } | |
7460 | ||
7461 | /* loop through the relevant tx-only indices */ | |
7462 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
7463 | tx_index < fp->max_cos; | |
7464 | tx_index++) { | |
7465 | ||
7466 | /* prepare and send tx-only ramrod*/ | |
7467 | rc = bnx2x_setup_tx_only(bp, fp, &q_params, | |
7468 | tx_only_params, tx_index, leading); | |
7469 | if (rc) { | |
7470 | BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", | |
7471 | fp->index, tx_index); | |
7472 | return rc; | |
7473 | } | |
7474 | } | |
523224a3 | 7475 | |
34f80b04 | 7476 | return rc; |
a2fbb9ea ET |
7477 | } |
7478 | ||
619c5cb6 | 7479 | static int bnx2x_stop_queue(struct bnx2x *bp, int index) |
a2fbb9ea | 7480 | { |
619c5cb6 | 7481 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
6383c0b3 | 7482 | struct bnx2x_fp_txdata *txdata; |
3b603066 | 7483 | struct bnx2x_queue_state_params q_params = {NULL}; |
6383c0b3 AE |
7484 | int rc, tx_index; |
7485 | ||
51c1a580 | 7486 | DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); |
a2fbb9ea | 7487 | |
619c5cb6 VZ |
7488 | q_params.q_obj = &fp->q_obj; |
7489 | /* We want to wait for completion in this context */ | |
7490 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 7491 | |
6383c0b3 AE |
7492 | |
7493 | /* close tx-only connections */ | |
7494 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
7495 | tx_index < fp->max_cos; | |
7496 | tx_index++){ | |
7497 | ||
7498 | /* ascertain this is a normal queue*/ | |
7499 | txdata = &fp->txdata[tx_index]; | |
7500 | ||
51c1a580 | 7501 | DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", |
6383c0b3 AE |
7502 | txdata->txq_index); |
7503 | ||
7504 | /* send halt terminate on tx-only connection */ | |
7505 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; | |
7506 | memset(&q_params.params.terminate, 0, | |
7507 | sizeof(q_params.params.terminate)); | |
7508 | q_params.params.terminate.cid_index = tx_index; | |
7509 | ||
7510 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7511 | if (rc) | |
7512 | return rc; | |
7513 | ||
7514 | /* send halt terminate on tx-only connection */ | |
7515 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; | |
7516 | memset(&q_params.params.cfc_del, 0, | |
7517 | sizeof(q_params.params.cfc_del)); | |
7518 | q_params.params.cfc_del.cid_index = tx_index; | |
7519 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7520 | if (rc) | |
7521 | return rc; | |
7522 | } | |
7523 | /* Stop the primary connection: */ | |
7524 | /* ...halt the connection */ | |
619c5cb6 VZ |
7525 | q_params.cmd = BNX2X_Q_CMD_HALT; |
7526 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7527 | if (rc) | |
da5a662a | 7528 | return rc; |
a2fbb9ea | 7529 | |
6383c0b3 | 7530 | /* ...terminate the connection */ |
619c5cb6 | 7531 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
6383c0b3 AE |
7532 | memset(&q_params.params.terminate, 0, |
7533 | sizeof(q_params.params.terminate)); | |
7534 | q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 VZ |
7535 | rc = bnx2x_queue_state_change(bp, &q_params); |
7536 | if (rc) | |
523224a3 | 7537 | return rc; |
6383c0b3 | 7538 | /* ...delete cfc entry */ |
619c5cb6 | 7539 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
6383c0b3 AE |
7540 | memset(&q_params.params.cfc_del, 0, |
7541 | sizeof(q_params.params.cfc_del)); | |
7542 | q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 | 7543 | return bnx2x_queue_state_change(bp, &q_params); |
523224a3 DK |
7544 | } |
7545 | ||
7546 | ||
34f80b04 EG |
7547 | static void bnx2x_reset_func(struct bnx2x *bp) |
7548 | { | |
7549 | int port = BP_PORT(bp); | |
7550 | int func = BP_FUNC(bp); | |
f2e0899f | 7551 | int i; |
523224a3 DK |
7552 | |
7553 | /* Disable the function in the FW */ | |
7554 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); | |
7555 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); | |
7556 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); | |
7557 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); | |
7558 | ||
7559 | /* FP SBs */ | |
ec6ba945 | 7560 | for_each_eth_queue(bp, i) { |
523224a3 | 7561 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
619c5cb6 | 7562 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
7563 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), |
7564 | SB_DISABLED); | |
523224a3 DK |
7565 | } |
7566 | ||
619c5cb6 VZ |
7567 | #ifdef BCM_CNIC |
7568 | /* CNIC SB */ | |
7569 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
7570 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), | |
7571 | SB_DISABLED); | |
7572 | #endif | |
523224a3 | 7573 | /* SP SB */ |
619c5cb6 | 7574 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
7575 | CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), |
7576 | SB_DISABLED); | |
523224a3 DK |
7577 | |
7578 | for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) | |
7579 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), | |
7580 | 0); | |
34f80b04 EG |
7581 | |
7582 | /* Configure IGU */ | |
f2e0899f DK |
7583 | if (bp->common.int_block == INT_BLOCK_HC) { |
7584 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7585 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7586 | } else { | |
7587 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); | |
7588 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
7589 | } | |
34f80b04 | 7590 | |
37b091ba MC |
7591 | #ifdef BCM_CNIC |
7592 | /* Disable Timer scan */ | |
7593 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); | |
7594 | /* | |
7595 | * Wait for at least 10ms and up to 2 second for the timers scan to | |
7596 | * complete | |
7597 | */ | |
7598 | for (i = 0; i < 200; i++) { | |
7599 | msleep(10); | |
7600 | if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) | |
7601 | break; | |
7602 | } | |
7603 | #endif | |
34f80b04 | 7604 | /* Clear ILT */ |
f2e0899f DK |
7605 | bnx2x_clear_func_ilt(bp, func); |
7606 | ||
7607 | /* Timers workaround bug for E2: if this is vnic-3, | |
7608 | * we need to set the entire ilt range for this timers. | |
7609 | */ | |
619c5cb6 | 7610 | if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { |
f2e0899f DK |
7611 | struct ilt_client_info ilt_cli; |
7612 | /* use dummy TM client */ | |
7613 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
7614 | ilt_cli.start = 0; | |
7615 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
7616 | ilt_cli.client_num = ILT_CLIENT_TM; | |
7617 | ||
7618 | bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); | |
7619 | } | |
7620 | ||
7621 | /* this assumes that reset_port() called before reset_func()*/ | |
619c5cb6 | 7622 | if (!CHIP_IS_E1x(bp)) |
f2e0899f | 7623 | bnx2x_pf_disable(bp); |
523224a3 DK |
7624 | |
7625 | bp->dmae_ready = 0; | |
34f80b04 EG |
7626 | } |
7627 | ||
7628 | static void bnx2x_reset_port(struct bnx2x *bp) | |
7629 | { | |
7630 | int port = BP_PORT(bp); | |
7631 | u32 val; | |
7632 | ||
619c5cb6 VZ |
7633 | /* Reset physical Link */ |
7634 | bnx2x__link_reset(bp); | |
7635 | ||
34f80b04 EG |
7636 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
7637 | ||
7638 | /* Do not rcv packets to BRB */ | |
7639 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); | |
7640 | /* Do not direct rcv packets that are not for MCP to the BRB */ | |
7641 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
7642 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
7643 | ||
7644 | /* Configure AEU */ | |
7645 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); | |
7646 | ||
7647 | msleep(100); | |
7648 | /* Check for BRB port occupancy */ | |
7649 | val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); | |
7650 | if (val) | |
7651 | DP(NETIF_MSG_IFDOWN, | |
33471629 | 7652 | "BRB1 is not empty %d blocks are occupied\n", val); |
34f80b04 EG |
7653 | |
7654 | /* TODO: Close Doorbell port? */ | |
7655 | } | |
7656 | ||
619c5cb6 | 7657 | static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) |
34f80b04 | 7658 | { |
3b603066 | 7659 | struct bnx2x_func_state_params func_params = {NULL}; |
34f80b04 | 7660 | |
619c5cb6 VZ |
7661 | /* Prepare parameters for function state transitions */ |
7662 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
34f80b04 | 7663 | |
619c5cb6 VZ |
7664 | func_params.f_obj = &bp->func_obj; |
7665 | func_params.cmd = BNX2X_F_CMD_HW_RESET; | |
34f80b04 | 7666 | |
619c5cb6 | 7667 | func_params.params.hw_init.load_phase = load_code; |
49d66772 | 7668 | |
619c5cb6 | 7669 | return bnx2x_func_state_change(bp, &func_params); |
34f80b04 EG |
7670 | } |
7671 | ||
619c5cb6 | 7672 | static inline int bnx2x_func_stop(struct bnx2x *bp) |
ec6ba945 | 7673 | { |
3b603066 | 7674 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 | 7675 | int rc; |
228241eb | 7676 | |
619c5cb6 VZ |
7677 | /* Prepare parameters for function state transitions */ |
7678 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
7679 | func_params.f_obj = &bp->func_obj; | |
7680 | func_params.cmd = BNX2X_F_CMD_STOP; | |
da5a662a | 7681 | |
619c5cb6 VZ |
7682 | /* |
7683 | * Try to stop the function the 'good way'. If fails (in case | |
7684 | * of a parity error during bnx2x_chip_cleanup()) and we are | |
7685 | * not in a debug mode, perform a state transaction in order to | |
7686 | * enable further HW_RESET transaction. | |
7687 | */ | |
7688 | rc = bnx2x_func_state_change(bp, &func_params); | |
7689 | if (rc) { | |
34f80b04 | 7690 | #ifdef BNX2X_STOP_ON_ERROR |
619c5cb6 | 7691 | return rc; |
34f80b04 | 7692 | #else |
51c1a580 | 7693 | BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); |
619c5cb6 VZ |
7694 | __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); |
7695 | return bnx2x_func_state_change(bp, &func_params); | |
34f80b04 | 7696 | #endif |
228241eb | 7697 | } |
a2fbb9ea | 7698 | |
619c5cb6 VZ |
7699 | return 0; |
7700 | } | |
523224a3 | 7701 | |
619c5cb6 VZ |
7702 | /** |
7703 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
7704 | * | |
7705 | * @bp: driver handle | |
7706 | * @unload_mode: requested function's unload mode | |
7707 | * | |
7708 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
7709 | */ | |
7710 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) | |
7711 | { | |
7712 | u32 reset_code = 0; | |
7713 | int port = BP_PORT(bp); | |
3101c2bc | 7714 | |
619c5cb6 | 7715 | /* Select the UNLOAD request mode */ |
65abd74d YG |
7716 | if (unload_mode == UNLOAD_NORMAL) |
7717 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
7718 | ||
7d0446c2 | 7719 | else if (bp->flags & NO_WOL_FLAG) |
65abd74d | 7720 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
65abd74d | 7721 | |
7d0446c2 | 7722 | else if (bp->wol) { |
65abd74d YG |
7723 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
7724 | u8 *mac_addr = bp->dev->dev_addr; | |
7725 | u32 val; | |
f9977903 DK |
7726 | u16 pmc; |
7727 | ||
65abd74d | 7728 | /* The mac address is written to entries 1-4 to |
f9977903 DK |
7729 | * preserve entry 0 which is used by the PMF |
7730 | */ | |
3395a033 | 7731 | u8 entry = (BP_VN(bp) + 1)*8; |
65abd74d YG |
7732 | |
7733 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
7734 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); | |
7735 | ||
7736 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | |
7737 | (mac_addr[4] << 8) | mac_addr[5]; | |
7738 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); | |
7739 | ||
f9977903 DK |
7740 | /* Enable the PME and clear the status */ |
7741 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); | |
7742 | pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; | |
7743 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); | |
7744 | ||
65abd74d YG |
7745 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; |
7746 | ||
7747 | } else | |
7748 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
da5a662a | 7749 | |
619c5cb6 VZ |
7750 | /* Send the request to the MCP */ |
7751 | if (!BP_NOMCP(bp)) | |
7752 | reset_code = bnx2x_fw_command(bp, reset_code, 0); | |
7753 | else { | |
7754 | int path = BP_PATH(bp); | |
7755 | ||
51c1a580 | 7756 | DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", |
619c5cb6 VZ |
7757 | path, load_count[path][0], load_count[path][1], |
7758 | load_count[path][2]); | |
7759 | load_count[path][0]--; | |
7760 | load_count[path][1 + port]--; | |
51c1a580 | 7761 | DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", |
619c5cb6 VZ |
7762 | path, load_count[path][0], load_count[path][1], |
7763 | load_count[path][2]); | |
7764 | if (load_count[path][0] == 0) | |
7765 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; | |
7766 | else if (load_count[path][1 + port] == 0) | |
7767 | reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; | |
7768 | else | |
7769 | reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; | |
7770 | } | |
7771 | ||
7772 | return reset_code; | |
7773 | } | |
7774 | ||
7775 | /** | |
7776 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
7777 | * | |
7778 | * @bp: driver handle | |
7779 | */ | |
7780 | void bnx2x_send_unload_done(struct bnx2x *bp) | |
7781 | { | |
7782 | /* Report UNLOAD_DONE to MCP */ | |
7783 | if (!BP_NOMCP(bp)) | |
7784 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
7785 | } | |
7786 | ||
6debea87 DK |
7787 | static inline int bnx2x_func_wait_started(struct bnx2x *bp) |
7788 | { | |
7789 | int tout = 50; | |
7790 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
7791 | ||
7792 | if (!bp->port.pmf) | |
7793 | return 0; | |
7794 | ||
7795 | /* | |
7796 | * (assumption: No Attention from MCP at this stage) | |
7797 | * PMF probably in the middle of TXdisable/enable transaction | |
7798 | * 1. Sync IRS for default SB | |
7799 | * 2. Sync SP queue - this guarantes us that attention handling started | |
7800 | * 3. Wait, that TXdisable/enable transaction completes | |
7801 | * | |
7802 | * 1+2 guranty that if DCBx attention was scheduled it already changed | |
7803 | * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy | |
7804 | * received complettion for the transaction the state is TX_STOPPED. | |
7805 | * State will return to STARTED after completion of TX_STOPPED-->STARTED | |
7806 | * transaction. | |
7807 | */ | |
7808 | ||
7809 | /* make sure default SB ISR is done */ | |
7810 | if (msix) | |
7811 | synchronize_irq(bp->msix_table[0].vector); | |
7812 | else | |
7813 | synchronize_irq(bp->pdev->irq); | |
7814 | ||
7815 | flush_workqueue(bnx2x_wq); | |
7816 | ||
7817 | while (bnx2x_func_get_state(bp, &bp->func_obj) != | |
7818 | BNX2X_F_STATE_STARTED && tout--) | |
7819 | msleep(20); | |
7820 | ||
7821 | if (bnx2x_func_get_state(bp, &bp->func_obj) != | |
7822 | BNX2X_F_STATE_STARTED) { | |
7823 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 7824 | BNX2X_ERR("Wrong function state\n"); |
6debea87 DK |
7825 | return -EBUSY; |
7826 | #else | |
7827 | /* | |
7828 | * Failed to complete the transaction in a "good way" | |
7829 | * Force both transactions with CLR bit | |
7830 | */ | |
3b603066 | 7831 | struct bnx2x_func_state_params func_params = {NULL}; |
6debea87 | 7832 | |
51c1a580 MS |
7833 | DP(NETIF_MSG_IFDOWN, |
7834 | "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n"); | |
6debea87 DK |
7835 | |
7836 | func_params.f_obj = &bp->func_obj; | |
7837 | __set_bit(RAMROD_DRV_CLR_ONLY, | |
7838 | &func_params.ramrod_flags); | |
7839 | ||
7840 | /* STARTED-->TX_ST0PPED */ | |
7841 | func_params.cmd = BNX2X_F_CMD_TX_STOP; | |
7842 | bnx2x_func_state_change(bp, &func_params); | |
7843 | ||
7844 | /* TX_ST0PPED-->STARTED */ | |
7845 | func_params.cmd = BNX2X_F_CMD_TX_START; | |
7846 | return bnx2x_func_state_change(bp, &func_params); | |
7847 | #endif | |
7848 | } | |
7849 | ||
7850 | return 0; | |
7851 | } | |
7852 | ||
619c5cb6 VZ |
7853 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) |
7854 | { | |
7855 | int port = BP_PORT(bp); | |
6383c0b3 AE |
7856 | int i, rc = 0; |
7857 | u8 cos; | |
3b603066 | 7858 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 VZ |
7859 | u32 reset_code; |
7860 | ||
7861 | /* Wait until tx fastpath tasks complete */ | |
7862 | for_each_tx_queue(bp, i) { | |
7863 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
7864 | ||
6383c0b3 AE |
7865 | for_each_cos_in_tx_queue(fp, cos) |
7866 | rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); | |
619c5cb6 VZ |
7867 | #ifdef BNX2X_STOP_ON_ERROR |
7868 | if (rc) | |
7869 | return; | |
7870 | #endif | |
7871 | } | |
7872 | ||
7873 | /* Give HW time to discard old tx messages */ | |
7874 | usleep_range(1000, 1000); | |
7875 | ||
7876 | /* Clean all ETH MACs */ | |
7877 | rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); | |
7878 | if (rc < 0) | |
7879 | BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); | |
7880 | ||
7881 | /* Clean up UC list */ | |
7882 | rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, | |
7883 | true); | |
7884 | if (rc < 0) | |
51c1a580 MS |
7885 | BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", |
7886 | rc); | |
619c5cb6 VZ |
7887 | |
7888 | /* Disable LLH */ | |
7889 | if (!CHIP_IS_E1(bp)) | |
7890 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
7891 | ||
7892 | /* Set "drop all" (stop Rx). | |
7893 | * We need to take a netif_addr_lock() here in order to prevent | |
7894 | * a race between the completion code and this code. | |
7895 | */ | |
7896 | netif_addr_lock_bh(bp->dev); | |
7897 | /* Schedule the rx_mode command */ | |
7898 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
7899 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
7900 | else | |
7901 | bnx2x_set_storm_rx_mode(bp); | |
7902 | ||
7903 | /* Cleanup multicast configuration */ | |
7904 | rparam.mcast_obj = &bp->mcast_obj; | |
7905 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
7906 | if (rc < 0) | |
7907 | BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); | |
7908 | ||
7909 | netif_addr_unlock_bh(bp->dev); | |
7910 | ||
7911 | ||
6debea87 DK |
7912 | |
7913 | /* | |
7914 | * Send the UNLOAD_REQUEST to the MCP. This will return if | |
7915 | * this function should perform FUNC, PORT or COMMON HW | |
7916 | * reset. | |
7917 | */ | |
7918 | reset_code = bnx2x_send_unload_req(bp, unload_mode); | |
7919 | ||
7920 | /* | |
7921 | * (assumption: No Attention from MCP at this stage) | |
7922 | * PMF probably in the middle of TXdisable/enable transaction | |
7923 | */ | |
7924 | rc = bnx2x_func_wait_started(bp); | |
7925 | if (rc) { | |
7926 | BNX2X_ERR("bnx2x_func_wait_started failed\n"); | |
7927 | #ifdef BNX2X_STOP_ON_ERROR | |
7928 | return; | |
7929 | #endif | |
7930 | } | |
7931 | ||
34f80b04 | 7932 | /* Close multi and leading connections |
619c5cb6 VZ |
7933 | * Completions for ramrods are collected in a synchronous way |
7934 | */ | |
523224a3 | 7935 | for_each_queue(bp, i) |
619c5cb6 | 7936 | if (bnx2x_stop_queue(bp, i)) |
523224a3 DK |
7937 | #ifdef BNX2X_STOP_ON_ERROR |
7938 | return; | |
7939 | #else | |
228241eb | 7940 | goto unload_error; |
523224a3 | 7941 | #endif |
619c5cb6 VZ |
7942 | /* If SP settings didn't get completed so far - something |
7943 | * very wrong has happen. | |
7944 | */ | |
7945 | if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) | |
7946 | BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); | |
a2fbb9ea | 7947 | |
619c5cb6 VZ |
7948 | #ifndef BNX2X_STOP_ON_ERROR |
7949 | unload_error: | |
7950 | #endif | |
523224a3 | 7951 | rc = bnx2x_func_stop(bp); |
da5a662a | 7952 | if (rc) { |
523224a3 | 7953 | BNX2X_ERR("Function stop failed!\n"); |
da5a662a | 7954 | #ifdef BNX2X_STOP_ON_ERROR |
523224a3 | 7955 | return; |
523224a3 | 7956 | #endif |
34f80b04 | 7957 | } |
a2fbb9ea | 7958 | |
523224a3 DK |
7959 | /* Disable HW interrupts, NAPI */ |
7960 | bnx2x_netif_stop(bp, 1); | |
7961 | ||
7962 | /* Release IRQs */ | |
d6214d7a | 7963 | bnx2x_free_irq(bp); |
523224a3 | 7964 | |
a2fbb9ea | 7965 | /* Reset the chip */ |
619c5cb6 VZ |
7966 | rc = bnx2x_reset_hw(bp, reset_code); |
7967 | if (rc) | |
7968 | BNX2X_ERR("HW_RESET failed\n"); | |
a2fbb9ea | 7969 | |
356e2385 | 7970 | |
619c5cb6 VZ |
7971 | /* Report UNLOAD_DONE to MCP */ |
7972 | bnx2x_send_unload_done(bp); | |
72fd0718 VZ |
7973 | } |
7974 | ||
9f6c9258 | 7975 | void bnx2x_disable_close_the_gate(struct bnx2x *bp) |
72fd0718 VZ |
7976 | { |
7977 | u32 val; | |
7978 | ||
51c1a580 | 7979 | DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); |
72fd0718 VZ |
7980 | |
7981 | if (CHIP_IS_E1(bp)) { | |
7982 | int port = BP_PORT(bp); | |
7983 | u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
7984 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
7985 | ||
7986 | val = REG_RD(bp, addr); | |
7987 | val &= ~(0x300); | |
7988 | REG_WR(bp, addr, val); | |
619c5cb6 | 7989 | } else { |
72fd0718 VZ |
7990 | val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); |
7991 | val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | | |
7992 | MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); | |
7993 | REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); | |
7994 | } | |
7995 | } | |
7996 | ||
72fd0718 VZ |
7997 | /* Close gates #2, #3 and #4: */ |
7998 | static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) | |
7999 | { | |
c9ee9206 | 8000 | u32 val; |
72fd0718 VZ |
8001 | |
8002 | /* Gates #2 and #4a are closed/opened for "not E1" only */ | |
8003 | if (!CHIP_IS_E1(bp)) { | |
8004 | /* #4 */ | |
c9ee9206 | 8005 | REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); |
72fd0718 | 8006 | /* #2 */ |
c9ee9206 | 8007 | REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); |
72fd0718 VZ |
8008 | } |
8009 | ||
8010 | /* #3 */ | |
c9ee9206 VZ |
8011 | if (CHIP_IS_E1x(bp)) { |
8012 | /* Prevent interrupts from HC on both ports */ | |
8013 | val = REG_RD(bp, HC_REG_CONFIG_1); | |
8014 | REG_WR(bp, HC_REG_CONFIG_1, | |
8015 | (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : | |
8016 | (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); | |
8017 | ||
8018 | val = REG_RD(bp, HC_REG_CONFIG_0); | |
8019 | REG_WR(bp, HC_REG_CONFIG_0, | |
8020 | (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : | |
8021 | (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); | |
8022 | } else { | |
8023 | /* Prevent incomming interrupts in IGU */ | |
8024 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); | |
8025 | ||
8026 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, | |
8027 | (!close) ? | |
8028 | (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : | |
8029 | (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); | |
8030 | } | |
72fd0718 | 8031 | |
51c1a580 | 8032 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", |
72fd0718 VZ |
8033 | close ? "closing" : "opening"); |
8034 | mmiowb(); | |
8035 | } | |
8036 | ||
8037 | #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ | |
8038 | ||
8039 | static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) | |
8040 | { | |
8041 | /* Do some magic... */ | |
8042 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); | |
8043 | *magic_val = val & SHARED_MF_CLP_MAGIC; | |
8044 | MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); | |
8045 | } | |
8046 | ||
e8920674 DK |
8047 | /** |
8048 | * bnx2x_clp_reset_done - restore the value of the `magic' bit. | |
72fd0718 | 8049 | * |
e8920674 DK |
8050 | * @bp: driver handle |
8051 | * @magic_val: old value of the `magic' bit. | |
72fd0718 VZ |
8052 | */ |
8053 | static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) | |
8054 | { | |
8055 | /* Restore the `magic' bit value... */ | |
72fd0718 VZ |
8056 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
8057 | MF_CFG_WR(bp, shared_mf_config.clp_mb, | |
8058 | (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); | |
8059 | } | |
8060 | ||
f85582f8 | 8061 | /** |
e8920674 | 8062 | * bnx2x_reset_mcp_prep - prepare for MCP reset. |
72fd0718 | 8063 | * |
e8920674 DK |
8064 | * @bp: driver handle |
8065 | * @magic_val: old value of 'magic' bit. | |
8066 | * | |
8067 | * Takes care of CLP configurations. | |
72fd0718 VZ |
8068 | */ |
8069 | static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) | |
8070 | { | |
8071 | u32 shmem; | |
8072 | u32 validity_offset; | |
8073 | ||
51c1a580 | 8074 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); |
72fd0718 VZ |
8075 | |
8076 | /* Set `magic' bit in order to save MF config */ | |
8077 | if (!CHIP_IS_E1(bp)) | |
8078 | bnx2x_clp_reset_prep(bp, magic_val); | |
8079 | ||
8080 | /* Get shmem offset */ | |
8081 | shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
8082 | validity_offset = offsetof(struct shmem_region, validity_map[0]); | |
8083 | ||
8084 | /* Clear validity map flags */ | |
8085 | if (shmem > 0) | |
8086 | REG_WR(bp, shmem + validity_offset, 0); | |
8087 | } | |
8088 | ||
8089 | #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ | |
8090 | #define MCP_ONE_TIMEOUT 100 /* 100 ms */ | |
8091 | ||
e8920674 DK |
8092 | /** |
8093 | * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT | |
72fd0718 | 8094 | * |
e8920674 | 8095 | * @bp: driver handle |
72fd0718 VZ |
8096 | */ |
8097 | static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) | |
8098 | { | |
8099 | /* special handling for emulation and FPGA, | |
8100 | wait 10 times longer */ | |
8101 | if (CHIP_REV_IS_SLOW(bp)) | |
8102 | msleep(MCP_ONE_TIMEOUT*10); | |
8103 | else | |
8104 | msleep(MCP_ONE_TIMEOUT); | |
8105 | } | |
8106 | ||
1b6e2ceb DK |
8107 | /* |
8108 | * initializes bp->common.shmem_base and waits for validity signature to appear | |
8109 | */ | |
8110 | static int bnx2x_init_shmem(struct bnx2x *bp) | |
72fd0718 | 8111 | { |
1b6e2ceb DK |
8112 | int cnt = 0; |
8113 | u32 val = 0; | |
72fd0718 | 8114 | |
1b6e2ceb DK |
8115 | do { |
8116 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
8117 | if (bp->common.shmem_base) { | |
8118 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
8119 | if (val & SHR_MEM_VALIDITY_MB) | |
8120 | return 0; | |
8121 | } | |
72fd0718 | 8122 | |
1b6e2ceb | 8123 | bnx2x_mcp_wait_one(bp); |
72fd0718 | 8124 | |
1b6e2ceb | 8125 | } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); |
72fd0718 | 8126 | |
1b6e2ceb | 8127 | BNX2X_ERR("BAD MCP validity signature\n"); |
72fd0718 | 8128 | |
1b6e2ceb DK |
8129 | return -ENODEV; |
8130 | } | |
72fd0718 | 8131 | |
1b6e2ceb DK |
8132 | static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) |
8133 | { | |
8134 | int rc = bnx2x_init_shmem(bp); | |
72fd0718 | 8135 | |
72fd0718 VZ |
8136 | /* Restore the `magic' bit value */ |
8137 | if (!CHIP_IS_E1(bp)) | |
8138 | bnx2x_clp_reset_done(bp, magic_val); | |
8139 | ||
8140 | return rc; | |
8141 | } | |
8142 | ||
8143 | static void bnx2x_pxp_prep(struct bnx2x *bp) | |
8144 | { | |
8145 | if (!CHIP_IS_E1(bp)) { | |
8146 | REG_WR(bp, PXP2_REG_RD_START_INIT, 0); | |
8147 | REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); | |
72fd0718 VZ |
8148 | mmiowb(); |
8149 | } | |
8150 | } | |
8151 | ||
8152 | /* | |
8153 | * Reset the whole chip except for: | |
8154 | * - PCIE core | |
8155 | * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by | |
8156 | * one reset bit) | |
8157 | * - IGU | |
8158 | * - MISC (including AEU) | |
8159 | * - GRC | |
8160 | * - RBCN, RBCP | |
8161 | */ | |
c9ee9206 | 8162 | static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) |
72fd0718 VZ |
8163 | { |
8164 | u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; | |
8736c826 | 8165 | u32 global_bits2, stay_reset2; |
c9ee9206 VZ |
8166 | |
8167 | /* | |
8168 | * Bits that have to be set in reset_mask2 if we want to reset 'global' | |
8169 | * (per chip) blocks. | |
8170 | */ | |
8171 | global_bits2 = | |
8172 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | | |
8173 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; | |
72fd0718 | 8174 | |
8736c826 | 8175 | /* Don't reset the following blocks */ |
72fd0718 VZ |
8176 | not_reset_mask1 = |
8177 | MISC_REGISTERS_RESET_REG_1_RST_HC | | |
8178 | MISC_REGISTERS_RESET_REG_1_RST_PXPV | | |
8179 | MISC_REGISTERS_RESET_REG_1_RST_PXP; | |
8180 | ||
8181 | not_reset_mask2 = | |
c9ee9206 | 8182 | MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | |
72fd0718 VZ |
8183 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | |
8184 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | | |
8185 | MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | | |
8186 | MISC_REGISTERS_RESET_REG_2_RST_RBCN | | |
8187 | MISC_REGISTERS_RESET_REG_2_RST_GRC | | |
8188 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | | |
8736c826 VZ |
8189 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | |
8190 | MISC_REGISTERS_RESET_REG_2_RST_ATC | | |
8191 | MISC_REGISTERS_RESET_REG_2_PGLC; | |
72fd0718 | 8192 | |
8736c826 VZ |
8193 | /* |
8194 | * Keep the following blocks in reset: | |
8195 | * - all xxMACs are handled by the bnx2x_link code. | |
8196 | */ | |
8197 | stay_reset2 = | |
8198 | MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | | |
8199 | MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | | |
8200 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | | |
8201 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | | |
8202 | MISC_REGISTERS_RESET_REG_2_UMAC0 | | |
8203 | MISC_REGISTERS_RESET_REG_2_UMAC1 | | |
8204 | MISC_REGISTERS_RESET_REG_2_XMAC | | |
8205 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; | |
8206 | ||
8207 | /* Full reset masks according to the chip */ | |
72fd0718 VZ |
8208 | reset_mask1 = 0xffffffff; |
8209 | ||
8210 | if (CHIP_IS_E1(bp)) | |
8211 | reset_mask2 = 0xffff; | |
8736c826 | 8212 | else if (CHIP_IS_E1H(bp)) |
72fd0718 | 8213 | reset_mask2 = 0x1ffff; |
8736c826 VZ |
8214 | else if (CHIP_IS_E2(bp)) |
8215 | reset_mask2 = 0xfffff; | |
8216 | else /* CHIP_IS_E3 */ | |
8217 | reset_mask2 = 0x3ffffff; | |
c9ee9206 VZ |
8218 | |
8219 | /* Don't reset global blocks unless we need to */ | |
8220 | if (!global) | |
8221 | reset_mask2 &= ~global_bits2; | |
8222 | ||
8223 | /* | |
8224 | * In case of attention in the QM, we need to reset PXP | |
8225 | * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM | |
8226 | * because otherwise QM reset would release 'close the gates' shortly | |
8227 | * before resetting the PXP, then the PSWRQ would send a write | |
8228 | * request to PGLUE. Then when PXP is reset, PGLUE would try to | |
8229 | * read the payload data from PSWWR, but PSWWR would not | |
8230 | * respond. The write queue in PGLUE would stuck, dmae commands | |
8231 | * would not return. Therefore it's important to reset the second | |
8232 | * reset register (containing the | |
8233 | * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the | |
8234 | * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM | |
8235 | * bit). | |
8236 | */ | |
72fd0718 VZ |
8237 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
8238 | reset_mask2 & (~not_reset_mask2)); | |
8239 | ||
c9ee9206 VZ |
8240 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
8241 | reset_mask1 & (~not_reset_mask1)); | |
8242 | ||
72fd0718 VZ |
8243 | barrier(); |
8244 | mmiowb(); | |
8245 | ||
8736c826 VZ |
8246 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
8247 | reset_mask2 & (~stay_reset2)); | |
8248 | ||
8249 | barrier(); | |
8250 | mmiowb(); | |
8251 | ||
c9ee9206 | 8252 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); |
72fd0718 VZ |
8253 | mmiowb(); |
8254 | } | |
8255 | ||
c9ee9206 VZ |
8256 | /** |
8257 | * bnx2x_er_poll_igu_vq - poll for pending writes bit. | |
8258 | * It should get cleared in no more than 1s. | |
8259 | * | |
8260 | * @bp: driver handle | |
8261 | * | |
8262 | * It should get cleared in no more than 1s. Returns 0 if | |
8263 | * pending writes bit gets cleared. | |
8264 | */ | |
8265 | static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) | |
8266 | { | |
8267 | u32 cnt = 1000; | |
8268 | u32 pend_bits = 0; | |
8269 | ||
8270 | do { | |
8271 | pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); | |
8272 | ||
8273 | if (pend_bits == 0) | |
8274 | break; | |
8275 | ||
8276 | usleep_range(1000, 1000); | |
8277 | } while (cnt-- > 0); | |
8278 | ||
8279 | if (cnt <= 0) { | |
8280 | BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", | |
8281 | pend_bits); | |
8282 | return -EBUSY; | |
8283 | } | |
8284 | ||
8285 | return 0; | |
8286 | } | |
8287 | ||
8288 | static int bnx2x_process_kill(struct bnx2x *bp, bool global) | |
72fd0718 VZ |
8289 | { |
8290 | int cnt = 1000; | |
8291 | u32 val = 0; | |
8292 | u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; | |
8293 | ||
8294 | ||
8295 | /* Empty the Tetris buffer, wait for 1s */ | |
8296 | do { | |
8297 | sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); | |
8298 | blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); | |
8299 | port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); | |
8300 | port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); | |
8301 | pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); | |
8302 | if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && | |
8303 | ((port_is_idle_0 & 0x1) == 0x1) && | |
8304 | ((port_is_idle_1 & 0x1) == 0x1) && | |
8305 | (pgl_exp_rom2 == 0xffffffff)) | |
8306 | break; | |
c9ee9206 | 8307 | usleep_range(1000, 1000); |
72fd0718 VZ |
8308 | } while (cnt-- > 0); |
8309 | ||
8310 | if (cnt <= 0) { | |
51c1a580 MS |
8311 | BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); |
8312 | BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", | |
72fd0718 VZ |
8313 | sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, |
8314 | pgl_exp_rom2); | |
8315 | return -EAGAIN; | |
8316 | } | |
8317 | ||
8318 | barrier(); | |
8319 | ||
8320 | /* Close gates #2, #3 and #4 */ | |
8321 | bnx2x_set_234_gates(bp, true); | |
8322 | ||
c9ee9206 VZ |
8323 | /* Poll for IGU VQs for 57712 and newer chips */ |
8324 | if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) | |
8325 | return -EAGAIN; | |
8326 | ||
8327 | ||
72fd0718 VZ |
8328 | /* TBD: Indicate that "process kill" is in progress to MCP */ |
8329 | ||
8330 | /* Clear "unprepared" bit */ | |
8331 | REG_WR(bp, MISC_REG_UNPREPARED, 0); | |
8332 | barrier(); | |
8333 | ||
8334 | /* Make sure all is written to the chip before the reset */ | |
8335 | mmiowb(); | |
8336 | ||
8337 | /* Wait for 1ms to empty GLUE and PCI-E core queues, | |
8338 | * PSWHST, GRC and PSWRD Tetris buffer. | |
8339 | */ | |
c9ee9206 | 8340 | usleep_range(1000, 1000); |
72fd0718 VZ |
8341 | |
8342 | /* Prepare to chip reset: */ | |
8343 | /* MCP */ | |
c9ee9206 VZ |
8344 | if (global) |
8345 | bnx2x_reset_mcp_prep(bp, &val); | |
72fd0718 VZ |
8346 | |
8347 | /* PXP */ | |
8348 | bnx2x_pxp_prep(bp); | |
8349 | barrier(); | |
8350 | ||
8351 | /* reset the chip */ | |
c9ee9206 | 8352 | bnx2x_process_kill_chip_reset(bp, global); |
72fd0718 VZ |
8353 | barrier(); |
8354 | ||
8355 | /* Recover after reset: */ | |
8356 | /* MCP */ | |
c9ee9206 | 8357 | if (global && bnx2x_reset_mcp_comp(bp, val)) |
72fd0718 VZ |
8358 | return -EAGAIN; |
8359 | ||
c9ee9206 VZ |
8360 | /* TBD: Add resetting the NO_MCP mode DB here */ |
8361 | ||
72fd0718 VZ |
8362 | /* PXP */ |
8363 | bnx2x_pxp_prep(bp); | |
8364 | ||
8365 | /* Open the gates #2, #3 and #4 */ | |
8366 | bnx2x_set_234_gates(bp, false); | |
8367 | ||
8368 | /* TBD: IGU/AEU preparation bring back the AEU/IGU to a | |
8369 | * reset state, re-enable attentions. */ | |
8370 | ||
a2fbb9ea ET |
8371 | return 0; |
8372 | } | |
8373 | ||
c9ee9206 | 8374 | int bnx2x_leader_reset(struct bnx2x *bp) |
72fd0718 VZ |
8375 | { |
8376 | int rc = 0; | |
c9ee9206 | 8377 | bool global = bnx2x_reset_is_global(bp); |
95c6c616 AE |
8378 | u32 load_code; |
8379 | ||
8380 | /* if not going to reset MCP - load "fake" driver to reset HW while | |
8381 | * driver is owner of the HW | |
8382 | */ | |
8383 | if (!global && !BP_NOMCP(bp)) { | |
8384 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0); | |
8385 | if (!load_code) { | |
8386 | BNX2X_ERR("MCP response failure, aborting\n"); | |
8387 | rc = -EAGAIN; | |
8388 | goto exit_leader_reset; | |
8389 | } | |
8390 | if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && | |
8391 | (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { | |
8392 | BNX2X_ERR("MCP unexpected resp, aborting\n"); | |
8393 | rc = -EAGAIN; | |
8394 | goto exit_leader_reset2; | |
8395 | } | |
8396 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); | |
8397 | if (!load_code) { | |
8398 | BNX2X_ERR("MCP response failure, aborting\n"); | |
8399 | rc = -EAGAIN; | |
8400 | goto exit_leader_reset2; | |
8401 | } | |
8402 | } | |
c9ee9206 | 8403 | |
72fd0718 | 8404 | /* Try to recover after the failure */ |
c9ee9206 | 8405 | if (bnx2x_process_kill(bp, global)) { |
51c1a580 MS |
8406 | BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", |
8407 | BP_PATH(bp)); | |
72fd0718 | 8408 | rc = -EAGAIN; |
95c6c616 | 8409 | goto exit_leader_reset2; |
72fd0718 VZ |
8410 | } |
8411 | ||
c9ee9206 VZ |
8412 | /* |
8413 | * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver | |
8414 | * state. | |
8415 | */ | |
72fd0718 | 8416 | bnx2x_set_reset_done(bp); |
c9ee9206 VZ |
8417 | if (global) |
8418 | bnx2x_clear_reset_global(bp); | |
72fd0718 | 8419 | |
95c6c616 AE |
8420 | exit_leader_reset2: |
8421 | /* unload "fake driver" if it was loaded */ | |
8422 | if (!global && !BP_NOMCP(bp)) { | |
8423 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); | |
8424 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
8425 | } | |
72fd0718 VZ |
8426 | exit_leader_reset: |
8427 | bp->is_leader = 0; | |
c9ee9206 VZ |
8428 | bnx2x_release_leader_lock(bp); |
8429 | smp_mb(); | |
72fd0718 VZ |
8430 | return rc; |
8431 | } | |
8432 | ||
c9ee9206 VZ |
8433 | static inline void bnx2x_recovery_failed(struct bnx2x *bp) |
8434 | { | |
8435 | netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); | |
8436 | ||
8437 | /* Disconnect this device */ | |
8438 | netif_device_detach(bp->dev); | |
8439 | ||
8440 | /* | |
8441 | * Block ifup for all function on this engine until "process kill" | |
8442 | * or power cycle. | |
8443 | */ | |
8444 | bnx2x_set_reset_in_progress(bp); | |
8445 | ||
8446 | /* Shut down the power */ | |
8447 | bnx2x_set_power_state(bp, PCI_D3hot); | |
8448 | ||
8449 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
8450 | ||
8451 | smp_mb(); | |
8452 | } | |
8453 | ||
8454 | /* | |
8455 | * Assumption: runs under rtnl lock. This together with the fact | |
6383c0b3 | 8456 | * that it's called only from bnx2x_sp_rtnl() ensure that it |
72fd0718 VZ |
8457 | * will never be called when netif_running(bp->dev) is false. |
8458 | */ | |
8459 | static void bnx2x_parity_recover(struct bnx2x *bp) | |
8460 | { | |
c9ee9206 | 8461 | bool global = false; |
7a752993 | 8462 | u32 error_recovered, error_unrecovered; |
95c6c616 | 8463 | bool is_parity; |
c9ee9206 | 8464 | |
72fd0718 VZ |
8465 | DP(NETIF_MSG_HW, "Handling parity\n"); |
8466 | while (1) { | |
8467 | switch (bp->recovery_state) { | |
8468 | case BNX2X_RECOVERY_INIT: | |
8469 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); | |
95c6c616 AE |
8470 | is_parity = bnx2x_chk_parity_attn(bp, &global, false); |
8471 | WARN_ON(!is_parity); | |
c9ee9206 | 8472 | |
72fd0718 | 8473 | /* Try to get a LEADER_LOCK HW lock */ |
c9ee9206 VZ |
8474 | if (bnx2x_trylock_leader_lock(bp)) { |
8475 | bnx2x_set_reset_in_progress(bp); | |
8476 | /* | |
8477 | * Check if there is a global attention and if | |
8478 | * there was a global attention, set the global | |
8479 | * reset bit. | |
8480 | */ | |
8481 | ||
8482 | if (global) | |
8483 | bnx2x_set_reset_global(bp); | |
8484 | ||
72fd0718 | 8485 | bp->is_leader = 1; |
c9ee9206 | 8486 | } |
72fd0718 VZ |
8487 | |
8488 | /* Stop the driver */ | |
8489 | /* If interface has been removed - break */ | |
8490 | if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) | |
8491 | return; | |
8492 | ||
8493 | bp->recovery_state = BNX2X_RECOVERY_WAIT; | |
c9ee9206 | 8494 | |
c9ee9206 VZ |
8495 | /* Ensure "is_leader", MCP command sequence and |
8496 | * "recovery_state" update values are seen on other | |
8497 | * CPUs. | |
72fd0718 | 8498 | */ |
c9ee9206 | 8499 | smp_mb(); |
72fd0718 VZ |
8500 | break; |
8501 | ||
8502 | case BNX2X_RECOVERY_WAIT: | |
8503 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); | |
8504 | if (bp->is_leader) { | |
c9ee9206 | 8505 | int other_engine = BP_PATH(bp) ? 0 : 1; |
889b9af3 AE |
8506 | bool other_load_status = |
8507 | bnx2x_get_load_status(bp, other_engine); | |
8508 | bool load_status = | |
8509 | bnx2x_get_load_status(bp, BP_PATH(bp)); | |
c9ee9206 VZ |
8510 | global = bnx2x_reset_is_global(bp); |
8511 | ||
8512 | /* | |
8513 | * In case of a parity in a global block, let | |
8514 | * the first leader that performs a | |
8515 | * leader_reset() reset the global blocks in | |
8516 | * order to clear global attentions. Otherwise | |
8517 | * the the gates will remain closed for that | |
8518 | * engine. | |
8519 | */ | |
889b9af3 AE |
8520 | if (load_status || |
8521 | (global && other_load_status)) { | |
72fd0718 VZ |
8522 | /* Wait until all other functions get |
8523 | * down. | |
8524 | */ | |
7be08a72 | 8525 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
8526 | HZ/10); |
8527 | return; | |
8528 | } else { | |
8529 | /* If all other functions got down - | |
8530 | * try to bring the chip back to | |
8531 | * normal. In any case it's an exit | |
8532 | * point for a leader. | |
8533 | */ | |
c9ee9206 VZ |
8534 | if (bnx2x_leader_reset(bp)) { |
8535 | bnx2x_recovery_failed(bp); | |
72fd0718 VZ |
8536 | return; |
8537 | } | |
8538 | ||
c9ee9206 VZ |
8539 | /* If we are here, means that the |
8540 | * leader has succeeded and doesn't | |
8541 | * want to be a leader any more. Try | |
8542 | * to continue as a none-leader. | |
8543 | */ | |
8544 | break; | |
72fd0718 VZ |
8545 | } |
8546 | } else { /* non-leader */ | |
c9ee9206 | 8547 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { |
72fd0718 VZ |
8548 | /* Try to get a LEADER_LOCK HW lock as |
8549 | * long as a former leader may have | |
8550 | * been unloaded by the user or | |
8551 | * released a leadership by another | |
8552 | * reason. | |
8553 | */ | |
c9ee9206 | 8554 | if (bnx2x_trylock_leader_lock(bp)) { |
72fd0718 VZ |
8555 | /* I'm a leader now! Restart a |
8556 | * switch case. | |
8557 | */ | |
8558 | bp->is_leader = 1; | |
8559 | break; | |
8560 | } | |
8561 | ||
7be08a72 | 8562 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
8563 | HZ/10); |
8564 | return; | |
8565 | ||
c9ee9206 VZ |
8566 | } else { |
8567 | /* | |
8568 | * If there was a global attention, wait | |
8569 | * for it to be cleared. | |
8570 | */ | |
8571 | if (bnx2x_reset_is_global(bp)) { | |
8572 | schedule_delayed_work( | |
7be08a72 AE |
8573 | &bp->sp_rtnl_task, |
8574 | HZ/10); | |
c9ee9206 VZ |
8575 | return; |
8576 | } | |
8577 | ||
7a752993 AE |
8578 | error_recovered = |
8579 | bp->eth_stats.recoverable_error; | |
8580 | error_unrecovered = | |
8581 | bp->eth_stats.unrecoverable_error; | |
95c6c616 AE |
8582 | bp->recovery_state = |
8583 | BNX2X_RECOVERY_NIC_LOADING; | |
8584 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) { | |
7a752993 | 8585 | error_unrecovered++; |
95c6c616 | 8586 | netdev_err(bp->dev, |
51c1a580 | 8587 | "Recovery failed. Power cycle needed\n"); |
95c6c616 AE |
8588 | /* Disconnect this device */ |
8589 | netif_device_detach(bp->dev); | |
8590 | /* Shut down the power */ | |
8591 | bnx2x_set_power_state( | |
8592 | bp, PCI_D3hot); | |
8593 | smp_mb(); | |
8594 | } else { | |
c9ee9206 VZ |
8595 | bp->recovery_state = |
8596 | BNX2X_RECOVERY_DONE; | |
7a752993 | 8597 | error_recovered++; |
c9ee9206 VZ |
8598 | smp_mb(); |
8599 | } | |
7a752993 AE |
8600 | bp->eth_stats.recoverable_error = |
8601 | error_recovered; | |
8602 | bp->eth_stats.unrecoverable_error = | |
8603 | error_unrecovered; | |
c9ee9206 | 8604 | |
72fd0718 VZ |
8605 | return; |
8606 | } | |
8607 | } | |
8608 | default: | |
8609 | return; | |
8610 | } | |
8611 | } | |
8612 | } | |
8613 | ||
56ad3152 MS |
8614 | static int bnx2x_close(struct net_device *dev); |
8615 | ||
72fd0718 VZ |
8616 | /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is |
8617 | * scheduled on a general queue in order to prevent a dead lock. | |
8618 | */ | |
7be08a72 | 8619 | static void bnx2x_sp_rtnl_task(struct work_struct *work) |
34f80b04 | 8620 | { |
7be08a72 | 8621 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); |
34f80b04 EG |
8622 | |
8623 | rtnl_lock(); | |
8624 | ||
8625 | if (!netif_running(bp->dev)) | |
7be08a72 AE |
8626 | goto sp_rtnl_exit; |
8627 | ||
8628 | /* if stop on error is defined no recovery flows should be executed */ | |
8629 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 8630 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" |
7be08a72 | 8631 | "you will need to reboot when done\n"); |
b1fb8740 | 8632 | goto sp_rtnl_not_reset; |
7be08a72 | 8633 | #endif |
34f80b04 | 8634 | |
7be08a72 AE |
8635 | if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { |
8636 | /* | |
b1fb8740 VZ |
8637 | * Clear all pending SP commands as we are going to reset the |
8638 | * function anyway. | |
7be08a72 | 8639 | */ |
b1fb8740 VZ |
8640 | bp->sp_rtnl_state = 0; |
8641 | smp_mb(); | |
8642 | ||
72fd0718 | 8643 | bnx2x_parity_recover(bp); |
b1fb8740 VZ |
8644 | |
8645 | goto sp_rtnl_exit; | |
8646 | } | |
8647 | ||
8648 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { | |
8649 | /* | |
8650 | * Clear all pending SP commands as we are going to reset the | |
8651 | * function anyway. | |
8652 | */ | |
8653 | bp->sp_rtnl_state = 0; | |
8654 | smp_mb(); | |
8655 | ||
72fd0718 VZ |
8656 | bnx2x_nic_unload(bp, UNLOAD_NORMAL); |
8657 | bnx2x_nic_load(bp, LOAD_NORMAL); | |
b1fb8740 VZ |
8658 | |
8659 | goto sp_rtnl_exit; | |
72fd0718 | 8660 | } |
b1fb8740 VZ |
8661 | #ifdef BNX2X_STOP_ON_ERROR |
8662 | sp_rtnl_not_reset: | |
8663 | #endif | |
8664 | if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) | |
8665 | bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); | |
34f80b04 | 8666 | |
8304859a AE |
8667 | /* |
8668 | * in case of fan failure we need to reset id if the "stop on error" | |
8669 | * debug flag is set, since we trying to prevent permanent overheating | |
8670 | * damage | |
8671 | */ | |
8672 | if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { | |
51c1a580 | 8673 | DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); |
8304859a AE |
8674 | netif_device_detach(bp->dev); |
8675 | bnx2x_close(bp->dev); | |
8676 | } | |
8677 | ||
7be08a72 | 8678 | sp_rtnl_exit: |
34f80b04 EG |
8679 | rtnl_unlock(); |
8680 | } | |
8681 | ||
a2fbb9ea ET |
8682 | /* end of nic load/unload */ |
8683 | ||
3deb8167 YR |
8684 | static void bnx2x_period_task(struct work_struct *work) |
8685 | { | |
8686 | struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); | |
8687 | ||
8688 | if (!netif_running(bp->dev)) | |
8689 | goto period_task_exit; | |
8690 | ||
8691 | if (CHIP_REV_IS_SLOW(bp)) { | |
8692 | BNX2X_ERR("period task called on emulation, ignoring\n"); | |
8693 | goto period_task_exit; | |
8694 | } | |
8695 | ||
8696 | bnx2x_acquire_phy_lock(bp); | |
8697 | /* | |
8698 | * The barrier is needed to ensure the ordering between the writing to | |
8699 | * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and | |
8700 | * the reading here. | |
8701 | */ | |
8702 | smp_mb(); | |
8703 | if (bp->port.pmf) { | |
8704 | bnx2x_period_func(&bp->link_params, &bp->link_vars); | |
8705 | ||
8706 | /* Re-queue task in 1 sec */ | |
8707 | queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); | |
8708 | } | |
8709 | ||
8710 | bnx2x_release_phy_lock(bp); | |
8711 | period_task_exit: | |
8712 | return; | |
8713 | } | |
8714 | ||
a2fbb9ea ET |
8715 | /* |
8716 | * Init service functions | |
8717 | */ | |
8718 | ||
8d96286a | 8719 | static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) |
f2e0899f DK |
8720 | { |
8721 | u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
8722 | u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; | |
8723 | return base + (BP_ABS_FUNC(bp)) * stride; | |
f1ef27ef EG |
8724 | } |
8725 | ||
f2e0899f | 8726 | static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) |
f1ef27ef | 8727 | { |
f2e0899f | 8728 | u32 reg = bnx2x_get_pretend_reg(bp); |
f1ef27ef EG |
8729 | |
8730 | /* Flush all outstanding writes */ | |
8731 | mmiowb(); | |
8732 | ||
8733 | /* Pretend to be function 0 */ | |
8734 | REG_WR(bp, reg, 0); | |
f2e0899f | 8735 | REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ |
f1ef27ef EG |
8736 | |
8737 | /* From now we are in the "like-E1" mode */ | |
8738 | bnx2x_int_disable(bp); | |
8739 | ||
8740 | /* Flush all outstanding writes */ | |
8741 | mmiowb(); | |
8742 | ||
f2e0899f DK |
8743 | /* Restore the original function */ |
8744 | REG_WR(bp, reg, BP_ABS_FUNC(bp)); | |
8745 | REG_RD(bp, reg); | |
f1ef27ef EG |
8746 | } |
8747 | ||
f2e0899f | 8748 | static inline void bnx2x_undi_int_disable(struct bnx2x *bp) |
f1ef27ef | 8749 | { |
f2e0899f | 8750 | if (CHIP_IS_E1(bp)) |
f1ef27ef | 8751 | bnx2x_int_disable(bp); |
f2e0899f DK |
8752 | else |
8753 | bnx2x_undi_int_disable_e1h(bp); | |
f1ef27ef EG |
8754 | } |
8755 | ||
452427b0 | 8756 | static void __devinit bnx2x_prev_unload_close_mac(struct bnx2x *bp) |
34f80b04 | 8757 | { |
452427b0 YM |
8758 | u32 val, base_addr, offset, mask, reset_reg; |
8759 | bool mac_stopped = false; | |
8760 | u8 port = BP_PORT(bp); | |
34f80b04 | 8761 | |
452427b0 | 8762 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); |
f16da43b | 8763 | |
452427b0 YM |
8764 | if (!CHIP_IS_E3(bp)) { |
8765 | val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); | |
8766 | mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; | |
8767 | if ((mask & reset_reg) && val) { | |
8768 | u32 wb_data[2]; | |
8769 | BNX2X_DEV_INFO("Disable bmac Rx\n"); | |
8770 | base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM | |
8771 | : NIG_REG_INGRESS_BMAC0_MEM; | |
8772 | offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL | |
8773 | : BIGMAC_REGISTER_BMAC_CONTROL; | |
7a06a122 | 8774 | |
452427b0 YM |
8775 | /* |
8776 | * use rd/wr since we cannot use dmae. This is safe | |
8777 | * since MCP won't access the bus due to the request | |
8778 | * to unload, and no function on the path can be | |
8779 | * loaded at this time. | |
8780 | */ | |
8781 | wb_data[0] = REG_RD(bp, base_addr + offset); | |
8782 | wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); | |
8783 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; | |
8784 | REG_WR(bp, base_addr + offset, wb_data[0]); | |
8785 | REG_WR(bp, base_addr + offset + 0x4, wb_data[1]); | |
8786 | ||
8787 | } | |
8788 | BNX2X_DEV_INFO("Disable emac Rx\n"); | |
8789 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0); | |
8790 | ||
8791 | mac_stopped = true; | |
8792 | } else { | |
8793 | if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { | |
8794 | BNX2X_DEV_INFO("Disable xmac Rx\n"); | |
8795 | base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
8796 | val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); | |
8797 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
8798 | val & ~(1 << 1)); | |
8799 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
8800 | val | (1 << 1)); | |
8801 | REG_WR(bp, base_addr + XMAC_REG_CTRL, 0); | |
8802 | mac_stopped = true; | |
8803 | } | |
8804 | mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; | |
8805 | if (mask & reset_reg) { | |
8806 | BNX2X_DEV_INFO("Disable umac Rx\n"); | |
8807 | base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
8808 | REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0); | |
8809 | mac_stopped = true; | |
8810 | } | |
8811 | } | |
8812 | ||
8813 | if (mac_stopped) | |
8814 | msleep(20); | |
8815 | ||
8816 | } | |
8817 | ||
8818 | #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) | |
8819 | #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) | |
8820 | #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) | |
8821 | #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) | |
8822 | ||
8823 | static void __devinit bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, | |
8824 | u8 inc) | |
8825 | { | |
8826 | u16 rcq, bd; | |
8827 | u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port)); | |
8828 | ||
8829 | rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; | |
8830 | bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; | |
8831 | ||
8832 | tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); | |
8833 | REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg); | |
8834 | ||
8835 | BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n", | |
8836 | port, bd, rcq); | |
8837 | } | |
8838 | ||
8839 | static int __devinit bnx2x_prev_mcp_done(struct bnx2x *bp) | |
8840 | { | |
8841 | u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
8842 | if (!rc) { | |
8843 | BNX2X_ERR("MCP response failure, aborting\n"); | |
8844 | return -EBUSY; | |
8845 | } | |
8846 | ||
8847 | return 0; | |
8848 | } | |
8849 | ||
8850 | static bool __devinit bnx2x_prev_is_path_marked(struct bnx2x *bp) | |
8851 | { | |
8852 | struct bnx2x_prev_path_list *tmp_list; | |
8853 | int rc = false; | |
8854 | ||
8855 | if (down_trylock(&bnx2x_prev_sem)) | |
8856 | return false; | |
8857 | ||
8858 | list_for_each_entry(tmp_list, &bnx2x_prev_list, list) { | |
8859 | if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && | |
8860 | bp->pdev->bus->number == tmp_list->bus && | |
8861 | BP_PATH(bp) == tmp_list->path) { | |
8862 | rc = true; | |
8863 | BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", | |
8864 | BP_PATH(bp)); | |
8865 | break; | |
8866 | } | |
8867 | } | |
8868 | ||
8869 | up(&bnx2x_prev_sem); | |
8870 | ||
8871 | return rc; | |
8872 | } | |
8873 | ||
8874 | static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp) | |
8875 | { | |
8876 | struct bnx2x_prev_path_list *tmp_list; | |
8877 | int rc; | |
8878 | ||
8879 | tmp_list = (struct bnx2x_prev_path_list *) | |
8880 | kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); | |
8881 | if (!tmp_list) { | |
8882 | BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); | |
8883 | return -ENOMEM; | |
8884 | } | |
8885 | ||
8886 | tmp_list->bus = bp->pdev->bus->number; | |
8887 | tmp_list->slot = PCI_SLOT(bp->pdev->devfn); | |
8888 | tmp_list->path = BP_PATH(bp); | |
8889 | ||
8890 | rc = down_interruptible(&bnx2x_prev_sem); | |
8891 | if (rc) { | |
8892 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
8893 | kfree(tmp_list); | |
8894 | } else { | |
8895 | BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n", | |
8896 | BP_PATH(bp)); | |
8897 | list_add(&tmp_list->list, &bnx2x_prev_list); | |
8898 | up(&bnx2x_prev_sem); | |
8899 | } | |
8900 | ||
8901 | return rc; | |
8902 | } | |
8903 | ||
8904 | static bool __devinit bnx2x_can_flr(struct bnx2x *bp) | |
8905 | { | |
8906 | int pos; | |
8907 | u32 cap; | |
8908 | struct pci_dev *dev = bp->pdev; | |
8909 | ||
8910 | pos = pci_pcie_cap(dev); | |
8911 | if (!pos) | |
8912 | return false; | |
8913 | ||
8914 | pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap); | |
8915 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | |
8916 | return false; | |
8917 | ||
8918 | return true; | |
8919 | } | |
8920 | ||
8921 | static int __devinit bnx2x_do_flr(struct bnx2x *bp) | |
8922 | { | |
8923 | int i, pos; | |
8924 | u16 status; | |
8925 | struct pci_dev *dev = bp->pdev; | |
8926 | ||
8927 | /* probe the capability first */ | |
8928 | if (bnx2x_can_flr(bp)) | |
8929 | return -ENOTTY; | |
8930 | ||
8931 | pos = pci_pcie_cap(dev); | |
8932 | if (!pos) | |
8933 | return -ENOTTY; | |
8934 | ||
8935 | /* Wait for Transaction Pending bit clean */ | |
8936 | for (i = 0; i < 4; i++) { | |
8937 | if (i) | |
8938 | msleep((1 << (i - 1)) * 100); | |
8939 | ||
8940 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); | |
8941 | if (!(status & PCI_EXP_DEVSTA_TRPND)) | |
8942 | goto clear; | |
8943 | } | |
8944 | ||
8945 | dev_err(&dev->dev, | |
8946 | "transaction is not cleared; proceeding with reset anyway\n"); | |
8947 | ||
8948 | clear: | |
8949 | if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { | |
8950 | BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", | |
8951 | bp->common.bc_ver); | |
8952 | return -EINVAL; | |
8953 | } | |
8954 | ||
8955 | bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); | |
8956 | ||
8957 | return 0; | |
8958 | } | |
8959 | ||
8960 | static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp) | |
8961 | { | |
8962 | int rc; | |
8963 | ||
8964 | BNX2X_DEV_INFO("Uncommon unload Flow\n"); | |
8965 | ||
8966 | /* Test if previous unload process was already finished for this path */ | |
8967 | if (bnx2x_prev_is_path_marked(bp)) | |
8968 | return bnx2x_prev_mcp_done(bp); | |
8969 | ||
8970 | /* If function has FLR capabilities, and existing FW version matches | |
8971 | * the one required, then FLR will be sufficient to clean any residue | |
8972 | * left by previous driver | |
8973 | */ | |
8974 | if (bnx2x_test_firmware_version(bp, false) && bnx2x_can_flr(bp)) | |
8975 | return bnx2x_do_flr(bp); | |
8976 | ||
8977 | /* Close the MCP request, return failure*/ | |
8978 | rc = bnx2x_prev_mcp_done(bp); | |
8979 | if (!rc) | |
8980 | rc = BNX2X_PREV_WAIT_NEEDED; | |
8981 | ||
8982 | return rc; | |
8983 | } | |
8984 | ||
8985 | static int __devinit bnx2x_prev_unload_common(struct bnx2x *bp) | |
8986 | { | |
8987 | u32 reset_reg, tmp_reg = 0, rc; | |
8988 | /* It is possible a previous function received 'common' answer, | |
8989 | * but hasn't loaded yet, therefore creating a scenario of | |
8990 | * multiple functions receiving 'common' on the same path. | |
8991 | */ | |
8992 | BNX2X_DEV_INFO("Common unload Flow\n"); | |
8993 | ||
8994 | if (bnx2x_prev_is_path_marked(bp)) | |
8995 | return bnx2x_prev_mcp_done(bp); | |
8996 | ||
8997 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); | |
8998 | ||
8999 | /* Reset should be performed after BRB is emptied */ | |
9000 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { | |
9001 | u32 timer_count = 1000; | |
9002 | bool prev_undi = false; | |
9003 | ||
9004 | /* Close the MAC Rx to prevent BRB from filling up */ | |
9005 | bnx2x_prev_unload_close_mac(bp); | |
9006 | ||
9007 | /* Check if the UNDI driver was previously loaded | |
34f80b04 EG |
9008 | * UNDI driver initializes CID offset for normal bell to 0x7 |
9009 | */ | |
452427b0 YM |
9010 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); |
9011 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { | |
9012 | tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST); | |
9013 | if (tmp_reg == 0x7) { | |
9014 | BNX2X_DEV_INFO("UNDI previously loaded\n"); | |
9015 | prev_undi = true; | |
9016 | /* clear the UNDI indication */ | |
9017 | REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); | |
34f80b04 | 9018 | } |
452427b0 YM |
9019 | } |
9020 | /* wait until BRB is empty */ | |
9021 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); | |
9022 | while (timer_count) { | |
9023 | u32 prev_brb = tmp_reg; | |
34f80b04 | 9024 | |
452427b0 YM |
9025 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); |
9026 | if (!tmp_reg) | |
9027 | break; | |
619c5cb6 | 9028 | |
452427b0 | 9029 | BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); |
619c5cb6 | 9030 | |
452427b0 YM |
9031 | /* reset timer as long as BRB actually gets emptied */ |
9032 | if (prev_brb > tmp_reg) | |
9033 | timer_count = 1000; | |
9034 | else | |
9035 | timer_count--; | |
da5a662a | 9036 | |
452427b0 YM |
9037 | /* If UNDI resides in memory, manually increment it */ |
9038 | if (prev_undi) | |
9039 | bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1); | |
da5a662a | 9040 | |
452427b0 | 9041 | udelay(10); |
7a06a122 | 9042 | } |
452427b0 YM |
9043 | |
9044 | if (!timer_count) | |
9045 | BNX2X_ERR("Failed to empty BRB, hope for the best\n"); | |
9046 | ||
34f80b04 | 9047 | } |
f16da43b | 9048 | |
452427b0 YM |
9049 | /* No packets are in the pipeline, path is ready for reset */ |
9050 | bnx2x_reset_common(bp); | |
9051 | ||
9052 | rc = bnx2x_prev_mark_path(bp); | |
9053 | if (rc) { | |
9054 | bnx2x_prev_mcp_done(bp); | |
9055 | return rc; | |
9056 | } | |
9057 | ||
9058 | return bnx2x_prev_mcp_done(bp); | |
9059 | } | |
9060 | ||
9061 | static int __devinit bnx2x_prev_unload(struct bnx2x *bp) | |
9062 | { | |
9063 | int time_counter = 10; | |
9064 | u32 rc, fw, hw_lock_reg, hw_lock_val; | |
9065 | BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); | |
9066 | ||
9067 | /* Release previously held locks */ | |
9068 | hw_lock_reg = (BP_FUNC(bp) <= 5) ? | |
9069 | (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : | |
9070 | (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); | |
9071 | ||
9072 | hw_lock_val = (REG_RD(bp, hw_lock_reg)); | |
9073 | if (hw_lock_val) { | |
9074 | if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { | |
9075 | BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); | |
9076 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
9077 | (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); | |
9078 | } | |
9079 | ||
9080 | BNX2X_DEV_INFO("Release Previously held hw lock\n"); | |
9081 | REG_WR(bp, hw_lock_reg, 0xffffffff); | |
9082 | } else | |
9083 | BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); | |
9084 | ||
9085 | if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { | |
9086 | BNX2X_DEV_INFO("Release previously held alr\n"); | |
9087 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); | |
9088 | } | |
9089 | ||
9090 | ||
9091 | do { | |
9092 | /* Lock MCP using an unload request */ | |
9093 | fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); | |
9094 | if (!fw) { | |
9095 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9096 | rc = -EBUSY; | |
9097 | break; | |
9098 | } | |
9099 | ||
9100 | if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) { | |
9101 | rc = bnx2x_prev_unload_common(bp); | |
9102 | break; | |
9103 | } | |
9104 | ||
9105 | /* non-common reply from MCP night require looping */ | |
9106 | rc = bnx2x_prev_unload_uncommon(bp); | |
9107 | if (rc != BNX2X_PREV_WAIT_NEEDED) | |
9108 | break; | |
9109 | ||
9110 | msleep(20); | |
9111 | } while (--time_counter); | |
9112 | ||
9113 | if (!time_counter || rc) { | |
9114 | BNX2X_ERR("Failed unloading previous driver, aborting\n"); | |
9115 | rc = -EBUSY; | |
9116 | } | |
9117 | ||
9118 | BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); | |
9119 | ||
9120 | return rc; | |
34f80b04 EG |
9121 | } |
9122 | ||
9123 | static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) | |
9124 | { | |
1d187b34 | 9125 | u32 val, val2, val3, val4, id, boot_mode; |
72ce58c3 | 9126 | u16 pmc; |
34f80b04 EG |
9127 | |
9128 | /* Get the chip revision id and number. */ | |
9129 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | |
9130 | val = REG_RD(bp, MISC_REG_CHIP_NUM); | |
9131 | id = ((val & 0xffff) << 16); | |
9132 | val = REG_RD(bp, MISC_REG_CHIP_REV); | |
9133 | id |= ((val & 0xf) << 12); | |
9134 | val = REG_RD(bp, MISC_REG_CHIP_METAL); | |
9135 | id |= ((val & 0xff) << 4); | |
5a40e08e | 9136 | val = REG_RD(bp, MISC_REG_BOND_ID); |
34f80b04 EG |
9137 | id |= (val & 0xf); |
9138 | bp->common.chip_id = id; | |
523224a3 | 9139 | |
7e8e02df BW |
9140 | /* force 57811 according to MISC register */ |
9141 | if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { | |
9142 | if (CHIP_IS_57810(bp)) | |
9143 | bp->common.chip_id = (CHIP_NUM_57811 << 16) | | |
9144 | (bp->common.chip_id & 0x0000FFFF); | |
9145 | else if (CHIP_IS_57810_MF(bp)) | |
9146 | bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | | |
9147 | (bp->common.chip_id & 0x0000FFFF); | |
9148 | bp->common.chip_id |= 0x1; | |
9149 | } | |
9150 | ||
523224a3 DK |
9151 | /* Set doorbell size */ |
9152 | bp->db_size = (1 << BNX2X_DB_SHIFT); | |
9153 | ||
619c5cb6 | 9154 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
9155 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
9156 | if ((val & 1) == 0) | |
9157 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
9158 | else | |
9159 | val = (val >> 1) & 1; | |
9160 | BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : | |
9161 | "2_PORT_MODE"); | |
9162 | bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : | |
9163 | CHIP_2_PORT_MODE; | |
9164 | ||
9165 | if (CHIP_MODE_IS_4_PORT(bp)) | |
9166 | bp->pfid = (bp->pf_num >> 1); /* 0..3 */ | |
9167 | else | |
9168 | bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ | |
9169 | } else { | |
9170 | bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ | |
9171 | bp->pfid = bp->pf_num; /* 0..7 */ | |
9172 | } | |
9173 | ||
51c1a580 MS |
9174 | BNX2X_DEV_INFO("pf_id: %x", bp->pfid); |
9175 | ||
f2e0899f DK |
9176 | bp->link_params.chip_id = bp->common.chip_id; |
9177 | BNX2X_DEV_INFO("chip ID is 0x%x\n", id); | |
523224a3 | 9178 | |
1c06328c EG |
9179 | val = (REG_RD(bp, 0x2874) & 0x55); |
9180 | if ((bp->common.chip_id & 0x1) || | |
9181 | (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { | |
9182 | bp->flags |= ONE_PORT_FLAG; | |
9183 | BNX2X_DEV_INFO("single port device\n"); | |
9184 | } | |
9185 | ||
34f80b04 | 9186 | val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); |
754a2f52 | 9187 | bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << |
34f80b04 EG |
9188 | (val & MCPR_NVM_CFG4_FLASH_SIZE)); |
9189 | BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", | |
9190 | bp->common.flash_size, bp->common.flash_size); | |
9191 | ||
1b6e2ceb DK |
9192 | bnx2x_init_shmem(bp); |
9193 | ||
619c5cb6 VZ |
9194 | |
9195 | ||
f2e0899f DK |
9196 | bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? |
9197 | MISC_REG_GENERIC_CR_1 : | |
9198 | MISC_REG_GENERIC_CR_0)); | |
1b6e2ceb | 9199 | |
34f80b04 | 9200 | bp->link_params.shmem_base = bp->common.shmem_base; |
a22f0788 | 9201 | bp->link_params.shmem2_base = bp->common.shmem2_base; |
2691d51d EG |
9202 | BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", |
9203 | bp->common.shmem_base, bp->common.shmem2_base); | |
34f80b04 | 9204 | |
f2e0899f | 9205 | if (!bp->common.shmem_base) { |
34f80b04 EG |
9206 | BNX2X_DEV_INFO("MCP not active\n"); |
9207 | bp->flags |= NO_MCP_FLAG; | |
9208 | return; | |
9209 | } | |
9210 | ||
34f80b04 | 9211 | bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
35b19ba5 | 9212 | BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); |
34f80b04 EG |
9213 | |
9214 | bp->link_params.hw_led_mode = ((bp->common.hw_config & | |
9215 | SHARED_HW_CFG_LED_MODE_MASK) >> | |
9216 | SHARED_HW_CFG_LED_MODE_SHIFT); | |
9217 | ||
c2c8b03e EG |
9218 | bp->link_params.feature_config_flags = 0; |
9219 | val = SHMEM_RD(bp, dev_info.shared_feature_config.config); | |
9220 | if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) | |
9221 | bp->link_params.feature_config_flags |= | |
9222 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
9223 | else | |
9224 | bp->link_params.feature_config_flags &= | |
9225 | ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
9226 | ||
34f80b04 EG |
9227 | val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; |
9228 | bp->common.bc_ver = val; | |
9229 | BNX2X_DEV_INFO("bc_ver %X\n", val); | |
9230 | if (val < BNX2X_BC_VER) { | |
9231 | /* for now only warn | |
9232 | * later we might need to enforce this */ | |
51c1a580 MS |
9233 | BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", |
9234 | BNX2X_BC_VER, val); | |
34f80b04 | 9235 | } |
4d295db0 | 9236 | bp->link_params.feature_config_flags |= |
a22f0788 | 9237 | (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? |
f85582f8 DK |
9238 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; |
9239 | ||
a22f0788 YR |
9240 | bp->link_params.feature_config_flags |= |
9241 | (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? | |
9242 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; | |
72ce58c3 | 9243 | |
85242eea YR |
9244 | bp->link_params.feature_config_flags |= |
9245 | (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? | |
9246 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; | |
0e898dd7 BW |
9247 | bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? |
9248 | BC_SUPPORTS_PFC_STATS : 0; | |
85242eea | 9249 | |
1d187b34 BW |
9250 | boot_mode = SHMEM_RD(bp, |
9251 | dev_info.port_feature_config[BP_PORT(bp)].mba_config) & | |
9252 | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; | |
9253 | switch (boot_mode) { | |
9254 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: | |
9255 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; | |
9256 | break; | |
9257 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: | |
9258 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; | |
9259 | break; | |
9260 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: | |
9261 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; | |
9262 | break; | |
9263 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: | |
9264 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; | |
9265 | break; | |
9266 | } | |
9267 | ||
f9a3ebbe DK |
9268 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); |
9269 | bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; | |
9270 | ||
72ce58c3 | 9271 | BNX2X_DEV_INFO("%sWoL capable\n", |
f5372251 | 9272 | (bp->flags & NO_WOL_FLAG) ? "not " : ""); |
34f80b04 EG |
9273 | |
9274 | val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); | |
9275 | val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); | |
9276 | val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); | |
9277 | val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); | |
9278 | ||
cdaa7cb8 VZ |
9279 | dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", |
9280 | val, val2, val3, val4); | |
34f80b04 EG |
9281 | } |
9282 | ||
f2e0899f DK |
9283 | #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) |
9284 | #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) | |
9285 | ||
9286 | static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) | |
9287 | { | |
9288 | int pfid = BP_FUNC(bp); | |
f2e0899f DK |
9289 | int igu_sb_id; |
9290 | u32 val; | |
6383c0b3 | 9291 | u8 fid, igu_sb_cnt = 0; |
f2e0899f DK |
9292 | |
9293 | bp->igu_base_sb = 0xff; | |
f2e0899f | 9294 | if (CHIP_INT_MODE_IS_BC(bp)) { |
3395a033 | 9295 | int vn = BP_VN(bp); |
6383c0b3 | 9296 | igu_sb_cnt = bp->igu_sb_cnt; |
f2e0899f DK |
9297 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
9298 | FP_SB_MAX_E1x; | |
9299 | ||
9300 | bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + | |
9301 | (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); | |
9302 | ||
9303 | return; | |
9304 | } | |
9305 | ||
9306 | /* IGU in normal mode - read CAM */ | |
9307 | for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; | |
9308 | igu_sb_id++) { | |
9309 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); | |
9310 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) | |
9311 | continue; | |
9312 | fid = IGU_FID(val); | |
9313 | if ((fid & IGU_FID_ENCODE_IS_PF)) { | |
9314 | if ((fid & IGU_FID_PF_NUM_MASK) != pfid) | |
9315 | continue; | |
9316 | if (IGU_VEC(val) == 0) | |
9317 | /* default status block */ | |
9318 | bp->igu_dsb_id = igu_sb_id; | |
9319 | else { | |
9320 | if (bp->igu_base_sb == 0xff) | |
9321 | bp->igu_base_sb = igu_sb_id; | |
6383c0b3 | 9322 | igu_sb_cnt++; |
f2e0899f DK |
9323 | } |
9324 | } | |
9325 | } | |
619c5cb6 | 9326 | |
6383c0b3 AE |
9327 | #ifdef CONFIG_PCI_MSI |
9328 | /* | |
9329 | * It's expected that number of CAM entries for this functions is equal | |
9330 | * to the number evaluated based on the MSI-X table size. We want a | |
9331 | * harsh warning if these values are different! | |
619c5cb6 | 9332 | */ |
6383c0b3 AE |
9333 | WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); |
9334 | #endif | |
619c5cb6 | 9335 | |
6383c0b3 | 9336 | if (igu_sb_cnt == 0) |
f2e0899f DK |
9337 | BNX2X_ERR("CAM configuration error\n"); |
9338 | } | |
9339 | ||
34f80b04 EG |
9340 | static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, |
9341 | u32 switch_cfg) | |
a2fbb9ea | 9342 | { |
a22f0788 YR |
9343 | int cfg_size = 0, idx, port = BP_PORT(bp); |
9344 | ||
9345 | /* Aggregation of supported attributes of all external phys */ | |
9346 | bp->port.supported[0] = 0; | |
9347 | bp->port.supported[1] = 0; | |
b7737c9b YR |
9348 | switch (bp->link_params.num_phys) { |
9349 | case 1: | |
a22f0788 YR |
9350 | bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; |
9351 | cfg_size = 1; | |
9352 | break; | |
b7737c9b | 9353 | case 2: |
a22f0788 YR |
9354 | bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; |
9355 | cfg_size = 1; | |
9356 | break; | |
9357 | case 3: | |
9358 | if (bp->link_params.multi_phy_config & | |
9359 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { | |
9360 | bp->port.supported[1] = | |
9361 | bp->link_params.phy[EXT_PHY1].supported; | |
9362 | bp->port.supported[0] = | |
9363 | bp->link_params.phy[EXT_PHY2].supported; | |
9364 | } else { | |
9365 | bp->port.supported[0] = | |
9366 | bp->link_params.phy[EXT_PHY1].supported; | |
9367 | bp->port.supported[1] = | |
9368 | bp->link_params.phy[EXT_PHY2].supported; | |
9369 | } | |
9370 | cfg_size = 2; | |
9371 | break; | |
b7737c9b | 9372 | } |
a2fbb9ea | 9373 | |
a22f0788 | 9374 | if (!(bp->port.supported[0] || bp->port.supported[1])) { |
51c1a580 | 9375 | BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", |
b7737c9b | 9376 | SHMEM_RD(bp, |
a22f0788 YR |
9377 | dev_info.port_hw_config[port].external_phy_config), |
9378 | SHMEM_RD(bp, | |
9379 | dev_info.port_hw_config[port].external_phy_config2)); | |
a2fbb9ea | 9380 | return; |
f85582f8 | 9381 | } |
a2fbb9ea | 9382 | |
619c5cb6 VZ |
9383 | if (CHIP_IS_E3(bp)) |
9384 | bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); | |
9385 | else { | |
9386 | switch (switch_cfg) { | |
9387 | case SWITCH_CFG_1G: | |
9388 | bp->port.phy_addr = REG_RD( | |
9389 | bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); | |
9390 | break; | |
9391 | case SWITCH_CFG_10G: | |
9392 | bp->port.phy_addr = REG_RD( | |
9393 | bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); | |
9394 | break; | |
9395 | default: | |
9396 | BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", | |
9397 | bp->port.link_config[0]); | |
9398 | return; | |
9399 | } | |
a2fbb9ea | 9400 | } |
619c5cb6 | 9401 | BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); |
a22f0788 YR |
9402 | /* mask what we support according to speed_cap_mask per configuration */ |
9403 | for (idx = 0; idx < cfg_size; idx++) { | |
9404 | if (!(bp->link_params.speed_cap_mask[idx] & | |
c18487ee | 9405 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) |
a22f0788 | 9406 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; |
a2fbb9ea | 9407 | |
a22f0788 | 9408 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9409 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) |
a22f0788 | 9410 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; |
a2fbb9ea | 9411 | |
a22f0788 | 9412 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9413 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) |
a22f0788 | 9414 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; |
a2fbb9ea | 9415 | |
a22f0788 | 9416 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9417 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) |
a22f0788 | 9418 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; |
a2fbb9ea | 9419 | |
a22f0788 | 9420 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9421 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) |
a22f0788 | 9422 | bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | |
f85582f8 | 9423 | SUPPORTED_1000baseT_Full); |
a2fbb9ea | 9424 | |
a22f0788 | 9425 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9426 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
a22f0788 | 9427 | bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; |
a2fbb9ea | 9428 | |
a22f0788 | 9429 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9430 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
a22f0788 YR |
9431 | bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; |
9432 | ||
9433 | } | |
a2fbb9ea | 9434 | |
a22f0788 YR |
9435 | BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], |
9436 | bp->port.supported[1]); | |
a2fbb9ea ET |
9437 | } |
9438 | ||
34f80b04 | 9439 | static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) |
a2fbb9ea | 9440 | { |
a22f0788 YR |
9441 | u32 link_config, idx, cfg_size = 0; |
9442 | bp->port.advertising[0] = 0; | |
9443 | bp->port.advertising[1] = 0; | |
9444 | switch (bp->link_params.num_phys) { | |
9445 | case 1: | |
9446 | case 2: | |
9447 | cfg_size = 1; | |
9448 | break; | |
9449 | case 3: | |
9450 | cfg_size = 2; | |
9451 | break; | |
9452 | } | |
9453 | for (idx = 0; idx < cfg_size; idx++) { | |
9454 | bp->link_params.req_duplex[idx] = DUPLEX_FULL; | |
9455 | link_config = bp->port.link_config[idx]; | |
9456 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
f85582f8 | 9457 | case PORT_FEATURE_LINK_SPEED_AUTO: |
a22f0788 YR |
9458 | if (bp->port.supported[idx] & SUPPORTED_Autoneg) { |
9459 | bp->link_params.req_line_speed[idx] = | |
9460 | SPEED_AUTO_NEG; | |
9461 | bp->port.advertising[idx] |= | |
9462 | bp->port.supported[idx]; | |
10bd1f24 MY |
9463 | if (bp->link_params.phy[EXT_PHY1].type == |
9464 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | |
9465 | bp->port.advertising[idx] |= | |
9466 | (SUPPORTED_100baseT_Half | | |
9467 | SUPPORTED_100baseT_Full); | |
f85582f8 DK |
9468 | } else { |
9469 | /* force 10G, no AN */ | |
a22f0788 YR |
9470 | bp->link_params.req_line_speed[idx] = |
9471 | SPEED_10000; | |
9472 | bp->port.advertising[idx] |= | |
9473 | (ADVERTISED_10000baseT_Full | | |
f85582f8 | 9474 | ADVERTISED_FIBRE); |
a22f0788 | 9475 | continue; |
f85582f8 DK |
9476 | } |
9477 | break; | |
a2fbb9ea | 9478 | |
f85582f8 | 9479 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
a22f0788 YR |
9480 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { |
9481 | bp->link_params.req_line_speed[idx] = | |
9482 | SPEED_10; | |
9483 | bp->port.advertising[idx] |= | |
9484 | (ADVERTISED_10baseT_Full | | |
f85582f8 DK |
9485 | ADVERTISED_TP); |
9486 | } else { | |
51c1a580 | 9487 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 | 9488 | link_config, |
a22f0788 | 9489 | bp->link_params.speed_cap_mask[idx]); |
f85582f8 DK |
9490 | return; |
9491 | } | |
9492 | break; | |
a2fbb9ea | 9493 | |
f85582f8 | 9494 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
a22f0788 YR |
9495 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { |
9496 | bp->link_params.req_line_speed[idx] = | |
9497 | SPEED_10; | |
9498 | bp->link_params.req_duplex[idx] = | |
9499 | DUPLEX_HALF; | |
9500 | bp->port.advertising[idx] |= | |
9501 | (ADVERTISED_10baseT_Half | | |
f85582f8 DK |
9502 | ADVERTISED_TP); |
9503 | } else { | |
51c1a580 | 9504 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
9505 | link_config, |
9506 | bp->link_params.speed_cap_mask[idx]); | |
9507 | return; | |
9508 | } | |
9509 | break; | |
a2fbb9ea | 9510 | |
f85582f8 DK |
9511 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
9512 | if (bp->port.supported[idx] & | |
9513 | SUPPORTED_100baseT_Full) { | |
a22f0788 YR |
9514 | bp->link_params.req_line_speed[idx] = |
9515 | SPEED_100; | |
9516 | bp->port.advertising[idx] |= | |
9517 | (ADVERTISED_100baseT_Full | | |
f85582f8 DK |
9518 | ADVERTISED_TP); |
9519 | } else { | |
51c1a580 | 9520 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
9521 | link_config, |
9522 | bp->link_params.speed_cap_mask[idx]); | |
9523 | return; | |
9524 | } | |
9525 | break; | |
a2fbb9ea | 9526 | |
f85582f8 DK |
9527 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
9528 | if (bp->port.supported[idx] & | |
9529 | SUPPORTED_100baseT_Half) { | |
9530 | bp->link_params.req_line_speed[idx] = | |
9531 | SPEED_100; | |
9532 | bp->link_params.req_duplex[idx] = | |
9533 | DUPLEX_HALF; | |
a22f0788 YR |
9534 | bp->port.advertising[idx] |= |
9535 | (ADVERTISED_100baseT_Half | | |
f85582f8 DK |
9536 | ADVERTISED_TP); |
9537 | } else { | |
51c1a580 | 9538 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
9539 | link_config, |
9540 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
9541 | return; |
9542 | } | |
9543 | break; | |
a2fbb9ea | 9544 | |
f85582f8 | 9545 | case PORT_FEATURE_LINK_SPEED_1G: |
a22f0788 YR |
9546 | if (bp->port.supported[idx] & |
9547 | SUPPORTED_1000baseT_Full) { | |
9548 | bp->link_params.req_line_speed[idx] = | |
9549 | SPEED_1000; | |
9550 | bp->port.advertising[idx] |= | |
9551 | (ADVERTISED_1000baseT_Full | | |
f85582f8 DK |
9552 | ADVERTISED_TP); |
9553 | } else { | |
51c1a580 | 9554 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
9555 | link_config, |
9556 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
9557 | return; |
9558 | } | |
9559 | break; | |
a2fbb9ea | 9560 | |
f85582f8 | 9561 | case PORT_FEATURE_LINK_SPEED_2_5G: |
a22f0788 YR |
9562 | if (bp->port.supported[idx] & |
9563 | SUPPORTED_2500baseX_Full) { | |
9564 | bp->link_params.req_line_speed[idx] = | |
9565 | SPEED_2500; | |
9566 | bp->port.advertising[idx] |= | |
9567 | (ADVERTISED_2500baseX_Full | | |
34f80b04 | 9568 | ADVERTISED_TP); |
f85582f8 | 9569 | } else { |
51c1a580 | 9570 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 9571 | link_config, |
f85582f8 DK |
9572 | bp->link_params.speed_cap_mask[idx]); |
9573 | return; | |
9574 | } | |
9575 | break; | |
a2fbb9ea | 9576 | |
f85582f8 | 9577 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
a22f0788 YR |
9578 | if (bp->port.supported[idx] & |
9579 | SUPPORTED_10000baseT_Full) { | |
9580 | bp->link_params.req_line_speed[idx] = | |
9581 | SPEED_10000; | |
9582 | bp->port.advertising[idx] |= | |
9583 | (ADVERTISED_10000baseT_Full | | |
34f80b04 | 9584 | ADVERTISED_FIBRE); |
f85582f8 | 9585 | } else { |
51c1a580 | 9586 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 9587 | link_config, |
f85582f8 DK |
9588 | bp->link_params.speed_cap_mask[idx]); |
9589 | return; | |
9590 | } | |
9591 | break; | |
3c9ada22 YR |
9592 | case PORT_FEATURE_LINK_SPEED_20G: |
9593 | bp->link_params.req_line_speed[idx] = SPEED_20000; | |
a2fbb9ea | 9594 | |
3c9ada22 | 9595 | break; |
f85582f8 | 9596 | default: |
51c1a580 | 9597 | BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", |
754a2f52 | 9598 | link_config); |
f85582f8 DK |
9599 | bp->link_params.req_line_speed[idx] = |
9600 | SPEED_AUTO_NEG; | |
9601 | bp->port.advertising[idx] = | |
9602 | bp->port.supported[idx]; | |
9603 | break; | |
9604 | } | |
a2fbb9ea | 9605 | |
a22f0788 | 9606 | bp->link_params.req_flow_ctrl[idx] = (link_config & |
34f80b04 | 9607 | PORT_FEATURE_FLOW_CONTROL_MASK); |
a22f0788 YR |
9608 | if ((bp->link_params.req_flow_ctrl[idx] == |
9609 | BNX2X_FLOW_CTRL_AUTO) && | |
9610 | !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { | |
9611 | bp->link_params.req_flow_ctrl[idx] = | |
9612 | BNX2X_FLOW_CTRL_NONE; | |
9613 | } | |
a2fbb9ea | 9614 | |
51c1a580 | 9615 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", |
a22f0788 YR |
9616 | bp->link_params.req_line_speed[idx], |
9617 | bp->link_params.req_duplex[idx], | |
9618 | bp->link_params.req_flow_ctrl[idx], | |
9619 | bp->port.advertising[idx]); | |
9620 | } | |
a2fbb9ea ET |
9621 | } |
9622 | ||
e665bfda MC |
9623 | static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) |
9624 | { | |
9625 | mac_hi = cpu_to_be16(mac_hi); | |
9626 | mac_lo = cpu_to_be32(mac_lo); | |
9627 | memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); | |
9628 | memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); | |
9629 | } | |
9630 | ||
34f80b04 | 9631 | static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) |
a2fbb9ea | 9632 | { |
34f80b04 | 9633 | int port = BP_PORT(bp); |
589abe3a | 9634 | u32 config; |
6f38ad93 | 9635 | u32 ext_phy_type, ext_phy_config; |
a2fbb9ea | 9636 | |
c18487ee | 9637 | bp->link_params.bp = bp; |
34f80b04 | 9638 | bp->link_params.port = port; |
c18487ee | 9639 | |
c18487ee | 9640 | bp->link_params.lane_config = |
a2fbb9ea | 9641 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
4d295db0 | 9642 | |
a22f0788 | 9643 | bp->link_params.speed_cap_mask[0] = |
a2fbb9ea ET |
9644 | SHMEM_RD(bp, |
9645 | dev_info.port_hw_config[port].speed_capability_mask); | |
a22f0788 YR |
9646 | bp->link_params.speed_cap_mask[1] = |
9647 | SHMEM_RD(bp, | |
9648 | dev_info.port_hw_config[port].speed_capability_mask2); | |
9649 | bp->port.link_config[0] = | |
a2fbb9ea ET |
9650 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
9651 | ||
a22f0788 YR |
9652 | bp->port.link_config[1] = |
9653 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); | |
c2c8b03e | 9654 | |
a22f0788 YR |
9655 | bp->link_params.multi_phy_config = |
9656 | SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); | |
3ce2c3f9 EG |
9657 | /* If the device is capable of WoL, set the default state according |
9658 | * to the HW | |
9659 | */ | |
4d295db0 | 9660 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); |
3ce2c3f9 EG |
9661 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
9662 | (config & PORT_FEATURE_WOL_ENABLED)); | |
9663 | ||
51c1a580 | 9664 | BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", |
c18487ee | 9665 | bp->link_params.lane_config, |
a22f0788 YR |
9666 | bp->link_params.speed_cap_mask[0], |
9667 | bp->port.link_config[0]); | |
a2fbb9ea | 9668 | |
a22f0788 | 9669 | bp->link_params.switch_cfg = (bp->port.link_config[0] & |
f85582f8 | 9670 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
b7737c9b | 9671 | bnx2x_phy_probe(&bp->link_params); |
c18487ee | 9672 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
a2fbb9ea ET |
9673 | |
9674 | bnx2x_link_settings_requested(bp); | |
9675 | ||
01cd4528 EG |
9676 | /* |
9677 | * If connected directly, work with the internal PHY, otherwise, work | |
9678 | * with the external PHY | |
9679 | */ | |
b7737c9b YR |
9680 | ext_phy_config = |
9681 | SHMEM_RD(bp, | |
9682 | dev_info.port_hw_config[port].external_phy_config); | |
9683 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
01cd4528 | 9684 | if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
b7737c9b | 9685 | bp->mdio.prtad = bp->port.phy_addr; |
01cd4528 EG |
9686 | |
9687 | else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && | |
9688 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
9689 | bp->mdio.prtad = | |
b7737c9b | 9690 | XGXS_EXT_PHY_ADDR(ext_phy_config); |
5866df6d YR |
9691 | |
9692 | /* | |
9693 | * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) | |
9694 | * In MF mode, it is set to cover self test cases | |
9695 | */ | |
9696 | if (IS_MF(bp)) | |
9697 | bp->port.need_hw_lock = 1; | |
9698 | else | |
9699 | bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, | |
9700 | bp->common.shmem_base, | |
9701 | bp->common.shmem2_base); | |
0793f83f | 9702 | } |
01cd4528 | 9703 | |
b306f5ed | 9704 | void bnx2x_get_iscsi_info(struct bnx2x *bp) |
2ba45142 | 9705 | { |
9e62e912 | 9706 | u32 no_flags = NO_ISCSI_FLAG; |
7185bb33 | 9707 | #ifdef BCM_CNIC |
bf61ee14 | 9708 | int port = BP_PORT(bp); |
bf61ee14 | 9709 | |
2ba45142 | 9710 | u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
bf61ee14 | 9711 | drv_lic_key[port].max_iscsi_conn); |
2ba45142 | 9712 | |
b306f5ed | 9713 | /* Get the number of maximum allowed iSCSI connections */ |
2ba45142 VZ |
9714 | bp->cnic_eth_dev.max_iscsi_conn = |
9715 | (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> | |
9716 | BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; | |
9717 | ||
b306f5ed DK |
9718 | BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", |
9719 | bp->cnic_eth_dev.max_iscsi_conn); | |
9720 | ||
9721 | /* | |
9722 | * If maximum allowed number of connections is zero - | |
9723 | * disable the feature. | |
9724 | */ | |
9725 | if (!bp->cnic_eth_dev.max_iscsi_conn) | |
9e62e912 | 9726 | bp->flags |= no_flags; |
7185bb33 | 9727 | #else |
9e62e912 | 9728 | bp->flags |= no_flags; |
7185bb33 | 9729 | #endif |
b306f5ed DK |
9730 | } |
9731 | ||
9e62e912 DK |
9732 | #ifdef BCM_CNIC |
9733 | static void __devinit bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) | |
9734 | { | |
9735 | /* Port info */ | |
9736 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
9737 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); | |
9738 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
9739 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); | |
9740 | ||
9741 | /* Node info */ | |
9742 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
9743 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); | |
9744 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
9745 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); | |
9746 | } | |
9747 | #endif | |
b306f5ed DK |
9748 | static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp) |
9749 | { | |
7185bb33 | 9750 | #ifdef BCM_CNIC |
b306f5ed DK |
9751 | int port = BP_PORT(bp); |
9752 | int func = BP_ABS_FUNC(bp); | |
9753 | ||
9754 | u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, | |
9755 | drv_lic_key[port].max_fcoe_conn); | |
9756 | ||
9757 | /* Get the number of maximum allowed FCoE connections */ | |
2ba45142 VZ |
9758 | bp->cnic_eth_dev.max_fcoe_conn = |
9759 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> | |
9760 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; | |
9761 | ||
bf61ee14 VZ |
9762 | /* Read the WWN: */ |
9763 | if (!IS_MF(bp)) { | |
9764 | /* Port info */ | |
9765 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
9766 | SHMEM_RD(bp, | |
9767 | dev_info.port_hw_config[port]. | |
9768 | fcoe_wwn_port_name_upper); | |
9769 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
9770 | SHMEM_RD(bp, | |
9771 | dev_info.port_hw_config[port]. | |
9772 | fcoe_wwn_port_name_lower); | |
9773 | ||
9774 | /* Node info */ | |
9775 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
9776 | SHMEM_RD(bp, | |
9777 | dev_info.port_hw_config[port]. | |
9778 | fcoe_wwn_node_name_upper); | |
9779 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
9780 | SHMEM_RD(bp, | |
9781 | dev_info.port_hw_config[port]. | |
9782 | fcoe_wwn_node_name_lower); | |
9783 | } else if (!IS_MF_SD(bp)) { | |
9784 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); | |
9785 | ||
9786 | /* | |
9787 | * Read the WWN info only if the FCoE feature is enabled for | |
9788 | * this function. | |
9789 | */ | |
9e62e912 DK |
9790 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) |
9791 | bnx2x_get_ext_wwn_info(bp, func); | |
9792 | ||
9793 | } else if (IS_MF_FCOE_SD(bp)) | |
9794 | bnx2x_get_ext_wwn_info(bp, func); | |
bf61ee14 | 9795 | |
b306f5ed | 9796 | BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); |
2ba45142 | 9797 | |
bf61ee14 VZ |
9798 | /* |
9799 | * If maximum allowed number of connections is zero - | |
2ba45142 VZ |
9800 | * disable the feature. |
9801 | */ | |
2ba45142 VZ |
9802 | if (!bp->cnic_eth_dev.max_fcoe_conn) |
9803 | bp->flags |= NO_FCOE_FLAG; | |
7185bb33 DK |
9804 | #else |
9805 | bp->flags |= NO_FCOE_FLAG; | |
9806 | #endif | |
2ba45142 | 9807 | } |
b306f5ed DK |
9808 | |
9809 | static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) | |
9810 | { | |
9811 | /* | |
9812 | * iSCSI may be dynamically disabled but reading | |
9813 | * info here we will decrease memory usage by driver | |
9814 | * if the feature is disabled for good | |
9815 | */ | |
9816 | bnx2x_get_iscsi_info(bp); | |
9817 | bnx2x_get_fcoe_info(bp); | |
9818 | } | |
2ba45142 | 9819 | |
0793f83f DK |
9820 | static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) |
9821 | { | |
9822 | u32 val, val2; | |
9823 | int func = BP_ABS_FUNC(bp); | |
9824 | int port = BP_PORT(bp); | |
2ba45142 VZ |
9825 | #ifdef BCM_CNIC |
9826 | u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; | |
9827 | u8 *fip_mac = bp->fip_mac; | |
9828 | #endif | |
0793f83f | 9829 | |
619c5cb6 VZ |
9830 | /* Zero primary MAC configuration */ |
9831 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
9832 | ||
0793f83f DK |
9833 | if (BP_NOMCP(bp)) { |
9834 | BNX2X_ERROR("warning: random MAC workaround active\n"); | |
7ce5d222 | 9835 | eth_hw_addr_random(bp->dev); |
0793f83f DK |
9836 | } else if (IS_MF(bp)) { |
9837 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
9838 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); | |
9839 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && | |
9840 | (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) | |
9841 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
37b091ba MC |
9842 | |
9843 | #ifdef BCM_CNIC | |
614c76df DK |
9844 | /* |
9845 | * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or | |
2ba45142 | 9846 | * FCoE MAC then the appropriate feature should be disabled. |
9e62e912 DK |
9847 | * |
9848 | * In non SD mode features configuration comes from | |
9849 | * struct func_ext_config. | |
2ba45142 | 9850 | */ |
9e62e912 | 9851 | if (!IS_MF_SD(bp)) { |
0793f83f DK |
9852 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); |
9853 | if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { | |
9854 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
9855 | iscsi_mac_addr_upper); | |
9856 | val = MF_CFG_RD(bp, func_ext_config[func]. | |
9857 | iscsi_mac_addr_lower); | |
2ba45142 | 9858 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
0f9dad10 JP |
9859 | BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", |
9860 | iscsi_mac); | |
2ba45142 VZ |
9861 | } else |
9862 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; | |
9863 | ||
9864 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
9865 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
9866 | fcoe_mac_addr_upper); | |
9867 | val = MF_CFG_RD(bp, func_ext_config[func]. | |
9868 | fcoe_mac_addr_lower); | |
2ba45142 | 9869 | bnx2x_set_mac_buf(fip_mac, val, val2); |
614c76df | 9870 | BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n", |
0f9dad10 | 9871 | fip_mac); |
2ba45142 | 9872 | |
2ba45142 VZ |
9873 | } else |
9874 | bp->flags |= NO_FCOE_FLAG; | |
9e62e912 DK |
9875 | } else { /* SD MODE */ |
9876 | if (IS_MF_STORAGE_SD(bp)) { | |
9877 | if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { | |
9878 | /* use primary mac as iscsi mac */ | |
9879 | memcpy(iscsi_mac, bp->dev->dev_addr, | |
9880 | ETH_ALEN); | |
9881 | ||
9882 | BNX2X_DEV_INFO("SD ISCSI MODE\n"); | |
9883 | BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", | |
9884 | iscsi_mac); | |
9885 | } else { /* FCoE */ | |
9886 | memcpy(fip_mac, bp->dev->dev_addr, | |
9887 | ETH_ALEN); | |
9888 | BNX2X_DEV_INFO("SD FCoE MODE\n"); | |
9889 | BNX2X_DEV_INFO("Read FIP MAC: %pM\n", | |
9890 | fip_mac); | |
9891 | } | |
614c76df DK |
9892 | /* Zero primary MAC configuration */ |
9893 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
614c76df | 9894 | } |
0793f83f | 9895 | } |
37b091ba | 9896 | #endif |
0793f83f DK |
9897 | } else { |
9898 | /* in SF read MACs from port configuration */ | |
9899 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
9900 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
9901 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
9902 | ||
9903 | #ifdef BCM_CNIC | |
9904 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
9905 | iscsi_mac_upper); | |
9906 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
9907 | iscsi_mac_lower); | |
2ba45142 | 9908 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
c03bd39c VZ |
9909 | |
9910 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
9911 | fcoe_fip_mac_upper); | |
9912 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
9913 | fcoe_fip_mac_lower); | |
9914 | bnx2x_set_mac_buf(fip_mac, val, val2); | |
0793f83f DK |
9915 | #endif |
9916 | } | |
9917 | ||
9918 | memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); | |
9919 | memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); | |
9920 | ||
ec6ba945 | 9921 | #ifdef BCM_CNIC |
426b9241 DK |
9922 | /* Disable iSCSI if MAC configuration is |
9923 | * invalid. | |
9924 | */ | |
9925 | if (!is_valid_ether_addr(iscsi_mac)) { | |
9926 | bp->flags |= NO_ISCSI_FLAG; | |
9927 | memset(iscsi_mac, 0, ETH_ALEN); | |
9928 | } | |
9929 | ||
9930 | /* Disable FCoE if MAC configuration is | |
9931 | * invalid. | |
9932 | */ | |
9933 | if (!is_valid_ether_addr(fip_mac)) { | |
9934 | bp->flags |= NO_FCOE_FLAG; | |
9935 | memset(bp->fip_mac, 0, ETH_ALEN); | |
9936 | } | |
ec6ba945 | 9937 | #endif |
619c5cb6 | 9938 | |
614c76df | 9939 | if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) |
619c5cb6 | 9940 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
9941 | "bad Ethernet MAC address configuration: %pM\n" |
9942 | "change it manually before bringing up the appropriate network interface\n", | |
0f9dad10 | 9943 | bp->dev->dev_addr); |
51c1a580 MS |
9944 | |
9945 | ||
34f80b04 EG |
9946 | } |
9947 | ||
9948 | static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) | |
9949 | { | |
0793f83f | 9950 | int /*abs*/func = BP_ABS_FUNC(bp); |
b8ee8328 | 9951 | int vn; |
0793f83f | 9952 | u32 val = 0; |
34f80b04 | 9953 | int rc = 0; |
a2fbb9ea | 9954 | |
34f80b04 | 9955 | bnx2x_get_common_hwinfo(bp); |
a2fbb9ea | 9956 | |
6383c0b3 AE |
9957 | /* |
9958 | * initialize IGU parameters | |
9959 | */ | |
f2e0899f DK |
9960 | if (CHIP_IS_E1x(bp)) { |
9961 | bp->common.int_block = INT_BLOCK_HC; | |
9962 | ||
9963 | bp->igu_dsb_id = DEF_SB_IGU_ID; | |
9964 | bp->igu_base_sb = 0; | |
f2e0899f DK |
9965 | } else { |
9966 | bp->common.int_block = INT_BLOCK_IGU; | |
7a06a122 DK |
9967 | |
9968 | /* do not allow device reset during IGU info preocessing */ | |
9969 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); | |
9970 | ||
f2e0899f | 9971 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
619c5cb6 VZ |
9972 | |
9973 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { | |
9974 | int tout = 5000; | |
9975 | ||
9976 | BNX2X_DEV_INFO("FORCING Normal Mode\n"); | |
9977 | ||
9978 | val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); | |
9979 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); | |
9980 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); | |
9981 | ||
9982 | while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
9983 | tout--; | |
9984 | usleep_range(1000, 1000); | |
9985 | } | |
9986 | ||
9987 | if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
9988 | dev_err(&bp->pdev->dev, | |
9989 | "FORCING Normal Mode failed!!!\n"); | |
9990 | return -EPERM; | |
9991 | } | |
9992 | } | |
9993 | ||
f2e0899f | 9994 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
619c5cb6 | 9995 | BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); |
f2e0899f DK |
9996 | bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; |
9997 | } else | |
619c5cb6 | 9998 | BNX2X_DEV_INFO("IGU Normal Mode\n"); |
523224a3 | 9999 | |
f2e0899f DK |
10000 | bnx2x_get_igu_cam_info(bp); |
10001 | ||
7a06a122 | 10002 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
f2e0899f | 10003 | } |
619c5cb6 VZ |
10004 | |
10005 | /* | |
10006 | * set base FW non-default (fast path) status block id, this value is | |
10007 | * used to initialize the fw_sb_id saved on the fp/queue structure to | |
10008 | * determine the id used by the FW. | |
10009 | */ | |
10010 | if (CHIP_IS_E1x(bp)) | |
10011 | bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); | |
10012 | else /* | |
10013 | * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of | |
10014 | * the same queue are indicated on the same IGU SB). So we prefer | |
10015 | * FW and IGU SBs to be the same value. | |
10016 | */ | |
10017 | bp->base_fw_ndsb = bp->igu_base_sb; | |
10018 | ||
10019 | BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" | |
10020 | "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, | |
10021 | bp->igu_sb_cnt, bp->base_fw_ndsb); | |
f2e0899f DK |
10022 | |
10023 | /* | |
10024 | * Initialize MF configuration | |
10025 | */ | |
523224a3 | 10026 | |
fb3bff17 DK |
10027 | bp->mf_ov = 0; |
10028 | bp->mf_mode = 0; | |
3395a033 | 10029 | vn = BP_VN(bp); |
0793f83f | 10030 | |
f2e0899f | 10031 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
619c5cb6 VZ |
10032 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
10033 | bp->common.shmem2_base, SHMEM2_RD(bp, size), | |
10034 | (u32)offsetof(struct shmem2_region, mf_cfg_addr)); | |
10035 | ||
f2e0899f DK |
10036 | if (SHMEM2_HAS(bp, mf_cfg_addr)) |
10037 | bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); | |
10038 | else | |
10039 | bp->common.mf_cfg_base = bp->common.shmem_base + | |
523224a3 DK |
10040 | offsetof(struct shmem_region, func_mb) + |
10041 | E1H_FUNC_MAX * sizeof(struct drv_func_mb); | |
0793f83f DK |
10042 | /* |
10043 | * get mf configuration: | |
25985edc | 10044 | * 1. existence of MF configuration |
0793f83f DK |
10045 | * 2. MAC address must be legal (check only upper bytes) |
10046 | * for Switch-Independent mode; | |
10047 | * OVLAN must be legal for Switch-Dependent mode | |
10048 | * 3. SF_MODE configures specific MF mode | |
10049 | */ | |
10050 | if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
10051 | /* get mf configuration */ | |
10052 | val = SHMEM_RD(bp, | |
10053 | dev_info.shared_feature_config.config); | |
10054 | val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; | |
10055 | ||
10056 | switch (val) { | |
10057 | case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: | |
10058 | val = MF_CFG_RD(bp, func_mf_config[func]. | |
10059 | mac_upper); | |
10060 | /* check for legal mac (upper bytes)*/ | |
10061 | if (val != 0xffff) { | |
10062 | bp->mf_mode = MULTI_FUNCTION_SI; | |
10063 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
10064 | func_mf_config[func].config); | |
10065 | } else | |
51c1a580 | 10066 | BNX2X_DEV_INFO("illegal MAC address for SI\n"); |
0793f83f DK |
10067 | break; |
10068 | case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: | |
10069 | /* get OV configuration */ | |
10070 | val = MF_CFG_RD(bp, | |
10071 | func_mf_config[FUNC_0].e1hov_tag); | |
10072 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; | |
10073 | ||
10074 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
10075 | bp->mf_mode = MULTI_FUNCTION_SD; | |
10076 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
10077 | func_mf_config[func].config); | |
10078 | } else | |
754a2f52 | 10079 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
0793f83f DK |
10080 | break; |
10081 | default: | |
10082 | /* Unknown configuration: reset mf_config */ | |
10083 | bp->mf_config[vn] = 0; | |
51c1a580 | 10084 | BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); |
0793f83f DK |
10085 | } |
10086 | } | |
a2fbb9ea | 10087 | |
2691d51d | 10088 | BNX2X_DEV_INFO("%s function mode\n", |
fb3bff17 | 10089 | IS_MF(bp) ? "multi" : "single"); |
2691d51d | 10090 | |
0793f83f DK |
10091 | switch (bp->mf_mode) { |
10092 | case MULTI_FUNCTION_SD: | |
10093 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
10094 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2691d51d | 10095 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
fb3bff17 | 10096 | bp->mf_ov = val; |
619c5cb6 VZ |
10097 | bp->path_has_ovlan = true; |
10098 | ||
51c1a580 MS |
10099 | BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", |
10100 | func, bp->mf_ov, bp->mf_ov); | |
2691d51d | 10101 | } else { |
619c5cb6 | 10102 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
10103 | "No valid MF OV for func %d, aborting\n", |
10104 | func); | |
619c5cb6 | 10105 | return -EPERM; |
34f80b04 | 10106 | } |
0793f83f DK |
10107 | break; |
10108 | case MULTI_FUNCTION_SI: | |
51c1a580 MS |
10109 | BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", |
10110 | func); | |
0793f83f DK |
10111 | break; |
10112 | default: | |
10113 | if (vn) { | |
619c5cb6 | 10114 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
10115 | "VN %d is in a single function mode, aborting\n", |
10116 | vn); | |
619c5cb6 | 10117 | return -EPERM; |
2691d51d | 10118 | } |
0793f83f | 10119 | break; |
34f80b04 | 10120 | } |
0793f83f | 10121 | |
619c5cb6 VZ |
10122 | /* check if other port on the path needs ovlan: |
10123 | * Since MF configuration is shared between ports | |
10124 | * Possible mixed modes are only | |
10125 | * {SF, SI} {SF, SD} {SD, SF} {SI, SF} | |
10126 | */ | |
10127 | if (CHIP_MODE_IS_4_PORT(bp) && | |
10128 | !bp->path_has_ovlan && | |
10129 | !IS_MF(bp) && | |
10130 | bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
10131 | u8 other_port = !BP_PORT(bp); | |
10132 | u8 other_func = BP_PATH(bp) + 2*other_port; | |
10133 | val = MF_CFG_RD(bp, | |
10134 | func_mf_config[other_func].e1hov_tag); | |
10135 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) | |
10136 | bp->path_has_ovlan = true; | |
10137 | } | |
34f80b04 | 10138 | } |
a2fbb9ea | 10139 | |
f2e0899f DK |
10140 | /* adjust igu_sb_cnt to MF for E1x */ |
10141 | if (CHIP_IS_E1x(bp) && IS_MF(bp)) | |
523224a3 DK |
10142 | bp->igu_sb_cnt /= E1HVN_MAX; |
10143 | ||
619c5cb6 VZ |
10144 | /* port info */ |
10145 | bnx2x_get_port_hwinfo(bp); | |
f2e0899f | 10146 | |
0793f83f DK |
10147 | /* Get MAC addresses */ |
10148 | bnx2x_get_mac_hwinfo(bp); | |
a2fbb9ea | 10149 | |
2ba45142 | 10150 | bnx2x_get_cnic_info(bp); |
2ba45142 | 10151 | |
34f80b04 EG |
10152 | return rc; |
10153 | } | |
10154 | ||
34f24c7f VZ |
10155 | static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) |
10156 | { | |
10157 | int cnt, i, block_end, rodi; | |
fcdf95cb | 10158 | char vpd_start[BNX2X_VPD_LEN+1]; |
34f24c7f VZ |
10159 | char str_id_reg[VENDOR_ID_LEN+1]; |
10160 | char str_id_cap[VENDOR_ID_LEN+1]; | |
fcdf95cb BW |
10161 | char *vpd_data; |
10162 | char *vpd_extended_data = NULL; | |
34f24c7f VZ |
10163 | u8 len; |
10164 | ||
fcdf95cb | 10165 | cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); |
34f24c7f VZ |
10166 | memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); |
10167 | ||
10168 | if (cnt < BNX2X_VPD_LEN) | |
10169 | goto out_not_found; | |
10170 | ||
fcdf95cb BW |
10171 | /* VPD RO tag should be first tag after identifier string, hence |
10172 | * we should be able to find it in first BNX2X_VPD_LEN chars | |
10173 | */ | |
10174 | i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, | |
34f24c7f VZ |
10175 | PCI_VPD_LRDT_RO_DATA); |
10176 | if (i < 0) | |
10177 | goto out_not_found; | |
10178 | ||
34f24c7f | 10179 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + |
fcdf95cb | 10180 | pci_vpd_lrdt_size(&vpd_start[i]); |
34f24c7f VZ |
10181 | |
10182 | i += PCI_VPD_LRDT_TAG_SIZE; | |
10183 | ||
fcdf95cb BW |
10184 | if (block_end > BNX2X_VPD_LEN) { |
10185 | vpd_extended_data = kmalloc(block_end, GFP_KERNEL); | |
10186 | if (vpd_extended_data == NULL) | |
10187 | goto out_not_found; | |
10188 | ||
10189 | /* read rest of vpd image into vpd_extended_data */ | |
10190 | memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); | |
10191 | cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, | |
10192 | block_end - BNX2X_VPD_LEN, | |
10193 | vpd_extended_data + BNX2X_VPD_LEN); | |
10194 | if (cnt < (block_end - BNX2X_VPD_LEN)) | |
10195 | goto out_not_found; | |
10196 | vpd_data = vpd_extended_data; | |
10197 | } else | |
10198 | vpd_data = vpd_start; | |
10199 | ||
10200 | /* now vpd_data holds full vpd content in both cases */ | |
34f24c7f VZ |
10201 | |
10202 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
10203 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
10204 | if (rodi < 0) | |
10205 | goto out_not_found; | |
10206 | ||
10207 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
10208 | ||
10209 | if (len != VENDOR_ID_LEN) | |
10210 | goto out_not_found; | |
10211 | ||
10212 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
10213 | ||
10214 | /* vendor specific info */ | |
10215 | snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); | |
10216 | snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); | |
10217 | if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || | |
10218 | !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { | |
10219 | ||
10220 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
10221 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
10222 | if (rodi >= 0) { | |
10223 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
10224 | ||
10225 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
10226 | ||
10227 | if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { | |
10228 | memcpy(bp->fw_ver, &vpd_data[rodi], len); | |
10229 | bp->fw_ver[len] = ' '; | |
10230 | } | |
10231 | } | |
fcdf95cb | 10232 | kfree(vpd_extended_data); |
34f24c7f VZ |
10233 | return; |
10234 | } | |
10235 | out_not_found: | |
fcdf95cb | 10236 | kfree(vpd_extended_data); |
34f24c7f VZ |
10237 | return; |
10238 | } | |
10239 | ||
619c5cb6 VZ |
10240 | static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) |
10241 | { | |
10242 | u32 flags = 0; | |
10243 | ||
10244 | if (CHIP_REV_IS_FPGA(bp)) | |
10245 | SET_FLAGS(flags, MODE_FPGA); | |
10246 | else if (CHIP_REV_IS_EMUL(bp)) | |
10247 | SET_FLAGS(flags, MODE_EMUL); | |
10248 | else | |
10249 | SET_FLAGS(flags, MODE_ASIC); | |
10250 | ||
10251 | if (CHIP_MODE_IS_4_PORT(bp)) | |
10252 | SET_FLAGS(flags, MODE_PORT4); | |
10253 | else | |
10254 | SET_FLAGS(flags, MODE_PORT2); | |
10255 | ||
10256 | if (CHIP_IS_E2(bp)) | |
10257 | SET_FLAGS(flags, MODE_E2); | |
10258 | else if (CHIP_IS_E3(bp)) { | |
10259 | SET_FLAGS(flags, MODE_E3); | |
10260 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
10261 | SET_FLAGS(flags, MODE_E3_A0); | |
6383c0b3 AE |
10262 | else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ |
10263 | SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); | |
619c5cb6 VZ |
10264 | } |
10265 | ||
10266 | if (IS_MF(bp)) { | |
10267 | SET_FLAGS(flags, MODE_MF); | |
10268 | switch (bp->mf_mode) { | |
10269 | case MULTI_FUNCTION_SD: | |
10270 | SET_FLAGS(flags, MODE_MF_SD); | |
10271 | break; | |
10272 | case MULTI_FUNCTION_SI: | |
10273 | SET_FLAGS(flags, MODE_MF_SI); | |
10274 | break; | |
10275 | } | |
10276 | } else | |
10277 | SET_FLAGS(flags, MODE_SF); | |
10278 | ||
10279 | #if defined(__LITTLE_ENDIAN) | |
10280 | SET_FLAGS(flags, MODE_LITTLE_ENDIAN); | |
10281 | #else /*(__BIG_ENDIAN)*/ | |
10282 | SET_FLAGS(flags, MODE_BIG_ENDIAN); | |
10283 | #endif | |
10284 | INIT_MODE_FLAGS(bp) = flags; | |
10285 | } | |
10286 | ||
34f80b04 EG |
10287 | static int __devinit bnx2x_init_bp(struct bnx2x *bp) |
10288 | { | |
f2e0899f | 10289 | int func; |
34f80b04 EG |
10290 | int rc; |
10291 | ||
34f80b04 | 10292 | mutex_init(&bp->port.phy_mutex); |
c4ff7cbf | 10293 | mutex_init(&bp->fw_mb_mutex); |
bb7e95c8 | 10294 | spin_lock_init(&bp->stats_lock); |
993ac7b5 MC |
10295 | #ifdef BCM_CNIC |
10296 | mutex_init(&bp->cnic_mutex); | |
10297 | #endif | |
a2fbb9ea | 10298 | |
1cf167f2 | 10299 | INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); |
7be08a72 | 10300 | INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); |
3deb8167 | 10301 | INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); |
34f80b04 | 10302 | rc = bnx2x_get_hwinfo(bp); |
619c5cb6 VZ |
10303 | if (rc) |
10304 | return rc; | |
34f80b04 | 10305 | |
619c5cb6 VZ |
10306 | bnx2x_set_modes_bitmap(bp); |
10307 | ||
10308 | rc = bnx2x_alloc_mem_bp(bp); | |
10309 | if (rc) | |
10310 | return rc; | |
523224a3 | 10311 | |
34f24c7f | 10312 | bnx2x_read_fwinfo(bp); |
f2e0899f DK |
10313 | |
10314 | func = BP_FUNC(bp); | |
10315 | ||
34f80b04 | 10316 | /* need to reset chip if undi was active */ |
452427b0 YM |
10317 | if (!BP_NOMCP(bp)) { |
10318 | /* init fw_seq */ | |
10319 | bp->fw_seq = | |
10320 | SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
10321 | DRV_MSG_SEQ_NUMBER_MASK; | |
10322 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | |
10323 | ||
10324 | bnx2x_prev_unload(bp); | |
10325 | } | |
10326 | ||
34f80b04 EG |
10327 | |
10328 | if (CHIP_REV_IS_FPGA(bp)) | |
cdaa7cb8 | 10329 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
34f80b04 EG |
10330 | |
10331 | if (BP_NOMCP(bp) && (func == 0)) | |
51c1a580 | 10332 | dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); |
34f80b04 | 10333 | |
555f6c78 | 10334 | bp->multi_mode = multi_mode; |
555f6c78 | 10335 | |
614c76df DK |
10336 | bp->disable_tpa = disable_tpa; |
10337 | ||
10338 | #ifdef BCM_CNIC | |
9e62e912 | 10339 | bp->disable_tpa |= IS_MF_STORAGE_SD(bp); |
614c76df DK |
10340 | #endif |
10341 | ||
7a9b2557 | 10342 | /* Set TPA flags */ |
614c76df | 10343 | if (bp->disable_tpa) { |
621b4d66 | 10344 | bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
7a9b2557 VZ |
10345 | bp->dev->features &= ~NETIF_F_LRO; |
10346 | } else { | |
621b4d66 | 10347 | bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
7a9b2557 VZ |
10348 | bp->dev->features |= NETIF_F_LRO; |
10349 | } | |
10350 | ||
a18f5128 EG |
10351 | if (CHIP_IS_E1(bp)) |
10352 | bp->dropless_fc = 0; | |
10353 | else | |
10354 | bp->dropless_fc = dropless_fc; | |
10355 | ||
8d5726c4 | 10356 | bp->mrrs = mrrs; |
7a9b2557 | 10357 | |
34f80b04 | 10358 | bp->tx_ring_size = MAX_TX_AVAIL; |
34f80b04 | 10359 | |
7d323bfd | 10360 | /* make sure that the numbers are in the right granularity */ |
523224a3 DK |
10361 | bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; |
10362 | bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; | |
34f80b04 | 10363 | |
fc543637 | 10364 | bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; |
34f80b04 EG |
10365 | |
10366 | init_timer(&bp->timer); | |
10367 | bp->timer.expires = jiffies + bp->current_interval; | |
10368 | bp->timer.data = (unsigned long) bp; | |
10369 | bp->timer.function = bnx2x_timer; | |
10370 | ||
785b9b1a | 10371 | bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); |
e4901dde VZ |
10372 | bnx2x_dcbx_init_params(bp); |
10373 | ||
619c5cb6 VZ |
10374 | #ifdef BCM_CNIC |
10375 | if (CHIP_IS_E1x(bp)) | |
10376 | bp->cnic_base_cl_id = FP_SB_MAX_E1x; | |
10377 | else | |
10378 | bp->cnic_base_cl_id = FP_SB_MAX_E2; | |
10379 | #endif | |
10380 | ||
6383c0b3 AE |
10381 | /* multiple tx priority */ |
10382 | if (CHIP_IS_E1x(bp)) | |
10383 | bp->max_cos = BNX2X_MULTI_TX_COS_E1X; | |
10384 | if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) | |
10385 | bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; | |
10386 | if (CHIP_IS_E3B0(bp)) | |
10387 | bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; | |
10388 | ||
fe603b4d DK |
10389 | bp->gro_check = bnx2x_need_gro_check(bp->dev->mtu); |
10390 | ||
34f80b04 | 10391 | return rc; |
a2fbb9ea ET |
10392 | } |
10393 | ||
a2fbb9ea | 10394 | |
de0c62db DK |
10395 | /**************************************************************************** |
10396 | * General service functions | |
10397 | ****************************************************************************/ | |
a2fbb9ea | 10398 | |
619c5cb6 VZ |
10399 | /* |
10400 | * net_device service functions | |
10401 | */ | |
10402 | ||
bb2a0f7a | 10403 | /* called with rtnl_lock */ |
a2fbb9ea ET |
10404 | static int bnx2x_open(struct net_device *dev) |
10405 | { | |
10406 | struct bnx2x *bp = netdev_priv(dev); | |
c9ee9206 VZ |
10407 | bool global = false; |
10408 | int other_engine = BP_PATH(bp) ? 0 : 1; | |
889b9af3 | 10409 | bool other_load_status, load_status; |
a2fbb9ea | 10410 | |
1355b704 MY |
10411 | bp->stats_init = true; |
10412 | ||
6eccabb3 EG |
10413 | netif_carrier_off(dev); |
10414 | ||
a2fbb9ea ET |
10415 | bnx2x_set_power_state(bp, PCI_D0); |
10416 | ||
889b9af3 AE |
10417 | other_load_status = bnx2x_get_load_status(bp, other_engine); |
10418 | load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); | |
c9ee9206 VZ |
10419 | |
10420 | /* | |
10421 | * If parity had happen during the unload, then attentions | |
10422 | * and/or RECOVERY_IN_PROGRES may still be set. In this case we | |
10423 | * want the first function loaded on the current engine to | |
10424 | * complete the recovery. | |
10425 | */ | |
10426 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || | |
10427 | bnx2x_chk_parity_attn(bp, &global, true)) | |
72fd0718 | 10428 | do { |
c9ee9206 VZ |
10429 | /* |
10430 | * If there are attentions and they are in a global | |
10431 | * blocks, set the GLOBAL_RESET bit regardless whether | |
10432 | * it will be this function that will complete the | |
10433 | * recovery or not. | |
72fd0718 | 10434 | */ |
c9ee9206 VZ |
10435 | if (global) |
10436 | bnx2x_set_reset_global(bp); | |
72fd0718 | 10437 | |
c9ee9206 VZ |
10438 | /* |
10439 | * Only the first function on the current engine should | |
10440 | * try to recover in open. In case of attentions in | |
10441 | * global blocks only the first in the chip should try | |
10442 | * to recover. | |
72fd0718 | 10443 | */ |
889b9af3 AE |
10444 | if ((!load_status && |
10445 | (!global || !other_load_status)) && | |
c9ee9206 VZ |
10446 | bnx2x_trylock_leader_lock(bp) && |
10447 | !bnx2x_leader_reset(bp)) { | |
10448 | netdev_info(bp->dev, "Recovered in open\n"); | |
72fd0718 VZ |
10449 | break; |
10450 | } | |
10451 | ||
c9ee9206 | 10452 | /* recovery has failed... */ |
72fd0718 | 10453 | bnx2x_set_power_state(bp, PCI_D3hot); |
c9ee9206 | 10454 | bp->recovery_state = BNX2X_RECOVERY_FAILED; |
72fd0718 | 10455 | |
51c1a580 MS |
10456 | BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" |
10457 | "If you still see this message after a few retries then power cycle is required.\n"); | |
72fd0718 VZ |
10458 | |
10459 | return -EAGAIN; | |
10460 | } while (0); | |
72fd0718 VZ |
10461 | |
10462 | bp->recovery_state = BNX2X_RECOVERY_DONE; | |
bb2a0f7a | 10463 | return bnx2x_nic_load(bp, LOAD_OPEN); |
a2fbb9ea ET |
10464 | } |
10465 | ||
bb2a0f7a | 10466 | /* called with rtnl_lock */ |
56ad3152 | 10467 | static int bnx2x_close(struct net_device *dev) |
a2fbb9ea | 10468 | { |
a2fbb9ea ET |
10469 | struct bnx2x *bp = netdev_priv(dev); |
10470 | ||
10471 | /* Unload the driver, release IRQs */ | |
bb2a0f7a | 10472 | bnx2x_nic_unload(bp, UNLOAD_CLOSE); |
c9ee9206 VZ |
10473 | |
10474 | /* Power off */ | |
d3dbfee0 | 10475 | bnx2x_set_power_state(bp, PCI_D3hot); |
a2fbb9ea ET |
10476 | |
10477 | return 0; | |
10478 | } | |
10479 | ||
619c5cb6 VZ |
10480 | static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, |
10481 | struct bnx2x_mcast_ramrod_params *p) | |
6e30dd4e | 10482 | { |
619c5cb6 VZ |
10483 | int mc_count = netdev_mc_count(bp->dev); |
10484 | struct bnx2x_mcast_list_elem *mc_mac = | |
10485 | kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); | |
10486 | struct netdev_hw_addr *ha; | |
6e30dd4e | 10487 | |
619c5cb6 VZ |
10488 | if (!mc_mac) |
10489 | return -ENOMEM; | |
6e30dd4e | 10490 | |
619c5cb6 | 10491 | INIT_LIST_HEAD(&p->mcast_list); |
6e30dd4e | 10492 | |
619c5cb6 VZ |
10493 | netdev_for_each_mc_addr(ha, bp->dev) { |
10494 | mc_mac->mac = bnx2x_mc_addr(ha); | |
10495 | list_add_tail(&mc_mac->link, &p->mcast_list); | |
10496 | mc_mac++; | |
6e30dd4e | 10497 | } |
619c5cb6 VZ |
10498 | |
10499 | p->mcast_list_len = mc_count; | |
10500 | ||
10501 | return 0; | |
6e30dd4e VZ |
10502 | } |
10503 | ||
619c5cb6 VZ |
10504 | static inline void bnx2x_free_mcast_macs_list( |
10505 | struct bnx2x_mcast_ramrod_params *p) | |
10506 | { | |
10507 | struct bnx2x_mcast_list_elem *mc_mac = | |
10508 | list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, | |
10509 | link); | |
10510 | ||
10511 | WARN_ON(!mc_mac); | |
10512 | kfree(mc_mac); | |
10513 | } | |
10514 | ||
10515 | /** | |
10516 | * bnx2x_set_uc_list - configure a new unicast MACs list. | |
10517 | * | |
10518 | * @bp: driver handle | |
6e30dd4e | 10519 | * |
619c5cb6 | 10520 | * We will use zero (0) as a MAC type for these MACs. |
6e30dd4e | 10521 | */ |
619c5cb6 | 10522 | static inline int bnx2x_set_uc_list(struct bnx2x *bp) |
6e30dd4e | 10523 | { |
619c5cb6 | 10524 | int rc; |
6e30dd4e | 10525 | struct net_device *dev = bp->dev; |
6e30dd4e | 10526 | struct netdev_hw_addr *ha; |
619c5cb6 VZ |
10527 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; |
10528 | unsigned long ramrod_flags = 0; | |
6e30dd4e | 10529 | |
619c5cb6 VZ |
10530 | /* First schedule a cleanup up of old configuration */ |
10531 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); | |
10532 | if (rc < 0) { | |
10533 | BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); | |
10534 | return rc; | |
10535 | } | |
6e30dd4e VZ |
10536 | |
10537 | netdev_for_each_uc_addr(ha, dev) { | |
619c5cb6 VZ |
10538 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
10539 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
10540 | if (rc < 0) { | |
10541 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", | |
10542 | rc); | |
10543 | return rc; | |
6e30dd4e VZ |
10544 | } |
10545 | } | |
10546 | ||
619c5cb6 VZ |
10547 | /* Execute the pending commands */ |
10548 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
10549 | return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, | |
10550 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
6e30dd4e VZ |
10551 | } |
10552 | ||
619c5cb6 | 10553 | static inline int bnx2x_set_mc_list(struct bnx2x *bp) |
6e30dd4e | 10554 | { |
619c5cb6 | 10555 | struct net_device *dev = bp->dev; |
3b603066 | 10556 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 | 10557 | int rc = 0; |
6e30dd4e | 10558 | |
619c5cb6 | 10559 | rparam.mcast_obj = &bp->mcast_obj; |
6e30dd4e | 10560 | |
619c5cb6 VZ |
10561 | /* first, clear all configured multicast MACs */ |
10562 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
10563 | if (rc < 0) { | |
51c1a580 | 10564 | BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); |
619c5cb6 VZ |
10565 | return rc; |
10566 | } | |
6e30dd4e | 10567 | |
619c5cb6 VZ |
10568 | /* then, configure a new MACs list */ |
10569 | if (netdev_mc_count(dev)) { | |
10570 | rc = bnx2x_init_mcast_macs_list(bp, &rparam); | |
10571 | if (rc) { | |
51c1a580 MS |
10572 | BNX2X_ERR("Failed to create multicast MACs list: %d\n", |
10573 | rc); | |
619c5cb6 VZ |
10574 | return rc; |
10575 | } | |
6e30dd4e | 10576 | |
619c5cb6 VZ |
10577 | /* Now add the new MACs */ |
10578 | rc = bnx2x_config_mcast(bp, &rparam, | |
10579 | BNX2X_MCAST_CMD_ADD); | |
10580 | if (rc < 0) | |
51c1a580 MS |
10581 | BNX2X_ERR("Failed to set a new multicast configuration: %d\n", |
10582 | rc); | |
6e30dd4e | 10583 | |
619c5cb6 VZ |
10584 | bnx2x_free_mcast_macs_list(&rparam); |
10585 | } | |
6e30dd4e | 10586 | |
619c5cb6 | 10587 | return rc; |
6e30dd4e VZ |
10588 | } |
10589 | ||
6e30dd4e | 10590 | |
619c5cb6 | 10591 | /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ |
9f6c9258 | 10592 | void bnx2x_set_rx_mode(struct net_device *dev) |
34f80b04 EG |
10593 | { |
10594 | struct bnx2x *bp = netdev_priv(dev); | |
10595 | u32 rx_mode = BNX2X_RX_MODE_NORMAL; | |
34f80b04 EG |
10596 | |
10597 | if (bp->state != BNX2X_STATE_OPEN) { | |
10598 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); | |
10599 | return; | |
10600 | } | |
10601 | ||
619c5cb6 | 10602 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); |
34f80b04 EG |
10603 | |
10604 | if (dev->flags & IFF_PROMISC) | |
10605 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
619c5cb6 VZ |
10606 | else if ((dev->flags & IFF_ALLMULTI) || |
10607 | ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && | |
10608 | CHIP_IS_E1(bp))) | |
34f80b04 | 10609 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
6e30dd4e VZ |
10610 | else { |
10611 | /* some multicasts */ | |
619c5cb6 | 10612 | if (bnx2x_set_mc_list(bp) < 0) |
6e30dd4e | 10613 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
34f80b04 | 10614 | |
619c5cb6 | 10615 | if (bnx2x_set_uc_list(bp) < 0) |
6e30dd4e | 10616 | rx_mode = BNX2X_RX_MODE_PROMISC; |
34f80b04 EG |
10617 | } |
10618 | ||
10619 | bp->rx_mode = rx_mode; | |
614c76df DK |
10620 | #ifdef BCM_CNIC |
10621 | /* handle ISCSI SD mode */ | |
10622 | if (IS_MF_ISCSI_SD(bp)) | |
10623 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
10624 | #endif | |
619c5cb6 VZ |
10625 | |
10626 | /* Schedule the rx_mode command */ | |
10627 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { | |
10628 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
10629 | return; | |
10630 | } | |
10631 | ||
34f80b04 EG |
10632 | bnx2x_set_storm_rx_mode(bp); |
10633 | } | |
10634 | ||
c18487ee | 10635 | /* called with rtnl_lock */ |
01cd4528 EG |
10636 | static int bnx2x_mdio_read(struct net_device *netdev, int prtad, |
10637 | int devad, u16 addr) | |
a2fbb9ea | 10638 | { |
01cd4528 EG |
10639 | struct bnx2x *bp = netdev_priv(netdev); |
10640 | u16 value; | |
10641 | int rc; | |
a2fbb9ea | 10642 | |
01cd4528 EG |
10643 | DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", |
10644 | prtad, devad, addr); | |
a2fbb9ea | 10645 | |
01cd4528 EG |
10646 | /* The HW expects different devad if CL22 is used */ |
10647 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
c18487ee | 10648 | |
01cd4528 | 10649 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 10650 | rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); |
01cd4528 EG |
10651 | bnx2x_release_phy_lock(bp); |
10652 | DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); | |
a2fbb9ea | 10653 | |
01cd4528 EG |
10654 | if (!rc) |
10655 | rc = value; | |
10656 | return rc; | |
10657 | } | |
a2fbb9ea | 10658 | |
01cd4528 EG |
10659 | /* called with rtnl_lock */ |
10660 | static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, | |
10661 | u16 addr, u16 value) | |
10662 | { | |
10663 | struct bnx2x *bp = netdev_priv(netdev); | |
01cd4528 EG |
10664 | int rc; |
10665 | ||
51c1a580 MS |
10666 | DP(NETIF_MSG_LINK, |
10667 | "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", | |
10668 | prtad, devad, addr, value); | |
01cd4528 | 10669 | |
01cd4528 EG |
10670 | /* The HW expects different devad if CL22 is used */ |
10671 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
a2fbb9ea | 10672 | |
01cd4528 | 10673 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 10674 | rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); |
01cd4528 EG |
10675 | bnx2x_release_phy_lock(bp); |
10676 | return rc; | |
10677 | } | |
c18487ee | 10678 | |
01cd4528 EG |
10679 | /* called with rtnl_lock */ |
10680 | static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
10681 | { | |
10682 | struct bnx2x *bp = netdev_priv(dev); | |
10683 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
a2fbb9ea | 10684 | |
01cd4528 EG |
10685 | DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", |
10686 | mdio->phy_id, mdio->reg_num, mdio->val_in); | |
a2fbb9ea | 10687 | |
01cd4528 EG |
10688 | if (!netif_running(dev)) |
10689 | return -EAGAIN; | |
10690 | ||
10691 | return mdio_mii_ioctl(&bp->mdio, mdio, cmd); | |
a2fbb9ea ET |
10692 | } |
10693 | ||
257ddbda | 10694 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a2fbb9ea ET |
10695 | static void poll_bnx2x(struct net_device *dev) |
10696 | { | |
10697 | struct bnx2x *bp = netdev_priv(dev); | |
10698 | ||
10699 | disable_irq(bp->pdev->irq); | |
10700 | bnx2x_interrupt(bp->pdev->irq, dev); | |
10701 | enable_irq(bp->pdev->irq); | |
10702 | } | |
10703 | #endif | |
10704 | ||
614c76df DK |
10705 | static int bnx2x_validate_addr(struct net_device *dev) |
10706 | { | |
10707 | struct bnx2x *bp = netdev_priv(dev); | |
10708 | ||
51c1a580 MS |
10709 | if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) { |
10710 | BNX2X_ERR("Non-valid Ethernet address\n"); | |
614c76df | 10711 | return -EADDRNOTAVAIL; |
51c1a580 | 10712 | } |
614c76df DK |
10713 | return 0; |
10714 | } | |
10715 | ||
c64213cd SH |
10716 | static const struct net_device_ops bnx2x_netdev_ops = { |
10717 | .ndo_open = bnx2x_open, | |
10718 | .ndo_stop = bnx2x_close, | |
10719 | .ndo_start_xmit = bnx2x_start_xmit, | |
8307fa3e | 10720 | .ndo_select_queue = bnx2x_select_queue, |
6e30dd4e | 10721 | .ndo_set_rx_mode = bnx2x_set_rx_mode, |
c64213cd | 10722 | .ndo_set_mac_address = bnx2x_change_mac_addr, |
614c76df | 10723 | .ndo_validate_addr = bnx2x_validate_addr, |
c64213cd SH |
10724 | .ndo_do_ioctl = bnx2x_ioctl, |
10725 | .ndo_change_mtu = bnx2x_change_mtu, | |
66371c44 MM |
10726 | .ndo_fix_features = bnx2x_fix_features, |
10727 | .ndo_set_features = bnx2x_set_features, | |
c64213cd | 10728 | .ndo_tx_timeout = bnx2x_tx_timeout, |
257ddbda | 10729 | #ifdef CONFIG_NET_POLL_CONTROLLER |
c64213cd SH |
10730 | .ndo_poll_controller = poll_bnx2x, |
10731 | #endif | |
6383c0b3 AE |
10732 | .ndo_setup_tc = bnx2x_setup_tc, |
10733 | ||
bf61ee14 VZ |
10734 | #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) |
10735 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, | |
10736 | #endif | |
c64213cd SH |
10737 | }; |
10738 | ||
619c5cb6 VZ |
10739 | static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) |
10740 | { | |
10741 | struct device *dev = &bp->pdev->dev; | |
10742 | ||
10743 | if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { | |
10744 | bp->flags |= USING_DAC_FLAG; | |
10745 | if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { | |
51c1a580 | 10746 | dev_err(dev, "dma_set_coherent_mask failed, aborting\n"); |
619c5cb6 VZ |
10747 | return -EIO; |
10748 | } | |
10749 | } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { | |
10750 | dev_err(dev, "System does not support DMA, aborting\n"); | |
10751 | return -EIO; | |
10752 | } | |
10753 | ||
10754 | return 0; | |
10755 | } | |
10756 | ||
34f80b04 | 10757 | static int __devinit bnx2x_init_dev(struct pci_dev *pdev, |
619c5cb6 VZ |
10758 | struct net_device *dev, |
10759 | unsigned long board_type) | |
a2fbb9ea ET |
10760 | { |
10761 | struct bnx2x *bp; | |
10762 | int rc; | |
c22610d0 | 10763 | u32 pci_cfg_dword; |
65087cfe AE |
10764 | bool chip_is_e1x = (board_type == BCM57710 || |
10765 | board_type == BCM57711 || | |
10766 | board_type == BCM57711E); | |
a2fbb9ea ET |
10767 | |
10768 | SET_NETDEV_DEV(dev, &pdev->dev); | |
10769 | bp = netdev_priv(dev); | |
10770 | ||
34f80b04 EG |
10771 | bp->dev = dev; |
10772 | bp->pdev = pdev; | |
a2fbb9ea | 10773 | bp->flags = 0; |
a2fbb9ea ET |
10774 | |
10775 | rc = pci_enable_device(pdev); | |
10776 | if (rc) { | |
cdaa7cb8 VZ |
10777 | dev_err(&bp->pdev->dev, |
10778 | "Cannot enable PCI device, aborting\n"); | |
a2fbb9ea ET |
10779 | goto err_out; |
10780 | } | |
10781 | ||
10782 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
10783 | dev_err(&bp->pdev->dev, |
10784 | "Cannot find PCI device base address, aborting\n"); | |
a2fbb9ea ET |
10785 | rc = -ENODEV; |
10786 | goto err_out_disable; | |
10787 | } | |
10788 | ||
10789 | if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
10790 | dev_err(&bp->pdev->dev, "Cannot find second PCI device" |
10791 | " base address, aborting\n"); | |
a2fbb9ea ET |
10792 | rc = -ENODEV; |
10793 | goto err_out_disable; | |
10794 | } | |
10795 | ||
34f80b04 EG |
10796 | if (atomic_read(&pdev->enable_cnt) == 1) { |
10797 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
10798 | if (rc) { | |
cdaa7cb8 VZ |
10799 | dev_err(&bp->pdev->dev, |
10800 | "Cannot obtain PCI resources, aborting\n"); | |
34f80b04 EG |
10801 | goto err_out_disable; |
10802 | } | |
a2fbb9ea | 10803 | |
34f80b04 EG |
10804 | pci_set_master(pdev); |
10805 | pci_save_state(pdev); | |
10806 | } | |
a2fbb9ea ET |
10807 | |
10808 | bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
10809 | if (bp->pm_cap == 0) { | |
cdaa7cb8 VZ |
10810 | dev_err(&bp->pdev->dev, |
10811 | "Cannot find power management capability, aborting\n"); | |
a2fbb9ea ET |
10812 | rc = -EIO; |
10813 | goto err_out_release; | |
10814 | } | |
10815 | ||
77c98e6a | 10816 | if (!pci_is_pcie(pdev)) { |
51c1a580 | 10817 | dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); |
a2fbb9ea ET |
10818 | rc = -EIO; |
10819 | goto err_out_release; | |
10820 | } | |
10821 | ||
619c5cb6 VZ |
10822 | rc = bnx2x_set_coherency_mask(bp); |
10823 | if (rc) | |
a2fbb9ea | 10824 | goto err_out_release; |
a2fbb9ea | 10825 | |
34f80b04 EG |
10826 | dev->mem_start = pci_resource_start(pdev, 0); |
10827 | dev->base_addr = dev->mem_start; | |
10828 | dev->mem_end = pci_resource_end(pdev, 0); | |
a2fbb9ea ET |
10829 | |
10830 | dev->irq = pdev->irq; | |
10831 | ||
275f165f | 10832 | bp->regview = pci_ioremap_bar(pdev, 0); |
a2fbb9ea | 10833 | if (!bp->regview) { |
cdaa7cb8 VZ |
10834 | dev_err(&bp->pdev->dev, |
10835 | "Cannot map register space, aborting\n"); | |
a2fbb9ea ET |
10836 | rc = -ENOMEM; |
10837 | goto err_out_release; | |
10838 | } | |
10839 | ||
c22610d0 AE |
10840 | /* In E1/E1H use pci device function given by kernel. |
10841 | * In E2/E3 read physical function from ME register since these chips | |
10842 | * support Physical Device Assignment where kernel BDF maybe arbitrary | |
10843 | * (depending on hypervisor). | |
10844 | */ | |
10845 | if (chip_is_e1x) | |
10846 | bp->pf_num = PCI_FUNC(pdev->devfn); | |
10847 | else {/* chip is E2/3*/ | |
10848 | pci_read_config_dword(bp->pdev, | |
10849 | PCICFG_ME_REGISTER, &pci_cfg_dword); | |
10850 | bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> | |
10851 | ME_REG_ABS_PF_NUM_SHIFT); | |
10852 | } | |
51c1a580 | 10853 | BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); |
c22610d0 | 10854 | |
a2fbb9ea ET |
10855 | bnx2x_set_power_state(bp, PCI_D0); |
10856 | ||
34f80b04 EG |
10857 | /* clean indirect addresses */ |
10858 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
10859 | PCICFG_VENDOR_ID_OFFSET); | |
a5c53dbc DK |
10860 | /* |
10861 | * Clean the following indirect addresses for all functions since it | |
9f0096a1 DK |
10862 | * is not used by the driver. |
10863 | */ | |
10864 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); | |
10865 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); | |
10866 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); | |
10867 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); | |
a5c53dbc | 10868 | |
65087cfe | 10869 | if (chip_is_e1x) { |
a5c53dbc DK |
10870 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); |
10871 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); | |
10872 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); | |
10873 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); | |
10874 | } | |
a2fbb9ea | 10875 | |
2189400b | 10876 | /* |
619c5cb6 | 10877 | * Enable internal target-read (in case we are probed after PF FLR). |
2189400b | 10878 | * Must be done prior to any BAR read access. Only for 57712 and up |
619c5cb6 | 10879 | */ |
65087cfe | 10880 | if (!chip_is_e1x) |
2189400b | 10881 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); |
619c5cb6 | 10882 | |
72fd0718 | 10883 | /* Reset the load counter */ |
889b9af3 | 10884 | bnx2x_clear_load_status(bp); |
72fd0718 | 10885 | |
34f80b04 | 10886 | dev->watchdog_timeo = TX_TIMEOUT; |
a2fbb9ea | 10887 | |
c64213cd | 10888 | dev->netdev_ops = &bnx2x_netdev_ops; |
de0c62db | 10889 | bnx2x_set_ethtool_ops(dev); |
5316bc0b | 10890 | |
01789349 JP |
10891 | dev->priv_flags |= IFF_UNICAST_FLT; |
10892 | ||
66371c44 | 10893 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
621b4d66 DK |
10894 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | |
10895 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | | |
10896 | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; | |
66371c44 MM |
10897 | |
10898 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
10899 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; | |
10900 | ||
10901 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; | |
5316bc0b | 10902 | if (bp->flags & USING_DAC_FLAG) |
66371c44 | 10903 | dev->features |= NETIF_F_HIGHDMA; |
a2fbb9ea | 10904 | |
538dd2e3 MB |
10905 | /* Add Loopback capability to the device */ |
10906 | dev->hw_features |= NETIF_F_LOOPBACK; | |
10907 | ||
98507672 | 10908 | #ifdef BCM_DCBNL |
785b9b1a SR |
10909 | dev->dcbnl_ops = &bnx2x_dcbnl_ops; |
10910 | #endif | |
10911 | ||
01cd4528 EG |
10912 | /* get_port_hwinfo() will set prtad and mmds properly */ |
10913 | bp->mdio.prtad = MDIO_PRTAD_NONE; | |
10914 | bp->mdio.mmds = 0; | |
10915 | bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
10916 | bp->mdio.dev = dev; | |
10917 | bp->mdio.mdio_read = bnx2x_mdio_read; | |
10918 | bp->mdio.mdio_write = bnx2x_mdio_write; | |
10919 | ||
a2fbb9ea ET |
10920 | return 0; |
10921 | ||
a2fbb9ea | 10922 | err_out_release: |
34f80b04 EG |
10923 | if (atomic_read(&pdev->enable_cnt) == 1) |
10924 | pci_release_regions(pdev); | |
a2fbb9ea ET |
10925 | |
10926 | err_out_disable: | |
10927 | pci_disable_device(pdev); | |
10928 | pci_set_drvdata(pdev, NULL); | |
10929 | ||
10930 | err_out: | |
10931 | return rc; | |
10932 | } | |
10933 | ||
37f9ce62 EG |
10934 | static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, |
10935 | int *width, int *speed) | |
25047950 ET |
10936 | { |
10937 | u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); | |
10938 | ||
37f9ce62 | 10939 | *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; |
25047950 | 10940 | |
37f9ce62 EG |
10941 | /* return value of 1=2.5GHz 2=5GHz */ |
10942 | *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; | |
25047950 | 10943 | } |
37f9ce62 | 10944 | |
6891dd25 | 10945 | static int bnx2x_check_firmware(struct bnx2x *bp) |
94a78b79 | 10946 | { |
37f9ce62 | 10947 | const struct firmware *firmware = bp->firmware; |
94a78b79 VZ |
10948 | struct bnx2x_fw_file_hdr *fw_hdr; |
10949 | struct bnx2x_fw_file_section *sections; | |
94a78b79 | 10950 | u32 offset, len, num_ops; |
37f9ce62 | 10951 | u16 *ops_offsets; |
94a78b79 | 10952 | int i; |
37f9ce62 | 10953 | const u8 *fw_ver; |
94a78b79 | 10954 | |
51c1a580 MS |
10955 | if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { |
10956 | BNX2X_ERR("Wrong FW size\n"); | |
94a78b79 | 10957 | return -EINVAL; |
51c1a580 | 10958 | } |
94a78b79 VZ |
10959 | |
10960 | fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; | |
10961 | sections = (struct bnx2x_fw_file_section *)fw_hdr; | |
10962 | ||
10963 | /* Make sure none of the offsets and sizes make us read beyond | |
10964 | * the end of the firmware data */ | |
10965 | for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { | |
10966 | offset = be32_to_cpu(sections[i].offset); | |
10967 | len = be32_to_cpu(sections[i].len); | |
10968 | if (offset + len > firmware->size) { | |
51c1a580 | 10969 | BNX2X_ERR("Section %d length is out of bounds\n", i); |
94a78b79 VZ |
10970 | return -EINVAL; |
10971 | } | |
10972 | } | |
10973 | ||
10974 | /* Likewise for the init_ops offsets */ | |
10975 | offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); | |
10976 | ops_offsets = (u16 *)(firmware->data + offset); | |
10977 | num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); | |
10978 | ||
10979 | for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { | |
10980 | if (be16_to_cpu(ops_offsets[i]) > num_ops) { | |
51c1a580 | 10981 | BNX2X_ERR("Section offset %d is out of bounds\n", i); |
94a78b79 VZ |
10982 | return -EINVAL; |
10983 | } | |
10984 | } | |
10985 | ||
10986 | /* Check FW version */ | |
10987 | offset = be32_to_cpu(fw_hdr->fw_version.offset); | |
10988 | fw_ver = firmware->data + offset; | |
10989 | if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || | |
10990 | (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || | |
10991 | (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || | |
10992 | (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { | |
51c1a580 MS |
10993 | BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", |
10994 | fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], | |
10995 | BCM_5710_FW_MAJOR_VERSION, | |
94a78b79 VZ |
10996 | BCM_5710_FW_MINOR_VERSION, |
10997 | BCM_5710_FW_REVISION_VERSION, | |
10998 | BCM_5710_FW_ENGINEERING_VERSION); | |
ab6ad5a4 | 10999 | return -EINVAL; |
94a78b79 VZ |
11000 | } |
11001 | ||
11002 | return 0; | |
11003 | } | |
11004 | ||
ab6ad5a4 | 11005 | static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 11006 | { |
ab6ad5a4 EG |
11007 | const __be32 *source = (const __be32 *)_source; |
11008 | u32 *target = (u32 *)_target; | |
94a78b79 | 11009 | u32 i; |
94a78b79 VZ |
11010 | |
11011 | for (i = 0; i < n/4; i++) | |
11012 | target[i] = be32_to_cpu(source[i]); | |
11013 | } | |
11014 | ||
11015 | /* | |
11016 | Ops array is stored in the following format: | |
11017 | {op(8bit), offset(24bit, big endian), data(32bit, big endian)} | |
11018 | */ | |
ab6ad5a4 | 11019 | static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 11020 | { |
ab6ad5a4 EG |
11021 | const __be32 *source = (const __be32 *)_source; |
11022 | struct raw_op *target = (struct raw_op *)_target; | |
94a78b79 | 11023 | u32 i, j, tmp; |
94a78b79 | 11024 | |
ab6ad5a4 | 11025 | for (i = 0, j = 0; i < n/8; i++, j += 2) { |
94a78b79 VZ |
11026 | tmp = be32_to_cpu(source[j]); |
11027 | target[i].op = (tmp >> 24) & 0xff; | |
cdaa7cb8 VZ |
11028 | target[i].offset = tmp & 0xffffff; |
11029 | target[i].raw_data = be32_to_cpu(source[j + 1]); | |
94a78b79 VZ |
11030 | } |
11031 | } | |
ab6ad5a4 | 11032 | |
523224a3 DK |
11033 | /** |
11034 | * IRO array is stored in the following format: | |
11035 | * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } | |
11036 | */ | |
11037 | static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) | |
11038 | { | |
11039 | const __be32 *source = (const __be32 *)_source; | |
11040 | struct iro *target = (struct iro *)_target; | |
11041 | u32 i, j, tmp; | |
11042 | ||
11043 | for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { | |
11044 | target[i].base = be32_to_cpu(source[j]); | |
11045 | j++; | |
11046 | tmp = be32_to_cpu(source[j]); | |
11047 | target[i].m1 = (tmp >> 16) & 0xffff; | |
11048 | target[i].m2 = tmp & 0xffff; | |
11049 | j++; | |
11050 | tmp = be32_to_cpu(source[j]); | |
11051 | target[i].m3 = (tmp >> 16) & 0xffff; | |
11052 | target[i].size = tmp & 0xffff; | |
11053 | j++; | |
11054 | } | |
11055 | } | |
11056 | ||
ab6ad5a4 | 11057 | static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 11058 | { |
ab6ad5a4 EG |
11059 | const __be16 *source = (const __be16 *)_source; |
11060 | u16 *target = (u16 *)_target; | |
94a78b79 | 11061 | u32 i; |
94a78b79 VZ |
11062 | |
11063 | for (i = 0; i < n/2; i++) | |
11064 | target[i] = be16_to_cpu(source[i]); | |
11065 | } | |
11066 | ||
7995c64e JP |
11067 | #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ |
11068 | do { \ | |
11069 | u32 len = be32_to_cpu(fw_hdr->arr.len); \ | |
11070 | bp->arr = kmalloc(len, GFP_KERNEL); \ | |
e404decb | 11071 | if (!bp->arr) \ |
7995c64e | 11072 | goto lbl; \ |
7995c64e JP |
11073 | func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ |
11074 | (u8 *)bp->arr, len); \ | |
11075 | } while (0) | |
94a78b79 | 11076 | |
3b603066 | 11077 | static int bnx2x_init_firmware(struct bnx2x *bp) |
94a78b79 | 11078 | { |
c0ea452e | 11079 | const char *fw_file_name; |
94a78b79 | 11080 | struct bnx2x_fw_file_hdr *fw_hdr; |
45229b42 | 11081 | int rc; |
94a78b79 | 11082 | |
c0ea452e MS |
11083 | if (bp->firmware) |
11084 | return 0; | |
94a78b79 | 11085 | |
c0ea452e MS |
11086 | if (CHIP_IS_E1(bp)) |
11087 | fw_file_name = FW_FILE_NAME_E1; | |
11088 | else if (CHIP_IS_E1H(bp)) | |
11089 | fw_file_name = FW_FILE_NAME_E1H; | |
11090 | else if (!CHIP_IS_E1x(bp)) | |
11091 | fw_file_name = FW_FILE_NAME_E2; | |
11092 | else { | |
11093 | BNX2X_ERR("Unsupported chip revision\n"); | |
11094 | return -EINVAL; | |
11095 | } | |
11096 | BNX2X_DEV_INFO("Loading %s\n", fw_file_name); | |
94a78b79 | 11097 | |
c0ea452e MS |
11098 | rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); |
11099 | if (rc) { | |
11100 | BNX2X_ERR("Can't load firmware file %s\n", | |
11101 | fw_file_name); | |
11102 | goto request_firmware_exit; | |
11103 | } | |
eb2afd4a | 11104 | |
c0ea452e MS |
11105 | rc = bnx2x_check_firmware(bp); |
11106 | if (rc) { | |
11107 | BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); | |
11108 | goto request_firmware_exit; | |
94a78b79 VZ |
11109 | } |
11110 | ||
11111 | fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; | |
11112 | ||
11113 | /* Initialize the pointers to the init arrays */ | |
11114 | /* Blob */ | |
11115 | BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); | |
11116 | ||
11117 | /* Opcodes */ | |
11118 | BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); | |
11119 | ||
11120 | /* Offsets */ | |
ab6ad5a4 EG |
11121 | BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, |
11122 | be16_to_cpu_n); | |
94a78b79 VZ |
11123 | |
11124 | /* STORMs firmware */ | |
573f2035 EG |
11125 | INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
11126 | be32_to_cpu(fw_hdr->tsem_int_table_data.offset); | |
11127 | INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + | |
11128 | be32_to_cpu(fw_hdr->tsem_pram_data.offset); | |
11129 | INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
11130 | be32_to_cpu(fw_hdr->usem_int_table_data.offset); | |
11131 | INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + | |
11132 | be32_to_cpu(fw_hdr->usem_pram_data.offset); | |
11133 | INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
11134 | be32_to_cpu(fw_hdr->xsem_int_table_data.offset); | |
11135 | INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + | |
11136 | be32_to_cpu(fw_hdr->xsem_pram_data.offset); | |
11137 | INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
11138 | be32_to_cpu(fw_hdr->csem_int_table_data.offset); | |
11139 | INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + | |
11140 | be32_to_cpu(fw_hdr->csem_pram_data.offset); | |
523224a3 DK |
11141 | /* IRO */ |
11142 | BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); | |
94a78b79 VZ |
11143 | |
11144 | return 0; | |
ab6ad5a4 | 11145 | |
523224a3 DK |
11146 | iro_alloc_err: |
11147 | kfree(bp->init_ops_offsets); | |
94a78b79 VZ |
11148 | init_offsets_alloc_err: |
11149 | kfree(bp->init_ops); | |
11150 | init_ops_alloc_err: | |
11151 | kfree(bp->init_data); | |
11152 | request_firmware_exit: | |
11153 | release_firmware(bp->firmware); | |
127d0a19 | 11154 | bp->firmware = NULL; |
94a78b79 VZ |
11155 | |
11156 | return rc; | |
11157 | } | |
11158 | ||
619c5cb6 VZ |
11159 | static void bnx2x_release_firmware(struct bnx2x *bp) |
11160 | { | |
11161 | kfree(bp->init_ops_offsets); | |
11162 | kfree(bp->init_ops); | |
11163 | kfree(bp->init_data); | |
11164 | release_firmware(bp->firmware); | |
eb2afd4a | 11165 | bp->firmware = NULL; |
619c5cb6 VZ |
11166 | } |
11167 | ||
11168 | ||
11169 | static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { | |
11170 | .init_hw_cmn_chip = bnx2x_init_hw_common_chip, | |
11171 | .init_hw_cmn = bnx2x_init_hw_common, | |
11172 | .init_hw_port = bnx2x_init_hw_port, | |
11173 | .init_hw_func = bnx2x_init_hw_func, | |
11174 | ||
11175 | .reset_hw_cmn = bnx2x_reset_common, | |
11176 | .reset_hw_port = bnx2x_reset_port, | |
11177 | .reset_hw_func = bnx2x_reset_func, | |
11178 | ||
11179 | .gunzip_init = bnx2x_gunzip_init, | |
11180 | .gunzip_end = bnx2x_gunzip_end, | |
11181 | ||
11182 | .init_fw = bnx2x_init_firmware, | |
11183 | .release_fw = bnx2x_release_firmware, | |
11184 | }; | |
11185 | ||
11186 | void bnx2x__init_func_obj(struct bnx2x *bp) | |
11187 | { | |
11188 | /* Prepare DMAE related driver resources */ | |
11189 | bnx2x_setup_dmae(bp); | |
11190 | ||
11191 | bnx2x_init_func_obj(bp, &bp->func_obj, | |
11192 | bnx2x_sp(bp, func_rdata), | |
11193 | bnx2x_sp_mapping(bp, func_rdata), | |
11194 | &bnx2x_func_sp_drv); | |
11195 | } | |
11196 | ||
11197 | /* must be called after sriov-enable */ | |
6383c0b3 | 11198 | static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) |
523224a3 | 11199 | { |
6383c0b3 | 11200 | int cid_count = BNX2X_L2_CID_COUNT(bp); |
94a78b79 | 11201 | |
523224a3 DK |
11202 | #ifdef BCM_CNIC |
11203 | cid_count += CNIC_CID_MAX; | |
11204 | #endif | |
11205 | return roundup(cid_count, QM_CID_ROUND); | |
11206 | } | |
f85582f8 | 11207 | |
619c5cb6 | 11208 | /** |
6383c0b3 | 11209 | * bnx2x_get_num_none_def_sbs - return the number of none default SBs |
619c5cb6 VZ |
11210 | * |
11211 | * @dev: pci device | |
11212 | * | |
11213 | */ | |
6383c0b3 | 11214 | static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) |
619c5cb6 VZ |
11215 | { |
11216 | int pos; | |
11217 | u16 control; | |
11218 | ||
11219 | pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); | |
6383c0b3 AE |
11220 | |
11221 | /* | |
11222 | * If MSI-X is not supported - return number of SBs needed to support | |
11223 | * one fast path queue: one FP queue + SB for CNIC | |
11224 | */ | |
619c5cb6 | 11225 | if (!pos) |
6383c0b3 | 11226 | return 1 + CNIC_PRESENT; |
619c5cb6 | 11227 | |
6383c0b3 AE |
11228 | /* |
11229 | * The value in the PCI configuration space is the index of the last | |
11230 | * entry, namely one less than the actual size of the table, which is | |
11231 | * exactly what we want to return from this function: number of all SBs | |
11232 | * without the default SB. | |
11233 | */ | |
619c5cb6 | 11234 | pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); |
6383c0b3 | 11235 | return control & PCI_MSIX_FLAGS_QSIZE; |
619c5cb6 VZ |
11236 | } |
11237 | ||
a2fbb9ea ET |
11238 | static int __devinit bnx2x_init_one(struct pci_dev *pdev, |
11239 | const struct pci_device_id *ent) | |
11240 | { | |
a2fbb9ea ET |
11241 | struct net_device *dev = NULL; |
11242 | struct bnx2x *bp; | |
37f9ce62 | 11243 | int pcie_width, pcie_speed; |
6383c0b3 AE |
11244 | int rc, max_non_def_sbs; |
11245 | int rx_count, tx_count, rss_count; | |
11246 | /* | |
11247 | * An estimated maximum supported CoS number according to the chip | |
11248 | * version. | |
11249 | * We will try to roughly estimate the maximum number of CoSes this chip | |
11250 | * may support in order to minimize the memory allocated for Tx | |
11251 | * netdev_queue's. This number will be accurately calculated during the | |
11252 | * initialization of bp->max_cos based on the chip versions AND chip | |
11253 | * revision in the bnx2x_init_bp(). | |
11254 | */ | |
11255 | u8 max_cos_est = 0; | |
523224a3 | 11256 | |
f2e0899f DK |
11257 | switch (ent->driver_data) { |
11258 | case BCM57710: | |
11259 | case BCM57711: | |
11260 | case BCM57711E: | |
6383c0b3 AE |
11261 | max_cos_est = BNX2X_MULTI_TX_COS_E1X; |
11262 | break; | |
11263 | ||
f2e0899f | 11264 | case BCM57712: |
619c5cb6 | 11265 | case BCM57712_MF: |
6383c0b3 AE |
11266 | max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; |
11267 | break; | |
11268 | ||
619c5cb6 VZ |
11269 | case BCM57800: |
11270 | case BCM57800_MF: | |
11271 | case BCM57810: | |
11272 | case BCM57810_MF: | |
11273 | case BCM57840: | |
11274 | case BCM57840_MF: | |
7e8e02df BW |
11275 | case BCM57811: |
11276 | case BCM57811_MF: | |
6383c0b3 | 11277 | max_cos_est = BNX2X_MULTI_TX_COS_E3B0; |
f2e0899f | 11278 | break; |
a2fbb9ea | 11279 | |
f2e0899f DK |
11280 | default: |
11281 | pr_err("Unknown board_type (%ld), aborting\n", | |
11282 | ent->driver_data); | |
870634b0 | 11283 | return -ENODEV; |
f2e0899f DK |
11284 | } |
11285 | ||
6383c0b3 AE |
11286 | max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); |
11287 | ||
11288 | /* !!! FIXME !!! | |
11289 | * Do not allow the maximum SB count to grow above 16 | |
11290 | * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. | |
11291 | * We will use the FP_SB_MAX_E1x macro for this matter. | |
11292 | */ | |
11293 | max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); | |
11294 | ||
11295 | WARN_ON(!max_non_def_sbs); | |
11296 | ||
11297 | /* Maximum number of RSS queues: one IGU SB goes to CNIC */ | |
11298 | rss_count = max_non_def_sbs - CNIC_PRESENT; | |
11299 | ||
11300 | /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ | |
11301 | rx_count = rss_count + FCOE_PRESENT; | |
11302 | ||
11303 | /* | |
11304 | * Maximum number of netdev Tx queues: | |
11305 | * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 | |
11306 | */ | |
11307 | tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; | |
f85582f8 | 11308 | |
a2fbb9ea | 11309 | /* dev zeroed in init_etherdev */ |
6383c0b3 | 11310 | dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); |
41de8d4c | 11311 | if (!dev) |
a2fbb9ea ET |
11312 | return -ENOMEM; |
11313 | ||
a2fbb9ea | 11314 | bp = netdev_priv(dev); |
a2fbb9ea | 11315 | |
51c1a580 | 11316 | BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", |
6383c0b3 | 11317 | tx_count, rx_count); |
df4770de | 11318 | |
6383c0b3 AE |
11319 | bp->igu_sb_cnt = max_non_def_sbs; |
11320 | bp->msg_enable = debug; | |
11321 | pci_set_drvdata(pdev, dev); | |
523224a3 | 11322 | |
619c5cb6 | 11323 | rc = bnx2x_init_dev(pdev, dev, ent->driver_data); |
a2fbb9ea ET |
11324 | if (rc < 0) { |
11325 | free_netdev(dev); | |
11326 | return rc; | |
11327 | } | |
11328 | ||
51c1a580 | 11329 | BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs); |
619c5cb6 | 11330 | |
34f80b04 | 11331 | rc = bnx2x_init_bp(bp); |
693fc0d1 EG |
11332 | if (rc) |
11333 | goto init_one_exit; | |
11334 | ||
6383c0b3 AE |
11335 | /* |
11336 | * Map doorbels here as we need the real value of bp->max_cos which | |
11337 | * is initialized in bnx2x_init_bp(). | |
11338 | */ | |
11339 | bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), | |
11340 | min_t(u64, BNX2X_DB_SIZE(bp), | |
11341 | pci_resource_len(pdev, 2))); | |
11342 | if (!bp->doorbells) { | |
11343 | dev_err(&bp->pdev->dev, | |
11344 | "Cannot map doorbell space, aborting\n"); | |
11345 | rc = -ENOMEM; | |
11346 | goto init_one_exit; | |
11347 | } | |
11348 | ||
523224a3 | 11349 | /* calc qm_cid_count */ |
6383c0b3 | 11350 | bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); |
523224a3 | 11351 | |
ec6ba945 | 11352 | #ifdef BCM_CNIC |
62ac0dc9 DK |
11353 | /* disable FCOE L2 queue for E1x */ |
11354 | if (CHIP_IS_E1x(bp)) | |
ec6ba945 VZ |
11355 | bp->flags |= NO_FCOE_FLAG; |
11356 | ||
11357 | #endif | |
11358 | ||
25985edc | 11359 | /* Configure interrupt mode: try to enable MSI-X/MSI if |
d6214d7a DK |
11360 | * needed, set bp->num_queues appropriately. |
11361 | */ | |
11362 | bnx2x_set_int_mode(bp); | |
11363 | ||
11364 | /* Add all NAPI objects */ | |
11365 | bnx2x_add_all_napi(bp); | |
11366 | ||
b340007f VZ |
11367 | rc = register_netdev(dev); |
11368 | if (rc) { | |
11369 | dev_err(&pdev->dev, "Cannot register net device\n"); | |
11370 | goto init_one_exit; | |
11371 | } | |
11372 | ||
ec6ba945 VZ |
11373 | #ifdef BCM_CNIC |
11374 | if (!NO_FCOE(bp)) { | |
11375 | /* Add storage MAC address */ | |
11376 | rtnl_lock(); | |
11377 | dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
11378 | rtnl_unlock(); | |
11379 | } | |
11380 | #endif | |
11381 | ||
37f9ce62 | 11382 | bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); |
d6214d7a | 11383 | |
51c1a580 MS |
11384 | BNX2X_DEV_INFO( |
11385 | "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", | |
94f05b0f JP |
11386 | board_info[ent->driver_data].name, |
11387 | (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), | |
11388 | pcie_width, | |
11389 | ((!CHIP_IS_E2(bp) && pcie_speed == 2) || | |
11390 | (CHIP_IS_E2(bp) && pcie_speed == 1)) ? | |
11391 | "5GHz (Gen2)" : "2.5GHz", | |
11392 | dev->base_addr, bp->pdev->irq, dev->dev_addr); | |
c016201c | 11393 | |
a2fbb9ea | 11394 | return 0; |
34f80b04 EG |
11395 | |
11396 | init_one_exit: | |
11397 | if (bp->regview) | |
11398 | iounmap(bp->regview); | |
11399 | ||
11400 | if (bp->doorbells) | |
11401 | iounmap(bp->doorbells); | |
11402 | ||
11403 | free_netdev(dev); | |
11404 | ||
11405 | if (atomic_read(&pdev->enable_cnt) == 1) | |
11406 | pci_release_regions(pdev); | |
11407 | ||
11408 | pci_disable_device(pdev); | |
11409 | pci_set_drvdata(pdev, NULL); | |
11410 | ||
11411 | return rc; | |
a2fbb9ea ET |
11412 | } |
11413 | ||
11414 | static void __devexit bnx2x_remove_one(struct pci_dev *pdev) | |
11415 | { | |
11416 | struct net_device *dev = pci_get_drvdata(pdev); | |
228241eb ET |
11417 | struct bnx2x *bp; |
11418 | ||
11419 | if (!dev) { | |
cdaa7cb8 | 11420 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); |
228241eb ET |
11421 | return; |
11422 | } | |
228241eb | 11423 | bp = netdev_priv(dev); |
a2fbb9ea | 11424 | |
ec6ba945 VZ |
11425 | #ifdef BCM_CNIC |
11426 | /* Delete storage MAC address */ | |
11427 | if (!NO_FCOE(bp)) { | |
11428 | rtnl_lock(); | |
11429 | dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
11430 | rtnl_unlock(); | |
11431 | } | |
11432 | #endif | |
11433 | ||
98507672 SR |
11434 | #ifdef BCM_DCBNL |
11435 | /* Delete app tlvs from dcbnl */ | |
11436 | bnx2x_dcbnl_update_applist(bp, true); | |
11437 | #endif | |
11438 | ||
a2fbb9ea ET |
11439 | unregister_netdev(dev); |
11440 | ||
d6214d7a DK |
11441 | /* Delete all NAPI objects */ |
11442 | bnx2x_del_all_napi(bp); | |
11443 | ||
084d6cbb VZ |
11444 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
11445 | bnx2x_set_power_state(bp, PCI_D0); | |
11446 | ||
d6214d7a DK |
11447 | /* Disable MSI/MSI-X */ |
11448 | bnx2x_disable_msi(bp); | |
f85582f8 | 11449 | |
084d6cbb VZ |
11450 | /* Power off */ |
11451 | bnx2x_set_power_state(bp, PCI_D3hot); | |
11452 | ||
72fd0718 | 11453 | /* Make sure RESET task is not scheduled before continuing */ |
7be08a72 | 11454 | cancel_delayed_work_sync(&bp->sp_rtnl_task); |
72fd0718 | 11455 | |
a2fbb9ea ET |
11456 | if (bp->regview) |
11457 | iounmap(bp->regview); | |
11458 | ||
11459 | if (bp->doorbells) | |
11460 | iounmap(bp->doorbells); | |
11461 | ||
eb2afd4a DK |
11462 | bnx2x_release_firmware(bp); |
11463 | ||
523224a3 DK |
11464 | bnx2x_free_mem_bp(bp); |
11465 | ||
a2fbb9ea | 11466 | free_netdev(dev); |
34f80b04 EG |
11467 | |
11468 | if (atomic_read(&pdev->enable_cnt) == 1) | |
11469 | pci_release_regions(pdev); | |
11470 | ||
a2fbb9ea ET |
11471 | pci_disable_device(pdev); |
11472 | pci_set_drvdata(pdev, NULL); | |
11473 | } | |
11474 | ||
f8ef6e44 YG |
11475 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
11476 | { | |
11477 | int i; | |
11478 | ||
11479 | bp->state = BNX2X_STATE_ERROR; | |
11480 | ||
11481 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
11482 | ||
619c5cb6 VZ |
11483 | #ifdef BCM_CNIC |
11484 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); | |
11485 | #endif | |
11486 | /* Stop Tx */ | |
11487 | bnx2x_tx_disable(bp); | |
11488 | ||
f8ef6e44 YG |
11489 | bnx2x_netif_stop(bp, 0); |
11490 | ||
11491 | del_timer_sync(&bp->timer); | |
619c5cb6 VZ |
11492 | |
11493 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
f8ef6e44 YG |
11494 | |
11495 | /* Release IRQs */ | |
d6214d7a | 11496 | bnx2x_free_irq(bp); |
f8ef6e44 | 11497 | |
f8ef6e44 YG |
11498 | /* Free SKBs, SGEs, TPA pool and driver internals */ |
11499 | bnx2x_free_skbs(bp); | |
523224a3 | 11500 | |
ec6ba945 | 11501 | for_each_rx_queue(bp, i) |
f8ef6e44 | 11502 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); |
d6214d7a | 11503 | |
f8ef6e44 YG |
11504 | bnx2x_free_mem(bp); |
11505 | ||
11506 | bp->state = BNX2X_STATE_CLOSED; | |
11507 | ||
619c5cb6 VZ |
11508 | netif_carrier_off(bp->dev); |
11509 | ||
f8ef6e44 YG |
11510 | return 0; |
11511 | } | |
11512 | ||
11513 | static void bnx2x_eeh_recover(struct bnx2x *bp) | |
11514 | { | |
11515 | u32 val; | |
11516 | ||
11517 | mutex_init(&bp->port.phy_mutex); | |
11518 | ||
f8ef6e44 YG |
11519 | |
11520 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
11521 | if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
11522 | != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
11523 | BNX2X_ERR("BAD MCP validity signature\n"); | |
f8ef6e44 YG |
11524 | } |
11525 | ||
493adb1f WX |
11526 | /** |
11527 | * bnx2x_io_error_detected - called when PCI error is detected | |
11528 | * @pdev: Pointer to PCI device | |
11529 | * @state: The current pci connection state | |
11530 | * | |
11531 | * This function is called after a PCI bus error affecting | |
11532 | * this device has been detected. | |
11533 | */ | |
11534 | static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, | |
11535 | pci_channel_state_t state) | |
11536 | { | |
11537 | struct net_device *dev = pci_get_drvdata(pdev); | |
11538 | struct bnx2x *bp = netdev_priv(dev); | |
11539 | ||
11540 | rtnl_lock(); | |
11541 | ||
11542 | netif_device_detach(dev); | |
11543 | ||
07ce50e4 DN |
11544 | if (state == pci_channel_io_perm_failure) { |
11545 | rtnl_unlock(); | |
11546 | return PCI_ERS_RESULT_DISCONNECT; | |
11547 | } | |
11548 | ||
493adb1f | 11549 | if (netif_running(dev)) |
f8ef6e44 | 11550 | bnx2x_eeh_nic_unload(bp); |
493adb1f WX |
11551 | |
11552 | pci_disable_device(pdev); | |
11553 | ||
11554 | rtnl_unlock(); | |
11555 | ||
11556 | /* Request a slot reset */ | |
11557 | return PCI_ERS_RESULT_NEED_RESET; | |
11558 | } | |
11559 | ||
11560 | /** | |
11561 | * bnx2x_io_slot_reset - called after the PCI bus has been reset | |
11562 | * @pdev: Pointer to PCI device | |
11563 | * | |
11564 | * Restart the card from scratch, as if from a cold-boot. | |
11565 | */ | |
11566 | static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) | |
11567 | { | |
11568 | struct net_device *dev = pci_get_drvdata(pdev); | |
11569 | struct bnx2x *bp = netdev_priv(dev); | |
11570 | ||
11571 | rtnl_lock(); | |
11572 | ||
11573 | if (pci_enable_device(pdev)) { | |
11574 | dev_err(&pdev->dev, | |
11575 | "Cannot re-enable PCI device after reset\n"); | |
11576 | rtnl_unlock(); | |
11577 | return PCI_ERS_RESULT_DISCONNECT; | |
11578 | } | |
11579 | ||
11580 | pci_set_master(pdev); | |
11581 | pci_restore_state(pdev); | |
11582 | ||
11583 | if (netif_running(dev)) | |
11584 | bnx2x_set_power_state(bp, PCI_D0); | |
11585 | ||
11586 | rtnl_unlock(); | |
11587 | ||
11588 | return PCI_ERS_RESULT_RECOVERED; | |
11589 | } | |
11590 | ||
11591 | /** | |
11592 | * bnx2x_io_resume - called when traffic can start flowing again | |
11593 | * @pdev: Pointer to PCI device | |
11594 | * | |
11595 | * This callback is called when the error recovery driver tells us that | |
11596 | * its OK to resume normal operation. | |
11597 | */ | |
11598 | static void bnx2x_io_resume(struct pci_dev *pdev) | |
11599 | { | |
11600 | struct net_device *dev = pci_get_drvdata(pdev); | |
11601 | struct bnx2x *bp = netdev_priv(dev); | |
11602 | ||
72fd0718 | 11603 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
51c1a580 | 11604 | netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); |
72fd0718 VZ |
11605 | return; |
11606 | } | |
11607 | ||
493adb1f WX |
11608 | rtnl_lock(); |
11609 | ||
f8ef6e44 YG |
11610 | bnx2x_eeh_recover(bp); |
11611 | ||
493adb1f | 11612 | if (netif_running(dev)) |
f8ef6e44 | 11613 | bnx2x_nic_load(bp, LOAD_NORMAL); |
493adb1f WX |
11614 | |
11615 | netif_device_attach(dev); | |
11616 | ||
11617 | rtnl_unlock(); | |
11618 | } | |
11619 | ||
11620 | static struct pci_error_handlers bnx2x_err_handler = { | |
11621 | .error_detected = bnx2x_io_error_detected, | |
356e2385 EG |
11622 | .slot_reset = bnx2x_io_slot_reset, |
11623 | .resume = bnx2x_io_resume, | |
493adb1f WX |
11624 | }; |
11625 | ||
a2fbb9ea | 11626 | static struct pci_driver bnx2x_pci_driver = { |
493adb1f WX |
11627 | .name = DRV_MODULE_NAME, |
11628 | .id_table = bnx2x_pci_tbl, | |
11629 | .probe = bnx2x_init_one, | |
11630 | .remove = __devexit_p(bnx2x_remove_one), | |
11631 | .suspend = bnx2x_suspend, | |
11632 | .resume = bnx2x_resume, | |
11633 | .err_handler = &bnx2x_err_handler, | |
a2fbb9ea ET |
11634 | }; |
11635 | ||
11636 | static int __init bnx2x_init(void) | |
11637 | { | |
dd21ca6d SG |
11638 | int ret; |
11639 | ||
7995c64e | 11640 | pr_info("%s", version); |
938cf541 | 11641 | |
1cf167f2 EG |
11642 | bnx2x_wq = create_singlethread_workqueue("bnx2x"); |
11643 | if (bnx2x_wq == NULL) { | |
7995c64e | 11644 | pr_err("Cannot create workqueue\n"); |
1cf167f2 EG |
11645 | return -ENOMEM; |
11646 | } | |
11647 | ||
dd21ca6d SG |
11648 | ret = pci_register_driver(&bnx2x_pci_driver); |
11649 | if (ret) { | |
7995c64e | 11650 | pr_err("Cannot register driver\n"); |
dd21ca6d SG |
11651 | destroy_workqueue(bnx2x_wq); |
11652 | } | |
11653 | return ret; | |
a2fbb9ea ET |
11654 | } |
11655 | ||
11656 | static void __exit bnx2x_cleanup(void) | |
11657 | { | |
452427b0 | 11658 | struct list_head *pos, *q; |
a2fbb9ea | 11659 | pci_unregister_driver(&bnx2x_pci_driver); |
1cf167f2 EG |
11660 | |
11661 | destroy_workqueue(bnx2x_wq); | |
452427b0 YM |
11662 | |
11663 | /* Free globablly allocated resources */ | |
11664 | list_for_each_safe(pos, q, &bnx2x_prev_list) { | |
11665 | struct bnx2x_prev_path_list *tmp = | |
11666 | list_entry(pos, struct bnx2x_prev_path_list, list); | |
11667 | list_del(pos); | |
11668 | kfree(tmp); | |
11669 | } | |
a2fbb9ea ET |
11670 | } |
11671 | ||
3deb8167 YR |
11672 | void bnx2x_notify_link_changed(struct bnx2x *bp) |
11673 | { | |
11674 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); | |
11675 | } | |
11676 | ||
a2fbb9ea ET |
11677 | module_init(bnx2x_init); |
11678 | module_exit(bnx2x_cleanup); | |
11679 | ||
993ac7b5 | 11680 | #ifdef BCM_CNIC |
619c5cb6 VZ |
11681 | /** |
11682 | * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). | |
11683 | * | |
11684 | * @bp: driver handle | |
11685 | * @set: set or clear the CAM entry | |
11686 | * | |
11687 | * This function will wait until the ramdord completion returns. | |
11688 | * Return 0 if success, -ENODEV if ramrod doesn't return. | |
11689 | */ | |
11690 | static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) | |
11691 | { | |
11692 | unsigned long ramrod_flags = 0; | |
11693 | ||
11694 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
11695 | return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, | |
11696 | &bp->iscsi_l2_mac_obj, true, | |
11697 | BNX2X_ISCSI_ETH_MAC, &ramrod_flags); | |
11698 | } | |
993ac7b5 MC |
11699 | |
11700 | /* count denotes the number of new completions we have seen */ | |
11701 | static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) | |
11702 | { | |
11703 | struct eth_spe *spe; | |
11704 | ||
11705 | #ifdef BNX2X_STOP_ON_ERROR | |
11706 | if (unlikely(bp->panic)) | |
11707 | return; | |
11708 | #endif | |
11709 | ||
11710 | spin_lock_bh(&bp->spq_lock); | |
c2bff63f | 11711 | BUG_ON(bp->cnic_spq_pending < count); |
993ac7b5 MC |
11712 | bp->cnic_spq_pending -= count; |
11713 | ||
993ac7b5 | 11714 | |
c2bff63f DK |
11715 | for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { |
11716 | u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) | |
11717 | & SPE_HDR_CONN_TYPE) >> | |
11718 | SPE_HDR_CONN_TYPE_SHIFT; | |
619c5cb6 VZ |
11719 | u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) |
11720 | >> SPE_HDR_CMD_ID_SHIFT) & 0xff; | |
c2bff63f DK |
11721 | |
11722 | /* Set validation for iSCSI L2 client before sending SETUP | |
11723 | * ramrod | |
11724 | */ | |
11725 | if (type == ETH_CONNECTION_TYPE) { | |
c2bff63f | 11726 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) |
619c5cb6 VZ |
11727 | bnx2x_set_ctx_validation(bp, &bp->context. |
11728 | vcxt[BNX2X_ISCSI_ETH_CID].eth, | |
11729 | BNX2X_ISCSI_ETH_CID); | |
c2bff63f DK |
11730 | } |
11731 | ||
619c5cb6 VZ |
11732 | /* |
11733 | * There may be not more than 8 L2, not more than 8 L5 SPEs | |
11734 | * and in the air. We also check that number of outstanding | |
6e30dd4e VZ |
11735 | * COMMON ramrods is not more than the EQ and SPQ can |
11736 | * accommodate. | |
c2bff63f | 11737 | */ |
6e30dd4e VZ |
11738 | if (type == ETH_CONNECTION_TYPE) { |
11739 | if (!atomic_read(&bp->cq_spq_left)) | |
11740 | break; | |
11741 | else | |
11742 | atomic_dec(&bp->cq_spq_left); | |
11743 | } else if (type == NONE_CONNECTION_TYPE) { | |
11744 | if (!atomic_read(&bp->eq_spq_left)) | |
c2bff63f DK |
11745 | break; |
11746 | else | |
6e30dd4e | 11747 | atomic_dec(&bp->eq_spq_left); |
ec6ba945 VZ |
11748 | } else if ((type == ISCSI_CONNECTION_TYPE) || |
11749 | (type == FCOE_CONNECTION_TYPE)) { | |
c2bff63f DK |
11750 | if (bp->cnic_spq_pending >= |
11751 | bp->cnic_eth_dev.max_kwqe_pending) | |
11752 | break; | |
11753 | else | |
11754 | bp->cnic_spq_pending++; | |
11755 | } else { | |
11756 | BNX2X_ERR("Unknown SPE type: %d\n", type); | |
11757 | bnx2x_panic(); | |
993ac7b5 | 11758 | break; |
c2bff63f | 11759 | } |
993ac7b5 MC |
11760 | |
11761 | spe = bnx2x_sp_get_next(bp); | |
11762 | *spe = *bp->cnic_kwq_cons; | |
11763 | ||
51c1a580 | 11764 | DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", |
993ac7b5 MC |
11765 | bp->cnic_spq_pending, bp->cnic_kwq_pending, count); |
11766 | ||
11767 | if (bp->cnic_kwq_cons == bp->cnic_kwq_last) | |
11768 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
11769 | else | |
11770 | bp->cnic_kwq_cons++; | |
11771 | } | |
11772 | bnx2x_sp_prod_update(bp); | |
11773 | spin_unlock_bh(&bp->spq_lock); | |
11774 | } | |
11775 | ||
11776 | static int bnx2x_cnic_sp_queue(struct net_device *dev, | |
11777 | struct kwqe_16 *kwqes[], u32 count) | |
11778 | { | |
11779 | struct bnx2x *bp = netdev_priv(dev); | |
11780 | int i; | |
11781 | ||
11782 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 MS |
11783 | if (unlikely(bp->panic)) { |
11784 | BNX2X_ERR("Can't post to SP queue while panic\n"); | |
993ac7b5 | 11785 | return -EIO; |
51c1a580 | 11786 | } |
993ac7b5 MC |
11787 | #endif |
11788 | ||
95c6c616 AE |
11789 | if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && |
11790 | (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
51c1a580 | 11791 | BNX2X_ERR("Handling parity error recovery. Try again later\n"); |
95c6c616 AE |
11792 | return -EAGAIN; |
11793 | } | |
11794 | ||
993ac7b5 MC |
11795 | spin_lock_bh(&bp->spq_lock); |
11796 | ||
11797 | for (i = 0; i < count; i++) { | |
11798 | struct eth_spe *spe = (struct eth_spe *)kwqes[i]; | |
11799 | ||
11800 | if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) | |
11801 | break; | |
11802 | ||
11803 | *bp->cnic_kwq_prod = *spe; | |
11804 | ||
11805 | bp->cnic_kwq_pending++; | |
11806 | ||
51c1a580 | 11807 | DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", |
993ac7b5 | 11808 | spe->hdr.conn_and_cmd_data, spe->hdr.type, |
523224a3 DK |
11809 | spe->data.update_data_addr.hi, |
11810 | spe->data.update_data_addr.lo, | |
993ac7b5 MC |
11811 | bp->cnic_kwq_pending); |
11812 | ||
11813 | if (bp->cnic_kwq_prod == bp->cnic_kwq_last) | |
11814 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
11815 | else | |
11816 | bp->cnic_kwq_prod++; | |
11817 | } | |
11818 | ||
11819 | spin_unlock_bh(&bp->spq_lock); | |
11820 | ||
11821 | if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) | |
11822 | bnx2x_cnic_sp_post(bp, 0); | |
11823 | ||
11824 | return i; | |
11825 | } | |
11826 | ||
11827 | static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
11828 | { | |
11829 | struct cnic_ops *c_ops; | |
11830 | int rc = 0; | |
11831 | ||
11832 | mutex_lock(&bp->cnic_mutex); | |
13707f9e ED |
11833 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
11834 | lockdep_is_held(&bp->cnic_mutex)); | |
993ac7b5 MC |
11835 | if (c_ops) |
11836 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
11837 | mutex_unlock(&bp->cnic_mutex); | |
11838 | ||
11839 | return rc; | |
11840 | } | |
11841 | ||
11842 | static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
11843 | { | |
11844 | struct cnic_ops *c_ops; | |
11845 | int rc = 0; | |
11846 | ||
11847 | rcu_read_lock(); | |
11848 | c_ops = rcu_dereference(bp->cnic_ops); | |
11849 | if (c_ops) | |
11850 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
11851 | rcu_read_unlock(); | |
11852 | ||
11853 | return rc; | |
11854 | } | |
11855 | ||
11856 | /* | |
11857 | * for commands that have no data | |
11858 | */ | |
9f6c9258 | 11859 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) |
993ac7b5 MC |
11860 | { |
11861 | struct cnic_ctl_info ctl = {0}; | |
11862 | ||
11863 | ctl.cmd = cmd; | |
11864 | ||
11865 | return bnx2x_cnic_ctl_send(bp, &ctl); | |
11866 | } | |
11867 | ||
619c5cb6 | 11868 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) |
993ac7b5 | 11869 | { |
619c5cb6 | 11870 | struct cnic_ctl_info ctl = {0}; |
993ac7b5 MC |
11871 | |
11872 | /* first we tell CNIC and only then we count this as a completion */ | |
11873 | ctl.cmd = CNIC_CTL_COMPLETION_CMD; | |
11874 | ctl.data.comp.cid = cid; | |
619c5cb6 | 11875 | ctl.data.comp.error = err; |
993ac7b5 MC |
11876 | |
11877 | bnx2x_cnic_ctl_send_bh(bp, &ctl); | |
c2bff63f | 11878 | bnx2x_cnic_sp_post(bp, 0); |
993ac7b5 MC |
11879 | } |
11880 | ||
619c5cb6 VZ |
11881 | |
11882 | /* Called with netif_addr_lock_bh() taken. | |
11883 | * Sets an rx_mode config for an iSCSI ETH client. | |
11884 | * Doesn't block. | |
11885 | * Completion should be checked outside. | |
11886 | */ | |
11887 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) | |
11888 | { | |
11889 | unsigned long accept_flags = 0, ramrod_flags = 0; | |
11890 | u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
11891 | int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; | |
11892 | ||
11893 | if (start) { | |
11894 | /* Start accepting on iSCSI L2 ring. Accept all multicasts | |
11895 | * because it's the only way for UIO Queue to accept | |
11896 | * multicasts (in non-promiscuous mode only one Queue per | |
11897 | * function will receive multicast packets (leading in our | |
11898 | * case). | |
11899 | */ | |
11900 | __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); | |
11901 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); | |
11902 | __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); | |
11903 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
11904 | ||
11905 | /* Clear STOP_PENDING bit if START is requested */ | |
11906 | clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); | |
11907 | ||
11908 | sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; | |
11909 | } else | |
11910 | /* Clear START_PENDING bit if STOP is requested */ | |
11911 | clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); | |
11912 | ||
11913 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
11914 | set_bit(sched_state, &bp->sp_state); | |
11915 | else { | |
11916 | __set_bit(RAMROD_RX, &ramrod_flags); | |
11917 | bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, | |
11918 | ramrod_flags); | |
11919 | } | |
11920 | } | |
11921 | ||
11922 | ||
993ac7b5 MC |
11923 | static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) |
11924 | { | |
11925 | struct bnx2x *bp = netdev_priv(dev); | |
11926 | int rc = 0; | |
11927 | ||
11928 | switch (ctl->cmd) { | |
11929 | case DRV_CTL_CTXTBL_WR_CMD: { | |
11930 | u32 index = ctl->data.io.offset; | |
11931 | dma_addr_t addr = ctl->data.io.dma_addr; | |
11932 | ||
11933 | bnx2x_ilt_wr(bp, index, addr); | |
11934 | break; | |
11935 | } | |
11936 | ||
c2bff63f DK |
11937 | case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { |
11938 | int count = ctl->data.credit.credit_count; | |
993ac7b5 MC |
11939 | |
11940 | bnx2x_cnic_sp_post(bp, count); | |
11941 | break; | |
11942 | } | |
11943 | ||
11944 | /* rtnl_lock is held. */ | |
11945 | case DRV_CTL_START_L2_CMD: { | |
619c5cb6 VZ |
11946 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
11947 | unsigned long sp_bits = 0; | |
11948 | ||
11949 | /* Configure the iSCSI classification object */ | |
11950 | bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, | |
11951 | cp->iscsi_l2_client_id, | |
11952 | cp->iscsi_l2_cid, BP_FUNC(bp), | |
11953 | bnx2x_sp(bp, mac_rdata), | |
11954 | bnx2x_sp_mapping(bp, mac_rdata), | |
11955 | BNX2X_FILTER_MAC_PENDING, | |
11956 | &bp->sp_state, BNX2X_OBJ_TYPE_RX, | |
11957 | &bp->macs_pool); | |
ec6ba945 | 11958 | |
523224a3 | 11959 | /* Set iSCSI MAC address */ |
619c5cb6 VZ |
11960 | rc = bnx2x_set_iscsi_eth_mac_addr(bp); |
11961 | if (rc) | |
11962 | break; | |
523224a3 DK |
11963 | |
11964 | mmiowb(); | |
11965 | barrier(); | |
11966 | ||
619c5cb6 VZ |
11967 | /* Start accepting on iSCSI L2 ring */ |
11968 | ||
11969 | netif_addr_lock_bh(dev); | |
11970 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
11971 | netif_addr_unlock_bh(dev); | |
11972 | ||
11973 | /* bits to wait on */ | |
11974 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
11975 | __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); | |
11976 | ||
11977 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
11978 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 | 11979 | |
993ac7b5 MC |
11980 | break; |
11981 | } | |
11982 | ||
11983 | /* rtnl_lock is held. */ | |
11984 | case DRV_CTL_STOP_L2_CMD: { | |
619c5cb6 | 11985 | unsigned long sp_bits = 0; |
993ac7b5 | 11986 | |
523224a3 | 11987 | /* Stop accepting on iSCSI L2 ring */ |
619c5cb6 VZ |
11988 | netif_addr_lock_bh(dev); |
11989 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
11990 | netif_addr_unlock_bh(dev); | |
11991 | ||
11992 | /* bits to wait on */ | |
11993 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
11994 | __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); | |
11995 | ||
11996 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
11997 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 DK |
11998 | |
11999 | mmiowb(); | |
12000 | barrier(); | |
12001 | ||
12002 | /* Unset iSCSI L2 MAC */ | |
619c5cb6 VZ |
12003 | rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, |
12004 | BNX2X_ISCSI_ETH_MAC, true); | |
993ac7b5 MC |
12005 | break; |
12006 | } | |
c2bff63f DK |
12007 | case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { |
12008 | int count = ctl->data.credit.credit_count; | |
12009 | ||
12010 | smp_mb__before_atomic_inc(); | |
6e30dd4e | 12011 | atomic_add(count, &bp->cq_spq_left); |
c2bff63f DK |
12012 | smp_mb__after_atomic_inc(); |
12013 | break; | |
12014 | } | |
1d187b34 BW |
12015 | case DRV_CTL_ULP_REGISTER_CMD: { |
12016 | int ulp_type = ctl->data.ulp_type; | |
12017 | ||
12018 | if (CHIP_IS_E3(bp)) { | |
12019 | int idx = BP_FW_MB_IDX(bp); | |
12020 | u32 cap; | |
12021 | ||
12022 | cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); | |
12023 | if (ulp_type == CNIC_ULP_ISCSI) | |
12024 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
12025 | else if (ulp_type == CNIC_ULP_FCOE) | |
12026 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
12027 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
12028 | } | |
12029 | break; | |
12030 | } | |
12031 | case DRV_CTL_ULP_UNREGISTER_CMD: { | |
12032 | int ulp_type = ctl->data.ulp_type; | |
12033 | ||
12034 | if (CHIP_IS_E3(bp)) { | |
12035 | int idx = BP_FW_MB_IDX(bp); | |
12036 | u32 cap; | |
12037 | ||
12038 | cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); | |
12039 | if (ulp_type == CNIC_ULP_ISCSI) | |
12040 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
12041 | else if (ulp_type == CNIC_ULP_FCOE) | |
12042 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
12043 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
12044 | } | |
12045 | break; | |
12046 | } | |
993ac7b5 MC |
12047 | |
12048 | default: | |
12049 | BNX2X_ERR("unknown command %x\n", ctl->cmd); | |
12050 | rc = -EINVAL; | |
12051 | } | |
12052 | ||
12053 | return rc; | |
12054 | } | |
12055 | ||
9f6c9258 | 12056 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) |
993ac7b5 MC |
12057 | { |
12058 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12059 | ||
12060 | if (bp->flags & USING_MSIX_FLAG) { | |
12061 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
12062 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
12063 | cp->irq_arr[0].vector = bp->msix_table[1].vector; | |
12064 | } else { | |
12065 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
12066 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
12067 | } | |
619c5cb6 | 12068 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
12069 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; |
12070 | else | |
12071 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; | |
12072 | ||
619c5cb6 VZ |
12073 | cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); |
12074 | cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); | |
993ac7b5 MC |
12075 | cp->irq_arr[1].status_blk = bp->def_status_blk; |
12076 | cp->irq_arr[1].status_blk_num = DEF_SB_ID; | |
523224a3 | 12077 | cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; |
993ac7b5 MC |
12078 | |
12079 | cp->num_irq = 2; | |
12080 | } | |
12081 | ||
12082 | static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, | |
12083 | void *data) | |
12084 | { | |
12085 | struct bnx2x *bp = netdev_priv(dev); | |
12086 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12087 | ||
51c1a580 MS |
12088 | if (ops == NULL) { |
12089 | BNX2X_ERR("NULL ops received\n"); | |
993ac7b5 | 12090 | return -EINVAL; |
51c1a580 | 12091 | } |
993ac7b5 | 12092 | |
993ac7b5 MC |
12093 | bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); |
12094 | if (!bp->cnic_kwq) | |
12095 | return -ENOMEM; | |
12096 | ||
12097 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
12098 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
12099 | bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; | |
12100 | ||
12101 | bp->cnic_spq_pending = 0; | |
12102 | bp->cnic_kwq_pending = 0; | |
12103 | ||
12104 | bp->cnic_data = data; | |
12105 | ||
12106 | cp->num_irq = 0; | |
619c5cb6 | 12107 | cp->drv_state |= CNIC_DRV_STATE_REGD; |
523224a3 | 12108 | cp->iro_arr = bp->iro_arr; |
993ac7b5 | 12109 | |
993ac7b5 | 12110 | bnx2x_setup_cnic_irq_info(bp); |
c2bff63f | 12111 | |
993ac7b5 MC |
12112 | rcu_assign_pointer(bp->cnic_ops, ops); |
12113 | ||
12114 | return 0; | |
12115 | } | |
12116 | ||
12117 | static int bnx2x_unregister_cnic(struct net_device *dev) | |
12118 | { | |
12119 | struct bnx2x *bp = netdev_priv(dev); | |
12120 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12121 | ||
12122 | mutex_lock(&bp->cnic_mutex); | |
993ac7b5 | 12123 | cp->drv_state = 0; |
2cfa5a04 | 12124 | RCU_INIT_POINTER(bp->cnic_ops, NULL); |
993ac7b5 MC |
12125 | mutex_unlock(&bp->cnic_mutex); |
12126 | synchronize_rcu(); | |
12127 | kfree(bp->cnic_kwq); | |
12128 | bp->cnic_kwq = NULL; | |
12129 | ||
12130 | return 0; | |
12131 | } | |
12132 | ||
12133 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) | |
12134 | { | |
12135 | struct bnx2x *bp = netdev_priv(dev); | |
12136 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12137 | ||
2ba45142 VZ |
12138 | /* If both iSCSI and FCoE are disabled - return NULL in |
12139 | * order to indicate CNIC that it should not try to work | |
12140 | * with this device. | |
12141 | */ | |
12142 | if (NO_ISCSI(bp) && NO_FCOE(bp)) | |
12143 | return NULL; | |
12144 | ||
993ac7b5 MC |
12145 | cp->drv_owner = THIS_MODULE; |
12146 | cp->chip_id = CHIP_ID(bp); | |
12147 | cp->pdev = bp->pdev; | |
12148 | cp->io_base = bp->regview; | |
12149 | cp->io_base2 = bp->doorbells; | |
12150 | cp->max_kwqe_pending = 8; | |
523224a3 | 12151 | cp->ctx_blk_size = CDU_ILT_PAGE_SZ; |
c2bff63f DK |
12152 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
12153 | bnx2x_cid_ilt_lines(bp); | |
993ac7b5 | 12154 | cp->ctx_tbl_len = CNIC_ILT_LINES; |
c2bff63f | 12155 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
993ac7b5 MC |
12156 | cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; |
12157 | cp->drv_ctl = bnx2x_drv_ctl; | |
12158 | cp->drv_register_cnic = bnx2x_register_cnic; | |
12159 | cp->drv_unregister_cnic = bnx2x_unregister_cnic; | |
ec6ba945 | 12160 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; |
619c5cb6 VZ |
12161 | cp->iscsi_l2_client_id = |
12162 | bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
c2bff63f DK |
12163 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; |
12164 | ||
2ba45142 VZ |
12165 | if (NO_ISCSI_OOO(bp)) |
12166 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
12167 | ||
12168 | if (NO_ISCSI(bp)) | |
12169 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; | |
12170 | ||
12171 | if (NO_FCOE(bp)) | |
12172 | cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; | |
12173 | ||
51c1a580 MS |
12174 | BNX2X_DEV_INFO( |
12175 | "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", | |
c2bff63f DK |
12176 | cp->ctx_blk_size, |
12177 | cp->ctx_tbl_offset, | |
12178 | cp->ctx_tbl_len, | |
12179 | cp->starting_cid); | |
993ac7b5 MC |
12180 | return cp; |
12181 | } | |
12182 | EXPORT_SYMBOL(bnx2x_cnic_probe); | |
12183 | ||
12184 | #endif /* BCM_CNIC */ | |
94a78b79 | 12185 |