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bnx2x: Support of PF driver of a VF acquire request
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
85b26ea1 3 * Copyright (c) 2007-2012 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
f1deab50
JP		 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
a2fbb9ea
ET		 20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/device.h> /* for dev_info() */
24#include <linux/timer.h>
25#include <linux/errno.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
a2fbb9ea
ET		 28#include <linux/interrupt.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/dma-mapping.h>
35#include <linux/bitops.h>
36#include <linux/irq.h>
37#include <linux/delay.h>
38#include <asm/byteorder.h>
39#include <linux/time.h>
40#include <linux/ethtool.h>
41#include <linux/mii.h>
0c6671b0 42#include <linux/if_vlan.h>
a2fbb9ea 43#include <net/ip.h>
619c5cb6 44#include <net/ipv6.h>
a2fbb9ea
ET		 45#include <net/tcp.h>
46#include <net/checksum.h>
34f80b04 47#include <net/ip6_checksum.h>
a2fbb9ea
ET		 48#include <linux/workqueue.h>
49#include <linux/crc32.h>
34f80b04 50#include <linux/crc32c.h>
a2fbb9ea
ET		 51#include <linux/prefetch.h>
52#include <linux/zlib.h>
a2fbb9ea 53#include <linux/io.h>
452427b0 54#include <linux/semaphore.h>
45229b42 55#include <linux/stringify.h>
7ab24bfd 56#include <linux/vmalloc.h>
a2fbb9ea 57
a2fbb9ea
ET		 58#include "bnx2x.h"
59#include "bnx2x_init.h"
94a78b79 60#include "bnx2x_init_ops.h"
9f6c9258 61#include "bnx2x_cmn.h"
1ab4434c
AE		 62#include "bnx2x_vfpf.h"
63#include "bnx2x_sriov.h"
e4901dde 64#include "bnx2x_dcb.h"
042181f5 65#include "bnx2x_sp.h"
a2fbb9ea 66
94a78b79
VZ		 67#include <linux/firmware.h>
68#include "bnx2x_fw_file_hdr.h"
69/* FW files */
45229b42
BH		 70#define FW_FILE_VERSION \
71 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
72 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
73 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
74 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 75#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
76#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 77#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 78
2e499d3c
BW		 79#define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
80
34f80b04
EG		 81/* Time in jiffies before concluding the transmitter is hung */
82#define TX_TIMEOUT (5*HZ)
a2fbb9ea 83
0329aba1 84static char version[] =
619c5cb6 85 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 86 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
87
24e3fcef 88MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 89MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 90 "BCM57710/57711/57711E/"
91 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
92 "57840/57840_MF Driver");
a2fbb9ea
ET		 93MODULE_LICENSE("GPL");
94MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 95MODULE_FIRMWARE(FW_FILE_NAME_E1);
96MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 97MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 98
ca00392c 99
d6214d7a 100int num_queues;
54b9ddaa 101module_param(num_queues, int, 0);
96305234
DK		 102MODULE_PARM_DESC(num_queues,
103 " Set number of queues (default is as a number of CPUs)");
555f6c78 104
19680c48 105static int disable_tpa;
19680c48 106module_param(disable_tpa, int, 0);
9898f86d 107MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 108
9ee3d37b
DK		 109#define INT_MODE_INTx 1
110#define INT_MODE_MSI 2
0e8d2ec5 111int int_mode;
8badd27a 112module_param(int_mode, int, 0);
619c5cb6 113MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 114 "(1 INT#x; 2 MSI)");
8badd27a 115
a18f5128
EG		 116static int dropless_fc;
117module_param(dropless_fc, int, 0);
118MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
119
8d5726c4
EG		 120static int mrrs = -1;
121module_param(mrrs, int, 0);
122MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
123
9898f86d 124static int debug;
a2fbb9ea 125module_param(debug, int, 0);
9898f86d
EG		 126MODULE_PARM_DESC(debug, " Default debug msglevel");
127
a2fbb9ea 128
619c5cb6
VZ		 129
130struct workqueue_struct *bnx2x_wq;
ec6ba945 131
a2fbb9ea
ET		 132enum bnx2x_board_type {
133 BCM57710 = 0,
619c5cb6
VZ		 134 BCM57711,
135 BCM57711E,
136 BCM57712,
137 BCM57712_MF,
1ab4434c 138 BCM57712_VF,
619c5cb6
VZ		 139 BCM57800,
140 BCM57800_MF,
1ab4434c 141 BCM57800_VF,
619c5cb6
VZ		 142 BCM57810,
143 BCM57810_MF,
1ab4434c 144 BCM57810_VF,
c3def943
YM		 145 BCM57840_4_10,
146 BCM57840_2_20,
7e8e02df 147 BCM57840_MF,
1ab4434c 148 BCM57840_VF,
7e8e02df 149 BCM57811,
1ab4434c
AE		 150 BCM57811_MF,
151 BCM57840_O,
152 BCM57840_MFO,
153 BCM57811_VF
a2fbb9ea
ET		 154};
155
34f80b04 156/* indexed by board_type, above */
53a10565 157static struct {
a2fbb9ea 158 char *name;
0329aba1 159} board_info[] = {
1ab4434c
AE		 160 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
161 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
162 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
163 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
164 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
165 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
166 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
167 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
168 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
169 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
170 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
171 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
172 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
173 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
174 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
175 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
176 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
177 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
178 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
179 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
180 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
a2fbb9ea
ET		 181};
182
619c5cb6
VZ		 183#ifndef PCI_DEVICE_ID_NX2_57710
184#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
185#endif
186#ifndef PCI_DEVICE_ID_NX2_57711
187#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
188#endif
189#ifndef PCI_DEVICE_ID_NX2_57711E
190#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
191#endif
192#ifndef PCI_DEVICE_ID_NX2_57712
193#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
194#endif
195#ifndef PCI_DEVICE_ID_NX2_57712_MF
196#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
197#endif
198#ifndef PCI_DEVICE_ID_NX2_57800
199#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
200#endif
201#ifndef PCI_DEVICE_ID_NX2_57800_MF
202#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
203#endif
204#ifndef PCI_DEVICE_ID_NX2_57810
205#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
206#endif
207#ifndef PCI_DEVICE_ID_NX2_57810_MF
208#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
209#endif
c3def943
YM		 210#ifndef PCI_DEVICE_ID_NX2_57840_O
211#define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
212#endif
213#ifndef PCI_DEVICE_ID_NX2_57840_4_10
214#define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
215#endif
216#ifndef PCI_DEVICE_ID_NX2_57840_2_20
217#define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
218#endif
219#ifndef PCI_DEVICE_ID_NX2_57840_MFO
220#define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
619c5cb6
VZ		 221#endif
222#ifndef PCI_DEVICE_ID_NX2_57840_MF
223#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
224#endif
7e8e02df
BW		 225#ifndef PCI_DEVICE_ID_NX2_57811
226#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
227#endif
228#ifndef PCI_DEVICE_ID_NX2_57811_MF
229#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
230#endif
a3aa1884 231static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 232 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
233 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
234 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 235 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6
VZ		 236 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
237 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
238 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
239 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
240 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
c3def943
YM		 241 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
242 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
243 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
244 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
619c5cb6 245 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
7e8e02df
BW		 246 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
247 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
a2fbb9ea
ET		 248 { 0 }
249};
250
251MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
252
452427b0
YM		 253/* Global resources for unloading a previously loaded device */
254#define BNX2X_PREV_WAIT_NEEDED 1
255static DEFINE_SEMAPHORE(bnx2x_prev_sem);
256static LIST_HEAD(bnx2x_prev_list);
a2fbb9ea
ET		 257/****************************************************************************
258* General service functions
259****************************************************************************/
260
1191cb83 261static void __storm_memset_dma_mapping(struct bnx2x *bp,
619c5cb6
VZ		 262 u32 addr, dma_addr_t mapping)
263{
264 REG_WR(bp, addr, U64_LO(mapping));
265 REG_WR(bp, addr + 4, U64_HI(mapping));
266}
267
1191cb83
ED		 268static void storm_memset_spq_addr(struct bnx2x *bp,
269 dma_addr_t mapping, u16 abs_fid)
619c5cb6
VZ		 270{
271 u32 addr = XSEM_REG_FAST_MEMORY +
272 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
273
274 __storm_memset_dma_mapping(bp, addr, mapping);
275}
276
1191cb83
ED		 277static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
278 u16 pf_id)
523224a3 279{
619c5cb6
VZ		 280 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
281 pf_id);
282 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
283 pf_id);
284 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
285 pf_id);
286 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
287 pf_id);
523224a3
DK		 288}
289
1191cb83
ED		 290static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
291 u8 enable)
619c5cb6
VZ		 292{
293 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
294 enable);
295 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
296 enable);
297 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
298 enable);
299 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
300 enable);
301}
523224a3 302
1191cb83
ED		 303static void storm_memset_eq_data(struct bnx2x *bp,
304 struct event_ring_data *eq_data,
523224a3
DK		 305 u16 pfid)
306{
307 size_t size = sizeof(struct event_ring_data);
308
309 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
310
311 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
312}
313
1191cb83
ED		 314static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
315 u16 pfid)
523224a3
DK		 316{
317 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
318 REG_WR16(bp, addr, eq_prod);
319}
320
a2fbb9ea
ET		 321/* used only at init
322 * locking is done by mcp
323 */
8d96286a 324static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 325{
326 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
327 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
328 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
329 PCICFG_VENDOR_ID_OFFSET);
330}
331
a2fbb9ea
ET		 332static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
333{
334 u32 val;
335
336 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
337 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
338 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
339 PCICFG_VENDOR_ID_OFFSET);
340
341 return val;
342}
a2fbb9ea 343
f2e0899f
DK		 344#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
345#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
346#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
347#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
348#define DMAE_DP_DST_NONE "dst_addr [none]"
349
fd1fc79d
AE		 350void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl)
351{
352 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
353
354 switch (dmae->opcode & DMAE_COMMAND_DST) {
355 case DMAE_CMD_DST_PCI:
356 if (src_type == DMAE_CMD_SRC_PCI)
357 DP(msglvl, "DMAE: opcode 0x%08x\n"
358 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
359 "comp_addr [%x:%08x], comp_val 0x%08x\n",
360 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
361 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
362 dmae->comp_addr_hi, dmae->comp_addr_lo,
363 dmae->comp_val);
364 else
365 DP(msglvl, "DMAE: opcode 0x%08x\n"
366 "src [%08x], len [%d*4], dst [%x:%08x]\n"
367 "comp_addr [%x:%08x], comp_val 0x%08x\n",
368 dmae->opcode, dmae->src_addr_lo >> 2,
369 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
370 dmae->comp_addr_hi, dmae->comp_addr_lo,
371 dmae->comp_val);
372 break;
373 case DMAE_CMD_DST_GRC:
374 if (src_type == DMAE_CMD_SRC_PCI)
375 DP(msglvl, "DMAE: opcode 0x%08x\n"
376 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
377 "comp_addr [%x:%08x], comp_val 0x%08x\n",
378 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
379 dmae->len, dmae->dst_addr_lo >> 2,
380 dmae->comp_addr_hi, dmae->comp_addr_lo,
381 dmae->comp_val);
382 else
383 DP(msglvl, "DMAE: opcode 0x%08x\n"
384 "src [%08x], len [%d*4], dst [%08x]\n"
385 "comp_addr [%x:%08x], comp_val 0x%08x\n",
386 dmae->opcode, dmae->src_addr_lo >> 2,
387 dmae->len, dmae->dst_addr_lo >> 2,
388 dmae->comp_addr_hi, dmae->comp_addr_lo,
389 dmae->comp_val);
390 break;
391 default:
392 if (src_type == DMAE_CMD_SRC_PCI)
393 DP(msglvl, "DMAE: opcode 0x%08x\n"
394 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
395 "comp_addr [%x:%08x] comp_val 0x%08x\n",
396 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
397 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
398 dmae->comp_val);
399 else
400 DP(msglvl, "DMAE: opcode 0x%08x\n"
401 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
402 "comp_addr [%x:%08x] comp_val 0x%08x\n",
403 dmae->opcode, dmae->src_addr_lo >> 2,
404 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
405 dmae->comp_val);
406 break;
407 }
408}
f2e0899f 409
a2fbb9ea 410/* copy command into DMAE command memory and set DMAE command go */
6c719d00 411void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 412{
413 u32 cmd_offset;
414 int i;
415
416 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
417 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
418 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 419 }
420 REG_WR(bp, dmae_reg_go_c[idx], 1);
421}
422
f2e0899f 423u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 424{
f2e0899f
DK		 425 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
426 DMAE_CMD_C_ENABLE);
427}
ad8d3948 428
f2e0899f
DK		 429u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
430{
431 return opcode & ~DMAE_CMD_SRC_RESET;
432}
ad8d3948 433
f2e0899f
DK		 434u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
435 bool with_comp, u8 comp_type)
436{
437 u32 opcode = 0;
438
439 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
440 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 441
f2e0899f
DK		 442 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
443
444 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 445 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
446 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 447 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 448
a2fbb9ea 449#ifdef __BIG_ENDIAN
f2e0899f 450 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 451#else
f2e0899f 452 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 453#endif
f2e0899f
DK		 454 if (with_comp)
455 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
456 return opcode;
457}
458
fd1fc79d 459void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
8d96286a 460 struct dmae_command *dmae,
461 u8 src_type, u8 dst_type)
f2e0899f
DK		 462{
463 memset(dmae, 0, sizeof(struct dmae_command));
464
465 /* set the opcode */
466 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
467 true, DMAE_COMP_PCI);
468
469 /* fill in the completion parameters */
470 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
471 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
472 dmae->comp_val = DMAE_COMP_VAL;
473}
474
fd1fc79d
AE		 475/* issue a dmae command over the init-channel and wait for completion */
476int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
f2e0899f
DK		 477{
478 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
5e374b5a 479 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 480 int rc = 0;
481
619c5cb6
VZ		 482 /*
483 * Lock the dmae channel. Disable BHs to prevent a dead-lock
484 * as long as this code is called both from syscall context and
485 * from ndo_set_rx_mode() flow that may be called from BH.
486 */
6e30dd4e 487 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 488
f2e0899f 489 /* reset completion */
a2fbb9ea
ET		 490 *wb_comp = 0;
491
f2e0899f
DK		 492 /* post the command on the channel used for initializations */
493 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 494
f2e0899f 495 /* wait for completion */
a2fbb9ea 496 udelay(5);
f2e0899f 497 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948 498
95c6c616
AE		 499 if (!cnt ||
500 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
501 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
c3eefaf6 502 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 503 rc = DMAE_TIMEOUT;
504 goto unlock;
a2fbb9ea 505 }
ad8d3948 506 cnt--;
f2e0899f 507 udelay(50);
a2fbb9ea 508 }
f2e0899f
DK		 509 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
510 BNX2X_ERR("DMAE PCI error!\n");
511 rc = DMAE_PCI_ERROR;
512 }
513
f2e0899f 514unlock:
6e30dd4e 515 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 516 return rc;
517}
518
519void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
520 u32 len32)
521{
522 struct dmae_command dmae;
523
524 if (!bp->dmae_ready) {
525 u32 *data = bnx2x_sp(bp, wb_data[0]);
526
127a425e
AE		 527 if (CHIP_IS_E1(bp))
528 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
529 else
530 bnx2x_init_str_wr(bp, dst_addr, data, len32);
f2e0899f
DK		 531 return;
532 }
533
534 /* set opcode and fixed command fields */
535 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
536
537 /* fill in addresses and len */
538 dmae.src_addr_lo = U64_LO(dma_addr);
539 dmae.src_addr_hi = U64_HI(dma_addr);
540 dmae.dst_addr_lo = dst_addr >> 2;
541 dmae.dst_addr_hi = 0;
542 dmae.len = len32;
543
f2e0899f
DK		 544 /* issue the command and wait for completion */
545 bnx2x_issue_dmae_with_comp(bp, &dmae);
a2fbb9ea
ET		 546}
547
c18487ee 548void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 549{
5ff7b6d4 550 struct dmae_command dmae;
ad8d3948
EG		 551
552 if (!bp->dmae_ready) {
553 u32 *data = bnx2x_sp(bp, wb_data[0]);
554 int i;
555
51c1a580 556 if (CHIP_IS_E1(bp))
127a425e
AE		 557 for (i = 0; i < len32; i++)
558 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
51c1a580 559 else
127a425e
AE		 560 for (i = 0; i < len32; i++)
561 data[i] = REG_RD(bp, src_addr + i*4);
562
ad8d3948
EG		 563 return;
564 }
565
f2e0899f
DK		 566 /* set opcode and fixed command fields */
567 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 568
f2e0899f 569 /* fill in addresses and len */
5ff7b6d4
EG		 570 dmae.src_addr_lo = src_addr >> 2;
571 dmae.src_addr_hi = 0;
572 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
573 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
574 dmae.len = len32;
ad8d3948 575
f2e0899f
DK		 576 /* issue the command and wait for completion */
577 bnx2x_issue_dmae_with_comp(bp, &dmae);
ad8d3948
EG		 578}
579
8d96286a 580static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
581 u32 addr, u32 len)
573f2035 582{
02e3c6cb 583 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 584 int offset = 0;
585
02e3c6cb 586 while (len > dmae_wr_max) {
573f2035 587 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 588 addr + offset, dmae_wr_max);
589 offset += dmae_wr_max * 4;
590 len -= dmae_wr_max;
573f2035
EG		 591 }
592
593 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
594}
595
a2fbb9ea
ET		 596static int bnx2x_mc_assert(struct bnx2x *bp)
597{
a2fbb9ea 598 char last_idx;
34f80b04
EG		 599 int i, rc = 0;
600 u32 row0, row1, row2, row3;
601
602 /* XSTORM */
603 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
604 XSTORM_ASSERT_LIST_INDEX_OFFSET);
605 if (last_idx)
606 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
607
608 /* print the asserts */
609 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
610
611 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
612 XSTORM_ASSERT_LIST_OFFSET(i));
613 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
614 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
615 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
616 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
617 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
618 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
619
620 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 621 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 622 i, row3, row2, row1, row0);
623 rc++;
624 } else {
625 break;
626 }
627 }
628
629 /* TSTORM */
630 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
631 TSTORM_ASSERT_LIST_INDEX_OFFSET);
632 if (last_idx)
633 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
634
635 /* print the asserts */
636 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
637
638 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
639 TSTORM_ASSERT_LIST_OFFSET(i));
640 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
641 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
642 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
643 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
644 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
645 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
646
647 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 648 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 649 i, row3, row2, row1, row0);
650 rc++;
651 } else {
652 break;
653 }
654 }
655
656 /* CSTORM */
657 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
658 CSTORM_ASSERT_LIST_INDEX_OFFSET);
659 if (last_idx)
660 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
661
662 /* print the asserts */
663 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
664
665 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
666 CSTORM_ASSERT_LIST_OFFSET(i));
667 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
668 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
669 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
670 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
671 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
672 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
673
674 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 675 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 676 i, row3, row2, row1, row0);
677 rc++;
678 } else {
679 break;
680 }
681 }
682
683 /* USTORM */
684 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
685 USTORM_ASSERT_LIST_INDEX_OFFSET);
686 if (last_idx)
687 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
688
689 /* print the asserts */
690 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
691
692 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
693 USTORM_ASSERT_LIST_OFFSET(i));
694 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
695 USTORM_ASSERT_LIST_OFFSET(i) + 4);
696 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
697 USTORM_ASSERT_LIST_OFFSET(i) + 8);
698 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
699 USTORM_ASSERT_LIST_OFFSET(i) + 12);
700
701 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 702 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 703 i, row3, row2, row1, row0);
704 rc++;
705 } else {
706 break;
a2fbb9ea
ET		 707 }
708 }
34f80b04 709
a2fbb9ea
ET		 710 return rc;
711}
c14423fe 712
7a25cc73 713void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 714{
7a25cc73 715 u32 addr, val;
a2fbb9ea 716 u32 mark, offset;
4781bfad 717 __be32 data[9];
a2fbb9ea 718 int word;
f2e0899f 719 u32 trace_shmem_base;
2145a920
VZ		 720 if (BP_NOMCP(bp)) {
721 BNX2X_ERR("NO MCP - can not dump\n");
722 return;
723 }
7a25cc73
DK		 724 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
725 (bp->common.bc_ver & 0xff0000) >> 16,
726 (bp->common.bc_ver & 0xff00) >> 8,
727 (bp->common.bc_ver & 0xff));
728
729 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
730 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
51c1a580 731 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 732
f2e0899f
DK		 733 if (BP_PATH(bp) == 0)
734 trace_shmem_base = bp->common.shmem_base;
735 else
736 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
de128804
DK		 737 addr = trace_shmem_base - 0x800;
738
739 /* validate TRCB signature */
740 mark = REG_RD(bp, addr);
741 if (mark != MFW_TRACE_SIGNATURE) {
742 BNX2X_ERR("Trace buffer signature is missing.");
743 return ;
744 }
745
746 /* read cyclic buffer pointer */
747 addr += 4;
cdaa7cb8 748 mark = REG_RD(bp, addr);
f2e0899f
DK		 749 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
750 + ((mark + 0x3) & ~0x3) - 0x08000000;
7a25cc73 751 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 752
7a25cc73 753 printk("%s", lvl);
f2e0899f 754 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 755 for (word = 0; word < 8; word++)
cdaa7cb8 756 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 757 data[8] = 0x0;
7995c64e 758 pr_cont("%s", (char *)data);
a2fbb9ea 759 }
cdaa7cb8 760 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 761 for (word = 0; word < 8; word++)
cdaa7cb8 762 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 763 data[8] = 0x0;
7995c64e 764 pr_cont("%s", (char *)data);
a2fbb9ea 765 }
7a25cc73
DK		 766 printk("%s" "end of fw dump\n", lvl);
767}
768
1191cb83 769static void bnx2x_fw_dump(struct bnx2x *bp)
7a25cc73
DK		 770{
771 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 772}
773
6c719d00 774void bnx2x_panic_dump(struct bnx2x *bp)
a2fbb9ea
ET		 775{
776 int i;
523224a3
DK		 777 u16 j;
778 struct hc_sp_status_block_data sp_sb_data;
779 int func = BP_FUNC(bp);
780#ifdef BNX2X_STOP_ON_ERROR
781 u16 start = 0, end = 0;
6383c0b3 782 u8 cos;
523224a3 783#endif
a2fbb9ea 784
66e855f3 785 bp->stats_state = STATS_STATE_DISABLED;
7a752993 786 bp->eth_stats.unrecoverable_error++;
66e855f3
YG		 787 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
788
a2fbb9ea
ET		 789 BNX2X_ERR("begin crash dump -----------------\n");
790
8440d2b6
EG		 791 /* Indices */
792 /* Common */
51c1a580 793 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
619c5cb6
VZ		 794 bp->def_idx, bp->def_att_idx, bp->attn_state,
795 bp->spq_prod_idx, bp->stats_counter);
523224a3
DK		 796 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
797 bp->def_status_blk->atten_status_block.attn_bits,
798 bp->def_status_blk->atten_status_block.attn_bits_ack,
799 bp->def_status_blk->atten_status_block.status_block_id,
800 bp->def_status_blk->atten_status_block.attn_bits_index);
801 BNX2X_ERR(" def (");
802 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
803 pr_cont("0x%x%s",
f1deab50
JP		 804 bp->def_status_blk->sp_sb.index_values[i],
805 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
523224a3
DK		 806
807 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
808 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
809 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
810 i*sizeof(u32));
811
f1deab50 812 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
523224a3
DK		 813 sp_sb_data.igu_sb_id,
814 sp_sb_data.igu_seg_id,
815 sp_sb_data.p_func.pf_id,
816 sp_sb_data.p_func.vnic_id,
817 sp_sb_data.p_func.vf_id,
619c5cb6
VZ		 818 sp_sb_data.p_func.vf_valid,
819 sp_sb_data.state);
523224a3 820
8440d2b6 821
ec6ba945 822 for_each_eth_queue(bp, i) {
a2fbb9ea 823 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 824 int loop;
f2e0899f 825 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 826 struct hc_status_block_data_e1x sb_data_e1x;
827 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 828 CHIP_IS_E1x(bp) ?
829 sb_data_e1x.common.state_machine :
830 sb_data_e2.common.state_machine;
523224a3 831 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 832 CHIP_IS_E1x(bp) ?
833 sb_data_e1x.index_data :
834 sb_data_e2.index_data;
6383c0b3 835 u8 data_size, cos;
523224a3 836 u32 *sb_data_p;
6383c0b3 837 struct bnx2x_fp_txdata txdata;
523224a3
DK		 838
839 /* Rx */
51c1a580 840 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 841 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 842 fp->rx_comp_prod,
66e855f3 843 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
51c1a580 844 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
8440d2b6 845 fp->rx_sge_prod, fp->last_max_sge,
523224a3 846 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 847
523224a3 848 /* Tx */
6383c0b3
AE		 849 for_each_cos_in_tx_queue(fp, cos)
850 {
65565884 851 txdata = *fp->txdata_ptr[cos];
51c1a580 852 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
6383c0b3
AE		 853 i, txdata.tx_pkt_prod,
854 txdata.tx_pkt_cons, txdata.tx_bd_prod,
855 txdata.tx_bd_cons,
856 le16_to_cpu(*txdata.tx_cons_sb));
857 }
523224a3 858
619c5cb6
VZ		 859 loop = CHIP_IS_E1x(bp) ?
860 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 861
862 /* host sb data */
863
ec6ba945
VZ		 864 if (IS_FCOE_FP(fp))
865 continue;
55c11941 866
523224a3
DK		 867 BNX2X_ERR(" run indexes (");
868 for (j = 0; j < HC_SB_MAX_SM; j++)
869 pr_cont("0x%x%s",
870 fp->sb_running_index[j],
871 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
872
873 BNX2X_ERR(" indexes (");
874 for (j = 0; j < loop; j++)
875 pr_cont("0x%x%s",
876 fp->sb_index_values[j],
877 (j == loop - 1) ? ")" : " ");
878 /* fw sb data */
619c5cb6
VZ		 879 data_size = CHIP_IS_E1x(bp) ?
880 sizeof(struct hc_status_block_data_e1x) :
881 sizeof(struct hc_status_block_data_e2);
523224a3 882 data_size /= sizeof(u32);
619c5cb6
VZ		 883 sb_data_p = CHIP_IS_E1x(bp) ?
884 (u32 *)&sb_data_e1x :
885 (u32 *)&sb_data_e2;
523224a3
DK		 886 /* copy sb data in here */
887 for (j = 0; j < data_size; j++)
888 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
889 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
890 j * sizeof(u32));
891
619c5cb6 892 if (!CHIP_IS_E1x(bp)) {
51c1a580 893 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 894 sb_data_e2.common.p_func.pf_id,
895 sb_data_e2.common.p_func.vf_id,
896 sb_data_e2.common.p_func.vf_valid,
897 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 898 sb_data_e2.common.same_igu_sb_1b,
899 sb_data_e2.common.state);
f2e0899f 900 } else {
51c1a580 901 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 902 sb_data_e1x.common.p_func.pf_id,
903 sb_data_e1x.common.p_func.vf_id,
904 sb_data_e1x.common.p_func.vf_valid,
905 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 906 sb_data_e1x.common.same_igu_sb_1b,
907 sb_data_e1x.common.state);
f2e0899f 908 }
523224a3
DK		 909
910 /* SB_SMs data */
911 for (j = 0; j < HC_SB_MAX_SM; j++) {
51c1a580
MS		 912 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
913 j, hc_sm_p[j].__flags,
914 hc_sm_p[j].igu_sb_id,
915 hc_sm_p[j].igu_seg_id,
916 hc_sm_p[j].time_to_expire,
917 hc_sm_p[j].timer_value);
523224a3
DK		 918 }
919
920 /* Indecies data */
921 for (j = 0; j < loop; j++) {
51c1a580 922 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
523224a3
DK		 923 hc_index_p[j].flags,
924 hc_index_p[j].timeout);
925 }
8440d2b6 926 }
a2fbb9ea 927
523224a3 928#ifdef BNX2X_STOP_ON_ERROR
8440d2b6
EG		 929 /* Rings */
930 /* Rx */
55c11941 931 for_each_valid_rx_queue(bp, i) {
8440d2b6 932 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 933
934 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
935 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 936 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 937 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
938 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
939
c3eefaf6 940 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
44151acb 941 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
a2fbb9ea
ET		 942 }
943
3196a88a
EG		 944 start = RX_SGE(fp->rx_sge_prod);
945 end = RX_SGE(fp->last_max_sge);
8440d2b6 946 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 947 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
948 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
949
c3eefaf6
EG		 950 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
951 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 952 }
953
a2fbb9ea
ET		 954 start = RCQ_BD(fp->rx_comp_cons - 10);
955 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 956 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 957 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
958
c3eefaf6
EG		 959 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
960 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 961 }
962 }
963
8440d2b6 964 /* Tx */
55c11941 965 for_each_valid_tx_queue(bp, i) {
8440d2b6 966 struct bnx2x_fastpath *fp = &bp->fp[i];
6383c0b3 967 for_each_cos_in_tx_queue(fp, cos) {
65565884 968 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
6383c0b3
AE		 969
970 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
971 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
972 for (j = start; j != end; j = TX_BD(j + 1)) {
973 struct sw_tx_bd *sw_bd =
974 &txdata->tx_buf_ring[j];
975
51c1a580 976 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
6383c0b3
AE		 977 i, cos, j, sw_bd->skb,
978 sw_bd->first_bd);
979 }
8440d2b6 980
6383c0b3
AE		 981 start = TX_BD(txdata->tx_bd_cons - 10);
982 end = TX_BD(txdata->tx_bd_cons + 254);
983 for (j = start; j != end; j = TX_BD(j + 1)) {
984 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 985
51c1a580 986 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
6383c0b3
AE		 987 i, cos, j, tx_bd[0], tx_bd[1],
988 tx_bd[2], tx_bd[3]);
989 }
8440d2b6
EG		 990 }
991 }
523224a3 992#endif
34f80b04 993 bnx2x_fw_dump(bp);
a2fbb9ea
ET		 994 bnx2x_mc_assert(bp);
995 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 996}
997
619c5cb6
VZ		 998/*
999 * FLR Support for E2
1000 *
1001 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1002 * initialization.
1003 */
1004#define FLR_WAIT_USEC 10000 /* 10 miliseconds */
89db4ad8
AE		 1005#define FLR_WAIT_INTERVAL 50 /* usec */
1006#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
619c5cb6
VZ		 1007
1008struct pbf_pN_buf_regs {
1009 int pN;
1010 u32 init_crd;
1011 u32 crd;
1012 u32 crd_freed;
1013};
1014
1015struct pbf_pN_cmd_regs {
1016 int pN;
1017 u32 lines_occup;
1018 u32 lines_freed;
1019};
1020
1021static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1022 struct pbf_pN_buf_regs *regs,
1023 u32 poll_count)
1024{
1025 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1026 u32 cur_cnt = poll_count;
1027
1028 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1029 crd = crd_start = REG_RD(bp, regs->crd);
1030 init_crd = REG_RD(bp, regs->init_crd);
1031
1032 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1033 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1034 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1035
1036 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1037 (init_crd - crd_start))) {
1038 if (cur_cnt--) {
89db4ad8 1039 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1040 crd = REG_RD(bp, regs->crd);
1041 crd_freed = REG_RD(bp, regs->crd_freed);
1042 } else {
1043 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1044 regs->pN);
1045 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1046 regs->pN, crd);
1047 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1048 regs->pN, crd_freed);
1049 break;
1050 }
1051 }
1052 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
89db4ad8 1053 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1054}
1055
1056static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1057 struct pbf_pN_cmd_regs *regs,
1058 u32 poll_count)
1059{
1060 u32 occup, to_free, freed, freed_start;
1061 u32 cur_cnt = poll_count;
1062
1063 occup = to_free = REG_RD(bp, regs->lines_occup);
1064 freed = freed_start = REG_RD(bp, regs->lines_freed);
1065
1066 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1067 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1068
1069 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1070 if (cur_cnt--) {
89db4ad8 1071 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1072 occup = REG_RD(bp, regs->lines_occup);
1073 freed = REG_RD(bp, regs->lines_freed);
1074 } else {
1075 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1076 regs->pN);
1077 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1078 regs->pN, occup);
1079 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1080 regs->pN, freed);
1081 break;
1082 }
1083 }
1084 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
89db4ad8 1085 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1086}
1087
1191cb83
ED		 1088static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1089 u32 expected, u32 poll_count)
619c5cb6
VZ		 1090{
1091 u32 cur_cnt = poll_count;
1092 u32 val;
1093
1094 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
89db4ad8 1095 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1096
1097 return val;
1098}
1099
1191cb83
ED		 1100static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1101 char *msg, u32 poll_cnt)
619c5cb6
VZ		 1102{
1103 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1104 if (val != 0) {
1105 BNX2X_ERR("%s usage count=%d\n", msg, val);
1106 return 1;
1107 }
1108 return 0;
1109}
1110
1111static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1112{
1113 /* adjust polling timeout */
1114 if (CHIP_REV_IS_EMUL(bp))
1115 return FLR_POLL_CNT * 2000;
1116
1117 if (CHIP_REV_IS_FPGA(bp))
1118 return FLR_POLL_CNT * 120;
1119
1120 return FLR_POLL_CNT;
1121}
1122
1123static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1124{
1125 struct pbf_pN_cmd_regs cmd_regs[] = {
1126 {0, (CHIP_IS_E3B0(bp)) ?
1127 PBF_REG_TQ_OCCUPANCY_Q0 :
1128 PBF_REG_P0_TQ_OCCUPANCY,
1129 (CHIP_IS_E3B0(bp)) ?
1130 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1131 PBF_REG_P0_TQ_LINES_FREED_CNT},
1132 {1, (CHIP_IS_E3B0(bp)) ?
1133 PBF_REG_TQ_OCCUPANCY_Q1 :
1134 PBF_REG_P1_TQ_OCCUPANCY,
1135 (CHIP_IS_E3B0(bp)) ?
1136 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1137 PBF_REG_P1_TQ_LINES_FREED_CNT},
1138 {4, (CHIP_IS_E3B0(bp)) ?
1139 PBF_REG_TQ_OCCUPANCY_LB_Q :
1140 PBF_REG_P4_TQ_OCCUPANCY,
1141 (CHIP_IS_E3B0(bp)) ?
1142 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1143 PBF_REG_P4_TQ_LINES_FREED_CNT}
1144 };
1145
1146 struct pbf_pN_buf_regs buf_regs[] = {
1147 {0, (CHIP_IS_E3B0(bp)) ?
1148 PBF_REG_INIT_CRD_Q0 :
1149 PBF_REG_P0_INIT_CRD ,
1150 (CHIP_IS_E3B0(bp)) ?
1151 PBF_REG_CREDIT_Q0 :
1152 PBF_REG_P0_CREDIT,
1153 (CHIP_IS_E3B0(bp)) ?
1154 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1155 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1156 {1, (CHIP_IS_E3B0(bp)) ?
1157 PBF_REG_INIT_CRD_Q1 :
1158 PBF_REG_P1_INIT_CRD,
1159 (CHIP_IS_E3B0(bp)) ?
1160 PBF_REG_CREDIT_Q1 :
1161 PBF_REG_P1_CREDIT,
1162 (CHIP_IS_E3B0(bp)) ?
1163 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1164 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1165 {4, (CHIP_IS_E3B0(bp)) ?
1166 PBF_REG_INIT_CRD_LB_Q :
1167 PBF_REG_P4_INIT_CRD,
1168 (CHIP_IS_E3B0(bp)) ?
1169 PBF_REG_CREDIT_LB_Q :
1170 PBF_REG_P4_CREDIT,
1171 (CHIP_IS_E3B0(bp)) ?
1172 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1173 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1174 };
1175
1176 int i;
1177
1178 /* Verify the command queues are flushed P0, P1, P4 */
1179 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1180 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1181
1182
1183 /* Verify the transmission buffers are flushed P0, P1, P4 */
1184 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1185 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1186}
1187
1188#define OP_GEN_PARAM(param) \
1189 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1190
1191#define OP_GEN_TYPE(type) \
1192 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1193
1194#define OP_GEN_AGG_VECT(index) \
1195 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1196
1197
1191cb83 1198static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
619c5cb6
VZ		 1199 u32 poll_cnt)
1200{
1201 struct sdm_op_gen op_gen = {0};
1202
1203 u32 comp_addr = BAR_CSTRORM_INTMEM +
1204 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1205 int ret = 0;
1206
1207 if (REG_RD(bp, comp_addr)) {
89db4ad8 1208 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
619c5cb6
VZ		 1209 return 1;
1210 }
1211
1212 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1213 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1214 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1215 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1216
89db4ad8 1217 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
619c5cb6
VZ		 1218 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1219
1220 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1221 BNX2X_ERR("FW final cleanup did not succeed\n");
51c1a580
MS		 1222 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1223 (REG_RD(bp, comp_addr)));
619c5cb6
VZ		 1224 ret = 1;
1225 }
1226 /* Zero completion for nxt FLR */
1227 REG_WR(bp, comp_addr, 0);
1228
1229 return ret;
1230}
1231
b56e9670 1232u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
619c5cb6 1233{
619c5cb6
VZ		 1234 u16 status;
1235
2a80eebc 1236 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
619c5cb6
VZ		 1237 return status & PCI_EXP_DEVSTA_TRPND;
1238}
1239
1240/* PF FLR specific routines
1241*/
1242static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1243{
1244
1245 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1246 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1247 CFC_REG_NUM_LCIDS_INSIDE_PF,
1248 "CFC PF usage counter timed out",
1249 poll_cnt))
1250 return 1;
1251
1252
1253 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1254 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1255 DORQ_REG_PF_USAGE_CNT,
1256 "DQ PF usage counter timed out",
1257 poll_cnt))
1258 return 1;
1259
1260 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1261 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1262 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1263 "QM PF usage counter timed out",
1264 poll_cnt))
1265 return 1;
1266
1267 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1268 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1269 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1270 "Timers VNIC usage counter timed out",
1271 poll_cnt))
1272 return 1;
1273 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1274 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1275 "Timers NUM_SCANS usage counter timed out",
1276 poll_cnt))
1277 return 1;
1278
1279 /* Wait DMAE PF usage counter to zero */
1280 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1281 dmae_reg_go_c[INIT_DMAE_C(bp)],
1282 "DMAE dommand register timed out",
1283 poll_cnt))
1284 return 1;
1285
1286 return 0;
1287}
1288
1289static void bnx2x_hw_enable_status(struct bnx2x *bp)
1290{
1291 u32 val;
1292
1293 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1294 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1295
1296 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1297 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1298
1299 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1300 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1301
1302 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1303 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1304
1305 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1306 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1307
1308 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1309 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1310
1311 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1312 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1313
1314 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1315 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1316 val);
1317}
1318
1319static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1320{
1321 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1322
1323 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1324
1325 /* Re-enable PF target read access */
1326 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1327
1328 /* Poll HW usage counters */
89db4ad8 1329 DP(BNX2X_MSG_SP, "Polling usage counters\n");
619c5cb6
VZ		 1330 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1331 return -EBUSY;
1332
1333 /* Zero the igu 'trailing edge' and 'leading edge' */
1334
1335 /* Send the FW cleanup command */
1336 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1337 return -EBUSY;
1338
1339 /* ATC cleanup */
1340
1341 /* Verify TX hw is flushed */
1342 bnx2x_tx_hw_flushed(bp, poll_cnt);
1343
1344 /* Wait 100ms (not adjusted according to platform) */
1345 msleep(100);
1346
1347 /* Verify no pending pci transactions */
1348 if (bnx2x_is_pcie_pending(bp->pdev))
1349 BNX2X_ERR("PCIE Transactions still pending\n");
1350
1351 /* Debug */
1352 bnx2x_hw_enable_status(bp);
1353
1354 /*
1355 * Master enable - Due to WB DMAE writes performed before this
1356 * register is re-initialized as part of the regular function init
1357 */
1358 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1359
1360 return 0;
1361}
1362
f2e0899f 1363static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1364{
34f80b04 1365 int port = BP_PORT(bp);
a2fbb9ea
ET		 1366 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1367 u32 val = REG_RD(bp, addr);
69c326b3
DK		 1368 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1369 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1370 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
a2fbb9ea
ET		 1371
1372 if (msix) {
8badd27a
EG		 1373 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1374 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1375 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1376 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
69c326b3
DK		 1377 if (single_msix)
1378 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
8badd27a
EG		 1379 } else if (msi) {
1380 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1381 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1382 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1383 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1384 } else {
1385 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1386 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1387 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1388 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1389
a0fd065c 1390 if (!CHIP_IS_E1(bp)) {
51c1a580
MS		 1391 DP(NETIF_MSG_IFUP,
1392 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
615f8fd9 1393
a0fd065c 1394 REG_WR(bp, addr, val);
615f8fd9 1395
a0fd065c
DK		 1396 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1397 }
a2fbb9ea
ET		 1398 }
1399
a0fd065c
DK		 1400 if (CHIP_IS_E1(bp))
1401 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1402
51c1a580
MS		 1403 DP(NETIF_MSG_IFUP,
1404 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1405 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1406
1407 REG_WR(bp, addr, val);
37dbbf32
EG		 1408 /*
1409 * Ensure that HC_CONFIG is written before leading/trailing edge config
1410 */
1411 mmiowb();
1412 barrier();
34f80b04 1413
f2e0899f 1414 if (!CHIP_IS_E1(bp)) {
34f80b04 1415 /* init leading/trailing edge */
fb3bff17 1416 if (IS_MF(bp)) {
3395a033 1417 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1418 if (bp->port.pmf)
4acac6a5
EG		 1419 /* enable nig and gpio3 attention */
1420 val |= 0x1100;
34f80b04
EG		 1421 } else
1422 val = 0xffff;
1423
1424 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1425 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1426 }
37dbbf32
EG		 1427
1428 /* Make sure that interrupts are indeed enabled from here on */
1429 mmiowb();
a2fbb9ea
ET		 1430}
1431
f2e0899f
DK		 1432static void bnx2x_igu_int_enable(struct bnx2x *bp)
1433{
1434 u32 val;
30a5de77
DK		 1435 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1436 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1437 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
f2e0899f
DK		 1438
1439 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1440
1441 if (msix) {
1442 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1443 IGU_PF_CONF_SINGLE_ISR_EN);
1444 val |= (IGU_PF_CONF_FUNC_EN |
1445 IGU_PF_CONF_MSI_MSIX_EN |
1446 IGU_PF_CONF_ATTN_BIT_EN);
30a5de77
DK		 1447
1448 if (single_msix)
1449 val |= IGU_PF_CONF_SINGLE_ISR_EN;
f2e0899f
DK		 1450 } else if (msi) {
1451 val &= ~IGU_PF_CONF_INT_LINE_EN;
1452 val |= (IGU_PF_CONF_FUNC_EN |
1453 IGU_PF_CONF_MSI_MSIX_EN |
1454 IGU_PF_CONF_ATTN_BIT_EN |
1455 IGU_PF_CONF_SINGLE_ISR_EN);
1456 } else {
1457 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1458 val |= (IGU_PF_CONF_FUNC_EN |
1459 IGU_PF_CONF_INT_LINE_EN |
1460 IGU_PF_CONF_ATTN_BIT_EN |
1461 IGU_PF_CONF_SINGLE_ISR_EN);
1462 }
1463
51c1a580 1464 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
f2e0899f
DK		 1465 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1466
1467 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1468
79a8557a
YM		 1469 if (val & IGU_PF_CONF_INT_LINE_EN)
1470 pci_intx(bp->pdev, true);
1471
f2e0899f
DK		 1472 barrier();
1473
1474 /* init leading/trailing edge */
1475 if (IS_MF(bp)) {
3395a033 1476 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1477 if (bp->port.pmf)
1478 /* enable nig and gpio3 attention */
1479 val |= 0x1100;
1480 } else
1481 val = 0xffff;
1482
1483 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1484 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1485
1486 /* Make sure that interrupts are indeed enabled from here on */
1487 mmiowb();
1488}
1489
1490void bnx2x_int_enable(struct bnx2x *bp)
1491{
1492 if (bp->common.int_block == INT_BLOCK_HC)
1493 bnx2x_hc_int_enable(bp);
1494 else
1495 bnx2x_igu_int_enable(bp);
1496}
1497
1498static void bnx2x_hc_int_disable(struct bnx2x *bp)
a2fbb9ea 1499{
34f80b04 1500 int port = BP_PORT(bp);
a2fbb9ea
ET		 1501 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1502 u32 val = REG_RD(bp, addr);
1503
a0fd065c
DK		 1504 /*
1505 * in E1 we must use only PCI configuration space to disable
1506 * MSI/MSIX capablility
1507 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1508 */
1509 if (CHIP_IS_E1(bp)) {
1510 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1511 * Use mask register to prevent from HC sending interrupts
1512 * after we exit the function
1513 */
1514 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1515
1516 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1517 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1518 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1519 } else
1520 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1521 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1522 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1523 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea 1524
51c1a580
MS		 1525 DP(NETIF_MSG_IFDOWN,
1526 "write %x to HC %d (addr 0x%x)\n",
a2fbb9ea
ET		 1527 val, port, addr);
1528
8badd27a
EG		 1529 /* flush all outstanding writes */
1530 mmiowb();
1531
a2fbb9ea
ET		 1532 REG_WR(bp, addr, val);
1533 if (REG_RD(bp, addr) != val)
1534 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1535}
1536
f2e0899f
DK		 1537static void bnx2x_igu_int_disable(struct bnx2x *bp)
1538{
1539 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1540
1541 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1542 IGU_PF_CONF_INT_LINE_EN |
1543 IGU_PF_CONF_ATTN_BIT_EN);
1544
51c1a580 1545 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
f2e0899f
DK		 1546
1547 /* flush all outstanding writes */
1548 mmiowb();
1549
1550 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1551 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1552 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1553}
1554
910cc727 1555static void bnx2x_int_disable(struct bnx2x *bp)
f2e0899f
DK		 1556{
1557 if (bp->common.int_block == INT_BLOCK_HC)
1558 bnx2x_hc_int_disable(bp);
1559 else
1560 bnx2x_igu_int_disable(bp);
1561}
1562
9f6c9258 1563void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1564{
a2fbb9ea 1565 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1566 int i, offset;
a2fbb9ea 1567
f8ef6e44
YG		 1568 if (disable_hw)
1569 /* prevent the HW from sending interrupts */
1570 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1571
1572 /* make sure all ISRs are done */
1573 if (msix) {
8badd27a
EG		 1574 synchronize_irq(bp->msix_table[0].vector);
1575 offset = 1;
55c11941
MS		 1576 if (CNIC_SUPPORT(bp))
1577 offset++;
ec6ba945 1578 for_each_eth_queue(bp, i)
754a2f52 1579 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1580 } else
1581 synchronize_irq(bp->pdev->irq);
1582
1583 /* make sure sp_task is not running */
1cf167f2 1584 cancel_delayed_work(&bp->sp_task);
3deb8167 1585 cancel_delayed_work(&bp->period_task);
1cf167f2 1586 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1587}
1588
34f80b04 1589/* fast path */
a2fbb9ea
ET		 1590
1591/*
34f80b04 1592 * General service functions
a2fbb9ea
ET		 1593 */
1594
72fd0718
VZ		 1595/* Return true if succeeded to acquire the lock */
1596static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1597{
1598 u32 lock_status;
1599 u32 resource_bit = (1 << resource);
1600 int func = BP_FUNC(bp);
1601 u32 hw_lock_control_reg;
1602
51c1a580
MS		 1603 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1604 "Trying to take a lock on resource %d\n", resource);
72fd0718
VZ		 1605
1606 /* Validating that the resource is within range */
1607 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1608 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
72fd0718
VZ		 1609 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1610 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1611 return false;
72fd0718
VZ		 1612 }
1613
1614 if (func <= 5)
1615 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1616 else
1617 hw_lock_control_reg =
1618 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1619
1620 /* Try to acquire the lock */
1621 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1622 lock_status = REG_RD(bp, hw_lock_control_reg);
1623 if (lock_status & resource_bit)
1624 return true;
1625
51c1a580
MS		 1626 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1627 "Failed to get a lock on resource %d\n", resource);
72fd0718
VZ		 1628 return false;
1629}
1630
c9ee9206
VZ		 1631/**
1632 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1633 *
1634 * @bp: driver handle
1635 *
1636 * Returns the recovery leader resource id according to the engine this function
1637 * belongs to. Currently only only 2 engines is supported.
1638 */
1191cb83 1639static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
c9ee9206
VZ		 1640{
1641 if (BP_PATH(bp))
1642 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1643 else
1644 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1645}
1646
1647/**
1648 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1649 *
1650 * @bp: driver handle
1651 *
1191cb83 1652 * Tries to aquire a leader lock for current engine.
c9ee9206 1653 */
1191cb83 1654static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
c9ee9206
VZ		 1655{
1656 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1657}
1658
619c5cb6 1659static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
55c11941 1660
fd1fc79d
AE		 1661/* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1662static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1663{
1664 /* Set the interrupt occurred bit for the sp-task to recognize it
1665 * must ack the interrupt and transition according to the IGU
1666 * state machine.
1667 */
1668 atomic_set(&bp->interrupt_occurred, 1);
1669
1670 /* The sp_task must execute only after this bit
1671 * is set, otherwise we will get out of sync and miss all
1672 * further interrupts. Hence, the barrier.
1673 */
1674 smp_wmb();
1675
1676 /* schedule sp_task to workqueue */
1677 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1678}
3196a88a 1679
619c5cb6 1680void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1681{
1682 struct bnx2x *bp = fp->bp;
1683 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1684 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6 1685 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
15192a8c 1686 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a2fbb9ea 1687
34f80b04 1688 DP(BNX2X_MSG_SP,
a2fbb9ea 1689 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1690 fp->index, cid, command, bp->state,
34f80b04 1691 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1692
fd1fc79d
AE		 1693 /* If cid is within VF range, replace the slowpath object with the
1694 * one corresponding to this VF
1695 */
1696 if (cid >= BNX2X_FIRST_VF_CID &&
1697 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1698 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1699
619c5cb6
VZ		 1700 switch (command) {
1701 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1702 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1703 drv_cmd = BNX2X_Q_CMD_UPDATE;
1704 break;
d6cae238 1705
619c5cb6 1706 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1707 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1708 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1709 break;
1710
6383c0b3 1711 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
51c1a580 1712 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
6383c0b3
AE		 1713 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1714 break;
1715
619c5cb6 1716 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1717 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1718 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1719 break;
1720
619c5cb6 1721 case (RAMROD_CMD_ID_ETH_TERMINATE):
d6cae238 1722 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
619c5cb6 1723 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1724 break;
1725
619c5cb6 1726 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1727 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1728 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1729 break;
619c5cb6
VZ		 1730
1731 default:
1732 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1733 command, fp->index);
1734 return;
523224a3 1735 }
3196a88a 1736
619c5cb6
VZ		 1737 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1738 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1739 /* q_obj->complete_cmd() failure means that this was
1740 * an unexpected completion.
1741 *
1742 * In this case we don't want to increase the bp->spq_left
1743 * because apparently we haven't sent this command the first
1744 * place.
1745 */
1746#ifdef BNX2X_STOP_ON_ERROR
1747 bnx2x_panic();
1748#else
1749 return;
1750#endif
fd1fc79d
AE		 1751 /* SRIOV: reschedule any 'in_progress' operations */
1752 bnx2x_iov_sp_event(bp, cid, true);
619c5cb6 1753
8fe23fbd 1754 smp_mb__before_atomic_inc();
6e30dd4e 1755 atomic_inc(&bp->cq_spq_left);
619c5cb6
VZ		 1756 /* push the change in bp->spq_left and towards the memory */
1757 smp_mb__after_atomic_inc();
49d66772 1758
d6cae238
VZ		 1759 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1760
a3348722
BW		 1761 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1762 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1763 /* if Q update ramrod is completed for last Q in AFEX vif set
1764 * flow, then ACK MCP at the end
1765 *
1766 * mark pending ACK to MCP bit.
1767 * prevent case that both bits are cleared.
1768 * At the end of load/unload driver checks that
1769 * sp_state is cleaerd, and this order prevents
1770 * races
1771 */
1772 smp_mb__before_clear_bit();
1773 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1774 wmb();
1775 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1776 smp_mb__after_clear_bit();
1777
fd1fc79d
AE		 1778 /* schedule the sp task as mcp ack is required */
1779 bnx2x_schedule_sp_task(bp);
a3348722
BW		 1780 }
1781
523224a3 1782 return;
a2fbb9ea
ET		 1783}
1784
9f6c9258 1785irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1786{
555f6c78 1787 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1788 u16 status = bnx2x_ack_int(bp);
34f80b04 1789 u16 mask;
ca00392c 1790 int i;
6383c0b3 1791 u8 cos;
a2fbb9ea 1792
34f80b04 1793 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1794 if (unlikely(status == 0)) {
1795 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1796 return IRQ_NONE;
1797 }
f5372251 1798 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1799
3196a88a
EG		 1800#ifdef BNX2X_STOP_ON_ERROR
1801 if (unlikely(bp->panic))
1802 return IRQ_HANDLED;
1803#endif
1804
ec6ba945 1805 for_each_eth_queue(bp, i) {
ca00392c 1806 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1807
55c11941 1808 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
ca00392c 1809 if (status & mask) {
619c5cb6 1810 /* Handle Rx or Tx according to SB id */
54b9ddaa 1811 prefetch(fp->rx_cons_sb);
6383c0b3 1812 for_each_cos_in_tx_queue(fp, cos)
65565884 1813 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
523224a3 1814 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1815 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1816 status &= ~mask;
1817 }
a2fbb9ea
ET		 1818 }
1819
55c11941
MS		 1820 if (CNIC_SUPPORT(bp)) {
1821 mask = 0x2;
1822 if (status & (mask | 0x1)) {
1823 struct cnic_ops *c_ops = NULL;
993ac7b5 1824
55c11941
MS		 1825 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1826 rcu_read_lock();
1827 c_ops = rcu_dereference(bp->cnic_ops);
1828 if (c_ops)
1829 c_ops->cnic_handler(bp->cnic_data,
1830 NULL);
1831 rcu_read_unlock();
1832 }
993ac7b5 1833
55c11941
MS		 1834 status &= ~mask;
1835 }
993ac7b5 1836 }
a2fbb9ea 1837
34f80b04 1838 if (unlikely(status & 0x1)) {
fd1fc79d
AE		 1839
1840 /* schedule sp task to perform default status block work, ack
1841 * attentions and enable interrupts.
1842 */
1843 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 1844
1845 status &= ~0x1;
1846 if (!status)
1847 return IRQ_HANDLED;
1848 }
1849
cdaa7cb8
VZ		 1850 if (unlikely(status))
1851 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1852 status);
a2fbb9ea 1853
c18487ee 1854 return IRQ_HANDLED;
a2fbb9ea
ET		 1855}
1856
c18487ee
YR		 1857/* Link */
1858
1859/*
1860 * General service functions
1861 */
a2fbb9ea 1862
9f6c9258 1863int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1864{
1865 u32 lock_status;
1866 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1867 int func = BP_FUNC(bp);
1868 u32 hw_lock_control_reg;
c18487ee 1869 int cnt;
a2fbb9ea 1870
c18487ee
YR		 1871 /* Validating that the resource is within range */
1872 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1873 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 1874 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1875 return -EINVAL;
1876 }
a2fbb9ea 1877
4a37fb66
YG		 1878 if (func <= 5) {
1879 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1880 } else {
1881 hw_lock_control_reg =
1882 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1883 }
1884
c18487ee 1885 /* Validating that the resource is not already taken */
4a37fb66 1886 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 1887 if (lock_status & resource_bit) {
51c1a580 1888 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
c18487ee
YR		 1889 lock_status, resource_bit);
1890 return -EEXIST;
1891 }
a2fbb9ea 1892
46230476
EG		 1893 /* Try for 5 second every 5ms */
1894 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1895 /* Try to acquire the lock */
4a37fb66
YG		 1896 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1897 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1898 if (lock_status & resource_bit)
1899 return 0;
a2fbb9ea 1900
c18487ee 1901 msleep(5);
a2fbb9ea 1902 }
51c1a580 1903 BNX2X_ERR("Timeout\n");
c18487ee
YR		 1904 return -EAGAIN;
1905}
a2fbb9ea 1906
c9ee9206
VZ		 1907int bnx2x_release_leader_lock(struct bnx2x *bp)
1908{
1909 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1910}
1911
9f6c9258 1912int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1913{
1914 u32 lock_status;
1915 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1916 int func = BP_FUNC(bp);
1917 u32 hw_lock_control_reg;
a2fbb9ea 1918
c18487ee
YR		 1919 /* Validating that the resource is within range */
1920 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1921 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 1922 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1923 return -EINVAL;
1924 }
1925
4a37fb66
YG		 1926 if (func <= 5) {
1927 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1928 } else {
1929 hw_lock_control_reg =
1930 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1931 }
1932
c18487ee 1933 /* Validating that the resource is currently taken */
4a37fb66 1934 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 1935 if (!(lock_status & resource_bit)) {
51c1a580 1936 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
c18487ee
YR		 1937 lock_status, resource_bit);
1938 return -EFAULT;
a2fbb9ea
ET		 1939 }
1940
9f6c9258
DK		 1941 REG_WR(bp, hw_lock_control_reg, resource_bit);
1942 return 0;
c18487ee 1943}
a2fbb9ea 1944
9f6c9258 1945
4acac6a5
EG		 1946int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1947{
1948 /* The GPIO should be swapped if swap register is set and active */
1949 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1950 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1951 int gpio_shift = gpio_num +
1952 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1953 u32 gpio_mask = (1 << gpio_shift);
1954 u32 gpio_reg;
1955 int value;
1956
1957 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1958 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1959 return -EINVAL;
1960 }
1961
1962 /* read GPIO value */
1963 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1964
1965 /* get the requested pin value */
1966 if ((gpio_reg & gpio_mask) == gpio_mask)
1967 value = 1;
1968 else
1969 value = 0;
1970
1971 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1972
1973 return value;
1974}
1975
17de50b7 1976int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 1977{
1978 /* The GPIO should be swapped if swap register is set and active */
1979 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 1980 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 1981 int gpio_shift = gpio_num +
1982 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1983 u32 gpio_mask = (1 << gpio_shift);
1984 u32 gpio_reg;
a2fbb9ea 1985
c18487ee
YR		 1986 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1987 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1988 return -EINVAL;
1989 }
a2fbb9ea 1990
4a37fb66 1991 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 1992 /* read GPIO and mask except the float bits */
1993 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 1994
c18487ee
YR		 1995 switch (mode) {
1996 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
51c1a580
MS		 1997 DP(NETIF_MSG_LINK,
1998 "Set GPIO %d (shift %d) -> output low\n",
c18487ee
YR		 1999 gpio_num, gpio_shift);
2000 /* clear FLOAT and set CLR */
2001 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2002 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2003 break;
a2fbb9ea 2004
c18487ee 2005 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
51c1a580
MS		 2006 DP(NETIF_MSG_LINK,
2007 "Set GPIO %d (shift %d) -> output high\n",
c18487ee
YR		 2008 gpio_num, gpio_shift);
2009 /* clear FLOAT and set SET */
2010 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2011 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2012 break;
a2fbb9ea 2013
17de50b7 2014 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
51c1a580
MS		 2015 DP(NETIF_MSG_LINK,
2016 "Set GPIO %d (shift %d) -> input\n",
c18487ee
YR		 2017 gpio_num, gpio_shift);
2018 /* set FLOAT */
2019 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2020 break;
a2fbb9ea 2021
c18487ee
YR		 2022 default:
2023 break;
a2fbb9ea
ET		 2024 }
2025
c18487ee 2026 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 2027 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 2028
c18487ee 2029 return 0;
a2fbb9ea
ET		 2030}
2031
0d40f0d4
YR		 2032int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2033{
2034 u32 gpio_reg = 0;
2035 int rc = 0;
2036
2037 /* Any port swapping should be handled by caller. */
2038
2039 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2040 /* read GPIO and mask except the float bits */
2041 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2042 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2043 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2044 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2045
2046 switch (mode) {
2047 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2048 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2049 /* set CLR */
2050 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2051 break;
2052
2053 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2054 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2055 /* set SET */
2056 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2057 break;
2058
2059 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2060 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2061 /* set FLOAT */
2062 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2063 break;
2064
2065 default:
2066 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2067 rc = -EINVAL;
2068 break;
2069 }
2070
2071 if (rc == 0)
2072 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2073
2074 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2075
2076 return rc;
2077}
2078
4acac6a5
EG		 2079int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2080{
2081 /* The GPIO should be swapped if swap register is set and active */
2082 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2083 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2084 int gpio_shift = gpio_num +
2085 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2086 u32 gpio_mask = (1 << gpio_shift);
2087 u32 gpio_reg;
2088
2089 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2090 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2091 return -EINVAL;
2092 }
2093
2094 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2095 /* read GPIO int */
2096 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2097
2098 switch (mode) {
2099 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
51c1a580
MS		 2100 DP(NETIF_MSG_LINK,
2101 "Clear GPIO INT %d (shift %d) -> output low\n",
2102 gpio_num, gpio_shift);
4acac6a5
EG		 2103 /* clear SET and set CLR */
2104 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2105 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2106 break;
2107
2108 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
51c1a580
MS		 2109 DP(NETIF_MSG_LINK,
2110 "Set GPIO INT %d (shift %d) -> output high\n",
2111 gpio_num, gpio_shift);
4acac6a5
EG		 2112 /* clear CLR and set SET */
2113 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2114 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2115 break;
2116
2117 default:
2118 break;
2119 }
2120
2121 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2122 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2123
2124 return 0;
2125}
2126
d6d99a3f 2127static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
a2fbb9ea 2128{
c18487ee 2129 u32 spio_reg;
a2fbb9ea 2130
d6d99a3f
YM		 2131 /* Only 2 SPIOs are configurable */
2132 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2133 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
c18487ee 2134 return -EINVAL;
a2fbb9ea
ET		 2135 }
2136
4a37fb66 2137 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2138 /* read SPIO and mask except the float bits */
d6d99a3f 2139 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
a2fbb9ea 2140
c18487ee 2141 switch (mode) {
d6d99a3f
YM		 2142 case MISC_SPIO_OUTPUT_LOW:
2143 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
c18487ee 2144 /* clear FLOAT and set CLR */
d6d99a3f
YM		 2145 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2146 spio_reg |= (spio << MISC_SPIO_CLR_POS);
c18487ee 2147 break;
a2fbb9ea 2148
d6d99a3f
YM		 2149 case MISC_SPIO_OUTPUT_HIGH:
2150 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
c18487ee 2151 /* clear FLOAT and set SET */
d6d99a3f
YM		 2152 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2153 spio_reg |= (spio << MISC_SPIO_SET_POS);
c18487ee 2154 break;
a2fbb9ea 2155
d6d99a3f
YM		 2156 case MISC_SPIO_INPUT_HI_Z:
2157 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
c18487ee 2158 /* set FLOAT */
d6d99a3f 2159 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
c18487ee 2160 break;
a2fbb9ea 2161
c18487ee
YR		 2162 default:
2163 break;
a2fbb9ea
ET		 2164 }
2165
c18487ee 2166 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2167 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2168
a2fbb9ea
ET		 2169 return 0;
2170}
2171
9f6c9258 2172void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2173{
a22f0788 2174 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2175 switch (bp->link_vars.ieee_fc &
2176 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2177 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2178 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2179 ADVERTISED_Pause);
c18487ee 2180 break;
356e2385 2181
c18487ee 2182 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2183 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2184 ADVERTISED_Pause);
c18487ee 2185 break;
356e2385 2186
c18487ee 2187 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2188 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2189 break;
356e2385 2190
c18487ee 2191 default:
a22f0788 2192 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2193 ADVERTISED_Pause);
c18487ee
YR		 2194 break;
2195 }
2196}
f1410647 2197
cd1dfce2 2198static void bnx2x_set_requested_fc(struct bnx2x *bp)
c18487ee 2199{
cd1dfce2
YM		 2200 /* Initialize link parameters structure variables
2201 * It is recommended to turn off RX FC for jumbo frames
2202 * for better performance
2203 */
2204 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2205 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2206 else
2207 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2208}
a2fbb9ea 2209
cd1dfce2
YM		 2210int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2211{
2212 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2213 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2214
2215 if (!BP_NOMCP(bp)) {
2216 bnx2x_set_requested_fc(bp);
4a37fb66 2217 bnx2x_acquire_phy_lock(bp);
b5bf9068 2218
a22f0788 2219 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2220 struct link_params *lp = &bp->link_params;
2221 lp->loopback_mode = LOOPBACK_XGXS;
2222 /* do PHY loopback at 10G speed, if possible */
2223 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2224 if (lp->speed_cap_mask[cfx_idx] &
2225 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2226 lp->req_line_speed[cfx_idx] =
2227 SPEED_10000;
2228 else
2229 lp->req_line_speed[cfx_idx] =
2230 SPEED_1000;
2231 }
a22f0788 2232 }
b5bf9068 2233
8970b2e4
MS		 2234 if (load_mode == LOAD_LOOPBACK_EXT) {
2235 struct link_params *lp = &bp->link_params;
2236 lp->loopback_mode = LOOPBACK_EXT;
2237 }
2238
19680c48 2239 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2240
4a37fb66 2241 bnx2x_release_phy_lock(bp);
a2fbb9ea 2242
3c96c68b
EG		 2243 bnx2x_calc_fc_adv(bp);
2244
cd1dfce2 2245 if (bp->link_vars.link_up) {
b5bf9068 2246 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2247 bnx2x_link_report(bp);
cd1dfce2
YM		 2248 }
2249 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2250 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2251 return rc;
2252 }
f5372251 2253 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2254 return -EINVAL;
a2fbb9ea
ET		 2255}
2256
9f6c9258 2257void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2258{
19680c48 2259 if (!BP_NOMCP(bp)) {
4a37fb66 2260 bnx2x_acquire_phy_lock(bp);
19680c48 2261 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2262 bnx2x_release_phy_lock(bp);
a2fbb9ea 2263
19680c48
EG		 2264 bnx2x_calc_fc_adv(bp);
2265 } else
f5372251 2266 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2267}
a2fbb9ea 2268
c18487ee
YR		 2269static void bnx2x__link_reset(struct bnx2x *bp)
2270{
19680c48 2271 if (!BP_NOMCP(bp)) {
4a37fb66 2272 bnx2x_acquire_phy_lock(bp);
5d07d868 2273 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
4a37fb66 2274 bnx2x_release_phy_lock(bp);
19680c48 2275 } else
f5372251 2276 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2277}
a2fbb9ea 2278
5d07d868
YM		 2279void bnx2x_force_link_reset(struct bnx2x *bp)
2280{
2281 bnx2x_acquire_phy_lock(bp);
2282 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2283 bnx2x_release_phy_lock(bp);
2284}
2285
a22f0788 2286u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2287{
2145a920 2288 u8 rc = 0;
a2fbb9ea 2289
2145a920
VZ		 2290 if (!BP_NOMCP(bp)) {
2291 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2292 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2293 is_serdes);
2145a920
VZ		 2294 bnx2x_release_phy_lock(bp);
2295 } else
2296 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2297
c18487ee
YR		 2298 return rc;
2299}
a2fbb9ea 2300
34f80b04 2301
2691d51d
EG		 2302/* Calculates the sum of vn_min_rates.
2303 It's needed for further normalizing of the min_rates.
2304 Returns:
2305 sum of vn_min_rates.
2306 or
2307 0 - if all the min_rates are 0.
2308 In the later case fainess algorithm should be deactivated.
2309 If not all min_rates are zero then those that are zeroes will be set to 1.
2310 */
b475d78f
YM		 2311static void bnx2x_calc_vn_min(struct bnx2x *bp,
2312 struct cmng_init_input *input)
2691d51d
EG		 2313{
2314 int all_zero = 1;
2691d51d
EG		 2315 int vn;
2316
3395a033 2317 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2318 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2319 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2320 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2321
2322 /* Skip hidden vns */
2323 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
b475d78f 2324 vn_min_rate = 0;
2691d51d 2325 /* If min rate is zero - set it to 1 */
b475d78f 2326 else if (!vn_min_rate)
2691d51d
EG		 2327 vn_min_rate = DEF_MIN_RATE;
2328 else
2329 all_zero = 0;
2330
b475d78f 2331 input->vnic_min_rate[vn] = vn_min_rate;
2691d51d
EG		 2332 }
2333
30ae438b
DK		 2334 /* if ETS or all min rates are zeros - disable fairness */
2335 if (BNX2X_IS_ETS_ENABLED(bp)) {
b475d78f 2336 input->flags.cmng_enables &=
30ae438b
DK		 2337 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2338 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2339 } else if (all_zero) {
b475d78f 2340 input->flags.cmng_enables &=
b015e3d1 2341 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
b475d78f
YM		 2342 DP(NETIF_MSG_IFUP,
2343 "All MIN values are zeroes fairness will be disabled\n");
b015e3d1 2344 } else
b475d78f 2345 input->flags.cmng_enables |=
b015e3d1 2346 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2347}
2348
b475d78f
YM		 2349static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2350 struct cmng_init_input *input)
34f80b04 2351{
b475d78f 2352 u16 vn_max_rate;
f2e0899f 2353 u32 vn_cfg = bp->mf_config[vn];
34f80b04 2354
b475d78f 2355 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
34f80b04 2356 vn_max_rate = 0;
b475d78f 2357 else {
faa6fcbb
DK		 2358 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2359
b475d78f 2360 if (IS_MF_SI(bp)) {
faa6fcbb
DK		 2361 /* maxCfg in percents of linkspeed */
2362 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
b475d78f 2363 } else /* SD modes */
faa6fcbb
DK		 2364 /* maxCfg is absolute in 100Mb units */
2365 vn_max_rate = maxCfg * 100;
34f80b04 2366 }
f85582f8 2367
b475d78f 2368 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
34f80b04 2369
b475d78f 2370 input->vnic_max_rate[vn] = vn_max_rate;
34f80b04 2371}
f85582f8 2372
b475d78f 2373
523224a3
DK		 2374static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2375{
2376 if (CHIP_REV_IS_SLOW(bp))
2377 return CMNG_FNS_NONE;
fb3bff17 2378 if (IS_MF(bp))
523224a3
DK		 2379 return CMNG_FNS_MINMAX;
2380
2381 return CMNG_FNS_NONE;
2382}
2383
2ae17f66 2384void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2385{
0793f83f 2386 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2387
2388 if (BP_NOMCP(bp))
2389 return; /* what should be the default bvalue in this case */
2390
0793f83f
DK		 2391 /* For 2 port configuration the absolute function number formula
2392 * is:
2393 * abs_func = 2 * vn + BP_PORT + BP_PATH
2394 *
2395 * and there are 4 functions per port
2396 *
2397 * For 4 port configuration it is
2398 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2399 *
2400 * and there are 2 functions per port
2401 */
3395a033 2402 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2403 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2404
2405 if (func >= E1H_FUNC_MAX)
2406 break;
2407
f2e0899f 2408 bp->mf_config[vn] =
523224a3
DK		 2409 MF_CFG_RD(bp, func_mf_config[func].config);
2410 }
a3348722
BW		 2411 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2412 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2413 bp->flags |= MF_FUNC_DIS;
2414 } else {
2415 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2416 bp->flags &= ~MF_FUNC_DIS;
2417 }
523224a3
DK		 2418}
2419
2420static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2421{
b475d78f
YM		 2422 struct cmng_init_input input;
2423 memset(&input, 0, sizeof(struct cmng_init_input));
2424
2425 input.port_rate = bp->link_vars.line_speed;
523224a3
DK		 2426
2427 if (cmng_type == CMNG_FNS_MINMAX) {
2428 int vn;
2429
523224a3
DK		 2430 /* read mf conf from shmem */
2431 if (read_cfg)
2432 bnx2x_read_mf_cfg(bp);
2433
523224a3 2434 /* vn_weight_sum and enable fairness if not 0 */
b475d78f 2435 bnx2x_calc_vn_min(bp, &input);
523224a3
DK		 2436
2437 /* calculate and set min-max rate for each vn */
c4154f25 2438 if (bp->port.pmf)
3395a033 2439 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
b475d78f 2440 bnx2x_calc_vn_max(bp, vn, &input);
523224a3
DK		 2441
2442 /* always enable rate shaping and fairness */
b475d78f 2443 input.flags.cmng_enables |=
523224a3 2444 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
b475d78f
YM		 2445
2446 bnx2x_init_cmng(&input, &bp->cmng);
523224a3
DK		 2447 return;
2448 }
2449
2450 /* rate shaping and fairness are disabled */
2451 DP(NETIF_MSG_IFUP,
2452 "rate shaping and fairness are disabled\n");
2453}
34f80b04 2454
1191cb83
ED		 2455static void storm_memset_cmng(struct bnx2x *bp,
2456 struct cmng_init *cmng,
2457 u8 port)
2458{
2459 int vn;
2460 size_t size = sizeof(struct cmng_struct_per_port);
2461
2462 u32 addr = BAR_XSTRORM_INTMEM +
2463 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2464
2465 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2466
2467 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2468 int func = func_by_vn(bp, vn);
2469
2470 addr = BAR_XSTRORM_INTMEM +
2471 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2472 size = sizeof(struct rate_shaping_vars_per_vn);
2473 __storm_memset_struct(bp, addr, size,
2474 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2475
2476 addr = BAR_XSTRORM_INTMEM +
2477 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2478 size = sizeof(struct fairness_vars_per_vn);
2479 __storm_memset_struct(bp, addr, size,
2480 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2481 }
2482}
2483
c18487ee
YR		 2484/* This function is called upon link interrupt */
2485static void bnx2x_link_attn(struct bnx2x *bp)
2486{
bb2a0f7a
YG		 2487 /* Make sure that we are synced with the current statistics */
2488 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2489
c18487ee 2490 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2491
bb2a0f7a
YG		 2492 if (bp->link_vars.link_up) {
2493
1c06328c 2494 /* dropless flow control */
f2e0899f 2495 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1c06328c
EG		 2496 int port = BP_PORT(bp);
2497 u32 pause_enabled = 0;
2498
2499 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2500 pause_enabled = 1;
2501
2502 REG_WR(bp, BAR_USTRORM_INTMEM +
ca00392c 2503 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
1c06328c
EG		 2504 pause_enabled);
2505 }
2506
619c5cb6 2507 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2508 struct host_port_stats *pstats;
2509
2510 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2511 /* reset old mac stats */
bb2a0f7a
YG		 2512 memset(&(pstats->mac_stx[0]), 0,
2513 sizeof(struct mac_stx));
2514 }
f34d28ea 2515 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2516 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2517 }
2518
f2e0899f
DK		 2519 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2520 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
8a1c38d1 2521
f2e0899f
DK		 2522 if (cmng_fns != CMNG_FNS_NONE) {
2523 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2524 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2525 } else
2526 /* rate shaping and fairness are disabled */
2527 DP(NETIF_MSG_IFUP,
2528 "single function mode without fairness\n");
34f80b04 2529 }
9fdc3e95 2530
2ae17f66
VZ		 2531 __bnx2x_link_report(bp);
2532
9fdc3e95
DK		 2533 if (IS_MF(bp))
2534 bnx2x_link_sync_notify(bp);
c18487ee 2535}
a2fbb9ea 2536
9f6c9258 2537void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2538{
2ae17f66 2539 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2540 return;
a2fbb9ea 2541
00253a8c 2542 /* read updated dcb configuration */
ad5afc89
AE		 2543 if (IS_PF(bp)) {
2544 bnx2x_dcbx_pmf_update(bp);
2545 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2546 if (bp->link_vars.link_up)
2547 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2548 else
2549 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2550 /* indicate link status */
2551 bnx2x_link_report(bp);
a2fbb9ea 2552
ad5afc89
AE		 2553 } else { /* VF */
2554 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2555 SUPPORTED_10baseT_Full |
2556 SUPPORTED_100baseT_Half |
2557 SUPPORTED_100baseT_Full |
2558 SUPPORTED_1000baseT_Full |
2559 SUPPORTED_2500baseX_Full |
2560 SUPPORTED_10000baseT_Full |
2561 SUPPORTED_TP |
2562 SUPPORTED_FIBRE |
2563 SUPPORTED_Autoneg |
2564 SUPPORTED_Pause |
2565 SUPPORTED_Asym_Pause);
2566 bp->port.advertising[0] = bp->port.supported[0];
2567
2568 bp->link_params.bp = bp;
2569 bp->link_params.port = BP_PORT(bp);
2570 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2571 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2572 bp->link_params.req_line_speed[0] = SPEED_10000;
2573 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2574 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2575 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2576 bp->link_vars.line_speed = SPEED_10000;
2577 bp->link_vars.link_status =
2578 (LINK_STATUS_LINK_UP |
2579 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2580 bp->link_vars.link_up = 1;
2581 bp->link_vars.duplex = DUPLEX_FULL;
2582 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2583 __bnx2x_link_report(bp);
bb2a0f7a 2584 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
ad5afc89 2585 }
a2fbb9ea 2586}
a2fbb9ea 2587
a3348722
BW		 2588static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2589 u16 vlan_val, u8 allowed_prio)
2590{
2591 struct bnx2x_func_state_params func_params = {0};
2592 struct bnx2x_func_afex_update_params *f_update_params =
2593 &func_params.params.afex_update;
2594
2595 func_params.f_obj = &bp->func_obj;
2596 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2597
2598 /* no need to wait for RAMROD completion, so don't
2599 * set RAMROD_COMP_WAIT flag
2600 */
2601
2602 f_update_params->vif_id = vifid;
2603 f_update_params->afex_default_vlan = vlan_val;
2604 f_update_params->allowed_priorities = allowed_prio;
2605
2606 /* if ramrod can not be sent, response to MCP immediately */
2607 if (bnx2x_func_state_change(bp, &func_params) < 0)
2608 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2609
2610 return 0;
2611}
2612
2613static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2614 u16 vif_index, u8 func_bit_map)
2615{
2616 struct bnx2x_func_state_params func_params = {0};
2617 struct bnx2x_func_afex_viflists_params *update_params =
2618 &func_params.params.afex_viflists;
2619 int rc;
2620 u32 drv_msg_code;
2621
2622 /* validate only LIST_SET and LIST_GET are received from switch */
2623 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2624 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2625 cmd_type);
2626
2627 func_params.f_obj = &bp->func_obj;
2628 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2629
2630 /* set parameters according to cmd_type */
2631 update_params->afex_vif_list_command = cmd_type;
2632 update_params->vif_list_index = cpu_to_le16(vif_index);
2633 update_params->func_bit_map =
2634 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2635 update_params->func_to_clear = 0;
2636 drv_msg_code =
2637 (cmd_type == VIF_LIST_RULE_GET) ?
2638 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2639 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2640
2641 /* if ramrod can not be sent, respond to MCP immediately for
2642 * SET and GET requests (other are not triggered from MCP)
2643 */
2644 rc = bnx2x_func_state_change(bp, &func_params);
2645 if (rc < 0)
2646 bnx2x_fw_command(bp, drv_msg_code, 0);
2647
2648 return 0;
2649}
2650
2651static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2652{
2653 struct afex_stats afex_stats;
2654 u32 func = BP_ABS_FUNC(bp);
2655 u32 mf_config;
2656 u16 vlan_val;
2657 u32 vlan_prio;
2658 u16 vif_id;
2659 u8 allowed_prio;
2660 u8 vlan_mode;
2661 u32 addr_to_write, vifid, addrs, stats_type, i;
2662
2663 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2664 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2665 DP(BNX2X_MSG_MCP,
2666 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2667 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2668 }
2669
2670 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2671 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2672 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2673 DP(BNX2X_MSG_MCP,
2674 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2675 vifid, addrs);
2676 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2677 addrs);
2678 }
2679
2680 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2681 addr_to_write = SHMEM2_RD(bp,
2682 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2683 stats_type = SHMEM2_RD(bp,
2684 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2685
2686 DP(BNX2X_MSG_MCP,
2687 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2688 addr_to_write);
2689
2690 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2691
2692 /* write response to scratchpad, for MCP */
2693 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2694 REG_WR(bp, addr_to_write + i*sizeof(u32),
2695 *(((u32 *)(&afex_stats))+i));
2696
2697 /* send ack message to MCP */
2698 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2699 }
2700
2701 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2702 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2703 bp->mf_config[BP_VN(bp)] = mf_config;
2704 DP(BNX2X_MSG_MCP,
2705 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2706 mf_config);
2707
2708 /* if VIF_SET is "enabled" */
2709 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2710 /* set rate limit directly to internal RAM */
2711 struct cmng_init_input cmng_input;
2712 struct rate_shaping_vars_per_vn m_rs_vn;
2713 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2714 u32 addr = BAR_XSTRORM_INTMEM +
2715 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2716
2717 bp->mf_config[BP_VN(bp)] = mf_config;
2718
2719 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2720 m_rs_vn.vn_counter.rate =
2721 cmng_input.vnic_max_rate[BP_VN(bp)];
2722 m_rs_vn.vn_counter.quota =
2723 (m_rs_vn.vn_counter.rate *
2724 RS_PERIODIC_TIMEOUT_USEC) / 8;
2725
2726 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2727
2728 /* read relevant values from mf_cfg struct in shmem */
2729 vif_id =
2730 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2731 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2732 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2733 vlan_val =
2734 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2735 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2736 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2737 vlan_prio = (mf_config &
2738 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2739 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2740 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2741 vlan_mode =
2742 (MF_CFG_RD(bp,
2743 func_mf_config[func].afex_config) &
2744 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2745 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2746 allowed_prio =
2747 (MF_CFG_RD(bp,
2748 func_mf_config[func].afex_config) &
2749 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2750 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2751
2752 /* send ramrod to FW, return in case of failure */
2753 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2754 allowed_prio))
2755 return;
2756
2757 bp->afex_def_vlan_tag = vlan_val;
2758 bp->afex_vlan_mode = vlan_mode;
2759 } else {
2760 /* notify link down because BP->flags is disabled */
2761 bnx2x_link_report(bp);
2762
2763 /* send INVALID VIF ramrod to FW */
2764 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2765
2766 /* Reset the default afex VLAN */
2767 bp->afex_def_vlan_tag = -1;
2768 }
2769 }
2770}
2771
34f80b04
EG		 2772static void bnx2x_pmf_update(struct bnx2x *bp)
2773{
2774 int port = BP_PORT(bp);
2775 u32 val;
2776
2777 bp->port.pmf = 1;
51c1a580 2778 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
34f80b04 2779
3deb8167
YR		 2780 /*
2781 * We need the mb() to ensure the ordering between the writing to
2782 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2783 */
2784 smp_mb();
2785
2786 /* queue a periodic task */
2787 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2788
ef01854e
DK		 2789 bnx2x_dcbx_pmf_update(bp);
2790
34f80b04 2791 /* enable nig attention */
3395a033 2792 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2793 if (bp->common.int_block == INT_BLOCK_HC) {
2794 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2795 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2796 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2797 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2798 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2799 }
bb2a0f7a
YG		 2800
2801 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2802}
2803
c18487ee 2804/* end of Link */
a2fbb9ea
ET		 2805
2806/* slow path */
2807
2808/*
2809 * General service functions
2810 */
2811
2691d51d 2812/* send the MCP a request, block until there is a reply */
a22f0788 2813u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2814{
f2e0899f 2815 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2816 u32 seq;
2691d51d
EG		 2817 u32 rc = 0;
2818 u32 cnt = 1;
2819 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2820
c4ff7cbf 2821 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2822 seq = ++bp->fw_seq;
f2e0899f
DK		 2823 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2824 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2825
754a2f52
DK		 2826 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2827 (command | seq), param);
2691d51d
EG		 2828
2829 do {
2830 /* let the FW do it's magic ... */
2831 msleep(delay);
2832
f2e0899f 2833 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2834
c4ff7cbf
EG		 2835 /* Give the FW up to 5 second (500*10ms) */
2836 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2837
2838 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2839 cnt*delay, rc, seq);
2840
2841 /* is this a reply to our command? */
2842 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2843 rc &= FW_MSG_CODE_MASK;
2844 else {
2845 /* FW BUG! */
2846 BNX2X_ERR("FW failed to respond!\n");
2847 bnx2x_fw_dump(bp);
2848 rc = 0;
2849 }
c4ff7cbf 2850 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2851
2852 return rc;
2853}
2854
ec6ba945 2855
1191cb83
ED		 2856static void storm_memset_func_cfg(struct bnx2x *bp,
2857 struct tstorm_eth_function_common_config *tcfg,
2858 u16 abs_fid)
2859{
2860 size_t size = sizeof(struct tstorm_eth_function_common_config);
2861
2862 u32 addr = BAR_TSTRORM_INTMEM +
2863 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2864
2865 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2866}
2867
619c5cb6
VZ		 2868void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2869{
2870 if (CHIP_IS_E1x(bp)) {
2871 struct tstorm_eth_function_common_config tcfg = {0};
2872
2873 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2874 }
2875
2876 /* Enable the function in the FW */
2877 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2878 storm_memset_func_en(bp, p->func_id, 1);
2879
2880 /* spq */
2881 if (p->func_flgs & FUNC_FLG_SPQ) {
2882 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2883 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2884 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2885 }
2886}
2887
6383c0b3
AE		 2888/**
2889 * bnx2x_get_tx_only_flags - Return common flags
2890 *
2891 * @bp device handle
2892 * @fp queue handle
2893 * @zero_stats TRUE if statistics zeroing is needed
2894 *
2895 * Return the flags that are common for the Tx-only and not normal connections.
2896 */
1191cb83
ED		 2897static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2898 struct bnx2x_fastpath *fp,
2899 bool zero_stats)
28912902 2900{
619c5cb6
VZ		 2901 unsigned long flags = 0;
2902
2903 /* PF driver will always initialize the Queue to an ACTIVE state */
2904 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 2905
6383c0b3
AE		 2906 /* tx only connections collect statistics (on the same index as the
2907 * parent connection). The statistics are zeroed when the parent
2908 * connection is initialized.
2909 */
50f0a562
BW		 2910
2911 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2912 if (zero_stats)
2913 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2914
6383c0b3
AE		 2915
2916 return flags;
2917}
2918
1191cb83
ED		 2919static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2920 struct bnx2x_fastpath *fp,
2921 bool leading)
6383c0b3
AE		 2922{
2923 unsigned long flags = 0;
2924
619c5cb6
VZ		 2925 /* calculate other queue flags */
2926 if (IS_MF_SD(bp))
2927 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 2928
a3348722 2929 if (IS_FCOE_FP(fp)) {
619c5cb6 2930 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
a3348722
BW		 2931 /* For FCoE - force usage of default priority (for afex) */
2932 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2933 }
523224a3 2934
f5219d8e 2935 if (!fp->disable_tpa) {
619c5cb6 2936 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e 2937 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
621b4d66
DK		 2938 if (fp->mode == TPA_MODE_GRO)
2939 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
f5219d8e 2940 }
619c5cb6 2941
619c5cb6
VZ		 2942 if (leading) {
2943 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2944 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2945 }
523224a3 2946
619c5cb6
VZ		 2947 /* Always set HW VLAN stripping */
2948 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 2949
a3348722
BW		 2950 /* configure silent vlan removal */
2951 if (IS_MF_AFEX(bp))
2952 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
2953
6383c0b3
AE		 2954
2955 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 2956}
2957
619c5cb6 2958static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 2959 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2960 u8 cos)
619c5cb6
VZ		 2961{
2962 gen_init->stat_id = bnx2x_stats_id(fp);
2963 gen_init->spcl_id = fp->cl_id;
2964
2965 /* Always use mini-jumbo MTU for FCoE L2 ring */
2966 if (IS_FCOE_FP(fp))
2967 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2968 else
2969 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 2970
2971 gen_init->cos = cos;
619c5cb6
VZ		 2972}
2973
2974static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 2975 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 2976 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 2977{
619c5cb6 2978 u8 max_sge = 0;
523224a3
DK		 2979 u16 sge_sz = 0;
2980 u16 tpa_agg_size = 0;
2981
523224a3 2982 if (!fp->disable_tpa) {
dfacf138
DK		 2983 pause->sge_th_lo = SGE_TH_LO(bp);
2984 pause->sge_th_hi = SGE_TH_HI(bp);
2985
2986 /* validate SGE ring has enough to cross high threshold */
2987 WARN_ON(bp->dropless_fc &&
2988 pause->sge_th_hi + FW_PREFETCH_CNT >
2989 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2990
523224a3
DK		 2991 tpa_agg_size = min_t(u32,
2992 (min_t(u32, 8, MAX_SKB_FRAGS) *
2993 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2994 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2995 SGE_PAGE_SHIFT;
2996 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2997 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2998 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2999 0xffff);
3000 }
3001
3002 /* pause - not for e1 */
3003 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 3004 pause->bd_th_lo = BD_TH_LO(bp);
3005 pause->bd_th_hi = BD_TH_HI(bp);
3006
3007 pause->rcq_th_lo = RCQ_TH_LO(bp);
3008 pause->rcq_th_hi = RCQ_TH_HI(bp);
3009 /*
3010 * validate that rings have enough entries to cross
3011 * high thresholds
3012 */
3013 WARN_ON(bp->dropless_fc &&
3014 pause->bd_th_hi + FW_PREFETCH_CNT >
3015 bp->rx_ring_size);
3016 WARN_ON(bp->dropless_fc &&
3017 pause->rcq_th_hi + FW_PREFETCH_CNT >
3018 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 3019
523224a3
DK		 3020 pause->pri_map = 1;
3021 }
3022
3023 /* rxq setup */
523224a3
DK		 3024 rxq_init->dscr_map = fp->rx_desc_mapping;
3025 rxq_init->sge_map = fp->rx_sge_mapping;
3026 rxq_init->rcq_map = fp->rx_comp_mapping;
3027 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 3028
619c5cb6
VZ		 3029 /* This should be a maximum number of data bytes that may be
3030 * placed on the BD (not including paddings).
3031 */
e52fcb24
ED		 3032 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3033 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 3034
523224a3 3035 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 3036 rxq_init->tpa_agg_sz = tpa_agg_size;
3037 rxq_init->sge_buf_sz = sge_sz;
3038 rxq_init->max_sges_pkt = max_sge;
619c5cb6 3039 rxq_init->rss_engine_id = BP_FUNC(bp);
259afa1f 3040 rxq_init->mcast_engine_id = BP_FUNC(bp);
619c5cb6
VZ		 3041
3042 /* Maximum number or simultaneous TPA aggregation for this Queue.
3043 *
3044 * For PF Clients it should be the maximum avaliable number.
3045 * VF driver(s) may want to define it to a smaller value.
3046 */
dfacf138 3047 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 3048
523224a3
DK		 3049 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3050 rxq_init->fw_sb_id = fp->fw_sb_id;
3051
ec6ba945
VZ		 3052 if (IS_FCOE_FP(fp))
3053 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3054 else
6383c0b3 3055 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
a3348722
BW		 3056 /* configure silent vlan removal
3057 * if multi function mode is afex, then mask default vlan
3058 */
3059 if (IS_MF_AFEX(bp)) {
3060 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3061 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3062 }
523224a3
DK		 3063}
3064
619c5cb6 3065static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 3066 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3067 u8 cos)
523224a3 3068{
65565884 3069 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
6383c0b3 3070 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 3071 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3072 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 3073
619c5cb6
VZ		 3074 /*
3075 * set the tss leading client id for TX classfication ==
3076 * leading RSS client id
3077 */
3078 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3079
ec6ba945
VZ		 3080 if (IS_FCOE_FP(fp)) {
3081 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3082 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3083 }
523224a3
DK		 3084}
3085
8d96286a 3086static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 3087{
3088 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 3089 struct event_ring_data eq_data = { {0} };
3090 u16 flags;
3091
619c5cb6 3092 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3093 /* reset IGU PF statistics: MSIX + ATTN */
3094 /* PF */
3095 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3096 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3097 (CHIP_MODE_IS_4_PORT(bp) ?
3098 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3099 /* ATTN */
3100 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3101 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3102 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3103 (CHIP_MODE_IS_4_PORT(bp) ?
3104 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3105 }
3106
523224a3
DK		 3107 /* function setup flags */
3108 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3109
619c5cb6
VZ		 3110 /* This flag is relevant for E1x only.
3111 * E2 doesn't have a TPA configuration in a function level.
523224a3 3112 */
619c5cb6 3113 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 3114
3115 func_init.func_flgs = flags;
3116 func_init.pf_id = BP_FUNC(bp);
3117 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 3118 func_init.spq_map = bp->spq_mapping;
3119 func_init.spq_prod = bp->spq_prod_idx;
3120
3121 bnx2x_func_init(bp, &func_init);
3122
3123 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3124
3125 /*
619c5cb6
VZ		 3126 * Congestion management values depend on the link rate
3127 * There is no active link so initial link rate is set to 10 Gbps.
3128 * When the link comes up The congestion management values are
3129 * re-calculated according to the actual link rate.
3130 */
523224a3
DK		 3131 bp->link_vars.line_speed = SPEED_10000;
3132 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3133
3134 /* Only the PMF sets the HW */
3135 if (bp->port.pmf)
3136 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3137
523224a3
DK		 3138 /* init Event Queue */
3139 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3140 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3141 eq_data.producer = bp->eq_prod;
3142 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3143 eq_data.sb_id = DEF_SB_ID;
3144 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3145}
3146
3147
3148static void bnx2x_e1h_disable(struct bnx2x *bp)
3149{
3150 int port = BP_PORT(bp);
3151
619c5cb6 3152 bnx2x_tx_disable(bp);
523224a3
DK		 3153
3154 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 3155}
3156
3157static void bnx2x_e1h_enable(struct bnx2x *bp)
3158{
3159 int port = BP_PORT(bp);
3160
3161 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3162
3163 /* Tx queue should be only reenabled */
3164 netif_tx_wake_all_queues(bp->dev);
3165
3166 /*
3167 * Should not call netif_carrier_on since it will be called if the link
3168 * is up when checking for link state
3169 */
3170}
3171
1d187b34
BW		 3172#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3173
3174static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3175{
3176 struct eth_stats_info *ether_stat =
3177 &bp->slowpath->drv_info_to_mcp.ether_stat;
3178
786fdf0b
DC		 3179 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3180 ETH_STAT_INFO_VERSION_LEN);
1d187b34 3181
15192a8c
BW		 3182 bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3183 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3184 ether_stat->mac_local);
1d187b34
BW		 3185
3186 ether_stat->mtu_size = bp->dev->mtu;
3187
3188 if (bp->dev->features & NETIF_F_RXCSUM)
3189 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3190 if (bp->dev->features & NETIF_F_TSO)
3191 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3192 ether_stat->feature_flags |= bp->common.boot_mode;
3193
3194 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3195
3196 ether_stat->txq_size = bp->tx_ring_size;
3197 ether_stat->rxq_size = bp->rx_ring_size;
3198}
3199
3200static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3201{
3202 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3203 struct fcoe_stats_info *fcoe_stat =
3204 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3205
55c11941
MS		 3206 if (!CNIC_LOADED(bp))
3207 return;
3208
2e499d3c
BW		 3209 memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT,
3210 bp->fip_mac, ETH_ALEN);
1d187b34
BW		 3211
3212 fcoe_stat->qos_priority =
3213 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3214
3215 /* insert FCoE stats from ramrod response */
3216 if (!NO_FCOE(bp)) {
3217 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
65565884 3218 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3219 tstorm_queue_statistics;
3220
3221 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
65565884 3222 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3223 xstorm_queue_statistics;
3224
3225 struct fcoe_statistics_params *fw_fcoe_stat =
3226 &bp->fw_stats_data->fcoe;
3227
3228 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
3229 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3230
3231 ADD_64(fcoe_stat->rx_bytes_hi,
3232 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3233 fcoe_stat->rx_bytes_lo,
3234 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3235
3236 ADD_64(fcoe_stat->rx_bytes_hi,
3237 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3238 fcoe_stat->rx_bytes_lo,
3239 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3240
3241 ADD_64(fcoe_stat->rx_bytes_hi,
3242 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3243 fcoe_stat->rx_bytes_lo,
3244 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3245
3246 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3247 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3248
3249 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3250 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3251
3252 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3253 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3254
3255 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
f33f1fcc 3256 fcoe_q_tstorm_stats->rcv_mcast_pkts);
1d187b34
BW		 3257
3258 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3259 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3260
3261 ADD_64(fcoe_stat->tx_bytes_hi,
3262 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3263 fcoe_stat->tx_bytes_lo,
3264 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3265
3266 ADD_64(fcoe_stat->tx_bytes_hi,
3267 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3268 fcoe_stat->tx_bytes_lo,
3269 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3270
3271 ADD_64(fcoe_stat->tx_bytes_hi,
3272 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3273 fcoe_stat->tx_bytes_lo,
3274 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3275
3276 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3277 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3278
3279 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3280 fcoe_q_xstorm_stats->ucast_pkts_sent);
3281
3282 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3283 fcoe_q_xstorm_stats->bcast_pkts_sent);
3284
3285 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3286 fcoe_q_xstorm_stats->mcast_pkts_sent);
3287 }
3288
1d187b34
BW		 3289 /* ask L5 driver to add data to the struct */
3290 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
1d187b34
BW		 3291}
3292
3293static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3294{
3295 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3296 struct iscsi_stats_info *iscsi_stat =
3297 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3298
55c11941
MS		 3299 if (!CNIC_LOADED(bp))
3300 return;
3301
2e499d3c
BW		 3302 memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT,
3303 bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
1d187b34
BW		 3304
3305 iscsi_stat->qos_priority =
3306 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3307
1d187b34
BW		 3308 /* ask L5 driver to add data to the struct */
3309 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
1d187b34
BW		 3310}
3311
0793f83f
DK		 3312/* called due to MCP event (on pmf):
3313 * reread new bandwidth configuration
3314 * configure FW
3315 * notify others function about the change
3316 */
1191cb83 3317static void bnx2x_config_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3318{
3319 if (bp->link_vars.link_up) {
3320 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3321 bnx2x_link_sync_notify(bp);
3322 }
3323 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3324}
3325
1191cb83 3326static void bnx2x_set_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3327{
3328 bnx2x_config_mf_bw(bp);
3329 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3330}
3331
c8c60d88
YM		 3332static void bnx2x_handle_eee_event(struct bnx2x *bp)
3333{
3334 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3335 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3336}
3337
1d187b34
BW		 3338static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3339{
3340 enum drv_info_opcode op_code;
3341 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3342
3343 /* if drv_info version supported by MFW doesn't match - send NACK */
3344 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3345 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3346 return;
3347 }
3348
3349 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3350 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3351
3352 memset(&bp->slowpath->drv_info_to_mcp, 0,
3353 sizeof(union drv_info_to_mcp));
3354
3355 switch (op_code) {
3356 case ETH_STATS_OPCODE:
3357 bnx2x_drv_info_ether_stat(bp);
3358 break;
3359 case FCOE_STATS_OPCODE:
3360 bnx2x_drv_info_fcoe_stat(bp);
3361 break;
3362 case ISCSI_STATS_OPCODE:
3363 bnx2x_drv_info_iscsi_stat(bp);
3364 break;
3365 default:
3366 /* if op code isn't supported - send NACK */
3367 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3368 return;
3369 }
3370
3371 /* if we got drv_info attn from MFW then these fields are defined in
3372 * shmem2 for sure
3373 */
3374 SHMEM2_WR(bp, drv_info_host_addr_lo,
3375 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3376 SHMEM2_WR(bp, drv_info_host_addr_hi,
3377 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3378
3379 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3380}
3381
523224a3
DK		 3382static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3383{
3384 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3385
3386 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3387
3388 /*
3389 * This is the only place besides the function initialization
3390 * where the bp->flags can change so it is done without any
3391 * locks
3392 */
f2e0899f 3393 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
51c1a580 3394 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
523224a3
DK		 3395 bp->flags |= MF_FUNC_DIS;
3396
3397 bnx2x_e1h_disable(bp);
3398 } else {
51c1a580 3399 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
523224a3
DK		 3400 bp->flags &= ~MF_FUNC_DIS;
3401
3402 bnx2x_e1h_enable(bp);
3403 }
3404 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3405 }
3406 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 3407 bnx2x_config_mf_bw(bp);
523224a3
DK		 3408 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3409 }
3410
3411 /* Report results to MCP */
3412 if (dcc_event)
3413 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3414 else
3415 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3416}
3417
3418/* must be called under the spq lock */
1191cb83 3419static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
523224a3
DK		 3420{
3421 struct eth_spe *next_spe = bp->spq_prod_bd;
3422
3423 if (bp->spq_prod_bd == bp->spq_last_bd) {
3424 bp->spq_prod_bd = bp->spq;
3425 bp->spq_prod_idx = 0;
51c1a580 3426 DP(BNX2X_MSG_SP, "end of spq\n");
523224a3
DK		 3427 } else {
3428 bp->spq_prod_bd++;
3429 bp->spq_prod_idx++;
3430 }
3431 return next_spe;
3432}
3433
3434/* must be called under the spq lock */
1191cb83 3435static void bnx2x_sp_prod_update(struct bnx2x *bp)
28912902
MC		 3436{
3437 int func = BP_FUNC(bp);
3438
53e51e2f
VZ		 3439 /*
3440 * Make sure that BD data is updated before writing the producer:
3441 * BD data is written to the memory, the producer is read from the
3442 * memory, thus we need a full memory barrier to ensure the ordering.
3443 */
3444 mb();
28912902 3445
523224a3 3446 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3447 bp->spq_prod_idx);
28912902
MC		 3448 mmiowb();
3449}
3450
619c5cb6
VZ		 3451/**
3452 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3453 *
3454 * @cmd: command to check
3455 * @cmd_type: command type
3456 */
1191cb83 3457static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
619c5cb6
VZ		 3458{
3459 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3460 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3461 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3462 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3463 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3464 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3465 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3466 return true;
3467 else
3468 return false;
3469
3470}
3471
3472
3473/**
3474 * bnx2x_sp_post - place a single command on an SP ring
3475 *
3476 * @bp: driver handle
3477 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3478 * @cid: SW CID the command is related to
3479 * @data_hi: command private data address (high 32 bits)
3480 * @data_lo: command private data address (low 32 bits)
3481 * @cmd_type: command type (e.g. NONE, ETH)
3482 *
3483 * SP data is handled as if it's always an address pair, thus data fields are
3484 * not swapped to little endian in upper functions. Instead this function swaps
3485 * data as if it's two u32 fields.
3486 */
9f6c9258 3487int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3488 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3489{
28912902 3490 struct eth_spe *spe;
523224a3 3491 u16 type;
619c5cb6 3492 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3493
a2fbb9ea 3494#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 3495 if (unlikely(bp->panic)) {
3496 BNX2X_ERR("Can't post SP when there is panic\n");
a2fbb9ea 3497 return -EIO;
51c1a580 3498 }
a2fbb9ea
ET		 3499#endif
3500
34f80b04 3501 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3502
6e30dd4e
VZ		 3503 if (common) {
3504 if (!atomic_read(&bp->eq_spq_left)) {
3505 BNX2X_ERR("BUG! EQ ring full!\n");
3506 spin_unlock_bh(&bp->spq_lock);
3507 bnx2x_panic();
3508 return -EBUSY;
3509 }
3510 } else if (!atomic_read(&bp->cq_spq_left)) {
3511 BNX2X_ERR("BUG! SPQ ring full!\n");
3512 spin_unlock_bh(&bp->spq_lock);
3513 bnx2x_panic();
3514 return -EBUSY;
a2fbb9ea 3515 }
f1410647 3516
28912902
MC		 3517 spe = bnx2x_sp_get_next(bp);
3518
a2fbb9ea 3519 /* CID needs port number to be encoded int it */
28912902 3520 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3521 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3522 HW_CID(bp, cid));
523224a3 3523
619c5cb6 3524 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
a2fbb9ea 3525
523224a3
DK		 3526 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3527 SPE_HDR_FUNCTION_ID);
a2fbb9ea 3528
523224a3
DK		 3529 spe->hdr.type = cpu_to_le16(type);
3530
3531 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3532 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3533
d6cae238
VZ		 3534 /*
3535 * It's ok if the actual decrement is issued towards the memory
3536 * somewhere between the spin_lock and spin_unlock. Thus no
3537 * more explict memory barrier is needed.
3538 */
3539 if (common)
3540 atomic_dec(&bp->eq_spq_left);
3541 else
3542 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3543
a2fbb9ea 3544
51c1a580
MS		 3545 DP(BNX2X_MSG_SP,
3546 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3547 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3548 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3549 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3550 HW_CID(bp, cid), data_hi, data_lo, type,
3551 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3552
28912902 3553 bnx2x_sp_prod_update(bp);
34f80b04 3554 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3555 return 0;
3556}
3557
3558/* acquire split MCP access lock register */
4a37fb66 3559static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3560{
72fd0718 3561 u32 j, val;
34f80b04 3562 int rc = 0;
a2fbb9ea
ET		 3563
3564 might_sleep();
72fd0718 3565 for (j = 0; j < 1000; j++) {
a2fbb9ea
ET		 3566 val = (1UL << 31);
3567 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3568 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3569 if (val & (1L << 31))
3570 break;
3571
3572 msleep(5);
3573 }
a2fbb9ea 3574 if (!(val & (1L << 31))) {
19680c48 3575 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3576 rc = -EBUSY;
3577 }
3578
3579 return rc;
3580}
3581
4a37fb66
YG		 3582/* release split MCP access lock register */
3583static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3584{
72fd0718 3585 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
a2fbb9ea
ET		 3586}
3587
523224a3
DK		 3588#define BNX2X_DEF_SB_ATT_IDX 0x0001
3589#define BNX2X_DEF_SB_IDX 0x0002
3590
1191cb83 3591static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
a2fbb9ea 3592{
523224a3 3593 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3594 u16 rc = 0;
3595
3596 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3597 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3598 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3599 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3600 }
523224a3
DK		 3601
3602 if (bp->def_idx != def_sb->sp_sb.running_index) {
3603 bp->def_idx = def_sb->sp_sb.running_index;
3604 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3605 }
523224a3
DK		 3606
3607 /* Do not reorder: indecies reading should complete before handling */
3608 barrier();
a2fbb9ea
ET		 3609 return rc;
3610}
3611
3612/*
3613 * slow path service functions
3614 */
3615
3616static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3617{
34f80b04 3618 int port = BP_PORT(bp);
a2fbb9ea
ET		 3619 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3620 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3621 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3622 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3623 u32 aeu_mask;
87942b46 3624 u32 nig_mask = 0;
f2e0899f 3625 u32 reg_addr;
a2fbb9ea 3626
a2fbb9ea
ET		 3627 if (bp->attn_state & asserted)
3628 BNX2X_ERR("IGU ERROR\n");
3629
3fcaf2e5
EG		 3630 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3631 aeu_mask = REG_RD(bp, aeu_addr);
3632
a2fbb9ea 3633 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3634 aeu_mask, asserted);
72fd0718 3635 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3636 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3637
3fcaf2e5
EG		 3638 REG_WR(bp, aeu_addr, aeu_mask);
3639 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3640
3fcaf2e5 3641 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3642 bp->attn_state |= asserted;
3fcaf2e5 3643 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3644
3645 if (asserted & ATTN_HARD_WIRED_MASK) {
3646 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3647
a5e9a7cf
EG		 3648 bnx2x_acquire_phy_lock(bp);
3649
877e9aa4 3650 /* save nig interrupt mask */
87942b46 3651 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3652
361c391e
YR		 3653 /* If nig_mask is not set, no need to call the update
3654 * function.
3655 */
3656 if (nig_mask) {
3657 REG_WR(bp, nig_int_mask_addr, 0);
3658
3659 bnx2x_link_attn(bp);
3660 }
a2fbb9ea
ET		 3661
3662 /* handle unicore attn? */
3663 }
3664 if (asserted & ATTN_SW_TIMER_4_FUNC)
3665 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3666
3667 if (asserted & GPIO_2_FUNC)
3668 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3669
3670 if (asserted & GPIO_3_FUNC)
3671 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3672
3673 if (asserted & GPIO_4_FUNC)
3674 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3675
3676 if (port == 0) {
3677 if (asserted & ATTN_GENERAL_ATTN_1) {
3678 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3679 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3680 }
3681 if (asserted & ATTN_GENERAL_ATTN_2) {
3682 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3683 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3684 }
3685 if (asserted & ATTN_GENERAL_ATTN_3) {
3686 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3687 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3688 }
3689 } else {
3690 if (asserted & ATTN_GENERAL_ATTN_4) {
3691 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3692 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3693 }
3694 if (asserted & ATTN_GENERAL_ATTN_5) {
3695 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3696 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3697 }
3698 if (asserted & ATTN_GENERAL_ATTN_6) {
3699 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3700 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3701 }
3702 }
3703
3704 } /* if hardwired */
3705
f2e0899f
DK		 3706 if (bp->common.int_block == INT_BLOCK_HC)
3707 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3708 COMMAND_REG_ATTN_BITS_SET);
3709 else
3710 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3711
3712 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3713 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3714 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3715
3716 /* now set back the mask */
a5e9a7cf 3717 if (asserted & ATTN_NIG_FOR_FUNC) {
27c1151c
YR		 3718 /* Verify that IGU ack through BAR was written before restoring
3719 * NIG mask. This loop should exit after 2-3 iterations max.
3720 */
3721 if (bp->common.int_block != INT_BLOCK_HC) {
3722 u32 cnt = 0, igu_acked;
3723 do {
3724 igu_acked = REG_RD(bp,
3725 IGU_REG_ATTENTION_ACK_BITS);
3726 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3727 (++cnt < MAX_IGU_ATTN_ACK_TO));
3728 if (!igu_acked)
3729 DP(NETIF_MSG_HW,
3730 "Failed to verify IGU ack on time\n");
3731 barrier();
3732 }
87942b46 3733 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 3734 bnx2x_release_phy_lock(bp);
3735 }
a2fbb9ea
ET		 3736}
3737
1191cb83 3738static void bnx2x_fan_failure(struct bnx2x *bp)
fd4ef40d
EG		 3739{
3740 int port = BP_PORT(bp);
b7737c9b 3741 u32 ext_phy_config;
fd4ef40d 3742 /* mark the failure */
b7737c9b
YR		 3743 ext_phy_config =
3744 SHMEM_RD(bp,
3745 dev_info.port_hw_config[port].external_phy_config);
3746
3747 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3748 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 3749 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 3750 ext_phy_config);
fd4ef40d
EG		 3751
3752 /* log the failure */
51c1a580
MS		 3753 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3754 "Please contact OEM Support for assistance\n");
8304859a
AE		 3755
3756 /*
3757 * Scheudle device reset (unload)
3758 * This is due to some boards consuming sufficient power when driver is
3759 * up to overheat if fan fails.
3760 */
3761 smp_mb__before_clear_bit();
3762 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3763 smp_mb__after_clear_bit();
3764 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3765
fd4ef40d 3766}
ab6ad5a4 3767
1191cb83 3768static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 3769{
34f80b04 3770 int port = BP_PORT(bp);
877e9aa4 3771 int reg_offset;
d90d96ba 3772 u32 val;
877e9aa4 3773
34f80b04
EG		 3774 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3775 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 3776
34f80b04 3777 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 3778
3779 val = REG_RD(bp, reg_offset);
3780 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3781 REG_WR(bp, reg_offset, val);
3782
3783 BNX2X_ERR("SPIO5 hw attention\n");
3784
fd4ef40d 3785 /* Fan failure attention */
d90d96ba 3786 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 3787 bnx2x_fan_failure(bp);
877e9aa4 3788 }
34f80b04 3789
3deb8167 3790 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 3791 bnx2x_acquire_phy_lock(bp);
3792 bnx2x_handle_module_detect_int(&bp->link_params);
3793 bnx2x_release_phy_lock(bp);
3794 }
3795
34f80b04
EG		 3796 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3797
3798 val = REG_RD(bp, reg_offset);
3799 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3800 REG_WR(bp, reg_offset, val);
3801
3802 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3803 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3804 bnx2x_panic();
3805 }
877e9aa4
ET		 3806}
3807
1191cb83 3808static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 3809{
3810 u32 val;
3811
0626b899 3812 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3813
3814 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3815 BNX2X_ERR("DB hw attention 0x%x\n", val);
3816 /* DORQ discard attention */
3817 if (val & 0x2)
3818 BNX2X_ERR("FATAL error from DORQ\n");
3819 }
34f80b04
EG		 3820
3821 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3822
3823 int port = BP_PORT(bp);
3824 int reg_offset;
3825
3826 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3827 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3828
3829 val = REG_RD(bp, reg_offset);
3830 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3831 REG_WR(bp, reg_offset, val);
3832
3833 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3834 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3835 bnx2x_panic();
3836 }
877e9aa4
ET		 3837}
3838
1191cb83 3839static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 3840{
3841 u32 val;
3842
3843 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3844
3845 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3846 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3847 /* CFC error attention */
3848 if (val & 0x2)
3849 BNX2X_ERR("FATAL error from CFC\n");
3850 }
3851
3852 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 3853 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 3854 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 3855 /* RQ_USDMDP_FIFO_OVERFLOW */
3856 if (val & 0x18000)
3857 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 3858
3859 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3860 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3861 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3862 }
877e9aa4 3863 }
34f80b04
EG		 3864
3865 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3866
3867 int port = BP_PORT(bp);
3868 int reg_offset;
3869
3870 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3871 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3872
3873 val = REG_RD(bp, reg_offset);
3874 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3875 REG_WR(bp, reg_offset, val);
3876
3877 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 3878 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 3879 bnx2x_panic();
3880 }
877e9aa4
ET		 3881}
3882
1191cb83 3883static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
877e9aa4 3884{
34f80b04
EG		 3885 u32 val;
3886
877e9aa4
ET		 3887 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3888
34f80b04
EG		 3889 if (attn & BNX2X_PMF_LINK_ASSERT) {
3890 int func = BP_FUNC(bp);
3891
3892 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
a3348722 3893 bnx2x_read_mf_cfg(bp);
f2e0899f
DK		 3894 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3895 func_mf_config[BP_ABS_FUNC(bp)].config);
3896 val = SHMEM_RD(bp,
3897 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 3898 if (val & DRV_STATUS_DCC_EVENT_MASK)
3899 bnx2x_dcc_event(bp,
3900 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 3901
3902 if (val & DRV_STATUS_SET_MF_BW)
3903 bnx2x_set_mf_bw(bp);
3904
1d187b34
BW		 3905 if (val & DRV_STATUS_DRV_INFO_REQ)
3906 bnx2x_handle_drv_info_req(bp);
2691d51d 3907 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 3908 bnx2x_pmf_update(bp);
3909
e4901dde 3910 if (bp->port.pmf &&
785b9b1a
SR		 3911 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3912 bp->dcbx_enabled > 0)
e4901dde
VZ		 3913 /* start dcbx state machine */
3914 bnx2x_dcbx_set_params(bp,
3915 BNX2X_DCBX_STATE_NEG_RECEIVED);
a3348722
BW		 3916 if (val & DRV_STATUS_AFEX_EVENT_MASK)
3917 bnx2x_handle_afex_cmd(bp,
3918 val & DRV_STATUS_AFEX_EVENT_MASK);
c8c60d88
YM		 3919 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3920 bnx2x_handle_eee_event(bp);
3deb8167
YR		 3921 if (bp->link_vars.periodic_flags &
3922 PERIODIC_FLAGS_LINK_EVENT) {
3923 /* sync with link */
3924 bnx2x_acquire_phy_lock(bp);
3925 bp->link_vars.periodic_flags &=
3926 ~PERIODIC_FLAGS_LINK_EVENT;
3927 bnx2x_release_phy_lock(bp);
3928 if (IS_MF(bp))
3929 bnx2x_link_sync_notify(bp);
3930 bnx2x_link_report(bp);
3931 }
3932 /* Always call it here: bnx2x_link_report() will
3933 * prevent the link indication duplication.
3934 */
3935 bnx2x__link_status_update(bp);
34f80b04 3936 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 3937
3938 BNX2X_ERR("MC assert!\n");
d6cae238 3939 bnx2x_mc_assert(bp);
877e9aa4
ET		 3940 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3941 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3942 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3943 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3944 bnx2x_panic();
3945
3946 } else if (attn & BNX2X_MCP_ASSERT) {
3947
3948 BNX2X_ERR("MCP assert!\n");
3949 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 3950 bnx2x_fw_dump(bp);
877e9aa4
ET		 3951
3952 } else
3953 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3954 }
3955
3956 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 3957 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3958 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 3959 val = CHIP_IS_E1(bp) ? 0 :
3960 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 3961 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3962 }
3963 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 3964 val = CHIP_IS_E1(bp) ? 0 :
3965 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 3966 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3967 }
877e9aa4 3968 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 3969 }
3970}
3971
c9ee9206
VZ		 3972/*
3973 * Bits map:
3974 * 0-7 - Engine0 load counter.
3975 * 8-15 - Engine1 load counter.
3976 * 16 - Engine0 RESET_IN_PROGRESS bit.
3977 * 17 - Engine1 RESET_IN_PROGRESS bit.
3978 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3979 * on the engine
3980 * 19 - Engine1 ONE_IS_LOADED.
3981 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3982 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3983 * just the one belonging to its engine).
3984 *
3985 */
3986#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3987
3988#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3989#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3990#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3991#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3992#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3993#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3994#define BNX2X_GLOBAL_RESET_BIT 0x00040000
3995
3996/*
3997 * Set the GLOBAL_RESET bit.
3998 *
3999 * Should be run under rtnl lock
4000 */
4001void bnx2x_set_reset_global(struct bnx2x *bp)
4002{
f16da43b
AE		 4003 u32 val;
4004 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4005 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4006 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
f16da43b 4007 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206
VZ		 4008}
4009
4010/*
4011 * Clear the GLOBAL_RESET bit.
4012 *
4013 * Should be run under rtnl lock
4014 */
1191cb83 4015static void bnx2x_clear_reset_global(struct bnx2x *bp)
c9ee9206 4016{
f16da43b
AE		 4017 u32 val;
4018 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4019 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4020 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
f16da43b 4021 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206 4022}
f85582f8 4023
72fd0718 4024/*
c9ee9206
VZ		 4025 * Checks the GLOBAL_RESET bit.
4026 *
72fd0718
VZ		 4027 * should be run under rtnl lock
4028 */
1191cb83 4029static bool bnx2x_reset_is_global(struct bnx2x *bp)
c9ee9206
VZ		 4030{
4031 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4032
4033 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4034 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4035}
4036
4037/*
4038 * Clear RESET_IN_PROGRESS bit for the current engine.
4039 *
4040 * Should be run under rtnl lock
4041 */
1191cb83 4042static void bnx2x_set_reset_done(struct bnx2x *bp)
72fd0718 4043{
f16da43b 4044 u32 val;
c9ee9206
VZ		 4045 u32 bit = BP_PATH(bp) ?
4046 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4047 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4048 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4049
4050 /* Clear the bit */
4051 val &= ~bit;
4052 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4053
4054 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4055}
4056
4057/*
c9ee9206
VZ		 4058 * Set RESET_IN_PROGRESS for the current engine.
4059 *
72fd0718
VZ		 4060 * should be run under rtnl lock
4061 */
c9ee9206 4062void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 4063{
f16da43b 4064 u32 val;
c9ee9206
VZ		 4065 u32 bit = BP_PATH(bp) ?
4066 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4067 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4068 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4069
4070 /* Set the bit */
4071 val |= bit;
4072 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4073 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4074}
4075
4076/*
c9ee9206 4077 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 4078 * should be run under rtnl lock
4079 */
c9ee9206 4080bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 4081{
c9ee9206
VZ		 4082 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4083 u32 bit = engine ?
4084 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4085
4086 /* return false if bit is set */
4087 return (val & bit) ? false : true;
72fd0718
VZ		 4088}
4089
4090/*
889b9af3 4091 * set pf load for the current pf.
c9ee9206 4092 *
72fd0718
VZ		 4093 * should be run under rtnl lock
4094 */
889b9af3 4095void bnx2x_set_pf_load(struct bnx2x *bp)
72fd0718 4096{
f16da43b 4097 u32 val1, val;
c9ee9206
VZ		 4098 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4099 BNX2X_PATH0_LOAD_CNT_MASK;
4100 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4101 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4102
f16da43b
AE		 4103 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4104 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4105
51c1a580 4106 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4107
c9ee9206
VZ		 4108 /* get the current counter value */
4109 val1 = (val & mask) >> shift;
4110
889b9af3
AE		 4111 /* set bit of that PF */
4112 val1 |= (1 << bp->pf_num);
c9ee9206
VZ		 4113
4114 /* clear the old value */
4115 val &= ~mask;
4116
4117 /* set the new one */
4118 val |= ((val1 << shift) & mask);
4119
4120 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4121 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4122}
4123
c9ee9206 4124/**
889b9af3 4125 * bnx2x_clear_pf_load - clear pf load mark
c9ee9206
VZ		 4126 *
4127 * @bp: driver handle
4128 *
4129 * Should be run under rtnl lock.
4130 * Decrements the load counter for the current engine. Returns
889b9af3 4131 * whether other functions are still loaded
72fd0718 4132 */
889b9af3 4133bool bnx2x_clear_pf_load(struct bnx2x *bp)
72fd0718 4134{
f16da43b 4135 u32 val1, val;
c9ee9206
VZ		 4136 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4137 BNX2X_PATH0_LOAD_CNT_MASK;
4138 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4139 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4140
f16da43b
AE		 4141 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4142 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
51c1a580 4143 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4144
c9ee9206
VZ		 4145 /* get the current counter value */
4146 val1 = (val & mask) >> shift;
4147
889b9af3
AE		 4148 /* clear bit of that PF */
4149 val1 &= ~(1 << bp->pf_num);
c9ee9206
VZ		 4150
4151 /* clear the old value */
4152 val &= ~mask;
4153
4154 /* set the new one */
4155 val |= ((val1 << shift) & mask);
4156
4157 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4158 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4159 return val1 != 0;
72fd0718
VZ		 4160}
4161
4162/*
889b9af3 4163 * Read the load status for the current engine.
c9ee9206 4164 *
72fd0718
VZ		 4165 * should be run under rtnl lock
4166 */
1191cb83 4167static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
72fd0718 4168{
c9ee9206
VZ		 4169 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4170 BNX2X_PATH0_LOAD_CNT_MASK);
4171 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4172 BNX2X_PATH0_LOAD_CNT_SHIFT);
4173 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4174
51c1a580 4175 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
c9ee9206
VZ		 4176
4177 val = (val & mask) >> shift;
4178
51c1a580
MS		 4179 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4180 engine, val);
c9ee9206 4181
889b9af3 4182 return val != 0;
72fd0718
VZ		 4183}
4184
1191cb83 4185static void _print_next_block(int idx, const char *blk)
72fd0718 4186{
f1deab50 4187 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 4188}
4189
1191cb83
ED		 4190static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4191 bool print)
72fd0718
VZ		 4192{
4193 int i = 0;
4194 u32 cur_bit = 0;
4195 for (i = 0; sig; i++) {
4196 cur_bit = ((u32)0x1 << i);
4197 if (sig & cur_bit) {
4198 switch (cur_bit) {
4199 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
c9ee9206
VZ		 4200 if (print)
4201 _print_next_block(par_num++, "BRB");
72fd0718
VZ		 4202 break;
4203 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
c9ee9206
VZ		 4204 if (print)
4205 _print_next_block(par_num++, "PARSER");
72fd0718
VZ		 4206 break;
4207 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
c9ee9206
VZ		 4208 if (print)
4209 _print_next_block(par_num++, "TSDM");
72fd0718
VZ		 4210 break;
4211 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
c9ee9206
VZ		 4212 if (print)
4213 _print_next_block(par_num++,
4214 "SEARCHER");
4215 break;
4216 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4217 if (print)
4218 _print_next_block(par_num++, "TCM");
72fd0718
VZ		 4219 break;
4220 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
c9ee9206
VZ		 4221 if (print)
4222 _print_next_block(par_num++, "TSEMI");
4223 break;
4224 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4225 if (print)
4226 _print_next_block(par_num++, "XPB");
72fd0718
VZ		 4227 break;
4228 }
4229
4230 /* Clear the bit */
4231 sig &= ~cur_bit;
4232 }
4233 }
4234
4235 return par_num;
4236}
4237
1191cb83
ED		 4238static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4239 bool *global, bool print)
72fd0718
VZ		 4240{
4241 int i = 0;
4242 u32 cur_bit = 0;
4243 for (i = 0; sig; i++) {
4244 cur_bit = ((u32)0x1 << i);
4245 if (sig & cur_bit) {
4246 switch (cur_bit) {
c9ee9206
VZ		 4247 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4248 if (print)
4249 _print_next_block(par_num++, "PBF");
72fd0718
VZ		 4250 break;
4251 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
c9ee9206
VZ		 4252 if (print)
4253 _print_next_block(par_num++, "QM");
4254 break;
4255 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4256 if (print)
4257 _print_next_block(par_num++, "TM");
72fd0718
VZ		 4258 break;
4259 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
c9ee9206
VZ		 4260 if (print)
4261 _print_next_block(par_num++, "XSDM");
4262 break;
4263 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4264 if (print)
4265 _print_next_block(par_num++, "XCM");
72fd0718
VZ		 4266 break;
4267 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
c9ee9206
VZ		 4268 if (print)
4269 _print_next_block(par_num++, "XSEMI");
72fd0718
VZ		 4270 break;
4271 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
c9ee9206
VZ		 4272 if (print)
4273 _print_next_block(par_num++,
4274 "DOORBELLQ");
4275 break;
4276 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4277 if (print)
4278 _print_next_block(par_num++, "NIG");
72fd0718
VZ		 4279 break;
4280 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206
VZ		 4281 if (print)
4282 _print_next_block(par_num++,
4283 "VAUX PCI CORE");
4284 *global = true;
72fd0718
VZ		 4285 break;
4286 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
c9ee9206
VZ		 4287 if (print)
4288 _print_next_block(par_num++, "DEBUG");
72fd0718
VZ		 4289 break;
4290 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
c9ee9206
VZ		 4291 if (print)
4292 _print_next_block(par_num++, "USDM");
72fd0718 4293 break;
8736c826
VZ		 4294 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4295 if (print)
4296 _print_next_block(par_num++, "UCM");
4297 break;
72fd0718 4298 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
c9ee9206
VZ		 4299 if (print)
4300 _print_next_block(par_num++, "USEMI");
72fd0718
VZ		 4301 break;
4302 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
c9ee9206
VZ		 4303 if (print)
4304 _print_next_block(par_num++, "UPB");
72fd0718
VZ		 4305 break;
4306 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
c9ee9206
VZ		 4307 if (print)
4308 _print_next_block(par_num++, "CSDM");
72fd0718 4309 break;
8736c826
VZ		 4310 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4311 if (print)
4312 _print_next_block(par_num++, "CCM");
4313 break;
72fd0718
VZ		 4314 }
4315
4316 /* Clear the bit */
4317 sig &= ~cur_bit;
4318 }
4319 }
4320
4321 return par_num;
4322}
4323
1191cb83
ED		 4324static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4325 bool print)
72fd0718
VZ		 4326{
4327 int i = 0;
4328 u32 cur_bit = 0;
4329 for (i = 0; sig; i++) {
4330 cur_bit = ((u32)0x1 << i);
4331 if (sig & cur_bit) {
4332 switch (cur_bit) {
4333 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
c9ee9206
VZ		 4334 if (print)
4335 _print_next_block(par_num++, "CSEMI");
72fd0718
VZ		 4336 break;
4337 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
c9ee9206
VZ		 4338 if (print)
4339 _print_next_block(par_num++, "PXP");
72fd0718
VZ		 4340 break;
4341 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
c9ee9206
VZ		 4342 if (print)
4343 _print_next_block(par_num++,
72fd0718
VZ		 4344 "PXPPCICLOCKCLIENT");
4345 break;
4346 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
c9ee9206
VZ		 4347 if (print)
4348 _print_next_block(par_num++, "CFC");
72fd0718
VZ		 4349 break;
4350 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
c9ee9206
VZ		 4351 if (print)
4352 _print_next_block(par_num++, "CDU");
4353 break;
4354 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4355 if (print)
4356 _print_next_block(par_num++, "DMAE");
72fd0718
VZ		 4357 break;
4358 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
c9ee9206
VZ		 4359 if (print)
4360 _print_next_block(par_num++, "IGU");
72fd0718
VZ		 4361 break;
4362 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
c9ee9206
VZ		 4363 if (print)
4364 _print_next_block(par_num++, "MISC");
72fd0718
VZ		 4365 break;
4366 }
4367
4368 /* Clear the bit */
4369 sig &= ~cur_bit;
4370 }
4371 }
4372
4373 return par_num;
4374}
4375
1191cb83
ED		 4376static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4377 bool *global, bool print)
72fd0718
VZ		 4378{
4379 int i = 0;
4380 u32 cur_bit = 0;
4381 for (i = 0; sig; i++) {
4382 cur_bit = ((u32)0x1 << i);
4383 if (sig & cur_bit) {
4384 switch (cur_bit) {
4385 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206
VZ		 4386 if (print)
4387 _print_next_block(par_num++, "MCP ROM");
4388 *global = true;
72fd0718
VZ		 4389 break;
4390 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206
VZ		 4391 if (print)
4392 _print_next_block(par_num++,
4393 "MCP UMP RX");
4394 *global = true;
72fd0718
VZ		 4395 break;
4396 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206
VZ		 4397 if (print)
4398 _print_next_block(par_num++,
4399 "MCP UMP TX");
4400 *global = true;
72fd0718
VZ		 4401 break;
4402 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206
VZ		 4403 if (print)
4404 _print_next_block(par_num++,
4405 "MCP SCPAD");
4406 *global = true;
72fd0718
VZ		 4407 break;
4408 }
4409
4410 /* Clear the bit */
4411 sig &= ~cur_bit;
4412 }
4413 }
4414
4415 return par_num;
4416}
4417
1191cb83
ED		 4418static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4419 bool print)
8736c826
VZ		 4420{
4421 int i = 0;
4422 u32 cur_bit = 0;
4423 for (i = 0; sig; i++) {
4424 cur_bit = ((u32)0x1 << i);
4425 if (sig & cur_bit) {
4426 switch (cur_bit) {
4427 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4428 if (print)
4429 _print_next_block(par_num++, "PGLUE_B");
4430 break;
4431 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4432 if (print)
4433 _print_next_block(par_num++, "ATC");
4434 break;
4435 }
4436
4437 /* Clear the bit */
4438 sig &= ~cur_bit;
4439 }
4440 }
4441
4442 return par_num;
4443}
4444
1191cb83
ED		 4445static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4446 u32 *sig)
72fd0718 4447{
8736c826
VZ		 4448 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4449 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4450 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4451 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4452 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718 4453 int par_num = 0;
51c1a580
MS		 4454 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4455 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
8736c826
VZ		 4456 sig[0] & HW_PRTY_ASSERT_SET_0,
4457 sig[1] & HW_PRTY_ASSERT_SET_1,
4458 sig[2] & HW_PRTY_ASSERT_SET_2,
4459 sig[3] & HW_PRTY_ASSERT_SET_3,
4460 sig[4] & HW_PRTY_ASSERT_SET_4);
c9ee9206
VZ		 4461 if (print)
4462 netdev_err(bp->dev,
4463 "Parity errors detected in blocks: ");
4464 par_num = bnx2x_check_blocks_with_parity0(
8736c826 4465 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
c9ee9206 4466 par_num = bnx2x_check_blocks_with_parity1(
8736c826 4467 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
c9ee9206 4468 par_num = bnx2x_check_blocks_with_parity2(
8736c826 4469 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
c9ee9206 4470 par_num = bnx2x_check_blocks_with_parity3(
8736c826
VZ		 4471 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4472 par_num = bnx2x_check_blocks_with_parity4(
4473 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4474
c9ee9206
VZ		 4475 if (print)
4476 pr_cont("\n");
8736c826 4477
72fd0718
VZ		 4478 return true;
4479 } else
4480 return false;
4481}
4482
c9ee9206
VZ		 4483/**
4484 * bnx2x_chk_parity_attn - checks for parity attentions.
4485 *
4486 * @bp: driver handle
4487 * @global: true if there was a global attention
4488 * @print: show parity attention in syslog
4489 */
4490bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 4491{
8736c826 4492 struct attn_route attn = { {0} };
72fd0718
VZ		 4493 int port = BP_PORT(bp);
4494
4495 attn.sig[0] = REG_RD(bp,
4496 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4497 port*4);
4498 attn.sig[1] = REG_RD(bp,
4499 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4500 port*4);
4501 attn.sig[2] = REG_RD(bp,
4502 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4503 port*4);
4504 attn.sig[3] = REG_RD(bp,
4505 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4506 port*4);
4507
8736c826
VZ		 4508 if (!CHIP_IS_E1x(bp))
4509 attn.sig[4] = REG_RD(bp,
4510 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4511 port*4);
4512
4513 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 4514}
4515
f2e0899f 4516
1191cb83 4517static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
f2e0899f
DK		 4518{
4519 u32 val;
4520 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4521
4522 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4523 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4524 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
51c1a580 4525 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
f2e0899f 4526 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
51c1a580 4527 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
f2e0899f 4528 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
51c1a580 4529 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
f2e0899f 4530 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
51c1a580 4531 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
f2e0899f
DK		 4532 if (val &
4533 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
51c1a580 4534 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
f2e0899f
DK		 4535 if (val &
4536 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
51c1a580 4537 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
f2e0899f 4538 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
51c1a580 4539 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
f2e0899f 4540 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
51c1a580 4541 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
f2e0899f 4542 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
51c1a580 4543 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
f2e0899f
DK		 4544 }
4545 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4546 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4547 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4548 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4549 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4550 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
51c1a580 4551 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
f2e0899f 4552 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
51c1a580 4553 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
f2e0899f 4554 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
51c1a580 4555 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
f2e0899f
DK		 4556 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4557 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4558 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
51c1a580 4559 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
f2e0899f
DK		 4560 }
4561
4562 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4563 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4564 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4565 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4566 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4567 }
4568
4569}
4570
72fd0718
VZ		 4571static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4572{
4573 struct attn_route attn, *group_mask;
34f80b04 4574 int port = BP_PORT(bp);
877e9aa4 4575 int index;
a2fbb9ea
ET		 4576 u32 reg_addr;
4577 u32 val;
3fcaf2e5 4578 u32 aeu_mask;
c9ee9206 4579 bool global = false;
a2fbb9ea
ET		 4580
4581 /* need to take HW lock because MCP or other port might also
4582 try to handle this event */
4a37fb66 4583 bnx2x_acquire_alr(bp);
a2fbb9ea 4584
c9ee9206
VZ		 4585 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4586#ifndef BNX2X_STOP_ON_ERROR
72fd0718 4587 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 4588 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 4589 /* Disable HW interrupts */
4590 bnx2x_int_disable(bp);
72fd0718
VZ		 4591 /* In case of parity errors don't handle attentions so that
4592 * other function would "see" parity errors.
4593 */
c9ee9206
VZ		 4594#else
4595 bnx2x_panic();
4596#endif
4597 bnx2x_release_alr(bp);
72fd0718
VZ		 4598 return;
4599 }
4600
a2fbb9ea
ET		 4601 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4602 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4603 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4604 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 4605 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4606 attn.sig[4] =
4607 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4608 else
4609 attn.sig[4] = 0;
4610
4611 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4612 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 4613
4614 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4615 if (deasserted & (1 << index)) {
72fd0718 4616 group_mask = &bp->attn_group[index];
a2fbb9ea 4617
51c1a580 4618 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
f2e0899f
DK		 4619 index,
4620 group_mask->sig[0], group_mask->sig[1],
4621 group_mask->sig[2], group_mask->sig[3],
4622 group_mask->sig[4]);
a2fbb9ea 4623
f2e0899f
DK		 4624 bnx2x_attn_int_deasserted4(bp,
4625 attn.sig[4] & group_mask->sig[4]);
877e9aa4 4626 bnx2x_attn_int_deasserted3(bp,
72fd0718 4627 attn.sig[3] & group_mask->sig[3]);
877e9aa4 4628 bnx2x_attn_int_deasserted1(bp,
72fd0718 4629 attn.sig[1] & group_mask->sig[1]);
877e9aa4 4630 bnx2x_attn_int_deasserted2(bp,
72fd0718 4631 attn.sig[2] & group_mask->sig[2]);
877e9aa4 4632 bnx2x_attn_int_deasserted0(bp,
72fd0718 4633 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 4634 }
4635 }
4636
4a37fb66 4637 bnx2x_release_alr(bp);
a2fbb9ea 4638
f2e0899f
DK		 4639 if (bp->common.int_block == INT_BLOCK_HC)
4640 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4641 COMMAND_REG_ATTN_BITS_CLR);
4642 else
4643 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 4644
4645 val = ~deasserted;
f2e0899f
DK		 4646 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4647 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 4648 REG_WR(bp, reg_addr, val);
a2fbb9ea 4649
a2fbb9ea 4650 if (~bp->attn_state & deasserted)
3fcaf2e5 4651 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 4652
4653 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4654 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4655
3fcaf2e5
EG		 4656 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4657 aeu_mask = REG_RD(bp, reg_addr);
4658
4659 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4660 aeu_mask, deasserted);
72fd0718 4661 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 4662 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 4663
3fcaf2e5
EG		 4664 REG_WR(bp, reg_addr, aeu_mask);
4665 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 4666
4667 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4668 bp->attn_state &= ~deasserted;
4669 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4670}
4671
4672static void bnx2x_attn_int(struct bnx2x *bp)
4673{
4674 /* read local copy of bits */
68d59484
EG		 4675 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4676 attn_bits);
4677 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4678 attn_bits_ack);
a2fbb9ea
ET		 4679 u32 attn_state = bp->attn_state;
4680
4681 /* look for changed bits */
4682 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4683 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4684
4685 DP(NETIF_MSG_HW,
4686 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4687 attn_bits, attn_ack, asserted, deasserted);
4688
4689 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 4690 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 4691
4692 /* handle bits that were raised */
4693 if (asserted)
4694 bnx2x_attn_int_asserted(bp, asserted);
4695
4696 if (deasserted)
4697 bnx2x_attn_int_deasserted(bp, deasserted);
4698}
4699
619c5cb6
VZ		 4700void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4701 u16 index, u8 op, u8 update)
4702{
dc1ba591
AE		 4703 u32 igu_addr = bp->igu_base_addr;
4704 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
619c5cb6
VZ		 4705 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4706 igu_addr);
4707}
4708
1191cb83 4709static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
523224a3
DK		 4710{
4711 /* No memory barriers */
4712 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4713 mmiowb(); /* keep prod updates ordered */
4714}
4715
523224a3
DK		 4716static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4717 union event_ring_elem *elem)
4718{
619c5cb6
VZ		 4719 u8 err = elem->message.error;
4720
523224a3 4721 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 4722 (cid < bp->cnic_eth_dev.starting_cid &&
4723 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 4724 return 1;
4725
4726 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4727
619c5cb6
VZ		 4728 if (unlikely(err)) {
4729
523224a3
DK		 4730 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4731 cid);
4732 bnx2x_panic_dump(bp);
4733 }
619c5cb6 4734 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 4735 return 0;
4736}
523224a3 4737
1191cb83 4738static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
619c5cb6
VZ		 4739{
4740 struct bnx2x_mcast_ramrod_params rparam;
4741 int rc;
4742
4743 memset(&rparam, 0, sizeof(rparam));
4744
4745 rparam.mcast_obj = &bp->mcast_obj;
4746
4747 netif_addr_lock_bh(bp->dev);
4748
4749 /* Clear pending state for the last command */
4750 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4751
4752 /* If there are pending mcast commands - send them */
4753 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4754 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4755 if (rc < 0)
4756 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4757 rc);
4758 }
4759
4760 netif_addr_unlock_bh(bp->dev);
4761}
4762
1191cb83
ED		 4763static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4764 union event_ring_elem *elem)
619c5cb6
VZ		 4765{
4766 unsigned long ramrod_flags = 0;
4767 int rc = 0;
4768 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4769 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4770
4771 /* Always push next commands out, don't wait here */
4772 __set_bit(RAMROD_CONT, &ramrod_flags);
4773
4774 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4775 case BNX2X_FILTER_MAC_PENDING:
51c1a580 4776 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
55c11941 4777 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
619c5cb6
VZ		 4778 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4779 else
15192a8c 4780 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
619c5cb6
VZ		 4781
4782 break;
619c5cb6 4783 case BNX2X_FILTER_MCAST_PENDING:
51c1a580 4784 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
619c5cb6
VZ		 4785 /* This is only relevant for 57710 where multicast MACs are
4786 * configured as unicast MACs using the same ramrod.
4787 */
4788 bnx2x_handle_mcast_eqe(bp);
4789 return;
4790 default:
4791 BNX2X_ERR("Unsupported classification command: %d\n",
4792 elem->message.data.eth_event.echo);
4793 return;
4794 }
4795
4796 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4797
4798 if (rc < 0)
4799 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4800 else if (rc > 0)
4801 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4802
4803}
4804
619c5cb6 4805static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
619c5cb6 4806
1191cb83 4807static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
619c5cb6
VZ		 4808{
4809 netif_addr_lock_bh(bp->dev);
4810
4811 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4812
4813 /* Send rx_mode command again if was requested */
4814 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4815 bnx2x_set_storm_rx_mode(bp);
619c5cb6
VZ		 4816 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4817 &bp->sp_state))
4818 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4819 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4820 &bp->sp_state))
4821 bnx2x_set_iscsi_eth_rx_mode(bp, false);
619c5cb6
VZ		 4822
4823 netif_addr_unlock_bh(bp->dev);
4824}
4825
1191cb83 4826static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
a3348722
BW		 4827 union event_ring_elem *elem)
4828{
4829 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4830 DP(BNX2X_MSG_SP,
4831 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4832 elem->message.data.vif_list_event.func_bit_map);
4833 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4834 elem->message.data.vif_list_event.func_bit_map);
4835 } else if (elem->message.data.vif_list_event.echo ==
4836 VIF_LIST_RULE_SET) {
4837 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4838 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4839 }
4840}
4841
4842/* called with rtnl_lock */
1191cb83 4843static void bnx2x_after_function_update(struct bnx2x *bp)
a3348722
BW		 4844{
4845 int q, rc;
4846 struct bnx2x_fastpath *fp;
4847 struct bnx2x_queue_state_params queue_params = {NULL};
4848 struct bnx2x_queue_update_params *q_update_params =
4849 &queue_params.params.update;
4850
4851 /* Send Q update command with afex vlan removal values for all Qs */
4852 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4853
4854 /* set silent vlan removal values according to vlan mode */
4855 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4856 &q_update_params->update_flags);
4857 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4858 &q_update_params->update_flags);
4859 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4860
4861 /* in access mode mark mask and value are 0 to strip all vlans */
4862 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4863 q_update_params->silent_removal_value = 0;
4864 q_update_params->silent_removal_mask = 0;
4865 } else {
4866 q_update_params->silent_removal_value =
4867 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4868 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4869 }
4870
4871 for_each_eth_queue(bp, q) {
4872 /* Set the appropriate Queue object */
4873 fp = &bp->fp[q];
15192a8c 4874 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 4875
4876 /* send the ramrod */
4877 rc = bnx2x_queue_state_change(bp, &queue_params);
4878 if (rc < 0)
4879 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4880 q);
4881 }
4882
a3348722 4883 if (!NO_FCOE(bp)) {
65565884 4884 fp = &bp->fp[FCOE_IDX(bp)];
15192a8c 4885 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 4886
4887 /* clear pending completion bit */
4888 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4889
4890 /* mark latest Q bit */
4891 smp_mb__before_clear_bit();
4892 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4893 smp_mb__after_clear_bit();
4894
4895 /* send Q update ramrod for FCoE Q */
4896 rc = bnx2x_queue_state_change(bp, &queue_params);
4897 if (rc < 0)
4898 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4899 q);
4900 } else {
4901 /* If no FCoE ring - ACK MCP now */
4902 bnx2x_link_report(bp);
4903 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4904 }
a3348722
BW		 4905}
4906
1191cb83 4907static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
619c5cb6
VZ		 4908 struct bnx2x *bp, u32 cid)
4909{
94f05b0f 4910 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
55c11941
MS		 4911
4912 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
15192a8c 4913 return &bnx2x_fcoe_sp_obj(bp, q_obj);
619c5cb6 4914 else
15192a8c 4915 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
619c5cb6
VZ		 4916}
4917
523224a3
DK		 4918static void bnx2x_eq_int(struct bnx2x *bp)
4919{
4920 u16 hw_cons, sw_cons, sw_prod;
4921 union event_ring_elem *elem;
55c11941 4922 u8 echo;
523224a3
DK		 4923 u32 cid;
4924 u8 opcode;
fd1fc79d 4925 int rc, spqe_cnt = 0;
619c5cb6
VZ		 4926 struct bnx2x_queue_sp_obj *q_obj;
4927 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4928 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 4929
4930 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4931
4932 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4933 * when we get the the next-page we nned to adjust so the loop
4934 * condition below will be met. The next element is the size of a
4935 * regular element and hence incrementing by 1
4936 */
4937 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4938 hw_cons++;
4939
25985edc 4940 /* This function may never run in parallel with itself for a
523224a3
DK		 4941 * specific bp, thus there is no need in "paired" read memory
4942 * barrier here.
4943 */
4944 sw_cons = bp->eq_cons;
4945 sw_prod = bp->eq_prod;
4946
d6cae238 4947 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 4948 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 4949
4950 for (; sw_cons != hw_cons;
4951 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4952
4953
4954 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4955
fd1fc79d
AE		 4956 rc = bnx2x_iov_eq_sp_event(bp, elem);
4957 if (!rc) {
4958 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
4959 rc);
4960 goto next_spqe;
4961 }
523224a3
DK		 4962 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4963 opcode = elem->message.opcode;
4964
4965
4966 /* handle eq element */
4967 switch (opcode) {
fd1fc79d
AE		 4968 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
4969 DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
4970 bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
4971 continue;
4972
523224a3 4973 case EVENT_RING_OPCODE_STAT_QUERY:
51c1a580
MS		 4974 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
4975 "got statistics comp event %d\n",
619c5cb6 4976 bp->stats_comp++);
523224a3 4977 /* nothing to do with stats comp */
d6cae238 4978 goto next_spqe;
523224a3
DK		 4979
4980 case EVENT_RING_OPCODE_CFC_DEL:
4981 /* handle according to cid range */
4982 /*
4983 * we may want to verify here that the bp state is
4984 * HALTING
4985 */
d6cae238 4986 DP(BNX2X_MSG_SP,
523224a3 4987 "got delete ramrod for MULTI[%d]\n", cid);
55c11941
MS		 4988
4989 if (CNIC_LOADED(bp) &&
4990 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
523224a3 4991 goto next_spqe;
55c11941 4992
619c5cb6
VZ		 4993 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4994
4995 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4996 break;
4997
4998
523224a3
DK		 4999
5000 goto next_spqe;
e4901dde
VZ		 5001
5002 case EVENT_RING_OPCODE_STOP_TRAFFIC:
51c1a580 5003 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
6debea87
DK		 5004 if (f_obj->complete_cmd(bp, f_obj,
5005 BNX2X_F_CMD_TX_STOP))
5006 break;
e4901dde
VZ		 5007 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5008 goto next_spqe;
619c5cb6 5009
e4901dde 5010 case EVENT_RING_OPCODE_START_TRAFFIC:
51c1a580 5011 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
6debea87
DK		 5012 if (f_obj->complete_cmd(bp, f_obj,
5013 BNX2X_F_CMD_TX_START))
5014 break;
e4901dde
VZ		 5015 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5016 goto next_spqe;
55c11941 5017
a3348722 5018 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
55c11941
MS		 5019 echo = elem->message.data.function_update_event.echo;
5020 if (echo == SWITCH_UPDATE) {
5021 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5022 "got FUNC_SWITCH_UPDATE ramrod\n");
5023 if (f_obj->complete_cmd(
5024 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5025 break;
a3348722 5026
55c11941
MS		 5027 } else {
5028 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5029 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5030 f_obj->complete_cmd(bp, f_obj,
5031 BNX2X_F_CMD_AFEX_UPDATE);
5032
5033 /* We will perform the Queues update from
5034 * sp_rtnl task as all Queue SP operations
5035 * should run under rtnl_lock.
5036 */
5037 smp_mb__before_clear_bit();
5038 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5039 &bp->sp_rtnl_state);
5040 smp_mb__after_clear_bit();
5041
5042 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5043 }
a3348722 5044
a3348722
BW		 5045 goto next_spqe;
5046
5047 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5048 f_obj->complete_cmd(bp, f_obj,
5049 BNX2X_F_CMD_AFEX_VIFLISTS);
5050 bnx2x_after_afex_vif_lists(bp, elem);
5051 goto next_spqe;
619c5cb6 5052 case EVENT_RING_OPCODE_FUNCTION_START:
51c1a580
MS		 5053 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5054 "got FUNC_START ramrod\n");
619c5cb6
VZ		 5055 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5056 break;
5057
5058 goto next_spqe;
5059
5060 case EVENT_RING_OPCODE_FUNCTION_STOP:
51c1a580
MS		 5061 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5062 "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 5063 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5064 break;
5065
5066 goto next_spqe;
523224a3
DK		 5067 }
5068
5069 switch (opcode | bp->state) {
619c5cb6
VZ		 5070 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5071 BNX2X_STATE_OPEN):
5072 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 5073 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 5074 cid = elem->message.data.eth_event.echo &
5075 BNX2X_SWCID_MASK;
d6cae238 5076 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
619c5cb6
VZ		 5077 cid);
5078 rss_raw->clear_pending(rss_raw);
523224a3
DK		 5079 break;
5080
619c5cb6
VZ		 5081 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5082 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5083 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 5084 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 5085 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5086 BNX2X_STATE_OPEN):
5087 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5088 BNX2X_STATE_DIAG):
5089 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5090 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5091 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
619c5cb6 5092 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 5093 break;
5094
619c5cb6
VZ		 5095 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5096 BNX2X_STATE_OPEN):
5097 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5098 BNX2X_STATE_DIAG):
5099 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5100 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5101 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 5102 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 5103 break;
5104
619c5cb6
VZ		 5105 case (EVENT_RING_OPCODE_FILTERS_RULES |
5106 BNX2X_STATE_OPEN):
5107 case (EVENT_RING_OPCODE_FILTERS_RULES |
5108 BNX2X_STATE_DIAG):
5109 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 5110 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5111 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 5112 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 5113 break;
5114 default:
5115 /* unknown event log error and continue */
619c5cb6
VZ		 5116 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5117 elem->message.opcode, bp->state);
523224a3
DK		 5118 }
5119next_spqe:
5120 spqe_cnt++;
5121 } /* for */
5122
8fe23fbd 5123 smp_mb__before_atomic_inc();
6e30dd4e 5124 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 5125
5126 bp->eq_cons = sw_cons;
5127 bp->eq_prod = sw_prod;
5128 /* Make sure that above mem writes were issued towards the memory */
5129 smp_wmb();
5130
5131 /* update producer */
5132 bnx2x_update_eq_prod(bp, bp->eq_prod);
5133}
5134
a2fbb9ea
ET		 5135static void bnx2x_sp_task(struct work_struct *work)
5136{
1cf167f2 5137 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea 5138
fd1fc79d 5139 DP(BNX2X_MSG_SP, "sp task invoked\n");
a2fbb9ea 5140
fd1fc79d
AE		 5141 /* make sure the atomic interupt_occurred has been written */
5142 smp_rmb();
5143 if (atomic_read(&bp->interrupt_occurred)) {
a2fbb9ea 5144
fd1fc79d
AE		 5145 /* what work needs to be performed? */
5146 u16 status = bnx2x_update_dsb_idx(bp);
cdaa7cb8 5147
fd1fc79d
AE		 5148 DP(BNX2X_MSG_SP, "status %x\n", status);
5149 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5150 atomic_set(&bp->interrupt_occurred, 0);
5151
5152 /* HW attentions */
5153 if (status & BNX2X_DEF_SB_ATT_IDX) {
5154 bnx2x_attn_int(bp);
5155 status &= ~BNX2X_DEF_SB_ATT_IDX;
5156 }
5157
5158 /* SP events: STAT_QUERY and others */
5159 if (status & BNX2X_DEF_SB_IDX) {
5160 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 5161
55c11941 5162 if (FCOE_INIT(bp) &&
fd1fc79d
AE		 5163 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5164 /* Prevent local bottom-halves from running as
5165 * we are going to change the local NAPI list.
5166 */
5167 local_bh_disable();
5168 napi_schedule(&bnx2x_fcoe(bp, napi));
5169 local_bh_enable();
5170 }
5171
5172 /* Handle EQ completions */
5173 bnx2x_eq_int(bp);
5174 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5175 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5176
5177 status &= ~BNX2X_DEF_SB_IDX;
019dbb4c 5178 }
55c11941 5179
fd1fc79d
AE		 5180 /* if status is non zero then perhaps something went wrong */
5181 if (unlikely(status))
5182 DP(BNX2X_MSG_SP,
5183 "got an unknown interrupt! (status 0x%x)\n", status);
523224a3 5184
fd1fc79d
AE		 5185 /* ack status block only if something was actually handled */
5186 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5187 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
523224a3 5188
cdaa7cb8
VZ		 5189 }
5190
fd1fc79d
AE		 5191 /* must be called after the EQ processing (since eq leads to sriov
5192 * ramrod completion flows).
5193 * This flow may have been scheduled by the arrival of a ramrod
5194 * completion, or by the sriov code rescheduling itself.
5195 */
5196 bnx2x_iov_sp_task(bp);
a3348722
BW		 5197
5198 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5199 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5200 &bp->sp_state)) {
5201 bnx2x_link_report(bp);
5202 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5203 }
a2fbb9ea
ET		 5204}
5205
9f6c9258 5206irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 5207{
5208 struct net_device *dev = dev_instance;
5209 struct bnx2x *bp = netdev_priv(dev);
5210
523224a3
DK		 5211 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5212 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 5213
5214#ifdef BNX2X_STOP_ON_ERROR
5215 if (unlikely(bp->panic))
5216 return IRQ_HANDLED;
5217#endif
5218
55c11941 5219 if (CNIC_LOADED(bp)) {
993ac7b5
MC		 5220 struct cnic_ops *c_ops;
5221
5222 rcu_read_lock();
5223 c_ops = rcu_dereference(bp->cnic_ops);
5224 if (c_ops)
5225 c_ops->cnic_handler(bp->cnic_data, NULL);
5226 rcu_read_unlock();
5227 }
55c11941 5228
fd1fc79d
AE		 5229 /* schedule sp task to perform default status block work, ack
5230 * attentions and enable interrupts.
5231 */
5232 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 5233
5234 return IRQ_HANDLED;
5235}
5236
5237/* end of slow path */
5238
619c5cb6
VZ		 5239
5240void bnx2x_drv_pulse(struct bnx2x *bp)
5241{
5242 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5243 bp->fw_drv_pulse_wr_seq);
5244}
5245
5246
a2fbb9ea
ET		 5247static void bnx2x_timer(unsigned long data)
5248{
5249 struct bnx2x *bp = (struct bnx2x *) data;
5250
5251 if (!netif_running(bp->dev))
5252 return;
5253
34f80b04 5254 if (!BP_NOMCP(bp)) {
f2e0899f 5255 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 5256 u32 drv_pulse;
5257 u32 mcp_pulse;
5258
5259 ++bp->fw_drv_pulse_wr_seq;
5260 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5261 /* TBD - add SYSTEM_TIME */
5262 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 5263 bnx2x_drv_pulse(bp);
a2fbb9ea 5264
f2e0899f 5265 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 5266 MCP_PULSE_SEQ_MASK);
5267 /* The delta between driver pulse and mcp response
5268 * should be 1 (before mcp response) or 0 (after mcp response)
5269 */
5270 if ((drv_pulse != mcp_pulse) &&
5271 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5272 /* someone lost a heartbeat... */
5273 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5274 drv_pulse, mcp_pulse);
5275 }
5276 }
5277
f34d28ea 5278 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 5279 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 5280
a2fbb9ea
ET		 5281 mod_timer(&bp->timer, jiffies + bp->current_interval);
5282}
5283
5284/* end of Statistics */
5285
5286/* nic init */
5287
5288/*
5289 * nic init service functions
5290 */
5291
1191cb83 5292static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 5293{
523224a3
DK		 5294 u32 i;
5295 if (!(len%4) && !(addr%4))
5296 for (i = 0; i < len; i += 4)
5297 REG_WR(bp, addr + i, fill);
5298 else
5299 for (i = 0; i < len; i++)
5300 REG_WR8(bp, addr + i, fill);
34f80b04 5301
34f80b04
EG		 5302}
5303
523224a3 5304/* helper: writes FP SP data to FW - data_size in dwords */
1191cb83
ED		 5305static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5306 int fw_sb_id,
5307 u32 *sb_data_p,
5308 u32 data_size)
34f80b04 5309{
a2fbb9ea 5310 int index;
523224a3
DK		 5311 for (index = 0; index < data_size; index++)
5312 REG_WR(bp, BAR_CSTRORM_INTMEM +
5313 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5314 sizeof(u32)*index,
5315 *(sb_data_p + index));
5316}
a2fbb9ea 5317
1191cb83 5318static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
523224a3
DK		 5319{
5320 u32 *sb_data_p;
5321 u32 data_size = 0;
f2e0899f 5322 struct hc_status_block_data_e2 sb_data_e2;
523224a3 5323 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 5324
523224a3 5325 /* disable the function first */
619c5cb6 5326 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5327 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5328 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 5329 sb_data_e2.common.p_func.vf_valid = false;
5330 sb_data_p = (u32 *)&sb_data_e2;
5331 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5332 } else {
5333 memset(&sb_data_e1x, 0,
5334 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5335 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 5336 sb_data_e1x.common.p_func.vf_valid = false;
5337 sb_data_p = (u32 *)&sb_data_e1x;
5338 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5339 }
523224a3 5340 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 5341
523224a3
DK		 5342 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5343 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5344 CSTORM_STATUS_BLOCK_SIZE);
5345 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5346 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5347 CSTORM_SYNC_BLOCK_SIZE);
5348}
34f80b04 5349
523224a3 5350/* helper: writes SP SB data to FW */
1191cb83 5351static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
523224a3
DK		 5352 struct hc_sp_status_block_data *sp_sb_data)
5353{
5354 int func = BP_FUNC(bp);
5355 int i;
5356 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5357 REG_WR(bp, BAR_CSTRORM_INTMEM +
5358 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5359 i*sizeof(u32),
5360 *((u32 *)sp_sb_data + i));
34f80b04
EG		 5361}
5362
1191cb83 5363static void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 5364{
5365 int func = BP_FUNC(bp);
523224a3
DK		 5366 struct hc_sp_status_block_data sp_sb_data;
5367 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 5368
619c5cb6 5369 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 5370 sp_sb_data.p_func.vf_valid = false;
5371
5372 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5373
5374 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5375 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5376 CSTORM_SP_STATUS_BLOCK_SIZE);
5377 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5378 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5379 CSTORM_SP_SYNC_BLOCK_SIZE);
5380
5381}
5382
5383
1191cb83 5384static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
523224a3
DK		 5385 int igu_sb_id, int igu_seg_id)
5386{
5387 hc_sm->igu_sb_id = igu_sb_id;
5388 hc_sm->igu_seg_id = igu_seg_id;
5389 hc_sm->timer_value = 0xFF;
5390 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 5391}
5392
150966ad
AE		 5393
5394/* allocates state machine ids. */
1191cb83 5395static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
150966ad
AE		 5396{
5397 /* zero out state machine indices */
5398 /* rx indices */
5399 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5400
5401 /* tx indices */
5402 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5403 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5404 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5405 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5406
5407 /* map indices */
5408 /* rx indices */
5409 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5410 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5411
5412 /* tx indices */
5413 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5414 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5415 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5416 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5417 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5418 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5419 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5420 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5421}
5422
8d96286a 5423static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 5424 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 5425{
523224a3
DK		 5426 int igu_seg_id;
5427
f2e0899f 5428 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 5429 struct hc_status_block_data_e1x sb_data_e1x;
5430 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 5431 int data_size;
5432 u32 *sb_data_p;
5433
f2e0899f
DK		 5434 if (CHIP_INT_MODE_IS_BC(bp))
5435 igu_seg_id = HC_SEG_ACCESS_NORM;
5436 else
5437 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 5438
5439 bnx2x_zero_fp_sb(bp, fw_sb_id);
5440
619c5cb6 5441 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5442 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5443 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 5444 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5445 sb_data_e2.common.p_func.vf_id = vfid;
5446 sb_data_e2.common.p_func.vf_valid = vf_valid;
5447 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5448 sb_data_e2.common.same_igu_sb_1b = true;
5449 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5450 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5451 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 5452 sb_data_p = (u32 *)&sb_data_e2;
5453 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 5454 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 5455 } else {
5456 memset(&sb_data_e1x, 0,
5457 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5458 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 5459 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5460 sb_data_e1x.common.p_func.vf_id = 0xff;
5461 sb_data_e1x.common.p_func.vf_valid = false;
5462 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5463 sb_data_e1x.common.same_igu_sb_1b = true;
5464 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5465 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5466 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 5467 sb_data_p = (u32 *)&sb_data_e1x;
5468 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 5469 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 5470 }
523224a3
DK		 5471
5472 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5473 igu_sb_id, igu_seg_id);
5474 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5475 igu_sb_id, igu_seg_id);
5476
51c1a580 5477 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
523224a3
DK		 5478
5479 /* write indecies to HW */
5480 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5481}
5482
619c5cb6 5483static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 5484 u16 tx_usec, u16 rx_usec)
5485{
6383c0b3 5486 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 5487 false, rx_usec);
6383c0b3
AE		 5488 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5489 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5490 tx_usec);
5491 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5492 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5493 tx_usec);
5494 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5495 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5496 tx_usec);
523224a3 5497}
f2e0899f 5498
523224a3
DK		 5499static void bnx2x_init_def_sb(struct bnx2x *bp)
5500{
5501 struct host_sp_status_block *def_sb = bp->def_status_blk;
5502 dma_addr_t mapping = bp->def_status_blk_mapping;
5503 int igu_sp_sb_index;
5504 int igu_seg_id;
34f80b04
EG		 5505 int port = BP_PORT(bp);
5506 int func = BP_FUNC(bp);
f2eaeb58 5507 int reg_offset, reg_offset_en5;
a2fbb9ea 5508 u64 section;
523224a3
DK		 5509 int index;
5510 struct hc_sp_status_block_data sp_sb_data;
5511 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5512
f2e0899f
DK		 5513 if (CHIP_INT_MODE_IS_BC(bp)) {
5514 igu_sp_sb_index = DEF_SB_IGU_ID;
5515 igu_seg_id = HC_SEG_ACCESS_DEF;
5516 } else {
5517 igu_sp_sb_index = bp->igu_dsb_id;
5518 igu_seg_id = IGU_SEG_ACCESS_DEF;
5519 }
a2fbb9ea
ET		 5520
5521 /* ATTN */
523224a3 5522 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 5523 atten_status_block);
523224a3 5524 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 5525
49d66772
ET		 5526 bp->attn_state = 0;
5527
a2fbb9ea
ET		 5528 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5529 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 5530 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5531 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 5532 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 5533 int sindex;
5534 /* take care of sig[0]..sig[4] */
5535 for (sindex = 0; sindex < 4; sindex++)
5536 bp->attn_group[index].sig[sindex] =
5537 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 5538
619c5cb6 5539 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5540 /*
5541 * enable5 is separate from the rest of the registers,
5542 * and therefore the address skip is 4
5543 * and not 16 between the different groups
5544 */
5545 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 5546 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 5547 else
5548 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 5549 }
5550
f2e0899f
DK		 5551 if (bp->common.int_block == INT_BLOCK_HC) {
5552 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5553 HC_REG_ATTN_MSG0_ADDR_L);
5554
5555 REG_WR(bp, reg_offset, U64_LO(section));
5556 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 5557 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5558 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5559 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5560 }
a2fbb9ea 5561
523224a3
DK		 5562 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5563 sp_sb);
a2fbb9ea 5564
523224a3 5565 bnx2x_zero_sp_sb(bp);
a2fbb9ea 5566
619c5cb6 5567 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 5568 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5569 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5570 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5571 sp_sb_data.igu_seg_id = igu_seg_id;
5572 sp_sb_data.p_func.pf_id = func;
f2e0899f 5573 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 5574 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 5575
523224a3 5576 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 5577
523224a3 5578 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 5579}
5580
9f6c9258 5581void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 5582{
a2fbb9ea
ET		 5583 int i;
5584
ec6ba945 5585 for_each_eth_queue(bp, i)
523224a3 5586 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 5587 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 5588}
5589
a2fbb9ea
ET		 5590static void bnx2x_init_sp_ring(struct bnx2x *bp)
5591{
a2fbb9ea 5592 spin_lock_init(&bp->spq_lock);
6e30dd4e 5593 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 5594
a2fbb9ea 5595 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 5596 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5597 bp->spq_prod_bd = bp->spq;
5598 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 5599}
5600
523224a3 5601static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 5602{
5603 int i;
523224a3
DK		 5604 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5605 union event_ring_elem *elem =
5606 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 5607
523224a3
DK		 5608 elem->next_page.addr.hi =
5609 cpu_to_le32(U64_HI(bp->eq_mapping +
5610 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5611 elem->next_page.addr.lo =
5612 cpu_to_le32(U64_LO(bp->eq_mapping +
5613 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 5614 }
523224a3
DK		 5615 bp->eq_cons = 0;
5616 bp->eq_prod = NUM_EQ_DESC;
5617 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6e30dd4e
VZ		 5618 /* we want a warning message before it gets rought... */
5619 atomic_set(&bp->eq_spq_left,
5620 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 5621}
5622
619c5cb6
VZ		 5623
5624/* called with netif_addr_lock_bh() */
5625void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5626 unsigned long rx_mode_flags,
5627 unsigned long rx_accept_flags,
5628 unsigned long tx_accept_flags,
5629 unsigned long ramrod_flags)
ab532cf3 5630{
619c5cb6
VZ		 5631 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5632 int rc;
5633
5634 memset(&ramrod_param, 0, sizeof(ramrod_param));
5635
5636 /* Prepare ramrod parameters */
5637 ramrod_param.cid = 0;
5638 ramrod_param.cl_id = cl_id;
5639 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5640 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 5641
619c5cb6
VZ		 5642 ramrod_param.pstate = &bp->sp_state;
5643 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 5644
619c5cb6
VZ		 5645 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5646 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5647
5648 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5649
5650 ramrod_param.ramrod_flags = ramrod_flags;
5651 ramrod_param.rx_mode_flags = rx_mode_flags;
5652
5653 ramrod_param.rx_accept_flags = rx_accept_flags;
5654 ramrod_param.tx_accept_flags = tx_accept_flags;
5655
5656 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5657 if (rc < 0) {
5658 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5659 return;
5660 }
a2fbb9ea
ET		 5661}
5662
619c5cb6
VZ		 5663/* called with netif_addr_lock_bh() */
5664void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
471de716 5665{
619c5cb6
VZ		 5666 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5667 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
471de716 5668
619c5cb6
VZ		 5669 if (!NO_FCOE(bp))
5670
5671 /* Configure rx_mode of FCoE Queue */
5672 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
619c5cb6
VZ		 5673
5674 switch (bp->rx_mode) {
5675 case BNX2X_RX_MODE_NONE:
5676 /*
5677 * 'drop all' supersedes any accept flags that may have been
5678 * passed to the function.
5679 */
5680 break;
5681 case BNX2X_RX_MODE_NORMAL:
5682 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5683 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5684 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5685
5686 /* internal switching mode */
5687 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5688 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5689 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5690
5691 break;
5692 case BNX2X_RX_MODE_ALLMULTI:
5693 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5694 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5695 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5696
5697 /* internal switching mode */
5698 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5699 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5700 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5701
5702 break;
5703 case BNX2X_RX_MODE_PROMISC:
5704 /* According to deffinition of SI mode, iface in promisc mode
5705 * should receive matched and unmatched (in resolution of port)
5706 * unicast packets.
5707 */
5708 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5709 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5710 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5711 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5712
5713 /* internal switching mode */
5714 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5715 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5716
5717 if (IS_MF_SI(bp))
5718 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5719 else
5720 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5721
5722 break;
5723 default:
5724 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5725 return;
5726 }
de832a55 5727
619c5cb6
VZ		 5728 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5729 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5730 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
34f80b04
EG		 5731 }
5732
619c5cb6
VZ		 5733 __set_bit(RAMROD_RX, &ramrod_flags);
5734 __set_bit(RAMROD_TX, &ramrod_flags);
5735
5736 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5737 tx_accept_flags, ramrod_flags);
5738}
5739
5740static void bnx2x_init_internal_common(struct bnx2x *bp)
5741{
5742 int i;
5743
0793f83f
DK		 5744 if (IS_MF_SI(bp))
5745 /*
5746 * In switch independent mode, the TSTORM needs to accept
5747 * packets that failed classification, since approximate match
5748 * mac addresses aren't written to NIG LLH
5749 */
5750 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5751 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
619c5cb6
VZ		 5752 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5753 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5754 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
0793f83f 5755
523224a3
DK		 5756 /* Zero this manually as its initialization is
5757 currently missing in the initTool */
5758 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 5759 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 5760 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 5761 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5762 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5763 CHIP_INT_MODE_IS_BC(bp) ?
5764 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5765 }
523224a3 5766}
8a1c38d1 5767
471de716
EG		 5768static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5769{
5770 switch (load_code) {
5771 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 5772 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 5773 bnx2x_init_internal_common(bp);
5774 /* no break */
5775
5776 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 5777 /* nothing to do */
471de716
EG		 5778 /* no break */
5779
5780 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 5781 /* internal memory per function is
5782 initialized inside bnx2x_pf_init */
471de716
EG		 5783 break;
5784
5785 default:
5786 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5787 break;
5788 }
5789}
5790
619c5cb6 5791static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 5792{
55c11941 5793 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6 5794}
523224a3 5795
619c5cb6
VZ		 5796static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5797{
55c11941 5798 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6
VZ		 5799}
5800
1191cb83 5801static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
619c5cb6
VZ		 5802{
5803 if (CHIP_IS_E1x(fp->bp))
5804 return BP_L_ID(fp->bp) + fp->index;
5805 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5806 return bnx2x_fp_igu_sb_id(fp);
5807}
5808
6383c0b3 5809static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 5810{
5811 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 5812 u8 cos;
619c5cb6 5813 unsigned long q_type = 0;
6383c0b3 5814 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 5815 fp->rx_queue = fp_idx;
b3b83c3f 5816 fp->cid = fp_idx;
619c5cb6
VZ		 5817 fp->cl_id = bnx2x_fp_cl_id(fp);
5818 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5819 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 5820 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 5821 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5822
523224a3 5823 /* init shortcut */
619c5cb6 5824 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
7a752993 5825
523224a3
DK		 5826 /* Setup SB indicies */
5827 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 5828
619c5cb6
VZ		 5829 /* Configure Queue State object */
5830 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5831 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 5832
5833 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5834
5835 /* init tx data */
5836 for_each_cos_in_tx_queue(fp, cos) {
65565884
MS		 5837 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5838 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5839 FP_COS_TO_TXQ(fp, cos, bp),
5840 BNX2X_TX_SB_INDEX_BASE + cos, fp);
5841 cids[cos] = fp->txdata_ptr[cos]->cid;
6383c0b3
AE		 5842 }
5843
ad5afc89
AE		 5844 /* nothing more for vf to do here */
5845 if (IS_VF(bp))
5846 return;
5847
5848 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5849 fp->fw_sb_id, fp->igu_sb_id);
5850 bnx2x_update_fpsb_idx(fp);
15192a8c
BW		 5851 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5852 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6383c0b3 5853 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 5854
5855 /**
5856 * Configure classification DBs: Always enable Tx switching
5857 */
5858 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5859
ad5afc89
AE		 5860 DP(NETIF_MSG_IFUP,
5861 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5862 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5863 fp->igu_sb_id);
523224a3
DK		 5864}
5865
1191cb83
ED		 5866static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5867{
5868 int i;
5869
5870 for (i = 1; i <= NUM_TX_RINGS; i++) {
5871 struct eth_tx_next_bd *tx_next_bd =
5872 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5873
5874 tx_next_bd->addr_hi =
5875 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5876 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5877 tx_next_bd->addr_lo =
5878 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5879 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5880 }
5881
5882 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5883 txdata->tx_db.data.zero_fill1 = 0;
5884 txdata->tx_db.data.prod = 0;
5885
5886 txdata->tx_pkt_prod = 0;
5887 txdata->tx_pkt_cons = 0;
5888 txdata->tx_bd_prod = 0;
5889 txdata->tx_bd_cons = 0;
5890 txdata->tx_pkt = 0;
5891}
5892
55c11941
MS		 5893static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
5894{
5895 int i;
5896
5897 for_each_tx_queue_cnic(bp, i)
5898 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
5899}
1191cb83
ED		 5900static void bnx2x_init_tx_rings(struct bnx2x *bp)
5901{
5902 int i;
5903 u8 cos;
5904
55c11941 5905 for_each_eth_queue(bp, i)
1191cb83 5906 for_each_cos_in_tx_queue(&bp->fp[i], cos)
65565884 5907 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
1191cb83
ED		 5908}
5909
55c11941 5910void bnx2x_nic_init_cnic(struct bnx2x *bp)
a2fbb9ea 5911{
ec6ba945
VZ		 5912 if (!NO_FCOE(bp))
5913 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 5914
5915 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5916 BNX2X_VF_ID_INVALID, false,
619c5cb6 5917 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 5918
55c11941
MS		 5919 /* ensure status block indices were read */
5920 rmb();
5921 bnx2x_init_rx_rings_cnic(bp);
5922 bnx2x_init_tx_rings_cnic(bp);
5923
5924 /* flush all */
5925 mb();
5926 mmiowb();
5927}
a2fbb9ea 5928
55c11941
MS		 5929void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5930{
5931 int i;
5932
5933 for_each_eth_queue(bp, i)
5934 bnx2x_init_eth_fp(bp, i);
ad5afc89
AE		 5935
5936 /* ensure status block indices were read */
5937 rmb();
5938 bnx2x_init_rx_rings(bp);
5939 bnx2x_init_tx_rings(bp);
5940
5941 if (IS_VF(bp))
5942 return;
5943
020c7e3f
YR		 5944 /* Initialize MOD_ABS interrupts */
5945 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5946 bp->common.shmem_base, bp->common.shmem2_base,
5947 BP_PORT(bp));
16119785 5948
523224a3 5949 bnx2x_init_def_sb(bp);
5c862848 5950 bnx2x_update_dsb_idx(bp);
a2fbb9ea 5951 bnx2x_init_sp_ring(bp);
523224a3 5952 bnx2x_init_eq_ring(bp);
471de716 5953 bnx2x_init_internal(bp, load_code);
523224a3 5954 bnx2x_pf_init(bp);
0ef00459
EG		 5955 bnx2x_stats_init(bp);
5956
0ef00459
EG		 5957 /* flush all before enabling interrupts */
5958 mb();
5959 mmiowb();
5960
615f8fd9 5961 bnx2x_int_enable(bp);
eb8da205
EG		 5962
5963 /* Check for SPIO5 */
5964 bnx2x_attn_int_deasserted0(bp,
5965 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5966 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 5967}
5968
5969/* end of nic init */
5970
5971/*
5972 * gzip service functions
5973 */
5974
5975static int bnx2x_gunzip_init(struct bnx2x *bp)
5976{
1a983142
FT		 5977 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5978 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 5979 if (bp->gunzip_buf == NULL)
5980 goto gunzip_nomem1;
5981
5982 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5983 if (bp->strm == NULL)
5984 goto gunzip_nomem2;
5985
7ab24bfd 5986 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 5987 if (bp->strm->workspace == NULL)
5988 goto gunzip_nomem3;
5989
5990 return 0;
5991
5992gunzip_nomem3:
5993 kfree(bp->strm);
5994 bp->strm = NULL;
5995
5996gunzip_nomem2:
1a983142
FT		 5997 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5998 bp->gunzip_mapping);
a2fbb9ea
ET		 5999 bp->gunzip_buf = NULL;
6000
6001gunzip_nomem1:
51c1a580 6002 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
a2fbb9ea
ET		 6003 return -ENOMEM;
6004}
6005
6006static void bnx2x_gunzip_end(struct bnx2x *bp)
6007{
b3b83c3f 6008 if (bp->strm) {
7ab24bfd 6009 vfree(bp->strm->workspace);
b3b83c3f
DK		 6010 kfree(bp->strm);
6011 bp->strm = NULL;
6012 }
a2fbb9ea
ET		 6013
6014 if (bp->gunzip_buf) {
1a983142
FT		 6015 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6016 bp->gunzip_mapping);
a2fbb9ea
ET		 6017 bp->gunzip_buf = NULL;
6018 }
6019}
6020
94a78b79 6021static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 6022{
6023 int n, rc;
6024
6025 /* check gzip header */
94a78b79
VZ		 6026 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6027 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 6028 return -EINVAL;
94a78b79 6029 }
a2fbb9ea
ET		 6030
6031 n = 10;
6032
34f80b04 6033#define FNAME 0x8
a2fbb9ea
ET		 6034
6035 if (zbuf[3] & FNAME)
6036 while ((zbuf[n++] != 0) && (n < len));
6037
94a78b79 6038 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 6039 bp->strm->avail_in = len - n;
6040 bp->strm->next_out = bp->gunzip_buf;
6041 bp->strm->avail_out = FW_BUF_SIZE;
6042
6043 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6044 if (rc != Z_OK)
6045 return rc;
6046
6047 rc = zlib_inflate(bp->strm, Z_FINISH);
6048 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 6049 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6050 bp->strm->msg);
a2fbb9ea
ET		 6051
6052 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6053 if (bp->gunzip_outlen & 0x3)
51c1a580
MS		 6054 netdev_err(bp->dev,
6055 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
cdaa7cb8 6056 bp->gunzip_outlen);
a2fbb9ea
ET		 6057 bp->gunzip_outlen >>= 2;
6058
6059 zlib_inflateEnd(bp->strm);
6060
6061 if (rc == Z_STREAM_END)
6062 return 0;
6063
6064 return rc;
6065}
6066
6067/* nic load/unload */
6068
6069/*
34f80b04 6070 * General service functions
a2fbb9ea
ET		 6071 */
6072
6073/* send a NIG loopback debug packet */
6074static void bnx2x_lb_pckt(struct bnx2x *bp)
6075{
a2fbb9ea 6076 u32 wb_write[3];
a2fbb9ea
ET		 6077
6078 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 6079 wb_write[0] = 0x55555555;
6080 wb_write[1] = 0x55555555;
34f80b04 6081 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 6082 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6083
6084 /* NON-IP protocol */
a2fbb9ea
ET		 6085 wb_write[0] = 0x09000000;
6086 wb_write[1] = 0x55555555;
34f80b04 6087 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 6088 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6089}
6090
6091/* some of the internal memories
6092 * are not directly readable from the driver
6093 * to test them we send debug packets
6094 */
6095static int bnx2x_int_mem_test(struct bnx2x *bp)
6096{
6097 int factor;
6098 int count, i;
6099 u32 val = 0;
6100
ad8d3948 6101 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 6102 factor = 120;
ad8d3948
EG		 6103 else if (CHIP_REV_IS_EMUL(bp))
6104 factor = 200;
6105 else
a2fbb9ea 6106 factor = 1;
a2fbb9ea 6107
a2fbb9ea
ET		 6108 /* Disable inputs of parser neighbor blocks */
6109 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6110 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6111 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6112 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6113
6114 /* Write 0 to parser credits for CFC search request */
6115 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6116
6117 /* send Ethernet packet */
6118 bnx2x_lb_pckt(bp);
6119
6120 /* TODO do i reset NIG statistic? */
6121 /* Wait until NIG register shows 1 packet of size 0x10 */
6122 count = 1000 * factor;
6123 while (count) {
34f80b04 6124
a2fbb9ea
ET		 6125 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6126 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6127 if (val == 0x10)
6128 break;
6129
6130 msleep(10);
6131 count--;
6132 }
6133 if (val != 0x10) {
6134 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6135 return -1;
6136 }
6137
6138 /* Wait until PRS register shows 1 packet */
6139 count = 1000 * factor;
6140 while (count) {
6141 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 6142 if (val == 1)
6143 break;
6144
6145 msleep(10);
6146 count--;
6147 }
6148 if (val != 0x1) {
6149 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6150 return -2;
6151 }
6152
6153 /* Reset and init BRB, PRS */
34f80b04 6154 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 6155 msleep(50);
34f80b04 6156 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 6157 msleep(50);
619c5cb6
VZ		 6158 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6159 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 6160
6161 DP(NETIF_MSG_HW, "part2\n");
6162
6163 /* Disable inputs of parser neighbor blocks */
6164 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6165 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6166 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6167 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6168
6169 /* Write 0 to parser credits for CFC search request */
6170 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6171
6172 /* send 10 Ethernet packets */
6173 for (i = 0; i < 10; i++)
6174 bnx2x_lb_pckt(bp);
6175
6176 /* Wait until NIG register shows 10 + 1
6177 packets of size 11*0x10 = 0xb0 */
6178 count = 1000 * factor;
6179 while (count) {
34f80b04 6180
a2fbb9ea
ET		 6181 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6182 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6183 if (val == 0xb0)
6184 break;
6185
6186 msleep(10);
6187 count--;
6188 }
6189 if (val != 0xb0) {
6190 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6191 return -3;
6192 }
6193
6194 /* Wait until PRS register shows 2 packets */
6195 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6196 if (val != 2)
6197 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6198
6199 /* Write 1 to parser credits for CFC search request */
6200 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6201
6202 /* Wait until PRS register shows 3 packets */
6203 msleep(10 * factor);
6204 /* Wait until NIG register shows 1 packet of size 0x10 */
6205 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6206 if (val != 3)
6207 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6208
6209 /* clear NIG EOP FIFO */
6210 for (i = 0; i < 11; i++)
6211 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6212 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6213 if (val != 1) {
6214 BNX2X_ERR("clear of NIG failed\n");
6215 return -4;
6216 }
6217
6218 /* Reset and init BRB, PRS, NIG */
6219 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6220 msleep(50);
6221 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6222 msleep(50);
619c5cb6
VZ		 6223 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6224 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
55c11941
MS		 6225 if (!CNIC_SUPPORT(bp))
6226 /* set NIC mode */
6227 REG_WR(bp, PRS_REG_NIC_MODE, 1);
a2fbb9ea
ET		 6228
6229 /* Enable inputs of parser neighbor blocks */
6230 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6231 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6232 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 6233 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 6234
6235 DP(NETIF_MSG_HW, "done\n");
6236
6237 return 0; /* OK */
6238}
6239
4a33bc03 6240static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea 6241{
b343d002
YM		 6242 u32 val;
6243
a2fbb9ea 6244 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 6245 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6246 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6247 else
6248 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 6249 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6250 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 6251 /*
6252 * mask read length error interrupts in brb for parser
6253 * (parsing unit and 'checksum and crc' unit)
6254 * these errors are legal (PU reads fixed length and CAC can cause
6255 * read length error on truncated packets)
6256 */
6257 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 6258 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6259 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6260 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6261 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6262 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 6263/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6264/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6265 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6266 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6267 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 6268/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6269/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6270 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6271 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6272 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6273 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 6274/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6275/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 6276
b343d002
YM		 6277 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6278 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6279 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6280 if (!CHIP_IS_E1x(bp))
6281 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6282 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6283 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6284
a2fbb9ea
ET		 6285 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6286 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6287 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 6288/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 6289
6290 if (!CHIP_IS_E1x(bp))
6291 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6292 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6293
a2fbb9ea
ET		 6294 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6295 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 6296/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 6297 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 6298}
6299
81f75bbf
EG		 6300static void bnx2x_reset_common(struct bnx2x *bp)
6301{
619c5cb6
VZ		 6302 u32 val = 0x1400;
6303
81f75bbf
EG		 6304 /* reset_common */
6305 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6306 0xd3ffff7f);
619c5cb6
VZ		 6307
6308 if (CHIP_IS_E3(bp)) {
6309 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6310 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6311 }
6312
6313 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6314}
6315
6316static void bnx2x_setup_dmae(struct bnx2x *bp)
6317{
6318 bp->dmae_ready = 0;
6319 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 6320}
6321
573f2035
EG		 6322static void bnx2x_init_pxp(struct bnx2x *bp)
6323{
6324 u16 devctl;
6325 int r_order, w_order;
6326
2a80eebc 6327 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 6328 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6329 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6330 if (bp->mrrs == -1)
6331 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6332 else {
6333 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6334 r_order = bp->mrrs;
6335 }
6336
6337 bnx2x_init_pxp_arb(bp, r_order, w_order);
6338}
fd4ef40d
EG		 6339
6340static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6341{
2145a920 6342 int is_required;
fd4ef40d 6343 u32 val;
2145a920 6344 int port;
fd4ef40d 6345
2145a920
VZ		 6346 if (BP_NOMCP(bp))
6347 return;
6348
6349 is_required = 0;
fd4ef40d
EG		 6350 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6351 SHARED_HW_CFG_FAN_FAILURE_MASK;
6352
6353 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6354 is_required = 1;
6355
6356 /*
6357 * The fan failure mechanism is usually related to the PHY type since
6358 * the power consumption of the board is affected by the PHY. Currently,
6359 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6360 */
6361 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6362 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 6363 is_required |=
d90d96ba
YR		 6364 bnx2x_fan_failure_det_req(
6365 bp,
6366 bp->common.shmem_base,
a22f0788 6367 bp->common.shmem2_base,
d90d96ba 6368 port);
fd4ef40d
EG		 6369 }
6370
6371 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6372
6373 if (is_required == 0)
6374 return;
6375
6376 /* Fan failure is indicated by SPIO 5 */
d6d99a3f 6377 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
fd4ef40d
EG		 6378
6379 /* set to active low mode */
6380 val = REG_RD(bp, MISC_REG_SPIO_INT);
d6d99a3f 6381 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 6382 REG_WR(bp, MISC_REG_SPIO_INT, val);
6383
6384 /* enable interrupt to signal the IGU */
6385 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 6386 val |= MISC_SPIO_SPIO5;
fd4ef40d
EG		 6387 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6388}
6389
c9ee9206 6390void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 6391{
6392 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6393 val &= ~IGU_PF_CONF_FUNC_EN;
6394
6395 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6396 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6397 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6398}
6399
1191cb83 6400static void bnx2x__common_init_phy(struct bnx2x *bp)
619c5cb6
VZ		 6401{
6402 u32 shmem_base[2], shmem2_base[2];
b884d95b
YR		 6403 /* Avoid common init in case MFW supports LFA */
6404 if (SHMEM2_RD(bp, size) >
6405 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6406 return;
619c5cb6
VZ		 6407 shmem_base[0] = bp->common.shmem_base;
6408 shmem2_base[0] = bp->common.shmem2_base;
6409 if (!CHIP_IS_E1x(bp)) {
6410 shmem_base[1] =
6411 SHMEM2_RD(bp, other_shmem_base_addr);
6412 shmem2_base[1] =
6413 SHMEM2_RD(bp, other_shmem2_base_addr);
6414 }
6415 bnx2x_acquire_phy_lock(bp);
6416 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6417 bp->common.chip_id);
6418 bnx2x_release_phy_lock(bp);
6419}
6420
6421/**
6422 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6423 *
6424 * @bp: driver handle
6425 */
6426static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 6427{
619c5cb6 6428 u32 val;
a2fbb9ea 6429
51c1a580 6430 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 6431
2031bd3a
DK		 6432 /*
6433 * take the UNDI lock to protect undi_unload flow from accessing
6434 * registers while we're resetting the chip
6435 */
7a06a122 6436 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6437
81f75bbf 6438 bnx2x_reset_common(bp);
34f80b04 6439 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 6440
619c5cb6
VZ		 6441 val = 0xfffc;
6442 if (CHIP_IS_E3(bp)) {
6443 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6444 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6445 }
6446 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6447
7a06a122 6448 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6449
619c5cb6 6450 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 6451
619c5cb6
VZ		 6452 if (!CHIP_IS_E1x(bp)) {
6453 u8 abs_func_id;
f2e0899f
DK		 6454
6455 /**
6456 * 4-port mode or 2-port mode we need to turn of master-enable
6457 * for everyone, after that, turn it back on for self.
6458 * so, we disregard multi-function or not, and always disable
6459 * for all functions on the given path, this means 0,2,4,6 for
6460 * path 0 and 1,3,5,7 for path 1
6461 */
619c5cb6
VZ		 6462 for (abs_func_id = BP_PATH(bp);
6463 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6464 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 6465 REG_WR(bp,
6466 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6467 1);
6468 continue;
6469 }
6470
619c5cb6 6471 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 6472 /* clear pf enable */
6473 bnx2x_pf_disable(bp);
6474 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6475 }
6476 }
a2fbb9ea 6477
619c5cb6 6478 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 6479 if (CHIP_IS_E1(bp)) {
6480 /* enable HW interrupt from PXP on USDM overflow
6481 bit 16 on INT_MASK_0 */
6482 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6483 }
a2fbb9ea 6484
619c5cb6 6485 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 6486 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 6487
6488#ifdef __BIG_ENDIAN
34f80b04
EG		 6489 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6490 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6491 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6492 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6493 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 6494 /* make sure this value is 0 */
6495 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 6496
6497/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6498 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6499 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6500 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6501 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 6502#endif
6503
523224a3
DK		 6504 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6505
34f80b04
EG		 6506 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6507 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 6508
34f80b04
EG		 6509 /* let the HW do it's magic ... */
6510 msleep(100);
6511 /* finish PXP init */
6512 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6513 if (val != 1) {
6514 BNX2X_ERR("PXP2 CFG failed\n");
6515 return -EBUSY;
6516 }
6517 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6518 if (val != 1) {
6519 BNX2X_ERR("PXP2 RD_INIT failed\n");
6520 return -EBUSY;
6521 }
a2fbb9ea 6522
f2e0899f
DK		 6523 /* Timers bug workaround E2 only. We need to set the entire ILT to
6524 * have entries with value "0" and valid bit on.
6525 * This needs to be done by the first PF that is loaded in a path
6526 * (i.e. common phase)
6527 */
619c5cb6
VZ		 6528 if (!CHIP_IS_E1x(bp)) {
6529/* In E2 there is a bug in the timers block that can cause function 6 / 7
6530 * (i.e. vnic3) to start even if it is marked as "scan-off".
6531 * This occurs when a different function (func2,3) is being marked
6532 * as "scan-off". Real-life scenario for example: if a driver is being
6533 * load-unloaded while func6,7 are down. This will cause the timer to access
6534 * the ilt, translate to a logical address and send a request to read/write.
6535 * Since the ilt for the function that is down is not valid, this will cause
6536 * a translation error which is unrecoverable.
6537 * The Workaround is intended to make sure that when this happens nothing fatal
6538 * will occur. The workaround:
6539 * 1. First PF driver which loads on a path will:
6540 * a. After taking the chip out of reset, by using pretend,
6541 * it will write "0" to the following registers of
6542 * the other vnics.
6543 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6544 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6545 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6546 * And for itself it will write '1' to
6547 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6548 * dmae-operations (writing to pram for example.)
6549 * note: can be done for only function 6,7 but cleaner this
6550 * way.
6551 * b. Write zero+valid to the entire ILT.
6552 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6553 * VNIC3 (of that port). The range allocated will be the
6554 * entire ILT. This is needed to prevent ILT range error.
6555 * 2. Any PF driver load flow:
6556 * a. ILT update with the physical addresses of the allocated
6557 * logical pages.
6558 * b. Wait 20msec. - note that this timeout is needed to make
6559 * sure there are no requests in one of the PXP internal
6560 * queues with "old" ILT addresses.
6561 * c. PF enable in the PGLC.
6562 * d. Clear the was_error of the PF in the PGLC. (could have
6563 * occured while driver was down)
6564 * e. PF enable in the CFC (WEAK + STRONG)
6565 * f. Timers scan enable
6566 * 3. PF driver unload flow:
6567 * a. Clear the Timers scan_en.
6568 * b. Polling for scan_on=0 for that PF.
6569 * c. Clear the PF enable bit in the PXP.
6570 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6571 * e. Write zero+valid to all ILT entries (The valid bit must
6572 * stay set)
6573 * f. If this is VNIC 3 of a port then also init
6574 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6575 * to the last enrty in the ILT.
6576 *
6577 * Notes:
6578 * Currently the PF error in the PGLC is non recoverable.
6579 * In the future the there will be a recovery routine for this error.
6580 * Currently attention is masked.
6581 * Having an MCP lock on the load/unload process does not guarantee that
6582 * there is no Timer disable during Func6/7 enable. This is because the
6583 * Timers scan is currently being cleared by the MCP on FLR.
6584 * Step 2.d can be done only for PF6/7 and the driver can also check if
6585 * there is error before clearing it. But the flow above is simpler and
6586 * more general.
6587 * All ILT entries are written by zero+valid and not just PF6/7
6588 * ILT entries since in the future the ILT entries allocation for
6589 * PF-s might be dynamic.
6590 */
f2e0899f
DK		 6591 struct ilt_client_info ilt_cli;
6592 struct bnx2x_ilt ilt;
6593 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6594 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6595
b595076a 6596 /* initialize dummy TM client */
f2e0899f
DK		 6597 ilt_cli.start = 0;
6598 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6599 ilt_cli.client_num = ILT_CLIENT_TM;
6600
6601 /* Step 1: set zeroes to all ilt page entries with valid bit on
6602 * Step 2: set the timers first/last ilt entry to point
6603 * to the entire range to prevent ILT range error for 3rd/4th
619c5cb6 6604 * vnic (this code assumes existance of the vnic)
f2e0899f
DK		 6605 *
6606 * both steps performed by call to bnx2x_ilt_client_init_op()
6607 * with dummy TM client
6608 *
6609 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6610 * and his brother are split registers
6611 */
6612 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6613 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6614 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6615
6616 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6617 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6618 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6619 }
6620
6621
34f80b04
EG		 6622 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6623 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 6624
619c5cb6 6625 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6626 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6627 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 6628 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 6629
619c5cb6 6630 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 6631
6632 /* let the HW do it's magic ... */
6633 do {
6634 msleep(200);
6635 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6636 } while (factor-- && (val != 1));
6637
6638 if (val != 1) {
6639 BNX2X_ERR("ATC_INIT failed\n");
6640 return -EBUSY;
6641 }
6642 }
6643
619c5cb6 6644 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 6645
b56e9670
AE		 6646 bnx2x_iov_init_dmae(bp);
6647
34f80b04
EG		 6648 /* clean the DMAE memory */
6649 bp->dmae_ready = 1;
619c5cb6
VZ		 6650 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6651
6652 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6653
6654 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6655
6656 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 6657
619c5cb6 6658 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 6659
34f80b04
EG		 6660 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6661 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6662 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6663 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6664
619c5cb6 6665 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 6666
f85582f8 6667
523224a3
DK		 6668 /* QM queues pointers table */
6669 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6670
34f80b04
EG		 6671 /* soft reset pulse */
6672 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6673 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 6674
55c11941
MS		 6675 if (CNIC_SUPPORT(bp))
6676 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 6677
619c5cb6 6678 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
523224a3 6679 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
619c5cb6 6680 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 6681 /* enable hw interrupt from doorbell Q */
6682 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 6683
619c5cb6 6684 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 6685
619c5cb6 6686 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 6687 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 6688
f2e0899f 6689 if (!CHIP_IS_E1(bp))
619c5cb6 6690 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 6691
a3348722
BW		 6692 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6693 if (IS_MF_AFEX(bp)) {
6694 /* configure that VNTag and VLAN headers must be
6695 * received in afex mode
6696 */
6697 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6698 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6699 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6700 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6701 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6702 } else {
6703 /* Bit-map indicating which L2 hdrs may appear
6704 * after the basic Ethernet header
6705 */
6706 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6707 bp->path_has_ovlan ? 7 : 6);
6708 }
6709 }
a2fbb9ea 6710
619c5cb6
VZ		 6711 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6712 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6713 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6714 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 6715
619c5cb6
VZ		 6716 if (!CHIP_IS_E1x(bp)) {
6717 /* reset VFC memories */
6718 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6719 VFC_MEMORIES_RST_REG_CAM_RST |
6720 VFC_MEMORIES_RST_REG_RAM_RST);
6721 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6722 VFC_MEMORIES_RST_REG_CAM_RST |
6723 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 6724
619c5cb6
VZ		 6725 msleep(20);
6726 }
a2fbb9ea 6727
619c5cb6
VZ		 6728 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6729 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6730 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6731 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 6732
34f80b04
EG		 6733 /* sync semi rtc */
6734 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6735 0x80000000);
6736 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6737 0x80000000);
a2fbb9ea 6738
619c5cb6
VZ		 6739 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6740 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6741 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 6742
a3348722
BW		 6743 if (!CHIP_IS_E1x(bp)) {
6744 if (IS_MF_AFEX(bp)) {
6745 /* configure that VNTag and VLAN headers must be
6746 * sent in afex mode
6747 */
6748 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6749 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6750 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6751 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6752 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6753 } else {
6754 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6755 bp->path_has_ovlan ? 7 : 6);
6756 }
6757 }
f2e0899f 6758
34f80b04 6759 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 6760
619c5cb6
VZ		 6761 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6762
55c11941
MS		 6763 if (CNIC_SUPPORT(bp)) {
6764 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6765 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6766 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6767 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6768 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6769 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6770 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6771 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6772 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6773 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6774 }
34f80b04 6775 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 6776
34f80b04
EG		 6777 if (sizeof(union cdu_context) != 1024)
6778 /* we currently assume that a context is 1024 bytes */
51c1a580
MS		 6779 dev_alert(&bp->pdev->dev,
6780 "please adjust the size of cdu_context(%ld)\n",
6781 (long)sizeof(union cdu_context));
a2fbb9ea 6782
619c5cb6 6783 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 6784 val = (4 << 24) + (0 << 12) + 1024;
6785 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 6786
619c5cb6 6787 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 6788 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 6789 /* enable context validation interrupt from CFC */
6790 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6791
6792 /* set the thresholds to prevent CFC/CDU race */
6793 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 6794
619c5cb6 6795 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 6796
619c5cb6 6797 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 6798 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6799
619c5cb6
VZ		 6800 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6801 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 6802
34f80b04
EG		 6803 /* Reset PCIE errors for debug */
6804 REG_WR(bp, 0x2814, 0xffffffff);
6805 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 6806
619c5cb6 6807 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6808 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6809 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6810 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6811 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6812 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6813 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6814 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6815 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6816 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6817 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6818 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6819 }
6820
619c5cb6 6821 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 6822 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 6823 /* in E3 this done in per-port section */
6824 if (!CHIP_IS_E3(bp))
6825 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 6826 }
619c5cb6
VZ		 6827 if (CHIP_IS_E1H(bp))
6828 /* not applicable for E2 (and above ...) */
6829 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 6830
6831 if (CHIP_REV_IS_SLOW(bp))
6832 msleep(200);
6833
6834 /* finish CFC init */
6835 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6836 if (val != 1) {
6837 BNX2X_ERR("CFC LL_INIT failed\n");
6838 return -EBUSY;
6839 }
6840 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6841 if (val != 1) {
6842 BNX2X_ERR("CFC AC_INIT failed\n");
6843 return -EBUSY;
6844 }
6845 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6846 if (val != 1) {
6847 BNX2X_ERR("CFC CAM_INIT failed\n");
6848 return -EBUSY;
6849 }
6850 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 6851
f2e0899f
DK		 6852 if (CHIP_IS_E1(bp)) {
6853 /* read NIG statistic
6854 to see if this is our first up since powerup */
6855 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6856 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 6857
f2e0899f
DK		 6858 /* do internal memory self test */
6859 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6860 BNX2X_ERR("internal mem self test failed\n");
6861 return -EBUSY;
6862 }
34f80b04
EG		 6863 }
6864
fd4ef40d
EG		 6865 bnx2x_setup_fan_failure_detection(bp);
6866
34f80b04
EG		 6867 /* clear PXP2 attentions */
6868 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 6869
4a33bc03 6870 bnx2x_enable_blocks_attention(bp);
c9ee9206 6871 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 6872
6bbca910 6873 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 6874 if (CHIP_IS_E1x(bp))
6875 bnx2x__common_init_phy(bp);
6bbca910
YR		 6876 } else
6877 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6878
34f80b04
EG		 6879 return 0;
6880}
a2fbb9ea 6881
619c5cb6
VZ		 6882/**
6883 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6884 *
6885 * @bp: driver handle
6886 */
6887static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6888{
6889 int rc = bnx2x_init_hw_common(bp);
6890
6891 if (rc)
6892 return rc;
6893
6894 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6895 if (!BP_NOMCP(bp))
6896 bnx2x__common_init_phy(bp);
6897
6898 return 0;
6899}
6900
523224a3 6901static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 6902{
6903 int port = BP_PORT(bp);
619c5cb6 6904 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 6905 u32 low, high;
34f80b04 6906 u32 val;
a2fbb9ea 6907
619c5cb6 6908
51c1a580 6909 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
34f80b04
EG		 6910
6911 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 6912
619c5cb6
VZ		 6913 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6914 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6915 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 6916
f2e0899f
DK		 6917 /* Timers bug workaround: disables the pf_master bit in pglue at
6918 * common phase, we need to enable it here before any dmae access are
6919 * attempted. Therefore we manually added the enable-master to the
6920 * port phase (it also happens in the function phase)
6921 */
619c5cb6 6922 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6923 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6924
619c5cb6
VZ		 6925 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6926 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6927 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6928 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6929
6930 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6931 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6932 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6933 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 6934
523224a3
DK		 6935 /* QM cid (connection) count */
6936 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 6937
55c11941
MS		 6938 if (CNIC_SUPPORT(bp)) {
6939 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6940 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6941 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6942 }
cdaa7cb8 6943
619c5cb6 6944 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f 6945
2b674047
DK		 6946 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6947
f2e0899f 6948 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 6949
6950 if (IS_MF(bp))
6951 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6952 else if (bp->dev->mtu > 4096) {
6953 if (bp->flags & ONE_PORT_FLAG)
6954 low = 160;
6955 else {
6956 val = bp->dev->mtu;
6957 /* (24*1024 + val*4)/256 */
6958 low = 96 + (val/64) +
6959 ((val % 64) ? 1 : 0);
6960 }
6961 } else
6962 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6963 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 6964 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6965 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 6966 }
1c06328c 6967
619c5cb6
VZ		 6968 if (CHIP_MODE_IS_4_PORT(bp))
6969 REG_WR(bp, (BP_PORT(bp) ?
6970 BRB1_REG_MAC_GUARANTIED_1 :
6971 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 6972
ca00392c 6973
619c5cb6 6974 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
a3348722
BW		 6975 if (CHIP_IS_E3B0(bp)) {
6976 if (IS_MF_AFEX(bp)) {
6977 /* configure headers for AFEX mode */
6978 REG_WR(bp, BP_PORT(bp) ?
6979 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6980 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
6981 REG_WR(bp, BP_PORT(bp) ?
6982 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
6983 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
6984 REG_WR(bp, BP_PORT(bp) ?
6985 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
6986 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
6987 } else {
6988 /* Ovlan exists only if we are in multi-function +
6989 * switch-dependent mode, in switch-independent there
6990 * is no ovlan headers
6991 */
6992 REG_WR(bp, BP_PORT(bp) ?
6993 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6994 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6995 (bp->path_has_ovlan ? 7 : 6));
6996 }
6997 }
356e2385 6998
619c5cb6
VZ		 6999 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7000 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7001 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7002 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 7003
619c5cb6
VZ		 7004 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7005 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7006 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7007 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 7008
619c5cb6
VZ		 7009 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7010 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 7011
619c5cb6
VZ		 7012 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7013
7014 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7015 /* configure PBF to work without PAUSE mtu 9000 */
7016 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 7017
f2e0899f
DK		 7018 /* update threshold */
7019 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7020 /* update init credit */
7021 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 7022
f2e0899f
DK		 7023 /* probe changes */
7024 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7025 udelay(50);
7026 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7027 }
a2fbb9ea 7028
55c11941
MS		 7029 if (CNIC_SUPPORT(bp))
7030 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7031
619c5cb6
VZ		 7032 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7033 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 7034
7035 if (CHIP_IS_E1(bp)) {
7036 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7037 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7038 }
619c5cb6 7039 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 7040
619c5cb6 7041 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7042
619c5cb6 7043 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04
EG		 7044 /* init aeu_mask_attn_func_0/1:
7045 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
7046 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
7047 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 7048 val = IS_MF(bp) ? 0xF7 : 0x7;
7049 /* Enable DCBX attention for all but E1 */
7050 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7051 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 7052
619c5cb6
VZ		 7053 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7054
7055 if (!CHIP_IS_E1x(bp)) {
7056 /* Bit-map indicating which L2 hdrs may appear after the
7057 * basic Ethernet header
7058 */
a3348722
BW		 7059 if (IS_MF_AFEX(bp))
7060 REG_WR(bp, BP_PORT(bp) ?
7061 NIG_REG_P1_HDRS_AFTER_BASIC :
7062 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7063 else
7064 REG_WR(bp, BP_PORT(bp) ?
7065 NIG_REG_P1_HDRS_AFTER_BASIC :
7066 NIG_REG_P0_HDRS_AFTER_BASIC,
7067 IS_MF_SD(bp) ? 7 : 6);
619c5cb6
VZ		 7068
7069 if (CHIP_IS_E3(bp))
7070 REG_WR(bp, BP_PORT(bp) ?
7071 NIG_REG_LLH1_MF_MODE :
7072 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7073 }
7074 if (!CHIP_IS_E3(bp))
7075 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 7076
f2e0899f 7077 if (!CHIP_IS_E1(bp)) {
fb3bff17 7078 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 7079 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 7080 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 7081
619c5cb6 7082 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7083 val = 0;
7084 switch (bp->mf_mode) {
7085 case MULTI_FUNCTION_SD:
7086 val = 1;
7087 break;
7088 case MULTI_FUNCTION_SI:
a3348722 7089 case MULTI_FUNCTION_AFEX:
f2e0899f
DK		 7090 val = 2;
7091 break;
7092 }
7093
7094 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7095 NIG_REG_LLH0_CLS_TYPE), val);
7096 }
1c06328c
EG		 7097 {
7098 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7099 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7100 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7101 }
34f80b04
EG		 7102 }
7103
619c5cb6
VZ		 7104
7105 /* If SPIO5 is set to generate interrupts, enable it for this port */
7106 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 7107 if (val & MISC_SPIO_SPIO5) {
4d295db0
EG		 7108 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7109 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7110 val = REG_RD(bp, reg_addr);
f1410647 7111 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 7112 REG_WR(bp, reg_addr, val);
f1410647 7113 }
a2fbb9ea 7114
34f80b04
EG		 7115 return 0;
7116}
7117
34f80b04
EG		 7118static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7119{
7120 int reg;
32d68de1 7121 u32 wb_write[2];
34f80b04 7122
f2e0899f 7123 if (CHIP_IS_E1(bp))
34f80b04 7124 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 7125 else
7126 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04 7127
32d68de1
YM		 7128 wb_write[0] = ONCHIP_ADDR1(addr);
7129 wb_write[1] = ONCHIP_ADDR2(addr);
7130 REG_WR_DMAE(bp, reg, wb_write, 2);
34f80b04
EG		 7131}
7132
b56e9670 7133void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
1191cb83
ED		 7134{
7135 u32 data, ctl, cnt = 100;
7136 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7137 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7138 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7139 u32 sb_bit = 1 << (idu_sb_id%32);
b56e9670 7140 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
1191cb83
ED		 7141 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7142
7143 /* Not supported in BC mode */
7144 if (CHIP_INT_MODE_IS_BC(bp))
7145 return;
7146
7147 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7148 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7149 IGU_REGULAR_CLEANUP_SET |
7150 IGU_REGULAR_BCLEANUP;
7151
7152 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7153 func_encode << IGU_CTRL_REG_FID_SHIFT |
7154 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7155
7156 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7157 data, igu_addr_data);
7158 REG_WR(bp, igu_addr_data, data);
7159 mmiowb();
7160 barrier();
7161 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7162 ctl, igu_addr_ctl);
7163 REG_WR(bp, igu_addr_ctl, ctl);
7164 mmiowb();
7165 barrier();
7166
7167 /* wait for clean up to finish */
7168 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7169 msleep(20);
7170
7171
7172 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7173 DP(NETIF_MSG_HW,
7174 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7175 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7176 }
7177}
7178
7179static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
f2e0899f 7180{
619c5cb6 7181 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 7182}
7183
1191cb83 7184static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
f2e0899f
DK		 7185{
7186 u32 i, base = FUNC_ILT_BASE(func);
7187 for (i = base; i < base + ILT_PER_FUNC; i++)
7188 bnx2x_ilt_wr(bp, i, 0);
7189}
7190
55c11941 7191
910cc727 7192static void bnx2x_init_searcher(struct bnx2x *bp)
55c11941
MS		 7193{
7194 int port = BP_PORT(bp);
7195 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7196 /* T1 hash bits value determines the T1 number of entries */
7197 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7198}
7199
7200static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7201{
7202 int rc;
7203 struct bnx2x_func_state_params func_params = {NULL};
7204 struct bnx2x_func_switch_update_params *switch_update_params =
7205 &func_params.params.switch_update;
7206
7207 /* Prepare parameters for function state transitions */
7208 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7209 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7210
7211 func_params.f_obj = &bp->func_obj;
7212 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7213
7214 /* Function parameters */
7215 switch_update_params->suspend = suspend;
7216
7217 rc = bnx2x_func_state_change(bp, &func_params);
7218
7219 return rc;
7220}
7221
910cc727 7222static int bnx2x_reset_nic_mode(struct bnx2x *bp)
55c11941
MS		 7223{
7224 int rc, i, port = BP_PORT(bp);
7225 int vlan_en = 0, mac_en[NUM_MACS];
7226
7227
7228 /* Close input from network */
7229 if (bp->mf_mode == SINGLE_FUNCTION) {
7230 bnx2x_set_rx_filter(&bp->link_params, 0);
7231 } else {
7232 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7233 NIG_REG_LLH0_FUNC_EN);
7234 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7235 NIG_REG_LLH0_FUNC_EN, 0);
7236 for (i = 0; i < NUM_MACS; i++) {
7237 mac_en[i] = REG_RD(bp, port ?
7238 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7239 4 * i) :
7240 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7241 4 * i));
7242 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7243 4 * i) :
7244 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7245 }
7246 }
7247
7248 /* Close BMC to host */
7249 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7250 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7251
7252 /* Suspend Tx switching to the PF. Completion of this ramrod
7253 * further guarantees that all the packets of that PF / child
7254 * VFs in BRB were processed by the Parser, so it is safe to
7255 * change the NIC_MODE register.
7256 */
7257 rc = bnx2x_func_switch_update(bp, 1);
7258 if (rc) {
7259 BNX2X_ERR("Can't suspend tx-switching!\n");
7260 return rc;
7261 }
7262
7263 /* Change NIC_MODE register */
7264 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7265
7266 /* Open input from network */
7267 if (bp->mf_mode == SINGLE_FUNCTION) {
7268 bnx2x_set_rx_filter(&bp->link_params, 1);
7269 } else {
7270 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7271 NIG_REG_LLH0_FUNC_EN, vlan_en);
7272 for (i = 0; i < NUM_MACS; i++) {
7273 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7274 4 * i) :
7275 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7276 mac_en[i]);
7277 }
7278 }
7279
7280 /* Enable BMC to host */
7281 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7282 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7283
7284 /* Resume Tx switching to the PF */
7285 rc = bnx2x_func_switch_update(bp, 0);
7286 if (rc) {
7287 BNX2X_ERR("Can't resume tx-switching!\n");
7288 return rc;
7289 }
7290
7291 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7292 return 0;
7293}
7294
7295int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7296{
7297 int rc;
7298
7299 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7300
7301 if (CONFIGURE_NIC_MODE(bp)) {
7302 /* Configrue searcher as part of function hw init */
7303 bnx2x_init_searcher(bp);
7304
7305 /* Reset NIC mode */
7306 rc = bnx2x_reset_nic_mode(bp);
7307 if (rc)
7308 BNX2X_ERR("Can't change NIC mode!\n");
7309 return rc;
7310 }
7311
7312 return 0;
7313}
7314
523224a3 7315static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 7316{
7317 int port = BP_PORT(bp);
7318 int func = BP_FUNC(bp);
619c5cb6 7319 int init_phase = PHASE_PF0 + func;
523224a3
DK		 7320 struct bnx2x_ilt *ilt = BP_ILT(bp);
7321 u16 cdu_ilt_start;
8badd27a 7322 u32 addr, val;
f4a66897 7323 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
89db4ad8 7324 int i, main_mem_width, rc;
34f80b04 7325
51c1a580 7326 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
34f80b04 7327
619c5cb6 7328 /* FLR cleanup - hmmm */
89db4ad8
AE		 7329 if (!CHIP_IS_E1x(bp)) {
7330 rc = bnx2x_pf_flr_clnup(bp);
7331 if (rc)
7332 return rc;
7333 }
619c5cb6 7334
8badd27a 7335 /* set MSI reconfigure capability */
f2e0899f
DK		 7336 if (bp->common.int_block == INT_BLOCK_HC) {
7337 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7338 val = REG_RD(bp, addr);
7339 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7340 REG_WR(bp, addr, val);
7341 }
8badd27a 7342
619c5cb6
VZ		 7343 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7344 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7345
523224a3
DK		 7346 ilt = BP_ILT(bp);
7347 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 7348
290ca2bb
AE		 7349 if (IS_SRIOV(bp))
7350 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7351 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7352
7353 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7354 * those of the VFs, so start line should be reset
7355 */
7356 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
523224a3 7357 for (i = 0; i < L2_ILT_LINES(bp); i++) {
a052997e 7358 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
523224a3 7359 ilt->lines[cdu_ilt_start + i].page_mapping =
a052997e
MS		 7360 bp->context[i].cxt_mapping;
7361 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
37b091ba 7362 }
290ca2bb 7363
523224a3 7364 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 7365
55c11941
MS		 7366 if (!CONFIGURE_NIC_MODE(bp)) {
7367 bnx2x_init_searcher(bp);
7368 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7369 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7370 } else {
7371 /* Set NIC mode */
7372 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7373 DP(NETIF_MSG_IFUP, "NIC MODE configrued\n");
37b091ba 7374
55c11941 7375 }
37b091ba 7376
619c5cb6 7377 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7378 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7379
7380 /* Turn on a single ISR mode in IGU if driver is going to use
7381 * INT#x or MSI
7382 */
7383 if (!(bp->flags & USING_MSIX_FLAG))
7384 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7385 /*
7386 * Timers workaround bug: function init part.
7387 * Need to wait 20msec after initializing ILT,
7388 * needed to make sure there are no requests in
7389 * one of the PXP internal queues with "old" ILT addresses
7390 */
7391 msleep(20);
7392 /*
7393 * Master enable - Due to WB DMAE writes performed before this
7394 * register is re-initialized as part of the regular function
7395 * init
7396 */
7397 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7398 /* Enable the function in IGU */
7399 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7400 }
7401
523224a3 7402 bp->dmae_ready = 1;
34f80b04 7403
619c5cb6 7404 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 7405
619c5cb6 7406 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7407 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7408
619c5cb6
VZ		 7409 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7410 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7411 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7412 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7413 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7414 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7415 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7416 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7417 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7418 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7419 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7420 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7421 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7422
7423 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7424 REG_WR(bp, QM_REG_PF_EN, 1);
7425
619c5cb6
VZ		 7426 if (!CHIP_IS_E1x(bp)) {
7427 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7428 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7429 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7430 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7431 }
7432 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7433
7434 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7435 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
b56e9670
AE		 7436
7437 bnx2x_iov_init_dq(bp);
7438
619c5cb6
VZ		 7439 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7440 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7441 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7442 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7443 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7444 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7445 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7446 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7447 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7448 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7449 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7450
619c5cb6 7451 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 7452
619c5cb6 7453 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 7454
619c5cb6 7455 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7456 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7457
fb3bff17 7458 if (IS_MF(bp)) {
34f80b04 7459 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 7460 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 7461 }
7462
619c5cb6 7463 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 7464
34f80b04 7465 /* HC init per function */
f2e0899f
DK		 7466 if (bp->common.int_block == INT_BLOCK_HC) {
7467 if (CHIP_IS_E1H(bp)) {
7468 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7469
7470 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7471 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7472 }
619c5cb6 7473 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 7474
7475 } else {
7476 int num_segs, sb_idx, prod_offset;
7477
34f80b04
EG		 7478 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7479
619c5cb6 7480 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7481 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7482 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7483 }
7484
619c5cb6 7485 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7486
619c5cb6 7487 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7488 int dsb_idx = 0;
7489 /**
7490 * Producer memory:
7491 * E2 mode: address 0-135 match to the mapping memory;
7492 * 136 - PF0 default prod; 137 - PF1 default prod;
7493 * 138 - PF2 default prod; 139 - PF3 default prod;
7494 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7495 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7496 * 144-147 reserved.
7497 *
7498 * E1.5 mode - In backward compatible mode;
7499 * for non default SB; each even line in the memory
7500 * holds the U producer and each odd line hold
7501 * the C producer. The first 128 producers are for
7502 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7503 * producers are for the DSB for each PF.
7504 * Each PF has five segments: (the order inside each
7505 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7506 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7507 * 144-147 attn prods;
7508 */
7509 /* non-default-status-blocks */
7510 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7511 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7512 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7513 prod_offset = (bp->igu_base_sb + sb_idx) *
7514 num_segs;
7515
7516 for (i = 0; i < num_segs; i++) {
7517 addr = IGU_REG_PROD_CONS_MEMORY +
7518 (prod_offset + i) * 4;
7519 REG_WR(bp, addr, 0);
7520 }
7521 /* send consumer update with value 0 */
7522 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7523 USTORM_ID, 0, IGU_INT_NOP, 1);
7524 bnx2x_igu_clear_sb(bp,
7525 bp->igu_base_sb + sb_idx);
7526 }
7527
7528 /* default-status-blocks */
7529 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7530 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7531
7532 if (CHIP_MODE_IS_4_PORT(bp))
7533 dsb_idx = BP_FUNC(bp);
7534 else
3395a033 7535 dsb_idx = BP_VN(bp);
f2e0899f
DK		 7536
7537 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7538 IGU_BC_BASE_DSB_PROD + dsb_idx :
7539 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7540
3395a033
DK		 7541 /*
7542 * igu prods come in chunks of E1HVN_MAX (4) -
7543 * does not matters what is the current chip mode
7544 */
f2e0899f
DK		 7545 for (i = 0; i < (num_segs * E1HVN_MAX);
7546 i += E1HVN_MAX) {
7547 addr = IGU_REG_PROD_CONS_MEMORY +
7548 (prod_offset + i)*4;
7549 REG_WR(bp, addr, 0);
7550 }
7551 /* send consumer update with 0 */
7552 if (CHIP_INT_MODE_IS_BC(bp)) {
7553 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7554 USTORM_ID, 0, IGU_INT_NOP, 1);
7555 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7556 CSTORM_ID, 0, IGU_INT_NOP, 1);
7557 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7558 XSTORM_ID, 0, IGU_INT_NOP, 1);
7559 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7560 TSTORM_ID, 0, IGU_INT_NOP, 1);
7561 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7562 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7563 } else {
7564 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7565 USTORM_ID, 0, IGU_INT_NOP, 1);
7566 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7567 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7568 }
7569 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7570
7571 /* !!! these should become driver const once
7572 rf-tool supports split-68 const */
7573 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7574 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7575 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7576 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7577 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7578 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7579 }
34f80b04 7580 }
34f80b04 7581
c14423fe 7582 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 7583 REG_WR(bp, 0x2114, 0xffffffff);
7584 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 7585
f4a66897
VZ		 7586 if (CHIP_IS_E1x(bp)) {
7587 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7588 main_mem_base = HC_REG_MAIN_MEMORY +
7589 BP_PORT(bp) * (main_mem_size * 4);
7590 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7591 main_mem_width = 8;
7592
7593 val = REG_RD(bp, main_mem_prty_clr);
7594 if (val)
51c1a580
MS		 7595 DP(NETIF_MSG_HW,
7596 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7597 val);
f4a66897
VZ		 7598
7599 /* Clear "false" parity errors in MSI-X table */
7600 for (i = main_mem_base;
7601 i < main_mem_base + main_mem_size * 4;
7602 i += main_mem_width) {
7603 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7604 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7605 i, main_mem_width / 4);
7606 }
7607 /* Clear HC parity attention */
7608 REG_RD(bp, main_mem_prty_clr);
7609 }
7610
619c5cb6
VZ		 7611#ifdef BNX2X_STOP_ON_ERROR
7612 /* Enable STORMs SP logging */
7613 REG_WR8(bp, BAR_USTRORM_INTMEM +
7614 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7615 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7616 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7617 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7618 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7619 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7620 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7621#endif
7622
b7737c9b 7623 bnx2x_phy_probe(&bp->link_params);
f85582f8 7624
34f80b04
EG		 7625 return 0;
7626}
7627
a2fbb9ea 7628
55c11941
MS		 7629void bnx2x_free_mem_cnic(struct bnx2x *bp)
7630{
7631 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7632
7633 if (!CHIP_IS_E1x(bp))
7634 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7635 sizeof(struct host_hc_status_block_e2));
7636 else
7637 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7638 sizeof(struct host_hc_status_block_e1x));
7639
7640 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7641}
7642
9f6c9258 7643void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 7644{
a052997e
MS		 7645 int i;
7646
a2fbb9ea 7647 /* fastpath */
b3b83c3f 7648 bnx2x_free_fp_mem(bp);
a2fbb9ea
ET		 7649 /* end of fastpath */
7650
7651 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
523224a3 7652 sizeof(struct host_sp_status_block));
a2fbb9ea 7653
619c5cb6
VZ		 7654 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7655 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7656
a2fbb9ea 7657 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 7658 sizeof(struct bnx2x_slowpath));
a2fbb9ea 7659
a052997e
MS		 7660 for (i = 0; i < L2_ILT_LINES(bp); i++)
7661 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7662 bp->context[i].size);
523224a3
DK		 7663 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7664
7665 BNX2X_FREE(bp->ilt->lines);
f85582f8 7666
7a9b2557 7667 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 7668
523224a3
DK		 7669 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7670 BCM_PAGE_SIZE * NUM_EQ_PAGES);
619c5cb6
VZ		 7671}
7672
1191cb83 7673static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
619c5cb6
VZ		 7674{
7675 int num_groups;
50f0a562 7676 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
619c5cb6 7677
50f0a562
BW		 7678 /* number of queues for statistics is number of eth queues + FCoE */
7679 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
619c5cb6
VZ		 7680
7681 /* Total number of FW statistics requests =
50f0a562
BW		 7682 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7683 * num of queues
7684 */
7685 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
523224a3 7686
619c5cb6
VZ		 7687
7688 /* Request is built from stats_query_header and an array of
7689 * stats_query_cmd_group each of which contains
7690 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7691 * configured in the stats_query_header.
7692 */
50f0a562
BW		 7693 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
7694 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
619c5cb6
VZ		 7695
7696 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
7697 num_groups * sizeof(struct stats_query_cmd_group);
7698
7699 /* Data for statistics requests + stats_conter
7700 *
7701 * stats_counter holds per-STORM counters that are incremented
7702 * when STORM has finished with the current request.
50f0a562
BW		 7703 *
7704 * memory for FCoE offloaded statistics are counted anyway,
7705 * even if they will not be sent.
619c5cb6
VZ		 7706 */
7707 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
7708 sizeof(struct per_pf_stats) +
50f0a562 7709 sizeof(struct fcoe_statistics_params) +
619c5cb6
VZ		 7710 sizeof(struct per_queue_stats) * num_queue_stats +
7711 sizeof(struct stats_counter);
7712
7713 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
7714 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7715
7716 /* Set shortcuts */
7717 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
7718 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
7719
7720 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
7721 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
7722
7723 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
7724 bp->fw_stats_req_sz;
7725 return 0;
7726
7727alloc_mem_err:
7728 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7729 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
51c1a580 7730 BNX2X_ERR("Can't allocate memory\n");
619c5cb6 7731 return -ENOMEM;
a2fbb9ea
ET		 7732}
7733
55c11941 7734int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
a2fbb9ea 7735{
619c5cb6
VZ		 7736 if (!CHIP_IS_E1x(bp))
7737 /* size = the status block + ramrod buffers */
f2e0899f
DK		 7738 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7739 sizeof(struct host_hc_status_block_e2));
7740 else
55c11941
MS		 7741 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7742 &bp->cnic_sb_mapping,
7743 sizeof(struct
7744 host_hc_status_block_e1x));
8badd27a 7745
55c11941
MS		 7746 if (CONFIGURE_NIC_MODE(bp))
7747 /* allocate searcher T2 table, as it wan't allocated before */
7748 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7749
7750 /* write address to which L5 should insert its values */
7751 bp->cnic_eth_dev.addr_drv_info_to_mcp =
7752 &bp->slowpath->drv_info_to_mcp;
7753
7754 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7755 goto alloc_mem_err;
7756
7757 return 0;
7758
7759alloc_mem_err:
7760 bnx2x_free_mem_cnic(bp);
7761 BNX2X_ERR("Can't allocate memory\n");
7762 return -ENOMEM;
7763}
7764
7765int bnx2x_alloc_mem(struct bnx2x *bp)
7766{
7767 int i, allocated, context_size;
a2fbb9ea 7768
55c11941
MS		 7769 if (!CONFIGURE_NIC_MODE(bp))
7770 /* allocate searcher T2 table */
7771 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
8badd27a 7772
523224a3
DK		 7773 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7774 sizeof(struct host_sp_status_block));
a2fbb9ea 7775
523224a3
DK		 7776 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7777 sizeof(struct bnx2x_slowpath));
a2fbb9ea 7778
619c5cb6
VZ		 7779 /* Allocated memory for FW statistics */
7780 if (bnx2x_alloc_fw_stats_mem(bp))
7781 goto alloc_mem_err;
7782
a052997e
MS		 7783 /* Allocate memory for CDU context:
7784 * This memory is allocated separately and not in the generic ILT
7785 * functions because CDU differs in few aspects:
7786 * 1. There are multiple entities allocating memory for context -
7787 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7788 * its own ILT lines.
7789 * 2. Since CDU page-size is not a single 4KB page (which is the case
7790 * for the other ILT clients), to be efficient we want to support
7791 * allocation of sub-page-size in the last entry.
7792 * 3. Context pointers are used by the driver to pass to FW / update
7793 * the context (for the other ILT clients the pointers are used just to
7794 * free the memory during unload).
7795 */
7796 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
65abd74d 7797
a052997e
MS		 7798 for (i = 0, allocated = 0; allocated < context_size; i++) {
7799 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7800 (context_size - allocated));
7801 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7802 &bp->context[i].cxt_mapping,
7803 bp->context[i].size);
7804 allocated += bp->context[i].size;
7805 }
523224a3 7806 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 7807
523224a3
DK		 7808 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7809 goto alloc_mem_err;
65abd74d 7810
9f6c9258
DK		 7811 /* Slow path ring */
7812 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 7813
523224a3
DK		 7814 /* EQ */
7815 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7816 BCM_PAGE_SIZE * NUM_EQ_PAGES);
ab532cf3 7817
b3b83c3f
DK		 7818
7819 /* fastpath */
7820 /* need to be done at the end, since it's self adjusting to amount
7821 * of memory available for RSS queues
7822 */
7823 if (bnx2x_alloc_fp_mem(bp))
7824 goto alloc_mem_err;
9f6c9258 7825 return 0;
e1510706 7826
9f6c9258
DK		 7827alloc_mem_err:
7828 bnx2x_free_mem(bp);
51c1a580 7829 BNX2X_ERR("Can't allocate memory\n");
9f6c9258 7830 return -ENOMEM;
65abd74d
YG		 7831}
7832
a2fbb9ea
ET		 7833/*
7834 * Init service functions
7835 */
a2fbb9ea 7836
619c5cb6
VZ		 7837int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7838 struct bnx2x_vlan_mac_obj *obj, bool set,
7839 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 7840{
619c5cb6
VZ		 7841 int rc;
7842 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 7843
619c5cb6 7844 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 7845
619c5cb6
VZ		 7846 /* Fill general parameters */
7847 ramrod_param.vlan_mac_obj = obj;
7848 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 7849
619c5cb6
VZ		 7850 /* Fill a user request section if needed */
7851 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7852 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 7853
619c5cb6 7854 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 7855
619c5cb6
VZ		 7856 /* Set the command: ADD or DEL */
7857 if (set)
7858 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7859 else
7860 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 7861 }
7862
619c5cb6 7863 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7b5342d9
YM		 7864
7865 if (rc == -EEXIST) {
7866 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7867 /* do not treat adding same MAC as error */
7868 rc = 0;
7869 } else if (rc < 0)
619c5cb6 7870 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7b5342d9 7871
619c5cb6 7872 return rc;
a2fbb9ea
ET		 7873}
7874
619c5cb6
VZ		 7875int bnx2x_del_all_macs(struct bnx2x *bp,
7876 struct bnx2x_vlan_mac_obj *mac_obj,
7877 int mac_type, bool wait_for_comp)
e665bfda 7878{
619c5cb6
VZ		 7879 int rc;
7880 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 7881
619c5cb6
VZ		 7882 /* Wait for completion of requested */
7883 if (wait_for_comp)
7884 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 7885
619c5cb6
VZ		 7886 /* Set the mac type of addresses we want to clear */
7887 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 7888
619c5cb6
VZ		 7889 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7890 if (rc < 0)
7891 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 7892
619c5cb6 7893 return rc;
0793f83f
DK		 7894}
7895
619c5cb6 7896int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 7897{
619c5cb6 7898 unsigned long ramrod_flags = 0;
e665bfda 7899
a3348722
BW		 7900 if (is_zero_ether_addr(bp->dev->dev_addr) &&
7901 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
51c1a580
MS		 7902 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7903 "Ignoring Zero MAC for STORAGE SD mode\n");
614c76df
DK		 7904 return 0;
7905 }
614c76df 7906
619c5cb6 7907 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
0793f83f 7908
619c5cb6
VZ		 7909 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7910 /* Eth MAC is set on RSS leading client (fp[0]) */
15192a8c
BW		 7911 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7912 set, BNX2X_ETH_MAC, &ramrod_flags);
e665bfda 7913}
6e30dd4e 7914
619c5cb6 7915int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 7916{
619c5cb6 7917 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
993ac7b5 7918}
a2fbb9ea 7919
d6214d7a 7920/**
e8920674 7921 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 7922 *
e8920674 7923 * @bp: driver handle
d6214d7a 7924 *
e8920674 7925 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 7926 */
1ab4434c 7927int bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 7928{
1ab4434c
AE		 7929 int rc = 0;
7930
7931 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX)
7932 return -EINVAL;
7933
9ee3d37b 7934 switch (int_mode) {
1ab4434c
AE		 7935 case BNX2X_INT_MODE_MSIX:
7936 /* attempt to enable msix */
7937 rc = bnx2x_enable_msix(bp);
7938
7939 /* msix attained */
7940 if (!rc)
7941 return 0;
7942
7943 /* vfs use only msix */
7944 if (rc && IS_VF(bp))
7945 return rc;
7946
7947 /* failed to enable multiple MSI-X */
7948 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7949 bp->num_queues,
7950 1 + bp->num_cnic_queues);
7951
7952 /* falling through... */
7953 case BNX2X_INT_MODE_MSI:
d6214d7a 7954 bnx2x_enable_msi(bp);
1ab4434c 7955
d6214d7a 7956 /* falling through... */
1ab4434c 7957 case BNX2X_INT_MODE_INTX:
55c11941
MS		 7958 bp->num_ethernet_queues = 1;
7959 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
51c1a580 7960 BNX2X_DEV_INFO("set number of queues to 1\n");
ca00392c 7961 break;
d6214d7a 7962 default:
1ab4434c
AE		 7963 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
7964 return -EINVAL;
9f6c9258 7965 }
1ab4434c 7966 return 0;
a2fbb9ea
ET		 7967}
7968
1ab4434c 7969/* must be called prior to any HW initializations */
c2bff63f
DK		 7970static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7971{
290ca2bb
AE		 7972 if (IS_SRIOV(bp))
7973 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
c2bff63f
DK		 7974 return L2_ILT_LINES(bp);
7975}
7976
523224a3
DK		 7977void bnx2x_ilt_set_info(struct bnx2x *bp)
7978{
7979 struct ilt_client_info *ilt_client;
7980 struct bnx2x_ilt *ilt = BP_ILT(bp);
7981 u16 line = 0;
7982
7983 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7984 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7985
7986 /* CDU */
7987 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7988 ilt_client->client_num = ILT_CLIENT_CDU;
7989 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7990 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7991 ilt_client->start = line;
619c5cb6 7992 line += bnx2x_cid_ilt_lines(bp);
55c11941
MS		 7993
7994 if (CNIC_SUPPORT(bp))
7995 line += CNIC_ILT_LINES;
523224a3
DK		 7996 ilt_client->end = line - 1;
7997
51c1a580 7998 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 7999 ilt_client->start,
8000 ilt_client->end,
8001 ilt_client->page_size,
8002 ilt_client->flags,
8003 ilog2(ilt_client->page_size >> 12));
8004
8005 /* QM */
8006 if (QM_INIT(bp->qm_cid_count)) {
8007 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8008 ilt_client->client_num = ILT_CLIENT_QM;
8009 ilt_client->page_size = QM_ILT_PAGE_SZ;
8010 ilt_client->flags = 0;
8011 ilt_client->start = line;
8012
8013 /* 4 bytes for each cid */
8014 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8015 QM_ILT_PAGE_SZ);
8016
8017 ilt_client->end = line - 1;
8018
51c1a580
MS		 8019 DP(NETIF_MSG_IFUP,
8020 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8021 ilt_client->start,
8022 ilt_client->end,
8023 ilt_client->page_size,
8024 ilt_client->flags,
8025 ilog2(ilt_client->page_size >> 12));
8026
8027 }
523224a3 8028
55c11941
MS		 8029 if (CNIC_SUPPORT(bp)) {
8030 /* SRC */
8031 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8032 ilt_client->client_num = ILT_CLIENT_SRC;
8033 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8034 ilt_client->flags = 0;
8035 ilt_client->start = line;
8036 line += SRC_ILT_LINES;
8037 ilt_client->end = line - 1;
523224a3 8038
55c11941
MS		 8039 DP(NETIF_MSG_IFUP,
8040 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8041 ilt_client->start,
8042 ilt_client->end,
8043 ilt_client->page_size,
8044 ilt_client->flags,
8045 ilog2(ilt_client->page_size >> 12));
9f6c9258 8046
55c11941
MS		 8047 /* TM */
8048 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8049 ilt_client->client_num = ILT_CLIENT_TM;
8050 ilt_client->page_size = TM_ILT_PAGE_SZ;
8051 ilt_client->flags = 0;
8052 ilt_client->start = line;
8053 line += TM_ILT_LINES;
8054 ilt_client->end = line - 1;
523224a3 8055
55c11941
MS		 8056 DP(NETIF_MSG_IFUP,
8057 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8058 ilt_client->start,
8059 ilt_client->end,
8060 ilt_client->page_size,
8061 ilt_client->flags,
8062 ilog2(ilt_client->page_size >> 12));
8063 }
9f6c9258 8064
619c5cb6 8065 BUG_ON(line > ILT_MAX_LINES);
523224a3 8066}
f85582f8 8067
619c5cb6
VZ		 8068/**
8069 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8070 *
8071 * @bp: driver handle
8072 * @fp: pointer to fastpath
8073 * @init_params: pointer to parameters structure
8074 *
8075 * parameters configured:
8076 * - HC configuration
8077 * - Queue's CDU context
8078 */
1191cb83 8079static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
619c5cb6 8080 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 8081{
6383c0b3
AE		 8082
8083 u8 cos;
a052997e
MS		 8084 int cxt_index, cxt_offset;
8085
619c5cb6
VZ		 8086 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8087 if (!IS_FCOE_FP(fp)) {
8088 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8089 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8090
8091 /* If HC is supporterd, enable host coalescing in the transition
8092 * to INIT state.
8093 */
8094 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8095 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8096
8097 /* HC rate */
8098 init_params->rx.hc_rate = bp->rx_ticks ?
8099 (1000000 / bp->rx_ticks) : 0;
8100 init_params->tx.hc_rate = bp->tx_ticks ?
8101 (1000000 / bp->tx_ticks) : 0;
8102
8103 /* FW SB ID */
8104 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8105 fp->fw_sb_id;
8106
8107 /*
8108 * CQ index among the SB indices: FCoE clients uses the default
8109 * SB, therefore it's different.
8110 */
6383c0b3
AE		 8111 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8112 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 8113 }
8114
6383c0b3
AE		 8115 /* set maximum number of COSs supported by this queue */
8116 init_params->max_cos = fp->max_cos;
8117
51c1a580 8118 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 8119 fp->index, init_params->max_cos);
8120
8121 /* set the context pointers queue object */
a052997e 8122 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
65565884
MS		 8123 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8124 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
a052997e 8125 ILT_PAGE_CIDS);
6383c0b3 8126 init_params->cxts[cos] =
a052997e
MS		 8127 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8128 }
619c5cb6
VZ		 8129}
8130
910cc727 8131static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6383c0b3
AE		 8132 struct bnx2x_queue_state_params *q_params,
8133 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8134 int tx_index, bool leading)
8135{
8136 memset(tx_only_params, 0, sizeof(*tx_only_params));
8137
8138 /* Set the command */
8139 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8140
8141 /* Set tx-only QUEUE flags: don't zero statistics */
8142 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8143
8144 /* choose the index of the cid to send the slow path on */
8145 tx_only_params->cid_index = tx_index;
8146
8147 /* Set general TX_ONLY_SETUP parameters */
8148 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8149
8150 /* Set Tx TX_ONLY_SETUP parameters */
8151 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8152
51c1a580
MS		 8153 DP(NETIF_MSG_IFUP,
8154 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 8155 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8156 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8157 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8158
8159 /* send the ramrod */
8160 return bnx2x_queue_state_change(bp, q_params);
8161}
8162
8163
619c5cb6
VZ		 8164/**
8165 * bnx2x_setup_queue - setup queue
8166 *
8167 * @bp: driver handle
8168 * @fp: pointer to fastpath
8169 * @leading: is leading
8170 *
8171 * This function performs 2 steps in a Queue state machine
8172 * actually: 1) RESET->INIT 2) INIT->SETUP
8173 */
8174
8175int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8176 bool leading)
8177{
3b603066 8178 struct bnx2x_queue_state_params q_params = {NULL};
619c5cb6
VZ		 8179 struct bnx2x_queue_setup_params *setup_params =
8180 &q_params.params.setup;
6383c0b3
AE		 8181 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8182 &q_params.params.tx_only;
a2fbb9ea 8183 int rc;
6383c0b3
AE		 8184 u8 tx_index;
8185
51c1a580 8186 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
a2fbb9ea 8187
ec6ba945
VZ		 8188 /* reset IGU state skip FCoE L2 queue */
8189 if (!IS_FCOE_FP(fp))
8190 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 8191 IGU_INT_ENABLE, 0);
a2fbb9ea 8192
15192a8c 8193 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8194 /* We want to wait for completion in this context */
8195 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8196
619c5cb6
VZ		 8197 /* Prepare the INIT parameters */
8198 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 8199
619c5cb6
VZ		 8200 /* Set the command */
8201 q_params.cmd = BNX2X_Q_CMD_INIT;
8202
8203 /* Change the state to INIT */
8204 rc = bnx2x_queue_state_change(bp, &q_params);
8205 if (rc) {
6383c0b3 8206 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 8207 return rc;
8208 }
ec6ba945 8209
51c1a580 8210 DP(NETIF_MSG_IFUP, "init complete\n");
6383c0b3
AE		 8211
8212
619c5cb6
VZ		 8213 /* Now move the Queue to the SETUP state... */
8214 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 8215
619c5cb6
VZ		 8216 /* Set QUEUE flags */
8217 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 8218
619c5cb6 8219 /* Set general SETUP parameters */
6383c0b3
AE		 8220 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8221 FIRST_TX_COS_INDEX);
619c5cb6 8222
6383c0b3 8223 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 8224 &setup_params->rxq_params);
8225
6383c0b3
AE		 8226 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8227 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 8228
8229 /* Set the command */
8230 q_params.cmd = BNX2X_Q_CMD_SETUP;
8231
55c11941
MS		 8232 if (IS_FCOE_FP(fp))
8233 bp->fcoe_init = true;
8234
619c5cb6
VZ		 8235 /* Change the state to SETUP */
8236 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 8237 if (rc) {
8238 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8239 return rc;
8240 }
8241
8242 /* loop through the relevant tx-only indices */
8243 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8244 tx_index < fp->max_cos;
8245 tx_index++) {
8246
8247 /* prepare and send tx-only ramrod*/
8248 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8249 tx_only_params, tx_index, leading);
8250 if (rc) {
8251 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8252 fp->index, tx_index);
8253 return rc;
8254 }
8255 }
523224a3 8256
34f80b04 8257 return rc;
a2fbb9ea
ET		 8258}
8259
619c5cb6 8260static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 8261{
619c5cb6 8262 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 8263 struct bnx2x_fp_txdata *txdata;
3b603066 8264 struct bnx2x_queue_state_params q_params = {NULL};
6383c0b3
AE		 8265 int rc, tx_index;
8266
51c1a580 8267 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 8268
15192a8c 8269 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8270 /* We want to wait for completion in this context */
8271 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8272
6383c0b3
AE		 8273
8274 /* close tx-only connections */
8275 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8276 tx_index < fp->max_cos;
8277 tx_index++){
8278
8279 /* ascertain this is a normal queue*/
65565884 8280 txdata = fp->txdata_ptr[tx_index];
6383c0b3 8281
51c1a580 8282 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
6383c0b3
AE		 8283 txdata->txq_index);
8284
8285 /* send halt terminate on tx-only connection */
8286 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8287 memset(&q_params.params.terminate, 0,
8288 sizeof(q_params.params.terminate));
8289 q_params.params.terminate.cid_index = tx_index;
8290
8291 rc = bnx2x_queue_state_change(bp, &q_params);
8292 if (rc)
8293 return rc;
8294
8295 /* send halt terminate on tx-only connection */
8296 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8297 memset(&q_params.params.cfc_del, 0,
8298 sizeof(q_params.params.cfc_del));
8299 q_params.params.cfc_del.cid_index = tx_index;
8300 rc = bnx2x_queue_state_change(bp, &q_params);
8301 if (rc)
8302 return rc;
8303 }
8304 /* Stop the primary connection: */
8305 /* ...halt the connection */
619c5cb6
VZ		 8306 q_params.cmd = BNX2X_Q_CMD_HALT;
8307 rc = bnx2x_queue_state_change(bp, &q_params);
8308 if (rc)
da5a662a 8309 return rc;
a2fbb9ea 8310
6383c0b3 8311 /* ...terminate the connection */
619c5cb6 8312 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 8313 memset(&q_params.params.terminate, 0,
8314 sizeof(q_params.params.terminate));
8315 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 8316 rc = bnx2x_queue_state_change(bp, &q_params);
8317 if (rc)
523224a3 8318 return rc;
6383c0b3 8319 /* ...delete cfc entry */
619c5cb6 8320 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 8321 memset(&q_params.params.cfc_del, 0,
8322 sizeof(q_params.params.cfc_del));
8323 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 8324 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 8325}
8326
8327
34f80b04
EG		 8328static void bnx2x_reset_func(struct bnx2x *bp)
8329{
8330 int port = BP_PORT(bp);
8331 int func = BP_FUNC(bp);
f2e0899f 8332 int i;
523224a3
DK		 8333
8334 /* Disable the function in the FW */
8335 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8336 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8337 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8338 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8339
8340 /* FP SBs */
ec6ba945 8341 for_each_eth_queue(bp, i) {
523224a3 8342 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 8343 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 8344 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8345 SB_DISABLED);
523224a3
DK		 8346 }
8347
55c11941
MS		 8348 if (CNIC_LOADED(bp))
8349 /* CNIC SB */
8350 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8351 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8352 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8353
523224a3 8354 /* SP SB */
619c5cb6 8355 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 8356 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8357 SB_DISABLED);
523224a3
DK		 8358
8359 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8360 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8361 0);
34f80b04
EG		 8362
8363 /* Configure IGU */
f2e0899f
DK		 8364 if (bp->common.int_block == INT_BLOCK_HC) {
8365 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8366 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8367 } else {
8368 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8369 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8370 }
34f80b04 8371
55c11941
MS		 8372 if (CNIC_LOADED(bp)) {
8373 /* Disable Timer scan */
8374 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8375 /*
8376 * Wait for at least 10ms and up to 2 second for the timers
8377 * scan to complete
8378 */
8379 for (i = 0; i < 200; i++) {
8380 msleep(10);
8381 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8382 break;
8383 }
37b091ba 8384 }
34f80b04 8385 /* Clear ILT */
f2e0899f
DK		 8386 bnx2x_clear_func_ilt(bp, func);
8387
8388 /* Timers workaround bug for E2: if this is vnic-3,
8389 * we need to set the entire ilt range for this timers.
8390 */
619c5cb6 8391 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 8392 struct ilt_client_info ilt_cli;
8393 /* use dummy TM client */
8394 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8395 ilt_cli.start = 0;
8396 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8397 ilt_cli.client_num = ILT_CLIENT_TM;
8398
8399 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8400 }
8401
8402 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 8403 if (!CHIP_IS_E1x(bp))
f2e0899f 8404 bnx2x_pf_disable(bp);
523224a3
DK		 8405
8406 bp->dmae_ready = 0;
34f80b04
EG		 8407}
8408
8409static void bnx2x_reset_port(struct bnx2x *bp)
8410{
8411 int port = BP_PORT(bp);
8412 u32 val;
8413
619c5cb6
VZ		 8414 /* Reset physical Link */
8415 bnx2x__link_reset(bp);
8416
34f80b04
EG		 8417 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8418
8419 /* Do not rcv packets to BRB */
8420 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8421 /* Do not direct rcv packets that are not for MCP to the BRB */
8422 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8423 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8424
8425 /* Configure AEU */
8426 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8427
8428 msleep(100);
8429 /* Check for BRB port occupancy */
8430 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8431 if (val)
8432 DP(NETIF_MSG_IFDOWN,
33471629 8433 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 8434
8435 /* TODO: Close Doorbell port? */
8436}
8437
1191cb83 8438static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 8439{
3b603066 8440 struct bnx2x_func_state_params func_params = {NULL};
34f80b04 8441
619c5cb6
VZ		 8442 /* Prepare parameters for function state transitions */
8443 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 8444
619c5cb6
VZ		 8445 func_params.f_obj = &bp->func_obj;
8446 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 8447
619c5cb6 8448 func_params.params.hw_init.load_phase = load_code;
49d66772 8449
619c5cb6 8450 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 8451}
8452
1191cb83 8453static int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 8454{
3b603066 8455 struct bnx2x_func_state_params func_params = {NULL};
619c5cb6 8456 int rc;
228241eb 8457
619c5cb6
VZ		 8458 /* Prepare parameters for function state transitions */
8459 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8460 func_params.f_obj = &bp->func_obj;
8461 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 8462
619c5cb6
VZ		 8463 /*
8464 * Try to stop the function the 'good way'. If fails (in case
8465 * of a parity error during bnx2x_chip_cleanup()) and we are
8466 * not in a debug mode, perform a state transaction in order to
8467 * enable further HW_RESET transaction.
8468 */
8469 rc = bnx2x_func_state_change(bp, &func_params);
8470 if (rc) {
34f80b04 8471#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 8472 return rc;
34f80b04 8473#else
51c1a580 8474 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
619c5cb6
VZ		 8475 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8476 return bnx2x_func_state_change(bp, &func_params);
34f80b04 8477#endif
228241eb 8478 }
a2fbb9ea 8479
619c5cb6
VZ		 8480 return 0;
8481}
523224a3 8482
619c5cb6
VZ		 8483/**
8484 * bnx2x_send_unload_req - request unload mode from the MCP.
8485 *
8486 * @bp: driver handle
8487 * @unload_mode: requested function's unload mode
8488 *
8489 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8490 */
8491u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8492{
8493 u32 reset_code = 0;
8494 int port = BP_PORT(bp);
3101c2bc 8495
619c5cb6 8496 /* Select the UNLOAD request mode */
65abd74d
YG		 8497 if (unload_mode == UNLOAD_NORMAL)
8498 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8499
7d0446c2 8500 else if (bp->flags & NO_WOL_FLAG)
65abd74d 8501 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 8502
7d0446c2 8503 else if (bp->wol) {
65abd74d
YG		 8504 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8505 u8 *mac_addr = bp->dev->dev_addr;
8506 u32 val;
f9977903
DK		 8507 u16 pmc;
8508
65abd74d 8509 /* The mac address is written to entries 1-4 to
f9977903
DK		 8510 * preserve entry 0 which is used by the PMF
8511 */
3395a033 8512 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 8513
8514 val = (mac_addr[0] << 8) | mac_addr[1];
8515 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8516
8517 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8518 (mac_addr[4] << 8) | mac_addr[5];
8519 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8520
f9977903
DK		 8521 /* Enable the PME and clear the status */
8522 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8523 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8524 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8525
65abd74d
YG		 8526 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8527
8528 } else
8529 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 8530
619c5cb6
VZ		 8531 /* Send the request to the MCP */
8532 if (!BP_NOMCP(bp))
8533 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8534 else {
8535 int path = BP_PATH(bp);
8536
51c1a580 8537 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
619c5cb6
VZ		 8538 path, load_count[path][0], load_count[path][1],
8539 load_count[path][2]);
8540 load_count[path][0]--;
8541 load_count[path][1 + port]--;
51c1a580 8542 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
619c5cb6
VZ		 8543 path, load_count[path][0], load_count[path][1],
8544 load_count[path][2]);
8545 if (load_count[path][0] == 0)
8546 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8547 else if (load_count[path][1 + port] == 0)
8548 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8549 else
8550 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8551 }
8552
8553 return reset_code;
8554}
8555
8556/**
8557 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8558 *
8559 * @bp: driver handle
5d07d868 8560 * @keep_link: true iff link should be kept up
619c5cb6 8561 */
5d07d868 8562void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
619c5cb6 8563{
5d07d868
YM		 8564 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8565
619c5cb6
VZ		 8566 /* Report UNLOAD_DONE to MCP */
8567 if (!BP_NOMCP(bp))
5d07d868 8568 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
619c5cb6
VZ		 8569}
8570
1191cb83 8571static int bnx2x_func_wait_started(struct bnx2x *bp)
6debea87
DK		 8572{
8573 int tout = 50;
8574 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8575
8576 if (!bp->port.pmf)
8577 return 0;
8578
8579 /*
8580 * (assumption: No Attention from MCP at this stage)
8581 * PMF probably in the middle of TXdisable/enable transaction
8582 * 1. Sync IRS for default SB
8583 * 2. Sync SP queue - this guarantes us that attention handling started
8584 * 3. Wait, that TXdisable/enable transaction completes
8585 *
8586 * 1+2 guranty that if DCBx attention was scheduled it already changed
8587 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8588 * received complettion for the transaction the state is TX_STOPPED.
8589 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8590 * transaction.
8591 */
8592
8593 /* make sure default SB ISR is done */
8594 if (msix)
8595 synchronize_irq(bp->msix_table[0].vector);
8596 else
8597 synchronize_irq(bp->pdev->irq);
8598
8599 flush_workqueue(bnx2x_wq);
8600
8601 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8602 BNX2X_F_STATE_STARTED && tout--)
8603 msleep(20);
8604
8605 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8606 BNX2X_F_STATE_STARTED) {
8607#ifdef BNX2X_STOP_ON_ERROR
51c1a580 8608 BNX2X_ERR("Wrong function state\n");
6debea87
DK		 8609 return -EBUSY;
8610#else
8611 /*
8612 * Failed to complete the transaction in a "good way"
8613 * Force both transactions with CLR bit
8614 */
3b603066 8615 struct bnx2x_func_state_params func_params = {NULL};
6debea87 8616
51c1a580
MS		 8617 DP(NETIF_MSG_IFDOWN,
8618 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
6debea87
DK		 8619
8620 func_params.f_obj = &bp->func_obj;
8621 __set_bit(RAMROD_DRV_CLR_ONLY,
8622 &func_params.ramrod_flags);
8623
8624 /* STARTED-->TX_ST0PPED */
8625 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8626 bnx2x_func_state_change(bp, &func_params);
8627
8628 /* TX_ST0PPED-->STARTED */
8629 func_params.cmd = BNX2X_F_CMD_TX_START;
8630 return bnx2x_func_state_change(bp, &func_params);
8631#endif
8632 }
8633
8634 return 0;
8635}
8636
5d07d868 8637void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
619c5cb6
VZ		 8638{
8639 int port = BP_PORT(bp);
6383c0b3
AE		 8640 int i, rc = 0;
8641 u8 cos;
3b603066 8642 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6
VZ		 8643 u32 reset_code;
8644
8645 /* Wait until tx fastpath tasks complete */
8646 for_each_tx_queue(bp, i) {
8647 struct bnx2x_fastpath *fp = &bp->fp[i];
8648
6383c0b3 8649 for_each_cos_in_tx_queue(fp, cos)
65565884 8650 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
619c5cb6
VZ		 8651#ifdef BNX2X_STOP_ON_ERROR
8652 if (rc)
8653 return;
8654#endif
8655 }
8656
8657 /* Give HW time to discard old tx messages */
8658 usleep_range(1000, 1000);
8659
8660 /* Clean all ETH MACs */
15192a8c
BW		 8661 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8662 false);
619c5cb6
VZ		 8663 if (rc < 0)
8664 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8665
8666 /* Clean up UC list */
15192a8c 8667 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
619c5cb6
VZ		 8668 true);
8669 if (rc < 0)
51c1a580
MS		 8670 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8671 rc);
619c5cb6
VZ		 8672
8673 /* Disable LLH */
8674 if (!CHIP_IS_E1(bp))
8675 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8676
8677 /* Set "drop all" (stop Rx).
8678 * We need to take a netif_addr_lock() here in order to prevent
8679 * a race between the completion code and this code.
8680 */
8681 netif_addr_lock_bh(bp->dev);
8682 /* Schedule the rx_mode command */
8683 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8684 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8685 else
8686 bnx2x_set_storm_rx_mode(bp);
8687
8688 /* Cleanup multicast configuration */
8689 rparam.mcast_obj = &bp->mcast_obj;
8690 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8691 if (rc < 0)
8692 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8693
8694 netif_addr_unlock_bh(bp->dev);
8695
8696
6debea87
DK		 8697
8698 /*
8699 * Send the UNLOAD_REQUEST to the MCP. This will return if
8700 * this function should perform FUNC, PORT or COMMON HW
8701 * reset.
8702 */
8703 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8704
8705 /*
8706 * (assumption: No Attention from MCP at this stage)
8707 * PMF probably in the middle of TXdisable/enable transaction
8708 */
8709 rc = bnx2x_func_wait_started(bp);
8710 if (rc) {
8711 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8712#ifdef BNX2X_STOP_ON_ERROR
8713 return;
8714#endif
8715 }
8716
34f80b04 8717 /* Close multi and leading connections
619c5cb6
VZ		 8718 * Completions for ramrods are collected in a synchronous way
8719 */
55c11941 8720 for_each_eth_queue(bp, i)
619c5cb6 8721 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 8722#ifdef BNX2X_STOP_ON_ERROR
8723 return;
8724#else
228241eb 8725 goto unload_error;
523224a3 8726#endif
55c11941
MS		 8727
8728 if (CNIC_LOADED(bp)) {
8729 for_each_cnic_queue(bp, i)
8730 if (bnx2x_stop_queue(bp, i))
8731#ifdef BNX2X_STOP_ON_ERROR
8732 return;
8733#else
8734 goto unload_error;
8735#endif
8736 }
8737
619c5cb6
VZ		 8738 /* If SP settings didn't get completed so far - something
8739 * very wrong has happen.
8740 */
8741 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8742 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 8743
619c5cb6
VZ		 8744#ifndef BNX2X_STOP_ON_ERROR
8745unload_error:
8746#endif
523224a3 8747 rc = bnx2x_func_stop(bp);
da5a662a 8748 if (rc) {
523224a3 8749 BNX2X_ERR("Function stop failed!\n");
da5a662a 8750#ifdef BNX2X_STOP_ON_ERROR
523224a3 8751 return;
523224a3 8752#endif
34f80b04 8753 }
a2fbb9ea 8754
523224a3
DK		 8755 /* Disable HW interrupts, NAPI */
8756 bnx2x_netif_stop(bp, 1);
26614ba5
MS		 8757 /* Delete all NAPI objects */
8758 bnx2x_del_all_napi(bp);
55c11941
MS		 8759 if (CNIC_LOADED(bp))
8760 bnx2x_del_all_napi_cnic(bp);
523224a3
DK		 8761
8762 /* Release IRQs */
d6214d7a 8763 bnx2x_free_irq(bp);
523224a3 8764
a2fbb9ea 8765 /* Reset the chip */
619c5cb6
VZ		 8766 rc = bnx2x_reset_hw(bp, reset_code);
8767 if (rc)
8768 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 8769
356e2385 8770
619c5cb6 8771 /* Report UNLOAD_DONE to MCP */
5d07d868 8772 bnx2x_send_unload_done(bp, keep_link);
72fd0718
VZ		 8773}
8774
9f6c9258 8775void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 8776{
8777 u32 val;
8778
51c1a580 8779 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
72fd0718
VZ		 8780
8781 if (CHIP_IS_E1(bp)) {
8782 int port = BP_PORT(bp);
8783 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8784 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8785
8786 val = REG_RD(bp, addr);
8787 val &= ~(0x300);
8788 REG_WR(bp, addr, val);
619c5cb6 8789 } else {
72fd0718
VZ		 8790 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8791 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8792 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8793 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8794 }
8795}
8796
72fd0718
VZ		 8797/* Close gates #2, #3 and #4: */
8798static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8799{
c9ee9206 8800 u32 val;
72fd0718
VZ		 8801
8802 /* Gates #2 and #4a are closed/opened for "not E1" only */
8803 if (!CHIP_IS_E1(bp)) {
8804 /* #4 */
c9ee9206 8805 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 8806 /* #2 */
c9ee9206 8807 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 8808 }
8809
8810 /* #3 */
c9ee9206
VZ		 8811 if (CHIP_IS_E1x(bp)) {
8812 /* Prevent interrupts from HC on both ports */
8813 val = REG_RD(bp, HC_REG_CONFIG_1);
8814 REG_WR(bp, HC_REG_CONFIG_1,
8815 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8816 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8817
8818 val = REG_RD(bp, HC_REG_CONFIG_0);
8819 REG_WR(bp, HC_REG_CONFIG_0,
8820 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8821 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8822 } else {
8823 /* Prevent incomming interrupts in IGU */
8824 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8825
8826 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8827 (!close) ?
8828 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8829 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8830 }
72fd0718 8831
51c1a580 8832 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
72fd0718
VZ		 8833 close ? "closing" : "opening");
8834 mmiowb();
8835}
8836
8837#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8838
8839static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8840{
8841 /* Do some magic... */
8842 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8843 *magic_val = val & SHARED_MF_CLP_MAGIC;
8844 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8845}
8846
e8920674
DK		 8847/**
8848 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 8849 *
e8920674
DK		 8850 * @bp: driver handle
8851 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 8852 */
8853static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8854{
8855 /* Restore the `magic' bit value... */
72fd0718
VZ		 8856 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8857 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8858 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8859}
8860
f85582f8 8861/**
e8920674 8862 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 8863 *
e8920674
DK		 8864 * @bp: driver handle
8865 * @magic_val: old value of 'magic' bit.
8866 *
8867 * Takes care of CLP configurations.
72fd0718
VZ		 8868 */
8869static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8870{
8871 u32 shmem;
8872 u32 validity_offset;
8873
51c1a580 8874 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
72fd0718
VZ		 8875
8876 /* Set `magic' bit in order to save MF config */
8877 if (!CHIP_IS_E1(bp))
8878 bnx2x_clp_reset_prep(bp, magic_val);
8879
8880 /* Get shmem offset */
8881 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
c55e771b
BW		 8882 validity_offset =
8883 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
72fd0718
VZ		 8884
8885 /* Clear validity map flags */
8886 if (shmem > 0)
8887 REG_WR(bp, shmem + validity_offset, 0);
8888}
8889
8890#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8891#define MCP_ONE_TIMEOUT 100 /* 100 ms */
8892
e8920674
DK		 8893/**
8894 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 8895 *
e8920674 8896 * @bp: driver handle
72fd0718 8897 */
1191cb83 8898static void bnx2x_mcp_wait_one(struct bnx2x *bp)
72fd0718
VZ		 8899{
8900 /* special handling for emulation and FPGA,
8901 wait 10 times longer */
8902 if (CHIP_REV_IS_SLOW(bp))
8903 msleep(MCP_ONE_TIMEOUT*10);
8904 else
8905 msleep(MCP_ONE_TIMEOUT);
8906}
8907
1b6e2ceb
DK		 8908/*
8909 * initializes bp->common.shmem_base and waits for validity signature to appear
8910 */
8911static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 8912{
1b6e2ceb
DK		 8913 int cnt = 0;
8914 u32 val = 0;
72fd0718 8915
1b6e2ceb
DK		 8916 do {
8917 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8918 if (bp->common.shmem_base) {
8919 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8920 if (val & SHR_MEM_VALIDITY_MB)
8921 return 0;
8922 }
72fd0718 8923
1b6e2ceb 8924 bnx2x_mcp_wait_one(bp);
72fd0718 8925
1b6e2ceb 8926 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 8927
1b6e2ceb 8928 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 8929
1b6e2ceb
DK		 8930 return -ENODEV;
8931}
72fd0718 8932
1b6e2ceb
DK		 8933static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8934{
8935 int rc = bnx2x_init_shmem(bp);
72fd0718 8936
72fd0718
VZ		 8937 /* Restore the `magic' bit value */
8938 if (!CHIP_IS_E1(bp))
8939 bnx2x_clp_reset_done(bp, magic_val);
8940
8941 return rc;
8942}
8943
8944static void bnx2x_pxp_prep(struct bnx2x *bp)
8945{
8946 if (!CHIP_IS_E1(bp)) {
8947 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8948 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 8949 mmiowb();
8950 }
8951}
8952
8953/*
8954 * Reset the whole chip except for:
8955 * - PCIE core
8956 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8957 * one reset bit)
8958 * - IGU
8959 * - MISC (including AEU)
8960 * - GRC
8961 * - RBCN, RBCP
8962 */
c9ee9206 8963static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 8964{
8965 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 8966 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 8967
8968 /*
8969 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8970 * (per chip) blocks.
8971 */
8972 global_bits2 =
8973 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8974 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 8975
c55e771b
BW		 8976 /* Don't reset the following blocks.
8977 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
8978 * reset, as in 4 port device they might still be owned
8979 * by the MCP (there is only one leader per path).
8980 */
72fd0718
VZ		 8981 not_reset_mask1 =
8982 MISC_REGISTERS_RESET_REG_1_RST_HC |
8983 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8984 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8985
8986 not_reset_mask2 =
c9ee9206 8987 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 8988 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8989 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8990 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8991 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8992 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8993 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 8994 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8995 MISC_REGISTERS_RESET_REG_2_RST_ATC |
c55e771b
BW		 8996 MISC_REGISTERS_RESET_REG_2_PGLC |
8997 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8998 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8999 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9000 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9001 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9002 MISC_REGISTERS_RESET_REG_2_UMAC1;
72fd0718 9003
8736c826
VZ		 9004 /*
9005 * Keep the following blocks in reset:
9006 * - all xxMACs are handled by the bnx2x_link code.
9007 */
9008 stay_reset2 =
8736c826
VZ		 9009 MISC_REGISTERS_RESET_REG_2_XMAC |
9010 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9011
9012 /* Full reset masks according to the chip */
72fd0718
VZ		 9013 reset_mask1 = 0xffffffff;
9014
9015 if (CHIP_IS_E1(bp))
9016 reset_mask2 = 0xffff;
8736c826 9017 else if (CHIP_IS_E1H(bp))
72fd0718 9018 reset_mask2 = 0x1ffff;
8736c826
VZ		 9019 else if (CHIP_IS_E2(bp))
9020 reset_mask2 = 0xfffff;
9021 else /* CHIP_IS_E3 */
9022 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 9023
9024 /* Don't reset global blocks unless we need to */
9025 if (!global)
9026 reset_mask2 &= ~global_bits2;
9027
9028 /*
9029 * In case of attention in the QM, we need to reset PXP
9030 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9031 * because otherwise QM reset would release 'close the gates' shortly
9032 * before resetting the PXP, then the PSWRQ would send a write
9033 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9034 * read the payload data from PSWWR, but PSWWR would not
9035 * respond. The write queue in PGLUE would stuck, dmae commands
9036 * would not return. Therefore it's important to reset the second
9037 * reset register (containing the
9038 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9039 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9040 * bit).
9041 */
72fd0718
VZ		 9042 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9043 reset_mask2 & (~not_reset_mask2));
9044
c9ee9206
VZ		 9045 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9046 reset_mask1 & (~not_reset_mask1));
9047
72fd0718
VZ		 9048 barrier();
9049 mmiowb();
9050
8736c826
VZ		 9051 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9052 reset_mask2 & (~stay_reset2));
9053
9054 barrier();
9055 mmiowb();
9056
c9ee9206 9057 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 9058 mmiowb();
9059}
9060
c9ee9206
VZ		 9061/**
9062 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9063 * It should get cleared in no more than 1s.
9064 *
9065 * @bp: driver handle
9066 *
9067 * It should get cleared in no more than 1s. Returns 0 if
9068 * pending writes bit gets cleared.
9069 */
9070static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9071{
9072 u32 cnt = 1000;
9073 u32 pend_bits = 0;
9074
9075 do {
9076 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9077
9078 if (pend_bits == 0)
9079 break;
9080
9081 usleep_range(1000, 1000);
9082 } while (cnt-- > 0);
9083
9084 if (cnt <= 0) {
9085 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9086 pend_bits);
9087 return -EBUSY;
9088 }
9089
9090 return 0;
9091}
9092
9093static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 9094{
9095 int cnt = 1000;
9096 u32 val = 0;
9097 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
c55e771b 9098 u32 tags_63_32 = 0;
72fd0718
VZ		 9099
9100
9101 /* Empty the Tetris buffer, wait for 1s */
9102 do {
9103 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9104 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9105 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9106 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9107 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
c55e771b
BW		 9108 if (CHIP_IS_E3(bp))
9109 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9110
72fd0718
VZ		 9111 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9112 ((port_is_idle_0 & 0x1) == 0x1) &&
9113 ((port_is_idle_1 & 0x1) == 0x1) &&
c55e771b
BW		 9114 (pgl_exp_rom2 == 0xffffffff) &&
9115 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
72fd0718 9116 break;
c9ee9206 9117 usleep_range(1000, 1000);
72fd0718
VZ		 9118 } while (cnt-- > 0);
9119
9120 if (cnt <= 0) {
51c1a580
MS		 9121 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9122 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
72fd0718
VZ		 9123 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9124 pgl_exp_rom2);
9125 return -EAGAIN;
9126 }
9127
9128 barrier();
9129
9130 /* Close gates #2, #3 and #4 */
9131 bnx2x_set_234_gates(bp, true);
9132
c9ee9206
VZ		 9133 /* Poll for IGU VQs for 57712 and newer chips */
9134 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9135 return -EAGAIN;
9136
9137
72fd0718
VZ		 9138 /* TBD: Indicate that "process kill" is in progress to MCP */
9139
9140 /* Clear "unprepared" bit */
9141 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9142 barrier();
9143
9144 /* Make sure all is written to the chip before the reset */
9145 mmiowb();
9146
9147 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9148 * PSWHST, GRC and PSWRD Tetris buffer.
9149 */
c9ee9206 9150 usleep_range(1000, 1000);
72fd0718
VZ		 9151
9152 /* Prepare to chip reset: */
9153 /* MCP */
c9ee9206
VZ		 9154 if (global)
9155 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 9156
9157 /* PXP */
9158 bnx2x_pxp_prep(bp);
9159 barrier();
9160
9161 /* reset the chip */
c9ee9206 9162 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 9163 barrier();
9164
9165 /* Recover after reset: */
9166 /* MCP */
c9ee9206 9167 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 9168 return -EAGAIN;
9169
c9ee9206
VZ		 9170 /* TBD: Add resetting the NO_MCP mode DB here */
9171
72fd0718
VZ		 9172 /* Open the gates #2, #3 and #4 */
9173 bnx2x_set_234_gates(bp, false);
9174
9175 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9176 * reset state, re-enable attentions. */
9177
a2fbb9ea
ET		 9178 return 0;
9179}
9180
910cc727 9181static int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 9182{
9183 int rc = 0;
c9ee9206 9184 bool global = bnx2x_reset_is_global(bp);
95c6c616
AE		 9185 u32 load_code;
9186
9187 /* if not going to reset MCP - load "fake" driver to reset HW while
9188 * driver is owner of the HW
9189 */
9190 if (!global && !BP_NOMCP(bp)) {
5d07d868
YM		 9191 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9192 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
95c6c616
AE		 9193 if (!load_code) {
9194 BNX2X_ERR("MCP response failure, aborting\n");
9195 rc = -EAGAIN;
9196 goto exit_leader_reset;
9197 }
9198 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9199 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9200 BNX2X_ERR("MCP unexpected resp, aborting\n");
9201 rc = -EAGAIN;
9202 goto exit_leader_reset2;
9203 }
9204 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9205 if (!load_code) {
9206 BNX2X_ERR("MCP response failure, aborting\n");
9207 rc = -EAGAIN;
9208 goto exit_leader_reset2;
9209 }
9210 }
c9ee9206 9211
72fd0718 9212 /* Try to recover after the failure */
c9ee9206 9213 if (bnx2x_process_kill(bp, global)) {
51c1a580
MS		 9214 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9215 BP_PATH(bp));
72fd0718 9216 rc = -EAGAIN;
95c6c616 9217 goto exit_leader_reset2;
72fd0718
VZ		 9218 }
9219
c9ee9206
VZ		 9220 /*
9221 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9222 * state.
9223 */
72fd0718 9224 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 9225 if (global)
9226 bnx2x_clear_reset_global(bp);
72fd0718 9227
95c6c616
AE		 9228exit_leader_reset2:
9229 /* unload "fake driver" if it was loaded */
9230 if (!global && !BP_NOMCP(bp)) {
9231 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9232 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9233 }
72fd0718
VZ		 9234exit_leader_reset:
9235 bp->is_leader = 0;
c9ee9206
VZ		 9236 bnx2x_release_leader_lock(bp);
9237 smp_mb();
72fd0718
VZ		 9238 return rc;
9239}
9240
1191cb83 9241static void bnx2x_recovery_failed(struct bnx2x *bp)
c9ee9206
VZ		 9242{
9243 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9244
9245 /* Disconnect this device */
9246 netif_device_detach(bp->dev);
9247
9248 /*
9249 * Block ifup for all function on this engine until "process kill"
9250 * or power cycle.
9251 */
9252 bnx2x_set_reset_in_progress(bp);
9253
9254 /* Shut down the power */
9255 bnx2x_set_power_state(bp, PCI_D3hot);
9256
9257 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9258
9259 smp_mb();
9260}
9261
9262/*
9263 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 9264 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 9265 * will never be called when netif_running(bp->dev) is false.
9266 */
9267static void bnx2x_parity_recover(struct bnx2x *bp)
9268{
c9ee9206 9269 bool global = false;
7a752993 9270 u32 error_recovered, error_unrecovered;
95c6c616 9271 bool is_parity;
c9ee9206 9272
72fd0718
VZ		 9273 DP(NETIF_MSG_HW, "Handling parity\n");
9274 while (1) {
9275 switch (bp->recovery_state) {
9276 case BNX2X_RECOVERY_INIT:
9277 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
95c6c616
AE		 9278 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9279 WARN_ON(!is_parity);
c9ee9206 9280
72fd0718 9281 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 9282 if (bnx2x_trylock_leader_lock(bp)) {
9283 bnx2x_set_reset_in_progress(bp);
9284 /*
9285 * Check if there is a global attention and if
9286 * there was a global attention, set the global
9287 * reset bit.
9288 */
9289
9290 if (global)
9291 bnx2x_set_reset_global(bp);
9292
72fd0718 9293 bp->is_leader = 1;
c9ee9206 9294 }
72fd0718
VZ		 9295
9296 /* Stop the driver */
9297 /* If interface has been removed - break */
5d07d868 9298 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
72fd0718
VZ		 9299 return;
9300
9301 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206 9302
c9ee9206
VZ		 9303 /* Ensure "is_leader", MCP command sequence and
9304 * "recovery_state" update values are seen on other
9305 * CPUs.
72fd0718 9306 */
c9ee9206 9307 smp_mb();
72fd0718
VZ		 9308 break;
9309
9310 case BNX2X_RECOVERY_WAIT:
9311 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9312 if (bp->is_leader) {
c9ee9206 9313 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3
AE		 9314 bool other_load_status =
9315 bnx2x_get_load_status(bp, other_engine);
9316 bool load_status =
9317 bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 9318 global = bnx2x_reset_is_global(bp);
9319
9320 /*
9321 * In case of a parity in a global block, let
9322 * the first leader that performs a
9323 * leader_reset() reset the global blocks in
9324 * order to clear global attentions. Otherwise
9325 * the the gates will remain closed for that
9326 * engine.
9327 */
889b9af3
AE		 9328 if (load_status ||
9329 (global && other_load_status)) {
72fd0718
VZ		 9330 /* Wait until all other functions get
9331 * down.
9332 */
7be08a72 9333 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9334 HZ/10);
9335 return;
9336 } else {
9337 /* If all other functions got down -
9338 * try to bring the chip back to
9339 * normal. In any case it's an exit
9340 * point for a leader.
9341 */
c9ee9206
VZ		 9342 if (bnx2x_leader_reset(bp)) {
9343 bnx2x_recovery_failed(bp);
72fd0718
VZ		 9344 return;
9345 }
9346
c9ee9206
VZ		 9347 /* If we are here, means that the
9348 * leader has succeeded and doesn't
9349 * want to be a leader any more. Try
9350 * to continue as a none-leader.
9351 */
9352 break;
72fd0718
VZ		 9353 }
9354 } else { /* non-leader */
c9ee9206 9355 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 9356 /* Try to get a LEADER_LOCK HW lock as
9357 * long as a former leader may have
9358 * been unloaded by the user or
9359 * released a leadership by another
9360 * reason.
9361 */
c9ee9206 9362 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 9363 /* I'm a leader now! Restart a
9364 * switch case.
9365 */
9366 bp->is_leader = 1;
9367 break;
9368 }
9369
7be08a72 9370 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9371 HZ/10);
9372 return;
9373
c9ee9206
VZ		 9374 } else {
9375 /*
9376 * If there was a global attention, wait
9377 * for it to be cleared.
9378 */
9379 if (bnx2x_reset_is_global(bp)) {
9380 schedule_delayed_work(
7be08a72
AE		 9381 &bp->sp_rtnl_task,
9382 HZ/10);
c9ee9206
VZ		 9383 return;
9384 }
9385
7a752993
AE		 9386 error_recovered =
9387 bp->eth_stats.recoverable_error;
9388 error_unrecovered =
9389 bp->eth_stats.unrecoverable_error;
95c6c616
AE		 9390 bp->recovery_state =
9391 BNX2X_RECOVERY_NIC_LOADING;
9392 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
7a752993 9393 error_unrecovered++;
95c6c616 9394 netdev_err(bp->dev,
51c1a580 9395 "Recovery failed. Power cycle needed\n");
95c6c616
AE		 9396 /* Disconnect this device */
9397 netif_device_detach(bp->dev);
9398 /* Shut down the power */
9399 bnx2x_set_power_state(
9400 bp, PCI_D3hot);
9401 smp_mb();
9402 } else {
c9ee9206
VZ		 9403 bp->recovery_state =
9404 BNX2X_RECOVERY_DONE;
7a752993 9405 error_recovered++;
c9ee9206
VZ		 9406 smp_mb();
9407 }
7a752993
AE		 9408 bp->eth_stats.recoverable_error =
9409 error_recovered;
9410 bp->eth_stats.unrecoverable_error =
9411 error_unrecovered;
c9ee9206 9412
72fd0718
VZ		 9413 return;
9414 }
9415 }
9416 default:
9417 return;
9418 }
9419 }
9420}
9421
56ad3152
MS		 9422static int bnx2x_close(struct net_device *dev);
9423
72fd0718
VZ		 9424/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9425 * scheduled on a general queue in order to prevent a dead lock.
9426 */
7be08a72 9427static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 9428{
7be08a72 9429 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 9430
9431 rtnl_lock();
9432
9433 if (!netif_running(bp->dev))
7be08a72
AE		 9434 goto sp_rtnl_exit;
9435
9436 /* if stop on error is defined no recovery flows should be executed */
9437#ifdef BNX2X_STOP_ON_ERROR
51c1a580 9438 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
7be08a72 9439 "you will need to reboot when done\n");
b1fb8740 9440 goto sp_rtnl_not_reset;
7be08a72 9441#endif
34f80b04 9442
7be08a72
AE		 9443 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9444 /*
b1fb8740
VZ		 9445 * Clear all pending SP commands as we are going to reset the
9446 * function anyway.
7be08a72 9447 */
b1fb8740
VZ		 9448 bp->sp_rtnl_state = 0;
9449 smp_mb();
9450
72fd0718 9451 bnx2x_parity_recover(bp);
b1fb8740
VZ		 9452
9453 goto sp_rtnl_exit;
9454 }
9455
9456 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9457 /*
9458 * Clear all pending SP commands as we are going to reset the
9459 * function anyway.
9460 */
9461 bp->sp_rtnl_state = 0;
9462 smp_mb();
9463
5d07d868 9464 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
72fd0718 9465 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740
VZ		 9466
9467 goto sp_rtnl_exit;
72fd0718 9468 }
b1fb8740
VZ		 9469#ifdef BNX2X_STOP_ON_ERROR
9470sp_rtnl_not_reset:
9471#endif
9472 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9473 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
a3348722
BW		 9474 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9475 bnx2x_after_function_update(bp);
8304859a
AE		 9476 /*
9477 * in case of fan failure we need to reset id if the "stop on error"
9478 * debug flag is set, since we trying to prevent permanent overheating
9479 * damage
9480 */
9481 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
51c1a580 9482 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
8304859a
AE		 9483 netif_device_detach(bp->dev);
9484 bnx2x_close(bp->dev);
9485 }
9486
381ac16b
AE		 9487 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9488 DP(BNX2X_MSG_SP,
9489 "sending set mcast vf pf channel message from rtnl sp-task\n");
9490 bnx2x_vfpf_set_mcast(bp->dev);
9491 }
9492
9493 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
9494 &bp->sp_rtnl_state)) {
9495 DP(BNX2X_MSG_SP,
9496 "sending set storm rx mode vf pf channel message from rtnl sp-task\n");
9497 bnx2x_vfpf_storm_rx_mode(bp);
9498 }
9499
7be08a72 9500sp_rtnl_exit:
34f80b04
EG		 9501 rtnl_unlock();
9502}
9503
a2fbb9ea
ET		 9504/* end of nic load/unload */
9505
3deb8167
YR		 9506static void bnx2x_period_task(struct work_struct *work)
9507{
9508 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9509
9510 if (!netif_running(bp->dev))
9511 goto period_task_exit;
9512
9513 if (CHIP_REV_IS_SLOW(bp)) {
9514 BNX2X_ERR("period task called on emulation, ignoring\n");
9515 goto period_task_exit;
9516 }
9517
9518 bnx2x_acquire_phy_lock(bp);
9519 /*
9520 * The barrier is needed to ensure the ordering between the writing to
9521 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9522 * the reading here.
9523 */
9524 smp_mb();
9525 if (bp->port.pmf) {
9526 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9527
9528 /* Re-queue task in 1 sec */
9529 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9530 }
9531
9532 bnx2x_release_phy_lock(bp);
9533period_task_exit:
9534 return;
9535}
9536
a2fbb9ea
ET		 9537/*
9538 * Init service functions
9539 */
9540
b56e9670 9541u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 9542{
9543 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9544 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9545 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 9546}
9547
f2e0899f 9548static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
f1ef27ef 9549{
f2e0899f 9550 u32 reg = bnx2x_get_pretend_reg(bp);
f1ef27ef
EG		 9551
9552 /* Flush all outstanding writes */
9553 mmiowb();
9554
9555 /* Pretend to be function 0 */
9556 REG_WR(bp, reg, 0);
f2e0899f 9557 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
f1ef27ef
EG		 9558
9559 /* From now we are in the "like-E1" mode */
9560 bnx2x_int_disable(bp);
9561
9562 /* Flush all outstanding writes */
9563 mmiowb();
9564
f2e0899f
DK		 9565 /* Restore the original function */
9566 REG_WR(bp, reg, BP_ABS_FUNC(bp));
9567 REG_RD(bp, reg);
f1ef27ef
EG		 9568}
9569
f2e0899f 9570static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
f1ef27ef 9571{
f2e0899f 9572 if (CHIP_IS_E1(bp))
f1ef27ef 9573 bnx2x_int_disable(bp);
f2e0899f
DK		 9574 else
9575 bnx2x_undi_int_disable_e1h(bp);
f1ef27ef
EG		 9576}
9577
0329aba1 9578static void bnx2x_prev_unload_close_mac(struct bnx2x *bp)
34f80b04 9579{
452427b0
YM		 9580 u32 val, base_addr, offset, mask, reset_reg;
9581 bool mac_stopped = false;
9582 u8 port = BP_PORT(bp);
34f80b04 9583
452427b0 9584 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
f16da43b 9585
452427b0
YM		 9586 if (!CHIP_IS_E3(bp)) {
9587 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9588 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9589 if ((mask & reset_reg) && val) {
9590 u32 wb_data[2];
9591 BNX2X_DEV_INFO("Disable bmac Rx\n");
9592 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9593 : NIG_REG_INGRESS_BMAC0_MEM;
9594 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9595 : BIGMAC_REGISTER_BMAC_CONTROL;
7a06a122 9596
452427b0
YM		 9597 /*
9598 * use rd/wr since we cannot use dmae. This is safe
9599 * since MCP won't access the bus due to the request
9600 * to unload, and no function on the path can be
9601 * loaded at this time.
9602 */
9603 wb_data[0] = REG_RD(bp, base_addr + offset);
9604 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9605 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9606 REG_WR(bp, base_addr + offset, wb_data[0]);
9607 REG_WR(bp, base_addr + offset + 0x4, wb_data[1]);
9608
9609 }
9610 BNX2X_DEV_INFO("Disable emac Rx\n");
9611 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0);
9612
9613 mac_stopped = true;
9614 } else {
9615 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9616 BNX2X_DEV_INFO("Disable xmac Rx\n");
9617 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9618 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9619 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9620 val & ~(1 << 1));
9621 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9622 val | (1 << 1));
9623 REG_WR(bp, base_addr + XMAC_REG_CTRL, 0);
9624 mac_stopped = true;
9625 }
9626 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9627 if (mask & reset_reg) {
9628 BNX2X_DEV_INFO("Disable umac Rx\n");
9629 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9630 REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0);
9631 mac_stopped = true;
9632 }
9633 }
9634
9635 if (mac_stopped)
9636 msleep(20);
9637
9638}
9639
9640#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9641#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9642#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9643#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9644
1dd06ae8 9645static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
452427b0
YM		 9646{
9647 u16 rcq, bd;
9648 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9649
9650 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9651 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9652
9653 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9654 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9655
9656 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9657 port, bd, rcq);
9658}
9659
0329aba1 9660static int bnx2x_prev_mcp_done(struct bnx2x *bp)
452427b0 9661{
5d07d868
YM		 9662 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9663 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
452427b0
YM		 9664 if (!rc) {
9665 BNX2X_ERR("MCP response failure, aborting\n");
9666 return -EBUSY;
9667 }
9668
9669 return 0;
9670}
9671
c63da990
BW		 9672static struct bnx2x_prev_path_list *
9673 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9674{
9675 struct bnx2x_prev_path_list *tmp_list;
9676
9677 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9678 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9679 bp->pdev->bus->number == tmp_list->bus &&
9680 BP_PATH(bp) == tmp_list->path)
9681 return tmp_list;
9682
9683 return NULL;
9684}
9685
0329aba1 9686static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
452427b0
YM		 9687{
9688 struct bnx2x_prev_path_list *tmp_list;
9689 int rc = false;
9690
9691 if (down_trylock(&bnx2x_prev_sem))
9692 return false;
9693
9694 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9695 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9696 bp->pdev->bus->number == tmp_list->bus &&
9697 BP_PATH(bp) == tmp_list->path) {
9698 rc = true;
9699 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9700 BP_PATH(bp));
9701 break;
9702 }
9703 }
9704
9705 up(&bnx2x_prev_sem);
9706
9707 return rc;
9708}
9709
c63da990 9710static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
452427b0
YM		 9711{
9712 struct bnx2x_prev_path_list *tmp_list;
9713 int rc;
9714
ea4b3857 9715 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
452427b0
YM		 9716 if (!tmp_list) {
9717 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9718 return -ENOMEM;
9719 }
9720
9721 tmp_list->bus = bp->pdev->bus->number;
9722 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9723 tmp_list->path = BP_PATH(bp);
c63da990 9724 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
452427b0
YM		 9725
9726 rc = down_interruptible(&bnx2x_prev_sem);
9727 if (rc) {
9728 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9729 kfree(tmp_list);
9730 } else {
9731 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9732 BP_PATH(bp));
9733 list_add(&tmp_list->list, &bnx2x_prev_list);
9734 up(&bnx2x_prev_sem);
9735 }
9736
9737 return rc;
9738}
9739
0329aba1 9740static int bnx2x_do_flr(struct bnx2x *bp)
452427b0 9741{
2a80eebc 9742 int i;
452427b0
YM		 9743 u16 status;
9744 struct pci_dev *dev = bp->pdev;
9745
8eee694c
YM		 9746
9747 if (CHIP_IS_E1x(bp)) {
9748 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9749 return -EINVAL;
9750 }
9751
9752 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9753 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9754 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9755 bp->common.bc_ver);
9756 return -EINVAL;
9757 }
452427b0 9758
452427b0
YM		 9759 /* Wait for Transaction Pending bit clean */
9760 for (i = 0; i < 4; i++) {
9761 if (i)
9762 msleep((1 << (i - 1)) * 100);
9763
2a80eebc 9764 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
452427b0
YM		 9765 if (!(status & PCI_EXP_DEVSTA_TRPND))
9766 goto clear;
9767 }
9768
9769 dev_err(&dev->dev,
9770 "transaction is not cleared; proceeding with reset anyway\n");
9771
9772clear:
452427b0 9773
8eee694c 9774 BNX2X_DEV_INFO("Initiating FLR\n");
452427b0
YM		 9775 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9776
9777 return 0;
9778}
9779
0329aba1 9780static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
452427b0
YM		 9781{
9782 int rc;
9783
9784 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9785
9786 /* Test if previous unload process was already finished for this path */
9787 if (bnx2x_prev_is_path_marked(bp))
9788 return bnx2x_prev_mcp_done(bp);
9789
9790 /* If function has FLR capabilities, and existing FW version matches
9791 * the one required, then FLR will be sufficient to clean any residue
9792 * left by previous driver
9793 */
ad5afc89 9794 rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
8eee694c
YM		 9795
9796 if (!rc) {
9797 /* fw version is good */
9798 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9799 rc = bnx2x_do_flr(bp);
9800 }
9801
9802 if (!rc) {
9803 /* FLR was performed */
9804 BNX2X_DEV_INFO("FLR successful\n");
9805 return 0;
9806 }
9807
9808 BNX2X_DEV_INFO("Could not FLR\n");
452427b0
YM		 9809
9810 /* Close the MCP request, return failure*/
9811 rc = bnx2x_prev_mcp_done(bp);
9812 if (!rc)
9813 rc = BNX2X_PREV_WAIT_NEEDED;
9814
9815 return rc;
9816}
9817
0329aba1 9818static int bnx2x_prev_unload_common(struct bnx2x *bp)
452427b0
YM		 9819{
9820 u32 reset_reg, tmp_reg = 0, rc;
c63da990 9821 bool prev_undi = false;
452427b0
YM		 9822 /* It is possible a previous function received 'common' answer,
9823 * but hasn't loaded yet, therefore creating a scenario of
9824 * multiple functions receiving 'common' on the same path.
9825 */
9826 BNX2X_DEV_INFO("Common unload Flow\n");
9827
9828 if (bnx2x_prev_is_path_marked(bp))
9829 return bnx2x_prev_mcp_done(bp);
9830
9831 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9832
9833 /* Reset should be performed after BRB is emptied */
9834 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9835 u32 timer_count = 1000;
452427b0
YM		 9836
9837 /* Close the MAC Rx to prevent BRB from filling up */
9838 bnx2x_prev_unload_close_mac(bp);
9839
9840 /* Check if the UNDI driver was previously loaded
34f80b04
EG		 9841 * UNDI driver initializes CID offset for normal bell to 0x7
9842 */
452427b0
YM		 9843 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9844 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9845 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9846 if (tmp_reg == 0x7) {
9847 BNX2X_DEV_INFO("UNDI previously loaded\n");
9848 prev_undi = true;
9849 /* clear the UNDI indication */
9850 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
34f80b04 9851 }
452427b0
YM		 9852 }
9853 /* wait until BRB is empty */
9854 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9855 while (timer_count) {
9856 u32 prev_brb = tmp_reg;
34f80b04 9857
452427b0
YM		 9858 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9859 if (!tmp_reg)
9860 break;
619c5cb6 9861
452427b0 9862 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
619c5cb6 9863
452427b0
YM		 9864 /* reset timer as long as BRB actually gets emptied */
9865 if (prev_brb > tmp_reg)
9866 timer_count = 1000;
9867 else
9868 timer_count--;
da5a662a 9869
452427b0
YM		 9870 /* If UNDI resides in memory, manually increment it */
9871 if (prev_undi)
9872 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
da5a662a 9873
452427b0 9874 udelay(10);
7a06a122 9875 }
452427b0
YM		 9876
9877 if (!timer_count)
9878 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9879
34f80b04 9880 }
f16da43b 9881
452427b0
YM		 9882 /* No packets are in the pipeline, path is ready for reset */
9883 bnx2x_reset_common(bp);
9884
c63da990 9885 rc = bnx2x_prev_mark_path(bp, prev_undi);
452427b0
YM		 9886 if (rc) {
9887 bnx2x_prev_mcp_done(bp);
9888 return rc;
9889 }
9890
9891 return bnx2x_prev_mcp_done(bp);
9892}
9893
24f06716
AE		 9894/* previous driver DMAE transaction may have occurred when pre-boot stage ended
9895 * and boot began, or when kdump kernel was loaded. Either case would invalidate
9896 * the addresses of the transaction, resulting in was-error bit set in the pci
9897 * causing all hw-to-host pcie transactions to timeout. If this happened we want
9898 * to clear the interrupt which detected this from the pglueb and the was done
9899 * bit
9900 */
0329aba1 9901static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
24f06716 9902{
4a25417c
AE		 9903 if (!CHIP_IS_E1x(bp)) {
9904 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
9905 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9906 BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
9907 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9908 1 << BP_FUNC(bp));
9909 }
24f06716
AE		 9910 }
9911}
9912
0329aba1 9913static int bnx2x_prev_unload(struct bnx2x *bp)
452427b0
YM		 9914{
9915 int time_counter = 10;
9916 u32 rc, fw, hw_lock_reg, hw_lock_val;
c63da990 9917 struct bnx2x_prev_path_list *prev_list;
452427b0
YM		 9918 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9919
24f06716
AE		 9920 /* clear hw from errors which may have resulted from an interrupted
9921 * dmae transaction.
9922 */
9923 bnx2x_prev_interrupted_dmae(bp);
9924
9925 /* Release previously held locks */
452427b0
YM		 9926 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9927 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9928 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9929
9930 hw_lock_val = (REG_RD(bp, hw_lock_reg));
9931 if (hw_lock_val) {
9932 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9933 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9934 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9935 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9936 }
9937
9938 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9939 REG_WR(bp, hw_lock_reg, 0xffffffff);
9940 } else
9941 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9942
9943 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9944 BNX2X_DEV_INFO("Release previously held alr\n");
9945 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
9946 }
9947
9948
9949 do {
9950 /* Lock MCP using an unload request */
9951 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9952 if (!fw) {
9953 BNX2X_ERR("MCP response failure, aborting\n");
9954 rc = -EBUSY;
9955 break;
9956 }
9957
9958 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9959 rc = bnx2x_prev_unload_common(bp);
9960 break;
9961 }
9962
9963 /* non-common reply from MCP night require looping */
9964 rc = bnx2x_prev_unload_uncommon(bp);
9965 if (rc != BNX2X_PREV_WAIT_NEEDED)
9966 break;
9967
9968 msleep(20);
9969 } while (--time_counter);
9970
9971 if (!time_counter || rc) {
9972 BNX2X_ERR("Failed unloading previous driver, aborting\n");
9973 rc = -EBUSY;
9974 }
9975
c63da990
BW		 9976 /* Mark function if its port was used to boot from SAN */
9977 prev_list = bnx2x_prev_path_get_entry(bp);
9978 if (prev_list && (prev_list->undi & (1 << BP_PORT(bp))))
9979 bp->link_params.feature_config_flags |=
9980 FEATURE_CONFIG_BOOT_FROM_SAN;
9981
452427b0
YM		 9982 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
9983
9984 return rc;
34f80b04
EG		 9985}
9986
0329aba1 9987static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
34f80b04 9988{
1d187b34 9989 u32 val, val2, val3, val4, id, boot_mode;
72ce58c3 9990 u16 pmc;
34f80b04
EG		 9991
9992 /* Get the chip revision id and number. */
9993 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
9994 val = REG_RD(bp, MISC_REG_CHIP_NUM);
9995 id = ((val & 0xffff) << 16);
9996 val = REG_RD(bp, MISC_REG_CHIP_REV);
9997 id |= ((val & 0xf) << 12);
9998 val = REG_RD(bp, MISC_REG_CHIP_METAL);
9999 id |= ((val & 0xff) << 4);
5a40e08e 10000 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 10001 id |= (val & 0xf);
10002 bp->common.chip_id = id;
523224a3 10003
7e8e02df
BW		 10004 /* force 57811 according to MISC register */
10005 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10006 if (CHIP_IS_57810(bp))
10007 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10008 (bp->common.chip_id & 0x0000FFFF);
10009 else if (CHIP_IS_57810_MF(bp))
10010 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10011 (bp->common.chip_id & 0x0000FFFF);
10012 bp->common.chip_id |= 0x1;
10013 }
10014
523224a3
DK		 10015 /* Set doorbell size */
10016 bp->db_size = (1 << BNX2X_DB_SHIFT);
10017
619c5cb6 10018 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 10019 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10020 if ((val & 1) == 0)
10021 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10022 else
10023 val = (val >> 1) & 1;
10024 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10025 "2_PORT_MODE");
10026 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10027 CHIP_2_PORT_MODE;
10028
10029 if (CHIP_MODE_IS_4_PORT(bp))
10030 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10031 else
10032 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10033 } else {
10034 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10035 bp->pfid = bp->pf_num; /* 0..7 */
10036 }
10037
51c1a580
MS		 10038 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10039
f2e0899f
DK		 10040 bp->link_params.chip_id = bp->common.chip_id;
10041 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 10042
1c06328c
EG		 10043 val = (REG_RD(bp, 0x2874) & 0x55);
10044 if ((bp->common.chip_id & 0x1) ||
10045 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10046 bp->flags |= ONE_PORT_FLAG;
10047 BNX2X_DEV_INFO("single port device\n");
10048 }
10049
34f80b04 10050 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 10051 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 10052 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10053 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10054 bp->common.flash_size, bp->common.flash_size);
10055
1b6e2ceb
DK		 10056 bnx2x_init_shmem(bp);
10057
619c5cb6
VZ		 10058
10059
f2e0899f
DK		 10060 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10061 MISC_REG_GENERIC_CR_1 :
10062 MISC_REG_GENERIC_CR_0));
1b6e2ceb 10063
34f80b04 10064 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 10065 bp->link_params.shmem2_base = bp->common.shmem2_base;
b884d95b
YR		 10066 if (SHMEM2_RD(bp, size) >
10067 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10068 bp->link_params.lfa_base =
10069 REG_RD(bp, bp->common.shmem2_base +
10070 (u32)offsetof(struct shmem2_region,
10071 lfa_host_addr[BP_PORT(bp)]));
10072 else
10073 bp->link_params.lfa_base = 0;
2691d51d
EG		 10074 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10075 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 10076
f2e0899f 10077 if (!bp->common.shmem_base) {
34f80b04
EG		 10078 BNX2X_DEV_INFO("MCP not active\n");
10079 bp->flags |= NO_MCP_FLAG;
10080 return;
10081 }
10082
34f80b04 10083 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 10084 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 10085
10086 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10087 SHARED_HW_CFG_LED_MODE_MASK) >>
10088 SHARED_HW_CFG_LED_MODE_SHIFT);
10089
c2c8b03e
EG		 10090 bp->link_params.feature_config_flags = 0;
10091 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10092 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10093 bp->link_params.feature_config_flags |=
10094 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10095 else
10096 bp->link_params.feature_config_flags &=
10097 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10098
34f80b04
EG		 10099 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10100 bp->common.bc_ver = val;
10101 BNX2X_DEV_INFO("bc_ver %X\n", val);
10102 if (val < BNX2X_BC_VER) {
10103 /* for now only warn
10104 * later we might need to enforce this */
51c1a580
MS		 10105 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10106 BNX2X_BC_VER, val);
34f80b04 10107 }
4d295db0 10108 bp->link_params.feature_config_flags |=
a22f0788 10109 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 10110 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10111
a22f0788
YR		 10112 bp->link_params.feature_config_flags |=
10113 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10114 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
a3348722
BW		 10115 bp->link_params.feature_config_flags |=
10116 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10117 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
85242eea
YR		 10118 bp->link_params.feature_config_flags |=
10119 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10120 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
55386fe8
YR		 10121
10122 bp->link_params.feature_config_flags |=
10123 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10124 FEATURE_CONFIG_MT_SUPPORT : 0;
10125
0e898dd7
BW		 10126 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10127 BC_SUPPORTS_PFC_STATS : 0;
85242eea 10128
2e499d3c
BW		 10129 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10130 BC_SUPPORTS_FCOE_FEATURES : 0;
10131
9876879f
BW		 10132 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10133 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
1d187b34
BW		 10134 boot_mode = SHMEM_RD(bp,
10135 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10136 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10137 switch (boot_mode) {
10138 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10139 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10140 break;
10141 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10142 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10143 break;
10144 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10145 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10146 break;
10147 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10148 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10149 break;
10150 }
10151
f9a3ebbe
DK		 10152 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
10153 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10154
72ce58c3 10155 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 10156 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 10157
10158 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10159 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10160 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10161 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10162
cdaa7cb8
VZ		 10163 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10164 val, val2, val3, val4);
34f80b04
EG		 10165}
10166
f2e0899f
DK		 10167#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10168#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10169
0329aba1 10170static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
f2e0899f
DK		 10171{
10172 int pfid = BP_FUNC(bp);
f2e0899f
DK		 10173 int igu_sb_id;
10174 u32 val;
6383c0b3 10175 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 10176
10177 bp->igu_base_sb = 0xff;
f2e0899f 10178 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 10179 int vn = BP_VN(bp);
6383c0b3 10180 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 10181 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10182 FP_SB_MAX_E1x;
10183
10184 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10185 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10186
9b341bb1 10187 return 0;
f2e0899f
DK		 10188 }
10189
10190 /* IGU in normal mode - read CAM */
10191 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10192 igu_sb_id++) {
10193 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10194 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10195 continue;
10196 fid = IGU_FID(val);
10197 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10198 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10199 continue;
10200 if (IGU_VEC(val) == 0)
10201 /* default status block */
10202 bp->igu_dsb_id = igu_sb_id;
10203 else {
10204 if (bp->igu_base_sb == 0xff)
10205 bp->igu_base_sb = igu_sb_id;
6383c0b3 10206 igu_sb_cnt++;
f2e0899f
DK		 10207 }
10208 }
10209 }
619c5cb6 10210
6383c0b3 10211#ifdef CONFIG_PCI_MSI
185d4c8b
AE		 10212 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10213 * optional that number of CAM entries will not be equal to the value
10214 * advertised in PCI.
10215 * Driver should use the minimal value of both as the actual status
10216 * block count
619c5cb6 10217 */
185d4c8b 10218 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
6383c0b3 10219#endif
619c5cb6 10220
9b341bb1 10221 if (igu_sb_cnt == 0) {
f2e0899f 10222 BNX2X_ERR("CAM configuration error\n");
9b341bb1
BW		 10223 return -EINVAL;
10224 }
10225
10226 return 0;
f2e0899f
DK		 10227}
10228
1dd06ae8 10229static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
a2fbb9ea 10230{
a22f0788
YR		 10231 int cfg_size = 0, idx, port = BP_PORT(bp);
10232
10233 /* Aggregation of supported attributes of all external phys */
10234 bp->port.supported[0] = 0;
10235 bp->port.supported[1] = 0;
b7737c9b
YR		 10236 switch (bp->link_params.num_phys) {
10237 case 1:
a22f0788
YR		 10238 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10239 cfg_size = 1;
10240 break;
b7737c9b 10241 case 2:
a22f0788
YR		 10242 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10243 cfg_size = 1;
10244 break;
10245 case 3:
10246 if (bp->link_params.multi_phy_config &
10247 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10248 bp->port.supported[1] =
10249 bp->link_params.phy[EXT_PHY1].supported;
10250 bp->port.supported[0] =
10251 bp->link_params.phy[EXT_PHY2].supported;
10252 } else {
10253 bp->port.supported[0] =
10254 bp->link_params.phy[EXT_PHY1].supported;
10255 bp->port.supported[1] =
10256 bp->link_params.phy[EXT_PHY2].supported;
10257 }
10258 cfg_size = 2;
10259 break;
b7737c9b 10260 }
a2fbb9ea 10261
a22f0788 10262 if (!(bp->port.supported[0] || bp->port.supported[1])) {
51c1a580 10263 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 10264 SHMEM_RD(bp,
a22f0788
YR		 10265 dev_info.port_hw_config[port].external_phy_config),
10266 SHMEM_RD(bp,
10267 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 10268 return;
f85582f8 10269 }
a2fbb9ea 10270
619c5cb6
VZ		 10271 if (CHIP_IS_E3(bp))
10272 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10273 else {
10274 switch (switch_cfg) {
10275 case SWITCH_CFG_1G:
10276 bp->port.phy_addr = REG_RD(
10277 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10278 break;
10279 case SWITCH_CFG_10G:
10280 bp->port.phy_addr = REG_RD(
10281 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10282 break;
10283 default:
10284 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10285 bp->port.link_config[0]);
10286 return;
10287 }
a2fbb9ea 10288 }
619c5cb6 10289 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 10290 /* mask what we support according to speed_cap_mask per configuration */
10291 for (idx = 0; idx < cfg_size; idx++) {
10292 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10293 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 10294 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 10295
a22f0788 10296 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10297 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 10298 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 10299
a22f0788 10300 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10301 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 10302 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 10303
a22f0788 10304 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10305 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 10306 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 10307
a22f0788 10308 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10309 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 10310 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 10311 SUPPORTED_1000baseT_Full);
a2fbb9ea 10312
a22f0788 10313 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10314 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 10315 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 10316
a22f0788 10317 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10318 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788
YR		 10319 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10320
10321 }
a2fbb9ea 10322
a22f0788
YR		 10323 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10324 bp->port.supported[1]);
a2fbb9ea
ET		 10325}
10326
0329aba1 10327static void bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 10328{
a22f0788
YR		 10329 u32 link_config, idx, cfg_size = 0;
10330 bp->port.advertising[0] = 0;
10331 bp->port.advertising[1] = 0;
10332 switch (bp->link_params.num_phys) {
10333 case 1:
10334 case 2:
10335 cfg_size = 1;
10336 break;
10337 case 3:
10338 cfg_size = 2;
10339 break;
10340 }
10341 for (idx = 0; idx < cfg_size; idx++) {
10342 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10343 link_config = bp->port.link_config[idx];
10344 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 10345 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 10346 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10347 bp->link_params.req_line_speed[idx] =
10348 SPEED_AUTO_NEG;
10349 bp->port.advertising[idx] |=
10350 bp->port.supported[idx];
10bd1f24
MY		 10351 if (bp->link_params.phy[EXT_PHY1].type ==
10352 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10353 bp->port.advertising[idx] |=
10354 (SUPPORTED_100baseT_Half |
10355 SUPPORTED_100baseT_Full);
f85582f8
DK		 10356 } else {
10357 /* force 10G, no AN */
a22f0788
YR		 10358 bp->link_params.req_line_speed[idx] =
10359 SPEED_10000;
10360 bp->port.advertising[idx] |=
10361 (ADVERTISED_10000baseT_Full |
f85582f8 10362 ADVERTISED_FIBRE);
a22f0788 10363 continue;
f85582f8
DK		 10364 }
10365 break;
a2fbb9ea 10366
f85582f8 10367 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 10368 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10369 bp->link_params.req_line_speed[idx] =
10370 SPEED_10;
10371 bp->port.advertising[idx] |=
10372 (ADVERTISED_10baseT_Full |
f85582f8
DK		 10373 ADVERTISED_TP);
10374 } else {
51c1a580 10375 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8 10376 link_config,
a22f0788 10377 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 10378 return;
10379 }
10380 break;
a2fbb9ea 10381
f85582f8 10382 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 10383 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10384 bp->link_params.req_line_speed[idx] =
10385 SPEED_10;
10386 bp->link_params.req_duplex[idx] =
10387 DUPLEX_HALF;
10388 bp->port.advertising[idx] |=
10389 (ADVERTISED_10baseT_Half |
f85582f8
DK		 10390 ADVERTISED_TP);
10391 } else {
51c1a580 10392 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 10393 link_config,
10394 bp->link_params.speed_cap_mask[idx]);
10395 return;
10396 }
10397 break;
a2fbb9ea 10398
f85582f8
DK		 10399 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10400 if (bp->port.supported[idx] &
10401 SUPPORTED_100baseT_Full) {
a22f0788
YR		 10402 bp->link_params.req_line_speed[idx] =
10403 SPEED_100;
10404 bp->port.advertising[idx] |=
10405 (ADVERTISED_100baseT_Full |
f85582f8
DK		 10406 ADVERTISED_TP);
10407 } else {
51c1a580 10408 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 10409 link_config,
10410 bp->link_params.speed_cap_mask[idx]);
10411 return;
10412 }
10413 break;
a2fbb9ea 10414
f85582f8
DK		 10415 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10416 if (bp->port.supported[idx] &
10417 SUPPORTED_100baseT_Half) {
10418 bp->link_params.req_line_speed[idx] =
10419 SPEED_100;
10420 bp->link_params.req_duplex[idx] =
10421 DUPLEX_HALF;
a22f0788
YR		 10422 bp->port.advertising[idx] |=
10423 (ADVERTISED_100baseT_Half |
f85582f8
DK		 10424 ADVERTISED_TP);
10425 } else {
51c1a580 10426 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 10427 link_config,
10428 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 10429 return;
10430 }
10431 break;
a2fbb9ea 10432
f85582f8 10433 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 10434 if (bp->port.supported[idx] &
10435 SUPPORTED_1000baseT_Full) {
10436 bp->link_params.req_line_speed[idx] =
10437 SPEED_1000;
10438 bp->port.advertising[idx] |=
10439 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 10440 ADVERTISED_TP);
10441 } else {
51c1a580 10442 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 10443 link_config,
10444 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 10445 return;
10446 }
10447 break;
a2fbb9ea 10448
f85582f8 10449 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 10450 if (bp->port.supported[idx] &
10451 SUPPORTED_2500baseX_Full) {
10452 bp->link_params.req_line_speed[idx] =
10453 SPEED_2500;
10454 bp->port.advertising[idx] |=
10455 (ADVERTISED_2500baseX_Full |
34f80b04 10456 ADVERTISED_TP);
f85582f8 10457 } else {
51c1a580 10458 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 10459 link_config,
f85582f8
DK		 10460 bp->link_params.speed_cap_mask[idx]);
10461 return;
10462 }
10463 break;
a2fbb9ea 10464
f85582f8 10465 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 10466 if (bp->port.supported[idx] &
10467 SUPPORTED_10000baseT_Full) {
10468 bp->link_params.req_line_speed[idx] =
10469 SPEED_10000;
10470 bp->port.advertising[idx] |=
10471 (ADVERTISED_10000baseT_Full |
34f80b04 10472 ADVERTISED_FIBRE);
f85582f8 10473 } else {
51c1a580 10474 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 10475 link_config,
f85582f8
DK		 10476 bp->link_params.speed_cap_mask[idx]);
10477 return;
10478 }
10479 break;
3c9ada22
YR		 10480 case PORT_FEATURE_LINK_SPEED_20G:
10481 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 10482
3c9ada22 10483 break;
f85582f8 10484 default:
51c1a580 10485 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
754a2f52 10486 link_config);
f85582f8
DK		 10487 bp->link_params.req_line_speed[idx] =
10488 SPEED_AUTO_NEG;
10489 bp->port.advertising[idx] =
10490 bp->port.supported[idx];
10491 break;
10492 }
a2fbb9ea 10493
a22f0788 10494 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 10495 PORT_FEATURE_FLOW_CONTROL_MASK);
cd1dfce2
YM		 10496 if (bp->link_params.req_flow_ctrl[idx] ==
10497 BNX2X_FLOW_CTRL_AUTO) {
10498 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10499 bp->link_params.req_flow_ctrl[idx] =
10500 BNX2X_FLOW_CTRL_NONE;
10501 else
10502 bnx2x_set_requested_fc(bp);
a22f0788 10503 }
a2fbb9ea 10504
51c1a580 10505 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
a22f0788
YR		 10506 bp->link_params.req_line_speed[idx],
10507 bp->link_params.req_duplex[idx],
10508 bp->link_params.req_flow_ctrl[idx],
10509 bp->port.advertising[idx]);
10510 }
a2fbb9ea
ET		 10511}
10512
0329aba1 10513static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
e665bfda
MC		 10514{
10515 mac_hi = cpu_to_be16(mac_hi);
10516 mac_lo = cpu_to_be32(mac_lo);
10517 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
10518 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
10519}
10520
0329aba1 10521static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 10522{
34f80b04 10523 int port = BP_PORT(bp);
589abe3a 10524 u32 config;
c8c60d88 10525 u32 ext_phy_type, ext_phy_config, eee_mode;
a2fbb9ea 10526
c18487ee 10527 bp->link_params.bp = bp;
34f80b04 10528 bp->link_params.port = port;
c18487ee 10529
c18487ee 10530 bp->link_params.lane_config =
a2fbb9ea 10531 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 10532
a22f0788 10533 bp->link_params.speed_cap_mask[0] =
a2fbb9ea
ET		 10534 SHMEM_RD(bp,
10535 dev_info.port_hw_config[port].speed_capability_mask);
a22f0788
YR		 10536 bp->link_params.speed_cap_mask[1] =
10537 SHMEM_RD(bp,
10538 dev_info.port_hw_config[port].speed_capability_mask2);
10539 bp->port.link_config[0] =
a2fbb9ea
ET		 10540 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10541
a22f0788
YR		 10542 bp->port.link_config[1] =
10543 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 10544
a22f0788
YR		 10545 bp->link_params.multi_phy_config =
10546 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 10547 /* If the device is capable of WoL, set the default state according
10548 * to the HW
10549 */
4d295db0 10550 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 10551 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10552 (config & PORT_FEATURE_WOL_ENABLED));
10553
51c1a580 10554 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 10555 bp->link_params.lane_config,
a22f0788
YR		 10556 bp->link_params.speed_cap_mask[0],
10557 bp->port.link_config[0]);
a2fbb9ea 10558
a22f0788 10559 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 10560 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 10561 bnx2x_phy_probe(&bp->link_params);
c18487ee 10562 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 10563
10564 bnx2x_link_settings_requested(bp);
10565
01cd4528
EG		 10566 /*
10567 * If connected directly, work with the internal PHY, otherwise, work
10568 * with the external PHY
10569 */
b7737c9b
YR		 10570 ext_phy_config =
10571 SHMEM_RD(bp,
10572 dev_info.port_hw_config[port].external_phy_config);
10573 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 10574 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 10575 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 10576
10577 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10578 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10579 bp->mdio.prtad =
b7737c9b 10580 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d 10581
c8c60d88
YM		 10582 /* Configure link feature according to nvram value */
10583 eee_mode = (((SHMEM_RD(bp, dev_info.
10584 port_feature_config[port].eee_power_mode)) &
10585 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10586 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10587 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10588 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10589 EEE_MODE_ENABLE_LPI |
10590 EEE_MODE_OUTPUT_TIME;
10591 } else {
10592 bp->link_params.eee_mode = 0;
10593 }
0793f83f 10594}
01cd4528 10595
b306f5ed 10596void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 10597{
9e62e912 10598 u32 no_flags = NO_ISCSI_FLAG;
bf61ee14 10599 int port = BP_PORT(bp);
2ba45142 10600 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 10601 drv_lic_key[port].max_iscsi_conn);
2ba45142 10602
55c11941
MS		 10603 if (!CNIC_SUPPORT(bp)) {
10604 bp->flags |= no_flags;
10605 return;
10606 }
10607
b306f5ed 10608 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 10609 bp->cnic_eth_dev.max_iscsi_conn =
10610 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10611 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10612
b306f5ed
DK		 10613 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10614 bp->cnic_eth_dev.max_iscsi_conn);
10615
10616 /*
10617 * If maximum allowed number of connections is zero -
10618 * disable the feature.
10619 */
10620 if (!bp->cnic_eth_dev.max_iscsi_conn)
9e62e912 10621 bp->flags |= no_flags;
55c11941 10622
b306f5ed
DK		 10623}
10624
0329aba1 10625static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
9e62e912
DK		 10626{
10627 /* Port info */
10628 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10629 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10630 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10631 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10632
10633 /* Node info */
10634 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10635 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10636 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10637 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10638}
0329aba1 10639static void bnx2x_get_fcoe_info(struct bnx2x *bp)
b306f5ed
DK		 10640{
10641 int port = BP_PORT(bp);
10642 int func = BP_ABS_FUNC(bp);
b306f5ed
DK		 10643 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10644 drv_lic_key[port].max_fcoe_conn);
10645
55c11941
MS		 10646 if (!CNIC_SUPPORT(bp)) {
10647 bp->flags |= NO_FCOE_FLAG;
10648 return;
10649 }
10650
b306f5ed 10651 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 10652 bp->cnic_eth_dev.max_fcoe_conn =
10653 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10654 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10655
bf61ee14
VZ		 10656 /* Read the WWN: */
10657 if (!IS_MF(bp)) {
10658 /* Port info */
10659 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10660 SHMEM_RD(bp,
10661 dev_info.port_hw_config[port].
10662 fcoe_wwn_port_name_upper);
10663 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10664 SHMEM_RD(bp,
10665 dev_info.port_hw_config[port].
10666 fcoe_wwn_port_name_lower);
10667
10668 /* Node info */
10669 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10670 SHMEM_RD(bp,
10671 dev_info.port_hw_config[port].
10672 fcoe_wwn_node_name_upper);
10673 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10674 SHMEM_RD(bp,
10675 dev_info.port_hw_config[port].
10676 fcoe_wwn_node_name_lower);
10677 } else if (!IS_MF_SD(bp)) {
bf61ee14
VZ		 10678 /*
10679 * Read the WWN info only if the FCoE feature is enabled for
10680 * this function.
10681 */
7b5342d9 10682 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
9e62e912
DK		 10683 bnx2x_get_ext_wwn_info(bp, func);
10684
382e513a 10685 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
9e62e912 10686 bnx2x_get_ext_wwn_info(bp, func);
382e513a 10687 }
bf61ee14 10688
b306f5ed 10689 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 10690
bf61ee14
VZ		 10691 /*
10692 * If maximum allowed number of connections is zero -
2ba45142
VZ		 10693 * disable the feature.
10694 */
2ba45142
VZ		 10695 if (!bp->cnic_eth_dev.max_fcoe_conn)
10696 bp->flags |= NO_FCOE_FLAG;
10697}
b306f5ed 10698
0329aba1 10699static void bnx2x_get_cnic_info(struct bnx2x *bp)
b306f5ed
DK		 10700{
10701 /*
10702 * iSCSI may be dynamically disabled but reading
10703 * info here we will decrease memory usage by driver
10704 * if the feature is disabled for good
10705 */
10706 bnx2x_get_iscsi_info(bp);
10707 bnx2x_get_fcoe_info(bp);
10708}
2ba45142 10709
0329aba1 10710static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
0793f83f
DK		 10711{
10712 u32 val, val2;
10713 int func = BP_ABS_FUNC(bp);
10714 int port = BP_PORT(bp);
2ba45142
VZ		 10715 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10716 u8 *fip_mac = bp->fip_mac;
0793f83f 10717
55c11941
MS		 10718 if (IS_MF(bp)) {
10719 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142 10720 * FCoE MAC then the appropriate feature should be disabled.
55c11941
MS		 10721 * In non SD mode features configuration comes from struct
10722 * func_ext_config.
2ba45142 10723 */
55c11941 10724 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
0793f83f
DK		 10725 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10726 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10727 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 10728 iscsi_mac_addr_upper);
0793f83f 10729 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 10730 iscsi_mac_addr_lower);
2ba45142 10731 bnx2x_set_mac_buf(iscsi_mac, val, val2);
55c11941
MS		 10732 BNX2X_DEV_INFO
10733 ("Read iSCSI MAC: %pM\n", iscsi_mac);
10734 } else {
2ba45142 10735 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
55c11941 10736 }
2ba45142
VZ		 10737
10738 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10739 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 10740 fcoe_mac_addr_upper);
2ba45142 10741 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 10742 fcoe_mac_addr_lower);
2ba45142 10743 bnx2x_set_mac_buf(fip_mac, val, val2);
55c11941
MS		 10744 BNX2X_DEV_INFO
10745 ("Read FCoE L2 MAC: %pM\n", fip_mac);
10746 } else {
2ba45142 10747 bp->flags |= NO_FCOE_FLAG;
55c11941 10748 }
a3348722
BW		 10749
10750 bp->mf_ext_config = cfg;
10751
9e62e912 10752 } else { /* SD MODE */
55c11941
MS		 10753 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10754 /* use primary mac as iscsi mac */
10755 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
10756
10757 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10758 BNX2X_DEV_INFO
10759 ("Read iSCSI MAC: %pM\n", iscsi_mac);
10760 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
10761 /* use primary mac as fip mac */
10762 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
10763 BNX2X_DEV_INFO("SD FCoE MODE\n");
10764 BNX2X_DEV_INFO
10765 ("Read FIP MAC: %pM\n", fip_mac);
614c76df 10766 }
0793f83f 10767 }
a3348722 10768
55c11941
MS		 10769 if (IS_MF_STORAGE_SD(bp))
10770 /* Zero primary MAC configuration */
10771 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10772
a3348722
BW		 10773 if (IS_MF_FCOE_AFEX(bp))
10774 /* use FIP MAC as primary MAC */
10775 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10776
0793f83f 10777 } else {
0793f83f 10778 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 10779 iscsi_mac_upper);
0793f83f 10780 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 10781 iscsi_mac_lower);
2ba45142 10782 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 10783
10784 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 10785 fcoe_fip_mac_upper);
c03bd39c 10786 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 10787 fcoe_fip_mac_lower);
c03bd39c 10788 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 10789 }
10790
55c11941 10791 /* Disable iSCSI OOO if MAC configuration is invalid. */
426b9241 10792 if (!is_valid_ether_addr(iscsi_mac)) {
55c11941 10793 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
426b9241
DK		 10794 memset(iscsi_mac, 0, ETH_ALEN);
10795 }
10796
55c11941 10797 /* Disable FCoE if MAC configuration is invalid. */
426b9241
DK		 10798 if (!is_valid_ether_addr(fip_mac)) {
10799 bp->flags |= NO_FCOE_FLAG;
10800 memset(bp->fip_mac, 0, ETH_ALEN);
10801 }
55c11941
MS		 10802}
10803
0329aba1 10804static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
55c11941
MS		 10805{
10806 u32 val, val2;
10807 int func = BP_ABS_FUNC(bp);
10808 int port = BP_PORT(bp);
10809
10810 /* Zero primary MAC configuration */
10811 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10812
10813 if (BP_NOMCP(bp)) {
10814 BNX2X_ERROR("warning: random MAC workaround active\n");
10815 eth_hw_addr_random(bp->dev);
10816 } else if (IS_MF(bp)) {
10817 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10818 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10819 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10820 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10821 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10822
10823 if (CNIC_SUPPORT(bp))
10824 bnx2x_get_cnic_mac_hwinfo(bp);
10825 } else {
10826 /* in SF read MACs from port configuration */
10827 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10828 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10829 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10830
10831 if (CNIC_SUPPORT(bp))
10832 bnx2x_get_cnic_mac_hwinfo(bp);
10833 }
10834
10835 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10836 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
619c5cb6 10837
614c76df 10838 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
619c5cb6 10839 dev_err(&bp->pdev->dev,
51c1a580
MS		 10840 "bad Ethernet MAC address configuration: %pM\n"
10841 "change it manually before bringing up the appropriate network interface\n",
0f9dad10 10842 bp->dev->dev_addr);
7964211d 10843}
51c1a580 10844
0329aba1 10845static bool bnx2x_get_dropless_info(struct bnx2x *bp)
7964211d
YM		 10846{
10847 int tmp;
10848 u32 cfg;
51c1a580 10849
7964211d
YM		 10850 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
10851 /* Take function: tmp = func */
10852 tmp = BP_ABS_FUNC(bp);
10853 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
10854 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
10855 } else {
10856 /* Take port: tmp = port */
10857 tmp = BP_PORT(bp);
10858 cfg = SHMEM_RD(bp,
10859 dev_info.port_hw_config[tmp].generic_features);
10860 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
10861 }
10862 return cfg;
34f80b04
EG		 10863}
10864
0329aba1 10865static int bnx2x_get_hwinfo(struct bnx2x *bp)
34f80b04 10866{
0793f83f 10867 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 10868 int vn;
0793f83f 10869 u32 val = 0;
34f80b04 10870 int rc = 0;
a2fbb9ea 10871
34f80b04 10872 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 10873
6383c0b3
AE		 10874 /*
10875 * initialize IGU parameters
10876 */
f2e0899f
DK		 10877 if (CHIP_IS_E1x(bp)) {
10878 bp->common.int_block = INT_BLOCK_HC;
10879
10880 bp->igu_dsb_id = DEF_SB_IGU_ID;
10881 bp->igu_base_sb = 0;
f2e0899f
DK		 10882 } else {
10883 bp->common.int_block = INT_BLOCK_IGU;
7a06a122
DK		 10884
10885 /* do not allow device reset during IGU info preocessing */
10886 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10887
f2e0899f 10888 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 10889
10890 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10891 int tout = 5000;
10892
10893 BNX2X_DEV_INFO("FORCING Normal Mode\n");
10894
10895 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
10896 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
10897 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10898
10899 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10900 tout--;
10901 usleep_range(1000, 1000);
10902 }
10903
10904 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10905 dev_err(&bp->pdev->dev,
10906 "FORCING Normal Mode failed!!!\n");
9b341bb1
BW		 10907 bnx2x_release_hw_lock(bp,
10908 HW_LOCK_RESOURCE_RESET);
619c5cb6
VZ		 10909 return -EPERM;
10910 }
10911 }
10912
f2e0899f 10913 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 10914 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 10915 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10916 } else
619c5cb6 10917 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 10918
9b341bb1 10919 rc = bnx2x_get_igu_cam_info(bp);
7a06a122 10920 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9b341bb1
BW		 10921 if (rc)
10922 return rc;
f2e0899f 10923 }
619c5cb6
VZ		 10924
10925 /*
10926 * set base FW non-default (fast path) status block id, this value is
10927 * used to initialize the fw_sb_id saved on the fp/queue structure to
10928 * determine the id used by the FW.
10929 */
10930 if (CHIP_IS_E1x(bp))
10931 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10932 else /*
10933 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10934 * the same queue are indicated on the same IGU SB). So we prefer
10935 * FW and IGU SBs to be the same value.
10936 */
10937 bp->base_fw_ndsb = bp->igu_base_sb;
10938
10939 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
10940 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
10941 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 10942
10943 /*
10944 * Initialize MF configuration
10945 */
523224a3 10946
fb3bff17
DK		 10947 bp->mf_ov = 0;
10948 bp->mf_mode = 0;
3395a033 10949 vn = BP_VN(bp);
0793f83f 10950
f2e0899f 10951 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 10952 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10953 bp->common.shmem2_base, SHMEM2_RD(bp, size),
10954 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
10955
f2e0899f
DK		 10956 if (SHMEM2_HAS(bp, mf_cfg_addr))
10957 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
10958 else
10959 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 10960 offsetof(struct shmem_region, func_mb) +
10961 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 10962 /*
10963 * get mf configuration:
25985edc 10964 * 1. existence of MF configuration
0793f83f
DK		 10965 * 2. MAC address must be legal (check only upper bytes)
10966 * for Switch-Independent mode;
10967 * OVLAN must be legal for Switch-Dependent mode
10968 * 3. SF_MODE configures specific MF mode
10969 */
10970 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10971 /* get mf configuration */
10972 val = SHMEM_RD(bp,
10973 dev_info.shared_feature_config.config);
10974 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
10975
10976 switch (val) {
10977 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
10978 val = MF_CFG_RD(bp, func_mf_config[func].
10979 mac_upper);
10980 /* check for legal mac (upper bytes)*/
10981 if (val != 0xffff) {
10982 bp->mf_mode = MULTI_FUNCTION_SI;
10983 bp->mf_config[vn] = MF_CFG_RD(bp,
10984 func_mf_config[func].config);
10985 } else
51c1a580 10986 BNX2X_DEV_INFO("illegal MAC address for SI\n");
0793f83f 10987 break;
a3348722
BW		 10988 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
10989 if ((!CHIP_IS_E1x(bp)) &&
10990 (MF_CFG_RD(bp, func_mf_config[func].
10991 mac_upper) != 0xffff) &&
10992 (SHMEM2_HAS(bp,
10993 afex_driver_support))) {
10994 bp->mf_mode = MULTI_FUNCTION_AFEX;
10995 bp->mf_config[vn] = MF_CFG_RD(bp,
10996 func_mf_config[func].config);
10997 } else {
10998 BNX2X_DEV_INFO("can not configure afex mode\n");
10999 }
11000 break;
0793f83f
DK		 11001 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11002 /* get OV configuration */
11003 val = MF_CFG_RD(bp,
11004 func_mf_config[FUNC_0].e1hov_tag);
11005 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11006
11007 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11008 bp->mf_mode = MULTI_FUNCTION_SD;
11009 bp->mf_config[vn] = MF_CFG_RD(bp,
11010 func_mf_config[func].config);
11011 } else
754a2f52 11012 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f
DK		 11013 break;
11014 default:
11015 /* Unknown configuration: reset mf_config */
11016 bp->mf_config[vn] = 0;
51c1a580 11017 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
0793f83f
DK		 11018 }
11019 }
a2fbb9ea 11020
2691d51d 11021 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 11022 IS_MF(bp) ? "multi" : "single");
2691d51d 11023
0793f83f
DK		 11024 switch (bp->mf_mode) {
11025 case MULTI_FUNCTION_SD:
11026 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11027 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 11028 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 11029 bp->mf_ov = val;
619c5cb6
VZ		 11030 bp->path_has_ovlan = true;
11031
51c1a580
MS		 11032 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11033 func, bp->mf_ov, bp->mf_ov);
2691d51d 11034 } else {
619c5cb6 11035 dev_err(&bp->pdev->dev,
51c1a580
MS		 11036 "No valid MF OV for func %d, aborting\n",
11037 func);
619c5cb6 11038 return -EPERM;
34f80b04 11039 }
0793f83f 11040 break;
a3348722
BW		 11041 case MULTI_FUNCTION_AFEX:
11042 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11043 break;
0793f83f 11044 case MULTI_FUNCTION_SI:
51c1a580
MS		 11045 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11046 func);
0793f83f
DK		 11047 break;
11048 default:
11049 if (vn) {
619c5cb6 11050 dev_err(&bp->pdev->dev,
51c1a580
MS		 11051 "VN %d is in a single function mode, aborting\n",
11052 vn);
619c5cb6 11053 return -EPERM;
2691d51d 11054 }
0793f83f 11055 break;
34f80b04 11056 }
0793f83f 11057
619c5cb6
VZ		 11058 /* check if other port on the path needs ovlan:
11059 * Since MF configuration is shared between ports
11060 * Possible mixed modes are only
11061 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11062 */
11063 if (CHIP_MODE_IS_4_PORT(bp) &&
11064 !bp->path_has_ovlan &&
11065 !IS_MF(bp) &&
11066 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11067 u8 other_port = !BP_PORT(bp);
11068 u8 other_func = BP_PATH(bp) + 2*other_port;
11069 val = MF_CFG_RD(bp,
11070 func_mf_config[other_func].e1hov_tag);
11071 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11072 bp->path_has_ovlan = true;
11073 }
34f80b04 11074 }
a2fbb9ea 11075
f2e0899f
DK		 11076 /* adjust igu_sb_cnt to MF for E1x */
11077 if (CHIP_IS_E1x(bp) && IS_MF(bp))
523224a3
DK		 11078 bp->igu_sb_cnt /= E1HVN_MAX;
11079
619c5cb6
VZ		 11080 /* port info */
11081 bnx2x_get_port_hwinfo(bp);
f2e0899f 11082
0793f83f
DK		 11083 /* Get MAC addresses */
11084 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 11085
2ba45142 11086 bnx2x_get_cnic_info(bp);
2ba45142 11087
34f80b04
EG		 11088 return rc;
11089}
11090
0329aba1 11091static void bnx2x_read_fwinfo(struct bnx2x *bp)
34f24c7f
VZ		 11092{
11093 int cnt, i, block_end, rodi;
fcdf95cb 11094 char vpd_start[BNX2X_VPD_LEN+1];
34f24c7f
VZ		 11095 char str_id_reg[VENDOR_ID_LEN+1];
11096 char str_id_cap[VENDOR_ID_LEN+1];
fcdf95cb
BW		 11097 char *vpd_data;
11098 char *vpd_extended_data = NULL;
34f24c7f
VZ		 11099 u8 len;
11100
fcdf95cb 11101 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
34f24c7f
VZ		 11102 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11103
11104 if (cnt < BNX2X_VPD_LEN)
11105 goto out_not_found;
11106
fcdf95cb
BW		 11107 /* VPD RO tag should be first tag after identifier string, hence
11108 * we should be able to find it in first BNX2X_VPD_LEN chars
11109 */
11110 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
34f24c7f
VZ		 11111 PCI_VPD_LRDT_RO_DATA);
11112 if (i < 0)
11113 goto out_not_found;
11114
34f24c7f 11115 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
fcdf95cb 11116 pci_vpd_lrdt_size(&vpd_start[i]);
34f24c7f
VZ		 11117
11118 i += PCI_VPD_LRDT_TAG_SIZE;
11119
fcdf95cb
BW		 11120 if (block_end > BNX2X_VPD_LEN) {
11121 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11122 if (vpd_extended_data == NULL)
11123 goto out_not_found;
11124
11125 /* read rest of vpd image into vpd_extended_data */
11126 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11127 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11128 block_end - BNX2X_VPD_LEN,
11129 vpd_extended_data + BNX2X_VPD_LEN);
11130 if (cnt < (block_end - BNX2X_VPD_LEN))
11131 goto out_not_found;
11132 vpd_data = vpd_extended_data;
11133 } else
11134 vpd_data = vpd_start;
11135
11136 /* now vpd_data holds full vpd content in both cases */
34f24c7f
VZ		 11137
11138 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11139 PCI_VPD_RO_KEYWORD_MFR_ID);
11140 if (rodi < 0)
11141 goto out_not_found;
11142
11143 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11144
11145 if (len != VENDOR_ID_LEN)
11146 goto out_not_found;
11147
11148 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11149
11150 /* vendor specific info */
11151 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11152 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11153 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11154 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11155
11156 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11157 PCI_VPD_RO_KEYWORD_VENDOR0);
11158 if (rodi >= 0) {
11159 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11160
11161 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11162
11163 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11164 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11165 bp->fw_ver[len] = ' ';
11166 }
11167 }
fcdf95cb 11168 kfree(vpd_extended_data);
34f24c7f
VZ		 11169 return;
11170 }
11171out_not_found:
fcdf95cb 11172 kfree(vpd_extended_data);
34f24c7f
VZ		 11173 return;
11174}
11175
0329aba1 11176static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
619c5cb6
VZ		 11177{
11178 u32 flags = 0;
11179
11180 if (CHIP_REV_IS_FPGA(bp))
11181 SET_FLAGS(flags, MODE_FPGA);
11182 else if (CHIP_REV_IS_EMUL(bp))
11183 SET_FLAGS(flags, MODE_EMUL);
11184 else
11185 SET_FLAGS(flags, MODE_ASIC);
11186
11187 if (CHIP_MODE_IS_4_PORT(bp))
11188 SET_FLAGS(flags, MODE_PORT4);
11189 else
11190 SET_FLAGS(flags, MODE_PORT2);
11191
11192 if (CHIP_IS_E2(bp))
11193 SET_FLAGS(flags, MODE_E2);
11194 else if (CHIP_IS_E3(bp)) {
11195 SET_FLAGS(flags, MODE_E3);
11196 if (CHIP_REV(bp) == CHIP_REV_Ax)
11197 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 11198 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11199 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 11200 }
11201
11202 if (IS_MF(bp)) {
11203 SET_FLAGS(flags, MODE_MF);
11204 switch (bp->mf_mode) {
11205 case MULTI_FUNCTION_SD:
11206 SET_FLAGS(flags, MODE_MF_SD);
11207 break;
11208 case MULTI_FUNCTION_SI:
11209 SET_FLAGS(flags, MODE_MF_SI);
11210 break;
a3348722
BW		 11211 case MULTI_FUNCTION_AFEX:
11212 SET_FLAGS(flags, MODE_MF_AFEX);
11213 break;
619c5cb6
VZ		 11214 }
11215 } else
11216 SET_FLAGS(flags, MODE_SF);
11217
11218#if defined(__LITTLE_ENDIAN)
11219 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11220#else /*(__BIG_ENDIAN)*/
11221 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11222#endif
11223 INIT_MODE_FLAGS(bp) = flags;
11224}
11225
0329aba1 11226static int bnx2x_init_bp(struct bnx2x *bp)
34f80b04 11227{
f2e0899f 11228 int func;
34f80b04
EG		 11229 int rc;
11230
34f80b04 11231 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 11232 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 11233 spin_lock_init(&bp->stats_lock);
55c11941 11234
a2fbb9ea 11235
1cf167f2 11236 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 11237 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 11238 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
1ab4434c
AE		 11239 if (IS_PF(bp)) {
11240 rc = bnx2x_get_hwinfo(bp);
11241 if (rc)
11242 return rc;
11243 } else {
11244 random_ether_addr(bp->dev->dev_addr);
11245 }
34f80b04 11246
619c5cb6
VZ		 11247 bnx2x_set_modes_bitmap(bp);
11248
11249 rc = bnx2x_alloc_mem_bp(bp);
11250 if (rc)
11251 return rc;
523224a3 11252
34f24c7f 11253 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 11254
11255 func = BP_FUNC(bp);
11256
34f80b04 11257 /* need to reset chip if undi was active */
1ab4434c 11258 if (IS_PF(bp) && !BP_NOMCP(bp)) {
452427b0
YM		 11259 /* init fw_seq */
11260 bp->fw_seq =
11261 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11262 DRV_MSG_SEQ_NUMBER_MASK;
11263 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11264
11265 bnx2x_prev_unload(bp);
11266 }
11267
34f80b04
EG		 11268
11269 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 11270 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 11271
11272 if (BP_NOMCP(bp) && (func == 0))
51c1a580 11273 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
34f80b04 11274
614c76df 11275 bp->disable_tpa = disable_tpa;
a3348722 11276 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
614c76df 11277
7a9b2557 11278 /* Set TPA flags */
614c76df 11279 if (bp->disable_tpa) {
621b4d66 11280 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 11281 bp->dev->features &= ~NETIF_F_LRO;
11282 } else {
621b4d66 11283 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 11284 bp->dev->features |= NETIF_F_LRO;
11285 }
11286
a18f5128
EG		 11287 if (CHIP_IS_E1(bp))
11288 bp->dropless_fc = 0;
11289 else
7964211d 11290 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
a18f5128 11291
8d5726c4 11292 bp->mrrs = mrrs;
7a9b2557 11293
a3348722 11294 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1ab4434c
AE		 11295 if (IS_VF(bp))
11296 bp->rx_ring_size = MAX_RX_AVAIL;
34f80b04 11297
7d323bfd 11298 /* make sure that the numbers are in the right granularity */
523224a3
DK		 11299 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11300 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 11301
fc543637 11302 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
34f80b04
EG		 11303
11304 init_timer(&bp->timer);
11305 bp->timer.expires = jiffies + bp->current_interval;
11306 bp->timer.data = (unsigned long) bp;
11307 bp->timer.function = bnx2x_timer;
11308
0370cf90
BW		 11309 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11310 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11311 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11312 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11313 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11314 bnx2x_dcbx_init_params(bp);
11315 } else {
11316 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11317 }
e4901dde 11318
619c5cb6
VZ		 11319 if (CHIP_IS_E1x(bp))
11320 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11321 else
11322 bp->cnic_base_cl_id = FP_SB_MAX_E2;
619c5cb6 11323
6383c0b3 11324 /* multiple tx priority */
1ab4434c
AE		 11325 if (IS_VF(bp))
11326 bp->max_cos = 1;
11327 else if (CHIP_IS_E1x(bp))
6383c0b3 11328 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
1ab4434c 11329 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
6383c0b3 11330 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
1ab4434c 11331 else if (CHIP_IS_E3B0(bp))
6383c0b3 11332 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
1ab4434c
AE		 11333 else
11334 BNX2X_ERR("unknown chip %x revision %x\n",
11335 CHIP_NUM(bp), CHIP_REV(bp));
11336 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
6383c0b3 11337
55c11941
MS		 11338 /* We need at least one default status block for slow-path events,
11339 * second status block for the L2 queue, and a third status block for
11340 * CNIC if supproted.
11341 */
11342 if (CNIC_SUPPORT(bp))
11343 bp->min_msix_vec_cnt = 3;
11344 else
11345 bp->min_msix_vec_cnt = 2;
11346 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11347
34f80b04 11348 return rc;
a2fbb9ea
ET		 11349}
11350
a2fbb9ea 11351
de0c62db
DK		 11352/****************************************************************************
11353* General service functions
11354****************************************************************************/
a2fbb9ea 11355
619c5cb6
VZ		 11356/*
11357 * net_device service functions
11358 */
11359
bb2a0f7a 11360/* called with rtnl_lock */
a2fbb9ea
ET		 11361static int bnx2x_open(struct net_device *dev)
11362{
11363 struct bnx2x *bp = netdev_priv(dev);
c9ee9206
VZ		 11364 bool global = false;
11365 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3 11366 bool other_load_status, load_status;
a2fbb9ea 11367
1355b704
MY		 11368 bp->stats_init = true;
11369
6eccabb3
EG		 11370 netif_carrier_off(dev);
11371
a2fbb9ea
ET		 11372 bnx2x_set_power_state(bp, PCI_D0);
11373
ad5afc89 11374 /* If parity had happen during the unload, then attentions
c9ee9206
VZ		 11375 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11376 * want the first function loaded on the current engine to
11377 * complete the recovery.
ad5afc89 11378 * Parity recovery is only relevant for PF driver.
c9ee9206 11379 */
ad5afc89
AE		 11380 if (IS_PF(bp)) {
11381 other_load_status = bnx2x_get_load_status(bp, other_engine);
11382 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11383 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11384 bnx2x_chk_parity_attn(bp, &global, true)) {
11385 do {
11386 /* If there are attentions and they are in a
11387 * global blocks, set the GLOBAL_RESET bit
11388 * regardless whether it will be this function
11389 * that will complete the recovery or not.
11390 */
11391 if (global)
11392 bnx2x_set_reset_global(bp);
72fd0718 11393
ad5afc89
AE		 11394 /* Only the first function on the current
11395 * engine should try to recover in open. In case
11396 * of attentions in global blocks only the first
11397 * in the chip should try to recover.
11398 */
11399 if ((!load_status &&
11400 (!global || !other_load_status)) &&
11401 bnx2x_trylock_leader_lock(bp) &&
11402 !bnx2x_leader_reset(bp)) {
11403 netdev_info(bp->dev,
11404 "Recovered in open\n");
11405 break;
11406 }
72fd0718 11407
ad5afc89
AE		 11408 /* recovery has failed... */
11409 bnx2x_set_power_state(bp, PCI_D3hot);
11410 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 11411
ad5afc89
AE		 11412 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11413 "If you still see this message after a few retries then power cycle is required.\n");
72fd0718 11414
ad5afc89
AE		 11415 return -EAGAIN;
11416 } while (0);
11417 }
11418 }
72fd0718
VZ		 11419
11420 bp->recovery_state = BNX2X_RECOVERY_DONE;
bb2a0f7a 11421 return bnx2x_nic_load(bp, LOAD_OPEN);
a2fbb9ea
ET		 11422}
11423
bb2a0f7a 11424/* called with rtnl_lock */
56ad3152 11425static int bnx2x_close(struct net_device *dev)
a2fbb9ea 11426{
a2fbb9ea
ET		 11427 struct bnx2x *bp = netdev_priv(dev);
11428
11429 /* Unload the driver, release IRQs */
5d07d868 11430 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
c9ee9206
VZ		 11431
11432 /* Power off */
d3dbfee0 11433 bnx2x_set_power_state(bp, PCI_D3hot);
a2fbb9ea
ET		 11434
11435 return 0;
11436}
11437
1191cb83
ED		 11438static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11439 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 11440{
619c5cb6
VZ		 11441 int mc_count = netdev_mc_count(bp->dev);
11442 struct bnx2x_mcast_list_elem *mc_mac =
11443 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11444 struct netdev_hw_addr *ha;
6e30dd4e 11445
619c5cb6
VZ		 11446 if (!mc_mac)
11447 return -ENOMEM;
6e30dd4e 11448
619c5cb6 11449 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 11450
619c5cb6
VZ		 11451 netdev_for_each_mc_addr(ha, bp->dev) {
11452 mc_mac->mac = bnx2x_mc_addr(ha);
11453 list_add_tail(&mc_mac->link, &p->mcast_list);
11454 mc_mac++;
6e30dd4e 11455 }
619c5cb6
VZ		 11456
11457 p->mcast_list_len = mc_count;
11458
11459 return 0;
6e30dd4e
VZ		 11460}
11461
1191cb83 11462static void bnx2x_free_mcast_macs_list(
619c5cb6
VZ		 11463 struct bnx2x_mcast_ramrod_params *p)
11464{
11465 struct bnx2x_mcast_list_elem *mc_mac =
11466 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11467 link);
11468
11469 WARN_ON(!mc_mac);
11470 kfree(mc_mac);
11471}
11472
11473/**
11474 * bnx2x_set_uc_list - configure a new unicast MACs list.
11475 *
11476 * @bp: driver handle
6e30dd4e 11477 *
619c5cb6 11478 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 11479 */
1191cb83 11480static int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 11481{
619c5cb6 11482 int rc;
6e30dd4e 11483 struct net_device *dev = bp->dev;
6e30dd4e 11484 struct netdev_hw_addr *ha;
15192a8c 11485 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
619c5cb6 11486 unsigned long ramrod_flags = 0;
6e30dd4e 11487
619c5cb6
VZ		 11488 /* First schedule a cleanup up of old configuration */
11489 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11490 if (rc < 0) {
11491 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11492 return rc;
11493 }
6e30dd4e
VZ		 11494
11495 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 11496 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11497 BNX2X_UC_LIST_MAC, &ramrod_flags);
7b5342d9
YM		 11498 if (rc == -EEXIST) {
11499 DP(BNX2X_MSG_SP,
11500 "Failed to schedule ADD operations: %d\n", rc);
11501 /* do not treat adding same MAC as error */
11502 rc = 0;
11503
11504 } else if (rc < 0) {
11505
619c5cb6
VZ		 11506 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11507 rc);
11508 return rc;
6e30dd4e
VZ		 11509 }
11510 }
11511
619c5cb6
VZ		 11512 /* Execute the pending commands */
11513 __set_bit(RAMROD_CONT, &ramrod_flags);
11514 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11515 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 11516}
11517
1191cb83 11518static int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 11519{
619c5cb6 11520 struct net_device *dev = bp->dev;
3b603066 11521 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6 11522 int rc = 0;
6e30dd4e 11523
619c5cb6 11524 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 11525
619c5cb6
VZ		 11526 /* first, clear all configured multicast MACs */
11527 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11528 if (rc < 0) {
51c1a580 11529 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
619c5cb6
VZ		 11530 return rc;
11531 }
6e30dd4e 11532
619c5cb6
VZ		 11533 /* then, configure a new MACs list */
11534 if (netdev_mc_count(dev)) {
11535 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11536 if (rc) {
51c1a580
MS		 11537 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11538 rc);
619c5cb6
VZ		 11539 return rc;
11540 }
6e30dd4e 11541
619c5cb6
VZ		 11542 /* Now add the new MACs */
11543 rc = bnx2x_config_mcast(bp, &rparam,
11544 BNX2X_MCAST_CMD_ADD);
11545 if (rc < 0)
51c1a580
MS		 11546 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11547 rc);
6e30dd4e 11548
619c5cb6
VZ		 11549 bnx2x_free_mcast_macs_list(&rparam);
11550 }
6e30dd4e 11551
619c5cb6 11552 return rc;
6e30dd4e
VZ		 11553}
11554
6e30dd4e 11555
619c5cb6 11556/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
9f6c9258 11557void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 11558{
11559 struct bnx2x *bp = netdev_priv(dev);
11560 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04
EG		 11561
11562 if (bp->state != BNX2X_STATE_OPEN) {
11563 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11564 return;
11565 }
11566
619c5cb6 11567 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04
EG		 11568
11569 if (dev->flags & IFF_PROMISC)
11570 rx_mode = BNX2X_RX_MODE_PROMISC;
619c5cb6
VZ		 11571 else if ((dev->flags & IFF_ALLMULTI) ||
11572 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11573 CHIP_IS_E1(bp)))
34f80b04 11574 rx_mode = BNX2X_RX_MODE_ALLMULTI;
6e30dd4e 11575 else {
381ac16b
AE		 11576 if (IS_PF(bp)) {
11577 /* some multicasts */
11578 if (bnx2x_set_mc_list(bp) < 0)
11579 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 11580
381ac16b
AE		 11581 if (bnx2x_set_uc_list(bp) < 0)
11582 rx_mode = BNX2X_RX_MODE_PROMISC;
11583 } else {
11584 /* configuring mcast to a vf involves sleeping (when we
11585 * wait for the pf's response). Since this function is
11586 * called from non sleepable context we must schedule
11587 * a work item for this purpose
11588 */
11589 smp_mb__before_clear_bit();
11590 set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11591 &bp->sp_rtnl_state);
11592 smp_mb__after_clear_bit();
11593 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11594 }
34f80b04
EG		 11595 }
11596
11597 bp->rx_mode = rx_mode;
614c76df
DK		 11598 /* handle ISCSI SD mode */
11599 if (IS_MF_ISCSI_SD(bp))
11600 bp->rx_mode = BNX2X_RX_MODE_NONE;
619c5cb6
VZ		 11601
11602 /* Schedule the rx_mode command */
11603 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11604 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11605 return;
11606 }
11607
381ac16b
AE		 11608 if (IS_PF(bp)) {
11609 bnx2x_set_storm_rx_mode(bp);
11610 } else {
11611 /* configuring rx mode to storms in a vf involves sleeping (when
11612 * we wait for the pf's response). Since this function is
11613 * called from non sleepable context we must schedule
11614 * a work item for this purpose
11615 */
11616 smp_mb__before_clear_bit();
11617 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
11618 &bp->sp_rtnl_state);
11619 smp_mb__after_clear_bit();
11620 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11621 }
34f80b04
EG		 11622}
11623
c18487ee 11624/* called with rtnl_lock */
01cd4528
EG		 11625static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11626 int devad, u16 addr)
a2fbb9ea 11627{
01cd4528
EG		 11628 struct bnx2x *bp = netdev_priv(netdev);
11629 u16 value;
11630 int rc;
a2fbb9ea 11631
01cd4528
EG		 11632 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11633 prtad, devad, addr);
a2fbb9ea 11634
01cd4528
EG		 11635 /* The HW expects different devad if CL22 is used */
11636 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 11637
01cd4528 11638 bnx2x_acquire_phy_lock(bp);
e10bc84d 11639 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 11640 bnx2x_release_phy_lock(bp);
11641 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 11642
01cd4528
EG		 11643 if (!rc)
11644 rc = value;
11645 return rc;
11646}
a2fbb9ea 11647
01cd4528
EG		 11648/* called with rtnl_lock */
11649static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11650 u16 addr, u16 value)
11651{
11652 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 11653 int rc;
11654
51c1a580
MS		 11655 DP(NETIF_MSG_LINK,
11656 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11657 prtad, devad, addr, value);
01cd4528 11658
01cd4528
EG		 11659 /* The HW expects different devad if CL22 is used */
11660 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 11661
01cd4528 11662 bnx2x_acquire_phy_lock(bp);
e10bc84d 11663 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 11664 bnx2x_release_phy_lock(bp);
11665 return rc;
11666}
c18487ee 11667
01cd4528
EG		 11668/* called with rtnl_lock */
11669static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11670{
11671 struct bnx2x *bp = netdev_priv(dev);
11672 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 11673
01cd4528
EG		 11674 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11675 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 11676
01cd4528
EG		 11677 if (!netif_running(dev))
11678 return -EAGAIN;
11679
11680 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 11681}
11682
257ddbda 11683#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 11684static void poll_bnx2x(struct net_device *dev)
11685{
11686 struct bnx2x *bp = netdev_priv(dev);
14a15d61 11687 int i;
a2fbb9ea 11688
14a15d61
MS		 11689 for_each_eth_queue(bp, i) {
11690 struct bnx2x_fastpath *fp = &bp->fp[i];
11691 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11692 }
a2fbb9ea
ET		 11693}
11694#endif
11695
614c76df
DK		 11696static int bnx2x_validate_addr(struct net_device *dev)
11697{
11698 struct bnx2x *bp = netdev_priv(dev);
11699
51c1a580
MS		 11700 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11701 BNX2X_ERR("Non-valid Ethernet address\n");
614c76df 11702 return -EADDRNOTAVAIL;
51c1a580 11703 }
614c76df
DK		 11704 return 0;
11705}
11706
c64213cd
SH		 11707static const struct net_device_ops bnx2x_netdev_ops = {
11708 .ndo_open = bnx2x_open,
11709 .ndo_stop = bnx2x_close,
11710 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 11711 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 11712 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 11713 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 11714 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 11715 .ndo_do_ioctl = bnx2x_ioctl,
11716 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 11717 .ndo_fix_features = bnx2x_fix_features,
11718 .ndo_set_features = bnx2x_set_features,
c64213cd 11719 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 11720#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 11721 .ndo_poll_controller = poll_bnx2x,
11722#endif
6383c0b3
AE		 11723 .ndo_setup_tc = bnx2x_setup_tc,
11724
55c11941 11725#ifdef NETDEV_FCOE_WWNN
bf61ee14
VZ		 11726 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
11727#endif
c64213cd
SH		 11728};
11729
1191cb83 11730static int bnx2x_set_coherency_mask(struct bnx2x *bp)
619c5cb6
VZ		 11731{
11732 struct device *dev = &bp->pdev->dev;
11733
11734 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11735 bp->flags |= USING_DAC_FLAG;
11736 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
51c1a580 11737 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
619c5cb6
VZ		 11738 return -EIO;
11739 }
11740 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11741 dev_err(dev, "System does not support DMA, aborting\n");
11742 return -EIO;
11743 }
11744
11745 return 0;
11746}
11747
1ab4434c
AE		 11748static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
11749 struct net_device *dev, unsigned long board_type)
a2fbb9ea 11750{
a2fbb9ea 11751 int rc;
c22610d0 11752 u32 pci_cfg_dword;
65087cfe
AE		 11753 bool chip_is_e1x = (board_type == BCM57710 ||
11754 board_type == BCM57711 ||
11755 board_type == BCM57711E);
a2fbb9ea
ET		 11756
11757 SET_NETDEV_DEV(dev, &pdev->dev);
a2fbb9ea 11758
34f80b04
EG		 11759 bp->dev = dev;
11760 bp->pdev = pdev;
a2fbb9ea
ET		 11761
11762 rc = pci_enable_device(pdev);
11763 if (rc) {
cdaa7cb8
VZ		 11764 dev_err(&bp->pdev->dev,
11765 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 11766 goto err_out;
11767 }
11768
11769 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 11770 dev_err(&bp->pdev->dev,
11771 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 11772 rc = -ENODEV;
11773 goto err_out_disable;
11774 }
11775
1ab4434c
AE		 11776 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11777 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
a2fbb9ea
ET		 11778 rc = -ENODEV;
11779 goto err_out_disable;
11780 }
11781
092a5fc9
YR		 11782 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
11783 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
11784 PCICFG_REVESION_ID_ERROR_VAL) {
11785 pr_err("PCI device error, probably due to fan failure, aborting\n");
11786 rc = -ENODEV;
11787 goto err_out_disable;
11788 }
11789
34f80b04
EG		 11790 if (atomic_read(&pdev->enable_cnt) == 1) {
11791 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11792 if (rc) {
cdaa7cb8
VZ		 11793 dev_err(&bp->pdev->dev,
11794 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 11795 goto err_out_disable;
11796 }
a2fbb9ea 11797
34f80b04
EG		 11798 pci_set_master(pdev);
11799 pci_save_state(pdev);
11800 }
a2fbb9ea 11801
1ab4434c
AE		 11802 if (IS_PF(bp)) {
11803 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11804 if (bp->pm_cap == 0) {
11805 dev_err(&bp->pdev->dev,
11806 "Cannot find power management capability, aborting\n");
11807 rc = -EIO;
11808 goto err_out_release;
11809 }
a2fbb9ea
ET		 11810 }
11811
77c98e6a 11812 if (!pci_is_pcie(pdev)) {
51c1a580 11813 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 11814 rc = -EIO;
11815 goto err_out_release;
11816 }
11817
619c5cb6
VZ		 11818 rc = bnx2x_set_coherency_mask(bp);
11819 if (rc)
a2fbb9ea 11820 goto err_out_release;
a2fbb9ea 11821
34f80b04
EG		 11822 dev->mem_start = pci_resource_start(pdev, 0);
11823 dev->base_addr = dev->mem_start;
11824 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 11825
11826 dev->irq = pdev->irq;
11827
275f165f 11828 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 11829 if (!bp->regview) {
cdaa7cb8
VZ		 11830 dev_err(&bp->pdev->dev,
11831 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 11832 rc = -ENOMEM;
11833 goto err_out_release;
11834 }
11835
c22610d0
AE		 11836 /* In E1/E1H use pci device function given by kernel.
11837 * In E2/E3 read physical function from ME register since these chips
11838 * support Physical Device Assignment where kernel BDF maybe arbitrary
11839 * (depending on hypervisor).
11840 */
11841 if (chip_is_e1x)
11842 bp->pf_num = PCI_FUNC(pdev->devfn);
11843 else {/* chip is E2/3*/
11844 pci_read_config_dword(bp->pdev,
11845 PCICFG_ME_REGISTER, &pci_cfg_dword);
11846 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11847 ME_REG_ABS_PF_NUM_SHIFT);
11848 }
51c1a580 11849 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
c22610d0 11850
a2fbb9ea
ET		 11851 bnx2x_set_power_state(bp, PCI_D0);
11852
34f80b04
EG		 11853 /* clean indirect addresses */
11854 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11855 PCICFG_VENDOR_ID_OFFSET);
a5c53dbc
DK		 11856 /*
11857 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 11858 * is not used by the driver.
11859 */
1ab4434c
AE		 11860 if (IS_PF(bp)) {
11861 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11862 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11863 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
11864 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
11865
11866 if (chip_is_e1x) {
11867 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
11868 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
11869 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
11870 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
11871 }
a5c53dbc 11872
1ab4434c
AE		 11873 /* Enable internal target-read (in case we are probed after PF
11874 * FLR). Must be done prior to any BAR read access. Only for
11875 * 57712 and up
11876 */
11877 if (!chip_is_e1x)
11878 REG_WR(bp,
11879 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
a5c53dbc 11880 }
a2fbb9ea 11881
34f80b04 11882 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 11883
c64213cd 11884 dev->netdev_ops = &bnx2x_netdev_ops;
de0c62db 11885 bnx2x_set_ethtool_ops(dev);
5316bc0b 11886
01789349
JP		 11887 dev->priv_flags |= IFF_UNICAST_FLT;
11888
66371c44 11889 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
621b4d66
DK		 11890 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
11891 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
11892 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
66371c44
MM		 11893
11894 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11895 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
11896
11897 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
5316bc0b 11898 if (bp->flags & USING_DAC_FLAG)
66371c44 11899 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 11900
538dd2e3
MB		 11901 /* Add Loopback capability to the device */
11902 dev->hw_features |= NETIF_F_LOOPBACK;
11903
98507672 11904#ifdef BCM_DCBNL
785b9b1a
SR		 11905 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
11906#endif
11907
01cd4528
EG		 11908 /* get_port_hwinfo() will set prtad and mmds properly */
11909 bp->mdio.prtad = MDIO_PRTAD_NONE;
11910 bp->mdio.mmds = 0;
11911 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
11912 bp->mdio.dev = dev;
11913 bp->mdio.mdio_read = bnx2x_mdio_read;
11914 bp->mdio.mdio_write = bnx2x_mdio_write;
11915
a2fbb9ea
ET		 11916 return 0;
11917
a2fbb9ea 11918err_out_release:
34f80b04
EG		 11919 if (atomic_read(&pdev->enable_cnt) == 1)
11920 pci_release_regions(pdev);
a2fbb9ea
ET		 11921
11922err_out_disable:
11923 pci_disable_device(pdev);
11924 pci_set_drvdata(pdev, NULL);
11925
11926err_out:
11927 return rc;
11928}
11929
1dd06ae8 11930static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed)
25047950 11931{
1ab4434c 11932 u32 val = 0;
25047950 11933
1ab4434c 11934 pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
37f9ce62 11935 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
25047950 11936
37f9ce62
EG		 11937 /* return value of 1=2.5GHz 2=5GHz */
11938 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
25047950 11939}
37f9ce62 11940
6891dd25 11941static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 11942{
37f9ce62 11943 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 11944 struct bnx2x_fw_file_hdr *fw_hdr;
11945 struct bnx2x_fw_file_section *sections;
94a78b79 11946 u32 offset, len, num_ops;
37f9ce62 11947 u16 *ops_offsets;
94a78b79 11948 int i;
37f9ce62 11949 const u8 *fw_ver;
94a78b79 11950
51c1a580
MS		 11951 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
11952 BNX2X_ERR("Wrong FW size\n");
94a78b79 11953 return -EINVAL;
51c1a580 11954 }
94a78b79
VZ		 11955
11956 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
11957 sections = (struct bnx2x_fw_file_section *)fw_hdr;
11958
11959 /* Make sure none of the offsets and sizes make us read beyond
11960 * the end of the firmware data */
11961 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
11962 offset = be32_to_cpu(sections[i].offset);
11963 len = be32_to_cpu(sections[i].len);
11964 if (offset + len > firmware->size) {
51c1a580 11965 BNX2X_ERR("Section %d length is out of bounds\n", i);
94a78b79
VZ		 11966 return -EINVAL;
11967 }
11968 }
11969
11970 /* Likewise for the init_ops offsets */
11971 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
11972 ops_offsets = (u16 *)(firmware->data + offset);
11973 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
11974
11975 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
11976 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
51c1a580 11977 BNX2X_ERR("Section offset %d is out of bounds\n", i);
94a78b79
VZ		 11978 return -EINVAL;
11979 }
11980 }
11981
11982 /* Check FW version */
11983 offset = be32_to_cpu(fw_hdr->fw_version.offset);
11984 fw_ver = firmware->data + offset;
11985 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
11986 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
11987 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
11988 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
51c1a580
MS		 11989 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
11990 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
11991 BCM_5710_FW_MAJOR_VERSION,
94a78b79
VZ		 11992 BCM_5710_FW_MINOR_VERSION,
11993 BCM_5710_FW_REVISION_VERSION,
11994 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 11995 return -EINVAL;
94a78b79
VZ		 11996 }
11997
11998 return 0;
11999}
12000
1191cb83 12001static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 12002{
ab6ad5a4
EG		 12003 const __be32 *source = (const __be32 *)_source;
12004 u32 *target = (u32 *)_target;
94a78b79 12005 u32 i;
94a78b79
VZ		 12006
12007 for (i = 0; i < n/4; i++)
12008 target[i] = be32_to_cpu(source[i]);
12009}
12010
12011/*
12012 Ops array is stored in the following format:
12013 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12014 */
1191cb83 12015static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 12016{
ab6ad5a4
EG		 12017 const __be32 *source = (const __be32 *)_source;
12018 struct raw_op *target = (struct raw_op *)_target;
94a78b79 12019 u32 i, j, tmp;
94a78b79 12020
ab6ad5a4 12021 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 12022 tmp = be32_to_cpu(source[j]);
12023 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 12024 target[i].offset = tmp & 0xffffff;
12025 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 12026 }
12027}
ab6ad5a4 12028
1aa8b471 12029/* IRO array is stored in the following format:
523224a3
DK		 12030 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12031 */
1191cb83 12032static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
523224a3
DK		 12033{
12034 const __be32 *source = (const __be32 *)_source;
12035 struct iro *target = (struct iro *)_target;
12036 u32 i, j, tmp;
12037
12038 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12039 target[i].base = be32_to_cpu(source[j]);
12040 j++;
12041 tmp = be32_to_cpu(source[j]);
12042 target[i].m1 = (tmp >> 16) & 0xffff;
12043 target[i].m2 = tmp & 0xffff;
12044 j++;
12045 tmp = be32_to_cpu(source[j]);
12046 target[i].m3 = (tmp >> 16) & 0xffff;
12047 target[i].size = tmp & 0xffff;
12048 j++;
12049 }
12050}
12051
1191cb83 12052static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 12053{
ab6ad5a4
EG		 12054 const __be16 *source = (const __be16 *)_source;
12055 u16 *target = (u16 *)_target;
94a78b79 12056 u32 i;
94a78b79
VZ		 12057
12058 for (i = 0; i < n/2; i++)
12059 target[i] = be16_to_cpu(source[i]);
12060}
12061
7995c64e
JP		 12062#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12063do { \
12064 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12065 bp->arr = kmalloc(len, GFP_KERNEL); \
e404decb 12066 if (!bp->arr) \
7995c64e 12067 goto lbl; \
7995c64e
JP		 12068 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12069 (u8 *)bp->arr, len); \
12070} while (0)
94a78b79 12071
3b603066 12072static int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 12073{
c0ea452e 12074 const char *fw_file_name;
94a78b79 12075 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 12076 int rc;
94a78b79 12077
c0ea452e
MS		 12078 if (bp->firmware)
12079 return 0;
94a78b79 12080
c0ea452e
MS		 12081 if (CHIP_IS_E1(bp))
12082 fw_file_name = FW_FILE_NAME_E1;
12083 else if (CHIP_IS_E1H(bp))
12084 fw_file_name = FW_FILE_NAME_E1H;
12085 else if (!CHIP_IS_E1x(bp))
12086 fw_file_name = FW_FILE_NAME_E2;
12087 else {
12088 BNX2X_ERR("Unsupported chip revision\n");
12089 return -EINVAL;
12090 }
12091 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 12092
c0ea452e
MS		 12093 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12094 if (rc) {
12095 BNX2X_ERR("Can't load firmware file %s\n",
12096 fw_file_name);
12097 goto request_firmware_exit;
12098 }
eb2afd4a 12099
c0ea452e
MS		 12100 rc = bnx2x_check_firmware(bp);
12101 if (rc) {
12102 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12103 goto request_firmware_exit;
94a78b79
VZ		 12104 }
12105
12106 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12107
12108 /* Initialize the pointers to the init arrays */
12109 /* Blob */
12110 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12111
12112 /* Opcodes */
12113 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12114
12115 /* Offsets */
ab6ad5a4
EG		 12116 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12117 be16_to_cpu_n);
94a78b79
VZ		 12118
12119 /* STORMs firmware */
573f2035
EG		 12120 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12121 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12122 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12123 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12124 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12125 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12126 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12127 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12128 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12129 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12130 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12131 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12132 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12133 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12134 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12135 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 12136 /* IRO */
12137 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 12138
12139 return 0;
ab6ad5a4 12140
523224a3
DK		 12141iro_alloc_err:
12142 kfree(bp->init_ops_offsets);
94a78b79
VZ		 12143init_offsets_alloc_err:
12144 kfree(bp->init_ops);
12145init_ops_alloc_err:
12146 kfree(bp->init_data);
12147request_firmware_exit:
12148 release_firmware(bp->firmware);
127d0a19 12149 bp->firmware = NULL;
94a78b79
VZ		 12150
12151 return rc;
12152}
12153
619c5cb6
VZ		 12154static void bnx2x_release_firmware(struct bnx2x *bp)
12155{
12156 kfree(bp->init_ops_offsets);
12157 kfree(bp->init_ops);
12158 kfree(bp->init_data);
12159 release_firmware(bp->firmware);
eb2afd4a 12160 bp->firmware = NULL;
619c5cb6
VZ		 12161}
12162
12163
12164static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12165 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12166 .init_hw_cmn = bnx2x_init_hw_common,
12167 .init_hw_port = bnx2x_init_hw_port,
12168 .init_hw_func = bnx2x_init_hw_func,
12169
12170 .reset_hw_cmn = bnx2x_reset_common,
12171 .reset_hw_port = bnx2x_reset_port,
12172 .reset_hw_func = bnx2x_reset_func,
12173
12174 .gunzip_init = bnx2x_gunzip_init,
12175 .gunzip_end = bnx2x_gunzip_end,
12176
12177 .init_fw = bnx2x_init_firmware,
12178 .release_fw = bnx2x_release_firmware,
12179};
12180
12181void bnx2x__init_func_obj(struct bnx2x *bp)
12182{
12183 /* Prepare DMAE related driver resources */
12184 bnx2x_setup_dmae(bp);
12185
12186 bnx2x_init_func_obj(bp, &bp->func_obj,
12187 bnx2x_sp(bp, func_rdata),
12188 bnx2x_sp_mapping(bp, func_rdata),
a3348722
BW		 12189 bnx2x_sp(bp, func_afex_rdata),
12190 bnx2x_sp_mapping(bp, func_afex_rdata),
619c5cb6
VZ		 12191 &bnx2x_func_sp_drv);
12192}
12193
12194/* must be called after sriov-enable */
1191cb83 12195static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 12196{
37ae41a9 12197 int cid_count = BNX2X_L2_MAX_CID(bp);
94a78b79 12198
290ca2bb
AE		 12199 if (IS_SRIOV(bp))
12200 cid_count += BNX2X_VF_CIDS;
12201
55c11941
MS		 12202 if (CNIC_SUPPORT(bp))
12203 cid_count += CNIC_CID_MAX;
290ca2bb 12204
523224a3
DK		 12205 return roundup(cid_count, QM_CID_ROUND);
12206}
f85582f8 12207
619c5cb6 12208/**
6383c0b3 12209 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 12210 *
12211 * @dev: pci device
12212 *
12213 */
55c11941 12214static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
1ab4434c 12215 int cnic_cnt, bool is_vf)
619c5cb6 12216{
1ab4434c
AE		 12217 int pos, index;
12218 u16 control = 0;
619c5cb6
VZ		 12219
12220 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
6383c0b3
AE		 12221
12222 /*
12223 * If MSI-X is not supported - return number of SBs needed to support
12224 * one fast path queue: one FP queue + SB for CNIC
12225 */
1ab4434c
AE		 12226 if (!pos) {
12227 dev_info(&pdev->dev, "no msix capability found\n");
55c11941 12228 return 1 + cnic_cnt;
1ab4434c
AE		 12229 }
12230 dev_info(&pdev->dev, "msix capability found\n");
619c5cb6 12231
6383c0b3
AE		 12232 /*
12233 * The value in the PCI configuration space is the index of the last
12234 * entry, namely one less than the actual size of the table, which is
12235 * exactly what we want to return from this function: number of all SBs
12236 * without the default SB.
1ab4434c 12237 * For VFs there is no default SB, then we return (index+1).
6383c0b3 12238 */
619c5cb6 12239 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
619c5cb6 12240
1ab4434c 12241 index = control & PCI_MSIX_FLAGS_QSIZE;
4bd9b0ff 12242
1ab4434c
AE		 12243 return is_vf ? index + 1 : index;
12244}
523224a3 12245
1ab4434c
AE		 12246static int set_max_cos_est(int chip_id)
12247{
12248 switch (chip_id) {
f2e0899f
DK		 12249 case BCM57710:
12250 case BCM57711:
12251 case BCM57711E:
1ab4434c 12252 return BNX2X_MULTI_TX_COS_E1X;
f2e0899f 12253 case BCM57712:
619c5cb6 12254 case BCM57712_MF:
1ab4434c
AE		 12255 case BCM57712_VF:
12256 return BNX2X_MULTI_TX_COS_E2_E3A0;
619c5cb6
VZ		 12257 case BCM57800:
12258 case BCM57800_MF:
1ab4434c 12259 case BCM57800_VF:
619c5cb6
VZ		 12260 case BCM57810:
12261 case BCM57810_MF:
c3def943
YM		 12262 case BCM57840_4_10:
12263 case BCM57840_2_20:
1ab4434c 12264 case BCM57840_O:
c3def943 12265 case BCM57840_MFO:
1ab4434c 12266 case BCM57810_VF:
619c5cb6 12267 case BCM57840_MF:
1ab4434c 12268 case BCM57840_VF:
7e8e02df
BW		 12269 case BCM57811:
12270 case BCM57811_MF:
1ab4434c
AE		 12271 case BCM57811_VF:
12272 return BNX2X_MULTI_TX_COS_E3B0;
12273 return 1;
f2e0899f 12274 default:
1ab4434c 12275 pr_err("Unknown board_type (%d), aborting\n", chip_id);
870634b0 12276 return -ENODEV;
f2e0899f 12277 }
1ab4434c 12278}
f2e0899f 12279
1ab4434c
AE		 12280static int set_is_vf(int chip_id)
12281{
12282 switch (chip_id) {
12283 case BCM57712_VF:
12284 case BCM57800_VF:
12285 case BCM57810_VF:
12286 case BCM57840_VF:
12287 case BCM57811_VF:
12288 return true;
12289 default:
12290 return false;
12291 }
12292}
6383c0b3 12293
1ab4434c
AE		 12294struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12295
12296static int bnx2x_init_one(struct pci_dev *pdev,
12297 const struct pci_device_id *ent)
12298{
12299 struct net_device *dev = NULL;
12300 struct bnx2x *bp;
12301 int pcie_width, pcie_speed;
12302 int rc, max_non_def_sbs;
12303 int rx_count, tx_count, rss_count, doorbell_size;
12304 int max_cos_est;
12305 bool is_vf;
12306 int cnic_cnt;
12307
12308 /* An estimated maximum supported CoS number according to the chip
12309 * version.
12310 * We will try to roughly estimate the maximum number of CoSes this chip
12311 * may support in order to minimize the memory allocated for Tx
12312 * netdev_queue's. This number will be accurately calculated during the
12313 * initialization of bp->max_cos based on the chip versions AND chip
12314 * revision in the bnx2x_init_bp().
12315 */
12316 max_cos_est = set_max_cos_est(ent->driver_data);
12317 if (max_cos_est < 0)
12318 return max_cos_est;
12319 is_vf = set_is_vf(ent->driver_data);
12320 cnic_cnt = is_vf ? 0 : 1;
12321
12322 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf);
6383c0b3
AE		 12323
12324 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
1ab4434c
AE		 12325 rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt;
12326
12327 if (rss_count < 1)
12328 return -EINVAL;
6383c0b3
AE		 12329
12330 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
55c11941 12331 rx_count = rss_count + cnic_cnt;
6383c0b3 12332
1ab4434c 12333 /* Maximum number of netdev Tx queues:
37ae41a9 12334 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
6383c0b3 12335 */
55c11941 12336 tx_count = rss_count * max_cos_est + cnic_cnt;
f85582f8 12337
a2fbb9ea 12338 /* dev zeroed in init_etherdev */
6383c0b3 12339 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
41de8d4c 12340 if (!dev)
a2fbb9ea
ET		 12341 return -ENOMEM;
12342
a2fbb9ea 12343 bp = netdev_priv(dev);
a2fbb9ea 12344
1ab4434c
AE		 12345 bp->flags = 0;
12346 if (is_vf)
12347 bp->flags |= IS_VF_FLAG;
12348
6383c0b3 12349 bp->igu_sb_cnt = max_non_def_sbs;
1ab4434c 12350 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
6383c0b3 12351 bp->msg_enable = debug;
55c11941 12352 bp->cnic_support = cnic_cnt;
4bd9b0ff 12353 bp->cnic_probe = bnx2x_cnic_probe;
55c11941 12354
6383c0b3 12355 pci_set_drvdata(pdev, dev);
523224a3 12356
1ab4434c 12357 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
a2fbb9ea
ET		 12358 if (rc < 0) {
12359 free_netdev(dev);
12360 return rc;
12361 }
12362
1ab4434c
AE		 12363 BNX2X_DEV_INFO("This is a %s function\n",
12364 IS_PF(bp) ? "physical" : "virtual");
55c11941 12365 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
1ab4434c 12366 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
60aa0509
MS		 12367 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12368 tx_count, rx_count);
12369
34f80b04 12370 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 12371 if (rc)
12372 goto init_one_exit;
12373
1ab4434c
AE		 12374 /* Map doorbells here as we need the real value of bp->max_cos which
12375 * is initialized in bnx2x_init_bp() to determine the number of
12376 * l2 connections.
6383c0b3 12377 */
1ab4434c
AE		 12378 if (IS_VF(bp)) {
12379 /* vf doorbells are embedded within the regview */
12380 bp->doorbells = bp->regview + PXP_VF_ADDR_DB_START;
12381
12382 /* allocate vf2pf mailbox for vf to pf channel */
12383 BNX2X_PCI_ALLOC(bp->vf2pf_mbox, &bp->vf2pf_mbox_mapping,
12384 sizeof(struct bnx2x_vf_mbx_msg));
12385 } else {
12386 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12387 if (doorbell_size > pci_resource_len(pdev, 2)) {
12388 dev_err(&bp->pdev->dev,
12389 "Cannot map doorbells, bar size too small, aborting\n");
12390 rc = -ENOMEM;
12391 goto init_one_exit;
12392 }
12393 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12394 doorbell_size);
37ae41a9 12395 }
6383c0b3
AE		 12396 if (!bp->doorbells) {
12397 dev_err(&bp->pdev->dev,
12398 "Cannot map doorbell space, aborting\n");
12399 rc = -ENOMEM;
12400 goto init_one_exit;
12401 }
12402
be1f1ffa
AE		 12403 if (IS_VF(bp)) {
12404 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12405 if (rc)
12406 goto init_one_exit;
12407 }
12408
290ca2bb
AE		 12409 /* Enable SRIOV if capability found in configuration space.
12410 * Once the generic SR-IOV framework makes it in from the
12411 * pci tree this will be revised, to allow dynamic control
12412 * over the number of VFs. Right now, change the num of vfs
12413 * param below to enable SR-IOV.
12414 */
12415 rc = bnx2x_iov_init_one(bp, int_mode, 0/*num vfs*/);
12416 if (rc)
12417 goto init_one_exit;
12418
523224a3 12419 /* calc qm_cid_count */
6383c0b3 12420 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
1ab4434c 12421 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
523224a3 12422
55c11941 12423 /* disable FCOE L2 queue for E1x*/
62ac0dc9 12424 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 12425 bp->flags |= NO_FCOE_FLAG;
12426
477864dd
DK		 12427 /* disable FCOE for 57840 device, until FW supports it */
12428 switch (ent->driver_data) {
12429 case BCM57840_O:
12430 case BCM57840_4_10:
12431 case BCM57840_2_20:
12432 case BCM57840_MFO:
12433 case BCM57840_MF:
12434 bp->flags |= NO_FCOE_FLAG;
12435 }
0e8d2ec5
MS		 12436
12437 /* Set bp->num_queues for MSI-X mode*/
12438 bnx2x_set_num_queues(bp);
12439
25985edc 12440 /* Configure interrupt mode: try to enable MSI-X/MSI if
0e8d2ec5 12441 * needed.
d6214d7a 12442 */
1ab4434c
AE		 12443 rc = bnx2x_set_int_mode(bp);
12444 if (rc) {
12445 dev_err(&pdev->dev, "Cannot set interrupts\n");
12446 goto init_one_exit;
12447 }
d6214d7a 12448
1ab4434c 12449 /* register the net device */
b340007f
VZ		 12450 rc = register_netdev(dev);
12451 if (rc) {
12452 dev_err(&pdev->dev, "Cannot register net device\n");
12453 goto init_one_exit;
12454 }
1ab4434c 12455 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
b340007f 12456
55c11941 12457
ec6ba945
VZ		 12458 if (!NO_FCOE(bp)) {
12459 /* Add storage MAC address */
12460 rtnl_lock();
12461 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12462 rtnl_unlock();
12463 }
ec6ba945 12464
37f9ce62 12465 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
1ab4434c
AE		 12466 BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12467 pcie_width, pcie_speed);
d6214d7a 12468
51c1a580
MS		 12469 BNX2X_DEV_INFO(
12470 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
94f05b0f
JP		 12471 board_info[ent->driver_data].name,
12472 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12473 pcie_width,
12474 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
12475 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
12476 "5GHz (Gen2)" : "2.5GHz",
12477 dev->base_addr, bp->pdev->irq, dev->dev_addr);
c016201c 12478
a2fbb9ea 12479 return 0;
34f80b04 12480
1ab4434c
AE		 12481alloc_mem_err:
12482 BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping,
12483 sizeof(struct bnx2x_vf_mbx_msg));
12484 rc = -ENOMEM;
12485
34f80b04
EG		 12486init_one_exit:
12487 if (bp->regview)
12488 iounmap(bp->regview);
12489
1ab4434c 12490 if (IS_PF(bp) && bp->doorbells)
34f80b04
EG		 12491 iounmap(bp->doorbells);
12492
12493 free_netdev(dev);
12494
12495 if (atomic_read(&pdev->enable_cnt) == 1)
12496 pci_release_regions(pdev);
12497
12498 pci_disable_device(pdev);
12499 pci_set_drvdata(pdev, NULL);
12500
12501 return rc;
a2fbb9ea
ET		 12502}
12503
0329aba1 12504static void bnx2x_remove_one(struct pci_dev *pdev)
a2fbb9ea
ET		 12505{
12506 struct net_device *dev = pci_get_drvdata(pdev);
228241eb
ET		 12507 struct bnx2x *bp;
12508
12509 if (!dev) {
cdaa7cb8 12510 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
228241eb
ET		 12511 return;
12512 }
228241eb 12513 bp = netdev_priv(dev);
a2fbb9ea 12514
ec6ba945
VZ		 12515 /* Delete storage MAC address */
12516 if (!NO_FCOE(bp)) {
12517 rtnl_lock();
12518 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12519 rtnl_unlock();
12520 }
ec6ba945 12521
98507672
SR		 12522#ifdef BCM_DCBNL
12523 /* Delete app tlvs from dcbnl */
12524 bnx2x_dcbnl_update_applist(bp, true);
12525#endif
12526
a2fbb9ea
ET		 12527 unregister_netdev(dev);
12528
084d6cbb 12529 /* Power on: we can't let PCI layer write to us while we are in D3 */
1ab4434c
AE		 12530 if (IS_PF(bp))
12531 bnx2x_set_power_state(bp, PCI_D0);
084d6cbb 12532
d6214d7a
DK		 12533 /* Disable MSI/MSI-X */
12534 bnx2x_disable_msi(bp);
f85582f8 12535
084d6cbb 12536 /* Power off */
1ab4434c
AE		 12537 if (IS_PF(bp))
12538 bnx2x_set_power_state(bp, PCI_D3hot);
084d6cbb 12539
72fd0718 12540 /* Make sure RESET task is not scheduled before continuing */
7be08a72 12541 cancel_delayed_work_sync(&bp->sp_rtnl_task);
290ca2bb
AE		 12542
12543 bnx2x_iov_remove_one(bp);
12544
4513f925
AE		 12545 /* send message via vfpf channel to release the resources of this vf */
12546 if (IS_VF(bp))
12547 bnx2x_vfpf_release(bp);
72fd0718 12548
a2fbb9ea
ET		 12549 if (bp->regview)
12550 iounmap(bp->regview);
12551
1ab4434c
AE		 12552 /* for vf doorbells are part of the regview and were unmapped along with
12553 * it. FW is only loaded by PF.
12554 */
12555 if (IS_PF(bp)) {
12556 if (bp->doorbells)
12557 iounmap(bp->doorbells);
eb2afd4a 12558
1ab4434c
AE		 12559 bnx2x_release_firmware(bp);
12560 }
523224a3
DK		 12561 bnx2x_free_mem_bp(bp);
12562
a2fbb9ea 12563 free_netdev(dev);
34f80b04
EG		 12564
12565 if (atomic_read(&pdev->enable_cnt) == 1)
12566 pci_release_regions(pdev);
12567
a2fbb9ea
ET		 12568 pci_disable_device(pdev);
12569 pci_set_drvdata(pdev, NULL);
12570}
12571
f8ef6e44
YG		 12572static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12573{
12574 int i;
12575
12576 bp->state = BNX2X_STATE_ERROR;
12577
12578 bp->rx_mode = BNX2X_RX_MODE_NONE;
12579
55c11941
MS		 12580 if (CNIC_LOADED(bp))
12581 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12582
619c5cb6
VZ		 12583 /* Stop Tx */
12584 bnx2x_tx_disable(bp);
12585
f8ef6e44 12586 bnx2x_netif_stop(bp, 0);
26614ba5
MS		 12587 /* Delete all NAPI objects */
12588 bnx2x_del_all_napi(bp);
55c11941
MS		 12589 if (CNIC_LOADED(bp))
12590 bnx2x_del_all_napi_cnic(bp);
f8ef6e44
YG		 12591
12592 del_timer_sync(&bp->timer);
619c5cb6
VZ		 12593
12594 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
f8ef6e44
YG		 12595
12596 /* Release IRQs */
d6214d7a 12597 bnx2x_free_irq(bp);
f8ef6e44 12598
f8ef6e44
YG		 12599 /* Free SKBs, SGEs, TPA pool and driver internals */
12600 bnx2x_free_skbs(bp);
523224a3 12601
ec6ba945 12602 for_each_rx_queue(bp, i)
f8ef6e44 12603 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 12604
f8ef6e44
YG		 12605 bnx2x_free_mem(bp);
12606
12607 bp->state = BNX2X_STATE_CLOSED;
12608
619c5cb6
VZ		 12609 netif_carrier_off(bp->dev);
12610
f8ef6e44
YG		 12611 return 0;
12612}
12613
12614static void bnx2x_eeh_recover(struct bnx2x *bp)
12615{
12616 u32 val;
12617
12618 mutex_init(&bp->port.phy_mutex);
12619
f8ef6e44
YG		 12620
12621 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12622 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12623 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12624 BNX2X_ERR("BAD MCP validity signature\n");
f8ef6e44
YG		 12625}
12626
493adb1f
WX		 12627/**
12628 * bnx2x_io_error_detected - called when PCI error is detected
12629 * @pdev: Pointer to PCI device
12630 * @state: The current pci connection state
12631 *
12632 * This function is called after a PCI bus error affecting
12633 * this device has been detected.
12634 */
12635static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12636 pci_channel_state_t state)
12637{
12638 struct net_device *dev = pci_get_drvdata(pdev);
12639 struct bnx2x *bp = netdev_priv(dev);
12640
12641 rtnl_lock();
12642
12643 netif_device_detach(dev);
12644
07ce50e4
DN		 12645 if (state == pci_channel_io_perm_failure) {
12646 rtnl_unlock();
12647 return PCI_ERS_RESULT_DISCONNECT;
12648 }
12649
493adb1f 12650 if (netif_running(dev))
f8ef6e44 12651 bnx2x_eeh_nic_unload(bp);
493adb1f
WX		 12652
12653 pci_disable_device(pdev);
12654
12655 rtnl_unlock();
12656
12657 /* Request a slot reset */
12658 return PCI_ERS_RESULT_NEED_RESET;
12659}
12660
12661/**
12662 * bnx2x_io_slot_reset - called after the PCI bus has been reset
12663 * @pdev: Pointer to PCI device
12664 *
12665 * Restart the card from scratch, as if from a cold-boot.
12666 */
12667static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12668{
12669 struct net_device *dev = pci_get_drvdata(pdev);
12670 struct bnx2x *bp = netdev_priv(dev);
12671
12672 rtnl_lock();
12673
12674 if (pci_enable_device(pdev)) {
12675 dev_err(&pdev->dev,
12676 "Cannot re-enable PCI device after reset\n");
12677 rtnl_unlock();
12678 return PCI_ERS_RESULT_DISCONNECT;
12679 }
12680
12681 pci_set_master(pdev);
12682 pci_restore_state(pdev);
12683
12684 if (netif_running(dev))
12685 bnx2x_set_power_state(bp, PCI_D0);
12686
12687 rtnl_unlock();
12688
12689 return PCI_ERS_RESULT_RECOVERED;
12690}
12691
12692/**
12693 * bnx2x_io_resume - called when traffic can start flowing again
12694 * @pdev: Pointer to PCI device
12695 *
12696 * This callback is called when the error recovery driver tells us that
12697 * its OK to resume normal operation.
12698 */
12699static void bnx2x_io_resume(struct pci_dev *pdev)
12700{
12701 struct net_device *dev = pci_get_drvdata(pdev);
12702 struct bnx2x *bp = netdev_priv(dev);
12703
72fd0718 12704 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580 12705 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
72fd0718
VZ		 12706 return;
12707 }
12708
493adb1f
WX		 12709 rtnl_lock();
12710
f8ef6e44
YG		 12711 bnx2x_eeh_recover(bp);
12712
493adb1f 12713 if (netif_running(dev))
f8ef6e44 12714 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 12715
12716 netif_device_attach(dev);
12717
12718 rtnl_unlock();
12719}
12720
3646f0e5 12721static const struct pci_error_handlers bnx2x_err_handler = {
493adb1f 12722 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 12723 .slot_reset = bnx2x_io_slot_reset,
12724 .resume = bnx2x_io_resume,
493adb1f
WX		 12725};
12726
a2fbb9ea 12727static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 12728 .name = DRV_MODULE_NAME,
12729 .id_table = bnx2x_pci_tbl,
12730 .probe = bnx2x_init_one,
0329aba1 12731 .remove = bnx2x_remove_one,
493adb1f
WX		 12732 .suspend = bnx2x_suspend,
12733 .resume = bnx2x_resume,
12734 .err_handler = &bnx2x_err_handler,
a2fbb9ea
ET		 12735};
12736
12737static int __init bnx2x_init(void)
12738{
dd21ca6d
SG		 12739 int ret;
12740
7995c64e 12741 pr_info("%s", version);
938cf541 12742
1cf167f2
EG		 12743 bnx2x_wq = create_singlethread_workqueue("bnx2x");
12744 if (bnx2x_wq == NULL) {
7995c64e 12745 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 12746 return -ENOMEM;
12747 }
12748
dd21ca6d
SG		 12749 ret = pci_register_driver(&bnx2x_pci_driver);
12750 if (ret) {
7995c64e 12751 pr_err("Cannot register driver\n");
dd21ca6d
SG		 12752 destroy_workqueue(bnx2x_wq);
12753 }
12754 return ret;
a2fbb9ea
ET		 12755}
12756
12757static void __exit bnx2x_cleanup(void)
12758{
452427b0 12759 struct list_head *pos, *q;
a2fbb9ea 12760 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 12761
12762 destroy_workqueue(bnx2x_wq);
452427b0
YM		 12763
12764 /* Free globablly allocated resources */
12765 list_for_each_safe(pos, q, &bnx2x_prev_list) {
12766 struct bnx2x_prev_path_list *tmp =
12767 list_entry(pos, struct bnx2x_prev_path_list, list);
12768 list_del(pos);
12769 kfree(tmp);
12770 }
a2fbb9ea
ET		 12771}
12772
3deb8167
YR		 12773void bnx2x_notify_link_changed(struct bnx2x *bp)
12774{
12775 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12776}
12777
a2fbb9ea
ET		 12778module_init(bnx2x_init);
12779module_exit(bnx2x_cleanup);
12780
619c5cb6
VZ		 12781/**
12782 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12783 *
12784 * @bp: driver handle
12785 * @set: set or clear the CAM entry
12786 *
12787 * This function will wait until the ramdord completion returns.
12788 * Return 0 if success, -ENODEV if ramrod doesn't return.
12789 */
1191cb83 12790static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
619c5cb6
VZ		 12791{
12792 unsigned long ramrod_flags = 0;
12793
12794 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12795 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12796 &bp->iscsi_l2_mac_obj, true,
12797 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12798}
993ac7b5
MC		 12799
12800/* count denotes the number of new completions we have seen */
12801static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12802{
12803 struct eth_spe *spe;
a052997e 12804 int cxt_index, cxt_offset;
993ac7b5
MC		 12805
12806#ifdef BNX2X_STOP_ON_ERROR
12807 if (unlikely(bp->panic))
12808 return;
12809#endif
12810
12811 spin_lock_bh(&bp->spq_lock);
c2bff63f 12812 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 12813 bp->cnic_spq_pending -= count;
12814
993ac7b5 12815
c2bff63f
DK		 12816 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12817 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12818 & SPE_HDR_CONN_TYPE) >>
12819 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 12820 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12821 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 12822
12823 /* Set validation for iSCSI L2 client before sending SETUP
12824 * ramrod
12825 */
12826 if (type == ETH_CONNECTION_TYPE) {
a052997e 12827 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
37ae41a9 12828 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
a052997e 12829 ILT_PAGE_CIDS;
37ae41a9 12830 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
a052997e
MS		 12831 (cxt_index * ILT_PAGE_CIDS);
12832 bnx2x_set_ctx_validation(bp,
12833 &bp->context[cxt_index].
12834 vcxt[cxt_offset].eth,
37ae41a9 12835 BNX2X_ISCSI_ETH_CID(bp));
a052997e 12836 }
c2bff63f
DK		 12837 }
12838
619c5cb6
VZ		 12839 /*
12840 * There may be not more than 8 L2, not more than 8 L5 SPEs
12841 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 12842 * COMMON ramrods is not more than the EQ and SPQ can
12843 * accommodate.
c2bff63f 12844 */
6e30dd4e
VZ		 12845 if (type == ETH_CONNECTION_TYPE) {
12846 if (!atomic_read(&bp->cq_spq_left))
12847 break;
12848 else
12849 atomic_dec(&bp->cq_spq_left);
12850 } else if (type == NONE_CONNECTION_TYPE) {
12851 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 12852 break;
12853 else
6e30dd4e 12854 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 12855 } else if ((type == ISCSI_CONNECTION_TYPE) ||
12856 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 12857 if (bp->cnic_spq_pending >=
12858 bp->cnic_eth_dev.max_kwqe_pending)
12859 break;
12860 else
12861 bp->cnic_spq_pending++;
12862 } else {
12863 BNX2X_ERR("Unknown SPE type: %d\n", type);
12864 bnx2x_panic();
993ac7b5 12865 break;
c2bff63f 12866 }
993ac7b5
MC		 12867
12868 spe = bnx2x_sp_get_next(bp);
12869 *spe = *bp->cnic_kwq_cons;
12870
51c1a580 12871 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
993ac7b5
MC		 12872 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12873
12874 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12875 bp->cnic_kwq_cons = bp->cnic_kwq;
12876 else
12877 bp->cnic_kwq_cons++;
12878 }
12879 bnx2x_sp_prod_update(bp);
12880 spin_unlock_bh(&bp->spq_lock);
12881}
12882
12883static int bnx2x_cnic_sp_queue(struct net_device *dev,
12884 struct kwqe_16 *kwqes[], u32 count)
12885{
12886 struct bnx2x *bp = netdev_priv(dev);
12887 int i;
12888
12889#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 12890 if (unlikely(bp->panic)) {
12891 BNX2X_ERR("Can't post to SP queue while panic\n");
993ac7b5 12892 return -EIO;
51c1a580 12893 }
993ac7b5
MC		 12894#endif
12895
95c6c616
AE		 12896 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12897 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
51c1a580 12898 BNX2X_ERR("Handling parity error recovery. Try again later\n");
95c6c616
AE		 12899 return -EAGAIN;
12900 }
12901
993ac7b5
MC		 12902 spin_lock_bh(&bp->spq_lock);
12903
12904 for (i = 0; i < count; i++) {
12905 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12906
12907 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12908 break;
12909
12910 *bp->cnic_kwq_prod = *spe;
12911
12912 bp->cnic_kwq_pending++;
12913
51c1a580 12914 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
993ac7b5 12915 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 12916 spe->data.update_data_addr.hi,
12917 spe->data.update_data_addr.lo,
993ac7b5
MC		 12918 bp->cnic_kwq_pending);
12919
12920 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
12921 bp->cnic_kwq_prod = bp->cnic_kwq;
12922 else
12923 bp->cnic_kwq_prod++;
12924 }
12925
12926 spin_unlock_bh(&bp->spq_lock);
12927
12928 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
12929 bnx2x_cnic_sp_post(bp, 0);
12930
12931 return i;
12932}
12933
12934static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12935{
12936 struct cnic_ops *c_ops;
12937 int rc = 0;
12938
12939 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 12940 c_ops = rcu_dereference_protected(bp->cnic_ops,
12941 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 12942 if (c_ops)
12943 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12944 mutex_unlock(&bp->cnic_mutex);
12945
12946 return rc;
12947}
12948
12949static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12950{
12951 struct cnic_ops *c_ops;
12952 int rc = 0;
12953
12954 rcu_read_lock();
12955 c_ops = rcu_dereference(bp->cnic_ops);
12956 if (c_ops)
12957 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12958 rcu_read_unlock();
12959
12960 return rc;
12961}
12962
12963/*
12964 * for commands that have no data
12965 */
9f6c9258 12966int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 12967{
12968 struct cnic_ctl_info ctl = {0};
12969
12970 ctl.cmd = cmd;
12971
12972 return bnx2x_cnic_ctl_send(bp, &ctl);
12973}
12974
619c5cb6 12975static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 12976{
619c5cb6 12977 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 12978
12979 /* first we tell CNIC and only then we count this as a completion */
12980 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
12981 ctl.data.comp.cid = cid;
619c5cb6 12982 ctl.data.comp.error = err;
993ac7b5
MC		 12983
12984 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 12985 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 12986}
12987
619c5cb6
VZ		 12988
12989/* Called with netif_addr_lock_bh() taken.
12990 * Sets an rx_mode config for an iSCSI ETH client.
12991 * Doesn't block.
12992 * Completion should be checked outside.
12993 */
12994static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
12995{
12996 unsigned long accept_flags = 0, ramrod_flags = 0;
12997 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12998 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
12999
13000 if (start) {
13001 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13002 * because it's the only way for UIO Queue to accept
13003 * multicasts (in non-promiscuous mode only one Queue per
13004 * function will receive multicast packets (leading in our
13005 * case).
13006 */
13007 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13008 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13009 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13010 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13011
13012 /* Clear STOP_PENDING bit if START is requested */
13013 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13014
13015 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13016 } else
13017 /* Clear START_PENDING bit if STOP is requested */
13018 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13019
13020 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13021 set_bit(sched_state, &bp->sp_state);
13022 else {
13023 __set_bit(RAMROD_RX, &ramrod_flags);
13024 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13025 ramrod_flags);
13026 }
13027}
13028
13029
993ac7b5
MC		 13030static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13031{
13032 struct bnx2x *bp = netdev_priv(dev);
13033 int rc = 0;
13034
13035 switch (ctl->cmd) {
13036 case DRV_CTL_CTXTBL_WR_CMD: {
13037 u32 index = ctl->data.io.offset;
13038 dma_addr_t addr = ctl->data.io.dma_addr;
13039
13040 bnx2x_ilt_wr(bp, index, addr);
13041 break;
13042 }
13043
c2bff63f
DK		 13044 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13045 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 13046
13047 bnx2x_cnic_sp_post(bp, count);
13048 break;
13049 }
13050
13051 /* rtnl_lock is held. */
13052 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 13053 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13054 unsigned long sp_bits = 0;
13055
13056 /* Configure the iSCSI classification object */
13057 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13058 cp->iscsi_l2_client_id,
13059 cp->iscsi_l2_cid, BP_FUNC(bp),
13060 bnx2x_sp(bp, mac_rdata),
13061 bnx2x_sp_mapping(bp, mac_rdata),
13062 BNX2X_FILTER_MAC_PENDING,
13063 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13064 &bp->macs_pool);
ec6ba945 13065
523224a3 13066 /* Set iSCSI MAC address */
619c5cb6
VZ		 13067 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13068 if (rc)
13069 break;
523224a3
DK		 13070
13071 mmiowb();
13072 barrier();
13073
619c5cb6
VZ		 13074 /* Start accepting on iSCSI L2 ring */
13075
13076 netif_addr_lock_bh(dev);
13077 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13078 netif_addr_unlock_bh(dev);
13079
13080 /* bits to wait on */
13081 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13082 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13083
13084 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13085 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 13086
993ac7b5
MC		 13087 break;
13088 }
13089
13090 /* rtnl_lock is held. */
13091 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 13092 unsigned long sp_bits = 0;
993ac7b5 13093
523224a3 13094 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 13095 netif_addr_lock_bh(dev);
13096 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13097 netif_addr_unlock_bh(dev);
13098
13099 /* bits to wait on */
13100 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13101 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13102
13103 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13104 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 13105
13106 mmiowb();
13107 barrier();
13108
13109 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 13110 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13111 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 13112 break;
13113 }
c2bff63f
DK		 13114 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13115 int count = ctl->data.credit.credit_count;
13116
13117 smp_mb__before_atomic_inc();
6e30dd4e 13118 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 13119 smp_mb__after_atomic_inc();
13120 break;
13121 }
1d187b34 13122 case DRV_CTL_ULP_REGISTER_CMD: {
2e499d3c 13123 int ulp_type = ctl->data.register_data.ulp_type;
1d187b34
BW		 13124
13125 if (CHIP_IS_E3(bp)) {
13126 int idx = BP_FW_MB_IDX(bp);
2e499d3c
BW		 13127 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13128 int path = BP_PATH(bp);
13129 int port = BP_PORT(bp);
13130 int i;
13131 u32 scratch_offset;
13132 u32 *host_addr;
1d187b34 13133
2e499d3c 13134 /* first write capability to shmem2 */
1d187b34
BW		 13135 if (ulp_type == CNIC_ULP_ISCSI)
13136 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13137 else if (ulp_type == CNIC_ULP_FCOE)
13138 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13139 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
2e499d3c
BW		 13140
13141 if ((ulp_type != CNIC_ULP_FCOE) ||
13142 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13143 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
13144 break;
13145
13146 /* if reached here - should write fcoe capabilities */
13147 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13148 if (!scratch_offset)
13149 break;
13150 scratch_offset += offsetof(struct glob_ncsi_oem_data,
13151 fcoe_features[path][port]);
13152 host_addr = (u32 *) &(ctl->data.register_data.
13153 fcoe_features);
13154 for (i = 0; i < sizeof(struct fcoe_capabilities);
13155 i += 4)
13156 REG_WR(bp, scratch_offset + i,
13157 *(host_addr + i/4));
1d187b34
BW		 13158 }
13159 break;
13160 }
2e499d3c 13161
1d187b34
BW		 13162 case DRV_CTL_ULP_UNREGISTER_CMD: {
13163 int ulp_type = ctl->data.ulp_type;
13164
13165 if (CHIP_IS_E3(bp)) {
13166 int idx = BP_FW_MB_IDX(bp);
13167 u32 cap;
13168
13169 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13170 if (ulp_type == CNIC_ULP_ISCSI)
13171 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13172 else if (ulp_type == CNIC_ULP_FCOE)
13173 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13174 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13175 }
13176 break;
13177 }
993ac7b5
MC		 13178
13179 default:
13180 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13181 rc = -EINVAL;
13182 }
13183
13184 return rc;
13185}
13186
9f6c9258 13187void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 13188{
13189 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13190
13191 if (bp->flags & USING_MSIX_FLAG) {
13192 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13193 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13194 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13195 } else {
13196 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13197 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13198 }
619c5cb6 13199 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 13200 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13201 else
13202 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13203
619c5cb6
VZ		 13204 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
13205 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 13206 cp->irq_arr[1].status_blk = bp->def_status_blk;
13207 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 13208 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 13209
13210 cp->num_irq = 2;
13211}
13212
37ae41a9
MS		 13213void bnx2x_setup_cnic_info(struct bnx2x *bp)
13214{
13215 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13216
13217
13218 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13219 bnx2x_cid_ilt_lines(bp);
13220 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13221 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13222 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13223
13224 if (NO_ISCSI_OOO(bp))
13225 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13226}
13227
993ac7b5
MC		 13228static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13229 void *data)
13230{
13231 struct bnx2x *bp = netdev_priv(dev);
13232 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
55c11941
MS		 13233 int rc;
13234
13235 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
993ac7b5 13236
51c1a580
MS		 13237 if (ops == NULL) {
13238 BNX2X_ERR("NULL ops received\n");
993ac7b5 13239 return -EINVAL;
51c1a580 13240 }
993ac7b5 13241
55c11941
MS		 13242 if (!CNIC_SUPPORT(bp)) {
13243 BNX2X_ERR("Can't register CNIC when not supported\n");
13244 return -EOPNOTSUPP;
13245 }
13246
13247 if (!CNIC_LOADED(bp)) {
13248 rc = bnx2x_load_cnic(bp);
13249 if (rc) {
13250 BNX2X_ERR("CNIC-related load failed\n");
13251 return rc;
13252 }
13253
13254 }
13255
13256 bp->cnic_enabled = true;
13257
993ac7b5
MC		 13258 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13259 if (!bp->cnic_kwq)
13260 return -ENOMEM;
13261
13262 bp->cnic_kwq_cons = bp->cnic_kwq;
13263 bp->cnic_kwq_prod = bp->cnic_kwq;
13264 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13265
13266 bp->cnic_spq_pending = 0;
13267 bp->cnic_kwq_pending = 0;
13268
13269 bp->cnic_data = data;
13270
13271 cp->num_irq = 0;
619c5cb6 13272 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 13273 cp->iro_arr = bp->iro_arr;
993ac7b5 13274
993ac7b5 13275 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 13276
993ac7b5
MC		 13277 rcu_assign_pointer(bp->cnic_ops, ops);
13278
13279 return 0;
13280}
13281
13282static int bnx2x_unregister_cnic(struct net_device *dev)
13283{
13284 struct bnx2x *bp = netdev_priv(dev);
13285 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13286
13287 mutex_lock(&bp->cnic_mutex);
993ac7b5 13288 cp->drv_state = 0;
2cfa5a04 13289 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 13290 mutex_unlock(&bp->cnic_mutex);
13291 synchronize_rcu();
13292 kfree(bp->cnic_kwq);
13293 bp->cnic_kwq = NULL;
13294
13295 return 0;
13296}
13297
13298struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13299{
13300 struct bnx2x *bp = netdev_priv(dev);
13301 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13302
2ba45142
VZ		 13303 /* If both iSCSI and FCoE are disabled - return NULL in
13304 * order to indicate CNIC that it should not try to work
13305 * with this device.
13306 */
13307 if (NO_ISCSI(bp) && NO_FCOE(bp))
13308 return NULL;
13309
993ac7b5
MC		 13310 cp->drv_owner = THIS_MODULE;
13311 cp->chip_id = CHIP_ID(bp);
13312 cp->pdev = bp->pdev;
13313 cp->io_base = bp->regview;
13314 cp->io_base2 = bp->doorbells;
13315 cp->max_kwqe_pending = 8;
523224a3 13316 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 13317 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13318 bnx2x_cid_ilt_lines(bp);
993ac7b5 13319 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 13320 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 13321 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13322 cp->drv_ctl = bnx2x_drv_ctl;
13323 cp->drv_register_cnic = bnx2x_register_cnic;
13324 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
37ae41a9 13325 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
619c5cb6
VZ		 13326 cp->iscsi_l2_client_id =
13327 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
37ae41a9 13328 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
c2bff63f 13329
2ba45142
VZ		 13330 if (NO_ISCSI_OOO(bp))
13331 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13332
13333 if (NO_ISCSI(bp))
13334 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13335
13336 if (NO_FCOE(bp))
13337 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13338
51c1a580
MS		 13339 BNX2X_DEV_INFO(
13340 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
c2bff63f
DK		 13341 cp->ctx_blk_size,
13342 cp->ctx_tbl_offset,
13343 cp->ctx_tbl_len,
13344 cp->starting_cid);
993ac7b5
MC		 13345 return cp;
13346}
993ac7b5 13347
be1f1ffa
AE		 13348int bnx2x_send_msg2pf(struct bnx2x *bp, u8 *done, dma_addr_t msg_mapping)
13349{
13350 struct cstorm_vf_zone_data __iomem *zone_data =
13351 REG_ADDR(bp, PXP_VF_ADDR_CSDM_GLOBAL_START);
13352 int tout = 600, interval = 100; /* wait for 60 seconds */
13353
13354 if (*done) {
13355 BNX2X_ERR("done was non zero before message to pf was sent\n");
13356 WARN_ON(true);
13357 return -EINVAL;
13358 }
13359
13360 /* Write message address */
13361 writel(U64_LO(msg_mapping),
13362 &zone_data->non_trigger.vf_pf_channel.msg_addr_lo);
13363 writel(U64_HI(msg_mapping),
13364 &zone_data->non_trigger.vf_pf_channel.msg_addr_hi);
13365
13366 /* make sure the address is written before FW accesses it */
13367 wmb();
13368
13369 /* Trigger the PF FW */
13370 writeb(1, &zone_data->trigger.vf_pf_channel.addr_valid);
13371
13372 /* Wait for PF to complete */
13373 while ((tout >= 0) && (!*done)) {
13374 msleep(interval);
13375 tout -= 1;
13376
13377 /* progress indicator - HV can take its own sweet time in
13378 * answering VFs...
13379 */
13380 DP_CONT(BNX2X_MSG_IOV, ".");
13381 }
13382
13383 if (!*done) {
13384 BNX2X_ERR("PF response has timed out\n");
13385 return -EAGAIN;
13386 }
13387 DP(BNX2X_MSG_SP, "Got a response from PF\n");
13388 return 0;
13389}
13390
13391int bnx2x_get_vf_id(struct bnx2x *bp, u32 *vf_id)
13392{
13393 u32 me_reg;
13394 int tout = 10, interval = 100; /* Wait for 1 sec */
13395
13396 do {
13397 /* pxp traps vf read of doorbells and returns me reg value */
13398 me_reg = readl(bp->doorbells);
13399 if (GOOD_ME_REG(me_reg))
13400 break;
13401
13402 msleep(interval);
13403
13404 BNX2X_ERR("Invalid ME register value: 0x%08x\n. Is pf driver up?",
13405 me_reg);
13406 } while (tout-- > 0);
13407
13408 if (!GOOD_ME_REG(me_reg)) {
13409 BNX2X_ERR("Invalid ME register value: 0x%08x\n", me_reg);
13410 return -EINVAL;
13411 }
13412
13413 BNX2X_ERR("valid ME register value: 0x%08x\n", me_reg);
13414
13415 *vf_id = (me_reg & ME_REG_VF_NUM_MASK) >> ME_REG_VF_NUM_SHIFT;
94a78b79 13416
be1f1ffa
AE		 13417 return 0;
13418}
13419
13420int bnx2x_vfpf_acquire(struct bnx2x *bp, u8 tx_count, u8 rx_count)
13421{
13422 int rc = 0, attempts = 0;
13423 struct vfpf_acquire_tlv *req = &bp->vf2pf_mbox->req.acquire;
13424 struct pfvf_acquire_resp_tlv *resp = &bp->vf2pf_mbox->resp.acquire_resp;
13425 u32 vf_id;
13426 bool resources_acquired = false;
13427
13428 /* clear mailbox and prep first tlv */
13429 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_ACQUIRE, sizeof(*req));
13430
13431 if (bnx2x_get_vf_id(bp, &vf_id))
13432 return -EAGAIN;
13433
13434 req->vfdev_info.vf_id = vf_id;
13435 req->vfdev_info.vf_os = 0;
13436
13437 req->resc_request.num_rxqs = rx_count;
13438 req->resc_request.num_txqs = tx_count;
13439 req->resc_request.num_sbs = bp->igu_sb_cnt;
13440 req->resc_request.num_mac_filters = VF_ACQUIRE_MAC_FILTERS;
13441 req->resc_request.num_mc_filters = VF_ACQUIRE_MC_FILTERS;
13442
13443 /* add list termination tlv */
13444 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13445 sizeof(struct channel_list_end_tlv));
13446
13447 /* output tlvs list */
13448 bnx2x_dp_tlv_list(bp, req);
13449
13450 while (!resources_acquired) {
13451 DP(BNX2X_MSG_SP, "attempting to acquire resources\n");
13452
13453 /* send acquire request */
13454 rc = bnx2x_send_msg2pf(bp,
13455 &resp->hdr.status,
13456 bp->vf2pf_mbox_mapping);
13457
13458 /* PF timeout */
13459 if (rc)
13460 return rc;
13461
13462 /* copy acquire response from buffer to bp */
13463 memcpy(&bp->acquire_resp, resp, sizeof(bp->acquire_resp));
13464
13465 attempts++;
13466
13467 /* test whether the PF accepted our request. If not, humble the
13468 * the request and try again.
13469 */
13470 if (bp->acquire_resp.hdr.status == PFVF_STATUS_SUCCESS) {
13471 DP(BNX2X_MSG_SP, "resources acquired\n");
13472 resources_acquired = true;
13473 } else if (bp->acquire_resp.hdr.status ==
13474 PFVF_STATUS_NO_RESOURCE &&
13475 attempts < VF_ACQUIRE_THRESH) {
13476 DP(BNX2X_MSG_SP,
13477 "PF unwilling to fulfill resource request. Try PF recommended amount\n");
13478
13479 /* humble our request */
13480 req->resc_request.num_txqs =
13481 bp->acquire_resp.resc.num_txqs;
13482 req->resc_request.num_rxqs =
13483 bp->acquire_resp.resc.num_rxqs;
13484 req->resc_request.num_sbs =
13485 bp->acquire_resp.resc.num_sbs;
13486 req->resc_request.num_mac_filters =
13487 bp->acquire_resp.resc.num_mac_filters;
13488 req->resc_request.num_vlan_filters =
13489 bp->acquire_resp.resc.num_vlan_filters;
13490 req->resc_request.num_mc_filters =
13491 bp->acquire_resp.resc.num_mc_filters;
13492
13493 /* Clear response buffer */
13494 memset(&bp->vf2pf_mbox->resp, 0,
13495 sizeof(union pfvf_tlvs));
13496 } else {
13497 /* PF reports error */
13498 BNX2X_ERR("Failed to get the requested amount of resources: %d. Breaking...\n",
13499 bp->acquire_resp.hdr.status);
13500 return -EAGAIN;
13501 }
13502 }
13503
13504 /* get HW info */
13505 bp->common.chip_id |= (bp->acquire_resp.pfdev_info.chip_num & 0xffff);
13506 bp->link_params.chip_id = bp->common.chip_id;
13507 bp->db_size = bp->acquire_resp.pfdev_info.db_size;
13508 bp->common.int_block = INT_BLOCK_IGU;
13509 bp->common.chip_port_mode = CHIP_2_PORT_MODE;
13510 bp->igu_dsb_id = -1;
13511 bp->mf_ov = 0;
13512 bp->mf_mode = 0;
13513 bp->common.flash_size = 0;
13514 bp->flags |=
13515 NO_WOL_FLAG | NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG | NO_FCOE_FLAG;
13516 bp->igu_sb_cnt = 1;
13517 bp->igu_base_sb = bp->acquire_resp.resc.hw_sbs[0].hw_sb_id;
13518 strlcpy(bp->fw_ver, bp->acquire_resp.pfdev_info.fw_ver,
13519 sizeof(bp->fw_ver));
13520
13521 if (is_valid_ether_addr(bp->acquire_resp.resc.current_mac_addr))
13522 memcpy(bp->dev->dev_addr,
13523 bp->acquire_resp.resc.current_mac_addr,
13524 ETH_ALEN);
13525
13526 return 0;
13527}
4513f925
AE		 13528
13529int bnx2x_vfpf_release(struct bnx2x *bp)
13530{
13531 struct vfpf_release_tlv *req = &bp->vf2pf_mbox->req.release;
13532 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13533 u32 rc = 0, vf_id;
13534
13535 /* clear mailbox and prep first tlv */
13536 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_RELEASE, sizeof(*req));
13537
13538 if (bnx2x_get_vf_id(bp, &vf_id))
13539 return -EAGAIN;
13540
13541 req->vf_id = vf_id;
13542
13543 /* add list termination tlv */
13544 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13545 sizeof(struct channel_list_end_tlv));
13546
13547 /* output tlvs list */
13548 bnx2x_dp_tlv_list(bp, req);
13549
13550 /* send release request */
13551 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13552
13553 if (rc)
13554 /* PF timeout */
13555 return rc;
13556 if (resp->hdr.status == PFVF_STATUS_SUCCESS) {
13557 /* PF released us */
13558 DP(BNX2X_MSG_SP, "vf released\n");
13559 } else {
13560 /* PF reports error */
13561 BNX2X_ERR("PF failed our release request - are we out of sync? response status: %d\n",
13562 resp->hdr.status);
13563 return -EAGAIN;
13564 }
13565
13566 return 0;
13567}
8d9ac297
AE		 13568
13569/* Tell PF about SB addresses */
13570int bnx2x_vfpf_init(struct bnx2x *bp)
13571{
13572 struct vfpf_init_tlv *req = &bp->vf2pf_mbox->req.init;
13573 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13574 int rc, i;
13575
13576 /* clear mailbox and prep first tlv */
13577 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_INIT, sizeof(*req));
13578
13579 /* status blocks */
13580 for_each_eth_queue(bp, i)
13581 req->sb_addr[i] = (dma_addr_t)bnx2x_fp(bp, i,
13582 status_blk_mapping);
13583
13584 /* statistics - requests only supports single queue for now */
13585 req->stats_addr = bp->fw_stats_data_mapping +
13586 offsetof(struct bnx2x_fw_stats_data, queue_stats);
13587
13588 /* add list termination tlv */
13589 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13590 sizeof(struct channel_list_end_tlv));
13591
13592 /* output tlvs list */
13593 bnx2x_dp_tlv_list(bp, req);
13594
13595 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13596 if (rc)
13597 return rc;
13598
13599 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13600 BNX2X_ERR("INIT VF failed: %d. Breaking...\n",
13601 resp->hdr.status);
13602 return -EAGAIN;
13603 }
13604
13605 DP(BNX2X_MSG_SP, "INIT VF Succeeded\n");
13606 return 0;
13607}
13608
9b176b6b
AE		 13609/* CLOSE VF - opposite to INIT_VF */
13610void bnx2x_vfpf_close_vf(struct bnx2x *bp)
13611{
13612 struct vfpf_close_tlv *req = &bp->vf2pf_mbox->req.close;
13613 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13614 int i, rc;
13615 u32 vf_id;
13616
13617 /* If we haven't got a valid VF id, there is no sense to
13618 * continue with sending messages
13619 */
13620 if (bnx2x_get_vf_id(bp, &vf_id))
13621 goto free_irq;
13622
13623 /* Close the queues */
13624 for_each_queue(bp, i)
13625 bnx2x_vfpf_teardown_queue(bp, i);
13626
13627 /* clear mailbox and prep first tlv */
13628 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_CLOSE, sizeof(*req));
13629
13630 req->vf_id = vf_id;
13631
13632 /* add list termination tlv */
13633 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13634 sizeof(struct channel_list_end_tlv));
13635
13636 /* output tlvs list */
13637 bnx2x_dp_tlv_list(bp, req);
13638
13639 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13640
13641 if (rc)
13642 BNX2X_ERR("Sending CLOSE failed. rc was: %d\n", rc);
13643
13644 else if (resp->hdr.status != PFVF_STATUS_SUCCESS)
13645 BNX2X_ERR("Sending CLOSE failed: pf response was %d\n",
13646 resp->hdr.status);
13647
13648free_irq:
13649 /* Disable HW interrupts, NAPI */
13650 bnx2x_netif_stop(bp, 0);
13651 /* Delete all NAPI objects */
13652 bnx2x_del_all_napi(bp);
13653
13654 /* Release IRQs */
13655 bnx2x_free_irq(bp);
13656}
13657
8d9ac297
AE		 13658/* ask the pf to open a queue for the vf */
13659int bnx2x_vfpf_setup_q(struct bnx2x *bp, int fp_idx)
13660{
13661 struct vfpf_setup_q_tlv *req = &bp->vf2pf_mbox->req.setup_q;
13662 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13663 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
13664 u16 tpa_agg_size = 0, flags = 0;
13665 int rc;
13666
13667 /* clear mailbox and prep first tlv */
13668 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SETUP_Q, sizeof(*req));
13669
13670 /* select tpa mode to request */
13671 if (!fp->disable_tpa) {
13672 flags |= VFPF_QUEUE_FLG_TPA;
13673 flags |= VFPF_QUEUE_FLG_TPA_IPV6;
13674 if (fp->mode == TPA_MODE_GRO)
13675 flags |= VFPF_QUEUE_FLG_TPA_GRO;
13676 tpa_agg_size = TPA_AGG_SIZE;
13677 }
13678
13679 /* calculate queue flags */
13680 flags |= VFPF_QUEUE_FLG_STATS;
13681 flags |= VFPF_QUEUE_FLG_CACHE_ALIGN;
13682 flags |= IS_MF_SD(bp) ? VFPF_QUEUE_FLG_OV : 0;
13683 flags |= VFPF_QUEUE_FLG_VLAN;
13684 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
13685
13686 /* Common */
13687 req->vf_qid = fp_idx;
13688 req->param_valid = VFPF_RXQ_VALID | VFPF_TXQ_VALID;
13689
13690 /* Rx */
13691 req->rxq.rcq_addr = fp->rx_comp_mapping;
13692 req->rxq.rcq_np_addr = fp->rx_comp_mapping + BCM_PAGE_SIZE;
13693 req->rxq.rxq_addr = fp->rx_desc_mapping;
13694 req->rxq.sge_addr = fp->rx_sge_mapping;
13695 req->rxq.vf_sb = fp_idx;
13696 req->rxq.sb_index = HC_INDEX_ETH_RX_CQ_CONS;
13697 req->rxq.hc_rate = bp->rx_ticks ? 1000000/bp->rx_ticks : 0;
13698 req->rxq.mtu = bp->dev->mtu;
13699 req->rxq.buf_sz = fp->rx_buf_size;
13700 req->rxq.sge_buf_sz = BCM_PAGE_SIZE * PAGES_PER_SGE;
13701 req->rxq.tpa_agg_sz = tpa_agg_size;
13702 req->rxq.max_sge_pkt = SGE_PAGE_ALIGN(bp->dev->mtu) >> SGE_PAGE_SHIFT;
13703 req->rxq.max_sge_pkt = ((req->rxq.max_sge_pkt + PAGES_PER_SGE - 1) &
13704 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
13705 req->rxq.flags = flags;
13706 req->rxq.drop_flags = 0;
13707 req->rxq.cache_line_log = BNX2X_RX_ALIGN_SHIFT;
13708 req->rxq.stat_id = -1; /* No stats at the moment */
13709
13710 /* Tx */
13711 req->txq.txq_addr = fp->txdata_ptr[FIRST_TX_COS_INDEX]->tx_desc_mapping;
13712 req->txq.vf_sb = fp_idx;
13713 req->txq.sb_index = HC_INDEX_ETH_TX_CQ_CONS_COS0;
13714 req->txq.hc_rate = bp->tx_ticks ? 1000000/bp->tx_ticks : 0;
13715 req->txq.flags = flags;
13716 req->txq.traffic_type = LLFC_TRAFFIC_TYPE_NW;
13717
13718 /* add list termination tlv */
13719 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13720 sizeof(struct channel_list_end_tlv));
13721
13722 /* output tlvs list */
13723 bnx2x_dp_tlv_list(bp, req);
13724
13725 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13726 if (rc)
13727 BNX2X_ERR("Sending SETUP_Q message for queue[%d] failed!\n",
13728 fp_idx);
13729
13730 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13731 BNX2X_ERR("Status of SETUP_Q for queue[%d] is %d\n",
13732 fp_idx, resp->hdr.status);
13733 return -EINVAL;
13734 }
13735 return rc;
13736}
13737
9b176b6b
AE		 13738int bnx2x_vfpf_teardown_queue(struct bnx2x *bp, int qidx)
13739{
13740 struct vfpf_q_op_tlv *req = &bp->vf2pf_mbox->req.q_op;
13741 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13742 int rc;
13743
13744 /* clear mailbox and prep first tlv */
13745 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_TEARDOWN_Q,
13746 sizeof(*req));
13747
13748 req->vf_qid = qidx;
13749
13750 /* add list termination tlv */
13751 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13752 sizeof(struct channel_list_end_tlv));
13753
13754 /* output tlvs list */
13755 bnx2x_dp_tlv_list(bp, req);
13756
13757 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13758
13759 if (rc) {
13760 BNX2X_ERR("Sending TEARDOWN for queue %d failed: %d\n", qidx,
13761 rc);
13762 return rc;
13763 }
13764
13765 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13766 BNX2X_ERR("TEARDOWN for queue %d failed: %d\n", qidx,
13767 resp->hdr.status);
13768 return -EINVAL;
13769 }
13770
13771 return 0;
13772}
13773
8d9ac297
AE		 13774/* request pf to add a mac for the vf */
13775int bnx2x_vfpf_set_mac(struct bnx2x *bp)
13776{
13777 struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters;
13778 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13779 int rc;
13780
13781 /* clear mailbox and prep first tlv */
13782 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS,
13783 sizeof(*req));
13784
13785 req->flags = VFPF_SET_Q_FILTERS_MAC_VLAN_CHANGED;
13786 req->vf_qid = 0;
13787 req->n_mac_vlan_filters = 1;
13788 req->filters[0].flags =
13789 VFPF_Q_FILTER_DEST_MAC_VALID | VFPF_Q_FILTER_SET_MAC;
13790
13791 /* copy mac from device to request */
13792 memcpy(req->filters[0].mac, bp->dev->dev_addr, ETH_ALEN);
13793
13794 /* add list termination tlv */
13795 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13796 sizeof(struct channel_list_end_tlv));
13797
13798 /* output tlvs list */
13799 bnx2x_dp_tlv_list(bp, req);
13800
13801 /* send message to pf */
13802 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13803 if (rc) {
13804 BNX2X_ERR("failed to send message to pf. rc was %d\n", rc);
13805 return rc;
13806 }
13807
13808 /* PF failed the transaction */
13809 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13810 BNX2X_ERR("vfpf SET MAC failed: %d\n", resp->hdr.status);
13811 return -EINVAL;
13812 }
13813
13814 return 0;
13815}
381ac16b
AE		 13816
13817int bnx2x_vfpf_set_mcast(struct net_device *dev)
13818{
13819 struct bnx2x *bp = netdev_priv(dev);
13820 struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters;
13821 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13822 int rc, i = 0;
13823 struct netdev_hw_addr *ha;
13824
13825 if (bp->state != BNX2X_STATE_OPEN) {
13826 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
13827 return -EINVAL;
13828 }
13829
13830 /* clear mailbox and prep first tlv */
13831 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS,
13832 sizeof(*req));
13833
13834 /* Get Rx mode requested */
13835 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
13836
13837 netdev_for_each_mc_addr(ha, dev) {
13838 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
13839 bnx2x_mc_addr(ha));
13840 memcpy(req->multicast[i], bnx2x_mc_addr(ha), ETH_ALEN);
13841 i++;
13842 }
13843
13844 /* We support four PFVF_MAX_MULTICAST_PER_VF mcast
13845 * addresses tops
13846 */
13847 if (i >= PFVF_MAX_MULTICAST_PER_VF) {
13848 DP(NETIF_MSG_IFUP,
13849 "VF supports not more than %d multicast MAC addresses\n",
13850 PFVF_MAX_MULTICAST_PER_VF);
13851 return -EINVAL;
13852 }
13853
13854 req->n_multicast = i;
13855 req->flags |= VFPF_SET_Q_FILTERS_MULTICAST_CHANGED;
13856 req->vf_qid = 0;
13857
13858 /* add list termination tlv */
13859 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13860 sizeof(struct channel_list_end_tlv));
13861
13862 /* output tlvs list */
13863 bnx2x_dp_tlv_list(bp, req);
13864
13865 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13866 if (rc) {
13867 BNX2X_ERR("Sending a message failed: %d\n", rc);
13868 return rc;
13869 }
13870
13871 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13872 BNX2X_ERR("Set Rx mode/multicast failed: %d\n",
13873 resp->hdr.status);
13874 return -EINVAL;
13875 }
13876
13877 return 0;
13878}
13879
13880int bnx2x_vfpf_storm_rx_mode(struct bnx2x *bp)
13881{
13882 int mode = bp->rx_mode;
13883 struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters;
13884 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13885 int rc;
13886
13887 /* clear mailbox and prep first tlv */
13888 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS,
13889 sizeof(*req));
13890
13891 DP(NETIF_MSG_IFUP, "Rx mode is %d\n", mode);
13892
13893 switch (mode) {
13894 case BNX2X_RX_MODE_NONE: /* no Rx */
13895 req->rx_mask = VFPF_RX_MASK_ACCEPT_NONE;
13896 break;
13897 case BNX2X_RX_MODE_NORMAL:
13898 req->rx_mask = VFPF_RX_MASK_ACCEPT_MATCHED_MULTICAST;
13899 req->rx_mask |= VFPF_RX_MASK_ACCEPT_MATCHED_UNICAST;
13900 req->rx_mask |= VFPF_RX_MASK_ACCEPT_BROADCAST;
13901 break;
13902 case BNX2X_RX_MODE_ALLMULTI:
13903 req->rx_mask = VFPF_RX_MASK_ACCEPT_ALL_MULTICAST;
13904 req->rx_mask |= VFPF_RX_MASK_ACCEPT_MATCHED_UNICAST;
13905 req->rx_mask |= VFPF_RX_MASK_ACCEPT_BROADCAST;
13906 break;
13907 case BNX2X_RX_MODE_PROMISC:
13908 req->rx_mask = VFPF_RX_MASK_ACCEPT_ALL_UNICAST;
13909 req->rx_mask |= VFPF_RX_MASK_ACCEPT_ALL_MULTICAST;
13910 req->rx_mask |= VFPF_RX_MASK_ACCEPT_BROADCAST;
13911 break;
13912 default:
13913 BNX2X_ERR("BAD rx mode (%d)\n", mode);
13914 return -EINVAL;
13915 }
13916
13917 req->flags |= VFPF_SET_Q_FILTERS_RX_MASK_CHANGED;
13918 req->vf_qid = 0;
13919
13920 /* add list termination tlv */
13921 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13922 sizeof(struct channel_list_end_tlv));
13923
13924 /* output tlvs list */
13925 bnx2x_dp_tlv_list(bp, req);
13926
13927 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13928 if (rc)
13929 BNX2X_ERR("Sending a message failed: %d\n", rc);
13930
13931 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13932 BNX2X_ERR("Set Rx mode failed: %d\n", resp->hdr.status);
13933 return -EINVAL;
13934 }
13935
13936 return rc;
13937}
Linux kernel - Deliverables
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