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bnx2x: use ktime_get_seconds() for timestamp
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
4ad79e13 1/* bnx2x_main.c: QLogic Everest network driver.
a2fbb9ea 2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
4ad79e13
YM		 4 * Copyright (c) 2014 QLogic Corporation
5 * All rights reserved
a2fbb9ea
ET		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
10 *
08f6dd89 11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
24e3fcef 12 * Written by: Eliezer Tamir
a2fbb9ea
ET		 13 * Based on code from Michael Chan's bnx2 driver
14 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 15 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 16 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 17 *
18 */
19
f1deab50
JP		 20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
a2fbb9ea
ET		 22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/kernel.h>
25#include <linux/device.h> /* for dev_info() */
26#include <linux/timer.h>
27#include <linux/errno.h>
28#include <linux/ioport.h>
29#include <linux/slab.h>
a2fbb9ea
ET		 30#include <linux/interrupt.h>
31#include <linux/pci.h>
33d8e6a5 32#include <linux/aer.h>
a2fbb9ea
ET		 33#include <linux/init.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
37#include <linux/dma-mapping.h>
38#include <linux/bitops.h>
39#include <linux/irq.h>
40#include <linux/delay.h>
41#include <asm/byteorder.h>
42#include <linux/time.h>
43#include <linux/ethtool.h>
44#include <linux/mii.h>
0c6671b0 45#include <linux/if_vlan.h>
c9931896 46#include <linux/crash_dump.h>
a2fbb9ea 47#include <net/ip.h>
619c5cb6 48#include <net/ipv6.h>
a2fbb9ea 49#include <net/tcp.h>
51de7bb9 50#include <net/vxlan.h>
a2fbb9ea 51#include <net/checksum.h>
34f80b04 52#include <net/ip6_checksum.h>
a2fbb9ea
ET		 53#include <linux/workqueue.h>
54#include <linux/crc32.h>
34f80b04 55#include <linux/crc32c.h>
a2fbb9ea
ET		 56#include <linux/prefetch.h>
57#include <linux/zlib.h>
a2fbb9ea 58#include <linux/io.h>
452427b0 59#include <linux/semaphore.h>
45229b42 60#include <linux/stringify.h>
7ab24bfd 61#include <linux/vmalloc.h>
a2fbb9ea 62
a2fbb9ea
ET		 63#include "bnx2x.h"
64#include "bnx2x_init.h"
94a78b79 65#include "bnx2x_init_ops.h"
9f6c9258 66#include "bnx2x_cmn.h"
1ab4434c 67#include "bnx2x_vfpf.h"
e4901dde 68#include "bnx2x_dcb.h"
042181f5 69#include "bnx2x_sp.h"
94a78b79
VZ		 70#include <linux/firmware.h>
71#include "bnx2x_fw_file_hdr.h"
72/* FW files */
45229b42
BH		 73#define FW_FILE_VERSION \
74 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
75 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
76 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
77 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 78#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
79#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 80#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 81
34f80b04
EG		 82/* Time in jiffies before concluding the transmitter is hung */
83#define TX_TIMEOUT (5*HZ)
a2fbb9ea 84
0329aba1 85static char version[] =
4ad79e13 86 "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 87 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
88
24e3fcef 89MODULE_AUTHOR("Eliezer Tamir");
4ad79e13 90MODULE_DESCRIPTION("QLogic "
619c5cb6
VZ		 91 "BCM57710/57711/57711E/"
92 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
93 "57840/57840_MF Driver");
a2fbb9ea
ET		 94MODULE_LICENSE("GPL");
95MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 96MODULE_FIRMWARE(FW_FILE_NAME_E1);
97MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 98MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 99
a8f47eb7 100int bnx2x_num_queues;
1c8bb760 101module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
96305234
DK		 102MODULE_PARM_DESC(num_queues,
103 " Set number of queues (default is as a number of CPUs)");
555f6c78 104
19680c48 105static int disable_tpa;
1c8bb760 106module_param(disable_tpa, int, S_IRUGO);
9898f86d 107MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 108
a8f47eb7 109static int int_mode;
1c8bb760 110module_param(int_mode, int, S_IRUGO);
619c5cb6 111MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 112 "(1 INT#x; 2 MSI)");
8badd27a 113
a18f5128 114static int dropless_fc;
1c8bb760 115module_param(dropless_fc, int, S_IRUGO);
a18f5128
EG		 116MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
117
8d5726c4 118static int mrrs = -1;
1c8bb760 119module_param(mrrs, int, S_IRUGO);
8d5726c4
EG		 120MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
121
9898f86d 122static int debug;
1c8bb760 123module_param(debug, int, S_IRUGO);
9898f86d
EG		 124MODULE_PARM_DESC(debug, " Default debug msglevel");
125
370d4a26
YM		 126static struct workqueue_struct *bnx2x_wq;
127struct workqueue_struct *bnx2x_iov_wq;
ec6ba945 128
1ef1d45a
BW		 129struct bnx2x_mac_vals {
130 u32 xmac_addr;
131 u32 xmac_val;
132 u32 emac_addr;
133 u32 emac_val;
3d6b7253
YM		 134 u32 umac_addr[2];
135 u32 umac_val[2];
1ef1d45a
BW		 136 u32 bmac_addr;
137 u32 bmac_val[2];
138};
139
a2fbb9ea
ET		 140enum bnx2x_board_type {
141 BCM57710 = 0,
619c5cb6
VZ		 142 BCM57711,
143 BCM57711E,
144 BCM57712,
145 BCM57712_MF,
1ab4434c 146 BCM57712_VF,
619c5cb6
VZ		 147 BCM57800,
148 BCM57800_MF,
1ab4434c 149 BCM57800_VF,
619c5cb6
VZ		 150 BCM57810,
151 BCM57810_MF,
1ab4434c 152 BCM57810_VF,
c3def943
YM		 153 BCM57840_4_10,
154 BCM57840_2_20,
7e8e02df 155 BCM57840_MF,
1ab4434c 156 BCM57840_VF,
7e8e02df 157 BCM57811,
1ab4434c
AE		 158 BCM57811_MF,
159 BCM57840_O,
160 BCM57840_MFO,
161 BCM57811_VF
a2fbb9ea
ET		 162};
163
34f80b04 164/* indexed by board_type, above */
53a10565 165static struct {
a2fbb9ea 166 char *name;
0329aba1 167} board_info[] = {
4ad79e13
YM		 168 [BCM57710] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
169 [BCM57711] = { "QLogic BCM57711 10 Gigabit PCIe" },
170 [BCM57711E] = { "QLogic BCM57711E 10 Gigabit PCIe" },
171 [BCM57712] = { "QLogic BCM57712 10 Gigabit Ethernet" },
172 [BCM57712_MF] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
173 [BCM57712_VF] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
174 [BCM57800] = { "QLogic BCM57800 10 Gigabit Ethernet" },
175 [BCM57800_MF] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
176 [BCM57800_VF] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
177 [BCM57810] = { "QLogic BCM57810 10 Gigabit Ethernet" },
178 [BCM57810_MF] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
179 [BCM57810_VF] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
180 [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
181 [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
182 [BCM57840_MF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
183 [BCM57840_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
184 [BCM57811] = { "QLogic BCM57811 10 Gigabit Ethernet" },
185 [BCM57811_MF] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
186 [BCM57840_O] = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
187 [BCM57840_MFO] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
188 [BCM57811_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
a2fbb9ea
ET		 189};
190
619c5cb6
VZ		 191#ifndef PCI_DEVICE_ID_NX2_57710
192#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
193#endif
194#ifndef PCI_DEVICE_ID_NX2_57711
195#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
196#endif
197#ifndef PCI_DEVICE_ID_NX2_57711E
198#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
199#endif
200#ifndef PCI_DEVICE_ID_NX2_57712
201#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
202#endif
203#ifndef PCI_DEVICE_ID_NX2_57712_MF
204#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
205#endif
8395be5e
AE		 206#ifndef PCI_DEVICE_ID_NX2_57712_VF
207#define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
208#endif
619c5cb6
VZ		 209#ifndef PCI_DEVICE_ID_NX2_57800
210#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
211#endif
212#ifndef PCI_DEVICE_ID_NX2_57800_MF
213#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
214#endif
8395be5e
AE		 215#ifndef PCI_DEVICE_ID_NX2_57800_VF
216#define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
217#endif
619c5cb6
VZ		 218#ifndef PCI_DEVICE_ID_NX2_57810
219#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
220#endif
221#ifndef PCI_DEVICE_ID_NX2_57810_MF
222#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
223#endif
c3def943
YM		 224#ifndef PCI_DEVICE_ID_NX2_57840_O
225#define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
226#endif
8395be5e
AE		 227#ifndef PCI_DEVICE_ID_NX2_57810_VF
228#define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
229#endif
c3def943
YM		 230#ifndef PCI_DEVICE_ID_NX2_57840_4_10
231#define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
232#endif
233#ifndef PCI_DEVICE_ID_NX2_57840_2_20
234#define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
235#endif
236#ifndef PCI_DEVICE_ID_NX2_57840_MFO
237#define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
619c5cb6
VZ		 238#endif
239#ifndef PCI_DEVICE_ID_NX2_57840_MF
240#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
241#endif
8395be5e
AE		 242#ifndef PCI_DEVICE_ID_NX2_57840_VF
243#define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
244#endif
7e8e02df
BW		 245#ifndef PCI_DEVICE_ID_NX2_57811
246#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
247#endif
248#ifndef PCI_DEVICE_ID_NX2_57811_MF
249#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
250#endif
8395be5e
AE		 251#ifndef PCI_DEVICE_ID_NX2_57811_VF
252#define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
253#endif
254
9baa3c34 255static const struct pci_device_id bnx2x_pci_tbl[] = {
e4ed7113
EG		 256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6 260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
8395be5e 261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
619c5cb6
VZ		 262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
8395be5e 264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
619c5cb6
VZ		 265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
c3def943
YM		 267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
9c9a6524 269 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
c3def943 270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
8395be5e 271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
c3def943 272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
619c5cb6 273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
9c9a6524 274 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
8395be5e 275 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
9c9a6524 276 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
7e8e02df
BW		 277 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
278 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
8395be5e 279 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
a2fbb9ea
ET		 280 { 0 }
281};
282
283MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
284
452427b0
YM		 285/* Global resources for unloading a previously loaded device */
286#define BNX2X_PREV_WAIT_NEEDED 1
287static DEFINE_SEMAPHORE(bnx2x_prev_sem);
288static LIST_HEAD(bnx2x_prev_list);
a8f47eb7 289
290/* Forward declaration */
291static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
292static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
293static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
294
a2fbb9ea
ET		 295/****************************************************************************
296* General service functions
297****************************************************************************/
298
eeed018c
MK		 299static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
300
1191cb83 301static void __storm_memset_dma_mapping(struct bnx2x *bp,
619c5cb6
VZ		 302 u32 addr, dma_addr_t mapping)
303{
304 REG_WR(bp, addr, U64_LO(mapping));
305 REG_WR(bp, addr + 4, U64_HI(mapping));
306}
307
1191cb83
ED		 308static void storm_memset_spq_addr(struct bnx2x *bp,
309 dma_addr_t mapping, u16 abs_fid)
619c5cb6
VZ		 310{
311 u32 addr = XSEM_REG_FAST_MEMORY +
312 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
313
314 __storm_memset_dma_mapping(bp, addr, mapping);
315}
316
1191cb83
ED		 317static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
318 u16 pf_id)
523224a3 319{
619c5cb6
VZ		 320 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
321 pf_id);
322 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
323 pf_id);
324 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
325 pf_id);
326 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
327 pf_id);
523224a3
DK		 328}
329
1191cb83
ED		 330static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
331 u8 enable)
619c5cb6
VZ		 332{
333 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
334 enable);
335 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
336 enable);
337 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
338 enable);
339 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
340 enable);
341}
523224a3 342
1191cb83
ED		 343static void storm_memset_eq_data(struct bnx2x *bp,
344 struct event_ring_data *eq_data,
523224a3
DK		 345 u16 pfid)
346{
347 size_t size = sizeof(struct event_ring_data);
348
349 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
350
351 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
352}
353
1191cb83
ED		 354static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
355 u16 pfid)
523224a3
DK		 356{
357 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
358 REG_WR16(bp, addr, eq_prod);
359}
360
a2fbb9ea
ET		 361/* used only at init
362 * locking is done by mcp
363 */
8d96286a 364static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 365{
366 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
367 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
368 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
369 PCICFG_VENDOR_ID_OFFSET);
370}
371
a2fbb9ea
ET		 372static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
373{
374 u32 val;
375
376 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
377 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
378 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
379 PCICFG_VENDOR_ID_OFFSET);
380
381 return val;
382}
a2fbb9ea 383
f2e0899f
DK		 384#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
385#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
386#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
387#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
388#define DMAE_DP_DST_NONE "dst_addr [none]"
389
6bf07b8e
YM		 390static void bnx2x_dp_dmae(struct bnx2x *bp,
391 struct dmae_command *dmae, int msglvl)
fd1fc79d
AE		 392{
393 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
6bf07b8e 394 int i;
fd1fc79d
AE		 395
396 switch (dmae->opcode & DMAE_COMMAND_DST) {
397 case DMAE_CMD_DST_PCI:
398 if (src_type == DMAE_CMD_SRC_PCI)
399 DP(msglvl, "DMAE: opcode 0x%08x\n"
400 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
401 "comp_addr [%x:%08x], comp_val 0x%08x\n",
402 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
403 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
404 dmae->comp_addr_hi, dmae->comp_addr_lo,
405 dmae->comp_val);
406 else
407 DP(msglvl, "DMAE: opcode 0x%08x\n"
408 "src [%08x], len [%d*4], dst [%x:%08x]\n"
409 "comp_addr [%x:%08x], comp_val 0x%08x\n",
410 dmae->opcode, dmae->src_addr_lo >> 2,
411 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
412 dmae->comp_addr_hi, dmae->comp_addr_lo,
413 dmae->comp_val);
414 break;
415 case DMAE_CMD_DST_GRC:
416 if (src_type == DMAE_CMD_SRC_PCI)
417 DP(msglvl, "DMAE: opcode 0x%08x\n"
418 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
419 "comp_addr [%x:%08x], comp_val 0x%08x\n",
420 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
421 dmae->len, dmae->dst_addr_lo >> 2,
422 dmae->comp_addr_hi, dmae->comp_addr_lo,
423 dmae->comp_val);
424 else
425 DP(msglvl, "DMAE: opcode 0x%08x\n"
426 "src [%08x], len [%d*4], dst [%08x]\n"
427 "comp_addr [%x:%08x], comp_val 0x%08x\n",
428 dmae->opcode, dmae->src_addr_lo >> 2,
429 dmae->len, dmae->dst_addr_lo >> 2,
430 dmae->comp_addr_hi, dmae->comp_addr_lo,
431 dmae->comp_val);
432 break;
433 default:
434 if (src_type == DMAE_CMD_SRC_PCI)
435 DP(msglvl, "DMAE: opcode 0x%08x\n"
436 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
437 "comp_addr [%x:%08x] comp_val 0x%08x\n",
438 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
439 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
440 dmae->comp_val);
441 else
442 DP(msglvl, "DMAE: opcode 0x%08x\n"
443 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
444 "comp_addr [%x:%08x] comp_val 0x%08x\n",
445 dmae->opcode, dmae->src_addr_lo >> 2,
446 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
447 dmae->comp_val);
448 break;
449 }
6bf07b8e
YM		 450
451 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
452 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
453 i, *(((u32 *)dmae) + i));
fd1fc79d 454}
f2e0899f 455
a2fbb9ea 456/* copy command into DMAE command memory and set DMAE command go */
6c719d00 457void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 458{
459 u32 cmd_offset;
460 int i;
461
462 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
463 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
464 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 465 }
466 REG_WR(bp, dmae_reg_go_c[idx], 1);
467}
468
f2e0899f 469u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 470{
f2e0899f
DK		 471 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
472 DMAE_CMD_C_ENABLE);
473}
ad8d3948 474
f2e0899f
DK		 475u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
476{
477 return opcode & ~DMAE_CMD_SRC_RESET;
478}
ad8d3948 479
f2e0899f
DK		 480u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
481 bool with_comp, u8 comp_type)
482{
483 u32 opcode = 0;
484
485 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
486 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 487
f2e0899f
DK		 488 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
489
490 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 491 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
492 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 493 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 494
a2fbb9ea 495#ifdef __BIG_ENDIAN
f2e0899f 496 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 497#else
f2e0899f 498 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 499#endif
f2e0899f
DK		 500 if (with_comp)
501 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
502 return opcode;
503}
504
fd1fc79d 505void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
8d96286a 506 struct dmae_command *dmae,
507 u8 src_type, u8 dst_type)
f2e0899f
DK		 508{
509 memset(dmae, 0, sizeof(struct dmae_command));
510
511 /* set the opcode */
512 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
513 true, DMAE_COMP_PCI);
514
515 /* fill in the completion parameters */
516 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
517 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
518 dmae->comp_val = DMAE_COMP_VAL;
519}
520
fd1fc79d 521/* issue a dmae command over the init-channel and wait for completion */
32316a46
AE		 522int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
523 u32 *comp)
f2e0899f 524{
5e374b5a 525 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 526 int rc = 0;
527
6bf07b8e
YM		 528 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
529
530 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
619c5cb6
VZ		 531 * as long as this code is called both from syscall context and
532 * from ndo_set_rx_mode() flow that may be called from BH.
533 */
eeed018c 534
6e30dd4e 535 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 536
f2e0899f 537 /* reset completion */
32316a46 538 *comp = 0;
a2fbb9ea 539
f2e0899f
DK		 540 /* post the command on the channel used for initializations */
541 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 542
f2e0899f 543 /* wait for completion */
a2fbb9ea 544 udelay(5);
32316a46 545 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948 546
95c6c616
AE		 547 if (!cnt ||
548 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
549 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
c3eefaf6 550 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 551 rc = DMAE_TIMEOUT;
552 goto unlock;
a2fbb9ea 553 }
ad8d3948 554 cnt--;
f2e0899f 555 udelay(50);
a2fbb9ea 556 }
32316a46 557 if (*comp & DMAE_PCI_ERR_FLAG) {
f2e0899f
DK		 558 BNX2X_ERR("DMAE PCI error!\n");
559 rc = DMAE_PCI_ERROR;
560 }
561
f2e0899f 562unlock:
eeed018c 563
6e30dd4e 564 spin_unlock_bh(&bp->dmae_lock);
eeed018c 565
f2e0899f
DK		 566 return rc;
567}
568
569void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
570 u32 len32)
571{
6bf07b8e 572 int rc;
f2e0899f
DK		 573 struct dmae_command dmae;
574
575 if (!bp->dmae_ready) {
576 u32 *data = bnx2x_sp(bp, wb_data[0]);
577
127a425e
AE		 578 if (CHIP_IS_E1(bp))
579 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
580 else
581 bnx2x_init_str_wr(bp, dst_addr, data, len32);
f2e0899f
DK		 582 return;
583 }
584
585 /* set opcode and fixed command fields */
586 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
587
588 /* fill in addresses and len */
589 dmae.src_addr_lo = U64_LO(dma_addr);
590 dmae.src_addr_hi = U64_HI(dma_addr);
591 dmae.dst_addr_lo = dst_addr >> 2;
592 dmae.dst_addr_hi = 0;
593 dmae.len = len32;
594
f2e0899f 595 /* issue the command and wait for completion */
32316a46 596 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 597 if (rc) {
598 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 599#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 600 bnx2x_panic();
9dcd9acd 601#endif
6bf07b8e 602 }
a2fbb9ea
ET		 603}
604
c18487ee 605void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 606{
6bf07b8e 607 int rc;
5ff7b6d4 608 struct dmae_command dmae;
ad8d3948
EG		 609
610 if (!bp->dmae_ready) {
611 u32 *data = bnx2x_sp(bp, wb_data[0]);
612 int i;
613
51c1a580 614 if (CHIP_IS_E1(bp))
127a425e
AE		 615 for (i = 0; i < len32; i++)
616 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
51c1a580 617 else
127a425e
AE		 618 for (i = 0; i < len32; i++)
619 data[i] = REG_RD(bp, src_addr + i*4);
620
ad8d3948
EG		 621 return;
622 }
623
f2e0899f
DK		 624 /* set opcode and fixed command fields */
625 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 626
f2e0899f 627 /* fill in addresses and len */
5ff7b6d4
EG		 628 dmae.src_addr_lo = src_addr >> 2;
629 dmae.src_addr_hi = 0;
630 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
631 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
632 dmae.len = len32;
ad8d3948 633
f2e0899f 634 /* issue the command and wait for completion */
32316a46 635 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 636 if (rc) {
637 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 638#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 639 bnx2x_panic();
9dcd9acd 640#endif
c957d09f 641 }
ad8d3948
EG		 642}
643
8d96286a 644static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
645 u32 addr, u32 len)
573f2035 646{
02e3c6cb 647 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 648 int offset = 0;
649
02e3c6cb 650 while (len > dmae_wr_max) {
573f2035 651 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 652 addr + offset, dmae_wr_max);
653 offset += dmae_wr_max * 4;
654 len -= dmae_wr_max;
573f2035
EG		 655 }
656
657 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
658}
659
97539f1e
AE		 660enum storms {
661 XSTORM,
662 TSTORM,
663 CSTORM,
664 USTORM,
665 MAX_STORMS
666};
34f80b04 667
97539f1e
AE		 668#define STORMS_NUM 4
669#define REGS_IN_ENTRY 4
34f80b04 670
97539f1e
AE		 671static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
672 enum storms storm,
673 int entry)
674{
675 switch (storm) {
676 case XSTORM:
677 return XSTORM_ASSERT_LIST_OFFSET(entry);
678 case TSTORM:
679 return TSTORM_ASSERT_LIST_OFFSET(entry);
680 case CSTORM:
681 return CSTORM_ASSERT_LIST_OFFSET(entry);
682 case USTORM:
683 return USTORM_ASSERT_LIST_OFFSET(entry);
684 case MAX_STORMS:
685 default:
686 BNX2X_ERR("unknown storm\n");
34f80b04 687 }
97539f1e
AE		 688 return -EINVAL;
689}
34f80b04 690
97539f1e
AE		 691static int bnx2x_mc_assert(struct bnx2x *bp)
692{
693 char last_idx;
694 int i, j, rc = 0;
695 enum storms storm;
696 u32 regs[REGS_IN_ENTRY];
697 u32 bar_storm_intmem[STORMS_NUM] = {
698 BAR_XSTRORM_INTMEM,
699 BAR_TSTRORM_INTMEM,
700 BAR_CSTRORM_INTMEM,
701 BAR_USTRORM_INTMEM
702 };
703 u32 storm_assert_list_index[STORMS_NUM] = {
704 XSTORM_ASSERT_LIST_INDEX_OFFSET,
705 TSTORM_ASSERT_LIST_INDEX_OFFSET,
706 CSTORM_ASSERT_LIST_INDEX_OFFSET,
707 USTORM_ASSERT_LIST_INDEX_OFFSET
708 };
709 char *storms_string[STORMS_NUM] = {
710 "XSTORM",
711 "TSTORM",
712 "CSTORM",
713 "USTORM"
714 };
715
716 for (storm = XSTORM; storm < MAX_STORMS; storm++) {
717 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
718 storm_assert_list_index[storm]);
719 if (last_idx)
720 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
721 storms_string[storm], last_idx);
722
723 /* print the asserts */
724 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
725 /* read a single assert entry */
726 for (j = 0; j < REGS_IN_ENTRY; j++)
727 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
728 bnx2x_get_assert_list_entry(bp,
729 storm,
730 i) +
731 sizeof(u32) * j);
732
733 /* log entry if it contains a valid assert */
734 if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
735 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
736 storms_string[storm], i, regs[3],
737 regs[2], regs[1], regs[0]);
738 rc++;
739 } else {
740 break;
741 }
a2fbb9ea
ET		 742 }
743 }
34f80b04 744
97539f1e
AE		 745 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
746 CHIP_IS_E1(bp) ? "everest1" :
747 CHIP_IS_E1H(bp) ? "everest1h" :
748 CHIP_IS_E2(bp) ? "everest2" : "everest3",
749 BCM_5710_FW_MAJOR_VERSION,
750 BCM_5710_FW_MINOR_VERSION,
751 BCM_5710_FW_REVISION_VERSION);
752
a2fbb9ea
ET		 753 return rc;
754}
c14423fe 755
1a6974b2
YM		 756#define MCPR_TRACE_BUFFER_SIZE (0x800)
757#define SCRATCH_BUFFER_SIZE(bp) \
758 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
759
7a25cc73 760void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 761{
7a25cc73 762 u32 addr, val;
a2fbb9ea 763 u32 mark, offset;
4781bfad 764 __be32 data[9];
a2fbb9ea 765 int word;
f2e0899f 766 u32 trace_shmem_base;
2145a920
VZ		 767 if (BP_NOMCP(bp)) {
768 BNX2X_ERR("NO MCP - can not dump\n");
769 return;
770 }
7a25cc73
DK		 771 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
772 (bp->common.bc_ver & 0xff0000) >> 16,
773 (bp->common.bc_ver & 0xff00) >> 8,
774 (bp->common.bc_ver & 0xff));
775
776 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
777 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
51c1a580 778 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 779
f2e0899f
DK		 780 if (BP_PATH(bp) == 0)
781 trace_shmem_base = bp->common.shmem_base;
782 else
783 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
1a6974b2
YM		 784
785 /* sanity */
786 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
787 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
788 SCRATCH_BUFFER_SIZE(bp)) {
789 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
790 trace_shmem_base);
791 return;
792 }
793
794 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
de128804
DK		 795
796 /* validate TRCB signature */
797 mark = REG_RD(bp, addr);
798 if (mark != MFW_TRACE_SIGNATURE) {
799 BNX2X_ERR("Trace buffer signature is missing.");
800 return ;
801 }
802
803 /* read cyclic buffer pointer */
804 addr += 4;
cdaa7cb8 805 mark = REG_RD(bp, addr);
1a6974b2
YM		 806 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
807 if (mark >= trace_shmem_base || mark < addr + 4) {
808 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
809 return;
810 }
7a25cc73 811 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 812
7a25cc73 813 printk("%s", lvl);
2de67439
YM		 814
815 /* dump buffer after the mark */
1a6974b2 816 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 817 for (word = 0; word < 8; word++)
cdaa7cb8 818 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 819 data[8] = 0x0;
7995c64e 820 pr_cont("%s", (char *)data);
a2fbb9ea 821 }
2de67439
YM		 822
823 /* dump buffer before the mark */
cdaa7cb8 824 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 825 for (word = 0; word < 8; word++)
cdaa7cb8 826 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 827 data[8] = 0x0;
7995c64e 828 pr_cont("%s", (char *)data);
a2fbb9ea 829 }
7a25cc73
DK		 830 printk("%s" "end of fw dump\n", lvl);
831}
832
1191cb83 833static void bnx2x_fw_dump(struct bnx2x *bp)
7a25cc73
DK		 834{
835 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 836}
837
823e1d90
YM		 838static void bnx2x_hc_int_disable(struct bnx2x *bp)
839{
840 int port = BP_PORT(bp);
841 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
842 u32 val = REG_RD(bp, addr);
843
844 /* in E1 we must use only PCI configuration space to disable
16a5fd92
YM		 845 * MSI/MSIX capability
846 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
823e1d90
YM		 847 */
848 if (CHIP_IS_E1(bp)) {
849 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
850 * Use mask register to prevent from HC sending interrupts
851 * after we exit the function
852 */
853 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
854
855 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
856 HC_CONFIG_0_REG_INT_LINE_EN_0 |
857 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
858 } else
859 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
860 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
861 HC_CONFIG_0_REG_INT_LINE_EN_0 |
862 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
863
864 DP(NETIF_MSG_IFDOWN,
865 "write %x to HC %d (addr 0x%x)\n",
866 val, port, addr);
867
868 /* flush all outstanding writes */
869 mmiowb();
870
871 REG_WR(bp, addr, val);
872 if (REG_RD(bp, addr) != val)
6bf07b8e 873 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 874}
875
876static void bnx2x_igu_int_disable(struct bnx2x *bp)
877{
878 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
879
880 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
881 IGU_PF_CONF_INT_LINE_EN |
882 IGU_PF_CONF_ATTN_BIT_EN);
883
884 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
885
886 /* flush all outstanding writes */
887 mmiowb();
888
889 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
890 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
6bf07b8e 891 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 892}
893
894static void bnx2x_int_disable(struct bnx2x *bp)
895{
896 if (bp->common.int_block == INT_BLOCK_HC)
897 bnx2x_hc_int_disable(bp);
898 else
899 bnx2x_igu_int_disable(bp);
900}
901
902void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
a2fbb9ea
ET		 903{
904 int i;
523224a3
DK		 905 u16 j;
906 struct hc_sp_status_block_data sp_sb_data;
907 int func = BP_FUNC(bp);
908#ifdef BNX2X_STOP_ON_ERROR
909 u16 start = 0, end = 0;
6383c0b3 910 u8 cos;
523224a3 911#endif
0155a27c 912 if (IS_PF(bp) && disable_int)
823e1d90 913 bnx2x_int_disable(bp);
a2fbb9ea 914
66e855f3 915 bp->stats_state = STATS_STATE_DISABLED;
7a752993 916 bp->eth_stats.unrecoverable_error++;
66e855f3
YG		 917 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
918
a2fbb9ea
ET		 919 BNX2X_ERR("begin crash dump -----------------\n");
920
8440d2b6
EG		 921 /* Indices */
922 /* Common */
0155a27c
YM		 923 if (IS_PF(bp)) {
924 struct host_sp_status_block *def_sb = bp->def_status_blk;
925 int data_size, cstorm_offset;
926
927 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
928 bp->def_idx, bp->def_att_idx, bp->attn_state,
929 bp->spq_prod_idx, bp->stats_counter);
930 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
931 def_sb->atten_status_block.attn_bits,
932 def_sb->atten_status_block.attn_bits_ack,
933 def_sb->atten_status_block.status_block_id,
934 def_sb->atten_status_block.attn_bits_index);
935 BNX2X_ERR(" def (");
936 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
937 pr_cont("0x%x%s",
938 def_sb->sp_sb.index_values[i],
939 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
940
941 data_size = sizeof(struct hc_sp_status_block_data) /
942 sizeof(u32);
943 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
944 for (i = 0; i < data_size; i++)
945 *((u32 *)&sp_sb_data + i) =
946 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
947 i * sizeof(u32));
948
949 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
950 sp_sb_data.igu_sb_id,
951 sp_sb_data.igu_seg_id,
952 sp_sb_data.p_func.pf_id,
953 sp_sb_data.p_func.vnic_id,
954 sp_sb_data.p_func.vf_id,
955 sp_sb_data.p_func.vf_valid,
956 sp_sb_data.state);
957 }
523224a3 958
ec6ba945 959 for_each_eth_queue(bp, i) {
a2fbb9ea 960 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 961 int loop;
f2e0899f 962 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 963 struct hc_status_block_data_e1x sb_data_e1x;
964 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 965 CHIP_IS_E1x(bp) ?
966 sb_data_e1x.common.state_machine :
967 sb_data_e2.common.state_machine;
523224a3 968 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 969 CHIP_IS_E1x(bp) ?
970 sb_data_e1x.index_data :
971 sb_data_e2.index_data;
6383c0b3 972 u8 data_size, cos;
523224a3 973 u32 *sb_data_p;
6383c0b3 974 struct bnx2x_fp_txdata txdata;
523224a3 975
e2611998
YM		 976 if (!bp->fp)
977 break;
978
979 if (!fp->rx_cons_sb)
980 continue;
981
523224a3 982 /* Rx */
51c1a580 983 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 984 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 985 fp->rx_comp_prod,
66e855f3 986 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
51c1a580 987 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
8440d2b6 988 fp->rx_sge_prod, fp->last_max_sge,
523224a3 989 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 990
523224a3 991 /* Tx */
6383c0b3
AE		 992 for_each_cos_in_tx_queue(fp, cos)
993 {
1fc3de94 994 if (!fp->txdata_ptr[cos])
e2611998
YM		 995 break;
996
65565884 997 txdata = *fp->txdata_ptr[cos];
e2611998
YM		 998
999 if (!txdata.tx_cons_sb)
1000 continue;
1001
51c1a580 1002 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
6383c0b3
AE		 1003 i, txdata.tx_pkt_prod,
1004 txdata.tx_pkt_cons, txdata.tx_bd_prod,
1005 txdata.tx_bd_cons,
1006 le16_to_cpu(*txdata.tx_cons_sb));
1007 }
523224a3 1008
619c5cb6
VZ		 1009 loop = CHIP_IS_E1x(bp) ?
1010 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 1011
1012 /* host sb data */
1013
ec6ba945
VZ		 1014 if (IS_FCOE_FP(fp))
1015 continue;
55c11941 1016
523224a3
DK		 1017 BNX2X_ERR(" run indexes (");
1018 for (j = 0; j < HC_SB_MAX_SM; j++)
1019 pr_cont("0x%x%s",
1020 fp->sb_running_index[j],
1021 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1022
1023 BNX2X_ERR(" indexes (");
1024 for (j = 0; j < loop; j++)
1025 pr_cont("0x%x%s",
1026 fp->sb_index_values[j],
1027 (j == loop - 1) ? ")" : " ");
0155a27c
YM		 1028
1029 /* VF cannot access FW refelection for status block */
1030 if (IS_VF(bp))
1031 continue;
1032
523224a3 1033 /* fw sb data */
619c5cb6
VZ		 1034 data_size = CHIP_IS_E1x(bp) ?
1035 sizeof(struct hc_status_block_data_e1x) :
1036 sizeof(struct hc_status_block_data_e2);
523224a3 1037 data_size /= sizeof(u32);
619c5cb6
VZ		 1038 sb_data_p = CHIP_IS_E1x(bp) ?
1039 (u32 *)&sb_data_e1x :
1040 (u32 *)&sb_data_e2;
523224a3
DK		 1041 /* copy sb data in here */
1042 for (j = 0; j < data_size; j++)
1043 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1044 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1045 j * sizeof(u32));
1046
619c5cb6 1047 if (!CHIP_IS_E1x(bp)) {
51c1a580 1048 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1049 sb_data_e2.common.p_func.pf_id,
1050 sb_data_e2.common.p_func.vf_id,
1051 sb_data_e2.common.p_func.vf_valid,
1052 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 1053 sb_data_e2.common.same_igu_sb_1b,
1054 sb_data_e2.common.state);
f2e0899f 1055 } else {
51c1a580 1056 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1057 sb_data_e1x.common.p_func.pf_id,
1058 sb_data_e1x.common.p_func.vf_id,
1059 sb_data_e1x.common.p_func.vf_valid,
1060 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 1061 sb_data_e1x.common.same_igu_sb_1b,
1062 sb_data_e1x.common.state);
f2e0899f 1063 }
523224a3
DK		 1064
1065 /* SB_SMs data */
1066 for (j = 0; j < HC_SB_MAX_SM; j++) {
51c1a580
MS		 1067 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1068 j, hc_sm_p[j].__flags,
1069 hc_sm_p[j].igu_sb_id,
1070 hc_sm_p[j].igu_seg_id,
1071 hc_sm_p[j].time_to_expire,
1072 hc_sm_p[j].timer_value);
523224a3
DK		 1073 }
1074
16a5fd92 1075 /* Indices data */
523224a3 1076 for (j = 0; j < loop; j++) {
51c1a580 1077 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
523224a3
DK		 1078 hc_index_p[j].flags,
1079 hc_index_p[j].timeout);
1080 }
8440d2b6 1081 }
a2fbb9ea 1082
523224a3 1083#ifdef BNX2X_STOP_ON_ERROR
0155a27c
YM		 1084 if (IS_PF(bp)) {
1085 /* event queue */
1086 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1087 for (i = 0; i < NUM_EQ_DESC; i++) {
1088 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1089
1090 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1091 i, bp->eq_ring[i].message.opcode,
1092 bp->eq_ring[i].message.error);
1093 BNX2X_ERR("data: %x %x %x\n",
1094 data[0], data[1], data[2]);
1095 }
04c46736
YM		 1096 }
1097
8440d2b6
EG		 1098 /* Rings */
1099 /* Rx */
55c11941 1100 for_each_valid_rx_queue(bp, i) {
8440d2b6 1101 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1102
e2611998
YM		 1103 if (!bp->fp)
1104 break;
1105
1106 if (!fp->rx_cons_sb)
1107 continue;
1108
a2fbb9ea
ET		 1109 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1110 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 1111 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 1112 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1113 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1114
c3eefaf6 1115 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
44151acb 1116 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
a2fbb9ea
ET		 1117 }
1118
3196a88a
EG		 1119 start = RX_SGE(fp->rx_sge_prod);
1120 end = RX_SGE(fp->last_max_sge);
8440d2b6 1121 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 1122 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1123 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1124
c3eefaf6
EG		 1125 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1126 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 1127 }
1128
a2fbb9ea
ET		 1129 start = RCQ_BD(fp->rx_comp_cons - 10);
1130 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 1131 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 1132 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1133
c3eefaf6
EG		 1134 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1135 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 1136 }
1137 }
1138
8440d2b6 1139 /* Tx */
55c11941 1140 for_each_valid_tx_queue(bp, i) {
8440d2b6 1141 struct bnx2x_fastpath *fp = &bp->fp[i];
e2611998
YM		 1142
1143 if (!bp->fp)
1144 break;
1145
6383c0b3 1146 for_each_cos_in_tx_queue(fp, cos) {
65565884 1147 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
6383c0b3 1148
1fc3de94 1149 if (!fp->txdata_ptr[cos])
e2611998
YM		 1150 break;
1151
ea36475a 1152 if (!txdata->tx_cons_sb)
e2611998
YM		 1153 continue;
1154
6383c0b3
AE		 1155 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1156 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1157 for (j = start; j != end; j = TX_BD(j + 1)) {
1158 struct sw_tx_bd *sw_bd =
1159 &txdata->tx_buf_ring[j];
1160
51c1a580 1161 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
6383c0b3
AE		 1162 i, cos, j, sw_bd->skb,
1163 sw_bd->first_bd);
1164 }
8440d2b6 1165
6383c0b3
AE		 1166 start = TX_BD(txdata->tx_bd_cons - 10);
1167 end = TX_BD(txdata->tx_bd_cons + 254);
1168 for (j = start; j != end; j = TX_BD(j + 1)) {
1169 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 1170
51c1a580 1171 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
6383c0b3
AE		 1172 i, cos, j, tx_bd[0], tx_bd[1],
1173 tx_bd[2], tx_bd[3]);
1174 }
8440d2b6
EG		 1175 }
1176 }
523224a3 1177#endif
0155a27c
YM		 1178 if (IS_PF(bp)) {
1179 bnx2x_fw_dump(bp);
1180 bnx2x_mc_assert(bp);
1181 }
a2fbb9ea 1182 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1183}
1184
619c5cb6
VZ		 1185/*
1186 * FLR Support for E2
1187 *
1188 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1189 * initialization.
1190 */
16a5fd92 1191#define FLR_WAIT_USEC 10000 /* 10 milliseconds */
89db4ad8
AE		 1192#define FLR_WAIT_INTERVAL 50 /* usec */
1193#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
619c5cb6
VZ		 1194
1195struct pbf_pN_buf_regs {
1196 int pN;
1197 u32 init_crd;
1198 u32 crd;
1199 u32 crd_freed;
1200};
1201
1202struct pbf_pN_cmd_regs {
1203 int pN;
1204 u32 lines_occup;
1205 u32 lines_freed;
1206};
1207
1208static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1209 struct pbf_pN_buf_regs *regs,
1210 u32 poll_count)
1211{
1212 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1213 u32 cur_cnt = poll_count;
1214
1215 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1216 crd = crd_start = REG_RD(bp, regs->crd);
1217 init_crd = REG_RD(bp, regs->init_crd);
1218
1219 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1220 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1221 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1222
1223 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1224 (init_crd - crd_start))) {
1225 if (cur_cnt--) {
89db4ad8 1226 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1227 crd = REG_RD(bp, regs->crd);
1228 crd_freed = REG_RD(bp, regs->crd_freed);
1229 } else {
1230 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1231 regs->pN);
1232 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1233 regs->pN, crd);
1234 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1235 regs->pN, crd_freed);
1236 break;
1237 }
1238 }
1239 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
89db4ad8 1240 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1241}
1242
1243static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1244 struct pbf_pN_cmd_regs *regs,
1245 u32 poll_count)
1246{
1247 u32 occup, to_free, freed, freed_start;
1248 u32 cur_cnt = poll_count;
1249
1250 occup = to_free = REG_RD(bp, regs->lines_occup);
1251 freed = freed_start = REG_RD(bp, regs->lines_freed);
1252
1253 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1254 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1255
1256 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1257 if (cur_cnt--) {
89db4ad8 1258 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1259 occup = REG_RD(bp, regs->lines_occup);
1260 freed = REG_RD(bp, regs->lines_freed);
1261 } else {
1262 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1263 regs->pN);
1264 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1265 regs->pN, occup);
1266 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1267 regs->pN, freed);
1268 break;
1269 }
1270 }
1271 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
89db4ad8 1272 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1273}
1274
1191cb83
ED		 1275static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1276 u32 expected, u32 poll_count)
619c5cb6
VZ		 1277{
1278 u32 cur_cnt = poll_count;
1279 u32 val;
1280
1281 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
89db4ad8 1282 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1283
1284 return val;
1285}
1286
d16132ce
AE		 1287int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1288 char *msg, u32 poll_cnt)
619c5cb6
VZ		 1289{
1290 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1291 if (val != 0) {
1292 BNX2X_ERR("%s usage count=%d\n", msg, val);
1293 return 1;
1294 }
1295 return 0;
1296}
1297
d16132ce
AE		 1298/* Common routines with VF FLR cleanup */
1299u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
619c5cb6
VZ		 1300{
1301 /* adjust polling timeout */
1302 if (CHIP_REV_IS_EMUL(bp))
1303 return FLR_POLL_CNT * 2000;
1304
1305 if (CHIP_REV_IS_FPGA(bp))
1306 return FLR_POLL_CNT * 120;
1307
1308 return FLR_POLL_CNT;
1309}
1310
d16132ce 1311void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
619c5cb6
VZ		 1312{
1313 struct pbf_pN_cmd_regs cmd_regs[] = {
1314 {0, (CHIP_IS_E3B0(bp)) ?
1315 PBF_REG_TQ_OCCUPANCY_Q0 :
1316 PBF_REG_P0_TQ_OCCUPANCY,
1317 (CHIP_IS_E3B0(bp)) ?
1318 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1319 PBF_REG_P0_TQ_LINES_FREED_CNT},
1320 {1, (CHIP_IS_E3B0(bp)) ?
1321 PBF_REG_TQ_OCCUPANCY_Q1 :
1322 PBF_REG_P1_TQ_OCCUPANCY,
1323 (CHIP_IS_E3B0(bp)) ?
1324 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1325 PBF_REG_P1_TQ_LINES_FREED_CNT},
1326 {4, (CHIP_IS_E3B0(bp)) ?
1327 PBF_REG_TQ_OCCUPANCY_LB_Q :
1328 PBF_REG_P4_TQ_OCCUPANCY,
1329 (CHIP_IS_E3B0(bp)) ?
1330 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1331 PBF_REG_P4_TQ_LINES_FREED_CNT}
1332 };
1333
1334 struct pbf_pN_buf_regs buf_regs[] = {
1335 {0, (CHIP_IS_E3B0(bp)) ?
1336 PBF_REG_INIT_CRD_Q0 :
1337 PBF_REG_P0_INIT_CRD ,
1338 (CHIP_IS_E3B0(bp)) ?
1339 PBF_REG_CREDIT_Q0 :
1340 PBF_REG_P0_CREDIT,
1341 (CHIP_IS_E3B0(bp)) ?
1342 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1343 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1344 {1, (CHIP_IS_E3B0(bp)) ?
1345 PBF_REG_INIT_CRD_Q1 :
1346 PBF_REG_P1_INIT_CRD,
1347 (CHIP_IS_E3B0(bp)) ?
1348 PBF_REG_CREDIT_Q1 :
1349 PBF_REG_P1_CREDIT,
1350 (CHIP_IS_E3B0(bp)) ?
1351 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1352 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1353 {4, (CHIP_IS_E3B0(bp)) ?
1354 PBF_REG_INIT_CRD_LB_Q :
1355 PBF_REG_P4_INIT_CRD,
1356 (CHIP_IS_E3B0(bp)) ?
1357 PBF_REG_CREDIT_LB_Q :
1358 PBF_REG_P4_CREDIT,
1359 (CHIP_IS_E3B0(bp)) ?
1360 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1361 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1362 };
1363
1364 int i;
1365
1366 /* Verify the command queues are flushed P0, P1, P4 */
1367 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1368 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1369
619c5cb6
VZ		 1370 /* Verify the transmission buffers are flushed P0, P1, P4 */
1371 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1372 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1373}
1374
1375#define OP_GEN_PARAM(param) \
1376 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1377
1378#define OP_GEN_TYPE(type) \
1379 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1380
1381#define OP_GEN_AGG_VECT(index) \
1382 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1383
d16132ce 1384int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
619c5cb6 1385{
86564c3f 1386 u32 op_gen_command = 0;
619c5cb6
VZ		 1387 u32 comp_addr = BAR_CSTRORM_INTMEM +
1388 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1389 int ret = 0;
1390
1391 if (REG_RD(bp, comp_addr)) {
89db4ad8 1392 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
619c5cb6
VZ		 1393 return 1;
1394 }
1395
86564c3f
YM		 1396 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1397 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1398 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1399 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
619c5cb6 1400
89db4ad8 1401 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
86564c3f 1402 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
619c5cb6
VZ		 1403
1404 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1405 BNX2X_ERR("FW final cleanup did not succeed\n");
51c1a580
MS		 1406 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1407 (REG_RD(bp, comp_addr)));
d16132ce
AE		 1408 bnx2x_panic();
1409 return 1;
619c5cb6 1410 }
16a5fd92 1411 /* Zero completion for next FLR */
619c5cb6
VZ		 1412 REG_WR(bp, comp_addr, 0);
1413
1414 return ret;
1415}
1416
b56e9670 1417u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
619c5cb6 1418{
619c5cb6
VZ		 1419 u16 status;
1420
2a80eebc 1421 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
619c5cb6
VZ		 1422 return status & PCI_EXP_DEVSTA_TRPND;
1423}
1424
1425/* PF FLR specific routines
1426*/
1427static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1428{
619c5cb6
VZ		 1429 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1430 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1431 CFC_REG_NUM_LCIDS_INSIDE_PF,
1432 "CFC PF usage counter timed out",
1433 poll_cnt))
1434 return 1;
1435
619c5cb6
VZ		 1436 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1437 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1438 DORQ_REG_PF_USAGE_CNT,
1439 "DQ PF usage counter timed out",
1440 poll_cnt))
1441 return 1;
1442
1443 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1444 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1445 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1446 "QM PF usage counter timed out",
1447 poll_cnt))
1448 return 1;
1449
1450 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1451 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1452 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1453 "Timers VNIC usage counter timed out",
1454 poll_cnt))
1455 return 1;
1456 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1457 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1458 "Timers NUM_SCANS usage counter timed out",
1459 poll_cnt))
1460 return 1;
1461
1462 /* Wait DMAE PF usage counter to zero */
1463 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1464 dmae_reg_go_c[INIT_DMAE_C(bp)],
6bf07b8e 1465 "DMAE command register timed out",
619c5cb6
VZ		 1466 poll_cnt))
1467 return 1;
1468
1469 return 0;
1470}
1471
1472static void bnx2x_hw_enable_status(struct bnx2x *bp)
1473{
1474 u32 val;
1475
1476 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1477 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1478
1479 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1480 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1481
1482 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1483 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1484
1485 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1486 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1487
1488 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1489 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1490
1491 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1492 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1493
1494 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1495 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1496
1497 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1498 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1499 val);
1500}
1501
1502static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1503{
1504 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1505
1506 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1507
1508 /* Re-enable PF target read access */
1509 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1510
1511 /* Poll HW usage counters */
89db4ad8 1512 DP(BNX2X_MSG_SP, "Polling usage counters\n");
619c5cb6
VZ		 1513 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1514 return -EBUSY;
1515
1516 /* Zero the igu 'trailing edge' and 'leading edge' */
1517
1518 /* Send the FW cleanup command */
1519 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1520 return -EBUSY;
1521
1522 /* ATC cleanup */
1523
1524 /* Verify TX hw is flushed */
1525 bnx2x_tx_hw_flushed(bp, poll_cnt);
1526
1527 /* Wait 100ms (not adjusted according to platform) */
1528 msleep(100);
1529
1530 /* Verify no pending pci transactions */
1531 if (bnx2x_is_pcie_pending(bp->pdev))
1532 BNX2X_ERR("PCIE Transactions still pending\n");
1533
1534 /* Debug */
1535 bnx2x_hw_enable_status(bp);
1536
1537 /*
1538 * Master enable - Due to WB DMAE writes performed before this
1539 * register is re-initialized as part of the regular function init
1540 */
1541 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1542
1543 return 0;
1544}
1545
f2e0899f 1546static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1547{
34f80b04 1548 int port = BP_PORT(bp);
a2fbb9ea
ET		 1549 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1550 u32 val = REG_RD(bp, addr);
69c326b3
DK		 1551 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1552 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1553 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
a2fbb9ea
ET		 1554
1555 if (msix) {
8badd27a
EG		 1556 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1557 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1558 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1559 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
69c326b3
DK		 1560 if (single_msix)
1561 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
8badd27a
EG		 1562 } else if (msi) {
1563 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1564 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1565 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1566 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1567 } else {
1568 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1569 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1570 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1571 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1572
a0fd065c 1573 if (!CHIP_IS_E1(bp)) {
51c1a580
MS		 1574 DP(NETIF_MSG_IFUP,
1575 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
615f8fd9 1576
a0fd065c 1577 REG_WR(bp, addr, val);
615f8fd9 1578
a0fd065c
DK		 1579 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1580 }
a2fbb9ea
ET		 1581 }
1582
a0fd065c
DK		 1583 if (CHIP_IS_E1(bp))
1584 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1585
51c1a580
MS		 1586 DP(NETIF_MSG_IFUP,
1587 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1588 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1589
1590 REG_WR(bp, addr, val);
37dbbf32
EG		 1591 /*
1592 * Ensure that HC_CONFIG is written before leading/trailing edge config
1593 */
1594 mmiowb();
1595 barrier();
34f80b04 1596
f2e0899f 1597 if (!CHIP_IS_E1(bp)) {
34f80b04 1598 /* init leading/trailing edge */
fb3bff17 1599 if (IS_MF(bp)) {
3395a033 1600 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1601 if (bp->port.pmf)
4acac6a5
EG		 1602 /* enable nig and gpio3 attention */
1603 val |= 0x1100;
34f80b04
EG		 1604 } else
1605 val = 0xffff;
1606
1607 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1608 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1609 }
37dbbf32
EG		 1610
1611 /* Make sure that interrupts are indeed enabled from here on */
1612 mmiowb();
a2fbb9ea
ET		 1613}
1614
f2e0899f
DK		 1615static void bnx2x_igu_int_enable(struct bnx2x *bp)
1616{
1617 u32 val;
30a5de77
DK		 1618 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1619 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1620 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
f2e0899f
DK		 1621
1622 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1623
1624 if (msix) {
1625 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1626 IGU_PF_CONF_SINGLE_ISR_EN);
ebe61d80 1627 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f 1628 IGU_PF_CONF_ATTN_BIT_EN);
30a5de77
DK		 1629
1630 if (single_msix)
1631 val |= IGU_PF_CONF_SINGLE_ISR_EN;
f2e0899f
DK		 1632 } else if (msi) {
1633 val &= ~IGU_PF_CONF_INT_LINE_EN;
ebe61d80 1634 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f
DK		 1635 IGU_PF_CONF_ATTN_BIT_EN |
1636 IGU_PF_CONF_SINGLE_ISR_EN);
1637 } else {
1638 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
ebe61d80 1639 val |= (IGU_PF_CONF_INT_LINE_EN |
f2e0899f
DK		 1640 IGU_PF_CONF_ATTN_BIT_EN |
1641 IGU_PF_CONF_SINGLE_ISR_EN);
1642 }
1643
ebe61d80
YM		 1644 /* Clean previous status - need to configure igu prior to ack*/
1645 if ((!msix) || single_msix) {
1646 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1647 bnx2x_ack_int(bp);
1648 }
1649
1650 val |= IGU_PF_CONF_FUNC_EN;
1651
51c1a580 1652 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
f2e0899f
DK		 1653 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1654
1655 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1656
79a8557a
YM		 1657 if (val & IGU_PF_CONF_INT_LINE_EN)
1658 pci_intx(bp->pdev, true);
1659
f2e0899f
DK		 1660 barrier();
1661
1662 /* init leading/trailing edge */
1663 if (IS_MF(bp)) {
3395a033 1664 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1665 if (bp->port.pmf)
1666 /* enable nig and gpio3 attention */
1667 val |= 0x1100;
1668 } else
1669 val = 0xffff;
1670
1671 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1672 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1673
1674 /* Make sure that interrupts are indeed enabled from here on */
1675 mmiowb();
1676}
1677
1678void bnx2x_int_enable(struct bnx2x *bp)
1679{
1680 if (bp->common.int_block == INT_BLOCK_HC)
1681 bnx2x_hc_int_enable(bp);
1682 else
1683 bnx2x_igu_int_enable(bp);
1684}
1685
9f6c9258 1686void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1687{
a2fbb9ea 1688 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1689 int i, offset;
a2fbb9ea 1690
f8ef6e44
YG		 1691 if (disable_hw)
1692 /* prevent the HW from sending interrupts */
1693 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1694
1695 /* make sure all ISRs are done */
1696 if (msix) {
8badd27a
EG		 1697 synchronize_irq(bp->msix_table[0].vector);
1698 offset = 1;
55c11941
MS		 1699 if (CNIC_SUPPORT(bp))
1700 offset++;
ec6ba945 1701 for_each_eth_queue(bp, i)
754a2f52 1702 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1703 } else
1704 synchronize_irq(bp->pdev->irq);
1705
1706 /* make sure sp_task is not running */
1cf167f2 1707 cancel_delayed_work(&bp->sp_task);
3deb8167 1708 cancel_delayed_work(&bp->period_task);
1cf167f2 1709 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1710}
1711
34f80b04 1712/* fast path */
a2fbb9ea
ET		 1713
1714/*
34f80b04 1715 * General service functions
a2fbb9ea
ET		 1716 */
1717
72fd0718
VZ		 1718/* Return true if succeeded to acquire the lock */
1719static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1720{
1721 u32 lock_status;
1722 u32 resource_bit = (1 << resource);
1723 int func = BP_FUNC(bp);
1724 u32 hw_lock_control_reg;
1725
51c1a580
MS		 1726 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1727 "Trying to take a lock on resource %d\n", resource);
72fd0718
VZ		 1728
1729 /* Validating that the resource is within range */
1730 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1731 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
72fd0718
VZ		 1732 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1733 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1734 return false;
72fd0718
VZ		 1735 }
1736
1737 if (func <= 5)
1738 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1739 else
1740 hw_lock_control_reg =
1741 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1742
1743 /* Try to acquire the lock */
1744 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1745 lock_status = REG_RD(bp, hw_lock_control_reg);
1746 if (lock_status & resource_bit)
1747 return true;
1748
51c1a580
MS		 1749 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1750 "Failed to get a lock on resource %d\n", resource);
72fd0718
VZ		 1751 return false;
1752}
1753
c9ee9206
VZ		 1754/**
1755 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1756 *
1757 * @bp: driver handle
1758 *
1759 * Returns the recovery leader resource id according to the engine this function
1760 * belongs to. Currently only only 2 engines is supported.
1761 */
1191cb83 1762static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
c9ee9206
VZ		 1763{
1764 if (BP_PATH(bp))
1765 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1766 else
1767 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1768}
1769
1770/**
2de67439 1771 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
c9ee9206
VZ		 1772 *
1773 * @bp: driver handle
1774 *
2de67439 1775 * Tries to acquire a leader lock for current engine.
c9ee9206 1776 */
1191cb83 1777static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
c9ee9206
VZ		 1778{
1779 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1780}
1781
619c5cb6 1782static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
55c11941 1783
fd1fc79d
AE		 1784/* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1785static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1786{
1787 /* Set the interrupt occurred bit for the sp-task to recognize it
1788 * must ack the interrupt and transition according to the IGU
1789 * state machine.
1790 */
1791 atomic_set(&bp->interrupt_occurred, 1);
1792
1793 /* The sp_task must execute only after this bit
1794 * is set, otherwise we will get out of sync and miss all
1795 * further interrupts. Hence, the barrier.
1796 */
1797 smp_wmb();
1798
1799 /* schedule sp_task to workqueue */
1800 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1801}
3196a88a 1802
619c5cb6 1803void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1804{
1805 struct bnx2x *bp = fp->bp;
1806 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1807 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6 1808 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
15192a8c 1809 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a2fbb9ea 1810
34f80b04 1811 DP(BNX2X_MSG_SP,
a2fbb9ea 1812 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1813 fp->index, cid, command, bp->state,
34f80b04 1814 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1815
fd1fc79d
AE		 1816 /* If cid is within VF range, replace the slowpath object with the
1817 * one corresponding to this VF
1818 */
1819 if (cid >= BNX2X_FIRST_VF_CID &&
1820 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1821 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1822
619c5cb6
VZ		 1823 switch (command) {
1824 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1825 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1826 drv_cmd = BNX2X_Q_CMD_UPDATE;
1827 break;
d6cae238 1828
619c5cb6 1829 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1830 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1831 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1832 break;
1833
6383c0b3 1834 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
51c1a580 1835 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
6383c0b3
AE		 1836 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1837 break;
1838
619c5cb6 1839 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1840 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1841 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1842 break;
1843
619c5cb6 1844 case (RAMROD_CMD_ID_ETH_TERMINATE):
6bf07b8e 1845 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
619c5cb6 1846 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1847 break;
1848
619c5cb6 1849 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1850 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1851 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1852 break;
619c5cb6 1853
14a94ebd
MK		 1854 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1855 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1856 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1857 break;
1858
619c5cb6
VZ		 1859 default:
1860 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1861 command, fp->index);
1862 return;
523224a3 1863 }
3196a88a 1864
619c5cb6
VZ		 1865 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1866 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1867 /* q_obj->complete_cmd() failure means that this was
1868 * an unexpected completion.
1869 *
1870 * In this case we don't want to increase the bp->spq_left
1871 * because apparently we haven't sent this command the first
1872 * place.
1873 */
1874#ifdef BNX2X_STOP_ON_ERROR
1875 bnx2x_panic();
1876#else
1877 return;
1878#endif
1879
4e857c58 1880 smp_mb__before_atomic();
6e30dd4e 1881 atomic_inc(&bp->cq_spq_left);
619c5cb6 1882 /* push the change in bp->spq_left and towards the memory */
4e857c58 1883 smp_mb__after_atomic();
49d66772 1884
d6cae238
VZ		 1885 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1886
a3348722
BW		 1887 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1888 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1889 /* if Q update ramrod is completed for last Q in AFEX vif set
1890 * flow, then ACK MCP at the end
1891 *
1892 * mark pending ACK to MCP bit.
1893 * prevent case that both bits are cleared.
1894 * At the end of load/unload driver checks that
2de67439 1895 * sp_state is cleared, and this order prevents
a3348722
BW		 1896 * races
1897 */
4e857c58 1898 smp_mb__before_atomic();
a3348722
BW		 1899 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1900 wmb();
1901 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4e857c58 1902 smp_mb__after_atomic();
a3348722 1903
fd1fc79d
AE		 1904 /* schedule the sp task as mcp ack is required */
1905 bnx2x_schedule_sp_task(bp);
a3348722
BW		 1906 }
1907
523224a3 1908 return;
a2fbb9ea
ET		 1909}
1910
9f6c9258 1911irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1912{
555f6c78 1913 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1914 u16 status = bnx2x_ack_int(bp);
34f80b04 1915 u16 mask;
ca00392c 1916 int i;
6383c0b3 1917 u8 cos;
a2fbb9ea 1918
34f80b04 1919 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1920 if (unlikely(status == 0)) {
1921 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1922 return IRQ_NONE;
1923 }
f5372251 1924 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1925
3196a88a
EG		 1926#ifdef BNX2X_STOP_ON_ERROR
1927 if (unlikely(bp->panic))
1928 return IRQ_HANDLED;
1929#endif
1930
ec6ba945 1931 for_each_eth_queue(bp, i) {
ca00392c 1932 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1933
55c11941 1934 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
ca00392c 1935 if (status & mask) {
619c5cb6 1936 /* Handle Rx or Tx according to SB id */
6383c0b3 1937 for_each_cos_in_tx_queue(fp, cos)
65565884 1938 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
523224a3 1939 prefetch(&fp->sb_running_index[SM_RX_ID]);
f5fbf115 1940 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1941 status &= ~mask;
1942 }
a2fbb9ea
ET		 1943 }
1944
55c11941
MS		 1945 if (CNIC_SUPPORT(bp)) {
1946 mask = 0x2;
1947 if (status & (mask | 0x1)) {
1948 struct cnic_ops *c_ops = NULL;
993ac7b5 1949
ad9b4359
MC		 1950 rcu_read_lock();
1951 c_ops = rcu_dereference(bp->cnic_ops);
1952 if (c_ops && (bp->cnic_eth_dev.drv_state &
1953 CNIC_DRV_STATE_HANDLES_IRQ))
1954 c_ops->cnic_handler(bp->cnic_data, NULL);
1955 rcu_read_unlock();
993ac7b5 1956
55c11941
MS		 1957 status &= ~mask;
1958 }
993ac7b5 1959 }
a2fbb9ea 1960
34f80b04 1961 if (unlikely(status & 0x1)) {
fd1fc79d
AE		 1962
1963 /* schedule sp task to perform default status block work, ack
1964 * attentions and enable interrupts.
1965 */
1966 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 1967
1968 status &= ~0x1;
1969 if (!status)
1970 return IRQ_HANDLED;
1971 }
1972
cdaa7cb8
VZ		 1973 if (unlikely(status))
1974 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1975 status);
a2fbb9ea 1976
c18487ee 1977 return IRQ_HANDLED;
a2fbb9ea
ET		 1978}
1979
c18487ee
YR		 1980/* Link */
1981
1982/*
1983 * General service functions
1984 */
a2fbb9ea 1985
9f6c9258 1986int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1987{
1988 u32 lock_status;
1989 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1990 int func = BP_FUNC(bp);
1991 u32 hw_lock_control_reg;
c18487ee 1992 int cnt;
a2fbb9ea 1993
c18487ee
YR		 1994 /* Validating that the resource is within range */
1995 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1996 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 1997 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1998 return -EINVAL;
1999 }
a2fbb9ea 2000
4a37fb66
YG		 2001 if (func <= 5) {
2002 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2003 } else {
2004 hw_lock_control_reg =
2005 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2006 }
2007
c18487ee 2008 /* Validating that the resource is not already taken */
4a37fb66 2009 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2010 if (lock_status & resource_bit) {
51c1a580 2011 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
c18487ee
YR		 2012 lock_status, resource_bit);
2013 return -EEXIST;
2014 }
a2fbb9ea 2015
46230476
EG		 2016 /* Try for 5 second every 5ms */
2017 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 2018 /* Try to acquire the lock */
4a37fb66
YG		 2019 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2020 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 2021 if (lock_status & resource_bit)
2022 return 0;
a2fbb9ea 2023
639d65b8 2024 usleep_range(5000, 10000);
a2fbb9ea 2025 }
51c1a580 2026 BNX2X_ERR("Timeout\n");
c18487ee
YR		 2027 return -EAGAIN;
2028}
a2fbb9ea 2029
c9ee9206
VZ		 2030int bnx2x_release_leader_lock(struct bnx2x *bp)
2031{
2032 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2033}
2034
9f6c9258 2035int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 2036{
2037 u32 lock_status;
2038 u32 resource_bit = (1 << resource);
4a37fb66
YG		 2039 int func = BP_FUNC(bp);
2040 u32 hw_lock_control_reg;
a2fbb9ea 2041
c18487ee
YR		 2042 /* Validating that the resource is within range */
2043 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 2044 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 2045 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2046 return -EINVAL;
2047 }
2048
4a37fb66
YG		 2049 if (func <= 5) {
2050 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2051 } else {
2052 hw_lock_control_reg =
2053 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2054 }
2055
c18487ee 2056 /* Validating that the resource is currently taken */
4a37fb66 2057 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2058 if (!(lock_status & resource_bit)) {
6bf07b8e
YM		 2059 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2060 lock_status, resource_bit);
c18487ee 2061 return -EFAULT;
a2fbb9ea
ET		 2062 }
2063
9f6c9258
DK		 2064 REG_WR(bp, hw_lock_control_reg, resource_bit);
2065 return 0;
c18487ee 2066}
a2fbb9ea 2067
4acac6a5
EG		 2068int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2069{
2070 /* The GPIO should be swapped if swap register is set and active */
2071 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2072 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2073 int gpio_shift = gpio_num +
2074 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2075 u32 gpio_mask = (1 << gpio_shift);
2076 u32 gpio_reg;
2077 int value;
2078
2079 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2080 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2081 return -EINVAL;
2082 }
2083
2084 /* read GPIO value */
2085 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2086
2087 /* get the requested pin value */
2088 if ((gpio_reg & gpio_mask) == gpio_mask)
2089 value = 1;
2090 else
2091 value = 0;
2092
4acac6a5
EG		 2093 return value;
2094}
2095
17de50b7 2096int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 2097{
2098 /* The GPIO should be swapped if swap register is set and active */
2099 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 2100 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 2101 int gpio_shift = gpio_num +
2102 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2103 u32 gpio_mask = (1 << gpio_shift);
2104 u32 gpio_reg;
a2fbb9ea 2105
c18487ee
YR		 2106 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2107 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2108 return -EINVAL;
2109 }
a2fbb9ea 2110
4a37fb66 2111 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 2112 /* read GPIO and mask except the float bits */
2113 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 2114
c18487ee
YR		 2115 switch (mode) {
2116 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
51c1a580
MS		 2117 DP(NETIF_MSG_LINK,
2118 "Set GPIO %d (shift %d) -> output low\n",
c18487ee
YR		 2119 gpio_num, gpio_shift);
2120 /* clear FLOAT and set CLR */
2121 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2122 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2123 break;
a2fbb9ea 2124
c18487ee 2125 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
51c1a580
MS		 2126 DP(NETIF_MSG_LINK,
2127 "Set GPIO %d (shift %d) -> output high\n",
c18487ee
YR		 2128 gpio_num, gpio_shift);
2129 /* clear FLOAT and set SET */
2130 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2131 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2132 break;
a2fbb9ea 2133
17de50b7 2134 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
51c1a580
MS		 2135 DP(NETIF_MSG_LINK,
2136 "Set GPIO %d (shift %d) -> input\n",
c18487ee
YR		 2137 gpio_num, gpio_shift);
2138 /* set FLOAT */
2139 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2140 break;
a2fbb9ea 2141
c18487ee
YR		 2142 default:
2143 break;
a2fbb9ea
ET		 2144 }
2145
c18487ee 2146 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 2147 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 2148
c18487ee 2149 return 0;
a2fbb9ea
ET		 2150}
2151
0d40f0d4
YR		 2152int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2153{
2154 u32 gpio_reg = 0;
2155 int rc = 0;
2156
2157 /* Any port swapping should be handled by caller. */
2158
2159 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2160 /* read GPIO and mask except the float bits */
2161 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2162 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2163 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2164 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2165
2166 switch (mode) {
2167 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2168 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2169 /* set CLR */
2170 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2171 break;
2172
2173 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2174 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2175 /* set SET */
2176 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2177 break;
2178
2179 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2180 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2181 /* set FLOAT */
2182 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2183 break;
2184
2185 default:
2186 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2187 rc = -EINVAL;
2188 break;
2189 }
2190
2191 if (rc == 0)
2192 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2193
2194 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2195
2196 return rc;
2197}
2198
4acac6a5
EG		 2199int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2200{
2201 /* The GPIO should be swapped if swap register is set and active */
2202 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2203 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2204 int gpio_shift = gpio_num +
2205 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2206 u32 gpio_mask = (1 << gpio_shift);
2207 u32 gpio_reg;
2208
2209 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2210 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2211 return -EINVAL;
2212 }
2213
2214 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2215 /* read GPIO int */
2216 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2217
2218 switch (mode) {
2219 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
51c1a580
MS		 2220 DP(NETIF_MSG_LINK,
2221 "Clear GPIO INT %d (shift %d) -> output low\n",
2222 gpio_num, gpio_shift);
4acac6a5
EG		 2223 /* clear SET and set CLR */
2224 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2225 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2226 break;
2227
2228 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
51c1a580
MS		 2229 DP(NETIF_MSG_LINK,
2230 "Set GPIO INT %d (shift %d) -> output high\n",
2231 gpio_num, gpio_shift);
4acac6a5
EG		 2232 /* clear CLR and set SET */
2233 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2234 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2235 break;
2236
2237 default:
2238 break;
2239 }
2240
2241 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2242 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2243
2244 return 0;
2245}
2246
d6d99a3f 2247static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
a2fbb9ea 2248{
c18487ee 2249 u32 spio_reg;
a2fbb9ea 2250
d6d99a3f
YM		 2251 /* Only 2 SPIOs are configurable */
2252 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2253 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
c18487ee 2254 return -EINVAL;
a2fbb9ea
ET		 2255 }
2256
4a37fb66 2257 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2258 /* read SPIO and mask except the float bits */
d6d99a3f 2259 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
a2fbb9ea 2260
c18487ee 2261 switch (mode) {
d6d99a3f
YM		 2262 case MISC_SPIO_OUTPUT_LOW:
2263 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
c18487ee 2264 /* clear FLOAT and set CLR */
d6d99a3f
YM		 2265 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2266 spio_reg |= (spio << MISC_SPIO_CLR_POS);
c18487ee 2267 break;
a2fbb9ea 2268
d6d99a3f
YM		 2269 case MISC_SPIO_OUTPUT_HIGH:
2270 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
c18487ee 2271 /* clear FLOAT and set SET */
d6d99a3f
YM		 2272 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2273 spio_reg |= (spio << MISC_SPIO_SET_POS);
c18487ee 2274 break;
a2fbb9ea 2275
d6d99a3f
YM		 2276 case MISC_SPIO_INPUT_HI_Z:
2277 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
c18487ee 2278 /* set FLOAT */
d6d99a3f 2279 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
c18487ee 2280 break;
a2fbb9ea 2281
c18487ee
YR		 2282 default:
2283 break;
a2fbb9ea
ET		 2284 }
2285
c18487ee 2286 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2287 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2288
a2fbb9ea
ET		 2289 return 0;
2290}
2291
9f6c9258 2292void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2293{
a22f0788 2294 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1359d73c
YM		 2295
2296 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2297 ADVERTISED_Pause);
ad33ea3a
EG		 2298 switch (bp->link_vars.ieee_fc &
2299 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2300 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2301 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2302 ADVERTISED_Pause);
c18487ee 2303 break;
356e2385 2304
c18487ee 2305 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2306 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2307 break;
356e2385 2308
c18487ee 2309 default:
c18487ee
YR		 2310 break;
2311 }
2312}
f1410647 2313
cd1dfce2 2314static void bnx2x_set_requested_fc(struct bnx2x *bp)
c18487ee 2315{
cd1dfce2
YM		 2316 /* Initialize link parameters structure variables
2317 * It is recommended to turn off RX FC for jumbo frames
2318 * for better performance
2319 */
2320 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2321 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2322 else
2323 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2324}
a2fbb9ea 2325
9156b30b
DK		 2326static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2327{
2328 u32 pause_enabled = 0;
2329
2330 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2331 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2332 pause_enabled = 1;
2333
2334 REG_WR(bp, BAR_USTRORM_INTMEM +
2335 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2336 pause_enabled);
2337 }
2338
2339 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2340 pause_enabled ? "enabled" : "disabled");
2341}
2342
cd1dfce2
YM		 2343int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2344{
2345 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2346 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2347
2348 if (!BP_NOMCP(bp)) {
2349 bnx2x_set_requested_fc(bp);
4a37fb66 2350 bnx2x_acquire_phy_lock(bp);
b5bf9068 2351
a22f0788 2352 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2353 struct link_params *lp = &bp->link_params;
2354 lp->loopback_mode = LOOPBACK_XGXS;
2f43b821
YM		 2355 /* Prefer doing PHY loopback at highest speed */
2356 if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
1cb0c788 2357 if (lp->speed_cap_mask[cfx_idx] &
2f43b821 2358 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
1cb0c788 2359 lp->req_line_speed[cfx_idx] =
2f43b821
YM		 2360 SPEED_20000;
2361 else if (lp->speed_cap_mask[cfx_idx] &
2362 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2363 lp->req_line_speed[cfx_idx] =
2364 SPEED_10000;
1cb0c788
YR		 2365 else
2366 lp->req_line_speed[cfx_idx] =
2367 SPEED_1000;
2368 }
a22f0788 2369 }
b5bf9068 2370
8970b2e4
MS		 2371 if (load_mode == LOAD_LOOPBACK_EXT) {
2372 struct link_params *lp = &bp->link_params;
2373 lp->loopback_mode = LOOPBACK_EXT;
2374 }
2375
19680c48 2376 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2377
4a37fb66 2378 bnx2x_release_phy_lock(bp);
a2fbb9ea 2379
9156b30b
DK		 2380 bnx2x_init_dropless_fc(bp);
2381
3c96c68b
EG		 2382 bnx2x_calc_fc_adv(bp);
2383
cd1dfce2 2384 if (bp->link_vars.link_up) {
b5bf9068 2385 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2386 bnx2x_link_report(bp);
cd1dfce2
YM		 2387 }
2388 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2389 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2390 return rc;
2391 }
f5372251 2392 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2393 return -EINVAL;
a2fbb9ea
ET		 2394}
2395
9f6c9258 2396void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2397{
19680c48 2398 if (!BP_NOMCP(bp)) {
4a37fb66 2399 bnx2x_acquire_phy_lock(bp);
19680c48 2400 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2401 bnx2x_release_phy_lock(bp);
a2fbb9ea 2402
9156b30b
DK		 2403 bnx2x_init_dropless_fc(bp);
2404
19680c48
EG		 2405 bnx2x_calc_fc_adv(bp);
2406 } else
f5372251 2407 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2408}
a2fbb9ea 2409
c18487ee
YR		 2410static void bnx2x__link_reset(struct bnx2x *bp)
2411{
19680c48 2412 if (!BP_NOMCP(bp)) {
4a37fb66 2413 bnx2x_acquire_phy_lock(bp);
5d07d868 2414 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
4a37fb66 2415 bnx2x_release_phy_lock(bp);
19680c48 2416 } else
f5372251 2417 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2418}
a2fbb9ea 2419
5d07d868
YM		 2420void bnx2x_force_link_reset(struct bnx2x *bp)
2421{
2422 bnx2x_acquire_phy_lock(bp);
2423 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2424 bnx2x_release_phy_lock(bp);
2425}
2426
a22f0788 2427u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2428{
2145a920 2429 u8 rc = 0;
a2fbb9ea 2430
2145a920
VZ		 2431 if (!BP_NOMCP(bp)) {
2432 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2433 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2434 is_serdes);
2145a920
VZ		 2435 bnx2x_release_phy_lock(bp);
2436 } else
2437 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2438
c18487ee
YR		 2439 return rc;
2440}
a2fbb9ea 2441
2691d51d
EG		 2442/* Calculates the sum of vn_min_rates.
2443 It's needed for further normalizing of the min_rates.
2444 Returns:
2445 sum of vn_min_rates.
2446 or
2447 0 - if all the min_rates are 0.
16a5fd92 2448 In the later case fairness algorithm should be deactivated.
2691d51d
EG		 2449 If not all min_rates are zero then those that are zeroes will be set to 1.
2450 */
b475d78f
YM		 2451static void bnx2x_calc_vn_min(struct bnx2x *bp,
2452 struct cmng_init_input *input)
2691d51d
EG		 2453{
2454 int all_zero = 1;
2691d51d
EG		 2455 int vn;
2456
3395a033 2457 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2458 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2459 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2460 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2461
2462 /* Skip hidden vns */
2463 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
b475d78f 2464 vn_min_rate = 0;
2691d51d 2465 /* If min rate is zero - set it to 1 */
b475d78f 2466 else if (!vn_min_rate)
2691d51d
EG		 2467 vn_min_rate = DEF_MIN_RATE;
2468 else
2469 all_zero = 0;
2470
b475d78f 2471 input->vnic_min_rate[vn] = vn_min_rate;
2691d51d
EG		 2472 }
2473
30ae438b
DK		 2474 /* if ETS or all min rates are zeros - disable fairness */
2475 if (BNX2X_IS_ETS_ENABLED(bp)) {
b475d78f 2476 input->flags.cmng_enables &=
30ae438b
DK		 2477 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2478 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2479 } else if (all_zero) {
b475d78f 2480 input->flags.cmng_enables &=
b015e3d1 2481 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
b475d78f
YM		 2482 DP(NETIF_MSG_IFUP,
2483 "All MIN values are zeroes fairness will be disabled\n");
b015e3d1 2484 } else
b475d78f 2485 input->flags.cmng_enables |=
b015e3d1 2486 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2487}
2488
b475d78f
YM		 2489static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2490 struct cmng_init_input *input)
34f80b04 2491{
b475d78f 2492 u16 vn_max_rate;
f2e0899f 2493 u32 vn_cfg = bp->mf_config[vn];
34f80b04 2494
b475d78f 2495 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
34f80b04 2496 vn_max_rate = 0;
b475d78f 2497 else {
faa6fcbb
DK		 2498 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2499
da3cc2da 2500 if (IS_MF_PERCENT_BW(bp)) {
faa6fcbb
DK		 2501 /* maxCfg in percents of linkspeed */
2502 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
b475d78f 2503 } else /* SD modes */
faa6fcbb
DK		 2504 /* maxCfg is absolute in 100Mb units */
2505 vn_max_rate = maxCfg * 100;
34f80b04 2506 }
f85582f8 2507
b475d78f 2508 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
34f80b04 2509
b475d78f 2510 input->vnic_max_rate[vn] = vn_max_rate;
34f80b04 2511}
f85582f8 2512
523224a3
DK		 2513static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2514{
2515 if (CHIP_REV_IS_SLOW(bp))
2516 return CMNG_FNS_NONE;
fb3bff17 2517 if (IS_MF(bp))
523224a3
DK		 2518 return CMNG_FNS_MINMAX;
2519
2520 return CMNG_FNS_NONE;
2521}
2522
2ae17f66 2523void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2524{
0793f83f 2525 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2526
2527 if (BP_NOMCP(bp))
16a5fd92 2528 return; /* what should be the default value in this case */
523224a3 2529
0793f83f
DK		 2530 /* For 2 port configuration the absolute function number formula
2531 * is:
2532 * abs_func = 2 * vn + BP_PORT + BP_PATH
2533 *
2534 * and there are 4 functions per port
2535 *
2536 * For 4 port configuration it is
2537 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2538 *
2539 * and there are 2 functions per port
2540 */
3395a033 2541 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2542 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2543
2544 if (func >= E1H_FUNC_MAX)
2545 break;
2546
f2e0899f 2547 bp->mf_config[vn] =
523224a3
DK		 2548 MF_CFG_RD(bp, func_mf_config[func].config);
2549 }
a3348722
BW		 2550 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2551 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2552 bp->flags |= MF_FUNC_DIS;
2553 } else {
2554 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2555 bp->flags &= ~MF_FUNC_DIS;
2556 }
523224a3
DK		 2557}
2558
2559static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2560{
b475d78f
YM		 2561 struct cmng_init_input input;
2562 memset(&input, 0, sizeof(struct cmng_init_input));
2563
2564 input.port_rate = bp->link_vars.line_speed;
523224a3 2565
568e2426 2566 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
523224a3
DK		 2567 int vn;
2568
523224a3
DK		 2569 /* read mf conf from shmem */
2570 if (read_cfg)
2571 bnx2x_read_mf_cfg(bp);
2572
523224a3 2573 /* vn_weight_sum and enable fairness if not 0 */
b475d78f 2574 bnx2x_calc_vn_min(bp, &input);
523224a3
DK		 2575
2576 /* calculate and set min-max rate for each vn */
c4154f25 2577 if (bp->port.pmf)
3395a033 2578 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
b475d78f 2579 bnx2x_calc_vn_max(bp, vn, &input);
523224a3
DK		 2580
2581 /* always enable rate shaping and fairness */
b475d78f 2582 input.flags.cmng_enables |=
523224a3 2583 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
b475d78f
YM		 2584
2585 bnx2x_init_cmng(&input, &bp->cmng);
523224a3
DK		 2586 return;
2587 }
2588
2589 /* rate shaping and fairness are disabled */
2590 DP(NETIF_MSG_IFUP,
2591 "rate shaping and fairness are disabled\n");
2592}
34f80b04 2593
1191cb83
ED		 2594static void storm_memset_cmng(struct bnx2x *bp,
2595 struct cmng_init *cmng,
2596 u8 port)
2597{
2598 int vn;
2599 size_t size = sizeof(struct cmng_struct_per_port);
2600
2601 u32 addr = BAR_XSTRORM_INTMEM +
2602 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2603
2604 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2605
2606 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2607 int func = func_by_vn(bp, vn);
2608
2609 addr = BAR_XSTRORM_INTMEM +
2610 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2611 size = sizeof(struct rate_shaping_vars_per_vn);
2612 __storm_memset_struct(bp, addr, size,
2613 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2614
2615 addr = BAR_XSTRORM_INTMEM +
2616 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2617 size = sizeof(struct fairness_vars_per_vn);
2618 __storm_memset_struct(bp, addr, size,
2619 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2620 }
2621}
2622
568e2426
DK		 2623/* init cmng mode in HW according to local configuration */
2624void bnx2x_set_local_cmng(struct bnx2x *bp)
2625{
2626 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2627
2628 if (cmng_fns != CMNG_FNS_NONE) {
2629 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2630 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2631 } else {
2632 /* rate shaping and fairness are disabled */
2633 DP(NETIF_MSG_IFUP,
2634 "single function mode without fairness\n");
2635 }
2636}
2637
c18487ee
YR		 2638/* This function is called upon link interrupt */
2639static void bnx2x_link_attn(struct bnx2x *bp)
2640{
bb2a0f7a
YG		 2641 /* Make sure that we are synced with the current statistics */
2642 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2643
c18487ee 2644 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2645
9156b30b 2646 bnx2x_init_dropless_fc(bp);
1c06328c 2647
9156b30b 2648 if (bp->link_vars.link_up) {
1c06328c 2649
619c5cb6 2650 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2651 struct host_port_stats *pstats;
2652
2653 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2654 /* reset old mac stats */
bb2a0f7a
YG		 2655 memset(&(pstats->mac_stx[0]), 0,
2656 sizeof(struct mac_stx));
2657 }
f34d28ea 2658 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2659 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2660 }
2661
568e2426
DK		 2662 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2663 bnx2x_set_local_cmng(bp);
9fdc3e95 2664
2ae17f66
VZ		 2665 __bnx2x_link_report(bp);
2666
9fdc3e95
DK		 2667 if (IS_MF(bp))
2668 bnx2x_link_sync_notify(bp);
c18487ee 2669}
a2fbb9ea 2670
9f6c9258 2671void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2672{
2ae17f66 2673 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2674 return;
a2fbb9ea 2675
00253a8c 2676 /* read updated dcb configuration */
ad5afc89
AE		 2677 if (IS_PF(bp)) {
2678 bnx2x_dcbx_pmf_update(bp);
2679 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2680 if (bp->link_vars.link_up)
2681 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2682 else
2683 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2684 /* indicate link status */
2685 bnx2x_link_report(bp);
a2fbb9ea 2686
ad5afc89
AE		 2687 } else { /* VF */
2688 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2689 SUPPORTED_10baseT_Full |
2690 SUPPORTED_100baseT_Half |
2691 SUPPORTED_100baseT_Full |
2692 SUPPORTED_1000baseT_Full |
2693 SUPPORTED_2500baseX_Full |
2694 SUPPORTED_10000baseT_Full |
2695 SUPPORTED_TP |
2696 SUPPORTED_FIBRE |
2697 SUPPORTED_Autoneg |
2698 SUPPORTED_Pause |
2699 SUPPORTED_Asym_Pause);
2700 bp->port.advertising[0] = bp->port.supported[0];
2701
2702 bp->link_params.bp = bp;
2703 bp->link_params.port = BP_PORT(bp);
2704 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2705 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2706 bp->link_params.req_line_speed[0] = SPEED_10000;
2707 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2708 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2709 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2710 bp->link_vars.line_speed = SPEED_10000;
2711 bp->link_vars.link_status =
2712 (LINK_STATUS_LINK_UP |
2713 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2714 bp->link_vars.link_up = 1;
2715 bp->link_vars.duplex = DUPLEX_FULL;
2716 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2717 __bnx2x_link_report(bp);
6495d15a
DK		 2718
2719 bnx2x_sample_bulletin(bp);
2720
2721 /* if bulletin board did not have an update for link status
2722 * __bnx2x_link_report will report current status
2723 * but it will NOT duplicate report in case of already reported
2724 * during sampling bulletin board.
2725 */
bb2a0f7a 2726 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
ad5afc89 2727 }
a2fbb9ea 2728}
a2fbb9ea 2729
a3348722
BW		 2730static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2731 u16 vlan_val, u8 allowed_prio)
2732{
86564c3f 2733 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2734 struct bnx2x_func_afex_update_params *f_update_params =
2735 &func_params.params.afex_update;
2736
2737 func_params.f_obj = &bp->func_obj;
2738 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2739
2740 /* no need to wait for RAMROD completion, so don't
2741 * set RAMROD_COMP_WAIT flag
2742 */
2743
2744 f_update_params->vif_id = vifid;
2745 f_update_params->afex_default_vlan = vlan_val;
2746 f_update_params->allowed_priorities = allowed_prio;
2747
2748 /* if ramrod can not be sent, response to MCP immediately */
2749 if (bnx2x_func_state_change(bp, &func_params) < 0)
2750 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2751
2752 return 0;
2753}
2754
2755static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2756 u16 vif_index, u8 func_bit_map)
2757{
86564c3f 2758 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2759 struct bnx2x_func_afex_viflists_params *update_params =
2760 &func_params.params.afex_viflists;
2761 int rc;
2762 u32 drv_msg_code;
2763
2764 /* validate only LIST_SET and LIST_GET are received from switch */
2765 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2766 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2767 cmd_type);
2768
2769 func_params.f_obj = &bp->func_obj;
2770 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2771
2772 /* set parameters according to cmd_type */
2773 update_params->afex_vif_list_command = cmd_type;
86564c3f 2774 update_params->vif_list_index = vif_index;
a3348722
BW		 2775 update_params->func_bit_map =
2776 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2777 update_params->func_to_clear = 0;
2778 drv_msg_code =
2779 (cmd_type == VIF_LIST_RULE_GET) ?
2780 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2781 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2782
2783 /* if ramrod can not be sent, respond to MCP immediately for
2784 * SET and GET requests (other are not triggered from MCP)
2785 */
2786 rc = bnx2x_func_state_change(bp, &func_params);
2787 if (rc < 0)
2788 bnx2x_fw_command(bp, drv_msg_code, 0);
2789
2790 return 0;
2791}
2792
2793static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2794{
2795 struct afex_stats afex_stats;
2796 u32 func = BP_ABS_FUNC(bp);
2797 u32 mf_config;
2798 u16 vlan_val;
2799 u32 vlan_prio;
2800 u16 vif_id;
2801 u8 allowed_prio;
2802 u8 vlan_mode;
2803 u32 addr_to_write, vifid, addrs, stats_type, i;
2804
2805 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2806 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2807 DP(BNX2X_MSG_MCP,
2808 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2809 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2810 }
2811
2812 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2813 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2814 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2815 DP(BNX2X_MSG_MCP,
2816 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2817 vifid, addrs);
2818 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2819 addrs);
2820 }
2821
2822 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2823 addr_to_write = SHMEM2_RD(bp,
2824 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2825 stats_type = SHMEM2_RD(bp,
2826 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2827
2828 DP(BNX2X_MSG_MCP,
2829 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2830 addr_to_write);
2831
2832 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2833
2834 /* write response to scratchpad, for MCP */
2835 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2836 REG_WR(bp, addr_to_write + i*sizeof(u32),
2837 *(((u32 *)(&afex_stats))+i));
2838
2839 /* send ack message to MCP */
2840 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2841 }
2842
2843 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2844 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2845 bp->mf_config[BP_VN(bp)] = mf_config;
2846 DP(BNX2X_MSG_MCP,
2847 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2848 mf_config);
2849
2850 /* if VIF_SET is "enabled" */
2851 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2852 /* set rate limit directly to internal RAM */
2853 struct cmng_init_input cmng_input;
2854 struct rate_shaping_vars_per_vn m_rs_vn;
2855 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2856 u32 addr = BAR_XSTRORM_INTMEM +
2857 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2858
2859 bp->mf_config[BP_VN(bp)] = mf_config;
2860
2861 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2862 m_rs_vn.vn_counter.rate =
2863 cmng_input.vnic_max_rate[BP_VN(bp)];
2864 m_rs_vn.vn_counter.quota =
2865 (m_rs_vn.vn_counter.rate *
2866 RS_PERIODIC_TIMEOUT_USEC) / 8;
2867
2868 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2869
2870 /* read relevant values from mf_cfg struct in shmem */
2871 vif_id =
2872 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2873 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2874 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2875 vlan_val =
2876 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2877 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2878 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2879 vlan_prio = (mf_config &
2880 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2881 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2882 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2883 vlan_mode =
2884 (MF_CFG_RD(bp,
2885 func_mf_config[func].afex_config) &
2886 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2887 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2888 allowed_prio =
2889 (MF_CFG_RD(bp,
2890 func_mf_config[func].afex_config) &
2891 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2892 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2893
2894 /* send ramrod to FW, return in case of failure */
2895 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2896 allowed_prio))
2897 return;
2898
2899 bp->afex_def_vlan_tag = vlan_val;
2900 bp->afex_vlan_mode = vlan_mode;
2901 } else {
2902 /* notify link down because BP->flags is disabled */
2903 bnx2x_link_report(bp);
2904
2905 /* send INVALID VIF ramrod to FW */
2906 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2907
2908 /* Reset the default afex VLAN */
2909 bp->afex_def_vlan_tag = -1;
2910 }
2911 }
2912}
2913
7609647e
YM		 2914static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2915{
2916 struct bnx2x_func_switch_update_params *switch_update_params;
2917 struct bnx2x_func_state_params func_params;
2918
2919 memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2920 switch_update_params = &func_params.params.switch_update;
2921 func_params.f_obj = &bp->func_obj;
2922 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2923
230d00eb 2924 if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
7609647e
YM		 2925 int func = BP_ABS_FUNC(bp);
2926 u32 val;
2927
2928 /* Re-learn the S-tag from shmem */
2929 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2930 FUNC_MF_CFG_E1HOV_TAG_MASK;
2931 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2932 bp->mf_ov = val;
2933 } else {
2934 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2935 goto fail;
2936 }
2937
2938 /* Configure new S-tag in LLH */
2939 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2940 bp->mf_ov);
2941
2942 /* Send Ramrod to update FW of change */
2943 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2944 &switch_update_params->changes);
2945 switch_update_params->vlan = bp->mf_ov;
2946
2947 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2948 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2949 bp->mf_ov);
2950 goto fail;
230d00eb
YM		 2951 } else {
2952 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2953 bp->mf_ov);
7609647e 2954 }
230d00eb
YM		 2955 } else {
2956 goto fail;
7609647e
YM		 2957 }
2958
230d00eb
YM		 2959 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2960 return;
7609647e
YM		 2961fail:
2962 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2963}
2964
34f80b04
EG		 2965static void bnx2x_pmf_update(struct bnx2x *bp)
2966{
2967 int port = BP_PORT(bp);
2968 u32 val;
2969
2970 bp->port.pmf = 1;
51c1a580 2971 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
34f80b04 2972
3deb8167
YR		 2973 /*
2974 * We need the mb() to ensure the ordering between the writing to
2975 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2976 */
2977 smp_mb();
2978
2979 /* queue a periodic task */
2980 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2981
ef01854e
DK		 2982 bnx2x_dcbx_pmf_update(bp);
2983
34f80b04 2984 /* enable nig attention */
3395a033 2985 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2986 if (bp->common.int_block == INT_BLOCK_HC) {
2987 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2988 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2989 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2990 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2991 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2992 }
bb2a0f7a
YG		 2993
2994 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2995}
2996
c18487ee 2997/* end of Link */
a2fbb9ea
ET		 2998
2999/* slow path */
3000
3001/*
3002 * General service functions
3003 */
3004
2691d51d 3005/* send the MCP a request, block until there is a reply */
a22f0788 3006u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 3007{
f2e0899f 3008 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 3009 u32 seq;
2691d51d
EG		 3010 u32 rc = 0;
3011 u32 cnt = 1;
3012 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3013
c4ff7cbf 3014 mutex_lock(&bp->fw_mb_mutex);
a5971d43 3015 seq = ++bp->fw_seq;
f2e0899f
DK		 3016 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3017 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3018
754a2f52
DK		 3019 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3020 (command | seq), param);
2691d51d
EG		 3021
3022 do {
3023 /* let the FW do it's magic ... */
3024 msleep(delay);
3025
f2e0899f 3026 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 3027
c4ff7cbf
EG		 3028 /* Give the FW up to 5 second (500*10ms) */
3029 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 3030
3031 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3032 cnt*delay, rc, seq);
3033
3034 /* is this a reply to our command? */
3035 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3036 rc &= FW_MSG_CODE_MASK;
3037 else {
3038 /* FW BUG! */
3039 BNX2X_ERR("FW failed to respond!\n");
3040 bnx2x_fw_dump(bp);
3041 rc = 0;
3042 }
c4ff7cbf 3043 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 3044
3045 return rc;
3046}
3047
1191cb83
ED		 3048static void storm_memset_func_cfg(struct bnx2x *bp,
3049 struct tstorm_eth_function_common_config *tcfg,
3050 u16 abs_fid)
3051{
3052 size_t size = sizeof(struct tstorm_eth_function_common_config);
3053
3054 u32 addr = BAR_TSTRORM_INTMEM +
3055 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3056
3057 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3058}
3059
619c5cb6
VZ		 3060void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3061{
3062 if (CHIP_IS_E1x(bp)) {
3063 struct tstorm_eth_function_common_config tcfg = {0};
3064
3065 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3066 }
3067
3068 /* Enable the function in the FW */
3069 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3070 storm_memset_func_en(bp, p->func_id, 1);
3071
3072 /* spq */
05cc5a39 3073 if (p->spq_active) {
619c5cb6
VZ		 3074 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3075 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3076 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3077 }
3078}
3079
6383c0b3 3080/**
16a5fd92 3081 * bnx2x_get_common_flags - Return common flags
6383c0b3
AE		 3082 *
3083 * @bp device handle
3084 * @fp queue handle
3085 * @zero_stats TRUE if statistics zeroing is needed
3086 *
3087 * Return the flags that are common for the Tx-only and not normal connections.
3088 */
1191cb83
ED		 3089static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3090 struct bnx2x_fastpath *fp,
3091 bool zero_stats)
28912902 3092{
619c5cb6
VZ		 3093 unsigned long flags = 0;
3094
3095 /* PF driver will always initialize the Queue to an ACTIVE state */
3096 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 3097
6383c0b3 3098 /* tx only connections collect statistics (on the same index as the
91226790
DK		 3099 * parent connection). The statistics are zeroed when the parent
3100 * connection is initialized.
6383c0b3 3101 */
50f0a562
BW		 3102
3103 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3104 if (zero_stats)
3105 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3106
c14db202
YM		 3107 if (bp->flags & TX_SWITCHING)
3108 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3109
91226790 3110 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
e287a75c 3111 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
6383c0b3 3112
823e1d90
YM		 3113#ifdef BNX2X_STOP_ON_ERROR
3114 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3115#endif
3116
6383c0b3
AE		 3117 return flags;
3118}
3119
1191cb83
ED		 3120static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3121 struct bnx2x_fastpath *fp,
3122 bool leading)
6383c0b3
AE		 3123{
3124 unsigned long flags = 0;
3125
619c5cb6
VZ		 3126 /* calculate other queue flags */
3127 if (IS_MF_SD(bp))
3128 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 3129
a3348722 3130 if (IS_FCOE_FP(fp)) {
619c5cb6 3131 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
a3348722
BW		 3132 /* For FCoE - force usage of default priority (for afex) */
3133 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3134 }
523224a3 3135
7e6b4d44 3136 if (fp->mode != TPA_MODE_DISABLED) {
619c5cb6 3137 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e 3138 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
621b4d66
DK		 3139 if (fp->mode == TPA_MODE_GRO)
3140 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
f5219d8e 3141 }
619c5cb6 3142
619c5cb6
VZ		 3143 if (leading) {
3144 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3145 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3146 }
523224a3 3147
619c5cb6
VZ		 3148 /* Always set HW VLAN stripping */
3149 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 3150
a3348722
BW		 3151 /* configure silent vlan removal */
3152 if (IS_MF_AFEX(bp))
3153 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3154
6383c0b3 3155 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 3156}
3157
619c5cb6 3158static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 3159 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3160 u8 cos)
619c5cb6
VZ		 3161{
3162 gen_init->stat_id = bnx2x_stats_id(fp);
3163 gen_init->spcl_id = fp->cl_id;
3164
3165 /* Always use mini-jumbo MTU for FCoE L2 ring */
3166 if (IS_FCOE_FP(fp))
3167 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3168 else
3169 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 3170
3171 gen_init->cos = cos;
02dc4025
YM		 3172
3173 gen_init->fp_hsi = ETH_FP_HSI_VERSION;
619c5cb6
VZ		 3174}
3175
3176static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 3177 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 3178 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 3179{
619c5cb6 3180 u8 max_sge = 0;
523224a3
DK		 3181 u16 sge_sz = 0;
3182 u16 tpa_agg_size = 0;
3183
7e6b4d44 3184 if (fp->mode != TPA_MODE_DISABLED) {
dfacf138
DK		 3185 pause->sge_th_lo = SGE_TH_LO(bp);
3186 pause->sge_th_hi = SGE_TH_HI(bp);
3187
3188 /* validate SGE ring has enough to cross high threshold */
3189 WARN_ON(bp->dropless_fc &&
3190 pause->sge_th_hi + FW_PREFETCH_CNT >
3191 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3192
924d75ab 3193 tpa_agg_size = TPA_AGG_SIZE;
523224a3
DK		 3194 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3195 SGE_PAGE_SHIFT;
3196 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3197 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
924d75ab 3198 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
523224a3
DK		 3199 }
3200
3201 /* pause - not for e1 */
3202 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 3203 pause->bd_th_lo = BD_TH_LO(bp);
3204 pause->bd_th_hi = BD_TH_HI(bp);
3205
3206 pause->rcq_th_lo = RCQ_TH_LO(bp);
3207 pause->rcq_th_hi = RCQ_TH_HI(bp);
3208 /*
3209 * validate that rings have enough entries to cross
3210 * high thresholds
3211 */
3212 WARN_ON(bp->dropless_fc &&
3213 pause->bd_th_hi + FW_PREFETCH_CNT >
3214 bp->rx_ring_size);
3215 WARN_ON(bp->dropless_fc &&
3216 pause->rcq_th_hi + FW_PREFETCH_CNT >
3217 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 3218
523224a3
DK		 3219 pause->pri_map = 1;
3220 }
3221
3222 /* rxq setup */
523224a3
DK		 3223 rxq_init->dscr_map = fp->rx_desc_mapping;
3224 rxq_init->sge_map = fp->rx_sge_mapping;
3225 rxq_init->rcq_map = fp->rx_comp_mapping;
3226 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 3227
619c5cb6
VZ		 3228 /* This should be a maximum number of data bytes that may be
3229 * placed on the BD (not including paddings).
3230 */
e52fcb24 3231 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3cdeec22 3232 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 3233
523224a3 3234 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 3235 rxq_init->tpa_agg_sz = tpa_agg_size;
3236 rxq_init->sge_buf_sz = sge_sz;
3237 rxq_init->max_sges_pkt = max_sge;
619c5cb6 3238 rxq_init->rss_engine_id = BP_FUNC(bp);
259afa1f 3239 rxq_init->mcast_engine_id = BP_FUNC(bp);
619c5cb6
VZ		 3240
3241 /* Maximum number or simultaneous TPA aggregation for this Queue.
3242 *
2de67439 3243 * For PF Clients it should be the maximum available number.
619c5cb6
VZ		 3244 * VF driver(s) may want to define it to a smaller value.
3245 */
dfacf138 3246 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 3247
523224a3
DK		 3248 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3249 rxq_init->fw_sb_id = fp->fw_sb_id;
3250
ec6ba945
VZ		 3251 if (IS_FCOE_FP(fp))
3252 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3253 else
6383c0b3 3254 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
a3348722
BW		 3255 /* configure silent vlan removal
3256 * if multi function mode is afex, then mask default vlan
3257 */
3258 if (IS_MF_AFEX(bp)) {
3259 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3260 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3261 }
523224a3
DK		 3262}
3263
619c5cb6 3264static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 3265 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3266 u8 cos)
523224a3 3267{
65565884 3268 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
6383c0b3 3269 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 3270 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3271 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 3272
619c5cb6 3273 /*
16a5fd92 3274 * set the tss leading client id for TX classification ==
619c5cb6
VZ		 3275 * leading RSS client id
3276 */
3277 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3278
ec6ba945
VZ		 3279 if (IS_FCOE_FP(fp)) {
3280 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3281 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3282 }
523224a3
DK		 3283}
3284
8d96286a 3285static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 3286{
3287 struct bnx2x_func_init_params func_init = {0};
523224a3 3288 struct event_ring_data eq_data = { {0} };
523224a3 3289
619c5cb6 3290 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3291 /* reset IGU PF statistics: MSIX + ATTN */
3292 /* PF */
3293 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3294 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3295 (CHIP_MODE_IS_4_PORT(bp) ?
3296 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3297 /* ATTN */
3298 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3299 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3300 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3301 (CHIP_MODE_IS_4_PORT(bp) ?
3302 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3303 }
3304
05cc5a39 3305 func_init.spq_active = true;
523224a3
DK		 3306 func_init.pf_id = BP_FUNC(bp);
3307 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 3308 func_init.spq_map = bp->spq_mapping;
3309 func_init.spq_prod = bp->spq_prod_idx;
3310
3311 bnx2x_func_init(bp, &func_init);
3312
3313 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3314
3315 /*
619c5cb6
VZ		 3316 * Congestion management values depend on the link rate
3317 * There is no active link so initial link rate is set to 10 Gbps.
3318 * When the link comes up The congestion management values are
3319 * re-calculated according to the actual link rate.
3320 */
523224a3
DK		 3321 bp->link_vars.line_speed = SPEED_10000;
3322 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3323
3324 /* Only the PMF sets the HW */
3325 if (bp->port.pmf)
3326 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3327
86564c3f 3328 /* init Event Queue - PCI bus guarantees correct endianity*/
523224a3
DK		 3329 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3330 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3331 eq_data.producer = bp->eq_prod;
3332 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3333 eq_data.sb_id = DEF_SB_ID;
3334 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3335}
3336
523224a3
DK		 3337static void bnx2x_e1h_disable(struct bnx2x *bp)
3338{
3339 int port = BP_PORT(bp);
3340
619c5cb6 3341 bnx2x_tx_disable(bp);
523224a3
DK		 3342
3343 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 3344}
3345
3346static void bnx2x_e1h_enable(struct bnx2x *bp)
3347{
3348 int port = BP_PORT(bp);
3349
7609647e
YM		 3350 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3351 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
523224a3 3352
16a5fd92 3353 /* Tx queue should be only re-enabled */
523224a3
DK		 3354 netif_tx_wake_all_queues(bp->dev);
3355
3356 /*
3357 * Should not call netif_carrier_on since it will be called if the link
3358 * is up when checking for link state
3359 */
3360}
3361
1d187b34
BW		 3362#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3363
3364static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3365{
3366 struct eth_stats_info *ether_stat =
3367 &bp->slowpath->drv_info_to_mcp.ether_stat;
3ec9f9ca
AE		 3368 struct bnx2x_vlan_mac_obj *mac_obj =
3369 &bp->sp_objs->mac_obj;
3370 int i;
1d187b34 3371
786fdf0b
DC		 3372 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3373 ETH_STAT_INFO_VERSION_LEN);
1d187b34 3374
3ec9f9ca
AE		 3375 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3376 * mac_local field in ether_stat struct. The base address is offset by 2
3377 * bytes to account for the field being 8 bytes but a mac address is
3378 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3379 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3380 * allocated by the ether_stat struct, so the macs will land in their
3381 * proper positions.
3382 */
3383 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3384 memset(ether_stat->mac_local + i, 0,
3385 sizeof(ether_stat->mac_local[0]));
3386 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3387 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3388 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3389 ETH_ALEN);
1d187b34 3390 ether_stat->mtu_size = bp->dev->mtu;
1d187b34
BW		 3391 if (bp->dev->features & NETIF_F_RXCSUM)
3392 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3393 if (bp->dev->features & NETIF_F_TSO)
3394 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3395 ether_stat->feature_flags |= bp->common.boot_mode;
3396
3397 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3398
3399 ether_stat->txq_size = bp->tx_ring_size;
3400 ether_stat->rxq_size = bp->rx_ring_size;
0c757dee 3401
fcf93a0a 3402#ifdef CONFIG_BNX2X_SRIOV
0c757dee 3403 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
fcf93a0a 3404#endif
1d187b34
BW		 3405}
3406
3407static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3408{
3409 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3410 struct fcoe_stats_info *fcoe_stat =
3411 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3412
55c11941
MS		 3413 if (!CNIC_LOADED(bp))
3414 return;
3415
3ec9f9ca 3416 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
1d187b34
BW		 3417
3418 fcoe_stat->qos_priority =
3419 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3420
3421 /* insert FCoE stats from ramrod response */
3422 if (!NO_FCOE(bp)) {
3423 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
65565884 3424 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3425 tstorm_queue_statistics;
3426
3427 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
65565884 3428 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3429 xstorm_queue_statistics;
3430
3431 struct fcoe_statistics_params *fw_fcoe_stat =
3432 &bp->fw_stats_data->fcoe;
3433
86564c3f
YM		 3434 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3435 fcoe_stat->rx_bytes_lo,
3436 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
1d187b34 3437
86564c3f
YM		 3438 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3439 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3440 fcoe_stat->rx_bytes_lo,
3441 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
1d187b34 3442
86564c3f
YM		 3443 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3444 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3445 fcoe_stat->rx_bytes_lo,
3446 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
1d187b34 3447
86564c3f
YM		 3448 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3449 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3450 fcoe_stat->rx_bytes_lo,
3451 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
1d187b34 3452
86564c3f
YM		 3453 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3454 fcoe_stat->rx_frames_lo,
3455 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
1d187b34 3456
86564c3f
YM		 3457 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3458 fcoe_stat->rx_frames_lo,
3459 fcoe_q_tstorm_stats->rcv_ucast_pkts);
1d187b34 3460
86564c3f
YM		 3461 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3462 fcoe_stat->rx_frames_lo,
3463 fcoe_q_tstorm_stats->rcv_bcast_pkts);
1d187b34 3464
86564c3f
YM		 3465 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3466 fcoe_stat->rx_frames_lo,
3467 fcoe_q_tstorm_stats->rcv_mcast_pkts);
1d187b34 3468
86564c3f
YM		 3469 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3470 fcoe_stat->tx_bytes_lo,
3471 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
1d187b34 3472
86564c3f
YM		 3473 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3474 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3475 fcoe_stat->tx_bytes_lo,
3476 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
1d187b34 3477
86564c3f
YM		 3478 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3479 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3480 fcoe_stat->tx_bytes_lo,
3481 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
1d187b34 3482
86564c3f
YM		 3483 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3484 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3485 fcoe_stat->tx_bytes_lo,
3486 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
1d187b34 3487
86564c3f
YM		 3488 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3489 fcoe_stat->tx_frames_lo,
3490 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
1d187b34 3491
86564c3f
YM		 3492 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3493 fcoe_stat->tx_frames_lo,
3494 fcoe_q_xstorm_stats->ucast_pkts_sent);
1d187b34 3495
86564c3f
YM		 3496 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3497 fcoe_stat->tx_frames_lo,
3498 fcoe_q_xstorm_stats->bcast_pkts_sent);
1d187b34 3499
86564c3f
YM		 3500 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3501 fcoe_stat->tx_frames_lo,
3502 fcoe_q_xstorm_stats->mcast_pkts_sent);
1d187b34
BW		 3503 }
3504
1d187b34
BW		 3505 /* ask L5 driver to add data to the struct */
3506 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
1d187b34
BW		 3507}
3508
3509static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3510{
3511 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3512 struct iscsi_stats_info *iscsi_stat =
3513 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3514
55c11941
MS		 3515 if (!CNIC_LOADED(bp))
3516 return;
3517
3ec9f9ca
AE		 3518 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3519 ETH_ALEN);
1d187b34
BW		 3520
3521 iscsi_stat->qos_priority =
3522 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3523
1d187b34
BW		 3524 /* ask L5 driver to add data to the struct */
3525 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
1d187b34
BW		 3526}
3527
0793f83f
DK		 3528/* called due to MCP event (on pmf):
3529 * reread new bandwidth configuration
3530 * configure FW
3531 * notify others function about the change
3532 */
1191cb83 3533static void bnx2x_config_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3534{
3535 if (bp->link_vars.link_up) {
3536 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3537 bnx2x_link_sync_notify(bp);
3538 }
3539 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3540}
3541
1191cb83 3542static void bnx2x_set_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3543{
3544 bnx2x_config_mf_bw(bp);
3545 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3546}
3547
c8c60d88
YM		 3548static void bnx2x_handle_eee_event(struct bnx2x *bp)
3549{
3550 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3551 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3552}
3553
42f8277f
YM		 3554#define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3555#define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3556
1d187b34
BW		 3557static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3558{
3559 enum drv_info_opcode op_code;
3560 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
42f8277f
YM		 3561 bool release = false;
3562 int wait;
1d187b34
BW		 3563
3564 /* if drv_info version supported by MFW doesn't match - send NACK */
3565 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3566 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3567 return;
3568 }
3569
3570 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3571 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3572
42f8277f
YM		 3573 /* Must prevent other flows from accessing drv_info_to_mcp */
3574 mutex_lock(&bp->drv_info_mutex);
3575
1d187b34
BW		 3576 memset(&bp->slowpath->drv_info_to_mcp, 0,
3577 sizeof(union drv_info_to_mcp));
3578
3579 switch (op_code) {
3580 case ETH_STATS_OPCODE:
3581 bnx2x_drv_info_ether_stat(bp);
3582 break;
3583 case FCOE_STATS_OPCODE:
3584 bnx2x_drv_info_fcoe_stat(bp);
3585 break;
3586 case ISCSI_STATS_OPCODE:
3587 bnx2x_drv_info_iscsi_stat(bp);
3588 break;
3589 default:
3590 /* if op code isn't supported - send NACK */
3591 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
42f8277f 3592 goto out;
1d187b34
BW		 3593 }
3594
3595 /* if we got drv_info attn from MFW then these fields are defined in
3596 * shmem2 for sure
3597 */
3598 SHMEM2_WR(bp, drv_info_host_addr_lo,
3599 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3600 SHMEM2_WR(bp, drv_info_host_addr_hi,
3601 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3602
3603 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
42f8277f
YM		 3604
3605 /* Since possible management wants both this and get_driver_version
3606 * need to wait until management notifies us it finished utilizing
3607 * the buffer.
3608 */
3609 if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3610 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3611 } else if (!bp->drv_info_mng_owner) {
3612 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3613
3614 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3615 u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3616
3617 /* Management is done; need to clear indication */
3618 if (indication & bit) {
3619 SHMEM2_WR(bp, mfw_drv_indication,
3620 indication & ~bit);
3621 release = true;
3622 break;
3623 }
3624
3625 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3626 }
3627 }
3628 if (!release) {
3629 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3630 bp->drv_info_mng_owner = true;
3631 }
3632
3633out:
3634 mutex_unlock(&bp->drv_info_mutex);
3635}
3636
3637static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3638{
3639 u8 vals[4];
3640 int i = 0;
3641
3642 if (bnx2x_format) {
3643 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3644 &vals[0], &vals[1], &vals[2], &vals[3]);
3645 if (i > 0)
3646 vals[0] -= '0';
3647 } else {
3648 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3649 &vals[0], &vals[1], &vals[2], &vals[3]);
3650 }
3651
3652 while (i < 4)
3653 vals[i++] = 0;
3654
3655 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3656}
3657
3658void bnx2x_update_mng_version(struct bnx2x *bp)
3659{
3660 u32 iscsiver = DRV_VER_NOT_LOADED;
3661 u32 fcoever = DRV_VER_NOT_LOADED;
3662 u32 ethver = DRV_VER_NOT_LOADED;
3663 int idx = BP_FW_MB_IDX(bp);
3664 u8 *version;
3665
3666 if (!SHMEM2_HAS(bp, func_os_drv_ver))
3667 return;
3668
3669 mutex_lock(&bp->drv_info_mutex);
3670 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3671 if (bp->drv_info_mng_owner)
3672 goto out;
3673
3674 if (bp->state != BNX2X_STATE_OPEN)
3675 goto out;
3676
3677 /* Parse ethernet driver version */
3678 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3679 if (!CNIC_LOADED(bp))
3680 goto out;
3681
3682 /* Try getting storage driver version via cnic */
3683 memset(&bp->slowpath->drv_info_to_mcp, 0,
3684 sizeof(union drv_info_to_mcp));
3685 bnx2x_drv_info_iscsi_stat(bp);
3686 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3687 iscsiver = bnx2x_update_mng_version_utility(version, false);
3688
3689 memset(&bp->slowpath->drv_info_to_mcp, 0,
3690 sizeof(union drv_info_to_mcp));
3691 bnx2x_drv_info_fcoe_stat(bp);
3692 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3693 fcoever = bnx2x_update_mng_version_utility(version, false);
3694
3695out:
3696 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3697 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3698 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3699
3700 mutex_unlock(&bp->drv_info_mutex);
3701
3702 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3703 ethver, iscsiver, fcoever);
1d187b34
BW		 3704}
3705
c48f350f
YM		 3706void bnx2x_update_mfw_dump(struct bnx2x *bp)
3707{
c48f350f
YM		 3708 u32 drv_ver;
3709 u32 valid_dump;
3710
3711 if (!SHMEM2_HAS(bp, drv_info))
3712 return;
3713
a19a19de
AB		 3714 /* Update Driver load time, possibly broken in y2038 */
3715 SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds());
c48f350f
YM		 3716
3717 drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3718 SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3719
3720 SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3721
3722 /* Check & notify On-Chip dump. */
3723 valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3724
3725 if (valid_dump & FIRST_DUMP_VALID)
3726 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3727
3728 if (valid_dump & SECOND_DUMP_VALID)
3729 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3730}
3731
7609647e 3732static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
523224a3 3733{
7609647e
YM		 3734 u32 cmd_ok, cmd_fail;
3735
3736 /* sanity */
3737 if (event & DRV_STATUS_DCC_EVENT_MASK &&
3738 event & DRV_STATUS_OEM_EVENT_MASK) {
3739 BNX2X_ERR("Received simultaneous events %08x\n", event);
3740 return;
3741 }
523224a3 3742
7609647e
YM		 3743 if (event & DRV_STATUS_DCC_EVENT_MASK) {
3744 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3745 cmd_ok = DRV_MSG_CODE_DCC_OK;
3746 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3747 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3748 cmd_ok = DRV_MSG_CODE_OEM_OK;
3749 }
523224a3 3750
7609647e
YM		 3751 DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3752
3753 if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3754 DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3755 /* This is the only place besides the function initialization
523224a3
DK		 3756 * where the bp->flags can change so it is done without any
3757 * locks
3758 */
f2e0899f 3759 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
51c1a580 3760 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
523224a3
DK		 3761 bp->flags |= MF_FUNC_DIS;
3762
3763 bnx2x_e1h_disable(bp);
3764 } else {
51c1a580 3765 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
523224a3
DK		 3766 bp->flags &= ~MF_FUNC_DIS;
3767
3768 bnx2x_e1h_enable(bp);
3769 }
7609647e
YM		 3770 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3771 DRV_STATUS_OEM_DISABLE_ENABLE_PF);
523224a3 3772 }
7609647e
YM		 3773
3774 if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3775 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
0793f83f 3776 bnx2x_config_mf_bw(bp);
7609647e
YM		 3777 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3778 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
523224a3
DK		 3779 }
3780
3781 /* Report results to MCP */
7609647e
YM		 3782 if (event)
3783 bnx2x_fw_command(bp, cmd_fail, 0);
523224a3 3784 else
7609647e 3785 bnx2x_fw_command(bp, cmd_ok, 0);
523224a3
DK		 3786}
3787
3788/* must be called under the spq lock */
1191cb83 3789static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
523224a3
DK		 3790{
3791 struct eth_spe *next_spe = bp->spq_prod_bd;
3792
3793 if (bp->spq_prod_bd == bp->spq_last_bd) {
3794 bp->spq_prod_bd = bp->spq;
3795 bp->spq_prod_idx = 0;
51c1a580 3796 DP(BNX2X_MSG_SP, "end of spq\n");
523224a3
DK		 3797 } else {
3798 bp->spq_prod_bd++;
3799 bp->spq_prod_idx++;
3800 }
3801 return next_spe;
3802}
3803
3804/* must be called under the spq lock */
1191cb83 3805static void bnx2x_sp_prod_update(struct bnx2x *bp)
28912902
MC		 3806{
3807 int func = BP_FUNC(bp);
3808
53e51e2f
VZ		 3809 /*
3810 * Make sure that BD data is updated before writing the producer:
3811 * BD data is written to the memory, the producer is read from the
3812 * memory, thus we need a full memory barrier to ensure the ordering.
3813 */
3814 mb();
28912902 3815
523224a3 3816 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3817 bp->spq_prod_idx);
28912902
MC		 3818 mmiowb();
3819}
3820
619c5cb6
VZ		 3821/**
3822 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3823 *
3824 * @cmd: command to check
3825 * @cmd_type: command type
3826 */
1191cb83 3827static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
619c5cb6
VZ		 3828{
3829 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3830 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3831 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3832 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3833 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3834 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3835 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3836 return true;
3837 else
3838 return false;
619c5cb6
VZ		 3839}
3840
619c5cb6
VZ		 3841/**
3842 * bnx2x_sp_post - place a single command on an SP ring
3843 *
3844 * @bp: driver handle
3845 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3846 * @cid: SW CID the command is related to
3847 * @data_hi: command private data address (high 32 bits)
3848 * @data_lo: command private data address (low 32 bits)
3849 * @cmd_type: command type (e.g. NONE, ETH)
3850 *
3851 * SP data is handled as if it's always an address pair, thus data fields are
3852 * not swapped to little endian in upper functions. Instead this function swaps
3853 * data as if it's two u32 fields.
3854 */
9f6c9258 3855int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3856 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3857{
28912902 3858 struct eth_spe *spe;
523224a3 3859 u16 type;
619c5cb6 3860 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3861
a2fbb9ea 3862#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 3863 if (unlikely(bp->panic)) {
3864 BNX2X_ERR("Can't post SP when there is panic\n");
a2fbb9ea 3865 return -EIO;
51c1a580 3866 }
a2fbb9ea
ET		 3867#endif
3868
34f80b04 3869 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3870
6e30dd4e
VZ		 3871 if (common) {
3872 if (!atomic_read(&bp->eq_spq_left)) {
3873 BNX2X_ERR("BUG! EQ ring full!\n");
3874 spin_unlock_bh(&bp->spq_lock);
3875 bnx2x_panic();
3876 return -EBUSY;
3877 }
3878 } else if (!atomic_read(&bp->cq_spq_left)) {
3879 BNX2X_ERR("BUG! SPQ ring full!\n");
3880 spin_unlock_bh(&bp->spq_lock);
3881 bnx2x_panic();
3882 return -EBUSY;
a2fbb9ea 3883 }
f1410647 3884
28912902
MC		 3885 spe = bnx2x_sp_get_next(bp);
3886
a2fbb9ea 3887 /* CID needs port number to be encoded int it */
28912902 3888 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3889 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3890 HW_CID(bp, cid));
523224a3 3891
14a94ebd
MK		 3892 /* In some cases, type may already contain the func-id
3893 * mainly in SRIOV related use cases, so we add it here only
3894 * if it's not already set.
3895 */
3896 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3897 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3898 SPE_HDR_CONN_TYPE;
3899 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3900 SPE_HDR_FUNCTION_ID);
3901 } else {
3902 type = cmd_type;
3903 }
a2fbb9ea 3904
523224a3
DK		 3905 spe->hdr.type = cpu_to_le16(type);
3906
3907 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3908 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3909
d6cae238
VZ		 3910 /*
3911 * It's ok if the actual decrement is issued towards the memory
3912 * somewhere between the spin_lock and spin_unlock. Thus no
16a5fd92 3913 * more explicit memory barrier is needed.
d6cae238
VZ		 3914 */
3915 if (common)
3916 atomic_dec(&bp->eq_spq_left);
3917 else
3918 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3919
51c1a580
MS		 3920 DP(BNX2X_MSG_SP,
3921 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3922 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3923 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3924 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3925 HW_CID(bp, cid), data_hi, data_lo, type,
3926 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3927
28912902 3928 bnx2x_sp_prod_update(bp);
34f80b04 3929 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3930 return 0;
3931}
3932
3933/* acquire split MCP access lock register */
4a37fb66 3934static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3935{
72fd0718 3936 u32 j, val;
34f80b04 3937 int rc = 0;
a2fbb9ea
ET		 3938
3939 might_sleep();
72fd0718 3940 for (j = 0; j < 1000; j++) {
3cdeec22
YM		 3941 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3942 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3943 if (val & MCPR_ACCESS_LOCK_LOCK)
a2fbb9ea
ET		 3944 break;
3945
639d65b8 3946 usleep_range(5000, 10000);
a2fbb9ea 3947 }
3cdeec22 3948 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
19680c48 3949 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3950 rc = -EBUSY;
3951 }
3952
3953 return rc;
3954}
3955
4a37fb66
YG		 3956/* release split MCP access lock register */
3957static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3958{
3cdeec22 3959 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
a2fbb9ea
ET		 3960}
3961
523224a3
DK		 3962#define BNX2X_DEF_SB_ATT_IDX 0x0001
3963#define BNX2X_DEF_SB_IDX 0x0002
3964
1191cb83 3965static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
a2fbb9ea 3966{
523224a3 3967 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3968 u16 rc = 0;
3969
3970 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3971 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3972 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3973 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3974 }
523224a3
DK		 3975
3976 if (bp->def_idx != def_sb->sp_sb.running_index) {
3977 bp->def_idx = def_sb->sp_sb.running_index;
3978 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3979 }
523224a3 3980
16a5fd92 3981 /* Do not reorder: indices reading should complete before handling */
523224a3 3982 barrier();
a2fbb9ea
ET		 3983 return rc;
3984}
3985
3986/*
3987 * slow path service functions
3988 */
3989
3990static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3991{
34f80b04 3992 int port = BP_PORT(bp);
a2fbb9ea
ET		 3993 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3994 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3995 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3996 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3997 u32 aeu_mask;
87942b46 3998 u32 nig_mask = 0;
f2e0899f 3999 u32 reg_addr;
a2fbb9ea 4000
a2fbb9ea
ET		 4001 if (bp->attn_state & asserted)
4002 BNX2X_ERR("IGU ERROR\n");
4003
3fcaf2e5
EG		 4004 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4005 aeu_mask = REG_RD(bp, aeu_addr);
4006
a2fbb9ea 4007 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 4008 aeu_mask, asserted);
72fd0718 4009 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 4010 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 4011
3fcaf2e5
EG		 4012 REG_WR(bp, aeu_addr, aeu_mask);
4013 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 4014
3fcaf2e5 4015 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 4016 bp->attn_state |= asserted;
3fcaf2e5 4017 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 4018
4019 if (asserted & ATTN_HARD_WIRED_MASK) {
4020 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 4021
a5e9a7cf
EG		 4022 bnx2x_acquire_phy_lock(bp);
4023
877e9aa4 4024 /* save nig interrupt mask */
87942b46 4025 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 4026
361c391e
YR		 4027 /* If nig_mask is not set, no need to call the update
4028 * function.
4029 */
4030 if (nig_mask) {
4031 REG_WR(bp, nig_int_mask_addr, 0);
4032
4033 bnx2x_link_attn(bp);
4034 }
a2fbb9ea
ET		 4035
4036 /* handle unicore attn? */
4037 }
4038 if (asserted & ATTN_SW_TIMER_4_FUNC)
4039 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4040
4041 if (asserted & GPIO_2_FUNC)
4042 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4043
4044 if (asserted & GPIO_3_FUNC)
4045 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4046
4047 if (asserted & GPIO_4_FUNC)
4048 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4049
4050 if (port == 0) {
4051 if (asserted & ATTN_GENERAL_ATTN_1) {
4052 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4053 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4054 }
4055 if (asserted & ATTN_GENERAL_ATTN_2) {
4056 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4057 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4058 }
4059 if (asserted & ATTN_GENERAL_ATTN_3) {
4060 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4061 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4062 }
4063 } else {
4064 if (asserted & ATTN_GENERAL_ATTN_4) {
4065 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4066 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4067 }
4068 if (asserted & ATTN_GENERAL_ATTN_5) {
4069 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4070 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4071 }
4072 if (asserted & ATTN_GENERAL_ATTN_6) {
4073 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4074 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4075 }
4076 }
4077
4078 } /* if hardwired */
4079
f2e0899f
DK		 4080 if (bp->common.int_block == INT_BLOCK_HC)
4081 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4082 COMMAND_REG_ATTN_BITS_SET);
4083 else
4084 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4085
4086 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4087 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4088 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 4089
4090 /* now set back the mask */
a5e9a7cf 4091 if (asserted & ATTN_NIG_FOR_FUNC) {
27c1151c
YR		 4092 /* Verify that IGU ack through BAR was written before restoring
4093 * NIG mask. This loop should exit after 2-3 iterations max.
4094 */
4095 if (bp->common.int_block != INT_BLOCK_HC) {
4096 u32 cnt = 0, igu_acked;
4097 do {
4098 igu_acked = REG_RD(bp,
4099 IGU_REG_ATTENTION_ACK_BITS);
4100 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4101 (++cnt < MAX_IGU_ATTN_ACK_TO));
4102 if (!igu_acked)
4103 DP(NETIF_MSG_HW,
4104 "Failed to verify IGU ack on time\n");
4105 barrier();
4106 }
87942b46 4107 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 4108 bnx2x_release_phy_lock(bp);
4109 }
a2fbb9ea
ET		 4110}
4111
1191cb83 4112static void bnx2x_fan_failure(struct bnx2x *bp)
fd4ef40d
EG		 4113{
4114 int port = BP_PORT(bp);
b7737c9b 4115 u32 ext_phy_config;
fd4ef40d 4116 /* mark the failure */
b7737c9b
YR		 4117 ext_phy_config =
4118 SHMEM_RD(bp,
4119 dev_info.port_hw_config[port].external_phy_config);
4120
4121 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4122 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 4123 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 4124 ext_phy_config);
fd4ef40d
EG		 4125
4126 /* log the failure */
51c1a580
MS		 4127 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4128 "Please contact OEM Support for assistance\n");
8304859a 4129
16a5fd92 4130 /* Schedule device reset (unload)
8304859a
AE		 4131 * This is due to some boards consuming sufficient power when driver is
4132 * up to overheat if fan fails.
4133 */
230bb0f3 4134 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
fd4ef40d 4135}
ab6ad5a4 4136
1191cb83 4137static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 4138{
34f80b04 4139 int port = BP_PORT(bp);
877e9aa4 4140 int reg_offset;
d90d96ba 4141 u32 val;
877e9aa4 4142
34f80b04
EG		 4143 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4144 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 4145
34f80b04 4146 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 4147
4148 val = REG_RD(bp, reg_offset);
4149 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4150 REG_WR(bp, reg_offset, val);
4151
4152 BNX2X_ERR("SPIO5 hw attention\n");
4153
fd4ef40d 4154 /* Fan failure attention */
d90d96ba 4155 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 4156 bnx2x_fan_failure(bp);
877e9aa4 4157 }
34f80b04 4158
3deb8167 4159 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 4160 bnx2x_acquire_phy_lock(bp);
4161 bnx2x_handle_module_detect_int(&bp->link_params);
4162 bnx2x_release_phy_lock(bp);
4163 }
4164
34f80b04
EG		 4165 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4166
4167 val = REG_RD(bp, reg_offset);
4168 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4169 REG_WR(bp, reg_offset, val);
4170
4171 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 4172 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 4173 bnx2x_panic();
4174 }
877e9aa4
ET		 4175}
4176
1191cb83 4177static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4178{
4179 u32 val;
4180
0626b899 4181 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 4182
4183 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4184 BNX2X_ERR("DB hw attention 0x%x\n", val);
4185 /* DORQ discard attention */
4186 if (val & 0x2)
4187 BNX2X_ERR("FATAL error from DORQ\n");
4188 }
34f80b04
EG		 4189
4190 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4191
4192 int port = BP_PORT(bp);
4193 int reg_offset;
4194
4195 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4196 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4197
4198 val = REG_RD(bp, reg_offset);
4199 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4200 REG_WR(bp, reg_offset, val);
4201
4202 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 4203 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 4204 bnx2x_panic();
4205 }
877e9aa4
ET		 4206}
4207
1191cb83 4208static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4209{
4210 u32 val;
4211
4212 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4213
4214 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4215 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4216 /* CFC error attention */
4217 if (val & 0x2)
4218 BNX2X_ERR("FATAL error from CFC\n");
4219 }
4220
4221 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 4222 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 4223 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 4224 /* RQ_USDMDP_FIFO_OVERFLOW */
4225 if (val & 0x18000)
4226 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 4227
4228 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4229 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4230 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4231 }
877e9aa4 4232 }
34f80b04
EG		 4233
4234 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4235
4236 int port = BP_PORT(bp);
4237 int reg_offset;
4238
4239 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4240 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4241
4242 val = REG_RD(bp, reg_offset);
4243 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4244 REG_WR(bp, reg_offset, val);
4245
4246 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 4247 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 4248 bnx2x_panic();
4249 }
877e9aa4
ET		 4250}
4251
1191cb83 4252static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
877e9aa4 4253{
34f80b04
EG		 4254 u32 val;
4255
877e9aa4
ET		 4256 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4257
34f80b04
EG		 4258 if (attn & BNX2X_PMF_LINK_ASSERT) {
4259 int func = BP_FUNC(bp);
4260
4261 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
a3348722 4262 bnx2x_read_mf_cfg(bp);
f2e0899f
DK		 4263 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4264 func_mf_config[BP_ABS_FUNC(bp)].config);
4265 val = SHMEM_RD(bp,
4266 func_mb[BP_FW_MB_IDX(bp)].drv_status);
7609647e
YM		 4267
4268 if (val & (DRV_STATUS_DCC_EVENT_MASK |
4269 DRV_STATUS_OEM_EVENT_MASK))
4270 bnx2x_oem_event(bp,
4271 (val & (DRV_STATUS_DCC_EVENT_MASK |
4272 DRV_STATUS_OEM_EVENT_MASK)));
0793f83f
DK		 4273
4274 if (val & DRV_STATUS_SET_MF_BW)
4275 bnx2x_set_mf_bw(bp);
4276
1d187b34
BW		 4277 if (val & DRV_STATUS_DRV_INFO_REQ)
4278 bnx2x_handle_drv_info_req(bp);
d16132ce
AE		 4279
4280 if (val & DRV_STATUS_VF_DISABLED)
370d4a26
YM		 4281 bnx2x_schedule_iov_task(bp,
4282 BNX2X_IOV_HANDLE_FLR);
d16132ce 4283
2691d51d 4284 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 4285 bnx2x_pmf_update(bp);
4286
e4901dde 4287 if (bp->port.pmf &&
785b9b1a
SR		 4288 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4289 bp->dcbx_enabled > 0)
e4901dde
VZ		 4290 /* start dcbx state machine */
4291 bnx2x_dcbx_set_params(bp,
4292 BNX2X_DCBX_STATE_NEG_RECEIVED);
a3348722
BW		 4293 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4294 bnx2x_handle_afex_cmd(bp,
4295 val & DRV_STATUS_AFEX_EVENT_MASK);
c8c60d88
YM		 4296 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4297 bnx2x_handle_eee_event(bp);
7609647e
YM		 4298
4299 if (val & DRV_STATUS_OEM_UPDATE_SVID)
4300 bnx2x_handle_update_svid_cmd(bp);
4301
3deb8167
YR		 4302 if (bp->link_vars.periodic_flags &
4303 PERIODIC_FLAGS_LINK_EVENT) {
4304 /* sync with link */
4305 bnx2x_acquire_phy_lock(bp);
4306 bp->link_vars.periodic_flags &=
4307 ~PERIODIC_FLAGS_LINK_EVENT;
4308 bnx2x_release_phy_lock(bp);
4309 if (IS_MF(bp))
4310 bnx2x_link_sync_notify(bp);
4311 bnx2x_link_report(bp);
4312 }
4313 /* Always call it here: bnx2x_link_report() will
4314 * prevent the link indication duplication.
4315 */
4316 bnx2x__link_status_update(bp);
34f80b04 4317 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 4318
4319 BNX2X_ERR("MC assert!\n");
d6cae238 4320 bnx2x_mc_assert(bp);
877e9aa4
ET		 4321 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4322 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4323 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4324 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4325 bnx2x_panic();
4326
4327 } else if (attn & BNX2X_MCP_ASSERT) {
4328
4329 BNX2X_ERR("MCP assert!\n");
4330 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 4331 bnx2x_fw_dump(bp);
877e9aa4
ET		 4332
4333 } else
4334 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4335 }
4336
4337 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 4338 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4339 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 4340 val = CHIP_IS_E1(bp) ? 0 :
4341 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 4342 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4343 }
4344 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 4345 val = CHIP_IS_E1(bp) ? 0 :
4346 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 4347 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4348 }
877e9aa4 4349 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 4350 }
4351}
4352
c9ee9206
VZ		 4353/*
4354 * Bits map:
4355 * 0-7 - Engine0 load counter.
4356 * 8-15 - Engine1 load counter.
4357 * 16 - Engine0 RESET_IN_PROGRESS bit.
4358 * 17 - Engine1 RESET_IN_PROGRESS bit.
4359 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4360 * on the engine
4361 * 19 - Engine1 ONE_IS_LOADED.
4362 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4363 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4364 * just the one belonging to its engine).
4365 *
4366 */
4367#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4368
4369#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4370#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4371#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4372#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4373#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4374#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4375#define BNX2X_GLOBAL_RESET_BIT 0x00040000
4376
4377/*
4378 * Set the GLOBAL_RESET bit.
4379 *
4380 * Should be run under rtnl lock
4381 */
4382void bnx2x_set_reset_global(struct bnx2x *bp)
4383{
f16da43b
AE		 4384 u32 val;
4385 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4386 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4387 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
f16da43b 4388 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206
VZ		 4389}
4390
4391/*
4392 * Clear the GLOBAL_RESET bit.
4393 *
4394 * Should be run under rtnl lock
4395 */
1191cb83 4396static void bnx2x_clear_reset_global(struct bnx2x *bp)
c9ee9206 4397{
f16da43b
AE		 4398 u32 val;
4399 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4400 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4401 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
f16da43b 4402 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206 4403}
f85582f8 4404
72fd0718 4405/*
c9ee9206
VZ		 4406 * Checks the GLOBAL_RESET bit.
4407 *
72fd0718
VZ		 4408 * should be run under rtnl lock
4409 */
1191cb83 4410static bool bnx2x_reset_is_global(struct bnx2x *bp)
c9ee9206 4411{
3cdeec22 4412 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4413
4414 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4415 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4416}
4417
4418/*
4419 * Clear RESET_IN_PROGRESS bit for the current engine.
4420 *
4421 * Should be run under rtnl lock
4422 */
1191cb83 4423static void bnx2x_set_reset_done(struct bnx2x *bp)
72fd0718 4424{
f16da43b 4425 u32 val;
c9ee9206
VZ		 4426 u32 bit = BP_PATH(bp) ?
4427 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4428 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4429 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4430
4431 /* Clear the bit */
4432 val &= ~bit;
4433 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4434
4435 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4436}
4437
4438/*
c9ee9206
VZ		 4439 * Set RESET_IN_PROGRESS for the current engine.
4440 *
72fd0718
VZ		 4441 * should be run under rtnl lock
4442 */
c9ee9206 4443void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 4444{
f16da43b 4445 u32 val;
c9ee9206
VZ		 4446 u32 bit = BP_PATH(bp) ?
4447 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4448 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4449 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4450
4451 /* Set the bit */
4452 val |= bit;
4453 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4454 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4455}
4456
4457/*
c9ee9206 4458 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 4459 * should be run under rtnl lock
4460 */
c9ee9206 4461bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 4462{
3cdeec22 4463 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4464 u32 bit = engine ?
4465 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4466
4467 /* return false if bit is set */
4468 return (val & bit) ? false : true;
72fd0718
VZ		 4469}
4470
4471/*
889b9af3 4472 * set pf load for the current pf.
c9ee9206 4473 *
72fd0718
VZ		 4474 * should be run under rtnl lock
4475 */
889b9af3 4476void bnx2x_set_pf_load(struct bnx2x *bp)
72fd0718 4477{
f16da43b 4478 u32 val1, val;
c9ee9206
VZ		 4479 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4480 BNX2X_PATH0_LOAD_CNT_MASK;
4481 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4482 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4483
f16da43b
AE		 4484 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4485 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4486
51c1a580 4487 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4488
c9ee9206
VZ		 4489 /* get the current counter value */
4490 val1 = (val & mask) >> shift;
4491
889b9af3
AE		 4492 /* set bit of that PF */
4493 val1 |= (1 << bp->pf_num);
c9ee9206
VZ		 4494
4495 /* clear the old value */
4496 val &= ~mask;
4497
4498 /* set the new one */
4499 val |= ((val1 << shift) & mask);
4500
4501 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4502 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4503}
4504
c9ee9206 4505/**
889b9af3 4506 * bnx2x_clear_pf_load - clear pf load mark
c9ee9206
VZ		 4507 *
4508 * @bp: driver handle
4509 *
4510 * Should be run under rtnl lock.
4511 * Decrements the load counter for the current engine. Returns
889b9af3 4512 * whether other functions are still loaded
72fd0718 4513 */
889b9af3 4514bool bnx2x_clear_pf_load(struct bnx2x *bp)
72fd0718 4515{
f16da43b 4516 u32 val1, val;
c9ee9206
VZ		 4517 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4518 BNX2X_PATH0_LOAD_CNT_MASK;
4519 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4520 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4521
f16da43b
AE		 4522 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4523 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
51c1a580 4524 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4525
c9ee9206
VZ		 4526 /* get the current counter value */
4527 val1 = (val & mask) >> shift;
4528
889b9af3
AE		 4529 /* clear bit of that PF */
4530 val1 &= ~(1 << bp->pf_num);
c9ee9206
VZ		 4531
4532 /* clear the old value */
4533 val &= ~mask;
4534
4535 /* set the new one */
4536 val |= ((val1 << shift) & mask);
4537
4538 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4539 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4540 return val1 != 0;
72fd0718
VZ		 4541}
4542
4543/*
889b9af3 4544 * Read the load status for the current engine.
c9ee9206 4545 *
72fd0718
VZ		 4546 * should be run under rtnl lock
4547 */
1191cb83 4548static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
72fd0718 4549{
c9ee9206
VZ		 4550 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4551 BNX2X_PATH0_LOAD_CNT_MASK);
4552 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4553 BNX2X_PATH0_LOAD_CNT_SHIFT);
4554 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4555
51c1a580 4556 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
c9ee9206
VZ		 4557
4558 val = (val & mask) >> shift;
4559
51c1a580
MS		 4560 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4561 engine, val);
c9ee9206 4562
889b9af3 4563 return val != 0;
72fd0718
VZ		 4564}
4565
6bf07b8e
YM		 4566static void _print_parity(struct bnx2x *bp, u32 reg)
4567{
4568 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4569}
4570
1191cb83 4571static void _print_next_block(int idx, const char *blk)
72fd0718 4572{
f1deab50 4573 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 4574}
4575
4293b9f5
DK		 4576static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4577 int *par_num, bool print)
72fd0718 4578{
4293b9f5
DK		 4579 u32 cur_bit;
4580 bool res;
4581 int i;
4582
4583 res = false;
4584
72fd0718 4585 for (i = 0; sig; i++) {
4293b9f5 4586 cur_bit = (0x1UL << i);
72fd0718 4587 if (sig & cur_bit) {
4293b9f5
DK		 4588 res |= true; /* Each bit is real error! */
4589
4590 if (print) {
4591 switch (cur_bit) {
4592 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4593 _print_next_block((*par_num)++, "BRB");
6bf07b8e
YM		 4594 _print_parity(bp,
4595 BRB1_REG_BRB1_PRTY_STS);
4293b9f5
DK		 4596 break;
4597 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4598 _print_next_block((*par_num)++,
4599 "PARSER");
6bf07b8e 4600 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4293b9f5
DK		 4601 break;
4602 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4603 _print_next_block((*par_num)++, "TSDM");
6bf07b8e
YM		 4604 _print_parity(bp,
4605 TSDM_REG_TSDM_PRTY_STS);
4293b9f5
DK		 4606 break;
4607 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4608 _print_next_block((*par_num)++,
c9ee9206 4609 "SEARCHER");
6bf07b8e 4610 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4293b9f5
DK		 4611 break;
4612 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4613 _print_next_block((*par_num)++, "TCM");
4614 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4615 break;
4616 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4617 _print_next_block((*par_num)++,
4618 "TSEMI");
6bf07b8e
YM		 4619 _print_parity(bp,
4620 TSEM_REG_TSEM_PRTY_STS_0);
4621 _print_parity(bp,
4622 TSEM_REG_TSEM_PRTY_STS_1);
4293b9f5
DK		 4623 break;
4624 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4625 _print_next_block((*par_num)++, "XPB");
6bf07b8e
YM		 4626 _print_parity(bp, GRCBASE_XPB +
4627 PB_REG_PB_PRTY_STS);
4293b9f5 4628 break;
6bf07b8e 4629 }
72fd0718
VZ		 4630 }
4631
4632 /* Clear the bit */
4633 sig &= ~cur_bit;
4634 }
4635 }
4636
4293b9f5 4637 return res;
72fd0718
VZ		 4638}
4639
4293b9f5
DK		 4640static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4641 int *par_num, bool *global,
6bf07b8e 4642 bool print)
72fd0718 4643{
4293b9f5
DK		 4644 u32 cur_bit;
4645 bool res;
4646 int i;
4647
4648 res = false;
4649
72fd0718 4650 for (i = 0; sig; i++) {
4293b9f5 4651 cur_bit = (0x1UL << i);
72fd0718 4652 if (sig & cur_bit) {
4293b9f5 4653 res |= true; /* Each bit is real error! */
72fd0718 4654 switch (cur_bit) {
c9ee9206 4655 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
6bf07b8e 4656 if (print) {
4293b9f5 4657 _print_next_block((*par_num)++, "PBF");
6bf07b8e
YM		 4658 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4659 }
72fd0718
VZ		 4660 break;
4661 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
6bf07b8e 4662 if (print) {
4293b9f5 4663 _print_next_block((*par_num)++, "QM");
6bf07b8e
YM		 4664 _print_parity(bp, QM_REG_QM_PRTY_STS);
4665 }
c9ee9206
VZ		 4666 break;
4667 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
6bf07b8e 4668 if (print) {
4293b9f5 4669 _print_next_block((*par_num)++, "TM");
6bf07b8e
YM		 4670 _print_parity(bp, TM_REG_TM_PRTY_STS);
4671 }
72fd0718
VZ		 4672 break;
4673 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
6bf07b8e 4674 if (print) {
4293b9f5 4675 _print_next_block((*par_num)++, "XSDM");
6bf07b8e
YM		 4676 _print_parity(bp,
4677 XSDM_REG_XSDM_PRTY_STS);
4678 }
c9ee9206
VZ		 4679 break;
4680 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
6bf07b8e 4681 if (print) {
4293b9f5 4682 _print_next_block((*par_num)++, "XCM");
6bf07b8e
YM		 4683 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4684 }
72fd0718
VZ		 4685 break;
4686 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
6bf07b8e 4687 if (print) {
4293b9f5
DK		 4688 _print_next_block((*par_num)++,
4689 "XSEMI");
6bf07b8e
YM		 4690 _print_parity(bp,
4691 XSEM_REG_XSEM_PRTY_STS_0);
4692 _print_parity(bp,
4693 XSEM_REG_XSEM_PRTY_STS_1);
4694 }
72fd0718
VZ		 4695 break;
4696 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
6bf07b8e 4697 if (print) {
4293b9f5 4698 _print_next_block((*par_num)++,
c9ee9206 4699 "DOORBELLQ");
6bf07b8e
YM		 4700 _print_parity(bp,
4701 DORQ_REG_DORQ_PRTY_STS);
4702 }
c9ee9206
VZ		 4703 break;
4704 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
6bf07b8e 4705 if (print) {
4293b9f5 4706 _print_next_block((*par_num)++, "NIG");
6bf07b8e
YM		 4707 if (CHIP_IS_E1x(bp)) {
4708 _print_parity(bp,
4709 NIG_REG_NIG_PRTY_STS);
4710 } else {
4711 _print_parity(bp,
4712 NIG_REG_NIG_PRTY_STS_0);
4713 _print_parity(bp,
4714 NIG_REG_NIG_PRTY_STS_1);
4715 }
4716 }
72fd0718
VZ		 4717 break;
4718 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206 4719 if (print)
4293b9f5 4720 _print_next_block((*par_num)++,
c9ee9206
VZ		 4721 "VAUX PCI CORE");
4722 *global = true;
72fd0718
VZ		 4723 break;
4724 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
6bf07b8e 4725 if (print) {
4293b9f5
DK		 4726 _print_next_block((*par_num)++,
4727 "DEBUG");
6bf07b8e
YM		 4728 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4729 }
72fd0718
VZ		 4730 break;
4731 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
6bf07b8e 4732 if (print) {
4293b9f5 4733 _print_next_block((*par_num)++, "USDM");
6bf07b8e
YM		 4734 _print_parity(bp,
4735 USDM_REG_USDM_PRTY_STS);
4736 }
72fd0718 4737 break;
8736c826 4738 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
6bf07b8e 4739 if (print) {
4293b9f5 4740 _print_next_block((*par_num)++, "UCM");
6bf07b8e
YM		 4741 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4742 }
8736c826 4743 break;
72fd0718 4744 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
6bf07b8e 4745 if (print) {
4293b9f5
DK		 4746 _print_next_block((*par_num)++,
4747 "USEMI");
6bf07b8e
YM		 4748 _print_parity(bp,
4749 USEM_REG_USEM_PRTY_STS_0);
4750 _print_parity(bp,
4751 USEM_REG_USEM_PRTY_STS_1);
4752 }
72fd0718
VZ		 4753 break;
4754 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
6bf07b8e 4755 if (print) {
4293b9f5 4756 _print_next_block((*par_num)++, "UPB");
6bf07b8e
YM		 4757 _print_parity(bp, GRCBASE_UPB +
4758 PB_REG_PB_PRTY_STS);
4759 }
72fd0718
VZ		 4760 break;
4761 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
6bf07b8e 4762 if (print) {
4293b9f5 4763 _print_next_block((*par_num)++, "CSDM");
6bf07b8e
YM		 4764 _print_parity(bp,
4765 CSDM_REG_CSDM_PRTY_STS);
4766 }
72fd0718 4767 break;
8736c826 4768 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
6bf07b8e 4769 if (print) {
4293b9f5 4770 _print_next_block((*par_num)++, "CCM");
6bf07b8e
YM		 4771 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4772 }
8736c826 4773 break;
72fd0718
VZ		 4774 }
4775
4776 /* Clear the bit */
4777 sig &= ~cur_bit;
4778 }
4779 }
4780
4293b9f5 4781 return res;
72fd0718
VZ		 4782}
4783
4293b9f5
DK		 4784static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4785 int *par_num, bool print)
72fd0718 4786{
4293b9f5
DK		 4787 u32 cur_bit;
4788 bool res;
4789 int i;
4790
4791 res = false;
4792
72fd0718 4793 for (i = 0; sig; i++) {
4293b9f5 4794 cur_bit = (0x1UL << i);
72fd0718 4795 if (sig & cur_bit) {
0c23ad37 4796 res = true; /* Each bit is real error! */
4293b9f5
DK		 4797 if (print) {
4798 switch (cur_bit) {
4799 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4800 _print_next_block((*par_num)++,
4801 "CSEMI");
6bf07b8e
YM		 4802 _print_parity(bp,
4803 CSEM_REG_CSEM_PRTY_STS_0);
4804 _print_parity(bp,
4805 CSEM_REG_CSEM_PRTY_STS_1);
4293b9f5
DK		 4806 break;
4807 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4808 _print_next_block((*par_num)++, "PXP");
6bf07b8e
YM		 4809 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4810 _print_parity(bp,
4811 PXP2_REG_PXP2_PRTY_STS_0);
4812 _print_parity(bp,
4813 PXP2_REG_PXP2_PRTY_STS_1);
4293b9f5
DK		 4814 break;
4815 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4816 _print_next_block((*par_num)++,
4817 "PXPPCICLOCKCLIENT");
4818 break;
4819 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4820 _print_next_block((*par_num)++, "CFC");
6bf07b8e
YM		 4821 _print_parity(bp,
4822 CFC_REG_CFC_PRTY_STS);
4293b9f5
DK		 4823 break;
4824 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4825 _print_next_block((*par_num)++, "CDU");
6bf07b8e 4826 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4293b9f5
DK		 4827 break;
4828 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4829 _print_next_block((*par_num)++, "DMAE");
6bf07b8e
YM		 4830 _print_parity(bp,
4831 DMAE_REG_DMAE_PRTY_STS);
4293b9f5
DK		 4832 break;
4833 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4834 _print_next_block((*par_num)++, "IGU");
6bf07b8e
YM		 4835 if (CHIP_IS_E1x(bp))
4836 _print_parity(bp,
4837 HC_REG_HC_PRTY_STS);
4838 else
4839 _print_parity(bp,
4840 IGU_REG_IGU_PRTY_STS);
4293b9f5
DK		 4841 break;
4842 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4843 _print_next_block((*par_num)++, "MISC");
6bf07b8e
YM		 4844 _print_parity(bp,
4845 MISC_REG_MISC_PRTY_STS);
4293b9f5 4846 break;
6bf07b8e 4847 }
72fd0718
VZ		 4848 }
4849
4850 /* Clear the bit */
4851 sig &= ~cur_bit;
4852 }
4853 }
4854
4293b9f5 4855 return res;
72fd0718
VZ		 4856}
4857
4293b9f5
DK		 4858static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4859 int *par_num, bool *global,
4860 bool print)
72fd0718 4861{
4293b9f5
DK		 4862 bool res = false;
4863 u32 cur_bit;
4864 int i;
4865
72fd0718 4866 for (i = 0; sig; i++) {
4293b9f5 4867 cur_bit = (0x1UL << i);
72fd0718
VZ		 4868 if (sig & cur_bit) {
4869 switch (cur_bit) {
4870 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206 4871 if (print)
4293b9f5
DK		 4872 _print_next_block((*par_num)++,
4873 "MCP ROM");
c9ee9206 4874 *global = true;
0c23ad37 4875 res = true;
72fd0718
VZ		 4876 break;
4877 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206 4878 if (print)
4293b9f5 4879 _print_next_block((*par_num)++,
c9ee9206
VZ		 4880 "MCP UMP RX");
4881 *global = true;
0c23ad37 4882 res = true;
72fd0718
VZ		 4883 break;
4884 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206 4885 if (print)
4293b9f5 4886 _print_next_block((*par_num)++,
c9ee9206
VZ		 4887 "MCP UMP TX");
4888 *global = true;
0c23ad37 4889 res = true;
72fd0718
VZ		 4890 break;
4891 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
ad6afbe9 4892 (*par_num)++;
4293b9f5
DK		 4893 /* clear latched SCPAD PATIRY from MCP */
4894 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4895 1UL << 10);
72fd0718
VZ		 4896 break;
4897 }
4898
4899 /* Clear the bit */
4900 sig &= ~cur_bit;
4901 }
4902 }
4903
4293b9f5 4904 return res;
72fd0718
VZ		 4905}
4906
4293b9f5
DK		 4907static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4908 int *par_num, bool print)
8736c826 4909{
4293b9f5
DK		 4910 u32 cur_bit;
4911 bool res;
4912 int i;
4913
4914 res = false;
4915
8736c826 4916 for (i = 0; sig; i++) {
4293b9f5 4917 cur_bit = (0x1UL << i);
8736c826 4918 if (sig & cur_bit) {
0c23ad37 4919 res = true; /* Each bit is real error! */
4293b9f5
DK		 4920 if (print) {
4921 switch (cur_bit) {
4922 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4923 _print_next_block((*par_num)++,
4924 "PGLUE_B");
6bf07b8e 4925 _print_parity(bp,
4293b9f5
DK		 4926 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4927 break;
4928 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4929 _print_next_block((*par_num)++, "ATC");
6bf07b8e
YM		 4930 _print_parity(bp,
4931 ATC_REG_ATC_PRTY_STS);
4293b9f5 4932 break;
6bf07b8e 4933 }
8736c826 4934 }
8736c826
VZ		 4935 /* Clear the bit */
4936 sig &= ~cur_bit;
4937 }
4938 }
4939
4293b9f5 4940 return res;
8736c826
VZ		 4941}
4942
1191cb83
ED		 4943static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4944 u32 *sig)
72fd0718 4945{
4293b9f5
DK		 4946 bool res = false;
4947
8736c826
VZ		 4948 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4949 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4950 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4951 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4952 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718 4953 int par_num = 0;
ad6afbe9 4954
51c1a580
MS		 4955 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4956 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
8736c826
VZ		 4957 sig[0] & HW_PRTY_ASSERT_SET_0,
4958 sig[1] & HW_PRTY_ASSERT_SET_1,
4959 sig[2] & HW_PRTY_ASSERT_SET_2,
4960 sig[3] & HW_PRTY_ASSERT_SET_3,
4961 sig[4] & HW_PRTY_ASSERT_SET_4);
ad6afbe9
MC		 4962 if (print) {
4963 if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4964 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4965 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4966 (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4967 (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4968 netdev_err(bp->dev,
4969 "Parity errors detected in blocks: ");
4970 } else {
4971 print = false;
4972 }
4973 }
4293b9f5
DK		 4974 res |= bnx2x_check_blocks_with_parity0(bp,
4975 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4976 res |= bnx2x_check_blocks_with_parity1(bp,
4977 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4978 res |= bnx2x_check_blocks_with_parity2(bp,
4979 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4980 res |= bnx2x_check_blocks_with_parity3(bp,
4981 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4982 res |= bnx2x_check_blocks_with_parity4(bp,
4983 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
8736c826 4984
c9ee9206
VZ		 4985 if (print)
4986 pr_cont("\n");
4293b9f5 4987 }
8736c826 4988
4293b9f5 4989 return res;
72fd0718
VZ		 4990}
4991
c9ee9206
VZ		 4992/**
4993 * bnx2x_chk_parity_attn - checks for parity attentions.
4994 *
4995 * @bp: driver handle
4996 * @global: true if there was a global attention
4997 * @print: show parity attention in syslog
4998 */
4999bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 5000{
8736c826 5001 struct attn_route attn = { {0} };
72fd0718
VZ		 5002 int port = BP_PORT(bp);
5003
5004 attn.sig[0] = REG_RD(bp,
5005 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5006 port*4);
5007 attn.sig[1] = REG_RD(bp,
5008 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5009 port*4);
5010 attn.sig[2] = REG_RD(bp,
5011 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5012 port*4);
5013 attn.sig[3] = REG_RD(bp,
5014 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5015 port*4);
0a5ccb75
YM		 5016 /* Since MCP attentions can't be disabled inside the block, we need to
5017 * read AEU registers to see whether they're currently disabled
5018 */
5019 attn.sig[3] &= ((REG_RD(bp,
5020 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5021 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5022 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5023 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
72fd0718 5024
8736c826
VZ		 5025 if (!CHIP_IS_E1x(bp))
5026 attn.sig[4] = REG_RD(bp,
5027 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5028 port*4);
5029
5030 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 5031}
5032
1191cb83 5033static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
f2e0899f
DK		 5034{
5035 u32 val;
5036 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5037
5038 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5039 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5040 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
51c1a580 5041 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
f2e0899f 5042 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
51c1a580 5043 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
f2e0899f 5044 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
51c1a580 5045 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
f2e0899f 5046 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
51c1a580 5047 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
f2e0899f
DK		 5048 if (val &
5049 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
51c1a580 5050 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
f2e0899f
DK		 5051 if (val &
5052 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
51c1a580 5053 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
f2e0899f 5054 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
51c1a580 5055 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
f2e0899f 5056 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
51c1a580 5057 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
f2e0899f 5058 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
51c1a580 5059 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
f2e0899f
DK		 5060 }
5061 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5062 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5063 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5064 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5065 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5066 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
51c1a580 5067 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
f2e0899f 5068 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
51c1a580 5069 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
f2e0899f 5070 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
51c1a580 5071 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
f2e0899f
DK		 5072 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5073 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5074 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
51c1a580 5075 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
f2e0899f
DK		 5076 }
5077
5078 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5079 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5080 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5081 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5082 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5083 }
f2e0899f
DK		 5084}
5085
72fd0718
VZ		 5086static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5087{
5088 struct attn_route attn, *group_mask;
34f80b04 5089 int port = BP_PORT(bp);
877e9aa4 5090 int index;
a2fbb9ea
ET		 5091 u32 reg_addr;
5092 u32 val;
3fcaf2e5 5093 u32 aeu_mask;
c9ee9206 5094 bool global = false;
a2fbb9ea
ET		 5095
5096 /* need to take HW lock because MCP or other port might also
5097 try to handle this event */
4a37fb66 5098 bnx2x_acquire_alr(bp);
a2fbb9ea 5099
c9ee9206
VZ		 5100 if (bnx2x_chk_parity_attn(bp, &global, true)) {
5101#ifndef BNX2X_STOP_ON_ERROR
72fd0718 5102 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 5103 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 5104 /* Disable HW interrupts */
5105 bnx2x_int_disable(bp);
72fd0718
VZ		 5106 /* In case of parity errors don't handle attentions so that
5107 * other function would "see" parity errors.
5108 */
c9ee9206
VZ		 5109#else
5110 bnx2x_panic();
5111#endif
5112 bnx2x_release_alr(bp);
72fd0718
VZ		 5113 return;
5114 }
5115
a2fbb9ea
ET		 5116 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5117 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5118 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5119 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 5120 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5121 attn.sig[4] =
5122 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5123 else
5124 attn.sig[4] = 0;
5125
5126 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5127 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 5128
5129 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5130 if (deasserted & (1 << index)) {
72fd0718 5131 group_mask = &bp->attn_group[index];
a2fbb9ea 5132
51c1a580 5133 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
f2e0899f
DK		 5134 index,
5135 group_mask->sig[0], group_mask->sig[1],
5136 group_mask->sig[2], group_mask->sig[3],
5137 group_mask->sig[4]);
a2fbb9ea 5138
f2e0899f
DK		 5139 bnx2x_attn_int_deasserted4(bp,
5140 attn.sig[4] & group_mask->sig[4]);
877e9aa4 5141 bnx2x_attn_int_deasserted3(bp,
72fd0718 5142 attn.sig[3] & group_mask->sig[3]);
877e9aa4 5143 bnx2x_attn_int_deasserted1(bp,
72fd0718 5144 attn.sig[1] & group_mask->sig[1]);
877e9aa4 5145 bnx2x_attn_int_deasserted2(bp,
72fd0718 5146 attn.sig[2] & group_mask->sig[2]);
877e9aa4 5147 bnx2x_attn_int_deasserted0(bp,
72fd0718 5148 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 5149 }
5150 }
5151
4a37fb66 5152 bnx2x_release_alr(bp);
a2fbb9ea 5153
f2e0899f
DK		 5154 if (bp->common.int_block == INT_BLOCK_HC)
5155 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5156 COMMAND_REG_ATTN_BITS_CLR);
5157 else
5158 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 5159
5160 val = ~deasserted;
f2e0899f
DK		 5161 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5162 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 5163 REG_WR(bp, reg_addr, val);
a2fbb9ea 5164
a2fbb9ea 5165 if (~bp->attn_state & deasserted)
3fcaf2e5 5166 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 5167
5168 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5169 MISC_REG_AEU_MASK_ATTN_FUNC_0;
5170
3fcaf2e5
EG		 5171 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5172 aeu_mask = REG_RD(bp, reg_addr);
5173
5174 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
5175 aeu_mask, deasserted);
72fd0718 5176 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 5177 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 5178
3fcaf2e5
EG		 5179 REG_WR(bp, reg_addr, aeu_mask);
5180 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 5181
5182 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5183 bp->attn_state &= ~deasserted;
5184 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5185}
5186
5187static void bnx2x_attn_int(struct bnx2x *bp)
5188{
5189 /* read local copy of bits */
68d59484
EG		 5190 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5191 attn_bits);
5192 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5193 attn_bits_ack);
a2fbb9ea
ET		 5194 u32 attn_state = bp->attn_state;
5195
5196 /* look for changed bits */
5197 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
5198 u32 deasserted = ~attn_bits & attn_ack & attn_state;
5199
5200 DP(NETIF_MSG_HW,
5201 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5202 attn_bits, attn_ack, asserted, deasserted);
5203
5204 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 5205 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 5206
5207 /* handle bits that were raised */
5208 if (asserted)
5209 bnx2x_attn_int_asserted(bp, asserted);
5210
5211 if (deasserted)
5212 bnx2x_attn_int_deasserted(bp, deasserted);
5213}
5214
619c5cb6
VZ		 5215void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5216 u16 index, u8 op, u8 update)
5217{
dc1ba591
AE		 5218 u32 igu_addr = bp->igu_base_addr;
5219 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
619c5cb6
VZ		 5220 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5221 igu_addr);
5222}
5223
1191cb83 5224static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
523224a3
DK		 5225{
5226 /* No memory barriers */
5227 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5228 mmiowb(); /* keep prod updates ordered */
5229}
5230
523224a3
DK		 5231static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5232 union event_ring_elem *elem)
5233{
619c5cb6
VZ		 5234 u8 err = elem->message.error;
5235
523224a3 5236 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 5237 (cid < bp->cnic_eth_dev.starting_cid &&
5238 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 5239 return 1;
5240
5241 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5242
619c5cb6
VZ		 5243 if (unlikely(err)) {
5244
523224a3
DK		 5245 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5246 cid);
823e1d90 5247 bnx2x_panic_dump(bp, false);
523224a3 5248 }
619c5cb6 5249 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 5250 return 0;
5251}
523224a3 5252
1191cb83 5253static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5254{
5255 struct bnx2x_mcast_ramrod_params rparam;
5256 int rc;
5257
5258 memset(&rparam, 0, sizeof(rparam));
5259
5260 rparam.mcast_obj = &bp->mcast_obj;
5261
5262 netif_addr_lock_bh(bp->dev);
5263
5264 /* Clear pending state for the last command */
5265 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5266
5267 /* If there are pending mcast commands - send them */
5268 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5269 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5270 if (rc < 0)
5271 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5272 rc);
5273 }
5274
5275 netif_addr_unlock_bh(bp->dev);
5276}
5277
1191cb83
ED		 5278static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5279 union event_ring_elem *elem)
619c5cb6
VZ		 5280{
5281 unsigned long ramrod_flags = 0;
5282 int rc = 0;
5283 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5284 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5285
5286 /* Always push next commands out, don't wait here */
5287 __set_bit(RAMROD_CONT, &ramrod_flags);
5288
86564c3f
YM		 5289 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5290 >> BNX2X_SWCID_SHIFT) {
619c5cb6 5291 case BNX2X_FILTER_MAC_PENDING:
51c1a580 5292 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
55c11941 5293 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
619c5cb6
VZ		 5294 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5295 else
15192a8c 5296 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
619c5cb6 5297
05cc5a39
YM		 5298 break;
5299 case BNX2X_FILTER_VLAN_PENDING:
5300 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5301 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
619c5cb6 5302 break;
619c5cb6 5303 case BNX2X_FILTER_MCAST_PENDING:
51c1a580 5304 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
619c5cb6
VZ		 5305 /* This is only relevant for 57710 where multicast MACs are
5306 * configured as unicast MACs using the same ramrod.
5307 */
5308 bnx2x_handle_mcast_eqe(bp);
5309 return;
5310 default:
5311 BNX2X_ERR("Unsupported classification command: %d\n",
5312 elem->message.data.eth_event.echo);
5313 return;
5314 }
5315
5316 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5317
5318 if (rc < 0)
5319 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5320 else if (rc > 0)
5321 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
619c5cb6
VZ		 5322}
5323
619c5cb6 5324static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
619c5cb6 5325
1191cb83 5326static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5327{
5328 netif_addr_lock_bh(bp->dev);
5329
5330 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5331
5332 /* Send rx_mode command again if was requested */
5333 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5334 bnx2x_set_storm_rx_mode(bp);
619c5cb6
VZ		 5335 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5336 &bp->sp_state))
5337 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5338 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5339 &bp->sp_state))
5340 bnx2x_set_iscsi_eth_rx_mode(bp, false);
619c5cb6
VZ		 5341
5342 netif_addr_unlock_bh(bp->dev);
5343}
5344
1191cb83 5345static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
a3348722
BW		 5346 union event_ring_elem *elem)
5347{
5348 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5349 DP(BNX2X_MSG_SP,
5350 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5351 elem->message.data.vif_list_event.func_bit_map);
5352 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5353 elem->message.data.vif_list_event.func_bit_map);
5354 } else if (elem->message.data.vif_list_event.echo ==
5355 VIF_LIST_RULE_SET) {
5356 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5357 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5358 }
5359}
5360
5361/* called with rtnl_lock */
1191cb83 5362static void bnx2x_after_function_update(struct bnx2x *bp)
a3348722
BW		 5363{
5364 int q, rc;
5365 struct bnx2x_fastpath *fp;
5366 struct bnx2x_queue_state_params queue_params = {NULL};
5367 struct bnx2x_queue_update_params *q_update_params =
5368 &queue_params.params.update;
5369
2de67439 5370 /* Send Q update command with afex vlan removal values for all Qs */
a3348722
BW		 5371 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5372
5373 /* set silent vlan removal values according to vlan mode */
5374 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5375 &q_update_params->update_flags);
5376 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5377 &q_update_params->update_flags);
5378 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5379
5380 /* in access mode mark mask and value are 0 to strip all vlans */
5381 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5382 q_update_params->silent_removal_value = 0;
5383 q_update_params->silent_removal_mask = 0;
5384 } else {
5385 q_update_params->silent_removal_value =
5386 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5387 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5388 }
5389
5390 for_each_eth_queue(bp, q) {
5391 /* Set the appropriate Queue object */
5392 fp = &bp->fp[q];
15192a8c 5393 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5394
5395 /* send the ramrod */
5396 rc = bnx2x_queue_state_change(bp, &queue_params);
5397 if (rc < 0)
5398 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5399 q);
5400 }
5401
fea75645 5402 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
65565884 5403 fp = &bp->fp[FCOE_IDX(bp)];
15192a8c 5404 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5405
5406 /* clear pending completion bit */
5407 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5408
5409 /* mark latest Q bit */
4e857c58 5410 smp_mb__before_atomic();
a3348722 5411 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4e857c58 5412 smp_mb__after_atomic();
a3348722
BW		 5413
5414 /* send Q update ramrod for FCoE Q */
5415 rc = bnx2x_queue_state_change(bp, &queue_params);
5416 if (rc < 0)
5417 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5418 q);
5419 } else {
5420 /* If no FCoE ring - ACK MCP now */
5421 bnx2x_link_report(bp);
5422 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5423 }
a3348722
BW		 5424}
5425
1191cb83 5426static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
619c5cb6
VZ		 5427 struct bnx2x *bp, u32 cid)
5428{
94f05b0f 5429 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
55c11941
MS		 5430
5431 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
15192a8c 5432 return &bnx2x_fcoe_sp_obj(bp, q_obj);
619c5cb6 5433 else
15192a8c 5434 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
619c5cb6
VZ		 5435}
5436
523224a3
DK		 5437static void bnx2x_eq_int(struct bnx2x *bp)
5438{
5439 u16 hw_cons, sw_cons, sw_prod;
5440 union event_ring_elem *elem;
55c11941 5441 u8 echo;
523224a3
DK		 5442 u32 cid;
5443 u8 opcode;
fd1fc79d 5444 int rc, spqe_cnt = 0;
619c5cb6
VZ		 5445 struct bnx2x_queue_sp_obj *q_obj;
5446 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5447 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 5448
5449 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5450
5451 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
16a5fd92 5452 * when we get the next-page we need to adjust so the loop
523224a3
DK		 5453 * condition below will be met. The next element is the size of a
5454 * regular element and hence incrementing by 1
5455 */
5456 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5457 hw_cons++;
5458
25985edc 5459 /* This function may never run in parallel with itself for a
523224a3
DK		 5460 * specific bp, thus there is no need in "paired" read memory
5461 * barrier here.
5462 */
5463 sw_cons = bp->eq_cons;
5464 sw_prod = bp->eq_prod;
5465
d6cae238 5466 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 5467 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 5468
5469 for (; sw_cons != hw_cons;
5470 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5471
523224a3
DK		 5472 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5473
fd1fc79d
AE		 5474 rc = bnx2x_iov_eq_sp_event(bp, elem);
5475 if (!rc) {
5476 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5477 rc);
5478 goto next_spqe;
5479 }
523224a3 5480
86564c3f
YM		 5481 /* elem CID originates from FW; actually LE */
5482 cid = SW_CID((__force __le32)
5483 elem->message.data.cfc_del_event.cid);
5484 opcode = elem->message.opcode;
523224a3
DK		 5485
5486 /* handle eq element */
5487 switch (opcode) {
fd1fc79d 5488 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
370d4a26
YM		 5489 bnx2x_vf_mbx_schedule(bp,
5490 &elem->message.data.vf_pf_event);
fd1fc79d
AE		 5491 continue;
5492
523224a3 5493 case EVENT_RING_OPCODE_STAT_QUERY:
76ca70fa
YM		 5494 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5495 "got statistics comp event %d\n",
5496 bp->stats_comp++);
523224a3 5497 /* nothing to do with stats comp */
d6cae238 5498 goto next_spqe;
523224a3
DK		 5499
5500 case EVENT_RING_OPCODE_CFC_DEL:
5501 /* handle according to cid range */
5502 /*
5503 * we may want to verify here that the bp state is
5504 * HALTING
5505 */
d6cae238 5506 DP(BNX2X_MSG_SP,
523224a3 5507 "got delete ramrod for MULTI[%d]\n", cid);
55c11941
MS		 5508
5509 if (CNIC_LOADED(bp) &&
5510 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
523224a3 5511 goto next_spqe;
55c11941 5512
619c5cb6
VZ		 5513 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5514
5515 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5516 break;
5517
523224a3 5518 goto next_spqe;
e4901dde
VZ		 5519
5520 case EVENT_RING_OPCODE_STOP_TRAFFIC:
51c1a580 5521 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
6ffa39f2 5522 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
6debea87
DK		 5523 if (f_obj->complete_cmd(bp, f_obj,
5524 BNX2X_F_CMD_TX_STOP))
5525 break;
e4901dde 5526 goto next_spqe;
619c5cb6 5527
e4901dde 5528 case EVENT_RING_OPCODE_START_TRAFFIC:
51c1a580 5529 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
6ffa39f2 5530 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
6debea87
DK		 5531 if (f_obj->complete_cmd(bp, f_obj,
5532 BNX2X_F_CMD_TX_START))
5533 break;
e4901dde 5534 goto next_spqe;
55c11941 5535
a3348722 5536 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
55c11941
MS		 5537 echo = elem->message.data.function_update_event.echo;
5538 if (echo == SWITCH_UPDATE) {
5539 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5540 "got FUNC_SWITCH_UPDATE ramrod\n");
5541 if (f_obj->complete_cmd(
5542 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5543 break;
a3348722 5544
55c11941 5545 } else {
230bb0f3
YM		 5546 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5547
55c11941
MS		 5548 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5549 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5550 f_obj->complete_cmd(bp, f_obj,
5551 BNX2X_F_CMD_AFEX_UPDATE);
5552
5553 /* We will perform the Queues update from
5554 * sp_rtnl task as all Queue SP operations
5555 * should run under rtnl_lock.
5556 */
230bb0f3 5557 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
55c11941 5558 }
a3348722 5559
a3348722
BW		 5560 goto next_spqe;
5561
5562 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5563 f_obj->complete_cmd(bp, f_obj,
5564 BNX2X_F_CMD_AFEX_VIFLISTS);
5565 bnx2x_after_afex_vif_lists(bp, elem);
5566 goto next_spqe;
619c5cb6 5567 case EVENT_RING_OPCODE_FUNCTION_START:
51c1a580
MS		 5568 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5569 "got FUNC_START ramrod\n");
619c5cb6
VZ		 5570 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5571 break;
5572
5573 goto next_spqe;
5574
5575 case EVENT_RING_OPCODE_FUNCTION_STOP:
51c1a580
MS		 5576 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5577 "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 5578 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5579 break;
5580
5581 goto next_spqe;
eeed018c
MK		 5582
5583 case EVENT_RING_OPCODE_SET_TIMESYNC:
5584 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5585 "got set_timesync ramrod completion\n");
5586 if (f_obj->complete_cmd(bp, f_obj,
5587 BNX2X_F_CMD_SET_TIMESYNC))
5588 break;
5589 goto next_spqe;
523224a3
DK		 5590 }
5591
5592 switch (opcode | bp->state) {
619c5cb6
VZ		 5593 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5594 BNX2X_STATE_OPEN):
5595 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 5596 BNX2X_STATE_OPENING_WAIT4_PORT):
28311f8e
YM		 5597 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5598 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 5599 cid = elem->message.data.eth_event.echo &
5600 BNX2X_SWCID_MASK;
d6cae238 5601 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
619c5cb6
VZ		 5602 cid);
5603 rss_raw->clear_pending(rss_raw);
523224a3
DK		 5604 break;
5605
619c5cb6
VZ		 5606 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5607 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5608 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 5609 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 5610 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5611 BNX2X_STATE_OPEN):
5612 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5613 BNX2X_STATE_DIAG):
5614 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5615 BNX2X_STATE_CLOSING_WAIT4_HALT):
05cc5a39 5616 DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
619c5cb6 5617 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 5618 break;
5619
619c5cb6
VZ		 5620 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5621 BNX2X_STATE_OPEN):
5622 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5623 BNX2X_STATE_DIAG):
5624 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5625 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5626 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 5627 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 5628 break;
5629
619c5cb6
VZ		 5630 case (EVENT_RING_OPCODE_FILTERS_RULES |
5631 BNX2X_STATE_OPEN):
5632 case (EVENT_RING_OPCODE_FILTERS_RULES |
5633 BNX2X_STATE_DIAG):
5634 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 5635 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5636 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 5637 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 5638 break;
5639 default:
5640 /* unknown event log error and continue */
619c5cb6
VZ		 5641 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5642 elem->message.opcode, bp->state);
523224a3
DK		 5643 }
5644next_spqe:
5645 spqe_cnt++;
5646 } /* for */
5647
4e857c58 5648 smp_mb__before_atomic();
6e30dd4e 5649 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 5650
5651 bp->eq_cons = sw_cons;
5652 bp->eq_prod = sw_prod;
5653 /* Make sure that above mem writes were issued towards the memory */
5654 smp_wmb();
5655
5656 /* update producer */
5657 bnx2x_update_eq_prod(bp, bp->eq_prod);
5658}
5659
a2fbb9ea
ET		 5660static void bnx2x_sp_task(struct work_struct *work)
5661{
1cf167f2 5662 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea 5663
fd1fc79d 5664 DP(BNX2X_MSG_SP, "sp task invoked\n");
a2fbb9ea 5665
16a5fd92 5666 /* make sure the atomic interrupt_occurred has been written */
fd1fc79d
AE		 5667 smp_rmb();
5668 if (atomic_read(&bp->interrupt_occurred)) {
a2fbb9ea 5669
fd1fc79d
AE		 5670 /* what work needs to be performed? */
5671 u16 status = bnx2x_update_dsb_idx(bp);
cdaa7cb8 5672
fd1fc79d
AE		 5673 DP(BNX2X_MSG_SP, "status %x\n", status);
5674 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5675 atomic_set(&bp->interrupt_occurred, 0);
5676
5677 /* HW attentions */
5678 if (status & BNX2X_DEF_SB_ATT_IDX) {
5679 bnx2x_attn_int(bp);
5680 status &= ~BNX2X_DEF_SB_ATT_IDX;
5681 }
5682
5683 /* SP events: STAT_QUERY and others */
5684 if (status & BNX2X_DEF_SB_IDX) {
5685 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 5686
55c11941 5687 if (FCOE_INIT(bp) &&
fd1fc79d
AE		 5688 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5689 /* Prevent local bottom-halves from running as
5690 * we are going to change the local NAPI list.
5691 */
5692 local_bh_disable();
5693 napi_schedule(&bnx2x_fcoe(bp, napi));
5694 local_bh_enable();
5695 }
5696
5697 /* Handle EQ completions */
5698 bnx2x_eq_int(bp);
5699 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5700 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5701
5702 status &= ~BNX2X_DEF_SB_IDX;
019dbb4c 5703 }
55c11941 5704
fd1fc79d
AE		 5705 /* if status is non zero then perhaps something went wrong */
5706 if (unlikely(status))
5707 DP(BNX2X_MSG_SP,
5708 "got an unknown interrupt! (status 0x%x)\n", status);
523224a3 5709
fd1fc79d
AE		 5710 /* ack status block only if something was actually handled */
5711 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5712 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
cdaa7cb8
VZ		 5713 }
5714
a3348722
BW		 5715 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5716 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5717 &bp->sp_state)) {
5718 bnx2x_link_report(bp);
5719 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5720 }
a2fbb9ea
ET		 5721}
5722
9f6c9258 5723irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 5724{
5725 struct net_device *dev = dev_instance;
5726 struct bnx2x *bp = netdev_priv(dev);
5727
523224a3
DK		 5728 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5729 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 5730
5731#ifdef BNX2X_STOP_ON_ERROR
5732 if (unlikely(bp->panic))
5733 return IRQ_HANDLED;
5734#endif
5735
55c11941 5736 if (CNIC_LOADED(bp)) {
993ac7b5
MC		 5737 struct cnic_ops *c_ops;
5738
5739 rcu_read_lock();
5740 c_ops = rcu_dereference(bp->cnic_ops);
5741 if (c_ops)
5742 c_ops->cnic_handler(bp->cnic_data, NULL);
5743 rcu_read_unlock();
5744 }
55c11941 5745
fd1fc79d
AE		 5746 /* schedule sp task to perform default status block work, ack
5747 * attentions and enable interrupts.
5748 */
5749 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 5750
5751 return IRQ_HANDLED;
5752}
5753
5754/* end of slow path */
5755
619c5cb6
VZ		 5756void bnx2x_drv_pulse(struct bnx2x *bp)
5757{
5758 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5759 bp->fw_drv_pulse_wr_seq);
5760}
5761
a2fbb9ea
ET		 5762static void bnx2x_timer(unsigned long data)
5763{
5764 struct bnx2x *bp = (struct bnx2x *) data;
5765
5766 if (!netif_running(bp->dev))
5767 return;
5768
67c431a5
AE		 5769 if (IS_PF(bp) &&
5770 !BP_NOMCP(bp)) {
f2e0899f 5771 int mb_idx = BP_FW_MB_IDX(bp);
4c868664
EG		 5772 u16 drv_pulse;
5773 u16 mcp_pulse;
a2fbb9ea
ET		 5774
5775 ++bp->fw_drv_pulse_wr_seq;
5776 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
a2fbb9ea 5777 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 5778 bnx2x_drv_pulse(bp);
a2fbb9ea 5779
f2e0899f 5780 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 5781 MCP_PULSE_SEQ_MASK);
5782 /* The delta between driver pulse and mcp response
4c868664
EG		 5783 * should not get too big. If the MFW is more than 5 pulses
5784 * behind, we should worry about it enough to generate an error
5785 * log.
a2fbb9ea 5786 */
4c868664
EG		 5787 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5788 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
a2fbb9ea 5789 drv_pulse, mcp_pulse);
a2fbb9ea
ET		 5790 }
5791
f34d28ea 5792 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 5793 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 5794
abc5a021 5795 /* sample pf vf bulletin board for new posts from pf */
37173488
YM		 5796 if (IS_VF(bp))
5797 bnx2x_timer_sriov(bp);
78c3bcc5 5798
a2fbb9ea
ET		 5799 mod_timer(&bp->timer, jiffies + bp->current_interval);
5800}
5801
5802/* end of Statistics */
5803
5804/* nic init */
5805
5806/*
5807 * nic init service functions
5808 */
5809
1191cb83 5810static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 5811{
523224a3
DK		 5812 u32 i;
5813 if (!(len%4) && !(addr%4))
5814 for (i = 0; i < len; i += 4)
5815 REG_WR(bp, addr + i, fill);
5816 else
5817 for (i = 0; i < len; i++)
5818 REG_WR8(bp, addr + i, fill);
34f80b04
EG		 5819}
5820
523224a3 5821/* helper: writes FP SP data to FW - data_size in dwords */
1191cb83
ED		 5822static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5823 int fw_sb_id,
5824 u32 *sb_data_p,
5825 u32 data_size)
34f80b04 5826{
a2fbb9ea 5827 int index;
523224a3
DK		 5828 for (index = 0; index < data_size; index++)
5829 REG_WR(bp, BAR_CSTRORM_INTMEM +
5830 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5831 sizeof(u32)*index,
5832 *(sb_data_p + index));
5833}
a2fbb9ea 5834
1191cb83 5835static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
523224a3
DK		 5836{
5837 u32 *sb_data_p;
5838 u32 data_size = 0;
f2e0899f 5839 struct hc_status_block_data_e2 sb_data_e2;
523224a3 5840 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 5841
523224a3 5842 /* disable the function first */
619c5cb6 5843 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5844 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5845 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 5846 sb_data_e2.common.p_func.vf_valid = false;
5847 sb_data_p = (u32 *)&sb_data_e2;
5848 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5849 } else {
5850 memset(&sb_data_e1x, 0,
5851 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5852 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 5853 sb_data_e1x.common.p_func.vf_valid = false;
5854 sb_data_p = (u32 *)&sb_data_e1x;
5855 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5856 }
523224a3 5857 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 5858
523224a3
DK		 5859 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5860 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5861 CSTORM_STATUS_BLOCK_SIZE);
5862 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5863 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5864 CSTORM_SYNC_BLOCK_SIZE);
5865}
34f80b04 5866
523224a3 5867/* helper: writes SP SB data to FW */
1191cb83 5868static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
523224a3
DK		 5869 struct hc_sp_status_block_data *sp_sb_data)
5870{
5871 int func = BP_FUNC(bp);
5872 int i;
5873 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5874 REG_WR(bp, BAR_CSTRORM_INTMEM +
5875 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5876 i*sizeof(u32),
5877 *((u32 *)sp_sb_data + i));
34f80b04
EG		 5878}
5879
1191cb83 5880static void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 5881{
5882 int func = BP_FUNC(bp);
523224a3
DK		 5883 struct hc_sp_status_block_data sp_sb_data;
5884 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 5885
619c5cb6 5886 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 5887 sp_sb_data.p_func.vf_valid = false;
5888
5889 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5890
5891 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5892 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5893 CSTORM_SP_STATUS_BLOCK_SIZE);
5894 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5895 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5896 CSTORM_SP_SYNC_BLOCK_SIZE);
523224a3
DK		 5897}
5898
1191cb83 5899static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
523224a3
DK		 5900 int igu_sb_id, int igu_seg_id)
5901{
5902 hc_sm->igu_sb_id = igu_sb_id;
5903 hc_sm->igu_seg_id = igu_seg_id;
5904 hc_sm->timer_value = 0xFF;
5905 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 5906}
5907
150966ad 5908/* allocates state machine ids. */
1191cb83 5909static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
150966ad
AE		 5910{
5911 /* zero out state machine indices */
5912 /* rx indices */
5913 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5914
5915 /* tx indices */
5916 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5917 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5918 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5919 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5920
5921 /* map indices */
5922 /* rx indices */
5923 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5924 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5925
5926 /* tx indices */
5927 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5928 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5929 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5930 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5931 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5932 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5933 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5934 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5935}
5936
b93288d5 5937void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 5938 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 5939{
523224a3
DK		 5940 int igu_seg_id;
5941
f2e0899f 5942 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 5943 struct hc_status_block_data_e1x sb_data_e1x;
5944 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 5945 int data_size;
5946 u32 *sb_data_p;
5947
f2e0899f
DK		 5948 if (CHIP_INT_MODE_IS_BC(bp))
5949 igu_seg_id = HC_SEG_ACCESS_NORM;
5950 else
5951 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 5952
5953 bnx2x_zero_fp_sb(bp, fw_sb_id);
5954
619c5cb6 5955 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5956 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5957 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 5958 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5959 sb_data_e2.common.p_func.vf_id = vfid;
5960 sb_data_e2.common.p_func.vf_valid = vf_valid;
5961 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5962 sb_data_e2.common.same_igu_sb_1b = true;
5963 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5964 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5965 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 5966 sb_data_p = (u32 *)&sb_data_e2;
5967 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 5968 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 5969 } else {
5970 memset(&sb_data_e1x, 0,
5971 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5972 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 5973 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5974 sb_data_e1x.common.p_func.vf_id = 0xff;
5975 sb_data_e1x.common.p_func.vf_valid = false;
5976 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5977 sb_data_e1x.common.same_igu_sb_1b = true;
5978 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5979 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5980 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 5981 sb_data_p = (u32 *)&sb_data_e1x;
5982 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 5983 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 5984 }
523224a3
DK		 5985
5986 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5987 igu_sb_id, igu_seg_id);
5988 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5989 igu_sb_id, igu_seg_id);
5990
51c1a580 5991 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
523224a3 5992
86564c3f 5993 /* write indices to HW - PCI guarantees endianity of regpairs */
523224a3
DK		 5994 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5995}
5996
619c5cb6 5997static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 5998 u16 tx_usec, u16 rx_usec)
5999{
6383c0b3 6000 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 6001 false, rx_usec);
6383c0b3
AE		 6002 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6003 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
6004 tx_usec);
6005 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6006 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6007 tx_usec);
6008 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6009 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6010 tx_usec);
523224a3 6011}
f2e0899f 6012
523224a3
DK		 6013static void bnx2x_init_def_sb(struct bnx2x *bp)
6014{
6015 struct host_sp_status_block *def_sb = bp->def_status_blk;
6016 dma_addr_t mapping = bp->def_status_blk_mapping;
6017 int igu_sp_sb_index;
6018 int igu_seg_id;
34f80b04
EG		 6019 int port = BP_PORT(bp);
6020 int func = BP_FUNC(bp);
f2eaeb58 6021 int reg_offset, reg_offset_en5;
a2fbb9ea 6022 u64 section;
523224a3
DK		 6023 int index;
6024 struct hc_sp_status_block_data sp_sb_data;
6025 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6026
f2e0899f
DK		 6027 if (CHIP_INT_MODE_IS_BC(bp)) {
6028 igu_sp_sb_index = DEF_SB_IGU_ID;
6029 igu_seg_id = HC_SEG_ACCESS_DEF;
6030 } else {
6031 igu_sp_sb_index = bp->igu_dsb_id;
6032 igu_seg_id = IGU_SEG_ACCESS_DEF;
6033 }
a2fbb9ea
ET		 6034
6035 /* ATTN */
523224a3 6036 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 6037 atten_status_block);
523224a3 6038 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 6039
49d66772
ET		 6040 bp->attn_state = 0;
6041
a2fbb9ea
ET		 6042 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6043 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 6044 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6045 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 6046 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 6047 int sindex;
6048 /* take care of sig[0]..sig[4] */
6049 for (sindex = 0; sindex < 4; sindex++)
6050 bp->attn_group[index].sig[sindex] =
6051 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 6052
619c5cb6 6053 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6054 /*
6055 * enable5 is separate from the rest of the registers,
6056 * and therefore the address skip is 4
6057 * and not 16 between the different groups
6058 */
6059 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 6060 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 6061 else
6062 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 6063 }
6064
f2e0899f
DK		 6065 if (bp->common.int_block == INT_BLOCK_HC) {
6066 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6067 HC_REG_ATTN_MSG0_ADDR_L);
6068
6069 REG_WR(bp, reg_offset, U64_LO(section));
6070 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 6071 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6072 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6073 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6074 }
a2fbb9ea 6075
523224a3
DK		 6076 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6077 sp_sb);
a2fbb9ea 6078
523224a3 6079 bnx2x_zero_sp_sb(bp);
a2fbb9ea 6080
86564c3f 6081 /* PCI guarantees endianity of regpairs */
619c5cb6 6082 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 6083 sp_sb_data.host_sb_addr.lo = U64_LO(section);
6084 sp_sb_data.host_sb_addr.hi = U64_HI(section);
6085 sp_sb_data.igu_sb_id = igu_sp_sb_index;
6086 sp_sb_data.igu_seg_id = igu_seg_id;
6087 sp_sb_data.p_func.pf_id = func;
f2e0899f 6088 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 6089 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 6090
523224a3 6091 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 6092
523224a3 6093 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 6094}
6095
9f6c9258 6096void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 6097{
a2fbb9ea
ET		 6098 int i;
6099
ec6ba945 6100 for_each_eth_queue(bp, i)
523224a3 6101 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 6102 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 6103}
6104
a2fbb9ea
ET		 6105static void bnx2x_init_sp_ring(struct bnx2x *bp)
6106{
a2fbb9ea 6107 spin_lock_init(&bp->spq_lock);
6e30dd4e 6108 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 6109
a2fbb9ea 6110 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 6111 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6112 bp->spq_prod_bd = bp->spq;
6113 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 6114}
6115
523224a3 6116static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 6117{
6118 int i;
523224a3
DK		 6119 for (i = 1; i <= NUM_EQ_PAGES; i++) {
6120 union event_ring_elem *elem =
6121 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 6122
523224a3
DK		 6123 elem->next_page.addr.hi =
6124 cpu_to_le32(U64_HI(bp->eq_mapping +
6125 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6126 elem->next_page.addr.lo =
6127 cpu_to_le32(U64_LO(bp->eq_mapping +
6128 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 6129 }
523224a3
DK		 6130 bp->eq_cons = 0;
6131 bp->eq_prod = NUM_EQ_DESC;
6132 bp->eq_cons_sb = BNX2X_EQ_INDEX;
16a5fd92 6133 /* we want a warning message before it gets wrought... */
6e30dd4e
VZ		 6134 atomic_set(&bp->eq_spq_left,
6135 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 6136}
6137
619c5cb6 6138/* called with netif_addr_lock_bh() */
a8f47eb7 6139static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6140 unsigned long rx_mode_flags,
6141 unsigned long rx_accept_flags,
6142 unsigned long tx_accept_flags,
6143 unsigned long ramrod_flags)
ab532cf3 6144{
619c5cb6
VZ		 6145 struct bnx2x_rx_mode_ramrod_params ramrod_param;
6146 int rc;
6147
6148 memset(&ramrod_param, 0, sizeof(ramrod_param));
6149
6150 /* Prepare ramrod parameters */
6151 ramrod_param.cid = 0;
6152 ramrod_param.cl_id = cl_id;
6153 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6154 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 6155
619c5cb6
VZ		 6156 ramrod_param.pstate = &bp->sp_state;
6157 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 6158
619c5cb6
VZ		 6159 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6160 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6161
6162 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6163
6164 ramrod_param.ramrod_flags = ramrod_flags;
6165 ramrod_param.rx_mode_flags = rx_mode_flags;
6166
6167 ramrod_param.rx_accept_flags = rx_accept_flags;
6168 ramrod_param.tx_accept_flags = tx_accept_flags;
6169
6170 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6171 if (rc < 0) {
6172 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
924d75ab 6173 return rc;
619c5cb6 6174 }
924d75ab
YM		 6175
6176 return 0;
a2fbb9ea
ET		 6177}
6178
86564c3f
YM		 6179static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6180 unsigned long *rx_accept_flags,
6181 unsigned long *tx_accept_flags)
471de716 6182{
924d75ab
YM		 6183 /* Clear the flags first */
6184 *rx_accept_flags = 0;
6185 *tx_accept_flags = 0;
619c5cb6 6186
924d75ab 6187 switch (rx_mode) {
619c5cb6
VZ		 6188 case BNX2X_RX_MODE_NONE:
6189 /*
6190 * 'drop all' supersedes any accept flags that may have been
6191 * passed to the function.
6192 */
6193 break;
6194 case BNX2X_RX_MODE_NORMAL:
924d75ab
YM		 6195 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6196 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6197 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6198
6199 /* internal switching mode */
924d75ab
YM		 6200 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6201 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6202 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6 6203
05cc5a39
YM		 6204 if (bp->accept_any_vlan) {
6205 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6206 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6207 }
6208
619c5cb6
VZ		 6209 break;
6210 case BNX2X_RX_MODE_ALLMULTI:
924d75ab
YM		 6211 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6212 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6213 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6214
6215 /* internal switching mode */
924d75ab
YM		 6216 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6217 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6218 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6 6219
05cc5a39
YM		 6220 if (bp->accept_any_vlan) {
6221 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6222 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6223 }
6224
619c5cb6
VZ		 6225 break;
6226 case BNX2X_RX_MODE_PROMISC:
16a5fd92 6227 /* According to definition of SI mode, iface in promisc mode
619c5cb6
VZ		 6228 * should receive matched and unmatched (in resolution of port)
6229 * unicast packets.
6230 */
924d75ab
YM		 6231 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6232 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6233 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6234 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6235
6236 /* internal switching mode */
924d75ab
YM		 6237 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6238 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6239
6240 if (IS_MF_SI(bp))
924d75ab 6241 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
619c5cb6 6242 else
924d75ab 6243 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
619c5cb6 6244
05cc5a39
YM		 6245 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6246 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6247
619c5cb6
VZ		 6248 break;
6249 default:
924d75ab
YM		 6250 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6251 return -EINVAL;
619c5cb6 6252 }
de832a55 6253
924d75ab
YM		 6254 return 0;
6255}
6256
6257/* called with netif_addr_lock_bh() */
a8f47eb7 6258static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
924d75ab
YM		 6259{
6260 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6261 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6262 int rc;
6263
6264 if (!NO_FCOE(bp))
6265 /* Configure rx_mode of FCoE Queue */
6266 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6267
6268 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6269 &tx_accept_flags);
6270 if (rc)
6271 return rc;
6272
619c5cb6
VZ		 6273 __set_bit(RAMROD_RX, &ramrod_flags);
6274 __set_bit(RAMROD_TX, &ramrod_flags);
6275
924d75ab
YM		 6276 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6277 rx_accept_flags, tx_accept_flags,
6278 ramrod_flags);
619c5cb6
VZ		 6279}
6280
6281static void bnx2x_init_internal_common(struct bnx2x *bp)
6282{
6283 int i;
6284
523224a3
DK		 6285 /* Zero this manually as its initialization is
6286 currently missing in the initTool */
6287 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 6288 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 6289 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 6290 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6291 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6292 CHIP_INT_MODE_IS_BC(bp) ?
6293 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6294 }
523224a3 6295}
8a1c38d1 6296
471de716
EG		 6297static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6298{
6299 switch (load_code) {
6300 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 6301 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 6302 bnx2x_init_internal_common(bp);
6303 /* no break */
6304
6305 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 6306 /* nothing to do */
471de716
EG		 6307 /* no break */
6308
6309 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 6310 /* internal memory per function is
6311 initialized inside bnx2x_pf_init */
471de716
EG		 6312 break;
6313
6314 default:
6315 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6316 break;
6317 }
6318}
6319
619c5cb6 6320static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 6321{
55c11941 6322 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6 6323}
523224a3 6324
619c5cb6
VZ		 6325static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6326{
55c11941 6327 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6
VZ		 6328}
6329
1191cb83 6330static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
619c5cb6
VZ		 6331{
6332 if (CHIP_IS_E1x(fp->bp))
6333 return BP_L_ID(fp->bp) + fp->index;
6334 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6335 return bnx2x_fp_igu_sb_id(fp);
6336}
6337
6383c0b3 6338static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 6339{
6340 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 6341 u8 cos;
619c5cb6 6342 unsigned long q_type = 0;
6383c0b3 6343 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 6344 fp->rx_queue = fp_idx;
b3b83c3f 6345 fp->cid = fp_idx;
619c5cb6
VZ		 6346 fp->cl_id = bnx2x_fp_cl_id(fp);
6347 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6348 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 6349 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 6350 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6351
523224a3 6352 /* init shortcut */
619c5cb6 6353 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
7a752993 6354
16a5fd92 6355 /* Setup SB indices */
523224a3 6356 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 6357
619c5cb6
VZ		 6358 /* Configure Queue State object */
6359 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6360 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 6361
6362 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6363
6364 /* init tx data */
6365 for_each_cos_in_tx_queue(fp, cos) {
65565884
MS		 6366 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6367 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6368 FP_COS_TO_TXQ(fp, cos, bp),
6369 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6370 cids[cos] = fp->txdata_ptr[cos]->cid;
6383c0b3
AE		 6371 }
6372
ad5afc89
AE		 6373 /* nothing more for vf to do here */
6374 if (IS_VF(bp))
6375 return;
6376
6377 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6378 fp->fw_sb_id, fp->igu_sb_id);
6379 bnx2x_update_fpsb_idx(fp);
15192a8c
BW		 6380 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6381 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6383c0b3 6382 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 6383
6384 /**
6385 * Configure classification DBs: Always enable Tx switching
6386 */
6387 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6388
ad5afc89
AE		 6389 DP(NETIF_MSG_IFUP,
6390 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6391 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6392 fp->igu_sb_id);
523224a3
DK		 6393}
6394
1191cb83
ED		 6395static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6396{
6397 int i;
6398
6399 for (i = 1; i <= NUM_TX_RINGS; i++) {
6400 struct eth_tx_next_bd *tx_next_bd =
6401 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6402
6403 tx_next_bd->addr_hi =
6404 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6405 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6406 tx_next_bd->addr_lo =
6407 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6408 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6409 }
6410
639d65b8
YM		 6411 *txdata->tx_cons_sb = cpu_to_le16(0);
6412
1191cb83
ED		 6413 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6414 txdata->tx_db.data.zero_fill1 = 0;
6415 txdata->tx_db.data.prod = 0;
6416
6417 txdata->tx_pkt_prod = 0;
6418 txdata->tx_pkt_cons = 0;
6419 txdata->tx_bd_prod = 0;
6420 txdata->tx_bd_cons = 0;
6421 txdata->tx_pkt = 0;
6422}
6423
55c11941
MS		 6424static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6425{
6426 int i;
6427
6428 for_each_tx_queue_cnic(bp, i)
6429 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6430}
d76a6111 6431
1191cb83
ED		 6432static void bnx2x_init_tx_rings(struct bnx2x *bp)
6433{
6434 int i;
6435 u8 cos;
6436
55c11941 6437 for_each_eth_queue(bp, i)
1191cb83 6438 for_each_cos_in_tx_queue(&bp->fp[i], cos)
65565884 6439 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
1191cb83
ED		 6440}
6441
a8f47eb7 6442static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6443{
6444 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6445 unsigned long q_type = 0;
6446
6447 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6448 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6449 BNX2X_FCOE_ETH_CL_ID_IDX);
6450 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6451 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6452 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6453 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6454 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6455 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6456 fp);
6457
6458 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6459
6460 /* qZone id equals to FW (per path) client id */
6461 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6462 /* init shortcut */
6463 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6464 bnx2x_rx_ustorm_prods_offset(fp);
6465
6466 /* Configure Queue State object */
6467 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6468 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6469
6470 /* No multi-CoS for FCoE L2 client */
6471 BUG_ON(fp->max_cos != 1);
6472
6473 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6474 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6475 bnx2x_sp_mapping(bp, q_rdata), q_type);
6476
6477 DP(NETIF_MSG_IFUP,
6478 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6479 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6480 fp->igu_sb_id);
6481}
6482
55c11941 6483void bnx2x_nic_init_cnic(struct bnx2x *bp)
a2fbb9ea 6484{
ec6ba945
VZ		 6485 if (!NO_FCOE(bp))
6486 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 6487
6488 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6489 BNX2X_VF_ID_INVALID, false,
619c5cb6 6490 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 6491
55c11941
MS		 6492 /* ensure status block indices were read */
6493 rmb();
6494 bnx2x_init_rx_rings_cnic(bp);
6495 bnx2x_init_tx_rings_cnic(bp);
6496
6497 /* flush all */
6498 mb();
6499 mmiowb();
6500}
a2fbb9ea 6501
ecf01c22 6502void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
55c11941
MS		 6503{
6504 int i;
6505
ecf01c22 6506 /* Setup NIC internals and enable interrupts */
55c11941
MS		 6507 for_each_eth_queue(bp, i)
6508 bnx2x_init_eth_fp(bp, i);
ad5afc89
AE		 6509
6510 /* ensure status block indices were read */
6511 rmb();
6512 bnx2x_init_rx_rings(bp);
6513 bnx2x_init_tx_rings(bp);
6514
ecf01c22
YM		 6515 if (IS_PF(bp)) {
6516 /* Initialize MOD_ABS interrupts */
6517 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6518 bp->common.shmem_base,
6519 bp->common.shmem2_base, BP_PORT(bp));
ad5afc89 6520
ecf01c22
YM		 6521 /* initialize the default status block and sp ring */
6522 bnx2x_init_def_sb(bp);
6523 bnx2x_update_dsb_idx(bp);
6524 bnx2x_init_sp_ring(bp);
3cdeec22
YM		 6525 } else {
6526 bnx2x_memset_stats(bp);
ecf01c22
YM		 6527 }
6528}
16119785 6529
ecf01c22
YM		 6530void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6531{
523224a3 6532 bnx2x_init_eq_ring(bp);
471de716 6533 bnx2x_init_internal(bp, load_code);
523224a3 6534 bnx2x_pf_init(bp);
0ef00459
EG		 6535 bnx2x_stats_init(bp);
6536
0ef00459
EG		 6537 /* flush all before enabling interrupts */
6538 mb();
6539 mmiowb();
6540
615f8fd9 6541 bnx2x_int_enable(bp);
eb8da205
EG		 6542
6543 /* Check for SPIO5 */
6544 bnx2x_attn_int_deasserted0(bp,
6545 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6546 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 6547}
6548
ecf01c22 6549/* gzip service functions */
a2fbb9ea
ET		 6550static int bnx2x_gunzip_init(struct bnx2x *bp)
6551{
1a983142
FT		 6552 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6553 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 6554 if (bp->gunzip_buf == NULL)
6555 goto gunzip_nomem1;
6556
6557 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6558 if (bp->strm == NULL)
6559 goto gunzip_nomem2;
6560
7ab24bfd 6561 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 6562 if (bp->strm->workspace == NULL)
6563 goto gunzip_nomem3;
6564
6565 return 0;
6566
6567gunzip_nomem3:
6568 kfree(bp->strm);
6569 bp->strm = NULL;
6570
6571gunzip_nomem2:
1a983142
FT		 6572 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6573 bp->gunzip_mapping);
a2fbb9ea
ET		 6574 bp->gunzip_buf = NULL;
6575
6576gunzip_nomem1:
51c1a580 6577 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
a2fbb9ea
ET		 6578 return -ENOMEM;
6579}
6580
6581static void bnx2x_gunzip_end(struct bnx2x *bp)
6582{
b3b83c3f 6583 if (bp->strm) {
7ab24bfd 6584 vfree(bp->strm->workspace);
b3b83c3f
DK		 6585 kfree(bp->strm);
6586 bp->strm = NULL;
6587 }
a2fbb9ea
ET		 6588
6589 if (bp->gunzip_buf) {
1a983142
FT		 6590 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6591 bp->gunzip_mapping);
a2fbb9ea
ET		 6592 bp->gunzip_buf = NULL;
6593 }
6594}
6595
94a78b79 6596static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 6597{
6598 int n, rc;
6599
6600 /* check gzip header */
94a78b79
VZ		 6601 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6602 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 6603 return -EINVAL;
94a78b79 6604 }
a2fbb9ea
ET		 6605
6606 n = 10;
6607
34f80b04 6608#define FNAME 0x8
a2fbb9ea
ET		 6609
6610 if (zbuf[3] & FNAME)
6611 while ((zbuf[n++] != 0) && (n < len));
6612
94a78b79 6613 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 6614 bp->strm->avail_in = len - n;
6615 bp->strm->next_out = bp->gunzip_buf;
6616 bp->strm->avail_out = FW_BUF_SIZE;
6617
6618 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6619 if (rc != Z_OK)
6620 return rc;
6621
6622 rc = zlib_inflate(bp->strm, Z_FINISH);
6623 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 6624 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6625 bp->strm->msg);
a2fbb9ea
ET		 6626
6627 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6628 if (bp->gunzip_outlen & 0x3)
51c1a580
MS		 6629 netdev_err(bp->dev,
6630 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
cdaa7cb8 6631 bp->gunzip_outlen);
a2fbb9ea
ET		 6632 bp->gunzip_outlen >>= 2;
6633
6634 zlib_inflateEnd(bp->strm);
6635
6636 if (rc == Z_STREAM_END)
6637 return 0;
6638
6639 return rc;
6640}
6641
6642/* nic load/unload */
6643
6644/*
34f80b04 6645 * General service functions
a2fbb9ea
ET		 6646 */
6647
6648/* send a NIG loopback debug packet */
6649static void bnx2x_lb_pckt(struct bnx2x *bp)
6650{
a2fbb9ea 6651 u32 wb_write[3];
a2fbb9ea
ET		 6652
6653 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 6654 wb_write[0] = 0x55555555;
6655 wb_write[1] = 0x55555555;
34f80b04 6656 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 6657 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6658
6659 /* NON-IP protocol */
a2fbb9ea
ET		 6660 wb_write[0] = 0x09000000;
6661 wb_write[1] = 0x55555555;
34f80b04 6662 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 6663 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6664}
6665
6666/* some of the internal memories
6667 * are not directly readable from the driver
6668 * to test them we send debug packets
6669 */
6670static int bnx2x_int_mem_test(struct bnx2x *bp)
6671{
6672 int factor;
6673 int count, i;
6674 u32 val = 0;
6675
ad8d3948 6676 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 6677 factor = 120;
ad8d3948
EG		 6678 else if (CHIP_REV_IS_EMUL(bp))
6679 factor = 200;
6680 else
a2fbb9ea 6681 factor = 1;
a2fbb9ea 6682
a2fbb9ea
ET		 6683 /* Disable inputs of parser neighbor blocks */
6684 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6685 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6686 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6687 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6688
6689 /* Write 0 to parser credits for CFC search request */
6690 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6691
6692 /* send Ethernet packet */
6693 bnx2x_lb_pckt(bp);
6694
6695 /* TODO do i reset NIG statistic? */
6696 /* Wait until NIG register shows 1 packet of size 0x10 */
6697 count = 1000 * factor;
6698 while (count) {
34f80b04 6699
a2fbb9ea
ET		 6700 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6701 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6702 if (val == 0x10)
6703 break;
6704
639d65b8 6705 usleep_range(10000, 20000);
a2fbb9ea
ET		 6706 count--;
6707 }
6708 if (val != 0x10) {
6709 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6710 return -1;
6711 }
6712
6713 /* Wait until PRS register shows 1 packet */
6714 count = 1000 * factor;
6715 while (count) {
6716 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 6717 if (val == 1)
6718 break;
6719
639d65b8 6720 usleep_range(10000, 20000);
a2fbb9ea
ET		 6721 count--;
6722 }
6723 if (val != 0x1) {
6724 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6725 return -2;
6726 }
6727
6728 /* Reset and init BRB, PRS */
34f80b04 6729 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 6730 msleep(50);
34f80b04 6731 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 6732 msleep(50);
619c5cb6
VZ		 6733 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6734 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 6735
6736 DP(NETIF_MSG_HW, "part2\n");
6737
6738 /* Disable inputs of parser neighbor blocks */
6739 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6740 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6741 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6742 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6743
6744 /* Write 0 to parser credits for CFC search request */
6745 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6746
6747 /* send 10 Ethernet packets */
6748 for (i = 0; i < 10; i++)
6749 bnx2x_lb_pckt(bp);
6750
6751 /* Wait until NIG register shows 10 + 1
6752 packets of size 11*0x10 = 0xb0 */
6753 count = 1000 * factor;
6754 while (count) {
34f80b04 6755
a2fbb9ea
ET		 6756 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6757 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6758 if (val == 0xb0)
6759 break;
6760
639d65b8 6761 usleep_range(10000, 20000);
a2fbb9ea
ET		 6762 count--;
6763 }
6764 if (val != 0xb0) {
6765 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6766 return -3;
6767 }
6768
6769 /* Wait until PRS register shows 2 packets */
6770 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6771 if (val != 2)
6772 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6773
6774 /* Write 1 to parser credits for CFC search request */
6775 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6776
6777 /* Wait until PRS register shows 3 packets */
6778 msleep(10 * factor);
6779 /* Wait until NIG register shows 1 packet of size 0x10 */
6780 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6781 if (val != 3)
6782 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6783
6784 /* clear NIG EOP FIFO */
6785 for (i = 0; i < 11; i++)
6786 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6787 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6788 if (val != 1) {
6789 BNX2X_ERR("clear of NIG failed\n");
6790 return -4;
6791 }
6792
6793 /* Reset and init BRB, PRS, NIG */
6794 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6795 msleep(50);
6796 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6797 msleep(50);
619c5cb6
VZ		 6798 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6799 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
55c11941
MS		 6800 if (!CNIC_SUPPORT(bp))
6801 /* set NIC mode */
6802 REG_WR(bp, PRS_REG_NIC_MODE, 1);
a2fbb9ea
ET		 6803
6804 /* Enable inputs of parser neighbor blocks */
6805 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6806 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6807 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 6808 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 6809
6810 DP(NETIF_MSG_HW, "done\n");
6811
6812 return 0; /* OK */
6813}
6814
4a33bc03 6815static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea 6816{
b343d002
YM		 6817 u32 val;
6818
a2fbb9ea 6819 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 6820 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6821 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6822 else
6823 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 6824 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6825 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 6826 /*
6827 * mask read length error interrupts in brb for parser
6828 * (parsing unit and 'checksum and crc' unit)
6829 * these errors are legal (PU reads fixed length and CAC can cause
6830 * read length error on truncated packets)
6831 */
6832 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 6833 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6834 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6835 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6836 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6837 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 6838/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6839/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6840 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6841 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6842 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 6843/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6844/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6845 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6846 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6847 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6848 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 6849/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6850/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 6851
b343d002
YM		 6852 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6853 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6854 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6855 if (!CHIP_IS_E1x(bp))
6856 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6857 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6858 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6859
a2fbb9ea
ET		 6860 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6861 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6862 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 6863/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 6864
6865 if (!CHIP_IS_E1x(bp))
6866 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6867 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6868
a2fbb9ea
ET		 6869 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6870 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 6871/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 6872 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 6873}
6874
81f75bbf
EG		 6875static void bnx2x_reset_common(struct bnx2x *bp)
6876{
619c5cb6
VZ		 6877 u32 val = 0x1400;
6878
81f75bbf
EG		 6879 /* reset_common */
6880 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6881 0xd3ffff7f);
619c5cb6
VZ		 6882
6883 if (CHIP_IS_E3(bp)) {
6884 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6885 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6886 }
6887
6888 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6889}
6890
6891static void bnx2x_setup_dmae(struct bnx2x *bp)
6892{
6893 bp->dmae_ready = 0;
6894 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 6895}
6896
573f2035
EG		 6897static void bnx2x_init_pxp(struct bnx2x *bp)
6898{
6899 u16 devctl;
6900 int r_order, w_order;
6901
2a80eebc 6902 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 6903 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6904 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6905 if (bp->mrrs == -1)
6906 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6907 else {
6908 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6909 r_order = bp->mrrs;
6910 }
6911
6912 bnx2x_init_pxp_arb(bp, r_order, w_order);
6913}
fd4ef40d
EG		 6914
6915static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6916{
2145a920 6917 int is_required;
fd4ef40d 6918 u32 val;
2145a920 6919 int port;
fd4ef40d 6920
2145a920
VZ		 6921 if (BP_NOMCP(bp))
6922 return;
6923
6924 is_required = 0;
fd4ef40d
EG		 6925 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6926 SHARED_HW_CFG_FAN_FAILURE_MASK;
6927
6928 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6929 is_required = 1;
6930
6931 /*
6932 * The fan failure mechanism is usually related to the PHY type since
6933 * the power consumption of the board is affected by the PHY. Currently,
6934 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6935 */
6936 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6937 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 6938 is_required |=
d90d96ba
YR		 6939 bnx2x_fan_failure_det_req(
6940 bp,
6941 bp->common.shmem_base,
a22f0788 6942 bp->common.shmem2_base,
d90d96ba 6943 port);
fd4ef40d
EG		 6944 }
6945
6946 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6947
6948 if (is_required == 0)
6949 return;
6950
6951 /* Fan failure is indicated by SPIO 5 */
d6d99a3f 6952 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
fd4ef40d
EG		 6953
6954 /* set to active low mode */
6955 val = REG_RD(bp, MISC_REG_SPIO_INT);
d6d99a3f 6956 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 6957 REG_WR(bp, MISC_REG_SPIO_INT, val);
6958
6959 /* enable interrupt to signal the IGU */
6960 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 6961 val |= MISC_SPIO_SPIO5;
fd4ef40d
EG		 6962 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6963}
6964
c9ee9206 6965void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 6966{
6967 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6968 val &= ~IGU_PF_CONF_FUNC_EN;
6969
6970 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6971 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6972 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6973}
6974
1191cb83 6975static void bnx2x__common_init_phy(struct bnx2x *bp)
619c5cb6
VZ		 6976{
6977 u32 shmem_base[2], shmem2_base[2];
b884d95b
YR		 6978 /* Avoid common init in case MFW supports LFA */
6979 if (SHMEM2_RD(bp, size) >
6980 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6981 return;
619c5cb6
VZ		 6982 shmem_base[0] = bp->common.shmem_base;
6983 shmem2_base[0] = bp->common.shmem2_base;
6984 if (!CHIP_IS_E1x(bp)) {
6985 shmem_base[1] =
6986 SHMEM2_RD(bp, other_shmem_base_addr);
6987 shmem2_base[1] =
6988 SHMEM2_RD(bp, other_shmem2_base_addr);
6989 }
6990 bnx2x_acquire_phy_lock(bp);
6991 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6992 bp->common.chip_id);
6993 bnx2x_release_phy_lock(bp);
6994}
6995
04860eb7
MC		 6996static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6997{
6998 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6999 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
7000 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
7001 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
7002 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
7003
7004 /* make sure this value is 0 */
7005 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
7006
7007 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
7008 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
7009 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
7010 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
7011}
7012
7013static void bnx2x_set_endianity(struct bnx2x *bp)
7014{
7015#ifdef __BIG_ENDIAN
7016 bnx2x_config_endianity(bp, 1);
7017#else
7018 bnx2x_config_endianity(bp, 0);
7019#endif
7020}
7021
7022static void bnx2x_reset_endianity(struct bnx2x *bp)
7023{
7024 bnx2x_config_endianity(bp, 0);
7025}
7026
619c5cb6
VZ		 7027/**
7028 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7029 *
7030 * @bp: driver handle
7031 */
7032static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 7033{
619c5cb6 7034 u32 val;
a2fbb9ea 7035
51c1a580 7036 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 7037
2031bd3a 7038 /*
2de67439 7039 * take the RESET lock to protect undi_unload flow from accessing
2031bd3a
DK		 7040 * registers while we're resetting the chip
7041 */
7a06a122 7042 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 7043
81f75bbf 7044 bnx2x_reset_common(bp);
34f80b04 7045 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 7046
619c5cb6
VZ		 7047 val = 0xfffc;
7048 if (CHIP_IS_E3(bp)) {
7049 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7050 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7051 }
7052 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7053
7a06a122 7054 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 7055
619c5cb6 7056 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 7057
619c5cb6
VZ		 7058 if (!CHIP_IS_E1x(bp)) {
7059 u8 abs_func_id;
f2e0899f
DK		 7060
7061 /**
7062 * 4-port mode or 2-port mode we need to turn of master-enable
7063 * for everyone, after that, turn it back on for self.
7064 * so, we disregard multi-function or not, and always disable
7065 * for all functions on the given path, this means 0,2,4,6 for
7066 * path 0 and 1,3,5,7 for path 1
7067 */
619c5cb6
VZ		 7068 for (abs_func_id = BP_PATH(bp);
7069 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7070 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 7071 REG_WR(bp,
7072 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7073 1);
7074 continue;
7075 }
7076
619c5cb6 7077 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 7078 /* clear pf enable */
7079 bnx2x_pf_disable(bp);
7080 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7081 }
7082 }
a2fbb9ea 7083
619c5cb6 7084 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 7085 if (CHIP_IS_E1(bp)) {
7086 /* enable HW interrupt from PXP on USDM overflow
7087 bit 16 on INT_MASK_0 */
7088 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7089 }
a2fbb9ea 7090
619c5cb6 7091 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 7092 bnx2x_init_pxp(bp);
04860eb7 7093 bnx2x_set_endianity(bp);
523224a3
DK		 7094 bnx2x_ilt_init_page_size(bp, INITOP_SET);
7095
34f80b04
EG		 7096 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7097 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 7098
34f80b04
EG		 7099 /* let the HW do it's magic ... */
7100 msleep(100);
7101 /* finish PXP init */
7102 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7103 if (val != 1) {
7104 BNX2X_ERR("PXP2 CFG failed\n");
7105 return -EBUSY;
7106 }
7107 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7108 if (val != 1) {
7109 BNX2X_ERR("PXP2 RD_INIT failed\n");
7110 return -EBUSY;
7111 }
a2fbb9ea 7112
f2e0899f
DK		 7113 /* Timers bug workaround E2 only. We need to set the entire ILT to
7114 * have entries with value "0" and valid bit on.
7115 * This needs to be done by the first PF that is loaded in a path
7116 * (i.e. common phase)
7117 */
619c5cb6
VZ		 7118 if (!CHIP_IS_E1x(bp)) {
7119/* In E2 there is a bug in the timers block that can cause function 6 / 7
7120 * (i.e. vnic3) to start even if it is marked as "scan-off".
7121 * This occurs when a different function (func2,3) is being marked
7122 * as "scan-off". Real-life scenario for example: if a driver is being
7123 * load-unloaded while func6,7 are down. This will cause the timer to access
7124 * the ilt, translate to a logical address and send a request to read/write.
7125 * Since the ilt for the function that is down is not valid, this will cause
7126 * a translation error which is unrecoverable.
7127 * The Workaround is intended to make sure that when this happens nothing fatal
7128 * will occur. The workaround:
7129 * 1. First PF driver which loads on a path will:
7130 * a. After taking the chip out of reset, by using pretend,
7131 * it will write "0" to the following registers of
7132 * the other vnics.
7133 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7134 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7135 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7136 * And for itself it will write '1' to
7137 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7138 * dmae-operations (writing to pram for example.)
7139 * note: can be done for only function 6,7 but cleaner this
7140 * way.
7141 * b. Write zero+valid to the entire ILT.
7142 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
7143 * VNIC3 (of that port). The range allocated will be the
7144 * entire ILT. This is needed to prevent ILT range error.
7145 * 2. Any PF driver load flow:
7146 * a. ILT update with the physical addresses of the allocated
7147 * logical pages.
7148 * b. Wait 20msec. - note that this timeout is needed to make
7149 * sure there are no requests in one of the PXP internal
7150 * queues with "old" ILT addresses.
7151 * c. PF enable in the PGLC.
7152 * d. Clear the was_error of the PF in the PGLC. (could have
2de67439 7153 * occurred while driver was down)
619c5cb6
VZ		 7154 * e. PF enable in the CFC (WEAK + STRONG)
7155 * f. Timers scan enable
7156 * 3. PF driver unload flow:
7157 * a. Clear the Timers scan_en.
7158 * b. Polling for scan_on=0 for that PF.
7159 * c. Clear the PF enable bit in the PXP.
7160 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7161 * e. Write zero+valid to all ILT entries (The valid bit must
7162 * stay set)
7163 * f. If this is VNIC 3 of a port then also init
7164 * first_timers_ilt_entry to zero and last_timers_ilt_entry
16a5fd92 7165 * to the last entry in the ILT.
619c5cb6
VZ		 7166 *
7167 * Notes:
7168 * Currently the PF error in the PGLC is non recoverable.
7169 * In the future the there will be a recovery routine for this error.
7170 * Currently attention is masked.
7171 * Having an MCP lock on the load/unload process does not guarantee that
7172 * there is no Timer disable during Func6/7 enable. This is because the
7173 * Timers scan is currently being cleared by the MCP on FLR.
7174 * Step 2.d can be done only for PF6/7 and the driver can also check if
7175 * there is error before clearing it. But the flow above is simpler and
7176 * more general.
7177 * All ILT entries are written by zero+valid and not just PF6/7
7178 * ILT entries since in the future the ILT entries allocation for
7179 * PF-s might be dynamic.
7180 */
f2e0899f
DK		 7181 struct ilt_client_info ilt_cli;
7182 struct bnx2x_ilt ilt;
7183 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7184 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7185
b595076a 7186 /* initialize dummy TM client */
f2e0899f
DK		 7187 ilt_cli.start = 0;
7188 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7189 ilt_cli.client_num = ILT_CLIENT_TM;
7190
7191 /* Step 1: set zeroes to all ilt page entries with valid bit on
7192 * Step 2: set the timers first/last ilt entry to point
7193 * to the entire range to prevent ILT range error for 3rd/4th
2de67439 7194 * vnic (this code assumes existence of the vnic)
f2e0899f
DK		 7195 *
7196 * both steps performed by call to bnx2x_ilt_client_init_op()
7197 * with dummy TM client
7198 *
7199 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7200 * and his brother are split registers
7201 */
7202 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7203 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7204 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7205
7206 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7207 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7208 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7209 }
7210
34f80b04
EG		 7211 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7212 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 7213
619c5cb6 7214 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7215 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7216 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 7217 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 7218
619c5cb6 7219 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 7220
7221 /* let the HW do it's magic ... */
7222 do {
7223 msleep(200);
7224 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7225 } while (factor-- && (val != 1));
7226
7227 if (val != 1) {
7228 BNX2X_ERR("ATC_INIT failed\n");
7229 return -EBUSY;
7230 }
7231 }
7232
619c5cb6 7233 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 7234
b56e9670
AE		 7235 bnx2x_iov_init_dmae(bp);
7236
34f80b04
EG		 7237 /* clean the DMAE memory */
7238 bp->dmae_ready = 1;
619c5cb6
VZ		 7239 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7240
7241 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7242
7243 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7244
7245 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 7246
619c5cb6 7247 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 7248
34f80b04
EG		 7249 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7250 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7251 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7252 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7253
619c5cb6 7254 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 7255
523224a3
DK		 7256 /* QM queues pointers table */
7257 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7258
34f80b04
EG		 7259 /* soft reset pulse */
7260 REG_WR(bp, QM_REG_SOFT_RESET, 1);
7261 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 7262
55c11941
MS		 7263 if (CNIC_SUPPORT(bp))
7264 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 7265
619c5cb6 7266 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
b9871bcf 7267
619c5cb6 7268 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 7269 /* enable hw interrupt from doorbell Q */
7270 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 7271
619c5cb6 7272 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 7273
619c5cb6 7274 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 7275 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 7276
f2e0899f 7277 if (!CHIP_IS_E1(bp))
619c5cb6 7278 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 7279
a3348722
BW		 7280 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7281 if (IS_MF_AFEX(bp)) {
7282 /* configure that VNTag and VLAN headers must be
7283 * received in afex mode
7284 */
7285 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7286 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7287 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7288 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7289 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7290 } else {
7291 /* Bit-map indicating which L2 hdrs may appear
7292 * after the basic Ethernet header
7293 */
7294 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7295 bp->path_has_ovlan ? 7 : 6);
7296 }
7297 }
a2fbb9ea 7298
619c5cb6
VZ		 7299 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7300 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7301 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7302 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 7303
619c5cb6
VZ		 7304 if (!CHIP_IS_E1x(bp)) {
7305 /* reset VFC memories */
7306 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7307 VFC_MEMORIES_RST_REG_CAM_RST |
7308 VFC_MEMORIES_RST_REG_RAM_RST);
7309 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7310 VFC_MEMORIES_RST_REG_CAM_RST |
7311 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 7312
619c5cb6
VZ		 7313 msleep(20);
7314 }
a2fbb9ea 7315
619c5cb6
VZ		 7316 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7317 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7318 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7319 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 7320
34f80b04
EG		 7321 /* sync semi rtc */
7322 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7323 0x80000000);
7324 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7325 0x80000000);
a2fbb9ea 7326
619c5cb6
VZ		 7327 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7328 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7329 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 7330
a3348722
BW		 7331 if (!CHIP_IS_E1x(bp)) {
7332 if (IS_MF_AFEX(bp)) {
7333 /* configure that VNTag and VLAN headers must be
7334 * sent in afex mode
7335 */
7336 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7337 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7338 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7339 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7340 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7341 } else {
7342 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7343 bp->path_has_ovlan ? 7 : 6);
7344 }
7345 }
f2e0899f 7346
34f80b04 7347 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 7348
619c5cb6
VZ		 7349 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7350
55c11941
MS		 7351 if (CNIC_SUPPORT(bp)) {
7352 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7353 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7354 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7355 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7356 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7357 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7358 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7359 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7360 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7361 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7362 }
34f80b04 7363 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 7364
34f80b04
EG		 7365 if (sizeof(union cdu_context) != 1024)
7366 /* we currently assume that a context is 1024 bytes */
51c1a580
MS		 7367 dev_alert(&bp->pdev->dev,
7368 "please adjust the size of cdu_context(%ld)\n",
7369 (long)sizeof(union cdu_context));
a2fbb9ea 7370
619c5cb6 7371 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 7372 val = (4 << 24) + (0 << 12) + 1024;
7373 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 7374
619c5cb6 7375 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 7376 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 7377 /* enable context validation interrupt from CFC */
7378 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7379
7380 /* set the thresholds to prevent CFC/CDU race */
7381 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 7382
619c5cb6 7383 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 7384
619c5cb6 7385 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 7386 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7387
619c5cb6
VZ		 7388 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7389 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 7390
34f80b04
EG		 7391 /* Reset PCIE errors for debug */
7392 REG_WR(bp, 0x2814, 0xffffffff);
7393 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 7394
619c5cb6 7395 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7396 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7397 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7398 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7399 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7400 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7401 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7402 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7403 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7404 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7405 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7406 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7407 }
7408
619c5cb6 7409 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 7410 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 7411 /* in E3 this done in per-port section */
7412 if (!CHIP_IS_E3(bp))
7413 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 7414 }
619c5cb6
VZ		 7415 if (CHIP_IS_E1H(bp))
7416 /* not applicable for E2 (and above ...) */
7417 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 7418
7419 if (CHIP_REV_IS_SLOW(bp))
7420 msleep(200);
7421
7422 /* finish CFC init */
7423 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7424 if (val != 1) {
7425 BNX2X_ERR("CFC LL_INIT failed\n");
7426 return -EBUSY;
7427 }
7428 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7429 if (val != 1) {
7430 BNX2X_ERR("CFC AC_INIT failed\n");
7431 return -EBUSY;
7432 }
7433 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7434 if (val != 1) {
7435 BNX2X_ERR("CFC CAM_INIT failed\n");
7436 return -EBUSY;
7437 }
7438 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 7439
f2e0899f
DK		 7440 if (CHIP_IS_E1(bp)) {
7441 /* read NIG statistic
7442 to see if this is our first up since powerup */
7443 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7444 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 7445
f2e0899f
DK		 7446 /* do internal memory self test */
7447 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7448 BNX2X_ERR("internal mem self test failed\n");
7449 return -EBUSY;
7450 }
34f80b04
EG		 7451 }
7452
fd4ef40d
EG		 7453 bnx2x_setup_fan_failure_detection(bp);
7454
34f80b04
EG		 7455 /* clear PXP2 attentions */
7456 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 7457
4a33bc03 7458 bnx2x_enable_blocks_attention(bp);
c9ee9206 7459 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 7460
6bbca910 7461 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 7462 if (CHIP_IS_E1x(bp))
7463 bnx2x__common_init_phy(bp);
6bbca910
YR		 7464 } else
7465 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7466
230d00eb
YM		 7467 if (SHMEM2_HAS(bp, netproc_fw_ver))
7468 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7469
34f80b04
EG		 7470 return 0;
7471}
a2fbb9ea 7472
619c5cb6
VZ		 7473/**
7474 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7475 *
7476 * @bp: driver handle
7477 */
7478static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7479{
7480 int rc = bnx2x_init_hw_common(bp);
7481
7482 if (rc)
7483 return rc;
7484
7485 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7486 if (!BP_NOMCP(bp))
7487 bnx2x__common_init_phy(bp);
7488
7489 return 0;
7490}
7491
523224a3 7492static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 7493{
7494 int port = BP_PORT(bp);
619c5cb6 7495 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 7496 u32 low, high;
4293b9f5 7497 u32 val, reg;
a2fbb9ea 7498
51c1a580 7499 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
34f80b04
EG		 7500
7501 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 7502
619c5cb6
VZ		 7503 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7504 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7505 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 7506
f2e0899f
DK		 7507 /* Timers bug workaround: disables the pf_master bit in pglue at
7508 * common phase, we need to enable it here before any dmae access are
7509 * attempted. Therefore we manually added the enable-master to the
7510 * port phase (it also happens in the function phase)
7511 */
619c5cb6 7512 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7513 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7514
619c5cb6
VZ		 7515 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7516 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7517 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7518 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7519
7520 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7521 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7522 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7523 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 7524
523224a3
DK		 7525 /* QM cid (connection) count */
7526 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 7527
55c11941
MS		 7528 if (CNIC_SUPPORT(bp)) {
7529 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7530 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7531 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7532 }
cdaa7cb8 7533
619c5cb6 7534 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f 7535
2b674047
DK		 7536 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7537
f2e0899f 7538 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 7539
7540 if (IS_MF(bp))
7541 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7542 else if (bp->dev->mtu > 4096) {
7543 if (bp->flags & ONE_PORT_FLAG)
7544 low = 160;
7545 else {
7546 val = bp->dev->mtu;
7547 /* (24*1024 + val*4)/256 */
7548 low = 96 + (val/64) +
7549 ((val % 64) ? 1 : 0);
7550 }
7551 } else
7552 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7553 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 7554 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7555 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 7556 }
1c06328c 7557
619c5cb6
VZ		 7558 if (CHIP_MODE_IS_4_PORT(bp))
7559 REG_WR(bp, (BP_PORT(bp) ?
7560 BRB1_REG_MAC_GUARANTIED_1 :
7561 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 7562
619c5cb6 7563 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
a3348722
BW		 7564 if (CHIP_IS_E3B0(bp)) {
7565 if (IS_MF_AFEX(bp)) {
7566 /* configure headers for AFEX mode */
7567 REG_WR(bp, BP_PORT(bp) ?
7568 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7569 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7570 REG_WR(bp, BP_PORT(bp) ?
7571 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7572 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7573 REG_WR(bp, BP_PORT(bp) ?
7574 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7575 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7576 } else {
7577 /* Ovlan exists only if we are in multi-function +
7578 * switch-dependent mode, in switch-independent there
7579 * is no ovlan headers
7580 */
7581 REG_WR(bp, BP_PORT(bp) ?
7582 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7583 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7584 (bp->path_has_ovlan ? 7 : 6));
7585 }
7586 }
356e2385 7587
619c5cb6
VZ		 7588 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7589 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7590 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7591 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 7592
619c5cb6
VZ		 7593 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7594 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7595 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7596 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 7597
619c5cb6
VZ		 7598 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7599 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 7600
619c5cb6
VZ		 7601 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7602
7603 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7604 /* configure PBF to work without PAUSE mtu 9000 */
7605 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 7606
f2e0899f
DK		 7607 /* update threshold */
7608 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7609 /* update init credit */
7610 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 7611
f2e0899f
DK		 7612 /* probe changes */
7613 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7614 udelay(50);
7615 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7616 }
a2fbb9ea 7617
55c11941
MS		 7618 if (CNIC_SUPPORT(bp))
7619 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7620
619c5cb6
VZ		 7621 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7622 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 7623
7624 if (CHIP_IS_E1(bp)) {
7625 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7626 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7627 }
619c5cb6 7628 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 7629
619c5cb6 7630 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7631
619c5cb6 7632 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04 7633 /* init aeu_mask_attn_func_0/1:
16a5fd92
YM		 7634 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7635 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
34f80b04 7636 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 7637 val = IS_MF(bp) ? 0xF7 : 0x7;
7638 /* Enable DCBX attention for all but E1 */
7639 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7640 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 7641
4293b9f5
DK		 7642 /* SCPAD_PARITY should NOT trigger close the gates */
7643 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7644 REG_WR(bp, reg,
7645 REG_RD(bp, reg) &
7646 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7647
7648 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7649 REG_WR(bp, reg,
7650 REG_RD(bp, reg) &
7651 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7652
619c5cb6
VZ		 7653 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7654
7655 if (!CHIP_IS_E1x(bp)) {
7656 /* Bit-map indicating which L2 hdrs may appear after the
7657 * basic Ethernet header
7658 */
a3348722
BW		 7659 if (IS_MF_AFEX(bp))
7660 REG_WR(bp, BP_PORT(bp) ?
7661 NIG_REG_P1_HDRS_AFTER_BASIC :
7662 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7663 else
7664 REG_WR(bp, BP_PORT(bp) ?
7665 NIG_REG_P1_HDRS_AFTER_BASIC :
7666 NIG_REG_P0_HDRS_AFTER_BASIC,
7667 IS_MF_SD(bp) ? 7 : 6);
619c5cb6
VZ		 7668
7669 if (CHIP_IS_E3(bp))
7670 REG_WR(bp, BP_PORT(bp) ?
7671 NIG_REG_LLH1_MF_MODE :
7672 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7673 }
7674 if (!CHIP_IS_E3(bp))
7675 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 7676
f2e0899f 7677 if (!CHIP_IS_E1(bp)) {
fb3bff17 7678 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 7679 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 7680 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 7681
619c5cb6 7682 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7683 val = 0;
7684 switch (bp->mf_mode) {
7685 case MULTI_FUNCTION_SD:
7686 val = 1;
7687 break;
7688 case MULTI_FUNCTION_SI:
a3348722 7689 case MULTI_FUNCTION_AFEX:
f2e0899f
DK		 7690 val = 2;
7691 break;
7692 }
7693
7694 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7695 NIG_REG_LLH0_CLS_TYPE), val);
7696 }
1c06328c
EG		 7697 {
7698 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7699 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7700 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7701 }
34f80b04
EG		 7702 }
7703
619c5cb6
VZ		 7704 /* If SPIO5 is set to generate interrupts, enable it for this port */
7705 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 7706 if (val & MISC_SPIO_SPIO5) {
4d295db0
EG		 7707 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7708 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7709 val = REG_RD(bp, reg_addr);
f1410647 7710 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 7711 REG_WR(bp, reg_addr, val);
f1410647 7712 }
a2fbb9ea 7713
34f80b04
EG		 7714 return 0;
7715}
7716
34f80b04
EG		 7717static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7718{
7719 int reg;
32d68de1 7720 u32 wb_write[2];
34f80b04 7721
f2e0899f 7722 if (CHIP_IS_E1(bp))
34f80b04 7723 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 7724 else
7725 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04 7726
32d68de1
YM		 7727 wb_write[0] = ONCHIP_ADDR1(addr);
7728 wb_write[1] = ONCHIP_ADDR2(addr);
7729 REG_WR_DMAE(bp, reg, wb_write, 2);
34f80b04
EG		 7730}
7731
b56e9670 7732void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
1191cb83
ED		 7733{
7734 u32 data, ctl, cnt = 100;
7735 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7736 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7737 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7738 u32 sb_bit = 1 << (idu_sb_id%32);
b56e9670 7739 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
1191cb83
ED		 7740 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7741
7742 /* Not supported in BC mode */
7743 if (CHIP_INT_MODE_IS_BC(bp))
7744 return;
7745
7746 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7747 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7748 IGU_REGULAR_CLEANUP_SET |
7749 IGU_REGULAR_BCLEANUP;
7750
7751 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7752 func_encode << IGU_CTRL_REG_FID_SHIFT |
7753 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7754
7755 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7756 data, igu_addr_data);
7757 REG_WR(bp, igu_addr_data, data);
7758 mmiowb();
7759 barrier();
7760 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7761 ctl, igu_addr_ctl);
7762 REG_WR(bp, igu_addr_ctl, ctl);
7763 mmiowb();
7764 barrier();
7765
7766 /* wait for clean up to finish */
7767 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7768 msleep(20);
7769
1191cb83
ED		 7770 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7771 DP(NETIF_MSG_HW,
7772 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7773 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7774 }
7775}
7776
7777static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
f2e0899f 7778{
619c5cb6 7779 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 7780}
7781
1191cb83 7782static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
f2e0899f
DK		 7783{
7784 u32 i, base = FUNC_ILT_BASE(func);
7785 for (i = base; i < base + ILT_PER_FUNC; i++)
7786 bnx2x_ilt_wr(bp, i, 0);
7787}
7788
910cc727 7789static void bnx2x_init_searcher(struct bnx2x *bp)
55c11941
MS		 7790{
7791 int port = BP_PORT(bp);
7792 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7793 /* T1 hash bits value determines the T1 number of entries */
7794 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7795}
7796
7797static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7798{
7799 int rc;
7800 struct bnx2x_func_state_params func_params = {NULL};
7801 struct bnx2x_func_switch_update_params *switch_update_params =
7802 &func_params.params.switch_update;
7803
7804 /* Prepare parameters for function state transitions */
7805 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7806 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7807
7808 func_params.f_obj = &bp->func_obj;
7809 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7810
7811 /* Function parameters */
e42780b6
DK		 7812 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7813 &switch_update_params->changes);
7814 if (suspend)
7815 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7816 &switch_update_params->changes);
55c11941
MS		 7817
7818 rc = bnx2x_func_state_change(bp, &func_params);
7819
7820 return rc;
7821}
7822
910cc727 7823static int bnx2x_reset_nic_mode(struct bnx2x *bp)
55c11941
MS		 7824{
7825 int rc, i, port = BP_PORT(bp);
7826 int vlan_en = 0, mac_en[NUM_MACS];
7827
55c11941
MS		 7828 /* Close input from network */
7829 if (bp->mf_mode == SINGLE_FUNCTION) {
7830 bnx2x_set_rx_filter(&bp->link_params, 0);
7831 } else {
7832 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7833 NIG_REG_LLH0_FUNC_EN);
7834 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7835 NIG_REG_LLH0_FUNC_EN, 0);
7836 for (i = 0; i < NUM_MACS; i++) {
7837 mac_en[i] = REG_RD(bp, port ?
7838 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7839 4 * i) :
7840 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7841 4 * i));
7842 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7843 4 * i) :
7844 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7845 }
7846 }
7847
7848 /* Close BMC to host */
7849 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7850 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7851
7852 /* Suspend Tx switching to the PF. Completion of this ramrod
7853 * further guarantees that all the packets of that PF / child
7854 * VFs in BRB were processed by the Parser, so it is safe to
7855 * change the NIC_MODE register.
7856 */
7857 rc = bnx2x_func_switch_update(bp, 1);
7858 if (rc) {
7859 BNX2X_ERR("Can't suspend tx-switching!\n");
7860 return rc;
7861 }
7862
7863 /* Change NIC_MODE register */
7864 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7865
7866 /* Open input from network */
7867 if (bp->mf_mode == SINGLE_FUNCTION) {
7868 bnx2x_set_rx_filter(&bp->link_params, 1);
7869 } else {
7870 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7871 NIG_REG_LLH0_FUNC_EN, vlan_en);
7872 for (i = 0; i < NUM_MACS; i++) {
7873 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7874 4 * i) :
7875 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7876 mac_en[i]);
7877 }
7878 }
7879
7880 /* Enable BMC to host */
7881 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7882 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7883
7884 /* Resume Tx switching to the PF */
7885 rc = bnx2x_func_switch_update(bp, 0);
7886 if (rc) {
7887 BNX2X_ERR("Can't resume tx-switching!\n");
7888 return rc;
7889 }
7890
7891 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7892 return 0;
7893}
7894
7895int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7896{
7897 int rc;
7898
7899 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7900
7901 if (CONFIGURE_NIC_MODE(bp)) {
16a5fd92 7902 /* Configure searcher as part of function hw init */
55c11941
MS		 7903 bnx2x_init_searcher(bp);
7904
7905 /* Reset NIC mode */
7906 rc = bnx2x_reset_nic_mode(bp);
7907 if (rc)
7908 BNX2X_ERR("Can't change NIC mode!\n");
7909 return rc;
7910 }
7911
7912 return 0;
7913}
7914
da254fbc
YM		 7915/* previous driver DMAE transaction may have occurred when pre-boot stage ended
7916 * and boot began, or when kdump kernel was loaded. Either case would invalidate
7917 * the addresses of the transaction, resulting in was-error bit set in the pci
7918 * causing all hw-to-host pcie transactions to timeout. If this happened we want
7919 * to clear the interrupt which detected this from the pglueb and the was done
7920 * bit
7921 */
7922static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7923{
7924 if (!CHIP_IS_E1x(bp))
7925 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7926 1 << BP_ABS_FUNC(bp));
7927}
7928
523224a3 7929static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 7930{
7931 int port = BP_PORT(bp);
7932 int func = BP_FUNC(bp);
619c5cb6 7933 int init_phase = PHASE_PF0 + func;
523224a3
DK		 7934 struct bnx2x_ilt *ilt = BP_ILT(bp);
7935 u16 cdu_ilt_start;
8badd27a 7936 u32 addr, val;
f4a66897 7937 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
89db4ad8 7938 int i, main_mem_width, rc;
34f80b04 7939
51c1a580 7940 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
34f80b04 7941
619c5cb6 7942 /* FLR cleanup - hmmm */
89db4ad8
AE		 7943 if (!CHIP_IS_E1x(bp)) {
7944 rc = bnx2x_pf_flr_clnup(bp);
04c46736
YM		 7945 if (rc) {
7946 bnx2x_fw_dump(bp);
89db4ad8 7947 return rc;
04c46736 7948 }
89db4ad8 7949 }
619c5cb6 7950
8badd27a 7951 /* set MSI reconfigure capability */
f2e0899f
DK		 7952 if (bp->common.int_block == INT_BLOCK_HC) {
7953 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7954 val = REG_RD(bp, addr);
7955 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7956 REG_WR(bp, addr, val);
7957 }
8badd27a 7958
619c5cb6
VZ		 7959 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7960 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7961
523224a3
DK		 7962 ilt = BP_ILT(bp);
7963 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 7964
290ca2bb
AE		 7965 if (IS_SRIOV(bp))
7966 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7967 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7968
7969 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7970 * those of the VFs, so start line should be reset
7971 */
7972 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
523224a3 7973 for (i = 0; i < L2_ILT_LINES(bp); i++) {
a052997e 7974 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
523224a3 7975 ilt->lines[cdu_ilt_start + i].page_mapping =
a052997e
MS		 7976 bp->context[i].cxt_mapping;
7977 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
37b091ba 7978 }
290ca2bb 7979
523224a3 7980 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 7981
55c11941
MS		 7982 if (!CONFIGURE_NIC_MODE(bp)) {
7983 bnx2x_init_searcher(bp);
7984 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7985 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7986 } else {
7987 /* Set NIC mode */
7988 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6bf07b8e 7989 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
55c11941 7990 }
37b091ba 7991
619c5cb6 7992 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7993 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7994
7995 /* Turn on a single ISR mode in IGU if driver is going to use
7996 * INT#x or MSI
7997 */
7998 if (!(bp->flags & USING_MSIX_FLAG))
7999 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
8000 /*
8001 * Timers workaround bug: function init part.
8002 * Need to wait 20msec after initializing ILT,
8003 * needed to make sure there are no requests in
8004 * one of the PXP internal queues with "old" ILT addresses
8005 */
8006 msleep(20);
8007 /*
8008 * Master enable - Due to WB DMAE writes performed before this
8009 * register is re-initialized as part of the regular function
8010 * init
8011 */
8012 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
8013 /* Enable the function in IGU */
8014 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
8015 }
8016
523224a3 8017 bp->dmae_ready = 1;
34f80b04 8018
619c5cb6 8019 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 8020
da254fbc 8021 bnx2x_clean_pglue_errors(bp);
f2e0899f 8022
619c5cb6
VZ		 8023 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
8024 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
8025 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
8026 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
8027 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
8028 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
8029 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
8030 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8031 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8032 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8033 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8034 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8035 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8036
8037 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 8038 REG_WR(bp, QM_REG_PF_EN, 1);
8039
619c5cb6
VZ		 8040 if (!CHIP_IS_E1x(bp)) {
8041 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8042 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8043 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8044 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8045 }
8046 bnx2x_init_block(bp, BLOCK_QM, init_phase);
8047
8048 bnx2x_init_block(bp, BLOCK_TM, init_phase);
8049 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
c19d65c9 8050 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
b56e9670
AE		 8051
8052 bnx2x_iov_init_dq(bp);
8053
619c5cb6
VZ		 8054 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8055 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8056 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8057 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8058 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8059 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8060 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8061 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8062 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8063 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 8064 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8065
619c5cb6 8066 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 8067
619c5cb6 8068 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 8069
619c5cb6 8070 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 8071 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8072
fb3bff17 8073 if (IS_MF(bp)) {
7609647e
YM		 8074 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8075 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8076 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8077 bp->mf_ov);
8078 }
34f80b04
EG		 8079 }
8080
619c5cb6 8081 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 8082
34f80b04 8083 /* HC init per function */
f2e0899f
DK		 8084 if (bp->common.int_block == INT_BLOCK_HC) {
8085 if (CHIP_IS_E1H(bp)) {
8086 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8087
8088 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8089 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8090 }
619c5cb6 8091 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 8092
8093 } else {
8094 int num_segs, sb_idx, prod_offset;
8095
34f80b04
EG		 8096 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8097
619c5cb6 8098 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 8099 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8100 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8101 }
8102
619c5cb6 8103 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 8104
619c5cb6 8105 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 8106 int dsb_idx = 0;
8107 /**
8108 * Producer memory:
8109 * E2 mode: address 0-135 match to the mapping memory;
8110 * 136 - PF0 default prod; 137 - PF1 default prod;
8111 * 138 - PF2 default prod; 139 - PF3 default prod;
8112 * 140 - PF0 attn prod; 141 - PF1 attn prod;
8113 * 142 - PF2 attn prod; 143 - PF3 attn prod;
8114 * 144-147 reserved.
8115 *
8116 * E1.5 mode - In backward compatible mode;
8117 * for non default SB; each even line in the memory
8118 * holds the U producer and each odd line hold
8119 * the C producer. The first 128 producers are for
8120 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8121 * producers are for the DSB for each PF.
8122 * Each PF has five segments: (the order inside each
8123 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8124 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8125 * 144-147 attn prods;
8126 */
8127 /* non-default-status-blocks */
8128 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8129 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8130 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8131 prod_offset = (bp->igu_base_sb + sb_idx) *
8132 num_segs;
8133
8134 for (i = 0; i < num_segs; i++) {
8135 addr = IGU_REG_PROD_CONS_MEMORY +
8136 (prod_offset + i) * 4;
8137 REG_WR(bp, addr, 0);
8138 }
8139 /* send consumer update with value 0 */
8140 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8141 USTORM_ID, 0, IGU_INT_NOP, 1);
8142 bnx2x_igu_clear_sb(bp,
8143 bp->igu_base_sb + sb_idx);
8144 }
8145
8146 /* default-status-blocks */
8147 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8148 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8149
8150 if (CHIP_MODE_IS_4_PORT(bp))
8151 dsb_idx = BP_FUNC(bp);
8152 else
3395a033 8153 dsb_idx = BP_VN(bp);
f2e0899f
DK		 8154
8155 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8156 IGU_BC_BASE_DSB_PROD + dsb_idx :
8157 IGU_NORM_BASE_DSB_PROD + dsb_idx);
8158
3395a033
DK		 8159 /*
8160 * igu prods come in chunks of E1HVN_MAX (4) -
8161 * does not matters what is the current chip mode
8162 */
f2e0899f
DK		 8163 for (i = 0; i < (num_segs * E1HVN_MAX);
8164 i += E1HVN_MAX) {
8165 addr = IGU_REG_PROD_CONS_MEMORY +
8166 (prod_offset + i)*4;
8167 REG_WR(bp, addr, 0);
8168 }
8169 /* send consumer update with 0 */
8170 if (CHIP_INT_MODE_IS_BC(bp)) {
8171 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8172 USTORM_ID, 0, IGU_INT_NOP, 1);
8173 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8174 CSTORM_ID, 0, IGU_INT_NOP, 1);
8175 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8176 XSTORM_ID, 0, IGU_INT_NOP, 1);
8177 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8178 TSTORM_ID, 0, IGU_INT_NOP, 1);
8179 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8180 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8181 } else {
8182 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8183 USTORM_ID, 0, IGU_INT_NOP, 1);
8184 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8185 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8186 }
8187 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8188
16a5fd92 8189 /* !!! These should become driver const once
f2e0899f
DK		 8190 rf-tool supports split-68 const */
8191 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8192 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8193 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8194 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8195 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8196 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8197 }
34f80b04 8198 }
34f80b04 8199
c14423fe 8200 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 8201 REG_WR(bp, 0x2114, 0xffffffff);
8202 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 8203
f4a66897
VZ		 8204 if (CHIP_IS_E1x(bp)) {
8205 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8206 main_mem_base = HC_REG_MAIN_MEMORY +
8207 BP_PORT(bp) * (main_mem_size * 4);
8208 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8209 main_mem_width = 8;
8210
8211 val = REG_RD(bp, main_mem_prty_clr);
8212 if (val)
51c1a580
MS		 8213 DP(NETIF_MSG_HW,
8214 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8215 val);
f4a66897
VZ		 8216
8217 /* Clear "false" parity errors in MSI-X table */
8218 for (i = main_mem_base;
8219 i < main_mem_base + main_mem_size * 4;
8220 i += main_mem_width) {
8221 bnx2x_read_dmae(bp, i, main_mem_width / 4);
8222 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8223 i, main_mem_width / 4);
8224 }
8225 /* Clear HC parity attention */
8226 REG_RD(bp, main_mem_prty_clr);
8227 }
8228
619c5cb6
VZ		 8229#ifdef BNX2X_STOP_ON_ERROR
8230 /* Enable STORMs SP logging */
8231 REG_WR8(bp, BAR_USTRORM_INTMEM +
8232 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8233 REG_WR8(bp, BAR_TSTRORM_INTMEM +
8234 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8235 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8236 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8237 REG_WR8(bp, BAR_XSTRORM_INTMEM +
8238 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8239#endif
8240
b7737c9b 8241 bnx2x_phy_probe(&bp->link_params);
f85582f8 8242
34f80b04
EG		 8243 return 0;
8244}
8245
55c11941
MS		 8246void bnx2x_free_mem_cnic(struct bnx2x *bp)
8247{
8248 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8249
8250 if (!CHIP_IS_E1x(bp))
8251 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8252 sizeof(struct host_hc_status_block_e2));
8253 else
8254 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8255 sizeof(struct host_hc_status_block_e1x));
8256
8257 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8258}
8259
9f6c9258 8260void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 8261{
a052997e
MS		 8262 int i;
8263
619c5cb6
VZ		 8264 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8265 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8266
b4cddbd6
AE		 8267 if (IS_VF(bp))
8268 return;
8269
8270 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8271 sizeof(struct host_sp_status_block));
8272
a2fbb9ea 8273 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 8274 sizeof(struct bnx2x_slowpath));
a2fbb9ea 8275
a052997e
MS		 8276 for (i = 0; i < L2_ILT_LINES(bp); i++)
8277 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8278 bp->context[i].size);
523224a3
DK		 8279 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8280
8281 BNX2X_FREE(bp->ilt->lines);
f85582f8 8282
7a9b2557 8283 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 8284
523224a3
DK		 8285 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8286 BCM_PAGE_SIZE * NUM_EQ_PAGES);
580d9d08 8287
05952246
YM		 8288 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8289
580d9d08 8290 bnx2x_iov_free_mem(bp);
619c5cb6
VZ		 8291}
8292
55c11941 8293int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
a2fbb9ea 8294{
cd2b0389 8295 if (!CHIP_IS_E1x(bp)) {
619c5cb6 8296 /* size = the status block + ramrod buffers */
cd2b0389
JP		 8297 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8298 sizeof(struct host_hc_status_block_e2));
8299 if (!bp->cnic_sb.e2_sb)
8300 goto alloc_mem_err;
8301 } else {
8302 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8303 sizeof(struct host_hc_status_block_e1x));
8304 if (!bp->cnic_sb.e1x_sb)
8305 goto alloc_mem_err;
8306 }
8badd27a 8307
cd2b0389 8308 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
16a5fd92 8309 /* allocate searcher T2 table, as it wasn't allocated before */
cd2b0389
JP		 8310 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8311 if (!bp->t2)
8312 goto alloc_mem_err;
8313 }
55c11941
MS		 8314
8315 /* write address to which L5 should insert its values */
8316 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8317 &bp->slowpath->drv_info_to_mcp;
8318
8319 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8320 goto alloc_mem_err;
8321
8322 return 0;
8323
8324alloc_mem_err:
8325 bnx2x_free_mem_cnic(bp);
8326 BNX2X_ERR("Can't allocate memory\n");
8327 return -ENOMEM;
8328}
8329
8330int bnx2x_alloc_mem(struct bnx2x *bp)
8331{
8332 int i, allocated, context_size;
a2fbb9ea 8333
cd2b0389 8334 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
55c11941 8335 /* allocate searcher T2 table */
cd2b0389
JP		 8336 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8337 if (!bp->t2)
8338 goto alloc_mem_err;
8339 }
8badd27a 8340
cd2b0389
JP		 8341 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8342 sizeof(struct host_sp_status_block));
8343 if (!bp->def_status_blk)
8344 goto alloc_mem_err;
a2fbb9ea 8345
cd2b0389
JP		 8346 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8347 sizeof(struct bnx2x_slowpath));
8348 if (!bp->slowpath)
8349 goto alloc_mem_err;
a2fbb9ea 8350
a052997e
MS		 8351 /* Allocate memory for CDU context:
8352 * This memory is allocated separately and not in the generic ILT
8353 * functions because CDU differs in few aspects:
8354 * 1. There are multiple entities allocating memory for context -
8355 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8356 * its own ILT lines.
8357 * 2. Since CDU page-size is not a single 4KB page (which is the case
8358 * for the other ILT clients), to be efficient we want to support
8359 * allocation of sub-page-size in the last entry.
8360 * 3. Context pointers are used by the driver to pass to FW / update
8361 * the context (for the other ILT clients the pointers are used just to
8362 * free the memory during unload).
8363 */
8364 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
65abd74d 8365
a052997e
MS		 8366 for (i = 0, allocated = 0; allocated < context_size; i++) {
8367 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8368 (context_size - allocated));
cd2b0389
JP		 8369 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8370 bp->context[i].size);
8371 if (!bp->context[i].vcxt)
8372 goto alloc_mem_err;
a052997e
MS		 8373 allocated += bp->context[i].size;
8374 }
cd2b0389
JP		 8375 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8376 GFP_KERNEL);
8377 if (!bp->ilt->lines)
8378 goto alloc_mem_err;
65abd74d 8379
523224a3
DK		 8380 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8381 goto alloc_mem_err;
65abd74d 8382
67c431a5
AE		 8383 if (bnx2x_iov_alloc_mem(bp))
8384 goto alloc_mem_err;
8385
9f6c9258 8386 /* Slow path ring */
cd2b0389
JP		 8387 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8388 if (!bp->spq)
8389 goto alloc_mem_err;
65abd74d 8390
523224a3 8391 /* EQ */
cd2b0389
JP		 8392 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8393 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8394 if (!bp->eq_ring)
8395 goto alloc_mem_err;
ab532cf3 8396
9f6c9258 8397 return 0;
e1510706 8398
9f6c9258
DK		 8399alloc_mem_err:
8400 bnx2x_free_mem(bp);
51c1a580 8401 BNX2X_ERR("Can't allocate memory\n");
9f6c9258 8402 return -ENOMEM;
65abd74d
YG		 8403}
8404
a2fbb9ea
ET		 8405/*
8406 * Init service functions
8407 */
a2fbb9ea 8408
619c5cb6
VZ		 8409int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8410 struct bnx2x_vlan_mac_obj *obj, bool set,
8411 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 8412{
619c5cb6
VZ		 8413 int rc;
8414 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 8415
619c5cb6 8416 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 8417
619c5cb6
VZ		 8418 /* Fill general parameters */
8419 ramrod_param.vlan_mac_obj = obj;
8420 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 8421
619c5cb6
VZ		 8422 /* Fill a user request section if needed */
8423 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8424 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 8425
619c5cb6 8426 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 8427
619c5cb6
VZ		 8428 /* Set the command: ADD or DEL */
8429 if (set)
8430 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8431 else
8432 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 8433 }
8434
619c5cb6 8435 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7b5342d9
YM		 8436
8437 if (rc == -EEXIST) {
8438 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8439 /* do not treat adding same MAC as error */
8440 rc = 0;
8441 } else if (rc < 0)
619c5cb6 8442 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7b5342d9 8443
619c5cb6 8444 return rc;
a2fbb9ea
ET		 8445}
8446
05cc5a39
YM		 8447int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
8448 struct bnx2x_vlan_mac_obj *obj, bool set,
8449 unsigned long *ramrod_flags)
8450{
8451 int rc;
8452 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8453
8454 memset(&ramrod_param, 0, sizeof(ramrod_param));
8455
8456 /* Fill general parameters */
8457 ramrod_param.vlan_mac_obj = obj;
8458 ramrod_param.ramrod_flags = *ramrod_flags;
8459
8460 /* Fill a user request section if needed */
8461 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8462 ramrod_param.user_req.u.vlan.vlan = vlan;
8463 /* Set the command: ADD or DEL */
8464 if (set)
8465 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8466 else
8467 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8468 }
8469
8470 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8471
8472 if (rc == -EEXIST) {
8473 /* Do not treat adding same vlan as error. */
8474 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8475 rc = 0;
8476 } else if (rc < 0) {
8477 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del"));
8478 }
8479
8480 return rc;
8481}
8482
619c5cb6
VZ		 8483int bnx2x_del_all_macs(struct bnx2x *bp,
8484 struct bnx2x_vlan_mac_obj *mac_obj,
8485 int mac_type, bool wait_for_comp)
e665bfda 8486{
619c5cb6
VZ		 8487 int rc;
8488 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 8489
619c5cb6
VZ		 8490 /* Wait for completion of requested */
8491 if (wait_for_comp)
8492 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 8493
619c5cb6
VZ		 8494 /* Set the mac type of addresses we want to clear */
8495 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 8496
619c5cb6
VZ		 8497 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8498 if (rc < 0)
8499 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 8500
619c5cb6 8501 return rc;
0793f83f
DK		 8502}
8503
619c5cb6 8504int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 8505{
f8f4f61a
DK		 8506 if (IS_PF(bp)) {
8507 unsigned long ramrod_flags = 0;
0793f83f 8508
f8f4f61a
DK		 8509 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8510 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8511 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8512 &bp->sp_objs->mac_obj, set,
8513 BNX2X_ETH_MAC, &ramrod_flags);
8514 } else { /* vf */
8515 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
bb9e9c1d 8516 bp->fp->index, set);
f8f4f61a 8517 }
e665bfda 8518}
6e30dd4e 8519
619c5cb6 8520int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 8521{
60cad4e6
AE		 8522 if (IS_PF(bp))
8523 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8524 else /* VF */
8525 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
993ac7b5 8526}
a2fbb9ea 8527
d6214d7a 8528/**
e8920674 8529 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 8530 *
e8920674 8531 * @bp: driver handle
d6214d7a 8532 *
e8920674 8533 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 8534 */
1ab4434c 8535int bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 8536{
1ab4434c
AE		 8537 int rc = 0;
8538
60cad4e6
AE		 8539 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8540 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
1ab4434c 8541 return -EINVAL;
60cad4e6 8542 }
1ab4434c 8543
9ee3d37b 8544 switch (int_mode) {
1ab4434c
AE		 8545 case BNX2X_INT_MODE_MSIX:
8546 /* attempt to enable msix */
8547 rc = bnx2x_enable_msix(bp);
8548
8549 /* msix attained */
8550 if (!rc)
8551 return 0;
8552
8553 /* vfs use only msix */
8554 if (rc && IS_VF(bp))
8555 return rc;
8556
8557 /* failed to enable multiple MSI-X */
8558 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8559 bp->num_queues,
8560 1 + bp->num_cnic_queues);
8561
8562 /* falling through... */
8563 case BNX2X_INT_MODE_MSI:
d6214d7a 8564 bnx2x_enable_msi(bp);
1ab4434c 8565
d6214d7a 8566 /* falling through... */
1ab4434c 8567 case BNX2X_INT_MODE_INTX:
55c11941
MS		 8568 bp->num_ethernet_queues = 1;
8569 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
51c1a580 8570 BNX2X_DEV_INFO("set number of queues to 1\n");
ca00392c 8571 break;
d6214d7a 8572 default:
1ab4434c
AE		 8573 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8574 return -EINVAL;
9f6c9258 8575 }
1ab4434c 8576 return 0;
a2fbb9ea
ET		 8577}
8578
1ab4434c 8579/* must be called prior to any HW initializations */
c2bff63f
DK		 8580static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8581{
290ca2bb
AE		 8582 if (IS_SRIOV(bp))
8583 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
c2bff63f
DK		 8584 return L2_ILT_LINES(bp);
8585}
8586
523224a3
DK		 8587void bnx2x_ilt_set_info(struct bnx2x *bp)
8588{
8589 struct ilt_client_info *ilt_client;
8590 struct bnx2x_ilt *ilt = BP_ILT(bp);
8591 u16 line = 0;
8592
8593 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8594 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8595
8596 /* CDU */
8597 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8598 ilt_client->client_num = ILT_CLIENT_CDU;
8599 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8600 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8601 ilt_client->start = line;
619c5cb6 8602 line += bnx2x_cid_ilt_lines(bp);
55c11941
MS		 8603
8604 if (CNIC_SUPPORT(bp))
8605 line += CNIC_ILT_LINES;
523224a3
DK		 8606 ilt_client->end = line - 1;
8607
51c1a580 8608 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8609 ilt_client->start,
8610 ilt_client->end,
8611 ilt_client->page_size,
8612 ilt_client->flags,
8613 ilog2(ilt_client->page_size >> 12));
8614
8615 /* QM */
8616 if (QM_INIT(bp->qm_cid_count)) {
8617 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8618 ilt_client->client_num = ILT_CLIENT_QM;
8619 ilt_client->page_size = QM_ILT_PAGE_SZ;
8620 ilt_client->flags = 0;
8621 ilt_client->start = line;
8622
8623 /* 4 bytes for each cid */
8624 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8625 QM_ILT_PAGE_SZ);
8626
8627 ilt_client->end = line - 1;
8628
51c1a580
MS		 8629 DP(NETIF_MSG_IFUP,
8630 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8631 ilt_client->start,
8632 ilt_client->end,
8633 ilt_client->page_size,
8634 ilt_client->flags,
8635 ilog2(ilt_client->page_size >> 12));
523224a3 8636 }
523224a3 8637
55c11941
MS		 8638 if (CNIC_SUPPORT(bp)) {
8639 /* SRC */
8640 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8641 ilt_client->client_num = ILT_CLIENT_SRC;
8642 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8643 ilt_client->flags = 0;
8644 ilt_client->start = line;
8645 line += SRC_ILT_LINES;
8646 ilt_client->end = line - 1;
523224a3 8647
55c11941
MS		 8648 DP(NETIF_MSG_IFUP,
8649 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8650 ilt_client->start,
8651 ilt_client->end,
8652 ilt_client->page_size,
8653 ilt_client->flags,
8654 ilog2(ilt_client->page_size >> 12));
9f6c9258 8655
55c11941
MS		 8656 /* TM */
8657 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8658 ilt_client->client_num = ILT_CLIENT_TM;
8659 ilt_client->page_size = TM_ILT_PAGE_SZ;
8660 ilt_client->flags = 0;
8661 ilt_client->start = line;
8662 line += TM_ILT_LINES;
8663 ilt_client->end = line - 1;
523224a3 8664
55c11941
MS		 8665 DP(NETIF_MSG_IFUP,
8666 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8667 ilt_client->start,
8668 ilt_client->end,
8669 ilt_client->page_size,
8670 ilt_client->flags,
8671 ilog2(ilt_client->page_size >> 12));
8672 }
9f6c9258 8673
619c5cb6 8674 BUG_ON(line > ILT_MAX_LINES);
523224a3 8675}
f85582f8 8676
619c5cb6
VZ		 8677/**
8678 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8679 *
8680 * @bp: driver handle
8681 * @fp: pointer to fastpath
8682 * @init_params: pointer to parameters structure
8683 *
8684 * parameters configured:
8685 * - HC configuration
8686 * - Queue's CDU context
8687 */
1191cb83 8688static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
619c5cb6 8689 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 8690{
6383c0b3 8691 u8 cos;
a052997e
MS		 8692 int cxt_index, cxt_offset;
8693
619c5cb6
VZ		 8694 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8695 if (!IS_FCOE_FP(fp)) {
8696 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8697 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8698
16a5fd92 8699 /* If HC is supported, enable host coalescing in the transition
619c5cb6
VZ		 8700 * to INIT state.
8701 */
8702 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8703 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8704
8705 /* HC rate */
8706 init_params->rx.hc_rate = bp->rx_ticks ?
8707 (1000000 / bp->rx_ticks) : 0;
8708 init_params->tx.hc_rate = bp->tx_ticks ?
8709 (1000000 / bp->tx_ticks) : 0;
8710
8711 /* FW SB ID */
8712 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8713 fp->fw_sb_id;
8714
8715 /*
8716 * CQ index among the SB indices: FCoE clients uses the default
8717 * SB, therefore it's different.
8718 */
6383c0b3
AE		 8719 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8720 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 8721 }
8722
6383c0b3
AE		 8723 /* set maximum number of COSs supported by this queue */
8724 init_params->max_cos = fp->max_cos;
8725
51c1a580 8726 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 8727 fp->index, init_params->max_cos);
8728
8729 /* set the context pointers queue object */
a052997e 8730 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
65565884
MS		 8731 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8732 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
a052997e 8733 ILT_PAGE_CIDS);
6383c0b3 8734 init_params->cxts[cos] =
a052997e
MS		 8735 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8736 }
619c5cb6
VZ		 8737}
8738
910cc727 8739static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6383c0b3
AE		 8740 struct bnx2x_queue_state_params *q_params,
8741 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8742 int tx_index, bool leading)
8743{
8744 memset(tx_only_params, 0, sizeof(*tx_only_params));
8745
8746 /* Set the command */
8747 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8748
8749 /* Set tx-only QUEUE flags: don't zero statistics */
8750 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8751
8752 /* choose the index of the cid to send the slow path on */
8753 tx_only_params->cid_index = tx_index;
8754
8755 /* Set general TX_ONLY_SETUP parameters */
8756 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8757
8758 /* Set Tx TX_ONLY_SETUP parameters */
8759 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8760
51c1a580
MS		 8761 DP(NETIF_MSG_IFUP,
8762 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 8763 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8764 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8765 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8766
8767 /* send the ramrod */
8768 return bnx2x_queue_state_change(bp, q_params);
8769}
8770
619c5cb6
VZ		 8771/**
8772 * bnx2x_setup_queue - setup queue
8773 *
8774 * @bp: driver handle
8775 * @fp: pointer to fastpath
8776 * @leading: is leading
8777 *
8778 * This function performs 2 steps in a Queue state machine
8779 * actually: 1) RESET->INIT 2) INIT->SETUP
8780 */
8781
8782int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8783 bool leading)
8784{
3b603066 8785 struct bnx2x_queue_state_params q_params = {NULL};
619c5cb6
VZ		 8786 struct bnx2x_queue_setup_params *setup_params =
8787 &q_params.params.setup;
6383c0b3
AE		 8788 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8789 &q_params.params.tx_only;
a2fbb9ea 8790 int rc;
6383c0b3
AE		 8791 u8 tx_index;
8792
51c1a580 8793 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
a2fbb9ea 8794
ec6ba945
VZ		 8795 /* reset IGU state skip FCoE L2 queue */
8796 if (!IS_FCOE_FP(fp))
8797 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 8798 IGU_INT_ENABLE, 0);
a2fbb9ea 8799
15192a8c 8800 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8801 /* We want to wait for completion in this context */
8802 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8803
619c5cb6
VZ		 8804 /* Prepare the INIT parameters */
8805 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 8806
619c5cb6
VZ		 8807 /* Set the command */
8808 q_params.cmd = BNX2X_Q_CMD_INIT;
8809
8810 /* Change the state to INIT */
8811 rc = bnx2x_queue_state_change(bp, &q_params);
8812 if (rc) {
6383c0b3 8813 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 8814 return rc;
8815 }
ec6ba945 8816
51c1a580 8817 DP(NETIF_MSG_IFUP, "init complete\n");
6383c0b3 8818
619c5cb6
VZ		 8819 /* Now move the Queue to the SETUP state... */
8820 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 8821
619c5cb6
VZ		 8822 /* Set QUEUE flags */
8823 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 8824
619c5cb6 8825 /* Set general SETUP parameters */
6383c0b3
AE		 8826 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8827 FIRST_TX_COS_INDEX);
619c5cb6 8828
6383c0b3 8829 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 8830 &setup_params->rxq_params);
8831
6383c0b3
AE		 8832 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8833 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 8834
8835 /* Set the command */
8836 q_params.cmd = BNX2X_Q_CMD_SETUP;
8837
55c11941
MS		 8838 if (IS_FCOE_FP(fp))
8839 bp->fcoe_init = true;
8840
619c5cb6
VZ		 8841 /* Change the state to SETUP */
8842 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 8843 if (rc) {
8844 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8845 return rc;
8846 }
8847
8848 /* loop through the relevant tx-only indices */
8849 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8850 tx_index < fp->max_cos;
8851 tx_index++) {
8852
8853 /* prepare and send tx-only ramrod*/
8854 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8855 tx_only_params, tx_index, leading);
8856 if (rc) {
8857 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8858 fp->index, tx_index);
8859 return rc;
8860 }
8861 }
523224a3 8862
34f80b04 8863 return rc;
a2fbb9ea
ET		 8864}
8865
619c5cb6 8866static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 8867{
619c5cb6 8868 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 8869 struct bnx2x_fp_txdata *txdata;
3b603066 8870 struct bnx2x_queue_state_params q_params = {NULL};
6383c0b3
AE		 8871 int rc, tx_index;
8872
51c1a580 8873 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 8874
15192a8c 8875 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8876 /* We want to wait for completion in this context */
8877 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8878
6383c0b3
AE		 8879 /* close tx-only connections */
8880 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8881 tx_index < fp->max_cos;
8882 tx_index++){
8883
8884 /* ascertain this is a normal queue*/
65565884 8885 txdata = fp->txdata_ptr[tx_index];
6383c0b3 8886
51c1a580 8887 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
6383c0b3
AE		 8888 txdata->txq_index);
8889
8890 /* send halt terminate on tx-only connection */
8891 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8892 memset(&q_params.params.terminate, 0,
8893 sizeof(q_params.params.terminate));
8894 q_params.params.terminate.cid_index = tx_index;
8895
8896 rc = bnx2x_queue_state_change(bp, &q_params);
8897 if (rc)
8898 return rc;
8899
8900 /* send halt terminate on tx-only connection */
8901 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8902 memset(&q_params.params.cfc_del, 0,
8903 sizeof(q_params.params.cfc_del));
8904 q_params.params.cfc_del.cid_index = tx_index;
8905 rc = bnx2x_queue_state_change(bp, &q_params);
8906 if (rc)
8907 return rc;
8908 }
8909 /* Stop the primary connection: */
8910 /* ...halt the connection */
619c5cb6
VZ		 8911 q_params.cmd = BNX2X_Q_CMD_HALT;
8912 rc = bnx2x_queue_state_change(bp, &q_params);
8913 if (rc)
da5a662a 8914 return rc;
a2fbb9ea 8915
6383c0b3 8916 /* ...terminate the connection */
619c5cb6 8917 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 8918 memset(&q_params.params.terminate, 0,
8919 sizeof(q_params.params.terminate));
8920 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 8921 rc = bnx2x_queue_state_change(bp, &q_params);
8922 if (rc)
523224a3 8923 return rc;
6383c0b3 8924 /* ...delete cfc entry */
619c5cb6 8925 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 8926 memset(&q_params.params.cfc_del, 0,
8927 sizeof(q_params.params.cfc_del));
8928 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 8929 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 8930}
8931
34f80b04
EG		 8932static void bnx2x_reset_func(struct bnx2x *bp)
8933{
8934 int port = BP_PORT(bp);
8935 int func = BP_FUNC(bp);
f2e0899f 8936 int i;
523224a3
DK		 8937
8938 /* Disable the function in the FW */
8939 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8940 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8941 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8942 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8943
8944 /* FP SBs */
ec6ba945 8945 for_each_eth_queue(bp, i) {
523224a3 8946 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 8947 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 8948 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8949 SB_DISABLED);
523224a3
DK		 8950 }
8951
55c11941
MS		 8952 if (CNIC_LOADED(bp))
8953 /* CNIC SB */
8954 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8955 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8956 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8957
523224a3 8958 /* SP SB */
619c5cb6 8959 REG_WR8(bp, BAR_CSTRORM_INTMEM +
2de67439
YM		 8960 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8961 SB_DISABLED);
523224a3
DK		 8962
8963 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8964 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8965 0);
34f80b04
EG		 8966
8967 /* Configure IGU */
f2e0899f
DK		 8968 if (bp->common.int_block == INT_BLOCK_HC) {
8969 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8970 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8971 } else {
8972 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8973 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8974 }
34f80b04 8975
55c11941
MS		 8976 if (CNIC_LOADED(bp)) {
8977 /* Disable Timer scan */
8978 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8979 /*
8980 * Wait for at least 10ms and up to 2 second for the timers
8981 * scan to complete
8982 */
8983 for (i = 0; i < 200; i++) {
639d65b8 8984 usleep_range(10000, 20000);
55c11941
MS		 8985 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8986 break;
8987 }
37b091ba 8988 }
34f80b04 8989 /* Clear ILT */
f2e0899f
DK		 8990 bnx2x_clear_func_ilt(bp, func);
8991
8992 /* Timers workaround bug for E2: if this is vnic-3,
8993 * we need to set the entire ilt range for this timers.
8994 */
619c5cb6 8995 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 8996 struct ilt_client_info ilt_cli;
8997 /* use dummy TM client */
8998 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8999 ilt_cli.start = 0;
9000 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
9001 ilt_cli.client_num = ILT_CLIENT_TM;
9002
9003 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
9004 }
9005
9006 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 9007 if (!CHIP_IS_E1x(bp))
f2e0899f 9008 bnx2x_pf_disable(bp);
523224a3
DK		 9009
9010 bp->dmae_ready = 0;
34f80b04
EG		 9011}
9012
9013static void bnx2x_reset_port(struct bnx2x *bp)
9014{
9015 int port = BP_PORT(bp);
9016 u32 val;
9017
619c5cb6
VZ		 9018 /* Reset physical Link */
9019 bnx2x__link_reset(bp);
9020
34f80b04
EG		 9021 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
9022
9023 /* Do not rcv packets to BRB */
9024 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
9025 /* Do not direct rcv packets that are not for MCP to the BRB */
9026 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
9027 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
9028
9029 /* Configure AEU */
9030 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
9031
9032 msleep(100);
9033 /* Check for BRB port occupancy */
9034 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
9035 if (val)
9036 DP(NETIF_MSG_IFDOWN,
33471629 9037 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 9038
9039 /* TODO: Close Doorbell port? */
9040}
9041
1191cb83 9042static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 9043{
3b603066 9044 struct bnx2x_func_state_params func_params = {NULL};
34f80b04 9045
619c5cb6
VZ		 9046 /* Prepare parameters for function state transitions */
9047 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 9048
619c5cb6
VZ		 9049 func_params.f_obj = &bp->func_obj;
9050 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 9051
619c5cb6 9052 func_params.params.hw_init.load_phase = load_code;
49d66772 9053
619c5cb6 9054 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 9055}
9056
1191cb83 9057static int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 9058{
3b603066 9059 struct bnx2x_func_state_params func_params = {NULL};
619c5cb6 9060 int rc;
228241eb 9061
619c5cb6
VZ		 9062 /* Prepare parameters for function state transitions */
9063 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9064 func_params.f_obj = &bp->func_obj;
9065 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 9066
619c5cb6
VZ		 9067 /*
9068 * Try to stop the function the 'good way'. If fails (in case
9069 * of a parity error during bnx2x_chip_cleanup()) and we are
9070 * not in a debug mode, perform a state transaction in order to
9071 * enable further HW_RESET transaction.
9072 */
9073 rc = bnx2x_func_state_change(bp, &func_params);
9074 if (rc) {
34f80b04 9075#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 9076 return rc;
34f80b04 9077#else
51c1a580 9078 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
619c5cb6
VZ		 9079 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9080 return bnx2x_func_state_change(bp, &func_params);
34f80b04 9081#endif
228241eb 9082 }
a2fbb9ea 9083
619c5cb6
VZ		 9084 return 0;
9085}
523224a3 9086
619c5cb6
VZ		 9087/**
9088 * bnx2x_send_unload_req - request unload mode from the MCP.
9089 *
9090 * @bp: driver handle
9091 * @unload_mode: requested function's unload mode
9092 *
9093 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9094 */
9095u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9096{
9097 u32 reset_code = 0;
9098 int port = BP_PORT(bp);
3101c2bc 9099
619c5cb6 9100 /* Select the UNLOAD request mode */
65abd74d
YG		 9101 if (unload_mode == UNLOAD_NORMAL)
9102 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9103
7d0446c2 9104 else if (bp->flags & NO_WOL_FLAG)
65abd74d 9105 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 9106
7d0446c2 9107 else if (bp->wol) {
65abd74d
YG		 9108 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9109 u8 *mac_addr = bp->dev->dev_addr;
29ed74c3 9110 struct pci_dev *pdev = bp->pdev;
65abd74d 9111 u32 val;
f9977903
DK		 9112 u16 pmc;
9113
65abd74d 9114 /* The mac address is written to entries 1-4 to
f9977903
DK		 9115 * preserve entry 0 which is used by the PMF
9116 */
3395a033 9117 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 9118
9119 val = (mac_addr[0] << 8) | mac_addr[1];
9120 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9121
9122 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9123 (mac_addr[4] << 8) | mac_addr[5];
9124 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9125
f9977903 9126 /* Enable the PME and clear the status */
29ed74c3 9127 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
f9977903 9128 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
29ed74c3 9129 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
f9977903 9130
65abd74d
YG		 9131 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9132
9133 } else
9134 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 9135
619c5cb6
VZ		 9136 /* Send the request to the MCP */
9137 if (!BP_NOMCP(bp))
9138 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9139 else {
9140 int path = BP_PATH(bp);
9141
51c1a580 9142 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
a8f47eb7 9143 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9144 bnx2x_load_count[path][2]);
9145 bnx2x_load_count[path][0]--;
9146 bnx2x_load_count[path][1 + port]--;
51c1a580 9147 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
a8f47eb7 9148 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9149 bnx2x_load_count[path][2]);
9150 if (bnx2x_load_count[path][0] == 0)
619c5cb6 9151 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
a8f47eb7 9152 else if (bnx2x_load_count[path][1 + port] == 0)
619c5cb6
VZ		 9153 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9154 else
9155 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9156 }
9157
9158 return reset_code;
9159}
9160
9161/**
9162 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9163 *
9164 * @bp: driver handle
5d07d868 9165 * @keep_link: true iff link should be kept up
619c5cb6 9166 */
5d07d868 9167void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
619c5cb6 9168{
5d07d868
YM		 9169 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9170
619c5cb6
VZ		 9171 /* Report UNLOAD_DONE to MCP */
9172 if (!BP_NOMCP(bp))
5d07d868 9173 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
619c5cb6
VZ		 9174}
9175
1191cb83 9176static int bnx2x_func_wait_started(struct bnx2x *bp)
6debea87
DK		 9177{
9178 int tout = 50;
9179 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9180
9181 if (!bp->port.pmf)
9182 return 0;
9183
9184 /*
9185 * (assumption: No Attention from MCP at this stage)
16a5fd92 9186 * PMF probably in the middle of TX disable/enable transaction
6debea87 9187 * 1. Sync IRS for default SB
16a5fd92
YM		 9188 * 2. Sync SP queue - this guarantees us that attention handling started
9189 * 3. Wait, that TX disable/enable transaction completes
6debea87 9190 *
16a5fd92
YM		 9191 * 1+2 guarantee that if DCBx attention was scheduled it already changed
9192 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9193 * received completion for the transaction the state is TX_STOPPED.
6debea87
DK		 9194 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9195 * transaction.
9196 */
9197
9198 /* make sure default SB ISR is done */
9199 if (msix)
9200 synchronize_irq(bp->msix_table[0].vector);
9201 else
9202 synchronize_irq(bp->pdev->irq);
9203
9204 flush_workqueue(bnx2x_wq);
370d4a26 9205 flush_workqueue(bnx2x_iov_wq);
6debea87
DK		 9206
9207 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9208 BNX2X_F_STATE_STARTED && tout--)
9209 msleep(20);
9210
9211 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9212 BNX2X_F_STATE_STARTED) {
9213#ifdef BNX2X_STOP_ON_ERROR
51c1a580 9214 BNX2X_ERR("Wrong function state\n");
6debea87
DK		 9215 return -EBUSY;
9216#else
9217 /*
9218 * Failed to complete the transaction in a "good way"
9219 * Force both transactions with CLR bit
9220 */
3b603066 9221 struct bnx2x_func_state_params func_params = {NULL};
6debea87 9222
51c1a580 9223 DP(NETIF_MSG_IFDOWN,
0c23ad37 9224 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
6debea87
DK		 9225
9226 func_params.f_obj = &bp->func_obj;
9227 __set_bit(RAMROD_DRV_CLR_ONLY,
9228 &func_params.ramrod_flags);
9229
9230 /* STARTED-->TX_ST0PPED */
9231 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9232 bnx2x_func_state_change(bp, &func_params);
9233
9234 /* TX_ST0PPED-->STARTED */
9235 func_params.cmd = BNX2X_F_CMD_TX_START;
9236 return bnx2x_func_state_change(bp, &func_params);
9237#endif
9238 }
9239
9240 return 0;
9241}
9242
eeed018c
MK		 9243static void bnx2x_disable_ptp(struct bnx2x *bp)
9244{
9245 int port = BP_PORT(bp);
9246
9247 /* Disable sending PTP packets to host */
9248 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9249 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9250
9251 /* Reset PTP event detection rules */
9252 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9253 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9254 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9255 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9256 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9257 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9258 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9259 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9260
9261 /* Disable the PTP feature */
9262 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9263 NIG_REG_P0_PTP_EN, 0x0);
9264}
9265
9266/* Called during unload, to stop PTP-related stuff */
1444c301 9267static void bnx2x_stop_ptp(struct bnx2x *bp)
eeed018c
MK		 9268{
9269 /* Cancel PTP work queue. Should be done after the Tx queues are
9270 * drained to prevent additional scheduling.
9271 */
9272 cancel_work_sync(&bp->ptp_task);
9273
9274 if (bp->ptp_tx_skb) {
9275 dev_kfree_skb_any(bp->ptp_tx_skb);
9276 bp->ptp_tx_skb = NULL;
9277 }
9278
9279 /* Disable PTP in HW */
9280 bnx2x_disable_ptp(bp);
9281
9282 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9283}
9284
5d07d868 9285void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
619c5cb6
VZ		 9286{
9287 int port = BP_PORT(bp);
6383c0b3
AE		 9288 int i, rc = 0;
9289 u8 cos;
3b603066 9290 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6
VZ		 9291 u32 reset_code;
9292
9293 /* Wait until tx fastpath tasks complete */
9294 for_each_tx_queue(bp, i) {
9295 struct bnx2x_fastpath *fp = &bp->fp[i];
9296
6383c0b3 9297 for_each_cos_in_tx_queue(fp, cos)
65565884 9298 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
619c5cb6
VZ		 9299#ifdef BNX2X_STOP_ON_ERROR
9300 if (rc)
9301 return;
9302#endif
9303 }
9304
9305 /* Give HW time to discard old tx messages */
0926d499 9306 usleep_range(1000, 2000);
619c5cb6
VZ		 9307
9308 /* Clean all ETH MACs */
15192a8c
BW		 9309 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9310 false);
619c5cb6
VZ		 9311 if (rc < 0)
9312 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9313
9314 /* Clean up UC list */
15192a8c 9315 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
619c5cb6
VZ		 9316 true);
9317 if (rc < 0)
51c1a580
MS		 9318 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9319 rc);
619c5cb6
VZ		 9320
9321 /* Disable LLH */
9322 if (!CHIP_IS_E1(bp))
9323 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9324
9325 /* Set "drop all" (stop Rx).
9326 * We need to take a netif_addr_lock() here in order to prevent
9327 * a race between the completion code and this code.
9328 */
9329 netif_addr_lock_bh(bp->dev);
9330 /* Schedule the rx_mode command */
9331 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9332 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9333 else
9334 bnx2x_set_storm_rx_mode(bp);
9335
9336 /* Cleanup multicast configuration */
9337 rparam.mcast_obj = &bp->mcast_obj;
9338 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9339 if (rc < 0)
9340 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9341
9342 netif_addr_unlock_bh(bp->dev);
9343
f1929b01 9344 bnx2x_iov_chip_cleanup(bp);
619c5cb6 9345
6debea87
DK		 9346 /*
9347 * Send the UNLOAD_REQUEST to the MCP. This will return if
9348 * this function should perform FUNC, PORT or COMMON HW
9349 * reset.
9350 */
9351 reset_code = bnx2x_send_unload_req(bp, unload_mode);
9352
9353 /*
9354 * (assumption: No Attention from MCP at this stage)
16a5fd92 9355 * PMF probably in the middle of TX disable/enable transaction
6debea87
DK		 9356 */
9357 rc = bnx2x_func_wait_started(bp);
9358 if (rc) {
9359 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9360#ifdef BNX2X_STOP_ON_ERROR
9361 return;
9362#endif
9363 }
9364
34f80b04 9365 /* Close multi and leading connections
619c5cb6
VZ		 9366 * Completions for ramrods are collected in a synchronous way
9367 */
55c11941 9368 for_each_eth_queue(bp, i)
619c5cb6 9369 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 9370#ifdef BNX2X_STOP_ON_ERROR
9371 return;
9372#else
228241eb 9373 goto unload_error;
523224a3 9374#endif
55c11941
MS		 9375
9376 if (CNIC_LOADED(bp)) {
9377 for_each_cnic_queue(bp, i)
9378 if (bnx2x_stop_queue(bp, i))
9379#ifdef BNX2X_STOP_ON_ERROR
9380 return;
9381#else
9382 goto unload_error;
9383#endif
9384 }
9385
619c5cb6
VZ		 9386 /* If SP settings didn't get completed so far - something
9387 * very wrong has happen.
9388 */
9389 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9390 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 9391
619c5cb6
VZ		 9392#ifndef BNX2X_STOP_ON_ERROR
9393unload_error:
9394#endif
523224a3 9395 rc = bnx2x_func_stop(bp);
da5a662a 9396 if (rc) {
523224a3 9397 BNX2X_ERR("Function stop failed!\n");
da5a662a 9398#ifdef BNX2X_STOP_ON_ERROR
523224a3 9399 return;
523224a3 9400#endif
34f80b04 9401 }
a2fbb9ea 9402
eeed018c
MK		 9403 /* stop_ptp should be after the Tx queues are drained to prevent
9404 * scheduling to the cancelled PTP work queue. It should also be after
9405 * function stop ramrod is sent, since as part of this ramrod FW access
9406 * PTP registers.
9407 */
d53c66a5
ED		 9408 if (bp->flags & PTP_SUPPORTED)
9409 bnx2x_stop_ptp(bp);
eeed018c 9410
523224a3
DK		 9411 /* Disable HW interrupts, NAPI */
9412 bnx2x_netif_stop(bp, 1);
26614ba5
MS		 9413 /* Delete all NAPI objects */
9414 bnx2x_del_all_napi(bp);
55c11941
MS		 9415 if (CNIC_LOADED(bp))
9416 bnx2x_del_all_napi_cnic(bp);
523224a3
DK		 9417
9418 /* Release IRQs */
d6214d7a 9419 bnx2x_free_irq(bp);
523224a3 9420
a2fbb9ea 9421 /* Reset the chip */
619c5cb6
VZ		 9422 rc = bnx2x_reset_hw(bp, reset_code);
9423 if (rc)
9424 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 9425
619c5cb6 9426 /* Report UNLOAD_DONE to MCP */
5d07d868 9427 bnx2x_send_unload_done(bp, keep_link);
72fd0718
VZ		 9428}
9429
9f6c9258 9430void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 9431{
9432 u32 val;
9433
51c1a580 9434 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
72fd0718
VZ		 9435
9436 if (CHIP_IS_E1(bp)) {
9437 int port = BP_PORT(bp);
9438 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9439 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9440
9441 val = REG_RD(bp, addr);
9442 val &= ~(0x300);
9443 REG_WR(bp, addr, val);
619c5cb6 9444 } else {
72fd0718
VZ		 9445 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9446 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9447 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9448 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9449 }
9450}
9451
72fd0718
VZ		 9452/* Close gates #2, #3 and #4: */
9453static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9454{
c9ee9206 9455 u32 val;
72fd0718
VZ		 9456
9457 /* Gates #2 and #4a are closed/opened for "not E1" only */
9458 if (!CHIP_IS_E1(bp)) {
9459 /* #4 */
c9ee9206 9460 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 9461 /* #2 */
c9ee9206 9462 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 9463 }
9464
9465 /* #3 */
c9ee9206
VZ		 9466 if (CHIP_IS_E1x(bp)) {
9467 /* Prevent interrupts from HC on both ports */
9468 val = REG_RD(bp, HC_REG_CONFIG_1);
9469 REG_WR(bp, HC_REG_CONFIG_1,
9470 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9471 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9472
9473 val = REG_RD(bp, HC_REG_CONFIG_0);
9474 REG_WR(bp, HC_REG_CONFIG_0,
9475 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9476 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9477 } else {
d82603c6 9478 /* Prevent incoming interrupts in IGU */
c9ee9206
VZ		 9479 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9480
9481 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9482 (!close) ?
9483 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9484 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9485 }
72fd0718 9486
51c1a580 9487 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
72fd0718
VZ		 9488 close ? "closing" : "opening");
9489 mmiowb();
9490}
9491
9492#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9493
9494static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9495{
9496 /* Do some magic... */
9497 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9498 *magic_val = val & SHARED_MF_CLP_MAGIC;
9499 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9500}
9501
e8920674
DK		 9502/**
9503 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 9504 *
e8920674
DK		 9505 * @bp: driver handle
9506 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 9507 */
9508static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9509{
9510 /* Restore the `magic' bit value... */
72fd0718
VZ		 9511 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9512 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9513 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9514}
9515
f85582f8 9516/**
e8920674 9517 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 9518 *
e8920674
DK		 9519 * @bp: driver handle
9520 * @magic_val: old value of 'magic' bit.
9521 *
9522 * Takes care of CLP configurations.
72fd0718
VZ		 9523 */
9524static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9525{
9526 u32 shmem;
9527 u32 validity_offset;
9528
51c1a580 9529 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
72fd0718
VZ		 9530
9531 /* Set `magic' bit in order to save MF config */
9532 if (!CHIP_IS_E1(bp))
9533 bnx2x_clp_reset_prep(bp, magic_val);
9534
9535 /* Get shmem offset */
9536 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
c55e771b
BW		 9537 validity_offset =
9538 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
72fd0718
VZ		 9539
9540 /* Clear validity map flags */
9541 if (shmem > 0)
9542 REG_WR(bp, shmem + validity_offset, 0);
9543}
9544
9545#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9546#define MCP_ONE_TIMEOUT 100 /* 100 ms */
9547
e8920674
DK		 9548/**
9549 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 9550 *
e8920674 9551 * @bp: driver handle
72fd0718 9552 */
1191cb83 9553static void bnx2x_mcp_wait_one(struct bnx2x *bp)
72fd0718
VZ		 9554{
9555 /* special handling for emulation and FPGA,
9556 wait 10 times longer */
9557 if (CHIP_REV_IS_SLOW(bp))
9558 msleep(MCP_ONE_TIMEOUT*10);
9559 else
9560 msleep(MCP_ONE_TIMEOUT);
9561}
9562
1b6e2ceb
DK		 9563/*
9564 * initializes bp->common.shmem_base and waits for validity signature to appear
9565 */
9566static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 9567{
1b6e2ceb
DK		 9568 int cnt = 0;
9569 u32 val = 0;
72fd0718 9570
1b6e2ceb
DK		 9571 do {
9572 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9573 if (bp->common.shmem_base) {
9574 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9575 if (val & SHR_MEM_VALIDITY_MB)
9576 return 0;
9577 }
72fd0718 9578
1b6e2ceb 9579 bnx2x_mcp_wait_one(bp);
72fd0718 9580
1b6e2ceb 9581 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 9582
1b6e2ceb 9583 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 9584
1b6e2ceb
DK		 9585 return -ENODEV;
9586}
72fd0718 9587
1b6e2ceb
DK		 9588static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9589{
9590 int rc = bnx2x_init_shmem(bp);
72fd0718 9591
72fd0718
VZ		 9592 /* Restore the `magic' bit value */
9593 if (!CHIP_IS_E1(bp))
9594 bnx2x_clp_reset_done(bp, magic_val);
9595
9596 return rc;
9597}
9598
9599static void bnx2x_pxp_prep(struct bnx2x *bp)
9600{
9601 if (!CHIP_IS_E1(bp)) {
9602 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9603 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 9604 mmiowb();
9605 }
9606}
9607
9608/*
9609 * Reset the whole chip except for:
9610 * - PCIE core
9611 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9612 * one reset bit)
9613 * - IGU
9614 * - MISC (including AEU)
9615 * - GRC
9616 * - RBCN, RBCP
9617 */
c9ee9206 9618static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 9619{
9620 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 9621 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 9622
9623 /*
9624 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9625 * (per chip) blocks.
9626 */
9627 global_bits2 =
9628 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9629 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 9630
c55e771b
BW		 9631 /* Don't reset the following blocks.
9632 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9633 * reset, as in 4 port device they might still be owned
9634 * by the MCP (there is only one leader per path).
9635 */
72fd0718
VZ		 9636 not_reset_mask1 =
9637 MISC_REGISTERS_RESET_REG_1_RST_HC |
9638 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9639 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9640
9641 not_reset_mask2 =
c9ee9206 9642 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 9643 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9644 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9645 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9646 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9647 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9648 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 9649 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9650 MISC_REGISTERS_RESET_REG_2_RST_ATC |
c55e771b
BW		 9651 MISC_REGISTERS_RESET_REG_2_PGLC |
9652 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9653 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9654 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9655 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9656 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9657 MISC_REGISTERS_RESET_REG_2_UMAC1;
72fd0718 9658
8736c826
VZ		 9659 /*
9660 * Keep the following blocks in reset:
9661 * - all xxMACs are handled by the bnx2x_link code.
9662 */
9663 stay_reset2 =
8736c826
VZ		 9664 MISC_REGISTERS_RESET_REG_2_XMAC |
9665 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9666
9667 /* Full reset masks according to the chip */
72fd0718
VZ		 9668 reset_mask1 = 0xffffffff;
9669
9670 if (CHIP_IS_E1(bp))
9671 reset_mask2 = 0xffff;
8736c826 9672 else if (CHIP_IS_E1H(bp))
72fd0718 9673 reset_mask2 = 0x1ffff;
8736c826
VZ		 9674 else if (CHIP_IS_E2(bp))
9675 reset_mask2 = 0xfffff;
9676 else /* CHIP_IS_E3 */
9677 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 9678
9679 /* Don't reset global blocks unless we need to */
9680 if (!global)
9681 reset_mask2 &= ~global_bits2;
9682
9683 /*
9684 * In case of attention in the QM, we need to reset PXP
9685 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9686 * because otherwise QM reset would release 'close the gates' shortly
9687 * before resetting the PXP, then the PSWRQ would send a write
9688 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9689 * read the payload data from PSWWR, but PSWWR would not
9690 * respond. The write queue in PGLUE would stuck, dmae commands
9691 * would not return. Therefore it's important to reset the second
9692 * reset register (containing the
9693 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9694 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9695 * bit).
9696 */
72fd0718
VZ		 9697 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9698 reset_mask2 & (~not_reset_mask2));
9699
c9ee9206
VZ		 9700 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9701 reset_mask1 & (~not_reset_mask1));
9702
72fd0718
VZ		 9703 barrier();
9704 mmiowb();
9705
8736c826
VZ		 9706 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9707 reset_mask2 & (~stay_reset2));
9708
9709 barrier();
9710 mmiowb();
9711
c9ee9206 9712 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 9713 mmiowb();
9714}
9715
c9ee9206
VZ		 9716/**
9717 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9718 * It should get cleared in no more than 1s.
9719 *
9720 * @bp: driver handle
9721 *
9722 * It should get cleared in no more than 1s. Returns 0 if
9723 * pending writes bit gets cleared.
9724 */
9725static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9726{
9727 u32 cnt = 1000;
9728 u32 pend_bits = 0;
9729
9730 do {
9731 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9732
9733 if (pend_bits == 0)
9734 break;
9735
0926d499 9736 usleep_range(1000, 2000);
c9ee9206
VZ		 9737 } while (cnt-- > 0);
9738
9739 if (cnt <= 0) {
9740 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9741 pend_bits);
9742 return -EBUSY;
9743 }
9744
9745 return 0;
9746}
9747
9748static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 9749{
9750 int cnt = 1000;
9751 u32 val = 0;
9752 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
2de67439 9753 u32 tags_63_32 = 0;
72fd0718
VZ		 9754
9755 /* Empty the Tetris buffer, wait for 1s */
9756 do {
9757 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9758 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9759 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9760 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9761 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
c55e771b
BW		 9762 if (CHIP_IS_E3(bp))
9763 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9764
72fd0718
VZ		 9765 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9766 ((port_is_idle_0 & 0x1) == 0x1) &&
9767 ((port_is_idle_1 & 0x1) == 0x1) &&
c55e771b
BW		 9768 (pgl_exp_rom2 == 0xffffffff) &&
9769 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
72fd0718 9770 break;
0926d499 9771 usleep_range(1000, 2000);
72fd0718
VZ		 9772 } while (cnt-- > 0);
9773
9774 if (cnt <= 0) {
51c1a580
MS		 9775 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9776 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
72fd0718
VZ		 9777 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9778 pgl_exp_rom2);
9779 return -EAGAIN;
9780 }
9781
9782 barrier();
9783
9784 /* Close gates #2, #3 and #4 */
9785 bnx2x_set_234_gates(bp, true);
9786
c9ee9206
VZ		 9787 /* Poll for IGU VQs for 57712 and newer chips */
9788 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9789 return -EAGAIN;
9790
72fd0718
VZ		 9791 /* TBD: Indicate that "process kill" is in progress to MCP */
9792
9793 /* Clear "unprepared" bit */
9794 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9795 barrier();
9796
9797 /* Make sure all is written to the chip before the reset */
9798 mmiowb();
9799
9800 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9801 * PSWHST, GRC and PSWRD Tetris buffer.
9802 */
0926d499 9803 usleep_range(1000, 2000);
72fd0718
VZ		 9804
9805 /* Prepare to chip reset: */
9806 /* MCP */
c9ee9206
VZ		 9807 if (global)
9808 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 9809
9810 /* PXP */
9811 bnx2x_pxp_prep(bp);
9812 barrier();
9813
9814 /* reset the chip */
c9ee9206 9815 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 9816 barrier();
9817
9dcd9acd
DK		 9818 /* clear errors in PGB */
9819 if (!CHIP_IS_E1x(bp))
9820 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9821
72fd0718
VZ		 9822 /* Recover after reset: */
9823 /* MCP */
c9ee9206 9824 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 9825 return -EAGAIN;
9826
c9ee9206
VZ		 9827 /* TBD: Add resetting the NO_MCP mode DB here */
9828
72fd0718
VZ		 9829 /* Open the gates #2, #3 and #4 */
9830 bnx2x_set_234_gates(bp, false);
9831
9832 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9833 * reset state, re-enable attentions. */
9834
a2fbb9ea
ET		 9835 return 0;
9836}
9837
910cc727 9838static int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 9839{
9840 int rc = 0;
c9ee9206 9841 bool global = bnx2x_reset_is_global(bp);
95c6c616
AE		 9842 u32 load_code;
9843
9844 /* if not going to reset MCP - load "fake" driver to reset HW while
9845 * driver is owner of the HW
9846 */
9847 if (!global && !BP_NOMCP(bp)) {
5d07d868
YM		 9848 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9849 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
95c6c616
AE		 9850 if (!load_code) {
9851 BNX2X_ERR("MCP response failure, aborting\n");
9852 rc = -EAGAIN;
9853 goto exit_leader_reset;
9854 }
9855 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9856 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9857 BNX2X_ERR("MCP unexpected resp, aborting\n");
9858 rc = -EAGAIN;
9859 goto exit_leader_reset2;
9860 }
9861 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9862 if (!load_code) {
9863 BNX2X_ERR("MCP response failure, aborting\n");
9864 rc = -EAGAIN;
9865 goto exit_leader_reset2;
9866 }
9867 }
c9ee9206 9868
72fd0718 9869 /* Try to recover after the failure */
c9ee9206 9870 if (bnx2x_process_kill(bp, global)) {
51c1a580
MS		 9871 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9872 BP_PATH(bp));
72fd0718 9873 rc = -EAGAIN;
95c6c616 9874 goto exit_leader_reset2;
72fd0718
VZ		 9875 }
9876
c9ee9206
VZ		 9877 /*
9878 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9879 * state.
9880 */
72fd0718 9881 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 9882 if (global)
9883 bnx2x_clear_reset_global(bp);
72fd0718 9884
95c6c616
AE		 9885exit_leader_reset2:
9886 /* unload "fake driver" if it was loaded */
9887 if (!global && !BP_NOMCP(bp)) {
9888 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9889 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9890 }
72fd0718
VZ		 9891exit_leader_reset:
9892 bp->is_leader = 0;
c9ee9206
VZ		 9893 bnx2x_release_leader_lock(bp);
9894 smp_mb();
72fd0718
VZ		 9895 return rc;
9896}
9897
1191cb83 9898static void bnx2x_recovery_failed(struct bnx2x *bp)
c9ee9206
VZ		 9899{
9900 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9901
9902 /* Disconnect this device */
9903 netif_device_detach(bp->dev);
9904
9905 /*
9906 * Block ifup for all function on this engine until "process kill"
9907 * or power cycle.
9908 */
9909 bnx2x_set_reset_in_progress(bp);
9910
9911 /* Shut down the power */
9912 bnx2x_set_power_state(bp, PCI_D3hot);
9913
9914 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9915
9916 smp_mb();
9917}
9918
9919/*
9920 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 9921 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 9922 * will never be called when netif_running(bp->dev) is false.
9923 */
9924static void bnx2x_parity_recover(struct bnx2x *bp)
9925{
c9ee9206 9926 bool global = false;
7a752993 9927 u32 error_recovered, error_unrecovered;
95c6c616 9928 bool is_parity;
c9ee9206 9929
72fd0718
VZ		 9930 DP(NETIF_MSG_HW, "Handling parity\n");
9931 while (1) {
9932 switch (bp->recovery_state) {
9933 case BNX2X_RECOVERY_INIT:
9934 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
95c6c616
AE		 9935 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9936 WARN_ON(!is_parity);
c9ee9206 9937
72fd0718 9938 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 9939 if (bnx2x_trylock_leader_lock(bp)) {
9940 bnx2x_set_reset_in_progress(bp);
9941 /*
9942 * Check if there is a global attention and if
9943 * there was a global attention, set the global
9944 * reset bit.
9945 */
9946
9947 if (global)
9948 bnx2x_set_reset_global(bp);
9949
72fd0718 9950 bp->is_leader = 1;
c9ee9206 9951 }
72fd0718
VZ		 9952
9953 /* Stop the driver */
9954 /* If interface has been removed - break */
5d07d868 9955 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
72fd0718
VZ		 9956 return;
9957
9958 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206 9959
c9ee9206
VZ		 9960 /* Ensure "is_leader", MCP command sequence and
9961 * "recovery_state" update values are seen on other
9962 * CPUs.
72fd0718 9963 */
c9ee9206 9964 smp_mb();
72fd0718
VZ		 9965 break;
9966
9967 case BNX2X_RECOVERY_WAIT:
9968 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9969 if (bp->is_leader) {
c9ee9206 9970 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3
AE		 9971 bool other_load_status =
9972 bnx2x_get_load_status(bp, other_engine);
9973 bool load_status =
9974 bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 9975 global = bnx2x_reset_is_global(bp);
9976
9977 /*
9978 * In case of a parity in a global block, let
9979 * the first leader that performs a
9980 * leader_reset() reset the global blocks in
9981 * order to clear global attentions. Otherwise
16a5fd92 9982 * the gates will remain closed for that
c9ee9206
VZ		 9983 * engine.
9984 */
889b9af3
AE		 9985 if (load_status ||
9986 (global && other_load_status)) {
72fd0718
VZ		 9987 /* Wait until all other functions get
9988 * down.
9989 */
7be08a72 9990 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9991 HZ/10);
9992 return;
9993 } else {
9994 /* If all other functions got down -
9995 * try to bring the chip back to
9996 * normal. In any case it's an exit
9997 * point for a leader.
9998 */
c9ee9206
VZ		 9999 if (bnx2x_leader_reset(bp)) {
10000 bnx2x_recovery_failed(bp);
72fd0718
VZ		 10001 return;
10002 }
10003
c9ee9206
VZ		 10004 /* If we are here, means that the
10005 * leader has succeeded and doesn't
10006 * want to be a leader any more. Try
10007 * to continue as a none-leader.
10008 */
10009 break;
72fd0718
VZ		 10010 }
10011 } else { /* non-leader */
c9ee9206 10012 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 10013 /* Try to get a LEADER_LOCK HW lock as
10014 * long as a former leader may have
10015 * been unloaded by the user or
10016 * released a leadership by another
10017 * reason.
10018 */
c9ee9206 10019 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 10020 /* I'm a leader now! Restart a
10021 * switch case.
10022 */
10023 bp->is_leader = 1;
10024 break;
10025 }
10026
7be08a72 10027 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 10028 HZ/10);
10029 return;
10030
c9ee9206
VZ		 10031 } else {
10032 /*
10033 * If there was a global attention, wait
10034 * for it to be cleared.
10035 */
10036 if (bnx2x_reset_is_global(bp)) {
10037 schedule_delayed_work(
7be08a72
AE		 10038 &bp->sp_rtnl_task,
10039 HZ/10);
c9ee9206
VZ		 10040 return;
10041 }
10042
7a752993
AE		 10043 error_recovered =
10044 bp->eth_stats.recoverable_error;
10045 error_unrecovered =
10046 bp->eth_stats.unrecoverable_error;
95c6c616
AE		 10047 bp->recovery_state =
10048 BNX2X_RECOVERY_NIC_LOADING;
10049 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
7a752993 10050 error_unrecovered++;
95c6c616 10051 netdev_err(bp->dev,
51c1a580 10052 "Recovery failed. Power cycle needed\n");
95c6c616
AE		 10053 /* Disconnect this device */
10054 netif_device_detach(bp->dev);
10055 /* Shut down the power */
10056 bnx2x_set_power_state(
10057 bp, PCI_D3hot);
10058 smp_mb();
10059 } else {
c9ee9206
VZ		 10060 bp->recovery_state =
10061 BNX2X_RECOVERY_DONE;
7a752993 10062 error_recovered++;
c9ee9206
VZ		 10063 smp_mb();
10064 }
7a752993
AE		 10065 bp->eth_stats.recoverable_error =
10066 error_recovered;
10067 bp->eth_stats.unrecoverable_error =
10068 error_unrecovered;
c9ee9206 10069
72fd0718
VZ		 10070 return;
10071 }
10072 }
10073 default:
10074 return;
10075 }
10076 }
10077}
10078
f34fa14c
RB		 10079#ifdef CONFIG_BNX2X_VXLAN
10080static int bnx2x_vxlan_port_update(struct bnx2x *bp, u16 port)
10081{
10082 struct bnx2x_func_switch_update_params *switch_update_params;
10083 struct bnx2x_func_state_params func_params = {NULL};
10084 int rc;
10085
10086 switch_update_params = &func_params.params.switch_update;
10087
10088 /* Prepare parameters for function state transitions */
10089 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
10090 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
10091
10092 func_params.f_obj = &bp->func_obj;
10093 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
10094
10095 /* Function parameters */
10096 __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
10097 &switch_update_params->changes);
10098 switch_update_params->vxlan_dst_port = port;
10099 rc = bnx2x_func_state_change(bp, &func_params);
10100 if (rc)
10101 BNX2X_ERR("failed to change vxlan dst port to %d (rc = 0x%x)\n",
10102 port, rc);
10103 return rc;
10104}
10105
10106static void __bnx2x_add_vxlan_port(struct bnx2x *bp, u16 port)
10107{
10108 if (!netif_running(bp->dev))
10109 return;
10110
10111 if (bp->vxlan_dst_port || !IS_PF(bp)) {
10112 DP(BNX2X_MSG_SP, "Vxlan destination port limit reached\n");
10113 return;
10114 }
10115
10116 bp->vxlan_dst_port = port;
10117 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_ADD_VXLAN_PORT, 0);
10118}
10119
10120static void bnx2x_add_vxlan_port(struct net_device *netdev,
10121 sa_family_t sa_family, __be16 port)
10122{
10123 struct bnx2x *bp = netdev_priv(netdev);
10124 u16 t_port = ntohs(port);
10125
10126 __bnx2x_add_vxlan_port(bp, t_port);
10127}
10128
10129static void __bnx2x_del_vxlan_port(struct bnx2x *bp, u16 port)
10130{
10131 if (!bp->vxlan_dst_port || bp->vxlan_dst_port != port || !IS_PF(bp)) {
10132 DP(BNX2X_MSG_SP, "Invalid vxlan port\n");
10133 return;
10134 }
10135
10136 if (netif_running(bp->dev)) {
10137 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_DEL_VXLAN_PORT, 0);
10138 } else {
10139 bp->vxlan_dst_port = 0;
10140 netdev_info(bp->dev, "Deleted vxlan dest port %d", port);
10141 }
10142}
10143
10144static void bnx2x_del_vxlan_port(struct net_device *netdev,
10145 sa_family_t sa_family, __be16 port)
10146{
10147 struct bnx2x *bp = netdev_priv(netdev);
10148 u16 t_port = ntohs(port);
10149
10150 __bnx2x_del_vxlan_port(bp, t_port);
10151}
10152#endif
10153
56ad3152
MS		 10154static int bnx2x_close(struct net_device *dev);
10155
72fd0718
VZ		 10156/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10157 * scheduled on a general queue in order to prevent a dead lock.
10158 */
7be08a72 10159static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 10160{
7be08a72 10161 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
f34fa14c
RB		 10162#ifdef CONFIG_BNX2X_VXLAN
10163 u16 port;
10164#endif
34f80b04
EG		 10165
10166 rtnl_lock();
10167
8395be5e
AE		 10168 if (!netif_running(bp->dev)) {
10169 rtnl_unlock();
10170 return;
10171 }
7be08a72 10172
6bf07b8e 10173 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
7be08a72 10174#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e
YM		 10175 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10176 "you will need to reboot when done\n");
10177 goto sp_rtnl_not_reset;
7be08a72 10178#endif
7be08a72 10179 /*
b1fb8740
VZ		 10180 * Clear all pending SP commands as we are going to reset the
10181 * function anyway.
7be08a72 10182 */
b1fb8740
VZ		 10183 bp->sp_rtnl_state = 0;
10184 smp_mb();
10185
72fd0718 10186 bnx2x_parity_recover(bp);
b1fb8740 10187
8395be5e
AE		 10188 rtnl_unlock();
10189 return;
b1fb8740
VZ		 10190 }
10191
10192 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
6bf07b8e
YM		 10193#ifdef BNX2X_STOP_ON_ERROR
10194 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10195 "you will need to reboot when done\n");
10196 goto sp_rtnl_not_reset;
10197#endif
10198
b1fb8740
VZ		 10199 /*
10200 * Clear all pending SP commands as we are going to reset the
10201 * function anyway.
10202 */
10203 bp->sp_rtnl_state = 0;
10204 smp_mb();
10205
5d07d868 10206 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
72fd0718 10207 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740 10208
8395be5e
AE		 10209 rtnl_unlock();
10210 return;
72fd0718 10211 }
b1fb8740
VZ		 10212#ifdef BNX2X_STOP_ON_ERROR
10213sp_rtnl_not_reset:
10214#endif
10215 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10216 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
a3348722
BW		 10217 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10218 bnx2x_after_function_update(bp);
8304859a
AE		 10219 /*
10220 * in case of fan failure we need to reset id if the "stop on error"
10221 * debug flag is set, since we trying to prevent permanent overheating
10222 * damage
10223 */
10224 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
51c1a580 10225 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
8304859a
AE		 10226 netif_device_detach(bp->dev);
10227 bnx2x_close(bp->dev);
8395be5e
AE		 10228 rtnl_unlock();
10229 return;
8304859a
AE		 10230 }
10231
381ac16b
AE		 10232 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10233 DP(BNX2X_MSG_SP,
10234 "sending set mcast vf pf channel message from rtnl sp-task\n");
10235 bnx2x_vfpf_set_mcast(bp->dev);
10236 }
78c3bcc5
AE		 10237 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10238 &bp->sp_rtnl_state)){
10239 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10240 bnx2x_tx_disable(bp);
10241 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10242 }
10243 }
381ac16b 10244
8b09be5f
YM		 10245 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10246 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10247 bnx2x_set_rx_mode_inner(bp);
381ac16b
AE		 10248 }
10249
3ec9f9ca
AE		 10250 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10251 &bp->sp_rtnl_state))
10252 bnx2x_pf_set_vfs_vlan(bp);
10253
6ffa39f2 10254 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
07b4eb3b 10255 bnx2x_dcbx_stop_hw_tx(bp);
07b4eb3b 10256 bnx2x_dcbx_resume_hw_tx(bp);
6ffa39f2 10257 }
07b4eb3b 10258
42f8277f
YM		 10259 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10260 &bp->sp_rtnl_state))
10261 bnx2x_update_mng_version(bp);
10262
f34fa14c
RB		 10263#ifdef CONFIG_BNX2X_VXLAN
10264 port = bp->vxlan_dst_port;
10265 if (test_and_clear_bit(BNX2X_SP_RTNL_ADD_VXLAN_PORT,
10266 &bp->sp_rtnl_state)) {
10267 if (!bnx2x_vxlan_port_update(bp, port))
10268 netdev_info(bp->dev, "Added vxlan dest port %d", port);
10269 else
10270 bp->vxlan_dst_port = 0;
10271 }
10272
10273 if (test_and_clear_bit(BNX2X_SP_RTNL_DEL_VXLAN_PORT,
10274 &bp->sp_rtnl_state)) {
10275 if (!bnx2x_vxlan_port_update(bp, 0)) {
10276 netdev_info(bp->dev,
10277 "Deleted vxlan dest port %d", port);
10278 bp->vxlan_dst_port = 0;
10279 vxlan_get_rx_port(bp->dev);
10280 }
10281 }
10282#endif
10283
8395be5e
AE		 10284 /* work which needs rtnl lock not-taken (as it takes the lock itself and
10285 * can be called from other contexts as well)
10286 */
34f80b04 10287 rtnl_unlock();
8395be5e 10288
6411280a 10289 /* enable SR-IOV if applicable */
8395be5e 10290 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
3c76feff
AE		 10291 &bp->sp_rtnl_state)) {
10292 bnx2x_disable_sriov(bp);
6411280a 10293 bnx2x_enable_sriov(bp);
3c76feff 10294 }
34f80b04
EG		 10295}
10296
3deb8167
YR		 10297static void bnx2x_period_task(struct work_struct *work)
10298{
10299 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10300
10301 if (!netif_running(bp->dev))
10302 goto period_task_exit;
10303
10304 if (CHIP_REV_IS_SLOW(bp)) {
10305 BNX2X_ERR("period task called on emulation, ignoring\n");
10306 goto period_task_exit;
10307 }
10308
10309 bnx2x_acquire_phy_lock(bp);
10310 /*
10311 * The barrier is needed to ensure the ordering between the writing to
10312 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10313 * the reading here.
10314 */
10315 smp_mb();
10316 if (bp->port.pmf) {
10317 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10318
10319 /* Re-queue task in 1 sec */
10320 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10321 }
10322
10323 bnx2x_release_phy_lock(bp);
10324period_task_exit:
10325 return;
10326}
10327
a2fbb9ea
ET		 10328/*
10329 * Init service functions
10330 */
10331
a8f47eb7 10332static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 10333{
10334 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10335 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10336 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 10337}
10338
3d6b7253
YM		 10339static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10340 u8 port, u32 reset_reg,
10341 struct bnx2x_mac_vals *vals)
10342{
10343 u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10344 u32 base_addr;
10345
10346 if (!(mask & reset_reg))
10347 return false;
10348
10349 BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10350 base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10351 vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10352 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10353 REG_WR(bp, vals->umac_addr[port], 0);
10354
10355 return true;
10356}
10357
1ef1d45a
BW		 10358static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10359 struct bnx2x_mac_vals *vals)
34f80b04 10360{
452427b0
YM		 10361 u32 val, base_addr, offset, mask, reset_reg;
10362 bool mac_stopped = false;
10363 u8 port = BP_PORT(bp);
34f80b04 10364
1ef1d45a 10365 /* reset addresses as they also mark which values were changed */
3d6b7253 10366 memset(vals, 0, sizeof(*vals));
1ef1d45a 10367
452427b0 10368 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
f16da43b 10369
452427b0
YM		 10370 if (!CHIP_IS_E3(bp)) {
10371 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10372 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10373 if ((mask & reset_reg) && val) {
10374 u32 wb_data[2];
10375 BNX2X_DEV_INFO("Disable bmac Rx\n");
10376 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10377 : NIG_REG_INGRESS_BMAC0_MEM;
10378 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10379 : BIGMAC_REGISTER_BMAC_CONTROL;
7a06a122 10380
452427b0
YM		 10381 /*
10382 * use rd/wr since we cannot use dmae. This is safe
10383 * since MCP won't access the bus due to the request
10384 * to unload, and no function on the path can be
10385 * loaded at this time.
10386 */
10387 wb_data[0] = REG_RD(bp, base_addr + offset);
10388 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
1ef1d45a
BW		 10389 vals->bmac_addr = base_addr + offset;
10390 vals->bmac_val[0] = wb_data[0];
10391 vals->bmac_val[1] = wb_data[1];
452427b0 10392 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1ef1d45a
BW		 10393 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10394 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
452427b0
YM		 10395 }
10396 BNX2X_DEV_INFO("Disable emac Rx\n");
1ef1d45a
BW		 10397 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10398 vals->emac_val = REG_RD(bp, vals->emac_addr);
10399 REG_WR(bp, vals->emac_addr, 0);
452427b0
YM		 10400 mac_stopped = true;
10401 } else {
10402 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10403 BNX2X_DEV_INFO("Disable xmac Rx\n");
10404 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10405 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10406 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10407 val & ~(1 << 1));
10408 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10409 val | (1 << 1));
1ef1d45a
BW		 10410 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10411 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10412 REG_WR(bp, vals->xmac_addr, 0);
452427b0
YM		 10413 mac_stopped = true;
10414 }
3d6b7253
YM		 10415
10416 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10417 reset_reg, vals);
10418 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10419 reset_reg, vals);
452427b0
YM		 10420 }
10421
10422 if (mac_stopped)
10423 msleep(20);
452427b0
YM		 10424}
10425
10426#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
7c3afd85
YM		 10427#define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10428 0x1848 + ((f) << 4))
452427b0
YM		 10429#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10430#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10431#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10432
91ebb929
YM		 10433#define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10434#define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10435#define BCM_5710_UNDI_FW_MF_VERS (0x05)
b17b0ca1
YM		 10436
10437static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10438{
10439 /* UNDI marks its presence in DORQ -
10440 * it initializes CID offset for normal bell to 0x7
10441 */
10442 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10443 MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10444 return false;
10445
10446 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10447 BNX2X_DEV_INFO("UNDI previously loaded\n");
10448 return true;
10449 }
10450
10451 return false;
10452}
10453
7c3afd85 10454static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
452427b0
YM		 10455{
10456 u16 rcq, bd;
7c3afd85 10457 u32 addr, tmp_reg;
452427b0 10458
7c3afd85
YM		 10459 if (BP_FUNC(bp) < 2)
10460 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10461 else
10462 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10463
10464 tmp_reg = REG_RD(bp, addr);
452427b0
YM		 10465 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10466 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10467
10468 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
7c3afd85 10469 REG_WR(bp, addr, tmp_reg);
452427b0 10470
7c3afd85
YM		 10471 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10472 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
452427b0
YM		 10473}
10474
0329aba1 10475static int bnx2x_prev_mcp_done(struct bnx2x *bp)
452427b0 10476{
5d07d868
YM		 10477 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10478 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
452427b0
YM		 10479 if (!rc) {
10480 BNX2X_ERR("MCP response failure, aborting\n");
10481 return -EBUSY;
10482 }
10483
10484 return 0;
10485}
10486
c63da990
BW		 10487static struct bnx2x_prev_path_list *
10488 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10489{
10490 struct bnx2x_prev_path_list *tmp_list;
10491
10492 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10493 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10494 bp->pdev->bus->number == tmp_list->bus &&
10495 BP_PATH(bp) == tmp_list->path)
10496 return tmp_list;
10497
10498 return NULL;
10499}
10500
7fa6f340
YM		 10501static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10502{
10503 struct bnx2x_prev_path_list *tmp_list;
10504 int rc;
10505
10506 rc = down_interruptible(&bnx2x_prev_sem);
10507 if (rc) {
10508 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10509 return rc;
10510 }
10511
10512 tmp_list = bnx2x_prev_path_get_entry(bp);
10513 if (tmp_list) {
10514 tmp_list->aer = 1;
10515 rc = 0;
10516 } else {
10517 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10518 BP_PATH(bp));
10519 }
10520
10521 up(&bnx2x_prev_sem);
10522
10523 return rc;
10524}
10525
0329aba1 10526static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
452427b0
YM		 10527{
10528 struct bnx2x_prev_path_list *tmp_list;
b85d717c 10529 bool rc = false;
452427b0
YM		 10530
10531 if (down_trylock(&bnx2x_prev_sem))
10532 return false;
10533
7fa6f340
YM		 10534 tmp_list = bnx2x_prev_path_get_entry(bp);
10535 if (tmp_list) {
10536 if (tmp_list->aer) {
10537 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10538 BP_PATH(bp));
10539 } else {
452427b0
YM		 10540 rc = true;
10541 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10542 BP_PATH(bp));
452427b0
YM		 10543 }
10544 }
10545
10546 up(&bnx2x_prev_sem);
10547
10548 return rc;
10549}
10550
178135c1
DK		 10551bool bnx2x_port_after_undi(struct bnx2x *bp)
10552{
10553 struct bnx2x_prev_path_list *entry;
10554 bool val;
10555
10556 down(&bnx2x_prev_sem);
10557
10558 entry = bnx2x_prev_path_get_entry(bp);
10559 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10560
10561 up(&bnx2x_prev_sem);
10562
10563 return val;
10564}
10565
c63da990 10566static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
452427b0
YM		 10567{
10568 struct bnx2x_prev_path_list *tmp_list;
10569 int rc;
10570
7fa6f340
YM		 10571 rc = down_interruptible(&bnx2x_prev_sem);
10572 if (rc) {
10573 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10574 return rc;
10575 }
10576
10577 /* Check whether the entry for this path already exists */
10578 tmp_list = bnx2x_prev_path_get_entry(bp);
10579 if (tmp_list) {
10580 if (!tmp_list->aer) {
10581 BNX2X_ERR("Re-Marking the path.\n");
10582 } else {
10583 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10584 BP_PATH(bp));
10585 tmp_list->aer = 0;
10586 }
10587 up(&bnx2x_prev_sem);
10588 return 0;
10589 }
10590 up(&bnx2x_prev_sem);
10591
10592 /* Create an entry for this path and add it */
ea4b3857 10593 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
452427b0
YM		 10594 if (!tmp_list) {
10595 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10596 return -ENOMEM;
10597 }
10598
10599 tmp_list->bus = bp->pdev->bus->number;
10600 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10601 tmp_list->path = BP_PATH(bp);
7fa6f340 10602 tmp_list->aer = 0;
c63da990 10603 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
452427b0
YM		 10604
10605 rc = down_interruptible(&bnx2x_prev_sem);
10606 if (rc) {
10607 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10608 kfree(tmp_list);
10609 } else {
7fa6f340
YM		 10610 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10611 BP_PATH(bp));
452427b0
YM		 10612 list_add(&tmp_list->list, &bnx2x_prev_list);
10613 up(&bnx2x_prev_sem);
10614 }
10615
10616 return rc;
10617}
10618
0329aba1 10619static int bnx2x_do_flr(struct bnx2x *bp)
452427b0 10620{
452427b0
YM		 10621 struct pci_dev *dev = bp->pdev;
10622
8eee694c
YM		 10623 if (CHIP_IS_E1x(bp)) {
10624 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10625 return -EINVAL;
10626 }
10627
10628 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10629 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10630 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10631 bp->common.bc_ver);
10632 return -EINVAL;
10633 }
452427b0 10634
8903b9eb
CL		 10635 if (!pci_wait_for_pending_transaction(dev))
10636 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
452427b0 10637
8eee694c 10638 BNX2X_DEV_INFO("Initiating FLR\n");
452427b0
YM		 10639 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10640
10641 return 0;
10642}
10643
0329aba1 10644static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
452427b0
YM		 10645{
10646 int rc;
10647
10648 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10649
10650 /* Test if previous unload process was already finished for this path */
10651 if (bnx2x_prev_is_path_marked(bp))
10652 return bnx2x_prev_mcp_done(bp);
10653
04c46736
YM		 10654 BNX2X_DEV_INFO("Path is unmarked\n");
10655
b17b0ca1
YM		 10656 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10657 if (bnx2x_prev_is_after_undi(bp))
10658 goto out;
10659
452427b0
YM		 10660 /* If function has FLR capabilities, and existing FW version matches
10661 * the one required, then FLR will be sufficient to clean any residue
10662 * left by previous driver
10663 */
91ebb929 10664 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
8eee694c
YM		 10665
10666 if (!rc) {
10667 /* fw version is good */
10668 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10669 rc = bnx2x_do_flr(bp);
10670 }
10671
10672 if (!rc) {
10673 /* FLR was performed */
10674 BNX2X_DEV_INFO("FLR successful\n");
10675 return 0;
10676 }
10677
10678 BNX2X_DEV_INFO("Could not FLR\n");
452427b0 10679
b17b0ca1 10680out:
452427b0
YM		 10681 /* Close the MCP request, return failure*/
10682 rc = bnx2x_prev_mcp_done(bp);
10683 if (!rc)
10684 rc = BNX2X_PREV_WAIT_NEEDED;
10685
10686 return rc;
10687}
10688
0329aba1 10689static int bnx2x_prev_unload_common(struct bnx2x *bp)
452427b0
YM		 10690{
10691 u32 reset_reg, tmp_reg = 0, rc;
c63da990 10692 bool prev_undi = false;
1ef1d45a
BW		 10693 struct bnx2x_mac_vals mac_vals;
10694
452427b0
YM		 10695 /* It is possible a previous function received 'common' answer,
10696 * but hasn't loaded yet, therefore creating a scenario of
10697 * multiple functions receiving 'common' on the same path.
10698 */
10699 BNX2X_DEV_INFO("Common unload Flow\n");
10700
1ef1d45a
BW		 10701 memset(&mac_vals, 0, sizeof(mac_vals));
10702
452427b0
YM		 10703 if (bnx2x_prev_is_path_marked(bp))
10704 return bnx2x_prev_mcp_done(bp);
10705
10706 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10707
10708 /* Reset should be performed after BRB is emptied */
10709 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10710 u32 timer_count = 1000;
452427b0
YM		 10711
10712 /* Close the MAC Rx to prevent BRB from filling up */
1ef1d45a
BW		 10713 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10714
3d6b7253 10715 /* close LLH filters for both ports towards the BRB */
1ef1d45a 10716 bnx2x_set_rx_filter(&bp->link_params, 0);
3d6b7253 10717 bp->link_params.port ^= 1;
1ef1d45a 10718 bnx2x_set_rx_filter(&bp->link_params, 0);
3d6b7253 10719 bp->link_params.port ^= 1;
452427b0 10720
b17b0ca1
YM		 10721 /* Check if the UNDI driver was previously loaded */
10722 if (bnx2x_prev_is_after_undi(bp)) {
10723 prev_undi = true;
10724 /* clear the UNDI indication */
10725 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10726 /* clear possible idle check errors */
10727 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
452427b0 10728 }
d46f7c4d
DK		 10729 if (!CHIP_IS_E1x(bp))
10730 /* block FW from writing to host */
10731 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10732
452427b0
YM		 10733 /* wait until BRB is empty */
10734 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10735 while (timer_count) {
10736 u32 prev_brb = tmp_reg;
34f80b04 10737
452427b0
YM		 10738 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10739 if (!tmp_reg)
10740 break;
619c5cb6 10741
452427b0 10742 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
619c5cb6 10743
452427b0
YM		 10744 /* reset timer as long as BRB actually gets emptied */
10745 if (prev_brb > tmp_reg)
10746 timer_count = 1000;
10747 else
10748 timer_count--;
da5a662a 10749
7c3afd85
YM		 10750 /* If UNDI resides in memory, manually increment it */
10751 if (prev_undi)
10752 bnx2x_prev_unload_undi_inc(bp, 1);
10753
452427b0 10754 udelay(10);
7a06a122 10755 }
452427b0
YM		 10756
10757 if (!timer_count)
10758 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
34f80b04 10759 }
f16da43b 10760
452427b0
YM		 10761 /* No packets are in the pipeline, path is ready for reset */
10762 bnx2x_reset_common(bp);
10763
1ef1d45a
BW		 10764 if (mac_vals.xmac_addr)
10765 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
3d6b7253
YM		 10766 if (mac_vals.umac_addr[0])
10767 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10768 if (mac_vals.umac_addr[1])
10769 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
1ef1d45a
BW		 10770 if (mac_vals.emac_addr)
10771 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10772 if (mac_vals.bmac_addr) {
10773 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10774 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10775 }
10776
c63da990 10777 rc = bnx2x_prev_mark_path(bp, prev_undi);
452427b0
YM		 10778 if (rc) {
10779 bnx2x_prev_mcp_done(bp);
10780 return rc;
10781 }
10782
10783 return bnx2x_prev_mcp_done(bp);
10784}
10785
0329aba1 10786static int bnx2x_prev_unload(struct bnx2x *bp)
452427b0
YM		 10787{
10788 int time_counter = 10;
10789 u32 rc, fw, hw_lock_reg, hw_lock_val;
10790 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10791
24f06716
AE		 10792 /* clear hw from errors which may have resulted from an interrupted
10793 * dmae transaction.
10794 */
da254fbc 10795 bnx2x_clean_pglue_errors(bp);
24f06716
AE		 10796
10797 /* Release previously held locks */
452427b0
YM		 10798 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10799 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10800 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10801
3cdeec22 10802 hw_lock_val = REG_RD(bp, hw_lock_reg);
452427b0
YM		 10803 if (hw_lock_val) {
10804 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10805 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10806 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10807 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10808 }
10809
10810 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10811 REG_WR(bp, hw_lock_reg, 0xffffffff);
10812 } else
10813 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10814
10815 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10816 BNX2X_DEV_INFO("Release previously held alr\n");
3cdeec22 10817 bnx2x_release_alr(bp);
452427b0
YM		 10818 }
10819
452427b0 10820 do {
7fa6f340 10821 int aer = 0;
452427b0
YM		 10822 /* Lock MCP using an unload request */
10823 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10824 if (!fw) {
10825 BNX2X_ERR("MCP response failure, aborting\n");
10826 rc = -EBUSY;
10827 break;
10828 }
10829
7fa6f340
YM		 10830 rc = down_interruptible(&bnx2x_prev_sem);
10831 if (rc) {
10832 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10833 rc);
10834 } else {
10835 /* If Path is marked by EEH, ignore unload status */
10836 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10837 bnx2x_prev_path_get_entry(bp)->aer);
60cde81f 10838 up(&bnx2x_prev_sem);
7fa6f340 10839 }
7fa6f340
YM		 10840
10841 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
452427b0
YM		 10842 rc = bnx2x_prev_unload_common(bp);
10843 break;
10844 }
10845
16a5fd92 10846 /* non-common reply from MCP might require looping */
452427b0
YM		 10847 rc = bnx2x_prev_unload_uncommon(bp);
10848 if (rc != BNX2X_PREV_WAIT_NEEDED)
10849 break;
10850
10851 msleep(20);
10852 } while (--time_counter);
10853
10854 if (!time_counter || rc) {
91ebb929
YM		 10855 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10856 rc = -EPROBE_DEFER;
452427b0
YM		 10857 }
10858
c63da990 10859 /* Mark function if its port was used to boot from SAN */
178135c1 10860 if (bnx2x_port_after_undi(bp))
c63da990
BW		 10861 bp->link_params.feature_config_flags |=
10862 FEATURE_CONFIG_BOOT_FROM_SAN;
10863
452427b0
YM		 10864 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10865
10866 return rc;
34f80b04
EG		 10867}
10868
0329aba1 10869static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
34f80b04 10870{
1d187b34 10871 u32 val, val2, val3, val4, id, boot_mode;
72ce58c3 10872 u16 pmc;
34f80b04
EG		 10873
10874 /* Get the chip revision id and number. */
10875 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10876 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10877 id = ((val & 0xffff) << 16);
10878 val = REG_RD(bp, MISC_REG_CHIP_REV);
10879 id |= ((val & 0xf) << 12);
f22fdf25
YM		 10880
10881 /* Metal is read from PCI regs, but we can't access >=0x400 from
10882 * the configuration space (so we need to reg_rd)
10883 */
10884 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10885 id |= (((val >> 24) & 0xf) << 4);
5a40e08e 10886 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 10887 id |= (val & 0xf);
10888 bp->common.chip_id = id;
523224a3 10889
7e8e02df
BW		 10890 /* force 57811 according to MISC register */
10891 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10892 if (CHIP_IS_57810(bp))
10893 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10894 (bp->common.chip_id & 0x0000FFFF);
10895 else if (CHIP_IS_57810_MF(bp))
10896 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10897 (bp->common.chip_id & 0x0000FFFF);
10898 bp->common.chip_id |= 0x1;
10899 }
10900
523224a3
DK		 10901 /* Set doorbell size */
10902 bp->db_size = (1 << BNX2X_DB_SHIFT);
10903
619c5cb6 10904 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 10905 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10906 if ((val & 1) == 0)
10907 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10908 else
10909 val = (val >> 1) & 1;
10910 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10911 "2_PORT_MODE");
10912 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10913 CHIP_2_PORT_MODE;
10914
10915 if (CHIP_MODE_IS_4_PORT(bp))
10916 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10917 else
10918 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10919 } else {
10920 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10921 bp->pfid = bp->pf_num; /* 0..7 */
10922 }
10923
51c1a580
MS		 10924 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10925
f2e0899f
DK		 10926 bp->link_params.chip_id = bp->common.chip_id;
10927 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 10928
1c06328c
EG		 10929 val = (REG_RD(bp, 0x2874) & 0x55);
10930 if ((bp->common.chip_id & 0x1) ||
10931 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10932 bp->flags |= ONE_PORT_FLAG;
10933 BNX2X_DEV_INFO("single port device\n");
10934 }
10935
34f80b04 10936 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 10937 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 10938 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10939 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10940 bp->common.flash_size, bp->common.flash_size);
10941
1b6e2ceb
DK		 10942 bnx2x_init_shmem(bp);
10943
f2e0899f
DK		 10944 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10945 MISC_REG_GENERIC_CR_1 :
10946 MISC_REG_GENERIC_CR_0));
1b6e2ceb 10947
34f80b04 10948 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 10949 bp->link_params.shmem2_base = bp->common.shmem2_base;
b884d95b
YR		 10950 if (SHMEM2_RD(bp, size) >
10951 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10952 bp->link_params.lfa_base =
10953 REG_RD(bp, bp->common.shmem2_base +
10954 (u32)offsetof(struct shmem2_region,
10955 lfa_host_addr[BP_PORT(bp)]));
10956 else
10957 bp->link_params.lfa_base = 0;
2691d51d
EG		 10958 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10959 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 10960
f2e0899f 10961 if (!bp->common.shmem_base) {
34f80b04
EG		 10962 BNX2X_DEV_INFO("MCP not active\n");
10963 bp->flags |= NO_MCP_FLAG;
10964 return;
10965 }
10966
34f80b04 10967 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 10968 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 10969
10970 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10971 SHARED_HW_CFG_LED_MODE_MASK) >>
10972 SHARED_HW_CFG_LED_MODE_SHIFT);
10973
c2c8b03e
EG		 10974 bp->link_params.feature_config_flags = 0;
10975 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10976 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10977 bp->link_params.feature_config_flags |=
10978 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10979 else
10980 bp->link_params.feature_config_flags &=
10981 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10982
34f80b04
EG		 10983 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10984 bp->common.bc_ver = val;
10985 BNX2X_DEV_INFO("bc_ver %X\n", val);
10986 if (val < BNX2X_BC_VER) {
10987 /* for now only warn
10988 * later we might need to enforce this */
51c1a580
MS		 10989 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10990 BNX2X_BC_VER, val);
34f80b04 10991 }
4d295db0 10992 bp->link_params.feature_config_flags |=
a22f0788 10993 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 10994 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10995
a22f0788
YR		 10996 bp->link_params.feature_config_flags |=
10997 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10998 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
a3348722
BW		 10999 bp->link_params.feature_config_flags |=
11000 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
11001 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
85242eea
YR		 11002 bp->link_params.feature_config_flags |=
11003 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
11004 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
55386fe8
YR		 11005
11006 bp->link_params.feature_config_flags |=
11007 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
11008 FEATURE_CONFIG_MT_SUPPORT : 0;
11009
0e898dd7
BW		 11010 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
11011 BC_SUPPORTS_PFC_STATS : 0;
85242eea 11012
2e499d3c
BW		 11013 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
11014 BC_SUPPORTS_FCOE_FEATURES : 0;
11015
9876879f
BW		 11016 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
11017 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
a6d3a5ba
BW		 11018
11019 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
11020 BC_SUPPORTS_RMMOD_CMD : 0;
11021
1d187b34
BW		 11022 boot_mode = SHMEM_RD(bp,
11023 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
11024 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
11025 switch (boot_mode) {
11026 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
11027 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
11028 break;
11029 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
11030 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
11031 break;
11032 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
11033 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
11034 break;
11035 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
11036 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
11037 break;
11038 }
11039
29ed74c3 11040 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
f9a3ebbe
DK		 11041 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
11042
72ce58c3 11043 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 11044 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 11045
11046 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
11047 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
11048 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
11049 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
11050
cdaa7cb8
VZ		 11051 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
11052 val, val2, val3, val4);
34f80b04
EG		 11053}
11054
f2e0899f
DK		 11055#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11056#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11057
0329aba1 11058static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
f2e0899f
DK		 11059{
11060 int pfid = BP_FUNC(bp);
f2e0899f
DK		 11061 int igu_sb_id;
11062 u32 val;
6383c0b3 11063 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 11064
11065 bp->igu_base_sb = 0xff;
f2e0899f 11066 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 11067 int vn = BP_VN(bp);
6383c0b3 11068 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 11069 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
11070 FP_SB_MAX_E1x;
11071
11072 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
11073 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
11074
9b341bb1 11075 return 0;
f2e0899f
DK		 11076 }
11077
11078 /* IGU in normal mode - read CAM */
11079 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
11080 igu_sb_id++) {
11081 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
11082 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
11083 continue;
11084 fid = IGU_FID(val);
11085 if ((fid & IGU_FID_ENCODE_IS_PF)) {
11086 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
11087 continue;
11088 if (IGU_VEC(val) == 0)
11089 /* default status block */
11090 bp->igu_dsb_id = igu_sb_id;
11091 else {
11092 if (bp->igu_base_sb == 0xff)
11093 bp->igu_base_sb = igu_sb_id;
6383c0b3 11094 igu_sb_cnt++;
f2e0899f
DK		 11095 }
11096 }
11097 }
619c5cb6 11098
6383c0b3 11099#ifdef CONFIG_PCI_MSI
185d4c8b
AE		 11100 /* Due to new PF resource allocation by MFW T7.4 and above, it's
11101 * optional that number of CAM entries will not be equal to the value
11102 * advertised in PCI.
11103 * Driver should use the minimal value of both as the actual status
11104 * block count
619c5cb6 11105 */
185d4c8b 11106 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
6383c0b3 11107#endif
619c5cb6 11108
9b341bb1 11109 if (igu_sb_cnt == 0) {
f2e0899f 11110 BNX2X_ERR("CAM configuration error\n");
9b341bb1
BW		 11111 return -EINVAL;
11112 }
11113
11114 return 0;
f2e0899f
DK		 11115}
11116
1dd06ae8 11117static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
a2fbb9ea 11118{
a22f0788
YR		 11119 int cfg_size = 0, idx, port = BP_PORT(bp);
11120
11121 /* Aggregation of supported attributes of all external phys */
11122 bp->port.supported[0] = 0;
11123 bp->port.supported[1] = 0;
b7737c9b
YR		 11124 switch (bp->link_params.num_phys) {
11125 case 1:
a22f0788
YR		 11126 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
11127 cfg_size = 1;
11128 break;
b7737c9b 11129 case 2:
a22f0788
YR		 11130 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
11131 cfg_size = 1;
11132 break;
11133 case 3:
11134 if (bp->link_params.multi_phy_config &
11135 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11136 bp->port.supported[1] =
11137 bp->link_params.phy[EXT_PHY1].supported;
11138 bp->port.supported[0] =
11139 bp->link_params.phy[EXT_PHY2].supported;
11140 } else {
11141 bp->port.supported[0] =
11142 bp->link_params.phy[EXT_PHY1].supported;
11143 bp->port.supported[1] =
11144 bp->link_params.phy[EXT_PHY2].supported;
11145 }
11146 cfg_size = 2;
11147 break;
b7737c9b 11148 }
a2fbb9ea 11149
a22f0788 11150 if (!(bp->port.supported[0] || bp->port.supported[1])) {
51c1a580 11151 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 11152 SHMEM_RD(bp,
a22f0788
YR		 11153 dev_info.port_hw_config[port].external_phy_config),
11154 SHMEM_RD(bp,
11155 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 11156 return;
f85582f8 11157 }
a2fbb9ea 11158
619c5cb6
VZ		 11159 if (CHIP_IS_E3(bp))
11160 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
11161 else {
11162 switch (switch_cfg) {
11163 case SWITCH_CFG_1G:
11164 bp->port.phy_addr = REG_RD(
11165 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11166 break;
11167 case SWITCH_CFG_10G:
11168 bp->port.phy_addr = REG_RD(
11169 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11170 break;
11171 default:
11172 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11173 bp->port.link_config[0]);
11174 return;
11175 }
a2fbb9ea 11176 }
619c5cb6 11177 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 11178 /* mask what we support according to speed_cap_mask per configuration */
11179 for (idx = 0; idx < cfg_size; idx++) {
11180 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11181 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 11182 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 11183
a22f0788 11184 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11185 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 11186 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 11187
a22f0788 11188 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11189 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 11190 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 11191
a22f0788 11192 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11193 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 11194 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 11195
a22f0788 11196 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11197 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 11198 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 11199 SUPPORTED_1000baseT_Full);
a2fbb9ea 11200
a22f0788 11201 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11202 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 11203 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 11204
a22f0788 11205 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11206 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788 11207 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
b8e0d884
YR		 11208
11209 if (!(bp->link_params.speed_cap_mask[idx] &
11210 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11211 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
a22f0788 11212 }
a2fbb9ea 11213
a22f0788
YR		 11214 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11215 bp->port.supported[1]);
a2fbb9ea
ET		 11216}
11217
0329aba1 11218static void bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 11219{
a22f0788
YR		 11220 u32 link_config, idx, cfg_size = 0;
11221 bp->port.advertising[0] = 0;
11222 bp->port.advertising[1] = 0;
11223 switch (bp->link_params.num_phys) {
11224 case 1:
11225 case 2:
11226 cfg_size = 1;
11227 break;
11228 case 3:
11229 cfg_size = 2;
11230 break;
11231 }
11232 for (idx = 0; idx < cfg_size; idx++) {
11233 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11234 link_config = bp->port.link_config[idx];
11235 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 11236 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 11237 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11238 bp->link_params.req_line_speed[idx] =
11239 SPEED_AUTO_NEG;
11240 bp->port.advertising[idx] |=
11241 bp->port.supported[idx];
10bd1f24
MY		 11242 if (bp->link_params.phy[EXT_PHY1].type ==
11243 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11244 bp->port.advertising[idx] |=
11245 (SUPPORTED_100baseT_Half |
11246 SUPPORTED_100baseT_Full);
f85582f8
DK		 11247 } else {
11248 /* force 10G, no AN */
a22f0788
YR		 11249 bp->link_params.req_line_speed[idx] =
11250 SPEED_10000;
11251 bp->port.advertising[idx] |=
11252 (ADVERTISED_10000baseT_Full |
f85582f8 11253 ADVERTISED_FIBRE);
a22f0788 11254 continue;
f85582f8
DK		 11255 }
11256 break;
a2fbb9ea 11257
f85582f8 11258 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 11259 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11260 bp->link_params.req_line_speed[idx] =
11261 SPEED_10;
11262 bp->port.advertising[idx] |=
11263 (ADVERTISED_10baseT_Full |
f85582f8
DK		 11264 ADVERTISED_TP);
11265 } else {
51c1a580 11266 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8 11267 link_config,
a22f0788 11268 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11269 return;
11270 }
11271 break;
a2fbb9ea 11272
f85582f8 11273 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 11274 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11275 bp->link_params.req_line_speed[idx] =
11276 SPEED_10;
11277 bp->link_params.req_duplex[idx] =
11278 DUPLEX_HALF;
11279 bp->port.advertising[idx] |=
11280 (ADVERTISED_10baseT_Half |
f85582f8
DK		 11281 ADVERTISED_TP);
11282 } else {
51c1a580 11283 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 11284 link_config,
11285 bp->link_params.speed_cap_mask[idx]);
11286 return;
11287 }
11288 break;
a2fbb9ea 11289
f85582f8
DK		 11290 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11291 if (bp->port.supported[idx] &
11292 SUPPORTED_100baseT_Full) {
a22f0788
YR		 11293 bp->link_params.req_line_speed[idx] =
11294 SPEED_100;
11295 bp->port.advertising[idx] |=
11296 (ADVERTISED_100baseT_Full |
f85582f8
DK		 11297 ADVERTISED_TP);
11298 } else {
51c1a580 11299 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 11300 link_config,
11301 bp->link_params.speed_cap_mask[idx]);
11302 return;
11303 }
11304 break;
a2fbb9ea 11305
f85582f8
DK		 11306 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11307 if (bp->port.supported[idx] &
11308 SUPPORTED_100baseT_Half) {
11309 bp->link_params.req_line_speed[idx] =
11310 SPEED_100;
11311 bp->link_params.req_duplex[idx] =
11312 DUPLEX_HALF;
a22f0788
YR		 11313 bp->port.advertising[idx] |=
11314 (ADVERTISED_100baseT_Half |
f85582f8
DK		 11315 ADVERTISED_TP);
11316 } else {
51c1a580 11317 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11318 link_config,
11319 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11320 return;
11321 }
11322 break;
a2fbb9ea 11323
f85582f8 11324 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 11325 if (bp->port.supported[idx] &
11326 SUPPORTED_1000baseT_Full) {
11327 bp->link_params.req_line_speed[idx] =
11328 SPEED_1000;
11329 bp->port.advertising[idx] |=
11330 (ADVERTISED_1000baseT_Full |
f85582f8 11331 ADVERTISED_TP);
5d67c1c5
YM		 11332 } else if (bp->port.supported[idx] &
11333 SUPPORTED_1000baseKX_Full) {
11334 bp->link_params.req_line_speed[idx] =
11335 SPEED_1000;
11336 bp->port.advertising[idx] |=
11337 ADVERTISED_1000baseKX_Full;
f85582f8 11338 } else {
51c1a580 11339 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11340 link_config,
11341 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11342 return;
11343 }
11344 break;
a2fbb9ea 11345
f85582f8 11346 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 11347 if (bp->port.supported[idx] &
11348 SUPPORTED_2500baseX_Full) {
11349 bp->link_params.req_line_speed[idx] =
11350 SPEED_2500;
11351 bp->port.advertising[idx] |=
11352 (ADVERTISED_2500baseX_Full |
34f80b04 11353 ADVERTISED_TP);
f85582f8 11354 } else {
51c1a580 11355 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11356 link_config,
f85582f8
DK		 11357 bp->link_params.speed_cap_mask[idx]);
11358 return;
11359 }
11360 break;
a2fbb9ea 11361
f85582f8 11362 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 11363 if (bp->port.supported[idx] &
11364 SUPPORTED_10000baseT_Full) {
11365 bp->link_params.req_line_speed[idx] =
11366 SPEED_10000;
11367 bp->port.advertising[idx] |=
11368 (ADVERTISED_10000baseT_Full |
34f80b04 11369 ADVERTISED_FIBRE);
5d67c1c5
YM		 11370 } else if (bp->port.supported[idx] &
11371 SUPPORTED_10000baseKR_Full) {
11372 bp->link_params.req_line_speed[idx] =
11373 SPEED_10000;
11374 bp->port.advertising[idx] |=
11375 (ADVERTISED_10000baseKR_Full |
11376 ADVERTISED_FIBRE);
f85582f8 11377 } else {
51c1a580 11378 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11379 link_config,
f85582f8
DK		 11380 bp->link_params.speed_cap_mask[idx]);
11381 return;
11382 }
11383 break;
3c9ada22
YR		 11384 case PORT_FEATURE_LINK_SPEED_20G:
11385 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 11386
3c9ada22 11387 break;
f85582f8 11388 default:
51c1a580 11389 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
754a2f52 11390 link_config);
f85582f8
DK		 11391 bp->link_params.req_line_speed[idx] =
11392 SPEED_AUTO_NEG;
11393 bp->port.advertising[idx] =
11394 bp->port.supported[idx];
11395 break;
11396 }
a2fbb9ea 11397
a22f0788 11398 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 11399 PORT_FEATURE_FLOW_CONTROL_MASK);
cd1dfce2
YM		 11400 if (bp->link_params.req_flow_ctrl[idx] ==
11401 BNX2X_FLOW_CTRL_AUTO) {
11402 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11403 bp->link_params.req_flow_ctrl[idx] =
11404 BNX2X_FLOW_CTRL_NONE;
11405 else
11406 bnx2x_set_requested_fc(bp);
a22f0788 11407 }
a2fbb9ea 11408
51c1a580 11409 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
a22f0788
YR		 11410 bp->link_params.req_line_speed[idx],
11411 bp->link_params.req_duplex[idx],
11412 bp->link_params.req_flow_ctrl[idx],
11413 bp->port.advertising[idx]);
11414 }
a2fbb9ea
ET		 11415}
11416
0329aba1 11417static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
e665bfda 11418{
86564c3f
YM		 11419 __be16 mac_hi_be = cpu_to_be16(mac_hi);
11420 __be32 mac_lo_be = cpu_to_be32(mac_lo);
11421 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11422 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
e665bfda
MC		 11423}
11424
0329aba1 11425static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 11426{
34f80b04 11427 int port = BP_PORT(bp);
589abe3a 11428 u32 config;
c8c60d88 11429 u32 ext_phy_type, ext_phy_config, eee_mode;
a2fbb9ea 11430
c18487ee 11431 bp->link_params.bp = bp;
34f80b04 11432 bp->link_params.port = port;
c18487ee 11433
c18487ee 11434 bp->link_params.lane_config =
a2fbb9ea 11435 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 11436
a22f0788 11437 bp->link_params.speed_cap_mask[0] =
a2fbb9ea 11438 SHMEM_RD(bp,
b0261926
YR		 11439 dev_info.port_hw_config[port].speed_capability_mask) &
11440 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788
YR		 11441 bp->link_params.speed_cap_mask[1] =
11442 SHMEM_RD(bp,
b0261926
YR		 11443 dev_info.port_hw_config[port].speed_capability_mask2) &
11444 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788 11445 bp->port.link_config[0] =
a2fbb9ea
ET		 11446 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11447
a22f0788
YR		 11448 bp->port.link_config[1] =
11449 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 11450
a22f0788
YR		 11451 bp->link_params.multi_phy_config =
11452 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 11453 /* If the device is capable of WoL, set the default state according
11454 * to the HW
11455 */
4d295db0 11456 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 11457 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11458 (config & PORT_FEATURE_WOL_ENABLED));
11459
4ba7699b
YM		 11460 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11461 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11462 bp->flags |= NO_ISCSI_FLAG;
11463 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11464 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11465 bp->flags |= NO_FCOE_FLAG;
11466
51c1a580 11467 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 11468 bp->link_params.lane_config,
a22f0788
YR		 11469 bp->link_params.speed_cap_mask[0],
11470 bp->port.link_config[0]);
a2fbb9ea 11471
a22f0788 11472 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 11473 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 11474 bnx2x_phy_probe(&bp->link_params);
c18487ee 11475 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 11476
11477 bnx2x_link_settings_requested(bp);
11478
01cd4528
EG		 11479 /*
11480 * If connected directly, work with the internal PHY, otherwise, work
11481 * with the external PHY
11482 */
b7737c9b
YR		 11483 ext_phy_config =
11484 SHMEM_RD(bp,
11485 dev_info.port_hw_config[port].external_phy_config);
11486 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 11487 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 11488 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 11489
11490 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11491 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11492 bp->mdio.prtad =
b7737c9b 11493 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d 11494
c8c60d88
YM		 11495 /* Configure link feature according to nvram value */
11496 eee_mode = (((SHMEM_RD(bp, dev_info.
11497 port_feature_config[port].eee_power_mode)) &
11498 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11499 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11500 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11501 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11502 EEE_MODE_ENABLE_LPI |
11503 EEE_MODE_OUTPUT_TIME;
11504 } else {
11505 bp->link_params.eee_mode = 0;
11506 }
0793f83f 11507}
01cd4528 11508
b306f5ed 11509void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 11510{
9e62e912 11511 u32 no_flags = NO_ISCSI_FLAG;
bf61ee14 11512 int port = BP_PORT(bp);
2ba45142 11513 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 11514 drv_lic_key[port].max_iscsi_conn);
2ba45142 11515
55c11941
MS		 11516 if (!CNIC_SUPPORT(bp)) {
11517 bp->flags |= no_flags;
11518 return;
11519 }
11520
b306f5ed 11521 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 11522 bp->cnic_eth_dev.max_iscsi_conn =
11523 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11524 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11525
b306f5ed
DK		 11526 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11527 bp->cnic_eth_dev.max_iscsi_conn);
11528
11529 /*
11530 * If maximum allowed number of connections is zero -
11531 * disable the feature.
11532 */
11533 if (!bp->cnic_eth_dev.max_iscsi_conn)
9e62e912 11534 bp->flags |= no_flags;
b306f5ed
DK		 11535}
11536
0329aba1 11537static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
9e62e912
DK		 11538{
11539 /* Port info */
11540 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11541 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11542 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11543 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11544
11545 /* Node info */
11546 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11547 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11548 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11549 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11550}
86800194
DK		 11551
11552static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11553{
11554 u8 count = 0;
11555
11556 if (IS_MF(bp)) {
11557 u8 fid;
11558
11559 /* iterate over absolute function ids for this path: */
11560 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11561 if (IS_MF_SD(bp)) {
11562 u32 cfg = MF_CFG_RD(bp,
11563 func_mf_config[fid].config);
11564
11565 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11566 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11567 FUNC_MF_CFG_PROTOCOL_FCOE))
11568 count++;
11569 } else {
11570 u32 cfg = MF_CFG_RD(bp,
11571 func_ext_config[fid].
11572 func_cfg);
11573
11574 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11575 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11576 count++;
11577 }
11578 }
11579 } else { /* SF */
11580 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11581
11582 for (port = 0; port < port_cnt; port++) {
11583 u32 lic = SHMEM_RD(bp,
11584 drv_lic_key[port].max_fcoe_conn) ^
11585 FW_ENCODE_32BIT_PATTERN;
11586 if (lic)
11587 count++;
11588 }
11589 }
11590
11591 return count;
11592}
11593
0329aba1 11594static void bnx2x_get_fcoe_info(struct bnx2x *bp)
b306f5ed
DK		 11595{
11596 int port = BP_PORT(bp);
11597 int func = BP_ABS_FUNC(bp);
b306f5ed
DK		 11598 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11599 drv_lic_key[port].max_fcoe_conn);
86800194 11600 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
b306f5ed 11601
55c11941
MS		 11602 if (!CNIC_SUPPORT(bp)) {
11603 bp->flags |= NO_FCOE_FLAG;
11604 return;
11605 }
11606
b306f5ed 11607 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 11608 bp->cnic_eth_dev.max_fcoe_conn =
11609 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11610 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11611
0eb43b4b
BPG		 11612 /* Calculate the number of maximum allowed FCoE tasks */
11613 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
86800194
DK		 11614
11615 /* check if FCoE resources must be shared between different functions */
11616 if (num_fcoe_func)
11617 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
0eb43b4b 11618
bf61ee14
VZ		 11619 /* Read the WWN: */
11620 if (!IS_MF(bp)) {
11621 /* Port info */
11622 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11623 SHMEM_RD(bp,
2de67439 11624 dev_info.port_hw_config[port].
bf61ee14
VZ		 11625 fcoe_wwn_port_name_upper);
11626 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11627 SHMEM_RD(bp,
2de67439 11628 dev_info.port_hw_config[port].
bf61ee14
VZ		 11629 fcoe_wwn_port_name_lower);
11630
11631 /* Node info */
11632 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11633 SHMEM_RD(bp,
2de67439 11634 dev_info.port_hw_config[port].
bf61ee14
VZ		 11635 fcoe_wwn_node_name_upper);
11636 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11637 SHMEM_RD(bp,
2de67439 11638 dev_info.port_hw_config[port].
bf61ee14
VZ		 11639 fcoe_wwn_node_name_lower);
11640 } else if (!IS_MF_SD(bp)) {
2e98ffc2 11641 /* Read the WWN info only if the FCoE feature is enabled for
bf61ee14
VZ		 11642 * this function.
11643 */
2e98ffc2
DK		 11644 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11645 bnx2x_get_ext_wwn_info(bp, func);
11646 } else {
11647 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
9e62e912 11648 bnx2x_get_ext_wwn_info(bp, func);
382e513a 11649 }
bf61ee14 11650
b306f5ed 11651 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 11652
bf61ee14
VZ		 11653 /*
11654 * If maximum allowed number of connections is zero -
2ba45142
VZ		 11655 * disable the feature.
11656 */
2ba45142
VZ		 11657 if (!bp->cnic_eth_dev.max_fcoe_conn)
11658 bp->flags |= NO_FCOE_FLAG;
11659}
b306f5ed 11660
0329aba1 11661static void bnx2x_get_cnic_info(struct bnx2x *bp)
b306f5ed
DK		 11662{
11663 /*
11664 * iSCSI may be dynamically disabled but reading
11665 * info here we will decrease memory usage by driver
11666 * if the feature is disabled for good
11667 */
11668 bnx2x_get_iscsi_info(bp);
11669 bnx2x_get_fcoe_info(bp);
11670}
2ba45142 11671
0329aba1 11672static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
0793f83f
DK		 11673{
11674 u32 val, val2;
11675 int func = BP_ABS_FUNC(bp);
11676 int port = BP_PORT(bp);
2ba45142
VZ		 11677 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11678 u8 *fip_mac = bp->fip_mac;
0793f83f 11679
55c11941
MS		 11680 if (IS_MF(bp)) {
11681 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142 11682 * FCoE MAC then the appropriate feature should be disabled.
55c11941
MS		 11683 * In non SD mode features configuration comes from struct
11684 * func_ext_config.
2ba45142 11685 */
2e98ffc2 11686 if (!IS_MF_SD(bp)) {
0793f83f
DK		 11687 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11688 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11689 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11690 iscsi_mac_addr_upper);
0793f83f 11691 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11692 iscsi_mac_addr_lower);
2ba45142 11693 bnx2x_set_mac_buf(iscsi_mac, val, val2);
55c11941
MS		 11694 BNX2X_DEV_INFO
11695 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11696 } else {
2ba45142 11697 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
55c11941 11698 }
2ba45142
VZ		 11699
11700 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11701 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11702 fcoe_mac_addr_upper);
2ba45142 11703 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11704 fcoe_mac_addr_lower);
2ba45142 11705 bnx2x_set_mac_buf(fip_mac, val, val2);
55c11941
MS		 11706 BNX2X_DEV_INFO
11707 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11708 } else {
2ba45142 11709 bp->flags |= NO_FCOE_FLAG;
55c11941 11710 }
a3348722
BW		 11711
11712 bp->mf_ext_config = cfg;
11713
9e62e912 11714 } else { /* SD MODE */
55c11941
MS		 11715 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11716 /* use primary mac as iscsi mac */
11717 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11718
11719 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11720 BNX2X_DEV_INFO
11721 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11722 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11723 /* use primary mac as fip mac */
11724 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11725 BNX2X_DEV_INFO("SD FCoE MODE\n");
11726 BNX2X_DEV_INFO
11727 ("Read FIP MAC: %pM\n", fip_mac);
614c76df 11728 }
0793f83f 11729 }
a3348722 11730
82594f8f
YM		 11731 /* If this is a storage-only interface, use SAN mac as
11732 * primary MAC. Notice that for SD this is already the case,
11733 * as the SAN mac was copied from the primary MAC.
11734 */
11735 if (IS_MF_FCOE_AFEX(bp))
a3348722 11736 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
0793f83f 11737 } else {
0793f83f 11738 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11739 iscsi_mac_upper);
0793f83f 11740 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11741 iscsi_mac_lower);
2ba45142 11742 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 11743
11744 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11745 fcoe_fip_mac_upper);
c03bd39c 11746 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11747 fcoe_fip_mac_lower);
c03bd39c 11748 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 11749 }
11750
55c11941 11751 /* Disable iSCSI OOO if MAC configuration is invalid. */
426b9241 11752 if (!is_valid_ether_addr(iscsi_mac)) {
55c11941 11753 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
c7bf7169 11754 eth_zero_addr(iscsi_mac);
426b9241
DK		 11755 }
11756
55c11941 11757 /* Disable FCoE if MAC configuration is invalid. */
426b9241
DK		 11758 if (!is_valid_ether_addr(fip_mac)) {
11759 bp->flags |= NO_FCOE_FLAG;
c7bf7169 11760 eth_zero_addr(bp->fip_mac);
426b9241 11761 }
55c11941
MS		 11762}
11763
0329aba1 11764static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
55c11941
MS		 11765{
11766 u32 val, val2;
11767 int func = BP_ABS_FUNC(bp);
11768 int port = BP_PORT(bp);
11769
11770 /* Zero primary MAC configuration */
c7bf7169 11771 eth_zero_addr(bp->dev->dev_addr);
55c11941
MS		 11772
11773 if (BP_NOMCP(bp)) {
11774 BNX2X_ERROR("warning: random MAC workaround active\n");
11775 eth_hw_addr_random(bp->dev);
11776 } else if (IS_MF(bp)) {
11777 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11778 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11779 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11780 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11781 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11782
11783 if (CNIC_SUPPORT(bp))
11784 bnx2x_get_cnic_mac_hwinfo(bp);
11785 } else {
11786 /* in SF read MACs from port configuration */
11787 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11788 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11789 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11790
11791 if (CNIC_SUPPORT(bp))
11792 bnx2x_get_cnic_mac_hwinfo(bp);
11793 }
11794
3d7d562c
YM		 11795 if (!BP_NOMCP(bp)) {
11796 /* Read physical port identifier from shmem */
11797 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11798 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11799 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11800 bp->flags |= HAS_PHYS_PORT_ID;
11801 }
11802
55c11941 11803 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
619c5cb6 11804
2e98ffc2 11805 if (!is_valid_ether_addr(bp->dev->dev_addr))
619c5cb6 11806 dev_err(&bp->pdev->dev,
51c1a580
MS		 11807 "bad Ethernet MAC address configuration: %pM\n"
11808 "change it manually before bringing up the appropriate network interface\n",
0f9dad10 11809 bp->dev->dev_addr);
7964211d 11810}
51c1a580 11811
0329aba1 11812static bool bnx2x_get_dropless_info(struct bnx2x *bp)
7964211d
YM		 11813{
11814 int tmp;
11815 u32 cfg;
51c1a580 11816
aeeddb8b 11817 if (IS_VF(bp))
4e833c59 11818 return false;
aeeddb8b 11819
7964211d
YM		 11820 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11821 /* Take function: tmp = func */
11822 tmp = BP_ABS_FUNC(bp);
11823 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11824 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11825 } else {
11826 /* Take port: tmp = port */
11827 tmp = BP_PORT(bp);
11828 cfg = SHMEM_RD(bp,
11829 dev_info.port_hw_config[tmp].generic_features);
11830 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11831 }
11832 return cfg;
34f80b04
EG		 11833}
11834
83bad206
YM		 11835static void validate_set_si_mode(struct bnx2x *bp)
11836{
11837 u8 func = BP_ABS_FUNC(bp);
11838 u32 val;
11839
11840 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11841
11842 /* check for legal mac (upper bytes) */
11843 if (val != 0xffff) {
11844 bp->mf_mode = MULTI_FUNCTION_SI;
11845 bp->mf_config[BP_VN(bp)] =
11846 MF_CFG_RD(bp, func_mf_config[func].config);
11847 } else
11848 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11849}
11850
0329aba1 11851static int bnx2x_get_hwinfo(struct bnx2x *bp)
34f80b04 11852{
0793f83f 11853 int /*abs*/func = BP_ABS_FUNC(bp);
230d00eb 11854 int vn, mfw_vn;
83bad206 11855 u32 val = 0, val2 = 0;
34f80b04 11856 int rc = 0;
a2fbb9ea 11857
0f587f1b
YM		 11858 /* Validate that chip access is feasible */
11859 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11860 dev_err(&bp->pdev->dev,
11861 "Chip read returns all Fs. Preventing probe from continuing\n");
11862 return -EINVAL;
11863 }
11864
34f80b04 11865 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 11866
6383c0b3
AE		 11867 /*
11868 * initialize IGU parameters
11869 */
f2e0899f
DK		 11870 if (CHIP_IS_E1x(bp)) {
11871 bp->common.int_block = INT_BLOCK_HC;
11872
11873 bp->igu_dsb_id = DEF_SB_IGU_ID;
11874 bp->igu_base_sb = 0;
f2e0899f
DK		 11875 } else {
11876 bp->common.int_block = INT_BLOCK_IGU;
7a06a122 11877
16a5fd92 11878 /* do not allow device reset during IGU info processing */
7a06a122
DK		 11879 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11880
f2e0899f 11881 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 11882
11883 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11884 int tout = 5000;
11885
11886 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11887
11888 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11889 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11890 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11891
11892 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11893 tout--;
0926d499 11894 usleep_range(1000, 2000);
619c5cb6
VZ		 11895 }
11896
11897 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11898 dev_err(&bp->pdev->dev,
11899 "FORCING Normal Mode failed!!!\n");
9b341bb1
BW		 11900 bnx2x_release_hw_lock(bp,
11901 HW_LOCK_RESOURCE_RESET);
619c5cb6
VZ		 11902 return -EPERM;
11903 }
11904 }
11905
f2e0899f 11906 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 11907 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 11908 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11909 } else
619c5cb6 11910 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 11911
9b341bb1 11912 rc = bnx2x_get_igu_cam_info(bp);
7a06a122 11913 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9b341bb1
BW		 11914 if (rc)
11915 return rc;
f2e0899f 11916 }
619c5cb6
VZ		 11917
11918 /*
11919 * set base FW non-default (fast path) status block id, this value is
11920 * used to initialize the fw_sb_id saved on the fp/queue structure to
11921 * determine the id used by the FW.
11922 */
11923 if (CHIP_IS_E1x(bp))
11924 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11925 else /*
11926 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11927 * the same queue are indicated on the same IGU SB). So we prefer
11928 * FW and IGU SBs to be the same value.
11929 */
11930 bp->base_fw_ndsb = bp->igu_base_sb;
11931
11932 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11933 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11934 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 11935
11936 /*
11937 * Initialize MF configuration
11938 */
523224a3 11939
fb3bff17
DK		 11940 bp->mf_ov = 0;
11941 bp->mf_mode = 0;
7609647e 11942 bp->mf_sub_mode = 0;
3395a033 11943 vn = BP_VN(bp);
230d00eb 11944 mfw_vn = BP_FW_MB_IDX(bp);
0793f83f 11945
f2e0899f 11946 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 11947 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11948 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11949 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11950
f2e0899f
DK		 11951 if (SHMEM2_HAS(bp, mf_cfg_addr))
11952 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11953 else
11954 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 11955 offsetof(struct shmem_region, func_mb) +
11956 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 11957 /*
11958 * get mf configuration:
16a5fd92 11959 * 1. Existence of MF configuration
0793f83f
DK		 11960 * 2. MAC address must be legal (check only upper bytes)
11961 * for Switch-Independent mode;
11962 * OVLAN must be legal for Switch-Dependent mode
11963 * 3. SF_MODE configures specific MF mode
11964 */
11965 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11966 /* get mf configuration */
11967 val = SHMEM_RD(bp,
11968 dev_info.shared_feature_config.config);
11969 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11970
11971 switch (val) {
11972 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
83bad206 11973 validate_set_si_mode(bp);
0793f83f 11974 break;
a3348722
BW		 11975 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11976 if ((!CHIP_IS_E1x(bp)) &&
11977 (MF_CFG_RD(bp, func_mf_config[func].
11978 mac_upper) != 0xffff) &&
11979 (SHMEM2_HAS(bp,
11980 afex_driver_support))) {
11981 bp->mf_mode = MULTI_FUNCTION_AFEX;
11982 bp->mf_config[vn] = MF_CFG_RD(bp,
11983 func_mf_config[func].config);
11984 } else {
11985 BNX2X_DEV_INFO("can not configure afex mode\n");
11986 }
11987 break;
0793f83f
DK		 11988 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11989 /* get OV configuration */
11990 val = MF_CFG_RD(bp,
11991 func_mf_config[FUNC_0].e1hov_tag);
11992 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11993
11994 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11995 bp->mf_mode = MULTI_FUNCTION_SD;
11996 bp->mf_config[vn] = MF_CFG_RD(bp,
11997 func_mf_config[func].config);
11998 } else
754a2f52 11999 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f 12000 break;
230d00eb
YM		 12001 case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
12002 bp->mf_mode = MULTI_FUNCTION_SD;
12003 bp->mf_sub_mode = SUB_MF_MODE_BD;
12004 bp->mf_config[vn] =
12005 MF_CFG_RD(bp,
12006 func_mf_config[func].config);
12007
12008 if (SHMEM2_HAS(bp, mtu_size)) {
12009 int mtu_idx = BP_FW_MB_IDX(bp);
12010 u16 mtu_size;
12011 u32 mtu;
12012
12013 mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
12014 mtu_size = (u16)mtu;
12015 DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
12016 mtu_size, mtu);
12017
12018 /* if valid: update device mtu */
12019 if (((mtu_size + ETH_HLEN) >=
12020 ETH_MIN_PACKET_SIZE) &&
12021 (mtu_size <=
12022 ETH_MAX_JUMBO_PACKET_SIZE))
12023 bp->dev->mtu = mtu_size;
12024 }
12025 break;
7609647e
YM		 12026 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
12027 bp->mf_mode = MULTI_FUNCTION_SD;
12028 bp->mf_sub_mode = SUB_MF_MODE_UFP;
12029 bp->mf_config[vn] =
12030 MF_CFG_RD(bp,
12031 func_mf_config[func].config);
12032 break;
3786b942
AE		 12033 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
12034 bp->mf_config[vn] = 0;
12035 break;
83bad206
YM		 12036 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
12037 val2 = SHMEM_RD(bp,
12038 dev_info.shared_hw_config.config_3);
12039 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
12040 switch (val2) {
12041 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
12042 validate_set_si_mode(bp);
12043 bp->mf_sub_mode =
12044 SUB_MF_MODE_NPAR1_DOT_5;
12045 break;
12046 default:
12047 /* Unknown configuration */
12048 bp->mf_config[vn] = 0;
12049 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12050 val);
12051 }
12052 break;
0793f83f
DK		 12053 default:
12054 /* Unknown configuration: reset mf_config */
12055 bp->mf_config[vn] = 0;
51c1a580 12056 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
0793f83f
DK		 12057 }
12058 }
a2fbb9ea 12059
2691d51d 12060 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 12061 IS_MF(bp) ? "multi" : "single");
2691d51d 12062
0793f83f
DK		 12063 switch (bp->mf_mode) {
12064 case MULTI_FUNCTION_SD:
12065 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
12066 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 12067 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 12068 bp->mf_ov = val;
619c5cb6
VZ		 12069 bp->path_has_ovlan = true;
12070
51c1a580
MS		 12071 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12072 func, bp->mf_ov, bp->mf_ov);
230d00eb
YM		 12073 } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
12074 (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
7609647e 12075 dev_err(&bp->pdev->dev,
230d00eb 12076 "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
7609647e
YM		 12077 func);
12078 bp->path_has_ovlan = true;
2691d51d 12079 } else {
619c5cb6 12080 dev_err(&bp->pdev->dev,
51c1a580
MS		 12081 "No valid MF OV for func %d, aborting\n",
12082 func);
619c5cb6 12083 return -EPERM;
34f80b04 12084 }
0793f83f 12085 break;
a3348722
BW		 12086 case MULTI_FUNCTION_AFEX:
12087 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
12088 break;
0793f83f 12089 case MULTI_FUNCTION_SI:
51c1a580
MS		 12090 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12091 func);
0793f83f
DK		 12092 break;
12093 default:
12094 if (vn) {
619c5cb6 12095 dev_err(&bp->pdev->dev,
51c1a580
MS		 12096 "VN %d is in a single function mode, aborting\n",
12097 vn);
619c5cb6 12098 return -EPERM;
2691d51d 12099 }
0793f83f 12100 break;
34f80b04 12101 }
0793f83f 12102
619c5cb6
VZ		 12103 /* check if other port on the path needs ovlan:
12104 * Since MF configuration is shared between ports
12105 * Possible mixed modes are only
12106 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12107 */
12108 if (CHIP_MODE_IS_4_PORT(bp) &&
12109 !bp->path_has_ovlan &&
12110 !IS_MF(bp) &&
12111 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12112 u8 other_port = !BP_PORT(bp);
12113 u8 other_func = BP_PATH(bp) + 2*other_port;
12114 val = MF_CFG_RD(bp,
12115 func_mf_config[other_func].e1hov_tag);
12116 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
12117 bp->path_has_ovlan = true;
12118 }
34f80b04 12119 }
a2fbb9ea 12120
e848582c
DK		 12121 /* adjust igu_sb_cnt to MF for E1H */
12122 if (CHIP_IS_E1H(bp) && IS_MF(bp))
12123 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
523224a3 12124
619c5cb6
VZ		 12125 /* port info */
12126 bnx2x_get_port_hwinfo(bp);
f2e0899f 12127
0793f83f
DK		 12128 /* Get MAC addresses */
12129 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 12130
2ba45142 12131 bnx2x_get_cnic_info(bp);
2ba45142 12132
34f80b04
EG		 12133 return rc;
12134}
12135
0329aba1 12136static void bnx2x_read_fwinfo(struct bnx2x *bp)
34f24c7f
VZ		 12137{
12138 int cnt, i, block_end, rodi;
fcdf95cb 12139 char vpd_start[BNX2X_VPD_LEN+1];
34f24c7f
VZ		 12140 char str_id_reg[VENDOR_ID_LEN+1];
12141 char str_id_cap[VENDOR_ID_LEN+1];
fcdf95cb
BW		 12142 char *vpd_data;
12143 char *vpd_extended_data = NULL;
34f24c7f
VZ		 12144 u8 len;
12145
fcdf95cb 12146 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
34f24c7f
VZ		 12147 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
12148
12149 if (cnt < BNX2X_VPD_LEN)
12150 goto out_not_found;
12151
fcdf95cb
BW		 12152 /* VPD RO tag should be first tag after identifier string, hence
12153 * we should be able to find it in first BNX2X_VPD_LEN chars
12154 */
12155 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
34f24c7f
VZ		 12156 PCI_VPD_LRDT_RO_DATA);
12157 if (i < 0)
12158 goto out_not_found;
12159
34f24c7f 12160 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
fcdf95cb 12161 pci_vpd_lrdt_size(&vpd_start[i]);
34f24c7f
VZ		 12162
12163 i += PCI_VPD_LRDT_TAG_SIZE;
12164
fcdf95cb
BW		 12165 if (block_end > BNX2X_VPD_LEN) {
12166 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
12167 if (vpd_extended_data == NULL)
12168 goto out_not_found;
12169
12170 /* read rest of vpd image into vpd_extended_data */
12171 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
12172 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
12173 block_end - BNX2X_VPD_LEN,
12174 vpd_extended_data + BNX2X_VPD_LEN);
12175 if (cnt < (block_end - BNX2X_VPD_LEN))
12176 goto out_not_found;
12177 vpd_data = vpd_extended_data;
12178 } else
12179 vpd_data = vpd_start;
12180
12181 /* now vpd_data holds full vpd content in both cases */
34f24c7f
VZ		 12182
12183 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12184 PCI_VPD_RO_KEYWORD_MFR_ID);
12185 if (rodi < 0)
12186 goto out_not_found;
12187
12188 len = pci_vpd_info_field_size(&vpd_data[rodi]);
12189
12190 if (len != VENDOR_ID_LEN)
12191 goto out_not_found;
12192
12193 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12194
12195 /* vendor specific info */
12196 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12197 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12198 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12199 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12200
12201 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12202 PCI_VPD_RO_KEYWORD_VENDOR0);
12203 if (rodi >= 0) {
12204 len = pci_vpd_info_field_size(&vpd_data[rodi]);
12205
12206 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12207
12208 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12209 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12210 bp->fw_ver[len] = ' ';
12211 }
12212 }
fcdf95cb 12213 kfree(vpd_extended_data);
34f24c7f
VZ		 12214 return;
12215 }
12216out_not_found:
fcdf95cb 12217 kfree(vpd_extended_data);
34f24c7f
VZ		 12218 return;
12219}
12220
0329aba1 12221static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
619c5cb6
VZ		 12222{
12223 u32 flags = 0;
12224
12225 if (CHIP_REV_IS_FPGA(bp))
12226 SET_FLAGS(flags, MODE_FPGA);
12227 else if (CHIP_REV_IS_EMUL(bp))
12228 SET_FLAGS(flags, MODE_EMUL);
12229 else
12230 SET_FLAGS(flags, MODE_ASIC);
12231
12232 if (CHIP_MODE_IS_4_PORT(bp))
12233 SET_FLAGS(flags, MODE_PORT4);
12234 else
12235 SET_FLAGS(flags, MODE_PORT2);
12236
12237 if (CHIP_IS_E2(bp))
12238 SET_FLAGS(flags, MODE_E2);
12239 else if (CHIP_IS_E3(bp)) {
12240 SET_FLAGS(flags, MODE_E3);
12241 if (CHIP_REV(bp) == CHIP_REV_Ax)
12242 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 12243 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12244 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 12245 }
12246
12247 if (IS_MF(bp)) {
12248 SET_FLAGS(flags, MODE_MF);
12249 switch (bp->mf_mode) {
12250 case MULTI_FUNCTION_SD:
12251 SET_FLAGS(flags, MODE_MF_SD);
12252 break;
12253 case MULTI_FUNCTION_SI:
12254 SET_FLAGS(flags, MODE_MF_SI);
12255 break;
a3348722
BW		 12256 case MULTI_FUNCTION_AFEX:
12257 SET_FLAGS(flags, MODE_MF_AFEX);
12258 break;
619c5cb6
VZ		 12259 }
12260 } else
12261 SET_FLAGS(flags, MODE_SF);
12262
12263#if defined(__LITTLE_ENDIAN)
12264 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12265#else /*(__BIG_ENDIAN)*/
12266 SET_FLAGS(flags, MODE_BIG_ENDIAN);
12267#endif
12268 INIT_MODE_FLAGS(bp) = flags;
12269}
12270
0329aba1 12271static int bnx2x_init_bp(struct bnx2x *bp)
34f80b04 12272{
f2e0899f 12273 int func;
34f80b04
EG		 12274 int rc;
12275
34f80b04 12276 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 12277 mutex_init(&bp->fw_mb_mutex);
42f8277f 12278 mutex_init(&bp->drv_info_mutex);
c6e36d8c 12279 sema_init(&bp->stats_lock, 1);
42f8277f 12280 bp->drv_info_mng_owner = false;
05cc5a39 12281 INIT_LIST_HEAD(&bp->vlan_reg);
55c11941 12282
1cf167f2 12283 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 12284 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 12285 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
370d4a26 12286 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
1ab4434c
AE		 12287 if (IS_PF(bp)) {
12288 rc = bnx2x_get_hwinfo(bp);
12289 if (rc)
12290 return rc;
12291 } else {
e09b74d0 12292 eth_zero_addr(bp->dev->dev_addr);
1ab4434c 12293 }
34f80b04 12294
619c5cb6
VZ		 12295 bnx2x_set_modes_bitmap(bp);
12296
12297 rc = bnx2x_alloc_mem_bp(bp);
12298 if (rc)
12299 return rc;
523224a3 12300
34f24c7f 12301 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 12302
12303 func = BP_FUNC(bp);
12304
34f80b04 12305 /* need to reset chip if undi was active */
1ab4434c 12306 if (IS_PF(bp) && !BP_NOMCP(bp)) {
452427b0
YM		 12307 /* init fw_seq */
12308 bp->fw_seq =
12309 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12310 DRV_MSG_SEQ_NUMBER_MASK;
12311 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12312
91ebb929
YM		 12313 rc = bnx2x_prev_unload(bp);
12314 if (rc) {
12315 bnx2x_free_mem_bp(bp);
12316 return rc;
12317 }
452427b0
YM		 12318 }
12319
34f80b04 12320 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 12321 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 12322
12323 if (BP_NOMCP(bp) && (func == 0))
51c1a580 12324 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
34f80b04 12325
614c76df 12326 bp->disable_tpa = disable_tpa;
2e98ffc2 12327 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
94d9de3c 12328 /* Reduce memory usage in kdump environment by disabling TPA */
c9931896 12329 bp->disable_tpa |= is_kdump_kernel();
614c76df 12330
7a9b2557 12331 /* Set TPA flags */
614c76df 12332 if (bp->disable_tpa) {
d9b9e860 12333 bp->dev->hw_features &= ~NETIF_F_LRO;
7a9b2557 12334 bp->dev->features &= ~NETIF_F_LRO;
7a9b2557
VZ		 12335 }
12336
a18f5128
EG		 12337 if (CHIP_IS_E1(bp))
12338 bp->dropless_fc = 0;
12339 else
7964211d 12340 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
a18f5128 12341
8d5726c4 12342 bp->mrrs = mrrs;
7a9b2557 12343
2e98ffc2 12344 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
1ab4434c
AE		 12345 if (IS_VF(bp))
12346 bp->rx_ring_size = MAX_RX_AVAIL;
34f80b04 12347
7d323bfd 12348 /* make sure that the numbers are in the right granularity */
523224a3
DK		 12349 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12350 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 12351
fc543637 12352 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
34f80b04
EG		 12353
12354 init_timer(&bp->timer);
12355 bp->timer.expires = jiffies + bp->current_interval;
12356 bp->timer.data = (unsigned long) bp;
12357 bp->timer.function = bnx2x_timer;
12358
0370cf90
BW		 12359 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12360 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12361 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12362 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12363 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12364 bnx2x_dcbx_init_params(bp);
12365 } else {
12366 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12367 }
e4901dde 12368
619c5cb6
VZ		 12369 if (CHIP_IS_E1x(bp))
12370 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12371 else
12372 bp->cnic_base_cl_id = FP_SB_MAX_E2;
619c5cb6 12373
6383c0b3 12374 /* multiple tx priority */
1ab4434c
AE		 12375 if (IS_VF(bp))
12376 bp->max_cos = 1;
12377 else if (CHIP_IS_E1x(bp))
6383c0b3 12378 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
1ab4434c 12379 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
6383c0b3 12380 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
1ab4434c 12381 else if (CHIP_IS_E3B0(bp))
6383c0b3 12382 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
1ab4434c
AE		 12383 else
12384 BNX2X_ERR("unknown chip %x revision %x\n",
12385 CHIP_NUM(bp), CHIP_REV(bp));
12386 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
6383c0b3 12387
55c11941
MS		 12388 /* We need at least one default status block for slow-path events,
12389 * second status block for the L2 queue, and a third status block for
16a5fd92 12390 * CNIC if supported.
55c11941 12391 */
60cad4e6
AE		 12392 if (IS_VF(bp))
12393 bp->min_msix_vec_cnt = 1;
12394 else if (CNIC_SUPPORT(bp))
55c11941 12395 bp->min_msix_vec_cnt = 3;
60cad4e6 12396 else /* PF w/o cnic */
55c11941
MS		 12397 bp->min_msix_vec_cnt = 2;
12398 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12399
5bb680d6
MS		 12400 bp->dump_preset_idx = 1;
12401
eeed018c
MK		 12402 if (CHIP_IS_E3B0(bp))
12403 bp->flags |= PTP_SUPPORTED;
12404
34f80b04 12405 return rc;
a2fbb9ea
ET		 12406}
12407
de0c62db
DK		 12408/****************************************************************************
12409* General service functions
12410****************************************************************************/
a2fbb9ea 12411
619c5cb6
VZ		 12412/*
12413 * net_device service functions
12414 */
12415
bb2a0f7a 12416/* called with rtnl_lock */
a2fbb9ea
ET		 12417static int bnx2x_open(struct net_device *dev)
12418{
12419 struct bnx2x *bp = netdev_priv(dev);
8395be5e 12420 int rc;
a2fbb9ea 12421
1355b704
MY		 12422 bp->stats_init = true;
12423
6eccabb3
EG		 12424 netif_carrier_off(dev);
12425
a2fbb9ea
ET		 12426 bnx2x_set_power_state(bp, PCI_D0);
12427
ad5afc89 12428 /* If parity had happen during the unload, then attentions
c9ee9206
VZ		 12429 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12430 * want the first function loaded on the current engine to
12431 * complete the recovery.
ad5afc89 12432 * Parity recovery is only relevant for PF driver.
c9ee9206 12433 */
ad5afc89 12434 if (IS_PF(bp)) {
1a6974b2
YM		 12435 int other_engine = BP_PATH(bp) ? 0 : 1;
12436 bool other_load_status, load_status;
12437 bool global = false;
12438
ad5afc89
AE		 12439 other_load_status = bnx2x_get_load_status(bp, other_engine);
12440 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12441 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12442 bnx2x_chk_parity_attn(bp, &global, true)) {
12443 do {
12444 /* If there are attentions and they are in a
12445 * global blocks, set the GLOBAL_RESET bit
12446 * regardless whether it will be this function
12447 * that will complete the recovery or not.
12448 */
12449 if (global)
12450 bnx2x_set_reset_global(bp);
72fd0718 12451
ad5afc89
AE		 12452 /* Only the first function on the current
12453 * engine should try to recover in open. In case
12454 * of attentions in global blocks only the first
12455 * in the chip should try to recover.
12456 */
12457 if ((!load_status &&
12458 (!global || !other_load_status)) &&
12459 bnx2x_trylock_leader_lock(bp) &&
12460 !bnx2x_leader_reset(bp)) {
12461 netdev_info(bp->dev,
12462 "Recovered in open\n");
12463 break;
12464 }
72fd0718 12465
ad5afc89
AE		 12466 /* recovery has failed... */
12467 bnx2x_set_power_state(bp, PCI_D3hot);
12468 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 12469
ad5afc89
AE		 12470 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12471 "If you still see this message after a few retries then power cycle is required.\n");
72fd0718 12472
ad5afc89
AE		 12473 return -EAGAIN;
12474 } while (0);
12475 }
12476 }
72fd0718
VZ		 12477
12478 bp->recovery_state = BNX2X_RECOVERY_DONE;
8395be5e
AE		 12479 rc = bnx2x_nic_load(bp, LOAD_OPEN);
12480 if (rc)
12481 return rc;
f34fa14c
RB		 12482
12483#ifdef CONFIG_BNX2X_VXLAN
12484 if (IS_PF(bp))
12485 vxlan_get_rx_port(dev);
12486#endif
12487
9a8130bc 12488 return 0;
a2fbb9ea
ET		 12489}
12490
bb2a0f7a 12491/* called with rtnl_lock */
56ad3152 12492static int bnx2x_close(struct net_device *dev)
a2fbb9ea 12493{
a2fbb9ea
ET		 12494 struct bnx2x *bp = netdev_priv(dev);
12495
12496 /* Unload the driver, release IRQs */
5d07d868 12497 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
c9ee9206 12498
a2fbb9ea
ET		 12499 return 0;
12500}
12501
1191cb83
ED		 12502static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12503 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 12504{
619c5cb6
VZ		 12505 int mc_count = netdev_mc_count(bp->dev);
12506 struct bnx2x_mcast_list_elem *mc_mac =
cd2b0389 12507 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
619c5cb6 12508 struct netdev_hw_addr *ha;
6e30dd4e 12509
619c5cb6
VZ		 12510 if (!mc_mac)
12511 return -ENOMEM;
6e30dd4e 12512
619c5cb6 12513 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 12514
619c5cb6
VZ		 12515 netdev_for_each_mc_addr(ha, bp->dev) {
12516 mc_mac->mac = bnx2x_mc_addr(ha);
12517 list_add_tail(&mc_mac->link, &p->mcast_list);
12518 mc_mac++;
6e30dd4e 12519 }
619c5cb6
VZ		 12520
12521 p->mcast_list_len = mc_count;
12522
12523 return 0;
6e30dd4e
VZ		 12524}
12525
1191cb83 12526static void bnx2x_free_mcast_macs_list(
619c5cb6
VZ		 12527 struct bnx2x_mcast_ramrod_params *p)
12528{
12529 struct bnx2x_mcast_list_elem *mc_mac =
12530 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12531 link);
12532
12533 WARN_ON(!mc_mac);
12534 kfree(mc_mac);
12535}
12536
12537/**
12538 * bnx2x_set_uc_list - configure a new unicast MACs list.
12539 *
12540 * @bp: driver handle
6e30dd4e 12541 *
619c5cb6 12542 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 12543 */
1191cb83 12544static int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 12545{
619c5cb6 12546 int rc;
6e30dd4e 12547 struct net_device *dev = bp->dev;
6e30dd4e 12548 struct netdev_hw_addr *ha;
15192a8c 12549 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
619c5cb6 12550 unsigned long ramrod_flags = 0;
6e30dd4e 12551
619c5cb6
VZ		 12552 /* First schedule a cleanup up of old configuration */
12553 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12554 if (rc < 0) {
12555 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12556 return rc;
12557 }
6e30dd4e
VZ		 12558
12559 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 12560 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12561 BNX2X_UC_LIST_MAC, &ramrod_flags);
7b5342d9
YM		 12562 if (rc == -EEXIST) {
12563 DP(BNX2X_MSG_SP,
12564 "Failed to schedule ADD operations: %d\n", rc);
12565 /* do not treat adding same MAC as error */
12566 rc = 0;
12567
12568 } else if (rc < 0) {
12569
619c5cb6
VZ		 12570 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12571 rc);
12572 return rc;
6e30dd4e
VZ		 12573 }
12574 }
12575
619c5cb6
VZ		 12576 /* Execute the pending commands */
12577 __set_bit(RAMROD_CONT, &ramrod_flags);
12578 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12579 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 12580}
12581
1191cb83 12582static int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 12583{
619c5cb6 12584 struct net_device *dev = bp->dev;
3b603066 12585 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6 12586 int rc = 0;
6e30dd4e 12587
619c5cb6 12588 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 12589
619c5cb6
VZ		 12590 /* first, clear all configured multicast MACs */
12591 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12592 if (rc < 0) {
51c1a580 12593 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
619c5cb6
VZ		 12594 return rc;
12595 }
6e30dd4e 12596
619c5cb6
VZ		 12597 /* then, configure a new MACs list */
12598 if (netdev_mc_count(dev)) {
12599 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12600 if (rc) {
51c1a580
MS		 12601 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12602 rc);
619c5cb6
VZ		 12603 return rc;
12604 }
6e30dd4e 12605
619c5cb6
VZ		 12606 /* Now add the new MACs */
12607 rc = bnx2x_config_mcast(bp, &rparam,
12608 BNX2X_MCAST_CMD_ADD);
12609 if (rc < 0)
51c1a580
MS		 12610 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12611 rc);
6e30dd4e 12612
619c5cb6
VZ		 12613 bnx2x_free_mcast_macs_list(&rparam);
12614 }
6e30dd4e 12615
619c5cb6 12616 return rc;
6e30dd4e
VZ		 12617}
12618
619c5cb6 12619/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
a8f47eb7 12620static void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 12621{
12622 struct bnx2x *bp = netdev_priv(dev);
34f80b04
EG		 12623
12624 if (bp->state != BNX2X_STATE_OPEN) {
12625 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12626 return;
8b09be5f
YM		 12627 } else {
12628 /* Schedule an SP task to handle rest of change */
230bb0f3
YM		 12629 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12630 NETIF_MSG_IFUP);
34f80b04 12631 }
8b09be5f
YM		 12632}
12633
12634void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12635{
12636 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04 12637
619c5cb6 12638 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04 12639
8b09be5f
YM		 12640 netif_addr_lock_bh(bp->dev);
12641
12642 if (bp->dev->flags & IFF_PROMISC) {
34f80b04 12643 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f
YM		 12644 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12645 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12646 CHIP_IS_E1(bp))) {
34f80b04 12647 rx_mode = BNX2X_RX_MODE_ALLMULTI;
8b09be5f 12648 } else {
381ac16b
AE		 12649 if (IS_PF(bp)) {
12650 /* some multicasts */
12651 if (bnx2x_set_mc_list(bp) < 0)
12652 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 12653
8b09be5f
YM		 12654 /* release bh lock, as bnx2x_set_uc_list might sleep */
12655 netif_addr_unlock_bh(bp->dev);
381ac16b
AE		 12656 if (bnx2x_set_uc_list(bp) < 0)
12657 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f 12658 netif_addr_lock_bh(bp->dev);
381ac16b
AE		 12659 } else {
12660 /* configuring mcast to a vf involves sleeping (when we
8b09be5f 12661 * wait for the pf's response).
381ac16b 12662 */
230bb0f3
YM		 12663 bnx2x_schedule_sp_rtnl(bp,
12664 BNX2X_SP_RTNL_VFPF_MCAST, 0);
381ac16b 12665 }
34f80b04
EG		 12666 }
12667
12668 bp->rx_mode = rx_mode;
614c76df 12669 /* handle ISCSI SD mode */
2e98ffc2 12670 if (IS_MF_ISCSI_ONLY(bp))
614c76df 12671 bp->rx_mode = BNX2X_RX_MODE_NONE;
619c5cb6
VZ		 12672
12673 /* Schedule the rx_mode command */
12674 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12675 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8b09be5f 12676 netif_addr_unlock_bh(bp->dev);
619c5cb6
VZ		 12677 return;
12678 }
12679
381ac16b
AE		 12680 if (IS_PF(bp)) {
12681 bnx2x_set_storm_rx_mode(bp);
8b09be5f 12682 netif_addr_unlock_bh(bp->dev);
381ac16b 12683 } else {
8b09be5f
YM		 12684 /* VF will need to request the PF to make this change, and so
12685 * the VF needs to release the bottom-half lock prior to the
12686 * request (as it will likely require sleep on the VF side)
381ac16b 12687 */
8b09be5f
YM		 12688 netif_addr_unlock_bh(bp->dev);
12689 bnx2x_vfpf_storm_rx_mode(bp);
381ac16b 12690 }
34f80b04
EG		 12691}
12692
c18487ee 12693/* called with rtnl_lock */
01cd4528
EG		 12694static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12695 int devad, u16 addr)
a2fbb9ea 12696{
01cd4528
EG		 12697 struct bnx2x *bp = netdev_priv(netdev);
12698 u16 value;
12699 int rc;
a2fbb9ea 12700
01cd4528
EG		 12701 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12702 prtad, devad, addr);
a2fbb9ea 12703
01cd4528
EG		 12704 /* The HW expects different devad if CL22 is used */
12705 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 12706
01cd4528 12707 bnx2x_acquire_phy_lock(bp);
e10bc84d 12708 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 12709 bnx2x_release_phy_lock(bp);
12710 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 12711
01cd4528
EG		 12712 if (!rc)
12713 rc = value;
12714 return rc;
12715}
a2fbb9ea 12716
01cd4528
EG		 12717/* called with rtnl_lock */
12718static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12719 u16 addr, u16 value)
12720{
12721 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 12722 int rc;
12723
51c1a580
MS		 12724 DP(NETIF_MSG_LINK,
12725 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12726 prtad, devad, addr, value);
01cd4528 12727
01cd4528
EG		 12728 /* The HW expects different devad if CL22 is used */
12729 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 12730
01cd4528 12731 bnx2x_acquire_phy_lock(bp);
e10bc84d 12732 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 12733 bnx2x_release_phy_lock(bp);
12734 return rc;
12735}
c18487ee 12736
01cd4528
EG		 12737/* called with rtnl_lock */
12738static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12739{
12740 struct bnx2x *bp = netdev_priv(dev);
12741 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 12742
01cd4528
EG		 12743 if (!netif_running(dev))
12744 return -EAGAIN;
12745
eeed018c
MK		 12746 switch (cmd) {
12747 case SIOCSHWTSTAMP:
12748 return bnx2x_hwtstamp_ioctl(bp, ifr);
12749 default:
12750 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12751 mdio->phy_id, mdio->reg_num, mdio->val_in);
12752 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12753 }
a2fbb9ea
ET		 12754}
12755
257ddbda 12756#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 12757static void poll_bnx2x(struct net_device *dev)
12758{
12759 struct bnx2x *bp = netdev_priv(dev);
14a15d61 12760 int i;
a2fbb9ea 12761
14a15d61
MS		 12762 for_each_eth_queue(bp, i) {
12763 struct bnx2x_fastpath *fp = &bp->fp[i];
12764 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12765 }
a2fbb9ea
ET		 12766}
12767#endif
12768
614c76df
DK		 12769static int bnx2x_validate_addr(struct net_device *dev)
12770{
12771 struct bnx2x *bp = netdev_priv(dev);
12772
e09b74d0
AE		 12773 /* query the bulletin board for mac address configured by the PF */
12774 if (IS_VF(bp))
12775 bnx2x_sample_bulletin(bp);
12776
2e98ffc2 12777 if (!is_valid_ether_addr(dev->dev_addr)) {
51c1a580 12778 BNX2X_ERR("Non-valid Ethernet address\n");
614c76df 12779 return -EADDRNOTAVAIL;
51c1a580 12780 }
614c76df
DK		 12781 return 0;
12782}
12783
3d7d562c 12784static int bnx2x_get_phys_port_id(struct net_device *netdev,
02637fce 12785 struct netdev_phys_item_id *ppid)
3d7d562c
YM		 12786{
12787 struct bnx2x *bp = netdev_priv(netdev);
12788
12789 if (!(bp->flags & HAS_PHYS_PORT_ID))
12790 return -EOPNOTSUPP;
12791
12792 ppid->id_len = sizeof(bp->phys_port_id);
12793 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12794
12795 return 0;
12796}
12797
5f35227e
JG		 12798static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12799 struct net_device *dev,
12800 netdev_features_t features)
51de7bb9 12801{
8cb65d00 12802 features = vlan_features_check(skb, features);
5f35227e 12803 return vxlan_features_check(skb, features);
51de7bb9
JS		 12804}
12805
05cc5a39
YM		 12806static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add)
12807{
12808 int rc;
12809
12810 if (IS_PF(bp)) {
12811 unsigned long ramrod_flags = 0;
12812
12813 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12814 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj,
12815 add, &ramrod_flags);
12816 } else {
12817 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add);
12818 }
12819
12820 return rc;
12821}
12822
12823int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp)
12824{
12825 struct bnx2x_vlan_entry *vlan;
12826 int rc = 0;
12827
12828 if (!bp->vlan_cnt) {
12829 DP(NETIF_MSG_IFUP, "No need to re-configure vlan filters\n");
12830 return 0;
12831 }
12832
12833 list_for_each_entry(vlan, &bp->vlan_reg, link) {
12834 /* Prepare for cleanup in case of errors */
12835 if (rc) {
12836 vlan->hw = false;
12837 continue;
12838 }
12839
12840 if (!vlan->hw)
12841 continue;
12842
12843 DP(NETIF_MSG_IFUP, "Re-configuring vlan 0x%04x\n", vlan->vid);
12844
12845 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
12846 if (rc) {
12847 BNX2X_ERR("Unable to configure VLAN %d\n", vlan->vid);
12848 vlan->hw = false;
12849 rc = -EINVAL;
12850 continue;
12851 }
12852 }
12853
12854 return rc;
12855}
12856
12857static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
12858{
12859 struct bnx2x *bp = netdev_priv(dev);
12860 struct bnx2x_vlan_entry *vlan;
12861 bool hw = false;
12862 int rc = 0;
12863
12864 if (!netif_running(bp->dev)) {
12865 DP(NETIF_MSG_IFUP,
12866 "Ignoring VLAN configuration the interface is down\n");
12867 return -EFAULT;
12868 }
12869
12870 DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid);
12871
12872 vlan = kmalloc(sizeof(*vlan), GFP_KERNEL);
12873 if (!vlan)
12874 return -ENOMEM;
12875
12876 bp->vlan_cnt++;
12877 if (bp->vlan_cnt > bp->vlan_credit && !bp->accept_any_vlan) {
12878 DP(NETIF_MSG_IFUP, "Accept all VLAN raised\n");
12879 bp->accept_any_vlan = true;
12880 if (IS_PF(bp))
12881 bnx2x_set_rx_mode_inner(bp);
12882 else
12883 bnx2x_vfpf_storm_rx_mode(bp);
12884 } else if (bp->vlan_cnt <= bp->vlan_credit) {
12885 rc = __bnx2x_vlan_configure_vid(bp, vid, true);
12886 hw = true;
12887 }
12888
12889 vlan->vid = vid;
12890 vlan->hw = hw;
12891
12892 if (!rc) {
12893 list_add(&vlan->link, &bp->vlan_reg);
12894 } else {
12895 bp->vlan_cnt--;
12896 kfree(vlan);
12897 }
12898
12899 DP(NETIF_MSG_IFUP, "Adding VLAN result %d\n", rc);
12900
12901 return rc;
12902}
12903
12904static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
12905{
12906 struct bnx2x *bp = netdev_priv(dev);
12907 struct bnx2x_vlan_entry *vlan;
12908 int rc = 0;
12909
12910 if (!netif_running(bp->dev)) {
12911 DP(NETIF_MSG_IFUP,
12912 "Ignoring VLAN configuration the interface is down\n");
12913 return -EFAULT;
12914 }
12915
12916 DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid);
12917
12918 if (!bp->vlan_cnt) {
12919 BNX2X_ERR("Unable to kill VLAN %d\n", vid);
12920 return -EINVAL;
12921 }
12922
12923 list_for_each_entry(vlan, &bp->vlan_reg, link)
12924 if (vlan->vid == vid)
12925 break;
12926
12927 if (vlan->vid != vid) {
12928 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid);
12929 return -EINVAL;
12930 }
12931
12932 if (vlan->hw)
12933 rc = __bnx2x_vlan_configure_vid(bp, vid, false);
12934
12935 list_del(&vlan->link);
12936 kfree(vlan);
12937
12938 bp->vlan_cnt--;
12939
12940 if (bp->vlan_cnt <= bp->vlan_credit && bp->accept_any_vlan) {
12941 /* Configure all non-configured entries */
12942 list_for_each_entry(vlan, &bp->vlan_reg, link) {
12943 if (vlan->hw)
12944 continue;
12945
12946 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
12947 if (rc) {
12948 BNX2X_ERR("Unable to config VLAN %d\n",
12949 vlan->vid);
12950 continue;
12951 }
12952 DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n",
12953 vlan->vid);
12954 vlan->hw = true;
12955 }
12956 DP(NETIF_MSG_IFUP, "Accept all VLAN Removed\n");
12957 bp->accept_any_vlan = false;
12958 if (IS_PF(bp))
12959 bnx2x_set_rx_mode_inner(bp);
12960 else
12961 bnx2x_vfpf_storm_rx_mode(bp);
12962 }
12963
12964 DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc);
12965
12966 return rc;
12967}
12968
c64213cd
SH		 12969static const struct net_device_ops bnx2x_netdev_ops = {
12970 .ndo_open = bnx2x_open,
12971 .ndo_stop = bnx2x_close,
12972 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 12973 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 12974 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 12975 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 12976 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 12977 .ndo_do_ioctl = bnx2x_ioctl,
12978 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 12979 .ndo_fix_features = bnx2x_fix_features,
12980 .ndo_set_features = bnx2x_set_features,
c64213cd 12981 .ndo_tx_timeout = bnx2x_tx_timeout,
05cc5a39
YM		 12982 .ndo_vlan_rx_add_vid = bnx2x_vlan_rx_add_vid,
12983 .ndo_vlan_rx_kill_vid = bnx2x_vlan_rx_kill_vid,
257ddbda 12984#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 12985 .ndo_poll_controller = poll_bnx2x,
12986#endif
6383c0b3 12987 .ndo_setup_tc = bnx2x_setup_tc,
6411280a 12988#ifdef CONFIG_BNX2X_SRIOV
abc5a021 12989 .ndo_set_vf_mac = bnx2x_set_vf_mac,
3cdeec22 12990 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
3ec9f9ca 12991 .ndo_get_vf_config = bnx2x_get_vf_config,
6411280a 12992#endif
55c11941 12993#ifdef NETDEV_FCOE_WWNN
bf61ee14
VZ		 12994 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
12995#endif
8f20aa57 12996
e0d1095a 12997#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 12998 .ndo_busy_poll = bnx2x_low_latency_recv,
8f20aa57 12999#endif
3d7d562c 13000 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
6495d15a 13001 .ndo_set_vf_link_state = bnx2x_set_vf_link_state,
5f35227e 13002 .ndo_features_check = bnx2x_features_check,
f34fa14c
RB		 13003#ifdef CONFIG_BNX2X_VXLAN
13004 .ndo_add_vxlan_port = bnx2x_add_vxlan_port,
13005 .ndo_del_vxlan_port = bnx2x_del_vxlan_port,
13006#endif
c64213cd
SH		 13007};
13008
1191cb83 13009static int bnx2x_set_coherency_mask(struct bnx2x *bp)
619c5cb6
VZ		 13010{
13011 struct device *dev = &bp->pdev->dev;
13012
8ceafbfa
LT		 13013 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
13014 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
619c5cb6
VZ		 13015 dev_err(dev, "System does not support DMA, aborting\n");
13016 return -EIO;
13017 }
13018
13019 return 0;
13020}
13021
33d8e6a5
YM		 13022static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
13023{
13024 if (bp->flags & AER_ENABLED) {
13025 pci_disable_pcie_error_reporting(bp->pdev);
13026 bp->flags &= ~AER_ENABLED;
13027 }
13028}
13029
1ab4434c
AE		 13030static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
13031 struct net_device *dev, unsigned long board_type)
a2fbb9ea 13032{
a2fbb9ea 13033 int rc;
c22610d0 13034 u32 pci_cfg_dword;
65087cfe
AE		 13035 bool chip_is_e1x = (board_type == BCM57710 ||
13036 board_type == BCM57711 ||
13037 board_type == BCM57711E);
a2fbb9ea
ET		 13038
13039 SET_NETDEV_DEV(dev, &pdev->dev);
a2fbb9ea 13040
34f80b04
EG		 13041 bp->dev = dev;
13042 bp->pdev = pdev;
a2fbb9ea
ET		 13043
13044 rc = pci_enable_device(pdev);
13045 if (rc) {
cdaa7cb8
VZ		 13046 dev_err(&bp->pdev->dev,
13047 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 13048 goto err_out;
13049 }
13050
13051 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 13052 dev_err(&bp->pdev->dev,
13053 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 13054 rc = -ENODEV;
13055 goto err_out_disable;
13056 }
13057
1ab4434c
AE		 13058 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13059 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
a2fbb9ea
ET		 13060 rc = -ENODEV;
13061 goto err_out_disable;
13062 }
13063
092a5fc9
YR		 13064 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
13065 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
13066 PCICFG_REVESION_ID_ERROR_VAL) {
13067 pr_err("PCI device error, probably due to fan failure, aborting\n");
13068 rc = -ENODEV;
13069 goto err_out_disable;
13070 }
13071
34f80b04
EG		 13072 if (atomic_read(&pdev->enable_cnt) == 1) {
13073 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
13074 if (rc) {
cdaa7cb8
VZ		 13075 dev_err(&bp->pdev->dev,
13076 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 13077 goto err_out_disable;
13078 }
a2fbb9ea 13079
34f80b04
EG		 13080 pci_set_master(pdev);
13081 pci_save_state(pdev);
13082 }
a2fbb9ea 13083
1ab4434c 13084 if (IS_PF(bp)) {
29ed74c3 13085 if (!pdev->pm_cap) {
1ab4434c
AE		 13086 dev_err(&bp->pdev->dev,
13087 "Cannot find power management capability, aborting\n");
13088 rc = -EIO;
13089 goto err_out_release;
13090 }
a2fbb9ea
ET		 13091 }
13092
77c98e6a 13093 if (!pci_is_pcie(pdev)) {
51c1a580 13094 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 13095 rc = -EIO;
13096 goto err_out_release;
13097 }
13098
619c5cb6
VZ		 13099 rc = bnx2x_set_coherency_mask(bp);
13100 if (rc)
a2fbb9ea 13101 goto err_out_release;
a2fbb9ea 13102
34f80b04
EG		 13103 dev->mem_start = pci_resource_start(pdev, 0);
13104 dev->base_addr = dev->mem_start;
13105 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 13106
13107 dev->irq = pdev->irq;
13108
275f165f 13109 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 13110 if (!bp->regview) {
cdaa7cb8
VZ		 13111 dev_err(&bp->pdev->dev,
13112 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 13113 rc = -ENOMEM;
13114 goto err_out_release;
13115 }
13116
c22610d0
AE		 13117 /* In E1/E1H use pci device function given by kernel.
13118 * In E2/E3 read physical function from ME register since these chips
13119 * support Physical Device Assignment where kernel BDF maybe arbitrary
13120 * (depending on hypervisor).
13121 */
2de67439 13122 if (chip_is_e1x) {
c22610d0 13123 bp->pf_num = PCI_FUNC(pdev->devfn);
2de67439
YM		 13124 } else {
13125 /* chip is E2/3*/
c22610d0
AE		 13126 pci_read_config_dword(bp->pdev,
13127 PCICFG_ME_REGISTER, &pci_cfg_dword);
13128 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
2de67439 13129 ME_REG_ABS_PF_NUM_SHIFT);
c22610d0 13130 }
51c1a580 13131 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
c22610d0 13132
34f80b04
EG		 13133 /* clean indirect addresses */
13134 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
13135 PCICFG_VENDOR_ID_OFFSET);
33d8e6a5 13136
da293700
BK		 13137 /* Set PCIe reset type to fundamental for EEH recovery */
13138 pdev->needs_freset = 1;
13139
33d8e6a5
YM		 13140 /* AER (Advanced Error reporting) configuration */
13141 rc = pci_enable_pcie_error_reporting(pdev);
13142 if (!rc)
13143 bp->flags |= AER_ENABLED;
13144 else
13145 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
13146
a5c53dbc
DK		 13147 /*
13148 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 13149 * is not used by the driver.
13150 */
1ab4434c
AE		 13151 if (IS_PF(bp)) {
13152 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
13153 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
13154 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
13155 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
13156
13157 if (chip_is_e1x) {
13158 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
13159 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
13160 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
13161 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
13162 }
a5c53dbc 13163
1ab4434c
AE		 13164 /* Enable internal target-read (in case we are probed after PF
13165 * FLR). Must be done prior to any BAR read access. Only for
13166 * 57712 and up
13167 */
13168 if (!chip_is_e1x)
13169 REG_WR(bp,
13170 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
a5c53dbc 13171 }
a2fbb9ea 13172
34f80b04 13173 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 13174
c64213cd 13175 dev->netdev_ops = &bnx2x_netdev_ops;
005a07ba 13176 bnx2x_set_ethtool_ops(bp, dev);
5316bc0b 13177
01789349
JP		 13178 dev->priv_flags |= IFF_UNICAST_FLT;
13179
66371c44 13180 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
621b4d66
DK		 13181 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13182 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
f646968f 13183 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
a8e0c246 13184 if (!chip_is_e1x) {
117401ee 13185 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
2e3bd6a4 13186 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
a848ade4
DK		 13187 dev->hw_enc_features =
13188 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13189 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
117401ee 13190 NETIF_F_GSO_IPIP |
2e3bd6a4 13191 NETIF_F_GSO_SIT |
65bc0cfe 13192 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
a848ade4 13193 }
66371c44
MM		 13194
13195 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13196 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
13197
05cc5a39
YM		 13198 /* VF with OLD Hypervisor or old PF do not support filtering */
13199 if (IS_PF(bp)) {
13200 if (CHIP_IS_E1x(bp))
13201 bp->accept_any_vlan = true;
13202 else
13203 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
ce7fa78c 13204#ifdef CONFIG_BNX2X_SRIOV
05cc5a39
YM		 13205 } else if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
13206 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
ce7fa78c 13207#endif
05cc5a39
YM		 13208 }
13209
f646968f 13210 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
edd31476 13211 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 13212
538dd2e3
MB		 13213 /* Add Loopback capability to the device */
13214 dev->hw_features |= NETIF_F_LOOPBACK;
13215
98507672 13216#ifdef BCM_DCBNL
785b9b1a
SR		 13217 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
13218#endif
13219
01cd4528
EG		 13220 /* get_port_hwinfo() will set prtad and mmds properly */
13221 bp->mdio.prtad = MDIO_PRTAD_NONE;
13222 bp->mdio.mmds = 0;
13223 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
13224 bp->mdio.dev = dev;
13225 bp->mdio.mdio_read = bnx2x_mdio_read;
13226 bp->mdio.mdio_write = bnx2x_mdio_write;
13227
a2fbb9ea
ET		 13228 return 0;
13229
a2fbb9ea 13230err_out_release:
34f80b04
EG		 13231 if (atomic_read(&pdev->enable_cnt) == 1)
13232 pci_release_regions(pdev);
a2fbb9ea
ET		 13233
13234err_out_disable:
13235 pci_disable_device(pdev);
a2fbb9ea
ET		 13236
13237err_out:
13238 return rc;
13239}
13240
6891dd25 13241static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 13242{
37f9ce62 13243 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 13244 struct bnx2x_fw_file_hdr *fw_hdr;
13245 struct bnx2x_fw_file_section *sections;
94a78b79 13246 u32 offset, len, num_ops;
86564c3f 13247 __be16 *ops_offsets;
94a78b79 13248 int i;
37f9ce62 13249 const u8 *fw_ver;
94a78b79 13250
51c1a580
MS		 13251 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
13252 BNX2X_ERR("Wrong FW size\n");
94a78b79 13253 return -EINVAL;
51c1a580 13254 }
94a78b79
VZ		 13255
13256 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
13257 sections = (struct bnx2x_fw_file_section *)fw_hdr;
13258
13259 /* Make sure none of the offsets and sizes make us read beyond
13260 * the end of the firmware data */
13261 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
13262 offset = be32_to_cpu(sections[i].offset);
13263 len = be32_to_cpu(sections[i].len);
13264 if (offset + len > firmware->size) {
51c1a580 13265 BNX2X_ERR("Section %d length is out of bounds\n", i);
94a78b79
VZ		 13266 return -EINVAL;
13267 }
13268 }
13269
13270 /* Likewise for the init_ops offsets */
13271 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
86564c3f 13272 ops_offsets = (__force __be16 *)(firmware->data + offset);
94a78b79
VZ		 13273 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
13274
13275 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
13276 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
51c1a580 13277 BNX2X_ERR("Section offset %d is out of bounds\n", i);
94a78b79
VZ		 13278 return -EINVAL;
13279 }
13280 }
13281
13282 /* Check FW version */
13283 offset = be32_to_cpu(fw_hdr->fw_version.offset);
13284 fw_ver = firmware->data + offset;
13285 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
13286 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
13287 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
13288 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
51c1a580
MS		 13289 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
13290 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
13291 BCM_5710_FW_MAJOR_VERSION,
94a78b79
VZ		 13292 BCM_5710_FW_MINOR_VERSION,
13293 BCM_5710_FW_REVISION_VERSION,
13294 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 13295 return -EINVAL;
94a78b79
VZ		 13296 }
13297
13298 return 0;
13299}
13300
1191cb83 13301static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 13302{
ab6ad5a4
EG		 13303 const __be32 *source = (const __be32 *)_source;
13304 u32 *target = (u32 *)_target;
94a78b79 13305 u32 i;
94a78b79
VZ		 13306
13307 for (i = 0; i < n/4; i++)
13308 target[i] = be32_to_cpu(source[i]);
13309}
13310
13311/*
13312 Ops array is stored in the following format:
13313 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13314 */
1191cb83 13315static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 13316{
ab6ad5a4
EG		 13317 const __be32 *source = (const __be32 *)_source;
13318 struct raw_op *target = (struct raw_op *)_target;
94a78b79 13319 u32 i, j, tmp;
94a78b79 13320
ab6ad5a4 13321 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 13322 tmp = be32_to_cpu(source[j]);
13323 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 13324 target[i].offset = tmp & 0xffffff;
13325 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 13326 }
13327}
ab6ad5a4 13328
1aa8b471 13329/* IRO array is stored in the following format:
523224a3
DK		 13330 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13331 */
1191cb83 13332static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
523224a3
DK		 13333{
13334 const __be32 *source = (const __be32 *)_source;
13335 struct iro *target = (struct iro *)_target;
13336 u32 i, j, tmp;
13337
13338 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
13339 target[i].base = be32_to_cpu(source[j]);
13340 j++;
13341 tmp = be32_to_cpu(source[j]);
13342 target[i].m1 = (tmp >> 16) & 0xffff;
13343 target[i].m2 = tmp & 0xffff;
13344 j++;
13345 tmp = be32_to_cpu(source[j]);
13346 target[i].m3 = (tmp >> 16) & 0xffff;
13347 target[i].size = tmp & 0xffff;
13348 j++;
13349 }
13350}
13351
1191cb83 13352static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 13353{
ab6ad5a4
EG		 13354 const __be16 *source = (const __be16 *)_source;
13355 u16 *target = (u16 *)_target;
94a78b79 13356 u32 i;
94a78b79
VZ		 13357
13358 for (i = 0; i < n/2; i++)
13359 target[i] = be16_to_cpu(source[i]);
13360}
13361
7995c64e
JP		 13362#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
13363do { \
13364 u32 len = be32_to_cpu(fw_hdr->arr.len); \
13365 bp->arr = kmalloc(len, GFP_KERNEL); \
e404decb 13366 if (!bp->arr) \
7995c64e 13367 goto lbl; \
7995c64e
JP		 13368 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
13369 (u8 *)bp->arr, len); \
13370} while (0)
94a78b79 13371
3b603066 13372static int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 13373{
c0ea452e 13374 const char *fw_file_name;
94a78b79 13375 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 13376 int rc;
94a78b79 13377
c0ea452e
MS		 13378 if (bp->firmware)
13379 return 0;
94a78b79 13380
c0ea452e
MS		 13381 if (CHIP_IS_E1(bp))
13382 fw_file_name = FW_FILE_NAME_E1;
13383 else if (CHIP_IS_E1H(bp))
13384 fw_file_name = FW_FILE_NAME_E1H;
13385 else if (!CHIP_IS_E1x(bp))
13386 fw_file_name = FW_FILE_NAME_E2;
13387 else {
13388 BNX2X_ERR("Unsupported chip revision\n");
13389 return -EINVAL;
13390 }
13391 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 13392
c0ea452e
MS		 13393 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13394 if (rc) {
13395 BNX2X_ERR("Can't load firmware file %s\n",
13396 fw_file_name);
13397 goto request_firmware_exit;
13398 }
eb2afd4a 13399
c0ea452e
MS		 13400 rc = bnx2x_check_firmware(bp);
13401 if (rc) {
13402 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13403 goto request_firmware_exit;
94a78b79
VZ		 13404 }
13405
13406 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13407
13408 /* Initialize the pointers to the init arrays */
13409 /* Blob */
13410 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13411
13412 /* Opcodes */
13413 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13414
13415 /* Offsets */
ab6ad5a4
EG		 13416 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13417 be16_to_cpu_n);
94a78b79
VZ		 13418
13419 /* STORMs firmware */
573f2035
EG		 13420 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13421 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13422 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
13423 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13424 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13425 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13426 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
13427 be32_to_cpu(fw_hdr->usem_pram_data.offset);
13428 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13429 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13430 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
13431 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13432 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13433 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13434 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
13435 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 13436 /* IRO */
13437 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 13438
13439 return 0;
ab6ad5a4 13440
523224a3
DK		 13441iro_alloc_err:
13442 kfree(bp->init_ops_offsets);
94a78b79
VZ		 13443init_offsets_alloc_err:
13444 kfree(bp->init_ops);
13445init_ops_alloc_err:
13446 kfree(bp->init_data);
13447request_firmware_exit:
13448 release_firmware(bp->firmware);
127d0a19 13449 bp->firmware = NULL;
94a78b79
VZ		 13450
13451 return rc;
13452}
13453
619c5cb6
VZ		 13454static void bnx2x_release_firmware(struct bnx2x *bp)
13455{
13456 kfree(bp->init_ops_offsets);
13457 kfree(bp->init_ops);
13458 kfree(bp->init_data);
13459 release_firmware(bp->firmware);
eb2afd4a 13460 bp->firmware = NULL;
619c5cb6
VZ		 13461}
13462
619c5cb6
VZ		 13463static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13464 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13465 .init_hw_cmn = bnx2x_init_hw_common,
13466 .init_hw_port = bnx2x_init_hw_port,
13467 .init_hw_func = bnx2x_init_hw_func,
13468
13469 .reset_hw_cmn = bnx2x_reset_common,
13470 .reset_hw_port = bnx2x_reset_port,
13471 .reset_hw_func = bnx2x_reset_func,
13472
13473 .gunzip_init = bnx2x_gunzip_init,
13474 .gunzip_end = bnx2x_gunzip_end,
13475
13476 .init_fw = bnx2x_init_firmware,
13477 .release_fw = bnx2x_release_firmware,
13478};
13479
13480void bnx2x__init_func_obj(struct bnx2x *bp)
13481{
13482 /* Prepare DMAE related driver resources */
13483 bnx2x_setup_dmae(bp);
13484
13485 bnx2x_init_func_obj(bp, &bp->func_obj,
13486 bnx2x_sp(bp, func_rdata),
13487 bnx2x_sp_mapping(bp, func_rdata),
a3348722
BW		 13488 bnx2x_sp(bp, func_afex_rdata),
13489 bnx2x_sp_mapping(bp, func_afex_rdata),
619c5cb6
VZ		 13490 &bnx2x_func_sp_drv);
13491}
13492
13493/* must be called after sriov-enable */
1191cb83 13494static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 13495{
37ae41a9 13496 int cid_count = BNX2X_L2_MAX_CID(bp);
94a78b79 13497
290ca2bb
AE		 13498 if (IS_SRIOV(bp))
13499 cid_count += BNX2X_VF_CIDS;
13500
55c11941
MS		 13501 if (CNIC_SUPPORT(bp))
13502 cid_count += CNIC_CID_MAX;
290ca2bb 13503
523224a3
DK		 13504 return roundup(cid_count, QM_CID_ROUND);
13505}
f85582f8 13506
619c5cb6 13507/**
6383c0b3 13508 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 13509 *
13510 * @dev: pci device
13511 *
13512 */
60cad4e6 13513static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
619c5cb6 13514{
ae2104be 13515 int index;
1ab4434c 13516 u16 control = 0;
619c5cb6 13517
6383c0b3
AE		 13518 /*
13519 * If MSI-X is not supported - return number of SBs needed to support
13520 * one fast path queue: one FP queue + SB for CNIC
13521 */
ae2104be 13522 if (!pdev->msix_cap) {
1ab4434c 13523 dev_info(&pdev->dev, "no msix capability found\n");
55c11941 13524 return 1 + cnic_cnt;
1ab4434c
AE		 13525 }
13526 dev_info(&pdev->dev, "msix capability found\n");
619c5cb6 13527
6383c0b3
AE		 13528 /*
13529 * The value in the PCI configuration space is the index of the last
13530 * entry, namely one less than the actual size of the table, which is
13531 * exactly what we want to return from this function: number of all SBs
13532 * without the default SB.
1ab4434c 13533 * For VFs there is no default SB, then we return (index+1).
6383c0b3 13534 */
73413ffa 13535 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
619c5cb6 13536
1ab4434c 13537 index = control & PCI_MSIX_FLAGS_QSIZE;
4bd9b0ff 13538
60cad4e6 13539 return index;
1ab4434c 13540}
523224a3 13541
1ab4434c
AE		 13542static int set_max_cos_est(int chip_id)
13543{
13544 switch (chip_id) {
f2e0899f
DK		 13545 case BCM57710:
13546 case BCM57711:
13547 case BCM57711E:
1ab4434c 13548 return BNX2X_MULTI_TX_COS_E1X;
f2e0899f 13549 case BCM57712:
619c5cb6 13550 case BCM57712_MF:
1ab4434c 13551 return BNX2X_MULTI_TX_COS_E2_E3A0;
619c5cb6
VZ		 13552 case BCM57800:
13553 case BCM57800_MF:
13554 case BCM57810:
13555 case BCM57810_MF:
c3def943
YM		 13556 case BCM57840_4_10:
13557 case BCM57840_2_20:
1ab4434c 13558 case BCM57840_O:
c3def943 13559 case BCM57840_MFO:
619c5cb6 13560 case BCM57840_MF:
7e8e02df
BW		 13561 case BCM57811:
13562 case BCM57811_MF:
1ab4434c 13563 return BNX2X_MULTI_TX_COS_E3B0;
b1239723
YM		 13564 case BCM57712_VF:
13565 case BCM57800_VF:
13566 case BCM57810_VF:
13567 case BCM57840_VF:
13568 case BCM57811_VF:
1ab4434c 13569 return 1;
f2e0899f 13570 default:
1ab4434c 13571 pr_err("Unknown board_type (%d), aborting\n", chip_id);
870634b0 13572 return -ENODEV;
f2e0899f 13573 }
1ab4434c 13574}
f2e0899f 13575
1ab4434c
AE		 13576static int set_is_vf(int chip_id)
13577{
13578 switch (chip_id) {
13579 case BCM57712_VF:
13580 case BCM57800_VF:
13581 case BCM57810_VF:
13582 case BCM57840_VF:
13583 case BCM57811_VF:
13584 return true;
13585 default:
13586 return false;
13587 }
13588}
6383c0b3 13589
eeed018c
MK		 13590/* nig_tsgen registers relative address */
13591#define tsgen_ctrl 0x0
13592#define tsgen_freecount 0x10
13593#define tsgen_synctime_t0 0x20
13594#define tsgen_offset_t0 0x28
13595#define tsgen_drift_t0 0x30
13596#define tsgen_synctime_t1 0x58
13597#define tsgen_offset_t1 0x60
13598#define tsgen_drift_t1 0x68
13599
13600/* FW workaround for setting drift */
13601static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13602 int best_val, int best_period)
13603{
13604 struct bnx2x_func_state_params func_params = {NULL};
13605 struct bnx2x_func_set_timesync_params *set_timesync_params =
13606 &func_params.params.set_timesync;
13607
13608 /* Prepare parameters for function state transitions */
13609 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13610 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13611
13612 func_params.f_obj = &bp->func_obj;
13613 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13614
13615 /* Function parameters */
13616 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13617 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13618 set_timesync_params->add_sub_drift_adjust_value =
13619 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13620 set_timesync_params->drift_adjust_value = best_val;
13621 set_timesync_params->drift_adjust_period = best_period;
13622
13623 return bnx2x_func_state_change(bp, &func_params);
13624}
13625
13626static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13627{
13628 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13629 int rc;
13630 int drift_dir = 1;
13631 int val, period, period1, period2, dif, dif1, dif2;
13632 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13633
13634 DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13635
13636 if (!netif_running(bp->dev)) {
13637 DP(BNX2X_MSG_PTP,
13638 "PTP adjfreq called while the interface is down\n");
13639 return -EFAULT;
13640 }
13641
13642 if (ppb < 0) {
13643 ppb = -ppb;
13644 drift_dir = 0;
13645 }
13646
13647 if (ppb == 0) {
13648 best_val = 1;
13649 best_period = 0x1FFFFFF;
13650 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13651 best_val = 31;
13652 best_period = 1;
13653 } else {
13654 /* Changed not to allow val = 8, 16, 24 as these values
13655 * are not supported in workaround.
13656 */
13657 for (val = 0; val <= 31; val++) {
13658 if ((val & 0x7) == 0)
13659 continue;
13660 period1 = val * 1000000 / ppb;
13661 period2 = period1 + 1;
13662 if (period1 != 0)
13663 dif1 = ppb - (val * 1000000 / period1);
13664 else
13665 dif1 = BNX2X_MAX_PHC_DRIFT;
13666 if (dif1 < 0)
13667 dif1 = -dif1;
13668 dif2 = ppb - (val * 1000000 / period2);
13669 if (dif2 < 0)
13670 dif2 = -dif2;
13671 dif = (dif1 < dif2) ? dif1 : dif2;
13672 period = (dif1 < dif2) ? period1 : period2;
13673 if (dif < best_dif) {
13674 best_dif = dif;
13675 best_val = val;
13676 best_period = period;
13677 }
13678 }
13679 }
13680
13681 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13682 best_period);
13683 if (rc) {
13684 BNX2X_ERR("Failed to set drift\n");
13685 return -EFAULT;
13686 }
13687
bf27c353 13688 DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
eeed018c
MK		 13689 best_period);
13690
13691 return 0;
13692}
13693
13694static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13695{
13696 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
eeed018c
MK		 13697
13698 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13699
2e5601f9 13700 timecounter_adjtime(&bp->timecounter, delta);
eeed018c
MK		 13701
13702 return 0;
13703}
13704
5d45186b 13705static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
eeed018c
MK		 13706{
13707 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13708 u64 ns;
eeed018c
MK		 13709
13710 ns = timecounter_read(&bp->timecounter);
13711
13712 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13713
f7dcdefe 13714 *ts = ns_to_timespec64(ns);
eeed018c
MK		 13715
13716 return 0;
13717}
13718
13719static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
5d45186b 13720 const struct timespec64 *ts)
eeed018c
MK		 13721{
13722 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13723 u64 ns;
13724
f7dcdefe 13725 ns = timespec64_to_ns(ts);
eeed018c
MK		 13726
13727 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13728
13729 /* Re-init the timecounter */
13730 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13731
13732 return 0;
13733}
13734
13735/* Enable (or disable) ancillary features of the phc subsystem */
13736static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13737 struct ptp_clock_request *rq, int on)
13738{
13739 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13740
13741 BNX2X_ERR("PHC ancillary features are not supported\n");
13742 return -ENOTSUPP;
13743}
13744
1444c301 13745static void bnx2x_register_phc(struct bnx2x *bp)
eeed018c
MK		 13746{
13747 /* Fill the ptp_clock_info struct and register PTP clock*/
13748 bp->ptp_clock_info.owner = THIS_MODULE;
13749 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13750 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13751 bp->ptp_clock_info.n_alarm = 0;
13752 bp->ptp_clock_info.n_ext_ts = 0;
13753 bp->ptp_clock_info.n_per_out = 0;
13754 bp->ptp_clock_info.pps = 0;
13755 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13756 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
5d45186b
RC		 13757 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13758 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
eeed018c
MK		 13759 bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13760
13761 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13762 if (IS_ERR(bp->ptp_clock)) {
13763 bp->ptp_clock = NULL;
13764 BNX2X_ERR("PTP clock registeration failed\n");
13765 }
13766}
13767
1ab4434c
AE		 13768static int bnx2x_init_one(struct pci_dev *pdev,
13769 const struct pci_device_id *ent)
13770{
13771 struct net_device *dev = NULL;
13772 struct bnx2x *bp;
b91e1a1a
YM		 13773 enum pcie_link_width pcie_width;
13774 enum pci_bus_speed pcie_speed;
1ab4434c
AE		 13775 int rc, max_non_def_sbs;
13776 int rx_count, tx_count, rss_count, doorbell_size;
13777 int max_cos_est;
13778 bool is_vf;
13779 int cnic_cnt;
13780
12a8541d
YM		 13781 /* Management FW 'remembers' living interfaces. Allow it some time
13782 * to forget previously living interfaces, allowing a proper re-load.
13783 */
cd9c3997
MS		 13784 if (is_kdump_kernel()) {
13785 ktime_t now = ktime_get_boottime();
13786 ktime_t fw_ready_time = ktime_set(5, 0);
13787
13788 if (ktime_before(now, fw_ready_time))
13789 msleep(ktime_ms_delta(fw_ready_time, now));
13790 }
12a8541d 13791
1ab4434c
AE		 13792 /* An estimated maximum supported CoS number according to the chip
13793 * version.
13794 * We will try to roughly estimate the maximum number of CoSes this chip
13795 * may support in order to minimize the memory allocated for Tx
13796 * netdev_queue's. This number will be accurately calculated during the
13797 * initialization of bp->max_cos based on the chip versions AND chip
13798 * revision in the bnx2x_init_bp().
13799 */
13800 max_cos_est = set_max_cos_est(ent->driver_data);
13801 if (max_cos_est < 0)
13802 return max_cos_est;
13803 is_vf = set_is_vf(ent->driver_data);
13804 cnic_cnt = is_vf ? 0 : 1;
13805
60cad4e6
AE		 13806 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13807
13808 /* add another SB for VF as it has no default SB */
13809 max_non_def_sbs += is_vf ? 1 : 0;
6383c0b3
AE		 13810
13811 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
60cad4e6 13812 rss_count = max_non_def_sbs - cnic_cnt;
1ab4434c
AE		 13813
13814 if (rss_count < 1)
13815 return -EINVAL;
6383c0b3
AE		 13816
13817 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
55c11941 13818 rx_count = rss_count + cnic_cnt;
6383c0b3 13819
1ab4434c 13820 /* Maximum number of netdev Tx queues:
37ae41a9 13821 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
6383c0b3 13822 */
55c11941 13823 tx_count = rss_count * max_cos_est + cnic_cnt;
f85582f8 13824
a2fbb9ea 13825 /* dev zeroed in init_etherdev */
6383c0b3 13826 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
41de8d4c 13827 if (!dev)
a2fbb9ea
ET		 13828 return -ENOMEM;
13829
a2fbb9ea 13830 bp = netdev_priv(dev);
a2fbb9ea 13831
1ab4434c
AE		 13832 bp->flags = 0;
13833 if (is_vf)
13834 bp->flags |= IS_VF_FLAG;
13835
6383c0b3 13836 bp->igu_sb_cnt = max_non_def_sbs;
1ab4434c 13837 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
6383c0b3 13838 bp->msg_enable = debug;
55c11941 13839 bp->cnic_support = cnic_cnt;
4bd9b0ff 13840 bp->cnic_probe = bnx2x_cnic_probe;
55c11941 13841
6383c0b3 13842 pci_set_drvdata(pdev, dev);
523224a3 13843
1ab4434c 13844 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
a2fbb9ea
ET		 13845 if (rc < 0) {
13846 free_netdev(dev);
13847 return rc;
13848 }
13849
1ab4434c
AE		 13850 BNX2X_DEV_INFO("This is a %s function\n",
13851 IS_PF(bp) ? "physical" : "virtual");
55c11941 13852 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
1ab4434c 13853 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
60aa0509 13854 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
2de67439 13855 tx_count, rx_count);
60aa0509 13856
34f80b04 13857 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 13858 if (rc)
13859 goto init_one_exit;
13860
1ab4434c
AE		 13861 /* Map doorbells here as we need the real value of bp->max_cos which
13862 * is initialized in bnx2x_init_bp() to determine the number of
13863 * l2 connections.
6383c0b3 13864 */
1ab4434c 13865 if (IS_VF(bp)) {
1d6f3cd8 13866 bp->doorbells = bnx2x_vf_doorbells(bp);
6411280a
AE		 13867 rc = bnx2x_vf_pci_alloc(bp);
13868 if (rc)
13869 goto init_one_exit;
1ab4434c
AE		 13870 } else {
13871 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13872 if (doorbell_size > pci_resource_len(pdev, 2)) {
13873 dev_err(&bp->pdev->dev,
13874 "Cannot map doorbells, bar size too small, aborting\n");
13875 rc = -ENOMEM;
13876 goto init_one_exit;
13877 }
13878 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13879 doorbell_size);
37ae41a9 13880 }
6383c0b3
AE		 13881 if (!bp->doorbells) {
13882 dev_err(&bp->pdev->dev,
13883 "Cannot map doorbell space, aborting\n");
13884 rc = -ENOMEM;
13885 goto init_one_exit;
13886 }
13887
be1f1ffa
AE		 13888 if (IS_VF(bp)) {
13889 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13890 if (rc)
13891 goto init_one_exit;
13892 }
13893
3c76feff
AE		 13894 /* Enable SRIOV if capability found in configuration space */
13895 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
290ca2bb
AE		 13896 if (rc)
13897 goto init_one_exit;
13898
523224a3 13899 /* calc qm_cid_count */
6383c0b3 13900 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
1ab4434c 13901 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
523224a3 13902
55c11941 13903 /* disable FCOE L2 queue for E1x*/
62ac0dc9 13904 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 13905 bp->flags |= NO_FCOE_FLAG;
13906
0e8d2ec5
MS		 13907 /* Set bp->num_queues for MSI-X mode*/
13908 bnx2x_set_num_queues(bp);
13909
25985edc 13910 /* Configure interrupt mode: try to enable MSI-X/MSI if
0e8d2ec5 13911 * needed.
d6214d7a 13912 */
1ab4434c
AE		 13913 rc = bnx2x_set_int_mode(bp);
13914 if (rc) {
13915 dev_err(&pdev->dev, "Cannot set interrupts\n");
13916 goto init_one_exit;
13917 }
04c46736 13918 BNX2X_DEV_INFO("set interrupts successfully\n");
d6214d7a 13919
1ab4434c 13920 /* register the net device */
b340007f
VZ		 13921 rc = register_netdev(dev);
13922 if (rc) {
13923 dev_err(&pdev->dev, "Cannot register net device\n");
13924 goto init_one_exit;
13925 }
1ab4434c 13926 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
b340007f 13927
ec6ba945
VZ		 13928 if (!NO_FCOE(bp)) {
13929 /* Add storage MAC address */
13930 rtnl_lock();
13931 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13932 rtnl_unlock();
13933 }
b91e1a1a
YM		 13934 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13935 pcie_speed == PCI_SPEED_UNKNOWN ||
13936 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13937 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13938 else
13939 BNX2X_DEV_INFO(
13940 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
ca1ee4b2
DK		 13941 board_info[ent->driver_data].name,
13942 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13943 pcie_width,
b91e1a1a
YM		 13944 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13945 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13946 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
ca1ee4b2
DK		 13947 "Unknown",
13948 dev->base_addr, bp->pdev->irq, dev->dev_addr);
c016201c 13949
eeed018c
MK		 13950 bnx2x_register_phc(bp);
13951
230d00eb
YM		 13952 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
13953 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
13954
a2fbb9ea 13955 return 0;
34f80b04
EG		 13956
13957init_one_exit:
33d8e6a5
YM		 13958 bnx2x_disable_pcie_error_reporting(bp);
13959
34f80b04
EG		 13960 if (bp->regview)
13961 iounmap(bp->regview);
13962
1ab4434c 13963 if (IS_PF(bp) && bp->doorbells)
34f80b04
EG		 13964 iounmap(bp->doorbells);
13965
13966 free_netdev(dev);
13967
13968 if (atomic_read(&pdev->enable_cnt) == 1)
13969 pci_release_regions(pdev);
13970
13971 pci_disable_device(pdev);
34f80b04
EG		 13972
13973 return rc;
a2fbb9ea
ET		 13974}
13975
b030ed2f
YM		 13976static void __bnx2x_remove(struct pci_dev *pdev,
13977 struct net_device *dev,
13978 struct bnx2x *bp,
13979 bool remove_netdev)
a2fbb9ea 13980{
eeed018c
MK		 13981 if (bp->ptp_clock) {
13982 ptp_clock_unregister(bp->ptp_clock);
13983 bp->ptp_clock = NULL;
13984 }
13985
ec6ba945
VZ		 13986 /* Delete storage MAC address */
13987 if (!NO_FCOE(bp)) {
13988 rtnl_lock();
13989 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13990 rtnl_unlock();
13991 }
ec6ba945 13992
98507672
SR		 13993#ifdef BCM_DCBNL
13994 /* Delete app tlvs from dcbnl */
13995 bnx2x_dcbnl_update_applist(bp, true);
13996#endif
13997
a6d3a5ba
BW		 13998 if (IS_PF(bp) &&
13999 !BP_NOMCP(bp) &&
14000 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
14001 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
14002
b030ed2f
YM		 14003 /* Close the interface - either directly or implicitly */
14004 if (remove_netdev) {
14005 unregister_netdev(dev);
14006 } else {
14007 rtnl_lock();
6ef5a92c 14008 dev_close(dev);
b030ed2f
YM		 14009 rtnl_unlock();
14010 }
a2fbb9ea 14011
78c3bcc5
AE		 14012 bnx2x_iov_remove_one(bp);
14013
084d6cbb 14014 /* Power on: we can't let PCI layer write to us while we are in D3 */
04860eb7 14015 if (IS_PF(bp)) {
1ab4434c 14016 bnx2x_set_power_state(bp, PCI_D0);
230d00eb 14017 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
084d6cbb 14018
04860eb7
MC		 14019 /* Set endianity registers to reset values in case next driver
14020 * boots in different endianty environment.
14021 */
14022 bnx2x_reset_endianity(bp);
14023 }
14024
d6214d7a
DK		 14025 /* Disable MSI/MSI-X */
14026 bnx2x_disable_msi(bp);
f85582f8 14027
084d6cbb 14028 /* Power off */
1ab4434c
AE		 14029 if (IS_PF(bp))
14030 bnx2x_set_power_state(bp, PCI_D3hot);
084d6cbb 14031
72fd0718 14032 /* Make sure RESET task is not scheduled before continuing */
7be08a72 14033 cancel_delayed_work_sync(&bp->sp_rtnl_task);
290ca2bb 14034
4513f925
AE		 14035 /* send message via vfpf channel to release the resources of this vf */
14036 if (IS_VF(bp))
14037 bnx2x_vfpf_release(bp);
72fd0718 14038
b030ed2f
YM		 14039 /* Assumes no further PCIe PM changes will occur */
14040 if (system_state == SYSTEM_POWER_OFF) {
14041 pci_wake_from_d3(pdev, bp->wol);
14042 pci_set_power_state(pdev, PCI_D3hot);
14043 }
14044
33d8e6a5 14045 bnx2x_disable_pcie_error_reporting(bp);
d9aee591
YM		 14046 if (remove_netdev) {
14047 if (bp->regview)
14048 iounmap(bp->regview);
33d8e6a5 14049
d9aee591
YM		 14050 /* For vfs, doorbells are part of the regview and were unmapped
14051 * along with it. FW is only loaded by PF.
14052 */
14053 if (IS_PF(bp)) {
14054 if (bp->doorbells)
14055 iounmap(bp->doorbells);
eb2afd4a 14056
d9aee591 14057 bnx2x_release_firmware(bp);
e2a367f8
YM		 14058 } else {
14059 bnx2x_vf_pci_dealloc(bp);
d9aee591
YM		 14060 }
14061 bnx2x_free_mem_bp(bp);
523224a3 14062
b030ed2f 14063 free_netdev(dev);
34f80b04 14064
d9aee591
YM		 14065 if (atomic_read(&pdev->enable_cnt) == 1)
14066 pci_release_regions(pdev);
34f80b04 14067
5f6db130
YM		 14068 pci_disable_device(pdev);
14069 }
a2fbb9ea
ET		 14070}
14071
b030ed2f
YM		 14072static void bnx2x_remove_one(struct pci_dev *pdev)
14073{
14074 struct net_device *dev = pci_get_drvdata(pdev);
14075 struct bnx2x *bp;
14076
14077 if (!dev) {
14078 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
14079 return;
14080 }
14081 bp = netdev_priv(dev);
14082
14083 __bnx2x_remove(pdev, dev, bp, true);
14084}
14085
f8ef6e44
YG		 14086static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
14087{
7fa6f340 14088 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
f8ef6e44
YG		 14089
14090 bp->rx_mode = BNX2X_RX_MODE_NONE;
14091
55c11941
MS		 14092 if (CNIC_LOADED(bp))
14093 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
14094
619c5cb6
VZ		 14095 /* Stop Tx */
14096 bnx2x_tx_disable(bp);
26614ba5
MS		 14097 /* Delete all NAPI objects */
14098 bnx2x_del_all_napi(bp);
55c11941
MS		 14099 if (CNIC_LOADED(bp))
14100 bnx2x_del_all_napi_cnic(bp);
7fa6f340 14101 netdev_reset_tc(bp->dev);
f8ef6e44
YG		 14102
14103 del_timer_sync(&bp->timer);
0c0e6341 14104 cancel_delayed_work_sync(&bp->sp_task);
14105 cancel_delayed_work_sync(&bp->period_task);
619c5cb6 14106
c6e36d8c
YM		 14107 if (!down_timeout(&bp->stats_lock, HZ / 10)) {
14108 bp->stats_state = STATS_STATE_DISABLED;
14109 up(&bp->stats_lock);
14110 }
f8ef6e44 14111
7fa6f340 14112 bnx2x_save_statistics(bp);
f8ef6e44 14113
619c5cb6
VZ		 14114 netif_carrier_off(bp->dev);
14115
f8ef6e44
YG		 14116 return 0;
14117}
14118
493adb1f
WX		 14119/**
14120 * bnx2x_io_error_detected - called when PCI error is detected
14121 * @pdev: Pointer to PCI device
14122 * @state: The current pci connection state
14123 *
14124 * This function is called after a PCI bus error affecting
14125 * this device has been detected.
14126 */
14127static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
14128 pci_channel_state_t state)
14129{
14130 struct net_device *dev = pci_get_drvdata(pdev);
14131 struct bnx2x *bp = netdev_priv(dev);
14132
14133 rtnl_lock();
14134
7fa6f340
YM		 14135 BNX2X_ERR("IO error detected\n");
14136
493adb1f
WX		 14137 netif_device_detach(dev);
14138
07ce50e4
DN		 14139 if (state == pci_channel_io_perm_failure) {
14140 rtnl_unlock();
14141 return PCI_ERS_RESULT_DISCONNECT;
14142 }
14143
493adb1f 14144 if (netif_running(dev))
f8ef6e44 14145 bnx2x_eeh_nic_unload(bp);
493adb1f 14146
7fa6f340
YM		 14147 bnx2x_prev_path_mark_eeh(bp);
14148
493adb1f
WX		 14149 pci_disable_device(pdev);
14150
14151 rtnl_unlock();
14152
14153 /* Request a slot reset */
14154 return PCI_ERS_RESULT_NEED_RESET;
14155}
14156
14157/**
14158 * bnx2x_io_slot_reset - called after the PCI bus has been reset
14159 * @pdev: Pointer to PCI device
14160 *
14161 * Restart the card from scratch, as if from a cold-boot.
14162 */
14163static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
14164{
14165 struct net_device *dev = pci_get_drvdata(pdev);
14166 struct bnx2x *bp = netdev_priv(dev);
7fa6f340 14167 int i;
493adb1f
WX		 14168
14169 rtnl_lock();
7fa6f340 14170 BNX2X_ERR("IO slot reset initializing...\n");
493adb1f
WX		 14171 if (pci_enable_device(pdev)) {
14172 dev_err(&pdev->dev,
14173 "Cannot re-enable PCI device after reset\n");
14174 rtnl_unlock();
14175 return PCI_ERS_RESULT_DISCONNECT;
14176 }
14177
14178 pci_set_master(pdev);
14179 pci_restore_state(pdev);
70632d0a 14180 pci_save_state(pdev);
493adb1f
WX		 14181
14182 if (netif_running(dev))
14183 bnx2x_set_power_state(bp, PCI_D0);
14184
7fa6f340
YM		 14185 if (netif_running(dev)) {
14186 BNX2X_ERR("IO slot reset --> driver unload\n");
e68072ef
YM		 14187
14188 /* MCP should have been reset; Need to wait for validity */
14189 bnx2x_init_shmem(bp);
14190
7fa6f340
YM		 14191 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
14192 u32 v;
14193
14194 v = SHMEM2_RD(bp,
14195 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
14196 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
14197 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
14198 }
14199 bnx2x_drain_tx_queues(bp);
14200 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
14201 bnx2x_netif_stop(bp, 1);
14202 bnx2x_free_irq(bp);
14203
14204 /* Report UNLOAD_DONE to MCP */
14205 bnx2x_send_unload_done(bp, true);
14206
14207 bp->sp_state = 0;
14208 bp->port.pmf = 0;
14209
14210 bnx2x_prev_unload(bp);
14211
16a5fd92 14212 /* We should have reseted the engine, so It's fair to
7fa6f340
YM		 14213 * assume the FW will no longer write to the bnx2x driver.
14214 */
14215 bnx2x_squeeze_objects(bp);
14216 bnx2x_free_skbs(bp);
14217 for_each_rx_queue(bp, i)
14218 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
14219 bnx2x_free_fp_mem(bp);
14220 bnx2x_free_mem(bp);
14221
14222 bp->state = BNX2X_STATE_CLOSED;
14223 }
14224
493adb1f
WX		 14225 rtnl_unlock();
14226
33d8e6a5
YM		 14227 /* If AER, perform cleanup of the PCIe registers */
14228 if (bp->flags & AER_ENABLED) {
14229 if (pci_cleanup_aer_uncorrect_error_status(pdev))
14230 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
14231 else
14232 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
14233 }
14234
493adb1f
WX		 14235 return PCI_ERS_RESULT_RECOVERED;
14236}
14237
14238/**
14239 * bnx2x_io_resume - called when traffic can start flowing again
14240 * @pdev: Pointer to PCI device
14241 *
14242 * This callback is called when the error recovery driver tells us that
14243 * its OK to resume normal operation.
14244 */
14245static void bnx2x_io_resume(struct pci_dev *pdev)
14246{
14247 struct net_device *dev = pci_get_drvdata(pdev);
14248 struct bnx2x *bp = netdev_priv(dev);
14249
72fd0718 14250 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580 14251 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
72fd0718
VZ		 14252 return;
14253 }
14254
493adb1f
WX		 14255 rtnl_lock();
14256
7fa6f340
YM		 14257 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
14258 DRV_MSG_SEQ_NUMBER_MASK;
14259
493adb1f 14260 if (netif_running(dev))
f8ef6e44 14261 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 14262
14263 netif_device_attach(dev);
14264
14265 rtnl_unlock();
14266}
14267
3646f0e5 14268static const struct pci_error_handlers bnx2x_err_handler = {
493adb1f 14269 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 14270 .slot_reset = bnx2x_io_slot_reset,
14271 .resume = bnx2x_io_resume,
493adb1f
WX		 14272};
14273
b030ed2f
YM		 14274static void bnx2x_shutdown(struct pci_dev *pdev)
14275{
14276 struct net_device *dev = pci_get_drvdata(pdev);
14277 struct bnx2x *bp;
14278
14279 if (!dev)
14280 return;
14281
14282 bp = netdev_priv(dev);
14283 if (!bp)
14284 return;
14285
14286 rtnl_lock();
14287 netif_device_detach(dev);
14288 rtnl_unlock();
14289
14290 /* Don't remove the netdevice, as there are scenarios which will cause
14291 * the kernel to hang, e.g., when trying to remove bnx2i while the
14292 * rootfs is mounted from SAN.
14293 */
14294 __bnx2x_remove(pdev, dev, bp, false);
14295}
14296
a2fbb9ea 14297static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 14298 .name = DRV_MODULE_NAME,
14299 .id_table = bnx2x_pci_tbl,
14300 .probe = bnx2x_init_one,
0329aba1 14301 .remove = bnx2x_remove_one,
493adb1f
WX		 14302 .suspend = bnx2x_suspend,
14303 .resume = bnx2x_resume,
14304 .err_handler = &bnx2x_err_handler,
3c76feff
AE		 14305#ifdef CONFIG_BNX2X_SRIOV
14306 .sriov_configure = bnx2x_sriov_configure,
14307#endif
b030ed2f 14308 .shutdown = bnx2x_shutdown,
a2fbb9ea
ET		 14309};
14310
14311static int __init bnx2x_init(void)
14312{
dd21ca6d
SG		 14313 int ret;
14314
7995c64e 14315 pr_info("%s", version);
938cf541 14316
1cf167f2
EG		 14317 bnx2x_wq = create_singlethread_workqueue("bnx2x");
14318 if (bnx2x_wq == NULL) {
7995c64e 14319 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 14320 return -ENOMEM;
14321 }
370d4a26
YM		 14322 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
14323 if (!bnx2x_iov_wq) {
14324 pr_err("Cannot create iov workqueue\n");
14325 destroy_workqueue(bnx2x_wq);
14326 return -ENOMEM;
14327 }
1cf167f2 14328
dd21ca6d
SG		 14329 ret = pci_register_driver(&bnx2x_pci_driver);
14330 if (ret) {
7995c64e 14331 pr_err("Cannot register driver\n");
dd21ca6d 14332 destroy_workqueue(bnx2x_wq);
370d4a26 14333 destroy_workqueue(bnx2x_iov_wq);
dd21ca6d
SG		 14334 }
14335 return ret;
a2fbb9ea
ET		 14336}
14337
14338static void __exit bnx2x_cleanup(void)
14339{
452427b0 14340 struct list_head *pos, *q;
d76a6111 14341
a2fbb9ea 14342 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 14343
14344 destroy_workqueue(bnx2x_wq);
370d4a26 14345 destroy_workqueue(bnx2x_iov_wq);
452427b0 14346
16a5fd92 14347 /* Free globally allocated resources */
452427b0
YM		 14348 list_for_each_safe(pos, q, &bnx2x_prev_list) {
14349 struct bnx2x_prev_path_list *tmp =
14350 list_entry(pos, struct bnx2x_prev_path_list, list);
14351 list_del(pos);
14352 kfree(tmp);
14353 }
a2fbb9ea
ET		 14354}
14355
3deb8167
YR		 14356void bnx2x_notify_link_changed(struct bnx2x *bp)
14357{
14358 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14359}
14360
a2fbb9ea
ET		 14361module_init(bnx2x_init);
14362module_exit(bnx2x_cleanup);
14363
619c5cb6
VZ		 14364/**
14365 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14366 *
14367 * @bp: driver handle
14368 * @set: set or clear the CAM entry
14369 *
16a5fd92 14370 * This function will wait until the ramrod completion returns.
619c5cb6
VZ		 14371 * Return 0 if success, -ENODEV if ramrod doesn't return.
14372 */
1191cb83 14373static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
619c5cb6
VZ		 14374{
14375 unsigned long ramrod_flags = 0;
14376
14377 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14378 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14379 &bp->iscsi_l2_mac_obj, true,
14380 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14381}
993ac7b5
MC		 14382
14383/* count denotes the number of new completions we have seen */
14384static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14385{
14386 struct eth_spe *spe;
a052997e 14387 int cxt_index, cxt_offset;
993ac7b5
MC		 14388
14389#ifdef BNX2X_STOP_ON_ERROR
14390 if (unlikely(bp->panic))
14391 return;
14392#endif
14393
14394 spin_lock_bh(&bp->spq_lock);
c2bff63f 14395 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 14396 bp->cnic_spq_pending -= count;
14397
c2bff63f
DK		 14398 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14399 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14400 & SPE_HDR_CONN_TYPE) >>
14401 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 14402 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14403 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 14404
14405 /* Set validation for iSCSI L2 client before sending SETUP
14406 * ramrod
14407 */
14408 if (type == ETH_CONNECTION_TYPE) {
a052997e 14409 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
37ae41a9 14410 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
a052997e 14411 ILT_PAGE_CIDS;
37ae41a9 14412 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
a052997e
MS		 14413 (cxt_index * ILT_PAGE_CIDS);
14414 bnx2x_set_ctx_validation(bp,
14415 &bp->context[cxt_index].
14416 vcxt[cxt_offset].eth,
37ae41a9 14417 BNX2X_ISCSI_ETH_CID(bp));
a052997e 14418 }
c2bff63f
DK		 14419 }
14420
619c5cb6
VZ		 14421 /*
14422 * There may be not more than 8 L2, not more than 8 L5 SPEs
14423 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 14424 * COMMON ramrods is not more than the EQ and SPQ can
14425 * accommodate.
c2bff63f 14426 */
6e30dd4e
VZ		 14427 if (type == ETH_CONNECTION_TYPE) {
14428 if (!atomic_read(&bp->cq_spq_left))
14429 break;
14430 else
14431 atomic_dec(&bp->cq_spq_left);
14432 } else if (type == NONE_CONNECTION_TYPE) {
14433 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 14434 break;
14435 else
6e30dd4e 14436 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 14437 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14438 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 14439 if (bp->cnic_spq_pending >=
14440 bp->cnic_eth_dev.max_kwqe_pending)
14441 break;
14442 else
14443 bp->cnic_spq_pending++;
14444 } else {
14445 BNX2X_ERR("Unknown SPE type: %d\n", type);
14446 bnx2x_panic();
993ac7b5 14447 break;
c2bff63f 14448 }
993ac7b5
MC		 14449
14450 spe = bnx2x_sp_get_next(bp);
14451 *spe = *bp->cnic_kwq_cons;
14452
51c1a580 14453 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
993ac7b5
MC		 14454 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14455
14456 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14457 bp->cnic_kwq_cons = bp->cnic_kwq;
14458 else
14459 bp->cnic_kwq_cons++;
14460 }
14461 bnx2x_sp_prod_update(bp);
14462 spin_unlock_bh(&bp->spq_lock);
14463}
14464
14465static int bnx2x_cnic_sp_queue(struct net_device *dev,
14466 struct kwqe_16 *kwqes[], u32 count)
14467{
14468 struct bnx2x *bp = netdev_priv(dev);
14469 int i;
14470
14471#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 14472 if (unlikely(bp->panic)) {
14473 BNX2X_ERR("Can't post to SP queue while panic\n");
993ac7b5 14474 return -EIO;
51c1a580 14475 }
993ac7b5
MC		 14476#endif
14477
95c6c616
AE		 14478 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14479 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
51c1a580 14480 BNX2X_ERR("Handling parity error recovery. Try again later\n");
95c6c616
AE		 14481 return -EAGAIN;
14482 }
14483
993ac7b5
MC		 14484 spin_lock_bh(&bp->spq_lock);
14485
14486 for (i = 0; i < count; i++) {
14487 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14488
14489 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14490 break;
14491
14492 *bp->cnic_kwq_prod = *spe;
14493
14494 bp->cnic_kwq_pending++;
14495
51c1a580 14496 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
993ac7b5 14497 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 14498 spe->data.update_data_addr.hi,
14499 spe->data.update_data_addr.lo,
993ac7b5
MC		 14500 bp->cnic_kwq_pending);
14501
14502 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14503 bp->cnic_kwq_prod = bp->cnic_kwq;
14504 else
14505 bp->cnic_kwq_prod++;
14506 }
14507
14508 spin_unlock_bh(&bp->spq_lock);
14509
14510 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14511 bnx2x_cnic_sp_post(bp, 0);
14512
14513 return i;
14514}
14515
14516static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14517{
14518 struct cnic_ops *c_ops;
14519 int rc = 0;
14520
14521 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 14522 c_ops = rcu_dereference_protected(bp->cnic_ops,
14523 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 14524 if (c_ops)
14525 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14526 mutex_unlock(&bp->cnic_mutex);
14527
14528 return rc;
14529}
14530
14531static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14532{
14533 struct cnic_ops *c_ops;
14534 int rc = 0;
14535
14536 rcu_read_lock();
14537 c_ops = rcu_dereference(bp->cnic_ops);
14538 if (c_ops)
14539 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14540 rcu_read_unlock();
14541
14542 return rc;
14543}
14544
14545/*
14546 * for commands that have no data
14547 */
9f6c9258 14548int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 14549{
14550 struct cnic_ctl_info ctl = {0};
14551
14552 ctl.cmd = cmd;
14553
14554 return bnx2x_cnic_ctl_send(bp, &ctl);
14555}
14556
619c5cb6 14557static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 14558{
619c5cb6 14559 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 14560
14561 /* first we tell CNIC and only then we count this as a completion */
14562 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14563 ctl.data.comp.cid = cid;
619c5cb6 14564 ctl.data.comp.error = err;
993ac7b5
MC		 14565
14566 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 14567 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 14568}
14569
619c5cb6
VZ		 14570/* Called with netif_addr_lock_bh() taken.
14571 * Sets an rx_mode config for an iSCSI ETH client.
14572 * Doesn't block.
14573 * Completion should be checked outside.
14574 */
14575static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14576{
14577 unsigned long accept_flags = 0, ramrod_flags = 0;
14578 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14579 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14580
14581 if (start) {
14582 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14583 * because it's the only way for UIO Queue to accept
14584 * multicasts (in non-promiscuous mode only one Queue per
14585 * function will receive multicast packets (leading in our
14586 * case).
14587 */
14588 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14589 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14590 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14591 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14592
14593 /* Clear STOP_PENDING bit if START is requested */
14594 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14595
14596 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14597 } else
14598 /* Clear START_PENDING bit if STOP is requested */
14599 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14600
14601 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14602 set_bit(sched_state, &bp->sp_state);
14603 else {
14604 __set_bit(RAMROD_RX, &ramrod_flags);
14605 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14606 ramrod_flags);
14607 }
14608}
14609
993ac7b5
MC		 14610static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14611{
14612 struct bnx2x *bp = netdev_priv(dev);
14613 int rc = 0;
14614
14615 switch (ctl->cmd) {
14616 case DRV_CTL_CTXTBL_WR_CMD: {
14617 u32 index = ctl->data.io.offset;
14618 dma_addr_t addr = ctl->data.io.dma_addr;
14619
14620 bnx2x_ilt_wr(bp, index, addr);
14621 break;
14622 }
14623
c2bff63f
DK		 14624 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14625 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 14626
14627 bnx2x_cnic_sp_post(bp, count);
14628 break;
14629 }
14630
14631 /* rtnl_lock is held. */
14632 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 14633 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14634 unsigned long sp_bits = 0;
14635
14636 /* Configure the iSCSI classification object */
14637 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14638 cp->iscsi_l2_client_id,
14639 cp->iscsi_l2_cid, BP_FUNC(bp),
14640 bnx2x_sp(bp, mac_rdata),
14641 bnx2x_sp_mapping(bp, mac_rdata),
14642 BNX2X_FILTER_MAC_PENDING,
14643 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14644 &bp->macs_pool);
ec6ba945 14645
523224a3 14646 /* Set iSCSI MAC address */
619c5cb6
VZ		 14647 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14648 if (rc)
14649 break;
523224a3
DK		 14650
14651 mmiowb();
14652 barrier();
14653
619c5cb6
VZ		 14654 /* Start accepting on iSCSI L2 ring */
14655
14656 netif_addr_lock_bh(dev);
14657 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14658 netif_addr_unlock_bh(dev);
14659
14660 /* bits to wait on */
14661 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14662 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14663
14664 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14665 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 14666
993ac7b5
MC		 14667 break;
14668 }
14669
14670 /* rtnl_lock is held. */
14671 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 14672 unsigned long sp_bits = 0;
993ac7b5 14673
523224a3 14674 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 14675 netif_addr_lock_bh(dev);
14676 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14677 netif_addr_unlock_bh(dev);
14678
14679 /* bits to wait on */
14680 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14681 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14682
14683 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14684 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 14685
14686 mmiowb();
14687 barrier();
14688
14689 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 14690 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14691 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 14692 break;
14693 }
c2bff63f
DK		 14694 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14695 int count = ctl->data.credit.credit_count;
14696
4e857c58 14697 smp_mb__before_atomic();
6e30dd4e 14698 atomic_add(count, &bp->cq_spq_left);
4e857c58 14699 smp_mb__after_atomic();
c2bff63f
DK		 14700 break;
14701 }
1d187b34 14702 case DRV_CTL_ULP_REGISTER_CMD: {
2e499d3c 14703 int ulp_type = ctl->data.register_data.ulp_type;
1d187b34
BW		 14704
14705 if (CHIP_IS_E3(bp)) {
14706 int idx = BP_FW_MB_IDX(bp);
2e499d3c
BW		 14707 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14708 int path = BP_PATH(bp);
14709 int port = BP_PORT(bp);
14710 int i;
14711 u32 scratch_offset;
14712 u32 *host_addr;
1d187b34 14713
2e499d3c 14714 /* first write capability to shmem2 */
1d187b34
BW		 14715 if (ulp_type == CNIC_ULP_ISCSI)
14716 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14717 else if (ulp_type == CNIC_ULP_FCOE)
14718 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14719 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
2e499d3c
BW		 14720
14721 if ((ulp_type != CNIC_ULP_FCOE) ||
14722 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14723 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
14724 break;
14725
14726 /* if reached here - should write fcoe capabilities */
14727 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14728 if (!scratch_offset)
14729 break;
14730 scratch_offset += offsetof(struct glob_ncsi_oem_data,
14731 fcoe_features[path][port]);
14732 host_addr = (u32 *) &(ctl->data.register_data.
14733 fcoe_features);
14734 for (i = 0; i < sizeof(struct fcoe_capabilities);
14735 i += 4)
14736 REG_WR(bp, scratch_offset + i,
14737 *(host_addr + i/4));
1d187b34 14738 }
42f8277f 14739 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 14740 break;
14741 }
2e499d3c 14742
1d187b34
BW		 14743 case DRV_CTL_ULP_UNREGISTER_CMD: {
14744 int ulp_type = ctl->data.ulp_type;
14745
14746 if (CHIP_IS_E3(bp)) {
14747 int idx = BP_FW_MB_IDX(bp);
14748 u32 cap;
14749
14750 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14751 if (ulp_type == CNIC_ULP_ISCSI)
14752 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14753 else if (ulp_type == CNIC_ULP_FCOE)
14754 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14755 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14756 }
42f8277f 14757 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 14758 break;
14759 }
993ac7b5
MC		 14760
14761 default:
14762 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14763 rc = -EINVAL;
14764 }
14765
97ac4ef7
YM		 14766 /* For storage-only interfaces, change driver state */
14767 if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) {
14768 switch (ctl->drv_state) {
14769 case DRV_NOP:
14770 break;
14771 case DRV_ACTIVE:
14772 bnx2x_set_os_driver_state(bp,
14773 OS_DRIVER_STATE_ACTIVE);
14774 break;
14775 case DRV_INACTIVE:
14776 bnx2x_set_os_driver_state(bp,
14777 OS_DRIVER_STATE_DISABLED);
14778 break;
14779 case DRV_UNLOADED:
14780 bnx2x_set_os_driver_state(bp,
14781 OS_DRIVER_STATE_NOT_LOADED);
14782 break;
14783 default:
14784 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state);
14785 }
14786 }
14787
14788 return rc;
14789}
14790
14791static int bnx2x_get_fc_npiv(struct net_device *dev,
14792 struct cnic_fc_npiv_tbl *cnic_tbl)
14793{
14794 struct bnx2x *bp = netdev_priv(dev);
14795 struct bdn_fc_npiv_tbl *tbl = NULL;
14796 u32 offset, entries;
14797 int rc = -EINVAL;
14798 int i;
14799
14800 if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0]))
14801 goto out;
14802
14803 DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n");
14804
14805 tbl = kmalloc(sizeof(*tbl), GFP_KERNEL);
14806 if (!tbl) {
14807 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14808 goto out;
14809 }
14810
14811 offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
14812 DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset);
14813
14814 /* Read the table contents from nvram */
14815 if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) {
14816 BNX2X_ERR("Failed to read FC-NPIV table\n");
14817 goto out;
14818 }
14819
14820 /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14821 * the number of entries back to cpu endianness.
14822 */
14823 entries = tbl->fc_npiv_cfg.num_of_npiv;
14824 entries = (__force u32)be32_to_cpu((__force __be32)entries);
14825 tbl->fc_npiv_cfg.num_of_npiv = entries;
14826
14827 if (!tbl->fc_npiv_cfg.num_of_npiv) {
14828 DP(BNX2X_MSG_MCP,
14829 "No FC-NPIV table [valid, simply not present]\n");
14830 goto out;
14831 } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) {
14832 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14833 tbl->fc_npiv_cfg.num_of_npiv);
14834 goto out;
14835 } else {
14836 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n",
14837 tbl->fc_npiv_cfg.num_of_npiv);
14838 }
14839
14840 /* Copy the data into cnic-provided struct */
14841 cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv;
14842 for (i = 0; i < cnic_tbl->count; i++) {
14843 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8);
14844 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8);
14845 }
14846
14847 rc = 0;
14848out:
14849 kfree(tbl);
993ac7b5
MC		 14850 return rc;
14851}
14852
9f6c9258 14853void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 14854{
14855 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14856
14857 if (bp->flags & USING_MSIX_FLAG) {
14858 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14859 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14860 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14861 } else {
14862 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14863 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14864 }
619c5cb6 14865 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 14866 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14867 else
14868 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14869
619c5cb6
VZ		 14870 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
14871 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 14872 cp->irq_arr[1].status_blk = bp->def_status_blk;
14873 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 14874 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 14875
14876 cp->num_irq = 2;
14877}
14878
37ae41a9
MS		 14879void bnx2x_setup_cnic_info(struct bnx2x *bp)
14880{
14881 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14882
37ae41a9
MS		 14883 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14884 bnx2x_cid_ilt_lines(bp);
14885 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14886 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14887 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14888
f78afb35
MC		 14889 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14890 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14891 cp->iscsi_l2_cid);
14892
37ae41a9
MS		 14893 if (NO_ISCSI_OOO(bp))
14894 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14895}
14896
993ac7b5
MC		 14897static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14898 void *data)
14899{
14900 struct bnx2x *bp = netdev_priv(dev);
14901 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
55c11941
MS		 14902 int rc;
14903
14904 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
993ac7b5 14905
51c1a580
MS		 14906 if (ops == NULL) {
14907 BNX2X_ERR("NULL ops received\n");
993ac7b5 14908 return -EINVAL;
51c1a580 14909 }
993ac7b5 14910
55c11941
MS		 14911 if (!CNIC_SUPPORT(bp)) {
14912 BNX2X_ERR("Can't register CNIC when not supported\n");
14913 return -EOPNOTSUPP;
14914 }
14915
14916 if (!CNIC_LOADED(bp)) {
14917 rc = bnx2x_load_cnic(bp);
14918 if (rc) {
14919 BNX2X_ERR("CNIC-related load failed\n");
14920 return rc;
14921 }
55c11941
MS		 14922 }
14923
14924 bp->cnic_enabled = true;
14925
993ac7b5
MC		 14926 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14927 if (!bp->cnic_kwq)
14928 return -ENOMEM;
14929
14930 bp->cnic_kwq_cons = bp->cnic_kwq;
14931 bp->cnic_kwq_prod = bp->cnic_kwq;
14932 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14933
14934 bp->cnic_spq_pending = 0;
14935 bp->cnic_kwq_pending = 0;
14936
14937 bp->cnic_data = data;
14938
14939 cp->num_irq = 0;
619c5cb6 14940 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 14941 cp->iro_arr = bp->iro_arr;
993ac7b5 14942
993ac7b5 14943 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 14944
993ac7b5
MC		 14945 rcu_assign_pointer(bp->cnic_ops, ops);
14946
42f8277f
YM		 14947 /* Schedule driver to read CNIC driver versions */
14948 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14949
993ac7b5
MC		 14950 return 0;
14951}
14952
14953static int bnx2x_unregister_cnic(struct net_device *dev)
14954{
14955 struct bnx2x *bp = netdev_priv(dev);
14956 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14957
14958 mutex_lock(&bp->cnic_mutex);
993ac7b5 14959 cp->drv_state = 0;
2cfa5a04 14960 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 14961 mutex_unlock(&bp->cnic_mutex);
14962 synchronize_rcu();
fea75645 14963 bp->cnic_enabled = false;
993ac7b5
MC		 14964 kfree(bp->cnic_kwq);
14965 bp->cnic_kwq = NULL;
14966
14967 return 0;
14968}
14969
a8f47eb7 14970static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
993ac7b5
MC		 14971{
14972 struct bnx2x *bp = netdev_priv(dev);
14973 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14974
2ba45142
VZ		 14975 /* If both iSCSI and FCoE are disabled - return NULL in
14976 * order to indicate CNIC that it should not try to work
14977 * with this device.
14978 */
14979 if (NO_ISCSI(bp) && NO_FCOE(bp))
14980 return NULL;
14981
993ac7b5
MC		 14982 cp->drv_owner = THIS_MODULE;
14983 cp->chip_id = CHIP_ID(bp);
14984 cp->pdev = bp->pdev;
14985 cp->io_base = bp->regview;
14986 cp->io_base2 = bp->doorbells;
14987 cp->max_kwqe_pending = 8;
523224a3 14988 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 14989 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14990 bnx2x_cid_ilt_lines(bp);
993ac7b5 14991 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 14992 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 14993 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14994 cp->drv_ctl = bnx2x_drv_ctl;
97ac4ef7 14995 cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv;
993ac7b5
MC		 14996 cp->drv_register_cnic = bnx2x_register_cnic;
14997 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
37ae41a9 14998 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
619c5cb6
VZ		 14999 cp->iscsi_l2_client_id =
15000 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
37ae41a9 15001 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
c2bff63f 15002
2ba45142
VZ		 15003 if (NO_ISCSI_OOO(bp))
15004 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15005
15006 if (NO_ISCSI(bp))
15007 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
15008
15009 if (NO_FCOE(bp))
15010 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
15011
51c1a580
MS		 15012 BNX2X_DEV_INFO(
15013 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
c2bff63f
DK		 15014 cp->ctx_blk_size,
15015 cp->ctx_tbl_offset,
15016 cp->ctx_tbl_len,
15017 cp->starting_cid);
993ac7b5
MC		 15018 return cp;
15019}
993ac7b5 15020
a8f47eb7 15021static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
9b176b6b 15022{
6411280a
AE		 15023 struct bnx2x *bp = fp->bp;
15024 u32 offset = BAR_USTRORM_INTMEM;
abc5a021 15025
6411280a
AE		 15026 if (IS_VF(bp))
15027 return bnx2x_vf_ustorm_prods_offset(bp, fp);
15028 else if (!CHIP_IS_E1x(bp))
15029 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
15030 else
15031 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
8d9ac297 15032
6411280a 15033 return offset;
8d9ac297 15034}
381ac16b 15035
6411280a
AE		 15036/* called only on E1H or E2.
15037 * When pretending to be PF, the pretend value is the function number 0...7
15038 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15039 * combination
15040 */
15041int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
381ac16b 15042{
6411280a 15043 u32 pretend_reg;
381ac16b 15044
23826850 15045 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
6411280a 15046 return -1;
381ac16b 15047
6411280a
AE		 15048 /* get my own pretend register */
15049 pretend_reg = bnx2x_get_pretend_reg(bp);
15050 REG_WR(bp, pretend_reg, pretend_func_val);
15051 REG_RD(bp, pretend_reg);
381ac16b
AE		 15052 return 0;
15053}
eeed018c
MK		 15054
15055static void bnx2x_ptp_task(struct work_struct *work)
15056{
15057 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
15058 int port = BP_PORT(bp);
15059 u32 val_seq;
15060 u64 timestamp, ns;
15061 struct skb_shared_hwtstamps shhwtstamps;
15062
15063 /* Read Tx timestamp registers */
15064 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15065 NIG_REG_P0_TLLH_PTP_BUF_SEQID);
15066 if (val_seq & 0x10000) {
15067 /* There is a valid timestamp value */
15068 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
15069 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
15070 timestamp <<= 32;
15071 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
15072 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
15073 /* Reset timestamp register to allow new timestamp */
15074 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15075 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15076 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15077
15078 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
15079 shhwtstamps.hwtstamp = ns_to_ktime(ns);
15080 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
15081 dev_kfree_skb_any(bp->ptp_tx_skb);
15082 bp->ptp_tx_skb = NULL;
15083
15084 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15085 timestamp, ns);
15086 } else {
15087 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
15088 /* Reschedule to keep checking for a valid timestamp value */
15089 schedule_work(&bp->ptp_task);
15090 }
15091}
15092
15093void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
15094{
15095 int port = BP_PORT(bp);
15096 u64 timestamp, ns;
15097
15098 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
15099 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
15100 timestamp <<= 32;
15101 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
15102 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
15103
15104 /* Reset timestamp register to allow new timestamp */
15105 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15106 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15107
15108 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15109
15110 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
15111
15112 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15113 timestamp, ns);
15114}
15115
15116/* Read the PHC */
15117static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
15118{
15119 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
15120 int port = BP_PORT(bp);
15121 u32 wb_data[2];
15122 u64 phc_cycles;
15123
15124 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
15125 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
15126 phc_cycles = wb_data[1];
15127 phc_cycles = (phc_cycles << 32) + wb_data[0];
15128
15129 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
15130
15131 return phc_cycles;
15132}
15133
15134static void bnx2x_init_cyclecounter(struct bnx2x *bp)
15135{
15136 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
15137 bp->cyclecounter.read = bnx2x_cyclecounter_read;
f28ba401 15138 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
eeed018c
MK		 15139 bp->cyclecounter.shift = 1;
15140 bp->cyclecounter.mult = 1;
15141}
15142
15143static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
15144{
15145 struct bnx2x_func_state_params func_params = {NULL};
15146 struct bnx2x_func_set_timesync_params *set_timesync_params =
15147 &func_params.params.set_timesync;
15148
15149 /* Prepare parameters for function state transitions */
15150 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
15151 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
15152
15153 func_params.f_obj = &bp->func_obj;
15154 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
15155
15156 /* Function parameters */
15157 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
15158 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
15159
15160 return bnx2x_func_state_change(bp, &func_params);
15161}
15162
1444c301 15163static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
eeed018c
MK		 15164{
15165 struct bnx2x_queue_state_params q_params;
15166 int rc, i;
15167
15168 /* send queue update ramrod to enable PTP packets */
15169 memset(&q_params, 0, sizeof(q_params));
15170 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
15171 q_params.cmd = BNX2X_Q_CMD_UPDATE;
15172 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
15173 &q_params.params.update.update_flags);
15174 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
15175 &q_params.params.update.update_flags);
15176
15177 /* send the ramrod on all the queues of the PF */
15178 for_each_eth_queue(bp, i) {
15179 struct bnx2x_fastpath *fp = &bp->fp[i];
15180
15181 /* Set the appropriate Queue object */
15182 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
15183
15184 /* Update the Queue state */
15185 rc = bnx2x_queue_state_change(bp, &q_params);
15186 if (rc) {
15187 BNX2X_ERR("Failed to enable PTP packets\n");
15188 return rc;
15189 }
15190 }
15191
15192 return 0;
15193}
15194
15195int bnx2x_configure_ptp_filters(struct bnx2x *bp)
15196{
15197 int port = BP_PORT(bp);
15198 int rc;
15199
15200 if (!bp->hwtstamp_ioctl_called)
15201 return 0;
15202
15203 switch (bp->tx_type) {
15204 case HWTSTAMP_TX_ON:
15205 bp->flags |= TX_TIMESTAMPING_EN;
15206 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15207 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
15208 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15209 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
15210 break;
15211 case HWTSTAMP_TX_ONESTEP_SYNC:
15212 BNX2X_ERR("One-step timestamping is not supported\n");
15213 return -ERANGE;
15214 }
15215
15216 switch (bp->rx_filter) {
15217 case HWTSTAMP_FILTER_NONE:
15218 break;
15219 case HWTSTAMP_FILTER_ALL:
15220 case HWTSTAMP_FILTER_SOME:
15221 bp->rx_filter = HWTSTAMP_FILTER_NONE;
15222 break;
15223 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
15224 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
15225 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
15226 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
15227 /* Initialize PTP detection for UDP/IPv4 events */
15228 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15229 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
15230 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15231 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
15232 break;
15233 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
15234 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
15235 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
15236 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
15237 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15238 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15239 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
15240 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15241 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
15242 break;
15243 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
15244 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
15245 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
15246 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
15247 /* Initialize PTP detection L2 events */
15248 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15249 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
15250 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15251 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
15252
15253 break;
15254 case HWTSTAMP_FILTER_PTP_V2_EVENT:
15255 case HWTSTAMP_FILTER_PTP_V2_SYNC:
15256 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
15257 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
15258 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15259 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15260 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
15261 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15262 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
15263 break;
15264 }
15265
15266 /* Indicate to FW that this PF expects recorded PTP packets */
15267 rc = bnx2x_enable_ptp_packets(bp);
15268 if (rc)
15269 return rc;
15270
15271 /* Enable sending PTP packets to host */
15272 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15273 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
15274
15275 return 0;
15276}
15277
15278static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
15279{
15280 struct hwtstamp_config config;
15281 int rc;
15282
15283 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
15284
15285 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
15286 return -EFAULT;
15287
15288 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
15289 config.tx_type, config.rx_filter);
15290
15291 if (config.flags) {
15292 BNX2X_ERR("config.flags is reserved for future use\n");
15293 return -EINVAL;
15294 }
15295
15296 bp->hwtstamp_ioctl_called = 1;
15297 bp->tx_type = config.tx_type;
15298 bp->rx_filter = config.rx_filter;
15299
15300 rc = bnx2x_configure_ptp_filters(bp);
15301 if (rc)
15302 return rc;
15303
15304 config.rx_filter = bp->rx_filter;
15305
15306 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
15307 -EFAULT : 0;
15308}
15309
bf27c353 15310/* Configures HW for PTP */
eeed018c
MK		 15311static int bnx2x_configure_ptp(struct bnx2x *bp)
15312{
15313 int rc, port = BP_PORT(bp);
15314 u32 wb_data[2];
15315
15316 /* Reset PTP event detection rules - will be configured in the IOCTL */
15317 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15318 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
15319 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15320 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
15321 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15322 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
15323 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15324 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
15325
15326 /* Disable PTP packets to host - will be configured in the IOCTL*/
15327 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15328 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
15329
15330 /* Enable the PTP feature */
15331 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
15332 NIG_REG_P0_PTP_EN, 0x3F);
15333
15334 /* Enable the free-running counter */
15335 wb_data[0] = 0;
15336 wb_data[1] = 0;
15337 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
15338
15339 /* Reset drift register (offset register is not reset) */
15340 rc = bnx2x_send_reset_timesync_ramrod(bp);
15341 if (rc) {
15342 BNX2X_ERR("Failed to reset PHC drift register\n");
15343 return -EFAULT;
15344 }
15345
15346 /* Reset possibly old timestamps */
15347 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15348 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15349 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15350 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15351
15352 return 0;
15353}
15354
15355/* Called during load, to initialize PTP-related stuff */
15356void bnx2x_init_ptp(struct bnx2x *bp)
15357{
15358 int rc;
15359
15360 /* Configure PTP in HW */
15361 rc = bnx2x_configure_ptp(bp);
15362 if (rc) {
15363 BNX2X_ERR("Stopping PTP initialization\n");
15364 return;
15365 }
15366
15367 /* Init work queue for Tx timestamping */
15368 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
15369
15370 /* Init cyclecounter and timecounter. This is done only in the first
15371 * load. If done in every load, PTP application will fail when doing
15372 * unload / load (e.g. MTU change) while it is running.
15373 */
15374 if (!bp->timecounter_init_done) {
15375 bnx2x_init_cyclecounter(bp);
15376 timecounter_init(&bp->timecounter, &bp->cyclecounter,
15377 ktime_to_ns(ktime_get_real()));
15378 bp->timecounter_init_done = 1;
15379 }
15380
15381 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
15382}
Linux kernel - Deliverables
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