Commit | Line | Data |
---|---|---|
34f80b04 | 1 | /* bnx2x_main.c: Broadcom Everest network driver. |
a2fbb9ea | 2 | * |
85b26ea1 | 3 | * Copyright (c) 2007-2012 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
ca00392c | 13 | * Slowpath and fastpath rework by Vladislav Zolotarov |
c14423fe | 14 | * Statistics and Link management by Yitchak Gertner |
a2fbb9ea ET |
15 | * |
16 | */ | |
17 | ||
f1deab50 JP |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
19 | ||
a2fbb9ea ET |
20 | #include <linux/module.h> |
21 | #include <linux/moduleparam.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/device.h> /* for dev_info() */ | |
24 | #include <linux/timer.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/slab.h> | |
a2fbb9ea ET |
28 | #include <linux/interrupt.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/bitops.h> | |
36 | #include <linux/irq.h> | |
37 | #include <linux/delay.h> | |
38 | #include <asm/byteorder.h> | |
39 | #include <linux/time.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/mii.h> | |
0c6671b0 | 42 | #include <linux/if_vlan.h> |
a2fbb9ea | 43 | #include <net/ip.h> |
619c5cb6 | 44 | #include <net/ipv6.h> |
a2fbb9ea ET |
45 | #include <net/tcp.h> |
46 | #include <net/checksum.h> | |
34f80b04 | 47 | #include <net/ip6_checksum.h> |
a2fbb9ea ET |
48 | #include <linux/workqueue.h> |
49 | #include <linux/crc32.h> | |
34f80b04 | 50 | #include <linux/crc32c.h> |
a2fbb9ea ET |
51 | #include <linux/prefetch.h> |
52 | #include <linux/zlib.h> | |
a2fbb9ea | 53 | #include <linux/io.h> |
452427b0 | 54 | #include <linux/semaphore.h> |
45229b42 | 55 | #include <linux/stringify.h> |
7ab24bfd | 56 | #include <linux/vmalloc.h> |
a2fbb9ea | 57 | |
a2fbb9ea ET |
58 | #include "bnx2x.h" |
59 | #include "bnx2x_init.h" | |
94a78b79 | 60 | #include "bnx2x_init_ops.h" |
9f6c9258 | 61 | #include "bnx2x_cmn.h" |
e4901dde | 62 | #include "bnx2x_dcb.h" |
042181f5 | 63 | #include "bnx2x_sp.h" |
a2fbb9ea | 64 | |
94a78b79 VZ |
65 | #include <linux/firmware.h> |
66 | #include "bnx2x_fw_file_hdr.h" | |
67 | /* FW files */ | |
45229b42 BH |
68 | #define FW_FILE_VERSION \ |
69 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ | |
70 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ | |
71 | __stringify(BCM_5710_FW_REVISION_VERSION) "." \ | |
72 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) | |
560131f3 DK |
73 | #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" |
74 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" | |
f2e0899f | 75 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
94a78b79 | 76 | |
34f80b04 EG |
77 | /* Time in jiffies before concluding the transmitter is hung */ |
78 | #define TX_TIMEOUT (5*HZ) | |
a2fbb9ea | 79 | |
53a10565 | 80 | static char version[] __devinitdata = |
619c5cb6 | 81 | "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " |
a2fbb9ea ET |
82 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
83 | ||
24e3fcef | 84 | MODULE_AUTHOR("Eliezer Tamir"); |
f2e0899f | 85 | MODULE_DESCRIPTION("Broadcom NetXtreme II " |
619c5cb6 VZ |
86 | "BCM57710/57711/57711E/" |
87 | "57712/57712_MF/57800/57800_MF/57810/57810_MF/" | |
88 | "57840/57840_MF Driver"); | |
a2fbb9ea ET |
89 | MODULE_LICENSE("GPL"); |
90 | MODULE_VERSION(DRV_MODULE_VERSION); | |
45229b42 BH |
91 | MODULE_FIRMWARE(FW_FILE_NAME_E1); |
92 | MODULE_FIRMWARE(FW_FILE_NAME_E1H); | |
f2e0899f | 93 | MODULE_FIRMWARE(FW_FILE_NAME_E2); |
a2fbb9ea | 94 | |
ca00392c | 95 | |
d6214d7a | 96 | int num_queues; |
54b9ddaa | 97 | module_param(num_queues, int, 0); |
96305234 DK |
98 | MODULE_PARM_DESC(num_queues, |
99 | " Set number of queues (default is as a number of CPUs)"); | |
555f6c78 | 100 | |
19680c48 | 101 | static int disable_tpa; |
19680c48 | 102 | module_param(disable_tpa, int, 0); |
9898f86d | 103 | MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); |
8badd27a | 104 | |
9ee3d37b DK |
105 | #define INT_MODE_INTx 1 |
106 | #define INT_MODE_MSI 2 | |
8badd27a EG |
107 | static int int_mode; |
108 | module_param(int_mode, int, 0); | |
619c5cb6 | 109 | MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " |
cdaa7cb8 | 110 | "(1 INT#x; 2 MSI)"); |
8badd27a | 111 | |
a18f5128 EG |
112 | static int dropless_fc; |
113 | module_param(dropless_fc, int, 0); | |
114 | MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); | |
115 | ||
8d5726c4 EG |
116 | static int mrrs = -1; |
117 | module_param(mrrs, int, 0); | |
118 | MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); | |
119 | ||
9898f86d | 120 | static int debug; |
a2fbb9ea | 121 | module_param(debug, int, 0); |
9898f86d EG |
122 | MODULE_PARM_DESC(debug, " Default debug msglevel"); |
123 | ||
a2fbb9ea | 124 | |
619c5cb6 VZ |
125 | |
126 | struct workqueue_struct *bnx2x_wq; | |
ec6ba945 | 127 | |
a2fbb9ea ET |
128 | enum bnx2x_board_type { |
129 | BCM57710 = 0, | |
619c5cb6 VZ |
130 | BCM57711, |
131 | BCM57711E, | |
132 | BCM57712, | |
133 | BCM57712_MF, | |
134 | BCM57800, | |
135 | BCM57800_MF, | |
136 | BCM57810, | |
137 | BCM57810_MF, | |
138 | BCM57840, | |
7e8e02df BW |
139 | BCM57840_MF, |
140 | BCM57811, | |
141 | BCM57811_MF | |
a2fbb9ea ET |
142 | }; |
143 | ||
34f80b04 | 144 | /* indexed by board_type, above */ |
53a10565 | 145 | static struct { |
a2fbb9ea ET |
146 | char *name; |
147 | } board_info[] __devinitdata = { | |
619c5cb6 VZ |
148 | { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, |
149 | { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, | |
150 | { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, | |
151 | { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, | |
152 | { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, | |
153 | { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, | |
154 | { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, | |
155 | { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, | |
156 | { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, | |
157 | { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, | |
7e8e02df BW |
158 | { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"}, |
159 | { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet"}, | |
160 | { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function"}, | |
a2fbb9ea ET |
161 | }; |
162 | ||
619c5cb6 VZ |
163 | #ifndef PCI_DEVICE_ID_NX2_57710 |
164 | #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 | |
165 | #endif | |
166 | #ifndef PCI_DEVICE_ID_NX2_57711 | |
167 | #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 | |
168 | #endif | |
169 | #ifndef PCI_DEVICE_ID_NX2_57711E | |
170 | #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E | |
171 | #endif | |
172 | #ifndef PCI_DEVICE_ID_NX2_57712 | |
173 | #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 | |
174 | #endif | |
175 | #ifndef PCI_DEVICE_ID_NX2_57712_MF | |
176 | #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF | |
177 | #endif | |
178 | #ifndef PCI_DEVICE_ID_NX2_57800 | |
179 | #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 | |
180 | #endif | |
181 | #ifndef PCI_DEVICE_ID_NX2_57800_MF | |
182 | #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF | |
183 | #endif | |
184 | #ifndef PCI_DEVICE_ID_NX2_57810 | |
185 | #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 | |
186 | #endif | |
187 | #ifndef PCI_DEVICE_ID_NX2_57810_MF | |
188 | #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF | |
189 | #endif | |
190 | #ifndef PCI_DEVICE_ID_NX2_57840 | |
191 | #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 | |
192 | #endif | |
193 | #ifndef PCI_DEVICE_ID_NX2_57840_MF | |
194 | #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF | |
195 | #endif | |
7e8e02df BW |
196 | #ifndef PCI_DEVICE_ID_NX2_57811 |
197 | #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 | |
198 | #endif | |
199 | #ifndef PCI_DEVICE_ID_NX2_57811_MF | |
200 | #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF | |
201 | #endif | |
a3aa1884 | 202 | static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { |
e4ed7113 EG |
203 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, |
204 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, | |
205 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, | |
f2e0899f | 206 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, |
619c5cb6 VZ |
207 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, |
208 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, | |
209 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, | |
210 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, | |
211 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, | |
212 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, | |
213 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, | |
7e8e02df BW |
214 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, |
215 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, | |
a2fbb9ea ET |
216 | { 0 } |
217 | }; | |
218 | ||
219 | MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); | |
220 | ||
452427b0 YM |
221 | /* Global resources for unloading a previously loaded device */ |
222 | #define BNX2X_PREV_WAIT_NEEDED 1 | |
223 | static DEFINE_SEMAPHORE(bnx2x_prev_sem); | |
224 | static LIST_HEAD(bnx2x_prev_list); | |
a2fbb9ea ET |
225 | /**************************************************************************** |
226 | * General service functions | |
227 | ****************************************************************************/ | |
228 | ||
619c5cb6 VZ |
229 | static inline void __storm_memset_dma_mapping(struct bnx2x *bp, |
230 | u32 addr, dma_addr_t mapping) | |
231 | { | |
232 | REG_WR(bp, addr, U64_LO(mapping)); | |
233 | REG_WR(bp, addr + 4, U64_HI(mapping)); | |
234 | } | |
235 | ||
236 | static inline void storm_memset_spq_addr(struct bnx2x *bp, | |
237 | dma_addr_t mapping, u16 abs_fid) | |
238 | { | |
239 | u32 addr = XSEM_REG_FAST_MEMORY + | |
240 | XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); | |
241 | ||
242 | __storm_memset_dma_mapping(bp, addr, mapping); | |
243 | } | |
244 | ||
245 | static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, | |
246 | u16 pf_id) | |
523224a3 | 247 | { |
619c5cb6 VZ |
248 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), |
249 | pf_id); | |
250 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), | |
251 | pf_id); | |
252 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), | |
253 | pf_id); | |
254 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), | |
255 | pf_id); | |
523224a3 DK |
256 | } |
257 | ||
619c5cb6 VZ |
258 | static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, |
259 | u8 enable) | |
260 | { | |
261 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), | |
262 | enable); | |
263 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), | |
264 | enable); | |
265 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), | |
266 | enable); | |
267 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), | |
268 | enable); | |
269 | } | |
523224a3 DK |
270 | |
271 | static inline void storm_memset_eq_data(struct bnx2x *bp, | |
272 | struct event_ring_data *eq_data, | |
273 | u16 pfid) | |
274 | { | |
275 | size_t size = sizeof(struct event_ring_data); | |
276 | ||
277 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); | |
278 | ||
279 | __storm_memset_struct(bp, addr, size, (u32 *)eq_data); | |
280 | } | |
281 | ||
282 | static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, | |
283 | u16 pfid) | |
284 | { | |
285 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); | |
286 | REG_WR16(bp, addr, eq_prod); | |
287 | } | |
288 | ||
a2fbb9ea ET |
289 | /* used only at init |
290 | * locking is done by mcp | |
291 | */ | |
8d96286a | 292 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) |
a2fbb9ea ET |
293 | { |
294 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
295 | pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); | |
296 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
297 | PCICFG_VENDOR_ID_OFFSET); | |
298 | } | |
299 | ||
a2fbb9ea ET |
300 | static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) |
301 | { | |
302 | u32 val; | |
303 | ||
304 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
305 | pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); | |
306 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
307 | PCICFG_VENDOR_ID_OFFSET); | |
308 | ||
309 | return val; | |
310 | } | |
a2fbb9ea | 311 | |
f2e0899f DK |
312 | #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" |
313 | #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" | |
314 | #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" | |
315 | #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" | |
316 | #define DMAE_DP_DST_NONE "dst_addr [none]" | |
317 | ||
f2e0899f | 318 | |
a2fbb9ea | 319 | /* copy command into DMAE command memory and set DMAE command go */ |
6c719d00 | 320 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) |
a2fbb9ea ET |
321 | { |
322 | u32 cmd_offset; | |
323 | int i; | |
324 | ||
325 | cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); | |
326 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { | |
327 | REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
a2fbb9ea ET |
328 | } |
329 | REG_WR(bp, dmae_reg_go_c[idx], 1); | |
330 | } | |
331 | ||
f2e0899f | 332 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) |
a2fbb9ea | 333 | { |
f2e0899f DK |
334 | return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | |
335 | DMAE_CMD_C_ENABLE); | |
336 | } | |
ad8d3948 | 337 | |
f2e0899f DK |
338 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) |
339 | { | |
340 | return opcode & ~DMAE_CMD_SRC_RESET; | |
341 | } | |
ad8d3948 | 342 | |
f2e0899f DK |
343 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
344 | bool with_comp, u8 comp_type) | |
345 | { | |
346 | u32 opcode = 0; | |
347 | ||
348 | opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | | |
349 | (dst_type << DMAE_COMMAND_DST_SHIFT)); | |
ad8d3948 | 350 | |
f2e0899f DK |
351 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
352 | ||
353 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); | |
3395a033 DK |
354 | opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | |
355 | (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); | |
f2e0899f | 356 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); |
a2fbb9ea | 357 | |
a2fbb9ea | 358 | #ifdef __BIG_ENDIAN |
f2e0899f | 359 | opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; |
a2fbb9ea | 360 | #else |
f2e0899f | 361 | opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; |
a2fbb9ea | 362 | #endif |
f2e0899f DK |
363 | if (with_comp) |
364 | opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); | |
365 | return opcode; | |
366 | } | |
367 | ||
8d96286a | 368 | static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, |
369 | struct dmae_command *dmae, | |
370 | u8 src_type, u8 dst_type) | |
f2e0899f DK |
371 | { |
372 | memset(dmae, 0, sizeof(struct dmae_command)); | |
373 | ||
374 | /* set the opcode */ | |
375 | dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, | |
376 | true, DMAE_COMP_PCI); | |
377 | ||
378 | /* fill in the completion parameters */ | |
379 | dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); | |
380 | dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); | |
381 | dmae->comp_val = DMAE_COMP_VAL; | |
382 | } | |
383 | ||
384 | /* issue a dmae command over the init-channel and wailt for completion */ | |
8d96286a | 385 | static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, |
386 | struct dmae_command *dmae) | |
f2e0899f DK |
387 | { |
388 | u32 *wb_comp = bnx2x_sp(bp, wb_comp); | |
5e374b5a | 389 | int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; |
f2e0899f DK |
390 | int rc = 0; |
391 | ||
619c5cb6 VZ |
392 | /* |
393 | * Lock the dmae channel. Disable BHs to prevent a dead-lock | |
394 | * as long as this code is called both from syscall context and | |
395 | * from ndo_set_rx_mode() flow that may be called from BH. | |
396 | */ | |
6e30dd4e | 397 | spin_lock_bh(&bp->dmae_lock); |
5ff7b6d4 | 398 | |
f2e0899f | 399 | /* reset completion */ |
a2fbb9ea ET |
400 | *wb_comp = 0; |
401 | ||
f2e0899f DK |
402 | /* post the command on the channel used for initializations */ |
403 | bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); | |
a2fbb9ea | 404 | |
f2e0899f | 405 | /* wait for completion */ |
a2fbb9ea | 406 | udelay(5); |
f2e0899f | 407 | while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { |
ad8d3948 | 408 | |
95c6c616 AE |
409 | if (!cnt || |
410 | (bp->recovery_state != BNX2X_RECOVERY_DONE && | |
411 | bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
c3eefaf6 | 412 | BNX2X_ERR("DMAE timeout!\n"); |
f2e0899f DK |
413 | rc = DMAE_TIMEOUT; |
414 | goto unlock; | |
a2fbb9ea | 415 | } |
ad8d3948 | 416 | cnt--; |
f2e0899f | 417 | udelay(50); |
a2fbb9ea | 418 | } |
f2e0899f DK |
419 | if (*wb_comp & DMAE_PCI_ERR_FLAG) { |
420 | BNX2X_ERR("DMAE PCI error!\n"); | |
421 | rc = DMAE_PCI_ERROR; | |
422 | } | |
423 | ||
f2e0899f | 424 | unlock: |
6e30dd4e | 425 | spin_unlock_bh(&bp->dmae_lock); |
f2e0899f DK |
426 | return rc; |
427 | } | |
428 | ||
429 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
430 | u32 len32) | |
431 | { | |
432 | struct dmae_command dmae; | |
433 | ||
434 | if (!bp->dmae_ready) { | |
435 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
436 | ||
127a425e AE |
437 | if (CHIP_IS_E1(bp)) |
438 | bnx2x_init_ind_wr(bp, dst_addr, data, len32); | |
439 | else | |
440 | bnx2x_init_str_wr(bp, dst_addr, data, len32); | |
f2e0899f DK |
441 | return; |
442 | } | |
443 | ||
444 | /* set opcode and fixed command fields */ | |
445 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); | |
446 | ||
447 | /* fill in addresses and len */ | |
448 | dmae.src_addr_lo = U64_LO(dma_addr); | |
449 | dmae.src_addr_hi = U64_HI(dma_addr); | |
450 | dmae.dst_addr_lo = dst_addr >> 2; | |
451 | dmae.dst_addr_hi = 0; | |
452 | dmae.len = len32; | |
453 | ||
f2e0899f DK |
454 | /* issue the command and wait for completion */ |
455 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
a2fbb9ea ET |
456 | } |
457 | ||
c18487ee | 458 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) |
a2fbb9ea | 459 | { |
5ff7b6d4 | 460 | struct dmae_command dmae; |
ad8d3948 EG |
461 | |
462 | if (!bp->dmae_ready) { | |
463 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
464 | int i; | |
465 | ||
51c1a580 | 466 | if (CHIP_IS_E1(bp)) |
127a425e AE |
467 | for (i = 0; i < len32; i++) |
468 | data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); | |
51c1a580 | 469 | else |
127a425e AE |
470 | for (i = 0; i < len32; i++) |
471 | data[i] = REG_RD(bp, src_addr + i*4); | |
472 | ||
ad8d3948 EG |
473 | return; |
474 | } | |
475 | ||
f2e0899f DK |
476 | /* set opcode and fixed command fields */ |
477 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); | |
a2fbb9ea | 478 | |
f2e0899f | 479 | /* fill in addresses and len */ |
5ff7b6d4 EG |
480 | dmae.src_addr_lo = src_addr >> 2; |
481 | dmae.src_addr_hi = 0; | |
482 | dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); | |
483 | dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); | |
484 | dmae.len = len32; | |
ad8d3948 | 485 | |
f2e0899f DK |
486 | /* issue the command and wait for completion */ |
487 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
ad8d3948 EG |
488 | } |
489 | ||
8d96286a | 490 | static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
491 | u32 addr, u32 len) | |
573f2035 | 492 | { |
02e3c6cb | 493 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); |
573f2035 EG |
494 | int offset = 0; |
495 | ||
02e3c6cb | 496 | while (len > dmae_wr_max) { |
573f2035 | 497 | bnx2x_write_dmae(bp, phys_addr + offset, |
02e3c6cb VZ |
498 | addr + offset, dmae_wr_max); |
499 | offset += dmae_wr_max * 4; | |
500 | len -= dmae_wr_max; | |
573f2035 EG |
501 | } |
502 | ||
503 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); | |
504 | } | |
505 | ||
a2fbb9ea ET |
506 | static int bnx2x_mc_assert(struct bnx2x *bp) |
507 | { | |
a2fbb9ea | 508 | char last_idx; |
34f80b04 EG |
509 | int i, rc = 0; |
510 | u32 row0, row1, row2, row3; | |
511 | ||
512 | /* XSTORM */ | |
513 | last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + | |
514 | XSTORM_ASSERT_LIST_INDEX_OFFSET); | |
515 | if (last_idx) | |
516 | BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
517 | ||
518 | /* print the asserts */ | |
519 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
520 | ||
521 | row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
522 | XSTORM_ASSERT_LIST_OFFSET(i)); | |
523 | row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
524 | XSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
525 | row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
526 | XSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
527 | row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
528 | XSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
529 | ||
530 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 531 | BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
532 | i, row3, row2, row1, row0); |
533 | rc++; | |
534 | } else { | |
535 | break; | |
536 | } | |
537 | } | |
538 | ||
539 | /* TSTORM */ | |
540 | last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + | |
541 | TSTORM_ASSERT_LIST_INDEX_OFFSET); | |
542 | if (last_idx) | |
543 | BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
544 | ||
545 | /* print the asserts */ | |
546 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
547 | ||
548 | row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
549 | TSTORM_ASSERT_LIST_OFFSET(i)); | |
550 | row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
551 | TSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
552 | row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
553 | TSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
554 | row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
555 | TSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
556 | ||
557 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 558 | BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
559 | i, row3, row2, row1, row0); |
560 | rc++; | |
561 | } else { | |
562 | break; | |
563 | } | |
564 | } | |
565 | ||
566 | /* CSTORM */ | |
567 | last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + | |
568 | CSTORM_ASSERT_LIST_INDEX_OFFSET); | |
569 | if (last_idx) | |
570 | BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
571 | ||
572 | /* print the asserts */ | |
573 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
574 | ||
575 | row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
576 | CSTORM_ASSERT_LIST_OFFSET(i)); | |
577 | row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
578 | CSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
579 | row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
580 | CSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
581 | row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
582 | CSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
583 | ||
584 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 585 | BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
586 | i, row3, row2, row1, row0); |
587 | rc++; | |
588 | } else { | |
589 | break; | |
590 | } | |
591 | } | |
592 | ||
593 | /* USTORM */ | |
594 | last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + | |
595 | USTORM_ASSERT_LIST_INDEX_OFFSET); | |
596 | if (last_idx) | |
597 | BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
598 | ||
599 | /* print the asserts */ | |
600 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
601 | ||
602 | row0 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
603 | USTORM_ASSERT_LIST_OFFSET(i)); | |
604 | row1 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
605 | USTORM_ASSERT_LIST_OFFSET(i) + 4); | |
606 | row2 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
607 | USTORM_ASSERT_LIST_OFFSET(i) + 8); | |
608 | row3 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
609 | USTORM_ASSERT_LIST_OFFSET(i) + 12); | |
610 | ||
611 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 612 | BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
613 | i, row3, row2, row1, row0); |
614 | rc++; | |
615 | } else { | |
616 | break; | |
a2fbb9ea ET |
617 | } |
618 | } | |
34f80b04 | 619 | |
a2fbb9ea ET |
620 | return rc; |
621 | } | |
c14423fe | 622 | |
7a25cc73 | 623 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) |
a2fbb9ea | 624 | { |
7a25cc73 | 625 | u32 addr, val; |
a2fbb9ea | 626 | u32 mark, offset; |
4781bfad | 627 | __be32 data[9]; |
a2fbb9ea | 628 | int word; |
f2e0899f | 629 | u32 trace_shmem_base; |
2145a920 VZ |
630 | if (BP_NOMCP(bp)) { |
631 | BNX2X_ERR("NO MCP - can not dump\n"); | |
632 | return; | |
633 | } | |
7a25cc73 DK |
634 | netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", |
635 | (bp->common.bc_ver & 0xff0000) >> 16, | |
636 | (bp->common.bc_ver & 0xff00) >> 8, | |
637 | (bp->common.bc_ver & 0xff)); | |
638 | ||
639 | val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); | |
640 | if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) | |
51c1a580 | 641 | BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); |
cdaa7cb8 | 642 | |
f2e0899f DK |
643 | if (BP_PATH(bp) == 0) |
644 | trace_shmem_base = bp->common.shmem_base; | |
645 | else | |
646 | trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); | |
de128804 DK |
647 | addr = trace_shmem_base - 0x800; |
648 | ||
649 | /* validate TRCB signature */ | |
650 | mark = REG_RD(bp, addr); | |
651 | if (mark != MFW_TRACE_SIGNATURE) { | |
652 | BNX2X_ERR("Trace buffer signature is missing."); | |
653 | return ; | |
654 | } | |
655 | ||
656 | /* read cyclic buffer pointer */ | |
657 | addr += 4; | |
cdaa7cb8 | 658 | mark = REG_RD(bp, addr); |
f2e0899f DK |
659 | mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) |
660 | + ((mark + 0x3) & ~0x3) - 0x08000000; | |
7a25cc73 | 661 | printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); |
a2fbb9ea | 662 | |
7a25cc73 | 663 | printk("%s", lvl); |
f2e0899f | 664 | for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { |
a2fbb9ea | 665 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 666 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 667 | data[8] = 0x0; |
7995c64e | 668 | pr_cont("%s", (char *)data); |
a2fbb9ea | 669 | } |
cdaa7cb8 | 670 | for (offset = addr + 4; offset <= mark; offset += 0x8*4) { |
a2fbb9ea | 671 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 672 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 673 | data[8] = 0x0; |
7995c64e | 674 | pr_cont("%s", (char *)data); |
a2fbb9ea | 675 | } |
7a25cc73 DK |
676 | printk("%s" "end of fw dump\n", lvl); |
677 | } | |
678 | ||
679 | static inline void bnx2x_fw_dump(struct bnx2x *bp) | |
680 | { | |
681 | bnx2x_fw_dump_lvl(bp, KERN_ERR); | |
a2fbb9ea ET |
682 | } |
683 | ||
6c719d00 | 684 | void bnx2x_panic_dump(struct bnx2x *bp) |
a2fbb9ea ET |
685 | { |
686 | int i; | |
523224a3 DK |
687 | u16 j; |
688 | struct hc_sp_status_block_data sp_sb_data; | |
689 | int func = BP_FUNC(bp); | |
690 | #ifdef BNX2X_STOP_ON_ERROR | |
691 | u16 start = 0, end = 0; | |
6383c0b3 | 692 | u8 cos; |
523224a3 | 693 | #endif |
a2fbb9ea | 694 | |
66e855f3 | 695 | bp->stats_state = STATS_STATE_DISABLED; |
7a752993 | 696 | bp->eth_stats.unrecoverable_error++; |
66e855f3 YG |
697 | DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); |
698 | ||
a2fbb9ea ET |
699 | BNX2X_ERR("begin crash dump -----------------\n"); |
700 | ||
8440d2b6 EG |
701 | /* Indices */ |
702 | /* Common */ | |
51c1a580 | 703 | BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", |
619c5cb6 VZ |
704 | bp->def_idx, bp->def_att_idx, bp->attn_state, |
705 | bp->spq_prod_idx, bp->stats_counter); | |
523224a3 DK |
706 | BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", |
707 | bp->def_status_blk->atten_status_block.attn_bits, | |
708 | bp->def_status_blk->atten_status_block.attn_bits_ack, | |
709 | bp->def_status_blk->atten_status_block.status_block_id, | |
710 | bp->def_status_blk->atten_status_block.attn_bits_index); | |
711 | BNX2X_ERR(" def ("); | |
712 | for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) | |
713 | pr_cont("0x%x%s", | |
f1deab50 JP |
714 | bp->def_status_blk->sp_sb.index_values[i], |
715 | (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); | |
523224a3 DK |
716 | |
717 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
718 | *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
719 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
720 | i*sizeof(u32)); | |
721 | ||
f1deab50 | 722 | pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", |
523224a3 DK |
723 | sp_sb_data.igu_sb_id, |
724 | sp_sb_data.igu_seg_id, | |
725 | sp_sb_data.p_func.pf_id, | |
726 | sp_sb_data.p_func.vnic_id, | |
727 | sp_sb_data.p_func.vf_id, | |
619c5cb6 VZ |
728 | sp_sb_data.p_func.vf_valid, |
729 | sp_sb_data.state); | |
523224a3 | 730 | |
8440d2b6 | 731 | |
ec6ba945 | 732 | for_each_eth_queue(bp, i) { |
a2fbb9ea | 733 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
523224a3 | 734 | int loop; |
f2e0899f | 735 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
736 | struct hc_status_block_data_e1x sb_data_e1x; |
737 | struct hc_status_block_sm *hc_sm_p = | |
619c5cb6 VZ |
738 | CHIP_IS_E1x(bp) ? |
739 | sb_data_e1x.common.state_machine : | |
740 | sb_data_e2.common.state_machine; | |
523224a3 | 741 | struct hc_index_data *hc_index_p = |
619c5cb6 VZ |
742 | CHIP_IS_E1x(bp) ? |
743 | sb_data_e1x.index_data : | |
744 | sb_data_e2.index_data; | |
6383c0b3 | 745 | u8 data_size, cos; |
523224a3 | 746 | u32 *sb_data_p; |
6383c0b3 | 747 | struct bnx2x_fp_txdata txdata; |
523224a3 DK |
748 | |
749 | /* Rx */ | |
51c1a580 | 750 | BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", |
8440d2b6 | 751 | i, fp->rx_bd_prod, fp->rx_bd_cons, |
523224a3 | 752 | fp->rx_comp_prod, |
66e855f3 | 753 | fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); |
51c1a580 | 754 | BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", |
8440d2b6 | 755 | fp->rx_sge_prod, fp->last_max_sge, |
523224a3 | 756 | le16_to_cpu(fp->fp_hc_idx)); |
a2fbb9ea | 757 | |
523224a3 | 758 | /* Tx */ |
6383c0b3 AE |
759 | for_each_cos_in_tx_queue(fp, cos) |
760 | { | |
761 | txdata = fp->txdata[cos]; | |
51c1a580 | 762 | BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", |
6383c0b3 AE |
763 | i, txdata.tx_pkt_prod, |
764 | txdata.tx_pkt_cons, txdata.tx_bd_prod, | |
765 | txdata.tx_bd_cons, | |
766 | le16_to_cpu(*txdata.tx_cons_sb)); | |
767 | } | |
523224a3 | 768 | |
619c5cb6 VZ |
769 | loop = CHIP_IS_E1x(bp) ? |
770 | HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; | |
523224a3 DK |
771 | |
772 | /* host sb data */ | |
773 | ||
ec6ba945 VZ |
774 | #ifdef BCM_CNIC |
775 | if (IS_FCOE_FP(fp)) | |
776 | continue; | |
777 | #endif | |
523224a3 DK |
778 | BNX2X_ERR(" run indexes ("); |
779 | for (j = 0; j < HC_SB_MAX_SM; j++) | |
780 | pr_cont("0x%x%s", | |
781 | fp->sb_running_index[j], | |
782 | (j == HC_SB_MAX_SM - 1) ? ")" : " "); | |
783 | ||
784 | BNX2X_ERR(" indexes ("); | |
785 | for (j = 0; j < loop; j++) | |
786 | pr_cont("0x%x%s", | |
787 | fp->sb_index_values[j], | |
788 | (j == loop - 1) ? ")" : " "); | |
789 | /* fw sb data */ | |
619c5cb6 VZ |
790 | data_size = CHIP_IS_E1x(bp) ? |
791 | sizeof(struct hc_status_block_data_e1x) : | |
792 | sizeof(struct hc_status_block_data_e2); | |
523224a3 | 793 | data_size /= sizeof(u32); |
619c5cb6 VZ |
794 | sb_data_p = CHIP_IS_E1x(bp) ? |
795 | (u32 *)&sb_data_e1x : | |
796 | (u32 *)&sb_data_e2; | |
523224a3 DK |
797 | /* copy sb data in here */ |
798 | for (j = 0; j < data_size; j++) | |
799 | *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
800 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + | |
801 | j * sizeof(u32)); | |
802 | ||
619c5cb6 | 803 | if (!CHIP_IS_E1x(bp)) { |
51c1a580 | 804 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
805 | sb_data_e2.common.p_func.pf_id, |
806 | sb_data_e2.common.p_func.vf_id, | |
807 | sb_data_e2.common.p_func.vf_valid, | |
808 | sb_data_e2.common.p_func.vnic_id, | |
619c5cb6 VZ |
809 | sb_data_e2.common.same_igu_sb_1b, |
810 | sb_data_e2.common.state); | |
f2e0899f | 811 | } else { |
51c1a580 | 812 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
813 | sb_data_e1x.common.p_func.pf_id, |
814 | sb_data_e1x.common.p_func.vf_id, | |
815 | sb_data_e1x.common.p_func.vf_valid, | |
816 | sb_data_e1x.common.p_func.vnic_id, | |
619c5cb6 VZ |
817 | sb_data_e1x.common.same_igu_sb_1b, |
818 | sb_data_e1x.common.state); | |
f2e0899f | 819 | } |
523224a3 DK |
820 | |
821 | /* SB_SMs data */ | |
822 | for (j = 0; j < HC_SB_MAX_SM; j++) { | |
51c1a580 MS |
823 | pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", |
824 | j, hc_sm_p[j].__flags, | |
825 | hc_sm_p[j].igu_sb_id, | |
826 | hc_sm_p[j].igu_seg_id, | |
827 | hc_sm_p[j].time_to_expire, | |
828 | hc_sm_p[j].timer_value); | |
523224a3 DK |
829 | } |
830 | ||
831 | /* Indecies data */ | |
832 | for (j = 0; j < loop; j++) { | |
51c1a580 | 833 | pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, |
523224a3 DK |
834 | hc_index_p[j].flags, |
835 | hc_index_p[j].timeout); | |
836 | } | |
8440d2b6 | 837 | } |
a2fbb9ea | 838 | |
523224a3 | 839 | #ifdef BNX2X_STOP_ON_ERROR |
8440d2b6 EG |
840 | /* Rings */ |
841 | /* Rx */ | |
ec6ba945 | 842 | for_each_rx_queue(bp, i) { |
8440d2b6 | 843 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea ET |
844 | |
845 | start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); | |
846 | end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); | |
8440d2b6 | 847 | for (j = start; j != end; j = RX_BD(j + 1)) { |
a2fbb9ea ET |
848 | u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; |
849 | struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; | |
850 | ||
c3eefaf6 | 851 | BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", |
44151acb | 852 | i, j, rx_bd[1], rx_bd[0], sw_bd->data); |
a2fbb9ea ET |
853 | } |
854 | ||
3196a88a EG |
855 | start = RX_SGE(fp->rx_sge_prod); |
856 | end = RX_SGE(fp->last_max_sge); | |
8440d2b6 | 857 | for (j = start; j != end; j = RX_SGE(j + 1)) { |
7a9b2557 VZ |
858 | u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; |
859 | struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; | |
860 | ||
c3eefaf6 EG |
861 | BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", |
862 | i, j, rx_sge[1], rx_sge[0], sw_page->page); | |
7a9b2557 VZ |
863 | } |
864 | ||
a2fbb9ea ET |
865 | start = RCQ_BD(fp->rx_comp_cons - 10); |
866 | end = RCQ_BD(fp->rx_comp_cons + 503); | |
8440d2b6 | 867 | for (j = start; j != end; j = RCQ_BD(j + 1)) { |
a2fbb9ea ET |
868 | u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; |
869 | ||
c3eefaf6 EG |
870 | BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", |
871 | i, j, cqe[0], cqe[1], cqe[2], cqe[3]); | |
a2fbb9ea ET |
872 | } |
873 | } | |
874 | ||
8440d2b6 | 875 | /* Tx */ |
ec6ba945 | 876 | for_each_tx_queue(bp, i) { |
8440d2b6 | 877 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
6383c0b3 AE |
878 | for_each_cos_in_tx_queue(fp, cos) { |
879 | struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; | |
880 | ||
881 | start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); | |
882 | end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); | |
883 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
884 | struct sw_tx_bd *sw_bd = | |
885 | &txdata->tx_buf_ring[j]; | |
886 | ||
51c1a580 | 887 | BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", |
6383c0b3 AE |
888 | i, cos, j, sw_bd->skb, |
889 | sw_bd->first_bd); | |
890 | } | |
8440d2b6 | 891 | |
6383c0b3 AE |
892 | start = TX_BD(txdata->tx_bd_cons - 10); |
893 | end = TX_BD(txdata->tx_bd_cons + 254); | |
894 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
895 | u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; | |
8440d2b6 | 896 | |
51c1a580 | 897 | BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", |
6383c0b3 AE |
898 | i, cos, j, tx_bd[0], tx_bd[1], |
899 | tx_bd[2], tx_bd[3]); | |
900 | } | |
8440d2b6 EG |
901 | } |
902 | } | |
523224a3 | 903 | #endif |
34f80b04 | 904 | bnx2x_fw_dump(bp); |
a2fbb9ea ET |
905 | bnx2x_mc_assert(bp); |
906 | BNX2X_ERR("end crash dump -----------------\n"); | |
a2fbb9ea ET |
907 | } |
908 | ||
619c5cb6 VZ |
909 | /* |
910 | * FLR Support for E2 | |
911 | * | |
912 | * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW | |
913 | * initialization. | |
914 | */ | |
915 | #define FLR_WAIT_USEC 10000 /* 10 miliseconds */ | |
89db4ad8 AE |
916 | #define FLR_WAIT_INTERVAL 50 /* usec */ |
917 | #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ | |
619c5cb6 VZ |
918 | |
919 | struct pbf_pN_buf_regs { | |
920 | int pN; | |
921 | u32 init_crd; | |
922 | u32 crd; | |
923 | u32 crd_freed; | |
924 | }; | |
925 | ||
926 | struct pbf_pN_cmd_regs { | |
927 | int pN; | |
928 | u32 lines_occup; | |
929 | u32 lines_freed; | |
930 | }; | |
931 | ||
932 | static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, | |
933 | struct pbf_pN_buf_regs *regs, | |
934 | u32 poll_count) | |
935 | { | |
936 | u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; | |
937 | u32 cur_cnt = poll_count; | |
938 | ||
939 | crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); | |
940 | crd = crd_start = REG_RD(bp, regs->crd); | |
941 | init_crd = REG_RD(bp, regs->init_crd); | |
942 | ||
943 | DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); | |
944 | DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); | |
945 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); | |
946 | ||
947 | while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < | |
948 | (init_crd - crd_start))) { | |
949 | if (cur_cnt--) { | |
89db4ad8 | 950 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
951 | crd = REG_RD(bp, regs->crd); |
952 | crd_freed = REG_RD(bp, regs->crd_freed); | |
953 | } else { | |
954 | DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", | |
955 | regs->pN); | |
956 | DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", | |
957 | regs->pN, crd); | |
958 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", | |
959 | regs->pN, crd_freed); | |
960 | break; | |
961 | } | |
962 | } | |
963 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", | |
89db4ad8 | 964 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
965 | } |
966 | ||
967 | static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, | |
968 | struct pbf_pN_cmd_regs *regs, | |
969 | u32 poll_count) | |
970 | { | |
971 | u32 occup, to_free, freed, freed_start; | |
972 | u32 cur_cnt = poll_count; | |
973 | ||
974 | occup = to_free = REG_RD(bp, regs->lines_occup); | |
975 | freed = freed_start = REG_RD(bp, regs->lines_freed); | |
976 | ||
977 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); | |
978 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); | |
979 | ||
980 | while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { | |
981 | if (cur_cnt--) { | |
89db4ad8 | 982 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
983 | occup = REG_RD(bp, regs->lines_occup); |
984 | freed = REG_RD(bp, regs->lines_freed); | |
985 | } else { | |
986 | DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", | |
987 | regs->pN); | |
988 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", | |
989 | regs->pN, occup); | |
990 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", | |
991 | regs->pN, freed); | |
992 | break; | |
993 | } | |
994 | } | |
995 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", | |
89db4ad8 | 996 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
997 | } |
998 | ||
999 | static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, | |
1000 | u32 expected, u32 poll_count) | |
1001 | { | |
1002 | u32 cur_cnt = poll_count; | |
1003 | u32 val; | |
1004 | ||
1005 | while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) | |
89db4ad8 | 1006 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1007 | |
1008 | return val; | |
1009 | } | |
1010 | ||
1011 | static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, | |
1012 | char *msg, u32 poll_cnt) | |
1013 | { | |
1014 | u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); | |
1015 | if (val != 0) { | |
1016 | BNX2X_ERR("%s usage count=%d\n", msg, val); | |
1017 | return 1; | |
1018 | } | |
1019 | return 0; | |
1020 | } | |
1021 | ||
1022 | static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) | |
1023 | { | |
1024 | /* adjust polling timeout */ | |
1025 | if (CHIP_REV_IS_EMUL(bp)) | |
1026 | return FLR_POLL_CNT * 2000; | |
1027 | ||
1028 | if (CHIP_REV_IS_FPGA(bp)) | |
1029 | return FLR_POLL_CNT * 120; | |
1030 | ||
1031 | return FLR_POLL_CNT; | |
1032 | } | |
1033 | ||
1034 | static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) | |
1035 | { | |
1036 | struct pbf_pN_cmd_regs cmd_regs[] = { | |
1037 | {0, (CHIP_IS_E3B0(bp)) ? | |
1038 | PBF_REG_TQ_OCCUPANCY_Q0 : | |
1039 | PBF_REG_P0_TQ_OCCUPANCY, | |
1040 | (CHIP_IS_E3B0(bp)) ? | |
1041 | PBF_REG_TQ_LINES_FREED_CNT_Q0 : | |
1042 | PBF_REG_P0_TQ_LINES_FREED_CNT}, | |
1043 | {1, (CHIP_IS_E3B0(bp)) ? | |
1044 | PBF_REG_TQ_OCCUPANCY_Q1 : | |
1045 | PBF_REG_P1_TQ_OCCUPANCY, | |
1046 | (CHIP_IS_E3B0(bp)) ? | |
1047 | PBF_REG_TQ_LINES_FREED_CNT_Q1 : | |
1048 | PBF_REG_P1_TQ_LINES_FREED_CNT}, | |
1049 | {4, (CHIP_IS_E3B0(bp)) ? | |
1050 | PBF_REG_TQ_OCCUPANCY_LB_Q : | |
1051 | PBF_REG_P4_TQ_OCCUPANCY, | |
1052 | (CHIP_IS_E3B0(bp)) ? | |
1053 | PBF_REG_TQ_LINES_FREED_CNT_LB_Q : | |
1054 | PBF_REG_P4_TQ_LINES_FREED_CNT} | |
1055 | }; | |
1056 | ||
1057 | struct pbf_pN_buf_regs buf_regs[] = { | |
1058 | {0, (CHIP_IS_E3B0(bp)) ? | |
1059 | PBF_REG_INIT_CRD_Q0 : | |
1060 | PBF_REG_P0_INIT_CRD , | |
1061 | (CHIP_IS_E3B0(bp)) ? | |
1062 | PBF_REG_CREDIT_Q0 : | |
1063 | PBF_REG_P0_CREDIT, | |
1064 | (CHIP_IS_E3B0(bp)) ? | |
1065 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : | |
1066 | PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, | |
1067 | {1, (CHIP_IS_E3B0(bp)) ? | |
1068 | PBF_REG_INIT_CRD_Q1 : | |
1069 | PBF_REG_P1_INIT_CRD, | |
1070 | (CHIP_IS_E3B0(bp)) ? | |
1071 | PBF_REG_CREDIT_Q1 : | |
1072 | PBF_REG_P1_CREDIT, | |
1073 | (CHIP_IS_E3B0(bp)) ? | |
1074 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : | |
1075 | PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, | |
1076 | {4, (CHIP_IS_E3B0(bp)) ? | |
1077 | PBF_REG_INIT_CRD_LB_Q : | |
1078 | PBF_REG_P4_INIT_CRD, | |
1079 | (CHIP_IS_E3B0(bp)) ? | |
1080 | PBF_REG_CREDIT_LB_Q : | |
1081 | PBF_REG_P4_CREDIT, | |
1082 | (CHIP_IS_E3B0(bp)) ? | |
1083 | PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : | |
1084 | PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, | |
1085 | }; | |
1086 | ||
1087 | int i; | |
1088 | ||
1089 | /* Verify the command queues are flushed P0, P1, P4 */ | |
1090 | for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) | |
1091 | bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); | |
1092 | ||
1093 | ||
1094 | /* Verify the transmission buffers are flushed P0, P1, P4 */ | |
1095 | for (i = 0; i < ARRAY_SIZE(buf_regs); i++) | |
1096 | bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); | |
1097 | } | |
1098 | ||
1099 | #define OP_GEN_PARAM(param) \ | |
1100 | (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) | |
1101 | ||
1102 | #define OP_GEN_TYPE(type) \ | |
1103 | (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) | |
1104 | ||
1105 | #define OP_GEN_AGG_VECT(index) \ | |
1106 | (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) | |
1107 | ||
1108 | ||
1109 | static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, | |
1110 | u32 poll_cnt) | |
1111 | { | |
1112 | struct sdm_op_gen op_gen = {0}; | |
1113 | ||
1114 | u32 comp_addr = BAR_CSTRORM_INTMEM + | |
1115 | CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); | |
1116 | int ret = 0; | |
1117 | ||
1118 | if (REG_RD(bp, comp_addr)) { | |
89db4ad8 | 1119 | BNX2X_ERR("Cleanup complete was not 0 before sending\n"); |
619c5cb6 VZ |
1120 | return 1; |
1121 | } | |
1122 | ||
1123 | op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); | |
1124 | op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); | |
1125 | op_gen.command |= OP_GEN_AGG_VECT(clnup_func); | |
1126 | op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; | |
1127 | ||
89db4ad8 | 1128 | DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); |
619c5cb6 VZ |
1129 | REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); |
1130 | ||
1131 | if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { | |
1132 | BNX2X_ERR("FW final cleanup did not succeed\n"); | |
51c1a580 MS |
1133 | DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", |
1134 | (REG_RD(bp, comp_addr))); | |
619c5cb6 VZ |
1135 | ret = 1; |
1136 | } | |
1137 | /* Zero completion for nxt FLR */ | |
1138 | REG_WR(bp, comp_addr, 0); | |
1139 | ||
1140 | return ret; | |
1141 | } | |
1142 | ||
1143 | static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) | |
1144 | { | |
1145 | int pos; | |
1146 | u16 status; | |
1147 | ||
77c98e6a | 1148 | pos = pci_pcie_cap(dev); |
619c5cb6 VZ |
1149 | if (!pos) |
1150 | return false; | |
1151 | ||
1152 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); | |
1153 | return status & PCI_EXP_DEVSTA_TRPND; | |
1154 | } | |
1155 | ||
1156 | /* PF FLR specific routines | |
1157 | */ | |
1158 | static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) | |
1159 | { | |
1160 | ||
1161 | /* wait for CFC PF usage-counter to zero (includes all the VFs) */ | |
1162 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1163 | CFC_REG_NUM_LCIDS_INSIDE_PF, | |
1164 | "CFC PF usage counter timed out", | |
1165 | poll_cnt)) | |
1166 | return 1; | |
1167 | ||
1168 | ||
1169 | /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ | |
1170 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1171 | DORQ_REG_PF_USAGE_CNT, | |
1172 | "DQ PF usage counter timed out", | |
1173 | poll_cnt)) | |
1174 | return 1; | |
1175 | ||
1176 | /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ | |
1177 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1178 | QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), | |
1179 | "QM PF usage counter timed out", | |
1180 | poll_cnt)) | |
1181 | return 1; | |
1182 | ||
1183 | /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ | |
1184 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1185 | TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), | |
1186 | "Timers VNIC usage counter timed out", | |
1187 | poll_cnt)) | |
1188 | return 1; | |
1189 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1190 | TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), | |
1191 | "Timers NUM_SCANS usage counter timed out", | |
1192 | poll_cnt)) | |
1193 | return 1; | |
1194 | ||
1195 | /* Wait DMAE PF usage counter to zero */ | |
1196 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1197 | dmae_reg_go_c[INIT_DMAE_C(bp)], | |
1198 | "DMAE dommand register timed out", | |
1199 | poll_cnt)) | |
1200 | return 1; | |
1201 | ||
1202 | return 0; | |
1203 | } | |
1204 | ||
1205 | static void bnx2x_hw_enable_status(struct bnx2x *bp) | |
1206 | { | |
1207 | u32 val; | |
1208 | ||
1209 | val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); | |
1210 | DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); | |
1211 | ||
1212 | val = REG_RD(bp, PBF_REG_DISABLE_PF); | |
1213 | DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); | |
1214 | ||
1215 | val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); | |
1216 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); | |
1217 | ||
1218 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); | |
1219 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); | |
1220 | ||
1221 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); | |
1222 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); | |
1223 | ||
1224 | val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); | |
1225 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); | |
1226 | ||
1227 | val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); | |
1228 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); | |
1229 | ||
1230 | val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
1231 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", | |
1232 | val); | |
1233 | } | |
1234 | ||
1235 | static int bnx2x_pf_flr_clnup(struct bnx2x *bp) | |
1236 | { | |
1237 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); | |
1238 | ||
1239 | DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); | |
1240 | ||
1241 | /* Re-enable PF target read access */ | |
1242 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
1243 | ||
1244 | /* Poll HW usage counters */ | |
89db4ad8 | 1245 | DP(BNX2X_MSG_SP, "Polling usage counters\n"); |
619c5cb6 VZ |
1246 | if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) |
1247 | return -EBUSY; | |
1248 | ||
1249 | /* Zero the igu 'trailing edge' and 'leading edge' */ | |
1250 | ||
1251 | /* Send the FW cleanup command */ | |
1252 | if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) | |
1253 | return -EBUSY; | |
1254 | ||
1255 | /* ATC cleanup */ | |
1256 | ||
1257 | /* Verify TX hw is flushed */ | |
1258 | bnx2x_tx_hw_flushed(bp, poll_cnt); | |
1259 | ||
1260 | /* Wait 100ms (not adjusted according to platform) */ | |
1261 | msleep(100); | |
1262 | ||
1263 | /* Verify no pending pci transactions */ | |
1264 | if (bnx2x_is_pcie_pending(bp->pdev)) | |
1265 | BNX2X_ERR("PCIE Transactions still pending\n"); | |
1266 | ||
1267 | /* Debug */ | |
1268 | bnx2x_hw_enable_status(bp); | |
1269 | ||
1270 | /* | |
1271 | * Master enable - Due to WB DMAE writes performed before this | |
1272 | * register is re-initialized as part of the regular function init | |
1273 | */ | |
1274 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
1275 | ||
1276 | return 0; | |
1277 | } | |
1278 | ||
f2e0899f | 1279 | static void bnx2x_hc_int_enable(struct bnx2x *bp) |
a2fbb9ea | 1280 | { |
34f80b04 | 1281 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1282 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1283 | u32 val = REG_RD(bp, addr); | |
1284 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
8badd27a | 1285 | int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; |
a2fbb9ea ET |
1286 | |
1287 | if (msix) { | |
8badd27a EG |
1288 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
1289 | HC_CONFIG_0_REG_INT_LINE_EN_0); | |
a2fbb9ea ET |
1290 | val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
1291 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
8badd27a EG |
1292 | } else if (msi) { |
1293 | val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; | |
1294 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1295 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1296 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1297 | } else { |
1298 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
615f8fd9 | 1299 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
a2fbb9ea ET |
1300 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
1301 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
615f8fd9 | 1302 | |
a0fd065c | 1303 | if (!CHIP_IS_E1(bp)) { |
51c1a580 MS |
1304 | DP(NETIF_MSG_IFUP, |
1305 | "write %x to HC %d (addr 0x%x)\n", val, port, addr); | |
615f8fd9 | 1306 | |
a0fd065c | 1307 | REG_WR(bp, addr, val); |
615f8fd9 | 1308 | |
a0fd065c DK |
1309 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
1310 | } | |
a2fbb9ea ET |
1311 | } |
1312 | ||
a0fd065c DK |
1313 | if (CHIP_IS_E1(bp)) |
1314 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); | |
1315 | ||
51c1a580 MS |
1316 | DP(NETIF_MSG_IFUP, |
1317 | "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, | |
1318 | (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
a2fbb9ea ET |
1319 | |
1320 | REG_WR(bp, addr, val); | |
37dbbf32 EG |
1321 | /* |
1322 | * Ensure that HC_CONFIG is written before leading/trailing edge config | |
1323 | */ | |
1324 | mmiowb(); | |
1325 | barrier(); | |
34f80b04 | 1326 | |
f2e0899f | 1327 | if (!CHIP_IS_E1(bp)) { |
34f80b04 | 1328 | /* init leading/trailing edge */ |
fb3bff17 | 1329 | if (IS_MF(bp)) { |
3395a033 | 1330 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
34f80b04 | 1331 | if (bp->port.pmf) |
4acac6a5 EG |
1332 | /* enable nig and gpio3 attention */ |
1333 | val |= 0x1100; | |
34f80b04 EG |
1334 | } else |
1335 | val = 0xffff; | |
1336 | ||
1337 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
1338 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
1339 | } | |
37dbbf32 EG |
1340 | |
1341 | /* Make sure that interrupts are indeed enabled from here on */ | |
1342 | mmiowb(); | |
a2fbb9ea ET |
1343 | } |
1344 | ||
f2e0899f DK |
1345 | static void bnx2x_igu_int_enable(struct bnx2x *bp) |
1346 | { | |
1347 | u32 val; | |
30a5de77 DK |
1348 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1349 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1350 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
f2e0899f DK |
1351 | |
1352 | val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1353 | ||
1354 | if (msix) { | |
1355 | val &= ~(IGU_PF_CONF_INT_LINE_EN | | |
1356 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1357 | val |= (IGU_PF_CONF_FUNC_EN | | |
1358 | IGU_PF_CONF_MSI_MSIX_EN | | |
1359 | IGU_PF_CONF_ATTN_BIT_EN); | |
30a5de77 DK |
1360 | |
1361 | if (single_msix) | |
1362 | val |= IGU_PF_CONF_SINGLE_ISR_EN; | |
f2e0899f DK |
1363 | } else if (msi) { |
1364 | val &= ~IGU_PF_CONF_INT_LINE_EN; | |
1365 | val |= (IGU_PF_CONF_FUNC_EN | | |
1366 | IGU_PF_CONF_MSI_MSIX_EN | | |
1367 | IGU_PF_CONF_ATTN_BIT_EN | | |
1368 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1369 | } else { | |
1370 | val &= ~IGU_PF_CONF_MSI_MSIX_EN; | |
1371 | val |= (IGU_PF_CONF_FUNC_EN | | |
1372 | IGU_PF_CONF_INT_LINE_EN | | |
1373 | IGU_PF_CONF_ATTN_BIT_EN | | |
1374 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1375 | } | |
1376 | ||
51c1a580 | 1377 | DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", |
f2e0899f DK |
1378 | val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); |
1379 | ||
1380 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1381 | ||
79a8557a YM |
1382 | if (val & IGU_PF_CONF_INT_LINE_EN) |
1383 | pci_intx(bp->pdev, true); | |
1384 | ||
f2e0899f DK |
1385 | barrier(); |
1386 | ||
1387 | /* init leading/trailing edge */ | |
1388 | if (IS_MF(bp)) { | |
3395a033 | 1389 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
1390 | if (bp->port.pmf) |
1391 | /* enable nig and gpio3 attention */ | |
1392 | val |= 0x1100; | |
1393 | } else | |
1394 | val = 0xffff; | |
1395 | ||
1396 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); | |
1397 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
1398 | ||
1399 | /* Make sure that interrupts are indeed enabled from here on */ | |
1400 | mmiowb(); | |
1401 | } | |
1402 | ||
1403 | void bnx2x_int_enable(struct bnx2x *bp) | |
1404 | { | |
1405 | if (bp->common.int_block == INT_BLOCK_HC) | |
1406 | bnx2x_hc_int_enable(bp); | |
1407 | else | |
1408 | bnx2x_igu_int_enable(bp); | |
1409 | } | |
1410 | ||
1411 | static void bnx2x_hc_int_disable(struct bnx2x *bp) | |
a2fbb9ea | 1412 | { |
34f80b04 | 1413 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1414 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1415 | u32 val = REG_RD(bp, addr); | |
1416 | ||
a0fd065c DK |
1417 | /* |
1418 | * in E1 we must use only PCI configuration space to disable | |
1419 | * MSI/MSIX capablility | |
1420 | * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block | |
1421 | */ | |
1422 | if (CHIP_IS_E1(bp)) { | |
1423 | /* Since IGU_PF_CONF_MSI_MSIX_EN still always on | |
1424 | * Use mask register to prevent from HC sending interrupts | |
1425 | * after we exit the function | |
1426 | */ | |
1427 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0); | |
1428 | ||
1429 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1430 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1431 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
1432 | } else | |
1433 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1434 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1435 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1436 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea | 1437 | |
51c1a580 MS |
1438 | DP(NETIF_MSG_IFDOWN, |
1439 | "write %x to HC %d (addr 0x%x)\n", | |
a2fbb9ea ET |
1440 | val, port, addr); |
1441 | ||
8badd27a EG |
1442 | /* flush all outstanding writes */ |
1443 | mmiowb(); | |
1444 | ||
a2fbb9ea ET |
1445 | REG_WR(bp, addr, val); |
1446 | if (REG_RD(bp, addr) != val) | |
1447 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1448 | } | |
1449 | ||
f2e0899f DK |
1450 | static void bnx2x_igu_int_disable(struct bnx2x *bp) |
1451 | { | |
1452 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1453 | ||
1454 | val &= ~(IGU_PF_CONF_MSI_MSIX_EN | | |
1455 | IGU_PF_CONF_INT_LINE_EN | | |
1456 | IGU_PF_CONF_ATTN_BIT_EN); | |
1457 | ||
51c1a580 | 1458 | DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); |
f2e0899f DK |
1459 | |
1460 | /* flush all outstanding writes */ | |
1461 | mmiowb(); | |
1462 | ||
1463 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1464 | if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) | |
1465 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1466 | } | |
1467 | ||
6383c0b3 | 1468 | void bnx2x_int_disable(struct bnx2x *bp) |
f2e0899f DK |
1469 | { |
1470 | if (bp->common.int_block == INT_BLOCK_HC) | |
1471 | bnx2x_hc_int_disable(bp); | |
1472 | else | |
1473 | bnx2x_igu_int_disable(bp); | |
1474 | } | |
1475 | ||
9f6c9258 | 1476 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) |
a2fbb9ea | 1477 | { |
a2fbb9ea | 1478 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
8badd27a | 1479 | int i, offset; |
a2fbb9ea | 1480 | |
f8ef6e44 YG |
1481 | if (disable_hw) |
1482 | /* prevent the HW from sending interrupts */ | |
1483 | bnx2x_int_disable(bp); | |
a2fbb9ea ET |
1484 | |
1485 | /* make sure all ISRs are done */ | |
1486 | if (msix) { | |
8badd27a EG |
1487 | synchronize_irq(bp->msix_table[0].vector); |
1488 | offset = 1; | |
37b091ba MC |
1489 | #ifdef BCM_CNIC |
1490 | offset++; | |
1491 | #endif | |
ec6ba945 | 1492 | for_each_eth_queue(bp, i) |
754a2f52 | 1493 | synchronize_irq(bp->msix_table[offset++].vector); |
a2fbb9ea ET |
1494 | } else |
1495 | synchronize_irq(bp->pdev->irq); | |
1496 | ||
1497 | /* make sure sp_task is not running */ | |
1cf167f2 | 1498 | cancel_delayed_work(&bp->sp_task); |
3deb8167 | 1499 | cancel_delayed_work(&bp->period_task); |
1cf167f2 | 1500 | flush_workqueue(bnx2x_wq); |
a2fbb9ea ET |
1501 | } |
1502 | ||
34f80b04 | 1503 | /* fast path */ |
a2fbb9ea ET |
1504 | |
1505 | /* | |
34f80b04 | 1506 | * General service functions |
a2fbb9ea ET |
1507 | */ |
1508 | ||
72fd0718 VZ |
1509 | /* Return true if succeeded to acquire the lock */ |
1510 | static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) | |
1511 | { | |
1512 | u32 lock_status; | |
1513 | u32 resource_bit = (1 << resource); | |
1514 | int func = BP_FUNC(bp); | |
1515 | u32 hw_lock_control_reg; | |
1516 | ||
51c1a580 MS |
1517 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1518 | "Trying to take a lock on resource %d\n", resource); | |
72fd0718 VZ |
1519 | |
1520 | /* Validating that the resource is within range */ | |
1521 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1522 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
72fd0718 VZ |
1523 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
1524 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
0fdf4d09 | 1525 | return false; |
72fd0718 VZ |
1526 | } |
1527 | ||
1528 | if (func <= 5) | |
1529 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1530 | else | |
1531 | hw_lock_control_reg = | |
1532 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1533 | ||
1534 | /* Try to acquire the lock */ | |
1535 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); | |
1536 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
1537 | if (lock_status & resource_bit) | |
1538 | return true; | |
1539 | ||
51c1a580 MS |
1540 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1541 | "Failed to get a lock on resource %d\n", resource); | |
72fd0718 VZ |
1542 | return false; |
1543 | } | |
1544 | ||
c9ee9206 VZ |
1545 | /** |
1546 | * bnx2x_get_leader_lock_resource - get the recovery leader resource id | |
1547 | * | |
1548 | * @bp: driver handle | |
1549 | * | |
1550 | * Returns the recovery leader resource id according to the engine this function | |
1551 | * belongs to. Currently only only 2 engines is supported. | |
1552 | */ | |
1553 | static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) | |
1554 | { | |
1555 | if (BP_PATH(bp)) | |
1556 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; | |
1557 | else | |
1558 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; | |
1559 | } | |
1560 | ||
1561 | /** | |
1562 | * bnx2x_trylock_leader_lock- try to aquire a leader lock. | |
1563 | * | |
1564 | * @bp: driver handle | |
1565 | * | |
1566 | * Tries to aquire a leader lock for cuurent engine. | |
1567 | */ | |
1568 | static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) | |
1569 | { | |
1570 | return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1571 | } | |
1572 | ||
993ac7b5 | 1573 | #ifdef BCM_CNIC |
619c5cb6 | 1574 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); |
993ac7b5 | 1575 | #endif |
3196a88a | 1576 | |
619c5cb6 | 1577 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) |
a2fbb9ea ET |
1578 | { |
1579 | struct bnx2x *bp = fp->bp; | |
1580 | int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
1581 | int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
619c5cb6 VZ |
1582 | enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; |
1583 | struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; | |
a2fbb9ea | 1584 | |
34f80b04 | 1585 | DP(BNX2X_MSG_SP, |
a2fbb9ea | 1586 | "fp %d cid %d got ramrod #%d state is %x type is %d\n", |
0626b899 | 1587 | fp->index, cid, command, bp->state, |
34f80b04 | 1588 | rr_cqe->ramrod_cqe.ramrod_type); |
a2fbb9ea | 1589 | |
619c5cb6 VZ |
1590 | switch (command) { |
1591 | case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): | |
d6cae238 | 1592 | DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); |
619c5cb6 VZ |
1593 | drv_cmd = BNX2X_Q_CMD_UPDATE; |
1594 | break; | |
d6cae238 | 1595 | |
619c5cb6 | 1596 | case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): |
d6cae238 | 1597 | DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); |
619c5cb6 | 1598 | drv_cmd = BNX2X_Q_CMD_SETUP; |
a2fbb9ea ET |
1599 | break; |
1600 | ||
6383c0b3 | 1601 | case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): |
51c1a580 | 1602 | DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); |
6383c0b3 AE |
1603 | drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; |
1604 | break; | |
1605 | ||
619c5cb6 | 1606 | case (RAMROD_CMD_ID_ETH_HALT): |
d6cae238 | 1607 | DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); |
619c5cb6 | 1608 | drv_cmd = BNX2X_Q_CMD_HALT; |
a2fbb9ea ET |
1609 | break; |
1610 | ||
619c5cb6 | 1611 | case (RAMROD_CMD_ID_ETH_TERMINATE): |
d6cae238 | 1612 | DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); |
619c5cb6 | 1613 | drv_cmd = BNX2X_Q_CMD_TERMINATE; |
a2fbb9ea ET |
1614 | break; |
1615 | ||
619c5cb6 | 1616 | case (RAMROD_CMD_ID_ETH_EMPTY): |
d6cae238 | 1617 | DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); |
619c5cb6 | 1618 | drv_cmd = BNX2X_Q_CMD_EMPTY; |
993ac7b5 | 1619 | break; |
619c5cb6 VZ |
1620 | |
1621 | default: | |
1622 | BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", | |
1623 | command, fp->index); | |
1624 | return; | |
523224a3 | 1625 | } |
3196a88a | 1626 | |
619c5cb6 VZ |
1627 | if ((drv_cmd != BNX2X_Q_CMD_MAX) && |
1628 | q_obj->complete_cmd(bp, q_obj, drv_cmd)) | |
1629 | /* q_obj->complete_cmd() failure means that this was | |
1630 | * an unexpected completion. | |
1631 | * | |
1632 | * In this case we don't want to increase the bp->spq_left | |
1633 | * because apparently we haven't sent this command the first | |
1634 | * place. | |
1635 | */ | |
1636 | #ifdef BNX2X_STOP_ON_ERROR | |
1637 | bnx2x_panic(); | |
1638 | #else | |
1639 | return; | |
1640 | #endif | |
1641 | ||
8fe23fbd | 1642 | smp_mb__before_atomic_inc(); |
6e30dd4e | 1643 | atomic_inc(&bp->cq_spq_left); |
619c5cb6 VZ |
1644 | /* push the change in bp->spq_left and towards the memory */ |
1645 | smp_mb__after_atomic_inc(); | |
49d66772 | 1646 | |
d6cae238 VZ |
1647 | DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); |
1648 | ||
a3348722 BW |
1649 | if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && |
1650 | (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { | |
1651 | /* if Q update ramrod is completed for last Q in AFEX vif set | |
1652 | * flow, then ACK MCP at the end | |
1653 | * | |
1654 | * mark pending ACK to MCP bit. | |
1655 | * prevent case that both bits are cleared. | |
1656 | * At the end of load/unload driver checks that | |
1657 | * sp_state is cleaerd, and this order prevents | |
1658 | * races | |
1659 | */ | |
1660 | smp_mb__before_clear_bit(); | |
1661 | set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); | |
1662 | wmb(); | |
1663 | clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
1664 | smp_mb__after_clear_bit(); | |
1665 | ||
1666 | /* schedule workqueue to send ack to MCP */ | |
1667 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); | |
1668 | } | |
1669 | ||
523224a3 | 1670 | return; |
a2fbb9ea ET |
1671 | } |
1672 | ||
619c5cb6 VZ |
1673 | void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
1674 | u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) | |
1675 | { | |
1676 | u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; | |
1677 | ||
1678 | bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, | |
1679 | start); | |
1680 | } | |
1681 | ||
9f6c9258 | 1682 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) |
a2fbb9ea | 1683 | { |
555f6c78 | 1684 | struct bnx2x *bp = netdev_priv(dev_instance); |
a2fbb9ea | 1685 | u16 status = bnx2x_ack_int(bp); |
34f80b04 | 1686 | u16 mask; |
ca00392c | 1687 | int i; |
6383c0b3 | 1688 | u8 cos; |
a2fbb9ea | 1689 | |
34f80b04 | 1690 | /* Return here if interrupt is shared and it's not for us */ |
a2fbb9ea ET |
1691 | if (unlikely(status == 0)) { |
1692 | DP(NETIF_MSG_INTR, "not our interrupt!\n"); | |
1693 | return IRQ_NONE; | |
1694 | } | |
f5372251 | 1695 | DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); |
a2fbb9ea | 1696 | |
3196a88a EG |
1697 | #ifdef BNX2X_STOP_ON_ERROR |
1698 | if (unlikely(bp->panic)) | |
1699 | return IRQ_HANDLED; | |
1700 | #endif | |
1701 | ||
ec6ba945 | 1702 | for_each_eth_queue(bp, i) { |
ca00392c | 1703 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1704 | |
6383c0b3 | 1705 | mask = 0x2 << (fp->index + CNIC_PRESENT); |
ca00392c | 1706 | if (status & mask) { |
619c5cb6 | 1707 | /* Handle Rx or Tx according to SB id */ |
54b9ddaa | 1708 | prefetch(fp->rx_cons_sb); |
6383c0b3 AE |
1709 | for_each_cos_in_tx_queue(fp, cos) |
1710 | prefetch(fp->txdata[cos].tx_cons_sb); | |
523224a3 | 1711 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
54b9ddaa | 1712 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); |
ca00392c EG |
1713 | status &= ~mask; |
1714 | } | |
a2fbb9ea ET |
1715 | } |
1716 | ||
993ac7b5 | 1717 | #ifdef BCM_CNIC |
523224a3 | 1718 | mask = 0x2; |
993ac7b5 MC |
1719 | if (status & (mask | 0x1)) { |
1720 | struct cnic_ops *c_ops = NULL; | |
1721 | ||
619c5cb6 VZ |
1722 | if (likely(bp->state == BNX2X_STATE_OPEN)) { |
1723 | rcu_read_lock(); | |
1724 | c_ops = rcu_dereference(bp->cnic_ops); | |
1725 | if (c_ops) | |
1726 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
1727 | rcu_read_unlock(); | |
1728 | } | |
993ac7b5 MC |
1729 | |
1730 | status &= ~mask; | |
1731 | } | |
1732 | #endif | |
a2fbb9ea | 1733 | |
34f80b04 | 1734 | if (unlikely(status & 0x1)) { |
1cf167f2 | 1735 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
a2fbb9ea ET |
1736 | |
1737 | status &= ~0x1; | |
1738 | if (!status) | |
1739 | return IRQ_HANDLED; | |
1740 | } | |
1741 | ||
cdaa7cb8 VZ |
1742 | if (unlikely(status)) |
1743 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
34f80b04 | 1744 | status); |
a2fbb9ea | 1745 | |
c18487ee | 1746 | return IRQ_HANDLED; |
a2fbb9ea ET |
1747 | } |
1748 | ||
c18487ee YR |
1749 | /* Link */ |
1750 | ||
1751 | /* | |
1752 | * General service functions | |
1753 | */ | |
a2fbb9ea | 1754 | |
9f6c9258 | 1755 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1756 | { |
1757 | u32 lock_status; | |
1758 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1759 | int func = BP_FUNC(bp); |
1760 | u32 hw_lock_control_reg; | |
c18487ee | 1761 | int cnt; |
a2fbb9ea | 1762 | |
c18487ee YR |
1763 | /* Validating that the resource is within range */ |
1764 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1765 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1766 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1767 | return -EINVAL; | |
1768 | } | |
a2fbb9ea | 1769 | |
4a37fb66 YG |
1770 | if (func <= 5) { |
1771 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1772 | } else { | |
1773 | hw_lock_control_reg = | |
1774 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1775 | } | |
1776 | ||
c18487ee | 1777 | /* Validating that the resource is not already taken */ |
4a37fb66 | 1778 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 1779 | if (lock_status & resource_bit) { |
51c1a580 | 1780 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", |
c18487ee YR |
1781 | lock_status, resource_bit); |
1782 | return -EEXIST; | |
1783 | } | |
a2fbb9ea | 1784 | |
46230476 EG |
1785 | /* Try for 5 second every 5ms */ |
1786 | for (cnt = 0; cnt < 1000; cnt++) { | |
c18487ee | 1787 | /* Try to acquire the lock */ |
4a37fb66 YG |
1788 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
1789 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
c18487ee YR |
1790 | if (lock_status & resource_bit) |
1791 | return 0; | |
a2fbb9ea | 1792 | |
c18487ee | 1793 | msleep(5); |
a2fbb9ea | 1794 | } |
51c1a580 | 1795 | BNX2X_ERR("Timeout\n"); |
c18487ee YR |
1796 | return -EAGAIN; |
1797 | } | |
a2fbb9ea | 1798 | |
c9ee9206 VZ |
1799 | int bnx2x_release_leader_lock(struct bnx2x *bp) |
1800 | { | |
1801 | return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1802 | } | |
1803 | ||
9f6c9258 | 1804 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1805 | { |
1806 | u32 lock_status; | |
1807 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1808 | int func = BP_FUNC(bp); |
1809 | u32 hw_lock_control_reg; | |
a2fbb9ea | 1810 | |
c18487ee YR |
1811 | /* Validating that the resource is within range */ |
1812 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1813 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1814 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1815 | return -EINVAL; | |
1816 | } | |
1817 | ||
4a37fb66 YG |
1818 | if (func <= 5) { |
1819 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1820 | } else { | |
1821 | hw_lock_control_reg = | |
1822 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1823 | } | |
1824 | ||
c18487ee | 1825 | /* Validating that the resource is currently taken */ |
4a37fb66 | 1826 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 1827 | if (!(lock_status & resource_bit)) { |
51c1a580 | 1828 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n", |
c18487ee YR |
1829 | lock_status, resource_bit); |
1830 | return -EFAULT; | |
a2fbb9ea ET |
1831 | } |
1832 | ||
9f6c9258 DK |
1833 | REG_WR(bp, hw_lock_control_reg, resource_bit); |
1834 | return 0; | |
c18487ee | 1835 | } |
a2fbb9ea | 1836 | |
9f6c9258 | 1837 | |
4acac6a5 EG |
1838 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) |
1839 | { | |
1840 | /* The GPIO should be swapped if swap register is set and active */ | |
1841 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
1842 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
1843 | int gpio_shift = gpio_num + | |
1844 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1845 | u32 gpio_mask = (1 << gpio_shift); | |
1846 | u32 gpio_reg; | |
1847 | int value; | |
1848 | ||
1849 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
1850 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1851 | return -EINVAL; | |
1852 | } | |
1853 | ||
1854 | /* read GPIO value */ | |
1855 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1856 | ||
1857 | /* get the requested pin value */ | |
1858 | if ((gpio_reg & gpio_mask) == gpio_mask) | |
1859 | value = 1; | |
1860 | else | |
1861 | value = 0; | |
1862 | ||
1863 | DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); | |
1864 | ||
1865 | return value; | |
1866 | } | |
1867 | ||
17de50b7 | 1868 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
c18487ee YR |
1869 | { |
1870 | /* The GPIO should be swapped if swap register is set and active */ | |
1871 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
17de50b7 | 1872 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
c18487ee YR |
1873 | int gpio_shift = gpio_num + |
1874 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1875 | u32 gpio_mask = (1 << gpio_shift); | |
1876 | u32 gpio_reg; | |
a2fbb9ea | 1877 | |
c18487ee YR |
1878 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
1879 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1880 | return -EINVAL; | |
1881 | } | |
a2fbb9ea | 1882 | |
4a37fb66 | 1883 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
c18487ee YR |
1884 | /* read GPIO and mask except the float bits */ |
1885 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); | |
a2fbb9ea | 1886 | |
c18487ee YR |
1887 | switch (mode) { |
1888 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
51c1a580 MS |
1889 | DP(NETIF_MSG_LINK, |
1890 | "Set GPIO %d (shift %d) -> output low\n", | |
c18487ee YR |
1891 | gpio_num, gpio_shift); |
1892 | /* clear FLOAT and set CLR */ | |
1893 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1894 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); | |
1895 | break; | |
a2fbb9ea | 1896 | |
c18487ee | 1897 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
51c1a580 MS |
1898 | DP(NETIF_MSG_LINK, |
1899 | "Set GPIO %d (shift %d) -> output high\n", | |
c18487ee YR |
1900 | gpio_num, gpio_shift); |
1901 | /* clear FLOAT and set SET */ | |
1902 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1903 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); | |
1904 | break; | |
a2fbb9ea | 1905 | |
17de50b7 | 1906 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
51c1a580 MS |
1907 | DP(NETIF_MSG_LINK, |
1908 | "Set GPIO %d (shift %d) -> input\n", | |
c18487ee YR |
1909 | gpio_num, gpio_shift); |
1910 | /* set FLOAT */ | |
1911 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1912 | break; | |
a2fbb9ea | 1913 | |
c18487ee YR |
1914 | default: |
1915 | break; | |
a2fbb9ea ET |
1916 | } |
1917 | ||
c18487ee | 1918 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
4a37fb66 | 1919 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
f1410647 | 1920 | |
c18487ee | 1921 | return 0; |
a2fbb9ea ET |
1922 | } |
1923 | ||
0d40f0d4 YR |
1924 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) |
1925 | { | |
1926 | u32 gpio_reg = 0; | |
1927 | int rc = 0; | |
1928 | ||
1929 | /* Any port swapping should be handled by caller. */ | |
1930 | ||
1931 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1932 | /* read GPIO and mask except the float bits */ | |
1933 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1934 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1935 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); | |
1936 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); | |
1937 | ||
1938 | switch (mode) { | |
1939 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
1940 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); | |
1941 | /* set CLR */ | |
1942 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); | |
1943 | break; | |
1944 | ||
1945 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: | |
1946 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); | |
1947 | /* set SET */ | |
1948 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); | |
1949 | break; | |
1950 | ||
1951 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: | |
1952 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); | |
1953 | /* set FLOAT */ | |
1954 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1955 | break; | |
1956 | ||
1957 | default: | |
1958 | BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); | |
1959 | rc = -EINVAL; | |
1960 | break; | |
1961 | } | |
1962 | ||
1963 | if (rc == 0) | |
1964 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); | |
1965 | ||
1966 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1967 | ||
1968 | return rc; | |
1969 | } | |
1970 | ||
4acac6a5 EG |
1971 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
1972 | { | |
1973 | /* The GPIO should be swapped if swap register is set and active */ | |
1974 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
1975 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
1976 | int gpio_shift = gpio_num + | |
1977 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1978 | u32 gpio_mask = (1 << gpio_shift); | |
1979 | u32 gpio_reg; | |
1980 | ||
1981 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
1982 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1983 | return -EINVAL; | |
1984 | } | |
1985 | ||
1986 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1987 | /* read GPIO int */ | |
1988 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); | |
1989 | ||
1990 | switch (mode) { | |
1991 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: | |
51c1a580 MS |
1992 | DP(NETIF_MSG_LINK, |
1993 | "Clear GPIO INT %d (shift %d) -> output low\n", | |
1994 | gpio_num, gpio_shift); | |
4acac6a5 EG |
1995 | /* clear SET and set CLR */ |
1996 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
1997 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
1998 | break; | |
1999 | ||
2000 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: | |
51c1a580 MS |
2001 | DP(NETIF_MSG_LINK, |
2002 | "Set GPIO INT %d (shift %d) -> output high\n", | |
2003 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2004 | /* clear CLR and set SET */ |
2005 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2006 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2007 | break; | |
2008 | ||
2009 | default: | |
2010 | break; | |
2011 | } | |
2012 | ||
2013 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); | |
2014 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2015 | ||
2016 | return 0; | |
2017 | } | |
2018 | ||
c18487ee | 2019 | static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) |
a2fbb9ea | 2020 | { |
c18487ee YR |
2021 | u32 spio_mask = (1 << spio_num); |
2022 | u32 spio_reg; | |
a2fbb9ea | 2023 | |
c18487ee YR |
2024 | if ((spio_num < MISC_REGISTERS_SPIO_4) || |
2025 | (spio_num > MISC_REGISTERS_SPIO_7)) { | |
2026 | BNX2X_ERR("Invalid SPIO %d\n", spio_num); | |
2027 | return -EINVAL; | |
a2fbb9ea ET |
2028 | } |
2029 | ||
4a37fb66 | 2030 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee YR |
2031 | /* read SPIO and mask except the float bits */ |
2032 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); | |
a2fbb9ea | 2033 | |
c18487ee | 2034 | switch (mode) { |
6378c025 | 2035 | case MISC_REGISTERS_SPIO_OUTPUT_LOW: |
51c1a580 | 2036 | DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num); |
c18487ee YR |
2037 | /* clear FLOAT and set CLR */ |
2038 | spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2039 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); | |
2040 | break; | |
a2fbb9ea | 2041 | |
6378c025 | 2042 | case MISC_REGISTERS_SPIO_OUTPUT_HIGH: |
51c1a580 | 2043 | DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num); |
c18487ee YR |
2044 | /* clear FLOAT and set SET */ |
2045 | spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2046 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); | |
2047 | break; | |
a2fbb9ea | 2048 | |
c18487ee | 2049 | case MISC_REGISTERS_SPIO_INPUT_HI_Z: |
51c1a580 | 2050 | DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num); |
c18487ee YR |
2051 | /* set FLOAT */ |
2052 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2053 | break; | |
a2fbb9ea | 2054 | |
c18487ee YR |
2055 | default: |
2056 | break; | |
a2fbb9ea ET |
2057 | } |
2058 | ||
c18487ee | 2059 | REG_WR(bp, MISC_REG_SPIO, spio_reg); |
4a37fb66 | 2060 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2061 | |
a2fbb9ea ET |
2062 | return 0; |
2063 | } | |
2064 | ||
9f6c9258 | 2065 | void bnx2x_calc_fc_adv(struct bnx2x *bp) |
a2fbb9ea | 2066 | { |
a22f0788 | 2067 | u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
ad33ea3a EG |
2068 | switch (bp->link_vars.ieee_fc & |
2069 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { | |
c18487ee | 2070 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: |
a22f0788 | 2071 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2072 | ADVERTISED_Pause); |
c18487ee | 2073 | break; |
356e2385 | 2074 | |
c18487ee | 2075 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: |
a22f0788 | 2076 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | |
f85582f8 | 2077 | ADVERTISED_Pause); |
c18487ee | 2078 | break; |
356e2385 | 2079 | |
c18487ee | 2080 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: |
a22f0788 | 2081 | bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; |
c18487ee | 2082 | break; |
356e2385 | 2083 | |
c18487ee | 2084 | default: |
a22f0788 | 2085 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2086 | ADVERTISED_Pause); |
c18487ee YR |
2087 | break; |
2088 | } | |
2089 | } | |
f1410647 | 2090 | |
9f6c9258 | 2091 | u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) |
c18487ee | 2092 | { |
19680c48 EG |
2093 | if (!BP_NOMCP(bp)) { |
2094 | u8 rc; | |
a22f0788 YR |
2095 | int cfx_idx = bnx2x_get_link_cfg_idx(bp); |
2096 | u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; | |
1cb0c788 YR |
2097 | /* |
2098 | * Initialize link parameters structure variables | |
2099 | * It is recommended to turn off RX FC for jumbo frames | |
2100 | * for better performance | |
2101 | */ | |
2102 | if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) | |
c0700f90 | 2103 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; |
8c99e7b0 | 2104 | else |
c0700f90 | 2105 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; |
a2fbb9ea | 2106 | |
4a37fb66 | 2107 | bnx2x_acquire_phy_lock(bp); |
b5bf9068 | 2108 | |
a22f0788 | 2109 | if (load_mode == LOAD_DIAG) { |
1cb0c788 YR |
2110 | struct link_params *lp = &bp->link_params; |
2111 | lp->loopback_mode = LOOPBACK_XGXS; | |
2112 | /* do PHY loopback at 10G speed, if possible */ | |
2113 | if (lp->req_line_speed[cfx_idx] < SPEED_10000) { | |
2114 | if (lp->speed_cap_mask[cfx_idx] & | |
2115 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
2116 | lp->req_line_speed[cfx_idx] = | |
2117 | SPEED_10000; | |
2118 | else | |
2119 | lp->req_line_speed[cfx_idx] = | |
2120 | SPEED_1000; | |
2121 | } | |
a22f0788 | 2122 | } |
b5bf9068 | 2123 | |
19680c48 | 2124 | rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
b5bf9068 | 2125 | |
4a37fb66 | 2126 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2127 | |
3c96c68b EG |
2128 | bnx2x_calc_fc_adv(bp); |
2129 | ||
b5bf9068 EG |
2130 | if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { |
2131 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
19680c48 | 2132 | bnx2x_link_report(bp); |
3deb8167 YR |
2133 | } else |
2134 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
a22f0788 | 2135 | bp->link_params.req_line_speed[cfx_idx] = req_line_speed; |
19680c48 EG |
2136 | return rc; |
2137 | } | |
f5372251 | 2138 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
19680c48 | 2139 | return -EINVAL; |
a2fbb9ea ET |
2140 | } |
2141 | ||
9f6c9258 | 2142 | void bnx2x_link_set(struct bnx2x *bp) |
a2fbb9ea | 2143 | { |
19680c48 | 2144 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2145 | bnx2x_acquire_phy_lock(bp); |
54c2fb78 | 2146 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); |
19680c48 | 2147 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2148 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2149 | |
19680c48 EG |
2150 | bnx2x_calc_fc_adv(bp); |
2151 | } else | |
f5372251 | 2152 | BNX2X_ERR("Bootcode is missing - can not set link\n"); |
c18487ee | 2153 | } |
a2fbb9ea | 2154 | |
c18487ee YR |
2155 | static void bnx2x__link_reset(struct bnx2x *bp) |
2156 | { | |
19680c48 | 2157 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2158 | bnx2x_acquire_phy_lock(bp); |
589abe3a | 2159 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); |
4a37fb66 | 2160 | bnx2x_release_phy_lock(bp); |
19680c48 | 2161 | } else |
f5372251 | 2162 | BNX2X_ERR("Bootcode is missing - can not reset link\n"); |
c18487ee | 2163 | } |
a2fbb9ea | 2164 | |
a22f0788 | 2165 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) |
c18487ee | 2166 | { |
2145a920 | 2167 | u8 rc = 0; |
a2fbb9ea | 2168 | |
2145a920 VZ |
2169 | if (!BP_NOMCP(bp)) { |
2170 | bnx2x_acquire_phy_lock(bp); | |
a22f0788 YR |
2171 | rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, |
2172 | is_serdes); | |
2145a920 VZ |
2173 | bnx2x_release_phy_lock(bp); |
2174 | } else | |
2175 | BNX2X_ERR("Bootcode is missing - can not test link\n"); | |
a2fbb9ea | 2176 | |
c18487ee YR |
2177 | return rc; |
2178 | } | |
a2fbb9ea | 2179 | |
34f80b04 | 2180 | |
2691d51d EG |
2181 | /* Calculates the sum of vn_min_rates. |
2182 | It's needed for further normalizing of the min_rates. | |
2183 | Returns: | |
2184 | sum of vn_min_rates. | |
2185 | or | |
2186 | 0 - if all the min_rates are 0. | |
2187 | In the later case fainess algorithm should be deactivated. | |
2188 | If not all min_rates are zero then those that are zeroes will be set to 1. | |
2189 | */ | |
b475d78f YM |
2190 | static void bnx2x_calc_vn_min(struct bnx2x *bp, |
2191 | struct cmng_init_input *input) | |
2691d51d EG |
2192 | { |
2193 | int all_zero = 1; | |
2691d51d EG |
2194 | int vn; |
2195 | ||
3395a033 | 2196 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
f2e0899f | 2197 | u32 vn_cfg = bp->mf_config[vn]; |
2691d51d EG |
2198 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2199 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
2200 | ||
2201 | /* Skip hidden vns */ | |
2202 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) | |
b475d78f | 2203 | vn_min_rate = 0; |
2691d51d | 2204 | /* If min rate is zero - set it to 1 */ |
b475d78f | 2205 | else if (!vn_min_rate) |
2691d51d EG |
2206 | vn_min_rate = DEF_MIN_RATE; |
2207 | else | |
2208 | all_zero = 0; | |
2209 | ||
b475d78f | 2210 | input->vnic_min_rate[vn] = vn_min_rate; |
2691d51d EG |
2211 | } |
2212 | ||
30ae438b DK |
2213 | /* if ETS or all min rates are zeros - disable fairness */ |
2214 | if (BNX2X_IS_ETS_ENABLED(bp)) { | |
b475d78f | 2215 | input->flags.cmng_enables &= |
30ae438b DK |
2216 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2217 | DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); | |
2218 | } else if (all_zero) { | |
b475d78f | 2219 | input->flags.cmng_enables &= |
b015e3d1 | 2220 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
b475d78f YM |
2221 | DP(NETIF_MSG_IFUP, |
2222 | "All MIN values are zeroes fairness will be disabled\n"); | |
b015e3d1 | 2223 | } else |
b475d78f | 2224 | input->flags.cmng_enables |= |
b015e3d1 | 2225 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2691d51d EG |
2226 | } |
2227 | ||
b475d78f YM |
2228 | static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, |
2229 | struct cmng_init_input *input) | |
34f80b04 | 2230 | { |
b475d78f | 2231 | u16 vn_max_rate; |
f2e0899f | 2232 | u32 vn_cfg = bp->mf_config[vn]; |
34f80b04 | 2233 | |
b475d78f | 2234 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) |
34f80b04 | 2235 | vn_max_rate = 0; |
b475d78f | 2236 | else { |
faa6fcbb DK |
2237 | u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); |
2238 | ||
b475d78f | 2239 | if (IS_MF_SI(bp)) { |
faa6fcbb DK |
2240 | /* maxCfg in percents of linkspeed */ |
2241 | vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; | |
b475d78f | 2242 | } else /* SD modes */ |
faa6fcbb DK |
2243 | /* maxCfg is absolute in 100Mb units */ |
2244 | vn_max_rate = maxCfg * 100; | |
34f80b04 | 2245 | } |
f85582f8 | 2246 | |
b475d78f | 2247 | DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); |
34f80b04 | 2248 | |
b475d78f | 2249 | input->vnic_max_rate[vn] = vn_max_rate; |
34f80b04 | 2250 | } |
f85582f8 | 2251 | |
b475d78f | 2252 | |
523224a3 DK |
2253 | static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) |
2254 | { | |
2255 | if (CHIP_REV_IS_SLOW(bp)) | |
2256 | return CMNG_FNS_NONE; | |
fb3bff17 | 2257 | if (IS_MF(bp)) |
523224a3 DK |
2258 | return CMNG_FNS_MINMAX; |
2259 | ||
2260 | return CMNG_FNS_NONE; | |
2261 | } | |
2262 | ||
2ae17f66 | 2263 | void bnx2x_read_mf_cfg(struct bnx2x *bp) |
523224a3 | 2264 | { |
0793f83f | 2265 | int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); |
523224a3 DK |
2266 | |
2267 | if (BP_NOMCP(bp)) | |
2268 | return; /* what should be the default bvalue in this case */ | |
2269 | ||
0793f83f DK |
2270 | /* For 2 port configuration the absolute function number formula |
2271 | * is: | |
2272 | * abs_func = 2 * vn + BP_PORT + BP_PATH | |
2273 | * | |
2274 | * and there are 4 functions per port | |
2275 | * | |
2276 | * For 4 port configuration it is | |
2277 | * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH | |
2278 | * | |
2279 | * and there are 2 functions per port | |
2280 | */ | |
3395a033 | 2281 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
0793f83f DK |
2282 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
2283 | ||
2284 | if (func >= E1H_FUNC_MAX) | |
2285 | break; | |
2286 | ||
f2e0899f | 2287 | bp->mf_config[vn] = |
523224a3 DK |
2288 | MF_CFG_RD(bp, func_mf_config[func].config); |
2289 | } | |
a3348722 BW |
2290 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
2291 | DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); | |
2292 | bp->flags |= MF_FUNC_DIS; | |
2293 | } else { | |
2294 | DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); | |
2295 | bp->flags &= ~MF_FUNC_DIS; | |
2296 | } | |
523224a3 DK |
2297 | } |
2298 | ||
2299 | static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |
2300 | { | |
b475d78f YM |
2301 | struct cmng_init_input input; |
2302 | memset(&input, 0, sizeof(struct cmng_init_input)); | |
2303 | ||
2304 | input.port_rate = bp->link_vars.line_speed; | |
523224a3 DK |
2305 | |
2306 | if (cmng_type == CMNG_FNS_MINMAX) { | |
2307 | int vn; | |
2308 | ||
523224a3 DK |
2309 | /* read mf conf from shmem */ |
2310 | if (read_cfg) | |
2311 | bnx2x_read_mf_cfg(bp); | |
2312 | ||
523224a3 | 2313 | /* vn_weight_sum and enable fairness if not 0 */ |
b475d78f | 2314 | bnx2x_calc_vn_min(bp, &input); |
523224a3 DK |
2315 | |
2316 | /* calculate and set min-max rate for each vn */ | |
c4154f25 | 2317 | if (bp->port.pmf) |
3395a033 | 2318 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) |
b475d78f | 2319 | bnx2x_calc_vn_max(bp, vn, &input); |
523224a3 DK |
2320 | |
2321 | /* always enable rate shaping and fairness */ | |
b475d78f | 2322 | input.flags.cmng_enables |= |
523224a3 | 2323 | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; |
b475d78f YM |
2324 | |
2325 | bnx2x_init_cmng(&input, &bp->cmng); | |
523224a3 DK |
2326 | return; |
2327 | } | |
2328 | ||
2329 | /* rate shaping and fairness are disabled */ | |
2330 | DP(NETIF_MSG_IFUP, | |
2331 | "rate shaping and fairness are disabled\n"); | |
2332 | } | |
34f80b04 | 2333 | |
c18487ee YR |
2334 | /* This function is called upon link interrupt */ |
2335 | static void bnx2x_link_attn(struct bnx2x *bp) | |
2336 | { | |
bb2a0f7a YG |
2337 | /* Make sure that we are synced with the current statistics */ |
2338 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2339 | ||
c18487ee | 2340 | bnx2x_link_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2341 | |
bb2a0f7a YG |
2342 | if (bp->link_vars.link_up) { |
2343 | ||
1c06328c | 2344 | /* dropless flow control */ |
f2e0899f | 2345 | if (!CHIP_IS_E1(bp) && bp->dropless_fc) { |
1c06328c EG |
2346 | int port = BP_PORT(bp); |
2347 | u32 pause_enabled = 0; | |
2348 | ||
2349 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
2350 | pause_enabled = 1; | |
2351 | ||
2352 | REG_WR(bp, BAR_USTRORM_INTMEM + | |
ca00392c | 2353 | USTORM_ETH_PAUSE_ENABLED_OFFSET(port), |
1c06328c EG |
2354 | pause_enabled); |
2355 | } | |
2356 | ||
619c5cb6 | 2357 | if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { |
bb2a0f7a YG |
2358 | struct host_port_stats *pstats; |
2359 | ||
2360 | pstats = bnx2x_sp(bp, port_stats); | |
619c5cb6 | 2361 | /* reset old mac stats */ |
bb2a0f7a YG |
2362 | memset(&(pstats->mac_stx[0]), 0, |
2363 | sizeof(struct mac_stx)); | |
2364 | } | |
f34d28ea | 2365 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a YG |
2366 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
2367 | } | |
2368 | ||
f2e0899f DK |
2369 | if (bp->link_vars.link_up && bp->link_vars.line_speed) { |
2370 | int cmng_fns = bnx2x_get_cmng_fns_mode(bp); | |
8a1c38d1 | 2371 | |
f2e0899f DK |
2372 | if (cmng_fns != CMNG_FNS_NONE) { |
2373 | bnx2x_cmng_fns_init(bp, false, cmng_fns); | |
2374 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2375 | } else | |
2376 | /* rate shaping and fairness are disabled */ | |
2377 | DP(NETIF_MSG_IFUP, | |
2378 | "single function mode without fairness\n"); | |
34f80b04 | 2379 | } |
9fdc3e95 | 2380 | |
2ae17f66 VZ |
2381 | __bnx2x_link_report(bp); |
2382 | ||
9fdc3e95 DK |
2383 | if (IS_MF(bp)) |
2384 | bnx2x_link_sync_notify(bp); | |
c18487ee | 2385 | } |
a2fbb9ea | 2386 | |
9f6c9258 | 2387 | void bnx2x__link_status_update(struct bnx2x *bp) |
c18487ee | 2388 | { |
2ae17f66 | 2389 | if (bp->state != BNX2X_STATE_OPEN) |
c18487ee | 2390 | return; |
a2fbb9ea | 2391 | |
00253a8c DK |
2392 | /* read updated dcb configuration */ |
2393 | bnx2x_dcbx_pmf_update(bp); | |
2394 | ||
c18487ee | 2395 | bnx2x_link_status_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2396 | |
bb2a0f7a YG |
2397 | if (bp->link_vars.link_up) |
2398 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
2399 | else | |
2400 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2401 | ||
c18487ee YR |
2402 | /* indicate link status */ |
2403 | bnx2x_link_report(bp); | |
a2fbb9ea | 2404 | } |
a2fbb9ea | 2405 | |
a3348722 BW |
2406 | static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, |
2407 | u16 vlan_val, u8 allowed_prio) | |
2408 | { | |
2409 | struct bnx2x_func_state_params func_params = {0}; | |
2410 | struct bnx2x_func_afex_update_params *f_update_params = | |
2411 | &func_params.params.afex_update; | |
2412 | ||
2413 | func_params.f_obj = &bp->func_obj; | |
2414 | func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; | |
2415 | ||
2416 | /* no need to wait for RAMROD completion, so don't | |
2417 | * set RAMROD_COMP_WAIT flag | |
2418 | */ | |
2419 | ||
2420 | f_update_params->vif_id = vifid; | |
2421 | f_update_params->afex_default_vlan = vlan_val; | |
2422 | f_update_params->allowed_priorities = allowed_prio; | |
2423 | ||
2424 | /* if ramrod can not be sent, response to MCP immediately */ | |
2425 | if (bnx2x_func_state_change(bp, &func_params) < 0) | |
2426 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
2427 | ||
2428 | return 0; | |
2429 | } | |
2430 | ||
2431 | static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, | |
2432 | u16 vif_index, u8 func_bit_map) | |
2433 | { | |
2434 | struct bnx2x_func_state_params func_params = {0}; | |
2435 | struct bnx2x_func_afex_viflists_params *update_params = | |
2436 | &func_params.params.afex_viflists; | |
2437 | int rc; | |
2438 | u32 drv_msg_code; | |
2439 | ||
2440 | /* validate only LIST_SET and LIST_GET are received from switch */ | |
2441 | if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) | |
2442 | BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", | |
2443 | cmd_type); | |
2444 | ||
2445 | func_params.f_obj = &bp->func_obj; | |
2446 | func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; | |
2447 | ||
2448 | /* set parameters according to cmd_type */ | |
2449 | update_params->afex_vif_list_command = cmd_type; | |
2450 | update_params->vif_list_index = cpu_to_le16(vif_index); | |
2451 | update_params->func_bit_map = | |
2452 | (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; | |
2453 | update_params->func_to_clear = 0; | |
2454 | drv_msg_code = | |
2455 | (cmd_type == VIF_LIST_RULE_GET) ? | |
2456 | DRV_MSG_CODE_AFEX_LISTGET_ACK : | |
2457 | DRV_MSG_CODE_AFEX_LISTSET_ACK; | |
2458 | ||
2459 | /* if ramrod can not be sent, respond to MCP immediately for | |
2460 | * SET and GET requests (other are not triggered from MCP) | |
2461 | */ | |
2462 | rc = bnx2x_func_state_change(bp, &func_params); | |
2463 | if (rc < 0) | |
2464 | bnx2x_fw_command(bp, drv_msg_code, 0); | |
2465 | ||
2466 | return 0; | |
2467 | } | |
2468 | ||
2469 | static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) | |
2470 | { | |
2471 | struct afex_stats afex_stats; | |
2472 | u32 func = BP_ABS_FUNC(bp); | |
2473 | u32 mf_config; | |
2474 | u16 vlan_val; | |
2475 | u32 vlan_prio; | |
2476 | u16 vif_id; | |
2477 | u8 allowed_prio; | |
2478 | u8 vlan_mode; | |
2479 | u32 addr_to_write, vifid, addrs, stats_type, i; | |
2480 | ||
2481 | if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { | |
2482 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2483 | DP(BNX2X_MSG_MCP, | |
2484 | "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); | |
2485 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); | |
2486 | } | |
2487 | ||
2488 | if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { | |
2489 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2490 | addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); | |
2491 | DP(BNX2X_MSG_MCP, | |
2492 | "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", | |
2493 | vifid, addrs); | |
2494 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, | |
2495 | addrs); | |
2496 | } | |
2497 | ||
2498 | if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { | |
2499 | addr_to_write = SHMEM2_RD(bp, | |
2500 | afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); | |
2501 | stats_type = SHMEM2_RD(bp, | |
2502 | afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2503 | ||
2504 | DP(BNX2X_MSG_MCP, | |
2505 | "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", | |
2506 | addr_to_write); | |
2507 | ||
2508 | bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); | |
2509 | ||
2510 | /* write response to scratchpad, for MCP */ | |
2511 | for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) | |
2512 | REG_WR(bp, addr_to_write + i*sizeof(u32), | |
2513 | *(((u32 *)(&afex_stats))+i)); | |
2514 | ||
2515 | /* send ack message to MCP */ | |
2516 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); | |
2517 | } | |
2518 | ||
2519 | if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { | |
2520 | mf_config = MF_CFG_RD(bp, func_mf_config[func].config); | |
2521 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2522 | DP(BNX2X_MSG_MCP, | |
2523 | "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", | |
2524 | mf_config); | |
2525 | ||
2526 | /* if VIF_SET is "enabled" */ | |
2527 | if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { | |
2528 | /* set rate limit directly to internal RAM */ | |
2529 | struct cmng_init_input cmng_input; | |
2530 | struct rate_shaping_vars_per_vn m_rs_vn; | |
2531 | size_t size = sizeof(struct rate_shaping_vars_per_vn); | |
2532 | u32 addr = BAR_XSTRORM_INTMEM + | |
2533 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); | |
2534 | ||
2535 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2536 | ||
2537 | bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); | |
2538 | m_rs_vn.vn_counter.rate = | |
2539 | cmng_input.vnic_max_rate[BP_VN(bp)]; | |
2540 | m_rs_vn.vn_counter.quota = | |
2541 | (m_rs_vn.vn_counter.rate * | |
2542 | RS_PERIODIC_TIMEOUT_USEC) / 8; | |
2543 | ||
2544 | __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); | |
2545 | ||
2546 | /* read relevant values from mf_cfg struct in shmem */ | |
2547 | vif_id = | |
2548 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2549 | FUNC_MF_CFG_E1HOV_TAG_MASK) >> | |
2550 | FUNC_MF_CFG_E1HOV_TAG_SHIFT; | |
2551 | vlan_val = | |
2552 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2553 | FUNC_MF_CFG_AFEX_VLAN_MASK) >> | |
2554 | FUNC_MF_CFG_AFEX_VLAN_SHIFT; | |
2555 | vlan_prio = (mf_config & | |
2556 | FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> | |
2557 | FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; | |
2558 | vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); | |
2559 | vlan_mode = | |
2560 | (MF_CFG_RD(bp, | |
2561 | func_mf_config[func].afex_config) & | |
2562 | FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> | |
2563 | FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; | |
2564 | allowed_prio = | |
2565 | (MF_CFG_RD(bp, | |
2566 | func_mf_config[func].afex_config) & | |
2567 | FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> | |
2568 | FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; | |
2569 | ||
2570 | /* send ramrod to FW, return in case of failure */ | |
2571 | if (bnx2x_afex_func_update(bp, vif_id, vlan_val, | |
2572 | allowed_prio)) | |
2573 | return; | |
2574 | ||
2575 | bp->afex_def_vlan_tag = vlan_val; | |
2576 | bp->afex_vlan_mode = vlan_mode; | |
2577 | } else { | |
2578 | /* notify link down because BP->flags is disabled */ | |
2579 | bnx2x_link_report(bp); | |
2580 | ||
2581 | /* send INVALID VIF ramrod to FW */ | |
2582 | bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); | |
2583 | ||
2584 | /* Reset the default afex VLAN */ | |
2585 | bp->afex_def_vlan_tag = -1; | |
2586 | } | |
2587 | } | |
2588 | } | |
2589 | ||
34f80b04 EG |
2590 | static void bnx2x_pmf_update(struct bnx2x *bp) |
2591 | { | |
2592 | int port = BP_PORT(bp); | |
2593 | u32 val; | |
2594 | ||
2595 | bp->port.pmf = 1; | |
51c1a580 | 2596 | DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); |
34f80b04 | 2597 | |
3deb8167 YR |
2598 | /* |
2599 | * We need the mb() to ensure the ordering between the writing to | |
2600 | * bp->port.pmf here and reading it from the bnx2x_periodic_task(). | |
2601 | */ | |
2602 | smp_mb(); | |
2603 | ||
2604 | /* queue a periodic task */ | |
2605 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
2606 | ||
ef01854e DK |
2607 | bnx2x_dcbx_pmf_update(bp); |
2608 | ||
34f80b04 | 2609 | /* enable nig attention */ |
3395a033 | 2610 | val = (0xff0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
2611 | if (bp->common.int_block == INT_BLOCK_HC) { |
2612 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
2613 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
619c5cb6 | 2614 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2615 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
2616 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
2617 | } | |
bb2a0f7a YG |
2618 | |
2619 | bnx2x_stats_handle(bp, STATS_EVENT_PMF); | |
34f80b04 EG |
2620 | } |
2621 | ||
c18487ee | 2622 | /* end of Link */ |
a2fbb9ea ET |
2623 | |
2624 | /* slow path */ | |
2625 | ||
2626 | /* | |
2627 | * General service functions | |
2628 | */ | |
2629 | ||
2691d51d | 2630 | /* send the MCP a request, block until there is a reply */ |
a22f0788 | 2631 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) |
2691d51d | 2632 | { |
f2e0899f | 2633 | int mb_idx = BP_FW_MB_IDX(bp); |
a5971d43 | 2634 | u32 seq; |
2691d51d EG |
2635 | u32 rc = 0; |
2636 | u32 cnt = 1; | |
2637 | u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; | |
2638 | ||
c4ff7cbf | 2639 | mutex_lock(&bp->fw_mb_mutex); |
a5971d43 | 2640 | seq = ++bp->fw_seq; |
f2e0899f DK |
2641 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); |
2642 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); | |
2643 | ||
754a2f52 DK |
2644 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", |
2645 | (command | seq), param); | |
2691d51d EG |
2646 | |
2647 | do { | |
2648 | /* let the FW do it's magic ... */ | |
2649 | msleep(delay); | |
2650 | ||
f2e0899f | 2651 | rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); |
2691d51d | 2652 | |
c4ff7cbf EG |
2653 | /* Give the FW up to 5 second (500*10ms) */ |
2654 | } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); | |
2691d51d EG |
2655 | |
2656 | DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", | |
2657 | cnt*delay, rc, seq); | |
2658 | ||
2659 | /* is this a reply to our command? */ | |
2660 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) | |
2661 | rc &= FW_MSG_CODE_MASK; | |
2662 | else { | |
2663 | /* FW BUG! */ | |
2664 | BNX2X_ERR("FW failed to respond!\n"); | |
2665 | bnx2x_fw_dump(bp); | |
2666 | rc = 0; | |
2667 | } | |
c4ff7cbf | 2668 | mutex_unlock(&bp->fw_mb_mutex); |
2691d51d EG |
2669 | |
2670 | return rc; | |
2671 | } | |
2672 | ||
ec6ba945 | 2673 | |
619c5cb6 VZ |
2674 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) |
2675 | { | |
2676 | if (CHIP_IS_E1x(bp)) { | |
2677 | struct tstorm_eth_function_common_config tcfg = {0}; | |
2678 | ||
2679 | storm_memset_func_cfg(bp, &tcfg, p->func_id); | |
2680 | } | |
2681 | ||
2682 | /* Enable the function in the FW */ | |
2683 | storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); | |
2684 | storm_memset_func_en(bp, p->func_id, 1); | |
2685 | ||
2686 | /* spq */ | |
2687 | if (p->func_flgs & FUNC_FLG_SPQ) { | |
2688 | storm_memset_spq_addr(bp, p->spq_map, p->func_id); | |
2689 | REG_WR(bp, XSEM_REG_FAST_MEMORY + | |
2690 | XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); | |
2691 | } | |
2692 | } | |
2693 | ||
6383c0b3 AE |
2694 | /** |
2695 | * bnx2x_get_tx_only_flags - Return common flags | |
2696 | * | |
2697 | * @bp device handle | |
2698 | * @fp queue handle | |
2699 | * @zero_stats TRUE if statistics zeroing is needed | |
2700 | * | |
2701 | * Return the flags that are common for the Tx-only and not normal connections. | |
2702 | */ | |
2703 | static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, | |
2704 | struct bnx2x_fastpath *fp, | |
2705 | bool zero_stats) | |
28912902 | 2706 | { |
619c5cb6 VZ |
2707 | unsigned long flags = 0; |
2708 | ||
2709 | /* PF driver will always initialize the Queue to an ACTIVE state */ | |
2710 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); | |
28912902 | 2711 | |
6383c0b3 AE |
2712 | /* tx only connections collect statistics (on the same index as the |
2713 | * parent connection). The statistics are zeroed when the parent | |
2714 | * connection is initialized. | |
2715 | */ | |
50f0a562 BW |
2716 | |
2717 | __set_bit(BNX2X_Q_FLG_STATS, &flags); | |
2718 | if (zero_stats) | |
2719 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); | |
2720 | ||
6383c0b3 AE |
2721 | |
2722 | return flags; | |
2723 | } | |
2724 | ||
2725 | static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, | |
2726 | struct bnx2x_fastpath *fp, | |
2727 | bool leading) | |
2728 | { | |
2729 | unsigned long flags = 0; | |
2730 | ||
619c5cb6 VZ |
2731 | /* calculate other queue flags */ |
2732 | if (IS_MF_SD(bp)) | |
2733 | __set_bit(BNX2X_Q_FLG_OV, &flags); | |
28912902 | 2734 | |
a3348722 | 2735 | if (IS_FCOE_FP(fp)) { |
619c5cb6 | 2736 | __set_bit(BNX2X_Q_FLG_FCOE, &flags); |
a3348722 BW |
2737 | /* For FCoE - force usage of default priority (for afex) */ |
2738 | __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); | |
2739 | } | |
523224a3 | 2740 | |
f5219d8e | 2741 | if (!fp->disable_tpa) { |
619c5cb6 | 2742 | __set_bit(BNX2X_Q_FLG_TPA, &flags); |
f5219d8e | 2743 | __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); |
621b4d66 DK |
2744 | if (fp->mode == TPA_MODE_GRO) |
2745 | __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); | |
f5219d8e | 2746 | } |
619c5cb6 | 2747 | |
619c5cb6 VZ |
2748 | if (leading) { |
2749 | __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); | |
2750 | __set_bit(BNX2X_Q_FLG_MCAST, &flags); | |
2751 | } | |
523224a3 | 2752 | |
619c5cb6 VZ |
2753 | /* Always set HW VLAN stripping */ |
2754 | __set_bit(BNX2X_Q_FLG_VLAN, &flags); | |
523224a3 | 2755 | |
a3348722 BW |
2756 | /* configure silent vlan removal */ |
2757 | if (IS_MF_AFEX(bp)) | |
2758 | __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); | |
2759 | ||
6383c0b3 AE |
2760 | |
2761 | return flags | bnx2x_get_common_flags(bp, fp, true); | |
523224a3 DK |
2762 | } |
2763 | ||
619c5cb6 | 2764 | static void bnx2x_pf_q_prep_general(struct bnx2x *bp, |
6383c0b3 AE |
2765 | struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, |
2766 | u8 cos) | |
619c5cb6 VZ |
2767 | { |
2768 | gen_init->stat_id = bnx2x_stats_id(fp); | |
2769 | gen_init->spcl_id = fp->cl_id; | |
2770 | ||
2771 | /* Always use mini-jumbo MTU for FCoE L2 ring */ | |
2772 | if (IS_FCOE_FP(fp)) | |
2773 | gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; | |
2774 | else | |
2775 | gen_init->mtu = bp->dev->mtu; | |
6383c0b3 AE |
2776 | |
2777 | gen_init->cos = cos; | |
619c5cb6 VZ |
2778 | } |
2779 | ||
2780 | static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |
523224a3 | 2781 | struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, |
619c5cb6 | 2782 | struct bnx2x_rxq_setup_params *rxq_init) |
523224a3 | 2783 | { |
619c5cb6 | 2784 | u8 max_sge = 0; |
523224a3 DK |
2785 | u16 sge_sz = 0; |
2786 | u16 tpa_agg_size = 0; | |
2787 | ||
523224a3 | 2788 | if (!fp->disable_tpa) { |
dfacf138 DK |
2789 | pause->sge_th_lo = SGE_TH_LO(bp); |
2790 | pause->sge_th_hi = SGE_TH_HI(bp); | |
2791 | ||
2792 | /* validate SGE ring has enough to cross high threshold */ | |
2793 | WARN_ON(bp->dropless_fc && | |
2794 | pause->sge_th_hi + FW_PREFETCH_CNT > | |
2795 | MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); | |
2796 | ||
523224a3 DK |
2797 | tpa_agg_size = min_t(u32, |
2798 | (min_t(u32, 8, MAX_SKB_FRAGS) * | |
2799 | SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); | |
2800 | max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> | |
2801 | SGE_PAGE_SHIFT; | |
2802 | max_sge = ((max_sge + PAGES_PER_SGE - 1) & | |
2803 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; | |
2804 | sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, | |
2805 | 0xffff); | |
2806 | } | |
2807 | ||
2808 | /* pause - not for e1 */ | |
2809 | if (!CHIP_IS_E1(bp)) { | |
dfacf138 DK |
2810 | pause->bd_th_lo = BD_TH_LO(bp); |
2811 | pause->bd_th_hi = BD_TH_HI(bp); | |
2812 | ||
2813 | pause->rcq_th_lo = RCQ_TH_LO(bp); | |
2814 | pause->rcq_th_hi = RCQ_TH_HI(bp); | |
2815 | /* | |
2816 | * validate that rings have enough entries to cross | |
2817 | * high thresholds | |
2818 | */ | |
2819 | WARN_ON(bp->dropless_fc && | |
2820 | pause->bd_th_hi + FW_PREFETCH_CNT > | |
2821 | bp->rx_ring_size); | |
2822 | WARN_ON(bp->dropless_fc && | |
2823 | pause->rcq_th_hi + FW_PREFETCH_CNT > | |
2824 | NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); | |
619c5cb6 | 2825 | |
523224a3 DK |
2826 | pause->pri_map = 1; |
2827 | } | |
2828 | ||
2829 | /* rxq setup */ | |
523224a3 DK |
2830 | rxq_init->dscr_map = fp->rx_desc_mapping; |
2831 | rxq_init->sge_map = fp->rx_sge_mapping; | |
2832 | rxq_init->rcq_map = fp->rx_comp_mapping; | |
2833 | rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; | |
a8c94b91 | 2834 | |
619c5cb6 VZ |
2835 | /* This should be a maximum number of data bytes that may be |
2836 | * placed on the BD (not including paddings). | |
2837 | */ | |
e52fcb24 ED |
2838 | rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - |
2839 | BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; | |
a8c94b91 | 2840 | |
523224a3 | 2841 | rxq_init->cl_qzone_id = fp->cl_qzone_id; |
523224a3 DK |
2842 | rxq_init->tpa_agg_sz = tpa_agg_size; |
2843 | rxq_init->sge_buf_sz = sge_sz; | |
2844 | rxq_init->max_sges_pkt = max_sge; | |
619c5cb6 | 2845 | rxq_init->rss_engine_id = BP_FUNC(bp); |
259afa1f | 2846 | rxq_init->mcast_engine_id = BP_FUNC(bp); |
619c5cb6 VZ |
2847 | |
2848 | /* Maximum number or simultaneous TPA aggregation for this Queue. | |
2849 | * | |
2850 | * For PF Clients it should be the maximum avaliable number. | |
2851 | * VF driver(s) may want to define it to a smaller value. | |
2852 | */ | |
dfacf138 | 2853 | rxq_init->max_tpa_queues = MAX_AGG_QS(bp); |
619c5cb6 | 2854 | |
523224a3 DK |
2855 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
2856 | rxq_init->fw_sb_id = fp->fw_sb_id; | |
2857 | ||
ec6ba945 VZ |
2858 | if (IS_FCOE_FP(fp)) |
2859 | rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; | |
2860 | else | |
6383c0b3 | 2861 | rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
a3348722 BW |
2862 | /* configure silent vlan removal |
2863 | * if multi function mode is afex, then mask default vlan | |
2864 | */ | |
2865 | if (IS_MF_AFEX(bp)) { | |
2866 | rxq_init->silent_removal_value = bp->afex_def_vlan_tag; | |
2867 | rxq_init->silent_removal_mask = VLAN_VID_MASK; | |
2868 | } | |
523224a3 DK |
2869 | } |
2870 | ||
619c5cb6 | 2871 | static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, |
6383c0b3 AE |
2872 | struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, |
2873 | u8 cos) | |
523224a3 | 2874 | { |
6383c0b3 AE |
2875 | txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; |
2876 | txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; | |
523224a3 DK |
2877 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; |
2878 | txq_init->fw_sb_id = fp->fw_sb_id; | |
ec6ba945 | 2879 | |
619c5cb6 VZ |
2880 | /* |
2881 | * set the tss leading client id for TX classfication == | |
2882 | * leading RSS client id | |
2883 | */ | |
2884 | txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); | |
2885 | ||
ec6ba945 VZ |
2886 | if (IS_FCOE_FP(fp)) { |
2887 | txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; | |
2888 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; | |
2889 | } | |
523224a3 DK |
2890 | } |
2891 | ||
8d96286a | 2892 | static void bnx2x_pf_init(struct bnx2x *bp) |
523224a3 DK |
2893 | { |
2894 | struct bnx2x_func_init_params func_init = {0}; | |
523224a3 DK |
2895 | struct event_ring_data eq_data = { {0} }; |
2896 | u16 flags; | |
2897 | ||
619c5cb6 | 2898 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2899 | /* reset IGU PF statistics: MSIX + ATTN */ |
2900 | /* PF */ | |
2901 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
2902 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
2903 | (CHIP_MODE_IS_4_PORT(bp) ? | |
2904 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
2905 | /* ATTN */ | |
2906 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
2907 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
2908 | BNX2X_IGU_STAS_MSG_PF_CNT*4 + | |
2909 | (CHIP_MODE_IS_4_PORT(bp) ? | |
2910 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
2911 | } | |
2912 | ||
523224a3 DK |
2913 | /* function setup flags */ |
2914 | flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); | |
2915 | ||
619c5cb6 VZ |
2916 | /* This flag is relevant for E1x only. |
2917 | * E2 doesn't have a TPA configuration in a function level. | |
523224a3 | 2918 | */ |
619c5cb6 | 2919 | flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; |
523224a3 DK |
2920 | |
2921 | func_init.func_flgs = flags; | |
2922 | func_init.pf_id = BP_FUNC(bp); | |
2923 | func_init.func_id = BP_FUNC(bp); | |
523224a3 DK |
2924 | func_init.spq_map = bp->spq_mapping; |
2925 | func_init.spq_prod = bp->spq_prod_idx; | |
2926 | ||
2927 | bnx2x_func_init(bp, &func_init); | |
2928 | ||
2929 | memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); | |
2930 | ||
2931 | /* | |
619c5cb6 VZ |
2932 | * Congestion management values depend on the link rate |
2933 | * There is no active link so initial link rate is set to 10 Gbps. | |
2934 | * When the link comes up The congestion management values are | |
2935 | * re-calculated according to the actual link rate. | |
2936 | */ | |
523224a3 DK |
2937 | bp->link_vars.line_speed = SPEED_10000; |
2938 | bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); | |
2939 | ||
2940 | /* Only the PMF sets the HW */ | |
2941 | if (bp->port.pmf) | |
2942 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2943 | ||
523224a3 DK |
2944 | /* init Event Queue */ |
2945 | eq_data.base_addr.hi = U64_HI(bp->eq_mapping); | |
2946 | eq_data.base_addr.lo = U64_LO(bp->eq_mapping); | |
2947 | eq_data.producer = bp->eq_prod; | |
2948 | eq_data.index_id = HC_SP_INDEX_EQ_CONS; | |
2949 | eq_data.sb_id = DEF_SB_ID; | |
2950 | storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); | |
2951 | } | |
2952 | ||
2953 | ||
2954 | static void bnx2x_e1h_disable(struct bnx2x *bp) | |
2955 | { | |
2956 | int port = BP_PORT(bp); | |
2957 | ||
619c5cb6 | 2958 | bnx2x_tx_disable(bp); |
523224a3 DK |
2959 | |
2960 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
523224a3 DK |
2961 | } |
2962 | ||
2963 | static void bnx2x_e1h_enable(struct bnx2x *bp) | |
2964 | { | |
2965 | int port = BP_PORT(bp); | |
2966 | ||
2967 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); | |
2968 | ||
2969 | /* Tx queue should be only reenabled */ | |
2970 | netif_tx_wake_all_queues(bp->dev); | |
2971 | ||
2972 | /* | |
2973 | * Should not call netif_carrier_on since it will be called if the link | |
2974 | * is up when checking for link state | |
2975 | */ | |
2976 | } | |
2977 | ||
1d187b34 BW |
2978 | #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 |
2979 | ||
2980 | static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) | |
2981 | { | |
2982 | struct eth_stats_info *ether_stat = | |
2983 | &bp->slowpath->drv_info_to_mcp.ether_stat; | |
2984 | ||
2985 | /* leave last char as NULL */ | |
2986 | memcpy(ether_stat->version, DRV_MODULE_VERSION, | |
2987 | ETH_STAT_INFO_VERSION_LEN - 1); | |
2988 | ||
2989 | bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj, | |
2990 | DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, | |
2991 | ether_stat->mac_local); | |
2992 | ||
2993 | ether_stat->mtu_size = bp->dev->mtu; | |
2994 | ||
2995 | if (bp->dev->features & NETIF_F_RXCSUM) | |
2996 | ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; | |
2997 | if (bp->dev->features & NETIF_F_TSO) | |
2998 | ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; | |
2999 | ether_stat->feature_flags |= bp->common.boot_mode; | |
3000 | ||
3001 | ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; | |
3002 | ||
3003 | ether_stat->txq_size = bp->tx_ring_size; | |
3004 | ether_stat->rxq_size = bp->rx_ring_size; | |
3005 | } | |
3006 | ||
3007 | static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) | |
3008 | { | |
f2fd5c34 | 3009 | #ifdef BCM_CNIC |
1d187b34 BW |
3010 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; |
3011 | struct fcoe_stats_info *fcoe_stat = | |
3012 | &bp->slowpath->drv_info_to_mcp.fcoe_stat; | |
3013 | ||
3014 | memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN); | |
3015 | ||
3016 | fcoe_stat->qos_priority = | |
3017 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; | |
3018 | ||
3019 | /* insert FCoE stats from ramrod response */ | |
3020 | if (!NO_FCOE(bp)) { | |
3021 | struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = | |
3022 | &bp->fw_stats_data->queue_stats[FCOE_IDX]. | |
3023 | tstorm_queue_statistics; | |
3024 | ||
3025 | struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = | |
3026 | &bp->fw_stats_data->queue_stats[FCOE_IDX]. | |
3027 | xstorm_queue_statistics; | |
3028 | ||
3029 | struct fcoe_statistics_params *fw_fcoe_stat = | |
3030 | &bp->fw_stats_data->fcoe; | |
3031 | ||
3032 | ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo, | |
3033 | fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); | |
3034 | ||
3035 | ADD_64(fcoe_stat->rx_bytes_hi, | |
3036 | fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, | |
3037 | fcoe_stat->rx_bytes_lo, | |
3038 | fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); | |
3039 | ||
3040 | ADD_64(fcoe_stat->rx_bytes_hi, | |
3041 | fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, | |
3042 | fcoe_stat->rx_bytes_lo, | |
3043 | fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); | |
3044 | ||
3045 | ADD_64(fcoe_stat->rx_bytes_hi, | |
3046 | fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, | |
3047 | fcoe_stat->rx_bytes_lo, | |
3048 | fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); | |
3049 | ||
3050 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
3051 | fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); | |
3052 | ||
3053 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
3054 | fcoe_q_tstorm_stats->rcv_ucast_pkts); | |
3055 | ||
3056 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
3057 | fcoe_q_tstorm_stats->rcv_bcast_pkts); | |
3058 | ||
3059 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
f33f1fcc | 3060 | fcoe_q_tstorm_stats->rcv_mcast_pkts); |
1d187b34 BW |
3061 | |
3062 | ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo, | |
3063 | fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); | |
3064 | ||
3065 | ADD_64(fcoe_stat->tx_bytes_hi, | |
3066 | fcoe_q_xstorm_stats->ucast_bytes_sent.hi, | |
3067 | fcoe_stat->tx_bytes_lo, | |
3068 | fcoe_q_xstorm_stats->ucast_bytes_sent.lo); | |
3069 | ||
3070 | ADD_64(fcoe_stat->tx_bytes_hi, | |
3071 | fcoe_q_xstorm_stats->bcast_bytes_sent.hi, | |
3072 | fcoe_stat->tx_bytes_lo, | |
3073 | fcoe_q_xstorm_stats->bcast_bytes_sent.lo); | |
3074 | ||
3075 | ADD_64(fcoe_stat->tx_bytes_hi, | |
3076 | fcoe_q_xstorm_stats->mcast_bytes_sent.hi, | |
3077 | fcoe_stat->tx_bytes_lo, | |
3078 | fcoe_q_xstorm_stats->mcast_bytes_sent.lo); | |
3079 | ||
3080 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3081 | fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); | |
3082 | ||
3083 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3084 | fcoe_q_xstorm_stats->ucast_pkts_sent); | |
3085 | ||
3086 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3087 | fcoe_q_xstorm_stats->bcast_pkts_sent); | |
3088 | ||
3089 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3090 | fcoe_q_xstorm_stats->mcast_pkts_sent); | |
3091 | } | |
3092 | ||
1d187b34 BW |
3093 | /* ask L5 driver to add data to the struct */ |
3094 | bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); | |
3095 | #endif | |
3096 | } | |
3097 | ||
3098 | static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) | |
3099 | { | |
f2fd5c34 | 3100 | #ifdef BCM_CNIC |
1d187b34 BW |
3101 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; |
3102 | struct iscsi_stats_info *iscsi_stat = | |
3103 | &bp->slowpath->drv_info_to_mcp.iscsi_stat; | |
3104 | ||
3105 | memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); | |
3106 | ||
3107 | iscsi_stat->qos_priority = | |
3108 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; | |
3109 | ||
1d187b34 BW |
3110 | /* ask L5 driver to add data to the struct */ |
3111 | bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); | |
3112 | #endif | |
3113 | } | |
3114 | ||
0793f83f DK |
3115 | /* called due to MCP event (on pmf): |
3116 | * reread new bandwidth configuration | |
3117 | * configure FW | |
3118 | * notify others function about the change | |
3119 | */ | |
3120 | static inline void bnx2x_config_mf_bw(struct bnx2x *bp) | |
3121 | { | |
3122 | if (bp->link_vars.link_up) { | |
3123 | bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); | |
3124 | bnx2x_link_sync_notify(bp); | |
3125 | } | |
3126 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3127 | } | |
3128 | ||
3129 | static inline void bnx2x_set_mf_bw(struct bnx2x *bp) | |
3130 | { | |
3131 | bnx2x_config_mf_bw(bp); | |
3132 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); | |
3133 | } | |
3134 | ||
1d187b34 BW |
3135 | static void bnx2x_handle_drv_info_req(struct bnx2x *bp) |
3136 | { | |
3137 | enum drv_info_opcode op_code; | |
3138 | u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); | |
3139 | ||
3140 | /* if drv_info version supported by MFW doesn't match - send NACK */ | |
3141 | if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { | |
3142 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3143 | return; | |
3144 | } | |
3145 | ||
3146 | op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> | |
3147 | DRV_INFO_CONTROL_OP_CODE_SHIFT; | |
3148 | ||
3149 | memset(&bp->slowpath->drv_info_to_mcp, 0, | |
3150 | sizeof(union drv_info_to_mcp)); | |
3151 | ||
3152 | switch (op_code) { | |
3153 | case ETH_STATS_OPCODE: | |
3154 | bnx2x_drv_info_ether_stat(bp); | |
3155 | break; | |
3156 | case FCOE_STATS_OPCODE: | |
3157 | bnx2x_drv_info_fcoe_stat(bp); | |
3158 | break; | |
3159 | case ISCSI_STATS_OPCODE: | |
3160 | bnx2x_drv_info_iscsi_stat(bp); | |
3161 | break; | |
3162 | default: | |
3163 | /* if op code isn't supported - send NACK */ | |
3164 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3165 | return; | |
3166 | } | |
3167 | ||
3168 | /* if we got drv_info attn from MFW then these fields are defined in | |
3169 | * shmem2 for sure | |
3170 | */ | |
3171 | SHMEM2_WR(bp, drv_info_host_addr_lo, | |
3172 | U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3173 | SHMEM2_WR(bp, drv_info_host_addr_hi, | |
3174 | U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3175 | ||
3176 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); | |
3177 | } | |
3178 | ||
523224a3 DK |
3179 | static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) |
3180 | { | |
3181 | DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); | |
3182 | ||
3183 | if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { | |
3184 | ||
3185 | /* | |
3186 | * This is the only place besides the function initialization | |
3187 | * where the bp->flags can change so it is done without any | |
3188 | * locks | |
3189 | */ | |
f2e0899f | 3190 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
51c1a580 | 3191 | DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); |
523224a3 DK |
3192 | bp->flags |= MF_FUNC_DIS; |
3193 | ||
3194 | bnx2x_e1h_disable(bp); | |
3195 | } else { | |
51c1a580 | 3196 | DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); |
523224a3 DK |
3197 | bp->flags &= ~MF_FUNC_DIS; |
3198 | ||
3199 | bnx2x_e1h_enable(bp); | |
3200 | } | |
3201 | dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; | |
3202 | } | |
3203 | if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { | |
0793f83f | 3204 | bnx2x_config_mf_bw(bp); |
523224a3 DK |
3205 | dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; |
3206 | } | |
3207 | ||
3208 | /* Report results to MCP */ | |
3209 | if (dcc_event) | |
3210 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); | |
3211 | else | |
3212 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); | |
3213 | } | |
3214 | ||
3215 | /* must be called under the spq lock */ | |
3216 | static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) | |
3217 | { | |
3218 | struct eth_spe *next_spe = bp->spq_prod_bd; | |
3219 | ||
3220 | if (bp->spq_prod_bd == bp->spq_last_bd) { | |
3221 | bp->spq_prod_bd = bp->spq; | |
3222 | bp->spq_prod_idx = 0; | |
51c1a580 | 3223 | DP(BNX2X_MSG_SP, "end of spq\n"); |
523224a3 DK |
3224 | } else { |
3225 | bp->spq_prod_bd++; | |
3226 | bp->spq_prod_idx++; | |
3227 | } | |
3228 | return next_spe; | |
3229 | } | |
3230 | ||
3231 | /* must be called under the spq lock */ | |
28912902 MC |
3232 | static inline void bnx2x_sp_prod_update(struct bnx2x *bp) |
3233 | { | |
3234 | int func = BP_FUNC(bp); | |
3235 | ||
53e51e2f VZ |
3236 | /* |
3237 | * Make sure that BD data is updated before writing the producer: | |
3238 | * BD data is written to the memory, the producer is read from the | |
3239 | * memory, thus we need a full memory barrier to ensure the ordering. | |
3240 | */ | |
3241 | mb(); | |
28912902 | 3242 | |
523224a3 | 3243 | REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), |
f85582f8 | 3244 | bp->spq_prod_idx); |
28912902 MC |
3245 | mmiowb(); |
3246 | } | |
3247 | ||
619c5cb6 VZ |
3248 | /** |
3249 | * bnx2x_is_contextless_ramrod - check if the current command ends on EQ | |
3250 | * | |
3251 | * @cmd: command to check | |
3252 | * @cmd_type: command type | |
3253 | */ | |
3254 | static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) | |
3255 | { | |
3256 | if ((cmd_type == NONE_CONNECTION_TYPE) || | |
6383c0b3 | 3257 | (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || |
619c5cb6 VZ |
3258 | (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || |
3259 | (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || | |
3260 | (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || | |
3261 | (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || | |
3262 | (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) | |
3263 | return true; | |
3264 | else | |
3265 | return false; | |
3266 | ||
3267 | } | |
3268 | ||
3269 | ||
3270 | /** | |
3271 | * bnx2x_sp_post - place a single command on an SP ring | |
3272 | * | |
3273 | * @bp: driver handle | |
3274 | * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) | |
3275 | * @cid: SW CID the command is related to | |
3276 | * @data_hi: command private data address (high 32 bits) | |
3277 | * @data_lo: command private data address (low 32 bits) | |
3278 | * @cmd_type: command type (e.g. NONE, ETH) | |
3279 | * | |
3280 | * SP data is handled as if it's always an address pair, thus data fields are | |
3281 | * not swapped to little endian in upper functions. Instead this function swaps | |
3282 | * data as if it's two u32 fields. | |
3283 | */ | |
9f6c9258 | 3284 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
619c5cb6 | 3285 | u32 data_hi, u32 data_lo, int cmd_type) |
a2fbb9ea | 3286 | { |
28912902 | 3287 | struct eth_spe *spe; |
523224a3 | 3288 | u16 type; |
619c5cb6 | 3289 | bool common = bnx2x_is_contextless_ramrod(command, cmd_type); |
a2fbb9ea | 3290 | |
a2fbb9ea | 3291 | #ifdef BNX2X_STOP_ON_ERROR |
51c1a580 MS |
3292 | if (unlikely(bp->panic)) { |
3293 | BNX2X_ERR("Can't post SP when there is panic\n"); | |
a2fbb9ea | 3294 | return -EIO; |
51c1a580 | 3295 | } |
a2fbb9ea ET |
3296 | #endif |
3297 | ||
34f80b04 | 3298 | spin_lock_bh(&bp->spq_lock); |
a2fbb9ea | 3299 | |
6e30dd4e VZ |
3300 | if (common) { |
3301 | if (!atomic_read(&bp->eq_spq_left)) { | |
3302 | BNX2X_ERR("BUG! EQ ring full!\n"); | |
3303 | spin_unlock_bh(&bp->spq_lock); | |
3304 | bnx2x_panic(); | |
3305 | return -EBUSY; | |
3306 | } | |
3307 | } else if (!atomic_read(&bp->cq_spq_left)) { | |
3308 | BNX2X_ERR("BUG! SPQ ring full!\n"); | |
3309 | spin_unlock_bh(&bp->spq_lock); | |
3310 | bnx2x_panic(); | |
3311 | return -EBUSY; | |
a2fbb9ea | 3312 | } |
f1410647 | 3313 | |
28912902 MC |
3314 | spe = bnx2x_sp_get_next(bp); |
3315 | ||
a2fbb9ea | 3316 | /* CID needs port number to be encoded int it */ |
28912902 | 3317 | spe->hdr.conn_and_cmd_data = |
cdaa7cb8 VZ |
3318 | cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | |
3319 | HW_CID(bp, cid)); | |
523224a3 | 3320 | |
619c5cb6 | 3321 | type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; |
a2fbb9ea | 3322 | |
523224a3 DK |
3323 | type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & |
3324 | SPE_HDR_FUNCTION_ID); | |
a2fbb9ea | 3325 | |
523224a3 DK |
3326 | spe->hdr.type = cpu_to_le16(type); |
3327 | ||
3328 | spe->data.update_data_addr.hi = cpu_to_le32(data_hi); | |
3329 | spe->data.update_data_addr.lo = cpu_to_le32(data_lo); | |
3330 | ||
d6cae238 VZ |
3331 | /* |
3332 | * It's ok if the actual decrement is issued towards the memory | |
3333 | * somewhere between the spin_lock and spin_unlock. Thus no | |
3334 | * more explict memory barrier is needed. | |
3335 | */ | |
3336 | if (common) | |
3337 | atomic_dec(&bp->eq_spq_left); | |
3338 | else | |
3339 | atomic_dec(&bp->cq_spq_left); | |
6e30dd4e | 3340 | |
a2fbb9ea | 3341 | |
51c1a580 MS |
3342 | DP(BNX2X_MSG_SP, |
3343 | "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", | |
cdaa7cb8 VZ |
3344 | bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), |
3345 | (u32)(U64_LO(bp->spq_mapping) + | |
d6cae238 | 3346 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, |
6e30dd4e VZ |
3347 | HW_CID(bp, cid), data_hi, data_lo, type, |
3348 | atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); | |
cdaa7cb8 | 3349 | |
28912902 | 3350 | bnx2x_sp_prod_update(bp); |
34f80b04 | 3351 | spin_unlock_bh(&bp->spq_lock); |
a2fbb9ea ET |
3352 | return 0; |
3353 | } | |
3354 | ||
3355 | /* acquire split MCP access lock register */ | |
4a37fb66 | 3356 | static int bnx2x_acquire_alr(struct bnx2x *bp) |
a2fbb9ea | 3357 | { |
72fd0718 | 3358 | u32 j, val; |
34f80b04 | 3359 | int rc = 0; |
a2fbb9ea ET |
3360 | |
3361 | might_sleep(); | |
72fd0718 | 3362 | for (j = 0; j < 1000; j++) { |
a2fbb9ea ET |
3363 | val = (1UL << 31); |
3364 | REG_WR(bp, GRCBASE_MCP + 0x9c, val); | |
3365 | val = REG_RD(bp, GRCBASE_MCP + 0x9c); | |
3366 | if (val & (1L << 31)) | |
3367 | break; | |
3368 | ||
3369 | msleep(5); | |
3370 | } | |
a2fbb9ea | 3371 | if (!(val & (1L << 31))) { |
19680c48 | 3372 | BNX2X_ERR("Cannot acquire MCP access lock register\n"); |
a2fbb9ea ET |
3373 | rc = -EBUSY; |
3374 | } | |
3375 | ||
3376 | return rc; | |
3377 | } | |
3378 | ||
4a37fb66 YG |
3379 | /* release split MCP access lock register */ |
3380 | static void bnx2x_release_alr(struct bnx2x *bp) | |
a2fbb9ea | 3381 | { |
72fd0718 | 3382 | REG_WR(bp, GRCBASE_MCP + 0x9c, 0); |
a2fbb9ea ET |
3383 | } |
3384 | ||
523224a3 DK |
3385 | #define BNX2X_DEF_SB_ATT_IDX 0x0001 |
3386 | #define BNX2X_DEF_SB_IDX 0x0002 | |
3387 | ||
a2fbb9ea ET |
3388 | static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) |
3389 | { | |
523224a3 | 3390 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
a2fbb9ea ET |
3391 | u16 rc = 0; |
3392 | ||
3393 | barrier(); /* status block is written to by the chip */ | |
a2fbb9ea ET |
3394 | if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { |
3395 | bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; | |
523224a3 | 3396 | rc |= BNX2X_DEF_SB_ATT_IDX; |
a2fbb9ea | 3397 | } |
523224a3 DK |
3398 | |
3399 | if (bp->def_idx != def_sb->sp_sb.running_index) { | |
3400 | bp->def_idx = def_sb->sp_sb.running_index; | |
3401 | rc |= BNX2X_DEF_SB_IDX; | |
a2fbb9ea | 3402 | } |
523224a3 DK |
3403 | |
3404 | /* Do not reorder: indecies reading should complete before handling */ | |
3405 | barrier(); | |
a2fbb9ea ET |
3406 | return rc; |
3407 | } | |
3408 | ||
3409 | /* | |
3410 | * slow path service functions | |
3411 | */ | |
3412 | ||
3413 | static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |
3414 | { | |
34f80b04 | 3415 | int port = BP_PORT(bp); |
a2fbb9ea ET |
3416 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
3417 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
877e9aa4 ET |
3418 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
3419 | NIG_REG_MASK_INTERRUPT_PORT0; | |
3fcaf2e5 | 3420 | u32 aeu_mask; |
87942b46 | 3421 | u32 nig_mask = 0; |
f2e0899f | 3422 | u32 reg_addr; |
a2fbb9ea | 3423 | |
a2fbb9ea ET |
3424 | if (bp->attn_state & asserted) |
3425 | BNX2X_ERR("IGU ERROR\n"); | |
3426 | ||
3fcaf2e5 EG |
3427 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
3428 | aeu_mask = REG_RD(bp, aeu_addr); | |
3429 | ||
a2fbb9ea | 3430 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
3fcaf2e5 | 3431 | aeu_mask, asserted); |
72fd0718 | 3432 | aeu_mask &= ~(asserted & 0x3ff); |
3fcaf2e5 | 3433 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 3434 | |
3fcaf2e5 EG |
3435 | REG_WR(bp, aeu_addr, aeu_mask); |
3436 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea | 3437 | |
3fcaf2e5 | 3438 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
a2fbb9ea | 3439 | bp->attn_state |= asserted; |
3fcaf2e5 | 3440 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
a2fbb9ea ET |
3441 | |
3442 | if (asserted & ATTN_HARD_WIRED_MASK) { | |
3443 | if (asserted & ATTN_NIG_FOR_FUNC) { | |
a2fbb9ea | 3444 | |
a5e9a7cf EG |
3445 | bnx2x_acquire_phy_lock(bp); |
3446 | ||
877e9aa4 | 3447 | /* save nig interrupt mask */ |
87942b46 | 3448 | nig_mask = REG_RD(bp, nig_int_mask_addr); |
a2fbb9ea | 3449 | |
361c391e YR |
3450 | /* If nig_mask is not set, no need to call the update |
3451 | * function. | |
3452 | */ | |
3453 | if (nig_mask) { | |
3454 | REG_WR(bp, nig_int_mask_addr, 0); | |
3455 | ||
3456 | bnx2x_link_attn(bp); | |
3457 | } | |
a2fbb9ea ET |
3458 | |
3459 | /* handle unicore attn? */ | |
3460 | } | |
3461 | if (asserted & ATTN_SW_TIMER_4_FUNC) | |
3462 | DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); | |
3463 | ||
3464 | if (asserted & GPIO_2_FUNC) | |
3465 | DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); | |
3466 | ||
3467 | if (asserted & GPIO_3_FUNC) | |
3468 | DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); | |
3469 | ||
3470 | if (asserted & GPIO_4_FUNC) | |
3471 | DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); | |
3472 | ||
3473 | if (port == 0) { | |
3474 | if (asserted & ATTN_GENERAL_ATTN_1) { | |
3475 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); | |
3476 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); | |
3477 | } | |
3478 | if (asserted & ATTN_GENERAL_ATTN_2) { | |
3479 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); | |
3480 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); | |
3481 | } | |
3482 | if (asserted & ATTN_GENERAL_ATTN_3) { | |
3483 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); | |
3484 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); | |
3485 | } | |
3486 | } else { | |
3487 | if (asserted & ATTN_GENERAL_ATTN_4) { | |
3488 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); | |
3489 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); | |
3490 | } | |
3491 | if (asserted & ATTN_GENERAL_ATTN_5) { | |
3492 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); | |
3493 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); | |
3494 | } | |
3495 | if (asserted & ATTN_GENERAL_ATTN_6) { | |
3496 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); | |
3497 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); | |
3498 | } | |
3499 | } | |
3500 | ||
3501 | } /* if hardwired */ | |
3502 | ||
f2e0899f DK |
3503 | if (bp->common.int_block == INT_BLOCK_HC) |
3504 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
3505 | COMMAND_REG_ATTN_BITS_SET); | |
3506 | else | |
3507 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); | |
3508 | ||
3509 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, | |
3510 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
3511 | REG_WR(bp, reg_addr, asserted); | |
a2fbb9ea ET |
3512 | |
3513 | /* now set back the mask */ | |
a5e9a7cf | 3514 | if (asserted & ATTN_NIG_FOR_FUNC) { |
87942b46 | 3515 | REG_WR(bp, nig_int_mask_addr, nig_mask); |
a5e9a7cf EG |
3516 | bnx2x_release_phy_lock(bp); |
3517 | } | |
a2fbb9ea ET |
3518 | } |
3519 | ||
fd4ef40d EG |
3520 | static inline void bnx2x_fan_failure(struct bnx2x *bp) |
3521 | { | |
3522 | int port = BP_PORT(bp); | |
b7737c9b | 3523 | u32 ext_phy_config; |
fd4ef40d | 3524 | /* mark the failure */ |
b7737c9b YR |
3525 | ext_phy_config = |
3526 | SHMEM_RD(bp, | |
3527 | dev_info.port_hw_config[port].external_phy_config); | |
3528 | ||
3529 | ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | |
3530 | ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; | |
fd4ef40d | 3531 | SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, |
b7737c9b | 3532 | ext_phy_config); |
fd4ef40d EG |
3533 | |
3534 | /* log the failure */ | |
51c1a580 MS |
3535 | netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" |
3536 | "Please contact OEM Support for assistance\n"); | |
8304859a AE |
3537 | |
3538 | /* | |
3539 | * Scheudle device reset (unload) | |
3540 | * This is due to some boards consuming sufficient power when driver is | |
3541 | * up to overheat if fan fails. | |
3542 | */ | |
3543 | smp_mb__before_clear_bit(); | |
3544 | set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); | |
3545 | smp_mb__after_clear_bit(); | |
3546 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
3547 | ||
fd4ef40d | 3548 | } |
ab6ad5a4 | 3549 | |
877e9aa4 | 3550 | static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
a2fbb9ea | 3551 | { |
34f80b04 | 3552 | int port = BP_PORT(bp); |
877e9aa4 | 3553 | int reg_offset; |
d90d96ba | 3554 | u32 val; |
877e9aa4 | 3555 | |
34f80b04 EG |
3556 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
3557 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
877e9aa4 | 3558 | |
34f80b04 | 3559 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { |
877e9aa4 ET |
3560 | |
3561 | val = REG_RD(bp, reg_offset); | |
3562 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; | |
3563 | REG_WR(bp, reg_offset, val); | |
3564 | ||
3565 | BNX2X_ERR("SPIO5 hw attention\n"); | |
3566 | ||
fd4ef40d | 3567 | /* Fan failure attention */ |
d90d96ba | 3568 | bnx2x_hw_reset_phy(&bp->link_params); |
fd4ef40d | 3569 | bnx2x_fan_failure(bp); |
877e9aa4 | 3570 | } |
34f80b04 | 3571 | |
3deb8167 | 3572 | if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { |
589abe3a EG |
3573 | bnx2x_acquire_phy_lock(bp); |
3574 | bnx2x_handle_module_detect_int(&bp->link_params); | |
3575 | bnx2x_release_phy_lock(bp); | |
3576 | } | |
3577 | ||
34f80b04 EG |
3578 | if (attn & HW_INTERRUT_ASSERT_SET_0) { |
3579 | ||
3580 | val = REG_RD(bp, reg_offset); | |
3581 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); | |
3582 | REG_WR(bp, reg_offset, val); | |
3583 | ||
3584 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", | |
0fc5d009 | 3585 | (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); |
34f80b04 EG |
3586 | bnx2x_panic(); |
3587 | } | |
877e9aa4 ET |
3588 | } |
3589 | ||
3590 | static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) | |
3591 | { | |
3592 | u32 val; | |
3593 | ||
0626b899 | 3594 | if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { |
877e9aa4 ET |
3595 | |
3596 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | |
3597 | BNX2X_ERR("DB hw attention 0x%x\n", val); | |
3598 | /* DORQ discard attention */ | |
3599 | if (val & 0x2) | |
3600 | BNX2X_ERR("FATAL error from DORQ\n"); | |
3601 | } | |
34f80b04 EG |
3602 | |
3603 | if (attn & HW_INTERRUT_ASSERT_SET_1) { | |
3604 | ||
3605 | int port = BP_PORT(bp); | |
3606 | int reg_offset; | |
3607 | ||
3608 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : | |
3609 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); | |
3610 | ||
3611 | val = REG_RD(bp, reg_offset); | |
3612 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); | |
3613 | REG_WR(bp, reg_offset, val); | |
3614 | ||
3615 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", | |
0fc5d009 | 3616 | (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); |
34f80b04 EG |
3617 | bnx2x_panic(); |
3618 | } | |
877e9aa4 ET |
3619 | } |
3620 | ||
3621 | static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) | |
3622 | { | |
3623 | u32 val; | |
3624 | ||
3625 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | |
3626 | ||
3627 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | |
3628 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | |
3629 | /* CFC error attention */ | |
3630 | if (val & 0x2) | |
3631 | BNX2X_ERR("FATAL error from CFC\n"); | |
3632 | } | |
3633 | ||
3634 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | |
877e9aa4 | 3635 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); |
619c5cb6 | 3636 | BNX2X_ERR("PXP hw attention-0 0x%x\n", val); |
877e9aa4 ET |
3637 | /* RQ_USDMDP_FIFO_OVERFLOW */ |
3638 | if (val & 0x18000) | |
3639 | BNX2X_ERR("FATAL error from PXP\n"); | |
619c5cb6 VZ |
3640 | |
3641 | if (!CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
3642 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); |
3643 | BNX2X_ERR("PXP hw attention-1 0x%x\n", val); | |
3644 | } | |
877e9aa4 | 3645 | } |
34f80b04 EG |
3646 | |
3647 | if (attn & HW_INTERRUT_ASSERT_SET_2) { | |
3648 | ||
3649 | int port = BP_PORT(bp); | |
3650 | int reg_offset; | |
3651 | ||
3652 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : | |
3653 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); | |
3654 | ||
3655 | val = REG_RD(bp, reg_offset); | |
3656 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); | |
3657 | REG_WR(bp, reg_offset, val); | |
3658 | ||
3659 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", | |
0fc5d009 | 3660 | (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); |
34f80b04 EG |
3661 | bnx2x_panic(); |
3662 | } | |
877e9aa4 ET |
3663 | } |
3664 | ||
3665 | static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) | |
3666 | { | |
34f80b04 EG |
3667 | u32 val; |
3668 | ||
877e9aa4 ET |
3669 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { |
3670 | ||
34f80b04 EG |
3671 | if (attn & BNX2X_PMF_LINK_ASSERT) { |
3672 | int func = BP_FUNC(bp); | |
3673 | ||
3674 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
a3348722 | 3675 | bnx2x_read_mf_cfg(bp); |
f2e0899f DK |
3676 | bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, |
3677 | func_mf_config[BP_ABS_FUNC(bp)].config); | |
3678 | val = SHMEM_RD(bp, | |
3679 | func_mb[BP_FW_MB_IDX(bp)].drv_status); | |
2691d51d EG |
3680 | if (val & DRV_STATUS_DCC_EVENT_MASK) |
3681 | bnx2x_dcc_event(bp, | |
3682 | (val & DRV_STATUS_DCC_EVENT_MASK)); | |
0793f83f DK |
3683 | |
3684 | if (val & DRV_STATUS_SET_MF_BW) | |
3685 | bnx2x_set_mf_bw(bp); | |
3686 | ||
1d187b34 BW |
3687 | if (val & DRV_STATUS_DRV_INFO_REQ) |
3688 | bnx2x_handle_drv_info_req(bp); | |
2691d51d | 3689 | if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) |
34f80b04 EG |
3690 | bnx2x_pmf_update(bp); |
3691 | ||
e4901dde | 3692 | if (bp->port.pmf && |
785b9b1a SR |
3693 | (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && |
3694 | bp->dcbx_enabled > 0) | |
e4901dde VZ |
3695 | /* start dcbx state machine */ |
3696 | bnx2x_dcbx_set_params(bp, | |
3697 | BNX2X_DCBX_STATE_NEG_RECEIVED); | |
a3348722 BW |
3698 | if (val & DRV_STATUS_AFEX_EVENT_MASK) |
3699 | bnx2x_handle_afex_cmd(bp, | |
3700 | val & DRV_STATUS_AFEX_EVENT_MASK); | |
3deb8167 YR |
3701 | if (bp->link_vars.periodic_flags & |
3702 | PERIODIC_FLAGS_LINK_EVENT) { | |
3703 | /* sync with link */ | |
3704 | bnx2x_acquire_phy_lock(bp); | |
3705 | bp->link_vars.periodic_flags &= | |
3706 | ~PERIODIC_FLAGS_LINK_EVENT; | |
3707 | bnx2x_release_phy_lock(bp); | |
3708 | if (IS_MF(bp)) | |
3709 | bnx2x_link_sync_notify(bp); | |
3710 | bnx2x_link_report(bp); | |
3711 | } | |
3712 | /* Always call it here: bnx2x_link_report() will | |
3713 | * prevent the link indication duplication. | |
3714 | */ | |
3715 | bnx2x__link_status_update(bp); | |
34f80b04 | 3716 | } else if (attn & BNX2X_MC_ASSERT_BITS) { |
877e9aa4 ET |
3717 | |
3718 | BNX2X_ERR("MC assert!\n"); | |
d6cae238 | 3719 | bnx2x_mc_assert(bp); |
877e9aa4 ET |
3720 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); |
3721 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); | |
3722 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); | |
3723 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); | |
3724 | bnx2x_panic(); | |
3725 | ||
3726 | } else if (attn & BNX2X_MCP_ASSERT) { | |
3727 | ||
3728 | BNX2X_ERR("MCP assert!\n"); | |
3729 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); | |
34f80b04 | 3730 | bnx2x_fw_dump(bp); |
877e9aa4 ET |
3731 | |
3732 | } else | |
3733 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); | |
3734 | } | |
3735 | ||
3736 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { | |
34f80b04 EG |
3737 | BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); |
3738 | if (attn & BNX2X_GRC_TIMEOUT) { | |
f2e0899f DK |
3739 | val = CHIP_IS_E1(bp) ? 0 : |
3740 | REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); | |
34f80b04 EG |
3741 | BNX2X_ERR("GRC time-out 0x%08x\n", val); |
3742 | } | |
3743 | if (attn & BNX2X_GRC_RSV) { | |
f2e0899f DK |
3744 | val = CHIP_IS_E1(bp) ? 0 : |
3745 | REG_RD(bp, MISC_REG_GRC_RSV_ATTN); | |
34f80b04 EG |
3746 | BNX2X_ERR("GRC reserved 0x%08x\n", val); |
3747 | } | |
877e9aa4 | 3748 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); |
877e9aa4 ET |
3749 | } |
3750 | } | |
3751 | ||
c9ee9206 VZ |
3752 | /* |
3753 | * Bits map: | |
3754 | * 0-7 - Engine0 load counter. | |
3755 | * 8-15 - Engine1 load counter. | |
3756 | * 16 - Engine0 RESET_IN_PROGRESS bit. | |
3757 | * 17 - Engine1 RESET_IN_PROGRESS bit. | |
3758 | * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function | |
3759 | * on the engine | |
3760 | * 19 - Engine1 ONE_IS_LOADED. | |
3761 | * 20 - Chip reset flow bit. When set none-leader must wait for both engines | |
3762 | * leader to complete (check for both RESET_IN_PROGRESS bits and not for | |
3763 | * just the one belonging to its engine). | |
3764 | * | |
3765 | */ | |
3766 | #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 | |
3767 | ||
3768 | #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff | |
3769 | #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 | |
3770 | #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 | |
3771 | #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 | |
3772 | #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 | |
3773 | #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 | |
3774 | #define BNX2X_GLOBAL_RESET_BIT 0x00040000 | |
3775 | ||
3776 | /* | |
3777 | * Set the GLOBAL_RESET bit. | |
3778 | * | |
3779 | * Should be run under rtnl lock | |
3780 | */ | |
3781 | void bnx2x_set_reset_global(struct bnx2x *bp) | |
3782 | { | |
f16da43b AE |
3783 | u32 val; |
3784 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
3785 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 3786 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); |
f16da43b | 3787 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 VZ |
3788 | } |
3789 | ||
3790 | /* | |
3791 | * Clear the GLOBAL_RESET bit. | |
3792 | * | |
3793 | * Should be run under rtnl lock | |
3794 | */ | |
3795 | static inline void bnx2x_clear_reset_global(struct bnx2x *bp) | |
3796 | { | |
f16da43b AE |
3797 | u32 val; |
3798 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
3799 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 3800 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); |
f16da43b | 3801 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 | 3802 | } |
f85582f8 | 3803 | |
72fd0718 | 3804 | /* |
c9ee9206 VZ |
3805 | * Checks the GLOBAL_RESET bit. |
3806 | * | |
72fd0718 VZ |
3807 | * should be run under rtnl lock |
3808 | */ | |
c9ee9206 VZ |
3809 | static inline bool bnx2x_reset_is_global(struct bnx2x *bp) |
3810 | { | |
3811 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3812 | ||
3813 | DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); | |
3814 | return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; | |
3815 | } | |
3816 | ||
3817 | /* | |
3818 | * Clear RESET_IN_PROGRESS bit for the current engine. | |
3819 | * | |
3820 | * Should be run under rtnl lock | |
3821 | */ | |
72fd0718 VZ |
3822 | static inline void bnx2x_set_reset_done(struct bnx2x *bp) |
3823 | { | |
f16da43b | 3824 | u32 val; |
c9ee9206 VZ |
3825 | u32 bit = BP_PATH(bp) ? |
3826 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
3827 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3828 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
3829 | |
3830 | /* Clear the bit */ | |
3831 | val &= ~bit; | |
3832 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
3833 | |
3834 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
72fd0718 VZ |
3835 | } |
3836 | ||
3837 | /* | |
c9ee9206 VZ |
3838 | * Set RESET_IN_PROGRESS for the current engine. |
3839 | * | |
72fd0718 VZ |
3840 | * should be run under rtnl lock |
3841 | */ | |
c9ee9206 | 3842 | void bnx2x_set_reset_in_progress(struct bnx2x *bp) |
72fd0718 | 3843 | { |
f16da43b | 3844 | u32 val; |
c9ee9206 VZ |
3845 | u32 bit = BP_PATH(bp) ? |
3846 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
3847 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3848 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
3849 | |
3850 | /* Set the bit */ | |
3851 | val |= bit; | |
3852 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 3853 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
3854 | } |
3855 | ||
3856 | /* | |
c9ee9206 | 3857 | * Checks the RESET_IN_PROGRESS bit for the given engine. |
72fd0718 VZ |
3858 | * should be run under rtnl lock |
3859 | */ | |
c9ee9206 | 3860 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) |
72fd0718 | 3861 | { |
c9ee9206 VZ |
3862 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3863 | u32 bit = engine ? | |
3864 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
3865 | ||
3866 | /* return false if bit is set */ | |
3867 | return (val & bit) ? false : true; | |
72fd0718 VZ |
3868 | } |
3869 | ||
3870 | /* | |
889b9af3 | 3871 | * set pf load for the current pf. |
c9ee9206 | 3872 | * |
72fd0718 VZ |
3873 | * should be run under rtnl lock |
3874 | */ | |
889b9af3 | 3875 | void bnx2x_set_pf_load(struct bnx2x *bp) |
72fd0718 | 3876 | { |
f16da43b | 3877 | u32 val1, val; |
c9ee9206 VZ |
3878 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
3879 | BNX2X_PATH0_LOAD_CNT_MASK; | |
3880 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3881 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 3882 | |
f16da43b AE |
3883 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3884 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3885 | ||
51c1a580 | 3886 | DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 3887 | |
c9ee9206 VZ |
3888 | /* get the current counter value */ |
3889 | val1 = (val & mask) >> shift; | |
3890 | ||
889b9af3 AE |
3891 | /* set bit of that PF */ |
3892 | val1 |= (1 << bp->pf_num); | |
c9ee9206 VZ |
3893 | |
3894 | /* clear the old value */ | |
3895 | val &= ~mask; | |
3896 | ||
3897 | /* set the new one */ | |
3898 | val |= ((val1 << shift) & mask); | |
3899 | ||
3900 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 3901 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
3902 | } |
3903 | ||
c9ee9206 | 3904 | /** |
889b9af3 | 3905 | * bnx2x_clear_pf_load - clear pf load mark |
c9ee9206 VZ |
3906 | * |
3907 | * @bp: driver handle | |
3908 | * | |
3909 | * Should be run under rtnl lock. | |
3910 | * Decrements the load counter for the current engine. Returns | |
889b9af3 | 3911 | * whether other functions are still loaded |
72fd0718 | 3912 | */ |
889b9af3 | 3913 | bool bnx2x_clear_pf_load(struct bnx2x *bp) |
72fd0718 | 3914 | { |
f16da43b | 3915 | u32 val1, val; |
c9ee9206 VZ |
3916 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
3917 | BNX2X_PATH0_LOAD_CNT_MASK; | |
3918 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3919 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 3920 | |
f16da43b AE |
3921 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3922 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
51c1a580 | 3923 | DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 3924 | |
c9ee9206 VZ |
3925 | /* get the current counter value */ |
3926 | val1 = (val & mask) >> shift; | |
3927 | ||
889b9af3 AE |
3928 | /* clear bit of that PF */ |
3929 | val1 &= ~(1 << bp->pf_num); | |
c9ee9206 VZ |
3930 | |
3931 | /* clear the old value */ | |
3932 | val &= ~mask; | |
3933 | ||
3934 | /* set the new one */ | |
3935 | val |= ((val1 << shift) & mask); | |
3936 | ||
3937 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
3938 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3939 | return val1 != 0; | |
72fd0718 VZ |
3940 | } |
3941 | ||
3942 | /* | |
889b9af3 | 3943 | * Read the load status for the current engine. |
c9ee9206 | 3944 | * |
72fd0718 VZ |
3945 | * should be run under rtnl lock |
3946 | */ | |
889b9af3 | 3947 | static inline bool bnx2x_get_load_status(struct bnx2x *bp, int engine) |
72fd0718 | 3948 | { |
c9ee9206 VZ |
3949 | u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : |
3950 | BNX2X_PATH0_LOAD_CNT_MASK); | |
3951 | u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3952 | BNX2X_PATH0_LOAD_CNT_SHIFT); | |
3953 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3954 | ||
51c1a580 | 3955 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); |
c9ee9206 VZ |
3956 | |
3957 | val = (val & mask) >> shift; | |
3958 | ||
51c1a580 MS |
3959 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", |
3960 | engine, val); | |
c9ee9206 | 3961 | |
889b9af3 | 3962 | return val != 0; |
72fd0718 VZ |
3963 | } |
3964 | ||
c9ee9206 | 3965 | /* |
889b9af3 | 3966 | * Reset the load status for the current engine. |
c9ee9206 | 3967 | */ |
889b9af3 | 3968 | static inline void bnx2x_clear_load_status(struct bnx2x *bp) |
72fd0718 | 3969 | { |
f16da43b | 3970 | u32 val; |
c9ee9206 | 3971 | u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
f16da43b AE |
3972 | BNX2X_PATH0_LOAD_CNT_MASK); |
3973 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
3974 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 3975 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); |
f16da43b | 3976 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
3977 | } |
3978 | ||
3979 | static inline void _print_next_block(int idx, const char *blk) | |
3980 | { | |
f1deab50 | 3981 | pr_cont("%s%s", idx ? ", " : "", blk); |
72fd0718 VZ |
3982 | } |
3983 | ||
c9ee9206 VZ |
3984 | static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, |
3985 | bool print) | |
72fd0718 VZ |
3986 | { |
3987 | int i = 0; | |
3988 | u32 cur_bit = 0; | |
3989 | for (i = 0; sig; i++) { | |
3990 | cur_bit = ((u32)0x1 << i); | |
3991 | if (sig & cur_bit) { | |
3992 | switch (cur_bit) { | |
3993 | case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: | |
c9ee9206 VZ |
3994 | if (print) |
3995 | _print_next_block(par_num++, "BRB"); | |
72fd0718 VZ |
3996 | break; |
3997 | case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: | |
c9ee9206 VZ |
3998 | if (print) |
3999 | _print_next_block(par_num++, "PARSER"); | |
72fd0718 VZ |
4000 | break; |
4001 | case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: | |
c9ee9206 VZ |
4002 | if (print) |
4003 | _print_next_block(par_num++, "TSDM"); | |
72fd0718 VZ |
4004 | break; |
4005 | case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: | |
c9ee9206 VZ |
4006 | if (print) |
4007 | _print_next_block(par_num++, | |
4008 | "SEARCHER"); | |
4009 | break; | |
4010 | case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: | |
4011 | if (print) | |
4012 | _print_next_block(par_num++, "TCM"); | |
72fd0718 VZ |
4013 | break; |
4014 | case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
4015 | if (print) |
4016 | _print_next_block(par_num++, "TSEMI"); | |
4017 | break; | |
4018 | case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: | |
4019 | if (print) | |
4020 | _print_next_block(par_num++, "XPB"); | |
72fd0718 VZ |
4021 | break; |
4022 | } | |
4023 | ||
4024 | /* Clear the bit */ | |
4025 | sig &= ~cur_bit; | |
4026 | } | |
4027 | } | |
4028 | ||
4029 | return par_num; | |
4030 | } | |
4031 | ||
c9ee9206 VZ |
4032 | static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, |
4033 | bool *global, bool print) | |
72fd0718 VZ |
4034 | { |
4035 | int i = 0; | |
4036 | u32 cur_bit = 0; | |
4037 | for (i = 0; sig; i++) { | |
4038 | cur_bit = ((u32)0x1 << i); | |
4039 | if (sig & cur_bit) { | |
4040 | switch (cur_bit) { | |
c9ee9206 VZ |
4041 | case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: |
4042 | if (print) | |
4043 | _print_next_block(par_num++, "PBF"); | |
72fd0718 VZ |
4044 | break; |
4045 | case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: | |
c9ee9206 VZ |
4046 | if (print) |
4047 | _print_next_block(par_num++, "QM"); | |
4048 | break; | |
4049 | case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: | |
4050 | if (print) | |
4051 | _print_next_block(par_num++, "TM"); | |
72fd0718 VZ |
4052 | break; |
4053 | case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: | |
c9ee9206 VZ |
4054 | if (print) |
4055 | _print_next_block(par_num++, "XSDM"); | |
4056 | break; | |
4057 | case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: | |
4058 | if (print) | |
4059 | _print_next_block(par_num++, "XCM"); | |
72fd0718 VZ |
4060 | break; |
4061 | case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
4062 | if (print) |
4063 | _print_next_block(par_num++, "XSEMI"); | |
72fd0718 VZ |
4064 | break; |
4065 | case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: | |
c9ee9206 VZ |
4066 | if (print) |
4067 | _print_next_block(par_num++, | |
4068 | "DOORBELLQ"); | |
4069 | break; | |
4070 | case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: | |
4071 | if (print) | |
4072 | _print_next_block(par_num++, "NIG"); | |
72fd0718 VZ |
4073 | break; |
4074 | case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: | |
c9ee9206 VZ |
4075 | if (print) |
4076 | _print_next_block(par_num++, | |
4077 | "VAUX PCI CORE"); | |
4078 | *global = true; | |
72fd0718 VZ |
4079 | break; |
4080 | case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: | |
c9ee9206 VZ |
4081 | if (print) |
4082 | _print_next_block(par_num++, "DEBUG"); | |
72fd0718 VZ |
4083 | break; |
4084 | case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: | |
c9ee9206 VZ |
4085 | if (print) |
4086 | _print_next_block(par_num++, "USDM"); | |
72fd0718 | 4087 | break; |
8736c826 VZ |
4088 | case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: |
4089 | if (print) | |
4090 | _print_next_block(par_num++, "UCM"); | |
4091 | break; | |
72fd0718 | 4092 | case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: |
c9ee9206 VZ |
4093 | if (print) |
4094 | _print_next_block(par_num++, "USEMI"); | |
72fd0718 VZ |
4095 | break; |
4096 | case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: | |
c9ee9206 VZ |
4097 | if (print) |
4098 | _print_next_block(par_num++, "UPB"); | |
72fd0718 VZ |
4099 | break; |
4100 | case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: | |
c9ee9206 VZ |
4101 | if (print) |
4102 | _print_next_block(par_num++, "CSDM"); | |
72fd0718 | 4103 | break; |
8736c826 VZ |
4104 | case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: |
4105 | if (print) | |
4106 | _print_next_block(par_num++, "CCM"); | |
4107 | break; | |
72fd0718 VZ |
4108 | } |
4109 | ||
4110 | /* Clear the bit */ | |
4111 | sig &= ~cur_bit; | |
4112 | } | |
4113 | } | |
4114 | ||
4115 | return par_num; | |
4116 | } | |
4117 | ||
c9ee9206 VZ |
4118 | static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, |
4119 | bool print) | |
72fd0718 VZ |
4120 | { |
4121 | int i = 0; | |
4122 | u32 cur_bit = 0; | |
4123 | for (i = 0; sig; i++) { | |
4124 | cur_bit = ((u32)0x1 << i); | |
4125 | if (sig & cur_bit) { | |
4126 | switch (cur_bit) { | |
4127 | case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
4128 | if (print) |
4129 | _print_next_block(par_num++, "CSEMI"); | |
72fd0718 VZ |
4130 | break; |
4131 | case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: | |
c9ee9206 VZ |
4132 | if (print) |
4133 | _print_next_block(par_num++, "PXP"); | |
72fd0718 VZ |
4134 | break; |
4135 | case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: | |
c9ee9206 VZ |
4136 | if (print) |
4137 | _print_next_block(par_num++, | |
72fd0718 VZ |
4138 | "PXPPCICLOCKCLIENT"); |
4139 | break; | |
4140 | case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: | |
c9ee9206 VZ |
4141 | if (print) |
4142 | _print_next_block(par_num++, "CFC"); | |
72fd0718 VZ |
4143 | break; |
4144 | case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: | |
c9ee9206 VZ |
4145 | if (print) |
4146 | _print_next_block(par_num++, "CDU"); | |
4147 | break; | |
4148 | case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: | |
4149 | if (print) | |
4150 | _print_next_block(par_num++, "DMAE"); | |
72fd0718 VZ |
4151 | break; |
4152 | case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: | |
c9ee9206 VZ |
4153 | if (print) |
4154 | _print_next_block(par_num++, "IGU"); | |
72fd0718 VZ |
4155 | break; |
4156 | case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: | |
c9ee9206 VZ |
4157 | if (print) |
4158 | _print_next_block(par_num++, "MISC"); | |
72fd0718 VZ |
4159 | break; |
4160 | } | |
4161 | ||
4162 | /* Clear the bit */ | |
4163 | sig &= ~cur_bit; | |
4164 | } | |
4165 | } | |
4166 | ||
4167 | return par_num; | |
4168 | } | |
4169 | ||
c9ee9206 VZ |
4170 | static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, |
4171 | bool *global, bool print) | |
72fd0718 VZ |
4172 | { |
4173 | int i = 0; | |
4174 | u32 cur_bit = 0; | |
4175 | for (i = 0; sig; i++) { | |
4176 | cur_bit = ((u32)0x1 << i); | |
4177 | if (sig & cur_bit) { | |
4178 | switch (cur_bit) { | |
4179 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: | |
c9ee9206 VZ |
4180 | if (print) |
4181 | _print_next_block(par_num++, "MCP ROM"); | |
4182 | *global = true; | |
72fd0718 VZ |
4183 | break; |
4184 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: | |
c9ee9206 VZ |
4185 | if (print) |
4186 | _print_next_block(par_num++, | |
4187 | "MCP UMP RX"); | |
4188 | *global = true; | |
72fd0718 VZ |
4189 | break; |
4190 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: | |
c9ee9206 VZ |
4191 | if (print) |
4192 | _print_next_block(par_num++, | |
4193 | "MCP UMP TX"); | |
4194 | *global = true; | |
72fd0718 VZ |
4195 | break; |
4196 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: | |
c9ee9206 VZ |
4197 | if (print) |
4198 | _print_next_block(par_num++, | |
4199 | "MCP SCPAD"); | |
4200 | *global = true; | |
72fd0718 VZ |
4201 | break; |
4202 | } | |
4203 | ||
4204 | /* Clear the bit */ | |
4205 | sig &= ~cur_bit; | |
4206 | } | |
4207 | } | |
4208 | ||
4209 | return par_num; | |
4210 | } | |
4211 | ||
8736c826 VZ |
4212 | static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, |
4213 | bool print) | |
4214 | { | |
4215 | int i = 0; | |
4216 | u32 cur_bit = 0; | |
4217 | for (i = 0; sig; i++) { | |
4218 | cur_bit = ((u32)0x1 << i); | |
4219 | if (sig & cur_bit) { | |
4220 | switch (cur_bit) { | |
4221 | case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: | |
4222 | if (print) | |
4223 | _print_next_block(par_num++, "PGLUE_B"); | |
4224 | break; | |
4225 | case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: | |
4226 | if (print) | |
4227 | _print_next_block(par_num++, "ATC"); | |
4228 | break; | |
4229 | } | |
4230 | ||
4231 | /* Clear the bit */ | |
4232 | sig &= ~cur_bit; | |
4233 | } | |
4234 | } | |
4235 | ||
4236 | return par_num; | |
4237 | } | |
4238 | ||
c9ee9206 | 4239 | static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, |
8736c826 | 4240 | u32 *sig) |
72fd0718 | 4241 | { |
8736c826 VZ |
4242 | if ((sig[0] & HW_PRTY_ASSERT_SET_0) || |
4243 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
4244 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
4245 | (sig[3] & HW_PRTY_ASSERT_SET_3) || | |
4246 | (sig[4] & HW_PRTY_ASSERT_SET_4)) { | |
72fd0718 | 4247 | int par_num = 0; |
51c1a580 MS |
4248 | DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" |
4249 | "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", | |
8736c826 VZ |
4250 | sig[0] & HW_PRTY_ASSERT_SET_0, |
4251 | sig[1] & HW_PRTY_ASSERT_SET_1, | |
4252 | sig[2] & HW_PRTY_ASSERT_SET_2, | |
4253 | sig[3] & HW_PRTY_ASSERT_SET_3, | |
4254 | sig[4] & HW_PRTY_ASSERT_SET_4); | |
c9ee9206 VZ |
4255 | if (print) |
4256 | netdev_err(bp->dev, | |
4257 | "Parity errors detected in blocks: "); | |
4258 | par_num = bnx2x_check_blocks_with_parity0( | |
8736c826 | 4259 | sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); |
c9ee9206 | 4260 | par_num = bnx2x_check_blocks_with_parity1( |
8736c826 | 4261 | sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); |
c9ee9206 | 4262 | par_num = bnx2x_check_blocks_with_parity2( |
8736c826 | 4263 | sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); |
c9ee9206 | 4264 | par_num = bnx2x_check_blocks_with_parity3( |
8736c826 VZ |
4265 | sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); |
4266 | par_num = bnx2x_check_blocks_with_parity4( | |
4267 | sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); | |
4268 | ||
c9ee9206 VZ |
4269 | if (print) |
4270 | pr_cont("\n"); | |
8736c826 | 4271 | |
72fd0718 VZ |
4272 | return true; |
4273 | } else | |
4274 | return false; | |
4275 | } | |
4276 | ||
c9ee9206 VZ |
4277 | /** |
4278 | * bnx2x_chk_parity_attn - checks for parity attentions. | |
4279 | * | |
4280 | * @bp: driver handle | |
4281 | * @global: true if there was a global attention | |
4282 | * @print: show parity attention in syslog | |
4283 | */ | |
4284 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) | |
877e9aa4 | 4285 | { |
8736c826 | 4286 | struct attn_route attn = { {0} }; |
72fd0718 VZ |
4287 | int port = BP_PORT(bp); |
4288 | ||
4289 | attn.sig[0] = REG_RD(bp, | |
4290 | MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + | |
4291 | port*4); | |
4292 | attn.sig[1] = REG_RD(bp, | |
4293 | MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + | |
4294 | port*4); | |
4295 | attn.sig[2] = REG_RD(bp, | |
4296 | MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + | |
4297 | port*4); | |
4298 | attn.sig[3] = REG_RD(bp, | |
4299 | MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + | |
4300 | port*4); | |
4301 | ||
8736c826 VZ |
4302 | if (!CHIP_IS_E1x(bp)) |
4303 | attn.sig[4] = REG_RD(bp, | |
4304 | MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + | |
4305 | port*4); | |
4306 | ||
4307 | return bnx2x_parity_attn(bp, global, print, attn.sig); | |
72fd0718 VZ |
4308 | } |
4309 | ||
f2e0899f DK |
4310 | |
4311 | static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) | |
4312 | { | |
4313 | u32 val; | |
4314 | if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { | |
4315 | ||
4316 | val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); | |
4317 | BNX2X_ERR("PGLUE hw attention 0x%x\n", val); | |
4318 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) | |
51c1a580 | 4319 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); |
f2e0899f | 4320 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) |
51c1a580 | 4321 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); |
f2e0899f | 4322 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) |
51c1a580 | 4323 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); |
f2e0899f | 4324 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) |
51c1a580 | 4325 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); |
f2e0899f DK |
4326 | if (val & |
4327 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) | |
51c1a580 | 4328 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); |
f2e0899f DK |
4329 | if (val & |
4330 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) | |
51c1a580 | 4331 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); |
f2e0899f | 4332 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) |
51c1a580 | 4333 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); |
f2e0899f | 4334 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) |
51c1a580 | 4335 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); |
f2e0899f | 4336 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) |
51c1a580 | 4337 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); |
f2e0899f DK |
4338 | } |
4339 | if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { | |
4340 | val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); | |
4341 | BNX2X_ERR("ATC hw attention 0x%x\n", val); | |
4342 | if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) | |
4343 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); | |
4344 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) | |
51c1a580 | 4345 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); |
f2e0899f | 4346 | if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) |
51c1a580 | 4347 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); |
f2e0899f | 4348 | if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) |
51c1a580 | 4349 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); |
f2e0899f DK |
4350 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) |
4351 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); | |
4352 | if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) | |
51c1a580 | 4353 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); |
f2e0899f DK |
4354 | } |
4355 | ||
4356 | if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4357 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { | |
4358 | BNX2X_ERR("FATAL parity attention set4 0x%x\n", | |
4359 | (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4360 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); | |
4361 | } | |
4362 | ||
4363 | } | |
4364 | ||
72fd0718 VZ |
4365 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) |
4366 | { | |
4367 | struct attn_route attn, *group_mask; | |
34f80b04 | 4368 | int port = BP_PORT(bp); |
877e9aa4 | 4369 | int index; |
a2fbb9ea ET |
4370 | u32 reg_addr; |
4371 | u32 val; | |
3fcaf2e5 | 4372 | u32 aeu_mask; |
c9ee9206 | 4373 | bool global = false; |
a2fbb9ea ET |
4374 | |
4375 | /* need to take HW lock because MCP or other port might also | |
4376 | try to handle this event */ | |
4a37fb66 | 4377 | bnx2x_acquire_alr(bp); |
a2fbb9ea | 4378 | |
c9ee9206 VZ |
4379 | if (bnx2x_chk_parity_attn(bp, &global, true)) { |
4380 | #ifndef BNX2X_STOP_ON_ERROR | |
72fd0718 | 4381 | bp->recovery_state = BNX2X_RECOVERY_INIT; |
7be08a72 | 4382 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
72fd0718 VZ |
4383 | /* Disable HW interrupts */ |
4384 | bnx2x_int_disable(bp); | |
72fd0718 VZ |
4385 | /* In case of parity errors don't handle attentions so that |
4386 | * other function would "see" parity errors. | |
4387 | */ | |
c9ee9206 VZ |
4388 | #else |
4389 | bnx2x_panic(); | |
4390 | #endif | |
4391 | bnx2x_release_alr(bp); | |
72fd0718 VZ |
4392 | return; |
4393 | } | |
4394 | ||
a2fbb9ea ET |
4395 | attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); |
4396 | attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); | |
4397 | attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); | |
4398 | attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); | |
619c5cb6 | 4399 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
4400 | attn.sig[4] = |
4401 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); | |
4402 | else | |
4403 | attn.sig[4] = 0; | |
4404 | ||
4405 | DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", | |
4406 | attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); | |
a2fbb9ea ET |
4407 | |
4408 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { | |
4409 | if (deasserted & (1 << index)) { | |
72fd0718 | 4410 | group_mask = &bp->attn_group[index]; |
a2fbb9ea | 4411 | |
51c1a580 | 4412 | DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", |
f2e0899f DK |
4413 | index, |
4414 | group_mask->sig[0], group_mask->sig[1], | |
4415 | group_mask->sig[2], group_mask->sig[3], | |
4416 | group_mask->sig[4]); | |
a2fbb9ea | 4417 | |
f2e0899f DK |
4418 | bnx2x_attn_int_deasserted4(bp, |
4419 | attn.sig[4] & group_mask->sig[4]); | |
877e9aa4 | 4420 | bnx2x_attn_int_deasserted3(bp, |
72fd0718 | 4421 | attn.sig[3] & group_mask->sig[3]); |
877e9aa4 | 4422 | bnx2x_attn_int_deasserted1(bp, |
72fd0718 | 4423 | attn.sig[1] & group_mask->sig[1]); |
877e9aa4 | 4424 | bnx2x_attn_int_deasserted2(bp, |
72fd0718 | 4425 | attn.sig[2] & group_mask->sig[2]); |
877e9aa4 | 4426 | bnx2x_attn_int_deasserted0(bp, |
72fd0718 | 4427 | attn.sig[0] & group_mask->sig[0]); |
a2fbb9ea ET |
4428 | } |
4429 | } | |
4430 | ||
4a37fb66 | 4431 | bnx2x_release_alr(bp); |
a2fbb9ea | 4432 | |
f2e0899f DK |
4433 | if (bp->common.int_block == INT_BLOCK_HC) |
4434 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
4435 | COMMAND_REG_ATTN_BITS_CLR); | |
4436 | else | |
4437 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); | |
a2fbb9ea ET |
4438 | |
4439 | val = ~deasserted; | |
f2e0899f DK |
4440 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, |
4441 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
5c862848 | 4442 | REG_WR(bp, reg_addr, val); |
a2fbb9ea | 4443 | |
a2fbb9ea | 4444 | if (~bp->attn_state & deasserted) |
3fcaf2e5 | 4445 | BNX2X_ERR("IGU ERROR\n"); |
a2fbb9ea ET |
4446 | |
4447 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
4448 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
4449 | ||
3fcaf2e5 EG |
4450 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
4451 | aeu_mask = REG_RD(bp, reg_addr); | |
4452 | ||
4453 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", | |
4454 | aeu_mask, deasserted); | |
72fd0718 | 4455 | aeu_mask |= (deasserted & 0x3ff); |
3fcaf2e5 | 4456 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 4457 | |
3fcaf2e5 EG |
4458 | REG_WR(bp, reg_addr, aeu_mask); |
4459 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea ET |
4460 | |
4461 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | |
4462 | bp->attn_state &= ~deasserted; | |
4463 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); | |
4464 | } | |
4465 | ||
4466 | static void bnx2x_attn_int(struct bnx2x *bp) | |
4467 | { | |
4468 | /* read local copy of bits */ | |
68d59484 EG |
4469 | u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. |
4470 | attn_bits); | |
4471 | u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. | |
4472 | attn_bits_ack); | |
a2fbb9ea ET |
4473 | u32 attn_state = bp->attn_state; |
4474 | ||
4475 | /* look for changed bits */ | |
4476 | u32 asserted = attn_bits & ~attn_ack & ~attn_state; | |
4477 | u32 deasserted = ~attn_bits & attn_ack & attn_state; | |
4478 | ||
4479 | DP(NETIF_MSG_HW, | |
4480 | "attn_bits %x attn_ack %x asserted %x deasserted %x\n", | |
4481 | attn_bits, attn_ack, asserted, deasserted); | |
4482 | ||
4483 | if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) | |
34f80b04 | 4484 | BNX2X_ERR("BAD attention state\n"); |
a2fbb9ea ET |
4485 | |
4486 | /* handle bits that were raised */ | |
4487 | if (asserted) | |
4488 | bnx2x_attn_int_asserted(bp, asserted); | |
4489 | ||
4490 | if (deasserted) | |
4491 | bnx2x_attn_int_deasserted(bp, deasserted); | |
4492 | } | |
4493 | ||
619c5cb6 VZ |
4494 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, |
4495 | u16 index, u8 op, u8 update) | |
4496 | { | |
4497 | u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
4498 | ||
4499 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, | |
4500 | igu_addr); | |
4501 | } | |
4502 | ||
523224a3 DK |
4503 | static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) |
4504 | { | |
4505 | /* No memory barriers */ | |
4506 | storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); | |
4507 | mmiowb(); /* keep prod updates ordered */ | |
4508 | } | |
4509 | ||
4510 | #ifdef BCM_CNIC | |
4511 | static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, | |
4512 | union event_ring_elem *elem) | |
4513 | { | |
619c5cb6 VZ |
4514 | u8 err = elem->message.error; |
4515 | ||
523224a3 | 4516 | if (!bp->cnic_eth_dev.starting_cid || |
c3a8ce61 VZ |
4517 | (cid < bp->cnic_eth_dev.starting_cid && |
4518 | cid != bp->cnic_eth_dev.iscsi_l2_cid)) | |
523224a3 DK |
4519 | return 1; |
4520 | ||
4521 | DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); | |
4522 | ||
619c5cb6 VZ |
4523 | if (unlikely(err)) { |
4524 | ||
523224a3 DK |
4525 | BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", |
4526 | cid); | |
4527 | bnx2x_panic_dump(bp); | |
4528 | } | |
619c5cb6 | 4529 | bnx2x_cnic_cfc_comp(bp, cid, err); |
523224a3 DK |
4530 | return 0; |
4531 | } | |
4532 | #endif | |
4533 | ||
619c5cb6 VZ |
4534 | static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) |
4535 | { | |
4536 | struct bnx2x_mcast_ramrod_params rparam; | |
4537 | int rc; | |
4538 | ||
4539 | memset(&rparam, 0, sizeof(rparam)); | |
4540 | ||
4541 | rparam.mcast_obj = &bp->mcast_obj; | |
4542 | ||
4543 | netif_addr_lock_bh(bp->dev); | |
4544 | ||
4545 | /* Clear pending state for the last command */ | |
4546 | bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); | |
4547 | ||
4548 | /* If there are pending mcast commands - send them */ | |
4549 | if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { | |
4550 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
4551 | if (rc < 0) | |
4552 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", | |
4553 | rc); | |
4554 | } | |
4555 | ||
4556 | netif_addr_unlock_bh(bp->dev); | |
4557 | } | |
4558 | ||
4559 | static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, | |
4560 | union event_ring_elem *elem) | |
4561 | { | |
4562 | unsigned long ramrod_flags = 0; | |
4563 | int rc = 0; | |
4564 | u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; | |
4565 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; | |
4566 | ||
4567 | /* Always push next commands out, don't wait here */ | |
4568 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
4569 | ||
4570 | switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { | |
4571 | case BNX2X_FILTER_MAC_PENDING: | |
51c1a580 | 4572 | DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); |
619c5cb6 VZ |
4573 | #ifdef BCM_CNIC |
4574 | if (cid == BNX2X_ISCSI_ETH_CID) | |
4575 | vlan_mac_obj = &bp->iscsi_l2_mac_obj; | |
4576 | else | |
4577 | #endif | |
4578 | vlan_mac_obj = &bp->fp[cid].mac_obj; | |
4579 | ||
4580 | break; | |
619c5cb6 | 4581 | case BNX2X_FILTER_MCAST_PENDING: |
51c1a580 | 4582 | DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); |
619c5cb6 VZ |
4583 | /* This is only relevant for 57710 where multicast MACs are |
4584 | * configured as unicast MACs using the same ramrod. | |
4585 | */ | |
4586 | bnx2x_handle_mcast_eqe(bp); | |
4587 | return; | |
4588 | default: | |
4589 | BNX2X_ERR("Unsupported classification command: %d\n", | |
4590 | elem->message.data.eth_event.echo); | |
4591 | return; | |
4592 | } | |
4593 | ||
4594 | rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); | |
4595 | ||
4596 | if (rc < 0) | |
4597 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); | |
4598 | else if (rc > 0) | |
4599 | DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); | |
4600 | ||
4601 | } | |
4602 | ||
4603 | #ifdef BCM_CNIC | |
4604 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); | |
4605 | #endif | |
4606 | ||
4607 | static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) | |
4608 | { | |
4609 | netif_addr_lock_bh(bp->dev); | |
4610 | ||
4611 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
4612 | ||
4613 | /* Send rx_mode command again if was requested */ | |
4614 | if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) | |
4615 | bnx2x_set_storm_rx_mode(bp); | |
4616 | #ifdef BCM_CNIC | |
4617 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, | |
4618 | &bp->sp_state)) | |
4619 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
4620 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, | |
4621 | &bp->sp_state)) | |
4622 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
4623 | #endif | |
4624 | ||
4625 | netif_addr_unlock_bh(bp->dev); | |
4626 | } | |
4627 | ||
a3348722 BW |
4628 | static inline void bnx2x_after_afex_vif_lists(struct bnx2x *bp, |
4629 | union event_ring_elem *elem) | |
4630 | { | |
4631 | if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { | |
4632 | DP(BNX2X_MSG_SP, | |
4633 | "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", | |
4634 | elem->message.data.vif_list_event.func_bit_map); | |
4635 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, | |
4636 | elem->message.data.vif_list_event.func_bit_map); | |
4637 | } else if (elem->message.data.vif_list_event.echo == | |
4638 | VIF_LIST_RULE_SET) { | |
4639 | DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); | |
4640 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); | |
4641 | } | |
4642 | } | |
4643 | ||
4644 | /* called with rtnl_lock */ | |
4645 | static inline void bnx2x_after_function_update(struct bnx2x *bp) | |
4646 | { | |
4647 | int q, rc; | |
4648 | struct bnx2x_fastpath *fp; | |
4649 | struct bnx2x_queue_state_params queue_params = {NULL}; | |
4650 | struct bnx2x_queue_update_params *q_update_params = | |
4651 | &queue_params.params.update; | |
4652 | ||
4653 | /* Send Q update command with afex vlan removal values for all Qs */ | |
4654 | queue_params.cmd = BNX2X_Q_CMD_UPDATE; | |
4655 | ||
4656 | /* set silent vlan removal values according to vlan mode */ | |
4657 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, | |
4658 | &q_update_params->update_flags); | |
4659 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, | |
4660 | &q_update_params->update_flags); | |
4661 | __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
4662 | ||
4663 | /* in access mode mark mask and value are 0 to strip all vlans */ | |
4664 | if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { | |
4665 | q_update_params->silent_removal_value = 0; | |
4666 | q_update_params->silent_removal_mask = 0; | |
4667 | } else { | |
4668 | q_update_params->silent_removal_value = | |
4669 | (bp->afex_def_vlan_tag & VLAN_VID_MASK); | |
4670 | q_update_params->silent_removal_mask = VLAN_VID_MASK; | |
4671 | } | |
4672 | ||
4673 | for_each_eth_queue(bp, q) { | |
4674 | /* Set the appropriate Queue object */ | |
4675 | fp = &bp->fp[q]; | |
4676 | queue_params.q_obj = &fp->q_obj; | |
4677 | ||
4678 | /* send the ramrod */ | |
4679 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
4680 | if (rc < 0) | |
4681 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
4682 | q); | |
4683 | } | |
4684 | ||
4685 | #ifdef BCM_CNIC | |
4686 | if (!NO_FCOE(bp)) { | |
4687 | fp = &bp->fp[FCOE_IDX]; | |
4688 | queue_params.q_obj = &fp->q_obj; | |
4689 | ||
4690 | /* clear pending completion bit */ | |
4691 | __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
4692 | ||
4693 | /* mark latest Q bit */ | |
4694 | smp_mb__before_clear_bit(); | |
4695 | set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
4696 | smp_mb__after_clear_bit(); | |
4697 | ||
4698 | /* send Q update ramrod for FCoE Q */ | |
4699 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
4700 | if (rc < 0) | |
4701 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
4702 | q); | |
4703 | } else { | |
4704 | /* If no FCoE ring - ACK MCP now */ | |
4705 | bnx2x_link_report(bp); | |
4706 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
4707 | } | |
4708 | #else | |
4709 | /* If no FCoE ring - ACK MCP now */ | |
4710 | bnx2x_link_report(bp); | |
4711 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
4712 | #endif /* BCM_CNIC */ | |
4713 | } | |
4714 | ||
619c5cb6 VZ |
4715 | static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( |
4716 | struct bnx2x *bp, u32 cid) | |
4717 | { | |
94f05b0f | 4718 | DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); |
619c5cb6 VZ |
4719 | #ifdef BCM_CNIC |
4720 | if (cid == BNX2X_FCOE_ETH_CID) | |
4721 | return &bnx2x_fcoe(bp, q_obj); | |
4722 | else | |
4723 | #endif | |
6383c0b3 | 4724 | return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); |
619c5cb6 VZ |
4725 | } |
4726 | ||
523224a3 DK |
4727 | static void bnx2x_eq_int(struct bnx2x *bp) |
4728 | { | |
4729 | u16 hw_cons, sw_cons, sw_prod; | |
4730 | union event_ring_elem *elem; | |
4731 | u32 cid; | |
4732 | u8 opcode; | |
4733 | int spqe_cnt = 0; | |
619c5cb6 VZ |
4734 | struct bnx2x_queue_sp_obj *q_obj; |
4735 | struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; | |
4736 | struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; | |
523224a3 DK |
4737 | |
4738 | hw_cons = le16_to_cpu(*bp->eq_cons_sb); | |
4739 | ||
4740 | /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. | |
4741 | * when we get the the next-page we nned to adjust so the loop | |
4742 | * condition below will be met. The next element is the size of a | |
4743 | * regular element and hence incrementing by 1 | |
4744 | */ | |
4745 | if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) | |
4746 | hw_cons++; | |
4747 | ||
25985edc | 4748 | /* This function may never run in parallel with itself for a |
523224a3 DK |
4749 | * specific bp, thus there is no need in "paired" read memory |
4750 | * barrier here. | |
4751 | */ | |
4752 | sw_cons = bp->eq_cons; | |
4753 | sw_prod = bp->eq_prod; | |
4754 | ||
d6cae238 | 4755 | DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", |
6e30dd4e | 4756 | hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); |
523224a3 DK |
4757 | |
4758 | for (; sw_cons != hw_cons; | |
4759 | sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { | |
4760 | ||
4761 | ||
4762 | elem = &bp->eq_ring[EQ_DESC(sw_cons)]; | |
4763 | ||
4764 | cid = SW_CID(elem->message.data.cfc_del_event.cid); | |
4765 | opcode = elem->message.opcode; | |
4766 | ||
4767 | ||
4768 | /* handle eq element */ | |
4769 | switch (opcode) { | |
4770 | case EVENT_RING_OPCODE_STAT_QUERY: | |
51c1a580 MS |
4771 | DP(BNX2X_MSG_SP | BNX2X_MSG_STATS, |
4772 | "got statistics comp event %d\n", | |
619c5cb6 | 4773 | bp->stats_comp++); |
523224a3 | 4774 | /* nothing to do with stats comp */ |
d6cae238 | 4775 | goto next_spqe; |
523224a3 DK |
4776 | |
4777 | case EVENT_RING_OPCODE_CFC_DEL: | |
4778 | /* handle according to cid range */ | |
4779 | /* | |
4780 | * we may want to verify here that the bp state is | |
4781 | * HALTING | |
4782 | */ | |
d6cae238 | 4783 | DP(BNX2X_MSG_SP, |
523224a3 DK |
4784 | "got delete ramrod for MULTI[%d]\n", cid); |
4785 | #ifdef BCM_CNIC | |
4786 | if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) | |
4787 | goto next_spqe; | |
4788 | #endif | |
619c5cb6 VZ |
4789 | q_obj = bnx2x_cid_to_q_obj(bp, cid); |
4790 | ||
4791 | if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) | |
4792 | break; | |
4793 | ||
4794 | ||
523224a3 DK |
4795 | |
4796 | goto next_spqe; | |
e4901dde VZ |
4797 | |
4798 | case EVENT_RING_OPCODE_STOP_TRAFFIC: | |
51c1a580 | 4799 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); |
6debea87 DK |
4800 | if (f_obj->complete_cmd(bp, f_obj, |
4801 | BNX2X_F_CMD_TX_STOP)) | |
4802 | break; | |
e4901dde VZ |
4803 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); |
4804 | goto next_spqe; | |
619c5cb6 | 4805 | |
e4901dde | 4806 | case EVENT_RING_OPCODE_START_TRAFFIC: |
51c1a580 | 4807 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); |
6debea87 DK |
4808 | if (f_obj->complete_cmd(bp, f_obj, |
4809 | BNX2X_F_CMD_TX_START)) | |
4810 | break; | |
e4901dde VZ |
4811 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); |
4812 | goto next_spqe; | |
a3348722 BW |
4813 | case EVENT_RING_OPCODE_FUNCTION_UPDATE: |
4814 | DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, | |
4815 | "AFEX: ramrod completed FUNCTION_UPDATE\n"); | |
4816 | f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_AFEX_UPDATE); | |
4817 | ||
4818 | /* We will perform the Queues update from sp_rtnl task | |
4819 | * as all Queue SP operations should run under | |
4820 | * rtnl_lock. | |
4821 | */ | |
4822 | smp_mb__before_clear_bit(); | |
4823 | set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, | |
4824 | &bp->sp_rtnl_state); | |
4825 | smp_mb__after_clear_bit(); | |
4826 | ||
4827 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
4828 | goto next_spqe; | |
4829 | ||
4830 | case EVENT_RING_OPCODE_AFEX_VIF_LISTS: | |
4831 | f_obj->complete_cmd(bp, f_obj, | |
4832 | BNX2X_F_CMD_AFEX_VIFLISTS); | |
4833 | bnx2x_after_afex_vif_lists(bp, elem); | |
4834 | goto next_spqe; | |
619c5cb6 | 4835 | case EVENT_RING_OPCODE_FUNCTION_START: |
51c1a580 MS |
4836 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
4837 | "got FUNC_START ramrod\n"); | |
619c5cb6 VZ |
4838 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) |
4839 | break; | |
4840 | ||
4841 | goto next_spqe; | |
4842 | ||
4843 | case EVENT_RING_OPCODE_FUNCTION_STOP: | |
51c1a580 MS |
4844 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
4845 | "got FUNC_STOP ramrod\n"); | |
619c5cb6 VZ |
4846 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) |
4847 | break; | |
4848 | ||
4849 | goto next_spqe; | |
523224a3 DK |
4850 | } |
4851 | ||
4852 | switch (opcode | bp->state) { | |
619c5cb6 VZ |
4853 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
4854 | BNX2X_STATE_OPEN): | |
4855 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | | |
523224a3 | 4856 | BNX2X_STATE_OPENING_WAIT4_PORT): |
619c5cb6 VZ |
4857 | cid = elem->message.data.eth_event.echo & |
4858 | BNX2X_SWCID_MASK; | |
d6cae238 | 4859 | DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", |
619c5cb6 VZ |
4860 | cid); |
4861 | rss_raw->clear_pending(rss_raw); | |
523224a3 DK |
4862 | break; |
4863 | ||
619c5cb6 VZ |
4864 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): |
4865 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): | |
4866 | case (EVENT_RING_OPCODE_SET_MAC | | |
523224a3 | 4867 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
619c5cb6 VZ |
4868 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
4869 | BNX2X_STATE_OPEN): | |
4870 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
4871 | BNX2X_STATE_DIAG): | |
4872 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
4873 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 4874 | DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); |
619c5cb6 | 4875 | bnx2x_handle_classification_eqe(bp, elem); |
523224a3 DK |
4876 | break; |
4877 | ||
619c5cb6 VZ |
4878 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
4879 | BNX2X_STATE_OPEN): | |
4880 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
4881 | BNX2X_STATE_DIAG): | |
4882 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
4883 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 4884 | DP(BNX2X_MSG_SP, "got mcast ramrod\n"); |
619c5cb6 | 4885 | bnx2x_handle_mcast_eqe(bp); |
523224a3 DK |
4886 | break; |
4887 | ||
619c5cb6 VZ |
4888 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
4889 | BNX2X_STATE_OPEN): | |
4890 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
4891 | BNX2X_STATE_DIAG): | |
4892 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
523224a3 | 4893 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
d6cae238 | 4894 | DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); |
619c5cb6 | 4895 | bnx2x_handle_rx_mode_eqe(bp); |
523224a3 DK |
4896 | break; |
4897 | default: | |
4898 | /* unknown event log error and continue */ | |
619c5cb6 VZ |
4899 | BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", |
4900 | elem->message.opcode, bp->state); | |
523224a3 DK |
4901 | } |
4902 | next_spqe: | |
4903 | spqe_cnt++; | |
4904 | } /* for */ | |
4905 | ||
8fe23fbd | 4906 | smp_mb__before_atomic_inc(); |
6e30dd4e | 4907 | atomic_add(spqe_cnt, &bp->eq_spq_left); |
523224a3 DK |
4908 | |
4909 | bp->eq_cons = sw_cons; | |
4910 | bp->eq_prod = sw_prod; | |
4911 | /* Make sure that above mem writes were issued towards the memory */ | |
4912 | smp_wmb(); | |
4913 | ||
4914 | /* update producer */ | |
4915 | bnx2x_update_eq_prod(bp, bp->eq_prod); | |
4916 | } | |
4917 | ||
a2fbb9ea ET |
4918 | static void bnx2x_sp_task(struct work_struct *work) |
4919 | { | |
1cf167f2 | 4920 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); |
a2fbb9ea ET |
4921 | u16 status; |
4922 | ||
a2fbb9ea | 4923 | status = bnx2x_update_dsb_idx(bp); |
34f80b04 EG |
4924 | /* if (status == 0) */ |
4925 | /* BNX2X_ERR("spurious slowpath interrupt!\n"); */ | |
a2fbb9ea | 4926 | |
51c1a580 | 4927 | DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status); |
a2fbb9ea | 4928 | |
877e9aa4 | 4929 | /* HW attentions */ |
523224a3 | 4930 | if (status & BNX2X_DEF_SB_ATT_IDX) { |
a2fbb9ea | 4931 | bnx2x_attn_int(bp); |
523224a3 | 4932 | status &= ~BNX2X_DEF_SB_ATT_IDX; |
cdaa7cb8 VZ |
4933 | } |
4934 | ||
523224a3 DK |
4935 | /* SP events: STAT_QUERY and others */ |
4936 | if (status & BNX2X_DEF_SB_IDX) { | |
ec6ba945 VZ |
4937 | #ifdef BCM_CNIC |
4938 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
523224a3 | 4939 | |
ec6ba945 | 4940 | if ((!NO_FCOE(bp)) && |
019dbb4c VZ |
4941 | (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { |
4942 | /* | |
4943 | * Prevent local bottom-halves from running as | |
4944 | * we are going to change the local NAPI list. | |
4945 | */ | |
4946 | local_bh_disable(); | |
ec6ba945 | 4947 | napi_schedule(&bnx2x_fcoe(bp, napi)); |
019dbb4c VZ |
4948 | local_bh_enable(); |
4949 | } | |
ec6ba945 | 4950 | #endif |
523224a3 DK |
4951 | /* Handle EQ completions */ |
4952 | bnx2x_eq_int(bp); | |
4953 | ||
4954 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, | |
4955 | le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); | |
4956 | ||
4957 | status &= ~BNX2X_DEF_SB_IDX; | |
cdaa7cb8 VZ |
4958 | } |
4959 | ||
4960 | if (unlikely(status)) | |
51c1a580 | 4961 | DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n", |
cdaa7cb8 | 4962 | status); |
a2fbb9ea | 4963 | |
523224a3 DK |
4964 | bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, |
4965 | le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); | |
a3348722 BW |
4966 | |
4967 | /* afex - poll to check if VIFSET_ACK should be sent to MFW */ | |
4968 | if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, | |
4969 | &bp->sp_state)) { | |
4970 | bnx2x_link_report(bp); | |
4971 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
4972 | } | |
a2fbb9ea ET |
4973 | } |
4974 | ||
9f6c9258 | 4975 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
a2fbb9ea ET |
4976 | { |
4977 | struct net_device *dev = dev_instance; | |
4978 | struct bnx2x *bp = netdev_priv(dev); | |
4979 | ||
523224a3 DK |
4980 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, |
4981 | IGU_INT_DISABLE, 0); | |
a2fbb9ea ET |
4982 | |
4983 | #ifdef BNX2X_STOP_ON_ERROR | |
4984 | if (unlikely(bp->panic)) | |
4985 | return IRQ_HANDLED; | |
4986 | #endif | |
4987 | ||
993ac7b5 MC |
4988 | #ifdef BCM_CNIC |
4989 | { | |
4990 | struct cnic_ops *c_ops; | |
4991 | ||
4992 | rcu_read_lock(); | |
4993 | c_ops = rcu_dereference(bp->cnic_ops); | |
4994 | if (c_ops) | |
4995 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
4996 | rcu_read_unlock(); | |
4997 | } | |
4998 | #endif | |
1cf167f2 | 4999 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
a2fbb9ea ET |
5000 | |
5001 | return IRQ_HANDLED; | |
5002 | } | |
5003 | ||
5004 | /* end of slow path */ | |
5005 | ||
619c5cb6 VZ |
5006 | |
5007 | void bnx2x_drv_pulse(struct bnx2x *bp) | |
5008 | { | |
5009 | SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, | |
5010 | bp->fw_drv_pulse_wr_seq); | |
5011 | } | |
5012 | ||
5013 | ||
a2fbb9ea ET |
5014 | static void bnx2x_timer(unsigned long data) |
5015 | { | |
5016 | struct bnx2x *bp = (struct bnx2x *) data; | |
5017 | ||
5018 | if (!netif_running(bp->dev)) | |
5019 | return; | |
5020 | ||
34f80b04 | 5021 | if (!BP_NOMCP(bp)) { |
f2e0899f | 5022 | int mb_idx = BP_FW_MB_IDX(bp); |
a2fbb9ea ET |
5023 | u32 drv_pulse; |
5024 | u32 mcp_pulse; | |
5025 | ||
5026 | ++bp->fw_drv_pulse_wr_seq; | |
5027 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; | |
5028 | /* TBD - add SYSTEM_TIME */ | |
5029 | drv_pulse = bp->fw_drv_pulse_wr_seq; | |
619c5cb6 | 5030 | bnx2x_drv_pulse(bp); |
a2fbb9ea | 5031 | |
f2e0899f | 5032 | mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & |
a2fbb9ea ET |
5033 | MCP_PULSE_SEQ_MASK); |
5034 | /* The delta between driver pulse and mcp response | |
5035 | * should be 1 (before mcp response) or 0 (after mcp response) | |
5036 | */ | |
5037 | if ((drv_pulse != mcp_pulse) && | |
5038 | (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { | |
5039 | /* someone lost a heartbeat... */ | |
5040 | BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", | |
5041 | drv_pulse, mcp_pulse); | |
5042 | } | |
5043 | } | |
5044 | ||
f34d28ea | 5045 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a | 5046 | bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); |
a2fbb9ea | 5047 | |
a2fbb9ea ET |
5048 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
5049 | } | |
5050 | ||
5051 | /* end of Statistics */ | |
5052 | ||
5053 | /* nic init */ | |
5054 | ||
5055 | /* | |
5056 | * nic init service functions | |
5057 | */ | |
5058 | ||
523224a3 | 5059 | static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
a2fbb9ea | 5060 | { |
523224a3 DK |
5061 | u32 i; |
5062 | if (!(len%4) && !(addr%4)) | |
5063 | for (i = 0; i < len; i += 4) | |
5064 | REG_WR(bp, addr + i, fill); | |
5065 | else | |
5066 | for (i = 0; i < len; i++) | |
5067 | REG_WR8(bp, addr + i, fill); | |
34f80b04 | 5068 | |
34f80b04 EG |
5069 | } |
5070 | ||
523224a3 DK |
5071 | /* helper: writes FP SP data to FW - data_size in dwords */ |
5072 | static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, | |
5073 | int fw_sb_id, | |
5074 | u32 *sb_data_p, | |
5075 | u32 data_size) | |
34f80b04 | 5076 | { |
a2fbb9ea | 5077 | int index; |
523224a3 DK |
5078 | for (index = 0; index < data_size; index++) |
5079 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5080 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + | |
5081 | sizeof(u32)*index, | |
5082 | *(sb_data_p + index)); | |
5083 | } | |
a2fbb9ea | 5084 | |
523224a3 DK |
5085 | static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) |
5086 | { | |
5087 | u32 *sb_data_p; | |
5088 | u32 data_size = 0; | |
f2e0899f | 5089 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 | 5090 | struct hc_status_block_data_e1x sb_data_e1x; |
a2fbb9ea | 5091 | |
523224a3 | 5092 | /* disable the function first */ |
619c5cb6 | 5093 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5094 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5095 | sb_data_e2.common.state = SB_DISABLED; |
f2e0899f DK |
5096 | sb_data_e2.common.p_func.vf_valid = false; |
5097 | sb_data_p = (u32 *)&sb_data_e2; | |
5098 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
5099 | } else { | |
5100 | memset(&sb_data_e1x, 0, | |
5101 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5102 | sb_data_e1x.common.state = SB_DISABLED; |
f2e0899f DK |
5103 | sb_data_e1x.common.p_func.vf_valid = false; |
5104 | sb_data_p = (u32 *)&sb_data_e1x; | |
5105 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
5106 | } | |
523224a3 | 5107 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
a2fbb9ea | 5108 | |
523224a3 DK |
5109 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
5110 | CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, | |
5111 | CSTORM_STATUS_BLOCK_SIZE); | |
5112 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5113 | CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, | |
5114 | CSTORM_SYNC_BLOCK_SIZE); | |
5115 | } | |
34f80b04 | 5116 | |
523224a3 DK |
5117 | /* helper: writes SP SB data to FW */ |
5118 | static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, | |
5119 | struct hc_sp_status_block_data *sp_sb_data) | |
5120 | { | |
5121 | int func = BP_FUNC(bp); | |
5122 | int i; | |
5123 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
5124 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5125 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
5126 | i*sizeof(u32), | |
5127 | *((u32 *)sp_sb_data + i)); | |
34f80b04 EG |
5128 | } |
5129 | ||
523224a3 | 5130 | static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) |
34f80b04 EG |
5131 | { |
5132 | int func = BP_FUNC(bp); | |
523224a3 DK |
5133 | struct hc_sp_status_block_data sp_sb_data; |
5134 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
a2fbb9ea | 5135 | |
619c5cb6 | 5136 | sp_sb_data.state = SB_DISABLED; |
523224a3 DK |
5137 | sp_sb_data.p_func.vf_valid = false; |
5138 | ||
5139 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); | |
5140 | ||
5141 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5142 | CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, | |
5143 | CSTORM_SP_STATUS_BLOCK_SIZE); | |
5144 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5145 | CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, | |
5146 | CSTORM_SP_SYNC_BLOCK_SIZE); | |
5147 | ||
5148 | } | |
5149 | ||
5150 | ||
5151 | static inline | |
5152 | void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, | |
5153 | int igu_sb_id, int igu_seg_id) | |
5154 | { | |
5155 | hc_sm->igu_sb_id = igu_sb_id; | |
5156 | hc_sm->igu_seg_id = igu_seg_id; | |
5157 | hc_sm->timer_value = 0xFF; | |
5158 | hc_sm->time_to_expire = 0xFFFFFFFF; | |
a2fbb9ea ET |
5159 | } |
5160 | ||
150966ad AE |
5161 | |
5162 | /* allocates state machine ids. */ | |
5163 | static inline | |
5164 | void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) | |
5165 | { | |
5166 | /* zero out state machine indices */ | |
5167 | /* rx indices */ | |
5168 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5169 | ||
5170 | /* tx indices */ | |
5171 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5172 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; | |
5173 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; | |
5174 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; | |
5175 | ||
5176 | /* map indices */ | |
5177 | /* rx indices */ | |
5178 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= | |
5179 | SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5180 | ||
5181 | /* tx indices */ | |
5182 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= | |
5183 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5184 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= | |
5185 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5186 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= | |
5187 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5188 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= | |
5189 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5190 | } | |
5191 | ||
8d96286a | 5192 | static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
523224a3 | 5193 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
a2fbb9ea | 5194 | { |
523224a3 DK |
5195 | int igu_seg_id; |
5196 | ||
f2e0899f | 5197 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
5198 | struct hc_status_block_data_e1x sb_data_e1x; |
5199 | struct hc_status_block_sm *hc_sm_p; | |
523224a3 DK |
5200 | int data_size; |
5201 | u32 *sb_data_p; | |
5202 | ||
f2e0899f DK |
5203 | if (CHIP_INT_MODE_IS_BC(bp)) |
5204 | igu_seg_id = HC_SEG_ACCESS_NORM; | |
5205 | else | |
5206 | igu_seg_id = IGU_SEG_ACCESS_NORM; | |
523224a3 DK |
5207 | |
5208 | bnx2x_zero_fp_sb(bp, fw_sb_id); | |
5209 | ||
619c5cb6 | 5210 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5211 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5212 | sb_data_e2.common.state = SB_ENABLED; |
f2e0899f DK |
5213 | sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); |
5214 | sb_data_e2.common.p_func.vf_id = vfid; | |
5215 | sb_data_e2.common.p_func.vf_valid = vf_valid; | |
5216 | sb_data_e2.common.p_func.vnic_id = BP_VN(bp); | |
5217 | sb_data_e2.common.same_igu_sb_1b = true; | |
5218 | sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); | |
5219 | sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); | |
5220 | hc_sm_p = sb_data_e2.common.state_machine; | |
f2e0899f DK |
5221 | sb_data_p = (u32 *)&sb_data_e2; |
5222 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
150966ad | 5223 | bnx2x_map_sb_state_machines(sb_data_e2.index_data); |
f2e0899f DK |
5224 | } else { |
5225 | memset(&sb_data_e1x, 0, | |
5226 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5227 | sb_data_e1x.common.state = SB_ENABLED; |
f2e0899f DK |
5228 | sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); |
5229 | sb_data_e1x.common.p_func.vf_id = 0xff; | |
5230 | sb_data_e1x.common.p_func.vf_valid = false; | |
5231 | sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); | |
5232 | sb_data_e1x.common.same_igu_sb_1b = true; | |
5233 | sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); | |
5234 | sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); | |
5235 | hc_sm_p = sb_data_e1x.common.state_machine; | |
f2e0899f DK |
5236 | sb_data_p = (u32 *)&sb_data_e1x; |
5237 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
150966ad | 5238 | bnx2x_map_sb_state_machines(sb_data_e1x.index_data); |
f2e0899f | 5239 | } |
523224a3 DK |
5240 | |
5241 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], | |
5242 | igu_sb_id, igu_seg_id); | |
5243 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], | |
5244 | igu_sb_id, igu_seg_id); | |
5245 | ||
51c1a580 | 5246 | DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); |
523224a3 DK |
5247 | |
5248 | /* write indecies to HW */ | |
5249 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); | |
5250 | } | |
5251 | ||
619c5cb6 | 5252 | static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, |
523224a3 DK |
5253 | u16 tx_usec, u16 rx_usec) |
5254 | { | |
6383c0b3 | 5255 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, |
523224a3 | 5256 | false, rx_usec); |
6383c0b3 AE |
5257 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
5258 | HC_INDEX_ETH_TX_CQ_CONS_COS0, false, | |
5259 | tx_usec); | |
5260 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5261 | HC_INDEX_ETH_TX_CQ_CONS_COS1, false, | |
5262 | tx_usec); | |
5263 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5264 | HC_INDEX_ETH_TX_CQ_CONS_COS2, false, | |
5265 | tx_usec); | |
523224a3 | 5266 | } |
f2e0899f | 5267 | |
523224a3 DK |
5268 | static void bnx2x_init_def_sb(struct bnx2x *bp) |
5269 | { | |
5270 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
5271 | dma_addr_t mapping = bp->def_status_blk_mapping; | |
5272 | int igu_sp_sb_index; | |
5273 | int igu_seg_id; | |
34f80b04 EG |
5274 | int port = BP_PORT(bp); |
5275 | int func = BP_FUNC(bp); | |
f2eaeb58 | 5276 | int reg_offset, reg_offset_en5; |
a2fbb9ea | 5277 | u64 section; |
523224a3 DK |
5278 | int index; |
5279 | struct hc_sp_status_block_data sp_sb_data; | |
5280 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
5281 | ||
f2e0899f DK |
5282 | if (CHIP_INT_MODE_IS_BC(bp)) { |
5283 | igu_sp_sb_index = DEF_SB_IGU_ID; | |
5284 | igu_seg_id = HC_SEG_ACCESS_DEF; | |
5285 | } else { | |
5286 | igu_sp_sb_index = bp->igu_dsb_id; | |
5287 | igu_seg_id = IGU_SEG_ACCESS_DEF; | |
5288 | } | |
a2fbb9ea ET |
5289 | |
5290 | /* ATTN */ | |
523224a3 | 5291 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
a2fbb9ea | 5292 | atten_status_block); |
523224a3 | 5293 | def_sb->atten_status_block.status_block_id = igu_sp_sb_index; |
a2fbb9ea | 5294 | |
49d66772 ET |
5295 | bp->attn_state = 0; |
5296 | ||
a2fbb9ea ET |
5297 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
5298 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
f2eaeb58 DK |
5299 | reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : |
5300 | MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); | |
34f80b04 | 5301 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
523224a3 DK |
5302 | int sindex; |
5303 | /* take care of sig[0]..sig[4] */ | |
5304 | for (sindex = 0; sindex < 4; sindex++) | |
5305 | bp->attn_group[index].sig[sindex] = | |
5306 | REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); | |
f2e0899f | 5307 | |
619c5cb6 | 5308 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5309 | /* |
5310 | * enable5 is separate from the rest of the registers, | |
5311 | * and therefore the address skip is 4 | |
5312 | * and not 16 between the different groups | |
5313 | */ | |
5314 | bp->attn_group[index].sig[4] = REG_RD(bp, | |
f2eaeb58 | 5315 | reg_offset_en5 + 0x4*index); |
f2e0899f DK |
5316 | else |
5317 | bp->attn_group[index].sig[4] = 0; | |
a2fbb9ea ET |
5318 | } |
5319 | ||
f2e0899f DK |
5320 | if (bp->common.int_block == INT_BLOCK_HC) { |
5321 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : | |
5322 | HC_REG_ATTN_MSG0_ADDR_L); | |
5323 | ||
5324 | REG_WR(bp, reg_offset, U64_LO(section)); | |
5325 | REG_WR(bp, reg_offset + 4, U64_HI(section)); | |
619c5cb6 | 5326 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5327 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); |
5328 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); | |
5329 | } | |
a2fbb9ea | 5330 | |
523224a3 DK |
5331 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
5332 | sp_sb); | |
a2fbb9ea | 5333 | |
523224a3 | 5334 | bnx2x_zero_sp_sb(bp); |
a2fbb9ea | 5335 | |
619c5cb6 | 5336 | sp_sb_data.state = SB_ENABLED; |
523224a3 DK |
5337 | sp_sb_data.host_sb_addr.lo = U64_LO(section); |
5338 | sp_sb_data.host_sb_addr.hi = U64_HI(section); | |
5339 | sp_sb_data.igu_sb_id = igu_sp_sb_index; | |
5340 | sp_sb_data.igu_seg_id = igu_seg_id; | |
5341 | sp_sb_data.p_func.pf_id = func; | |
f2e0899f | 5342 | sp_sb_data.p_func.vnic_id = BP_VN(bp); |
523224a3 | 5343 | sp_sb_data.p_func.vf_id = 0xff; |
a2fbb9ea | 5344 | |
523224a3 | 5345 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
49d66772 | 5346 | |
523224a3 | 5347 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); |
a2fbb9ea ET |
5348 | } |
5349 | ||
9f6c9258 | 5350 | void bnx2x_update_coalesce(struct bnx2x *bp) |
a2fbb9ea | 5351 | { |
a2fbb9ea ET |
5352 | int i; |
5353 | ||
ec6ba945 | 5354 | for_each_eth_queue(bp, i) |
523224a3 | 5355 | bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, |
423cfa7e | 5356 | bp->tx_ticks, bp->rx_ticks); |
a2fbb9ea ET |
5357 | } |
5358 | ||
a2fbb9ea ET |
5359 | static void bnx2x_init_sp_ring(struct bnx2x *bp) |
5360 | { | |
a2fbb9ea | 5361 | spin_lock_init(&bp->spq_lock); |
6e30dd4e | 5362 | atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); |
a2fbb9ea | 5363 | |
a2fbb9ea | 5364 | bp->spq_prod_idx = 0; |
a2fbb9ea ET |
5365 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
5366 | bp->spq_prod_bd = bp->spq; | |
5367 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; | |
a2fbb9ea ET |
5368 | } |
5369 | ||
523224a3 | 5370 | static void bnx2x_init_eq_ring(struct bnx2x *bp) |
a2fbb9ea ET |
5371 | { |
5372 | int i; | |
523224a3 DK |
5373 | for (i = 1; i <= NUM_EQ_PAGES; i++) { |
5374 | union event_ring_elem *elem = | |
5375 | &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; | |
a2fbb9ea | 5376 | |
523224a3 DK |
5377 | elem->next_page.addr.hi = |
5378 | cpu_to_le32(U64_HI(bp->eq_mapping + | |
5379 | BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); | |
5380 | elem->next_page.addr.lo = | |
5381 | cpu_to_le32(U64_LO(bp->eq_mapping + | |
5382 | BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); | |
a2fbb9ea | 5383 | } |
523224a3 DK |
5384 | bp->eq_cons = 0; |
5385 | bp->eq_prod = NUM_EQ_DESC; | |
5386 | bp->eq_cons_sb = BNX2X_EQ_INDEX; | |
6e30dd4e VZ |
5387 | /* we want a warning message before it gets rought... */ |
5388 | atomic_set(&bp->eq_spq_left, | |
5389 | min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); | |
a2fbb9ea ET |
5390 | } |
5391 | ||
619c5cb6 VZ |
5392 | |
5393 | /* called with netif_addr_lock_bh() */ | |
5394 | void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, | |
5395 | unsigned long rx_mode_flags, | |
5396 | unsigned long rx_accept_flags, | |
5397 | unsigned long tx_accept_flags, | |
5398 | unsigned long ramrod_flags) | |
ab532cf3 | 5399 | { |
619c5cb6 VZ |
5400 | struct bnx2x_rx_mode_ramrod_params ramrod_param; |
5401 | int rc; | |
5402 | ||
5403 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
5404 | ||
5405 | /* Prepare ramrod parameters */ | |
5406 | ramrod_param.cid = 0; | |
5407 | ramrod_param.cl_id = cl_id; | |
5408 | ramrod_param.rx_mode_obj = &bp->rx_mode_obj; | |
5409 | ramrod_param.func_id = BP_FUNC(bp); | |
ab532cf3 | 5410 | |
619c5cb6 VZ |
5411 | ramrod_param.pstate = &bp->sp_state; |
5412 | ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; | |
ab532cf3 | 5413 | |
619c5cb6 VZ |
5414 | ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); |
5415 | ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); | |
5416 | ||
5417 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
5418 | ||
5419 | ramrod_param.ramrod_flags = ramrod_flags; | |
5420 | ramrod_param.rx_mode_flags = rx_mode_flags; | |
5421 | ||
5422 | ramrod_param.rx_accept_flags = rx_accept_flags; | |
5423 | ramrod_param.tx_accept_flags = tx_accept_flags; | |
5424 | ||
5425 | rc = bnx2x_config_rx_mode(bp, &ramrod_param); | |
5426 | if (rc < 0) { | |
5427 | BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); | |
5428 | return; | |
5429 | } | |
a2fbb9ea ET |
5430 | } |
5431 | ||
619c5cb6 VZ |
5432 | /* called with netif_addr_lock_bh() */ |
5433 | void bnx2x_set_storm_rx_mode(struct bnx2x *bp) | |
471de716 | 5434 | { |
619c5cb6 VZ |
5435 | unsigned long rx_mode_flags = 0, ramrod_flags = 0; |
5436 | unsigned long rx_accept_flags = 0, tx_accept_flags = 0; | |
471de716 | 5437 | |
619c5cb6 VZ |
5438 | #ifdef BCM_CNIC |
5439 | if (!NO_FCOE(bp)) | |
5440 | ||
5441 | /* Configure rx_mode of FCoE Queue */ | |
5442 | __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); | |
5443 | #endif | |
5444 | ||
5445 | switch (bp->rx_mode) { | |
5446 | case BNX2X_RX_MODE_NONE: | |
5447 | /* | |
5448 | * 'drop all' supersedes any accept flags that may have been | |
5449 | * passed to the function. | |
5450 | */ | |
5451 | break; | |
5452 | case BNX2X_RX_MODE_NORMAL: | |
5453 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5454 | __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); | |
5455 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5456 | ||
5457 | /* internal switching mode */ | |
5458 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5459 | __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); | |
5460 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5461 | ||
5462 | break; | |
5463 | case BNX2X_RX_MODE_ALLMULTI: | |
5464 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5465 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5466 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5467 | ||
5468 | /* internal switching mode */ | |
5469 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5470 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5471 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5472 | ||
5473 | break; | |
5474 | case BNX2X_RX_MODE_PROMISC: | |
5475 | /* According to deffinition of SI mode, iface in promisc mode | |
5476 | * should receive matched and unmatched (in resolution of port) | |
5477 | * unicast packets. | |
5478 | */ | |
5479 | __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); | |
5480 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5481 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5482 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5483 | ||
5484 | /* internal switching mode */ | |
5485 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5486 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5487 | ||
5488 | if (IS_MF_SI(bp)) | |
5489 | __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); | |
5490 | else | |
5491 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5492 | ||
5493 | break; | |
5494 | default: | |
5495 | BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); | |
5496 | return; | |
5497 | } | |
de832a55 | 5498 | |
619c5cb6 VZ |
5499 | if (bp->rx_mode != BNX2X_RX_MODE_NONE) { |
5500 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); | |
5501 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); | |
34f80b04 EG |
5502 | } |
5503 | ||
619c5cb6 VZ |
5504 | __set_bit(RAMROD_RX, &ramrod_flags); |
5505 | __set_bit(RAMROD_TX, &ramrod_flags); | |
5506 | ||
5507 | bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, | |
5508 | tx_accept_flags, ramrod_flags); | |
5509 | } | |
5510 | ||
5511 | static void bnx2x_init_internal_common(struct bnx2x *bp) | |
5512 | { | |
5513 | int i; | |
5514 | ||
0793f83f DK |
5515 | if (IS_MF_SI(bp)) |
5516 | /* | |
5517 | * In switch independent mode, the TSTORM needs to accept | |
5518 | * packets that failed classification, since approximate match | |
5519 | * mac addresses aren't written to NIG LLH | |
5520 | */ | |
5521 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5522 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); | |
619c5cb6 VZ |
5523 | else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ |
5524 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5525 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); | |
0793f83f | 5526 | |
523224a3 DK |
5527 | /* Zero this manually as its initialization is |
5528 | currently missing in the initTool */ | |
5529 | for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) | |
ca00392c | 5530 | REG_WR(bp, BAR_USTRORM_INTMEM + |
523224a3 | 5531 | USTORM_AGG_DATA_OFFSET + i * 4, 0); |
619c5cb6 | 5532 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5533 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, |
5534 | CHIP_INT_MODE_IS_BC(bp) ? | |
5535 | HC_IGU_BC_MODE : HC_IGU_NBC_MODE); | |
5536 | } | |
523224a3 | 5537 | } |
8a1c38d1 | 5538 | |
471de716 EG |
5539 | static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) |
5540 | { | |
5541 | switch (load_code) { | |
5542 | case FW_MSG_CODE_DRV_LOAD_COMMON: | |
f2e0899f | 5543 | case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: |
471de716 EG |
5544 | bnx2x_init_internal_common(bp); |
5545 | /* no break */ | |
5546 | ||
5547 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
619c5cb6 | 5548 | /* nothing to do */ |
471de716 EG |
5549 | /* no break */ |
5550 | ||
5551 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
523224a3 DK |
5552 | /* internal memory per function is |
5553 | initialized inside bnx2x_pf_init */ | |
471de716 EG |
5554 | break; |
5555 | ||
5556 | default: | |
5557 | BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); | |
5558 | break; | |
5559 | } | |
5560 | } | |
5561 | ||
619c5cb6 | 5562 | static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) |
523224a3 | 5563 | { |
6383c0b3 | 5564 | return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; |
619c5cb6 | 5565 | } |
523224a3 | 5566 | |
619c5cb6 VZ |
5567 | static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) |
5568 | { | |
6383c0b3 | 5569 | return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; |
619c5cb6 VZ |
5570 | } |
5571 | ||
5572 | static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) | |
5573 | { | |
5574 | if (CHIP_IS_E1x(fp->bp)) | |
5575 | return BP_L_ID(fp->bp) + fp->index; | |
5576 | else /* We want Client ID to be the same as IGU SB ID for 57712 */ | |
5577 | return bnx2x_fp_igu_sb_id(fp); | |
5578 | } | |
5579 | ||
6383c0b3 | 5580 | static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) |
619c5cb6 VZ |
5581 | { |
5582 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; | |
6383c0b3 | 5583 | u8 cos; |
619c5cb6 | 5584 | unsigned long q_type = 0; |
6383c0b3 | 5585 | u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; |
f233cafe | 5586 | fp->rx_queue = fp_idx; |
b3b83c3f | 5587 | fp->cid = fp_idx; |
619c5cb6 VZ |
5588 | fp->cl_id = bnx2x_fp_cl_id(fp); |
5589 | fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); | |
5590 | fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); | |
523224a3 | 5591 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 VZ |
5592 | fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); |
5593 | ||
523224a3 | 5594 | /* init shortcut */ |
619c5cb6 | 5595 | fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); |
7a752993 | 5596 | |
523224a3 DK |
5597 | /* Setup SB indicies */ |
5598 | fp->rx_cons_sb = BNX2X_RX_SB_INDEX; | |
523224a3 | 5599 | |
619c5cb6 VZ |
5600 | /* Configure Queue State object */ |
5601 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
5602 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
5603 | |
5604 | BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); | |
5605 | ||
5606 | /* init tx data */ | |
5607 | for_each_cos_in_tx_queue(fp, cos) { | |
5608 | bnx2x_init_txdata(bp, &fp->txdata[cos], | |
5609 | CID_COS_TO_TX_ONLY_CID(fp->cid, cos), | |
5610 | FP_COS_TO_TXQ(fp, cos), | |
5611 | BNX2X_TX_SB_INDEX_BASE + cos); | |
5612 | cids[cos] = fp->txdata[cos].cid; | |
5613 | } | |
5614 | ||
5615 | bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, | |
5616 | BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
5617 | bnx2x_sp_mapping(bp, q_rdata), q_type); | |
619c5cb6 VZ |
5618 | |
5619 | /** | |
5620 | * Configure classification DBs: Always enable Tx switching | |
5621 | */ | |
5622 | bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); | |
5623 | ||
51c1a580 | 5624 | DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", |
619c5cb6 | 5625 | fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, |
523224a3 DK |
5626 | fp->igu_sb_id); |
5627 | bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, | |
5628 | fp->fw_sb_id, fp->igu_sb_id); | |
5629 | ||
5630 | bnx2x_update_fpsb_idx(fp); | |
5631 | } | |
5632 | ||
9f6c9258 | 5633 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) |
a2fbb9ea ET |
5634 | { |
5635 | int i; | |
5636 | ||
ec6ba945 | 5637 | for_each_eth_queue(bp, i) |
6383c0b3 | 5638 | bnx2x_init_eth_fp(bp, i); |
37b091ba | 5639 | #ifdef BCM_CNIC |
ec6ba945 VZ |
5640 | if (!NO_FCOE(bp)) |
5641 | bnx2x_init_fcoe_fp(bp); | |
523224a3 DK |
5642 | |
5643 | bnx2x_init_sb(bp, bp->cnic_sb_mapping, | |
5644 | BNX2X_VF_ID_INVALID, false, | |
619c5cb6 | 5645 | bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); |
523224a3 | 5646 | |
37b091ba | 5647 | #endif |
a2fbb9ea | 5648 | |
020c7e3f YR |
5649 | /* Initialize MOD_ABS interrupts */ |
5650 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, | |
5651 | bp->common.shmem_base, bp->common.shmem2_base, | |
5652 | BP_PORT(bp)); | |
16119785 EG |
5653 | /* ensure status block indices were read */ |
5654 | rmb(); | |
5655 | ||
523224a3 | 5656 | bnx2x_init_def_sb(bp); |
5c862848 | 5657 | bnx2x_update_dsb_idx(bp); |
a2fbb9ea | 5658 | bnx2x_init_rx_rings(bp); |
523224a3 | 5659 | bnx2x_init_tx_rings(bp); |
a2fbb9ea | 5660 | bnx2x_init_sp_ring(bp); |
523224a3 | 5661 | bnx2x_init_eq_ring(bp); |
471de716 | 5662 | bnx2x_init_internal(bp, load_code); |
523224a3 | 5663 | bnx2x_pf_init(bp); |
0ef00459 EG |
5664 | bnx2x_stats_init(bp); |
5665 | ||
0ef00459 EG |
5666 | /* flush all before enabling interrupts */ |
5667 | mb(); | |
5668 | mmiowb(); | |
5669 | ||
615f8fd9 | 5670 | bnx2x_int_enable(bp); |
eb8da205 EG |
5671 | |
5672 | /* Check for SPIO5 */ | |
5673 | bnx2x_attn_int_deasserted0(bp, | |
5674 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & | |
5675 | AEU_INPUTS_ATTN_BITS_SPIO5); | |
a2fbb9ea ET |
5676 | } |
5677 | ||
5678 | /* end of nic init */ | |
5679 | ||
5680 | /* | |
5681 | * gzip service functions | |
5682 | */ | |
5683 | ||
5684 | static int bnx2x_gunzip_init(struct bnx2x *bp) | |
5685 | { | |
1a983142 FT |
5686 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
5687 | &bp->gunzip_mapping, GFP_KERNEL); | |
a2fbb9ea ET |
5688 | if (bp->gunzip_buf == NULL) |
5689 | goto gunzip_nomem1; | |
5690 | ||
5691 | bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); | |
5692 | if (bp->strm == NULL) | |
5693 | goto gunzip_nomem2; | |
5694 | ||
7ab24bfd | 5695 | bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); |
a2fbb9ea ET |
5696 | if (bp->strm->workspace == NULL) |
5697 | goto gunzip_nomem3; | |
5698 | ||
5699 | return 0; | |
5700 | ||
5701 | gunzip_nomem3: | |
5702 | kfree(bp->strm); | |
5703 | bp->strm = NULL; | |
5704 | ||
5705 | gunzip_nomem2: | |
1a983142 FT |
5706 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
5707 | bp->gunzip_mapping); | |
a2fbb9ea ET |
5708 | bp->gunzip_buf = NULL; |
5709 | ||
5710 | gunzip_nomem1: | |
51c1a580 | 5711 | BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); |
a2fbb9ea ET |
5712 | return -ENOMEM; |
5713 | } | |
5714 | ||
5715 | static void bnx2x_gunzip_end(struct bnx2x *bp) | |
5716 | { | |
b3b83c3f | 5717 | if (bp->strm) { |
7ab24bfd | 5718 | vfree(bp->strm->workspace); |
b3b83c3f DK |
5719 | kfree(bp->strm); |
5720 | bp->strm = NULL; | |
5721 | } | |
a2fbb9ea ET |
5722 | |
5723 | if (bp->gunzip_buf) { | |
1a983142 FT |
5724 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
5725 | bp->gunzip_mapping); | |
a2fbb9ea ET |
5726 | bp->gunzip_buf = NULL; |
5727 | } | |
5728 | } | |
5729 | ||
94a78b79 | 5730 | static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) |
a2fbb9ea ET |
5731 | { |
5732 | int n, rc; | |
5733 | ||
5734 | /* check gzip header */ | |
94a78b79 VZ |
5735 | if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { |
5736 | BNX2X_ERR("Bad gzip header\n"); | |
a2fbb9ea | 5737 | return -EINVAL; |
94a78b79 | 5738 | } |
a2fbb9ea ET |
5739 | |
5740 | n = 10; | |
5741 | ||
34f80b04 | 5742 | #define FNAME 0x8 |
a2fbb9ea ET |
5743 | |
5744 | if (zbuf[3] & FNAME) | |
5745 | while ((zbuf[n++] != 0) && (n < len)); | |
5746 | ||
94a78b79 | 5747 | bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; |
a2fbb9ea ET |
5748 | bp->strm->avail_in = len - n; |
5749 | bp->strm->next_out = bp->gunzip_buf; | |
5750 | bp->strm->avail_out = FW_BUF_SIZE; | |
5751 | ||
5752 | rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); | |
5753 | if (rc != Z_OK) | |
5754 | return rc; | |
5755 | ||
5756 | rc = zlib_inflate(bp->strm, Z_FINISH); | |
5757 | if ((rc != Z_OK) && (rc != Z_STREAM_END)) | |
7995c64e JP |
5758 | netdev_err(bp->dev, "Firmware decompression error: %s\n", |
5759 | bp->strm->msg); | |
a2fbb9ea ET |
5760 | |
5761 | bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); | |
5762 | if (bp->gunzip_outlen & 0x3) | |
51c1a580 MS |
5763 | netdev_err(bp->dev, |
5764 | "Firmware decompression error: gunzip_outlen (%d) not aligned\n", | |
cdaa7cb8 | 5765 | bp->gunzip_outlen); |
a2fbb9ea ET |
5766 | bp->gunzip_outlen >>= 2; |
5767 | ||
5768 | zlib_inflateEnd(bp->strm); | |
5769 | ||
5770 | if (rc == Z_STREAM_END) | |
5771 | return 0; | |
5772 | ||
5773 | return rc; | |
5774 | } | |
5775 | ||
5776 | /* nic load/unload */ | |
5777 | ||
5778 | /* | |
34f80b04 | 5779 | * General service functions |
a2fbb9ea ET |
5780 | */ |
5781 | ||
5782 | /* send a NIG loopback debug packet */ | |
5783 | static void bnx2x_lb_pckt(struct bnx2x *bp) | |
5784 | { | |
a2fbb9ea | 5785 | u32 wb_write[3]; |
a2fbb9ea ET |
5786 | |
5787 | /* Ethernet source and destination addresses */ | |
a2fbb9ea ET |
5788 | wb_write[0] = 0x55555555; |
5789 | wb_write[1] = 0x55555555; | |
34f80b04 | 5790 | wb_write[2] = 0x20; /* SOP */ |
a2fbb9ea | 5791 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
5792 | |
5793 | /* NON-IP protocol */ | |
a2fbb9ea ET |
5794 | wb_write[0] = 0x09000000; |
5795 | wb_write[1] = 0x55555555; | |
34f80b04 | 5796 | wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ |
a2fbb9ea | 5797 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
5798 | } |
5799 | ||
5800 | /* some of the internal memories | |
5801 | * are not directly readable from the driver | |
5802 | * to test them we send debug packets | |
5803 | */ | |
5804 | static int bnx2x_int_mem_test(struct bnx2x *bp) | |
5805 | { | |
5806 | int factor; | |
5807 | int count, i; | |
5808 | u32 val = 0; | |
5809 | ||
ad8d3948 | 5810 | if (CHIP_REV_IS_FPGA(bp)) |
a2fbb9ea | 5811 | factor = 120; |
ad8d3948 EG |
5812 | else if (CHIP_REV_IS_EMUL(bp)) |
5813 | factor = 200; | |
5814 | else | |
a2fbb9ea | 5815 | factor = 1; |
a2fbb9ea | 5816 | |
a2fbb9ea ET |
5817 | /* Disable inputs of parser neighbor blocks */ |
5818 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
5819 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
5820 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 5821 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
5822 | |
5823 | /* Write 0 to parser credits for CFC search request */ | |
5824 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
5825 | ||
5826 | /* send Ethernet packet */ | |
5827 | bnx2x_lb_pckt(bp); | |
5828 | ||
5829 | /* TODO do i reset NIG statistic? */ | |
5830 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
5831 | count = 1000 * factor; | |
5832 | while (count) { | |
34f80b04 | 5833 | |
a2fbb9ea ET |
5834 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
5835 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
5836 | if (val == 0x10) |
5837 | break; | |
5838 | ||
5839 | msleep(10); | |
5840 | count--; | |
5841 | } | |
5842 | if (val != 0x10) { | |
5843 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
5844 | return -1; | |
5845 | } | |
5846 | ||
5847 | /* Wait until PRS register shows 1 packet */ | |
5848 | count = 1000 * factor; | |
5849 | while (count) { | |
5850 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
a2fbb9ea ET |
5851 | if (val == 1) |
5852 | break; | |
5853 | ||
5854 | msleep(10); | |
5855 | count--; | |
5856 | } | |
5857 | if (val != 0x1) { | |
5858 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5859 | return -2; | |
5860 | } | |
5861 | ||
5862 | /* Reset and init BRB, PRS */ | |
34f80b04 | 5863 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
a2fbb9ea | 5864 | msleep(50); |
34f80b04 | 5865 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
a2fbb9ea | 5866 | msleep(50); |
619c5cb6 VZ |
5867 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
5868 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
a2fbb9ea ET |
5869 | |
5870 | DP(NETIF_MSG_HW, "part2\n"); | |
5871 | ||
5872 | /* Disable inputs of parser neighbor blocks */ | |
5873 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
5874 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
5875 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 5876 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
5877 | |
5878 | /* Write 0 to parser credits for CFC search request */ | |
5879 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
5880 | ||
5881 | /* send 10 Ethernet packets */ | |
5882 | for (i = 0; i < 10; i++) | |
5883 | bnx2x_lb_pckt(bp); | |
5884 | ||
5885 | /* Wait until NIG register shows 10 + 1 | |
5886 | packets of size 11*0x10 = 0xb0 */ | |
5887 | count = 1000 * factor; | |
5888 | while (count) { | |
34f80b04 | 5889 | |
a2fbb9ea ET |
5890 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
5891 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
5892 | if (val == 0xb0) |
5893 | break; | |
5894 | ||
5895 | msleep(10); | |
5896 | count--; | |
5897 | } | |
5898 | if (val != 0xb0) { | |
5899 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
5900 | return -3; | |
5901 | } | |
5902 | ||
5903 | /* Wait until PRS register shows 2 packets */ | |
5904 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
5905 | if (val != 2) | |
5906 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5907 | ||
5908 | /* Write 1 to parser credits for CFC search request */ | |
5909 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); | |
5910 | ||
5911 | /* Wait until PRS register shows 3 packets */ | |
5912 | msleep(10 * factor); | |
5913 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
5914 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
5915 | if (val != 3) | |
5916 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5917 | ||
5918 | /* clear NIG EOP FIFO */ | |
5919 | for (i = 0; i < 11; i++) | |
5920 | REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); | |
5921 | val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); | |
5922 | if (val != 1) { | |
5923 | BNX2X_ERR("clear of NIG failed\n"); | |
5924 | return -4; | |
5925 | } | |
5926 | ||
5927 | /* Reset and init BRB, PRS, NIG */ | |
5928 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); | |
5929 | msleep(50); | |
5930 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); | |
5931 | msleep(50); | |
619c5cb6 VZ |
5932 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
5933 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
37b091ba | 5934 | #ifndef BCM_CNIC |
a2fbb9ea ET |
5935 | /* set NIC mode */ |
5936 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
5937 | #endif | |
5938 | ||
5939 | /* Enable inputs of parser neighbor blocks */ | |
5940 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); | |
5941 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); | |
5942 | REG_WR(bp, CFC_REG_DEBUG0, 0x0); | |
3196a88a | 5943 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); |
a2fbb9ea ET |
5944 | |
5945 | DP(NETIF_MSG_HW, "done\n"); | |
5946 | ||
5947 | return 0; /* OK */ | |
5948 | } | |
5949 | ||
4a33bc03 | 5950 | static void bnx2x_enable_blocks_attention(struct bnx2x *bp) |
a2fbb9ea ET |
5951 | { |
5952 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
619c5cb6 | 5953 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5954 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); |
5955 | else | |
5956 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); | |
a2fbb9ea ET |
5957 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
5958 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
f2e0899f DK |
5959 | /* |
5960 | * mask read length error interrupts in brb for parser | |
5961 | * (parsing unit and 'checksum and crc' unit) | |
5962 | * these errors are legal (PU reads fixed length and CAC can cause | |
5963 | * read length error on truncated packets) | |
5964 | */ | |
5965 | REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); | |
a2fbb9ea ET |
5966 | REG_WR(bp, QM_REG_QM_INT_MASK, 0); |
5967 | REG_WR(bp, TM_REG_TM_INT_MASK, 0); | |
5968 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); | |
5969 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); | |
5970 | REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); | |
34f80b04 EG |
5971 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ |
5972 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
5973 | REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); |
5974 | REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); | |
5975 | REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); | |
34f80b04 EG |
5976 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ |
5977 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
5978 | REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); |
5979 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); | |
5980 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); | |
5981 | REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); | |
34f80b04 EG |
5982 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ |
5983 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ | |
f85582f8 | 5984 | |
34f80b04 EG |
5985 | if (CHIP_REV_IS_FPGA(bp)) |
5986 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); | |
619c5cb6 | 5987 | else if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5988 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, |
5989 | (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | |
5990 | | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | |
5991 | | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN | |
5992 | | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | |
5993 | | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); | |
34f80b04 EG |
5994 | else |
5995 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); | |
a2fbb9ea ET |
5996 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); |
5997 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); | |
5998 | REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); | |
34f80b04 | 5999 | /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ |
619c5cb6 VZ |
6000 | |
6001 | if (!CHIP_IS_E1x(bp)) | |
6002 | /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ | |
6003 | REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); | |
6004 | ||
a2fbb9ea ET |
6005 | REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); |
6006 | REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); | |
34f80b04 | 6007 | /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ |
4a33bc03 | 6008 | REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ |
a2fbb9ea ET |
6009 | } |
6010 | ||
81f75bbf EG |
6011 | static void bnx2x_reset_common(struct bnx2x *bp) |
6012 | { | |
619c5cb6 VZ |
6013 | u32 val = 0x1400; |
6014 | ||
81f75bbf EG |
6015 | /* reset_common */ |
6016 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6017 | 0xd3ffff7f); | |
619c5cb6 VZ |
6018 | |
6019 | if (CHIP_IS_E3(bp)) { | |
6020 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6021 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6022 | } | |
6023 | ||
6024 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); | |
6025 | } | |
6026 | ||
6027 | static void bnx2x_setup_dmae(struct bnx2x *bp) | |
6028 | { | |
6029 | bp->dmae_ready = 0; | |
6030 | spin_lock_init(&bp->dmae_lock); | |
81f75bbf EG |
6031 | } |
6032 | ||
573f2035 EG |
6033 | static void bnx2x_init_pxp(struct bnx2x *bp) |
6034 | { | |
6035 | u16 devctl; | |
6036 | int r_order, w_order; | |
6037 | ||
6038 | pci_read_config_word(bp->pdev, | |
b6c2f86e | 6039 | pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); |
573f2035 EG |
6040 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
6041 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | |
6042 | if (bp->mrrs == -1) | |
6043 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
6044 | else { | |
6045 | DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); | |
6046 | r_order = bp->mrrs; | |
6047 | } | |
6048 | ||
6049 | bnx2x_init_pxp_arb(bp, r_order, w_order); | |
6050 | } | |
fd4ef40d EG |
6051 | |
6052 | static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) | |
6053 | { | |
2145a920 | 6054 | int is_required; |
fd4ef40d | 6055 | u32 val; |
2145a920 | 6056 | int port; |
fd4ef40d | 6057 | |
2145a920 VZ |
6058 | if (BP_NOMCP(bp)) |
6059 | return; | |
6060 | ||
6061 | is_required = 0; | |
fd4ef40d EG |
6062 | val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
6063 | SHARED_HW_CFG_FAN_FAILURE_MASK; | |
6064 | ||
6065 | if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) | |
6066 | is_required = 1; | |
6067 | ||
6068 | /* | |
6069 | * The fan failure mechanism is usually related to the PHY type since | |
6070 | * the power consumption of the board is affected by the PHY. Currently, | |
6071 | * fan is required for most designs with SFX7101, BCM8727 and BCM8481. | |
6072 | */ | |
6073 | else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) | |
6074 | for (port = PORT_0; port < PORT_MAX; port++) { | |
fd4ef40d | 6075 | is_required |= |
d90d96ba YR |
6076 | bnx2x_fan_failure_det_req( |
6077 | bp, | |
6078 | bp->common.shmem_base, | |
a22f0788 | 6079 | bp->common.shmem2_base, |
d90d96ba | 6080 | port); |
fd4ef40d EG |
6081 | } |
6082 | ||
6083 | DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); | |
6084 | ||
6085 | if (is_required == 0) | |
6086 | return; | |
6087 | ||
6088 | /* Fan failure is indicated by SPIO 5 */ | |
6089 | bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, | |
6090 | MISC_REGISTERS_SPIO_INPUT_HI_Z); | |
6091 | ||
6092 | /* set to active low mode */ | |
6093 | val = REG_RD(bp, MISC_REG_SPIO_INT); | |
6094 | val |= ((1 << MISC_REGISTERS_SPIO_5) << | |
cdaa7cb8 | 6095 | MISC_REGISTERS_SPIO_INT_OLD_SET_POS); |
fd4ef40d EG |
6096 | REG_WR(bp, MISC_REG_SPIO_INT, val); |
6097 | ||
6098 | /* enable interrupt to signal the IGU */ | |
6099 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
6100 | val |= (1 << MISC_REGISTERS_SPIO_5); | |
6101 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); | |
6102 | } | |
6103 | ||
f2e0899f DK |
6104 | static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) |
6105 | { | |
6106 | u32 offset = 0; | |
6107 | ||
6108 | if (CHIP_IS_E1(bp)) | |
6109 | return; | |
6110 | if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) | |
6111 | return; | |
6112 | ||
6113 | switch (BP_ABS_FUNC(bp)) { | |
6114 | case 0: | |
6115 | offset = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
6116 | break; | |
6117 | case 1: | |
6118 | offset = PXP2_REG_PGL_PRETEND_FUNC_F1; | |
6119 | break; | |
6120 | case 2: | |
6121 | offset = PXP2_REG_PGL_PRETEND_FUNC_F2; | |
6122 | break; | |
6123 | case 3: | |
6124 | offset = PXP2_REG_PGL_PRETEND_FUNC_F3; | |
6125 | break; | |
6126 | case 4: | |
6127 | offset = PXP2_REG_PGL_PRETEND_FUNC_F4; | |
6128 | break; | |
6129 | case 5: | |
6130 | offset = PXP2_REG_PGL_PRETEND_FUNC_F5; | |
6131 | break; | |
6132 | case 6: | |
6133 | offset = PXP2_REG_PGL_PRETEND_FUNC_F6; | |
6134 | break; | |
6135 | case 7: | |
6136 | offset = PXP2_REG_PGL_PRETEND_FUNC_F7; | |
6137 | break; | |
6138 | default: | |
6139 | return; | |
6140 | } | |
6141 | ||
6142 | REG_WR(bp, offset, pretend_func_num); | |
6143 | REG_RD(bp, offset); | |
6144 | DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); | |
6145 | } | |
6146 | ||
c9ee9206 | 6147 | void bnx2x_pf_disable(struct bnx2x *bp) |
f2e0899f DK |
6148 | { |
6149 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
6150 | val &= ~IGU_PF_CONF_FUNC_EN; | |
6151 | ||
6152 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
6153 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6154 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); | |
6155 | } | |
6156 | ||
619c5cb6 VZ |
6157 | static inline void bnx2x__common_init_phy(struct bnx2x *bp) |
6158 | { | |
6159 | u32 shmem_base[2], shmem2_base[2]; | |
6160 | shmem_base[0] = bp->common.shmem_base; | |
6161 | shmem2_base[0] = bp->common.shmem2_base; | |
6162 | if (!CHIP_IS_E1x(bp)) { | |
6163 | shmem_base[1] = | |
6164 | SHMEM2_RD(bp, other_shmem_base_addr); | |
6165 | shmem2_base[1] = | |
6166 | SHMEM2_RD(bp, other_shmem2_base_addr); | |
6167 | } | |
6168 | bnx2x_acquire_phy_lock(bp); | |
6169 | bnx2x_common_init_phy(bp, shmem_base, shmem2_base, | |
6170 | bp->common.chip_id); | |
6171 | bnx2x_release_phy_lock(bp); | |
6172 | } | |
6173 | ||
6174 | /** | |
6175 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. | |
6176 | * | |
6177 | * @bp: driver handle | |
6178 | */ | |
6179 | static int bnx2x_init_hw_common(struct bnx2x *bp) | |
a2fbb9ea | 6180 | { |
619c5cb6 | 6181 | u32 val; |
a2fbb9ea | 6182 | |
51c1a580 | 6183 | DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); |
a2fbb9ea | 6184 | |
2031bd3a DK |
6185 | /* |
6186 | * take the UNDI lock to protect undi_unload flow from accessing | |
6187 | * registers while we're resetting the chip | |
6188 | */ | |
7a06a122 | 6189 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 6190 | |
81f75bbf | 6191 | bnx2x_reset_common(bp); |
34f80b04 | 6192 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
a2fbb9ea | 6193 | |
619c5cb6 VZ |
6194 | val = 0xfffc; |
6195 | if (CHIP_IS_E3(bp)) { | |
6196 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6197 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6198 | } | |
6199 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); | |
6200 | ||
7a06a122 | 6201 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 6202 | |
619c5cb6 | 6203 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); |
a2fbb9ea | 6204 | |
619c5cb6 VZ |
6205 | if (!CHIP_IS_E1x(bp)) { |
6206 | u8 abs_func_id; | |
f2e0899f DK |
6207 | |
6208 | /** | |
6209 | * 4-port mode or 2-port mode we need to turn of master-enable | |
6210 | * for everyone, after that, turn it back on for self. | |
6211 | * so, we disregard multi-function or not, and always disable | |
6212 | * for all functions on the given path, this means 0,2,4,6 for | |
6213 | * path 0 and 1,3,5,7 for path 1 | |
6214 | */ | |
619c5cb6 VZ |
6215 | for (abs_func_id = BP_PATH(bp); |
6216 | abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { | |
6217 | if (abs_func_id == BP_ABS_FUNC(bp)) { | |
f2e0899f DK |
6218 | REG_WR(bp, |
6219 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, | |
6220 | 1); | |
6221 | continue; | |
6222 | } | |
6223 | ||
619c5cb6 | 6224 | bnx2x_pretend_func(bp, abs_func_id); |
f2e0899f DK |
6225 | /* clear pf enable */ |
6226 | bnx2x_pf_disable(bp); | |
6227 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
6228 | } | |
6229 | } | |
a2fbb9ea | 6230 | |
619c5cb6 | 6231 | bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); |
34f80b04 EG |
6232 | if (CHIP_IS_E1(bp)) { |
6233 | /* enable HW interrupt from PXP on USDM overflow | |
6234 | bit 16 on INT_MASK_0 */ | |
6235 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
6236 | } | |
a2fbb9ea | 6237 | |
619c5cb6 | 6238 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
34f80b04 | 6239 | bnx2x_init_pxp(bp); |
a2fbb9ea ET |
6240 | |
6241 | #ifdef __BIG_ENDIAN | |
34f80b04 EG |
6242 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); |
6243 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); | |
6244 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); | |
6245 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); | |
6246 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); | |
8badd27a EG |
6247 | /* make sure this value is 0 */ |
6248 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | |
34f80b04 EG |
6249 | |
6250 | /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ | |
6251 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); | |
6252 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); | |
6253 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); | |
6254 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); | |
a2fbb9ea ET |
6255 | #endif |
6256 | ||
523224a3 DK |
6257 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
6258 | ||
34f80b04 EG |
6259 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
6260 | REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); | |
a2fbb9ea | 6261 | |
34f80b04 EG |
6262 | /* let the HW do it's magic ... */ |
6263 | msleep(100); | |
6264 | /* finish PXP init */ | |
6265 | val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); | |
6266 | if (val != 1) { | |
6267 | BNX2X_ERR("PXP2 CFG failed\n"); | |
6268 | return -EBUSY; | |
6269 | } | |
6270 | val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); | |
6271 | if (val != 1) { | |
6272 | BNX2X_ERR("PXP2 RD_INIT failed\n"); | |
6273 | return -EBUSY; | |
6274 | } | |
a2fbb9ea | 6275 | |
f2e0899f DK |
6276 | /* Timers bug workaround E2 only. We need to set the entire ILT to |
6277 | * have entries with value "0" and valid bit on. | |
6278 | * This needs to be done by the first PF that is loaded in a path | |
6279 | * (i.e. common phase) | |
6280 | */ | |
619c5cb6 VZ |
6281 | if (!CHIP_IS_E1x(bp)) { |
6282 | /* In E2 there is a bug in the timers block that can cause function 6 / 7 | |
6283 | * (i.e. vnic3) to start even if it is marked as "scan-off". | |
6284 | * This occurs when a different function (func2,3) is being marked | |
6285 | * as "scan-off". Real-life scenario for example: if a driver is being | |
6286 | * load-unloaded while func6,7 are down. This will cause the timer to access | |
6287 | * the ilt, translate to a logical address and send a request to read/write. | |
6288 | * Since the ilt for the function that is down is not valid, this will cause | |
6289 | * a translation error which is unrecoverable. | |
6290 | * The Workaround is intended to make sure that when this happens nothing fatal | |
6291 | * will occur. The workaround: | |
6292 | * 1. First PF driver which loads on a path will: | |
6293 | * a. After taking the chip out of reset, by using pretend, | |
6294 | * it will write "0" to the following registers of | |
6295 | * the other vnics. | |
6296 | * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6297 | * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); | |
6298 | * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); | |
6299 | * And for itself it will write '1' to | |
6300 | * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable | |
6301 | * dmae-operations (writing to pram for example.) | |
6302 | * note: can be done for only function 6,7 but cleaner this | |
6303 | * way. | |
6304 | * b. Write zero+valid to the entire ILT. | |
6305 | * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of | |
6306 | * VNIC3 (of that port). The range allocated will be the | |
6307 | * entire ILT. This is needed to prevent ILT range error. | |
6308 | * 2. Any PF driver load flow: | |
6309 | * a. ILT update with the physical addresses of the allocated | |
6310 | * logical pages. | |
6311 | * b. Wait 20msec. - note that this timeout is needed to make | |
6312 | * sure there are no requests in one of the PXP internal | |
6313 | * queues with "old" ILT addresses. | |
6314 | * c. PF enable in the PGLC. | |
6315 | * d. Clear the was_error of the PF in the PGLC. (could have | |
6316 | * occured while driver was down) | |
6317 | * e. PF enable in the CFC (WEAK + STRONG) | |
6318 | * f. Timers scan enable | |
6319 | * 3. PF driver unload flow: | |
6320 | * a. Clear the Timers scan_en. | |
6321 | * b. Polling for scan_on=0 for that PF. | |
6322 | * c. Clear the PF enable bit in the PXP. | |
6323 | * d. Clear the PF enable in the CFC (WEAK + STRONG) | |
6324 | * e. Write zero+valid to all ILT entries (The valid bit must | |
6325 | * stay set) | |
6326 | * f. If this is VNIC 3 of a port then also init | |
6327 | * first_timers_ilt_entry to zero and last_timers_ilt_entry | |
6328 | * to the last enrty in the ILT. | |
6329 | * | |
6330 | * Notes: | |
6331 | * Currently the PF error in the PGLC is non recoverable. | |
6332 | * In the future the there will be a recovery routine for this error. | |
6333 | * Currently attention is masked. | |
6334 | * Having an MCP lock on the load/unload process does not guarantee that | |
6335 | * there is no Timer disable during Func6/7 enable. This is because the | |
6336 | * Timers scan is currently being cleared by the MCP on FLR. | |
6337 | * Step 2.d can be done only for PF6/7 and the driver can also check if | |
6338 | * there is error before clearing it. But the flow above is simpler and | |
6339 | * more general. | |
6340 | * All ILT entries are written by zero+valid and not just PF6/7 | |
6341 | * ILT entries since in the future the ILT entries allocation for | |
6342 | * PF-s might be dynamic. | |
6343 | */ | |
f2e0899f DK |
6344 | struct ilt_client_info ilt_cli; |
6345 | struct bnx2x_ilt ilt; | |
6346 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
6347 | memset(&ilt, 0, sizeof(struct bnx2x_ilt)); | |
6348 | ||
b595076a | 6349 | /* initialize dummy TM client */ |
f2e0899f DK |
6350 | ilt_cli.start = 0; |
6351 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
6352 | ilt_cli.client_num = ILT_CLIENT_TM; | |
6353 | ||
6354 | /* Step 1: set zeroes to all ilt page entries with valid bit on | |
6355 | * Step 2: set the timers first/last ilt entry to point | |
6356 | * to the entire range to prevent ILT range error for 3rd/4th | |
619c5cb6 | 6357 | * vnic (this code assumes existance of the vnic) |
f2e0899f DK |
6358 | * |
6359 | * both steps performed by call to bnx2x_ilt_client_init_op() | |
6360 | * with dummy TM client | |
6361 | * | |
6362 | * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT | |
6363 | * and his brother are split registers | |
6364 | */ | |
6365 | bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); | |
6366 | bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); | |
6367 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
6368 | ||
6369 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); | |
6370 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); | |
6371 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); | |
6372 | } | |
6373 | ||
6374 | ||
34f80b04 EG |
6375 | REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); |
6376 | REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); | |
a2fbb9ea | 6377 | |
619c5cb6 | 6378 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6379 | int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : |
6380 | (CHIP_REV_IS_FPGA(bp) ? 400 : 0); | |
619c5cb6 | 6381 | bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); |
f2e0899f | 6382 | |
619c5cb6 | 6383 | bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); |
f2e0899f DK |
6384 | |
6385 | /* let the HW do it's magic ... */ | |
6386 | do { | |
6387 | msleep(200); | |
6388 | val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); | |
6389 | } while (factor-- && (val != 1)); | |
6390 | ||
6391 | if (val != 1) { | |
6392 | BNX2X_ERR("ATC_INIT failed\n"); | |
6393 | return -EBUSY; | |
6394 | } | |
6395 | } | |
6396 | ||
619c5cb6 | 6397 | bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); |
a2fbb9ea | 6398 | |
34f80b04 EG |
6399 | /* clean the DMAE memory */ |
6400 | bp->dmae_ready = 1; | |
619c5cb6 VZ |
6401 | bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); |
6402 | ||
6403 | bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); | |
6404 | ||
6405 | bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); | |
6406 | ||
6407 | bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); | |
a2fbb9ea | 6408 | |
619c5cb6 | 6409 | bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); |
a2fbb9ea | 6410 | |
34f80b04 EG |
6411 | bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); |
6412 | bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); | |
6413 | bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); | |
6414 | bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); | |
6415 | ||
619c5cb6 | 6416 | bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); |
37b091ba | 6417 | |
f85582f8 | 6418 | |
523224a3 DK |
6419 | /* QM queues pointers table */ |
6420 | bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); | |
6421 | ||
34f80b04 EG |
6422 | /* soft reset pulse */ |
6423 | REG_WR(bp, QM_REG_SOFT_RESET, 1); | |
6424 | REG_WR(bp, QM_REG_SOFT_RESET, 0); | |
a2fbb9ea | 6425 | |
37b091ba | 6426 | #ifdef BCM_CNIC |
619c5cb6 | 6427 | bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); |
a2fbb9ea | 6428 | #endif |
a2fbb9ea | 6429 | |
619c5cb6 | 6430 | bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); |
523224a3 | 6431 | REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); |
619c5cb6 | 6432 | if (!CHIP_REV_IS_SLOW(bp)) |
34f80b04 EG |
6433 | /* enable hw interrupt from doorbell Q */ |
6434 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); | |
a2fbb9ea | 6435 | |
619c5cb6 | 6436 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
f2e0899f | 6437 | |
619c5cb6 | 6438 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
26c8fa4d | 6439 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
619c5cb6 | 6440 | |
f2e0899f | 6441 | if (!CHIP_IS_E1(bp)) |
619c5cb6 | 6442 | REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); |
f85582f8 | 6443 | |
a3348722 BW |
6444 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { |
6445 | if (IS_MF_AFEX(bp)) { | |
6446 | /* configure that VNTag and VLAN headers must be | |
6447 | * received in afex mode | |
6448 | */ | |
6449 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); | |
6450 | REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); | |
6451 | REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); | |
6452 | REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); | |
6453 | REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); | |
6454 | } else { | |
6455 | /* Bit-map indicating which L2 hdrs may appear | |
6456 | * after the basic Ethernet header | |
6457 | */ | |
6458 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, | |
6459 | bp->path_has_ovlan ? 7 : 6); | |
6460 | } | |
6461 | } | |
a2fbb9ea | 6462 | |
619c5cb6 VZ |
6463 | bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); |
6464 | bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); | |
6465 | bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); | |
6466 | bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); | |
a2fbb9ea | 6467 | |
619c5cb6 VZ |
6468 | if (!CHIP_IS_E1x(bp)) { |
6469 | /* reset VFC memories */ | |
6470 | REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6471 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6472 | VFC_MEMORIES_RST_REG_RAM_RST); | |
6473 | REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6474 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6475 | VFC_MEMORIES_RST_REG_RAM_RST); | |
a2fbb9ea | 6476 | |
619c5cb6 VZ |
6477 | msleep(20); |
6478 | } | |
a2fbb9ea | 6479 | |
619c5cb6 VZ |
6480 | bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); |
6481 | bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); | |
6482 | bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); | |
6483 | bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); | |
f2e0899f | 6484 | |
34f80b04 EG |
6485 | /* sync semi rtc */ |
6486 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6487 | 0x80000000); | |
6488 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
6489 | 0x80000000); | |
a2fbb9ea | 6490 | |
619c5cb6 VZ |
6491 | bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); |
6492 | bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); | |
6493 | bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); | |
a2fbb9ea | 6494 | |
a3348722 BW |
6495 | if (!CHIP_IS_E1x(bp)) { |
6496 | if (IS_MF_AFEX(bp)) { | |
6497 | /* configure that VNTag and VLAN headers must be | |
6498 | * sent in afex mode | |
6499 | */ | |
6500 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); | |
6501 | REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); | |
6502 | REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); | |
6503 | REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); | |
6504 | REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); | |
6505 | } else { | |
6506 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, | |
6507 | bp->path_has_ovlan ? 7 : 6); | |
6508 | } | |
6509 | } | |
f2e0899f | 6510 | |
34f80b04 | 6511 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
f85582f8 | 6512 | |
619c5cb6 VZ |
6513 | bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); |
6514 | ||
37b091ba MC |
6515 | #ifdef BCM_CNIC |
6516 | REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); | |
6517 | REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); | |
6518 | REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); | |
6519 | REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); | |
6520 | REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); | |
6521 | REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); | |
6522 | REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); | |
6523 | REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); | |
6524 | REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); | |
6525 | REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); | |
6526 | #endif | |
34f80b04 | 6527 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
a2fbb9ea | 6528 | |
34f80b04 EG |
6529 | if (sizeof(union cdu_context) != 1024) |
6530 | /* we currently assume that a context is 1024 bytes */ | |
51c1a580 MS |
6531 | dev_alert(&bp->pdev->dev, |
6532 | "please adjust the size of cdu_context(%ld)\n", | |
6533 | (long)sizeof(union cdu_context)); | |
a2fbb9ea | 6534 | |
619c5cb6 | 6535 | bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); |
34f80b04 EG |
6536 | val = (4 << 24) + (0 << 12) + 1024; |
6537 | REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); | |
a2fbb9ea | 6538 | |
619c5cb6 | 6539 | bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); |
34f80b04 | 6540 | REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); |
8d9c5f34 EG |
6541 | /* enable context validation interrupt from CFC */ |
6542 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
6543 | ||
6544 | /* set the thresholds to prevent CFC/CDU race */ | |
6545 | REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); | |
a2fbb9ea | 6546 | |
619c5cb6 | 6547 | bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); |
f2e0899f | 6548 | |
619c5cb6 | 6549 | if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) |
f2e0899f DK |
6550 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); |
6551 | ||
619c5cb6 VZ |
6552 | bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); |
6553 | bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); | |
a2fbb9ea | 6554 | |
34f80b04 EG |
6555 | /* Reset PCIE errors for debug */ |
6556 | REG_WR(bp, 0x2814, 0xffffffff); | |
6557 | REG_WR(bp, 0x3820, 0xffffffff); | |
a2fbb9ea | 6558 | |
619c5cb6 | 6559 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6560 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, |
6561 | (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | | |
6562 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); | |
6563 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, | |
6564 | (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | | |
6565 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | | |
6566 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); | |
6567 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, | |
6568 | (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | | |
6569 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | | |
6570 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); | |
6571 | } | |
6572 | ||
619c5cb6 | 6573 | bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); |
f2e0899f | 6574 | if (!CHIP_IS_E1(bp)) { |
619c5cb6 VZ |
6575 | /* in E3 this done in per-port section */ |
6576 | if (!CHIP_IS_E3(bp)) | |
6577 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
f2e0899f | 6578 | } |
619c5cb6 VZ |
6579 | if (CHIP_IS_E1H(bp)) |
6580 | /* not applicable for E2 (and above ...) */ | |
6581 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); | |
34f80b04 EG |
6582 | |
6583 | if (CHIP_REV_IS_SLOW(bp)) | |
6584 | msleep(200); | |
6585 | ||
6586 | /* finish CFC init */ | |
6587 | val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); | |
6588 | if (val != 1) { | |
6589 | BNX2X_ERR("CFC LL_INIT failed\n"); | |
6590 | return -EBUSY; | |
6591 | } | |
6592 | val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); | |
6593 | if (val != 1) { | |
6594 | BNX2X_ERR("CFC AC_INIT failed\n"); | |
6595 | return -EBUSY; | |
6596 | } | |
6597 | val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); | |
6598 | if (val != 1) { | |
6599 | BNX2X_ERR("CFC CAM_INIT failed\n"); | |
6600 | return -EBUSY; | |
6601 | } | |
6602 | REG_WR(bp, CFC_REG_DEBUG0, 0); | |
f1410647 | 6603 | |
f2e0899f DK |
6604 | if (CHIP_IS_E1(bp)) { |
6605 | /* read NIG statistic | |
6606 | to see if this is our first up since powerup */ | |
6607 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); | |
6608 | val = *bnx2x_sp(bp, wb_data[0]); | |
34f80b04 | 6609 | |
f2e0899f DK |
6610 | /* do internal memory self test */ |
6611 | if ((val == 0) && bnx2x_int_mem_test(bp)) { | |
6612 | BNX2X_ERR("internal mem self test failed\n"); | |
6613 | return -EBUSY; | |
6614 | } | |
34f80b04 EG |
6615 | } |
6616 | ||
fd4ef40d EG |
6617 | bnx2x_setup_fan_failure_detection(bp); |
6618 | ||
34f80b04 EG |
6619 | /* clear PXP2 attentions */ |
6620 | REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); | |
a2fbb9ea | 6621 | |
4a33bc03 | 6622 | bnx2x_enable_blocks_attention(bp); |
c9ee9206 | 6623 | bnx2x_enable_blocks_parity(bp); |
a2fbb9ea | 6624 | |
6bbca910 | 6625 | if (!BP_NOMCP(bp)) { |
619c5cb6 VZ |
6626 | if (CHIP_IS_E1x(bp)) |
6627 | bnx2x__common_init_phy(bp); | |
6bbca910 YR |
6628 | } else |
6629 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); | |
6630 | ||
34f80b04 EG |
6631 | return 0; |
6632 | } | |
a2fbb9ea | 6633 | |
619c5cb6 VZ |
6634 | /** |
6635 | * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. | |
6636 | * | |
6637 | * @bp: driver handle | |
6638 | */ | |
6639 | static int bnx2x_init_hw_common_chip(struct bnx2x *bp) | |
6640 | { | |
6641 | int rc = bnx2x_init_hw_common(bp); | |
6642 | ||
6643 | if (rc) | |
6644 | return rc; | |
6645 | ||
6646 | /* In E2 2-PORT mode, same ext phy is used for the two paths */ | |
6647 | if (!BP_NOMCP(bp)) | |
6648 | bnx2x__common_init_phy(bp); | |
6649 | ||
6650 | return 0; | |
6651 | } | |
6652 | ||
523224a3 | 6653 | static int bnx2x_init_hw_port(struct bnx2x *bp) |
34f80b04 EG |
6654 | { |
6655 | int port = BP_PORT(bp); | |
619c5cb6 | 6656 | int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; |
1c06328c | 6657 | u32 low, high; |
34f80b04 | 6658 | u32 val; |
a2fbb9ea | 6659 | |
619c5cb6 VZ |
6660 | bnx2x__link_reset(bp); |
6661 | ||
51c1a580 | 6662 | DP(NETIF_MSG_HW, "starting port init port %d\n", port); |
34f80b04 EG |
6663 | |
6664 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); | |
a2fbb9ea | 6665 | |
619c5cb6 VZ |
6666 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
6667 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); | |
6668 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
ca00392c | 6669 | |
f2e0899f DK |
6670 | /* Timers bug workaround: disables the pf_master bit in pglue at |
6671 | * common phase, we need to enable it here before any dmae access are | |
6672 | * attempted. Therefore we manually added the enable-master to the | |
6673 | * port phase (it also happens in the function phase) | |
6674 | */ | |
619c5cb6 | 6675 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6676 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
6677 | ||
619c5cb6 VZ |
6678 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
6679 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
6680 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); | |
6681 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
6682 | ||
6683 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
6684 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
6685 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
6686 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
a2fbb9ea | 6687 | |
523224a3 DK |
6688 | /* QM cid (connection) count */ |
6689 | bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); | |
a2fbb9ea | 6690 | |
523224a3 | 6691 | #ifdef BCM_CNIC |
619c5cb6 | 6692 | bnx2x_init_block(bp, BLOCK_TM, init_phase); |
37b091ba MC |
6693 | REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); |
6694 | REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); | |
a2fbb9ea | 6695 | #endif |
cdaa7cb8 | 6696 | |
619c5cb6 | 6697 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
f2e0899f DK |
6698 | |
6699 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { | |
619c5cb6 VZ |
6700 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
6701 | ||
6702 | if (IS_MF(bp)) | |
6703 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | |
6704 | else if (bp->dev->mtu > 4096) { | |
6705 | if (bp->flags & ONE_PORT_FLAG) | |
6706 | low = 160; | |
6707 | else { | |
6708 | val = bp->dev->mtu; | |
6709 | /* (24*1024 + val*4)/256 */ | |
6710 | low = 96 + (val/64) + | |
6711 | ((val % 64) ? 1 : 0); | |
6712 | } | |
6713 | } else | |
6714 | low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); | |
6715 | high = low + 56; /* 14*1024/256 */ | |
f2e0899f DK |
6716 | REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); |
6717 | REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); | |
1c06328c | 6718 | } |
1c06328c | 6719 | |
619c5cb6 VZ |
6720 | if (CHIP_MODE_IS_4_PORT(bp)) |
6721 | REG_WR(bp, (BP_PORT(bp) ? | |
6722 | BRB1_REG_MAC_GUARANTIED_1 : | |
6723 | BRB1_REG_MAC_GUARANTIED_0), 40); | |
1c06328c | 6724 | |
ca00392c | 6725 | |
619c5cb6 | 6726 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
a3348722 BW |
6727 | if (CHIP_IS_E3B0(bp)) { |
6728 | if (IS_MF_AFEX(bp)) { | |
6729 | /* configure headers for AFEX mode */ | |
6730 | REG_WR(bp, BP_PORT(bp) ? | |
6731 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
6732 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); | |
6733 | REG_WR(bp, BP_PORT(bp) ? | |
6734 | PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : | |
6735 | PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); | |
6736 | REG_WR(bp, BP_PORT(bp) ? | |
6737 | PRS_REG_MUST_HAVE_HDRS_PORT_1 : | |
6738 | PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); | |
6739 | } else { | |
6740 | /* Ovlan exists only if we are in multi-function + | |
6741 | * switch-dependent mode, in switch-independent there | |
6742 | * is no ovlan headers | |
6743 | */ | |
6744 | REG_WR(bp, BP_PORT(bp) ? | |
6745 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
6746 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, | |
6747 | (bp->path_has_ovlan ? 7 : 6)); | |
6748 | } | |
6749 | } | |
356e2385 | 6750 | |
619c5cb6 VZ |
6751 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
6752 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
6753 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
6754 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
356e2385 | 6755 | |
619c5cb6 VZ |
6756 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
6757 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
6758 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
6759 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
34f80b04 | 6760 | |
619c5cb6 VZ |
6761 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
6762 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
a2fbb9ea | 6763 | |
619c5cb6 VZ |
6764 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
6765 | ||
6766 | if (CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
6767 | /* configure PBF to work without PAUSE mtu 9000 */ |
6768 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); | |
a2fbb9ea | 6769 | |
f2e0899f DK |
6770 | /* update threshold */ |
6771 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); | |
6772 | /* update init credit */ | |
6773 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); | |
a2fbb9ea | 6774 | |
f2e0899f DK |
6775 | /* probe changes */ |
6776 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); | |
6777 | udelay(50); | |
6778 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); | |
6779 | } | |
a2fbb9ea | 6780 | |
37b091ba | 6781 | #ifdef BCM_CNIC |
619c5cb6 | 6782 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); |
a2fbb9ea | 6783 | #endif |
619c5cb6 VZ |
6784 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
6785 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); | |
34f80b04 EG |
6786 | |
6787 | if (CHIP_IS_E1(bp)) { | |
6788 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
6789 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
6790 | } | |
619c5cb6 | 6791 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
34f80b04 | 6792 | |
619c5cb6 | 6793 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 6794 | |
619c5cb6 | 6795 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
34f80b04 EG |
6796 | /* init aeu_mask_attn_func_0/1: |
6797 | * - SF mode: bits 3-7 are masked. only bits 0-2 are in use | |
6798 | * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF | |
6799 | * bits 4-7 are used for "per vn group attention" */ | |
e4901dde VZ |
6800 | val = IS_MF(bp) ? 0xF7 : 0x7; |
6801 | /* Enable DCBX attention for all but E1 */ | |
6802 | val |= CHIP_IS_E1(bp) ? 0 : 0x10; | |
6803 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); | |
34f80b04 | 6804 | |
619c5cb6 VZ |
6805 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
6806 | ||
6807 | if (!CHIP_IS_E1x(bp)) { | |
6808 | /* Bit-map indicating which L2 hdrs may appear after the | |
6809 | * basic Ethernet header | |
6810 | */ | |
a3348722 BW |
6811 | if (IS_MF_AFEX(bp)) |
6812 | REG_WR(bp, BP_PORT(bp) ? | |
6813 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
6814 | NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); | |
6815 | else | |
6816 | REG_WR(bp, BP_PORT(bp) ? | |
6817 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
6818 | NIG_REG_P0_HDRS_AFTER_BASIC, | |
6819 | IS_MF_SD(bp) ? 7 : 6); | |
619c5cb6 VZ |
6820 | |
6821 | if (CHIP_IS_E3(bp)) | |
6822 | REG_WR(bp, BP_PORT(bp) ? | |
6823 | NIG_REG_LLH1_MF_MODE : | |
6824 | NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
6825 | } | |
6826 | if (!CHIP_IS_E3(bp)) | |
6827 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); | |
34f80b04 | 6828 | |
f2e0899f | 6829 | if (!CHIP_IS_E1(bp)) { |
fb3bff17 | 6830 | /* 0x2 disable mf_ov, 0x1 enable */ |
34f80b04 | 6831 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
0793f83f | 6832 | (IS_MF_SD(bp) ? 0x1 : 0x2)); |
34f80b04 | 6833 | |
619c5cb6 | 6834 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6835 | val = 0; |
6836 | switch (bp->mf_mode) { | |
6837 | case MULTI_FUNCTION_SD: | |
6838 | val = 1; | |
6839 | break; | |
6840 | case MULTI_FUNCTION_SI: | |
a3348722 | 6841 | case MULTI_FUNCTION_AFEX: |
f2e0899f DK |
6842 | val = 2; |
6843 | break; | |
6844 | } | |
6845 | ||
6846 | REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : | |
6847 | NIG_REG_LLH0_CLS_TYPE), val); | |
6848 | } | |
1c06328c EG |
6849 | { |
6850 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); | |
6851 | REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); | |
6852 | REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); | |
6853 | } | |
34f80b04 EG |
6854 | } |
6855 | ||
619c5cb6 VZ |
6856 | |
6857 | /* If SPIO5 is set to generate interrupts, enable it for this port */ | |
6858 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
6859 | if (val & (1 << MISC_REGISTERS_SPIO_5)) { | |
4d295db0 EG |
6860 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
6861 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
6862 | val = REG_RD(bp, reg_addr); | |
f1410647 | 6863 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
4d295db0 | 6864 | REG_WR(bp, reg_addr, val); |
f1410647 | 6865 | } |
a2fbb9ea | 6866 | |
34f80b04 EG |
6867 | return 0; |
6868 | } | |
6869 | ||
34f80b04 EG |
6870 | static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) |
6871 | { | |
6872 | int reg; | |
32d68de1 | 6873 | u32 wb_write[2]; |
34f80b04 | 6874 | |
f2e0899f | 6875 | if (CHIP_IS_E1(bp)) |
34f80b04 | 6876 | reg = PXP2_REG_RQ_ONCHIP_AT + index*8; |
f2e0899f DK |
6877 | else |
6878 | reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; | |
34f80b04 | 6879 | |
32d68de1 YM |
6880 | wb_write[0] = ONCHIP_ADDR1(addr); |
6881 | wb_write[1] = ONCHIP_ADDR2(addr); | |
6882 | REG_WR_DMAE(bp, reg, wb_write, 2); | |
34f80b04 EG |
6883 | } |
6884 | ||
f2e0899f DK |
6885 | static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) |
6886 | { | |
619c5cb6 | 6887 | bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); |
f2e0899f DK |
6888 | } |
6889 | ||
6890 | static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) | |
6891 | { | |
6892 | u32 i, base = FUNC_ILT_BASE(func); | |
6893 | for (i = base; i < base + ILT_PER_FUNC; i++) | |
6894 | bnx2x_ilt_wr(bp, i, 0); | |
6895 | } | |
6896 | ||
523224a3 | 6897 | static int bnx2x_init_hw_func(struct bnx2x *bp) |
34f80b04 EG |
6898 | { |
6899 | int port = BP_PORT(bp); | |
6900 | int func = BP_FUNC(bp); | |
619c5cb6 | 6901 | int init_phase = PHASE_PF0 + func; |
523224a3 DK |
6902 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
6903 | u16 cdu_ilt_start; | |
8badd27a | 6904 | u32 addr, val; |
f4a66897 | 6905 | u32 main_mem_base, main_mem_size, main_mem_prty_clr; |
89db4ad8 | 6906 | int i, main_mem_width, rc; |
34f80b04 | 6907 | |
51c1a580 | 6908 | DP(NETIF_MSG_HW, "starting func init func %d\n", func); |
34f80b04 | 6909 | |
619c5cb6 | 6910 | /* FLR cleanup - hmmm */ |
89db4ad8 AE |
6911 | if (!CHIP_IS_E1x(bp)) { |
6912 | rc = bnx2x_pf_flr_clnup(bp); | |
6913 | if (rc) | |
6914 | return rc; | |
6915 | } | |
619c5cb6 | 6916 | |
8badd27a | 6917 | /* set MSI reconfigure capability */ |
f2e0899f DK |
6918 | if (bp->common.int_block == INT_BLOCK_HC) { |
6919 | addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); | |
6920 | val = REG_RD(bp, addr); | |
6921 | val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; | |
6922 | REG_WR(bp, addr, val); | |
6923 | } | |
8badd27a | 6924 | |
619c5cb6 VZ |
6925 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
6926 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
6927 | ||
523224a3 DK |
6928 | ilt = BP_ILT(bp); |
6929 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
37b091ba | 6930 | |
523224a3 DK |
6931 | for (i = 0; i < L2_ILT_LINES(bp); i++) { |
6932 | ilt->lines[cdu_ilt_start + i].page = | |
6933 | bp->context.vcxt + (ILT_PAGE_CIDS * i); | |
6934 | ilt->lines[cdu_ilt_start + i].page_mapping = | |
6935 | bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); | |
6936 | /* cdu ilt pages are allocated manually so there's no need to | |
6937 | set the size */ | |
37b091ba | 6938 | } |
523224a3 | 6939 | bnx2x_ilt_init_op(bp, INITOP_SET); |
f85582f8 | 6940 | |
523224a3 DK |
6941 | #ifdef BCM_CNIC |
6942 | bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); | |
37b091ba | 6943 | |
523224a3 DK |
6944 | /* T1 hash bits value determines the T1 number of entries */ |
6945 | REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); | |
6946 | #endif | |
37b091ba | 6947 | |
523224a3 DK |
6948 | #ifndef BCM_CNIC |
6949 | /* set NIC mode */ | |
6950 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
6951 | #endif /* BCM_CNIC */ | |
37b091ba | 6952 | |
619c5cb6 | 6953 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6954 | u32 pf_conf = IGU_PF_CONF_FUNC_EN; |
6955 | ||
6956 | /* Turn on a single ISR mode in IGU if driver is going to use | |
6957 | * INT#x or MSI | |
6958 | */ | |
6959 | if (!(bp->flags & USING_MSIX_FLAG)) | |
6960 | pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; | |
6961 | /* | |
6962 | * Timers workaround bug: function init part. | |
6963 | * Need to wait 20msec after initializing ILT, | |
6964 | * needed to make sure there are no requests in | |
6965 | * one of the PXP internal queues with "old" ILT addresses | |
6966 | */ | |
6967 | msleep(20); | |
6968 | /* | |
6969 | * Master enable - Due to WB DMAE writes performed before this | |
6970 | * register is re-initialized as part of the regular function | |
6971 | * init | |
6972 | */ | |
6973 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
6974 | /* Enable the function in IGU */ | |
6975 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); | |
6976 | } | |
6977 | ||
523224a3 | 6978 | bp->dmae_ready = 1; |
34f80b04 | 6979 | |
619c5cb6 | 6980 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
523224a3 | 6981 | |
619c5cb6 | 6982 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6983 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); |
6984 | ||
619c5cb6 VZ |
6985 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
6986 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
6987 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); | |
6988 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
6989 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); | |
6990 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
6991 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
6992 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
6993 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
6994 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); | |
6995 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
6996 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
6997 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
6998 | ||
6999 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
7000 | REG_WR(bp, QM_REG_PF_EN, 1); |
7001 | ||
619c5cb6 VZ |
7002 | if (!CHIP_IS_E1x(bp)) { |
7003 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7004 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7005 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7006 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7007 | } | |
7008 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
7009 | ||
7010 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
7011 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); | |
7012 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); | |
7013 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); | |
7014 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); | |
7015 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
7016 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
7017 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
7018 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); | |
7019 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
7020 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); | |
7021 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
7022 | REG_WR(bp, PBF_REG_DISABLE_PF, 0); |
7023 | ||
619c5cb6 | 7024 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
523224a3 | 7025 | |
619c5cb6 | 7026 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
34f80b04 | 7027 | |
619c5cb6 | 7028 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7029 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); |
7030 | ||
fb3bff17 | 7031 | if (IS_MF(bp)) { |
34f80b04 | 7032 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); |
fb3bff17 | 7033 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); |
34f80b04 EG |
7034 | } |
7035 | ||
619c5cb6 | 7036 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
523224a3 | 7037 | |
34f80b04 | 7038 | /* HC init per function */ |
f2e0899f DK |
7039 | if (bp->common.int_block == INT_BLOCK_HC) { |
7040 | if (CHIP_IS_E1H(bp)) { | |
7041 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
7042 | ||
7043 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7044 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7045 | } | |
619c5cb6 | 7046 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
f2e0899f DK |
7047 | |
7048 | } else { | |
7049 | int num_segs, sb_idx, prod_offset; | |
7050 | ||
34f80b04 EG |
7051 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
7052 | ||
619c5cb6 | 7053 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7054 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
7055 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
7056 | } | |
7057 | ||
619c5cb6 | 7058 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 7059 | |
619c5cb6 | 7060 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7061 | int dsb_idx = 0; |
7062 | /** | |
7063 | * Producer memory: | |
7064 | * E2 mode: address 0-135 match to the mapping memory; | |
7065 | * 136 - PF0 default prod; 137 - PF1 default prod; | |
7066 | * 138 - PF2 default prod; 139 - PF3 default prod; | |
7067 | * 140 - PF0 attn prod; 141 - PF1 attn prod; | |
7068 | * 142 - PF2 attn prod; 143 - PF3 attn prod; | |
7069 | * 144-147 reserved. | |
7070 | * | |
7071 | * E1.5 mode - In backward compatible mode; | |
7072 | * for non default SB; each even line in the memory | |
7073 | * holds the U producer and each odd line hold | |
7074 | * the C producer. The first 128 producers are for | |
7075 | * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 | |
7076 | * producers are for the DSB for each PF. | |
7077 | * Each PF has five segments: (the order inside each | |
7078 | * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; | |
7079 | * 132-135 C prods; 136-139 X prods; 140-143 T prods; | |
7080 | * 144-147 attn prods; | |
7081 | */ | |
7082 | /* non-default-status-blocks */ | |
7083 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
7084 | IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; | |
7085 | for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { | |
7086 | prod_offset = (bp->igu_base_sb + sb_idx) * | |
7087 | num_segs; | |
7088 | ||
7089 | for (i = 0; i < num_segs; i++) { | |
7090 | addr = IGU_REG_PROD_CONS_MEMORY + | |
7091 | (prod_offset + i) * 4; | |
7092 | REG_WR(bp, addr, 0); | |
7093 | } | |
7094 | /* send consumer update with value 0 */ | |
7095 | bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, | |
7096 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7097 | bnx2x_igu_clear_sb(bp, | |
7098 | bp->igu_base_sb + sb_idx); | |
7099 | } | |
7100 | ||
7101 | /* default-status-blocks */ | |
7102 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
7103 | IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; | |
7104 | ||
7105 | if (CHIP_MODE_IS_4_PORT(bp)) | |
7106 | dsb_idx = BP_FUNC(bp); | |
7107 | else | |
3395a033 | 7108 | dsb_idx = BP_VN(bp); |
f2e0899f DK |
7109 | |
7110 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? | |
7111 | IGU_BC_BASE_DSB_PROD + dsb_idx : | |
7112 | IGU_NORM_BASE_DSB_PROD + dsb_idx); | |
7113 | ||
3395a033 DK |
7114 | /* |
7115 | * igu prods come in chunks of E1HVN_MAX (4) - | |
7116 | * does not matters what is the current chip mode | |
7117 | */ | |
f2e0899f DK |
7118 | for (i = 0; i < (num_segs * E1HVN_MAX); |
7119 | i += E1HVN_MAX) { | |
7120 | addr = IGU_REG_PROD_CONS_MEMORY + | |
7121 | (prod_offset + i)*4; | |
7122 | REG_WR(bp, addr, 0); | |
7123 | } | |
7124 | /* send consumer update with 0 */ | |
7125 | if (CHIP_INT_MODE_IS_BC(bp)) { | |
7126 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7127 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7128 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7129 | CSTORM_ID, 0, IGU_INT_NOP, 1); | |
7130 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7131 | XSTORM_ID, 0, IGU_INT_NOP, 1); | |
7132 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7133 | TSTORM_ID, 0, IGU_INT_NOP, 1); | |
7134 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7135 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
7136 | } else { | |
7137 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7138 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7139 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7140 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
7141 | } | |
7142 | bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); | |
7143 | ||
7144 | /* !!! these should become driver const once | |
7145 | rf-tool supports split-68 const */ | |
7146 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); | |
7147 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); | |
7148 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); | |
7149 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); | |
7150 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); | |
7151 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); | |
7152 | } | |
34f80b04 | 7153 | } |
34f80b04 | 7154 | |
c14423fe | 7155 | /* Reset PCIE errors for debug */ |
a2fbb9ea ET |
7156 | REG_WR(bp, 0x2114, 0xffffffff); |
7157 | REG_WR(bp, 0x2120, 0xffffffff); | |
523224a3 | 7158 | |
f4a66897 VZ |
7159 | if (CHIP_IS_E1x(bp)) { |
7160 | main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ | |
7161 | main_mem_base = HC_REG_MAIN_MEMORY + | |
7162 | BP_PORT(bp) * (main_mem_size * 4); | |
7163 | main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; | |
7164 | main_mem_width = 8; | |
7165 | ||
7166 | val = REG_RD(bp, main_mem_prty_clr); | |
7167 | if (val) | |
51c1a580 MS |
7168 | DP(NETIF_MSG_HW, |
7169 | "Hmmm... Parity errors in HC block during function init (0x%x)!\n", | |
7170 | val); | |
f4a66897 VZ |
7171 | |
7172 | /* Clear "false" parity errors in MSI-X table */ | |
7173 | for (i = main_mem_base; | |
7174 | i < main_mem_base + main_mem_size * 4; | |
7175 | i += main_mem_width) { | |
7176 | bnx2x_read_dmae(bp, i, main_mem_width / 4); | |
7177 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), | |
7178 | i, main_mem_width / 4); | |
7179 | } | |
7180 | /* Clear HC parity attention */ | |
7181 | REG_RD(bp, main_mem_prty_clr); | |
7182 | } | |
7183 | ||
619c5cb6 VZ |
7184 | #ifdef BNX2X_STOP_ON_ERROR |
7185 | /* Enable STORMs SP logging */ | |
7186 | REG_WR8(bp, BAR_USTRORM_INTMEM + | |
7187 | USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7188 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
7189 | TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7190 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
7191 | CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7192 | REG_WR8(bp, BAR_XSTRORM_INTMEM + | |
7193 | XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7194 | #endif | |
7195 | ||
b7737c9b | 7196 | bnx2x_phy_probe(&bp->link_params); |
f85582f8 | 7197 | |
34f80b04 EG |
7198 | return 0; |
7199 | } | |
7200 | ||
a2fbb9ea | 7201 | |
9f6c9258 | 7202 | void bnx2x_free_mem(struct bnx2x *bp) |
a2fbb9ea | 7203 | { |
a2fbb9ea | 7204 | /* fastpath */ |
b3b83c3f | 7205 | bnx2x_free_fp_mem(bp); |
a2fbb9ea ET |
7206 | /* end of fastpath */ |
7207 | ||
7208 | BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, | |
523224a3 | 7209 | sizeof(struct host_sp_status_block)); |
a2fbb9ea | 7210 | |
619c5cb6 VZ |
7211 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, |
7212 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
7213 | ||
a2fbb9ea | 7214 | BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, |
34f80b04 | 7215 | sizeof(struct bnx2x_slowpath)); |
a2fbb9ea | 7216 | |
523224a3 DK |
7217 | BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, |
7218 | bp->context.size); | |
7219 | ||
7220 | bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); | |
7221 | ||
7222 | BNX2X_FREE(bp->ilt->lines); | |
f85582f8 | 7223 | |
37b091ba | 7224 | #ifdef BCM_CNIC |
619c5cb6 | 7225 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7226 | BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, |
7227 | sizeof(struct host_hc_status_block_e2)); | |
7228 | else | |
7229 | BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, | |
7230 | sizeof(struct host_hc_status_block_e1x)); | |
f85582f8 | 7231 | |
523224a3 | 7232 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); |
a2fbb9ea | 7233 | #endif |
f85582f8 | 7234 | |
7a9b2557 | 7235 | BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); |
a2fbb9ea | 7236 | |
523224a3 DK |
7237 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
7238 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
619c5cb6 VZ |
7239 | } |
7240 | ||
7241 | static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) | |
7242 | { | |
7243 | int num_groups; | |
50f0a562 | 7244 | int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1; |
619c5cb6 | 7245 | |
50f0a562 BW |
7246 | /* number of queues for statistics is number of eth queues + FCoE */ |
7247 | u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats; | |
619c5cb6 VZ |
7248 | |
7249 | /* Total number of FW statistics requests = | |
50f0a562 BW |
7250 | * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats + |
7251 | * num of queues | |
7252 | */ | |
7253 | bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats; | |
523224a3 | 7254 | |
619c5cb6 VZ |
7255 | |
7256 | /* Request is built from stats_query_header and an array of | |
7257 | * stats_query_cmd_group each of which contains | |
7258 | * STATS_QUERY_CMD_COUNT rules. The real number or requests is | |
7259 | * configured in the stats_query_header. | |
7260 | */ | |
50f0a562 BW |
7261 | num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) + |
7262 | (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0); | |
619c5cb6 VZ |
7263 | |
7264 | bp->fw_stats_req_sz = sizeof(struct stats_query_header) + | |
7265 | num_groups * sizeof(struct stats_query_cmd_group); | |
7266 | ||
7267 | /* Data for statistics requests + stats_conter | |
7268 | * | |
7269 | * stats_counter holds per-STORM counters that are incremented | |
7270 | * when STORM has finished with the current request. | |
50f0a562 BW |
7271 | * |
7272 | * memory for FCoE offloaded statistics are counted anyway, | |
7273 | * even if they will not be sent. | |
619c5cb6 VZ |
7274 | */ |
7275 | bp->fw_stats_data_sz = sizeof(struct per_port_stats) + | |
7276 | sizeof(struct per_pf_stats) + | |
50f0a562 | 7277 | sizeof(struct fcoe_statistics_params) + |
619c5cb6 VZ |
7278 | sizeof(struct per_queue_stats) * num_queue_stats + |
7279 | sizeof(struct stats_counter); | |
7280 | ||
7281 | BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, | |
7282 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
7283 | ||
7284 | /* Set shortcuts */ | |
7285 | bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; | |
7286 | bp->fw_stats_req_mapping = bp->fw_stats_mapping; | |
7287 | ||
7288 | bp->fw_stats_data = (struct bnx2x_fw_stats_data *) | |
7289 | ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); | |
7290 | ||
7291 | bp->fw_stats_data_mapping = bp->fw_stats_mapping + | |
7292 | bp->fw_stats_req_sz; | |
7293 | return 0; | |
7294 | ||
7295 | alloc_mem_err: | |
7296 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, | |
7297 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
51c1a580 | 7298 | BNX2X_ERR("Can't allocate memory\n"); |
619c5cb6 | 7299 | return -ENOMEM; |
a2fbb9ea ET |
7300 | } |
7301 | ||
f2e0899f | 7302 | |
9f6c9258 | 7303 | int bnx2x_alloc_mem(struct bnx2x *bp) |
a2fbb9ea | 7304 | { |
523224a3 | 7305 | #ifdef BCM_CNIC |
619c5cb6 VZ |
7306 | if (!CHIP_IS_E1x(bp)) |
7307 | /* size = the status block + ramrod buffers */ | |
f2e0899f DK |
7308 | BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, |
7309 | sizeof(struct host_hc_status_block_e2)); | |
7310 | else | |
7311 | BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, | |
7312 | sizeof(struct host_hc_status_block_e1x)); | |
8badd27a | 7313 | |
523224a3 DK |
7314 | /* allocate searcher T2 table */ |
7315 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); | |
7316 | #endif | |
a2fbb9ea | 7317 | |
8badd27a | 7318 | |
523224a3 DK |
7319 | BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, |
7320 | sizeof(struct host_sp_status_block)); | |
a2fbb9ea | 7321 | |
523224a3 DK |
7322 | BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, |
7323 | sizeof(struct bnx2x_slowpath)); | |
a2fbb9ea | 7324 | |
82fa848c MY |
7325 | #ifdef BCM_CNIC |
7326 | /* write address to which L5 should insert its values */ | |
7327 | bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp; | |
7328 | #endif | |
7329 | ||
619c5cb6 VZ |
7330 | /* Allocated memory for FW statistics */ |
7331 | if (bnx2x_alloc_fw_stats_mem(bp)) | |
7332 | goto alloc_mem_err; | |
7333 | ||
6383c0b3 | 7334 | bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); |
f85582f8 | 7335 | |
523224a3 DK |
7336 | BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, |
7337 | bp->context.size); | |
65abd74d | 7338 | |
523224a3 | 7339 | BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); |
65abd74d | 7340 | |
523224a3 DK |
7341 | if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) |
7342 | goto alloc_mem_err; | |
65abd74d | 7343 | |
9f6c9258 DK |
7344 | /* Slow path ring */ |
7345 | BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); | |
65abd74d | 7346 | |
523224a3 DK |
7347 | /* EQ */ |
7348 | BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, | |
7349 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
ab532cf3 | 7350 | |
b3b83c3f DK |
7351 | |
7352 | /* fastpath */ | |
7353 | /* need to be done at the end, since it's self adjusting to amount | |
7354 | * of memory available for RSS queues | |
7355 | */ | |
7356 | if (bnx2x_alloc_fp_mem(bp)) | |
7357 | goto alloc_mem_err; | |
9f6c9258 | 7358 | return 0; |
e1510706 | 7359 | |
9f6c9258 DK |
7360 | alloc_mem_err: |
7361 | bnx2x_free_mem(bp); | |
51c1a580 | 7362 | BNX2X_ERR("Can't allocate memory\n"); |
9f6c9258 | 7363 | return -ENOMEM; |
65abd74d YG |
7364 | } |
7365 | ||
a2fbb9ea ET |
7366 | /* |
7367 | * Init service functions | |
7368 | */ | |
a2fbb9ea | 7369 | |
619c5cb6 VZ |
7370 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, |
7371 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
7372 | int mac_type, unsigned long *ramrod_flags) | |
a2fbb9ea | 7373 | { |
619c5cb6 VZ |
7374 | int rc; |
7375 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
a2fbb9ea | 7376 | |
619c5cb6 | 7377 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
a2fbb9ea | 7378 | |
619c5cb6 VZ |
7379 | /* Fill general parameters */ |
7380 | ramrod_param.vlan_mac_obj = obj; | |
7381 | ramrod_param.ramrod_flags = *ramrod_flags; | |
a2fbb9ea | 7382 | |
619c5cb6 VZ |
7383 | /* Fill a user request section if needed */ |
7384 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
7385 | memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); | |
a2fbb9ea | 7386 | |
619c5cb6 | 7387 | __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); |
e3553b29 | 7388 | |
619c5cb6 VZ |
7389 | /* Set the command: ADD or DEL */ |
7390 | if (set) | |
7391 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
7392 | else | |
7393 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
a2fbb9ea ET |
7394 | } |
7395 | ||
619c5cb6 VZ |
7396 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
7397 | if (rc < 0) | |
7398 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); | |
7399 | return rc; | |
a2fbb9ea ET |
7400 | } |
7401 | ||
619c5cb6 VZ |
7402 | int bnx2x_del_all_macs(struct bnx2x *bp, |
7403 | struct bnx2x_vlan_mac_obj *mac_obj, | |
7404 | int mac_type, bool wait_for_comp) | |
e665bfda | 7405 | { |
619c5cb6 VZ |
7406 | int rc; |
7407 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | |
0793f83f | 7408 | |
619c5cb6 VZ |
7409 | /* Wait for completion of requested */ |
7410 | if (wait_for_comp) | |
7411 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
0793f83f | 7412 | |
619c5cb6 VZ |
7413 | /* Set the mac type of addresses we want to clear */ |
7414 | __set_bit(mac_type, &vlan_mac_flags); | |
0793f83f | 7415 | |
619c5cb6 VZ |
7416 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); |
7417 | if (rc < 0) | |
7418 | BNX2X_ERR("Failed to delete MACs: %d\n", rc); | |
0793f83f | 7419 | |
619c5cb6 | 7420 | return rc; |
0793f83f DK |
7421 | } |
7422 | ||
619c5cb6 | 7423 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
523224a3 | 7424 | { |
619c5cb6 | 7425 | unsigned long ramrod_flags = 0; |
e665bfda | 7426 | |
614c76df | 7427 | #ifdef BCM_CNIC |
a3348722 BW |
7428 | if (is_zero_ether_addr(bp->dev->dev_addr) && |
7429 | (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) { | |
51c1a580 MS |
7430 | DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN, |
7431 | "Ignoring Zero MAC for STORAGE SD mode\n"); | |
614c76df DK |
7432 | return 0; |
7433 | } | |
7434 | #endif | |
7435 | ||
619c5cb6 | 7436 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
0793f83f | 7437 | |
619c5cb6 VZ |
7438 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); |
7439 | /* Eth MAC is set on RSS leading client (fp[0]) */ | |
7440 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, | |
7441 | BNX2X_ETH_MAC, &ramrod_flags); | |
e665bfda | 7442 | } |
6e30dd4e | 7443 | |
619c5cb6 | 7444 | int bnx2x_setup_leading(struct bnx2x *bp) |
ec6ba945 | 7445 | { |
619c5cb6 | 7446 | return bnx2x_setup_queue(bp, &bp->fp[0], 1); |
993ac7b5 | 7447 | } |
a2fbb9ea | 7448 | |
d6214d7a | 7449 | /** |
e8920674 | 7450 | * bnx2x_set_int_mode - configure interrupt mode |
d6214d7a | 7451 | * |
e8920674 | 7452 | * @bp: driver handle |
d6214d7a | 7453 | * |
e8920674 | 7454 | * In case of MSI-X it will also try to enable MSI-X. |
d6214d7a | 7455 | */ |
9ee3d37b | 7456 | static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) |
ca00392c | 7457 | { |
9ee3d37b | 7458 | switch (int_mode) { |
d6214d7a DK |
7459 | case INT_MODE_MSI: |
7460 | bnx2x_enable_msi(bp); | |
7461 | /* falling through... */ | |
7462 | case INT_MODE_INTx: | |
6383c0b3 | 7463 | bp->num_queues = 1 + NON_ETH_CONTEXT_USE; |
51c1a580 | 7464 | BNX2X_DEV_INFO("set number of queues to 1\n"); |
ca00392c | 7465 | break; |
d6214d7a | 7466 | default: |
30a5de77 | 7467 | /* Set number of queues for MSI-X mode */ |
d6214d7a | 7468 | bnx2x_set_num_queues(bp); |
ca00392c | 7469 | |
51c1a580 | 7470 | BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); |
ca00392c | 7471 | |
d6214d7a DK |
7472 | /* if we can't use MSI-X we only need one fp, |
7473 | * so try to enable MSI-X with the requested number of fp's | |
7474 | * and fallback to MSI or legacy INTx with one fp | |
7475 | */ | |
30a5de77 DK |
7476 | if (bnx2x_enable_msix(bp) || |
7477 | bp->flags & USING_SINGLE_MSIX_FLAG) { | |
7478 | /* failed to enable multiple MSI-X */ | |
7479 | BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", | |
51c1a580 MS |
7480 | bp->num_queues, 1 + NON_ETH_CONTEXT_USE); |
7481 | ||
6383c0b3 | 7482 | bp->num_queues = 1 + NON_ETH_CONTEXT_USE; |
d6214d7a | 7483 | |
9ee3d37b | 7484 | /* Try to enable MSI */ |
30a5de77 DK |
7485 | if (!(bp->flags & USING_SINGLE_MSIX_FLAG) && |
7486 | !(bp->flags & DISABLE_MSI_FLAG)) | |
d6214d7a DK |
7487 | bnx2x_enable_msi(bp); |
7488 | } | |
9f6c9258 DK |
7489 | break; |
7490 | } | |
a2fbb9ea ET |
7491 | } |
7492 | ||
c2bff63f DK |
7493 | /* must be called prioir to any HW initializations */ |
7494 | static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) | |
7495 | { | |
7496 | return L2_ILT_LINES(bp); | |
7497 | } | |
7498 | ||
523224a3 DK |
7499 | void bnx2x_ilt_set_info(struct bnx2x *bp) |
7500 | { | |
7501 | struct ilt_client_info *ilt_client; | |
7502 | struct bnx2x_ilt *ilt = BP_ILT(bp); | |
7503 | u16 line = 0; | |
7504 | ||
7505 | ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); | |
7506 | DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); | |
7507 | ||
7508 | /* CDU */ | |
7509 | ilt_client = &ilt->clients[ILT_CLIENT_CDU]; | |
7510 | ilt_client->client_num = ILT_CLIENT_CDU; | |
7511 | ilt_client->page_size = CDU_ILT_PAGE_SZ; | |
7512 | ilt_client->flags = ILT_CLIENT_SKIP_MEM; | |
7513 | ilt_client->start = line; | |
619c5cb6 | 7514 | line += bnx2x_cid_ilt_lines(bp); |
523224a3 DK |
7515 | #ifdef BCM_CNIC |
7516 | line += CNIC_ILT_LINES; | |
7517 | #endif | |
7518 | ilt_client->end = line - 1; | |
7519 | ||
51c1a580 | 7520 | DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", |
523224a3 DK |
7521 | ilt_client->start, |
7522 | ilt_client->end, | |
7523 | ilt_client->page_size, | |
7524 | ilt_client->flags, | |
7525 | ilog2(ilt_client->page_size >> 12)); | |
7526 | ||
7527 | /* QM */ | |
7528 | if (QM_INIT(bp->qm_cid_count)) { | |
7529 | ilt_client = &ilt->clients[ILT_CLIENT_QM]; | |
7530 | ilt_client->client_num = ILT_CLIENT_QM; | |
7531 | ilt_client->page_size = QM_ILT_PAGE_SZ; | |
7532 | ilt_client->flags = 0; | |
7533 | ilt_client->start = line; | |
7534 | ||
7535 | /* 4 bytes for each cid */ | |
7536 | line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, | |
7537 | QM_ILT_PAGE_SZ); | |
7538 | ||
7539 | ilt_client->end = line - 1; | |
7540 | ||
51c1a580 MS |
7541 | DP(NETIF_MSG_IFUP, |
7542 | "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
7543 | ilt_client->start, |
7544 | ilt_client->end, | |
7545 | ilt_client->page_size, | |
7546 | ilt_client->flags, | |
7547 | ilog2(ilt_client->page_size >> 12)); | |
7548 | ||
7549 | } | |
7550 | /* SRC */ | |
7551 | ilt_client = &ilt->clients[ILT_CLIENT_SRC]; | |
7552 | #ifdef BCM_CNIC | |
7553 | ilt_client->client_num = ILT_CLIENT_SRC; | |
7554 | ilt_client->page_size = SRC_ILT_PAGE_SZ; | |
7555 | ilt_client->flags = 0; | |
7556 | ilt_client->start = line; | |
7557 | line += SRC_ILT_LINES; | |
7558 | ilt_client->end = line - 1; | |
7559 | ||
51c1a580 MS |
7560 | DP(NETIF_MSG_IFUP, |
7561 | "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
7562 | ilt_client->start, |
7563 | ilt_client->end, | |
7564 | ilt_client->page_size, | |
7565 | ilt_client->flags, | |
7566 | ilog2(ilt_client->page_size >> 12)); | |
7567 | ||
7568 | #else | |
7569 | ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); | |
7570 | #endif | |
9f6c9258 | 7571 | |
523224a3 DK |
7572 | /* TM */ |
7573 | ilt_client = &ilt->clients[ILT_CLIENT_TM]; | |
7574 | #ifdef BCM_CNIC | |
7575 | ilt_client->client_num = ILT_CLIENT_TM; | |
7576 | ilt_client->page_size = TM_ILT_PAGE_SZ; | |
7577 | ilt_client->flags = 0; | |
7578 | ilt_client->start = line; | |
7579 | line += TM_ILT_LINES; | |
7580 | ilt_client->end = line - 1; | |
7581 | ||
51c1a580 MS |
7582 | DP(NETIF_MSG_IFUP, |
7583 | "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
7584 | ilt_client->start, |
7585 | ilt_client->end, | |
7586 | ilt_client->page_size, | |
7587 | ilt_client->flags, | |
7588 | ilog2(ilt_client->page_size >> 12)); | |
9f6c9258 | 7589 | |
523224a3 DK |
7590 | #else |
7591 | ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); | |
7592 | #endif | |
619c5cb6 | 7593 | BUG_ON(line > ILT_MAX_LINES); |
523224a3 | 7594 | } |
f85582f8 | 7595 | |
619c5cb6 VZ |
7596 | /** |
7597 | * bnx2x_pf_q_prep_init - prepare INIT transition parameters | |
7598 | * | |
7599 | * @bp: driver handle | |
7600 | * @fp: pointer to fastpath | |
7601 | * @init_params: pointer to parameters structure | |
7602 | * | |
7603 | * parameters configured: | |
7604 | * - HC configuration | |
7605 | * - Queue's CDU context | |
7606 | */ | |
7607 | static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, | |
7608 | struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) | |
a2fbb9ea | 7609 | { |
6383c0b3 AE |
7610 | |
7611 | u8 cos; | |
619c5cb6 VZ |
7612 | /* FCoE Queue uses Default SB, thus has no HC capabilities */ |
7613 | if (!IS_FCOE_FP(fp)) { | |
7614 | __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); | |
7615 | __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); | |
7616 | ||
7617 | /* If HC is supporterd, enable host coalescing in the transition | |
7618 | * to INIT state. | |
7619 | */ | |
7620 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); | |
7621 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); | |
7622 | ||
7623 | /* HC rate */ | |
7624 | init_params->rx.hc_rate = bp->rx_ticks ? | |
7625 | (1000000 / bp->rx_ticks) : 0; | |
7626 | init_params->tx.hc_rate = bp->tx_ticks ? | |
7627 | (1000000 / bp->tx_ticks) : 0; | |
7628 | ||
7629 | /* FW SB ID */ | |
7630 | init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = | |
7631 | fp->fw_sb_id; | |
7632 | ||
7633 | /* | |
7634 | * CQ index among the SB indices: FCoE clients uses the default | |
7635 | * SB, therefore it's different. | |
7636 | */ | |
6383c0b3 AE |
7637 | init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
7638 | init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; | |
619c5cb6 VZ |
7639 | } |
7640 | ||
6383c0b3 AE |
7641 | /* set maximum number of COSs supported by this queue */ |
7642 | init_params->max_cos = fp->max_cos; | |
7643 | ||
51c1a580 | 7644 | DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", |
6383c0b3 AE |
7645 | fp->index, init_params->max_cos); |
7646 | ||
7647 | /* set the context pointers queue object */ | |
7648 | for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) | |
7649 | init_params->cxts[cos] = | |
7650 | &bp->context.vcxt[fp->txdata[cos].cid].eth; | |
619c5cb6 VZ |
7651 | } |
7652 | ||
6383c0b3 AE |
7653 | int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
7654 | struct bnx2x_queue_state_params *q_params, | |
7655 | struct bnx2x_queue_setup_tx_only_params *tx_only_params, | |
7656 | int tx_index, bool leading) | |
7657 | { | |
7658 | memset(tx_only_params, 0, sizeof(*tx_only_params)); | |
7659 | ||
7660 | /* Set the command */ | |
7661 | q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
7662 | ||
7663 | /* Set tx-only QUEUE flags: don't zero statistics */ | |
7664 | tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); | |
7665 | ||
7666 | /* choose the index of the cid to send the slow path on */ | |
7667 | tx_only_params->cid_index = tx_index; | |
7668 | ||
7669 | /* Set general TX_ONLY_SETUP parameters */ | |
7670 | bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); | |
7671 | ||
7672 | /* Set Tx TX_ONLY_SETUP parameters */ | |
7673 | bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); | |
7674 | ||
51c1a580 MS |
7675 | DP(NETIF_MSG_IFUP, |
7676 | "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", | |
6383c0b3 AE |
7677 | tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], |
7678 | q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, | |
7679 | tx_only_params->gen_params.spcl_id, tx_only_params->flags); | |
7680 | ||
7681 | /* send the ramrod */ | |
7682 | return bnx2x_queue_state_change(bp, q_params); | |
7683 | } | |
7684 | ||
7685 | ||
619c5cb6 VZ |
7686 | /** |
7687 | * bnx2x_setup_queue - setup queue | |
7688 | * | |
7689 | * @bp: driver handle | |
7690 | * @fp: pointer to fastpath | |
7691 | * @leading: is leading | |
7692 | * | |
7693 | * This function performs 2 steps in a Queue state machine | |
7694 | * actually: 1) RESET->INIT 2) INIT->SETUP | |
7695 | */ | |
7696 | ||
7697 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
7698 | bool leading) | |
7699 | { | |
3b603066 | 7700 | struct bnx2x_queue_state_params q_params = {NULL}; |
619c5cb6 VZ |
7701 | struct bnx2x_queue_setup_params *setup_params = |
7702 | &q_params.params.setup; | |
6383c0b3 AE |
7703 | struct bnx2x_queue_setup_tx_only_params *tx_only_params = |
7704 | &q_params.params.tx_only; | |
a2fbb9ea | 7705 | int rc; |
6383c0b3 AE |
7706 | u8 tx_index; |
7707 | ||
51c1a580 | 7708 | DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); |
a2fbb9ea | 7709 | |
ec6ba945 VZ |
7710 | /* reset IGU state skip FCoE L2 queue */ |
7711 | if (!IS_FCOE_FP(fp)) | |
7712 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, | |
523224a3 | 7713 | IGU_INT_ENABLE, 0); |
a2fbb9ea | 7714 | |
619c5cb6 VZ |
7715 | q_params.q_obj = &fp->q_obj; |
7716 | /* We want to wait for completion in this context */ | |
7717 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 7718 | |
619c5cb6 VZ |
7719 | /* Prepare the INIT parameters */ |
7720 | bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); | |
ec6ba945 | 7721 | |
619c5cb6 VZ |
7722 | /* Set the command */ |
7723 | q_params.cmd = BNX2X_Q_CMD_INIT; | |
7724 | ||
7725 | /* Change the state to INIT */ | |
7726 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7727 | if (rc) { | |
6383c0b3 | 7728 | BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); |
619c5cb6 VZ |
7729 | return rc; |
7730 | } | |
ec6ba945 | 7731 | |
51c1a580 | 7732 | DP(NETIF_MSG_IFUP, "init complete\n"); |
6383c0b3 AE |
7733 | |
7734 | ||
619c5cb6 VZ |
7735 | /* Now move the Queue to the SETUP state... */ |
7736 | memset(setup_params, 0, sizeof(*setup_params)); | |
a2fbb9ea | 7737 | |
619c5cb6 VZ |
7738 | /* Set QUEUE flags */ |
7739 | setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); | |
523224a3 | 7740 | |
619c5cb6 | 7741 | /* Set general SETUP parameters */ |
6383c0b3 AE |
7742 | bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, |
7743 | FIRST_TX_COS_INDEX); | |
619c5cb6 | 7744 | |
6383c0b3 | 7745 | bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, |
619c5cb6 VZ |
7746 | &setup_params->rxq_params); |
7747 | ||
6383c0b3 AE |
7748 | bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, |
7749 | FIRST_TX_COS_INDEX); | |
619c5cb6 VZ |
7750 | |
7751 | /* Set the command */ | |
7752 | q_params.cmd = BNX2X_Q_CMD_SETUP; | |
7753 | ||
7754 | /* Change the state to SETUP */ | |
7755 | rc = bnx2x_queue_state_change(bp, &q_params); | |
6383c0b3 AE |
7756 | if (rc) { |
7757 | BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); | |
7758 | return rc; | |
7759 | } | |
7760 | ||
7761 | /* loop through the relevant tx-only indices */ | |
7762 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
7763 | tx_index < fp->max_cos; | |
7764 | tx_index++) { | |
7765 | ||
7766 | /* prepare and send tx-only ramrod*/ | |
7767 | rc = bnx2x_setup_tx_only(bp, fp, &q_params, | |
7768 | tx_only_params, tx_index, leading); | |
7769 | if (rc) { | |
7770 | BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", | |
7771 | fp->index, tx_index); | |
7772 | return rc; | |
7773 | } | |
7774 | } | |
523224a3 | 7775 | |
34f80b04 | 7776 | return rc; |
a2fbb9ea ET |
7777 | } |
7778 | ||
619c5cb6 | 7779 | static int bnx2x_stop_queue(struct bnx2x *bp, int index) |
a2fbb9ea | 7780 | { |
619c5cb6 | 7781 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
6383c0b3 | 7782 | struct bnx2x_fp_txdata *txdata; |
3b603066 | 7783 | struct bnx2x_queue_state_params q_params = {NULL}; |
6383c0b3 AE |
7784 | int rc, tx_index; |
7785 | ||
51c1a580 | 7786 | DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); |
a2fbb9ea | 7787 | |
619c5cb6 VZ |
7788 | q_params.q_obj = &fp->q_obj; |
7789 | /* We want to wait for completion in this context */ | |
7790 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 7791 | |
6383c0b3 AE |
7792 | |
7793 | /* close tx-only connections */ | |
7794 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
7795 | tx_index < fp->max_cos; | |
7796 | tx_index++){ | |
7797 | ||
7798 | /* ascertain this is a normal queue*/ | |
7799 | txdata = &fp->txdata[tx_index]; | |
7800 | ||
51c1a580 | 7801 | DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", |
6383c0b3 AE |
7802 | txdata->txq_index); |
7803 | ||
7804 | /* send halt terminate on tx-only connection */ | |
7805 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; | |
7806 | memset(&q_params.params.terminate, 0, | |
7807 | sizeof(q_params.params.terminate)); | |
7808 | q_params.params.terminate.cid_index = tx_index; | |
7809 | ||
7810 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7811 | if (rc) | |
7812 | return rc; | |
7813 | ||
7814 | /* send halt terminate on tx-only connection */ | |
7815 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; | |
7816 | memset(&q_params.params.cfc_del, 0, | |
7817 | sizeof(q_params.params.cfc_del)); | |
7818 | q_params.params.cfc_del.cid_index = tx_index; | |
7819 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7820 | if (rc) | |
7821 | return rc; | |
7822 | } | |
7823 | /* Stop the primary connection: */ | |
7824 | /* ...halt the connection */ | |
619c5cb6 VZ |
7825 | q_params.cmd = BNX2X_Q_CMD_HALT; |
7826 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7827 | if (rc) | |
da5a662a | 7828 | return rc; |
a2fbb9ea | 7829 | |
6383c0b3 | 7830 | /* ...terminate the connection */ |
619c5cb6 | 7831 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
6383c0b3 AE |
7832 | memset(&q_params.params.terminate, 0, |
7833 | sizeof(q_params.params.terminate)); | |
7834 | q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 VZ |
7835 | rc = bnx2x_queue_state_change(bp, &q_params); |
7836 | if (rc) | |
523224a3 | 7837 | return rc; |
6383c0b3 | 7838 | /* ...delete cfc entry */ |
619c5cb6 | 7839 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
6383c0b3 AE |
7840 | memset(&q_params.params.cfc_del, 0, |
7841 | sizeof(q_params.params.cfc_del)); | |
7842 | q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 | 7843 | return bnx2x_queue_state_change(bp, &q_params); |
523224a3 DK |
7844 | } |
7845 | ||
7846 | ||
34f80b04 EG |
7847 | static void bnx2x_reset_func(struct bnx2x *bp) |
7848 | { | |
7849 | int port = BP_PORT(bp); | |
7850 | int func = BP_FUNC(bp); | |
f2e0899f | 7851 | int i; |
523224a3 DK |
7852 | |
7853 | /* Disable the function in the FW */ | |
7854 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); | |
7855 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); | |
7856 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); | |
7857 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); | |
7858 | ||
7859 | /* FP SBs */ | |
ec6ba945 | 7860 | for_each_eth_queue(bp, i) { |
523224a3 | 7861 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
619c5cb6 | 7862 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
7863 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), |
7864 | SB_DISABLED); | |
523224a3 DK |
7865 | } |
7866 | ||
619c5cb6 VZ |
7867 | #ifdef BCM_CNIC |
7868 | /* CNIC SB */ | |
7869 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
7870 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), | |
7871 | SB_DISABLED); | |
7872 | #endif | |
523224a3 | 7873 | /* SP SB */ |
619c5cb6 | 7874 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
7875 | CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), |
7876 | SB_DISABLED); | |
523224a3 DK |
7877 | |
7878 | for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) | |
7879 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), | |
7880 | 0); | |
34f80b04 EG |
7881 | |
7882 | /* Configure IGU */ | |
f2e0899f DK |
7883 | if (bp->common.int_block == INT_BLOCK_HC) { |
7884 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7885 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7886 | } else { | |
7887 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); | |
7888 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
7889 | } | |
34f80b04 | 7890 | |
37b091ba MC |
7891 | #ifdef BCM_CNIC |
7892 | /* Disable Timer scan */ | |
7893 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); | |
7894 | /* | |
7895 | * Wait for at least 10ms and up to 2 second for the timers scan to | |
7896 | * complete | |
7897 | */ | |
7898 | for (i = 0; i < 200; i++) { | |
7899 | msleep(10); | |
7900 | if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) | |
7901 | break; | |
7902 | } | |
7903 | #endif | |
34f80b04 | 7904 | /* Clear ILT */ |
f2e0899f DK |
7905 | bnx2x_clear_func_ilt(bp, func); |
7906 | ||
7907 | /* Timers workaround bug for E2: if this is vnic-3, | |
7908 | * we need to set the entire ilt range for this timers. | |
7909 | */ | |
619c5cb6 | 7910 | if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { |
f2e0899f DK |
7911 | struct ilt_client_info ilt_cli; |
7912 | /* use dummy TM client */ | |
7913 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
7914 | ilt_cli.start = 0; | |
7915 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
7916 | ilt_cli.client_num = ILT_CLIENT_TM; | |
7917 | ||
7918 | bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); | |
7919 | } | |
7920 | ||
7921 | /* this assumes that reset_port() called before reset_func()*/ | |
619c5cb6 | 7922 | if (!CHIP_IS_E1x(bp)) |
f2e0899f | 7923 | bnx2x_pf_disable(bp); |
523224a3 DK |
7924 | |
7925 | bp->dmae_ready = 0; | |
34f80b04 EG |
7926 | } |
7927 | ||
7928 | static void bnx2x_reset_port(struct bnx2x *bp) | |
7929 | { | |
7930 | int port = BP_PORT(bp); | |
7931 | u32 val; | |
7932 | ||
619c5cb6 VZ |
7933 | /* Reset physical Link */ |
7934 | bnx2x__link_reset(bp); | |
7935 | ||
34f80b04 EG |
7936 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
7937 | ||
7938 | /* Do not rcv packets to BRB */ | |
7939 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); | |
7940 | /* Do not direct rcv packets that are not for MCP to the BRB */ | |
7941 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
7942 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
7943 | ||
7944 | /* Configure AEU */ | |
7945 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); | |
7946 | ||
7947 | msleep(100); | |
7948 | /* Check for BRB port occupancy */ | |
7949 | val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); | |
7950 | if (val) | |
7951 | DP(NETIF_MSG_IFDOWN, | |
33471629 | 7952 | "BRB1 is not empty %d blocks are occupied\n", val); |
34f80b04 EG |
7953 | |
7954 | /* TODO: Close Doorbell port? */ | |
7955 | } | |
7956 | ||
619c5cb6 | 7957 | static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) |
34f80b04 | 7958 | { |
3b603066 | 7959 | struct bnx2x_func_state_params func_params = {NULL}; |
34f80b04 | 7960 | |
619c5cb6 VZ |
7961 | /* Prepare parameters for function state transitions */ |
7962 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
34f80b04 | 7963 | |
619c5cb6 VZ |
7964 | func_params.f_obj = &bp->func_obj; |
7965 | func_params.cmd = BNX2X_F_CMD_HW_RESET; | |
34f80b04 | 7966 | |
619c5cb6 | 7967 | func_params.params.hw_init.load_phase = load_code; |
49d66772 | 7968 | |
619c5cb6 | 7969 | return bnx2x_func_state_change(bp, &func_params); |
34f80b04 EG |
7970 | } |
7971 | ||
619c5cb6 | 7972 | static inline int bnx2x_func_stop(struct bnx2x *bp) |
ec6ba945 | 7973 | { |
3b603066 | 7974 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 | 7975 | int rc; |
228241eb | 7976 | |
619c5cb6 VZ |
7977 | /* Prepare parameters for function state transitions */ |
7978 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
7979 | func_params.f_obj = &bp->func_obj; | |
7980 | func_params.cmd = BNX2X_F_CMD_STOP; | |
da5a662a | 7981 | |
619c5cb6 VZ |
7982 | /* |
7983 | * Try to stop the function the 'good way'. If fails (in case | |
7984 | * of a parity error during bnx2x_chip_cleanup()) and we are | |
7985 | * not in a debug mode, perform a state transaction in order to | |
7986 | * enable further HW_RESET transaction. | |
7987 | */ | |
7988 | rc = bnx2x_func_state_change(bp, &func_params); | |
7989 | if (rc) { | |
34f80b04 | 7990 | #ifdef BNX2X_STOP_ON_ERROR |
619c5cb6 | 7991 | return rc; |
34f80b04 | 7992 | #else |
51c1a580 | 7993 | BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); |
619c5cb6 VZ |
7994 | __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); |
7995 | return bnx2x_func_state_change(bp, &func_params); | |
34f80b04 | 7996 | #endif |
228241eb | 7997 | } |
a2fbb9ea | 7998 | |
619c5cb6 VZ |
7999 | return 0; |
8000 | } | |
523224a3 | 8001 | |
619c5cb6 VZ |
8002 | /** |
8003 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
8004 | * | |
8005 | * @bp: driver handle | |
8006 | * @unload_mode: requested function's unload mode | |
8007 | * | |
8008 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
8009 | */ | |
8010 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) | |
8011 | { | |
8012 | u32 reset_code = 0; | |
8013 | int port = BP_PORT(bp); | |
3101c2bc | 8014 | |
619c5cb6 | 8015 | /* Select the UNLOAD request mode */ |
65abd74d YG |
8016 | if (unload_mode == UNLOAD_NORMAL) |
8017 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
8018 | ||
7d0446c2 | 8019 | else if (bp->flags & NO_WOL_FLAG) |
65abd74d | 8020 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
65abd74d | 8021 | |
7d0446c2 | 8022 | else if (bp->wol) { |
65abd74d YG |
8023 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
8024 | u8 *mac_addr = bp->dev->dev_addr; | |
8025 | u32 val; | |
f9977903 DK |
8026 | u16 pmc; |
8027 | ||
65abd74d | 8028 | /* The mac address is written to entries 1-4 to |
f9977903 DK |
8029 | * preserve entry 0 which is used by the PMF |
8030 | */ | |
3395a033 | 8031 | u8 entry = (BP_VN(bp) + 1)*8; |
65abd74d YG |
8032 | |
8033 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
8034 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); | |
8035 | ||
8036 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | |
8037 | (mac_addr[4] << 8) | mac_addr[5]; | |
8038 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); | |
8039 | ||
f9977903 DK |
8040 | /* Enable the PME and clear the status */ |
8041 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); | |
8042 | pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; | |
8043 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); | |
8044 | ||
65abd74d YG |
8045 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; |
8046 | ||
8047 | } else | |
8048 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
da5a662a | 8049 | |
619c5cb6 VZ |
8050 | /* Send the request to the MCP */ |
8051 | if (!BP_NOMCP(bp)) | |
8052 | reset_code = bnx2x_fw_command(bp, reset_code, 0); | |
8053 | else { | |
8054 | int path = BP_PATH(bp); | |
8055 | ||
51c1a580 | 8056 | DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", |
619c5cb6 VZ |
8057 | path, load_count[path][0], load_count[path][1], |
8058 | load_count[path][2]); | |
8059 | load_count[path][0]--; | |
8060 | load_count[path][1 + port]--; | |
51c1a580 | 8061 | DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", |
619c5cb6 VZ |
8062 | path, load_count[path][0], load_count[path][1], |
8063 | load_count[path][2]); | |
8064 | if (load_count[path][0] == 0) | |
8065 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; | |
8066 | else if (load_count[path][1 + port] == 0) | |
8067 | reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; | |
8068 | else | |
8069 | reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; | |
8070 | } | |
8071 | ||
8072 | return reset_code; | |
8073 | } | |
8074 | ||
8075 | /** | |
8076 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
8077 | * | |
8078 | * @bp: driver handle | |
8079 | */ | |
8080 | void bnx2x_send_unload_done(struct bnx2x *bp) | |
8081 | { | |
8082 | /* Report UNLOAD_DONE to MCP */ | |
8083 | if (!BP_NOMCP(bp)) | |
8084 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
8085 | } | |
8086 | ||
6debea87 DK |
8087 | static inline int bnx2x_func_wait_started(struct bnx2x *bp) |
8088 | { | |
8089 | int tout = 50; | |
8090 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
8091 | ||
8092 | if (!bp->port.pmf) | |
8093 | return 0; | |
8094 | ||
8095 | /* | |
8096 | * (assumption: No Attention from MCP at this stage) | |
8097 | * PMF probably in the middle of TXdisable/enable transaction | |
8098 | * 1. Sync IRS for default SB | |
8099 | * 2. Sync SP queue - this guarantes us that attention handling started | |
8100 | * 3. Wait, that TXdisable/enable transaction completes | |
8101 | * | |
8102 | * 1+2 guranty that if DCBx attention was scheduled it already changed | |
8103 | * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy | |
8104 | * received complettion for the transaction the state is TX_STOPPED. | |
8105 | * State will return to STARTED after completion of TX_STOPPED-->STARTED | |
8106 | * transaction. | |
8107 | */ | |
8108 | ||
8109 | /* make sure default SB ISR is done */ | |
8110 | if (msix) | |
8111 | synchronize_irq(bp->msix_table[0].vector); | |
8112 | else | |
8113 | synchronize_irq(bp->pdev->irq); | |
8114 | ||
8115 | flush_workqueue(bnx2x_wq); | |
8116 | ||
8117 | while (bnx2x_func_get_state(bp, &bp->func_obj) != | |
8118 | BNX2X_F_STATE_STARTED && tout--) | |
8119 | msleep(20); | |
8120 | ||
8121 | if (bnx2x_func_get_state(bp, &bp->func_obj) != | |
8122 | BNX2X_F_STATE_STARTED) { | |
8123 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 8124 | BNX2X_ERR("Wrong function state\n"); |
6debea87 DK |
8125 | return -EBUSY; |
8126 | #else | |
8127 | /* | |
8128 | * Failed to complete the transaction in a "good way" | |
8129 | * Force both transactions with CLR bit | |
8130 | */ | |
3b603066 | 8131 | struct bnx2x_func_state_params func_params = {NULL}; |
6debea87 | 8132 | |
51c1a580 MS |
8133 | DP(NETIF_MSG_IFDOWN, |
8134 | "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n"); | |
6debea87 DK |
8135 | |
8136 | func_params.f_obj = &bp->func_obj; | |
8137 | __set_bit(RAMROD_DRV_CLR_ONLY, | |
8138 | &func_params.ramrod_flags); | |
8139 | ||
8140 | /* STARTED-->TX_ST0PPED */ | |
8141 | func_params.cmd = BNX2X_F_CMD_TX_STOP; | |
8142 | bnx2x_func_state_change(bp, &func_params); | |
8143 | ||
8144 | /* TX_ST0PPED-->STARTED */ | |
8145 | func_params.cmd = BNX2X_F_CMD_TX_START; | |
8146 | return bnx2x_func_state_change(bp, &func_params); | |
8147 | #endif | |
8148 | } | |
8149 | ||
8150 | return 0; | |
8151 | } | |
8152 | ||
619c5cb6 VZ |
8153 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) |
8154 | { | |
8155 | int port = BP_PORT(bp); | |
6383c0b3 AE |
8156 | int i, rc = 0; |
8157 | u8 cos; | |
3b603066 | 8158 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 VZ |
8159 | u32 reset_code; |
8160 | ||
8161 | /* Wait until tx fastpath tasks complete */ | |
8162 | for_each_tx_queue(bp, i) { | |
8163 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
8164 | ||
6383c0b3 AE |
8165 | for_each_cos_in_tx_queue(fp, cos) |
8166 | rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); | |
619c5cb6 VZ |
8167 | #ifdef BNX2X_STOP_ON_ERROR |
8168 | if (rc) | |
8169 | return; | |
8170 | #endif | |
8171 | } | |
8172 | ||
8173 | /* Give HW time to discard old tx messages */ | |
8174 | usleep_range(1000, 1000); | |
8175 | ||
8176 | /* Clean all ETH MACs */ | |
8177 | rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); | |
8178 | if (rc < 0) | |
8179 | BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); | |
8180 | ||
8181 | /* Clean up UC list */ | |
8182 | rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, | |
8183 | true); | |
8184 | if (rc < 0) | |
51c1a580 MS |
8185 | BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", |
8186 | rc); | |
619c5cb6 VZ |
8187 | |
8188 | /* Disable LLH */ | |
8189 | if (!CHIP_IS_E1(bp)) | |
8190 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
8191 | ||
8192 | /* Set "drop all" (stop Rx). | |
8193 | * We need to take a netif_addr_lock() here in order to prevent | |
8194 | * a race between the completion code and this code. | |
8195 | */ | |
8196 | netif_addr_lock_bh(bp->dev); | |
8197 | /* Schedule the rx_mode command */ | |
8198 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
8199 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
8200 | else | |
8201 | bnx2x_set_storm_rx_mode(bp); | |
8202 | ||
8203 | /* Cleanup multicast configuration */ | |
8204 | rparam.mcast_obj = &bp->mcast_obj; | |
8205 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
8206 | if (rc < 0) | |
8207 | BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); | |
8208 | ||
8209 | netif_addr_unlock_bh(bp->dev); | |
8210 | ||
8211 | ||
6debea87 DK |
8212 | |
8213 | /* | |
8214 | * Send the UNLOAD_REQUEST to the MCP. This will return if | |
8215 | * this function should perform FUNC, PORT or COMMON HW | |
8216 | * reset. | |
8217 | */ | |
8218 | reset_code = bnx2x_send_unload_req(bp, unload_mode); | |
8219 | ||
8220 | /* | |
8221 | * (assumption: No Attention from MCP at this stage) | |
8222 | * PMF probably in the middle of TXdisable/enable transaction | |
8223 | */ | |
8224 | rc = bnx2x_func_wait_started(bp); | |
8225 | if (rc) { | |
8226 | BNX2X_ERR("bnx2x_func_wait_started failed\n"); | |
8227 | #ifdef BNX2X_STOP_ON_ERROR | |
8228 | return; | |
8229 | #endif | |
8230 | } | |
8231 | ||
34f80b04 | 8232 | /* Close multi and leading connections |
619c5cb6 VZ |
8233 | * Completions for ramrods are collected in a synchronous way |
8234 | */ | |
523224a3 | 8235 | for_each_queue(bp, i) |
619c5cb6 | 8236 | if (bnx2x_stop_queue(bp, i)) |
523224a3 DK |
8237 | #ifdef BNX2X_STOP_ON_ERROR |
8238 | return; | |
8239 | #else | |
228241eb | 8240 | goto unload_error; |
523224a3 | 8241 | #endif |
619c5cb6 VZ |
8242 | /* If SP settings didn't get completed so far - something |
8243 | * very wrong has happen. | |
8244 | */ | |
8245 | if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) | |
8246 | BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); | |
a2fbb9ea | 8247 | |
619c5cb6 VZ |
8248 | #ifndef BNX2X_STOP_ON_ERROR |
8249 | unload_error: | |
8250 | #endif | |
523224a3 | 8251 | rc = bnx2x_func_stop(bp); |
da5a662a | 8252 | if (rc) { |
523224a3 | 8253 | BNX2X_ERR("Function stop failed!\n"); |
da5a662a | 8254 | #ifdef BNX2X_STOP_ON_ERROR |
523224a3 | 8255 | return; |
523224a3 | 8256 | #endif |
34f80b04 | 8257 | } |
a2fbb9ea | 8258 | |
523224a3 DK |
8259 | /* Disable HW interrupts, NAPI */ |
8260 | bnx2x_netif_stop(bp, 1); | |
8261 | ||
8262 | /* Release IRQs */ | |
d6214d7a | 8263 | bnx2x_free_irq(bp); |
523224a3 | 8264 | |
a2fbb9ea | 8265 | /* Reset the chip */ |
619c5cb6 VZ |
8266 | rc = bnx2x_reset_hw(bp, reset_code); |
8267 | if (rc) | |
8268 | BNX2X_ERR("HW_RESET failed\n"); | |
a2fbb9ea | 8269 | |
356e2385 | 8270 | |
619c5cb6 VZ |
8271 | /* Report UNLOAD_DONE to MCP */ |
8272 | bnx2x_send_unload_done(bp); | |
72fd0718 VZ |
8273 | } |
8274 | ||
9f6c9258 | 8275 | void bnx2x_disable_close_the_gate(struct bnx2x *bp) |
72fd0718 VZ |
8276 | { |
8277 | u32 val; | |
8278 | ||
51c1a580 | 8279 | DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); |
72fd0718 VZ |
8280 | |
8281 | if (CHIP_IS_E1(bp)) { | |
8282 | int port = BP_PORT(bp); | |
8283 | u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
8284 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
8285 | ||
8286 | val = REG_RD(bp, addr); | |
8287 | val &= ~(0x300); | |
8288 | REG_WR(bp, addr, val); | |
619c5cb6 | 8289 | } else { |
72fd0718 VZ |
8290 | val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); |
8291 | val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | | |
8292 | MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); | |
8293 | REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); | |
8294 | } | |
8295 | } | |
8296 | ||
72fd0718 VZ |
8297 | /* Close gates #2, #3 and #4: */ |
8298 | static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) | |
8299 | { | |
c9ee9206 | 8300 | u32 val; |
72fd0718 VZ |
8301 | |
8302 | /* Gates #2 and #4a are closed/opened for "not E1" only */ | |
8303 | if (!CHIP_IS_E1(bp)) { | |
8304 | /* #4 */ | |
c9ee9206 | 8305 | REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); |
72fd0718 | 8306 | /* #2 */ |
c9ee9206 | 8307 | REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); |
72fd0718 VZ |
8308 | } |
8309 | ||
8310 | /* #3 */ | |
c9ee9206 VZ |
8311 | if (CHIP_IS_E1x(bp)) { |
8312 | /* Prevent interrupts from HC on both ports */ | |
8313 | val = REG_RD(bp, HC_REG_CONFIG_1); | |
8314 | REG_WR(bp, HC_REG_CONFIG_1, | |
8315 | (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : | |
8316 | (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); | |
8317 | ||
8318 | val = REG_RD(bp, HC_REG_CONFIG_0); | |
8319 | REG_WR(bp, HC_REG_CONFIG_0, | |
8320 | (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : | |
8321 | (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); | |
8322 | } else { | |
8323 | /* Prevent incomming interrupts in IGU */ | |
8324 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); | |
8325 | ||
8326 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, | |
8327 | (!close) ? | |
8328 | (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : | |
8329 | (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); | |
8330 | } | |
72fd0718 | 8331 | |
51c1a580 | 8332 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", |
72fd0718 VZ |
8333 | close ? "closing" : "opening"); |
8334 | mmiowb(); | |
8335 | } | |
8336 | ||
8337 | #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ | |
8338 | ||
8339 | static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) | |
8340 | { | |
8341 | /* Do some magic... */ | |
8342 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); | |
8343 | *magic_val = val & SHARED_MF_CLP_MAGIC; | |
8344 | MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); | |
8345 | } | |
8346 | ||
e8920674 DK |
8347 | /** |
8348 | * bnx2x_clp_reset_done - restore the value of the `magic' bit. | |
72fd0718 | 8349 | * |
e8920674 DK |
8350 | * @bp: driver handle |
8351 | * @magic_val: old value of the `magic' bit. | |
72fd0718 VZ |
8352 | */ |
8353 | static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) | |
8354 | { | |
8355 | /* Restore the `magic' bit value... */ | |
72fd0718 VZ |
8356 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
8357 | MF_CFG_WR(bp, shared_mf_config.clp_mb, | |
8358 | (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); | |
8359 | } | |
8360 | ||
f85582f8 | 8361 | /** |
e8920674 | 8362 | * bnx2x_reset_mcp_prep - prepare for MCP reset. |
72fd0718 | 8363 | * |
e8920674 DK |
8364 | * @bp: driver handle |
8365 | * @magic_val: old value of 'magic' bit. | |
8366 | * | |
8367 | * Takes care of CLP configurations. | |
72fd0718 VZ |
8368 | */ |
8369 | static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) | |
8370 | { | |
8371 | u32 shmem; | |
8372 | u32 validity_offset; | |
8373 | ||
51c1a580 | 8374 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); |
72fd0718 VZ |
8375 | |
8376 | /* Set `magic' bit in order to save MF config */ | |
8377 | if (!CHIP_IS_E1(bp)) | |
8378 | bnx2x_clp_reset_prep(bp, magic_val); | |
8379 | ||
8380 | /* Get shmem offset */ | |
8381 | shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
8382 | validity_offset = offsetof(struct shmem_region, validity_map[0]); | |
8383 | ||
8384 | /* Clear validity map flags */ | |
8385 | if (shmem > 0) | |
8386 | REG_WR(bp, shmem + validity_offset, 0); | |
8387 | } | |
8388 | ||
8389 | #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ | |
8390 | #define MCP_ONE_TIMEOUT 100 /* 100 ms */ | |
8391 | ||
e8920674 DK |
8392 | /** |
8393 | * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT | |
72fd0718 | 8394 | * |
e8920674 | 8395 | * @bp: driver handle |
72fd0718 VZ |
8396 | */ |
8397 | static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) | |
8398 | { | |
8399 | /* special handling for emulation and FPGA, | |
8400 | wait 10 times longer */ | |
8401 | if (CHIP_REV_IS_SLOW(bp)) | |
8402 | msleep(MCP_ONE_TIMEOUT*10); | |
8403 | else | |
8404 | msleep(MCP_ONE_TIMEOUT); | |
8405 | } | |
8406 | ||
1b6e2ceb DK |
8407 | /* |
8408 | * initializes bp->common.shmem_base and waits for validity signature to appear | |
8409 | */ | |
8410 | static int bnx2x_init_shmem(struct bnx2x *bp) | |
72fd0718 | 8411 | { |
1b6e2ceb DK |
8412 | int cnt = 0; |
8413 | u32 val = 0; | |
72fd0718 | 8414 | |
1b6e2ceb DK |
8415 | do { |
8416 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
8417 | if (bp->common.shmem_base) { | |
8418 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
8419 | if (val & SHR_MEM_VALIDITY_MB) | |
8420 | return 0; | |
8421 | } | |
72fd0718 | 8422 | |
1b6e2ceb | 8423 | bnx2x_mcp_wait_one(bp); |
72fd0718 | 8424 | |
1b6e2ceb | 8425 | } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); |
72fd0718 | 8426 | |
1b6e2ceb | 8427 | BNX2X_ERR("BAD MCP validity signature\n"); |
72fd0718 | 8428 | |
1b6e2ceb DK |
8429 | return -ENODEV; |
8430 | } | |
72fd0718 | 8431 | |
1b6e2ceb DK |
8432 | static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) |
8433 | { | |
8434 | int rc = bnx2x_init_shmem(bp); | |
72fd0718 | 8435 | |
72fd0718 VZ |
8436 | /* Restore the `magic' bit value */ |
8437 | if (!CHIP_IS_E1(bp)) | |
8438 | bnx2x_clp_reset_done(bp, magic_val); | |
8439 | ||
8440 | return rc; | |
8441 | } | |
8442 | ||
8443 | static void bnx2x_pxp_prep(struct bnx2x *bp) | |
8444 | { | |
8445 | if (!CHIP_IS_E1(bp)) { | |
8446 | REG_WR(bp, PXP2_REG_RD_START_INIT, 0); | |
8447 | REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); | |
72fd0718 VZ |
8448 | mmiowb(); |
8449 | } | |
8450 | } | |
8451 | ||
8452 | /* | |
8453 | * Reset the whole chip except for: | |
8454 | * - PCIE core | |
8455 | * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by | |
8456 | * one reset bit) | |
8457 | * - IGU | |
8458 | * - MISC (including AEU) | |
8459 | * - GRC | |
8460 | * - RBCN, RBCP | |
8461 | */ | |
c9ee9206 | 8462 | static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) |
72fd0718 VZ |
8463 | { |
8464 | u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; | |
8736c826 | 8465 | u32 global_bits2, stay_reset2; |
c9ee9206 VZ |
8466 | |
8467 | /* | |
8468 | * Bits that have to be set in reset_mask2 if we want to reset 'global' | |
8469 | * (per chip) blocks. | |
8470 | */ | |
8471 | global_bits2 = | |
8472 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | | |
8473 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; | |
72fd0718 | 8474 | |
8736c826 | 8475 | /* Don't reset the following blocks */ |
72fd0718 VZ |
8476 | not_reset_mask1 = |
8477 | MISC_REGISTERS_RESET_REG_1_RST_HC | | |
8478 | MISC_REGISTERS_RESET_REG_1_RST_PXPV | | |
8479 | MISC_REGISTERS_RESET_REG_1_RST_PXP; | |
8480 | ||
8481 | not_reset_mask2 = | |
c9ee9206 | 8482 | MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | |
72fd0718 VZ |
8483 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | |
8484 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | | |
8485 | MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | | |
8486 | MISC_REGISTERS_RESET_REG_2_RST_RBCN | | |
8487 | MISC_REGISTERS_RESET_REG_2_RST_GRC | | |
8488 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | | |
8736c826 VZ |
8489 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | |
8490 | MISC_REGISTERS_RESET_REG_2_RST_ATC | | |
8491 | MISC_REGISTERS_RESET_REG_2_PGLC; | |
72fd0718 | 8492 | |
8736c826 VZ |
8493 | /* |
8494 | * Keep the following blocks in reset: | |
8495 | * - all xxMACs are handled by the bnx2x_link code. | |
8496 | */ | |
8497 | stay_reset2 = | |
8498 | MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | | |
8499 | MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | | |
8500 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | | |
8501 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | | |
8502 | MISC_REGISTERS_RESET_REG_2_UMAC0 | | |
8503 | MISC_REGISTERS_RESET_REG_2_UMAC1 | | |
8504 | MISC_REGISTERS_RESET_REG_2_XMAC | | |
8505 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; | |
8506 | ||
8507 | /* Full reset masks according to the chip */ | |
72fd0718 VZ |
8508 | reset_mask1 = 0xffffffff; |
8509 | ||
8510 | if (CHIP_IS_E1(bp)) | |
8511 | reset_mask2 = 0xffff; | |
8736c826 | 8512 | else if (CHIP_IS_E1H(bp)) |
72fd0718 | 8513 | reset_mask2 = 0x1ffff; |
8736c826 VZ |
8514 | else if (CHIP_IS_E2(bp)) |
8515 | reset_mask2 = 0xfffff; | |
8516 | else /* CHIP_IS_E3 */ | |
8517 | reset_mask2 = 0x3ffffff; | |
c9ee9206 VZ |
8518 | |
8519 | /* Don't reset global blocks unless we need to */ | |
8520 | if (!global) | |
8521 | reset_mask2 &= ~global_bits2; | |
8522 | ||
8523 | /* | |
8524 | * In case of attention in the QM, we need to reset PXP | |
8525 | * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM | |
8526 | * because otherwise QM reset would release 'close the gates' shortly | |
8527 | * before resetting the PXP, then the PSWRQ would send a write | |
8528 | * request to PGLUE. Then when PXP is reset, PGLUE would try to | |
8529 | * read the payload data from PSWWR, but PSWWR would not | |
8530 | * respond. The write queue in PGLUE would stuck, dmae commands | |
8531 | * would not return. Therefore it's important to reset the second | |
8532 | * reset register (containing the | |
8533 | * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the | |
8534 | * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM | |
8535 | * bit). | |
8536 | */ | |
72fd0718 VZ |
8537 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
8538 | reset_mask2 & (~not_reset_mask2)); | |
8539 | ||
c9ee9206 VZ |
8540 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
8541 | reset_mask1 & (~not_reset_mask1)); | |
8542 | ||
72fd0718 VZ |
8543 | barrier(); |
8544 | mmiowb(); | |
8545 | ||
8736c826 VZ |
8546 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
8547 | reset_mask2 & (~stay_reset2)); | |
8548 | ||
8549 | barrier(); | |
8550 | mmiowb(); | |
8551 | ||
c9ee9206 | 8552 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); |
72fd0718 VZ |
8553 | mmiowb(); |
8554 | } | |
8555 | ||
c9ee9206 VZ |
8556 | /** |
8557 | * bnx2x_er_poll_igu_vq - poll for pending writes bit. | |
8558 | * It should get cleared in no more than 1s. | |
8559 | * | |
8560 | * @bp: driver handle | |
8561 | * | |
8562 | * It should get cleared in no more than 1s. Returns 0 if | |
8563 | * pending writes bit gets cleared. | |
8564 | */ | |
8565 | static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) | |
8566 | { | |
8567 | u32 cnt = 1000; | |
8568 | u32 pend_bits = 0; | |
8569 | ||
8570 | do { | |
8571 | pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); | |
8572 | ||
8573 | if (pend_bits == 0) | |
8574 | break; | |
8575 | ||
8576 | usleep_range(1000, 1000); | |
8577 | } while (cnt-- > 0); | |
8578 | ||
8579 | if (cnt <= 0) { | |
8580 | BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", | |
8581 | pend_bits); | |
8582 | return -EBUSY; | |
8583 | } | |
8584 | ||
8585 | return 0; | |
8586 | } | |
8587 | ||
8588 | static int bnx2x_process_kill(struct bnx2x *bp, bool global) | |
72fd0718 VZ |
8589 | { |
8590 | int cnt = 1000; | |
8591 | u32 val = 0; | |
8592 | u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; | |
8593 | ||
8594 | ||
8595 | /* Empty the Tetris buffer, wait for 1s */ | |
8596 | do { | |
8597 | sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); | |
8598 | blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); | |
8599 | port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); | |
8600 | port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); | |
8601 | pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); | |
8602 | if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && | |
8603 | ((port_is_idle_0 & 0x1) == 0x1) && | |
8604 | ((port_is_idle_1 & 0x1) == 0x1) && | |
8605 | (pgl_exp_rom2 == 0xffffffff)) | |
8606 | break; | |
c9ee9206 | 8607 | usleep_range(1000, 1000); |
72fd0718 VZ |
8608 | } while (cnt-- > 0); |
8609 | ||
8610 | if (cnt <= 0) { | |
51c1a580 MS |
8611 | BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); |
8612 | BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", | |
72fd0718 VZ |
8613 | sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, |
8614 | pgl_exp_rom2); | |
8615 | return -EAGAIN; | |
8616 | } | |
8617 | ||
8618 | barrier(); | |
8619 | ||
8620 | /* Close gates #2, #3 and #4 */ | |
8621 | bnx2x_set_234_gates(bp, true); | |
8622 | ||
c9ee9206 VZ |
8623 | /* Poll for IGU VQs for 57712 and newer chips */ |
8624 | if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) | |
8625 | return -EAGAIN; | |
8626 | ||
8627 | ||
72fd0718 VZ |
8628 | /* TBD: Indicate that "process kill" is in progress to MCP */ |
8629 | ||
8630 | /* Clear "unprepared" bit */ | |
8631 | REG_WR(bp, MISC_REG_UNPREPARED, 0); | |
8632 | barrier(); | |
8633 | ||
8634 | /* Make sure all is written to the chip before the reset */ | |
8635 | mmiowb(); | |
8636 | ||
8637 | /* Wait for 1ms to empty GLUE and PCI-E core queues, | |
8638 | * PSWHST, GRC and PSWRD Tetris buffer. | |
8639 | */ | |
c9ee9206 | 8640 | usleep_range(1000, 1000); |
72fd0718 VZ |
8641 | |
8642 | /* Prepare to chip reset: */ | |
8643 | /* MCP */ | |
c9ee9206 VZ |
8644 | if (global) |
8645 | bnx2x_reset_mcp_prep(bp, &val); | |
72fd0718 VZ |
8646 | |
8647 | /* PXP */ | |
8648 | bnx2x_pxp_prep(bp); | |
8649 | barrier(); | |
8650 | ||
8651 | /* reset the chip */ | |
c9ee9206 | 8652 | bnx2x_process_kill_chip_reset(bp, global); |
72fd0718 VZ |
8653 | barrier(); |
8654 | ||
8655 | /* Recover after reset: */ | |
8656 | /* MCP */ | |
c9ee9206 | 8657 | if (global && bnx2x_reset_mcp_comp(bp, val)) |
72fd0718 VZ |
8658 | return -EAGAIN; |
8659 | ||
c9ee9206 VZ |
8660 | /* TBD: Add resetting the NO_MCP mode DB here */ |
8661 | ||
72fd0718 VZ |
8662 | /* PXP */ |
8663 | bnx2x_pxp_prep(bp); | |
8664 | ||
8665 | /* Open the gates #2, #3 and #4 */ | |
8666 | bnx2x_set_234_gates(bp, false); | |
8667 | ||
8668 | /* TBD: IGU/AEU preparation bring back the AEU/IGU to a | |
8669 | * reset state, re-enable attentions. */ | |
8670 | ||
a2fbb9ea ET |
8671 | return 0; |
8672 | } | |
8673 | ||
c9ee9206 | 8674 | int bnx2x_leader_reset(struct bnx2x *bp) |
72fd0718 VZ |
8675 | { |
8676 | int rc = 0; | |
c9ee9206 | 8677 | bool global = bnx2x_reset_is_global(bp); |
95c6c616 AE |
8678 | u32 load_code; |
8679 | ||
8680 | /* if not going to reset MCP - load "fake" driver to reset HW while | |
8681 | * driver is owner of the HW | |
8682 | */ | |
8683 | if (!global && !BP_NOMCP(bp)) { | |
8684 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0); | |
8685 | if (!load_code) { | |
8686 | BNX2X_ERR("MCP response failure, aborting\n"); | |
8687 | rc = -EAGAIN; | |
8688 | goto exit_leader_reset; | |
8689 | } | |
8690 | if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && | |
8691 | (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { | |
8692 | BNX2X_ERR("MCP unexpected resp, aborting\n"); | |
8693 | rc = -EAGAIN; | |
8694 | goto exit_leader_reset2; | |
8695 | } | |
8696 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); | |
8697 | if (!load_code) { | |
8698 | BNX2X_ERR("MCP response failure, aborting\n"); | |
8699 | rc = -EAGAIN; | |
8700 | goto exit_leader_reset2; | |
8701 | } | |
8702 | } | |
c9ee9206 | 8703 | |
72fd0718 | 8704 | /* Try to recover after the failure */ |
c9ee9206 | 8705 | if (bnx2x_process_kill(bp, global)) { |
51c1a580 MS |
8706 | BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", |
8707 | BP_PATH(bp)); | |
72fd0718 | 8708 | rc = -EAGAIN; |
95c6c616 | 8709 | goto exit_leader_reset2; |
72fd0718 VZ |
8710 | } |
8711 | ||
c9ee9206 VZ |
8712 | /* |
8713 | * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver | |
8714 | * state. | |
8715 | */ | |
72fd0718 | 8716 | bnx2x_set_reset_done(bp); |
c9ee9206 VZ |
8717 | if (global) |
8718 | bnx2x_clear_reset_global(bp); | |
72fd0718 | 8719 | |
95c6c616 AE |
8720 | exit_leader_reset2: |
8721 | /* unload "fake driver" if it was loaded */ | |
8722 | if (!global && !BP_NOMCP(bp)) { | |
8723 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); | |
8724 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
8725 | } | |
72fd0718 VZ |
8726 | exit_leader_reset: |
8727 | bp->is_leader = 0; | |
c9ee9206 VZ |
8728 | bnx2x_release_leader_lock(bp); |
8729 | smp_mb(); | |
72fd0718 VZ |
8730 | return rc; |
8731 | } | |
8732 | ||
c9ee9206 VZ |
8733 | static inline void bnx2x_recovery_failed(struct bnx2x *bp) |
8734 | { | |
8735 | netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); | |
8736 | ||
8737 | /* Disconnect this device */ | |
8738 | netif_device_detach(bp->dev); | |
8739 | ||
8740 | /* | |
8741 | * Block ifup for all function on this engine until "process kill" | |
8742 | * or power cycle. | |
8743 | */ | |
8744 | bnx2x_set_reset_in_progress(bp); | |
8745 | ||
8746 | /* Shut down the power */ | |
8747 | bnx2x_set_power_state(bp, PCI_D3hot); | |
8748 | ||
8749 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
8750 | ||
8751 | smp_mb(); | |
8752 | } | |
8753 | ||
8754 | /* | |
8755 | * Assumption: runs under rtnl lock. This together with the fact | |
6383c0b3 | 8756 | * that it's called only from bnx2x_sp_rtnl() ensure that it |
72fd0718 VZ |
8757 | * will never be called when netif_running(bp->dev) is false. |
8758 | */ | |
8759 | static void bnx2x_parity_recover(struct bnx2x *bp) | |
8760 | { | |
c9ee9206 | 8761 | bool global = false; |
7a752993 | 8762 | u32 error_recovered, error_unrecovered; |
95c6c616 | 8763 | bool is_parity; |
c9ee9206 | 8764 | |
72fd0718 VZ |
8765 | DP(NETIF_MSG_HW, "Handling parity\n"); |
8766 | while (1) { | |
8767 | switch (bp->recovery_state) { | |
8768 | case BNX2X_RECOVERY_INIT: | |
8769 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); | |
95c6c616 AE |
8770 | is_parity = bnx2x_chk_parity_attn(bp, &global, false); |
8771 | WARN_ON(!is_parity); | |
c9ee9206 | 8772 | |
72fd0718 | 8773 | /* Try to get a LEADER_LOCK HW lock */ |
c9ee9206 VZ |
8774 | if (bnx2x_trylock_leader_lock(bp)) { |
8775 | bnx2x_set_reset_in_progress(bp); | |
8776 | /* | |
8777 | * Check if there is a global attention and if | |
8778 | * there was a global attention, set the global | |
8779 | * reset bit. | |
8780 | */ | |
8781 | ||
8782 | if (global) | |
8783 | bnx2x_set_reset_global(bp); | |
8784 | ||
72fd0718 | 8785 | bp->is_leader = 1; |
c9ee9206 | 8786 | } |
72fd0718 VZ |
8787 | |
8788 | /* Stop the driver */ | |
8789 | /* If interface has been removed - break */ | |
8790 | if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) | |
8791 | return; | |
8792 | ||
8793 | bp->recovery_state = BNX2X_RECOVERY_WAIT; | |
c9ee9206 | 8794 | |
c9ee9206 VZ |
8795 | /* Ensure "is_leader", MCP command sequence and |
8796 | * "recovery_state" update values are seen on other | |
8797 | * CPUs. | |
72fd0718 | 8798 | */ |
c9ee9206 | 8799 | smp_mb(); |
72fd0718 VZ |
8800 | break; |
8801 | ||
8802 | case BNX2X_RECOVERY_WAIT: | |
8803 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); | |
8804 | if (bp->is_leader) { | |
c9ee9206 | 8805 | int other_engine = BP_PATH(bp) ? 0 : 1; |
889b9af3 AE |
8806 | bool other_load_status = |
8807 | bnx2x_get_load_status(bp, other_engine); | |
8808 | bool load_status = | |
8809 | bnx2x_get_load_status(bp, BP_PATH(bp)); | |
c9ee9206 VZ |
8810 | global = bnx2x_reset_is_global(bp); |
8811 | ||
8812 | /* | |
8813 | * In case of a parity in a global block, let | |
8814 | * the first leader that performs a | |
8815 | * leader_reset() reset the global blocks in | |
8816 | * order to clear global attentions. Otherwise | |
8817 | * the the gates will remain closed for that | |
8818 | * engine. | |
8819 | */ | |
889b9af3 AE |
8820 | if (load_status || |
8821 | (global && other_load_status)) { | |
72fd0718 VZ |
8822 | /* Wait until all other functions get |
8823 | * down. | |
8824 | */ | |
7be08a72 | 8825 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
8826 | HZ/10); |
8827 | return; | |
8828 | } else { | |
8829 | /* If all other functions got down - | |
8830 | * try to bring the chip back to | |
8831 | * normal. In any case it's an exit | |
8832 | * point for a leader. | |
8833 | */ | |
c9ee9206 VZ |
8834 | if (bnx2x_leader_reset(bp)) { |
8835 | bnx2x_recovery_failed(bp); | |
72fd0718 VZ |
8836 | return; |
8837 | } | |
8838 | ||
c9ee9206 VZ |
8839 | /* If we are here, means that the |
8840 | * leader has succeeded and doesn't | |
8841 | * want to be a leader any more. Try | |
8842 | * to continue as a none-leader. | |
8843 | */ | |
8844 | break; | |
72fd0718 VZ |
8845 | } |
8846 | } else { /* non-leader */ | |
c9ee9206 | 8847 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { |
72fd0718 VZ |
8848 | /* Try to get a LEADER_LOCK HW lock as |
8849 | * long as a former leader may have | |
8850 | * been unloaded by the user or | |
8851 | * released a leadership by another | |
8852 | * reason. | |
8853 | */ | |
c9ee9206 | 8854 | if (bnx2x_trylock_leader_lock(bp)) { |
72fd0718 VZ |
8855 | /* I'm a leader now! Restart a |
8856 | * switch case. | |
8857 | */ | |
8858 | bp->is_leader = 1; | |
8859 | break; | |
8860 | } | |
8861 | ||
7be08a72 | 8862 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
8863 | HZ/10); |
8864 | return; | |
8865 | ||
c9ee9206 VZ |
8866 | } else { |
8867 | /* | |
8868 | * If there was a global attention, wait | |
8869 | * for it to be cleared. | |
8870 | */ | |
8871 | if (bnx2x_reset_is_global(bp)) { | |
8872 | schedule_delayed_work( | |
7be08a72 AE |
8873 | &bp->sp_rtnl_task, |
8874 | HZ/10); | |
c9ee9206 VZ |
8875 | return; |
8876 | } | |
8877 | ||
7a752993 AE |
8878 | error_recovered = |
8879 | bp->eth_stats.recoverable_error; | |
8880 | error_unrecovered = | |
8881 | bp->eth_stats.unrecoverable_error; | |
95c6c616 AE |
8882 | bp->recovery_state = |
8883 | BNX2X_RECOVERY_NIC_LOADING; | |
8884 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) { | |
7a752993 | 8885 | error_unrecovered++; |
95c6c616 | 8886 | netdev_err(bp->dev, |
51c1a580 | 8887 | "Recovery failed. Power cycle needed\n"); |
95c6c616 AE |
8888 | /* Disconnect this device */ |
8889 | netif_device_detach(bp->dev); | |
8890 | /* Shut down the power */ | |
8891 | bnx2x_set_power_state( | |
8892 | bp, PCI_D3hot); | |
8893 | smp_mb(); | |
8894 | } else { | |
c9ee9206 VZ |
8895 | bp->recovery_state = |
8896 | BNX2X_RECOVERY_DONE; | |
7a752993 | 8897 | error_recovered++; |
c9ee9206 VZ |
8898 | smp_mb(); |
8899 | } | |
7a752993 AE |
8900 | bp->eth_stats.recoverable_error = |
8901 | error_recovered; | |
8902 | bp->eth_stats.unrecoverable_error = | |
8903 | error_unrecovered; | |
c9ee9206 | 8904 | |
72fd0718 VZ |
8905 | return; |
8906 | } | |
8907 | } | |
8908 | default: | |
8909 | return; | |
8910 | } | |
8911 | } | |
8912 | } | |
8913 | ||
56ad3152 MS |
8914 | static int bnx2x_close(struct net_device *dev); |
8915 | ||
72fd0718 VZ |
8916 | /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is |
8917 | * scheduled on a general queue in order to prevent a dead lock. | |
8918 | */ | |
7be08a72 | 8919 | static void bnx2x_sp_rtnl_task(struct work_struct *work) |
34f80b04 | 8920 | { |
7be08a72 | 8921 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); |
34f80b04 EG |
8922 | |
8923 | rtnl_lock(); | |
8924 | ||
8925 | if (!netif_running(bp->dev)) | |
7be08a72 AE |
8926 | goto sp_rtnl_exit; |
8927 | ||
8928 | /* if stop on error is defined no recovery flows should be executed */ | |
8929 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 8930 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" |
7be08a72 | 8931 | "you will need to reboot when done\n"); |
b1fb8740 | 8932 | goto sp_rtnl_not_reset; |
7be08a72 | 8933 | #endif |
34f80b04 | 8934 | |
7be08a72 AE |
8935 | if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { |
8936 | /* | |
b1fb8740 VZ |
8937 | * Clear all pending SP commands as we are going to reset the |
8938 | * function anyway. | |
7be08a72 | 8939 | */ |
b1fb8740 VZ |
8940 | bp->sp_rtnl_state = 0; |
8941 | smp_mb(); | |
8942 | ||
72fd0718 | 8943 | bnx2x_parity_recover(bp); |
b1fb8740 VZ |
8944 | |
8945 | goto sp_rtnl_exit; | |
8946 | } | |
8947 | ||
8948 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { | |
8949 | /* | |
8950 | * Clear all pending SP commands as we are going to reset the | |
8951 | * function anyway. | |
8952 | */ | |
8953 | bp->sp_rtnl_state = 0; | |
8954 | smp_mb(); | |
8955 | ||
72fd0718 VZ |
8956 | bnx2x_nic_unload(bp, UNLOAD_NORMAL); |
8957 | bnx2x_nic_load(bp, LOAD_NORMAL); | |
b1fb8740 VZ |
8958 | |
8959 | goto sp_rtnl_exit; | |
72fd0718 | 8960 | } |
b1fb8740 VZ |
8961 | #ifdef BNX2X_STOP_ON_ERROR |
8962 | sp_rtnl_not_reset: | |
8963 | #endif | |
8964 | if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) | |
8965 | bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); | |
a3348722 BW |
8966 | if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) |
8967 | bnx2x_after_function_update(bp); | |
8304859a AE |
8968 | /* |
8969 | * in case of fan failure we need to reset id if the "stop on error" | |
8970 | * debug flag is set, since we trying to prevent permanent overheating | |
8971 | * damage | |
8972 | */ | |
8973 | if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { | |
51c1a580 | 8974 | DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); |
8304859a AE |
8975 | netif_device_detach(bp->dev); |
8976 | bnx2x_close(bp->dev); | |
8977 | } | |
8978 | ||
7be08a72 | 8979 | sp_rtnl_exit: |
34f80b04 EG |
8980 | rtnl_unlock(); |
8981 | } | |
8982 | ||
a2fbb9ea ET |
8983 | /* end of nic load/unload */ |
8984 | ||
3deb8167 YR |
8985 | static void bnx2x_period_task(struct work_struct *work) |
8986 | { | |
8987 | struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); | |
8988 | ||
8989 | if (!netif_running(bp->dev)) | |
8990 | goto period_task_exit; | |
8991 | ||
8992 | if (CHIP_REV_IS_SLOW(bp)) { | |
8993 | BNX2X_ERR("period task called on emulation, ignoring\n"); | |
8994 | goto period_task_exit; | |
8995 | } | |
8996 | ||
8997 | bnx2x_acquire_phy_lock(bp); | |
8998 | /* | |
8999 | * The barrier is needed to ensure the ordering between the writing to | |
9000 | * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and | |
9001 | * the reading here. | |
9002 | */ | |
9003 | smp_mb(); | |
9004 | if (bp->port.pmf) { | |
9005 | bnx2x_period_func(&bp->link_params, &bp->link_vars); | |
9006 | ||
9007 | /* Re-queue task in 1 sec */ | |
9008 | queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); | |
9009 | } | |
9010 | ||
9011 | bnx2x_release_phy_lock(bp); | |
9012 | period_task_exit: | |
9013 | return; | |
9014 | } | |
9015 | ||
a2fbb9ea ET |
9016 | /* |
9017 | * Init service functions | |
9018 | */ | |
9019 | ||
8d96286a | 9020 | static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) |
f2e0899f DK |
9021 | { |
9022 | u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
9023 | u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; | |
9024 | return base + (BP_ABS_FUNC(bp)) * stride; | |
f1ef27ef EG |
9025 | } |
9026 | ||
f2e0899f | 9027 | static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) |
f1ef27ef | 9028 | { |
f2e0899f | 9029 | u32 reg = bnx2x_get_pretend_reg(bp); |
f1ef27ef EG |
9030 | |
9031 | /* Flush all outstanding writes */ | |
9032 | mmiowb(); | |
9033 | ||
9034 | /* Pretend to be function 0 */ | |
9035 | REG_WR(bp, reg, 0); | |
f2e0899f | 9036 | REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ |
f1ef27ef EG |
9037 | |
9038 | /* From now we are in the "like-E1" mode */ | |
9039 | bnx2x_int_disable(bp); | |
9040 | ||
9041 | /* Flush all outstanding writes */ | |
9042 | mmiowb(); | |
9043 | ||
f2e0899f DK |
9044 | /* Restore the original function */ |
9045 | REG_WR(bp, reg, BP_ABS_FUNC(bp)); | |
9046 | REG_RD(bp, reg); | |
f1ef27ef EG |
9047 | } |
9048 | ||
f2e0899f | 9049 | static inline void bnx2x_undi_int_disable(struct bnx2x *bp) |
f1ef27ef | 9050 | { |
f2e0899f | 9051 | if (CHIP_IS_E1(bp)) |
f1ef27ef | 9052 | bnx2x_int_disable(bp); |
f2e0899f DK |
9053 | else |
9054 | bnx2x_undi_int_disable_e1h(bp); | |
f1ef27ef EG |
9055 | } |
9056 | ||
452427b0 | 9057 | static void __devinit bnx2x_prev_unload_close_mac(struct bnx2x *bp) |
34f80b04 | 9058 | { |
452427b0 YM |
9059 | u32 val, base_addr, offset, mask, reset_reg; |
9060 | bool mac_stopped = false; | |
9061 | u8 port = BP_PORT(bp); | |
34f80b04 | 9062 | |
452427b0 | 9063 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); |
f16da43b | 9064 | |
452427b0 YM |
9065 | if (!CHIP_IS_E3(bp)) { |
9066 | val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); | |
9067 | mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; | |
9068 | if ((mask & reset_reg) && val) { | |
9069 | u32 wb_data[2]; | |
9070 | BNX2X_DEV_INFO("Disable bmac Rx\n"); | |
9071 | base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM | |
9072 | : NIG_REG_INGRESS_BMAC0_MEM; | |
9073 | offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL | |
9074 | : BIGMAC_REGISTER_BMAC_CONTROL; | |
7a06a122 | 9075 | |
452427b0 YM |
9076 | /* |
9077 | * use rd/wr since we cannot use dmae. This is safe | |
9078 | * since MCP won't access the bus due to the request | |
9079 | * to unload, and no function on the path can be | |
9080 | * loaded at this time. | |
9081 | */ | |
9082 | wb_data[0] = REG_RD(bp, base_addr + offset); | |
9083 | wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); | |
9084 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; | |
9085 | REG_WR(bp, base_addr + offset, wb_data[0]); | |
9086 | REG_WR(bp, base_addr + offset + 0x4, wb_data[1]); | |
9087 | ||
9088 | } | |
9089 | BNX2X_DEV_INFO("Disable emac Rx\n"); | |
9090 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0); | |
9091 | ||
9092 | mac_stopped = true; | |
9093 | } else { | |
9094 | if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { | |
9095 | BNX2X_DEV_INFO("Disable xmac Rx\n"); | |
9096 | base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
9097 | val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); | |
9098 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
9099 | val & ~(1 << 1)); | |
9100 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
9101 | val | (1 << 1)); | |
9102 | REG_WR(bp, base_addr + XMAC_REG_CTRL, 0); | |
9103 | mac_stopped = true; | |
9104 | } | |
9105 | mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; | |
9106 | if (mask & reset_reg) { | |
9107 | BNX2X_DEV_INFO("Disable umac Rx\n"); | |
9108 | base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
9109 | REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0); | |
9110 | mac_stopped = true; | |
9111 | } | |
9112 | } | |
9113 | ||
9114 | if (mac_stopped) | |
9115 | msleep(20); | |
9116 | ||
9117 | } | |
9118 | ||
9119 | #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) | |
9120 | #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) | |
9121 | #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) | |
9122 | #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) | |
9123 | ||
9124 | static void __devinit bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, | |
9125 | u8 inc) | |
9126 | { | |
9127 | u16 rcq, bd; | |
9128 | u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port)); | |
9129 | ||
9130 | rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; | |
9131 | bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; | |
9132 | ||
9133 | tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); | |
9134 | REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg); | |
9135 | ||
9136 | BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n", | |
9137 | port, bd, rcq); | |
9138 | } | |
9139 | ||
9140 | static int __devinit bnx2x_prev_mcp_done(struct bnx2x *bp) | |
9141 | { | |
9142 | u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
9143 | if (!rc) { | |
9144 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9145 | return -EBUSY; | |
9146 | } | |
9147 | ||
9148 | return 0; | |
9149 | } | |
9150 | ||
9151 | static bool __devinit bnx2x_prev_is_path_marked(struct bnx2x *bp) | |
9152 | { | |
9153 | struct bnx2x_prev_path_list *tmp_list; | |
9154 | int rc = false; | |
9155 | ||
9156 | if (down_trylock(&bnx2x_prev_sem)) | |
9157 | return false; | |
9158 | ||
9159 | list_for_each_entry(tmp_list, &bnx2x_prev_list, list) { | |
9160 | if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && | |
9161 | bp->pdev->bus->number == tmp_list->bus && | |
9162 | BP_PATH(bp) == tmp_list->path) { | |
9163 | rc = true; | |
9164 | BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", | |
9165 | BP_PATH(bp)); | |
9166 | break; | |
9167 | } | |
9168 | } | |
9169 | ||
9170 | up(&bnx2x_prev_sem); | |
9171 | ||
9172 | return rc; | |
9173 | } | |
9174 | ||
9175 | static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp) | |
9176 | { | |
9177 | struct bnx2x_prev_path_list *tmp_list; | |
9178 | int rc; | |
9179 | ||
9180 | tmp_list = (struct bnx2x_prev_path_list *) | |
9181 | kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); | |
9182 | if (!tmp_list) { | |
9183 | BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); | |
9184 | return -ENOMEM; | |
9185 | } | |
9186 | ||
9187 | tmp_list->bus = bp->pdev->bus->number; | |
9188 | tmp_list->slot = PCI_SLOT(bp->pdev->devfn); | |
9189 | tmp_list->path = BP_PATH(bp); | |
9190 | ||
9191 | rc = down_interruptible(&bnx2x_prev_sem); | |
9192 | if (rc) { | |
9193 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
9194 | kfree(tmp_list); | |
9195 | } else { | |
9196 | BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n", | |
9197 | BP_PATH(bp)); | |
9198 | list_add(&tmp_list->list, &bnx2x_prev_list); | |
9199 | up(&bnx2x_prev_sem); | |
9200 | } | |
9201 | ||
9202 | return rc; | |
9203 | } | |
9204 | ||
9205 | static bool __devinit bnx2x_can_flr(struct bnx2x *bp) | |
9206 | { | |
9207 | int pos; | |
9208 | u32 cap; | |
9209 | struct pci_dev *dev = bp->pdev; | |
9210 | ||
9211 | pos = pci_pcie_cap(dev); | |
9212 | if (!pos) | |
9213 | return false; | |
9214 | ||
9215 | pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap); | |
9216 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | |
9217 | return false; | |
9218 | ||
9219 | return true; | |
9220 | } | |
9221 | ||
9222 | static int __devinit bnx2x_do_flr(struct bnx2x *bp) | |
9223 | { | |
9224 | int i, pos; | |
9225 | u16 status; | |
9226 | struct pci_dev *dev = bp->pdev; | |
9227 | ||
9228 | /* probe the capability first */ | |
9229 | if (bnx2x_can_flr(bp)) | |
9230 | return -ENOTTY; | |
9231 | ||
9232 | pos = pci_pcie_cap(dev); | |
9233 | if (!pos) | |
9234 | return -ENOTTY; | |
9235 | ||
9236 | /* Wait for Transaction Pending bit clean */ | |
9237 | for (i = 0; i < 4; i++) { | |
9238 | if (i) | |
9239 | msleep((1 << (i - 1)) * 100); | |
9240 | ||
9241 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); | |
9242 | if (!(status & PCI_EXP_DEVSTA_TRPND)) | |
9243 | goto clear; | |
9244 | } | |
9245 | ||
9246 | dev_err(&dev->dev, | |
9247 | "transaction is not cleared; proceeding with reset anyway\n"); | |
9248 | ||
9249 | clear: | |
9250 | if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { | |
9251 | BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", | |
9252 | bp->common.bc_ver); | |
9253 | return -EINVAL; | |
9254 | } | |
9255 | ||
9256 | bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); | |
9257 | ||
9258 | return 0; | |
9259 | } | |
9260 | ||
9261 | static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp) | |
9262 | { | |
9263 | int rc; | |
9264 | ||
9265 | BNX2X_DEV_INFO("Uncommon unload Flow\n"); | |
9266 | ||
9267 | /* Test if previous unload process was already finished for this path */ | |
9268 | if (bnx2x_prev_is_path_marked(bp)) | |
9269 | return bnx2x_prev_mcp_done(bp); | |
9270 | ||
9271 | /* If function has FLR capabilities, and existing FW version matches | |
9272 | * the one required, then FLR will be sufficient to clean any residue | |
9273 | * left by previous driver | |
9274 | */ | |
9275 | if (bnx2x_test_firmware_version(bp, false) && bnx2x_can_flr(bp)) | |
9276 | return bnx2x_do_flr(bp); | |
9277 | ||
9278 | /* Close the MCP request, return failure*/ | |
9279 | rc = bnx2x_prev_mcp_done(bp); | |
9280 | if (!rc) | |
9281 | rc = BNX2X_PREV_WAIT_NEEDED; | |
9282 | ||
9283 | return rc; | |
9284 | } | |
9285 | ||
9286 | static int __devinit bnx2x_prev_unload_common(struct bnx2x *bp) | |
9287 | { | |
9288 | u32 reset_reg, tmp_reg = 0, rc; | |
9289 | /* It is possible a previous function received 'common' answer, | |
9290 | * but hasn't loaded yet, therefore creating a scenario of | |
9291 | * multiple functions receiving 'common' on the same path. | |
9292 | */ | |
9293 | BNX2X_DEV_INFO("Common unload Flow\n"); | |
9294 | ||
9295 | if (bnx2x_prev_is_path_marked(bp)) | |
9296 | return bnx2x_prev_mcp_done(bp); | |
9297 | ||
9298 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); | |
9299 | ||
9300 | /* Reset should be performed after BRB is emptied */ | |
9301 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { | |
9302 | u32 timer_count = 1000; | |
9303 | bool prev_undi = false; | |
9304 | ||
9305 | /* Close the MAC Rx to prevent BRB from filling up */ | |
9306 | bnx2x_prev_unload_close_mac(bp); | |
9307 | ||
9308 | /* Check if the UNDI driver was previously loaded | |
34f80b04 EG |
9309 | * UNDI driver initializes CID offset for normal bell to 0x7 |
9310 | */ | |
452427b0 YM |
9311 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); |
9312 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { | |
9313 | tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST); | |
9314 | if (tmp_reg == 0x7) { | |
9315 | BNX2X_DEV_INFO("UNDI previously loaded\n"); | |
9316 | prev_undi = true; | |
9317 | /* clear the UNDI indication */ | |
9318 | REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); | |
34f80b04 | 9319 | } |
452427b0 YM |
9320 | } |
9321 | /* wait until BRB is empty */ | |
9322 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); | |
9323 | while (timer_count) { | |
9324 | u32 prev_brb = tmp_reg; | |
34f80b04 | 9325 | |
452427b0 YM |
9326 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); |
9327 | if (!tmp_reg) | |
9328 | break; | |
619c5cb6 | 9329 | |
452427b0 | 9330 | BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); |
619c5cb6 | 9331 | |
452427b0 YM |
9332 | /* reset timer as long as BRB actually gets emptied */ |
9333 | if (prev_brb > tmp_reg) | |
9334 | timer_count = 1000; | |
9335 | else | |
9336 | timer_count--; | |
da5a662a | 9337 | |
452427b0 YM |
9338 | /* If UNDI resides in memory, manually increment it */ |
9339 | if (prev_undi) | |
9340 | bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1); | |
da5a662a | 9341 | |
452427b0 | 9342 | udelay(10); |
7a06a122 | 9343 | } |
452427b0 YM |
9344 | |
9345 | if (!timer_count) | |
9346 | BNX2X_ERR("Failed to empty BRB, hope for the best\n"); | |
9347 | ||
34f80b04 | 9348 | } |
f16da43b | 9349 | |
452427b0 YM |
9350 | /* No packets are in the pipeline, path is ready for reset */ |
9351 | bnx2x_reset_common(bp); | |
9352 | ||
9353 | rc = bnx2x_prev_mark_path(bp); | |
9354 | if (rc) { | |
9355 | bnx2x_prev_mcp_done(bp); | |
9356 | return rc; | |
9357 | } | |
9358 | ||
9359 | return bnx2x_prev_mcp_done(bp); | |
9360 | } | |
9361 | ||
9362 | static int __devinit bnx2x_prev_unload(struct bnx2x *bp) | |
9363 | { | |
9364 | int time_counter = 10; | |
9365 | u32 rc, fw, hw_lock_reg, hw_lock_val; | |
9366 | BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); | |
9367 | ||
9368 | /* Release previously held locks */ | |
9369 | hw_lock_reg = (BP_FUNC(bp) <= 5) ? | |
9370 | (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : | |
9371 | (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); | |
9372 | ||
9373 | hw_lock_val = (REG_RD(bp, hw_lock_reg)); | |
9374 | if (hw_lock_val) { | |
9375 | if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { | |
9376 | BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); | |
9377 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
9378 | (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); | |
9379 | } | |
9380 | ||
9381 | BNX2X_DEV_INFO("Release Previously held hw lock\n"); | |
9382 | REG_WR(bp, hw_lock_reg, 0xffffffff); | |
9383 | } else | |
9384 | BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); | |
9385 | ||
9386 | if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { | |
9387 | BNX2X_DEV_INFO("Release previously held alr\n"); | |
9388 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); | |
9389 | } | |
9390 | ||
9391 | ||
9392 | do { | |
9393 | /* Lock MCP using an unload request */ | |
9394 | fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); | |
9395 | if (!fw) { | |
9396 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9397 | rc = -EBUSY; | |
9398 | break; | |
9399 | } | |
9400 | ||
9401 | if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) { | |
9402 | rc = bnx2x_prev_unload_common(bp); | |
9403 | break; | |
9404 | } | |
9405 | ||
9406 | /* non-common reply from MCP night require looping */ | |
9407 | rc = bnx2x_prev_unload_uncommon(bp); | |
9408 | if (rc != BNX2X_PREV_WAIT_NEEDED) | |
9409 | break; | |
9410 | ||
9411 | msleep(20); | |
9412 | } while (--time_counter); | |
9413 | ||
9414 | if (!time_counter || rc) { | |
9415 | BNX2X_ERR("Failed unloading previous driver, aborting\n"); | |
9416 | rc = -EBUSY; | |
9417 | } | |
9418 | ||
9419 | BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); | |
9420 | ||
9421 | return rc; | |
34f80b04 EG |
9422 | } |
9423 | ||
9424 | static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) | |
9425 | { | |
1d187b34 | 9426 | u32 val, val2, val3, val4, id, boot_mode; |
72ce58c3 | 9427 | u16 pmc; |
34f80b04 EG |
9428 | |
9429 | /* Get the chip revision id and number. */ | |
9430 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | |
9431 | val = REG_RD(bp, MISC_REG_CHIP_NUM); | |
9432 | id = ((val & 0xffff) << 16); | |
9433 | val = REG_RD(bp, MISC_REG_CHIP_REV); | |
9434 | id |= ((val & 0xf) << 12); | |
9435 | val = REG_RD(bp, MISC_REG_CHIP_METAL); | |
9436 | id |= ((val & 0xff) << 4); | |
5a40e08e | 9437 | val = REG_RD(bp, MISC_REG_BOND_ID); |
34f80b04 EG |
9438 | id |= (val & 0xf); |
9439 | bp->common.chip_id = id; | |
523224a3 | 9440 | |
7e8e02df BW |
9441 | /* force 57811 according to MISC register */ |
9442 | if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { | |
9443 | if (CHIP_IS_57810(bp)) | |
9444 | bp->common.chip_id = (CHIP_NUM_57811 << 16) | | |
9445 | (bp->common.chip_id & 0x0000FFFF); | |
9446 | else if (CHIP_IS_57810_MF(bp)) | |
9447 | bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | | |
9448 | (bp->common.chip_id & 0x0000FFFF); | |
9449 | bp->common.chip_id |= 0x1; | |
9450 | } | |
9451 | ||
523224a3 DK |
9452 | /* Set doorbell size */ |
9453 | bp->db_size = (1 << BNX2X_DB_SHIFT); | |
9454 | ||
619c5cb6 | 9455 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
9456 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
9457 | if ((val & 1) == 0) | |
9458 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
9459 | else | |
9460 | val = (val >> 1) & 1; | |
9461 | BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : | |
9462 | "2_PORT_MODE"); | |
9463 | bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : | |
9464 | CHIP_2_PORT_MODE; | |
9465 | ||
9466 | if (CHIP_MODE_IS_4_PORT(bp)) | |
9467 | bp->pfid = (bp->pf_num >> 1); /* 0..3 */ | |
9468 | else | |
9469 | bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ | |
9470 | } else { | |
9471 | bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ | |
9472 | bp->pfid = bp->pf_num; /* 0..7 */ | |
9473 | } | |
9474 | ||
51c1a580 MS |
9475 | BNX2X_DEV_INFO("pf_id: %x", bp->pfid); |
9476 | ||
f2e0899f DK |
9477 | bp->link_params.chip_id = bp->common.chip_id; |
9478 | BNX2X_DEV_INFO("chip ID is 0x%x\n", id); | |
523224a3 | 9479 | |
1c06328c EG |
9480 | val = (REG_RD(bp, 0x2874) & 0x55); |
9481 | if ((bp->common.chip_id & 0x1) || | |
9482 | (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { | |
9483 | bp->flags |= ONE_PORT_FLAG; | |
9484 | BNX2X_DEV_INFO("single port device\n"); | |
9485 | } | |
9486 | ||
34f80b04 | 9487 | val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); |
754a2f52 | 9488 | bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << |
34f80b04 EG |
9489 | (val & MCPR_NVM_CFG4_FLASH_SIZE)); |
9490 | BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", | |
9491 | bp->common.flash_size, bp->common.flash_size); | |
9492 | ||
1b6e2ceb DK |
9493 | bnx2x_init_shmem(bp); |
9494 | ||
619c5cb6 VZ |
9495 | |
9496 | ||
f2e0899f DK |
9497 | bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? |
9498 | MISC_REG_GENERIC_CR_1 : | |
9499 | MISC_REG_GENERIC_CR_0)); | |
1b6e2ceb | 9500 | |
34f80b04 | 9501 | bp->link_params.shmem_base = bp->common.shmem_base; |
a22f0788 | 9502 | bp->link_params.shmem2_base = bp->common.shmem2_base; |
2691d51d EG |
9503 | BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", |
9504 | bp->common.shmem_base, bp->common.shmem2_base); | |
34f80b04 | 9505 | |
f2e0899f | 9506 | if (!bp->common.shmem_base) { |
34f80b04 EG |
9507 | BNX2X_DEV_INFO("MCP not active\n"); |
9508 | bp->flags |= NO_MCP_FLAG; | |
9509 | return; | |
9510 | } | |
9511 | ||
34f80b04 | 9512 | bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
35b19ba5 | 9513 | BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); |
34f80b04 EG |
9514 | |
9515 | bp->link_params.hw_led_mode = ((bp->common.hw_config & | |
9516 | SHARED_HW_CFG_LED_MODE_MASK) >> | |
9517 | SHARED_HW_CFG_LED_MODE_SHIFT); | |
9518 | ||
c2c8b03e EG |
9519 | bp->link_params.feature_config_flags = 0; |
9520 | val = SHMEM_RD(bp, dev_info.shared_feature_config.config); | |
9521 | if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) | |
9522 | bp->link_params.feature_config_flags |= | |
9523 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
9524 | else | |
9525 | bp->link_params.feature_config_flags &= | |
9526 | ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
9527 | ||
34f80b04 EG |
9528 | val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; |
9529 | bp->common.bc_ver = val; | |
9530 | BNX2X_DEV_INFO("bc_ver %X\n", val); | |
9531 | if (val < BNX2X_BC_VER) { | |
9532 | /* for now only warn | |
9533 | * later we might need to enforce this */ | |
51c1a580 MS |
9534 | BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", |
9535 | BNX2X_BC_VER, val); | |
34f80b04 | 9536 | } |
4d295db0 | 9537 | bp->link_params.feature_config_flags |= |
a22f0788 | 9538 | (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? |
f85582f8 DK |
9539 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; |
9540 | ||
a22f0788 YR |
9541 | bp->link_params.feature_config_flags |= |
9542 | (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? | |
9543 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; | |
a3348722 BW |
9544 | bp->link_params.feature_config_flags |= |
9545 | (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? | |
9546 | FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; | |
85242eea YR |
9547 | bp->link_params.feature_config_flags |= |
9548 | (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? | |
9549 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; | |
0e898dd7 BW |
9550 | bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? |
9551 | BC_SUPPORTS_PFC_STATS : 0; | |
85242eea | 9552 | |
1d187b34 BW |
9553 | boot_mode = SHMEM_RD(bp, |
9554 | dev_info.port_feature_config[BP_PORT(bp)].mba_config) & | |
9555 | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; | |
9556 | switch (boot_mode) { | |
9557 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: | |
9558 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; | |
9559 | break; | |
9560 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: | |
9561 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; | |
9562 | break; | |
9563 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: | |
9564 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; | |
9565 | break; | |
9566 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: | |
9567 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; | |
9568 | break; | |
9569 | } | |
9570 | ||
f9a3ebbe DK |
9571 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); |
9572 | bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; | |
9573 | ||
72ce58c3 | 9574 | BNX2X_DEV_INFO("%sWoL capable\n", |
f5372251 | 9575 | (bp->flags & NO_WOL_FLAG) ? "not " : ""); |
34f80b04 EG |
9576 | |
9577 | val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); | |
9578 | val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); | |
9579 | val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); | |
9580 | val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); | |
9581 | ||
cdaa7cb8 VZ |
9582 | dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", |
9583 | val, val2, val3, val4); | |
34f80b04 EG |
9584 | } |
9585 | ||
f2e0899f DK |
9586 | #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) |
9587 | #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) | |
9588 | ||
9589 | static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) | |
9590 | { | |
9591 | int pfid = BP_FUNC(bp); | |
f2e0899f DK |
9592 | int igu_sb_id; |
9593 | u32 val; | |
6383c0b3 | 9594 | u8 fid, igu_sb_cnt = 0; |
f2e0899f DK |
9595 | |
9596 | bp->igu_base_sb = 0xff; | |
f2e0899f | 9597 | if (CHIP_INT_MODE_IS_BC(bp)) { |
3395a033 | 9598 | int vn = BP_VN(bp); |
6383c0b3 | 9599 | igu_sb_cnt = bp->igu_sb_cnt; |
f2e0899f DK |
9600 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
9601 | FP_SB_MAX_E1x; | |
9602 | ||
9603 | bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + | |
9604 | (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); | |
9605 | ||
9606 | return; | |
9607 | } | |
9608 | ||
9609 | /* IGU in normal mode - read CAM */ | |
9610 | for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; | |
9611 | igu_sb_id++) { | |
9612 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); | |
9613 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) | |
9614 | continue; | |
9615 | fid = IGU_FID(val); | |
9616 | if ((fid & IGU_FID_ENCODE_IS_PF)) { | |
9617 | if ((fid & IGU_FID_PF_NUM_MASK) != pfid) | |
9618 | continue; | |
9619 | if (IGU_VEC(val) == 0) | |
9620 | /* default status block */ | |
9621 | bp->igu_dsb_id = igu_sb_id; | |
9622 | else { | |
9623 | if (bp->igu_base_sb == 0xff) | |
9624 | bp->igu_base_sb = igu_sb_id; | |
6383c0b3 | 9625 | igu_sb_cnt++; |
f2e0899f DK |
9626 | } |
9627 | } | |
9628 | } | |
619c5cb6 | 9629 | |
6383c0b3 AE |
9630 | #ifdef CONFIG_PCI_MSI |
9631 | /* | |
9632 | * It's expected that number of CAM entries for this functions is equal | |
9633 | * to the number evaluated based on the MSI-X table size. We want a | |
9634 | * harsh warning if these values are different! | |
619c5cb6 | 9635 | */ |
6383c0b3 AE |
9636 | WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); |
9637 | #endif | |
619c5cb6 | 9638 | |
6383c0b3 | 9639 | if (igu_sb_cnt == 0) |
f2e0899f DK |
9640 | BNX2X_ERR("CAM configuration error\n"); |
9641 | } | |
9642 | ||
34f80b04 EG |
9643 | static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, |
9644 | u32 switch_cfg) | |
a2fbb9ea | 9645 | { |
a22f0788 YR |
9646 | int cfg_size = 0, idx, port = BP_PORT(bp); |
9647 | ||
9648 | /* Aggregation of supported attributes of all external phys */ | |
9649 | bp->port.supported[0] = 0; | |
9650 | bp->port.supported[1] = 0; | |
b7737c9b YR |
9651 | switch (bp->link_params.num_phys) { |
9652 | case 1: | |
a22f0788 YR |
9653 | bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; |
9654 | cfg_size = 1; | |
9655 | break; | |
b7737c9b | 9656 | case 2: |
a22f0788 YR |
9657 | bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; |
9658 | cfg_size = 1; | |
9659 | break; | |
9660 | case 3: | |
9661 | if (bp->link_params.multi_phy_config & | |
9662 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { | |
9663 | bp->port.supported[1] = | |
9664 | bp->link_params.phy[EXT_PHY1].supported; | |
9665 | bp->port.supported[0] = | |
9666 | bp->link_params.phy[EXT_PHY2].supported; | |
9667 | } else { | |
9668 | bp->port.supported[0] = | |
9669 | bp->link_params.phy[EXT_PHY1].supported; | |
9670 | bp->port.supported[1] = | |
9671 | bp->link_params.phy[EXT_PHY2].supported; | |
9672 | } | |
9673 | cfg_size = 2; | |
9674 | break; | |
b7737c9b | 9675 | } |
a2fbb9ea | 9676 | |
a22f0788 | 9677 | if (!(bp->port.supported[0] || bp->port.supported[1])) { |
51c1a580 | 9678 | BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", |
b7737c9b | 9679 | SHMEM_RD(bp, |
a22f0788 YR |
9680 | dev_info.port_hw_config[port].external_phy_config), |
9681 | SHMEM_RD(bp, | |
9682 | dev_info.port_hw_config[port].external_phy_config2)); | |
a2fbb9ea | 9683 | return; |
f85582f8 | 9684 | } |
a2fbb9ea | 9685 | |
619c5cb6 VZ |
9686 | if (CHIP_IS_E3(bp)) |
9687 | bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); | |
9688 | else { | |
9689 | switch (switch_cfg) { | |
9690 | case SWITCH_CFG_1G: | |
9691 | bp->port.phy_addr = REG_RD( | |
9692 | bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); | |
9693 | break; | |
9694 | case SWITCH_CFG_10G: | |
9695 | bp->port.phy_addr = REG_RD( | |
9696 | bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); | |
9697 | break; | |
9698 | default: | |
9699 | BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", | |
9700 | bp->port.link_config[0]); | |
9701 | return; | |
9702 | } | |
a2fbb9ea | 9703 | } |
619c5cb6 | 9704 | BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); |
a22f0788 YR |
9705 | /* mask what we support according to speed_cap_mask per configuration */ |
9706 | for (idx = 0; idx < cfg_size; idx++) { | |
9707 | if (!(bp->link_params.speed_cap_mask[idx] & | |
c18487ee | 9708 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) |
a22f0788 | 9709 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; |
a2fbb9ea | 9710 | |
a22f0788 | 9711 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9712 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) |
a22f0788 | 9713 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; |
a2fbb9ea | 9714 | |
a22f0788 | 9715 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9716 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) |
a22f0788 | 9717 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; |
a2fbb9ea | 9718 | |
a22f0788 | 9719 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9720 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) |
a22f0788 | 9721 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; |
a2fbb9ea | 9722 | |
a22f0788 | 9723 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9724 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) |
a22f0788 | 9725 | bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | |
f85582f8 | 9726 | SUPPORTED_1000baseT_Full); |
a2fbb9ea | 9727 | |
a22f0788 | 9728 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9729 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
a22f0788 | 9730 | bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; |
a2fbb9ea | 9731 | |
a22f0788 | 9732 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9733 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
a22f0788 YR |
9734 | bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; |
9735 | ||
9736 | } | |
a2fbb9ea | 9737 | |
a22f0788 YR |
9738 | BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], |
9739 | bp->port.supported[1]); | |
a2fbb9ea ET |
9740 | } |
9741 | ||
34f80b04 | 9742 | static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) |
a2fbb9ea | 9743 | { |
a22f0788 YR |
9744 | u32 link_config, idx, cfg_size = 0; |
9745 | bp->port.advertising[0] = 0; | |
9746 | bp->port.advertising[1] = 0; | |
9747 | switch (bp->link_params.num_phys) { | |
9748 | case 1: | |
9749 | case 2: | |
9750 | cfg_size = 1; | |
9751 | break; | |
9752 | case 3: | |
9753 | cfg_size = 2; | |
9754 | break; | |
9755 | } | |
9756 | for (idx = 0; idx < cfg_size; idx++) { | |
9757 | bp->link_params.req_duplex[idx] = DUPLEX_FULL; | |
9758 | link_config = bp->port.link_config[idx]; | |
9759 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
f85582f8 | 9760 | case PORT_FEATURE_LINK_SPEED_AUTO: |
a22f0788 YR |
9761 | if (bp->port.supported[idx] & SUPPORTED_Autoneg) { |
9762 | bp->link_params.req_line_speed[idx] = | |
9763 | SPEED_AUTO_NEG; | |
9764 | bp->port.advertising[idx] |= | |
9765 | bp->port.supported[idx]; | |
10bd1f24 MY |
9766 | if (bp->link_params.phy[EXT_PHY1].type == |
9767 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | |
9768 | bp->port.advertising[idx] |= | |
9769 | (SUPPORTED_100baseT_Half | | |
9770 | SUPPORTED_100baseT_Full); | |
f85582f8 DK |
9771 | } else { |
9772 | /* force 10G, no AN */ | |
a22f0788 YR |
9773 | bp->link_params.req_line_speed[idx] = |
9774 | SPEED_10000; | |
9775 | bp->port.advertising[idx] |= | |
9776 | (ADVERTISED_10000baseT_Full | | |
f85582f8 | 9777 | ADVERTISED_FIBRE); |
a22f0788 | 9778 | continue; |
f85582f8 DK |
9779 | } |
9780 | break; | |
a2fbb9ea | 9781 | |
f85582f8 | 9782 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
a22f0788 YR |
9783 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { |
9784 | bp->link_params.req_line_speed[idx] = | |
9785 | SPEED_10; | |
9786 | bp->port.advertising[idx] |= | |
9787 | (ADVERTISED_10baseT_Full | | |
f85582f8 DK |
9788 | ADVERTISED_TP); |
9789 | } else { | |
51c1a580 | 9790 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 | 9791 | link_config, |
a22f0788 | 9792 | bp->link_params.speed_cap_mask[idx]); |
f85582f8 DK |
9793 | return; |
9794 | } | |
9795 | break; | |
a2fbb9ea | 9796 | |
f85582f8 | 9797 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
a22f0788 YR |
9798 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { |
9799 | bp->link_params.req_line_speed[idx] = | |
9800 | SPEED_10; | |
9801 | bp->link_params.req_duplex[idx] = | |
9802 | DUPLEX_HALF; | |
9803 | bp->port.advertising[idx] |= | |
9804 | (ADVERTISED_10baseT_Half | | |
f85582f8 DK |
9805 | ADVERTISED_TP); |
9806 | } else { | |
51c1a580 | 9807 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
9808 | link_config, |
9809 | bp->link_params.speed_cap_mask[idx]); | |
9810 | return; | |
9811 | } | |
9812 | break; | |
a2fbb9ea | 9813 | |
f85582f8 DK |
9814 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
9815 | if (bp->port.supported[idx] & | |
9816 | SUPPORTED_100baseT_Full) { | |
a22f0788 YR |
9817 | bp->link_params.req_line_speed[idx] = |
9818 | SPEED_100; | |
9819 | bp->port.advertising[idx] |= | |
9820 | (ADVERTISED_100baseT_Full | | |
f85582f8 DK |
9821 | ADVERTISED_TP); |
9822 | } else { | |
51c1a580 | 9823 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
9824 | link_config, |
9825 | bp->link_params.speed_cap_mask[idx]); | |
9826 | return; | |
9827 | } | |
9828 | break; | |
a2fbb9ea | 9829 | |
f85582f8 DK |
9830 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
9831 | if (bp->port.supported[idx] & | |
9832 | SUPPORTED_100baseT_Half) { | |
9833 | bp->link_params.req_line_speed[idx] = | |
9834 | SPEED_100; | |
9835 | bp->link_params.req_duplex[idx] = | |
9836 | DUPLEX_HALF; | |
a22f0788 YR |
9837 | bp->port.advertising[idx] |= |
9838 | (ADVERTISED_100baseT_Half | | |
f85582f8 DK |
9839 | ADVERTISED_TP); |
9840 | } else { | |
51c1a580 | 9841 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
9842 | link_config, |
9843 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
9844 | return; |
9845 | } | |
9846 | break; | |
a2fbb9ea | 9847 | |
f85582f8 | 9848 | case PORT_FEATURE_LINK_SPEED_1G: |
a22f0788 YR |
9849 | if (bp->port.supported[idx] & |
9850 | SUPPORTED_1000baseT_Full) { | |
9851 | bp->link_params.req_line_speed[idx] = | |
9852 | SPEED_1000; | |
9853 | bp->port.advertising[idx] |= | |
9854 | (ADVERTISED_1000baseT_Full | | |
f85582f8 DK |
9855 | ADVERTISED_TP); |
9856 | } else { | |
51c1a580 | 9857 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
9858 | link_config, |
9859 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
9860 | return; |
9861 | } | |
9862 | break; | |
a2fbb9ea | 9863 | |
f85582f8 | 9864 | case PORT_FEATURE_LINK_SPEED_2_5G: |
a22f0788 YR |
9865 | if (bp->port.supported[idx] & |
9866 | SUPPORTED_2500baseX_Full) { | |
9867 | bp->link_params.req_line_speed[idx] = | |
9868 | SPEED_2500; | |
9869 | bp->port.advertising[idx] |= | |
9870 | (ADVERTISED_2500baseX_Full | | |
34f80b04 | 9871 | ADVERTISED_TP); |
f85582f8 | 9872 | } else { |
51c1a580 | 9873 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 9874 | link_config, |
f85582f8 DK |
9875 | bp->link_params.speed_cap_mask[idx]); |
9876 | return; | |
9877 | } | |
9878 | break; | |
a2fbb9ea | 9879 | |
f85582f8 | 9880 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
a22f0788 YR |
9881 | if (bp->port.supported[idx] & |
9882 | SUPPORTED_10000baseT_Full) { | |
9883 | bp->link_params.req_line_speed[idx] = | |
9884 | SPEED_10000; | |
9885 | bp->port.advertising[idx] |= | |
9886 | (ADVERTISED_10000baseT_Full | | |
34f80b04 | 9887 | ADVERTISED_FIBRE); |
f85582f8 | 9888 | } else { |
51c1a580 | 9889 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 9890 | link_config, |
f85582f8 DK |
9891 | bp->link_params.speed_cap_mask[idx]); |
9892 | return; | |
9893 | } | |
9894 | break; | |
3c9ada22 YR |
9895 | case PORT_FEATURE_LINK_SPEED_20G: |
9896 | bp->link_params.req_line_speed[idx] = SPEED_20000; | |
a2fbb9ea | 9897 | |
3c9ada22 | 9898 | break; |
f85582f8 | 9899 | default: |
51c1a580 | 9900 | BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", |
754a2f52 | 9901 | link_config); |
f85582f8 DK |
9902 | bp->link_params.req_line_speed[idx] = |
9903 | SPEED_AUTO_NEG; | |
9904 | bp->port.advertising[idx] = | |
9905 | bp->port.supported[idx]; | |
9906 | break; | |
9907 | } | |
a2fbb9ea | 9908 | |
a22f0788 | 9909 | bp->link_params.req_flow_ctrl[idx] = (link_config & |
34f80b04 | 9910 | PORT_FEATURE_FLOW_CONTROL_MASK); |
a22f0788 YR |
9911 | if ((bp->link_params.req_flow_ctrl[idx] == |
9912 | BNX2X_FLOW_CTRL_AUTO) && | |
9913 | !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { | |
9914 | bp->link_params.req_flow_ctrl[idx] = | |
9915 | BNX2X_FLOW_CTRL_NONE; | |
9916 | } | |
a2fbb9ea | 9917 | |
51c1a580 | 9918 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", |
a22f0788 YR |
9919 | bp->link_params.req_line_speed[idx], |
9920 | bp->link_params.req_duplex[idx], | |
9921 | bp->link_params.req_flow_ctrl[idx], | |
9922 | bp->port.advertising[idx]); | |
9923 | } | |
a2fbb9ea ET |
9924 | } |
9925 | ||
e665bfda MC |
9926 | static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) |
9927 | { | |
9928 | mac_hi = cpu_to_be16(mac_hi); | |
9929 | mac_lo = cpu_to_be32(mac_lo); | |
9930 | memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); | |
9931 | memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); | |
9932 | } | |
9933 | ||
34f80b04 | 9934 | static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) |
a2fbb9ea | 9935 | { |
34f80b04 | 9936 | int port = BP_PORT(bp); |
589abe3a | 9937 | u32 config; |
6f38ad93 | 9938 | u32 ext_phy_type, ext_phy_config; |
a2fbb9ea | 9939 | |
c18487ee | 9940 | bp->link_params.bp = bp; |
34f80b04 | 9941 | bp->link_params.port = port; |
c18487ee | 9942 | |
c18487ee | 9943 | bp->link_params.lane_config = |
a2fbb9ea | 9944 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
4d295db0 | 9945 | |
a22f0788 | 9946 | bp->link_params.speed_cap_mask[0] = |
a2fbb9ea ET |
9947 | SHMEM_RD(bp, |
9948 | dev_info.port_hw_config[port].speed_capability_mask); | |
a22f0788 YR |
9949 | bp->link_params.speed_cap_mask[1] = |
9950 | SHMEM_RD(bp, | |
9951 | dev_info.port_hw_config[port].speed_capability_mask2); | |
9952 | bp->port.link_config[0] = | |
a2fbb9ea ET |
9953 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
9954 | ||
a22f0788 YR |
9955 | bp->port.link_config[1] = |
9956 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); | |
c2c8b03e | 9957 | |
a22f0788 YR |
9958 | bp->link_params.multi_phy_config = |
9959 | SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); | |
3ce2c3f9 EG |
9960 | /* If the device is capable of WoL, set the default state according |
9961 | * to the HW | |
9962 | */ | |
4d295db0 | 9963 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); |
3ce2c3f9 EG |
9964 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
9965 | (config & PORT_FEATURE_WOL_ENABLED)); | |
9966 | ||
51c1a580 | 9967 | BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", |
c18487ee | 9968 | bp->link_params.lane_config, |
a22f0788 YR |
9969 | bp->link_params.speed_cap_mask[0], |
9970 | bp->port.link_config[0]); | |
a2fbb9ea | 9971 | |
a22f0788 | 9972 | bp->link_params.switch_cfg = (bp->port.link_config[0] & |
f85582f8 | 9973 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
b7737c9b | 9974 | bnx2x_phy_probe(&bp->link_params); |
c18487ee | 9975 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
a2fbb9ea ET |
9976 | |
9977 | bnx2x_link_settings_requested(bp); | |
9978 | ||
01cd4528 EG |
9979 | /* |
9980 | * If connected directly, work with the internal PHY, otherwise, work | |
9981 | * with the external PHY | |
9982 | */ | |
b7737c9b YR |
9983 | ext_phy_config = |
9984 | SHMEM_RD(bp, | |
9985 | dev_info.port_hw_config[port].external_phy_config); | |
9986 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
01cd4528 | 9987 | if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
b7737c9b | 9988 | bp->mdio.prtad = bp->port.phy_addr; |
01cd4528 EG |
9989 | |
9990 | else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && | |
9991 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
9992 | bp->mdio.prtad = | |
b7737c9b | 9993 | XGXS_EXT_PHY_ADDR(ext_phy_config); |
5866df6d YR |
9994 | |
9995 | /* | |
9996 | * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) | |
9997 | * In MF mode, it is set to cover self test cases | |
9998 | */ | |
9999 | if (IS_MF(bp)) | |
10000 | bp->port.need_hw_lock = 1; | |
10001 | else | |
10002 | bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, | |
10003 | bp->common.shmem_base, | |
10004 | bp->common.shmem2_base); | |
0793f83f | 10005 | } |
01cd4528 | 10006 | |
b306f5ed | 10007 | void bnx2x_get_iscsi_info(struct bnx2x *bp) |
2ba45142 | 10008 | { |
9e62e912 | 10009 | u32 no_flags = NO_ISCSI_FLAG; |
7185bb33 | 10010 | #ifdef BCM_CNIC |
bf61ee14 | 10011 | int port = BP_PORT(bp); |
bf61ee14 | 10012 | |
2ba45142 | 10013 | u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
bf61ee14 | 10014 | drv_lic_key[port].max_iscsi_conn); |
2ba45142 | 10015 | |
b306f5ed | 10016 | /* Get the number of maximum allowed iSCSI connections */ |
2ba45142 VZ |
10017 | bp->cnic_eth_dev.max_iscsi_conn = |
10018 | (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> | |
10019 | BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; | |
10020 | ||
b306f5ed DK |
10021 | BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", |
10022 | bp->cnic_eth_dev.max_iscsi_conn); | |
10023 | ||
10024 | /* | |
10025 | * If maximum allowed number of connections is zero - | |
10026 | * disable the feature. | |
10027 | */ | |
10028 | if (!bp->cnic_eth_dev.max_iscsi_conn) | |
9e62e912 | 10029 | bp->flags |= no_flags; |
7185bb33 | 10030 | #else |
9e62e912 | 10031 | bp->flags |= no_flags; |
7185bb33 | 10032 | #endif |
b306f5ed DK |
10033 | } |
10034 | ||
9e62e912 DK |
10035 | #ifdef BCM_CNIC |
10036 | static void __devinit bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) | |
10037 | { | |
10038 | /* Port info */ | |
10039 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
10040 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); | |
10041 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
10042 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); | |
10043 | ||
10044 | /* Node info */ | |
10045 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
10046 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); | |
10047 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
10048 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); | |
10049 | } | |
10050 | #endif | |
b306f5ed DK |
10051 | static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp) |
10052 | { | |
7185bb33 | 10053 | #ifdef BCM_CNIC |
b306f5ed DK |
10054 | int port = BP_PORT(bp); |
10055 | int func = BP_ABS_FUNC(bp); | |
10056 | ||
10057 | u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, | |
10058 | drv_lic_key[port].max_fcoe_conn); | |
10059 | ||
10060 | /* Get the number of maximum allowed FCoE connections */ | |
2ba45142 VZ |
10061 | bp->cnic_eth_dev.max_fcoe_conn = |
10062 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> | |
10063 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; | |
10064 | ||
bf61ee14 VZ |
10065 | /* Read the WWN: */ |
10066 | if (!IS_MF(bp)) { | |
10067 | /* Port info */ | |
10068 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
10069 | SHMEM_RD(bp, | |
10070 | dev_info.port_hw_config[port]. | |
10071 | fcoe_wwn_port_name_upper); | |
10072 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
10073 | SHMEM_RD(bp, | |
10074 | dev_info.port_hw_config[port]. | |
10075 | fcoe_wwn_port_name_lower); | |
10076 | ||
10077 | /* Node info */ | |
10078 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
10079 | SHMEM_RD(bp, | |
10080 | dev_info.port_hw_config[port]. | |
10081 | fcoe_wwn_node_name_upper); | |
10082 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
10083 | SHMEM_RD(bp, | |
10084 | dev_info.port_hw_config[port]. | |
10085 | fcoe_wwn_node_name_lower); | |
10086 | } else if (!IS_MF_SD(bp)) { | |
10087 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); | |
10088 | ||
10089 | /* | |
10090 | * Read the WWN info only if the FCoE feature is enabled for | |
10091 | * this function. | |
10092 | */ | |
9e62e912 DK |
10093 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) |
10094 | bnx2x_get_ext_wwn_info(bp, func); | |
10095 | ||
10096 | } else if (IS_MF_FCOE_SD(bp)) | |
10097 | bnx2x_get_ext_wwn_info(bp, func); | |
bf61ee14 | 10098 | |
b306f5ed | 10099 | BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); |
2ba45142 | 10100 | |
bf61ee14 VZ |
10101 | /* |
10102 | * If maximum allowed number of connections is zero - | |
2ba45142 VZ |
10103 | * disable the feature. |
10104 | */ | |
2ba45142 VZ |
10105 | if (!bp->cnic_eth_dev.max_fcoe_conn) |
10106 | bp->flags |= NO_FCOE_FLAG; | |
7185bb33 DK |
10107 | #else |
10108 | bp->flags |= NO_FCOE_FLAG; | |
10109 | #endif | |
2ba45142 | 10110 | } |
b306f5ed DK |
10111 | |
10112 | static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) | |
10113 | { | |
10114 | /* | |
10115 | * iSCSI may be dynamically disabled but reading | |
10116 | * info here we will decrease memory usage by driver | |
10117 | * if the feature is disabled for good | |
10118 | */ | |
10119 | bnx2x_get_iscsi_info(bp); | |
10120 | bnx2x_get_fcoe_info(bp); | |
10121 | } | |
2ba45142 | 10122 | |
0793f83f DK |
10123 | static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) |
10124 | { | |
10125 | u32 val, val2; | |
10126 | int func = BP_ABS_FUNC(bp); | |
10127 | int port = BP_PORT(bp); | |
2ba45142 VZ |
10128 | #ifdef BCM_CNIC |
10129 | u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; | |
10130 | u8 *fip_mac = bp->fip_mac; | |
10131 | #endif | |
0793f83f | 10132 | |
619c5cb6 VZ |
10133 | /* Zero primary MAC configuration */ |
10134 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
10135 | ||
0793f83f DK |
10136 | if (BP_NOMCP(bp)) { |
10137 | BNX2X_ERROR("warning: random MAC workaround active\n"); | |
7ce5d222 | 10138 | eth_hw_addr_random(bp->dev); |
0793f83f DK |
10139 | } else if (IS_MF(bp)) { |
10140 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
10141 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); | |
10142 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && | |
10143 | (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) | |
10144 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
37b091ba MC |
10145 | |
10146 | #ifdef BCM_CNIC | |
614c76df DK |
10147 | /* |
10148 | * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or | |
2ba45142 | 10149 | * FCoE MAC then the appropriate feature should be disabled. |
9e62e912 DK |
10150 | * |
10151 | * In non SD mode features configuration comes from | |
10152 | * struct func_ext_config. | |
2ba45142 | 10153 | */ |
9e62e912 | 10154 | if (!IS_MF_SD(bp)) { |
0793f83f DK |
10155 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); |
10156 | if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { | |
10157 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
10158 | iscsi_mac_addr_upper); | |
10159 | val = MF_CFG_RD(bp, func_ext_config[func]. | |
10160 | iscsi_mac_addr_lower); | |
2ba45142 | 10161 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
0f9dad10 JP |
10162 | BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", |
10163 | iscsi_mac); | |
2ba45142 VZ |
10164 | } else |
10165 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; | |
10166 | ||
10167 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
10168 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
10169 | fcoe_mac_addr_upper); | |
10170 | val = MF_CFG_RD(bp, func_ext_config[func]. | |
10171 | fcoe_mac_addr_lower); | |
2ba45142 | 10172 | bnx2x_set_mac_buf(fip_mac, val, val2); |
614c76df | 10173 | BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n", |
0f9dad10 | 10174 | fip_mac); |
2ba45142 | 10175 | |
2ba45142 VZ |
10176 | } else |
10177 | bp->flags |= NO_FCOE_FLAG; | |
a3348722 BW |
10178 | |
10179 | bp->mf_ext_config = cfg; | |
10180 | ||
9e62e912 DK |
10181 | } else { /* SD MODE */ |
10182 | if (IS_MF_STORAGE_SD(bp)) { | |
10183 | if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { | |
10184 | /* use primary mac as iscsi mac */ | |
10185 | memcpy(iscsi_mac, bp->dev->dev_addr, | |
10186 | ETH_ALEN); | |
10187 | ||
10188 | BNX2X_DEV_INFO("SD ISCSI MODE\n"); | |
10189 | BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", | |
10190 | iscsi_mac); | |
10191 | } else { /* FCoE */ | |
10192 | memcpy(fip_mac, bp->dev->dev_addr, | |
10193 | ETH_ALEN); | |
10194 | BNX2X_DEV_INFO("SD FCoE MODE\n"); | |
10195 | BNX2X_DEV_INFO("Read FIP MAC: %pM\n", | |
10196 | fip_mac); | |
10197 | } | |
614c76df DK |
10198 | /* Zero primary MAC configuration */ |
10199 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
614c76df | 10200 | } |
0793f83f | 10201 | } |
a3348722 BW |
10202 | |
10203 | if (IS_MF_FCOE_AFEX(bp)) | |
10204 | /* use FIP MAC as primary MAC */ | |
10205 | memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); | |
10206 | ||
37b091ba | 10207 | #endif |
0793f83f DK |
10208 | } else { |
10209 | /* in SF read MACs from port configuration */ | |
10210 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
10211 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
10212 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
10213 | ||
10214 | #ifdef BCM_CNIC | |
10215 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
10216 | iscsi_mac_upper); | |
10217 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
10218 | iscsi_mac_lower); | |
2ba45142 | 10219 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
c03bd39c VZ |
10220 | |
10221 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
10222 | fcoe_fip_mac_upper); | |
10223 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
10224 | fcoe_fip_mac_lower); | |
10225 | bnx2x_set_mac_buf(fip_mac, val, val2); | |
0793f83f DK |
10226 | #endif |
10227 | } | |
10228 | ||
10229 | memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); | |
10230 | memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); | |
10231 | ||
ec6ba945 | 10232 | #ifdef BCM_CNIC |
426b9241 DK |
10233 | /* Disable iSCSI if MAC configuration is |
10234 | * invalid. | |
10235 | */ | |
10236 | if (!is_valid_ether_addr(iscsi_mac)) { | |
10237 | bp->flags |= NO_ISCSI_FLAG; | |
10238 | memset(iscsi_mac, 0, ETH_ALEN); | |
10239 | } | |
10240 | ||
10241 | /* Disable FCoE if MAC configuration is | |
10242 | * invalid. | |
10243 | */ | |
10244 | if (!is_valid_ether_addr(fip_mac)) { | |
10245 | bp->flags |= NO_FCOE_FLAG; | |
10246 | memset(bp->fip_mac, 0, ETH_ALEN); | |
10247 | } | |
ec6ba945 | 10248 | #endif |
619c5cb6 | 10249 | |
614c76df | 10250 | if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) |
619c5cb6 | 10251 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
10252 | "bad Ethernet MAC address configuration: %pM\n" |
10253 | "change it manually before bringing up the appropriate network interface\n", | |
0f9dad10 | 10254 | bp->dev->dev_addr); |
51c1a580 MS |
10255 | |
10256 | ||
34f80b04 EG |
10257 | } |
10258 | ||
10259 | static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) | |
10260 | { | |
0793f83f | 10261 | int /*abs*/func = BP_ABS_FUNC(bp); |
b8ee8328 | 10262 | int vn; |
0793f83f | 10263 | u32 val = 0; |
34f80b04 | 10264 | int rc = 0; |
a2fbb9ea | 10265 | |
34f80b04 | 10266 | bnx2x_get_common_hwinfo(bp); |
a2fbb9ea | 10267 | |
6383c0b3 AE |
10268 | /* |
10269 | * initialize IGU parameters | |
10270 | */ | |
f2e0899f DK |
10271 | if (CHIP_IS_E1x(bp)) { |
10272 | bp->common.int_block = INT_BLOCK_HC; | |
10273 | ||
10274 | bp->igu_dsb_id = DEF_SB_IGU_ID; | |
10275 | bp->igu_base_sb = 0; | |
f2e0899f DK |
10276 | } else { |
10277 | bp->common.int_block = INT_BLOCK_IGU; | |
7a06a122 DK |
10278 | |
10279 | /* do not allow device reset during IGU info preocessing */ | |
10280 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); | |
10281 | ||
f2e0899f | 10282 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
619c5cb6 VZ |
10283 | |
10284 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { | |
10285 | int tout = 5000; | |
10286 | ||
10287 | BNX2X_DEV_INFO("FORCING Normal Mode\n"); | |
10288 | ||
10289 | val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); | |
10290 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); | |
10291 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); | |
10292 | ||
10293 | while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
10294 | tout--; | |
10295 | usleep_range(1000, 1000); | |
10296 | } | |
10297 | ||
10298 | if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
10299 | dev_err(&bp->pdev->dev, | |
10300 | "FORCING Normal Mode failed!!!\n"); | |
10301 | return -EPERM; | |
10302 | } | |
10303 | } | |
10304 | ||
f2e0899f | 10305 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
619c5cb6 | 10306 | BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); |
f2e0899f DK |
10307 | bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; |
10308 | } else | |
619c5cb6 | 10309 | BNX2X_DEV_INFO("IGU Normal Mode\n"); |
523224a3 | 10310 | |
f2e0899f DK |
10311 | bnx2x_get_igu_cam_info(bp); |
10312 | ||
7a06a122 | 10313 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
f2e0899f | 10314 | } |
619c5cb6 VZ |
10315 | |
10316 | /* | |
10317 | * set base FW non-default (fast path) status block id, this value is | |
10318 | * used to initialize the fw_sb_id saved on the fp/queue structure to | |
10319 | * determine the id used by the FW. | |
10320 | */ | |
10321 | if (CHIP_IS_E1x(bp)) | |
10322 | bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); | |
10323 | else /* | |
10324 | * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of | |
10325 | * the same queue are indicated on the same IGU SB). So we prefer | |
10326 | * FW and IGU SBs to be the same value. | |
10327 | */ | |
10328 | bp->base_fw_ndsb = bp->igu_base_sb; | |
10329 | ||
10330 | BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" | |
10331 | "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, | |
10332 | bp->igu_sb_cnt, bp->base_fw_ndsb); | |
f2e0899f DK |
10333 | |
10334 | /* | |
10335 | * Initialize MF configuration | |
10336 | */ | |
523224a3 | 10337 | |
fb3bff17 DK |
10338 | bp->mf_ov = 0; |
10339 | bp->mf_mode = 0; | |
3395a033 | 10340 | vn = BP_VN(bp); |
0793f83f | 10341 | |
f2e0899f | 10342 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
619c5cb6 VZ |
10343 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
10344 | bp->common.shmem2_base, SHMEM2_RD(bp, size), | |
10345 | (u32)offsetof(struct shmem2_region, mf_cfg_addr)); | |
10346 | ||
f2e0899f DK |
10347 | if (SHMEM2_HAS(bp, mf_cfg_addr)) |
10348 | bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); | |
10349 | else | |
10350 | bp->common.mf_cfg_base = bp->common.shmem_base + | |
523224a3 DK |
10351 | offsetof(struct shmem_region, func_mb) + |
10352 | E1H_FUNC_MAX * sizeof(struct drv_func_mb); | |
0793f83f DK |
10353 | /* |
10354 | * get mf configuration: | |
25985edc | 10355 | * 1. existence of MF configuration |
0793f83f DK |
10356 | * 2. MAC address must be legal (check only upper bytes) |
10357 | * for Switch-Independent mode; | |
10358 | * OVLAN must be legal for Switch-Dependent mode | |
10359 | * 3. SF_MODE configures specific MF mode | |
10360 | */ | |
10361 | if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
10362 | /* get mf configuration */ | |
10363 | val = SHMEM_RD(bp, | |
10364 | dev_info.shared_feature_config.config); | |
10365 | val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; | |
10366 | ||
10367 | switch (val) { | |
10368 | case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: | |
10369 | val = MF_CFG_RD(bp, func_mf_config[func]. | |
10370 | mac_upper); | |
10371 | /* check for legal mac (upper bytes)*/ | |
10372 | if (val != 0xffff) { | |
10373 | bp->mf_mode = MULTI_FUNCTION_SI; | |
10374 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
10375 | func_mf_config[func].config); | |
10376 | } else | |
51c1a580 | 10377 | BNX2X_DEV_INFO("illegal MAC address for SI\n"); |
0793f83f | 10378 | break; |
a3348722 BW |
10379 | case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: |
10380 | if ((!CHIP_IS_E1x(bp)) && | |
10381 | (MF_CFG_RD(bp, func_mf_config[func]. | |
10382 | mac_upper) != 0xffff) && | |
10383 | (SHMEM2_HAS(bp, | |
10384 | afex_driver_support))) { | |
10385 | bp->mf_mode = MULTI_FUNCTION_AFEX; | |
10386 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
10387 | func_mf_config[func].config); | |
10388 | } else { | |
10389 | BNX2X_DEV_INFO("can not configure afex mode\n"); | |
10390 | } | |
10391 | break; | |
0793f83f DK |
10392 | case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: |
10393 | /* get OV configuration */ | |
10394 | val = MF_CFG_RD(bp, | |
10395 | func_mf_config[FUNC_0].e1hov_tag); | |
10396 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; | |
10397 | ||
10398 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
10399 | bp->mf_mode = MULTI_FUNCTION_SD; | |
10400 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
10401 | func_mf_config[func].config); | |
10402 | } else | |
754a2f52 | 10403 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
0793f83f DK |
10404 | break; |
10405 | default: | |
10406 | /* Unknown configuration: reset mf_config */ | |
10407 | bp->mf_config[vn] = 0; | |
51c1a580 | 10408 | BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); |
0793f83f DK |
10409 | } |
10410 | } | |
a2fbb9ea | 10411 | |
2691d51d | 10412 | BNX2X_DEV_INFO("%s function mode\n", |
fb3bff17 | 10413 | IS_MF(bp) ? "multi" : "single"); |
2691d51d | 10414 | |
0793f83f DK |
10415 | switch (bp->mf_mode) { |
10416 | case MULTI_FUNCTION_SD: | |
10417 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
10418 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2691d51d | 10419 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
fb3bff17 | 10420 | bp->mf_ov = val; |
619c5cb6 VZ |
10421 | bp->path_has_ovlan = true; |
10422 | ||
51c1a580 MS |
10423 | BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", |
10424 | func, bp->mf_ov, bp->mf_ov); | |
2691d51d | 10425 | } else { |
619c5cb6 | 10426 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
10427 | "No valid MF OV for func %d, aborting\n", |
10428 | func); | |
619c5cb6 | 10429 | return -EPERM; |
34f80b04 | 10430 | } |
0793f83f | 10431 | break; |
a3348722 BW |
10432 | case MULTI_FUNCTION_AFEX: |
10433 | BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); | |
10434 | break; | |
0793f83f | 10435 | case MULTI_FUNCTION_SI: |
51c1a580 MS |
10436 | BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", |
10437 | func); | |
0793f83f DK |
10438 | break; |
10439 | default: | |
10440 | if (vn) { | |
619c5cb6 | 10441 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
10442 | "VN %d is in a single function mode, aborting\n", |
10443 | vn); | |
619c5cb6 | 10444 | return -EPERM; |
2691d51d | 10445 | } |
0793f83f | 10446 | break; |
34f80b04 | 10447 | } |
0793f83f | 10448 | |
619c5cb6 VZ |
10449 | /* check if other port on the path needs ovlan: |
10450 | * Since MF configuration is shared between ports | |
10451 | * Possible mixed modes are only | |
10452 | * {SF, SI} {SF, SD} {SD, SF} {SI, SF} | |
10453 | */ | |
10454 | if (CHIP_MODE_IS_4_PORT(bp) && | |
10455 | !bp->path_has_ovlan && | |
10456 | !IS_MF(bp) && | |
10457 | bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
10458 | u8 other_port = !BP_PORT(bp); | |
10459 | u8 other_func = BP_PATH(bp) + 2*other_port; | |
10460 | val = MF_CFG_RD(bp, | |
10461 | func_mf_config[other_func].e1hov_tag); | |
10462 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) | |
10463 | bp->path_has_ovlan = true; | |
10464 | } | |
34f80b04 | 10465 | } |
a2fbb9ea | 10466 | |
f2e0899f DK |
10467 | /* adjust igu_sb_cnt to MF for E1x */ |
10468 | if (CHIP_IS_E1x(bp) && IS_MF(bp)) | |
523224a3 DK |
10469 | bp->igu_sb_cnt /= E1HVN_MAX; |
10470 | ||
619c5cb6 VZ |
10471 | /* port info */ |
10472 | bnx2x_get_port_hwinfo(bp); | |
f2e0899f | 10473 | |
0793f83f DK |
10474 | /* Get MAC addresses */ |
10475 | bnx2x_get_mac_hwinfo(bp); | |
a2fbb9ea | 10476 | |
2ba45142 | 10477 | bnx2x_get_cnic_info(bp); |
2ba45142 | 10478 | |
34f80b04 EG |
10479 | return rc; |
10480 | } | |
10481 | ||
34f24c7f VZ |
10482 | static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) |
10483 | { | |
10484 | int cnt, i, block_end, rodi; | |
fcdf95cb | 10485 | char vpd_start[BNX2X_VPD_LEN+1]; |
34f24c7f VZ |
10486 | char str_id_reg[VENDOR_ID_LEN+1]; |
10487 | char str_id_cap[VENDOR_ID_LEN+1]; | |
fcdf95cb BW |
10488 | char *vpd_data; |
10489 | char *vpd_extended_data = NULL; | |
34f24c7f VZ |
10490 | u8 len; |
10491 | ||
fcdf95cb | 10492 | cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); |
34f24c7f VZ |
10493 | memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); |
10494 | ||
10495 | if (cnt < BNX2X_VPD_LEN) | |
10496 | goto out_not_found; | |
10497 | ||
fcdf95cb BW |
10498 | /* VPD RO tag should be first tag after identifier string, hence |
10499 | * we should be able to find it in first BNX2X_VPD_LEN chars | |
10500 | */ | |
10501 | i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, | |
34f24c7f VZ |
10502 | PCI_VPD_LRDT_RO_DATA); |
10503 | if (i < 0) | |
10504 | goto out_not_found; | |
10505 | ||
34f24c7f | 10506 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + |
fcdf95cb | 10507 | pci_vpd_lrdt_size(&vpd_start[i]); |
34f24c7f VZ |
10508 | |
10509 | i += PCI_VPD_LRDT_TAG_SIZE; | |
10510 | ||
fcdf95cb BW |
10511 | if (block_end > BNX2X_VPD_LEN) { |
10512 | vpd_extended_data = kmalloc(block_end, GFP_KERNEL); | |
10513 | if (vpd_extended_data == NULL) | |
10514 | goto out_not_found; | |
10515 | ||
10516 | /* read rest of vpd image into vpd_extended_data */ | |
10517 | memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); | |
10518 | cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, | |
10519 | block_end - BNX2X_VPD_LEN, | |
10520 | vpd_extended_data + BNX2X_VPD_LEN); | |
10521 | if (cnt < (block_end - BNX2X_VPD_LEN)) | |
10522 | goto out_not_found; | |
10523 | vpd_data = vpd_extended_data; | |
10524 | } else | |
10525 | vpd_data = vpd_start; | |
10526 | ||
10527 | /* now vpd_data holds full vpd content in both cases */ | |
34f24c7f VZ |
10528 | |
10529 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
10530 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
10531 | if (rodi < 0) | |
10532 | goto out_not_found; | |
10533 | ||
10534 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
10535 | ||
10536 | if (len != VENDOR_ID_LEN) | |
10537 | goto out_not_found; | |
10538 | ||
10539 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
10540 | ||
10541 | /* vendor specific info */ | |
10542 | snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); | |
10543 | snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); | |
10544 | if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || | |
10545 | !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { | |
10546 | ||
10547 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
10548 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
10549 | if (rodi >= 0) { | |
10550 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
10551 | ||
10552 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
10553 | ||
10554 | if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { | |
10555 | memcpy(bp->fw_ver, &vpd_data[rodi], len); | |
10556 | bp->fw_ver[len] = ' '; | |
10557 | } | |
10558 | } | |
fcdf95cb | 10559 | kfree(vpd_extended_data); |
34f24c7f VZ |
10560 | return; |
10561 | } | |
10562 | out_not_found: | |
fcdf95cb | 10563 | kfree(vpd_extended_data); |
34f24c7f VZ |
10564 | return; |
10565 | } | |
10566 | ||
619c5cb6 VZ |
10567 | static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) |
10568 | { | |
10569 | u32 flags = 0; | |
10570 | ||
10571 | if (CHIP_REV_IS_FPGA(bp)) | |
10572 | SET_FLAGS(flags, MODE_FPGA); | |
10573 | else if (CHIP_REV_IS_EMUL(bp)) | |
10574 | SET_FLAGS(flags, MODE_EMUL); | |
10575 | else | |
10576 | SET_FLAGS(flags, MODE_ASIC); | |
10577 | ||
10578 | if (CHIP_MODE_IS_4_PORT(bp)) | |
10579 | SET_FLAGS(flags, MODE_PORT4); | |
10580 | else | |
10581 | SET_FLAGS(flags, MODE_PORT2); | |
10582 | ||
10583 | if (CHIP_IS_E2(bp)) | |
10584 | SET_FLAGS(flags, MODE_E2); | |
10585 | else if (CHIP_IS_E3(bp)) { | |
10586 | SET_FLAGS(flags, MODE_E3); | |
10587 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
10588 | SET_FLAGS(flags, MODE_E3_A0); | |
6383c0b3 AE |
10589 | else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ |
10590 | SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); | |
619c5cb6 VZ |
10591 | } |
10592 | ||
10593 | if (IS_MF(bp)) { | |
10594 | SET_FLAGS(flags, MODE_MF); | |
10595 | switch (bp->mf_mode) { | |
10596 | case MULTI_FUNCTION_SD: | |
10597 | SET_FLAGS(flags, MODE_MF_SD); | |
10598 | break; | |
10599 | case MULTI_FUNCTION_SI: | |
10600 | SET_FLAGS(flags, MODE_MF_SI); | |
10601 | break; | |
a3348722 BW |
10602 | case MULTI_FUNCTION_AFEX: |
10603 | SET_FLAGS(flags, MODE_MF_AFEX); | |
10604 | break; | |
619c5cb6 VZ |
10605 | } |
10606 | } else | |
10607 | SET_FLAGS(flags, MODE_SF); | |
10608 | ||
10609 | #if defined(__LITTLE_ENDIAN) | |
10610 | SET_FLAGS(flags, MODE_LITTLE_ENDIAN); | |
10611 | #else /*(__BIG_ENDIAN)*/ | |
10612 | SET_FLAGS(flags, MODE_BIG_ENDIAN); | |
10613 | #endif | |
10614 | INIT_MODE_FLAGS(bp) = flags; | |
10615 | } | |
10616 | ||
34f80b04 EG |
10617 | static int __devinit bnx2x_init_bp(struct bnx2x *bp) |
10618 | { | |
f2e0899f | 10619 | int func; |
34f80b04 EG |
10620 | int rc; |
10621 | ||
34f80b04 | 10622 | mutex_init(&bp->port.phy_mutex); |
c4ff7cbf | 10623 | mutex_init(&bp->fw_mb_mutex); |
bb7e95c8 | 10624 | spin_lock_init(&bp->stats_lock); |
993ac7b5 MC |
10625 | #ifdef BCM_CNIC |
10626 | mutex_init(&bp->cnic_mutex); | |
10627 | #endif | |
a2fbb9ea | 10628 | |
1cf167f2 | 10629 | INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); |
7be08a72 | 10630 | INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); |
3deb8167 | 10631 | INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); |
34f80b04 | 10632 | rc = bnx2x_get_hwinfo(bp); |
619c5cb6 VZ |
10633 | if (rc) |
10634 | return rc; | |
34f80b04 | 10635 | |
619c5cb6 VZ |
10636 | bnx2x_set_modes_bitmap(bp); |
10637 | ||
10638 | rc = bnx2x_alloc_mem_bp(bp); | |
10639 | if (rc) | |
10640 | return rc; | |
523224a3 | 10641 | |
34f24c7f | 10642 | bnx2x_read_fwinfo(bp); |
f2e0899f DK |
10643 | |
10644 | func = BP_FUNC(bp); | |
10645 | ||
34f80b04 | 10646 | /* need to reset chip if undi was active */ |
452427b0 YM |
10647 | if (!BP_NOMCP(bp)) { |
10648 | /* init fw_seq */ | |
10649 | bp->fw_seq = | |
10650 | SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
10651 | DRV_MSG_SEQ_NUMBER_MASK; | |
10652 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | |
10653 | ||
10654 | bnx2x_prev_unload(bp); | |
10655 | } | |
10656 | ||
34f80b04 EG |
10657 | |
10658 | if (CHIP_REV_IS_FPGA(bp)) | |
cdaa7cb8 | 10659 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
34f80b04 EG |
10660 | |
10661 | if (BP_NOMCP(bp) && (func == 0)) | |
51c1a580 | 10662 | dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); |
34f80b04 | 10663 | |
614c76df DK |
10664 | bp->disable_tpa = disable_tpa; |
10665 | ||
10666 | #ifdef BCM_CNIC | |
a3348722 | 10667 | bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp); |
614c76df DK |
10668 | #endif |
10669 | ||
7a9b2557 | 10670 | /* Set TPA flags */ |
614c76df | 10671 | if (bp->disable_tpa) { |
621b4d66 | 10672 | bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
7a9b2557 VZ |
10673 | bp->dev->features &= ~NETIF_F_LRO; |
10674 | } else { | |
621b4d66 | 10675 | bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
7a9b2557 VZ |
10676 | bp->dev->features |= NETIF_F_LRO; |
10677 | } | |
10678 | ||
a18f5128 EG |
10679 | if (CHIP_IS_E1(bp)) |
10680 | bp->dropless_fc = 0; | |
10681 | else | |
10682 | bp->dropless_fc = dropless_fc; | |
10683 | ||
8d5726c4 | 10684 | bp->mrrs = mrrs; |
7a9b2557 | 10685 | |
a3348722 | 10686 | bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; |
34f80b04 | 10687 | |
7d323bfd | 10688 | /* make sure that the numbers are in the right granularity */ |
523224a3 DK |
10689 | bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; |
10690 | bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; | |
34f80b04 | 10691 | |
fc543637 | 10692 | bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; |
34f80b04 EG |
10693 | |
10694 | init_timer(&bp->timer); | |
10695 | bp->timer.expires = jiffies + bp->current_interval; | |
10696 | bp->timer.data = (unsigned long) bp; | |
10697 | bp->timer.function = bnx2x_timer; | |
10698 | ||
785b9b1a | 10699 | bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); |
e4901dde VZ |
10700 | bnx2x_dcbx_init_params(bp); |
10701 | ||
619c5cb6 VZ |
10702 | #ifdef BCM_CNIC |
10703 | if (CHIP_IS_E1x(bp)) | |
10704 | bp->cnic_base_cl_id = FP_SB_MAX_E1x; | |
10705 | else | |
10706 | bp->cnic_base_cl_id = FP_SB_MAX_E2; | |
10707 | #endif | |
10708 | ||
6383c0b3 AE |
10709 | /* multiple tx priority */ |
10710 | if (CHIP_IS_E1x(bp)) | |
10711 | bp->max_cos = BNX2X_MULTI_TX_COS_E1X; | |
10712 | if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) | |
10713 | bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; | |
10714 | if (CHIP_IS_E3B0(bp)) | |
10715 | bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; | |
10716 | ||
34f80b04 | 10717 | return rc; |
a2fbb9ea ET |
10718 | } |
10719 | ||
a2fbb9ea | 10720 | |
de0c62db DK |
10721 | /**************************************************************************** |
10722 | * General service functions | |
10723 | ****************************************************************************/ | |
a2fbb9ea | 10724 | |
619c5cb6 VZ |
10725 | /* |
10726 | * net_device service functions | |
10727 | */ | |
10728 | ||
bb2a0f7a | 10729 | /* called with rtnl_lock */ |
a2fbb9ea ET |
10730 | static int bnx2x_open(struct net_device *dev) |
10731 | { | |
10732 | struct bnx2x *bp = netdev_priv(dev); | |
c9ee9206 VZ |
10733 | bool global = false; |
10734 | int other_engine = BP_PATH(bp) ? 0 : 1; | |
889b9af3 | 10735 | bool other_load_status, load_status; |
a2fbb9ea | 10736 | |
1355b704 MY |
10737 | bp->stats_init = true; |
10738 | ||
6eccabb3 EG |
10739 | netif_carrier_off(dev); |
10740 | ||
a2fbb9ea ET |
10741 | bnx2x_set_power_state(bp, PCI_D0); |
10742 | ||
889b9af3 AE |
10743 | other_load_status = bnx2x_get_load_status(bp, other_engine); |
10744 | load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); | |
c9ee9206 VZ |
10745 | |
10746 | /* | |
10747 | * If parity had happen during the unload, then attentions | |
10748 | * and/or RECOVERY_IN_PROGRES may still be set. In this case we | |
10749 | * want the first function loaded on the current engine to | |
10750 | * complete the recovery. | |
10751 | */ | |
10752 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || | |
10753 | bnx2x_chk_parity_attn(bp, &global, true)) | |
72fd0718 | 10754 | do { |
c9ee9206 VZ |
10755 | /* |
10756 | * If there are attentions and they are in a global | |
10757 | * blocks, set the GLOBAL_RESET bit regardless whether | |
10758 | * it will be this function that will complete the | |
10759 | * recovery or not. | |
72fd0718 | 10760 | */ |
c9ee9206 VZ |
10761 | if (global) |
10762 | bnx2x_set_reset_global(bp); | |
72fd0718 | 10763 | |
c9ee9206 VZ |
10764 | /* |
10765 | * Only the first function on the current engine should | |
10766 | * try to recover in open. In case of attentions in | |
10767 | * global blocks only the first in the chip should try | |
10768 | * to recover. | |
72fd0718 | 10769 | */ |
889b9af3 AE |
10770 | if ((!load_status && |
10771 | (!global || !other_load_status)) && | |
c9ee9206 VZ |
10772 | bnx2x_trylock_leader_lock(bp) && |
10773 | !bnx2x_leader_reset(bp)) { | |
10774 | netdev_info(bp->dev, "Recovered in open\n"); | |
72fd0718 VZ |
10775 | break; |
10776 | } | |
10777 | ||
c9ee9206 | 10778 | /* recovery has failed... */ |
72fd0718 | 10779 | bnx2x_set_power_state(bp, PCI_D3hot); |
c9ee9206 | 10780 | bp->recovery_state = BNX2X_RECOVERY_FAILED; |
72fd0718 | 10781 | |
51c1a580 MS |
10782 | BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" |
10783 | "If you still see this message after a few retries then power cycle is required.\n"); | |
72fd0718 VZ |
10784 | |
10785 | return -EAGAIN; | |
10786 | } while (0); | |
72fd0718 VZ |
10787 | |
10788 | bp->recovery_state = BNX2X_RECOVERY_DONE; | |
bb2a0f7a | 10789 | return bnx2x_nic_load(bp, LOAD_OPEN); |
a2fbb9ea ET |
10790 | } |
10791 | ||
bb2a0f7a | 10792 | /* called with rtnl_lock */ |
56ad3152 | 10793 | static int bnx2x_close(struct net_device *dev) |
a2fbb9ea | 10794 | { |
a2fbb9ea ET |
10795 | struct bnx2x *bp = netdev_priv(dev); |
10796 | ||
10797 | /* Unload the driver, release IRQs */ | |
bb2a0f7a | 10798 | bnx2x_nic_unload(bp, UNLOAD_CLOSE); |
c9ee9206 VZ |
10799 | |
10800 | /* Power off */ | |
d3dbfee0 | 10801 | bnx2x_set_power_state(bp, PCI_D3hot); |
a2fbb9ea ET |
10802 | |
10803 | return 0; | |
10804 | } | |
10805 | ||
619c5cb6 VZ |
10806 | static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, |
10807 | struct bnx2x_mcast_ramrod_params *p) | |
6e30dd4e | 10808 | { |
619c5cb6 VZ |
10809 | int mc_count = netdev_mc_count(bp->dev); |
10810 | struct bnx2x_mcast_list_elem *mc_mac = | |
10811 | kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); | |
10812 | struct netdev_hw_addr *ha; | |
6e30dd4e | 10813 | |
619c5cb6 VZ |
10814 | if (!mc_mac) |
10815 | return -ENOMEM; | |
6e30dd4e | 10816 | |
619c5cb6 | 10817 | INIT_LIST_HEAD(&p->mcast_list); |
6e30dd4e | 10818 | |
619c5cb6 VZ |
10819 | netdev_for_each_mc_addr(ha, bp->dev) { |
10820 | mc_mac->mac = bnx2x_mc_addr(ha); | |
10821 | list_add_tail(&mc_mac->link, &p->mcast_list); | |
10822 | mc_mac++; | |
6e30dd4e | 10823 | } |
619c5cb6 VZ |
10824 | |
10825 | p->mcast_list_len = mc_count; | |
10826 | ||
10827 | return 0; | |
6e30dd4e VZ |
10828 | } |
10829 | ||
619c5cb6 VZ |
10830 | static inline void bnx2x_free_mcast_macs_list( |
10831 | struct bnx2x_mcast_ramrod_params *p) | |
10832 | { | |
10833 | struct bnx2x_mcast_list_elem *mc_mac = | |
10834 | list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, | |
10835 | link); | |
10836 | ||
10837 | WARN_ON(!mc_mac); | |
10838 | kfree(mc_mac); | |
10839 | } | |
10840 | ||
10841 | /** | |
10842 | * bnx2x_set_uc_list - configure a new unicast MACs list. | |
10843 | * | |
10844 | * @bp: driver handle | |
6e30dd4e | 10845 | * |
619c5cb6 | 10846 | * We will use zero (0) as a MAC type for these MACs. |
6e30dd4e | 10847 | */ |
619c5cb6 | 10848 | static inline int bnx2x_set_uc_list(struct bnx2x *bp) |
6e30dd4e | 10849 | { |
619c5cb6 | 10850 | int rc; |
6e30dd4e | 10851 | struct net_device *dev = bp->dev; |
6e30dd4e | 10852 | struct netdev_hw_addr *ha; |
619c5cb6 VZ |
10853 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; |
10854 | unsigned long ramrod_flags = 0; | |
6e30dd4e | 10855 | |
619c5cb6 VZ |
10856 | /* First schedule a cleanup up of old configuration */ |
10857 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); | |
10858 | if (rc < 0) { | |
10859 | BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); | |
10860 | return rc; | |
10861 | } | |
6e30dd4e VZ |
10862 | |
10863 | netdev_for_each_uc_addr(ha, dev) { | |
619c5cb6 VZ |
10864 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
10865 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
10866 | if (rc < 0) { | |
10867 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", | |
10868 | rc); | |
10869 | return rc; | |
6e30dd4e VZ |
10870 | } |
10871 | } | |
10872 | ||
619c5cb6 VZ |
10873 | /* Execute the pending commands */ |
10874 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
10875 | return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, | |
10876 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
6e30dd4e VZ |
10877 | } |
10878 | ||
619c5cb6 | 10879 | static inline int bnx2x_set_mc_list(struct bnx2x *bp) |
6e30dd4e | 10880 | { |
619c5cb6 | 10881 | struct net_device *dev = bp->dev; |
3b603066 | 10882 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 | 10883 | int rc = 0; |
6e30dd4e | 10884 | |
619c5cb6 | 10885 | rparam.mcast_obj = &bp->mcast_obj; |
6e30dd4e | 10886 | |
619c5cb6 VZ |
10887 | /* first, clear all configured multicast MACs */ |
10888 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
10889 | if (rc < 0) { | |
51c1a580 | 10890 | BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); |
619c5cb6 VZ |
10891 | return rc; |
10892 | } | |
6e30dd4e | 10893 | |
619c5cb6 VZ |
10894 | /* then, configure a new MACs list */ |
10895 | if (netdev_mc_count(dev)) { | |
10896 | rc = bnx2x_init_mcast_macs_list(bp, &rparam); | |
10897 | if (rc) { | |
51c1a580 MS |
10898 | BNX2X_ERR("Failed to create multicast MACs list: %d\n", |
10899 | rc); | |
619c5cb6 VZ |
10900 | return rc; |
10901 | } | |
6e30dd4e | 10902 | |
619c5cb6 VZ |
10903 | /* Now add the new MACs */ |
10904 | rc = bnx2x_config_mcast(bp, &rparam, | |
10905 | BNX2X_MCAST_CMD_ADD); | |
10906 | if (rc < 0) | |
51c1a580 MS |
10907 | BNX2X_ERR("Failed to set a new multicast configuration: %d\n", |
10908 | rc); | |
6e30dd4e | 10909 | |
619c5cb6 VZ |
10910 | bnx2x_free_mcast_macs_list(&rparam); |
10911 | } | |
6e30dd4e | 10912 | |
619c5cb6 | 10913 | return rc; |
6e30dd4e VZ |
10914 | } |
10915 | ||
6e30dd4e | 10916 | |
619c5cb6 | 10917 | /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ |
9f6c9258 | 10918 | void bnx2x_set_rx_mode(struct net_device *dev) |
34f80b04 EG |
10919 | { |
10920 | struct bnx2x *bp = netdev_priv(dev); | |
10921 | u32 rx_mode = BNX2X_RX_MODE_NORMAL; | |
34f80b04 EG |
10922 | |
10923 | if (bp->state != BNX2X_STATE_OPEN) { | |
10924 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); | |
10925 | return; | |
10926 | } | |
10927 | ||
619c5cb6 | 10928 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); |
34f80b04 EG |
10929 | |
10930 | if (dev->flags & IFF_PROMISC) | |
10931 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
619c5cb6 VZ |
10932 | else if ((dev->flags & IFF_ALLMULTI) || |
10933 | ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && | |
10934 | CHIP_IS_E1(bp))) | |
34f80b04 | 10935 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
6e30dd4e VZ |
10936 | else { |
10937 | /* some multicasts */ | |
619c5cb6 | 10938 | if (bnx2x_set_mc_list(bp) < 0) |
6e30dd4e | 10939 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
34f80b04 | 10940 | |
619c5cb6 | 10941 | if (bnx2x_set_uc_list(bp) < 0) |
6e30dd4e | 10942 | rx_mode = BNX2X_RX_MODE_PROMISC; |
34f80b04 EG |
10943 | } |
10944 | ||
10945 | bp->rx_mode = rx_mode; | |
614c76df DK |
10946 | #ifdef BCM_CNIC |
10947 | /* handle ISCSI SD mode */ | |
10948 | if (IS_MF_ISCSI_SD(bp)) | |
10949 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
10950 | #endif | |
619c5cb6 VZ |
10951 | |
10952 | /* Schedule the rx_mode command */ | |
10953 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { | |
10954 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
10955 | return; | |
10956 | } | |
10957 | ||
34f80b04 EG |
10958 | bnx2x_set_storm_rx_mode(bp); |
10959 | } | |
10960 | ||
c18487ee | 10961 | /* called with rtnl_lock */ |
01cd4528 EG |
10962 | static int bnx2x_mdio_read(struct net_device *netdev, int prtad, |
10963 | int devad, u16 addr) | |
a2fbb9ea | 10964 | { |
01cd4528 EG |
10965 | struct bnx2x *bp = netdev_priv(netdev); |
10966 | u16 value; | |
10967 | int rc; | |
a2fbb9ea | 10968 | |
01cd4528 EG |
10969 | DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", |
10970 | prtad, devad, addr); | |
a2fbb9ea | 10971 | |
01cd4528 EG |
10972 | /* The HW expects different devad if CL22 is used */ |
10973 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
c18487ee | 10974 | |
01cd4528 | 10975 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 10976 | rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); |
01cd4528 EG |
10977 | bnx2x_release_phy_lock(bp); |
10978 | DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); | |
a2fbb9ea | 10979 | |
01cd4528 EG |
10980 | if (!rc) |
10981 | rc = value; | |
10982 | return rc; | |
10983 | } | |
a2fbb9ea | 10984 | |
01cd4528 EG |
10985 | /* called with rtnl_lock */ |
10986 | static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, | |
10987 | u16 addr, u16 value) | |
10988 | { | |
10989 | struct bnx2x *bp = netdev_priv(netdev); | |
01cd4528 EG |
10990 | int rc; |
10991 | ||
51c1a580 MS |
10992 | DP(NETIF_MSG_LINK, |
10993 | "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", | |
10994 | prtad, devad, addr, value); | |
01cd4528 | 10995 | |
01cd4528 EG |
10996 | /* The HW expects different devad if CL22 is used */ |
10997 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
a2fbb9ea | 10998 | |
01cd4528 | 10999 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 11000 | rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); |
01cd4528 EG |
11001 | bnx2x_release_phy_lock(bp); |
11002 | return rc; | |
11003 | } | |
c18487ee | 11004 | |
01cd4528 EG |
11005 | /* called with rtnl_lock */ |
11006 | static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
11007 | { | |
11008 | struct bnx2x *bp = netdev_priv(dev); | |
11009 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
a2fbb9ea | 11010 | |
01cd4528 EG |
11011 | DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", |
11012 | mdio->phy_id, mdio->reg_num, mdio->val_in); | |
a2fbb9ea | 11013 | |
01cd4528 EG |
11014 | if (!netif_running(dev)) |
11015 | return -EAGAIN; | |
11016 | ||
11017 | return mdio_mii_ioctl(&bp->mdio, mdio, cmd); | |
a2fbb9ea ET |
11018 | } |
11019 | ||
257ddbda | 11020 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a2fbb9ea ET |
11021 | static void poll_bnx2x(struct net_device *dev) |
11022 | { | |
11023 | struct bnx2x *bp = netdev_priv(dev); | |
11024 | ||
11025 | disable_irq(bp->pdev->irq); | |
11026 | bnx2x_interrupt(bp->pdev->irq, dev); | |
11027 | enable_irq(bp->pdev->irq); | |
11028 | } | |
11029 | #endif | |
11030 | ||
614c76df DK |
11031 | static int bnx2x_validate_addr(struct net_device *dev) |
11032 | { | |
11033 | struct bnx2x *bp = netdev_priv(dev); | |
11034 | ||
51c1a580 MS |
11035 | if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) { |
11036 | BNX2X_ERR("Non-valid Ethernet address\n"); | |
614c76df | 11037 | return -EADDRNOTAVAIL; |
51c1a580 | 11038 | } |
614c76df DK |
11039 | return 0; |
11040 | } | |
11041 | ||
c64213cd SH |
11042 | static const struct net_device_ops bnx2x_netdev_ops = { |
11043 | .ndo_open = bnx2x_open, | |
11044 | .ndo_stop = bnx2x_close, | |
11045 | .ndo_start_xmit = bnx2x_start_xmit, | |
8307fa3e | 11046 | .ndo_select_queue = bnx2x_select_queue, |
6e30dd4e | 11047 | .ndo_set_rx_mode = bnx2x_set_rx_mode, |
c64213cd | 11048 | .ndo_set_mac_address = bnx2x_change_mac_addr, |
614c76df | 11049 | .ndo_validate_addr = bnx2x_validate_addr, |
c64213cd SH |
11050 | .ndo_do_ioctl = bnx2x_ioctl, |
11051 | .ndo_change_mtu = bnx2x_change_mtu, | |
66371c44 MM |
11052 | .ndo_fix_features = bnx2x_fix_features, |
11053 | .ndo_set_features = bnx2x_set_features, | |
c64213cd | 11054 | .ndo_tx_timeout = bnx2x_tx_timeout, |
257ddbda | 11055 | #ifdef CONFIG_NET_POLL_CONTROLLER |
c64213cd SH |
11056 | .ndo_poll_controller = poll_bnx2x, |
11057 | #endif | |
6383c0b3 AE |
11058 | .ndo_setup_tc = bnx2x_setup_tc, |
11059 | ||
bf61ee14 VZ |
11060 | #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) |
11061 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, | |
11062 | #endif | |
c64213cd SH |
11063 | }; |
11064 | ||
619c5cb6 VZ |
11065 | static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) |
11066 | { | |
11067 | struct device *dev = &bp->pdev->dev; | |
11068 | ||
11069 | if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { | |
11070 | bp->flags |= USING_DAC_FLAG; | |
11071 | if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { | |
51c1a580 | 11072 | dev_err(dev, "dma_set_coherent_mask failed, aborting\n"); |
619c5cb6 VZ |
11073 | return -EIO; |
11074 | } | |
11075 | } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { | |
11076 | dev_err(dev, "System does not support DMA, aborting\n"); | |
11077 | return -EIO; | |
11078 | } | |
11079 | ||
11080 | return 0; | |
11081 | } | |
11082 | ||
34f80b04 | 11083 | static int __devinit bnx2x_init_dev(struct pci_dev *pdev, |
619c5cb6 VZ |
11084 | struct net_device *dev, |
11085 | unsigned long board_type) | |
a2fbb9ea ET |
11086 | { |
11087 | struct bnx2x *bp; | |
11088 | int rc; | |
c22610d0 | 11089 | u32 pci_cfg_dword; |
65087cfe AE |
11090 | bool chip_is_e1x = (board_type == BCM57710 || |
11091 | board_type == BCM57711 || | |
11092 | board_type == BCM57711E); | |
a2fbb9ea ET |
11093 | |
11094 | SET_NETDEV_DEV(dev, &pdev->dev); | |
11095 | bp = netdev_priv(dev); | |
11096 | ||
34f80b04 EG |
11097 | bp->dev = dev; |
11098 | bp->pdev = pdev; | |
a2fbb9ea | 11099 | bp->flags = 0; |
a2fbb9ea ET |
11100 | |
11101 | rc = pci_enable_device(pdev); | |
11102 | if (rc) { | |
cdaa7cb8 VZ |
11103 | dev_err(&bp->pdev->dev, |
11104 | "Cannot enable PCI device, aborting\n"); | |
a2fbb9ea ET |
11105 | goto err_out; |
11106 | } | |
11107 | ||
11108 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
11109 | dev_err(&bp->pdev->dev, |
11110 | "Cannot find PCI device base address, aborting\n"); | |
a2fbb9ea ET |
11111 | rc = -ENODEV; |
11112 | goto err_out_disable; | |
11113 | } | |
11114 | ||
11115 | if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
11116 | dev_err(&bp->pdev->dev, "Cannot find second PCI device" |
11117 | " base address, aborting\n"); | |
a2fbb9ea ET |
11118 | rc = -ENODEV; |
11119 | goto err_out_disable; | |
11120 | } | |
11121 | ||
34f80b04 EG |
11122 | if (atomic_read(&pdev->enable_cnt) == 1) { |
11123 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
11124 | if (rc) { | |
cdaa7cb8 VZ |
11125 | dev_err(&bp->pdev->dev, |
11126 | "Cannot obtain PCI resources, aborting\n"); | |
34f80b04 EG |
11127 | goto err_out_disable; |
11128 | } | |
a2fbb9ea | 11129 | |
34f80b04 EG |
11130 | pci_set_master(pdev); |
11131 | pci_save_state(pdev); | |
11132 | } | |
a2fbb9ea ET |
11133 | |
11134 | bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
11135 | if (bp->pm_cap == 0) { | |
cdaa7cb8 VZ |
11136 | dev_err(&bp->pdev->dev, |
11137 | "Cannot find power management capability, aborting\n"); | |
a2fbb9ea ET |
11138 | rc = -EIO; |
11139 | goto err_out_release; | |
11140 | } | |
11141 | ||
77c98e6a | 11142 | if (!pci_is_pcie(pdev)) { |
51c1a580 | 11143 | dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); |
a2fbb9ea ET |
11144 | rc = -EIO; |
11145 | goto err_out_release; | |
11146 | } | |
11147 | ||
619c5cb6 VZ |
11148 | rc = bnx2x_set_coherency_mask(bp); |
11149 | if (rc) | |
a2fbb9ea | 11150 | goto err_out_release; |
a2fbb9ea | 11151 | |
34f80b04 EG |
11152 | dev->mem_start = pci_resource_start(pdev, 0); |
11153 | dev->base_addr = dev->mem_start; | |
11154 | dev->mem_end = pci_resource_end(pdev, 0); | |
a2fbb9ea ET |
11155 | |
11156 | dev->irq = pdev->irq; | |
11157 | ||
275f165f | 11158 | bp->regview = pci_ioremap_bar(pdev, 0); |
a2fbb9ea | 11159 | if (!bp->regview) { |
cdaa7cb8 VZ |
11160 | dev_err(&bp->pdev->dev, |
11161 | "Cannot map register space, aborting\n"); | |
a2fbb9ea ET |
11162 | rc = -ENOMEM; |
11163 | goto err_out_release; | |
11164 | } | |
11165 | ||
c22610d0 AE |
11166 | /* In E1/E1H use pci device function given by kernel. |
11167 | * In E2/E3 read physical function from ME register since these chips | |
11168 | * support Physical Device Assignment where kernel BDF maybe arbitrary | |
11169 | * (depending on hypervisor). | |
11170 | */ | |
11171 | if (chip_is_e1x) | |
11172 | bp->pf_num = PCI_FUNC(pdev->devfn); | |
11173 | else {/* chip is E2/3*/ | |
11174 | pci_read_config_dword(bp->pdev, | |
11175 | PCICFG_ME_REGISTER, &pci_cfg_dword); | |
11176 | bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> | |
11177 | ME_REG_ABS_PF_NUM_SHIFT); | |
11178 | } | |
51c1a580 | 11179 | BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); |
c22610d0 | 11180 | |
a2fbb9ea ET |
11181 | bnx2x_set_power_state(bp, PCI_D0); |
11182 | ||
34f80b04 EG |
11183 | /* clean indirect addresses */ |
11184 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
11185 | PCICFG_VENDOR_ID_OFFSET); | |
a5c53dbc DK |
11186 | /* |
11187 | * Clean the following indirect addresses for all functions since it | |
9f0096a1 DK |
11188 | * is not used by the driver. |
11189 | */ | |
11190 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); | |
11191 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); | |
11192 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); | |
11193 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); | |
a5c53dbc | 11194 | |
65087cfe | 11195 | if (chip_is_e1x) { |
a5c53dbc DK |
11196 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); |
11197 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); | |
11198 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); | |
11199 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); | |
11200 | } | |
a2fbb9ea | 11201 | |
2189400b | 11202 | /* |
619c5cb6 | 11203 | * Enable internal target-read (in case we are probed after PF FLR). |
2189400b | 11204 | * Must be done prior to any BAR read access. Only for 57712 and up |
619c5cb6 | 11205 | */ |
65087cfe | 11206 | if (!chip_is_e1x) |
2189400b | 11207 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); |
619c5cb6 | 11208 | |
72fd0718 | 11209 | /* Reset the load counter */ |
889b9af3 | 11210 | bnx2x_clear_load_status(bp); |
72fd0718 | 11211 | |
34f80b04 | 11212 | dev->watchdog_timeo = TX_TIMEOUT; |
a2fbb9ea | 11213 | |
c64213cd | 11214 | dev->netdev_ops = &bnx2x_netdev_ops; |
de0c62db | 11215 | bnx2x_set_ethtool_ops(dev); |
5316bc0b | 11216 | |
01789349 JP |
11217 | dev->priv_flags |= IFF_UNICAST_FLT; |
11218 | ||
66371c44 | 11219 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
621b4d66 DK |
11220 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | |
11221 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | | |
11222 | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; | |
66371c44 MM |
11223 | |
11224 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
11225 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; | |
11226 | ||
11227 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; | |
5316bc0b | 11228 | if (bp->flags & USING_DAC_FLAG) |
66371c44 | 11229 | dev->features |= NETIF_F_HIGHDMA; |
a2fbb9ea | 11230 | |
538dd2e3 MB |
11231 | /* Add Loopback capability to the device */ |
11232 | dev->hw_features |= NETIF_F_LOOPBACK; | |
11233 | ||
98507672 | 11234 | #ifdef BCM_DCBNL |
785b9b1a SR |
11235 | dev->dcbnl_ops = &bnx2x_dcbnl_ops; |
11236 | #endif | |
11237 | ||
01cd4528 EG |
11238 | /* get_port_hwinfo() will set prtad and mmds properly */ |
11239 | bp->mdio.prtad = MDIO_PRTAD_NONE; | |
11240 | bp->mdio.mmds = 0; | |
11241 | bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
11242 | bp->mdio.dev = dev; | |
11243 | bp->mdio.mdio_read = bnx2x_mdio_read; | |
11244 | bp->mdio.mdio_write = bnx2x_mdio_write; | |
11245 | ||
a2fbb9ea ET |
11246 | return 0; |
11247 | ||
a2fbb9ea | 11248 | err_out_release: |
34f80b04 EG |
11249 | if (atomic_read(&pdev->enable_cnt) == 1) |
11250 | pci_release_regions(pdev); | |
a2fbb9ea ET |
11251 | |
11252 | err_out_disable: | |
11253 | pci_disable_device(pdev); | |
11254 | pci_set_drvdata(pdev, NULL); | |
11255 | ||
11256 | err_out: | |
11257 | return rc; | |
11258 | } | |
11259 | ||
37f9ce62 EG |
11260 | static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, |
11261 | int *width, int *speed) | |
25047950 ET |
11262 | { |
11263 | u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); | |
11264 | ||
37f9ce62 | 11265 | *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; |
25047950 | 11266 | |
37f9ce62 EG |
11267 | /* return value of 1=2.5GHz 2=5GHz */ |
11268 | *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; | |
25047950 | 11269 | } |
37f9ce62 | 11270 | |
6891dd25 | 11271 | static int bnx2x_check_firmware(struct bnx2x *bp) |
94a78b79 | 11272 | { |
37f9ce62 | 11273 | const struct firmware *firmware = bp->firmware; |
94a78b79 VZ |
11274 | struct bnx2x_fw_file_hdr *fw_hdr; |
11275 | struct bnx2x_fw_file_section *sections; | |
94a78b79 | 11276 | u32 offset, len, num_ops; |
37f9ce62 | 11277 | u16 *ops_offsets; |
94a78b79 | 11278 | int i; |
37f9ce62 | 11279 | const u8 *fw_ver; |
94a78b79 | 11280 | |
51c1a580 MS |
11281 | if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { |
11282 | BNX2X_ERR("Wrong FW size\n"); | |
94a78b79 | 11283 | return -EINVAL; |
51c1a580 | 11284 | } |
94a78b79 VZ |
11285 | |
11286 | fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; | |
11287 | sections = (struct bnx2x_fw_file_section *)fw_hdr; | |
11288 | ||
11289 | /* Make sure none of the offsets and sizes make us read beyond | |
11290 | * the end of the firmware data */ | |
11291 | for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { | |
11292 | offset = be32_to_cpu(sections[i].offset); | |
11293 | len = be32_to_cpu(sections[i].len); | |
11294 | if (offset + len > firmware->size) { | |
51c1a580 | 11295 | BNX2X_ERR("Section %d length is out of bounds\n", i); |
94a78b79 VZ |
11296 | return -EINVAL; |
11297 | } | |
11298 | } | |
11299 | ||
11300 | /* Likewise for the init_ops offsets */ | |
11301 | offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); | |
11302 | ops_offsets = (u16 *)(firmware->data + offset); | |
11303 | num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); | |
11304 | ||
11305 | for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { | |
11306 | if (be16_to_cpu(ops_offsets[i]) > num_ops) { | |
51c1a580 | 11307 | BNX2X_ERR("Section offset %d is out of bounds\n", i); |
94a78b79 VZ |
11308 | return -EINVAL; |
11309 | } | |
11310 | } | |
11311 | ||
11312 | /* Check FW version */ | |
11313 | offset = be32_to_cpu(fw_hdr->fw_version.offset); | |
11314 | fw_ver = firmware->data + offset; | |
11315 | if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || | |
11316 | (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || | |
11317 | (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || | |
11318 | (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { | |
51c1a580 MS |
11319 | BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", |
11320 | fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], | |
11321 | BCM_5710_FW_MAJOR_VERSION, | |
94a78b79 VZ |
11322 | BCM_5710_FW_MINOR_VERSION, |
11323 | BCM_5710_FW_REVISION_VERSION, | |
11324 | BCM_5710_FW_ENGINEERING_VERSION); | |
ab6ad5a4 | 11325 | return -EINVAL; |
94a78b79 VZ |
11326 | } |
11327 | ||
11328 | return 0; | |
11329 | } | |
11330 | ||
ab6ad5a4 | 11331 | static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 11332 | { |
ab6ad5a4 EG |
11333 | const __be32 *source = (const __be32 *)_source; |
11334 | u32 *target = (u32 *)_target; | |
94a78b79 | 11335 | u32 i; |
94a78b79 VZ |
11336 | |
11337 | for (i = 0; i < n/4; i++) | |
11338 | target[i] = be32_to_cpu(source[i]); | |
11339 | } | |
11340 | ||
11341 | /* | |
11342 | Ops array is stored in the following format: | |
11343 | {op(8bit), offset(24bit, big endian), data(32bit, big endian)} | |
11344 | */ | |
ab6ad5a4 | 11345 | static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 11346 | { |
ab6ad5a4 EG |
11347 | const __be32 *source = (const __be32 *)_source; |
11348 | struct raw_op *target = (struct raw_op *)_target; | |
94a78b79 | 11349 | u32 i, j, tmp; |
94a78b79 | 11350 | |
ab6ad5a4 | 11351 | for (i = 0, j = 0; i < n/8; i++, j += 2) { |
94a78b79 VZ |
11352 | tmp = be32_to_cpu(source[j]); |
11353 | target[i].op = (tmp >> 24) & 0xff; | |
cdaa7cb8 VZ |
11354 | target[i].offset = tmp & 0xffffff; |
11355 | target[i].raw_data = be32_to_cpu(source[j + 1]); | |
94a78b79 VZ |
11356 | } |
11357 | } | |
ab6ad5a4 | 11358 | |
523224a3 DK |
11359 | /** |
11360 | * IRO array is stored in the following format: | |
11361 | * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } | |
11362 | */ | |
11363 | static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) | |
11364 | { | |
11365 | const __be32 *source = (const __be32 *)_source; | |
11366 | struct iro *target = (struct iro *)_target; | |
11367 | u32 i, j, tmp; | |
11368 | ||
11369 | for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { | |
11370 | target[i].base = be32_to_cpu(source[j]); | |
11371 | j++; | |
11372 | tmp = be32_to_cpu(source[j]); | |
11373 | target[i].m1 = (tmp >> 16) & 0xffff; | |
11374 | target[i].m2 = tmp & 0xffff; | |
11375 | j++; | |
11376 | tmp = be32_to_cpu(source[j]); | |
11377 | target[i].m3 = (tmp >> 16) & 0xffff; | |
11378 | target[i].size = tmp & 0xffff; | |
11379 | j++; | |
11380 | } | |
11381 | } | |
11382 | ||
ab6ad5a4 | 11383 | static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 11384 | { |
ab6ad5a4 EG |
11385 | const __be16 *source = (const __be16 *)_source; |
11386 | u16 *target = (u16 *)_target; | |
94a78b79 | 11387 | u32 i; |
94a78b79 VZ |
11388 | |
11389 | for (i = 0; i < n/2; i++) | |
11390 | target[i] = be16_to_cpu(source[i]); | |
11391 | } | |
11392 | ||
7995c64e JP |
11393 | #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ |
11394 | do { \ | |
11395 | u32 len = be32_to_cpu(fw_hdr->arr.len); \ | |
11396 | bp->arr = kmalloc(len, GFP_KERNEL); \ | |
e404decb | 11397 | if (!bp->arr) \ |
7995c64e | 11398 | goto lbl; \ |
7995c64e JP |
11399 | func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ |
11400 | (u8 *)bp->arr, len); \ | |
11401 | } while (0) | |
94a78b79 | 11402 | |
3b603066 | 11403 | static int bnx2x_init_firmware(struct bnx2x *bp) |
94a78b79 | 11404 | { |
c0ea452e | 11405 | const char *fw_file_name; |
94a78b79 | 11406 | struct bnx2x_fw_file_hdr *fw_hdr; |
45229b42 | 11407 | int rc; |
94a78b79 | 11408 | |
c0ea452e MS |
11409 | if (bp->firmware) |
11410 | return 0; | |
94a78b79 | 11411 | |
c0ea452e MS |
11412 | if (CHIP_IS_E1(bp)) |
11413 | fw_file_name = FW_FILE_NAME_E1; | |
11414 | else if (CHIP_IS_E1H(bp)) | |
11415 | fw_file_name = FW_FILE_NAME_E1H; | |
11416 | else if (!CHIP_IS_E1x(bp)) | |
11417 | fw_file_name = FW_FILE_NAME_E2; | |
11418 | else { | |
11419 | BNX2X_ERR("Unsupported chip revision\n"); | |
11420 | return -EINVAL; | |
11421 | } | |
11422 | BNX2X_DEV_INFO("Loading %s\n", fw_file_name); | |
94a78b79 | 11423 | |
c0ea452e MS |
11424 | rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); |
11425 | if (rc) { | |
11426 | BNX2X_ERR("Can't load firmware file %s\n", | |
11427 | fw_file_name); | |
11428 | goto request_firmware_exit; | |
11429 | } | |
eb2afd4a | 11430 | |
c0ea452e MS |
11431 | rc = bnx2x_check_firmware(bp); |
11432 | if (rc) { | |
11433 | BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); | |
11434 | goto request_firmware_exit; | |
94a78b79 VZ |
11435 | } |
11436 | ||
11437 | fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; | |
11438 | ||
11439 | /* Initialize the pointers to the init arrays */ | |
11440 | /* Blob */ | |
11441 | BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); | |
11442 | ||
11443 | /* Opcodes */ | |
11444 | BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); | |
11445 | ||
11446 | /* Offsets */ | |
ab6ad5a4 EG |
11447 | BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, |
11448 | be16_to_cpu_n); | |
94a78b79 VZ |
11449 | |
11450 | /* STORMs firmware */ | |
573f2035 EG |
11451 | INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
11452 | be32_to_cpu(fw_hdr->tsem_int_table_data.offset); | |
11453 | INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + | |
11454 | be32_to_cpu(fw_hdr->tsem_pram_data.offset); | |
11455 | INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
11456 | be32_to_cpu(fw_hdr->usem_int_table_data.offset); | |
11457 | INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + | |
11458 | be32_to_cpu(fw_hdr->usem_pram_data.offset); | |
11459 | INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
11460 | be32_to_cpu(fw_hdr->xsem_int_table_data.offset); | |
11461 | INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + | |
11462 | be32_to_cpu(fw_hdr->xsem_pram_data.offset); | |
11463 | INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
11464 | be32_to_cpu(fw_hdr->csem_int_table_data.offset); | |
11465 | INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + | |
11466 | be32_to_cpu(fw_hdr->csem_pram_data.offset); | |
523224a3 DK |
11467 | /* IRO */ |
11468 | BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); | |
94a78b79 VZ |
11469 | |
11470 | return 0; | |
ab6ad5a4 | 11471 | |
523224a3 DK |
11472 | iro_alloc_err: |
11473 | kfree(bp->init_ops_offsets); | |
94a78b79 VZ |
11474 | init_offsets_alloc_err: |
11475 | kfree(bp->init_ops); | |
11476 | init_ops_alloc_err: | |
11477 | kfree(bp->init_data); | |
11478 | request_firmware_exit: | |
11479 | release_firmware(bp->firmware); | |
127d0a19 | 11480 | bp->firmware = NULL; |
94a78b79 VZ |
11481 | |
11482 | return rc; | |
11483 | } | |
11484 | ||
619c5cb6 VZ |
11485 | static void bnx2x_release_firmware(struct bnx2x *bp) |
11486 | { | |
11487 | kfree(bp->init_ops_offsets); | |
11488 | kfree(bp->init_ops); | |
11489 | kfree(bp->init_data); | |
11490 | release_firmware(bp->firmware); | |
eb2afd4a | 11491 | bp->firmware = NULL; |
619c5cb6 VZ |
11492 | } |
11493 | ||
11494 | ||
11495 | static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { | |
11496 | .init_hw_cmn_chip = bnx2x_init_hw_common_chip, | |
11497 | .init_hw_cmn = bnx2x_init_hw_common, | |
11498 | .init_hw_port = bnx2x_init_hw_port, | |
11499 | .init_hw_func = bnx2x_init_hw_func, | |
11500 | ||
11501 | .reset_hw_cmn = bnx2x_reset_common, | |
11502 | .reset_hw_port = bnx2x_reset_port, | |
11503 | .reset_hw_func = bnx2x_reset_func, | |
11504 | ||
11505 | .gunzip_init = bnx2x_gunzip_init, | |
11506 | .gunzip_end = bnx2x_gunzip_end, | |
11507 | ||
11508 | .init_fw = bnx2x_init_firmware, | |
11509 | .release_fw = bnx2x_release_firmware, | |
11510 | }; | |
11511 | ||
11512 | void bnx2x__init_func_obj(struct bnx2x *bp) | |
11513 | { | |
11514 | /* Prepare DMAE related driver resources */ | |
11515 | bnx2x_setup_dmae(bp); | |
11516 | ||
11517 | bnx2x_init_func_obj(bp, &bp->func_obj, | |
11518 | bnx2x_sp(bp, func_rdata), | |
11519 | bnx2x_sp_mapping(bp, func_rdata), | |
a3348722 BW |
11520 | bnx2x_sp(bp, func_afex_rdata), |
11521 | bnx2x_sp_mapping(bp, func_afex_rdata), | |
619c5cb6 VZ |
11522 | &bnx2x_func_sp_drv); |
11523 | } | |
11524 | ||
11525 | /* must be called after sriov-enable */ | |
6383c0b3 | 11526 | static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) |
523224a3 | 11527 | { |
6383c0b3 | 11528 | int cid_count = BNX2X_L2_CID_COUNT(bp); |
94a78b79 | 11529 | |
523224a3 DK |
11530 | #ifdef BCM_CNIC |
11531 | cid_count += CNIC_CID_MAX; | |
11532 | #endif | |
11533 | return roundup(cid_count, QM_CID_ROUND); | |
11534 | } | |
f85582f8 | 11535 | |
619c5cb6 | 11536 | /** |
6383c0b3 | 11537 | * bnx2x_get_num_none_def_sbs - return the number of none default SBs |
619c5cb6 VZ |
11538 | * |
11539 | * @dev: pci device | |
11540 | * | |
11541 | */ | |
6383c0b3 | 11542 | static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) |
619c5cb6 VZ |
11543 | { |
11544 | int pos; | |
11545 | u16 control; | |
11546 | ||
11547 | pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); | |
6383c0b3 AE |
11548 | |
11549 | /* | |
11550 | * If MSI-X is not supported - return number of SBs needed to support | |
11551 | * one fast path queue: one FP queue + SB for CNIC | |
11552 | */ | |
619c5cb6 | 11553 | if (!pos) |
6383c0b3 | 11554 | return 1 + CNIC_PRESENT; |
619c5cb6 | 11555 | |
6383c0b3 AE |
11556 | /* |
11557 | * The value in the PCI configuration space is the index of the last | |
11558 | * entry, namely one less than the actual size of the table, which is | |
11559 | * exactly what we want to return from this function: number of all SBs | |
11560 | * without the default SB. | |
11561 | */ | |
619c5cb6 | 11562 | pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); |
6383c0b3 | 11563 | return control & PCI_MSIX_FLAGS_QSIZE; |
619c5cb6 VZ |
11564 | } |
11565 | ||
a2fbb9ea ET |
11566 | static int __devinit bnx2x_init_one(struct pci_dev *pdev, |
11567 | const struct pci_device_id *ent) | |
11568 | { | |
a2fbb9ea ET |
11569 | struct net_device *dev = NULL; |
11570 | struct bnx2x *bp; | |
37f9ce62 | 11571 | int pcie_width, pcie_speed; |
6383c0b3 AE |
11572 | int rc, max_non_def_sbs; |
11573 | int rx_count, tx_count, rss_count; | |
11574 | /* | |
11575 | * An estimated maximum supported CoS number according to the chip | |
11576 | * version. | |
11577 | * We will try to roughly estimate the maximum number of CoSes this chip | |
11578 | * may support in order to minimize the memory allocated for Tx | |
11579 | * netdev_queue's. This number will be accurately calculated during the | |
11580 | * initialization of bp->max_cos based on the chip versions AND chip | |
11581 | * revision in the bnx2x_init_bp(). | |
11582 | */ | |
11583 | u8 max_cos_est = 0; | |
523224a3 | 11584 | |
f2e0899f DK |
11585 | switch (ent->driver_data) { |
11586 | case BCM57710: | |
11587 | case BCM57711: | |
11588 | case BCM57711E: | |
6383c0b3 AE |
11589 | max_cos_est = BNX2X_MULTI_TX_COS_E1X; |
11590 | break; | |
11591 | ||
f2e0899f | 11592 | case BCM57712: |
619c5cb6 | 11593 | case BCM57712_MF: |
6383c0b3 AE |
11594 | max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; |
11595 | break; | |
11596 | ||
619c5cb6 VZ |
11597 | case BCM57800: |
11598 | case BCM57800_MF: | |
11599 | case BCM57810: | |
11600 | case BCM57810_MF: | |
11601 | case BCM57840: | |
11602 | case BCM57840_MF: | |
7e8e02df BW |
11603 | case BCM57811: |
11604 | case BCM57811_MF: | |
6383c0b3 | 11605 | max_cos_est = BNX2X_MULTI_TX_COS_E3B0; |
f2e0899f | 11606 | break; |
a2fbb9ea | 11607 | |
f2e0899f DK |
11608 | default: |
11609 | pr_err("Unknown board_type (%ld), aborting\n", | |
11610 | ent->driver_data); | |
870634b0 | 11611 | return -ENODEV; |
f2e0899f DK |
11612 | } |
11613 | ||
6383c0b3 AE |
11614 | max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); |
11615 | ||
11616 | /* !!! FIXME !!! | |
11617 | * Do not allow the maximum SB count to grow above 16 | |
11618 | * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. | |
11619 | * We will use the FP_SB_MAX_E1x macro for this matter. | |
11620 | */ | |
11621 | max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); | |
11622 | ||
11623 | WARN_ON(!max_non_def_sbs); | |
11624 | ||
11625 | /* Maximum number of RSS queues: one IGU SB goes to CNIC */ | |
11626 | rss_count = max_non_def_sbs - CNIC_PRESENT; | |
11627 | ||
11628 | /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ | |
11629 | rx_count = rss_count + FCOE_PRESENT; | |
11630 | ||
11631 | /* | |
11632 | * Maximum number of netdev Tx queues: | |
11633 | * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 | |
11634 | */ | |
11635 | tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; | |
f85582f8 | 11636 | |
a2fbb9ea | 11637 | /* dev zeroed in init_etherdev */ |
6383c0b3 | 11638 | dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); |
41de8d4c | 11639 | if (!dev) |
a2fbb9ea ET |
11640 | return -ENOMEM; |
11641 | ||
a2fbb9ea | 11642 | bp = netdev_priv(dev); |
a2fbb9ea | 11643 | |
51c1a580 | 11644 | BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", |
6383c0b3 | 11645 | tx_count, rx_count); |
df4770de | 11646 | |
6383c0b3 AE |
11647 | bp->igu_sb_cnt = max_non_def_sbs; |
11648 | bp->msg_enable = debug; | |
11649 | pci_set_drvdata(pdev, dev); | |
523224a3 | 11650 | |
619c5cb6 | 11651 | rc = bnx2x_init_dev(pdev, dev, ent->driver_data); |
a2fbb9ea ET |
11652 | if (rc < 0) { |
11653 | free_netdev(dev); | |
11654 | return rc; | |
11655 | } | |
11656 | ||
51c1a580 | 11657 | BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs); |
619c5cb6 | 11658 | |
34f80b04 | 11659 | rc = bnx2x_init_bp(bp); |
693fc0d1 EG |
11660 | if (rc) |
11661 | goto init_one_exit; | |
11662 | ||
6383c0b3 AE |
11663 | /* |
11664 | * Map doorbels here as we need the real value of bp->max_cos which | |
11665 | * is initialized in bnx2x_init_bp(). | |
11666 | */ | |
11667 | bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), | |
11668 | min_t(u64, BNX2X_DB_SIZE(bp), | |
11669 | pci_resource_len(pdev, 2))); | |
11670 | if (!bp->doorbells) { | |
11671 | dev_err(&bp->pdev->dev, | |
11672 | "Cannot map doorbell space, aborting\n"); | |
11673 | rc = -ENOMEM; | |
11674 | goto init_one_exit; | |
11675 | } | |
11676 | ||
523224a3 | 11677 | /* calc qm_cid_count */ |
6383c0b3 | 11678 | bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); |
523224a3 | 11679 | |
ec6ba945 | 11680 | #ifdef BCM_CNIC |
62ac0dc9 DK |
11681 | /* disable FCOE L2 queue for E1x */ |
11682 | if (CHIP_IS_E1x(bp)) | |
ec6ba945 VZ |
11683 | bp->flags |= NO_FCOE_FLAG; |
11684 | ||
11685 | #endif | |
11686 | ||
25985edc | 11687 | /* Configure interrupt mode: try to enable MSI-X/MSI if |
d6214d7a DK |
11688 | * needed, set bp->num_queues appropriately. |
11689 | */ | |
11690 | bnx2x_set_int_mode(bp); | |
11691 | ||
11692 | /* Add all NAPI objects */ | |
11693 | bnx2x_add_all_napi(bp); | |
11694 | ||
b340007f VZ |
11695 | rc = register_netdev(dev); |
11696 | if (rc) { | |
11697 | dev_err(&pdev->dev, "Cannot register net device\n"); | |
11698 | goto init_one_exit; | |
11699 | } | |
11700 | ||
ec6ba945 VZ |
11701 | #ifdef BCM_CNIC |
11702 | if (!NO_FCOE(bp)) { | |
11703 | /* Add storage MAC address */ | |
11704 | rtnl_lock(); | |
11705 | dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
11706 | rtnl_unlock(); | |
11707 | } | |
11708 | #endif | |
11709 | ||
37f9ce62 | 11710 | bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); |
d6214d7a | 11711 | |
51c1a580 MS |
11712 | BNX2X_DEV_INFO( |
11713 | "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", | |
94f05b0f JP |
11714 | board_info[ent->driver_data].name, |
11715 | (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), | |
11716 | pcie_width, | |
11717 | ((!CHIP_IS_E2(bp) && pcie_speed == 2) || | |
11718 | (CHIP_IS_E2(bp) && pcie_speed == 1)) ? | |
11719 | "5GHz (Gen2)" : "2.5GHz", | |
11720 | dev->base_addr, bp->pdev->irq, dev->dev_addr); | |
c016201c | 11721 | |
a2fbb9ea | 11722 | return 0; |
34f80b04 EG |
11723 | |
11724 | init_one_exit: | |
11725 | if (bp->regview) | |
11726 | iounmap(bp->regview); | |
11727 | ||
11728 | if (bp->doorbells) | |
11729 | iounmap(bp->doorbells); | |
11730 | ||
11731 | free_netdev(dev); | |
11732 | ||
11733 | if (atomic_read(&pdev->enable_cnt) == 1) | |
11734 | pci_release_regions(pdev); | |
11735 | ||
11736 | pci_disable_device(pdev); | |
11737 | pci_set_drvdata(pdev, NULL); | |
11738 | ||
11739 | return rc; | |
a2fbb9ea ET |
11740 | } |
11741 | ||
11742 | static void __devexit bnx2x_remove_one(struct pci_dev *pdev) | |
11743 | { | |
11744 | struct net_device *dev = pci_get_drvdata(pdev); | |
228241eb ET |
11745 | struct bnx2x *bp; |
11746 | ||
11747 | if (!dev) { | |
cdaa7cb8 | 11748 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); |
228241eb ET |
11749 | return; |
11750 | } | |
228241eb | 11751 | bp = netdev_priv(dev); |
a2fbb9ea | 11752 | |
ec6ba945 VZ |
11753 | #ifdef BCM_CNIC |
11754 | /* Delete storage MAC address */ | |
11755 | if (!NO_FCOE(bp)) { | |
11756 | rtnl_lock(); | |
11757 | dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
11758 | rtnl_unlock(); | |
11759 | } | |
11760 | #endif | |
11761 | ||
98507672 SR |
11762 | #ifdef BCM_DCBNL |
11763 | /* Delete app tlvs from dcbnl */ | |
11764 | bnx2x_dcbnl_update_applist(bp, true); | |
11765 | #endif | |
11766 | ||
a2fbb9ea ET |
11767 | unregister_netdev(dev); |
11768 | ||
d6214d7a DK |
11769 | /* Delete all NAPI objects */ |
11770 | bnx2x_del_all_napi(bp); | |
11771 | ||
084d6cbb VZ |
11772 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
11773 | bnx2x_set_power_state(bp, PCI_D0); | |
11774 | ||
d6214d7a DK |
11775 | /* Disable MSI/MSI-X */ |
11776 | bnx2x_disable_msi(bp); | |
f85582f8 | 11777 | |
084d6cbb VZ |
11778 | /* Power off */ |
11779 | bnx2x_set_power_state(bp, PCI_D3hot); | |
11780 | ||
72fd0718 | 11781 | /* Make sure RESET task is not scheduled before continuing */ |
7be08a72 | 11782 | cancel_delayed_work_sync(&bp->sp_rtnl_task); |
72fd0718 | 11783 | |
a2fbb9ea ET |
11784 | if (bp->regview) |
11785 | iounmap(bp->regview); | |
11786 | ||
11787 | if (bp->doorbells) | |
11788 | iounmap(bp->doorbells); | |
11789 | ||
eb2afd4a DK |
11790 | bnx2x_release_firmware(bp); |
11791 | ||
523224a3 DK |
11792 | bnx2x_free_mem_bp(bp); |
11793 | ||
a2fbb9ea | 11794 | free_netdev(dev); |
34f80b04 EG |
11795 | |
11796 | if (atomic_read(&pdev->enable_cnt) == 1) | |
11797 | pci_release_regions(pdev); | |
11798 | ||
a2fbb9ea ET |
11799 | pci_disable_device(pdev); |
11800 | pci_set_drvdata(pdev, NULL); | |
11801 | } | |
11802 | ||
f8ef6e44 YG |
11803 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
11804 | { | |
11805 | int i; | |
11806 | ||
11807 | bp->state = BNX2X_STATE_ERROR; | |
11808 | ||
11809 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
11810 | ||
619c5cb6 VZ |
11811 | #ifdef BCM_CNIC |
11812 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); | |
11813 | #endif | |
11814 | /* Stop Tx */ | |
11815 | bnx2x_tx_disable(bp); | |
11816 | ||
f8ef6e44 YG |
11817 | bnx2x_netif_stop(bp, 0); |
11818 | ||
11819 | del_timer_sync(&bp->timer); | |
619c5cb6 VZ |
11820 | |
11821 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
f8ef6e44 YG |
11822 | |
11823 | /* Release IRQs */ | |
d6214d7a | 11824 | bnx2x_free_irq(bp); |
f8ef6e44 | 11825 | |
f8ef6e44 YG |
11826 | /* Free SKBs, SGEs, TPA pool and driver internals */ |
11827 | bnx2x_free_skbs(bp); | |
523224a3 | 11828 | |
ec6ba945 | 11829 | for_each_rx_queue(bp, i) |
f8ef6e44 | 11830 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); |
d6214d7a | 11831 | |
f8ef6e44 YG |
11832 | bnx2x_free_mem(bp); |
11833 | ||
11834 | bp->state = BNX2X_STATE_CLOSED; | |
11835 | ||
619c5cb6 VZ |
11836 | netif_carrier_off(bp->dev); |
11837 | ||
f8ef6e44 YG |
11838 | return 0; |
11839 | } | |
11840 | ||
11841 | static void bnx2x_eeh_recover(struct bnx2x *bp) | |
11842 | { | |
11843 | u32 val; | |
11844 | ||
11845 | mutex_init(&bp->port.phy_mutex); | |
11846 | ||
f8ef6e44 YG |
11847 | |
11848 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
11849 | if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
11850 | != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
11851 | BNX2X_ERR("BAD MCP validity signature\n"); | |
f8ef6e44 YG |
11852 | } |
11853 | ||
493adb1f WX |
11854 | /** |
11855 | * bnx2x_io_error_detected - called when PCI error is detected | |
11856 | * @pdev: Pointer to PCI device | |
11857 | * @state: The current pci connection state | |
11858 | * | |
11859 | * This function is called after a PCI bus error affecting | |
11860 | * this device has been detected. | |
11861 | */ | |
11862 | static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, | |
11863 | pci_channel_state_t state) | |
11864 | { | |
11865 | struct net_device *dev = pci_get_drvdata(pdev); | |
11866 | struct bnx2x *bp = netdev_priv(dev); | |
11867 | ||
11868 | rtnl_lock(); | |
11869 | ||
11870 | netif_device_detach(dev); | |
11871 | ||
07ce50e4 DN |
11872 | if (state == pci_channel_io_perm_failure) { |
11873 | rtnl_unlock(); | |
11874 | return PCI_ERS_RESULT_DISCONNECT; | |
11875 | } | |
11876 | ||
493adb1f | 11877 | if (netif_running(dev)) |
f8ef6e44 | 11878 | bnx2x_eeh_nic_unload(bp); |
493adb1f WX |
11879 | |
11880 | pci_disable_device(pdev); | |
11881 | ||
11882 | rtnl_unlock(); | |
11883 | ||
11884 | /* Request a slot reset */ | |
11885 | return PCI_ERS_RESULT_NEED_RESET; | |
11886 | } | |
11887 | ||
11888 | /** | |
11889 | * bnx2x_io_slot_reset - called after the PCI bus has been reset | |
11890 | * @pdev: Pointer to PCI device | |
11891 | * | |
11892 | * Restart the card from scratch, as if from a cold-boot. | |
11893 | */ | |
11894 | static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) | |
11895 | { | |
11896 | struct net_device *dev = pci_get_drvdata(pdev); | |
11897 | struct bnx2x *bp = netdev_priv(dev); | |
11898 | ||
11899 | rtnl_lock(); | |
11900 | ||
11901 | if (pci_enable_device(pdev)) { | |
11902 | dev_err(&pdev->dev, | |
11903 | "Cannot re-enable PCI device after reset\n"); | |
11904 | rtnl_unlock(); | |
11905 | return PCI_ERS_RESULT_DISCONNECT; | |
11906 | } | |
11907 | ||
11908 | pci_set_master(pdev); | |
11909 | pci_restore_state(pdev); | |
11910 | ||
11911 | if (netif_running(dev)) | |
11912 | bnx2x_set_power_state(bp, PCI_D0); | |
11913 | ||
11914 | rtnl_unlock(); | |
11915 | ||
11916 | return PCI_ERS_RESULT_RECOVERED; | |
11917 | } | |
11918 | ||
11919 | /** | |
11920 | * bnx2x_io_resume - called when traffic can start flowing again | |
11921 | * @pdev: Pointer to PCI device | |
11922 | * | |
11923 | * This callback is called when the error recovery driver tells us that | |
11924 | * its OK to resume normal operation. | |
11925 | */ | |
11926 | static void bnx2x_io_resume(struct pci_dev *pdev) | |
11927 | { | |
11928 | struct net_device *dev = pci_get_drvdata(pdev); | |
11929 | struct bnx2x *bp = netdev_priv(dev); | |
11930 | ||
72fd0718 | 11931 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
51c1a580 | 11932 | netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); |
72fd0718 VZ |
11933 | return; |
11934 | } | |
11935 | ||
493adb1f WX |
11936 | rtnl_lock(); |
11937 | ||
f8ef6e44 YG |
11938 | bnx2x_eeh_recover(bp); |
11939 | ||
493adb1f | 11940 | if (netif_running(dev)) |
f8ef6e44 | 11941 | bnx2x_nic_load(bp, LOAD_NORMAL); |
493adb1f WX |
11942 | |
11943 | netif_device_attach(dev); | |
11944 | ||
11945 | rtnl_unlock(); | |
11946 | } | |
11947 | ||
11948 | static struct pci_error_handlers bnx2x_err_handler = { | |
11949 | .error_detected = bnx2x_io_error_detected, | |
356e2385 EG |
11950 | .slot_reset = bnx2x_io_slot_reset, |
11951 | .resume = bnx2x_io_resume, | |
493adb1f WX |
11952 | }; |
11953 | ||
a2fbb9ea | 11954 | static struct pci_driver bnx2x_pci_driver = { |
493adb1f WX |
11955 | .name = DRV_MODULE_NAME, |
11956 | .id_table = bnx2x_pci_tbl, | |
11957 | .probe = bnx2x_init_one, | |
11958 | .remove = __devexit_p(bnx2x_remove_one), | |
11959 | .suspend = bnx2x_suspend, | |
11960 | .resume = bnx2x_resume, | |
11961 | .err_handler = &bnx2x_err_handler, | |
a2fbb9ea ET |
11962 | }; |
11963 | ||
11964 | static int __init bnx2x_init(void) | |
11965 | { | |
dd21ca6d SG |
11966 | int ret; |
11967 | ||
7995c64e | 11968 | pr_info("%s", version); |
938cf541 | 11969 | |
1cf167f2 EG |
11970 | bnx2x_wq = create_singlethread_workqueue("bnx2x"); |
11971 | if (bnx2x_wq == NULL) { | |
7995c64e | 11972 | pr_err("Cannot create workqueue\n"); |
1cf167f2 EG |
11973 | return -ENOMEM; |
11974 | } | |
11975 | ||
dd21ca6d SG |
11976 | ret = pci_register_driver(&bnx2x_pci_driver); |
11977 | if (ret) { | |
7995c64e | 11978 | pr_err("Cannot register driver\n"); |
dd21ca6d SG |
11979 | destroy_workqueue(bnx2x_wq); |
11980 | } | |
11981 | return ret; | |
a2fbb9ea ET |
11982 | } |
11983 | ||
11984 | static void __exit bnx2x_cleanup(void) | |
11985 | { | |
452427b0 | 11986 | struct list_head *pos, *q; |
a2fbb9ea | 11987 | pci_unregister_driver(&bnx2x_pci_driver); |
1cf167f2 EG |
11988 | |
11989 | destroy_workqueue(bnx2x_wq); | |
452427b0 YM |
11990 | |
11991 | /* Free globablly allocated resources */ | |
11992 | list_for_each_safe(pos, q, &bnx2x_prev_list) { | |
11993 | struct bnx2x_prev_path_list *tmp = | |
11994 | list_entry(pos, struct bnx2x_prev_path_list, list); | |
11995 | list_del(pos); | |
11996 | kfree(tmp); | |
11997 | } | |
a2fbb9ea ET |
11998 | } |
11999 | ||
3deb8167 YR |
12000 | void bnx2x_notify_link_changed(struct bnx2x *bp) |
12001 | { | |
12002 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); | |
12003 | } | |
12004 | ||
a2fbb9ea ET |
12005 | module_init(bnx2x_init); |
12006 | module_exit(bnx2x_cleanup); | |
12007 | ||
993ac7b5 | 12008 | #ifdef BCM_CNIC |
619c5cb6 VZ |
12009 | /** |
12010 | * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). | |
12011 | * | |
12012 | * @bp: driver handle | |
12013 | * @set: set or clear the CAM entry | |
12014 | * | |
12015 | * This function will wait until the ramdord completion returns. | |
12016 | * Return 0 if success, -ENODEV if ramrod doesn't return. | |
12017 | */ | |
12018 | static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) | |
12019 | { | |
12020 | unsigned long ramrod_flags = 0; | |
12021 | ||
12022 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
12023 | return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, | |
12024 | &bp->iscsi_l2_mac_obj, true, | |
12025 | BNX2X_ISCSI_ETH_MAC, &ramrod_flags); | |
12026 | } | |
993ac7b5 MC |
12027 | |
12028 | /* count denotes the number of new completions we have seen */ | |
12029 | static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) | |
12030 | { | |
12031 | struct eth_spe *spe; | |
12032 | ||
12033 | #ifdef BNX2X_STOP_ON_ERROR | |
12034 | if (unlikely(bp->panic)) | |
12035 | return; | |
12036 | #endif | |
12037 | ||
12038 | spin_lock_bh(&bp->spq_lock); | |
c2bff63f | 12039 | BUG_ON(bp->cnic_spq_pending < count); |
993ac7b5 MC |
12040 | bp->cnic_spq_pending -= count; |
12041 | ||
993ac7b5 | 12042 | |
c2bff63f DK |
12043 | for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { |
12044 | u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) | |
12045 | & SPE_HDR_CONN_TYPE) >> | |
12046 | SPE_HDR_CONN_TYPE_SHIFT; | |
619c5cb6 VZ |
12047 | u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) |
12048 | >> SPE_HDR_CMD_ID_SHIFT) & 0xff; | |
c2bff63f DK |
12049 | |
12050 | /* Set validation for iSCSI L2 client before sending SETUP | |
12051 | * ramrod | |
12052 | */ | |
12053 | if (type == ETH_CONNECTION_TYPE) { | |
c2bff63f | 12054 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) |
619c5cb6 VZ |
12055 | bnx2x_set_ctx_validation(bp, &bp->context. |
12056 | vcxt[BNX2X_ISCSI_ETH_CID].eth, | |
12057 | BNX2X_ISCSI_ETH_CID); | |
c2bff63f DK |
12058 | } |
12059 | ||
619c5cb6 VZ |
12060 | /* |
12061 | * There may be not more than 8 L2, not more than 8 L5 SPEs | |
12062 | * and in the air. We also check that number of outstanding | |
6e30dd4e VZ |
12063 | * COMMON ramrods is not more than the EQ and SPQ can |
12064 | * accommodate. | |
c2bff63f | 12065 | */ |
6e30dd4e VZ |
12066 | if (type == ETH_CONNECTION_TYPE) { |
12067 | if (!atomic_read(&bp->cq_spq_left)) | |
12068 | break; | |
12069 | else | |
12070 | atomic_dec(&bp->cq_spq_left); | |
12071 | } else if (type == NONE_CONNECTION_TYPE) { | |
12072 | if (!atomic_read(&bp->eq_spq_left)) | |
c2bff63f DK |
12073 | break; |
12074 | else | |
6e30dd4e | 12075 | atomic_dec(&bp->eq_spq_left); |
ec6ba945 VZ |
12076 | } else if ((type == ISCSI_CONNECTION_TYPE) || |
12077 | (type == FCOE_CONNECTION_TYPE)) { | |
c2bff63f DK |
12078 | if (bp->cnic_spq_pending >= |
12079 | bp->cnic_eth_dev.max_kwqe_pending) | |
12080 | break; | |
12081 | else | |
12082 | bp->cnic_spq_pending++; | |
12083 | } else { | |
12084 | BNX2X_ERR("Unknown SPE type: %d\n", type); | |
12085 | bnx2x_panic(); | |
993ac7b5 | 12086 | break; |
c2bff63f | 12087 | } |
993ac7b5 MC |
12088 | |
12089 | spe = bnx2x_sp_get_next(bp); | |
12090 | *spe = *bp->cnic_kwq_cons; | |
12091 | ||
51c1a580 | 12092 | DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", |
993ac7b5 MC |
12093 | bp->cnic_spq_pending, bp->cnic_kwq_pending, count); |
12094 | ||
12095 | if (bp->cnic_kwq_cons == bp->cnic_kwq_last) | |
12096 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
12097 | else | |
12098 | bp->cnic_kwq_cons++; | |
12099 | } | |
12100 | bnx2x_sp_prod_update(bp); | |
12101 | spin_unlock_bh(&bp->spq_lock); | |
12102 | } | |
12103 | ||
12104 | static int bnx2x_cnic_sp_queue(struct net_device *dev, | |
12105 | struct kwqe_16 *kwqes[], u32 count) | |
12106 | { | |
12107 | struct bnx2x *bp = netdev_priv(dev); | |
12108 | int i; | |
12109 | ||
12110 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 MS |
12111 | if (unlikely(bp->panic)) { |
12112 | BNX2X_ERR("Can't post to SP queue while panic\n"); | |
993ac7b5 | 12113 | return -EIO; |
51c1a580 | 12114 | } |
993ac7b5 MC |
12115 | #endif |
12116 | ||
95c6c616 AE |
12117 | if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && |
12118 | (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
51c1a580 | 12119 | BNX2X_ERR("Handling parity error recovery. Try again later\n"); |
95c6c616 AE |
12120 | return -EAGAIN; |
12121 | } | |
12122 | ||
993ac7b5 MC |
12123 | spin_lock_bh(&bp->spq_lock); |
12124 | ||
12125 | for (i = 0; i < count; i++) { | |
12126 | struct eth_spe *spe = (struct eth_spe *)kwqes[i]; | |
12127 | ||
12128 | if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) | |
12129 | break; | |
12130 | ||
12131 | *bp->cnic_kwq_prod = *spe; | |
12132 | ||
12133 | bp->cnic_kwq_pending++; | |
12134 | ||
51c1a580 | 12135 | DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", |
993ac7b5 | 12136 | spe->hdr.conn_and_cmd_data, spe->hdr.type, |
523224a3 DK |
12137 | spe->data.update_data_addr.hi, |
12138 | spe->data.update_data_addr.lo, | |
993ac7b5 MC |
12139 | bp->cnic_kwq_pending); |
12140 | ||
12141 | if (bp->cnic_kwq_prod == bp->cnic_kwq_last) | |
12142 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
12143 | else | |
12144 | bp->cnic_kwq_prod++; | |
12145 | } | |
12146 | ||
12147 | spin_unlock_bh(&bp->spq_lock); | |
12148 | ||
12149 | if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) | |
12150 | bnx2x_cnic_sp_post(bp, 0); | |
12151 | ||
12152 | return i; | |
12153 | } | |
12154 | ||
12155 | static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
12156 | { | |
12157 | struct cnic_ops *c_ops; | |
12158 | int rc = 0; | |
12159 | ||
12160 | mutex_lock(&bp->cnic_mutex); | |
13707f9e ED |
12161 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
12162 | lockdep_is_held(&bp->cnic_mutex)); | |
993ac7b5 MC |
12163 | if (c_ops) |
12164 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
12165 | mutex_unlock(&bp->cnic_mutex); | |
12166 | ||
12167 | return rc; | |
12168 | } | |
12169 | ||
12170 | static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
12171 | { | |
12172 | struct cnic_ops *c_ops; | |
12173 | int rc = 0; | |
12174 | ||
12175 | rcu_read_lock(); | |
12176 | c_ops = rcu_dereference(bp->cnic_ops); | |
12177 | if (c_ops) | |
12178 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
12179 | rcu_read_unlock(); | |
12180 | ||
12181 | return rc; | |
12182 | } | |
12183 | ||
12184 | /* | |
12185 | * for commands that have no data | |
12186 | */ | |
9f6c9258 | 12187 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) |
993ac7b5 MC |
12188 | { |
12189 | struct cnic_ctl_info ctl = {0}; | |
12190 | ||
12191 | ctl.cmd = cmd; | |
12192 | ||
12193 | return bnx2x_cnic_ctl_send(bp, &ctl); | |
12194 | } | |
12195 | ||
619c5cb6 | 12196 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) |
993ac7b5 | 12197 | { |
619c5cb6 | 12198 | struct cnic_ctl_info ctl = {0}; |
993ac7b5 MC |
12199 | |
12200 | /* first we tell CNIC and only then we count this as a completion */ | |
12201 | ctl.cmd = CNIC_CTL_COMPLETION_CMD; | |
12202 | ctl.data.comp.cid = cid; | |
619c5cb6 | 12203 | ctl.data.comp.error = err; |
993ac7b5 MC |
12204 | |
12205 | bnx2x_cnic_ctl_send_bh(bp, &ctl); | |
c2bff63f | 12206 | bnx2x_cnic_sp_post(bp, 0); |
993ac7b5 MC |
12207 | } |
12208 | ||
619c5cb6 VZ |
12209 | |
12210 | /* Called with netif_addr_lock_bh() taken. | |
12211 | * Sets an rx_mode config for an iSCSI ETH client. | |
12212 | * Doesn't block. | |
12213 | * Completion should be checked outside. | |
12214 | */ | |
12215 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) | |
12216 | { | |
12217 | unsigned long accept_flags = 0, ramrod_flags = 0; | |
12218 | u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
12219 | int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; | |
12220 | ||
12221 | if (start) { | |
12222 | /* Start accepting on iSCSI L2 ring. Accept all multicasts | |
12223 | * because it's the only way for UIO Queue to accept | |
12224 | * multicasts (in non-promiscuous mode only one Queue per | |
12225 | * function will receive multicast packets (leading in our | |
12226 | * case). | |
12227 | */ | |
12228 | __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); | |
12229 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); | |
12230 | __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); | |
12231 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
12232 | ||
12233 | /* Clear STOP_PENDING bit if START is requested */ | |
12234 | clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); | |
12235 | ||
12236 | sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; | |
12237 | } else | |
12238 | /* Clear START_PENDING bit if STOP is requested */ | |
12239 | clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); | |
12240 | ||
12241 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
12242 | set_bit(sched_state, &bp->sp_state); | |
12243 | else { | |
12244 | __set_bit(RAMROD_RX, &ramrod_flags); | |
12245 | bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, | |
12246 | ramrod_flags); | |
12247 | } | |
12248 | } | |
12249 | ||
12250 | ||
993ac7b5 MC |
12251 | static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) |
12252 | { | |
12253 | struct bnx2x *bp = netdev_priv(dev); | |
12254 | int rc = 0; | |
12255 | ||
12256 | switch (ctl->cmd) { | |
12257 | case DRV_CTL_CTXTBL_WR_CMD: { | |
12258 | u32 index = ctl->data.io.offset; | |
12259 | dma_addr_t addr = ctl->data.io.dma_addr; | |
12260 | ||
12261 | bnx2x_ilt_wr(bp, index, addr); | |
12262 | break; | |
12263 | } | |
12264 | ||
c2bff63f DK |
12265 | case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { |
12266 | int count = ctl->data.credit.credit_count; | |
993ac7b5 MC |
12267 | |
12268 | bnx2x_cnic_sp_post(bp, count); | |
12269 | break; | |
12270 | } | |
12271 | ||
12272 | /* rtnl_lock is held. */ | |
12273 | case DRV_CTL_START_L2_CMD: { | |
619c5cb6 VZ |
12274 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
12275 | unsigned long sp_bits = 0; | |
12276 | ||
12277 | /* Configure the iSCSI classification object */ | |
12278 | bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, | |
12279 | cp->iscsi_l2_client_id, | |
12280 | cp->iscsi_l2_cid, BP_FUNC(bp), | |
12281 | bnx2x_sp(bp, mac_rdata), | |
12282 | bnx2x_sp_mapping(bp, mac_rdata), | |
12283 | BNX2X_FILTER_MAC_PENDING, | |
12284 | &bp->sp_state, BNX2X_OBJ_TYPE_RX, | |
12285 | &bp->macs_pool); | |
ec6ba945 | 12286 | |
523224a3 | 12287 | /* Set iSCSI MAC address */ |
619c5cb6 VZ |
12288 | rc = bnx2x_set_iscsi_eth_mac_addr(bp); |
12289 | if (rc) | |
12290 | break; | |
523224a3 DK |
12291 | |
12292 | mmiowb(); | |
12293 | barrier(); | |
12294 | ||
619c5cb6 VZ |
12295 | /* Start accepting on iSCSI L2 ring */ |
12296 | ||
12297 | netif_addr_lock_bh(dev); | |
12298 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
12299 | netif_addr_unlock_bh(dev); | |
12300 | ||
12301 | /* bits to wait on */ | |
12302 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
12303 | __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); | |
12304 | ||
12305 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
12306 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 | 12307 | |
993ac7b5 MC |
12308 | break; |
12309 | } | |
12310 | ||
12311 | /* rtnl_lock is held. */ | |
12312 | case DRV_CTL_STOP_L2_CMD: { | |
619c5cb6 | 12313 | unsigned long sp_bits = 0; |
993ac7b5 | 12314 | |
523224a3 | 12315 | /* Stop accepting on iSCSI L2 ring */ |
619c5cb6 VZ |
12316 | netif_addr_lock_bh(dev); |
12317 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
12318 | netif_addr_unlock_bh(dev); | |
12319 | ||
12320 | /* bits to wait on */ | |
12321 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
12322 | __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); | |
12323 | ||
12324 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
12325 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 DK |
12326 | |
12327 | mmiowb(); | |
12328 | barrier(); | |
12329 | ||
12330 | /* Unset iSCSI L2 MAC */ | |
619c5cb6 VZ |
12331 | rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, |
12332 | BNX2X_ISCSI_ETH_MAC, true); | |
993ac7b5 MC |
12333 | break; |
12334 | } | |
c2bff63f DK |
12335 | case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { |
12336 | int count = ctl->data.credit.credit_count; | |
12337 | ||
12338 | smp_mb__before_atomic_inc(); | |
6e30dd4e | 12339 | atomic_add(count, &bp->cq_spq_left); |
c2bff63f DK |
12340 | smp_mb__after_atomic_inc(); |
12341 | break; | |
12342 | } | |
1d187b34 BW |
12343 | case DRV_CTL_ULP_REGISTER_CMD: { |
12344 | int ulp_type = ctl->data.ulp_type; | |
12345 | ||
12346 | if (CHIP_IS_E3(bp)) { | |
12347 | int idx = BP_FW_MB_IDX(bp); | |
12348 | u32 cap; | |
12349 | ||
12350 | cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); | |
12351 | if (ulp_type == CNIC_ULP_ISCSI) | |
12352 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
12353 | else if (ulp_type == CNIC_ULP_FCOE) | |
12354 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
12355 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
12356 | } | |
12357 | break; | |
12358 | } | |
12359 | case DRV_CTL_ULP_UNREGISTER_CMD: { | |
12360 | int ulp_type = ctl->data.ulp_type; | |
12361 | ||
12362 | if (CHIP_IS_E3(bp)) { | |
12363 | int idx = BP_FW_MB_IDX(bp); | |
12364 | u32 cap; | |
12365 | ||
12366 | cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); | |
12367 | if (ulp_type == CNIC_ULP_ISCSI) | |
12368 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
12369 | else if (ulp_type == CNIC_ULP_FCOE) | |
12370 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
12371 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
12372 | } | |
12373 | break; | |
12374 | } | |
993ac7b5 MC |
12375 | |
12376 | default: | |
12377 | BNX2X_ERR("unknown command %x\n", ctl->cmd); | |
12378 | rc = -EINVAL; | |
12379 | } | |
12380 | ||
12381 | return rc; | |
12382 | } | |
12383 | ||
9f6c9258 | 12384 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) |
993ac7b5 MC |
12385 | { |
12386 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12387 | ||
12388 | if (bp->flags & USING_MSIX_FLAG) { | |
12389 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
12390 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
12391 | cp->irq_arr[0].vector = bp->msix_table[1].vector; | |
12392 | } else { | |
12393 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
12394 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
12395 | } | |
619c5cb6 | 12396 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
12397 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; |
12398 | else | |
12399 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; | |
12400 | ||
619c5cb6 VZ |
12401 | cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); |
12402 | cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); | |
993ac7b5 MC |
12403 | cp->irq_arr[1].status_blk = bp->def_status_blk; |
12404 | cp->irq_arr[1].status_blk_num = DEF_SB_ID; | |
523224a3 | 12405 | cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; |
993ac7b5 MC |
12406 | |
12407 | cp->num_irq = 2; | |
12408 | } | |
12409 | ||
12410 | static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, | |
12411 | void *data) | |
12412 | { | |
12413 | struct bnx2x *bp = netdev_priv(dev); | |
12414 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12415 | ||
51c1a580 MS |
12416 | if (ops == NULL) { |
12417 | BNX2X_ERR("NULL ops received\n"); | |
993ac7b5 | 12418 | return -EINVAL; |
51c1a580 | 12419 | } |
993ac7b5 | 12420 | |
993ac7b5 MC |
12421 | bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); |
12422 | if (!bp->cnic_kwq) | |
12423 | return -ENOMEM; | |
12424 | ||
12425 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
12426 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
12427 | bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; | |
12428 | ||
12429 | bp->cnic_spq_pending = 0; | |
12430 | bp->cnic_kwq_pending = 0; | |
12431 | ||
12432 | bp->cnic_data = data; | |
12433 | ||
12434 | cp->num_irq = 0; | |
619c5cb6 | 12435 | cp->drv_state |= CNIC_DRV_STATE_REGD; |
523224a3 | 12436 | cp->iro_arr = bp->iro_arr; |
993ac7b5 | 12437 | |
993ac7b5 | 12438 | bnx2x_setup_cnic_irq_info(bp); |
c2bff63f | 12439 | |
993ac7b5 MC |
12440 | rcu_assign_pointer(bp->cnic_ops, ops); |
12441 | ||
12442 | return 0; | |
12443 | } | |
12444 | ||
12445 | static int bnx2x_unregister_cnic(struct net_device *dev) | |
12446 | { | |
12447 | struct bnx2x *bp = netdev_priv(dev); | |
12448 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12449 | ||
12450 | mutex_lock(&bp->cnic_mutex); | |
993ac7b5 | 12451 | cp->drv_state = 0; |
2cfa5a04 | 12452 | RCU_INIT_POINTER(bp->cnic_ops, NULL); |
993ac7b5 MC |
12453 | mutex_unlock(&bp->cnic_mutex); |
12454 | synchronize_rcu(); | |
12455 | kfree(bp->cnic_kwq); | |
12456 | bp->cnic_kwq = NULL; | |
12457 | ||
12458 | return 0; | |
12459 | } | |
12460 | ||
12461 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) | |
12462 | { | |
12463 | struct bnx2x *bp = netdev_priv(dev); | |
12464 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12465 | ||
2ba45142 VZ |
12466 | /* If both iSCSI and FCoE are disabled - return NULL in |
12467 | * order to indicate CNIC that it should not try to work | |
12468 | * with this device. | |
12469 | */ | |
12470 | if (NO_ISCSI(bp) && NO_FCOE(bp)) | |
12471 | return NULL; | |
12472 | ||
993ac7b5 MC |
12473 | cp->drv_owner = THIS_MODULE; |
12474 | cp->chip_id = CHIP_ID(bp); | |
12475 | cp->pdev = bp->pdev; | |
12476 | cp->io_base = bp->regview; | |
12477 | cp->io_base2 = bp->doorbells; | |
12478 | cp->max_kwqe_pending = 8; | |
523224a3 | 12479 | cp->ctx_blk_size = CDU_ILT_PAGE_SZ; |
c2bff63f DK |
12480 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
12481 | bnx2x_cid_ilt_lines(bp); | |
993ac7b5 | 12482 | cp->ctx_tbl_len = CNIC_ILT_LINES; |
c2bff63f | 12483 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
993ac7b5 MC |
12484 | cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; |
12485 | cp->drv_ctl = bnx2x_drv_ctl; | |
12486 | cp->drv_register_cnic = bnx2x_register_cnic; | |
12487 | cp->drv_unregister_cnic = bnx2x_unregister_cnic; | |
ec6ba945 | 12488 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; |
619c5cb6 VZ |
12489 | cp->iscsi_l2_client_id = |
12490 | bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
c2bff63f DK |
12491 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; |
12492 | ||
2ba45142 VZ |
12493 | if (NO_ISCSI_OOO(bp)) |
12494 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
12495 | ||
12496 | if (NO_ISCSI(bp)) | |
12497 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; | |
12498 | ||
12499 | if (NO_FCOE(bp)) | |
12500 | cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; | |
12501 | ||
51c1a580 MS |
12502 | BNX2X_DEV_INFO( |
12503 | "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", | |
c2bff63f DK |
12504 | cp->ctx_blk_size, |
12505 | cp->ctx_tbl_offset, | |
12506 | cp->ctx_tbl_len, | |
12507 | cp->starting_cid); | |
993ac7b5 MC |
12508 | return cp; |
12509 | } | |
12510 | EXPORT_SYMBOL(bnx2x_cnic_probe); | |
12511 | ||
12512 | #endif /* BCM_CNIC */ | |
94a78b79 | 12513 |