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bnx2x: save RAM in kdump kernel by using a single queue
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
f1deab50
JP		 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
a2fbb9ea
ET		 20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/device.h> /* for dev_info() */
24#include <linux/timer.h>
25#include <linux/errno.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
a2fbb9ea
ET		 28#include <linux/interrupt.h>
29#include <linux/pci.h>
33d8e6a5 30#include <linux/aer.h>
a2fbb9ea
ET		 31#include <linux/init.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/dma-mapping.h>
36#include <linux/bitops.h>
37#include <linux/irq.h>
38#include <linux/delay.h>
39#include <asm/byteorder.h>
40#include <linux/time.h>
41#include <linux/ethtool.h>
42#include <linux/mii.h>
0c6671b0 43#include <linux/if_vlan.h>
a2fbb9ea 44#include <net/ip.h>
619c5cb6 45#include <net/ipv6.h>
a2fbb9ea
ET		 46#include <net/tcp.h>
47#include <net/checksum.h>
34f80b04 48#include <net/ip6_checksum.h>
a2fbb9ea
ET		 49#include <linux/workqueue.h>
50#include <linux/crc32.h>
34f80b04 51#include <linux/crc32c.h>
a2fbb9ea
ET		 52#include <linux/prefetch.h>
53#include <linux/zlib.h>
a2fbb9ea 54#include <linux/io.h>
452427b0 55#include <linux/semaphore.h>
45229b42 56#include <linux/stringify.h>
7ab24bfd 57#include <linux/vmalloc.h>
a2fbb9ea 58
a2fbb9ea
ET		 59#include "bnx2x.h"
60#include "bnx2x_init.h"
94a78b79 61#include "bnx2x_init_ops.h"
9f6c9258 62#include "bnx2x_cmn.h"
1ab4434c 63#include "bnx2x_vfpf.h"
e4901dde 64#include "bnx2x_dcb.h"
042181f5 65#include "bnx2x_sp.h"
a2fbb9ea 66
94a78b79
VZ		 67#include <linux/firmware.h>
68#include "bnx2x_fw_file_hdr.h"
69/* FW files */
45229b42
BH		 70#define FW_FILE_VERSION \
71 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
72 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
73 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
74 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 75#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
76#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 77#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 78
34f80b04
EG		 79/* Time in jiffies before concluding the transmitter is hung */
80#define TX_TIMEOUT (5*HZ)
a2fbb9ea 81
0329aba1 82static char version[] =
619c5cb6 83 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 84 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
85
24e3fcef 86MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 87MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 88 "BCM57710/57711/57711E/"
89 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
90 "57840/57840_MF Driver");
a2fbb9ea
ET		 91MODULE_LICENSE("GPL");
92MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 93MODULE_FIRMWARE(FW_FILE_NAME_E1);
94MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 95MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 96
a8f47eb7 97int bnx2x_num_queues;
1c8bb760 98module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
96305234
DK		 99MODULE_PARM_DESC(num_queues,
100 " Set number of queues (default is as a number of CPUs)");
555f6c78 101
19680c48 102static int disable_tpa;
1c8bb760 103module_param(disable_tpa, int, S_IRUGO);
9898f86d 104MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 105
a8f47eb7 106static int int_mode;
1c8bb760 107module_param(int_mode, int, S_IRUGO);
619c5cb6 108MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 109 "(1 INT#x; 2 MSI)");
8badd27a 110
a18f5128 111static int dropless_fc;
1c8bb760 112module_param(dropless_fc, int, S_IRUGO);
a18f5128
EG		 113MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
114
8d5726c4 115static int mrrs = -1;
1c8bb760 116module_param(mrrs, int, S_IRUGO);
8d5726c4
EG		 117MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118
9898f86d 119static int debug;
1c8bb760 120module_param(debug, int, S_IRUGO);
9898f86d
EG		 121MODULE_PARM_DESC(debug, " Default debug msglevel");
122
619c5cb6 123struct workqueue_struct *bnx2x_wq;
ec6ba945 124
1ef1d45a
BW		 125struct bnx2x_mac_vals {
126 u32 xmac_addr;
127 u32 xmac_val;
128 u32 emac_addr;
129 u32 emac_val;
130 u32 umac_addr;
131 u32 umac_val;
132 u32 bmac_addr;
133 u32 bmac_val[2];
134};
135
a2fbb9ea
ET		 136enum bnx2x_board_type {
137 BCM57710 = 0,
619c5cb6
VZ		 138 BCM57711,
139 BCM57711E,
140 BCM57712,
141 BCM57712_MF,
1ab4434c 142 BCM57712_VF,
619c5cb6
VZ		 143 BCM57800,
144 BCM57800_MF,
1ab4434c 145 BCM57800_VF,
619c5cb6
VZ		 146 BCM57810,
147 BCM57810_MF,
1ab4434c 148 BCM57810_VF,
c3def943
YM		 149 BCM57840_4_10,
150 BCM57840_2_20,
7e8e02df 151 BCM57840_MF,
1ab4434c 152 BCM57840_VF,
7e8e02df 153 BCM57811,
1ab4434c
AE		 154 BCM57811_MF,
155 BCM57840_O,
156 BCM57840_MFO,
157 BCM57811_VF
a2fbb9ea
ET		 158};
159
34f80b04 160/* indexed by board_type, above */
53a10565 161static struct {
a2fbb9ea 162 char *name;
0329aba1 163} board_info[] = {
1ab4434c
AE		 164 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
165 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
166 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
167 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
168 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
169 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
170 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
171 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
172 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
173 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
174 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
175 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
176 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
177 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
178 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
179 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
180 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
181 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
182 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
183 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
184 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
a2fbb9ea
ET		 185};
186
619c5cb6
VZ		 187#ifndef PCI_DEVICE_ID_NX2_57710
188#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
189#endif
190#ifndef PCI_DEVICE_ID_NX2_57711
191#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
192#endif
193#ifndef PCI_DEVICE_ID_NX2_57711E
194#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
195#endif
196#ifndef PCI_DEVICE_ID_NX2_57712
197#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
198#endif
199#ifndef PCI_DEVICE_ID_NX2_57712_MF
200#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
201#endif
8395be5e
AE		 202#ifndef PCI_DEVICE_ID_NX2_57712_VF
203#define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
204#endif
619c5cb6
VZ		 205#ifndef PCI_DEVICE_ID_NX2_57800
206#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
207#endif
208#ifndef PCI_DEVICE_ID_NX2_57800_MF
209#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
210#endif
8395be5e
AE		 211#ifndef PCI_DEVICE_ID_NX2_57800_VF
212#define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
213#endif
619c5cb6
VZ		 214#ifndef PCI_DEVICE_ID_NX2_57810
215#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
216#endif
217#ifndef PCI_DEVICE_ID_NX2_57810_MF
218#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
219#endif
c3def943
YM		 220#ifndef PCI_DEVICE_ID_NX2_57840_O
221#define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
222#endif
8395be5e
AE		 223#ifndef PCI_DEVICE_ID_NX2_57810_VF
224#define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
225#endif
c3def943
YM		 226#ifndef PCI_DEVICE_ID_NX2_57840_4_10
227#define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
228#endif
229#ifndef PCI_DEVICE_ID_NX2_57840_2_20
230#define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
231#endif
232#ifndef PCI_DEVICE_ID_NX2_57840_MFO
233#define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
619c5cb6
VZ		 234#endif
235#ifndef PCI_DEVICE_ID_NX2_57840_MF
236#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
237#endif
8395be5e
AE		 238#ifndef PCI_DEVICE_ID_NX2_57840_VF
239#define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
240#endif
7e8e02df
BW		 241#ifndef PCI_DEVICE_ID_NX2_57811
242#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
243#endif
244#ifndef PCI_DEVICE_ID_NX2_57811_MF
245#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
246#endif
8395be5e
AE		 247#ifndef PCI_DEVICE_ID_NX2_57811_VF
248#define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
249#endif
250
a3aa1884 251static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 252 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
253 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
254 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6 256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
8395be5e 257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
619c5cb6
VZ		 258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
8395be5e 260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
619c5cb6
VZ		 261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
c3def943
YM		 263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
8395be5e 266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
c3def943 267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
619c5cb6 268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
8395be5e 269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
7e8e02df
BW		 270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
8395be5e 272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
a2fbb9ea
ET		 273 { 0 }
274};
275
276MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
277
452427b0
YM		 278/* Global resources for unloading a previously loaded device */
279#define BNX2X_PREV_WAIT_NEEDED 1
280static DEFINE_SEMAPHORE(bnx2x_prev_sem);
281static LIST_HEAD(bnx2x_prev_list);
a8f47eb7 282
283/* Forward declaration */
284static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
285static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
286static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
287
a2fbb9ea
ET		 288/****************************************************************************
289* General service functions
290****************************************************************************/
291
1191cb83 292static void __storm_memset_dma_mapping(struct bnx2x *bp,
619c5cb6
VZ		 293 u32 addr, dma_addr_t mapping)
294{
295 REG_WR(bp, addr, U64_LO(mapping));
296 REG_WR(bp, addr + 4, U64_HI(mapping));
297}
298
1191cb83
ED		 299static void storm_memset_spq_addr(struct bnx2x *bp,
300 dma_addr_t mapping, u16 abs_fid)
619c5cb6
VZ		 301{
302 u32 addr = XSEM_REG_FAST_MEMORY +
303 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
304
305 __storm_memset_dma_mapping(bp, addr, mapping);
306}
307
1191cb83
ED		 308static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
309 u16 pf_id)
523224a3 310{
619c5cb6
VZ		 311 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
312 pf_id);
313 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
314 pf_id);
315 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
316 pf_id);
317 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
318 pf_id);
523224a3
DK		 319}
320
1191cb83
ED		 321static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
322 u8 enable)
619c5cb6
VZ		 323{
324 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
325 enable);
326 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
327 enable);
328 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
329 enable);
330 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
331 enable);
332}
523224a3 333
1191cb83
ED		 334static void storm_memset_eq_data(struct bnx2x *bp,
335 struct event_ring_data *eq_data,
523224a3
DK		 336 u16 pfid)
337{
338 size_t size = sizeof(struct event_ring_data);
339
340 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
341
342 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
343}
344
1191cb83
ED		 345static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
346 u16 pfid)
523224a3
DK		 347{
348 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
349 REG_WR16(bp, addr, eq_prod);
350}
351
a2fbb9ea
ET		 352/* used only at init
353 * locking is done by mcp
354 */
8d96286a 355static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 356{
357 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
358 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
359 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
360 PCICFG_VENDOR_ID_OFFSET);
361}
362
a2fbb9ea
ET		 363static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
364{
365 u32 val;
366
367 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
368 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
369 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
370 PCICFG_VENDOR_ID_OFFSET);
371
372 return val;
373}
a2fbb9ea 374
f2e0899f
DK		 375#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
376#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
377#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
378#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
379#define DMAE_DP_DST_NONE "dst_addr [none]"
380
6bf07b8e
YM		 381static void bnx2x_dp_dmae(struct bnx2x *bp,
382 struct dmae_command *dmae, int msglvl)
fd1fc79d
AE		 383{
384 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
6bf07b8e 385 int i;
fd1fc79d
AE		 386
387 switch (dmae->opcode & DMAE_COMMAND_DST) {
388 case DMAE_CMD_DST_PCI:
389 if (src_type == DMAE_CMD_SRC_PCI)
390 DP(msglvl, "DMAE: opcode 0x%08x\n"
391 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
392 "comp_addr [%x:%08x], comp_val 0x%08x\n",
393 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
394 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
395 dmae->comp_addr_hi, dmae->comp_addr_lo,
396 dmae->comp_val);
397 else
398 DP(msglvl, "DMAE: opcode 0x%08x\n"
399 "src [%08x], len [%d*4], dst [%x:%08x]\n"
400 "comp_addr [%x:%08x], comp_val 0x%08x\n",
401 dmae->opcode, dmae->src_addr_lo >> 2,
402 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
403 dmae->comp_addr_hi, dmae->comp_addr_lo,
404 dmae->comp_val);
405 break;
406 case DMAE_CMD_DST_GRC:
407 if (src_type == DMAE_CMD_SRC_PCI)
408 DP(msglvl, "DMAE: opcode 0x%08x\n"
409 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
410 "comp_addr [%x:%08x], comp_val 0x%08x\n",
411 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
412 dmae->len, dmae->dst_addr_lo >> 2,
413 dmae->comp_addr_hi, dmae->comp_addr_lo,
414 dmae->comp_val);
415 else
416 DP(msglvl, "DMAE: opcode 0x%08x\n"
417 "src [%08x], len [%d*4], dst [%08x]\n"
418 "comp_addr [%x:%08x], comp_val 0x%08x\n",
419 dmae->opcode, dmae->src_addr_lo >> 2,
420 dmae->len, dmae->dst_addr_lo >> 2,
421 dmae->comp_addr_hi, dmae->comp_addr_lo,
422 dmae->comp_val);
423 break;
424 default:
425 if (src_type == DMAE_CMD_SRC_PCI)
426 DP(msglvl, "DMAE: opcode 0x%08x\n"
427 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
428 "comp_addr [%x:%08x] comp_val 0x%08x\n",
429 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
430 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
431 dmae->comp_val);
432 else
433 DP(msglvl, "DMAE: opcode 0x%08x\n"
434 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
435 "comp_addr [%x:%08x] comp_val 0x%08x\n",
436 dmae->opcode, dmae->src_addr_lo >> 2,
437 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
438 dmae->comp_val);
439 break;
440 }
6bf07b8e
YM		 441
442 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
443 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
444 i, *(((u32 *)dmae) + i));
fd1fc79d 445}
f2e0899f 446
a2fbb9ea 447/* copy command into DMAE command memory and set DMAE command go */
6c719d00 448void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 449{
450 u32 cmd_offset;
451 int i;
452
453 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
454 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
455 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 456 }
457 REG_WR(bp, dmae_reg_go_c[idx], 1);
458}
459
f2e0899f 460u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 461{
f2e0899f
DK		 462 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
463 DMAE_CMD_C_ENABLE);
464}
ad8d3948 465
f2e0899f
DK		 466u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
467{
468 return opcode & ~DMAE_CMD_SRC_RESET;
469}
ad8d3948 470
f2e0899f
DK		 471u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
472 bool with_comp, u8 comp_type)
473{
474 u32 opcode = 0;
475
476 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
477 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 478
f2e0899f
DK		 479 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
480
481 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 482 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
483 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 484 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 485
a2fbb9ea 486#ifdef __BIG_ENDIAN
f2e0899f 487 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 488#else
f2e0899f 489 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 490#endif
f2e0899f
DK		 491 if (with_comp)
492 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
493 return opcode;
494}
495
fd1fc79d 496void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
8d96286a 497 struct dmae_command *dmae,
498 u8 src_type, u8 dst_type)
f2e0899f
DK		 499{
500 memset(dmae, 0, sizeof(struct dmae_command));
501
502 /* set the opcode */
503 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
504 true, DMAE_COMP_PCI);
505
506 /* fill in the completion parameters */
507 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
508 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
509 dmae->comp_val = DMAE_COMP_VAL;
510}
511
fd1fc79d 512/* issue a dmae command over the init-channel and wait for completion */
32316a46
AE		 513int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
514 u32 *comp)
f2e0899f 515{
5e374b5a 516 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 517 int rc = 0;
518
6bf07b8e
YM		 519 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
520
521 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
619c5cb6
VZ		 522 * as long as this code is called both from syscall context and
523 * from ndo_set_rx_mode() flow that may be called from BH.
524 */
6e30dd4e 525 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 526
f2e0899f 527 /* reset completion */
32316a46 528 *comp = 0;
a2fbb9ea 529
f2e0899f
DK		 530 /* post the command on the channel used for initializations */
531 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 532
f2e0899f 533 /* wait for completion */
a2fbb9ea 534 udelay(5);
32316a46 535 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948 536
95c6c616
AE		 537 if (!cnt ||
538 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
539 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
c3eefaf6 540 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 541 rc = DMAE_TIMEOUT;
542 goto unlock;
a2fbb9ea 543 }
ad8d3948 544 cnt--;
f2e0899f 545 udelay(50);
a2fbb9ea 546 }
32316a46 547 if (*comp & DMAE_PCI_ERR_FLAG) {
f2e0899f
DK		 548 BNX2X_ERR("DMAE PCI error!\n");
549 rc = DMAE_PCI_ERROR;
550 }
551
f2e0899f 552unlock:
6e30dd4e 553 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 554 return rc;
555}
556
557void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
558 u32 len32)
559{
6bf07b8e 560 int rc;
f2e0899f
DK		 561 struct dmae_command dmae;
562
563 if (!bp->dmae_ready) {
564 u32 *data = bnx2x_sp(bp, wb_data[0]);
565
127a425e
AE		 566 if (CHIP_IS_E1(bp))
567 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
568 else
569 bnx2x_init_str_wr(bp, dst_addr, data, len32);
f2e0899f
DK		 570 return;
571 }
572
573 /* set opcode and fixed command fields */
574 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
575
576 /* fill in addresses and len */
577 dmae.src_addr_lo = U64_LO(dma_addr);
578 dmae.src_addr_hi = U64_HI(dma_addr);
579 dmae.dst_addr_lo = dst_addr >> 2;
580 dmae.dst_addr_hi = 0;
581 dmae.len = len32;
582
f2e0899f 583 /* issue the command and wait for completion */
32316a46 584 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 585 if (rc) {
586 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 587#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 588 bnx2x_panic();
9dcd9acd 589#endif
6bf07b8e 590 }
a2fbb9ea
ET		 591}
592
c18487ee 593void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 594{
6bf07b8e 595 int rc;
5ff7b6d4 596 struct dmae_command dmae;
ad8d3948
EG		 597
598 if (!bp->dmae_ready) {
599 u32 *data = bnx2x_sp(bp, wb_data[0]);
600 int i;
601
51c1a580 602 if (CHIP_IS_E1(bp))
127a425e
AE		 603 for (i = 0; i < len32; i++)
604 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
51c1a580 605 else
127a425e
AE		 606 for (i = 0; i < len32; i++)
607 data[i] = REG_RD(bp, src_addr + i*4);
608
ad8d3948
EG		 609 return;
610 }
611
f2e0899f
DK		 612 /* set opcode and fixed command fields */
613 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 614
f2e0899f 615 /* fill in addresses and len */
5ff7b6d4
EG		 616 dmae.src_addr_lo = src_addr >> 2;
617 dmae.src_addr_hi = 0;
618 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
619 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
620 dmae.len = len32;
ad8d3948 621
f2e0899f 622 /* issue the command and wait for completion */
32316a46 623 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 624 if (rc) {
625 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 626#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 627 bnx2x_panic();
9dcd9acd 628#endif
c957d09f 629 }
ad8d3948
EG		 630}
631
8d96286a 632static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
633 u32 addr, u32 len)
573f2035 634{
02e3c6cb 635 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 636 int offset = 0;
637
02e3c6cb 638 while (len > dmae_wr_max) {
573f2035 639 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 640 addr + offset, dmae_wr_max);
641 offset += dmae_wr_max * 4;
642 len -= dmae_wr_max;
573f2035
EG		 643 }
644
645 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
646}
647
a2fbb9ea
ET		 648static int bnx2x_mc_assert(struct bnx2x *bp)
649{
a2fbb9ea 650 char last_idx;
34f80b04
EG		 651 int i, rc = 0;
652 u32 row0, row1, row2, row3;
653
654 /* XSTORM */
655 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
656 XSTORM_ASSERT_LIST_INDEX_OFFSET);
657 if (last_idx)
658 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
659
660 /* print the asserts */
661 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
662
663 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
664 XSTORM_ASSERT_LIST_OFFSET(i));
665 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
666 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
667 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
668 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
669 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
670 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
671
672 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 673 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 674 i, row3, row2, row1, row0);
675 rc++;
676 } else {
677 break;
678 }
679 }
680
681 /* TSTORM */
682 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
683 TSTORM_ASSERT_LIST_INDEX_OFFSET);
684 if (last_idx)
685 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
686
687 /* print the asserts */
688 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
689
690 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
691 TSTORM_ASSERT_LIST_OFFSET(i));
692 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
693 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
694 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
695 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
696 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
697 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
698
699 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 700 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 701 i, row3, row2, row1, row0);
702 rc++;
703 } else {
704 break;
705 }
706 }
707
708 /* CSTORM */
709 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
710 CSTORM_ASSERT_LIST_INDEX_OFFSET);
711 if (last_idx)
712 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
713
714 /* print the asserts */
715 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
716
717 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
718 CSTORM_ASSERT_LIST_OFFSET(i));
719 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
720 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
721 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
722 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
723 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
724 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
725
726 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 727 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 728 i, row3, row2, row1, row0);
729 rc++;
730 } else {
731 break;
732 }
733 }
734
735 /* USTORM */
736 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
737 USTORM_ASSERT_LIST_INDEX_OFFSET);
738 if (last_idx)
739 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
740
741 /* print the asserts */
742 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
743
744 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
745 USTORM_ASSERT_LIST_OFFSET(i));
746 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
747 USTORM_ASSERT_LIST_OFFSET(i) + 4);
748 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
749 USTORM_ASSERT_LIST_OFFSET(i) + 8);
750 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
751 USTORM_ASSERT_LIST_OFFSET(i) + 12);
752
753 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 754 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 755 i, row3, row2, row1, row0);
756 rc++;
757 } else {
758 break;
a2fbb9ea
ET		 759 }
760 }
34f80b04 761
a2fbb9ea
ET		 762 return rc;
763}
c14423fe 764
1a6974b2
YM		 765#define MCPR_TRACE_BUFFER_SIZE (0x800)
766#define SCRATCH_BUFFER_SIZE(bp) \
767 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
768
7a25cc73 769void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 770{
7a25cc73 771 u32 addr, val;
a2fbb9ea 772 u32 mark, offset;
4781bfad 773 __be32 data[9];
a2fbb9ea 774 int word;
f2e0899f 775 u32 trace_shmem_base;
2145a920
VZ		 776 if (BP_NOMCP(bp)) {
777 BNX2X_ERR("NO MCP - can not dump\n");
778 return;
779 }
7a25cc73
DK		 780 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
781 (bp->common.bc_ver & 0xff0000) >> 16,
782 (bp->common.bc_ver & 0xff00) >> 8,
783 (bp->common.bc_ver & 0xff));
784
785 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
786 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
51c1a580 787 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 788
f2e0899f
DK		 789 if (BP_PATH(bp) == 0)
790 trace_shmem_base = bp->common.shmem_base;
791 else
792 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
1a6974b2
YM		 793
794 /* sanity */
795 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
796 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
797 SCRATCH_BUFFER_SIZE(bp)) {
798 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
799 trace_shmem_base);
800 return;
801 }
802
803 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
de128804
DK		 804
805 /* validate TRCB signature */
806 mark = REG_RD(bp, addr);
807 if (mark != MFW_TRACE_SIGNATURE) {
808 BNX2X_ERR("Trace buffer signature is missing.");
809 return ;
810 }
811
812 /* read cyclic buffer pointer */
813 addr += 4;
cdaa7cb8 814 mark = REG_RD(bp, addr);
1a6974b2
YM		 815 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
816 if (mark >= trace_shmem_base || mark < addr + 4) {
817 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
818 return;
819 }
7a25cc73 820 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 821
7a25cc73 822 printk("%s", lvl);
2de67439
YM		 823
824 /* dump buffer after the mark */
1a6974b2 825 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 826 for (word = 0; word < 8; word++)
cdaa7cb8 827 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 828 data[8] = 0x0;
7995c64e 829 pr_cont("%s", (char *)data);
a2fbb9ea 830 }
2de67439
YM		 831
832 /* dump buffer before the mark */
cdaa7cb8 833 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 834 for (word = 0; word < 8; word++)
cdaa7cb8 835 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 836 data[8] = 0x0;
7995c64e 837 pr_cont("%s", (char *)data);
a2fbb9ea 838 }
7a25cc73
DK		 839 printk("%s" "end of fw dump\n", lvl);
840}
841
1191cb83 842static void bnx2x_fw_dump(struct bnx2x *bp)
7a25cc73
DK		 843{
844 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 845}
846
823e1d90
YM		 847static void bnx2x_hc_int_disable(struct bnx2x *bp)
848{
849 int port = BP_PORT(bp);
850 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
851 u32 val = REG_RD(bp, addr);
852
853 /* in E1 we must use only PCI configuration space to disable
16a5fd92
YM		 854 * MSI/MSIX capability
855 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
823e1d90
YM		 856 */
857 if (CHIP_IS_E1(bp)) {
858 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
859 * Use mask register to prevent from HC sending interrupts
860 * after we exit the function
861 */
862 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
863
864 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
865 HC_CONFIG_0_REG_INT_LINE_EN_0 |
866 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
867 } else
868 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
869 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
870 HC_CONFIG_0_REG_INT_LINE_EN_0 |
871 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
872
873 DP(NETIF_MSG_IFDOWN,
874 "write %x to HC %d (addr 0x%x)\n",
875 val, port, addr);
876
877 /* flush all outstanding writes */
878 mmiowb();
879
880 REG_WR(bp, addr, val);
881 if (REG_RD(bp, addr) != val)
6bf07b8e 882 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 883}
884
885static void bnx2x_igu_int_disable(struct bnx2x *bp)
886{
887 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
888
889 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
890 IGU_PF_CONF_INT_LINE_EN |
891 IGU_PF_CONF_ATTN_BIT_EN);
892
893 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
894
895 /* flush all outstanding writes */
896 mmiowb();
897
898 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
899 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
6bf07b8e 900 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 901}
902
903static void bnx2x_int_disable(struct bnx2x *bp)
904{
905 if (bp->common.int_block == INT_BLOCK_HC)
906 bnx2x_hc_int_disable(bp);
907 else
908 bnx2x_igu_int_disable(bp);
909}
910
911void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
a2fbb9ea
ET		 912{
913 int i;
523224a3
DK		 914 u16 j;
915 struct hc_sp_status_block_data sp_sb_data;
916 int func = BP_FUNC(bp);
917#ifdef BNX2X_STOP_ON_ERROR
918 u16 start = 0, end = 0;
6383c0b3 919 u8 cos;
523224a3 920#endif
0155a27c 921 if (IS_PF(bp) && disable_int)
823e1d90 922 bnx2x_int_disable(bp);
a2fbb9ea 923
66e855f3 924 bp->stats_state = STATS_STATE_DISABLED;
7a752993 925 bp->eth_stats.unrecoverable_error++;
66e855f3
YG		 926 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
927
a2fbb9ea
ET		 928 BNX2X_ERR("begin crash dump -----------------\n");
929
8440d2b6
EG		 930 /* Indices */
931 /* Common */
0155a27c
YM		 932 if (IS_PF(bp)) {
933 struct host_sp_status_block *def_sb = bp->def_status_blk;
934 int data_size, cstorm_offset;
935
936 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
937 bp->def_idx, bp->def_att_idx, bp->attn_state,
938 bp->spq_prod_idx, bp->stats_counter);
939 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
940 def_sb->atten_status_block.attn_bits,
941 def_sb->atten_status_block.attn_bits_ack,
942 def_sb->atten_status_block.status_block_id,
943 def_sb->atten_status_block.attn_bits_index);
944 BNX2X_ERR(" def (");
945 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
946 pr_cont("0x%x%s",
947 def_sb->sp_sb.index_values[i],
948 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
949
950 data_size = sizeof(struct hc_sp_status_block_data) /
951 sizeof(u32);
952 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
953 for (i = 0; i < data_size; i++)
954 *((u32 *)&sp_sb_data + i) =
955 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
956 i * sizeof(u32));
957
958 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
959 sp_sb_data.igu_sb_id,
960 sp_sb_data.igu_seg_id,
961 sp_sb_data.p_func.pf_id,
962 sp_sb_data.p_func.vnic_id,
963 sp_sb_data.p_func.vf_id,
964 sp_sb_data.p_func.vf_valid,
965 sp_sb_data.state);
966 }
523224a3 967
ec6ba945 968 for_each_eth_queue(bp, i) {
a2fbb9ea 969 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 970 int loop;
f2e0899f 971 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 972 struct hc_status_block_data_e1x sb_data_e1x;
973 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 974 CHIP_IS_E1x(bp) ?
975 sb_data_e1x.common.state_machine :
976 sb_data_e2.common.state_machine;
523224a3 977 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 978 CHIP_IS_E1x(bp) ?
979 sb_data_e1x.index_data :
980 sb_data_e2.index_data;
6383c0b3 981 u8 data_size, cos;
523224a3 982 u32 *sb_data_p;
6383c0b3 983 struct bnx2x_fp_txdata txdata;
523224a3
DK		 984
985 /* Rx */
51c1a580 986 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 987 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 988 fp->rx_comp_prod,
66e855f3 989 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
51c1a580 990 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
8440d2b6 991 fp->rx_sge_prod, fp->last_max_sge,
523224a3 992 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 993
523224a3 994 /* Tx */
6383c0b3
AE		 995 for_each_cos_in_tx_queue(fp, cos)
996 {
65565884 997 txdata = *fp->txdata_ptr[cos];
51c1a580 998 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
6383c0b3
AE		 999 i, txdata.tx_pkt_prod,
1000 txdata.tx_pkt_cons, txdata.tx_bd_prod,
1001 txdata.tx_bd_cons,
1002 le16_to_cpu(*txdata.tx_cons_sb));
1003 }
523224a3 1004
619c5cb6
VZ		 1005 loop = CHIP_IS_E1x(bp) ?
1006 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 1007
1008 /* host sb data */
1009
ec6ba945
VZ		 1010 if (IS_FCOE_FP(fp))
1011 continue;
55c11941 1012
523224a3
DK		 1013 BNX2X_ERR(" run indexes (");
1014 for (j = 0; j < HC_SB_MAX_SM; j++)
1015 pr_cont("0x%x%s",
1016 fp->sb_running_index[j],
1017 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1018
1019 BNX2X_ERR(" indexes (");
1020 for (j = 0; j < loop; j++)
1021 pr_cont("0x%x%s",
1022 fp->sb_index_values[j],
1023 (j == loop - 1) ? ")" : " ");
0155a27c
YM		 1024
1025 /* VF cannot access FW refelection for status block */
1026 if (IS_VF(bp))
1027 continue;
1028
523224a3 1029 /* fw sb data */
619c5cb6
VZ		 1030 data_size = CHIP_IS_E1x(bp) ?
1031 sizeof(struct hc_status_block_data_e1x) :
1032 sizeof(struct hc_status_block_data_e2);
523224a3 1033 data_size /= sizeof(u32);
619c5cb6
VZ		 1034 sb_data_p = CHIP_IS_E1x(bp) ?
1035 (u32 *)&sb_data_e1x :
1036 (u32 *)&sb_data_e2;
523224a3
DK		 1037 /* copy sb data in here */
1038 for (j = 0; j < data_size; j++)
1039 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1040 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1041 j * sizeof(u32));
1042
619c5cb6 1043 if (!CHIP_IS_E1x(bp)) {
51c1a580 1044 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1045 sb_data_e2.common.p_func.pf_id,
1046 sb_data_e2.common.p_func.vf_id,
1047 sb_data_e2.common.p_func.vf_valid,
1048 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 1049 sb_data_e2.common.same_igu_sb_1b,
1050 sb_data_e2.common.state);
f2e0899f 1051 } else {
51c1a580 1052 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1053 sb_data_e1x.common.p_func.pf_id,
1054 sb_data_e1x.common.p_func.vf_id,
1055 sb_data_e1x.common.p_func.vf_valid,
1056 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 1057 sb_data_e1x.common.same_igu_sb_1b,
1058 sb_data_e1x.common.state);
f2e0899f 1059 }
523224a3
DK		 1060
1061 /* SB_SMs data */
1062 for (j = 0; j < HC_SB_MAX_SM; j++) {
51c1a580
MS		 1063 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1064 j, hc_sm_p[j].__flags,
1065 hc_sm_p[j].igu_sb_id,
1066 hc_sm_p[j].igu_seg_id,
1067 hc_sm_p[j].time_to_expire,
1068 hc_sm_p[j].timer_value);
523224a3
DK		 1069 }
1070
16a5fd92 1071 /* Indices data */
523224a3 1072 for (j = 0; j < loop; j++) {
51c1a580 1073 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
523224a3
DK		 1074 hc_index_p[j].flags,
1075 hc_index_p[j].timeout);
1076 }
8440d2b6 1077 }
a2fbb9ea 1078
523224a3 1079#ifdef BNX2X_STOP_ON_ERROR
0155a27c
YM		 1080 if (IS_PF(bp)) {
1081 /* event queue */
1082 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1083 for (i = 0; i < NUM_EQ_DESC; i++) {
1084 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1085
1086 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1087 i, bp->eq_ring[i].message.opcode,
1088 bp->eq_ring[i].message.error);
1089 BNX2X_ERR("data: %x %x %x\n",
1090 data[0], data[1], data[2]);
1091 }
04c46736
YM		 1092 }
1093
8440d2b6
EG		 1094 /* Rings */
1095 /* Rx */
55c11941 1096 for_each_valid_rx_queue(bp, i) {
8440d2b6 1097 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 1098
1099 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1100 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 1101 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 1102 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1103 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1104
c3eefaf6 1105 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
44151acb 1106 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
a2fbb9ea
ET		 1107 }
1108
3196a88a
EG		 1109 start = RX_SGE(fp->rx_sge_prod);
1110 end = RX_SGE(fp->last_max_sge);
8440d2b6 1111 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 1112 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1113 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1114
c3eefaf6
EG		 1115 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1116 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 1117 }
1118
a2fbb9ea
ET		 1119 start = RCQ_BD(fp->rx_comp_cons - 10);
1120 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 1121 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 1122 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1123
c3eefaf6
EG		 1124 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1125 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 1126 }
1127 }
1128
8440d2b6 1129 /* Tx */
55c11941 1130 for_each_valid_tx_queue(bp, i) {
8440d2b6 1131 struct bnx2x_fastpath *fp = &bp->fp[i];
6383c0b3 1132 for_each_cos_in_tx_queue(fp, cos) {
65565884 1133 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
6383c0b3
AE		 1134
1135 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1136 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1137 for (j = start; j != end; j = TX_BD(j + 1)) {
1138 struct sw_tx_bd *sw_bd =
1139 &txdata->tx_buf_ring[j];
1140
51c1a580 1141 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
6383c0b3
AE		 1142 i, cos, j, sw_bd->skb,
1143 sw_bd->first_bd);
1144 }
8440d2b6 1145
6383c0b3
AE		 1146 start = TX_BD(txdata->tx_bd_cons - 10);
1147 end = TX_BD(txdata->tx_bd_cons + 254);
1148 for (j = start; j != end; j = TX_BD(j + 1)) {
1149 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 1150
51c1a580 1151 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
6383c0b3
AE		 1152 i, cos, j, tx_bd[0], tx_bd[1],
1153 tx_bd[2], tx_bd[3]);
1154 }
8440d2b6
EG		 1155 }
1156 }
523224a3 1157#endif
0155a27c
YM		 1158 if (IS_PF(bp)) {
1159 bnx2x_fw_dump(bp);
1160 bnx2x_mc_assert(bp);
1161 }
a2fbb9ea 1162 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1163}
1164
619c5cb6
VZ		 1165/*
1166 * FLR Support for E2
1167 *
1168 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1169 * initialization.
1170 */
16a5fd92 1171#define FLR_WAIT_USEC 10000 /* 10 milliseconds */
89db4ad8
AE		 1172#define FLR_WAIT_INTERVAL 50 /* usec */
1173#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
619c5cb6
VZ		 1174
1175struct pbf_pN_buf_regs {
1176 int pN;
1177 u32 init_crd;
1178 u32 crd;
1179 u32 crd_freed;
1180};
1181
1182struct pbf_pN_cmd_regs {
1183 int pN;
1184 u32 lines_occup;
1185 u32 lines_freed;
1186};
1187
1188static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1189 struct pbf_pN_buf_regs *regs,
1190 u32 poll_count)
1191{
1192 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1193 u32 cur_cnt = poll_count;
1194
1195 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1196 crd = crd_start = REG_RD(bp, regs->crd);
1197 init_crd = REG_RD(bp, regs->init_crd);
1198
1199 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1200 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1201 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1202
1203 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1204 (init_crd - crd_start))) {
1205 if (cur_cnt--) {
89db4ad8 1206 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1207 crd = REG_RD(bp, regs->crd);
1208 crd_freed = REG_RD(bp, regs->crd_freed);
1209 } else {
1210 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1211 regs->pN);
1212 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1213 regs->pN, crd);
1214 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1215 regs->pN, crd_freed);
1216 break;
1217 }
1218 }
1219 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
89db4ad8 1220 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1221}
1222
1223static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1224 struct pbf_pN_cmd_regs *regs,
1225 u32 poll_count)
1226{
1227 u32 occup, to_free, freed, freed_start;
1228 u32 cur_cnt = poll_count;
1229
1230 occup = to_free = REG_RD(bp, regs->lines_occup);
1231 freed = freed_start = REG_RD(bp, regs->lines_freed);
1232
1233 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1234 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1235
1236 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1237 if (cur_cnt--) {
89db4ad8 1238 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1239 occup = REG_RD(bp, regs->lines_occup);
1240 freed = REG_RD(bp, regs->lines_freed);
1241 } else {
1242 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1243 regs->pN);
1244 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1245 regs->pN, occup);
1246 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1247 regs->pN, freed);
1248 break;
1249 }
1250 }
1251 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
89db4ad8 1252 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1253}
1254
1191cb83
ED		 1255static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1256 u32 expected, u32 poll_count)
619c5cb6
VZ		 1257{
1258 u32 cur_cnt = poll_count;
1259 u32 val;
1260
1261 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
89db4ad8 1262 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1263
1264 return val;
1265}
1266
d16132ce
AE		 1267int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1268 char *msg, u32 poll_cnt)
619c5cb6
VZ		 1269{
1270 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1271 if (val != 0) {
1272 BNX2X_ERR("%s usage count=%d\n", msg, val);
1273 return 1;
1274 }
1275 return 0;
1276}
1277
d16132ce
AE		 1278/* Common routines with VF FLR cleanup */
1279u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
619c5cb6
VZ		 1280{
1281 /* adjust polling timeout */
1282 if (CHIP_REV_IS_EMUL(bp))
1283 return FLR_POLL_CNT * 2000;
1284
1285 if (CHIP_REV_IS_FPGA(bp))
1286 return FLR_POLL_CNT * 120;
1287
1288 return FLR_POLL_CNT;
1289}
1290
d16132ce 1291void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
619c5cb6
VZ		 1292{
1293 struct pbf_pN_cmd_regs cmd_regs[] = {
1294 {0, (CHIP_IS_E3B0(bp)) ?
1295 PBF_REG_TQ_OCCUPANCY_Q0 :
1296 PBF_REG_P0_TQ_OCCUPANCY,
1297 (CHIP_IS_E3B0(bp)) ?
1298 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1299 PBF_REG_P0_TQ_LINES_FREED_CNT},
1300 {1, (CHIP_IS_E3B0(bp)) ?
1301 PBF_REG_TQ_OCCUPANCY_Q1 :
1302 PBF_REG_P1_TQ_OCCUPANCY,
1303 (CHIP_IS_E3B0(bp)) ?
1304 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1305 PBF_REG_P1_TQ_LINES_FREED_CNT},
1306 {4, (CHIP_IS_E3B0(bp)) ?
1307 PBF_REG_TQ_OCCUPANCY_LB_Q :
1308 PBF_REG_P4_TQ_OCCUPANCY,
1309 (CHIP_IS_E3B0(bp)) ?
1310 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1311 PBF_REG_P4_TQ_LINES_FREED_CNT}
1312 };
1313
1314 struct pbf_pN_buf_regs buf_regs[] = {
1315 {0, (CHIP_IS_E3B0(bp)) ?
1316 PBF_REG_INIT_CRD_Q0 :
1317 PBF_REG_P0_INIT_CRD ,
1318 (CHIP_IS_E3B0(bp)) ?
1319 PBF_REG_CREDIT_Q0 :
1320 PBF_REG_P0_CREDIT,
1321 (CHIP_IS_E3B0(bp)) ?
1322 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1323 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1324 {1, (CHIP_IS_E3B0(bp)) ?
1325 PBF_REG_INIT_CRD_Q1 :
1326 PBF_REG_P1_INIT_CRD,
1327 (CHIP_IS_E3B0(bp)) ?
1328 PBF_REG_CREDIT_Q1 :
1329 PBF_REG_P1_CREDIT,
1330 (CHIP_IS_E3B0(bp)) ?
1331 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1332 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1333 {4, (CHIP_IS_E3B0(bp)) ?
1334 PBF_REG_INIT_CRD_LB_Q :
1335 PBF_REG_P4_INIT_CRD,
1336 (CHIP_IS_E3B0(bp)) ?
1337 PBF_REG_CREDIT_LB_Q :
1338 PBF_REG_P4_CREDIT,
1339 (CHIP_IS_E3B0(bp)) ?
1340 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1341 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1342 };
1343
1344 int i;
1345
1346 /* Verify the command queues are flushed P0, P1, P4 */
1347 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1348 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1349
619c5cb6
VZ		 1350 /* Verify the transmission buffers are flushed P0, P1, P4 */
1351 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1352 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1353}
1354
1355#define OP_GEN_PARAM(param) \
1356 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1357
1358#define OP_GEN_TYPE(type) \
1359 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1360
1361#define OP_GEN_AGG_VECT(index) \
1362 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1363
d16132ce 1364int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
619c5cb6 1365{
86564c3f 1366 u32 op_gen_command = 0;
619c5cb6
VZ		 1367 u32 comp_addr = BAR_CSTRORM_INTMEM +
1368 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1369 int ret = 0;
1370
1371 if (REG_RD(bp, comp_addr)) {
89db4ad8 1372 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
619c5cb6
VZ		 1373 return 1;
1374 }
1375
86564c3f
YM		 1376 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1377 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1378 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1379 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
619c5cb6 1380
89db4ad8 1381 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
86564c3f 1382 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
619c5cb6
VZ		 1383
1384 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1385 BNX2X_ERR("FW final cleanup did not succeed\n");
51c1a580
MS		 1386 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1387 (REG_RD(bp, comp_addr)));
d16132ce
AE		 1388 bnx2x_panic();
1389 return 1;
619c5cb6 1390 }
16a5fd92 1391 /* Zero completion for next FLR */
619c5cb6
VZ		 1392 REG_WR(bp, comp_addr, 0);
1393
1394 return ret;
1395}
1396
b56e9670 1397u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
619c5cb6 1398{
619c5cb6
VZ		 1399 u16 status;
1400
2a80eebc 1401 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
619c5cb6
VZ		 1402 return status & PCI_EXP_DEVSTA_TRPND;
1403}
1404
1405/* PF FLR specific routines
1406*/
1407static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1408{
619c5cb6
VZ		 1409 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1410 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1411 CFC_REG_NUM_LCIDS_INSIDE_PF,
1412 "CFC PF usage counter timed out",
1413 poll_cnt))
1414 return 1;
1415
619c5cb6
VZ		 1416 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1417 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1418 DORQ_REG_PF_USAGE_CNT,
1419 "DQ PF usage counter timed out",
1420 poll_cnt))
1421 return 1;
1422
1423 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1424 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1425 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1426 "QM PF usage counter timed out",
1427 poll_cnt))
1428 return 1;
1429
1430 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1431 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1432 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1433 "Timers VNIC usage counter timed out",
1434 poll_cnt))
1435 return 1;
1436 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1437 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1438 "Timers NUM_SCANS usage counter timed out",
1439 poll_cnt))
1440 return 1;
1441
1442 /* Wait DMAE PF usage counter to zero */
1443 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1444 dmae_reg_go_c[INIT_DMAE_C(bp)],
6bf07b8e 1445 "DMAE command register timed out",
619c5cb6
VZ		 1446 poll_cnt))
1447 return 1;
1448
1449 return 0;
1450}
1451
1452static void bnx2x_hw_enable_status(struct bnx2x *bp)
1453{
1454 u32 val;
1455
1456 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1457 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1458
1459 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1460 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1461
1462 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1463 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1464
1465 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1466 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1467
1468 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1469 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1470
1471 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1472 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1473
1474 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1475 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1476
1477 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1478 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1479 val);
1480}
1481
1482static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1483{
1484 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1485
1486 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1487
1488 /* Re-enable PF target read access */
1489 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1490
1491 /* Poll HW usage counters */
89db4ad8 1492 DP(BNX2X_MSG_SP, "Polling usage counters\n");
619c5cb6
VZ		 1493 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1494 return -EBUSY;
1495
1496 /* Zero the igu 'trailing edge' and 'leading edge' */
1497
1498 /* Send the FW cleanup command */
1499 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1500 return -EBUSY;
1501
1502 /* ATC cleanup */
1503
1504 /* Verify TX hw is flushed */
1505 bnx2x_tx_hw_flushed(bp, poll_cnt);
1506
1507 /* Wait 100ms (not adjusted according to platform) */
1508 msleep(100);
1509
1510 /* Verify no pending pci transactions */
1511 if (bnx2x_is_pcie_pending(bp->pdev))
1512 BNX2X_ERR("PCIE Transactions still pending\n");
1513
1514 /* Debug */
1515 bnx2x_hw_enable_status(bp);
1516
1517 /*
1518 * Master enable - Due to WB DMAE writes performed before this
1519 * register is re-initialized as part of the regular function init
1520 */
1521 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1522
1523 return 0;
1524}
1525
f2e0899f 1526static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1527{
34f80b04 1528 int port = BP_PORT(bp);
a2fbb9ea
ET		 1529 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1530 u32 val = REG_RD(bp, addr);
69c326b3
DK		 1531 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1532 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1533 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
a2fbb9ea
ET		 1534
1535 if (msix) {
8badd27a
EG		 1536 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1537 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1538 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1539 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
69c326b3
DK		 1540 if (single_msix)
1541 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
8badd27a
EG		 1542 } else if (msi) {
1543 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1544 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1545 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1546 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1547 } else {
1548 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1549 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1550 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1551 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1552
a0fd065c 1553 if (!CHIP_IS_E1(bp)) {
51c1a580
MS		 1554 DP(NETIF_MSG_IFUP,
1555 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
615f8fd9 1556
a0fd065c 1557 REG_WR(bp, addr, val);
615f8fd9 1558
a0fd065c
DK		 1559 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1560 }
a2fbb9ea
ET		 1561 }
1562
a0fd065c
DK		 1563 if (CHIP_IS_E1(bp))
1564 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1565
51c1a580
MS		 1566 DP(NETIF_MSG_IFUP,
1567 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1568 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1569
1570 REG_WR(bp, addr, val);
37dbbf32
EG		 1571 /*
1572 * Ensure that HC_CONFIG is written before leading/trailing edge config
1573 */
1574 mmiowb();
1575 barrier();
34f80b04 1576
f2e0899f 1577 if (!CHIP_IS_E1(bp)) {
34f80b04 1578 /* init leading/trailing edge */
fb3bff17 1579 if (IS_MF(bp)) {
3395a033 1580 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1581 if (bp->port.pmf)
4acac6a5
EG		 1582 /* enable nig and gpio3 attention */
1583 val |= 0x1100;
34f80b04
EG		 1584 } else
1585 val = 0xffff;
1586
1587 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1588 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1589 }
37dbbf32
EG		 1590
1591 /* Make sure that interrupts are indeed enabled from here on */
1592 mmiowb();
a2fbb9ea
ET		 1593}
1594
f2e0899f
DK		 1595static void bnx2x_igu_int_enable(struct bnx2x *bp)
1596{
1597 u32 val;
30a5de77
DK		 1598 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1599 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1600 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
f2e0899f
DK		 1601
1602 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1603
1604 if (msix) {
1605 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1606 IGU_PF_CONF_SINGLE_ISR_EN);
ebe61d80 1607 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f 1608 IGU_PF_CONF_ATTN_BIT_EN);
30a5de77
DK		 1609
1610 if (single_msix)
1611 val |= IGU_PF_CONF_SINGLE_ISR_EN;
f2e0899f
DK		 1612 } else if (msi) {
1613 val &= ~IGU_PF_CONF_INT_LINE_EN;
ebe61d80 1614 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f
DK		 1615 IGU_PF_CONF_ATTN_BIT_EN |
1616 IGU_PF_CONF_SINGLE_ISR_EN);
1617 } else {
1618 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
ebe61d80 1619 val |= (IGU_PF_CONF_INT_LINE_EN |
f2e0899f
DK		 1620 IGU_PF_CONF_ATTN_BIT_EN |
1621 IGU_PF_CONF_SINGLE_ISR_EN);
1622 }
1623
ebe61d80
YM		 1624 /* Clean previous status - need to configure igu prior to ack*/
1625 if ((!msix) || single_msix) {
1626 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1627 bnx2x_ack_int(bp);
1628 }
1629
1630 val |= IGU_PF_CONF_FUNC_EN;
1631
51c1a580 1632 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
f2e0899f
DK		 1633 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1634
1635 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1636
79a8557a
YM		 1637 if (val & IGU_PF_CONF_INT_LINE_EN)
1638 pci_intx(bp->pdev, true);
1639
f2e0899f
DK		 1640 barrier();
1641
1642 /* init leading/trailing edge */
1643 if (IS_MF(bp)) {
3395a033 1644 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1645 if (bp->port.pmf)
1646 /* enable nig and gpio3 attention */
1647 val |= 0x1100;
1648 } else
1649 val = 0xffff;
1650
1651 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1652 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1653
1654 /* Make sure that interrupts are indeed enabled from here on */
1655 mmiowb();
1656}
1657
1658void bnx2x_int_enable(struct bnx2x *bp)
1659{
1660 if (bp->common.int_block == INT_BLOCK_HC)
1661 bnx2x_hc_int_enable(bp);
1662 else
1663 bnx2x_igu_int_enable(bp);
1664}
1665
9f6c9258 1666void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1667{
a2fbb9ea 1668 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1669 int i, offset;
a2fbb9ea 1670
f8ef6e44
YG		 1671 if (disable_hw)
1672 /* prevent the HW from sending interrupts */
1673 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1674
1675 /* make sure all ISRs are done */
1676 if (msix) {
8badd27a
EG		 1677 synchronize_irq(bp->msix_table[0].vector);
1678 offset = 1;
55c11941
MS		 1679 if (CNIC_SUPPORT(bp))
1680 offset++;
ec6ba945 1681 for_each_eth_queue(bp, i)
754a2f52 1682 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1683 } else
1684 synchronize_irq(bp->pdev->irq);
1685
1686 /* make sure sp_task is not running */
1cf167f2 1687 cancel_delayed_work(&bp->sp_task);
3deb8167 1688 cancel_delayed_work(&bp->period_task);
1cf167f2 1689 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1690}
1691
34f80b04 1692/* fast path */
a2fbb9ea
ET		 1693
1694/*
34f80b04 1695 * General service functions
a2fbb9ea
ET		 1696 */
1697
72fd0718
VZ		 1698/* Return true if succeeded to acquire the lock */
1699static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1700{
1701 u32 lock_status;
1702 u32 resource_bit = (1 << resource);
1703 int func = BP_FUNC(bp);
1704 u32 hw_lock_control_reg;
1705
51c1a580
MS		 1706 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1707 "Trying to take a lock on resource %d\n", resource);
72fd0718
VZ		 1708
1709 /* Validating that the resource is within range */
1710 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1711 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
72fd0718
VZ		 1712 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1713 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1714 return false;
72fd0718
VZ		 1715 }
1716
1717 if (func <= 5)
1718 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1719 else
1720 hw_lock_control_reg =
1721 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1722
1723 /* Try to acquire the lock */
1724 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1725 lock_status = REG_RD(bp, hw_lock_control_reg);
1726 if (lock_status & resource_bit)
1727 return true;
1728
51c1a580
MS		 1729 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1730 "Failed to get a lock on resource %d\n", resource);
72fd0718
VZ		 1731 return false;
1732}
1733
c9ee9206
VZ		 1734/**
1735 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1736 *
1737 * @bp: driver handle
1738 *
1739 * Returns the recovery leader resource id according to the engine this function
1740 * belongs to. Currently only only 2 engines is supported.
1741 */
1191cb83 1742static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
c9ee9206
VZ		 1743{
1744 if (BP_PATH(bp))
1745 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1746 else
1747 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1748}
1749
1750/**
2de67439 1751 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
c9ee9206
VZ		 1752 *
1753 * @bp: driver handle
1754 *
2de67439 1755 * Tries to acquire a leader lock for current engine.
c9ee9206 1756 */
1191cb83 1757static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
c9ee9206
VZ		 1758{
1759 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1760}
1761
619c5cb6 1762static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
55c11941 1763
fd1fc79d
AE		 1764/* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1765static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1766{
1767 /* Set the interrupt occurred bit for the sp-task to recognize it
1768 * must ack the interrupt and transition according to the IGU
1769 * state machine.
1770 */
1771 atomic_set(&bp->interrupt_occurred, 1);
1772
1773 /* The sp_task must execute only after this bit
1774 * is set, otherwise we will get out of sync and miss all
1775 * further interrupts. Hence, the barrier.
1776 */
1777 smp_wmb();
1778
1779 /* schedule sp_task to workqueue */
1780 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1781}
3196a88a 1782
619c5cb6 1783void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1784{
1785 struct bnx2x *bp = fp->bp;
1786 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1787 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6 1788 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
15192a8c 1789 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a2fbb9ea 1790
34f80b04 1791 DP(BNX2X_MSG_SP,
a2fbb9ea 1792 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1793 fp->index, cid, command, bp->state,
34f80b04 1794 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1795
fd1fc79d
AE		 1796 /* If cid is within VF range, replace the slowpath object with the
1797 * one corresponding to this VF
1798 */
1799 if (cid >= BNX2X_FIRST_VF_CID &&
1800 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1801 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1802
619c5cb6
VZ		 1803 switch (command) {
1804 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1805 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1806 drv_cmd = BNX2X_Q_CMD_UPDATE;
1807 break;
d6cae238 1808
619c5cb6 1809 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1810 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1811 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1812 break;
1813
6383c0b3 1814 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
51c1a580 1815 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
6383c0b3
AE		 1816 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1817 break;
1818
619c5cb6 1819 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1820 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1821 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1822 break;
1823
619c5cb6 1824 case (RAMROD_CMD_ID_ETH_TERMINATE):
6bf07b8e 1825 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
619c5cb6 1826 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1827 break;
1828
619c5cb6 1829 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1830 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1831 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1832 break;
619c5cb6 1833
14a94ebd
MK		 1834 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1835 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1836 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1837 break;
1838
619c5cb6
VZ		 1839 default:
1840 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1841 command, fp->index);
1842 return;
523224a3 1843 }
3196a88a 1844
619c5cb6
VZ		 1845 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1846 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1847 /* q_obj->complete_cmd() failure means that this was
1848 * an unexpected completion.
1849 *
1850 * In this case we don't want to increase the bp->spq_left
1851 * because apparently we haven't sent this command the first
1852 * place.
1853 */
1854#ifdef BNX2X_STOP_ON_ERROR
1855 bnx2x_panic();
1856#else
1857 return;
1858#endif
fd1fc79d
AE		 1859 /* SRIOV: reschedule any 'in_progress' operations */
1860 bnx2x_iov_sp_event(bp, cid, true);
619c5cb6 1861
8fe23fbd 1862 smp_mb__before_atomic_inc();
6e30dd4e 1863 atomic_inc(&bp->cq_spq_left);
619c5cb6
VZ		 1864 /* push the change in bp->spq_left and towards the memory */
1865 smp_mb__after_atomic_inc();
49d66772 1866
d6cae238
VZ		 1867 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1868
a3348722
BW		 1869 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1870 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1871 /* if Q update ramrod is completed for last Q in AFEX vif set
1872 * flow, then ACK MCP at the end
1873 *
1874 * mark pending ACK to MCP bit.
1875 * prevent case that both bits are cleared.
1876 * At the end of load/unload driver checks that
2de67439 1877 * sp_state is cleared, and this order prevents
a3348722
BW		 1878 * races
1879 */
1880 smp_mb__before_clear_bit();
1881 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1882 wmb();
1883 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1884 smp_mb__after_clear_bit();
1885
fd1fc79d
AE		 1886 /* schedule the sp task as mcp ack is required */
1887 bnx2x_schedule_sp_task(bp);
a3348722
BW		 1888 }
1889
523224a3 1890 return;
a2fbb9ea
ET		 1891}
1892
9f6c9258 1893irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1894{
555f6c78 1895 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1896 u16 status = bnx2x_ack_int(bp);
34f80b04 1897 u16 mask;
ca00392c 1898 int i;
6383c0b3 1899 u8 cos;
a2fbb9ea 1900
34f80b04 1901 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1902 if (unlikely(status == 0)) {
1903 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1904 return IRQ_NONE;
1905 }
f5372251 1906 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1907
3196a88a
EG		 1908#ifdef BNX2X_STOP_ON_ERROR
1909 if (unlikely(bp->panic))
1910 return IRQ_HANDLED;
1911#endif
1912
ec6ba945 1913 for_each_eth_queue(bp, i) {
ca00392c 1914 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1915
55c11941 1916 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
ca00392c 1917 if (status & mask) {
619c5cb6 1918 /* Handle Rx or Tx according to SB id */
6383c0b3 1919 for_each_cos_in_tx_queue(fp, cos)
65565884 1920 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
523224a3 1921 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1922 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1923 status &= ~mask;
1924 }
a2fbb9ea
ET		 1925 }
1926
55c11941
MS		 1927 if (CNIC_SUPPORT(bp)) {
1928 mask = 0x2;
1929 if (status & (mask | 0x1)) {
1930 struct cnic_ops *c_ops = NULL;
993ac7b5 1931
ad9b4359
MC		 1932 rcu_read_lock();
1933 c_ops = rcu_dereference(bp->cnic_ops);
1934 if (c_ops && (bp->cnic_eth_dev.drv_state &
1935 CNIC_DRV_STATE_HANDLES_IRQ))
1936 c_ops->cnic_handler(bp->cnic_data, NULL);
1937 rcu_read_unlock();
993ac7b5 1938
55c11941
MS		 1939 status &= ~mask;
1940 }
993ac7b5 1941 }
a2fbb9ea 1942
34f80b04 1943 if (unlikely(status & 0x1)) {
fd1fc79d
AE		 1944
1945 /* schedule sp task to perform default status block work, ack
1946 * attentions and enable interrupts.
1947 */
1948 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 1949
1950 status &= ~0x1;
1951 if (!status)
1952 return IRQ_HANDLED;
1953 }
1954
cdaa7cb8
VZ		 1955 if (unlikely(status))
1956 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1957 status);
a2fbb9ea 1958
c18487ee 1959 return IRQ_HANDLED;
a2fbb9ea
ET		 1960}
1961
c18487ee
YR		 1962/* Link */
1963
1964/*
1965 * General service functions
1966 */
a2fbb9ea 1967
9f6c9258 1968int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1969{
1970 u32 lock_status;
1971 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1972 int func = BP_FUNC(bp);
1973 u32 hw_lock_control_reg;
c18487ee 1974 int cnt;
a2fbb9ea 1975
c18487ee
YR		 1976 /* Validating that the resource is within range */
1977 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1978 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 1979 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1980 return -EINVAL;
1981 }
a2fbb9ea 1982
4a37fb66
YG		 1983 if (func <= 5) {
1984 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1985 } else {
1986 hw_lock_control_reg =
1987 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1988 }
1989
c18487ee 1990 /* Validating that the resource is not already taken */
4a37fb66 1991 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 1992 if (lock_status & resource_bit) {
51c1a580 1993 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
c18487ee
YR		 1994 lock_status, resource_bit);
1995 return -EEXIST;
1996 }
a2fbb9ea 1997
46230476
EG		 1998 /* Try for 5 second every 5ms */
1999 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 2000 /* Try to acquire the lock */
4a37fb66
YG		 2001 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2002 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 2003 if (lock_status & resource_bit)
2004 return 0;
a2fbb9ea 2005
639d65b8 2006 usleep_range(5000, 10000);
a2fbb9ea 2007 }
51c1a580 2008 BNX2X_ERR("Timeout\n");
c18487ee
YR		 2009 return -EAGAIN;
2010}
a2fbb9ea 2011
c9ee9206
VZ		 2012int bnx2x_release_leader_lock(struct bnx2x *bp)
2013{
2014 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2015}
2016
9f6c9258 2017int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 2018{
2019 u32 lock_status;
2020 u32 resource_bit = (1 << resource);
4a37fb66
YG		 2021 int func = BP_FUNC(bp);
2022 u32 hw_lock_control_reg;
a2fbb9ea 2023
c18487ee
YR		 2024 /* Validating that the resource is within range */
2025 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 2026 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 2027 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2028 return -EINVAL;
2029 }
2030
4a37fb66
YG		 2031 if (func <= 5) {
2032 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2033 } else {
2034 hw_lock_control_reg =
2035 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2036 }
2037
c18487ee 2038 /* Validating that the resource is currently taken */
4a37fb66 2039 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2040 if (!(lock_status & resource_bit)) {
6bf07b8e
YM		 2041 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2042 lock_status, resource_bit);
c18487ee 2043 return -EFAULT;
a2fbb9ea
ET		 2044 }
2045
9f6c9258
DK		 2046 REG_WR(bp, hw_lock_control_reg, resource_bit);
2047 return 0;
c18487ee 2048}
a2fbb9ea 2049
4acac6a5
EG		 2050int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2051{
2052 /* The GPIO should be swapped if swap register is set and active */
2053 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2054 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2055 int gpio_shift = gpio_num +
2056 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2057 u32 gpio_mask = (1 << gpio_shift);
2058 u32 gpio_reg;
2059 int value;
2060
2061 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2062 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2063 return -EINVAL;
2064 }
2065
2066 /* read GPIO value */
2067 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2068
2069 /* get the requested pin value */
2070 if ((gpio_reg & gpio_mask) == gpio_mask)
2071 value = 1;
2072 else
2073 value = 0;
2074
2075 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
2076
2077 return value;
2078}
2079
17de50b7 2080int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 2081{
2082 /* The GPIO should be swapped if swap register is set and active */
2083 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 2084 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 2085 int gpio_shift = gpio_num +
2086 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2087 u32 gpio_mask = (1 << gpio_shift);
2088 u32 gpio_reg;
a2fbb9ea 2089
c18487ee
YR		 2090 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2091 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2092 return -EINVAL;
2093 }
a2fbb9ea 2094
4a37fb66 2095 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 2096 /* read GPIO and mask except the float bits */
2097 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 2098
c18487ee
YR		 2099 switch (mode) {
2100 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
51c1a580
MS		 2101 DP(NETIF_MSG_LINK,
2102 "Set GPIO %d (shift %d) -> output low\n",
c18487ee
YR		 2103 gpio_num, gpio_shift);
2104 /* clear FLOAT and set CLR */
2105 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2106 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2107 break;
a2fbb9ea 2108
c18487ee 2109 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
51c1a580
MS		 2110 DP(NETIF_MSG_LINK,
2111 "Set GPIO %d (shift %d) -> output high\n",
c18487ee
YR		 2112 gpio_num, gpio_shift);
2113 /* clear FLOAT and set SET */
2114 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2115 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2116 break;
a2fbb9ea 2117
17de50b7 2118 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
51c1a580
MS		 2119 DP(NETIF_MSG_LINK,
2120 "Set GPIO %d (shift %d) -> input\n",
c18487ee
YR		 2121 gpio_num, gpio_shift);
2122 /* set FLOAT */
2123 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2124 break;
a2fbb9ea 2125
c18487ee
YR		 2126 default:
2127 break;
a2fbb9ea
ET		 2128 }
2129
c18487ee 2130 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 2131 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 2132
c18487ee 2133 return 0;
a2fbb9ea
ET		 2134}
2135
0d40f0d4
YR		 2136int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2137{
2138 u32 gpio_reg = 0;
2139 int rc = 0;
2140
2141 /* Any port swapping should be handled by caller. */
2142
2143 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2144 /* read GPIO and mask except the float bits */
2145 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2146 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2147 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2148 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2149
2150 switch (mode) {
2151 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2152 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2153 /* set CLR */
2154 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2155 break;
2156
2157 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2158 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2159 /* set SET */
2160 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2161 break;
2162
2163 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2164 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2165 /* set FLOAT */
2166 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2167 break;
2168
2169 default:
2170 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2171 rc = -EINVAL;
2172 break;
2173 }
2174
2175 if (rc == 0)
2176 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2177
2178 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2179
2180 return rc;
2181}
2182
4acac6a5
EG		 2183int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2184{
2185 /* The GPIO should be swapped if swap register is set and active */
2186 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2187 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2188 int gpio_shift = gpio_num +
2189 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2190 u32 gpio_mask = (1 << gpio_shift);
2191 u32 gpio_reg;
2192
2193 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2194 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2195 return -EINVAL;
2196 }
2197
2198 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2199 /* read GPIO int */
2200 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2201
2202 switch (mode) {
2203 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
51c1a580
MS		 2204 DP(NETIF_MSG_LINK,
2205 "Clear GPIO INT %d (shift %d) -> output low\n",
2206 gpio_num, gpio_shift);
4acac6a5
EG		 2207 /* clear SET and set CLR */
2208 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2209 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2210 break;
2211
2212 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
51c1a580
MS		 2213 DP(NETIF_MSG_LINK,
2214 "Set GPIO INT %d (shift %d) -> output high\n",
2215 gpio_num, gpio_shift);
4acac6a5
EG		 2216 /* clear CLR and set SET */
2217 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2218 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2219 break;
2220
2221 default:
2222 break;
2223 }
2224
2225 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2226 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2227
2228 return 0;
2229}
2230
d6d99a3f 2231static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
a2fbb9ea 2232{
c18487ee 2233 u32 spio_reg;
a2fbb9ea 2234
d6d99a3f
YM		 2235 /* Only 2 SPIOs are configurable */
2236 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2237 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
c18487ee 2238 return -EINVAL;
a2fbb9ea
ET		 2239 }
2240
4a37fb66 2241 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2242 /* read SPIO and mask except the float bits */
d6d99a3f 2243 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
a2fbb9ea 2244
c18487ee 2245 switch (mode) {
d6d99a3f
YM		 2246 case MISC_SPIO_OUTPUT_LOW:
2247 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
c18487ee 2248 /* clear FLOAT and set CLR */
d6d99a3f
YM		 2249 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2250 spio_reg |= (spio << MISC_SPIO_CLR_POS);
c18487ee 2251 break;
a2fbb9ea 2252
d6d99a3f
YM		 2253 case MISC_SPIO_OUTPUT_HIGH:
2254 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
c18487ee 2255 /* clear FLOAT and set SET */
d6d99a3f
YM		 2256 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2257 spio_reg |= (spio << MISC_SPIO_SET_POS);
c18487ee 2258 break;
a2fbb9ea 2259
d6d99a3f
YM		 2260 case MISC_SPIO_INPUT_HI_Z:
2261 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
c18487ee 2262 /* set FLOAT */
d6d99a3f 2263 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
c18487ee 2264 break;
a2fbb9ea 2265
c18487ee
YR		 2266 default:
2267 break;
a2fbb9ea
ET		 2268 }
2269
c18487ee 2270 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2271 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2272
a2fbb9ea
ET		 2273 return 0;
2274}
2275
9f6c9258 2276void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2277{
a22f0788 2278 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2279 switch (bp->link_vars.ieee_fc &
2280 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2281 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2282 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2283 ADVERTISED_Pause);
c18487ee 2284 break;
356e2385 2285
c18487ee 2286 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2287 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2288 ADVERTISED_Pause);
c18487ee 2289 break;
356e2385 2290
c18487ee 2291 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2292 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2293 break;
356e2385 2294
c18487ee 2295 default:
a22f0788 2296 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2297 ADVERTISED_Pause);
c18487ee
YR		 2298 break;
2299 }
2300}
f1410647 2301
cd1dfce2 2302static void bnx2x_set_requested_fc(struct bnx2x *bp)
c18487ee 2303{
cd1dfce2
YM		 2304 /* Initialize link parameters structure variables
2305 * It is recommended to turn off RX FC for jumbo frames
2306 * for better performance
2307 */
2308 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2309 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2310 else
2311 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2312}
a2fbb9ea 2313
9156b30b
DK		 2314static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2315{
2316 u32 pause_enabled = 0;
2317
2318 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2319 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2320 pause_enabled = 1;
2321
2322 REG_WR(bp, BAR_USTRORM_INTMEM +
2323 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2324 pause_enabled);
2325 }
2326
2327 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2328 pause_enabled ? "enabled" : "disabled");
2329}
2330
cd1dfce2
YM		 2331int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2332{
2333 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2334 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2335
2336 if (!BP_NOMCP(bp)) {
2337 bnx2x_set_requested_fc(bp);
4a37fb66 2338 bnx2x_acquire_phy_lock(bp);
b5bf9068 2339
a22f0788 2340 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2341 struct link_params *lp = &bp->link_params;
2342 lp->loopback_mode = LOOPBACK_XGXS;
2343 /* do PHY loopback at 10G speed, if possible */
2344 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2345 if (lp->speed_cap_mask[cfx_idx] &
2346 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2347 lp->req_line_speed[cfx_idx] =
2348 SPEED_10000;
2349 else
2350 lp->req_line_speed[cfx_idx] =
2351 SPEED_1000;
2352 }
a22f0788 2353 }
b5bf9068 2354
8970b2e4
MS		 2355 if (load_mode == LOAD_LOOPBACK_EXT) {
2356 struct link_params *lp = &bp->link_params;
2357 lp->loopback_mode = LOOPBACK_EXT;
2358 }
2359
19680c48 2360 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2361
4a37fb66 2362 bnx2x_release_phy_lock(bp);
a2fbb9ea 2363
9156b30b
DK		 2364 bnx2x_init_dropless_fc(bp);
2365
3c96c68b
EG		 2366 bnx2x_calc_fc_adv(bp);
2367
cd1dfce2 2368 if (bp->link_vars.link_up) {
b5bf9068 2369 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2370 bnx2x_link_report(bp);
cd1dfce2
YM		 2371 }
2372 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2373 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2374 return rc;
2375 }
f5372251 2376 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2377 return -EINVAL;
a2fbb9ea
ET		 2378}
2379
9f6c9258 2380void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2381{
19680c48 2382 if (!BP_NOMCP(bp)) {
4a37fb66 2383 bnx2x_acquire_phy_lock(bp);
19680c48 2384 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2385 bnx2x_release_phy_lock(bp);
a2fbb9ea 2386
9156b30b
DK		 2387 bnx2x_init_dropless_fc(bp);
2388
19680c48
EG		 2389 bnx2x_calc_fc_adv(bp);
2390 } else
f5372251 2391 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2392}
a2fbb9ea 2393
c18487ee
YR		 2394static void bnx2x__link_reset(struct bnx2x *bp)
2395{
19680c48 2396 if (!BP_NOMCP(bp)) {
4a37fb66 2397 bnx2x_acquire_phy_lock(bp);
5d07d868 2398 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
4a37fb66 2399 bnx2x_release_phy_lock(bp);
19680c48 2400 } else
f5372251 2401 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2402}
a2fbb9ea 2403
5d07d868
YM		 2404void bnx2x_force_link_reset(struct bnx2x *bp)
2405{
2406 bnx2x_acquire_phy_lock(bp);
2407 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2408 bnx2x_release_phy_lock(bp);
2409}
2410
a22f0788 2411u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2412{
2145a920 2413 u8 rc = 0;
a2fbb9ea 2414
2145a920
VZ		 2415 if (!BP_NOMCP(bp)) {
2416 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2417 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2418 is_serdes);
2145a920
VZ		 2419 bnx2x_release_phy_lock(bp);
2420 } else
2421 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2422
c18487ee
YR		 2423 return rc;
2424}
a2fbb9ea 2425
2691d51d
EG		 2426/* Calculates the sum of vn_min_rates.
2427 It's needed for further normalizing of the min_rates.
2428 Returns:
2429 sum of vn_min_rates.
2430 or
2431 0 - if all the min_rates are 0.
16a5fd92 2432 In the later case fairness algorithm should be deactivated.
2691d51d
EG		 2433 If not all min_rates are zero then those that are zeroes will be set to 1.
2434 */
b475d78f
YM		 2435static void bnx2x_calc_vn_min(struct bnx2x *bp,
2436 struct cmng_init_input *input)
2691d51d
EG		 2437{
2438 int all_zero = 1;
2691d51d
EG		 2439 int vn;
2440
3395a033 2441 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2442 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2443 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2444 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2445
2446 /* Skip hidden vns */
2447 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
b475d78f 2448 vn_min_rate = 0;
2691d51d 2449 /* If min rate is zero - set it to 1 */
b475d78f 2450 else if (!vn_min_rate)
2691d51d
EG		 2451 vn_min_rate = DEF_MIN_RATE;
2452 else
2453 all_zero = 0;
2454
b475d78f 2455 input->vnic_min_rate[vn] = vn_min_rate;
2691d51d
EG		 2456 }
2457
30ae438b
DK		 2458 /* if ETS or all min rates are zeros - disable fairness */
2459 if (BNX2X_IS_ETS_ENABLED(bp)) {
b475d78f 2460 input->flags.cmng_enables &=
30ae438b
DK		 2461 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2462 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2463 } else if (all_zero) {
b475d78f 2464 input->flags.cmng_enables &=
b015e3d1 2465 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
b475d78f
YM		 2466 DP(NETIF_MSG_IFUP,
2467 "All MIN values are zeroes fairness will be disabled\n");
b015e3d1 2468 } else
b475d78f 2469 input->flags.cmng_enables |=
b015e3d1 2470 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2471}
2472
b475d78f
YM		 2473static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2474 struct cmng_init_input *input)
34f80b04 2475{
b475d78f 2476 u16 vn_max_rate;
f2e0899f 2477 u32 vn_cfg = bp->mf_config[vn];
34f80b04 2478
b475d78f 2479 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
34f80b04 2480 vn_max_rate = 0;
b475d78f 2481 else {
faa6fcbb
DK		 2482 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2483
b475d78f 2484 if (IS_MF_SI(bp)) {
faa6fcbb
DK		 2485 /* maxCfg in percents of linkspeed */
2486 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
b475d78f 2487 } else /* SD modes */
faa6fcbb
DK		 2488 /* maxCfg is absolute in 100Mb units */
2489 vn_max_rate = maxCfg * 100;
34f80b04 2490 }
f85582f8 2491
b475d78f 2492 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
34f80b04 2493
b475d78f 2494 input->vnic_max_rate[vn] = vn_max_rate;
34f80b04 2495}
f85582f8 2496
523224a3
DK		 2497static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2498{
2499 if (CHIP_REV_IS_SLOW(bp))
2500 return CMNG_FNS_NONE;
fb3bff17 2501 if (IS_MF(bp))
523224a3
DK		 2502 return CMNG_FNS_MINMAX;
2503
2504 return CMNG_FNS_NONE;
2505}
2506
2ae17f66 2507void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2508{
0793f83f 2509 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2510
2511 if (BP_NOMCP(bp))
16a5fd92 2512 return; /* what should be the default value in this case */
523224a3 2513
0793f83f
DK		 2514 /* For 2 port configuration the absolute function number formula
2515 * is:
2516 * abs_func = 2 * vn + BP_PORT + BP_PATH
2517 *
2518 * and there are 4 functions per port
2519 *
2520 * For 4 port configuration it is
2521 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2522 *
2523 * and there are 2 functions per port
2524 */
3395a033 2525 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2526 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2527
2528 if (func >= E1H_FUNC_MAX)
2529 break;
2530
f2e0899f 2531 bp->mf_config[vn] =
523224a3
DK		 2532 MF_CFG_RD(bp, func_mf_config[func].config);
2533 }
a3348722
BW		 2534 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2535 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2536 bp->flags |= MF_FUNC_DIS;
2537 } else {
2538 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2539 bp->flags &= ~MF_FUNC_DIS;
2540 }
523224a3
DK		 2541}
2542
2543static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2544{
b475d78f
YM		 2545 struct cmng_init_input input;
2546 memset(&input, 0, sizeof(struct cmng_init_input));
2547
2548 input.port_rate = bp->link_vars.line_speed;
523224a3 2549
568e2426 2550 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
523224a3
DK		 2551 int vn;
2552
523224a3
DK		 2553 /* read mf conf from shmem */
2554 if (read_cfg)
2555 bnx2x_read_mf_cfg(bp);
2556
523224a3 2557 /* vn_weight_sum and enable fairness if not 0 */
b475d78f 2558 bnx2x_calc_vn_min(bp, &input);
523224a3
DK		 2559
2560 /* calculate and set min-max rate for each vn */
c4154f25 2561 if (bp->port.pmf)
3395a033 2562 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
b475d78f 2563 bnx2x_calc_vn_max(bp, vn, &input);
523224a3
DK		 2564
2565 /* always enable rate shaping and fairness */
b475d78f 2566 input.flags.cmng_enables |=
523224a3 2567 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
b475d78f
YM		 2568
2569 bnx2x_init_cmng(&input, &bp->cmng);
523224a3
DK		 2570 return;
2571 }
2572
2573 /* rate shaping and fairness are disabled */
2574 DP(NETIF_MSG_IFUP,
2575 "rate shaping and fairness are disabled\n");
2576}
34f80b04 2577
1191cb83
ED		 2578static void storm_memset_cmng(struct bnx2x *bp,
2579 struct cmng_init *cmng,
2580 u8 port)
2581{
2582 int vn;
2583 size_t size = sizeof(struct cmng_struct_per_port);
2584
2585 u32 addr = BAR_XSTRORM_INTMEM +
2586 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2587
2588 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2589
2590 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2591 int func = func_by_vn(bp, vn);
2592
2593 addr = BAR_XSTRORM_INTMEM +
2594 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2595 size = sizeof(struct rate_shaping_vars_per_vn);
2596 __storm_memset_struct(bp, addr, size,
2597 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2598
2599 addr = BAR_XSTRORM_INTMEM +
2600 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2601 size = sizeof(struct fairness_vars_per_vn);
2602 __storm_memset_struct(bp, addr, size,
2603 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2604 }
2605}
2606
568e2426
DK		 2607/* init cmng mode in HW according to local configuration */
2608void bnx2x_set_local_cmng(struct bnx2x *bp)
2609{
2610 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2611
2612 if (cmng_fns != CMNG_FNS_NONE) {
2613 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2614 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2615 } else {
2616 /* rate shaping and fairness are disabled */
2617 DP(NETIF_MSG_IFUP,
2618 "single function mode without fairness\n");
2619 }
2620}
2621
c18487ee
YR		 2622/* This function is called upon link interrupt */
2623static void bnx2x_link_attn(struct bnx2x *bp)
2624{
bb2a0f7a
YG		 2625 /* Make sure that we are synced with the current statistics */
2626 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2627
c18487ee 2628 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2629
9156b30b 2630 bnx2x_init_dropless_fc(bp);
1c06328c 2631
9156b30b 2632 if (bp->link_vars.link_up) {
1c06328c 2633
619c5cb6 2634 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2635 struct host_port_stats *pstats;
2636
2637 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2638 /* reset old mac stats */
bb2a0f7a
YG		 2639 memset(&(pstats->mac_stx[0]), 0,
2640 sizeof(struct mac_stx));
2641 }
f34d28ea 2642 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2643 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2644 }
2645
568e2426
DK		 2646 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2647 bnx2x_set_local_cmng(bp);
9fdc3e95 2648
2ae17f66
VZ		 2649 __bnx2x_link_report(bp);
2650
9fdc3e95
DK		 2651 if (IS_MF(bp))
2652 bnx2x_link_sync_notify(bp);
c18487ee 2653}
a2fbb9ea 2654
9f6c9258 2655void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2656{
2ae17f66 2657 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2658 return;
a2fbb9ea 2659
00253a8c 2660 /* read updated dcb configuration */
ad5afc89
AE		 2661 if (IS_PF(bp)) {
2662 bnx2x_dcbx_pmf_update(bp);
2663 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2664 if (bp->link_vars.link_up)
2665 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2666 else
2667 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2668 /* indicate link status */
2669 bnx2x_link_report(bp);
a2fbb9ea 2670
ad5afc89
AE		 2671 } else { /* VF */
2672 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2673 SUPPORTED_10baseT_Full |
2674 SUPPORTED_100baseT_Half |
2675 SUPPORTED_100baseT_Full |
2676 SUPPORTED_1000baseT_Full |
2677 SUPPORTED_2500baseX_Full |
2678 SUPPORTED_10000baseT_Full |
2679 SUPPORTED_TP |
2680 SUPPORTED_FIBRE |
2681 SUPPORTED_Autoneg |
2682 SUPPORTED_Pause |
2683 SUPPORTED_Asym_Pause);
2684 bp->port.advertising[0] = bp->port.supported[0];
2685
2686 bp->link_params.bp = bp;
2687 bp->link_params.port = BP_PORT(bp);
2688 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2689 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2690 bp->link_params.req_line_speed[0] = SPEED_10000;
2691 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2692 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2693 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2694 bp->link_vars.line_speed = SPEED_10000;
2695 bp->link_vars.link_status =
2696 (LINK_STATUS_LINK_UP |
2697 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2698 bp->link_vars.link_up = 1;
2699 bp->link_vars.duplex = DUPLEX_FULL;
2700 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2701 __bnx2x_link_report(bp);
bb2a0f7a 2702 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
ad5afc89 2703 }
a2fbb9ea 2704}
a2fbb9ea 2705
a3348722
BW		 2706static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2707 u16 vlan_val, u8 allowed_prio)
2708{
86564c3f 2709 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2710 struct bnx2x_func_afex_update_params *f_update_params =
2711 &func_params.params.afex_update;
2712
2713 func_params.f_obj = &bp->func_obj;
2714 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2715
2716 /* no need to wait for RAMROD completion, so don't
2717 * set RAMROD_COMP_WAIT flag
2718 */
2719
2720 f_update_params->vif_id = vifid;
2721 f_update_params->afex_default_vlan = vlan_val;
2722 f_update_params->allowed_priorities = allowed_prio;
2723
2724 /* if ramrod can not be sent, response to MCP immediately */
2725 if (bnx2x_func_state_change(bp, &func_params) < 0)
2726 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2727
2728 return 0;
2729}
2730
2731static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2732 u16 vif_index, u8 func_bit_map)
2733{
86564c3f 2734 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2735 struct bnx2x_func_afex_viflists_params *update_params =
2736 &func_params.params.afex_viflists;
2737 int rc;
2738 u32 drv_msg_code;
2739
2740 /* validate only LIST_SET and LIST_GET are received from switch */
2741 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2742 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2743 cmd_type);
2744
2745 func_params.f_obj = &bp->func_obj;
2746 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2747
2748 /* set parameters according to cmd_type */
2749 update_params->afex_vif_list_command = cmd_type;
86564c3f 2750 update_params->vif_list_index = vif_index;
a3348722
BW		 2751 update_params->func_bit_map =
2752 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2753 update_params->func_to_clear = 0;
2754 drv_msg_code =
2755 (cmd_type == VIF_LIST_RULE_GET) ?
2756 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2757 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2758
2759 /* if ramrod can not be sent, respond to MCP immediately for
2760 * SET and GET requests (other are not triggered from MCP)
2761 */
2762 rc = bnx2x_func_state_change(bp, &func_params);
2763 if (rc < 0)
2764 bnx2x_fw_command(bp, drv_msg_code, 0);
2765
2766 return 0;
2767}
2768
2769static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2770{
2771 struct afex_stats afex_stats;
2772 u32 func = BP_ABS_FUNC(bp);
2773 u32 mf_config;
2774 u16 vlan_val;
2775 u32 vlan_prio;
2776 u16 vif_id;
2777 u8 allowed_prio;
2778 u8 vlan_mode;
2779 u32 addr_to_write, vifid, addrs, stats_type, i;
2780
2781 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2782 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2783 DP(BNX2X_MSG_MCP,
2784 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2785 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2786 }
2787
2788 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2789 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2790 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2791 DP(BNX2X_MSG_MCP,
2792 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2793 vifid, addrs);
2794 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2795 addrs);
2796 }
2797
2798 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2799 addr_to_write = SHMEM2_RD(bp,
2800 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2801 stats_type = SHMEM2_RD(bp,
2802 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2803
2804 DP(BNX2X_MSG_MCP,
2805 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2806 addr_to_write);
2807
2808 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2809
2810 /* write response to scratchpad, for MCP */
2811 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2812 REG_WR(bp, addr_to_write + i*sizeof(u32),
2813 *(((u32 *)(&afex_stats))+i));
2814
2815 /* send ack message to MCP */
2816 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2817 }
2818
2819 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2820 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2821 bp->mf_config[BP_VN(bp)] = mf_config;
2822 DP(BNX2X_MSG_MCP,
2823 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2824 mf_config);
2825
2826 /* if VIF_SET is "enabled" */
2827 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2828 /* set rate limit directly to internal RAM */
2829 struct cmng_init_input cmng_input;
2830 struct rate_shaping_vars_per_vn m_rs_vn;
2831 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2832 u32 addr = BAR_XSTRORM_INTMEM +
2833 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2834
2835 bp->mf_config[BP_VN(bp)] = mf_config;
2836
2837 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2838 m_rs_vn.vn_counter.rate =
2839 cmng_input.vnic_max_rate[BP_VN(bp)];
2840 m_rs_vn.vn_counter.quota =
2841 (m_rs_vn.vn_counter.rate *
2842 RS_PERIODIC_TIMEOUT_USEC) / 8;
2843
2844 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2845
2846 /* read relevant values from mf_cfg struct in shmem */
2847 vif_id =
2848 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2849 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2850 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2851 vlan_val =
2852 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2853 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2854 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2855 vlan_prio = (mf_config &
2856 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2857 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2858 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2859 vlan_mode =
2860 (MF_CFG_RD(bp,
2861 func_mf_config[func].afex_config) &
2862 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2863 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2864 allowed_prio =
2865 (MF_CFG_RD(bp,
2866 func_mf_config[func].afex_config) &
2867 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2868 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2869
2870 /* send ramrod to FW, return in case of failure */
2871 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2872 allowed_prio))
2873 return;
2874
2875 bp->afex_def_vlan_tag = vlan_val;
2876 bp->afex_vlan_mode = vlan_mode;
2877 } else {
2878 /* notify link down because BP->flags is disabled */
2879 bnx2x_link_report(bp);
2880
2881 /* send INVALID VIF ramrod to FW */
2882 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2883
2884 /* Reset the default afex VLAN */
2885 bp->afex_def_vlan_tag = -1;
2886 }
2887 }
2888}
2889
34f80b04
EG		 2890static void bnx2x_pmf_update(struct bnx2x *bp)
2891{
2892 int port = BP_PORT(bp);
2893 u32 val;
2894
2895 bp->port.pmf = 1;
51c1a580 2896 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
34f80b04 2897
3deb8167
YR		 2898 /*
2899 * We need the mb() to ensure the ordering between the writing to
2900 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2901 */
2902 smp_mb();
2903
2904 /* queue a periodic task */
2905 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2906
ef01854e
DK		 2907 bnx2x_dcbx_pmf_update(bp);
2908
34f80b04 2909 /* enable nig attention */
3395a033 2910 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2911 if (bp->common.int_block == INT_BLOCK_HC) {
2912 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2913 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2914 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2915 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2916 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2917 }
bb2a0f7a
YG		 2918
2919 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2920}
2921
c18487ee 2922/* end of Link */
a2fbb9ea
ET		 2923
2924/* slow path */
2925
2926/*
2927 * General service functions
2928 */
2929
2691d51d 2930/* send the MCP a request, block until there is a reply */
a22f0788 2931u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2932{
f2e0899f 2933 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2934 u32 seq;
2691d51d
EG		 2935 u32 rc = 0;
2936 u32 cnt = 1;
2937 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2938
c4ff7cbf 2939 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2940 seq = ++bp->fw_seq;
f2e0899f
DK		 2941 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2942 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2943
754a2f52
DK		 2944 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2945 (command | seq), param);
2691d51d
EG		 2946
2947 do {
2948 /* let the FW do it's magic ... */
2949 msleep(delay);
2950
f2e0899f 2951 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2952
c4ff7cbf
EG		 2953 /* Give the FW up to 5 second (500*10ms) */
2954 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2955
2956 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2957 cnt*delay, rc, seq);
2958
2959 /* is this a reply to our command? */
2960 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2961 rc &= FW_MSG_CODE_MASK;
2962 else {
2963 /* FW BUG! */
2964 BNX2X_ERR("FW failed to respond!\n");
2965 bnx2x_fw_dump(bp);
2966 rc = 0;
2967 }
c4ff7cbf 2968 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2969
2970 return rc;
2971}
2972
1191cb83
ED		 2973static void storm_memset_func_cfg(struct bnx2x *bp,
2974 struct tstorm_eth_function_common_config *tcfg,
2975 u16 abs_fid)
2976{
2977 size_t size = sizeof(struct tstorm_eth_function_common_config);
2978
2979 u32 addr = BAR_TSTRORM_INTMEM +
2980 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2981
2982 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2983}
2984
619c5cb6
VZ		 2985void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2986{
2987 if (CHIP_IS_E1x(bp)) {
2988 struct tstorm_eth_function_common_config tcfg = {0};
2989
2990 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2991 }
2992
2993 /* Enable the function in the FW */
2994 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2995 storm_memset_func_en(bp, p->func_id, 1);
2996
2997 /* spq */
2998 if (p->func_flgs & FUNC_FLG_SPQ) {
2999 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3000 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3001 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3002 }
3003}
3004
6383c0b3 3005/**
16a5fd92 3006 * bnx2x_get_common_flags - Return common flags
6383c0b3
AE		 3007 *
3008 * @bp device handle
3009 * @fp queue handle
3010 * @zero_stats TRUE if statistics zeroing is needed
3011 *
3012 * Return the flags that are common for the Tx-only and not normal connections.
3013 */
1191cb83
ED		 3014static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3015 struct bnx2x_fastpath *fp,
3016 bool zero_stats)
28912902 3017{
619c5cb6
VZ		 3018 unsigned long flags = 0;
3019
3020 /* PF driver will always initialize the Queue to an ACTIVE state */
3021 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 3022
6383c0b3 3023 /* tx only connections collect statistics (on the same index as the
91226790
DK		 3024 * parent connection). The statistics are zeroed when the parent
3025 * connection is initialized.
6383c0b3 3026 */
50f0a562
BW		 3027
3028 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3029 if (zero_stats)
3030 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3031
c14db202
YM		 3032 if (bp->flags & TX_SWITCHING)
3033 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3034
91226790 3035 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
e287a75c 3036 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
6383c0b3 3037
823e1d90
YM		 3038#ifdef BNX2X_STOP_ON_ERROR
3039 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3040#endif
3041
6383c0b3
AE		 3042 return flags;
3043}
3044
1191cb83
ED		 3045static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3046 struct bnx2x_fastpath *fp,
3047 bool leading)
6383c0b3
AE		 3048{
3049 unsigned long flags = 0;
3050
619c5cb6
VZ		 3051 /* calculate other queue flags */
3052 if (IS_MF_SD(bp))
3053 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 3054
a3348722 3055 if (IS_FCOE_FP(fp)) {
619c5cb6 3056 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
a3348722
BW		 3057 /* For FCoE - force usage of default priority (for afex) */
3058 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3059 }
523224a3 3060
f5219d8e 3061 if (!fp->disable_tpa) {
619c5cb6 3062 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e 3063 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
621b4d66
DK		 3064 if (fp->mode == TPA_MODE_GRO)
3065 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
f5219d8e 3066 }
619c5cb6 3067
619c5cb6
VZ		 3068 if (leading) {
3069 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3070 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3071 }
523224a3 3072
619c5cb6
VZ		 3073 /* Always set HW VLAN stripping */
3074 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 3075
a3348722
BW		 3076 /* configure silent vlan removal */
3077 if (IS_MF_AFEX(bp))
3078 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3079
6383c0b3 3080 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 3081}
3082
619c5cb6 3083static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 3084 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3085 u8 cos)
619c5cb6
VZ		 3086{
3087 gen_init->stat_id = bnx2x_stats_id(fp);
3088 gen_init->spcl_id = fp->cl_id;
3089
3090 /* Always use mini-jumbo MTU for FCoE L2 ring */
3091 if (IS_FCOE_FP(fp))
3092 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3093 else
3094 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 3095
3096 gen_init->cos = cos;
619c5cb6
VZ		 3097}
3098
3099static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 3100 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 3101 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 3102{
619c5cb6 3103 u8 max_sge = 0;
523224a3
DK		 3104 u16 sge_sz = 0;
3105 u16 tpa_agg_size = 0;
3106
523224a3 3107 if (!fp->disable_tpa) {
dfacf138
DK		 3108 pause->sge_th_lo = SGE_TH_LO(bp);
3109 pause->sge_th_hi = SGE_TH_HI(bp);
3110
3111 /* validate SGE ring has enough to cross high threshold */
3112 WARN_ON(bp->dropless_fc &&
3113 pause->sge_th_hi + FW_PREFETCH_CNT >
3114 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3115
924d75ab 3116 tpa_agg_size = TPA_AGG_SIZE;
523224a3
DK		 3117 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3118 SGE_PAGE_SHIFT;
3119 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3120 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
924d75ab 3121 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
523224a3
DK		 3122 }
3123
3124 /* pause - not for e1 */
3125 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 3126 pause->bd_th_lo = BD_TH_LO(bp);
3127 pause->bd_th_hi = BD_TH_HI(bp);
3128
3129 pause->rcq_th_lo = RCQ_TH_LO(bp);
3130 pause->rcq_th_hi = RCQ_TH_HI(bp);
3131 /*
3132 * validate that rings have enough entries to cross
3133 * high thresholds
3134 */
3135 WARN_ON(bp->dropless_fc &&
3136 pause->bd_th_hi + FW_PREFETCH_CNT >
3137 bp->rx_ring_size);
3138 WARN_ON(bp->dropless_fc &&
3139 pause->rcq_th_hi + FW_PREFETCH_CNT >
3140 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 3141
523224a3
DK		 3142 pause->pri_map = 1;
3143 }
3144
3145 /* rxq setup */
523224a3
DK		 3146 rxq_init->dscr_map = fp->rx_desc_mapping;
3147 rxq_init->sge_map = fp->rx_sge_mapping;
3148 rxq_init->rcq_map = fp->rx_comp_mapping;
3149 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 3150
619c5cb6
VZ		 3151 /* This should be a maximum number of data bytes that may be
3152 * placed on the BD (not including paddings).
3153 */
e52fcb24 3154 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3cdeec22 3155 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 3156
523224a3 3157 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 3158 rxq_init->tpa_agg_sz = tpa_agg_size;
3159 rxq_init->sge_buf_sz = sge_sz;
3160 rxq_init->max_sges_pkt = max_sge;
619c5cb6 3161 rxq_init->rss_engine_id = BP_FUNC(bp);
259afa1f 3162 rxq_init->mcast_engine_id = BP_FUNC(bp);
619c5cb6
VZ		 3163
3164 /* Maximum number or simultaneous TPA aggregation for this Queue.
3165 *
2de67439 3166 * For PF Clients it should be the maximum available number.
619c5cb6
VZ		 3167 * VF driver(s) may want to define it to a smaller value.
3168 */
dfacf138 3169 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 3170
523224a3
DK		 3171 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3172 rxq_init->fw_sb_id = fp->fw_sb_id;
3173
ec6ba945
VZ		 3174 if (IS_FCOE_FP(fp))
3175 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3176 else
6383c0b3 3177 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
a3348722
BW		 3178 /* configure silent vlan removal
3179 * if multi function mode is afex, then mask default vlan
3180 */
3181 if (IS_MF_AFEX(bp)) {
3182 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3183 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3184 }
523224a3
DK		 3185}
3186
619c5cb6 3187static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 3188 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3189 u8 cos)
523224a3 3190{
65565884 3191 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
6383c0b3 3192 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 3193 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3194 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 3195
619c5cb6 3196 /*
16a5fd92 3197 * set the tss leading client id for TX classification ==
619c5cb6
VZ		 3198 * leading RSS client id
3199 */
3200 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3201
ec6ba945
VZ		 3202 if (IS_FCOE_FP(fp)) {
3203 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3204 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3205 }
523224a3
DK		 3206}
3207
8d96286a 3208static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 3209{
3210 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 3211 struct event_ring_data eq_data = { {0} };
3212 u16 flags;
3213
619c5cb6 3214 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3215 /* reset IGU PF statistics: MSIX + ATTN */
3216 /* PF */
3217 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3218 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3219 (CHIP_MODE_IS_4_PORT(bp) ?
3220 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3221 /* ATTN */
3222 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3223 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3224 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3225 (CHIP_MODE_IS_4_PORT(bp) ?
3226 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3227 }
3228
523224a3
DK		 3229 /* function setup flags */
3230 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3231
619c5cb6
VZ		 3232 /* This flag is relevant for E1x only.
3233 * E2 doesn't have a TPA configuration in a function level.
523224a3 3234 */
619c5cb6 3235 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 3236
3237 func_init.func_flgs = flags;
3238 func_init.pf_id = BP_FUNC(bp);
3239 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 3240 func_init.spq_map = bp->spq_mapping;
3241 func_init.spq_prod = bp->spq_prod_idx;
3242
3243 bnx2x_func_init(bp, &func_init);
3244
3245 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3246
3247 /*
619c5cb6
VZ		 3248 * Congestion management values depend on the link rate
3249 * There is no active link so initial link rate is set to 10 Gbps.
3250 * When the link comes up The congestion management values are
3251 * re-calculated according to the actual link rate.
3252 */
523224a3
DK		 3253 bp->link_vars.line_speed = SPEED_10000;
3254 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3255
3256 /* Only the PMF sets the HW */
3257 if (bp->port.pmf)
3258 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3259
86564c3f 3260 /* init Event Queue - PCI bus guarantees correct endianity*/
523224a3
DK		 3261 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3262 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3263 eq_data.producer = bp->eq_prod;
3264 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3265 eq_data.sb_id = DEF_SB_ID;
3266 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3267}
3268
523224a3
DK		 3269static void bnx2x_e1h_disable(struct bnx2x *bp)
3270{
3271 int port = BP_PORT(bp);
3272
619c5cb6 3273 bnx2x_tx_disable(bp);
523224a3
DK		 3274
3275 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 3276}
3277
3278static void bnx2x_e1h_enable(struct bnx2x *bp)
3279{
3280 int port = BP_PORT(bp);
3281
3282 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3283
16a5fd92 3284 /* Tx queue should be only re-enabled */
523224a3
DK		 3285 netif_tx_wake_all_queues(bp->dev);
3286
3287 /*
3288 * Should not call netif_carrier_on since it will be called if the link
3289 * is up when checking for link state
3290 */
3291}
3292
1d187b34
BW		 3293#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3294
3295static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3296{
3297 struct eth_stats_info *ether_stat =
3298 &bp->slowpath->drv_info_to_mcp.ether_stat;
3ec9f9ca
AE		 3299 struct bnx2x_vlan_mac_obj *mac_obj =
3300 &bp->sp_objs->mac_obj;
3301 int i;
1d187b34 3302
786fdf0b
DC		 3303 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3304 ETH_STAT_INFO_VERSION_LEN);
1d187b34 3305
3ec9f9ca
AE		 3306 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3307 * mac_local field in ether_stat struct. The base address is offset by 2
3308 * bytes to account for the field being 8 bytes but a mac address is
3309 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3310 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3311 * allocated by the ether_stat struct, so the macs will land in their
3312 * proper positions.
3313 */
3314 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3315 memset(ether_stat->mac_local + i, 0,
3316 sizeof(ether_stat->mac_local[0]));
3317 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3318 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3319 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3320 ETH_ALEN);
1d187b34 3321 ether_stat->mtu_size = bp->dev->mtu;
1d187b34
BW		 3322 if (bp->dev->features & NETIF_F_RXCSUM)
3323 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3324 if (bp->dev->features & NETIF_F_TSO)
3325 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3326 ether_stat->feature_flags |= bp->common.boot_mode;
3327
3328 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3329
3330 ether_stat->txq_size = bp->tx_ring_size;
3331 ether_stat->rxq_size = bp->rx_ring_size;
0c757dee 3332
fcf93a0a 3333#ifdef CONFIG_BNX2X_SRIOV
0c757dee 3334 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
fcf93a0a 3335#endif
1d187b34
BW		 3336}
3337
3338static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3339{
3340 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3341 struct fcoe_stats_info *fcoe_stat =
3342 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3343
55c11941
MS		 3344 if (!CNIC_LOADED(bp))
3345 return;
3346
3ec9f9ca 3347 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
1d187b34
BW		 3348
3349 fcoe_stat->qos_priority =
3350 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3351
3352 /* insert FCoE stats from ramrod response */
3353 if (!NO_FCOE(bp)) {
3354 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
65565884 3355 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3356 tstorm_queue_statistics;
3357
3358 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
65565884 3359 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3360 xstorm_queue_statistics;
3361
3362 struct fcoe_statistics_params *fw_fcoe_stat =
3363 &bp->fw_stats_data->fcoe;
3364
86564c3f
YM		 3365 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3366 fcoe_stat->rx_bytes_lo,
3367 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
1d187b34 3368
86564c3f
YM		 3369 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3370 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3371 fcoe_stat->rx_bytes_lo,
3372 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
1d187b34 3373
86564c3f
YM		 3374 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3375 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3376 fcoe_stat->rx_bytes_lo,
3377 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
1d187b34 3378
86564c3f
YM		 3379 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3380 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3381 fcoe_stat->rx_bytes_lo,
3382 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
1d187b34 3383
86564c3f
YM		 3384 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3385 fcoe_stat->rx_frames_lo,
3386 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
1d187b34 3387
86564c3f
YM		 3388 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3389 fcoe_stat->rx_frames_lo,
3390 fcoe_q_tstorm_stats->rcv_ucast_pkts);
1d187b34 3391
86564c3f
YM		 3392 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3393 fcoe_stat->rx_frames_lo,
3394 fcoe_q_tstorm_stats->rcv_bcast_pkts);
1d187b34 3395
86564c3f
YM		 3396 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3397 fcoe_stat->rx_frames_lo,
3398 fcoe_q_tstorm_stats->rcv_mcast_pkts);
1d187b34 3399
86564c3f
YM		 3400 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3401 fcoe_stat->tx_bytes_lo,
3402 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
1d187b34 3403
86564c3f
YM		 3404 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3405 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3406 fcoe_stat->tx_bytes_lo,
3407 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
1d187b34 3408
86564c3f
YM		 3409 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3410 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3411 fcoe_stat->tx_bytes_lo,
3412 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
1d187b34 3413
86564c3f
YM		 3414 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3415 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3416 fcoe_stat->tx_bytes_lo,
3417 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
1d187b34 3418
86564c3f
YM		 3419 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3420 fcoe_stat->tx_frames_lo,
3421 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
1d187b34 3422
86564c3f
YM		 3423 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3424 fcoe_stat->tx_frames_lo,
3425 fcoe_q_xstorm_stats->ucast_pkts_sent);
1d187b34 3426
86564c3f
YM		 3427 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3428 fcoe_stat->tx_frames_lo,
3429 fcoe_q_xstorm_stats->bcast_pkts_sent);
1d187b34 3430
86564c3f
YM		 3431 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3432 fcoe_stat->tx_frames_lo,
3433 fcoe_q_xstorm_stats->mcast_pkts_sent);
1d187b34
BW		 3434 }
3435
1d187b34
BW		 3436 /* ask L5 driver to add data to the struct */
3437 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
1d187b34
BW		 3438}
3439
3440static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3441{
3442 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3443 struct iscsi_stats_info *iscsi_stat =
3444 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3445
55c11941
MS		 3446 if (!CNIC_LOADED(bp))
3447 return;
3448
3ec9f9ca
AE		 3449 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3450 ETH_ALEN);
1d187b34
BW		 3451
3452 iscsi_stat->qos_priority =
3453 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3454
1d187b34
BW		 3455 /* ask L5 driver to add data to the struct */
3456 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
1d187b34
BW		 3457}
3458
0793f83f
DK		 3459/* called due to MCP event (on pmf):
3460 * reread new bandwidth configuration
3461 * configure FW
3462 * notify others function about the change
3463 */
1191cb83 3464static void bnx2x_config_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3465{
3466 if (bp->link_vars.link_up) {
3467 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3468 bnx2x_link_sync_notify(bp);
3469 }
3470 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3471}
3472
1191cb83 3473static void bnx2x_set_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3474{
3475 bnx2x_config_mf_bw(bp);
3476 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3477}
3478
c8c60d88
YM		 3479static void bnx2x_handle_eee_event(struct bnx2x *bp)
3480{
3481 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3482 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3483}
3484
1d187b34
BW		 3485static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3486{
3487 enum drv_info_opcode op_code;
3488 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3489
3490 /* if drv_info version supported by MFW doesn't match - send NACK */
3491 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3492 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3493 return;
3494 }
3495
3496 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3497 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3498
3499 memset(&bp->slowpath->drv_info_to_mcp, 0,
3500 sizeof(union drv_info_to_mcp));
3501
3502 switch (op_code) {
3503 case ETH_STATS_OPCODE:
3504 bnx2x_drv_info_ether_stat(bp);
3505 break;
3506 case FCOE_STATS_OPCODE:
3507 bnx2x_drv_info_fcoe_stat(bp);
3508 break;
3509 case ISCSI_STATS_OPCODE:
3510 bnx2x_drv_info_iscsi_stat(bp);
3511 break;
3512 default:
3513 /* if op code isn't supported - send NACK */
3514 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3515 return;
3516 }
3517
3518 /* if we got drv_info attn from MFW then these fields are defined in
3519 * shmem2 for sure
3520 */
3521 SHMEM2_WR(bp, drv_info_host_addr_lo,
3522 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3523 SHMEM2_WR(bp, drv_info_host_addr_hi,
3524 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3525
3526 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3527}
3528
523224a3
DK		 3529static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3530{
3531 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3532
3533 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3534
3535 /*
3536 * This is the only place besides the function initialization
3537 * where the bp->flags can change so it is done without any
3538 * locks
3539 */
f2e0899f 3540 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
51c1a580 3541 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
523224a3
DK		 3542 bp->flags |= MF_FUNC_DIS;
3543
3544 bnx2x_e1h_disable(bp);
3545 } else {
51c1a580 3546 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
523224a3
DK		 3547 bp->flags &= ~MF_FUNC_DIS;
3548
3549 bnx2x_e1h_enable(bp);
3550 }
3551 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3552 }
3553 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 3554 bnx2x_config_mf_bw(bp);
523224a3
DK		 3555 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3556 }
3557
3558 /* Report results to MCP */
3559 if (dcc_event)
3560 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3561 else
3562 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3563}
3564
3565/* must be called under the spq lock */
1191cb83 3566static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
523224a3
DK		 3567{
3568 struct eth_spe *next_spe = bp->spq_prod_bd;
3569
3570 if (bp->spq_prod_bd == bp->spq_last_bd) {
3571 bp->spq_prod_bd = bp->spq;
3572 bp->spq_prod_idx = 0;
51c1a580 3573 DP(BNX2X_MSG_SP, "end of spq\n");
523224a3
DK		 3574 } else {
3575 bp->spq_prod_bd++;
3576 bp->spq_prod_idx++;
3577 }
3578 return next_spe;
3579}
3580
3581/* must be called under the spq lock */
1191cb83 3582static void bnx2x_sp_prod_update(struct bnx2x *bp)
28912902
MC		 3583{
3584 int func = BP_FUNC(bp);
3585
53e51e2f
VZ		 3586 /*
3587 * Make sure that BD data is updated before writing the producer:
3588 * BD data is written to the memory, the producer is read from the
3589 * memory, thus we need a full memory barrier to ensure the ordering.
3590 */
3591 mb();
28912902 3592
523224a3 3593 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3594 bp->spq_prod_idx);
28912902
MC		 3595 mmiowb();
3596}
3597
619c5cb6
VZ		 3598/**
3599 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3600 *
3601 * @cmd: command to check
3602 * @cmd_type: command type
3603 */
1191cb83 3604static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
619c5cb6
VZ		 3605{
3606 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3607 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3608 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3609 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3610 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3611 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3612 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3613 return true;
3614 else
3615 return false;
619c5cb6
VZ		 3616}
3617
619c5cb6
VZ		 3618/**
3619 * bnx2x_sp_post - place a single command on an SP ring
3620 *
3621 * @bp: driver handle
3622 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3623 * @cid: SW CID the command is related to
3624 * @data_hi: command private data address (high 32 bits)
3625 * @data_lo: command private data address (low 32 bits)
3626 * @cmd_type: command type (e.g. NONE, ETH)
3627 *
3628 * SP data is handled as if it's always an address pair, thus data fields are
3629 * not swapped to little endian in upper functions. Instead this function swaps
3630 * data as if it's two u32 fields.
3631 */
9f6c9258 3632int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3633 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3634{
28912902 3635 struct eth_spe *spe;
523224a3 3636 u16 type;
619c5cb6 3637 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3638
a2fbb9ea 3639#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 3640 if (unlikely(bp->panic)) {
3641 BNX2X_ERR("Can't post SP when there is panic\n");
a2fbb9ea 3642 return -EIO;
51c1a580 3643 }
a2fbb9ea
ET		 3644#endif
3645
34f80b04 3646 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3647
6e30dd4e
VZ		 3648 if (common) {
3649 if (!atomic_read(&bp->eq_spq_left)) {
3650 BNX2X_ERR("BUG! EQ ring full!\n");
3651 spin_unlock_bh(&bp->spq_lock);
3652 bnx2x_panic();
3653 return -EBUSY;
3654 }
3655 } else if (!atomic_read(&bp->cq_spq_left)) {
3656 BNX2X_ERR("BUG! SPQ ring full!\n");
3657 spin_unlock_bh(&bp->spq_lock);
3658 bnx2x_panic();
3659 return -EBUSY;
a2fbb9ea 3660 }
f1410647 3661
28912902
MC		 3662 spe = bnx2x_sp_get_next(bp);
3663
a2fbb9ea 3664 /* CID needs port number to be encoded int it */
28912902 3665 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3666 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3667 HW_CID(bp, cid));
523224a3 3668
14a94ebd
MK		 3669 /* In some cases, type may already contain the func-id
3670 * mainly in SRIOV related use cases, so we add it here only
3671 * if it's not already set.
3672 */
3673 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3674 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3675 SPE_HDR_CONN_TYPE;
3676 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3677 SPE_HDR_FUNCTION_ID);
3678 } else {
3679 type = cmd_type;
3680 }
a2fbb9ea 3681
523224a3
DK		 3682 spe->hdr.type = cpu_to_le16(type);
3683
3684 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3685 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3686
d6cae238
VZ		 3687 /*
3688 * It's ok if the actual decrement is issued towards the memory
3689 * somewhere between the spin_lock and spin_unlock. Thus no
16a5fd92 3690 * more explicit memory barrier is needed.
d6cae238
VZ		 3691 */
3692 if (common)
3693 atomic_dec(&bp->eq_spq_left);
3694 else
3695 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3696
51c1a580
MS		 3697 DP(BNX2X_MSG_SP,
3698 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3699 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3700 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3701 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3702 HW_CID(bp, cid), data_hi, data_lo, type,
3703 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3704
28912902 3705 bnx2x_sp_prod_update(bp);
34f80b04 3706 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3707 return 0;
3708}
3709
3710/* acquire split MCP access lock register */
4a37fb66 3711static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3712{
72fd0718 3713 u32 j, val;
34f80b04 3714 int rc = 0;
a2fbb9ea
ET		 3715
3716 might_sleep();
72fd0718 3717 for (j = 0; j < 1000; j++) {
3cdeec22
YM		 3718 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3719 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3720 if (val & MCPR_ACCESS_LOCK_LOCK)
a2fbb9ea
ET		 3721 break;
3722
639d65b8 3723 usleep_range(5000, 10000);
a2fbb9ea 3724 }
3cdeec22 3725 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
19680c48 3726 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3727 rc = -EBUSY;
3728 }
3729
3730 return rc;
3731}
3732
4a37fb66
YG		 3733/* release split MCP access lock register */
3734static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3735{
3cdeec22 3736 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
a2fbb9ea
ET		 3737}
3738
523224a3
DK		 3739#define BNX2X_DEF_SB_ATT_IDX 0x0001
3740#define BNX2X_DEF_SB_IDX 0x0002
3741
1191cb83 3742static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
a2fbb9ea 3743{
523224a3 3744 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3745 u16 rc = 0;
3746
3747 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3748 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3749 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3750 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3751 }
523224a3
DK		 3752
3753 if (bp->def_idx != def_sb->sp_sb.running_index) {
3754 bp->def_idx = def_sb->sp_sb.running_index;
3755 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3756 }
523224a3 3757
16a5fd92 3758 /* Do not reorder: indices reading should complete before handling */
523224a3 3759 barrier();
a2fbb9ea
ET		 3760 return rc;
3761}
3762
3763/*
3764 * slow path service functions
3765 */
3766
3767static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3768{
34f80b04 3769 int port = BP_PORT(bp);
a2fbb9ea
ET		 3770 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3771 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3772 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3773 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3774 u32 aeu_mask;
87942b46 3775 u32 nig_mask = 0;
f2e0899f 3776 u32 reg_addr;
a2fbb9ea 3777
a2fbb9ea
ET		 3778 if (bp->attn_state & asserted)
3779 BNX2X_ERR("IGU ERROR\n");
3780
3fcaf2e5
EG		 3781 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3782 aeu_mask = REG_RD(bp, aeu_addr);
3783
a2fbb9ea 3784 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3785 aeu_mask, asserted);
72fd0718 3786 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3787 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3788
3fcaf2e5
EG		 3789 REG_WR(bp, aeu_addr, aeu_mask);
3790 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3791
3fcaf2e5 3792 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3793 bp->attn_state |= asserted;
3fcaf2e5 3794 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3795
3796 if (asserted & ATTN_HARD_WIRED_MASK) {
3797 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3798
a5e9a7cf
EG		 3799 bnx2x_acquire_phy_lock(bp);
3800
877e9aa4 3801 /* save nig interrupt mask */
87942b46 3802 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3803
361c391e
YR		 3804 /* If nig_mask is not set, no need to call the update
3805 * function.
3806 */
3807 if (nig_mask) {
3808 REG_WR(bp, nig_int_mask_addr, 0);
3809
3810 bnx2x_link_attn(bp);
3811 }
a2fbb9ea
ET		 3812
3813 /* handle unicore attn? */
3814 }
3815 if (asserted & ATTN_SW_TIMER_4_FUNC)
3816 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3817
3818 if (asserted & GPIO_2_FUNC)
3819 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3820
3821 if (asserted & GPIO_3_FUNC)
3822 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3823
3824 if (asserted & GPIO_4_FUNC)
3825 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3826
3827 if (port == 0) {
3828 if (asserted & ATTN_GENERAL_ATTN_1) {
3829 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3830 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3831 }
3832 if (asserted & ATTN_GENERAL_ATTN_2) {
3833 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3834 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3835 }
3836 if (asserted & ATTN_GENERAL_ATTN_3) {
3837 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3838 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3839 }
3840 } else {
3841 if (asserted & ATTN_GENERAL_ATTN_4) {
3842 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3843 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3844 }
3845 if (asserted & ATTN_GENERAL_ATTN_5) {
3846 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3847 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3848 }
3849 if (asserted & ATTN_GENERAL_ATTN_6) {
3850 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3851 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3852 }
3853 }
3854
3855 } /* if hardwired */
3856
f2e0899f
DK		 3857 if (bp->common.int_block == INT_BLOCK_HC)
3858 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3859 COMMAND_REG_ATTN_BITS_SET);
3860 else
3861 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3862
3863 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3864 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3865 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3866
3867 /* now set back the mask */
a5e9a7cf 3868 if (asserted & ATTN_NIG_FOR_FUNC) {
27c1151c
YR		 3869 /* Verify that IGU ack through BAR was written before restoring
3870 * NIG mask. This loop should exit after 2-3 iterations max.
3871 */
3872 if (bp->common.int_block != INT_BLOCK_HC) {
3873 u32 cnt = 0, igu_acked;
3874 do {
3875 igu_acked = REG_RD(bp,
3876 IGU_REG_ATTENTION_ACK_BITS);
3877 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3878 (++cnt < MAX_IGU_ATTN_ACK_TO));
3879 if (!igu_acked)
3880 DP(NETIF_MSG_HW,
3881 "Failed to verify IGU ack on time\n");
3882 barrier();
3883 }
87942b46 3884 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 3885 bnx2x_release_phy_lock(bp);
3886 }
a2fbb9ea
ET		 3887}
3888
1191cb83 3889static void bnx2x_fan_failure(struct bnx2x *bp)
fd4ef40d
EG		 3890{
3891 int port = BP_PORT(bp);
b7737c9b 3892 u32 ext_phy_config;
fd4ef40d 3893 /* mark the failure */
b7737c9b
YR		 3894 ext_phy_config =
3895 SHMEM_RD(bp,
3896 dev_info.port_hw_config[port].external_phy_config);
3897
3898 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3899 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 3900 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 3901 ext_phy_config);
fd4ef40d
EG		 3902
3903 /* log the failure */
51c1a580
MS		 3904 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3905 "Please contact OEM Support for assistance\n");
8304859a 3906
16a5fd92 3907 /* Schedule device reset (unload)
8304859a
AE		 3908 * This is due to some boards consuming sufficient power when driver is
3909 * up to overheat if fan fails.
3910 */
230bb0f3 3911 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
fd4ef40d 3912}
ab6ad5a4 3913
1191cb83 3914static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 3915{
34f80b04 3916 int port = BP_PORT(bp);
877e9aa4 3917 int reg_offset;
d90d96ba 3918 u32 val;
877e9aa4 3919
34f80b04
EG		 3920 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3921 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 3922
34f80b04 3923 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 3924
3925 val = REG_RD(bp, reg_offset);
3926 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3927 REG_WR(bp, reg_offset, val);
3928
3929 BNX2X_ERR("SPIO5 hw attention\n");
3930
fd4ef40d 3931 /* Fan failure attention */
d90d96ba 3932 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 3933 bnx2x_fan_failure(bp);
877e9aa4 3934 }
34f80b04 3935
3deb8167 3936 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 3937 bnx2x_acquire_phy_lock(bp);
3938 bnx2x_handle_module_detect_int(&bp->link_params);
3939 bnx2x_release_phy_lock(bp);
3940 }
3941
34f80b04
EG		 3942 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3943
3944 val = REG_RD(bp, reg_offset);
3945 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3946 REG_WR(bp, reg_offset, val);
3947
3948 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3949 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3950 bnx2x_panic();
3951 }
877e9aa4
ET		 3952}
3953
1191cb83 3954static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 3955{
3956 u32 val;
3957
0626b899 3958 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3959
3960 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3961 BNX2X_ERR("DB hw attention 0x%x\n", val);
3962 /* DORQ discard attention */
3963 if (val & 0x2)
3964 BNX2X_ERR("FATAL error from DORQ\n");
3965 }
34f80b04
EG		 3966
3967 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3968
3969 int port = BP_PORT(bp);
3970 int reg_offset;
3971
3972 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3973 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3974
3975 val = REG_RD(bp, reg_offset);
3976 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3977 REG_WR(bp, reg_offset, val);
3978
3979 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3980 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3981 bnx2x_panic();
3982 }
877e9aa4
ET		 3983}
3984
1191cb83 3985static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 3986{
3987 u32 val;
3988
3989 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3990
3991 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3992 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3993 /* CFC error attention */
3994 if (val & 0x2)
3995 BNX2X_ERR("FATAL error from CFC\n");
3996 }
3997
3998 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 3999 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 4000 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 4001 /* RQ_USDMDP_FIFO_OVERFLOW */
4002 if (val & 0x18000)
4003 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 4004
4005 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4006 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4007 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4008 }
877e9aa4 4009 }
34f80b04
EG		 4010
4011 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4012
4013 int port = BP_PORT(bp);
4014 int reg_offset;
4015
4016 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4017 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4018
4019 val = REG_RD(bp, reg_offset);
4020 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4021 REG_WR(bp, reg_offset, val);
4022
4023 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 4024 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 4025 bnx2x_panic();
4026 }
877e9aa4
ET		 4027}
4028
1191cb83 4029static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
877e9aa4 4030{
34f80b04
EG		 4031 u32 val;
4032
877e9aa4
ET		 4033 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4034
34f80b04
EG		 4035 if (attn & BNX2X_PMF_LINK_ASSERT) {
4036 int func = BP_FUNC(bp);
4037
4038 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
a3348722 4039 bnx2x_read_mf_cfg(bp);
f2e0899f
DK		 4040 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4041 func_mf_config[BP_ABS_FUNC(bp)].config);
4042 val = SHMEM_RD(bp,
4043 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 4044 if (val & DRV_STATUS_DCC_EVENT_MASK)
4045 bnx2x_dcc_event(bp,
4046 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 4047
4048 if (val & DRV_STATUS_SET_MF_BW)
4049 bnx2x_set_mf_bw(bp);
4050
1d187b34
BW		 4051 if (val & DRV_STATUS_DRV_INFO_REQ)
4052 bnx2x_handle_drv_info_req(bp);
d16132ce
AE		 4053
4054 if (val & DRV_STATUS_VF_DISABLED)
4055 bnx2x_vf_handle_flr_event(bp);
4056
2691d51d 4057 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 4058 bnx2x_pmf_update(bp);
4059
e4901dde 4060 if (bp->port.pmf &&
785b9b1a
SR		 4061 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4062 bp->dcbx_enabled > 0)
e4901dde
VZ		 4063 /* start dcbx state machine */
4064 bnx2x_dcbx_set_params(bp,
4065 BNX2X_DCBX_STATE_NEG_RECEIVED);
a3348722
BW		 4066 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4067 bnx2x_handle_afex_cmd(bp,
4068 val & DRV_STATUS_AFEX_EVENT_MASK);
c8c60d88
YM		 4069 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4070 bnx2x_handle_eee_event(bp);
3deb8167
YR		 4071 if (bp->link_vars.periodic_flags &
4072 PERIODIC_FLAGS_LINK_EVENT) {
4073 /* sync with link */
4074 bnx2x_acquire_phy_lock(bp);
4075 bp->link_vars.periodic_flags &=
4076 ~PERIODIC_FLAGS_LINK_EVENT;
4077 bnx2x_release_phy_lock(bp);
4078 if (IS_MF(bp))
4079 bnx2x_link_sync_notify(bp);
4080 bnx2x_link_report(bp);
4081 }
4082 /* Always call it here: bnx2x_link_report() will
4083 * prevent the link indication duplication.
4084 */
4085 bnx2x__link_status_update(bp);
34f80b04 4086 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 4087
4088 BNX2X_ERR("MC assert!\n");
d6cae238 4089 bnx2x_mc_assert(bp);
877e9aa4
ET		 4090 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4091 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4092 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4093 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4094 bnx2x_panic();
4095
4096 } else if (attn & BNX2X_MCP_ASSERT) {
4097
4098 BNX2X_ERR("MCP assert!\n");
4099 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 4100 bnx2x_fw_dump(bp);
877e9aa4
ET		 4101
4102 } else
4103 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4104 }
4105
4106 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 4107 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4108 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 4109 val = CHIP_IS_E1(bp) ? 0 :
4110 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 4111 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4112 }
4113 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 4114 val = CHIP_IS_E1(bp) ? 0 :
4115 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 4116 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4117 }
877e9aa4 4118 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 4119 }
4120}
4121
c9ee9206
VZ		 4122/*
4123 * Bits map:
4124 * 0-7 - Engine0 load counter.
4125 * 8-15 - Engine1 load counter.
4126 * 16 - Engine0 RESET_IN_PROGRESS bit.
4127 * 17 - Engine1 RESET_IN_PROGRESS bit.
4128 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4129 * on the engine
4130 * 19 - Engine1 ONE_IS_LOADED.
4131 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4132 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4133 * just the one belonging to its engine).
4134 *
4135 */
4136#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4137
4138#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4139#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4140#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4141#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4142#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4143#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4144#define BNX2X_GLOBAL_RESET_BIT 0x00040000
4145
4146/*
4147 * Set the GLOBAL_RESET bit.
4148 *
4149 * Should be run under rtnl lock
4150 */
4151void bnx2x_set_reset_global(struct bnx2x *bp)
4152{
f16da43b
AE		 4153 u32 val;
4154 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4155 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4156 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
f16da43b 4157 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206
VZ		 4158}
4159
4160/*
4161 * Clear the GLOBAL_RESET bit.
4162 *
4163 * Should be run under rtnl lock
4164 */
1191cb83 4165static void bnx2x_clear_reset_global(struct bnx2x *bp)
c9ee9206 4166{
f16da43b
AE		 4167 u32 val;
4168 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4169 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4170 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
f16da43b 4171 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206 4172}
f85582f8 4173
72fd0718 4174/*
c9ee9206
VZ		 4175 * Checks the GLOBAL_RESET bit.
4176 *
72fd0718
VZ		 4177 * should be run under rtnl lock
4178 */
1191cb83 4179static bool bnx2x_reset_is_global(struct bnx2x *bp)
c9ee9206 4180{
3cdeec22 4181 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4182
4183 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4184 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4185}
4186
4187/*
4188 * Clear RESET_IN_PROGRESS bit for the current engine.
4189 *
4190 * Should be run under rtnl lock
4191 */
1191cb83 4192static void bnx2x_set_reset_done(struct bnx2x *bp)
72fd0718 4193{
f16da43b 4194 u32 val;
c9ee9206
VZ		 4195 u32 bit = BP_PATH(bp) ?
4196 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4197 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4198 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4199
4200 /* Clear the bit */
4201 val &= ~bit;
4202 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4203
4204 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4205}
4206
4207/*
c9ee9206
VZ		 4208 * Set RESET_IN_PROGRESS for the current engine.
4209 *
72fd0718
VZ		 4210 * should be run under rtnl lock
4211 */
c9ee9206 4212void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 4213{
f16da43b 4214 u32 val;
c9ee9206
VZ		 4215 u32 bit = BP_PATH(bp) ?
4216 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4217 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4218 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4219
4220 /* Set the bit */
4221 val |= bit;
4222 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4223 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4224}
4225
4226/*
c9ee9206 4227 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 4228 * should be run under rtnl lock
4229 */
c9ee9206 4230bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 4231{
3cdeec22 4232 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4233 u32 bit = engine ?
4234 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4235
4236 /* return false if bit is set */
4237 return (val & bit) ? false : true;
72fd0718
VZ		 4238}
4239
4240/*
889b9af3 4241 * set pf load for the current pf.
c9ee9206 4242 *
72fd0718
VZ		 4243 * should be run under rtnl lock
4244 */
889b9af3 4245void bnx2x_set_pf_load(struct bnx2x *bp)
72fd0718 4246{
f16da43b 4247 u32 val1, val;
c9ee9206
VZ		 4248 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4249 BNX2X_PATH0_LOAD_CNT_MASK;
4250 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4251 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4252
f16da43b
AE		 4253 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4254 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4255
51c1a580 4256 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4257
c9ee9206
VZ		 4258 /* get the current counter value */
4259 val1 = (val & mask) >> shift;
4260
889b9af3
AE		 4261 /* set bit of that PF */
4262 val1 |= (1 << bp->pf_num);
c9ee9206
VZ		 4263
4264 /* clear the old value */
4265 val &= ~mask;
4266
4267 /* set the new one */
4268 val |= ((val1 << shift) & mask);
4269
4270 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4271 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4272}
4273
c9ee9206 4274/**
889b9af3 4275 * bnx2x_clear_pf_load - clear pf load mark
c9ee9206
VZ		 4276 *
4277 * @bp: driver handle
4278 *
4279 * Should be run under rtnl lock.
4280 * Decrements the load counter for the current engine. Returns
889b9af3 4281 * whether other functions are still loaded
72fd0718 4282 */
889b9af3 4283bool bnx2x_clear_pf_load(struct bnx2x *bp)
72fd0718 4284{
f16da43b 4285 u32 val1, val;
c9ee9206
VZ		 4286 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4287 BNX2X_PATH0_LOAD_CNT_MASK;
4288 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4289 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4290
f16da43b
AE		 4291 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4292 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
51c1a580 4293 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4294
c9ee9206
VZ		 4295 /* get the current counter value */
4296 val1 = (val & mask) >> shift;
4297
889b9af3
AE		 4298 /* clear bit of that PF */
4299 val1 &= ~(1 << bp->pf_num);
c9ee9206
VZ		 4300
4301 /* clear the old value */
4302 val &= ~mask;
4303
4304 /* set the new one */
4305 val |= ((val1 << shift) & mask);
4306
4307 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4308 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4309 return val1 != 0;
72fd0718
VZ		 4310}
4311
4312/*
889b9af3 4313 * Read the load status for the current engine.
c9ee9206 4314 *
72fd0718
VZ		 4315 * should be run under rtnl lock
4316 */
1191cb83 4317static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
72fd0718 4318{
c9ee9206
VZ		 4319 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4320 BNX2X_PATH0_LOAD_CNT_MASK);
4321 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4322 BNX2X_PATH0_LOAD_CNT_SHIFT);
4323 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4324
51c1a580 4325 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
c9ee9206
VZ		 4326
4327 val = (val & mask) >> shift;
4328
51c1a580
MS		 4329 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4330 engine, val);
c9ee9206 4331
889b9af3 4332 return val != 0;
72fd0718
VZ		 4333}
4334
6bf07b8e
YM		 4335static void _print_parity(struct bnx2x *bp, u32 reg)
4336{
4337 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4338}
4339
1191cb83 4340static void _print_next_block(int idx, const char *blk)
72fd0718 4341{
f1deab50 4342 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 4343}
4344
4293b9f5
DK		 4345static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4346 int *par_num, bool print)
72fd0718 4347{
4293b9f5
DK		 4348 u32 cur_bit;
4349 bool res;
4350 int i;
4351
4352 res = false;
4353
72fd0718 4354 for (i = 0; sig; i++) {
4293b9f5 4355 cur_bit = (0x1UL << i);
72fd0718 4356 if (sig & cur_bit) {
4293b9f5
DK		 4357 res |= true; /* Each bit is real error! */
4358
4359 if (print) {
4360 switch (cur_bit) {
4361 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4362 _print_next_block((*par_num)++, "BRB");
6bf07b8e
YM		 4363 _print_parity(bp,
4364 BRB1_REG_BRB1_PRTY_STS);
4293b9f5
DK		 4365 break;
4366 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4367 _print_next_block((*par_num)++,
4368 "PARSER");
6bf07b8e 4369 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4293b9f5
DK		 4370 break;
4371 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4372 _print_next_block((*par_num)++, "TSDM");
6bf07b8e
YM		 4373 _print_parity(bp,
4374 TSDM_REG_TSDM_PRTY_STS);
4293b9f5
DK		 4375 break;
4376 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4377 _print_next_block((*par_num)++,
c9ee9206 4378 "SEARCHER");
6bf07b8e 4379 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4293b9f5
DK		 4380 break;
4381 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4382 _print_next_block((*par_num)++, "TCM");
4383 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4384 break;
4385 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4386 _print_next_block((*par_num)++,
4387 "TSEMI");
6bf07b8e
YM		 4388 _print_parity(bp,
4389 TSEM_REG_TSEM_PRTY_STS_0);
4390 _print_parity(bp,
4391 TSEM_REG_TSEM_PRTY_STS_1);
4293b9f5
DK		 4392 break;
4393 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4394 _print_next_block((*par_num)++, "XPB");
6bf07b8e
YM		 4395 _print_parity(bp, GRCBASE_XPB +
4396 PB_REG_PB_PRTY_STS);
4293b9f5 4397 break;
6bf07b8e 4398 }
72fd0718
VZ		 4399 }
4400
4401 /* Clear the bit */
4402 sig &= ~cur_bit;
4403 }
4404 }
4405
4293b9f5 4406 return res;
72fd0718
VZ		 4407}
4408
4293b9f5
DK		 4409static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4410 int *par_num, bool *global,
6bf07b8e 4411 bool print)
72fd0718 4412{
4293b9f5
DK		 4413 u32 cur_bit;
4414 bool res;
4415 int i;
4416
4417 res = false;
4418
72fd0718 4419 for (i = 0; sig; i++) {
4293b9f5 4420 cur_bit = (0x1UL << i);
72fd0718 4421 if (sig & cur_bit) {
4293b9f5 4422 res |= true; /* Each bit is real error! */
72fd0718 4423 switch (cur_bit) {
c9ee9206 4424 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
6bf07b8e 4425 if (print) {
4293b9f5 4426 _print_next_block((*par_num)++, "PBF");
6bf07b8e
YM		 4427 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4428 }
72fd0718
VZ		 4429 break;
4430 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
6bf07b8e 4431 if (print) {
4293b9f5 4432 _print_next_block((*par_num)++, "QM");
6bf07b8e
YM		 4433 _print_parity(bp, QM_REG_QM_PRTY_STS);
4434 }
c9ee9206
VZ		 4435 break;
4436 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
6bf07b8e 4437 if (print) {
4293b9f5 4438 _print_next_block((*par_num)++, "TM");
6bf07b8e
YM		 4439 _print_parity(bp, TM_REG_TM_PRTY_STS);
4440 }
72fd0718
VZ		 4441 break;
4442 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
6bf07b8e 4443 if (print) {
4293b9f5 4444 _print_next_block((*par_num)++, "XSDM");
6bf07b8e
YM		 4445 _print_parity(bp,
4446 XSDM_REG_XSDM_PRTY_STS);
4447 }
c9ee9206
VZ		 4448 break;
4449 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
6bf07b8e 4450 if (print) {
4293b9f5 4451 _print_next_block((*par_num)++, "XCM");
6bf07b8e
YM		 4452 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4453 }
72fd0718
VZ		 4454 break;
4455 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
6bf07b8e 4456 if (print) {
4293b9f5
DK		 4457 _print_next_block((*par_num)++,
4458 "XSEMI");
6bf07b8e
YM		 4459 _print_parity(bp,
4460 XSEM_REG_XSEM_PRTY_STS_0);
4461 _print_parity(bp,
4462 XSEM_REG_XSEM_PRTY_STS_1);
4463 }
72fd0718
VZ		 4464 break;
4465 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
6bf07b8e 4466 if (print) {
4293b9f5 4467 _print_next_block((*par_num)++,
c9ee9206 4468 "DOORBELLQ");
6bf07b8e
YM		 4469 _print_parity(bp,
4470 DORQ_REG_DORQ_PRTY_STS);
4471 }
c9ee9206
VZ		 4472 break;
4473 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
6bf07b8e 4474 if (print) {
4293b9f5 4475 _print_next_block((*par_num)++, "NIG");
6bf07b8e
YM		 4476 if (CHIP_IS_E1x(bp)) {
4477 _print_parity(bp,
4478 NIG_REG_NIG_PRTY_STS);
4479 } else {
4480 _print_parity(bp,
4481 NIG_REG_NIG_PRTY_STS_0);
4482 _print_parity(bp,
4483 NIG_REG_NIG_PRTY_STS_1);
4484 }
4485 }
72fd0718
VZ		 4486 break;
4487 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206 4488 if (print)
4293b9f5 4489 _print_next_block((*par_num)++,
c9ee9206
VZ		 4490 "VAUX PCI CORE");
4491 *global = true;
72fd0718
VZ		 4492 break;
4493 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
6bf07b8e 4494 if (print) {
4293b9f5
DK		 4495 _print_next_block((*par_num)++,
4496 "DEBUG");
6bf07b8e
YM		 4497 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4498 }
72fd0718
VZ		 4499 break;
4500 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
6bf07b8e 4501 if (print) {
4293b9f5 4502 _print_next_block((*par_num)++, "USDM");
6bf07b8e
YM		 4503 _print_parity(bp,
4504 USDM_REG_USDM_PRTY_STS);
4505 }
72fd0718 4506 break;
8736c826 4507 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
6bf07b8e 4508 if (print) {
4293b9f5 4509 _print_next_block((*par_num)++, "UCM");
6bf07b8e
YM		 4510 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4511 }
8736c826 4512 break;
72fd0718 4513 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
6bf07b8e 4514 if (print) {
4293b9f5
DK		 4515 _print_next_block((*par_num)++,
4516 "USEMI");
6bf07b8e
YM		 4517 _print_parity(bp,
4518 USEM_REG_USEM_PRTY_STS_0);
4519 _print_parity(bp,
4520 USEM_REG_USEM_PRTY_STS_1);
4521 }
72fd0718
VZ		 4522 break;
4523 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
6bf07b8e 4524 if (print) {
4293b9f5 4525 _print_next_block((*par_num)++, "UPB");
6bf07b8e
YM		 4526 _print_parity(bp, GRCBASE_UPB +
4527 PB_REG_PB_PRTY_STS);
4528 }
72fd0718
VZ		 4529 break;
4530 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
6bf07b8e 4531 if (print) {
4293b9f5 4532 _print_next_block((*par_num)++, "CSDM");
6bf07b8e
YM		 4533 _print_parity(bp,
4534 CSDM_REG_CSDM_PRTY_STS);
4535 }
72fd0718 4536 break;
8736c826 4537 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
6bf07b8e 4538 if (print) {
4293b9f5 4539 _print_next_block((*par_num)++, "CCM");
6bf07b8e
YM		 4540 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4541 }
8736c826 4542 break;
72fd0718
VZ		 4543 }
4544
4545 /* Clear the bit */
4546 sig &= ~cur_bit;
4547 }
4548 }
4549
4293b9f5 4550 return res;
72fd0718
VZ		 4551}
4552
4293b9f5
DK		 4553static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4554 int *par_num, bool print)
72fd0718 4555{
4293b9f5
DK		 4556 u32 cur_bit;
4557 bool res;
4558 int i;
4559
4560 res = false;
4561
72fd0718 4562 for (i = 0; sig; i++) {
4293b9f5 4563 cur_bit = (0x1UL << i);
72fd0718 4564 if (sig & cur_bit) {
4293b9f5
DK		 4565 res |= true; /* Each bit is real error! */
4566 if (print) {
4567 switch (cur_bit) {
4568 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4569 _print_next_block((*par_num)++,
4570 "CSEMI");
6bf07b8e
YM		 4571 _print_parity(bp,
4572 CSEM_REG_CSEM_PRTY_STS_0);
4573 _print_parity(bp,
4574 CSEM_REG_CSEM_PRTY_STS_1);
4293b9f5
DK		 4575 break;
4576 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4577 _print_next_block((*par_num)++, "PXP");
6bf07b8e
YM		 4578 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4579 _print_parity(bp,
4580 PXP2_REG_PXP2_PRTY_STS_0);
4581 _print_parity(bp,
4582 PXP2_REG_PXP2_PRTY_STS_1);
4293b9f5
DK		 4583 break;
4584 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4585 _print_next_block((*par_num)++,
4586 "PXPPCICLOCKCLIENT");
4587 break;
4588 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4589 _print_next_block((*par_num)++, "CFC");
6bf07b8e
YM		 4590 _print_parity(bp,
4591 CFC_REG_CFC_PRTY_STS);
4293b9f5
DK		 4592 break;
4593 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4594 _print_next_block((*par_num)++, "CDU");
6bf07b8e 4595 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4293b9f5
DK		 4596 break;
4597 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4598 _print_next_block((*par_num)++, "DMAE");
6bf07b8e
YM		 4599 _print_parity(bp,
4600 DMAE_REG_DMAE_PRTY_STS);
4293b9f5
DK		 4601 break;
4602 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4603 _print_next_block((*par_num)++, "IGU");
6bf07b8e
YM		 4604 if (CHIP_IS_E1x(bp))
4605 _print_parity(bp,
4606 HC_REG_HC_PRTY_STS);
4607 else
4608 _print_parity(bp,
4609 IGU_REG_IGU_PRTY_STS);
4293b9f5
DK		 4610 break;
4611 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4612 _print_next_block((*par_num)++, "MISC");
6bf07b8e
YM		 4613 _print_parity(bp,
4614 MISC_REG_MISC_PRTY_STS);
4293b9f5 4615 break;
6bf07b8e 4616 }
72fd0718
VZ		 4617 }
4618
4619 /* Clear the bit */
4620 sig &= ~cur_bit;
4621 }
4622 }
4623
4293b9f5 4624 return res;
72fd0718
VZ		 4625}
4626
4293b9f5
DK		 4627static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4628 int *par_num, bool *global,
4629 bool print)
72fd0718 4630{
4293b9f5
DK		 4631 bool res = false;
4632 u32 cur_bit;
4633 int i;
4634
72fd0718 4635 for (i = 0; sig; i++) {
4293b9f5 4636 cur_bit = (0x1UL << i);
72fd0718
VZ		 4637 if (sig & cur_bit) {
4638 switch (cur_bit) {
4639 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206 4640 if (print)
4293b9f5
DK		 4641 _print_next_block((*par_num)++,
4642 "MCP ROM");
c9ee9206 4643 *global = true;
4293b9f5 4644 res |= true;
72fd0718
VZ		 4645 break;
4646 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206 4647 if (print)
4293b9f5 4648 _print_next_block((*par_num)++,
c9ee9206
VZ		 4649 "MCP UMP RX");
4650 *global = true;
4293b9f5 4651 res |= true;
72fd0718
VZ		 4652 break;
4653 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206 4654 if (print)
4293b9f5 4655 _print_next_block((*par_num)++,
c9ee9206
VZ		 4656 "MCP UMP TX");
4657 *global = true;
4293b9f5 4658 res |= true;
72fd0718
VZ		 4659 break;
4660 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206 4661 if (print)
4293b9f5 4662 _print_next_block((*par_num)++,
c9ee9206 4663 "MCP SCPAD");
4293b9f5
DK		 4664 /* clear latched SCPAD PATIRY from MCP */
4665 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4666 1UL << 10);
72fd0718
VZ		 4667 break;
4668 }
4669
4670 /* Clear the bit */
4671 sig &= ~cur_bit;
4672 }
4673 }
4674
4293b9f5 4675 return res;
72fd0718
VZ		 4676}
4677
4293b9f5
DK		 4678static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4679 int *par_num, bool print)
8736c826 4680{
4293b9f5
DK		 4681 u32 cur_bit;
4682 bool res;
4683 int i;
4684
4685 res = false;
4686
8736c826 4687 for (i = 0; sig; i++) {
4293b9f5 4688 cur_bit = (0x1UL << i);
8736c826 4689 if (sig & cur_bit) {
4293b9f5
DK		 4690 res |= true; /* Each bit is real error! */
4691 if (print) {
4692 switch (cur_bit) {
4693 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4694 _print_next_block((*par_num)++,
4695 "PGLUE_B");
6bf07b8e 4696 _print_parity(bp,
4293b9f5
DK		 4697 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4698 break;
4699 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4700 _print_next_block((*par_num)++, "ATC");
6bf07b8e
YM		 4701 _print_parity(bp,
4702 ATC_REG_ATC_PRTY_STS);
4293b9f5 4703 break;
6bf07b8e 4704 }
8736c826 4705 }
8736c826
VZ		 4706 /* Clear the bit */
4707 sig &= ~cur_bit;
4708 }
4709 }
4710
4293b9f5 4711 return res;
8736c826
VZ		 4712}
4713
1191cb83
ED		 4714static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4715 u32 *sig)
72fd0718 4716{
4293b9f5
DK		 4717 bool res = false;
4718
8736c826
VZ		 4719 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4720 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4721 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4722 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4723 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718 4724 int par_num = 0;
51c1a580
MS		 4725 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4726 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
8736c826
VZ		 4727 sig[0] & HW_PRTY_ASSERT_SET_0,
4728 sig[1] & HW_PRTY_ASSERT_SET_1,
4729 sig[2] & HW_PRTY_ASSERT_SET_2,
4730 sig[3] & HW_PRTY_ASSERT_SET_3,
4731 sig[4] & HW_PRTY_ASSERT_SET_4);
c9ee9206
VZ		 4732 if (print)
4733 netdev_err(bp->dev,
4734 "Parity errors detected in blocks: ");
4293b9f5
DK		 4735 res |= bnx2x_check_blocks_with_parity0(bp,
4736 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4737 res |= bnx2x_check_blocks_with_parity1(bp,
4738 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4739 res |= bnx2x_check_blocks_with_parity2(bp,
4740 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4741 res |= bnx2x_check_blocks_with_parity3(bp,
4742 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4743 res |= bnx2x_check_blocks_with_parity4(bp,
4744 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
8736c826 4745
c9ee9206
VZ		 4746 if (print)
4747 pr_cont("\n");
4293b9f5 4748 }
8736c826 4749
4293b9f5 4750 return res;
72fd0718
VZ		 4751}
4752
c9ee9206
VZ		 4753/**
4754 * bnx2x_chk_parity_attn - checks for parity attentions.
4755 *
4756 * @bp: driver handle
4757 * @global: true if there was a global attention
4758 * @print: show parity attention in syslog
4759 */
4760bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 4761{
8736c826 4762 struct attn_route attn = { {0} };
72fd0718
VZ		 4763 int port = BP_PORT(bp);
4764
4765 attn.sig[0] = REG_RD(bp,
4766 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4767 port*4);
4768 attn.sig[1] = REG_RD(bp,
4769 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4770 port*4);
4771 attn.sig[2] = REG_RD(bp,
4772 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4773 port*4);
4774 attn.sig[3] = REG_RD(bp,
4775 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4776 port*4);
0a5ccb75
YM		 4777 /* Since MCP attentions can't be disabled inside the block, we need to
4778 * read AEU registers to see whether they're currently disabled
4779 */
4780 attn.sig[3] &= ((REG_RD(bp,
4781 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4782 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4783 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4784 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
72fd0718 4785
8736c826
VZ		 4786 if (!CHIP_IS_E1x(bp))
4787 attn.sig[4] = REG_RD(bp,
4788 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4789 port*4);
4790
4791 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 4792}
4793
1191cb83 4794static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
f2e0899f
DK		 4795{
4796 u32 val;
4797 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4798
4799 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4800 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4801 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
51c1a580 4802 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
f2e0899f 4803 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
51c1a580 4804 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
f2e0899f 4805 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
51c1a580 4806 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
f2e0899f 4807 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
51c1a580 4808 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
f2e0899f
DK		 4809 if (val &
4810 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
51c1a580 4811 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
f2e0899f
DK		 4812 if (val &
4813 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
51c1a580 4814 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
f2e0899f 4815 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
51c1a580 4816 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
f2e0899f 4817 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
51c1a580 4818 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
f2e0899f 4819 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
51c1a580 4820 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
f2e0899f
DK		 4821 }
4822 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4823 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4824 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4825 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4826 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4827 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
51c1a580 4828 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
f2e0899f 4829 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
51c1a580 4830 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
f2e0899f 4831 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
51c1a580 4832 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
f2e0899f
DK		 4833 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4834 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4835 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
51c1a580 4836 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
f2e0899f
DK		 4837 }
4838
4839 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4840 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4841 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4842 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4843 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4844 }
f2e0899f
DK		 4845}
4846
72fd0718
VZ		 4847static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4848{
4849 struct attn_route attn, *group_mask;
34f80b04 4850 int port = BP_PORT(bp);
877e9aa4 4851 int index;
a2fbb9ea
ET		 4852 u32 reg_addr;
4853 u32 val;
3fcaf2e5 4854 u32 aeu_mask;
c9ee9206 4855 bool global = false;
a2fbb9ea
ET		 4856
4857 /* need to take HW lock because MCP or other port might also
4858 try to handle this event */
4a37fb66 4859 bnx2x_acquire_alr(bp);
a2fbb9ea 4860
c9ee9206
VZ		 4861 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4862#ifndef BNX2X_STOP_ON_ERROR
72fd0718 4863 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 4864 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 4865 /* Disable HW interrupts */
4866 bnx2x_int_disable(bp);
72fd0718
VZ		 4867 /* In case of parity errors don't handle attentions so that
4868 * other function would "see" parity errors.
4869 */
c9ee9206
VZ		 4870#else
4871 bnx2x_panic();
4872#endif
4873 bnx2x_release_alr(bp);
72fd0718
VZ		 4874 return;
4875 }
4876
a2fbb9ea
ET		 4877 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4878 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4879 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4880 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 4881 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4882 attn.sig[4] =
4883 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4884 else
4885 attn.sig[4] = 0;
4886
4887 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4888 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 4889
4890 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4891 if (deasserted & (1 << index)) {
72fd0718 4892 group_mask = &bp->attn_group[index];
a2fbb9ea 4893
51c1a580 4894 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
f2e0899f
DK		 4895 index,
4896 group_mask->sig[0], group_mask->sig[1],
4897 group_mask->sig[2], group_mask->sig[3],
4898 group_mask->sig[4]);
a2fbb9ea 4899
f2e0899f
DK		 4900 bnx2x_attn_int_deasserted4(bp,
4901 attn.sig[4] & group_mask->sig[4]);
877e9aa4 4902 bnx2x_attn_int_deasserted3(bp,
72fd0718 4903 attn.sig[3] & group_mask->sig[3]);
877e9aa4 4904 bnx2x_attn_int_deasserted1(bp,
72fd0718 4905 attn.sig[1] & group_mask->sig[1]);
877e9aa4 4906 bnx2x_attn_int_deasserted2(bp,
72fd0718 4907 attn.sig[2] & group_mask->sig[2]);
877e9aa4 4908 bnx2x_attn_int_deasserted0(bp,
72fd0718 4909 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 4910 }
4911 }
4912
4a37fb66 4913 bnx2x_release_alr(bp);
a2fbb9ea 4914
f2e0899f
DK		 4915 if (bp->common.int_block == INT_BLOCK_HC)
4916 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4917 COMMAND_REG_ATTN_BITS_CLR);
4918 else
4919 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 4920
4921 val = ~deasserted;
f2e0899f
DK		 4922 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4923 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 4924 REG_WR(bp, reg_addr, val);
a2fbb9ea 4925
a2fbb9ea 4926 if (~bp->attn_state & deasserted)
3fcaf2e5 4927 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 4928
4929 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4930 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4931
3fcaf2e5
EG		 4932 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4933 aeu_mask = REG_RD(bp, reg_addr);
4934
4935 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4936 aeu_mask, deasserted);
72fd0718 4937 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 4938 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 4939
3fcaf2e5
EG		 4940 REG_WR(bp, reg_addr, aeu_mask);
4941 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 4942
4943 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4944 bp->attn_state &= ~deasserted;
4945 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4946}
4947
4948static void bnx2x_attn_int(struct bnx2x *bp)
4949{
4950 /* read local copy of bits */
68d59484
EG		 4951 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4952 attn_bits);
4953 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4954 attn_bits_ack);
a2fbb9ea
ET		 4955 u32 attn_state = bp->attn_state;
4956
4957 /* look for changed bits */
4958 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4959 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4960
4961 DP(NETIF_MSG_HW,
4962 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4963 attn_bits, attn_ack, asserted, deasserted);
4964
4965 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 4966 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 4967
4968 /* handle bits that were raised */
4969 if (asserted)
4970 bnx2x_attn_int_asserted(bp, asserted);
4971
4972 if (deasserted)
4973 bnx2x_attn_int_deasserted(bp, deasserted);
4974}
4975
619c5cb6
VZ		 4976void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4977 u16 index, u8 op, u8 update)
4978{
dc1ba591
AE		 4979 u32 igu_addr = bp->igu_base_addr;
4980 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
619c5cb6
VZ		 4981 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4982 igu_addr);
4983}
4984
1191cb83 4985static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
523224a3
DK		 4986{
4987 /* No memory barriers */
4988 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4989 mmiowb(); /* keep prod updates ordered */
4990}
4991
523224a3
DK		 4992static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4993 union event_ring_elem *elem)
4994{
619c5cb6
VZ		 4995 u8 err = elem->message.error;
4996
523224a3 4997 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 4998 (cid < bp->cnic_eth_dev.starting_cid &&
4999 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 5000 return 1;
5001
5002 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5003
619c5cb6
VZ		 5004 if (unlikely(err)) {
5005
523224a3
DK		 5006 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5007 cid);
823e1d90 5008 bnx2x_panic_dump(bp, false);
523224a3 5009 }
619c5cb6 5010 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 5011 return 0;
5012}
523224a3 5013
1191cb83 5014static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5015{
5016 struct bnx2x_mcast_ramrod_params rparam;
5017 int rc;
5018
5019 memset(&rparam, 0, sizeof(rparam));
5020
5021 rparam.mcast_obj = &bp->mcast_obj;
5022
5023 netif_addr_lock_bh(bp->dev);
5024
5025 /* Clear pending state for the last command */
5026 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5027
5028 /* If there are pending mcast commands - send them */
5029 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5030 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5031 if (rc < 0)
5032 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5033 rc);
5034 }
5035
5036 netif_addr_unlock_bh(bp->dev);
5037}
5038
1191cb83
ED		 5039static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5040 union event_ring_elem *elem)
619c5cb6
VZ		 5041{
5042 unsigned long ramrod_flags = 0;
5043 int rc = 0;
5044 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5045 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5046
5047 /* Always push next commands out, don't wait here */
5048 __set_bit(RAMROD_CONT, &ramrod_flags);
5049
86564c3f
YM		 5050 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5051 >> BNX2X_SWCID_SHIFT) {
619c5cb6 5052 case BNX2X_FILTER_MAC_PENDING:
51c1a580 5053 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
55c11941 5054 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
619c5cb6
VZ		 5055 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5056 else
15192a8c 5057 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
619c5cb6
VZ		 5058
5059 break;
619c5cb6 5060 case BNX2X_FILTER_MCAST_PENDING:
51c1a580 5061 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
619c5cb6
VZ		 5062 /* This is only relevant for 57710 where multicast MACs are
5063 * configured as unicast MACs using the same ramrod.
5064 */
5065 bnx2x_handle_mcast_eqe(bp);
5066 return;
5067 default:
5068 BNX2X_ERR("Unsupported classification command: %d\n",
5069 elem->message.data.eth_event.echo);
5070 return;
5071 }
5072
5073 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5074
5075 if (rc < 0)
5076 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5077 else if (rc > 0)
5078 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
619c5cb6
VZ		 5079}
5080
619c5cb6 5081static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
619c5cb6 5082
1191cb83 5083static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5084{
5085 netif_addr_lock_bh(bp->dev);
5086
5087 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5088
5089 /* Send rx_mode command again if was requested */
5090 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5091 bnx2x_set_storm_rx_mode(bp);
619c5cb6
VZ		 5092 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5093 &bp->sp_state))
5094 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5095 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5096 &bp->sp_state))
5097 bnx2x_set_iscsi_eth_rx_mode(bp, false);
619c5cb6
VZ		 5098
5099 netif_addr_unlock_bh(bp->dev);
5100}
5101
1191cb83 5102static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
a3348722
BW		 5103 union event_ring_elem *elem)
5104{
5105 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5106 DP(BNX2X_MSG_SP,
5107 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5108 elem->message.data.vif_list_event.func_bit_map);
5109 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5110 elem->message.data.vif_list_event.func_bit_map);
5111 } else if (elem->message.data.vif_list_event.echo ==
5112 VIF_LIST_RULE_SET) {
5113 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5114 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5115 }
5116}
5117
5118/* called with rtnl_lock */
1191cb83 5119static void bnx2x_after_function_update(struct bnx2x *bp)
a3348722
BW		 5120{
5121 int q, rc;
5122 struct bnx2x_fastpath *fp;
5123 struct bnx2x_queue_state_params queue_params = {NULL};
5124 struct bnx2x_queue_update_params *q_update_params =
5125 &queue_params.params.update;
5126
2de67439 5127 /* Send Q update command with afex vlan removal values for all Qs */
a3348722
BW		 5128 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5129
5130 /* set silent vlan removal values according to vlan mode */
5131 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5132 &q_update_params->update_flags);
5133 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5134 &q_update_params->update_flags);
5135 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5136
5137 /* in access mode mark mask and value are 0 to strip all vlans */
5138 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5139 q_update_params->silent_removal_value = 0;
5140 q_update_params->silent_removal_mask = 0;
5141 } else {
5142 q_update_params->silent_removal_value =
5143 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5144 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5145 }
5146
5147 for_each_eth_queue(bp, q) {
5148 /* Set the appropriate Queue object */
5149 fp = &bp->fp[q];
15192a8c 5150 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5151
5152 /* send the ramrod */
5153 rc = bnx2x_queue_state_change(bp, &queue_params);
5154 if (rc < 0)
5155 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5156 q);
5157 }
5158
fea75645 5159 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
65565884 5160 fp = &bp->fp[FCOE_IDX(bp)];
15192a8c 5161 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5162
5163 /* clear pending completion bit */
5164 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5165
5166 /* mark latest Q bit */
5167 smp_mb__before_clear_bit();
5168 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5169 smp_mb__after_clear_bit();
5170
5171 /* send Q update ramrod for FCoE Q */
5172 rc = bnx2x_queue_state_change(bp, &queue_params);
5173 if (rc < 0)
5174 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5175 q);
5176 } else {
5177 /* If no FCoE ring - ACK MCP now */
5178 bnx2x_link_report(bp);
5179 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5180 }
a3348722
BW		 5181}
5182
1191cb83 5183static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
619c5cb6
VZ		 5184 struct bnx2x *bp, u32 cid)
5185{
94f05b0f 5186 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
55c11941
MS		 5187
5188 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
15192a8c 5189 return &bnx2x_fcoe_sp_obj(bp, q_obj);
619c5cb6 5190 else
15192a8c 5191 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
619c5cb6
VZ		 5192}
5193
523224a3
DK		 5194static void bnx2x_eq_int(struct bnx2x *bp)
5195{
5196 u16 hw_cons, sw_cons, sw_prod;
5197 union event_ring_elem *elem;
55c11941 5198 u8 echo;
523224a3
DK		 5199 u32 cid;
5200 u8 opcode;
fd1fc79d 5201 int rc, spqe_cnt = 0;
619c5cb6
VZ		 5202 struct bnx2x_queue_sp_obj *q_obj;
5203 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5204 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 5205
5206 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5207
5208 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
16a5fd92 5209 * when we get the next-page we need to adjust so the loop
523224a3
DK		 5210 * condition below will be met. The next element is the size of a
5211 * regular element and hence incrementing by 1
5212 */
5213 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5214 hw_cons++;
5215
25985edc 5216 /* This function may never run in parallel with itself for a
523224a3
DK		 5217 * specific bp, thus there is no need in "paired" read memory
5218 * barrier here.
5219 */
5220 sw_cons = bp->eq_cons;
5221 sw_prod = bp->eq_prod;
5222
d6cae238 5223 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 5224 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 5225
5226 for (; sw_cons != hw_cons;
5227 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5228
523224a3
DK		 5229 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5230
fd1fc79d
AE		 5231 rc = bnx2x_iov_eq_sp_event(bp, elem);
5232 if (!rc) {
5233 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5234 rc);
5235 goto next_spqe;
5236 }
523224a3 5237
86564c3f
YM		 5238 /* elem CID originates from FW; actually LE */
5239 cid = SW_CID((__force __le32)
5240 elem->message.data.cfc_del_event.cid);
5241 opcode = elem->message.opcode;
523224a3
DK		 5242
5243 /* handle eq element */
5244 switch (opcode) {
fd1fc79d
AE		 5245 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5246 DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5247 bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5248 continue;
5249
523224a3 5250 case EVENT_RING_OPCODE_STAT_QUERY:
76ca70fa
YM		 5251 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5252 "got statistics comp event %d\n",
5253 bp->stats_comp++);
523224a3 5254 /* nothing to do with stats comp */
d6cae238 5255 goto next_spqe;
523224a3
DK		 5256
5257 case EVENT_RING_OPCODE_CFC_DEL:
5258 /* handle according to cid range */
5259 /*
5260 * we may want to verify here that the bp state is
5261 * HALTING
5262 */
d6cae238 5263 DP(BNX2X_MSG_SP,
523224a3 5264 "got delete ramrod for MULTI[%d]\n", cid);
55c11941
MS		 5265
5266 if (CNIC_LOADED(bp) &&
5267 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
523224a3 5268 goto next_spqe;
55c11941 5269
619c5cb6
VZ		 5270 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5271
5272 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5273 break;
5274
523224a3 5275 goto next_spqe;
e4901dde
VZ		 5276
5277 case EVENT_RING_OPCODE_STOP_TRAFFIC:
51c1a580 5278 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
6ffa39f2 5279 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
6debea87
DK		 5280 if (f_obj->complete_cmd(bp, f_obj,
5281 BNX2X_F_CMD_TX_STOP))
5282 break;
e4901dde 5283 goto next_spqe;
619c5cb6 5284
e4901dde 5285 case EVENT_RING_OPCODE_START_TRAFFIC:
51c1a580 5286 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
6ffa39f2 5287 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
6debea87
DK		 5288 if (f_obj->complete_cmd(bp, f_obj,
5289 BNX2X_F_CMD_TX_START))
5290 break;
e4901dde 5291 goto next_spqe;
55c11941 5292
a3348722 5293 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
55c11941
MS		 5294 echo = elem->message.data.function_update_event.echo;
5295 if (echo == SWITCH_UPDATE) {
5296 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5297 "got FUNC_SWITCH_UPDATE ramrod\n");
5298 if (f_obj->complete_cmd(
5299 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5300 break;
a3348722 5301
55c11941 5302 } else {
230bb0f3
YM		 5303 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5304
55c11941
MS		 5305 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5306 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5307 f_obj->complete_cmd(bp, f_obj,
5308 BNX2X_F_CMD_AFEX_UPDATE);
5309
5310 /* We will perform the Queues update from
5311 * sp_rtnl task as all Queue SP operations
5312 * should run under rtnl_lock.
5313 */
230bb0f3 5314 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
55c11941 5315 }
a3348722 5316
a3348722
BW		 5317 goto next_spqe;
5318
5319 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5320 f_obj->complete_cmd(bp, f_obj,
5321 BNX2X_F_CMD_AFEX_VIFLISTS);
5322 bnx2x_after_afex_vif_lists(bp, elem);
5323 goto next_spqe;
619c5cb6 5324 case EVENT_RING_OPCODE_FUNCTION_START:
51c1a580
MS		 5325 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5326 "got FUNC_START ramrod\n");
619c5cb6
VZ		 5327 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5328 break;
5329
5330 goto next_spqe;
5331
5332 case EVENT_RING_OPCODE_FUNCTION_STOP:
51c1a580
MS		 5333 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5334 "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 5335 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5336 break;
5337
5338 goto next_spqe;
523224a3
DK		 5339 }
5340
5341 switch (opcode | bp->state) {
619c5cb6
VZ		 5342 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5343 BNX2X_STATE_OPEN):
5344 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 5345 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 5346 cid = elem->message.data.eth_event.echo &
5347 BNX2X_SWCID_MASK;
d6cae238 5348 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
619c5cb6
VZ		 5349 cid);
5350 rss_raw->clear_pending(rss_raw);
523224a3
DK		 5351 break;
5352
619c5cb6
VZ		 5353 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5354 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5355 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 5356 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 5357 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5358 BNX2X_STATE_OPEN):
5359 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5360 BNX2X_STATE_DIAG):
5361 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5362 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5363 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
619c5cb6 5364 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 5365 break;
5366
619c5cb6
VZ		 5367 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5368 BNX2X_STATE_OPEN):
5369 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5370 BNX2X_STATE_DIAG):
5371 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5372 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5373 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 5374 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 5375 break;
5376
619c5cb6
VZ		 5377 case (EVENT_RING_OPCODE_FILTERS_RULES |
5378 BNX2X_STATE_OPEN):
5379 case (EVENT_RING_OPCODE_FILTERS_RULES |
5380 BNX2X_STATE_DIAG):
5381 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 5382 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5383 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 5384 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 5385 break;
5386 default:
5387 /* unknown event log error and continue */
619c5cb6
VZ		 5388 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5389 elem->message.opcode, bp->state);
523224a3
DK		 5390 }
5391next_spqe:
5392 spqe_cnt++;
5393 } /* for */
5394
8fe23fbd 5395 smp_mb__before_atomic_inc();
6e30dd4e 5396 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 5397
5398 bp->eq_cons = sw_cons;
5399 bp->eq_prod = sw_prod;
5400 /* Make sure that above mem writes were issued towards the memory */
5401 smp_wmb();
5402
5403 /* update producer */
5404 bnx2x_update_eq_prod(bp, bp->eq_prod);
5405}
5406
a2fbb9ea
ET		 5407static void bnx2x_sp_task(struct work_struct *work)
5408{
1cf167f2 5409 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea 5410
fd1fc79d 5411 DP(BNX2X_MSG_SP, "sp task invoked\n");
a2fbb9ea 5412
16a5fd92 5413 /* make sure the atomic interrupt_occurred has been written */
fd1fc79d
AE		 5414 smp_rmb();
5415 if (atomic_read(&bp->interrupt_occurred)) {
a2fbb9ea 5416
fd1fc79d
AE		 5417 /* what work needs to be performed? */
5418 u16 status = bnx2x_update_dsb_idx(bp);
cdaa7cb8 5419
fd1fc79d
AE		 5420 DP(BNX2X_MSG_SP, "status %x\n", status);
5421 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5422 atomic_set(&bp->interrupt_occurred, 0);
5423
5424 /* HW attentions */
5425 if (status & BNX2X_DEF_SB_ATT_IDX) {
5426 bnx2x_attn_int(bp);
5427 status &= ~BNX2X_DEF_SB_ATT_IDX;
5428 }
5429
5430 /* SP events: STAT_QUERY and others */
5431 if (status & BNX2X_DEF_SB_IDX) {
5432 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 5433
55c11941 5434 if (FCOE_INIT(bp) &&
fd1fc79d
AE		 5435 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5436 /* Prevent local bottom-halves from running as
5437 * we are going to change the local NAPI list.
5438 */
5439 local_bh_disable();
5440 napi_schedule(&bnx2x_fcoe(bp, napi));
5441 local_bh_enable();
5442 }
5443
5444 /* Handle EQ completions */
5445 bnx2x_eq_int(bp);
5446 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5447 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5448
5449 status &= ~BNX2X_DEF_SB_IDX;
019dbb4c 5450 }
55c11941 5451
fd1fc79d
AE		 5452 /* if status is non zero then perhaps something went wrong */
5453 if (unlikely(status))
5454 DP(BNX2X_MSG_SP,
5455 "got an unknown interrupt! (status 0x%x)\n", status);
523224a3 5456
fd1fc79d
AE		 5457 /* ack status block only if something was actually handled */
5458 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5459 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
cdaa7cb8
VZ		 5460 }
5461
fd1fc79d
AE		 5462 /* must be called after the EQ processing (since eq leads to sriov
5463 * ramrod completion flows).
5464 * This flow may have been scheduled by the arrival of a ramrod
5465 * completion, or by the sriov code rescheduling itself.
5466 */
5467 bnx2x_iov_sp_task(bp);
a3348722
BW		 5468
5469 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5470 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5471 &bp->sp_state)) {
5472 bnx2x_link_report(bp);
5473 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5474 }
a2fbb9ea
ET		 5475}
5476
9f6c9258 5477irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 5478{
5479 struct net_device *dev = dev_instance;
5480 struct bnx2x *bp = netdev_priv(dev);
5481
523224a3
DK		 5482 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5483 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 5484
5485#ifdef BNX2X_STOP_ON_ERROR
5486 if (unlikely(bp->panic))
5487 return IRQ_HANDLED;
5488#endif
5489
55c11941 5490 if (CNIC_LOADED(bp)) {
993ac7b5
MC		 5491 struct cnic_ops *c_ops;
5492
5493 rcu_read_lock();
5494 c_ops = rcu_dereference(bp->cnic_ops);
5495 if (c_ops)
5496 c_ops->cnic_handler(bp->cnic_data, NULL);
5497 rcu_read_unlock();
5498 }
55c11941 5499
fd1fc79d
AE		 5500 /* schedule sp task to perform default status block work, ack
5501 * attentions and enable interrupts.
5502 */
5503 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 5504
5505 return IRQ_HANDLED;
5506}
5507
5508/* end of slow path */
5509
619c5cb6
VZ		 5510void bnx2x_drv_pulse(struct bnx2x *bp)
5511{
5512 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5513 bp->fw_drv_pulse_wr_seq);
5514}
5515
a2fbb9ea
ET		 5516static void bnx2x_timer(unsigned long data)
5517{
5518 struct bnx2x *bp = (struct bnx2x *) data;
5519
5520 if (!netif_running(bp->dev))
5521 return;
5522
67c431a5
AE		 5523 if (IS_PF(bp) &&
5524 !BP_NOMCP(bp)) {
f2e0899f 5525 int mb_idx = BP_FW_MB_IDX(bp);
4c868664
EG		 5526 u16 drv_pulse;
5527 u16 mcp_pulse;
a2fbb9ea
ET		 5528
5529 ++bp->fw_drv_pulse_wr_seq;
5530 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
a2fbb9ea 5531 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 5532 bnx2x_drv_pulse(bp);
a2fbb9ea 5533
f2e0899f 5534 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 5535 MCP_PULSE_SEQ_MASK);
5536 /* The delta between driver pulse and mcp response
4c868664
EG		 5537 * should not get too big. If the MFW is more than 5 pulses
5538 * behind, we should worry about it enough to generate an error
5539 * log.
a2fbb9ea 5540 */
4c868664
EG		 5541 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5542 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
a2fbb9ea 5543 drv_pulse, mcp_pulse);
a2fbb9ea
ET		 5544 }
5545
f34d28ea 5546 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 5547 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 5548
abc5a021 5549 /* sample pf vf bulletin board for new posts from pf */
37173488
YM		 5550 if (IS_VF(bp))
5551 bnx2x_timer_sriov(bp);
78c3bcc5 5552
a2fbb9ea
ET		 5553 mod_timer(&bp->timer, jiffies + bp->current_interval);
5554}
5555
5556/* end of Statistics */
5557
5558/* nic init */
5559
5560/*
5561 * nic init service functions
5562 */
5563
1191cb83 5564static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 5565{
523224a3
DK		 5566 u32 i;
5567 if (!(len%4) && !(addr%4))
5568 for (i = 0; i < len; i += 4)
5569 REG_WR(bp, addr + i, fill);
5570 else
5571 for (i = 0; i < len; i++)
5572 REG_WR8(bp, addr + i, fill);
34f80b04
EG		 5573}
5574
523224a3 5575/* helper: writes FP SP data to FW - data_size in dwords */
1191cb83
ED		 5576static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5577 int fw_sb_id,
5578 u32 *sb_data_p,
5579 u32 data_size)
34f80b04 5580{
a2fbb9ea 5581 int index;
523224a3
DK		 5582 for (index = 0; index < data_size; index++)
5583 REG_WR(bp, BAR_CSTRORM_INTMEM +
5584 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5585 sizeof(u32)*index,
5586 *(sb_data_p + index));
5587}
a2fbb9ea 5588
1191cb83 5589static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
523224a3
DK		 5590{
5591 u32 *sb_data_p;
5592 u32 data_size = 0;
f2e0899f 5593 struct hc_status_block_data_e2 sb_data_e2;
523224a3 5594 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 5595
523224a3 5596 /* disable the function first */
619c5cb6 5597 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5598 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5599 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 5600 sb_data_e2.common.p_func.vf_valid = false;
5601 sb_data_p = (u32 *)&sb_data_e2;
5602 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5603 } else {
5604 memset(&sb_data_e1x, 0,
5605 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5606 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 5607 sb_data_e1x.common.p_func.vf_valid = false;
5608 sb_data_p = (u32 *)&sb_data_e1x;
5609 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5610 }
523224a3 5611 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 5612
523224a3
DK		 5613 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5614 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5615 CSTORM_STATUS_BLOCK_SIZE);
5616 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5617 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5618 CSTORM_SYNC_BLOCK_SIZE);
5619}
34f80b04 5620
523224a3 5621/* helper: writes SP SB data to FW */
1191cb83 5622static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
523224a3
DK		 5623 struct hc_sp_status_block_data *sp_sb_data)
5624{
5625 int func = BP_FUNC(bp);
5626 int i;
5627 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5628 REG_WR(bp, BAR_CSTRORM_INTMEM +
5629 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5630 i*sizeof(u32),
5631 *((u32 *)sp_sb_data + i));
34f80b04
EG		 5632}
5633
1191cb83 5634static void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 5635{
5636 int func = BP_FUNC(bp);
523224a3
DK		 5637 struct hc_sp_status_block_data sp_sb_data;
5638 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 5639
619c5cb6 5640 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 5641 sp_sb_data.p_func.vf_valid = false;
5642
5643 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5644
5645 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5646 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5647 CSTORM_SP_STATUS_BLOCK_SIZE);
5648 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5649 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5650 CSTORM_SP_SYNC_BLOCK_SIZE);
523224a3
DK		 5651}
5652
1191cb83 5653static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
523224a3
DK		 5654 int igu_sb_id, int igu_seg_id)
5655{
5656 hc_sm->igu_sb_id = igu_sb_id;
5657 hc_sm->igu_seg_id = igu_seg_id;
5658 hc_sm->timer_value = 0xFF;
5659 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 5660}
5661
150966ad 5662/* allocates state machine ids. */
1191cb83 5663static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
150966ad
AE		 5664{
5665 /* zero out state machine indices */
5666 /* rx indices */
5667 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5668
5669 /* tx indices */
5670 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5671 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5672 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5673 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5674
5675 /* map indices */
5676 /* rx indices */
5677 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5678 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5679
5680 /* tx indices */
5681 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5682 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5683 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5684 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5685 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5686 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5687 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5688 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5689}
5690
b93288d5 5691void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 5692 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 5693{
523224a3
DK		 5694 int igu_seg_id;
5695
f2e0899f 5696 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 5697 struct hc_status_block_data_e1x sb_data_e1x;
5698 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 5699 int data_size;
5700 u32 *sb_data_p;
5701
f2e0899f
DK		 5702 if (CHIP_INT_MODE_IS_BC(bp))
5703 igu_seg_id = HC_SEG_ACCESS_NORM;
5704 else
5705 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 5706
5707 bnx2x_zero_fp_sb(bp, fw_sb_id);
5708
619c5cb6 5709 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5710 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5711 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 5712 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5713 sb_data_e2.common.p_func.vf_id = vfid;
5714 sb_data_e2.common.p_func.vf_valid = vf_valid;
5715 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5716 sb_data_e2.common.same_igu_sb_1b = true;
5717 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5718 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5719 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 5720 sb_data_p = (u32 *)&sb_data_e2;
5721 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 5722 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 5723 } else {
5724 memset(&sb_data_e1x, 0,
5725 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5726 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 5727 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5728 sb_data_e1x.common.p_func.vf_id = 0xff;
5729 sb_data_e1x.common.p_func.vf_valid = false;
5730 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5731 sb_data_e1x.common.same_igu_sb_1b = true;
5732 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5733 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5734 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 5735 sb_data_p = (u32 *)&sb_data_e1x;
5736 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 5737 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 5738 }
523224a3
DK		 5739
5740 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5741 igu_sb_id, igu_seg_id);
5742 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5743 igu_sb_id, igu_seg_id);
5744
51c1a580 5745 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
523224a3 5746
86564c3f 5747 /* write indices to HW - PCI guarantees endianity of regpairs */
523224a3
DK		 5748 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5749}
5750
619c5cb6 5751static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 5752 u16 tx_usec, u16 rx_usec)
5753{
6383c0b3 5754 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 5755 false, rx_usec);
6383c0b3
AE		 5756 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5757 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5758 tx_usec);
5759 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5760 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5761 tx_usec);
5762 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5763 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5764 tx_usec);
523224a3 5765}
f2e0899f 5766
523224a3
DK		 5767static void bnx2x_init_def_sb(struct bnx2x *bp)
5768{
5769 struct host_sp_status_block *def_sb = bp->def_status_blk;
5770 dma_addr_t mapping = bp->def_status_blk_mapping;
5771 int igu_sp_sb_index;
5772 int igu_seg_id;
34f80b04
EG		 5773 int port = BP_PORT(bp);
5774 int func = BP_FUNC(bp);
f2eaeb58 5775 int reg_offset, reg_offset_en5;
a2fbb9ea 5776 u64 section;
523224a3
DK		 5777 int index;
5778 struct hc_sp_status_block_data sp_sb_data;
5779 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5780
f2e0899f
DK		 5781 if (CHIP_INT_MODE_IS_BC(bp)) {
5782 igu_sp_sb_index = DEF_SB_IGU_ID;
5783 igu_seg_id = HC_SEG_ACCESS_DEF;
5784 } else {
5785 igu_sp_sb_index = bp->igu_dsb_id;
5786 igu_seg_id = IGU_SEG_ACCESS_DEF;
5787 }
a2fbb9ea
ET		 5788
5789 /* ATTN */
523224a3 5790 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 5791 atten_status_block);
523224a3 5792 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 5793
49d66772
ET		 5794 bp->attn_state = 0;
5795
a2fbb9ea
ET		 5796 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5797 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 5798 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5799 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 5800 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 5801 int sindex;
5802 /* take care of sig[0]..sig[4] */
5803 for (sindex = 0; sindex < 4; sindex++)
5804 bp->attn_group[index].sig[sindex] =
5805 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 5806
619c5cb6 5807 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5808 /*
5809 * enable5 is separate from the rest of the registers,
5810 * and therefore the address skip is 4
5811 * and not 16 between the different groups
5812 */
5813 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 5814 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 5815 else
5816 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 5817 }
5818
f2e0899f
DK		 5819 if (bp->common.int_block == INT_BLOCK_HC) {
5820 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5821 HC_REG_ATTN_MSG0_ADDR_L);
5822
5823 REG_WR(bp, reg_offset, U64_LO(section));
5824 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 5825 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5826 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5827 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5828 }
a2fbb9ea 5829
523224a3
DK		 5830 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5831 sp_sb);
a2fbb9ea 5832
523224a3 5833 bnx2x_zero_sp_sb(bp);
a2fbb9ea 5834
86564c3f 5835 /* PCI guarantees endianity of regpairs */
619c5cb6 5836 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 5837 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5838 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5839 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5840 sp_sb_data.igu_seg_id = igu_seg_id;
5841 sp_sb_data.p_func.pf_id = func;
f2e0899f 5842 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 5843 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 5844
523224a3 5845 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 5846
523224a3 5847 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 5848}
5849
9f6c9258 5850void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 5851{
a2fbb9ea
ET		 5852 int i;
5853
ec6ba945 5854 for_each_eth_queue(bp, i)
523224a3 5855 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 5856 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 5857}
5858
a2fbb9ea
ET		 5859static void bnx2x_init_sp_ring(struct bnx2x *bp)
5860{
a2fbb9ea 5861 spin_lock_init(&bp->spq_lock);
6e30dd4e 5862 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 5863
a2fbb9ea 5864 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 5865 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5866 bp->spq_prod_bd = bp->spq;
5867 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 5868}
5869
523224a3 5870static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 5871{
5872 int i;
523224a3
DK		 5873 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5874 union event_ring_elem *elem =
5875 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 5876
523224a3
DK		 5877 elem->next_page.addr.hi =
5878 cpu_to_le32(U64_HI(bp->eq_mapping +
5879 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5880 elem->next_page.addr.lo =
5881 cpu_to_le32(U64_LO(bp->eq_mapping +
5882 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 5883 }
523224a3
DK		 5884 bp->eq_cons = 0;
5885 bp->eq_prod = NUM_EQ_DESC;
5886 bp->eq_cons_sb = BNX2X_EQ_INDEX;
16a5fd92 5887 /* we want a warning message before it gets wrought... */
6e30dd4e
VZ		 5888 atomic_set(&bp->eq_spq_left,
5889 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 5890}
5891
619c5cb6 5892/* called with netif_addr_lock_bh() */
a8f47eb7 5893static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5894 unsigned long rx_mode_flags,
5895 unsigned long rx_accept_flags,
5896 unsigned long tx_accept_flags,
5897 unsigned long ramrod_flags)
ab532cf3 5898{
619c5cb6
VZ		 5899 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5900 int rc;
5901
5902 memset(&ramrod_param, 0, sizeof(ramrod_param));
5903
5904 /* Prepare ramrod parameters */
5905 ramrod_param.cid = 0;
5906 ramrod_param.cl_id = cl_id;
5907 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5908 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 5909
619c5cb6
VZ		 5910 ramrod_param.pstate = &bp->sp_state;
5911 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 5912
619c5cb6
VZ		 5913 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5914 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5915
5916 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5917
5918 ramrod_param.ramrod_flags = ramrod_flags;
5919 ramrod_param.rx_mode_flags = rx_mode_flags;
5920
5921 ramrod_param.rx_accept_flags = rx_accept_flags;
5922 ramrod_param.tx_accept_flags = tx_accept_flags;
5923
5924 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5925 if (rc < 0) {
5926 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
924d75ab 5927 return rc;
619c5cb6 5928 }
924d75ab
YM		 5929
5930 return 0;
a2fbb9ea
ET		 5931}
5932
86564c3f
YM		 5933static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5934 unsigned long *rx_accept_flags,
5935 unsigned long *tx_accept_flags)
471de716 5936{
924d75ab
YM		 5937 /* Clear the flags first */
5938 *rx_accept_flags = 0;
5939 *tx_accept_flags = 0;
619c5cb6 5940
924d75ab 5941 switch (rx_mode) {
619c5cb6
VZ		 5942 case BNX2X_RX_MODE_NONE:
5943 /*
5944 * 'drop all' supersedes any accept flags that may have been
5945 * passed to the function.
5946 */
5947 break;
5948 case BNX2X_RX_MODE_NORMAL:
924d75ab
YM		 5949 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5950 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5951 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 5952
5953 /* internal switching mode */
924d75ab
YM		 5954 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5955 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5956 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 5957
5958 break;
5959 case BNX2X_RX_MODE_ALLMULTI:
924d75ab
YM		 5960 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5961 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5962 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 5963
5964 /* internal switching mode */
924d75ab
YM		 5965 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5966 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5967 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 5968
5969 break;
5970 case BNX2X_RX_MODE_PROMISC:
16a5fd92 5971 /* According to definition of SI mode, iface in promisc mode
619c5cb6
VZ		 5972 * should receive matched and unmatched (in resolution of port)
5973 * unicast packets.
5974 */
924d75ab
YM		 5975 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5976 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5977 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5978 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 5979
5980 /* internal switching mode */
924d75ab
YM		 5981 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5982 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 5983
5984 if (IS_MF_SI(bp))
924d75ab 5985 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
619c5cb6 5986 else
924d75ab 5987 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
619c5cb6
VZ		 5988
5989 break;
5990 default:
924d75ab
YM		 5991 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5992 return -EINVAL;
619c5cb6 5993 }
de832a55 5994
924d75ab 5995 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
619c5cb6 5996 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
924d75ab
YM		 5997 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
5998 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
34f80b04
EG		 5999 }
6000
924d75ab
YM		 6001 return 0;
6002}
6003
6004/* called with netif_addr_lock_bh() */
a8f47eb7 6005static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
924d75ab
YM		 6006{
6007 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6008 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6009 int rc;
6010
6011 if (!NO_FCOE(bp))
6012 /* Configure rx_mode of FCoE Queue */
6013 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6014
6015 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6016 &tx_accept_flags);
6017 if (rc)
6018 return rc;
6019
619c5cb6
VZ		 6020 __set_bit(RAMROD_RX, &ramrod_flags);
6021 __set_bit(RAMROD_TX, &ramrod_flags);
6022
924d75ab
YM		 6023 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6024 rx_accept_flags, tx_accept_flags,
6025 ramrod_flags);
619c5cb6
VZ		 6026}
6027
6028static void bnx2x_init_internal_common(struct bnx2x *bp)
6029{
6030 int i;
6031
523224a3
DK		 6032 /* Zero this manually as its initialization is
6033 currently missing in the initTool */
6034 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 6035 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 6036 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 6037 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6038 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6039 CHIP_INT_MODE_IS_BC(bp) ?
6040 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6041 }
523224a3 6042}
8a1c38d1 6043
471de716
EG		 6044static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6045{
6046 switch (load_code) {
6047 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 6048 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 6049 bnx2x_init_internal_common(bp);
6050 /* no break */
6051
6052 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 6053 /* nothing to do */
471de716
EG		 6054 /* no break */
6055
6056 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 6057 /* internal memory per function is
6058 initialized inside bnx2x_pf_init */
471de716
EG		 6059 break;
6060
6061 default:
6062 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6063 break;
6064 }
6065}
6066
619c5cb6 6067static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 6068{
55c11941 6069 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6 6070}
523224a3 6071
619c5cb6
VZ		 6072static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6073{
55c11941 6074 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6
VZ		 6075}
6076
1191cb83 6077static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
619c5cb6
VZ		 6078{
6079 if (CHIP_IS_E1x(fp->bp))
6080 return BP_L_ID(fp->bp) + fp->index;
6081 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6082 return bnx2x_fp_igu_sb_id(fp);
6083}
6084
6383c0b3 6085static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 6086{
6087 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 6088 u8 cos;
619c5cb6 6089 unsigned long q_type = 0;
6383c0b3 6090 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 6091 fp->rx_queue = fp_idx;
b3b83c3f 6092 fp->cid = fp_idx;
619c5cb6
VZ		 6093 fp->cl_id = bnx2x_fp_cl_id(fp);
6094 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6095 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 6096 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 6097 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6098
523224a3 6099 /* init shortcut */
619c5cb6 6100 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
7a752993 6101
16a5fd92 6102 /* Setup SB indices */
523224a3 6103 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 6104
619c5cb6
VZ		 6105 /* Configure Queue State object */
6106 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6107 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 6108
6109 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6110
6111 /* init tx data */
6112 for_each_cos_in_tx_queue(fp, cos) {
65565884
MS		 6113 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6114 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6115 FP_COS_TO_TXQ(fp, cos, bp),
6116 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6117 cids[cos] = fp->txdata_ptr[cos]->cid;
6383c0b3
AE		 6118 }
6119
ad5afc89
AE		 6120 /* nothing more for vf to do here */
6121 if (IS_VF(bp))
6122 return;
6123
6124 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6125 fp->fw_sb_id, fp->igu_sb_id);
6126 bnx2x_update_fpsb_idx(fp);
15192a8c
BW		 6127 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6128 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6383c0b3 6129 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 6130
6131 /**
6132 * Configure classification DBs: Always enable Tx switching
6133 */
6134 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6135
ad5afc89
AE		 6136 DP(NETIF_MSG_IFUP,
6137 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6138 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6139 fp->igu_sb_id);
523224a3
DK		 6140}
6141
1191cb83
ED		 6142static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6143{
6144 int i;
6145
6146 for (i = 1; i <= NUM_TX_RINGS; i++) {
6147 struct eth_tx_next_bd *tx_next_bd =
6148 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6149
6150 tx_next_bd->addr_hi =
6151 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6152 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6153 tx_next_bd->addr_lo =
6154 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6155 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6156 }
6157
639d65b8
YM		 6158 *txdata->tx_cons_sb = cpu_to_le16(0);
6159
1191cb83
ED		 6160 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6161 txdata->tx_db.data.zero_fill1 = 0;
6162 txdata->tx_db.data.prod = 0;
6163
6164 txdata->tx_pkt_prod = 0;
6165 txdata->tx_pkt_cons = 0;
6166 txdata->tx_bd_prod = 0;
6167 txdata->tx_bd_cons = 0;
6168 txdata->tx_pkt = 0;
6169}
6170
55c11941
MS		 6171static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6172{
6173 int i;
6174
6175 for_each_tx_queue_cnic(bp, i)
6176 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6177}
d76a6111 6178
1191cb83
ED		 6179static void bnx2x_init_tx_rings(struct bnx2x *bp)
6180{
6181 int i;
6182 u8 cos;
6183
55c11941 6184 for_each_eth_queue(bp, i)
1191cb83 6185 for_each_cos_in_tx_queue(&bp->fp[i], cos)
65565884 6186 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
1191cb83
ED		 6187}
6188
a8f47eb7 6189static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6190{
6191 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6192 unsigned long q_type = 0;
6193
6194 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6195 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6196 BNX2X_FCOE_ETH_CL_ID_IDX);
6197 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6198 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6199 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6200 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6201 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6202 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6203 fp);
6204
6205 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6206
6207 /* qZone id equals to FW (per path) client id */
6208 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6209 /* init shortcut */
6210 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6211 bnx2x_rx_ustorm_prods_offset(fp);
6212
6213 /* Configure Queue State object */
6214 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6215 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6216
6217 /* No multi-CoS for FCoE L2 client */
6218 BUG_ON(fp->max_cos != 1);
6219
6220 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6221 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6222 bnx2x_sp_mapping(bp, q_rdata), q_type);
6223
6224 DP(NETIF_MSG_IFUP,
6225 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6226 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6227 fp->igu_sb_id);
6228}
6229
55c11941 6230void bnx2x_nic_init_cnic(struct bnx2x *bp)
a2fbb9ea 6231{
ec6ba945
VZ		 6232 if (!NO_FCOE(bp))
6233 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 6234
6235 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6236 BNX2X_VF_ID_INVALID, false,
619c5cb6 6237 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 6238
55c11941
MS		 6239 /* ensure status block indices were read */
6240 rmb();
6241 bnx2x_init_rx_rings_cnic(bp);
6242 bnx2x_init_tx_rings_cnic(bp);
6243
6244 /* flush all */
6245 mb();
6246 mmiowb();
6247}
a2fbb9ea 6248
ecf01c22 6249void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
55c11941
MS		 6250{
6251 int i;
6252
ecf01c22 6253 /* Setup NIC internals and enable interrupts */
55c11941
MS		 6254 for_each_eth_queue(bp, i)
6255 bnx2x_init_eth_fp(bp, i);
ad5afc89
AE		 6256
6257 /* ensure status block indices were read */
6258 rmb();
6259 bnx2x_init_rx_rings(bp);
6260 bnx2x_init_tx_rings(bp);
6261
ecf01c22
YM		 6262 if (IS_PF(bp)) {
6263 /* Initialize MOD_ABS interrupts */
6264 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6265 bp->common.shmem_base,
6266 bp->common.shmem2_base, BP_PORT(bp));
ad5afc89 6267
ecf01c22
YM		 6268 /* initialize the default status block and sp ring */
6269 bnx2x_init_def_sb(bp);
6270 bnx2x_update_dsb_idx(bp);
6271 bnx2x_init_sp_ring(bp);
3cdeec22
YM		 6272 } else {
6273 bnx2x_memset_stats(bp);
ecf01c22
YM		 6274 }
6275}
16119785 6276
ecf01c22
YM		 6277void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6278{
523224a3 6279 bnx2x_init_eq_ring(bp);
471de716 6280 bnx2x_init_internal(bp, load_code);
523224a3 6281 bnx2x_pf_init(bp);
0ef00459
EG		 6282 bnx2x_stats_init(bp);
6283
0ef00459
EG		 6284 /* flush all before enabling interrupts */
6285 mb();
6286 mmiowb();
6287
615f8fd9 6288 bnx2x_int_enable(bp);
eb8da205
EG		 6289
6290 /* Check for SPIO5 */
6291 bnx2x_attn_int_deasserted0(bp,
6292 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6293 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 6294}
6295
ecf01c22 6296/* gzip service functions */
a2fbb9ea
ET		 6297static int bnx2x_gunzip_init(struct bnx2x *bp)
6298{
1a983142
FT		 6299 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6300 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 6301 if (bp->gunzip_buf == NULL)
6302 goto gunzip_nomem1;
6303
6304 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6305 if (bp->strm == NULL)
6306 goto gunzip_nomem2;
6307
7ab24bfd 6308 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 6309 if (bp->strm->workspace == NULL)
6310 goto gunzip_nomem3;
6311
6312 return 0;
6313
6314gunzip_nomem3:
6315 kfree(bp->strm);
6316 bp->strm = NULL;
6317
6318gunzip_nomem2:
1a983142
FT		 6319 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6320 bp->gunzip_mapping);
a2fbb9ea
ET		 6321 bp->gunzip_buf = NULL;
6322
6323gunzip_nomem1:
51c1a580 6324 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
a2fbb9ea
ET		 6325 return -ENOMEM;
6326}
6327
6328static void bnx2x_gunzip_end(struct bnx2x *bp)
6329{
b3b83c3f 6330 if (bp->strm) {
7ab24bfd 6331 vfree(bp->strm->workspace);
b3b83c3f
DK		 6332 kfree(bp->strm);
6333 bp->strm = NULL;
6334 }
a2fbb9ea
ET		 6335
6336 if (bp->gunzip_buf) {
1a983142
FT		 6337 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6338 bp->gunzip_mapping);
a2fbb9ea
ET		 6339 bp->gunzip_buf = NULL;
6340 }
6341}
6342
94a78b79 6343static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 6344{
6345 int n, rc;
6346
6347 /* check gzip header */
94a78b79
VZ		 6348 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6349 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 6350 return -EINVAL;
94a78b79 6351 }
a2fbb9ea
ET		 6352
6353 n = 10;
6354
34f80b04 6355#define FNAME 0x8
a2fbb9ea
ET		 6356
6357 if (zbuf[3] & FNAME)
6358 while ((zbuf[n++] != 0) && (n < len));
6359
94a78b79 6360 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 6361 bp->strm->avail_in = len - n;
6362 bp->strm->next_out = bp->gunzip_buf;
6363 bp->strm->avail_out = FW_BUF_SIZE;
6364
6365 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6366 if (rc != Z_OK)
6367 return rc;
6368
6369 rc = zlib_inflate(bp->strm, Z_FINISH);
6370 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 6371 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6372 bp->strm->msg);
a2fbb9ea
ET		 6373
6374 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6375 if (bp->gunzip_outlen & 0x3)
51c1a580
MS		 6376 netdev_err(bp->dev,
6377 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
cdaa7cb8 6378 bp->gunzip_outlen);
a2fbb9ea
ET		 6379 bp->gunzip_outlen >>= 2;
6380
6381 zlib_inflateEnd(bp->strm);
6382
6383 if (rc == Z_STREAM_END)
6384 return 0;
6385
6386 return rc;
6387}
6388
6389/* nic load/unload */
6390
6391/*
34f80b04 6392 * General service functions
a2fbb9ea
ET		 6393 */
6394
6395/* send a NIG loopback debug packet */
6396static void bnx2x_lb_pckt(struct bnx2x *bp)
6397{
a2fbb9ea 6398 u32 wb_write[3];
a2fbb9ea
ET		 6399
6400 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 6401 wb_write[0] = 0x55555555;
6402 wb_write[1] = 0x55555555;
34f80b04 6403 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 6404 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6405
6406 /* NON-IP protocol */
a2fbb9ea
ET		 6407 wb_write[0] = 0x09000000;
6408 wb_write[1] = 0x55555555;
34f80b04 6409 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 6410 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6411}
6412
6413/* some of the internal memories
6414 * are not directly readable from the driver
6415 * to test them we send debug packets
6416 */
6417static int bnx2x_int_mem_test(struct bnx2x *bp)
6418{
6419 int factor;
6420 int count, i;
6421 u32 val = 0;
6422
ad8d3948 6423 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 6424 factor = 120;
ad8d3948
EG		 6425 else if (CHIP_REV_IS_EMUL(bp))
6426 factor = 200;
6427 else
a2fbb9ea 6428 factor = 1;
a2fbb9ea 6429
a2fbb9ea
ET		 6430 /* Disable inputs of parser neighbor blocks */
6431 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6432 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6433 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6434 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6435
6436 /* Write 0 to parser credits for CFC search request */
6437 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6438
6439 /* send Ethernet packet */
6440 bnx2x_lb_pckt(bp);
6441
6442 /* TODO do i reset NIG statistic? */
6443 /* Wait until NIG register shows 1 packet of size 0x10 */
6444 count = 1000 * factor;
6445 while (count) {
34f80b04 6446
a2fbb9ea
ET		 6447 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6448 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6449 if (val == 0x10)
6450 break;
6451
639d65b8 6452 usleep_range(10000, 20000);
a2fbb9ea
ET		 6453 count--;
6454 }
6455 if (val != 0x10) {
6456 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6457 return -1;
6458 }
6459
6460 /* Wait until PRS register shows 1 packet */
6461 count = 1000 * factor;
6462 while (count) {
6463 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 6464 if (val == 1)
6465 break;
6466
639d65b8 6467 usleep_range(10000, 20000);
a2fbb9ea
ET		 6468 count--;
6469 }
6470 if (val != 0x1) {
6471 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6472 return -2;
6473 }
6474
6475 /* Reset and init BRB, PRS */
34f80b04 6476 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 6477 msleep(50);
34f80b04 6478 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 6479 msleep(50);
619c5cb6
VZ		 6480 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6481 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 6482
6483 DP(NETIF_MSG_HW, "part2\n");
6484
6485 /* Disable inputs of parser neighbor blocks */
6486 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6487 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6488 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6489 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6490
6491 /* Write 0 to parser credits for CFC search request */
6492 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6493
6494 /* send 10 Ethernet packets */
6495 for (i = 0; i < 10; i++)
6496 bnx2x_lb_pckt(bp);
6497
6498 /* Wait until NIG register shows 10 + 1
6499 packets of size 11*0x10 = 0xb0 */
6500 count = 1000 * factor;
6501 while (count) {
34f80b04 6502
a2fbb9ea
ET		 6503 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6504 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6505 if (val == 0xb0)
6506 break;
6507
639d65b8 6508 usleep_range(10000, 20000);
a2fbb9ea
ET		 6509 count--;
6510 }
6511 if (val != 0xb0) {
6512 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6513 return -3;
6514 }
6515
6516 /* Wait until PRS register shows 2 packets */
6517 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6518 if (val != 2)
6519 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6520
6521 /* Write 1 to parser credits for CFC search request */
6522 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6523
6524 /* Wait until PRS register shows 3 packets */
6525 msleep(10 * factor);
6526 /* Wait until NIG register shows 1 packet of size 0x10 */
6527 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6528 if (val != 3)
6529 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6530
6531 /* clear NIG EOP FIFO */
6532 for (i = 0; i < 11; i++)
6533 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6534 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6535 if (val != 1) {
6536 BNX2X_ERR("clear of NIG failed\n");
6537 return -4;
6538 }
6539
6540 /* Reset and init BRB, PRS, NIG */
6541 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6542 msleep(50);
6543 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6544 msleep(50);
619c5cb6
VZ		 6545 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6546 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
55c11941
MS		 6547 if (!CNIC_SUPPORT(bp))
6548 /* set NIC mode */
6549 REG_WR(bp, PRS_REG_NIC_MODE, 1);
a2fbb9ea
ET		 6550
6551 /* Enable inputs of parser neighbor blocks */
6552 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6553 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6554 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 6555 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 6556
6557 DP(NETIF_MSG_HW, "done\n");
6558
6559 return 0; /* OK */
6560}
6561
4a33bc03 6562static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea 6563{
b343d002
YM		 6564 u32 val;
6565
a2fbb9ea 6566 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 6567 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6568 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6569 else
6570 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 6571 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6572 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 6573 /*
6574 * mask read length error interrupts in brb for parser
6575 * (parsing unit and 'checksum and crc' unit)
6576 * these errors are legal (PU reads fixed length and CAC can cause
6577 * read length error on truncated packets)
6578 */
6579 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 6580 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6581 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6582 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6583 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6584 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 6585/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6586/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6587 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6588 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6589 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 6590/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6591/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6592 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6593 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6594 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6595 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 6596/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6597/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 6598
b343d002
YM		 6599 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6600 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6601 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6602 if (!CHIP_IS_E1x(bp))
6603 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6604 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6605 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6606
a2fbb9ea
ET		 6607 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6608 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6609 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 6610/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 6611
6612 if (!CHIP_IS_E1x(bp))
6613 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6614 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6615
a2fbb9ea
ET		 6616 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6617 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 6618/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 6619 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 6620}
6621
81f75bbf
EG		 6622static void bnx2x_reset_common(struct bnx2x *bp)
6623{
619c5cb6
VZ		 6624 u32 val = 0x1400;
6625
81f75bbf
EG		 6626 /* reset_common */
6627 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6628 0xd3ffff7f);
619c5cb6
VZ		 6629
6630 if (CHIP_IS_E3(bp)) {
6631 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6632 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6633 }
6634
6635 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6636}
6637
6638static void bnx2x_setup_dmae(struct bnx2x *bp)
6639{
6640 bp->dmae_ready = 0;
6641 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 6642}
6643
573f2035
EG		 6644static void bnx2x_init_pxp(struct bnx2x *bp)
6645{
6646 u16 devctl;
6647 int r_order, w_order;
6648
2a80eebc 6649 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 6650 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6651 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6652 if (bp->mrrs == -1)
6653 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6654 else {
6655 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6656 r_order = bp->mrrs;
6657 }
6658
6659 bnx2x_init_pxp_arb(bp, r_order, w_order);
6660}
fd4ef40d
EG		 6661
6662static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6663{
2145a920 6664 int is_required;
fd4ef40d 6665 u32 val;
2145a920 6666 int port;
fd4ef40d 6667
2145a920
VZ		 6668 if (BP_NOMCP(bp))
6669 return;
6670
6671 is_required = 0;
fd4ef40d
EG		 6672 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6673 SHARED_HW_CFG_FAN_FAILURE_MASK;
6674
6675 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6676 is_required = 1;
6677
6678 /*
6679 * The fan failure mechanism is usually related to the PHY type since
6680 * the power consumption of the board is affected by the PHY. Currently,
6681 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6682 */
6683 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6684 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 6685 is_required |=
d90d96ba
YR		 6686 bnx2x_fan_failure_det_req(
6687 bp,
6688 bp->common.shmem_base,
a22f0788 6689 bp->common.shmem2_base,
d90d96ba 6690 port);
fd4ef40d
EG		 6691 }
6692
6693 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6694
6695 if (is_required == 0)
6696 return;
6697
6698 /* Fan failure is indicated by SPIO 5 */
d6d99a3f 6699 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
fd4ef40d
EG		 6700
6701 /* set to active low mode */
6702 val = REG_RD(bp, MISC_REG_SPIO_INT);
d6d99a3f 6703 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 6704 REG_WR(bp, MISC_REG_SPIO_INT, val);
6705
6706 /* enable interrupt to signal the IGU */
6707 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 6708 val |= MISC_SPIO_SPIO5;
fd4ef40d
EG		 6709 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6710}
6711
c9ee9206 6712void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 6713{
6714 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6715 val &= ~IGU_PF_CONF_FUNC_EN;
6716
6717 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6718 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6719 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6720}
6721
1191cb83 6722static void bnx2x__common_init_phy(struct bnx2x *bp)
619c5cb6
VZ		 6723{
6724 u32 shmem_base[2], shmem2_base[2];
b884d95b
YR		 6725 /* Avoid common init in case MFW supports LFA */
6726 if (SHMEM2_RD(bp, size) >
6727 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6728 return;
619c5cb6
VZ		 6729 shmem_base[0] = bp->common.shmem_base;
6730 shmem2_base[0] = bp->common.shmem2_base;
6731 if (!CHIP_IS_E1x(bp)) {
6732 shmem_base[1] =
6733 SHMEM2_RD(bp, other_shmem_base_addr);
6734 shmem2_base[1] =
6735 SHMEM2_RD(bp, other_shmem2_base_addr);
6736 }
6737 bnx2x_acquire_phy_lock(bp);
6738 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6739 bp->common.chip_id);
6740 bnx2x_release_phy_lock(bp);
6741}
6742
6743/**
6744 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6745 *
6746 * @bp: driver handle
6747 */
6748static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 6749{
619c5cb6 6750 u32 val;
a2fbb9ea 6751
51c1a580 6752 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 6753
2031bd3a 6754 /*
2de67439 6755 * take the RESET lock to protect undi_unload flow from accessing
2031bd3a
DK		 6756 * registers while we're resetting the chip
6757 */
7a06a122 6758 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6759
81f75bbf 6760 bnx2x_reset_common(bp);
34f80b04 6761 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 6762
619c5cb6
VZ		 6763 val = 0xfffc;
6764 if (CHIP_IS_E3(bp)) {
6765 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6766 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6767 }
6768 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6769
7a06a122 6770 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6771
619c5cb6 6772 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 6773
619c5cb6
VZ		 6774 if (!CHIP_IS_E1x(bp)) {
6775 u8 abs_func_id;
f2e0899f
DK		 6776
6777 /**
6778 * 4-port mode or 2-port mode we need to turn of master-enable
6779 * for everyone, after that, turn it back on for self.
6780 * so, we disregard multi-function or not, and always disable
6781 * for all functions on the given path, this means 0,2,4,6 for
6782 * path 0 and 1,3,5,7 for path 1
6783 */
619c5cb6
VZ		 6784 for (abs_func_id = BP_PATH(bp);
6785 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6786 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 6787 REG_WR(bp,
6788 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6789 1);
6790 continue;
6791 }
6792
619c5cb6 6793 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 6794 /* clear pf enable */
6795 bnx2x_pf_disable(bp);
6796 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6797 }
6798 }
a2fbb9ea 6799
619c5cb6 6800 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 6801 if (CHIP_IS_E1(bp)) {
6802 /* enable HW interrupt from PXP on USDM overflow
6803 bit 16 on INT_MASK_0 */
6804 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6805 }
a2fbb9ea 6806
619c5cb6 6807 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 6808 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 6809
6810#ifdef __BIG_ENDIAN
34f80b04
EG		 6811 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6812 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6813 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6814 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6815 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 6816 /* make sure this value is 0 */
6817 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 6818
6819/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6820 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6821 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6822 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6823 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 6824#endif
6825
523224a3
DK		 6826 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6827
34f80b04
EG		 6828 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6829 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 6830
34f80b04
EG		 6831 /* let the HW do it's magic ... */
6832 msleep(100);
6833 /* finish PXP init */
6834 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6835 if (val != 1) {
6836 BNX2X_ERR("PXP2 CFG failed\n");
6837 return -EBUSY;
6838 }
6839 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6840 if (val != 1) {
6841 BNX2X_ERR("PXP2 RD_INIT failed\n");
6842 return -EBUSY;
6843 }
a2fbb9ea 6844
f2e0899f
DK		 6845 /* Timers bug workaround E2 only. We need to set the entire ILT to
6846 * have entries with value "0" and valid bit on.
6847 * This needs to be done by the first PF that is loaded in a path
6848 * (i.e. common phase)
6849 */
619c5cb6
VZ		 6850 if (!CHIP_IS_E1x(bp)) {
6851/* In E2 there is a bug in the timers block that can cause function 6 / 7
6852 * (i.e. vnic3) to start even if it is marked as "scan-off".
6853 * This occurs when a different function (func2,3) is being marked
6854 * as "scan-off". Real-life scenario for example: if a driver is being
6855 * load-unloaded while func6,7 are down. This will cause the timer to access
6856 * the ilt, translate to a logical address and send a request to read/write.
6857 * Since the ilt for the function that is down is not valid, this will cause
6858 * a translation error which is unrecoverable.
6859 * The Workaround is intended to make sure that when this happens nothing fatal
6860 * will occur. The workaround:
6861 * 1. First PF driver which loads on a path will:
6862 * a. After taking the chip out of reset, by using pretend,
6863 * it will write "0" to the following registers of
6864 * the other vnics.
6865 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6866 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6867 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6868 * And for itself it will write '1' to
6869 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6870 * dmae-operations (writing to pram for example.)
6871 * note: can be done for only function 6,7 but cleaner this
6872 * way.
6873 * b. Write zero+valid to the entire ILT.
6874 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6875 * VNIC3 (of that port). The range allocated will be the
6876 * entire ILT. This is needed to prevent ILT range error.
6877 * 2. Any PF driver load flow:
6878 * a. ILT update with the physical addresses of the allocated
6879 * logical pages.
6880 * b. Wait 20msec. - note that this timeout is needed to make
6881 * sure there are no requests in one of the PXP internal
6882 * queues with "old" ILT addresses.
6883 * c. PF enable in the PGLC.
6884 * d. Clear the was_error of the PF in the PGLC. (could have
2de67439 6885 * occurred while driver was down)
619c5cb6
VZ		 6886 * e. PF enable in the CFC (WEAK + STRONG)
6887 * f. Timers scan enable
6888 * 3. PF driver unload flow:
6889 * a. Clear the Timers scan_en.
6890 * b. Polling for scan_on=0 for that PF.
6891 * c. Clear the PF enable bit in the PXP.
6892 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6893 * e. Write zero+valid to all ILT entries (The valid bit must
6894 * stay set)
6895 * f. If this is VNIC 3 of a port then also init
6896 * first_timers_ilt_entry to zero and last_timers_ilt_entry
16a5fd92 6897 * to the last entry in the ILT.
619c5cb6
VZ		 6898 *
6899 * Notes:
6900 * Currently the PF error in the PGLC is non recoverable.
6901 * In the future the there will be a recovery routine for this error.
6902 * Currently attention is masked.
6903 * Having an MCP lock on the load/unload process does not guarantee that
6904 * there is no Timer disable during Func6/7 enable. This is because the
6905 * Timers scan is currently being cleared by the MCP on FLR.
6906 * Step 2.d can be done only for PF6/7 and the driver can also check if
6907 * there is error before clearing it. But the flow above is simpler and
6908 * more general.
6909 * All ILT entries are written by zero+valid and not just PF6/7
6910 * ILT entries since in the future the ILT entries allocation for
6911 * PF-s might be dynamic.
6912 */
f2e0899f
DK		 6913 struct ilt_client_info ilt_cli;
6914 struct bnx2x_ilt ilt;
6915 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6916 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6917
b595076a 6918 /* initialize dummy TM client */
f2e0899f
DK		 6919 ilt_cli.start = 0;
6920 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6921 ilt_cli.client_num = ILT_CLIENT_TM;
6922
6923 /* Step 1: set zeroes to all ilt page entries with valid bit on
6924 * Step 2: set the timers first/last ilt entry to point
6925 * to the entire range to prevent ILT range error for 3rd/4th
2de67439 6926 * vnic (this code assumes existence of the vnic)
f2e0899f
DK		 6927 *
6928 * both steps performed by call to bnx2x_ilt_client_init_op()
6929 * with dummy TM client
6930 *
6931 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6932 * and his brother are split registers
6933 */
6934 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6935 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6936 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6937
6938 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6939 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6940 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6941 }
6942
34f80b04
EG		 6943 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6944 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 6945
619c5cb6 6946 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6947 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6948 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 6949 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 6950
619c5cb6 6951 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 6952
6953 /* let the HW do it's magic ... */
6954 do {
6955 msleep(200);
6956 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6957 } while (factor-- && (val != 1));
6958
6959 if (val != 1) {
6960 BNX2X_ERR("ATC_INIT failed\n");
6961 return -EBUSY;
6962 }
6963 }
6964
619c5cb6 6965 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 6966
b56e9670
AE		 6967 bnx2x_iov_init_dmae(bp);
6968
34f80b04
EG		 6969 /* clean the DMAE memory */
6970 bp->dmae_ready = 1;
619c5cb6
VZ		 6971 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6972
6973 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6974
6975 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6976
6977 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 6978
619c5cb6 6979 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 6980
34f80b04
EG		 6981 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6982 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6983 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6984 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6985
619c5cb6 6986 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 6987
523224a3
DK		 6988 /* QM queues pointers table */
6989 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6990
34f80b04
EG		 6991 /* soft reset pulse */
6992 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6993 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 6994
55c11941
MS		 6995 if (CNIC_SUPPORT(bp))
6996 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 6997
619c5cb6 6998 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
b9871bcf 6999
619c5cb6 7000 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 7001 /* enable hw interrupt from doorbell Q */
7002 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 7003
619c5cb6 7004 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 7005
619c5cb6 7006 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 7007 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 7008
f2e0899f 7009 if (!CHIP_IS_E1(bp))
619c5cb6 7010 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 7011
a3348722
BW		 7012 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7013 if (IS_MF_AFEX(bp)) {
7014 /* configure that VNTag and VLAN headers must be
7015 * received in afex mode
7016 */
7017 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7018 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7019 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7020 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7021 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7022 } else {
7023 /* Bit-map indicating which L2 hdrs may appear
7024 * after the basic Ethernet header
7025 */
7026 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7027 bp->path_has_ovlan ? 7 : 6);
7028 }
7029 }
a2fbb9ea 7030
619c5cb6
VZ		 7031 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7032 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7033 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7034 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 7035
619c5cb6
VZ		 7036 if (!CHIP_IS_E1x(bp)) {
7037 /* reset VFC memories */
7038 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7039 VFC_MEMORIES_RST_REG_CAM_RST |
7040 VFC_MEMORIES_RST_REG_RAM_RST);
7041 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7042 VFC_MEMORIES_RST_REG_CAM_RST |
7043 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 7044
619c5cb6
VZ		 7045 msleep(20);
7046 }
a2fbb9ea 7047
619c5cb6
VZ		 7048 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7049 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7050 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7051 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 7052
34f80b04
EG		 7053 /* sync semi rtc */
7054 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7055 0x80000000);
7056 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7057 0x80000000);
a2fbb9ea 7058
619c5cb6
VZ		 7059 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7060 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7061 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 7062
a3348722
BW		 7063 if (!CHIP_IS_E1x(bp)) {
7064 if (IS_MF_AFEX(bp)) {
7065 /* configure that VNTag and VLAN headers must be
7066 * sent in afex mode
7067 */
7068 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7069 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7070 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7071 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7072 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7073 } else {
7074 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7075 bp->path_has_ovlan ? 7 : 6);
7076 }
7077 }
f2e0899f 7078
34f80b04 7079 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 7080
619c5cb6
VZ		 7081 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7082
55c11941
MS		 7083 if (CNIC_SUPPORT(bp)) {
7084 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7085 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7086 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7087 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7088 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7089 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7090 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7091 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7092 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7093 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7094 }
34f80b04 7095 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 7096
34f80b04
EG		 7097 if (sizeof(union cdu_context) != 1024)
7098 /* we currently assume that a context is 1024 bytes */
51c1a580
MS		 7099 dev_alert(&bp->pdev->dev,
7100 "please adjust the size of cdu_context(%ld)\n",
7101 (long)sizeof(union cdu_context));
a2fbb9ea 7102
619c5cb6 7103 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 7104 val = (4 << 24) + (0 << 12) + 1024;
7105 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 7106
619c5cb6 7107 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 7108 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 7109 /* enable context validation interrupt from CFC */
7110 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7111
7112 /* set the thresholds to prevent CFC/CDU race */
7113 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 7114
619c5cb6 7115 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 7116
619c5cb6 7117 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 7118 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7119
619c5cb6
VZ		 7120 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7121 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 7122
34f80b04
EG		 7123 /* Reset PCIE errors for debug */
7124 REG_WR(bp, 0x2814, 0xffffffff);
7125 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 7126
619c5cb6 7127 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7128 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7129 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7130 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7131 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7132 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7133 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7134 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7135 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7136 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7137 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7138 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7139 }
7140
619c5cb6 7141 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 7142 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 7143 /* in E3 this done in per-port section */
7144 if (!CHIP_IS_E3(bp))
7145 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 7146 }
619c5cb6
VZ		 7147 if (CHIP_IS_E1H(bp))
7148 /* not applicable for E2 (and above ...) */
7149 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 7150
7151 if (CHIP_REV_IS_SLOW(bp))
7152 msleep(200);
7153
7154 /* finish CFC init */
7155 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7156 if (val != 1) {
7157 BNX2X_ERR("CFC LL_INIT failed\n");
7158 return -EBUSY;
7159 }
7160 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7161 if (val != 1) {
7162 BNX2X_ERR("CFC AC_INIT failed\n");
7163 return -EBUSY;
7164 }
7165 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7166 if (val != 1) {
7167 BNX2X_ERR("CFC CAM_INIT failed\n");
7168 return -EBUSY;
7169 }
7170 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 7171
f2e0899f
DK		 7172 if (CHIP_IS_E1(bp)) {
7173 /* read NIG statistic
7174 to see if this is our first up since powerup */
7175 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7176 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 7177
f2e0899f
DK		 7178 /* do internal memory self test */
7179 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7180 BNX2X_ERR("internal mem self test failed\n");
7181 return -EBUSY;
7182 }
34f80b04
EG		 7183 }
7184
fd4ef40d
EG		 7185 bnx2x_setup_fan_failure_detection(bp);
7186
34f80b04
EG		 7187 /* clear PXP2 attentions */
7188 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 7189
4a33bc03 7190 bnx2x_enable_blocks_attention(bp);
c9ee9206 7191 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 7192
6bbca910 7193 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 7194 if (CHIP_IS_E1x(bp))
7195 bnx2x__common_init_phy(bp);
6bbca910
YR		 7196 } else
7197 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7198
34f80b04
EG		 7199 return 0;
7200}
a2fbb9ea 7201
619c5cb6
VZ		 7202/**
7203 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7204 *
7205 * @bp: driver handle
7206 */
7207static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7208{
7209 int rc = bnx2x_init_hw_common(bp);
7210
7211 if (rc)
7212 return rc;
7213
7214 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7215 if (!BP_NOMCP(bp))
7216 bnx2x__common_init_phy(bp);
7217
7218 return 0;
7219}
7220
523224a3 7221static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 7222{
7223 int port = BP_PORT(bp);
619c5cb6 7224 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 7225 u32 low, high;
4293b9f5 7226 u32 val, reg;
a2fbb9ea 7227
51c1a580 7228 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
34f80b04
EG		 7229
7230 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 7231
619c5cb6
VZ		 7232 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7233 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7234 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 7235
f2e0899f
DK		 7236 /* Timers bug workaround: disables the pf_master bit in pglue at
7237 * common phase, we need to enable it here before any dmae access are
7238 * attempted. Therefore we manually added the enable-master to the
7239 * port phase (it also happens in the function phase)
7240 */
619c5cb6 7241 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7242 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7243
619c5cb6
VZ		 7244 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7245 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7246 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7247 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7248
7249 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7250 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7251 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7252 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 7253
523224a3
DK		 7254 /* QM cid (connection) count */
7255 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 7256
55c11941
MS		 7257 if (CNIC_SUPPORT(bp)) {
7258 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7259 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7260 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7261 }
cdaa7cb8 7262
619c5cb6 7263 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f 7264
2b674047
DK		 7265 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7266
f2e0899f 7267 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 7268
7269 if (IS_MF(bp))
7270 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7271 else if (bp->dev->mtu > 4096) {
7272 if (bp->flags & ONE_PORT_FLAG)
7273 low = 160;
7274 else {
7275 val = bp->dev->mtu;
7276 /* (24*1024 + val*4)/256 */
7277 low = 96 + (val/64) +
7278 ((val % 64) ? 1 : 0);
7279 }
7280 } else
7281 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7282 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 7283 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7284 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 7285 }
1c06328c 7286
619c5cb6
VZ		 7287 if (CHIP_MODE_IS_4_PORT(bp))
7288 REG_WR(bp, (BP_PORT(bp) ?
7289 BRB1_REG_MAC_GUARANTIED_1 :
7290 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 7291
619c5cb6 7292 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
a3348722
BW		 7293 if (CHIP_IS_E3B0(bp)) {
7294 if (IS_MF_AFEX(bp)) {
7295 /* configure headers for AFEX mode */
7296 REG_WR(bp, BP_PORT(bp) ?
7297 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7298 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7299 REG_WR(bp, BP_PORT(bp) ?
7300 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7301 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7302 REG_WR(bp, BP_PORT(bp) ?
7303 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7304 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7305 } else {
7306 /* Ovlan exists only if we are in multi-function +
7307 * switch-dependent mode, in switch-independent there
7308 * is no ovlan headers
7309 */
7310 REG_WR(bp, BP_PORT(bp) ?
7311 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7312 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7313 (bp->path_has_ovlan ? 7 : 6));
7314 }
7315 }
356e2385 7316
619c5cb6
VZ		 7317 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7318 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7319 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7320 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 7321
619c5cb6
VZ		 7322 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7323 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7324 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7325 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 7326
619c5cb6
VZ		 7327 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7328 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 7329
619c5cb6
VZ		 7330 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7331
7332 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7333 /* configure PBF to work without PAUSE mtu 9000 */
7334 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 7335
f2e0899f
DK		 7336 /* update threshold */
7337 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7338 /* update init credit */
7339 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 7340
f2e0899f
DK		 7341 /* probe changes */
7342 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7343 udelay(50);
7344 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7345 }
a2fbb9ea 7346
55c11941
MS		 7347 if (CNIC_SUPPORT(bp))
7348 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7349
619c5cb6
VZ		 7350 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7351 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 7352
7353 if (CHIP_IS_E1(bp)) {
7354 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7355 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7356 }
619c5cb6 7357 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 7358
619c5cb6 7359 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7360
619c5cb6 7361 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04 7362 /* init aeu_mask_attn_func_0/1:
16a5fd92
YM		 7363 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7364 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
34f80b04 7365 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 7366 val = IS_MF(bp) ? 0xF7 : 0x7;
7367 /* Enable DCBX attention for all but E1 */
7368 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7369 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 7370
4293b9f5
DK		 7371 /* SCPAD_PARITY should NOT trigger close the gates */
7372 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7373 REG_WR(bp, reg,
7374 REG_RD(bp, reg) &
7375 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7376
7377 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7378 REG_WR(bp, reg,
7379 REG_RD(bp, reg) &
7380 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7381
619c5cb6
VZ		 7382 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7383
7384 if (!CHIP_IS_E1x(bp)) {
7385 /* Bit-map indicating which L2 hdrs may appear after the
7386 * basic Ethernet header
7387 */
a3348722
BW		 7388 if (IS_MF_AFEX(bp))
7389 REG_WR(bp, BP_PORT(bp) ?
7390 NIG_REG_P1_HDRS_AFTER_BASIC :
7391 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7392 else
7393 REG_WR(bp, BP_PORT(bp) ?
7394 NIG_REG_P1_HDRS_AFTER_BASIC :
7395 NIG_REG_P0_HDRS_AFTER_BASIC,
7396 IS_MF_SD(bp) ? 7 : 6);
619c5cb6
VZ		 7397
7398 if (CHIP_IS_E3(bp))
7399 REG_WR(bp, BP_PORT(bp) ?
7400 NIG_REG_LLH1_MF_MODE :
7401 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7402 }
7403 if (!CHIP_IS_E3(bp))
7404 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 7405
f2e0899f 7406 if (!CHIP_IS_E1(bp)) {
fb3bff17 7407 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 7408 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 7409 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 7410
619c5cb6 7411 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7412 val = 0;
7413 switch (bp->mf_mode) {
7414 case MULTI_FUNCTION_SD:
7415 val = 1;
7416 break;
7417 case MULTI_FUNCTION_SI:
a3348722 7418 case MULTI_FUNCTION_AFEX:
f2e0899f
DK		 7419 val = 2;
7420 break;
7421 }
7422
7423 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7424 NIG_REG_LLH0_CLS_TYPE), val);
7425 }
1c06328c
EG		 7426 {
7427 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7428 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7429 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7430 }
34f80b04
EG		 7431 }
7432
619c5cb6
VZ		 7433 /* If SPIO5 is set to generate interrupts, enable it for this port */
7434 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 7435 if (val & MISC_SPIO_SPIO5) {
4d295db0
EG		 7436 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7437 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7438 val = REG_RD(bp, reg_addr);
f1410647 7439 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 7440 REG_WR(bp, reg_addr, val);
f1410647 7441 }
a2fbb9ea 7442
34f80b04
EG		 7443 return 0;
7444}
7445
34f80b04
EG		 7446static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7447{
7448 int reg;
32d68de1 7449 u32 wb_write[2];
34f80b04 7450
f2e0899f 7451 if (CHIP_IS_E1(bp))
34f80b04 7452 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 7453 else
7454 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04 7455
32d68de1
YM		 7456 wb_write[0] = ONCHIP_ADDR1(addr);
7457 wb_write[1] = ONCHIP_ADDR2(addr);
7458 REG_WR_DMAE(bp, reg, wb_write, 2);
34f80b04
EG		 7459}
7460
b56e9670 7461void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
1191cb83
ED		 7462{
7463 u32 data, ctl, cnt = 100;
7464 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7465 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7466 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7467 u32 sb_bit = 1 << (idu_sb_id%32);
b56e9670 7468 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
1191cb83
ED		 7469 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7470
7471 /* Not supported in BC mode */
7472 if (CHIP_INT_MODE_IS_BC(bp))
7473 return;
7474
7475 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7476 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7477 IGU_REGULAR_CLEANUP_SET |
7478 IGU_REGULAR_BCLEANUP;
7479
7480 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7481 func_encode << IGU_CTRL_REG_FID_SHIFT |
7482 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7483
7484 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7485 data, igu_addr_data);
7486 REG_WR(bp, igu_addr_data, data);
7487 mmiowb();
7488 barrier();
7489 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7490 ctl, igu_addr_ctl);
7491 REG_WR(bp, igu_addr_ctl, ctl);
7492 mmiowb();
7493 barrier();
7494
7495 /* wait for clean up to finish */
7496 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7497 msleep(20);
7498
1191cb83
ED		 7499 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7500 DP(NETIF_MSG_HW,
7501 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7502 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7503 }
7504}
7505
7506static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
f2e0899f 7507{
619c5cb6 7508 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 7509}
7510
1191cb83 7511static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
f2e0899f
DK		 7512{
7513 u32 i, base = FUNC_ILT_BASE(func);
7514 for (i = base; i < base + ILT_PER_FUNC; i++)
7515 bnx2x_ilt_wr(bp, i, 0);
7516}
7517
910cc727 7518static void bnx2x_init_searcher(struct bnx2x *bp)
55c11941
MS		 7519{
7520 int port = BP_PORT(bp);
7521 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7522 /* T1 hash bits value determines the T1 number of entries */
7523 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7524}
7525
7526static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7527{
7528 int rc;
7529 struct bnx2x_func_state_params func_params = {NULL};
7530 struct bnx2x_func_switch_update_params *switch_update_params =
7531 &func_params.params.switch_update;
7532
7533 /* Prepare parameters for function state transitions */
7534 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7535 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7536
7537 func_params.f_obj = &bp->func_obj;
7538 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7539
7540 /* Function parameters */
7541 switch_update_params->suspend = suspend;
7542
7543 rc = bnx2x_func_state_change(bp, &func_params);
7544
7545 return rc;
7546}
7547
910cc727 7548static int bnx2x_reset_nic_mode(struct bnx2x *bp)
55c11941
MS		 7549{
7550 int rc, i, port = BP_PORT(bp);
7551 int vlan_en = 0, mac_en[NUM_MACS];
7552
55c11941
MS		 7553 /* Close input from network */
7554 if (bp->mf_mode == SINGLE_FUNCTION) {
7555 bnx2x_set_rx_filter(&bp->link_params, 0);
7556 } else {
7557 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7558 NIG_REG_LLH0_FUNC_EN);
7559 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7560 NIG_REG_LLH0_FUNC_EN, 0);
7561 for (i = 0; i < NUM_MACS; i++) {
7562 mac_en[i] = REG_RD(bp, port ?
7563 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7564 4 * i) :
7565 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7566 4 * i));
7567 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7568 4 * i) :
7569 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7570 }
7571 }
7572
7573 /* Close BMC to host */
7574 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7575 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7576
7577 /* Suspend Tx switching to the PF. Completion of this ramrod
7578 * further guarantees that all the packets of that PF / child
7579 * VFs in BRB were processed by the Parser, so it is safe to
7580 * change the NIC_MODE register.
7581 */
7582 rc = bnx2x_func_switch_update(bp, 1);
7583 if (rc) {
7584 BNX2X_ERR("Can't suspend tx-switching!\n");
7585 return rc;
7586 }
7587
7588 /* Change NIC_MODE register */
7589 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7590
7591 /* Open input from network */
7592 if (bp->mf_mode == SINGLE_FUNCTION) {
7593 bnx2x_set_rx_filter(&bp->link_params, 1);
7594 } else {
7595 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7596 NIG_REG_LLH0_FUNC_EN, vlan_en);
7597 for (i = 0; i < NUM_MACS; i++) {
7598 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7599 4 * i) :
7600 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7601 mac_en[i]);
7602 }
7603 }
7604
7605 /* Enable BMC to host */
7606 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7607 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7608
7609 /* Resume Tx switching to the PF */
7610 rc = bnx2x_func_switch_update(bp, 0);
7611 if (rc) {
7612 BNX2X_ERR("Can't resume tx-switching!\n");
7613 return rc;
7614 }
7615
7616 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7617 return 0;
7618}
7619
7620int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7621{
7622 int rc;
7623
7624 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7625
7626 if (CONFIGURE_NIC_MODE(bp)) {
16a5fd92 7627 /* Configure searcher as part of function hw init */
55c11941
MS		 7628 bnx2x_init_searcher(bp);
7629
7630 /* Reset NIC mode */
7631 rc = bnx2x_reset_nic_mode(bp);
7632 if (rc)
7633 BNX2X_ERR("Can't change NIC mode!\n");
7634 return rc;
7635 }
7636
7637 return 0;
7638}
7639
523224a3 7640static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 7641{
7642 int port = BP_PORT(bp);
7643 int func = BP_FUNC(bp);
619c5cb6 7644 int init_phase = PHASE_PF0 + func;
523224a3
DK		 7645 struct bnx2x_ilt *ilt = BP_ILT(bp);
7646 u16 cdu_ilt_start;
8badd27a 7647 u32 addr, val;
f4a66897 7648 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
89db4ad8 7649 int i, main_mem_width, rc;
34f80b04 7650
51c1a580 7651 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
34f80b04 7652
619c5cb6 7653 /* FLR cleanup - hmmm */
89db4ad8
AE		 7654 if (!CHIP_IS_E1x(bp)) {
7655 rc = bnx2x_pf_flr_clnup(bp);
04c46736
YM		 7656 if (rc) {
7657 bnx2x_fw_dump(bp);
89db4ad8 7658 return rc;
04c46736 7659 }
89db4ad8 7660 }
619c5cb6 7661
8badd27a 7662 /* set MSI reconfigure capability */
f2e0899f
DK		 7663 if (bp->common.int_block == INT_BLOCK_HC) {
7664 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7665 val = REG_RD(bp, addr);
7666 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7667 REG_WR(bp, addr, val);
7668 }
8badd27a 7669
619c5cb6
VZ		 7670 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7671 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7672
523224a3
DK		 7673 ilt = BP_ILT(bp);
7674 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 7675
290ca2bb
AE		 7676 if (IS_SRIOV(bp))
7677 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7678 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7679
7680 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7681 * those of the VFs, so start line should be reset
7682 */
7683 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
523224a3 7684 for (i = 0; i < L2_ILT_LINES(bp); i++) {
a052997e 7685 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
523224a3 7686 ilt->lines[cdu_ilt_start + i].page_mapping =
a052997e
MS		 7687 bp->context[i].cxt_mapping;
7688 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
37b091ba 7689 }
290ca2bb 7690
523224a3 7691 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 7692
55c11941
MS		 7693 if (!CONFIGURE_NIC_MODE(bp)) {
7694 bnx2x_init_searcher(bp);
7695 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7696 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7697 } else {
7698 /* Set NIC mode */
7699 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6bf07b8e 7700 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
55c11941 7701 }
37b091ba 7702
619c5cb6 7703 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7704 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7705
7706 /* Turn on a single ISR mode in IGU if driver is going to use
7707 * INT#x or MSI
7708 */
7709 if (!(bp->flags & USING_MSIX_FLAG))
7710 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7711 /*
7712 * Timers workaround bug: function init part.
7713 * Need to wait 20msec after initializing ILT,
7714 * needed to make sure there are no requests in
7715 * one of the PXP internal queues with "old" ILT addresses
7716 */
7717 msleep(20);
7718 /*
7719 * Master enable - Due to WB DMAE writes performed before this
7720 * register is re-initialized as part of the regular function
7721 * init
7722 */
7723 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7724 /* Enable the function in IGU */
7725 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7726 }
7727
523224a3 7728 bp->dmae_ready = 1;
34f80b04 7729
619c5cb6 7730 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 7731
619c5cb6 7732 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7733 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7734
619c5cb6
VZ		 7735 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7736 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7737 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7738 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7739 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7740 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7741 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7742 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7743 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7744 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7745 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7746 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7747 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7748
7749 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7750 REG_WR(bp, QM_REG_PF_EN, 1);
7751
619c5cb6
VZ		 7752 if (!CHIP_IS_E1x(bp)) {
7753 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7754 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7755 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7756 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7757 }
7758 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7759
7760 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7761 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
c19d65c9 7762 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
b56e9670
AE		 7763
7764 bnx2x_iov_init_dq(bp);
7765
619c5cb6
VZ		 7766 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7767 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7768 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7769 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7770 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7771 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7772 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7773 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7774 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7775 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7776 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7777
619c5cb6 7778 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 7779
619c5cb6 7780 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 7781
619c5cb6 7782 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7783 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7784
fb3bff17 7785 if (IS_MF(bp)) {
34f80b04 7786 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 7787 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 7788 }
7789
619c5cb6 7790 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 7791
34f80b04 7792 /* HC init per function */
f2e0899f
DK		 7793 if (bp->common.int_block == INT_BLOCK_HC) {
7794 if (CHIP_IS_E1H(bp)) {
7795 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7796
7797 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7798 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7799 }
619c5cb6 7800 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 7801
7802 } else {
7803 int num_segs, sb_idx, prod_offset;
7804
34f80b04
EG		 7805 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7806
619c5cb6 7807 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7808 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7809 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7810 }
7811
619c5cb6 7812 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7813
619c5cb6 7814 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7815 int dsb_idx = 0;
7816 /**
7817 * Producer memory:
7818 * E2 mode: address 0-135 match to the mapping memory;
7819 * 136 - PF0 default prod; 137 - PF1 default prod;
7820 * 138 - PF2 default prod; 139 - PF3 default prod;
7821 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7822 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7823 * 144-147 reserved.
7824 *
7825 * E1.5 mode - In backward compatible mode;
7826 * for non default SB; each even line in the memory
7827 * holds the U producer and each odd line hold
7828 * the C producer. The first 128 producers are for
7829 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7830 * producers are for the DSB for each PF.
7831 * Each PF has five segments: (the order inside each
7832 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7833 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7834 * 144-147 attn prods;
7835 */
7836 /* non-default-status-blocks */
7837 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7838 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7839 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7840 prod_offset = (bp->igu_base_sb + sb_idx) *
7841 num_segs;
7842
7843 for (i = 0; i < num_segs; i++) {
7844 addr = IGU_REG_PROD_CONS_MEMORY +
7845 (prod_offset + i) * 4;
7846 REG_WR(bp, addr, 0);
7847 }
7848 /* send consumer update with value 0 */
7849 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7850 USTORM_ID, 0, IGU_INT_NOP, 1);
7851 bnx2x_igu_clear_sb(bp,
7852 bp->igu_base_sb + sb_idx);
7853 }
7854
7855 /* default-status-blocks */
7856 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7857 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7858
7859 if (CHIP_MODE_IS_4_PORT(bp))
7860 dsb_idx = BP_FUNC(bp);
7861 else
3395a033 7862 dsb_idx = BP_VN(bp);
f2e0899f
DK		 7863
7864 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7865 IGU_BC_BASE_DSB_PROD + dsb_idx :
7866 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7867
3395a033
DK		 7868 /*
7869 * igu prods come in chunks of E1HVN_MAX (4) -
7870 * does not matters what is the current chip mode
7871 */
f2e0899f
DK		 7872 for (i = 0; i < (num_segs * E1HVN_MAX);
7873 i += E1HVN_MAX) {
7874 addr = IGU_REG_PROD_CONS_MEMORY +
7875 (prod_offset + i)*4;
7876 REG_WR(bp, addr, 0);
7877 }
7878 /* send consumer update with 0 */
7879 if (CHIP_INT_MODE_IS_BC(bp)) {
7880 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7881 USTORM_ID, 0, IGU_INT_NOP, 1);
7882 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7883 CSTORM_ID, 0, IGU_INT_NOP, 1);
7884 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7885 XSTORM_ID, 0, IGU_INT_NOP, 1);
7886 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7887 TSTORM_ID, 0, IGU_INT_NOP, 1);
7888 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7889 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7890 } else {
7891 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7892 USTORM_ID, 0, IGU_INT_NOP, 1);
7893 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7894 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7895 }
7896 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7897
16a5fd92 7898 /* !!! These should become driver const once
f2e0899f
DK		 7899 rf-tool supports split-68 const */
7900 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7901 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7902 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7903 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7904 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7905 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7906 }
34f80b04 7907 }
34f80b04 7908
c14423fe 7909 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 7910 REG_WR(bp, 0x2114, 0xffffffff);
7911 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 7912
f4a66897
VZ		 7913 if (CHIP_IS_E1x(bp)) {
7914 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7915 main_mem_base = HC_REG_MAIN_MEMORY +
7916 BP_PORT(bp) * (main_mem_size * 4);
7917 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7918 main_mem_width = 8;
7919
7920 val = REG_RD(bp, main_mem_prty_clr);
7921 if (val)
51c1a580
MS		 7922 DP(NETIF_MSG_HW,
7923 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7924 val);
f4a66897
VZ		 7925
7926 /* Clear "false" parity errors in MSI-X table */
7927 for (i = main_mem_base;
7928 i < main_mem_base + main_mem_size * 4;
7929 i += main_mem_width) {
7930 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7931 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7932 i, main_mem_width / 4);
7933 }
7934 /* Clear HC parity attention */
7935 REG_RD(bp, main_mem_prty_clr);
7936 }
7937
619c5cb6
VZ		 7938#ifdef BNX2X_STOP_ON_ERROR
7939 /* Enable STORMs SP logging */
7940 REG_WR8(bp, BAR_USTRORM_INTMEM +
7941 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7942 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7943 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7944 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7945 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7946 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7947 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7948#endif
7949
b7737c9b 7950 bnx2x_phy_probe(&bp->link_params);
f85582f8 7951
34f80b04
EG		 7952 return 0;
7953}
7954
55c11941
MS		 7955void bnx2x_free_mem_cnic(struct bnx2x *bp)
7956{
7957 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7958
7959 if (!CHIP_IS_E1x(bp))
7960 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7961 sizeof(struct host_hc_status_block_e2));
7962 else
7963 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7964 sizeof(struct host_hc_status_block_e1x));
7965
7966 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7967}
7968
9f6c9258 7969void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 7970{
a052997e
MS		 7971 int i;
7972
619c5cb6
VZ		 7973 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7974 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7975
b4cddbd6
AE		 7976 if (IS_VF(bp))
7977 return;
7978
7979 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7980 sizeof(struct host_sp_status_block));
7981
a2fbb9ea 7982 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 7983 sizeof(struct bnx2x_slowpath));
a2fbb9ea 7984
a052997e
MS		 7985 for (i = 0; i < L2_ILT_LINES(bp); i++)
7986 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7987 bp->context[i].size);
523224a3
DK		 7988 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7989
7990 BNX2X_FREE(bp->ilt->lines);
f85582f8 7991
7a9b2557 7992 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 7993
523224a3
DK		 7994 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7995 BCM_PAGE_SIZE * NUM_EQ_PAGES);
580d9d08 7996
05952246
YM		 7997 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7998
580d9d08 7999 bnx2x_iov_free_mem(bp);
619c5cb6
VZ		 8000}
8001
55c11941 8002int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
a2fbb9ea 8003{
cd2b0389 8004 if (!CHIP_IS_E1x(bp)) {
619c5cb6 8005 /* size = the status block + ramrod buffers */
cd2b0389
JP		 8006 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8007 sizeof(struct host_hc_status_block_e2));
8008 if (!bp->cnic_sb.e2_sb)
8009 goto alloc_mem_err;
8010 } else {
8011 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8012 sizeof(struct host_hc_status_block_e1x));
8013 if (!bp->cnic_sb.e1x_sb)
8014 goto alloc_mem_err;
8015 }
8badd27a 8016
cd2b0389 8017 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
16a5fd92 8018 /* allocate searcher T2 table, as it wasn't allocated before */
cd2b0389
JP		 8019 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8020 if (!bp->t2)
8021 goto alloc_mem_err;
8022 }
55c11941
MS		 8023
8024 /* write address to which L5 should insert its values */
8025 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8026 &bp->slowpath->drv_info_to_mcp;
8027
8028 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8029 goto alloc_mem_err;
8030
8031 return 0;
8032
8033alloc_mem_err:
8034 bnx2x_free_mem_cnic(bp);
8035 BNX2X_ERR("Can't allocate memory\n");
8036 return -ENOMEM;
8037}
8038
8039int bnx2x_alloc_mem(struct bnx2x *bp)
8040{
8041 int i, allocated, context_size;
a2fbb9ea 8042
cd2b0389 8043 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
55c11941 8044 /* allocate searcher T2 table */
cd2b0389
JP		 8045 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8046 if (!bp->t2)
8047 goto alloc_mem_err;
8048 }
8badd27a 8049
cd2b0389
JP		 8050 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8051 sizeof(struct host_sp_status_block));
8052 if (!bp->def_status_blk)
8053 goto alloc_mem_err;
a2fbb9ea 8054
cd2b0389
JP		 8055 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8056 sizeof(struct bnx2x_slowpath));
8057 if (!bp->slowpath)
8058 goto alloc_mem_err;
a2fbb9ea 8059
a052997e
MS		 8060 /* Allocate memory for CDU context:
8061 * This memory is allocated separately and not in the generic ILT
8062 * functions because CDU differs in few aspects:
8063 * 1. There are multiple entities allocating memory for context -
8064 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8065 * its own ILT lines.
8066 * 2. Since CDU page-size is not a single 4KB page (which is the case
8067 * for the other ILT clients), to be efficient we want to support
8068 * allocation of sub-page-size in the last entry.
8069 * 3. Context pointers are used by the driver to pass to FW / update
8070 * the context (for the other ILT clients the pointers are used just to
8071 * free the memory during unload).
8072 */
8073 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
65abd74d 8074
a052997e
MS		 8075 for (i = 0, allocated = 0; allocated < context_size; i++) {
8076 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8077 (context_size - allocated));
cd2b0389
JP		 8078 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8079 bp->context[i].size);
8080 if (!bp->context[i].vcxt)
8081 goto alloc_mem_err;
a052997e
MS		 8082 allocated += bp->context[i].size;
8083 }
cd2b0389
JP		 8084 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8085 GFP_KERNEL);
8086 if (!bp->ilt->lines)
8087 goto alloc_mem_err;
65abd74d 8088
523224a3
DK		 8089 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8090 goto alloc_mem_err;
65abd74d 8091
67c431a5
AE		 8092 if (bnx2x_iov_alloc_mem(bp))
8093 goto alloc_mem_err;
8094
9f6c9258 8095 /* Slow path ring */
cd2b0389
JP		 8096 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8097 if (!bp->spq)
8098 goto alloc_mem_err;
65abd74d 8099
523224a3 8100 /* EQ */
cd2b0389
JP		 8101 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8102 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8103 if (!bp->eq_ring)
8104 goto alloc_mem_err;
ab532cf3 8105
9f6c9258 8106 return 0;
e1510706 8107
9f6c9258
DK		 8108alloc_mem_err:
8109 bnx2x_free_mem(bp);
51c1a580 8110 BNX2X_ERR("Can't allocate memory\n");
9f6c9258 8111 return -ENOMEM;
65abd74d
YG		 8112}
8113
a2fbb9ea
ET		 8114/*
8115 * Init service functions
8116 */
a2fbb9ea 8117
619c5cb6
VZ		 8118int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8119 struct bnx2x_vlan_mac_obj *obj, bool set,
8120 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 8121{
619c5cb6
VZ		 8122 int rc;
8123 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 8124
619c5cb6 8125 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 8126
619c5cb6
VZ		 8127 /* Fill general parameters */
8128 ramrod_param.vlan_mac_obj = obj;
8129 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 8130
619c5cb6
VZ		 8131 /* Fill a user request section if needed */
8132 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8133 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 8134
619c5cb6 8135 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 8136
619c5cb6
VZ		 8137 /* Set the command: ADD or DEL */
8138 if (set)
8139 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8140 else
8141 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 8142 }
8143
619c5cb6 8144 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7b5342d9
YM		 8145
8146 if (rc == -EEXIST) {
8147 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8148 /* do not treat adding same MAC as error */
8149 rc = 0;
8150 } else if (rc < 0)
619c5cb6 8151 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7b5342d9 8152
619c5cb6 8153 return rc;
a2fbb9ea
ET		 8154}
8155
619c5cb6
VZ		 8156int bnx2x_del_all_macs(struct bnx2x *bp,
8157 struct bnx2x_vlan_mac_obj *mac_obj,
8158 int mac_type, bool wait_for_comp)
e665bfda 8159{
619c5cb6
VZ		 8160 int rc;
8161 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 8162
619c5cb6
VZ		 8163 /* Wait for completion of requested */
8164 if (wait_for_comp)
8165 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 8166
619c5cb6
VZ		 8167 /* Set the mac type of addresses we want to clear */
8168 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 8169
619c5cb6
VZ		 8170 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8171 if (rc < 0)
8172 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 8173
619c5cb6 8174 return rc;
0793f83f
DK		 8175}
8176
619c5cb6 8177int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 8178{
a3348722
BW		 8179 if (is_zero_ether_addr(bp->dev->dev_addr) &&
8180 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
51c1a580
MS		 8181 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8182 "Ignoring Zero MAC for STORAGE SD mode\n");
614c76df
DK		 8183 return 0;
8184 }
614c76df 8185
f8f4f61a
DK		 8186 if (IS_PF(bp)) {
8187 unsigned long ramrod_flags = 0;
0793f83f 8188
f8f4f61a
DK		 8189 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8190 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8191 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8192 &bp->sp_objs->mac_obj, set,
8193 BNX2X_ETH_MAC, &ramrod_flags);
8194 } else { /* vf */
8195 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8196 bp->fp->index, true);
8197 }
e665bfda 8198}
6e30dd4e 8199
619c5cb6 8200int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 8201{
60cad4e6
AE		 8202 if (IS_PF(bp))
8203 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8204 else /* VF */
8205 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
993ac7b5 8206}
a2fbb9ea 8207
d6214d7a 8208/**
e8920674 8209 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 8210 *
e8920674 8211 * @bp: driver handle
d6214d7a 8212 *
e8920674 8213 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 8214 */
1ab4434c 8215int bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 8216{
1ab4434c
AE		 8217 int rc = 0;
8218
60cad4e6
AE		 8219 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8220 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
1ab4434c 8221 return -EINVAL;
60cad4e6 8222 }
1ab4434c 8223
9ee3d37b 8224 switch (int_mode) {
1ab4434c
AE		 8225 case BNX2X_INT_MODE_MSIX:
8226 /* attempt to enable msix */
8227 rc = bnx2x_enable_msix(bp);
8228
8229 /* msix attained */
8230 if (!rc)
8231 return 0;
8232
8233 /* vfs use only msix */
8234 if (rc && IS_VF(bp))
8235 return rc;
8236
8237 /* failed to enable multiple MSI-X */
8238 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8239 bp->num_queues,
8240 1 + bp->num_cnic_queues);
8241
8242 /* falling through... */
8243 case BNX2X_INT_MODE_MSI:
d6214d7a 8244 bnx2x_enable_msi(bp);
1ab4434c 8245
d6214d7a 8246 /* falling through... */
1ab4434c 8247 case BNX2X_INT_MODE_INTX:
55c11941
MS		 8248 bp->num_ethernet_queues = 1;
8249 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
51c1a580 8250 BNX2X_DEV_INFO("set number of queues to 1\n");
ca00392c 8251 break;
d6214d7a 8252 default:
1ab4434c
AE		 8253 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8254 return -EINVAL;
9f6c9258 8255 }
1ab4434c 8256 return 0;
a2fbb9ea
ET		 8257}
8258
1ab4434c 8259/* must be called prior to any HW initializations */
c2bff63f
DK		 8260static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8261{
290ca2bb
AE		 8262 if (IS_SRIOV(bp))
8263 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
c2bff63f
DK		 8264 return L2_ILT_LINES(bp);
8265}
8266
523224a3
DK		 8267void bnx2x_ilt_set_info(struct bnx2x *bp)
8268{
8269 struct ilt_client_info *ilt_client;
8270 struct bnx2x_ilt *ilt = BP_ILT(bp);
8271 u16 line = 0;
8272
8273 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8274 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8275
8276 /* CDU */
8277 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8278 ilt_client->client_num = ILT_CLIENT_CDU;
8279 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8280 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8281 ilt_client->start = line;
619c5cb6 8282 line += bnx2x_cid_ilt_lines(bp);
55c11941
MS		 8283
8284 if (CNIC_SUPPORT(bp))
8285 line += CNIC_ILT_LINES;
523224a3
DK		 8286 ilt_client->end = line - 1;
8287
51c1a580 8288 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8289 ilt_client->start,
8290 ilt_client->end,
8291 ilt_client->page_size,
8292 ilt_client->flags,
8293 ilog2(ilt_client->page_size >> 12));
8294
8295 /* QM */
8296 if (QM_INIT(bp->qm_cid_count)) {
8297 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8298 ilt_client->client_num = ILT_CLIENT_QM;
8299 ilt_client->page_size = QM_ILT_PAGE_SZ;
8300 ilt_client->flags = 0;
8301 ilt_client->start = line;
8302
8303 /* 4 bytes for each cid */
8304 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8305 QM_ILT_PAGE_SZ);
8306
8307 ilt_client->end = line - 1;
8308
51c1a580
MS		 8309 DP(NETIF_MSG_IFUP,
8310 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8311 ilt_client->start,
8312 ilt_client->end,
8313 ilt_client->page_size,
8314 ilt_client->flags,
8315 ilog2(ilt_client->page_size >> 12));
523224a3 8316 }
523224a3 8317
55c11941
MS		 8318 if (CNIC_SUPPORT(bp)) {
8319 /* SRC */
8320 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8321 ilt_client->client_num = ILT_CLIENT_SRC;
8322 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8323 ilt_client->flags = 0;
8324 ilt_client->start = line;
8325 line += SRC_ILT_LINES;
8326 ilt_client->end = line - 1;
523224a3 8327
55c11941
MS		 8328 DP(NETIF_MSG_IFUP,
8329 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8330 ilt_client->start,
8331 ilt_client->end,
8332 ilt_client->page_size,
8333 ilt_client->flags,
8334 ilog2(ilt_client->page_size >> 12));
9f6c9258 8335
55c11941
MS		 8336 /* TM */
8337 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8338 ilt_client->client_num = ILT_CLIENT_TM;
8339 ilt_client->page_size = TM_ILT_PAGE_SZ;
8340 ilt_client->flags = 0;
8341 ilt_client->start = line;
8342 line += TM_ILT_LINES;
8343 ilt_client->end = line - 1;
523224a3 8344
55c11941
MS		 8345 DP(NETIF_MSG_IFUP,
8346 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8347 ilt_client->start,
8348 ilt_client->end,
8349 ilt_client->page_size,
8350 ilt_client->flags,
8351 ilog2(ilt_client->page_size >> 12));
8352 }
9f6c9258 8353
619c5cb6 8354 BUG_ON(line > ILT_MAX_LINES);
523224a3 8355}
f85582f8 8356
619c5cb6
VZ		 8357/**
8358 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8359 *
8360 * @bp: driver handle
8361 * @fp: pointer to fastpath
8362 * @init_params: pointer to parameters structure
8363 *
8364 * parameters configured:
8365 * - HC configuration
8366 * - Queue's CDU context
8367 */
1191cb83 8368static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
619c5cb6 8369 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 8370{
6383c0b3 8371 u8 cos;
a052997e
MS		 8372 int cxt_index, cxt_offset;
8373
619c5cb6
VZ		 8374 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8375 if (!IS_FCOE_FP(fp)) {
8376 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8377 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8378
16a5fd92 8379 /* If HC is supported, enable host coalescing in the transition
619c5cb6
VZ		 8380 * to INIT state.
8381 */
8382 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8383 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8384
8385 /* HC rate */
8386 init_params->rx.hc_rate = bp->rx_ticks ?
8387 (1000000 / bp->rx_ticks) : 0;
8388 init_params->tx.hc_rate = bp->tx_ticks ?
8389 (1000000 / bp->tx_ticks) : 0;
8390
8391 /* FW SB ID */
8392 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8393 fp->fw_sb_id;
8394
8395 /*
8396 * CQ index among the SB indices: FCoE clients uses the default
8397 * SB, therefore it's different.
8398 */
6383c0b3
AE		 8399 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8400 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 8401 }
8402
6383c0b3
AE		 8403 /* set maximum number of COSs supported by this queue */
8404 init_params->max_cos = fp->max_cos;
8405
51c1a580 8406 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 8407 fp->index, init_params->max_cos);
8408
8409 /* set the context pointers queue object */
a052997e 8410 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
65565884
MS		 8411 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8412 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
a052997e 8413 ILT_PAGE_CIDS);
6383c0b3 8414 init_params->cxts[cos] =
a052997e
MS		 8415 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8416 }
619c5cb6
VZ		 8417}
8418
910cc727 8419static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6383c0b3
AE		 8420 struct bnx2x_queue_state_params *q_params,
8421 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8422 int tx_index, bool leading)
8423{
8424 memset(tx_only_params, 0, sizeof(*tx_only_params));
8425
8426 /* Set the command */
8427 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8428
8429 /* Set tx-only QUEUE flags: don't zero statistics */
8430 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8431
8432 /* choose the index of the cid to send the slow path on */
8433 tx_only_params->cid_index = tx_index;
8434
8435 /* Set general TX_ONLY_SETUP parameters */
8436 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8437
8438 /* Set Tx TX_ONLY_SETUP parameters */
8439 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8440
51c1a580
MS		 8441 DP(NETIF_MSG_IFUP,
8442 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 8443 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8444 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8445 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8446
8447 /* send the ramrod */
8448 return bnx2x_queue_state_change(bp, q_params);
8449}
8450
619c5cb6
VZ		 8451/**
8452 * bnx2x_setup_queue - setup queue
8453 *
8454 * @bp: driver handle
8455 * @fp: pointer to fastpath
8456 * @leading: is leading
8457 *
8458 * This function performs 2 steps in a Queue state machine
8459 * actually: 1) RESET->INIT 2) INIT->SETUP
8460 */
8461
8462int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8463 bool leading)
8464{
3b603066 8465 struct bnx2x_queue_state_params q_params = {NULL};
619c5cb6
VZ		 8466 struct bnx2x_queue_setup_params *setup_params =
8467 &q_params.params.setup;
6383c0b3
AE		 8468 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8469 &q_params.params.tx_only;
a2fbb9ea 8470 int rc;
6383c0b3
AE		 8471 u8 tx_index;
8472
51c1a580 8473 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
a2fbb9ea 8474
ec6ba945
VZ		 8475 /* reset IGU state skip FCoE L2 queue */
8476 if (!IS_FCOE_FP(fp))
8477 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 8478 IGU_INT_ENABLE, 0);
a2fbb9ea 8479
15192a8c 8480 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8481 /* We want to wait for completion in this context */
8482 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8483
619c5cb6
VZ		 8484 /* Prepare the INIT parameters */
8485 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 8486
619c5cb6
VZ		 8487 /* Set the command */
8488 q_params.cmd = BNX2X_Q_CMD_INIT;
8489
8490 /* Change the state to INIT */
8491 rc = bnx2x_queue_state_change(bp, &q_params);
8492 if (rc) {
6383c0b3 8493 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 8494 return rc;
8495 }
ec6ba945 8496
51c1a580 8497 DP(NETIF_MSG_IFUP, "init complete\n");
6383c0b3 8498
619c5cb6
VZ		 8499 /* Now move the Queue to the SETUP state... */
8500 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 8501
619c5cb6
VZ		 8502 /* Set QUEUE flags */
8503 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 8504
619c5cb6 8505 /* Set general SETUP parameters */
6383c0b3
AE		 8506 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8507 FIRST_TX_COS_INDEX);
619c5cb6 8508
6383c0b3 8509 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 8510 &setup_params->rxq_params);
8511
6383c0b3
AE		 8512 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8513 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 8514
8515 /* Set the command */
8516 q_params.cmd = BNX2X_Q_CMD_SETUP;
8517
55c11941
MS		 8518 if (IS_FCOE_FP(fp))
8519 bp->fcoe_init = true;
8520
619c5cb6
VZ		 8521 /* Change the state to SETUP */
8522 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 8523 if (rc) {
8524 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8525 return rc;
8526 }
8527
8528 /* loop through the relevant tx-only indices */
8529 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8530 tx_index < fp->max_cos;
8531 tx_index++) {
8532
8533 /* prepare and send tx-only ramrod*/
8534 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8535 tx_only_params, tx_index, leading);
8536 if (rc) {
8537 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8538 fp->index, tx_index);
8539 return rc;
8540 }
8541 }
523224a3 8542
34f80b04 8543 return rc;
a2fbb9ea
ET		 8544}
8545
619c5cb6 8546static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 8547{
619c5cb6 8548 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 8549 struct bnx2x_fp_txdata *txdata;
3b603066 8550 struct bnx2x_queue_state_params q_params = {NULL};
6383c0b3
AE		 8551 int rc, tx_index;
8552
51c1a580 8553 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 8554
15192a8c 8555 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8556 /* We want to wait for completion in this context */
8557 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8558
6383c0b3
AE		 8559 /* close tx-only connections */
8560 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8561 tx_index < fp->max_cos;
8562 tx_index++){
8563
8564 /* ascertain this is a normal queue*/
65565884 8565 txdata = fp->txdata_ptr[tx_index];
6383c0b3 8566
51c1a580 8567 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
6383c0b3
AE		 8568 txdata->txq_index);
8569
8570 /* send halt terminate on tx-only connection */
8571 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8572 memset(&q_params.params.terminate, 0,
8573 sizeof(q_params.params.terminate));
8574 q_params.params.terminate.cid_index = tx_index;
8575
8576 rc = bnx2x_queue_state_change(bp, &q_params);
8577 if (rc)
8578 return rc;
8579
8580 /* send halt terminate on tx-only connection */
8581 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8582 memset(&q_params.params.cfc_del, 0,
8583 sizeof(q_params.params.cfc_del));
8584 q_params.params.cfc_del.cid_index = tx_index;
8585 rc = bnx2x_queue_state_change(bp, &q_params);
8586 if (rc)
8587 return rc;
8588 }
8589 /* Stop the primary connection: */
8590 /* ...halt the connection */
619c5cb6
VZ		 8591 q_params.cmd = BNX2X_Q_CMD_HALT;
8592 rc = bnx2x_queue_state_change(bp, &q_params);
8593 if (rc)
da5a662a 8594 return rc;
a2fbb9ea 8595
6383c0b3 8596 /* ...terminate the connection */
619c5cb6 8597 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 8598 memset(&q_params.params.terminate, 0,
8599 sizeof(q_params.params.terminate));
8600 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 8601 rc = bnx2x_queue_state_change(bp, &q_params);
8602 if (rc)
523224a3 8603 return rc;
6383c0b3 8604 /* ...delete cfc entry */
619c5cb6 8605 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 8606 memset(&q_params.params.cfc_del, 0,
8607 sizeof(q_params.params.cfc_del));
8608 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 8609 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 8610}
8611
34f80b04
EG		 8612static void bnx2x_reset_func(struct bnx2x *bp)
8613{
8614 int port = BP_PORT(bp);
8615 int func = BP_FUNC(bp);
f2e0899f 8616 int i;
523224a3
DK		 8617
8618 /* Disable the function in the FW */
8619 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8620 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8621 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8622 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8623
8624 /* FP SBs */
ec6ba945 8625 for_each_eth_queue(bp, i) {
523224a3 8626 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 8627 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 8628 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8629 SB_DISABLED);
523224a3
DK		 8630 }
8631
55c11941
MS		 8632 if (CNIC_LOADED(bp))
8633 /* CNIC SB */
8634 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8635 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8636 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8637
523224a3 8638 /* SP SB */
619c5cb6 8639 REG_WR8(bp, BAR_CSTRORM_INTMEM +
2de67439
YM		 8640 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8641 SB_DISABLED);
523224a3
DK		 8642
8643 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8644 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8645 0);
34f80b04
EG		 8646
8647 /* Configure IGU */
f2e0899f
DK		 8648 if (bp->common.int_block == INT_BLOCK_HC) {
8649 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8650 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8651 } else {
8652 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8653 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8654 }
34f80b04 8655
55c11941
MS		 8656 if (CNIC_LOADED(bp)) {
8657 /* Disable Timer scan */
8658 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8659 /*
8660 * Wait for at least 10ms and up to 2 second for the timers
8661 * scan to complete
8662 */
8663 for (i = 0; i < 200; i++) {
639d65b8 8664 usleep_range(10000, 20000);
55c11941
MS		 8665 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8666 break;
8667 }
37b091ba 8668 }
34f80b04 8669 /* Clear ILT */
f2e0899f
DK		 8670 bnx2x_clear_func_ilt(bp, func);
8671
8672 /* Timers workaround bug for E2: if this is vnic-3,
8673 * we need to set the entire ilt range for this timers.
8674 */
619c5cb6 8675 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 8676 struct ilt_client_info ilt_cli;
8677 /* use dummy TM client */
8678 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8679 ilt_cli.start = 0;
8680 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8681 ilt_cli.client_num = ILT_CLIENT_TM;
8682
8683 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8684 }
8685
8686 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 8687 if (!CHIP_IS_E1x(bp))
f2e0899f 8688 bnx2x_pf_disable(bp);
523224a3
DK		 8689
8690 bp->dmae_ready = 0;
34f80b04
EG		 8691}
8692
8693static void bnx2x_reset_port(struct bnx2x *bp)
8694{
8695 int port = BP_PORT(bp);
8696 u32 val;
8697
619c5cb6
VZ		 8698 /* Reset physical Link */
8699 bnx2x__link_reset(bp);
8700
34f80b04
EG		 8701 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8702
8703 /* Do not rcv packets to BRB */
8704 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8705 /* Do not direct rcv packets that are not for MCP to the BRB */
8706 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8707 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8708
8709 /* Configure AEU */
8710 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8711
8712 msleep(100);
8713 /* Check for BRB port occupancy */
8714 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8715 if (val)
8716 DP(NETIF_MSG_IFDOWN,
33471629 8717 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 8718
8719 /* TODO: Close Doorbell port? */
8720}
8721
1191cb83 8722static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 8723{
3b603066 8724 struct bnx2x_func_state_params func_params = {NULL};
34f80b04 8725
619c5cb6
VZ		 8726 /* Prepare parameters for function state transitions */
8727 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 8728
619c5cb6
VZ		 8729 func_params.f_obj = &bp->func_obj;
8730 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 8731
619c5cb6 8732 func_params.params.hw_init.load_phase = load_code;
49d66772 8733
619c5cb6 8734 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 8735}
8736
1191cb83 8737static int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 8738{
3b603066 8739 struct bnx2x_func_state_params func_params = {NULL};
619c5cb6 8740 int rc;
228241eb 8741
619c5cb6
VZ		 8742 /* Prepare parameters for function state transitions */
8743 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8744 func_params.f_obj = &bp->func_obj;
8745 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 8746
619c5cb6
VZ		 8747 /*
8748 * Try to stop the function the 'good way'. If fails (in case
8749 * of a parity error during bnx2x_chip_cleanup()) and we are
8750 * not in a debug mode, perform a state transaction in order to
8751 * enable further HW_RESET transaction.
8752 */
8753 rc = bnx2x_func_state_change(bp, &func_params);
8754 if (rc) {
34f80b04 8755#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 8756 return rc;
34f80b04 8757#else
51c1a580 8758 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
619c5cb6
VZ		 8759 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8760 return bnx2x_func_state_change(bp, &func_params);
34f80b04 8761#endif
228241eb 8762 }
a2fbb9ea 8763
619c5cb6
VZ		 8764 return 0;
8765}
523224a3 8766
619c5cb6
VZ		 8767/**
8768 * bnx2x_send_unload_req - request unload mode from the MCP.
8769 *
8770 * @bp: driver handle
8771 * @unload_mode: requested function's unload mode
8772 *
8773 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8774 */
8775u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8776{
8777 u32 reset_code = 0;
8778 int port = BP_PORT(bp);
3101c2bc 8779
619c5cb6 8780 /* Select the UNLOAD request mode */
65abd74d
YG		 8781 if (unload_mode == UNLOAD_NORMAL)
8782 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8783
7d0446c2 8784 else if (bp->flags & NO_WOL_FLAG)
65abd74d 8785 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 8786
7d0446c2 8787 else if (bp->wol) {
65abd74d
YG		 8788 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8789 u8 *mac_addr = bp->dev->dev_addr;
29ed74c3 8790 struct pci_dev *pdev = bp->pdev;
65abd74d 8791 u32 val;
f9977903
DK		 8792 u16 pmc;
8793
65abd74d 8794 /* The mac address is written to entries 1-4 to
f9977903
DK		 8795 * preserve entry 0 which is used by the PMF
8796 */
3395a033 8797 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 8798
8799 val = (mac_addr[0] << 8) | mac_addr[1];
8800 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8801
8802 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8803 (mac_addr[4] << 8) | mac_addr[5];
8804 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8805
f9977903 8806 /* Enable the PME and clear the status */
29ed74c3 8807 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
f9977903 8808 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
29ed74c3 8809 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
f9977903 8810
65abd74d
YG		 8811 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8812
8813 } else
8814 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 8815
619c5cb6
VZ		 8816 /* Send the request to the MCP */
8817 if (!BP_NOMCP(bp))
8818 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8819 else {
8820 int path = BP_PATH(bp);
8821
51c1a580 8822 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
a8f47eb7 8823 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8824 bnx2x_load_count[path][2]);
8825 bnx2x_load_count[path][0]--;
8826 bnx2x_load_count[path][1 + port]--;
51c1a580 8827 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
a8f47eb7 8828 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8829 bnx2x_load_count[path][2]);
8830 if (bnx2x_load_count[path][0] == 0)
619c5cb6 8831 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
a8f47eb7 8832 else if (bnx2x_load_count[path][1 + port] == 0)
619c5cb6
VZ		 8833 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8834 else
8835 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8836 }
8837
8838 return reset_code;
8839}
8840
8841/**
8842 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8843 *
8844 * @bp: driver handle
5d07d868 8845 * @keep_link: true iff link should be kept up
619c5cb6 8846 */
5d07d868 8847void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
619c5cb6 8848{
5d07d868
YM		 8849 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8850
619c5cb6
VZ		 8851 /* Report UNLOAD_DONE to MCP */
8852 if (!BP_NOMCP(bp))
5d07d868 8853 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
619c5cb6
VZ		 8854}
8855
1191cb83 8856static int bnx2x_func_wait_started(struct bnx2x *bp)
6debea87
DK		 8857{
8858 int tout = 50;
8859 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8860
8861 if (!bp->port.pmf)
8862 return 0;
8863
8864 /*
8865 * (assumption: No Attention from MCP at this stage)
16a5fd92 8866 * PMF probably in the middle of TX disable/enable transaction
6debea87 8867 * 1. Sync IRS for default SB
16a5fd92
YM		 8868 * 2. Sync SP queue - this guarantees us that attention handling started
8869 * 3. Wait, that TX disable/enable transaction completes
6debea87 8870 *
16a5fd92
YM		 8871 * 1+2 guarantee that if DCBx attention was scheduled it already changed
8872 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
8873 * received completion for the transaction the state is TX_STOPPED.
6debea87
DK		 8874 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8875 * transaction.
8876 */
8877
8878 /* make sure default SB ISR is done */
8879 if (msix)
8880 synchronize_irq(bp->msix_table[0].vector);
8881 else
8882 synchronize_irq(bp->pdev->irq);
8883
8884 flush_workqueue(bnx2x_wq);
8885
8886 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8887 BNX2X_F_STATE_STARTED && tout--)
8888 msleep(20);
8889
8890 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8891 BNX2X_F_STATE_STARTED) {
8892#ifdef BNX2X_STOP_ON_ERROR
51c1a580 8893 BNX2X_ERR("Wrong function state\n");
6debea87
DK		 8894 return -EBUSY;
8895#else
8896 /*
8897 * Failed to complete the transaction in a "good way"
8898 * Force both transactions with CLR bit
8899 */
3b603066 8900 struct bnx2x_func_state_params func_params = {NULL};
6debea87 8901
51c1a580 8902 DP(NETIF_MSG_IFDOWN,
6bf07b8e 8903 "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
6debea87
DK		 8904
8905 func_params.f_obj = &bp->func_obj;
8906 __set_bit(RAMROD_DRV_CLR_ONLY,
8907 &func_params.ramrod_flags);
8908
8909 /* STARTED-->TX_ST0PPED */
8910 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8911 bnx2x_func_state_change(bp, &func_params);
8912
8913 /* TX_ST0PPED-->STARTED */
8914 func_params.cmd = BNX2X_F_CMD_TX_START;
8915 return bnx2x_func_state_change(bp, &func_params);
8916#endif
8917 }
8918
8919 return 0;
8920}
8921
5d07d868 8922void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
619c5cb6
VZ		 8923{
8924 int port = BP_PORT(bp);
6383c0b3
AE		 8925 int i, rc = 0;
8926 u8 cos;
3b603066 8927 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6
VZ		 8928 u32 reset_code;
8929
8930 /* Wait until tx fastpath tasks complete */
8931 for_each_tx_queue(bp, i) {
8932 struct bnx2x_fastpath *fp = &bp->fp[i];
8933
6383c0b3 8934 for_each_cos_in_tx_queue(fp, cos)
65565884 8935 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
619c5cb6
VZ		 8936#ifdef BNX2X_STOP_ON_ERROR
8937 if (rc)
8938 return;
8939#endif
8940 }
8941
8942 /* Give HW time to discard old tx messages */
0926d499 8943 usleep_range(1000, 2000);
619c5cb6
VZ		 8944
8945 /* Clean all ETH MACs */
15192a8c
BW		 8946 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8947 false);
619c5cb6
VZ		 8948 if (rc < 0)
8949 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8950
8951 /* Clean up UC list */
15192a8c 8952 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
619c5cb6
VZ		 8953 true);
8954 if (rc < 0)
51c1a580
MS		 8955 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8956 rc);
619c5cb6
VZ		 8957
8958 /* Disable LLH */
8959 if (!CHIP_IS_E1(bp))
8960 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8961
8962 /* Set "drop all" (stop Rx).
8963 * We need to take a netif_addr_lock() here in order to prevent
8964 * a race between the completion code and this code.
8965 */
8966 netif_addr_lock_bh(bp->dev);
8967 /* Schedule the rx_mode command */
8968 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8969 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8970 else
8971 bnx2x_set_storm_rx_mode(bp);
8972
8973 /* Cleanup multicast configuration */
8974 rparam.mcast_obj = &bp->mcast_obj;
8975 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8976 if (rc < 0)
8977 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8978
8979 netif_addr_unlock_bh(bp->dev);
8980
f1929b01 8981 bnx2x_iov_chip_cleanup(bp);
619c5cb6 8982
6debea87
DK		 8983 /*
8984 * Send the UNLOAD_REQUEST to the MCP. This will return if
8985 * this function should perform FUNC, PORT or COMMON HW
8986 * reset.
8987 */
8988 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8989
8990 /*
8991 * (assumption: No Attention from MCP at this stage)
16a5fd92 8992 * PMF probably in the middle of TX disable/enable transaction
6debea87
DK		 8993 */
8994 rc = bnx2x_func_wait_started(bp);
8995 if (rc) {
8996 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8997#ifdef BNX2X_STOP_ON_ERROR
8998 return;
8999#endif
9000 }
9001
34f80b04 9002 /* Close multi and leading connections
619c5cb6
VZ		 9003 * Completions for ramrods are collected in a synchronous way
9004 */
55c11941 9005 for_each_eth_queue(bp, i)
619c5cb6 9006 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 9007#ifdef BNX2X_STOP_ON_ERROR
9008 return;
9009#else
228241eb 9010 goto unload_error;
523224a3 9011#endif
55c11941
MS		 9012
9013 if (CNIC_LOADED(bp)) {
9014 for_each_cnic_queue(bp, i)
9015 if (bnx2x_stop_queue(bp, i))
9016#ifdef BNX2X_STOP_ON_ERROR
9017 return;
9018#else
9019 goto unload_error;
9020#endif
9021 }
9022
619c5cb6
VZ		 9023 /* If SP settings didn't get completed so far - something
9024 * very wrong has happen.
9025 */
9026 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9027 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 9028
619c5cb6
VZ		 9029#ifndef BNX2X_STOP_ON_ERROR
9030unload_error:
9031#endif
523224a3 9032 rc = bnx2x_func_stop(bp);
da5a662a 9033 if (rc) {
523224a3 9034 BNX2X_ERR("Function stop failed!\n");
da5a662a 9035#ifdef BNX2X_STOP_ON_ERROR
523224a3 9036 return;
523224a3 9037#endif
34f80b04 9038 }
a2fbb9ea 9039
523224a3
DK		 9040 /* Disable HW interrupts, NAPI */
9041 bnx2x_netif_stop(bp, 1);
26614ba5
MS		 9042 /* Delete all NAPI objects */
9043 bnx2x_del_all_napi(bp);
55c11941
MS		 9044 if (CNIC_LOADED(bp))
9045 bnx2x_del_all_napi_cnic(bp);
523224a3
DK		 9046
9047 /* Release IRQs */
d6214d7a 9048 bnx2x_free_irq(bp);
523224a3 9049
a2fbb9ea 9050 /* Reset the chip */
619c5cb6
VZ		 9051 rc = bnx2x_reset_hw(bp, reset_code);
9052 if (rc)
9053 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 9054
619c5cb6 9055 /* Report UNLOAD_DONE to MCP */
5d07d868 9056 bnx2x_send_unload_done(bp, keep_link);
72fd0718
VZ		 9057}
9058
9f6c9258 9059void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 9060{
9061 u32 val;
9062
51c1a580 9063 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
72fd0718
VZ		 9064
9065 if (CHIP_IS_E1(bp)) {
9066 int port = BP_PORT(bp);
9067 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9068 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9069
9070 val = REG_RD(bp, addr);
9071 val &= ~(0x300);
9072 REG_WR(bp, addr, val);
619c5cb6 9073 } else {
72fd0718
VZ		 9074 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9075 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9076 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9077 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9078 }
9079}
9080
72fd0718
VZ		 9081/* Close gates #2, #3 and #4: */
9082static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9083{
c9ee9206 9084 u32 val;
72fd0718
VZ		 9085
9086 /* Gates #2 and #4a are closed/opened for "not E1" only */
9087 if (!CHIP_IS_E1(bp)) {
9088 /* #4 */
c9ee9206 9089 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 9090 /* #2 */
c9ee9206 9091 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 9092 }
9093
9094 /* #3 */
c9ee9206
VZ		 9095 if (CHIP_IS_E1x(bp)) {
9096 /* Prevent interrupts from HC on both ports */
9097 val = REG_RD(bp, HC_REG_CONFIG_1);
9098 REG_WR(bp, HC_REG_CONFIG_1,
9099 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9100 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9101
9102 val = REG_RD(bp, HC_REG_CONFIG_0);
9103 REG_WR(bp, HC_REG_CONFIG_0,
9104 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9105 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9106 } else {
d82603c6 9107 /* Prevent incoming interrupts in IGU */
c9ee9206
VZ		 9108 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9109
9110 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9111 (!close) ?
9112 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9113 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9114 }
72fd0718 9115
51c1a580 9116 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
72fd0718
VZ		 9117 close ? "closing" : "opening");
9118 mmiowb();
9119}
9120
9121#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9122
9123static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9124{
9125 /* Do some magic... */
9126 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9127 *magic_val = val & SHARED_MF_CLP_MAGIC;
9128 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9129}
9130
e8920674
DK		 9131/**
9132 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 9133 *
e8920674
DK		 9134 * @bp: driver handle
9135 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 9136 */
9137static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9138{
9139 /* Restore the `magic' bit value... */
72fd0718
VZ		 9140 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9141 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9142 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9143}
9144
f85582f8 9145/**
e8920674 9146 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 9147 *
e8920674
DK		 9148 * @bp: driver handle
9149 * @magic_val: old value of 'magic' bit.
9150 *
9151 * Takes care of CLP configurations.
72fd0718
VZ		 9152 */
9153static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9154{
9155 u32 shmem;
9156 u32 validity_offset;
9157
51c1a580 9158 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
72fd0718
VZ		 9159
9160 /* Set `magic' bit in order to save MF config */
9161 if (!CHIP_IS_E1(bp))
9162 bnx2x_clp_reset_prep(bp, magic_val);
9163
9164 /* Get shmem offset */
9165 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
c55e771b
BW		 9166 validity_offset =
9167 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
72fd0718
VZ		 9168
9169 /* Clear validity map flags */
9170 if (shmem > 0)
9171 REG_WR(bp, shmem + validity_offset, 0);
9172}
9173
9174#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9175#define MCP_ONE_TIMEOUT 100 /* 100 ms */
9176
e8920674
DK		 9177/**
9178 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 9179 *
e8920674 9180 * @bp: driver handle
72fd0718 9181 */
1191cb83 9182static void bnx2x_mcp_wait_one(struct bnx2x *bp)
72fd0718
VZ		 9183{
9184 /* special handling for emulation and FPGA,
9185 wait 10 times longer */
9186 if (CHIP_REV_IS_SLOW(bp))
9187 msleep(MCP_ONE_TIMEOUT*10);
9188 else
9189 msleep(MCP_ONE_TIMEOUT);
9190}
9191
1b6e2ceb
DK		 9192/*
9193 * initializes bp->common.shmem_base and waits for validity signature to appear
9194 */
9195static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 9196{
1b6e2ceb
DK		 9197 int cnt = 0;
9198 u32 val = 0;
72fd0718 9199
1b6e2ceb
DK		 9200 do {
9201 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9202 if (bp->common.shmem_base) {
9203 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9204 if (val & SHR_MEM_VALIDITY_MB)
9205 return 0;
9206 }
72fd0718 9207
1b6e2ceb 9208 bnx2x_mcp_wait_one(bp);
72fd0718 9209
1b6e2ceb 9210 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 9211
1b6e2ceb 9212 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 9213
1b6e2ceb
DK		 9214 return -ENODEV;
9215}
72fd0718 9216
1b6e2ceb
DK		 9217static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9218{
9219 int rc = bnx2x_init_shmem(bp);
72fd0718 9220
72fd0718
VZ		 9221 /* Restore the `magic' bit value */
9222 if (!CHIP_IS_E1(bp))
9223 bnx2x_clp_reset_done(bp, magic_val);
9224
9225 return rc;
9226}
9227
9228static void bnx2x_pxp_prep(struct bnx2x *bp)
9229{
9230 if (!CHIP_IS_E1(bp)) {
9231 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9232 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 9233 mmiowb();
9234 }
9235}
9236
9237/*
9238 * Reset the whole chip except for:
9239 * - PCIE core
9240 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9241 * one reset bit)
9242 * - IGU
9243 * - MISC (including AEU)
9244 * - GRC
9245 * - RBCN, RBCP
9246 */
c9ee9206 9247static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 9248{
9249 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 9250 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 9251
9252 /*
9253 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9254 * (per chip) blocks.
9255 */
9256 global_bits2 =
9257 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9258 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 9259
c55e771b
BW		 9260 /* Don't reset the following blocks.
9261 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9262 * reset, as in 4 port device they might still be owned
9263 * by the MCP (there is only one leader per path).
9264 */
72fd0718
VZ		 9265 not_reset_mask1 =
9266 MISC_REGISTERS_RESET_REG_1_RST_HC |
9267 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9268 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9269
9270 not_reset_mask2 =
c9ee9206 9271 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 9272 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9273 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9274 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9275 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9276 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9277 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 9278 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9279 MISC_REGISTERS_RESET_REG_2_RST_ATC |
c55e771b
BW		 9280 MISC_REGISTERS_RESET_REG_2_PGLC |
9281 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9282 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9283 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9284 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9285 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9286 MISC_REGISTERS_RESET_REG_2_UMAC1;
72fd0718 9287
8736c826
VZ		 9288 /*
9289 * Keep the following blocks in reset:
9290 * - all xxMACs are handled by the bnx2x_link code.
9291 */
9292 stay_reset2 =
8736c826
VZ		 9293 MISC_REGISTERS_RESET_REG_2_XMAC |
9294 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9295
9296 /* Full reset masks according to the chip */
72fd0718
VZ		 9297 reset_mask1 = 0xffffffff;
9298
9299 if (CHIP_IS_E1(bp))
9300 reset_mask2 = 0xffff;
8736c826 9301 else if (CHIP_IS_E1H(bp))
72fd0718 9302 reset_mask2 = 0x1ffff;
8736c826
VZ		 9303 else if (CHIP_IS_E2(bp))
9304 reset_mask2 = 0xfffff;
9305 else /* CHIP_IS_E3 */
9306 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 9307
9308 /* Don't reset global blocks unless we need to */
9309 if (!global)
9310 reset_mask2 &= ~global_bits2;
9311
9312 /*
9313 * In case of attention in the QM, we need to reset PXP
9314 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9315 * because otherwise QM reset would release 'close the gates' shortly
9316 * before resetting the PXP, then the PSWRQ would send a write
9317 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9318 * read the payload data from PSWWR, but PSWWR would not
9319 * respond. The write queue in PGLUE would stuck, dmae commands
9320 * would not return. Therefore it's important to reset the second
9321 * reset register (containing the
9322 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9323 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9324 * bit).
9325 */
72fd0718
VZ		 9326 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9327 reset_mask2 & (~not_reset_mask2));
9328
c9ee9206
VZ		 9329 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9330 reset_mask1 & (~not_reset_mask1));
9331
72fd0718
VZ		 9332 barrier();
9333 mmiowb();
9334
8736c826
VZ		 9335 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9336 reset_mask2 & (~stay_reset2));
9337
9338 barrier();
9339 mmiowb();
9340
c9ee9206 9341 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 9342 mmiowb();
9343}
9344
c9ee9206
VZ		 9345/**
9346 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9347 * It should get cleared in no more than 1s.
9348 *
9349 * @bp: driver handle
9350 *
9351 * It should get cleared in no more than 1s. Returns 0 if
9352 * pending writes bit gets cleared.
9353 */
9354static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9355{
9356 u32 cnt = 1000;
9357 u32 pend_bits = 0;
9358
9359 do {
9360 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9361
9362 if (pend_bits == 0)
9363 break;
9364
0926d499 9365 usleep_range(1000, 2000);
c9ee9206
VZ		 9366 } while (cnt-- > 0);
9367
9368 if (cnt <= 0) {
9369 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9370 pend_bits);
9371 return -EBUSY;
9372 }
9373
9374 return 0;
9375}
9376
9377static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 9378{
9379 int cnt = 1000;
9380 u32 val = 0;
9381 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
2de67439 9382 u32 tags_63_32 = 0;
72fd0718
VZ		 9383
9384 /* Empty the Tetris buffer, wait for 1s */
9385 do {
9386 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9387 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9388 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9389 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9390 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
c55e771b
BW		 9391 if (CHIP_IS_E3(bp))
9392 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9393
72fd0718
VZ		 9394 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9395 ((port_is_idle_0 & 0x1) == 0x1) &&
9396 ((port_is_idle_1 & 0x1) == 0x1) &&
c55e771b
BW		 9397 (pgl_exp_rom2 == 0xffffffff) &&
9398 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
72fd0718 9399 break;
0926d499 9400 usleep_range(1000, 2000);
72fd0718
VZ		 9401 } while (cnt-- > 0);
9402
9403 if (cnt <= 0) {
51c1a580
MS		 9404 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9405 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
72fd0718
VZ		 9406 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9407 pgl_exp_rom2);
9408 return -EAGAIN;
9409 }
9410
9411 barrier();
9412
9413 /* Close gates #2, #3 and #4 */
9414 bnx2x_set_234_gates(bp, true);
9415
c9ee9206
VZ		 9416 /* Poll for IGU VQs for 57712 and newer chips */
9417 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9418 return -EAGAIN;
9419
72fd0718
VZ		 9420 /* TBD: Indicate that "process kill" is in progress to MCP */
9421
9422 /* Clear "unprepared" bit */
9423 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9424 barrier();
9425
9426 /* Make sure all is written to the chip before the reset */
9427 mmiowb();
9428
9429 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9430 * PSWHST, GRC and PSWRD Tetris buffer.
9431 */
0926d499 9432 usleep_range(1000, 2000);
72fd0718
VZ		 9433
9434 /* Prepare to chip reset: */
9435 /* MCP */
c9ee9206
VZ		 9436 if (global)
9437 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 9438
9439 /* PXP */
9440 bnx2x_pxp_prep(bp);
9441 barrier();
9442
9443 /* reset the chip */
c9ee9206 9444 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 9445 barrier();
9446
9dcd9acd
DK		 9447 /* clear errors in PGB */
9448 if (!CHIP_IS_E1x(bp))
9449 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9450
72fd0718
VZ		 9451 /* Recover after reset: */
9452 /* MCP */
c9ee9206 9453 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 9454 return -EAGAIN;
9455
c9ee9206
VZ		 9456 /* TBD: Add resetting the NO_MCP mode DB here */
9457
72fd0718
VZ		 9458 /* Open the gates #2, #3 and #4 */
9459 bnx2x_set_234_gates(bp, false);
9460
9461 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9462 * reset state, re-enable attentions. */
9463
a2fbb9ea
ET		 9464 return 0;
9465}
9466
910cc727 9467static int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 9468{
9469 int rc = 0;
c9ee9206 9470 bool global = bnx2x_reset_is_global(bp);
95c6c616
AE		 9471 u32 load_code;
9472
9473 /* if not going to reset MCP - load "fake" driver to reset HW while
9474 * driver is owner of the HW
9475 */
9476 if (!global && !BP_NOMCP(bp)) {
5d07d868
YM		 9477 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9478 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
95c6c616
AE		 9479 if (!load_code) {
9480 BNX2X_ERR("MCP response failure, aborting\n");
9481 rc = -EAGAIN;
9482 goto exit_leader_reset;
9483 }
9484 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9485 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9486 BNX2X_ERR("MCP unexpected resp, aborting\n");
9487 rc = -EAGAIN;
9488 goto exit_leader_reset2;
9489 }
9490 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9491 if (!load_code) {
9492 BNX2X_ERR("MCP response failure, aborting\n");
9493 rc = -EAGAIN;
9494 goto exit_leader_reset2;
9495 }
9496 }
c9ee9206 9497
72fd0718 9498 /* Try to recover after the failure */
c9ee9206 9499 if (bnx2x_process_kill(bp, global)) {
51c1a580
MS		 9500 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9501 BP_PATH(bp));
72fd0718 9502 rc = -EAGAIN;
95c6c616 9503 goto exit_leader_reset2;
72fd0718
VZ		 9504 }
9505
c9ee9206
VZ		 9506 /*
9507 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9508 * state.
9509 */
72fd0718 9510 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 9511 if (global)
9512 bnx2x_clear_reset_global(bp);
72fd0718 9513
95c6c616
AE		 9514exit_leader_reset2:
9515 /* unload "fake driver" if it was loaded */
9516 if (!global && !BP_NOMCP(bp)) {
9517 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9518 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9519 }
72fd0718
VZ		 9520exit_leader_reset:
9521 bp->is_leader = 0;
c9ee9206
VZ		 9522 bnx2x_release_leader_lock(bp);
9523 smp_mb();
72fd0718
VZ		 9524 return rc;
9525}
9526
1191cb83 9527static void bnx2x_recovery_failed(struct bnx2x *bp)
c9ee9206
VZ		 9528{
9529 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9530
9531 /* Disconnect this device */
9532 netif_device_detach(bp->dev);
9533
9534 /*
9535 * Block ifup for all function on this engine until "process kill"
9536 * or power cycle.
9537 */
9538 bnx2x_set_reset_in_progress(bp);
9539
9540 /* Shut down the power */
9541 bnx2x_set_power_state(bp, PCI_D3hot);
9542
9543 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9544
9545 smp_mb();
9546}
9547
9548/*
9549 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 9550 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 9551 * will never be called when netif_running(bp->dev) is false.
9552 */
9553static void bnx2x_parity_recover(struct bnx2x *bp)
9554{
c9ee9206 9555 bool global = false;
7a752993 9556 u32 error_recovered, error_unrecovered;
95c6c616 9557 bool is_parity;
c9ee9206 9558
72fd0718
VZ		 9559 DP(NETIF_MSG_HW, "Handling parity\n");
9560 while (1) {
9561 switch (bp->recovery_state) {
9562 case BNX2X_RECOVERY_INIT:
9563 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
95c6c616
AE		 9564 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9565 WARN_ON(!is_parity);
c9ee9206 9566
72fd0718 9567 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 9568 if (bnx2x_trylock_leader_lock(bp)) {
9569 bnx2x_set_reset_in_progress(bp);
9570 /*
9571 * Check if there is a global attention and if
9572 * there was a global attention, set the global
9573 * reset bit.
9574 */
9575
9576 if (global)
9577 bnx2x_set_reset_global(bp);
9578
72fd0718 9579 bp->is_leader = 1;
c9ee9206 9580 }
72fd0718
VZ		 9581
9582 /* Stop the driver */
9583 /* If interface has been removed - break */
5d07d868 9584 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
72fd0718
VZ		 9585 return;
9586
9587 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206 9588
c9ee9206
VZ		 9589 /* Ensure "is_leader", MCP command sequence and
9590 * "recovery_state" update values are seen on other
9591 * CPUs.
72fd0718 9592 */
c9ee9206 9593 smp_mb();
72fd0718
VZ		 9594 break;
9595
9596 case BNX2X_RECOVERY_WAIT:
9597 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9598 if (bp->is_leader) {
c9ee9206 9599 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3
AE		 9600 bool other_load_status =
9601 bnx2x_get_load_status(bp, other_engine);
9602 bool load_status =
9603 bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 9604 global = bnx2x_reset_is_global(bp);
9605
9606 /*
9607 * In case of a parity in a global block, let
9608 * the first leader that performs a
9609 * leader_reset() reset the global blocks in
9610 * order to clear global attentions. Otherwise
16a5fd92 9611 * the gates will remain closed for that
c9ee9206
VZ		 9612 * engine.
9613 */
889b9af3
AE		 9614 if (load_status ||
9615 (global && other_load_status)) {
72fd0718
VZ		 9616 /* Wait until all other functions get
9617 * down.
9618 */
7be08a72 9619 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9620 HZ/10);
9621 return;
9622 } else {
9623 /* If all other functions got down -
9624 * try to bring the chip back to
9625 * normal. In any case it's an exit
9626 * point for a leader.
9627 */
c9ee9206
VZ		 9628 if (bnx2x_leader_reset(bp)) {
9629 bnx2x_recovery_failed(bp);
72fd0718
VZ		 9630 return;
9631 }
9632
c9ee9206
VZ		 9633 /* If we are here, means that the
9634 * leader has succeeded and doesn't
9635 * want to be a leader any more. Try
9636 * to continue as a none-leader.
9637 */
9638 break;
72fd0718
VZ		 9639 }
9640 } else { /* non-leader */
c9ee9206 9641 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 9642 /* Try to get a LEADER_LOCK HW lock as
9643 * long as a former leader may have
9644 * been unloaded by the user or
9645 * released a leadership by another
9646 * reason.
9647 */
c9ee9206 9648 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 9649 /* I'm a leader now! Restart a
9650 * switch case.
9651 */
9652 bp->is_leader = 1;
9653 break;
9654 }
9655
7be08a72 9656 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9657 HZ/10);
9658 return;
9659
c9ee9206
VZ		 9660 } else {
9661 /*
9662 * If there was a global attention, wait
9663 * for it to be cleared.
9664 */
9665 if (bnx2x_reset_is_global(bp)) {
9666 schedule_delayed_work(
7be08a72
AE		 9667 &bp->sp_rtnl_task,
9668 HZ/10);
c9ee9206
VZ		 9669 return;
9670 }
9671
7a752993
AE		 9672 error_recovered =
9673 bp->eth_stats.recoverable_error;
9674 error_unrecovered =
9675 bp->eth_stats.unrecoverable_error;
95c6c616
AE		 9676 bp->recovery_state =
9677 BNX2X_RECOVERY_NIC_LOADING;
9678 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
7a752993 9679 error_unrecovered++;
95c6c616 9680 netdev_err(bp->dev,
51c1a580 9681 "Recovery failed. Power cycle needed\n");
95c6c616
AE		 9682 /* Disconnect this device */
9683 netif_device_detach(bp->dev);
9684 /* Shut down the power */
9685 bnx2x_set_power_state(
9686 bp, PCI_D3hot);
9687 smp_mb();
9688 } else {
c9ee9206
VZ		 9689 bp->recovery_state =
9690 BNX2X_RECOVERY_DONE;
7a752993 9691 error_recovered++;
c9ee9206
VZ		 9692 smp_mb();
9693 }
7a752993
AE		 9694 bp->eth_stats.recoverable_error =
9695 error_recovered;
9696 bp->eth_stats.unrecoverable_error =
9697 error_unrecovered;
c9ee9206 9698
72fd0718
VZ		 9699 return;
9700 }
9701 }
9702 default:
9703 return;
9704 }
9705 }
9706}
9707
56ad3152
MS		 9708static int bnx2x_close(struct net_device *dev);
9709
72fd0718
VZ		 9710/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9711 * scheduled on a general queue in order to prevent a dead lock.
9712 */
7be08a72 9713static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 9714{
7be08a72 9715 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 9716
9717 rtnl_lock();
9718
8395be5e
AE		 9719 if (!netif_running(bp->dev)) {
9720 rtnl_unlock();
9721 return;
9722 }
7be08a72 9723
6bf07b8e 9724 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
7be08a72 9725#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e
YM		 9726 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9727 "you will need to reboot when done\n");
9728 goto sp_rtnl_not_reset;
7be08a72 9729#endif
7be08a72 9730 /*
b1fb8740
VZ		 9731 * Clear all pending SP commands as we are going to reset the
9732 * function anyway.
7be08a72 9733 */
b1fb8740
VZ		 9734 bp->sp_rtnl_state = 0;
9735 smp_mb();
9736
72fd0718 9737 bnx2x_parity_recover(bp);
b1fb8740 9738
8395be5e
AE		 9739 rtnl_unlock();
9740 return;
b1fb8740
VZ		 9741 }
9742
9743 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
6bf07b8e
YM		 9744#ifdef BNX2X_STOP_ON_ERROR
9745 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9746 "you will need to reboot when done\n");
9747 goto sp_rtnl_not_reset;
9748#endif
9749
b1fb8740
VZ		 9750 /*
9751 * Clear all pending SP commands as we are going to reset the
9752 * function anyway.
9753 */
9754 bp->sp_rtnl_state = 0;
9755 smp_mb();
9756
5d07d868 9757 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
72fd0718 9758 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740 9759
8395be5e
AE		 9760 rtnl_unlock();
9761 return;
72fd0718 9762 }
b1fb8740
VZ		 9763#ifdef BNX2X_STOP_ON_ERROR
9764sp_rtnl_not_reset:
9765#endif
9766 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9767 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
a3348722
BW		 9768 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9769 bnx2x_after_function_update(bp);
8304859a
AE		 9770 /*
9771 * in case of fan failure we need to reset id if the "stop on error"
9772 * debug flag is set, since we trying to prevent permanent overheating
9773 * damage
9774 */
9775 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
51c1a580 9776 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
8304859a
AE		 9777 netif_device_detach(bp->dev);
9778 bnx2x_close(bp->dev);
8395be5e
AE		 9779 rtnl_unlock();
9780 return;
8304859a
AE		 9781 }
9782
381ac16b
AE		 9783 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9784 DP(BNX2X_MSG_SP,
9785 "sending set mcast vf pf channel message from rtnl sp-task\n");
9786 bnx2x_vfpf_set_mcast(bp->dev);
9787 }
78c3bcc5
AE		 9788 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9789 &bp->sp_rtnl_state)){
9790 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9791 bnx2x_tx_disable(bp);
9792 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9793 }
9794 }
381ac16b 9795
8b09be5f
YM		 9796 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
9797 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
9798 bnx2x_set_rx_mode_inner(bp);
381ac16b
AE		 9799 }
9800
3ec9f9ca
AE		 9801 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9802 &bp->sp_rtnl_state))
9803 bnx2x_pf_set_vfs_vlan(bp);
9804
6ffa39f2 9805 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
07b4eb3b 9806 bnx2x_dcbx_stop_hw_tx(bp);
07b4eb3b 9807 bnx2x_dcbx_resume_hw_tx(bp);
6ffa39f2 9808 }
07b4eb3b 9809
8395be5e
AE		 9810 /* work which needs rtnl lock not-taken (as it takes the lock itself and
9811 * can be called from other contexts as well)
9812 */
34f80b04 9813 rtnl_unlock();
8395be5e 9814
6411280a 9815 /* enable SR-IOV if applicable */
8395be5e 9816 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
3c76feff
AE		 9817 &bp->sp_rtnl_state)) {
9818 bnx2x_disable_sriov(bp);
6411280a 9819 bnx2x_enable_sriov(bp);
3c76feff 9820 }
34f80b04
EG		 9821}
9822
3deb8167
YR		 9823static void bnx2x_period_task(struct work_struct *work)
9824{
9825 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9826
9827 if (!netif_running(bp->dev))
9828 goto period_task_exit;
9829
9830 if (CHIP_REV_IS_SLOW(bp)) {
9831 BNX2X_ERR("period task called on emulation, ignoring\n");
9832 goto period_task_exit;
9833 }
9834
9835 bnx2x_acquire_phy_lock(bp);
9836 /*
9837 * The barrier is needed to ensure the ordering between the writing to
9838 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9839 * the reading here.
9840 */
9841 smp_mb();
9842 if (bp->port.pmf) {
9843 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9844
9845 /* Re-queue task in 1 sec */
9846 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9847 }
9848
9849 bnx2x_release_phy_lock(bp);
9850period_task_exit:
9851 return;
9852}
9853
a2fbb9ea
ET		 9854/*
9855 * Init service functions
9856 */
9857
a8f47eb7 9858static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 9859{
9860 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9861 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9862 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 9863}
9864
1ef1d45a
BW		 9865static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9866 struct bnx2x_mac_vals *vals)
34f80b04 9867{
452427b0
YM		 9868 u32 val, base_addr, offset, mask, reset_reg;
9869 bool mac_stopped = false;
9870 u8 port = BP_PORT(bp);
34f80b04 9871
1ef1d45a
BW		 9872 /* reset addresses as they also mark which values were changed */
9873 vals->bmac_addr = 0;
9874 vals->umac_addr = 0;
9875 vals->xmac_addr = 0;
9876 vals->emac_addr = 0;
9877
452427b0 9878 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
f16da43b 9879
452427b0
YM		 9880 if (!CHIP_IS_E3(bp)) {
9881 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9882 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9883 if ((mask & reset_reg) && val) {
9884 u32 wb_data[2];
9885 BNX2X_DEV_INFO("Disable bmac Rx\n");
9886 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9887 : NIG_REG_INGRESS_BMAC0_MEM;
9888 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9889 : BIGMAC_REGISTER_BMAC_CONTROL;
7a06a122 9890
452427b0
YM		 9891 /*
9892 * use rd/wr since we cannot use dmae. This is safe
9893 * since MCP won't access the bus due to the request
9894 * to unload, and no function on the path can be
9895 * loaded at this time.
9896 */
9897 wb_data[0] = REG_RD(bp, base_addr + offset);
9898 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
1ef1d45a
BW		 9899 vals->bmac_addr = base_addr + offset;
9900 vals->bmac_val[0] = wb_data[0];
9901 vals->bmac_val[1] = wb_data[1];
452427b0 9902 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1ef1d45a
BW		 9903 REG_WR(bp, vals->bmac_addr, wb_data[0]);
9904 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
452427b0
YM		 9905 }
9906 BNX2X_DEV_INFO("Disable emac Rx\n");
1ef1d45a
BW		 9907 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9908 vals->emac_val = REG_RD(bp, vals->emac_addr);
9909 REG_WR(bp, vals->emac_addr, 0);
452427b0
YM		 9910 mac_stopped = true;
9911 } else {
9912 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9913 BNX2X_DEV_INFO("Disable xmac Rx\n");
9914 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9915 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9916 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9917 val & ~(1 << 1));
9918 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9919 val | (1 << 1));
1ef1d45a
BW		 9920 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9921 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9922 REG_WR(bp, vals->xmac_addr, 0);
452427b0
YM		 9923 mac_stopped = true;
9924 }
9925 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9926 if (mask & reset_reg) {
9927 BNX2X_DEV_INFO("Disable umac Rx\n");
9928 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1ef1d45a
BW		 9929 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9930 vals->umac_val = REG_RD(bp, vals->umac_addr);
9931 REG_WR(bp, vals->umac_addr, 0);
452427b0
YM		 9932 mac_stopped = true;
9933 }
9934 }
9935
9936 if (mac_stopped)
9937 msleep(20);
452427b0
YM		 9938}
9939
9940#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9941#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9942#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9943#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9944
91ebb929
YM		 9945#define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
9946#define BCM_5710_UNDI_FW_MF_MINOR (0x08)
9947#define BCM_5710_UNDI_FW_MF_VERS (0x05)
9948#define BNX2X_PREV_UNDI_MF_PORT(p) (0x1a150c + ((p) << 4))
9949#define BNX2X_PREV_UNDI_MF_FUNC(f) (0x1a184c + ((f) << 4))
9950static bool bnx2x_prev_unload_undi_fw_supports_mf(struct bnx2x *bp)
9951{
9952 u8 major, minor, version;
9953 u32 fw;
9954
9955 /* Must check that FW is loaded */
9956 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
9957 MISC_REGISTERS_RESET_REG_1_RST_XSEM)) {
9958 BNX2X_DEV_INFO("XSEM is reset - UNDI MF FW is not loaded\n");
9959 return false;
9960 }
9961
9962 /* Read Currently loaded FW version */
9963 fw = REG_RD(bp, XSEM_REG_PRAM);
9964 major = fw & 0xff;
9965 minor = (fw >> 0x8) & 0xff;
9966 version = (fw >> 0x10) & 0xff;
9967 BNX2X_DEV_INFO("Loaded FW: 0x%08x: Major 0x%02x Minor 0x%02x Version 0x%02x\n",
9968 fw, major, minor, version);
9969
9970 if (major > BCM_5710_UNDI_FW_MF_MAJOR)
9971 return true;
9972
9973 if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
9974 (minor > BCM_5710_UNDI_FW_MF_MINOR))
9975 return true;
9976
9977 if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
9978 (minor == BCM_5710_UNDI_FW_MF_MINOR) &&
9979 (version >= BCM_5710_UNDI_FW_MF_VERS))
9980 return true;
9981
9982 return false;
9983}
9984
9985static void bnx2x_prev_unload_undi_mf(struct bnx2x *bp)
9986{
9987 int i;
9988
9989 /* Due to legacy (FW) code, the first function on each engine has a
9990 * different offset macro from the rest of the functions.
9991 * Setting this for all 8 functions is harmless regardless of whether
9992 * this is actually a multi-function device.
9993 */
9994 for (i = 0; i < 2; i++)
9995 REG_WR(bp, BNX2X_PREV_UNDI_MF_PORT(i), 1);
9996
9997 for (i = 2; i < 8; i++)
9998 REG_WR(bp, BNX2X_PREV_UNDI_MF_FUNC(i - 2), 1);
9999
10000 BNX2X_DEV_INFO("UNDI FW (MF) set to discard\n");
10001}
10002
1dd06ae8 10003static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
452427b0
YM		 10004{
10005 u16 rcq, bd;
10006 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
10007
10008 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10009 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10010
10011 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10012 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
10013
10014 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10015 port, bd, rcq);
10016}
10017
0329aba1 10018static int bnx2x_prev_mcp_done(struct bnx2x *bp)
452427b0 10019{
5d07d868
YM		 10020 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10021 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
452427b0
YM		 10022 if (!rc) {
10023 BNX2X_ERR("MCP response failure, aborting\n");
10024 return -EBUSY;
10025 }
10026
10027 return 0;
10028}
10029
c63da990
BW		 10030static struct bnx2x_prev_path_list *
10031 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10032{
10033 struct bnx2x_prev_path_list *tmp_list;
10034
10035 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10036 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10037 bp->pdev->bus->number == tmp_list->bus &&
10038 BP_PATH(bp) == tmp_list->path)
10039 return tmp_list;
10040
10041 return NULL;
10042}
10043
7fa6f340
YM		 10044static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10045{
10046 struct bnx2x_prev_path_list *tmp_list;
10047 int rc;
10048
10049 rc = down_interruptible(&bnx2x_prev_sem);
10050 if (rc) {
10051 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10052 return rc;
10053 }
10054
10055 tmp_list = bnx2x_prev_path_get_entry(bp);
10056 if (tmp_list) {
10057 tmp_list->aer = 1;
10058 rc = 0;
10059 } else {
10060 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10061 BP_PATH(bp));
10062 }
10063
10064 up(&bnx2x_prev_sem);
10065
10066 return rc;
10067}
10068
0329aba1 10069static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
452427b0
YM		 10070{
10071 struct bnx2x_prev_path_list *tmp_list;
b85d717c 10072 bool rc = false;
452427b0
YM		 10073
10074 if (down_trylock(&bnx2x_prev_sem))
10075 return false;
10076
7fa6f340
YM		 10077 tmp_list = bnx2x_prev_path_get_entry(bp);
10078 if (tmp_list) {
10079 if (tmp_list->aer) {
10080 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10081 BP_PATH(bp));
10082 } else {
452427b0
YM		 10083 rc = true;
10084 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10085 BP_PATH(bp));
452427b0
YM		 10086 }
10087 }
10088
10089 up(&bnx2x_prev_sem);
10090
10091 return rc;
10092}
10093
178135c1
DK		 10094bool bnx2x_port_after_undi(struct bnx2x *bp)
10095{
10096 struct bnx2x_prev_path_list *entry;
10097 bool val;
10098
10099 down(&bnx2x_prev_sem);
10100
10101 entry = bnx2x_prev_path_get_entry(bp);
10102 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10103
10104 up(&bnx2x_prev_sem);
10105
10106 return val;
10107}
10108
c63da990 10109static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
452427b0
YM		 10110{
10111 struct bnx2x_prev_path_list *tmp_list;
10112 int rc;
10113
7fa6f340
YM		 10114 rc = down_interruptible(&bnx2x_prev_sem);
10115 if (rc) {
10116 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10117 return rc;
10118 }
10119
10120 /* Check whether the entry for this path already exists */
10121 tmp_list = bnx2x_prev_path_get_entry(bp);
10122 if (tmp_list) {
10123 if (!tmp_list->aer) {
10124 BNX2X_ERR("Re-Marking the path.\n");
10125 } else {
10126 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10127 BP_PATH(bp));
10128 tmp_list->aer = 0;
10129 }
10130 up(&bnx2x_prev_sem);
10131 return 0;
10132 }
10133 up(&bnx2x_prev_sem);
10134
10135 /* Create an entry for this path and add it */
ea4b3857 10136 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
452427b0
YM		 10137 if (!tmp_list) {
10138 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10139 return -ENOMEM;
10140 }
10141
10142 tmp_list->bus = bp->pdev->bus->number;
10143 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10144 tmp_list->path = BP_PATH(bp);
7fa6f340 10145 tmp_list->aer = 0;
c63da990 10146 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
452427b0
YM		 10147
10148 rc = down_interruptible(&bnx2x_prev_sem);
10149 if (rc) {
10150 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10151 kfree(tmp_list);
10152 } else {
7fa6f340
YM		 10153 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10154 BP_PATH(bp));
452427b0
YM		 10155 list_add(&tmp_list->list, &bnx2x_prev_list);
10156 up(&bnx2x_prev_sem);
10157 }
10158
10159 return rc;
10160}
10161
0329aba1 10162static int bnx2x_do_flr(struct bnx2x *bp)
452427b0 10163{
452427b0
YM		 10164 struct pci_dev *dev = bp->pdev;
10165
8eee694c
YM		 10166 if (CHIP_IS_E1x(bp)) {
10167 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10168 return -EINVAL;
10169 }
10170
10171 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10172 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10173 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10174 bp->common.bc_ver);
10175 return -EINVAL;
10176 }
452427b0 10177
8903b9eb
CL		 10178 if (!pci_wait_for_pending_transaction(dev))
10179 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
452427b0 10180
8eee694c 10181 BNX2X_DEV_INFO("Initiating FLR\n");
452427b0
YM		 10182 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10183
10184 return 0;
10185}
10186
0329aba1 10187static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
452427b0
YM		 10188{
10189 int rc;
10190
10191 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10192
10193 /* Test if previous unload process was already finished for this path */
10194 if (bnx2x_prev_is_path_marked(bp))
10195 return bnx2x_prev_mcp_done(bp);
10196
04c46736
YM		 10197 BNX2X_DEV_INFO("Path is unmarked\n");
10198
452427b0
YM		 10199 /* If function has FLR capabilities, and existing FW version matches
10200 * the one required, then FLR will be sufficient to clean any residue
10201 * left by previous driver
10202 */
91ebb929 10203 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
8eee694c
YM		 10204
10205 if (!rc) {
10206 /* fw version is good */
10207 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10208 rc = bnx2x_do_flr(bp);
10209 }
10210
10211 if (!rc) {
10212 /* FLR was performed */
10213 BNX2X_DEV_INFO("FLR successful\n");
10214 return 0;
10215 }
10216
10217 BNX2X_DEV_INFO("Could not FLR\n");
452427b0
YM		 10218
10219 /* Close the MCP request, return failure*/
10220 rc = bnx2x_prev_mcp_done(bp);
10221 if (!rc)
10222 rc = BNX2X_PREV_WAIT_NEEDED;
10223
10224 return rc;
10225}
10226
0329aba1 10227static int bnx2x_prev_unload_common(struct bnx2x *bp)
452427b0
YM		 10228{
10229 u32 reset_reg, tmp_reg = 0, rc;
c63da990 10230 bool prev_undi = false;
1ef1d45a
BW		 10231 struct bnx2x_mac_vals mac_vals;
10232
452427b0
YM		 10233 /* It is possible a previous function received 'common' answer,
10234 * but hasn't loaded yet, therefore creating a scenario of
10235 * multiple functions receiving 'common' on the same path.
10236 */
10237 BNX2X_DEV_INFO("Common unload Flow\n");
10238
1ef1d45a
BW		 10239 memset(&mac_vals, 0, sizeof(mac_vals));
10240
452427b0
YM		 10241 if (bnx2x_prev_is_path_marked(bp))
10242 return bnx2x_prev_mcp_done(bp);
10243
10244 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10245
10246 /* Reset should be performed after BRB is emptied */
10247 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10248 u32 timer_count = 1000;
452427b0
YM		 10249
10250 /* Close the MAC Rx to prevent BRB from filling up */
1ef1d45a
BW		 10251 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10252
10253 /* close LLH filters towards the BRB */
10254 bnx2x_set_rx_filter(&bp->link_params, 0);
452427b0
YM		 10255
10256 /* Check if the UNDI driver was previously loaded
34f80b04
EG		 10257 * UNDI driver initializes CID offset for normal bell to 0x7
10258 */
452427b0
YM		 10259 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
10260 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
10261 if (tmp_reg == 0x7) {
10262 BNX2X_DEV_INFO("UNDI previously loaded\n");
10263 prev_undi = true;
10264 /* clear the UNDI indication */
10265 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
a74801c5
YM		 10266 /* clear possible idle check errors */
10267 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
34f80b04 10268 }
452427b0 10269 }
d46f7c4d
DK		 10270 if (!CHIP_IS_E1x(bp))
10271 /* block FW from writing to host */
10272 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10273
452427b0
YM		 10274 /* wait until BRB is empty */
10275 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10276 while (timer_count) {
10277 u32 prev_brb = tmp_reg;
34f80b04 10278
452427b0
YM		 10279 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10280 if (!tmp_reg)
10281 break;
619c5cb6 10282
452427b0 10283 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
619c5cb6 10284
452427b0
YM		 10285 /* reset timer as long as BRB actually gets emptied */
10286 if (prev_brb > tmp_reg)
10287 timer_count = 1000;
10288 else
10289 timer_count--;
da5a662a 10290
91ebb929
YM		 10291 /* New UNDI FW supports MF and contains better
10292 * cleaning methods - might be redundant but harmless.
10293 */
10294 if (bnx2x_prev_unload_undi_fw_supports_mf(bp)) {
10295 bnx2x_prev_unload_undi_mf(bp);
10296 } else if (prev_undi) {
10297 /* If UNDI resides in memory,
10298 * manually increment it
10299 */
452427b0 10300 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
91ebb929 10301 }
452427b0 10302 udelay(10);
7a06a122 10303 }
452427b0
YM		 10304
10305 if (!timer_count)
10306 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
34f80b04 10307 }
f16da43b 10308
452427b0
YM		 10309 /* No packets are in the pipeline, path is ready for reset */
10310 bnx2x_reset_common(bp);
10311
1ef1d45a
BW		 10312 if (mac_vals.xmac_addr)
10313 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10314 if (mac_vals.umac_addr)
10315 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10316 if (mac_vals.emac_addr)
10317 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10318 if (mac_vals.bmac_addr) {
10319 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10320 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10321 }
10322
c63da990 10323 rc = bnx2x_prev_mark_path(bp, prev_undi);
452427b0
YM		 10324 if (rc) {
10325 bnx2x_prev_mcp_done(bp);
10326 return rc;
10327 }
10328
10329 return bnx2x_prev_mcp_done(bp);
10330}
10331
24f06716
AE		 10332/* previous driver DMAE transaction may have occurred when pre-boot stage ended
10333 * and boot began, or when kdump kernel was loaded. Either case would invalidate
10334 * the addresses of the transaction, resulting in was-error bit set in the pci
10335 * causing all hw-to-host pcie transactions to timeout. If this happened we want
10336 * to clear the interrupt which detected this from the pglueb and the was done
10337 * bit
10338 */
0329aba1 10339static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
24f06716 10340{
4a25417c
AE		 10341 if (!CHIP_IS_E1x(bp)) {
10342 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10343 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
04c46736
YM		 10344 DP(BNX2X_MSG_SP,
10345 "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
4a25417c
AE		 10346 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10347 1 << BP_FUNC(bp));
10348 }
24f06716
AE		 10349 }
10350}
10351
0329aba1 10352static int bnx2x_prev_unload(struct bnx2x *bp)
452427b0
YM		 10353{
10354 int time_counter = 10;
10355 u32 rc, fw, hw_lock_reg, hw_lock_val;
10356 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10357
24f06716
AE		 10358 /* clear hw from errors which may have resulted from an interrupted
10359 * dmae transaction.
10360 */
10361 bnx2x_prev_interrupted_dmae(bp);
10362
10363 /* Release previously held locks */
452427b0
YM		 10364 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10365 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10366 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10367
3cdeec22 10368 hw_lock_val = REG_RD(bp, hw_lock_reg);
452427b0
YM		 10369 if (hw_lock_val) {
10370 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10371 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10372 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10373 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10374 }
10375
10376 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10377 REG_WR(bp, hw_lock_reg, 0xffffffff);
10378 } else
10379 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10380
10381 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10382 BNX2X_DEV_INFO("Release previously held alr\n");
3cdeec22 10383 bnx2x_release_alr(bp);
452427b0
YM		 10384 }
10385
452427b0 10386 do {
7fa6f340 10387 int aer = 0;
452427b0
YM		 10388 /* Lock MCP using an unload request */
10389 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10390 if (!fw) {
10391 BNX2X_ERR("MCP response failure, aborting\n");
10392 rc = -EBUSY;
10393 break;
10394 }
10395
7fa6f340
YM		 10396 rc = down_interruptible(&bnx2x_prev_sem);
10397 if (rc) {
10398 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10399 rc);
10400 } else {
10401 /* If Path is marked by EEH, ignore unload status */
10402 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10403 bnx2x_prev_path_get_entry(bp)->aer);
60cde81f 10404 up(&bnx2x_prev_sem);
7fa6f340 10405 }
7fa6f340
YM		 10406
10407 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
452427b0
YM		 10408 rc = bnx2x_prev_unload_common(bp);
10409 break;
10410 }
10411
16a5fd92 10412 /* non-common reply from MCP might require looping */
452427b0
YM		 10413 rc = bnx2x_prev_unload_uncommon(bp);
10414 if (rc != BNX2X_PREV_WAIT_NEEDED)
10415 break;
10416
10417 msleep(20);
10418 } while (--time_counter);
10419
10420 if (!time_counter || rc) {
91ebb929
YM		 10421 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10422 rc = -EPROBE_DEFER;
452427b0
YM		 10423 }
10424
c63da990 10425 /* Mark function if its port was used to boot from SAN */
178135c1 10426 if (bnx2x_port_after_undi(bp))
c63da990
BW		 10427 bp->link_params.feature_config_flags |=
10428 FEATURE_CONFIG_BOOT_FROM_SAN;
10429
452427b0
YM		 10430 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10431
10432 return rc;
34f80b04
EG		 10433}
10434
0329aba1 10435static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
34f80b04 10436{
1d187b34 10437 u32 val, val2, val3, val4, id, boot_mode;
72ce58c3 10438 u16 pmc;
34f80b04
EG		 10439
10440 /* Get the chip revision id and number. */
10441 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10442 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10443 id = ((val & 0xffff) << 16);
10444 val = REG_RD(bp, MISC_REG_CHIP_REV);
10445 id |= ((val & 0xf) << 12);
f22fdf25
YM		 10446
10447 /* Metal is read from PCI regs, but we can't access >=0x400 from
10448 * the configuration space (so we need to reg_rd)
10449 */
10450 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10451 id |= (((val >> 24) & 0xf) << 4);
5a40e08e 10452 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 10453 id |= (val & 0xf);
10454 bp->common.chip_id = id;
523224a3 10455
7e8e02df
BW		 10456 /* force 57811 according to MISC register */
10457 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10458 if (CHIP_IS_57810(bp))
10459 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10460 (bp->common.chip_id & 0x0000FFFF);
10461 else if (CHIP_IS_57810_MF(bp))
10462 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10463 (bp->common.chip_id & 0x0000FFFF);
10464 bp->common.chip_id |= 0x1;
10465 }
10466
523224a3
DK		 10467 /* Set doorbell size */
10468 bp->db_size = (1 << BNX2X_DB_SHIFT);
10469
619c5cb6 10470 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 10471 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10472 if ((val & 1) == 0)
10473 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10474 else
10475 val = (val >> 1) & 1;
10476 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10477 "2_PORT_MODE");
10478 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10479 CHIP_2_PORT_MODE;
10480
10481 if (CHIP_MODE_IS_4_PORT(bp))
10482 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10483 else
10484 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10485 } else {
10486 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10487 bp->pfid = bp->pf_num; /* 0..7 */
10488 }
10489
51c1a580
MS		 10490 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10491
f2e0899f
DK		 10492 bp->link_params.chip_id = bp->common.chip_id;
10493 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 10494
1c06328c
EG		 10495 val = (REG_RD(bp, 0x2874) & 0x55);
10496 if ((bp->common.chip_id & 0x1) ||
10497 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10498 bp->flags |= ONE_PORT_FLAG;
10499 BNX2X_DEV_INFO("single port device\n");
10500 }
10501
34f80b04 10502 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 10503 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 10504 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10505 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10506 bp->common.flash_size, bp->common.flash_size);
10507
1b6e2ceb
DK		 10508 bnx2x_init_shmem(bp);
10509
f2e0899f
DK		 10510 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10511 MISC_REG_GENERIC_CR_1 :
10512 MISC_REG_GENERIC_CR_0));
1b6e2ceb 10513
34f80b04 10514 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 10515 bp->link_params.shmem2_base = bp->common.shmem2_base;
b884d95b
YR		 10516 if (SHMEM2_RD(bp, size) >
10517 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10518 bp->link_params.lfa_base =
10519 REG_RD(bp, bp->common.shmem2_base +
10520 (u32)offsetof(struct shmem2_region,
10521 lfa_host_addr[BP_PORT(bp)]));
10522 else
10523 bp->link_params.lfa_base = 0;
2691d51d
EG		 10524 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10525 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 10526
f2e0899f 10527 if (!bp->common.shmem_base) {
34f80b04
EG		 10528 BNX2X_DEV_INFO("MCP not active\n");
10529 bp->flags |= NO_MCP_FLAG;
10530 return;
10531 }
10532
34f80b04 10533 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 10534 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 10535
10536 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10537 SHARED_HW_CFG_LED_MODE_MASK) >>
10538 SHARED_HW_CFG_LED_MODE_SHIFT);
10539
c2c8b03e
EG		 10540 bp->link_params.feature_config_flags = 0;
10541 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10542 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10543 bp->link_params.feature_config_flags |=
10544 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10545 else
10546 bp->link_params.feature_config_flags &=
10547 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10548
34f80b04
EG		 10549 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10550 bp->common.bc_ver = val;
10551 BNX2X_DEV_INFO("bc_ver %X\n", val);
10552 if (val < BNX2X_BC_VER) {
10553 /* for now only warn
10554 * later we might need to enforce this */
51c1a580
MS		 10555 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10556 BNX2X_BC_VER, val);
34f80b04 10557 }
4d295db0 10558 bp->link_params.feature_config_flags |=
a22f0788 10559 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 10560 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10561
a22f0788
YR		 10562 bp->link_params.feature_config_flags |=
10563 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10564 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
a3348722
BW		 10565 bp->link_params.feature_config_flags |=
10566 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10567 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
85242eea
YR		 10568 bp->link_params.feature_config_flags |=
10569 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10570 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
55386fe8
YR		 10571
10572 bp->link_params.feature_config_flags |=
10573 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10574 FEATURE_CONFIG_MT_SUPPORT : 0;
10575
0e898dd7
BW		 10576 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10577 BC_SUPPORTS_PFC_STATS : 0;
85242eea 10578
2e499d3c
BW		 10579 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10580 BC_SUPPORTS_FCOE_FEATURES : 0;
10581
9876879f
BW		 10582 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10583 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
a6d3a5ba
BW		 10584
10585 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10586 BC_SUPPORTS_RMMOD_CMD : 0;
10587
1d187b34
BW		 10588 boot_mode = SHMEM_RD(bp,
10589 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10590 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10591 switch (boot_mode) {
10592 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10593 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10594 break;
10595 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10596 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10597 break;
10598 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10599 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10600 break;
10601 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10602 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10603 break;
10604 }
10605
29ed74c3 10606 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
f9a3ebbe
DK		 10607 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10608
72ce58c3 10609 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 10610 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 10611
10612 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10613 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10614 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10615 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10616
cdaa7cb8
VZ		 10617 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10618 val, val2, val3, val4);
34f80b04
EG		 10619}
10620
f2e0899f
DK		 10621#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10622#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10623
0329aba1 10624static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
f2e0899f
DK		 10625{
10626 int pfid = BP_FUNC(bp);
f2e0899f
DK		 10627 int igu_sb_id;
10628 u32 val;
6383c0b3 10629 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 10630
10631 bp->igu_base_sb = 0xff;
f2e0899f 10632 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 10633 int vn = BP_VN(bp);
6383c0b3 10634 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 10635 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10636 FP_SB_MAX_E1x;
10637
10638 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10639 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10640
9b341bb1 10641 return 0;
f2e0899f
DK		 10642 }
10643
10644 /* IGU in normal mode - read CAM */
10645 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10646 igu_sb_id++) {
10647 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10648 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10649 continue;
10650 fid = IGU_FID(val);
10651 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10652 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10653 continue;
10654 if (IGU_VEC(val) == 0)
10655 /* default status block */
10656 bp->igu_dsb_id = igu_sb_id;
10657 else {
10658 if (bp->igu_base_sb == 0xff)
10659 bp->igu_base_sb = igu_sb_id;
6383c0b3 10660 igu_sb_cnt++;
f2e0899f
DK		 10661 }
10662 }
10663 }
619c5cb6 10664
6383c0b3 10665#ifdef CONFIG_PCI_MSI
185d4c8b
AE		 10666 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10667 * optional that number of CAM entries will not be equal to the value
10668 * advertised in PCI.
10669 * Driver should use the minimal value of both as the actual status
10670 * block count
619c5cb6 10671 */
185d4c8b 10672 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
6383c0b3 10673#endif
619c5cb6 10674
9b341bb1 10675 if (igu_sb_cnt == 0) {
f2e0899f 10676 BNX2X_ERR("CAM configuration error\n");
9b341bb1
BW		 10677 return -EINVAL;
10678 }
10679
10680 return 0;
f2e0899f
DK		 10681}
10682
1dd06ae8 10683static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
a2fbb9ea 10684{
a22f0788
YR		 10685 int cfg_size = 0, idx, port = BP_PORT(bp);
10686
10687 /* Aggregation of supported attributes of all external phys */
10688 bp->port.supported[0] = 0;
10689 bp->port.supported[1] = 0;
b7737c9b
YR		 10690 switch (bp->link_params.num_phys) {
10691 case 1:
a22f0788
YR		 10692 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10693 cfg_size = 1;
10694 break;
b7737c9b 10695 case 2:
a22f0788
YR		 10696 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10697 cfg_size = 1;
10698 break;
10699 case 3:
10700 if (bp->link_params.multi_phy_config &
10701 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10702 bp->port.supported[1] =
10703 bp->link_params.phy[EXT_PHY1].supported;
10704 bp->port.supported[0] =
10705 bp->link_params.phy[EXT_PHY2].supported;
10706 } else {
10707 bp->port.supported[0] =
10708 bp->link_params.phy[EXT_PHY1].supported;
10709 bp->port.supported[1] =
10710 bp->link_params.phy[EXT_PHY2].supported;
10711 }
10712 cfg_size = 2;
10713 break;
b7737c9b 10714 }
a2fbb9ea 10715
a22f0788 10716 if (!(bp->port.supported[0] || bp->port.supported[1])) {
51c1a580 10717 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 10718 SHMEM_RD(bp,
a22f0788
YR		 10719 dev_info.port_hw_config[port].external_phy_config),
10720 SHMEM_RD(bp,
10721 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 10722 return;
f85582f8 10723 }
a2fbb9ea 10724
619c5cb6
VZ		 10725 if (CHIP_IS_E3(bp))
10726 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10727 else {
10728 switch (switch_cfg) {
10729 case SWITCH_CFG_1G:
10730 bp->port.phy_addr = REG_RD(
10731 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10732 break;
10733 case SWITCH_CFG_10G:
10734 bp->port.phy_addr = REG_RD(
10735 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10736 break;
10737 default:
10738 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10739 bp->port.link_config[0]);
10740 return;
10741 }
a2fbb9ea 10742 }
619c5cb6 10743 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 10744 /* mask what we support according to speed_cap_mask per configuration */
10745 for (idx = 0; idx < cfg_size; idx++) {
10746 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10747 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 10748 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 10749
a22f0788 10750 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10751 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 10752 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 10753
a22f0788 10754 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10755 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 10756 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 10757
a22f0788 10758 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10759 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 10760 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 10761
a22f0788 10762 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10763 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 10764 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 10765 SUPPORTED_1000baseT_Full);
a2fbb9ea 10766
a22f0788 10767 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10768 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 10769 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 10770
a22f0788 10771 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10772 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788 10773 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
b8e0d884
YR		 10774
10775 if (!(bp->link_params.speed_cap_mask[idx] &
10776 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10777 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
a22f0788 10778 }
a2fbb9ea 10779
a22f0788
YR		 10780 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10781 bp->port.supported[1]);
a2fbb9ea
ET		 10782}
10783
0329aba1 10784static void bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 10785{
a22f0788
YR		 10786 u32 link_config, idx, cfg_size = 0;
10787 bp->port.advertising[0] = 0;
10788 bp->port.advertising[1] = 0;
10789 switch (bp->link_params.num_phys) {
10790 case 1:
10791 case 2:
10792 cfg_size = 1;
10793 break;
10794 case 3:
10795 cfg_size = 2;
10796 break;
10797 }
10798 for (idx = 0; idx < cfg_size; idx++) {
10799 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10800 link_config = bp->port.link_config[idx];
10801 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 10802 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 10803 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10804 bp->link_params.req_line_speed[idx] =
10805 SPEED_AUTO_NEG;
10806 bp->port.advertising[idx] |=
10807 bp->port.supported[idx];
10bd1f24
MY		 10808 if (bp->link_params.phy[EXT_PHY1].type ==
10809 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10810 bp->port.advertising[idx] |=
10811 (SUPPORTED_100baseT_Half |
10812 SUPPORTED_100baseT_Full);
f85582f8
DK		 10813 } else {
10814 /* force 10G, no AN */
a22f0788
YR		 10815 bp->link_params.req_line_speed[idx] =
10816 SPEED_10000;
10817 bp->port.advertising[idx] |=
10818 (ADVERTISED_10000baseT_Full |
f85582f8 10819 ADVERTISED_FIBRE);
a22f0788 10820 continue;
f85582f8
DK		 10821 }
10822 break;
a2fbb9ea 10823
f85582f8 10824 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 10825 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10826 bp->link_params.req_line_speed[idx] =
10827 SPEED_10;
10828 bp->port.advertising[idx] |=
10829 (ADVERTISED_10baseT_Full |
f85582f8
DK		 10830 ADVERTISED_TP);
10831 } else {
51c1a580 10832 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8 10833 link_config,
a22f0788 10834 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 10835 return;
10836 }
10837 break;
a2fbb9ea 10838
f85582f8 10839 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 10840 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10841 bp->link_params.req_line_speed[idx] =
10842 SPEED_10;
10843 bp->link_params.req_duplex[idx] =
10844 DUPLEX_HALF;
10845 bp->port.advertising[idx] |=
10846 (ADVERTISED_10baseT_Half |
f85582f8
DK		 10847 ADVERTISED_TP);
10848 } else {
51c1a580 10849 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 10850 link_config,
10851 bp->link_params.speed_cap_mask[idx]);
10852 return;
10853 }
10854 break;
a2fbb9ea 10855
f85582f8
DK		 10856 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10857 if (bp->port.supported[idx] &
10858 SUPPORTED_100baseT_Full) {
a22f0788
YR		 10859 bp->link_params.req_line_speed[idx] =
10860 SPEED_100;
10861 bp->port.advertising[idx] |=
10862 (ADVERTISED_100baseT_Full |
f85582f8
DK		 10863 ADVERTISED_TP);
10864 } else {
51c1a580 10865 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 10866 link_config,
10867 bp->link_params.speed_cap_mask[idx]);
10868 return;
10869 }
10870 break;
a2fbb9ea 10871
f85582f8
DK		 10872 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10873 if (bp->port.supported[idx] &
10874 SUPPORTED_100baseT_Half) {
10875 bp->link_params.req_line_speed[idx] =
10876 SPEED_100;
10877 bp->link_params.req_duplex[idx] =
10878 DUPLEX_HALF;
a22f0788
YR		 10879 bp->port.advertising[idx] |=
10880 (ADVERTISED_100baseT_Half |
f85582f8
DK		 10881 ADVERTISED_TP);
10882 } else {
51c1a580 10883 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 10884 link_config,
10885 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 10886 return;
10887 }
10888 break;
a2fbb9ea 10889
f85582f8 10890 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 10891 if (bp->port.supported[idx] &
10892 SUPPORTED_1000baseT_Full) {
10893 bp->link_params.req_line_speed[idx] =
10894 SPEED_1000;
10895 bp->port.advertising[idx] |=
10896 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 10897 ADVERTISED_TP);
10898 } else {
51c1a580 10899 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 10900 link_config,
10901 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 10902 return;
10903 }
10904 break;
a2fbb9ea 10905
f85582f8 10906 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 10907 if (bp->port.supported[idx] &
10908 SUPPORTED_2500baseX_Full) {
10909 bp->link_params.req_line_speed[idx] =
10910 SPEED_2500;
10911 bp->port.advertising[idx] |=
10912 (ADVERTISED_2500baseX_Full |
34f80b04 10913 ADVERTISED_TP);
f85582f8 10914 } else {
51c1a580 10915 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 10916 link_config,
f85582f8
DK		 10917 bp->link_params.speed_cap_mask[idx]);
10918 return;
10919 }
10920 break;
a2fbb9ea 10921
f85582f8 10922 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 10923 if (bp->port.supported[idx] &
10924 SUPPORTED_10000baseT_Full) {
10925 bp->link_params.req_line_speed[idx] =
10926 SPEED_10000;
10927 bp->port.advertising[idx] |=
10928 (ADVERTISED_10000baseT_Full |
34f80b04 10929 ADVERTISED_FIBRE);
f85582f8 10930 } else {
51c1a580 10931 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 10932 link_config,
f85582f8
DK		 10933 bp->link_params.speed_cap_mask[idx]);
10934 return;
10935 }
10936 break;
3c9ada22
YR		 10937 case PORT_FEATURE_LINK_SPEED_20G:
10938 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 10939
3c9ada22 10940 break;
f85582f8 10941 default:
51c1a580 10942 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
754a2f52 10943 link_config);
f85582f8
DK		 10944 bp->link_params.req_line_speed[idx] =
10945 SPEED_AUTO_NEG;
10946 bp->port.advertising[idx] =
10947 bp->port.supported[idx];
10948 break;
10949 }
a2fbb9ea 10950
a22f0788 10951 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 10952 PORT_FEATURE_FLOW_CONTROL_MASK);
cd1dfce2
YM		 10953 if (bp->link_params.req_flow_ctrl[idx] ==
10954 BNX2X_FLOW_CTRL_AUTO) {
10955 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10956 bp->link_params.req_flow_ctrl[idx] =
10957 BNX2X_FLOW_CTRL_NONE;
10958 else
10959 bnx2x_set_requested_fc(bp);
a22f0788 10960 }
a2fbb9ea 10961
51c1a580 10962 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
a22f0788
YR		 10963 bp->link_params.req_line_speed[idx],
10964 bp->link_params.req_duplex[idx],
10965 bp->link_params.req_flow_ctrl[idx],
10966 bp->port.advertising[idx]);
10967 }
a2fbb9ea
ET		 10968}
10969
0329aba1 10970static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
e665bfda 10971{
86564c3f
YM		 10972 __be16 mac_hi_be = cpu_to_be16(mac_hi);
10973 __be32 mac_lo_be = cpu_to_be32(mac_lo);
10974 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10975 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
e665bfda
MC		 10976}
10977
0329aba1 10978static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 10979{
34f80b04 10980 int port = BP_PORT(bp);
589abe3a 10981 u32 config;
c8c60d88 10982 u32 ext_phy_type, ext_phy_config, eee_mode;
a2fbb9ea 10983
c18487ee 10984 bp->link_params.bp = bp;
34f80b04 10985 bp->link_params.port = port;
c18487ee 10986
c18487ee 10987 bp->link_params.lane_config =
a2fbb9ea 10988 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 10989
a22f0788 10990 bp->link_params.speed_cap_mask[0] =
a2fbb9ea 10991 SHMEM_RD(bp,
b0261926
YR		 10992 dev_info.port_hw_config[port].speed_capability_mask) &
10993 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788
YR		 10994 bp->link_params.speed_cap_mask[1] =
10995 SHMEM_RD(bp,
b0261926
YR		 10996 dev_info.port_hw_config[port].speed_capability_mask2) &
10997 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788 10998 bp->port.link_config[0] =
a2fbb9ea
ET		 10999 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11000
a22f0788
YR		 11001 bp->port.link_config[1] =
11002 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 11003
a22f0788
YR		 11004 bp->link_params.multi_phy_config =
11005 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 11006 /* If the device is capable of WoL, set the default state according
11007 * to the HW
11008 */
4d295db0 11009 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 11010 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11011 (config & PORT_FEATURE_WOL_ENABLED));
11012
4ba7699b
YM		 11013 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11014 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11015 bp->flags |= NO_ISCSI_FLAG;
11016 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11017 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11018 bp->flags |= NO_FCOE_FLAG;
11019
51c1a580 11020 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 11021 bp->link_params.lane_config,
a22f0788
YR		 11022 bp->link_params.speed_cap_mask[0],
11023 bp->port.link_config[0]);
a2fbb9ea 11024
a22f0788 11025 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 11026 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 11027 bnx2x_phy_probe(&bp->link_params);
c18487ee 11028 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 11029
11030 bnx2x_link_settings_requested(bp);
11031
01cd4528
EG		 11032 /*
11033 * If connected directly, work with the internal PHY, otherwise, work
11034 * with the external PHY
11035 */
b7737c9b
YR		 11036 ext_phy_config =
11037 SHMEM_RD(bp,
11038 dev_info.port_hw_config[port].external_phy_config);
11039 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 11040 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 11041 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 11042
11043 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11044 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11045 bp->mdio.prtad =
b7737c9b 11046 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d 11047
c8c60d88
YM		 11048 /* Configure link feature according to nvram value */
11049 eee_mode = (((SHMEM_RD(bp, dev_info.
11050 port_feature_config[port].eee_power_mode)) &
11051 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11052 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11053 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11054 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11055 EEE_MODE_ENABLE_LPI |
11056 EEE_MODE_OUTPUT_TIME;
11057 } else {
11058 bp->link_params.eee_mode = 0;
11059 }
0793f83f 11060}
01cd4528 11061
b306f5ed 11062void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 11063{
9e62e912 11064 u32 no_flags = NO_ISCSI_FLAG;
bf61ee14 11065 int port = BP_PORT(bp);
2ba45142 11066 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 11067 drv_lic_key[port].max_iscsi_conn);
2ba45142 11068
55c11941
MS		 11069 if (!CNIC_SUPPORT(bp)) {
11070 bp->flags |= no_flags;
11071 return;
11072 }
11073
b306f5ed 11074 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 11075 bp->cnic_eth_dev.max_iscsi_conn =
11076 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11077 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11078
b306f5ed
DK		 11079 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11080 bp->cnic_eth_dev.max_iscsi_conn);
11081
11082 /*
11083 * If maximum allowed number of connections is zero -
11084 * disable the feature.
11085 */
11086 if (!bp->cnic_eth_dev.max_iscsi_conn)
9e62e912 11087 bp->flags |= no_flags;
b306f5ed
DK		 11088}
11089
0329aba1 11090static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
9e62e912
DK		 11091{
11092 /* Port info */
11093 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11094 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11095 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11096 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11097
11098 /* Node info */
11099 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11100 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11101 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11102 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11103}
86800194
DK		 11104
11105static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11106{
11107 u8 count = 0;
11108
11109 if (IS_MF(bp)) {
11110 u8 fid;
11111
11112 /* iterate over absolute function ids for this path: */
11113 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11114 if (IS_MF_SD(bp)) {
11115 u32 cfg = MF_CFG_RD(bp,
11116 func_mf_config[fid].config);
11117
11118 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11119 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11120 FUNC_MF_CFG_PROTOCOL_FCOE))
11121 count++;
11122 } else {
11123 u32 cfg = MF_CFG_RD(bp,
11124 func_ext_config[fid].
11125 func_cfg);
11126
11127 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11128 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11129 count++;
11130 }
11131 }
11132 } else { /* SF */
11133 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11134
11135 for (port = 0; port < port_cnt; port++) {
11136 u32 lic = SHMEM_RD(bp,
11137 drv_lic_key[port].max_fcoe_conn) ^
11138 FW_ENCODE_32BIT_PATTERN;
11139 if (lic)
11140 count++;
11141 }
11142 }
11143
11144 return count;
11145}
11146
0329aba1 11147static void bnx2x_get_fcoe_info(struct bnx2x *bp)
b306f5ed
DK		 11148{
11149 int port = BP_PORT(bp);
11150 int func = BP_ABS_FUNC(bp);
b306f5ed
DK		 11151 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11152 drv_lic_key[port].max_fcoe_conn);
86800194 11153 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
b306f5ed 11154
55c11941
MS		 11155 if (!CNIC_SUPPORT(bp)) {
11156 bp->flags |= NO_FCOE_FLAG;
11157 return;
11158 }
11159
b306f5ed 11160 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 11161 bp->cnic_eth_dev.max_fcoe_conn =
11162 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11163 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11164
0eb43b4b
BPG		 11165 /* Calculate the number of maximum allowed FCoE tasks */
11166 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
86800194
DK		 11167
11168 /* check if FCoE resources must be shared between different functions */
11169 if (num_fcoe_func)
11170 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
0eb43b4b 11171
bf61ee14
VZ		 11172 /* Read the WWN: */
11173 if (!IS_MF(bp)) {
11174 /* Port info */
11175 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11176 SHMEM_RD(bp,
2de67439 11177 dev_info.port_hw_config[port].
bf61ee14
VZ		 11178 fcoe_wwn_port_name_upper);
11179 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11180 SHMEM_RD(bp,
2de67439 11181 dev_info.port_hw_config[port].
bf61ee14
VZ		 11182 fcoe_wwn_port_name_lower);
11183
11184 /* Node info */
11185 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11186 SHMEM_RD(bp,
2de67439 11187 dev_info.port_hw_config[port].
bf61ee14
VZ		 11188 fcoe_wwn_node_name_upper);
11189 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11190 SHMEM_RD(bp,
2de67439 11191 dev_info.port_hw_config[port].
bf61ee14
VZ		 11192 fcoe_wwn_node_name_lower);
11193 } else if (!IS_MF_SD(bp)) {
bf61ee14
VZ		 11194 /*
11195 * Read the WWN info only if the FCoE feature is enabled for
11196 * this function.
11197 */
7b5342d9 11198 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
9e62e912
DK		 11199 bnx2x_get_ext_wwn_info(bp, func);
11200
382e513a 11201 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
9e62e912 11202 bnx2x_get_ext_wwn_info(bp, func);
382e513a 11203 }
bf61ee14 11204
b306f5ed 11205 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 11206
bf61ee14
VZ		 11207 /*
11208 * If maximum allowed number of connections is zero -
2ba45142
VZ		 11209 * disable the feature.
11210 */
2ba45142
VZ		 11211 if (!bp->cnic_eth_dev.max_fcoe_conn)
11212 bp->flags |= NO_FCOE_FLAG;
11213}
b306f5ed 11214
0329aba1 11215static void bnx2x_get_cnic_info(struct bnx2x *bp)
b306f5ed
DK		 11216{
11217 /*
11218 * iSCSI may be dynamically disabled but reading
11219 * info here we will decrease memory usage by driver
11220 * if the feature is disabled for good
11221 */
11222 bnx2x_get_iscsi_info(bp);
11223 bnx2x_get_fcoe_info(bp);
11224}
2ba45142 11225
0329aba1 11226static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
0793f83f
DK		 11227{
11228 u32 val, val2;
11229 int func = BP_ABS_FUNC(bp);
11230 int port = BP_PORT(bp);
2ba45142
VZ		 11231 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11232 u8 *fip_mac = bp->fip_mac;
0793f83f 11233
55c11941
MS		 11234 if (IS_MF(bp)) {
11235 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142 11236 * FCoE MAC then the appropriate feature should be disabled.
55c11941
MS		 11237 * In non SD mode features configuration comes from struct
11238 * func_ext_config.
2ba45142 11239 */
55c11941 11240 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
0793f83f
DK		 11241 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11242 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11243 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11244 iscsi_mac_addr_upper);
0793f83f 11245 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11246 iscsi_mac_addr_lower);
2ba45142 11247 bnx2x_set_mac_buf(iscsi_mac, val, val2);
55c11941
MS		 11248 BNX2X_DEV_INFO
11249 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11250 } else {
2ba45142 11251 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
55c11941 11252 }
2ba45142
VZ		 11253
11254 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11255 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11256 fcoe_mac_addr_upper);
2ba45142 11257 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11258 fcoe_mac_addr_lower);
2ba45142 11259 bnx2x_set_mac_buf(fip_mac, val, val2);
55c11941
MS		 11260 BNX2X_DEV_INFO
11261 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11262 } else {
2ba45142 11263 bp->flags |= NO_FCOE_FLAG;
55c11941 11264 }
a3348722
BW		 11265
11266 bp->mf_ext_config = cfg;
11267
9e62e912 11268 } else { /* SD MODE */
55c11941
MS		 11269 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11270 /* use primary mac as iscsi mac */
11271 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11272
11273 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11274 BNX2X_DEV_INFO
11275 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11276 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11277 /* use primary mac as fip mac */
11278 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11279 BNX2X_DEV_INFO("SD FCoE MODE\n");
11280 BNX2X_DEV_INFO
11281 ("Read FIP MAC: %pM\n", fip_mac);
614c76df 11282 }
0793f83f 11283 }
a3348722 11284
82594f8f
YM		 11285 /* If this is a storage-only interface, use SAN mac as
11286 * primary MAC. Notice that for SD this is already the case,
11287 * as the SAN mac was copied from the primary MAC.
11288 */
11289 if (IS_MF_FCOE_AFEX(bp))
a3348722 11290 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
0793f83f 11291 } else {
0793f83f 11292 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11293 iscsi_mac_upper);
0793f83f 11294 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11295 iscsi_mac_lower);
2ba45142 11296 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 11297
11298 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11299 fcoe_fip_mac_upper);
c03bd39c 11300 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11301 fcoe_fip_mac_lower);
c03bd39c 11302 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 11303 }
11304
55c11941 11305 /* Disable iSCSI OOO if MAC configuration is invalid. */
426b9241 11306 if (!is_valid_ether_addr(iscsi_mac)) {
55c11941 11307 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
426b9241
DK		 11308 memset(iscsi_mac, 0, ETH_ALEN);
11309 }
11310
55c11941 11311 /* Disable FCoE if MAC configuration is invalid. */
426b9241
DK		 11312 if (!is_valid_ether_addr(fip_mac)) {
11313 bp->flags |= NO_FCOE_FLAG;
11314 memset(bp->fip_mac, 0, ETH_ALEN);
11315 }
55c11941
MS		 11316}
11317
0329aba1 11318static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
55c11941
MS		 11319{
11320 u32 val, val2;
11321 int func = BP_ABS_FUNC(bp);
11322 int port = BP_PORT(bp);
11323
11324 /* Zero primary MAC configuration */
11325 memset(bp->dev->dev_addr, 0, ETH_ALEN);
11326
11327 if (BP_NOMCP(bp)) {
11328 BNX2X_ERROR("warning: random MAC workaround active\n");
11329 eth_hw_addr_random(bp->dev);
11330 } else if (IS_MF(bp)) {
11331 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11332 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11333 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11334 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11335 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11336
11337 if (CNIC_SUPPORT(bp))
11338 bnx2x_get_cnic_mac_hwinfo(bp);
11339 } else {
11340 /* in SF read MACs from port configuration */
11341 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11342 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11343 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11344
11345 if (CNIC_SUPPORT(bp))
11346 bnx2x_get_cnic_mac_hwinfo(bp);
11347 }
11348
3d7d562c
YM		 11349 if (!BP_NOMCP(bp)) {
11350 /* Read physical port identifier from shmem */
11351 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11352 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11353 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11354 bp->flags |= HAS_PHYS_PORT_ID;
11355 }
11356
55c11941 11357 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
619c5cb6 11358
614c76df 11359 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
619c5cb6 11360 dev_err(&bp->pdev->dev,
51c1a580
MS		 11361 "bad Ethernet MAC address configuration: %pM\n"
11362 "change it manually before bringing up the appropriate network interface\n",
0f9dad10 11363 bp->dev->dev_addr);
7964211d 11364}
51c1a580 11365
0329aba1 11366static bool bnx2x_get_dropless_info(struct bnx2x *bp)
7964211d
YM		 11367{
11368 int tmp;
11369 u32 cfg;
51c1a580 11370
aeeddb8b
YM		 11371 if (IS_VF(bp))
11372 return 0;
11373
7964211d
YM		 11374 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11375 /* Take function: tmp = func */
11376 tmp = BP_ABS_FUNC(bp);
11377 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11378 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11379 } else {
11380 /* Take port: tmp = port */
11381 tmp = BP_PORT(bp);
11382 cfg = SHMEM_RD(bp,
11383 dev_info.port_hw_config[tmp].generic_features);
11384 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11385 }
11386 return cfg;
34f80b04
EG		 11387}
11388
0329aba1 11389static int bnx2x_get_hwinfo(struct bnx2x *bp)
34f80b04 11390{
0793f83f 11391 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 11392 int vn;
0793f83f 11393 u32 val = 0;
34f80b04 11394 int rc = 0;
a2fbb9ea 11395
34f80b04 11396 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 11397
6383c0b3
AE		 11398 /*
11399 * initialize IGU parameters
11400 */
f2e0899f
DK		 11401 if (CHIP_IS_E1x(bp)) {
11402 bp->common.int_block = INT_BLOCK_HC;
11403
11404 bp->igu_dsb_id = DEF_SB_IGU_ID;
11405 bp->igu_base_sb = 0;
f2e0899f
DK		 11406 } else {
11407 bp->common.int_block = INT_BLOCK_IGU;
7a06a122 11408
16a5fd92 11409 /* do not allow device reset during IGU info processing */
7a06a122
DK		 11410 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11411
f2e0899f 11412 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 11413
11414 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11415 int tout = 5000;
11416
11417 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11418
11419 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11420 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11421 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11422
11423 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11424 tout--;
0926d499 11425 usleep_range(1000, 2000);
619c5cb6
VZ		 11426 }
11427
11428 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11429 dev_err(&bp->pdev->dev,
11430 "FORCING Normal Mode failed!!!\n");
9b341bb1
BW		 11431 bnx2x_release_hw_lock(bp,
11432 HW_LOCK_RESOURCE_RESET);
619c5cb6
VZ		 11433 return -EPERM;
11434 }
11435 }
11436
f2e0899f 11437 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 11438 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 11439 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11440 } else
619c5cb6 11441 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 11442
9b341bb1 11443 rc = bnx2x_get_igu_cam_info(bp);
7a06a122 11444 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9b341bb1
BW		 11445 if (rc)
11446 return rc;
f2e0899f 11447 }
619c5cb6
VZ		 11448
11449 /*
11450 * set base FW non-default (fast path) status block id, this value is
11451 * used to initialize the fw_sb_id saved on the fp/queue structure to
11452 * determine the id used by the FW.
11453 */
11454 if (CHIP_IS_E1x(bp))
11455 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11456 else /*
11457 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11458 * the same queue are indicated on the same IGU SB). So we prefer
11459 * FW and IGU SBs to be the same value.
11460 */
11461 bp->base_fw_ndsb = bp->igu_base_sb;
11462
11463 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11464 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11465 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 11466
11467 /*
11468 * Initialize MF configuration
11469 */
523224a3 11470
fb3bff17
DK		 11471 bp->mf_ov = 0;
11472 bp->mf_mode = 0;
3395a033 11473 vn = BP_VN(bp);
0793f83f 11474
f2e0899f 11475 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 11476 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11477 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11478 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11479
f2e0899f
DK		 11480 if (SHMEM2_HAS(bp, mf_cfg_addr))
11481 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11482 else
11483 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 11484 offsetof(struct shmem_region, func_mb) +
11485 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 11486 /*
11487 * get mf configuration:
16a5fd92 11488 * 1. Existence of MF configuration
0793f83f
DK		 11489 * 2. MAC address must be legal (check only upper bytes)
11490 * for Switch-Independent mode;
11491 * OVLAN must be legal for Switch-Dependent mode
11492 * 3. SF_MODE configures specific MF mode
11493 */
11494 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11495 /* get mf configuration */
11496 val = SHMEM_RD(bp,
11497 dev_info.shared_feature_config.config);
11498 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11499
11500 switch (val) {
11501 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11502 val = MF_CFG_RD(bp, func_mf_config[func].
11503 mac_upper);
11504 /* check for legal mac (upper bytes)*/
11505 if (val != 0xffff) {
11506 bp->mf_mode = MULTI_FUNCTION_SI;
11507 bp->mf_config[vn] = MF_CFG_RD(bp,
11508 func_mf_config[func].config);
11509 } else
51c1a580 11510 BNX2X_DEV_INFO("illegal MAC address for SI\n");
0793f83f 11511 break;
a3348722
BW		 11512 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11513 if ((!CHIP_IS_E1x(bp)) &&
11514 (MF_CFG_RD(bp, func_mf_config[func].
11515 mac_upper) != 0xffff) &&
11516 (SHMEM2_HAS(bp,
11517 afex_driver_support))) {
11518 bp->mf_mode = MULTI_FUNCTION_AFEX;
11519 bp->mf_config[vn] = MF_CFG_RD(bp,
11520 func_mf_config[func].config);
11521 } else {
11522 BNX2X_DEV_INFO("can not configure afex mode\n");
11523 }
11524 break;
0793f83f
DK		 11525 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11526 /* get OV configuration */
11527 val = MF_CFG_RD(bp,
11528 func_mf_config[FUNC_0].e1hov_tag);
11529 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11530
11531 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11532 bp->mf_mode = MULTI_FUNCTION_SD;
11533 bp->mf_config[vn] = MF_CFG_RD(bp,
11534 func_mf_config[func].config);
11535 } else
754a2f52 11536 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f 11537 break;
3786b942
AE		 11538 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11539 bp->mf_config[vn] = 0;
11540 break;
0793f83f
DK		 11541 default:
11542 /* Unknown configuration: reset mf_config */
11543 bp->mf_config[vn] = 0;
51c1a580 11544 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
0793f83f
DK		 11545 }
11546 }
a2fbb9ea 11547
2691d51d 11548 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 11549 IS_MF(bp) ? "multi" : "single");
2691d51d 11550
0793f83f
DK		 11551 switch (bp->mf_mode) {
11552 case MULTI_FUNCTION_SD:
11553 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11554 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 11555 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 11556 bp->mf_ov = val;
619c5cb6
VZ		 11557 bp->path_has_ovlan = true;
11558
51c1a580
MS		 11559 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11560 func, bp->mf_ov, bp->mf_ov);
2691d51d 11561 } else {
619c5cb6 11562 dev_err(&bp->pdev->dev,
51c1a580
MS		 11563 "No valid MF OV for func %d, aborting\n",
11564 func);
619c5cb6 11565 return -EPERM;
34f80b04 11566 }
0793f83f 11567 break;
a3348722
BW		 11568 case MULTI_FUNCTION_AFEX:
11569 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11570 break;
0793f83f 11571 case MULTI_FUNCTION_SI:
51c1a580
MS		 11572 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11573 func);
0793f83f
DK		 11574 break;
11575 default:
11576 if (vn) {
619c5cb6 11577 dev_err(&bp->pdev->dev,
51c1a580
MS		 11578 "VN %d is in a single function mode, aborting\n",
11579 vn);
619c5cb6 11580 return -EPERM;
2691d51d 11581 }
0793f83f 11582 break;
34f80b04 11583 }
0793f83f 11584
619c5cb6
VZ		 11585 /* check if other port on the path needs ovlan:
11586 * Since MF configuration is shared between ports
11587 * Possible mixed modes are only
11588 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11589 */
11590 if (CHIP_MODE_IS_4_PORT(bp) &&
11591 !bp->path_has_ovlan &&
11592 !IS_MF(bp) &&
11593 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11594 u8 other_port = !BP_PORT(bp);
11595 u8 other_func = BP_PATH(bp) + 2*other_port;
11596 val = MF_CFG_RD(bp,
11597 func_mf_config[other_func].e1hov_tag);
11598 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11599 bp->path_has_ovlan = true;
11600 }
34f80b04 11601 }
a2fbb9ea 11602
e848582c
DK		 11603 /* adjust igu_sb_cnt to MF for E1H */
11604 if (CHIP_IS_E1H(bp) && IS_MF(bp))
11605 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
523224a3 11606
619c5cb6
VZ		 11607 /* port info */
11608 bnx2x_get_port_hwinfo(bp);
f2e0899f 11609
0793f83f
DK		 11610 /* Get MAC addresses */
11611 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 11612
2ba45142 11613 bnx2x_get_cnic_info(bp);
2ba45142 11614
34f80b04
EG		 11615 return rc;
11616}
11617
0329aba1 11618static void bnx2x_read_fwinfo(struct bnx2x *bp)
34f24c7f
VZ		 11619{
11620 int cnt, i, block_end, rodi;
fcdf95cb 11621 char vpd_start[BNX2X_VPD_LEN+1];
34f24c7f
VZ		 11622 char str_id_reg[VENDOR_ID_LEN+1];
11623 char str_id_cap[VENDOR_ID_LEN+1];
fcdf95cb
BW		 11624 char *vpd_data;
11625 char *vpd_extended_data = NULL;
34f24c7f
VZ		 11626 u8 len;
11627
fcdf95cb 11628 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
34f24c7f
VZ		 11629 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11630
11631 if (cnt < BNX2X_VPD_LEN)
11632 goto out_not_found;
11633
fcdf95cb
BW		 11634 /* VPD RO tag should be first tag after identifier string, hence
11635 * we should be able to find it in first BNX2X_VPD_LEN chars
11636 */
11637 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
34f24c7f
VZ		 11638 PCI_VPD_LRDT_RO_DATA);
11639 if (i < 0)
11640 goto out_not_found;
11641
34f24c7f 11642 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
fcdf95cb 11643 pci_vpd_lrdt_size(&vpd_start[i]);
34f24c7f
VZ		 11644
11645 i += PCI_VPD_LRDT_TAG_SIZE;
11646
fcdf95cb
BW		 11647 if (block_end > BNX2X_VPD_LEN) {
11648 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11649 if (vpd_extended_data == NULL)
11650 goto out_not_found;
11651
11652 /* read rest of vpd image into vpd_extended_data */
11653 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11654 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11655 block_end - BNX2X_VPD_LEN,
11656 vpd_extended_data + BNX2X_VPD_LEN);
11657 if (cnt < (block_end - BNX2X_VPD_LEN))
11658 goto out_not_found;
11659 vpd_data = vpd_extended_data;
11660 } else
11661 vpd_data = vpd_start;
11662
11663 /* now vpd_data holds full vpd content in both cases */
34f24c7f
VZ		 11664
11665 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11666 PCI_VPD_RO_KEYWORD_MFR_ID);
11667 if (rodi < 0)
11668 goto out_not_found;
11669
11670 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11671
11672 if (len != VENDOR_ID_LEN)
11673 goto out_not_found;
11674
11675 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11676
11677 /* vendor specific info */
11678 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11679 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11680 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11681 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11682
11683 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11684 PCI_VPD_RO_KEYWORD_VENDOR0);
11685 if (rodi >= 0) {
11686 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11687
11688 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11689
11690 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11691 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11692 bp->fw_ver[len] = ' ';
11693 }
11694 }
fcdf95cb 11695 kfree(vpd_extended_data);
34f24c7f
VZ		 11696 return;
11697 }
11698out_not_found:
fcdf95cb 11699 kfree(vpd_extended_data);
34f24c7f
VZ		 11700 return;
11701}
11702
0329aba1 11703static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
619c5cb6
VZ		 11704{
11705 u32 flags = 0;
11706
11707 if (CHIP_REV_IS_FPGA(bp))
11708 SET_FLAGS(flags, MODE_FPGA);
11709 else if (CHIP_REV_IS_EMUL(bp))
11710 SET_FLAGS(flags, MODE_EMUL);
11711 else
11712 SET_FLAGS(flags, MODE_ASIC);
11713
11714 if (CHIP_MODE_IS_4_PORT(bp))
11715 SET_FLAGS(flags, MODE_PORT4);
11716 else
11717 SET_FLAGS(flags, MODE_PORT2);
11718
11719 if (CHIP_IS_E2(bp))
11720 SET_FLAGS(flags, MODE_E2);
11721 else if (CHIP_IS_E3(bp)) {
11722 SET_FLAGS(flags, MODE_E3);
11723 if (CHIP_REV(bp) == CHIP_REV_Ax)
11724 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 11725 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11726 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 11727 }
11728
11729 if (IS_MF(bp)) {
11730 SET_FLAGS(flags, MODE_MF);
11731 switch (bp->mf_mode) {
11732 case MULTI_FUNCTION_SD:
11733 SET_FLAGS(flags, MODE_MF_SD);
11734 break;
11735 case MULTI_FUNCTION_SI:
11736 SET_FLAGS(flags, MODE_MF_SI);
11737 break;
a3348722
BW		 11738 case MULTI_FUNCTION_AFEX:
11739 SET_FLAGS(flags, MODE_MF_AFEX);
11740 break;
619c5cb6
VZ		 11741 }
11742 } else
11743 SET_FLAGS(flags, MODE_SF);
11744
11745#if defined(__LITTLE_ENDIAN)
11746 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11747#else /*(__BIG_ENDIAN)*/
11748 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11749#endif
11750 INIT_MODE_FLAGS(bp) = flags;
11751}
11752
0329aba1 11753static int bnx2x_init_bp(struct bnx2x *bp)
34f80b04 11754{
f2e0899f 11755 int func;
34f80b04
EG		 11756 int rc;
11757
34f80b04 11758 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 11759 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 11760 spin_lock_init(&bp->stats_lock);
507393eb 11761 sema_init(&bp->stats_sema, 1);
55c11941 11762
1cf167f2 11763 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 11764 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 11765 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
1ab4434c
AE		 11766 if (IS_PF(bp)) {
11767 rc = bnx2x_get_hwinfo(bp);
11768 if (rc)
11769 return rc;
11770 } else {
e09b74d0 11771 eth_zero_addr(bp->dev->dev_addr);
1ab4434c 11772 }
34f80b04 11773
619c5cb6
VZ		 11774 bnx2x_set_modes_bitmap(bp);
11775
11776 rc = bnx2x_alloc_mem_bp(bp);
11777 if (rc)
11778 return rc;
523224a3 11779
34f24c7f 11780 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 11781
11782 func = BP_FUNC(bp);
11783
34f80b04 11784 /* need to reset chip if undi was active */
1ab4434c 11785 if (IS_PF(bp) && !BP_NOMCP(bp)) {
452427b0
YM		 11786 /* init fw_seq */
11787 bp->fw_seq =
11788 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11789 DRV_MSG_SEQ_NUMBER_MASK;
11790 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11791
91ebb929
YM		 11792 rc = bnx2x_prev_unload(bp);
11793 if (rc) {
11794 bnx2x_free_mem_bp(bp);
11795 return rc;
11796 }
452427b0
YM		 11797 }
11798
34f80b04 11799 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 11800 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 11801
11802 if (BP_NOMCP(bp) && (func == 0))
51c1a580 11803 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
34f80b04 11804
614c76df 11805 bp->disable_tpa = disable_tpa;
a3348722 11806 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
614c76df 11807
7a9b2557 11808 /* Set TPA flags */
614c76df 11809 if (bp->disable_tpa) {
621b4d66 11810 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 11811 bp->dev->features &= ~NETIF_F_LRO;
11812 } else {
621b4d66 11813 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 11814 bp->dev->features |= NETIF_F_LRO;
11815 }
11816
a18f5128
EG		 11817 if (CHIP_IS_E1(bp))
11818 bp->dropless_fc = 0;
11819 else
7964211d 11820 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
a18f5128 11821
8d5726c4 11822 bp->mrrs = mrrs;
7a9b2557 11823
a3348722 11824 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1ab4434c
AE		 11825 if (IS_VF(bp))
11826 bp->rx_ring_size = MAX_RX_AVAIL;
34f80b04 11827
7d323bfd 11828 /* make sure that the numbers are in the right granularity */
523224a3
DK		 11829 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11830 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 11831
fc543637 11832 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
34f80b04
EG		 11833
11834 init_timer(&bp->timer);
11835 bp->timer.expires = jiffies + bp->current_interval;
11836 bp->timer.data = (unsigned long) bp;
11837 bp->timer.function = bnx2x_timer;
11838
0370cf90
BW		 11839 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11840 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11841 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11842 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11843 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11844 bnx2x_dcbx_init_params(bp);
11845 } else {
11846 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11847 }
e4901dde 11848
619c5cb6
VZ		 11849 if (CHIP_IS_E1x(bp))
11850 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11851 else
11852 bp->cnic_base_cl_id = FP_SB_MAX_E2;
619c5cb6 11853
6383c0b3 11854 /* multiple tx priority */
1ab4434c
AE		 11855 if (IS_VF(bp))
11856 bp->max_cos = 1;
11857 else if (CHIP_IS_E1x(bp))
6383c0b3 11858 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
1ab4434c 11859 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
6383c0b3 11860 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
1ab4434c 11861 else if (CHIP_IS_E3B0(bp))
6383c0b3 11862 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
1ab4434c
AE		 11863 else
11864 BNX2X_ERR("unknown chip %x revision %x\n",
11865 CHIP_NUM(bp), CHIP_REV(bp));
11866 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
6383c0b3 11867
55c11941
MS		 11868 /* We need at least one default status block for slow-path events,
11869 * second status block for the L2 queue, and a third status block for
16a5fd92 11870 * CNIC if supported.
55c11941 11871 */
60cad4e6
AE		 11872 if (IS_VF(bp))
11873 bp->min_msix_vec_cnt = 1;
11874 else if (CNIC_SUPPORT(bp))
55c11941 11875 bp->min_msix_vec_cnt = 3;
60cad4e6 11876 else /* PF w/o cnic */
55c11941
MS		 11877 bp->min_msix_vec_cnt = 2;
11878 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11879
5bb680d6
MS		 11880 bp->dump_preset_idx = 1;
11881
34f80b04 11882 return rc;
a2fbb9ea
ET		 11883}
11884
de0c62db
DK		 11885/****************************************************************************
11886* General service functions
11887****************************************************************************/
a2fbb9ea 11888
619c5cb6
VZ		 11889/*
11890 * net_device service functions
11891 */
11892
bb2a0f7a 11893/* called with rtnl_lock */
a2fbb9ea
ET		 11894static int bnx2x_open(struct net_device *dev)
11895{
11896 struct bnx2x *bp = netdev_priv(dev);
8395be5e 11897 int rc;
a2fbb9ea 11898
1355b704
MY		 11899 bp->stats_init = true;
11900
6eccabb3
EG		 11901 netif_carrier_off(dev);
11902
a2fbb9ea
ET		 11903 bnx2x_set_power_state(bp, PCI_D0);
11904
ad5afc89 11905 /* If parity had happen during the unload, then attentions
c9ee9206
VZ		 11906 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11907 * want the first function loaded on the current engine to
11908 * complete the recovery.
ad5afc89 11909 * Parity recovery is only relevant for PF driver.
c9ee9206 11910 */
ad5afc89 11911 if (IS_PF(bp)) {
1a6974b2
YM		 11912 int other_engine = BP_PATH(bp) ? 0 : 1;
11913 bool other_load_status, load_status;
11914 bool global = false;
11915
ad5afc89
AE		 11916 other_load_status = bnx2x_get_load_status(bp, other_engine);
11917 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11918 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11919 bnx2x_chk_parity_attn(bp, &global, true)) {
11920 do {
11921 /* If there are attentions and they are in a
11922 * global blocks, set the GLOBAL_RESET bit
11923 * regardless whether it will be this function
11924 * that will complete the recovery or not.
11925 */
11926 if (global)
11927 bnx2x_set_reset_global(bp);
72fd0718 11928
ad5afc89
AE		 11929 /* Only the first function on the current
11930 * engine should try to recover in open. In case
11931 * of attentions in global blocks only the first
11932 * in the chip should try to recover.
11933 */
11934 if ((!load_status &&
11935 (!global || !other_load_status)) &&
11936 bnx2x_trylock_leader_lock(bp) &&
11937 !bnx2x_leader_reset(bp)) {
11938 netdev_info(bp->dev,
11939 "Recovered in open\n");
11940 break;
11941 }
72fd0718 11942
ad5afc89
AE		 11943 /* recovery has failed... */
11944 bnx2x_set_power_state(bp, PCI_D3hot);
11945 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 11946
ad5afc89
AE		 11947 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11948 "If you still see this message after a few retries then power cycle is required.\n");
72fd0718 11949
ad5afc89
AE		 11950 return -EAGAIN;
11951 } while (0);
11952 }
11953 }
72fd0718
VZ		 11954
11955 bp->recovery_state = BNX2X_RECOVERY_DONE;
8395be5e
AE		 11956 rc = bnx2x_nic_load(bp, LOAD_OPEN);
11957 if (rc)
11958 return rc;
9a8130bc 11959 return 0;
a2fbb9ea
ET		 11960}
11961
bb2a0f7a 11962/* called with rtnl_lock */
56ad3152 11963static int bnx2x_close(struct net_device *dev)
a2fbb9ea 11964{
a2fbb9ea
ET		 11965 struct bnx2x *bp = netdev_priv(dev);
11966
11967 /* Unload the driver, release IRQs */
5d07d868 11968 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
c9ee9206 11969
a2fbb9ea
ET		 11970 return 0;
11971}
11972
1191cb83
ED		 11973static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11974 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 11975{
619c5cb6
VZ		 11976 int mc_count = netdev_mc_count(bp->dev);
11977 struct bnx2x_mcast_list_elem *mc_mac =
cd2b0389 11978 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
619c5cb6 11979 struct netdev_hw_addr *ha;
6e30dd4e 11980
619c5cb6
VZ		 11981 if (!mc_mac)
11982 return -ENOMEM;
6e30dd4e 11983
619c5cb6 11984 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 11985
619c5cb6
VZ		 11986 netdev_for_each_mc_addr(ha, bp->dev) {
11987 mc_mac->mac = bnx2x_mc_addr(ha);
11988 list_add_tail(&mc_mac->link, &p->mcast_list);
11989 mc_mac++;
6e30dd4e 11990 }
619c5cb6
VZ		 11991
11992 p->mcast_list_len = mc_count;
11993
11994 return 0;
6e30dd4e
VZ		 11995}
11996
1191cb83 11997static void bnx2x_free_mcast_macs_list(
619c5cb6
VZ		 11998 struct bnx2x_mcast_ramrod_params *p)
11999{
12000 struct bnx2x_mcast_list_elem *mc_mac =
12001 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12002 link);
12003
12004 WARN_ON(!mc_mac);
12005 kfree(mc_mac);
12006}
12007
12008/**
12009 * bnx2x_set_uc_list - configure a new unicast MACs list.
12010 *
12011 * @bp: driver handle
6e30dd4e 12012 *
619c5cb6 12013 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 12014 */
1191cb83 12015static int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 12016{
619c5cb6 12017 int rc;
6e30dd4e 12018 struct net_device *dev = bp->dev;
6e30dd4e 12019 struct netdev_hw_addr *ha;
15192a8c 12020 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
619c5cb6 12021 unsigned long ramrod_flags = 0;
6e30dd4e 12022
619c5cb6
VZ		 12023 /* First schedule a cleanup up of old configuration */
12024 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12025 if (rc < 0) {
12026 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12027 return rc;
12028 }
6e30dd4e
VZ		 12029
12030 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 12031 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12032 BNX2X_UC_LIST_MAC, &ramrod_flags);
7b5342d9
YM		 12033 if (rc == -EEXIST) {
12034 DP(BNX2X_MSG_SP,
12035 "Failed to schedule ADD operations: %d\n", rc);
12036 /* do not treat adding same MAC as error */
12037 rc = 0;
12038
12039 } else if (rc < 0) {
12040
619c5cb6
VZ		 12041 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12042 rc);
12043 return rc;
6e30dd4e
VZ		 12044 }
12045 }
12046
619c5cb6
VZ		 12047 /* Execute the pending commands */
12048 __set_bit(RAMROD_CONT, &ramrod_flags);
12049 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12050 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 12051}
12052
1191cb83 12053static int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 12054{
619c5cb6 12055 struct net_device *dev = bp->dev;
3b603066 12056 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6 12057 int rc = 0;
6e30dd4e 12058
619c5cb6 12059 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 12060
619c5cb6
VZ		 12061 /* first, clear all configured multicast MACs */
12062 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12063 if (rc < 0) {
51c1a580 12064 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
619c5cb6
VZ		 12065 return rc;
12066 }
6e30dd4e 12067
619c5cb6
VZ		 12068 /* then, configure a new MACs list */
12069 if (netdev_mc_count(dev)) {
12070 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12071 if (rc) {
51c1a580
MS		 12072 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12073 rc);
619c5cb6
VZ		 12074 return rc;
12075 }
6e30dd4e 12076
619c5cb6
VZ		 12077 /* Now add the new MACs */
12078 rc = bnx2x_config_mcast(bp, &rparam,
12079 BNX2X_MCAST_CMD_ADD);
12080 if (rc < 0)
51c1a580
MS		 12081 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12082 rc);
6e30dd4e 12083
619c5cb6
VZ		 12084 bnx2x_free_mcast_macs_list(&rparam);
12085 }
6e30dd4e 12086
619c5cb6 12087 return rc;
6e30dd4e
VZ		 12088}
12089
619c5cb6 12090/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
a8f47eb7 12091static void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 12092{
12093 struct bnx2x *bp = netdev_priv(dev);
34f80b04
EG		 12094
12095 if (bp->state != BNX2X_STATE_OPEN) {
12096 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12097 return;
8b09be5f
YM		 12098 } else {
12099 /* Schedule an SP task to handle rest of change */
230bb0f3
YM		 12100 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12101 NETIF_MSG_IFUP);
34f80b04 12102 }
8b09be5f
YM		 12103}
12104
12105void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12106{
12107 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04 12108
619c5cb6 12109 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04 12110
8b09be5f
YM		 12111 netif_addr_lock_bh(bp->dev);
12112
12113 if (bp->dev->flags & IFF_PROMISC) {
34f80b04 12114 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f
YM		 12115 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12116 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12117 CHIP_IS_E1(bp))) {
34f80b04 12118 rx_mode = BNX2X_RX_MODE_ALLMULTI;
8b09be5f 12119 } else {
381ac16b
AE		 12120 if (IS_PF(bp)) {
12121 /* some multicasts */
12122 if (bnx2x_set_mc_list(bp) < 0)
12123 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 12124
8b09be5f
YM		 12125 /* release bh lock, as bnx2x_set_uc_list might sleep */
12126 netif_addr_unlock_bh(bp->dev);
381ac16b
AE		 12127 if (bnx2x_set_uc_list(bp) < 0)
12128 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f 12129 netif_addr_lock_bh(bp->dev);
381ac16b
AE		 12130 } else {
12131 /* configuring mcast to a vf involves sleeping (when we
8b09be5f 12132 * wait for the pf's response).
381ac16b 12133 */
230bb0f3
YM		 12134 bnx2x_schedule_sp_rtnl(bp,
12135 BNX2X_SP_RTNL_VFPF_MCAST, 0);
381ac16b 12136 }
34f80b04
EG		 12137 }
12138
12139 bp->rx_mode = rx_mode;
614c76df
DK		 12140 /* handle ISCSI SD mode */
12141 if (IS_MF_ISCSI_SD(bp))
12142 bp->rx_mode = BNX2X_RX_MODE_NONE;
619c5cb6
VZ		 12143
12144 /* Schedule the rx_mode command */
12145 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12146 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8b09be5f 12147 netif_addr_unlock_bh(bp->dev);
619c5cb6
VZ		 12148 return;
12149 }
12150
381ac16b
AE		 12151 if (IS_PF(bp)) {
12152 bnx2x_set_storm_rx_mode(bp);
8b09be5f 12153 netif_addr_unlock_bh(bp->dev);
381ac16b 12154 } else {
8b09be5f
YM		 12155 /* VF will need to request the PF to make this change, and so
12156 * the VF needs to release the bottom-half lock prior to the
12157 * request (as it will likely require sleep on the VF side)
381ac16b 12158 */
8b09be5f
YM		 12159 netif_addr_unlock_bh(bp->dev);
12160 bnx2x_vfpf_storm_rx_mode(bp);
381ac16b 12161 }
34f80b04
EG		 12162}
12163
c18487ee 12164/* called with rtnl_lock */
01cd4528
EG		 12165static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12166 int devad, u16 addr)
a2fbb9ea 12167{
01cd4528
EG		 12168 struct bnx2x *bp = netdev_priv(netdev);
12169 u16 value;
12170 int rc;
a2fbb9ea 12171
01cd4528
EG		 12172 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12173 prtad, devad, addr);
a2fbb9ea 12174
01cd4528
EG		 12175 /* The HW expects different devad if CL22 is used */
12176 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 12177
01cd4528 12178 bnx2x_acquire_phy_lock(bp);
e10bc84d 12179 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 12180 bnx2x_release_phy_lock(bp);
12181 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 12182
01cd4528
EG		 12183 if (!rc)
12184 rc = value;
12185 return rc;
12186}
a2fbb9ea 12187
01cd4528
EG		 12188/* called with rtnl_lock */
12189static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12190 u16 addr, u16 value)
12191{
12192 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 12193 int rc;
12194
51c1a580
MS		 12195 DP(NETIF_MSG_LINK,
12196 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12197 prtad, devad, addr, value);
01cd4528 12198
01cd4528
EG		 12199 /* The HW expects different devad if CL22 is used */
12200 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 12201
01cd4528 12202 bnx2x_acquire_phy_lock(bp);
e10bc84d 12203 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 12204 bnx2x_release_phy_lock(bp);
12205 return rc;
12206}
c18487ee 12207
01cd4528
EG		 12208/* called with rtnl_lock */
12209static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12210{
12211 struct bnx2x *bp = netdev_priv(dev);
12212 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 12213
01cd4528
EG		 12214 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12215 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 12216
01cd4528
EG		 12217 if (!netif_running(dev))
12218 return -EAGAIN;
12219
12220 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 12221}
12222
257ddbda 12223#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 12224static void poll_bnx2x(struct net_device *dev)
12225{
12226 struct bnx2x *bp = netdev_priv(dev);
14a15d61 12227 int i;
a2fbb9ea 12228
14a15d61
MS		 12229 for_each_eth_queue(bp, i) {
12230 struct bnx2x_fastpath *fp = &bp->fp[i];
12231 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12232 }
a2fbb9ea
ET		 12233}
12234#endif
12235
614c76df
DK		 12236static int bnx2x_validate_addr(struct net_device *dev)
12237{
12238 struct bnx2x *bp = netdev_priv(dev);
12239
e09b74d0
AE		 12240 /* query the bulletin board for mac address configured by the PF */
12241 if (IS_VF(bp))
12242 bnx2x_sample_bulletin(bp);
12243
51c1a580
MS		 12244 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
12245 BNX2X_ERR("Non-valid Ethernet address\n");
614c76df 12246 return -EADDRNOTAVAIL;
51c1a580 12247 }
614c76df
DK		 12248 return 0;
12249}
12250
3d7d562c
YM		 12251static int bnx2x_get_phys_port_id(struct net_device *netdev,
12252 struct netdev_phys_port_id *ppid)
12253{
12254 struct bnx2x *bp = netdev_priv(netdev);
12255
12256 if (!(bp->flags & HAS_PHYS_PORT_ID))
12257 return -EOPNOTSUPP;
12258
12259 ppid->id_len = sizeof(bp->phys_port_id);
12260 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12261
12262 return 0;
12263}
12264
c64213cd
SH		 12265static const struct net_device_ops bnx2x_netdev_ops = {
12266 .ndo_open = bnx2x_open,
12267 .ndo_stop = bnx2x_close,
12268 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 12269 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 12270 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 12271 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 12272 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 12273 .ndo_do_ioctl = bnx2x_ioctl,
12274 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 12275 .ndo_fix_features = bnx2x_fix_features,
12276 .ndo_set_features = bnx2x_set_features,
c64213cd 12277 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 12278#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 12279 .ndo_poll_controller = poll_bnx2x,
12280#endif
6383c0b3 12281 .ndo_setup_tc = bnx2x_setup_tc,
6411280a 12282#ifdef CONFIG_BNX2X_SRIOV
abc5a021 12283 .ndo_set_vf_mac = bnx2x_set_vf_mac,
3cdeec22 12284 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
3ec9f9ca 12285 .ndo_get_vf_config = bnx2x_get_vf_config,
6411280a 12286#endif
55c11941 12287#ifdef NETDEV_FCOE_WWNN
bf61ee14
VZ		 12288 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
12289#endif
8f20aa57 12290
e0d1095a 12291#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 12292 .ndo_busy_poll = bnx2x_low_latency_recv,
8f20aa57 12293#endif
3d7d562c 12294 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
c64213cd
SH		 12295};
12296
1191cb83 12297static int bnx2x_set_coherency_mask(struct bnx2x *bp)
619c5cb6
VZ		 12298{
12299 struct device *dev = &bp->pdev->dev;
12300
8ceafbfa
LT		 12301 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12302 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
619c5cb6
VZ		 12303 dev_err(dev, "System does not support DMA, aborting\n");
12304 return -EIO;
12305 }
12306
12307 return 0;
12308}
12309
33d8e6a5
YM		 12310static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12311{
12312 if (bp->flags & AER_ENABLED) {
12313 pci_disable_pcie_error_reporting(bp->pdev);
12314 bp->flags &= ~AER_ENABLED;
12315 }
12316}
12317
1ab4434c
AE		 12318static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12319 struct net_device *dev, unsigned long board_type)
a2fbb9ea 12320{
a2fbb9ea 12321 int rc;
c22610d0 12322 u32 pci_cfg_dword;
65087cfe
AE		 12323 bool chip_is_e1x = (board_type == BCM57710 ||
12324 board_type == BCM57711 ||
12325 board_type == BCM57711E);
a2fbb9ea
ET		 12326
12327 SET_NETDEV_DEV(dev, &pdev->dev);
a2fbb9ea 12328
34f80b04
EG		 12329 bp->dev = dev;
12330 bp->pdev = pdev;
a2fbb9ea
ET		 12331
12332 rc = pci_enable_device(pdev);
12333 if (rc) {
cdaa7cb8
VZ		 12334 dev_err(&bp->pdev->dev,
12335 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 12336 goto err_out;
12337 }
12338
12339 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 12340 dev_err(&bp->pdev->dev,
12341 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 12342 rc = -ENODEV;
12343 goto err_out_disable;
12344 }
12345
1ab4434c
AE		 12346 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12347 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
a2fbb9ea
ET		 12348 rc = -ENODEV;
12349 goto err_out_disable;
12350 }
12351
092a5fc9
YR		 12352 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12353 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12354 PCICFG_REVESION_ID_ERROR_VAL) {
12355 pr_err("PCI device error, probably due to fan failure, aborting\n");
12356 rc = -ENODEV;
12357 goto err_out_disable;
12358 }
12359
34f80b04
EG		 12360 if (atomic_read(&pdev->enable_cnt) == 1) {
12361 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12362 if (rc) {
cdaa7cb8
VZ		 12363 dev_err(&bp->pdev->dev,
12364 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 12365 goto err_out_disable;
12366 }
a2fbb9ea 12367
34f80b04
EG		 12368 pci_set_master(pdev);
12369 pci_save_state(pdev);
12370 }
a2fbb9ea 12371
1ab4434c 12372 if (IS_PF(bp)) {
29ed74c3 12373 if (!pdev->pm_cap) {
1ab4434c
AE		 12374 dev_err(&bp->pdev->dev,
12375 "Cannot find power management capability, aborting\n");
12376 rc = -EIO;
12377 goto err_out_release;
12378 }
a2fbb9ea
ET		 12379 }
12380
77c98e6a 12381 if (!pci_is_pcie(pdev)) {
51c1a580 12382 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 12383 rc = -EIO;
12384 goto err_out_release;
12385 }
12386
619c5cb6
VZ		 12387 rc = bnx2x_set_coherency_mask(bp);
12388 if (rc)
a2fbb9ea 12389 goto err_out_release;
a2fbb9ea 12390
34f80b04
EG		 12391 dev->mem_start = pci_resource_start(pdev, 0);
12392 dev->base_addr = dev->mem_start;
12393 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 12394
12395 dev->irq = pdev->irq;
12396
275f165f 12397 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 12398 if (!bp->regview) {
cdaa7cb8
VZ		 12399 dev_err(&bp->pdev->dev,
12400 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 12401 rc = -ENOMEM;
12402 goto err_out_release;
12403 }
12404
c22610d0
AE		 12405 /* In E1/E1H use pci device function given by kernel.
12406 * In E2/E3 read physical function from ME register since these chips
12407 * support Physical Device Assignment where kernel BDF maybe arbitrary
12408 * (depending on hypervisor).
12409 */
2de67439 12410 if (chip_is_e1x) {
c22610d0 12411 bp->pf_num = PCI_FUNC(pdev->devfn);
2de67439
YM		 12412 } else {
12413 /* chip is E2/3*/
c22610d0
AE		 12414 pci_read_config_dword(bp->pdev,
12415 PCICFG_ME_REGISTER, &pci_cfg_dword);
12416 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
2de67439 12417 ME_REG_ABS_PF_NUM_SHIFT);
c22610d0 12418 }
51c1a580 12419 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
c22610d0 12420
34f80b04
EG		 12421 /* clean indirect addresses */
12422 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12423 PCICFG_VENDOR_ID_OFFSET);
33d8e6a5
YM		 12424
12425 /* AER (Advanced Error reporting) configuration */
12426 rc = pci_enable_pcie_error_reporting(pdev);
12427 if (!rc)
12428 bp->flags |= AER_ENABLED;
12429 else
12430 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12431
a5c53dbc
DK		 12432 /*
12433 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 12434 * is not used by the driver.
12435 */
1ab4434c
AE		 12436 if (IS_PF(bp)) {
12437 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12438 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12439 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12440 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12441
12442 if (chip_is_e1x) {
12443 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12444 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12445 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12446 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12447 }
a5c53dbc 12448
1ab4434c
AE		 12449 /* Enable internal target-read (in case we are probed after PF
12450 * FLR). Must be done prior to any BAR read access. Only for
12451 * 57712 and up
12452 */
12453 if (!chip_is_e1x)
12454 REG_WR(bp,
12455 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
a5c53dbc 12456 }
a2fbb9ea 12457
34f80b04 12458 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 12459
c64213cd 12460 dev->netdev_ops = &bnx2x_netdev_ops;
005a07ba 12461 bnx2x_set_ethtool_ops(bp, dev);
5316bc0b 12462
01789349
JP		 12463 dev->priv_flags |= IFF_UNICAST_FLT;
12464
66371c44 12465 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
621b4d66
DK		 12466 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12467 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
f646968f 12468 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
a848ade4 12469 if (!CHIP_IS_E1x(bp)) {
117401ee 12470 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
2e3bd6a4 12471 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
a848ade4
DK		 12472 dev->hw_enc_features =
12473 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12474 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
117401ee 12475 NETIF_F_GSO_IPIP |
2e3bd6a4 12476 NETIF_F_GSO_SIT |
65bc0cfe 12477 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
a848ade4 12478 }
66371c44
MM		 12479
12480 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12481 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12482
f646968f 12483 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
edd31476 12484 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 12485
538dd2e3
MB		 12486 /* Add Loopback capability to the device */
12487 dev->hw_features |= NETIF_F_LOOPBACK;
12488
98507672 12489#ifdef BCM_DCBNL
785b9b1a
SR		 12490 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12491#endif
12492
01cd4528
EG		 12493 /* get_port_hwinfo() will set prtad and mmds properly */
12494 bp->mdio.prtad = MDIO_PRTAD_NONE;
12495 bp->mdio.mmds = 0;
12496 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12497 bp->mdio.dev = dev;
12498 bp->mdio.mdio_read = bnx2x_mdio_read;
12499 bp->mdio.mdio_write = bnx2x_mdio_write;
12500
a2fbb9ea
ET		 12501 return 0;
12502
a2fbb9ea 12503err_out_release:
34f80b04
EG		 12504 if (atomic_read(&pdev->enable_cnt) == 1)
12505 pci_release_regions(pdev);
a2fbb9ea
ET		 12506
12507err_out_disable:
12508 pci_disable_device(pdev);
a2fbb9ea
ET		 12509
12510err_out:
12511 return rc;
12512}
12513
6891dd25 12514static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 12515{
37f9ce62 12516 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 12517 struct bnx2x_fw_file_hdr *fw_hdr;
12518 struct bnx2x_fw_file_section *sections;
94a78b79 12519 u32 offset, len, num_ops;
86564c3f 12520 __be16 *ops_offsets;
94a78b79 12521 int i;
37f9ce62 12522 const u8 *fw_ver;
94a78b79 12523
51c1a580
MS		 12524 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12525 BNX2X_ERR("Wrong FW size\n");
94a78b79 12526 return -EINVAL;
51c1a580 12527 }
94a78b79
VZ		 12528
12529 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12530 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12531
12532 /* Make sure none of the offsets and sizes make us read beyond
12533 * the end of the firmware data */
12534 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12535 offset = be32_to_cpu(sections[i].offset);
12536 len = be32_to_cpu(sections[i].len);
12537 if (offset + len > firmware->size) {
51c1a580 12538 BNX2X_ERR("Section %d length is out of bounds\n", i);
94a78b79
VZ		 12539 return -EINVAL;
12540 }
12541 }
12542
12543 /* Likewise for the init_ops offsets */
12544 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
86564c3f 12545 ops_offsets = (__force __be16 *)(firmware->data + offset);
94a78b79
VZ		 12546 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12547
12548 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12549 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
51c1a580 12550 BNX2X_ERR("Section offset %d is out of bounds\n", i);
94a78b79
VZ		 12551 return -EINVAL;
12552 }
12553 }
12554
12555 /* Check FW version */
12556 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12557 fw_ver = firmware->data + offset;
12558 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12559 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12560 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12561 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
51c1a580
MS		 12562 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12563 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12564 BCM_5710_FW_MAJOR_VERSION,
94a78b79
VZ		 12565 BCM_5710_FW_MINOR_VERSION,
12566 BCM_5710_FW_REVISION_VERSION,
12567 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 12568 return -EINVAL;
94a78b79
VZ		 12569 }
12570
12571 return 0;
12572}
12573
1191cb83 12574static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 12575{
ab6ad5a4
EG		 12576 const __be32 *source = (const __be32 *)_source;
12577 u32 *target = (u32 *)_target;
94a78b79 12578 u32 i;
94a78b79
VZ		 12579
12580 for (i = 0; i < n/4; i++)
12581 target[i] = be32_to_cpu(source[i]);
12582}
12583
12584/*
12585 Ops array is stored in the following format:
12586 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12587 */
1191cb83 12588static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 12589{
ab6ad5a4
EG		 12590 const __be32 *source = (const __be32 *)_source;
12591 struct raw_op *target = (struct raw_op *)_target;
94a78b79 12592 u32 i, j, tmp;
94a78b79 12593
ab6ad5a4 12594 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 12595 tmp = be32_to_cpu(source[j]);
12596 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 12597 target[i].offset = tmp & 0xffffff;
12598 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 12599 }
12600}
ab6ad5a4 12601
1aa8b471 12602/* IRO array is stored in the following format:
523224a3
DK		 12603 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12604 */
1191cb83 12605static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
523224a3
DK		 12606{
12607 const __be32 *source = (const __be32 *)_source;
12608 struct iro *target = (struct iro *)_target;
12609 u32 i, j, tmp;
12610
12611 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12612 target[i].base = be32_to_cpu(source[j]);
12613 j++;
12614 tmp = be32_to_cpu(source[j]);
12615 target[i].m1 = (tmp >> 16) & 0xffff;
12616 target[i].m2 = tmp & 0xffff;
12617 j++;
12618 tmp = be32_to_cpu(source[j]);
12619 target[i].m3 = (tmp >> 16) & 0xffff;
12620 target[i].size = tmp & 0xffff;
12621 j++;
12622 }
12623}
12624
1191cb83 12625static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 12626{
ab6ad5a4
EG		 12627 const __be16 *source = (const __be16 *)_source;
12628 u16 *target = (u16 *)_target;
94a78b79 12629 u32 i;
94a78b79
VZ		 12630
12631 for (i = 0; i < n/2; i++)
12632 target[i] = be16_to_cpu(source[i]);
12633}
12634
7995c64e
JP		 12635#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12636do { \
12637 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12638 bp->arr = kmalloc(len, GFP_KERNEL); \
e404decb 12639 if (!bp->arr) \
7995c64e 12640 goto lbl; \
7995c64e
JP		 12641 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12642 (u8 *)bp->arr, len); \
12643} while (0)
94a78b79 12644
3b603066 12645static int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 12646{
c0ea452e 12647 const char *fw_file_name;
94a78b79 12648 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 12649 int rc;
94a78b79 12650
c0ea452e
MS		 12651 if (bp->firmware)
12652 return 0;
94a78b79 12653
c0ea452e
MS		 12654 if (CHIP_IS_E1(bp))
12655 fw_file_name = FW_FILE_NAME_E1;
12656 else if (CHIP_IS_E1H(bp))
12657 fw_file_name = FW_FILE_NAME_E1H;
12658 else if (!CHIP_IS_E1x(bp))
12659 fw_file_name = FW_FILE_NAME_E2;
12660 else {
12661 BNX2X_ERR("Unsupported chip revision\n");
12662 return -EINVAL;
12663 }
12664 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 12665
c0ea452e
MS		 12666 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12667 if (rc) {
12668 BNX2X_ERR("Can't load firmware file %s\n",
12669 fw_file_name);
12670 goto request_firmware_exit;
12671 }
eb2afd4a 12672
c0ea452e
MS		 12673 rc = bnx2x_check_firmware(bp);
12674 if (rc) {
12675 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12676 goto request_firmware_exit;
94a78b79
VZ		 12677 }
12678
12679 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12680
12681 /* Initialize the pointers to the init arrays */
12682 /* Blob */
12683 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12684
12685 /* Opcodes */
12686 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12687
12688 /* Offsets */
ab6ad5a4
EG		 12689 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12690 be16_to_cpu_n);
94a78b79
VZ		 12691
12692 /* STORMs firmware */
573f2035
EG		 12693 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12694 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12695 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12696 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12697 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12698 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12699 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12700 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12701 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12702 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12703 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12704 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12705 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12706 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12707 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12708 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 12709 /* IRO */
12710 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 12711
12712 return 0;
ab6ad5a4 12713
523224a3
DK		 12714iro_alloc_err:
12715 kfree(bp->init_ops_offsets);
94a78b79
VZ		 12716init_offsets_alloc_err:
12717 kfree(bp->init_ops);
12718init_ops_alloc_err:
12719 kfree(bp->init_data);
12720request_firmware_exit:
12721 release_firmware(bp->firmware);
127d0a19 12722 bp->firmware = NULL;
94a78b79
VZ		 12723
12724 return rc;
12725}
12726
619c5cb6
VZ		 12727static void bnx2x_release_firmware(struct bnx2x *bp)
12728{
12729 kfree(bp->init_ops_offsets);
12730 kfree(bp->init_ops);
12731 kfree(bp->init_data);
12732 release_firmware(bp->firmware);
eb2afd4a 12733 bp->firmware = NULL;
619c5cb6
VZ		 12734}
12735
619c5cb6
VZ		 12736static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12737 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12738 .init_hw_cmn = bnx2x_init_hw_common,
12739 .init_hw_port = bnx2x_init_hw_port,
12740 .init_hw_func = bnx2x_init_hw_func,
12741
12742 .reset_hw_cmn = bnx2x_reset_common,
12743 .reset_hw_port = bnx2x_reset_port,
12744 .reset_hw_func = bnx2x_reset_func,
12745
12746 .gunzip_init = bnx2x_gunzip_init,
12747 .gunzip_end = bnx2x_gunzip_end,
12748
12749 .init_fw = bnx2x_init_firmware,
12750 .release_fw = bnx2x_release_firmware,
12751};
12752
12753void bnx2x__init_func_obj(struct bnx2x *bp)
12754{
12755 /* Prepare DMAE related driver resources */
12756 bnx2x_setup_dmae(bp);
12757
12758 bnx2x_init_func_obj(bp, &bp->func_obj,
12759 bnx2x_sp(bp, func_rdata),
12760 bnx2x_sp_mapping(bp, func_rdata),
a3348722
BW		 12761 bnx2x_sp(bp, func_afex_rdata),
12762 bnx2x_sp_mapping(bp, func_afex_rdata),
619c5cb6
VZ		 12763 &bnx2x_func_sp_drv);
12764}
12765
12766/* must be called after sriov-enable */
1191cb83 12767static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 12768{
37ae41a9 12769 int cid_count = BNX2X_L2_MAX_CID(bp);
94a78b79 12770
290ca2bb
AE		 12771 if (IS_SRIOV(bp))
12772 cid_count += BNX2X_VF_CIDS;
12773
55c11941
MS		 12774 if (CNIC_SUPPORT(bp))
12775 cid_count += CNIC_CID_MAX;
290ca2bb 12776
523224a3
DK		 12777 return roundup(cid_count, QM_CID_ROUND);
12778}
f85582f8 12779
619c5cb6 12780/**
6383c0b3 12781 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 12782 *
12783 * @dev: pci device
12784 *
12785 */
60cad4e6 12786static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
619c5cb6 12787{
ae2104be 12788 int index;
1ab4434c 12789 u16 control = 0;
619c5cb6 12790
6383c0b3
AE		 12791 /*
12792 * If MSI-X is not supported - return number of SBs needed to support
12793 * one fast path queue: one FP queue + SB for CNIC
12794 */
ae2104be 12795 if (!pdev->msix_cap) {
1ab4434c 12796 dev_info(&pdev->dev, "no msix capability found\n");
55c11941 12797 return 1 + cnic_cnt;
1ab4434c
AE		 12798 }
12799 dev_info(&pdev->dev, "msix capability found\n");
619c5cb6 12800
6383c0b3
AE		 12801 /*
12802 * The value in the PCI configuration space is the index of the last
12803 * entry, namely one less than the actual size of the table, which is
12804 * exactly what we want to return from this function: number of all SBs
12805 * without the default SB.
1ab4434c 12806 * For VFs there is no default SB, then we return (index+1).
6383c0b3 12807 */
ae2104be 12808 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSI_FLAGS, &control);
619c5cb6 12809
1ab4434c 12810 index = control & PCI_MSIX_FLAGS_QSIZE;
4bd9b0ff 12811
60cad4e6 12812 return index;
1ab4434c 12813}
523224a3 12814
1ab4434c
AE		 12815static int set_max_cos_est(int chip_id)
12816{
12817 switch (chip_id) {
f2e0899f
DK		 12818 case BCM57710:
12819 case BCM57711:
12820 case BCM57711E:
1ab4434c 12821 return BNX2X_MULTI_TX_COS_E1X;
f2e0899f 12822 case BCM57712:
619c5cb6 12823 case BCM57712_MF:
1ab4434c 12824 return BNX2X_MULTI_TX_COS_E2_E3A0;
619c5cb6
VZ		 12825 case BCM57800:
12826 case BCM57800_MF:
12827 case BCM57810:
12828 case BCM57810_MF:
c3def943
YM		 12829 case BCM57840_4_10:
12830 case BCM57840_2_20:
1ab4434c 12831 case BCM57840_O:
c3def943 12832 case BCM57840_MFO:
619c5cb6 12833 case BCM57840_MF:
7e8e02df
BW		 12834 case BCM57811:
12835 case BCM57811_MF:
1ab4434c 12836 return BNX2X_MULTI_TX_COS_E3B0;
b1239723
YM		 12837 case BCM57712_VF:
12838 case BCM57800_VF:
12839 case BCM57810_VF:
12840 case BCM57840_VF:
12841 case BCM57811_VF:
1ab4434c 12842 return 1;
f2e0899f 12843 default:
1ab4434c 12844 pr_err("Unknown board_type (%d), aborting\n", chip_id);
870634b0 12845 return -ENODEV;
f2e0899f 12846 }
1ab4434c 12847}
f2e0899f 12848
1ab4434c
AE		 12849static int set_is_vf(int chip_id)
12850{
12851 switch (chip_id) {
12852 case BCM57712_VF:
12853 case BCM57800_VF:
12854 case BCM57810_VF:
12855 case BCM57840_VF:
12856 case BCM57811_VF:
12857 return true;
12858 default:
12859 return false;
12860 }
12861}
6383c0b3 12862
1ab4434c
AE		 12863static int bnx2x_init_one(struct pci_dev *pdev,
12864 const struct pci_device_id *ent)
12865{
12866 struct net_device *dev = NULL;
12867 struct bnx2x *bp;
b91e1a1a
YM		 12868 enum pcie_link_width pcie_width;
12869 enum pci_bus_speed pcie_speed;
1ab4434c
AE		 12870 int rc, max_non_def_sbs;
12871 int rx_count, tx_count, rss_count, doorbell_size;
12872 int max_cos_est;
12873 bool is_vf;
12874 int cnic_cnt;
12875
12876 /* An estimated maximum supported CoS number according to the chip
12877 * version.
12878 * We will try to roughly estimate the maximum number of CoSes this chip
12879 * may support in order to minimize the memory allocated for Tx
12880 * netdev_queue's. This number will be accurately calculated during the
12881 * initialization of bp->max_cos based on the chip versions AND chip
12882 * revision in the bnx2x_init_bp().
12883 */
12884 max_cos_est = set_max_cos_est(ent->driver_data);
12885 if (max_cos_est < 0)
12886 return max_cos_est;
12887 is_vf = set_is_vf(ent->driver_data);
12888 cnic_cnt = is_vf ? 0 : 1;
12889
60cad4e6
AE		 12890 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
12891
12892 /* add another SB for VF as it has no default SB */
12893 max_non_def_sbs += is_vf ? 1 : 0;
6383c0b3
AE		 12894
12895 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
60cad4e6 12896 rss_count = max_non_def_sbs - cnic_cnt;
1ab4434c
AE		 12897
12898 if (rss_count < 1)
12899 return -EINVAL;
6383c0b3
AE		 12900
12901 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
55c11941 12902 rx_count = rss_count + cnic_cnt;
6383c0b3 12903
1ab4434c 12904 /* Maximum number of netdev Tx queues:
37ae41a9 12905 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
6383c0b3 12906 */
55c11941 12907 tx_count = rss_count * max_cos_est + cnic_cnt;
f85582f8 12908
a2fbb9ea 12909 /* dev zeroed in init_etherdev */
6383c0b3 12910 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
41de8d4c 12911 if (!dev)
a2fbb9ea
ET		 12912 return -ENOMEM;
12913
a2fbb9ea 12914 bp = netdev_priv(dev);
a2fbb9ea 12915
1ab4434c
AE		 12916 bp->flags = 0;
12917 if (is_vf)
12918 bp->flags |= IS_VF_FLAG;
12919
6383c0b3 12920 bp->igu_sb_cnt = max_non_def_sbs;
1ab4434c 12921 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
6383c0b3 12922 bp->msg_enable = debug;
55c11941 12923 bp->cnic_support = cnic_cnt;
4bd9b0ff 12924 bp->cnic_probe = bnx2x_cnic_probe;
55c11941 12925
6383c0b3 12926 pci_set_drvdata(pdev, dev);
523224a3 12927
1ab4434c 12928 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
a2fbb9ea
ET		 12929 if (rc < 0) {
12930 free_netdev(dev);
12931 return rc;
12932 }
12933
1ab4434c
AE		 12934 BNX2X_DEV_INFO("This is a %s function\n",
12935 IS_PF(bp) ? "physical" : "virtual");
55c11941 12936 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
1ab4434c 12937 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
60aa0509 12938 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
2de67439 12939 tx_count, rx_count);
60aa0509 12940
34f80b04 12941 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 12942 if (rc)
12943 goto init_one_exit;
12944
1ab4434c
AE		 12945 /* Map doorbells here as we need the real value of bp->max_cos which
12946 * is initialized in bnx2x_init_bp() to determine the number of
12947 * l2 connections.
6383c0b3 12948 */
1ab4434c 12949 if (IS_VF(bp)) {
1d6f3cd8 12950 bp->doorbells = bnx2x_vf_doorbells(bp);
6411280a
AE		 12951 rc = bnx2x_vf_pci_alloc(bp);
12952 if (rc)
12953 goto init_one_exit;
1ab4434c
AE		 12954 } else {
12955 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12956 if (doorbell_size > pci_resource_len(pdev, 2)) {
12957 dev_err(&bp->pdev->dev,
12958 "Cannot map doorbells, bar size too small, aborting\n");
12959 rc = -ENOMEM;
12960 goto init_one_exit;
12961 }
12962 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12963 doorbell_size);
37ae41a9 12964 }
6383c0b3
AE		 12965 if (!bp->doorbells) {
12966 dev_err(&bp->pdev->dev,
12967 "Cannot map doorbell space, aborting\n");
12968 rc = -ENOMEM;
12969 goto init_one_exit;
12970 }
12971
be1f1ffa
AE		 12972 if (IS_VF(bp)) {
12973 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12974 if (rc)
12975 goto init_one_exit;
12976 }
12977
3c76feff
AE		 12978 /* Enable SRIOV if capability found in configuration space */
12979 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
290ca2bb
AE		 12980 if (rc)
12981 goto init_one_exit;
12982
523224a3 12983 /* calc qm_cid_count */
6383c0b3 12984 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
1ab4434c 12985 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
523224a3 12986
55c11941 12987 /* disable FCOE L2 queue for E1x*/
62ac0dc9 12988 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 12989 bp->flags |= NO_FCOE_FLAG;
12990
0e8d2ec5
MS		 12991 /* Set bp->num_queues for MSI-X mode*/
12992 bnx2x_set_num_queues(bp);
12993
25985edc 12994 /* Configure interrupt mode: try to enable MSI-X/MSI if
0e8d2ec5 12995 * needed.
d6214d7a 12996 */
1ab4434c
AE		 12997 rc = bnx2x_set_int_mode(bp);
12998 if (rc) {
12999 dev_err(&pdev->dev, "Cannot set interrupts\n");
13000 goto init_one_exit;
13001 }
04c46736 13002 BNX2X_DEV_INFO("set interrupts successfully\n");
d6214d7a 13003
1ab4434c 13004 /* register the net device */
b340007f
VZ		 13005 rc = register_netdev(dev);
13006 if (rc) {
13007 dev_err(&pdev->dev, "Cannot register net device\n");
13008 goto init_one_exit;
13009 }
1ab4434c 13010 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
b340007f 13011
ec6ba945
VZ		 13012 if (!NO_FCOE(bp)) {
13013 /* Add storage MAC address */
13014 rtnl_lock();
13015 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13016 rtnl_unlock();
13017 }
b91e1a1a
YM		 13018 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13019 pcie_speed == PCI_SPEED_UNKNOWN ||
13020 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13021 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13022 else
13023 BNX2X_DEV_INFO(
13024 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
ca1ee4b2
DK		 13025 board_info[ent->driver_data].name,
13026 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13027 pcie_width,
b91e1a1a
YM		 13028 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13029 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13030 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
ca1ee4b2
DK		 13031 "Unknown",
13032 dev->base_addr, bp->pdev->irq, dev->dev_addr);
c016201c 13033
a2fbb9ea 13034 return 0;
34f80b04
EG		 13035
13036init_one_exit:
33d8e6a5
YM		 13037 bnx2x_disable_pcie_error_reporting(bp);
13038
34f80b04
EG		 13039 if (bp->regview)
13040 iounmap(bp->regview);
13041
1ab4434c 13042 if (IS_PF(bp) && bp->doorbells)
34f80b04
EG		 13043 iounmap(bp->doorbells);
13044
13045 free_netdev(dev);
13046
13047 if (atomic_read(&pdev->enable_cnt) == 1)
13048 pci_release_regions(pdev);
13049
13050 pci_disable_device(pdev);
34f80b04
EG		 13051
13052 return rc;
a2fbb9ea
ET		 13053}
13054
b030ed2f
YM		 13055static void __bnx2x_remove(struct pci_dev *pdev,
13056 struct net_device *dev,
13057 struct bnx2x *bp,
13058 bool remove_netdev)
a2fbb9ea 13059{
ec6ba945
VZ		 13060 /* Delete storage MAC address */
13061 if (!NO_FCOE(bp)) {
13062 rtnl_lock();
13063 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13064 rtnl_unlock();
13065 }
ec6ba945 13066
98507672
SR		 13067#ifdef BCM_DCBNL
13068 /* Delete app tlvs from dcbnl */
13069 bnx2x_dcbnl_update_applist(bp, true);
13070#endif
13071
a6d3a5ba
BW		 13072 if (IS_PF(bp) &&
13073 !BP_NOMCP(bp) &&
13074 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13075 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13076
b030ed2f
YM		 13077 /* Close the interface - either directly or implicitly */
13078 if (remove_netdev) {
13079 unregister_netdev(dev);
13080 } else {
13081 rtnl_lock();
6ef5a92c 13082 dev_close(dev);
b030ed2f
YM		 13083 rtnl_unlock();
13084 }
a2fbb9ea 13085
78c3bcc5
AE		 13086 bnx2x_iov_remove_one(bp);
13087
084d6cbb 13088 /* Power on: we can't let PCI layer write to us while we are in D3 */
1ab4434c
AE		 13089 if (IS_PF(bp))
13090 bnx2x_set_power_state(bp, PCI_D0);
084d6cbb 13091
d6214d7a
DK		 13092 /* Disable MSI/MSI-X */
13093 bnx2x_disable_msi(bp);
f85582f8 13094
084d6cbb 13095 /* Power off */
1ab4434c
AE		 13096 if (IS_PF(bp))
13097 bnx2x_set_power_state(bp, PCI_D3hot);
084d6cbb 13098
72fd0718 13099 /* Make sure RESET task is not scheduled before continuing */
7be08a72 13100 cancel_delayed_work_sync(&bp->sp_rtnl_task);
290ca2bb 13101
4513f925
AE		 13102 /* send message via vfpf channel to release the resources of this vf */
13103 if (IS_VF(bp))
13104 bnx2x_vfpf_release(bp);
72fd0718 13105
b030ed2f
YM		 13106 /* Assumes no further PCIe PM changes will occur */
13107 if (system_state == SYSTEM_POWER_OFF) {
13108 pci_wake_from_d3(pdev, bp->wol);
13109 pci_set_power_state(pdev, PCI_D3hot);
13110 }
13111
33d8e6a5 13112 bnx2x_disable_pcie_error_reporting(bp);
d9aee591
YM		 13113 if (remove_netdev) {
13114 if (bp->regview)
13115 iounmap(bp->regview);
33d8e6a5 13116
d9aee591
YM		 13117 /* For vfs, doorbells are part of the regview and were unmapped
13118 * along with it. FW is only loaded by PF.
13119 */
13120 if (IS_PF(bp)) {
13121 if (bp->doorbells)
13122 iounmap(bp->doorbells);
eb2afd4a 13123
d9aee591
YM		 13124 bnx2x_release_firmware(bp);
13125 }
13126 bnx2x_free_mem_bp(bp);
523224a3 13127
b030ed2f 13128 free_netdev(dev);
34f80b04 13129
d9aee591
YM		 13130 if (atomic_read(&pdev->enable_cnt) == 1)
13131 pci_release_regions(pdev);
34f80b04 13132
5f6db130
YM		 13133 pci_disable_device(pdev);
13134 }
a2fbb9ea
ET		 13135}
13136
b030ed2f
YM		 13137static void bnx2x_remove_one(struct pci_dev *pdev)
13138{
13139 struct net_device *dev = pci_get_drvdata(pdev);
13140 struct bnx2x *bp;
13141
13142 if (!dev) {
13143 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13144 return;
13145 }
13146 bp = netdev_priv(dev);
13147
13148 __bnx2x_remove(pdev, dev, bp, true);
13149}
13150
f8ef6e44
YG		 13151static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13152{
7fa6f340 13153 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
f8ef6e44
YG		 13154
13155 bp->rx_mode = BNX2X_RX_MODE_NONE;
13156
55c11941
MS		 13157 if (CNIC_LOADED(bp))
13158 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13159
619c5cb6
VZ		 13160 /* Stop Tx */
13161 bnx2x_tx_disable(bp);
26614ba5
MS		 13162 /* Delete all NAPI objects */
13163 bnx2x_del_all_napi(bp);
55c11941
MS		 13164 if (CNIC_LOADED(bp))
13165 bnx2x_del_all_napi_cnic(bp);
7fa6f340 13166 netdev_reset_tc(bp->dev);
f8ef6e44
YG		 13167
13168 del_timer_sync(&bp->timer);
7fa6f340
YM		 13169 cancel_delayed_work(&bp->sp_task);
13170 cancel_delayed_work(&bp->period_task);
619c5cb6 13171
7fa6f340
YM		 13172 spin_lock_bh(&bp->stats_lock);
13173 bp->stats_state = STATS_STATE_DISABLED;
13174 spin_unlock_bh(&bp->stats_lock);
f8ef6e44 13175
7fa6f340 13176 bnx2x_save_statistics(bp);
f8ef6e44 13177
619c5cb6
VZ		 13178 netif_carrier_off(bp->dev);
13179
f8ef6e44
YG		 13180 return 0;
13181}
13182
493adb1f
WX		 13183/**
13184 * bnx2x_io_error_detected - called when PCI error is detected
13185 * @pdev: Pointer to PCI device
13186 * @state: The current pci connection state
13187 *
13188 * This function is called after a PCI bus error affecting
13189 * this device has been detected.
13190 */
13191static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13192 pci_channel_state_t state)
13193{
13194 struct net_device *dev = pci_get_drvdata(pdev);
13195 struct bnx2x *bp = netdev_priv(dev);
13196
13197 rtnl_lock();
13198
7fa6f340
YM		 13199 BNX2X_ERR("IO error detected\n");
13200
493adb1f
WX		 13201 netif_device_detach(dev);
13202
07ce50e4
DN		 13203 if (state == pci_channel_io_perm_failure) {
13204 rtnl_unlock();
13205 return PCI_ERS_RESULT_DISCONNECT;
13206 }
13207
493adb1f 13208 if (netif_running(dev))
f8ef6e44 13209 bnx2x_eeh_nic_unload(bp);
493adb1f 13210
7fa6f340
YM		 13211 bnx2x_prev_path_mark_eeh(bp);
13212
493adb1f
WX		 13213 pci_disable_device(pdev);
13214
13215 rtnl_unlock();
13216
13217 /* Request a slot reset */
13218 return PCI_ERS_RESULT_NEED_RESET;
13219}
13220
13221/**
13222 * bnx2x_io_slot_reset - called after the PCI bus has been reset
13223 * @pdev: Pointer to PCI device
13224 *
13225 * Restart the card from scratch, as if from a cold-boot.
13226 */
13227static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13228{
13229 struct net_device *dev = pci_get_drvdata(pdev);
13230 struct bnx2x *bp = netdev_priv(dev);
7fa6f340 13231 int i;
493adb1f
WX		 13232
13233 rtnl_lock();
7fa6f340 13234 BNX2X_ERR("IO slot reset initializing...\n");
493adb1f
WX		 13235 if (pci_enable_device(pdev)) {
13236 dev_err(&pdev->dev,
13237 "Cannot re-enable PCI device after reset\n");
13238 rtnl_unlock();
13239 return PCI_ERS_RESULT_DISCONNECT;
13240 }
13241
13242 pci_set_master(pdev);
13243 pci_restore_state(pdev);
70632d0a 13244 pci_save_state(pdev);
493adb1f
WX		 13245
13246 if (netif_running(dev))
13247 bnx2x_set_power_state(bp, PCI_D0);
13248
7fa6f340
YM		 13249 if (netif_running(dev)) {
13250 BNX2X_ERR("IO slot reset --> driver unload\n");
e68072ef
YM		 13251
13252 /* MCP should have been reset; Need to wait for validity */
13253 bnx2x_init_shmem(bp);
13254
7fa6f340
YM		 13255 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13256 u32 v;
13257
13258 v = SHMEM2_RD(bp,
13259 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13260 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13261 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13262 }
13263 bnx2x_drain_tx_queues(bp);
13264 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13265 bnx2x_netif_stop(bp, 1);
13266 bnx2x_free_irq(bp);
13267
13268 /* Report UNLOAD_DONE to MCP */
13269 bnx2x_send_unload_done(bp, true);
13270
13271 bp->sp_state = 0;
13272 bp->port.pmf = 0;
13273
13274 bnx2x_prev_unload(bp);
13275
16a5fd92 13276 /* We should have reseted the engine, so It's fair to
7fa6f340
YM		 13277 * assume the FW will no longer write to the bnx2x driver.
13278 */
13279 bnx2x_squeeze_objects(bp);
13280 bnx2x_free_skbs(bp);
13281 for_each_rx_queue(bp, i)
13282 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13283 bnx2x_free_fp_mem(bp);
13284 bnx2x_free_mem(bp);
13285
13286 bp->state = BNX2X_STATE_CLOSED;
13287 }
13288
493adb1f
WX		 13289 rtnl_unlock();
13290
33d8e6a5
YM		 13291 /* If AER, perform cleanup of the PCIe registers */
13292 if (bp->flags & AER_ENABLED) {
13293 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13294 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13295 else
13296 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13297 }
13298
493adb1f
WX		 13299 return PCI_ERS_RESULT_RECOVERED;
13300}
13301
13302/**
13303 * bnx2x_io_resume - called when traffic can start flowing again
13304 * @pdev: Pointer to PCI device
13305 *
13306 * This callback is called when the error recovery driver tells us that
13307 * its OK to resume normal operation.
13308 */
13309static void bnx2x_io_resume(struct pci_dev *pdev)
13310{
13311 struct net_device *dev = pci_get_drvdata(pdev);
13312 struct bnx2x *bp = netdev_priv(dev);
13313
72fd0718 13314 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580 13315 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
72fd0718
VZ		 13316 return;
13317 }
13318
493adb1f
WX		 13319 rtnl_lock();
13320
7fa6f340
YM		 13321 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13322 DRV_MSG_SEQ_NUMBER_MASK;
13323
493adb1f 13324 if (netif_running(dev))
f8ef6e44 13325 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 13326
13327 netif_device_attach(dev);
13328
13329 rtnl_unlock();
13330}
13331
3646f0e5 13332static const struct pci_error_handlers bnx2x_err_handler = {
493adb1f 13333 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 13334 .slot_reset = bnx2x_io_slot_reset,
13335 .resume = bnx2x_io_resume,
493adb1f
WX		 13336};
13337
b030ed2f
YM		 13338static void bnx2x_shutdown(struct pci_dev *pdev)
13339{
13340 struct net_device *dev = pci_get_drvdata(pdev);
13341 struct bnx2x *bp;
13342
13343 if (!dev)
13344 return;
13345
13346 bp = netdev_priv(dev);
13347 if (!bp)
13348 return;
13349
13350 rtnl_lock();
13351 netif_device_detach(dev);
13352 rtnl_unlock();
13353
13354 /* Don't remove the netdevice, as there are scenarios which will cause
13355 * the kernel to hang, e.g., when trying to remove bnx2i while the
13356 * rootfs is mounted from SAN.
13357 */
13358 __bnx2x_remove(pdev, dev, bp, false);
13359}
13360
a2fbb9ea 13361static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 13362 .name = DRV_MODULE_NAME,
13363 .id_table = bnx2x_pci_tbl,
13364 .probe = bnx2x_init_one,
0329aba1 13365 .remove = bnx2x_remove_one,
493adb1f
WX		 13366 .suspend = bnx2x_suspend,
13367 .resume = bnx2x_resume,
13368 .err_handler = &bnx2x_err_handler,
3c76feff
AE		 13369#ifdef CONFIG_BNX2X_SRIOV
13370 .sriov_configure = bnx2x_sriov_configure,
13371#endif
b030ed2f 13372 .shutdown = bnx2x_shutdown,
a2fbb9ea
ET		 13373};
13374
13375static int __init bnx2x_init(void)
13376{
dd21ca6d
SG		 13377 int ret;
13378
7995c64e 13379 pr_info("%s", version);
938cf541 13380
1cf167f2
EG		 13381 bnx2x_wq = create_singlethread_workqueue("bnx2x");
13382 if (bnx2x_wq == NULL) {
7995c64e 13383 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 13384 return -ENOMEM;
13385 }
13386
dd21ca6d
SG		 13387 ret = pci_register_driver(&bnx2x_pci_driver);
13388 if (ret) {
7995c64e 13389 pr_err("Cannot register driver\n");
dd21ca6d
SG		 13390 destroy_workqueue(bnx2x_wq);
13391 }
13392 return ret;
a2fbb9ea
ET		 13393}
13394
13395static void __exit bnx2x_cleanup(void)
13396{
452427b0 13397 struct list_head *pos, *q;
d76a6111 13398
a2fbb9ea 13399 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 13400
13401 destroy_workqueue(bnx2x_wq);
452427b0 13402
16a5fd92 13403 /* Free globally allocated resources */
452427b0
YM		 13404 list_for_each_safe(pos, q, &bnx2x_prev_list) {
13405 struct bnx2x_prev_path_list *tmp =
13406 list_entry(pos, struct bnx2x_prev_path_list, list);
13407 list_del(pos);
13408 kfree(tmp);
13409 }
a2fbb9ea
ET		 13410}
13411
3deb8167
YR		 13412void bnx2x_notify_link_changed(struct bnx2x *bp)
13413{
13414 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13415}
13416
a2fbb9ea
ET		 13417module_init(bnx2x_init);
13418module_exit(bnx2x_cleanup);
13419
619c5cb6
VZ		 13420/**
13421 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13422 *
13423 * @bp: driver handle
13424 * @set: set or clear the CAM entry
13425 *
16a5fd92 13426 * This function will wait until the ramrod completion returns.
619c5cb6
VZ		 13427 * Return 0 if success, -ENODEV if ramrod doesn't return.
13428 */
1191cb83 13429static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
619c5cb6
VZ		 13430{
13431 unsigned long ramrod_flags = 0;
13432
13433 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13434 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13435 &bp->iscsi_l2_mac_obj, true,
13436 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13437}
993ac7b5
MC		 13438
13439/* count denotes the number of new completions we have seen */
13440static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13441{
13442 struct eth_spe *spe;
a052997e 13443 int cxt_index, cxt_offset;
993ac7b5
MC		 13444
13445#ifdef BNX2X_STOP_ON_ERROR
13446 if (unlikely(bp->panic))
13447 return;
13448#endif
13449
13450 spin_lock_bh(&bp->spq_lock);
c2bff63f 13451 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 13452 bp->cnic_spq_pending -= count;
13453
c2bff63f
DK		 13454 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13455 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13456 & SPE_HDR_CONN_TYPE) >>
13457 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 13458 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13459 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 13460
13461 /* Set validation for iSCSI L2 client before sending SETUP
13462 * ramrod
13463 */
13464 if (type == ETH_CONNECTION_TYPE) {
a052997e 13465 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
37ae41a9 13466 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
a052997e 13467 ILT_PAGE_CIDS;
37ae41a9 13468 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
a052997e
MS		 13469 (cxt_index * ILT_PAGE_CIDS);
13470 bnx2x_set_ctx_validation(bp,
13471 &bp->context[cxt_index].
13472 vcxt[cxt_offset].eth,
37ae41a9 13473 BNX2X_ISCSI_ETH_CID(bp));
a052997e 13474 }
c2bff63f
DK		 13475 }
13476
619c5cb6
VZ		 13477 /*
13478 * There may be not more than 8 L2, not more than 8 L5 SPEs
13479 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 13480 * COMMON ramrods is not more than the EQ and SPQ can
13481 * accommodate.
c2bff63f 13482 */
6e30dd4e
VZ		 13483 if (type == ETH_CONNECTION_TYPE) {
13484 if (!atomic_read(&bp->cq_spq_left))
13485 break;
13486 else
13487 atomic_dec(&bp->cq_spq_left);
13488 } else if (type == NONE_CONNECTION_TYPE) {
13489 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 13490 break;
13491 else
6e30dd4e 13492 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 13493 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13494 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 13495 if (bp->cnic_spq_pending >=
13496 bp->cnic_eth_dev.max_kwqe_pending)
13497 break;
13498 else
13499 bp->cnic_spq_pending++;
13500 } else {
13501 BNX2X_ERR("Unknown SPE type: %d\n", type);
13502 bnx2x_panic();
993ac7b5 13503 break;
c2bff63f 13504 }
993ac7b5
MC		 13505
13506 spe = bnx2x_sp_get_next(bp);
13507 *spe = *bp->cnic_kwq_cons;
13508
51c1a580 13509 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
993ac7b5
MC		 13510 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13511
13512 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13513 bp->cnic_kwq_cons = bp->cnic_kwq;
13514 else
13515 bp->cnic_kwq_cons++;
13516 }
13517 bnx2x_sp_prod_update(bp);
13518 spin_unlock_bh(&bp->spq_lock);
13519}
13520
13521static int bnx2x_cnic_sp_queue(struct net_device *dev,
13522 struct kwqe_16 *kwqes[], u32 count)
13523{
13524 struct bnx2x *bp = netdev_priv(dev);
13525 int i;
13526
13527#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 13528 if (unlikely(bp->panic)) {
13529 BNX2X_ERR("Can't post to SP queue while panic\n");
993ac7b5 13530 return -EIO;
51c1a580 13531 }
993ac7b5
MC		 13532#endif
13533
95c6c616
AE		 13534 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13535 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
51c1a580 13536 BNX2X_ERR("Handling parity error recovery. Try again later\n");
95c6c616
AE		 13537 return -EAGAIN;
13538 }
13539
993ac7b5
MC		 13540 spin_lock_bh(&bp->spq_lock);
13541
13542 for (i = 0; i < count; i++) {
13543 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13544
13545 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13546 break;
13547
13548 *bp->cnic_kwq_prod = *spe;
13549
13550 bp->cnic_kwq_pending++;
13551
51c1a580 13552 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
993ac7b5 13553 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 13554 spe->data.update_data_addr.hi,
13555 spe->data.update_data_addr.lo,
993ac7b5
MC		 13556 bp->cnic_kwq_pending);
13557
13558 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13559 bp->cnic_kwq_prod = bp->cnic_kwq;
13560 else
13561 bp->cnic_kwq_prod++;
13562 }
13563
13564 spin_unlock_bh(&bp->spq_lock);
13565
13566 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13567 bnx2x_cnic_sp_post(bp, 0);
13568
13569 return i;
13570}
13571
13572static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13573{
13574 struct cnic_ops *c_ops;
13575 int rc = 0;
13576
13577 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 13578 c_ops = rcu_dereference_protected(bp->cnic_ops,
13579 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 13580 if (c_ops)
13581 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13582 mutex_unlock(&bp->cnic_mutex);
13583
13584 return rc;
13585}
13586
13587static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13588{
13589 struct cnic_ops *c_ops;
13590 int rc = 0;
13591
13592 rcu_read_lock();
13593 c_ops = rcu_dereference(bp->cnic_ops);
13594 if (c_ops)
13595 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13596 rcu_read_unlock();
13597
13598 return rc;
13599}
13600
13601/*
13602 * for commands that have no data
13603 */
9f6c9258 13604int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 13605{
13606 struct cnic_ctl_info ctl = {0};
13607
13608 ctl.cmd = cmd;
13609
13610 return bnx2x_cnic_ctl_send(bp, &ctl);
13611}
13612
619c5cb6 13613static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 13614{
619c5cb6 13615 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 13616
13617 /* first we tell CNIC and only then we count this as a completion */
13618 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13619 ctl.data.comp.cid = cid;
619c5cb6 13620 ctl.data.comp.error = err;
993ac7b5
MC		 13621
13622 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 13623 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 13624}
13625
619c5cb6
VZ		 13626/* Called with netif_addr_lock_bh() taken.
13627 * Sets an rx_mode config for an iSCSI ETH client.
13628 * Doesn't block.
13629 * Completion should be checked outside.
13630 */
13631static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13632{
13633 unsigned long accept_flags = 0, ramrod_flags = 0;
13634 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13635 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13636
13637 if (start) {
13638 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13639 * because it's the only way for UIO Queue to accept
13640 * multicasts (in non-promiscuous mode only one Queue per
13641 * function will receive multicast packets (leading in our
13642 * case).
13643 */
13644 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13645 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13646 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13647 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13648
13649 /* Clear STOP_PENDING bit if START is requested */
13650 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13651
13652 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13653 } else
13654 /* Clear START_PENDING bit if STOP is requested */
13655 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13656
13657 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13658 set_bit(sched_state, &bp->sp_state);
13659 else {
13660 __set_bit(RAMROD_RX, &ramrod_flags);
13661 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13662 ramrod_flags);
13663 }
13664}
13665
993ac7b5
MC		 13666static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13667{
13668 struct bnx2x *bp = netdev_priv(dev);
13669 int rc = 0;
13670
13671 switch (ctl->cmd) {
13672 case DRV_CTL_CTXTBL_WR_CMD: {
13673 u32 index = ctl->data.io.offset;
13674 dma_addr_t addr = ctl->data.io.dma_addr;
13675
13676 bnx2x_ilt_wr(bp, index, addr);
13677 break;
13678 }
13679
c2bff63f
DK		 13680 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13681 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 13682
13683 bnx2x_cnic_sp_post(bp, count);
13684 break;
13685 }
13686
13687 /* rtnl_lock is held. */
13688 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 13689 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13690 unsigned long sp_bits = 0;
13691
13692 /* Configure the iSCSI classification object */
13693 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13694 cp->iscsi_l2_client_id,
13695 cp->iscsi_l2_cid, BP_FUNC(bp),
13696 bnx2x_sp(bp, mac_rdata),
13697 bnx2x_sp_mapping(bp, mac_rdata),
13698 BNX2X_FILTER_MAC_PENDING,
13699 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13700 &bp->macs_pool);
ec6ba945 13701
523224a3 13702 /* Set iSCSI MAC address */
619c5cb6
VZ		 13703 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13704 if (rc)
13705 break;
523224a3
DK		 13706
13707 mmiowb();
13708 barrier();
13709
619c5cb6
VZ		 13710 /* Start accepting on iSCSI L2 ring */
13711
13712 netif_addr_lock_bh(dev);
13713 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13714 netif_addr_unlock_bh(dev);
13715
13716 /* bits to wait on */
13717 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13718 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13719
13720 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13721 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 13722
993ac7b5
MC		 13723 break;
13724 }
13725
13726 /* rtnl_lock is held. */
13727 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 13728 unsigned long sp_bits = 0;
993ac7b5 13729
523224a3 13730 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 13731 netif_addr_lock_bh(dev);
13732 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13733 netif_addr_unlock_bh(dev);
13734
13735 /* bits to wait on */
13736 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13737 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13738
13739 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13740 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 13741
13742 mmiowb();
13743 barrier();
13744
13745 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 13746 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13747 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 13748 break;
13749 }
c2bff63f
DK		 13750 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13751 int count = ctl->data.credit.credit_count;
13752
13753 smp_mb__before_atomic_inc();
6e30dd4e 13754 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 13755 smp_mb__after_atomic_inc();
13756 break;
13757 }
1d187b34 13758 case DRV_CTL_ULP_REGISTER_CMD: {
2e499d3c 13759 int ulp_type = ctl->data.register_data.ulp_type;
1d187b34
BW		 13760
13761 if (CHIP_IS_E3(bp)) {
13762 int idx = BP_FW_MB_IDX(bp);
2e499d3c
BW		 13763 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13764 int path = BP_PATH(bp);
13765 int port = BP_PORT(bp);
13766 int i;
13767 u32 scratch_offset;
13768 u32 *host_addr;
1d187b34 13769
2e499d3c 13770 /* first write capability to shmem2 */
1d187b34
BW		 13771 if (ulp_type == CNIC_ULP_ISCSI)
13772 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13773 else if (ulp_type == CNIC_ULP_FCOE)
13774 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13775 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
2e499d3c
BW		 13776
13777 if ((ulp_type != CNIC_ULP_FCOE) ||
13778 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13779 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
13780 break;
13781
13782 /* if reached here - should write fcoe capabilities */
13783 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13784 if (!scratch_offset)
13785 break;
13786 scratch_offset += offsetof(struct glob_ncsi_oem_data,
13787 fcoe_features[path][port]);
13788 host_addr = (u32 *) &(ctl->data.register_data.
13789 fcoe_features);
13790 for (i = 0; i < sizeof(struct fcoe_capabilities);
13791 i += 4)
13792 REG_WR(bp, scratch_offset + i,
13793 *(host_addr + i/4));
1d187b34
BW		 13794 }
13795 break;
13796 }
2e499d3c 13797
1d187b34
BW		 13798 case DRV_CTL_ULP_UNREGISTER_CMD: {
13799 int ulp_type = ctl->data.ulp_type;
13800
13801 if (CHIP_IS_E3(bp)) {
13802 int idx = BP_FW_MB_IDX(bp);
13803 u32 cap;
13804
13805 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13806 if (ulp_type == CNIC_ULP_ISCSI)
13807 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13808 else if (ulp_type == CNIC_ULP_FCOE)
13809 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13810 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13811 }
13812 break;
13813 }
993ac7b5
MC		 13814
13815 default:
13816 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13817 rc = -EINVAL;
13818 }
13819
13820 return rc;
13821}
13822
9f6c9258 13823void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 13824{
13825 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13826
13827 if (bp->flags & USING_MSIX_FLAG) {
13828 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13829 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13830 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13831 } else {
13832 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13833 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13834 }
619c5cb6 13835 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 13836 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13837 else
13838 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13839
619c5cb6
VZ		 13840 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
13841 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 13842 cp->irq_arr[1].status_blk = bp->def_status_blk;
13843 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 13844 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 13845
13846 cp->num_irq = 2;
13847}
13848
37ae41a9
MS		 13849void bnx2x_setup_cnic_info(struct bnx2x *bp)
13850{
13851 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13852
37ae41a9
MS		 13853 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13854 bnx2x_cid_ilt_lines(bp);
13855 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13856 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13857 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13858
f78afb35
MC		 13859 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
13860 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
13861 cp->iscsi_l2_cid);
13862
37ae41a9
MS		 13863 if (NO_ISCSI_OOO(bp))
13864 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13865}
13866
993ac7b5
MC		 13867static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13868 void *data)
13869{
13870 struct bnx2x *bp = netdev_priv(dev);
13871 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
55c11941
MS		 13872 int rc;
13873
13874 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
993ac7b5 13875
51c1a580
MS		 13876 if (ops == NULL) {
13877 BNX2X_ERR("NULL ops received\n");
993ac7b5 13878 return -EINVAL;
51c1a580 13879 }
993ac7b5 13880
55c11941
MS		 13881 if (!CNIC_SUPPORT(bp)) {
13882 BNX2X_ERR("Can't register CNIC when not supported\n");
13883 return -EOPNOTSUPP;
13884 }
13885
13886 if (!CNIC_LOADED(bp)) {
13887 rc = bnx2x_load_cnic(bp);
13888 if (rc) {
13889 BNX2X_ERR("CNIC-related load failed\n");
13890 return rc;
13891 }
55c11941
MS		 13892 }
13893
13894 bp->cnic_enabled = true;
13895
993ac7b5
MC		 13896 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13897 if (!bp->cnic_kwq)
13898 return -ENOMEM;
13899
13900 bp->cnic_kwq_cons = bp->cnic_kwq;
13901 bp->cnic_kwq_prod = bp->cnic_kwq;
13902 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13903
13904 bp->cnic_spq_pending = 0;
13905 bp->cnic_kwq_pending = 0;
13906
13907 bp->cnic_data = data;
13908
13909 cp->num_irq = 0;
619c5cb6 13910 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 13911 cp->iro_arr = bp->iro_arr;
993ac7b5 13912
993ac7b5 13913 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 13914
993ac7b5
MC		 13915 rcu_assign_pointer(bp->cnic_ops, ops);
13916
13917 return 0;
13918}
13919
13920static int bnx2x_unregister_cnic(struct net_device *dev)
13921{
13922 struct bnx2x *bp = netdev_priv(dev);
13923 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13924
13925 mutex_lock(&bp->cnic_mutex);
993ac7b5 13926 cp->drv_state = 0;
2cfa5a04 13927 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 13928 mutex_unlock(&bp->cnic_mutex);
13929 synchronize_rcu();
fea75645 13930 bp->cnic_enabled = false;
993ac7b5
MC		 13931 kfree(bp->cnic_kwq);
13932 bp->cnic_kwq = NULL;
13933
13934 return 0;
13935}
13936
a8f47eb7 13937static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
993ac7b5
MC		 13938{
13939 struct bnx2x *bp = netdev_priv(dev);
13940 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13941
2ba45142
VZ		 13942 /* If both iSCSI and FCoE are disabled - return NULL in
13943 * order to indicate CNIC that it should not try to work
13944 * with this device.
13945 */
13946 if (NO_ISCSI(bp) && NO_FCOE(bp))
13947 return NULL;
13948
993ac7b5
MC		 13949 cp->drv_owner = THIS_MODULE;
13950 cp->chip_id = CHIP_ID(bp);
13951 cp->pdev = bp->pdev;
13952 cp->io_base = bp->regview;
13953 cp->io_base2 = bp->doorbells;
13954 cp->max_kwqe_pending = 8;
523224a3 13955 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 13956 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13957 bnx2x_cid_ilt_lines(bp);
993ac7b5 13958 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 13959 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 13960 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13961 cp->drv_ctl = bnx2x_drv_ctl;
13962 cp->drv_register_cnic = bnx2x_register_cnic;
13963 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
37ae41a9 13964 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
619c5cb6
VZ		 13965 cp->iscsi_l2_client_id =
13966 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
37ae41a9 13967 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
c2bff63f 13968
2ba45142
VZ		 13969 if (NO_ISCSI_OOO(bp))
13970 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13971
13972 if (NO_ISCSI(bp))
13973 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13974
13975 if (NO_FCOE(bp))
13976 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13977
51c1a580
MS		 13978 BNX2X_DEV_INFO(
13979 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
c2bff63f
DK		 13980 cp->ctx_blk_size,
13981 cp->ctx_tbl_offset,
13982 cp->ctx_tbl_len,
13983 cp->starting_cid);
993ac7b5
MC		 13984 return cp;
13985}
993ac7b5 13986
a8f47eb7 13987static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
9b176b6b 13988{
6411280a
AE		 13989 struct bnx2x *bp = fp->bp;
13990 u32 offset = BAR_USTRORM_INTMEM;
abc5a021 13991
6411280a
AE		 13992 if (IS_VF(bp))
13993 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13994 else if (!CHIP_IS_E1x(bp))
13995 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13996 else
13997 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
8d9ac297 13998
6411280a 13999 return offset;
8d9ac297 14000}
381ac16b 14001
6411280a
AE		 14002/* called only on E1H or E2.
14003 * When pretending to be PF, the pretend value is the function number 0...7
14004 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14005 * combination
14006 */
14007int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
381ac16b 14008{
6411280a 14009 u32 pretend_reg;
381ac16b 14010
23826850 14011 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
6411280a 14012 return -1;
381ac16b 14013
6411280a
AE		 14014 /* get my own pretend register */
14015 pretend_reg = bnx2x_get_pretend_reg(bp);
14016 REG_WR(bp, pretend_reg, pretend_func_val);
14017 REG_RD(bp, pretend_reg);
381ac16b
AE		 14018 return 0;
14019}
Linux kernel - Deliverables
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