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bnxt_en: Send PF driver unload notification to all VFs.
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
CommitLineData
c0c050c5
MC		 1/* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2015 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11
12#include <linux/stringify.h>
13#include <linux/kernel.h>
14#include <linux/timer.h>
15#include <linux/errno.h>
16#include <linux/ioport.h>
17#include <linux/slab.h>
18#include <linux/vmalloc.h>
19#include <linux/interrupt.h>
20#include <linux/pci.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/dma-mapping.h>
25#include <linux/bitops.h>
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/delay.h>
29#include <asm/byteorder.h>
30#include <asm/page.h>
31#include <linux/time.h>
32#include <linux/mii.h>
33#include <linux/if.h>
34#include <linux/if_vlan.h>
35#include <net/ip.h>
36#include <net/tcp.h>
37#include <net/udp.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41#include <net/vxlan.h>
42#endif
43#ifdef CONFIG_NET_RX_BUSY_POLL
44#include <net/busy_poll.h>
45#endif
46#include <linux/workqueue.h>
47#include <linux/prefetch.h>
48#include <linux/cache.h>
49#include <linux/log2.h>
50#include <linux/aer.h>
51#include <linux/bitmap.h>
52#include <linux/cpu_rmap.h>
53
54#include "bnxt_hsi.h"
55#include "bnxt.h"
56#include "bnxt_sriov.h"
57#include "bnxt_ethtool.h"
58
59#define BNXT_TX_TIMEOUT (5 * HZ)
60
61static const char version[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
63
64MODULE_LICENSE("GPL");
65MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66MODULE_VERSION(DRV_MODULE_VERSION);
67
68#define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69#define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70#define BNXT_RX_COPY_THRESH 256
71
4419dbe6 72#define BNXT_TX_PUSH_THRESH 164
c0c050c5
MC		 73
74enum board_idx {
fbc9a523 75 BCM57301,
c0c050c5
MC		 76 BCM57302,
77 BCM57304,
fbc9a523 78 BCM57402,
c0c050c5
MC		 79 BCM57404,
80 BCM57406,
81 BCM57304_VF,
82 BCM57404_VF,
83};
84
85/* indexed by enum above */
86static const struct {
87 char *name;
88} board_info[] = {
fbc9a523
DC		 89 { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
90 { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
c0c050c5 91 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
fbc9a523 92 { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
c0c050c5 93 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
fbc9a523 94 { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
c0c050c5
MC		 95 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
96 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
97};
98
99static const struct pci_device_id bnxt_pci_tbl[] = {
fbc9a523 100 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
c0c050c5
MC		 101 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
102 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
fbc9a523 103 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
c0c050c5
MC		 104 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
105 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
106#ifdef CONFIG_BNXT_SRIOV
107 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
108 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
109#endif
110 { 0 }
111};
112
113MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
114
115static const u16 bnxt_vf_req_snif[] = {
116 HWRM_FUNC_CFG,
117 HWRM_PORT_PHY_QCFG,
118 HWRM_CFA_L2_FILTER_ALLOC,
119};
120
121static bool bnxt_vf_pciid(enum board_idx idx)
122{
123 return (idx == BCM57304_VF || idx == BCM57404_VF);
124}
125
126#define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
127#define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
128#define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
129
130#define BNXT_CP_DB_REARM(db, raw_cons) \
131 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
132
133#define BNXT_CP_DB(db, raw_cons) \
134 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
135
136#define BNXT_CP_DB_IRQ_DIS(db) \
137 writel(DB_CP_IRQ_DIS_FLAGS, db)
138
139static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
140{
141 /* Tell compiler to fetch tx indices from memory. */
142 barrier();
143
144 return bp->tx_ring_size -
145 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
146}
147
148static const u16 bnxt_lhint_arr[] = {
149 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
150 TX_BD_FLAGS_LHINT_512_TO_1023,
151 TX_BD_FLAGS_LHINT_1024_TO_2047,
152 TX_BD_FLAGS_LHINT_1024_TO_2047,
153 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
154 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
155 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
156 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
157 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
158 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
159 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
160 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
161 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
162 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
163 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
164 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
165 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
166 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
167 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
168};
169
170static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
171{
172 struct bnxt *bp = netdev_priv(dev);
173 struct tx_bd *txbd;
174 struct tx_bd_ext *txbd1;
175 struct netdev_queue *txq;
176 int i;
177 dma_addr_t mapping;
178 unsigned int length, pad = 0;
179 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
180 u16 prod, last_frag;
181 struct pci_dev *pdev = bp->pdev;
c0c050c5
MC		 182 struct bnxt_tx_ring_info *txr;
183 struct bnxt_sw_tx_bd *tx_buf;
184
185 i = skb_get_queue_mapping(skb);
186 if (unlikely(i >= bp->tx_nr_rings)) {
187 dev_kfree_skb_any(skb);
188 return NETDEV_TX_OK;
189 }
190
b6ab4b01 191 txr = &bp->tx_ring[i];
c0c050c5
MC		 192 txq = netdev_get_tx_queue(dev, i);
193 prod = txr->tx_prod;
194
195 free_size = bnxt_tx_avail(bp, txr);
196 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
197 netif_tx_stop_queue(txq);
198 return NETDEV_TX_BUSY;
199 }
200
201 length = skb->len;
202 len = skb_headlen(skb);
203 last_frag = skb_shinfo(skb)->nr_frags;
204
205 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
206
207 txbd->tx_bd_opaque = prod;
208
209 tx_buf = &txr->tx_buf_ring[prod];
210 tx_buf->skb = skb;
211 tx_buf->nr_frags = last_frag;
212
213 vlan_tag_flags = 0;
214 cfa_action = 0;
215 if (skb_vlan_tag_present(skb)) {
216 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
217 skb_vlan_tag_get(skb);
218 /* Currently supports 8021Q, 8021AD vlan offloads
219 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
220 */
221 if (skb->vlan_proto == htons(ETH_P_8021Q))
222 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
223 }
224
225 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
4419dbe6
MC		 226 struct tx_push_buffer *tx_push_buf = txr->tx_push;
227 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
228 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
229 void *pdata = tx_push_buf->data;
230 u64 *end;
231 int j, push_len;
c0c050c5
MC		 232
233 /* Set COAL_NOW to be ready quickly for the next push */
234 tx_push->tx_bd_len_flags_type =
235 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
236 TX_BD_TYPE_LONG_TX_BD |
237 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
238 TX_BD_FLAGS_COAL_NOW |
239 TX_BD_FLAGS_PACKET_END |
240 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
241
242 if (skb->ip_summed == CHECKSUM_PARTIAL)
243 tx_push1->tx_bd_hsize_lflags =
244 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
245 else
246 tx_push1->tx_bd_hsize_lflags = 0;
247
248 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
249 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
250
4419dbe6
MC		 251 end = PTR_ALIGN(pdata + length + 1, 8) - 1;
252 *end = 0;
253
c0c050c5
MC		 254 skb_copy_from_linear_data(skb, pdata, len);
255 pdata += len;
256 for (j = 0; j < last_frag; j++) {
257 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
258 void *fptr;
259
260 fptr = skb_frag_address_safe(frag);
261 if (!fptr)
262 goto normal_tx;
263
264 memcpy(pdata, fptr, skb_frag_size(frag));
265 pdata += skb_frag_size(frag);
266 }
267
4419dbe6
MC		 268 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
269 txbd->tx_bd_haddr = txr->data_mapping;
c0c050c5
MC		 270 prod = NEXT_TX(prod);
271 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
272 memcpy(txbd, tx_push1, sizeof(*txbd));
273 prod = NEXT_TX(prod);
4419dbe6 274 tx_push->doorbell =
c0c050c5
MC		 275 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
276 txr->tx_prod = prod;
277
278 netdev_tx_sent_queue(txq, skb->len);
279
4419dbe6
MC		 280 push_len = (length + sizeof(*tx_push) + 7) / 8;
281 if (push_len > 16) {
282 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
283 __iowrite64_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
284 push_len - 16);
285 } else {
286 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
287 push_len);
288 }
c0c050c5
MC		 289
290 tx_buf->is_push = 1;
c0c050c5
MC		 291 goto tx_done;
292 }
293
294normal_tx:
295 if (length < BNXT_MIN_PKT_SIZE) {
296 pad = BNXT_MIN_PKT_SIZE - length;
297 if (skb_pad(skb, pad)) {
298 /* SKB already freed. */
299 tx_buf->skb = NULL;
300 return NETDEV_TX_OK;
301 }
302 length = BNXT_MIN_PKT_SIZE;
303 }
304
305 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
306
307 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
308 dev_kfree_skb_any(skb);
309 tx_buf->skb = NULL;
310 return NETDEV_TX_OK;
311 }
312
313 dma_unmap_addr_set(tx_buf, mapping, mapping);
314 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
315 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
316
317 txbd->tx_bd_haddr = cpu_to_le64(mapping);
318
319 prod = NEXT_TX(prod);
320 txbd1 = (struct tx_bd_ext *)
321 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
322
323 txbd1->tx_bd_hsize_lflags = 0;
324 if (skb_is_gso(skb)) {
325 u32 hdr_len;
326
327 if (skb->encapsulation)
328 hdr_len = skb_inner_network_offset(skb) +
329 skb_inner_network_header_len(skb) +
330 inner_tcp_hdrlen(skb);
331 else
332 hdr_len = skb_transport_offset(skb) +
333 tcp_hdrlen(skb);
334
335 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
336 TX_BD_FLAGS_T_IPID |
337 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
338 length = skb_shinfo(skb)->gso_size;
339 txbd1->tx_bd_mss = cpu_to_le32(length);
340 length += hdr_len;
341 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
342 txbd1->tx_bd_hsize_lflags =
343 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
344 txbd1->tx_bd_mss = 0;
345 }
346
347 length >>= 9;
348 flags |= bnxt_lhint_arr[length];
349 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
350
351 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
352 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
353 for (i = 0; i < last_frag; i++) {
354 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
355
356 prod = NEXT_TX(prod);
357 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
358
359 len = skb_frag_size(frag);
360 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
361 DMA_TO_DEVICE);
362
363 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
364 goto tx_dma_error;
365
366 tx_buf = &txr->tx_buf_ring[prod];
367 dma_unmap_addr_set(tx_buf, mapping, mapping);
368
369 txbd->tx_bd_haddr = cpu_to_le64(mapping);
370
371 flags = len << TX_BD_LEN_SHIFT;
372 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
373 }
374
375 flags &= ~TX_BD_LEN;
376 txbd->tx_bd_len_flags_type =
377 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
378 TX_BD_FLAGS_PACKET_END);
379
380 netdev_tx_sent_queue(txq, skb->len);
381
382 /* Sync BD data before updating doorbell */
383 wmb();
384
385 prod = NEXT_TX(prod);
386 txr->tx_prod = prod;
387
388 writel(DB_KEY_TX | prod, txr->tx_doorbell);
389 writel(DB_KEY_TX | prod, txr->tx_doorbell);
390
391tx_done:
392
393 mmiowb();
394
395 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
396 netif_tx_stop_queue(txq);
397
398 /* netif_tx_stop_queue() must be done before checking
399 * tx index in bnxt_tx_avail() below, because in
400 * bnxt_tx_int(), we update tx index before checking for
401 * netif_tx_queue_stopped().
402 */
403 smp_mb();
404 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
405 netif_tx_wake_queue(txq);
406 }
407 return NETDEV_TX_OK;
408
409tx_dma_error:
410 last_frag = i;
411
412 /* start back at beginning and unmap skb */
413 prod = txr->tx_prod;
414 tx_buf = &txr->tx_buf_ring[prod];
415 tx_buf->skb = NULL;
416 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
417 skb_headlen(skb), PCI_DMA_TODEVICE);
418 prod = NEXT_TX(prod);
419
420 /* unmap remaining mapped pages */
421 for (i = 0; i < last_frag; i++) {
422 prod = NEXT_TX(prod);
423 tx_buf = &txr->tx_buf_ring[prod];
424 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
425 skb_frag_size(&skb_shinfo(skb)->frags[i]),
426 PCI_DMA_TODEVICE);
427 }
428
429 dev_kfree_skb_any(skb);
430 return NETDEV_TX_OK;
431}
432
433static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
434{
b6ab4b01 435 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
b81a90d3 436 int index = txr - &bp->tx_ring[0];
c0c050c5
MC		 437 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
438 u16 cons = txr->tx_cons;
439 struct pci_dev *pdev = bp->pdev;
440 int i;
441 unsigned int tx_bytes = 0;
442
443 for (i = 0; i < nr_pkts; i++) {
444 struct bnxt_sw_tx_bd *tx_buf;
445 struct sk_buff *skb;
446 int j, last;
447
448 tx_buf = &txr->tx_buf_ring[cons];
449 cons = NEXT_TX(cons);
450 skb = tx_buf->skb;
451 tx_buf->skb = NULL;
452
453 if (tx_buf->is_push) {
454 tx_buf->is_push = 0;
455 goto next_tx_int;
456 }
457
458 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
459 skb_headlen(skb), PCI_DMA_TODEVICE);
460 last = tx_buf->nr_frags;
461
462 for (j = 0; j < last; j++) {
463 cons = NEXT_TX(cons);
464 tx_buf = &txr->tx_buf_ring[cons];
465 dma_unmap_page(
466 &pdev->dev,
467 dma_unmap_addr(tx_buf, mapping),
468 skb_frag_size(&skb_shinfo(skb)->frags[j]),
469 PCI_DMA_TODEVICE);
470 }
471
472next_tx_int:
473 cons = NEXT_TX(cons);
474
475 tx_bytes += skb->len;
476 dev_kfree_skb_any(skb);
477 }
478
479 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
480 txr->tx_cons = cons;
481
482 /* Need to make the tx_cons update visible to bnxt_start_xmit()
483 * before checking for netif_tx_queue_stopped(). Without the
484 * memory barrier, there is a small possibility that bnxt_start_xmit()
485 * will miss it and cause the queue to be stopped forever.
486 */
487 smp_mb();
488
489 if (unlikely(netif_tx_queue_stopped(txq)) &&
490 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
491 __netif_tx_lock(txq, smp_processor_id());
492 if (netif_tx_queue_stopped(txq) &&
493 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
494 txr->dev_state != BNXT_DEV_STATE_CLOSING)
495 netif_tx_wake_queue(txq);
496 __netif_tx_unlock(txq);
497 }
498}
499
500static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
501 gfp_t gfp)
502{
503 u8 *data;
504 struct pci_dev *pdev = bp->pdev;
505
506 data = kmalloc(bp->rx_buf_size, gfp);
507 if (!data)
508 return NULL;
509
510 *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
511 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
512
513 if (dma_mapping_error(&pdev->dev, *mapping)) {
514 kfree(data);
515 data = NULL;
516 }
517 return data;
518}
519
520static inline int bnxt_alloc_rx_data(struct bnxt *bp,
521 struct bnxt_rx_ring_info *rxr,
522 u16 prod, gfp_t gfp)
523{
524 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
525 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
526 u8 *data;
527 dma_addr_t mapping;
528
529 data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
530 if (!data)
531 return -ENOMEM;
532
533 rx_buf->data = data;
534 dma_unmap_addr_set(rx_buf, mapping, mapping);
535
536 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
537
538 return 0;
539}
540
541static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
542 u8 *data)
543{
544 u16 prod = rxr->rx_prod;
545 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
546 struct rx_bd *cons_bd, *prod_bd;
547
548 prod_rx_buf = &rxr->rx_buf_ring[prod];
549 cons_rx_buf = &rxr->rx_buf_ring[cons];
550
551 prod_rx_buf->data = data;
552
553 dma_unmap_addr_set(prod_rx_buf, mapping,
554 dma_unmap_addr(cons_rx_buf, mapping));
555
556 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
557 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
558
559 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
560}
561
562static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
563{
564 u16 next, max = rxr->rx_agg_bmap_size;
565
566 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
567 if (next >= max)
568 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
569 return next;
570}
571
572static inline int bnxt_alloc_rx_page(struct bnxt *bp,
573 struct bnxt_rx_ring_info *rxr,
574 u16 prod, gfp_t gfp)
575{
576 struct rx_bd *rxbd =
577 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
578 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
579 struct pci_dev *pdev = bp->pdev;
580 struct page *page;
581 dma_addr_t mapping;
582 u16 sw_prod = rxr->rx_sw_agg_prod;
583
584 page = alloc_page(gfp);
585 if (!page)
586 return -ENOMEM;
587
588 mapping = dma_map_page(&pdev->dev, page, 0, PAGE_SIZE,
589 PCI_DMA_FROMDEVICE);
590 if (dma_mapping_error(&pdev->dev, mapping)) {
591 __free_page(page);
592 return -EIO;
593 }
594
595 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
596 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
597
598 __set_bit(sw_prod, rxr->rx_agg_bmap);
599 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
600 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
601
602 rx_agg_buf->page = page;
603 rx_agg_buf->mapping = mapping;
604 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
605 rxbd->rx_bd_opaque = sw_prod;
606 return 0;
607}
608
609static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
610 u32 agg_bufs)
611{
612 struct bnxt *bp = bnapi->bp;
613 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 614 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 615 u16 prod = rxr->rx_agg_prod;
616 u16 sw_prod = rxr->rx_sw_agg_prod;
617 u32 i;
618
619 for (i = 0; i < agg_bufs; i++) {
620 u16 cons;
621 struct rx_agg_cmp *agg;
622 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
623 struct rx_bd *prod_bd;
624 struct page *page;
625
626 agg = (struct rx_agg_cmp *)
627 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
628 cons = agg->rx_agg_cmp_opaque;
629 __clear_bit(cons, rxr->rx_agg_bmap);
630
631 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
632 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
633
634 __set_bit(sw_prod, rxr->rx_agg_bmap);
635 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
636 cons_rx_buf = &rxr->rx_agg_ring[cons];
637
638 /* It is possible for sw_prod to be equal to cons, so
639 * set cons_rx_buf->page to NULL first.
640 */
641 page = cons_rx_buf->page;
642 cons_rx_buf->page = NULL;
643 prod_rx_buf->page = page;
644
645 prod_rx_buf->mapping = cons_rx_buf->mapping;
646
647 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
648
649 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
650 prod_bd->rx_bd_opaque = sw_prod;
651
652 prod = NEXT_RX_AGG(prod);
653 sw_prod = NEXT_RX_AGG(sw_prod);
654 cp_cons = NEXT_CMP(cp_cons);
655 }
656 rxr->rx_agg_prod = prod;
657 rxr->rx_sw_agg_prod = sw_prod;
658}
659
660static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
661 struct bnxt_rx_ring_info *rxr, u16 cons,
662 u16 prod, u8 *data, dma_addr_t dma_addr,
663 unsigned int len)
664{
665 int err;
666 struct sk_buff *skb;
667
668 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
669 if (unlikely(err)) {
670 bnxt_reuse_rx_data(rxr, cons, data);
671 return NULL;
672 }
673
674 skb = build_skb(data, 0);
675 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
676 PCI_DMA_FROMDEVICE);
677 if (!skb) {
678 kfree(data);
679 return NULL;
680 }
681
682 skb_reserve(skb, BNXT_RX_OFFSET);
683 skb_put(skb, len);
684 return skb;
685}
686
687static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
688 struct sk_buff *skb, u16 cp_cons,
689 u32 agg_bufs)
690{
691 struct pci_dev *pdev = bp->pdev;
692 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 693 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 694 u16 prod = rxr->rx_agg_prod;
695 u32 i;
696
697 for (i = 0; i < agg_bufs; i++) {
698 u16 cons, frag_len;
699 struct rx_agg_cmp *agg;
700 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
701 struct page *page;
702 dma_addr_t mapping;
703
704 agg = (struct rx_agg_cmp *)
705 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
706 cons = agg->rx_agg_cmp_opaque;
707 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
708 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
709
710 cons_rx_buf = &rxr->rx_agg_ring[cons];
711 skb_fill_page_desc(skb, i, cons_rx_buf->page, 0, frag_len);
712 __clear_bit(cons, rxr->rx_agg_bmap);
713
714 /* It is possible for bnxt_alloc_rx_page() to allocate
715 * a sw_prod index that equals the cons index, so we
716 * need to clear the cons entry now.
717 */
718 mapping = dma_unmap_addr(cons_rx_buf, mapping);
719 page = cons_rx_buf->page;
720 cons_rx_buf->page = NULL;
721
722 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
723 struct skb_shared_info *shinfo;
724 unsigned int nr_frags;
725
726 shinfo = skb_shinfo(skb);
727 nr_frags = --shinfo->nr_frags;
728 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
729
730 dev_kfree_skb(skb);
731
732 cons_rx_buf->page = page;
733
734 /* Update prod since possibly some pages have been
735 * allocated already.
736 */
737 rxr->rx_agg_prod = prod;
738 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
739 return NULL;
740 }
741
742 dma_unmap_page(&pdev->dev, mapping, PAGE_SIZE,
743 PCI_DMA_FROMDEVICE);
744
745 skb->data_len += frag_len;
746 skb->len += frag_len;
747 skb->truesize += PAGE_SIZE;
748
749 prod = NEXT_RX_AGG(prod);
750 cp_cons = NEXT_CMP(cp_cons);
751 }
752 rxr->rx_agg_prod = prod;
753 return skb;
754}
755
756static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
757 u8 agg_bufs, u32 *raw_cons)
758{
759 u16 last;
760 struct rx_agg_cmp *agg;
761
762 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
763 last = RING_CMP(*raw_cons);
764 agg = (struct rx_agg_cmp *)
765 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
766 return RX_AGG_CMP_VALID(agg, *raw_cons);
767}
768
769static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
770 unsigned int len,
771 dma_addr_t mapping)
772{
773 struct bnxt *bp = bnapi->bp;
774 struct pci_dev *pdev = bp->pdev;
775 struct sk_buff *skb;
776
777 skb = napi_alloc_skb(&bnapi->napi, len);
778 if (!skb)
779 return NULL;
780
781 dma_sync_single_for_cpu(&pdev->dev, mapping,
782 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
783
784 memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
785
786 dma_sync_single_for_device(&pdev->dev, mapping,
787 bp->rx_copy_thresh,
788 PCI_DMA_FROMDEVICE);
789
790 skb_put(skb, len);
791 return skb;
792}
793
794static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
795 struct rx_tpa_start_cmp *tpa_start,
796 struct rx_tpa_start_cmp_ext *tpa_start1)
797{
798 u8 agg_id = TPA_START_AGG_ID(tpa_start);
799 u16 cons, prod;
800 struct bnxt_tpa_info *tpa_info;
801 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
802 struct rx_bd *prod_bd;
803 dma_addr_t mapping;
804
805 cons = tpa_start->rx_tpa_start_cmp_opaque;
806 prod = rxr->rx_prod;
807 cons_rx_buf = &rxr->rx_buf_ring[cons];
808 prod_rx_buf = &rxr->rx_buf_ring[prod];
809 tpa_info = &rxr->rx_tpa[agg_id];
810
811 prod_rx_buf->data = tpa_info->data;
812
813 mapping = tpa_info->mapping;
814 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
815
816 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
817
818 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
819
820 tpa_info->data = cons_rx_buf->data;
821 cons_rx_buf->data = NULL;
822 tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
823
824 tpa_info->len =
825 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
826 RX_TPA_START_CMP_LEN_SHIFT;
827 if (likely(TPA_START_HASH_VALID(tpa_start))) {
828 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
829
830 tpa_info->hash_type = PKT_HASH_TYPE_L4;
831 tpa_info->gso_type = SKB_GSO_TCPV4;
832 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
833 if (hash_type == 3)
834 tpa_info->gso_type = SKB_GSO_TCPV6;
835 tpa_info->rss_hash =
836 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
837 } else {
838 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
839 tpa_info->gso_type = 0;
840 if (netif_msg_rx_err(bp))
841 netdev_warn(bp->dev, "TPA packet without valid hash\n");
842 }
843 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
844 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
845
846 rxr->rx_prod = NEXT_RX(prod);
847 cons = NEXT_RX(cons);
848 cons_rx_buf = &rxr->rx_buf_ring[cons];
849
850 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
851 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
852 cons_rx_buf->data = NULL;
853}
854
855static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
856 u16 cp_cons, u32 agg_bufs)
857{
858 if (agg_bufs)
859 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
860}
861
862#define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
863#define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
864
865static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info,
866 struct rx_tpa_end_cmp *tpa_end,
867 struct rx_tpa_end_cmp_ext *tpa_end1,
868 struct sk_buff *skb)
869{
d1611c3a 870#ifdef CONFIG_INET
c0c050c5
MC		 871 struct tcphdr *th;
872 int payload_off, tcp_opt_len = 0;
873 int len, nw_off;
27e24189 874 u16 segs;
c0c050c5 875
27e24189
MC		 876 segs = TPA_END_TPA_SEGS(tpa_end);
877 if (segs == 1)
878 return skb;
879
880 NAPI_GRO_CB(skb)->count = segs;
c0c050c5
MC		 881 skb_shinfo(skb)->gso_size =
882 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
883 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
884 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
885 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
886 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
887 if (TPA_END_GRO_TS(tpa_end))
888 tcp_opt_len = 12;
889
c0c050c5
MC		 890 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
891 struct iphdr *iph;
892
893 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
894 ETH_HLEN;
895 skb_set_network_header(skb, nw_off);
896 iph = ip_hdr(skb);
897 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
898 len = skb->len - skb_transport_offset(skb);
899 th = tcp_hdr(skb);
900 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
901 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
902 struct ipv6hdr *iph;
903
904 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
905 ETH_HLEN;
906 skb_set_network_header(skb, nw_off);
907 iph = ipv6_hdr(skb);
908 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
909 len = skb->len - skb_transport_offset(skb);
910 th = tcp_hdr(skb);
911 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
912 } else {
913 dev_kfree_skb_any(skb);
914 return NULL;
915 }
916 tcp_gro_complete(skb);
917
918 if (nw_off) { /* tunnel */
919 struct udphdr *uh = NULL;
920
921 if (skb->protocol == htons(ETH_P_IP)) {
922 struct iphdr *iph = (struct iphdr *)skb->data;
923
924 if (iph->protocol == IPPROTO_UDP)
925 uh = (struct udphdr *)(iph + 1);
926 } else {
927 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
928
929 if (iph->nexthdr == IPPROTO_UDP)
930 uh = (struct udphdr *)(iph + 1);
931 }
932 if (uh) {
933 if (uh->check)
934 skb_shinfo(skb)->gso_type |=
935 SKB_GSO_UDP_TUNNEL_CSUM;
936 else
937 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
938 }
939 }
940#endif
941 return skb;
942}
943
944static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
945 struct bnxt_napi *bnapi,
946 u32 *raw_cons,
947 struct rx_tpa_end_cmp *tpa_end,
948 struct rx_tpa_end_cmp_ext *tpa_end1,
949 bool *agg_event)
950{
951 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 952 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 953 u8 agg_id = TPA_END_AGG_ID(tpa_end);
954 u8 *data, agg_bufs;
955 u16 cp_cons = RING_CMP(*raw_cons);
956 unsigned int len;
957 struct bnxt_tpa_info *tpa_info;
958 dma_addr_t mapping;
959 struct sk_buff *skb;
960
961 tpa_info = &rxr->rx_tpa[agg_id];
962 data = tpa_info->data;
963 prefetch(data);
964 len = tpa_info->len;
965 mapping = tpa_info->mapping;
966
967 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
968 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
969
970 if (agg_bufs) {
971 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
972 return ERR_PTR(-EBUSY);
973
974 *agg_event = true;
975 cp_cons = NEXT_CMP(cp_cons);
976 }
977
978 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
979 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
980 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
981 agg_bufs, (int)MAX_SKB_FRAGS);
982 return NULL;
983 }
984
985 if (len <= bp->rx_copy_thresh) {
986 skb = bnxt_copy_skb(bnapi, data, len, mapping);
987 if (!skb) {
988 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
989 return NULL;
990 }
991 } else {
992 u8 *new_data;
993 dma_addr_t new_mapping;
994
995 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
996 if (!new_data) {
997 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
998 return NULL;
999 }
1000
1001 tpa_info->data = new_data;
1002 tpa_info->mapping = new_mapping;
1003
1004 skb = build_skb(data, 0);
1005 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1006 PCI_DMA_FROMDEVICE);
1007
1008 if (!skb) {
1009 kfree(data);
1010 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1011 return NULL;
1012 }
1013 skb_reserve(skb, BNXT_RX_OFFSET);
1014 skb_put(skb, len);
1015 }
1016
1017 if (agg_bufs) {
1018 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1019 if (!skb) {
1020 /* Page reuse already handled by bnxt_rx_pages(). */
1021 return NULL;
1022 }
1023 }
1024 skb->protocol = eth_type_trans(skb, bp->dev);
1025
1026 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1027 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1028
1029 if (tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) {
1030 netdev_features_t features = skb->dev->features;
1031 u16 vlan_proto = tpa_info->metadata >>
1032 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1033
1034 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1035 vlan_proto == ETH_P_8021Q) ||
1036 ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1037 vlan_proto == ETH_P_8021AD)) {
1038 __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1039 tpa_info->metadata &
1040 RX_CMP_FLAGS2_METADATA_VID_MASK);
1041 }
1042 }
1043
1044 skb_checksum_none_assert(skb);
1045 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1046 skb->ip_summed = CHECKSUM_UNNECESSARY;
1047 skb->csum_level =
1048 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1049 }
1050
1051 if (TPA_END_GRO(tpa_end))
1052 skb = bnxt_gro_skb(tpa_info, tpa_end, tpa_end1, skb);
1053
1054 return skb;
1055}
1056
1057/* returns the following:
1058 * 1 - 1 packet successfully received
1059 * 0 - successful TPA_START, packet not completed yet
1060 * -EBUSY - completion ring does not have all the agg buffers yet
1061 * -ENOMEM - packet aborted due to out of memory
1062 * -EIO - packet aborted due to hw error indicated in BD
1063 */
1064static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1065 bool *agg_event)
1066{
1067 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1068 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1069 struct net_device *dev = bp->dev;
1070 struct rx_cmp *rxcmp;
1071 struct rx_cmp_ext *rxcmp1;
1072 u32 tmp_raw_cons = *raw_cons;
1073 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1074 struct bnxt_sw_rx_bd *rx_buf;
1075 unsigned int len;
1076 u8 *data, agg_bufs, cmp_type;
1077 dma_addr_t dma_addr;
1078 struct sk_buff *skb;
1079 int rc = 0;
1080
1081 rxcmp = (struct rx_cmp *)
1082 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1083
1084 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1085 cp_cons = RING_CMP(tmp_raw_cons);
1086 rxcmp1 = (struct rx_cmp_ext *)
1087 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1088
1089 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1090 return -EBUSY;
1091
1092 cmp_type = RX_CMP_TYPE(rxcmp);
1093
1094 prod = rxr->rx_prod;
1095
1096 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1097 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1098 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1099
1100 goto next_rx_no_prod;
1101
1102 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1103 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1104 (struct rx_tpa_end_cmp *)rxcmp,
1105 (struct rx_tpa_end_cmp_ext *)rxcmp1,
1106 agg_event);
1107
1108 if (unlikely(IS_ERR(skb)))
1109 return -EBUSY;
1110
1111 rc = -ENOMEM;
1112 if (likely(skb)) {
1113 skb_record_rx_queue(skb, bnapi->index);
1114 skb_mark_napi_id(skb, &bnapi->napi);
1115 if (bnxt_busy_polling(bnapi))
1116 netif_receive_skb(skb);
1117 else
1118 napi_gro_receive(&bnapi->napi, skb);
1119 rc = 1;
1120 }
1121 goto next_rx_no_prod;
1122 }
1123
1124 cons = rxcmp->rx_cmp_opaque;
1125 rx_buf = &rxr->rx_buf_ring[cons];
1126 data = rx_buf->data;
1127 prefetch(data);
1128
1129 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1130 RX_CMP_AGG_BUFS_SHIFT;
1131
1132 if (agg_bufs) {
1133 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1134 return -EBUSY;
1135
1136 cp_cons = NEXT_CMP(cp_cons);
1137 *agg_event = true;
1138 }
1139
1140 rx_buf->data = NULL;
1141 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1142 bnxt_reuse_rx_data(rxr, cons, data);
1143 if (agg_bufs)
1144 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1145
1146 rc = -EIO;
1147 goto next_rx;
1148 }
1149
1150 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1151 dma_addr = dma_unmap_addr(rx_buf, mapping);
1152
1153 if (len <= bp->rx_copy_thresh) {
1154 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1155 bnxt_reuse_rx_data(rxr, cons, data);
1156 if (!skb) {
1157 rc = -ENOMEM;
1158 goto next_rx;
1159 }
1160 } else {
1161 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1162 if (!skb) {
1163 rc = -ENOMEM;
1164 goto next_rx;
1165 }
1166 }
1167
1168 if (agg_bufs) {
1169 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1170 if (!skb) {
1171 rc = -ENOMEM;
1172 goto next_rx;
1173 }
1174 }
1175
1176 if (RX_CMP_HASH_VALID(rxcmp)) {
1177 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1178 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1179
1180 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1181 if (hash_type != 1 && hash_type != 3)
1182 type = PKT_HASH_TYPE_L3;
1183 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1184 }
1185
1186 skb->protocol = eth_type_trans(skb, dev);
1187
1188 if (rxcmp1->rx_cmp_flags2 &
1189 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) {
1190 netdev_features_t features = skb->dev->features;
1191 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1192 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1193
1194 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1195 vlan_proto == ETH_P_8021Q) ||
1196 ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1197 vlan_proto == ETH_P_8021AD))
1198 __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1199 meta_data &
1200 RX_CMP_FLAGS2_METADATA_VID_MASK);
1201 }
1202
1203 skb_checksum_none_assert(skb);
1204 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1205 if (dev->features & NETIF_F_RXCSUM) {
1206 skb->ip_summed = CHECKSUM_UNNECESSARY;
1207 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1208 }
1209 } else {
665e350d
SB		 1210 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1211 if (dev->features & NETIF_F_RXCSUM)
1212 cpr->rx_l4_csum_errors++;
1213 }
c0c050c5
MC		 1214 }
1215
1216 skb_record_rx_queue(skb, bnapi->index);
1217 skb_mark_napi_id(skb, &bnapi->napi);
1218 if (bnxt_busy_polling(bnapi))
1219 netif_receive_skb(skb);
1220 else
1221 napi_gro_receive(&bnapi->napi, skb);
1222 rc = 1;
1223
1224next_rx:
1225 rxr->rx_prod = NEXT_RX(prod);
1226
1227next_rx_no_prod:
1228 *raw_cons = tmp_raw_cons;
1229
1230 return rc;
1231}
1232
1233static int bnxt_async_event_process(struct bnxt *bp,
1234 struct hwrm_async_event_cmpl *cmpl)
1235{
1236 u16 event_id = le16_to_cpu(cmpl->event_id);
1237
1238 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1239 switch (event_id) {
1240 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1241 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
19241368
JH		 1242 break;
1243 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1244 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
c0c050c5
MC		 1245 break;
1246 default:
1247 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1248 event_id);
19241368 1249 goto async_event_process_exit;
c0c050c5 1250 }
19241368
JH		 1251 schedule_work(&bp->sp_task);
1252async_event_process_exit:
c0c050c5
MC		 1253 return 0;
1254}
1255
1256static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1257{
1258 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1259 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1260 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1261 (struct hwrm_fwd_req_cmpl *)txcmp;
1262
1263 switch (cmpl_type) {
1264 case CMPL_BASE_TYPE_HWRM_DONE:
1265 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1266 if (seq_id == bp->hwrm_intr_seq_id)
1267 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1268 else
1269 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1270 break;
1271
1272 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1273 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1274
1275 if ((vf_id < bp->pf.first_vf_id) ||
1276 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1277 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1278 vf_id);
1279 return -EINVAL;
1280 }
1281
1282 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1283 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1284 schedule_work(&bp->sp_task);
1285 break;
1286
1287 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1288 bnxt_async_event_process(bp,
1289 (struct hwrm_async_event_cmpl *)txcmp);
1290
1291 default:
1292 break;
1293 }
1294
1295 return 0;
1296}
1297
1298static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1299{
1300 struct bnxt_napi *bnapi = dev_instance;
1301 struct bnxt *bp = bnapi->bp;
1302 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1303 u32 cons = RING_CMP(cpr->cp_raw_cons);
1304
1305 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1306 napi_schedule(&bnapi->napi);
1307 return IRQ_HANDLED;
1308}
1309
1310static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1311{
1312 u32 raw_cons = cpr->cp_raw_cons;
1313 u16 cons = RING_CMP(raw_cons);
1314 struct tx_cmp *txcmp;
1315
1316 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1317
1318 return TX_CMP_VALID(txcmp, raw_cons);
1319}
1320
c0c050c5
MC		 1321static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1322{
1323 struct bnxt_napi *bnapi = dev_instance;
1324 struct bnxt *bp = bnapi->bp;
1325 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1326 u32 cons = RING_CMP(cpr->cp_raw_cons);
1327 u32 int_status;
1328
1329 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1330
1331 if (!bnxt_has_work(bp, cpr)) {
11809490 1332 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
c0c050c5
MC		 1333 /* return if erroneous interrupt */
1334 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1335 return IRQ_NONE;
1336 }
1337
1338 /* disable ring IRQ */
1339 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1340
1341 /* Return here if interrupt is shared and is disabled. */
1342 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1343 return IRQ_HANDLED;
1344
1345 napi_schedule(&bnapi->napi);
1346 return IRQ_HANDLED;
1347}
1348
1349static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1350{
1351 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1352 u32 raw_cons = cpr->cp_raw_cons;
1353 u32 cons;
1354 int tx_pkts = 0;
1355 int rx_pkts = 0;
1356 bool rx_event = false;
1357 bool agg_event = false;
1358 struct tx_cmp *txcmp;
1359
1360 while (1) {
1361 int rc;
1362
1363 cons = RING_CMP(raw_cons);
1364 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1365
1366 if (!TX_CMP_VALID(txcmp, raw_cons))
1367 break;
1368
1369 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1370 tx_pkts++;
1371 /* return full budget so NAPI will complete. */
1372 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1373 rx_pkts = budget;
1374 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1375 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1376 if (likely(rc >= 0))
1377 rx_pkts += rc;
1378 else if (rc == -EBUSY) /* partial completion */
1379 break;
1380 rx_event = true;
1381 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1382 CMPL_BASE_TYPE_HWRM_DONE) ||
1383 (TX_CMP_TYPE(txcmp) ==
1384 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1385 (TX_CMP_TYPE(txcmp) ==
1386 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1387 bnxt_hwrm_handler(bp, txcmp);
1388 }
1389 raw_cons = NEXT_RAW_CMP(raw_cons);
1390
1391 if (rx_pkts == budget)
1392 break;
1393 }
1394
1395 cpr->cp_raw_cons = raw_cons;
1396 /* ACK completion ring before freeing tx ring and producing new
1397 * buffers in rx/agg rings to prevent overflowing the completion
1398 * ring.
1399 */
1400 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1401
1402 if (tx_pkts)
1403 bnxt_tx_int(bp, bnapi, tx_pkts);
1404
1405 if (rx_event) {
b6ab4b01 1406 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1407
1408 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1409 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1410 if (agg_event) {
1411 writel(DB_KEY_RX | rxr->rx_agg_prod,
1412 rxr->rx_agg_doorbell);
1413 writel(DB_KEY_RX | rxr->rx_agg_prod,
1414 rxr->rx_agg_doorbell);
1415 }
1416 }
1417 return rx_pkts;
1418}
1419
1420static int bnxt_poll(struct napi_struct *napi, int budget)
1421{
1422 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1423 struct bnxt *bp = bnapi->bp;
1424 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1425 int work_done = 0;
1426
1427 if (!bnxt_lock_napi(bnapi))
1428 return budget;
1429
1430 while (1) {
1431 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1432
1433 if (work_done >= budget)
1434 break;
1435
1436 if (!bnxt_has_work(bp, cpr)) {
1437 napi_complete(napi);
1438 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1439 break;
1440 }
1441 }
1442 mmiowb();
1443 bnxt_unlock_napi(bnapi);
1444 return work_done;
1445}
1446
1447#ifdef CONFIG_NET_RX_BUSY_POLL
1448static int bnxt_busy_poll(struct napi_struct *napi)
1449{
1450 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1451 struct bnxt *bp = bnapi->bp;
1452 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1453 int rx_work, budget = 4;
1454
1455 if (atomic_read(&bp->intr_sem) != 0)
1456 return LL_FLUSH_FAILED;
1457
1458 if (!bnxt_lock_poll(bnapi))
1459 return LL_FLUSH_BUSY;
1460
1461 rx_work = bnxt_poll_work(bp, bnapi, budget);
1462
1463 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1464
1465 bnxt_unlock_poll(bnapi);
1466 return rx_work;
1467}
1468#endif
1469
1470static void bnxt_free_tx_skbs(struct bnxt *bp)
1471{
1472 int i, max_idx;
1473 struct pci_dev *pdev = bp->pdev;
1474
b6ab4b01 1475 if (!bp->tx_ring)
c0c050c5
MC		 1476 return;
1477
1478 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1479 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 1480 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 1481 int j;
1482
c0c050c5
MC		 1483 for (j = 0; j < max_idx;) {
1484 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1485 struct sk_buff *skb = tx_buf->skb;
1486 int k, last;
1487
1488 if (!skb) {
1489 j++;
1490 continue;
1491 }
1492
1493 tx_buf->skb = NULL;
1494
1495 if (tx_buf->is_push) {
1496 dev_kfree_skb(skb);
1497 j += 2;
1498 continue;
1499 }
1500
1501 dma_unmap_single(&pdev->dev,
1502 dma_unmap_addr(tx_buf, mapping),
1503 skb_headlen(skb),
1504 PCI_DMA_TODEVICE);
1505
1506 last = tx_buf->nr_frags;
1507 j += 2;
d612a579
MC		 1508 for (k = 0; k < last; k++, j++) {
1509 int ring_idx = j & bp->tx_ring_mask;
c0c050c5
MC		 1510 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1511
d612a579 1512 tx_buf = &txr->tx_buf_ring[ring_idx];
c0c050c5
MC		 1513 dma_unmap_page(
1514 &pdev->dev,
1515 dma_unmap_addr(tx_buf, mapping),
1516 skb_frag_size(frag), PCI_DMA_TODEVICE);
1517 }
1518 dev_kfree_skb(skb);
1519 }
1520 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1521 }
1522}
1523
1524static void bnxt_free_rx_skbs(struct bnxt *bp)
1525{
1526 int i, max_idx, max_agg_idx;
1527 struct pci_dev *pdev = bp->pdev;
1528
b6ab4b01 1529 if (!bp->rx_ring)
c0c050c5
MC		 1530 return;
1531
1532 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1533 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1534 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 1535 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 1536 int j;
1537
c0c050c5
MC		 1538 if (rxr->rx_tpa) {
1539 for (j = 0; j < MAX_TPA; j++) {
1540 struct bnxt_tpa_info *tpa_info =
1541 &rxr->rx_tpa[j];
1542 u8 *data = tpa_info->data;
1543
1544 if (!data)
1545 continue;
1546
1547 dma_unmap_single(
1548 &pdev->dev,
1549 dma_unmap_addr(tpa_info, mapping),
1550 bp->rx_buf_use_size,
1551 PCI_DMA_FROMDEVICE);
1552
1553 tpa_info->data = NULL;
1554
1555 kfree(data);
1556 }
1557 }
1558
1559 for (j = 0; j < max_idx; j++) {
1560 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1561 u8 *data = rx_buf->data;
1562
1563 if (!data)
1564 continue;
1565
1566 dma_unmap_single(&pdev->dev,
1567 dma_unmap_addr(rx_buf, mapping),
1568 bp->rx_buf_use_size,
1569 PCI_DMA_FROMDEVICE);
1570
1571 rx_buf->data = NULL;
1572
1573 kfree(data);
1574 }
1575
1576 for (j = 0; j < max_agg_idx; j++) {
1577 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1578 &rxr->rx_agg_ring[j];
1579 struct page *page = rx_agg_buf->page;
1580
1581 if (!page)
1582 continue;
1583
1584 dma_unmap_page(&pdev->dev,
1585 dma_unmap_addr(rx_agg_buf, mapping),
1586 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1587
1588 rx_agg_buf->page = NULL;
1589 __clear_bit(j, rxr->rx_agg_bmap);
1590
1591 __free_page(page);
1592 }
1593 }
1594}
1595
1596static void bnxt_free_skbs(struct bnxt *bp)
1597{
1598 bnxt_free_tx_skbs(bp);
1599 bnxt_free_rx_skbs(bp);
1600}
1601
1602static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1603{
1604 struct pci_dev *pdev = bp->pdev;
1605 int i;
1606
1607 for (i = 0; i < ring->nr_pages; i++) {
1608 if (!ring->pg_arr[i])
1609 continue;
1610
1611 dma_free_coherent(&pdev->dev, ring->page_size,
1612 ring->pg_arr[i], ring->dma_arr[i]);
1613
1614 ring->pg_arr[i] = NULL;
1615 }
1616 if (ring->pg_tbl) {
1617 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1618 ring->pg_tbl, ring->pg_tbl_map);
1619 ring->pg_tbl = NULL;
1620 }
1621 if (ring->vmem_size && *ring->vmem) {
1622 vfree(*ring->vmem);
1623 *ring->vmem = NULL;
1624 }
1625}
1626
1627static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1628{
1629 int i;
1630 struct pci_dev *pdev = bp->pdev;
1631
1632 if (ring->nr_pages > 1) {
1633 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1634 ring->nr_pages * 8,
1635 &ring->pg_tbl_map,
1636 GFP_KERNEL);
1637 if (!ring->pg_tbl)
1638 return -ENOMEM;
1639 }
1640
1641 for (i = 0; i < ring->nr_pages; i++) {
1642 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1643 ring->page_size,
1644 &ring->dma_arr[i],
1645 GFP_KERNEL);
1646 if (!ring->pg_arr[i])
1647 return -ENOMEM;
1648
1649 if (ring->nr_pages > 1)
1650 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1651 }
1652
1653 if (ring->vmem_size) {
1654 *ring->vmem = vzalloc(ring->vmem_size);
1655 if (!(*ring->vmem))
1656 return -ENOMEM;
1657 }
1658 return 0;
1659}
1660
1661static void bnxt_free_rx_rings(struct bnxt *bp)
1662{
1663 int i;
1664
b6ab4b01 1665 if (!bp->rx_ring)
c0c050c5
MC		 1666 return;
1667
1668 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 1669 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 1670 struct bnxt_ring_struct *ring;
1671
c0c050c5
MC		 1672 kfree(rxr->rx_tpa);
1673 rxr->rx_tpa = NULL;
1674
1675 kfree(rxr->rx_agg_bmap);
1676 rxr->rx_agg_bmap = NULL;
1677
1678 ring = &rxr->rx_ring_struct;
1679 bnxt_free_ring(bp, ring);
1680
1681 ring = &rxr->rx_agg_ring_struct;
1682 bnxt_free_ring(bp, ring);
1683 }
1684}
1685
1686static int bnxt_alloc_rx_rings(struct bnxt *bp)
1687{
1688 int i, rc, agg_rings = 0, tpa_rings = 0;
1689
b6ab4b01
MC		 1690 if (!bp->rx_ring)
1691 return -ENOMEM;
1692
c0c050c5
MC		 1693 if (bp->flags & BNXT_FLAG_AGG_RINGS)
1694 agg_rings = 1;
1695
1696 if (bp->flags & BNXT_FLAG_TPA)
1697 tpa_rings = 1;
1698
1699 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 1700 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 1701 struct bnxt_ring_struct *ring;
1702
c0c050c5
MC		 1703 ring = &rxr->rx_ring_struct;
1704
1705 rc = bnxt_alloc_ring(bp, ring);
1706 if (rc)
1707 return rc;
1708
1709 if (agg_rings) {
1710 u16 mem_size;
1711
1712 ring = &rxr->rx_agg_ring_struct;
1713 rc = bnxt_alloc_ring(bp, ring);
1714 if (rc)
1715 return rc;
1716
1717 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1718 mem_size = rxr->rx_agg_bmap_size / 8;
1719 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1720 if (!rxr->rx_agg_bmap)
1721 return -ENOMEM;
1722
1723 if (tpa_rings) {
1724 rxr->rx_tpa = kcalloc(MAX_TPA,
1725 sizeof(struct bnxt_tpa_info),
1726 GFP_KERNEL);
1727 if (!rxr->rx_tpa)
1728 return -ENOMEM;
1729 }
1730 }
1731 }
1732 return 0;
1733}
1734
1735static void bnxt_free_tx_rings(struct bnxt *bp)
1736{
1737 int i;
1738 struct pci_dev *pdev = bp->pdev;
1739
b6ab4b01 1740 if (!bp->tx_ring)
c0c050c5
MC		 1741 return;
1742
1743 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 1744 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 1745 struct bnxt_ring_struct *ring;
1746
c0c050c5
MC		 1747 if (txr->tx_push) {
1748 dma_free_coherent(&pdev->dev, bp->tx_push_size,
1749 txr->tx_push, txr->tx_push_mapping);
1750 txr->tx_push = NULL;
1751 }
1752
1753 ring = &txr->tx_ring_struct;
1754
1755 bnxt_free_ring(bp, ring);
1756 }
1757}
1758
1759static int bnxt_alloc_tx_rings(struct bnxt *bp)
1760{
1761 int i, j, rc;
1762 struct pci_dev *pdev = bp->pdev;
1763
1764 bp->tx_push_size = 0;
1765 if (bp->tx_push_thresh) {
1766 int push_size;
1767
1768 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
1769 bp->tx_push_thresh);
1770
4419dbe6 1771 if (push_size > 256) {
c0c050c5
MC		 1772 push_size = 0;
1773 bp->tx_push_thresh = 0;
1774 }
1775
1776 bp->tx_push_size = push_size;
1777 }
1778
1779 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 1780 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 1781 struct bnxt_ring_struct *ring;
1782
c0c050c5
MC		 1783 ring = &txr->tx_ring_struct;
1784
1785 rc = bnxt_alloc_ring(bp, ring);
1786 if (rc)
1787 return rc;
1788
1789 if (bp->tx_push_size) {
c0c050c5
MC		 1790 dma_addr_t mapping;
1791
1792 /* One pre-allocated DMA buffer to backup
1793 * TX push operation
1794 */
1795 txr->tx_push = dma_alloc_coherent(&pdev->dev,
1796 bp->tx_push_size,
1797 &txr->tx_push_mapping,
1798 GFP_KERNEL);
1799
1800 if (!txr->tx_push)
1801 return -ENOMEM;
1802
c0c050c5
MC		 1803 mapping = txr->tx_push_mapping +
1804 sizeof(struct tx_push_bd);
4419dbe6 1805 txr->data_mapping = cpu_to_le64(mapping);
c0c050c5 1806
4419dbe6 1807 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
c0c050c5
MC		 1808 }
1809 ring->queue_id = bp->q_info[j].queue_id;
1810 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
1811 j++;
1812 }
1813 return 0;
1814}
1815
1816static void bnxt_free_cp_rings(struct bnxt *bp)
1817{
1818 int i;
1819
1820 if (!bp->bnapi)
1821 return;
1822
1823 for (i = 0; i < bp->cp_nr_rings; i++) {
1824 struct bnxt_napi *bnapi = bp->bnapi[i];
1825 struct bnxt_cp_ring_info *cpr;
1826 struct bnxt_ring_struct *ring;
1827
1828 if (!bnapi)
1829 continue;
1830
1831 cpr = &bnapi->cp_ring;
1832 ring = &cpr->cp_ring_struct;
1833
1834 bnxt_free_ring(bp, ring);
1835 }
1836}
1837
1838static int bnxt_alloc_cp_rings(struct bnxt *bp)
1839{
1840 int i, rc;
1841
1842 for (i = 0; i < bp->cp_nr_rings; i++) {
1843 struct bnxt_napi *bnapi = bp->bnapi[i];
1844 struct bnxt_cp_ring_info *cpr;
1845 struct bnxt_ring_struct *ring;
1846
1847 if (!bnapi)
1848 continue;
1849
1850 cpr = &bnapi->cp_ring;
1851 ring = &cpr->cp_ring_struct;
1852
1853 rc = bnxt_alloc_ring(bp, ring);
1854 if (rc)
1855 return rc;
1856 }
1857 return 0;
1858}
1859
1860static void bnxt_init_ring_struct(struct bnxt *bp)
1861{
1862 int i;
1863
1864 for (i = 0; i < bp->cp_nr_rings; i++) {
1865 struct bnxt_napi *bnapi = bp->bnapi[i];
1866 struct bnxt_cp_ring_info *cpr;
1867 struct bnxt_rx_ring_info *rxr;
1868 struct bnxt_tx_ring_info *txr;
1869 struct bnxt_ring_struct *ring;
1870
1871 if (!bnapi)
1872 continue;
1873
1874 cpr = &bnapi->cp_ring;
1875 ring = &cpr->cp_ring_struct;
1876 ring->nr_pages = bp->cp_nr_pages;
1877 ring->page_size = HW_CMPD_RING_SIZE;
1878 ring->pg_arr = (void **)cpr->cp_desc_ring;
1879 ring->dma_arr = cpr->cp_desc_mapping;
1880 ring->vmem_size = 0;
1881
b6ab4b01 1882 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 1883 if (!rxr)
1884 goto skip_rx;
1885
c0c050c5
MC		 1886 ring = &rxr->rx_ring_struct;
1887 ring->nr_pages = bp->rx_nr_pages;
1888 ring->page_size = HW_RXBD_RING_SIZE;
1889 ring->pg_arr = (void **)rxr->rx_desc_ring;
1890 ring->dma_arr = rxr->rx_desc_mapping;
1891 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
1892 ring->vmem = (void **)&rxr->rx_buf_ring;
1893
1894 ring = &rxr->rx_agg_ring_struct;
1895 ring->nr_pages = bp->rx_agg_nr_pages;
1896 ring->page_size = HW_RXBD_RING_SIZE;
1897 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
1898 ring->dma_arr = rxr->rx_agg_desc_mapping;
1899 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
1900 ring->vmem = (void **)&rxr->rx_agg_ring;
1901
3b2b7d9d 1902skip_rx:
b6ab4b01 1903 txr = bnapi->tx_ring;
3b2b7d9d
MC		 1904 if (!txr)
1905 continue;
1906
c0c050c5
MC		 1907 ring = &txr->tx_ring_struct;
1908 ring->nr_pages = bp->tx_nr_pages;
1909 ring->page_size = HW_RXBD_RING_SIZE;
1910 ring->pg_arr = (void **)txr->tx_desc_ring;
1911 ring->dma_arr = txr->tx_desc_mapping;
1912 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
1913 ring->vmem = (void **)&txr->tx_buf_ring;
1914 }
1915}
1916
1917static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
1918{
1919 int i;
1920 u32 prod;
1921 struct rx_bd **rx_buf_ring;
1922
1923 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
1924 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
1925 int j;
1926 struct rx_bd *rxbd;
1927
1928 rxbd = rx_buf_ring[i];
1929 if (!rxbd)
1930 continue;
1931
1932 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
1933 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
1934 rxbd->rx_bd_opaque = prod;
1935 }
1936 }
1937}
1938
1939static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
1940{
1941 struct net_device *dev = bp->dev;
c0c050c5
MC		 1942 struct bnxt_rx_ring_info *rxr;
1943 struct bnxt_ring_struct *ring;
1944 u32 prod, type;
1945 int i;
1946
c0c050c5
MC		 1947 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
1948 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
1949
1950 if (NET_IP_ALIGN == 2)
1951 type |= RX_BD_FLAGS_SOP;
1952
b6ab4b01 1953 rxr = &bp->rx_ring[ring_nr];
c0c050c5
MC		 1954 ring = &rxr->rx_ring_struct;
1955 bnxt_init_rxbd_pages(ring, type);
1956
1957 prod = rxr->rx_prod;
1958 for (i = 0; i < bp->rx_ring_size; i++) {
1959 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
1960 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
1961 ring_nr, i, bp->rx_ring_size);
1962 break;
1963 }
1964 prod = NEXT_RX(prod);
1965 }
1966 rxr->rx_prod = prod;
1967 ring->fw_ring_id = INVALID_HW_RING_ID;
1968
edd0c2cc
MC		 1969 ring = &rxr->rx_agg_ring_struct;
1970 ring->fw_ring_id = INVALID_HW_RING_ID;
1971
c0c050c5
MC		 1972 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
1973 return 0;
1974
c0c050c5
MC		 1975 type = ((u32)PAGE_SIZE << RX_BD_LEN_SHIFT) |
1976 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
1977
1978 bnxt_init_rxbd_pages(ring, type);
1979
1980 prod = rxr->rx_agg_prod;
1981 for (i = 0; i < bp->rx_agg_ring_size; i++) {
1982 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
1983 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
1984 ring_nr, i, bp->rx_ring_size);
1985 break;
1986 }
1987 prod = NEXT_RX_AGG(prod);
1988 }
1989 rxr->rx_agg_prod = prod;
c0c050c5
MC		 1990
1991 if (bp->flags & BNXT_FLAG_TPA) {
1992 if (rxr->rx_tpa) {
1993 u8 *data;
1994 dma_addr_t mapping;
1995
1996 for (i = 0; i < MAX_TPA; i++) {
1997 data = __bnxt_alloc_rx_data(bp, &mapping,
1998 GFP_KERNEL);
1999 if (!data)
2000 return -ENOMEM;
2001
2002 rxr->rx_tpa[i].data = data;
2003 rxr->rx_tpa[i].mapping = mapping;
2004 }
2005 } else {
2006 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2007 return -ENOMEM;
2008 }
2009 }
2010
2011 return 0;
2012}
2013
2014static int bnxt_init_rx_rings(struct bnxt *bp)
2015{
2016 int i, rc = 0;
2017
2018 for (i = 0; i < bp->rx_nr_rings; i++) {
2019 rc = bnxt_init_one_rx_ring(bp, i);
2020 if (rc)
2021 break;
2022 }
2023
2024 return rc;
2025}
2026
2027static int bnxt_init_tx_rings(struct bnxt *bp)
2028{
2029 u16 i;
2030
2031 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2032 MAX_SKB_FRAGS + 1);
2033
2034 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2035 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2036 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2037
2038 ring->fw_ring_id = INVALID_HW_RING_ID;
2039 }
2040
2041 return 0;
2042}
2043
2044static void bnxt_free_ring_grps(struct bnxt *bp)
2045{
2046 kfree(bp->grp_info);
2047 bp->grp_info = NULL;
2048}
2049
2050static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2051{
2052 int i;
2053
2054 if (irq_re_init) {
2055 bp->grp_info = kcalloc(bp->cp_nr_rings,
2056 sizeof(struct bnxt_ring_grp_info),
2057 GFP_KERNEL);
2058 if (!bp->grp_info)
2059 return -ENOMEM;
2060 }
2061 for (i = 0; i < bp->cp_nr_rings; i++) {
2062 if (irq_re_init)
2063 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2064 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2065 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2066 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2067 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2068 }
2069 return 0;
2070}
2071
2072static void bnxt_free_vnics(struct bnxt *bp)
2073{
2074 kfree(bp->vnic_info);
2075 bp->vnic_info = NULL;
2076 bp->nr_vnics = 0;
2077}
2078
2079static int bnxt_alloc_vnics(struct bnxt *bp)
2080{
2081 int num_vnics = 1;
2082
2083#ifdef CONFIG_RFS_ACCEL
2084 if (bp->flags & BNXT_FLAG_RFS)
2085 num_vnics += bp->rx_nr_rings;
2086#endif
2087
2088 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2089 GFP_KERNEL);
2090 if (!bp->vnic_info)
2091 return -ENOMEM;
2092
2093 bp->nr_vnics = num_vnics;
2094 return 0;
2095}
2096
2097static void bnxt_init_vnics(struct bnxt *bp)
2098{
2099 int i;
2100
2101 for (i = 0; i < bp->nr_vnics; i++) {
2102 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2103
2104 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2105 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2106 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2107
2108 if (bp->vnic_info[i].rss_hash_key) {
2109 if (i == 0)
2110 prandom_bytes(vnic->rss_hash_key,
2111 HW_HASH_KEY_SIZE);
2112 else
2113 memcpy(vnic->rss_hash_key,
2114 bp->vnic_info[0].rss_hash_key,
2115 HW_HASH_KEY_SIZE);
2116 }
2117 }
2118}
2119
2120static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2121{
2122 int pages;
2123
2124 pages = ring_size / desc_per_pg;
2125
2126 if (!pages)
2127 return 1;
2128
2129 pages++;
2130
2131 while (pages & (pages - 1))
2132 pages++;
2133
2134 return pages;
2135}
2136
2137static void bnxt_set_tpa_flags(struct bnxt *bp)
2138{
2139 bp->flags &= ~BNXT_FLAG_TPA;
2140 if (bp->dev->features & NETIF_F_LRO)
2141 bp->flags |= BNXT_FLAG_LRO;
2142 if ((bp->dev->features & NETIF_F_GRO) && (bp->pdev->revision > 0))
2143 bp->flags |= BNXT_FLAG_GRO;
2144}
2145
2146/* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2147 * be set on entry.
2148 */
2149void bnxt_set_ring_params(struct bnxt *bp)
2150{
2151 u32 ring_size, rx_size, rx_space;
2152 u32 agg_factor = 0, agg_ring_size = 0;
2153
2154 /* 8 for CRC and VLAN */
2155 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2156
2157 rx_space = rx_size + NET_SKB_PAD +
2158 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2159
2160 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2161 ring_size = bp->rx_ring_size;
2162 bp->rx_agg_ring_size = 0;
2163 bp->rx_agg_nr_pages = 0;
2164
2165 if (bp->flags & BNXT_FLAG_TPA)
2166 agg_factor = 4;
2167
2168 bp->flags &= ~BNXT_FLAG_JUMBO;
2169 if (rx_space > PAGE_SIZE) {
2170 u32 jumbo_factor;
2171
2172 bp->flags |= BNXT_FLAG_JUMBO;
2173 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2174 if (jumbo_factor > agg_factor)
2175 agg_factor = jumbo_factor;
2176 }
2177 agg_ring_size = ring_size * agg_factor;
2178
2179 if (agg_ring_size) {
2180 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2181 RX_DESC_CNT);
2182 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2183 u32 tmp = agg_ring_size;
2184
2185 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2186 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2187 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2188 tmp, agg_ring_size);
2189 }
2190 bp->rx_agg_ring_size = agg_ring_size;
2191 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2192 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2193 rx_space = rx_size + NET_SKB_PAD +
2194 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2195 }
2196
2197 bp->rx_buf_use_size = rx_size;
2198 bp->rx_buf_size = rx_space;
2199
2200 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2201 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2202
2203 ring_size = bp->tx_ring_size;
2204 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2205 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2206
2207 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2208 bp->cp_ring_size = ring_size;
2209
2210 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2211 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2212 bp->cp_nr_pages = MAX_CP_PAGES;
2213 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2214 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2215 ring_size, bp->cp_ring_size);
2216 }
2217 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2218 bp->cp_ring_mask = bp->cp_bit - 1;
2219}
2220
2221static void bnxt_free_vnic_attributes(struct bnxt *bp)
2222{
2223 int i;
2224 struct bnxt_vnic_info *vnic;
2225 struct pci_dev *pdev = bp->pdev;
2226
2227 if (!bp->vnic_info)
2228 return;
2229
2230 for (i = 0; i < bp->nr_vnics; i++) {
2231 vnic = &bp->vnic_info[i];
2232
2233 kfree(vnic->fw_grp_ids);
2234 vnic->fw_grp_ids = NULL;
2235
2236 kfree(vnic->uc_list);
2237 vnic->uc_list = NULL;
2238
2239 if (vnic->mc_list) {
2240 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2241 vnic->mc_list, vnic->mc_list_mapping);
2242 vnic->mc_list = NULL;
2243 }
2244
2245 if (vnic->rss_table) {
2246 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2247 vnic->rss_table,
2248 vnic->rss_table_dma_addr);
2249 vnic->rss_table = NULL;
2250 }
2251
2252 vnic->rss_hash_key = NULL;
2253 vnic->flags = 0;
2254 }
2255}
2256
2257static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2258{
2259 int i, rc = 0, size;
2260 struct bnxt_vnic_info *vnic;
2261 struct pci_dev *pdev = bp->pdev;
2262 int max_rings;
2263
2264 for (i = 0; i < bp->nr_vnics; i++) {
2265 vnic = &bp->vnic_info[i];
2266
2267 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2268 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2269
2270 if (mem_size > 0) {
2271 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2272 if (!vnic->uc_list) {
2273 rc = -ENOMEM;
2274 goto out;
2275 }
2276 }
2277 }
2278
2279 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2280 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2281 vnic->mc_list =
2282 dma_alloc_coherent(&pdev->dev,
2283 vnic->mc_list_size,
2284 &vnic->mc_list_mapping,
2285 GFP_KERNEL);
2286 if (!vnic->mc_list) {
2287 rc = -ENOMEM;
2288 goto out;
2289 }
2290 }
2291
2292 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2293 max_rings = bp->rx_nr_rings;
2294 else
2295 max_rings = 1;
2296
2297 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2298 if (!vnic->fw_grp_ids) {
2299 rc = -ENOMEM;
2300 goto out;
2301 }
2302
2303 /* Allocate rss table and hash key */
2304 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2305 &vnic->rss_table_dma_addr,
2306 GFP_KERNEL);
2307 if (!vnic->rss_table) {
2308 rc = -ENOMEM;
2309 goto out;
2310 }
2311
2312 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2313
2314 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2315 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2316 }
2317 return 0;
2318
2319out:
2320 return rc;
2321}
2322
2323static void bnxt_free_hwrm_resources(struct bnxt *bp)
2324{
2325 struct pci_dev *pdev = bp->pdev;
2326
2327 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2328 bp->hwrm_cmd_resp_dma_addr);
2329
2330 bp->hwrm_cmd_resp_addr = NULL;
2331 if (bp->hwrm_dbg_resp_addr) {
2332 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2333 bp->hwrm_dbg_resp_addr,
2334 bp->hwrm_dbg_resp_dma_addr);
2335
2336 bp->hwrm_dbg_resp_addr = NULL;
2337 }
2338}
2339
2340static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2341{
2342 struct pci_dev *pdev = bp->pdev;
2343
2344 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2345 &bp->hwrm_cmd_resp_dma_addr,
2346 GFP_KERNEL);
2347 if (!bp->hwrm_cmd_resp_addr)
2348 return -ENOMEM;
2349 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2350 HWRM_DBG_REG_BUF_SIZE,
2351 &bp->hwrm_dbg_resp_dma_addr,
2352 GFP_KERNEL);
2353 if (!bp->hwrm_dbg_resp_addr)
2354 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2355
2356 return 0;
2357}
2358
2359static void bnxt_free_stats(struct bnxt *bp)
2360{
2361 u32 size, i;
2362 struct pci_dev *pdev = bp->pdev;
2363
2364 if (!bp->bnapi)
2365 return;
2366
2367 size = sizeof(struct ctx_hw_stats);
2368
2369 for (i = 0; i < bp->cp_nr_rings; i++) {
2370 struct bnxt_napi *bnapi = bp->bnapi[i];
2371 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2372
2373 if (cpr->hw_stats) {
2374 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2375 cpr->hw_stats_map);
2376 cpr->hw_stats = NULL;
2377 }
2378 }
2379}
2380
2381static int bnxt_alloc_stats(struct bnxt *bp)
2382{
2383 u32 size, i;
2384 struct pci_dev *pdev = bp->pdev;
2385
2386 size = sizeof(struct ctx_hw_stats);
2387
2388 for (i = 0; i < bp->cp_nr_rings; i++) {
2389 struct bnxt_napi *bnapi = bp->bnapi[i];
2390 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2391
2392 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2393 &cpr->hw_stats_map,
2394 GFP_KERNEL);
2395 if (!cpr->hw_stats)
2396 return -ENOMEM;
2397
2398 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2399 }
2400 return 0;
2401}
2402
2403static void bnxt_clear_ring_indices(struct bnxt *bp)
2404{
2405 int i;
2406
2407 if (!bp->bnapi)
2408 return;
2409
2410 for (i = 0; i < bp->cp_nr_rings; i++) {
2411 struct bnxt_napi *bnapi = bp->bnapi[i];
2412 struct bnxt_cp_ring_info *cpr;
2413 struct bnxt_rx_ring_info *rxr;
2414 struct bnxt_tx_ring_info *txr;
2415
2416 if (!bnapi)
2417 continue;
2418
2419 cpr = &bnapi->cp_ring;
2420 cpr->cp_raw_cons = 0;
2421
b6ab4b01 2422 txr = bnapi->tx_ring;
3b2b7d9d
MC		 2423 if (txr) {
2424 txr->tx_prod = 0;
2425 txr->tx_cons = 0;
2426 }
c0c050c5 2427
b6ab4b01 2428 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 2429 if (rxr) {
2430 rxr->rx_prod = 0;
2431 rxr->rx_agg_prod = 0;
2432 rxr->rx_sw_agg_prod = 0;
2433 }
c0c050c5
MC		 2434 }
2435}
2436
2437static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2438{
2439#ifdef CONFIG_RFS_ACCEL
2440 int i;
2441
2442 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2443 * safe to delete the hash table.
2444 */
2445 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2446 struct hlist_head *head;
2447 struct hlist_node *tmp;
2448 struct bnxt_ntuple_filter *fltr;
2449
2450 head = &bp->ntp_fltr_hash_tbl[i];
2451 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2452 hlist_del(&fltr->hash);
2453 kfree(fltr);
2454 }
2455 }
2456 if (irq_reinit) {
2457 kfree(bp->ntp_fltr_bmap);
2458 bp->ntp_fltr_bmap = NULL;
2459 }
2460 bp->ntp_fltr_count = 0;
2461#endif
2462}
2463
2464static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2465{
2466#ifdef CONFIG_RFS_ACCEL
2467 int i, rc = 0;
2468
2469 if (!(bp->flags & BNXT_FLAG_RFS))
2470 return 0;
2471
2472 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2473 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2474
2475 bp->ntp_fltr_count = 0;
2476 bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2477 GFP_KERNEL);
2478
2479 if (!bp->ntp_fltr_bmap)
2480 rc = -ENOMEM;
2481
2482 return rc;
2483#else
2484 return 0;
2485#endif
2486}
2487
2488static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2489{
2490 bnxt_free_vnic_attributes(bp);
2491 bnxt_free_tx_rings(bp);
2492 bnxt_free_rx_rings(bp);
2493 bnxt_free_cp_rings(bp);
2494 bnxt_free_ntp_fltrs(bp, irq_re_init);
2495 if (irq_re_init) {
2496 bnxt_free_stats(bp);
2497 bnxt_free_ring_grps(bp);
2498 bnxt_free_vnics(bp);
b6ab4b01
MC		 2499 kfree(bp->tx_ring);
2500 bp->tx_ring = NULL;
2501 kfree(bp->rx_ring);
2502 bp->rx_ring = NULL;
c0c050c5
MC		 2503 kfree(bp->bnapi);
2504 bp->bnapi = NULL;
2505 } else {
2506 bnxt_clear_ring_indices(bp);
2507 }
2508}
2509
2510static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2511{
01657bcd 2512 int i, j, rc, size, arr_size;
c0c050c5
MC		 2513 void *bnapi;
2514
2515 if (irq_re_init) {
2516 /* Allocate bnapi mem pointer array and mem block for
2517 * all queues
2518 */
2519 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2520 bp->cp_nr_rings);
2521 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2522 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2523 if (!bnapi)
2524 return -ENOMEM;
2525
2526 bp->bnapi = bnapi;
2527 bnapi += arr_size;
2528 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2529 bp->bnapi[i] = bnapi;
2530 bp->bnapi[i]->index = i;
2531 bp->bnapi[i]->bp = bp;
2532 }
2533
b6ab4b01
MC		 2534 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2535 sizeof(struct bnxt_rx_ring_info),
2536 GFP_KERNEL);
2537 if (!bp->rx_ring)
2538 return -ENOMEM;
2539
2540 for (i = 0; i < bp->rx_nr_rings; i++) {
2541 bp->rx_ring[i].bnapi = bp->bnapi[i];
2542 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2543 }
2544
2545 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2546 sizeof(struct bnxt_tx_ring_info),
2547 GFP_KERNEL);
2548 if (!bp->tx_ring)
2549 return -ENOMEM;
2550
01657bcd
MC		 2551 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2552 j = 0;
2553 else
2554 j = bp->rx_nr_rings;
2555
2556 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2557 bp->tx_ring[i].bnapi = bp->bnapi[j];
2558 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
b6ab4b01
MC		 2559 }
2560
c0c050c5
MC		 2561 rc = bnxt_alloc_stats(bp);
2562 if (rc)
2563 goto alloc_mem_err;
2564
2565 rc = bnxt_alloc_ntp_fltrs(bp);
2566 if (rc)
2567 goto alloc_mem_err;
2568
2569 rc = bnxt_alloc_vnics(bp);
2570 if (rc)
2571 goto alloc_mem_err;
2572 }
2573
2574 bnxt_init_ring_struct(bp);
2575
2576 rc = bnxt_alloc_rx_rings(bp);
2577 if (rc)
2578 goto alloc_mem_err;
2579
2580 rc = bnxt_alloc_tx_rings(bp);
2581 if (rc)
2582 goto alloc_mem_err;
2583
2584 rc = bnxt_alloc_cp_rings(bp);
2585 if (rc)
2586 goto alloc_mem_err;
2587
2588 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2589 BNXT_VNIC_UCAST_FLAG;
2590 rc = bnxt_alloc_vnic_attributes(bp);
2591 if (rc)
2592 goto alloc_mem_err;
2593 return 0;
2594
2595alloc_mem_err:
2596 bnxt_free_mem(bp, true);
2597 return rc;
2598}
2599
2600void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2601 u16 cmpl_ring, u16 target_id)
2602{
2603 struct hwrm_cmd_req_hdr *req = request;
2604
2605 req->cmpl_ring_req_type =
2606 cpu_to_le32(req_type | (cmpl_ring << HWRM_CMPL_RING_SFT));
2607 req->target_id_seq_id = cpu_to_le32(target_id << HWRM_TARGET_FID_SFT);
2608 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2609}
2610
2611int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2612{
2613 int i, intr_process, rc;
2614 struct hwrm_cmd_req_hdr *req = msg;
2615 u32 *data = msg;
2616 __le32 *resp_len, *valid;
2617 u16 cp_ring_id, len = 0;
2618 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2619
2620 req->target_id_seq_id |= cpu_to_le32(bp->hwrm_cmd_seq++);
2621 memset(resp, 0, PAGE_SIZE);
2622 cp_ring_id = (le32_to_cpu(req->cmpl_ring_req_type) &
2623 HWRM_CMPL_RING_MASK) >>
2624 HWRM_CMPL_RING_SFT;
2625 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2626
2627 /* Write request msg to hwrm channel */
2628 __iowrite32_copy(bp->bar0, data, msg_len / 4);
2629
d79979a1
MC		 2630 for (i = msg_len; i < HWRM_MAX_REQ_LEN; i += 4)
2631 writel(0, bp->bar0 + i);
2632
c0c050c5
MC		 2633 /* currently supports only one outstanding message */
2634 if (intr_process)
2635 bp->hwrm_intr_seq_id = le32_to_cpu(req->target_id_seq_id) &
2636 HWRM_SEQ_ID_MASK;
2637
2638 /* Ring channel doorbell */
2639 writel(1, bp->bar0 + 0x100);
2640
2641 i = 0;
2642 if (intr_process) {
2643 /* Wait until hwrm response cmpl interrupt is processed */
2644 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
2645 i++ < timeout) {
2646 usleep_range(600, 800);
2647 }
2648
2649 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2650 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
2651 req->cmpl_ring_req_type);
2652 return -1;
2653 }
2654 } else {
2655 /* Check if response len is updated */
2656 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
2657 for (i = 0; i < timeout; i++) {
2658 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2659 HWRM_RESP_LEN_SFT;
2660 if (len)
2661 break;
2662 usleep_range(600, 800);
2663 }
2664
2665 if (i >= timeout) {
2666 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2667 timeout, req->cmpl_ring_req_type,
2668 req->target_id_seq_id, *resp_len);
2669 return -1;
2670 }
2671
2672 /* Last word of resp contains valid bit */
2673 valid = bp->hwrm_cmd_resp_addr + len - 4;
2674 for (i = 0; i < timeout; i++) {
2675 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2676 break;
2677 usleep_range(600, 800);
2678 }
2679
2680 if (i >= timeout) {
2681 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2682 timeout, req->cmpl_ring_req_type,
2683 req->target_id_seq_id, len, *valid);
2684 return -1;
2685 }
2686 }
2687
2688 rc = le16_to_cpu(resp->error_code);
2689 if (rc) {
2690 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2691 le16_to_cpu(resp->req_type),
2692 le16_to_cpu(resp->seq_id), rc);
2693 return rc;
2694 }
2695 return 0;
2696}
2697
2698int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2699{
2700 int rc;
2701
2702 mutex_lock(&bp->hwrm_cmd_lock);
2703 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2704 mutex_unlock(&bp->hwrm_cmd_lock);
2705 return rc;
2706}
2707
2708static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
2709{
2710 struct hwrm_func_drv_rgtr_input req = {0};
2711 int i;
2712
2713 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
2714
2715 req.enables =
2716 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
2717 FUNC_DRV_RGTR_REQ_ENABLES_VER |
2718 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
2719
2720 /* TODO: current async event fwd bits are not defined and the firmware
2721 * only checks if it is non-zero to enable async event forwarding
2722 */
2723 req.async_event_fwd[0] |= cpu_to_le32(1);
2724 req.os_type = cpu_to_le16(1);
2725 req.ver_maj = DRV_VER_MAJ;
2726 req.ver_min = DRV_VER_MIN;
2727 req.ver_upd = DRV_VER_UPD;
2728
2729 if (BNXT_PF(bp)) {
de68f5de 2730 DECLARE_BITMAP(vf_req_snif_bmap, 256);
c0c050c5
MC		 2731 u32 *data = (u32 *)vf_req_snif_bmap;
2732
de68f5de 2733 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
c0c050c5
MC		 2734 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
2735 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
2736
de68f5de
MC		 2737 for (i = 0; i < 8; i++)
2738 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
2739
c0c050c5
MC		 2740 req.enables |=
2741 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
2742 }
2743
2744 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2745}
2746
be58a0da
JH		 2747static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
2748{
2749 struct hwrm_func_drv_unrgtr_input req = {0};
2750
2751 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
2752 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2753}
2754
c0c050c5
MC		 2755static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
2756{
2757 u32 rc = 0;
2758 struct hwrm_tunnel_dst_port_free_input req = {0};
2759
2760 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
2761 req.tunnel_type = tunnel_type;
2762
2763 switch (tunnel_type) {
2764 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
2765 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
2766 break;
2767 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
2768 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
2769 break;
2770 default:
2771 break;
2772 }
2773
2774 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2775 if (rc)
2776 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2777 rc);
2778 return rc;
2779}
2780
2781static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
2782 u8 tunnel_type)
2783{
2784 u32 rc = 0;
2785 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2786 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2787
2788 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
2789
2790 req.tunnel_type = tunnel_type;
2791 req.tunnel_dst_port_val = port;
2792
2793 mutex_lock(&bp->hwrm_cmd_lock);
2794 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2795 if (rc) {
2796 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2797 rc);
2798 goto err_out;
2799 }
2800
2801 if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
2802 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2803
2804 else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
2805 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
2806err_out:
2807 mutex_unlock(&bp->hwrm_cmd_lock);
2808 return rc;
2809}
2810
2811static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
2812{
2813 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
2814 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2815
2816 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
c193554e 2817 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
c0c050c5
MC		 2818
2819 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
2820 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
2821 req.mask = cpu_to_le32(vnic->rx_mask);
2822 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2823}
2824
2825#ifdef CONFIG_RFS_ACCEL
2826static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2827 struct bnxt_ntuple_filter *fltr)
2828{
2829 struct hwrm_cfa_ntuple_filter_free_input req = {0};
2830
2831 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
2832 req.ntuple_filter_id = fltr->filter_id;
2833 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2834}
2835
2836#define BNXT_NTP_FLTR_FLAGS \
2837 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
2838 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
2839 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
2840 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
2841 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
2842 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
2843 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
2844 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
2845 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
2846 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
2847 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
2848 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
2849 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
c193554e 2850 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
c0c050c5
MC		 2851
2852static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2853 struct bnxt_ntuple_filter *fltr)
2854{
2855 int rc = 0;
2856 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
2857 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
2858 bp->hwrm_cmd_resp_addr;
2859 struct flow_keys *keys = &fltr->fkeys;
2860 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
2861
2862 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
2863 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
2864
2865 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
2866
2867 req.ethertype = htons(ETH_P_IP);
2868 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
c193554e 2869 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
c0c050c5
MC		 2870 req.ip_protocol = keys->basic.ip_proto;
2871
2872 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
2873 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2874 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
2875 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2876
2877 req.src_port = keys->ports.src;
2878 req.src_port_mask = cpu_to_be16(0xffff);
2879 req.dst_port = keys->ports.dst;
2880 req.dst_port_mask = cpu_to_be16(0xffff);
2881
c193554e 2882 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
c0c050c5
MC		 2883 mutex_lock(&bp->hwrm_cmd_lock);
2884 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2885 if (!rc)
2886 fltr->filter_id = resp->ntuple_filter_id;
2887 mutex_unlock(&bp->hwrm_cmd_lock);
2888 return rc;
2889}
2890#endif
2891
2892static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
2893 u8 *mac_addr)
2894{
2895 u32 rc = 0;
2896 struct hwrm_cfa_l2_filter_alloc_input req = {0};
2897 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2898
2899 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
2900 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
2901 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
c193554e 2902 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
c0c050c5
MC		 2903 req.enables =
2904 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
c193554e 2905 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
c0c050c5
MC		 2906 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
2907 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
2908 req.l2_addr_mask[0] = 0xff;
2909 req.l2_addr_mask[1] = 0xff;
2910 req.l2_addr_mask[2] = 0xff;
2911 req.l2_addr_mask[3] = 0xff;
2912 req.l2_addr_mask[4] = 0xff;
2913 req.l2_addr_mask[5] = 0xff;
2914
2915 mutex_lock(&bp->hwrm_cmd_lock);
2916 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2917 if (!rc)
2918 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
2919 resp->l2_filter_id;
2920 mutex_unlock(&bp->hwrm_cmd_lock);
2921 return rc;
2922}
2923
2924static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
2925{
2926 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
2927 int rc = 0;
2928
2929 /* Any associated ntuple filters will also be cleared by firmware. */
2930 mutex_lock(&bp->hwrm_cmd_lock);
2931 for (i = 0; i < num_of_vnics; i++) {
2932 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2933
2934 for (j = 0; j < vnic->uc_filter_count; j++) {
2935 struct hwrm_cfa_l2_filter_free_input req = {0};
2936
2937 bnxt_hwrm_cmd_hdr_init(bp, &req,
2938 HWRM_CFA_L2_FILTER_FREE, -1, -1);
2939
2940 req.l2_filter_id = vnic->fw_l2_filter_id[j];
2941
2942 rc = _hwrm_send_message(bp, &req, sizeof(req),
2943 HWRM_CMD_TIMEOUT);
2944 }
2945 vnic->uc_filter_count = 0;
2946 }
2947 mutex_unlock(&bp->hwrm_cmd_lock);
2948
2949 return rc;
2950}
2951
2952static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
2953{
2954 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2955 struct hwrm_vnic_tpa_cfg_input req = {0};
2956
2957 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
2958
2959 if (tpa_flags) {
2960 u16 mss = bp->dev->mtu - 40;
2961 u32 nsegs, n, segs = 0, flags;
2962
2963 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
2964 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
2965 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
2966 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
2967 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
2968 if (tpa_flags & BNXT_FLAG_GRO)
2969 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
2970
2971 req.flags = cpu_to_le32(flags);
2972
2973 req.enables =
2974 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
c193554e
MC		 2975 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
2976 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
c0c050c5
MC		 2977
2978 /* Number of segs are log2 units, and first packet is not
2979 * included as part of this units.
2980 */
2981 if (mss <= PAGE_SIZE) {
2982 n = PAGE_SIZE / mss;
2983 nsegs = (MAX_SKB_FRAGS - 1) * n;
2984 } else {
2985 n = mss / PAGE_SIZE;
2986 if (mss & (PAGE_SIZE - 1))
2987 n++;
2988 nsegs = (MAX_SKB_FRAGS - n) / n;
2989 }
2990
2991 segs = ilog2(nsegs);
2992 req.max_agg_segs = cpu_to_le16(segs);
2993 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
c193554e
MC		 2994
2995 req.min_agg_len = cpu_to_le32(512);
c0c050c5
MC		 2996 }
2997 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
2998
2999 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3000}
3001
3002static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3003{
3004 u32 i, j, max_rings;
3005 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3006 struct hwrm_vnic_rss_cfg_input req = {0};
3007
3008 if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
3009 return 0;
3010
3011 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3012 if (set_rss) {
3013 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
3014 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
3015 BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
3016 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
3017
3018 req.hash_type = cpu_to_le32(vnic->hash_type);
3019
3020 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3021 max_rings = bp->rx_nr_rings;
3022 else
3023 max_rings = 1;
3024
3025 /* Fill the RSS indirection table with ring group ids */
3026 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3027 if (j == max_rings)
3028 j = 0;
3029 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3030 }
3031
3032 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3033 req.hash_key_tbl_addr =
3034 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3035 }
3036 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3037 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3038}
3039
3040static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3041{
3042 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3043 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3044
3045 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3046 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3047 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3048 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3049 req.enables =
3050 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3051 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3052 /* thresholds not implemented in firmware yet */
3053 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3054 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3055 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3056 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3057}
3058
3059static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3060{
3061 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3062
3063 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3064 req.rss_cos_lb_ctx_id =
3065 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3066
3067 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3068 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3069}
3070
3071static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3072{
3073 int i;
3074
3075 for (i = 0; i < bp->nr_vnics; i++) {
3076 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3077
3078 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3079 bnxt_hwrm_vnic_ctx_free_one(bp, i);
3080 }
3081 bp->rsscos_nr_ctxs = 0;
3082}
3083
3084static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3085{
3086 int rc;
3087 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3088 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3089 bp->hwrm_cmd_resp_addr;
3090
3091 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3092 -1);
3093
3094 mutex_lock(&bp->hwrm_cmd_lock);
3095 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3096 if (!rc)
3097 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3098 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3099 mutex_unlock(&bp->hwrm_cmd_lock);
3100
3101 return rc;
3102}
3103
3104static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3105{
b81a90d3 3106 unsigned int ring = 0, grp_idx;
c0c050c5
MC		 3107 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3108 struct hwrm_vnic_cfg_input req = {0};
3109
3110 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3111 /* Only RSS support for now TBD: COS & LB */
3112 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
3113 VNIC_CFG_REQ_ENABLES_RSS_RULE);
3114 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3115 req.cos_rule = cpu_to_le16(0xffff);
3116 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
b81a90d3 3117 ring = 0;
c0c050c5 3118 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
b81a90d3 3119 ring = vnic_id - 1;
c0c050c5 3120
b81a90d3 3121 grp_idx = bp->rx_ring[ring].bnapi->index;
c0c050c5
MC		 3122 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3123 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3124
3125 req.lb_rule = cpu_to_le16(0xffff);
3126 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3127 VLAN_HLEN);
3128
3129 if (bp->flags & BNXT_FLAG_STRIP_VLAN)
3130 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3131
3132 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3133}
3134
3135static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3136{
3137 u32 rc = 0;
3138
3139 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3140 struct hwrm_vnic_free_input req = {0};
3141
3142 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3143 req.vnic_id =
3144 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3145
3146 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3147 if (rc)
3148 return rc;
3149 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3150 }
3151 return rc;
3152}
3153
3154static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3155{
3156 u16 i;
3157
3158 for (i = 0; i < bp->nr_vnics; i++)
3159 bnxt_hwrm_vnic_free_one(bp, i);
3160}
3161
b81a90d3
MC		 3162static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3163 unsigned int start_rx_ring_idx,
3164 unsigned int nr_rings)
c0c050c5 3165{
b81a90d3
MC		 3166 int rc = 0;
3167 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
c0c050c5
MC		 3168 struct hwrm_vnic_alloc_input req = {0};
3169 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3170
3171 /* map ring groups to this vnic */
b81a90d3
MC		 3172 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3173 grp_idx = bp->rx_ring[i].bnapi->index;
3174 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
c0c050c5 3175 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
b81a90d3 3176 j, nr_rings);
c0c050c5
MC		 3177 break;
3178 }
3179 bp->vnic_info[vnic_id].fw_grp_ids[j] =
b81a90d3 3180 bp->grp_info[grp_idx].fw_grp_id;
c0c050c5
MC		 3181 }
3182
3183 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3184 if (vnic_id == 0)
3185 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3186
3187 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3188
3189 mutex_lock(&bp->hwrm_cmd_lock);
3190 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3191 if (!rc)
3192 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3193 mutex_unlock(&bp->hwrm_cmd_lock);
3194 return rc;
3195}
3196
3197static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3198{
3199 u16 i;
3200 u32 rc = 0;
3201
3202 mutex_lock(&bp->hwrm_cmd_lock);
3203 for (i = 0; i < bp->rx_nr_rings; i++) {
3204 struct hwrm_ring_grp_alloc_input req = {0};
3205 struct hwrm_ring_grp_alloc_output *resp =
3206 bp->hwrm_cmd_resp_addr;
b81a90d3 3207 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
c0c050c5
MC		 3208
3209 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3210
b81a90d3
MC		 3211 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3212 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3213 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3214 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
c0c050c5
MC		 3215
3216 rc = _hwrm_send_message(bp, &req, sizeof(req),
3217 HWRM_CMD_TIMEOUT);
3218 if (rc)
3219 break;
3220
b81a90d3
MC		 3221 bp->grp_info[grp_idx].fw_grp_id =
3222 le32_to_cpu(resp->ring_group_id);
c0c050c5
MC		 3223 }
3224 mutex_unlock(&bp->hwrm_cmd_lock);
3225 return rc;
3226}
3227
3228static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3229{
3230 u16 i;
3231 u32 rc = 0;
3232 struct hwrm_ring_grp_free_input req = {0};
3233
3234 if (!bp->grp_info)
3235 return 0;
3236
3237 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3238
3239 mutex_lock(&bp->hwrm_cmd_lock);
3240 for (i = 0; i < bp->cp_nr_rings; i++) {
3241 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3242 continue;
3243 req.ring_group_id =
3244 cpu_to_le32(bp->grp_info[i].fw_grp_id);
3245
3246 rc = _hwrm_send_message(bp, &req, sizeof(req),
3247 HWRM_CMD_TIMEOUT);
3248 if (rc)
3249 break;
3250 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3251 }
3252 mutex_unlock(&bp->hwrm_cmd_lock);
3253 return rc;
3254}
3255
3256static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3257 struct bnxt_ring_struct *ring,
3258 u32 ring_type, u32 map_index,
3259 u32 stats_ctx_id)
3260{
3261 int rc = 0, err = 0;
3262 struct hwrm_ring_alloc_input req = {0};
3263 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3264 u16 ring_id;
3265
3266 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3267
3268 req.enables = 0;
3269 if (ring->nr_pages > 1) {
3270 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3271 /* Page size is in log2 units */
3272 req.page_size = BNXT_PAGE_SHIFT;
3273 req.page_tbl_depth = 1;
3274 } else {
3275 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
3276 }
3277 req.fbo = 0;
3278 /* Association of ring index with doorbell index and MSIX number */
3279 req.logical_id = cpu_to_le16(map_index);
3280
3281 switch (ring_type) {
3282 case HWRM_RING_ALLOC_TX:
3283 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3284 /* Association of transmit ring with completion ring */
3285 req.cmpl_ring_id =
3286 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3287 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3288 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3289 req.queue_id = cpu_to_le16(ring->queue_id);
3290 break;
3291 case HWRM_RING_ALLOC_RX:
3292 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3293 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3294 break;
3295 case HWRM_RING_ALLOC_AGG:
3296 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3297 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3298 break;
3299 case HWRM_RING_ALLOC_CMPL:
3300 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3301 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3302 if (bp->flags & BNXT_FLAG_USING_MSIX)
3303 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3304 break;
3305 default:
3306 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3307 ring_type);
3308 return -1;
3309 }
3310
3311 mutex_lock(&bp->hwrm_cmd_lock);
3312 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3313 err = le16_to_cpu(resp->error_code);
3314 ring_id = le16_to_cpu(resp->ring_id);
3315 mutex_unlock(&bp->hwrm_cmd_lock);
3316
3317 if (rc || err) {
3318 switch (ring_type) {
3319 case RING_FREE_REQ_RING_TYPE_CMPL:
3320 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3321 rc, err);
3322 return -1;
3323
3324 case RING_FREE_REQ_RING_TYPE_RX:
3325 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3326 rc, err);
3327 return -1;
3328
3329 case RING_FREE_REQ_RING_TYPE_TX:
3330 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3331 rc, err);
3332 return -1;
3333
3334 default:
3335 netdev_err(bp->dev, "Invalid ring\n");
3336 return -1;
3337 }
3338 }
3339 ring->fw_ring_id = ring_id;
3340 return rc;
3341}
3342
3343static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3344{
3345 int i, rc = 0;
3346
edd0c2cc
MC		 3347 for (i = 0; i < bp->cp_nr_rings; i++) {
3348 struct bnxt_napi *bnapi = bp->bnapi[i];
3349 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3350 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
c0c050c5 3351
edd0c2cc
MC		 3352 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3353 INVALID_STATS_CTX_ID);
3354 if (rc)
3355 goto err_out;
3356 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3357 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3358 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3359 }
3360
edd0c2cc 3361 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 3362 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 3363 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 3364 u32 map_idx = txr->bnapi->index;
3365 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
c0c050c5 3366
b81a90d3
MC		 3367 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3368 map_idx, fw_stats_ctx);
edd0c2cc
MC		 3369 if (rc)
3370 goto err_out;
b81a90d3 3371 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 3372 }
3373
edd0c2cc 3374 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3375 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 3376 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3 3377 u32 map_idx = rxr->bnapi->index;
c0c050c5 3378
b81a90d3
MC		 3379 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3380 map_idx, INVALID_STATS_CTX_ID);
edd0c2cc
MC		 3381 if (rc)
3382 goto err_out;
b81a90d3 3383 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
edd0c2cc 3384 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
b81a90d3 3385 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3386 }
3387
3388 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3389 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3390 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 3391 struct bnxt_ring_struct *ring =
3392 &rxr->rx_agg_ring_struct;
b81a90d3
MC		 3393 u32 grp_idx = rxr->bnapi->index;
3394 u32 map_idx = grp_idx + bp->rx_nr_rings;
c0c050c5
MC		 3395
3396 rc = hwrm_ring_alloc_send_msg(bp, ring,
3397 HWRM_RING_ALLOC_AGG,
b81a90d3 3398 map_idx,
c0c050c5
MC		 3399 INVALID_STATS_CTX_ID);
3400 if (rc)
3401 goto err_out;
3402
b81a90d3 3403 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 3404 writel(DB_KEY_RX | rxr->rx_agg_prod,
3405 rxr->rx_agg_doorbell);
b81a90d3 3406 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3407 }
3408 }
3409err_out:
3410 return rc;
3411}
3412
3413static int hwrm_ring_free_send_msg(struct bnxt *bp,
3414 struct bnxt_ring_struct *ring,
3415 u32 ring_type, int cmpl_ring_id)
3416{
3417 int rc;
3418 struct hwrm_ring_free_input req = {0};
3419 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3420 u16 error_code;
3421
74608fc9 3422 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
c0c050c5
MC		 3423 req.ring_type = ring_type;
3424 req.ring_id = cpu_to_le16(ring->fw_ring_id);
3425
3426 mutex_lock(&bp->hwrm_cmd_lock);
3427 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3428 error_code = le16_to_cpu(resp->error_code);
3429 mutex_unlock(&bp->hwrm_cmd_lock);
3430
3431 if (rc || error_code) {
3432 switch (ring_type) {
3433 case RING_FREE_REQ_RING_TYPE_CMPL:
3434 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3435 rc);
3436 return rc;
3437 case RING_FREE_REQ_RING_TYPE_RX:
3438 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3439 rc);
3440 return rc;
3441 case RING_FREE_REQ_RING_TYPE_TX:
3442 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3443 rc);
3444 return rc;
3445 default:
3446 netdev_err(bp->dev, "Invalid ring\n");
3447 return -1;
3448 }
3449 }
3450 return 0;
3451}
3452
edd0c2cc 3453static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
c0c050c5 3454{
edd0c2cc 3455 int i;
c0c050c5
MC		 3456
3457 if (!bp->bnapi)
edd0c2cc 3458 return;
c0c050c5 3459
edd0c2cc 3460 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 3461 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 3462 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 3463 u32 grp_idx = txr->bnapi->index;
3464 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 3465
3466 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3467 hwrm_ring_free_send_msg(bp, ring,
3468 RING_FREE_REQ_RING_TYPE_TX,
3469 close_path ? cmpl_ring_id :
3470 INVALID_HW_RING_ID);
3471 ring->fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 3472 }
3473 }
3474
edd0c2cc 3475 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3476 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 3477 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3
MC		 3478 u32 grp_idx = rxr->bnapi->index;
3479 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 3480
3481 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3482 hwrm_ring_free_send_msg(bp, ring,
3483 RING_FREE_REQ_RING_TYPE_RX,
3484 close_path ? cmpl_ring_id :
3485 INVALID_HW_RING_ID);
3486 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 3487 bp->grp_info[grp_idx].rx_fw_ring_id =
3488 INVALID_HW_RING_ID;
c0c050c5
MC		 3489 }
3490 }
3491
edd0c2cc 3492 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3493 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 3494 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
b81a90d3
MC		 3495 u32 grp_idx = rxr->bnapi->index;
3496 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 3497
3498 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3499 hwrm_ring_free_send_msg(bp, ring,
3500 RING_FREE_REQ_RING_TYPE_RX,
3501 close_path ? cmpl_ring_id :
3502 INVALID_HW_RING_ID);
3503 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 3504 bp->grp_info[grp_idx].agg_fw_ring_id =
3505 INVALID_HW_RING_ID;
c0c050c5
MC		 3506 }
3507 }
3508
edd0c2cc
MC		 3509 for (i = 0; i < bp->cp_nr_rings; i++) {
3510 struct bnxt_napi *bnapi = bp->bnapi[i];
3511 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3512 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3513
3514 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3515 hwrm_ring_free_send_msg(bp, ring,
3516 RING_FREE_REQ_RING_TYPE_CMPL,
3517 INVALID_HW_RING_ID);
3518 ring->fw_ring_id = INVALID_HW_RING_ID;
3519 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 3520 }
3521 }
c0c050c5
MC		 3522}
3523
3524int bnxt_hwrm_set_coal(struct bnxt *bp)
3525{
3526 int i, rc = 0;
3527 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
3528 u16 max_buf, max_buf_irq;
3529 u16 buf_tmr, buf_tmr_irq;
3530 u32 flags;
3531
3532 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
3533 -1, -1);
3534
3535 /* Each rx completion (2 records) should be DMAed immediately */
3536 max_buf = min_t(u16, bp->coal_bufs / 4, 2);
3537 /* max_buf must not be zero */
3538 max_buf = clamp_t(u16, max_buf, 1, 63);
3539 max_buf_irq = clamp_t(u16, bp->coal_bufs_irq, 1, 63);
3540 buf_tmr = max_t(u16, bp->coal_ticks / 4, 1);
3541 buf_tmr_irq = max_t(u16, bp->coal_ticks_irq, 1);
3542
3543 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3544
3545 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3546 * if coal_ticks is less than 25 us.
3547 */
3548 if (BNXT_COAL_TIMER_TO_USEC(bp->coal_ticks) < 25)
3549 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3550
3551 req.flags = cpu_to_le16(flags);
3552 req.num_cmpl_dma_aggr = cpu_to_le16(max_buf);
3553 req.num_cmpl_dma_aggr_during_int = cpu_to_le16(max_buf_irq);
3554 req.cmpl_aggr_dma_tmr = cpu_to_le16(buf_tmr);
3555 req.cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmr_irq);
3556 req.int_lat_tmr_min = cpu_to_le16(buf_tmr);
3557 req.int_lat_tmr_max = cpu_to_le16(bp->coal_ticks);
3558 req.num_cmpl_aggr_int = cpu_to_le16(bp->coal_bufs);
3559
3560 mutex_lock(&bp->hwrm_cmd_lock);
3561 for (i = 0; i < bp->cp_nr_rings; i++) {
3562 req.ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3563
3564 rc = _hwrm_send_message(bp, &req, sizeof(req),
3565 HWRM_CMD_TIMEOUT);
3566 if (rc)
3567 break;
3568 }
3569 mutex_unlock(&bp->hwrm_cmd_lock);
3570 return rc;
3571}
3572
3573static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3574{
3575 int rc = 0, i;
3576 struct hwrm_stat_ctx_free_input req = {0};
3577
3578 if (!bp->bnapi)
3579 return 0;
3580
3581 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3582
3583 mutex_lock(&bp->hwrm_cmd_lock);
3584 for (i = 0; i < bp->cp_nr_rings; i++) {
3585 struct bnxt_napi *bnapi = bp->bnapi[i];
3586 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3587
3588 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3589 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3590
3591 rc = _hwrm_send_message(bp, &req, sizeof(req),
3592 HWRM_CMD_TIMEOUT);
3593 if (rc)
3594 break;
3595
3596 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3597 }
3598 }
3599 mutex_unlock(&bp->hwrm_cmd_lock);
3600 return rc;
3601}
3602
3603static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3604{
3605 int rc = 0, i;
3606 struct hwrm_stat_ctx_alloc_input req = {0};
3607 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3608
3609 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3610
3611 req.update_period_ms = cpu_to_le32(1000);
3612
3613 mutex_lock(&bp->hwrm_cmd_lock);
3614 for (i = 0; i < bp->cp_nr_rings; i++) {
3615 struct bnxt_napi *bnapi = bp->bnapi[i];
3616 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3617
3618 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3619
3620 rc = _hwrm_send_message(bp, &req, sizeof(req),
3621 HWRM_CMD_TIMEOUT);
3622 if (rc)
3623 break;
3624
3625 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3626
3627 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3628 }
3629 mutex_unlock(&bp->hwrm_cmd_lock);
3630 return 0;
3631}
3632
4a21b49b 3633int bnxt_hwrm_func_qcaps(struct bnxt *bp)
c0c050c5
MC		 3634{
3635 int rc = 0;
3636 struct hwrm_func_qcaps_input req = {0};
3637 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3638
3639 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
3640 req.fid = cpu_to_le16(0xffff);
3641
3642 mutex_lock(&bp->hwrm_cmd_lock);
3643 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3644 if (rc)
3645 goto hwrm_func_qcaps_exit;
3646
3647 if (BNXT_PF(bp)) {
3648 struct bnxt_pf_info *pf = &bp->pf;
3649
3650 pf->fw_fid = le16_to_cpu(resp->fid);
3651 pf->port_id = le16_to_cpu(resp->port_id);
3652 memcpy(pf->mac_addr, resp->perm_mac_address, ETH_ALEN);
bdd4347b 3653 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
c0c050c5
MC		 3654 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3655 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3656 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
c0c050c5 3657 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 3658 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3659 if (!pf->max_hw_ring_grps)
3660 pf->max_hw_ring_grps = pf->max_tx_rings;
c0c050c5
MC		 3661 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3662 pf->max_vnics = le16_to_cpu(resp->max_vnics);
3663 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3664 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
3665 pf->max_vfs = le16_to_cpu(resp->max_vfs);
3666 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
3667 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
3668 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
3669 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
3670 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
3671 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
3672 } else {
379a80a1 3673#ifdef CONFIG_BNXT_SRIOV
c0c050c5
MC		 3674 struct bnxt_vf_info *vf = &bp->vf;
3675
3676 vf->fw_fid = le16_to_cpu(resp->fid);
3677 memcpy(vf->mac_addr, resp->perm_mac_address, ETH_ALEN);
bdd4347b
JH		 3678 if (is_valid_ether_addr(vf->mac_addr))
3679 /* overwrite netdev dev_adr with admin VF MAC */
3680 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
3681 else
3682 random_ether_addr(bp->dev->dev_addr);
c0c050c5
MC		 3683
3684 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3685 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3686 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3687 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 3688 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3689 if (!vf->max_hw_ring_grps)
3690 vf->max_hw_ring_grps = vf->max_tx_rings;
c0c050c5
MC		 3691 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3692 vf->max_vnics = le16_to_cpu(resp->max_vnics);
3693 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
379a80a1 3694#endif
c0c050c5
MC		 3695 }
3696
3697 bp->tx_push_thresh = 0;
3698 if (resp->flags &
3699 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
3700 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
3701
3702hwrm_func_qcaps_exit:
3703 mutex_unlock(&bp->hwrm_cmd_lock);
3704 return rc;
3705}
3706
3707static int bnxt_hwrm_func_reset(struct bnxt *bp)
3708{
3709 struct hwrm_func_reset_input req = {0};
3710
3711 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
3712 req.enables = 0;
3713
3714 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
3715}
3716
3717static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
3718{
3719 int rc = 0;
3720 struct hwrm_queue_qportcfg_input req = {0};
3721 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
3722 u8 i, *qptr;
3723
3724 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
3725
3726 mutex_lock(&bp->hwrm_cmd_lock);
3727 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3728 if (rc)
3729 goto qportcfg_exit;
3730
3731 if (!resp->max_configurable_queues) {
3732 rc = -EINVAL;
3733 goto qportcfg_exit;
3734 }
3735 bp->max_tc = resp->max_configurable_queues;
3736 if (bp->max_tc > BNXT_MAX_QUEUE)
3737 bp->max_tc = BNXT_MAX_QUEUE;
3738
3739 qptr = &resp->queue_id0;
3740 for (i = 0; i < bp->max_tc; i++) {
3741 bp->q_info[i].queue_id = *qptr++;
3742 bp->q_info[i].queue_profile = *qptr++;
3743 }
3744
3745qportcfg_exit:
3746 mutex_unlock(&bp->hwrm_cmd_lock);
3747 return rc;
3748}
3749
3750static int bnxt_hwrm_ver_get(struct bnxt *bp)
3751{
3752 int rc;
3753 struct hwrm_ver_get_input req = {0};
3754 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
3755
3756 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
3757 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
3758 req.hwrm_intf_min = HWRM_VERSION_MINOR;
3759 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
3760 mutex_lock(&bp->hwrm_cmd_lock);
3761 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3762 if (rc)
3763 goto hwrm_ver_get_exit;
3764
3765 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
3766
c193554e
MC		 3767 if (resp->hwrm_intf_maj < 1) {
3768 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
c0c050c5 3769 resp->hwrm_intf_maj, resp->hwrm_intf_min,
c193554e
MC		 3770 resp->hwrm_intf_upd);
3771 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
c0c050c5
MC		 3772 }
3773 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "bc %d.%d.%d rm %d.%d.%d",
3774 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
3775 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
3776
3777hwrm_ver_get_exit:
3778 mutex_unlock(&bp->hwrm_cmd_lock);
3779 return rc;
3780}
3781
3782static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
3783{
3784 if (bp->vxlan_port_cnt) {
3785 bnxt_hwrm_tunnel_dst_port_free(
3786 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
3787 }
3788 bp->vxlan_port_cnt = 0;
3789 if (bp->nge_port_cnt) {
3790 bnxt_hwrm_tunnel_dst_port_free(
3791 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
3792 }
3793 bp->nge_port_cnt = 0;
3794}
3795
3796static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
3797{
3798 int rc, i;
3799 u32 tpa_flags = 0;
3800
3801 if (set_tpa)
3802 tpa_flags = bp->flags & BNXT_FLAG_TPA;
3803 for (i = 0; i < bp->nr_vnics; i++) {
3804 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
3805 if (rc) {
3806 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3807 rc, i);
3808 return rc;
3809 }
3810 }
3811 return 0;
3812}
3813
3814static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
3815{
3816 int i;
3817
3818 for (i = 0; i < bp->nr_vnics; i++)
3819 bnxt_hwrm_vnic_set_rss(bp, i, false);
3820}
3821
3822static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
3823 bool irq_re_init)
3824{
3825 if (bp->vnic_info) {
3826 bnxt_hwrm_clear_vnic_filter(bp);
3827 /* clear all RSS setting before free vnic ctx */
3828 bnxt_hwrm_clear_vnic_rss(bp);
3829 bnxt_hwrm_vnic_ctx_free(bp);
3830 /* before free the vnic, undo the vnic tpa settings */
3831 if (bp->flags & BNXT_FLAG_TPA)
3832 bnxt_set_tpa(bp, false);
3833 bnxt_hwrm_vnic_free(bp);
3834 }
3835 bnxt_hwrm_ring_free(bp, close_path);
3836 bnxt_hwrm_ring_grp_free(bp);
3837 if (irq_re_init) {
3838 bnxt_hwrm_stat_ctx_free(bp);
3839 bnxt_hwrm_free_tunnel_ports(bp);
3840 }
3841}
3842
3843static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
3844{
3845 int rc;
3846
3847 /* allocate context for vnic */
3848 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
3849 if (rc) {
3850 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3851 vnic_id, rc);
3852 goto vnic_setup_err;
3853 }
3854 bp->rsscos_nr_ctxs++;
3855
3856 /* configure default vnic, ring grp */
3857 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
3858 if (rc) {
3859 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
3860 vnic_id, rc);
3861 goto vnic_setup_err;
3862 }
3863
3864 /* Enable RSS hashing on vnic */
3865 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
3866 if (rc) {
3867 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
3868 vnic_id, rc);
3869 goto vnic_setup_err;
3870 }
3871
3872 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3873 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
3874 if (rc) {
3875 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
3876 vnic_id, rc);
3877 }
3878 }
3879
3880vnic_setup_err:
3881 return rc;
3882}
3883
3884static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
3885{
3886#ifdef CONFIG_RFS_ACCEL
3887 int i, rc = 0;
3888
3889 for (i = 0; i < bp->rx_nr_rings; i++) {
3890 u16 vnic_id = i + 1;
3891 u16 ring_id = i;
3892
3893 if (vnic_id >= bp->nr_vnics)
3894 break;
3895
3896 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
b81a90d3 3897 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
c0c050c5
MC		 3898 if (rc) {
3899 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3900 vnic_id, rc);
3901 break;
3902 }
3903 rc = bnxt_setup_vnic(bp, vnic_id);
3904 if (rc)
3905 break;
3906 }
3907 return rc;
3908#else
3909 return 0;
3910#endif
3911}
3912
b664f008
MC		 3913static int bnxt_cfg_rx_mode(struct bnxt *);
3914
c0c050c5
MC		 3915static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
3916{
3917 int rc = 0;
3918
3919 if (irq_re_init) {
3920 rc = bnxt_hwrm_stat_ctx_alloc(bp);
3921 if (rc) {
3922 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
3923 rc);
3924 goto err_out;
3925 }
3926 }
3927
3928 rc = bnxt_hwrm_ring_alloc(bp);
3929 if (rc) {
3930 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
3931 goto err_out;
3932 }
3933
3934 rc = bnxt_hwrm_ring_grp_alloc(bp);
3935 if (rc) {
3936 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
3937 goto err_out;
3938 }
3939
3940 /* default vnic 0 */
3941 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
3942 if (rc) {
3943 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
3944 goto err_out;
3945 }
3946
3947 rc = bnxt_setup_vnic(bp, 0);
3948 if (rc)
3949 goto err_out;
3950
3951 if (bp->flags & BNXT_FLAG_RFS) {
3952 rc = bnxt_alloc_rfs_vnics(bp);
3953 if (rc)
3954 goto err_out;
3955 }
3956
3957 if (bp->flags & BNXT_FLAG_TPA) {
3958 rc = bnxt_set_tpa(bp, true);
3959 if (rc)
3960 goto err_out;
3961 }
3962
3963 if (BNXT_VF(bp))
3964 bnxt_update_vf_mac(bp);
3965
3966 /* Filter for default vnic 0 */
3967 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
3968 if (rc) {
3969 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
3970 goto err_out;
3971 }
3972 bp->vnic_info[0].uc_filter_count = 1;
3973
c193554e 3974 bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
c0c050c5
MC		 3975
3976 if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
3977 bp->vnic_info[0].rx_mask |=
3978 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
3979
b664f008
MC		 3980 rc = bnxt_cfg_rx_mode(bp);
3981 if (rc)
c0c050c5 3982 goto err_out;
c0c050c5
MC		 3983
3984 rc = bnxt_hwrm_set_coal(bp);
3985 if (rc)
3986 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
3987 rc);
3988
3989 return 0;
3990
3991err_out:
3992 bnxt_hwrm_resource_free(bp, 0, true);
3993
3994 return rc;
3995}
3996
3997static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
3998{
3999 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4000 return 0;
4001}
4002
4003static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4004{
4005 bnxt_init_rx_rings(bp);
4006 bnxt_init_tx_rings(bp);
4007 bnxt_init_ring_grps(bp, irq_re_init);
4008 bnxt_init_vnics(bp);
4009
4010 return bnxt_init_chip(bp, irq_re_init);
4011}
4012
4013static void bnxt_disable_int(struct bnxt *bp)
4014{
4015 int i;
4016
4017 if (!bp->bnapi)
4018 return;
4019
4020 for (i = 0; i < bp->cp_nr_rings; i++) {
4021 struct bnxt_napi *bnapi = bp->bnapi[i];
4022 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4023
4024 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4025 }
4026}
4027
4028static void bnxt_enable_int(struct bnxt *bp)
4029{
4030 int i;
4031
4032 atomic_set(&bp->intr_sem, 0);
4033 for (i = 0; i < bp->cp_nr_rings; i++) {
4034 struct bnxt_napi *bnapi = bp->bnapi[i];
4035 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4036
4037 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4038 }
4039}
4040
4041static int bnxt_set_real_num_queues(struct bnxt *bp)
4042{
4043 int rc;
4044 struct net_device *dev = bp->dev;
4045
4046 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4047 if (rc)
4048 return rc;
4049
4050 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4051 if (rc)
4052 return rc;
4053
4054#ifdef CONFIG_RFS_ACCEL
45019a18 4055 if (bp->flags & BNXT_FLAG_RFS)
c0c050c5 4056 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
c0c050c5
MC		 4057#endif
4058
4059 return rc;
4060}
4061
6e6c5a57
MC		 4062static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4063 bool shared)
4064{
4065 int _rx = *rx, _tx = *tx;
4066
4067 if (shared) {
4068 *rx = min_t(int, _rx, max);
4069 *tx = min_t(int, _tx, max);
4070 } else {
4071 if (max < 2)
4072 return -ENOMEM;
4073
4074 while (_rx + _tx > max) {
4075 if (_rx > _tx && _rx > 1)
4076 _rx--;
4077 else if (_tx > 1)
4078 _tx--;
4079 }
4080 *rx = _rx;
4081 *tx = _tx;
4082 }
4083 return 0;
4084}
4085
c0c050c5
MC		 4086static int bnxt_setup_msix(struct bnxt *bp)
4087{
4088 struct msix_entry *msix_ent;
4089 struct net_device *dev = bp->dev;
01657bcd 4090 int i, total_vecs, rc = 0, min = 1;
c0c050c5
MC		 4091 const int len = sizeof(bp->irq_tbl[0].name);
4092
4093 bp->flags &= ~BNXT_FLAG_USING_MSIX;
4094 total_vecs = bp->cp_nr_rings;
4095
4096 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4097 if (!msix_ent)
4098 return -ENOMEM;
4099
4100 for (i = 0; i < total_vecs; i++) {
4101 msix_ent[i].entry = i;
4102 msix_ent[i].vector = 0;
4103 }
4104
01657bcd
MC		 4105 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
4106 min = 2;
4107
4108 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
c0c050c5
MC		 4109 if (total_vecs < 0) {
4110 rc = -ENODEV;
4111 goto msix_setup_exit;
4112 }
4113
4114 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4115 if (bp->irq_tbl) {
4116 int tcs;
4117
4118 /* Trim rings based upon num of vectors allocated */
6e6c5a57 4119 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
01657bcd 4120 total_vecs, min == 1);
6e6c5a57
MC		 4121 if (rc)
4122 goto msix_setup_exit;
4123
c0c050c5
MC		 4124 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4125 tcs = netdev_get_num_tc(dev);
4126 if (tcs > 1) {
4127 bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4128 if (bp->tx_nr_rings_per_tc == 0) {
4129 netdev_reset_tc(dev);
4130 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4131 } else {
4132 int i, off, count;
4133
4134 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4135 for (i = 0; i < tcs; i++) {
4136 count = bp->tx_nr_rings_per_tc;
4137 off = i * count;
4138 netdev_set_tc_queue(dev, i, count, off);
4139 }
4140 }
4141 }
01657bcd 4142 bp->cp_nr_rings = total_vecs;
c0c050c5
MC		 4143
4144 for (i = 0; i < bp->cp_nr_rings; i++) {
01657bcd
MC		 4145 char *attr;
4146
c0c050c5 4147 bp->irq_tbl[i].vector = msix_ent[i].vector;
01657bcd
MC		 4148 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4149 attr = "TxRx";
4150 else if (i < bp->rx_nr_rings)
4151 attr = "rx";
4152 else
4153 attr = "tx";
4154
c0c050c5 4155 snprintf(bp->irq_tbl[i].name, len,
01657bcd 4156 "%s-%s-%d", dev->name, attr, i);
c0c050c5
MC		 4157 bp->irq_tbl[i].handler = bnxt_msix;
4158 }
4159 rc = bnxt_set_real_num_queues(bp);
4160 if (rc)
4161 goto msix_setup_exit;
4162 } else {
4163 rc = -ENOMEM;
4164 goto msix_setup_exit;
4165 }
4166 bp->flags |= BNXT_FLAG_USING_MSIX;
4167 kfree(msix_ent);
4168 return 0;
4169
4170msix_setup_exit:
4171 netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4172 pci_disable_msix(bp->pdev);
4173 kfree(msix_ent);
4174 return rc;
4175}
4176
4177static int bnxt_setup_inta(struct bnxt *bp)
4178{
4179 int rc;
4180 const int len = sizeof(bp->irq_tbl[0].name);
4181
4182 if (netdev_get_num_tc(bp->dev))
4183 netdev_reset_tc(bp->dev);
4184
4185 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4186 if (!bp->irq_tbl) {
4187 rc = -ENOMEM;
4188 return rc;
4189 }
4190 bp->rx_nr_rings = 1;
4191 bp->tx_nr_rings = 1;
4192 bp->cp_nr_rings = 1;
4193 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
01657bcd 4194 bp->flags |= BNXT_FLAG_SHARED_RINGS;
c0c050c5
MC		 4195 bp->irq_tbl[0].vector = bp->pdev->irq;
4196 snprintf(bp->irq_tbl[0].name, len,
4197 "%s-%s-%d", bp->dev->name, "TxRx", 0);
4198 bp->irq_tbl[0].handler = bnxt_inta;
4199 rc = bnxt_set_real_num_queues(bp);
4200 return rc;
4201}
4202
4203static int bnxt_setup_int_mode(struct bnxt *bp)
4204{
4205 int rc = 0;
4206
4207 if (bp->flags & BNXT_FLAG_MSIX_CAP)
4208 rc = bnxt_setup_msix(bp);
4209
4210 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) {
4211 /* fallback to INTA */
4212 rc = bnxt_setup_inta(bp);
4213 }
4214 return rc;
4215}
4216
4217static void bnxt_free_irq(struct bnxt *bp)
4218{
4219 struct bnxt_irq *irq;
4220 int i;
4221
4222#ifdef CONFIG_RFS_ACCEL
4223 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4224 bp->dev->rx_cpu_rmap = NULL;
4225#endif
4226 if (!bp->irq_tbl)
4227 return;
4228
4229 for (i = 0; i < bp->cp_nr_rings; i++) {
4230 irq = &bp->irq_tbl[i];
4231 if (irq->requested)
4232 free_irq(irq->vector, bp->bnapi[i]);
4233 irq->requested = 0;
4234 }
4235 if (bp->flags & BNXT_FLAG_USING_MSIX)
4236 pci_disable_msix(bp->pdev);
4237 kfree(bp->irq_tbl);
4238 bp->irq_tbl = NULL;
4239}
4240
4241static int bnxt_request_irq(struct bnxt *bp)
4242{
b81a90d3 4243 int i, j, rc = 0;
c0c050c5
MC		 4244 unsigned long flags = 0;
4245#ifdef CONFIG_RFS_ACCEL
4246 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4247#endif
4248
4249 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4250 flags = IRQF_SHARED;
4251
b81a90d3 4252 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
c0c050c5
MC		 4253 struct bnxt_irq *irq = &bp->irq_tbl[i];
4254#ifdef CONFIG_RFS_ACCEL
b81a90d3 4255 if (rmap && bp->bnapi[i]->rx_ring) {
c0c050c5
MC		 4256 rc = irq_cpu_rmap_add(rmap, irq->vector);
4257 if (rc)
4258 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
b81a90d3
MC		 4259 j);
4260 j++;
c0c050c5
MC		 4261 }
4262#endif
4263 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4264 bp->bnapi[i]);
4265 if (rc)
4266 break;
4267
4268 irq->requested = 1;
4269 }
4270 return rc;
4271}
4272
4273static void bnxt_del_napi(struct bnxt *bp)
4274{
4275 int i;
4276
4277 if (!bp->bnapi)
4278 return;
4279
4280 for (i = 0; i < bp->cp_nr_rings; i++) {
4281 struct bnxt_napi *bnapi = bp->bnapi[i];
4282
4283 napi_hash_del(&bnapi->napi);
4284 netif_napi_del(&bnapi->napi);
4285 }
4286}
4287
4288static void bnxt_init_napi(struct bnxt *bp)
4289{
4290 int i;
4291 struct bnxt_napi *bnapi;
4292
4293 if (bp->flags & BNXT_FLAG_USING_MSIX) {
4294 for (i = 0; i < bp->cp_nr_rings; i++) {
4295 bnapi = bp->bnapi[i];
4296 netif_napi_add(bp->dev, &bnapi->napi,
4297 bnxt_poll, 64);
c0c050c5
MC		 4298 }
4299 } else {
4300 bnapi = bp->bnapi[0];
4301 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
c0c050c5
MC		 4302 }
4303}
4304
4305static void bnxt_disable_napi(struct bnxt *bp)
4306{
4307 int i;
4308
4309 if (!bp->bnapi)
4310 return;
4311
4312 for (i = 0; i < bp->cp_nr_rings; i++) {
4313 napi_disable(&bp->bnapi[i]->napi);
4314 bnxt_disable_poll(bp->bnapi[i]);
4315 }
4316}
4317
4318static void bnxt_enable_napi(struct bnxt *bp)
4319{
4320 int i;
4321
4322 for (i = 0; i < bp->cp_nr_rings; i++) {
4323 bnxt_enable_poll(bp->bnapi[i]);
4324 napi_enable(&bp->bnapi[i]->napi);
4325 }
4326}
4327
4328static void bnxt_tx_disable(struct bnxt *bp)
4329{
4330 int i;
c0c050c5
MC		 4331 struct bnxt_tx_ring_info *txr;
4332 struct netdev_queue *txq;
4333
b6ab4b01 4334 if (bp->tx_ring) {
c0c050c5 4335 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4336 txr = &bp->tx_ring[i];
c0c050c5
MC		 4337 txq = netdev_get_tx_queue(bp->dev, i);
4338 __netif_tx_lock(txq, smp_processor_id());
4339 txr->dev_state = BNXT_DEV_STATE_CLOSING;
4340 __netif_tx_unlock(txq);
4341 }
4342 }
4343 /* Stop all TX queues */
4344 netif_tx_disable(bp->dev);
4345 netif_carrier_off(bp->dev);
4346}
4347
4348static void bnxt_tx_enable(struct bnxt *bp)
4349{
4350 int i;
c0c050c5
MC		 4351 struct bnxt_tx_ring_info *txr;
4352 struct netdev_queue *txq;
4353
4354 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4355 txr = &bp->tx_ring[i];
c0c050c5
MC		 4356 txq = netdev_get_tx_queue(bp->dev, i);
4357 txr->dev_state = 0;
4358 }
4359 netif_tx_wake_all_queues(bp->dev);
4360 if (bp->link_info.link_up)
4361 netif_carrier_on(bp->dev);
4362}
4363
4364static void bnxt_report_link(struct bnxt *bp)
4365{
4366 if (bp->link_info.link_up) {
4367 const char *duplex;
4368 const char *flow_ctrl;
4369 u16 speed;
4370
4371 netif_carrier_on(bp->dev);
4372 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4373 duplex = "full";
4374 else
4375 duplex = "half";
4376 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4377 flow_ctrl = "ON - receive & transmit";
4378 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4379 flow_ctrl = "ON - transmit";
4380 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4381 flow_ctrl = "ON - receive";
4382 else
4383 flow_ctrl = "none";
4384 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4385 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4386 speed, duplex, flow_ctrl);
4387 } else {
4388 netif_carrier_off(bp->dev);
4389 netdev_err(bp->dev, "NIC Link is Down\n");
4390 }
4391}
4392
4393static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4394{
4395 int rc = 0;
4396 struct bnxt_link_info *link_info = &bp->link_info;
4397 struct hwrm_port_phy_qcfg_input req = {0};
4398 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4399 u8 link_up = link_info->link_up;
4400
4401 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4402
4403 mutex_lock(&bp->hwrm_cmd_lock);
4404 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4405 if (rc) {
4406 mutex_unlock(&bp->hwrm_cmd_lock);
4407 return rc;
4408 }
4409
4410 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4411 link_info->phy_link_status = resp->link;
4412 link_info->duplex = resp->duplex;
4413 link_info->pause = resp->pause;
4414 link_info->auto_mode = resp->auto_mode;
4415 link_info->auto_pause_setting = resp->auto_pause;
4416 link_info->force_pause_setting = resp->force_pause;
c193554e 4417 link_info->duplex_setting = resp->duplex;
c0c050c5
MC		 4418 if (link_info->phy_link_status == BNXT_LINK_LINK)
4419 link_info->link_speed = le16_to_cpu(resp->link_speed);
4420 else
4421 link_info->link_speed = 0;
4422 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
4423 link_info->auto_link_speed = le16_to_cpu(resp->auto_link_speed);
4424 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4425 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
4426 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4427 link_info->phy_ver[0] = resp->phy_maj;
4428 link_info->phy_ver[1] = resp->phy_min;
4429 link_info->phy_ver[2] = resp->phy_bld;
4430 link_info->media_type = resp->media_type;
4431 link_info->transceiver = resp->transceiver_type;
4432 link_info->phy_addr = resp->phy_addr;
4433
4434 /* TODO: need to add more logic to report VF link */
4435 if (chng_link_state) {
4436 if (link_info->phy_link_status == BNXT_LINK_LINK)
4437 link_info->link_up = 1;
4438 else
4439 link_info->link_up = 0;
4440 if (link_up != link_info->link_up)
4441 bnxt_report_link(bp);
4442 } else {
4443 /* alwasy link down if not require to update link state */
4444 link_info->link_up = 0;
4445 }
4446 mutex_unlock(&bp->hwrm_cmd_lock);
4447 return 0;
4448}
4449
4450static void
4451bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4452{
4453 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
4454 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4455 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4456 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4457 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4458 req->enables |=
4459 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4460 } else {
4461 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4462 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4463 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4464 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4465 req->enables |=
4466 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
4467 }
4468}
4469
4470static void bnxt_hwrm_set_link_common(struct bnxt *bp,
4471 struct hwrm_port_phy_cfg_input *req)
4472{
4473 u8 autoneg = bp->link_info.autoneg;
4474 u16 fw_link_speed = bp->link_info.req_link_speed;
4475 u32 advertising = bp->link_info.advertising;
4476
4477 if (autoneg & BNXT_AUTONEG_SPEED) {
4478 req->auto_mode |=
4479 PORT_PHY_CFG_REQ_AUTO_MODE_MASK;
4480
4481 req->enables |= cpu_to_le32(
4482 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
4483 req->auto_link_speed_mask = cpu_to_le16(advertising);
4484
4485 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
4486 req->flags |=
4487 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
4488 } else {
4489 req->force_link_speed = cpu_to_le16(fw_link_speed);
4490 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
4491 }
4492
4493 /* currently don't support half duplex */
4494 req->auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL;
4495 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX);
4496 /* tell chimp that the setting takes effect immediately */
4497 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4498}
4499
4500int bnxt_hwrm_set_pause(struct bnxt *bp)
4501{
4502 struct hwrm_port_phy_cfg_input req = {0};
4503 int rc;
4504
4505 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4506 bnxt_hwrm_set_pause_common(bp, &req);
4507
4508 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
4509 bp->link_info.force_link_chng)
4510 bnxt_hwrm_set_link_common(bp, &req);
4511
4512 mutex_lock(&bp->hwrm_cmd_lock);
4513 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4514 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
4515 /* since changing of pause setting doesn't trigger any link
4516 * change event, the driver needs to update the current pause
4517 * result upon successfully return of the phy_cfg command
4518 */
4519 bp->link_info.pause =
4520 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
4521 bp->link_info.auto_pause_setting = 0;
4522 if (!bp->link_info.force_link_chng)
4523 bnxt_report_link(bp);
4524 }
4525 bp->link_info.force_link_chng = false;
4526 mutex_unlock(&bp->hwrm_cmd_lock);
4527 return rc;
4528}
4529
4530int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause)
4531{
4532 struct hwrm_port_phy_cfg_input req = {0};
4533
4534 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4535 if (set_pause)
4536 bnxt_hwrm_set_pause_common(bp, &req);
4537
4538 bnxt_hwrm_set_link_common(bp, &req);
4539 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4540}
4541
4542static int bnxt_update_phy_setting(struct bnxt *bp)
4543{
4544 int rc;
4545 bool update_link = false;
4546 bool update_pause = false;
4547 struct bnxt_link_info *link_info = &bp->link_info;
4548
4549 rc = bnxt_update_link(bp, true);
4550 if (rc) {
4551 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
4552 rc);
4553 return rc;
4554 }
4555 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4556 link_info->auto_pause_setting != link_info->req_flow_ctrl)
4557 update_pause = true;
4558 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4559 link_info->force_pause_setting != link_info->req_flow_ctrl)
4560 update_pause = true;
c0c050c5
MC		 4561 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4562 if (BNXT_AUTO_MODE(link_info->auto_mode))
4563 update_link = true;
4564 if (link_info->req_link_speed != link_info->force_link_speed)
4565 update_link = true;
de73018f
MC		 4566 if (link_info->req_duplex != link_info->duplex_setting)
4567 update_link = true;
c0c050c5
MC		 4568 } else {
4569 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
4570 update_link = true;
4571 if (link_info->advertising != link_info->auto_link_speeds)
4572 update_link = true;
c0c050c5
MC		 4573 }
4574
4575 if (update_link)
4576 rc = bnxt_hwrm_set_link_setting(bp, update_pause);
4577 else if (update_pause)
4578 rc = bnxt_hwrm_set_pause(bp);
4579 if (rc) {
4580 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
4581 rc);
4582 return rc;
4583 }
4584
4585 return rc;
4586}
4587
11809490
JH		 4588/* Common routine to pre-map certain register block to different GRC window.
4589 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4590 * in PF and 3 windows in VF that can be customized to map in different
4591 * register blocks.
4592 */
4593static void bnxt_preset_reg_win(struct bnxt *bp)
4594{
4595 if (BNXT_PF(bp)) {
4596 /* CAG registers map to GRC window #4 */
4597 writel(BNXT_CAG_REG_BASE,
4598 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
4599 }
4600}
4601
c0c050c5
MC		 4602static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4603{
4604 int rc = 0;
4605
11809490 4606 bnxt_preset_reg_win(bp);
c0c050c5
MC		 4607 netif_carrier_off(bp->dev);
4608 if (irq_re_init) {
4609 rc = bnxt_setup_int_mode(bp);
4610 if (rc) {
4611 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
4612 rc);
4613 return rc;
4614 }
4615 }
4616 if ((bp->flags & BNXT_FLAG_RFS) &&
4617 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
4618 /* disable RFS if falling back to INTA */
4619 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
4620 bp->flags &= ~BNXT_FLAG_RFS;
4621 }
4622
4623 rc = bnxt_alloc_mem(bp, irq_re_init);
4624 if (rc) {
4625 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
4626 goto open_err_free_mem;
4627 }
4628
4629 if (irq_re_init) {
4630 bnxt_init_napi(bp);
4631 rc = bnxt_request_irq(bp);
4632 if (rc) {
4633 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
4634 goto open_err;
4635 }
4636 }
4637
4638 bnxt_enable_napi(bp);
4639
4640 rc = bnxt_init_nic(bp, irq_re_init);
4641 if (rc) {
4642 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
4643 goto open_err;
4644 }
4645
4646 if (link_re_init) {
4647 rc = bnxt_update_phy_setting(bp);
4648 if (rc)
ba41d46f 4649 netdev_warn(bp->dev, "failed to update phy settings\n");
c0c050c5
MC		 4650 }
4651
4652 if (irq_re_init) {
4653#if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4654 vxlan_get_rx_port(bp->dev);
4655#endif
4656 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4657 bp, htons(0x17c1),
4658 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE))
4659 bp->nge_port_cnt = 1;
4660 }
4661
caefe526 4662 set_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 4663 bnxt_enable_int(bp);
4664 /* Enable TX queues */
4665 bnxt_tx_enable(bp);
4666 mod_timer(&bp->timer, jiffies + bp->current_interval);
035a1539 4667 bnxt_update_link(bp, true);
c0c050c5
MC		 4668
4669 return 0;
4670
4671open_err:
4672 bnxt_disable_napi(bp);
4673 bnxt_del_napi(bp);
4674
4675open_err_free_mem:
4676 bnxt_free_skbs(bp);
4677 bnxt_free_irq(bp);
4678 bnxt_free_mem(bp, true);
4679 return rc;
4680}
4681
4682/* rtnl_lock held */
4683int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4684{
4685 int rc = 0;
4686
4687 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
4688 if (rc) {
4689 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
4690 dev_close(bp->dev);
4691 }
4692 return rc;
4693}
4694
4695static int bnxt_open(struct net_device *dev)
4696{
4697 struct bnxt *bp = netdev_priv(dev);
4698 int rc = 0;
4699
4700 rc = bnxt_hwrm_func_reset(bp);
4701 if (rc) {
4702 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
4703 rc);
4704 rc = -1;
4705 return rc;
4706 }
4707 return __bnxt_open_nic(bp, true, true);
4708}
4709
4710static void bnxt_disable_int_sync(struct bnxt *bp)
4711{
4712 int i;
4713
4714 atomic_inc(&bp->intr_sem);
4715 if (!netif_running(bp->dev))
4716 return;
4717
4718 bnxt_disable_int(bp);
4719 for (i = 0; i < bp->cp_nr_rings; i++)
4720 synchronize_irq(bp->irq_tbl[i].vector);
4721}
4722
4723int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4724{
4725 int rc = 0;
4726
4727#ifdef CONFIG_BNXT_SRIOV
4728 if (bp->sriov_cfg) {
4729 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
4730 !bp->sriov_cfg,
4731 BNXT_SRIOV_CFG_WAIT_TMO);
4732 if (rc)
4733 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
4734 }
4735#endif
4736 /* Change device state to avoid TX queue wake up's */
4737 bnxt_tx_disable(bp);
4738
caefe526 4739 clear_bit(BNXT_STATE_OPEN, &bp->state);
4cebdcec
MC		 4740 smp_mb__after_atomic();
4741 while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
4742 msleep(20);
c0c050c5
MC		 4743
4744 /* Flush rings before disabling interrupts */
4745 bnxt_shutdown_nic(bp, irq_re_init);
4746
4747 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4748
4749 bnxt_disable_napi(bp);
4750 bnxt_disable_int_sync(bp);
4751 del_timer_sync(&bp->timer);
4752 bnxt_free_skbs(bp);
4753
4754 if (irq_re_init) {
4755 bnxt_free_irq(bp);
4756 bnxt_del_napi(bp);
4757 }
4758 bnxt_free_mem(bp, irq_re_init);
4759 return rc;
4760}
4761
4762static int bnxt_close(struct net_device *dev)
4763{
4764 struct bnxt *bp = netdev_priv(dev);
4765
4766 bnxt_close_nic(bp, true, true);
4767 return 0;
4768}
4769
4770/* rtnl_lock held */
4771static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4772{
4773 switch (cmd) {
4774 case SIOCGMIIPHY:
4775 /* fallthru */
4776 case SIOCGMIIREG: {
4777 if (!netif_running(dev))
4778 return -EAGAIN;
4779
4780 return 0;
4781 }
4782
4783 case SIOCSMIIREG:
4784 if (!netif_running(dev))
4785 return -EAGAIN;
4786
4787 return 0;
4788
4789 default:
4790 /* do nothing */
4791 break;
4792 }
4793 return -EOPNOTSUPP;
4794}
4795
4796static struct rtnl_link_stats64 *
4797bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4798{
4799 u32 i;
4800 struct bnxt *bp = netdev_priv(dev);
4801
4802 memset(stats, 0, sizeof(struct rtnl_link_stats64));
4803
4804 if (!bp->bnapi)
4805 return stats;
4806
4807 /* TODO check if we need to synchronize with bnxt_close path */
4808 for (i = 0; i < bp->cp_nr_rings; i++) {
4809 struct bnxt_napi *bnapi = bp->bnapi[i];
4810 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4811 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
4812
4813 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
4814 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
4815 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
4816
4817 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
4818 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
4819 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
4820
4821 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
4822 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
4823 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
4824
4825 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
4826 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
4827 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
4828
4829 stats->rx_missed_errors +=
4830 le64_to_cpu(hw_stats->rx_discard_pkts);
4831
4832 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
4833
c0c050c5
MC		 4834 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
4835 }
4836
4837 return stats;
4838}
4839
4840static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
4841{
4842 struct net_device *dev = bp->dev;
4843 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4844 struct netdev_hw_addr *ha;
4845 u8 *haddr;
4846 int mc_count = 0;
4847 bool update = false;
4848 int off = 0;
4849
4850 netdev_for_each_mc_addr(ha, dev) {
4851 if (mc_count >= BNXT_MAX_MC_ADDRS) {
4852 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4853 vnic->mc_list_count = 0;
4854 return false;
4855 }
4856 haddr = ha->addr;
4857 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
4858 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
4859 update = true;
4860 }
4861 off += ETH_ALEN;
4862 mc_count++;
4863 }
4864 if (mc_count)
4865 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
4866
4867 if (mc_count != vnic->mc_list_count) {
4868 vnic->mc_list_count = mc_count;
4869 update = true;
4870 }
4871 return update;
4872}
4873
4874static bool bnxt_uc_list_updated(struct bnxt *bp)
4875{
4876 struct net_device *dev = bp->dev;
4877 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4878 struct netdev_hw_addr *ha;
4879 int off = 0;
4880
4881 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
4882 return true;
4883
4884 netdev_for_each_uc_addr(ha, dev) {
4885 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
4886 return true;
4887
4888 off += ETH_ALEN;
4889 }
4890 return false;
4891}
4892
4893static void bnxt_set_rx_mode(struct net_device *dev)
4894{
4895 struct bnxt *bp = netdev_priv(dev);
4896 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4897 u32 mask = vnic->rx_mask;
4898 bool mc_update = false;
4899 bool uc_update;
4900
4901 if (!netif_running(dev))
4902 return;
4903
4904 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
4905 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
4906 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
4907
4908 /* Only allow PF to be in promiscuous mode */
4909 if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4910 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4911
4912 uc_update = bnxt_uc_list_updated(bp);
4913
4914 if (dev->flags & IFF_ALLMULTI) {
4915 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4916 vnic->mc_list_count = 0;
4917 } else {
4918 mc_update = bnxt_mc_list_updated(bp, &mask);
4919 }
4920
4921 if (mask != vnic->rx_mask || uc_update || mc_update) {
4922 vnic->rx_mask = mask;
4923
4924 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
4925 schedule_work(&bp->sp_task);
4926 }
4927}
4928
b664f008 4929static int bnxt_cfg_rx_mode(struct bnxt *bp)
c0c050c5
MC		 4930{
4931 struct net_device *dev = bp->dev;
4932 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4933 struct netdev_hw_addr *ha;
4934 int i, off = 0, rc;
4935 bool uc_update;
4936
4937 netif_addr_lock_bh(dev);
4938 uc_update = bnxt_uc_list_updated(bp);
4939 netif_addr_unlock_bh(dev);
4940
4941 if (!uc_update)
4942 goto skip_uc;
4943
4944 mutex_lock(&bp->hwrm_cmd_lock);
4945 for (i = 1; i < vnic->uc_filter_count; i++) {
4946 struct hwrm_cfa_l2_filter_free_input req = {0};
4947
4948 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
4949 -1);
4950
4951 req.l2_filter_id = vnic->fw_l2_filter_id[i];
4952
4953 rc = _hwrm_send_message(bp, &req, sizeof(req),
4954 HWRM_CMD_TIMEOUT);
4955 }
4956 mutex_unlock(&bp->hwrm_cmd_lock);
4957
4958 vnic->uc_filter_count = 1;
4959
4960 netif_addr_lock_bh(dev);
4961 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
4962 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4963 } else {
4964 netdev_for_each_uc_addr(ha, dev) {
4965 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
4966 off += ETH_ALEN;
4967 vnic->uc_filter_count++;
4968 }
4969 }
4970 netif_addr_unlock_bh(dev);
4971
4972 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
4973 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
4974 if (rc) {
4975 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
4976 rc);
4977 vnic->uc_filter_count = i;
b664f008 4978 return rc;
c0c050c5
MC		 4979 }
4980 }
4981
4982skip_uc:
4983 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
4984 if (rc)
4985 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
4986 rc);
b664f008
MC		 4987
4988 return rc;
c0c050c5
MC		 4989}
4990
2bcfa6f6
MC		 4991static bool bnxt_rfs_capable(struct bnxt *bp)
4992{
4993#ifdef CONFIG_RFS_ACCEL
4994 struct bnxt_pf_info *pf = &bp->pf;
4995 int vnics;
4996
4997 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
4998 return false;
4999
5000 vnics = 1 + bp->rx_nr_rings;
5001 if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics)
5002 return false;
5003
5004 return true;
5005#else
5006 return false;
5007#endif
5008}
5009
c0c050c5
MC		 5010static netdev_features_t bnxt_fix_features(struct net_device *dev,
5011 netdev_features_t features)
5012{
2bcfa6f6
MC		 5013 struct bnxt *bp = netdev_priv(dev);
5014
5015 if (!bnxt_rfs_capable(bp))
5016 features &= ~NETIF_F_NTUPLE;
c0c050c5
MC		 5017 return features;
5018}
5019
5020static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
5021{
5022 struct bnxt *bp = netdev_priv(dev);
5023 u32 flags = bp->flags;
5024 u32 changes;
5025 int rc = 0;
5026 bool re_init = false;
5027 bool update_tpa = false;
5028
5029 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
5030 if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
5031 flags |= BNXT_FLAG_GRO;
5032 if (features & NETIF_F_LRO)
5033 flags |= BNXT_FLAG_LRO;
5034
5035 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5036 flags |= BNXT_FLAG_STRIP_VLAN;
5037
5038 if (features & NETIF_F_NTUPLE)
5039 flags |= BNXT_FLAG_RFS;
5040
5041 changes = flags ^ bp->flags;
5042 if (changes & BNXT_FLAG_TPA) {
5043 update_tpa = true;
5044 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5045 (flags & BNXT_FLAG_TPA) == 0)
5046 re_init = true;
5047 }
5048
5049 if (changes & ~BNXT_FLAG_TPA)
5050 re_init = true;
5051
5052 if (flags != bp->flags) {
5053 u32 old_flags = bp->flags;
5054
5055 bp->flags = flags;
5056
2bcfa6f6 5057 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
c0c050c5
MC		 5058 if (update_tpa)
5059 bnxt_set_ring_params(bp);
5060 return rc;
5061 }
5062
5063 if (re_init) {
5064 bnxt_close_nic(bp, false, false);
5065 if (update_tpa)
5066 bnxt_set_ring_params(bp);
5067
5068 return bnxt_open_nic(bp, false, false);
5069 }
5070 if (update_tpa) {
5071 rc = bnxt_set_tpa(bp,
5072 (flags & BNXT_FLAG_TPA) ?
5073 true : false);
5074 if (rc)
5075 bp->flags = old_flags;
5076 }
5077 }
5078 return rc;
5079}
5080
9f554590
MC		 5081static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
5082{
b6ab4b01 5083 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9f554590
MC		 5084 int i = bnapi->index;
5085
3b2b7d9d
MC		 5086 if (!txr)
5087 return;
5088
9f554590
MC		 5089 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5090 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
5091 txr->tx_cons);
5092}
5093
5094static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
5095{
b6ab4b01 5096 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9f554590
MC		 5097 int i = bnapi->index;
5098
3b2b7d9d
MC		 5099 if (!rxr)
5100 return;
5101
9f554590
MC		 5102 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5103 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
5104 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
5105 rxr->rx_sw_agg_prod);
5106}
5107
5108static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
5109{
5110 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5111 int i = bnapi->index;
5112
5113 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5114 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
5115}
5116
c0c050c5
MC		 5117static void bnxt_dbg_dump_states(struct bnxt *bp)
5118{
5119 int i;
5120 struct bnxt_napi *bnapi;
c0c050c5
MC		 5121
5122 for (i = 0; i < bp->cp_nr_rings; i++) {
5123 bnapi = bp->bnapi[i];
c0c050c5 5124 if (netif_msg_drv(bp)) {
9f554590
MC		 5125 bnxt_dump_tx_sw_state(bnapi);
5126 bnxt_dump_rx_sw_state(bnapi);
5127 bnxt_dump_cp_sw_state(bnapi);
c0c050c5
MC		 5128 }
5129 }
5130}
5131
5132static void bnxt_reset_task(struct bnxt *bp)
5133{
5134 bnxt_dbg_dump_states(bp);
028de140
MC		 5135 if (netif_running(bp->dev)) {
5136 bnxt_close_nic(bp, false, false);
5137 bnxt_open_nic(bp, false, false);
5138 }
c0c050c5
MC		 5139}
5140
5141static void bnxt_tx_timeout(struct net_device *dev)
5142{
5143 struct bnxt *bp = netdev_priv(dev);
5144
5145 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
5146 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5147 schedule_work(&bp->sp_task);
5148}
5149
5150#ifdef CONFIG_NET_POLL_CONTROLLER
5151static void bnxt_poll_controller(struct net_device *dev)
5152{
5153 struct bnxt *bp = netdev_priv(dev);
5154 int i;
5155
5156 for (i = 0; i < bp->cp_nr_rings; i++) {
5157 struct bnxt_irq *irq = &bp->irq_tbl[i];
5158
5159 disable_irq(irq->vector);
5160 irq->handler(irq->vector, bp->bnapi[i]);
5161 enable_irq(irq->vector);
5162 }
5163}
5164#endif
5165
5166static void bnxt_timer(unsigned long data)
5167{
5168 struct bnxt *bp = (struct bnxt *)data;
5169 struct net_device *dev = bp->dev;
5170
5171 if (!netif_running(dev))
5172 return;
5173
5174 if (atomic_read(&bp->intr_sem) != 0)
5175 goto bnxt_restart_timer;
5176
5177bnxt_restart_timer:
5178 mod_timer(&bp->timer, jiffies + bp->current_interval);
5179}
5180
5181static void bnxt_cfg_ntp_filters(struct bnxt *);
5182
5183static void bnxt_sp_task(struct work_struct *work)
5184{
5185 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5186 int rc;
5187
4cebdcec
MC		 5188 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5189 smp_mb__after_atomic();
5190 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5191 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5 5192 return;
4cebdcec 5193 }
c0c050c5
MC		 5194
5195 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5196 bnxt_cfg_rx_mode(bp);
5197
5198 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5199 bnxt_cfg_ntp_filters(bp);
5200 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5201 rc = bnxt_update_link(bp, true);
5202 if (rc)
5203 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5204 rc);
5205 }
5206 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5207 bnxt_hwrm_exec_fwd_req(bp);
5208 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5209 bnxt_hwrm_tunnel_dst_port_alloc(
5210 bp, bp->vxlan_port,
5211 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5212 }
5213 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5214 bnxt_hwrm_tunnel_dst_port_free(
5215 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5216 }
028de140
MC		 5217 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) {
5218 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5219 * for BNXT_STATE_IN_SP_TASK to clear.
5220 */
5221 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5222 rtnl_lock();
c0c050c5 5223 bnxt_reset_task(bp);
028de140
MC		 5224 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5225 rtnl_unlock();
5226 }
4cebdcec
MC		 5227
5228 smp_mb__before_atomic();
5229 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5
MC		 5230}
5231
5232static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5233{
5234 int rc;
5235 struct bnxt *bp = netdev_priv(dev);
5236
5237 SET_NETDEV_DEV(dev, &pdev->dev);
5238
5239 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5240 rc = pci_enable_device(pdev);
5241 if (rc) {
5242 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5243 goto init_err;
5244 }
5245
5246 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5247 dev_err(&pdev->dev,
5248 "Cannot find PCI device base address, aborting\n");
5249 rc = -ENODEV;
5250 goto init_err_disable;
5251 }
5252
5253 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5254 if (rc) {
5255 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5256 goto init_err_disable;
5257 }
5258
5259 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5260 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5261 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5262 goto init_err_disable;
5263 }
5264
5265 pci_set_master(pdev);
5266
5267 bp->dev = dev;
5268 bp->pdev = pdev;
5269
5270 bp->bar0 = pci_ioremap_bar(pdev, 0);
5271 if (!bp->bar0) {
5272 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5273 rc = -ENOMEM;
5274 goto init_err_release;
5275 }
5276
5277 bp->bar1 = pci_ioremap_bar(pdev, 2);
5278 if (!bp->bar1) {
5279 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5280 rc = -ENOMEM;
5281 goto init_err_release;
5282 }
5283
5284 bp->bar2 = pci_ioremap_bar(pdev, 4);
5285 if (!bp->bar2) {
5286 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5287 rc = -ENOMEM;
5288 goto init_err_release;
5289 }
5290
5291 INIT_WORK(&bp->sp_task, bnxt_sp_task);
5292
5293 spin_lock_init(&bp->ntp_fltr_lock);
5294
5295 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5296 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5297
5298 bp->coal_ticks = BNXT_USEC_TO_COAL_TIMER(4);
5299 bp->coal_bufs = 20;
5300 bp->coal_ticks_irq = BNXT_USEC_TO_COAL_TIMER(1);
5301 bp->coal_bufs_irq = 2;
5302
5303 init_timer(&bp->timer);
5304 bp->timer.data = (unsigned long)bp;
5305 bp->timer.function = bnxt_timer;
5306 bp->current_interval = BNXT_TIMER_INTERVAL;
5307
caefe526 5308 clear_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 5309
5310 return 0;
5311
5312init_err_release:
5313 if (bp->bar2) {
5314 pci_iounmap(pdev, bp->bar2);
5315 bp->bar2 = NULL;
5316 }
5317
5318 if (bp->bar1) {
5319 pci_iounmap(pdev, bp->bar1);
5320 bp->bar1 = NULL;
5321 }
5322
5323 if (bp->bar0) {
5324 pci_iounmap(pdev, bp->bar0);
5325 bp->bar0 = NULL;
5326 }
5327
5328 pci_release_regions(pdev);
5329
5330init_err_disable:
5331 pci_disable_device(pdev);
5332
5333init_err:
5334 return rc;
5335}
5336
5337/* rtnl_lock held */
5338static int bnxt_change_mac_addr(struct net_device *dev, void *p)
5339{
5340 struct sockaddr *addr = p;
1fc2cfd0
JH		 5341 struct bnxt *bp = netdev_priv(dev);
5342 int rc = 0;
c0c050c5
MC		 5343
5344 if (!is_valid_ether_addr(addr->sa_data))
5345 return -EADDRNOTAVAIL;
5346
bdd4347b
JH		 5347#ifdef CONFIG_BNXT_SRIOV
5348 if (BNXT_VF(bp) && is_valid_ether_addr(bp->vf.mac_addr))
5349 return -EADDRNOTAVAIL;
5350#endif
5351
1fc2cfd0
JH		 5352 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
5353 return 0;
5354
c0c050c5 5355 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1fc2cfd0
JH		 5356 if (netif_running(dev)) {
5357 bnxt_close_nic(bp, false, false);
5358 rc = bnxt_open_nic(bp, false, false);
5359 }
c0c050c5 5360
1fc2cfd0 5361 return rc;
c0c050c5
MC		 5362}
5363
5364/* rtnl_lock held */
5365static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
5366{
5367 struct bnxt *bp = netdev_priv(dev);
5368
5369 if (new_mtu < 60 || new_mtu > 9000)
5370 return -EINVAL;
5371
5372 if (netif_running(dev))
5373 bnxt_close_nic(bp, false, false);
5374
5375 dev->mtu = new_mtu;
5376 bnxt_set_ring_params(bp);
5377
5378 if (netif_running(dev))
5379 return bnxt_open_nic(bp, false, false);
5380
5381 return 0;
5382}
5383
16e5cc64
JF		 5384static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
5385 struct tc_to_netdev *ntc)
c0c050c5
MC		 5386{
5387 struct bnxt *bp = netdev_priv(dev);
16e5cc64 5388 u8 tc;
c0c050c5 5389
16e5cc64 5390 if (handle != TC_H_ROOT || ntc->type != TC_SETUP_MQPRIO)
e4c6734e
JF		 5391 return -EINVAL;
5392
16e5cc64
JF		 5393 tc = ntc->tc;
5394
c0c050c5
MC		 5395 if (tc > bp->max_tc) {
5396 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
5397 tc, bp->max_tc);
5398 return -EINVAL;
5399 }
5400
5401 if (netdev_get_num_tc(dev) == tc)
5402 return 0;
5403
5404 if (tc) {
6e6c5a57 5405 int max_rx_rings, max_tx_rings, rc;
01657bcd
MC		 5406 bool sh = false;
5407
5408 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5409 sh = true;
c0c050c5 5410
01657bcd 5411 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6e6c5a57 5412 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
c0c050c5
MC		 5413 return -ENOMEM;
5414 }
5415
5416 /* Needs to close the device and do hw resource re-allocations */
5417 if (netif_running(bp->dev))
5418 bnxt_close_nic(bp, true, false);
5419
5420 if (tc) {
5421 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
5422 netdev_set_num_tc(dev, tc);
5423 } else {
5424 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5425 netdev_reset_tc(dev);
5426 }
5427 bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
5428 bp->num_stat_ctxs = bp->cp_nr_rings;
5429
5430 if (netif_running(bp->dev))
5431 return bnxt_open_nic(bp, true, false);
5432
5433 return 0;
5434}
5435
5436#ifdef CONFIG_RFS_ACCEL
5437static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
5438 struct bnxt_ntuple_filter *f2)
5439{
5440 struct flow_keys *keys1 = &f1->fkeys;
5441 struct flow_keys *keys2 = &f2->fkeys;
5442
5443 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
5444 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
5445 keys1->ports.ports == keys2->ports.ports &&
5446 keys1->basic.ip_proto == keys2->basic.ip_proto &&
5447 keys1->basic.n_proto == keys2->basic.n_proto &&
5448 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
5449 return true;
5450
5451 return false;
5452}
5453
5454static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
5455 u16 rxq_index, u32 flow_id)
5456{
5457 struct bnxt *bp = netdev_priv(dev);
5458 struct bnxt_ntuple_filter *fltr, *new_fltr;
5459 struct flow_keys *fkeys;
5460 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
84e86b98 5461 int rc = 0, idx, bit_id;
c0c050c5
MC		 5462 struct hlist_head *head;
5463
5464 if (skb->encapsulation)
5465 return -EPROTONOSUPPORT;
5466
5467 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
5468 if (!new_fltr)
5469 return -ENOMEM;
5470
5471 fkeys = &new_fltr->fkeys;
5472 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
5473 rc = -EPROTONOSUPPORT;
5474 goto err_free;
5475 }
5476
5477 if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
5478 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
5479 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
5480 rc = -EPROTONOSUPPORT;
5481 goto err_free;
5482 }
5483
5484 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
5485
5486 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
5487 head = &bp->ntp_fltr_hash_tbl[idx];
5488 rcu_read_lock();
5489 hlist_for_each_entry_rcu(fltr, head, hash) {
5490 if (bnxt_fltr_match(fltr, new_fltr)) {
5491 rcu_read_unlock();
5492 rc = 0;
5493 goto err_free;
5494 }
5495 }
5496 rcu_read_unlock();
5497
5498 spin_lock_bh(&bp->ntp_fltr_lock);
84e86b98
MC		 5499 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
5500 BNXT_NTP_FLTR_MAX_FLTR, 0);
5501 if (bit_id < 0) {
c0c050c5
MC		 5502 spin_unlock_bh(&bp->ntp_fltr_lock);
5503 rc = -ENOMEM;
5504 goto err_free;
5505 }
5506
84e86b98 5507 new_fltr->sw_id = (u16)bit_id;
c0c050c5
MC		 5508 new_fltr->flow_id = flow_id;
5509 new_fltr->rxq = rxq_index;
5510 hlist_add_head_rcu(&new_fltr->hash, head);
5511 bp->ntp_fltr_count++;
5512 spin_unlock_bh(&bp->ntp_fltr_lock);
5513
5514 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
5515 schedule_work(&bp->sp_task);
5516
5517 return new_fltr->sw_id;
5518
5519err_free:
5520 kfree(new_fltr);
5521 return rc;
5522}
5523
5524static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5525{
5526 int i;
5527
5528 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
5529 struct hlist_head *head;
5530 struct hlist_node *tmp;
5531 struct bnxt_ntuple_filter *fltr;
5532 int rc;
5533
5534 head = &bp->ntp_fltr_hash_tbl[i];
5535 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
5536 bool del = false;
5537
5538 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
5539 if (rps_may_expire_flow(bp->dev, fltr->rxq,
5540 fltr->flow_id,
5541 fltr->sw_id)) {
5542 bnxt_hwrm_cfa_ntuple_filter_free(bp,
5543 fltr);
5544 del = true;
5545 }
5546 } else {
5547 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
5548 fltr);
5549 if (rc)
5550 del = true;
5551 else
5552 set_bit(BNXT_FLTR_VALID, &fltr->state);
5553 }
5554
5555 if (del) {
5556 spin_lock_bh(&bp->ntp_fltr_lock);
5557 hlist_del_rcu(&fltr->hash);
5558 bp->ntp_fltr_count--;
5559 spin_unlock_bh(&bp->ntp_fltr_lock);
5560 synchronize_rcu();
5561 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
5562 kfree(fltr);
5563 }
5564 }
5565 }
19241368
JH		 5566 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
5567 netdev_info(bp->dev, "Receive PF driver unload event!");
c0c050c5
MC		 5568}
5569
5570#else
5571
5572static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5573{
5574}
5575
5576#endif /* CONFIG_RFS_ACCEL */
5577
5578static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5579 __be16 port)
5580{
5581 struct bnxt *bp = netdev_priv(dev);
5582
5583 if (!netif_running(dev))
5584 return;
5585
5586 if (sa_family != AF_INET6 && sa_family != AF_INET)
5587 return;
5588
5589 if (bp->vxlan_port_cnt && bp->vxlan_port != port)
5590 return;
5591
5592 bp->vxlan_port_cnt++;
5593 if (bp->vxlan_port_cnt == 1) {
5594 bp->vxlan_port = port;
5595 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
5596 schedule_work(&bp->sp_task);
5597 }
5598}
5599
5600static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5601 __be16 port)
5602{
5603 struct bnxt *bp = netdev_priv(dev);
5604
5605 if (!netif_running(dev))
5606 return;
5607
5608 if (sa_family != AF_INET6 && sa_family != AF_INET)
5609 return;
5610
5611 if (bp->vxlan_port_cnt && bp->vxlan_port == port) {
5612 bp->vxlan_port_cnt--;
5613
5614 if (bp->vxlan_port_cnt == 0) {
5615 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
5616 schedule_work(&bp->sp_task);
5617 }
5618 }
5619}
5620
5621static const struct net_device_ops bnxt_netdev_ops = {
5622 .ndo_open = bnxt_open,
5623 .ndo_start_xmit = bnxt_start_xmit,
5624 .ndo_stop = bnxt_close,
5625 .ndo_get_stats64 = bnxt_get_stats64,
5626 .ndo_set_rx_mode = bnxt_set_rx_mode,
5627 .ndo_do_ioctl = bnxt_ioctl,
5628 .ndo_validate_addr = eth_validate_addr,
5629 .ndo_set_mac_address = bnxt_change_mac_addr,
5630 .ndo_change_mtu = bnxt_change_mtu,
5631 .ndo_fix_features = bnxt_fix_features,
5632 .ndo_set_features = bnxt_set_features,
5633 .ndo_tx_timeout = bnxt_tx_timeout,
5634#ifdef CONFIG_BNXT_SRIOV
5635 .ndo_get_vf_config = bnxt_get_vf_config,
5636 .ndo_set_vf_mac = bnxt_set_vf_mac,
5637 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
5638 .ndo_set_vf_rate = bnxt_set_vf_bw,
5639 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
5640 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
5641#endif
5642#ifdef CONFIG_NET_POLL_CONTROLLER
5643 .ndo_poll_controller = bnxt_poll_controller,
5644#endif
5645 .ndo_setup_tc = bnxt_setup_tc,
5646#ifdef CONFIG_RFS_ACCEL
5647 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
5648#endif
5649 .ndo_add_vxlan_port = bnxt_add_vxlan_port,
5650 .ndo_del_vxlan_port = bnxt_del_vxlan_port,
5651#ifdef CONFIG_NET_RX_BUSY_POLL
5652 .ndo_busy_poll = bnxt_busy_poll,
5653#endif
5654};
5655
5656static void bnxt_remove_one(struct pci_dev *pdev)
5657{
5658 struct net_device *dev = pci_get_drvdata(pdev);
5659 struct bnxt *bp = netdev_priv(dev);
5660
5661 if (BNXT_PF(bp))
5662 bnxt_sriov_disable(bp);
5663
5664 unregister_netdev(dev);
5665 cancel_work_sync(&bp->sp_task);
5666 bp->sp_event = 0;
5667
be58a0da 5668 bnxt_hwrm_func_drv_unrgtr(bp);
c0c050c5
MC		 5669 bnxt_free_hwrm_resources(bp);
5670 pci_iounmap(pdev, bp->bar2);
5671 pci_iounmap(pdev, bp->bar1);
5672 pci_iounmap(pdev, bp->bar0);
5673 free_netdev(dev);
5674
5675 pci_release_regions(pdev);
5676 pci_disable_device(pdev);
5677}
5678
5679static int bnxt_probe_phy(struct bnxt *bp)
5680{
5681 int rc = 0;
5682 struct bnxt_link_info *link_info = &bp->link_info;
5683 char phy_ver[PHY_VER_STR_LEN];
5684
5685 rc = bnxt_update_link(bp, false);
5686 if (rc) {
5687 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
5688 rc);
5689 return rc;
5690 }
5691
5692 /*initialize the ethool setting copy with NVM settings */
0d8abf02
MC		 5693 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
5694 link_info->autoneg = BNXT_AUTONEG_SPEED |
5695 BNXT_AUTONEG_FLOW_CTRL;
5696 link_info->advertising = link_info->auto_link_speeds;
c0c050c5 5697 link_info->req_flow_ctrl = link_info->auto_pause_setting;
0d8abf02
MC		 5698 } else {
5699 link_info->req_link_speed = link_info->force_link_speed;
5700 link_info->req_duplex = link_info->duplex_setting;
c0c050c5
MC		 5701 link_info->req_flow_ctrl = link_info->force_pause_setting;
5702 }
c0c050c5
MC		 5703 snprintf(phy_ver, PHY_VER_STR_LEN, " ph %d.%d.%d",
5704 link_info->phy_ver[0],
5705 link_info->phy_ver[1],
5706 link_info->phy_ver[2]);
5707 strcat(bp->fw_ver_str, phy_ver);
5708 return rc;
5709}
5710
5711static int bnxt_get_max_irq(struct pci_dev *pdev)
5712{
5713 u16 ctrl;
5714
5715 if (!pdev->msix_cap)
5716 return 1;
5717
5718 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
5719 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
5720}
5721
6e6c5a57
MC		 5722static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
5723 int *max_cp)
c0c050c5 5724{
6e6c5a57 5725 int max_ring_grps = 0;
c0c050c5 5726
379a80a1 5727#ifdef CONFIG_BNXT_SRIOV
415b6f19 5728 if (!BNXT_PF(bp)) {
c0c050c5
MC		 5729 *max_tx = bp->vf.max_tx_rings;
5730 *max_rx = bp->vf.max_rx_rings;
6e6c5a57
MC		 5731 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
5732 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
b72d4a68 5733 max_ring_grps = bp->vf.max_hw_ring_grps;
415b6f19 5734 } else
379a80a1 5735#endif
415b6f19
AB		 5736 {
5737 *max_tx = bp->pf.max_tx_rings;
5738 *max_rx = bp->pf.max_rx_rings;
5739 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5740 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
5741 max_ring_grps = bp->pf.max_hw_ring_grps;
c0c050c5 5742 }
415b6f19 5743
c0c050c5
MC		 5744 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5745 *max_rx >>= 1;
b72d4a68 5746 *max_rx = min_t(int, *max_rx, max_ring_grps);
6e6c5a57
MC		 5747}
5748
5749int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
5750{
5751 int rx, tx, cp;
5752
5753 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
5754 if (!rx || !tx || !cp)
5755 return -ENOMEM;
5756
5757 *max_rx = rx;
5758 *max_tx = tx;
5759 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
5760}
5761
5762static int bnxt_set_dflt_rings(struct bnxt *bp)
5763{
5764 int dflt_rings, max_rx_rings, max_tx_rings, rc;
5765 bool sh = true;
5766
5767 if (sh)
5768 bp->flags |= BNXT_FLAG_SHARED_RINGS;
5769 dflt_rings = netif_get_num_default_rss_queues();
5770 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
5771 if (rc)
5772 return rc;
5773 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
5774 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
5775 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5776 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5777 bp->tx_nr_rings + bp->rx_nr_rings;
5778 bp->num_stat_ctxs = bp->cp_nr_rings;
5779 return rc;
c0c050c5
MC		 5780}
5781
5782static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5783{
5784 static int version_printed;
5785 struct net_device *dev;
5786 struct bnxt *bp;
6e6c5a57 5787 int rc, max_irqs;
c0c050c5
MC		 5788
5789 if (version_printed++ == 0)
5790 pr_info("%s", version);
5791
5792 max_irqs = bnxt_get_max_irq(pdev);
5793 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
5794 if (!dev)
5795 return -ENOMEM;
5796
5797 bp = netdev_priv(dev);
5798
5799 if (bnxt_vf_pciid(ent->driver_data))
5800 bp->flags |= BNXT_FLAG_VF;
5801
2bcfa6f6 5802 if (pdev->msix_cap)
c0c050c5 5803 bp->flags |= BNXT_FLAG_MSIX_CAP;
c0c050c5
MC		 5804
5805 rc = bnxt_init_board(pdev, dev);
5806 if (rc < 0)
5807 goto init_err_free;
5808
5809 dev->netdev_ops = &bnxt_netdev_ops;
5810 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
5811 dev->ethtool_ops = &bnxt_ethtool_ops;
5812
5813 pci_set_drvdata(pdev, dev);
5814
5815 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5816 NETIF_F_TSO | NETIF_F_TSO6 |
5817 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5818 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT |
5819 NETIF_F_RXHASH |
5820 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
5821
c0c050c5
MC		 5822 dev->hw_enc_features =
5823 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5824 NETIF_F_TSO | NETIF_F_TSO6 |
5825 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5826 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
5827 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
5828 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
5829 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
5830 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
5831 dev->priv_flags |= IFF_UNICAST_FLT;
5832
5833#ifdef CONFIG_BNXT_SRIOV
5834 init_waitqueue_head(&bp->sriov_cfg_wait);
5835#endif
5836 rc = bnxt_alloc_hwrm_resources(bp);
5837 if (rc)
5838 goto init_err;
5839
5840 mutex_init(&bp->hwrm_cmd_lock);
5841 bnxt_hwrm_ver_get(bp);
5842
5843 rc = bnxt_hwrm_func_drv_rgtr(bp);
5844 if (rc)
5845 goto init_err;
5846
5847 /* Get the MAX capabilities for this function */
5848 rc = bnxt_hwrm_func_qcaps(bp);
5849 if (rc) {
5850 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
5851 rc);
5852 rc = -1;
5853 goto init_err;
5854 }
5855
5856 rc = bnxt_hwrm_queue_qportcfg(bp);
5857 if (rc) {
5858 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
5859 rc);
5860 rc = -1;
5861 goto init_err;
5862 }
5863
5864 bnxt_set_tpa_flags(bp);
5865 bnxt_set_ring_params(bp);
bdd4347b 5866 if (BNXT_PF(bp))
c0c050c5 5867 bp->pf.max_irqs = max_irqs;
379a80a1 5868#if defined(CONFIG_BNXT_SRIOV)
bdd4347b 5869 else
c0c050c5 5870 bp->vf.max_irqs = max_irqs;
379a80a1 5871#endif
6e6c5a57 5872 bnxt_set_dflt_rings(bp);
c0c050c5 5873
2bcfa6f6
MC		 5874 if (BNXT_PF(bp)) {
5875 dev->hw_features |= NETIF_F_NTUPLE;
5876 if (bnxt_rfs_capable(bp)) {
5877 bp->flags |= BNXT_FLAG_RFS;
5878 dev->features |= NETIF_F_NTUPLE;
5879 }
5880 }
5881
c0c050c5
MC		 5882 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
5883 bp->flags |= BNXT_FLAG_STRIP_VLAN;
5884
5885 rc = bnxt_probe_phy(bp);
5886 if (rc)
5887 goto init_err;
5888
5889 rc = register_netdev(dev);
5890 if (rc)
5891 goto init_err;
5892
5893 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
5894 board_info[ent->driver_data].name,
5895 (long)pci_resource_start(pdev, 0), dev->dev_addr);
5896
5897 return 0;
5898
5899init_err:
5900 pci_iounmap(pdev, bp->bar0);
5901 pci_release_regions(pdev);
5902 pci_disable_device(pdev);
5903
5904init_err_free:
5905 free_netdev(dev);
5906 return rc;
5907}
5908
5909static struct pci_driver bnxt_pci_driver = {
5910 .name = DRV_MODULE_NAME,
5911 .id_table = bnxt_pci_tbl,
5912 .probe = bnxt_init_one,
5913 .remove = bnxt_remove_one,
5914#if defined(CONFIG_BNXT_SRIOV)
5915 .sriov_configure = bnxt_sriov_configure,
5916#endif
5917};
5918
5919module_pci_driver(bnxt_pci_driver);
Linux kernel - Deliverables
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