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bnxt_en: Fixed incorrect implementation of ndo_set_mac_address
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
CommitLineData
c0c050c5
MC		 1/* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2015 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11
12#include <linux/stringify.h>
13#include <linux/kernel.h>
14#include <linux/timer.h>
15#include <linux/errno.h>
16#include <linux/ioport.h>
17#include <linux/slab.h>
18#include <linux/vmalloc.h>
19#include <linux/interrupt.h>
20#include <linux/pci.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/dma-mapping.h>
25#include <linux/bitops.h>
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/delay.h>
29#include <asm/byteorder.h>
30#include <asm/page.h>
31#include <linux/time.h>
32#include <linux/mii.h>
33#include <linux/if.h>
34#include <linux/if_vlan.h>
35#include <net/ip.h>
36#include <net/tcp.h>
37#include <net/udp.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41#include <net/vxlan.h>
42#endif
43#ifdef CONFIG_NET_RX_BUSY_POLL
44#include <net/busy_poll.h>
45#endif
46#include <linux/workqueue.h>
47#include <linux/prefetch.h>
48#include <linux/cache.h>
49#include <linux/log2.h>
50#include <linux/aer.h>
51#include <linux/bitmap.h>
52#include <linux/cpu_rmap.h>
53
54#include "bnxt_hsi.h"
55#include "bnxt.h"
56#include "bnxt_sriov.h"
57#include "bnxt_ethtool.h"
58
59#define BNXT_TX_TIMEOUT (5 * HZ)
60
61static const char version[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
63
64MODULE_LICENSE("GPL");
65MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66MODULE_VERSION(DRV_MODULE_VERSION);
67
68#define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69#define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70#define BNXT_RX_COPY_THRESH 256
71
72#define BNXT_TX_PUSH_THRESH 92
73
74enum board_idx {
75 BCM57302,
76 BCM57304,
77 BCM57404,
78 BCM57406,
79 BCM57304_VF,
80 BCM57404_VF,
81};
82
83/* indexed by enum above */
84static const struct {
85 char *name;
86} board_info[] = {
87 { "Broadcom BCM57302 NetXtreme-C Single-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
88 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
89 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
90 { "Broadcom BCM57406 NetXtreme-E Dual-port 10Gb Ethernet" },
91 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
92 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
93};
94
95static const struct pci_device_id bnxt_pci_tbl[] = {
96 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
97 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
98 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
99 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
100#ifdef CONFIG_BNXT_SRIOV
101 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
102 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
103#endif
104 { 0 }
105};
106
107MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
108
109static const u16 bnxt_vf_req_snif[] = {
110 HWRM_FUNC_CFG,
111 HWRM_PORT_PHY_QCFG,
112 HWRM_CFA_L2_FILTER_ALLOC,
113};
114
115static bool bnxt_vf_pciid(enum board_idx idx)
116{
117 return (idx == BCM57304_VF || idx == BCM57404_VF);
118}
119
120#define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
121#define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
122#define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
123
124#define BNXT_CP_DB_REARM(db, raw_cons) \
125 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
126
127#define BNXT_CP_DB(db, raw_cons) \
128 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
129
130#define BNXT_CP_DB_IRQ_DIS(db) \
131 writel(DB_CP_IRQ_DIS_FLAGS, db)
132
133static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
134{
135 /* Tell compiler to fetch tx indices from memory. */
136 barrier();
137
138 return bp->tx_ring_size -
139 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
140}
141
142static const u16 bnxt_lhint_arr[] = {
143 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
144 TX_BD_FLAGS_LHINT_512_TO_1023,
145 TX_BD_FLAGS_LHINT_1024_TO_2047,
146 TX_BD_FLAGS_LHINT_1024_TO_2047,
147 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
148 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
149 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
150 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
151 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
152 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
153 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
154 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
155 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
156 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
157 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
158 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
159 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
160 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
161 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
162};
163
164static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
165{
166 struct bnxt *bp = netdev_priv(dev);
167 struct tx_bd *txbd;
168 struct tx_bd_ext *txbd1;
169 struct netdev_queue *txq;
170 int i;
171 dma_addr_t mapping;
172 unsigned int length, pad = 0;
173 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
174 u16 prod, last_frag;
175 struct pci_dev *pdev = bp->pdev;
176 struct bnxt_napi *bnapi;
177 struct bnxt_tx_ring_info *txr;
178 struct bnxt_sw_tx_bd *tx_buf;
179
180 i = skb_get_queue_mapping(skb);
181 if (unlikely(i >= bp->tx_nr_rings)) {
182 dev_kfree_skb_any(skb);
183 return NETDEV_TX_OK;
184 }
185
186 bnapi = bp->bnapi[i];
187 txr = &bnapi->tx_ring;
188 txq = netdev_get_tx_queue(dev, i);
189 prod = txr->tx_prod;
190
191 free_size = bnxt_tx_avail(bp, txr);
192 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
193 netif_tx_stop_queue(txq);
194 return NETDEV_TX_BUSY;
195 }
196
197 length = skb->len;
198 len = skb_headlen(skb);
199 last_frag = skb_shinfo(skb)->nr_frags;
200
201 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
202
203 txbd->tx_bd_opaque = prod;
204
205 tx_buf = &txr->tx_buf_ring[prod];
206 tx_buf->skb = skb;
207 tx_buf->nr_frags = last_frag;
208
209 vlan_tag_flags = 0;
210 cfa_action = 0;
211 if (skb_vlan_tag_present(skb)) {
212 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
213 skb_vlan_tag_get(skb);
214 /* Currently supports 8021Q, 8021AD vlan offloads
215 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
216 */
217 if (skb->vlan_proto == htons(ETH_P_8021Q))
218 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
219 }
220
221 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
222 struct tx_push_bd *push = txr->tx_push;
223 struct tx_bd *tx_push = &push->txbd1;
224 struct tx_bd_ext *tx_push1 = &push->txbd2;
225 void *pdata = tx_push1 + 1;
226 int j;
227
228 /* Set COAL_NOW to be ready quickly for the next push */
229 tx_push->tx_bd_len_flags_type =
230 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
231 TX_BD_TYPE_LONG_TX_BD |
232 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
233 TX_BD_FLAGS_COAL_NOW |
234 TX_BD_FLAGS_PACKET_END |
235 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
236
237 if (skb->ip_summed == CHECKSUM_PARTIAL)
238 tx_push1->tx_bd_hsize_lflags =
239 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
240 else
241 tx_push1->tx_bd_hsize_lflags = 0;
242
243 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
244 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
245
246 skb_copy_from_linear_data(skb, pdata, len);
247 pdata += len;
248 for (j = 0; j < last_frag; j++) {
249 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
250 void *fptr;
251
252 fptr = skb_frag_address_safe(frag);
253 if (!fptr)
254 goto normal_tx;
255
256 memcpy(pdata, fptr, skb_frag_size(frag));
257 pdata += skb_frag_size(frag);
258 }
259
260 memcpy(txbd, tx_push, sizeof(*txbd));
261 prod = NEXT_TX(prod);
262 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
263 memcpy(txbd, tx_push1, sizeof(*txbd));
264 prod = NEXT_TX(prod);
265 push->doorbell =
266 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
267 txr->tx_prod = prod;
268
269 netdev_tx_sent_queue(txq, skb->len);
270
271 __iowrite64_copy(txr->tx_doorbell, push,
272 (length + sizeof(*push) + 8) / 8);
273
274 tx_buf->is_push = 1;
275
276 goto tx_done;
277 }
278
279normal_tx:
280 if (length < BNXT_MIN_PKT_SIZE) {
281 pad = BNXT_MIN_PKT_SIZE - length;
282 if (skb_pad(skb, pad)) {
283 /* SKB already freed. */
284 tx_buf->skb = NULL;
285 return NETDEV_TX_OK;
286 }
287 length = BNXT_MIN_PKT_SIZE;
288 }
289
290 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
291
292 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
293 dev_kfree_skb_any(skb);
294 tx_buf->skb = NULL;
295 return NETDEV_TX_OK;
296 }
297
298 dma_unmap_addr_set(tx_buf, mapping, mapping);
299 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
300 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
301
302 txbd->tx_bd_haddr = cpu_to_le64(mapping);
303
304 prod = NEXT_TX(prod);
305 txbd1 = (struct tx_bd_ext *)
306 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
307
308 txbd1->tx_bd_hsize_lflags = 0;
309 if (skb_is_gso(skb)) {
310 u32 hdr_len;
311
312 if (skb->encapsulation)
313 hdr_len = skb_inner_network_offset(skb) +
314 skb_inner_network_header_len(skb) +
315 inner_tcp_hdrlen(skb);
316 else
317 hdr_len = skb_transport_offset(skb) +
318 tcp_hdrlen(skb);
319
320 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
321 TX_BD_FLAGS_T_IPID |
322 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
323 length = skb_shinfo(skb)->gso_size;
324 txbd1->tx_bd_mss = cpu_to_le32(length);
325 length += hdr_len;
326 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
327 txbd1->tx_bd_hsize_lflags =
328 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
329 txbd1->tx_bd_mss = 0;
330 }
331
332 length >>= 9;
333 flags |= bnxt_lhint_arr[length];
334 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
335
336 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
337 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
338 for (i = 0; i < last_frag; i++) {
339 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
340
341 prod = NEXT_TX(prod);
342 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
343
344 len = skb_frag_size(frag);
345 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
346 DMA_TO_DEVICE);
347
348 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
349 goto tx_dma_error;
350
351 tx_buf = &txr->tx_buf_ring[prod];
352 dma_unmap_addr_set(tx_buf, mapping, mapping);
353
354 txbd->tx_bd_haddr = cpu_to_le64(mapping);
355
356 flags = len << TX_BD_LEN_SHIFT;
357 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
358 }
359
360 flags &= ~TX_BD_LEN;
361 txbd->tx_bd_len_flags_type =
362 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
363 TX_BD_FLAGS_PACKET_END);
364
365 netdev_tx_sent_queue(txq, skb->len);
366
367 /* Sync BD data before updating doorbell */
368 wmb();
369
370 prod = NEXT_TX(prod);
371 txr->tx_prod = prod;
372
373 writel(DB_KEY_TX | prod, txr->tx_doorbell);
374 writel(DB_KEY_TX | prod, txr->tx_doorbell);
375
376tx_done:
377
378 mmiowb();
379
380 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
381 netif_tx_stop_queue(txq);
382
383 /* netif_tx_stop_queue() must be done before checking
384 * tx index in bnxt_tx_avail() below, because in
385 * bnxt_tx_int(), we update tx index before checking for
386 * netif_tx_queue_stopped().
387 */
388 smp_mb();
389 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
390 netif_tx_wake_queue(txq);
391 }
392 return NETDEV_TX_OK;
393
394tx_dma_error:
395 last_frag = i;
396
397 /* start back at beginning and unmap skb */
398 prod = txr->tx_prod;
399 tx_buf = &txr->tx_buf_ring[prod];
400 tx_buf->skb = NULL;
401 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
402 skb_headlen(skb), PCI_DMA_TODEVICE);
403 prod = NEXT_TX(prod);
404
405 /* unmap remaining mapped pages */
406 for (i = 0; i < last_frag; i++) {
407 prod = NEXT_TX(prod);
408 tx_buf = &txr->tx_buf_ring[prod];
409 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
410 skb_frag_size(&skb_shinfo(skb)->frags[i]),
411 PCI_DMA_TODEVICE);
412 }
413
414 dev_kfree_skb_any(skb);
415 return NETDEV_TX_OK;
416}
417
418static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
419{
420 struct bnxt_tx_ring_info *txr = &bnapi->tx_ring;
421 int index = bnapi->index;
422 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
423 u16 cons = txr->tx_cons;
424 struct pci_dev *pdev = bp->pdev;
425 int i;
426 unsigned int tx_bytes = 0;
427
428 for (i = 0; i < nr_pkts; i++) {
429 struct bnxt_sw_tx_bd *tx_buf;
430 struct sk_buff *skb;
431 int j, last;
432
433 tx_buf = &txr->tx_buf_ring[cons];
434 cons = NEXT_TX(cons);
435 skb = tx_buf->skb;
436 tx_buf->skb = NULL;
437
438 if (tx_buf->is_push) {
439 tx_buf->is_push = 0;
440 goto next_tx_int;
441 }
442
443 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
444 skb_headlen(skb), PCI_DMA_TODEVICE);
445 last = tx_buf->nr_frags;
446
447 for (j = 0; j < last; j++) {
448 cons = NEXT_TX(cons);
449 tx_buf = &txr->tx_buf_ring[cons];
450 dma_unmap_page(
451 &pdev->dev,
452 dma_unmap_addr(tx_buf, mapping),
453 skb_frag_size(&skb_shinfo(skb)->frags[j]),
454 PCI_DMA_TODEVICE);
455 }
456
457next_tx_int:
458 cons = NEXT_TX(cons);
459
460 tx_bytes += skb->len;
461 dev_kfree_skb_any(skb);
462 }
463
464 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
465 txr->tx_cons = cons;
466
467 /* Need to make the tx_cons update visible to bnxt_start_xmit()
468 * before checking for netif_tx_queue_stopped(). Without the
469 * memory barrier, there is a small possibility that bnxt_start_xmit()
470 * will miss it and cause the queue to be stopped forever.
471 */
472 smp_mb();
473
474 if (unlikely(netif_tx_queue_stopped(txq)) &&
475 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
476 __netif_tx_lock(txq, smp_processor_id());
477 if (netif_tx_queue_stopped(txq) &&
478 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
479 txr->dev_state != BNXT_DEV_STATE_CLOSING)
480 netif_tx_wake_queue(txq);
481 __netif_tx_unlock(txq);
482 }
483}
484
485static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
486 gfp_t gfp)
487{
488 u8 *data;
489 struct pci_dev *pdev = bp->pdev;
490
491 data = kmalloc(bp->rx_buf_size, gfp);
492 if (!data)
493 return NULL;
494
495 *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
496 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
497
498 if (dma_mapping_error(&pdev->dev, *mapping)) {
499 kfree(data);
500 data = NULL;
501 }
502 return data;
503}
504
505static inline int bnxt_alloc_rx_data(struct bnxt *bp,
506 struct bnxt_rx_ring_info *rxr,
507 u16 prod, gfp_t gfp)
508{
509 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
510 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
511 u8 *data;
512 dma_addr_t mapping;
513
514 data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
515 if (!data)
516 return -ENOMEM;
517
518 rx_buf->data = data;
519 dma_unmap_addr_set(rx_buf, mapping, mapping);
520
521 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
522
523 return 0;
524}
525
526static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
527 u8 *data)
528{
529 u16 prod = rxr->rx_prod;
530 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
531 struct rx_bd *cons_bd, *prod_bd;
532
533 prod_rx_buf = &rxr->rx_buf_ring[prod];
534 cons_rx_buf = &rxr->rx_buf_ring[cons];
535
536 prod_rx_buf->data = data;
537
538 dma_unmap_addr_set(prod_rx_buf, mapping,
539 dma_unmap_addr(cons_rx_buf, mapping));
540
541 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
542 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
543
544 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
545}
546
547static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
548{
549 u16 next, max = rxr->rx_agg_bmap_size;
550
551 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
552 if (next >= max)
553 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
554 return next;
555}
556
557static inline int bnxt_alloc_rx_page(struct bnxt *bp,
558 struct bnxt_rx_ring_info *rxr,
559 u16 prod, gfp_t gfp)
560{
561 struct rx_bd *rxbd =
562 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
563 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
564 struct pci_dev *pdev = bp->pdev;
565 struct page *page;
566 dma_addr_t mapping;
567 u16 sw_prod = rxr->rx_sw_agg_prod;
568
569 page = alloc_page(gfp);
570 if (!page)
571 return -ENOMEM;
572
573 mapping = dma_map_page(&pdev->dev, page, 0, PAGE_SIZE,
574 PCI_DMA_FROMDEVICE);
575 if (dma_mapping_error(&pdev->dev, mapping)) {
576 __free_page(page);
577 return -EIO;
578 }
579
580 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
581 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
582
583 __set_bit(sw_prod, rxr->rx_agg_bmap);
584 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
585 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
586
587 rx_agg_buf->page = page;
588 rx_agg_buf->mapping = mapping;
589 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
590 rxbd->rx_bd_opaque = sw_prod;
591 return 0;
592}
593
594static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
595 u32 agg_bufs)
596{
597 struct bnxt *bp = bnapi->bp;
598 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
599 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
600 u16 prod = rxr->rx_agg_prod;
601 u16 sw_prod = rxr->rx_sw_agg_prod;
602 u32 i;
603
604 for (i = 0; i < agg_bufs; i++) {
605 u16 cons;
606 struct rx_agg_cmp *agg;
607 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
608 struct rx_bd *prod_bd;
609 struct page *page;
610
611 agg = (struct rx_agg_cmp *)
612 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
613 cons = agg->rx_agg_cmp_opaque;
614 __clear_bit(cons, rxr->rx_agg_bmap);
615
616 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
617 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
618
619 __set_bit(sw_prod, rxr->rx_agg_bmap);
620 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
621 cons_rx_buf = &rxr->rx_agg_ring[cons];
622
623 /* It is possible for sw_prod to be equal to cons, so
624 * set cons_rx_buf->page to NULL first.
625 */
626 page = cons_rx_buf->page;
627 cons_rx_buf->page = NULL;
628 prod_rx_buf->page = page;
629
630 prod_rx_buf->mapping = cons_rx_buf->mapping;
631
632 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
633
634 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
635 prod_bd->rx_bd_opaque = sw_prod;
636
637 prod = NEXT_RX_AGG(prod);
638 sw_prod = NEXT_RX_AGG(sw_prod);
639 cp_cons = NEXT_CMP(cp_cons);
640 }
641 rxr->rx_agg_prod = prod;
642 rxr->rx_sw_agg_prod = sw_prod;
643}
644
645static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
646 struct bnxt_rx_ring_info *rxr, u16 cons,
647 u16 prod, u8 *data, dma_addr_t dma_addr,
648 unsigned int len)
649{
650 int err;
651 struct sk_buff *skb;
652
653 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
654 if (unlikely(err)) {
655 bnxt_reuse_rx_data(rxr, cons, data);
656 return NULL;
657 }
658
659 skb = build_skb(data, 0);
660 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
661 PCI_DMA_FROMDEVICE);
662 if (!skb) {
663 kfree(data);
664 return NULL;
665 }
666
667 skb_reserve(skb, BNXT_RX_OFFSET);
668 skb_put(skb, len);
669 return skb;
670}
671
672static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
673 struct sk_buff *skb, u16 cp_cons,
674 u32 agg_bufs)
675{
676 struct pci_dev *pdev = bp->pdev;
677 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
678 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
679 u16 prod = rxr->rx_agg_prod;
680 u32 i;
681
682 for (i = 0; i < agg_bufs; i++) {
683 u16 cons, frag_len;
684 struct rx_agg_cmp *agg;
685 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
686 struct page *page;
687 dma_addr_t mapping;
688
689 agg = (struct rx_agg_cmp *)
690 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
691 cons = agg->rx_agg_cmp_opaque;
692 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
693 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
694
695 cons_rx_buf = &rxr->rx_agg_ring[cons];
696 skb_fill_page_desc(skb, i, cons_rx_buf->page, 0, frag_len);
697 __clear_bit(cons, rxr->rx_agg_bmap);
698
699 /* It is possible for bnxt_alloc_rx_page() to allocate
700 * a sw_prod index that equals the cons index, so we
701 * need to clear the cons entry now.
702 */
703 mapping = dma_unmap_addr(cons_rx_buf, mapping);
704 page = cons_rx_buf->page;
705 cons_rx_buf->page = NULL;
706
707 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
708 struct skb_shared_info *shinfo;
709 unsigned int nr_frags;
710
711 shinfo = skb_shinfo(skb);
712 nr_frags = --shinfo->nr_frags;
713 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
714
715 dev_kfree_skb(skb);
716
717 cons_rx_buf->page = page;
718
719 /* Update prod since possibly some pages have been
720 * allocated already.
721 */
722 rxr->rx_agg_prod = prod;
723 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
724 return NULL;
725 }
726
727 dma_unmap_page(&pdev->dev, mapping, PAGE_SIZE,
728 PCI_DMA_FROMDEVICE);
729
730 skb->data_len += frag_len;
731 skb->len += frag_len;
732 skb->truesize += PAGE_SIZE;
733
734 prod = NEXT_RX_AGG(prod);
735 cp_cons = NEXT_CMP(cp_cons);
736 }
737 rxr->rx_agg_prod = prod;
738 return skb;
739}
740
741static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
742 u8 agg_bufs, u32 *raw_cons)
743{
744 u16 last;
745 struct rx_agg_cmp *agg;
746
747 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
748 last = RING_CMP(*raw_cons);
749 agg = (struct rx_agg_cmp *)
750 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
751 return RX_AGG_CMP_VALID(agg, *raw_cons);
752}
753
754static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
755 unsigned int len,
756 dma_addr_t mapping)
757{
758 struct bnxt *bp = bnapi->bp;
759 struct pci_dev *pdev = bp->pdev;
760 struct sk_buff *skb;
761
762 skb = napi_alloc_skb(&bnapi->napi, len);
763 if (!skb)
764 return NULL;
765
766 dma_sync_single_for_cpu(&pdev->dev, mapping,
767 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
768
769 memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
770
771 dma_sync_single_for_device(&pdev->dev, mapping,
772 bp->rx_copy_thresh,
773 PCI_DMA_FROMDEVICE);
774
775 skb_put(skb, len);
776 return skb;
777}
778
779static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
780 struct rx_tpa_start_cmp *tpa_start,
781 struct rx_tpa_start_cmp_ext *tpa_start1)
782{
783 u8 agg_id = TPA_START_AGG_ID(tpa_start);
784 u16 cons, prod;
785 struct bnxt_tpa_info *tpa_info;
786 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
787 struct rx_bd *prod_bd;
788 dma_addr_t mapping;
789
790 cons = tpa_start->rx_tpa_start_cmp_opaque;
791 prod = rxr->rx_prod;
792 cons_rx_buf = &rxr->rx_buf_ring[cons];
793 prod_rx_buf = &rxr->rx_buf_ring[prod];
794 tpa_info = &rxr->rx_tpa[agg_id];
795
796 prod_rx_buf->data = tpa_info->data;
797
798 mapping = tpa_info->mapping;
799 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
800
801 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
802
803 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
804
805 tpa_info->data = cons_rx_buf->data;
806 cons_rx_buf->data = NULL;
807 tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
808
809 tpa_info->len =
810 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
811 RX_TPA_START_CMP_LEN_SHIFT;
812 if (likely(TPA_START_HASH_VALID(tpa_start))) {
813 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
814
815 tpa_info->hash_type = PKT_HASH_TYPE_L4;
816 tpa_info->gso_type = SKB_GSO_TCPV4;
817 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
818 if (hash_type == 3)
819 tpa_info->gso_type = SKB_GSO_TCPV6;
820 tpa_info->rss_hash =
821 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
822 } else {
823 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
824 tpa_info->gso_type = 0;
825 if (netif_msg_rx_err(bp))
826 netdev_warn(bp->dev, "TPA packet without valid hash\n");
827 }
828 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
829 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
830
831 rxr->rx_prod = NEXT_RX(prod);
832 cons = NEXT_RX(cons);
833 cons_rx_buf = &rxr->rx_buf_ring[cons];
834
835 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
836 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
837 cons_rx_buf->data = NULL;
838}
839
840static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
841 u16 cp_cons, u32 agg_bufs)
842{
843 if (agg_bufs)
844 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
845}
846
847#define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
848#define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
849
850static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info,
851 struct rx_tpa_end_cmp *tpa_end,
852 struct rx_tpa_end_cmp_ext *tpa_end1,
853 struct sk_buff *skb)
854{
d1611c3a 855#ifdef CONFIG_INET
c0c050c5
MC		 856 struct tcphdr *th;
857 int payload_off, tcp_opt_len = 0;
858 int len, nw_off;
859
860 NAPI_GRO_CB(skb)->count = TPA_END_TPA_SEGS(tpa_end);
861 skb_shinfo(skb)->gso_size =
862 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
863 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
864 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
865 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
866 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
867 if (TPA_END_GRO_TS(tpa_end))
868 tcp_opt_len = 12;
869
c0c050c5
MC		 870 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
871 struct iphdr *iph;
872
873 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
874 ETH_HLEN;
875 skb_set_network_header(skb, nw_off);
876 iph = ip_hdr(skb);
877 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
878 len = skb->len - skb_transport_offset(skb);
879 th = tcp_hdr(skb);
880 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
881 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
882 struct ipv6hdr *iph;
883
884 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
885 ETH_HLEN;
886 skb_set_network_header(skb, nw_off);
887 iph = ipv6_hdr(skb);
888 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
889 len = skb->len - skb_transport_offset(skb);
890 th = tcp_hdr(skb);
891 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
892 } else {
893 dev_kfree_skb_any(skb);
894 return NULL;
895 }
896 tcp_gro_complete(skb);
897
898 if (nw_off) { /* tunnel */
899 struct udphdr *uh = NULL;
900
901 if (skb->protocol == htons(ETH_P_IP)) {
902 struct iphdr *iph = (struct iphdr *)skb->data;
903
904 if (iph->protocol == IPPROTO_UDP)
905 uh = (struct udphdr *)(iph + 1);
906 } else {
907 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
908
909 if (iph->nexthdr == IPPROTO_UDP)
910 uh = (struct udphdr *)(iph + 1);
911 }
912 if (uh) {
913 if (uh->check)
914 skb_shinfo(skb)->gso_type |=
915 SKB_GSO_UDP_TUNNEL_CSUM;
916 else
917 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
918 }
919 }
920#endif
921 return skb;
922}
923
924static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
925 struct bnxt_napi *bnapi,
926 u32 *raw_cons,
927 struct rx_tpa_end_cmp *tpa_end,
928 struct rx_tpa_end_cmp_ext *tpa_end1,
929 bool *agg_event)
930{
931 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
932 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
933 u8 agg_id = TPA_END_AGG_ID(tpa_end);
934 u8 *data, agg_bufs;
935 u16 cp_cons = RING_CMP(*raw_cons);
936 unsigned int len;
937 struct bnxt_tpa_info *tpa_info;
938 dma_addr_t mapping;
939 struct sk_buff *skb;
940
941 tpa_info = &rxr->rx_tpa[agg_id];
942 data = tpa_info->data;
943 prefetch(data);
944 len = tpa_info->len;
945 mapping = tpa_info->mapping;
946
947 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
948 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
949
950 if (agg_bufs) {
951 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
952 return ERR_PTR(-EBUSY);
953
954 *agg_event = true;
955 cp_cons = NEXT_CMP(cp_cons);
956 }
957
958 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
959 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
960 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
961 agg_bufs, (int)MAX_SKB_FRAGS);
962 return NULL;
963 }
964
965 if (len <= bp->rx_copy_thresh) {
966 skb = bnxt_copy_skb(bnapi, data, len, mapping);
967 if (!skb) {
968 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
969 return NULL;
970 }
971 } else {
972 u8 *new_data;
973 dma_addr_t new_mapping;
974
975 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
976 if (!new_data) {
977 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
978 return NULL;
979 }
980
981 tpa_info->data = new_data;
982 tpa_info->mapping = new_mapping;
983
984 skb = build_skb(data, 0);
985 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
986 PCI_DMA_FROMDEVICE);
987
988 if (!skb) {
989 kfree(data);
990 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
991 return NULL;
992 }
993 skb_reserve(skb, BNXT_RX_OFFSET);
994 skb_put(skb, len);
995 }
996
997 if (agg_bufs) {
998 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
999 if (!skb) {
1000 /* Page reuse already handled by bnxt_rx_pages(). */
1001 return NULL;
1002 }
1003 }
1004 skb->protocol = eth_type_trans(skb, bp->dev);
1005
1006 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1007 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1008
1009 if (tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) {
1010 netdev_features_t features = skb->dev->features;
1011 u16 vlan_proto = tpa_info->metadata >>
1012 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1013
1014 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1015 vlan_proto == ETH_P_8021Q) ||
1016 ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1017 vlan_proto == ETH_P_8021AD)) {
1018 __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1019 tpa_info->metadata &
1020 RX_CMP_FLAGS2_METADATA_VID_MASK);
1021 }
1022 }
1023
1024 skb_checksum_none_assert(skb);
1025 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1026 skb->ip_summed = CHECKSUM_UNNECESSARY;
1027 skb->csum_level =
1028 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1029 }
1030
1031 if (TPA_END_GRO(tpa_end))
1032 skb = bnxt_gro_skb(tpa_info, tpa_end, tpa_end1, skb);
1033
1034 return skb;
1035}
1036
1037/* returns the following:
1038 * 1 - 1 packet successfully received
1039 * 0 - successful TPA_START, packet not completed yet
1040 * -EBUSY - completion ring does not have all the agg buffers yet
1041 * -ENOMEM - packet aborted due to out of memory
1042 * -EIO - packet aborted due to hw error indicated in BD
1043 */
1044static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1045 bool *agg_event)
1046{
1047 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1048 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
1049 struct net_device *dev = bp->dev;
1050 struct rx_cmp *rxcmp;
1051 struct rx_cmp_ext *rxcmp1;
1052 u32 tmp_raw_cons = *raw_cons;
1053 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1054 struct bnxt_sw_rx_bd *rx_buf;
1055 unsigned int len;
1056 u8 *data, agg_bufs, cmp_type;
1057 dma_addr_t dma_addr;
1058 struct sk_buff *skb;
1059 int rc = 0;
1060
1061 rxcmp = (struct rx_cmp *)
1062 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1063
1064 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1065 cp_cons = RING_CMP(tmp_raw_cons);
1066 rxcmp1 = (struct rx_cmp_ext *)
1067 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1068
1069 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1070 return -EBUSY;
1071
1072 cmp_type = RX_CMP_TYPE(rxcmp);
1073
1074 prod = rxr->rx_prod;
1075
1076 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1077 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1078 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1079
1080 goto next_rx_no_prod;
1081
1082 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1083 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1084 (struct rx_tpa_end_cmp *)rxcmp,
1085 (struct rx_tpa_end_cmp_ext *)rxcmp1,
1086 agg_event);
1087
1088 if (unlikely(IS_ERR(skb)))
1089 return -EBUSY;
1090
1091 rc = -ENOMEM;
1092 if (likely(skb)) {
1093 skb_record_rx_queue(skb, bnapi->index);
1094 skb_mark_napi_id(skb, &bnapi->napi);
1095 if (bnxt_busy_polling(bnapi))
1096 netif_receive_skb(skb);
1097 else
1098 napi_gro_receive(&bnapi->napi, skb);
1099 rc = 1;
1100 }
1101 goto next_rx_no_prod;
1102 }
1103
1104 cons = rxcmp->rx_cmp_opaque;
1105 rx_buf = &rxr->rx_buf_ring[cons];
1106 data = rx_buf->data;
1107 prefetch(data);
1108
1109 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1110 RX_CMP_AGG_BUFS_SHIFT;
1111
1112 if (agg_bufs) {
1113 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1114 return -EBUSY;
1115
1116 cp_cons = NEXT_CMP(cp_cons);
1117 *agg_event = true;
1118 }
1119
1120 rx_buf->data = NULL;
1121 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1122 bnxt_reuse_rx_data(rxr, cons, data);
1123 if (agg_bufs)
1124 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1125
1126 rc = -EIO;
1127 goto next_rx;
1128 }
1129
1130 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1131 dma_addr = dma_unmap_addr(rx_buf, mapping);
1132
1133 if (len <= bp->rx_copy_thresh) {
1134 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1135 bnxt_reuse_rx_data(rxr, cons, data);
1136 if (!skb) {
1137 rc = -ENOMEM;
1138 goto next_rx;
1139 }
1140 } else {
1141 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1142 if (!skb) {
1143 rc = -ENOMEM;
1144 goto next_rx;
1145 }
1146 }
1147
1148 if (agg_bufs) {
1149 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1150 if (!skb) {
1151 rc = -ENOMEM;
1152 goto next_rx;
1153 }
1154 }
1155
1156 if (RX_CMP_HASH_VALID(rxcmp)) {
1157 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1158 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1159
1160 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1161 if (hash_type != 1 && hash_type != 3)
1162 type = PKT_HASH_TYPE_L3;
1163 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1164 }
1165
1166 skb->protocol = eth_type_trans(skb, dev);
1167
1168 if (rxcmp1->rx_cmp_flags2 &
1169 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) {
1170 netdev_features_t features = skb->dev->features;
1171 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1172 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1173
1174 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1175 vlan_proto == ETH_P_8021Q) ||
1176 ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1177 vlan_proto == ETH_P_8021AD))
1178 __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1179 meta_data &
1180 RX_CMP_FLAGS2_METADATA_VID_MASK);
1181 }
1182
1183 skb_checksum_none_assert(skb);
1184 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1185 if (dev->features & NETIF_F_RXCSUM) {
1186 skb->ip_summed = CHECKSUM_UNNECESSARY;
1187 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1188 }
1189 } else {
1190 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS)
1191 cpr->rx_l4_csum_errors++;
1192 }
1193
1194 skb_record_rx_queue(skb, bnapi->index);
1195 skb_mark_napi_id(skb, &bnapi->napi);
1196 if (bnxt_busy_polling(bnapi))
1197 netif_receive_skb(skb);
1198 else
1199 napi_gro_receive(&bnapi->napi, skb);
1200 rc = 1;
1201
1202next_rx:
1203 rxr->rx_prod = NEXT_RX(prod);
1204
1205next_rx_no_prod:
1206 *raw_cons = tmp_raw_cons;
1207
1208 return rc;
1209}
1210
1211static int bnxt_async_event_process(struct bnxt *bp,
1212 struct hwrm_async_event_cmpl *cmpl)
1213{
1214 u16 event_id = le16_to_cpu(cmpl->event_id);
1215
1216 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1217 switch (event_id) {
1218 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1219 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1220 schedule_work(&bp->sp_task);
1221 break;
1222 default:
1223 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1224 event_id);
1225 break;
1226 }
1227 return 0;
1228}
1229
1230static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1231{
1232 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1233 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1234 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1235 (struct hwrm_fwd_req_cmpl *)txcmp;
1236
1237 switch (cmpl_type) {
1238 case CMPL_BASE_TYPE_HWRM_DONE:
1239 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1240 if (seq_id == bp->hwrm_intr_seq_id)
1241 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1242 else
1243 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1244 break;
1245
1246 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1247 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1248
1249 if ((vf_id < bp->pf.first_vf_id) ||
1250 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1251 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1252 vf_id);
1253 return -EINVAL;
1254 }
1255
1256 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1257 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1258 schedule_work(&bp->sp_task);
1259 break;
1260
1261 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1262 bnxt_async_event_process(bp,
1263 (struct hwrm_async_event_cmpl *)txcmp);
1264
1265 default:
1266 break;
1267 }
1268
1269 return 0;
1270}
1271
1272static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1273{
1274 struct bnxt_napi *bnapi = dev_instance;
1275 struct bnxt *bp = bnapi->bp;
1276 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1277 u32 cons = RING_CMP(cpr->cp_raw_cons);
1278
1279 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1280 napi_schedule(&bnapi->napi);
1281 return IRQ_HANDLED;
1282}
1283
1284static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1285{
1286 u32 raw_cons = cpr->cp_raw_cons;
1287 u16 cons = RING_CMP(raw_cons);
1288 struct tx_cmp *txcmp;
1289
1290 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1291
1292 return TX_CMP_VALID(txcmp, raw_cons);
1293}
1294
c0c050c5
MC		 1295static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1296{
1297 struct bnxt_napi *bnapi = dev_instance;
1298 struct bnxt *bp = bnapi->bp;
1299 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1300 u32 cons = RING_CMP(cpr->cp_raw_cons);
1301 u32 int_status;
1302
1303 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1304
1305 if (!bnxt_has_work(bp, cpr)) {
11809490 1306 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
c0c050c5
MC		 1307 /* return if erroneous interrupt */
1308 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1309 return IRQ_NONE;
1310 }
1311
1312 /* disable ring IRQ */
1313 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1314
1315 /* Return here if interrupt is shared and is disabled. */
1316 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1317 return IRQ_HANDLED;
1318
1319 napi_schedule(&bnapi->napi);
1320 return IRQ_HANDLED;
1321}
1322
1323static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1324{
1325 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1326 u32 raw_cons = cpr->cp_raw_cons;
1327 u32 cons;
1328 int tx_pkts = 0;
1329 int rx_pkts = 0;
1330 bool rx_event = false;
1331 bool agg_event = false;
1332 struct tx_cmp *txcmp;
1333
1334 while (1) {
1335 int rc;
1336
1337 cons = RING_CMP(raw_cons);
1338 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1339
1340 if (!TX_CMP_VALID(txcmp, raw_cons))
1341 break;
1342
1343 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1344 tx_pkts++;
1345 /* return full budget so NAPI will complete. */
1346 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1347 rx_pkts = budget;
1348 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1349 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1350 if (likely(rc >= 0))
1351 rx_pkts += rc;
1352 else if (rc == -EBUSY) /* partial completion */
1353 break;
1354 rx_event = true;
1355 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1356 CMPL_BASE_TYPE_HWRM_DONE) ||
1357 (TX_CMP_TYPE(txcmp) ==
1358 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1359 (TX_CMP_TYPE(txcmp) ==
1360 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1361 bnxt_hwrm_handler(bp, txcmp);
1362 }
1363 raw_cons = NEXT_RAW_CMP(raw_cons);
1364
1365 if (rx_pkts == budget)
1366 break;
1367 }
1368
1369 cpr->cp_raw_cons = raw_cons;
1370 /* ACK completion ring before freeing tx ring and producing new
1371 * buffers in rx/agg rings to prevent overflowing the completion
1372 * ring.
1373 */
1374 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1375
1376 if (tx_pkts)
1377 bnxt_tx_int(bp, bnapi, tx_pkts);
1378
1379 if (rx_event) {
1380 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
1381
1382 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1383 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1384 if (agg_event) {
1385 writel(DB_KEY_RX | rxr->rx_agg_prod,
1386 rxr->rx_agg_doorbell);
1387 writel(DB_KEY_RX | rxr->rx_agg_prod,
1388 rxr->rx_agg_doorbell);
1389 }
1390 }
1391 return rx_pkts;
1392}
1393
1394static int bnxt_poll(struct napi_struct *napi, int budget)
1395{
1396 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1397 struct bnxt *bp = bnapi->bp;
1398 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1399 int work_done = 0;
1400
1401 if (!bnxt_lock_napi(bnapi))
1402 return budget;
1403
1404 while (1) {
1405 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1406
1407 if (work_done >= budget)
1408 break;
1409
1410 if (!bnxt_has_work(bp, cpr)) {
1411 napi_complete(napi);
1412 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1413 break;
1414 }
1415 }
1416 mmiowb();
1417 bnxt_unlock_napi(bnapi);
1418 return work_done;
1419}
1420
1421#ifdef CONFIG_NET_RX_BUSY_POLL
1422static int bnxt_busy_poll(struct napi_struct *napi)
1423{
1424 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1425 struct bnxt *bp = bnapi->bp;
1426 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1427 int rx_work, budget = 4;
1428
1429 if (atomic_read(&bp->intr_sem) != 0)
1430 return LL_FLUSH_FAILED;
1431
1432 if (!bnxt_lock_poll(bnapi))
1433 return LL_FLUSH_BUSY;
1434
1435 rx_work = bnxt_poll_work(bp, bnapi, budget);
1436
1437 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1438
1439 bnxt_unlock_poll(bnapi);
1440 return rx_work;
1441}
1442#endif
1443
1444static void bnxt_free_tx_skbs(struct bnxt *bp)
1445{
1446 int i, max_idx;
1447 struct pci_dev *pdev = bp->pdev;
1448
1449 if (!bp->bnapi)
1450 return;
1451
1452 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1453 for (i = 0; i < bp->tx_nr_rings; i++) {
1454 struct bnxt_napi *bnapi = bp->bnapi[i];
1455 struct bnxt_tx_ring_info *txr;
1456 int j;
1457
1458 if (!bnapi)
1459 continue;
1460
1461 txr = &bnapi->tx_ring;
1462 for (j = 0; j < max_idx;) {
1463 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1464 struct sk_buff *skb = tx_buf->skb;
1465 int k, last;
1466
1467 if (!skb) {
1468 j++;
1469 continue;
1470 }
1471
1472 tx_buf->skb = NULL;
1473
1474 if (tx_buf->is_push) {
1475 dev_kfree_skb(skb);
1476 j += 2;
1477 continue;
1478 }
1479
1480 dma_unmap_single(&pdev->dev,
1481 dma_unmap_addr(tx_buf, mapping),
1482 skb_headlen(skb),
1483 PCI_DMA_TODEVICE);
1484
1485 last = tx_buf->nr_frags;
1486 j += 2;
1487 for (k = 0; k < last; k++, j = NEXT_TX(j)) {
1488 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1489
1490 tx_buf = &txr->tx_buf_ring[j];
1491 dma_unmap_page(
1492 &pdev->dev,
1493 dma_unmap_addr(tx_buf, mapping),
1494 skb_frag_size(frag), PCI_DMA_TODEVICE);
1495 }
1496 dev_kfree_skb(skb);
1497 }
1498 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1499 }
1500}
1501
1502static void bnxt_free_rx_skbs(struct bnxt *bp)
1503{
1504 int i, max_idx, max_agg_idx;
1505 struct pci_dev *pdev = bp->pdev;
1506
1507 if (!bp->bnapi)
1508 return;
1509
1510 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1511 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1512 for (i = 0; i < bp->rx_nr_rings; i++) {
1513 struct bnxt_napi *bnapi = bp->bnapi[i];
1514 struct bnxt_rx_ring_info *rxr;
1515 int j;
1516
1517 if (!bnapi)
1518 continue;
1519
1520 rxr = &bnapi->rx_ring;
1521
1522 if (rxr->rx_tpa) {
1523 for (j = 0; j < MAX_TPA; j++) {
1524 struct bnxt_tpa_info *tpa_info =
1525 &rxr->rx_tpa[j];
1526 u8 *data = tpa_info->data;
1527
1528 if (!data)
1529 continue;
1530
1531 dma_unmap_single(
1532 &pdev->dev,
1533 dma_unmap_addr(tpa_info, mapping),
1534 bp->rx_buf_use_size,
1535 PCI_DMA_FROMDEVICE);
1536
1537 tpa_info->data = NULL;
1538
1539 kfree(data);
1540 }
1541 }
1542
1543 for (j = 0; j < max_idx; j++) {
1544 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1545 u8 *data = rx_buf->data;
1546
1547 if (!data)
1548 continue;
1549
1550 dma_unmap_single(&pdev->dev,
1551 dma_unmap_addr(rx_buf, mapping),
1552 bp->rx_buf_use_size,
1553 PCI_DMA_FROMDEVICE);
1554
1555 rx_buf->data = NULL;
1556
1557 kfree(data);
1558 }
1559
1560 for (j = 0; j < max_agg_idx; j++) {
1561 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1562 &rxr->rx_agg_ring[j];
1563 struct page *page = rx_agg_buf->page;
1564
1565 if (!page)
1566 continue;
1567
1568 dma_unmap_page(&pdev->dev,
1569 dma_unmap_addr(rx_agg_buf, mapping),
1570 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1571
1572 rx_agg_buf->page = NULL;
1573 __clear_bit(j, rxr->rx_agg_bmap);
1574
1575 __free_page(page);
1576 }
1577 }
1578}
1579
1580static void bnxt_free_skbs(struct bnxt *bp)
1581{
1582 bnxt_free_tx_skbs(bp);
1583 bnxt_free_rx_skbs(bp);
1584}
1585
1586static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1587{
1588 struct pci_dev *pdev = bp->pdev;
1589 int i;
1590
1591 for (i = 0; i < ring->nr_pages; i++) {
1592 if (!ring->pg_arr[i])
1593 continue;
1594
1595 dma_free_coherent(&pdev->dev, ring->page_size,
1596 ring->pg_arr[i], ring->dma_arr[i]);
1597
1598 ring->pg_arr[i] = NULL;
1599 }
1600 if (ring->pg_tbl) {
1601 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1602 ring->pg_tbl, ring->pg_tbl_map);
1603 ring->pg_tbl = NULL;
1604 }
1605 if (ring->vmem_size && *ring->vmem) {
1606 vfree(*ring->vmem);
1607 *ring->vmem = NULL;
1608 }
1609}
1610
1611static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1612{
1613 int i;
1614 struct pci_dev *pdev = bp->pdev;
1615
1616 if (ring->nr_pages > 1) {
1617 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1618 ring->nr_pages * 8,
1619 &ring->pg_tbl_map,
1620 GFP_KERNEL);
1621 if (!ring->pg_tbl)
1622 return -ENOMEM;
1623 }
1624
1625 for (i = 0; i < ring->nr_pages; i++) {
1626 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1627 ring->page_size,
1628 &ring->dma_arr[i],
1629 GFP_KERNEL);
1630 if (!ring->pg_arr[i])
1631 return -ENOMEM;
1632
1633 if (ring->nr_pages > 1)
1634 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1635 }
1636
1637 if (ring->vmem_size) {
1638 *ring->vmem = vzalloc(ring->vmem_size);
1639 if (!(*ring->vmem))
1640 return -ENOMEM;
1641 }
1642 return 0;
1643}
1644
1645static void bnxt_free_rx_rings(struct bnxt *bp)
1646{
1647 int i;
1648
1649 if (!bp->bnapi)
1650 return;
1651
1652 for (i = 0; i < bp->rx_nr_rings; i++) {
1653 struct bnxt_napi *bnapi = bp->bnapi[i];
1654 struct bnxt_rx_ring_info *rxr;
1655 struct bnxt_ring_struct *ring;
1656
1657 if (!bnapi)
1658 continue;
1659
1660 rxr = &bnapi->rx_ring;
1661
1662 kfree(rxr->rx_tpa);
1663 rxr->rx_tpa = NULL;
1664
1665 kfree(rxr->rx_agg_bmap);
1666 rxr->rx_agg_bmap = NULL;
1667
1668 ring = &rxr->rx_ring_struct;
1669 bnxt_free_ring(bp, ring);
1670
1671 ring = &rxr->rx_agg_ring_struct;
1672 bnxt_free_ring(bp, ring);
1673 }
1674}
1675
1676static int bnxt_alloc_rx_rings(struct bnxt *bp)
1677{
1678 int i, rc, agg_rings = 0, tpa_rings = 0;
1679
1680 if (bp->flags & BNXT_FLAG_AGG_RINGS)
1681 agg_rings = 1;
1682
1683 if (bp->flags & BNXT_FLAG_TPA)
1684 tpa_rings = 1;
1685
1686 for (i = 0; i < bp->rx_nr_rings; i++) {
1687 struct bnxt_napi *bnapi = bp->bnapi[i];
1688 struct bnxt_rx_ring_info *rxr;
1689 struct bnxt_ring_struct *ring;
1690
1691 if (!bnapi)
1692 continue;
1693
1694 rxr = &bnapi->rx_ring;
1695 ring = &rxr->rx_ring_struct;
1696
1697 rc = bnxt_alloc_ring(bp, ring);
1698 if (rc)
1699 return rc;
1700
1701 if (agg_rings) {
1702 u16 mem_size;
1703
1704 ring = &rxr->rx_agg_ring_struct;
1705 rc = bnxt_alloc_ring(bp, ring);
1706 if (rc)
1707 return rc;
1708
1709 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1710 mem_size = rxr->rx_agg_bmap_size / 8;
1711 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1712 if (!rxr->rx_agg_bmap)
1713 return -ENOMEM;
1714
1715 if (tpa_rings) {
1716 rxr->rx_tpa = kcalloc(MAX_TPA,
1717 sizeof(struct bnxt_tpa_info),
1718 GFP_KERNEL);
1719 if (!rxr->rx_tpa)
1720 return -ENOMEM;
1721 }
1722 }
1723 }
1724 return 0;
1725}
1726
1727static void bnxt_free_tx_rings(struct bnxt *bp)
1728{
1729 int i;
1730 struct pci_dev *pdev = bp->pdev;
1731
1732 if (!bp->bnapi)
1733 return;
1734
1735 for (i = 0; i < bp->tx_nr_rings; i++) {
1736 struct bnxt_napi *bnapi = bp->bnapi[i];
1737 struct bnxt_tx_ring_info *txr;
1738 struct bnxt_ring_struct *ring;
1739
1740 if (!bnapi)
1741 continue;
1742
1743 txr = &bnapi->tx_ring;
1744
1745 if (txr->tx_push) {
1746 dma_free_coherent(&pdev->dev, bp->tx_push_size,
1747 txr->tx_push, txr->tx_push_mapping);
1748 txr->tx_push = NULL;
1749 }
1750
1751 ring = &txr->tx_ring_struct;
1752
1753 bnxt_free_ring(bp, ring);
1754 }
1755}
1756
1757static int bnxt_alloc_tx_rings(struct bnxt *bp)
1758{
1759 int i, j, rc;
1760 struct pci_dev *pdev = bp->pdev;
1761
1762 bp->tx_push_size = 0;
1763 if (bp->tx_push_thresh) {
1764 int push_size;
1765
1766 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
1767 bp->tx_push_thresh);
1768
1769 if (push_size > 128) {
1770 push_size = 0;
1771 bp->tx_push_thresh = 0;
1772 }
1773
1774 bp->tx_push_size = push_size;
1775 }
1776
1777 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
1778 struct bnxt_napi *bnapi = bp->bnapi[i];
1779 struct bnxt_tx_ring_info *txr;
1780 struct bnxt_ring_struct *ring;
1781
1782 if (!bnapi)
1783 continue;
1784
1785 txr = &bnapi->tx_ring;
1786 ring = &txr->tx_ring_struct;
1787
1788 rc = bnxt_alloc_ring(bp, ring);
1789 if (rc)
1790 return rc;
1791
1792 if (bp->tx_push_size) {
1793 struct tx_bd *txbd;
1794 dma_addr_t mapping;
1795
1796 /* One pre-allocated DMA buffer to backup
1797 * TX push operation
1798 */
1799 txr->tx_push = dma_alloc_coherent(&pdev->dev,
1800 bp->tx_push_size,
1801 &txr->tx_push_mapping,
1802 GFP_KERNEL);
1803
1804 if (!txr->tx_push)
1805 return -ENOMEM;
1806
1807 txbd = &txr->tx_push->txbd1;
1808
1809 mapping = txr->tx_push_mapping +
1810 sizeof(struct tx_push_bd);
1811 txbd->tx_bd_haddr = cpu_to_le64(mapping);
1812
1813 memset(txbd + 1, 0, sizeof(struct tx_bd_ext));
1814 }
1815 ring->queue_id = bp->q_info[j].queue_id;
1816 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
1817 j++;
1818 }
1819 return 0;
1820}
1821
1822static void bnxt_free_cp_rings(struct bnxt *bp)
1823{
1824 int i;
1825
1826 if (!bp->bnapi)
1827 return;
1828
1829 for (i = 0; i < bp->cp_nr_rings; i++) {
1830 struct bnxt_napi *bnapi = bp->bnapi[i];
1831 struct bnxt_cp_ring_info *cpr;
1832 struct bnxt_ring_struct *ring;
1833
1834 if (!bnapi)
1835 continue;
1836
1837 cpr = &bnapi->cp_ring;
1838 ring = &cpr->cp_ring_struct;
1839
1840 bnxt_free_ring(bp, ring);
1841 }
1842}
1843
1844static int bnxt_alloc_cp_rings(struct bnxt *bp)
1845{
1846 int i, rc;
1847
1848 for (i = 0; i < bp->cp_nr_rings; i++) {
1849 struct bnxt_napi *bnapi = bp->bnapi[i];
1850 struct bnxt_cp_ring_info *cpr;
1851 struct bnxt_ring_struct *ring;
1852
1853 if (!bnapi)
1854 continue;
1855
1856 cpr = &bnapi->cp_ring;
1857 ring = &cpr->cp_ring_struct;
1858
1859 rc = bnxt_alloc_ring(bp, ring);
1860 if (rc)
1861 return rc;
1862 }
1863 return 0;
1864}
1865
1866static void bnxt_init_ring_struct(struct bnxt *bp)
1867{
1868 int i;
1869
1870 for (i = 0; i < bp->cp_nr_rings; i++) {
1871 struct bnxt_napi *bnapi = bp->bnapi[i];
1872 struct bnxt_cp_ring_info *cpr;
1873 struct bnxt_rx_ring_info *rxr;
1874 struct bnxt_tx_ring_info *txr;
1875 struct bnxt_ring_struct *ring;
1876
1877 if (!bnapi)
1878 continue;
1879
1880 cpr = &bnapi->cp_ring;
1881 ring = &cpr->cp_ring_struct;
1882 ring->nr_pages = bp->cp_nr_pages;
1883 ring->page_size = HW_CMPD_RING_SIZE;
1884 ring->pg_arr = (void **)cpr->cp_desc_ring;
1885 ring->dma_arr = cpr->cp_desc_mapping;
1886 ring->vmem_size = 0;
1887
1888 rxr = &bnapi->rx_ring;
1889 ring = &rxr->rx_ring_struct;
1890 ring->nr_pages = bp->rx_nr_pages;
1891 ring->page_size = HW_RXBD_RING_SIZE;
1892 ring->pg_arr = (void **)rxr->rx_desc_ring;
1893 ring->dma_arr = rxr->rx_desc_mapping;
1894 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
1895 ring->vmem = (void **)&rxr->rx_buf_ring;
1896
1897 ring = &rxr->rx_agg_ring_struct;
1898 ring->nr_pages = bp->rx_agg_nr_pages;
1899 ring->page_size = HW_RXBD_RING_SIZE;
1900 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
1901 ring->dma_arr = rxr->rx_agg_desc_mapping;
1902 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
1903 ring->vmem = (void **)&rxr->rx_agg_ring;
1904
1905 txr = &bnapi->tx_ring;
1906 ring = &txr->tx_ring_struct;
1907 ring->nr_pages = bp->tx_nr_pages;
1908 ring->page_size = HW_RXBD_RING_SIZE;
1909 ring->pg_arr = (void **)txr->tx_desc_ring;
1910 ring->dma_arr = txr->tx_desc_mapping;
1911 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
1912 ring->vmem = (void **)&txr->tx_buf_ring;
1913 }
1914}
1915
1916static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
1917{
1918 int i;
1919 u32 prod;
1920 struct rx_bd **rx_buf_ring;
1921
1922 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
1923 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
1924 int j;
1925 struct rx_bd *rxbd;
1926
1927 rxbd = rx_buf_ring[i];
1928 if (!rxbd)
1929 continue;
1930
1931 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
1932 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
1933 rxbd->rx_bd_opaque = prod;
1934 }
1935 }
1936}
1937
1938static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
1939{
1940 struct net_device *dev = bp->dev;
1941 struct bnxt_napi *bnapi = bp->bnapi[ring_nr];
1942 struct bnxt_rx_ring_info *rxr;
1943 struct bnxt_ring_struct *ring;
1944 u32 prod, type;
1945 int i;
1946
1947 if (!bnapi)
1948 return -EINVAL;
1949
1950 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
1951 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
1952
1953 if (NET_IP_ALIGN == 2)
1954 type |= RX_BD_FLAGS_SOP;
1955
1956 rxr = &bnapi->rx_ring;
1957 ring = &rxr->rx_ring_struct;
1958 bnxt_init_rxbd_pages(ring, type);
1959
1960 prod = rxr->rx_prod;
1961 for (i = 0; i < bp->rx_ring_size; i++) {
1962 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
1963 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
1964 ring_nr, i, bp->rx_ring_size);
1965 break;
1966 }
1967 prod = NEXT_RX(prod);
1968 }
1969 rxr->rx_prod = prod;
1970 ring->fw_ring_id = INVALID_HW_RING_ID;
1971
1972 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
1973 return 0;
1974
1975 ring = &rxr->rx_agg_ring_struct;
1976
1977 type = ((u32)PAGE_SIZE << RX_BD_LEN_SHIFT) |
1978 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
1979
1980 bnxt_init_rxbd_pages(ring, type);
1981
1982 prod = rxr->rx_agg_prod;
1983 for (i = 0; i < bp->rx_agg_ring_size; i++) {
1984 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
1985 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
1986 ring_nr, i, bp->rx_ring_size);
1987 break;
1988 }
1989 prod = NEXT_RX_AGG(prod);
1990 }
1991 rxr->rx_agg_prod = prod;
1992 ring->fw_ring_id = INVALID_HW_RING_ID;
1993
1994 if (bp->flags & BNXT_FLAG_TPA) {
1995 if (rxr->rx_tpa) {
1996 u8 *data;
1997 dma_addr_t mapping;
1998
1999 for (i = 0; i < MAX_TPA; i++) {
2000 data = __bnxt_alloc_rx_data(bp, &mapping,
2001 GFP_KERNEL);
2002 if (!data)
2003 return -ENOMEM;
2004
2005 rxr->rx_tpa[i].data = data;
2006 rxr->rx_tpa[i].mapping = mapping;
2007 }
2008 } else {
2009 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2010 return -ENOMEM;
2011 }
2012 }
2013
2014 return 0;
2015}
2016
2017static int bnxt_init_rx_rings(struct bnxt *bp)
2018{
2019 int i, rc = 0;
2020
2021 for (i = 0; i < bp->rx_nr_rings; i++) {
2022 rc = bnxt_init_one_rx_ring(bp, i);
2023 if (rc)
2024 break;
2025 }
2026
2027 return rc;
2028}
2029
2030static int bnxt_init_tx_rings(struct bnxt *bp)
2031{
2032 u16 i;
2033
2034 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2035 MAX_SKB_FRAGS + 1);
2036
2037 for (i = 0; i < bp->tx_nr_rings; i++) {
2038 struct bnxt_napi *bnapi = bp->bnapi[i];
2039 struct bnxt_tx_ring_info *txr = &bnapi->tx_ring;
2040 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2041
2042 ring->fw_ring_id = INVALID_HW_RING_ID;
2043 }
2044
2045 return 0;
2046}
2047
2048static void bnxt_free_ring_grps(struct bnxt *bp)
2049{
2050 kfree(bp->grp_info);
2051 bp->grp_info = NULL;
2052}
2053
2054static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2055{
2056 int i;
2057
2058 if (irq_re_init) {
2059 bp->grp_info = kcalloc(bp->cp_nr_rings,
2060 sizeof(struct bnxt_ring_grp_info),
2061 GFP_KERNEL);
2062 if (!bp->grp_info)
2063 return -ENOMEM;
2064 }
2065 for (i = 0; i < bp->cp_nr_rings; i++) {
2066 if (irq_re_init)
2067 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2068 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2069 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2070 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2071 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2072 }
2073 return 0;
2074}
2075
2076static void bnxt_free_vnics(struct bnxt *bp)
2077{
2078 kfree(bp->vnic_info);
2079 bp->vnic_info = NULL;
2080 bp->nr_vnics = 0;
2081}
2082
2083static int bnxt_alloc_vnics(struct bnxt *bp)
2084{
2085 int num_vnics = 1;
2086
2087#ifdef CONFIG_RFS_ACCEL
2088 if (bp->flags & BNXT_FLAG_RFS)
2089 num_vnics += bp->rx_nr_rings;
2090#endif
2091
2092 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2093 GFP_KERNEL);
2094 if (!bp->vnic_info)
2095 return -ENOMEM;
2096
2097 bp->nr_vnics = num_vnics;
2098 return 0;
2099}
2100
2101static void bnxt_init_vnics(struct bnxt *bp)
2102{
2103 int i;
2104
2105 for (i = 0; i < bp->nr_vnics; i++) {
2106 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2107
2108 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2109 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2110 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2111
2112 if (bp->vnic_info[i].rss_hash_key) {
2113 if (i == 0)
2114 prandom_bytes(vnic->rss_hash_key,
2115 HW_HASH_KEY_SIZE);
2116 else
2117 memcpy(vnic->rss_hash_key,
2118 bp->vnic_info[0].rss_hash_key,
2119 HW_HASH_KEY_SIZE);
2120 }
2121 }
2122}
2123
2124static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2125{
2126 int pages;
2127
2128 pages = ring_size / desc_per_pg;
2129
2130 if (!pages)
2131 return 1;
2132
2133 pages++;
2134
2135 while (pages & (pages - 1))
2136 pages++;
2137
2138 return pages;
2139}
2140
2141static void bnxt_set_tpa_flags(struct bnxt *bp)
2142{
2143 bp->flags &= ~BNXT_FLAG_TPA;
2144 if (bp->dev->features & NETIF_F_LRO)
2145 bp->flags |= BNXT_FLAG_LRO;
2146 if ((bp->dev->features & NETIF_F_GRO) && (bp->pdev->revision > 0))
2147 bp->flags |= BNXT_FLAG_GRO;
2148}
2149
2150/* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2151 * be set on entry.
2152 */
2153void bnxt_set_ring_params(struct bnxt *bp)
2154{
2155 u32 ring_size, rx_size, rx_space;
2156 u32 agg_factor = 0, agg_ring_size = 0;
2157
2158 /* 8 for CRC and VLAN */
2159 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2160
2161 rx_space = rx_size + NET_SKB_PAD +
2162 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2163
2164 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2165 ring_size = bp->rx_ring_size;
2166 bp->rx_agg_ring_size = 0;
2167 bp->rx_agg_nr_pages = 0;
2168
2169 if (bp->flags & BNXT_FLAG_TPA)
2170 agg_factor = 4;
2171
2172 bp->flags &= ~BNXT_FLAG_JUMBO;
2173 if (rx_space > PAGE_SIZE) {
2174 u32 jumbo_factor;
2175
2176 bp->flags |= BNXT_FLAG_JUMBO;
2177 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2178 if (jumbo_factor > agg_factor)
2179 agg_factor = jumbo_factor;
2180 }
2181 agg_ring_size = ring_size * agg_factor;
2182
2183 if (agg_ring_size) {
2184 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2185 RX_DESC_CNT);
2186 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2187 u32 tmp = agg_ring_size;
2188
2189 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2190 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2191 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2192 tmp, agg_ring_size);
2193 }
2194 bp->rx_agg_ring_size = agg_ring_size;
2195 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2196 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2197 rx_space = rx_size + NET_SKB_PAD +
2198 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2199 }
2200
2201 bp->rx_buf_use_size = rx_size;
2202 bp->rx_buf_size = rx_space;
2203
2204 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2205 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2206
2207 ring_size = bp->tx_ring_size;
2208 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2209 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2210
2211 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2212 bp->cp_ring_size = ring_size;
2213
2214 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2215 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2216 bp->cp_nr_pages = MAX_CP_PAGES;
2217 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2218 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2219 ring_size, bp->cp_ring_size);
2220 }
2221 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2222 bp->cp_ring_mask = bp->cp_bit - 1;
2223}
2224
2225static void bnxt_free_vnic_attributes(struct bnxt *bp)
2226{
2227 int i;
2228 struct bnxt_vnic_info *vnic;
2229 struct pci_dev *pdev = bp->pdev;
2230
2231 if (!bp->vnic_info)
2232 return;
2233
2234 for (i = 0; i < bp->nr_vnics; i++) {
2235 vnic = &bp->vnic_info[i];
2236
2237 kfree(vnic->fw_grp_ids);
2238 vnic->fw_grp_ids = NULL;
2239
2240 kfree(vnic->uc_list);
2241 vnic->uc_list = NULL;
2242
2243 if (vnic->mc_list) {
2244 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2245 vnic->mc_list, vnic->mc_list_mapping);
2246 vnic->mc_list = NULL;
2247 }
2248
2249 if (vnic->rss_table) {
2250 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2251 vnic->rss_table,
2252 vnic->rss_table_dma_addr);
2253 vnic->rss_table = NULL;
2254 }
2255
2256 vnic->rss_hash_key = NULL;
2257 vnic->flags = 0;
2258 }
2259}
2260
2261static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2262{
2263 int i, rc = 0, size;
2264 struct bnxt_vnic_info *vnic;
2265 struct pci_dev *pdev = bp->pdev;
2266 int max_rings;
2267
2268 for (i = 0; i < bp->nr_vnics; i++) {
2269 vnic = &bp->vnic_info[i];
2270
2271 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2272 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2273
2274 if (mem_size > 0) {
2275 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2276 if (!vnic->uc_list) {
2277 rc = -ENOMEM;
2278 goto out;
2279 }
2280 }
2281 }
2282
2283 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2284 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2285 vnic->mc_list =
2286 dma_alloc_coherent(&pdev->dev,
2287 vnic->mc_list_size,
2288 &vnic->mc_list_mapping,
2289 GFP_KERNEL);
2290 if (!vnic->mc_list) {
2291 rc = -ENOMEM;
2292 goto out;
2293 }
2294 }
2295
2296 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2297 max_rings = bp->rx_nr_rings;
2298 else
2299 max_rings = 1;
2300
2301 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2302 if (!vnic->fw_grp_ids) {
2303 rc = -ENOMEM;
2304 goto out;
2305 }
2306
2307 /* Allocate rss table and hash key */
2308 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2309 &vnic->rss_table_dma_addr,
2310 GFP_KERNEL);
2311 if (!vnic->rss_table) {
2312 rc = -ENOMEM;
2313 goto out;
2314 }
2315
2316 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2317
2318 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2319 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2320 }
2321 return 0;
2322
2323out:
2324 return rc;
2325}
2326
2327static void bnxt_free_hwrm_resources(struct bnxt *bp)
2328{
2329 struct pci_dev *pdev = bp->pdev;
2330
2331 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2332 bp->hwrm_cmd_resp_dma_addr);
2333
2334 bp->hwrm_cmd_resp_addr = NULL;
2335 if (bp->hwrm_dbg_resp_addr) {
2336 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2337 bp->hwrm_dbg_resp_addr,
2338 bp->hwrm_dbg_resp_dma_addr);
2339
2340 bp->hwrm_dbg_resp_addr = NULL;
2341 }
2342}
2343
2344static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2345{
2346 struct pci_dev *pdev = bp->pdev;
2347
2348 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2349 &bp->hwrm_cmd_resp_dma_addr,
2350 GFP_KERNEL);
2351 if (!bp->hwrm_cmd_resp_addr)
2352 return -ENOMEM;
2353 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2354 HWRM_DBG_REG_BUF_SIZE,
2355 &bp->hwrm_dbg_resp_dma_addr,
2356 GFP_KERNEL);
2357 if (!bp->hwrm_dbg_resp_addr)
2358 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2359
2360 return 0;
2361}
2362
2363static void bnxt_free_stats(struct bnxt *bp)
2364{
2365 u32 size, i;
2366 struct pci_dev *pdev = bp->pdev;
2367
2368 if (!bp->bnapi)
2369 return;
2370
2371 size = sizeof(struct ctx_hw_stats);
2372
2373 for (i = 0; i < bp->cp_nr_rings; i++) {
2374 struct bnxt_napi *bnapi = bp->bnapi[i];
2375 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2376
2377 if (cpr->hw_stats) {
2378 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2379 cpr->hw_stats_map);
2380 cpr->hw_stats = NULL;
2381 }
2382 }
2383}
2384
2385static int bnxt_alloc_stats(struct bnxt *bp)
2386{
2387 u32 size, i;
2388 struct pci_dev *pdev = bp->pdev;
2389
2390 size = sizeof(struct ctx_hw_stats);
2391
2392 for (i = 0; i < bp->cp_nr_rings; i++) {
2393 struct bnxt_napi *bnapi = bp->bnapi[i];
2394 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2395
2396 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2397 &cpr->hw_stats_map,
2398 GFP_KERNEL);
2399 if (!cpr->hw_stats)
2400 return -ENOMEM;
2401
2402 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2403 }
2404 return 0;
2405}
2406
2407static void bnxt_clear_ring_indices(struct bnxt *bp)
2408{
2409 int i;
2410
2411 if (!bp->bnapi)
2412 return;
2413
2414 for (i = 0; i < bp->cp_nr_rings; i++) {
2415 struct bnxt_napi *bnapi = bp->bnapi[i];
2416 struct bnxt_cp_ring_info *cpr;
2417 struct bnxt_rx_ring_info *rxr;
2418 struct bnxt_tx_ring_info *txr;
2419
2420 if (!bnapi)
2421 continue;
2422
2423 cpr = &bnapi->cp_ring;
2424 cpr->cp_raw_cons = 0;
2425
2426 txr = &bnapi->tx_ring;
2427 txr->tx_prod = 0;
2428 txr->tx_cons = 0;
2429
2430 rxr = &bnapi->rx_ring;
2431 rxr->rx_prod = 0;
2432 rxr->rx_agg_prod = 0;
2433 rxr->rx_sw_agg_prod = 0;
2434 }
2435}
2436
2437static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2438{
2439#ifdef CONFIG_RFS_ACCEL
2440 int i;
2441
2442 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2443 * safe to delete the hash table.
2444 */
2445 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2446 struct hlist_head *head;
2447 struct hlist_node *tmp;
2448 struct bnxt_ntuple_filter *fltr;
2449
2450 head = &bp->ntp_fltr_hash_tbl[i];
2451 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2452 hlist_del(&fltr->hash);
2453 kfree(fltr);
2454 }
2455 }
2456 if (irq_reinit) {
2457 kfree(bp->ntp_fltr_bmap);
2458 bp->ntp_fltr_bmap = NULL;
2459 }
2460 bp->ntp_fltr_count = 0;
2461#endif
2462}
2463
2464static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2465{
2466#ifdef CONFIG_RFS_ACCEL
2467 int i, rc = 0;
2468
2469 if (!(bp->flags & BNXT_FLAG_RFS))
2470 return 0;
2471
2472 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2473 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2474
2475 bp->ntp_fltr_count = 0;
2476 bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2477 GFP_KERNEL);
2478
2479 if (!bp->ntp_fltr_bmap)
2480 rc = -ENOMEM;
2481
2482 return rc;
2483#else
2484 return 0;
2485#endif
2486}
2487
2488static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2489{
2490 bnxt_free_vnic_attributes(bp);
2491 bnxt_free_tx_rings(bp);
2492 bnxt_free_rx_rings(bp);
2493 bnxt_free_cp_rings(bp);
2494 bnxt_free_ntp_fltrs(bp, irq_re_init);
2495 if (irq_re_init) {
2496 bnxt_free_stats(bp);
2497 bnxt_free_ring_grps(bp);
2498 bnxt_free_vnics(bp);
2499 kfree(bp->bnapi);
2500 bp->bnapi = NULL;
2501 } else {
2502 bnxt_clear_ring_indices(bp);
2503 }
2504}
2505
2506static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2507{
2508 int i, rc, size, arr_size;
2509 void *bnapi;
2510
2511 if (irq_re_init) {
2512 /* Allocate bnapi mem pointer array and mem block for
2513 * all queues
2514 */
2515 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2516 bp->cp_nr_rings);
2517 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2518 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2519 if (!bnapi)
2520 return -ENOMEM;
2521
2522 bp->bnapi = bnapi;
2523 bnapi += arr_size;
2524 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2525 bp->bnapi[i] = bnapi;
2526 bp->bnapi[i]->index = i;
2527 bp->bnapi[i]->bp = bp;
2528 }
2529
2530 rc = bnxt_alloc_stats(bp);
2531 if (rc)
2532 goto alloc_mem_err;
2533
2534 rc = bnxt_alloc_ntp_fltrs(bp);
2535 if (rc)
2536 goto alloc_mem_err;
2537
2538 rc = bnxt_alloc_vnics(bp);
2539 if (rc)
2540 goto alloc_mem_err;
2541 }
2542
2543 bnxt_init_ring_struct(bp);
2544
2545 rc = bnxt_alloc_rx_rings(bp);
2546 if (rc)
2547 goto alloc_mem_err;
2548
2549 rc = bnxt_alloc_tx_rings(bp);
2550 if (rc)
2551 goto alloc_mem_err;
2552
2553 rc = bnxt_alloc_cp_rings(bp);
2554 if (rc)
2555 goto alloc_mem_err;
2556
2557 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2558 BNXT_VNIC_UCAST_FLAG;
2559 rc = bnxt_alloc_vnic_attributes(bp);
2560 if (rc)
2561 goto alloc_mem_err;
2562 return 0;
2563
2564alloc_mem_err:
2565 bnxt_free_mem(bp, true);
2566 return rc;
2567}
2568
2569void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2570 u16 cmpl_ring, u16 target_id)
2571{
2572 struct hwrm_cmd_req_hdr *req = request;
2573
2574 req->cmpl_ring_req_type =
2575 cpu_to_le32(req_type | (cmpl_ring << HWRM_CMPL_RING_SFT));
2576 req->target_id_seq_id = cpu_to_le32(target_id << HWRM_TARGET_FID_SFT);
2577 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2578}
2579
2580int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2581{
2582 int i, intr_process, rc;
2583 struct hwrm_cmd_req_hdr *req = msg;
2584 u32 *data = msg;
2585 __le32 *resp_len, *valid;
2586 u16 cp_ring_id, len = 0;
2587 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2588
2589 req->target_id_seq_id |= cpu_to_le32(bp->hwrm_cmd_seq++);
2590 memset(resp, 0, PAGE_SIZE);
2591 cp_ring_id = (le32_to_cpu(req->cmpl_ring_req_type) &
2592 HWRM_CMPL_RING_MASK) >>
2593 HWRM_CMPL_RING_SFT;
2594 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2595
2596 /* Write request msg to hwrm channel */
2597 __iowrite32_copy(bp->bar0, data, msg_len / 4);
2598
2599 /* currently supports only one outstanding message */
2600 if (intr_process)
2601 bp->hwrm_intr_seq_id = le32_to_cpu(req->target_id_seq_id) &
2602 HWRM_SEQ_ID_MASK;
2603
2604 /* Ring channel doorbell */
2605 writel(1, bp->bar0 + 0x100);
2606
2607 i = 0;
2608 if (intr_process) {
2609 /* Wait until hwrm response cmpl interrupt is processed */
2610 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
2611 i++ < timeout) {
2612 usleep_range(600, 800);
2613 }
2614
2615 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2616 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
2617 req->cmpl_ring_req_type);
2618 return -1;
2619 }
2620 } else {
2621 /* Check if response len is updated */
2622 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
2623 for (i = 0; i < timeout; i++) {
2624 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2625 HWRM_RESP_LEN_SFT;
2626 if (len)
2627 break;
2628 usleep_range(600, 800);
2629 }
2630
2631 if (i >= timeout) {
2632 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2633 timeout, req->cmpl_ring_req_type,
2634 req->target_id_seq_id, *resp_len);
2635 return -1;
2636 }
2637
2638 /* Last word of resp contains valid bit */
2639 valid = bp->hwrm_cmd_resp_addr + len - 4;
2640 for (i = 0; i < timeout; i++) {
2641 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2642 break;
2643 usleep_range(600, 800);
2644 }
2645
2646 if (i >= timeout) {
2647 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2648 timeout, req->cmpl_ring_req_type,
2649 req->target_id_seq_id, len, *valid);
2650 return -1;
2651 }
2652 }
2653
2654 rc = le16_to_cpu(resp->error_code);
2655 if (rc) {
2656 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2657 le16_to_cpu(resp->req_type),
2658 le16_to_cpu(resp->seq_id), rc);
2659 return rc;
2660 }
2661 return 0;
2662}
2663
2664int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2665{
2666 int rc;
2667
2668 mutex_lock(&bp->hwrm_cmd_lock);
2669 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2670 mutex_unlock(&bp->hwrm_cmd_lock);
2671 return rc;
2672}
2673
2674static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
2675{
2676 struct hwrm_func_drv_rgtr_input req = {0};
2677 int i;
2678
2679 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
2680
2681 req.enables =
2682 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
2683 FUNC_DRV_RGTR_REQ_ENABLES_VER |
2684 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
2685
2686 /* TODO: current async event fwd bits are not defined and the firmware
2687 * only checks if it is non-zero to enable async event forwarding
2688 */
2689 req.async_event_fwd[0] |= cpu_to_le32(1);
2690 req.os_type = cpu_to_le16(1);
2691 req.ver_maj = DRV_VER_MAJ;
2692 req.ver_min = DRV_VER_MIN;
2693 req.ver_upd = DRV_VER_UPD;
2694
2695 if (BNXT_PF(bp)) {
2696 unsigned long vf_req_snif_bmap[4];
2697 u32 *data = (u32 *)vf_req_snif_bmap;
2698
2699 memset(vf_req_snif_bmap, 0, 32);
2700 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
2701 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
2702
2703 for (i = 0; i < 8; i++) {
2704 req.vf_req_fwd[i] = cpu_to_le32(*data);
2705 data++;
2706 }
2707 req.enables |=
2708 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
2709 }
2710
2711 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2712}
2713
2714static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
2715{
2716 u32 rc = 0;
2717 struct hwrm_tunnel_dst_port_free_input req = {0};
2718
2719 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
2720 req.tunnel_type = tunnel_type;
2721
2722 switch (tunnel_type) {
2723 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
2724 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
2725 break;
2726 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
2727 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
2728 break;
2729 default:
2730 break;
2731 }
2732
2733 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2734 if (rc)
2735 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2736 rc);
2737 return rc;
2738}
2739
2740static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
2741 u8 tunnel_type)
2742{
2743 u32 rc = 0;
2744 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2745 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2746
2747 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
2748
2749 req.tunnel_type = tunnel_type;
2750 req.tunnel_dst_port_val = port;
2751
2752 mutex_lock(&bp->hwrm_cmd_lock);
2753 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2754 if (rc) {
2755 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2756 rc);
2757 goto err_out;
2758 }
2759
2760 if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
2761 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2762
2763 else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
2764 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
2765err_out:
2766 mutex_unlock(&bp->hwrm_cmd_lock);
2767 return rc;
2768}
2769
2770static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
2771{
2772 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
2773 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2774
2775 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
2776 req.dflt_vnic_id = cpu_to_le32(vnic->fw_vnic_id);
2777
2778 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
2779 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
2780 req.mask = cpu_to_le32(vnic->rx_mask);
2781 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2782}
2783
2784#ifdef CONFIG_RFS_ACCEL
2785static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2786 struct bnxt_ntuple_filter *fltr)
2787{
2788 struct hwrm_cfa_ntuple_filter_free_input req = {0};
2789
2790 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
2791 req.ntuple_filter_id = fltr->filter_id;
2792 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2793}
2794
2795#define BNXT_NTP_FLTR_FLAGS \
2796 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
2797 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
2798 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
2799 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
2800 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
2801 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
2802 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
2803 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
2804 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
2805 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
2806 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
2807 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
2808 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
2809 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID)
2810
2811static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2812 struct bnxt_ntuple_filter *fltr)
2813{
2814 int rc = 0;
2815 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
2816 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
2817 bp->hwrm_cmd_resp_addr;
2818 struct flow_keys *keys = &fltr->fkeys;
2819 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
2820
2821 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
2822 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
2823
2824 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
2825
2826 req.ethertype = htons(ETH_P_IP);
2827 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
2828 req.ipaddr_type = 4;
2829 req.ip_protocol = keys->basic.ip_proto;
2830
2831 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
2832 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2833 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
2834 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2835
2836 req.src_port = keys->ports.src;
2837 req.src_port_mask = cpu_to_be16(0xffff);
2838 req.dst_port = keys->ports.dst;
2839 req.dst_port_mask = cpu_to_be16(0xffff);
2840
2841 req.dst_vnic_id = cpu_to_le16(vnic->fw_vnic_id);
2842 mutex_lock(&bp->hwrm_cmd_lock);
2843 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2844 if (!rc)
2845 fltr->filter_id = resp->ntuple_filter_id;
2846 mutex_unlock(&bp->hwrm_cmd_lock);
2847 return rc;
2848}
2849#endif
2850
2851static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
2852 u8 *mac_addr)
2853{
2854 u32 rc = 0;
2855 struct hwrm_cfa_l2_filter_alloc_input req = {0};
2856 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2857
2858 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
2859 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
2860 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
2861 req.dst_vnic_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
2862 req.enables =
2863 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
2864 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID |
2865 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
2866 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
2867 req.l2_addr_mask[0] = 0xff;
2868 req.l2_addr_mask[1] = 0xff;
2869 req.l2_addr_mask[2] = 0xff;
2870 req.l2_addr_mask[3] = 0xff;
2871 req.l2_addr_mask[4] = 0xff;
2872 req.l2_addr_mask[5] = 0xff;
2873
2874 mutex_lock(&bp->hwrm_cmd_lock);
2875 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2876 if (!rc)
2877 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
2878 resp->l2_filter_id;
2879 mutex_unlock(&bp->hwrm_cmd_lock);
2880 return rc;
2881}
2882
2883static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
2884{
2885 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
2886 int rc = 0;
2887
2888 /* Any associated ntuple filters will also be cleared by firmware. */
2889 mutex_lock(&bp->hwrm_cmd_lock);
2890 for (i = 0; i < num_of_vnics; i++) {
2891 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2892
2893 for (j = 0; j < vnic->uc_filter_count; j++) {
2894 struct hwrm_cfa_l2_filter_free_input req = {0};
2895
2896 bnxt_hwrm_cmd_hdr_init(bp, &req,
2897 HWRM_CFA_L2_FILTER_FREE, -1, -1);
2898
2899 req.l2_filter_id = vnic->fw_l2_filter_id[j];
2900
2901 rc = _hwrm_send_message(bp, &req, sizeof(req),
2902 HWRM_CMD_TIMEOUT);
2903 }
2904 vnic->uc_filter_count = 0;
2905 }
2906 mutex_unlock(&bp->hwrm_cmd_lock);
2907
2908 return rc;
2909}
2910
2911static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
2912{
2913 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2914 struct hwrm_vnic_tpa_cfg_input req = {0};
2915
2916 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
2917
2918 if (tpa_flags) {
2919 u16 mss = bp->dev->mtu - 40;
2920 u32 nsegs, n, segs = 0, flags;
2921
2922 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
2923 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
2924 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
2925 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
2926 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
2927 if (tpa_flags & BNXT_FLAG_GRO)
2928 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
2929
2930 req.flags = cpu_to_le32(flags);
2931
2932 req.enables =
2933 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
2934 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS);
2935
2936 /* Number of segs are log2 units, and first packet is not
2937 * included as part of this units.
2938 */
2939 if (mss <= PAGE_SIZE) {
2940 n = PAGE_SIZE / mss;
2941 nsegs = (MAX_SKB_FRAGS - 1) * n;
2942 } else {
2943 n = mss / PAGE_SIZE;
2944 if (mss & (PAGE_SIZE - 1))
2945 n++;
2946 nsegs = (MAX_SKB_FRAGS - n) / n;
2947 }
2948
2949 segs = ilog2(nsegs);
2950 req.max_agg_segs = cpu_to_le16(segs);
2951 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
2952 }
2953 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
2954
2955 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2956}
2957
2958static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
2959{
2960 u32 i, j, max_rings;
2961 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2962 struct hwrm_vnic_rss_cfg_input req = {0};
2963
2964 if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
2965 return 0;
2966
2967 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
2968 if (set_rss) {
2969 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
2970 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
2971 BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
2972 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
2973
2974 req.hash_type = cpu_to_le32(vnic->hash_type);
2975
2976 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2977 max_rings = bp->rx_nr_rings;
2978 else
2979 max_rings = 1;
2980
2981 /* Fill the RSS indirection table with ring group ids */
2982 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
2983 if (j == max_rings)
2984 j = 0;
2985 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
2986 }
2987
2988 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
2989 req.hash_key_tbl_addr =
2990 cpu_to_le64(vnic->rss_hash_key_dma_addr);
2991 }
2992 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
2993 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2994}
2995
2996static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
2997{
2998 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2999 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3000
3001 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3002 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3003 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3004 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3005 req.enables =
3006 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3007 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3008 /* thresholds not implemented in firmware yet */
3009 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3010 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3011 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3012 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3013}
3014
3015static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3016{
3017 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3018
3019 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3020 req.rss_cos_lb_ctx_id =
3021 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3022
3023 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3024 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3025}
3026
3027static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3028{
3029 int i;
3030
3031 for (i = 0; i < bp->nr_vnics; i++) {
3032 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3033
3034 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3035 bnxt_hwrm_vnic_ctx_free_one(bp, i);
3036 }
3037 bp->rsscos_nr_ctxs = 0;
3038}
3039
3040static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3041{
3042 int rc;
3043 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3044 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3045 bp->hwrm_cmd_resp_addr;
3046
3047 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3048 -1);
3049
3050 mutex_lock(&bp->hwrm_cmd_lock);
3051 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3052 if (!rc)
3053 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3054 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3055 mutex_unlock(&bp->hwrm_cmd_lock);
3056
3057 return rc;
3058}
3059
3060static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3061{
3062 int grp_idx = 0;
3063 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3064 struct hwrm_vnic_cfg_input req = {0};
3065
3066 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3067 /* Only RSS support for now TBD: COS & LB */
3068 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
3069 VNIC_CFG_REQ_ENABLES_RSS_RULE);
3070 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3071 req.cos_rule = cpu_to_le16(0xffff);
3072 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3073 grp_idx = 0;
3074 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3075 grp_idx = vnic_id - 1;
3076
3077 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3078 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3079
3080 req.lb_rule = cpu_to_le16(0xffff);
3081 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3082 VLAN_HLEN);
3083
3084 if (bp->flags & BNXT_FLAG_STRIP_VLAN)
3085 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3086
3087 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3088}
3089
3090static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3091{
3092 u32 rc = 0;
3093
3094 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3095 struct hwrm_vnic_free_input req = {0};
3096
3097 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3098 req.vnic_id =
3099 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3100
3101 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3102 if (rc)
3103 return rc;
3104 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3105 }
3106 return rc;
3107}
3108
3109static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3110{
3111 u16 i;
3112
3113 for (i = 0; i < bp->nr_vnics; i++)
3114 bnxt_hwrm_vnic_free_one(bp, i);
3115}
3116
3117static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, u16 start_grp_id,
3118 u16 end_grp_id)
3119{
3120 u32 rc = 0, i, j;
3121 struct hwrm_vnic_alloc_input req = {0};
3122 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3123
3124 /* map ring groups to this vnic */
3125 for (i = start_grp_id, j = 0; i < end_grp_id; i++, j++) {
3126 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) {
3127 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3128 j, (end_grp_id - start_grp_id));
3129 break;
3130 }
3131 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3132 bp->grp_info[i].fw_grp_id;
3133 }
3134
3135 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3136 if (vnic_id == 0)
3137 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3138
3139 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3140
3141 mutex_lock(&bp->hwrm_cmd_lock);
3142 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3143 if (!rc)
3144 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3145 mutex_unlock(&bp->hwrm_cmd_lock);
3146 return rc;
3147}
3148
3149static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3150{
3151 u16 i;
3152 u32 rc = 0;
3153
3154 mutex_lock(&bp->hwrm_cmd_lock);
3155 for (i = 0; i < bp->rx_nr_rings; i++) {
3156 struct hwrm_ring_grp_alloc_input req = {0};
3157 struct hwrm_ring_grp_alloc_output *resp =
3158 bp->hwrm_cmd_resp_addr;
3159
3160 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3161
3162 req.cr = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3163 req.rr = cpu_to_le16(bp->grp_info[i].rx_fw_ring_id);
3164 req.ar = cpu_to_le16(bp->grp_info[i].agg_fw_ring_id);
3165 req.sc = cpu_to_le16(bp->grp_info[i].fw_stats_ctx);
3166
3167 rc = _hwrm_send_message(bp, &req, sizeof(req),
3168 HWRM_CMD_TIMEOUT);
3169 if (rc)
3170 break;
3171
3172 bp->grp_info[i].fw_grp_id = le32_to_cpu(resp->ring_group_id);
3173 }
3174 mutex_unlock(&bp->hwrm_cmd_lock);
3175 return rc;
3176}
3177
3178static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3179{
3180 u16 i;
3181 u32 rc = 0;
3182 struct hwrm_ring_grp_free_input req = {0};
3183
3184 if (!bp->grp_info)
3185 return 0;
3186
3187 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3188
3189 mutex_lock(&bp->hwrm_cmd_lock);
3190 for (i = 0; i < bp->cp_nr_rings; i++) {
3191 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3192 continue;
3193 req.ring_group_id =
3194 cpu_to_le32(bp->grp_info[i].fw_grp_id);
3195
3196 rc = _hwrm_send_message(bp, &req, sizeof(req),
3197 HWRM_CMD_TIMEOUT);
3198 if (rc)
3199 break;
3200 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3201 }
3202 mutex_unlock(&bp->hwrm_cmd_lock);
3203 return rc;
3204}
3205
3206static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3207 struct bnxt_ring_struct *ring,
3208 u32 ring_type, u32 map_index,
3209 u32 stats_ctx_id)
3210{
3211 int rc = 0, err = 0;
3212 struct hwrm_ring_alloc_input req = {0};
3213 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3214 u16 ring_id;
3215
3216 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3217
3218 req.enables = 0;
3219 if (ring->nr_pages > 1) {
3220 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3221 /* Page size is in log2 units */
3222 req.page_size = BNXT_PAGE_SHIFT;
3223 req.page_tbl_depth = 1;
3224 } else {
3225 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
3226 }
3227 req.fbo = 0;
3228 /* Association of ring index with doorbell index and MSIX number */
3229 req.logical_id = cpu_to_le16(map_index);
3230
3231 switch (ring_type) {
3232 case HWRM_RING_ALLOC_TX:
3233 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3234 /* Association of transmit ring with completion ring */
3235 req.cmpl_ring_id =
3236 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3237 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3238 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3239 req.queue_id = cpu_to_le16(ring->queue_id);
3240 break;
3241 case HWRM_RING_ALLOC_RX:
3242 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3243 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3244 break;
3245 case HWRM_RING_ALLOC_AGG:
3246 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3247 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3248 break;
3249 case HWRM_RING_ALLOC_CMPL:
3250 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3251 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3252 if (bp->flags & BNXT_FLAG_USING_MSIX)
3253 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3254 break;
3255 default:
3256 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3257 ring_type);
3258 return -1;
3259 }
3260
3261 mutex_lock(&bp->hwrm_cmd_lock);
3262 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3263 err = le16_to_cpu(resp->error_code);
3264 ring_id = le16_to_cpu(resp->ring_id);
3265 mutex_unlock(&bp->hwrm_cmd_lock);
3266
3267 if (rc || err) {
3268 switch (ring_type) {
3269 case RING_FREE_REQ_RING_TYPE_CMPL:
3270 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3271 rc, err);
3272 return -1;
3273
3274 case RING_FREE_REQ_RING_TYPE_RX:
3275 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3276 rc, err);
3277 return -1;
3278
3279 case RING_FREE_REQ_RING_TYPE_TX:
3280 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3281 rc, err);
3282 return -1;
3283
3284 default:
3285 netdev_err(bp->dev, "Invalid ring\n");
3286 return -1;
3287 }
3288 }
3289 ring->fw_ring_id = ring_id;
3290 return rc;
3291}
3292
3293static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3294{
3295 int i, rc = 0;
3296
3297 if (bp->cp_nr_rings) {
3298 for (i = 0; i < bp->cp_nr_rings; i++) {
3299 struct bnxt_napi *bnapi = bp->bnapi[i];
3300 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3301 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3302
3303 rc = hwrm_ring_alloc_send_msg(bp, ring,
3304 HWRM_RING_ALLOC_CMPL, i,
3305 INVALID_STATS_CTX_ID);
3306 if (rc)
3307 goto err_out;
3308 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3309 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3310 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
3311 }
3312 }
3313
3314 if (bp->tx_nr_rings) {
3315 for (i = 0; i < bp->tx_nr_rings; i++) {
3316 struct bnxt_napi *bnapi = bp->bnapi[i];
3317 struct bnxt_tx_ring_info *txr = &bnapi->tx_ring;
3318 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3319 u16 fw_stats_ctx = bp->grp_info[i].fw_stats_ctx;
3320
3321 rc = hwrm_ring_alloc_send_msg(bp, ring,
3322 HWRM_RING_ALLOC_TX, i,
3323 fw_stats_ctx);
3324 if (rc)
3325 goto err_out;
3326 txr->tx_doorbell = bp->bar1 + i * 0x80;
3327 }
3328 }
3329
3330 if (bp->rx_nr_rings) {
3331 for (i = 0; i < bp->rx_nr_rings; i++) {
3332 struct bnxt_napi *bnapi = bp->bnapi[i];
3333 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
3334 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3335
3336 rc = hwrm_ring_alloc_send_msg(bp, ring,
3337 HWRM_RING_ALLOC_RX, i,
3338 INVALID_STATS_CTX_ID);
3339 if (rc)
3340 goto err_out;
3341 rxr->rx_doorbell = bp->bar1 + i * 0x80;
3342 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
3343 bp->grp_info[i].rx_fw_ring_id = ring->fw_ring_id;
3344 }
3345 }
3346
3347 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3348 for (i = 0; i < bp->rx_nr_rings; i++) {
3349 struct bnxt_napi *bnapi = bp->bnapi[i];
3350 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
3351 struct bnxt_ring_struct *ring =
3352 &rxr->rx_agg_ring_struct;
3353
3354 rc = hwrm_ring_alloc_send_msg(bp, ring,
3355 HWRM_RING_ALLOC_AGG,
3356 bp->rx_nr_rings + i,
3357 INVALID_STATS_CTX_ID);
3358 if (rc)
3359 goto err_out;
3360
3361 rxr->rx_agg_doorbell =
3362 bp->bar1 + (bp->rx_nr_rings + i) * 0x80;
3363 writel(DB_KEY_RX | rxr->rx_agg_prod,
3364 rxr->rx_agg_doorbell);
3365 bp->grp_info[i].agg_fw_ring_id = ring->fw_ring_id;
3366 }
3367 }
3368err_out:
3369 return rc;
3370}
3371
3372static int hwrm_ring_free_send_msg(struct bnxt *bp,
3373 struct bnxt_ring_struct *ring,
3374 u32 ring_type, int cmpl_ring_id)
3375{
3376 int rc;
3377 struct hwrm_ring_free_input req = {0};
3378 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3379 u16 error_code;
3380
3381 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, -1, -1);
3382 req.ring_type = ring_type;
3383 req.ring_id = cpu_to_le16(ring->fw_ring_id);
3384
3385 mutex_lock(&bp->hwrm_cmd_lock);
3386 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3387 error_code = le16_to_cpu(resp->error_code);
3388 mutex_unlock(&bp->hwrm_cmd_lock);
3389
3390 if (rc || error_code) {
3391 switch (ring_type) {
3392 case RING_FREE_REQ_RING_TYPE_CMPL:
3393 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3394 rc);
3395 return rc;
3396 case RING_FREE_REQ_RING_TYPE_RX:
3397 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3398 rc);
3399 return rc;
3400 case RING_FREE_REQ_RING_TYPE_TX:
3401 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3402 rc);
3403 return rc;
3404 default:
3405 netdev_err(bp->dev, "Invalid ring\n");
3406 return -1;
3407 }
3408 }
3409 return 0;
3410}
3411
3412static int bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
3413{
3414 int i, rc = 0;
3415
3416 if (!bp->bnapi)
3417 return 0;
3418
3419 if (bp->tx_nr_rings) {
3420 for (i = 0; i < bp->tx_nr_rings; i++) {
3421 struct bnxt_napi *bnapi = bp->bnapi[i];
3422 struct bnxt_tx_ring_info *txr = &bnapi->tx_ring;
3423 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3424 u32 cmpl_ring_id = bp->grp_info[i].cp_fw_ring_id;
3425
3426 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3427 hwrm_ring_free_send_msg(
3428 bp, ring,
3429 RING_FREE_REQ_RING_TYPE_TX,
3430 close_path ? cmpl_ring_id :
3431 INVALID_HW_RING_ID);
3432 ring->fw_ring_id = INVALID_HW_RING_ID;
3433 }
3434 }
3435 }
3436
3437 if (bp->rx_nr_rings) {
3438 for (i = 0; i < bp->rx_nr_rings; i++) {
3439 struct bnxt_napi *bnapi = bp->bnapi[i];
3440 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
3441 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3442 u32 cmpl_ring_id = bp->grp_info[i].cp_fw_ring_id;
3443
3444 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3445 hwrm_ring_free_send_msg(
3446 bp, ring,
3447 RING_FREE_REQ_RING_TYPE_RX,
3448 close_path ? cmpl_ring_id :
3449 INVALID_HW_RING_ID);
3450 ring->fw_ring_id = INVALID_HW_RING_ID;
3451 bp->grp_info[i].rx_fw_ring_id =
3452 INVALID_HW_RING_ID;
3453 }
3454 }
3455 }
3456
3457 if (bp->rx_agg_nr_pages) {
3458 for (i = 0; i < bp->rx_nr_rings; i++) {
3459 struct bnxt_napi *bnapi = bp->bnapi[i];
3460 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
3461 struct bnxt_ring_struct *ring =
3462 &rxr->rx_agg_ring_struct;
3463 u32 cmpl_ring_id = bp->grp_info[i].cp_fw_ring_id;
3464
3465 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3466 hwrm_ring_free_send_msg(
3467 bp, ring,
3468 RING_FREE_REQ_RING_TYPE_RX,
3469 close_path ? cmpl_ring_id :
3470 INVALID_HW_RING_ID);
3471 ring->fw_ring_id = INVALID_HW_RING_ID;
3472 bp->grp_info[i].agg_fw_ring_id =
3473 INVALID_HW_RING_ID;
3474 }
3475 }
3476 }
3477
3478 if (bp->cp_nr_rings) {
3479 for (i = 0; i < bp->cp_nr_rings; i++) {
3480 struct bnxt_napi *bnapi = bp->bnapi[i];
3481 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3482 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3483
3484 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3485 hwrm_ring_free_send_msg(
3486 bp, ring,
3487 RING_FREE_REQ_RING_TYPE_CMPL,
3488 INVALID_HW_RING_ID);
3489 ring->fw_ring_id = INVALID_HW_RING_ID;
3490 bp->grp_info[i].cp_fw_ring_id =
3491 INVALID_HW_RING_ID;
3492 }
3493 }
3494 }
3495
3496 return rc;
3497}
3498
3499int bnxt_hwrm_set_coal(struct bnxt *bp)
3500{
3501 int i, rc = 0;
3502 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
3503 u16 max_buf, max_buf_irq;
3504 u16 buf_tmr, buf_tmr_irq;
3505 u32 flags;
3506
3507 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
3508 -1, -1);
3509
3510 /* Each rx completion (2 records) should be DMAed immediately */
3511 max_buf = min_t(u16, bp->coal_bufs / 4, 2);
3512 /* max_buf must not be zero */
3513 max_buf = clamp_t(u16, max_buf, 1, 63);
3514 max_buf_irq = clamp_t(u16, bp->coal_bufs_irq, 1, 63);
3515 buf_tmr = max_t(u16, bp->coal_ticks / 4, 1);
3516 buf_tmr_irq = max_t(u16, bp->coal_ticks_irq, 1);
3517
3518 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3519
3520 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3521 * if coal_ticks is less than 25 us.
3522 */
3523 if (BNXT_COAL_TIMER_TO_USEC(bp->coal_ticks) < 25)
3524 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3525
3526 req.flags = cpu_to_le16(flags);
3527 req.num_cmpl_dma_aggr = cpu_to_le16(max_buf);
3528 req.num_cmpl_dma_aggr_during_int = cpu_to_le16(max_buf_irq);
3529 req.cmpl_aggr_dma_tmr = cpu_to_le16(buf_tmr);
3530 req.cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmr_irq);
3531 req.int_lat_tmr_min = cpu_to_le16(buf_tmr);
3532 req.int_lat_tmr_max = cpu_to_le16(bp->coal_ticks);
3533 req.num_cmpl_aggr_int = cpu_to_le16(bp->coal_bufs);
3534
3535 mutex_lock(&bp->hwrm_cmd_lock);
3536 for (i = 0; i < bp->cp_nr_rings; i++) {
3537 req.ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3538
3539 rc = _hwrm_send_message(bp, &req, sizeof(req),
3540 HWRM_CMD_TIMEOUT);
3541 if (rc)
3542 break;
3543 }
3544 mutex_unlock(&bp->hwrm_cmd_lock);
3545 return rc;
3546}
3547
3548static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3549{
3550 int rc = 0, i;
3551 struct hwrm_stat_ctx_free_input req = {0};
3552
3553 if (!bp->bnapi)
3554 return 0;
3555
3556 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3557
3558 mutex_lock(&bp->hwrm_cmd_lock);
3559 for (i = 0; i < bp->cp_nr_rings; i++) {
3560 struct bnxt_napi *bnapi = bp->bnapi[i];
3561 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3562
3563 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3564 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3565
3566 rc = _hwrm_send_message(bp, &req, sizeof(req),
3567 HWRM_CMD_TIMEOUT);
3568 if (rc)
3569 break;
3570
3571 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3572 }
3573 }
3574 mutex_unlock(&bp->hwrm_cmd_lock);
3575 return rc;
3576}
3577
3578static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3579{
3580 int rc = 0, i;
3581 struct hwrm_stat_ctx_alloc_input req = {0};
3582 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3583
3584 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3585
3586 req.update_period_ms = cpu_to_le32(1000);
3587
3588 mutex_lock(&bp->hwrm_cmd_lock);
3589 for (i = 0; i < bp->cp_nr_rings; i++) {
3590 struct bnxt_napi *bnapi = bp->bnapi[i];
3591 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3592
3593 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3594
3595 rc = _hwrm_send_message(bp, &req, sizeof(req),
3596 HWRM_CMD_TIMEOUT);
3597 if (rc)
3598 break;
3599
3600 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3601
3602 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3603 }
3604 mutex_unlock(&bp->hwrm_cmd_lock);
3605 return 0;
3606}
3607
3608static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
3609{
3610 int rc = 0;
3611 struct hwrm_func_qcaps_input req = {0};
3612 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3613
3614 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
3615 req.fid = cpu_to_le16(0xffff);
3616
3617 mutex_lock(&bp->hwrm_cmd_lock);
3618 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3619 if (rc)
3620 goto hwrm_func_qcaps_exit;
3621
3622 if (BNXT_PF(bp)) {
3623 struct bnxt_pf_info *pf = &bp->pf;
3624
3625 pf->fw_fid = le16_to_cpu(resp->fid);
3626 pf->port_id = le16_to_cpu(resp->port_id);
3627 memcpy(pf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3628 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3629 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3630 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3631 pf->max_pf_tx_rings = pf->max_tx_rings;
3632 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3633 pf->max_pf_rx_rings = pf->max_rx_rings;
3634 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3635 pf->max_vnics = le16_to_cpu(resp->max_vnics);
3636 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3637 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
3638 pf->max_vfs = le16_to_cpu(resp->max_vfs);
3639 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
3640 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
3641 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
3642 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
3643 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
3644 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
3645 } else {
379a80a1 3646#ifdef CONFIG_BNXT_SRIOV
c0c050c5
MC		 3647 struct bnxt_vf_info *vf = &bp->vf;
3648
3649 vf->fw_fid = le16_to_cpu(resp->fid);
3650 memcpy(vf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3651 if (!is_valid_ether_addr(vf->mac_addr))
3652 random_ether_addr(vf->mac_addr);
3653
3654 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3655 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3656 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3657 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3658 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3659 vf->max_vnics = le16_to_cpu(resp->max_vnics);
3660 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
379a80a1 3661#endif
c0c050c5
MC		 3662 }
3663
3664 bp->tx_push_thresh = 0;
3665 if (resp->flags &
3666 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
3667 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
3668
3669hwrm_func_qcaps_exit:
3670 mutex_unlock(&bp->hwrm_cmd_lock);
3671 return rc;
3672}
3673
3674static int bnxt_hwrm_func_reset(struct bnxt *bp)
3675{
3676 struct hwrm_func_reset_input req = {0};
3677
3678 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
3679 req.enables = 0;
3680
3681 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
3682}
3683
3684static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
3685{
3686 int rc = 0;
3687 struct hwrm_queue_qportcfg_input req = {0};
3688 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
3689 u8 i, *qptr;
3690
3691 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
3692
3693 mutex_lock(&bp->hwrm_cmd_lock);
3694 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3695 if (rc)
3696 goto qportcfg_exit;
3697
3698 if (!resp->max_configurable_queues) {
3699 rc = -EINVAL;
3700 goto qportcfg_exit;
3701 }
3702 bp->max_tc = resp->max_configurable_queues;
3703 if (bp->max_tc > BNXT_MAX_QUEUE)
3704 bp->max_tc = BNXT_MAX_QUEUE;
3705
3706 qptr = &resp->queue_id0;
3707 for (i = 0; i < bp->max_tc; i++) {
3708 bp->q_info[i].queue_id = *qptr++;
3709 bp->q_info[i].queue_profile = *qptr++;
3710 }
3711
3712qportcfg_exit:
3713 mutex_unlock(&bp->hwrm_cmd_lock);
3714 return rc;
3715}
3716
3717static int bnxt_hwrm_ver_get(struct bnxt *bp)
3718{
3719 int rc;
3720 struct hwrm_ver_get_input req = {0};
3721 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
3722
3723 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
3724 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
3725 req.hwrm_intf_min = HWRM_VERSION_MINOR;
3726 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
3727 mutex_lock(&bp->hwrm_cmd_lock);
3728 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3729 if (rc)
3730 goto hwrm_ver_get_exit;
3731
3732 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
3733
3734 if (req.hwrm_intf_maj != resp->hwrm_intf_maj ||
3735 req.hwrm_intf_min != resp->hwrm_intf_min ||
3736 req.hwrm_intf_upd != resp->hwrm_intf_upd) {
3737 netdev_warn(bp->dev, "HWRM interface %d.%d.%d does not match driver interface %d.%d.%d.\n",
3738 resp->hwrm_intf_maj, resp->hwrm_intf_min,
3739 resp->hwrm_intf_upd, req.hwrm_intf_maj,
3740 req.hwrm_intf_min, req.hwrm_intf_upd);
3741 netdev_warn(bp->dev, "Please update driver or firmware with matching interface versions.\n");
3742 }
3743 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "bc %d.%d.%d rm %d.%d.%d",
3744 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
3745 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
3746
3747hwrm_ver_get_exit:
3748 mutex_unlock(&bp->hwrm_cmd_lock);
3749 return rc;
3750}
3751
3752static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
3753{
3754 if (bp->vxlan_port_cnt) {
3755 bnxt_hwrm_tunnel_dst_port_free(
3756 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
3757 }
3758 bp->vxlan_port_cnt = 0;
3759 if (bp->nge_port_cnt) {
3760 bnxt_hwrm_tunnel_dst_port_free(
3761 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
3762 }
3763 bp->nge_port_cnt = 0;
3764}
3765
3766static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
3767{
3768 int rc, i;
3769 u32 tpa_flags = 0;
3770
3771 if (set_tpa)
3772 tpa_flags = bp->flags & BNXT_FLAG_TPA;
3773 for (i = 0; i < bp->nr_vnics; i++) {
3774 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
3775 if (rc) {
3776 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3777 rc, i);
3778 return rc;
3779 }
3780 }
3781 return 0;
3782}
3783
3784static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
3785{
3786 int i;
3787
3788 for (i = 0; i < bp->nr_vnics; i++)
3789 bnxt_hwrm_vnic_set_rss(bp, i, false);
3790}
3791
3792static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
3793 bool irq_re_init)
3794{
3795 if (bp->vnic_info) {
3796 bnxt_hwrm_clear_vnic_filter(bp);
3797 /* clear all RSS setting before free vnic ctx */
3798 bnxt_hwrm_clear_vnic_rss(bp);
3799 bnxt_hwrm_vnic_ctx_free(bp);
3800 /* before free the vnic, undo the vnic tpa settings */
3801 if (bp->flags & BNXT_FLAG_TPA)
3802 bnxt_set_tpa(bp, false);
3803 bnxt_hwrm_vnic_free(bp);
3804 }
3805 bnxt_hwrm_ring_free(bp, close_path);
3806 bnxt_hwrm_ring_grp_free(bp);
3807 if (irq_re_init) {
3808 bnxt_hwrm_stat_ctx_free(bp);
3809 bnxt_hwrm_free_tunnel_ports(bp);
3810 }
3811}
3812
3813static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
3814{
3815 int rc;
3816
3817 /* allocate context for vnic */
3818 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
3819 if (rc) {
3820 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3821 vnic_id, rc);
3822 goto vnic_setup_err;
3823 }
3824 bp->rsscos_nr_ctxs++;
3825
3826 /* configure default vnic, ring grp */
3827 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
3828 if (rc) {
3829 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
3830 vnic_id, rc);
3831 goto vnic_setup_err;
3832 }
3833
3834 /* Enable RSS hashing on vnic */
3835 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
3836 if (rc) {
3837 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
3838 vnic_id, rc);
3839 goto vnic_setup_err;
3840 }
3841
3842 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3843 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
3844 if (rc) {
3845 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
3846 vnic_id, rc);
3847 }
3848 }
3849
3850vnic_setup_err:
3851 return rc;
3852}
3853
3854static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
3855{
3856#ifdef CONFIG_RFS_ACCEL
3857 int i, rc = 0;
3858
3859 for (i = 0; i < bp->rx_nr_rings; i++) {
3860 u16 vnic_id = i + 1;
3861 u16 ring_id = i;
3862
3863 if (vnic_id >= bp->nr_vnics)
3864 break;
3865
3866 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
3867 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, ring_id + 1);
3868 if (rc) {
3869 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3870 vnic_id, rc);
3871 break;
3872 }
3873 rc = bnxt_setup_vnic(bp, vnic_id);
3874 if (rc)
3875 break;
3876 }
3877 return rc;
3878#else
3879 return 0;
3880#endif
3881}
3882
c0c050c5
MC		 3883static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
3884{
3885 int rc = 0;
3886
3887 if (irq_re_init) {
3888 rc = bnxt_hwrm_stat_ctx_alloc(bp);
3889 if (rc) {
3890 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
3891 rc);
3892 goto err_out;
3893 }
3894 }
3895
3896 rc = bnxt_hwrm_ring_alloc(bp);
3897 if (rc) {
3898 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
3899 goto err_out;
3900 }
3901
3902 rc = bnxt_hwrm_ring_grp_alloc(bp);
3903 if (rc) {
3904 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
3905 goto err_out;
3906 }
3907
3908 /* default vnic 0 */
3909 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
3910 if (rc) {
3911 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
3912 goto err_out;
3913 }
3914
3915 rc = bnxt_setup_vnic(bp, 0);
3916 if (rc)
3917 goto err_out;
3918
3919 if (bp->flags & BNXT_FLAG_RFS) {
3920 rc = bnxt_alloc_rfs_vnics(bp);
3921 if (rc)
3922 goto err_out;
3923 }
3924
3925 if (bp->flags & BNXT_FLAG_TPA) {
3926 rc = bnxt_set_tpa(bp, true);
3927 if (rc)
3928 goto err_out;
3929 }
3930
3931 if (BNXT_VF(bp))
3932 bnxt_update_vf_mac(bp);
3933
3934 /* Filter for default vnic 0 */
3935 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
3936 if (rc) {
3937 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
3938 goto err_out;
3939 }
3940 bp->vnic_info[0].uc_filter_count = 1;
3941
3942 bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_UNICAST |
3943 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
3944
3945 if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
3946 bp->vnic_info[0].rx_mask |=
3947 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
3948
3949 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
3950 if (rc) {
3951 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n", rc);
3952 goto err_out;
3953 }
3954
3955 rc = bnxt_hwrm_set_coal(bp);
3956 if (rc)
3957 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
3958 rc);
3959
3960 return 0;
3961
3962err_out:
3963 bnxt_hwrm_resource_free(bp, 0, true);
3964
3965 return rc;
3966}
3967
3968static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
3969{
3970 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
3971 return 0;
3972}
3973
3974static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
3975{
3976 bnxt_init_rx_rings(bp);
3977 bnxt_init_tx_rings(bp);
3978 bnxt_init_ring_grps(bp, irq_re_init);
3979 bnxt_init_vnics(bp);
3980
3981 return bnxt_init_chip(bp, irq_re_init);
3982}
3983
3984static void bnxt_disable_int(struct bnxt *bp)
3985{
3986 int i;
3987
3988 if (!bp->bnapi)
3989 return;
3990
3991 for (i = 0; i < bp->cp_nr_rings; i++) {
3992 struct bnxt_napi *bnapi = bp->bnapi[i];
3993 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3994
3995 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3996 }
3997}
3998
3999static void bnxt_enable_int(struct bnxt *bp)
4000{
4001 int i;
4002
4003 atomic_set(&bp->intr_sem, 0);
4004 for (i = 0; i < bp->cp_nr_rings; i++) {
4005 struct bnxt_napi *bnapi = bp->bnapi[i];
4006 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4007
4008 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4009 }
4010}
4011
4012static int bnxt_set_real_num_queues(struct bnxt *bp)
4013{
4014 int rc;
4015 struct net_device *dev = bp->dev;
4016
4017 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4018 if (rc)
4019 return rc;
4020
4021 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4022 if (rc)
4023 return rc;
4024
4025#ifdef CONFIG_RFS_ACCEL
4026 if (bp->rx_nr_rings)
4027 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4028 if (!dev->rx_cpu_rmap)
4029 rc = -ENOMEM;
4030#endif
4031
4032 return rc;
4033}
4034
4035static int bnxt_setup_msix(struct bnxt *bp)
4036{
4037 struct msix_entry *msix_ent;
4038 struct net_device *dev = bp->dev;
4039 int i, total_vecs, rc = 0;
4040 const int len = sizeof(bp->irq_tbl[0].name);
4041
4042 bp->flags &= ~BNXT_FLAG_USING_MSIX;
4043 total_vecs = bp->cp_nr_rings;
4044
4045 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4046 if (!msix_ent)
4047 return -ENOMEM;
4048
4049 for (i = 0; i < total_vecs; i++) {
4050 msix_ent[i].entry = i;
4051 msix_ent[i].vector = 0;
4052 }
4053
4054 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, 1, total_vecs);
4055 if (total_vecs < 0) {
4056 rc = -ENODEV;
4057 goto msix_setup_exit;
4058 }
4059
4060 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4061 if (bp->irq_tbl) {
4062 int tcs;
4063
4064 /* Trim rings based upon num of vectors allocated */
4065 bp->rx_nr_rings = min_t(int, total_vecs, bp->rx_nr_rings);
4066 bp->tx_nr_rings = min_t(int, total_vecs, bp->tx_nr_rings);
4067 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4068 tcs = netdev_get_num_tc(dev);
4069 if (tcs > 1) {
4070 bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4071 if (bp->tx_nr_rings_per_tc == 0) {
4072 netdev_reset_tc(dev);
4073 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4074 } else {
4075 int i, off, count;
4076
4077 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4078 for (i = 0; i < tcs; i++) {
4079 count = bp->tx_nr_rings_per_tc;
4080 off = i * count;
4081 netdev_set_tc_queue(dev, i, count, off);
4082 }
4083 }
4084 }
4085 bp->cp_nr_rings = max_t(int, bp->rx_nr_rings, bp->tx_nr_rings);
4086
4087 for (i = 0; i < bp->cp_nr_rings; i++) {
4088 bp->irq_tbl[i].vector = msix_ent[i].vector;
4089 snprintf(bp->irq_tbl[i].name, len,
4090 "%s-%s-%d", dev->name, "TxRx", i);
4091 bp->irq_tbl[i].handler = bnxt_msix;
4092 }
4093 rc = bnxt_set_real_num_queues(bp);
4094 if (rc)
4095 goto msix_setup_exit;
4096 } else {
4097 rc = -ENOMEM;
4098 goto msix_setup_exit;
4099 }
4100 bp->flags |= BNXT_FLAG_USING_MSIX;
4101 kfree(msix_ent);
4102 return 0;
4103
4104msix_setup_exit:
4105 netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4106 pci_disable_msix(bp->pdev);
4107 kfree(msix_ent);
4108 return rc;
4109}
4110
4111static int bnxt_setup_inta(struct bnxt *bp)
4112{
4113 int rc;
4114 const int len = sizeof(bp->irq_tbl[0].name);
4115
4116 if (netdev_get_num_tc(bp->dev))
4117 netdev_reset_tc(bp->dev);
4118
4119 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4120 if (!bp->irq_tbl) {
4121 rc = -ENOMEM;
4122 return rc;
4123 }
4124 bp->rx_nr_rings = 1;
4125 bp->tx_nr_rings = 1;
4126 bp->cp_nr_rings = 1;
4127 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4128 bp->irq_tbl[0].vector = bp->pdev->irq;
4129 snprintf(bp->irq_tbl[0].name, len,
4130 "%s-%s-%d", bp->dev->name, "TxRx", 0);
4131 bp->irq_tbl[0].handler = bnxt_inta;
4132 rc = bnxt_set_real_num_queues(bp);
4133 return rc;
4134}
4135
4136static int bnxt_setup_int_mode(struct bnxt *bp)
4137{
4138 int rc = 0;
4139
4140 if (bp->flags & BNXT_FLAG_MSIX_CAP)
4141 rc = bnxt_setup_msix(bp);
4142
4143 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) {
4144 /* fallback to INTA */
4145 rc = bnxt_setup_inta(bp);
4146 }
4147 return rc;
4148}
4149
4150static void bnxt_free_irq(struct bnxt *bp)
4151{
4152 struct bnxt_irq *irq;
4153 int i;
4154
4155#ifdef CONFIG_RFS_ACCEL
4156 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4157 bp->dev->rx_cpu_rmap = NULL;
4158#endif
4159 if (!bp->irq_tbl)
4160 return;
4161
4162 for (i = 0; i < bp->cp_nr_rings; i++) {
4163 irq = &bp->irq_tbl[i];
4164 if (irq->requested)
4165 free_irq(irq->vector, bp->bnapi[i]);
4166 irq->requested = 0;
4167 }
4168 if (bp->flags & BNXT_FLAG_USING_MSIX)
4169 pci_disable_msix(bp->pdev);
4170 kfree(bp->irq_tbl);
4171 bp->irq_tbl = NULL;
4172}
4173
4174static int bnxt_request_irq(struct bnxt *bp)
4175{
4176 int i, rc = 0;
4177 unsigned long flags = 0;
4178#ifdef CONFIG_RFS_ACCEL
4179 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4180#endif
4181
4182 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4183 flags = IRQF_SHARED;
4184
4185 for (i = 0; i < bp->cp_nr_rings; i++) {
4186 struct bnxt_irq *irq = &bp->irq_tbl[i];
4187#ifdef CONFIG_RFS_ACCEL
4188 if (rmap && (i < bp->rx_nr_rings)) {
4189 rc = irq_cpu_rmap_add(rmap, irq->vector);
4190 if (rc)
4191 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
4192 i);
4193 }
4194#endif
4195 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4196 bp->bnapi[i]);
4197 if (rc)
4198 break;
4199
4200 irq->requested = 1;
4201 }
4202 return rc;
4203}
4204
4205static void bnxt_del_napi(struct bnxt *bp)
4206{
4207 int i;
4208
4209 if (!bp->bnapi)
4210 return;
4211
4212 for (i = 0; i < bp->cp_nr_rings; i++) {
4213 struct bnxt_napi *bnapi = bp->bnapi[i];
4214
4215 napi_hash_del(&bnapi->napi);
4216 netif_napi_del(&bnapi->napi);
4217 }
4218}
4219
4220static void bnxt_init_napi(struct bnxt *bp)
4221{
4222 int i;
4223 struct bnxt_napi *bnapi;
4224
4225 if (bp->flags & BNXT_FLAG_USING_MSIX) {
4226 for (i = 0; i < bp->cp_nr_rings; i++) {
4227 bnapi = bp->bnapi[i];
4228 netif_napi_add(bp->dev, &bnapi->napi,
4229 bnxt_poll, 64);
4230 napi_hash_add(&bnapi->napi);
4231 }
4232 } else {
4233 bnapi = bp->bnapi[0];
4234 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
4235 napi_hash_add(&bnapi->napi);
4236 }
4237}
4238
4239static void bnxt_disable_napi(struct bnxt *bp)
4240{
4241 int i;
4242
4243 if (!bp->bnapi)
4244 return;
4245
4246 for (i = 0; i < bp->cp_nr_rings; i++) {
4247 napi_disable(&bp->bnapi[i]->napi);
4248 bnxt_disable_poll(bp->bnapi[i]);
4249 }
4250}
4251
4252static void bnxt_enable_napi(struct bnxt *bp)
4253{
4254 int i;
4255
4256 for (i = 0; i < bp->cp_nr_rings; i++) {
4257 bnxt_enable_poll(bp->bnapi[i]);
4258 napi_enable(&bp->bnapi[i]->napi);
4259 }
4260}
4261
4262static void bnxt_tx_disable(struct bnxt *bp)
4263{
4264 int i;
4265 struct bnxt_napi *bnapi;
4266 struct bnxt_tx_ring_info *txr;
4267 struct netdev_queue *txq;
4268
4269 if (bp->bnapi) {
4270 for (i = 0; i < bp->tx_nr_rings; i++) {
4271 bnapi = bp->bnapi[i];
4272 txr = &bnapi->tx_ring;
4273 txq = netdev_get_tx_queue(bp->dev, i);
4274 __netif_tx_lock(txq, smp_processor_id());
4275 txr->dev_state = BNXT_DEV_STATE_CLOSING;
4276 __netif_tx_unlock(txq);
4277 }
4278 }
4279 /* Stop all TX queues */
4280 netif_tx_disable(bp->dev);
4281 netif_carrier_off(bp->dev);
4282}
4283
4284static void bnxt_tx_enable(struct bnxt *bp)
4285{
4286 int i;
4287 struct bnxt_napi *bnapi;
4288 struct bnxt_tx_ring_info *txr;
4289 struct netdev_queue *txq;
4290
4291 for (i = 0; i < bp->tx_nr_rings; i++) {
4292 bnapi = bp->bnapi[i];
4293 txr = &bnapi->tx_ring;
4294 txq = netdev_get_tx_queue(bp->dev, i);
4295 txr->dev_state = 0;
4296 }
4297 netif_tx_wake_all_queues(bp->dev);
4298 if (bp->link_info.link_up)
4299 netif_carrier_on(bp->dev);
4300}
4301
4302static void bnxt_report_link(struct bnxt *bp)
4303{
4304 if (bp->link_info.link_up) {
4305 const char *duplex;
4306 const char *flow_ctrl;
4307 u16 speed;
4308
4309 netif_carrier_on(bp->dev);
4310 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4311 duplex = "full";
4312 else
4313 duplex = "half";
4314 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4315 flow_ctrl = "ON - receive & transmit";
4316 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4317 flow_ctrl = "ON - transmit";
4318 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4319 flow_ctrl = "ON - receive";
4320 else
4321 flow_ctrl = "none";
4322 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4323 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4324 speed, duplex, flow_ctrl);
4325 } else {
4326 netif_carrier_off(bp->dev);
4327 netdev_err(bp->dev, "NIC Link is Down\n");
4328 }
4329}
4330
4331static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4332{
4333 int rc = 0;
4334 struct bnxt_link_info *link_info = &bp->link_info;
4335 struct hwrm_port_phy_qcfg_input req = {0};
4336 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4337 u8 link_up = link_info->link_up;
4338
4339 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4340
4341 mutex_lock(&bp->hwrm_cmd_lock);
4342 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4343 if (rc) {
4344 mutex_unlock(&bp->hwrm_cmd_lock);
4345 return rc;
4346 }
4347
4348 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4349 link_info->phy_link_status = resp->link;
4350 link_info->duplex = resp->duplex;
4351 link_info->pause = resp->pause;
4352 link_info->auto_mode = resp->auto_mode;
4353 link_info->auto_pause_setting = resp->auto_pause;
4354 link_info->force_pause_setting = resp->force_pause;
4355 link_info->duplex_setting = resp->duplex_setting;
4356 if (link_info->phy_link_status == BNXT_LINK_LINK)
4357 link_info->link_speed = le16_to_cpu(resp->link_speed);
4358 else
4359 link_info->link_speed = 0;
4360 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
4361 link_info->auto_link_speed = le16_to_cpu(resp->auto_link_speed);
4362 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4363 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
4364 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4365 link_info->phy_ver[0] = resp->phy_maj;
4366 link_info->phy_ver[1] = resp->phy_min;
4367 link_info->phy_ver[2] = resp->phy_bld;
4368 link_info->media_type = resp->media_type;
4369 link_info->transceiver = resp->transceiver_type;
4370 link_info->phy_addr = resp->phy_addr;
4371
4372 /* TODO: need to add more logic to report VF link */
4373 if (chng_link_state) {
4374 if (link_info->phy_link_status == BNXT_LINK_LINK)
4375 link_info->link_up = 1;
4376 else
4377 link_info->link_up = 0;
4378 if (link_up != link_info->link_up)
4379 bnxt_report_link(bp);
4380 } else {
4381 /* alwasy link down if not require to update link state */
4382 link_info->link_up = 0;
4383 }
4384 mutex_unlock(&bp->hwrm_cmd_lock);
4385 return 0;
4386}
4387
4388static void
4389bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4390{
4391 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
4392 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4393 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4394 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4395 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4396 req->enables |=
4397 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4398 } else {
4399 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4400 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4401 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4402 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4403 req->enables |=
4404 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
4405 }
4406}
4407
4408static void bnxt_hwrm_set_link_common(struct bnxt *bp,
4409 struct hwrm_port_phy_cfg_input *req)
4410{
4411 u8 autoneg = bp->link_info.autoneg;
4412 u16 fw_link_speed = bp->link_info.req_link_speed;
4413 u32 advertising = bp->link_info.advertising;
4414
4415 if (autoneg & BNXT_AUTONEG_SPEED) {
4416 req->auto_mode |=
4417 PORT_PHY_CFG_REQ_AUTO_MODE_MASK;
4418
4419 req->enables |= cpu_to_le32(
4420 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
4421 req->auto_link_speed_mask = cpu_to_le16(advertising);
4422
4423 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
4424 req->flags |=
4425 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
4426 } else {
4427 req->force_link_speed = cpu_to_le16(fw_link_speed);
4428 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
4429 }
4430
4431 /* currently don't support half duplex */
4432 req->auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL;
4433 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX);
4434 /* tell chimp that the setting takes effect immediately */
4435 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4436}
4437
4438int bnxt_hwrm_set_pause(struct bnxt *bp)
4439{
4440 struct hwrm_port_phy_cfg_input req = {0};
4441 int rc;
4442
4443 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4444 bnxt_hwrm_set_pause_common(bp, &req);
4445
4446 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
4447 bp->link_info.force_link_chng)
4448 bnxt_hwrm_set_link_common(bp, &req);
4449
4450 mutex_lock(&bp->hwrm_cmd_lock);
4451 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4452 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
4453 /* since changing of pause setting doesn't trigger any link
4454 * change event, the driver needs to update the current pause
4455 * result upon successfully return of the phy_cfg command
4456 */
4457 bp->link_info.pause =
4458 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
4459 bp->link_info.auto_pause_setting = 0;
4460 if (!bp->link_info.force_link_chng)
4461 bnxt_report_link(bp);
4462 }
4463 bp->link_info.force_link_chng = false;
4464 mutex_unlock(&bp->hwrm_cmd_lock);
4465 return rc;
4466}
4467
4468int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause)
4469{
4470 struct hwrm_port_phy_cfg_input req = {0};
4471
4472 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4473 if (set_pause)
4474 bnxt_hwrm_set_pause_common(bp, &req);
4475
4476 bnxt_hwrm_set_link_common(bp, &req);
4477 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4478}
4479
4480static int bnxt_update_phy_setting(struct bnxt *bp)
4481{
4482 int rc;
4483 bool update_link = false;
4484 bool update_pause = false;
4485 struct bnxt_link_info *link_info = &bp->link_info;
4486
4487 rc = bnxt_update_link(bp, true);
4488 if (rc) {
4489 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
4490 rc);
4491 return rc;
4492 }
4493 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4494 link_info->auto_pause_setting != link_info->req_flow_ctrl)
4495 update_pause = true;
4496 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4497 link_info->force_pause_setting != link_info->req_flow_ctrl)
4498 update_pause = true;
4499 if (link_info->req_duplex != link_info->duplex_setting)
4500 update_link = true;
4501 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4502 if (BNXT_AUTO_MODE(link_info->auto_mode))
4503 update_link = true;
4504 if (link_info->req_link_speed != link_info->force_link_speed)
4505 update_link = true;
4506 } else {
4507 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
4508 update_link = true;
4509 if (link_info->advertising != link_info->auto_link_speeds)
4510 update_link = true;
4511 if (link_info->req_link_speed != link_info->auto_link_speed)
4512 update_link = true;
4513 }
4514
4515 if (update_link)
4516 rc = bnxt_hwrm_set_link_setting(bp, update_pause);
4517 else if (update_pause)
4518 rc = bnxt_hwrm_set_pause(bp);
4519 if (rc) {
4520 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
4521 rc);
4522 return rc;
4523 }
4524
4525 return rc;
4526}
4527
11809490
JH		 4528/* Common routine to pre-map certain register block to different GRC window.
4529 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4530 * in PF and 3 windows in VF that can be customized to map in different
4531 * register blocks.
4532 */
4533static void bnxt_preset_reg_win(struct bnxt *bp)
4534{
4535 if (BNXT_PF(bp)) {
4536 /* CAG registers map to GRC window #4 */
4537 writel(BNXT_CAG_REG_BASE,
4538 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
4539 }
4540}
4541
c0c050c5
MC		 4542static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4543{
4544 int rc = 0;
4545
11809490 4546 bnxt_preset_reg_win(bp);
c0c050c5
MC		 4547 netif_carrier_off(bp->dev);
4548 if (irq_re_init) {
4549 rc = bnxt_setup_int_mode(bp);
4550 if (rc) {
4551 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
4552 rc);
4553 return rc;
4554 }
4555 }
4556 if ((bp->flags & BNXT_FLAG_RFS) &&
4557 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
4558 /* disable RFS if falling back to INTA */
4559 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
4560 bp->flags &= ~BNXT_FLAG_RFS;
4561 }
4562
4563 rc = bnxt_alloc_mem(bp, irq_re_init);
4564 if (rc) {
4565 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
4566 goto open_err_free_mem;
4567 }
4568
4569 if (irq_re_init) {
4570 bnxt_init_napi(bp);
4571 rc = bnxt_request_irq(bp);
4572 if (rc) {
4573 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
4574 goto open_err;
4575 }
4576 }
4577
4578 bnxt_enable_napi(bp);
4579
4580 rc = bnxt_init_nic(bp, irq_re_init);
4581 if (rc) {
4582 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
4583 goto open_err;
4584 }
4585
4586 if (link_re_init) {
4587 rc = bnxt_update_phy_setting(bp);
4588 if (rc)
4589 goto open_err;
4590 }
4591
4592 if (irq_re_init) {
4593#if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4594 vxlan_get_rx_port(bp->dev);
4595#endif
4596 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4597 bp, htons(0x17c1),
4598 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE))
4599 bp->nge_port_cnt = 1;
4600 }
4601
4602 bp->state = BNXT_STATE_OPEN;
4603 bnxt_enable_int(bp);
4604 /* Enable TX queues */
4605 bnxt_tx_enable(bp);
4606 mod_timer(&bp->timer, jiffies + bp->current_interval);
4607
4608 return 0;
4609
4610open_err:
4611 bnxt_disable_napi(bp);
4612 bnxt_del_napi(bp);
4613
4614open_err_free_mem:
4615 bnxt_free_skbs(bp);
4616 bnxt_free_irq(bp);
4617 bnxt_free_mem(bp, true);
4618 return rc;
4619}
4620
4621/* rtnl_lock held */
4622int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4623{
4624 int rc = 0;
4625
4626 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
4627 if (rc) {
4628 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
4629 dev_close(bp->dev);
4630 }
4631 return rc;
4632}
4633
4634static int bnxt_open(struct net_device *dev)
4635{
4636 struct bnxt *bp = netdev_priv(dev);
4637 int rc = 0;
4638
4639 rc = bnxt_hwrm_func_reset(bp);
4640 if (rc) {
4641 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
4642 rc);
4643 rc = -1;
4644 return rc;
4645 }
4646 return __bnxt_open_nic(bp, true, true);
4647}
4648
4649static void bnxt_disable_int_sync(struct bnxt *bp)
4650{
4651 int i;
4652
4653 atomic_inc(&bp->intr_sem);
4654 if (!netif_running(bp->dev))
4655 return;
4656
4657 bnxt_disable_int(bp);
4658 for (i = 0; i < bp->cp_nr_rings; i++)
4659 synchronize_irq(bp->irq_tbl[i].vector);
4660}
4661
4662int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4663{
4664 int rc = 0;
4665
4666#ifdef CONFIG_BNXT_SRIOV
4667 if (bp->sriov_cfg) {
4668 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
4669 !bp->sriov_cfg,
4670 BNXT_SRIOV_CFG_WAIT_TMO);
4671 if (rc)
4672 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
4673 }
4674#endif
4675 /* Change device state to avoid TX queue wake up's */
4676 bnxt_tx_disable(bp);
4677
4678 bp->state = BNXT_STATE_CLOSED;
4679 cancel_work_sync(&bp->sp_task);
4680
4681 /* Flush rings before disabling interrupts */
4682 bnxt_shutdown_nic(bp, irq_re_init);
4683
4684 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4685
4686 bnxt_disable_napi(bp);
4687 bnxt_disable_int_sync(bp);
4688 del_timer_sync(&bp->timer);
4689 bnxt_free_skbs(bp);
4690
4691 if (irq_re_init) {
4692 bnxt_free_irq(bp);
4693 bnxt_del_napi(bp);
4694 }
4695 bnxt_free_mem(bp, irq_re_init);
4696 return rc;
4697}
4698
4699static int bnxt_close(struct net_device *dev)
4700{
4701 struct bnxt *bp = netdev_priv(dev);
4702
4703 bnxt_close_nic(bp, true, true);
4704 return 0;
4705}
4706
4707/* rtnl_lock held */
4708static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4709{
4710 switch (cmd) {
4711 case SIOCGMIIPHY:
4712 /* fallthru */
4713 case SIOCGMIIREG: {
4714 if (!netif_running(dev))
4715 return -EAGAIN;
4716
4717 return 0;
4718 }
4719
4720 case SIOCSMIIREG:
4721 if (!netif_running(dev))
4722 return -EAGAIN;
4723
4724 return 0;
4725
4726 default:
4727 /* do nothing */
4728 break;
4729 }
4730 return -EOPNOTSUPP;
4731}
4732
4733static struct rtnl_link_stats64 *
4734bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4735{
4736 u32 i;
4737 struct bnxt *bp = netdev_priv(dev);
4738
4739 memset(stats, 0, sizeof(struct rtnl_link_stats64));
4740
4741 if (!bp->bnapi)
4742 return stats;
4743
4744 /* TODO check if we need to synchronize with bnxt_close path */
4745 for (i = 0; i < bp->cp_nr_rings; i++) {
4746 struct bnxt_napi *bnapi = bp->bnapi[i];
4747 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4748 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
4749
4750 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
4751 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
4752 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
4753
4754 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
4755 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
4756 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
4757
4758 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
4759 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
4760 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
4761
4762 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
4763 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
4764 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
4765
4766 stats->rx_missed_errors +=
4767 le64_to_cpu(hw_stats->rx_discard_pkts);
4768
4769 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
4770
4771 stats->rx_dropped += le64_to_cpu(hw_stats->rx_drop_pkts);
4772
4773 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
4774 }
4775
4776 return stats;
4777}
4778
4779static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
4780{
4781 struct net_device *dev = bp->dev;
4782 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4783 struct netdev_hw_addr *ha;
4784 u8 *haddr;
4785 int mc_count = 0;
4786 bool update = false;
4787 int off = 0;
4788
4789 netdev_for_each_mc_addr(ha, dev) {
4790 if (mc_count >= BNXT_MAX_MC_ADDRS) {
4791 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4792 vnic->mc_list_count = 0;
4793 return false;
4794 }
4795 haddr = ha->addr;
4796 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
4797 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
4798 update = true;
4799 }
4800 off += ETH_ALEN;
4801 mc_count++;
4802 }
4803 if (mc_count)
4804 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
4805
4806 if (mc_count != vnic->mc_list_count) {
4807 vnic->mc_list_count = mc_count;
4808 update = true;
4809 }
4810 return update;
4811}
4812
4813static bool bnxt_uc_list_updated(struct bnxt *bp)
4814{
4815 struct net_device *dev = bp->dev;
4816 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4817 struct netdev_hw_addr *ha;
4818 int off = 0;
4819
4820 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
4821 return true;
4822
4823 netdev_for_each_uc_addr(ha, dev) {
4824 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
4825 return true;
4826
4827 off += ETH_ALEN;
4828 }
4829 return false;
4830}
4831
4832static void bnxt_set_rx_mode(struct net_device *dev)
4833{
4834 struct bnxt *bp = netdev_priv(dev);
4835 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4836 u32 mask = vnic->rx_mask;
4837 bool mc_update = false;
4838 bool uc_update;
4839
4840 if (!netif_running(dev))
4841 return;
4842
4843 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
4844 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
4845 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
4846
4847 /* Only allow PF to be in promiscuous mode */
4848 if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4849 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4850
4851 uc_update = bnxt_uc_list_updated(bp);
4852
4853 if (dev->flags & IFF_ALLMULTI) {
4854 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4855 vnic->mc_list_count = 0;
4856 } else {
4857 mc_update = bnxt_mc_list_updated(bp, &mask);
4858 }
4859
4860 if (mask != vnic->rx_mask || uc_update || mc_update) {
4861 vnic->rx_mask = mask;
4862
4863 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
4864 schedule_work(&bp->sp_task);
4865 }
4866}
4867
4868static void bnxt_cfg_rx_mode(struct bnxt *bp)
4869{
4870 struct net_device *dev = bp->dev;
4871 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4872 struct netdev_hw_addr *ha;
4873 int i, off = 0, rc;
4874 bool uc_update;
4875
4876 netif_addr_lock_bh(dev);
4877 uc_update = bnxt_uc_list_updated(bp);
4878 netif_addr_unlock_bh(dev);
4879
4880 if (!uc_update)
4881 goto skip_uc;
4882
4883 mutex_lock(&bp->hwrm_cmd_lock);
4884 for (i = 1; i < vnic->uc_filter_count; i++) {
4885 struct hwrm_cfa_l2_filter_free_input req = {0};
4886
4887 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
4888 -1);
4889
4890 req.l2_filter_id = vnic->fw_l2_filter_id[i];
4891
4892 rc = _hwrm_send_message(bp, &req, sizeof(req),
4893 HWRM_CMD_TIMEOUT);
4894 }
4895 mutex_unlock(&bp->hwrm_cmd_lock);
4896
4897 vnic->uc_filter_count = 1;
4898
4899 netif_addr_lock_bh(dev);
4900 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
4901 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4902 } else {
4903 netdev_for_each_uc_addr(ha, dev) {
4904 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
4905 off += ETH_ALEN;
4906 vnic->uc_filter_count++;
4907 }
4908 }
4909 netif_addr_unlock_bh(dev);
4910
4911 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
4912 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
4913 if (rc) {
4914 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
4915 rc);
4916 vnic->uc_filter_count = i;
4917 }
4918 }
4919
4920skip_uc:
4921 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
4922 if (rc)
4923 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
4924 rc);
4925}
4926
4927static netdev_features_t bnxt_fix_features(struct net_device *dev,
4928 netdev_features_t features)
4929{
4930 return features;
4931}
4932
4933static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
4934{
4935 struct bnxt *bp = netdev_priv(dev);
4936 u32 flags = bp->flags;
4937 u32 changes;
4938 int rc = 0;
4939 bool re_init = false;
4940 bool update_tpa = false;
4941
4942 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
4943 if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
4944 flags |= BNXT_FLAG_GRO;
4945 if (features & NETIF_F_LRO)
4946 flags |= BNXT_FLAG_LRO;
4947
4948 if (features & NETIF_F_HW_VLAN_CTAG_RX)
4949 flags |= BNXT_FLAG_STRIP_VLAN;
4950
4951 if (features & NETIF_F_NTUPLE)
4952 flags |= BNXT_FLAG_RFS;
4953
4954 changes = flags ^ bp->flags;
4955 if (changes & BNXT_FLAG_TPA) {
4956 update_tpa = true;
4957 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
4958 (flags & BNXT_FLAG_TPA) == 0)
4959 re_init = true;
4960 }
4961
4962 if (changes & ~BNXT_FLAG_TPA)
4963 re_init = true;
4964
4965 if (flags != bp->flags) {
4966 u32 old_flags = bp->flags;
4967
4968 bp->flags = flags;
4969
4970 if (!netif_running(dev)) {
4971 if (update_tpa)
4972 bnxt_set_ring_params(bp);
4973 return rc;
4974 }
4975
4976 if (re_init) {
4977 bnxt_close_nic(bp, false, false);
4978 if (update_tpa)
4979 bnxt_set_ring_params(bp);
4980
4981 return bnxt_open_nic(bp, false, false);
4982 }
4983 if (update_tpa) {
4984 rc = bnxt_set_tpa(bp,
4985 (flags & BNXT_FLAG_TPA) ?
4986 true : false);
4987 if (rc)
4988 bp->flags = old_flags;
4989 }
4990 }
4991 return rc;
4992}
4993
4994static void bnxt_dbg_dump_states(struct bnxt *bp)
4995{
4996 int i;
4997 struct bnxt_napi *bnapi;
4998 struct bnxt_tx_ring_info *txr;
4999 struct bnxt_rx_ring_info *rxr;
5000 struct bnxt_cp_ring_info *cpr;
5001
5002 for (i = 0; i < bp->cp_nr_rings; i++) {
5003 bnapi = bp->bnapi[i];
5004 txr = &bnapi->tx_ring;
5005 rxr = &bnapi->rx_ring;
5006 cpr = &bnapi->cp_ring;
5007 if (netif_msg_drv(bp)) {
5008 netdev_info(bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5009 i, txr->tx_ring_struct.fw_ring_id,
5010 txr->tx_prod, txr->tx_cons);
5011 netdev_info(bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5012 i, rxr->rx_ring_struct.fw_ring_id,
5013 rxr->rx_prod,
5014 rxr->rx_agg_ring_struct.fw_ring_id,
5015 rxr->rx_agg_prod, rxr->rx_sw_agg_prod);
5016 netdev_info(bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5017 i, cpr->cp_ring_struct.fw_ring_id,
5018 cpr->cp_raw_cons);
5019 }
5020 }
5021}
5022
5023static void bnxt_reset_task(struct bnxt *bp)
5024{
5025 bnxt_dbg_dump_states(bp);
5026 if (netif_running(bp->dev))
5027 bnxt_tx_disable(bp); /* prevent tx timout again */
5028}
5029
5030static void bnxt_tx_timeout(struct net_device *dev)
5031{
5032 struct bnxt *bp = netdev_priv(dev);
5033
5034 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
5035 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5036 schedule_work(&bp->sp_task);
5037}
5038
5039#ifdef CONFIG_NET_POLL_CONTROLLER
5040static void bnxt_poll_controller(struct net_device *dev)
5041{
5042 struct bnxt *bp = netdev_priv(dev);
5043 int i;
5044
5045 for (i = 0; i < bp->cp_nr_rings; i++) {
5046 struct bnxt_irq *irq = &bp->irq_tbl[i];
5047
5048 disable_irq(irq->vector);
5049 irq->handler(irq->vector, bp->bnapi[i]);
5050 enable_irq(irq->vector);
5051 }
5052}
5053#endif
5054
5055static void bnxt_timer(unsigned long data)
5056{
5057 struct bnxt *bp = (struct bnxt *)data;
5058 struct net_device *dev = bp->dev;
5059
5060 if (!netif_running(dev))
5061 return;
5062
5063 if (atomic_read(&bp->intr_sem) != 0)
5064 goto bnxt_restart_timer;
5065
5066bnxt_restart_timer:
5067 mod_timer(&bp->timer, jiffies + bp->current_interval);
5068}
5069
5070static void bnxt_cfg_ntp_filters(struct bnxt *);
5071
5072static void bnxt_sp_task(struct work_struct *work)
5073{
5074 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5075 int rc;
5076
5077 if (bp->state != BNXT_STATE_OPEN)
5078 return;
5079
5080 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5081 bnxt_cfg_rx_mode(bp);
5082
5083 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5084 bnxt_cfg_ntp_filters(bp);
5085 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5086 rc = bnxt_update_link(bp, true);
5087 if (rc)
5088 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5089 rc);
5090 }
5091 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5092 bnxt_hwrm_exec_fwd_req(bp);
5093 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5094 bnxt_hwrm_tunnel_dst_port_alloc(
5095 bp, bp->vxlan_port,
5096 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5097 }
5098 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5099 bnxt_hwrm_tunnel_dst_port_free(
5100 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5101 }
5102 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
5103 bnxt_reset_task(bp);
5104}
5105
5106static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5107{
5108 int rc;
5109 struct bnxt *bp = netdev_priv(dev);
5110
5111 SET_NETDEV_DEV(dev, &pdev->dev);
5112
5113 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5114 rc = pci_enable_device(pdev);
5115 if (rc) {
5116 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5117 goto init_err;
5118 }
5119
5120 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5121 dev_err(&pdev->dev,
5122 "Cannot find PCI device base address, aborting\n");
5123 rc = -ENODEV;
5124 goto init_err_disable;
5125 }
5126
5127 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5128 if (rc) {
5129 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5130 goto init_err_disable;
5131 }
5132
5133 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5134 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5135 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5136 goto init_err_disable;
5137 }
5138
5139 pci_set_master(pdev);
5140
5141 bp->dev = dev;
5142 bp->pdev = pdev;
5143
5144 bp->bar0 = pci_ioremap_bar(pdev, 0);
5145 if (!bp->bar0) {
5146 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5147 rc = -ENOMEM;
5148 goto init_err_release;
5149 }
5150
5151 bp->bar1 = pci_ioremap_bar(pdev, 2);
5152 if (!bp->bar1) {
5153 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5154 rc = -ENOMEM;
5155 goto init_err_release;
5156 }
5157
5158 bp->bar2 = pci_ioremap_bar(pdev, 4);
5159 if (!bp->bar2) {
5160 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5161 rc = -ENOMEM;
5162 goto init_err_release;
5163 }
5164
5165 INIT_WORK(&bp->sp_task, bnxt_sp_task);
5166
5167 spin_lock_init(&bp->ntp_fltr_lock);
5168
5169 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5170 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5171
5172 bp->coal_ticks = BNXT_USEC_TO_COAL_TIMER(4);
5173 bp->coal_bufs = 20;
5174 bp->coal_ticks_irq = BNXT_USEC_TO_COAL_TIMER(1);
5175 bp->coal_bufs_irq = 2;
5176
5177 init_timer(&bp->timer);
5178 bp->timer.data = (unsigned long)bp;
5179 bp->timer.function = bnxt_timer;
5180 bp->current_interval = BNXT_TIMER_INTERVAL;
5181
5182 bp->state = BNXT_STATE_CLOSED;
5183
5184 return 0;
5185
5186init_err_release:
5187 if (bp->bar2) {
5188 pci_iounmap(pdev, bp->bar2);
5189 bp->bar2 = NULL;
5190 }
5191
5192 if (bp->bar1) {
5193 pci_iounmap(pdev, bp->bar1);
5194 bp->bar1 = NULL;
5195 }
5196
5197 if (bp->bar0) {
5198 pci_iounmap(pdev, bp->bar0);
5199 bp->bar0 = NULL;
5200 }
5201
5202 pci_release_regions(pdev);
5203
5204init_err_disable:
5205 pci_disable_device(pdev);
5206
5207init_err:
5208 return rc;
5209}
5210
5211/* rtnl_lock held */
5212static int bnxt_change_mac_addr(struct net_device *dev, void *p)
5213{
5214 struct sockaddr *addr = p;
1fc2cfd0
JH		 5215 struct bnxt *bp = netdev_priv(dev);
5216 int rc = 0;
c0c050c5
MC		 5217
5218 if (!is_valid_ether_addr(addr->sa_data))
5219 return -EADDRNOTAVAIL;
5220
1fc2cfd0
JH		 5221 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
5222 return 0;
5223
c0c050c5 5224 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1fc2cfd0
JH		 5225 if (netif_running(dev)) {
5226 bnxt_close_nic(bp, false, false);
5227 rc = bnxt_open_nic(bp, false, false);
5228 }
c0c050c5 5229
1fc2cfd0 5230 return rc;
c0c050c5
MC		 5231}
5232
5233/* rtnl_lock held */
5234static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
5235{
5236 struct bnxt *bp = netdev_priv(dev);
5237
5238 if (new_mtu < 60 || new_mtu > 9000)
5239 return -EINVAL;
5240
5241 if (netif_running(dev))
5242 bnxt_close_nic(bp, false, false);
5243
5244 dev->mtu = new_mtu;
5245 bnxt_set_ring_params(bp);
5246
5247 if (netif_running(dev))
5248 return bnxt_open_nic(bp, false, false);
5249
5250 return 0;
5251}
5252
5253static int bnxt_setup_tc(struct net_device *dev, u8 tc)
5254{
5255 struct bnxt *bp = netdev_priv(dev);
5256
5257 if (tc > bp->max_tc) {
5258 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
5259 tc, bp->max_tc);
5260 return -EINVAL;
5261 }
5262
5263 if (netdev_get_num_tc(dev) == tc)
5264 return 0;
5265
5266 if (tc) {
5267 int max_rx_rings, max_tx_rings;
5268
5269 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings);
5270 if (bp->tx_nr_rings_per_tc * tc > max_tx_rings)
5271 return -ENOMEM;
5272 }
5273
5274 /* Needs to close the device and do hw resource re-allocations */
5275 if (netif_running(bp->dev))
5276 bnxt_close_nic(bp, true, false);
5277
5278 if (tc) {
5279 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
5280 netdev_set_num_tc(dev, tc);
5281 } else {
5282 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5283 netdev_reset_tc(dev);
5284 }
5285 bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
5286 bp->num_stat_ctxs = bp->cp_nr_rings;
5287
5288 if (netif_running(bp->dev))
5289 return bnxt_open_nic(bp, true, false);
5290
5291 return 0;
5292}
5293
5294#ifdef CONFIG_RFS_ACCEL
5295static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
5296 struct bnxt_ntuple_filter *f2)
5297{
5298 struct flow_keys *keys1 = &f1->fkeys;
5299 struct flow_keys *keys2 = &f2->fkeys;
5300
5301 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
5302 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
5303 keys1->ports.ports == keys2->ports.ports &&
5304 keys1->basic.ip_proto == keys2->basic.ip_proto &&
5305 keys1->basic.n_proto == keys2->basic.n_proto &&
5306 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
5307 return true;
5308
5309 return false;
5310}
5311
5312static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
5313 u16 rxq_index, u32 flow_id)
5314{
5315 struct bnxt *bp = netdev_priv(dev);
5316 struct bnxt_ntuple_filter *fltr, *new_fltr;
5317 struct flow_keys *fkeys;
5318 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
84e86b98 5319 int rc = 0, idx, bit_id;
c0c050c5
MC		 5320 struct hlist_head *head;
5321
5322 if (skb->encapsulation)
5323 return -EPROTONOSUPPORT;
5324
5325 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
5326 if (!new_fltr)
5327 return -ENOMEM;
5328
5329 fkeys = &new_fltr->fkeys;
5330 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
5331 rc = -EPROTONOSUPPORT;
5332 goto err_free;
5333 }
5334
5335 if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
5336 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
5337 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
5338 rc = -EPROTONOSUPPORT;
5339 goto err_free;
5340 }
5341
5342 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
5343
5344 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
5345 head = &bp->ntp_fltr_hash_tbl[idx];
5346 rcu_read_lock();
5347 hlist_for_each_entry_rcu(fltr, head, hash) {
5348 if (bnxt_fltr_match(fltr, new_fltr)) {
5349 rcu_read_unlock();
5350 rc = 0;
5351 goto err_free;
5352 }
5353 }
5354 rcu_read_unlock();
5355
5356 spin_lock_bh(&bp->ntp_fltr_lock);
84e86b98
MC		 5357 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
5358 BNXT_NTP_FLTR_MAX_FLTR, 0);
5359 if (bit_id < 0) {
c0c050c5
MC		 5360 spin_unlock_bh(&bp->ntp_fltr_lock);
5361 rc = -ENOMEM;
5362 goto err_free;
5363 }
5364
84e86b98 5365 new_fltr->sw_id = (u16)bit_id;
c0c050c5
MC		 5366 new_fltr->flow_id = flow_id;
5367 new_fltr->rxq = rxq_index;
5368 hlist_add_head_rcu(&new_fltr->hash, head);
5369 bp->ntp_fltr_count++;
5370 spin_unlock_bh(&bp->ntp_fltr_lock);
5371
5372 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
5373 schedule_work(&bp->sp_task);
5374
5375 return new_fltr->sw_id;
5376
5377err_free:
5378 kfree(new_fltr);
5379 return rc;
5380}
5381
5382static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5383{
5384 int i;
5385
5386 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
5387 struct hlist_head *head;
5388 struct hlist_node *tmp;
5389 struct bnxt_ntuple_filter *fltr;
5390 int rc;
5391
5392 head = &bp->ntp_fltr_hash_tbl[i];
5393 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
5394 bool del = false;
5395
5396 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
5397 if (rps_may_expire_flow(bp->dev, fltr->rxq,
5398 fltr->flow_id,
5399 fltr->sw_id)) {
5400 bnxt_hwrm_cfa_ntuple_filter_free(bp,
5401 fltr);
5402 del = true;
5403 }
5404 } else {
5405 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
5406 fltr);
5407 if (rc)
5408 del = true;
5409 else
5410 set_bit(BNXT_FLTR_VALID, &fltr->state);
5411 }
5412
5413 if (del) {
5414 spin_lock_bh(&bp->ntp_fltr_lock);
5415 hlist_del_rcu(&fltr->hash);
5416 bp->ntp_fltr_count--;
5417 spin_unlock_bh(&bp->ntp_fltr_lock);
5418 synchronize_rcu();
5419 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
5420 kfree(fltr);
5421 }
5422 }
5423 }
5424}
5425
5426#else
5427
5428static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5429{
5430}
5431
5432#endif /* CONFIG_RFS_ACCEL */
5433
5434static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5435 __be16 port)
5436{
5437 struct bnxt *bp = netdev_priv(dev);
5438
5439 if (!netif_running(dev))
5440 return;
5441
5442 if (sa_family != AF_INET6 && sa_family != AF_INET)
5443 return;
5444
5445 if (bp->vxlan_port_cnt && bp->vxlan_port != port)
5446 return;
5447
5448 bp->vxlan_port_cnt++;
5449 if (bp->vxlan_port_cnt == 1) {
5450 bp->vxlan_port = port;
5451 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
5452 schedule_work(&bp->sp_task);
5453 }
5454}
5455
5456static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5457 __be16 port)
5458{
5459 struct bnxt *bp = netdev_priv(dev);
5460
5461 if (!netif_running(dev))
5462 return;
5463
5464 if (sa_family != AF_INET6 && sa_family != AF_INET)
5465 return;
5466
5467 if (bp->vxlan_port_cnt && bp->vxlan_port == port) {
5468 bp->vxlan_port_cnt--;
5469
5470 if (bp->vxlan_port_cnt == 0) {
5471 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
5472 schedule_work(&bp->sp_task);
5473 }
5474 }
5475}
5476
5477static const struct net_device_ops bnxt_netdev_ops = {
5478 .ndo_open = bnxt_open,
5479 .ndo_start_xmit = bnxt_start_xmit,
5480 .ndo_stop = bnxt_close,
5481 .ndo_get_stats64 = bnxt_get_stats64,
5482 .ndo_set_rx_mode = bnxt_set_rx_mode,
5483 .ndo_do_ioctl = bnxt_ioctl,
5484 .ndo_validate_addr = eth_validate_addr,
5485 .ndo_set_mac_address = bnxt_change_mac_addr,
5486 .ndo_change_mtu = bnxt_change_mtu,
5487 .ndo_fix_features = bnxt_fix_features,
5488 .ndo_set_features = bnxt_set_features,
5489 .ndo_tx_timeout = bnxt_tx_timeout,
5490#ifdef CONFIG_BNXT_SRIOV
5491 .ndo_get_vf_config = bnxt_get_vf_config,
5492 .ndo_set_vf_mac = bnxt_set_vf_mac,
5493 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
5494 .ndo_set_vf_rate = bnxt_set_vf_bw,
5495 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
5496 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
5497#endif
5498#ifdef CONFIG_NET_POLL_CONTROLLER
5499 .ndo_poll_controller = bnxt_poll_controller,
5500#endif
5501 .ndo_setup_tc = bnxt_setup_tc,
5502#ifdef CONFIG_RFS_ACCEL
5503 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
5504#endif
5505 .ndo_add_vxlan_port = bnxt_add_vxlan_port,
5506 .ndo_del_vxlan_port = bnxt_del_vxlan_port,
5507#ifdef CONFIG_NET_RX_BUSY_POLL
5508 .ndo_busy_poll = bnxt_busy_poll,
5509#endif
5510};
5511
5512static void bnxt_remove_one(struct pci_dev *pdev)
5513{
5514 struct net_device *dev = pci_get_drvdata(pdev);
5515 struct bnxt *bp = netdev_priv(dev);
5516
5517 if (BNXT_PF(bp))
5518 bnxt_sriov_disable(bp);
5519
5520 unregister_netdev(dev);
5521 cancel_work_sync(&bp->sp_task);
5522 bp->sp_event = 0;
5523
5524 bnxt_free_hwrm_resources(bp);
5525 pci_iounmap(pdev, bp->bar2);
5526 pci_iounmap(pdev, bp->bar1);
5527 pci_iounmap(pdev, bp->bar0);
5528 free_netdev(dev);
5529
5530 pci_release_regions(pdev);
5531 pci_disable_device(pdev);
5532}
5533
5534static int bnxt_probe_phy(struct bnxt *bp)
5535{
5536 int rc = 0;
5537 struct bnxt_link_info *link_info = &bp->link_info;
5538 char phy_ver[PHY_VER_STR_LEN];
5539
5540 rc = bnxt_update_link(bp, false);
5541 if (rc) {
5542 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
5543 rc);
5544 return rc;
5545 }
5546
5547 /*initialize the ethool setting copy with NVM settings */
5548 if (BNXT_AUTO_MODE(link_info->auto_mode))
5549 link_info->autoneg |= BNXT_AUTONEG_SPEED;
5550
5551 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) {
5552 if (link_info->auto_pause_setting == BNXT_LINK_PAUSE_BOTH)
5553 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
5554 link_info->req_flow_ctrl = link_info->auto_pause_setting;
5555 } else if (link_info->force_pause_setting & BNXT_LINK_PAUSE_BOTH) {
5556 link_info->req_flow_ctrl = link_info->force_pause_setting;
5557 }
5558 link_info->req_duplex = link_info->duplex_setting;
5559 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
5560 link_info->req_link_speed = link_info->auto_link_speed;
5561 else
5562 link_info->req_link_speed = link_info->force_link_speed;
5563 link_info->advertising = link_info->auto_link_speeds;
5564 snprintf(phy_ver, PHY_VER_STR_LEN, " ph %d.%d.%d",
5565 link_info->phy_ver[0],
5566 link_info->phy_ver[1],
5567 link_info->phy_ver[2]);
5568 strcat(bp->fw_ver_str, phy_ver);
5569 return rc;
5570}
5571
5572static int bnxt_get_max_irq(struct pci_dev *pdev)
5573{
5574 u16 ctrl;
5575
5576 if (!pdev->msix_cap)
5577 return 1;
5578
5579 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
5580 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
5581}
5582
5583void bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx)
5584{
379a80a1 5585 int max_rings = 0;
c0c050c5
MC		 5586
5587 if (BNXT_PF(bp)) {
5588 *max_tx = bp->pf.max_pf_tx_rings;
5589 *max_rx = bp->pf.max_pf_rx_rings;
5590 max_rings = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5591 max_rings = min_t(int, max_rings, bp->pf.max_stat_ctxs);
5592 } else {
379a80a1 5593#ifdef CONFIG_BNXT_SRIOV
c0c050c5
MC		 5594 *max_tx = bp->vf.max_tx_rings;
5595 *max_rx = bp->vf.max_rx_rings;
5596 max_rings = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
5597 max_rings = min_t(int, max_rings, bp->vf.max_stat_ctxs);
379a80a1 5598#endif
c0c050c5
MC		 5599 }
5600 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5601 *max_rx >>= 1;
5602
5603 *max_rx = min_t(int, *max_rx, max_rings);
5604 *max_tx = min_t(int, *max_tx, max_rings);
5605}
5606
5607static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5608{
5609 static int version_printed;
5610 struct net_device *dev;
5611 struct bnxt *bp;
5612 int rc, max_rx_rings, max_tx_rings, max_irqs, dflt_rings;
5613
5614 if (version_printed++ == 0)
5615 pr_info("%s", version);
5616
5617 max_irqs = bnxt_get_max_irq(pdev);
5618 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
5619 if (!dev)
5620 return -ENOMEM;
5621
5622 bp = netdev_priv(dev);
5623
5624 if (bnxt_vf_pciid(ent->driver_data))
5625 bp->flags |= BNXT_FLAG_VF;
5626
5627 if (pdev->msix_cap) {
5628 bp->flags |= BNXT_FLAG_MSIX_CAP;
5629 if (BNXT_PF(bp))
5630 bp->flags |= BNXT_FLAG_RFS;
5631 }
5632
5633 rc = bnxt_init_board(pdev, dev);
5634 if (rc < 0)
5635 goto init_err_free;
5636
5637 dev->netdev_ops = &bnxt_netdev_ops;
5638 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
5639 dev->ethtool_ops = &bnxt_ethtool_ops;
5640
5641 pci_set_drvdata(pdev, dev);
5642
5643 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5644 NETIF_F_TSO | NETIF_F_TSO6 |
5645 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5646 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT |
5647 NETIF_F_RXHASH |
5648 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
5649
5650 if (bp->flags & BNXT_FLAG_RFS)
5651 dev->hw_features |= NETIF_F_NTUPLE;
5652
5653 dev->hw_enc_features =
5654 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5655 NETIF_F_TSO | NETIF_F_TSO6 |
5656 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5657 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
5658 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
5659 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
5660 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
5661 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
5662 dev->priv_flags |= IFF_UNICAST_FLT;
5663
5664#ifdef CONFIG_BNXT_SRIOV
5665 init_waitqueue_head(&bp->sriov_cfg_wait);
5666#endif
5667 rc = bnxt_alloc_hwrm_resources(bp);
5668 if (rc)
5669 goto init_err;
5670
5671 mutex_init(&bp->hwrm_cmd_lock);
5672 bnxt_hwrm_ver_get(bp);
5673
5674 rc = bnxt_hwrm_func_drv_rgtr(bp);
5675 if (rc)
5676 goto init_err;
5677
5678 /* Get the MAX capabilities for this function */
5679 rc = bnxt_hwrm_func_qcaps(bp);
5680 if (rc) {
5681 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
5682 rc);
5683 rc = -1;
5684 goto init_err;
5685 }
5686
5687 rc = bnxt_hwrm_queue_qportcfg(bp);
5688 if (rc) {
5689 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
5690 rc);
5691 rc = -1;
5692 goto init_err;
5693 }
5694
5695 bnxt_set_tpa_flags(bp);
5696 bnxt_set_ring_params(bp);
5697 dflt_rings = netif_get_num_default_rss_queues();
5698 if (BNXT_PF(bp)) {
5699 memcpy(dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
5700 bp->pf.max_irqs = max_irqs;
5701 } else {
379a80a1 5702#if defined(CONFIG_BNXT_SRIOV)
c0c050c5
MC		 5703 memcpy(dev->dev_addr, bp->vf.mac_addr, ETH_ALEN);
5704 bp->vf.max_irqs = max_irqs;
379a80a1 5705#endif
c0c050c5
MC		 5706 }
5707 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings);
5708 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
5709 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
5710 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5711 bp->cp_nr_rings = max_t(int, bp->rx_nr_rings, bp->tx_nr_rings);
5712 bp->num_stat_ctxs = bp->cp_nr_rings;
5713
5714 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
5715 bp->flags |= BNXT_FLAG_STRIP_VLAN;
5716
5717 rc = bnxt_probe_phy(bp);
5718 if (rc)
5719 goto init_err;
5720
5721 rc = register_netdev(dev);
5722 if (rc)
5723 goto init_err;
5724
5725 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
5726 board_info[ent->driver_data].name,
5727 (long)pci_resource_start(pdev, 0), dev->dev_addr);
5728
5729 return 0;
5730
5731init_err:
5732 pci_iounmap(pdev, bp->bar0);
5733 pci_release_regions(pdev);
5734 pci_disable_device(pdev);
5735
5736init_err_free:
5737 free_netdev(dev);
5738 return rc;
5739}
5740
5741static struct pci_driver bnxt_pci_driver = {
5742 .name = DRV_MODULE_NAME,
5743 .id_table = bnxt_pci_tbl,
5744 .probe = bnxt_init_one,
5745 .remove = bnxt_remove_one,
5746#if defined(CONFIG_BNXT_SRIOV)
5747 .sriov_configure = bnxt_sriov_configure,
5748#endif
5749};
5750
5751module_pci_driver(bnxt_pci_driver);
Linux kernel - Deliverables
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