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bnxt_en: Need memory barrier when processing the completion ring.
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
CommitLineData
c0c050c5
MC		 1/* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2015 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11
12#include <linux/stringify.h>
13#include <linux/kernel.h>
14#include <linux/timer.h>
15#include <linux/errno.h>
16#include <linux/ioport.h>
17#include <linux/slab.h>
18#include <linux/vmalloc.h>
19#include <linux/interrupt.h>
20#include <linux/pci.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/dma-mapping.h>
25#include <linux/bitops.h>
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/delay.h>
29#include <asm/byteorder.h>
30#include <asm/page.h>
31#include <linux/time.h>
32#include <linux/mii.h>
33#include <linux/if.h>
34#include <linux/if_vlan.h>
35#include <net/ip.h>
36#include <net/tcp.h>
37#include <net/udp.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41#include <net/vxlan.h>
42#endif
43#ifdef CONFIG_NET_RX_BUSY_POLL
44#include <net/busy_poll.h>
45#endif
46#include <linux/workqueue.h>
47#include <linux/prefetch.h>
48#include <linux/cache.h>
49#include <linux/log2.h>
50#include <linux/aer.h>
51#include <linux/bitmap.h>
52#include <linux/cpu_rmap.h>
53
54#include "bnxt_hsi.h"
55#include "bnxt.h"
56#include "bnxt_sriov.h"
57#include "bnxt_ethtool.h"
58
59#define BNXT_TX_TIMEOUT (5 * HZ)
60
61static const char version[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
63
64MODULE_LICENSE("GPL");
65MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66MODULE_VERSION(DRV_MODULE_VERSION);
67
68#define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69#define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70#define BNXT_RX_COPY_THRESH 256
71
4419dbe6 72#define BNXT_TX_PUSH_THRESH 164
c0c050c5
MC		 73
74enum board_idx {
fbc9a523 75 BCM57301,
c0c050c5
MC		 76 BCM57302,
77 BCM57304,
fbc9a523 78 BCM57402,
c0c050c5
MC		 79 BCM57404,
80 BCM57406,
81 BCM57304_VF,
82 BCM57404_VF,
83};
84
85/* indexed by enum above */
86static const struct {
87 char *name;
88} board_info[] = {
fbc9a523
DC		 89 { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
90 { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
c0c050c5 91 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
fbc9a523 92 { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
c0c050c5 93 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
fbc9a523 94 { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
c0c050c5
MC		 95 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
96 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
97};
98
99static const struct pci_device_id bnxt_pci_tbl[] = {
fbc9a523 100 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
c0c050c5
MC		 101 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
102 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
fbc9a523 103 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
c0c050c5
MC		 104 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
105 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
106#ifdef CONFIG_BNXT_SRIOV
107 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
108 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
109#endif
110 { 0 }
111};
112
113MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
114
115static const u16 bnxt_vf_req_snif[] = {
116 HWRM_FUNC_CFG,
117 HWRM_PORT_PHY_QCFG,
118 HWRM_CFA_L2_FILTER_ALLOC,
119};
120
121static bool bnxt_vf_pciid(enum board_idx idx)
122{
123 return (idx == BCM57304_VF || idx == BCM57404_VF);
124}
125
126#define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
127#define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
128#define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
129
130#define BNXT_CP_DB_REARM(db, raw_cons) \
131 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
132
133#define BNXT_CP_DB(db, raw_cons) \
134 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
135
136#define BNXT_CP_DB_IRQ_DIS(db) \
137 writel(DB_CP_IRQ_DIS_FLAGS, db)
138
139static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
140{
141 /* Tell compiler to fetch tx indices from memory. */
142 barrier();
143
144 return bp->tx_ring_size -
145 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
146}
147
148static const u16 bnxt_lhint_arr[] = {
149 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
150 TX_BD_FLAGS_LHINT_512_TO_1023,
151 TX_BD_FLAGS_LHINT_1024_TO_2047,
152 TX_BD_FLAGS_LHINT_1024_TO_2047,
153 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
154 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
155 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
156 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
157 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
158 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
159 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
160 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
161 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
162 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
163 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
164 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
165 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
166 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
167 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
168};
169
170static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
171{
172 struct bnxt *bp = netdev_priv(dev);
173 struct tx_bd *txbd;
174 struct tx_bd_ext *txbd1;
175 struct netdev_queue *txq;
176 int i;
177 dma_addr_t mapping;
178 unsigned int length, pad = 0;
179 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
180 u16 prod, last_frag;
181 struct pci_dev *pdev = bp->pdev;
c0c050c5
MC		 182 struct bnxt_tx_ring_info *txr;
183 struct bnxt_sw_tx_bd *tx_buf;
184
185 i = skb_get_queue_mapping(skb);
186 if (unlikely(i >= bp->tx_nr_rings)) {
187 dev_kfree_skb_any(skb);
188 return NETDEV_TX_OK;
189 }
190
b6ab4b01 191 txr = &bp->tx_ring[i];
c0c050c5
MC		 192 txq = netdev_get_tx_queue(dev, i);
193 prod = txr->tx_prod;
194
195 free_size = bnxt_tx_avail(bp, txr);
196 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
197 netif_tx_stop_queue(txq);
198 return NETDEV_TX_BUSY;
199 }
200
201 length = skb->len;
202 len = skb_headlen(skb);
203 last_frag = skb_shinfo(skb)->nr_frags;
204
205 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
206
207 txbd->tx_bd_opaque = prod;
208
209 tx_buf = &txr->tx_buf_ring[prod];
210 tx_buf->skb = skb;
211 tx_buf->nr_frags = last_frag;
212
213 vlan_tag_flags = 0;
214 cfa_action = 0;
215 if (skb_vlan_tag_present(skb)) {
216 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
217 skb_vlan_tag_get(skb);
218 /* Currently supports 8021Q, 8021AD vlan offloads
219 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
220 */
221 if (skb->vlan_proto == htons(ETH_P_8021Q))
222 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
223 }
224
225 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
4419dbe6
MC		 226 struct tx_push_buffer *tx_push_buf = txr->tx_push;
227 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
228 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
229 void *pdata = tx_push_buf->data;
230 u64 *end;
231 int j, push_len;
c0c050c5
MC		 232
233 /* Set COAL_NOW to be ready quickly for the next push */
234 tx_push->tx_bd_len_flags_type =
235 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
236 TX_BD_TYPE_LONG_TX_BD |
237 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
238 TX_BD_FLAGS_COAL_NOW |
239 TX_BD_FLAGS_PACKET_END |
240 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
241
242 if (skb->ip_summed == CHECKSUM_PARTIAL)
243 tx_push1->tx_bd_hsize_lflags =
244 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
245 else
246 tx_push1->tx_bd_hsize_lflags = 0;
247
248 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
249 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
250
fbb0fa8b
MC		 251 end = pdata + length;
252 end = PTR_ALIGN(end, 8) - 1;
4419dbe6
MC		 253 *end = 0;
254
c0c050c5
MC		 255 skb_copy_from_linear_data(skb, pdata, len);
256 pdata += len;
257 for (j = 0; j < last_frag; j++) {
258 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
259 void *fptr;
260
261 fptr = skb_frag_address_safe(frag);
262 if (!fptr)
263 goto normal_tx;
264
265 memcpy(pdata, fptr, skb_frag_size(frag));
266 pdata += skb_frag_size(frag);
267 }
268
4419dbe6
MC		 269 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
270 txbd->tx_bd_haddr = txr->data_mapping;
c0c050c5
MC		 271 prod = NEXT_TX(prod);
272 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
273 memcpy(txbd, tx_push1, sizeof(*txbd));
274 prod = NEXT_TX(prod);
4419dbe6 275 tx_push->doorbell =
c0c050c5
MC		 276 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
277 txr->tx_prod = prod;
278
279 netdev_tx_sent_queue(txq, skb->len);
280
4419dbe6
MC		 281 push_len = (length + sizeof(*tx_push) + 7) / 8;
282 if (push_len > 16) {
283 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
284 __iowrite64_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
285 push_len - 16);
286 } else {
287 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
288 push_len);
289 }
c0c050c5
MC		 290
291 tx_buf->is_push = 1;
c0c050c5
MC		 292 goto tx_done;
293 }
294
295normal_tx:
296 if (length < BNXT_MIN_PKT_SIZE) {
297 pad = BNXT_MIN_PKT_SIZE - length;
298 if (skb_pad(skb, pad)) {
299 /* SKB already freed. */
300 tx_buf->skb = NULL;
301 return NETDEV_TX_OK;
302 }
303 length = BNXT_MIN_PKT_SIZE;
304 }
305
306 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
307
308 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
309 dev_kfree_skb_any(skb);
310 tx_buf->skb = NULL;
311 return NETDEV_TX_OK;
312 }
313
314 dma_unmap_addr_set(tx_buf, mapping, mapping);
315 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
316 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
317
318 txbd->tx_bd_haddr = cpu_to_le64(mapping);
319
320 prod = NEXT_TX(prod);
321 txbd1 = (struct tx_bd_ext *)
322 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
323
324 txbd1->tx_bd_hsize_lflags = 0;
325 if (skb_is_gso(skb)) {
326 u32 hdr_len;
327
328 if (skb->encapsulation)
329 hdr_len = skb_inner_network_offset(skb) +
330 skb_inner_network_header_len(skb) +
331 inner_tcp_hdrlen(skb);
332 else
333 hdr_len = skb_transport_offset(skb) +
334 tcp_hdrlen(skb);
335
336 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
337 TX_BD_FLAGS_T_IPID |
338 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
339 length = skb_shinfo(skb)->gso_size;
340 txbd1->tx_bd_mss = cpu_to_le32(length);
341 length += hdr_len;
342 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
343 txbd1->tx_bd_hsize_lflags =
344 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
345 txbd1->tx_bd_mss = 0;
346 }
347
348 length >>= 9;
349 flags |= bnxt_lhint_arr[length];
350 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
351
352 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
353 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
354 for (i = 0; i < last_frag; i++) {
355 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
356
357 prod = NEXT_TX(prod);
358 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
359
360 len = skb_frag_size(frag);
361 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
362 DMA_TO_DEVICE);
363
364 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
365 goto tx_dma_error;
366
367 tx_buf = &txr->tx_buf_ring[prod];
368 dma_unmap_addr_set(tx_buf, mapping, mapping);
369
370 txbd->tx_bd_haddr = cpu_to_le64(mapping);
371
372 flags = len << TX_BD_LEN_SHIFT;
373 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
374 }
375
376 flags &= ~TX_BD_LEN;
377 txbd->tx_bd_len_flags_type =
378 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
379 TX_BD_FLAGS_PACKET_END);
380
381 netdev_tx_sent_queue(txq, skb->len);
382
383 /* Sync BD data before updating doorbell */
384 wmb();
385
386 prod = NEXT_TX(prod);
387 txr->tx_prod = prod;
388
389 writel(DB_KEY_TX | prod, txr->tx_doorbell);
390 writel(DB_KEY_TX | prod, txr->tx_doorbell);
391
392tx_done:
393
394 mmiowb();
395
396 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
397 netif_tx_stop_queue(txq);
398
399 /* netif_tx_stop_queue() must be done before checking
400 * tx index in bnxt_tx_avail() below, because in
401 * bnxt_tx_int(), we update tx index before checking for
402 * netif_tx_queue_stopped().
403 */
404 smp_mb();
405 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
406 netif_tx_wake_queue(txq);
407 }
408 return NETDEV_TX_OK;
409
410tx_dma_error:
411 last_frag = i;
412
413 /* start back at beginning and unmap skb */
414 prod = txr->tx_prod;
415 tx_buf = &txr->tx_buf_ring[prod];
416 tx_buf->skb = NULL;
417 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
418 skb_headlen(skb), PCI_DMA_TODEVICE);
419 prod = NEXT_TX(prod);
420
421 /* unmap remaining mapped pages */
422 for (i = 0; i < last_frag; i++) {
423 prod = NEXT_TX(prod);
424 tx_buf = &txr->tx_buf_ring[prod];
425 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
426 skb_frag_size(&skb_shinfo(skb)->frags[i]),
427 PCI_DMA_TODEVICE);
428 }
429
430 dev_kfree_skb_any(skb);
431 return NETDEV_TX_OK;
432}
433
434static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
435{
b6ab4b01 436 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
b81a90d3 437 int index = txr - &bp->tx_ring[0];
c0c050c5
MC		 438 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
439 u16 cons = txr->tx_cons;
440 struct pci_dev *pdev = bp->pdev;
441 int i;
442 unsigned int tx_bytes = 0;
443
444 for (i = 0; i < nr_pkts; i++) {
445 struct bnxt_sw_tx_bd *tx_buf;
446 struct sk_buff *skb;
447 int j, last;
448
449 tx_buf = &txr->tx_buf_ring[cons];
450 cons = NEXT_TX(cons);
451 skb = tx_buf->skb;
452 tx_buf->skb = NULL;
453
454 if (tx_buf->is_push) {
455 tx_buf->is_push = 0;
456 goto next_tx_int;
457 }
458
459 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
460 skb_headlen(skb), PCI_DMA_TODEVICE);
461 last = tx_buf->nr_frags;
462
463 for (j = 0; j < last; j++) {
464 cons = NEXT_TX(cons);
465 tx_buf = &txr->tx_buf_ring[cons];
466 dma_unmap_page(
467 &pdev->dev,
468 dma_unmap_addr(tx_buf, mapping),
469 skb_frag_size(&skb_shinfo(skb)->frags[j]),
470 PCI_DMA_TODEVICE);
471 }
472
473next_tx_int:
474 cons = NEXT_TX(cons);
475
476 tx_bytes += skb->len;
477 dev_kfree_skb_any(skb);
478 }
479
480 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
481 txr->tx_cons = cons;
482
483 /* Need to make the tx_cons update visible to bnxt_start_xmit()
484 * before checking for netif_tx_queue_stopped(). Without the
485 * memory barrier, there is a small possibility that bnxt_start_xmit()
486 * will miss it and cause the queue to be stopped forever.
487 */
488 smp_mb();
489
490 if (unlikely(netif_tx_queue_stopped(txq)) &&
491 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
492 __netif_tx_lock(txq, smp_processor_id());
493 if (netif_tx_queue_stopped(txq) &&
494 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
495 txr->dev_state != BNXT_DEV_STATE_CLOSING)
496 netif_tx_wake_queue(txq);
497 __netif_tx_unlock(txq);
498 }
499}
500
501static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
502 gfp_t gfp)
503{
504 u8 *data;
505 struct pci_dev *pdev = bp->pdev;
506
507 data = kmalloc(bp->rx_buf_size, gfp);
508 if (!data)
509 return NULL;
510
511 *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
512 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
513
514 if (dma_mapping_error(&pdev->dev, *mapping)) {
515 kfree(data);
516 data = NULL;
517 }
518 return data;
519}
520
521static inline int bnxt_alloc_rx_data(struct bnxt *bp,
522 struct bnxt_rx_ring_info *rxr,
523 u16 prod, gfp_t gfp)
524{
525 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
526 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
527 u8 *data;
528 dma_addr_t mapping;
529
530 data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
531 if (!data)
532 return -ENOMEM;
533
534 rx_buf->data = data;
535 dma_unmap_addr_set(rx_buf, mapping, mapping);
536
537 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
538
539 return 0;
540}
541
542static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
543 u8 *data)
544{
545 u16 prod = rxr->rx_prod;
546 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
547 struct rx_bd *cons_bd, *prod_bd;
548
549 prod_rx_buf = &rxr->rx_buf_ring[prod];
550 cons_rx_buf = &rxr->rx_buf_ring[cons];
551
552 prod_rx_buf->data = data;
553
554 dma_unmap_addr_set(prod_rx_buf, mapping,
555 dma_unmap_addr(cons_rx_buf, mapping));
556
557 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
558 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
559
560 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
561}
562
563static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
564{
565 u16 next, max = rxr->rx_agg_bmap_size;
566
567 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
568 if (next >= max)
569 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
570 return next;
571}
572
573static inline int bnxt_alloc_rx_page(struct bnxt *bp,
574 struct bnxt_rx_ring_info *rxr,
575 u16 prod, gfp_t gfp)
576{
577 struct rx_bd *rxbd =
578 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
579 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
580 struct pci_dev *pdev = bp->pdev;
581 struct page *page;
582 dma_addr_t mapping;
583 u16 sw_prod = rxr->rx_sw_agg_prod;
89d0a06c 584 unsigned int offset = 0;
c0c050c5 585
89d0a06c
MC		 586 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
587 page = rxr->rx_page;
588 if (!page) {
589 page = alloc_page(gfp);
590 if (!page)
591 return -ENOMEM;
592 rxr->rx_page = page;
593 rxr->rx_page_offset = 0;
594 }
595 offset = rxr->rx_page_offset;
596 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
597 if (rxr->rx_page_offset == PAGE_SIZE)
598 rxr->rx_page = NULL;
599 else
600 get_page(page);
601 } else {
602 page = alloc_page(gfp);
603 if (!page)
604 return -ENOMEM;
605 }
c0c050c5 606
89d0a06c 607 mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE,
c0c050c5
MC		 608 PCI_DMA_FROMDEVICE);
609 if (dma_mapping_error(&pdev->dev, mapping)) {
610 __free_page(page);
611 return -EIO;
612 }
613
614 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
615 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
616
617 __set_bit(sw_prod, rxr->rx_agg_bmap);
618 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
619 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
620
621 rx_agg_buf->page = page;
89d0a06c 622 rx_agg_buf->offset = offset;
c0c050c5
MC		 623 rx_agg_buf->mapping = mapping;
624 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
625 rxbd->rx_bd_opaque = sw_prod;
626 return 0;
627}
628
629static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
630 u32 agg_bufs)
631{
632 struct bnxt *bp = bnapi->bp;
633 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 634 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 635 u16 prod = rxr->rx_agg_prod;
636 u16 sw_prod = rxr->rx_sw_agg_prod;
637 u32 i;
638
639 for (i = 0; i < agg_bufs; i++) {
640 u16 cons;
641 struct rx_agg_cmp *agg;
642 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
643 struct rx_bd *prod_bd;
644 struct page *page;
645
646 agg = (struct rx_agg_cmp *)
647 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
648 cons = agg->rx_agg_cmp_opaque;
649 __clear_bit(cons, rxr->rx_agg_bmap);
650
651 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
652 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
653
654 __set_bit(sw_prod, rxr->rx_agg_bmap);
655 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
656 cons_rx_buf = &rxr->rx_agg_ring[cons];
657
658 /* It is possible for sw_prod to be equal to cons, so
659 * set cons_rx_buf->page to NULL first.
660 */
661 page = cons_rx_buf->page;
662 cons_rx_buf->page = NULL;
663 prod_rx_buf->page = page;
89d0a06c 664 prod_rx_buf->offset = cons_rx_buf->offset;
c0c050c5
MC		 665
666 prod_rx_buf->mapping = cons_rx_buf->mapping;
667
668 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
669
670 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
671 prod_bd->rx_bd_opaque = sw_prod;
672
673 prod = NEXT_RX_AGG(prod);
674 sw_prod = NEXT_RX_AGG(sw_prod);
675 cp_cons = NEXT_CMP(cp_cons);
676 }
677 rxr->rx_agg_prod = prod;
678 rxr->rx_sw_agg_prod = sw_prod;
679}
680
681static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
682 struct bnxt_rx_ring_info *rxr, u16 cons,
683 u16 prod, u8 *data, dma_addr_t dma_addr,
684 unsigned int len)
685{
686 int err;
687 struct sk_buff *skb;
688
689 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
690 if (unlikely(err)) {
691 bnxt_reuse_rx_data(rxr, cons, data);
692 return NULL;
693 }
694
695 skb = build_skb(data, 0);
696 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
697 PCI_DMA_FROMDEVICE);
698 if (!skb) {
699 kfree(data);
700 return NULL;
701 }
702
703 skb_reserve(skb, BNXT_RX_OFFSET);
704 skb_put(skb, len);
705 return skb;
706}
707
708static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
709 struct sk_buff *skb, u16 cp_cons,
710 u32 agg_bufs)
711{
712 struct pci_dev *pdev = bp->pdev;
713 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 714 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 715 u16 prod = rxr->rx_agg_prod;
716 u32 i;
717
718 for (i = 0; i < agg_bufs; i++) {
719 u16 cons, frag_len;
720 struct rx_agg_cmp *agg;
721 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
722 struct page *page;
723 dma_addr_t mapping;
724
725 agg = (struct rx_agg_cmp *)
726 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
727 cons = agg->rx_agg_cmp_opaque;
728 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
729 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
730
731 cons_rx_buf = &rxr->rx_agg_ring[cons];
89d0a06c
MC		 732 skb_fill_page_desc(skb, i, cons_rx_buf->page,
733 cons_rx_buf->offset, frag_len);
c0c050c5
MC		 734 __clear_bit(cons, rxr->rx_agg_bmap);
735
736 /* It is possible for bnxt_alloc_rx_page() to allocate
737 * a sw_prod index that equals the cons index, so we
738 * need to clear the cons entry now.
739 */
740 mapping = dma_unmap_addr(cons_rx_buf, mapping);
741 page = cons_rx_buf->page;
742 cons_rx_buf->page = NULL;
743
744 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
745 struct skb_shared_info *shinfo;
746 unsigned int nr_frags;
747
748 shinfo = skb_shinfo(skb);
749 nr_frags = --shinfo->nr_frags;
750 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
751
752 dev_kfree_skb(skb);
753
754 cons_rx_buf->page = page;
755
756 /* Update prod since possibly some pages have been
757 * allocated already.
758 */
759 rxr->rx_agg_prod = prod;
760 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
761 return NULL;
762 }
763
2839f28b 764 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
c0c050c5
MC		 765 PCI_DMA_FROMDEVICE);
766
767 skb->data_len += frag_len;
768 skb->len += frag_len;
769 skb->truesize += PAGE_SIZE;
770
771 prod = NEXT_RX_AGG(prod);
772 cp_cons = NEXT_CMP(cp_cons);
773 }
774 rxr->rx_agg_prod = prod;
775 return skb;
776}
777
778static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
779 u8 agg_bufs, u32 *raw_cons)
780{
781 u16 last;
782 struct rx_agg_cmp *agg;
783
784 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
785 last = RING_CMP(*raw_cons);
786 agg = (struct rx_agg_cmp *)
787 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
788 return RX_AGG_CMP_VALID(agg, *raw_cons);
789}
790
791static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
792 unsigned int len,
793 dma_addr_t mapping)
794{
795 struct bnxt *bp = bnapi->bp;
796 struct pci_dev *pdev = bp->pdev;
797 struct sk_buff *skb;
798
799 skb = napi_alloc_skb(&bnapi->napi, len);
800 if (!skb)
801 return NULL;
802
803 dma_sync_single_for_cpu(&pdev->dev, mapping,
804 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
805
806 memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
807
808 dma_sync_single_for_device(&pdev->dev, mapping,
809 bp->rx_copy_thresh,
810 PCI_DMA_FROMDEVICE);
811
812 skb_put(skb, len);
813 return skb;
814}
815
816static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
817 struct rx_tpa_start_cmp *tpa_start,
818 struct rx_tpa_start_cmp_ext *tpa_start1)
819{
820 u8 agg_id = TPA_START_AGG_ID(tpa_start);
821 u16 cons, prod;
822 struct bnxt_tpa_info *tpa_info;
823 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
824 struct rx_bd *prod_bd;
825 dma_addr_t mapping;
826
827 cons = tpa_start->rx_tpa_start_cmp_opaque;
828 prod = rxr->rx_prod;
829 cons_rx_buf = &rxr->rx_buf_ring[cons];
830 prod_rx_buf = &rxr->rx_buf_ring[prod];
831 tpa_info = &rxr->rx_tpa[agg_id];
832
833 prod_rx_buf->data = tpa_info->data;
834
835 mapping = tpa_info->mapping;
836 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
837
838 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
839
840 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
841
842 tpa_info->data = cons_rx_buf->data;
843 cons_rx_buf->data = NULL;
844 tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
845
846 tpa_info->len =
847 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
848 RX_TPA_START_CMP_LEN_SHIFT;
849 if (likely(TPA_START_HASH_VALID(tpa_start))) {
850 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
851
852 tpa_info->hash_type = PKT_HASH_TYPE_L4;
853 tpa_info->gso_type = SKB_GSO_TCPV4;
854 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
855 if (hash_type == 3)
856 tpa_info->gso_type = SKB_GSO_TCPV6;
857 tpa_info->rss_hash =
858 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
859 } else {
860 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
861 tpa_info->gso_type = 0;
862 if (netif_msg_rx_err(bp))
863 netdev_warn(bp->dev, "TPA packet without valid hash\n");
864 }
865 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
866 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
867
868 rxr->rx_prod = NEXT_RX(prod);
869 cons = NEXT_RX(cons);
870 cons_rx_buf = &rxr->rx_buf_ring[cons];
871
872 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
873 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
874 cons_rx_buf->data = NULL;
875}
876
877static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
878 u16 cp_cons, u32 agg_bufs)
879{
880 if (agg_bufs)
881 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
882}
883
884#define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
885#define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
886
887static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info,
888 struct rx_tpa_end_cmp *tpa_end,
889 struct rx_tpa_end_cmp_ext *tpa_end1,
890 struct sk_buff *skb)
891{
d1611c3a 892#ifdef CONFIG_INET
c0c050c5
MC		 893 struct tcphdr *th;
894 int payload_off, tcp_opt_len = 0;
895 int len, nw_off;
27e24189 896 u16 segs;
c0c050c5 897
27e24189
MC		 898 segs = TPA_END_TPA_SEGS(tpa_end);
899 if (segs == 1)
900 return skb;
901
902 NAPI_GRO_CB(skb)->count = segs;
c0c050c5
MC		 903 skb_shinfo(skb)->gso_size =
904 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
905 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
906 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
907 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
908 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
909 if (TPA_END_GRO_TS(tpa_end))
910 tcp_opt_len = 12;
911
c0c050c5
MC		 912 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
913 struct iphdr *iph;
914
915 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
916 ETH_HLEN;
917 skb_set_network_header(skb, nw_off);
918 iph = ip_hdr(skb);
919 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
920 len = skb->len - skb_transport_offset(skb);
921 th = tcp_hdr(skb);
922 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
923 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
924 struct ipv6hdr *iph;
925
926 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
927 ETH_HLEN;
928 skb_set_network_header(skb, nw_off);
929 iph = ipv6_hdr(skb);
930 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
931 len = skb->len - skb_transport_offset(skb);
932 th = tcp_hdr(skb);
933 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
934 } else {
935 dev_kfree_skb_any(skb);
936 return NULL;
937 }
938 tcp_gro_complete(skb);
939
940 if (nw_off) { /* tunnel */
941 struct udphdr *uh = NULL;
942
943 if (skb->protocol == htons(ETH_P_IP)) {
944 struct iphdr *iph = (struct iphdr *)skb->data;
945
946 if (iph->protocol == IPPROTO_UDP)
947 uh = (struct udphdr *)(iph + 1);
948 } else {
949 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
950
951 if (iph->nexthdr == IPPROTO_UDP)
952 uh = (struct udphdr *)(iph + 1);
953 }
954 if (uh) {
955 if (uh->check)
956 skb_shinfo(skb)->gso_type |=
957 SKB_GSO_UDP_TUNNEL_CSUM;
958 else
959 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
960 }
961 }
962#endif
963 return skb;
964}
965
966static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
967 struct bnxt_napi *bnapi,
968 u32 *raw_cons,
969 struct rx_tpa_end_cmp *tpa_end,
970 struct rx_tpa_end_cmp_ext *tpa_end1,
971 bool *agg_event)
972{
973 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 974 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 975 u8 agg_id = TPA_END_AGG_ID(tpa_end);
976 u8 *data, agg_bufs;
977 u16 cp_cons = RING_CMP(*raw_cons);
978 unsigned int len;
979 struct bnxt_tpa_info *tpa_info;
980 dma_addr_t mapping;
981 struct sk_buff *skb;
982
983 tpa_info = &rxr->rx_tpa[agg_id];
984 data = tpa_info->data;
985 prefetch(data);
986 len = tpa_info->len;
987 mapping = tpa_info->mapping;
988
989 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
990 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
991
992 if (agg_bufs) {
993 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
994 return ERR_PTR(-EBUSY);
995
996 *agg_event = true;
997 cp_cons = NEXT_CMP(cp_cons);
998 }
999
1000 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1001 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1002 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1003 agg_bufs, (int)MAX_SKB_FRAGS);
1004 return NULL;
1005 }
1006
1007 if (len <= bp->rx_copy_thresh) {
1008 skb = bnxt_copy_skb(bnapi, data, len, mapping);
1009 if (!skb) {
1010 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1011 return NULL;
1012 }
1013 } else {
1014 u8 *new_data;
1015 dma_addr_t new_mapping;
1016
1017 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1018 if (!new_data) {
1019 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1020 return NULL;
1021 }
1022
1023 tpa_info->data = new_data;
1024 tpa_info->mapping = new_mapping;
1025
1026 skb = build_skb(data, 0);
1027 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1028 PCI_DMA_FROMDEVICE);
1029
1030 if (!skb) {
1031 kfree(data);
1032 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1033 return NULL;
1034 }
1035 skb_reserve(skb, BNXT_RX_OFFSET);
1036 skb_put(skb, len);
1037 }
1038
1039 if (agg_bufs) {
1040 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1041 if (!skb) {
1042 /* Page reuse already handled by bnxt_rx_pages(). */
1043 return NULL;
1044 }
1045 }
1046 skb->protocol = eth_type_trans(skb, bp->dev);
1047
1048 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1049 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1050
1051 if (tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) {
1052 netdev_features_t features = skb->dev->features;
1053 u16 vlan_proto = tpa_info->metadata >>
1054 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1055
1056 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1057 vlan_proto == ETH_P_8021Q) ||
1058 ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1059 vlan_proto == ETH_P_8021AD)) {
1060 __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1061 tpa_info->metadata &
1062 RX_CMP_FLAGS2_METADATA_VID_MASK);
1063 }
1064 }
1065
1066 skb_checksum_none_assert(skb);
1067 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1068 skb->ip_summed = CHECKSUM_UNNECESSARY;
1069 skb->csum_level =
1070 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1071 }
1072
1073 if (TPA_END_GRO(tpa_end))
1074 skb = bnxt_gro_skb(tpa_info, tpa_end, tpa_end1, skb);
1075
1076 return skb;
1077}
1078
1079/* returns the following:
1080 * 1 - 1 packet successfully received
1081 * 0 - successful TPA_START, packet not completed yet
1082 * -EBUSY - completion ring does not have all the agg buffers yet
1083 * -ENOMEM - packet aborted due to out of memory
1084 * -EIO - packet aborted due to hw error indicated in BD
1085 */
1086static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1087 bool *agg_event)
1088{
1089 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1090 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1091 struct net_device *dev = bp->dev;
1092 struct rx_cmp *rxcmp;
1093 struct rx_cmp_ext *rxcmp1;
1094 u32 tmp_raw_cons = *raw_cons;
1095 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1096 struct bnxt_sw_rx_bd *rx_buf;
1097 unsigned int len;
1098 u8 *data, agg_bufs, cmp_type;
1099 dma_addr_t dma_addr;
1100 struct sk_buff *skb;
1101 int rc = 0;
1102
1103 rxcmp = (struct rx_cmp *)
1104 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1105
1106 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1107 cp_cons = RING_CMP(tmp_raw_cons);
1108 rxcmp1 = (struct rx_cmp_ext *)
1109 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1110
1111 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1112 return -EBUSY;
1113
1114 cmp_type = RX_CMP_TYPE(rxcmp);
1115
1116 prod = rxr->rx_prod;
1117
1118 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1119 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1120 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1121
1122 goto next_rx_no_prod;
1123
1124 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1125 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1126 (struct rx_tpa_end_cmp *)rxcmp,
1127 (struct rx_tpa_end_cmp_ext *)rxcmp1,
1128 agg_event);
1129
1130 if (unlikely(IS_ERR(skb)))
1131 return -EBUSY;
1132
1133 rc = -ENOMEM;
1134 if (likely(skb)) {
1135 skb_record_rx_queue(skb, bnapi->index);
1136 skb_mark_napi_id(skb, &bnapi->napi);
1137 if (bnxt_busy_polling(bnapi))
1138 netif_receive_skb(skb);
1139 else
1140 napi_gro_receive(&bnapi->napi, skb);
1141 rc = 1;
1142 }
1143 goto next_rx_no_prod;
1144 }
1145
1146 cons = rxcmp->rx_cmp_opaque;
1147 rx_buf = &rxr->rx_buf_ring[cons];
1148 data = rx_buf->data;
1149 prefetch(data);
1150
1151 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1152 RX_CMP_AGG_BUFS_SHIFT;
1153
1154 if (agg_bufs) {
1155 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1156 return -EBUSY;
1157
1158 cp_cons = NEXT_CMP(cp_cons);
1159 *agg_event = true;
1160 }
1161
1162 rx_buf->data = NULL;
1163 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1164 bnxt_reuse_rx_data(rxr, cons, data);
1165 if (agg_bufs)
1166 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1167
1168 rc = -EIO;
1169 goto next_rx;
1170 }
1171
1172 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1173 dma_addr = dma_unmap_addr(rx_buf, mapping);
1174
1175 if (len <= bp->rx_copy_thresh) {
1176 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1177 bnxt_reuse_rx_data(rxr, cons, data);
1178 if (!skb) {
1179 rc = -ENOMEM;
1180 goto next_rx;
1181 }
1182 } else {
1183 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1184 if (!skb) {
1185 rc = -ENOMEM;
1186 goto next_rx;
1187 }
1188 }
1189
1190 if (agg_bufs) {
1191 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1192 if (!skb) {
1193 rc = -ENOMEM;
1194 goto next_rx;
1195 }
1196 }
1197
1198 if (RX_CMP_HASH_VALID(rxcmp)) {
1199 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1200 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1201
1202 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1203 if (hash_type != 1 && hash_type != 3)
1204 type = PKT_HASH_TYPE_L3;
1205 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1206 }
1207
1208 skb->protocol = eth_type_trans(skb, dev);
1209
1210 if (rxcmp1->rx_cmp_flags2 &
1211 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) {
1212 netdev_features_t features = skb->dev->features;
1213 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1214 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1215
1216 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1217 vlan_proto == ETH_P_8021Q) ||
1218 ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1219 vlan_proto == ETH_P_8021AD))
1220 __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1221 meta_data &
1222 RX_CMP_FLAGS2_METADATA_VID_MASK);
1223 }
1224
1225 skb_checksum_none_assert(skb);
1226 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1227 if (dev->features & NETIF_F_RXCSUM) {
1228 skb->ip_summed = CHECKSUM_UNNECESSARY;
1229 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1230 }
1231 } else {
665e350d
SB		 1232 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1233 if (dev->features & NETIF_F_RXCSUM)
1234 cpr->rx_l4_csum_errors++;
1235 }
c0c050c5
MC		 1236 }
1237
1238 skb_record_rx_queue(skb, bnapi->index);
1239 skb_mark_napi_id(skb, &bnapi->napi);
1240 if (bnxt_busy_polling(bnapi))
1241 netif_receive_skb(skb);
1242 else
1243 napi_gro_receive(&bnapi->napi, skb);
1244 rc = 1;
1245
1246next_rx:
1247 rxr->rx_prod = NEXT_RX(prod);
1248
1249next_rx_no_prod:
1250 *raw_cons = tmp_raw_cons;
1251
1252 return rc;
1253}
1254
1255static int bnxt_async_event_process(struct bnxt *bp,
1256 struct hwrm_async_event_cmpl *cmpl)
1257{
1258 u16 event_id = le16_to_cpu(cmpl->event_id);
1259
1260 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1261 switch (event_id) {
1262 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1263 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
19241368
JH		 1264 break;
1265 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1266 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
c0c050c5
MC		 1267 break;
1268 default:
1269 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1270 event_id);
19241368 1271 goto async_event_process_exit;
c0c050c5 1272 }
19241368
JH		 1273 schedule_work(&bp->sp_task);
1274async_event_process_exit:
c0c050c5
MC		 1275 return 0;
1276}
1277
1278static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1279{
1280 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1281 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1282 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1283 (struct hwrm_fwd_req_cmpl *)txcmp;
1284
1285 switch (cmpl_type) {
1286 case CMPL_BASE_TYPE_HWRM_DONE:
1287 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1288 if (seq_id == bp->hwrm_intr_seq_id)
1289 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1290 else
1291 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1292 break;
1293
1294 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1295 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1296
1297 if ((vf_id < bp->pf.first_vf_id) ||
1298 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1299 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1300 vf_id);
1301 return -EINVAL;
1302 }
1303
1304 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1305 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1306 schedule_work(&bp->sp_task);
1307 break;
1308
1309 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1310 bnxt_async_event_process(bp,
1311 (struct hwrm_async_event_cmpl *)txcmp);
1312
1313 default:
1314 break;
1315 }
1316
1317 return 0;
1318}
1319
1320static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1321{
1322 struct bnxt_napi *bnapi = dev_instance;
1323 struct bnxt *bp = bnapi->bp;
1324 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1325 u32 cons = RING_CMP(cpr->cp_raw_cons);
1326
1327 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1328 napi_schedule(&bnapi->napi);
1329 return IRQ_HANDLED;
1330}
1331
1332static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1333{
1334 u32 raw_cons = cpr->cp_raw_cons;
1335 u16 cons = RING_CMP(raw_cons);
1336 struct tx_cmp *txcmp;
1337
1338 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1339
1340 return TX_CMP_VALID(txcmp, raw_cons);
1341}
1342
c0c050c5
MC		 1343static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1344{
1345 struct bnxt_napi *bnapi = dev_instance;
1346 struct bnxt *bp = bnapi->bp;
1347 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1348 u32 cons = RING_CMP(cpr->cp_raw_cons);
1349 u32 int_status;
1350
1351 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1352
1353 if (!bnxt_has_work(bp, cpr)) {
11809490 1354 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
c0c050c5
MC		 1355 /* return if erroneous interrupt */
1356 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1357 return IRQ_NONE;
1358 }
1359
1360 /* disable ring IRQ */
1361 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1362
1363 /* Return here if interrupt is shared and is disabled. */
1364 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1365 return IRQ_HANDLED;
1366
1367 napi_schedule(&bnapi->napi);
1368 return IRQ_HANDLED;
1369}
1370
1371static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1372{
1373 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1374 u32 raw_cons = cpr->cp_raw_cons;
1375 u32 cons;
1376 int tx_pkts = 0;
1377 int rx_pkts = 0;
1378 bool rx_event = false;
1379 bool agg_event = false;
1380 struct tx_cmp *txcmp;
1381
1382 while (1) {
1383 int rc;
1384
1385 cons = RING_CMP(raw_cons);
1386 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1387
1388 if (!TX_CMP_VALID(txcmp, raw_cons))
1389 break;
1390
67a95e20
MC		 1391 /* The valid test of the entry must be done first before
1392 * reading any further.
1393 */
1394 rmb();
c0c050c5
MC		 1395 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1396 tx_pkts++;
1397 /* return full budget so NAPI will complete. */
1398 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1399 rx_pkts = budget;
1400 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1401 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1402 if (likely(rc >= 0))
1403 rx_pkts += rc;
1404 else if (rc == -EBUSY) /* partial completion */
1405 break;
1406 rx_event = true;
1407 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1408 CMPL_BASE_TYPE_HWRM_DONE) ||
1409 (TX_CMP_TYPE(txcmp) ==
1410 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1411 (TX_CMP_TYPE(txcmp) ==
1412 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1413 bnxt_hwrm_handler(bp, txcmp);
1414 }
1415 raw_cons = NEXT_RAW_CMP(raw_cons);
1416
1417 if (rx_pkts == budget)
1418 break;
1419 }
1420
1421 cpr->cp_raw_cons = raw_cons;
1422 /* ACK completion ring before freeing tx ring and producing new
1423 * buffers in rx/agg rings to prevent overflowing the completion
1424 * ring.
1425 */
1426 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1427
1428 if (tx_pkts)
1429 bnxt_tx_int(bp, bnapi, tx_pkts);
1430
1431 if (rx_event) {
b6ab4b01 1432 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1433
1434 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1435 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1436 if (agg_event) {
1437 writel(DB_KEY_RX | rxr->rx_agg_prod,
1438 rxr->rx_agg_doorbell);
1439 writel(DB_KEY_RX | rxr->rx_agg_prod,
1440 rxr->rx_agg_doorbell);
1441 }
1442 }
1443 return rx_pkts;
1444}
1445
1446static int bnxt_poll(struct napi_struct *napi, int budget)
1447{
1448 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1449 struct bnxt *bp = bnapi->bp;
1450 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1451 int work_done = 0;
1452
1453 if (!bnxt_lock_napi(bnapi))
1454 return budget;
1455
1456 while (1) {
1457 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1458
1459 if (work_done >= budget)
1460 break;
1461
1462 if (!bnxt_has_work(bp, cpr)) {
1463 napi_complete(napi);
1464 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1465 break;
1466 }
1467 }
1468 mmiowb();
1469 bnxt_unlock_napi(bnapi);
1470 return work_done;
1471}
1472
1473#ifdef CONFIG_NET_RX_BUSY_POLL
1474static int bnxt_busy_poll(struct napi_struct *napi)
1475{
1476 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1477 struct bnxt *bp = bnapi->bp;
1478 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1479 int rx_work, budget = 4;
1480
1481 if (atomic_read(&bp->intr_sem) != 0)
1482 return LL_FLUSH_FAILED;
1483
1484 if (!bnxt_lock_poll(bnapi))
1485 return LL_FLUSH_BUSY;
1486
1487 rx_work = bnxt_poll_work(bp, bnapi, budget);
1488
1489 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1490
1491 bnxt_unlock_poll(bnapi);
1492 return rx_work;
1493}
1494#endif
1495
1496static void bnxt_free_tx_skbs(struct bnxt *bp)
1497{
1498 int i, max_idx;
1499 struct pci_dev *pdev = bp->pdev;
1500
b6ab4b01 1501 if (!bp->tx_ring)
c0c050c5
MC		 1502 return;
1503
1504 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1505 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 1506 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 1507 int j;
1508
c0c050c5
MC		 1509 for (j = 0; j < max_idx;) {
1510 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1511 struct sk_buff *skb = tx_buf->skb;
1512 int k, last;
1513
1514 if (!skb) {
1515 j++;
1516 continue;
1517 }
1518
1519 tx_buf->skb = NULL;
1520
1521 if (tx_buf->is_push) {
1522 dev_kfree_skb(skb);
1523 j += 2;
1524 continue;
1525 }
1526
1527 dma_unmap_single(&pdev->dev,
1528 dma_unmap_addr(tx_buf, mapping),
1529 skb_headlen(skb),
1530 PCI_DMA_TODEVICE);
1531
1532 last = tx_buf->nr_frags;
1533 j += 2;
d612a579
MC		 1534 for (k = 0; k < last; k++, j++) {
1535 int ring_idx = j & bp->tx_ring_mask;
c0c050c5
MC		 1536 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1537
d612a579 1538 tx_buf = &txr->tx_buf_ring[ring_idx];
c0c050c5
MC		 1539 dma_unmap_page(
1540 &pdev->dev,
1541 dma_unmap_addr(tx_buf, mapping),
1542 skb_frag_size(frag), PCI_DMA_TODEVICE);
1543 }
1544 dev_kfree_skb(skb);
1545 }
1546 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1547 }
1548}
1549
1550static void bnxt_free_rx_skbs(struct bnxt *bp)
1551{
1552 int i, max_idx, max_agg_idx;
1553 struct pci_dev *pdev = bp->pdev;
1554
b6ab4b01 1555 if (!bp->rx_ring)
c0c050c5
MC		 1556 return;
1557
1558 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1559 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1560 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 1561 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 1562 int j;
1563
c0c050c5
MC		 1564 if (rxr->rx_tpa) {
1565 for (j = 0; j < MAX_TPA; j++) {
1566 struct bnxt_tpa_info *tpa_info =
1567 &rxr->rx_tpa[j];
1568 u8 *data = tpa_info->data;
1569
1570 if (!data)
1571 continue;
1572
1573 dma_unmap_single(
1574 &pdev->dev,
1575 dma_unmap_addr(tpa_info, mapping),
1576 bp->rx_buf_use_size,
1577 PCI_DMA_FROMDEVICE);
1578
1579 tpa_info->data = NULL;
1580
1581 kfree(data);
1582 }
1583 }
1584
1585 for (j = 0; j < max_idx; j++) {
1586 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1587 u8 *data = rx_buf->data;
1588
1589 if (!data)
1590 continue;
1591
1592 dma_unmap_single(&pdev->dev,
1593 dma_unmap_addr(rx_buf, mapping),
1594 bp->rx_buf_use_size,
1595 PCI_DMA_FROMDEVICE);
1596
1597 rx_buf->data = NULL;
1598
1599 kfree(data);
1600 }
1601
1602 for (j = 0; j < max_agg_idx; j++) {
1603 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1604 &rxr->rx_agg_ring[j];
1605 struct page *page = rx_agg_buf->page;
1606
1607 if (!page)
1608 continue;
1609
1610 dma_unmap_page(&pdev->dev,
1611 dma_unmap_addr(rx_agg_buf, mapping),
2839f28b 1612 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE);
c0c050c5
MC		 1613
1614 rx_agg_buf->page = NULL;
1615 __clear_bit(j, rxr->rx_agg_bmap);
1616
1617 __free_page(page);
1618 }
89d0a06c
MC		 1619 if (rxr->rx_page) {
1620 __free_page(rxr->rx_page);
1621 rxr->rx_page = NULL;
1622 }
c0c050c5
MC		 1623 }
1624}
1625
1626static void bnxt_free_skbs(struct bnxt *bp)
1627{
1628 bnxt_free_tx_skbs(bp);
1629 bnxt_free_rx_skbs(bp);
1630}
1631
1632static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1633{
1634 struct pci_dev *pdev = bp->pdev;
1635 int i;
1636
1637 for (i = 0; i < ring->nr_pages; i++) {
1638 if (!ring->pg_arr[i])
1639 continue;
1640
1641 dma_free_coherent(&pdev->dev, ring->page_size,
1642 ring->pg_arr[i], ring->dma_arr[i]);
1643
1644 ring->pg_arr[i] = NULL;
1645 }
1646 if (ring->pg_tbl) {
1647 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1648 ring->pg_tbl, ring->pg_tbl_map);
1649 ring->pg_tbl = NULL;
1650 }
1651 if (ring->vmem_size && *ring->vmem) {
1652 vfree(*ring->vmem);
1653 *ring->vmem = NULL;
1654 }
1655}
1656
1657static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1658{
1659 int i;
1660 struct pci_dev *pdev = bp->pdev;
1661
1662 if (ring->nr_pages > 1) {
1663 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1664 ring->nr_pages * 8,
1665 &ring->pg_tbl_map,
1666 GFP_KERNEL);
1667 if (!ring->pg_tbl)
1668 return -ENOMEM;
1669 }
1670
1671 for (i = 0; i < ring->nr_pages; i++) {
1672 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1673 ring->page_size,
1674 &ring->dma_arr[i],
1675 GFP_KERNEL);
1676 if (!ring->pg_arr[i])
1677 return -ENOMEM;
1678
1679 if (ring->nr_pages > 1)
1680 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1681 }
1682
1683 if (ring->vmem_size) {
1684 *ring->vmem = vzalloc(ring->vmem_size);
1685 if (!(*ring->vmem))
1686 return -ENOMEM;
1687 }
1688 return 0;
1689}
1690
1691static void bnxt_free_rx_rings(struct bnxt *bp)
1692{
1693 int i;
1694
b6ab4b01 1695 if (!bp->rx_ring)
c0c050c5
MC		 1696 return;
1697
1698 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 1699 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 1700 struct bnxt_ring_struct *ring;
1701
c0c050c5
MC		 1702 kfree(rxr->rx_tpa);
1703 rxr->rx_tpa = NULL;
1704
1705 kfree(rxr->rx_agg_bmap);
1706 rxr->rx_agg_bmap = NULL;
1707
1708 ring = &rxr->rx_ring_struct;
1709 bnxt_free_ring(bp, ring);
1710
1711 ring = &rxr->rx_agg_ring_struct;
1712 bnxt_free_ring(bp, ring);
1713 }
1714}
1715
1716static int bnxt_alloc_rx_rings(struct bnxt *bp)
1717{
1718 int i, rc, agg_rings = 0, tpa_rings = 0;
1719
b6ab4b01
MC		 1720 if (!bp->rx_ring)
1721 return -ENOMEM;
1722
c0c050c5
MC		 1723 if (bp->flags & BNXT_FLAG_AGG_RINGS)
1724 agg_rings = 1;
1725
1726 if (bp->flags & BNXT_FLAG_TPA)
1727 tpa_rings = 1;
1728
1729 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 1730 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 1731 struct bnxt_ring_struct *ring;
1732
c0c050c5
MC		 1733 ring = &rxr->rx_ring_struct;
1734
1735 rc = bnxt_alloc_ring(bp, ring);
1736 if (rc)
1737 return rc;
1738
1739 if (agg_rings) {
1740 u16 mem_size;
1741
1742 ring = &rxr->rx_agg_ring_struct;
1743 rc = bnxt_alloc_ring(bp, ring);
1744 if (rc)
1745 return rc;
1746
1747 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1748 mem_size = rxr->rx_agg_bmap_size / 8;
1749 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1750 if (!rxr->rx_agg_bmap)
1751 return -ENOMEM;
1752
1753 if (tpa_rings) {
1754 rxr->rx_tpa = kcalloc(MAX_TPA,
1755 sizeof(struct bnxt_tpa_info),
1756 GFP_KERNEL);
1757 if (!rxr->rx_tpa)
1758 return -ENOMEM;
1759 }
1760 }
1761 }
1762 return 0;
1763}
1764
1765static void bnxt_free_tx_rings(struct bnxt *bp)
1766{
1767 int i;
1768 struct pci_dev *pdev = bp->pdev;
1769
b6ab4b01 1770 if (!bp->tx_ring)
c0c050c5
MC		 1771 return;
1772
1773 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 1774 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 1775 struct bnxt_ring_struct *ring;
1776
c0c050c5
MC		 1777 if (txr->tx_push) {
1778 dma_free_coherent(&pdev->dev, bp->tx_push_size,
1779 txr->tx_push, txr->tx_push_mapping);
1780 txr->tx_push = NULL;
1781 }
1782
1783 ring = &txr->tx_ring_struct;
1784
1785 bnxt_free_ring(bp, ring);
1786 }
1787}
1788
1789static int bnxt_alloc_tx_rings(struct bnxt *bp)
1790{
1791 int i, j, rc;
1792 struct pci_dev *pdev = bp->pdev;
1793
1794 bp->tx_push_size = 0;
1795 if (bp->tx_push_thresh) {
1796 int push_size;
1797
1798 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
1799 bp->tx_push_thresh);
1800
4419dbe6 1801 if (push_size > 256) {
c0c050c5
MC		 1802 push_size = 0;
1803 bp->tx_push_thresh = 0;
1804 }
1805
1806 bp->tx_push_size = push_size;
1807 }
1808
1809 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 1810 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 1811 struct bnxt_ring_struct *ring;
1812
c0c050c5
MC		 1813 ring = &txr->tx_ring_struct;
1814
1815 rc = bnxt_alloc_ring(bp, ring);
1816 if (rc)
1817 return rc;
1818
1819 if (bp->tx_push_size) {
c0c050c5
MC		 1820 dma_addr_t mapping;
1821
1822 /* One pre-allocated DMA buffer to backup
1823 * TX push operation
1824 */
1825 txr->tx_push = dma_alloc_coherent(&pdev->dev,
1826 bp->tx_push_size,
1827 &txr->tx_push_mapping,
1828 GFP_KERNEL);
1829
1830 if (!txr->tx_push)
1831 return -ENOMEM;
1832
c0c050c5
MC		 1833 mapping = txr->tx_push_mapping +
1834 sizeof(struct tx_push_bd);
4419dbe6 1835 txr->data_mapping = cpu_to_le64(mapping);
c0c050c5 1836
4419dbe6 1837 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
c0c050c5
MC		 1838 }
1839 ring->queue_id = bp->q_info[j].queue_id;
1840 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
1841 j++;
1842 }
1843 return 0;
1844}
1845
1846static void bnxt_free_cp_rings(struct bnxt *bp)
1847{
1848 int i;
1849
1850 if (!bp->bnapi)
1851 return;
1852
1853 for (i = 0; i < bp->cp_nr_rings; i++) {
1854 struct bnxt_napi *bnapi = bp->bnapi[i];
1855 struct bnxt_cp_ring_info *cpr;
1856 struct bnxt_ring_struct *ring;
1857
1858 if (!bnapi)
1859 continue;
1860
1861 cpr = &bnapi->cp_ring;
1862 ring = &cpr->cp_ring_struct;
1863
1864 bnxt_free_ring(bp, ring);
1865 }
1866}
1867
1868static int bnxt_alloc_cp_rings(struct bnxt *bp)
1869{
1870 int i, rc;
1871
1872 for (i = 0; i < bp->cp_nr_rings; i++) {
1873 struct bnxt_napi *bnapi = bp->bnapi[i];
1874 struct bnxt_cp_ring_info *cpr;
1875 struct bnxt_ring_struct *ring;
1876
1877 if (!bnapi)
1878 continue;
1879
1880 cpr = &bnapi->cp_ring;
1881 ring = &cpr->cp_ring_struct;
1882
1883 rc = bnxt_alloc_ring(bp, ring);
1884 if (rc)
1885 return rc;
1886 }
1887 return 0;
1888}
1889
1890static void bnxt_init_ring_struct(struct bnxt *bp)
1891{
1892 int i;
1893
1894 for (i = 0; i < bp->cp_nr_rings; i++) {
1895 struct bnxt_napi *bnapi = bp->bnapi[i];
1896 struct bnxt_cp_ring_info *cpr;
1897 struct bnxt_rx_ring_info *rxr;
1898 struct bnxt_tx_ring_info *txr;
1899 struct bnxt_ring_struct *ring;
1900
1901 if (!bnapi)
1902 continue;
1903
1904 cpr = &bnapi->cp_ring;
1905 ring = &cpr->cp_ring_struct;
1906 ring->nr_pages = bp->cp_nr_pages;
1907 ring->page_size = HW_CMPD_RING_SIZE;
1908 ring->pg_arr = (void **)cpr->cp_desc_ring;
1909 ring->dma_arr = cpr->cp_desc_mapping;
1910 ring->vmem_size = 0;
1911
b6ab4b01 1912 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 1913 if (!rxr)
1914 goto skip_rx;
1915
c0c050c5
MC		 1916 ring = &rxr->rx_ring_struct;
1917 ring->nr_pages = bp->rx_nr_pages;
1918 ring->page_size = HW_RXBD_RING_SIZE;
1919 ring->pg_arr = (void **)rxr->rx_desc_ring;
1920 ring->dma_arr = rxr->rx_desc_mapping;
1921 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
1922 ring->vmem = (void **)&rxr->rx_buf_ring;
1923
1924 ring = &rxr->rx_agg_ring_struct;
1925 ring->nr_pages = bp->rx_agg_nr_pages;
1926 ring->page_size = HW_RXBD_RING_SIZE;
1927 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
1928 ring->dma_arr = rxr->rx_agg_desc_mapping;
1929 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
1930 ring->vmem = (void **)&rxr->rx_agg_ring;
1931
3b2b7d9d 1932skip_rx:
b6ab4b01 1933 txr = bnapi->tx_ring;
3b2b7d9d
MC		 1934 if (!txr)
1935 continue;
1936
c0c050c5
MC		 1937 ring = &txr->tx_ring_struct;
1938 ring->nr_pages = bp->tx_nr_pages;
1939 ring->page_size = HW_RXBD_RING_SIZE;
1940 ring->pg_arr = (void **)txr->tx_desc_ring;
1941 ring->dma_arr = txr->tx_desc_mapping;
1942 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
1943 ring->vmem = (void **)&txr->tx_buf_ring;
1944 }
1945}
1946
1947static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
1948{
1949 int i;
1950 u32 prod;
1951 struct rx_bd **rx_buf_ring;
1952
1953 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
1954 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
1955 int j;
1956 struct rx_bd *rxbd;
1957
1958 rxbd = rx_buf_ring[i];
1959 if (!rxbd)
1960 continue;
1961
1962 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
1963 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
1964 rxbd->rx_bd_opaque = prod;
1965 }
1966 }
1967}
1968
1969static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
1970{
1971 struct net_device *dev = bp->dev;
c0c050c5
MC		 1972 struct bnxt_rx_ring_info *rxr;
1973 struct bnxt_ring_struct *ring;
1974 u32 prod, type;
1975 int i;
1976
c0c050c5
MC		 1977 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
1978 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
1979
1980 if (NET_IP_ALIGN == 2)
1981 type |= RX_BD_FLAGS_SOP;
1982
b6ab4b01 1983 rxr = &bp->rx_ring[ring_nr];
c0c050c5
MC		 1984 ring = &rxr->rx_ring_struct;
1985 bnxt_init_rxbd_pages(ring, type);
1986
1987 prod = rxr->rx_prod;
1988 for (i = 0; i < bp->rx_ring_size; i++) {
1989 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
1990 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
1991 ring_nr, i, bp->rx_ring_size);
1992 break;
1993 }
1994 prod = NEXT_RX(prod);
1995 }
1996 rxr->rx_prod = prod;
1997 ring->fw_ring_id = INVALID_HW_RING_ID;
1998
edd0c2cc
MC		 1999 ring = &rxr->rx_agg_ring_struct;
2000 ring->fw_ring_id = INVALID_HW_RING_ID;
2001
c0c050c5
MC		 2002 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2003 return 0;
2004
2839f28b 2005 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
c0c050c5
MC		 2006 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2007
2008 bnxt_init_rxbd_pages(ring, type);
2009
2010 prod = rxr->rx_agg_prod;
2011 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2012 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2013 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2014 ring_nr, i, bp->rx_ring_size);
2015 break;
2016 }
2017 prod = NEXT_RX_AGG(prod);
2018 }
2019 rxr->rx_agg_prod = prod;
c0c050c5
MC		 2020
2021 if (bp->flags & BNXT_FLAG_TPA) {
2022 if (rxr->rx_tpa) {
2023 u8 *data;
2024 dma_addr_t mapping;
2025
2026 for (i = 0; i < MAX_TPA; i++) {
2027 data = __bnxt_alloc_rx_data(bp, &mapping,
2028 GFP_KERNEL);
2029 if (!data)
2030 return -ENOMEM;
2031
2032 rxr->rx_tpa[i].data = data;
2033 rxr->rx_tpa[i].mapping = mapping;
2034 }
2035 } else {
2036 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2037 return -ENOMEM;
2038 }
2039 }
2040
2041 return 0;
2042}
2043
2044static int bnxt_init_rx_rings(struct bnxt *bp)
2045{
2046 int i, rc = 0;
2047
2048 for (i = 0; i < bp->rx_nr_rings; i++) {
2049 rc = bnxt_init_one_rx_ring(bp, i);
2050 if (rc)
2051 break;
2052 }
2053
2054 return rc;
2055}
2056
2057static int bnxt_init_tx_rings(struct bnxt *bp)
2058{
2059 u16 i;
2060
2061 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2062 MAX_SKB_FRAGS + 1);
2063
2064 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2065 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2066 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2067
2068 ring->fw_ring_id = INVALID_HW_RING_ID;
2069 }
2070
2071 return 0;
2072}
2073
2074static void bnxt_free_ring_grps(struct bnxt *bp)
2075{
2076 kfree(bp->grp_info);
2077 bp->grp_info = NULL;
2078}
2079
2080static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2081{
2082 int i;
2083
2084 if (irq_re_init) {
2085 bp->grp_info = kcalloc(bp->cp_nr_rings,
2086 sizeof(struct bnxt_ring_grp_info),
2087 GFP_KERNEL);
2088 if (!bp->grp_info)
2089 return -ENOMEM;
2090 }
2091 for (i = 0; i < bp->cp_nr_rings; i++) {
2092 if (irq_re_init)
2093 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2094 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2095 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2096 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2097 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2098 }
2099 return 0;
2100}
2101
2102static void bnxt_free_vnics(struct bnxt *bp)
2103{
2104 kfree(bp->vnic_info);
2105 bp->vnic_info = NULL;
2106 bp->nr_vnics = 0;
2107}
2108
2109static int bnxt_alloc_vnics(struct bnxt *bp)
2110{
2111 int num_vnics = 1;
2112
2113#ifdef CONFIG_RFS_ACCEL
2114 if (bp->flags & BNXT_FLAG_RFS)
2115 num_vnics += bp->rx_nr_rings;
2116#endif
2117
2118 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2119 GFP_KERNEL);
2120 if (!bp->vnic_info)
2121 return -ENOMEM;
2122
2123 bp->nr_vnics = num_vnics;
2124 return 0;
2125}
2126
2127static void bnxt_init_vnics(struct bnxt *bp)
2128{
2129 int i;
2130
2131 for (i = 0; i < bp->nr_vnics; i++) {
2132 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2133
2134 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2135 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2136 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2137
2138 if (bp->vnic_info[i].rss_hash_key) {
2139 if (i == 0)
2140 prandom_bytes(vnic->rss_hash_key,
2141 HW_HASH_KEY_SIZE);
2142 else
2143 memcpy(vnic->rss_hash_key,
2144 bp->vnic_info[0].rss_hash_key,
2145 HW_HASH_KEY_SIZE);
2146 }
2147 }
2148}
2149
2150static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2151{
2152 int pages;
2153
2154 pages = ring_size / desc_per_pg;
2155
2156 if (!pages)
2157 return 1;
2158
2159 pages++;
2160
2161 while (pages & (pages - 1))
2162 pages++;
2163
2164 return pages;
2165}
2166
2167static void bnxt_set_tpa_flags(struct bnxt *bp)
2168{
2169 bp->flags &= ~BNXT_FLAG_TPA;
2170 if (bp->dev->features & NETIF_F_LRO)
2171 bp->flags |= BNXT_FLAG_LRO;
2172 if ((bp->dev->features & NETIF_F_GRO) && (bp->pdev->revision > 0))
2173 bp->flags |= BNXT_FLAG_GRO;
2174}
2175
2176/* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2177 * be set on entry.
2178 */
2179void bnxt_set_ring_params(struct bnxt *bp)
2180{
2181 u32 ring_size, rx_size, rx_space;
2182 u32 agg_factor = 0, agg_ring_size = 0;
2183
2184 /* 8 for CRC and VLAN */
2185 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2186
2187 rx_space = rx_size + NET_SKB_PAD +
2188 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2189
2190 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2191 ring_size = bp->rx_ring_size;
2192 bp->rx_agg_ring_size = 0;
2193 bp->rx_agg_nr_pages = 0;
2194
2195 if (bp->flags & BNXT_FLAG_TPA)
2839f28b 2196 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
c0c050c5
MC		 2197
2198 bp->flags &= ~BNXT_FLAG_JUMBO;
2199 if (rx_space > PAGE_SIZE) {
2200 u32 jumbo_factor;
2201
2202 bp->flags |= BNXT_FLAG_JUMBO;
2203 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2204 if (jumbo_factor > agg_factor)
2205 agg_factor = jumbo_factor;
2206 }
2207 agg_ring_size = ring_size * agg_factor;
2208
2209 if (agg_ring_size) {
2210 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2211 RX_DESC_CNT);
2212 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2213 u32 tmp = agg_ring_size;
2214
2215 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2216 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2217 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2218 tmp, agg_ring_size);
2219 }
2220 bp->rx_agg_ring_size = agg_ring_size;
2221 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2222 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2223 rx_space = rx_size + NET_SKB_PAD +
2224 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2225 }
2226
2227 bp->rx_buf_use_size = rx_size;
2228 bp->rx_buf_size = rx_space;
2229
2230 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2231 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2232
2233 ring_size = bp->tx_ring_size;
2234 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2235 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2236
2237 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2238 bp->cp_ring_size = ring_size;
2239
2240 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2241 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2242 bp->cp_nr_pages = MAX_CP_PAGES;
2243 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2244 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2245 ring_size, bp->cp_ring_size);
2246 }
2247 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2248 bp->cp_ring_mask = bp->cp_bit - 1;
2249}
2250
2251static void bnxt_free_vnic_attributes(struct bnxt *bp)
2252{
2253 int i;
2254 struct bnxt_vnic_info *vnic;
2255 struct pci_dev *pdev = bp->pdev;
2256
2257 if (!bp->vnic_info)
2258 return;
2259
2260 for (i = 0; i < bp->nr_vnics; i++) {
2261 vnic = &bp->vnic_info[i];
2262
2263 kfree(vnic->fw_grp_ids);
2264 vnic->fw_grp_ids = NULL;
2265
2266 kfree(vnic->uc_list);
2267 vnic->uc_list = NULL;
2268
2269 if (vnic->mc_list) {
2270 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2271 vnic->mc_list, vnic->mc_list_mapping);
2272 vnic->mc_list = NULL;
2273 }
2274
2275 if (vnic->rss_table) {
2276 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2277 vnic->rss_table,
2278 vnic->rss_table_dma_addr);
2279 vnic->rss_table = NULL;
2280 }
2281
2282 vnic->rss_hash_key = NULL;
2283 vnic->flags = 0;
2284 }
2285}
2286
2287static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2288{
2289 int i, rc = 0, size;
2290 struct bnxt_vnic_info *vnic;
2291 struct pci_dev *pdev = bp->pdev;
2292 int max_rings;
2293
2294 for (i = 0; i < bp->nr_vnics; i++) {
2295 vnic = &bp->vnic_info[i];
2296
2297 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2298 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2299
2300 if (mem_size > 0) {
2301 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2302 if (!vnic->uc_list) {
2303 rc = -ENOMEM;
2304 goto out;
2305 }
2306 }
2307 }
2308
2309 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2310 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2311 vnic->mc_list =
2312 dma_alloc_coherent(&pdev->dev,
2313 vnic->mc_list_size,
2314 &vnic->mc_list_mapping,
2315 GFP_KERNEL);
2316 if (!vnic->mc_list) {
2317 rc = -ENOMEM;
2318 goto out;
2319 }
2320 }
2321
2322 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2323 max_rings = bp->rx_nr_rings;
2324 else
2325 max_rings = 1;
2326
2327 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2328 if (!vnic->fw_grp_ids) {
2329 rc = -ENOMEM;
2330 goto out;
2331 }
2332
2333 /* Allocate rss table and hash key */
2334 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2335 &vnic->rss_table_dma_addr,
2336 GFP_KERNEL);
2337 if (!vnic->rss_table) {
2338 rc = -ENOMEM;
2339 goto out;
2340 }
2341
2342 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2343
2344 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2345 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2346 }
2347 return 0;
2348
2349out:
2350 return rc;
2351}
2352
2353static void bnxt_free_hwrm_resources(struct bnxt *bp)
2354{
2355 struct pci_dev *pdev = bp->pdev;
2356
2357 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2358 bp->hwrm_cmd_resp_dma_addr);
2359
2360 bp->hwrm_cmd_resp_addr = NULL;
2361 if (bp->hwrm_dbg_resp_addr) {
2362 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2363 bp->hwrm_dbg_resp_addr,
2364 bp->hwrm_dbg_resp_dma_addr);
2365
2366 bp->hwrm_dbg_resp_addr = NULL;
2367 }
2368}
2369
2370static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2371{
2372 struct pci_dev *pdev = bp->pdev;
2373
2374 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2375 &bp->hwrm_cmd_resp_dma_addr,
2376 GFP_KERNEL);
2377 if (!bp->hwrm_cmd_resp_addr)
2378 return -ENOMEM;
2379 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2380 HWRM_DBG_REG_BUF_SIZE,
2381 &bp->hwrm_dbg_resp_dma_addr,
2382 GFP_KERNEL);
2383 if (!bp->hwrm_dbg_resp_addr)
2384 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2385
2386 return 0;
2387}
2388
2389static void bnxt_free_stats(struct bnxt *bp)
2390{
2391 u32 size, i;
2392 struct pci_dev *pdev = bp->pdev;
2393
3bdf56c4
MC		 2394 if (bp->hw_rx_port_stats) {
2395 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2396 bp->hw_rx_port_stats,
2397 bp->hw_rx_port_stats_map);
2398 bp->hw_rx_port_stats = NULL;
2399 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2400 }
2401
c0c050c5
MC		 2402 if (!bp->bnapi)
2403 return;
2404
2405 size = sizeof(struct ctx_hw_stats);
2406
2407 for (i = 0; i < bp->cp_nr_rings; i++) {
2408 struct bnxt_napi *bnapi = bp->bnapi[i];
2409 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2410
2411 if (cpr->hw_stats) {
2412 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2413 cpr->hw_stats_map);
2414 cpr->hw_stats = NULL;
2415 }
2416 }
2417}
2418
2419static int bnxt_alloc_stats(struct bnxt *bp)
2420{
2421 u32 size, i;
2422 struct pci_dev *pdev = bp->pdev;
2423
2424 size = sizeof(struct ctx_hw_stats);
2425
2426 for (i = 0; i < bp->cp_nr_rings; i++) {
2427 struct bnxt_napi *bnapi = bp->bnapi[i];
2428 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2429
2430 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2431 &cpr->hw_stats_map,
2432 GFP_KERNEL);
2433 if (!cpr->hw_stats)
2434 return -ENOMEM;
2435
2436 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2437 }
3bdf56c4
MC		 2438
2439 if (BNXT_PF(bp)) {
2440 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2441 sizeof(struct tx_port_stats) + 1024;
2442
2443 bp->hw_rx_port_stats =
2444 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2445 &bp->hw_rx_port_stats_map,
2446 GFP_KERNEL);
2447 if (!bp->hw_rx_port_stats)
2448 return -ENOMEM;
2449
2450 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2451 512;
2452 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2453 sizeof(struct rx_port_stats) + 512;
2454 bp->flags |= BNXT_FLAG_PORT_STATS;
2455 }
c0c050c5
MC		 2456 return 0;
2457}
2458
2459static void bnxt_clear_ring_indices(struct bnxt *bp)
2460{
2461 int i;
2462
2463 if (!bp->bnapi)
2464 return;
2465
2466 for (i = 0; i < bp->cp_nr_rings; i++) {
2467 struct bnxt_napi *bnapi = bp->bnapi[i];
2468 struct bnxt_cp_ring_info *cpr;
2469 struct bnxt_rx_ring_info *rxr;
2470 struct bnxt_tx_ring_info *txr;
2471
2472 if (!bnapi)
2473 continue;
2474
2475 cpr = &bnapi->cp_ring;
2476 cpr->cp_raw_cons = 0;
2477
b6ab4b01 2478 txr = bnapi->tx_ring;
3b2b7d9d
MC		 2479 if (txr) {
2480 txr->tx_prod = 0;
2481 txr->tx_cons = 0;
2482 }
c0c050c5 2483
b6ab4b01 2484 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 2485 if (rxr) {
2486 rxr->rx_prod = 0;
2487 rxr->rx_agg_prod = 0;
2488 rxr->rx_sw_agg_prod = 0;
2489 }
c0c050c5
MC		 2490 }
2491}
2492
2493static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2494{
2495#ifdef CONFIG_RFS_ACCEL
2496 int i;
2497
2498 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2499 * safe to delete the hash table.
2500 */
2501 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2502 struct hlist_head *head;
2503 struct hlist_node *tmp;
2504 struct bnxt_ntuple_filter *fltr;
2505
2506 head = &bp->ntp_fltr_hash_tbl[i];
2507 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2508 hlist_del(&fltr->hash);
2509 kfree(fltr);
2510 }
2511 }
2512 if (irq_reinit) {
2513 kfree(bp->ntp_fltr_bmap);
2514 bp->ntp_fltr_bmap = NULL;
2515 }
2516 bp->ntp_fltr_count = 0;
2517#endif
2518}
2519
2520static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2521{
2522#ifdef CONFIG_RFS_ACCEL
2523 int i, rc = 0;
2524
2525 if (!(bp->flags & BNXT_FLAG_RFS))
2526 return 0;
2527
2528 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2529 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2530
2531 bp->ntp_fltr_count = 0;
2532 bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2533 GFP_KERNEL);
2534
2535 if (!bp->ntp_fltr_bmap)
2536 rc = -ENOMEM;
2537
2538 return rc;
2539#else
2540 return 0;
2541#endif
2542}
2543
2544static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2545{
2546 bnxt_free_vnic_attributes(bp);
2547 bnxt_free_tx_rings(bp);
2548 bnxt_free_rx_rings(bp);
2549 bnxt_free_cp_rings(bp);
2550 bnxt_free_ntp_fltrs(bp, irq_re_init);
2551 if (irq_re_init) {
2552 bnxt_free_stats(bp);
2553 bnxt_free_ring_grps(bp);
2554 bnxt_free_vnics(bp);
b6ab4b01
MC		 2555 kfree(bp->tx_ring);
2556 bp->tx_ring = NULL;
2557 kfree(bp->rx_ring);
2558 bp->rx_ring = NULL;
c0c050c5
MC		 2559 kfree(bp->bnapi);
2560 bp->bnapi = NULL;
2561 } else {
2562 bnxt_clear_ring_indices(bp);
2563 }
2564}
2565
2566static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2567{
01657bcd 2568 int i, j, rc, size, arr_size;
c0c050c5
MC		 2569 void *bnapi;
2570
2571 if (irq_re_init) {
2572 /* Allocate bnapi mem pointer array and mem block for
2573 * all queues
2574 */
2575 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2576 bp->cp_nr_rings);
2577 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2578 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2579 if (!bnapi)
2580 return -ENOMEM;
2581
2582 bp->bnapi = bnapi;
2583 bnapi += arr_size;
2584 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2585 bp->bnapi[i] = bnapi;
2586 bp->bnapi[i]->index = i;
2587 bp->bnapi[i]->bp = bp;
2588 }
2589
b6ab4b01
MC		 2590 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2591 sizeof(struct bnxt_rx_ring_info),
2592 GFP_KERNEL);
2593 if (!bp->rx_ring)
2594 return -ENOMEM;
2595
2596 for (i = 0; i < bp->rx_nr_rings; i++) {
2597 bp->rx_ring[i].bnapi = bp->bnapi[i];
2598 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2599 }
2600
2601 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2602 sizeof(struct bnxt_tx_ring_info),
2603 GFP_KERNEL);
2604 if (!bp->tx_ring)
2605 return -ENOMEM;
2606
01657bcd
MC		 2607 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2608 j = 0;
2609 else
2610 j = bp->rx_nr_rings;
2611
2612 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2613 bp->tx_ring[i].bnapi = bp->bnapi[j];
2614 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
b6ab4b01
MC		 2615 }
2616
c0c050c5
MC		 2617 rc = bnxt_alloc_stats(bp);
2618 if (rc)
2619 goto alloc_mem_err;
2620
2621 rc = bnxt_alloc_ntp_fltrs(bp);
2622 if (rc)
2623 goto alloc_mem_err;
2624
2625 rc = bnxt_alloc_vnics(bp);
2626 if (rc)
2627 goto alloc_mem_err;
2628 }
2629
2630 bnxt_init_ring_struct(bp);
2631
2632 rc = bnxt_alloc_rx_rings(bp);
2633 if (rc)
2634 goto alloc_mem_err;
2635
2636 rc = bnxt_alloc_tx_rings(bp);
2637 if (rc)
2638 goto alloc_mem_err;
2639
2640 rc = bnxt_alloc_cp_rings(bp);
2641 if (rc)
2642 goto alloc_mem_err;
2643
2644 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2645 BNXT_VNIC_UCAST_FLAG;
2646 rc = bnxt_alloc_vnic_attributes(bp);
2647 if (rc)
2648 goto alloc_mem_err;
2649 return 0;
2650
2651alloc_mem_err:
2652 bnxt_free_mem(bp, true);
2653 return rc;
2654}
2655
2656void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2657 u16 cmpl_ring, u16 target_id)
2658{
a8643e16 2659 struct input *req = request;
c0c050c5 2660
a8643e16
MC		 2661 req->req_type = cpu_to_le16(req_type);
2662 req->cmpl_ring = cpu_to_le16(cmpl_ring);
2663 req->target_id = cpu_to_le16(target_id);
c0c050c5
MC		 2664 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2665}
2666
fbfbc485
MC		 2667static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
2668 int timeout, bool silent)
c0c050c5
MC		 2669{
2670 int i, intr_process, rc;
a8643e16 2671 struct input *req = msg;
c0c050c5
MC		 2672 u32 *data = msg;
2673 __le32 *resp_len, *valid;
2674 u16 cp_ring_id, len = 0;
2675 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2676
a8643e16 2677 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
c0c050c5 2678 memset(resp, 0, PAGE_SIZE);
a8643e16 2679 cp_ring_id = le16_to_cpu(req->cmpl_ring);
c0c050c5
MC		 2680 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2681
2682 /* Write request msg to hwrm channel */
2683 __iowrite32_copy(bp->bar0, data, msg_len / 4);
2684
e6ef2699 2685 for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
d79979a1
MC		 2686 writel(0, bp->bar0 + i);
2687
c0c050c5
MC		 2688 /* currently supports only one outstanding message */
2689 if (intr_process)
a8643e16 2690 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
c0c050c5
MC		 2691
2692 /* Ring channel doorbell */
2693 writel(1, bp->bar0 + 0x100);
2694
ff4fe81d
MC		 2695 if (!timeout)
2696 timeout = DFLT_HWRM_CMD_TIMEOUT;
2697
c0c050c5
MC		 2698 i = 0;
2699 if (intr_process) {
2700 /* Wait until hwrm response cmpl interrupt is processed */
2701 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
2702 i++ < timeout) {
2703 usleep_range(600, 800);
2704 }
2705
2706 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2707 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
a8643e16 2708 le16_to_cpu(req->req_type));
c0c050c5
MC		 2709 return -1;
2710 }
2711 } else {
2712 /* Check if response len is updated */
2713 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
2714 for (i = 0; i < timeout; i++) {
2715 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2716 HWRM_RESP_LEN_SFT;
2717 if (len)
2718 break;
2719 usleep_range(600, 800);
2720 }
2721
2722 if (i >= timeout) {
2723 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
a8643e16
MC		 2724 timeout, le16_to_cpu(req->req_type),
2725 le16_to_cpu(req->seq_id), *resp_len);
c0c050c5
MC		 2726 return -1;
2727 }
2728
2729 /* Last word of resp contains valid bit */
2730 valid = bp->hwrm_cmd_resp_addr + len - 4;
2731 for (i = 0; i < timeout; i++) {
2732 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2733 break;
2734 usleep_range(600, 800);
2735 }
2736
2737 if (i >= timeout) {
2738 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
a8643e16
MC		 2739 timeout, le16_to_cpu(req->req_type),
2740 le16_to_cpu(req->seq_id), len, *valid);
c0c050c5
MC		 2741 return -1;
2742 }
2743 }
2744
2745 rc = le16_to_cpu(resp->error_code);
fbfbc485 2746 if (rc && !silent)
c0c050c5
MC		 2747 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2748 le16_to_cpu(resp->req_type),
2749 le16_to_cpu(resp->seq_id), rc);
fbfbc485
MC		 2750 return rc;
2751}
2752
2753int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2754{
2755 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
c0c050c5
MC		 2756}
2757
2758int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2759{
2760 int rc;
2761
2762 mutex_lock(&bp->hwrm_cmd_lock);
2763 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2764 mutex_unlock(&bp->hwrm_cmd_lock);
2765 return rc;
2766}
2767
90e20921
MC		 2768int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
2769 int timeout)
2770{
2771 int rc;
2772
2773 mutex_lock(&bp->hwrm_cmd_lock);
2774 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
2775 mutex_unlock(&bp->hwrm_cmd_lock);
2776 return rc;
2777}
2778
c0c050c5
MC		 2779static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
2780{
2781 struct hwrm_func_drv_rgtr_input req = {0};
2782 int i;
2783
2784 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
2785
2786 req.enables =
2787 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
2788 FUNC_DRV_RGTR_REQ_ENABLES_VER |
2789 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
2790
2791 /* TODO: current async event fwd bits are not defined and the firmware
2792 * only checks if it is non-zero to enable async event forwarding
2793 */
2794 req.async_event_fwd[0] |= cpu_to_le32(1);
2795 req.os_type = cpu_to_le16(1);
2796 req.ver_maj = DRV_VER_MAJ;
2797 req.ver_min = DRV_VER_MIN;
2798 req.ver_upd = DRV_VER_UPD;
2799
2800 if (BNXT_PF(bp)) {
de68f5de 2801 DECLARE_BITMAP(vf_req_snif_bmap, 256);
c0c050c5
MC		 2802 u32 *data = (u32 *)vf_req_snif_bmap;
2803
de68f5de 2804 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
c0c050c5
MC		 2805 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
2806 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
2807
de68f5de
MC		 2808 for (i = 0; i < 8; i++)
2809 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
2810
c0c050c5
MC		 2811 req.enables |=
2812 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
2813 }
2814
2815 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2816}
2817
be58a0da
JH		 2818static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
2819{
2820 struct hwrm_func_drv_unrgtr_input req = {0};
2821
2822 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
2823 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2824}
2825
c0c050c5
MC		 2826static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
2827{
2828 u32 rc = 0;
2829 struct hwrm_tunnel_dst_port_free_input req = {0};
2830
2831 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
2832 req.tunnel_type = tunnel_type;
2833
2834 switch (tunnel_type) {
2835 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
2836 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
2837 break;
2838 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
2839 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
2840 break;
2841 default:
2842 break;
2843 }
2844
2845 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2846 if (rc)
2847 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2848 rc);
2849 return rc;
2850}
2851
2852static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
2853 u8 tunnel_type)
2854{
2855 u32 rc = 0;
2856 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2857 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2858
2859 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
2860
2861 req.tunnel_type = tunnel_type;
2862 req.tunnel_dst_port_val = port;
2863
2864 mutex_lock(&bp->hwrm_cmd_lock);
2865 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2866 if (rc) {
2867 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2868 rc);
2869 goto err_out;
2870 }
2871
2872 if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
2873 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2874
2875 else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
2876 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
2877err_out:
2878 mutex_unlock(&bp->hwrm_cmd_lock);
2879 return rc;
2880}
2881
2882static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
2883{
2884 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
2885 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2886
2887 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
c193554e 2888 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
c0c050c5
MC		 2889
2890 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
2891 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
2892 req.mask = cpu_to_le32(vnic->rx_mask);
2893 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2894}
2895
2896#ifdef CONFIG_RFS_ACCEL
2897static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2898 struct bnxt_ntuple_filter *fltr)
2899{
2900 struct hwrm_cfa_ntuple_filter_free_input req = {0};
2901
2902 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
2903 req.ntuple_filter_id = fltr->filter_id;
2904 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2905}
2906
2907#define BNXT_NTP_FLTR_FLAGS \
2908 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
2909 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
2910 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
2911 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
2912 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
2913 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
2914 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
2915 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
2916 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
2917 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
2918 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
2919 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
2920 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
c193554e 2921 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
c0c050c5
MC		 2922
2923static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2924 struct bnxt_ntuple_filter *fltr)
2925{
2926 int rc = 0;
2927 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
2928 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
2929 bp->hwrm_cmd_resp_addr;
2930 struct flow_keys *keys = &fltr->fkeys;
2931 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
2932
2933 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
2934 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
2935
2936 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
2937
2938 req.ethertype = htons(ETH_P_IP);
2939 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
c193554e 2940 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
c0c050c5
MC		 2941 req.ip_protocol = keys->basic.ip_proto;
2942
2943 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
2944 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2945 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
2946 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2947
2948 req.src_port = keys->ports.src;
2949 req.src_port_mask = cpu_to_be16(0xffff);
2950 req.dst_port = keys->ports.dst;
2951 req.dst_port_mask = cpu_to_be16(0xffff);
2952
c193554e 2953 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
c0c050c5
MC		 2954 mutex_lock(&bp->hwrm_cmd_lock);
2955 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2956 if (!rc)
2957 fltr->filter_id = resp->ntuple_filter_id;
2958 mutex_unlock(&bp->hwrm_cmd_lock);
2959 return rc;
2960}
2961#endif
2962
2963static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
2964 u8 *mac_addr)
2965{
2966 u32 rc = 0;
2967 struct hwrm_cfa_l2_filter_alloc_input req = {0};
2968 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2969
2970 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
2971 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
2972 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
c193554e 2973 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
c0c050c5
MC		 2974 req.enables =
2975 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
c193554e 2976 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
c0c050c5
MC		 2977 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
2978 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
2979 req.l2_addr_mask[0] = 0xff;
2980 req.l2_addr_mask[1] = 0xff;
2981 req.l2_addr_mask[2] = 0xff;
2982 req.l2_addr_mask[3] = 0xff;
2983 req.l2_addr_mask[4] = 0xff;
2984 req.l2_addr_mask[5] = 0xff;
2985
2986 mutex_lock(&bp->hwrm_cmd_lock);
2987 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2988 if (!rc)
2989 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
2990 resp->l2_filter_id;
2991 mutex_unlock(&bp->hwrm_cmd_lock);
2992 return rc;
2993}
2994
2995static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
2996{
2997 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
2998 int rc = 0;
2999
3000 /* Any associated ntuple filters will also be cleared by firmware. */
3001 mutex_lock(&bp->hwrm_cmd_lock);
3002 for (i = 0; i < num_of_vnics; i++) {
3003 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3004
3005 for (j = 0; j < vnic->uc_filter_count; j++) {
3006 struct hwrm_cfa_l2_filter_free_input req = {0};
3007
3008 bnxt_hwrm_cmd_hdr_init(bp, &req,
3009 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3010
3011 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3012
3013 rc = _hwrm_send_message(bp, &req, sizeof(req),
3014 HWRM_CMD_TIMEOUT);
3015 }
3016 vnic->uc_filter_count = 0;
3017 }
3018 mutex_unlock(&bp->hwrm_cmd_lock);
3019
3020 return rc;
3021}
3022
3023static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3024{
3025 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3026 struct hwrm_vnic_tpa_cfg_input req = {0};
3027
3028 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3029
3030 if (tpa_flags) {
3031 u16 mss = bp->dev->mtu - 40;
3032 u32 nsegs, n, segs = 0, flags;
3033
3034 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3035 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3036 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3037 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3038 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3039 if (tpa_flags & BNXT_FLAG_GRO)
3040 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3041
3042 req.flags = cpu_to_le32(flags);
3043
3044 req.enables =
3045 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
c193554e
MC		 3046 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3047 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
c0c050c5
MC		 3048
3049 /* Number of segs are log2 units, and first packet is not
3050 * included as part of this units.
3051 */
2839f28b
MC		 3052 if (mss <= BNXT_RX_PAGE_SIZE) {
3053 n = BNXT_RX_PAGE_SIZE / mss;
c0c050c5
MC		 3054 nsegs = (MAX_SKB_FRAGS - 1) * n;
3055 } else {
2839f28b
MC		 3056 n = mss / BNXT_RX_PAGE_SIZE;
3057 if (mss & (BNXT_RX_PAGE_SIZE - 1))
c0c050c5
MC		 3058 n++;
3059 nsegs = (MAX_SKB_FRAGS - n) / n;
3060 }
3061
3062 segs = ilog2(nsegs);
3063 req.max_agg_segs = cpu_to_le16(segs);
3064 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
c193554e
MC		 3065
3066 req.min_agg_len = cpu_to_le32(512);
c0c050c5
MC		 3067 }
3068 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3069
3070 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3071}
3072
3073static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3074{
3075 u32 i, j, max_rings;
3076 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3077 struct hwrm_vnic_rss_cfg_input req = {0};
3078
3079 if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
3080 return 0;
3081
3082 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3083 if (set_rss) {
3084 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
3085 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
3086 BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
3087 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
3088
3089 req.hash_type = cpu_to_le32(vnic->hash_type);
3090
3091 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3092 max_rings = bp->rx_nr_rings;
3093 else
3094 max_rings = 1;
3095
3096 /* Fill the RSS indirection table with ring group ids */
3097 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3098 if (j == max_rings)
3099 j = 0;
3100 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3101 }
3102
3103 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3104 req.hash_key_tbl_addr =
3105 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3106 }
3107 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3108 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3109}
3110
3111static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3112{
3113 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3114 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3115
3116 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3117 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3118 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3119 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3120 req.enables =
3121 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3122 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3123 /* thresholds not implemented in firmware yet */
3124 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3125 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3126 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3127 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3128}
3129
3130static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3131{
3132 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3133
3134 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3135 req.rss_cos_lb_ctx_id =
3136 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3137
3138 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3139 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3140}
3141
3142static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3143{
3144 int i;
3145
3146 for (i = 0; i < bp->nr_vnics; i++) {
3147 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3148
3149 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3150 bnxt_hwrm_vnic_ctx_free_one(bp, i);
3151 }
3152 bp->rsscos_nr_ctxs = 0;
3153}
3154
3155static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3156{
3157 int rc;
3158 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3159 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3160 bp->hwrm_cmd_resp_addr;
3161
3162 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3163 -1);
3164
3165 mutex_lock(&bp->hwrm_cmd_lock);
3166 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3167 if (!rc)
3168 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3169 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3170 mutex_unlock(&bp->hwrm_cmd_lock);
3171
3172 return rc;
3173}
3174
3175static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3176{
b81a90d3 3177 unsigned int ring = 0, grp_idx;
c0c050c5
MC		 3178 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3179 struct hwrm_vnic_cfg_input req = {0};
3180
3181 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3182 /* Only RSS support for now TBD: COS & LB */
3183 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
3184 VNIC_CFG_REQ_ENABLES_RSS_RULE);
3185 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3186 req.cos_rule = cpu_to_le16(0xffff);
3187 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
b81a90d3 3188 ring = 0;
c0c050c5 3189 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
b81a90d3 3190 ring = vnic_id - 1;
c0c050c5 3191
b81a90d3 3192 grp_idx = bp->rx_ring[ring].bnapi->index;
c0c050c5
MC		 3193 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3194 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3195
3196 req.lb_rule = cpu_to_le16(0xffff);
3197 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3198 VLAN_HLEN);
3199
3200 if (bp->flags & BNXT_FLAG_STRIP_VLAN)
3201 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3202
3203 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3204}
3205
3206static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3207{
3208 u32 rc = 0;
3209
3210 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3211 struct hwrm_vnic_free_input req = {0};
3212
3213 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3214 req.vnic_id =
3215 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3216
3217 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3218 if (rc)
3219 return rc;
3220 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3221 }
3222 return rc;
3223}
3224
3225static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3226{
3227 u16 i;
3228
3229 for (i = 0; i < bp->nr_vnics; i++)
3230 bnxt_hwrm_vnic_free_one(bp, i);
3231}
3232
b81a90d3
MC		 3233static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3234 unsigned int start_rx_ring_idx,
3235 unsigned int nr_rings)
c0c050c5 3236{
b81a90d3
MC		 3237 int rc = 0;
3238 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
c0c050c5
MC		 3239 struct hwrm_vnic_alloc_input req = {0};
3240 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3241
3242 /* map ring groups to this vnic */
b81a90d3
MC		 3243 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3244 grp_idx = bp->rx_ring[i].bnapi->index;
3245 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
c0c050c5 3246 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
b81a90d3 3247 j, nr_rings);
c0c050c5
MC		 3248 break;
3249 }
3250 bp->vnic_info[vnic_id].fw_grp_ids[j] =
b81a90d3 3251 bp->grp_info[grp_idx].fw_grp_id;
c0c050c5
MC		 3252 }
3253
3254 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3255 if (vnic_id == 0)
3256 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3257
3258 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3259
3260 mutex_lock(&bp->hwrm_cmd_lock);
3261 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3262 if (!rc)
3263 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3264 mutex_unlock(&bp->hwrm_cmd_lock);
3265 return rc;
3266}
3267
3268static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3269{
3270 u16 i;
3271 u32 rc = 0;
3272
3273 mutex_lock(&bp->hwrm_cmd_lock);
3274 for (i = 0; i < bp->rx_nr_rings; i++) {
3275 struct hwrm_ring_grp_alloc_input req = {0};
3276 struct hwrm_ring_grp_alloc_output *resp =
3277 bp->hwrm_cmd_resp_addr;
b81a90d3 3278 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
c0c050c5
MC		 3279
3280 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3281
b81a90d3
MC		 3282 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3283 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3284 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3285 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
c0c050c5
MC		 3286
3287 rc = _hwrm_send_message(bp, &req, sizeof(req),
3288 HWRM_CMD_TIMEOUT);
3289 if (rc)
3290 break;
3291
b81a90d3
MC		 3292 bp->grp_info[grp_idx].fw_grp_id =
3293 le32_to_cpu(resp->ring_group_id);
c0c050c5
MC		 3294 }
3295 mutex_unlock(&bp->hwrm_cmd_lock);
3296 return rc;
3297}
3298
3299static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3300{
3301 u16 i;
3302 u32 rc = 0;
3303 struct hwrm_ring_grp_free_input req = {0};
3304
3305 if (!bp->grp_info)
3306 return 0;
3307
3308 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3309
3310 mutex_lock(&bp->hwrm_cmd_lock);
3311 for (i = 0; i < bp->cp_nr_rings; i++) {
3312 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3313 continue;
3314 req.ring_group_id =
3315 cpu_to_le32(bp->grp_info[i].fw_grp_id);
3316
3317 rc = _hwrm_send_message(bp, &req, sizeof(req),
3318 HWRM_CMD_TIMEOUT);
3319 if (rc)
3320 break;
3321 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3322 }
3323 mutex_unlock(&bp->hwrm_cmd_lock);
3324 return rc;
3325}
3326
3327static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3328 struct bnxt_ring_struct *ring,
3329 u32 ring_type, u32 map_index,
3330 u32 stats_ctx_id)
3331{
3332 int rc = 0, err = 0;
3333 struct hwrm_ring_alloc_input req = {0};
3334 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3335 u16 ring_id;
3336
3337 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3338
3339 req.enables = 0;
3340 if (ring->nr_pages > 1) {
3341 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3342 /* Page size is in log2 units */
3343 req.page_size = BNXT_PAGE_SHIFT;
3344 req.page_tbl_depth = 1;
3345 } else {
3346 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
3347 }
3348 req.fbo = 0;
3349 /* Association of ring index with doorbell index and MSIX number */
3350 req.logical_id = cpu_to_le16(map_index);
3351
3352 switch (ring_type) {
3353 case HWRM_RING_ALLOC_TX:
3354 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3355 /* Association of transmit ring with completion ring */
3356 req.cmpl_ring_id =
3357 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3358 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3359 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3360 req.queue_id = cpu_to_le16(ring->queue_id);
3361 break;
3362 case HWRM_RING_ALLOC_RX:
3363 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3364 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3365 break;
3366 case HWRM_RING_ALLOC_AGG:
3367 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3368 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3369 break;
3370 case HWRM_RING_ALLOC_CMPL:
3371 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3372 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3373 if (bp->flags & BNXT_FLAG_USING_MSIX)
3374 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3375 break;
3376 default:
3377 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3378 ring_type);
3379 return -1;
3380 }
3381
3382 mutex_lock(&bp->hwrm_cmd_lock);
3383 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3384 err = le16_to_cpu(resp->error_code);
3385 ring_id = le16_to_cpu(resp->ring_id);
3386 mutex_unlock(&bp->hwrm_cmd_lock);
3387
3388 if (rc || err) {
3389 switch (ring_type) {
3390 case RING_FREE_REQ_RING_TYPE_CMPL:
3391 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3392 rc, err);
3393 return -1;
3394
3395 case RING_FREE_REQ_RING_TYPE_RX:
3396 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3397 rc, err);
3398 return -1;
3399
3400 case RING_FREE_REQ_RING_TYPE_TX:
3401 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3402 rc, err);
3403 return -1;
3404
3405 default:
3406 netdev_err(bp->dev, "Invalid ring\n");
3407 return -1;
3408 }
3409 }
3410 ring->fw_ring_id = ring_id;
3411 return rc;
3412}
3413
3414static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3415{
3416 int i, rc = 0;
3417
edd0c2cc
MC		 3418 for (i = 0; i < bp->cp_nr_rings; i++) {
3419 struct bnxt_napi *bnapi = bp->bnapi[i];
3420 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3421 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
c0c050c5 3422
33e52d88 3423 cpr->cp_doorbell = bp->bar1 + i * 0x80;
edd0c2cc
MC		 3424 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3425 INVALID_STATS_CTX_ID);
3426 if (rc)
3427 goto err_out;
edd0c2cc
MC		 3428 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3429 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3430 }
3431
edd0c2cc 3432 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 3433 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 3434 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 3435 u32 map_idx = txr->bnapi->index;
3436 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
c0c050c5 3437
b81a90d3
MC		 3438 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3439 map_idx, fw_stats_ctx);
edd0c2cc
MC		 3440 if (rc)
3441 goto err_out;
b81a90d3 3442 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 3443 }
3444
edd0c2cc 3445 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3446 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 3447 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3 3448 u32 map_idx = rxr->bnapi->index;
c0c050c5 3449
b81a90d3
MC		 3450 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3451 map_idx, INVALID_STATS_CTX_ID);
edd0c2cc
MC		 3452 if (rc)
3453 goto err_out;
b81a90d3 3454 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
edd0c2cc 3455 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
b81a90d3 3456 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3457 }
3458
3459 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3460 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3461 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 3462 struct bnxt_ring_struct *ring =
3463 &rxr->rx_agg_ring_struct;
b81a90d3
MC		 3464 u32 grp_idx = rxr->bnapi->index;
3465 u32 map_idx = grp_idx + bp->rx_nr_rings;
c0c050c5
MC		 3466
3467 rc = hwrm_ring_alloc_send_msg(bp, ring,
3468 HWRM_RING_ALLOC_AGG,
b81a90d3 3469 map_idx,
c0c050c5
MC		 3470 INVALID_STATS_CTX_ID);
3471 if (rc)
3472 goto err_out;
3473
b81a90d3 3474 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 3475 writel(DB_KEY_RX | rxr->rx_agg_prod,
3476 rxr->rx_agg_doorbell);
b81a90d3 3477 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3478 }
3479 }
3480err_out:
3481 return rc;
3482}
3483
3484static int hwrm_ring_free_send_msg(struct bnxt *bp,
3485 struct bnxt_ring_struct *ring,
3486 u32 ring_type, int cmpl_ring_id)
3487{
3488 int rc;
3489 struct hwrm_ring_free_input req = {0};
3490 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3491 u16 error_code;
3492
74608fc9 3493 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
c0c050c5
MC		 3494 req.ring_type = ring_type;
3495 req.ring_id = cpu_to_le16(ring->fw_ring_id);
3496
3497 mutex_lock(&bp->hwrm_cmd_lock);
3498 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3499 error_code = le16_to_cpu(resp->error_code);
3500 mutex_unlock(&bp->hwrm_cmd_lock);
3501
3502 if (rc || error_code) {
3503 switch (ring_type) {
3504 case RING_FREE_REQ_RING_TYPE_CMPL:
3505 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3506 rc);
3507 return rc;
3508 case RING_FREE_REQ_RING_TYPE_RX:
3509 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3510 rc);
3511 return rc;
3512 case RING_FREE_REQ_RING_TYPE_TX:
3513 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3514 rc);
3515 return rc;
3516 default:
3517 netdev_err(bp->dev, "Invalid ring\n");
3518 return -1;
3519 }
3520 }
3521 return 0;
3522}
3523
edd0c2cc 3524static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
c0c050c5 3525{
edd0c2cc 3526 int i;
c0c050c5
MC		 3527
3528 if (!bp->bnapi)
edd0c2cc 3529 return;
c0c050c5 3530
edd0c2cc 3531 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 3532 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 3533 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 3534 u32 grp_idx = txr->bnapi->index;
3535 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 3536
3537 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3538 hwrm_ring_free_send_msg(bp, ring,
3539 RING_FREE_REQ_RING_TYPE_TX,
3540 close_path ? cmpl_ring_id :
3541 INVALID_HW_RING_ID);
3542 ring->fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 3543 }
3544 }
3545
edd0c2cc 3546 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3547 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 3548 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3
MC		 3549 u32 grp_idx = rxr->bnapi->index;
3550 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 3551
3552 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3553 hwrm_ring_free_send_msg(bp, ring,
3554 RING_FREE_REQ_RING_TYPE_RX,
3555 close_path ? cmpl_ring_id :
3556 INVALID_HW_RING_ID);
3557 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 3558 bp->grp_info[grp_idx].rx_fw_ring_id =
3559 INVALID_HW_RING_ID;
c0c050c5
MC		 3560 }
3561 }
3562
edd0c2cc 3563 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3564 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 3565 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
b81a90d3
MC		 3566 u32 grp_idx = rxr->bnapi->index;
3567 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 3568
3569 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3570 hwrm_ring_free_send_msg(bp, ring,
3571 RING_FREE_REQ_RING_TYPE_RX,
3572 close_path ? cmpl_ring_id :
3573 INVALID_HW_RING_ID);
3574 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 3575 bp->grp_info[grp_idx].agg_fw_ring_id =
3576 INVALID_HW_RING_ID;
c0c050c5
MC		 3577 }
3578 }
3579
edd0c2cc
MC		 3580 for (i = 0; i < bp->cp_nr_rings; i++) {
3581 struct bnxt_napi *bnapi = bp->bnapi[i];
3582 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3583 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3584
3585 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3586 hwrm_ring_free_send_msg(bp, ring,
3587 RING_FREE_REQ_RING_TYPE_CMPL,
3588 INVALID_HW_RING_ID);
3589 ring->fw_ring_id = INVALID_HW_RING_ID;
3590 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 3591 }
3592 }
c0c050c5
MC		 3593}
3594
bb053f52
MC		 3595static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
3596 u32 buf_tmrs, u16 flags,
3597 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
3598{
3599 req->flags = cpu_to_le16(flags);
3600 req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
3601 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
3602 req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
3603 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
3604 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3605 req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
3606 req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
3607 req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
3608}
3609
c0c050c5
MC		 3610int bnxt_hwrm_set_coal(struct bnxt *bp)
3611{
3612 int i, rc = 0;
dfc9c94a
MC		 3613 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
3614 req_tx = {0}, *req;
c0c050c5
MC		 3615 u16 max_buf, max_buf_irq;
3616 u16 buf_tmr, buf_tmr_irq;
3617 u32 flags;
3618
dfc9c94a
MC		 3619 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
3620 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3621 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
3622 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
c0c050c5 3623
dfb5b894
MC		 3624 /* Each rx completion (2 records) should be DMAed immediately.
3625 * DMA 1/4 of the completion buffers at a time.
3626 */
3627 max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
c0c050c5
MC		 3628 /* max_buf must not be zero */
3629 max_buf = clamp_t(u16, max_buf, 1, 63);
dfb5b894
MC		 3630 max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
3631 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
3632 /* buf timer set to 1/4 of interrupt timer */
3633 buf_tmr = max_t(u16, buf_tmr / 4, 1);
3634 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
3635 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
c0c050c5
MC		 3636
3637 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3638
3639 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3640 * if coal_ticks is less than 25 us.
3641 */
dfb5b894 3642 if (bp->rx_coal_ticks < 25)
c0c050c5
MC		 3643 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3644
bb053f52 3645 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
dfc9c94a
MC		 3646 buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
3647
3648 /* max_buf must not be zero */
3649 max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
3650 max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
3651 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
3652 /* buf timer set to 1/4 of interrupt timer */
3653 buf_tmr = max_t(u16, buf_tmr / 4, 1);
3654 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
3655 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
3656
3657 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3658 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
3659 buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
c0c050c5
MC		 3660
3661 mutex_lock(&bp->hwrm_cmd_lock);
3662 for (i = 0; i < bp->cp_nr_rings; i++) {
dfc9c94a 3663 struct bnxt_napi *bnapi = bp->bnapi[i];
c0c050c5 3664
dfc9c94a
MC		 3665 req = &req_rx;
3666 if (!bnapi->rx_ring)
3667 req = &req_tx;
3668 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3669
3670 rc = _hwrm_send_message(bp, req, sizeof(*req),
c0c050c5
MC		 3671 HWRM_CMD_TIMEOUT);
3672 if (rc)
3673 break;
3674 }
3675 mutex_unlock(&bp->hwrm_cmd_lock);
3676 return rc;
3677}
3678
3679static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3680{
3681 int rc = 0, i;
3682 struct hwrm_stat_ctx_free_input req = {0};
3683
3684 if (!bp->bnapi)
3685 return 0;
3686
3687 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3688
3689 mutex_lock(&bp->hwrm_cmd_lock);
3690 for (i = 0; i < bp->cp_nr_rings; i++) {
3691 struct bnxt_napi *bnapi = bp->bnapi[i];
3692 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3693
3694 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3695 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3696
3697 rc = _hwrm_send_message(bp, &req, sizeof(req),
3698 HWRM_CMD_TIMEOUT);
3699 if (rc)
3700 break;
3701
3702 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3703 }
3704 }
3705 mutex_unlock(&bp->hwrm_cmd_lock);
3706 return rc;
3707}
3708
3709static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3710{
3711 int rc = 0, i;
3712 struct hwrm_stat_ctx_alloc_input req = {0};
3713 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3714
3715 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3716
3717 req.update_period_ms = cpu_to_le32(1000);
3718
3719 mutex_lock(&bp->hwrm_cmd_lock);
3720 for (i = 0; i < bp->cp_nr_rings; i++) {
3721 struct bnxt_napi *bnapi = bp->bnapi[i];
3722 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3723
3724 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3725
3726 rc = _hwrm_send_message(bp, &req, sizeof(req),
3727 HWRM_CMD_TIMEOUT);
3728 if (rc)
3729 break;
3730
3731 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3732
3733 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3734 }
3735 mutex_unlock(&bp->hwrm_cmd_lock);
3736 return 0;
3737}
3738
4a21b49b 3739int bnxt_hwrm_func_qcaps(struct bnxt *bp)
c0c050c5
MC		 3740{
3741 int rc = 0;
3742 struct hwrm_func_qcaps_input req = {0};
3743 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3744
3745 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
3746 req.fid = cpu_to_le16(0xffff);
3747
3748 mutex_lock(&bp->hwrm_cmd_lock);
3749 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3750 if (rc)
3751 goto hwrm_func_qcaps_exit;
3752
3753 if (BNXT_PF(bp)) {
3754 struct bnxt_pf_info *pf = &bp->pf;
3755
3756 pf->fw_fid = le16_to_cpu(resp->fid);
3757 pf->port_id = le16_to_cpu(resp->port_id);
3758 memcpy(pf->mac_addr, resp->perm_mac_address, ETH_ALEN);
bdd4347b 3759 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
c0c050c5
MC		 3760 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3761 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3762 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
c0c050c5 3763 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 3764 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3765 if (!pf->max_hw_ring_grps)
3766 pf->max_hw_ring_grps = pf->max_tx_rings;
c0c050c5
MC		 3767 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3768 pf->max_vnics = le16_to_cpu(resp->max_vnics);
3769 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3770 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
3771 pf->max_vfs = le16_to_cpu(resp->max_vfs);
3772 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
3773 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
3774 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
3775 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
3776 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
3777 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
3778 } else {
379a80a1 3779#ifdef CONFIG_BNXT_SRIOV
c0c050c5
MC		 3780 struct bnxt_vf_info *vf = &bp->vf;
3781
3782 vf->fw_fid = le16_to_cpu(resp->fid);
3783 memcpy(vf->mac_addr, resp->perm_mac_address, ETH_ALEN);
bdd4347b
JH		 3784 if (is_valid_ether_addr(vf->mac_addr))
3785 /* overwrite netdev dev_adr with admin VF MAC */
3786 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
3787 else
3788 random_ether_addr(bp->dev->dev_addr);
c0c050c5
MC		 3789
3790 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3791 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3792 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3793 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 3794 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3795 if (!vf->max_hw_ring_grps)
3796 vf->max_hw_ring_grps = vf->max_tx_rings;
c0c050c5
MC		 3797 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3798 vf->max_vnics = le16_to_cpu(resp->max_vnics);
3799 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
379a80a1 3800#endif
c0c050c5
MC		 3801 }
3802
3803 bp->tx_push_thresh = 0;
3804 if (resp->flags &
3805 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
3806 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
3807
3808hwrm_func_qcaps_exit:
3809 mutex_unlock(&bp->hwrm_cmd_lock);
3810 return rc;
3811}
3812
3813static int bnxt_hwrm_func_reset(struct bnxt *bp)
3814{
3815 struct hwrm_func_reset_input req = {0};
3816
3817 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
3818 req.enables = 0;
3819
3820 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
3821}
3822
3823static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
3824{
3825 int rc = 0;
3826 struct hwrm_queue_qportcfg_input req = {0};
3827 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
3828 u8 i, *qptr;
3829
3830 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
3831
3832 mutex_lock(&bp->hwrm_cmd_lock);
3833 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3834 if (rc)
3835 goto qportcfg_exit;
3836
3837 if (!resp->max_configurable_queues) {
3838 rc = -EINVAL;
3839 goto qportcfg_exit;
3840 }
3841 bp->max_tc = resp->max_configurable_queues;
3842 if (bp->max_tc > BNXT_MAX_QUEUE)
3843 bp->max_tc = BNXT_MAX_QUEUE;
3844
3845 qptr = &resp->queue_id0;
3846 for (i = 0; i < bp->max_tc; i++) {
3847 bp->q_info[i].queue_id = *qptr++;
3848 bp->q_info[i].queue_profile = *qptr++;
3849 }
3850
3851qportcfg_exit:
3852 mutex_unlock(&bp->hwrm_cmd_lock);
3853 return rc;
3854}
3855
3856static int bnxt_hwrm_ver_get(struct bnxt *bp)
3857{
3858 int rc;
3859 struct hwrm_ver_get_input req = {0};
3860 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
3861
e6ef2699 3862 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
c0c050c5
MC		 3863 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
3864 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
3865 req.hwrm_intf_min = HWRM_VERSION_MINOR;
3866 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
3867 mutex_lock(&bp->hwrm_cmd_lock);
3868 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3869 if (rc)
3870 goto hwrm_ver_get_exit;
3871
3872 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
3873
c193554e
MC		 3874 if (resp->hwrm_intf_maj < 1) {
3875 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
c0c050c5 3876 resp->hwrm_intf_maj, resp->hwrm_intf_min,
c193554e
MC		 3877 resp->hwrm_intf_upd);
3878 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
c0c050c5 3879 }
3ebf6f0a 3880 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
c0c050c5
MC		 3881 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
3882 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
3883
ff4fe81d
MC		 3884 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
3885 if (!bp->hwrm_cmd_timeout)
3886 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
3887
e6ef2699
MC		 3888 if (resp->hwrm_intf_maj >= 1)
3889 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
3890
c0c050c5
MC		 3891hwrm_ver_get_exit:
3892 mutex_unlock(&bp->hwrm_cmd_lock);
3893 return rc;
3894}
3895
3bdf56c4
MC		 3896static int bnxt_hwrm_port_qstats(struct bnxt *bp)
3897{
3898 int rc;
3899 struct bnxt_pf_info *pf = &bp->pf;
3900 struct hwrm_port_qstats_input req = {0};
3901
3902 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3903 return 0;
3904
3905 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
3906 req.port_id = cpu_to_le16(pf->port_id);
3907 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
3908 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
3909 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3910 return rc;
3911}
3912
c0c050c5
MC		 3913static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
3914{
3915 if (bp->vxlan_port_cnt) {
3916 bnxt_hwrm_tunnel_dst_port_free(
3917 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
3918 }
3919 bp->vxlan_port_cnt = 0;
3920 if (bp->nge_port_cnt) {
3921 bnxt_hwrm_tunnel_dst_port_free(
3922 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
3923 }
3924 bp->nge_port_cnt = 0;
3925}
3926
3927static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
3928{
3929 int rc, i;
3930 u32 tpa_flags = 0;
3931
3932 if (set_tpa)
3933 tpa_flags = bp->flags & BNXT_FLAG_TPA;
3934 for (i = 0; i < bp->nr_vnics; i++) {
3935 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
3936 if (rc) {
3937 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3938 rc, i);
3939 return rc;
3940 }
3941 }
3942 return 0;
3943}
3944
3945static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
3946{
3947 int i;
3948
3949 for (i = 0; i < bp->nr_vnics; i++)
3950 bnxt_hwrm_vnic_set_rss(bp, i, false);
3951}
3952
3953static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
3954 bool irq_re_init)
3955{
3956 if (bp->vnic_info) {
3957 bnxt_hwrm_clear_vnic_filter(bp);
3958 /* clear all RSS setting before free vnic ctx */
3959 bnxt_hwrm_clear_vnic_rss(bp);
3960 bnxt_hwrm_vnic_ctx_free(bp);
3961 /* before free the vnic, undo the vnic tpa settings */
3962 if (bp->flags & BNXT_FLAG_TPA)
3963 bnxt_set_tpa(bp, false);
3964 bnxt_hwrm_vnic_free(bp);
3965 }
3966 bnxt_hwrm_ring_free(bp, close_path);
3967 bnxt_hwrm_ring_grp_free(bp);
3968 if (irq_re_init) {
3969 bnxt_hwrm_stat_ctx_free(bp);
3970 bnxt_hwrm_free_tunnel_ports(bp);
3971 }
3972}
3973
3974static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
3975{
3976 int rc;
3977
3978 /* allocate context for vnic */
3979 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
3980 if (rc) {
3981 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3982 vnic_id, rc);
3983 goto vnic_setup_err;
3984 }
3985 bp->rsscos_nr_ctxs++;
3986
3987 /* configure default vnic, ring grp */
3988 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
3989 if (rc) {
3990 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
3991 vnic_id, rc);
3992 goto vnic_setup_err;
3993 }
3994
3995 /* Enable RSS hashing on vnic */
3996 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
3997 if (rc) {
3998 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
3999 vnic_id, rc);
4000 goto vnic_setup_err;
4001 }
4002
4003 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4004 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4005 if (rc) {
4006 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4007 vnic_id, rc);
4008 }
4009 }
4010
4011vnic_setup_err:
4012 return rc;
4013}
4014
4015static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4016{
4017#ifdef CONFIG_RFS_ACCEL
4018 int i, rc = 0;
4019
4020 for (i = 0; i < bp->rx_nr_rings; i++) {
4021 u16 vnic_id = i + 1;
4022 u16 ring_id = i;
4023
4024 if (vnic_id >= bp->nr_vnics)
4025 break;
4026
4027 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
b81a90d3 4028 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
c0c050c5
MC		 4029 if (rc) {
4030 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4031 vnic_id, rc);
4032 break;
4033 }
4034 rc = bnxt_setup_vnic(bp, vnic_id);
4035 if (rc)
4036 break;
4037 }
4038 return rc;
4039#else
4040 return 0;
4041#endif
4042}
4043
b664f008
MC		 4044static int bnxt_cfg_rx_mode(struct bnxt *);
4045
c0c050c5
MC		 4046static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4047{
4048 int rc = 0;
4049
4050 if (irq_re_init) {
4051 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4052 if (rc) {
4053 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4054 rc);
4055 goto err_out;
4056 }
4057 }
4058
4059 rc = bnxt_hwrm_ring_alloc(bp);
4060 if (rc) {
4061 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4062 goto err_out;
4063 }
4064
4065 rc = bnxt_hwrm_ring_grp_alloc(bp);
4066 if (rc) {
4067 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4068 goto err_out;
4069 }
4070
4071 /* default vnic 0 */
4072 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
4073 if (rc) {
4074 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4075 goto err_out;
4076 }
4077
4078 rc = bnxt_setup_vnic(bp, 0);
4079 if (rc)
4080 goto err_out;
4081
4082 if (bp->flags & BNXT_FLAG_RFS) {
4083 rc = bnxt_alloc_rfs_vnics(bp);
4084 if (rc)
4085 goto err_out;
4086 }
4087
4088 if (bp->flags & BNXT_FLAG_TPA) {
4089 rc = bnxt_set_tpa(bp, true);
4090 if (rc)
4091 goto err_out;
4092 }
4093
4094 if (BNXT_VF(bp))
4095 bnxt_update_vf_mac(bp);
4096
4097 /* Filter for default vnic 0 */
4098 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4099 if (rc) {
4100 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4101 goto err_out;
4102 }
4103 bp->vnic_info[0].uc_filter_count = 1;
4104
c193554e 4105 bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
c0c050c5
MC		 4106
4107 if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4108 bp->vnic_info[0].rx_mask |=
4109 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4110
b664f008
MC		 4111 rc = bnxt_cfg_rx_mode(bp);
4112 if (rc)
c0c050c5 4113 goto err_out;
c0c050c5
MC		 4114
4115 rc = bnxt_hwrm_set_coal(bp);
4116 if (rc)
4117 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
4118 rc);
4119
4120 return 0;
4121
4122err_out:
4123 bnxt_hwrm_resource_free(bp, 0, true);
4124
4125 return rc;
4126}
4127
4128static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4129{
4130 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4131 return 0;
4132}
4133
4134static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4135{
4136 bnxt_init_rx_rings(bp);
4137 bnxt_init_tx_rings(bp);
4138 bnxt_init_ring_grps(bp, irq_re_init);
4139 bnxt_init_vnics(bp);
4140
4141 return bnxt_init_chip(bp, irq_re_init);
4142}
4143
4144static void bnxt_disable_int(struct bnxt *bp)
4145{
4146 int i;
4147
4148 if (!bp->bnapi)
4149 return;
4150
4151 for (i = 0; i < bp->cp_nr_rings; i++) {
4152 struct bnxt_napi *bnapi = bp->bnapi[i];
4153 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4154
4155 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4156 }
4157}
4158
4159static void bnxt_enable_int(struct bnxt *bp)
4160{
4161 int i;
4162
4163 atomic_set(&bp->intr_sem, 0);
4164 for (i = 0; i < bp->cp_nr_rings; i++) {
4165 struct bnxt_napi *bnapi = bp->bnapi[i];
4166 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4167
4168 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4169 }
4170}
4171
4172static int bnxt_set_real_num_queues(struct bnxt *bp)
4173{
4174 int rc;
4175 struct net_device *dev = bp->dev;
4176
4177 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4178 if (rc)
4179 return rc;
4180
4181 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4182 if (rc)
4183 return rc;
4184
4185#ifdef CONFIG_RFS_ACCEL
45019a18 4186 if (bp->flags & BNXT_FLAG_RFS)
c0c050c5 4187 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
c0c050c5
MC		 4188#endif
4189
4190 return rc;
4191}
4192
6e6c5a57
MC		 4193static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4194 bool shared)
4195{
4196 int _rx = *rx, _tx = *tx;
4197
4198 if (shared) {
4199 *rx = min_t(int, _rx, max);
4200 *tx = min_t(int, _tx, max);
4201 } else {
4202 if (max < 2)
4203 return -ENOMEM;
4204
4205 while (_rx + _tx > max) {
4206 if (_rx > _tx && _rx > 1)
4207 _rx--;
4208 else if (_tx > 1)
4209 _tx--;
4210 }
4211 *rx = _rx;
4212 *tx = _tx;
4213 }
4214 return 0;
4215}
4216
c0c050c5
MC		 4217static int bnxt_setup_msix(struct bnxt *bp)
4218{
4219 struct msix_entry *msix_ent;
4220 struct net_device *dev = bp->dev;
01657bcd 4221 int i, total_vecs, rc = 0, min = 1;
c0c050c5
MC		 4222 const int len = sizeof(bp->irq_tbl[0].name);
4223
4224 bp->flags &= ~BNXT_FLAG_USING_MSIX;
4225 total_vecs = bp->cp_nr_rings;
4226
4227 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4228 if (!msix_ent)
4229 return -ENOMEM;
4230
4231 for (i = 0; i < total_vecs; i++) {
4232 msix_ent[i].entry = i;
4233 msix_ent[i].vector = 0;
4234 }
4235
01657bcd
MC		 4236 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
4237 min = 2;
4238
4239 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
c0c050c5
MC		 4240 if (total_vecs < 0) {
4241 rc = -ENODEV;
4242 goto msix_setup_exit;
4243 }
4244
4245 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4246 if (bp->irq_tbl) {
4247 int tcs;
4248
4249 /* Trim rings based upon num of vectors allocated */
6e6c5a57 4250 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
01657bcd 4251 total_vecs, min == 1);
6e6c5a57
MC		 4252 if (rc)
4253 goto msix_setup_exit;
4254
c0c050c5
MC		 4255 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4256 tcs = netdev_get_num_tc(dev);
4257 if (tcs > 1) {
4258 bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4259 if (bp->tx_nr_rings_per_tc == 0) {
4260 netdev_reset_tc(dev);
4261 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4262 } else {
4263 int i, off, count;
4264
4265 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4266 for (i = 0; i < tcs; i++) {
4267 count = bp->tx_nr_rings_per_tc;
4268 off = i * count;
4269 netdev_set_tc_queue(dev, i, count, off);
4270 }
4271 }
4272 }
01657bcd 4273 bp->cp_nr_rings = total_vecs;
c0c050c5
MC		 4274
4275 for (i = 0; i < bp->cp_nr_rings; i++) {
01657bcd
MC		 4276 char *attr;
4277
c0c050c5 4278 bp->irq_tbl[i].vector = msix_ent[i].vector;
01657bcd
MC		 4279 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4280 attr = "TxRx";
4281 else if (i < bp->rx_nr_rings)
4282 attr = "rx";
4283 else
4284 attr = "tx";
4285
c0c050c5 4286 snprintf(bp->irq_tbl[i].name, len,
01657bcd 4287 "%s-%s-%d", dev->name, attr, i);
c0c050c5
MC		 4288 bp->irq_tbl[i].handler = bnxt_msix;
4289 }
4290 rc = bnxt_set_real_num_queues(bp);
4291 if (rc)
4292 goto msix_setup_exit;
4293 } else {
4294 rc = -ENOMEM;
4295 goto msix_setup_exit;
4296 }
4297 bp->flags |= BNXT_FLAG_USING_MSIX;
4298 kfree(msix_ent);
4299 return 0;
4300
4301msix_setup_exit:
4302 netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4303 pci_disable_msix(bp->pdev);
4304 kfree(msix_ent);
4305 return rc;
4306}
4307
4308static int bnxt_setup_inta(struct bnxt *bp)
4309{
4310 int rc;
4311 const int len = sizeof(bp->irq_tbl[0].name);
4312
4313 if (netdev_get_num_tc(bp->dev))
4314 netdev_reset_tc(bp->dev);
4315
4316 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4317 if (!bp->irq_tbl) {
4318 rc = -ENOMEM;
4319 return rc;
4320 }
4321 bp->rx_nr_rings = 1;
4322 bp->tx_nr_rings = 1;
4323 bp->cp_nr_rings = 1;
4324 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
01657bcd 4325 bp->flags |= BNXT_FLAG_SHARED_RINGS;
c0c050c5
MC		 4326 bp->irq_tbl[0].vector = bp->pdev->irq;
4327 snprintf(bp->irq_tbl[0].name, len,
4328 "%s-%s-%d", bp->dev->name, "TxRx", 0);
4329 bp->irq_tbl[0].handler = bnxt_inta;
4330 rc = bnxt_set_real_num_queues(bp);
4331 return rc;
4332}
4333
4334static int bnxt_setup_int_mode(struct bnxt *bp)
4335{
4336 int rc = 0;
4337
4338 if (bp->flags & BNXT_FLAG_MSIX_CAP)
4339 rc = bnxt_setup_msix(bp);
4340
1fa72e29 4341 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
c0c050c5
MC		 4342 /* fallback to INTA */
4343 rc = bnxt_setup_inta(bp);
4344 }
4345 return rc;
4346}
4347
4348static void bnxt_free_irq(struct bnxt *bp)
4349{
4350 struct bnxt_irq *irq;
4351 int i;
4352
4353#ifdef CONFIG_RFS_ACCEL
4354 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4355 bp->dev->rx_cpu_rmap = NULL;
4356#endif
4357 if (!bp->irq_tbl)
4358 return;
4359
4360 for (i = 0; i < bp->cp_nr_rings; i++) {
4361 irq = &bp->irq_tbl[i];
4362 if (irq->requested)
4363 free_irq(irq->vector, bp->bnapi[i]);
4364 irq->requested = 0;
4365 }
4366 if (bp->flags & BNXT_FLAG_USING_MSIX)
4367 pci_disable_msix(bp->pdev);
4368 kfree(bp->irq_tbl);
4369 bp->irq_tbl = NULL;
4370}
4371
4372static int bnxt_request_irq(struct bnxt *bp)
4373{
b81a90d3 4374 int i, j, rc = 0;
c0c050c5
MC		 4375 unsigned long flags = 0;
4376#ifdef CONFIG_RFS_ACCEL
4377 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4378#endif
4379
4380 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4381 flags = IRQF_SHARED;
4382
b81a90d3 4383 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
c0c050c5
MC		 4384 struct bnxt_irq *irq = &bp->irq_tbl[i];
4385#ifdef CONFIG_RFS_ACCEL
b81a90d3 4386 if (rmap && bp->bnapi[i]->rx_ring) {
c0c050c5
MC		 4387 rc = irq_cpu_rmap_add(rmap, irq->vector);
4388 if (rc)
4389 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
b81a90d3
MC		 4390 j);
4391 j++;
c0c050c5
MC		 4392 }
4393#endif
4394 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4395 bp->bnapi[i]);
4396 if (rc)
4397 break;
4398
4399 irq->requested = 1;
4400 }
4401 return rc;
4402}
4403
4404static void bnxt_del_napi(struct bnxt *bp)
4405{
4406 int i;
4407
4408 if (!bp->bnapi)
4409 return;
4410
4411 for (i = 0; i < bp->cp_nr_rings; i++) {
4412 struct bnxt_napi *bnapi = bp->bnapi[i];
4413
4414 napi_hash_del(&bnapi->napi);
4415 netif_napi_del(&bnapi->napi);
4416 }
4417}
4418
4419static void bnxt_init_napi(struct bnxt *bp)
4420{
4421 int i;
4422 struct bnxt_napi *bnapi;
4423
4424 if (bp->flags & BNXT_FLAG_USING_MSIX) {
4425 for (i = 0; i < bp->cp_nr_rings; i++) {
4426 bnapi = bp->bnapi[i];
4427 netif_napi_add(bp->dev, &bnapi->napi,
4428 bnxt_poll, 64);
c0c050c5
MC		 4429 }
4430 } else {
4431 bnapi = bp->bnapi[0];
4432 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
c0c050c5
MC		 4433 }
4434}
4435
4436static void bnxt_disable_napi(struct bnxt *bp)
4437{
4438 int i;
4439
4440 if (!bp->bnapi)
4441 return;
4442
4443 for (i = 0; i < bp->cp_nr_rings; i++) {
4444 napi_disable(&bp->bnapi[i]->napi);
4445 bnxt_disable_poll(bp->bnapi[i]);
4446 }
4447}
4448
4449static void bnxt_enable_napi(struct bnxt *bp)
4450{
4451 int i;
4452
4453 for (i = 0; i < bp->cp_nr_rings; i++) {
4454 bnxt_enable_poll(bp->bnapi[i]);
4455 napi_enable(&bp->bnapi[i]->napi);
4456 }
4457}
4458
4459static void bnxt_tx_disable(struct bnxt *bp)
4460{
4461 int i;
c0c050c5
MC		 4462 struct bnxt_tx_ring_info *txr;
4463 struct netdev_queue *txq;
4464
b6ab4b01 4465 if (bp->tx_ring) {
c0c050c5 4466 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4467 txr = &bp->tx_ring[i];
c0c050c5
MC		 4468 txq = netdev_get_tx_queue(bp->dev, i);
4469 __netif_tx_lock(txq, smp_processor_id());
4470 txr->dev_state = BNXT_DEV_STATE_CLOSING;
4471 __netif_tx_unlock(txq);
4472 }
4473 }
4474 /* Stop all TX queues */
4475 netif_tx_disable(bp->dev);
4476 netif_carrier_off(bp->dev);
4477}
4478
4479static void bnxt_tx_enable(struct bnxt *bp)
4480{
4481 int i;
c0c050c5
MC		 4482 struct bnxt_tx_ring_info *txr;
4483 struct netdev_queue *txq;
4484
4485 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4486 txr = &bp->tx_ring[i];
c0c050c5
MC		 4487 txq = netdev_get_tx_queue(bp->dev, i);
4488 txr->dev_state = 0;
4489 }
4490 netif_tx_wake_all_queues(bp->dev);
4491 if (bp->link_info.link_up)
4492 netif_carrier_on(bp->dev);
4493}
4494
4495static void bnxt_report_link(struct bnxt *bp)
4496{
4497 if (bp->link_info.link_up) {
4498 const char *duplex;
4499 const char *flow_ctrl;
4500 u16 speed;
4501
4502 netif_carrier_on(bp->dev);
4503 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4504 duplex = "full";
4505 else
4506 duplex = "half";
4507 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4508 flow_ctrl = "ON - receive & transmit";
4509 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4510 flow_ctrl = "ON - transmit";
4511 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4512 flow_ctrl = "ON - receive";
4513 else
4514 flow_ctrl = "none";
4515 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4516 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4517 speed, duplex, flow_ctrl);
4518 } else {
4519 netif_carrier_off(bp->dev);
4520 netdev_err(bp->dev, "NIC Link is Down\n");
4521 }
4522}
4523
4524static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4525{
4526 int rc = 0;
4527 struct bnxt_link_info *link_info = &bp->link_info;
4528 struct hwrm_port_phy_qcfg_input req = {0};
4529 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4530 u8 link_up = link_info->link_up;
4531
4532 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4533
4534 mutex_lock(&bp->hwrm_cmd_lock);
4535 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4536 if (rc) {
4537 mutex_unlock(&bp->hwrm_cmd_lock);
4538 return rc;
4539 }
4540
4541 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4542 link_info->phy_link_status = resp->link;
4543 link_info->duplex = resp->duplex;
4544 link_info->pause = resp->pause;
4545 link_info->auto_mode = resp->auto_mode;
4546 link_info->auto_pause_setting = resp->auto_pause;
3277360e 4547 link_info->lp_pause = resp->link_partner_adv_pause;
c0c050c5 4548 link_info->force_pause_setting = resp->force_pause;
c193554e 4549 link_info->duplex_setting = resp->duplex;
c0c050c5
MC		 4550 if (link_info->phy_link_status == BNXT_LINK_LINK)
4551 link_info->link_speed = le16_to_cpu(resp->link_speed);
4552 else
4553 link_info->link_speed = 0;
4554 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
4555 link_info->auto_link_speed = le16_to_cpu(resp->auto_link_speed);
4556 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4557 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
3277360e
MC		 4558 link_info->lp_auto_link_speeds =
4559 le16_to_cpu(resp->link_partner_adv_speeds);
c0c050c5
MC		 4560 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4561 link_info->phy_ver[0] = resp->phy_maj;
4562 link_info->phy_ver[1] = resp->phy_min;
4563 link_info->phy_ver[2] = resp->phy_bld;
4564 link_info->media_type = resp->media_type;
4565 link_info->transceiver = resp->transceiver_type;
4566 link_info->phy_addr = resp->phy_addr;
4567
4568 /* TODO: need to add more logic to report VF link */
4569 if (chng_link_state) {
4570 if (link_info->phy_link_status == BNXT_LINK_LINK)
4571 link_info->link_up = 1;
4572 else
4573 link_info->link_up = 0;
4574 if (link_up != link_info->link_up)
4575 bnxt_report_link(bp);
4576 } else {
4577 /* alwasy link down if not require to update link state */
4578 link_info->link_up = 0;
4579 }
4580 mutex_unlock(&bp->hwrm_cmd_lock);
4581 return 0;
4582}
4583
4584static void
4585bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4586{
4587 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
4588 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4589 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4590 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
49b5c7a1 4591 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
c0c050c5
MC		 4592 req->enables |=
4593 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4594 } else {
4595 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4596 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4597 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4598 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4599 req->enables |=
4600 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
4601 }
4602}
4603
4604static void bnxt_hwrm_set_link_common(struct bnxt *bp,
4605 struct hwrm_port_phy_cfg_input *req)
4606{
4607 u8 autoneg = bp->link_info.autoneg;
4608 u16 fw_link_speed = bp->link_info.req_link_speed;
4609 u32 advertising = bp->link_info.advertising;
4610
4611 if (autoneg & BNXT_AUTONEG_SPEED) {
4612 req->auto_mode |=
4613 PORT_PHY_CFG_REQ_AUTO_MODE_MASK;
4614
4615 req->enables |= cpu_to_le32(
4616 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
4617 req->auto_link_speed_mask = cpu_to_le16(advertising);
4618
4619 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
4620 req->flags |=
4621 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
4622 } else {
4623 req->force_link_speed = cpu_to_le16(fw_link_speed);
4624 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
4625 }
4626
4627 /* currently don't support half duplex */
4628 req->auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL;
4629 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX);
4630 /* tell chimp that the setting takes effect immediately */
4631 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4632}
4633
4634int bnxt_hwrm_set_pause(struct bnxt *bp)
4635{
4636 struct hwrm_port_phy_cfg_input req = {0};
4637 int rc;
4638
4639 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4640 bnxt_hwrm_set_pause_common(bp, &req);
4641
4642 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
4643 bp->link_info.force_link_chng)
4644 bnxt_hwrm_set_link_common(bp, &req);
4645
4646 mutex_lock(&bp->hwrm_cmd_lock);
4647 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4648 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
4649 /* since changing of pause setting doesn't trigger any link
4650 * change event, the driver needs to update the current pause
4651 * result upon successfully return of the phy_cfg command
4652 */
4653 bp->link_info.pause =
4654 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
4655 bp->link_info.auto_pause_setting = 0;
4656 if (!bp->link_info.force_link_chng)
4657 bnxt_report_link(bp);
4658 }
4659 bp->link_info.force_link_chng = false;
4660 mutex_unlock(&bp->hwrm_cmd_lock);
4661 return rc;
4662}
4663
4664int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause)
4665{
4666 struct hwrm_port_phy_cfg_input req = {0};
4667
4668 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4669 if (set_pause)
4670 bnxt_hwrm_set_pause_common(bp, &req);
4671
4672 bnxt_hwrm_set_link_common(bp, &req);
4673 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4674}
4675
4676static int bnxt_update_phy_setting(struct bnxt *bp)
4677{
4678 int rc;
4679 bool update_link = false;
4680 bool update_pause = false;
4681 struct bnxt_link_info *link_info = &bp->link_info;
4682
4683 rc = bnxt_update_link(bp, true);
4684 if (rc) {
4685 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
4686 rc);
4687 return rc;
4688 }
4689 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4690 link_info->auto_pause_setting != link_info->req_flow_ctrl)
4691 update_pause = true;
4692 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4693 link_info->force_pause_setting != link_info->req_flow_ctrl)
4694 update_pause = true;
c0c050c5
MC		 4695 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4696 if (BNXT_AUTO_MODE(link_info->auto_mode))
4697 update_link = true;
4698 if (link_info->req_link_speed != link_info->force_link_speed)
4699 update_link = true;
de73018f
MC		 4700 if (link_info->req_duplex != link_info->duplex_setting)
4701 update_link = true;
c0c050c5
MC		 4702 } else {
4703 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
4704 update_link = true;
4705 if (link_info->advertising != link_info->auto_link_speeds)
4706 update_link = true;
c0c050c5
MC		 4707 }
4708
4709 if (update_link)
4710 rc = bnxt_hwrm_set_link_setting(bp, update_pause);
4711 else if (update_pause)
4712 rc = bnxt_hwrm_set_pause(bp);
4713 if (rc) {
4714 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
4715 rc);
4716 return rc;
4717 }
4718
4719 return rc;
4720}
4721
11809490
JH		 4722/* Common routine to pre-map certain register block to different GRC window.
4723 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4724 * in PF and 3 windows in VF that can be customized to map in different
4725 * register blocks.
4726 */
4727static void bnxt_preset_reg_win(struct bnxt *bp)
4728{
4729 if (BNXT_PF(bp)) {
4730 /* CAG registers map to GRC window #4 */
4731 writel(BNXT_CAG_REG_BASE,
4732 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
4733 }
4734}
4735
c0c050c5
MC		 4736static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4737{
4738 int rc = 0;
4739
11809490 4740 bnxt_preset_reg_win(bp);
c0c050c5
MC		 4741 netif_carrier_off(bp->dev);
4742 if (irq_re_init) {
4743 rc = bnxt_setup_int_mode(bp);
4744 if (rc) {
4745 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
4746 rc);
4747 return rc;
4748 }
4749 }
4750 if ((bp->flags & BNXT_FLAG_RFS) &&
4751 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
4752 /* disable RFS if falling back to INTA */
4753 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
4754 bp->flags &= ~BNXT_FLAG_RFS;
4755 }
4756
4757 rc = bnxt_alloc_mem(bp, irq_re_init);
4758 if (rc) {
4759 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
4760 goto open_err_free_mem;
4761 }
4762
4763 if (irq_re_init) {
4764 bnxt_init_napi(bp);
4765 rc = bnxt_request_irq(bp);
4766 if (rc) {
4767 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
4768 goto open_err;
4769 }
4770 }
4771
4772 bnxt_enable_napi(bp);
4773
4774 rc = bnxt_init_nic(bp, irq_re_init);
4775 if (rc) {
4776 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
4777 goto open_err;
4778 }
4779
4780 if (link_re_init) {
4781 rc = bnxt_update_phy_setting(bp);
4782 if (rc)
ba41d46f 4783 netdev_warn(bp->dev, "failed to update phy settings\n");
c0c050c5
MC		 4784 }
4785
4786 if (irq_re_init) {
4787#if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4788 vxlan_get_rx_port(bp->dev);
4789#endif
4790 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4791 bp, htons(0x17c1),
4792 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE))
4793 bp->nge_port_cnt = 1;
4794 }
4795
caefe526 4796 set_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 4797 bnxt_enable_int(bp);
4798 /* Enable TX queues */
4799 bnxt_tx_enable(bp);
4800 mod_timer(&bp->timer, jiffies + bp->current_interval);
035a1539 4801 bnxt_update_link(bp, true);
c0c050c5
MC		 4802
4803 return 0;
4804
4805open_err:
4806 bnxt_disable_napi(bp);
4807 bnxt_del_napi(bp);
4808
4809open_err_free_mem:
4810 bnxt_free_skbs(bp);
4811 bnxt_free_irq(bp);
4812 bnxt_free_mem(bp, true);
4813 return rc;
4814}
4815
4816/* rtnl_lock held */
4817int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4818{
4819 int rc = 0;
4820
4821 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
4822 if (rc) {
4823 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
4824 dev_close(bp->dev);
4825 }
4826 return rc;
4827}
4828
4829static int bnxt_open(struct net_device *dev)
4830{
4831 struct bnxt *bp = netdev_priv(dev);
4832 int rc = 0;
4833
4834 rc = bnxt_hwrm_func_reset(bp);
4835 if (rc) {
4836 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
4837 rc);
4838 rc = -1;
4839 return rc;
4840 }
4841 return __bnxt_open_nic(bp, true, true);
4842}
4843
4844static void bnxt_disable_int_sync(struct bnxt *bp)
4845{
4846 int i;
4847
4848 atomic_inc(&bp->intr_sem);
4849 if (!netif_running(bp->dev))
4850 return;
4851
4852 bnxt_disable_int(bp);
4853 for (i = 0; i < bp->cp_nr_rings; i++)
4854 synchronize_irq(bp->irq_tbl[i].vector);
4855}
4856
4857int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4858{
4859 int rc = 0;
4860
4861#ifdef CONFIG_BNXT_SRIOV
4862 if (bp->sriov_cfg) {
4863 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
4864 !bp->sriov_cfg,
4865 BNXT_SRIOV_CFG_WAIT_TMO);
4866 if (rc)
4867 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
4868 }
4869#endif
4870 /* Change device state to avoid TX queue wake up's */
4871 bnxt_tx_disable(bp);
4872
caefe526 4873 clear_bit(BNXT_STATE_OPEN, &bp->state);
4cebdcec
MC		 4874 smp_mb__after_atomic();
4875 while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
4876 msleep(20);
c0c050c5
MC		 4877
4878 /* Flush rings before disabling interrupts */
4879 bnxt_shutdown_nic(bp, irq_re_init);
4880
4881 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4882
4883 bnxt_disable_napi(bp);
4884 bnxt_disable_int_sync(bp);
4885 del_timer_sync(&bp->timer);
4886 bnxt_free_skbs(bp);
4887
4888 if (irq_re_init) {
4889 bnxt_free_irq(bp);
4890 bnxt_del_napi(bp);
4891 }
4892 bnxt_free_mem(bp, irq_re_init);
4893 return rc;
4894}
4895
4896static int bnxt_close(struct net_device *dev)
4897{
4898 struct bnxt *bp = netdev_priv(dev);
4899
4900 bnxt_close_nic(bp, true, true);
4901 return 0;
4902}
4903
4904/* rtnl_lock held */
4905static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4906{
4907 switch (cmd) {
4908 case SIOCGMIIPHY:
4909 /* fallthru */
4910 case SIOCGMIIREG: {
4911 if (!netif_running(dev))
4912 return -EAGAIN;
4913
4914 return 0;
4915 }
4916
4917 case SIOCSMIIREG:
4918 if (!netif_running(dev))
4919 return -EAGAIN;
4920
4921 return 0;
4922
4923 default:
4924 /* do nothing */
4925 break;
4926 }
4927 return -EOPNOTSUPP;
4928}
4929
4930static struct rtnl_link_stats64 *
4931bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4932{
4933 u32 i;
4934 struct bnxt *bp = netdev_priv(dev);
4935
4936 memset(stats, 0, sizeof(struct rtnl_link_stats64));
4937
4938 if (!bp->bnapi)
4939 return stats;
4940
4941 /* TODO check if we need to synchronize with bnxt_close path */
4942 for (i = 0; i < bp->cp_nr_rings; i++) {
4943 struct bnxt_napi *bnapi = bp->bnapi[i];
4944 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4945 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
4946
4947 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
4948 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
4949 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
4950
4951 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
4952 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
4953 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
4954
4955 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
4956 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
4957 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
4958
4959 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
4960 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
4961 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
4962
4963 stats->rx_missed_errors +=
4964 le64_to_cpu(hw_stats->rx_discard_pkts);
4965
4966 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
4967
c0c050c5
MC		 4968 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
4969 }
4970
9947f83f
MC		 4971 if (bp->flags & BNXT_FLAG_PORT_STATS) {
4972 struct rx_port_stats *rx = bp->hw_rx_port_stats;
4973 struct tx_port_stats *tx = bp->hw_tx_port_stats;
4974
4975 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
4976 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
4977 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
4978 le64_to_cpu(rx->rx_ovrsz_frames) +
4979 le64_to_cpu(rx->rx_runt_frames);
4980 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
4981 le64_to_cpu(rx->rx_jbr_frames);
4982 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
4983 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
4984 stats->tx_errors = le64_to_cpu(tx->tx_err);
4985 }
4986
c0c050c5
MC		 4987 return stats;
4988}
4989
4990static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
4991{
4992 struct net_device *dev = bp->dev;
4993 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4994 struct netdev_hw_addr *ha;
4995 u8 *haddr;
4996 int mc_count = 0;
4997 bool update = false;
4998 int off = 0;
4999
5000 netdev_for_each_mc_addr(ha, dev) {
5001 if (mc_count >= BNXT_MAX_MC_ADDRS) {
5002 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5003 vnic->mc_list_count = 0;
5004 return false;
5005 }
5006 haddr = ha->addr;
5007 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
5008 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
5009 update = true;
5010 }
5011 off += ETH_ALEN;
5012 mc_count++;
5013 }
5014 if (mc_count)
5015 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
5016
5017 if (mc_count != vnic->mc_list_count) {
5018 vnic->mc_list_count = mc_count;
5019 update = true;
5020 }
5021 return update;
5022}
5023
5024static bool bnxt_uc_list_updated(struct bnxt *bp)
5025{
5026 struct net_device *dev = bp->dev;
5027 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5028 struct netdev_hw_addr *ha;
5029 int off = 0;
5030
5031 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
5032 return true;
5033
5034 netdev_for_each_uc_addr(ha, dev) {
5035 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
5036 return true;
5037
5038 off += ETH_ALEN;
5039 }
5040 return false;
5041}
5042
5043static void bnxt_set_rx_mode(struct net_device *dev)
5044{
5045 struct bnxt *bp = netdev_priv(dev);
5046 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5047 u32 mask = vnic->rx_mask;
5048 bool mc_update = false;
5049 bool uc_update;
5050
5051 if (!netif_running(dev))
5052 return;
5053
5054 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
5055 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
5056 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
5057
5058 /* Only allow PF to be in promiscuous mode */
5059 if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
5060 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5061
5062 uc_update = bnxt_uc_list_updated(bp);
5063
5064 if (dev->flags & IFF_ALLMULTI) {
5065 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5066 vnic->mc_list_count = 0;
5067 } else {
5068 mc_update = bnxt_mc_list_updated(bp, &mask);
5069 }
5070
5071 if (mask != vnic->rx_mask || uc_update || mc_update) {
5072 vnic->rx_mask = mask;
5073
5074 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
5075 schedule_work(&bp->sp_task);
5076 }
5077}
5078
b664f008 5079static int bnxt_cfg_rx_mode(struct bnxt *bp)
c0c050c5
MC		 5080{
5081 struct net_device *dev = bp->dev;
5082 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5083 struct netdev_hw_addr *ha;
5084 int i, off = 0, rc;
5085 bool uc_update;
5086
5087 netif_addr_lock_bh(dev);
5088 uc_update = bnxt_uc_list_updated(bp);
5089 netif_addr_unlock_bh(dev);
5090
5091 if (!uc_update)
5092 goto skip_uc;
5093
5094 mutex_lock(&bp->hwrm_cmd_lock);
5095 for (i = 1; i < vnic->uc_filter_count; i++) {
5096 struct hwrm_cfa_l2_filter_free_input req = {0};
5097
5098 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
5099 -1);
5100
5101 req.l2_filter_id = vnic->fw_l2_filter_id[i];
5102
5103 rc = _hwrm_send_message(bp, &req, sizeof(req),
5104 HWRM_CMD_TIMEOUT);
5105 }
5106 mutex_unlock(&bp->hwrm_cmd_lock);
5107
5108 vnic->uc_filter_count = 1;
5109
5110 netif_addr_lock_bh(dev);
5111 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
5112 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5113 } else {
5114 netdev_for_each_uc_addr(ha, dev) {
5115 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
5116 off += ETH_ALEN;
5117 vnic->uc_filter_count++;
5118 }
5119 }
5120 netif_addr_unlock_bh(dev);
5121
5122 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
5123 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
5124 if (rc) {
5125 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
5126 rc);
5127 vnic->uc_filter_count = i;
b664f008 5128 return rc;
c0c050c5
MC		 5129 }
5130 }
5131
5132skip_uc:
5133 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
5134 if (rc)
5135 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
5136 rc);
b664f008
MC		 5137
5138 return rc;
c0c050c5
MC		 5139}
5140
2bcfa6f6
MC		 5141static bool bnxt_rfs_capable(struct bnxt *bp)
5142{
5143#ifdef CONFIG_RFS_ACCEL
5144 struct bnxt_pf_info *pf = &bp->pf;
5145 int vnics;
5146
5147 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
5148 return false;
5149
5150 vnics = 1 + bp->rx_nr_rings;
5151 if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics)
5152 return false;
5153
5154 return true;
5155#else
5156 return false;
5157#endif
5158}
5159
c0c050c5
MC		 5160static netdev_features_t bnxt_fix_features(struct net_device *dev,
5161 netdev_features_t features)
5162{
2bcfa6f6
MC		 5163 struct bnxt *bp = netdev_priv(dev);
5164
5165 if (!bnxt_rfs_capable(bp))
5166 features &= ~NETIF_F_NTUPLE;
c0c050c5
MC		 5167 return features;
5168}
5169
5170static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
5171{
5172 struct bnxt *bp = netdev_priv(dev);
5173 u32 flags = bp->flags;
5174 u32 changes;
5175 int rc = 0;
5176 bool re_init = false;
5177 bool update_tpa = false;
5178
5179 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
5180 if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
5181 flags |= BNXT_FLAG_GRO;
5182 if (features & NETIF_F_LRO)
5183 flags |= BNXT_FLAG_LRO;
5184
5185 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5186 flags |= BNXT_FLAG_STRIP_VLAN;
5187
5188 if (features & NETIF_F_NTUPLE)
5189 flags |= BNXT_FLAG_RFS;
5190
5191 changes = flags ^ bp->flags;
5192 if (changes & BNXT_FLAG_TPA) {
5193 update_tpa = true;
5194 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5195 (flags & BNXT_FLAG_TPA) == 0)
5196 re_init = true;
5197 }
5198
5199 if (changes & ~BNXT_FLAG_TPA)
5200 re_init = true;
5201
5202 if (flags != bp->flags) {
5203 u32 old_flags = bp->flags;
5204
5205 bp->flags = flags;
5206
2bcfa6f6 5207 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
c0c050c5
MC		 5208 if (update_tpa)
5209 bnxt_set_ring_params(bp);
5210 return rc;
5211 }
5212
5213 if (re_init) {
5214 bnxt_close_nic(bp, false, false);
5215 if (update_tpa)
5216 bnxt_set_ring_params(bp);
5217
5218 return bnxt_open_nic(bp, false, false);
5219 }
5220 if (update_tpa) {
5221 rc = bnxt_set_tpa(bp,
5222 (flags & BNXT_FLAG_TPA) ?
5223 true : false);
5224 if (rc)
5225 bp->flags = old_flags;
5226 }
5227 }
5228 return rc;
5229}
5230
9f554590
MC		 5231static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
5232{
b6ab4b01 5233 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9f554590
MC		 5234 int i = bnapi->index;
5235
3b2b7d9d
MC		 5236 if (!txr)
5237 return;
5238
9f554590
MC		 5239 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5240 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
5241 txr->tx_cons);
5242}
5243
5244static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
5245{
b6ab4b01 5246 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9f554590
MC		 5247 int i = bnapi->index;
5248
3b2b7d9d
MC		 5249 if (!rxr)
5250 return;
5251
9f554590
MC		 5252 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5253 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
5254 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
5255 rxr->rx_sw_agg_prod);
5256}
5257
5258static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
5259{
5260 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5261 int i = bnapi->index;
5262
5263 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5264 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
5265}
5266
c0c050c5
MC		 5267static void bnxt_dbg_dump_states(struct bnxt *bp)
5268{
5269 int i;
5270 struct bnxt_napi *bnapi;
c0c050c5
MC		 5271
5272 for (i = 0; i < bp->cp_nr_rings; i++) {
5273 bnapi = bp->bnapi[i];
c0c050c5 5274 if (netif_msg_drv(bp)) {
9f554590
MC		 5275 bnxt_dump_tx_sw_state(bnapi);
5276 bnxt_dump_rx_sw_state(bnapi);
5277 bnxt_dump_cp_sw_state(bnapi);
c0c050c5
MC		 5278 }
5279 }
5280}
5281
5282static void bnxt_reset_task(struct bnxt *bp)
5283{
5284 bnxt_dbg_dump_states(bp);
028de140
MC		 5285 if (netif_running(bp->dev)) {
5286 bnxt_close_nic(bp, false, false);
5287 bnxt_open_nic(bp, false, false);
5288 }
c0c050c5
MC		 5289}
5290
5291static void bnxt_tx_timeout(struct net_device *dev)
5292{
5293 struct bnxt *bp = netdev_priv(dev);
5294
5295 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
5296 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5297 schedule_work(&bp->sp_task);
5298}
5299
5300#ifdef CONFIG_NET_POLL_CONTROLLER
5301static void bnxt_poll_controller(struct net_device *dev)
5302{
5303 struct bnxt *bp = netdev_priv(dev);
5304 int i;
5305
5306 for (i = 0; i < bp->cp_nr_rings; i++) {
5307 struct bnxt_irq *irq = &bp->irq_tbl[i];
5308
5309 disable_irq(irq->vector);
5310 irq->handler(irq->vector, bp->bnapi[i]);
5311 enable_irq(irq->vector);
5312 }
5313}
5314#endif
5315
5316static void bnxt_timer(unsigned long data)
5317{
5318 struct bnxt *bp = (struct bnxt *)data;
5319 struct net_device *dev = bp->dev;
5320
5321 if (!netif_running(dev))
5322 return;
5323
5324 if (atomic_read(&bp->intr_sem) != 0)
5325 goto bnxt_restart_timer;
5326
3bdf56c4
MC		 5327 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
5328 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
5329 schedule_work(&bp->sp_task);
5330 }
c0c050c5
MC		 5331bnxt_restart_timer:
5332 mod_timer(&bp->timer, jiffies + bp->current_interval);
5333}
5334
5335static void bnxt_cfg_ntp_filters(struct bnxt *);
5336
5337static void bnxt_sp_task(struct work_struct *work)
5338{
5339 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5340 int rc;
5341
4cebdcec
MC		 5342 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5343 smp_mb__after_atomic();
5344 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5345 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5 5346 return;
4cebdcec 5347 }
c0c050c5
MC		 5348
5349 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5350 bnxt_cfg_rx_mode(bp);
5351
5352 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5353 bnxt_cfg_ntp_filters(bp);
5354 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5355 rc = bnxt_update_link(bp, true);
5356 if (rc)
5357 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5358 rc);
5359 }
5360 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5361 bnxt_hwrm_exec_fwd_req(bp);
5362 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5363 bnxt_hwrm_tunnel_dst_port_alloc(
5364 bp, bp->vxlan_port,
5365 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5366 }
5367 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5368 bnxt_hwrm_tunnel_dst_port_free(
5369 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5370 }
028de140
MC		 5371 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) {
5372 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5373 * for BNXT_STATE_IN_SP_TASK to clear.
5374 */
5375 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5376 rtnl_lock();
c0c050c5 5377 bnxt_reset_task(bp);
028de140
MC		 5378 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5379 rtnl_unlock();
5380 }
4cebdcec 5381
3bdf56c4
MC		 5382 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
5383 bnxt_hwrm_port_qstats(bp);
5384
4cebdcec
MC		 5385 smp_mb__before_atomic();
5386 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5
MC		 5387}
5388
5389static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5390{
5391 int rc;
5392 struct bnxt *bp = netdev_priv(dev);
5393
5394 SET_NETDEV_DEV(dev, &pdev->dev);
5395
5396 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5397 rc = pci_enable_device(pdev);
5398 if (rc) {
5399 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5400 goto init_err;
5401 }
5402
5403 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5404 dev_err(&pdev->dev,
5405 "Cannot find PCI device base address, aborting\n");
5406 rc = -ENODEV;
5407 goto init_err_disable;
5408 }
5409
5410 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5411 if (rc) {
5412 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5413 goto init_err_disable;
5414 }
5415
5416 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5417 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5418 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5419 goto init_err_disable;
5420 }
5421
5422 pci_set_master(pdev);
5423
5424 bp->dev = dev;
5425 bp->pdev = pdev;
5426
5427 bp->bar0 = pci_ioremap_bar(pdev, 0);
5428 if (!bp->bar0) {
5429 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5430 rc = -ENOMEM;
5431 goto init_err_release;
5432 }
5433
5434 bp->bar1 = pci_ioremap_bar(pdev, 2);
5435 if (!bp->bar1) {
5436 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5437 rc = -ENOMEM;
5438 goto init_err_release;
5439 }
5440
5441 bp->bar2 = pci_ioremap_bar(pdev, 4);
5442 if (!bp->bar2) {
5443 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5444 rc = -ENOMEM;
5445 goto init_err_release;
5446 }
5447
6316ea6d
SB		 5448 pci_enable_pcie_error_reporting(pdev);
5449
c0c050c5
MC		 5450 INIT_WORK(&bp->sp_task, bnxt_sp_task);
5451
5452 spin_lock_init(&bp->ntp_fltr_lock);
5453
5454 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5455 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5456
dfb5b894 5457 /* tick values in micro seconds */
dfc9c94a
MC		 5458 bp->rx_coal_ticks = 12;
5459 bp->rx_coal_bufs = 30;
dfb5b894
MC		 5460 bp->rx_coal_ticks_irq = 1;
5461 bp->rx_coal_bufs_irq = 2;
c0c050c5 5462
dfc9c94a
MC		 5463 bp->tx_coal_ticks = 25;
5464 bp->tx_coal_bufs = 30;
5465 bp->tx_coal_ticks_irq = 2;
5466 bp->tx_coal_bufs_irq = 2;
5467
c0c050c5
MC		 5468 init_timer(&bp->timer);
5469 bp->timer.data = (unsigned long)bp;
5470 bp->timer.function = bnxt_timer;
5471 bp->current_interval = BNXT_TIMER_INTERVAL;
5472
caefe526 5473 clear_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 5474
5475 return 0;
5476
5477init_err_release:
5478 if (bp->bar2) {
5479 pci_iounmap(pdev, bp->bar2);
5480 bp->bar2 = NULL;
5481 }
5482
5483 if (bp->bar1) {
5484 pci_iounmap(pdev, bp->bar1);
5485 bp->bar1 = NULL;
5486 }
5487
5488 if (bp->bar0) {
5489 pci_iounmap(pdev, bp->bar0);
5490 bp->bar0 = NULL;
5491 }
5492
5493 pci_release_regions(pdev);
5494
5495init_err_disable:
5496 pci_disable_device(pdev);
5497
5498init_err:
5499 return rc;
5500}
5501
5502/* rtnl_lock held */
5503static int bnxt_change_mac_addr(struct net_device *dev, void *p)
5504{
5505 struct sockaddr *addr = p;
1fc2cfd0
JH		 5506 struct bnxt *bp = netdev_priv(dev);
5507 int rc = 0;
c0c050c5
MC		 5508
5509 if (!is_valid_ether_addr(addr->sa_data))
5510 return -EADDRNOTAVAIL;
5511
bdd4347b
JH		 5512#ifdef CONFIG_BNXT_SRIOV
5513 if (BNXT_VF(bp) && is_valid_ether_addr(bp->vf.mac_addr))
5514 return -EADDRNOTAVAIL;
5515#endif
5516
1fc2cfd0
JH		 5517 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
5518 return 0;
5519
c0c050c5 5520 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1fc2cfd0
JH		 5521 if (netif_running(dev)) {
5522 bnxt_close_nic(bp, false, false);
5523 rc = bnxt_open_nic(bp, false, false);
5524 }
c0c050c5 5525
1fc2cfd0 5526 return rc;
c0c050c5
MC		 5527}
5528
5529/* rtnl_lock held */
5530static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
5531{
5532 struct bnxt *bp = netdev_priv(dev);
5533
5534 if (new_mtu < 60 || new_mtu > 9000)
5535 return -EINVAL;
5536
5537 if (netif_running(dev))
5538 bnxt_close_nic(bp, false, false);
5539
5540 dev->mtu = new_mtu;
5541 bnxt_set_ring_params(bp);
5542
5543 if (netif_running(dev))
5544 return bnxt_open_nic(bp, false, false);
5545
5546 return 0;
5547}
5548
16e5cc64
JF		 5549static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
5550 struct tc_to_netdev *ntc)
c0c050c5
MC		 5551{
5552 struct bnxt *bp = netdev_priv(dev);
16e5cc64 5553 u8 tc;
c0c050c5 5554
5eb4dce3 5555 if (ntc->type != TC_SETUP_MQPRIO)
e4c6734e
JF		 5556 return -EINVAL;
5557
16e5cc64
JF		 5558 tc = ntc->tc;
5559
c0c050c5
MC		 5560 if (tc > bp->max_tc) {
5561 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
5562 tc, bp->max_tc);
5563 return -EINVAL;
5564 }
5565
5566 if (netdev_get_num_tc(dev) == tc)
5567 return 0;
5568
5569 if (tc) {
6e6c5a57 5570 int max_rx_rings, max_tx_rings, rc;
01657bcd
MC		 5571 bool sh = false;
5572
5573 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5574 sh = true;
c0c050c5 5575
01657bcd 5576 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6e6c5a57 5577 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
c0c050c5
MC		 5578 return -ENOMEM;
5579 }
5580
5581 /* Needs to close the device and do hw resource re-allocations */
5582 if (netif_running(bp->dev))
5583 bnxt_close_nic(bp, true, false);
5584
5585 if (tc) {
5586 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
5587 netdev_set_num_tc(dev, tc);
5588 } else {
5589 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5590 netdev_reset_tc(dev);
5591 }
5592 bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
5593 bp->num_stat_ctxs = bp->cp_nr_rings;
5594
5595 if (netif_running(bp->dev))
5596 return bnxt_open_nic(bp, true, false);
5597
5598 return 0;
5599}
5600
5601#ifdef CONFIG_RFS_ACCEL
5602static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
5603 struct bnxt_ntuple_filter *f2)
5604{
5605 struct flow_keys *keys1 = &f1->fkeys;
5606 struct flow_keys *keys2 = &f2->fkeys;
5607
5608 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
5609 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
5610 keys1->ports.ports == keys2->ports.ports &&
5611 keys1->basic.ip_proto == keys2->basic.ip_proto &&
5612 keys1->basic.n_proto == keys2->basic.n_proto &&
5613 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
5614 return true;
5615
5616 return false;
5617}
5618
5619static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
5620 u16 rxq_index, u32 flow_id)
5621{
5622 struct bnxt *bp = netdev_priv(dev);
5623 struct bnxt_ntuple_filter *fltr, *new_fltr;
5624 struct flow_keys *fkeys;
5625 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
84e86b98 5626 int rc = 0, idx, bit_id;
c0c050c5
MC		 5627 struct hlist_head *head;
5628
5629 if (skb->encapsulation)
5630 return -EPROTONOSUPPORT;
5631
5632 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
5633 if (!new_fltr)
5634 return -ENOMEM;
5635
5636 fkeys = &new_fltr->fkeys;
5637 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
5638 rc = -EPROTONOSUPPORT;
5639 goto err_free;
5640 }
5641
5642 if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
5643 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
5644 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
5645 rc = -EPROTONOSUPPORT;
5646 goto err_free;
5647 }
5648
5649 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
5650
5651 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
5652 head = &bp->ntp_fltr_hash_tbl[idx];
5653 rcu_read_lock();
5654 hlist_for_each_entry_rcu(fltr, head, hash) {
5655 if (bnxt_fltr_match(fltr, new_fltr)) {
5656 rcu_read_unlock();
5657 rc = 0;
5658 goto err_free;
5659 }
5660 }
5661 rcu_read_unlock();
5662
5663 spin_lock_bh(&bp->ntp_fltr_lock);
84e86b98
MC		 5664 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
5665 BNXT_NTP_FLTR_MAX_FLTR, 0);
5666 if (bit_id < 0) {
c0c050c5
MC		 5667 spin_unlock_bh(&bp->ntp_fltr_lock);
5668 rc = -ENOMEM;
5669 goto err_free;
5670 }
5671
84e86b98 5672 new_fltr->sw_id = (u16)bit_id;
c0c050c5
MC		 5673 new_fltr->flow_id = flow_id;
5674 new_fltr->rxq = rxq_index;
5675 hlist_add_head_rcu(&new_fltr->hash, head);
5676 bp->ntp_fltr_count++;
5677 spin_unlock_bh(&bp->ntp_fltr_lock);
5678
5679 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
5680 schedule_work(&bp->sp_task);
5681
5682 return new_fltr->sw_id;
5683
5684err_free:
5685 kfree(new_fltr);
5686 return rc;
5687}
5688
5689static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5690{
5691 int i;
5692
5693 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
5694 struct hlist_head *head;
5695 struct hlist_node *tmp;
5696 struct bnxt_ntuple_filter *fltr;
5697 int rc;
5698
5699 head = &bp->ntp_fltr_hash_tbl[i];
5700 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
5701 bool del = false;
5702
5703 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
5704 if (rps_may_expire_flow(bp->dev, fltr->rxq,
5705 fltr->flow_id,
5706 fltr->sw_id)) {
5707 bnxt_hwrm_cfa_ntuple_filter_free(bp,
5708 fltr);
5709 del = true;
5710 }
5711 } else {
5712 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
5713 fltr);
5714 if (rc)
5715 del = true;
5716 else
5717 set_bit(BNXT_FLTR_VALID, &fltr->state);
5718 }
5719
5720 if (del) {
5721 spin_lock_bh(&bp->ntp_fltr_lock);
5722 hlist_del_rcu(&fltr->hash);
5723 bp->ntp_fltr_count--;
5724 spin_unlock_bh(&bp->ntp_fltr_lock);
5725 synchronize_rcu();
5726 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
5727 kfree(fltr);
5728 }
5729 }
5730 }
19241368
JH		 5731 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
5732 netdev_info(bp->dev, "Receive PF driver unload event!");
c0c050c5
MC		 5733}
5734
5735#else
5736
5737static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5738{
5739}
5740
5741#endif /* CONFIG_RFS_ACCEL */
5742
5743static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5744 __be16 port)
5745{
5746 struct bnxt *bp = netdev_priv(dev);
5747
5748 if (!netif_running(dev))
5749 return;
5750
5751 if (sa_family != AF_INET6 && sa_family != AF_INET)
5752 return;
5753
5754 if (bp->vxlan_port_cnt && bp->vxlan_port != port)
5755 return;
5756
5757 bp->vxlan_port_cnt++;
5758 if (bp->vxlan_port_cnt == 1) {
5759 bp->vxlan_port = port;
5760 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
5761 schedule_work(&bp->sp_task);
5762 }
5763}
5764
5765static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5766 __be16 port)
5767{
5768 struct bnxt *bp = netdev_priv(dev);
5769
5770 if (!netif_running(dev))
5771 return;
5772
5773 if (sa_family != AF_INET6 && sa_family != AF_INET)
5774 return;
5775
5776 if (bp->vxlan_port_cnt && bp->vxlan_port == port) {
5777 bp->vxlan_port_cnt--;
5778
5779 if (bp->vxlan_port_cnt == 0) {
5780 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
5781 schedule_work(&bp->sp_task);
5782 }
5783 }
5784}
5785
5786static const struct net_device_ops bnxt_netdev_ops = {
5787 .ndo_open = bnxt_open,
5788 .ndo_start_xmit = bnxt_start_xmit,
5789 .ndo_stop = bnxt_close,
5790 .ndo_get_stats64 = bnxt_get_stats64,
5791 .ndo_set_rx_mode = bnxt_set_rx_mode,
5792 .ndo_do_ioctl = bnxt_ioctl,
5793 .ndo_validate_addr = eth_validate_addr,
5794 .ndo_set_mac_address = bnxt_change_mac_addr,
5795 .ndo_change_mtu = bnxt_change_mtu,
5796 .ndo_fix_features = bnxt_fix_features,
5797 .ndo_set_features = bnxt_set_features,
5798 .ndo_tx_timeout = bnxt_tx_timeout,
5799#ifdef CONFIG_BNXT_SRIOV
5800 .ndo_get_vf_config = bnxt_get_vf_config,
5801 .ndo_set_vf_mac = bnxt_set_vf_mac,
5802 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
5803 .ndo_set_vf_rate = bnxt_set_vf_bw,
5804 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
5805 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
5806#endif
5807#ifdef CONFIG_NET_POLL_CONTROLLER
5808 .ndo_poll_controller = bnxt_poll_controller,
5809#endif
5810 .ndo_setup_tc = bnxt_setup_tc,
5811#ifdef CONFIG_RFS_ACCEL
5812 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
5813#endif
5814 .ndo_add_vxlan_port = bnxt_add_vxlan_port,
5815 .ndo_del_vxlan_port = bnxt_del_vxlan_port,
5816#ifdef CONFIG_NET_RX_BUSY_POLL
5817 .ndo_busy_poll = bnxt_busy_poll,
5818#endif
5819};
5820
5821static void bnxt_remove_one(struct pci_dev *pdev)
5822{
5823 struct net_device *dev = pci_get_drvdata(pdev);
5824 struct bnxt *bp = netdev_priv(dev);
5825
5826 if (BNXT_PF(bp))
5827 bnxt_sriov_disable(bp);
5828
6316ea6d 5829 pci_disable_pcie_error_reporting(pdev);
c0c050c5
MC		 5830 unregister_netdev(dev);
5831 cancel_work_sync(&bp->sp_task);
5832 bp->sp_event = 0;
5833
be58a0da 5834 bnxt_hwrm_func_drv_unrgtr(bp);
c0c050c5
MC		 5835 bnxt_free_hwrm_resources(bp);
5836 pci_iounmap(pdev, bp->bar2);
5837 pci_iounmap(pdev, bp->bar1);
5838 pci_iounmap(pdev, bp->bar0);
5839 free_netdev(dev);
5840
5841 pci_release_regions(pdev);
5842 pci_disable_device(pdev);
5843}
5844
5845static int bnxt_probe_phy(struct bnxt *bp)
5846{
5847 int rc = 0;
5848 struct bnxt_link_info *link_info = &bp->link_info;
c0c050c5
MC		 5849
5850 rc = bnxt_update_link(bp, false);
5851 if (rc) {
5852 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
5853 rc);
5854 return rc;
5855 }
5856
5857 /*initialize the ethool setting copy with NVM settings */
0d8abf02
MC		 5858 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
5859 link_info->autoneg = BNXT_AUTONEG_SPEED |
5860 BNXT_AUTONEG_FLOW_CTRL;
5861 link_info->advertising = link_info->auto_link_speeds;
c0c050c5 5862 link_info->req_flow_ctrl = link_info->auto_pause_setting;
0d8abf02
MC		 5863 } else {
5864 link_info->req_link_speed = link_info->force_link_speed;
5865 link_info->req_duplex = link_info->duplex_setting;
c0c050c5
MC		 5866 link_info->req_flow_ctrl = link_info->force_pause_setting;
5867 }
c0c050c5
MC		 5868 return rc;
5869}
5870
5871static int bnxt_get_max_irq(struct pci_dev *pdev)
5872{
5873 u16 ctrl;
5874
5875 if (!pdev->msix_cap)
5876 return 1;
5877
5878 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
5879 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
5880}
5881
6e6c5a57
MC		 5882static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
5883 int *max_cp)
c0c050c5 5884{
6e6c5a57 5885 int max_ring_grps = 0;
c0c050c5 5886
379a80a1 5887#ifdef CONFIG_BNXT_SRIOV
415b6f19 5888 if (!BNXT_PF(bp)) {
c0c050c5
MC		 5889 *max_tx = bp->vf.max_tx_rings;
5890 *max_rx = bp->vf.max_rx_rings;
6e6c5a57
MC		 5891 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
5892 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
b72d4a68 5893 max_ring_grps = bp->vf.max_hw_ring_grps;
415b6f19 5894 } else
379a80a1 5895#endif
415b6f19
AB		 5896 {
5897 *max_tx = bp->pf.max_tx_rings;
5898 *max_rx = bp->pf.max_rx_rings;
5899 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5900 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
5901 max_ring_grps = bp->pf.max_hw_ring_grps;
c0c050c5 5902 }
415b6f19 5903
c0c050c5
MC		 5904 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5905 *max_rx >>= 1;
b72d4a68 5906 *max_rx = min_t(int, *max_rx, max_ring_grps);
6e6c5a57
MC		 5907}
5908
5909int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
5910{
5911 int rx, tx, cp;
5912
5913 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
5914 if (!rx || !tx || !cp)
5915 return -ENOMEM;
5916
5917 *max_rx = rx;
5918 *max_tx = tx;
5919 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
5920}
5921
5922static int bnxt_set_dflt_rings(struct bnxt *bp)
5923{
5924 int dflt_rings, max_rx_rings, max_tx_rings, rc;
5925 bool sh = true;
5926
5927 if (sh)
5928 bp->flags |= BNXT_FLAG_SHARED_RINGS;
5929 dflt_rings = netif_get_num_default_rss_queues();
5930 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
5931 if (rc)
5932 return rc;
5933 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
5934 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
5935 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5936 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5937 bp->tx_nr_rings + bp->rx_nr_rings;
5938 bp->num_stat_ctxs = bp->cp_nr_rings;
5939 return rc;
c0c050c5
MC		 5940}
5941
5942static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5943{
5944 static int version_printed;
5945 struct net_device *dev;
5946 struct bnxt *bp;
6e6c5a57 5947 int rc, max_irqs;
c0c050c5
MC		 5948
5949 if (version_printed++ == 0)
5950 pr_info("%s", version);
5951
5952 max_irqs = bnxt_get_max_irq(pdev);
5953 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
5954 if (!dev)
5955 return -ENOMEM;
5956
5957 bp = netdev_priv(dev);
5958
5959 if (bnxt_vf_pciid(ent->driver_data))
5960 bp->flags |= BNXT_FLAG_VF;
5961
2bcfa6f6 5962 if (pdev->msix_cap)
c0c050c5 5963 bp->flags |= BNXT_FLAG_MSIX_CAP;
c0c050c5
MC		 5964
5965 rc = bnxt_init_board(pdev, dev);
5966 if (rc < 0)
5967 goto init_err_free;
5968
5969 dev->netdev_ops = &bnxt_netdev_ops;
5970 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
5971 dev->ethtool_ops = &bnxt_ethtool_ops;
5972
5973 pci_set_drvdata(pdev, dev);
5974
5975 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5976 NETIF_F_TSO | NETIF_F_TSO6 |
5977 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5978 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT |
5979 NETIF_F_RXHASH |
5980 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
5981
c0c050c5
MC		 5982 dev->hw_enc_features =
5983 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5984 NETIF_F_TSO | NETIF_F_TSO6 |
5985 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5986 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
5987 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
5988 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
5989 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
5990 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
5991 dev->priv_flags |= IFF_UNICAST_FLT;
5992
5993#ifdef CONFIG_BNXT_SRIOV
5994 init_waitqueue_head(&bp->sriov_cfg_wait);
5995#endif
5996 rc = bnxt_alloc_hwrm_resources(bp);
5997 if (rc)
5998 goto init_err;
5999
6000 mutex_init(&bp->hwrm_cmd_lock);
6001 bnxt_hwrm_ver_get(bp);
6002
6003 rc = bnxt_hwrm_func_drv_rgtr(bp);
6004 if (rc)
6005 goto init_err;
6006
6007 /* Get the MAX capabilities for this function */
6008 rc = bnxt_hwrm_func_qcaps(bp);
6009 if (rc) {
6010 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
6011 rc);
6012 rc = -1;
6013 goto init_err;
6014 }
6015
6016 rc = bnxt_hwrm_queue_qportcfg(bp);
6017 if (rc) {
6018 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
6019 rc);
6020 rc = -1;
6021 goto init_err;
6022 }
6023
6024 bnxt_set_tpa_flags(bp);
6025 bnxt_set_ring_params(bp);
bdd4347b 6026 if (BNXT_PF(bp))
c0c050c5 6027 bp->pf.max_irqs = max_irqs;
379a80a1 6028#if defined(CONFIG_BNXT_SRIOV)
bdd4347b 6029 else
c0c050c5 6030 bp->vf.max_irqs = max_irqs;
379a80a1 6031#endif
6e6c5a57 6032 bnxt_set_dflt_rings(bp);
c0c050c5 6033
2bcfa6f6
MC		 6034 if (BNXT_PF(bp)) {
6035 dev->hw_features |= NETIF_F_NTUPLE;
6036 if (bnxt_rfs_capable(bp)) {
6037 bp->flags |= BNXT_FLAG_RFS;
6038 dev->features |= NETIF_F_NTUPLE;
6039 }
6040 }
6041
c0c050c5
MC		 6042 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
6043 bp->flags |= BNXT_FLAG_STRIP_VLAN;
6044
6045 rc = bnxt_probe_phy(bp);
6046 if (rc)
6047 goto init_err;
6048
6049 rc = register_netdev(dev);
6050 if (rc)
6051 goto init_err;
6052
6053 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
6054 board_info[ent->driver_data].name,
6055 (long)pci_resource_start(pdev, 0), dev->dev_addr);
6056
6057 return 0;
6058
6059init_err:
6060 pci_iounmap(pdev, bp->bar0);
6061 pci_release_regions(pdev);
6062 pci_disable_device(pdev);
6063
6064init_err_free:
6065 free_netdev(dev);
6066 return rc;
6067}
6068
6316ea6d
SB		 6069/**
6070 * bnxt_io_error_detected - called when PCI error is detected
6071 * @pdev: Pointer to PCI device
6072 * @state: The current pci connection state
6073 *
6074 * This function is called after a PCI bus error affecting
6075 * this device has been detected.
6076 */
6077static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
6078 pci_channel_state_t state)
6079{
6080 struct net_device *netdev = pci_get_drvdata(pdev);
6081
6082 netdev_info(netdev, "PCI I/O error detected\n");
6083
6084 rtnl_lock();
6085 netif_device_detach(netdev);
6086
6087 if (state == pci_channel_io_perm_failure) {
6088 rtnl_unlock();
6089 return PCI_ERS_RESULT_DISCONNECT;
6090 }
6091
6092 if (netif_running(netdev))
6093 bnxt_close(netdev);
6094
6095 pci_disable_device(pdev);
6096 rtnl_unlock();
6097
6098 /* Request a slot slot reset. */
6099 return PCI_ERS_RESULT_NEED_RESET;
6100}
6101
6102/**
6103 * bnxt_io_slot_reset - called after the pci bus has been reset.
6104 * @pdev: Pointer to PCI device
6105 *
6106 * Restart the card from scratch, as if from a cold-boot.
6107 * At this point, the card has exprienced a hard reset,
6108 * followed by fixups by BIOS, and has its config space
6109 * set up identically to what it was at cold boot.
6110 */
6111static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
6112{
6113 struct net_device *netdev = pci_get_drvdata(pdev);
6114 struct bnxt *bp = netdev_priv(netdev);
6115 int err = 0;
6116 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
6117
6118 netdev_info(bp->dev, "PCI Slot Reset\n");
6119
6120 rtnl_lock();
6121
6122 if (pci_enable_device(pdev)) {
6123 dev_err(&pdev->dev,
6124 "Cannot re-enable PCI device after reset.\n");
6125 } else {
6126 pci_set_master(pdev);
6127
6128 if (netif_running(netdev))
6129 err = bnxt_open(netdev);
6130
6131 if (!err)
6132 result = PCI_ERS_RESULT_RECOVERED;
6133 }
6134
6135 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
6136 dev_close(netdev);
6137
6138 rtnl_unlock();
6139
6140 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6141 if (err) {
6142 dev_err(&pdev->dev,
6143 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
6144 err); /* non-fatal, continue */
6145 }
6146
6147 return PCI_ERS_RESULT_RECOVERED;
6148}
6149
6150/**
6151 * bnxt_io_resume - called when traffic can start flowing again.
6152 * @pdev: Pointer to PCI device
6153 *
6154 * This callback is called when the error recovery driver tells
6155 * us that its OK to resume normal operation.
6156 */
6157static void bnxt_io_resume(struct pci_dev *pdev)
6158{
6159 struct net_device *netdev = pci_get_drvdata(pdev);
6160
6161 rtnl_lock();
6162
6163 netif_device_attach(netdev);
6164
6165 rtnl_unlock();
6166}
6167
6168static const struct pci_error_handlers bnxt_err_handler = {
6169 .error_detected = bnxt_io_error_detected,
6170 .slot_reset = bnxt_io_slot_reset,
6171 .resume = bnxt_io_resume
6172};
6173
c0c050c5
MC		 6174static struct pci_driver bnxt_pci_driver = {
6175 .name = DRV_MODULE_NAME,
6176 .id_table = bnxt_pci_tbl,
6177 .probe = bnxt_init_one,
6178 .remove = bnxt_remove_one,
6316ea6d 6179 .err_handler = &bnxt_err_handler,
c0c050c5
MC		 6180#if defined(CONFIG_BNXT_SRIOV)
6181 .sriov_configure = bnxt_sriov_configure,
6182#endif
6183};
6184
6185module_pci_driver(bnxt_pci_driver);
Linux kernel - Deliverables
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