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ipv4: do not use this_cpu_ptr() in preemptible context
[deliverable/linux.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
45
46#include <asm/unaligned.h>
47
48#include "bcmgenet.h"
49
50/* Maximum number of hardware queues, downsized if needed */
51#define GENET_MAX_MQ_CNT 4
52
53/* Default highest priority queue for multi queue support */
54#define GENET_Q0_PRIORITY 0
55
56#define GENET_DEFAULT_BD_CNT \
57 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
58
59#define RX_BUF_LENGTH 2048
60#define SKB_ALIGNMENT 32
61
62/* Tx/Rx DMA register offset, skip 256 descriptors */
63#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
64#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
65
66#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
67 TOTAL_DESC * DMA_DESC_SIZE)
68
69#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 73 void __iomem *d, u32 value)
1c1008c7
FF		 74{
75 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
76}
77
78static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
c91b7f66 79 void __iomem *d)
1c1008c7
FF		 80{
81 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
82}
83
84static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
85 void __iomem *d,
86 dma_addr_t addr)
87{
88 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
89
90 /* Register writes to GISB bus can take couple hundred nanoseconds
91 * and are done for each packet, save these expensive writes unless
7fc527f9 92 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 93 */
94#ifdef CONFIG_PHYS_ADDR_T_64BIT
95 if (priv->hw_params->flags & GENET_HAS_40BITS)
96 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
97#endif
98}
99
100/* Combined address + length/status setter */
101static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 102 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7
FF		 103{
104 dmadesc_set_length_status(priv, d, val);
105 dmadesc_set_addr(priv, d, addr);
106}
107
108static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
109 void __iomem *d)
110{
111 dma_addr_t addr;
112
113 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
114
115 /* Register writes to GISB bus can take couple hundred nanoseconds
116 * and are done for each packet, save these expensive writes unless
7fc527f9 117 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 118 */
119#ifdef CONFIG_PHYS_ADDR_T_64BIT
120 if (priv->hw_params->flags & GENET_HAS_40BITS)
121 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
122#endif
123 return addr;
124}
125
126#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
127
128#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
129 NETIF_MSG_LINK)
130
131static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
132{
133 if (GENET_IS_V1(priv))
134 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
135 else
136 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
137}
138
139static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
140{
141 if (GENET_IS_V1(priv))
142 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
143 else
144 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
145}
146
147/* These macros are defined to deal with register map change
148 * between GENET1.1 and GENET2. Only those currently being used
149 * by driver are defined.
150 */
151static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
152{
153 if (GENET_IS_V1(priv))
154 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
155 else
156 return __raw_readl(priv->base +
157 priv->hw_params->tbuf_offset + TBUF_CTRL);
158}
159
160static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
161{
162 if (GENET_IS_V1(priv))
163 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
164 else
165 __raw_writel(val, priv->base +
166 priv->hw_params->tbuf_offset + TBUF_CTRL);
167}
168
169static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
170{
171 if (GENET_IS_V1(priv))
172 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
173 else
174 return __raw_readl(priv->base +
175 priv->hw_params->tbuf_offset + TBUF_BP_MC);
176}
177
178static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
179{
180 if (GENET_IS_V1(priv))
181 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
182 else
183 __raw_writel(val, priv->base +
184 priv->hw_params->tbuf_offset + TBUF_BP_MC);
185}
186
187/* RX/TX DMA register accessors */
188enum dma_reg {
189 DMA_RING_CFG = 0,
190 DMA_CTRL,
191 DMA_STATUS,
192 DMA_SCB_BURST_SIZE,
193 DMA_ARB_CTRL,
194 DMA_PRIORITY,
195 DMA_RING_PRIORITY,
196};
197
198static const u8 bcmgenet_dma_regs_v3plus[] = {
199 [DMA_RING_CFG] = 0x00,
200 [DMA_CTRL] = 0x04,
201 [DMA_STATUS] = 0x08,
202 [DMA_SCB_BURST_SIZE] = 0x0C,
203 [DMA_ARB_CTRL] = 0x2C,
204 [DMA_PRIORITY] = 0x30,
205 [DMA_RING_PRIORITY] = 0x38,
206};
207
208static const u8 bcmgenet_dma_regs_v2[] = {
209 [DMA_RING_CFG] = 0x00,
210 [DMA_CTRL] = 0x04,
211 [DMA_STATUS] = 0x08,
212 [DMA_SCB_BURST_SIZE] = 0x0C,
213 [DMA_ARB_CTRL] = 0x30,
214 [DMA_PRIORITY] = 0x34,
215 [DMA_RING_PRIORITY] = 0x3C,
216};
217
218static const u8 bcmgenet_dma_regs_v1[] = {
219 [DMA_CTRL] = 0x00,
220 [DMA_STATUS] = 0x04,
221 [DMA_SCB_BURST_SIZE] = 0x0C,
222 [DMA_ARB_CTRL] = 0x30,
223 [DMA_PRIORITY] = 0x34,
224 [DMA_RING_PRIORITY] = 0x3C,
225};
226
227/* Set at runtime once bcmgenet version is known */
228static const u8 *bcmgenet_dma_regs;
229
230static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
231{
232 return netdev_priv(dev_get_drvdata(dev));
233}
234
235static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 236 enum dma_reg r)
1c1008c7
FF		 237{
238 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
239 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
240}
241
242static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
243 u32 val, enum dma_reg r)
244{
245 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
246 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
247}
248
249static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 250 enum dma_reg r)
1c1008c7
FF		 251{
252 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
253 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
254}
255
256static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
257 u32 val, enum dma_reg r)
258{
259 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
260 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
261}
262
263/* RDMA/TDMA ring registers and accessors
264 * we merge the common fields and just prefix with T/D the registers
265 * having different meaning depending on the direction
266 */
267enum dma_ring_reg {
268 TDMA_READ_PTR = 0,
269 RDMA_WRITE_PTR = TDMA_READ_PTR,
270 TDMA_READ_PTR_HI,
271 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
272 TDMA_CONS_INDEX,
273 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
274 TDMA_PROD_INDEX,
275 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
276 DMA_RING_BUF_SIZE,
277 DMA_START_ADDR,
278 DMA_START_ADDR_HI,
279 DMA_END_ADDR,
280 DMA_END_ADDR_HI,
281 DMA_MBUF_DONE_THRESH,
282 TDMA_FLOW_PERIOD,
283 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
284 TDMA_WRITE_PTR,
285 RDMA_READ_PTR = TDMA_WRITE_PTR,
286 TDMA_WRITE_PTR_HI,
287 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
288};
289
290/* GENET v4 supports 40-bits pointer addressing
291 * for obvious reasons the LO and HI word parts
292 * are contiguous, but this offsets the other
293 * registers.
294 */
295static const u8 genet_dma_ring_regs_v4[] = {
296 [TDMA_READ_PTR] = 0x00,
297 [TDMA_READ_PTR_HI] = 0x04,
298 [TDMA_CONS_INDEX] = 0x08,
299 [TDMA_PROD_INDEX] = 0x0C,
300 [DMA_RING_BUF_SIZE] = 0x10,
301 [DMA_START_ADDR] = 0x14,
302 [DMA_START_ADDR_HI] = 0x18,
303 [DMA_END_ADDR] = 0x1C,
304 [DMA_END_ADDR_HI] = 0x20,
305 [DMA_MBUF_DONE_THRESH] = 0x24,
306 [TDMA_FLOW_PERIOD] = 0x28,
307 [TDMA_WRITE_PTR] = 0x2C,
308 [TDMA_WRITE_PTR_HI] = 0x30,
309};
310
311static const u8 genet_dma_ring_regs_v123[] = {
312 [TDMA_READ_PTR] = 0x00,
313 [TDMA_CONS_INDEX] = 0x04,
314 [TDMA_PROD_INDEX] = 0x08,
315 [DMA_RING_BUF_SIZE] = 0x0C,
316 [DMA_START_ADDR] = 0x10,
317 [DMA_END_ADDR] = 0x14,
318 [DMA_MBUF_DONE_THRESH] = 0x18,
319 [TDMA_FLOW_PERIOD] = 0x1C,
320 [TDMA_WRITE_PTR] = 0x20,
321};
322
323/* Set at runtime once GENET version is known */
324static const u8 *genet_dma_ring_regs;
325
326static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 327 unsigned int ring,
328 enum dma_ring_reg r)
1c1008c7
FF		 329{
330 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
331 (DMA_RING_SIZE * ring) +
332 genet_dma_ring_regs[r]);
333}
334
335static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 336 unsigned int ring, u32 val,
337 enum dma_ring_reg r)
1c1008c7
FF		 338{
339 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
340 (DMA_RING_SIZE * ring) +
341 genet_dma_ring_regs[r]);
342}
343
344static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 345 unsigned int ring,
346 enum dma_ring_reg r)
1c1008c7
FF		 347{
348 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
349 (DMA_RING_SIZE * ring) +
350 genet_dma_ring_regs[r]);
351}
352
353static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 354 unsigned int ring, u32 val,
355 enum dma_ring_reg r)
1c1008c7
FF		 356{
357 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
358 (DMA_RING_SIZE * ring) +
359 genet_dma_ring_regs[r]);
360}
361
362static int bcmgenet_get_settings(struct net_device *dev,
c91b7f66 363 struct ethtool_cmd *cmd)
1c1008c7
FF		 364{
365 struct bcmgenet_priv *priv = netdev_priv(dev);
366
367 if (!netif_running(dev))
368 return -EINVAL;
369
370 if (!priv->phydev)
371 return -ENODEV;
372
373 return phy_ethtool_gset(priv->phydev, cmd);
374}
375
376static int bcmgenet_set_settings(struct net_device *dev,
c91b7f66 377 struct ethtool_cmd *cmd)
1c1008c7
FF		 378{
379 struct bcmgenet_priv *priv = netdev_priv(dev);
380
381 if (!netif_running(dev))
382 return -EINVAL;
383
384 if (!priv->phydev)
385 return -ENODEV;
386
387 return phy_ethtool_sset(priv->phydev, cmd);
388}
389
390static int bcmgenet_set_rx_csum(struct net_device *dev,
391 netdev_features_t wanted)
392{
393 struct bcmgenet_priv *priv = netdev_priv(dev);
394 u32 rbuf_chk_ctrl;
395 bool rx_csum_en;
396
397 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
398
399 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
400
401 /* enable rx checksumming */
402 if (rx_csum_en)
403 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
404 else
405 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
406 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 407
408 /* If UniMAC forwards CRC, we need to skip over it to get
409 * a valid CHK bit to be set in the per-packet status word
410 */
411 if (rx_csum_en && priv->crc_fwd_en)
412 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
413 else
414 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
415
1c1008c7
FF		 416 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
417
418 return 0;
419}
420
421static int bcmgenet_set_tx_csum(struct net_device *dev,
422 netdev_features_t wanted)
423{
424 struct bcmgenet_priv *priv = netdev_priv(dev);
425 bool desc_64b_en;
426 u32 tbuf_ctrl, rbuf_ctrl;
427
428 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
429 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
430
431 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
432
433 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
434 if (desc_64b_en) {
435 tbuf_ctrl |= RBUF_64B_EN;
436 rbuf_ctrl |= RBUF_64B_EN;
437 } else {
438 tbuf_ctrl &= ~RBUF_64B_EN;
439 rbuf_ctrl &= ~RBUF_64B_EN;
440 }
441 priv->desc_64b_en = desc_64b_en;
442
443 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
444 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
445
446 return 0;
447}
448
449static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 450 netdev_features_t features)
1c1008c7
FF		 451{
452 netdev_features_t changed = features ^ dev->features;
453 netdev_features_t wanted = dev->wanted_features;
454 int ret = 0;
455
456 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
457 ret = bcmgenet_set_tx_csum(dev, wanted);
458 if (changed & (NETIF_F_RXCSUM))
459 ret = bcmgenet_set_rx_csum(dev, wanted);
460
461 return ret;
462}
463
464static u32 bcmgenet_get_msglevel(struct net_device *dev)
465{
466 struct bcmgenet_priv *priv = netdev_priv(dev);
467
468 return priv->msg_enable;
469}
470
471static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
472{
473 struct bcmgenet_priv *priv = netdev_priv(dev);
474
475 priv->msg_enable = level;
476}
477
478/* standard ethtool support functions. */
479enum bcmgenet_stat_type {
480 BCMGENET_STAT_NETDEV = -1,
481 BCMGENET_STAT_MIB_RX,
482 BCMGENET_STAT_MIB_TX,
483 BCMGENET_STAT_RUNT,
484 BCMGENET_STAT_MISC,
485};
486
487struct bcmgenet_stats {
488 char stat_string[ETH_GSTRING_LEN];
489 int stat_sizeof;
490 int stat_offset;
491 enum bcmgenet_stat_type type;
492 /* reg offset from UMAC base for misc counters */
493 u16 reg_offset;
494};
495
496#define STAT_NETDEV(m) { \
497 .stat_string = __stringify(m), \
498 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
499 .stat_offset = offsetof(struct net_device_stats, m), \
500 .type = BCMGENET_STAT_NETDEV, \
501}
502
503#define STAT_GENET_MIB(str, m, _type) { \
504 .stat_string = str, \
505 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
506 .stat_offset = offsetof(struct bcmgenet_priv, m), \
507 .type = _type, \
508}
509
510#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
511#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
512#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
513
514#define STAT_GENET_MISC(str, m, offset) { \
515 .stat_string = str, \
516 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
517 .stat_offset = offsetof(struct bcmgenet_priv, m), \
518 .type = BCMGENET_STAT_MISC, \
519 .reg_offset = offset, \
520}
521
522
523/* There is a 0xC gap between the end of RX and beginning of TX stats and then
524 * between the end of TX stats and the beginning of the RX RUNT
525 */
526#define BCMGENET_STAT_OFFSET 0xc
527
528/* Hardware counters must be kept in sync because the order/offset
529 * is important here (order in structure declaration = order in hardware)
530 */
531static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
532 /* general stats */
533 STAT_NETDEV(rx_packets),
534 STAT_NETDEV(tx_packets),
535 STAT_NETDEV(rx_bytes),
536 STAT_NETDEV(tx_bytes),
537 STAT_NETDEV(rx_errors),
538 STAT_NETDEV(tx_errors),
539 STAT_NETDEV(rx_dropped),
540 STAT_NETDEV(tx_dropped),
541 STAT_NETDEV(multicast),
542 /* UniMAC RSV counters */
543 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
544 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
545 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
546 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
547 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
548 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
549 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
550 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
551 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
552 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
553 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
554 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
555 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
556 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
557 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
558 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
559 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
560 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
561 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
562 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
563 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
564 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
565 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
566 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
567 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
568 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
569 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
570 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
571 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
572 /* UniMAC TSV counters */
573 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
574 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
575 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
576 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
577 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
578 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
579 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
580 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
581 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
582 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
583 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
584 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
585 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
586 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
587 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
588 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
589 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
590 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
591 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
592 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
593 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
594 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
595 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
596 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
597 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
598 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
599 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
600 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
601 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
602 /* UniMAC RUNT counters */
603 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
604 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
605 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
606 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
607 /* Misc UniMAC counters */
608 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
609 UMAC_RBUF_OVFL_CNT),
610 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
611 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
612};
613
614#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
615
616static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 617 struct ethtool_drvinfo *info)
1c1008c7
FF		 618{
619 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
620 strlcpy(info->version, "v2.0", sizeof(info->version));
621 info->n_stats = BCMGENET_STATS_LEN;
1c1008c7
FF		 622}
623
624static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
625{
626 switch (string_set) {
627 case ETH_SS_STATS:
628 return BCMGENET_STATS_LEN;
629 default:
630 return -EOPNOTSUPP;
631 }
632}
633
c91b7f66
FF		 634static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
635 u8 *data)
1c1008c7
FF		 636{
637 int i;
638
639 switch (stringset) {
640 case ETH_SS_STATS:
641 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
642 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 643 bcmgenet_gstrings_stats[i].stat_string,
644 ETH_GSTRING_LEN);
1c1008c7
FF		 645 }
646 break;
647 }
648}
649
650static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
651{
652 int i, j = 0;
653
654 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
655 const struct bcmgenet_stats *s;
656 u8 offset = 0;
657 u32 val = 0;
658 char *p;
659
660 s = &bcmgenet_gstrings_stats[i];
661 switch (s->type) {
662 case BCMGENET_STAT_NETDEV:
663 continue;
664 case BCMGENET_STAT_MIB_RX:
665 case BCMGENET_STAT_MIB_TX:
666 case BCMGENET_STAT_RUNT:
667 if (s->type != BCMGENET_STAT_MIB_RX)
668 offset = BCMGENET_STAT_OFFSET;
c91b7f66
FF		 669 val = bcmgenet_umac_readl(priv,
670 UMAC_MIB_START + j + offset);
1c1008c7
FF		 671 break;
672 case BCMGENET_STAT_MISC:
673 val = bcmgenet_umac_readl(priv, s->reg_offset);
674 /* clear if overflowed */
675 if (val == ~0)
676 bcmgenet_umac_writel(priv, 0, s->reg_offset);
677 break;
678 }
679
680 j += s->stat_sizeof;
681 p = (char *)priv + s->stat_offset;
682 *(u32 *)p = val;
683 }
684}
685
686static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 687 struct ethtool_stats *stats,
688 u64 *data)
1c1008c7
FF		 689{
690 struct bcmgenet_priv *priv = netdev_priv(dev);
691 int i;
692
693 if (netif_running(dev))
694 bcmgenet_update_mib_counters(priv);
695
696 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
697 const struct bcmgenet_stats *s;
698 char *p;
699
700 s = &bcmgenet_gstrings_stats[i];
701 if (s->type == BCMGENET_STAT_NETDEV)
702 p = (char *)&dev->stats;
703 else
704 p = (char *)priv;
705 p += s->stat_offset;
706 data[i] = *(u32 *)p;
707 }
708}
709
710/* standard ethtool support functions. */
711static struct ethtool_ops bcmgenet_ethtool_ops = {
712 .get_strings = bcmgenet_get_strings,
713 .get_sset_count = bcmgenet_get_sset_count,
714 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
715 .get_settings = bcmgenet_get_settings,
716 .set_settings = bcmgenet_set_settings,
717 .get_drvinfo = bcmgenet_get_drvinfo,
718 .get_link = ethtool_op_get_link,
719 .get_msglevel = bcmgenet_get_msglevel,
720 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 721 .get_wol = bcmgenet_get_wol,
722 .set_wol = bcmgenet_set_wol,
1c1008c7
FF		 723};
724
725/* Power down the unimac, based on mode. */
726static void bcmgenet_power_down(struct bcmgenet_priv *priv,
727 enum bcmgenet_power_mode mode)
728{
729 u32 reg;
730
731 switch (mode) {
732 case GENET_POWER_CABLE_SENSE:
80d8e96d 733 phy_detach(priv->phydev);
1c1008c7
FF		 734 break;
735
c3ae64ae
FF		 736 case GENET_POWER_WOL_MAGIC:
737 bcmgenet_wol_power_down_cfg(priv, mode);
738 break;
739
1c1008c7
FF		 740 case GENET_POWER_PASSIVE:
741 /* Power down LED */
1c1008c7
FF		 742 if (priv->hw_params->flags & GENET_HAS_EXT) {
743 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
744 reg |= (EXT_PWR_DOWN_PHY |
745 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
746 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
747 }
748 break;
749 default:
750 break;
751 }
752}
753
754static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 755 enum bcmgenet_power_mode mode)
1c1008c7
FF		 756{
757 u32 reg;
758
759 if (!(priv->hw_params->flags & GENET_HAS_EXT))
760 return;
761
762 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
763
764 switch (mode) {
765 case GENET_POWER_PASSIVE:
766 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
767 EXT_PWR_DOWN_BIAS);
768 /* fallthrough */
769 case GENET_POWER_CABLE_SENSE:
770 /* enable APD */
771 reg |= EXT_PWR_DN_EN_LD;
772 break;
c3ae64ae
FF		 773 case GENET_POWER_WOL_MAGIC:
774 bcmgenet_wol_power_up_cfg(priv, mode);
775 return;
1c1008c7
FF		 776 default:
777 break;
778 }
779
780 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
cc013fb4
FF		 781
782 if (mode == GENET_POWER_PASSIVE)
783 bcmgenet_mii_reset(priv->dev);
1c1008c7
FF		 784}
785
786/* ioctl handle special commands that are not present in ethtool. */
787static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
788{
789 struct bcmgenet_priv *priv = netdev_priv(dev);
790 int val = 0;
791
792 if (!netif_running(dev))
793 return -EINVAL;
794
795 switch (cmd) {
796 case SIOCGMIIPHY:
797 case SIOCGMIIREG:
798 case SIOCSMIIREG:
799 if (!priv->phydev)
800 val = -ENODEV;
801 else
802 val = phy_mii_ioctl(priv->phydev, rq, cmd);
803 break;
804
805 default:
806 val = -EINVAL;
807 break;
808 }
809
810 return val;
811}
812
813static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
814 struct bcmgenet_tx_ring *ring)
815{
816 struct enet_cb *tx_cb_ptr;
817
818 tx_cb_ptr = ring->cbs;
819 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
820 tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE;
821 /* Advancing local write pointer */
822 if (ring->write_ptr == ring->end_ptr)
823 ring->write_ptr = ring->cb_ptr;
824 else
825 ring->write_ptr++;
826
827 return tx_cb_ptr;
828}
829
830/* Simple helper to free a control block's resources */
831static void bcmgenet_free_cb(struct enet_cb *cb)
832{
833 dev_kfree_skb_any(cb->skb);
834 cb->skb = NULL;
835 dma_unmap_addr_set(cb, dma_addr, 0);
836}
837
838static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
839 struct bcmgenet_tx_ring *ring)
840{
841 bcmgenet_intrl2_0_writel(priv,
c91b7f66
FF		 842 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
843 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 844}
845
846static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
847 struct bcmgenet_tx_ring *ring)
848{
849 bcmgenet_intrl2_0_writel(priv,
c91b7f66
FF		 850 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
851 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 852}
853
854static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
c91b7f66 855 struct bcmgenet_tx_ring *ring)
1c1008c7 856{
c91b7f66
FF		 857 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
858 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 859 priv->int1_mask &= ~(1 << ring->index);
860}
861
862static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
863 struct bcmgenet_tx_ring *ring)
864{
c91b7f66
FF		 865 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
866 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 867 priv->int1_mask |= (1 << ring->index);
868}
869
870/* Unlocked version of the reclaim routine */
871static void __bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 872 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 873{
874 struct bcmgenet_priv *priv = netdev_priv(dev);
875 int last_tx_cn, last_c_index, num_tx_bds;
876 struct enet_cb *tx_cb_ptr;
b2cde2cc 877 struct netdev_queue *txq;
1c1008c7
FF		 878 unsigned int c_index;
879
7fc527f9 880 /* Compute how many buffers are transmitted since last xmit call */
1c1008c7 881 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
b2cde2cc 882 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 883
884 last_c_index = ring->c_index;
885 num_tx_bds = ring->size;
886
887 c_index &= (num_tx_bds - 1);
888
889 if (c_index >= last_c_index)
890 last_tx_cn = c_index - last_c_index;
891 else
892 last_tx_cn = num_tx_bds - last_c_index + c_index;
893
894 netif_dbg(priv, tx_done, dev,
c91b7f66
FF		 895 "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
896 __func__, ring->index,
897 c_index, last_tx_cn, last_c_index);
1c1008c7
FF		 898
899 /* Reclaim transmitted buffers */
900 while (last_tx_cn-- > 0) {
901 tx_cb_ptr = ring->cbs + last_c_index;
902 if (tx_cb_ptr->skb) {
903 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
904 dma_unmap_single(&dev->dev,
c91b7f66
FF		 905 dma_unmap_addr(tx_cb_ptr, dma_addr),
906 tx_cb_ptr->skb->len,
907 DMA_TO_DEVICE);
1c1008c7
FF		 908 bcmgenet_free_cb(tx_cb_ptr);
909 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
910 dev->stats.tx_bytes +=
911 dma_unmap_len(tx_cb_ptr, dma_len);
912 dma_unmap_page(&dev->dev,
c91b7f66
FF		 913 dma_unmap_addr(tx_cb_ptr, dma_addr),
914 dma_unmap_len(tx_cb_ptr, dma_len),
915 DMA_TO_DEVICE);
1c1008c7
FF		 916 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
917 }
918 dev->stats.tx_packets++;
919 ring->free_bds += 1;
920
921 last_c_index++;
922 last_c_index &= (num_tx_bds - 1);
923 }
924
925 if (ring->free_bds > (MAX_SKB_FRAGS + 1))
926 ring->int_disable(priv, ring);
927
b2cde2cc
FF		 928 if (netif_tx_queue_stopped(txq))
929 netif_tx_wake_queue(txq);
1c1008c7
FF		 930
931 ring->c_index = c_index;
932}
933
934static void bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 935 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 936{
937 unsigned long flags;
938
939 spin_lock_irqsave(&ring->lock, flags);
940 __bcmgenet_tx_reclaim(dev, ring);
941 spin_unlock_irqrestore(&ring->lock, flags);
942}
943
944static void bcmgenet_tx_reclaim_all(struct net_device *dev)
945{
946 struct bcmgenet_priv *priv = netdev_priv(dev);
947 int i;
948
949 if (netif_is_multiqueue(dev)) {
950 for (i = 0; i < priv->hw_params->tx_queues; i++)
951 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
952 }
953
954 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
955}
956
957/* Transmits a single SKB (either head of a fragment or a single SKB)
958 * caller must hold priv->lock
959 */
960static int bcmgenet_xmit_single(struct net_device *dev,
961 struct sk_buff *skb,
962 u16 dma_desc_flags,
963 struct bcmgenet_tx_ring *ring)
964{
965 struct bcmgenet_priv *priv = netdev_priv(dev);
966 struct device *kdev = &priv->pdev->dev;
967 struct enet_cb *tx_cb_ptr;
968 unsigned int skb_len;
969 dma_addr_t mapping;
970 u32 length_status;
971 int ret;
972
973 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
974
975 if (unlikely(!tx_cb_ptr))
976 BUG();
977
978 tx_cb_ptr->skb = skb;
979
980 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
981
982 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
983 ret = dma_mapping_error(kdev, mapping);
984 if (ret) {
985 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
986 dev_kfree_skb(skb);
987 return ret;
988 }
989
990 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
991 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
992 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
993 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
994 DMA_TX_APPEND_CRC;
995
996 if (skb->ip_summed == CHECKSUM_PARTIAL)
997 length_status |= DMA_TX_DO_CSUM;
998
999 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1000
1001 /* Decrement total BD count and advance our write pointer */
1002 ring->free_bds -= 1;
1003 ring->prod_index += 1;
1004 ring->prod_index &= DMA_P_INDEX_MASK;
1005
1006 return 0;
1007}
1008
7fc527f9 1009/* Transmit a SKB fragment */
1c1008c7 1010static int bcmgenet_xmit_frag(struct net_device *dev,
c91b7f66
FF		 1011 skb_frag_t *frag,
1012 u16 dma_desc_flags,
1013 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1014{
1015 struct bcmgenet_priv *priv = netdev_priv(dev);
1016 struct device *kdev = &priv->pdev->dev;
1017 struct enet_cb *tx_cb_ptr;
1018 dma_addr_t mapping;
1019 int ret;
1020
1021 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1022
1023 if (unlikely(!tx_cb_ptr))
1024 BUG();
1025 tx_cb_ptr->skb = NULL;
1026
1027 mapping = skb_frag_dma_map(kdev, frag, 0,
c91b7f66 1028 skb_frag_size(frag), DMA_TO_DEVICE);
1c1008c7
FF		 1029 ret = dma_mapping_error(kdev, mapping);
1030 if (ret) {
1031 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
c91b7f66 1032 __func__);
1c1008c7
FF		 1033 return ret;
1034 }
1035
1036 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1037 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1038
1039 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
c91b7f66
FF		 1040 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1041 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1c1008c7
FF		 1042
1043
1044 ring->free_bds -= 1;
1045 ring->prod_index += 1;
1046 ring->prod_index &= DMA_P_INDEX_MASK;
1047
1048 return 0;
1049}
1050
1051/* Reallocate the SKB to put enough headroom in front of it and insert
1052 * the transmit checksum offsets in the descriptors
1053 */
1054static int bcmgenet_put_tx_csum(struct net_device *dev, struct sk_buff *skb)
1055{
1056 struct status_64 *status = NULL;
1057 struct sk_buff *new_skb;
1058 u16 offset;
1059 u8 ip_proto;
1060 u16 ip_ver;
1061 u32 tx_csum_info;
1062
1063 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1064 /* If 64 byte status block enabled, must make sure skb has
1065 * enough headroom for us to insert 64B status block.
1066 */
1067 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1068 dev_kfree_skb(skb);
1069 if (!new_skb) {
1070 dev->stats.tx_errors++;
1071 dev->stats.tx_dropped++;
1072 return -ENOMEM;
1073 }
1074 skb = new_skb;
1075 }
1076
1077 skb_push(skb, sizeof(*status));
1078 status = (struct status_64 *)skb->data;
1079
1080 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1081 ip_ver = htons(skb->protocol);
1082 switch (ip_ver) {
1083 case ETH_P_IP:
1084 ip_proto = ip_hdr(skb)->protocol;
1085 break;
1086 case ETH_P_IPV6:
1087 ip_proto = ipv6_hdr(skb)->nexthdr;
1088 break;
1089 default:
1090 return 0;
1091 }
1092
1093 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1094 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1095 (offset + skb->csum_offset);
1096
1097 /* Set the length valid bit for TCP and UDP and just set
1098 * the special UDP flag for IPv4, else just set to 0.
1099 */
1100 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1101 tx_csum_info |= STATUS_TX_CSUM_LV;
1102 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1103 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
8900ea57 1104 } else {
1c1008c7 1105 tx_csum_info = 0;
8900ea57 1106 }
1c1008c7
FF		 1107
1108 status->tx_csum_info = tx_csum_info;
1109 }
1110
1111 return 0;
1112}
1113
1114static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1115{
1116 struct bcmgenet_priv *priv = netdev_priv(dev);
1117 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1118 struct netdev_queue *txq;
1c1008c7
FF		 1119 unsigned long flags = 0;
1120 int nr_frags, index;
1121 u16 dma_desc_flags;
1122 int ret;
1123 int i;
1124
1125 index = skb_get_queue_mapping(skb);
1126 /* Mapping strategy:
1127 * queue_mapping = 0, unclassified, packet xmited through ring16
1128 * queue_mapping = 1, goes to ring 0. (highest priority queue
1129 * queue_mapping = 2, goes to ring 1.
1130 * queue_mapping = 3, goes to ring 2.
1131 * queue_mapping = 4, goes to ring 3.
1132 */
1133 if (index == 0)
1134 index = DESC_INDEX;
1135 else
1136 index -= 1;
1137
1c1008c7
FF		 1138 nr_frags = skb_shinfo(skb)->nr_frags;
1139 ring = &priv->tx_rings[index];
b2cde2cc 1140 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 1141
1142 spin_lock_irqsave(&ring->lock, flags);
1143 if (ring->free_bds <= nr_frags + 1) {
b2cde2cc 1144 netif_tx_stop_queue(txq);
1c1008c7 1145 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
c91b7f66 1146 __func__, index, ring->queue);
1c1008c7
FF		 1147 ret = NETDEV_TX_BUSY;
1148 goto out;
1149 }
1150
474ea9ca
FF		 1151 if (skb_padto(skb, ETH_ZLEN)) {
1152 ret = NETDEV_TX_OK;
1153 goto out;
1154 }
1155
1c1008c7
FF		 1156 /* set the SKB transmit checksum */
1157 if (priv->desc_64b_en) {
1158 ret = bcmgenet_put_tx_csum(dev, skb);
1159 if (ret) {
1160 ret = NETDEV_TX_OK;
1161 goto out;
1162 }
1163 }
1164
1165 dma_desc_flags = DMA_SOP;
1166 if (nr_frags == 0)
1167 dma_desc_flags |= DMA_EOP;
1168
1169 /* Transmit single SKB or head of fragment list */
1170 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1171 if (ret) {
1172 ret = NETDEV_TX_OK;
1173 goto out;
1174 }
1175
1176 /* xmit fragment */
1177 for (i = 0; i < nr_frags; i++) {
1178 ret = bcmgenet_xmit_frag(dev,
c91b7f66
FF		 1179 &skb_shinfo(skb)->frags[i],
1180 (i == nr_frags - 1) ? DMA_EOP : 0,
1181 ring);
1c1008c7
FF		 1182 if (ret) {
1183 ret = NETDEV_TX_OK;
1184 goto out;
1185 }
1186 }
1187
d03825fb
FF		 1188 skb_tx_timestamp(skb);
1189
1c1008c7
FF		 1190 /* we kept a software copy of how much we should advance the TDMA
1191 * producer index, now write it down to the hardware
1192 */
1193 bcmgenet_tdma_ring_writel(priv, ring->index,
c91b7f66 1194 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7
FF		 1195
1196 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) {
b2cde2cc 1197 netif_tx_stop_queue(txq);
1c1008c7
FF		 1198 ring->int_enable(priv, ring);
1199 }
1200
1201out:
1202 spin_unlock_irqrestore(&ring->lock, flags);
1203
1204 return ret;
1205}
1206
1207
c91b7f66 1208static int bcmgenet_rx_refill(struct bcmgenet_priv *priv, struct enet_cb *cb)
1c1008c7
FF		 1209{
1210 struct device *kdev = &priv->pdev->dev;
1211 struct sk_buff *skb;
1212 dma_addr_t mapping;
1213 int ret;
1214
c91b7f66 1215 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1c1008c7
FF		 1216 if (!skb)
1217 return -ENOMEM;
1218
1219 /* a caller did not release this control block */
1220 WARN_ON(cb->skb != NULL);
1221 cb->skb = skb;
1222 mapping = dma_map_single(kdev, skb->data,
c91b7f66 1223 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1224 ret = dma_mapping_error(kdev, mapping);
1225 if (ret) {
1226 bcmgenet_free_cb(cb);
1227 netif_err(priv, rx_err, priv->dev,
c91b7f66 1228 "%s DMA map failed\n", __func__);
1c1008c7
FF		 1229 return ret;
1230 }
1231
1232 dma_unmap_addr_set(cb, dma_addr, mapping);
1233 /* assign packet, prepare descriptor, and advance pointer */
1234
1235 dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1236
1237 /* turn on the newly assigned BD for DMA to use */
1238 priv->rx_bd_assign_index++;
1239 priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1240
1241 priv->rx_bd_assign_ptr = priv->rx_bds +
1242 (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1243
1244 return 0;
1245}
1246
1247/* bcmgenet_desc_rx - descriptor based rx process.
1248 * this could be called from bottom half, or from NAPI polling method.
1249 */
1250static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1251 unsigned int budget)
1252{
1253 struct net_device *dev = priv->dev;
1254 struct enet_cb *cb;
1255 struct sk_buff *skb;
1256 u32 dma_length_status;
1257 unsigned long dma_flag;
1258 int len, err;
1259 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1260 unsigned int p_index;
1261 unsigned int chksum_ok = 0;
1262
c91b7f66 1263 p_index = bcmgenet_rdma_ring_readl(priv, DESC_INDEX, RDMA_PROD_INDEX);
1c1008c7
FF		 1264 p_index &= DMA_P_INDEX_MASK;
1265
1266 if (p_index < priv->rx_c_index)
1267 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1268 priv->rx_c_index + p_index;
1269 else
1270 rxpkttoprocess = p_index - priv->rx_c_index;
1271
1272 netif_dbg(priv, rx_status, dev,
c91b7f66 1273 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1274
1275 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1276 (rxpktprocessed < budget)) {
b629be5c
FF		 1277 cb = &priv->rx_cbs[priv->rx_read_ptr];
1278 skb = cb->skb;
1279
1280 rxpktprocessed++;
1281
1282 priv->rx_read_ptr++;
1283 priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1284
1285 /* We do not have a backing SKB, so we do not have a
1286 * corresponding DMA mapping for this incoming packet since
1287 * bcmgenet_rx_refill always either has both skb and mapping or
1288 * none.
1289 */
1290 if (unlikely(!skb)) {
1291 dev->stats.rx_dropped++;
1292 dev->stats.rx_errors++;
1293 goto refill;
1294 }
1295
1c1008c7
FF		 1296 /* Unmap the packet contents such that we can use the
1297 * RSV from the 64 bytes descriptor when enabled and save
1298 * a 32-bits register read
1299 */
1c1008c7 1300 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
c91b7f66 1301 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1302
1303 if (!priv->desc_64b_en) {
c91b7f66
FF		 1304 dma_length_status =
1305 dmadesc_get_length_status(priv,
1306 priv->rx_bds +
1307 (priv->rx_read_ptr *
1308 DMA_DESC_SIZE));
1c1008c7
FF		 1309 } else {
1310 struct status_64 *status;
164d4f20 1311
1c1008c7
FF		 1312 status = (struct status_64 *)skb->data;
1313 dma_length_status = status->length_status;
1314 }
1315
1316 /* DMA flags and length are still valid no matter how
1317 * we got the Receive Status Vector (64B RSB or register)
1318 */
1319 dma_flag = dma_length_status & 0xffff;
1320 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1321
1322 netif_dbg(priv, rx_status, dev,
c91b7f66
FF		 1323 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1324 __func__, p_index, priv->rx_c_index,
1325 priv->rx_read_ptr, dma_length_status);
1c1008c7 1326
1c1008c7
FF		 1327 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1328 netif_err(priv, rx_status, dev,
c91b7f66 1329 "dropping fragmented packet!\n");
1c1008c7
FF		 1330 dev->stats.rx_dropped++;
1331 dev->stats.rx_errors++;
1332 dev_kfree_skb_any(cb->skb);
1333 cb->skb = NULL;
1334 goto refill;
1335 }
1336 /* report errors */
1337 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1338 DMA_RX_OV |
1339 DMA_RX_NO |
1340 DMA_RX_LG |
1341 DMA_RX_RXER))) {
1342 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1343 (unsigned int)dma_flag);
1c1008c7
FF		 1344 if (dma_flag & DMA_RX_CRC_ERROR)
1345 dev->stats.rx_crc_errors++;
1346 if (dma_flag & DMA_RX_OV)
1347 dev->stats.rx_over_errors++;
1348 if (dma_flag & DMA_RX_NO)
1349 dev->stats.rx_frame_errors++;
1350 if (dma_flag & DMA_RX_LG)
1351 dev->stats.rx_length_errors++;
1352 dev->stats.rx_dropped++;
1353 dev->stats.rx_errors++;
1354
1355 /* discard the packet and advance consumer index.*/
1356 dev_kfree_skb_any(cb->skb);
1357 cb->skb = NULL;
1358 goto refill;
1359 } /* error packet */
1360
1361 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
c91b7f66 1362 priv->desc_rxchk_en;
1c1008c7
FF		 1363
1364 skb_put(skb, len);
1365 if (priv->desc_64b_en) {
1366 skb_pull(skb, 64);
1367 len -= 64;
1368 }
1369
1370 if (likely(chksum_ok))
1371 skb->ip_summed = CHECKSUM_UNNECESSARY;
1372
1373 /* remove hardware 2bytes added for IP alignment */
1374 skb_pull(skb, 2);
1375 len -= 2;
1376
1377 if (priv->crc_fwd_en) {
1378 skb_trim(skb, len - ETH_FCS_LEN);
1379 len -= ETH_FCS_LEN;
1380 }
1381
1382 /*Finish setting up the received SKB and send it to the kernel*/
1383 skb->protocol = eth_type_trans(skb, priv->dev);
1384 dev->stats.rx_packets++;
1385 dev->stats.rx_bytes += len;
1386 if (dma_flag & DMA_RX_MULT)
1387 dev->stats.multicast++;
1388
1389 /* Notify kernel */
1390 napi_gro_receive(&priv->napi, skb);
1391 cb->skb = NULL;
1392 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1393
1394 /* refill RX path on the current control block */
1395refill:
1396 err = bcmgenet_rx_refill(priv, cb);
1397 if (err)
1398 netif_err(priv, rx_err, dev, "Rx refill failed\n");
1399 }
1400
1401 return rxpktprocessed;
1402}
1403
1404/* Assign skb to RX DMA descriptor. */
1405static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1406{
1407 struct enet_cb *cb;
1408 int ret = 0;
1409 int i;
1410
1411 netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1412
1413 /* loop here for each buffer needing assign */
1414 for (i = 0; i < priv->num_rx_bds; i++) {
1415 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1416 if (cb->skb)
1417 continue;
1418
1c1008c7
FF		 1419 ret = bcmgenet_rx_refill(priv, cb);
1420 if (ret)
1421 break;
1c1008c7
FF		 1422 }
1423
1424 return ret;
1425}
1426
1427static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1428{
1429 struct enet_cb *cb;
1430 int i;
1431
1432 for (i = 0; i < priv->num_rx_bds; i++) {
1433 cb = &priv->rx_cbs[i];
1434
1435 if (dma_unmap_addr(cb, dma_addr)) {
1436 dma_unmap_single(&priv->dev->dev,
c91b7f66
FF		 1437 dma_unmap_addr(cb, dma_addr),
1438 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1439 dma_unmap_addr_set(cb, dma_addr, 0);
1440 }
1441
1442 if (cb->skb)
1443 bcmgenet_free_cb(cb);
1444 }
1445}
1446
c91b7f66 1447static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1448{
1449 u32 reg;
1450
1451 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1452 if (enable)
1453 reg |= mask;
1454 else
1455 reg &= ~mask;
1456 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1457
1458 /* UniMAC stops on a packet boundary, wait for a full-size packet
1459 * to be processed
1460 */
1461 if (enable == 0)
1462 usleep_range(1000, 2000);
1463}
1464
1c1008c7
FF		 1465static int reset_umac(struct bcmgenet_priv *priv)
1466{
1467 struct device *kdev = &priv->pdev->dev;
1468 unsigned int timeout = 0;
1469 u32 reg;
1470
1471 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1472 bcmgenet_rbuf_ctrl_set(priv, 0);
1473 udelay(10);
1474
1475 /* disable MAC while updating its registers */
1476 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1477
1478 /* issue soft reset, wait for it to complete */
1479 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1480 while (timeout++ < 1000) {
1481 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1482 if (!(reg & CMD_SW_RESET))
1483 return 0;
1484
1485 udelay(1);
1486 }
1487
1488 if (timeout == 1000) {
1489 dev_err(kdev,
7fc527f9 1490 "timeout waiting for MAC to come out of reset\n");
1c1008c7
FF		 1491 return -ETIMEDOUT;
1492 }
1493
1494 return 0;
1495}
1496
909ff5ef
FF		 1497static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1498{
1499 /* Mask all interrupts.*/
1500 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1501 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1502 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1503 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1504 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1505 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1506}
1507
1c1008c7
FF		 1508static int init_umac(struct bcmgenet_priv *priv)
1509{
1510 struct device *kdev = &priv->pdev->dev;
1511 int ret;
1512 u32 reg, cpu_mask_clear;
1513
1514 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1515
1516 ret = reset_umac(priv);
1517 if (ret)
1518 return ret;
1519
1520 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1521 /* clear tx/rx counter */
1522 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1523 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1524 UMAC_MIB_CTRL);
1c1008c7
FF		 1525 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1526
1527 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1528
1529 /* init rx registers, enable ip header optimization */
1530 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1531 reg |= RBUF_ALIGN_2B;
1532 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1533
1534 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1535 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1536
909ff5ef 1537 bcmgenet_intr_disable(priv);
1c1008c7
FF		 1538
1539 cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE;
1540
1541 dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1542
7fc527f9 1543 /* Monitor cable plug/unplugged event for internal PHY */
8900ea57 1544 if (phy_is_internal(priv->phydev)) {
1c1008c7 1545 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1546 } else if (priv->ext_phy) {
1c1008c7 1547 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1548 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 1549 reg = bcmgenet_bp_mc_get(priv);
1550 reg |= BIT(priv->hw_params->bp_in_en_shift);
1551
1552 /* bp_mask: back pressure mask */
1553 if (netif_is_multiqueue(priv->dev))
1554 reg |= priv->hw_params->bp_in_mask;
1555 else
1556 reg &= ~priv->hw_params->bp_in_mask;
1557 bcmgenet_bp_mc_set(priv, reg);
1558 }
1559
1560 /* Enable MDIO interrupts on GENET v3+ */
1561 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1562 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1563
c91b7f66 1564 bcmgenet_intrl2_0_writel(priv, cpu_mask_clear, INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1565
1566 /* Enable rx/tx engine.*/
1567 dev_dbg(kdev, "done init umac\n");
1568
1569 return 0;
1570}
1571
1572/* Initialize all house-keeping variables for a TX ring, along
1573 * with corresponding hardware registers
1574 */
1575static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1576 unsigned int index, unsigned int size,
1577 unsigned int write_ptr, unsigned int end_ptr)
1578{
1579 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1580 u32 words_per_bd = WORDS_PER_BD(priv);
1581 u32 flow_period_val = 0;
1582 unsigned int first_bd;
1583
1584 spin_lock_init(&ring->lock);
1585 ring->index = index;
1586 if (index == DESC_INDEX) {
1587 ring->queue = 0;
1588 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1589 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1590 } else {
1591 ring->queue = index + 1;
1592 ring->int_enable = bcmgenet_tx_ring_int_enable;
1593 ring->int_disable = bcmgenet_tx_ring_int_disable;
1594 }
1595 ring->cbs = priv->tx_cbs + write_ptr;
1596 ring->size = size;
1597 ring->c_index = 0;
1598 ring->free_bds = size;
1599 ring->write_ptr = write_ptr;
1600 ring->cb_ptr = write_ptr;
1601 ring->end_ptr = end_ptr - 1;
1602 ring->prod_index = 0;
1603
1604 /* Set flow period for ring != 16 */
1605 if (index != DESC_INDEX)
1606 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1607
1608 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1609 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1610 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1611 /* Disable rate control for now */
1612 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 1613 TDMA_FLOW_PERIOD);
1c1008c7
FF		 1614 /* Unclassified traffic goes to ring 16 */
1615 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 1616 ((size << DMA_RING_SIZE_SHIFT) |
1617 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7
FF		 1618
1619 first_bd = write_ptr;
1620
1621 /* Set start and end address, read and write pointers */
1622 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
c91b7f66 1623 DMA_START_ADDR);
1c1008c7 1624 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
c91b7f66 1625 TDMA_READ_PTR);
1c1008c7 1626 bcmgenet_tdma_ring_writel(priv, index, first_bd,
c91b7f66 1627 TDMA_WRITE_PTR);
1c1008c7 1628 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 1629 DMA_END_ADDR);
1c1008c7
FF		 1630}
1631
1632/* Initialize a RDMA ring */
1633static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
c91b7f66 1634 unsigned int index, unsigned int size)
1c1008c7
FF		 1635{
1636 u32 words_per_bd = WORDS_PER_BD(priv);
1637 int ret;
1638
1639 priv->num_rx_bds = TOTAL_DESC;
1640 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1641 priv->rx_bd_assign_ptr = priv->rx_bds;
1642 priv->rx_bd_assign_index = 0;
1643 priv->rx_c_index = 0;
1644 priv->rx_read_ptr = 0;
c489be08
FF		 1645 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
1646 GFP_KERNEL);
1c1008c7
FF		 1647 if (!priv->rx_cbs)
1648 return -ENOMEM;
1649
1650 ret = bcmgenet_alloc_rx_buffers(priv);
1651 if (ret) {
1652 kfree(priv->rx_cbs);
1653 return ret;
1654 }
1655
1656 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1657 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1658 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1659 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1660 ((size << DMA_RING_SIZE_SHIFT) |
1661 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7
FF		 1662 bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1663 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66 1664 words_per_bd * size - 1, DMA_END_ADDR);
1c1008c7 1665 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1666 (DMA_FC_THRESH_LO <<
1667 DMA_XOFF_THRESHOLD_SHIFT) |
1668 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1c1008c7
FF		 1669 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
1670
1671 return ret;
1672}
1673
1674/* init multi xmit queues, only available for GENET2+
1675 * the queue is partitioned as follows:
1676 *
1677 * queue 0 - 3 is priority based, each one has 32 descriptors,
1678 * with queue 0 being the highest priority queue.
1679 *
1680 * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1681 * descriptors: 256 - (number of tx queues * bds per queues) = 128
1682 * descriptors.
1683 *
1684 * The transmit control block pool is then partitioned as following:
1685 * - tx_cbs[0...127] are for queue 16
1686 * - tx_ring_cbs[0] points to tx_cbs[128..159]
1687 * - tx_ring_cbs[1] points to tx_cbs[160..191]
1688 * - tx_ring_cbs[2] points to tx_cbs[192..223]
1689 * - tx_ring_cbs[3] points to tx_cbs[224..255]
1690 */
1691static void bcmgenet_init_multiq(struct net_device *dev)
1692{
1693 struct bcmgenet_priv *priv = netdev_priv(dev);
1694 unsigned int i, dma_enable;
1695 u32 reg, dma_ctrl, ring_cfg = 0, dma_priority = 0;
1696
1697 if (!netif_is_multiqueue(dev)) {
1698 netdev_warn(dev, "called with non multi queue aware HW\n");
1699 return;
1700 }
1701
1702 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1703 dma_enable = dma_ctrl & DMA_EN;
1704 dma_ctrl &= ~DMA_EN;
1705 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1706
1707 /* Enable strict priority arbiter mode */
1708 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1709
1710 for (i = 0; i < priv->hw_params->tx_queues; i++) {
1711 /* first 64 tx_cbs are reserved for default tx queue
1712 * (ring 16)
1713 */
1714 bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt,
c91b7f66
FF		 1715 i * priv->hw_params->bds_cnt,
1716 (i + 1) * priv->hw_params->bds_cnt);
1c1008c7 1717
7fc527f9 1718 /* Configure ring as descriptor ring and setup priority */
1c1008c7
FF		 1719 ring_cfg |= 1 << i;
1720 dma_priority |= ((GENET_Q0_PRIORITY + i) <<
1721 (GENET_MAX_MQ_CNT + 1) * i);
1722 dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT);
1723 }
1724
1725 /* Enable rings */
1726 reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG);
1727 reg |= ring_cfg;
1728 bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG);
1729
1730 /* Use configured rings priority and set ring #16 priority */
1731 reg = bcmgenet_tdma_readl(priv, DMA_RING_PRIORITY);
1732 reg |= ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 20);
1733 reg |= dma_priority;
1734 bcmgenet_tdma_writel(priv, reg, DMA_PRIORITY);
1735
1736 /* Configure ring as descriptor ring and re-enable DMA if enabled */
1737 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1738 reg |= dma_ctrl;
1739 if (dma_enable)
1740 reg |= DMA_EN;
1741 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1742}
1743
1744static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1745{
1746 int i;
1747
1748 /* disable DMA */
1749 bcmgenet_rdma_writel(priv, 0, DMA_CTRL);
1750 bcmgenet_tdma_writel(priv, 0, DMA_CTRL);
1751
1752 for (i = 0; i < priv->num_tx_bds; i++) {
1753 if (priv->tx_cbs[i].skb != NULL) {
1754 dev_kfree_skb(priv->tx_cbs[i].skb);
1755 priv->tx_cbs[i].skb = NULL;
1756 }
1757 }
1758
1759 bcmgenet_free_rx_buffers(priv);
1760 kfree(priv->rx_cbs);
1761 kfree(priv->tx_cbs);
1762}
1763
1764/* init_edma: Initialize DMA control register */
1765static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1766{
1767 int ret;
1768
1769 netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
1770
1771 /* by default, enable ring 16 (descriptor based) */
1772 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1773 if (ret) {
1774 netdev_err(priv->dev, "failed to initialize RX ring\n");
1775 return ret;
1776 }
1777
1778 /* init rDma */
1779 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1780
1781 /* Init tDma */
1782 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1783
7fc527f9 1784 /* Initialize common TX ring structures */
1c1008c7
FF		 1785 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
1786 priv->num_tx_bds = TOTAL_DESC;
c489be08 1787 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 1788 GFP_KERNEL);
1c1008c7
FF		 1789 if (!priv->tx_cbs) {
1790 bcmgenet_fini_dma(priv);
1791 return -ENOMEM;
1792 }
1793
1794 /* initialize multi xmit queue */
1795 bcmgenet_init_multiq(priv->dev);
1796
1797 /* initialize special ring 16 */
1798 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT,
c91b7f66
FF		 1799 priv->hw_params->tx_queues *
1800 priv->hw_params->bds_cnt,
1801 TOTAL_DESC);
1c1008c7
FF		 1802
1803 return 0;
1804}
1805
1806/* NAPI polling method*/
1807static int bcmgenet_poll(struct napi_struct *napi, int budget)
1808{
1809 struct bcmgenet_priv *priv = container_of(napi,
1810 struct bcmgenet_priv, napi);
1811 unsigned int work_done;
1812
1813 /* tx reclaim */
1814 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1815
1816 work_done = bcmgenet_desc_rx(priv, budget);
1817
1818 /* Advancing our consumer index*/
1819 priv->rx_c_index += work_done;
1820 priv->rx_c_index &= DMA_C_INDEX_MASK;
1821 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
c91b7f66 1822 priv->rx_c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 1823 if (work_done < budget) {
1824 napi_complete(napi);
c91b7f66
FF		 1825 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
1826 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1827 }
1828
1829 return work_done;
1830}
1831
1832/* Interrupt bottom half */
1833static void bcmgenet_irq_task(struct work_struct *work)
1834{
1835 struct bcmgenet_priv *priv = container_of(
1836 work, struct bcmgenet_priv, bcmgenet_irq_work);
1837
1838 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
1839
8fdb0e0f
FF		 1840 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
1841 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
1842 netif_dbg(priv, wol, priv->dev,
1843 "magic packet detected, waking up\n");
1844 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
1845 }
1846
1c1008c7
FF		 1847 /* Link UP/DOWN event */
1848 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 1849 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
80d8e96d 1850 phy_mac_interrupt(priv->phydev,
c91b7f66 1851 priv->irq0_stat & UMAC_IRQ_LINK_UP);
1c1008c7
FF		 1852 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
1853 }
1854}
1855
1856/* bcmgenet_isr1: interrupt handler for ring buffer. */
1857static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
1858{
1859 struct bcmgenet_priv *priv = dev_id;
1860 unsigned int index;
1861
1862 /* Save irq status for bottom-half processing. */
1863 priv->irq1_stat =
1864 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
1865 ~priv->int1_mask;
7fc527f9 1866 /* clear interrupts */
1c1008c7
FF		 1867 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
1868
1869 netif_dbg(priv, intr, priv->dev,
c91b7f66 1870 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
1c1008c7
FF		 1871 /* Check the MBDONE interrupts.
1872 * packet is done, reclaim descriptors
1873 */
1874 if (priv->irq1_stat & 0x0000ffff) {
1875 index = 0;
1876 for (index = 0; index < 16; index++) {
1877 if (priv->irq1_stat & (1 << index))
1878 bcmgenet_tx_reclaim(priv->dev,
c91b7f66 1879 &priv->tx_rings[index]);
1c1008c7
FF		 1880 }
1881 }
1882 return IRQ_HANDLED;
1883}
1884
1885/* bcmgenet_isr0: Handle various interrupts. */
1886static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
1887{
1888 struct bcmgenet_priv *priv = dev_id;
1889
1890 /* Save irq status for bottom-half processing. */
1891 priv->irq0_stat =
1892 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
1893 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
7fc527f9 1894 /* clear interrupts */
1c1008c7
FF		 1895 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
1896
1897 netif_dbg(priv, intr, priv->dev,
c91b7f66 1898 "IRQ=0x%x\n", priv->irq0_stat);
1c1008c7
FF		 1899
1900 if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
1901 /* We use NAPI(software interrupt throttling, if
1902 * Rx Descriptor throttling is not used.
1903 * Disable interrupt, will be enabled in the poll method.
1904 */
1905 if (likely(napi_schedule_prep(&priv->napi))) {
c91b7f66
FF		 1906 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
1907 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1908 __napi_schedule(&priv->napi);
1909 }
1910 }
1911 if (priv->irq0_stat &
1912 (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
1913 /* Tx reclaim */
1914 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1915 }
1916 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
1917 UMAC_IRQ_PHY_DET_F |
1918 UMAC_IRQ_LINK_UP |
1919 UMAC_IRQ_LINK_DOWN |
1920 UMAC_IRQ_HFB_SM |
1921 UMAC_IRQ_HFB_MM |
1922 UMAC_IRQ_MPD_R)) {
1923 /* all other interested interrupts handled in bottom half */
1924 schedule_work(&priv->bcmgenet_irq_work);
1925 }
1926
1927 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 1928 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 1929 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1930 wake_up(&priv->wq);
1931 }
1932
1933 return IRQ_HANDLED;
1934}
1935
8562056f
FF		 1936static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
1937{
1938 struct bcmgenet_priv *priv = dev_id;
1939
1940 pm_wakeup_event(&priv->pdev->dev, 0);
1941
1942 return IRQ_HANDLED;
1943}
1944
1c1008c7
FF		 1945static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
1946{
1947 u32 reg;
1948
1949 reg = bcmgenet_rbuf_ctrl_get(priv);
1950 reg |= BIT(1);
1951 bcmgenet_rbuf_ctrl_set(priv, reg);
1952 udelay(10);
1953
1954 reg &= ~BIT(1);
1955 bcmgenet_rbuf_ctrl_set(priv, reg);
1956 udelay(10);
1957}
1958
1959static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 1960 unsigned char *addr)
1c1008c7
FF		 1961{
1962 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
1963 (addr[2] << 8) | addr[3], UMAC_MAC0);
1964 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
1965}
1966
1967static int bcmgenet_wol_resume(struct bcmgenet_priv *priv)
1968{
1c1008c7 1969 /* From WOL-enabled suspend, switch to regular clock */
98bb7399
FF		 1970 if (priv->wolopts)
1971 clk_disable_unprepare(priv->clk_wol);
1c1008c7 1972
80d8e96d 1973 phy_init_hw(priv->phydev);
1c1008c7
FF		 1974 /* Speed settings must be restored */
1975 bcmgenet_mii_config(priv->dev);
1976
1977 return 0;
1978}
1979
1980/* Returns a reusable dma control register value */
1981static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
1982{
1983 u32 reg;
1984 u32 dma_ctrl;
1985
1986 /* disable DMA */
1987 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
1988 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1989 reg &= ~dma_ctrl;
1990 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1991
1992 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1993 reg &= ~dma_ctrl;
1994 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1995
1996 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
1997 udelay(10);
1998 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
1999
2000 return dma_ctrl;
2001}
2002
2003static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2004{
2005 u32 reg;
2006
2007 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2008 reg |= dma_ctrl;
2009 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2010
2011 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2012 reg |= dma_ctrl;
2013 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2014}
2015
909ff5ef
FF		 2016static void bcmgenet_netif_start(struct net_device *dev)
2017{
2018 struct bcmgenet_priv *priv = netdev_priv(dev);
2019
2020 /* Start the network engine */
2021 napi_enable(&priv->napi);
2022
2023 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2024
2025 if (phy_is_internal(priv->phydev))
2026 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2027
2028 netif_tx_start_all_queues(dev);
2029
2030 phy_start(priv->phydev);
2031}
2032
1c1008c7
FF		 2033static int bcmgenet_open(struct net_device *dev)
2034{
2035 struct bcmgenet_priv *priv = netdev_priv(dev);
2036 unsigned long dma_ctrl;
2037 u32 reg;
2038 int ret;
2039
2040 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2041
2042 /* Turn on the clock */
2043 if (!IS_ERR(priv->clk))
2044 clk_prepare_enable(priv->clk);
2045
2046 /* take MAC out of reset */
2047 bcmgenet_umac_reset(priv);
2048
2049 ret = init_umac(priv);
2050 if (ret)
2051 goto err_clk_disable;
2052
2053 /* disable ethernet MAC while updating its registers */
e29585b8 2054 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2055
909ff5ef
FF		 2056 /* Make sure we reflect the value of CRC_CMD_FWD */
2057 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2058 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2059
1c1008c7
FF		 2060 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2061
1c1008c7
FF		 2062 if (phy_is_internal(priv->phydev)) {
2063 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2064 reg |= EXT_ENERGY_DET_MASK;
2065 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2066 }
2067
2068 /* Disable RX/TX DMA and flush TX queues */
2069 dma_ctrl = bcmgenet_dma_disable(priv);
2070
2071 /* Reinitialize TDMA and RDMA and SW housekeeping */
2072 ret = bcmgenet_init_dma(priv);
2073 if (ret) {
2074 netdev_err(dev, "failed to initialize DMA\n");
2075 goto err_fini_dma;
2076 }
2077
2078 /* Always enable ring 16 - descriptor ring */
2079 bcmgenet_enable_dma(priv, dma_ctrl);
2080
2081 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2082 dev->name, priv);
1c1008c7
FF		 2083 if (ret < 0) {
2084 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2085 goto err_fini_dma;
2086 }
2087
2088 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2089 dev->name, priv);
1c1008c7
FF		 2090 if (ret < 0) {
2091 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2092 goto err_irq0;
2093 }
2094
909ff5ef 2095 bcmgenet_netif_start(dev);
1c1008c7
FF		 2096
2097 return 0;
2098
2099err_irq0:
2100 free_irq(priv->irq0, dev);
2101err_fini_dma:
2102 bcmgenet_fini_dma(priv);
2103err_clk_disable:
2104 if (!IS_ERR(priv->clk))
2105 clk_disable_unprepare(priv->clk);
2106 return ret;
2107}
2108
2109static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2110{
2111 int ret = 0;
2112 int timeout = 0;
2113 u32 reg;
2114
2115 /* Disable TDMA to stop add more frames in TX DMA */
2116 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2117 reg &= ~DMA_EN;
2118 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2119
2120 /* Check TDMA status register to confirm TDMA is disabled */
2121 while (timeout++ < DMA_TIMEOUT_VAL) {
2122 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2123 if (reg & DMA_DISABLED)
2124 break;
2125
2126 udelay(1);
2127 }
2128
2129 if (timeout == DMA_TIMEOUT_VAL) {
c91b7f66 2130 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
1c1008c7
FF		 2131 ret = -ETIMEDOUT;
2132 }
2133
2134 /* Wait 10ms for packet drain in both tx and rx dma */
2135 usleep_range(10000, 20000);
2136
2137 /* Disable RDMA */
2138 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2139 reg &= ~DMA_EN;
2140 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2141
2142 timeout = 0;
2143 /* Check RDMA status register to confirm RDMA is disabled */
2144 while (timeout++ < DMA_TIMEOUT_VAL) {
2145 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2146 if (reg & DMA_DISABLED)
2147 break;
2148
2149 udelay(1);
2150 }
2151
2152 if (timeout == DMA_TIMEOUT_VAL) {
c91b7f66
FF		 2153 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2154 ret = -ETIMEDOUT;
1c1008c7
FF		 2155 }
2156
2157 return ret;
2158}
2159
909ff5ef
FF		 2160static void bcmgenet_netif_stop(struct net_device *dev)
2161{
2162 struct bcmgenet_priv *priv = netdev_priv(dev);
2163
2164 netif_tx_stop_all_queues(dev);
2165 napi_disable(&priv->napi);
2166 phy_stop(priv->phydev);
2167
2168 bcmgenet_intr_disable(priv);
2169
2170 /* Wait for pending work items to complete. Since interrupts are
2171 * disabled no new work will be scheduled.
2172 */
2173 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4
FF		 2174
2175 priv->old_pause = -1;
2176 priv->old_link = -1;
2177 priv->old_duplex = -1;
909ff5ef
FF		 2178}
2179
1c1008c7
FF		 2180static int bcmgenet_close(struct net_device *dev)
2181{
2182 struct bcmgenet_priv *priv = netdev_priv(dev);
2183 int ret;
1c1008c7
FF		 2184
2185 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2186
909ff5ef 2187 bcmgenet_netif_stop(dev);
1c1008c7
FF		 2188
2189 /* Disable MAC receive */
e29585b8 2190 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2191
1c1008c7
FF		 2192 ret = bcmgenet_dma_teardown(priv);
2193 if (ret)
2194 return ret;
2195
2196 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2197 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2198
1c1008c7
FF		 2199 /* tx reclaim */
2200 bcmgenet_tx_reclaim_all(dev);
2201 bcmgenet_fini_dma(priv);
2202
2203 free_irq(priv->irq0, priv);
2204 free_irq(priv->irq1, priv);
2205
1c1008c7
FF		 2206 if (phy_is_internal(priv->phydev))
2207 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2208
1c1008c7
FF		 2209 if (!IS_ERR(priv->clk))
2210 clk_disable_unprepare(priv->clk);
2211
2212 return 0;
2213}
2214
2215static void bcmgenet_timeout(struct net_device *dev)
2216{
2217 struct bcmgenet_priv *priv = netdev_priv(dev);
2218
2219 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2220
2221 dev->trans_start = jiffies;
2222
2223 dev->stats.tx_errors++;
2224
2225 netif_tx_wake_all_queues(dev);
2226}
2227
2228#define MAX_MC_COUNT 16
2229
2230static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2231 unsigned char *addr,
2232 int *i,
2233 int *mc)
2234{
2235 u32 reg;
2236
c91b7f66
FF		 2237 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2238 UMAC_MDF_ADDR + (*i * 4));
2239 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2240 addr[4] << 8 | addr[5],
2241 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7
FF		 2242 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2243 reg |= (1 << (MAX_MC_COUNT - *mc));
2244 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2245 *i += 2;
2246 (*mc)++;
2247}
2248
2249static void bcmgenet_set_rx_mode(struct net_device *dev)
2250{
2251 struct bcmgenet_priv *priv = netdev_priv(dev);
2252 struct netdev_hw_addr *ha;
2253 int i, mc;
2254 u32 reg;
2255
2256 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2257
7fc527f9 2258 /* Promiscuous mode */
1c1008c7
FF		 2259 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2260 if (dev->flags & IFF_PROMISC) {
2261 reg |= CMD_PROMISC;
2262 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2263 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2264 return;
2265 } else {
2266 reg &= ~CMD_PROMISC;
2267 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2268 }
2269
2270 /* UniMac doesn't support ALLMULTI */
2271 if (dev->flags & IFF_ALLMULTI) {
2272 netdev_warn(dev, "ALLMULTI is not supported\n");
2273 return;
2274 }
2275
2276 /* update MDF filter */
2277 i = 0;
2278 mc = 0;
2279 /* Broadcast */
2280 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2281 /* my own address.*/
2282 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2283 /* Unicast list*/
2284 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2285 return;
2286
2287 if (!netdev_uc_empty(dev))
2288 netdev_for_each_uc_addr(ha, dev)
2289 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2290 /* Multicast */
2291 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2292 return;
2293
2294 netdev_for_each_mc_addr(ha, dev)
2295 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2296}
2297
2298/* Set the hardware MAC address. */
2299static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2300{
2301 struct sockaddr *addr = p;
2302
2303 /* Setting the MAC address at the hardware level is not possible
2304 * without disabling the UniMAC RX/TX enable bits.
2305 */
2306 if (netif_running(dev))
2307 return -EBUSY;
2308
2309 ether_addr_copy(dev->dev_addr, addr->sa_data);
2310
2311 return 0;
2312}
2313
1c1008c7
FF		 2314static const struct net_device_ops bcmgenet_netdev_ops = {
2315 .ndo_open = bcmgenet_open,
2316 .ndo_stop = bcmgenet_close,
2317 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 2318 .ndo_tx_timeout = bcmgenet_timeout,
2319 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2320 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2321 .ndo_do_ioctl = bcmgenet_ioctl,
2322 .ndo_set_features = bcmgenet_set_features,
2323};
2324
2325/* Array of GENET hardware parameters/characteristics */
2326static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2327 [GENET_V1] = {
2328 .tx_queues = 0,
2329 .rx_queues = 0,
2330 .bds_cnt = 0,
2331 .bp_in_en_shift = 16,
2332 .bp_in_mask = 0xffff,
2333 .hfb_filter_cnt = 16,
2334 .qtag_mask = 0x1F,
2335 .hfb_offset = 0x1000,
2336 .rdma_offset = 0x2000,
2337 .tdma_offset = 0x3000,
2338 .words_per_bd = 2,
2339 },
2340 [GENET_V2] = {
2341 .tx_queues = 4,
2342 .rx_queues = 4,
2343 .bds_cnt = 32,
2344 .bp_in_en_shift = 16,
2345 .bp_in_mask = 0xffff,
2346 .hfb_filter_cnt = 16,
2347 .qtag_mask = 0x1F,
2348 .tbuf_offset = 0x0600,
2349 .hfb_offset = 0x1000,
2350 .hfb_reg_offset = 0x2000,
2351 .rdma_offset = 0x3000,
2352 .tdma_offset = 0x4000,
2353 .words_per_bd = 2,
2354 .flags = GENET_HAS_EXT,
2355 },
2356 [GENET_V3] = {
2357 .tx_queues = 4,
2358 .rx_queues = 4,
2359 .bds_cnt = 32,
2360 .bp_in_en_shift = 17,
2361 .bp_in_mask = 0x1ffff,
2362 .hfb_filter_cnt = 48,
2363 .qtag_mask = 0x3F,
2364 .tbuf_offset = 0x0600,
2365 .hfb_offset = 0x8000,
2366 .hfb_reg_offset = 0xfc00,
2367 .rdma_offset = 0x10000,
2368 .tdma_offset = 0x11000,
2369 .words_per_bd = 2,
2370 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2371 },
2372 [GENET_V4] = {
2373 .tx_queues = 4,
2374 .rx_queues = 4,
2375 .bds_cnt = 32,
2376 .bp_in_en_shift = 17,
2377 .bp_in_mask = 0x1ffff,
2378 .hfb_filter_cnt = 48,
2379 .qtag_mask = 0x3F,
2380 .tbuf_offset = 0x0600,
2381 .hfb_offset = 0x8000,
2382 .hfb_reg_offset = 0xfc00,
2383 .rdma_offset = 0x2000,
2384 .tdma_offset = 0x4000,
2385 .words_per_bd = 3,
2386 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2387 },
2388};
2389
2390/* Infer hardware parameters from the detected GENET version */
2391static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2392{
2393 struct bcmgenet_hw_params *params;
2394 u32 reg;
2395 u8 major;
2396
2397 if (GENET_IS_V4(priv)) {
2398 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2399 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2400 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2401 priv->version = GENET_V4;
2402 } else if (GENET_IS_V3(priv)) {
2403 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2404 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2405 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2406 priv->version = GENET_V3;
2407 } else if (GENET_IS_V2(priv)) {
2408 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2409 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2410 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2411 priv->version = GENET_V2;
2412 } else if (GENET_IS_V1(priv)) {
2413 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2414 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2415 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2416 priv->version = GENET_V1;
2417 }
2418
2419 /* enum genet_version starts at 1 */
2420 priv->hw_params = &bcmgenet_hw_params[priv->version];
2421 params = priv->hw_params;
2422
2423 /* Read GENET HW version */
2424 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2425 major = (reg >> 24 & 0x0f);
2426 if (major == 5)
2427 major = 4;
2428 else if (major == 0)
2429 major = 1;
2430 if (major != priv->version) {
2431 dev_err(&priv->pdev->dev,
2432 "GENET version mismatch, got: %d, configured for: %d\n",
2433 major, priv->version);
2434 }
2435
2436 /* Print the GENET core version */
2437 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 2438 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7
FF		 2439
2440#ifdef CONFIG_PHYS_ADDR_T_64BIT
2441 if (!(params->flags & GENET_HAS_40BITS))
2442 pr_warn("GENET does not support 40-bits PA\n");
2443#endif
2444
2445 pr_debug("Configuration for version: %d\n"
2446 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2447 "BP << en: %2d, BP msk: 0x%05x\n"
2448 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2449 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2450 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2451 "Words/BD: %d\n",
2452 priv->version,
2453 params->tx_queues, params->rx_queues, params->bds_cnt,
2454 params->bp_in_en_shift, params->bp_in_mask,
2455 params->hfb_filter_cnt, params->qtag_mask,
2456 params->tbuf_offset, params->hfb_offset,
2457 params->hfb_reg_offset,
2458 params->rdma_offset, params->tdma_offset,
2459 params->words_per_bd);
2460}
2461
2462static const struct of_device_id bcmgenet_match[] = {
2463 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2464 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2465 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2466 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2467 { },
2468};
2469
2470static int bcmgenet_probe(struct platform_device *pdev)
2471{
2472 struct device_node *dn = pdev->dev.of_node;
2473 const struct of_device_id *of_id;
2474 struct bcmgenet_priv *priv;
2475 struct net_device *dev;
2476 const void *macaddr;
2477 struct resource *r;
2478 int err = -EIO;
2479
2480 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2481 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
2482 if (!dev) {
2483 dev_err(&pdev->dev, "can't allocate net device\n");
2484 return -ENOMEM;
2485 }
2486
2487 of_id = of_match_node(bcmgenet_match, dn);
2488 if (!of_id)
2489 return -EINVAL;
2490
2491 priv = netdev_priv(dev);
2492 priv->irq0 = platform_get_irq(pdev, 0);
2493 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 2494 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 2495 if (!priv->irq0 || !priv->irq1) {
2496 dev_err(&pdev->dev, "can't find IRQs\n");
2497 err = -EINVAL;
2498 goto err;
2499 }
2500
2501 macaddr = of_get_mac_address(dn);
2502 if (!macaddr) {
2503 dev_err(&pdev->dev, "can't find MAC address\n");
2504 err = -EINVAL;
2505 goto err;
2506 }
2507
2508 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 2509 priv->base = devm_ioremap_resource(&pdev->dev, r);
2510 if (IS_ERR(priv->base)) {
2511 err = PTR_ERR(priv->base);
1c1008c7
FF		 2512 goto err;
2513 }
2514
2515 SET_NETDEV_DEV(dev, &pdev->dev);
2516 dev_set_drvdata(&pdev->dev, dev);
2517 ether_addr_copy(dev->dev_addr, macaddr);
2518 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 2519 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7
FF		 2520 dev->netdev_ops = &bcmgenet_netdev_ops;
2521 netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2522
2523 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2524
2525 /* Set hardware features */
2526 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2527 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2528
8562056f
FF		 2529 /* Request the WOL interrupt and advertise suspend if available */
2530 priv->wol_irq_disabled = true;
2531 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
2532 dev->name, priv);
2533 if (!err)
2534 device_set_wakeup_capable(&pdev->dev, 1);
2535
1c1008c7
FF		 2536 /* Set the needed headroom to account for any possible
2537 * features enabling/disabling at runtime
2538 */
2539 dev->needed_headroom += 64;
2540
2541 netdev_boot_setup_check(dev);
2542
2543 priv->dev = dev;
2544 priv->pdev = pdev;
2545 priv->version = (enum bcmgenet_version)of_id->data;
2546
e4a60a93
FF		 2547 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2548 if (IS_ERR(priv->clk))
2549 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2550
2551 if (!IS_ERR(priv->clk))
2552 clk_prepare_enable(priv->clk);
2553
1c1008c7
FF		 2554 bcmgenet_set_hw_params(priv);
2555
1c1008c7
FF		 2556 /* Mii wait queue */
2557 init_waitqueue_head(&priv->wq);
2558 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2559 priv->rx_buf_len = RX_BUF_LENGTH;
2560 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2561
1c1008c7
FF		 2562 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2563 if (IS_ERR(priv->clk_wol))
2564 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2565
1c1008c7
FF		 2566 err = reset_umac(priv);
2567 if (err)
2568 goto err_clk_disable;
2569
2570 err = bcmgenet_mii_init(dev);
2571 if (err)
2572 goto err_clk_disable;
2573
2574 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
2575 * just the ring 16 descriptor based TX
2576 */
2577 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2578 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2579
219575eb
FF		 2580 /* libphy will determine the link state */
2581 netif_carrier_off(dev);
2582
1c1008c7
FF		 2583 /* Turn off the main clock, WOL clock is handled separately */
2584 if (!IS_ERR(priv->clk))
2585 clk_disable_unprepare(priv->clk);
2586
0f50ce96
FF		 2587 err = register_netdev(dev);
2588 if (err)
2589 goto err;
2590
1c1008c7
FF		 2591 return err;
2592
2593err_clk_disable:
2594 if (!IS_ERR(priv->clk))
2595 clk_disable_unprepare(priv->clk);
2596err:
2597 free_netdev(dev);
2598 return err;
2599}
2600
2601static int bcmgenet_remove(struct platform_device *pdev)
2602{
2603 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2604
2605 dev_set_drvdata(&pdev->dev, NULL);
2606 unregister_netdev(priv->dev);
2607 bcmgenet_mii_exit(priv->dev);
2608 free_netdev(priv->dev);
2609
2610 return 0;
2611}
2612
b6e978e5
FF		 2613#ifdef CONFIG_PM_SLEEP
2614static int bcmgenet_suspend(struct device *d)
2615{
2616 struct net_device *dev = dev_get_drvdata(d);
2617 struct bcmgenet_priv *priv = netdev_priv(dev);
2618 int ret;
2619
2620 if (!netif_running(dev))
2621 return 0;
2622
2623 bcmgenet_netif_stop(dev);
2624
cc013fb4
FF		 2625 phy_suspend(priv->phydev);
2626
b6e978e5
FF		 2627 netif_device_detach(dev);
2628
2629 /* Disable MAC receive */
2630 umac_enable_set(priv, CMD_RX_EN, false);
2631
2632 ret = bcmgenet_dma_teardown(priv);
2633 if (ret)
2634 return ret;
2635
2636 /* Disable MAC transmit. TX DMA disabled have to done before this */
2637 umac_enable_set(priv, CMD_TX_EN, false);
2638
2639 /* tx reclaim */
2640 bcmgenet_tx_reclaim_all(dev);
2641 bcmgenet_fini_dma(priv);
2642
8c90db72
FF		 2643 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
2644 if (device_may_wakeup(d) && priv->wolopts) {
2645 bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
2646 clk_prepare_enable(priv->clk_wol);
2647 }
2648
b6e978e5
FF		 2649 /* Turn off the clocks */
2650 clk_disable_unprepare(priv->clk);
2651
2652 return 0;
2653}
2654
2655static int bcmgenet_resume(struct device *d)
2656{
2657 struct net_device *dev = dev_get_drvdata(d);
2658 struct bcmgenet_priv *priv = netdev_priv(dev);
2659 unsigned long dma_ctrl;
2660 int ret;
2661 u32 reg;
2662
2663 if (!netif_running(dev))
2664 return 0;
2665
2666 /* Turn on the clock */
2667 ret = clk_prepare_enable(priv->clk);
2668 if (ret)
2669 return ret;
2670
2671 bcmgenet_umac_reset(priv);
2672
2673 ret = init_umac(priv);
2674 if (ret)
2675 goto out_clk_disable;
2676
98bb7399 2677 ret = bcmgenet_wol_resume(priv);
8c90db72
FF		 2678 if (ret)
2679 goto out_clk_disable;
2680
b6e978e5
FF		 2681 /* disable ethernet MAC while updating its registers */
2682 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2683
2684 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2685
2686 if (phy_is_internal(priv->phydev)) {
2687 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2688 reg |= EXT_ENERGY_DET_MASK;
2689 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2690 }
2691
98bb7399
FF		 2692 if (priv->wolopts)
2693 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2694
b6e978e5
FF		 2695 /* Disable RX/TX DMA and flush TX queues */
2696 dma_ctrl = bcmgenet_dma_disable(priv);
2697
2698 /* Reinitialize TDMA and RDMA and SW housekeeping */
2699 ret = bcmgenet_init_dma(priv);
2700 if (ret) {
2701 netdev_err(dev, "failed to initialize DMA\n");
2702 goto out_clk_disable;
2703 }
2704
2705 /* Always enable ring 16 - descriptor ring */
2706 bcmgenet_enable_dma(priv, dma_ctrl);
2707
2708 netif_device_attach(dev);
2709
cc013fb4
FF		 2710 phy_resume(priv->phydev);
2711
b6e978e5
FF		 2712 bcmgenet_netif_start(dev);
2713
2714 return 0;
2715
2716out_clk_disable:
2717 clk_disable_unprepare(priv->clk);
2718 return ret;
2719}
2720#endif /* CONFIG_PM_SLEEP */
2721
2722static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
2723
1c1008c7
FF		 2724static struct platform_driver bcmgenet_driver = {
2725 .probe = bcmgenet_probe,
2726 .remove = bcmgenet_remove,
2727 .driver = {
2728 .name = "bcmgenet",
2729 .owner = THIS_MODULE,
2730 .of_match_table = bcmgenet_match,
b6e978e5 2731 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 2732 },
2733};
2734module_platform_driver(bcmgenet_driver);
2735
2736MODULE_AUTHOR("Broadcom Corporation");
2737MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2738MODULE_ALIAS("platform:bcmgenet");
2739MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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