Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
f90fdc3c | 2 | * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation |
f5279ffd | 3 | * Copyright (c) 2006, 2007 Maciej W. Rozycki |
1da177e4 LT |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
74b0247f | 14 | * |
1da177e4 | 15 | * You should have received a copy of the GNU General Public License |
0ab75ae8 | 16 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
1da177e4 LT |
17 | * |
18 | * | |
19 | * This driver is designed for the Broadcom SiByte SOC built-in | |
20 | * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp. | |
f5279ffd MR |
21 | * |
22 | * Updated to the driver model and the PHY abstraction layer | |
23 | * by Maciej W. Rozycki. | |
1da177e4 | 24 | */ |
f5279ffd MR |
25 | |
26 | #include <linux/bug.h> | |
1da177e4 LT |
27 | #include <linux/module.h> |
28 | #include <linux/kernel.h> | |
29 | #include <linux/string.h> | |
30 | #include <linux/timer.h> | |
31 | #include <linux/errno.h> | |
32 | #include <linux/ioport.h> | |
33 | #include <linux/slab.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <linux/skbuff.h> | |
1da177e4 | 38 | #include <linux/bitops.h> |
f5279ffd MR |
39 | #include <linux/err.h> |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/mii.h> | |
42 | #include <linux/phy.h> | |
43 | #include <linux/platform_device.h> | |
70c71606 | 44 | #include <linux/prefetch.h> |
f5279ffd | 45 | |
1da177e4 | 46 | #include <asm/cache.h> |
f5279ffd MR |
47 | #include <asm/io.h> |
48 | #include <asm/processor.h> /* Processor type for cache alignment. */ | |
1da177e4 | 49 | |
1da177e4 LT |
50 | /* Operational parameters that usually are not changed. */ |
51 | ||
52 | #define CONFIG_SBMAC_COALESCE | |
53 | ||
1da177e4 LT |
54 | /* Time in jiffies before concluding the transmitter is hung. */ |
55 | #define TX_TIMEOUT (2*HZ) | |
56 | ||
57 | ||
58 | MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)"); | |
59 | MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver"); | |
60 | ||
61 | /* A few user-configurable values which may be modified when a driver | |
62 | module is loaded. */ | |
63 | ||
64 | /* 1 normal messages, 0 quiet .. 7 verbose. */ | |
65 | static int debug = 1; | |
66 | module_param(debug, int, S_IRUGO); | |
67 | MODULE_PARM_DESC(debug, "Debug messages"); | |
68 | ||
1da177e4 | 69 | #ifdef CONFIG_SBMAC_COALESCE |
693aa947 MM |
70 | static int int_pktcnt_tx = 255; |
71 | module_param(int_pktcnt_tx, int, S_IRUGO); | |
72 | MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count"); | |
1da177e4 | 73 | |
693aa947 MM |
74 | static int int_timeout_tx = 255; |
75 | module_param(int_timeout_tx, int, S_IRUGO); | |
76 | MODULE_PARM_DESC(int_timeout_tx, "TX timeout value"); | |
77 | ||
78 | static int int_pktcnt_rx = 64; | |
79 | module_param(int_pktcnt_rx, int, S_IRUGO); | |
80 | MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count"); | |
81 | ||
82 | static int int_timeout_rx = 64; | |
83 | module_param(int_timeout_rx, int, S_IRUGO); | |
84 | MODULE_PARM_DESC(int_timeout_rx, "RX timeout value"); | |
1da177e4 LT |
85 | #endif |
86 | ||
f5279ffd | 87 | #include <asm/sibyte/board.h> |
1da177e4 | 88 | #include <asm/sibyte/sb1250.h> |
f90fdc3c RB |
89 | #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) |
90 | #include <asm/sibyte/bcm1480_regs.h> | |
91 | #include <asm/sibyte/bcm1480_int.h> | |
693aa947 | 92 | #define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST |
f90fdc3c | 93 | #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) |
1da177e4 | 94 | #include <asm/sibyte/sb1250_regs.h> |
1da177e4 | 95 | #include <asm/sibyte/sb1250_int.h> |
f90fdc3c | 96 | #else |
0b1974de | 97 | #error invalid SiByte MAC configuration |
f90fdc3c | 98 | #endif |
1da177e4 | 99 | #include <asm/sibyte/sb1250_scd.h> |
f90fdc3c RB |
100 | #include <asm/sibyte/sb1250_mac.h> |
101 | #include <asm/sibyte/sb1250_dma.h> | |
1da177e4 | 102 | |
f90fdc3c RB |
103 | #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) |
104 | #define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2)) | |
105 | #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) | |
106 | #define UNIT_INT(n) (K_INT_MAC_0 + (n)) | |
107 | #else | |
0b1974de | 108 | #error invalid SiByte MAC configuration |
f90fdc3c | 109 | #endif |
1da177e4 | 110 | |
f5279ffd MR |
111 | #ifdef K_INT_PHY |
112 | #define SBMAC_PHY_INT K_INT_PHY | |
113 | #else | |
114 | #define SBMAC_PHY_INT PHY_POLL | |
115 | #endif | |
116 | ||
1da177e4 LT |
117 | /********************************************************************** |
118 | * Simple types | |
119 | ********************************************************************* */ | |
120 | ||
f5279ffd MR |
121 | enum sbmac_speed { |
122 | sbmac_speed_none = 0, | |
123 | sbmac_speed_10 = SPEED_10, | |
124 | sbmac_speed_100 = SPEED_100, | |
125 | sbmac_speed_1000 = SPEED_1000, | |
126 | }; | |
1da177e4 | 127 | |
f5279ffd MR |
128 | enum sbmac_duplex { |
129 | sbmac_duplex_none = -1, | |
130 | sbmac_duplex_half = DUPLEX_HALF, | |
131 | sbmac_duplex_full = DUPLEX_FULL, | |
132 | }; | |
1da177e4 | 133 | |
f5279ffd MR |
134 | enum sbmac_fc { |
135 | sbmac_fc_none, | |
136 | sbmac_fc_disabled, | |
137 | sbmac_fc_frame, | |
138 | sbmac_fc_collision, | |
139 | sbmac_fc_carrier, | |
140 | }; | |
1da177e4 | 141 | |
f5279ffd MR |
142 | enum sbmac_state { |
143 | sbmac_state_uninit, | |
144 | sbmac_state_off, | |
145 | sbmac_state_on, | |
146 | sbmac_state_broken, | |
147 | }; | |
1da177e4 LT |
148 | |
149 | ||
150 | /********************************************************************** | |
151 | * Macros | |
152 | ********************************************************************* */ | |
153 | ||
154 | ||
155 | #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \ | |
156 | (d)->sbdma_dscrtable : (d)->f+1) | |
157 | ||
158 | ||
159 | #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES) | |
160 | ||
693aa947 MM |
161 | #define SBMAC_MAX_TXDESCR 256 |
162 | #define SBMAC_MAX_RXDESCR 256 | |
1da177e4 | 163 | |
74b0247f RB |
164 | #define ENET_PACKET_SIZE 1518 |
165 | /*#define ENET_PACKET_SIZE 9216 */ | |
1da177e4 LT |
166 | |
167 | /********************************************************************** | |
168 | * DMA Descriptor structure | |
169 | ********************************************************************* */ | |
170 | ||
73d73969 | 171 | struct sbdmadscr { |
1da177e4 LT |
172 | uint64_t dscr_a; |
173 | uint64_t dscr_b; | |
73d73969 | 174 | }; |
1da177e4 LT |
175 | |
176 | /********************************************************************** | |
177 | * DMA Controller structure | |
178 | ********************************************************************* */ | |
179 | ||
73d73969 | 180 | struct sbmacdma { |
74b0247f RB |
181 | |
182 | /* | |
1da177e4 LT |
183 | * This stuff is used to identify the channel and the registers |
184 | * associated with it. | |
185 | */ | |
73d73969 MR |
186 | struct sbmac_softc *sbdma_eth; /* back pointer to associated |
187 | MAC */ | |
188 | int sbdma_channel; /* channel number */ | |
189 | int sbdma_txdir; /* direction (1=transmit) */ | |
190 | int sbdma_maxdescr; /* total # of descriptors | |
191 | in ring */ | |
1da177e4 | 192 | #ifdef CONFIG_SBMAC_COALESCE |
73d73969 MR |
193 | int sbdma_int_pktcnt; |
194 | /* # descriptors rx/tx | |
195 | before interrupt */ | |
196 | int sbdma_int_timeout; | |
197 | /* # usec rx/tx interrupt */ | |
1da177e4 | 198 | #endif |
73d73969 MR |
199 | void __iomem *sbdma_config0; /* DMA config register 0 */ |
200 | void __iomem *sbdma_config1; /* DMA config register 1 */ | |
201 | void __iomem *sbdma_dscrbase; | |
202 | /* descriptor base address */ | |
203 | void __iomem *sbdma_dscrcnt; /* descriptor count register */ | |
204 | void __iomem *sbdma_curdscr; /* current descriptor | |
205 | address */ | |
206 | void __iomem *sbdma_oodpktlost; | |
207 | /* pkt drop (rx only) */ | |
74b0247f | 208 | |
1da177e4 LT |
209 | /* |
210 | * This stuff is for maintenance of the ring | |
211 | */ | |
73d73969 MR |
212 | void *sbdma_dscrtable_unaligned; |
213 | struct sbdmadscr *sbdma_dscrtable; | |
214 | /* base of descriptor table */ | |
215 | struct sbdmadscr *sbdma_dscrtable_end; | |
216 | /* end of descriptor table */ | |
217 | struct sk_buff **sbdma_ctxtable; | |
218 | /* context table, one | |
219 | per descr */ | |
220 | dma_addr_t sbdma_dscrtable_phys; | |
221 | /* and also the phys addr */ | |
222 | struct sbdmadscr *sbdma_addptr; /* next dscr for sw to add */ | |
223 | struct sbdmadscr *sbdma_remptr; /* next dscr for sw | |
224 | to remove */ | |
225 | }; | |
1da177e4 LT |
226 | |
227 | ||
228 | /********************************************************************** | |
229 | * Ethernet softc structure | |
230 | ********************************************************************* */ | |
231 | ||
232 | struct sbmac_softc { | |
74b0247f | 233 | |
1da177e4 LT |
234 | /* |
235 | * Linux-specific things | |
236 | */ | |
73d73969 MR |
237 | struct net_device *sbm_dev; /* pointer to linux device */ |
238 | struct napi_struct napi; | |
f5279ffd | 239 | struct phy_device *phy_dev; /* the associated PHY device */ |
298cf9be | 240 | struct mii_bus *mii_bus; /* the MII bus */ |
f5279ffd | 241 | int phy_irq[PHY_MAX_ADDR]; |
73d73969 | 242 | spinlock_t sbm_lock; /* spin lock */ |
73d73969 | 243 | int sbm_devflags; /* current device flags */ |
74b0247f | 244 | |
1da177e4 LT |
245 | /* |
246 | * Controller-specific things | |
247 | */ | |
73d73969 MR |
248 | void __iomem *sbm_base; /* MAC's base address */ |
249 | enum sbmac_state sbm_state; /* current state */ | |
74b0247f | 250 | |
73d73969 MR |
251 | void __iomem *sbm_macenable; /* MAC Enable Register */ |
252 | void __iomem *sbm_maccfg; /* MAC Config Register */ | |
253 | void __iomem *sbm_fifocfg; /* FIFO Config Register */ | |
254 | void __iomem *sbm_framecfg; /* Frame Config Register */ | |
255 | void __iomem *sbm_rxfilter; /* Receive Filter Register */ | |
256 | void __iomem *sbm_isr; /* Interrupt Status Register */ | |
257 | void __iomem *sbm_imr; /* Interrupt Mask Register */ | |
258 | void __iomem *sbm_mdio; /* MDIO Register */ | |
74b0247f | 259 | |
73d73969 MR |
260 | enum sbmac_speed sbm_speed; /* current speed */ |
261 | enum sbmac_duplex sbm_duplex; /* current duplex */ | |
262 | enum sbmac_fc sbm_fc; /* cur. flow control setting */ | |
f5279ffd MR |
263 | int sbm_pause; /* current pause setting */ |
264 | int sbm_link; /* current link state */ | |
74b0247f | 265 | |
104bf3fb | 266 | unsigned char sbm_hwaddr[ETH_ALEN]; |
74b0247f | 267 | |
73d73969 MR |
268 | struct sbmacdma sbm_txdma; /* only channel 0 for now */ |
269 | struct sbmacdma sbm_rxdma; | |
270 | int rx_hw_checksum; | |
271 | int sbe_idx; | |
1da177e4 LT |
272 | }; |
273 | ||
274 | ||
275 | /********************************************************************** | |
276 | * Externs | |
277 | ********************************************************************* */ | |
278 | ||
279 | /********************************************************************** | |
280 | * Prototypes | |
281 | ********************************************************************* */ | |
282 | ||
73d73969 MR |
283 | static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan, |
284 | int txrx, int maxdescr); | |
285 | static void sbdma_channel_start(struct sbmacdma *d, int rxtx); | |
789585e9 SH |
286 | static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d, |
287 | struct sk_buff *m); | |
73d73969 MR |
288 | static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *m); |
289 | static void sbdma_emptyring(struct sbmacdma *d); | |
789585e9 | 290 | static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d); |
73d73969 MR |
291 | static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d, |
292 | int work_to_do, int poll); | |
293 | static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d, | |
294 | int poll); | |
1da177e4 LT |
295 | static int sbmac_initctx(struct sbmac_softc *s); |
296 | static void sbmac_channel_start(struct sbmac_softc *s); | |
297 | static void sbmac_channel_stop(struct sbmac_softc *s); | |
73d73969 MR |
298 | static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *, |
299 | enum sbmac_state); | |
300 | static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff); | |
1da177e4 | 301 | static uint64_t sbmac_addr2reg(unsigned char *ptr); |
73d73969 | 302 | static irqreturn_t sbmac_intr(int irq, void *dev_instance); |
1da177e4 LT |
303 | static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev); |
304 | static void sbmac_setmulti(struct sbmac_softc *sc); | |
f5279ffd | 305 | static int sbmac_init(struct platform_device *pldev, long long base); |
73d73969 MR |
306 | static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed); |
307 | static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex, | |
308 | enum sbmac_fc fc); | |
1da177e4 LT |
309 | |
310 | static int sbmac_open(struct net_device *dev); | |
1da177e4 | 311 | static void sbmac_tx_timeout (struct net_device *dev); |
1da177e4 LT |
312 | static void sbmac_set_rx_mode(struct net_device *dev); |
313 | static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
314 | static int sbmac_close(struct net_device *dev); | |
bea3348e | 315 | static int sbmac_poll(struct napi_struct *napi, int budget); |
693aa947 | 316 | |
f5279ffd | 317 | static void sbmac_mii_poll(struct net_device *dev); |
59b81827 | 318 | static int sbmac_mii_probe(struct net_device *dev); |
1da177e4 | 319 | |
f5279ffd MR |
320 | static void sbmac_mii_sync(void __iomem *sbm_mdio); |
321 | static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data, | |
73d73969 | 322 | int bitcnt); |
f5279ffd MR |
323 | static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx); |
324 | static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, | |
325 | u16 val); | |
1da177e4 LT |
326 | |
327 | ||
328 | /********************************************************************** | |
329 | * Globals | |
330 | ********************************************************************* */ | |
331 | ||
f5279ffd | 332 | static char sbmac_string[] = "sb1250-mac"; |
f5279ffd MR |
333 | |
334 | static char sbmac_mdio_string[] = "sb1250-mac-mdio"; | |
1da177e4 LT |
335 | |
336 | ||
337 | /********************************************************************** | |
338 | * MDIO constants | |
339 | ********************************************************************* */ | |
340 | ||
341 | #define MII_COMMAND_START 0x01 | |
342 | #define MII_COMMAND_READ 0x02 | |
343 | #define MII_COMMAND_WRITE 0x01 | |
344 | #define MII_COMMAND_ACK 0x02 | |
345 | ||
1da177e4 LT |
346 | #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */ |
347 | ||
348 | #define ENABLE 1 | |
349 | #define DISABLE 0 | |
350 | ||
351 | /********************************************************************** | |
f5279ffd | 352 | * SBMAC_MII_SYNC(sbm_mdio) |
74b0247f | 353 | * |
1da177e4 LT |
354 | * Synchronize with the MII - send a pattern of bits to the MII |
355 | * that will guarantee that it is ready to accept a command. | |
74b0247f RB |
356 | * |
357 | * Input parameters: | |
f5279ffd | 358 | * sbm_mdio - address of the MAC's MDIO register |
74b0247f | 359 | * |
1da177e4 LT |
360 | * Return value: |
361 | * nothing | |
362 | ********************************************************************* */ | |
363 | ||
f5279ffd | 364 | static void sbmac_mii_sync(void __iomem *sbm_mdio) |
1da177e4 LT |
365 | { |
366 | int cnt; | |
367 | uint64_t bits; | |
368 | int mac_mdio_genc; | |
369 | ||
f5279ffd | 370 | mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; |
74b0247f | 371 | |
1da177e4 | 372 | bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT; |
74b0247f | 373 | |
f5279ffd | 374 | __raw_writeq(bits | mac_mdio_genc, sbm_mdio); |
74b0247f | 375 | |
1da177e4 | 376 | for (cnt = 0; cnt < 32; cnt++) { |
f5279ffd MR |
377 | __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio); |
378 | __raw_writeq(bits | mac_mdio_genc, sbm_mdio); | |
1da177e4 LT |
379 | } |
380 | } | |
381 | ||
382 | /********************************************************************** | |
f5279ffd | 383 | * SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt) |
74b0247f | 384 | * |
1da177e4 LT |
385 | * Send some bits to the MII. The bits to be sent are right- |
386 | * justified in the 'data' parameter. | |
74b0247f RB |
387 | * |
388 | * Input parameters: | |
f5279ffd MR |
389 | * sbm_mdio - address of the MAC's MDIO register |
390 | * data - data to send | |
391 | * bitcnt - number of bits to send | |
1da177e4 LT |
392 | ********************************************************************* */ |
393 | ||
f5279ffd MR |
394 | static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data, |
395 | int bitcnt) | |
1da177e4 LT |
396 | { |
397 | int i; | |
398 | uint64_t bits; | |
399 | unsigned int curmask; | |
400 | int mac_mdio_genc; | |
401 | ||
f5279ffd | 402 | mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; |
74b0247f | 403 | |
1da177e4 | 404 | bits = M_MAC_MDIO_DIR_OUTPUT; |
f5279ffd | 405 | __raw_writeq(bits | mac_mdio_genc, sbm_mdio); |
74b0247f | 406 | |
1da177e4 | 407 | curmask = 1 << (bitcnt - 1); |
74b0247f | 408 | |
1da177e4 LT |
409 | for (i = 0; i < bitcnt; i++) { |
410 | if (data & curmask) | |
411 | bits |= M_MAC_MDIO_OUT; | |
412 | else bits &= ~M_MAC_MDIO_OUT; | |
f5279ffd MR |
413 | __raw_writeq(bits | mac_mdio_genc, sbm_mdio); |
414 | __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio); | |
415 | __raw_writeq(bits | mac_mdio_genc, sbm_mdio); | |
1da177e4 LT |
416 | curmask >>= 1; |
417 | } | |
418 | } | |
419 | ||
420 | ||
421 | ||
422 | /********************************************************************** | |
f5279ffd | 423 | * SBMAC_MII_READ(bus, phyaddr, regidx) |
1da177e4 | 424 | * Read a PHY register. |
74b0247f RB |
425 | * |
426 | * Input parameters: | |
f5279ffd | 427 | * bus - MDIO bus handle |
1da177e4 | 428 | * phyaddr - PHY's address |
f5279ffd | 429 | * regnum - index of register to read |
74b0247f | 430 | * |
1da177e4 | 431 | * Return value: |
f5279ffd | 432 | * value read, or 0xffff if an error occurred. |
1da177e4 LT |
433 | ********************************************************************* */ |
434 | ||
f5279ffd | 435 | static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx) |
1da177e4 | 436 | { |
f5279ffd MR |
437 | struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv; |
438 | void __iomem *sbm_mdio = sc->sbm_mdio; | |
1da177e4 LT |
439 | int idx; |
440 | int error; | |
441 | int regval; | |
442 | int mac_mdio_genc; | |
443 | ||
444 | /* | |
445 | * Synchronize ourselves so that the PHY knows the next | |
446 | * thing coming down is a command | |
447 | */ | |
f5279ffd | 448 | sbmac_mii_sync(sbm_mdio); |
74b0247f | 449 | |
1da177e4 LT |
450 | /* |
451 | * Send the data to the PHY. The sequence is | |
452 | * a "start" command (2 bits) | |
453 | * a "read" command (2 bits) | |
454 | * the PHY addr (5 bits) | |
455 | * the register index (5 bits) | |
456 | */ | |
f5279ffd MR |
457 | sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2); |
458 | sbmac_mii_senddata(sbm_mdio, MII_COMMAND_READ, 2); | |
459 | sbmac_mii_senddata(sbm_mdio, phyaddr, 5); | |
460 | sbmac_mii_senddata(sbm_mdio, regidx, 5); | |
74b0247f | 461 | |
f5279ffd | 462 | mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; |
74b0247f RB |
463 | |
464 | /* | |
1da177e4 LT |
465 | * Switch the port around without a clock transition. |
466 | */ | |
f5279ffd | 467 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); |
74b0247f | 468 | |
1da177e4 LT |
469 | /* |
470 | * Send out a clock pulse to signal we want the status | |
471 | */ | |
f5279ffd MR |
472 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, |
473 | sbm_mdio); | |
474 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); | |
74b0247f RB |
475 | |
476 | /* | |
1da177e4 LT |
477 | * If an error occurred, the PHY will signal '1' back |
478 | */ | |
f5279ffd | 479 | error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN; |
74b0247f RB |
480 | |
481 | /* | |
1da177e4 LT |
482 | * Issue an 'idle' clock pulse, but keep the direction |
483 | * the same. | |
484 | */ | |
f5279ffd MR |
485 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, |
486 | sbm_mdio); | |
487 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); | |
74b0247f | 488 | |
1da177e4 | 489 | regval = 0; |
74b0247f | 490 | |
1da177e4 LT |
491 | for (idx = 0; idx < 16; idx++) { |
492 | regval <<= 1; | |
74b0247f | 493 | |
1da177e4 | 494 | if (error == 0) { |
f5279ffd | 495 | if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN) |
1da177e4 LT |
496 | regval |= 1; |
497 | } | |
74b0247f | 498 | |
f5279ffd MR |
499 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, |
500 | sbm_mdio); | |
501 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); | |
1da177e4 | 502 | } |
74b0247f | 503 | |
1da177e4 | 504 | /* Switch back to output */ |
f5279ffd | 505 | __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio); |
74b0247f | 506 | |
1da177e4 LT |
507 | if (error == 0) |
508 | return regval; | |
f5279ffd | 509 | return 0xffff; |
1da177e4 LT |
510 | } |
511 | ||
512 | ||
513 | /********************************************************************** | |
f5279ffd | 514 | * SBMAC_MII_WRITE(bus, phyaddr, regidx, regval) |
74b0247f | 515 | * |
1da177e4 | 516 | * Write a value to a PHY register. |
74b0247f RB |
517 | * |
518 | * Input parameters: | |
f5279ffd | 519 | * bus - MDIO bus handle |
1da177e4 | 520 | * phyaddr - PHY to use |
f5279ffd MR |
521 | * regidx - register within the PHY |
522 | * regval - data to write to register | |
74b0247f | 523 | * |
1da177e4 | 524 | * Return value: |
f5279ffd | 525 | * 0 for success |
1da177e4 LT |
526 | ********************************************************************* */ |
527 | ||
f5279ffd MR |
528 | static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, |
529 | u16 regval) | |
1da177e4 | 530 | { |
f5279ffd MR |
531 | struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv; |
532 | void __iomem *sbm_mdio = sc->sbm_mdio; | |
1da177e4 LT |
533 | int mac_mdio_genc; |
534 | ||
f5279ffd | 535 | sbmac_mii_sync(sbm_mdio); |
74b0247f | 536 | |
f5279ffd MR |
537 | sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2); |
538 | sbmac_mii_senddata(sbm_mdio, MII_COMMAND_WRITE, 2); | |
539 | sbmac_mii_senddata(sbm_mdio, phyaddr, 5); | |
540 | sbmac_mii_senddata(sbm_mdio, regidx, 5); | |
541 | sbmac_mii_senddata(sbm_mdio, MII_COMMAND_ACK, 2); | |
542 | sbmac_mii_senddata(sbm_mdio, regval, 16); | |
1da177e4 | 543 | |
f5279ffd | 544 | mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; |
1da177e4 | 545 | |
f5279ffd MR |
546 | __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio); |
547 | ||
548 | return 0; | |
1da177e4 LT |
549 | } |
550 | ||
551 | ||
552 | ||
553 | /********************************************************************** | |
554 | * SBDMA_INITCTX(d,s,chan,txrx,maxdescr) | |
74b0247f | 555 | * |
1da177e4 LT |
556 | * Initialize a DMA channel context. Since there are potentially |
557 | * eight DMA channels per MAC, it's nice to do this in a standard | |
74b0247f RB |
558 | * way. |
559 | * | |
560 | * Input parameters: | |
73d73969 MR |
561 | * d - struct sbmacdma (DMA channel context) |
562 | * s - struct sbmac_softc (pointer to a MAC) | |
1da177e4 LT |
563 | * chan - channel number (0..1 right now) |
564 | * txrx - Identifies DMA_TX or DMA_RX for channel direction | |
565 | * maxdescr - number of descriptors | |
74b0247f | 566 | * |
1da177e4 LT |
567 | * Return value: |
568 | * nothing | |
569 | ********************************************************************* */ | |
570 | ||
73d73969 MR |
571 | static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan, |
572 | int txrx, int maxdescr) | |
1da177e4 | 573 | { |
693aa947 MM |
574 | #ifdef CONFIG_SBMAC_COALESCE |
575 | int int_pktcnt, int_timeout; | |
576 | #endif | |
577 | ||
74b0247f RB |
578 | /* |
579 | * Save away interesting stuff in the structure | |
1da177e4 | 580 | */ |
74b0247f | 581 | |
1da177e4 LT |
582 | d->sbdma_eth = s; |
583 | d->sbdma_channel = chan; | |
584 | d->sbdma_txdir = txrx; | |
74b0247f | 585 | |
1da177e4 LT |
586 | #if 0 |
587 | /* RMON clearing */ | |
588 | s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING; | |
589 | #endif | |
590 | ||
f5279ffd MR |
591 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BYTES); |
592 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_COLLISIONS); | |
593 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_LATE_COL); | |
594 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_EX_COL); | |
595 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_FCS_ERROR); | |
596 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_ABORT); | |
597 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BAD); | |
598 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_GOOD); | |
599 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_RUNT); | |
600 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_OVERSIZE); | |
601 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BYTES); | |
602 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_MCAST); | |
603 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BCAST); | |
604 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BAD); | |
605 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_GOOD); | |
606 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_RUNT); | |
607 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_OVERSIZE); | |
608 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_FCS_ERROR); | |
609 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_LENGTH_ERROR); | |
610 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_CODE_ERROR); | |
611 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_ALIGN_ERROR); | |
1da177e4 | 612 | |
74b0247f RB |
613 | /* |
614 | * initialize register pointers | |
1da177e4 | 615 | */ |
74b0247f RB |
616 | |
617 | d->sbdma_config0 = | |
1da177e4 | 618 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0); |
74b0247f | 619 | d->sbdma_config1 = |
1da177e4 | 620 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1); |
74b0247f | 621 | d->sbdma_dscrbase = |
1da177e4 | 622 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE); |
74b0247f | 623 | d->sbdma_dscrcnt = |
1da177e4 | 624 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT); |
74b0247f | 625 | d->sbdma_curdscr = |
1da177e4 | 626 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR); |
693aa947 MM |
627 | if (d->sbdma_txdir) |
628 | d->sbdma_oodpktlost = NULL; | |
629 | else | |
630 | d->sbdma_oodpktlost = | |
631 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX); | |
74b0247f | 632 | |
1da177e4 LT |
633 | /* |
634 | * Allocate memory for the ring | |
635 | */ | |
74b0247f | 636 | |
1da177e4 | 637 | d->sbdma_maxdescr = maxdescr; |
74b0247f | 638 | |
73d73969 MR |
639 | d->sbdma_dscrtable_unaligned = kcalloc(d->sbdma_maxdescr + 1, |
640 | sizeof(*d->sbdma_dscrtable), | |
641 | GFP_KERNEL); | |
04115def RB |
642 | |
643 | /* | |
644 | * The descriptor table must be aligned to at least 16 bytes or the | |
645 | * MAC will corrupt it. | |
646 | */ | |
73d73969 MR |
647 | d->sbdma_dscrtable = (struct sbdmadscr *) |
648 | ALIGN((unsigned long)d->sbdma_dscrtable_unaligned, | |
649 | sizeof(*d->sbdma_dscrtable)); | |
74b0247f | 650 | |
1da177e4 | 651 | d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr; |
74b0247f | 652 | |
1da177e4 | 653 | d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable); |
74b0247f | 654 | |
1da177e4 LT |
655 | /* |
656 | * And context table | |
657 | */ | |
74b0247f | 658 | |
c477f334 | 659 | d->sbdma_ctxtable = kcalloc(d->sbdma_maxdescr, |
73d73969 | 660 | sizeof(*d->sbdma_ctxtable), GFP_KERNEL); |
74b0247f | 661 | |
1da177e4 LT |
662 | #ifdef CONFIG_SBMAC_COALESCE |
663 | /* | |
664 | * Setup Rx/Tx DMA coalescing defaults | |
665 | */ | |
666 | ||
693aa947 | 667 | int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx; |
1da177e4 LT |
668 | if ( int_pktcnt ) { |
669 | d->sbdma_int_pktcnt = int_pktcnt; | |
670 | } else { | |
671 | d->sbdma_int_pktcnt = 1; | |
672 | } | |
74b0247f | 673 | |
693aa947 | 674 | int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx; |
1da177e4 LT |
675 | if ( int_timeout ) { |
676 | d->sbdma_int_timeout = int_timeout; | |
677 | } else { | |
678 | d->sbdma_int_timeout = 0; | |
679 | } | |
680 | #endif | |
681 | ||
682 | } | |
683 | ||
684 | /********************************************************************** | |
685 | * SBDMA_CHANNEL_START(d) | |
74b0247f | 686 | * |
1da177e4 | 687 | * Initialize the hardware registers for a DMA channel. |
74b0247f RB |
688 | * |
689 | * Input parameters: | |
1da177e4 LT |
690 | * d - DMA channel to init (context must be previously init'd |
691 | * rxtx - DMA_RX or DMA_TX depending on what type of channel | |
74b0247f | 692 | * |
1da177e4 LT |
693 | * Return value: |
694 | * nothing | |
695 | ********************************************************************* */ | |
696 | ||
73d73969 | 697 | static void sbdma_channel_start(struct sbmacdma *d, int rxtx) |
1da177e4 LT |
698 | { |
699 | /* | |
700 | * Turn on the DMA channel | |
701 | */ | |
74b0247f | 702 | |
1da177e4 | 703 | #ifdef CONFIG_SBMAC_COALESCE |
2039973a RB |
704 | __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) | |
705 | 0, d->sbdma_config1); | |
706 | __raw_writeq(M_DMA_EOP_INT_EN | | |
1da177e4 LT |
707 | V_DMA_RINGSZ(d->sbdma_maxdescr) | |
708 | V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) | | |
2039973a | 709 | 0, d->sbdma_config0); |
1da177e4 | 710 | #else |
2039973a RB |
711 | __raw_writeq(0, d->sbdma_config1); |
712 | __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) | | |
713 | 0, d->sbdma_config0); | |
1da177e4 LT |
714 | #endif |
715 | ||
2039973a | 716 | __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase); |
1da177e4 LT |
717 | |
718 | /* | |
719 | * Initialize ring pointers | |
720 | */ | |
721 | ||
722 | d->sbdma_addptr = d->sbdma_dscrtable; | |
723 | d->sbdma_remptr = d->sbdma_dscrtable; | |
724 | } | |
725 | ||
726 | /********************************************************************** | |
727 | * SBDMA_CHANNEL_STOP(d) | |
74b0247f | 728 | * |
1da177e4 | 729 | * Initialize the hardware registers for a DMA channel. |
74b0247f RB |
730 | * |
731 | * Input parameters: | |
1da177e4 | 732 | * d - DMA channel to init (context must be previously init'd |
74b0247f | 733 | * |
1da177e4 LT |
734 | * Return value: |
735 | * nothing | |
736 | ********************************************************************* */ | |
737 | ||
73d73969 | 738 | static void sbdma_channel_stop(struct sbmacdma *d) |
1da177e4 LT |
739 | { |
740 | /* | |
741 | * Turn off the DMA channel | |
742 | */ | |
74b0247f | 743 | |
2039973a | 744 | __raw_writeq(0, d->sbdma_config1); |
74b0247f | 745 | |
2039973a | 746 | __raw_writeq(0, d->sbdma_dscrbase); |
74b0247f | 747 | |
2039973a | 748 | __raw_writeq(0, d->sbdma_config0); |
74b0247f | 749 | |
1da177e4 LT |
750 | /* |
751 | * Zero ring pointers | |
752 | */ | |
74b0247f | 753 | |
2039973a RB |
754 | d->sbdma_addptr = NULL; |
755 | d->sbdma_remptr = NULL; | |
1da177e4 LT |
756 | } |
757 | ||
789585e9 SH |
758 | static inline void sbdma_align_skb(struct sk_buff *skb, |
759 | unsigned int power2, unsigned int offset) | |
1da177e4 | 760 | { |
789585e9 SH |
761 | unsigned char *addr = skb->data; |
762 | unsigned char *newaddr = PTR_ALIGN(addr, power2); | |
74b0247f | 763 | |
789585e9 | 764 | skb_reserve(skb, newaddr - addr + offset); |
1da177e4 LT |
765 | } |
766 | ||
767 | ||
768 | /********************************************************************** | |
769 | * SBDMA_ADD_RCVBUFFER(d,sb) | |
74b0247f | 770 | * |
1da177e4 LT |
771 | * Add a buffer to the specified DMA channel. For receive channels, |
772 | * this queues a buffer for inbound packets. | |
74b0247f RB |
773 | * |
774 | * Input parameters: | |
789585e9 SH |
775 | * sc - softc structure |
776 | * d - DMA channel descriptor | |
1da177e4 | 777 | * sb - sk_buff to add, or NULL if we should allocate one |
74b0247f | 778 | * |
1da177e4 LT |
779 | * Return value: |
780 | * 0 if buffer could not be added (ring is full) | |
781 | * 1 if buffer added successfully | |
782 | ********************************************************************* */ | |
783 | ||
784 | ||
789585e9 SH |
785 | static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d, |
786 | struct sk_buff *sb) | |
1da177e4 | 787 | { |
789585e9 | 788 | struct net_device *dev = sc->sbm_dev; |
73d73969 MR |
789 | struct sbdmadscr *dsc; |
790 | struct sbdmadscr *nextdsc; | |
1da177e4 LT |
791 | struct sk_buff *sb_new = NULL; |
792 | int pktsize = ENET_PACKET_SIZE; | |
74b0247f | 793 | |
1da177e4 | 794 | /* get pointer to our current place in the ring */ |
74b0247f | 795 | |
1da177e4 LT |
796 | dsc = d->sbdma_addptr; |
797 | nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); | |
74b0247f | 798 | |
1da177e4 LT |
799 | /* |
800 | * figure out if the ring is full - if the next descriptor | |
801 | * is the same as the one that we're going to remove from | |
802 | * the ring, the ring is full | |
803 | */ | |
74b0247f | 804 | |
1da177e4 LT |
805 | if (nextdsc == d->sbdma_remptr) { |
806 | return -ENOSPC; | |
807 | } | |
808 | ||
74b0247f RB |
809 | /* |
810 | * Allocate a sk_buff if we don't already have one. | |
1da177e4 LT |
811 | * If we do have an sk_buff, reset it so that it's empty. |
812 | * | |
813 | * Note: sk_buffs don't seem to be guaranteed to have any sort | |
814 | * of alignment when they are allocated. Therefore, allocate enough | |
815 | * extra space to make sure that: | |
816 | * | |
817 | * 1. the data does not start in the middle of a cache line. | |
818 | * 2. The data does not end in the middle of a cache line | |
74b0247f | 819 | * 3. The buffer can be aligned such that the IP addresses are |
1da177e4 LT |
820 | * naturally aligned. |
821 | * | |
822 | * Remember, the SOCs MAC writes whole cache lines at a time, | |
823 | * without reading the old contents first. So, if the sk_buff's | |
824 | * data portion starts in the middle of a cache line, the SOC | |
825 | * DMA will trash the beginning (and ending) portions. | |
826 | */ | |
74b0247f | 827 | |
1da177e4 | 828 | if (sb == NULL) { |
789585e9 SH |
829 | sb_new = netdev_alloc_skb(dev, ENET_PACKET_SIZE + |
830 | SMP_CACHE_BYTES * 2 + | |
831 | NET_IP_ALIGN); | |
720a43ef | 832 | if (sb_new == NULL) |
1da177e4 | 833 | return -ENOBUFS; |
1da177e4 | 834 | |
789585e9 | 835 | sbdma_align_skb(sb_new, SMP_CACHE_BYTES, NET_IP_ALIGN); |
1da177e4 LT |
836 | } |
837 | else { | |
838 | sb_new = sb; | |
74b0247f | 839 | /* |
1da177e4 LT |
840 | * nothing special to reinit buffer, it's already aligned |
841 | * and sb->data already points to a good place. | |
842 | */ | |
843 | } | |
74b0247f | 844 | |
1da177e4 | 845 | /* |
74b0247f | 846 | * fill in the descriptor |
1da177e4 | 847 | */ |
74b0247f | 848 | |
1da177e4 LT |
849 | #ifdef CONFIG_SBMAC_COALESCE |
850 | /* | |
851 | * Do not interrupt per DMA transfer. | |
852 | */ | |
689be439 | 853 | dsc->dscr_a = virt_to_phys(sb_new->data) | |
789585e9 | 854 | V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) | 0; |
1da177e4 | 855 | #else |
689be439 | 856 | dsc->dscr_a = virt_to_phys(sb_new->data) | |
789585e9 | 857 | V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) | |
1da177e4 LT |
858 | M_DMA_DSCRA_INTERRUPT; |
859 | #endif | |
860 | ||
861 | /* receiving: no options */ | |
862 | dsc->dscr_b = 0; | |
74b0247f | 863 | |
1da177e4 | 864 | /* |
74b0247f | 865 | * fill in the context |
1da177e4 | 866 | */ |
74b0247f | 867 | |
1da177e4 | 868 | d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new; |
74b0247f RB |
869 | |
870 | /* | |
871 | * point at next packet | |
1da177e4 | 872 | */ |
74b0247f | 873 | |
1da177e4 | 874 | d->sbdma_addptr = nextdsc; |
74b0247f RB |
875 | |
876 | /* | |
1da177e4 LT |
877 | * Give the buffer to the DMA engine. |
878 | */ | |
74b0247f | 879 | |
2039973a | 880 | __raw_writeq(1, d->sbdma_dscrcnt); |
74b0247f | 881 | |
1da177e4 LT |
882 | return 0; /* we did it */ |
883 | } | |
884 | ||
885 | /********************************************************************** | |
886 | * SBDMA_ADD_TXBUFFER(d,sb) | |
74b0247f | 887 | * |
1da177e4 LT |
888 | * Add a transmit buffer to the specified DMA channel, causing a |
889 | * transmit to start. | |
74b0247f RB |
890 | * |
891 | * Input parameters: | |
1da177e4 LT |
892 | * d - DMA channel descriptor |
893 | * sb - sk_buff to add | |
74b0247f | 894 | * |
1da177e4 LT |
895 | * Return value: |
896 | * 0 transmit queued successfully | |
897 | * otherwise error code | |
898 | ********************************************************************* */ | |
899 | ||
900 | ||
73d73969 | 901 | static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *sb) |
1da177e4 | 902 | { |
73d73969 MR |
903 | struct sbdmadscr *dsc; |
904 | struct sbdmadscr *nextdsc; | |
1da177e4 LT |
905 | uint64_t phys; |
906 | uint64_t ncb; | |
907 | int length; | |
74b0247f | 908 | |
1da177e4 | 909 | /* get pointer to our current place in the ring */ |
74b0247f | 910 | |
1da177e4 LT |
911 | dsc = d->sbdma_addptr; |
912 | nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); | |
74b0247f | 913 | |
1da177e4 LT |
914 | /* |
915 | * figure out if the ring is full - if the next descriptor | |
916 | * is the same as the one that we're going to remove from | |
917 | * the ring, the ring is full | |
918 | */ | |
74b0247f | 919 | |
1da177e4 LT |
920 | if (nextdsc == d->sbdma_remptr) { |
921 | return -ENOSPC; | |
922 | } | |
74b0247f | 923 | |
1da177e4 LT |
924 | /* |
925 | * Under Linux, it's not necessary to copy/coalesce buffers | |
926 | * like it is on NetBSD. We think they're all contiguous, | |
927 | * but that may not be true for GBE. | |
928 | */ | |
74b0247f | 929 | |
1da177e4 | 930 | length = sb->len; |
74b0247f | 931 | |
1da177e4 LT |
932 | /* |
933 | * fill in the descriptor. Note that the number of cache | |
934 | * blocks in the descriptor is the number of blocks | |
935 | * *spanned*, so we need to add in the offset (if any) | |
936 | * while doing the calculation. | |
937 | */ | |
74b0247f | 938 | |
1da177e4 LT |
939 | phys = virt_to_phys(sb->data); |
940 | ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1))); | |
941 | ||
74b0247f | 942 | dsc->dscr_a = phys | |
1da177e4 LT |
943 | V_DMA_DSCRA_A_SIZE(ncb) | |
944 | #ifndef CONFIG_SBMAC_COALESCE | |
945 | M_DMA_DSCRA_INTERRUPT | | |
946 | #endif | |
947 | M_DMA_ETHTX_SOP; | |
74b0247f | 948 | |
1da177e4 LT |
949 | /* transmitting: set outbound options and length */ |
950 | ||
951 | dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | | |
952 | V_DMA_DSCRB_PKT_SIZE(length); | |
74b0247f | 953 | |
1da177e4 | 954 | /* |
74b0247f | 955 | * fill in the context |
1da177e4 | 956 | */ |
74b0247f | 957 | |
1da177e4 | 958 | d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb; |
74b0247f RB |
959 | |
960 | /* | |
961 | * point at next packet | |
1da177e4 | 962 | */ |
74b0247f | 963 | |
1da177e4 | 964 | d->sbdma_addptr = nextdsc; |
74b0247f RB |
965 | |
966 | /* | |
1da177e4 LT |
967 | * Give the buffer to the DMA engine. |
968 | */ | |
74b0247f | 969 | |
2039973a | 970 | __raw_writeq(1, d->sbdma_dscrcnt); |
74b0247f | 971 | |
1da177e4 LT |
972 | return 0; /* we did it */ |
973 | } | |
974 | ||
975 | ||
976 | ||
977 | ||
978 | /********************************************************************** | |
979 | * SBDMA_EMPTYRING(d) | |
74b0247f | 980 | * |
1da177e4 | 981 | * Free all allocated sk_buffs on the specified DMA channel; |
74b0247f RB |
982 | * |
983 | * Input parameters: | |
1da177e4 | 984 | * d - DMA channel |
74b0247f | 985 | * |
1da177e4 LT |
986 | * Return value: |
987 | * nothing | |
988 | ********************************************************************* */ | |
989 | ||
73d73969 | 990 | static void sbdma_emptyring(struct sbmacdma *d) |
1da177e4 LT |
991 | { |
992 | int idx; | |
993 | struct sk_buff *sb; | |
74b0247f | 994 | |
1da177e4 LT |
995 | for (idx = 0; idx < d->sbdma_maxdescr; idx++) { |
996 | sb = d->sbdma_ctxtable[idx]; | |
997 | if (sb) { | |
998 | dev_kfree_skb(sb); | |
999 | d->sbdma_ctxtable[idx] = NULL; | |
1000 | } | |
1001 | } | |
1002 | } | |
1003 | ||
1004 | ||
1005 | /********************************************************************** | |
1006 | * SBDMA_FILLRING(d) | |
74b0247f | 1007 | * |
1da177e4 LT |
1008 | * Fill the specified DMA channel (must be receive channel) |
1009 | * with sk_buffs | |
74b0247f RB |
1010 | * |
1011 | * Input parameters: | |
789585e9 SH |
1012 | * sc - softc structure |
1013 | * d - DMA channel | |
74b0247f | 1014 | * |
1da177e4 LT |
1015 | * Return value: |
1016 | * nothing | |
1017 | ********************************************************************* */ | |
1018 | ||
789585e9 | 1019 | static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d) |
1da177e4 LT |
1020 | { |
1021 | int idx; | |
74b0247f | 1022 | |
789585e9 SH |
1023 | for (idx = 0; idx < SBMAC_MAX_RXDESCR - 1; idx++) { |
1024 | if (sbdma_add_rcvbuffer(sc, d, NULL) != 0) | |
1da177e4 LT |
1025 | break; |
1026 | } | |
1027 | } | |
1028 | ||
d6830018 DS |
1029 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1030 | static void sbmac_netpoll(struct net_device *netdev) | |
1031 | { | |
1032 | struct sbmac_softc *sc = netdev_priv(netdev); | |
1033 | int irq = sc->sbm_dev->irq; | |
1034 | ||
1035 | __raw_writeq(0, sc->sbm_imr); | |
1036 | ||
0da2f0f1 | 1037 | sbmac_intr(irq, netdev); |
d6830018 DS |
1038 | |
1039 | #ifdef CONFIG_SBMAC_COALESCE | |
1040 | __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | | |
1041 | ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), | |
1042 | sc->sbm_imr); | |
1043 | #else | |
7d2e3cb7 | 1044 | __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | |
d6830018 DS |
1045 | (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr); |
1046 | #endif | |
1047 | } | |
1048 | #endif | |
1da177e4 LT |
1049 | |
1050 | /********************************************************************** | |
693aa947 | 1051 | * SBDMA_RX_PROCESS(sc,d,work_to_do,poll) |
74b0247f RB |
1052 | * |
1053 | * Process "completed" receive buffers on the specified DMA channel. | |
1da177e4 | 1054 | * |
74b0247f | 1055 | * Input parameters: |
693aa947 MM |
1056 | * sc - softc structure |
1057 | * d - DMA channel context | |
1058 | * work_to_do - no. of packets to process before enabling interrupt | |
1059 | * again (for NAPI) | |
1060 | * poll - 1: using polling (for NAPI) | |
74b0247f | 1061 | * |
1da177e4 LT |
1062 | * Return value: |
1063 | * nothing | |
1064 | ********************************************************************* */ | |
1065 | ||
73d73969 MR |
1066 | static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d, |
1067 | int work_to_do, int poll) | |
1da177e4 | 1068 | { |
09f75cd7 | 1069 | struct net_device *dev = sc->sbm_dev; |
1da177e4 LT |
1070 | int curidx; |
1071 | int hwidx; | |
73d73969 | 1072 | struct sbdmadscr *dsc; |
1da177e4 LT |
1073 | struct sk_buff *sb; |
1074 | int len; | |
693aa947 MM |
1075 | int work_done = 0; |
1076 | int dropped = 0; | |
74b0247f | 1077 | |
693aa947 MM |
1078 | prefetch(d); |
1079 | ||
1080 | again: | |
1081 | /* Check if the HW dropped any frames */ | |
09f75cd7 | 1082 | dev->stats.rx_fifo_errors |
693aa947 MM |
1083 | += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff; |
1084 | __raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost); | |
1085 | ||
1086 | while (work_to_do-- > 0) { | |
74b0247f | 1087 | /* |
1da177e4 LT |
1088 | * figure out where we are (as an index) and where |
1089 | * the hardware is (also as an index) | |
1090 | * | |
74b0247f | 1091 | * This could be done faster if (for example) the |
1da177e4 LT |
1092 | * descriptor table was page-aligned and contiguous in |
1093 | * both virtual and physical memory -- you could then | |
1094 | * just compare the low-order bits of the virtual address | |
1095 | * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) | |
1096 | */ | |
74b0247f | 1097 | |
693aa947 MM |
1098 | dsc = d->sbdma_remptr; |
1099 | curidx = dsc - d->sbdma_dscrtable; | |
1100 | ||
1101 | prefetch(dsc); | |
1102 | prefetch(&d->sbdma_ctxtable[curidx]); | |
1103 | ||
73d73969 MR |
1104 | hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - |
1105 | d->sbdma_dscrtable_phys) / | |
1106 | sizeof(*d->sbdma_dscrtable); | |
74b0247f | 1107 | |
1da177e4 LT |
1108 | /* |
1109 | * If they're the same, that means we've processed all | |
1110 | * of the descriptors up to (but not including) the one that | |
1111 | * the hardware is working on right now. | |
1112 | */ | |
74b0247f | 1113 | |
1da177e4 | 1114 | if (curidx == hwidx) |
693aa947 | 1115 | goto done; |
74b0247f | 1116 | |
1da177e4 LT |
1117 | /* |
1118 | * Otherwise, get the packet's sk_buff ptr back | |
1119 | */ | |
74b0247f | 1120 | |
1da177e4 LT |
1121 | sb = d->sbdma_ctxtable[curidx]; |
1122 | d->sbdma_ctxtable[curidx] = NULL; | |
74b0247f | 1123 | |
1da177e4 | 1124 | len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4; |
74b0247f | 1125 | |
1da177e4 LT |
1126 | /* |
1127 | * Check packet status. If good, process it. | |
1128 | * If not, silently drop it and put it back on the | |
1129 | * receive ring. | |
1130 | */ | |
74b0247f | 1131 | |
693aa947 | 1132 | if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) { |
74b0247f | 1133 | |
1da177e4 LT |
1134 | /* |
1135 | * Add a new buffer to replace the old one. If we fail | |
1136 | * to allocate a buffer, we're going to drop this | |
1137 | * packet and put it right back on the receive ring. | |
1138 | */ | |
74b0247f | 1139 | |
789585e9 SH |
1140 | if (unlikely(sbdma_add_rcvbuffer(sc, d, NULL) == |
1141 | -ENOBUFS)) { | |
09f75cd7 | 1142 | dev->stats.rx_dropped++; |
789585e9 SH |
1143 | /* Re-add old buffer */ |
1144 | sbdma_add_rcvbuffer(sc, d, sb); | |
693aa947 MM |
1145 | /* No point in continuing at the moment */ |
1146 | printk(KERN_ERR "dropped packet (1)\n"); | |
1147 | d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); | |
1148 | goto done; | |
1da177e4 LT |
1149 | } else { |
1150 | /* | |
1151 | * Set length into the packet | |
1152 | */ | |
1153 | skb_put(sb,len); | |
74b0247f | 1154 | |
1da177e4 LT |
1155 | /* |
1156 | * Buffer has been replaced on the | |
1157 | * receive ring. Pass the buffer to | |
1158 | * the kernel | |
1159 | */ | |
1da177e4 LT |
1160 | sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev); |
1161 | /* Check hw IPv4/TCP checksum if supported */ | |
1162 | if (sc->rx_hw_checksum == ENABLE) { | |
1163 | if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) && | |
1164 | !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) { | |
1165 | sb->ip_summed = CHECKSUM_UNNECESSARY; | |
1166 | /* don't need to set sb->csum */ | |
1167 | } else { | |
bc8acf2c | 1168 | skb_checksum_none_assert(sb); |
1da177e4 LT |
1169 | } |
1170 | } | |
693aa947 MM |
1171 | prefetch(sb->data); |
1172 | prefetch((const void *)(((char *)sb->data)+32)); | |
1173 | if (poll) | |
1174 | dropped = netif_receive_skb(sb); | |
1175 | else | |
1176 | dropped = netif_rx(sb); | |
1177 | ||
1178 | if (dropped == NET_RX_DROP) { | |
09f75cd7 | 1179 | dev->stats.rx_dropped++; |
693aa947 MM |
1180 | d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); |
1181 | goto done; | |
1182 | } | |
1183 | else { | |
09f75cd7 JG |
1184 | dev->stats.rx_bytes += len; |
1185 | dev->stats.rx_packets++; | |
693aa947 | 1186 | } |
1da177e4 LT |
1187 | } |
1188 | } else { | |
1189 | /* | |
1190 | * Packet was mangled somehow. Just drop it and | |
1191 | * put it back on the receive ring. | |
1192 | */ | |
09f75cd7 | 1193 | dev->stats.rx_errors++; |
789585e9 | 1194 | sbdma_add_rcvbuffer(sc, d, sb); |
1da177e4 | 1195 | } |
74b0247f RB |
1196 | |
1197 | ||
1198 | /* | |
1da177e4 LT |
1199 | * .. and advance to the next buffer. |
1200 | */ | |
74b0247f | 1201 | |
1da177e4 | 1202 | d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); |
693aa947 MM |
1203 | work_done++; |
1204 | } | |
1205 | if (!poll) { | |
1206 | work_to_do = 32; | |
1207 | goto again; /* collect fifo drop statistics again */ | |
1da177e4 | 1208 | } |
693aa947 MM |
1209 | done: |
1210 | return work_done; | |
1da177e4 LT |
1211 | } |
1212 | ||
1da177e4 LT |
1213 | /********************************************************************** |
1214 | * SBDMA_TX_PROCESS(sc,d) | |
74b0247f RB |
1215 | * |
1216 | * Process "completed" transmit buffers on the specified DMA channel. | |
1da177e4 LT |
1217 | * This is normally called within the interrupt service routine. |
1218 | * Note that this isn't really ideal for priority channels, since | |
74b0247f RB |
1219 | * it processes all of the packets on a given channel before |
1220 | * returning. | |
1da177e4 | 1221 | * |
74b0247f | 1222 | * Input parameters: |
1da177e4 | 1223 | * sc - softc structure |
693aa947 MM |
1224 | * d - DMA channel context |
1225 | * poll - 1: using polling (for NAPI) | |
74b0247f | 1226 | * |
1da177e4 LT |
1227 | * Return value: |
1228 | * nothing | |
1229 | ********************************************************************* */ | |
1230 | ||
73d73969 MR |
1231 | static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d, |
1232 | int poll) | |
1da177e4 | 1233 | { |
09f75cd7 | 1234 | struct net_device *dev = sc->sbm_dev; |
1da177e4 LT |
1235 | int curidx; |
1236 | int hwidx; | |
73d73969 | 1237 | struct sbdmadscr *dsc; |
1da177e4 LT |
1238 | struct sk_buff *sb; |
1239 | unsigned long flags; | |
693aa947 | 1240 | int packets_handled = 0; |
1da177e4 LT |
1241 | |
1242 | spin_lock_irqsave(&(sc->sbm_lock), flags); | |
74b0247f | 1243 | |
693aa947 MM |
1244 | if (d->sbdma_remptr == d->sbdma_addptr) |
1245 | goto end_unlock; | |
1246 | ||
73d73969 MR |
1247 | hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - |
1248 | d->sbdma_dscrtable_phys) / sizeof(*d->sbdma_dscrtable); | |
693aa947 | 1249 | |
1da177e4 | 1250 | for (;;) { |
74b0247f | 1251 | /* |
1da177e4 LT |
1252 | * figure out where we are (as an index) and where |
1253 | * the hardware is (also as an index) | |
1254 | * | |
74b0247f | 1255 | * This could be done faster if (for example) the |
1da177e4 LT |
1256 | * descriptor table was page-aligned and contiguous in |
1257 | * both virtual and physical memory -- you could then | |
1258 | * just compare the low-order bits of the virtual address | |
1259 | * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) | |
1260 | */ | |
74b0247f | 1261 | |
1da177e4 | 1262 | curidx = d->sbdma_remptr - d->sbdma_dscrtable; |
1da177e4 LT |
1263 | |
1264 | /* | |
1265 | * If they're the same, that means we've processed all | |
1266 | * of the descriptors up to (but not including) the one that | |
1267 | * the hardware is working on right now. | |
1268 | */ | |
74b0247f | 1269 | |
1da177e4 LT |
1270 | if (curidx == hwidx) |
1271 | break; | |
74b0247f | 1272 | |
1da177e4 LT |
1273 | /* |
1274 | * Otherwise, get the packet's sk_buff ptr back | |
1275 | */ | |
74b0247f | 1276 | |
1da177e4 LT |
1277 | dsc = &(d->sbdma_dscrtable[curidx]); |
1278 | sb = d->sbdma_ctxtable[curidx]; | |
1279 | d->sbdma_ctxtable[curidx] = NULL; | |
74b0247f | 1280 | |
1da177e4 LT |
1281 | /* |
1282 | * Stats | |
1283 | */ | |
74b0247f | 1284 | |
09f75cd7 JG |
1285 | dev->stats.tx_bytes += sb->len; |
1286 | dev->stats.tx_packets++; | |
74b0247f | 1287 | |
1da177e4 LT |
1288 | /* |
1289 | * for transmits, we just free buffers. | |
1290 | */ | |
74b0247f | 1291 | |
1da177e4 | 1292 | dev_kfree_skb_irq(sb); |
74b0247f RB |
1293 | |
1294 | /* | |
1da177e4 LT |
1295 | * .. and advance to the next buffer. |
1296 | */ | |
1297 | ||
1298 | d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); | |
74b0247f | 1299 | |
693aa947 MM |
1300 | packets_handled++; |
1301 | ||
1da177e4 | 1302 | } |
74b0247f | 1303 | |
1da177e4 LT |
1304 | /* |
1305 | * Decide if we should wake up the protocol or not. | |
1306 | * Other drivers seem to do this when we reach a low | |
1307 | * watermark on the transmit queue. | |
1308 | */ | |
74b0247f | 1309 | |
693aa947 MM |
1310 | if (packets_handled) |
1311 | netif_wake_queue(d->sbdma_eth->sbm_dev); | |
74b0247f | 1312 | |
693aa947 | 1313 | end_unlock: |
1da177e4 | 1314 | spin_unlock_irqrestore(&(sc->sbm_lock), flags); |
74b0247f | 1315 | |
1da177e4 LT |
1316 | } |
1317 | ||
1318 | ||
1319 | ||
1320 | /********************************************************************** | |
1321 | * SBMAC_INITCTX(s) | |
74b0247f | 1322 | * |
1da177e4 LT |
1323 | * Initialize an Ethernet context structure - this is called |
1324 | * once per MAC on the 1250. Memory is allocated here, so don't | |
1325 | * call it again from inside the ioctl routines that bring the | |
1326 | * interface up/down | |
74b0247f RB |
1327 | * |
1328 | * Input parameters: | |
1da177e4 | 1329 | * s - sbmac context structure |
74b0247f | 1330 | * |
1da177e4 LT |
1331 | * Return value: |
1332 | * 0 | |
1333 | ********************************************************************* */ | |
1334 | ||
1335 | static int sbmac_initctx(struct sbmac_softc *s) | |
1336 | { | |
74b0247f RB |
1337 | |
1338 | /* | |
1339 | * figure out the addresses of some ports | |
1da177e4 | 1340 | */ |
74b0247f | 1341 | |
1da177e4 LT |
1342 | s->sbm_macenable = s->sbm_base + R_MAC_ENABLE; |
1343 | s->sbm_maccfg = s->sbm_base + R_MAC_CFG; | |
1344 | s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG; | |
1345 | s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG; | |
1346 | s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG; | |
1347 | s->sbm_isr = s->sbm_base + R_MAC_STATUS; | |
1348 | s->sbm_imr = s->sbm_base + R_MAC_INT_MASK; | |
1349 | s->sbm_mdio = s->sbm_base + R_MAC_MDIO; | |
1350 | ||
1da177e4 LT |
1351 | /* |
1352 | * Initialize the DMA channels. Right now, only one per MAC is used | |
1353 | * Note: Only do this _once_, as it allocates memory from the kernel! | |
1354 | */ | |
74b0247f | 1355 | |
1da177e4 LT |
1356 | sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR); |
1357 | sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR); | |
74b0247f | 1358 | |
1da177e4 LT |
1359 | /* |
1360 | * initial state is OFF | |
1361 | */ | |
74b0247f | 1362 | |
1da177e4 | 1363 | s->sbm_state = sbmac_state_off; |
74b0247f | 1364 | |
1da177e4 LT |
1365 | return 0; |
1366 | } | |
1367 | ||
1368 | ||
73d73969 | 1369 | static void sbdma_uninitctx(struct sbmacdma *d) |
1da177e4 | 1370 | { |
693aa947 MM |
1371 | if (d->sbdma_dscrtable_unaligned) { |
1372 | kfree(d->sbdma_dscrtable_unaligned); | |
1373 | d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL; | |
1da177e4 | 1374 | } |
74b0247f | 1375 | |
1da177e4 LT |
1376 | if (d->sbdma_ctxtable) { |
1377 | kfree(d->sbdma_ctxtable); | |
1378 | d->sbdma_ctxtable = NULL; | |
1379 | } | |
1380 | } | |
1381 | ||
1382 | ||
1383 | static void sbmac_uninitctx(struct sbmac_softc *sc) | |
1384 | { | |
1385 | sbdma_uninitctx(&(sc->sbm_txdma)); | |
1386 | sbdma_uninitctx(&(sc->sbm_rxdma)); | |
1387 | } | |
1388 | ||
1389 | ||
1390 | /********************************************************************** | |
1391 | * SBMAC_CHANNEL_START(s) | |
74b0247f | 1392 | * |
1da177e4 | 1393 | * Start packet processing on this MAC. |
74b0247f RB |
1394 | * |
1395 | * Input parameters: | |
1da177e4 | 1396 | * s - sbmac structure |
74b0247f | 1397 | * |
1da177e4 LT |
1398 | * Return value: |
1399 | * nothing | |
1400 | ********************************************************************* */ | |
1401 | ||
1402 | static void sbmac_channel_start(struct sbmac_softc *s) | |
1403 | { | |
1404 | uint64_t reg; | |
73d73969 | 1405 | void __iomem *port; |
1da177e4 LT |
1406 | uint64_t cfg,fifo,framecfg; |
1407 | int idx, th_value; | |
74b0247f | 1408 | |
1da177e4 LT |
1409 | /* |
1410 | * Don't do this if running | |
1411 | */ | |
1412 | ||
1413 | if (s->sbm_state == sbmac_state_on) | |
1414 | return; | |
74b0247f | 1415 | |
1da177e4 LT |
1416 | /* |
1417 | * Bring the controller out of reset, but leave it off. | |
1418 | */ | |
74b0247f | 1419 | |
2039973a | 1420 | __raw_writeq(0, s->sbm_macenable); |
74b0247f | 1421 | |
1da177e4 LT |
1422 | /* |
1423 | * Ignore all received packets | |
1424 | */ | |
74b0247f | 1425 | |
2039973a | 1426 | __raw_writeq(0, s->sbm_rxfilter); |
74b0247f RB |
1427 | |
1428 | /* | |
1da177e4 LT |
1429 | * Calculate values for various control registers. |
1430 | */ | |
74b0247f | 1431 | |
1da177e4 | 1432 | cfg = M_MAC_RETRY_EN | |
74b0247f | 1433 | M_MAC_TX_HOLD_SOP_EN | |
1da177e4 LT |
1434 | V_MAC_TX_PAUSE_CNT_16K | |
1435 | M_MAC_AP_STAT_EN | | |
1436 | M_MAC_FAST_SYNC | | |
1437 | M_MAC_SS_EN | | |
1438 | 0; | |
74b0247f RB |
1439 | |
1440 | /* | |
1da177e4 LT |
1441 | * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars |
1442 | * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above | |
1443 | * Use a larger RD_THRSH for gigabit | |
1444 | */ | |
f90fdc3c | 1445 | if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) |
1da177e4 | 1446 | th_value = 28; |
f90fdc3c RB |
1447 | else |
1448 | th_value = 64; | |
1da177e4 LT |
1449 | |
1450 | fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */ | |
1451 | ((s->sbm_speed == sbmac_speed_1000) | |
1452 | ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) | | |
1453 | V_MAC_TX_RL_THRSH(4) | | |
1454 | V_MAC_RX_PL_THRSH(4) | | |
1455 | V_MAC_RX_RD_THRSH(4) | /* Must be '4' */ | |
1da177e4 LT |
1456 | V_MAC_RX_RL_THRSH(8) | |
1457 | 0; | |
1458 | ||
1459 | framecfg = V_MAC_MIN_FRAMESZ_DEFAULT | | |
1460 | V_MAC_MAX_FRAMESZ_DEFAULT | | |
1461 | V_MAC_BACKOFF_SEL(1); | |
1462 | ||
1463 | /* | |
74b0247f | 1464 | * Clear out the hash address map |
1da177e4 | 1465 | */ |
74b0247f | 1466 | |
1da177e4 LT |
1467 | port = s->sbm_base + R_MAC_HASH_BASE; |
1468 | for (idx = 0; idx < MAC_HASH_COUNT; idx++) { | |
2039973a | 1469 | __raw_writeq(0, port); |
1da177e4 LT |
1470 | port += sizeof(uint64_t); |
1471 | } | |
74b0247f | 1472 | |
1da177e4 LT |
1473 | /* |
1474 | * Clear out the exact-match table | |
1475 | */ | |
74b0247f | 1476 | |
1da177e4 LT |
1477 | port = s->sbm_base + R_MAC_ADDR_BASE; |
1478 | for (idx = 0; idx < MAC_ADDR_COUNT; idx++) { | |
2039973a | 1479 | __raw_writeq(0, port); |
1da177e4 LT |
1480 | port += sizeof(uint64_t); |
1481 | } | |
74b0247f | 1482 | |
1da177e4 LT |
1483 | /* |
1484 | * Clear out the DMA Channel mapping table registers | |
1485 | */ | |
74b0247f | 1486 | |
1da177e4 LT |
1487 | port = s->sbm_base + R_MAC_CHUP0_BASE; |
1488 | for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { | |
2039973a | 1489 | __raw_writeq(0, port); |
1da177e4 LT |
1490 | port += sizeof(uint64_t); |
1491 | } | |
1492 | ||
1493 | ||
1494 | port = s->sbm_base + R_MAC_CHLO0_BASE; | |
1495 | for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { | |
2039973a | 1496 | __raw_writeq(0, port); |
1da177e4 LT |
1497 | port += sizeof(uint64_t); |
1498 | } | |
74b0247f | 1499 | |
1da177e4 LT |
1500 | /* |
1501 | * Program the hardware address. It goes into the hardware-address | |
1502 | * register as well as the first filter register. | |
1503 | */ | |
74b0247f | 1504 | |
1da177e4 | 1505 | reg = sbmac_addr2reg(s->sbm_hwaddr); |
74b0247f | 1506 | |
1da177e4 | 1507 | port = s->sbm_base + R_MAC_ADDR_BASE; |
2039973a | 1508 | __raw_writeq(reg, port); |
1da177e4 LT |
1509 | port = s->sbm_base + R_MAC_ETHERNET_ADDR; |
1510 | ||
2039973a | 1511 | __raw_writeq(reg, port); |
74b0247f | 1512 | |
1da177e4 LT |
1513 | /* |
1514 | * Set the receive filter for no packets, and write values | |
1515 | * to the various config registers | |
1516 | */ | |
74b0247f | 1517 | |
2039973a RB |
1518 | __raw_writeq(0, s->sbm_rxfilter); |
1519 | __raw_writeq(0, s->sbm_imr); | |
1520 | __raw_writeq(framecfg, s->sbm_framecfg); | |
1521 | __raw_writeq(fifo, s->sbm_fifocfg); | |
1522 | __raw_writeq(cfg, s->sbm_maccfg); | |
74b0247f | 1523 | |
1da177e4 LT |
1524 | /* |
1525 | * Initialize DMA channels (rings should be ok now) | |
1526 | */ | |
74b0247f | 1527 | |
1da177e4 LT |
1528 | sbdma_channel_start(&(s->sbm_rxdma), DMA_RX); |
1529 | sbdma_channel_start(&(s->sbm_txdma), DMA_TX); | |
74b0247f | 1530 | |
1da177e4 LT |
1531 | /* |
1532 | * Configure the speed, duplex, and flow control | |
1533 | */ | |
1534 | ||
1535 | sbmac_set_speed(s,s->sbm_speed); | |
1536 | sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc); | |
74b0247f | 1537 | |
1da177e4 LT |
1538 | /* |
1539 | * Fill the receive ring | |
1540 | */ | |
74b0247f | 1541 | |
789585e9 | 1542 | sbdma_fillring(s, &(s->sbm_rxdma)); |
74b0247f RB |
1543 | |
1544 | /* | |
1da177e4 | 1545 | * Turn on the rest of the bits in the enable register |
74b0247f RB |
1546 | */ |
1547 | ||
f90fdc3c RB |
1548 | #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) |
1549 | __raw_writeq(M_MAC_RXDMA_EN0 | | |
1550 | M_MAC_TXDMA_EN0, s->sbm_macenable); | |
1551 | #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) | |
2039973a | 1552 | __raw_writeq(M_MAC_RXDMA_EN0 | |
1da177e4 LT |
1553 | M_MAC_TXDMA_EN0 | |
1554 | M_MAC_RX_ENABLE | | |
2039973a | 1555 | M_MAC_TX_ENABLE, s->sbm_macenable); |
f90fdc3c | 1556 | #else |
0b1974de | 1557 | #error invalid SiByte MAC configuration |
f90fdc3c | 1558 | #endif |
1da177e4 LT |
1559 | |
1560 | #ifdef CONFIG_SBMAC_COALESCE | |
2039973a RB |
1561 | __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | |
1562 | ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr); | |
1da177e4 | 1563 | #else |
2039973a RB |
1564 | __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | |
1565 | (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr); | |
1da177e4 | 1566 | #endif |
74b0247f RB |
1567 | |
1568 | /* | |
1569 | * Enable receiving unicasts and broadcasts | |
1da177e4 | 1570 | */ |
74b0247f | 1571 | |
2039973a | 1572 | __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter); |
74b0247f | 1573 | |
1da177e4 | 1574 | /* |
74b0247f | 1575 | * we're running now. |
1da177e4 | 1576 | */ |
74b0247f | 1577 | |
1da177e4 | 1578 | s->sbm_state = sbmac_state_on; |
74b0247f RB |
1579 | |
1580 | /* | |
1581 | * Program multicast addresses | |
1da177e4 | 1582 | */ |
74b0247f | 1583 | |
1da177e4 | 1584 | sbmac_setmulti(s); |
74b0247f RB |
1585 | |
1586 | /* | |
1587 | * If channel was in promiscuous mode before, turn that on | |
1da177e4 | 1588 | */ |
74b0247f | 1589 | |
1da177e4 LT |
1590 | if (s->sbm_devflags & IFF_PROMISC) { |
1591 | sbmac_promiscuous_mode(s,1); | |
1592 | } | |
74b0247f | 1593 | |
1da177e4 LT |
1594 | } |
1595 | ||
1596 | ||
1597 | /********************************************************************** | |
1598 | * SBMAC_CHANNEL_STOP(s) | |
74b0247f | 1599 | * |
1da177e4 | 1600 | * Stop packet processing on this MAC. |
74b0247f RB |
1601 | * |
1602 | * Input parameters: | |
1da177e4 | 1603 | * s - sbmac structure |
74b0247f | 1604 | * |
1da177e4 LT |
1605 | * Return value: |
1606 | * nothing | |
1607 | ********************************************************************* */ | |
1608 | ||
1609 | static void sbmac_channel_stop(struct sbmac_softc *s) | |
1610 | { | |
1611 | /* don't do this if already stopped */ | |
74b0247f | 1612 | |
1da177e4 LT |
1613 | if (s->sbm_state == sbmac_state_off) |
1614 | return; | |
74b0247f | 1615 | |
1da177e4 | 1616 | /* don't accept any packets, disable all interrupts */ |
74b0247f | 1617 | |
2039973a RB |
1618 | __raw_writeq(0, s->sbm_rxfilter); |
1619 | __raw_writeq(0, s->sbm_imr); | |
74b0247f | 1620 | |
1da177e4 | 1621 | /* Turn off ticker */ |
74b0247f | 1622 | |
1da177e4 | 1623 | /* XXX */ |
74b0247f | 1624 | |
1da177e4 | 1625 | /* turn off receiver and transmitter */ |
74b0247f | 1626 | |
2039973a | 1627 | __raw_writeq(0, s->sbm_macenable); |
74b0247f | 1628 | |
1da177e4 | 1629 | /* We're stopped now. */ |
74b0247f | 1630 | |
1da177e4 | 1631 | s->sbm_state = sbmac_state_off; |
74b0247f | 1632 | |
1da177e4 LT |
1633 | /* |
1634 | * Stop DMA channels (rings should be ok now) | |
1635 | */ | |
74b0247f | 1636 | |
1da177e4 LT |
1637 | sbdma_channel_stop(&(s->sbm_rxdma)); |
1638 | sbdma_channel_stop(&(s->sbm_txdma)); | |
74b0247f | 1639 | |
1da177e4 | 1640 | /* Empty the receive and transmit rings */ |
74b0247f | 1641 | |
1da177e4 LT |
1642 | sbdma_emptyring(&(s->sbm_rxdma)); |
1643 | sbdma_emptyring(&(s->sbm_txdma)); | |
74b0247f | 1644 | |
1da177e4 LT |
1645 | } |
1646 | ||
1647 | /********************************************************************** | |
1648 | * SBMAC_SET_CHANNEL_STATE(state) | |
74b0247f | 1649 | * |
1da177e4 | 1650 | * Set the channel's state ON or OFF |
74b0247f RB |
1651 | * |
1652 | * Input parameters: | |
1da177e4 | 1653 | * state - new state |
74b0247f | 1654 | * |
1da177e4 LT |
1655 | * Return value: |
1656 | * old state | |
1657 | ********************************************************************* */ | |
73d73969 MR |
1658 | static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *sc, |
1659 | enum sbmac_state state) | |
1da177e4 | 1660 | { |
73d73969 | 1661 | enum sbmac_state oldstate = sc->sbm_state; |
74b0247f | 1662 | |
1da177e4 LT |
1663 | /* |
1664 | * If same as previous state, return | |
1665 | */ | |
74b0247f | 1666 | |
1da177e4 LT |
1667 | if (state == oldstate) { |
1668 | return oldstate; | |
1669 | } | |
74b0247f | 1670 | |
1da177e4 | 1671 | /* |
74b0247f | 1672 | * If new state is ON, turn channel on |
1da177e4 | 1673 | */ |
74b0247f | 1674 | |
1da177e4 LT |
1675 | if (state == sbmac_state_on) { |
1676 | sbmac_channel_start(sc); | |
1677 | } | |
1678 | else { | |
1679 | sbmac_channel_stop(sc); | |
1680 | } | |
74b0247f | 1681 | |
1da177e4 LT |
1682 | /* |
1683 | * Return previous state | |
1684 | */ | |
74b0247f | 1685 | |
1da177e4 LT |
1686 | return oldstate; |
1687 | } | |
1688 | ||
1689 | ||
1690 | /********************************************************************** | |
1691 | * SBMAC_PROMISCUOUS_MODE(sc,onoff) | |
74b0247f | 1692 | * |
1da177e4 | 1693 | * Turn on or off promiscuous mode |
74b0247f RB |
1694 | * |
1695 | * Input parameters: | |
1da177e4 LT |
1696 | * sc - softc |
1697 | * onoff - 1 to turn on, 0 to turn off | |
74b0247f | 1698 | * |
1da177e4 LT |
1699 | * Return value: |
1700 | * nothing | |
1701 | ********************************************************************* */ | |
1702 | ||
1703 | static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff) | |
1704 | { | |
1705 | uint64_t reg; | |
74b0247f | 1706 | |
1da177e4 LT |
1707 | if (sc->sbm_state != sbmac_state_on) |
1708 | return; | |
74b0247f | 1709 | |
1da177e4 | 1710 | if (onoff) { |
2039973a | 1711 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 1712 | reg |= M_MAC_ALLPKT_EN; |
2039973a | 1713 | __raw_writeq(reg, sc->sbm_rxfilter); |
74b0247f | 1714 | } |
1da177e4 | 1715 | else { |
2039973a | 1716 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 1717 | reg &= ~M_MAC_ALLPKT_EN; |
2039973a | 1718 | __raw_writeq(reg, sc->sbm_rxfilter); |
1da177e4 LT |
1719 | } |
1720 | } | |
1721 | ||
1722 | /********************************************************************** | |
1723 | * SBMAC_SETIPHDR_OFFSET(sc,onoff) | |
74b0247f | 1724 | * |
1da177e4 | 1725 | * Set the iphdr offset as 15 assuming ethernet encapsulation |
74b0247f RB |
1726 | * |
1727 | * Input parameters: | |
1da177e4 | 1728 | * sc - softc |
74b0247f | 1729 | * |
1da177e4 LT |
1730 | * Return value: |
1731 | * nothing | |
1732 | ********************************************************************* */ | |
1733 | ||
1734 | static void sbmac_set_iphdr_offset(struct sbmac_softc *sc) | |
1735 | { | |
1736 | uint64_t reg; | |
74b0247f | 1737 | |
1da177e4 | 1738 | /* Hard code the off set to 15 for now */ |
2039973a | 1739 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 1740 | reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15); |
2039973a | 1741 | __raw_writeq(reg, sc->sbm_rxfilter); |
74b0247f | 1742 | |
f90fdc3c RB |
1743 | /* BCM1250 pass1 didn't have hardware checksum. Everything |
1744 | later does. */ | |
1745 | if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) { | |
1da177e4 | 1746 | sc->rx_hw_checksum = DISABLE; |
f90fdc3c RB |
1747 | } else { |
1748 | sc->rx_hw_checksum = ENABLE; | |
1da177e4 LT |
1749 | } |
1750 | } | |
1751 | ||
1752 | ||
1753 | /********************************************************************** | |
1754 | * SBMAC_ADDR2REG(ptr) | |
74b0247f | 1755 | * |
1da177e4 LT |
1756 | * Convert six bytes into the 64-bit register value that |
1757 | * we typically write into the SBMAC's address/mcast registers | |
74b0247f RB |
1758 | * |
1759 | * Input parameters: | |
1da177e4 | 1760 | * ptr - pointer to 6 bytes |
74b0247f | 1761 | * |
1da177e4 LT |
1762 | * Return value: |
1763 | * register value | |
1764 | ********************************************************************* */ | |
1765 | ||
1766 | static uint64_t sbmac_addr2reg(unsigned char *ptr) | |
1767 | { | |
1768 | uint64_t reg = 0; | |
74b0247f | 1769 | |
1da177e4 | 1770 | ptr += 6; |
74b0247f RB |
1771 | |
1772 | reg |= (uint64_t) *(--ptr); | |
1da177e4 | 1773 | reg <<= 8; |
74b0247f | 1774 | reg |= (uint64_t) *(--ptr); |
1da177e4 | 1775 | reg <<= 8; |
74b0247f | 1776 | reg |= (uint64_t) *(--ptr); |
1da177e4 | 1777 | reg <<= 8; |
74b0247f | 1778 | reg |= (uint64_t) *(--ptr); |
1da177e4 | 1779 | reg <<= 8; |
74b0247f | 1780 | reg |= (uint64_t) *(--ptr); |
1da177e4 | 1781 | reg <<= 8; |
74b0247f RB |
1782 | reg |= (uint64_t) *(--ptr); |
1783 | ||
1da177e4 LT |
1784 | return reg; |
1785 | } | |
1786 | ||
1787 | ||
1788 | /********************************************************************** | |
1789 | * SBMAC_SET_SPEED(s,speed) | |
74b0247f | 1790 | * |
1da177e4 LT |
1791 | * Configure LAN speed for the specified MAC. |
1792 | * Warning: must be called when MAC is off! | |
74b0247f RB |
1793 | * |
1794 | * Input parameters: | |
1da177e4 | 1795 | * s - sbmac structure |
73d73969 | 1796 | * speed - speed to set MAC to (see enum sbmac_speed) |
74b0247f | 1797 | * |
1da177e4 LT |
1798 | * Return value: |
1799 | * 1 if successful | |
1800 | * 0 indicates invalid parameters | |
1801 | ********************************************************************* */ | |
1802 | ||
73d73969 | 1803 | static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed) |
1da177e4 LT |
1804 | { |
1805 | uint64_t cfg; | |
1806 | uint64_t framecfg; | |
1807 | ||
1808 | /* | |
1809 | * Save new current values | |
1810 | */ | |
74b0247f | 1811 | |
1da177e4 | 1812 | s->sbm_speed = speed; |
74b0247f | 1813 | |
1da177e4 LT |
1814 | if (s->sbm_state == sbmac_state_on) |
1815 | return 0; /* save for next restart */ | |
1816 | ||
1817 | /* | |
74b0247f | 1818 | * Read current register values |
1da177e4 | 1819 | */ |
74b0247f | 1820 | |
2039973a RB |
1821 | cfg = __raw_readq(s->sbm_maccfg); |
1822 | framecfg = __raw_readq(s->sbm_framecfg); | |
74b0247f | 1823 | |
1da177e4 LT |
1824 | /* |
1825 | * Mask out the stuff we want to change | |
1826 | */ | |
74b0247f | 1827 | |
1da177e4 LT |
1828 | cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL); |
1829 | framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH | | |
1830 | M_MAC_SLOT_SIZE); | |
74b0247f | 1831 | |
1da177e4 LT |
1832 | /* |
1833 | * Now add in the new bits | |
1834 | */ | |
74b0247f | 1835 | |
1da177e4 LT |
1836 | switch (speed) { |
1837 | case sbmac_speed_10: | |
1838 | framecfg |= V_MAC_IFG_RX_10 | | |
1839 | V_MAC_IFG_TX_10 | | |
1840 | K_MAC_IFG_THRSH_10 | | |
1841 | V_MAC_SLOT_SIZE_10; | |
1842 | cfg |= V_MAC_SPEED_SEL_10MBPS; | |
1843 | break; | |
74b0247f | 1844 | |
1da177e4 LT |
1845 | case sbmac_speed_100: |
1846 | framecfg |= V_MAC_IFG_RX_100 | | |
1847 | V_MAC_IFG_TX_100 | | |
1848 | V_MAC_IFG_THRSH_100 | | |
1849 | V_MAC_SLOT_SIZE_100; | |
1850 | cfg |= V_MAC_SPEED_SEL_100MBPS ; | |
1851 | break; | |
74b0247f | 1852 | |
1da177e4 LT |
1853 | case sbmac_speed_1000: |
1854 | framecfg |= V_MAC_IFG_RX_1000 | | |
1855 | V_MAC_IFG_TX_1000 | | |
1856 | V_MAC_IFG_THRSH_1000 | | |
1857 | V_MAC_SLOT_SIZE_1000; | |
1858 | cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; | |
1859 | break; | |
74b0247f | 1860 | |
1da177e4 LT |
1861 | default: |
1862 | return 0; | |
1863 | } | |
74b0247f | 1864 | |
1da177e4 | 1865 | /* |
74b0247f | 1866 | * Send the bits back to the hardware |
1da177e4 | 1867 | */ |
74b0247f | 1868 | |
2039973a RB |
1869 | __raw_writeq(framecfg, s->sbm_framecfg); |
1870 | __raw_writeq(cfg, s->sbm_maccfg); | |
74b0247f | 1871 | |
1da177e4 LT |
1872 | return 1; |
1873 | } | |
1874 | ||
1875 | /********************************************************************** | |
1876 | * SBMAC_SET_DUPLEX(s,duplex,fc) | |
74b0247f | 1877 | * |
1da177e4 LT |
1878 | * Set Ethernet duplex and flow control options for this MAC |
1879 | * Warning: must be called when MAC is off! | |
74b0247f RB |
1880 | * |
1881 | * Input parameters: | |
1da177e4 | 1882 | * s - sbmac structure |
73d73969 MR |
1883 | * duplex - duplex setting (see enum sbmac_duplex) |
1884 | * fc - flow control setting (see enum sbmac_fc) | |
74b0247f | 1885 | * |
1da177e4 LT |
1886 | * Return value: |
1887 | * 1 if ok | |
1888 | * 0 if an invalid parameter combination was specified | |
1889 | ********************************************************************* */ | |
1890 | ||
73d73969 MR |
1891 | static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex, |
1892 | enum sbmac_fc fc) | |
1da177e4 LT |
1893 | { |
1894 | uint64_t cfg; | |
74b0247f | 1895 | |
1da177e4 LT |
1896 | /* |
1897 | * Save new current values | |
1898 | */ | |
74b0247f | 1899 | |
1da177e4 LT |
1900 | s->sbm_duplex = duplex; |
1901 | s->sbm_fc = fc; | |
74b0247f | 1902 | |
1da177e4 LT |
1903 | if (s->sbm_state == sbmac_state_on) |
1904 | return 0; /* save for next restart */ | |
74b0247f | 1905 | |
1da177e4 | 1906 | /* |
74b0247f | 1907 | * Read current register values |
1da177e4 | 1908 | */ |
74b0247f | 1909 | |
2039973a | 1910 | cfg = __raw_readq(s->sbm_maccfg); |
74b0247f | 1911 | |
1da177e4 LT |
1912 | /* |
1913 | * Mask off the stuff we're about to change | |
1914 | */ | |
74b0247f | 1915 | |
1da177e4 | 1916 | cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN); |
74b0247f RB |
1917 | |
1918 | ||
1da177e4 LT |
1919 | switch (duplex) { |
1920 | case sbmac_duplex_half: | |
1921 | switch (fc) { | |
1922 | case sbmac_fc_disabled: | |
1923 | cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED; | |
1924 | break; | |
74b0247f | 1925 | |
1da177e4 LT |
1926 | case sbmac_fc_collision: |
1927 | cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED; | |
1928 | break; | |
74b0247f | 1929 | |
1da177e4 LT |
1930 | case sbmac_fc_carrier: |
1931 | cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; | |
1932 | break; | |
74b0247f | 1933 | |
1da177e4 LT |
1934 | case sbmac_fc_frame: /* not valid in half duplex */ |
1935 | default: /* invalid selection */ | |
1936 | return 0; | |
1937 | } | |
1938 | break; | |
74b0247f | 1939 | |
1da177e4 LT |
1940 | case sbmac_duplex_full: |
1941 | switch (fc) { | |
1942 | case sbmac_fc_disabled: | |
1943 | cfg |= V_MAC_FC_CMD_DISABLED; | |
1944 | break; | |
74b0247f | 1945 | |
1da177e4 LT |
1946 | case sbmac_fc_frame: |
1947 | cfg |= V_MAC_FC_CMD_ENABLED; | |
1948 | break; | |
74b0247f | 1949 | |
1da177e4 LT |
1950 | case sbmac_fc_collision: /* not valid in full duplex */ |
1951 | case sbmac_fc_carrier: /* not valid in full duplex */ | |
1da177e4 LT |
1952 | default: |
1953 | return 0; | |
1954 | } | |
1955 | break; | |
f5279ffd MR |
1956 | default: |
1957 | return 0; | |
1da177e4 | 1958 | } |
74b0247f | 1959 | |
1da177e4 | 1960 | /* |
74b0247f | 1961 | * Send the bits back to the hardware |
1da177e4 | 1962 | */ |
74b0247f | 1963 | |
2039973a | 1964 | __raw_writeq(cfg, s->sbm_maccfg); |
74b0247f | 1965 | |
1da177e4 LT |
1966 | return 1; |
1967 | } | |
1968 | ||
1969 | ||
1970 | ||
1971 | ||
1972 | /********************************************************************** | |
1973 | * SBMAC_INTR() | |
74b0247f | 1974 | * |
1da177e4 | 1975 | * Interrupt handler for MAC interrupts |
74b0247f RB |
1976 | * |
1977 | * Input parameters: | |
1da177e4 | 1978 | * MAC structure |
74b0247f | 1979 | * |
1da177e4 LT |
1980 | * Return value: |
1981 | * nothing | |
1982 | ********************************************************************* */ | |
7d12e780 | 1983 | static irqreturn_t sbmac_intr(int irq,void *dev_instance) |
1da177e4 LT |
1984 | { |
1985 | struct net_device *dev = (struct net_device *) dev_instance; | |
1986 | struct sbmac_softc *sc = netdev_priv(dev); | |
1987 | uint64_t isr; | |
1988 | int handled = 0; | |
1989 | ||
693aa947 MM |
1990 | /* |
1991 | * Read the ISR (this clears the bits in the real | |
1992 | * register, except for counter addr) | |
1993 | */ | |
74b0247f | 1994 | |
693aa947 | 1995 | isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR; |
1da177e4 | 1996 | |
693aa947 MM |
1997 | if (isr == 0) |
1998 | return IRQ_RETVAL(0); | |
1999 | handled = 1; | |
74b0247f | 2000 | |
693aa947 MM |
2001 | /* |
2002 | * Transmits on channel 0 | |
2003 | */ | |
74b0247f | 2004 | |
bea3348e | 2005 | if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) |
693aa947 | 2006 | sbdma_tx_process(sc,&(sc->sbm_txdma), 0); |
74b0247f | 2007 | |
693aa947 | 2008 | if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) { |
288379f0 | 2009 | if (napi_schedule_prep(&sc->napi)) { |
693aa947 | 2010 | __raw_writeq(0, sc->sbm_imr); |
288379f0 | 2011 | __napi_schedule(&sc->napi); |
693aa947 MM |
2012 | /* Depend on the exit from poll to reenable intr */ |
2013 | } | |
2014 | else { | |
2015 | /* may leave some packets behind */ | |
2016 | sbdma_rx_process(sc,&(sc->sbm_rxdma), | |
2017 | SBMAC_MAX_RXDESCR * 2, 0); | |
1da177e4 LT |
2018 | } |
2019 | } | |
2020 | return IRQ_RETVAL(handled); | |
2021 | } | |
2022 | ||
1da177e4 LT |
2023 | /********************************************************************** |
2024 | * SBMAC_START_TX(skb,dev) | |
74b0247f RB |
2025 | * |
2026 | * Start output on the specified interface. Basically, we | |
1da177e4 LT |
2027 | * queue as many buffers as we can until the ring fills up, or |
2028 | * we run off the end of the queue, whichever comes first. | |
74b0247f RB |
2029 | * |
2030 | * Input parameters: | |
2031 | * | |
2032 | * | |
1da177e4 LT |
2033 | * Return value: |
2034 | * nothing | |
2035 | ********************************************************************* */ | |
2036 | static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev) | |
2037 | { | |
2038 | struct sbmac_softc *sc = netdev_priv(dev); | |
be61ea52 | 2039 | unsigned long flags; |
74b0247f | 2040 | |
1da177e4 | 2041 | /* lock eth irq */ |
be61ea52 | 2042 | spin_lock_irqsave(&sc->sbm_lock, flags); |
74b0247f | 2043 | |
1da177e4 | 2044 | /* |
74b0247f | 2045 | * Put the buffer on the transmit ring. If we |
1da177e4 LT |
2046 | * don't have room, stop the queue. |
2047 | */ | |
74b0247f | 2048 | |
1da177e4 LT |
2049 | if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) { |
2050 | /* XXX save skb that we could not send */ | |
2051 | netif_stop_queue(dev); | |
be61ea52 | 2052 | spin_unlock_irqrestore(&sc->sbm_lock, flags); |
1da177e4 | 2053 | |
5b548140 | 2054 | return NETDEV_TX_BUSY; |
1da177e4 | 2055 | } |
74b0247f | 2056 | |
be61ea52 | 2057 | spin_unlock_irqrestore(&sc->sbm_lock, flags); |
74b0247f | 2058 | |
6ed10654 | 2059 | return NETDEV_TX_OK; |
1da177e4 LT |
2060 | } |
2061 | ||
2062 | /********************************************************************** | |
2063 | * SBMAC_SETMULTI(sc) | |
74b0247f | 2064 | * |
1da177e4 LT |
2065 | * Reprogram the multicast table into the hardware, given |
2066 | * the list of multicasts associated with the interface | |
2067 | * structure. | |
74b0247f RB |
2068 | * |
2069 | * Input parameters: | |
1da177e4 | 2070 | * sc - softc |
74b0247f | 2071 | * |
1da177e4 LT |
2072 | * Return value: |
2073 | * nothing | |
2074 | ********************************************************************* */ | |
2075 | ||
2076 | static void sbmac_setmulti(struct sbmac_softc *sc) | |
2077 | { | |
2078 | uint64_t reg; | |
73d73969 | 2079 | void __iomem *port; |
1da177e4 | 2080 | int idx; |
22bedad3 | 2081 | struct netdev_hw_addr *ha; |
1da177e4 | 2082 | struct net_device *dev = sc->sbm_dev; |
74b0247f RB |
2083 | |
2084 | /* | |
1da177e4 LT |
2085 | * Clear out entire multicast table. We do this by nuking |
2086 | * the entire hash table and all the direct matches except | |
74b0247f | 2087 | * the first one, which is used for our station address |
1da177e4 | 2088 | */ |
74b0247f | 2089 | |
1da177e4 LT |
2090 | for (idx = 1; idx < MAC_ADDR_COUNT; idx++) { |
2091 | port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t)); | |
2039973a | 2092 | __raw_writeq(0, port); |
1da177e4 | 2093 | } |
74b0247f | 2094 | |
1da177e4 LT |
2095 | for (idx = 0; idx < MAC_HASH_COUNT; idx++) { |
2096 | port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t)); | |
2039973a | 2097 | __raw_writeq(0, port); |
1da177e4 | 2098 | } |
74b0247f | 2099 | |
1da177e4 LT |
2100 | /* |
2101 | * Clear the filter to say we don't want any multicasts. | |
2102 | */ | |
74b0247f | 2103 | |
2039973a | 2104 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 2105 | reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN); |
2039973a | 2106 | __raw_writeq(reg, sc->sbm_rxfilter); |
74b0247f | 2107 | |
1da177e4 | 2108 | if (dev->flags & IFF_ALLMULTI) { |
74b0247f RB |
2109 | /* |
2110 | * Enable ALL multicasts. Do this by inverting the | |
2111 | * multicast enable bit. | |
1da177e4 | 2112 | */ |
2039973a | 2113 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 2114 | reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN); |
2039973a | 2115 | __raw_writeq(reg, sc->sbm_rxfilter); |
1da177e4 LT |
2116 | return; |
2117 | } | |
1da177e4 | 2118 | |
74b0247f RB |
2119 | |
2120 | /* | |
1da177e4 LT |
2121 | * Progam new multicast entries. For now, only use the |
2122 | * perfect filter. In the future we'll need to use the | |
2123 | * hash filter if the perfect filter overflows | |
2124 | */ | |
74b0247f | 2125 | |
1da177e4 LT |
2126 | /* XXX only using perfect filter for now, need to use hash |
2127 | * XXX if the table overflows */ | |
74b0247f | 2128 | |
1da177e4 | 2129 | idx = 1; /* skip station address */ |
22bedad3 | 2130 | netdev_for_each_mc_addr(ha, dev) { |
5508590c JP |
2131 | if (idx == MAC_ADDR_COUNT) |
2132 | break; | |
22bedad3 | 2133 | reg = sbmac_addr2reg(ha->addr); |
1da177e4 | 2134 | port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t)); |
2039973a | 2135 | __raw_writeq(reg, port); |
1da177e4 | 2136 | idx++; |
1da177e4 | 2137 | } |
74b0247f RB |
2138 | |
2139 | /* | |
1da177e4 | 2140 | * Enable the "accept multicast bits" if we programmed at least one |
74b0247f | 2141 | * multicast. |
1da177e4 | 2142 | */ |
74b0247f | 2143 | |
1da177e4 | 2144 | if (idx > 1) { |
2039973a | 2145 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 2146 | reg |= M_MAC_MCAST_EN; |
2039973a | 2147 | __raw_writeq(reg, sc->sbm_rxfilter); |
1da177e4 LT |
2148 | } |
2149 | } | |
2150 | ||
1da177e4 LT |
2151 | static int sb1250_change_mtu(struct net_device *_dev, int new_mtu) |
2152 | { | |
2153 | if (new_mtu > ENET_PACKET_SIZE) | |
2154 | return -EINVAL; | |
2155 | _dev->mtu = new_mtu; | |
f5279ffd | 2156 | pr_info("changing the mtu to %d\n", new_mtu); |
1da177e4 LT |
2157 | return 0; |
2158 | } | |
2159 | ||
b4cf3421 AB |
2160 | static const struct net_device_ops sbmac_netdev_ops = { |
2161 | .ndo_open = sbmac_open, | |
2162 | .ndo_stop = sbmac_close, | |
2163 | .ndo_start_xmit = sbmac_start_tx, | |
afc4b13d | 2164 | .ndo_set_rx_mode = sbmac_set_rx_mode, |
b4cf3421 AB |
2165 | .ndo_tx_timeout = sbmac_tx_timeout, |
2166 | .ndo_do_ioctl = sbmac_mii_ioctl, | |
2167 | .ndo_change_mtu = sb1250_change_mtu, | |
2168 | .ndo_validate_addr = eth_validate_addr, | |
2169 | .ndo_set_mac_address = eth_mac_addr, | |
2170 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2171 | .ndo_poll_controller = sbmac_netpoll, | |
2172 | #endif | |
2173 | }; | |
2174 | ||
1da177e4 LT |
2175 | /********************************************************************** |
2176 | * SBMAC_INIT(dev) | |
74b0247f | 2177 | * |
1da177e4 | 2178 | * Attach routine - init hardware and hook ourselves into linux |
74b0247f RB |
2179 | * |
2180 | * Input parameters: | |
1da177e4 | 2181 | * dev - net_device structure |
74b0247f | 2182 | * |
1da177e4 LT |
2183 | * Return value: |
2184 | * status | |
2185 | ********************************************************************* */ | |
2186 | ||
f5279ffd | 2187 | static int sbmac_init(struct platform_device *pldev, long long base) |
1da177e4 | 2188 | { |
8513fbd8 | 2189 | struct net_device *dev = platform_get_drvdata(pldev); |
f5279ffd MR |
2190 | int idx = pldev->id; |
2191 | struct sbmac_softc *sc = netdev_priv(dev); | |
1da177e4 LT |
2192 | unsigned char *eaddr; |
2193 | uint64_t ea_reg; | |
2194 | int i; | |
2195 | int err; | |
74b0247f | 2196 | |
1da177e4 LT |
2197 | sc->sbm_dev = dev; |
2198 | sc->sbe_idx = idx; | |
74b0247f | 2199 | |
1da177e4 | 2200 | eaddr = sc->sbm_hwaddr; |
74b0247f RB |
2201 | |
2202 | /* | |
877d0310 | 2203 | * Read the ethernet address. The firmware left this programmed |
1da177e4 LT |
2204 | * for us in the ethernet address register for each mac. |
2205 | */ | |
74b0247f | 2206 | |
2039973a RB |
2207 | ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR); |
2208 | __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR); | |
1da177e4 LT |
2209 | for (i = 0; i < 6; i++) { |
2210 | eaddr[i] = (uint8_t) (ea_reg & 0xFF); | |
2211 | ea_reg >>= 8; | |
2212 | } | |
74b0247f | 2213 | |
1da177e4 LT |
2214 | for (i = 0; i < 6; i++) { |
2215 | dev->dev_addr[i] = eaddr[i]; | |
2216 | } | |
74b0247f | 2217 | |
74b0247f | 2218 | /* |
1da177e4 LT |
2219 | * Initialize context (get pointers to registers and stuff), then |
2220 | * allocate the memory for the descriptor tables. | |
2221 | */ | |
74b0247f | 2222 | |
1da177e4 | 2223 | sbmac_initctx(sc); |
74b0247f | 2224 | |
1da177e4 LT |
2225 | /* |
2226 | * Set up Linux device callins | |
2227 | */ | |
74b0247f | 2228 | |
1da177e4 | 2229 | spin_lock_init(&(sc->sbm_lock)); |
74b0247f | 2230 | |
b4cf3421 AB |
2231 | dev->netdev_ops = &sbmac_netdev_ops; |
2232 | dev->watchdog_timeo = TX_TIMEOUT; | |
bea3348e SH |
2233 | |
2234 | netif_napi_add(dev, &sc->napi, sbmac_poll, 16); | |
1da177e4 | 2235 | |
f5279ffd MR |
2236 | dev->irq = UNIT_INT(idx); |
2237 | ||
1da177e4 LT |
2238 | /* This is needed for PASS2 for Rx H/W checksum feature */ |
2239 | sbmac_set_iphdr_offset(sc); | |
2240 | ||
298cf9be LB |
2241 | sc->mii_bus = mdiobus_alloc(); |
2242 | if (sc->mii_bus == NULL) { | |
03f80cc3 SS |
2243 | err = -ENOMEM; |
2244 | goto uninit_ctx; | |
298cf9be LB |
2245 | } |
2246 | ||
03f80cc3 | 2247 | sc->mii_bus->name = sbmac_mdio_string; |
446bbc4b FF |
2248 | snprintf(sc->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
2249 | pldev->name, idx); | |
03f80cc3 SS |
2250 | sc->mii_bus->priv = sc; |
2251 | sc->mii_bus->read = sbmac_mii_read; | |
2252 | sc->mii_bus->write = sbmac_mii_write; | |
2253 | sc->mii_bus->irq = sc->phy_irq; | |
2254 | for (i = 0; i < PHY_MAX_ADDR; ++i) | |
2255 | sc->mii_bus->irq[i] = SBMAC_PHY_INT; | |
2256 | ||
2257 | sc->mii_bus->parent = &pldev->dev; | |
2258 | /* | |
2259 | * Probe PHY address | |
2260 | */ | |
2261 | err = mdiobus_register(sc->mii_bus); | |
2262 | if (err) { | |
2263 | printk(KERN_ERR "%s: unable to register MDIO bus\n", | |
2264 | dev->name); | |
2265 | goto free_mdio; | |
2266 | } | |
8513fbd8 | 2267 | platform_set_drvdata(pldev, sc->mii_bus); |
03f80cc3 | 2268 | |
1da177e4 | 2269 | err = register_netdev(dev); |
f5279ffd MR |
2270 | if (err) { |
2271 | printk(KERN_ERR "%s.%d: unable to register netdev\n", | |
2272 | sbmac_string, idx); | |
03f80cc3 | 2273 | goto unreg_mdio; |
1da177e4 LT |
2274 | } |
2275 | ||
f5279ffd MR |
2276 | pr_info("%s.%d: registered as %s\n", sbmac_string, idx, dev->name); |
2277 | ||
2278 | if (sc->rx_hw_checksum == ENABLE) | |
2279 | pr_info("%s: enabling TCP rcv checksum\n", dev->name); | |
2280 | ||
1da177e4 LT |
2281 | /* |
2282 | * Display Ethernet address (this is called during the config | |
2283 | * process so we need to finish off the config message that | |
2284 | * was being displayed) | |
2285 | */ | |
e174961c JB |
2286 | pr_info("%s: SiByte Ethernet at 0x%08Lx, address: %pM\n", |
2287 | dev->name, base, eaddr); | |
1da177e4 | 2288 | |
f5279ffd | 2289 | return 0; |
03f80cc3 SS |
2290 | unreg_mdio: |
2291 | mdiobus_unregister(sc->mii_bus); | |
03f80cc3 SS |
2292 | free_mdio: |
2293 | mdiobus_free(sc->mii_bus); | |
2294 | uninit_ctx: | |
2295 | sbmac_uninitctx(sc); | |
2296 | return err; | |
1da177e4 LT |
2297 | } |
2298 | ||
2299 | ||
2300 | static int sbmac_open(struct net_device *dev) | |
2301 | { | |
2302 | struct sbmac_softc *sc = netdev_priv(dev); | |
f5279ffd | 2303 | int err; |
74b0247f | 2304 | |
f5279ffd MR |
2305 | if (debug > 1) |
2306 | pr_debug("%s: sbmac_open() irq %d.\n", dev->name, dev->irq); | |
74b0247f RB |
2307 | |
2308 | /* | |
1da177e4 LT |
2309 | * map/route interrupt (clear status first, in case something |
2310 | * weird is pending; we haven't initialized the mac registers | |
2311 | * yet) | |
2312 | */ | |
2313 | ||
2039973a | 2314 | __raw_readq(sc->sbm_isr); |
a0607fd3 | 2315 | err = request_irq(dev->irq, sbmac_intr, IRQF_SHARED, dev->name, dev); |
f5279ffd MR |
2316 | if (err) { |
2317 | printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name, | |
2318 | dev->irq); | |
2319 | goto out_err; | |
2320 | } | |
1da177e4 | 2321 | |
f5279ffd MR |
2322 | sc->sbm_speed = sbmac_speed_none; |
2323 | sc->sbm_duplex = sbmac_duplex_none; | |
2324 | sc->sbm_fc = sbmac_fc_none; | |
2325 | sc->sbm_pause = -1; | |
2326 | sc->sbm_link = 0; | |
bea3348e | 2327 | |
1da177e4 | 2328 | /* |
f5279ffd | 2329 | * Attach to the PHY |
1da177e4 | 2330 | */ |
f5279ffd MR |
2331 | err = sbmac_mii_probe(dev); |
2332 | if (err) | |
2333 | goto out_unregister; | |
74b0247f | 2334 | |
1da177e4 LT |
2335 | /* |
2336 | * Turn on the channel | |
2337 | */ | |
2338 | ||
2339 | sbmac_set_channel_state(sc,sbmac_state_on); | |
74b0247f | 2340 | |
1da177e4 | 2341 | netif_start_queue(dev); |
74b0247f | 2342 | |
1da177e4 | 2343 | sbmac_set_rx_mode(dev); |
74b0247f | 2344 | |
f5279ffd MR |
2345 | phy_start(sc->phy_dev); |
2346 | ||
2347 | napi_enable(&sc->napi); | |
74b0247f | 2348 | |
1da177e4 | 2349 | return 0; |
f5279ffd MR |
2350 | |
2351 | out_unregister: | |
f5279ffd | 2352 | free_irq(dev->irq, dev); |
f5279ffd MR |
2353 | out_err: |
2354 | return err; | |
1da177e4 LT |
2355 | } |
2356 | ||
59b81827 RB |
2357 | static int sbmac_mii_probe(struct net_device *dev) |
2358 | { | |
f5279ffd MR |
2359 | struct sbmac_softc *sc = netdev_priv(dev); |
2360 | struct phy_device *phy_dev; | |
59b81827 | 2361 | int i; |
1da177e4 | 2362 | |
f5279ffd | 2363 | for (i = 0; i < PHY_MAX_ADDR; i++) { |
298cf9be | 2364 | phy_dev = sc->mii_bus->phy_map[i]; |
f5279ffd MR |
2365 | if (phy_dev) |
2366 | break; | |
1da177e4 | 2367 | } |
f5279ffd MR |
2368 | if (!phy_dev) { |
2369 | printk(KERN_ERR "%s: no PHY found\n", dev->name); | |
2370 | return -ENXIO; | |
1da177e4 LT |
2371 | } |
2372 | ||
f9a8f83b | 2373 | phy_dev = phy_connect(dev, dev_name(&phy_dev->dev), &sbmac_mii_poll, |
f5279ffd MR |
2374 | PHY_INTERFACE_MODE_GMII); |
2375 | if (IS_ERR(phy_dev)) { | |
2376 | printk(KERN_ERR "%s: could not attach to PHY\n", dev->name); | |
2377 | return PTR_ERR(phy_dev); | |
1da177e4 LT |
2378 | } |
2379 | ||
f5279ffd MR |
2380 | /* Remove any features not supported by the controller */ |
2381 | phy_dev->supported &= SUPPORTED_10baseT_Half | | |
2382 | SUPPORTED_10baseT_Full | | |
2383 | SUPPORTED_100baseT_Half | | |
2384 | SUPPORTED_100baseT_Full | | |
2385 | SUPPORTED_1000baseT_Half | | |
2386 | SUPPORTED_1000baseT_Full | | |
2387 | SUPPORTED_Autoneg | | |
2388 | SUPPORTED_MII | | |
2389 | SUPPORTED_Pause | | |
2390 | SUPPORTED_Asym_Pause; | |
2391 | phy_dev->advertising = phy_dev->supported; | |
2392 | ||
2393 | pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", | |
2394 | dev->name, phy_dev->drv->name, | |
db1d7bf7 | 2395 | dev_name(&phy_dev->dev), phy_dev->irq); |
f5279ffd MR |
2396 | |
2397 | sc->phy_dev = phy_dev; | |
1da177e4 | 2398 | |
f5279ffd | 2399 | return 0; |
1da177e4 LT |
2400 | } |
2401 | ||
2402 | ||
f5279ffd | 2403 | static void sbmac_mii_poll(struct net_device *dev) |
1da177e4 | 2404 | { |
1da177e4 | 2405 | struct sbmac_softc *sc = netdev_priv(dev); |
f5279ffd MR |
2406 | struct phy_device *phy_dev = sc->phy_dev; |
2407 | unsigned long flags; | |
2408 | enum sbmac_fc fc; | |
2409 | int link_chg, speed_chg, duplex_chg, pause_chg, fc_chg; | |
2410 | ||
2411 | link_chg = (sc->sbm_link != phy_dev->link); | |
2412 | speed_chg = (sc->sbm_speed != phy_dev->speed); | |
2413 | duplex_chg = (sc->sbm_duplex != phy_dev->duplex); | |
2414 | pause_chg = (sc->sbm_pause != phy_dev->pause); | |
2415 | ||
2416 | if (!link_chg && !speed_chg && !duplex_chg && !pause_chg) | |
2417 | return; /* Hmmm... */ | |
2418 | ||
2419 | if (!phy_dev->link) { | |
2420 | if (link_chg) { | |
2421 | sc->sbm_link = phy_dev->link; | |
2422 | sc->sbm_speed = sbmac_speed_none; | |
2423 | sc->sbm_duplex = sbmac_duplex_none; | |
2424 | sc->sbm_fc = sbmac_fc_disabled; | |
2425 | sc->sbm_pause = -1; | |
2426 | pr_info("%s: link unavailable\n", dev->name); | |
2427 | } | |
2428 | return; | |
2429 | } | |
1da177e4 | 2430 | |
f5279ffd MR |
2431 | if (phy_dev->duplex == DUPLEX_FULL) { |
2432 | if (phy_dev->pause) | |
2433 | fc = sbmac_fc_frame; | |
2434 | else | |
2435 | fc = sbmac_fc_disabled; | |
2436 | } else | |
2437 | fc = sbmac_fc_collision; | |
2438 | fc_chg = (sc->sbm_fc != fc); | |
74b0247f | 2439 | |
f5279ffd MR |
2440 | pr_info("%s: link available: %dbase-%cD\n", dev->name, phy_dev->speed, |
2441 | phy_dev->duplex == DUPLEX_FULL ? 'F' : 'H'); | |
74b0247f | 2442 | |
f5279ffd | 2443 | spin_lock_irqsave(&sc->sbm_lock, flags); |
74b0247f | 2444 | |
f5279ffd MR |
2445 | sc->sbm_speed = phy_dev->speed; |
2446 | sc->sbm_duplex = phy_dev->duplex; | |
2447 | sc->sbm_fc = fc; | |
2448 | sc->sbm_pause = phy_dev->pause; | |
2449 | sc->sbm_link = phy_dev->link; | |
1da177e4 | 2450 | |
f5279ffd MR |
2451 | if ((speed_chg || duplex_chg || fc_chg) && |
2452 | sc->sbm_state != sbmac_state_off) { | |
2453 | /* | |
2454 | * something changed, restart the channel | |
2455 | */ | |
2456 | if (debug > 1) | |
2457 | pr_debug("%s: restarting channel " | |
2458 | "because PHY state changed\n", dev->name); | |
2459 | sbmac_channel_stop(sc); | |
2460 | sbmac_channel_start(sc); | |
1da177e4 | 2461 | } |
74b0247f | 2462 | |
f5279ffd | 2463 | spin_unlock_irqrestore(&sc->sbm_lock, flags); |
1da177e4 LT |
2464 | } |
2465 | ||
2466 | ||
2467 | static void sbmac_tx_timeout (struct net_device *dev) | |
2468 | { | |
2469 | struct sbmac_softc *sc = netdev_priv(dev); | |
be61ea52 | 2470 | unsigned long flags; |
74b0247f | 2471 | |
be61ea52 | 2472 | spin_lock_irqsave(&sc->sbm_lock, flags); |
74b0247f RB |
2473 | |
2474 | ||
1ae5dc34 | 2475 | dev->trans_start = jiffies; /* prevent tx timeout */ |
09f75cd7 | 2476 | dev->stats.tx_errors++; |
74b0247f | 2477 | |
be61ea52 | 2478 | spin_unlock_irqrestore(&sc->sbm_lock, flags); |
1da177e4 LT |
2479 | |
2480 | printk (KERN_WARNING "%s: Transmit timed out\n",dev->name); | |
2481 | } | |
2482 | ||
2483 | ||
2484 | ||
2485 | ||
1da177e4 LT |
2486 | static void sbmac_set_rx_mode(struct net_device *dev) |
2487 | { | |
2488 | unsigned long flags; | |
1da177e4 LT |
2489 | struct sbmac_softc *sc = netdev_priv(dev); |
2490 | ||
2491 | spin_lock_irqsave(&sc->sbm_lock, flags); | |
2492 | if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) { | |
2493 | /* | |
2494 | * Promiscuous changed. | |
2495 | */ | |
74b0247f RB |
2496 | |
2497 | if (dev->flags & IFF_PROMISC) { | |
1da177e4 LT |
2498 | sbmac_promiscuous_mode(sc,1); |
2499 | } | |
2500 | else { | |
1da177e4 LT |
2501 | sbmac_promiscuous_mode(sc,0); |
2502 | } | |
2503 | } | |
2504 | spin_unlock_irqrestore(&sc->sbm_lock, flags); | |
74b0247f | 2505 | |
1da177e4 LT |
2506 | /* |
2507 | * Program the multicasts. Do this every time. | |
2508 | */ | |
74b0247f | 2509 | |
1da177e4 | 2510 | sbmac_setmulti(sc); |
74b0247f | 2511 | |
1da177e4 LT |
2512 | } |
2513 | ||
2514 | static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2515 | { | |
2516 | struct sbmac_softc *sc = netdev_priv(dev); | |
74b0247f | 2517 | |
f5279ffd MR |
2518 | if (!netif_running(dev) || !sc->phy_dev) |
2519 | return -EINVAL; | |
74b0247f | 2520 | |
28b04113 | 2521 | return phy_mii_ioctl(sc->phy_dev, rq, cmd); |
1da177e4 LT |
2522 | } |
2523 | ||
2524 | static int sbmac_close(struct net_device *dev) | |
2525 | { | |
2526 | struct sbmac_softc *sc = netdev_priv(dev); | |
1da177e4 | 2527 | |
bea3348e SH |
2528 | napi_disable(&sc->napi); |
2529 | ||
f5279ffd | 2530 | phy_stop(sc->phy_dev); |
1da177e4 | 2531 | |
f5279ffd | 2532 | sbmac_set_channel_state(sc, sbmac_state_off); |
1da177e4 LT |
2533 | |
2534 | netif_stop_queue(dev); | |
2535 | ||
f5279ffd MR |
2536 | if (debug > 1) |
2537 | pr_debug("%s: Shutting down ethercard\n", dev->name); | |
1da177e4 | 2538 | |
f5279ffd MR |
2539 | phy_disconnect(sc->phy_dev); |
2540 | sc->phy_dev = NULL; | |
f5279ffd | 2541 | free_irq(dev->irq, dev); |
1da177e4 LT |
2542 | |
2543 | sbdma_emptyring(&(sc->sbm_txdma)); | |
2544 | sbdma_emptyring(&(sc->sbm_rxdma)); | |
74b0247f | 2545 | |
1da177e4 LT |
2546 | return 0; |
2547 | } | |
2548 | ||
bea3348e | 2549 | static int sbmac_poll(struct napi_struct *napi, int budget) |
693aa947 | 2550 | { |
bea3348e | 2551 | struct sbmac_softc *sc = container_of(napi, struct sbmac_softc, napi); |
693aa947 | 2552 | int work_done; |
1da177e4 | 2553 | |
bea3348e | 2554 | work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), budget, 1); |
693aa947 MM |
2555 | sbdma_tx_process(sc, &(sc->sbm_txdma), 1); |
2556 | ||
bea3348e | 2557 | if (work_done < budget) { |
288379f0 | 2558 | napi_complete(napi); |
693aa947 MM |
2559 | |
2560 | #ifdef CONFIG_SBMAC_COALESCE | |
2561 | __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | | |
2562 | ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), | |
2563 | sc->sbm_imr); | |
2564 | #else | |
2565 | __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | | |
2566 | (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr); | |
2567 | #endif | |
2568 | } | |
2569 | ||
bea3348e | 2570 | return work_done; |
693aa947 | 2571 | } |
1da177e4 | 2572 | |
f5279ffd | 2573 | |
047fc566 | 2574 | static int sbmac_probe(struct platform_device *pldev) |
f5279ffd MR |
2575 | { |
2576 | struct net_device *dev; | |
2577 | struct sbmac_softc *sc; | |
2578 | void __iomem *sbm_base; | |
2579 | struct resource *res; | |
2580 | u64 sbmac_orig_hwaddr; | |
2581 | int err; | |
2582 | ||
2583 | res = platform_get_resource(pldev, IORESOURCE_MEM, 0); | |
2584 | BUG_ON(!res); | |
28f65c11 | 2585 | sbm_base = ioremap_nocache(res->start, resource_size(res)); |
f5279ffd MR |
2586 | if (!sbm_base) { |
2587 | printk(KERN_ERR "%s: unable to map device registers\n", | |
db1d7bf7 | 2588 | dev_name(&pldev->dev)); |
f5279ffd MR |
2589 | err = -ENOMEM; |
2590 | goto out_out; | |
2591 | } | |
2592 | ||
2593 | /* | |
2594 | * The R_MAC_ETHERNET_ADDR register will be set to some nonzero | |
2595 | * value for us by the firmware if we're going to use this MAC. | |
2596 | * If we find a zero, skip this MAC. | |
2597 | */ | |
2598 | sbmac_orig_hwaddr = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR); | |
db1d7bf7 | 2599 | pr_debug("%s: %sconfiguring MAC at 0x%08Lx\n", dev_name(&pldev->dev), |
f5279ffd MR |
2600 | sbmac_orig_hwaddr ? "" : "not ", (long long)res->start); |
2601 | if (sbmac_orig_hwaddr == 0) { | |
2602 | err = 0; | |
2603 | goto out_unmap; | |
2604 | } | |
2605 | ||
2606 | /* | |
2607 | * Okay, cool. Initialize this MAC. | |
2608 | */ | |
2609 | dev = alloc_etherdev(sizeof(struct sbmac_softc)); | |
2610 | if (!dev) { | |
f5279ffd MR |
2611 | err = -ENOMEM; |
2612 | goto out_unmap; | |
2613 | } | |
2614 | ||
8513fbd8 | 2615 | platform_set_drvdata(pldev, dev); |
f5279ffd MR |
2616 | SET_NETDEV_DEV(dev, &pldev->dev); |
2617 | ||
2618 | sc = netdev_priv(dev); | |
2619 | sc->sbm_base = sbm_base; | |
2620 | ||
2621 | err = sbmac_init(pldev, res->start); | |
2622 | if (err) | |
2623 | goto out_kfree; | |
2624 | ||
2625 | return 0; | |
2626 | ||
2627 | out_kfree: | |
2628 | free_netdev(dev); | |
2629 | __raw_writeq(sbmac_orig_hwaddr, sbm_base + R_MAC_ETHERNET_ADDR); | |
2630 | ||
2631 | out_unmap: | |
2632 | iounmap(sbm_base); | |
2633 | ||
2634 | out_out: | |
2635 | return err; | |
2636 | } | |
2637 | ||
2638 | static int __exit sbmac_remove(struct platform_device *pldev) | |
2639 | { | |
8513fbd8 | 2640 | struct net_device *dev = platform_get_drvdata(pldev); |
f5279ffd MR |
2641 | struct sbmac_softc *sc = netdev_priv(dev); |
2642 | ||
2643 | unregister_netdev(dev); | |
2644 | sbmac_uninitctx(sc); | |
03f80cc3 | 2645 | mdiobus_unregister(sc->mii_bus); |
298cf9be | 2646 | mdiobus_free(sc->mii_bus); |
f5279ffd MR |
2647 | iounmap(sc->sbm_base); |
2648 | free_netdev(dev); | |
2649 | ||
2650 | return 0; | |
2651 | } | |
2652 | ||
f5279ffd MR |
2653 | static struct platform_driver sbmac_driver = { |
2654 | .probe = sbmac_probe, | |
2655 | .remove = __exit_p(sbmac_remove), | |
2656 | .driver = { | |
2657 | .name = sbmac_string, | |
2658 | }, | |
2659 | }; | |
1da177e4 | 2660 | |
db62f684 | 2661 | module_platform_driver(sbmac_driver); |