Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
b86fb2cf | 7 | * Copyright (C) 2005-2011 Broadcom Corporation. |
1da177e4 LT |
8 | * |
9 | * Firmware is: | |
49cabf49 MC |
10 | * Derived from proprietary unpublished source code, |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | |
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
6867c843 | 21 | #include <linux/stringify.h> |
1da177e4 LT |
22 | #include <linux/kernel.h> |
23 | #include <linux/types.h> | |
24 | #include <linux/compiler.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
14c85021 | 27 | #include <linux/in.h> |
1da177e4 | 28 | #include <linux/init.h> |
a6b7a407 | 29 | #include <linux/interrupt.h> |
1da177e4 LT |
30 | #include <linux/ioport.h> |
31 | #include <linux/pci.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/ethtool.h> | |
3110f5f5 | 36 | #include <linux/mdio.h> |
1da177e4 | 37 | #include <linux/mii.h> |
158d7abd | 38 | #include <linux/phy.h> |
a9daf367 | 39 | #include <linux/brcmphy.h> |
1da177e4 LT |
40 | #include <linux/if_vlan.h> |
41 | #include <linux/ip.h> | |
42 | #include <linux/tcp.h> | |
43 | #include <linux/workqueue.h> | |
61487480 | 44 | #include <linux/prefetch.h> |
f9a5f7d3 | 45 | #include <linux/dma-mapping.h> |
077f849d | 46 | #include <linux/firmware.h> |
1da177e4 LT |
47 | |
48 | #include <net/checksum.h> | |
c9bdd4b5 | 49 | #include <net/ip.h> |
1da177e4 LT |
50 | |
51 | #include <asm/system.h> | |
27fd9de8 | 52 | #include <linux/io.h> |
1da177e4 | 53 | #include <asm/byteorder.h> |
27fd9de8 | 54 | #include <linux/uaccess.h> |
1da177e4 | 55 | |
49b6e95f | 56 | #ifdef CONFIG_SPARC |
1da177e4 | 57 | #include <asm/idprom.h> |
49b6e95f | 58 | #include <asm/prom.h> |
1da177e4 LT |
59 | #endif |
60 | ||
63532394 MC |
61 | #define BAR_0 0 |
62 | #define BAR_2 2 | |
63 | ||
1da177e4 LT |
64 | #include "tg3.h" |
65 | ||
63c3a66f JP |
66 | /* Functions & macros to verify TG3_FLAGS types */ |
67 | ||
68 | static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits) | |
69 | { | |
70 | return test_bit(flag, bits); | |
71 | } | |
72 | ||
73 | static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits) | |
74 | { | |
75 | set_bit(flag, bits); | |
76 | } | |
77 | ||
78 | static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits) | |
79 | { | |
80 | clear_bit(flag, bits); | |
81 | } | |
82 | ||
83 | #define tg3_flag(tp, flag) \ | |
84 | _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags) | |
85 | #define tg3_flag_set(tp, flag) \ | |
86 | _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags) | |
87 | #define tg3_flag_clear(tp, flag) \ | |
88 | _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags) | |
89 | ||
1da177e4 | 90 | #define DRV_MODULE_NAME "tg3" |
6867c843 | 91 | #define TG3_MAJ_NUM 3 |
5ae7fa06 | 92 | #define TG3_MIN_NUM 121 |
6867c843 MC |
93 | #define DRV_MODULE_VERSION \ |
94 | __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) | |
5ae7fa06 | 95 | #define DRV_MODULE_RELDATE "November 2, 2011" |
1da177e4 | 96 | |
fd6d3f0e MC |
97 | #define RESET_KIND_SHUTDOWN 0 |
98 | #define RESET_KIND_INIT 1 | |
99 | #define RESET_KIND_SUSPEND 2 | |
100 | ||
1da177e4 LT |
101 | #define TG3_DEF_RX_MODE 0 |
102 | #define TG3_DEF_TX_MODE 0 | |
103 | #define TG3_DEF_MSG_ENABLE \ | |
104 | (NETIF_MSG_DRV | \ | |
105 | NETIF_MSG_PROBE | \ | |
106 | NETIF_MSG_LINK | \ | |
107 | NETIF_MSG_TIMER | \ | |
108 | NETIF_MSG_IFDOWN | \ | |
109 | NETIF_MSG_IFUP | \ | |
110 | NETIF_MSG_RX_ERR | \ | |
111 | NETIF_MSG_TX_ERR) | |
112 | ||
520b2756 MC |
113 | #define TG3_GRC_LCLCTL_PWRSW_DELAY 100 |
114 | ||
1da177e4 LT |
115 | /* length of time before we decide the hardware is borked, |
116 | * and dev->tx_timeout() should be called to fix the problem | |
117 | */ | |
63c3a66f | 118 | |
1da177e4 LT |
119 | #define TG3_TX_TIMEOUT (5 * HZ) |
120 | ||
121 | /* hardware minimum and maximum for a single frame's data payload */ | |
122 | #define TG3_MIN_MTU 60 | |
123 | #define TG3_MAX_MTU(tp) \ | |
63c3a66f | 124 | (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500) |
1da177e4 LT |
125 | |
126 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
127 | * You can't change the ring sizes, but you can change where you place | |
128 | * them in the NIC onboard memory. | |
129 | */ | |
7cb32cf2 | 130 | #define TG3_RX_STD_RING_SIZE(tp) \ |
63c3a66f | 131 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
de9f5230 | 132 | TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700) |
1da177e4 | 133 | #define TG3_DEF_RX_RING_PENDING 200 |
7cb32cf2 | 134 | #define TG3_RX_JMB_RING_SIZE(tp) \ |
63c3a66f | 135 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
de9f5230 | 136 | TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700) |
1da177e4 | 137 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 |
c6cdf436 | 138 | #define TG3_RSS_INDIR_TBL_SIZE 128 |
1da177e4 LT |
139 | |
140 | /* Do not place this n-ring entries value into the tp struct itself, | |
141 | * we really want to expose these constants to GCC so that modulo et | |
142 | * al. operations are done with shifts and masks instead of with | |
143 | * hw multiply/modulo instructions. Another solution would be to | |
144 | * replace things like '% foo' with '& (foo - 1)'. | |
145 | */ | |
1da177e4 LT |
146 | |
147 | #define TG3_TX_RING_SIZE 512 | |
148 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
149 | ||
2c49a44d MC |
150 | #define TG3_RX_STD_RING_BYTES(tp) \ |
151 | (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp)) | |
152 | #define TG3_RX_JMB_RING_BYTES(tp) \ | |
153 | (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp)) | |
154 | #define TG3_RX_RCB_RING_BYTES(tp) \ | |
7cb32cf2 | 155 | (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1)) |
1da177e4 LT |
156 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ |
157 | TG3_TX_RING_SIZE) | |
1da177e4 LT |
158 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
159 | ||
287be12e MC |
160 | #define TG3_DMA_BYTE_ENAB 64 |
161 | ||
162 | #define TG3_RX_STD_DMA_SZ 1536 | |
163 | #define TG3_RX_JMB_DMA_SZ 9046 | |
164 | ||
165 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
166 | ||
167 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
168 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
1da177e4 | 169 | |
2c49a44d MC |
170 | #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ |
171 | (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp)) | |
2b2cdb65 | 172 | |
2c49a44d MC |
173 | #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ |
174 | (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp)) | |
2b2cdb65 | 175 | |
d2757fc4 MC |
176 | /* Due to a hardware bug, the 5701 can only DMA to memory addresses |
177 | * that are at least dword aligned when used in PCIX mode. The driver | |
178 | * works around this bug by double copying the packet. This workaround | |
179 | * is built into the normal double copy length check for efficiency. | |
180 | * | |
181 | * However, the double copy is only necessary on those architectures | |
182 | * where unaligned memory accesses are inefficient. For those architectures | |
183 | * where unaligned memory accesses incur little penalty, we can reintegrate | |
184 | * the 5701 in the normal rx path. Doing so saves a device structure | |
185 | * dereference by hardcoding the double copy threshold in place. | |
186 | */ | |
187 | #define TG3_RX_COPY_THRESHOLD 256 | |
188 | #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) | |
189 | #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD | |
190 | #else | |
191 | #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) | |
192 | #endif | |
193 | ||
81389f57 MC |
194 | #if (NET_IP_ALIGN != 0) |
195 | #define TG3_RX_OFFSET(tp) ((tp)->rx_offset) | |
196 | #else | |
197 | #define TG3_RX_OFFSET(tp) 0 | |
198 | #endif | |
199 | ||
1da177e4 | 200 | /* minimum number of free TX descriptors required to wake up TX process */ |
f3f3f27e | 201 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
e31aa987 | 202 | #define TG3_TX_BD_DMA_MAX 4096 |
1da177e4 | 203 | |
ad829268 MC |
204 | #define TG3_RAW_IP_ALIGN 2 |
205 | ||
c6cdf436 MC |
206 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 |
207 | ||
077f849d JSR |
208 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
209 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
210 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
211 | ||
1da177e4 | 212 | static char version[] __devinitdata = |
05dbe005 | 213 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")"; |
1da177e4 LT |
214 | |
215 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
216 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
217 | MODULE_LICENSE("GPL"); | |
218 | MODULE_VERSION(DRV_MODULE_VERSION); | |
077f849d JSR |
219 | MODULE_FIRMWARE(FIRMWARE_TG3); |
220 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
221 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
222 | ||
1da177e4 LT |
223 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ |
224 | module_param(tg3_debug, int, 0); | |
225 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
226 | ||
a3aa1884 | 227 | static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = { |
13185217 HK |
228 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, |
229 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
230 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
231 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
232 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
235 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
238 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
239 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
240 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
241 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
242 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
243 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
244 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
245 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
246 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, | |
247 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, | |
248 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, | |
249 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, | |
13185217 | 250 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, |
126a3368 | 251 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, |
13185217 | 252 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, |
13185217 HK |
253 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, |
254 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, | |
255 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, | |
256 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
257 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
258 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
259 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, | |
260 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, | |
261 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
262 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
263 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
126a3368 | 264 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, |
13185217 HK |
265 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, |
266 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
267 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, | |
676917d4 | 268 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, |
13185217 HK |
269 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, |
270 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
271 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
272 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
273 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
274 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
275 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
b5d3772c MC |
276 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, |
277 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
d30cdd28 MC |
278 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, |
279 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
6c7af27c | 280 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, |
9936bcf6 MC |
281 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, |
282 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
c88e668b MC |
283 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, |
284 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
2befdcea MC |
285 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, |
286 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
321d32a0 MC |
287 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, |
288 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
289 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, | |
5e7ccf20 | 290 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, |
5001e2f6 MC |
291 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)}, |
292 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)}, | |
b0f75221 MC |
293 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)}, |
294 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)}, | |
295 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)}, | |
296 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)}, | |
297 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)}, | |
298 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)}, | |
302b500b | 299 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)}, |
ba1f3c76 | 300 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)}, |
13185217 HK |
301 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, |
302 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
303 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
304 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
305 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
306 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
307 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
1dcb14d9 | 308 | {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */ |
13185217 | 309 | {} |
1da177e4 LT |
310 | }; |
311 | ||
312 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
313 | ||
50da859d | 314 | static const struct { |
1da177e4 | 315 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 316 | } ethtool_stats_keys[] = { |
1da177e4 LT |
317 | { "rx_octets" }, |
318 | { "rx_fragments" }, | |
319 | { "rx_ucast_packets" }, | |
320 | { "rx_mcast_packets" }, | |
321 | { "rx_bcast_packets" }, | |
322 | { "rx_fcs_errors" }, | |
323 | { "rx_align_errors" }, | |
324 | { "rx_xon_pause_rcvd" }, | |
325 | { "rx_xoff_pause_rcvd" }, | |
326 | { "rx_mac_ctrl_rcvd" }, | |
327 | { "rx_xoff_entered" }, | |
328 | { "rx_frame_too_long_errors" }, | |
329 | { "rx_jabbers" }, | |
330 | { "rx_undersize_packets" }, | |
331 | { "rx_in_length_errors" }, | |
332 | { "rx_out_length_errors" }, | |
333 | { "rx_64_or_less_octet_packets" }, | |
334 | { "rx_65_to_127_octet_packets" }, | |
335 | { "rx_128_to_255_octet_packets" }, | |
336 | { "rx_256_to_511_octet_packets" }, | |
337 | { "rx_512_to_1023_octet_packets" }, | |
338 | { "rx_1024_to_1522_octet_packets" }, | |
339 | { "rx_1523_to_2047_octet_packets" }, | |
340 | { "rx_2048_to_4095_octet_packets" }, | |
341 | { "rx_4096_to_8191_octet_packets" }, | |
342 | { "rx_8192_to_9022_octet_packets" }, | |
343 | ||
344 | { "tx_octets" }, | |
345 | { "tx_collisions" }, | |
346 | ||
347 | { "tx_xon_sent" }, | |
348 | { "tx_xoff_sent" }, | |
349 | { "tx_flow_control" }, | |
350 | { "tx_mac_errors" }, | |
351 | { "tx_single_collisions" }, | |
352 | { "tx_mult_collisions" }, | |
353 | { "tx_deferred" }, | |
354 | { "tx_excessive_collisions" }, | |
355 | { "tx_late_collisions" }, | |
356 | { "tx_collide_2times" }, | |
357 | { "tx_collide_3times" }, | |
358 | { "tx_collide_4times" }, | |
359 | { "tx_collide_5times" }, | |
360 | { "tx_collide_6times" }, | |
361 | { "tx_collide_7times" }, | |
362 | { "tx_collide_8times" }, | |
363 | { "tx_collide_9times" }, | |
364 | { "tx_collide_10times" }, | |
365 | { "tx_collide_11times" }, | |
366 | { "tx_collide_12times" }, | |
367 | { "tx_collide_13times" }, | |
368 | { "tx_collide_14times" }, | |
369 | { "tx_collide_15times" }, | |
370 | { "tx_ucast_packets" }, | |
371 | { "tx_mcast_packets" }, | |
372 | { "tx_bcast_packets" }, | |
373 | { "tx_carrier_sense_errors" }, | |
374 | { "tx_discards" }, | |
375 | { "tx_errors" }, | |
376 | ||
377 | { "dma_writeq_full" }, | |
378 | { "dma_write_prioq_full" }, | |
379 | { "rxbds_empty" }, | |
380 | { "rx_discards" }, | |
381 | { "rx_errors" }, | |
382 | { "rx_threshold_hit" }, | |
383 | ||
384 | { "dma_readq_full" }, | |
385 | { "dma_read_prioq_full" }, | |
386 | { "tx_comp_queue_full" }, | |
387 | ||
388 | { "ring_set_send_prod_index" }, | |
389 | { "ring_status_update" }, | |
390 | { "nic_irqs" }, | |
391 | { "nic_avoided_irqs" }, | |
4452d099 MC |
392 | { "nic_tx_threshold_hit" }, |
393 | ||
394 | { "mbuf_lwm_thresh_hit" }, | |
1da177e4 LT |
395 | }; |
396 | ||
48fa55a0 MC |
397 | #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys) |
398 | ||
399 | ||
50da859d | 400 | static const struct { |
4cafd3f5 | 401 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 402 | } ethtool_test_keys[] = { |
28a45957 MC |
403 | { "nvram test (online) " }, |
404 | { "link test (online) " }, | |
405 | { "register test (offline)" }, | |
406 | { "memory test (offline)" }, | |
407 | { "mac loopback test (offline)" }, | |
408 | { "phy loopback test (offline)" }, | |
941ec90f | 409 | { "ext loopback test (offline)" }, |
28a45957 | 410 | { "interrupt test (offline)" }, |
4cafd3f5 MC |
411 | }; |
412 | ||
48fa55a0 MC |
413 | #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys) |
414 | ||
415 | ||
b401e9e2 MC |
416 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) |
417 | { | |
418 | writel(val, tp->regs + off); | |
419 | } | |
420 | ||
421 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
422 | { | |
de6f31eb | 423 | return readl(tp->regs + off); |
b401e9e2 MC |
424 | } |
425 | ||
0d3031d9 MC |
426 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) |
427 | { | |
428 | writel(val, tp->aperegs + off); | |
429 | } | |
430 | ||
431 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
432 | { | |
de6f31eb | 433 | return readl(tp->aperegs + off); |
0d3031d9 MC |
434 | } |
435 | ||
1da177e4 LT |
436 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
437 | { | |
6892914f MC |
438 | unsigned long flags; |
439 | ||
440 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
1ee582d8 MC |
441 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
442 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
6892914f | 443 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1ee582d8 MC |
444 | } |
445 | ||
446 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
447 | { | |
448 | writel(val, tp->regs + off); | |
449 | readl(tp->regs + off); | |
1da177e4 LT |
450 | } |
451 | ||
6892914f | 452 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) |
1da177e4 | 453 | { |
6892914f MC |
454 | unsigned long flags; |
455 | u32 val; | |
456 | ||
457 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
458 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
459 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
460 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
461 | return val; | |
462 | } | |
463 | ||
464 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
465 | { | |
466 | unsigned long flags; | |
467 | ||
468 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
469 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
470 | TG3_64BIT_REG_LOW, val); | |
471 | return; | |
472 | } | |
66711e66 | 473 | if (off == TG3_RX_STD_PROD_IDX_REG) { |
6892914f MC |
474 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + |
475 | TG3_64BIT_REG_LOW, val); | |
476 | return; | |
1da177e4 | 477 | } |
6892914f MC |
478 | |
479 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
480 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
481 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
482 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
483 | ||
484 | /* In indirect mode when disabling interrupts, we also need | |
485 | * to clear the interrupt bit in the GRC local ctrl register. | |
486 | */ | |
487 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
488 | (val == 0x1)) { | |
489 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
490 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
491 | } | |
492 | } | |
493 | ||
494 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
495 | { | |
496 | unsigned long flags; | |
497 | u32 val; | |
498 | ||
499 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
500 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
501 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
502 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
503 | return val; | |
504 | } | |
505 | ||
b401e9e2 MC |
506 | /* usec_wait specifies the wait time in usec when writing to certain registers |
507 | * where it is unsafe to read back the register without some delay. | |
508 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
509 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
510 | */ | |
511 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
6892914f | 512 | { |
63c3a66f | 513 | if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) |
b401e9e2 MC |
514 | /* Non-posted methods */ |
515 | tp->write32(tp, off, val); | |
516 | else { | |
517 | /* Posted method */ | |
518 | tg3_write32(tp, off, val); | |
519 | if (usec_wait) | |
520 | udelay(usec_wait); | |
521 | tp->read32(tp, off); | |
522 | } | |
523 | /* Wait again after the read for the posted method to guarantee that | |
524 | * the wait time is met. | |
525 | */ | |
526 | if (usec_wait) | |
527 | udelay(usec_wait); | |
1da177e4 LT |
528 | } |
529 | ||
09ee929c MC |
530 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
531 | { | |
532 | tp->write32_mbox(tp, off, val); | |
63c3a66f | 533 | if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)) |
6892914f | 534 | tp->read32_mbox(tp, off); |
09ee929c MC |
535 | } |
536 | ||
20094930 | 537 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
1da177e4 LT |
538 | { |
539 | void __iomem *mbox = tp->regs + off; | |
540 | writel(val, mbox); | |
63c3a66f | 541 | if (tg3_flag(tp, TXD_MBOX_HWBUG)) |
1da177e4 | 542 | writel(val, mbox); |
63c3a66f | 543 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
1da177e4 LT |
544 | readl(mbox); |
545 | } | |
546 | ||
b5d3772c MC |
547 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) |
548 | { | |
de6f31eb | 549 | return readl(tp->regs + off + GRCMBOX_BASE); |
b5d3772c MC |
550 | } |
551 | ||
552 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
553 | { | |
554 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
555 | } | |
556 | ||
c6cdf436 | 557 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
09ee929c | 558 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
c6cdf436 MC |
559 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
560 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
561 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | |
20094930 | 562 | |
c6cdf436 MC |
563 | #define tw32(reg, val) tp->write32(tp, reg, val) |
564 | #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) | |
565 | #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) | |
566 | #define tr32(reg) tp->read32(tp, reg) | |
1da177e4 LT |
567 | |
568 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
569 | { | |
6892914f MC |
570 | unsigned long flags; |
571 | ||
6ff6f81d | 572 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
b5d3772c MC |
573 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) |
574 | return; | |
575 | ||
6892914f | 576 | spin_lock_irqsave(&tp->indirect_lock, flags); |
63c3a66f | 577 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
bbadf503 MC |
578 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
579 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 580 | |
bbadf503 MC |
581 | /* Always leave this as zero. */ |
582 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
583 | } else { | |
584 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
585 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
28fbef78 | 586 | |
bbadf503 MC |
587 | /* Always leave this as zero. */ |
588 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
589 | } | |
590 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
758a6139 DM |
591 | } |
592 | ||
1da177e4 LT |
593 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) |
594 | { | |
6892914f MC |
595 | unsigned long flags; |
596 | ||
6ff6f81d | 597 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
b5d3772c MC |
598 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { |
599 | *val = 0; | |
600 | return; | |
601 | } | |
602 | ||
6892914f | 603 | spin_lock_irqsave(&tp->indirect_lock, flags); |
63c3a66f | 604 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
bbadf503 MC |
605 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
606 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 607 | |
bbadf503 MC |
608 | /* Always leave this as zero. */ |
609 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
610 | } else { | |
611 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
612 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
613 | ||
614 | /* Always leave this as zero. */ | |
615 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
616 | } | |
6892914f | 617 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1da177e4 LT |
618 | } |
619 | ||
0d3031d9 MC |
620 | static void tg3_ape_lock_init(struct tg3 *tp) |
621 | { | |
622 | int i; | |
6f5c8f83 | 623 | u32 regbase, bit; |
f92d9dc1 MC |
624 | |
625 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
626 | regbase = TG3_APE_LOCK_GRANT; | |
627 | else | |
628 | regbase = TG3_APE_PER_LOCK_GRANT; | |
0d3031d9 MC |
629 | |
630 | /* Make sure the driver hasn't any stale locks. */ | |
78f94dc7 MC |
631 | for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) { |
632 | switch (i) { | |
633 | case TG3_APE_LOCK_PHY0: | |
634 | case TG3_APE_LOCK_PHY1: | |
635 | case TG3_APE_LOCK_PHY2: | |
636 | case TG3_APE_LOCK_PHY3: | |
637 | bit = APE_LOCK_GRANT_DRIVER; | |
638 | break; | |
639 | default: | |
640 | if (!tp->pci_fn) | |
641 | bit = APE_LOCK_GRANT_DRIVER; | |
642 | else | |
643 | bit = 1 << tp->pci_fn; | |
644 | } | |
645 | tg3_ape_write32(tp, regbase + 4 * i, bit); | |
6f5c8f83 MC |
646 | } |
647 | ||
0d3031d9 MC |
648 | } |
649 | ||
650 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
651 | { | |
652 | int i, off; | |
653 | int ret = 0; | |
6f5c8f83 | 654 | u32 status, req, gnt, bit; |
0d3031d9 | 655 | |
63c3a66f | 656 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
657 | return 0; |
658 | ||
659 | switch (locknum) { | |
6f5c8f83 MC |
660 | case TG3_APE_LOCK_GPIO: |
661 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
662 | return 0; | |
33f401ae MC |
663 | case TG3_APE_LOCK_GRC: |
664 | case TG3_APE_LOCK_MEM: | |
78f94dc7 MC |
665 | if (!tp->pci_fn) |
666 | bit = APE_LOCK_REQ_DRIVER; | |
667 | else | |
668 | bit = 1 << tp->pci_fn; | |
33f401ae MC |
669 | break; |
670 | default: | |
671 | return -EINVAL; | |
0d3031d9 MC |
672 | } |
673 | ||
f92d9dc1 MC |
674 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { |
675 | req = TG3_APE_LOCK_REQ; | |
676 | gnt = TG3_APE_LOCK_GRANT; | |
677 | } else { | |
678 | req = TG3_APE_PER_LOCK_REQ; | |
679 | gnt = TG3_APE_PER_LOCK_GRANT; | |
680 | } | |
681 | ||
0d3031d9 MC |
682 | off = 4 * locknum; |
683 | ||
6f5c8f83 | 684 | tg3_ape_write32(tp, req + off, bit); |
0d3031d9 MC |
685 | |
686 | /* Wait for up to 1 millisecond to acquire lock. */ | |
687 | for (i = 0; i < 100; i++) { | |
f92d9dc1 | 688 | status = tg3_ape_read32(tp, gnt + off); |
6f5c8f83 | 689 | if (status == bit) |
0d3031d9 MC |
690 | break; |
691 | udelay(10); | |
692 | } | |
693 | ||
6f5c8f83 | 694 | if (status != bit) { |
0d3031d9 | 695 | /* Revoke the lock request. */ |
6f5c8f83 | 696 | tg3_ape_write32(tp, gnt + off, bit); |
0d3031d9 MC |
697 | ret = -EBUSY; |
698 | } | |
699 | ||
700 | return ret; | |
701 | } | |
702 | ||
703 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
704 | { | |
6f5c8f83 | 705 | u32 gnt, bit; |
0d3031d9 | 706 | |
63c3a66f | 707 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
708 | return; |
709 | ||
710 | switch (locknum) { | |
6f5c8f83 MC |
711 | case TG3_APE_LOCK_GPIO: |
712 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
713 | return; | |
33f401ae MC |
714 | case TG3_APE_LOCK_GRC: |
715 | case TG3_APE_LOCK_MEM: | |
78f94dc7 MC |
716 | if (!tp->pci_fn) |
717 | bit = APE_LOCK_GRANT_DRIVER; | |
718 | else | |
719 | bit = 1 << tp->pci_fn; | |
33f401ae MC |
720 | break; |
721 | default: | |
722 | return; | |
0d3031d9 MC |
723 | } |
724 | ||
f92d9dc1 MC |
725 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
726 | gnt = TG3_APE_LOCK_GRANT; | |
727 | else | |
728 | gnt = TG3_APE_PER_LOCK_GRANT; | |
729 | ||
6f5c8f83 | 730 | tg3_ape_write32(tp, gnt + 4 * locknum, bit); |
0d3031d9 MC |
731 | } |
732 | ||
fd6d3f0e MC |
733 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) |
734 | { | |
735 | int i; | |
736 | u32 apedata; | |
737 | ||
738 | /* NCSI does not support APE events */ | |
739 | if (tg3_flag(tp, APE_HAS_NCSI)) | |
740 | return; | |
741 | ||
742 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
743 | if (apedata != APE_SEG_SIG_MAGIC) | |
744 | return; | |
745 | ||
746 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
747 | if (!(apedata & APE_FW_STATUS_READY)) | |
748 | return; | |
749 | ||
750 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
751 | for (i = 0; i < 10; i++) { | |
752 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
753 | return; | |
754 | ||
755 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
756 | ||
757 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
758 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, | |
759 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
760 | ||
761 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
762 | ||
763 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
764 | break; | |
765 | ||
766 | udelay(100); | |
767 | } | |
768 | ||
769 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
770 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
771 | } | |
772 | ||
773 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
774 | { | |
775 | u32 event; | |
776 | u32 apedata; | |
777 | ||
778 | if (!tg3_flag(tp, ENABLE_APE)) | |
779 | return; | |
780 | ||
781 | switch (kind) { | |
782 | case RESET_KIND_INIT: | |
783 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
784 | APE_HOST_SEG_SIG_MAGIC); | |
785 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
786 | APE_HOST_SEG_LEN_MAGIC); | |
787 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
788 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
789 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
790 | APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM)); | |
791 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, | |
792 | APE_HOST_BEHAV_NO_PHYLOCK); | |
793 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, | |
794 | TG3_APE_HOST_DRVR_STATE_START); | |
795 | ||
796 | event = APE_EVENT_STATUS_STATE_START; | |
797 | break; | |
798 | case RESET_KIND_SHUTDOWN: | |
799 | /* With the interface we are currently using, | |
800 | * APE does not track driver state. Wiping | |
801 | * out the HOST SEGMENT SIGNATURE forces | |
802 | * the APE to assume OS absent status. | |
803 | */ | |
804 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
805 | ||
806 | if (device_may_wakeup(&tp->pdev->dev) && | |
807 | tg3_flag(tp, WOL_ENABLE)) { | |
808 | tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, | |
809 | TG3_APE_HOST_WOL_SPEED_AUTO); | |
810 | apedata = TG3_APE_HOST_DRVR_STATE_WOL; | |
811 | } else | |
812 | apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD; | |
813 | ||
814 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); | |
815 | ||
816 | event = APE_EVENT_STATUS_STATE_UNLOAD; | |
817 | break; | |
818 | case RESET_KIND_SUSPEND: | |
819 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
820 | break; | |
821 | default: | |
822 | return; | |
823 | } | |
824 | ||
825 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
826 | ||
827 | tg3_ape_send_event(tp, event); | |
828 | } | |
829 | ||
1da177e4 LT |
830 | static void tg3_disable_ints(struct tg3 *tp) |
831 | { | |
89aeb3bc MC |
832 | int i; |
833 | ||
1da177e4 LT |
834 | tw32(TG3PCI_MISC_HOST_CTRL, |
835 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc MC |
836 | for (i = 0; i < tp->irq_max; i++) |
837 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); | |
1da177e4 LT |
838 | } |
839 | ||
1da177e4 LT |
840 | static void tg3_enable_ints(struct tg3 *tp) |
841 | { | |
89aeb3bc | 842 | int i; |
89aeb3bc | 843 | |
bbe832c0 MC |
844 | tp->irq_sync = 0; |
845 | wmb(); | |
846 | ||
1da177e4 LT |
847 | tw32(TG3PCI_MISC_HOST_CTRL, |
848 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc | 849 | |
f89f38b8 | 850 | tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; |
89aeb3bc MC |
851 | for (i = 0; i < tp->irq_cnt; i++) { |
852 | struct tg3_napi *tnapi = &tp->napi[i]; | |
c6cdf436 | 853 | |
898a56f8 | 854 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
63c3a66f | 855 | if (tg3_flag(tp, 1SHOT_MSI)) |
89aeb3bc | 856 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
f19af9c2 | 857 | |
f89f38b8 | 858 | tp->coal_now |= tnapi->coal_now; |
89aeb3bc | 859 | } |
f19af9c2 MC |
860 | |
861 | /* Force an initial interrupt */ | |
63c3a66f | 862 | if (!tg3_flag(tp, TAGGED_STATUS) && |
f19af9c2 MC |
863 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) |
864 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
865 | else | |
f89f38b8 MC |
866 | tw32(HOSTCC_MODE, tp->coal_now); |
867 | ||
868 | tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); | |
1da177e4 LT |
869 | } |
870 | ||
17375d25 | 871 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) |
04237ddd | 872 | { |
17375d25 | 873 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 874 | struct tg3_hw_status *sblk = tnapi->hw_status; |
04237ddd MC |
875 | unsigned int work_exists = 0; |
876 | ||
877 | /* check for phy events */ | |
63c3a66f | 878 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
04237ddd MC |
879 | if (sblk->status & SD_STATUS_LINK_CHG) |
880 | work_exists = 1; | |
881 | } | |
882 | /* check for RX/TX work to do */ | |
f3f3f27e | 883 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons || |
8d9d7cfc | 884 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
04237ddd MC |
885 | work_exists = 1; |
886 | ||
887 | return work_exists; | |
888 | } | |
889 | ||
17375d25 | 890 | /* tg3_int_reenable |
04237ddd MC |
891 | * similar to tg3_enable_ints, but it accurately determines whether there |
892 | * is new work pending and can return without flushing the PIO write | |
6aa20a22 | 893 | * which reenables interrupts |
1da177e4 | 894 | */ |
17375d25 | 895 | static void tg3_int_reenable(struct tg3_napi *tnapi) |
1da177e4 | 896 | { |
17375d25 MC |
897 | struct tg3 *tp = tnapi->tp; |
898 | ||
898a56f8 | 899 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
1da177e4 LT |
900 | mmiowb(); |
901 | ||
fac9b83e DM |
902 | /* When doing tagged status, this work check is unnecessary. |
903 | * The last_tag we write above tells the chip which piece of | |
904 | * work we've completed. | |
905 | */ | |
63c3a66f | 906 | if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) |
04237ddd | 907 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
fd2ce37f | 908 | HOSTCC_MODE_ENABLE | tnapi->coal_now); |
1da177e4 LT |
909 | } |
910 | ||
1da177e4 LT |
911 | static void tg3_switch_clocks(struct tg3 *tp) |
912 | { | |
f6eb9b1f | 913 | u32 clock_ctrl; |
1da177e4 LT |
914 | u32 orig_clock_ctrl; |
915 | ||
63c3a66f | 916 | if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) |
4cf78e4f MC |
917 | return; |
918 | ||
f6eb9b1f MC |
919 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); |
920 | ||
1da177e4 LT |
921 | orig_clock_ctrl = clock_ctrl; |
922 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
923 | CLOCK_CTRL_CLKRUN_OENABLE | | |
924 | 0x1f); | |
925 | tp->pci_clock_ctrl = clock_ctrl; | |
926 | ||
63c3a66f | 927 | if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 | 928 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { |
b401e9e2 MC |
929 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
930 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
1da177e4 LT |
931 | } |
932 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
b401e9e2 MC |
933 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
934 | clock_ctrl | | |
935 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
936 | 40); | |
937 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
938 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
939 | 40); | |
1da177e4 | 940 | } |
b401e9e2 | 941 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); |
1da177e4 LT |
942 | } |
943 | ||
944 | #define PHY_BUSY_LOOPS 5000 | |
945 | ||
946 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
947 | { | |
948 | u32 frame_val; | |
949 | unsigned int loops; | |
950 | int ret; | |
951 | ||
952 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
953 | tw32_f(MAC_MI_MODE, | |
954 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
955 | udelay(80); | |
956 | } | |
957 | ||
958 | *val = 0x0; | |
959 | ||
882e9793 | 960 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
961 | MI_COM_PHY_ADDR_MASK); |
962 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
963 | MI_COM_REG_ADDR_MASK); | |
964 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
6aa20a22 | 965 | |
1da177e4 LT |
966 | tw32_f(MAC_MI_COM, frame_val); |
967 | ||
968 | loops = PHY_BUSY_LOOPS; | |
969 | while (loops != 0) { | |
970 | udelay(10); | |
971 | frame_val = tr32(MAC_MI_COM); | |
972 | ||
973 | if ((frame_val & MI_COM_BUSY) == 0) { | |
974 | udelay(5); | |
975 | frame_val = tr32(MAC_MI_COM); | |
976 | break; | |
977 | } | |
978 | loops -= 1; | |
979 | } | |
980 | ||
981 | ret = -EBUSY; | |
982 | if (loops != 0) { | |
983 | *val = frame_val & MI_COM_DATA_MASK; | |
984 | ret = 0; | |
985 | } | |
986 | ||
987 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
988 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
989 | udelay(80); | |
990 | } | |
991 | ||
992 | return ret; | |
993 | } | |
994 | ||
995 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
996 | { | |
997 | u32 frame_val; | |
998 | unsigned int loops; | |
999 | int ret; | |
1000 | ||
f07e9af3 | 1001 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && |
221c5637 | 1002 | (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL)) |
b5d3772c MC |
1003 | return 0; |
1004 | ||
1da177e4 LT |
1005 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
1006 | tw32_f(MAC_MI_MODE, | |
1007 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
1008 | udelay(80); | |
1009 | } | |
1010 | ||
882e9793 | 1011 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
1012 | MI_COM_PHY_ADDR_MASK); |
1013 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
1014 | MI_COM_REG_ADDR_MASK); | |
1015 | frame_val |= (val & MI_COM_DATA_MASK); | |
1016 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
6aa20a22 | 1017 | |
1da177e4 LT |
1018 | tw32_f(MAC_MI_COM, frame_val); |
1019 | ||
1020 | loops = PHY_BUSY_LOOPS; | |
1021 | while (loops != 0) { | |
1022 | udelay(10); | |
1023 | frame_val = tr32(MAC_MI_COM); | |
1024 | if ((frame_val & MI_COM_BUSY) == 0) { | |
1025 | udelay(5); | |
1026 | frame_val = tr32(MAC_MI_COM); | |
1027 | break; | |
1028 | } | |
1029 | loops -= 1; | |
1030 | } | |
1031 | ||
1032 | ret = -EBUSY; | |
1033 | if (loops != 0) | |
1034 | ret = 0; | |
1035 | ||
1036 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
1037 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1038 | udelay(80); | |
1039 | } | |
1040 | ||
1041 | return ret; | |
1042 | } | |
1043 | ||
b0988c15 MC |
1044 | static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) |
1045 | { | |
1046 | int err; | |
1047 | ||
1048 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
1049 | if (err) | |
1050 | goto done; | |
1051 | ||
1052 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
1053 | if (err) | |
1054 | goto done; | |
1055 | ||
1056 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
1057 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
1058 | if (err) | |
1059 | goto done; | |
1060 | ||
1061 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); | |
1062 | ||
1063 | done: | |
1064 | return err; | |
1065 | } | |
1066 | ||
1067 | static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) | |
1068 | { | |
1069 | int err; | |
1070 | ||
1071 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
1072 | if (err) | |
1073 | goto done; | |
1074 | ||
1075 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
1076 | if (err) | |
1077 | goto done; | |
1078 | ||
1079 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
1080 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
1081 | if (err) | |
1082 | goto done; | |
1083 | ||
1084 | err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); | |
1085 | ||
1086 | done: | |
1087 | return err; | |
1088 | } | |
1089 | ||
1090 | static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) | |
1091 | { | |
1092 | int err; | |
1093 | ||
1094 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1095 | if (!err) | |
1096 | err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); | |
1097 | ||
1098 | return err; | |
1099 | } | |
1100 | ||
1101 | static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) | |
1102 | { | |
1103 | int err; | |
1104 | ||
1105 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1106 | if (!err) | |
1107 | err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
1108 | ||
1109 | return err; | |
1110 | } | |
1111 | ||
15ee95c3 MC |
1112 | static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) |
1113 | { | |
1114 | int err; | |
1115 | ||
1116 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
1117 | (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) | | |
1118 | MII_TG3_AUXCTL_SHDWSEL_MISC); | |
1119 | if (!err) | |
1120 | err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); | |
1121 | ||
1122 | return err; | |
1123 | } | |
1124 | ||
b4bd2929 MC |
1125 | static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) |
1126 | { | |
1127 | if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) | |
1128 | set |= MII_TG3_AUXCTL_MISC_WREN; | |
1129 | ||
1130 | return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); | |
1131 | } | |
1132 | ||
1d36ba45 MC |
1133 | #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \ |
1134 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1135 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \ | |
1136 | MII_TG3_AUXCTL_ACTL_TX_6DB) | |
1137 | ||
1138 | #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \ | |
1139 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1140 | MII_TG3_AUXCTL_ACTL_TX_6DB); | |
1141 | ||
95e2869a MC |
1142 | static int tg3_bmcr_reset(struct tg3 *tp) |
1143 | { | |
1144 | u32 phy_control; | |
1145 | int limit, err; | |
1146 | ||
1147 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
1148 | * clears or we time out. | |
1149 | */ | |
1150 | phy_control = BMCR_RESET; | |
1151 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
1152 | if (err != 0) | |
1153 | return -EBUSY; | |
1154 | ||
1155 | limit = 5000; | |
1156 | while (limit--) { | |
1157 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
1158 | if (err != 0) | |
1159 | return -EBUSY; | |
1160 | ||
1161 | if ((phy_control & BMCR_RESET) == 0) { | |
1162 | udelay(40); | |
1163 | break; | |
1164 | } | |
1165 | udelay(10); | |
1166 | } | |
d4675b52 | 1167 | if (limit < 0) |
95e2869a MC |
1168 | return -EBUSY; |
1169 | ||
1170 | return 0; | |
1171 | } | |
1172 | ||
158d7abd MC |
1173 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) |
1174 | { | |
3d16543d | 1175 | struct tg3 *tp = bp->priv; |
158d7abd MC |
1176 | u32 val; |
1177 | ||
24bb4fb6 | 1178 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1179 | |
1180 | if (tg3_readphy(tp, reg, &val)) | |
24bb4fb6 MC |
1181 | val = -EIO; |
1182 | ||
1183 | spin_unlock_bh(&tp->lock); | |
158d7abd MC |
1184 | |
1185 | return val; | |
1186 | } | |
1187 | ||
1188 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
1189 | { | |
3d16543d | 1190 | struct tg3 *tp = bp->priv; |
24bb4fb6 | 1191 | u32 ret = 0; |
158d7abd | 1192 | |
24bb4fb6 | 1193 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1194 | |
1195 | if (tg3_writephy(tp, reg, val)) | |
24bb4fb6 | 1196 | ret = -EIO; |
158d7abd | 1197 | |
24bb4fb6 MC |
1198 | spin_unlock_bh(&tp->lock); |
1199 | ||
1200 | return ret; | |
158d7abd MC |
1201 | } |
1202 | ||
1203 | static int tg3_mdio_reset(struct mii_bus *bp) | |
1204 | { | |
1205 | return 0; | |
1206 | } | |
1207 | ||
9c61d6bc | 1208 | static void tg3_mdio_config_5785(struct tg3 *tp) |
a9daf367 MC |
1209 | { |
1210 | u32 val; | |
fcb389df | 1211 | struct phy_device *phydev; |
a9daf367 | 1212 | |
3f0e3ad7 | 1213 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
fcb389df | 1214 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
6a443a0f MC |
1215 | case PHY_ID_BCM50610: |
1216 | case PHY_ID_BCM50610M: | |
fcb389df MC |
1217 | val = MAC_PHYCFG2_50610_LED_MODES; |
1218 | break; | |
6a443a0f | 1219 | case PHY_ID_BCMAC131: |
fcb389df MC |
1220 | val = MAC_PHYCFG2_AC131_LED_MODES; |
1221 | break; | |
6a443a0f | 1222 | case PHY_ID_RTL8211C: |
fcb389df MC |
1223 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; |
1224 | break; | |
6a443a0f | 1225 | case PHY_ID_RTL8201E: |
fcb389df MC |
1226 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; |
1227 | break; | |
1228 | default: | |
a9daf367 | 1229 | return; |
fcb389df MC |
1230 | } |
1231 | ||
1232 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
1233 | tw32(MAC_PHYCFG2, val); | |
1234 | ||
1235 | val = tr32(MAC_PHYCFG1); | |
bb85fbb6 MC |
1236 | val &= ~(MAC_PHYCFG1_RGMII_INT | |
1237 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
1238 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
fcb389df MC |
1239 | tw32(MAC_PHYCFG1, val); |
1240 | ||
1241 | return; | |
1242 | } | |
1243 | ||
63c3a66f | 1244 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) |
fcb389df MC |
1245 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | |
1246 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
1247 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
1248 | MAC_PHYCFG2_ACT_MASK_MASK | | |
1249 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
1250 | MAC_PHYCFG2_INBAND_ENABLE; | |
1251 | ||
1252 | tw32(MAC_PHYCFG2, val); | |
a9daf367 | 1253 | |
bb85fbb6 MC |
1254 | val = tr32(MAC_PHYCFG1); |
1255 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
1256 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
63c3a66f JP |
1257 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
1258 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
a9daf367 | 1259 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; |
63c3a66f | 1260 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 MC |
1261 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; |
1262 | } | |
bb85fbb6 MC |
1263 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | |
1264 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
1265 | tw32(MAC_PHYCFG1, val); | |
a9daf367 | 1266 | |
a9daf367 MC |
1267 | val = tr32(MAC_EXT_RGMII_MODE); |
1268 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
1269 | MAC_RGMII_MODE_RX_QUALITY | | |
1270 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1271 | MAC_RGMII_MODE_RX_ENG_DET | | |
1272 | MAC_RGMII_MODE_TX_ENABLE | | |
1273 | MAC_RGMII_MODE_TX_LOWPWR | | |
1274 | MAC_RGMII_MODE_TX_RESET); | |
63c3a66f JP |
1275 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
1276 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
a9daf367 MC |
1277 | val |= MAC_RGMII_MODE_RX_INT_B | |
1278 | MAC_RGMII_MODE_RX_QUALITY | | |
1279 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1280 | MAC_RGMII_MODE_RX_ENG_DET; | |
63c3a66f | 1281 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 MC |
1282 | val |= MAC_RGMII_MODE_TX_ENABLE | |
1283 | MAC_RGMII_MODE_TX_LOWPWR | | |
1284 | MAC_RGMII_MODE_TX_RESET; | |
1285 | } | |
1286 | tw32(MAC_EXT_RGMII_MODE, val); | |
1287 | } | |
1288 | ||
158d7abd MC |
1289 | static void tg3_mdio_start(struct tg3 *tp) |
1290 | { | |
158d7abd MC |
1291 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; |
1292 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1293 | udelay(80); | |
a9daf367 | 1294 | |
63c3a66f | 1295 | if (tg3_flag(tp, MDIOBUS_INITED) && |
9ea4818d MC |
1296 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
1297 | tg3_mdio_config_5785(tp); | |
1298 | } | |
1299 | ||
1300 | static int tg3_mdio_init(struct tg3 *tp) | |
1301 | { | |
1302 | int i; | |
1303 | u32 reg; | |
1304 | struct phy_device *phydev; | |
1305 | ||
63c3a66f | 1306 | if (tg3_flag(tp, 5717_PLUS)) { |
9c7df915 | 1307 | u32 is_serdes; |
882e9793 | 1308 | |
69f11c99 | 1309 | tp->phy_addr = tp->pci_fn + 1; |
882e9793 | 1310 | |
d1ec96af MC |
1311 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) |
1312 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | |
1313 | else | |
1314 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & | |
1315 | TG3_CPMU_PHY_STRAP_IS_SERDES; | |
882e9793 MC |
1316 | if (is_serdes) |
1317 | tp->phy_addr += 7; | |
1318 | } else | |
3f0e3ad7 | 1319 | tp->phy_addr = TG3_PHY_MII_ADDR; |
882e9793 | 1320 | |
158d7abd MC |
1321 | tg3_mdio_start(tp); |
1322 | ||
63c3a66f | 1323 | if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) |
158d7abd MC |
1324 | return 0; |
1325 | ||
298cf9be LB |
1326 | tp->mdio_bus = mdiobus_alloc(); |
1327 | if (tp->mdio_bus == NULL) | |
1328 | return -ENOMEM; | |
158d7abd | 1329 | |
298cf9be LB |
1330 | tp->mdio_bus->name = "tg3 mdio bus"; |
1331 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
158d7abd | 1332 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); |
298cf9be LB |
1333 | tp->mdio_bus->priv = tp; |
1334 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1335 | tp->mdio_bus->read = &tg3_mdio_read; | |
1336 | tp->mdio_bus->write = &tg3_mdio_write; | |
1337 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
3f0e3ad7 | 1338 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); |
298cf9be | 1339 | tp->mdio_bus->irq = &tp->mdio_irq[0]; |
158d7abd MC |
1340 | |
1341 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
298cf9be | 1342 | tp->mdio_bus->irq[i] = PHY_POLL; |
158d7abd MC |
1343 | |
1344 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1345 | * Unfortunately, it does not ensure the PHY is powered up before | |
1346 | * accessing the PHY ID registers. A chip reset is the | |
1347 | * quickest way to bring the device back to an operational state.. | |
1348 | */ | |
1349 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1350 | tg3_bmcr_reset(tp); | |
1351 | ||
298cf9be | 1352 | i = mdiobus_register(tp->mdio_bus); |
a9daf367 | 1353 | if (i) { |
ab96b241 | 1354 | dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); |
9c61d6bc | 1355 | mdiobus_free(tp->mdio_bus); |
a9daf367 MC |
1356 | return i; |
1357 | } | |
158d7abd | 1358 | |
3f0e3ad7 | 1359 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
a9daf367 | 1360 | |
9c61d6bc | 1361 | if (!phydev || !phydev->drv) { |
ab96b241 | 1362 | dev_warn(&tp->pdev->dev, "No PHY devices\n"); |
9c61d6bc MC |
1363 | mdiobus_unregister(tp->mdio_bus); |
1364 | mdiobus_free(tp->mdio_bus); | |
1365 | return -ENODEV; | |
1366 | } | |
1367 | ||
1368 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
6a443a0f | 1369 | case PHY_ID_BCM57780: |
321d32a0 | 1370 | phydev->interface = PHY_INTERFACE_MODE_GMII; |
c704dc23 | 1371 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
321d32a0 | 1372 | break; |
6a443a0f MC |
1373 | case PHY_ID_BCM50610: |
1374 | case PHY_ID_BCM50610M: | |
32e5a8d6 | 1375 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | |
c704dc23 | 1376 | PHY_BRCM_RX_REFCLK_UNUSED | |
52fae083 | 1377 | PHY_BRCM_DIS_TXCRXC_NOENRGY | |
c704dc23 | 1378 | PHY_BRCM_AUTO_PWRDWN_ENABLE; |
63c3a66f | 1379 | if (tg3_flag(tp, RGMII_INBAND_DISABLE)) |
a9daf367 | 1380 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; |
63c3a66f | 1381 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) |
a9daf367 | 1382 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; |
63c3a66f | 1383 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 | 1384 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; |
fcb389df | 1385 | /* fallthru */ |
6a443a0f | 1386 | case PHY_ID_RTL8211C: |
fcb389df | 1387 | phydev->interface = PHY_INTERFACE_MODE_RGMII; |
a9daf367 | 1388 | break; |
6a443a0f MC |
1389 | case PHY_ID_RTL8201E: |
1390 | case PHY_ID_BCMAC131: | |
a9daf367 | 1391 | phydev->interface = PHY_INTERFACE_MODE_MII; |
cdd4e09d | 1392 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
f07e9af3 | 1393 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
a9daf367 MC |
1394 | break; |
1395 | } | |
1396 | ||
63c3a66f | 1397 | tg3_flag_set(tp, MDIOBUS_INITED); |
9c61d6bc MC |
1398 | |
1399 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1400 | tg3_mdio_config_5785(tp); | |
a9daf367 MC |
1401 | |
1402 | return 0; | |
158d7abd MC |
1403 | } |
1404 | ||
1405 | static void tg3_mdio_fini(struct tg3 *tp) | |
1406 | { | |
63c3a66f JP |
1407 | if (tg3_flag(tp, MDIOBUS_INITED)) { |
1408 | tg3_flag_clear(tp, MDIOBUS_INITED); | |
298cf9be LB |
1409 | mdiobus_unregister(tp->mdio_bus); |
1410 | mdiobus_free(tp->mdio_bus); | |
158d7abd MC |
1411 | } |
1412 | } | |
1413 | ||
4ba526ce MC |
1414 | /* tp->lock is held. */ |
1415 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1416 | { | |
1417 | u32 val; | |
1418 | ||
1419 | val = tr32(GRC_RX_CPU_EVENT); | |
1420 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1421 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1422 | ||
1423 | tp->last_event_jiffies = jiffies; | |
1424 | } | |
1425 | ||
1426 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1427 | ||
95e2869a MC |
1428 | /* tp->lock is held. */ |
1429 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1430 | { | |
1431 | int i; | |
4ba526ce MC |
1432 | unsigned int delay_cnt; |
1433 | long time_remain; | |
1434 | ||
1435 | /* If enough time has passed, no wait is necessary. */ | |
1436 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1437 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1438 | (long)jiffies; | |
1439 | if (time_remain < 0) | |
1440 | return; | |
1441 | ||
1442 | /* Check if we can shorten the wait time. */ | |
1443 | delay_cnt = jiffies_to_usecs(time_remain); | |
1444 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1445 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1446 | delay_cnt = (delay_cnt >> 3) + 1; | |
95e2869a | 1447 | |
4ba526ce | 1448 | for (i = 0; i < delay_cnt; i++) { |
95e2869a MC |
1449 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) |
1450 | break; | |
4ba526ce | 1451 | udelay(8); |
95e2869a MC |
1452 | } |
1453 | } | |
1454 | ||
1455 | /* tp->lock is held. */ | |
1456 | static void tg3_ump_link_report(struct tg3 *tp) | |
1457 | { | |
1458 | u32 reg; | |
1459 | u32 val; | |
1460 | ||
63c3a66f | 1461 | if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) |
95e2869a MC |
1462 | return; |
1463 | ||
1464 | tg3_wait_for_event_ack(tp); | |
1465 | ||
1466 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1467 | ||
1468 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1469 | ||
1470 | val = 0; | |
1471 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1472 | val = reg << 16; | |
1473 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1474 | val |= (reg & 0xffff); | |
1475 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val); | |
1476 | ||
1477 | val = 0; | |
1478 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1479 | val = reg << 16; | |
1480 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1481 | val |= (reg & 0xffff); | |
1482 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val); | |
1483 | ||
1484 | val = 0; | |
f07e9af3 | 1485 | if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { |
95e2869a MC |
1486 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) |
1487 | val = reg << 16; | |
1488 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1489 | val |= (reg & 0xffff); | |
1490 | } | |
1491 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val); | |
1492 | ||
1493 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1494 | val = reg << 16; | |
1495 | else | |
1496 | val = 0; | |
1497 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); | |
1498 | ||
4ba526ce | 1499 | tg3_generate_fw_event(tp); |
95e2869a MC |
1500 | } |
1501 | ||
8d5a89b3 MC |
1502 | /* tp->lock is held. */ |
1503 | static void tg3_stop_fw(struct tg3 *tp) | |
1504 | { | |
1505 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { | |
1506 | /* Wait for RX cpu to ACK the previous event. */ | |
1507 | tg3_wait_for_event_ack(tp); | |
1508 | ||
1509 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
1510 | ||
1511 | tg3_generate_fw_event(tp); | |
1512 | ||
1513 | /* Wait for RX cpu to ACK this event. */ | |
1514 | tg3_wait_for_event_ack(tp); | |
1515 | } | |
1516 | } | |
1517 | ||
fd6d3f0e MC |
1518 | /* tp->lock is held. */ |
1519 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
1520 | { | |
1521 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, | |
1522 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
1523 | ||
1524 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { | |
1525 | switch (kind) { | |
1526 | case RESET_KIND_INIT: | |
1527 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1528 | DRV_STATE_START); | |
1529 | break; | |
1530 | ||
1531 | case RESET_KIND_SHUTDOWN: | |
1532 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1533 | DRV_STATE_UNLOAD); | |
1534 | break; | |
1535 | ||
1536 | case RESET_KIND_SUSPEND: | |
1537 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1538 | DRV_STATE_SUSPEND); | |
1539 | break; | |
1540 | ||
1541 | default: | |
1542 | break; | |
1543 | } | |
1544 | } | |
1545 | ||
1546 | if (kind == RESET_KIND_INIT || | |
1547 | kind == RESET_KIND_SUSPEND) | |
1548 | tg3_ape_driver_state_change(tp, kind); | |
1549 | } | |
1550 | ||
1551 | /* tp->lock is held. */ | |
1552 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
1553 | { | |
1554 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { | |
1555 | switch (kind) { | |
1556 | case RESET_KIND_INIT: | |
1557 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1558 | DRV_STATE_START_DONE); | |
1559 | break; | |
1560 | ||
1561 | case RESET_KIND_SHUTDOWN: | |
1562 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1563 | DRV_STATE_UNLOAD_DONE); | |
1564 | break; | |
1565 | ||
1566 | default: | |
1567 | break; | |
1568 | } | |
1569 | } | |
1570 | ||
1571 | if (kind == RESET_KIND_SHUTDOWN) | |
1572 | tg3_ape_driver_state_change(tp, kind); | |
1573 | } | |
1574 | ||
1575 | /* tp->lock is held. */ | |
1576 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
1577 | { | |
1578 | if (tg3_flag(tp, ENABLE_ASF)) { | |
1579 | switch (kind) { | |
1580 | case RESET_KIND_INIT: | |
1581 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1582 | DRV_STATE_START); | |
1583 | break; | |
1584 | ||
1585 | case RESET_KIND_SHUTDOWN: | |
1586 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1587 | DRV_STATE_UNLOAD); | |
1588 | break; | |
1589 | ||
1590 | case RESET_KIND_SUSPEND: | |
1591 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1592 | DRV_STATE_SUSPEND); | |
1593 | break; | |
1594 | ||
1595 | default: | |
1596 | break; | |
1597 | } | |
1598 | } | |
1599 | } | |
1600 | ||
1601 | static int tg3_poll_fw(struct tg3 *tp) | |
1602 | { | |
1603 | int i; | |
1604 | u32 val; | |
1605 | ||
1606 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
1607 | /* Wait up to 20ms for init done. */ | |
1608 | for (i = 0; i < 200; i++) { | |
1609 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) | |
1610 | return 0; | |
1611 | udelay(100); | |
1612 | } | |
1613 | return -ENODEV; | |
1614 | } | |
1615 | ||
1616 | /* Wait for firmware initialization to complete. */ | |
1617 | for (i = 0; i < 100000; i++) { | |
1618 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
1619 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
1620 | break; | |
1621 | udelay(10); | |
1622 | } | |
1623 | ||
1624 | /* Chip might not be fitted with firmware. Some Sun onboard | |
1625 | * parts are configured like that. So don't signal the timeout | |
1626 | * of the above loop as an error, but do report the lack of | |
1627 | * running firmware once. | |
1628 | */ | |
1629 | if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { | |
1630 | tg3_flag_set(tp, NO_FWARE_REPORTED); | |
1631 | ||
1632 | netdev_info(tp->dev, "No firmware running\n"); | |
1633 | } | |
1634 | ||
1635 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | |
1636 | /* The 57765 A0 needs a little more | |
1637 | * time to do some important work. | |
1638 | */ | |
1639 | mdelay(10); | |
1640 | } | |
1641 | ||
1642 | return 0; | |
1643 | } | |
1644 | ||
95e2869a MC |
1645 | static void tg3_link_report(struct tg3 *tp) |
1646 | { | |
1647 | if (!netif_carrier_ok(tp->dev)) { | |
05dbe005 | 1648 | netif_info(tp, link, tp->dev, "Link is down\n"); |
95e2869a MC |
1649 | tg3_ump_link_report(tp); |
1650 | } else if (netif_msg_link(tp)) { | |
05dbe005 JP |
1651 | netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", |
1652 | (tp->link_config.active_speed == SPEED_1000 ? | |
1653 | 1000 : | |
1654 | (tp->link_config.active_speed == SPEED_100 ? | |
1655 | 100 : 10)), | |
1656 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1657 | "full" : "half")); | |
1658 | ||
1659 | netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", | |
1660 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? | |
1661 | "on" : "off", | |
1662 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? | |
1663 | "on" : "off"); | |
47007831 MC |
1664 | |
1665 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) | |
1666 | netdev_info(tp->dev, "EEE is %s\n", | |
1667 | tp->setlpicnt ? "enabled" : "disabled"); | |
1668 | ||
95e2869a MC |
1669 | tg3_ump_link_report(tp); |
1670 | } | |
1671 | } | |
1672 | ||
1673 | static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl) | |
1674 | { | |
1675 | u16 miireg; | |
1676 | ||
e18ce346 | 1677 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1678 | miireg = ADVERTISE_PAUSE_CAP; |
e18ce346 | 1679 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1680 | miireg = ADVERTISE_PAUSE_ASYM; |
e18ce346 | 1681 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1682 | miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1683 | else | |
1684 | miireg = 0; | |
1685 | ||
1686 | return miireg; | |
1687 | } | |
1688 | ||
1689 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) | |
1690 | { | |
1691 | u16 miireg; | |
1692 | ||
e18ce346 | 1693 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1694 | miireg = ADVERTISE_1000XPAUSE; |
e18ce346 | 1695 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1696 | miireg = ADVERTISE_1000XPSE_ASYM; |
e18ce346 | 1697 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1698 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1699 | else | |
1700 | miireg = 0; | |
1701 | ||
1702 | return miireg; | |
1703 | } | |
1704 | ||
95e2869a MC |
1705 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
1706 | { | |
1707 | u8 cap = 0; | |
1708 | ||
1709 | if (lcladv & ADVERTISE_1000XPAUSE) { | |
1710 | if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1711 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1712 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a | 1713 | else if (rmtadv & LPA_1000XPAUSE_ASYM) |
e18ce346 | 1714 | cap = FLOW_CTRL_RX; |
95e2869a MC |
1715 | } else { |
1716 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1717 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a MC |
1718 | } |
1719 | } else if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1720 | if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM)) | |
e18ce346 | 1721 | cap = FLOW_CTRL_TX; |
95e2869a MC |
1722 | } |
1723 | ||
1724 | return cap; | |
1725 | } | |
1726 | ||
f51f3562 | 1727 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
95e2869a | 1728 | { |
b02fd9e3 | 1729 | u8 autoneg; |
f51f3562 | 1730 | u8 flowctrl = 0; |
95e2869a MC |
1731 | u32 old_rx_mode = tp->rx_mode; |
1732 | u32 old_tx_mode = tp->tx_mode; | |
1733 | ||
63c3a66f | 1734 | if (tg3_flag(tp, USE_PHYLIB)) |
3f0e3ad7 | 1735 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; |
b02fd9e3 MC |
1736 | else |
1737 | autoneg = tp->link_config.autoneg; | |
1738 | ||
63c3a66f | 1739 | if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { |
f07e9af3 | 1740 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
f51f3562 | 1741 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
95e2869a | 1742 | else |
bc02ff95 | 1743 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
f51f3562 MC |
1744 | } else |
1745 | flowctrl = tp->link_config.flowctrl; | |
95e2869a | 1746 | |
f51f3562 | 1747 | tp->link_config.active_flowctrl = flowctrl; |
95e2869a | 1748 | |
e18ce346 | 1749 | if (flowctrl & FLOW_CTRL_RX) |
95e2869a MC |
1750 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
1751 | else | |
1752 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1753 | ||
f51f3562 | 1754 | if (old_rx_mode != tp->rx_mode) |
95e2869a | 1755 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
95e2869a | 1756 | |
e18ce346 | 1757 | if (flowctrl & FLOW_CTRL_TX) |
95e2869a MC |
1758 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1759 | else | |
1760 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1761 | ||
f51f3562 | 1762 | if (old_tx_mode != tp->tx_mode) |
95e2869a | 1763 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
95e2869a MC |
1764 | } |
1765 | ||
b02fd9e3 MC |
1766 | static void tg3_adjust_link(struct net_device *dev) |
1767 | { | |
1768 | u8 oldflowctrl, linkmesg = 0; | |
1769 | u32 mac_mode, lcl_adv, rmt_adv; | |
1770 | struct tg3 *tp = netdev_priv(dev); | |
3f0e3ad7 | 1771 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1772 | |
24bb4fb6 | 1773 | spin_lock_bh(&tp->lock); |
b02fd9e3 MC |
1774 | |
1775 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1776 | MAC_MODE_HALF_DUPLEX); | |
1777 | ||
1778 | oldflowctrl = tp->link_config.active_flowctrl; | |
1779 | ||
1780 | if (phydev->link) { | |
1781 | lcl_adv = 0; | |
1782 | rmt_adv = 0; | |
1783 | ||
1784 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1785 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
c3df0748 MC |
1786 | else if (phydev->speed == SPEED_1000 || |
1787 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | |
b02fd9e3 | 1788 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
c3df0748 MC |
1789 | else |
1790 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
b02fd9e3 MC |
1791 | |
1792 | if (phydev->duplex == DUPLEX_HALF) | |
1793 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1794 | else { | |
1795 | lcl_adv = tg3_advert_flowctrl_1000T( | |
1796 | tp->link_config.flowctrl); | |
1797 | ||
1798 | if (phydev->pause) | |
1799 | rmt_adv = LPA_PAUSE_CAP; | |
1800 | if (phydev->asym_pause) | |
1801 | rmt_adv |= LPA_PAUSE_ASYM; | |
1802 | } | |
1803 | ||
1804 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1805 | } else | |
1806 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1807 | ||
1808 | if (mac_mode != tp->mac_mode) { | |
1809 | tp->mac_mode = mac_mode; | |
1810 | tw32_f(MAC_MODE, tp->mac_mode); | |
1811 | udelay(40); | |
1812 | } | |
1813 | ||
fcb389df MC |
1814 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
1815 | if (phydev->speed == SPEED_10) | |
1816 | tw32(MAC_MI_STAT, | |
1817 | MAC_MI_STAT_10MBPS_MODE | | |
1818 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1819 | else | |
1820 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1821 | } | |
1822 | ||
b02fd9e3 MC |
1823 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) |
1824 | tw32(MAC_TX_LENGTHS, | |
1825 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1826 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1827 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1828 | else | |
1829 | tw32(MAC_TX_LENGTHS, | |
1830 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1831 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1832 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1833 | ||
1834 | if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || | |
1835 | (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) || | |
1836 | phydev->speed != tp->link_config.active_speed || | |
1837 | phydev->duplex != tp->link_config.active_duplex || | |
1838 | oldflowctrl != tp->link_config.active_flowctrl) | |
c6cdf436 | 1839 | linkmesg = 1; |
b02fd9e3 MC |
1840 | |
1841 | tp->link_config.active_speed = phydev->speed; | |
1842 | tp->link_config.active_duplex = phydev->duplex; | |
1843 | ||
24bb4fb6 | 1844 | spin_unlock_bh(&tp->lock); |
b02fd9e3 MC |
1845 | |
1846 | if (linkmesg) | |
1847 | tg3_link_report(tp); | |
1848 | } | |
1849 | ||
1850 | static int tg3_phy_init(struct tg3 *tp) | |
1851 | { | |
1852 | struct phy_device *phydev; | |
1853 | ||
f07e9af3 | 1854 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) |
b02fd9e3 MC |
1855 | return 0; |
1856 | ||
1857 | /* Bring the PHY back to a known state. */ | |
1858 | tg3_bmcr_reset(tp); | |
1859 | ||
3f0e3ad7 | 1860 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
1861 | |
1862 | /* Attach the MAC to the PHY. */ | |
fb28ad35 | 1863 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, |
a9daf367 | 1864 | phydev->dev_flags, phydev->interface); |
b02fd9e3 | 1865 | if (IS_ERR(phydev)) { |
ab96b241 | 1866 | dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); |
b02fd9e3 MC |
1867 | return PTR_ERR(phydev); |
1868 | } | |
1869 | ||
b02fd9e3 | 1870 | /* Mask with MAC supported features. */ |
9c61d6bc MC |
1871 | switch (phydev->interface) { |
1872 | case PHY_INTERFACE_MODE_GMII: | |
1873 | case PHY_INTERFACE_MODE_RGMII: | |
f07e9af3 | 1874 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
321d32a0 MC |
1875 | phydev->supported &= (PHY_GBIT_FEATURES | |
1876 | SUPPORTED_Pause | | |
1877 | SUPPORTED_Asym_Pause); | |
1878 | break; | |
1879 | } | |
1880 | /* fallthru */ | |
9c61d6bc MC |
1881 | case PHY_INTERFACE_MODE_MII: |
1882 | phydev->supported &= (PHY_BASIC_FEATURES | | |
1883 | SUPPORTED_Pause | | |
1884 | SUPPORTED_Asym_Pause); | |
1885 | break; | |
1886 | default: | |
3f0e3ad7 | 1887 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
9c61d6bc MC |
1888 | return -EINVAL; |
1889 | } | |
1890 | ||
f07e9af3 | 1891 | tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1892 | |
1893 | phydev->advertising = phydev->supported; | |
1894 | ||
b02fd9e3 MC |
1895 | return 0; |
1896 | } | |
1897 | ||
1898 | static void tg3_phy_start(struct tg3 *tp) | |
1899 | { | |
1900 | struct phy_device *phydev; | |
1901 | ||
f07e9af3 | 1902 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1903 | return; |
1904 | ||
3f0e3ad7 | 1905 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1906 | |
80096068 MC |
1907 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
1908 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
b02fd9e3 MC |
1909 | phydev->speed = tp->link_config.orig_speed; |
1910 | phydev->duplex = tp->link_config.orig_duplex; | |
1911 | phydev->autoneg = tp->link_config.orig_autoneg; | |
1912 | phydev->advertising = tp->link_config.orig_advertising; | |
1913 | } | |
1914 | ||
1915 | phy_start(phydev); | |
1916 | ||
1917 | phy_start_aneg(phydev); | |
1918 | } | |
1919 | ||
1920 | static void tg3_phy_stop(struct tg3 *tp) | |
1921 | { | |
f07e9af3 | 1922 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1923 | return; |
1924 | ||
3f0e3ad7 | 1925 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
1926 | } |
1927 | ||
1928 | static void tg3_phy_fini(struct tg3 *tp) | |
1929 | { | |
f07e9af3 | 1930 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 | 1931 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
f07e9af3 | 1932 | tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1933 | } |
1934 | } | |
1935 | ||
941ec90f MC |
1936 | static int tg3_phy_set_extloopbk(struct tg3 *tp) |
1937 | { | |
1938 | int err; | |
1939 | u32 val; | |
1940 | ||
1941 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) | |
1942 | return 0; | |
1943 | ||
1944 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { | |
1945 | /* Cannot do read-modify-write on 5401 */ | |
1946 | err = tg3_phy_auxctl_write(tp, | |
1947 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, | |
1948 | MII_TG3_AUXCTL_ACTL_EXTLOOPBK | | |
1949 | 0x4c20); | |
1950 | goto done; | |
1951 | } | |
1952 | ||
1953 | err = tg3_phy_auxctl_read(tp, | |
1954 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); | |
1955 | if (err) | |
1956 | return err; | |
1957 | ||
1958 | val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK; | |
1959 | err = tg3_phy_auxctl_write(tp, | |
1960 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val); | |
1961 | ||
1962 | done: | |
1963 | return err; | |
1964 | } | |
1965 | ||
7f97a4bd MC |
1966 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) |
1967 | { | |
1968 | u32 phytest; | |
1969 | ||
1970 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
1971 | u32 phy; | |
1972 | ||
1973 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1974 | phytest | MII_TG3_FET_SHADOW_EN); | |
1975 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
1976 | if (enable) | |
1977 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1978 | else | |
1979 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1980 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
1981 | } | |
1982 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
1983 | } | |
1984 | } | |
1985 | ||
6833c043 MC |
1986 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
1987 | { | |
1988 | u32 reg; | |
1989 | ||
63c3a66f JP |
1990 | if (!tg3_flag(tp, 5705_PLUS) || |
1991 | (tg3_flag(tp, 5717_PLUS) && | |
f07e9af3 | 1992 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
6833c043 MC |
1993 | return; |
1994 | ||
f07e9af3 | 1995 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd MC |
1996 | tg3_phy_fet_toggle_apd(tp, enable); |
1997 | return; | |
1998 | } | |
1999 | ||
6833c043 MC |
2000 | reg = MII_TG3_MISC_SHDW_WREN | |
2001 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
2002 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
2003 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
2004 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
2005 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
2006 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
2007 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
2008 | ||
2009 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
2010 | ||
2011 | ||
2012 | reg = MII_TG3_MISC_SHDW_WREN | | |
2013 | MII_TG3_MISC_SHDW_APD_SEL | | |
2014 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
2015 | if (enable) | |
2016 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
2017 | ||
2018 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
2019 | } | |
2020 | ||
9ef8ca99 MC |
2021 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) |
2022 | { | |
2023 | u32 phy; | |
2024 | ||
63c3a66f | 2025 | if (!tg3_flag(tp, 5705_PLUS) || |
f07e9af3 | 2026 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
9ef8ca99 MC |
2027 | return; |
2028 | ||
f07e9af3 | 2029 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
9ef8ca99 MC |
2030 | u32 ephy; |
2031 | ||
535ef6e1 MC |
2032 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
2033 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
2034 | ||
2035 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2036 | ephy | MII_TG3_FET_SHADOW_EN); | |
2037 | if (!tg3_readphy(tp, reg, &phy)) { | |
9ef8ca99 | 2038 | if (enable) |
535ef6e1 | 2039 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
9ef8ca99 | 2040 | else |
535ef6e1 MC |
2041 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
2042 | tg3_writephy(tp, reg, phy); | |
9ef8ca99 | 2043 | } |
535ef6e1 | 2044 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); |
9ef8ca99 MC |
2045 | } |
2046 | } else { | |
15ee95c3 MC |
2047 | int ret; |
2048 | ||
2049 | ret = tg3_phy_auxctl_read(tp, | |
2050 | MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); | |
2051 | if (!ret) { | |
9ef8ca99 MC |
2052 | if (enable) |
2053 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
2054 | else | |
2055 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
b4bd2929 MC |
2056 | tg3_phy_auxctl_write(tp, |
2057 | MII_TG3_AUXCTL_SHDWSEL_MISC, phy); | |
9ef8ca99 MC |
2058 | } |
2059 | } | |
2060 | } | |
2061 | ||
1da177e4 LT |
2062 | static void tg3_phy_set_wirespeed(struct tg3 *tp) |
2063 | { | |
15ee95c3 | 2064 | int ret; |
1da177e4 LT |
2065 | u32 val; |
2066 | ||
f07e9af3 | 2067 | if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) |
1da177e4 LT |
2068 | return; |
2069 | ||
15ee95c3 MC |
2070 | ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); |
2071 | if (!ret) | |
b4bd2929 MC |
2072 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, |
2073 | val | MII_TG3_AUXCTL_MISC_WIRESPD_EN); | |
1da177e4 LT |
2074 | } |
2075 | ||
b2a5c19c MC |
2076 | static void tg3_phy_apply_otp(struct tg3 *tp) |
2077 | { | |
2078 | u32 otp, phy; | |
2079 | ||
2080 | if (!tp->phy_otp) | |
2081 | return; | |
2082 | ||
2083 | otp = tp->phy_otp; | |
2084 | ||
1d36ba45 MC |
2085 | if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) |
2086 | return; | |
b2a5c19c MC |
2087 | |
2088 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
2089 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
2090 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
2091 | ||
2092 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
2093 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
2094 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
2095 | ||
2096 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
2097 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
2098 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
2099 | ||
2100 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
2101 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
2102 | ||
2103 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
2104 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
2105 | ||
2106 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
2107 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
2108 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
2109 | ||
1d36ba45 | 2110 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
b2a5c19c MC |
2111 | } |
2112 | ||
52b02d04 MC |
2113 | static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) |
2114 | { | |
2115 | u32 val; | |
2116 | ||
2117 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) | |
2118 | return; | |
2119 | ||
2120 | tp->setlpicnt = 0; | |
2121 | ||
2122 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | |
2123 | current_link_up == 1 && | |
a6b68dab MC |
2124 | tp->link_config.active_duplex == DUPLEX_FULL && |
2125 | (tp->link_config.active_speed == SPEED_100 || | |
2126 | tp->link_config.active_speed == SPEED_1000)) { | |
52b02d04 MC |
2127 | u32 eeectl; |
2128 | ||
2129 | if (tp->link_config.active_speed == SPEED_1000) | |
2130 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US; | |
2131 | else | |
2132 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US; | |
2133 | ||
2134 | tw32(TG3_CPMU_EEE_CTRL, eeectl); | |
2135 | ||
3110f5f5 MC |
2136 | tg3_phy_cl45_read(tp, MDIO_MMD_AN, |
2137 | TG3_CL45_D7_EEERES_STAT, &val); | |
52b02d04 | 2138 | |
b0c5943f MC |
2139 | if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T || |
2140 | val == TG3_CL45_D7_EEERES_STAT_LP_100TX) | |
52b02d04 MC |
2141 | tp->setlpicnt = 2; |
2142 | } | |
2143 | ||
2144 | if (!tp->setlpicnt) { | |
b715ce94 MC |
2145 | if (current_link_up == 1 && |
2146 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
2147 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); | |
2148 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2149 | } | |
2150 | ||
52b02d04 MC |
2151 | val = tr32(TG3_CPMU_EEE_MODE); |
2152 | tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
2153 | } | |
2154 | } | |
2155 | ||
b0c5943f MC |
2156 | static void tg3_phy_eee_enable(struct tg3 *tp) |
2157 | { | |
2158 | u32 val; | |
2159 | ||
2160 | if (tp->link_config.active_speed == SPEED_1000 && | |
2161 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2162 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
2163 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) && | |
2164 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
b715ce94 MC |
2165 | val = MII_TG3_DSP_TAP26_ALNOKO | |
2166 | MII_TG3_DSP_TAP26_RMRXSTO; | |
2167 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); | |
b0c5943f MC |
2168 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
2169 | } | |
2170 | ||
2171 | val = tr32(TG3_CPMU_EEE_MODE); | |
2172 | tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE); | |
2173 | } | |
2174 | ||
1da177e4 LT |
2175 | static int tg3_wait_macro_done(struct tg3 *tp) |
2176 | { | |
2177 | int limit = 100; | |
2178 | ||
2179 | while (limit--) { | |
2180 | u32 tmp32; | |
2181 | ||
f08aa1a8 | 2182 | if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { |
1da177e4 LT |
2183 | if ((tmp32 & 0x1000) == 0) |
2184 | break; | |
2185 | } | |
2186 | } | |
d4675b52 | 2187 | if (limit < 0) |
1da177e4 LT |
2188 | return -EBUSY; |
2189 | ||
2190 | return 0; | |
2191 | } | |
2192 | ||
2193 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
2194 | { | |
2195 | static const u32 test_pat[4][6] = { | |
2196 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
2197 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
2198 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
2199 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
2200 | }; | |
2201 | int chan; | |
2202 | ||
2203 | for (chan = 0; chan < 4; chan++) { | |
2204 | int i; | |
2205 | ||
2206 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
2207 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 2208 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
2209 | |
2210 | for (i = 0; i < 6; i++) | |
2211 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
2212 | test_pat[chan][i]); | |
2213 | ||
f08aa1a8 | 2214 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
2215 | if (tg3_wait_macro_done(tp)) { |
2216 | *resetp = 1; | |
2217 | return -EBUSY; | |
2218 | } | |
2219 | ||
2220 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
2221 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 2222 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); |
1da177e4 LT |
2223 | if (tg3_wait_macro_done(tp)) { |
2224 | *resetp = 1; | |
2225 | return -EBUSY; | |
2226 | } | |
2227 | ||
f08aa1a8 | 2228 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); |
1da177e4 LT |
2229 | if (tg3_wait_macro_done(tp)) { |
2230 | *resetp = 1; | |
2231 | return -EBUSY; | |
2232 | } | |
2233 | ||
2234 | for (i = 0; i < 6; i += 2) { | |
2235 | u32 low, high; | |
2236 | ||
2237 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
2238 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
2239 | tg3_wait_macro_done(tp)) { | |
2240 | *resetp = 1; | |
2241 | return -EBUSY; | |
2242 | } | |
2243 | low &= 0x7fff; | |
2244 | high &= 0x000f; | |
2245 | if (low != test_pat[chan][i] || | |
2246 | high != test_pat[chan][i+1]) { | |
2247 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
2248 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
2249 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
2250 | ||
2251 | return -EBUSY; | |
2252 | } | |
2253 | } | |
2254 | } | |
2255 | ||
2256 | return 0; | |
2257 | } | |
2258 | ||
2259 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
2260 | { | |
2261 | int chan; | |
2262 | ||
2263 | for (chan = 0; chan < 4; chan++) { | |
2264 | int i; | |
2265 | ||
2266 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
2267 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 2268 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
2269 | for (i = 0; i < 6; i++) |
2270 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
f08aa1a8 | 2271 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
2272 | if (tg3_wait_macro_done(tp)) |
2273 | return -EBUSY; | |
2274 | } | |
2275 | ||
2276 | return 0; | |
2277 | } | |
2278 | ||
2279 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
2280 | { | |
2281 | u32 reg32, phy9_orig; | |
2282 | int retries, do_phy_reset, err; | |
2283 | ||
2284 | retries = 10; | |
2285 | do_phy_reset = 1; | |
2286 | do { | |
2287 | if (do_phy_reset) { | |
2288 | err = tg3_bmcr_reset(tp); | |
2289 | if (err) | |
2290 | return err; | |
2291 | do_phy_reset = 0; | |
2292 | } | |
2293 | ||
2294 | /* Disable transmitter and interrupt. */ | |
2295 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
2296 | continue; | |
2297 | ||
2298 | reg32 |= 0x3000; | |
2299 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2300 | ||
2301 | /* Set full-duplex, 1000 mbps. */ | |
2302 | tg3_writephy(tp, MII_BMCR, | |
221c5637 | 2303 | BMCR_FULLDPLX | BMCR_SPEED1000); |
1da177e4 LT |
2304 | |
2305 | /* Set to master mode. */ | |
221c5637 | 2306 | if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) |
1da177e4 LT |
2307 | continue; |
2308 | ||
221c5637 MC |
2309 | tg3_writephy(tp, MII_CTRL1000, |
2310 | CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER); | |
1da177e4 | 2311 | |
1d36ba45 MC |
2312 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
2313 | if (err) | |
2314 | return err; | |
1da177e4 LT |
2315 | |
2316 | /* Block the PHY control access. */ | |
6ee7c0a0 | 2317 | tg3_phydsp_write(tp, 0x8005, 0x0800); |
1da177e4 LT |
2318 | |
2319 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
2320 | if (!err) | |
2321 | break; | |
2322 | } while (--retries); | |
2323 | ||
2324 | err = tg3_phy_reset_chanpat(tp); | |
2325 | if (err) | |
2326 | return err; | |
2327 | ||
6ee7c0a0 | 2328 | tg3_phydsp_write(tp, 0x8005, 0x0000); |
1da177e4 LT |
2329 | |
2330 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
f08aa1a8 | 2331 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); |
1da177e4 | 2332 | |
1d36ba45 | 2333 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2334 | |
221c5637 | 2335 | tg3_writephy(tp, MII_CTRL1000, phy9_orig); |
1da177e4 LT |
2336 | |
2337 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
2338 | reg32 &= ~0x3000; | |
2339 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2340 | } else if (!err) | |
2341 | err = -EBUSY; | |
2342 | ||
2343 | return err; | |
2344 | } | |
2345 | ||
2346 | /* This will reset the tigon3 PHY if there is no valid | |
2347 | * link unless the FORCE argument is non-zero. | |
2348 | */ | |
2349 | static int tg3_phy_reset(struct tg3 *tp) | |
2350 | { | |
f833c4c1 | 2351 | u32 val, cpmuctrl; |
1da177e4 LT |
2352 | int err; |
2353 | ||
60189ddf | 2354 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2355 | val = tr32(GRC_MISC_CFG); |
2356 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
2357 | udelay(40); | |
2358 | } | |
f833c4c1 MC |
2359 | err = tg3_readphy(tp, MII_BMSR, &val); |
2360 | err |= tg3_readphy(tp, MII_BMSR, &val); | |
1da177e4 LT |
2361 | if (err != 0) |
2362 | return -EBUSY; | |
2363 | ||
c8e1e82b MC |
2364 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { |
2365 | netif_carrier_off(tp->dev); | |
2366 | tg3_link_report(tp); | |
2367 | } | |
2368 | ||
1da177e4 LT |
2369 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
2370 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2371 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
2372 | err = tg3_phy_reset_5703_4_5(tp); | |
2373 | if (err) | |
2374 | return err; | |
2375 | goto out; | |
2376 | } | |
2377 | ||
b2a5c19c MC |
2378 | cpmuctrl = 0; |
2379 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
2380 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
2381 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
2382 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
2383 | tw32(TG3_CPMU_CTRL, | |
2384 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
2385 | } | |
2386 | ||
1da177e4 LT |
2387 | err = tg3_bmcr_reset(tp); |
2388 | if (err) | |
2389 | return err; | |
2390 | ||
b2a5c19c | 2391 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { |
f833c4c1 MC |
2392 | val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; |
2393 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); | |
b2a5c19c MC |
2394 | |
2395 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
2396 | } | |
2397 | ||
bcb37f6c MC |
2398 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2399 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2400 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2401 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
2402 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
2403 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2404 | udelay(40); | |
2405 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2406 | } | |
2407 | } | |
2408 | ||
63c3a66f | 2409 | if (tg3_flag(tp, 5717_PLUS) && |
f07e9af3 | 2410 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) |
ecf1410b MC |
2411 | return 0; |
2412 | ||
b2a5c19c MC |
2413 | tg3_phy_apply_otp(tp); |
2414 | ||
f07e9af3 | 2415 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
2416 | tg3_phy_toggle_apd(tp, true); |
2417 | else | |
2418 | tg3_phy_toggle_apd(tp, false); | |
2419 | ||
1da177e4 | 2420 | out: |
1d36ba45 MC |
2421 | if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && |
2422 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
6ee7c0a0 MC |
2423 | tg3_phydsp_write(tp, 0x201f, 0x2aaa); |
2424 | tg3_phydsp_write(tp, 0x000a, 0x0323); | |
1d36ba45 | 2425 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2426 | } |
1d36ba45 | 2427 | |
f07e9af3 | 2428 | if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { |
f08aa1a8 MC |
2429 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); |
2430 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
1da177e4 | 2431 | } |
1d36ba45 | 2432 | |
f07e9af3 | 2433 | if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { |
1d36ba45 MC |
2434 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2435 | tg3_phydsp_write(tp, 0x000a, 0x310b); | |
2436 | tg3_phydsp_write(tp, 0x201f, 0x9506); | |
2437 | tg3_phydsp_write(tp, 0x401f, 0x14e2); | |
2438 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2439 | } | |
f07e9af3 | 2440 | } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { |
1d36ba45 MC |
2441 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2442 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
2443 | if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { | |
2444 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); | |
2445 | tg3_writephy(tp, MII_TG3_TEST1, | |
2446 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
2447 | } else | |
2448 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
2449 | ||
2450 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2451 | } | |
c424cb24 | 2452 | } |
1d36ba45 | 2453 | |
1da177e4 LT |
2454 | /* Set Extended packet length bit (bit 14) on all chips that */ |
2455 | /* support jumbo frames */ | |
79eb6904 | 2456 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 | 2457 | /* Cannot do read-modify-write on 5401 */ |
b4bd2929 | 2458 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
63c3a66f | 2459 | } else if (tg3_flag(tp, JUMBO_CAPABLE)) { |
1da177e4 | 2460 | /* Set bit 14 with read-modify-write to preserve other bits */ |
15ee95c3 MC |
2461 | err = tg3_phy_auxctl_read(tp, |
2462 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); | |
2463 | if (!err) | |
b4bd2929 MC |
2464 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, |
2465 | val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN); | |
1da177e4 LT |
2466 | } |
2467 | ||
2468 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
2469 | * jumbo frames transmission. | |
2470 | */ | |
63c3a66f | 2471 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
f833c4c1 | 2472 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) |
c6cdf436 | 2473 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
f833c4c1 | 2474 | val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); |
1da177e4 LT |
2475 | } |
2476 | ||
715116a1 | 2477 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
715116a1 | 2478 | /* adjust output voltage */ |
535ef6e1 | 2479 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
715116a1 MC |
2480 | } |
2481 | ||
9ef8ca99 | 2482 | tg3_phy_toggle_automdix(tp, 1); |
1da177e4 LT |
2483 | tg3_phy_set_wirespeed(tp); |
2484 | return 0; | |
2485 | } | |
2486 | ||
3a1e19d3 MC |
2487 | #define TG3_GPIO_MSG_DRVR_PRES 0x00000001 |
2488 | #define TG3_GPIO_MSG_NEED_VAUX 0x00000002 | |
2489 | #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \ | |
2490 | TG3_GPIO_MSG_NEED_VAUX) | |
2491 | #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \ | |
2492 | ((TG3_GPIO_MSG_DRVR_PRES << 0) | \ | |
2493 | (TG3_GPIO_MSG_DRVR_PRES << 4) | \ | |
2494 | (TG3_GPIO_MSG_DRVR_PRES << 8) | \ | |
2495 | (TG3_GPIO_MSG_DRVR_PRES << 12)) | |
2496 | ||
2497 | #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \ | |
2498 | ((TG3_GPIO_MSG_NEED_VAUX << 0) | \ | |
2499 | (TG3_GPIO_MSG_NEED_VAUX << 4) | \ | |
2500 | (TG3_GPIO_MSG_NEED_VAUX << 8) | \ | |
2501 | (TG3_GPIO_MSG_NEED_VAUX << 12)) | |
2502 | ||
2503 | static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) | |
2504 | { | |
2505 | u32 status, shift; | |
2506 | ||
2507 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2508 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
2509 | status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG); | |
2510 | else | |
2511 | status = tr32(TG3_CPMU_DRV_STATUS); | |
2512 | ||
2513 | shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; | |
2514 | status &= ~(TG3_GPIO_MSG_MASK << shift); | |
2515 | status |= (newstat << shift); | |
2516 | ||
2517 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2518 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
2519 | tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status); | |
2520 | else | |
2521 | tw32(TG3_CPMU_DRV_STATUS, status); | |
2522 | ||
2523 | return status >> TG3_APE_GPIO_MSG_SHIFT; | |
2524 | } | |
2525 | ||
520b2756 MC |
2526 | static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) |
2527 | { | |
2528 | if (!tg3_flag(tp, IS_NIC)) | |
2529 | return 0; | |
2530 | ||
3a1e19d3 MC |
2531 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2532 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
2533 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
2534 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | |
2535 | return -EIO; | |
520b2756 | 2536 | |
3a1e19d3 MC |
2537 | tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES); |
2538 | ||
2539 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, | |
2540 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2541 | ||
2542 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); | |
2543 | } else { | |
2544 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, | |
2545 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2546 | } | |
6f5c8f83 | 2547 | |
520b2756 MC |
2548 | return 0; |
2549 | } | |
2550 | ||
2551 | static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) | |
2552 | { | |
2553 | u32 grc_local_ctrl; | |
2554 | ||
2555 | if (!tg3_flag(tp, IS_NIC) || | |
2556 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2557 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) | |
2558 | return; | |
2559 | ||
2560 | grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; | |
2561 | ||
2562 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2563 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, | |
2564 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2565 | ||
2566 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2567 | grc_local_ctrl, | |
2568 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2569 | ||
2570 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2571 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, | |
2572 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2573 | } | |
2574 | ||
2575 | static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) | |
2576 | { | |
2577 | if (!tg3_flag(tp, IS_NIC)) | |
2578 | return; | |
2579 | ||
2580 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2581 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2582 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2583 | (GRC_LCLCTRL_GPIO_OE0 | | |
2584 | GRC_LCLCTRL_GPIO_OE1 | | |
2585 | GRC_LCLCTRL_GPIO_OE2 | | |
2586 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2587 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
2588 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2589 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || | |
2590 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
2591 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ | |
2592 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
2593 | GRC_LCLCTRL_GPIO_OE1 | | |
2594 | GRC_LCLCTRL_GPIO_OE2 | | |
2595 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2596 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2597 | tp->grc_local_ctrl; | |
2598 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2599 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2600 | ||
2601 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2602 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2603 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2604 | ||
2605 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2606 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2607 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2608 | } else { | |
2609 | u32 no_gpio2; | |
2610 | u32 grc_local_ctrl = 0; | |
2611 | ||
2612 | /* Workaround to prevent overdrawing Amps. */ | |
2613 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
2614 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
2615 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2616 | grc_local_ctrl, | |
2617 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2618 | } | |
2619 | ||
2620 | /* On 5753 and variants, GPIO2 cannot be used. */ | |
2621 | no_gpio2 = tp->nic_sram_data_cfg & | |
2622 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2623 | ||
2624 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
2625 | GRC_LCLCTRL_GPIO_OE1 | | |
2626 | GRC_LCLCTRL_GPIO_OE2 | | |
2627 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2628 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2629 | if (no_gpio2) { | |
2630 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2631 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2632 | } | |
2633 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2634 | tp->grc_local_ctrl | grc_local_ctrl, | |
2635 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2636 | ||
2637 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2638 | ||
2639 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2640 | tp->grc_local_ctrl | grc_local_ctrl, | |
2641 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2642 | ||
2643 | if (!no_gpio2) { | |
2644 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
2645 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2646 | tp->grc_local_ctrl | grc_local_ctrl, | |
2647 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2648 | } | |
2649 | } | |
3a1e19d3 MC |
2650 | } |
2651 | ||
cd0d7228 | 2652 | static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable) |
3a1e19d3 MC |
2653 | { |
2654 | u32 msg = 0; | |
2655 | ||
2656 | /* Serialize power state transitions */ | |
2657 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | |
2658 | return; | |
2659 | ||
cd0d7228 | 2660 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable) |
3a1e19d3 MC |
2661 | msg = TG3_GPIO_MSG_NEED_VAUX; |
2662 | ||
2663 | msg = tg3_set_function_status(tp, msg); | |
2664 | ||
2665 | if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK) | |
2666 | goto done; | |
6f5c8f83 | 2667 | |
3a1e19d3 MC |
2668 | if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK) |
2669 | tg3_pwrsrc_switch_to_vaux(tp); | |
2670 | else | |
2671 | tg3_pwrsrc_die_with_vmain(tp); | |
2672 | ||
2673 | done: | |
6f5c8f83 | 2674 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); |
520b2756 MC |
2675 | } |
2676 | ||
cd0d7228 | 2677 | static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol) |
1da177e4 | 2678 | { |
683644b7 | 2679 | bool need_vaux = false; |
1da177e4 | 2680 | |
334355aa | 2681 | /* The GPIOs do something completely different on 57765. */ |
63c3a66f | 2682 | if (!tg3_flag(tp, IS_NIC) || |
334355aa | 2683 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
1da177e4 LT |
2684 | return; |
2685 | ||
3a1e19d3 MC |
2686 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2687 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
2688 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
cd0d7228 MC |
2689 | tg3_frob_aux_power_5717(tp, include_wol ? |
2690 | tg3_flag(tp, WOL_ENABLE) != 0 : 0); | |
3a1e19d3 MC |
2691 | return; |
2692 | } | |
2693 | ||
2694 | if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { | |
8c2dc7e1 MC |
2695 | struct net_device *dev_peer; |
2696 | ||
2697 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
683644b7 | 2698 | |
bc1c7567 | 2699 | /* remove_one() may have been run on the peer. */ |
683644b7 MC |
2700 | if (dev_peer) { |
2701 | struct tg3 *tp_peer = netdev_priv(dev_peer); | |
2702 | ||
63c3a66f | 2703 | if (tg3_flag(tp_peer, INIT_COMPLETE)) |
683644b7 MC |
2704 | return; |
2705 | ||
cd0d7228 | 2706 | if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) || |
63c3a66f | 2707 | tg3_flag(tp_peer, ENABLE_ASF)) |
683644b7 MC |
2708 | need_vaux = true; |
2709 | } | |
1da177e4 LT |
2710 | } |
2711 | ||
cd0d7228 MC |
2712 | if ((include_wol && tg3_flag(tp, WOL_ENABLE)) || |
2713 | tg3_flag(tp, ENABLE_ASF)) | |
683644b7 MC |
2714 | need_vaux = true; |
2715 | ||
520b2756 MC |
2716 | if (need_vaux) |
2717 | tg3_pwrsrc_switch_to_vaux(tp); | |
2718 | else | |
2719 | tg3_pwrsrc_die_with_vmain(tp); | |
1da177e4 LT |
2720 | } |
2721 | ||
e8f3f6ca MC |
2722 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) |
2723 | { | |
2724 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2725 | return 1; | |
79eb6904 | 2726 | else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { |
e8f3f6ca MC |
2727 | if (speed != SPEED_10) |
2728 | return 1; | |
2729 | } else if (speed == SPEED_10) | |
2730 | return 1; | |
2731 | ||
2732 | return 0; | |
2733 | } | |
2734 | ||
1da177e4 | 2735 | static int tg3_setup_phy(struct tg3 *, int); |
1da177e4 LT |
2736 | static int tg3_halt_cpu(struct tg3 *, u32); |
2737 | ||
0a459aac | 2738 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
15c3b696 | 2739 | { |
ce057f01 MC |
2740 | u32 val; |
2741 | ||
f07e9af3 | 2742 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
5129724a MC |
2743 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
2744 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2745 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2746 | ||
2747 | sg_dig_ctrl |= | |
2748 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2749 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2750 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2751 | } | |
3f7045c1 | 2752 | return; |
5129724a | 2753 | } |
3f7045c1 | 2754 | |
60189ddf | 2755 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2756 | tg3_bmcr_reset(tp); |
2757 | val = tr32(GRC_MISC_CFG); | |
2758 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2759 | udelay(40); | |
2760 | return; | |
f07e9af3 | 2761 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
0e5f784c MC |
2762 | u32 phytest; |
2763 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2764 | u32 phy; | |
2765 | ||
2766 | tg3_writephy(tp, MII_ADVERTISE, 0); | |
2767 | tg3_writephy(tp, MII_BMCR, | |
2768 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2769 | ||
2770 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2771 | phytest | MII_TG3_FET_SHADOW_EN); | |
2772 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | |
2773 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | |
2774 | tg3_writephy(tp, | |
2775 | MII_TG3_FET_SHDW_AUXMODE4, | |
2776 | phy); | |
2777 | } | |
2778 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2779 | } | |
2780 | return; | |
0a459aac | 2781 | } else if (do_low_power) { |
715116a1 MC |
2782 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2783 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
0a459aac | 2784 | |
b4bd2929 MC |
2785 | val = MII_TG3_AUXCTL_PCTL_100TX_LPWR | |
2786 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2787 | MII_TG3_AUXCTL_PCTL_VREG_11V; | |
2788 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); | |
715116a1 | 2789 | } |
3f7045c1 | 2790 | |
15c3b696 MC |
2791 | /* The PHY should not be powered down on some chips because |
2792 | * of bugs. | |
2793 | */ | |
2794 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2795 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2796 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
f07e9af3 | 2797 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
15c3b696 | 2798 | return; |
ce057f01 | 2799 | |
bcb37f6c MC |
2800 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2801 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2802 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2803 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2804 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2805 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2806 | } | |
2807 | ||
15c3b696 MC |
2808 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); |
2809 | } | |
2810 | ||
ffbcfed4 MC |
2811 | /* tp->lock is held. */ |
2812 | static int tg3_nvram_lock(struct tg3 *tp) | |
2813 | { | |
63c3a66f | 2814 | if (tg3_flag(tp, NVRAM)) { |
ffbcfed4 MC |
2815 | int i; |
2816 | ||
2817 | if (tp->nvram_lock_cnt == 0) { | |
2818 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2819 | for (i = 0; i < 8000; i++) { | |
2820 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2821 | break; | |
2822 | udelay(20); | |
2823 | } | |
2824 | if (i == 8000) { | |
2825 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2826 | return -ENODEV; | |
2827 | } | |
2828 | } | |
2829 | tp->nvram_lock_cnt++; | |
2830 | } | |
2831 | return 0; | |
2832 | } | |
2833 | ||
2834 | /* tp->lock is held. */ | |
2835 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2836 | { | |
63c3a66f | 2837 | if (tg3_flag(tp, NVRAM)) { |
ffbcfed4 MC |
2838 | if (tp->nvram_lock_cnt > 0) |
2839 | tp->nvram_lock_cnt--; | |
2840 | if (tp->nvram_lock_cnt == 0) | |
2841 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2842 | } | |
2843 | } | |
2844 | ||
2845 | /* tp->lock is held. */ | |
2846 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2847 | { | |
63c3a66f | 2848 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2849 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2850 | ||
2851 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
2852 | } | |
2853 | } | |
2854 | ||
2855 | /* tp->lock is held. */ | |
2856 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
2857 | { | |
63c3a66f | 2858 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2859 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2860 | ||
2861 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
2862 | } | |
2863 | } | |
2864 | ||
2865 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
2866 | u32 offset, u32 *val) | |
2867 | { | |
2868 | u32 tmp; | |
2869 | int i; | |
2870 | ||
2871 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
2872 | return -EINVAL; | |
2873 | ||
2874 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
2875 | EEPROM_ADDR_DEVID_MASK | | |
2876 | EEPROM_ADDR_READ); | |
2877 | tw32(GRC_EEPROM_ADDR, | |
2878 | tmp | | |
2879 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
2880 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
2881 | EEPROM_ADDR_ADDR_MASK) | | |
2882 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
2883 | ||
2884 | for (i = 0; i < 1000; i++) { | |
2885 | tmp = tr32(GRC_EEPROM_ADDR); | |
2886 | ||
2887 | if (tmp & EEPROM_ADDR_COMPLETE) | |
2888 | break; | |
2889 | msleep(1); | |
2890 | } | |
2891 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
2892 | return -EBUSY; | |
2893 | ||
62cedd11 MC |
2894 | tmp = tr32(GRC_EEPROM_DATA); |
2895 | ||
2896 | /* | |
2897 | * The data will always be opposite the native endian | |
2898 | * format. Perform a blind byteswap to compensate. | |
2899 | */ | |
2900 | *val = swab32(tmp); | |
2901 | ||
ffbcfed4 MC |
2902 | return 0; |
2903 | } | |
2904 | ||
2905 | #define NVRAM_CMD_TIMEOUT 10000 | |
2906 | ||
2907 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
2908 | { | |
2909 | int i; | |
2910 | ||
2911 | tw32(NVRAM_CMD, nvram_cmd); | |
2912 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
2913 | udelay(10); | |
2914 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
2915 | udelay(10); | |
2916 | break; | |
2917 | } | |
2918 | } | |
2919 | ||
2920 | if (i == NVRAM_CMD_TIMEOUT) | |
2921 | return -EBUSY; | |
2922 | ||
2923 | return 0; | |
2924 | } | |
2925 | ||
2926 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
2927 | { | |
63c3a66f JP |
2928 | if (tg3_flag(tp, NVRAM) && |
2929 | tg3_flag(tp, NVRAM_BUFFERED) && | |
2930 | tg3_flag(tp, FLASH) && | |
2931 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
ffbcfed4 MC |
2932 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
2933 | ||
2934 | addr = ((addr / tp->nvram_pagesize) << | |
2935 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
2936 | (addr % tp->nvram_pagesize); | |
2937 | ||
2938 | return addr; | |
2939 | } | |
2940 | ||
2941 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
2942 | { | |
63c3a66f JP |
2943 | if (tg3_flag(tp, NVRAM) && |
2944 | tg3_flag(tp, NVRAM_BUFFERED) && | |
2945 | tg3_flag(tp, FLASH) && | |
2946 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
ffbcfed4 MC |
2947 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
2948 | ||
2949 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
2950 | tp->nvram_pagesize) + | |
2951 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
2952 | ||
2953 | return addr; | |
2954 | } | |
2955 | ||
e4f34110 MC |
2956 | /* NOTE: Data read in from NVRAM is byteswapped according to |
2957 | * the byteswapping settings for all other register accesses. | |
2958 | * tg3 devices are BE devices, so on a BE machine, the data | |
2959 | * returned will be exactly as it is seen in NVRAM. On a LE | |
2960 | * machine, the 32-bit value will be byteswapped. | |
2961 | */ | |
ffbcfed4 MC |
2962 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
2963 | { | |
2964 | int ret; | |
2965 | ||
63c3a66f | 2966 | if (!tg3_flag(tp, NVRAM)) |
ffbcfed4 MC |
2967 | return tg3_nvram_read_using_eeprom(tp, offset, val); |
2968 | ||
2969 | offset = tg3_nvram_phys_addr(tp, offset); | |
2970 | ||
2971 | if (offset > NVRAM_ADDR_MSK) | |
2972 | return -EINVAL; | |
2973 | ||
2974 | ret = tg3_nvram_lock(tp); | |
2975 | if (ret) | |
2976 | return ret; | |
2977 | ||
2978 | tg3_enable_nvram_access(tp); | |
2979 | ||
2980 | tw32(NVRAM_ADDR, offset); | |
2981 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
2982 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
2983 | ||
2984 | if (ret == 0) | |
e4f34110 | 2985 | *val = tr32(NVRAM_RDDATA); |
ffbcfed4 MC |
2986 | |
2987 | tg3_disable_nvram_access(tp); | |
2988 | ||
2989 | tg3_nvram_unlock(tp); | |
2990 | ||
2991 | return ret; | |
2992 | } | |
2993 | ||
a9dc529d MC |
2994 | /* Ensures NVRAM data is in bytestream format. */ |
2995 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
ffbcfed4 MC |
2996 | { |
2997 | u32 v; | |
a9dc529d | 2998 | int res = tg3_nvram_read(tp, offset, &v); |
ffbcfed4 | 2999 | if (!res) |
a9dc529d | 3000 | *val = cpu_to_be32(v); |
ffbcfed4 MC |
3001 | return res; |
3002 | } | |
3003 | ||
997b4f13 MC |
3004 | #define RX_CPU_SCRATCH_BASE 0x30000 |
3005 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
3006 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
3007 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
3008 | ||
3009 | /* tp->lock is held. */ | |
3010 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
3011 | { | |
3012 | int i; | |
3013 | ||
3014 | BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); | |
3015 | ||
3016 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
3017 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
3018 | ||
3019 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
3020 | return 0; | |
3021 | } | |
3022 | if (offset == RX_CPU_BASE) { | |
3023 | for (i = 0; i < 10000; i++) { | |
3024 | tw32(offset + CPU_STATE, 0xffffffff); | |
3025 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
3026 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
3027 | break; | |
3028 | } | |
3029 | ||
3030 | tw32(offset + CPU_STATE, 0xffffffff); | |
3031 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
3032 | udelay(10); | |
3033 | } else { | |
3034 | for (i = 0; i < 10000; i++) { | |
3035 | tw32(offset + CPU_STATE, 0xffffffff); | |
3036 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
3037 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
3038 | break; | |
3039 | } | |
3040 | } | |
3041 | ||
3042 | if (i >= 10000) { | |
3043 | netdev_err(tp->dev, "%s timed out, %s CPU\n", | |
3044 | __func__, offset == RX_CPU_BASE ? "RX" : "TX"); | |
3045 | return -ENODEV; | |
3046 | } | |
3047 | ||
3048 | /* Clear firmware's nvram arbitration. */ | |
3049 | if (tg3_flag(tp, NVRAM)) | |
3050 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); | |
3051 | return 0; | |
3052 | } | |
3053 | ||
3054 | struct fw_info { | |
3055 | unsigned int fw_base; | |
3056 | unsigned int fw_len; | |
3057 | const __be32 *fw_data; | |
3058 | }; | |
3059 | ||
3060 | /* tp->lock is held. */ | |
3061 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, | |
3062 | u32 cpu_scratch_base, int cpu_scratch_size, | |
3063 | struct fw_info *info) | |
3064 | { | |
3065 | int err, lock_err, i; | |
3066 | void (*write_op)(struct tg3 *, u32, u32); | |
3067 | ||
3068 | if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { | |
3069 | netdev_err(tp->dev, | |
3070 | "%s: Trying to load TX cpu firmware which is 5705\n", | |
3071 | __func__); | |
3072 | return -EINVAL; | |
3073 | } | |
3074 | ||
3075 | if (tg3_flag(tp, 5705_PLUS)) | |
3076 | write_op = tg3_write_mem; | |
3077 | else | |
3078 | write_op = tg3_write_indirect_reg32; | |
3079 | ||
3080 | /* It is possible that bootcode is still loading at this point. | |
3081 | * Get the nvram lock first before halting the cpu. | |
3082 | */ | |
3083 | lock_err = tg3_nvram_lock(tp); | |
3084 | err = tg3_halt_cpu(tp, cpu_base); | |
3085 | if (!lock_err) | |
3086 | tg3_nvram_unlock(tp); | |
3087 | if (err) | |
3088 | goto out; | |
3089 | ||
3090 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
3091 | write_op(tp, cpu_scratch_base + i, 0); | |
3092 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3093 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
3094 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) | |
3095 | write_op(tp, (cpu_scratch_base + | |
3096 | (info->fw_base & 0xffff) + | |
3097 | (i * sizeof(u32))), | |
3098 | be32_to_cpu(info->fw_data[i])); | |
3099 | ||
3100 | err = 0; | |
3101 | ||
3102 | out: | |
3103 | return err; | |
3104 | } | |
3105 | ||
3106 | /* tp->lock is held. */ | |
3107 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
3108 | { | |
3109 | struct fw_info info; | |
3110 | const __be32 *fw_data; | |
3111 | int err, i; | |
3112 | ||
3113 | fw_data = (void *)tp->fw->data; | |
3114 | ||
3115 | /* Firmware blob starts with version numbers, followed by | |
3116 | start address and length. We are setting complete length. | |
3117 | length = end_address_of_bss - start_address_of_text. | |
3118 | Remainder is the blob to be loaded contiguously | |
3119 | from start address. */ | |
3120 | ||
3121 | info.fw_base = be32_to_cpu(fw_data[1]); | |
3122 | info.fw_len = tp->fw->size - 12; | |
3123 | info.fw_data = &fw_data[3]; | |
3124 | ||
3125 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
3126 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
3127 | &info); | |
3128 | if (err) | |
3129 | return err; | |
3130 | ||
3131 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
3132 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
3133 | &info); | |
3134 | if (err) | |
3135 | return err; | |
3136 | ||
3137 | /* Now startup only the RX cpu. */ | |
3138 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
3139 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | |
3140 | ||
3141 | for (i = 0; i < 5; i++) { | |
3142 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) | |
3143 | break; | |
3144 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
3145 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
3146 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | |
3147 | udelay(1000); | |
3148 | } | |
3149 | if (i >= 5) { | |
3150 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " | |
3151 | "should be %08x\n", __func__, | |
3152 | tr32(RX_CPU_BASE + CPU_PC), info.fw_base); | |
3153 | return -ENODEV; | |
3154 | } | |
3155 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
3156 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
3157 | ||
3158 | return 0; | |
3159 | } | |
3160 | ||
3161 | /* tp->lock is held. */ | |
3162 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
3163 | { | |
3164 | struct fw_info info; | |
3165 | const __be32 *fw_data; | |
3166 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; | |
3167 | int err, i; | |
3168 | ||
3169 | if (tg3_flag(tp, HW_TSO_1) || | |
3170 | tg3_flag(tp, HW_TSO_2) || | |
3171 | tg3_flag(tp, HW_TSO_3)) | |
3172 | return 0; | |
3173 | ||
3174 | fw_data = (void *)tp->fw->data; | |
3175 | ||
3176 | /* Firmware blob starts with version numbers, followed by | |
3177 | start address and length. We are setting complete length. | |
3178 | length = end_address_of_bss - start_address_of_text. | |
3179 | Remainder is the blob to be loaded contiguously | |
3180 | from start address. */ | |
3181 | ||
3182 | info.fw_base = be32_to_cpu(fw_data[1]); | |
3183 | cpu_scratch_size = tp->fw_len; | |
3184 | info.fw_len = tp->fw->size - 12; | |
3185 | info.fw_data = &fw_data[3]; | |
3186 | ||
3187 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
3188 | cpu_base = RX_CPU_BASE; | |
3189 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
3190 | } else { | |
3191 | cpu_base = TX_CPU_BASE; | |
3192 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
3193 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
3194 | } | |
3195 | ||
3196 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
3197 | cpu_scratch_base, cpu_scratch_size, | |
3198 | &info); | |
3199 | if (err) | |
3200 | return err; | |
3201 | ||
3202 | /* Now startup the cpu. */ | |
3203 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3204 | tw32_f(cpu_base + CPU_PC, info.fw_base); | |
3205 | ||
3206 | for (i = 0; i < 5; i++) { | |
3207 | if (tr32(cpu_base + CPU_PC) == info.fw_base) | |
3208 | break; | |
3209 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3210 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
3211 | tw32_f(cpu_base + CPU_PC, info.fw_base); | |
3212 | udelay(1000); | |
3213 | } | |
3214 | if (i >= 5) { | |
3215 | netdev_err(tp->dev, | |
3216 | "%s fails to set CPU PC, is %08x should be %08x\n", | |
3217 | __func__, tr32(cpu_base + CPU_PC), info.fw_base); | |
3218 | return -ENODEV; | |
3219 | } | |
3220 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3221 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
3222 | return 0; | |
3223 | } | |
3224 | ||
3225 | ||
3f007891 MC |
3226 | /* tp->lock is held. */ |
3227 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
3228 | { | |
3229 | u32 addr_high, addr_low; | |
3230 | int i; | |
3231 | ||
3232 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
3233 | tp->dev->dev_addr[1]); | |
3234 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
3235 | (tp->dev->dev_addr[3] << 16) | | |
3236 | (tp->dev->dev_addr[4] << 8) | | |
3237 | (tp->dev->dev_addr[5] << 0)); | |
3238 | for (i = 0; i < 4; i++) { | |
3239 | if (i == 1 && skip_mac_1) | |
3240 | continue; | |
3241 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
3242 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
3243 | } | |
3244 | ||
3245 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3246 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
3247 | for (i = 0; i < 12; i++) { | |
3248 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
3249 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
3250 | } | |
3251 | } | |
3252 | ||
3253 | addr_high = (tp->dev->dev_addr[0] + | |
3254 | tp->dev->dev_addr[1] + | |
3255 | tp->dev->dev_addr[2] + | |
3256 | tp->dev->dev_addr[3] + | |
3257 | tp->dev->dev_addr[4] + | |
3258 | tp->dev->dev_addr[5]) & | |
3259 | TX_BACKOFF_SEED_MASK; | |
3260 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
3261 | } | |
3262 | ||
c866b7ea | 3263 | static void tg3_enable_register_access(struct tg3 *tp) |
1da177e4 | 3264 | { |
c866b7ea RW |
3265 | /* |
3266 | * Make sure register accesses (indirect or otherwise) will function | |
3267 | * correctly. | |
1da177e4 LT |
3268 | */ |
3269 | pci_write_config_dword(tp->pdev, | |
c866b7ea RW |
3270 | TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); |
3271 | } | |
1da177e4 | 3272 | |
c866b7ea RW |
3273 | static int tg3_power_up(struct tg3 *tp) |
3274 | { | |
bed9829f | 3275 | int err; |
8c6bda1a | 3276 | |
bed9829f | 3277 | tg3_enable_register_access(tp); |
1da177e4 | 3278 | |
bed9829f MC |
3279 | err = pci_set_power_state(tp->pdev, PCI_D0); |
3280 | if (!err) { | |
3281 | /* Switch out of Vaux if it is a NIC */ | |
3282 | tg3_pwrsrc_switch_to_vmain(tp); | |
3283 | } else { | |
3284 | netdev_err(tp->dev, "Transition to D0 failed\n"); | |
3285 | } | |
1da177e4 | 3286 | |
bed9829f | 3287 | return err; |
c866b7ea | 3288 | } |
1da177e4 | 3289 | |
c866b7ea RW |
3290 | static int tg3_power_down_prepare(struct tg3 *tp) |
3291 | { | |
3292 | u32 misc_host_ctrl; | |
3293 | bool device_should_wake, do_low_power; | |
3294 | ||
3295 | tg3_enable_register_access(tp); | |
5e7dfd0f MC |
3296 | |
3297 | /* Restore the CLKREQ setting. */ | |
63c3a66f | 3298 | if (tg3_flag(tp, CLKREQ_BUG)) { |
5e7dfd0f MC |
3299 | u16 lnkctl; |
3300 | ||
3301 | pci_read_config_word(tp->pdev, | |
708ebb3a | 3302 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
3303 | &lnkctl); |
3304 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
3305 | pci_write_config_word(tp->pdev, | |
708ebb3a | 3306 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
3307 | lnkctl); |
3308 | } | |
3309 | ||
1da177e4 LT |
3310 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
3311 | tw32(TG3PCI_MISC_HOST_CTRL, | |
3312 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
3313 | ||
c866b7ea | 3314 | device_should_wake = device_may_wakeup(&tp->pdev->dev) && |
63c3a66f | 3315 | tg3_flag(tp, WOL_ENABLE); |
05ac4cb7 | 3316 | |
63c3a66f | 3317 | if (tg3_flag(tp, USE_PHYLIB)) { |
0a459aac | 3318 | do_low_power = false; |
f07e9af3 | 3319 | if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && |
80096068 | 3320 | !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
b02fd9e3 | 3321 | struct phy_device *phydev; |
0a459aac | 3322 | u32 phyid, advertising; |
b02fd9e3 | 3323 | |
3f0e3ad7 | 3324 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 3325 | |
80096068 | 3326 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
b02fd9e3 MC |
3327 | |
3328 | tp->link_config.orig_speed = phydev->speed; | |
3329 | tp->link_config.orig_duplex = phydev->duplex; | |
3330 | tp->link_config.orig_autoneg = phydev->autoneg; | |
3331 | tp->link_config.orig_advertising = phydev->advertising; | |
3332 | ||
3333 | advertising = ADVERTISED_TP | | |
3334 | ADVERTISED_Pause | | |
3335 | ADVERTISED_Autoneg | | |
3336 | ADVERTISED_10baseT_Half; | |
3337 | ||
63c3a66f JP |
3338 | if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { |
3339 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
b02fd9e3 MC |
3340 | advertising |= |
3341 | ADVERTISED_100baseT_Half | | |
3342 | ADVERTISED_100baseT_Full | | |
3343 | ADVERTISED_10baseT_Full; | |
3344 | else | |
3345 | advertising |= ADVERTISED_10baseT_Full; | |
3346 | } | |
3347 | ||
3348 | phydev->advertising = advertising; | |
3349 | ||
3350 | phy_start_aneg(phydev); | |
0a459aac MC |
3351 | |
3352 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
6a443a0f MC |
3353 | if (phyid != PHY_ID_BCMAC131) { |
3354 | phyid &= PHY_BCM_OUI_MASK; | |
3355 | if (phyid == PHY_BCM_OUI_1 || | |
3356 | phyid == PHY_BCM_OUI_2 || | |
3357 | phyid == PHY_BCM_OUI_3) | |
0a459aac MC |
3358 | do_low_power = true; |
3359 | } | |
b02fd9e3 | 3360 | } |
dd477003 | 3361 | } else { |
2023276e | 3362 | do_low_power = true; |
0a459aac | 3363 | |
80096068 MC |
3364 | if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
3365 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
3366 | tp->link_config.orig_speed = tp->link_config.speed; |
3367 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
3368 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
3369 | } | |
1da177e4 | 3370 | |
f07e9af3 | 3371 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
dd477003 MC |
3372 | tp->link_config.speed = SPEED_10; |
3373 | tp->link_config.duplex = DUPLEX_HALF; | |
3374 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
3375 | tg3_setup_phy(tp, 0); | |
3376 | } | |
1da177e4 LT |
3377 | } |
3378 | ||
b5d3772c MC |
3379 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
3380 | u32 val; | |
3381 | ||
3382 | val = tr32(GRC_VCPU_EXT_CTRL); | |
3383 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
63c3a66f | 3384 | } else if (!tg3_flag(tp, ENABLE_ASF)) { |
6921d201 MC |
3385 | int i; |
3386 | u32 val; | |
3387 | ||
3388 | for (i = 0; i < 200; i++) { | |
3389 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
3390 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
3391 | break; | |
3392 | msleep(1); | |
3393 | } | |
3394 | } | |
63c3a66f | 3395 | if (tg3_flag(tp, WOL_CAP)) |
a85feb8c GZ |
3396 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | |
3397 | WOL_DRV_STATE_SHUTDOWN | | |
3398 | WOL_DRV_WOL | | |
3399 | WOL_SET_MAGIC_PKT); | |
6921d201 | 3400 | |
05ac4cb7 | 3401 | if (device_should_wake) { |
1da177e4 LT |
3402 | u32 mac_mode; |
3403 | ||
f07e9af3 | 3404 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
b4bd2929 MC |
3405 | if (do_low_power && |
3406 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
3407 | tg3_phy_auxctl_write(tp, | |
3408 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL, | |
3409 | MII_TG3_AUXCTL_PCTL_WOL_EN | | |
3410 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
3411 | MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC); | |
dd477003 MC |
3412 | udelay(40); |
3413 | } | |
1da177e4 | 3414 | |
f07e9af3 | 3415 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
3f7045c1 MC |
3416 | mac_mode = MAC_MODE_PORT_MODE_GMII; |
3417 | else | |
3418 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
1da177e4 | 3419 | |
e8f3f6ca MC |
3420 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
3421 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
3422 | ASIC_REV_5700) { | |
63c3a66f | 3423 | u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? |
e8f3f6ca MC |
3424 | SPEED_100 : SPEED_10; |
3425 | if (tg3_5700_link_polarity(tp, speed)) | |
3426 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
3427 | else | |
3428 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
3429 | } | |
1da177e4 LT |
3430 | } else { |
3431 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
3432 | } | |
3433 | ||
63c3a66f | 3434 | if (!tg3_flag(tp, 5750_PLUS)) |
1da177e4 LT |
3435 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
3436 | ||
05ac4cb7 | 3437 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; |
63c3a66f JP |
3438 | if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && |
3439 | (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE))) | |
05ac4cb7 | 3440 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; |
1da177e4 | 3441 | |
63c3a66f | 3442 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b MC |
3443 | mac_mode |= MAC_MODE_APE_TX_EN | |
3444 | MAC_MODE_APE_RX_EN | | |
3445 | MAC_MODE_TDE_ENABLE; | |
3bda1258 | 3446 | |
1da177e4 LT |
3447 | tw32_f(MAC_MODE, mac_mode); |
3448 | udelay(100); | |
3449 | ||
3450 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
3451 | udelay(10); | |
3452 | } | |
3453 | ||
63c3a66f | 3454 | if (!tg3_flag(tp, WOL_SPEED_100MB) && |
1da177e4 LT |
3455 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
3456 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
3457 | u32 base_val; | |
3458 | ||
3459 | base_val = tp->pci_clock_ctrl; | |
3460 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
3461 | CLOCK_CTRL_TXCLK_DISABLE); | |
3462 | ||
b401e9e2 MC |
3463 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | |
3464 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
63c3a66f JP |
3465 | } else if (tg3_flag(tp, 5780_CLASS) || |
3466 | tg3_flag(tp, CPMU_PRESENT) || | |
6ff6f81d | 3467 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
4cf78e4f | 3468 | /* do nothing */ |
63c3a66f | 3469 | } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { |
1da177e4 LT |
3470 | u32 newbits1, newbits2; |
3471 | ||
3472 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3473 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3474 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
3475 | CLOCK_CTRL_TXCLK_DISABLE | | |
3476 | CLOCK_CTRL_ALTCLK); | |
3477 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
63c3a66f | 3478 | } else if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
3479 | newbits1 = CLOCK_CTRL_625_CORE; |
3480 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
3481 | } else { | |
3482 | newbits1 = CLOCK_CTRL_ALTCLK; | |
3483 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
3484 | } | |
3485 | ||
b401e9e2 MC |
3486 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, |
3487 | 40); | |
1da177e4 | 3488 | |
b401e9e2 MC |
3489 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, |
3490 | 40); | |
1da177e4 | 3491 | |
63c3a66f | 3492 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
3493 | u32 newbits3; |
3494 | ||
3495 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3496 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3497 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
3498 | CLOCK_CTRL_TXCLK_DISABLE | | |
3499 | CLOCK_CTRL_44MHZ_CORE); | |
3500 | } else { | |
3501 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
3502 | } | |
3503 | ||
b401e9e2 MC |
3504 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
3505 | tp->pci_clock_ctrl | newbits3, 40); | |
1da177e4 LT |
3506 | } |
3507 | } | |
3508 | ||
63c3a66f | 3509 | if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) |
0a459aac | 3510 | tg3_power_down_phy(tp, do_low_power); |
6921d201 | 3511 | |
cd0d7228 | 3512 | tg3_frob_aux_power(tp, true); |
1da177e4 LT |
3513 | |
3514 | /* Workaround for unstable PLL clock */ | |
3515 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
3516 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
3517 | u32 val = tr32(0x7d00); | |
3518 | ||
3519 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
3520 | tw32(0x7d00, val); | |
63c3a66f | 3521 | if (!tg3_flag(tp, ENABLE_ASF)) { |
ec41c7df MC |
3522 | int err; |
3523 | ||
3524 | err = tg3_nvram_lock(tp); | |
1da177e4 | 3525 | tg3_halt_cpu(tp, RX_CPU_BASE); |
ec41c7df MC |
3526 | if (!err) |
3527 | tg3_nvram_unlock(tp); | |
6921d201 | 3528 | } |
1da177e4 LT |
3529 | } |
3530 | ||
bbadf503 MC |
3531 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); |
3532 | ||
c866b7ea RW |
3533 | return 0; |
3534 | } | |
12dac075 | 3535 | |
c866b7ea RW |
3536 | static void tg3_power_down(struct tg3 *tp) |
3537 | { | |
3538 | tg3_power_down_prepare(tp); | |
1da177e4 | 3539 | |
63c3a66f | 3540 | pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); |
c866b7ea | 3541 | pci_set_power_state(tp->pdev, PCI_D3hot); |
1da177e4 LT |
3542 | } |
3543 | ||
1da177e4 LT |
3544 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) |
3545 | { | |
3546 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
3547 | case MII_TG3_AUX_STAT_10HALF: | |
3548 | *speed = SPEED_10; | |
3549 | *duplex = DUPLEX_HALF; | |
3550 | break; | |
3551 | ||
3552 | case MII_TG3_AUX_STAT_10FULL: | |
3553 | *speed = SPEED_10; | |
3554 | *duplex = DUPLEX_FULL; | |
3555 | break; | |
3556 | ||
3557 | case MII_TG3_AUX_STAT_100HALF: | |
3558 | *speed = SPEED_100; | |
3559 | *duplex = DUPLEX_HALF; | |
3560 | break; | |
3561 | ||
3562 | case MII_TG3_AUX_STAT_100FULL: | |
3563 | *speed = SPEED_100; | |
3564 | *duplex = DUPLEX_FULL; | |
3565 | break; | |
3566 | ||
3567 | case MII_TG3_AUX_STAT_1000HALF: | |
3568 | *speed = SPEED_1000; | |
3569 | *duplex = DUPLEX_HALF; | |
3570 | break; | |
3571 | ||
3572 | case MII_TG3_AUX_STAT_1000FULL: | |
3573 | *speed = SPEED_1000; | |
3574 | *duplex = DUPLEX_FULL; | |
3575 | break; | |
3576 | ||
3577 | default: | |
f07e9af3 | 3578 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
715116a1 MC |
3579 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
3580 | SPEED_10; | |
3581 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
3582 | DUPLEX_HALF; | |
3583 | break; | |
3584 | } | |
1da177e4 LT |
3585 | *speed = SPEED_INVALID; |
3586 | *duplex = DUPLEX_INVALID; | |
3587 | break; | |
855e1111 | 3588 | } |
1da177e4 LT |
3589 | } |
3590 | ||
42b64a45 | 3591 | static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) |
1da177e4 | 3592 | { |
42b64a45 MC |
3593 | int err = 0; |
3594 | u32 val, new_adv; | |
1da177e4 | 3595 | |
42b64a45 | 3596 | new_adv = ADVERTISE_CSMA; |
37f07023 | 3597 | new_adv |= ethtool_adv_to_mii_adv_t(advertise); |
42b64a45 | 3598 | new_adv |= tg3_advert_flowctrl_1000T(flowctrl); |
1da177e4 | 3599 | |
42b64a45 MC |
3600 | err = tg3_writephy(tp, MII_ADVERTISE, new_adv); |
3601 | if (err) | |
3602 | goto done; | |
ba4d07a8 | 3603 | |
42b64a45 MC |
3604 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
3605 | goto done; | |
1da177e4 | 3606 | |
37f07023 | 3607 | new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise); |
ba4d07a8 | 3608 | |
42b64a45 MC |
3609 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || |
3610 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
221c5637 | 3611 | new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; |
ba4d07a8 | 3612 | |
221c5637 | 3613 | err = tg3_writephy(tp, MII_CTRL1000, new_adv); |
42b64a45 MC |
3614 | if (err) |
3615 | goto done; | |
1da177e4 | 3616 | |
42b64a45 MC |
3617 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) |
3618 | goto done; | |
52b02d04 | 3619 | |
42b64a45 MC |
3620 | tw32(TG3_CPMU_EEE_MODE, |
3621 | tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
52b02d04 | 3622 | |
42b64a45 MC |
3623 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
3624 | if (!err) { | |
3625 | u32 err2; | |
52b02d04 | 3626 | |
b715ce94 MC |
3627 | val = 0; |
3628 | /* Advertise 100-BaseTX EEE ability */ | |
3629 | if (advertise & ADVERTISED_100baseT_Full) | |
3630 | val |= MDIO_AN_EEE_ADV_100TX; | |
3631 | /* Advertise 1000-BaseT EEE ability */ | |
3632 | if (advertise & ADVERTISED_1000baseT_Full) | |
3633 | val |= MDIO_AN_EEE_ADV_1000T; | |
3634 | err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
3635 | if (err) | |
3636 | val = 0; | |
3637 | ||
21a00ab2 MC |
3638 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { |
3639 | case ASIC_REV_5717: | |
3640 | case ASIC_REV_57765: | |
21a00ab2 | 3641 | case ASIC_REV_5719: |
b715ce94 MC |
3642 | /* If we advertised any eee advertisements above... */ |
3643 | if (val) | |
3644 | val = MII_TG3_DSP_TAP26_ALNOKO | | |
3645 | MII_TG3_DSP_TAP26_RMRXSTO | | |
3646 | MII_TG3_DSP_TAP26_OPCSINPT; | |
21a00ab2 | 3647 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); |
be671947 MC |
3648 | /* Fall through */ |
3649 | case ASIC_REV_5720: | |
3650 | if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) | |
3651 | tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | | |
3652 | MII_TG3_DSP_CH34TP2_HIBW01); | |
21a00ab2 | 3653 | } |
52b02d04 | 3654 | |
42b64a45 MC |
3655 | err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
3656 | if (!err) | |
3657 | err = err2; | |
3658 | } | |
3659 | ||
3660 | done: | |
3661 | return err; | |
3662 | } | |
3663 | ||
3664 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
3665 | { | |
3666 | u32 new_adv; | |
3667 | int i; | |
3668 | ||
3669 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { | |
3670 | new_adv = ADVERTISED_10baseT_Half | | |
3671 | ADVERTISED_10baseT_Full; | |
3672 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
3673 | new_adv |= ADVERTISED_100baseT_Half | | |
3674 | ADVERTISED_100baseT_Full; | |
3675 | ||
3676 | tg3_phy_autoneg_cfg(tp, new_adv, | |
3677 | FLOW_CTRL_TX | FLOW_CTRL_RX); | |
3678 | } else if (tp->link_config.speed == SPEED_INVALID) { | |
3679 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
3680 | tp->link_config.advertising &= | |
3681 | ~(ADVERTISED_1000baseT_Half | | |
3682 | ADVERTISED_1000baseT_Full); | |
3683 | ||
3684 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, | |
3685 | tp->link_config.flowctrl); | |
3686 | } else { | |
3687 | /* Asking for a specific link mode. */ | |
3688 | if (tp->link_config.speed == SPEED_1000) { | |
3689 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3690 | new_adv = ADVERTISED_1000baseT_Full; | |
3691 | else | |
3692 | new_adv = ADVERTISED_1000baseT_Half; | |
3693 | } else if (tp->link_config.speed == SPEED_100) { | |
3694 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3695 | new_adv = ADVERTISED_100baseT_Full; | |
3696 | else | |
3697 | new_adv = ADVERTISED_100baseT_Half; | |
3698 | } else { | |
3699 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3700 | new_adv = ADVERTISED_10baseT_Full; | |
3701 | else | |
3702 | new_adv = ADVERTISED_10baseT_Half; | |
52b02d04 | 3703 | } |
52b02d04 | 3704 | |
42b64a45 MC |
3705 | tg3_phy_autoneg_cfg(tp, new_adv, |
3706 | tp->link_config.flowctrl); | |
52b02d04 MC |
3707 | } |
3708 | ||
1da177e4 LT |
3709 | if (tp->link_config.autoneg == AUTONEG_DISABLE && |
3710 | tp->link_config.speed != SPEED_INVALID) { | |
3711 | u32 bmcr, orig_bmcr; | |
3712 | ||
3713 | tp->link_config.active_speed = tp->link_config.speed; | |
3714 | tp->link_config.active_duplex = tp->link_config.duplex; | |
3715 | ||
3716 | bmcr = 0; | |
3717 | switch (tp->link_config.speed) { | |
3718 | default: | |
3719 | case SPEED_10: | |
3720 | break; | |
3721 | ||
3722 | case SPEED_100: | |
3723 | bmcr |= BMCR_SPEED100; | |
3724 | break; | |
3725 | ||
3726 | case SPEED_1000: | |
221c5637 | 3727 | bmcr |= BMCR_SPEED1000; |
1da177e4 | 3728 | break; |
855e1111 | 3729 | } |
1da177e4 LT |
3730 | |
3731 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3732 | bmcr |= BMCR_FULLDPLX; | |
3733 | ||
3734 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
3735 | (bmcr != orig_bmcr)) { | |
3736 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
3737 | for (i = 0; i < 1500; i++) { | |
3738 | u32 tmp; | |
3739 | ||
3740 | udelay(10); | |
3741 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
3742 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
3743 | continue; | |
3744 | if (!(tmp & BMSR_LSTATUS)) { | |
3745 | udelay(40); | |
3746 | break; | |
3747 | } | |
3748 | } | |
3749 | tg3_writephy(tp, MII_BMCR, bmcr); | |
3750 | udelay(40); | |
3751 | } | |
3752 | } else { | |
3753 | tg3_writephy(tp, MII_BMCR, | |
3754 | BMCR_ANENABLE | BMCR_ANRESTART); | |
3755 | } | |
3756 | } | |
3757 | ||
3758 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
3759 | { | |
3760 | int err; | |
3761 | ||
3762 | /* Turn off tap power management. */ | |
3763 | /* Set Extended packet length bit */ | |
b4bd2929 | 3764 | err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
1da177e4 | 3765 | |
6ee7c0a0 MC |
3766 | err |= tg3_phydsp_write(tp, 0x0012, 0x1804); |
3767 | err |= tg3_phydsp_write(tp, 0x0013, 0x1204); | |
3768 | err |= tg3_phydsp_write(tp, 0x8006, 0x0132); | |
3769 | err |= tg3_phydsp_write(tp, 0x8006, 0x0232); | |
3770 | err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); | |
1da177e4 LT |
3771 | |
3772 | udelay(40); | |
3773 | ||
3774 | return err; | |
3775 | } | |
3776 | ||
3600d918 | 3777 | static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask) |
1da177e4 | 3778 | { |
3600d918 MC |
3779 | u32 adv_reg, all_mask = 0; |
3780 | ||
37f07023 | 3781 | all_mask = ethtool_adv_to_mii_adv_t(mask); |
1da177e4 LT |
3782 | |
3783 | if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg)) | |
3784 | return 0; | |
3785 | ||
b99d2a57 | 3786 | if ((adv_reg & ADVERTISE_ALL) != all_mask) |
1da177e4 | 3787 | return 0; |
b99d2a57 | 3788 | |
f07e9af3 | 3789 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
1da177e4 LT |
3790 | u32 tg3_ctrl; |
3791 | ||
37f07023 | 3792 | all_mask = ethtool_adv_to_mii_ctrl1000_t(mask); |
3600d918 | 3793 | |
221c5637 | 3794 | if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) |
1da177e4 LT |
3795 | return 0; |
3796 | ||
b99d2a57 MC |
3797 | tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL); |
3798 | if (tg3_ctrl != all_mask) | |
1da177e4 LT |
3799 | return 0; |
3800 | } | |
93a700a9 | 3801 | |
1da177e4 LT |
3802 | return 1; |
3803 | } | |
3804 | ||
ef167e27 MC |
3805 | static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv) |
3806 | { | |
3807 | u32 curadv, reqadv; | |
3808 | ||
3809 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) | |
3810 | return 1; | |
3811 | ||
3812 | curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
3813 | reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
3814 | ||
3815 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
3816 | if (curadv != reqadv) | |
3817 | return 0; | |
3818 | ||
63c3a66f | 3819 | if (tg3_flag(tp, PAUSE_AUTONEG)) |
ef167e27 MC |
3820 | tg3_readphy(tp, MII_LPA, rmtadv); |
3821 | } else { | |
3822 | /* Reprogram the advertisement register, even if it | |
3823 | * does not affect the current link. If the link | |
3824 | * gets renegotiated in the future, we can save an | |
3825 | * additional renegotiation cycle by advertising | |
3826 | * it correctly in the first place. | |
3827 | */ | |
3828 | if (curadv != reqadv) { | |
3829 | *lcladv &= ~(ADVERTISE_PAUSE_CAP | | |
3830 | ADVERTISE_PAUSE_ASYM); | |
3831 | tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv); | |
3832 | } | |
3833 | } | |
3834 | ||
3835 | return 1; | |
3836 | } | |
3837 | ||
1da177e4 LT |
3838 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) |
3839 | { | |
3840 | int current_link_up; | |
f833c4c1 | 3841 | u32 bmsr, val; |
ef167e27 | 3842 | u32 lcl_adv, rmt_adv; |
1da177e4 LT |
3843 | u16 current_speed; |
3844 | u8 current_duplex; | |
3845 | int i, err; | |
3846 | ||
3847 | tw32(MAC_EVENT, 0); | |
3848 | ||
3849 | tw32_f(MAC_STATUS, | |
3850 | (MAC_STATUS_SYNC_CHANGED | | |
3851 | MAC_STATUS_CFG_CHANGED | | |
3852 | MAC_STATUS_MI_COMPLETION | | |
3853 | MAC_STATUS_LNKSTATE_CHANGED)); | |
3854 | udelay(40); | |
3855 | ||
8ef21428 MC |
3856 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
3857 | tw32_f(MAC_MI_MODE, | |
3858 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
3859 | udelay(80); | |
3860 | } | |
1da177e4 | 3861 | |
b4bd2929 | 3862 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); |
1da177e4 LT |
3863 | |
3864 | /* Some third-party PHYs need to be reset on link going | |
3865 | * down. | |
3866 | */ | |
3867 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3868 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
3869 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
3870 | netif_carrier_ok(tp->dev)) { | |
3871 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3872 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3873 | !(bmsr & BMSR_LSTATUS)) | |
3874 | force_reset = 1; | |
3875 | } | |
3876 | if (force_reset) | |
3877 | tg3_phy_reset(tp); | |
3878 | ||
79eb6904 | 3879 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
3880 | tg3_readphy(tp, MII_BMSR, &bmsr); |
3881 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
63c3a66f | 3882 | !tg3_flag(tp, INIT_COMPLETE)) |
1da177e4 LT |
3883 | bmsr = 0; |
3884 | ||
3885 | if (!(bmsr & BMSR_LSTATUS)) { | |
3886 | err = tg3_init_5401phy_dsp(tp); | |
3887 | if (err) | |
3888 | return err; | |
3889 | ||
3890 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3891 | for (i = 0; i < 1000; i++) { | |
3892 | udelay(10); | |
3893 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3894 | (bmsr & BMSR_LSTATUS)) { | |
3895 | udelay(40); | |
3896 | break; | |
3897 | } | |
3898 | } | |
3899 | ||
79eb6904 MC |
3900 | if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == |
3901 | TG3_PHY_REV_BCM5401_B0 && | |
1da177e4 LT |
3902 | !(bmsr & BMSR_LSTATUS) && |
3903 | tp->link_config.active_speed == SPEED_1000) { | |
3904 | err = tg3_phy_reset(tp); | |
3905 | if (!err) | |
3906 | err = tg3_init_5401phy_dsp(tp); | |
3907 | if (err) | |
3908 | return err; | |
3909 | } | |
3910 | } | |
3911 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
3912 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
3913 | /* 5701 {A0,B0} CRC bug workaround */ | |
3914 | tg3_writephy(tp, 0x15, 0x0a75); | |
f08aa1a8 MC |
3915 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); |
3916 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
3917 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); | |
1da177e4 LT |
3918 | } |
3919 | ||
3920 | /* Clear pending interrupts... */ | |
f833c4c1 MC |
3921 | tg3_readphy(tp, MII_TG3_ISTAT, &val); |
3922 | tg3_readphy(tp, MII_TG3_ISTAT, &val); | |
1da177e4 | 3923 | |
f07e9af3 | 3924 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) |
1da177e4 | 3925 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); |
f07e9af3 | 3926 | else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) |
1da177e4 LT |
3927 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
3928 | ||
3929 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3930 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3931 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
3932 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
3933 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
3934 | else | |
3935 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
3936 | } | |
3937 | ||
3938 | current_link_up = 0; | |
3939 | current_speed = SPEED_INVALID; | |
3940 | current_duplex = DUPLEX_INVALID; | |
3941 | ||
f07e9af3 | 3942 | if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { |
15ee95c3 MC |
3943 | err = tg3_phy_auxctl_read(tp, |
3944 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
3945 | &val); | |
3946 | if (!err && !(val & (1 << 10))) { | |
b4bd2929 MC |
3947 | tg3_phy_auxctl_write(tp, |
3948 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
3949 | val | (1 << 10)); | |
1da177e4 LT |
3950 | goto relink; |
3951 | } | |
3952 | } | |
3953 | ||
3954 | bmsr = 0; | |
3955 | for (i = 0; i < 100; i++) { | |
3956 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3957 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3958 | (bmsr & BMSR_LSTATUS)) | |
3959 | break; | |
3960 | udelay(40); | |
3961 | } | |
3962 | ||
3963 | if (bmsr & BMSR_LSTATUS) { | |
3964 | u32 aux_stat, bmcr; | |
3965 | ||
3966 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
3967 | for (i = 0; i < 2000; i++) { | |
3968 | udelay(10); | |
3969 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
3970 | aux_stat) | |
3971 | break; | |
3972 | } | |
3973 | ||
3974 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
3975 | ¤t_speed, | |
3976 | ¤t_duplex); | |
3977 | ||
3978 | bmcr = 0; | |
3979 | for (i = 0; i < 200; i++) { | |
3980 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
3981 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
3982 | continue; | |
3983 | if (bmcr && bmcr != 0x7fff) | |
3984 | break; | |
3985 | udelay(10); | |
3986 | } | |
3987 | ||
ef167e27 MC |
3988 | lcl_adv = 0; |
3989 | rmt_adv = 0; | |
1da177e4 | 3990 | |
ef167e27 MC |
3991 | tp->link_config.active_speed = current_speed; |
3992 | tp->link_config.active_duplex = current_duplex; | |
3993 | ||
3994 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3995 | if ((bmcr & BMCR_ANENABLE) && | |
3996 | tg3_copper_is_advertising_all(tp, | |
3997 | tp->link_config.advertising)) { | |
3998 | if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv, | |
3999 | &rmt_adv)) | |
4000 | current_link_up = 1; | |
1da177e4 LT |
4001 | } |
4002 | } else { | |
4003 | if (!(bmcr & BMCR_ANENABLE) && | |
4004 | tp->link_config.speed == current_speed && | |
ef167e27 MC |
4005 | tp->link_config.duplex == current_duplex && |
4006 | tp->link_config.flowctrl == | |
4007 | tp->link_config.active_flowctrl) { | |
1da177e4 | 4008 | current_link_up = 1; |
1da177e4 LT |
4009 | } |
4010 | } | |
4011 | ||
ef167e27 MC |
4012 | if (current_link_up == 1 && |
4013 | tp->link_config.active_duplex == DUPLEX_FULL) | |
4014 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1da177e4 LT |
4015 | } |
4016 | ||
1da177e4 | 4017 | relink: |
80096068 | 4018 | if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
1da177e4 LT |
4019 | tg3_phy_copper_begin(tp); |
4020 | ||
f833c4c1 | 4021 | tg3_readphy(tp, MII_BMSR, &bmsr); |
06c03c02 MB |
4022 | if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || |
4023 | (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
1da177e4 LT |
4024 | current_link_up = 1; |
4025 | } | |
4026 | ||
4027 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
4028 | if (current_link_up == 1) { | |
4029 | if (tp->link_config.active_speed == SPEED_100 || | |
4030 | tp->link_config.active_speed == SPEED_10) | |
4031 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
4032 | else | |
4033 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
f07e9af3 | 4034 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) |
7f97a4bd MC |
4035 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
4036 | else | |
1da177e4 LT |
4037 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
4038 | ||
4039 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
4040 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4041 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4042 | ||
1da177e4 | 4043 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
e8f3f6ca MC |
4044 | if (current_link_up == 1 && |
4045 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
1da177e4 | 4046 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
e8f3f6ca MC |
4047 | else |
4048 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
4049 | } |
4050 | ||
4051 | /* ??? Without this setting Netgear GA302T PHY does not | |
4052 | * ??? send/receive packets... | |
4053 | */ | |
79eb6904 | 4054 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && |
1da177e4 LT |
4055 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { |
4056 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
4057 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
4058 | udelay(80); | |
4059 | } | |
4060 | ||
4061 | tw32_f(MAC_MODE, tp->mac_mode); | |
4062 | udelay(40); | |
4063 | ||
52b02d04 MC |
4064 | tg3_phy_eee_adjust(tp, current_link_up); |
4065 | ||
63c3a66f | 4066 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
1da177e4 LT |
4067 | /* Polled via timer. */ |
4068 | tw32_f(MAC_EVENT, 0); | |
4069 | } else { | |
4070 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4071 | } | |
4072 | udelay(40); | |
4073 | ||
4074 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
4075 | current_link_up == 1 && | |
4076 | tp->link_config.active_speed == SPEED_1000 && | |
63c3a66f | 4077 | (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { |
1da177e4 LT |
4078 | udelay(120); |
4079 | tw32_f(MAC_STATUS, | |
4080 | (MAC_STATUS_SYNC_CHANGED | | |
4081 | MAC_STATUS_CFG_CHANGED)); | |
4082 | udelay(40); | |
4083 | tg3_write_mem(tp, | |
4084 | NIC_SRAM_FIRMWARE_MBOX, | |
4085 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
4086 | } | |
4087 | ||
5e7dfd0f | 4088 | /* Prevent send BD corruption. */ |
63c3a66f | 4089 | if (tg3_flag(tp, CLKREQ_BUG)) { |
5e7dfd0f MC |
4090 | u16 oldlnkctl, newlnkctl; |
4091 | ||
4092 | pci_read_config_word(tp->pdev, | |
708ebb3a | 4093 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
4094 | &oldlnkctl); |
4095 | if (tp->link_config.active_speed == SPEED_100 || | |
4096 | tp->link_config.active_speed == SPEED_10) | |
4097 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
4098 | else | |
4099 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; | |
4100 | if (newlnkctl != oldlnkctl) | |
4101 | pci_write_config_word(tp->pdev, | |
93a700a9 MC |
4102 | pci_pcie_cap(tp->pdev) + |
4103 | PCI_EXP_LNKCTL, newlnkctl); | |
5e7dfd0f MC |
4104 | } |
4105 | ||
1da177e4 LT |
4106 | if (current_link_up != netif_carrier_ok(tp->dev)) { |
4107 | if (current_link_up) | |
4108 | netif_carrier_on(tp->dev); | |
4109 | else | |
4110 | netif_carrier_off(tp->dev); | |
4111 | tg3_link_report(tp); | |
4112 | } | |
4113 | ||
4114 | return 0; | |
4115 | } | |
4116 | ||
4117 | struct tg3_fiber_aneginfo { | |
4118 | int state; | |
4119 | #define ANEG_STATE_UNKNOWN 0 | |
4120 | #define ANEG_STATE_AN_ENABLE 1 | |
4121 | #define ANEG_STATE_RESTART_INIT 2 | |
4122 | #define ANEG_STATE_RESTART 3 | |
4123 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
4124 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
4125 | #define ANEG_STATE_ABILITY_DETECT 6 | |
4126 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
4127 | #define ANEG_STATE_ACK_DETECT 8 | |
4128 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
4129 | #define ANEG_STATE_COMPLETE_ACK 10 | |
4130 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
4131 | #define ANEG_STATE_IDLE_DETECT 12 | |
4132 | #define ANEG_STATE_LINK_OK 13 | |
4133 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
4134 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
4135 | ||
4136 | u32 flags; | |
4137 | #define MR_AN_ENABLE 0x00000001 | |
4138 | #define MR_RESTART_AN 0x00000002 | |
4139 | #define MR_AN_COMPLETE 0x00000004 | |
4140 | #define MR_PAGE_RX 0x00000008 | |
4141 | #define MR_NP_LOADED 0x00000010 | |
4142 | #define MR_TOGGLE_TX 0x00000020 | |
4143 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
4144 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
4145 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
4146 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
4147 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
4148 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
4149 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
4150 | #define MR_TOGGLE_RX 0x00002000 | |
4151 | #define MR_NP_RX 0x00004000 | |
4152 | ||
4153 | #define MR_LINK_OK 0x80000000 | |
4154 | ||
4155 | unsigned long link_time, cur_time; | |
4156 | ||
4157 | u32 ability_match_cfg; | |
4158 | int ability_match_count; | |
4159 | ||
4160 | char ability_match, idle_match, ack_match; | |
4161 | ||
4162 | u32 txconfig, rxconfig; | |
4163 | #define ANEG_CFG_NP 0x00000080 | |
4164 | #define ANEG_CFG_ACK 0x00000040 | |
4165 | #define ANEG_CFG_RF2 0x00000020 | |
4166 | #define ANEG_CFG_RF1 0x00000010 | |
4167 | #define ANEG_CFG_PS2 0x00000001 | |
4168 | #define ANEG_CFG_PS1 0x00008000 | |
4169 | #define ANEG_CFG_HD 0x00004000 | |
4170 | #define ANEG_CFG_FD 0x00002000 | |
4171 | #define ANEG_CFG_INVAL 0x00001f06 | |
4172 | ||
4173 | }; | |
4174 | #define ANEG_OK 0 | |
4175 | #define ANEG_DONE 1 | |
4176 | #define ANEG_TIMER_ENAB 2 | |
4177 | #define ANEG_FAILED -1 | |
4178 | ||
4179 | #define ANEG_STATE_SETTLE_TIME 10000 | |
4180 | ||
4181 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
4182 | struct tg3_fiber_aneginfo *ap) | |
4183 | { | |
5be73b47 | 4184 | u16 flowctrl; |
1da177e4 LT |
4185 | unsigned long delta; |
4186 | u32 rx_cfg_reg; | |
4187 | int ret; | |
4188 | ||
4189 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
4190 | ap->rxconfig = 0; | |
4191 | ap->link_time = 0; | |
4192 | ap->cur_time = 0; | |
4193 | ap->ability_match_cfg = 0; | |
4194 | ap->ability_match_count = 0; | |
4195 | ap->ability_match = 0; | |
4196 | ap->idle_match = 0; | |
4197 | ap->ack_match = 0; | |
4198 | } | |
4199 | ap->cur_time++; | |
4200 | ||
4201 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
4202 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
4203 | ||
4204 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
4205 | ap->ability_match_cfg = rx_cfg_reg; | |
4206 | ap->ability_match = 0; | |
4207 | ap->ability_match_count = 0; | |
4208 | } else { | |
4209 | if (++ap->ability_match_count > 1) { | |
4210 | ap->ability_match = 1; | |
4211 | ap->ability_match_cfg = rx_cfg_reg; | |
4212 | } | |
4213 | } | |
4214 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
4215 | ap->ack_match = 1; | |
4216 | else | |
4217 | ap->ack_match = 0; | |
4218 | ||
4219 | ap->idle_match = 0; | |
4220 | } else { | |
4221 | ap->idle_match = 1; | |
4222 | ap->ability_match_cfg = 0; | |
4223 | ap->ability_match_count = 0; | |
4224 | ap->ability_match = 0; | |
4225 | ap->ack_match = 0; | |
4226 | ||
4227 | rx_cfg_reg = 0; | |
4228 | } | |
4229 | ||
4230 | ap->rxconfig = rx_cfg_reg; | |
4231 | ret = ANEG_OK; | |
4232 | ||
33f401ae | 4233 | switch (ap->state) { |
1da177e4 LT |
4234 | case ANEG_STATE_UNKNOWN: |
4235 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
4236 | ap->state = ANEG_STATE_AN_ENABLE; | |
4237 | ||
4238 | /* fallthru */ | |
4239 | case ANEG_STATE_AN_ENABLE: | |
4240 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
4241 | if (ap->flags & MR_AN_ENABLE) { | |
4242 | ap->link_time = 0; | |
4243 | ap->cur_time = 0; | |
4244 | ap->ability_match_cfg = 0; | |
4245 | ap->ability_match_count = 0; | |
4246 | ap->ability_match = 0; | |
4247 | ap->idle_match = 0; | |
4248 | ap->ack_match = 0; | |
4249 | ||
4250 | ap->state = ANEG_STATE_RESTART_INIT; | |
4251 | } else { | |
4252 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
4253 | } | |
4254 | break; | |
4255 | ||
4256 | case ANEG_STATE_RESTART_INIT: | |
4257 | ap->link_time = ap->cur_time; | |
4258 | ap->flags &= ~(MR_NP_LOADED); | |
4259 | ap->txconfig = 0; | |
4260 | tw32(MAC_TX_AUTO_NEG, 0); | |
4261 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
4262 | tw32_f(MAC_MODE, tp->mac_mode); | |
4263 | udelay(40); | |
4264 | ||
4265 | ret = ANEG_TIMER_ENAB; | |
4266 | ap->state = ANEG_STATE_RESTART; | |
4267 | ||
4268 | /* fallthru */ | |
4269 | case ANEG_STATE_RESTART: | |
4270 | delta = ap->cur_time - ap->link_time; | |
859a5887 | 4271 | if (delta > ANEG_STATE_SETTLE_TIME) |
1da177e4 | 4272 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; |
859a5887 | 4273 | else |
1da177e4 | 4274 | ret = ANEG_TIMER_ENAB; |
1da177e4 LT |
4275 | break; |
4276 | ||
4277 | case ANEG_STATE_DISABLE_LINK_OK: | |
4278 | ret = ANEG_DONE; | |
4279 | break; | |
4280 | ||
4281 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
4282 | ap->flags &= ~(MR_TOGGLE_TX); | |
5be73b47 MC |
4283 | ap->txconfig = ANEG_CFG_FD; |
4284 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
4285 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
4286 | ap->txconfig |= ANEG_CFG_PS1; | |
4287 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
4288 | ap->txconfig |= ANEG_CFG_PS2; | |
1da177e4 LT |
4289 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
4290 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
4291 | tw32_f(MAC_MODE, tp->mac_mode); | |
4292 | udelay(40); | |
4293 | ||
4294 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
4295 | break; | |
4296 | ||
4297 | case ANEG_STATE_ABILITY_DETECT: | |
859a5887 | 4298 | if (ap->ability_match != 0 && ap->rxconfig != 0) |
1da177e4 | 4299 | ap->state = ANEG_STATE_ACK_DETECT_INIT; |
1da177e4 LT |
4300 | break; |
4301 | ||
4302 | case ANEG_STATE_ACK_DETECT_INIT: | |
4303 | ap->txconfig |= ANEG_CFG_ACK; | |
4304 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
4305 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
4306 | tw32_f(MAC_MODE, tp->mac_mode); | |
4307 | udelay(40); | |
4308 | ||
4309 | ap->state = ANEG_STATE_ACK_DETECT; | |
4310 | ||
4311 | /* fallthru */ | |
4312 | case ANEG_STATE_ACK_DETECT: | |
4313 | if (ap->ack_match != 0) { | |
4314 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
4315 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
4316 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
4317 | } else { | |
4318 | ap->state = ANEG_STATE_AN_ENABLE; | |
4319 | } | |
4320 | } else if (ap->ability_match != 0 && | |
4321 | ap->rxconfig == 0) { | |
4322 | ap->state = ANEG_STATE_AN_ENABLE; | |
4323 | } | |
4324 | break; | |
4325 | ||
4326 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
4327 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
4328 | ret = ANEG_FAILED; | |
4329 | break; | |
4330 | } | |
4331 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
4332 | MR_LP_ADV_HALF_DUPLEX | | |
4333 | MR_LP_ADV_SYM_PAUSE | | |
4334 | MR_LP_ADV_ASYM_PAUSE | | |
4335 | MR_LP_ADV_REMOTE_FAULT1 | | |
4336 | MR_LP_ADV_REMOTE_FAULT2 | | |
4337 | MR_LP_ADV_NEXT_PAGE | | |
4338 | MR_TOGGLE_RX | | |
4339 | MR_NP_RX); | |
4340 | if (ap->rxconfig & ANEG_CFG_FD) | |
4341 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
4342 | if (ap->rxconfig & ANEG_CFG_HD) | |
4343 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
4344 | if (ap->rxconfig & ANEG_CFG_PS1) | |
4345 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
4346 | if (ap->rxconfig & ANEG_CFG_PS2) | |
4347 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
4348 | if (ap->rxconfig & ANEG_CFG_RF1) | |
4349 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
4350 | if (ap->rxconfig & ANEG_CFG_RF2) | |
4351 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
4352 | if (ap->rxconfig & ANEG_CFG_NP) | |
4353 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
4354 | ||
4355 | ap->link_time = ap->cur_time; | |
4356 | ||
4357 | ap->flags ^= (MR_TOGGLE_TX); | |
4358 | if (ap->rxconfig & 0x0008) | |
4359 | ap->flags |= MR_TOGGLE_RX; | |
4360 | if (ap->rxconfig & ANEG_CFG_NP) | |
4361 | ap->flags |= MR_NP_RX; | |
4362 | ap->flags |= MR_PAGE_RX; | |
4363 | ||
4364 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
4365 | ret = ANEG_TIMER_ENAB; | |
4366 | break; | |
4367 | ||
4368 | case ANEG_STATE_COMPLETE_ACK: | |
4369 | if (ap->ability_match != 0 && | |
4370 | ap->rxconfig == 0) { | |
4371 | ap->state = ANEG_STATE_AN_ENABLE; | |
4372 | break; | |
4373 | } | |
4374 | delta = ap->cur_time - ap->link_time; | |
4375 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
4376 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
4377 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
4378 | } else { | |
4379 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
4380 | !(ap->flags & MR_NP_RX)) { | |
4381 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
4382 | } else { | |
4383 | ret = ANEG_FAILED; | |
4384 | } | |
4385 | } | |
4386 | } | |
4387 | break; | |
4388 | ||
4389 | case ANEG_STATE_IDLE_DETECT_INIT: | |
4390 | ap->link_time = ap->cur_time; | |
4391 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
4392 | tw32_f(MAC_MODE, tp->mac_mode); | |
4393 | udelay(40); | |
4394 | ||
4395 | ap->state = ANEG_STATE_IDLE_DETECT; | |
4396 | ret = ANEG_TIMER_ENAB; | |
4397 | break; | |
4398 | ||
4399 | case ANEG_STATE_IDLE_DETECT: | |
4400 | if (ap->ability_match != 0 && | |
4401 | ap->rxconfig == 0) { | |
4402 | ap->state = ANEG_STATE_AN_ENABLE; | |
4403 | break; | |
4404 | } | |
4405 | delta = ap->cur_time - ap->link_time; | |
4406 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
4407 | /* XXX another gem from the Broadcom driver :( */ | |
4408 | ap->state = ANEG_STATE_LINK_OK; | |
4409 | } | |
4410 | break; | |
4411 | ||
4412 | case ANEG_STATE_LINK_OK: | |
4413 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
4414 | ret = ANEG_DONE; | |
4415 | break; | |
4416 | ||
4417 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
4418 | /* ??? unimplemented */ | |
4419 | break; | |
4420 | ||
4421 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
4422 | /* ??? unimplemented */ | |
4423 | break; | |
4424 | ||
4425 | default: | |
4426 | ret = ANEG_FAILED; | |
4427 | break; | |
855e1111 | 4428 | } |
1da177e4 LT |
4429 | |
4430 | return ret; | |
4431 | } | |
4432 | ||
5be73b47 | 4433 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) |
1da177e4 LT |
4434 | { |
4435 | int res = 0; | |
4436 | struct tg3_fiber_aneginfo aninfo; | |
4437 | int status = ANEG_FAILED; | |
4438 | unsigned int tick; | |
4439 | u32 tmp; | |
4440 | ||
4441 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
4442 | ||
4443 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
4444 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
4445 | udelay(40); | |
4446 | ||
4447 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
4448 | udelay(40); | |
4449 | ||
4450 | memset(&aninfo, 0, sizeof(aninfo)); | |
4451 | aninfo.flags |= MR_AN_ENABLE; | |
4452 | aninfo.state = ANEG_STATE_UNKNOWN; | |
4453 | aninfo.cur_time = 0; | |
4454 | tick = 0; | |
4455 | while (++tick < 195000) { | |
4456 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
4457 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
4458 | break; | |
4459 | ||
4460 | udelay(1); | |
4461 | } | |
4462 | ||
4463 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
4464 | tw32_f(MAC_MODE, tp->mac_mode); | |
4465 | udelay(40); | |
4466 | ||
5be73b47 MC |
4467 | *txflags = aninfo.txconfig; |
4468 | *rxflags = aninfo.flags; | |
1da177e4 LT |
4469 | |
4470 | if (status == ANEG_DONE && | |
4471 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
4472 | MR_LP_ADV_FULL_DUPLEX))) | |
4473 | res = 1; | |
4474 | ||
4475 | return res; | |
4476 | } | |
4477 | ||
4478 | static void tg3_init_bcm8002(struct tg3 *tp) | |
4479 | { | |
4480 | u32 mac_status = tr32(MAC_STATUS); | |
4481 | int i; | |
4482 | ||
4483 | /* Reset when initting first time or we have a link. */ | |
63c3a66f | 4484 | if (tg3_flag(tp, INIT_COMPLETE) && |
1da177e4 LT |
4485 | !(mac_status & MAC_STATUS_PCS_SYNCED)) |
4486 | return; | |
4487 | ||
4488 | /* Set PLL lock range. */ | |
4489 | tg3_writephy(tp, 0x16, 0x8007); | |
4490 | ||
4491 | /* SW reset */ | |
4492 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
4493 | ||
4494 | /* Wait for reset to complete. */ | |
4495 | /* XXX schedule_timeout() ... */ | |
4496 | for (i = 0; i < 500; i++) | |
4497 | udelay(10); | |
4498 | ||
4499 | /* Config mode; select PMA/Ch 1 regs. */ | |
4500 | tg3_writephy(tp, 0x10, 0x8411); | |
4501 | ||
4502 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
4503 | tg3_writephy(tp, 0x11, 0x0a10); | |
4504 | ||
4505 | tg3_writephy(tp, 0x18, 0x00a0); | |
4506 | tg3_writephy(tp, 0x16, 0x41ff); | |
4507 | ||
4508 | /* Assert and deassert POR. */ | |
4509 | tg3_writephy(tp, 0x13, 0x0400); | |
4510 | udelay(40); | |
4511 | tg3_writephy(tp, 0x13, 0x0000); | |
4512 | ||
4513 | tg3_writephy(tp, 0x11, 0x0a50); | |
4514 | udelay(40); | |
4515 | tg3_writephy(tp, 0x11, 0x0a10); | |
4516 | ||
4517 | /* Wait for signal to stabilize */ | |
4518 | /* XXX schedule_timeout() ... */ | |
4519 | for (i = 0; i < 15000; i++) | |
4520 | udelay(10); | |
4521 | ||
4522 | /* Deselect the channel register so we can read the PHYID | |
4523 | * later. | |
4524 | */ | |
4525 | tg3_writephy(tp, 0x10, 0x8011); | |
4526 | } | |
4527 | ||
4528 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
4529 | { | |
82cd3d11 | 4530 | u16 flowctrl; |
1da177e4 LT |
4531 | u32 sg_dig_ctrl, sg_dig_status; |
4532 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
4533 | int workaround, port_a; | |
4534 | int current_link_up; | |
4535 | ||
4536 | serdes_cfg = 0; | |
4537 | expected_sg_dig_ctrl = 0; | |
4538 | workaround = 0; | |
4539 | port_a = 1; | |
4540 | current_link_up = 0; | |
4541 | ||
4542 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
4543 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
4544 | workaround = 1; | |
4545 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
4546 | port_a = 0; | |
4547 | ||
4548 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
4549 | /* preserve bits 20-23 for voltage regulator */ | |
4550 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
4551 | } | |
4552 | ||
4553 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
4554 | ||
4555 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
c98f6e3b | 4556 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { |
1da177e4 LT |
4557 | if (workaround) { |
4558 | u32 val = serdes_cfg; | |
4559 | ||
4560 | if (port_a) | |
4561 | val |= 0xc010000; | |
4562 | else | |
4563 | val |= 0x4010000; | |
4564 | tw32_f(MAC_SERDES_CFG, val); | |
4565 | } | |
c98f6e3b MC |
4566 | |
4567 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
1da177e4 LT |
4568 | } |
4569 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
4570 | tg3_setup_flow_control(tp, 0, 0); | |
4571 | current_link_up = 1; | |
4572 | } | |
4573 | goto out; | |
4574 | } | |
4575 | ||
4576 | /* Want auto-negotiation. */ | |
c98f6e3b | 4577 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; |
1da177e4 | 4578 | |
82cd3d11 MC |
4579 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
4580 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
4581 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
4582 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
4583 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
1da177e4 LT |
4584 | |
4585 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
f07e9af3 | 4586 | if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && |
3d3ebe74 MC |
4587 | tp->serdes_counter && |
4588 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
4589 | MAC_STATUS_RCVD_CFG)) == | |
4590 | MAC_STATUS_PCS_SYNCED)) { | |
4591 | tp->serdes_counter--; | |
4592 | current_link_up = 1; | |
4593 | goto out; | |
4594 | } | |
4595 | restart_autoneg: | |
1da177e4 LT |
4596 | if (workaround) |
4597 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
c98f6e3b | 4598 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); |
1da177e4 LT |
4599 | udelay(5); |
4600 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
4601 | ||
3d3ebe74 | 4602 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
f07e9af3 | 4603 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
4604 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | |
4605 | MAC_STATUS_SIGNAL_DET)) { | |
3d3ebe74 | 4606 | sg_dig_status = tr32(SG_DIG_STATUS); |
1da177e4 LT |
4607 | mac_status = tr32(MAC_STATUS); |
4608 | ||
c98f6e3b | 4609 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && |
1da177e4 | 4610 | (mac_status & MAC_STATUS_PCS_SYNCED)) { |
82cd3d11 MC |
4611 | u32 local_adv = 0, remote_adv = 0; |
4612 | ||
4613 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
4614 | local_adv |= ADVERTISE_1000XPAUSE; | |
4615 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
4616 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
1da177e4 | 4617 | |
c98f6e3b | 4618 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) |
82cd3d11 | 4619 | remote_adv |= LPA_1000XPAUSE; |
c98f6e3b | 4620 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) |
82cd3d11 | 4621 | remote_adv |= LPA_1000XPAUSE_ASYM; |
1da177e4 LT |
4622 | |
4623 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4624 | current_link_up = 1; | |
3d3ebe74 | 4625 | tp->serdes_counter = 0; |
f07e9af3 | 4626 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
c98f6e3b | 4627 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
3d3ebe74 MC |
4628 | if (tp->serdes_counter) |
4629 | tp->serdes_counter--; | |
1da177e4 LT |
4630 | else { |
4631 | if (workaround) { | |
4632 | u32 val = serdes_cfg; | |
4633 | ||
4634 | if (port_a) | |
4635 | val |= 0xc010000; | |
4636 | else | |
4637 | val |= 0x4010000; | |
4638 | ||
4639 | tw32_f(MAC_SERDES_CFG, val); | |
4640 | } | |
4641 | ||
c98f6e3b | 4642 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
1da177e4 LT |
4643 | udelay(40); |
4644 | ||
4645 | /* Link parallel detection - link is up */ | |
4646 | /* only if we have PCS_SYNC and not */ | |
4647 | /* receiving config code words */ | |
4648 | mac_status = tr32(MAC_STATUS); | |
4649 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
4650 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
4651 | tg3_setup_flow_control(tp, 0, 0); | |
4652 | current_link_up = 1; | |
f07e9af3 MC |
4653 | tp->phy_flags |= |
4654 | TG3_PHYFLG_PARALLEL_DETECT; | |
3d3ebe74 MC |
4655 | tp->serdes_counter = |
4656 | SERDES_PARALLEL_DET_TIMEOUT; | |
4657 | } else | |
4658 | goto restart_autoneg; | |
1da177e4 LT |
4659 | } |
4660 | } | |
3d3ebe74 MC |
4661 | } else { |
4662 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
f07e9af3 | 4663 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
4664 | } |
4665 | ||
4666 | out: | |
4667 | return current_link_up; | |
4668 | } | |
4669 | ||
4670 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
4671 | { | |
4672 | int current_link_up = 0; | |
4673 | ||
5cf64b8a | 4674 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
1da177e4 | 4675 | goto out; |
1da177e4 LT |
4676 | |
4677 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
5be73b47 | 4678 | u32 txflags, rxflags; |
1da177e4 | 4679 | int i; |
6aa20a22 | 4680 | |
5be73b47 MC |
4681 | if (fiber_autoneg(tp, &txflags, &rxflags)) { |
4682 | u32 local_adv = 0, remote_adv = 0; | |
1da177e4 | 4683 | |
5be73b47 MC |
4684 | if (txflags & ANEG_CFG_PS1) |
4685 | local_adv |= ADVERTISE_1000XPAUSE; | |
4686 | if (txflags & ANEG_CFG_PS2) | |
4687 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
4688 | ||
4689 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
4690 | remote_adv |= LPA_1000XPAUSE; | |
4691 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
4692 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
1da177e4 LT |
4693 | |
4694 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4695 | ||
1da177e4 LT |
4696 | current_link_up = 1; |
4697 | } | |
4698 | for (i = 0; i < 30; i++) { | |
4699 | udelay(20); | |
4700 | tw32_f(MAC_STATUS, | |
4701 | (MAC_STATUS_SYNC_CHANGED | | |
4702 | MAC_STATUS_CFG_CHANGED)); | |
4703 | udelay(40); | |
4704 | if ((tr32(MAC_STATUS) & | |
4705 | (MAC_STATUS_SYNC_CHANGED | | |
4706 | MAC_STATUS_CFG_CHANGED)) == 0) | |
4707 | break; | |
4708 | } | |
4709 | ||
4710 | mac_status = tr32(MAC_STATUS); | |
4711 | if (current_link_up == 0 && | |
4712 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
4713 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
4714 | current_link_up = 1; | |
4715 | } else { | |
5be73b47 MC |
4716 | tg3_setup_flow_control(tp, 0, 0); |
4717 | ||
1da177e4 LT |
4718 | /* Forcing 1000FD link up. */ |
4719 | current_link_up = 1; | |
1da177e4 LT |
4720 | |
4721 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
4722 | udelay(40); | |
e8f3f6ca MC |
4723 | |
4724 | tw32_f(MAC_MODE, tp->mac_mode); | |
4725 | udelay(40); | |
1da177e4 LT |
4726 | } |
4727 | ||
4728 | out: | |
4729 | return current_link_up; | |
4730 | } | |
4731 | ||
4732 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
4733 | { | |
4734 | u32 orig_pause_cfg; | |
4735 | u16 orig_active_speed; | |
4736 | u8 orig_active_duplex; | |
4737 | u32 mac_status; | |
4738 | int current_link_up; | |
4739 | int i; | |
4740 | ||
8d018621 | 4741 | orig_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4742 | orig_active_speed = tp->link_config.active_speed; |
4743 | orig_active_duplex = tp->link_config.active_duplex; | |
4744 | ||
63c3a66f | 4745 | if (!tg3_flag(tp, HW_AUTONEG) && |
1da177e4 | 4746 | netif_carrier_ok(tp->dev) && |
63c3a66f | 4747 | tg3_flag(tp, INIT_COMPLETE)) { |
1da177e4 LT |
4748 | mac_status = tr32(MAC_STATUS); |
4749 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
4750 | MAC_STATUS_SIGNAL_DET | | |
4751 | MAC_STATUS_CFG_CHANGED | | |
4752 | MAC_STATUS_RCVD_CFG); | |
4753 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
4754 | MAC_STATUS_SIGNAL_DET)) { | |
4755 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4756 | MAC_STATUS_CFG_CHANGED)); | |
4757 | return 0; | |
4758 | } | |
4759 | } | |
4760 | ||
4761 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
4762 | ||
4763 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
4764 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
4765 | tw32_f(MAC_MODE, tp->mac_mode); | |
4766 | udelay(40); | |
4767 | ||
79eb6904 | 4768 | if (tp->phy_id == TG3_PHY_ID_BCM8002) |
1da177e4 LT |
4769 | tg3_init_bcm8002(tp); |
4770 | ||
4771 | /* Enable link change event even when serdes polling. */ | |
4772 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4773 | udelay(40); | |
4774 | ||
4775 | current_link_up = 0; | |
4776 | mac_status = tr32(MAC_STATUS); | |
4777 | ||
63c3a66f | 4778 | if (tg3_flag(tp, HW_AUTONEG)) |
1da177e4 LT |
4779 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); |
4780 | else | |
4781 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
4782 | ||
898a56f8 | 4783 | tp->napi[0].hw_status->status = |
1da177e4 | 4784 | (SD_STATUS_UPDATED | |
898a56f8 | 4785 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); |
1da177e4 LT |
4786 | |
4787 | for (i = 0; i < 100; i++) { | |
4788 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4789 | MAC_STATUS_CFG_CHANGED)); | |
4790 | udelay(5); | |
4791 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3d3ebe74 MC |
4792 | MAC_STATUS_CFG_CHANGED | |
4793 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
1da177e4 LT |
4794 | break; |
4795 | } | |
4796 | ||
4797 | mac_status = tr32(MAC_STATUS); | |
4798 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
4799 | current_link_up = 0; | |
3d3ebe74 MC |
4800 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
4801 | tp->serdes_counter == 0) { | |
1da177e4 LT |
4802 | tw32_f(MAC_MODE, (tp->mac_mode | |
4803 | MAC_MODE_SEND_CONFIGS)); | |
4804 | udelay(1); | |
4805 | tw32_f(MAC_MODE, tp->mac_mode); | |
4806 | } | |
4807 | } | |
4808 | ||
4809 | if (current_link_up == 1) { | |
4810 | tp->link_config.active_speed = SPEED_1000; | |
4811 | tp->link_config.active_duplex = DUPLEX_FULL; | |
4812 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4813 | LED_CTRL_LNKLED_OVERRIDE | | |
4814 | LED_CTRL_1000MBPS_ON)); | |
4815 | } else { | |
4816 | tp->link_config.active_speed = SPEED_INVALID; | |
4817 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
4818 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4819 | LED_CTRL_LNKLED_OVERRIDE | | |
4820 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
4821 | } | |
4822 | ||
4823 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4824 | if (current_link_up) | |
4825 | netif_carrier_on(tp->dev); | |
4826 | else | |
4827 | netif_carrier_off(tp->dev); | |
4828 | tg3_link_report(tp); | |
4829 | } else { | |
8d018621 | 4830 | u32 now_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4831 | if (orig_pause_cfg != now_pause_cfg || |
4832 | orig_active_speed != tp->link_config.active_speed || | |
4833 | orig_active_duplex != tp->link_config.active_duplex) | |
4834 | tg3_link_report(tp); | |
4835 | } | |
4836 | ||
4837 | return 0; | |
4838 | } | |
4839 | ||
747e8f8b MC |
4840 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) |
4841 | { | |
4842 | int current_link_up, err = 0; | |
4843 | u32 bmsr, bmcr; | |
4844 | u16 current_speed; | |
4845 | u8 current_duplex; | |
ef167e27 | 4846 | u32 local_adv, remote_adv; |
747e8f8b MC |
4847 | |
4848 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
4849 | tw32_f(MAC_MODE, tp->mac_mode); | |
4850 | udelay(40); | |
4851 | ||
4852 | tw32(MAC_EVENT, 0); | |
4853 | ||
4854 | tw32_f(MAC_STATUS, | |
4855 | (MAC_STATUS_SYNC_CHANGED | | |
4856 | MAC_STATUS_CFG_CHANGED | | |
4857 | MAC_STATUS_MI_COMPLETION | | |
4858 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4859 | udelay(40); | |
4860 | ||
4861 | if (force_reset) | |
4862 | tg3_phy_reset(tp); | |
4863 | ||
4864 | current_link_up = 0; | |
4865 | current_speed = SPEED_INVALID; | |
4866 | current_duplex = DUPLEX_INVALID; | |
4867 | ||
4868 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4869 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4870 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
4871 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4872 | bmsr |= BMSR_LSTATUS; | |
4873 | else | |
4874 | bmsr &= ~BMSR_LSTATUS; | |
4875 | } | |
747e8f8b MC |
4876 | |
4877 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
4878 | ||
4879 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
f07e9af3 | 4880 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
4881 | /* do nothing, just check for link up at the end */ |
4882 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
28011cf1 | 4883 | u32 adv, newadv; |
747e8f8b MC |
4884 | |
4885 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
28011cf1 MC |
4886 | newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | |
4887 | ADVERTISE_1000XPAUSE | | |
4888 | ADVERTISE_1000XPSE_ASYM | | |
4889 | ADVERTISE_SLCT); | |
747e8f8b | 4890 | |
28011cf1 | 4891 | newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
37f07023 | 4892 | newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); |
747e8f8b | 4893 | |
28011cf1 MC |
4894 | if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) { |
4895 | tg3_writephy(tp, MII_ADVERTISE, newadv); | |
747e8f8b MC |
4896 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; |
4897 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4898 | ||
4899 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3d3ebe74 | 4900 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; |
f07e9af3 | 4901 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4902 | |
4903 | return err; | |
4904 | } | |
4905 | } else { | |
4906 | u32 new_bmcr; | |
4907 | ||
4908 | bmcr &= ~BMCR_SPEED1000; | |
4909 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
4910 | ||
4911 | if (tp->link_config.duplex == DUPLEX_FULL) | |
4912 | new_bmcr |= BMCR_FULLDPLX; | |
4913 | ||
4914 | if (new_bmcr != bmcr) { | |
4915 | /* BMCR_SPEED1000 is a reserved bit that needs | |
4916 | * to be set on write. | |
4917 | */ | |
4918 | new_bmcr |= BMCR_SPEED1000; | |
4919 | ||
4920 | /* Force a linkdown */ | |
4921 | if (netif_carrier_ok(tp->dev)) { | |
4922 | u32 adv; | |
4923 | ||
4924 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4925 | adv &= ~(ADVERTISE_1000XFULL | | |
4926 | ADVERTISE_1000XHALF | | |
4927 | ADVERTISE_SLCT); | |
4928 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
4929 | tg3_writephy(tp, MII_BMCR, bmcr | | |
4930 | BMCR_ANRESTART | | |
4931 | BMCR_ANENABLE); | |
4932 | udelay(10); | |
4933 | netif_carrier_off(tp->dev); | |
4934 | } | |
4935 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
4936 | bmcr = new_bmcr; | |
4937 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4938 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4939 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
4940 | ASIC_REV_5714) { | |
4941 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4942 | bmsr |= BMSR_LSTATUS; | |
4943 | else | |
4944 | bmsr &= ~BMSR_LSTATUS; | |
4945 | } | |
f07e9af3 | 4946 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4947 | } |
4948 | } | |
4949 | ||
4950 | if (bmsr & BMSR_LSTATUS) { | |
4951 | current_speed = SPEED_1000; | |
4952 | current_link_up = 1; | |
4953 | if (bmcr & BMCR_FULLDPLX) | |
4954 | current_duplex = DUPLEX_FULL; | |
4955 | else | |
4956 | current_duplex = DUPLEX_HALF; | |
4957 | ||
ef167e27 MC |
4958 | local_adv = 0; |
4959 | remote_adv = 0; | |
4960 | ||
747e8f8b | 4961 | if (bmcr & BMCR_ANENABLE) { |
ef167e27 | 4962 | u32 common; |
747e8f8b MC |
4963 | |
4964 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
4965 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
4966 | common = local_adv & remote_adv; | |
4967 | if (common & (ADVERTISE_1000XHALF | | |
4968 | ADVERTISE_1000XFULL)) { | |
4969 | if (common & ADVERTISE_1000XFULL) | |
4970 | current_duplex = DUPLEX_FULL; | |
4971 | else | |
4972 | current_duplex = DUPLEX_HALF; | |
63c3a66f | 4973 | } else if (!tg3_flag(tp, 5780_CLASS)) { |
57d8b880 | 4974 | /* Link is up via parallel detect */ |
859a5887 | 4975 | } else { |
747e8f8b | 4976 | current_link_up = 0; |
859a5887 | 4977 | } |
747e8f8b MC |
4978 | } |
4979 | } | |
4980 | ||
ef167e27 MC |
4981 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) |
4982 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4983 | ||
747e8f8b MC |
4984 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
4985 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4986 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4987 | ||
4988 | tw32_f(MAC_MODE, tp->mac_mode); | |
4989 | udelay(40); | |
4990 | ||
4991 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4992 | ||
4993 | tp->link_config.active_speed = current_speed; | |
4994 | tp->link_config.active_duplex = current_duplex; | |
4995 | ||
4996 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4997 | if (current_link_up) | |
4998 | netif_carrier_on(tp->dev); | |
4999 | else { | |
5000 | netif_carrier_off(tp->dev); | |
f07e9af3 | 5001 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5002 | } |
5003 | tg3_link_report(tp); | |
5004 | } | |
5005 | return err; | |
5006 | } | |
5007 | ||
5008 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
5009 | { | |
3d3ebe74 | 5010 | if (tp->serdes_counter) { |
747e8f8b | 5011 | /* Give autoneg time to complete. */ |
3d3ebe74 | 5012 | tp->serdes_counter--; |
747e8f8b MC |
5013 | return; |
5014 | } | |
c6cdf436 | 5015 | |
747e8f8b MC |
5016 | if (!netif_carrier_ok(tp->dev) && |
5017 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { | |
5018 | u32 bmcr; | |
5019 | ||
5020 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
5021 | if (bmcr & BMCR_ANENABLE) { | |
5022 | u32 phy1, phy2; | |
5023 | ||
5024 | /* Select shadow register 0x1f */ | |
f08aa1a8 MC |
5025 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); |
5026 | tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); | |
747e8f8b MC |
5027 | |
5028 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
5029 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
5030 | MII_TG3_DSP_EXP1_INT_STAT); | |
5031 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
5032 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
5033 | |
5034 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
5035 | /* We have signal detect and not receiving | |
5036 | * config code words, link is up by parallel | |
5037 | * detection. | |
5038 | */ | |
5039 | ||
5040 | bmcr &= ~BMCR_ANENABLE; | |
5041 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
5042 | tg3_writephy(tp, MII_BMCR, bmcr); | |
f07e9af3 | 5043 | tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5044 | } |
5045 | } | |
859a5887 MC |
5046 | } else if (netif_carrier_ok(tp->dev) && |
5047 | (tp->link_config.autoneg == AUTONEG_ENABLE) && | |
f07e9af3 | 5048 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
5049 | u32 phy2; |
5050 | ||
5051 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
5052 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
5053 | MII_TG3_DSP_EXP1_INT_STAT); | |
5054 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
5055 | if (phy2 & 0x20) { |
5056 | u32 bmcr; | |
5057 | ||
5058 | /* Config code words received, turn on autoneg. */ | |
5059 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
5060 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
5061 | ||
f07e9af3 | 5062 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5063 | |
5064 | } | |
5065 | } | |
5066 | } | |
5067 | ||
1da177e4 LT |
5068 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) |
5069 | { | |
f2096f94 | 5070 | u32 val; |
1da177e4 LT |
5071 | int err; |
5072 | ||
f07e9af3 | 5073 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 | 5074 | err = tg3_setup_fiber_phy(tp, force_reset); |
f07e9af3 | 5075 | else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
747e8f8b | 5076 | err = tg3_setup_fiber_mii_phy(tp, force_reset); |
859a5887 | 5077 | else |
1da177e4 | 5078 | err = tg3_setup_copper_phy(tp, force_reset); |
1da177e4 | 5079 | |
bcb37f6c | 5080 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
f2096f94 | 5081 | u32 scale; |
aa6c91fe MC |
5082 | |
5083 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
5084 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
5085 | scale = 65; | |
5086 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
5087 | scale = 6; | |
5088 | else | |
5089 | scale = 12; | |
5090 | ||
5091 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
5092 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
5093 | tw32(GRC_MISC_CFG, val); | |
5094 | } | |
5095 | ||
f2096f94 MC |
5096 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
5097 | (6 << TX_LENGTHS_IPG_SHIFT); | |
5098 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
5099 | val |= tr32(MAC_TX_LENGTHS) & | |
5100 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
5101 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
5102 | ||
1da177e4 LT |
5103 | if (tp->link_config.active_speed == SPEED_1000 && |
5104 | tp->link_config.active_duplex == DUPLEX_HALF) | |
f2096f94 MC |
5105 | tw32(MAC_TX_LENGTHS, val | |
5106 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 5107 | else |
f2096f94 MC |
5108 | tw32(MAC_TX_LENGTHS, val | |
5109 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 5110 | |
63c3a66f | 5111 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
5112 | if (netif_carrier_ok(tp->dev)) { |
5113 | tw32(HOSTCC_STAT_COAL_TICKS, | |
15f9850d | 5114 | tp->coal.stats_block_coalesce_usecs); |
1da177e4 LT |
5115 | } else { |
5116 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
5117 | } | |
5118 | } | |
5119 | ||
63c3a66f | 5120 | if (tg3_flag(tp, ASPM_WORKAROUND)) { |
f2096f94 | 5121 | val = tr32(PCIE_PWR_MGMT_THRESH); |
8ed5d97e MC |
5122 | if (!netif_carrier_ok(tp->dev)) |
5123 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | | |
5124 | tp->pwrmgmt_thresh; | |
5125 | else | |
5126 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
5127 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
5128 | } | |
5129 | ||
1da177e4 LT |
5130 | return err; |
5131 | } | |
5132 | ||
66cfd1bd MC |
5133 | static inline int tg3_irq_sync(struct tg3 *tp) |
5134 | { | |
5135 | return tp->irq_sync; | |
5136 | } | |
5137 | ||
97bd8e49 MC |
5138 | static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) |
5139 | { | |
5140 | int i; | |
5141 | ||
5142 | dst = (u32 *)((u8 *)dst + off); | |
5143 | for (i = 0; i < len; i += sizeof(u32)) | |
5144 | *dst++ = tr32(off + i); | |
5145 | } | |
5146 | ||
5147 | static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) | |
5148 | { | |
5149 | tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); | |
5150 | tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); | |
5151 | tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); | |
5152 | tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); | |
5153 | tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); | |
5154 | tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); | |
5155 | tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); | |
5156 | tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); | |
5157 | tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); | |
5158 | tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); | |
5159 | tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); | |
5160 | tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); | |
5161 | tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); | |
5162 | tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); | |
5163 | tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); | |
5164 | tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); | |
5165 | tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); | |
5166 | tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); | |
5167 | tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); | |
5168 | ||
63c3a66f | 5169 | if (tg3_flag(tp, SUPPORT_MSIX)) |
97bd8e49 MC |
5170 | tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); |
5171 | ||
5172 | tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); | |
5173 | tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); | |
5174 | tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); | |
5175 | tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); | |
5176 | tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); | |
5177 | tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); | |
5178 | tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); | |
5179 | tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); | |
5180 | ||
63c3a66f | 5181 | if (!tg3_flag(tp, 5705_PLUS)) { |
97bd8e49 MC |
5182 | tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); |
5183 | tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); | |
5184 | tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); | |
5185 | } | |
5186 | ||
5187 | tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); | |
5188 | tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); | |
5189 | tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); | |
5190 | tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); | |
5191 | tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); | |
5192 | ||
63c3a66f | 5193 | if (tg3_flag(tp, NVRAM)) |
97bd8e49 MC |
5194 | tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); |
5195 | } | |
5196 | ||
5197 | static void tg3_dump_state(struct tg3 *tp) | |
5198 | { | |
5199 | int i; | |
5200 | u32 *regs; | |
5201 | ||
5202 | regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC); | |
5203 | if (!regs) { | |
5204 | netdev_err(tp->dev, "Failed allocating register dump buffer\n"); | |
5205 | return; | |
5206 | } | |
5207 | ||
63c3a66f | 5208 | if (tg3_flag(tp, PCI_EXPRESS)) { |
97bd8e49 MC |
5209 | /* Read up to but not including private PCI registers */ |
5210 | for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) | |
5211 | regs[i / sizeof(u32)] = tr32(i); | |
5212 | } else | |
5213 | tg3_dump_legacy_regs(tp, regs); | |
5214 | ||
5215 | for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) { | |
5216 | if (!regs[i + 0] && !regs[i + 1] && | |
5217 | !regs[i + 2] && !regs[i + 3]) | |
5218 | continue; | |
5219 | ||
5220 | netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", | |
5221 | i * 4, | |
5222 | regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]); | |
5223 | } | |
5224 | ||
5225 | kfree(regs); | |
5226 | ||
5227 | for (i = 0; i < tp->irq_cnt; i++) { | |
5228 | struct tg3_napi *tnapi = &tp->napi[i]; | |
5229 | ||
5230 | /* SW status block */ | |
5231 | netdev_err(tp->dev, | |
5232 | "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", | |
5233 | i, | |
5234 | tnapi->hw_status->status, | |
5235 | tnapi->hw_status->status_tag, | |
5236 | tnapi->hw_status->rx_jumbo_consumer, | |
5237 | tnapi->hw_status->rx_consumer, | |
5238 | tnapi->hw_status->rx_mini_consumer, | |
5239 | tnapi->hw_status->idx[0].rx_producer, | |
5240 | tnapi->hw_status->idx[0].tx_consumer); | |
5241 | ||
5242 | netdev_err(tp->dev, | |
5243 | "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n", | |
5244 | i, | |
5245 | tnapi->last_tag, tnapi->last_irq_tag, | |
5246 | tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, | |
5247 | tnapi->rx_rcb_ptr, | |
5248 | tnapi->prodring.rx_std_prod_idx, | |
5249 | tnapi->prodring.rx_std_cons_idx, | |
5250 | tnapi->prodring.rx_jmb_prod_idx, | |
5251 | tnapi->prodring.rx_jmb_cons_idx); | |
5252 | } | |
5253 | } | |
5254 | ||
df3e6548 MC |
5255 | /* This is called whenever we suspect that the system chipset is re- |
5256 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
5257 | * is bogus tx completions. We try to recover by setting the | |
5258 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
5259 | * in the workqueue. | |
5260 | */ | |
5261 | static void tg3_tx_recover(struct tg3 *tp) | |
5262 | { | |
63c3a66f | 5263 | BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) || |
df3e6548 MC |
5264 | tp->write32_tx_mbox == tg3_write_indirect_mbox); |
5265 | ||
5129c3a3 MC |
5266 | netdev_warn(tp->dev, |
5267 | "The system may be re-ordering memory-mapped I/O " | |
5268 | "cycles to the network device, attempting to recover. " | |
5269 | "Please report the problem to the driver maintainer " | |
5270 | "and include system chipset information.\n"); | |
df3e6548 MC |
5271 | |
5272 | spin_lock(&tp->lock); | |
63c3a66f | 5273 | tg3_flag_set(tp, TX_RECOVERY_PENDING); |
df3e6548 MC |
5274 | spin_unlock(&tp->lock); |
5275 | } | |
5276 | ||
f3f3f27e | 5277 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) |
1b2a7205 | 5278 | { |
f65aac16 MC |
5279 | /* Tell compiler to fetch tx indices from memory. */ |
5280 | barrier(); | |
f3f3f27e MC |
5281 | return tnapi->tx_pending - |
5282 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
1b2a7205 MC |
5283 | } |
5284 | ||
1da177e4 LT |
5285 | /* Tigon3 never reports partial packet sends. So we do not |
5286 | * need special logic to handle SKBs that have not had all | |
5287 | * of their frags sent yet, like SunGEM does. | |
5288 | */ | |
17375d25 | 5289 | static void tg3_tx(struct tg3_napi *tnapi) |
1da177e4 | 5290 | { |
17375d25 | 5291 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 5292 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; |
f3f3f27e | 5293 | u32 sw_idx = tnapi->tx_cons; |
fe5f5787 MC |
5294 | struct netdev_queue *txq; |
5295 | int index = tnapi - tp->napi; | |
5296 | ||
63c3a66f | 5297 | if (tg3_flag(tp, ENABLE_TSS)) |
fe5f5787 MC |
5298 | index--; |
5299 | ||
5300 | txq = netdev_get_tx_queue(tp->dev, index); | |
1da177e4 LT |
5301 | |
5302 | while (sw_idx != hw_idx) { | |
df8944cf | 5303 | struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; |
1da177e4 | 5304 | struct sk_buff *skb = ri->skb; |
df3e6548 MC |
5305 | int i, tx_bug = 0; |
5306 | ||
5307 | if (unlikely(skb == NULL)) { | |
5308 | tg3_tx_recover(tp); | |
5309 | return; | |
5310 | } | |
1da177e4 | 5311 | |
f4188d8a | 5312 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 5313 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
5314 | skb_headlen(skb), |
5315 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
5316 | |
5317 | ri->skb = NULL; | |
5318 | ||
e01ee14d MC |
5319 | while (ri->fragmented) { |
5320 | ri->fragmented = false; | |
5321 | sw_idx = NEXT_TX(sw_idx); | |
5322 | ri = &tnapi->tx_buffers[sw_idx]; | |
5323 | } | |
5324 | ||
1da177e4 LT |
5325 | sw_idx = NEXT_TX(sw_idx); |
5326 | ||
5327 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
f3f3f27e | 5328 | ri = &tnapi->tx_buffers[sw_idx]; |
df3e6548 MC |
5329 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) |
5330 | tx_bug = 1; | |
f4188d8a AD |
5331 | |
5332 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 5333 | dma_unmap_addr(ri, mapping), |
9e903e08 | 5334 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
f4188d8a | 5335 | PCI_DMA_TODEVICE); |
e01ee14d MC |
5336 | |
5337 | while (ri->fragmented) { | |
5338 | ri->fragmented = false; | |
5339 | sw_idx = NEXT_TX(sw_idx); | |
5340 | ri = &tnapi->tx_buffers[sw_idx]; | |
5341 | } | |
5342 | ||
1da177e4 LT |
5343 | sw_idx = NEXT_TX(sw_idx); |
5344 | } | |
5345 | ||
f47c11ee | 5346 | dev_kfree_skb(skb); |
df3e6548 MC |
5347 | |
5348 | if (unlikely(tx_bug)) { | |
5349 | tg3_tx_recover(tp); | |
5350 | return; | |
5351 | } | |
1da177e4 LT |
5352 | } |
5353 | ||
f3f3f27e | 5354 | tnapi->tx_cons = sw_idx; |
1da177e4 | 5355 | |
1b2a7205 MC |
5356 | /* Need to make the tx_cons update visible to tg3_start_xmit() |
5357 | * before checking for netif_queue_stopped(). Without the | |
5358 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
5359 | * will miss it and cause the queue to be stopped forever. | |
5360 | */ | |
5361 | smp_mb(); | |
5362 | ||
fe5f5787 | 5363 | if (unlikely(netif_tx_queue_stopped(txq) && |
f3f3f27e | 5364 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { |
fe5f5787 MC |
5365 | __netif_tx_lock(txq, smp_processor_id()); |
5366 | if (netif_tx_queue_stopped(txq) && | |
f3f3f27e | 5367 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) |
fe5f5787 MC |
5368 | netif_tx_wake_queue(txq); |
5369 | __netif_tx_unlock(txq); | |
51b91468 | 5370 | } |
1da177e4 LT |
5371 | } |
5372 | ||
2b2cdb65 MC |
5373 | static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) |
5374 | { | |
5375 | if (!ri->skb) | |
5376 | return; | |
5377 | ||
4e5e4f0d | 5378 | pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), |
2b2cdb65 MC |
5379 | map_sz, PCI_DMA_FROMDEVICE); |
5380 | dev_kfree_skb_any(ri->skb); | |
5381 | ri->skb = NULL; | |
5382 | } | |
5383 | ||
1da177e4 LT |
5384 | /* Returns size of skb allocated or < 0 on error. |
5385 | * | |
5386 | * We only need to fill in the address because the other members | |
5387 | * of the RX descriptor are invariant, see tg3_init_rings. | |
5388 | * | |
5389 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
5390 | * posting buffers we only dirty the first cache line of the RX | |
5391 | * descriptor (containing the address). Whereas for the RX status | |
5392 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
5393 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
5394 | */ | |
86b21e59 | 5395 | static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, |
a3896167 | 5396 | u32 opaque_key, u32 dest_idx_unmasked) |
1da177e4 LT |
5397 | { |
5398 | struct tg3_rx_buffer_desc *desc; | |
f94e290e | 5399 | struct ring_info *map; |
1da177e4 LT |
5400 | struct sk_buff *skb; |
5401 | dma_addr_t mapping; | |
5402 | int skb_size, dest_idx; | |
5403 | ||
1da177e4 LT |
5404 | switch (opaque_key) { |
5405 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 5406 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
21f581a5 MC |
5407 | desc = &tpr->rx_std[dest_idx]; |
5408 | map = &tpr->rx_std_buffers[dest_idx]; | |
287be12e | 5409 | skb_size = tp->rx_pkt_map_sz; |
1da177e4 LT |
5410 | break; |
5411 | ||
5412 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 5413 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
79ed5ac7 | 5414 | desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 5415 | map = &tpr->rx_jmb_buffers[dest_idx]; |
287be12e | 5416 | skb_size = TG3_RX_JMB_MAP_SZ; |
1da177e4 LT |
5417 | break; |
5418 | ||
5419 | default: | |
5420 | return -EINVAL; | |
855e1111 | 5421 | } |
1da177e4 LT |
5422 | |
5423 | /* Do not overwrite any of the map or rp information | |
5424 | * until we are sure we can commit to a new buffer. | |
5425 | * | |
5426 | * Callers depend upon this behavior and assume that | |
5427 | * we leave everything unchanged if we fail. | |
5428 | */ | |
81389f57 | 5429 | skb = netdev_alloc_skb(tp->dev, skb_size + TG3_RX_OFFSET(tp)); |
1da177e4 LT |
5430 | if (skb == NULL) |
5431 | return -ENOMEM; | |
5432 | ||
81389f57 | 5433 | skb_reserve(skb, TG3_RX_OFFSET(tp)); |
1da177e4 | 5434 | |
287be12e | 5435 | mapping = pci_map_single(tp->pdev, skb->data, skb_size, |
1da177e4 | 5436 | PCI_DMA_FROMDEVICE); |
a21771dd MC |
5437 | if (pci_dma_mapping_error(tp->pdev, mapping)) { |
5438 | dev_kfree_skb(skb); | |
5439 | return -EIO; | |
5440 | } | |
1da177e4 LT |
5441 | |
5442 | map->skb = skb; | |
4e5e4f0d | 5443 | dma_unmap_addr_set(map, mapping, mapping); |
1da177e4 | 5444 | |
1da177e4 LT |
5445 | desc->addr_hi = ((u64)mapping >> 32); |
5446 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
5447 | ||
5448 | return skb_size; | |
5449 | } | |
5450 | ||
5451 | /* We only need to move over in the address because the other | |
5452 | * members of the RX descriptor are invariant. See notes above | |
5453 | * tg3_alloc_rx_skb for full details. | |
5454 | */ | |
a3896167 MC |
5455 | static void tg3_recycle_rx(struct tg3_napi *tnapi, |
5456 | struct tg3_rx_prodring_set *dpr, | |
5457 | u32 opaque_key, int src_idx, | |
5458 | u32 dest_idx_unmasked) | |
1da177e4 | 5459 | { |
17375d25 | 5460 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
5461 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; |
5462 | struct ring_info *src_map, *dest_map; | |
8fea32b9 | 5463 | struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; |
c6cdf436 | 5464 | int dest_idx; |
1da177e4 LT |
5465 | |
5466 | switch (opaque_key) { | |
5467 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 5468 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
a3896167 MC |
5469 | dest_desc = &dpr->rx_std[dest_idx]; |
5470 | dest_map = &dpr->rx_std_buffers[dest_idx]; | |
5471 | src_desc = &spr->rx_std[src_idx]; | |
5472 | src_map = &spr->rx_std_buffers[src_idx]; | |
1da177e4 LT |
5473 | break; |
5474 | ||
5475 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 5476 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
a3896167 MC |
5477 | dest_desc = &dpr->rx_jmb[dest_idx].std; |
5478 | dest_map = &dpr->rx_jmb_buffers[dest_idx]; | |
5479 | src_desc = &spr->rx_jmb[src_idx].std; | |
5480 | src_map = &spr->rx_jmb_buffers[src_idx]; | |
1da177e4 LT |
5481 | break; |
5482 | ||
5483 | default: | |
5484 | return; | |
855e1111 | 5485 | } |
1da177e4 LT |
5486 | |
5487 | dest_map->skb = src_map->skb; | |
4e5e4f0d FT |
5488 | dma_unmap_addr_set(dest_map, mapping, |
5489 | dma_unmap_addr(src_map, mapping)); | |
1da177e4 LT |
5490 | dest_desc->addr_hi = src_desc->addr_hi; |
5491 | dest_desc->addr_lo = src_desc->addr_lo; | |
e92967bf MC |
5492 | |
5493 | /* Ensure that the update to the skb happens after the physical | |
5494 | * addresses have been transferred to the new BD location. | |
5495 | */ | |
5496 | smp_wmb(); | |
5497 | ||
1da177e4 LT |
5498 | src_map->skb = NULL; |
5499 | } | |
5500 | ||
1da177e4 LT |
5501 | /* The RX ring scheme is composed of multiple rings which post fresh |
5502 | * buffers to the chip, and one special ring the chip uses to report | |
5503 | * status back to the host. | |
5504 | * | |
5505 | * The special ring reports the status of received packets to the | |
5506 | * host. The chip does not write into the original descriptor the | |
5507 | * RX buffer was obtained from. The chip simply takes the original | |
5508 | * descriptor as provided by the host, updates the status and length | |
5509 | * field, then writes this into the next status ring entry. | |
5510 | * | |
5511 | * Each ring the host uses to post buffers to the chip is described | |
5512 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
5513 | * it is first placed into the on-chip ram. When the packet's length | |
5514 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
5515 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
5516 | * which is within the range of the new packet's length is chosen. | |
5517 | * | |
5518 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
5519 | * sense from a cache coherency perspective. If only the host writes | |
5520 | * to the buffer post rings, and only the chip writes to the rx status | |
5521 | * rings, then cache lines never move beyond shared-modified state. | |
5522 | * If both the host and chip were to write into the same ring, cache line | |
5523 | * eviction could occur since both entities want it in an exclusive state. | |
5524 | */ | |
17375d25 | 5525 | static int tg3_rx(struct tg3_napi *tnapi, int budget) |
1da177e4 | 5526 | { |
17375d25 | 5527 | struct tg3 *tp = tnapi->tp; |
f92905de | 5528 | u32 work_mask, rx_std_posted = 0; |
4361935a | 5529 | u32 std_prod_idx, jmb_prod_idx; |
72334482 | 5530 | u32 sw_idx = tnapi->rx_rcb_ptr; |
483ba50b | 5531 | u16 hw_idx; |
1da177e4 | 5532 | int received; |
8fea32b9 | 5533 | struct tg3_rx_prodring_set *tpr = &tnapi->prodring; |
1da177e4 | 5534 | |
8d9d7cfc | 5535 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
1da177e4 LT |
5536 | /* |
5537 | * We need to order the read of hw_idx and the read of | |
5538 | * the opaque cookie. | |
5539 | */ | |
5540 | rmb(); | |
1da177e4 LT |
5541 | work_mask = 0; |
5542 | received = 0; | |
4361935a MC |
5543 | std_prod_idx = tpr->rx_std_prod_idx; |
5544 | jmb_prod_idx = tpr->rx_jmb_prod_idx; | |
1da177e4 | 5545 | while (sw_idx != hw_idx && budget > 0) { |
afc081f8 | 5546 | struct ring_info *ri; |
72334482 | 5547 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
1da177e4 LT |
5548 | unsigned int len; |
5549 | struct sk_buff *skb; | |
5550 | dma_addr_t dma_addr; | |
5551 | u32 opaque_key, desc_idx, *post_ptr; | |
5552 | ||
5553 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
5554 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
5555 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
8fea32b9 | 5556 | ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; |
4e5e4f0d | 5557 | dma_addr = dma_unmap_addr(ri, mapping); |
21f581a5 | 5558 | skb = ri->skb; |
4361935a | 5559 | post_ptr = &std_prod_idx; |
f92905de | 5560 | rx_std_posted++; |
1da177e4 | 5561 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
8fea32b9 | 5562 | ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; |
4e5e4f0d | 5563 | dma_addr = dma_unmap_addr(ri, mapping); |
21f581a5 | 5564 | skb = ri->skb; |
4361935a | 5565 | post_ptr = &jmb_prod_idx; |
21f581a5 | 5566 | } else |
1da177e4 | 5567 | goto next_pkt_nopost; |
1da177e4 LT |
5568 | |
5569 | work_mask |= opaque_key; | |
5570 | ||
5571 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
5572 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
5573 | drop_it: | |
a3896167 | 5574 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
5575 | desc_idx, *post_ptr); |
5576 | drop_it_no_recycle: | |
5577 | /* Other statistics kept track of by card. */ | |
b0057c51 | 5578 | tp->rx_dropped++; |
1da177e4 LT |
5579 | goto next_pkt; |
5580 | } | |
5581 | ||
ad829268 MC |
5582 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - |
5583 | ETH_FCS_LEN; | |
1da177e4 | 5584 | |
d2757fc4 | 5585 | if (len > TG3_RX_COPY_THRESH(tp)) { |
1da177e4 LT |
5586 | int skb_size; |
5587 | ||
86b21e59 | 5588 | skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key, |
afc081f8 | 5589 | *post_ptr); |
1da177e4 LT |
5590 | if (skb_size < 0) |
5591 | goto drop_it; | |
5592 | ||
287be12e | 5593 | pci_unmap_single(tp->pdev, dma_addr, skb_size, |
1da177e4 LT |
5594 | PCI_DMA_FROMDEVICE); |
5595 | ||
61e800cf MC |
5596 | /* Ensure that the update to the skb happens |
5597 | * after the usage of the old DMA mapping. | |
5598 | */ | |
5599 | smp_wmb(); | |
5600 | ||
5601 | ri->skb = NULL; | |
5602 | ||
1da177e4 LT |
5603 | skb_put(skb, len); |
5604 | } else { | |
5605 | struct sk_buff *copy_skb; | |
5606 | ||
a3896167 | 5607 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
5608 | desc_idx, *post_ptr); |
5609 | ||
bf933c80 | 5610 | copy_skb = netdev_alloc_skb(tp->dev, len + |
9dc7a113 | 5611 | TG3_RAW_IP_ALIGN); |
1da177e4 LT |
5612 | if (copy_skb == NULL) |
5613 | goto drop_it_no_recycle; | |
5614 | ||
bf933c80 | 5615 | skb_reserve(copy_skb, TG3_RAW_IP_ALIGN); |
1da177e4 LT |
5616 | skb_put(copy_skb, len); |
5617 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
d626f62b | 5618 | skb_copy_from_linear_data(skb, copy_skb->data, len); |
1da177e4 LT |
5619 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
5620 | ||
5621 | /* We'll reuse the original ring buffer. */ | |
5622 | skb = copy_skb; | |
5623 | } | |
5624 | ||
dc668910 | 5625 | if ((tp->dev->features & NETIF_F_RXCSUM) && |
1da177e4 LT |
5626 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && |
5627 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
5628 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
5629 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
5630 | else | |
bc8acf2c | 5631 | skb_checksum_none_assert(skb); |
1da177e4 LT |
5632 | |
5633 | skb->protocol = eth_type_trans(skb, tp->dev); | |
f7b493e0 MC |
5634 | |
5635 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
5636 | skb->protocol != htons(ETH_P_8021Q)) { | |
5637 | dev_kfree_skb(skb); | |
b0057c51 | 5638 | goto drop_it_no_recycle; |
f7b493e0 MC |
5639 | } |
5640 | ||
9dc7a113 | 5641 | if (desc->type_flags & RXD_FLAG_VLAN && |
bf933c80 MC |
5642 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) |
5643 | __vlan_hwaccel_put_tag(skb, | |
5644 | desc->err_vlan & RXD_VLAN_MASK); | |
9dc7a113 | 5645 | |
bf933c80 | 5646 | napi_gro_receive(&tnapi->napi, skb); |
1da177e4 | 5647 | |
1da177e4 LT |
5648 | received++; |
5649 | budget--; | |
5650 | ||
5651 | next_pkt: | |
5652 | (*post_ptr)++; | |
f92905de MC |
5653 | |
5654 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
2c49a44d MC |
5655 | tpr->rx_std_prod_idx = std_prod_idx & |
5656 | tp->rx_std_ring_mask; | |
86cfe4ff MC |
5657 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
5658 | tpr->rx_std_prod_idx); | |
f92905de MC |
5659 | work_mask &= ~RXD_OPAQUE_RING_STD; |
5660 | rx_std_posted = 0; | |
5661 | } | |
1da177e4 | 5662 | next_pkt_nopost: |
483ba50b | 5663 | sw_idx++; |
7cb32cf2 | 5664 | sw_idx &= tp->rx_ret_ring_mask; |
52f6d697 MC |
5665 | |
5666 | /* Refresh hw_idx to see if there is new work */ | |
5667 | if (sw_idx == hw_idx) { | |
8d9d7cfc | 5668 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
52f6d697 MC |
5669 | rmb(); |
5670 | } | |
1da177e4 LT |
5671 | } |
5672 | ||
5673 | /* ACK the status ring. */ | |
72334482 MC |
5674 | tnapi->rx_rcb_ptr = sw_idx; |
5675 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
1da177e4 LT |
5676 | |
5677 | /* Refill RX ring(s). */ | |
63c3a66f | 5678 | if (!tg3_flag(tp, ENABLE_RSS)) { |
b196c7e4 | 5679 | if (work_mask & RXD_OPAQUE_RING_STD) { |
2c49a44d MC |
5680 | tpr->rx_std_prod_idx = std_prod_idx & |
5681 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
5682 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
5683 | tpr->rx_std_prod_idx); | |
5684 | } | |
5685 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
2c49a44d MC |
5686 | tpr->rx_jmb_prod_idx = jmb_prod_idx & |
5687 | tp->rx_jmb_ring_mask; | |
b196c7e4 MC |
5688 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, |
5689 | tpr->rx_jmb_prod_idx); | |
5690 | } | |
5691 | mmiowb(); | |
5692 | } else if (work_mask) { | |
5693 | /* rx_std_buffers[] and rx_jmb_buffers[] entries must be | |
5694 | * updated before the producer indices can be updated. | |
5695 | */ | |
5696 | smp_wmb(); | |
5697 | ||
2c49a44d MC |
5698 | tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; |
5699 | tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; | |
b196c7e4 | 5700 | |
e4af1af9 MC |
5701 | if (tnapi != &tp->napi[1]) |
5702 | napi_schedule(&tp->napi[1].napi); | |
1da177e4 | 5703 | } |
1da177e4 LT |
5704 | |
5705 | return received; | |
5706 | } | |
5707 | ||
35f2d7d0 | 5708 | static void tg3_poll_link(struct tg3 *tp) |
1da177e4 | 5709 | { |
1da177e4 | 5710 | /* handle link change and other phy events */ |
63c3a66f | 5711 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
35f2d7d0 MC |
5712 | struct tg3_hw_status *sblk = tp->napi[0].hw_status; |
5713 | ||
1da177e4 LT |
5714 | if (sblk->status & SD_STATUS_LINK_CHG) { |
5715 | sblk->status = SD_STATUS_UPDATED | | |
35f2d7d0 | 5716 | (sblk->status & ~SD_STATUS_LINK_CHG); |
f47c11ee | 5717 | spin_lock(&tp->lock); |
63c3a66f | 5718 | if (tg3_flag(tp, USE_PHYLIB)) { |
dd477003 MC |
5719 | tw32_f(MAC_STATUS, |
5720 | (MAC_STATUS_SYNC_CHANGED | | |
5721 | MAC_STATUS_CFG_CHANGED | | |
5722 | MAC_STATUS_MI_COMPLETION | | |
5723 | MAC_STATUS_LNKSTATE_CHANGED)); | |
5724 | udelay(40); | |
5725 | } else | |
5726 | tg3_setup_phy(tp, 0); | |
f47c11ee | 5727 | spin_unlock(&tp->lock); |
1da177e4 LT |
5728 | } |
5729 | } | |
35f2d7d0 MC |
5730 | } |
5731 | ||
f89f38b8 MC |
5732 | static int tg3_rx_prodring_xfer(struct tg3 *tp, |
5733 | struct tg3_rx_prodring_set *dpr, | |
5734 | struct tg3_rx_prodring_set *spr) | |
b196c7e4 MC |
5735 | { |
5736 | u32 si, di, cpycnt, src_prod_idx; | |
f89f38b8 | 5737 | int i, err = 0; |
b196c7e4 MC |
5738 | |
5739 | while (1) { | |
5740 | src_prod_idx = spr->rx_std_prod_idx; | |
5741 | ||
5742 | /* Make sure updates to the rx_std_buffers[] entries and the | |
5743 | * standard producer index are seen in the correct order. | |
5744 | */ | |
5745 | smp_rmb(); | |
5746 | ||
5747 | if (spr->rx_std_cons_idx == src_prod_idx) | |
5748 | break; | |
5749 | ||
5750 | if (spr->rx_std_cons_idx < src_prod_idx) | |
5751 | cpycnt = src_prod_idx - spr->rx_std_cons_idx; | |
5752 | else | |
2c49a44d MC |
5753 | cpycnt = tp->rx_std_ring_mask + 1 - |
5754 | spr->rx_std_cons_idx; | |
b196c7e4 | 5755 | |
2c49a44d MC |
5756 | cpycnt = min(cpycnt, |
5757 | tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); | |
b196c7e4 MC |
5758 | |
5759 | si = spr->rx_std_cons_idx; | |
5760 | di = dpr->rx_std_prod_idx; | |
5761 | ||
e92967bf MC |
5762 | for (i = di; i < di + cpycnt; i++) { |
5763 | if (dpr->rx_std_buffers[i].skb) { | |
5764 | cpycnt = i - di; | |
f89f38b8 | 5765 | err = -ENOSPC; |
e92967bf MC |
5766 | break; |
5767 | } | |
5768 | } | |
5769 | ||
5770 | if (!cpycnt) | |
5771 | break; | |
5772 | ||
5773 | /* Ensure that updates to the rx_std_buffers ring and the | |
5774 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5775 | * ordered correctly WRT the skb check above. | |
5776 | */ | |
5777 | smp_rmb(); | |
5778 | ||
b196c7e4 MC |
5779 | memcpy(&dpr->rx_std_buffers[di], |
5780 | &spr->rx_std_buffers[si], | |
5781 | cpycnt * sizeof(struct ring_info)); | |
5782 | ||
5783 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5784 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5785 | sbd = &spr->rx_std[si]; | |
5786 | dbd = &dpr->rx_std[di]; | |
5787 | dbd->addr_hi = sbd->addr_hi; | |
5788 | dbd->addr_lo = sbd->addr_lo; | |
5789 | } | |
5790 | ||
2c49a44d MC |
5791 | spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & |
5792 | tp->rx_std_ring_mask; | |
5793 | dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & | |
5794 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
5795 | } |
5796 | ||
5797 | while (1) { | |
5798 | src_prod_idx = spr->rx_jmb_prod_idx; | |
5799 | ||
5800 | /* Make sure updates to the rx_jmb_buffers[] entries and | |
5801 | * the jumbo producer index are seen in the correct order. | |
5802 | */ | |
5803 | smp_rmb(); | |
5804 | ||
5805 | if (spr->rx_jmb_cons_idx == src_prod_idx) | |
5806 | break; | |
5807 | ||
5808 | if (spr->rx_jmb_cons_idx < src_prod_idx) | |
5809 | cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; | |
5810 | else | |
2c49a44d MC |
5811 | cpycnt = tp->rx_jmb_ring_mask + 1 - |
5812 | spr->rx_jmb_cons_idx; | |
b196c7e4 MC |
5813 | |
5814 | cpycnt = min(cpycnt, | |
2c49a44d | 5815 | tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); |
b196c7e4 MC |
5816 | |
5817 | si = spr->rx_jmb_cons_idx; | |
5818 | di = dpr->rx_jmb_prod_idx; | |
5819 | ||
e92967bf MC |
5820 | for (i = di; i < di + cpycnt; i++) { |
5821 | if (dpr->rx_jmb_buffers[i].skb) { | |
5822 | cpycnt = i - di; | |
f89f38b8 | 5823 | err = -ENOSPC; |
e92967bf MC |
5824 | break; |
5825 | } | |
5826 | } | |
5827 | ||
5828 | if (!cpycnt) | |
5829 | break; | |
5830 | ||
5831 | /* Ensure that updates to the rx_jmb_buffers ring and the | |
5832 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5833 | * ordered correctly WRT the skb check above. | |
5834 | */ | |
5835 | smp_rmb(); | |
5836 | ||
b196c7e4 MC |
5837 | memcpy(&dpr->rx_jmb_buffers[di], |
5838 | &spr->rx_jmb_buffers[si], | |
5839 | cpycnt * sizeof(struct ring_info)); | |
5840 | ||
5841 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5842 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5843 | sbd = &spr->rx_jmb[si].std; | |
5844 | dbd = &dpr->rx_jmb[di].std; | |
5845 | dbd->addr_hi = sbd->addr_hi; | |
5846 | dbd->addr_lo = sbd->addr_lo; | |
5847 | } | |
5848 | ||
2c49a44d MC |
5849 | spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & |
5850 | tp->rx_jmb_ring_mask; | |
5851 | dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & | |
5852 | tp->rx_jmb_ring_mask; | |
b196c7e4 | 5853 | } |
f89f38b8 MC |
5854 | |
5855 | return err; | |
b196c7e4 MC |
5856 | } |
5857 | ||
35f2d7d0 MC |
5858 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) |
5859 | { | |
5860 | struct tg3 *tp = tnapi->tp; | |
1da177e4 LT |
5861 | |
5862 | /* run TX completion thread */ | |
f3f3f27e | 5863 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { |
17375d25 | 5864 | tg3_tx(tnapi); |
63c3a66f | 5865 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
4fd7ab59 | 5866 | return work_done; |
1da177e4 LT |
5867 | } |
5868 | ||
1da177e4 LT |
5869 | /* run RX thread, within the bounds set by NAPI. |
5870 | * All RX "locking" is done by ensuring outside | |
bea3348e | 5871 | * code synchronizes with tg3->napi.poll() |
1da177e4 | 5872 | */ |
8d9d7cfc | 5873 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
17375d25 | 5874 | work_done += tg3_rx(tnapi, budget - work_done); |
1da177e4 | 5875 | |
63c3a66f | 5876 | if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { |
8fea32b9 | 5877 | struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; |
f89f38b8 | 5878 | int i, err = 0; |
e4af1af9 MC |
5879 | u32 std_prod_idx = dpr->rx_std_prod_idx; |
5880 | u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; | |
b196c7e4 | 5881 | |
e4af1af9 | 5882 | for (i = 1; i < tp->irq_cnt; i++) |
f89f38b8 | 5883 | err |= tg3_rx_prodring_xfer(tp, dpr, |
8fea32b9 | 5884 | &tp->napi[i].prodring); |
b196c7e4 MC |
5885 | |
5886 | wmb(); | |
5887 | ||
e4af1af9 MC |
5888 | if (std_prod_idx != dpr->rx_std_prod_idx) |
5889 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
5890 | dpr->rx_std_prod_idx); | |
b196c7e4 | 5891 | |
e4af1af9 MC |
5892 | if (jmb_prod_idx != dpr->rx_jmb_prod_idx) |
5893 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
5894 | dpr->rx_jmb_prod_idx); | |
b196c7e4 MC |
5895 | |
5896 | mmiowb(); | |
f89f38b8 MC |
5897 | |
5898 | if (err) | |
5899 | tw32_f(HOSTCC_MODE, tp->coal_now); | |
b196c7e4 MC |
5900 | } |
5901 | ||
6f535763 DM |
5902 | return work_done; |
5903 | } | |
5904 | ||
db219973 MC |
5905 | static inline void tg3_reset_task_schedule(struct tg3 *tp) |
5906 | { | |
5907 | if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) | |
5908 | schedule_work(&tp->reset_task); | |
5909 | } | |
5910 | ||
5911 | static inline void tg3_reset_task_cancel(struct tg3 *tp) | |
5912 | { | |
5913 | cancel_work_sync(&tp->reset_task); | |
5914 | tg3_flag_clear(tp, RESET_TASK_PENDING); | |
5915 | } | |
5916 | ||
35f2d7d0 MC |
5917 | static int tg3_poll_msix(struct napi_struct *napi, int budget) |
5918 | { | |
5919 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
5920 | struct tg3 *tp = tnapi->tp; | |
5921 | int work_done = 0; | |
5922 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5923 | ||
5924 | while (1) { | |
5925 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
5926 | ||
63c3a66f | 5927 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
35f2d7d0 MC |
5928 | goto tx_recovery; |
5929 | ||
5930 | if (unlikely(work_done >= budget)) | |
5931 | break; | |
5932 | ||
c6cdf436 | 5933 | /* tp->last_tag is used in tg3_int_reenable() below |
35f2d7d0 MC |
5934 | * to tell the hw how much work has been processed, |
5935 | * so we must read it before checking for more work. | |
5936 | */ | |
5937 | tnapi->last_tag = sblk->status_tag; | |
5938 | tnapi->last_irq_tag = tnapi->last_tag; | |
5939 | rmb(); | |
5940 | ||
5941 | /* check for RX/TX work to do */ | |
6d40db7b MC |
5942 | if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && |
5943 | *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { | |
35f2d7d0 MC |
5944 | napi_complete(napi); |
5945 | /* Reenable interrupts. */ | |
5946 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
5947 | mmiowb(); | |
5948 | break; | |
5949 | } | |
5950 | } | |
5951 | ||
5952 | return work_done; | |
5953 | ||
5954 | tx_recovery: | |
5955 | /* work_done is guaranteed to be less than budget. */ | |
5956 | napi_complete(napi); | |
db219973 | 5957 | tg3_reset_task_schedule(tp); |
35f2d7d0 MC |
5958 | return work_done; |
5959 | } | |
5960 | ||
e64de4e6 MC |
5961 | static void tg3_process_error(struct tg3 *tp) |
5962 | { | |
5963 | u32 val; | |
5964 | bool real_error = false; | |
5965 | ||
63c3a66f | 5966 | if (tg3_flag(tp, ERROR_PROCESSED)) |
e64de4e6 MC |
5967 | return; |
5968 | ||
5969 | /* Check Flow Attention register */ | |
5970 | val = tr32(HOSTCC_FLOW_ATTN); | |
5971 | if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) { | |
5972 | netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); | |
5973 | real_error = true; | |
5974 | } | |
5975 | ||
5976 | if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { | |
5977 | netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); | |
5978 | real_error = true; | |
5979 | } | |
5980 | ||
5981 | if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { | |
5982 | netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); | |
5983 | real_error = true; | |
5984 | } | |
5985 | ||
5986 | if (!real_error) | |
5987 | return; | |
5988 | ||
5989 | tg3_dump_state(tp); | |
5990 | ||
63c3a66f | 5991 | tg3_flag_set(tp, ERROR_PROCESSED); |
db219973 | 5992 | tg3_reset_task_schedule(tp); |
e64de4e6 MC |
5993 | } |
5994 | ||
6f535763 DM |
5995 | static int tg3_poll(struct napi_struct *napi, int budget) |
5996 | { | |
8ef0442f MC |
5997 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
5998 | struct tg3 *tp = tnapi->tp; | |
6f535763 | 5999 | int work_done = 0; |
898a56f8 | 6000 | struct tg3_hw_status *sblk = tnapi->hw_status; |
6f535763 DM |
6001 | |
6002 | while (1) { | |
e64de4e6 MC |
6003 | if (sblk->status & SD_STATUS_ERROR) |
6004 | tg3_process_error(tp); | |
6005 | ||
35f2d7d0 MC |
6006 | tg3_poll_link(tp); |
6007 | ||
17375d25 | 6008 | work_done = tg3_poll_work(tnapi, work_done, budget); |
6f535763 | 6009 | |
63c3a66f | 6010 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
6f535763 DM |
6011 | goto tx_recovery; |
6012 | ||
6013 | if (unlikely(work_done >= budget)) | |
6014 | break; | |
6015 | ||
63c3a66f | 6016 | if (tg3_flag(tp, TAGGED_STATUS)) { |
17375d25 | 6017 | /* tp->last_tag is used in tg3_int_reenable() below |
4fd7ab59 MC |
6018 | * to tell the hw how much work has been processed, |
6019 | * so we must read it before checking for more work. | |
6020 | */ | |
898a56f8 MC |
6021 | tnapi->last_tag = sblk->status_tag; |
6022 | tnapi->last_irq_tag = tnapi->last_tag; | |
4fd7ab59 MC |
6023 | rmb(); |
6024 | } else | |
6025 | sblk->status &= ~SD_STATUS_UPDATED; | |
6f535763 | 6026 | |
17375d25 | 6027 | if (likely(!tg3_has_work(tnapi))) { |
288379f0 | 6028 | napi_complete(napi); |
17375d25 | 6029 | tg3_int_reenable(tnapi); |
6f535763 DM |
6030 | break; |
6031 | } | |
1da177e4 LT |
6032 | } |
6033 | ||
bea3348e | 6034 | return work_done; |
6f535763 DM |
6035 | |
6036 | tx_recovery: | |
4fd7ab59 | 6037 | /* work_done is guaranteed to be less than budget. */ |
288379f0 | 6038 | napi_complete(napi); |
db219973 | 6039 | tg3_reset_task_schedule(tp); |
4fd7ab59 | 6040 | return work_done; |
1da177e4 LT |
6041 | } |
6042 | ||
66cfd1bd MC |
6043 | static void tg3_napi_disable(struct tg3 *tp) |
6044 | { | |
6045 | int i; | |
6046 | ||
6047 | for (i = tp->irq_cnt - 1; i >= 0; i--) | |
6048 | napi_disable(&tp->napi[i].napi); | |
6049 | } | |
6050 | ||
6051 | static void tg3_napi_enable(struct tg3 *tp) | |
6052 | { | |
6053 | int i; | |
6054 | ||
6055 | for (i = 0; i < tp->irq_cnt; i++) | |
6056 | napi_enable(&tp->napi[i].napi); | |
6057 | } | |
6058 | ||
6059 | static void tg3_napi_init(struct tg3 *tp) | |
6060 | { | |
6061 | int i; | |
6062 | ||
6063 | netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); | |
6064 | for (i = 1; i < tp->irq_cnt; i++) | |
6065 | netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); | |
6066 | } | |
6067 | ||
6068 | static void tg3_napi_fini(struct tg3 *tp) | |
6069 | { | |
6070 | int i; | |
6071 | ||
6072 | for (i = 0; i < tp->irq_cnt; i++) | |
6073 | netif_napi_del(&tp->napi[i].napi); | |
6074 | } | |
6075 | ||
6076 | static inline void tg3_netif_stop(struct tg3 *tp) | |
6077 | { | |
6078 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
6079 | tg3_napi_disable(tp); | |
6080 | netif_tx_disable(tp->dev); | |
6081 | } | |
6082 | ||
6083 | static inline void tg3_netif_start(struct tg3 *tp) | |
6084 | { | |
6085 | /* NOTE: unconditional netif_tx_wake_all_queues is only | |
6086 | * appropriate so long as all callers are assured to | |
6087 | * have free tx slots (such as after tg3_init_hw) | |
6088 | */ | |
6089 | netif_tx_wake_all_queues(tp->dev); | |
6090 | ||
6091 | tg3_napi_enable(tp); | |
6092 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; | |
6093 | tg3_enable_ints(tp); | |
6094 | } | |
6095 | ||
f47c11ee DM |
6096 | static void tg3_irq_quiesce(struct tg3 *tp) |
6097 | { | |
4f125f42 MC |
6098 | int i; |
6099 | ||
f47c11ee DM |
6100 | BUG_ON(tp->irq_sync); |
6101 | ||
6102 | tp->irq_sync = 1; | |
6103 | smp_mb(); | |
6104 | ||
4f125f42 MC |
6105 | for (i = 0; i < tp->irq_cnt; i++) |
6106 | synchronize_irq(tp->napi[i].irq_vec); | |
f47c11ee DM |
6107 | } |
6108 | ||
f47c11ee DM |
6109 | /* Fully shutdown all tg3 driver activity elsewhere in the system. |
6110 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
6111 | * with as well. Most of the time, this is not necessary except when | |
6112 | * shutting down the device. | |
6113 | */ | |
6114 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
6115 | { | |
46966545 | 6116 | spin_lock_bh(&tp->lock); |
f47c11ee DM |
6117 | if (irq_sync) |
6118 | tg3_irq_quiesce(tp); | |
f47c11ee DM |
6119 | } |
6120 | ||
6121 | static inline void tg3_full_unlock(struct tg3 *tp) | |
6122 | { | |
f47c11ee DM |
6123 | spin_unlock_bh(&tp->lock); |
6124 | } | |
6125 | ||
fcfa0a32 MC |
6126 | /* One-shot MSI handler - Chip automatically disables interrupt |
6127 | * after sending MSI so driver doesn't have to do it. | |
6128 | */ | |
7d12e780 | 6129 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) |
fcfa0a32 | 6130 | { |
09943a18 MC |
6131 | struct tg3_napi *tnapi = dev_id; |
6132 | struct tg3 *tp = tnapi->tp; | |
fcfa0a32 | 6133 | |
898a56f8 | 6134 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
6135 | if (tnapi->rx_rcb) |
6136 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
fcfa0a32 MC |
6137 | |
6138 | if (likely(!tg3_irq_sync(tp))) | |
09943a18 | 6139 | napi_schedule(&tnapi->napi); |
fcfa0a32 MC |
6140 | |
6141 | return IRQ_HANDLED; | |
6142 | } | |
6143 | ||
88b06bc2 MC |
6144 | /* MSI ISR - No need to check for interrupt sharing and no need to |
6145 | * flush status block and interrupt mailbox. PCI ordering rules | |
6146 | * guarantee that MSI will arrive after the status block. | |
6147 | */ | |
7d12e780 | 6148 | static irqreturn_t tg3_msi(int irq, void *dev_id) |
88b06bc2 | 6149 | { |
09943a18 MC |
6150 | struct tg3_napi *tnapi = dev_id; |
6151 | struct tg3 *tp = tnapi->tp; | |
88b06bc2 | 6152 | |
898a56f8 | 6153 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
6154 | if (tnapi->rx_rcb) |
6155 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
88b06bc2 | 6156 | /* |
fac9b83e | 6157 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
88b06bc2 | 6158 | * chip-internal interrupt pending events. |
fac9b83e | 6159 | * Writing non-zero to intr-mbox-0 additional tells the |
88b06bc2 MC |
6160 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
6161 | * event coalescing. | |
6162 | */ | |
5b39de91 | 6163 | tw32_mailbox(tnapi->int_mbox, 0x00000001); |
61487480 | 6164 | if (likely(!tg3_irq_sync(tp))) |
09943a18 | 6165 | napi_schedule(&tnapi->napi); |
61487480 | 6166 | |
88b06bc2 MC |
6167 | return IRQ_RETVAL(1); |
6168 | } | |
6169 | ||
7d12e780 | 6170 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) |
1da177e4 | 6171 | { |
09943a18 MC |
6172 | struct tg3_napi *tnapi = dev_id; |
6173 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 6174 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 LT |
6175 | unsigned int handled = 1; |
6176 | ||
1da177e4 LT |
6177 | /* In INTx mode, it is possible for the interrupt to arrive at |
6178 | * the CPU before the status block posted prior to the interrupt. | |
6179 | * Reading the PCI State register will confirm whether the | |
6180 | * interrupt is ours and will flush the status block. | |
6181 | */ | |
d18edcb2 | 6182 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { |
63c3a66f | 6183 | if (tg3_flag(tp, CHIP_RESETTING) || |
d18edcb2 MC |
6184 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
6185 | handled = 0; | |
f47c11ee | 6186 | goto out; |
fac9b83e | 6187 | } |
d18edcb2 MC |
6188 | } |
6189 | ||
6190 | /* | |
6191 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
6192 | * chip-internal interrupt pending events. | |
6193 | * Writing non-zero to intr-mbox-0 additional tells the | |
6194 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
6195 | * event coalescing. | |
c04cb347 MC |
6196 | * |
6197 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
6198 | * spurious interrupts. The flush impacts performance but | |
6199 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 6200 | */ |
c04cb347 | 6201 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
d18edcb2 MC |
6202 | if (tg3_irq_sync(tp)) |
6203 | goto out; | |
6204 | sblk->status &= ~SD_STATUS_UPDATED; | |
17375d25 | 6205 | if (likely(tg3_has_work(tnapi))) { |
72334482 | 6206 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
09943a18 | 6207 | napi_schedule(&tnapi->napi); |
d18edcb2 MC |
6208 | } else { |
6209 | /* No work, shared interrupt perhaps? re-enable | |
6210 | * interrupts, and flush that PCI write | |
6211 | */ | |
6212 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
6213 | 0x00000000); | |
fac9b83e | 6214 | } |
f47c11ee | 6215 | out: |
fac9b83e DM |
6216 | return IRQ_RETVAL(handled); |
6217 | } | |
6218 | ||
7d12e780 | 6219 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) |
fac9b83e | 6220 | { |
09943a18 MC |
6221 | struct tg3_napi *tnapi = dev_id; |
6222 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 6223 | struct tg3_hw_status *sblk = tnapi->hw_status; |
fac9b83e DM |
6224 | unsigned int handled = 1; |
6225 | ||
fac9b83e DM |
6226 | /* In INTx mode, it is possible for the interrupt to arrive at |
6227 | * the CPU before the status block posted prior to the interrupt. | |
6228 | * Reading the PCI State register will confirm whether the | |
6229 | * interrupt is ours and will flush the status block. | |
6230 | */ | |
898a56f8 | 6231 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { |
63c3a66f | 6232 | if (tg3_flag(tp, CHIP_RESETTING) || |
d18edcb2 MC |
6233 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
6234 | handled = 0; | |
f47c11ee | 6235 | goto out; |
1da177e4 | 6236 | } |
d18edcb2 MC |
6237 | } |
6238 | ||
6239 | /* | |
6240 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
6241 | * chip-internal interrupt pending events. | |
6242 | * writing non-zero to intr-mbox-0 additional tells the | |
6243 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
6244 | * event coalescing. | |
c04cb347 MC |
6245 | * |
6246 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
6247 | * spurious interrupts. The flush impacts performance but | |
6248 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 6249 | */ |
c04cb347 | 6250 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
624f8e50 MC |
6251 | |
6252 | /* | |
6253 | * In a shared interrupt configuration, sometimes other devices' | |
6254 | * interrupts will scream. We record the current status tag here | |
6255 | * so that the above check can report that the screaming interrupts | |
6256 | * are unhandled. Eventually they will be silenced. | |
6257 | */ | |
898a56f8 | 6258 | tnapi->last_irq_tag = sblk->status_tag; |
624f8e50 | 6259 | |
d18edcb2 MC |
6260 | if (tg3_irq_sync(tp)) |
6261 | goto out; | |
624f8e50 | 6262 | |
72334482 | 6263 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
624f8e50 | 6264 | |
09943a18 | 6265 | napi_schedule(&tnapi->napi); |
624f8e50 | 6266 | |
f47c11ee | 6267 | out: |
1da177e4 LT |
6268 | return IRQ_RETVAL(handled); |
6269 | } | |
6270 | ||
7938109f | 6271 | /* ISR for interrupt test */ |
7d12e780 | 6272 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) |
7938109f | 6273 | { |
09943a18 MC |
6274 | struct tg3_napi *tnapi = dev_id; |
6275 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 6276 | struct tg3_hw_status *sblk = tnapi->hw_status; |
7938109f | 6277 | |
f9804ddb MC |
6278 | if ((sblk->status & SD_STATUS_UPDATED) || |
6279 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
b16250e3 | 6280 | tg3_disable_ints(tp); |
7938109f MC |
6281 | return IRQ_RETVAL(1); |
6282 | } | |
6283 | return IRQ_RETVAL(0); | |
6284 | } | |
6285 | ||
8e7a22e3 | 6286 | static int tg3_init_hw(struct tg3 *, int); |
944d980e | 6287 | static int tg3_halt(struct tg3 *, int, int); |
1da177e4 | 6288 | |
b9ec6c1b MC |
6289 | /* Restart hardware after configuration changes, self-test, etc. |
6290 | * Invoked with tp->lock held. | |
6291 | */ | |
6292 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
78c6146f ED |
6293 | __releases(tp->lock) |
6294 | __acquires(tp->lock) | |
b9ec6c1b MC |
6295 | { |
6296 | int err; | |
6297 | ||
6298 | err = tg3_init_hw(tp, reset_phy); | |
6299 | if (err) { | |
5129c3a3 MC |
6300 | netdev_err(tp->dev, |
6301 | "Failed to re-initialize device, aborting\n"); | |
b9ec6c1b MC |
6302 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
6303 | tg3_full_unlock(tp); | |
6304 | del_timer_sync(&tp->timer); | |
6305 | tp->irq_sync = 0; | |
fed97810 | 6306 | tg3_napi_enable(tp); |
b9ec6c1b MC |
6307 | dev_close(tp->dev); |
6308 | tg3_full_lock(tp, 0); | |
6309 | } | |
6310 | return err; | |
6311 | } | |
6312 | ||
1da177e4 LT |
6313 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6314 | static void tg3_poll_controller(struct net_device *dev) | |
6315 | { | |
4f125f42 | 6316 | int i; |
88b06bc2 MC |
6317 | struct tg3 *tp = netdev_priv(dev); |
6318 | ||
4f125f42 | 6319 | for (i = 0; i < tp->irq_cnt; i++) |
fe234f0e | 6320 | tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); |
1da177e4 LT |
6321 | } |
6322 | #endif | |
6323 | ||
c4028958 | 6324 | static void tg3_reset_task(struct work_struct *work) |
1da177e4 | 6325 | { |
c4028958 | 6326 | struct tg3 *tp = container_of(work, struct tg3, reset_task); |
b02fd9e3 | 6327 | int err; |
1da177e4 | 6328 | |
7faa006f | 6329 | tg3_full_lock(tp, 0); |
7faa006f MC |
6330 | |
6331 | if (!netif_running(tp->dev)) { | |
db219973 | 6332 | tg3_flag_clear(tp, RESET_TASK_PENDING); |
7faa006f MC |
6333 | tg3_full_unlock(tp); |
6334 | return; | |
6335 | } | |
6336 | ||
6337 | tg3_full_unlock(tp); | |
6338 | ||
b02fd9e3 MC |
6339 | tg3_phy_stop(tp); |
6340 | ||
1da177e4 LT |
6341 | tg3_netif_stop(tp); |
6342 | ||
f47c11ee | 6343 | tg3_full_lock(tp, 1); |
1da177e4 | 6344 | |
63c3a66f | 6345 | if (tg3_flag(tp, TX_RECOVERY_PENDING)) { |
df3e6548 MC |
6346 | tp->write32_tx_mbox = tg3_write32_tx_mbox; |
6347 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
63c3a66f JP |
6348 | tg3_flag_set(tp, MBOX_WRITE_REORDER); |
6349 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); | |
df3e6548 MC |
6350 | } |
6351 | ||
944d980e | 6352 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); |
b02fd9e3 MC |
6353 | err = tg3_init_hw(tp, 1); |
6354 | if (err) | |
b9ec6c1b | 6355 | goto out; |
1da177e4 LT |
6356 | |
6357 | tg3_netif_start(tp); | |
6358 | ||
b9ec6c1b | 6359 | out: |
7faa006f | 6360 | tg3_full_unlock(tp); |
b02fd9e3 MC |
6361 | |
6362 | if (!err) | |
6363 | tg3_phy_start(tp); | |
db219973 MC |
6364 | |
6365 | tg3_flag_clear(tp, RESET_TASK_PENDING); | |
1da177e4 LT |
6366 | } |
6367 | ||
6368 | static void tg3_tx_timeout(struct net_device *dev) | |
6369 | { | |
6370 | struct tg3 *tp = netdev_priv(dev); | |
6371 | ||
b0408751 | 6372 | if (netif_msg_tx_err(tp)) { |
05dbe005 | 6373 | netdev_err(dev, "transmit timed out, resetting\n"); |
97bd8e49 | 6374 | tg3_dump_state(tp); |
b0408751 | 6375 | } |
1da177e4 | 6376 | |
db219973 | 6377 | tg3_reset_task_schedule(tp); |
1da177e4 LT |
6378 | } |
6379 | ||
c58ec932 MC |
6380 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ |
6381 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
6382 | { | |
6383 | u32 base = (u32) mapping & 0xffffffff; | |
6384 | ||
807540ba | 6385 | return (base > 0xffffdcc0) && (base + len + 8 < base); |
c58ec932 MC |
6386 | } |
6387 | ||
72f2afb8 MC |
6388 | /* Test for DMA addresses > 40-bit */ |
6389 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
6390 | int len) | |
6391 | { | |
6392 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
63c3a66f | 6393 | if (tg3_flag(tp, 40BIT_DMA_BUG)) |
807540ba | 6394 | return ((u64) mapping + len) > DMA_BIT_MASK(40); |
72f2afb8 MC |
6395 | return 0; |
6396 | #else | |
6397 | return 0; | |
6398 | #endif | |
6399 | } | |
6400 | ||
d1a3b737 | 6401 | static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd, |
92cd3a17 MC |
6402 | dma_addr_t mapping, u32 len, u32 flags, |
6403 | u32 mss, u32 vlan) | |
2ffcc981 | 6404 | { |
92cd3a17 MC |
6405 | txbd->addr_hi = ((u64) mapping >> 32); |
6406 | txbd->addr_lo = ((u64) mapping & 0xffffffff); | |
6407 | txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff); | |
6408 | txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT); | |
2ffcc981 | 6409 | } |
1da177e4 | 6410 | |
84b67b27 | 6411 | static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget, |
d1a3b737 MC |
6412 | dma_addr_t map, u32 len, u32 flags, |
6413 | u32 mss, u32 vlan) | |
6414 | { | |
6415 | struct tg3 *tp = tnapi->tp; | |
6416 | bool hwbug = false; | |
6417 | ||
6418 | if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) | |
6419 | hwbug = 1; | |
6420 | ||
6421 | if (tg3_4g_overflow_test(map, len)) | |
6422 | hwbug = 1; | |
6423 | ||
6424 | if (tg3_40bit_overflow_test(tp, map, len)) | |
6425 | hwbug = 1; | |
6426 | ||
e31aa987 | 6427 | if (tg3_flag(tp, 4K_FIFO_LIMIT)) { |
b9e45482 | 6428 | u32 prvidx = *entry; |
e31aa987 | 6429 | u32 tmp_flag = flags & ~TXD_FLAG_END; |
b9e45482 | 6430 | while (len > TG3_TX_BD_DMA_MAX && *budget) { |
e31aa987 MC |
6431 | u32 frag_len = TG3_TX_BD_DMA_MAX; |
6432 | len -= TG3_TX_BD_DMA_MAX; | |
6433 | ||
b9e45482 MC |
6434 | /* Avoid the 8byte DMA problem */ |
6435 | if (len <= 8) { | |
6436 | len += TG3_TX_BD_DMA_MAX / 2; | |
6437 | frag_len = TG3_TX_BD_DMA_MAX / 2; | |
e31aa987 MC |
6438 | } |
6439 | ||
b9e45482 MC |
6440 | tnapi->tx_buffers[*entry].fragmented = true; |
6441 | ||
6442 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, | |
6443 | frag_len, tmp_flag, mss, vlan); | |
6444 | *budget -= 1; | |
6445 | prvidx = *entry; | |
6446 | *entry = NEXT_TX(*entry); | |
6447 | ||
e31aa987 MC |
6448 | map += frag_len; |
6449 | } | |
6450 | ||
6451 | if (len) { | |
6452 | if (*budget) { | |
6453 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, | |
6454 | len, flags, mss, vlan); | |
b9e45482 | 6455 | *budget -= 1; |
e31aa987 MC |
6456 | *entry = NEXT_TX(*entry); |
6457 | } else { | |
6458 | hwbug = 1; | |
b9e45482 | 6459 | tnapi->tx_buffers[prvidx].fragmented = false; |
e31aa987 MC |
6460 | } |
6461 | } | |
6462 | } else { | |
84b67b27 MC |
6463 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, |
6464 | len, flags, mss, vlan); | |
e31aa987 MC |
6465 | *entry = NEXT_TX(*entry); |
6466 | } | |
d1a3b737 MC |
6467 | |
6468 | return hwbug; | |
6469 | } | |
6470 | ||
0d681b27 | 6471 | static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last) |
432aa7ed MC |
6472 | { |
6473 | int i; | |
0d681b27 | 6474 | struct sk_buff *skb; |
df8944cf | 6475 | struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry]; |
432aa7ed | 6476 | |
0d681b27 MC |
6477 | skb = txb->skb; |
6478 | txb->skb = NULL; | |
6479 | ||
432aa7ed MC |
6480 | pci_unmap_single(tnapi->tp->pdev, |
6481 | dma_unmap_addr(txb, mapping), | |
6482 | skb_headlen(skb), | |
6483 | PCI_DMA_TODEVICE); | |
e01ee14d MC |
6484 | |
6485 | while (txb->fragmented) { | |
6486 | txb->fragmented = false; | |
6487 | entry = NEXT_TX(entry); | |
6488 | txb = &tnapi->tx_buffers[entry]; | |
6489 | } | |
6490 | ||
ba1142e4 | 6491 | for (i = 0; i <= last; i++) { |
9e903e08 | 6492 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
432aa7ed MC |
6493 | |
6494 | entry = NEXT_TX(entry); | |
6495 | txb = &tnapi->tx_buffers[entry]; | |
6496 | ||
6497 | pci_unmap_page(tnapi->tp->pdev, | |
6498 | dma_unmap_addr(txb, mapping), | |
9e903e08 | 6499 | skb_frag_size(frag), PCI_DMA_TODEVICE); |
e01ee14d MC |
6500 | |
6501 | while (txb->fragmented) { | |
6502 | txb->fragmented = false; | |
6503 | entry = NEXT_TX(entry); | |
6504 | txb = &tnapi->tx_buffers[entry]; | |
6505 | } | |
432aa7ed MC |
6506 | } |
6507 | } | |
6508 | ||
72f2afb8 | 6509 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ |
24f4efd4 | 6510 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, |
f7ff1987 | 6511 | struct sk_buff **pskb, |
84b67b27 | 6512 | u32 *entry, u32 *budget, |
92cd3a17 | 6513 | u32 base_flags, u32 mss, u32 vlan) |
1da177e4 | 6514 | { |
24f4efd4 | 6515 | struct tg3 *tp = tnapi->tp; |
f7ff1987 | 6516 | struct sk_buff *new_skb, *skb = *pskb; |
c58ec932 | 6517 | dma_addr_t new_addr = 0; |
432aa7ed | 6518 | int ret = 0; |
1da177e4 | 6519 | |
41588ba1 MC |
6520 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
6521 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
6522 | else { | |
6523 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
6524 | ||
6525 | new_skb = skb_copy_expand(skb, | |
6526 | skb_headroom(skb) + more_headroom, | |
6527 | skb_tailroom(skb), GFP_ATOMIC); | |
6528 | } | |
6529 | ||
1da177e4 | 6530 | if (!new_skb) { |
c58ec932 MC |
6531 | ret = -1; |
6532 | } else { | |
6533 | /* New SKB is guaranteed to be linear. */ | |
f4188d8a AD |
6534 | new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, |
6535 | PCI_DMA_TODEVICE); | |
6536 | /* Make sure the mapping succeeded */ | |
6537 | if (pci_dma_mapping_error(tp->pdev, new_addr)) { | |
f4188d8a | 6538 | dev_kfree_skb(new_skb); |
c58ec932 | 6539 | ret = -1; |
c58ec932 | 6540 | } else { |
b9e45482 MC |
6541 | u32 save_entry = *entry; |
6542 | ||
92cd3a17 MC |
6543 | base_flags |= TXD_FLAG_END; |
6544 | ||
84b67b27 MC |
6545 | tnapi->tx_buffers[*entry].skb = new_skb; |
6546 | dma_unmap_addr_set(&tnapi->tx_buffers[*entry], | |
432aa7ed MC |
6547 | mapping, new_addr); |
6548 | ||
84b67b27 | 6549 | if (tg3_tx_frag_set(tnapi, entry, budget, new_addr, |
d1a3b737 MC |
6550 | new_skb->len, base_flags, |
6551 | mss, vlan)) { | |
ba1142e4 | 6552 | tg3_tx_skb_unmap(tnapi, save_entry, -1); |
d1a3b737 MC |
6553 | dev_kfree_skb(new_skb); |
6554 | ret = -1; | |
6555 | } | |
f4188d8a | 6556 | } |
1da177e4 LT |
6557 | } |
6558 | ||
6559 | dev_kfree_skb(skb); | |
f7ff1987 | 6560 | *pskb = new_skb; |
c58ec932 | 6561 | return ret; |
1da177e4 LT |
6562 | } |
6563 | ||
2ffcc981 | 6564 | static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *); |
52c0fd83 MC |
6565 | |
6566 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
6567 | * TSO header is greater than 80 bytes. | |
6568 | */ | |
6569 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
6570 | { | |
6571 | struct sk_buff *segs, *nskb; | |
f3f3f27e | 6572 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; |
52c0fd83 MC |
6573 | |
6574 | /* Estimate the number of fragments in the worst case */ | |
f3f3f27e | 6575 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { |
52c0fd83 | 6576 | netif_stop_queue(tp->dev); |
f65aac16 MC |
6577 | |
6578 | /* netif_tx_stop_queue() must be done before checking | |
6579 | * checking tx index in tg3_tx_avail() below, because in | |
6580 | * tg3_tx(), we update tx index before checking for | |
6581 | * netif_tx_queue_stopped(). | |
6582 | */ | |
6583 | smp_mb(); | |
f3f3f27e | 6584 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) |
7f62ad5d MC |
6585 | return NETDEV_TX_BUSY; |
6586 | ||
6587 | netif_wake_queue(tp->dev); | |
52c0fd83 MC |
6588 | } |
6589 | ||
6590 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
801678c5 | 6591 | if (IS_ERR(segs)) |
52c0fd83 MC |
6592 | goto tg3_tso_bug_end; |
6593 | ||
6594 | do { | |
6595 | nskb = segs; | |
6596 | segs = segs->next; | |
6597 | nskb->next = NULL; | |
2ffcc981 | 6598 | tg3_start_xmit(nskb, tp->dev); |
52c0fd83 MC |
6599 | } while (segs); |
6600 | ||
6601 | tg3_tso_bug_end: | |
6602 | dev_kfree_skb(skb); | |
6603 | ||
6604 | return NETDEV_TX_OK; | |
6605 | } | |
52c0fd83 | 6606 | |
5a6f3074 | 6607 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and |
63c3a66f | 6608 | * support TG3_FLAG_HW_TSO_1 or firmware TSO only. |
5a6f3074 | 6609 | */ |
2ffcc981 | 6610 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 LT |
6611 | { |
6612 | struct tg3 *tp = netdev_priv(dev); | |
92cd3a17 | 6613 | u32 len, entry, base_flags, mss, vlan = 0; |
84b67b27 | 6614 | u32 budget; |
432aa7ed | 6615 | int i = -1, would_hit_hwbug; |
90079ce8 | 6616 | dma_addr_t mapping; |
24f4efd4 MC |
6617 | struct tg3_napi *tnapi; |
6618 | struct netdev_queue *txq; | |
432aa7ed | 6619 | unsigned int last; |
f4188d8a | 6620 | |
24f4efd4 MC |
6621 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
6622 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
63c3a66f | 6623 | if (tg3_flag(tp, ENABLE_TSS)) |
24f4efd4 | 6624 | tnapi++; |
1da177e4 | 6625 | |
84b67b27 MC |
6626 | budget = tg3_tx_avail(tnapi); |
6627 | ||
00b70504 | 6628 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 6629 | * and TX reclaim runs via tp->napi.poll inside of a software |
f47c11ee DM |
6630 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
6631 | * no IRQ context deadlocks to worry about either. Rejoice! | |
1da177e4 | 6632 | */ |
84b67b27 | 6633 | if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { |
24f4efd4 MC |
6634 | if (!netif_tx_queue_stopped(txq)) { |
6635 | netif_tx_stop_queue(txq); | |
1f064a87 SH |
6636 | |
6637 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
6638 | netdev_err(dev, |
6639 | "BUG! Tx Ring full when queue awake!\n"); | |
1f064a87 | 6640 | } |
1da177e4 LT |
6641 | return NETDEV_TX_BUSY; |
6642 | } | |
6643 | ||
f3f3f27e | 6644 | entry = tnapi->tx_prod; |
1da177e4 | 6645 | base_flags = 0; |
84fa7933 | 6646 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
1da177e4 | 6647 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
24f4efd4 | 6648 | |
be98da6a MC |
6649 | mss = skb_shinfo(skb)->gso_size; |
6650 | if (mss) { | |
eddc9ec5 | 6651 | struct iphdr *iph; |
34195c3d | 6652 | u32 tcp_opt_len, hdr_len; |
1da177e4 LT |
6653 | |
6654 | if (skb_header_cloned(skb) && | |
48855432 ED |
6655 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) |
6656 | goto drop; | |
1da177e4 | 6657 | |
34195c3d | 6658 | iph = ip_hdr(skb); |
ab6a5bb6 | 6659 | tcp_opt_len = tcp_optlen(skb); |
1da177e4 | 6660 | |
02e96080 | 6661 | if (skb_is_gso_v6(skb)) { |
34195c3d MC |
6662 | hdr_len = skb_headlen(skb) - ETH_HLEN; |
6663 | } else { | |
6664 | u32 ip_tcp_len; | |
6665 | ||
6666 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); | |
6667 | hdr_len = ip_tcp_len + tcp_opt_len; | |
6668 | ||
6669 | iph->check = 0; | |
6670 | iph->tot_len = htons(mss + hdr_len); | |
6671 | } | |
6672 | ||
52c0fd83 | 6673 | if (unlikely((ETH_HLEN + hdr_len) > 80) && |
63c3a66f | 6674 | tg3_flag(tp, TSO_BUG)) |
de6f31eb | 6675 | return tg3_tso_bug(tp, skb); |
52c0fd83 | 6676 | |
1da177e4 LT |
6677 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
6678 | TXD_FLAG_CPU_POST_DMA); | |
6679 | ||
63c3a66f JP |
6680 | if (tg3_flag(tp, HW_TSO_1) || |
6681 | tg3_flag(tp, HW_TSO_2) || | |
6682 | tg3_flag(tp, HW_TSO_3)) { | |
aa8223c7 | 6683 | tcp_hdr(skb)->check = 0; |
1da177e4 | 6684 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; |
aa8223c7 ACM |
6685 | } else |
6686 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
6687 | iph->daddr, 0, | |
6688 | IPPROTO_TCP, | |
6689 | 0); | |
1da177e4 | 6690 | |
63c3a66f | 6691 | if (tg3_flag(tp, HW_TSO_3)) { |
615774fe MC |
6692 | mss |= (hdr_len & 0xc) << 12; |
6693 | if (hdr_len & 0x10) | |
6694 | base_flags |= 0x00000010; | |
6695 | base_flags |= (hdr_len & 0x3e0) << 5; | |
63c3a66f | 6696 | } else if (tg3_flag(tp, HW_TSO_2)) |
92c6b8d1 | 6697 | mss |= hdr_len << 9; |
63c3a66f | 6698 | else if (tg3_flag(tp, HW_TSO_1) || |
92c6b8d1 | 6699 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
eddc9ec5 | 6700 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
6701 | int tsflags; |
6702 | ||
eddc9ec5 | 6703 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
6704 | mss |= (tsflags << 11); |
6705 | } | |
6706 | } else { | |
eddc9ec5 | 6707 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
6708 | int tsflags; |
6709 | ||
eddc9ec5 | 6710 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
6711 | base_flags |= tsflags << 12; |
6712 | } | |
6713 | } | |
6714 | } | |
bf933c80 | 6715 | |
93a700a9 MC |
6716 | if (tg3_flag(tp, USE_JUMBO_BDFLAG) && |
6717 | !mss && skb->len > VLAN_ETH_FRAME_LEN) | |
6718 | base_flags |= TXD_FLAG_JMB_PKT; | |
6719 | ||
92cd3a17 MC |
6720 | if (vlan_tx_tag_present(skb)) { |
6721 | base_flags |= TXD_FLAG_VLAN; | |
6722 | vlan = vlan_tx_tag_get(skb); | |
6723 | } | |
1da177e4 | 6724 | |
f4188d8a AD |
6725 | len = skb_headlen(skb); |
6726 | ||
6727 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
48855432 ED |
6728 | if (pci_dma_mapping_error(tp->pdev, mapping)) |
6729 | goto drop; | |
6730 | ||
90079ce8 | 6731 | |
f3f3f27e | 6732 | tnapi->tx_buffers[entry].skb = skb; |
4e5e4f0d | 6733 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
1da177e4 LT |
6734 | |
6735 | would_hit_hwbug = 0; | |
6736 | ||
63c3a66f | 6737 | if (tg3_flag(tp, 5701_DMA_BUG)) |
c58ec932 | 6738 | would_hit_hwbug = 1; |
1da177e4 | 6739 | |
84b67b27 | 6740 | if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags | |
d1a3b737 | 6741 | ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0), |
ba1142e4 | 6742 | mss, vlan)) { |
d1a3b737 | 6743 | would_hit_hwbug = 1; |
1da177e4 | 6744 | /* Now loop through additional data fragments, and queue them. */ |
ba1142e4 | 6745 | } else if (skb_shinfo(skb)->nr_frags > 0) { |
92cd3a17 MC |
6746 | u32 tmp_mss = mss; |
6747 | ||
6748 | if (!tg3_flag(tp, HW_TSO_1) && | |
6749 | !tg3_flag(tp, HW_TSO_2) && | |
6750 | !tg3_flag(tp, HW_TSO_3)) | |
6751 | tmp_mss = 0; | |
6752 | ||
1da177e4 LT |
6753 | last = skb_shinfo(skb)->nr_frags - 1; |
6754 | for (i = 0; i <= last; i++) { | |
6755 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6756 | ||
9e903e08 | 6757 | len = skb_frag_size(frag); |
dc234d0b | 6758 | mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, |
5d6bcdfe | 6759 | len, DMA_TO_DEVICE); |
1da177e4 | 6760 | |
f3f3f27e | 6761 | tnapi->tx_buffers[entry].skb = NULL; |
4e5e4f0d | 6762 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a | 6763 | mapping); |
5d6bcdfe | 6764 | if (dma_mapping_error(&tp->pdev->dev, mapping)) |
f4188d8a | 6765 | goto dma_error; |
1da177e4 | 6766 | |
b9e45482 MC |
6767 | if (!budget || |
6768 | tg3_tx_frag_set(tnapi, &entry, &budget, mapping, | |
84b67b27 MC |
6769 | len, base_flags | |
6770 | ((i == last) ? TXD_FLAG_END : 0), | |
b9e45482 | 6771 | tmp_mss, vlan)) { |
72f2afb8 | 6772 | would_hit_hwbug = 1; |
b9e45482 MC |
6773 | break; |
6774 | } | |
1da177e4 LT |
6775 | } |
6776 | } | |
6777 | ||
6778 | if (would_hit_hwbug) { | |
0d681b27 | 6779 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i); |
1da177e4 LT |
6780 | |
6781 | /* If the workaround fails due to memory/mapping | |
6782 | * failure, silently drop this packet. | |
6783 | */ | |
84b67b27 MC |
6784 | entry = tnapi->tx_prod; |
6785 | budget = tg3_tx_avail(tnapi); | |
f7ff1987 | 6786 | if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget, |
84b67b27 | 6787 | base_flags, mss, vlan)) |
48855432 | 6788 | goto drop_nofree; |
1da177e4 LT |
6789 | } |
6790 | ||
d515b450 RC |
6791 | skb_tx_timestamp(skb); |
6792 | ||
1da177e4 | 6793 | /* Packets are ready, update Tx producer idx local and on card. */ |
24f4efd4 | 6794 | tw32_tx_mbox(tnapi->prodmbox, entry); |
1da177e4 | 6795 | |
f3f3f27e MC |
6796 | tnapi->tx_prod = entry; |
6797 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
24f4efd4 | 6798 | netif_tx_stop_queue(txq); |
f65aac16 MC |
6799 | |
6800 | /* netif_tx_stop_queue() must be done before checking | |
6801 | * checking tx index in tg3_tx_avail() below, because in | |
6802 | * tg3_tx(), we update tx index before checking for | |
6803 | * netif_tx_queue_stopped(). | |
6804 | */ | |
6805 | smp_mb(); | |
f3f3f27e | 6806 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
24f4efd4 | 6807 | netif_tx_wake_queue(txq); |
51b91468 | 6808 | } |
1da177e4 | 6809 | |
cdd0db05 | 6810 | mmiowb(); |
1da177e4 | 6811 | return NETDEV_TX_OK; |
f4188d8a AD |
6812 | |
6813 | dma_error: | |
ba1142e4 | 6814 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i); |
432aa7ed | 6815 | tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; |
48855432 ED |
6816 | drop: |
6817 | dev_kfree_skb(skb); | |
6818 | drop_nofree: | |
6819 | tp->tx_dropped++; | |
f4188d8a | 6820 | return NETDEV_TX_OK; |
1da177e4 LT |
6821 | } |
6822 | ||
6e01b20b MC |
6823 | static void tg3_mac_loopback(struct tg3 *tp, bool enable) |
6824 | { | |
6825 | if (enable) { | |
6826 | tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | | |
6827 | MAC_MODE_PORT_MODE_MASK); | |
6828 | ||
6829 | tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; | |
6830 | ||
6831 | if (!tg3_flag(tp, 5705_PLUS)) | |
6832 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
6833 | ||
6834 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
6835 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
6836 | else | |
6837 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
6838 | } else { | |
6839 | tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; | |
6840 | ||
6841 | if (tg3_flag(tp, 5705_PLUS) || | |
6842 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || | |
6843 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
6844 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
6845 | } | |
6846 | ||
6847 | tw32(MAC_MODE, tp->mac_mode); | |
6848 | udelay(40); | |
6849 | } | |
6850 | ||
941ec90f | 6851 | static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) |
5e5a7f37 | 6852 | { |
941ec90f | 6853 | u32 val, bmcr, mac_mode, ptest = 0; |
5e5a7f37 MC |
6854 | |
6855 | tg3_phy_toggle_apd(tp, false); | |
6856 | tg3_phy_toggle_automdix(tp, 0); | |
6857 | ||
941ec90f MC |
6858 | if (extlpbk && tg3_phy_set_extloopbk(tp)) |
6859 | return -EIO; | |
6860 | ||
6861 | bmcr = BMCR_FULLDPLX; | |
5e5a7f37 MC |
6862 | switch (speed) { |
6863 | case SPEED_10: | |
6864 | break; | |
6865 | case SPEED_100: | |
6866 | bmcr |= BMCR_SPEED100; | |
6867 | break; | |
6868 | case SPEED_1000: | |
6869 | default: | |
6870 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { | |
6871 | speed = SPEED_100; | |
6872 | bmcr |= BMCR_SPEED100; | |
6873 | } else { | |
6874 | speed = SPEED_1000; | |
6875 | bmcr |= BMCR_SPEED1000; | |
6876 | } | |
6877 | } | |
6878 | ||
941ec90f MC |
6879 | if (extlpbk) { |
6880 | if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
6881 | tg3_readphy(tp, MII_CTRL1000, &val); | |
6882 | val |= CTL1000_AS_MASTER | | |
6883 | CTL1000_ENABLE_MASTER; | |
6884 | tg3_writephy(tp, MII_CTRL1000, val); | |
6885 | } else { | |
6886 | ptest = MII_TG3_FET_PTEST_TRIM_SEL | | |
6887 | MII_TG3_FET_PTEST_TRIM_2; | |
6888 | tg3_writephy(tp, MII_TG3_FET_PTEST, ptest); | |
6889 | } | |
6890 | } else | |
6891 | bmcr |= BMCR_LOOPBACK; | |
6892 | ||
5e5a7f37 MC |
6893 | tg3_writephy(tp, MII_BMCR, bmcr); |
6894 | ||
6895 | /* The write needs to be flushed for the FETs */ | |
6896 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) | |
6897 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
6898 | ||
6899 | udelay(40); | |
6900 | ||
6901 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && | |
6902 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { | |
941ec90f | 6903 | tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | |
5e5a7f37 MC |
6904 | MII_TG3_FET_PTEST_FRC_TX_LINK | |
6905 | MII_TG3_FET_PTEST_FRC_TX_LOCK); | |
6906 | ||
6907 | /* The write needs to be flushed for the AC131 */ | |
6908 | tg3_readphy(tp, MII_TG3_FET_PTEST, &val); | |
6909 | } | |
6910 | ||
6911 | /* Reset to prevent losing 1st rx packet intermittently */ | |
6912 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && | |
6913 | tg3_flag(tp, 5780_CLASS)) { | |
6914 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
6915 | udelay(10); | |
6916 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
6917 | } | |
6918 | ||
6919 | mac_mode = tp->mac_mode & | |
6920 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
6921 | if (speed == SPEED_1000) | |
6922 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
6923 | else | |
6924 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
6925 | ||
6926 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { | |
6927 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; | |
6928 | ||
6929 | if (masked_phy_id == TG3_PHY_ID_BCM5401) | |
6930 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
6931 | else if (masked_phy_id == TG3_PHY_ID_BCM5411) | |
6932 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
6933 | ||
6934 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
6935 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
6936 | } | |
6937 | ||
6938 | tw32(MAC_MODE, mac_mode); | |
6939 | udelay(40); | |
941ec90f MC |
6940 | |
6941 | return 0; | |
5e5a7f37 MC |
6942 | } |
6943 | ||
c8f44aff | 6944 | static void tg3_set_loopback(struct net_device *dev, netdev_features_t features) |
06c03c02 MB |
6945 | { |
6946 | struct tg3 *tp = netdev_priv(dev); | |
6947 | ||
6948 | if (features & NETIF_F_LOOPBACK) { | |
6949 | if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) | |
6950 | return; | |
6951 | ||
06c03c02 | 6952 | spin_lock_bh(&tp->lock); |
6e01b20b | 6953 | tg3_mac_loopback(tp, true); |
06c03c02 MB |
6954 | netif_carrier_on(tp->dev); |
6955 | spin_unlock_bh(&tp->lock); | |
6956 | netdev_info(dev, "Internal MAC loopback mode enabled.\n"); | |
6957 | } else { | |
6958 | if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
6959 | return; | |
6960 | ||
06c03c02 | 6961 | spin_lock_bh(&tp->lock); |
6e01b20b | 6962 | tg3_mac_loopback(tp, false); |
06c03c02 MB |
6963 | /* Force link status check */ |
6964 | tg3_setup_phy(tp, 1); | |
6965 | spin_unlock_bh(&tp->lock); | |
6966 | netdev_info(dev, "Internal MAC loopback mode disabled.\n"); | |
6967 | } | |
6968 | } | |
6969 | ||
c8f44aff MM |
6970 | static netdev_features_t tg3_fix_features(struct net_device *dev, |
6971 | netdev_features_t features) | |
dc668910 MM |
6972 | { |
6973 | struct tg3 *tp = netdev_priv(dev); | |
6974 | ||
63c3a66f | 6975 | if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) |
dc668910 MM |
6976 | features &= ~NETIF_F_ALL_TSO; |
6977 | ||
6978 | return features; | |
6979 | } | |
6980 | ||
c8f44aff | 6981 | static int tg3_set_features(struct net_device *dev, netdev_features_t features) |
06c03c02 | 6982 | { |
c8f44aff | 6983 | netdev_features_t changed = dev->features ^ features; |
06c03c02 MB |
6984 | |
6985 | if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) | |
6986 | tg3_set_loopback(dev, features); | |
6987 | ||
6988 | return 0; | |
6989 | } | |
6990 | ||
1da177e4 LT |
6991 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, |
6992 | int new_mtu) | |
6993 | { | |
6994 | dev->mtu = new_mtu; | |
6995 | ||
ef7f5ec0 | 6996 | if (new_mtu > ETH_DATA_LEN) { |
63c3a66f | 6997 | if (tg3_flag(tp, 5780_CLASS)) { |
dc668910 | 6998 | netdev_update_features(dev); |
63c3a66f | 6999 | tg3_flag_clear(tp, TSO_CAPABLE); |
859a5887 | 7000 | } else { |
63c3a66f | 7001 | tg3_flag_set(tp, JUMBO_RING_ENABLE); |
859a5887 | 7002 | } |
ef7f5ec0 | 7003 | } else { |
63c3a66f JP |
7004 | if (tg3_flag(tp, 5780_CLASS)) { |
7005 | tg3_flag_set(tp, TSO_CAPABLE); | |
dc668910 MM |
7006 | netdev_update_features(dev); |
7007 | } | |
63c3a66f | 7008 | tg3_flag_clear(tp, JUMBO_RING_ENABLE); |
ef7f5ec0 | 7009 | } |
1da177e4 LT |
7010 | } |
7011 | ||
7012 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
7013 | { | |
7014 | struct tg3 *tp = netdev_priv(dev); | |
b9ec6c1b | 7015 | int err; |
1da177e4 LT |
7016 | |
7017 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
7018 | return -EINVAL; | |
7019 | ||
7020 | if (!netif_running(dev)) { | |
7021 | /* We'll just catch it later when the | |
7022 | * device is up'd. | |
7023 | */ | |
7024 | tg3_set_mtu(dev, tp, new_mtu); | |
7025 | return 0; | |
7026 | } | |
7027 | ||
b02fd9e3 MC |
7028 | tg3_phy_stop(tp); |
7029 | ||
1da177e4 | 7030 | tg3_netif_stop(tp); |
f47c11ee DM |
7031 | |
7032 | tg3_full_lock(tp, 1); | |
1da177e4 | 7033 | |
944d980e | 7034 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
7035 | |
7036 | tg3_set_mtu(dev, tp, new_mtu); | |
7037 | ||
b9ec6c1b | 7038 | err = tg3_restart_hw(tp, 0); |
1da177e4 | 7039 | |
b9ec6c1b MC |
7040 | if (!err) |
7041 | tg3_netif_start(tp); | |
1da177e4 | 7042 | |
f47c11ee | 7043 | tg3_full_unlock(tp); |
1da177e4 | 7044 | |
b02fd9e3 MC |
7045 | if (!err) |
7046 | tg3_phy_start(tp); | |
7047 | ||
b9ec6c1b | 7048 | return err; |
1da177e4 LT |
7049 | } |
7050 | ||
21f581a5 MC |
7051 | static void tg3_rx_prodring_free(struct tg3 *tp, |
7052 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 7053 | { |
1da177e4 LT |
7054 | int i; |
7055 | ||
8fea32b9 | 7056 | if (tpr != &tp->napi[0].prodring) { |
b196c7e4 | 7057 | for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; |
2c49a44d | 7058 | i = (i + 1) & tp->rx_std_ring_mask) |
b196c7e4 MC |
7059 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], |
7060 | tp->rx_pkt_map_sz); | |
7061 | ||
63c3a66f | 7062 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
b196c7e4 MC |
7063 | for (i = tpr->rx_jmb_cons_idx; |
7064 | i != tpr->rx_jmb_prod_idx; | |
2c49a44d | 7065 | i = (i + 1) & tp->rx_jmb_ring_mask) { |
b196c7e4 MC |
7066 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], |
7067 | TG3_RX_JMB_MAP_SZ); | |
7068 | } | |
7069 | } | |
7070 | ||
2b2cdb65 | 7071 | return; |
b196c7e4 | 7072 | } |
1da177e4 | 7073 | |
2c49a44d | 7074 | for (i = 0; i <= tp->rx_std_ring_mask; i++) |
2b2cdb65 MC |
7075 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], |
7076 | tp->rx_pkt_map_sz); | |
1da177e4 | 7077 | |
63c3a66f | 7078 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
2c49a44d | 7079 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) |
2b2cdb65 MC |
7080 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], |
7081 | TG3_RX_JMB_MAP_SZ); | |
1da177e4 LT |
7082 | } |
7083 | } | |
7084 | ||
c6cdf436 | 7085 | /* Initialize rx rings for packet processing. |
1da177e4 LT |
7086 | * |
7087 | * The chip has been shut down and the driver detached from | |
7088 | * the networking, so no interrupts or new tx packets will | |
7089 | * end up in the driver. tp->{tx,}lock are held and thus | |
7090 | * we may not sleep. | |
7091 | */ | |
21f581a5 MC |
7092 | static int tg3_rx_prodring_alloc(struct tg3 *tp, |
7093 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 7094 | { |
287be12e | 7095 | u32 i, rx_pkt_dma_sz; |
1da177e4 | 7096 | |
b196c7e4 MC |
7097 | tpr->rx_std_cons_idx = 0; |
7098 | tpr->rx_std_prod_idx = 0; | |
7099 | tpr->rx_jmb_cons_idx = 0; | |
7100 | tpr->rx_jmb_prod_idx = 0; | |
7101 | ||
8fea32b9 | 7102 | if (tpr != &tp->napi[0].prodring) { |
2c49a44d MC |
7103 | memset(&tpr->rx_std_buffers[0], 0, |
7104 | TG3_RX_STD_BUFF_RING_SIZE(tp)); | |
48035728 | 7105 | if (tpr->rx_jmb_buffers) |
2b2cdb65 | 7106 | memset(&tpr->rx_jmb_buffers[0], 0, |
2c49a44d | 7107 | TG3_RX_JMB_BUFF_RING_SIZE(tp)); |
2b2cdb65 MC |
7108 | goto done; |
7109 | } | |
7110 | ||
1da177e4 | 7111 | /* Zero out all descriptors. */ |
2c49a44d | 7112 | memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); |
1da177e4 | 7113 | |
287be12e | 7114 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; |
63c3a66f | 7115 | if (tg3_flag(tp, 5780_CLASS) && |
287be12e MC |
7116 | tp->dev->mtu > ETH_DATA_LEN) |
7117 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
7118 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
7e72aad4 | 7119 | |
1da177e4 LT |
7120 | /* Initialize invariants of the rings, we only set this |
7121 | * stuff once. This works because the card does not | |
7122 | * write into the rx buffer posting rings. | |
7123 | */ | |
2c49a44d | 7124 | for (i = 0; i <= tp->rx_std_ring_mask; i++) { |
1da177e4 LT |
7125 | struct tg3_rx_buffer_desc *rxd; |
7126 | ||
21f581a5 | 7127 | rxd = &tpr->rx_std[i]; |
287be12e | 7128 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; |
1da177e4 LT |
7129 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); |
7130 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
7131 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
7132 | } | |
7133 | ||
1da177e4 LT |
7134 | /* Now allocate fresh SKBs for each rx ring. */ |
7135 | for (i = 0; i < tp->rx_pending; i++) { | |
86b21e59 | 7136 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) { |
5129c3a3 MC |
7137 | netdev_warn(tp->dev, |
7138 | "Using a smaller RX standard ring. Only " | |
7139 | "%d out of %d buffers were allocated " | |
7140 | "successfully\n", i, tp->rx_pending); | |
32d8c572 | 7141 | if (i == 0) |
cf7a7298 | 7142 | goto initfail; |
32d8c572 | 7143 | tp->rx_pending = i; |
1da177e4 | 7144 | break; |
32d8c572 | 7145 | } |
1da177e4 LT |
7146 | } |
7147 | ||
63c3a66f | 7148 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
cf7a7298 MC |
7149 | goto done; |
7150 | ||
2c49a44d | 7151 | memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); |
cf7a7298 | 7152 | |
63c3a66f | 7153 | if (!tg3_flag(tp, JUMBO_RING_ENABLE)) |
0d86df80 | 7154 | goto done; |
cf7a7298 | 7155 | |
2c49a44d | 7156 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { |
0d86df80 MC |
7157 | struct tg3_rx_buffer_desc *rxd; |
7158 | ||
7159 | rxd = &tpr->rx_jmb[i].std; | |
7160 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; | |
7161 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
7162 | RXD_FLAG_JUMBO; | |
7163 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
7164 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
7165 | } | |
7166 | ||
7167 | for (i = 0; i < tp->rx_jumbo_pending; i++) { | |
7168 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) { | |
5129c3a3 MC |
7169 | netdev_warn(tp->dev, |
7170 | "Using a smaller RX jumbo ring. Only %d " | |
7171 | "out of %d buffers were allocated " | |
7172 | "successfully\n", i, tp->rx_jumbo_pending); | |
0d86df80 MC |
7173 | if (i == 0) |
7174 | goto initfail; | |
7175 | tp->rx_jumbo_pending = i; | |
7176 | break; | |
1da177e4 LT |
7177 | } |
7178 | } | |
cf7a7298 MC |
7179 | |
7180 | done: | |
32d8c572 | 7181 | return 0; |
cf7a7298 MC |
7182 | |
7183 | initfail: | |
21f581a5 | 7184 | tg3_rx_prodring_free(tp, tpr); |
cf7a7298 | 7185 | return -ENOMEM; |
1da177e4 LT |
7186 | } |
7187 | ||
21f581a5 MC |
7188 | static void tg3_rx_prodring_fini(struct tg3 *tp, |
7189 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 7190 | { |
21f581a5 MC |
7191 | kfree(tpr->rx_std_buffers); |
7192 | tpr->rx_std_buffers = NULL; | |
7193 | kfree(tpr->rx_jmb_buffers); | |
7194 | tpr->rx_jmb_buffers = NULL; | |
7195 | if (tpr->rx_std) { | |
4bae65c8 MC |
7196 | dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), |
7197 | tpr->rx_std, tpr->rx_std_mapping); | |
21f581a5 | 7198 | tpr->rx_std = NULL; |
1da177e4 | 7199 | } |
21f581a5 | 7200 | if (tpr->rx_jmb) { |
4bae65c8 MC |
7201 | dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), |
7202 | tpr->rx_jmb, tpr->rx_jmb_mapping); | |
21f581a5 | 7203 | tpr->rx_jmb = NULL; |
1da177e4 | 7204 | } |
cf7a7298 MC |
7205 | } |
7206 | ||
21f581a5 MC |
7207 | static int tg3_rx_prodring_init(struct tg3 *tp, |
7208 | struct tg3_rx_prodring_set *tpr) | |
cf7a7298 | 7209 | { |
2c49a44d MC |
7210 | tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), |
7211 | GFP_KERNEL); | |
21f581a5 | 7212 | if (!tpr->rx_std_buffers) |
cf7a7298 MC |
7213 | return -ENOMEM; |
7214 | ||
4bae65c8 MC |
7215 | tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, |
7216 | TG3_RX_STD_RING_BYTES(tp), | |
7217 | &tpr->rx_std_mapping, | |
7218 | GFP_KERNEL); | |
21f581a5 | 7219 | if (!tpr->rx_std) |
cf7a7298 MC |
7220 | goto err_out; |
7221 | ||
63c3a66f | 7222 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
2c49a44d | 7223 | tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), |
21f581a5 MC |
7224 | GFP_KERNEL); |
7225 | if (!tpr->rx_jmb_buffers) | |
cf7a7298 MC |
7226 | goto err_out; |
7227 | ||
4bae65c8 MC |
7228 | tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, |
7229 | TG3_RX_JMB_RING_BYTES(tp), | |
7230 | &tpr->rx_jmb_mapping, | |
7231 | GFP_KERNEL); | |
21f581a5 | 7232 | if (!tpr->rx_jmb) |
cf7a7298 MC |
7233 | goto err_out; |
7234 | } | |
7235 | ||
7236 | return 0; | |
7237 | ||
7238 | err_out: | |
21f581a5 | 7239 | tg3_rx_prodring_fini(tp, tpr); |
cf7a7298 MC |
7240 | return -ENOMEM; |
7241 | } | |
7242 | ||
7243 | /* Free up pending packets in all rx/tx rings. | |
7244 | * | |
7245 | * The chip has been shut down and the driver detached from | |
7246 | * the networking, so no interrupts or new tx packets will | |
7247 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
7248 | * in an interrupt context and thus may sleep. | |
7249 | */ | |
7250 | static void tg3_free_rings(struct tg3 *tp) | |
7251 | { | |
f77a6a8e | 7252 | int i, j; |
cf7a7298 | 7253 | |
f77a6a8e MC |
7254 | for (j = 0; j < tp->irq_cnt; j++) { |
7255 | struct tg3_napi *tnapi = &tp->napi[j]; | |
cf7a7298 | 7256 | |
8fea32b9 | 7257 | tg3_rx_prodring_free(tp, &tnapi->prodring); |
b28f6428 | 7258 | |
0c1d0e2b MC |
7259 | if (!tnapi->tx_buffers) |
7260 | continue; | |
7261 | ||
0d681b27 MC |
7262 | for (i = 0; i < TG3_TX_RING_SIZE; i++) { |
7263 | struct sk_buff *skb = tnapi->tx_buffers[i].skb; | |
cf7a7298 | 7264 | |
0d681b27 | 7265 | if (!skb) |
f77a6a8e | 7266 | continue; |
cf7a7298 | 7267 | |
ba1142e4 MC |
7268 | tg3_tx_skb_unmap(tnapi, i, |
7269 | skb_shinfo(skb)->nr_frags - 1); | |
f77a6a8e MC |
7270 | |
7271 | dev_kfree_skb_any(skb); | |
7272 | } | |
2b2cdb65 | 7273 | } |
cf7a7298 MC |
7274 | } |
7275 | ||
7276 | /* Initialize tx/rx rings for packet processing. | |
7277 | * | |
7278 | * The chip has been shut down and the driver detached from | |
7279 | * the networking, so no interrupts or new tx packets will | |
7280 | * end up in the driver. tp->{tx,}lock are held and thus | |
7281 | * we may not sleep. | |
7282 | */ | |
7283 | static int tg3_init_rings(struct tg3 *tp) | |
7284 | { | |
f77a6a8e | 7285 | int i; |
72334482 | 7286 | |
cf7a7298 MC |
7287 | /* Free up all the SKBs. */ |
7288 | tg3_free_rings(tp); | |
7289 | ||
f77a6a8e MC |
7290 | for (i = 0; i < tp->irq_cnt; i++) { |
7291 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7292 | ||
7293 | tnapi->last_tag = 0; | |
7294 | tnapi->last_irq_tag = 0; | |
7295 | tnapi->hw_status->status = 0; | |
7296 | tnapi->hw_status->status_tag = 0; | |
7297 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
cf7a7298 | 7298 | |
f77a6a8e MC |
7299 | tnapi->tx_prod = 0; |
7300 | tnapi->tx_cons = 0; | |
0c1d0e2b MC |
7301 | if (tnapi->tx_ring) |
7302 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); | |
f77a6a8e MC |
7303 | |
7304 | tnapi->rx_rcb_ptr = 0; | |
0c1d0e2b MC |
7305 | if (tnapi->rx_rcb) |
7306 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
2b2cdb65 | 7307 | |
8fea32b9 | 7308 | if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { |
e4af1af9 | 7309 | tg3_free_rings(tp); |
2b2cdb65 | 7310 | return -ENOMEM; |
e4af1af9 | 7311 | } |
f77a6a8e | 7312 | } |
72334482 | 7313 | |
2b2cdb65 | 7314 | return 0; |
cf7a7298 MC |
7315 | } |
7316 | ||
7317 | /* | |
7318 | * Must not be invoked with interrupt sources disabled and | |
7319 | * the hardware shutdown down. | |
7320 | */ | |
7321 | static void tg3_free_consistent(struct tg3 *tp) | |
7322 | { | |
f77a6a8e | 7323 | int i; |
898a56f8 | 7324 | |
f77a6a8e MC |
7325 | for (i = 0; i < tp->irq_cnt; i++) { |
7326 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7327 | ||
7328 | if (tnapi->tx_ring) { | |
4bae65c8 | 7329 | dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, |
f77a6a8e MC |
7330 | tnapi->tx_ring, tnapi->tx_desc_mapping); |
7331 | tnapi->tx_ring = NULL; | |
7332 | } | |
7333 | ||
7334 | kfree(tnapi->tx_buffers); | |
7335 | tnapi->tx_buffers = NULL; | |
7336 | ||
7337 | if (tnapi->rx_rcb) { | |
4bae65c8 MC |
7338 | dma_free_coherent(&tp->pdev->dev, |
7339 | TG3_RX_RCB_RING_BYTES(tp), | |
7340 | tnapi->rx_rcb, | |
7341 | tnapi->rx_rcb_mapping); | |
f77a6a8e MC |
7342 | tnapi->rx_rcb = NULL; |
7343 | } | |
7344 | ||
8fea32b9 MC |
7345 | tg3_rx_prodring_fini(tp, &tnapi->prodring); |
7346 | ||
f77a6a8e | 7347 | if (tnapi->hw_status) { |
4bae65c8 MC |
7348 | dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, |
7349 | tnapi->hw_status, | |
7350 | tnapi->status_mapping); | |
f77a6a8e MC |
7351 | tnapi->hw_status = NULL; |
7352 | } | |
1da177e4 | 7353 | } |
f77a6a8e | 7354 | |
1da177e4 | 7355 | if (tp->hw_stats) { |
4bae65c8 MC |
7356 | dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), |
7357 | tp->hw_stats, tp->stats_mapping); | |
1da177e4 LT |
7358 | tp->hw_stats = NULL; |
7359 | } | |
7360 | } | |
7361 | ||
7362 | /* | |
7363 | * Must not be invoked with interrupt sources disabled and | |
7364 | * the hardware shutdown down. Can sleep. | |
7365 | */ | |
7366 | static int tg3_alloc_consistent(struct tg3 *tp) | |
7367 | { | |
f77a6a8e | 7368 | int i; |
898a56f8 | 7369 | |
4bae65c8 MC |
7370 | tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, |
7371 | sizeof(struct tg3_hw_stats), | |
7372 | &tp->stats_mapping, | |
7373 | GFP_KERNEL); | |
f77a6a8e | 7374 | if (!tp->hw_stats) |
1da177e4 LT |
7375 | goto err_out; |
7376 | ||
f77a6a8e | 7377 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
1da177e4 | 7378 | |
f77a6a8e MC |
7379 | for (i = 0; i < tp->irq_cnt; i++) { |
7380 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8d9d7cfc | 7381 | struct tg3_hw_status *sblk; |
1da177e4 | 7382 | |
4bae65c8 MC |
7383 | tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, |
7384 | TG3_HW_STATUS_SIZE, | |
7385 | &tnapi->status_mapping, | |
7386 | GFP_KERNEL); | |
f77a6a8e MC |
7387 | if (!tnapi->hw_status) |
7388 | goto err_out; | |
898a56f8 | 7389 | |
f77a6a8e | 7390 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
8d9d7cfc MC |
7391 | sblk = tnapi->hw_status; |
7392 | ||
8fea32b9 MC |
7393 | if (tg3_rx_prodring_init(tp, &tnapi->prodring)) |
7394 | goto err_out; | |
7395 | ||
19cfaecc MC |
7396 | /* If multivector TSS is enabled, vector 0 does not handle |
7397 | * tx interrupts. Don't allocate any resources for it. | |
7398 | */ | |
63c3a66f JP |
7399 | if ((!i && !tg3_flag(tp, ENABLE_TSS)) || |
7400 | (i && tg3_flag(tp, ENABLE_TSS))) { | |
df8944cf MC |
7401 | tnapi->tx_buffers = kzalloc( |
7402 | sizeof(struct tg3_tx_ring_info) * | |
7403 | TG3_TX_RING_SIZE, GFP_KERNEL); | |
19cfaecc MC |
7404 | if (!tnapi->tx_buffers) |
7405 | goto err_out; | |
7406 | ||
4bae65c8 MC |
7407 | tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, |
7408 | TG3_TX_RING_BYTES, | |
7409 | &tnapi->tx_desc_mapping, | |
7410 | GFP_KERNEL); | |
19cfaecc MC |
7411 | if (!tnapi->tx_ring) |
7412 | goto err_out; | |
7413 | } | |
7414 | ||
8d9d7cfc MC |
7415 | /* |
7416 | * When RSS is enabled, the status block format changes | |
7417 | * slightly. The "rx_jumbo_consumer", "reserved", | |
7418 | * and "rx_mini_consumer" members get mapped to the | |
7419 | * other three rx return ring producer indexes. | |
7420 | */ | |
7421 | switch (i) { | |
7422 | default: | |
7423 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; | |
7424 | break; | |
7425 | case 2: | |
7426 | tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer; | |
7427 | break; | |
7428 | case 3: | |
7429 | tnapi->rx_rcb_prod_idx = &sblk->reserved; | |
7430 | break; | |
7431 | case 4: | |
7432 | tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer; | |
7433 | break; | |
7434 | } | |
72334482 | 7435 | |
0c1d0e2b MC |
7436 | /* |
7437 | * If multivector RSS is enabled, vector 0 does not handle | |
7438 | * rx or tx interrupts. Don't allocate any resources for it. | |
7439 | */ | |
63c3a66f | 7440 | if (!i && tg3_flag(tp, ENABLE_RSS)) |
0c1d0e2b MC |
7441 | continue; |
7442 | ||
4bae65c8 MC |
7443 | tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, |
7444 | TG3_RX_RCB_RING_BYTES(tp), | |
7445 | &tnapi->rx_rcb_mapping, | |
7446 | GFP_KERNEL); | |
f77a6a8e MC |
7447 | if (!tnapi->rx_rcb) |
7448 | goto err_out; | |
72334482 | 7449 | |
f77a6a8e | 7450 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); |
f77a6a8e | 7451 | } |
1da177e4 LT |
7452 | |
7453 | return 0; | |
7454 | ||
7455 | err_out: | |
7456 | tg3_free_consistent(tp); | |
7457 | return -ENOMEM; | |
7458 | } | |
7459 | ||
7460 | #define MAX_WAIT_CNT 1000 | |
7461 | ||
7462 | /* To stop a block, clear the enable bit and poll till it | |
7463 | * clears. tp->lock is held. | |
7464 | */ | |
b3b7d6be | 7465 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) |
1da177e4 LT |
7466 | { |
7467 | unsigned int i; | |
7468 | u32 val; | |
7469 | ||
63c3a66f | 7470 | if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
7471 | switch (ofs) { |
7472 | case RCVLSC_MODE: | |
7473 | case DMAC_MODE: | |
7474 | case MBFREE_MODE: | |
7475 | case BUFMGR_MODE: | |
7476 | case MEMARB_MODE: | |
7477 | /* We can't enable/disable these bits of the | |
7478 | * 5705/5750, just say success. | |
7479 | */ | |
7480 | return 0; | |
7481 | ||
7482 | default: | |
7483 | break; | |
855e1111 | 7484 | } |
1da177e4 LT |
7485 | } |
7486 | ||
7487 | val = tr32(ofs); | |
7488 | val &= ~enable_bit; | |
7489 | tw32_f(ofs, val); | |
7490 | ||
7491 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
7492 | udelay(100); | |
7493 | val = tr32(ofs); | |
7494 | if ((val & enable_bit) == 0) | |
7495 | break; | |
7496 | } | |
7497 | ||
b3b7d6be | 7498 | if (i == MAX_WAIT_CNT && !silent) { |
2445e461 MC |
7499 | dev_err(&tp->pdev->dev, |
7500 | "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", | |
7501 | ofs, enable_bit); | |
1da177e4 LT |
7502 | return -ENODEV; |
7503 | } | |
7504 | ||
7505 | return 0; | |
7506 | } | |
7507 | ||
7508 | /* tp->lock is held. */ | |
b3b7d6be | 7509 | static int tg3_abort_hw(struct tg3 *tp, int silent) |
1da177e4 LT |
7510 | { |
7511 | int i, err; | |
7512 | ||
7513 | tg3_disable_ints(tp); | |
7514 | ||
7515 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
7516 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
7517 | udelay(10); | |
7518 | ||
b3b7d6be DM |
7519 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); |
7520 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
7521 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
7522 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
7523 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
7524 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
7525 | ||
7526 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
7527 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
7528 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
7529 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
7530 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
7531 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
7532 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
1da177e4 LT |
7533 | |
7534 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
7535 | tw32_f(MAC_MODE, tp->mac_mode); | |
7536 | udelay(40); | |
7537 | ||
7538 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
7539 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
7540 | ||
7541 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
7542 | udelay(100); | |
7543 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
7544 | break; | |
7545 | } | |
7546 | if (i >= MAX_WAIT_CNT) { | |
ab96b241 MC |
7547 | dev_err(&tp->pdev->dev, |
7548 | "%s timed out, TX_MODE_ENABLE will not clear " | |
7549 | "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); | |
e6de8ad1 | 7550 | err |= -ENODEV; |
1da177e4 LT |
7551 | } |
7552 | ||
e6de8ad1 | 7553 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); |
b3b7d6be DM |
7554 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); |
7555 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
1da177e4 LT |
7556 | |
7557 | tw32(FTQ_RESET, 0xffffffff); | |
7558 | tw32(FTQ_RESET, 0x00000000); | |
7559 | ||
b3b7d6be DM |
7560 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); |
7561 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
1da177e4 | 7562 | |
f77a6a8e MC |
7563 | for (i = 0; i < tp->irq_cnt; i++) { |
7564 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7565 | if (tnapi->hw_status) | |
7566 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7567 | } | |
1da177e4 LT |
7568 | if (tp->hw_stats) |
7569 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
7570 | ||
1da177e4 LT |
7571 | return err; |
7572 | } | |
7573 | ||
ee6a99b5 MC |
7574 | /* Save PCI command register before chip reset */ |
7575 | static void tg3_save_pci_state(struct tg3 *tp) | |
7576 | { | |
8a6eac90 | 7577 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); |
ee6a99b5 MC |
7578 | } |
7579 | ||
7580 | /* Restore PCI state after chip reset */ | |
7581 | static void tg3_restore_pci_state(struct tg3 *tp) | |
7582 | { | |
7583 | u32 val; | |
7584 | ||
7585 | /* Re-enable indirect register accesses. */ | |
7586 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
7587 | tp->misc_host_ctrl); | |
7588 | ||
7589 | /* Set MAX PCI retry to zero. */ | |
7590 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
7591 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
63c3a66f | 7592 | tg3_flag(tp, PCIX_MODE)) |
ee6a99b5 | 7593 | val |= PCISTATE_RETRY_SAME_DMA; |
0d3031d9 | 7594 | /* Allow reads and writes to the APE register and memory space. */ |
63c3a66f | 7595 | if (tg3_flag(tp, ENABLE_APE)) |
0d3031d9 | 7596 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | |
f92d9dc1 MC |
7597 | PCISTATE_ALLOW_APE_SHMEM_WR | |
7598 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
ee6a99b5 MC |
7599 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); |
7600 | ||
8a6eac90 | 7601 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); |
ee6a99b5 | 7602 | |
fcb389df | 7603 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) { |
63c3a66f | 7604 | if (tg3_flag(tp, PCI_EXPRESS)) |
cf79003d | 7605 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); |
fcb389df MC |
7606 | else { |
7607 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
7608 | tp->pci_cacheline_sz); | |
7609 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
7610 | tp->pci_lat_timer); | |
7611 | } | |
114342f2 | 7612 | } |
5f5c51e3 | 7613 | |
ee6a99b5 | 7614 | /* Make sure PCI-X relaxed ordering bit is clear. */ |
63c3a66f | 7615 | if (tg3_flag(tp, PCIX_MODE)) { |
9974a356 MC |
7616 | u16 pcix_cmd; |
7617 | ||
7618 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7619 | &pcix_cmd); | |
7620 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
7621 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7622 | pcix_cmd); | |
7623 | } | |
ee6a99b5 | 7624 | |
63c3a66f | 7625 | if (tg3_flag(tp, 5780_CLASS)) { |
ee6a99b5 MC |
7626 | |
7627 | /* Chip reset on 5780 will reset MSI enable bit, | |
7628 | * so need to restore it. | |
7629 | */ | |
63c3a66f | 7630 | if (tg3_flag(tp, USING_MSI)) { |
ee6a99b5 MC |
7631 | u16 ctrl; |
7632 | ||
7633 | pci_read_config_word(tp->pdev, | |
7634 | tp->msi_cap + PCI_MSI_FLAGS, | |
7635 | &ctrl); | |
7636 | pci_write_config_word(tp->pdev, | |
7637 | tp->msi_cap + PCI_MSI_FLAGS, | |
7638 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
7639 | val = tr32(MSGINT_MODE); | |
7640 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
7641 | } | |
7642 | } | |
7643 | } | |
7644 | ||
1da177e4 LT |
7645 | /* tp->lock is held. */ |
7646 | static int tg3_chip_reset(struct tg3 *tp) | |
7647 | { | |
7648 | u32 val; | |
1ee582d8 | 7649 | void (*write_op)(struct tg3 *, u32, u32); |
4f125f42 | 7650 | int i, err; |
1da177e4 | 7651 | |
f49639e6 DM |
7652 | tg3_nvram_lock(tp); |
7653 | ||
77b483f1 MC |
7654 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); |
7655 | ||
f49639e6 DM |
7656 | /* No matching tg3_nvram_unlock() after this because |
7657 | * chip reset below will undo the nvram lock. | |
7658 | */ | |
7659 | tp->nvram_lock_cnt = 0; | |
1da177e4 | 7660 | |
ee6a99b5 MC |
7661 | /* GRC_MISC_CFG core clock reset will clear the memory |
7662 | * enable bit in PCI register 4 and the MSI enable bit | |
7663 | * on some chips, so we save relevant registers here. | |
7664 | */ | |
7665 | tg3_save_pci_state(tp); | |
7666 | ||
d9ab5ad1 | 7667 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
63c3a66f | 7668 | tg3_flag(tp, 5755_PLUS)) |
d9ab5ad1 MC |
7669 | tw32(GRC_FASTBOOT_PC, 0); |
7670 | ||
1da177e4 LT |
7671 | /* |
7672 | * We must avoid the readl() that normally takes place. | |
7673 | * It locks machines, causes machine checks, and other | |
7674 | * fun things. So, temporarily disable the 5701 | |
7675 | * hardware workaround, while we do the reset. | |
7676 | */ | |
1ee582d8 MC |
7677 | write_op = tp->write32; |
7678 | if (write_op == tg3_write_flush_reg32) | |
7679 | tp->write32 = tg3_write32; | |
1da177e4 | 7680 | |
d18edcb2 MC |
7681 | /* Prevent the irq handler from reading or writing PCI registers |
7682 | * during chip reset when the memory enable bit in the PCI command | |
7683 | * register may be cleared. The chip does not generate interrupt | |
7684 | * at this time, but the irq handler may still be called due to irq | |
7685 | * sharing or irqpoll. | |
7686 | */ | |
63c3a66f | 7687 | tg3_flag_set(tp, CHIP_RESETTING); |
f77a6a8e MC |
7688 | for (i = 0; i < tp->irq_cnt; i++) { |
7689 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7690 | if (tnapi->hw_status) { | |
7691 | tnapi->hw_status->status = 0; | |
7692 | tnapi->hw_status->status_tag = 0; | |
7693 | } | |
7694 | tnapi->last_tag = 0; | |
7695 | tnapi->last_irq_tag = 0; | |
b8fa2f3a | 7696 | } |
d18edcb2 | 7697 | smp_mb(); |
4f125f42 MC |
7698 | |
7699 | for (i = 0; i < tp->irq_cnt; i++) | |
7700 | synchronize_irq(tp->napi[i].irq_vec); | |
d18edcb2 | 7701 | |
255ca311 MC |
7702 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
7703 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
7704 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
7705 | } | |
7706 | ||
1da177e4 LT |
7707 | /* do the reset */ |
7708 | val = GRC_MISC_CFG_CORECLK_RESET; | |
7709 | ||
63c3a66f | 7710 | if (tg3_flag(tp, PCI_EXPRESS)) { |
88075d91 MC |
7711 | /* Force PCIe 1.0a mode */ |
7712 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
63c3a66f | 7713 | !tg3_flag(tp, 57765_PLUS) && |
88075d91 MC |
7714 | tr32(TG3_PCIE_PHY_TSTCTL) == |
7715 | (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) | |
7716 | tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); | |
7717 | ||
1da177e4 LT |
7718 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { |
7719 | tw32(GRC_MISC_CFG, (1 << 29)); | |
7720 | val |= (1 << 29); | |
7721 | } | |
7722 | } | |
7723 | ||
b5d3772c MC |
7724 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7725 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
7726 | tw32(GRC_VCPU_EXT_CTRL, | |
7727 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7728 | } | |
7729 | ||
f37500d3 | 7730 | /* Manage gphy power for all CPMU absent PCIe devices. */ |
63c3a66f | 7731 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) |
1da177e4 | 7732 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; |
f37500d3 | 7733 | |
1da177e4 LT |
7734 | tw32(GRC_MISC_CFG, val); |
7735 | ||
1ee582d8 MC |
7736 | /* restore 5701 hardware bug workaround write method */ |
7737 | tp->write32 = write_op; | |
1da177e4 LT |
7738 | |
7739 | /* Unfortunately, we have to delay before the PCI read back. | |
7740 | * Some 575X chips even will not respond to a PCI cfg access | |
7741 | * when the reset command is given to the chip. | |
7742 | * | |
7743 | * How do these hardware designers expect things to work | |
7744 | * properly if the PCI write is posted for a long period | |
7745 | * of time? It is always necessary to have some method by | |
7746 | * which a register read back can occur to push the write | |
7747 | * out which does the reset. | |
7748 | * | |
7749 | * For most tg3 variants the trick below was working. | |
7750 | * Ho hum... | |
7751 | */ | |
7752 | udelay(120); | |
7753 | ||
7754 | /* Flush PCI posted writes. The normal MMIO registers | |
7755 | * are inaccessible at this time so this is the only | |
7756 | * way to make this reliably (actually, this is no longer | |
7757 | * the case, see above). I tried to use indirect | |
7758 | * register read/write but this upset some 5701 variants. | |
7759 | */ | |
7760 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
7761 | ||
7762 | udelay(120); | |
7763 | ||
708ebb3a | 7764 | if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) { |
e7126997 MC |
7765 | u16 val16; |
7766 | ||
1da177e4 LT |
7767 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { |
7768 | int i; | |
7769 | u32 cfg_val; | |
7770 | ||
7771 | /* Wait for link training to complete. */ | |
7772 | for (i = 0; i < 5000; i++) | |
7773 | udelay(100); | |
7774 | ||
7775 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
7776 | pci_write_config_dword(tp->pdev, 0xc4, | |
7777 | cfg_val | (1 << 15)); | |
7778 | } | |
5e7dfd0f | 7779 | |
e7126997 MC |
7780 | /* Clear the "no snoop" and "relaxed ordering" bits. */ |
7781 | pci_read_config_word(tp->pdev, | |
708ebb3a | 7782 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL, |
e7126997 MC |
7783 | &val16); |
7784 | val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | | |
7785 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
7786 | /* | |
7787 | * Older PCIe devices only support the 128 byte | |
7788 | * MPS setting. Enforce the restriction. | |
5e7dfd0f | 7789 | */ |
63c3a66f | 7790 | if (!tg3_flag(tp, CPMU_PRESENT)) |
e7126997 | 7791 | val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; |
5e7dfd0f | 7792 | pci_write_config_word(tp->pdev, |
708ebb3a | 7793 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL, |
e7126997 | 7794 | val16); |
5e7dfd0f | 7795 | |
cf79003d | 7796 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); |
5e7dfd0f MC |
7797 | |
7798 | /* Clear error status */ | |
7799 | pci_write_config_word(tp->pdev, | |
708ebb3a | 7800 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA, |
5e7dfd0f MC |
7801 | PCI_EXP_DEVSTA_CED | |
7802 | PCI_EXP_DEVSTA_NFED | | |
7803 | PCI_EXP_DEVSTA_FED | | |
7804 | PCI_EXP_DEVSTA_URD); | |
1da177e4 LT |
7805 | } |
7806 | ||
ee6a99b5 | 7807 | tg3_restore_pci_state(tp); |
1da177e4 | 7808 | |
63c3a66f JP |
7809 | tg3_flag_clear(tp, CHIP_RESETTING); |
7810 | tg3_flag_clear(tp, ERROR_PROCESSED); | |
d18edcb2 | 7811 | |
ee6a99b5 | 7812 | val = 0; |
63c3a66f | 7813 | if (tg3_flag(tp, 5780_CLASS)) |
4cf78e4f | 7814 | val = tr32(MEMARB_MODE); |
ee6a99b5 | 7815 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
1da177e4 LT |
7816 | |
7817 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
7818 | tg3_stop_fw(tp); | |
7819 | tw32(0x5000, 0x400); | |
7820 | } | |
7821 | ||
7822 | tw32(GRC_MODE, tp->grc_mode); | |
7823 | ||
7824 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
ab0049b4 | 7825 | val = tr32(0xc4); |
1da177e4 LT |
7826 | |
7827 | tw32(0xc4, val | (1 << 15)); | |
7828 | } | |
7829 | ||
7830 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
7831 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
7832 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
7833 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
7834 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
7835 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
7836 | } | |
7837 | ||
f07e9af3 | 7838 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
9e975cc2 | 7839 | tp->mac_mode = MAC_MODE_PORT_MODE_TBI; |
d2394e6b | 7840 | val = tp->mac_mode; |
f07e9af3 | 7841 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
9e975cc2 | 7842 | tp->mac_mode = MAC_MODE_PORT_MODE_GMII; |
d2394e6b | 7843 | val = tp->mac_mode; |
1da177e4 | 7844 | } else |
d2394e6b MC |
7845 | val = 0; |
7846 | ||
7847 | tw32_f(MAC_MODE, val); | |
1da177e4 LT |
7848 | udelay(40); |
7849 | ||
77b483f1 MC |
7850 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); |
7851 | ||
7a6f4369 MC |
7852 | err = tg3_poll_fw(tp); |
7853 | if (err) | |
7854 | return err; | |
1da177e4 | 7855 | |
0a9140cf MC |
7856 | tg3_mdio_start(tp); |
7857 | ||
63c3a66f | 7858 | if (tg3_flag(tp, PCI_EXPRESS) && |
f6eb9b1f MC |
7859 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
7860 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
63c3a66f | 7861 | !tg3_flag(tp, 57765_PLUS)) { |
ab0049b4 | 7862 | val = tr32(0x7c00); |
1da177e4 LT |
7863 | |
7864 | tw32(0x7c00, val | (1 << 25)); | |
7865 | } | |
7866 | ||
d78b59f5 MC |
7867 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
7868 | val = tr32(TG3_CPMU_CLCK_ORIDE); | |
7869 | tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); | |
7870 | } | |
7871 | ||
1da177e4 | 7872 | /* Reprobe ASF enable state. */ |
63c3a66f JP |
7873 | tg3_flag_clear(tp, ENABLE_ASF); |
7874 | tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 LT |
7875 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
7876 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
7877 | u32 nic_cfg; | |
7878 | ||
7879 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
7880 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
63c3a66f | 7881 | tg3_flag_set(tp, ENABLE_ASF); |
4ba526ce | 7882 | tp->last_event_jiffies = jiffies; |
63c3a66f JP |
7883 | if (tg3_flag(tp, 5750_PLUS)) |
7884 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 LT |
7885 | } |
7886 | } | |
7887 | ||
7888 | return 0; | |
7889 | } | |
7890 | ||
1da177e4 | 7891 | /* tp->lock is held. */ |
944d980e | 7892 | static int tg3_halt(struct tg3 *tp, int kind, int silent) |
1da177e4 LT |
7893 | { |
7894 | int err; | |
7895 | ||
7896 | tg3_stop_fw(tp); | |
7897 | ||
944d980e | 7898 | tg3_write_sig_pre_reset(tp, kind); |
1da177e4 | 7899 | |
b3b7d6be | 7900 | tg3_abort_hw(tp, silent); |
1da177e4 LT |
7901 | err = tg3_chip_reset(tp); |
7902 | ||
daba2a63 MC |
7903 | __tg3_set_mac_addr(tp, 0); |
7904 | ||
944d980e MC |
7905 | tg3_write_sig_legacy(tp, kind); |
7906 | tg3_write_sig_post_reset(tp, kind); | |
1da177e4 LT |
7907 | |
7908 | if (err) | |
7909 | return err; | |
7910 | ||
7911 | return 0; | |
7912 | } | |
7913 | ||
1da177e4 LT |
7914 | static int tg3_set_mac_addr(struct net_device *dev, void *p) |
7915 | { | |
7916 | struct tg3 *tp = netdev_priv(dev); | |
7917 | struct sockaddr *addr = p; | |
986e0aeb | 7918 | int err = 0, skip_mac_1 = 0; |
1da177e4 | 7919 | |
f9804ddb MC |
7920 | if (!is_valid_ether_addr(addr->sa_data)) |
7921 | return -EINVAL; | |
7922 | ||
1da177e4 LT |
7923 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
7924 | ||
e75f7c90 MC |
7925 | if (!netif_running(dev)) |
7926 | return 0; | |
7927 | ||
63c3a66f | 7928 | if (tg3_flag(tp, ENABLE_ASF)) { |
986e0aeb | 7929 | u32 addr0_high, addr0_low, addr1_high, addr1_low; |
58712ef9 | 7930 | |
986e0aeb MC |
7931 | addr0_high = tr32(MAC_ADDR_0_HIGH); |
7932 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
7933 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
7934 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
7935 | ||
7936 | /* Skip MAC addr 1 if ASF is using it. */ | |
7937 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
7938 | !(addr1_high == 0 && addr1_low == 0)) | |
7939 | skip_mac_1 = 1; | |
58712ef9 | 7940 | } |
986e0aeb MC |
7941 | spin_lock_bh(&tp->lock); |
7942 | __tg3_set_mac_addr(tp, skip_mac_1); | |
7943 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 7944 | |
b9ec6c1b | 7945 | return err; |
1da177e4 LT |
7946 | } |
7947 | ||
7948 | /* tp->lock is held. */ | |
7949 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
7950 | dma_addr_t mapping, u32 maxlen_flags, | |
7951 | u32 nic_addr) | |
7952 | { | |
7953 | tg3_write_mem(tp, | |
7954 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
7955 | ((u64) mapping >> 32)); | |
7956 | tg3_write_mem(tp, | |
7957 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
7958 | ((u64) mapping & 0xffffffff)); | |
7959 | tg3_write_mem(tp, | |
7960 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
7961 | maxlen_flags); | |
7962 | ||
63c3a66f | 7963 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
7964 | tg3_write_mem(tp, |
7965 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
7966 | nic_addr); | |
7967 | } | |
7968 | ||
7969 | static void __tg3_set_rx_mode(struct net_device *); | |
d244c892 | 7970 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) |
15f9850d | 7971 | { |
b6080e12 MC |
7972 | int i; |
7973 | ||
63c3a66f | 7974 | if (!tg3_flag(tp, ENABLE_TSS)) { |
b6080e12 MC |
7975 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); |
7976 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
7977 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
b6080e12 MC |
7978 | } else { |
7979 | tw32(HOSTCC_TXCOL_TICKS, 0); | |
7980 | tw32(HOSTCC_TXMAX_FRAMES, 0); | |
7981 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | |
19cfaecc | 7982 | } |
b6080e12 | 7983 | |
63c3a66f | 7984 | if (!tg3_flag(tp, ENABLE_RSS)) { |
19cfaecc MC |
7985 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); |
7986 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
7987 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
7988 | } else { | |
b6080e12 MC |
7989 | tw32(HOSTCC_RXCOL_TICKS, 0); |
7990 | tw32(HOSTCC_RXMAX_FRAMES, 0); | |
7991 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); | |
15f9850d | 7992 | } |
b6080e12 | 7993 | |
63c3a66f | 7994 | if (!tg3_flag(tp, 5705_PLUS)) { |
15f9850d DM |
7995 | u32 val = ec->stats_block_coalesce_usecs; |
7996 | ||
b6080e12 MC |
7997 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); |
7998 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
7999 | ||
15f9850d DM |
8000 | if (!netif_carrier_ok(tp->dev)) |
8001 | val = 0; | |
8002 | ||
8003 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
8004 | } | |
b6080e12 MC |
8005 | |
8006 | for (i = 0; i < tp->irq_cnt - 1; i++) { | |
8007 | u32 reg; | |
8008 | ||
8009 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; | |
8010 | tw32(reg, ec->rx_coalesce_usecs); | |
b6080e12 MC |
8011 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; |
8012 | tw32(reg, ec->rx_max_coalesced_frames); | |
b6080e12 MC |
8013 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; |
8014 | tw32(reg, ec->rx_max_coalesced_frames_irq); | |
19cfaecc | 8015 | |
63c3a66f | 8016 | if (tg3_flag(tp, ENABLE_TSS)) { |
19cfaecc MC |
8017 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; |
8018 | tw32(reg, ec->tx_coalesce_usecs); | |
8019 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; | |
8020 | tw32(reg, ec->tx_max_coalesced_frames); | |
8021 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
8022 | tw32(reg, ec->tx_max_coalesced_frames_irq); | |
8023 | } | |
b6080e12 MC |
8024 | } |
8025 | ||
8026 | for (; i < tp->irq_max - 1; i++) { | |
8027 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); | |
b6080e12 | 8028 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); |
b6080e12 | 8029 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); |
19cfaecc | 8030 | |
63c3a66f | 8031 | if (tg3_flag(tp, ENABLE_TSS)) { |
19cfaecc MC |
8032 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); |
8033 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
8034 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
8035 | } | |
b6080e12 | 8036 | } |
15f9850d | 8037 | } |
1da177e4 | 8038 | |
2d31ecaf MC |
8039 | /* tp->lock is held. */ |
8040 | static void tg3_rings_reset(struct tg3 *tp) | |
8041 | { | |
8042 | int i; | |
f77a6a8e | 8043 | u32 stblk, txrcb, rxrcb, limit; |
2d31ecaf MC |
8044 | struct tg3_napi *tnapi = &tp->napi[0]; |
8045 | ||
8046 | /* Disable all transmit rings but the first. */ | |
63c3a66f | 8047 | if (!tg3_flag(tp, 5705_PLUS)) |
2d31ecaf | 8048 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; |
63c3a66f | 8049 | else if (tg3_flag(tp, 5717_PLUS)) |
3d37728b | 8050 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; |
b703df6f MC |
8051 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
8052 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; | |
2d31ecaf MC |
8053 | else |
8054 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
8055 | ||
8056 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
8057 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) | |
8058 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
8059 | BDINFO_FLAGS_DISABLED); | |
8060 | ||
8061 | ||
8062 | /* Disable all receive return rings but the first. */ | |
63c3a66f | 8063 | if (tg3_flag(tp, 5717_PLUS)) |
f6eb9b1f | 8064 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; |
63c3a66f | 8065 | else if (!tg3_flag(tp, 5705_PLUS)) |
2d31ecaf | 8066 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; |
b703df6f MC |
8067 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
8068 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
2d31ecaf MC |
8069 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; |
8070 | else | |
8071 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
8072 | ||
8073 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
8074 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) | |
8075 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
8076 | BDINFO_FLAGS_DISABLED); | |
8077 | ||
8078 | /* Disable interrupts */ | |
8079 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); | |
0e6cf6a9 MC |
8080 | tp->napi[0].chk_msi_cnt = 0; |
8081 | tp->napi[0].last_rx_cons = 0; | |
8082 | tp->napi[0].last_tx_cons = 0; | |
2d31ecaf MC |
8083 | |
8084 | /* Zero mailbox registers. */ | |
63c3a66f | 8085 | if (tg3_flag(tp, SUPPORT_MSIX)) { |
6fd45cb8 | 8086 | for (i = 1; i < tp->irq_max; i++) { |
f77a6a8e MC |
8087 | tp->napi[i].tx_prod = 0; |
8088 | tp->napi[i].tx_cons = 0; | |
63c3a66f | 8089 | if (tg3_flag(tp, ENABLE_TSS)) |
c2353a32 | 8090 | tw32_mailbox(tp->napi[i].prodmbox, 0); |
f77a6a8e MC |
8091 | tw32_rx_mbox(tp->napi[i].consmbox, 0); |
8092 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); | |
7f230735 | 8093 | tp->napi[i].chk_msi_cnt = 0; |
0e6cf6a9 MC |
8094 | tp->napi[i].last_rx_cons = 0; |
8095 | tp->napi[i].last_tx_cons = 0; | |
f77a6a8e | 8096 | } |
63c3a66f | 8097 | if (!tg3_flag(tp, ENABLE_TSS)) |
c2353a32 | 8098 | tw32_mailbox(tp->napi[0].prodmbox, 0); |
f77a6a8e MC |
8099 | } else { |
8100 | tp->napi[0].tx_prod = 0; | |
8101 | tp->napi[0].tx_cons = 0; | |
8102 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
8103 | tw32_rx_mbox(tp->napi[0].consmbox, 0); | |
8104 | } | |
2d31ecaf MC |
8105 | |
8106 | /* Make sure the NIC-based send BD rings are disabled. */ | |
63c3a66f | 8107 | if (!tg3_flag(tp, 5705_PLUS)) { |
2d31ecaf MC |
8108 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; |
8109 | for (i = 0; i < 16; i++) | |
8110 | tw32_tx_mbox(mbox + i * 8, 0); | |
8111 | } | |
8112 | ||
8113 | txrcb = NIC_SRAM_SEND_RCB; | |
8114 | rxrcb = NIC_SRAM_RCV_RET_RCB; | |
8115 | ||
8116 | /* Clear status block in ram. */ | |
8117 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
8118 | ||
8119 | /* Set status block DMA address */ | |
8120 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
8121 | ((u64) tnapi->status_mapping >> 32)); | |
8122 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8123 | ((u64) tnapi->status_mapping & 0xffffffff)); | |
8124 | ||
f77a6a8e MC |
8125 | if (tnapi->tx_ring) { |
8126 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
8127 | (TG3_TX_RING_SIZE << | |
8128 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
8129 | NIC_SRAM_TX_BUFFER_DESC); | |
8130 | txrcb += TG3_BDINFO_SIZE; | |
8131 | } | |
8132 | ||
8133 | if (tnapi->rx_rcb) { | |
8134 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 MC |
8135 | (tp->rx_ret_ring_mask + 1) << |
8136 | BDINFO_FLAGS_MAXLEN_SHIFT, 0); | |
f77a6a8e MC |
8137 | rxrcb += TG3_BDINFO_SIZE; |
8138 | } | |
8139 | ||
8140 | stblk = HOSTCC_STATBLCK_RING1; | |
2d31ecaf | 8141 | |
f77a6a8e MC |
8142 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { |
8143 | u64 mapping = (u64)tnapi->status_mapping; | |
8144 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); | |
8145 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); | |
8146 | ||
8147 | /* Clear status block in ram. */ | |
8148 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
8149 | ||
19cfaecc MC |
8150 | if (tnapi->tx_ring) { |
8151 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
8152 | (TG3_TX_RING_SIZE << | |
8153 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
8154 | NIC_SRAM_TX_BUFFER_DESC); | |
8155 | txrcb += TG3_BDINFO_SIZE; | |
8156 | } | |
f77a6a8e MC |
8157 | |
8158 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 | 8159 | ((tp->rx_ret_ring_mask + 1) << |
f77a6a8e MC |
8160 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); |
8161 | ||
8162 | stblk += 8; | |
f77a6a8e MC |
8163 | rxrcb += TG3_BDINFO_SIZE; |
8164 | } | |
2d31ecaf MC |
8165 | } |
8166 | ||
eb07a940 MC |
8167 | static void tg3_setup_rxbd_thresholds(struct tg3 *tp) |
8168 | { | |
8169 | u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh; | |
8170 | ||
63c3a66f JP |
8171 | if (!tg3_flag(tp, 5750_PLUS) || |
8172 | tg3_flag(tp, 5780_CLASS) || | |
eb07a940 MC |
8173 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
8174 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
8175 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700; | |
8176 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
8177 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) | |
8178 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755; | |
8179 | else | |
8180 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906; | |
8181 | ||
8182 | nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); | |
8183 | host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); | |
8184 | ||
8185 | val = min(nic_rep_thresh, host_rep_thresh); | |
8186 | tw32(RCVBDI_STD_THRESH, val); | |
8187 | ||
63c3a66f | 8188 | if (tg3_flag(tp, 57765_PLUS)) |
eb07a940 MC |
8189 | tw32(STD_REPLENISH_LWM, bdcache_maxcnt); |
8190 | ||
63c3a66f | 8191 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
eb07a940 MC |
8192 | return; |
8193 | ||
63c3a66f | 8194 | if (!tg3_flag(tp, 5705_PLUS)) |
eb07a940 MC |
8195 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700; |
8196 | else | |
8197 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717; | |
8198 | ||
8199 | host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); | |
8200 | ||
8201 | val = min(bdcache_maxcnt / 2, host_rep_thresh); | |
8202 | tw32(RCVBDI_JUMBO_THRESH, val); | |
8203 | ||
63c3a66f | 8204 | if (tg3_flag(tp, 57765_PLUS)) |
eb07a940 MC |
8205 | tw32(JMB_REPLENISH_LWM, bdcache_maxcnt); |
8206 | } | |
8207 | ||
1da177e4 | 8208 | /* tp->lock is held. */ |
8e7a22e3 | 8209 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) |
1da177e4 LT |
8210 | { |
8211 | u32 val, rdmac_mode; | |
8212 | int i, err, limit; | |
8fea32b9 | 8213 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
1da177e4 LT |
8214 | |
8215 | tg3_disable_ints(tp); | |
8216 | ||
8217 | tg3_stop_fw(tp); | |
8218 | ||
8219 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
8220 | ||
63c3a66f | 8221 | if (tg3_flag(tp, INIT_COMPLETE)) |
e6de8ad1 | 8222 | tg3_abort_hw(tp, 1); |
1da177e4 | 8223 | |
699c0193 MC |
8224 | /* Enable MAC control of LPI */ |
8225 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { | |
8226 | tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, | |
8227 | TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | | |
8228 | TG3_CPMU_EEE_LNKIDL_UART_IDL); | |
8229 | ||
8230 | tw32_f(TG3_CPMU_EEE_CTRL, | |
8231 | TG3_CPMU_EEE_CTRL_EXIT_20_1_US); | |
8232 | ||
a386b901 MC |
8233 | val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET | |
8234 | TG3_CPMU_EEEMD_LPI_IN_TX | | |
8235 | TG3_CPMU_EEEMD_LPI_IN_RX | | |
8236 | TG3_CPMU_EEEMD_EEE_ENABLE; | |
8237 | ||
8238 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
8239 | val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; | |
8240 | ||
63c3a66f | 8241 | if (tg3_flag(tp, ENABLE_APE)) |
a386b901 MC |
8242 | val |= TG3_CPMU_EEEMD_APE_TX_DET_EN; |
8243 | ||
8244 | tw32_f(TG3_CPMU_EEE_MODE, val); | |
8245 | ||
8246 | tw32_f(TG3_CPMU_EEE_DBTMR1, | |
8247 | TG3_CPMU_DBTMR1_PCIEXIT_2047US | | |
8248 | TG3_CPMU_DBTMR1_LNKIDLE_2047US); | |
8249 | ||
8250 | tw32_f(TG3_CPMU_EEE_DBTMR2, | |
d7f2ab20 | 8251 | TG3_CPMU_DBTMR2_APE_TX_2047US | |
a386b901 | 8252 | TG3_CPMU_DBTMR2_TXIDXEQ_2047US); |
699c0193 MC |
8253 | } |
8254 | ||
603f1173 | 8255 | if (reset_phy) |
d4d2c558 MC |
8256 | tg3_phy_reset(tp); |
8257 | ||
1da177e4 LT |
8258 | err = tg3_chip_reset(tp); |
8259 | if (err) | |
8260 | return err; | |
8261 | ||
8262 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
8263 | ||
bcb37f6c | 8264 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
d30cdd28 MC |
8265 | val = tr32(TG3_CPMU_CTRL); |
8266 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
8267 | tw32(TG3_CPMU_CTRL, val); | |
9acb961e MC |
8268 | |
8269 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
8270 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8271 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8272 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
8273 | ||
8274 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
8275 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
8276 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
8277 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
8278 | ||
8279 | val = tr32(TG3_CPMU_HST_ACC); | |
8280 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
8281 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
8282 | tw32(TG3_CPMU_HST_ACC, val); | |
d30cdd28 MC |
8283 | } |
8284 | ||
33466d93 MC |
8285 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
8286 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
8287 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
8288 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
8289 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
521e6b90 MC |
8290 | |
8291 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
8292 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
8293 | ||
8294 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
33466d93 | 8295 | |
f40386c8 MC |
8296 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
8297 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
255ca311 MC |
8298 | } |
8299 | ||
63c3a66f | 8300 | if (tg3_flag(tp, L1PLLPD_EN)) { |
614b0590 MC |
8301 | u32 grc_mode = tr32(GRC_MODE); |
8302 | ||
8303 | /* Access the lower 1K of PL PCIE block registers. */ | |
8304 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8305 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
8306 | ||
8307 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); | |
8308 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, | |
8309 | val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); | |
8310 | ||
8311 | tw32(GRC_MODE, grc_mode); | |
8312 | } | |
8313 | ||
5093eedc MC |
8314 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { |
8315 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | |
8316 | u32 grc_mode = tr32(GRC_MODE); | |
cea46462 | 8317 | |
5093eedc MC |
8318 | /* Access the lower 1K of PL PCIE block registers. */ |
8319 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8320 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
cea46462 | 8321 | |
5093eedc MC |
8322 | val = tr32(TG3_PCIE_TLDLPL_PORT + |
8323 | TG3_PCIE_PL_LO_PHYCTL5); | |
8324 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, | |
8325 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); | |
cea46462 | 8326 | |
5093eedc MC |
8327 | tw32(GRC_MODE, grc_mode); |
8328 | } | |
a977dbe8 | 8329 | |
1ff30a59 MC |
8330 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) { |
8331 | u32 grc_mode = tr32(GRC_MODE); | |
8332 | ||
8333 | /* Access the lower 1K of DL PCIE block registers. */ | |
8334 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8335 | tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL); | |
8336 | ||
8337 | val = tr32(TG3_PCIE_TLDLPL_PORT + | |
8338 | TG3_PCIE_DL_LO_FTSMAX); | |
8339 | val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK; | |
8340 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, | |
8341 | val | TG3_PCIE_DL_LO_FTSMAX_VAL); | |
8342 | ||
8343 | tw32(GRC_MODE, grc_mode); | |
8344 | } | |
8345 | ||
a977dbe8 MC |
8346 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); |
8347 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8348 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8349 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
cea46462 MC |
8350 | } |
8351 | ||
1da177e4 LT |
8352 | /* This works around an issue with Athlon chipsets on |
8353 | * B3 tigon3 silicon. This bit has no effect on any | |
8354 | * other revision. But do not set this on PCI Express | |
795d01c5 | 8355 | * chips and don't even touch the clocks if the CPMU is present. |
1da177e4 | 8356 | */ |
63c3a66f JP |
8357 | if (!tg3_flag(tp, CPMU_PRESENT)) { |
8358 | if (!tg3_flag(tp, PCI_EXPRESS)) | |
795d01c5 MC |
8359 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; |
8360 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
8361 | } | |
1da177e4 LT |
8362 | |
8363 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
63c3a66f | 8364 | tg3_flag(tp, PCIX_MODE)) { |
1da177e4 LT |
8365 | val = tr32(TG3PCI_PCISTATE); |
8366 | val |= PCISTATE_RETRY_SAME_DMA; | |
8367 | tw32(TG3PCI_PCISTATE, val); | |
8368 | } | |
8369 | ||
63c3a66f | 8370 | if (tg3_flag(tp, ENABLE_APE)) { |
0d3031d9 MC |
8371 | /* Allow reads and writes to the |
8372 | * APE register and memory space. | |
8373 | */ | |
8374 | val = tr32(TG3PCI_PCISTATE); | |
8375 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
8376 | PCISTATE_ALLOW_APE_SHMEM_WR | |
8377 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
8378 | tw32(TG3PCI_PCISTATE, val); |
8379 | } | |
8380 | ||
1da177e4 LT |
8381 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { |
8382 | /* Enable some hw fixes. */ | |
8383 | val = tr32(TG3PCI_MSI_DATA); | |
8384 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
8385 | tw32(TG3PCI_MSI_DATA, val); | |
8386 | } | |
8387 | ||
8388 | /* Descriptor ring init may make accesses to the | |
8389 | * NIC SRAM area to setup the TX descriptors, so we | |
8390 | * can only do this after the hardware has been | |
8391 | * successfully reset. | |
8392 | */ | |
32d8c572 MC |
8393 | err = tg3_init_rings(tp); |
8394 | if (err) | |
8395 | return err; | |
1da177e4 | 8396 | |
63c3a66f | 8397 | if (tg3_flag(tp, 57765_PLUS)) { |
cbf9ca6c MC |
8398 | val = tr32(TG3PCI_DMA_RW_CTRL) & |
8399 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
1a319025 MC |
8400 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) |
8401 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; | |
0aebff48 MC |
8402 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 && |
8403 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
8404 | val |= DMA_RWCTRL_TAGGED_STAT_WA; | |
cbf9ca6c MC |
8405 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); |
8406 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | |
8407 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | |
d30cdd28 MC |
8408 | /* This value is determined during the probe time DMA |
8409 | * engine test, tg3_test_dma. | |
8410 | */ | |
8411 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
8412 | } | |
1da177e4 LT |
8413 | |
8414 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
8415 | GRC_MODE_4X_NIC_SEND_RINGS | | |
8416 | GRC_MODE_NO_TX_PHDR_CSUM | | |
8417 | GRC_MODE_NO_RX_PHDR_CSUM); | |
8418 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
d2d746f8 MC |
8419 | |
8420 | /* Pseudo-header checksum is done by hardware logic and not | |
8421 | * the offload processers, so make the chip do the pseudo- | |
8422 | * header checksums on receive. For transmit it is more | |
8423 | * convenient to do the pseudo-header checksum in software | |
8424 | * as Linux does that on transmit for us in all cases. | |
8425 | */ | |
8426 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
1da177e4 LT |
8427 | |
8428 | tw32(GRC_MODE, | |
8429 | tp->grc_mode | | |
8430 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
8431 | ||
8432 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
8433 | val = tr32(GRC_MISC_CFG); | |
8434 | val &= ~0xff; | |
8435 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
8436 | tw32(GRC_MISC_CFG, val); | |
8437 | ||
8438 | /* Initialize MBUF/DESC pool. */ | |
63c3a66f | 8439 | if (tg3_flag(tp, 5750_PLUS)) { |
1da177e4 LT |
8440 | /* Do nothing. */ |
8441 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
8442 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
8443 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
8444 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
8445 | else | |
8446 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
8447 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
8448 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
63c3a66f | 8449 | } else if (tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8450 | int fw_len; |
8451 | ||
077f849d | 8452 | fw_len = tp->fw_len; |
1da177e4 LT |
8453 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); |
8454 | tw32(BUFMGR_MB_POOL_ADDR, | |
8455 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
8456 | tw32(BUFMGR_MB_POOL_SIZE, | |
8457 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
8458 | } | |
1da177e4 | 8459 | |
0f893dc6 | 8460 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
1da177e4 LT |
8461 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
8462 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
8463 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8464 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
8465 | tw32(BUFMGR_MB_HIGH_WATER, | |
8466 | tp->bufmgr_config.mbuf_high_water); | |
8467 | } else { | |
8468 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
8469 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
8470 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8471 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
8472 | tw32(BUFMGR_MB_HIGH_WATER, | |
8473 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
8474 | } | |
8475 | tw32(BUFMGR_DMA_LOW_WATER, | |
8476 | tp->bufmgr_config.dma_low_water); | |
8477 | tw32(BUFMGR_DMA_HIGH_WATER, | |
8478 | tp->bufmgr_config.dma_high_water); | |
8479 | ||
d309a46e MC |
8480 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; |
8481 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
8482 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; | |
4d958473 MC |
8483 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
8484 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
8485 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) | |
8486 | val |= BUFMGR_MODE_MBLOW_ATTN_ENAB; | |
d309a46e | 8487 | tw32(BUFMGR_MODE, val); |
1da177e4 LT |
8488 | for (i = 0; i < 2000; i++) { |
8489 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
8490 | break; | |
8491 | udelay(10); | |
8492 | } | |
8493 | if (i >= 2000) { | |
05dbe005 | 8494 | netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); |
1da177e4 LT |
8495 | return -ENODEV; |
8496 | } | |
8497 | ||
eb07a940 MC |
8498 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) |
8499 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
b5d3772c | 8500 | |
eb07a940 | 8501 | tg3_setup_rxbd_thresholds(tp); |
1da177e4 LT |
8502 | |
8503 | /* Initialize TG3_BDINFO's at: | |
8504 | * RCVDBDI_STD_BD: standard eth size rx ring | |
8505 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
8506 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
8507 | * | |
8508 | * like so: | |
8509 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
8510 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
8511 | * ring attribute flags | |
8512 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
8513 | * | |
8514 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
8515 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
8516 | * | |
8517 | * The size of each ring is fixed in the firmware, but the location is | |
8518 | * configurable. | |
8519 | */ | |
8520 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
21f581a5 | 8521 | ((u64) tpr->rx_std_mapping >> 32)); |
1da177e4 | 8522 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8523 | ((u64) tpr->rx_std_mapping & 0xffffffff)); |
63c3a66f | 8524 | if (!tg3_flag(tp, 5717_PLUS)) |
87668d35 MC |
8525 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, |
8526 | NIC_SRAM_RX_BUFFER_DESC); | |
1da177e4 | 8527 | |
fdb72b38 | 8528 | /* Disable the mini ring */ |
63c3a66f | 8529 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
8530 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, |
8531 | BDINFO_FLAGS_DISABLED); | |
8532 | ||
fdb72b38 MC |
8533 | /* Program the jumbo buffer descriptor ring control |
8534 | * blocks on those devices that have them. | |
8535 | */ | |
a0512944 | 8536 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || |
63c3a66f | 8537 | (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { |
1da177e4 | 8538 | |
63c3a66f | 8539 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) { |
1da177e4 | 8540 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
21f581a5 | 8541 | ((u64) tpr->rx_jmb_mapping >> 32)); |
1da177e4 | 8542 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8543 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
de9f5230 MC |
8544 | val = TG3_RX_JMB_RING_SIZE(tp) << |
8545 | BDINFO_FLAGS_MAXLEN_SHIFT; | |
1da177e4 | 8546 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
de9f5230 | 8547 | val | BDINFO_FLAGS_USE_EXT_RECV); |
63c3a66f | 8548 | if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || |
a50d0796 | 8549 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
87668d35 MC |
8550 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
8551 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
1da177e4 LT |
8552 | } else { |
8553 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
8554 | BDINFO_FLAGS_DISABLED); | |
8555 | } | |
8556 | ||
63c3a66f | 8557 | if (tg3_flag(tp, 57765_PLUS)) { |
7cb32cf2 | 8558 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
de9f5230 | 8559 | val = TG3_RX_STD_MAX_SIZE_5700; |
7cb32cf2 | 8560 | else |
de9f5230 | 8561 | val = TG3_RX_STD_MAX_SIZE_5717; |
7cb32cf2 MC |
8562 | val <<= BDINFO_FLAGS_MAXLEN_SHIFT; |
8563 | val |= (TG3_RX_STD_DMA_SZ << 2); | |
8564 | } else | |
04380d40 | 8565 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 | 8566 | } else |
de9f5230 | 8567 | val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 MC |
8568 | |
8569 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
1da177e4 | 8570 | |
411da640 | 8571 | tpr->rx_std_prod_idx = tp->rx_pending; |
66711e66 | 8572 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); |
1da177e4 | 8573 | |
63c3a66f JP |
8574 | tpr->rx_jmb_prod_idx = |
8575 | tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; | |
66711e66 | 8576 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); |
1da177e4 | 8577 | |
2d31ecaf MC |
8578 | tg3_rings_reset(tp); |
8579 | ||
1da177e4 | 8580 | /* Initialize MAC address and backoff seed. */ |
986e0aeb | 8581 | __tg3_set_mac_addr(tp, 0); |
1da177e4 LT |
8582 | |
8583 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
f7b493e0 MC |
8584 | tw32(MAC_RX_MTU_SIZE, |
8585 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
1da177e4 LT |
8586 | |
8587 | /* The slot time is changed by tg3_setup_phy if we | |
8588 | * run at gigabit with half duplex. | |
8589 | */ | |
f2096f94 MC |
8590 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
8591 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
8592 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT); | |
8593 | ||
8594 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
8595 | val |= tr32(MAC_TX_LENGTHS) & | |
8596 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
8597 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
8598 | ||
8599 | tw32(MAC_TX_LENGTHS, val); | |
1da177e4 LT |
8600 | |
8601 | /* Receive rules. */ | |
8602 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
8603 | tw32(RCVLPC_CONFIG, 0x0181); | |
8604 | ||
8605 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
8606 | * the RCVLPC_STATE_ENABLE mask. | |
8607 | */ | |
8608 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
8609 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
8610 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
8611 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
8612 | RDMAC_MODE_LNGREAD_ENAB); | |
85e94ced | 8613 | |
deabaac8 | 8614 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
0339e4e3 MC |
8615 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; |
8616 | ||
57e6983c | 8617 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 MC |
8618 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
8619 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
d30cdd28 MC |
8620 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
8621 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
8622 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
8623 | ||
c5908939 MC |
8624 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8625 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 8626 | if (tg3_flag(tp, TSO_CAPABLE) && |
c13e3713 | 8627 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
8628 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
8629 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
63c3a66f | 8630 | !tg3_flag(tp, IS_5788)) { |
1da177e4 LT |
8631 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
8632 | } | |
8633 | } | |
8634 | ||
63c3a66f | 8635 | if (tg3_flag(tp, PCI_EXPRESS)) |
85e94ced MC |
8636 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
8637 | ||
63c3a66f JP |
8638 | if (tg3_flag(tp, HW_TSO_1) || |
8639 | tg3_flag(tp, HW_TSO_2) || | |
8640 | tg3_flag(tp, HW_TSO_3)) | |
027455ad MC |
8641 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
8642 | ||
108a6c16 | 8643 | if (tg3_flag(tp, 57765_PLUS) || |
e849cdc3 | 8644 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
027455ad MC |
8645 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
8646 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
1da177e4 | 8647 | |
f2096f94 MC |
8648 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
8649 | rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; | |
8650 | ||
41a8a7ee MC |
8651 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
8652 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
8653 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
8654 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
63c3a66f | 8655 | tg3_flag(tp, 57765_PLUS)) { |
41a8a7ee | 8656 | val = tr32(TG3_RDMA_RSRVCTRL_REG); |
d78b59f5 MC |
8657 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8658 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
b4495ed8 MC |
8659 | val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | |
8660 | TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK | | |
8661 | TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK); | |
8662 | val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B | | |
8663 | TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K | | |
8664 | TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K; | |
b75cc0e4 | 8665 | } |
41a8a7ee MC |
8666 | tw32(TG3_RDMA_RSRVCTRL_REG, |
8667 | val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); | |
8668 | } | |
8669 | ||
d78b59f5 MC |
8670 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8671 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
d309a46e MC |
8672 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); |
8673 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val | | |
8674 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K | | |
8675 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K); | |
8676 | } | |
8677 | ||
1da177e4 | 8678 | /* Receive/send statistics. */ |
63c3a66f | 8679 | if (tg3_flag(tp, 5750_PLUS)) { |
1661394e MC |
8680 | val = tr32(RCVLPC_STATS_ENABLE); |
8681 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
8682 | tw32(RCVLPC_STATS_ENABLE, val); | |
8683 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
63c3a66f | 8684 | tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8685 | val = tr32(RCVLPC_STATS_ENABLE); |
8686 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
8687 | tw32(RCVLPC_STATS_ENABLE, val); | |
8688 | } else { | |
8689 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
8690 | } | |
8691 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
8692 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
8693 | tw32(SNDDATAI_STATSCTRL, | |
8694 | (SNDDATAI_SCTRL_ENABLE | | |
8695 | SNDDATAI_SCTRL_FASTUPD)); | |
8696 | ||
8697 | /* Setup host coalescing engine. */ | |
8698 | tw32(HOSTCC_MODE, 0); | |
8699 | for (i = 0; i < 2000; i++) { | |
8700 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
8701 | break; | |
8702 | udelay(10); | |
8703 | } | |
8704 | ||
d244c892 | 8705 | __tg3_set_coalesce(tp, &tp->coal); |
1da177e4 | 8706 | |
63c3a66f | 8707 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
8708 | /* Status/statistics block address. See tg3_timer, |
8709 | * the tg3_periodic_fetch_stats call there, and | |
8710 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
8711 | */ | |
1da177e4 LT |
8712 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
8713 | ((u64) tp->stats_mapping >> 32)); | |
8714 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8715 | ((u64) tp->stats_mapping & 0xffffffff)); | |
8716 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
2d31ecaf | 8717 | |
1da177e4 | 8718 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); |
2d31ecaf MC |
8719 | |
8720 | /* Clear statistics and status block memory areas */ | |
8721 | for (i = NIC_SRAM_STATS_BLK; | |
8722 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
8723 | i += sizeof(u32)) { | |
8724 | tg3_write_mem(tp, i, 0); | |
8725 | udelay(40); | |
8726 | } | |
1da177e4 LT |
8727 | } |
8728 | ||
8729 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
8730 | ||
8731 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
8732 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
63c3a66f | 8733 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
8734 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); |
8735 | ||
f07e9af3 MC |
8736 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
8737 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
c94e3941 MC |
8738 | /* reset to prevent losing 1st rx packet intermittently */ |
8739 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
8740 | udelay(10); | |
8741 | } | |
8742 | ||
3bda1258 | 8743 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | |
9e975cc2 MC |
8744 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | |
8745 | MAC_MODE_FHDE_ENABLE; | |
8746 | if (tg3_flag(tp, ENABLE_APE)) | |
8747 | tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
63c3a66f | 8748 | if (!tg3_flag(tp, 5705_PLUS) && |
f07e9af3 | 8749 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
e8f3f6ca MC |
8750 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
8751 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
8752 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
8753 | udelay(40); | |
8754 | ||
314fba34 | 8755 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
63c3a66f | 8756 | * If TG3_FLAG_IS_NIC is zero, we should read the |
314fba34 MC |
8757 | * register to preserve the GPIO settings for LOMs. The GPIOs, |
8758 | * whether used as inputs or outputs, are set by boot code after | |
8759 | * reset. | |
8760 | */ | |
63c3a66f | 8761 | if (!tg3_flag(tp, IS_NIC)) { |
314fba34 MC |
8762 | u32 gpio_mask; |
8763 | ||
9d26e213 MC |
8764 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | |
8765 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
8766 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
3e7d83bc MC |
8767 | |
8768 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
8769 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
8770 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
8771 | ||
af36e6b6 MC |
8772 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
8773 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
8774 | ||
aaf84465 | 8775 | tp->grc_local_ctrl &= ~gpio_mask; |
314fba34 MC |
8776 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; |
8777 | ||
8778 | /* GPIO1 must be driven high for eeprom write protect */ | |
63c3a66f | 8779 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) |
9d26e213 MC |
8780 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
8781 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
314fba34 | 8782 | } |
1da177e4 LT |
8783 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
8784 | udelay(100); | |
8785 | ||
63c3a66f | 8786 | if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) { |
baf8a94a MC |
8787 | val = tr32(MSGINT_MODE); |
8788 | val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE; | |
5b39de91 MC |
8789 | if (!tg3_flag(tp, 1SHOT_MSI)) |
8790 | val |= MSGINT_MODE_ONE_SHOT_DISABLE; | |
baf8a94a MC |
8791 | tw32(MSGINT_MODE, val); |
8792 | } | |
8793 | ||
63c3a66f | 8794 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
8795 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); |
8796 | udelay(40); | |
8797 | } | |
8798 | ||
8799 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
8800 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
8801 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
8802 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
8803 | WDMAC_MODE_LNGREAD_ENAB); | |
8804 | ||
c5908939 MC |
8805 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8806 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 8807 | if (tg3_flag(tp, TSO_CAPABLE) && |
1da177e4 LT |
8808 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
8809 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
8810 | /* nothing */ | |
8811 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
63c3a66f | 8812 | !tg3_flag(tp, IS_5788)) { |
1da177e4 LT |
8813 | val |= WDMAC_MODE_RX_ACCEL; |
8814 | } | |
8815 | } | |
8816 | ||
d9ab5ad1 | 8817 | /* Enable host coalescing bug fix */ |
63c3a66f | 8818 | if (tg3_flag(tp, 5755_PLUS)) |
f51f3562 | 8819 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
d9ab5ad1 | 8820 | |
788a035e MC |
8821 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
8822 | val |= WDMAC_MODE_BURST_ALL_DATA; | |
8823 | ||
1da177e4 LT |
8824 | tw32_f(WDMAC_MODE, val); |
8825 | udelay(40); | |
8826 | ||
63c3a66f | 8827 | if (tg3_flag(tp, PCIX_MODE)) { |
9974a356 MC |
8828 | u16 pcix_cmd; |
8829 | ||
8830 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8831 | &pcix_cmd); | |
1da177e4 | 8832 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { |
9974a356 MC |
8833 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
8834 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8835 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
9974a356 MC |
8836 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
8837 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8838 | } |
9974a356 MC |
8839 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
8840 | pcix_cmd); | |
1da177e4 LT |
8841 | } |
8842 | ||
8843 | tw32_f(RDMAC_MODE, rdmac_mode); | |
8844 | udelay(40); | |
8845 | ||
8846 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); | |
63c3a66f | 8847 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 | 8848 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); |
9936bcf6 MC |
8849 | |
8850 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
8851 | tw32(SNDDATAC_MODE, | |
8852 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
8853 | else | |
8854 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
8855 | ||
1da177e4 LT |
8856 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
8857 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
7cb32cf2 | 8858 | val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; |
63c3a66f | 8859 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
7cb32cf2 MC |
8860 | val |= RCVDBDI_MODE_LRG_RING_SZ; |
8861 | tw32(RCVDBDI_MODE, val); | |
1da177e4 | 8862 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); |
63c3a66f JP |
8863 | if (tg3_flag(tp, HW_TSO_1) || |
8864 | tg3_flag(tp, HW_TSO_2) || | |
8865 | tg3_flag(tp, HW_TSO_3)) | |
1da177e4 | 8866 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); |
baf8a94a | 8867 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; |
63c3a66f | 8868 | if (tg3_flag(tp, ENABLE_TSS)) |
baf8a94a MC |
8869 | val |= SNDBDI_MODE_MULTI_TXQ_EN; |
8870 | tw32(SNDBDI_MODE, val); | |
1da177e4 LT |
8871 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); |
8872 | ||
8873 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
8874 | err = tg3_load_5701_a0_firmware_fix(tp); | |
8875 | if (err) | |
8876 | return err; | |
8877 | } | |
8878 | ||
63c3a66f | 8879 | if (tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8880 | err = tg3_load_tso_firmware(tp); |
8881 | if (err) | |
8882 | return err; | |
8883 | } | |
1da177e4 LT |
8884 | |
8885 | tp->tx_mode = TX_MODE_ENABLE; | |
f2096f94 | 8886 | |
63c3a66f | 8887 | if (tg3_flag(tp, 5755_PLUS) || |
b1d05210 MC |
8888 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
8889 | tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; | |
f2096f94 MC |
8890 | |
8891 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
8892 | val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE; | |
8893 | tp->tx_mode &= ~val; | |
8894 | tp->tx_mode |= tr32(MAC_TX_MODE) & val; | |
8895 | } | |
8896 | ||
1da177e4 LT |
8897 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
8898 | udelay(100); | |
8899 | ||
63c3a66f | 8900 | if (tg3_flag(tp, ENABLE_RSS)) { |
9d53fa12 | 8901 | int i = 0; |
baf8a94a | 8902 | u32 reg = MAC_RSS_INDIR_TBL_0; |
baf8a94a | 8903 | |
9d53fa12 MC |
8904 | if (tp->irq_cnt == 2) { |
8905 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i += 8) { | |
8906 | tw32(reg, 0x0); | |
8907 | reg += 4; | |
8908 | } | |
8909 | } else { | |
8910 | u32 val; | |
baf8a94a | 8911 | |
9d53fa12 MC |
8912 | while (i < TG3_RSS_INDIR_TBL_SIZE) { |
8913 | val = i % (tp->irq_cnt - 1); | |
8914 | i++; | |
8915 | for (; i % 8; i++) { | |
8916 | val <<= 4; | |
8917 | val |= (i % (tp->irq_cnt - 1)); | |
8918 | } | |
baf8a94a MC |
8919 | tw32(reg, val); |
8920 | reg += 4; | |
8921 | } | |
8922 | } | |
8923 | ||
8924 | /* Setup the "secret" hash key. */ | |
8925 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); | |
8926 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); | |
8927 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); | |
8928 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); | |
8929 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); | |
8930 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); | |
8931 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); | |
8932 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); | |
8933 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); | |
8934 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); | |
8935 | } | |
8936 | ||
1da177e4 | 8937 | tp->rx_mode = RX_MODE_ENABLE; |
63c3a66f | 8938 | if (tg3_flag(tp, 5755_PLUS)) |
af36e6b6 MC |
8939 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; |
8940 | ||
63c3a66f | 8941 | if (tg3_flag(tp, ENABLE_RSS)) |
baf8a94a MC |
8942 | tp->rx_mode |= RX_MODE_RSS_ENABLE | |
8943 | RX_MODE_RSS_ITBL_HASH_BITS_7 | | |
8944 | RX_MODE_RSS_IPV6_HASH_EN | | |
8945 | RX_MODE_RSS_TCP_IPV6_HASH_EN | | |
8946 | RX_MODE_RSS_IPV4_HASH_EN | | |
8947 | RX_MODE_RSS_TCP_IPV4_HASH_EN; | |
8948 | ||
1da177e4 LT |
8949 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
8950 | udelay(10); | |
8951 | ||
1da177e4 LT |
8952 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
8953 | ||
8954 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
f07e9af3 | 8955 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 LT |
8956 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
8957 | udelay(10); | |
8958 | } | |
8959 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
8960 | udelay(10); | |
8961 | ||
f07e9af3 | 8962 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 | 8963 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && |
f07e9af3 | 8964 | !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { |
1da177e4 LT |
8965 | /* Set drive transmission level to 1.2V */ |
8966 | /* only if the signal pre-emphasis bit is not set */ | |
8967 | val = tr32(MAC_SERDES_CFG); | |
8968 | val &= 0xfffff000; | |
8969 | val |= 0x880; | |
8970 | tw32(MAC_SERDES_CFG, val); | |
8971 | } | |
8972 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
8973 | tw32(MAC_SERDES_CFG, 0x616000); | |
8974 | } | |
8975 | ||
8976 | /* Prevent chip from dropping frames when flow control | |
8977 | * is enabled. | |
8978 | */ | |
666bc831 MC |
8979 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
8980 | val = 1; | |
8981 | else | |
8982 | val = 2; | |
8983 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); | |
1da177e4 LT |
8984 | |
8985 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
f07e9af3 | 8986 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
1da177e4 | 8987 | /* Use hardware link auto-negotiation */ |
63c3a66f | 8988 | tg3_flag_set(tp, HW_AUTONEG); |
1da177e4 LT |
8989 | } |
8990 | ||
f07e9af3 | 8991 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
6ff6f81d | 8992 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
d4d2c558 MC |
8993 | u32 tmp; |
8994 | ||
8995 | tmp = tr32(SERDES_RX_CTRL); | |
8996 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
8997 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
8998 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
8999 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
9000 | } | |
9001 | ||
63c3a66f | 9002 | if (!tg3_flag(tp, USE_PHYLIB)) { |
80096068 MC |
9003 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
9004 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
9005 | tp->link_config.speed = tp->link_config.orig_speed; |
9006 | tp->link_config.duplex = tp->link_config.orig_duplex; | |
9007 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | |
9008 | } | |
1da177e4 | 9009 | |
dd477003 MC |
9010 | err = tg3_setup_phy(tp, 0); |
9011 | if (err) | |
9012 | return err; | |
1da177e4 | 9013 | |
f07e9af3 MC |
9014 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
9015 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
dd477003 MC |
9016 | u32 tmp; |
9017 | ||
9018 | /* Clear CRC stats. */ | |
9019 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
9020 | tg3_writephy(tp, MII_TG3_TEST1, | |
9021 | tmp | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 9022 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); |
dd477003 | 9023 | } |
1da177e4 LT |
9024 | } |
9025 | } | |
9026 | ||
9027 | __tg3_set_rx_mode(tp->dev); | |
9028 | ||
9029 | /* Initialize receive rules. */ | |
9030 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
9031 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
9032 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
9033 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
9034 | ||
63c3a66f | 9035 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) |
1da177e4 LT |
9036 | limit = 8; |
9037 | else | |
9038 | limit = 16; | |
63c3a66f | 9039 | if (tg3_flag(tp, ENABLE_ASF)) |
1da177e4 LT |
9040 | limit -= 4; |
9041 | switch (limit) { | |
9042 | case 16: | |
9043 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
9044 | case 15: | |
9045 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
9046 | case 14: | |
9047 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
9048 | case 13: | |
9049 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
9050 | case 12: | |
9051 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
9052 | case 11: | |
9053 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
9054 | case 10: | |
9055 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
9056 | case 9: | |
9057 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
9058 | case 8: | |
9059 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
9060 | case 7: | |
9061 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
9062 | case 6: | |
9063 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
9064 | case 5: | |
9065 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
9066 | case 4: | |
9067 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
9068 | case 3: | |
9069 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
9070 | case 2: | |
9071 | case 1: | |
9072 | ||
9073 | default: | |
9074 | break; | |
855e1111 | 9075 | } |
1da177e4 | 9076 | |
63c3a66f | 9077 | if (tg3_flag(tp, ENABLE_APE)) |
9ce768ea MC |
9078 | /* Write our heartbeat update interval to APE. */ |
9079 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
9080 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
0d3031d9 | 9081 | |
1da177e4 LT |
9082 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); |
9083 | ||
1da177e4 LT |
9084 | return 0; |
9085 | } | |
9086 | ||
9087 | /* Called at device open time to get the chip ready for | |
9088 | * packet processing. Invoked with tp->lock held. | |
9089 | */ | |
8e7a22e3 | 9090 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
1da177e4 | 9091 | { |
1da177e4 LT |
9092 | tg3_switch_clocks(tp); |
9093 | ||
9094 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
9095 | ||
2f751b67 | 9096 | return tg3_reset_hw(tp, reset_phy); |
1da177e4 LT |
9097 | } |
9098 | ||
9099 | #define TG3_STAT_ADD32(PSTAT, REG) \ | |
9100 | do { u32 __val = tr32(REG); \ | |
9101 | (PSTAT)->low += __val; \ | |
9102 | if ((PSTAT)->low < __val) \ | |
9103 | (PSTAT)->high += 1; \ | |
9104 | } while (0) | |
9105 | ||
9106 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
9107 | { | |
9108 | struct tg3_hw_stats *sp = tp->hw_stats; | |
9109 | ||
9110 | if (!netif_carrier_ok(tp->dev)) | |
9111 | return; | |
9112 | ||
9113 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
9114 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
9115 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
9116 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
9117 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
9118 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
9119 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
9120 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
9121 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
9122 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
9123 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
9124 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
9125 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
9126 | ||
9127 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
9128 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
9129 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
9130 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
9131 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
9132 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
9133 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
9134 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
9135 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
9136 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
9137 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
9138 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
9139 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
9140 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
463d305b MC |
9141 | |
9142 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
310050fa MC |
9143 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
9144 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 && | |
9145 | tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) { | |
4d958473 MC |
9146 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); |
9147 | } else { | |
9148 | u32 val = tr32(HOSTCC_FLOW_ATTN); | |
9149 | val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0; | |
9150 | if (val) { | |
9151 | tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM); | |
9152 | sp->rx_discards.low += val; | |
9153 | if (sp->rx_discards.low < val) | |
9154 | sp->rx_discards.high += 1; | |
9155 | } | |
9156 | sp->mbuf_lwm_thresh_hit = sp->rx_discards; | |
9157 | } | |
463d305b | 9158 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); |
1da177e4 LT |
9159 | } |
9160 | ||
0e6cf6a9 MC |
9161 | static void tg3_chk_missed_msi(struct tg3 *tp) |
9162 | { | |
9163 | u32 i; | |
9164 | ||
9165 | for (i = 0; i < tp->irq_cnt; i++) { | |
9166 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9167 | ||
9168 | if (tg3_has_work(tnapi)) { | |
9169 | if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && | |
9170 | tnapi->last_tx_cons == tnapi->tx_cons) { | |
9171 | if (tnapi->chk_msi_cnt < 1) { | |
9172 | tnapi->chk_msi_cnt++; | |
9173 | return; | |
9174 | } | |
7f230735 | 9175 | tg3_msi(0, tnapi); |
0e6cf6a9 MC |
9176 | } |
9177 | } | |
9178 | tnapi->chk_msi_cnt = 0; | |
9179 | tnapi->last_rx_cons = tnapi->rx_rcb_ptr; | |
9180 | tnapi->last_tx_cons = tnapi->tx_cons; | |
9181 | } | |
9182 | } | |
9183 | ||
1da177e4 LT |
9184 | static void tg3_timer(unsigned long __opaque) |
9185 | { | |
9186 | struct tg3 *tp = (struct tg3 *) __opaque; | |
1da177e4 | 9187 | |
5b190624 | 9188 | if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) |
f475f163 MC |
9189 | goto restart_timer; |
9190 | ||
f47c11ee | 9191 | spin_lock(&tp->lock); |
1da177e4 | 9192 | |
0e6cf6a9 MC |
9193 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
9194 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
9195 | tg3_chk_missed_msi(tp); | |
9196 | ||
63c3a66f | 9197 | if (!tg3_flag(tp, TAGGED_STATUS)) { |
fac9b83e DM |
9198 | /* All of this garbage is because when using non-tagged |
9199 | * IRQ status the mailbox/status_block protocol the chip | |
9200 | * uses with the cpu is race prone. | |
9201 | */ | |
898a56f8 | 9202 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { |
fac9b83e DM |
9203 | tw32(GRC_LOCAL_CTRL, |
9204 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
9205 | } else { | |
9206 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
fd2ce37f | 9207 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); |
fac9b83e | 9208 | } |
1da177e4 | 9209 | |
fac9b83e | 9210 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
f47c11ee | 9211 | spin_unlock(&tp->lock); |
db219973 | 9212 | tg3_reset_task_schedule(tp); |
5b190624 | 9213 | goto restart_timer; |
fac9b83e | 9214 | } |
1da177e4 LT |
9215 | } |
9216 | ||
1da177e4 LT |
9217 | /* This part only runs once per second. */ |
9218 | if (!--tp->timer_counter) { | |
63c3a66f | 9219 | if (tg3_flag(tp, 5705_PLUS)) |
fac9b83e DM |
9220 | tg3_periodic_fetch_stats(tp); |
9221 | ||
b0c5943f MC |
9222 | if (tp->setlpicnt && !--tp->setlpicnt) |
9223 | tg3_phy_eee_enable(tp); | |
52b02d04 | 9224 | |
63c3a66f | 9225 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
1da177e4 LT |
9226 | u32 mac_stat; |
9227 | int phy_event; | |
9228 | ||
9229 | mac_stat = tr32(MAC_STATUS); | |
9230 | ||
9231 | phy_event = 0; | |
f07e9af3 | 9232 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { |
1da177e4 LT |
9233 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) |
9234 | phy_event = 1; | |
9235 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
9236 | phy_event = 1; | |
9237 | ||
9238 | if (phy_event) | |
9239 | tg3_setup_phy(tp, 0); | |
63c3a66f | 9240 | } else if (tg3_flag(tp, POLL_SERDES)) { |
1da177e4 LT |
9241 | u32 mac_stat = tr32(MAC_STATUS); |
9242 | int need_setup = 0; | |
9243 | ||
9244 | if (netif_carrier_ok(tp->dev) && | |
9245 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { | |
9246 | need_setup = 1; | |
9247 | } | |
be98da6a | 9248 | if (!netif_carrier_ok(tp->dev) && |
1da177e4 LT |
9249 | (mac_stat & (MAC_STATUS_PCS_SYNCED | |
9250 | MAC_STATUS_SIGNAL_DET))) { | |
9251 | need_setup = 1; | |
9252 | } | |
9253 | if (need_setup) { | |
3d3ebe74 MC |
9254 | if (!tp->serdes_counter) { |
9255 | tw32_f(MAC_MODE, | |
9256 | (tp->mac_mode & | |
9257 | ~MAC_MODE_PORT_MODE_MASK)); | |
9258 | udelay(40); | |
9259 | tw32_f(MAC_MODE, tp->mac_mode); | |
9260 | udelay(40); | |
9261 | } | |
1da177e4 LT |
9262 | tg3_setup_phy(tp, 0); |
9263 | } | |
f07e9af3 | 9264 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
63c3a66f | 9265 | tg3_flag(tp, 5780_CLASS)) { |
747e8f8b | 9266 | tg3_serdes_parallel_detect(tp); |
57d8b880 | 9267 | } |
1da177e4 LT |
9268 | |
9269 | tp->timer_counter = tp->timer_multiplier; | |
9270 | } | |
9271 | ||
130b8e4d MC |
9272 | /* Heartbeat is only sent once every 2 seconds. |
9273 | * | |
9274 | * The heartbeat is to tell the ASF firmware that the host | |
9275 | * driver is still alive. In the event that the OS crashes, | |
9276 | * ASF needs to reset the hardware to free up the FIFO space | |
9277 | * that may be filled with rx packets destined for the host. | |
9278 | * If the FIFO is full, ASF will no longer function properly. | |
9279 | * | |
9280 | * Unintended resets have been reported on real time kernels | |
9281 | * where the timer doesn't run on time. Netpoll will also have | |
9282 | * same problem. | |
9283 | * | |
9284 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
9285 | * to check the ring condition when the heartbeat is expiring | |
9286 | * before doing the reset. This will prevent most unintended | |
9287 | * resets. | |
9288 | */ | |
1da177e4 | 9289 | if (!--tp->asf_counter) { |
63c3a66f | 9290 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { |
7c5026aa MC |
9291 | tg3_wait_for_event_ack(tp); |
9292 | ||
bbadf503 | 9293 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, |
130b8e4d | 9294 | FWCMD_NICDRV_ALIVE3); |
bbadf503 | 9295 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); |
c6cdf436 MC |
9296 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, |
9297 | TG3_FW_UPDATE_TIMEOUT_SEC); | |
4ba526ce MC |
9298 | |
9299 | tg3_generate_fw_event(tp); | |
1da177e4 LT |
9300 | } |
9301 | tp->asf_counter = tp->asf_multiplier; | |
9302 | } | |
9303 | ||
f47c11ee | 9304 | spin_unlock(&tp->lock); |
1da177e4 | 9305 | |
f475f163 | 9306 | restart_timer: |
1da177e4 LT |
9307 | tp->timer.expires = jiffies + tp->timer_offset; |
9308 | add_timer(&tp->timer); | |
9309 | } | |
9310 | ||
4f125f42 | 9311 | static int tg3_request_irq(struct tg3 *tp, int irq_num) |
fcfa0a32 | 9312 | { |
7d12e780 | 9313 | irq_handler_t fn; |
fcfa0a32 | 9314 | unsigned long flags; |
4f125f42 MC |
9315 | char *name; |
9316 | struct tg3_napi *tnapi = &tp->napi[irq_num]; | |
9317 | ||
9318 | if (tp->irq_cnt == 1) | |
9319 | name = tp->dev->name; | |
9320 | else { | |
9321 | name = &tnapi->irq_lbl[0]; | |
9322 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); | |
9323 | name[IFNAMSIZ-1] = 0; | |
9324 | } | |
fcfa0a32 | 9325 | |
63c3a66f | 9326 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
fcfa0a32 | 9327 | fn = tg3_msi; |
63c3a66f | 9328 | if (tg3_flag(tp, 1SHOT_MSI)) |
fcfa0a32 | 9329 | fn = tg3_msi_1shot; |
ab392d2d | 9330 | flags = 0; |
fcfa0a32 MC |
9331 | } else { |
9332 | fn = tg3_interrupt; | |
63c3a66f | 9333 | if (tg3_flag(tp, TAGGED_STATUS)) |
fcfa0a32 | 9334 | fn = tg3_interrupt_tagged; |
ab392d2d | 9335 | flags = IRQF_SHARED; |
fcfa0a32 | 9336 | } |
4f125f42 MC |
9337 | |
9338 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); | |
fcfa0a32 MC |
9339 | } |
9340 | ||
7938109f MC |
9341 | static int tg3_test_interrupt(struct tg3 *tp) |
9342 | { | |
09943a18 | 9343 | struct tg3_napi *tnapi = &tp->napi[0]; |
7938109f | 9344 | struct net_device *dev = tp->dev; |
b16250e3 | 9345 | int err, i, intr_ok = 0; |
f6eb9b1f | 9346 | u32 val; |
7938109f | 9347 | |
d4bc3927 MC |
9348 | if (!netif_running(dev)) |
9349 | return -ENODEV; | |
9350 | ||
7938109f MC |
9351 | tg3_disable_ints(tp); |
9352 | ||
4f125f42 | 9353 | free_irq(tnapi->irq_vec, tnapi); |
7938109f | 9354 | |
f6eb9b1f MC |
9355 | /* |
9356 | * Turn off MSI one shot mode. Otherwise this test has no | |
9357 | * observable way to know whether the interrupt was delivered. | |
9358 | */ | |
3aa1cdf8 | 9359 | if (tg3_flag(tp, 57765_PLUS)) { |
f6eb9b1f MC |
9360 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; |
9361 | tw32(MSGINT_MODE, val); | |
9362 | } | |
9363 | ||
4f125f42 | 9364 | err = request_irq(tnapi->irq_vec, tg3_test_isr, |
09943a18 | 9365 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi); |
7938109f MC |
9366 | if (err) |
9367 | return err; | |
9368 | ||
898a56f8 | 9369 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; |
7938109f MC |
9370 | tg3_enable_ints(tp); |
9371 | ||
9372 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 9373 | tnapi->coal_now); |
7938109f MC |
9374 | |
9375 | for (i = 0; i < 5; i++) { | |
b16250e3 MC |
9376 | u32 int_mbox, misc_host_ctrl; |
9377 | ||
898a56f8 | 9378 | int_mbox = tr32_mailbox(tnapi->int_mbox); |
b16250e3 MC |
9379 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
9380 | ||
9381 | if ((int_mbox != 0) || | |
9382 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
9383 | intr_ok = 1; | |
7938109f | 9384 | break; |
b16250e3 MC |
9385 | } |
9386 | ||
3aa1cdf8 MC |
9387 | if (tg3_flag(tp, 57765_PLUS) && |
9388 | tnapi->hw_status->status_tag != tnapi->last_tag) | |
9389 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | |
9390 | ||
7938109f MC |
9391 | msleep(10); |
9392 | } | |
9393 | ||
9394 | tg3_disable_ints(tp); | |
9395 | ||
4f125f42 | 9396 | free_irq(tnapi->irq_vec, tnapi); |
6aa20a22 | 9397 | |
4f125f42 | 9398 | err = tg3_request_irq(tp, 0); |
7938109f MC |
9399 | |
9400 | if (err) | |
9401 | return err; | |
9402 | ||
f6eb9b1f MC |
9403 | if (intr_ok) { |
9404 | /* Reenable MSI one shot mode. */ | |
5b39de91 | 9405 | if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) { |
f6eb9b1f MC |
9406 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; |
9407 | tw32(MSGINT_MODE, val); | |
9408 | } | |
7938109f | 9409 | return 0; |
f6eb9b1f | 9410 | } |
7938109f MC |
9411 | |
9412 | return -EIO; | |
9413 | } | |
9414 | ||
9415 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
9416 | * successfully restored | |
9417 | */ | |
9418 | static int tg3_test_msi(struct tg3 *tp) | |
9419 | { | |
7938109f MC |
9420 | int err; |
9421 | u16 pci_cmd; | |
9422 | ||
63c3a66f | 9423 | if (!tg3_flag(tp, USING_MSI)) |
7938109f MC |
9424 | return 0; |
9425 | ||
9426 | /* Turn off SERR reporting in case MSI terminates with Master | |
9427 | * Abort. | |
9428 | */ | |
9429 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
9430 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
9431 | pci_cmd & ~PCI_COMMAND_SERR); | |
9432 | ||
9433 | err = tg3_test_interrupt(tp); | |
9434 | ||
9435 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
9436 | ||
9437 | if (!err) | |
9438 | return 0; | |
9439 | ||
9440 | /* other failures */ | |
9441 | if (err != -EIO) | |
9442 | return err; | |
9443 | ||
9444 | /* MSI test failed, go back to INTx mode */ | |
5129c3a3 MC |
9445 | netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " |
9446 | "to INTx mode. Please report this failure to the PCI " | |
9447 | "maintainer and include system chipset information\n"); | |
7938109f | 9448 | |
4f125f42 | 9449 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
09943a18 | 9450 | |
7938109f MC |
9451 | pci_disable_msi(tp->pdev); |
9452 | ||
63c3a66f | 9453 | tg3_flag_clear(tp, USING_MSI); |
dc8bf1b1 | 9454 | tp->napi[0].irq_vec = tp->pdev->irq; |
7938109f | 9455 | |
4f125f42 | 9456 | err = tg3_request_irq(tp, 0); |
7938109f MC |
9457 | if (err) |
9458 | return err; | |
9459 | ||
9460 | /* Need to reset the chip because the MSI cycle may have terminated | |
9461 | * with Master Abort. | |
9462 | */ | |
f47c11ee | 9463 | tg3_full_lock(tp, 1); |
7938109f | 9464 | |
944d980e | 9465 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
8e7a22e3 | 9466 | err = tg3_init_hw(tp, 1); |
7938109f | 9467 | |
f47c11ee | 9468 | tg3_full_unlock(tp); |
7938109f MC |
9469 | |
9470 | if (err) | |
4f125f42 | 9471 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
7938109f MC |
9472 | |
9473 | return err; | |
9474 | } | |
9475 | ||
9e9fd12d MC |
9476 | static int tg3_request_firmware(struct tg3 *tp) |
9477 | { | |
9478 | const __be32 *fw_data; | |
9479 | ||
9480 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
05dbe005 JP |
9481 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", |
9482 | tp->fw_needed); | |
9e9fd12d MC |
9483 | return -ENOENT; |
9484 | } | |
9485 | ||
9486 | fw_data = (void *)tp->fw->data; | |
9487 | ||
9488 | /* Firmware blob starts with version numbers, followed by | |
9489 | * start address and _full_ length including BSS sections | |
9490 | * (which must be longer than the actual data, of course | |
9491 | */ | |
9492 | ||
9493 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
9494 | if (tp->fw_len < (tp->fw->size - 12)) { | |
05dbe005 JP |
9495 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", |
9496 | tp->fw_len, tp->fw_needed); | |
9e9fd12d MC |
9497 | release_firmware(tp->fw); |
9498 | tp->fw = NULL; | |
9499 | return -EINVAL; | |
9500 | } | |
9501 | ||
9502 | /* We no longer need firmware; we have it. */ | |
9503 | tp->fw_needed = NULL; | |
9504 | return 0; | |
9505 | } | |
9506 | ||
679563f4 MC |
9507 | static bool tg3_enable_msix(struct tg3 *tp) |
9508 | { | |
9509 | int i, rc, cpus = num_online_cpus(); | |
9510 | struct msix_entry msix_ent[tp->irq_max]; | |
9511 | ||
9512 | if (cpus == 1) | |
9513 | /* Just fallback to the simpler MSI mode. */ | |
9514 | return false; | |
9515 | ||
9516 | /* | |
9517 | * We want as many rx rings enabled as there are cpus. | |
9518 | * The first MSIX vector only deals with link interrupts, etc, | |
9519 | * so we add one to the number of vectors we are requesting. | |
9520 | */ | |
9521 | tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max); | |
9522 | ||
9523 | for (i = 0; i < tp->irq_max; i++) { | |
9524 | msix_ent[i].entry = i; | |
9525 | msix_ent[i].vector = 0; | |
9526 | } | |
9527 | ||
9528 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); | |
2430b031 MC |
9529 | if (rc < 0) { |
9530 | return false; | |
9531 | } else if (rc != 0) { | |
679563f4 MC |
9532 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) |
9533 | return false; | |
05dbe005 JP |
9534 | netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", |
9535 | tp->irq_cnt, rc); | |
679563f4 MC |
9536 | tp->irq_cnt = rc; |
9537 | } | |
9538 | ||
9539 | for (i = 0; i < tp->irq_max; i++) | |
9540 | tp->napi[i].irq_vec = msix_ent[i].vector; | |
9541 | ||
2ddaad39 BH |
9542 | netif_set_real_num_tx_queues(tp->dev, 1); |
9543 | rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1; | |
9544 | if (netif_set_real_num_rx_queues(tp->dev, rc)) { | |
9545 | pci_disable_msix(tp->pdev); | |
9546 | return false; | |
9547 | } | |
b92b9040 MC |
9548 | |
9549 | if (tp->irq_cnt > 1) { | |
63c3a66f | 9550 | tg3_flag_set(tp, ENABLE_RSS); |
d78b59f5 MC |
9551 | |
9552 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
9553 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
63c3a66f | 9554 | tg3_flag_set(tp, ENABLE_TSS); |
b92b9040 MC |
9555 | netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1); |
9556 | } | |
9557 | } | |
2430b031 | 9558 | |
679563f4 MC |
9559 | return true; |
9560 | } | |
9561 | ||
07b0173c MC |
9562 | static void tg3_ints_init(struct tg3 *tp) |
9563 | { | |
63c3a66f JP |
9564 | if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && |
9565 | !tg3_flag(tp, TAGGED_STATUS)) { | |
07b0173c MC |
9566 | /* All MSI supporting chips should support tagged |
9567 | * status. Assert that this is the case. | |
9568 | */ | |
5129c3a3 MC |
9569 | netdev_warn(tp->dev, |
9570 | "MSI without TAGGED_STATUS? Not using MSI\n"); | |
679563f4 | 9571 | goto defcfg; |
07b0173c | 9572 | } |
4f125f42 | 9573 | |
63c3a66f JP |
9574 | if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) |
9575 | tg3_flag_set(tp, USING_MSIX); | |
9576 | else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) | |
9577 | tg3_flag_set(tp, USING_MSI); | |
679563f4 | 9578 | |
63c3a66f | 9579 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
679563f4 | 9580 | u32 msi_mode = tr32(MSGINT_MODE); |
63c3a66f | 9581 | if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) |
baf8a94a | 9582 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; |
5b39de91 MC |
9583 | if (!tg3_flag(tp, 1SHOT_MSI)) |
9584 | msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE; | |
679563f4 MC |
9585 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); |
9586 | } | |
9587 | defcfg: | |
63c3a66f | 9588 | if (!tg3_flag(tp, USING_MSIX)) { |
679563f4 MC |
9589 | tp->irq_cnt = 1; |
9590 | tp->napi[0].irq_vec = tp->pdev->irq; | |
2ddaad39 | 9591 | netif_set_real_num_tx_queues(tp->dev, 1); |
85407885 | 9592 | netif_set_real_num_rx_queues(tp->dev, 1); |
679563f4 | 9593 | } |
07b0173c MC |
9594 | } |
9595 | ||
9596 | static void tg3_ints_fini(struct tg3 *tp) | |
9597 | { | |
63c3a66f | 9598 | if (tg3_flag(tp, USING_MSIX)) |
679563f4 | 9599 | pci_disable_msix(tp->pdev); |
63c3a66f | 9600 | else if (tg3_flag(tp, USING_MSI)) |
679563f4 | 9601 | pci_disable_msi(tp->pdev); |
63c3a66f JP |
9602 | tg3_flag_clear(tp, USING_MSI); |
9603 | tg3_flag_clear(tp, USING_MSIX); | |
9604 | tg3_flag_clear(tp, ENABLE_RSS); | |
9605 | tg3_flag_clear(tp, ENABLE_TSS); | |
07b0173c MC |
9606 | } |
9607 | ||
1da177e4 LT |
9608 | static int tg3_open(struct net_device *dev) |
9609 | { | |
9610 | struct tg3 *tp = netdev_priv(dev); | |
4f125f42 | 9611 | int i, err; |
1da177e4 | 9612 | |
9e9fd12d MC |
9613 | if (tp->fw_needed) { |
9614 | err = tg3_request_firmware(tp); | |
9615 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
9616 | if (err) | |
9617 | return err; | |
9618 | } else if (err) { | |
05dbe005 | 9619 | netdev_warn(tp->dev, "TSO capability disabled\n"); |
63c3a66f JP |
9620 | tg3_flag_clear(tp, TSO_CAPABLE); |
9621 | } else if (!tg3_flag(tp, TSO_CAPABLE)) { | |
05dbe005 | 9622 | netdev_notice(tp->dev, "TSO capability restored\n"); |
63c3a66f | 9623 | tg3_flag_set(tp, TSO_CAPABLE); |
9e9fd12d MC |
9624 | } |
9625 | } | |
9626 | ||
c49a1561 MC |
9627 | netif_carrier_off(tp->dev); |
9628 | ||
c866b7ea | 9629 | err = tg3_power_up(tp); |
2f751b67 | 9630 | if (err) |
bc1c7567 | 9631 | return err; |
2f751b67 MC |
9632 | |
9633 | tg3_full_lock(tp, 0); | |
bc1c7567 | 9634 | |
1da177e4 | 9635 | tg3_disable_ints(tp); |
63c3a66f | 9636 | tg3_flag_clear(tp, INIT_COMPLETE); |
1da177e4 | 9637 | |
f47c11ee | 9638 | tg3_full_unlock(tp); |
1da177e4 | 9639 | |
679563f4 MC |
9640 | /* |
9641 | * Setup interrupts first so we know how | |
9642 | * many NAPI resources to allocate | |
9643 | */ | |
9644 | tg3_ints_init(tp); | |
9645 | ||
1da177e4 LT |
9646 | /* The placement of this call is tied |
9647 | * to the setup and use of Host TX descriptors. | |
9648 | */ | |
9649 | err = tg3_alloc_consistent(tp); | |
9650 | if (err) | |
679563f4 | 9651 | goto err_out1; |
88b06bc2 | 9652 | |
66cfd1bd MC |
9653 | tg3_napi_init(tp); |
9654 | ||
fed97810 | 9655 | tg3_napi_enable(tp); |
1da177e4 | 9656 | |
4f125f42 MC |
9657 | for (i = 0; i < tp->irq_cnt; i++) { |
9658 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9659 | err = tg3_request_irq(tp, i); | |
9660 | if (err) { | |
5bc09186 MC |
9661 | for (i--; i >= 0; i--) { |
9662 | tnapi = &tp->napi[i]; | |
4f125f42 | 9663 | free_irq(tnapi->irq_vec, tnapi); |
5bc09186 MC |
9664 | } |
9665 | goto err_out2; | |
4f125f42 MC |
9666 | } |
9667 | } | |
1da177e4 | 9668 | |
f47c11ee | 9669 | tg3_full_lock(tp, 0); |
1da177e4 | 9670 | |
8e7a22e3 | 9671 | err = tg3_init_hw(tp, 1); |
1da177e4 | 9672 | if (err) { |
944d980e | 9673 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
9674 | tg3_free_rings(tp); |
9675 | } else { | |
0e6cf6a9 MC |
9676 | if (tg3_flag(tp, TAGGED_STATUS) && |
9677 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | |
9678 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) | |
fac9b83e DM |
9679 | tp->timer_offset = HZ; |
9680 | else | |
9681 | tp->timer_offset = HZ / 10; | |
9682 | ||
9683 | BUG_ON(tp->timer_offset > HZ); | |
9684 | tp->timer_counter = tp->timer_multiplier = | |
9685 | (HZ / tp->timer_offset); | |
9686 | tp->asf_counter = tp->asf_multiplier = | |
28fbef78 | 9687 | ((HZ / tp->timer_offset) * 2); |
1da177e4 LT |
9688 | |
9689 | init_timer(&tp->timer); | |
9690 | tp->timer.expires = jiffies + tp->timer_offset; | |
9691 | tp->timer.data = (unsigned long) tp; | |
9692 | tp->timer.function = tg3_timer; | |
1da177e4 LT |
9693 | } |
9694 | ||
f47c11ee | 9695 | tg3_full_unlock(tp); |
1da177e4 | 9696 | |
07b0173c | 9697 | if (err) |
679563f4 | 9698 | goto err_out3; |
1da177e4 | 9699 | |
63c3a66f | 9700 | if (tg3_flag(tp, USING_MSI)) { |
7938109f | 9701 | err = tg3_test_msi(tp); |
fac9b83e | 9702 | |
7938109f | 9703 | if (err) { |
f47c11ee | 9704 | tg3_full_lock(tp, 0); |
944d980e | 9705 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
7938109f | 9706 | tg3_free_rings(tp); |
f47c11ee | 9707 | tg3_full_unlock(tp); |
7938109f | 9708 | |
679563f4 | 9709 | goto err_out2; |
7938109f | 9710 | } |
fcfa0a32 | 9711 | |
63c3a66f | 9712 | if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { |
f6eb9b1f | 9713 | u32 val = tr32(PCIE_TRANSACTION_CFG); |
fcfa0a32 | 9714 | |
f6eb9b1f MC |
9715 | tw32(PCIE_TRANSACTION_CFG, |
9716 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
fcfa0a32 | 9717 | } |
7938109f MC |
9718 | } |
9719 | ||
b02fd9e3 MC |
9720 | tg3_phy_start(tp); |
9721 | ||
f47c11ee | 9722 | tg3_full_lock(tp, 0); |
1da177e4 | 9723 | |
7938109f | 9724 | add_timer(&tp->timer); |
63c3a66f | 9725 | tg3_flag_set(tp, INIT_COMPLETE); |
1da177e4 LT |
9726 | tg3_enable_ints(tp); |
9727 | ||
f47c11ee | 9728 | tg3_full_unlock(tp); |
1da177e4 | 9729 | |
fe5f5787 | 9730 | netif_tx_start_all_queues(dev); |
1da177e4 | 9731 | |
06c03c02 MB |
9732 | /* |
9733 | * Reset loopback feature if it was turned on while the device was down | |
9734 | * make sure that it's installed properly now. | |
9735 | */ | |
9736 | if (dev->features & NETIF_F_LOOPBACK) | |
9737 | tg3_set_loopback(dev, dev->features); | |
9738 | ||
1da177e4 | 9739 | return 0; |
07b0173c | 9740 | |
679563f4 | 9741 | err_out3: |
4f125f42 MC |
9742 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9743 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9744 | free_irq(tnapi->irq_vec, tnapi); | |
9745 | } | |
07b0173c | 9746 | |
679563f4 | 9747 | err_out2: |
fed97810 | 9748 | tg3_napi_disable(tp); |
66cfd1bd | 9749 | tg3_napi_fini(tp); |
07b0173c | 9750 | tg3_free_consistent(tp); |
679563f4 MC |
9751 | |
9752 | err_out1: | |
9753 | tg3_ints_fini(tp); | |
cd0d7228 MC |
9754 | tg3_frob_aux_power(tp, false); |
9755 | pci_set_power_state(tp->pdev, PCI_D3hot); | |
07b0173c | 9756 | return err; |
1da177e4 LT |
9757 | } |
9758 | ||
511d2224 ED |
9759 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *, |
9760 | struct rtnl_link_stats64 *); | |
1da177e4 LT |
9761 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *); |
9762 | ||
9763 | static int tg3_close(struct net_device *dev) | |
9764 | { | |
4f125f42 | 9765 | int i; |
1da177e4 LT |
9766 | struct tg3 *tp = netdev_priv(dev); |
9767 | ||
fed97810 | 9768 | tg3_napi_disable(tp); |
db219973 | 9769 | tg3_reset_task_cancel(tp); |
7faa006f | 9770 | |
fe5f5787 | 9771 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
9772 | |
9773 | del_timer_sync(&tp->timer); | |
9774 | ||
24bb4fb6 MC |
9775 | tg3_phy_stop(tp); |
9776 | ||
f47c11ee | 9777 | tg3_full_lock(tp, 1); |
1da177e4 LT |
9778 | |
9779 | tg3_disable_ints(tp); | |
9780 | ||
944d980e | 9781 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 9782 | tg3_free_rings(tp); |
63c3a66f | 9783 | tg3_flag_clear(tp, INIT_COMPLETE); |
1da177e4 | 9784 | |
f47c11ee | 9785 | tg3_full_unlock(tp); |
1da177e4 | 9786 | |
4f125f42 MC |
9787 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9788 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9789 | free_irq(tnapi->irq_vec, tnapi); | |
9790 | } | |
07b0173c MC |
9791 | |
9792 | tg3_ints_fini(tp); | |
1da177e4 | 9793 | |
511d2224 ED |
9794 | tg3_get_stats64(tp->dev, &tp->net_stats_prev); |
9795 | ||
1da177e4 LT |
9796 | memcpy(&tp->estats_prev, tg3_get_estats(tp), |
9797 | sizeof(tp->estats_prev)); | |
9798 | ||
66cfd1bd MC |
9799 | tg3_napi_fini(tp); |
9800 | ||
1da177e4 LT |
9801 | tg3_free_consistent(tp); |
9802 | ||
c866b7ea | 9803 | tg3_power_down(tp); |
bc1c7567 MC |
9804 | |
9805 | netif_carrier_off(tp->dev); | |
9806 | ||
1da177e4 LT |
9807 | return 0; |
9808 | } | |
9809 | ||
511d2224 | 9810 | static inline u64 get_stat64(tg3_stat64_t *val) |
816f8b86 SB |
9811 | { |
9812 | return ((u64)val->high << 32) | ((u64)val->low); | |
9813 | } | |
9814 | ||
511d2224 | 9815 | static u64 calc_crc_errors(struct tg3 *tp) |
1da177e4 LT |
9816 | { |
9817 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9818 | ||
f07e9af3 | 9819 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
1da177e4 LT |
9820 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
9821 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
1da177e4 LT |
9822 | u32 val; |
9823 | ||
f47c11ee | 9824 | spin_lock_bh(&tp->lock); |
569a5df8 MC |
9825 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
9826 | tg3_writephy(tp, MII_TG3_TEST1, | |
9827 | val | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 9828 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); |
1da177e4 LT |
9829 | } else |
9830 | val = 0; | |
f47c11ee | 9831 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
9832 | |
9833 | tp->phy_crc_errors += val; | |
9834 | ||
9835 | return tp->phy_crc_errors; | |
9836 | } | |
9837 | ||
9838 | return get_stat64(&hw_stats->rx_fcs_errors); | |
9839 | } | |
9840 | ||
9841 | #define ESTAT_ADD(member) \ | |
9842 | estats->member = old_estats->member + \ | |
511d2224 | 9843 | get_stat64(&hw_stats->member) |
1da177e4 LT |
9844 | |
9845 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) | |
9846 | { | |
9847 | struct tg3_ethtool_stats *estats = &tp->estats; | |
9848 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; | |
9849 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9850 | ||
9851 | if (!hw_stats) | |
9852 | return old_estats; | |
9853 | ||
9854 | ESTAT_ADD(rx_octets); | |
9855 | ESTAT_ADD(rx_fragments); | |
9856 | ESTAT_ADD(rx_ucast_packets); | |
9857 | ESTAT_ADD(rx_mcast_packets); | |
9858 | ESTAT_ADD(rx_bcast_packets); | |
9859 | ESTAT_ADD(rx_fcs_errors); | |
9860 | ESTAT_ADD(rx_align_errors); | |
9861 | ESTAT_ADD(rx_xon_pause_rcvd); | |
9862 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
9863 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
9864 | ESTAT_ADD(rx_xoff_entered); | |
9865 | ESTAT_ADD(rx_frame_too_long_errors); | |
9866 | ESTAT_ADD(rx_jabbers); | |
9867 | ESTAT_ADD(rx_undersize_packets); | |
9868 | ESTAT_ADD(rx_in_length_errors); | |
9869 | ESTAT_ADD(rx_out_length_errors); | |
9870 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
9871 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
9872 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
9873 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
9874 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
9875 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
9876 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
9877 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
9878 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
9879 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
9880 | ||
9881 | ESTAT_ADD(tx_octets); | |
9882 | ESTAT_ADD(tx_collisions); | |
9883 | ESTAT_ADD(tx_xon_sent); | |
9884 | ESTAT_ADD(tx_xoff_sent); | |
9885 | ESTAT_ADD(tx_flow_control); | |
9886 | ESTAT_ADD(tx_mac_errors); | |
9887 | ESTAT_ADD(tx_single_collisions); | |
9888 | ESTAT_ADD(tx_mult_collisions); | |
9889 | ESTAT_ADD(tx_deferred); | |
9890 | ESTAT_ADD(tx_excessive_collisions); | |
9891 | ESTAT_ADD(tx_late_collisions); | |
9892 | ESTAT_ADD(tx_collide_2times); | |
9893 | ESTAT_ADD(tx_collide_3times); | |
9894 | ESTAT_ADD(tx_collide_4times); | |
9895 | ESTAT_ADD(tx_collide_5times); | |
9896 | ESTAT_ADD(tx_collide_6times); | |
9897 | ESTAT_ADD(tx_collide_7times); | |
9898 | ESTAT_ADD(tx_collide_8times); | |
9899 | ESTAT_ADD(tx_collide_9times); | |
9900 | ESTAT_ADD(tx_collide_10times); | |
9901 | ESTAT_ADD(tx_collide_11times); | |
9902 | ESTAT_ADD(tx_collide_12times); | |
9903 | ESTAT_ADD(tx_collide_13times); | |
9904 | ESTAT_ADD(tx_collide_14times); | |
9905 | ESTAT_ADD(tx_collide_15times); | |
9906 | ESTAT_ADD(tx_ucast_packets); | |
9907 | ESTAT_ADD(tx_mcast_packets); | |
9908 | ESTAT_ADD(tx_bcast_packets); | |
9909 | ESTAT_ADD(tx_carrier_sense_errors); | |
9910 | ESTAT_ADD(tx_discards); | |
9911 | ESTAT_ADD(tx_errors); | |
9912 | ||
9913 | ESTAT_ADD(dma_writeq_full); | |
9914 | ESTAT_ADD(dma_write_prioq_full); | |
9915 | ESTAT_ADD(rxbds_empty); | |
9916 | ESTAT_ADD(rx_discards); | |
9917 | ESTAT_ADD(rx_errors); | |
9918 | ESTAT_ADD(rx_threshold_hit); | |
9919 | ||
9920 | ESTAT_ADD(dma_readq_full); | |
9921 | ESTAT_ADD(dma_read_prioq_full); | |
9922 | ESTAT_ADD(tx_comp_queue_full); | |
9923 | ||
9924 | ESTAT_ADD(ring_set_send_prod_index); | |
9925 | ESTAT_ADD(ring_status_update); | |
9926 | ESTAT_ADD(nic_irqs); | |
9927 | ESTAT_ADD(nic_avoided_irqs); | |
9928 | ESTAT_ADD(nic_tx_threshold_hit); | |
9929 | ||
4452d099 MC |
9930 | ESTAT_ADD(mbuf_lwm_thresh_hit); |
9931 | ||
1da177e4 LT |
9932 | return estats; |
9933 | } | |
9934 | ||
511d2224 ED |
9935 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev, |
9936 | struct rtnl_link_stats64 *stats) | |
1da177e4 LT |
9937 | { |
9938 | struct tg3 *tp = netdev_priv(dev); | |
511d2224 | 9939 | struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; |
1da177e4 LT |
9940 | struct tg3_hw_stats *hw_stats = tp->hw_stats; |
9941 | ||
9942 | if (!hw_stats) | |
9943 | return old_stats; | |
9944 | ||
9945 | stats->rx_packets = old_stats->rx_packets + | |
9946 | get_stat64(&hw_stats->rx_ucast_packets) + | |
9947 | get_stat64(&hw_stats->rx_mcast_packets) + | |
9948 | get_stat64(&hw_stats->rx_bcast_packets); | |
6aa20a22 | 9949 | |
1da177e4 LT |
9950 | stats->tx_packets = old_stats->tx_packets + |
9951 | get_stat64(&hw_stats->tx_ucast_packets) + | |
9952 | get_stat64(&hw_stats->tx_mcast_packets) + | |
9953 | get_stat64(&hw_stats->tx_bcast_packets); | |
9954 | ||
9955 | stats->rx_bytes = old_stats->rx_bytes + | |
9956 | get_stat64(&hw_stats->rx_octets); | |
9957 | stats->tx_bytes = old_stats->tx_bytes + | |
9958 | get_stat64(&hw_stats->tx_octets); | |
9959 | ||
9960 | stats->rx_errors = old_stats->rx_errors + | |
4f63b877 | 9961 | get_stat64(&hw_stats->rx_errors); |
1da177e4 LT |
9962 | stats->tx_errors = old_stats->tx_errors + |
9963 | get_stat64(&hw_stats->tx_errors) + | |
9964 | get_stat64(&hw_stats->tx_mac_errors) + | |
9965 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
9966 | get_stat64(&hw_stats->tx_discards); | |
9967 | ||
9968 | stats->multicast = old_stats->multicast + | |
9969 | get_stat64(&hw_stats->rx_mcast_packets); | |
9970 | stats->collisions = old_stats->collisions + | |
9971 | get_stat64(&hw_stats->tx_collisions); | |
9972 | ||
9973 | stats->rx_length_errors = old_stats->rx_length_errors + | |
9974 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
9975 | get_stat64(&hw_stats->rx_undersize_packets); | |
9976 | ||
9977 | stats->rx_over_errors = old_stats->rx_over_errors + | |
9978 | get_stat64(&hw_stats->rxbds_empty); | |
9979 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
9980 | get_stat64(&hw_stats->rx_align_errors); | |
9981 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
9982 | get_stat64(&hw_stats->tx_discards); | |
9983 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
9984 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
9985 | ||
9986 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
9987 | calc_crc_errors(tp); | |
9988 | ||
4f63b877 JL |
9989 | stats->rx_missed_errors = old_stats->rx_missed_errors + |
9990 | get_stat64(&hw_stats->rx_discards); | |
9991 | ||
b0057c51 | 9992 | stats->rx_dropped = tp->rx_dropped; |
48855432 | 9993 | stats->tx_dropped = tp->tx_dropped; |
b0057c51 | 9994 | |
1da177e4 LT |
9995 | return stats; |
9996 | } | |
9997 | ||
9998 | static inline u32 calc_crc(unsigned char *buf, int len) | |
9999 | { | |
10000 | u32 reg; | |
10001 | u32 tmp; | |
10002 | int j, k; | |
10003 | ||
10004 | reg = 0xffffffff; | |
10005 | ||
10006 | for (j = 0; j < len; j++) { | |
10007 | reg ^= buf[j]; | |
10008 | ||
10009 | for (k = 0; k < 8; k++) { | |
10010 | tmp = reg & 0x01; | |
10011 | ||
10012 | reg >>= 1; | |
10013 | ||
859a5887 | 10014 | if (tmp) |
1da177e4 | 10015 | reg ^= 0xedb88320; |
1da177e4 LT |
10016 | } |
10017 | } | |
10018 | ||
10019 | return ~reg; | |
10020 | } | |
10021 | ||
10022 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
10023 | { | |
10024 | /* accept or reject all multicast frames */ | |
10025 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
10026 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
10027 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
10028 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
10029 | } | |
10030 | ||
10031 | static void __tg3_set_rx_mode(struct net_device *dev) | |
10032 | { | |
10033 | struct tg3 *tp = netdev_priv(dev); | |
10034 | u32 rx_mode; | |
10035 | ||
10036 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
10037 | RX_MODE_KEEP_VLAN_TAG); | |
10038 | ||
bf933c80 | 10039 | #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE) |
1da177e4 LT |
10040 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG |
10041 | * flag clear. | |
10042 | */ | |
63c3a66f | 10043 | if (!tg3_flag(tp, ENABLE_ASF)) |
1da177e4 LT |
10044 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; |
10045 | #endif | |
10046 | ||
10047 | if (dev->flags & IFF_PROMISC) { | |
10048 | /* Promiscuous mode. */ | |
10049 | rx_mode |= RX_MODE_PROMISC; | |
10050 | } else if (dev->flags & IFF_ALLMULTI) { | |
10051 | /* Accept all multicast. */ | |
de6f31eb | 10052 | tg3_set_multi(tp, 1); |
4cd24eaf | 10053 | } else if (netdev_mc_empty(dev)) { |
1da177e4 | 10054 | /* Reject all multicast. */ |
de6f31eb | 10055 | tg3_set_multi(tp, 0); |
1da177e4 LT |
10056 | } else { |
10057 | /* Accept one or more multicast(s). */ | |
22bedad3 | 10058 | struct netdev_hw_addr *ha; |
1da177e4 LT |
10059 | u32 mc_filter[4] = { 0, }; |
10060 | u32 regidx; | |
10061 | u32 bit; | |
10062 | u32 crc; | |
10063 | ||
22bedad3 JP |
10064 | netdev_for_each_mc_addr(ha, dev) { |
10065 | crc = calc_crc(ha->addr, ETH_ALEN); | |
1da177e4 LT |
10066 | bit = ~crc & 0x7f; |
10067 | regidx = (bit & 0x60) >> 5; | |
10068 | bit &= 0x1f; | |
10069 | mc_filter[regidx] |= (1 << bit); | |
10070 | } | |
10071 | ||
10072 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
10073 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
10074 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
10075 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
10076 | } | |
10077 | ||
10078 | if (rx_mode != tp->rx_mode) { | |
10079 | tp->rx_mode = rx_mode; | |
10080 | tw32_f(MAC_RX_MODE, rx_mode); | |
10081 | udelay(10); | |
10082 | } | |
10083 | } | |
10084 | ||
10085 | static void tg3_set_rx_mode(struct net_device *dev) | |
10086 | { | |
10087 | struct tg3 *tp = netdev_priv(dev); | |
10088 | ||
e75f7c90 MC |
10089 | if (!netif_running(dev)) |
10090 | return; | |
10091 | ||
f47c11ee | 10092 | tg3_full_lock(tp, 0); |
1da177e4 | 10093 | __tg3_set_rx_mode(dev); |
f47c11ee | 10094 | tg3_full_unlock(tp); |
1da177e4 LT |
10095 | } |
10096 | ||
1da177e4 LT |
10097 | static int tg3_get_regs_len(struct net_device *dev) |
10098 | { | |
97bd8e49 | 10099 | return TG3_REG_BLK_SIZE; |
1da177e4 LT |
10100 | } |
10101 | ||
10102 | static void tg3_get_regs(struct net_device *dev, | |
10103 | struct ethtool_regs *regs, void *_p) | |
10104 | { | |
1da177e4 | 10105 | struct tg3 *tp = netdev_priv(dev); |
1da177e4 LT |
10106 | |
10107 | regs->version = 0; | |
10108 | ||
97bd8e49 | 10109 | memset(_p, 0, TG3_REG_BLK_SIZE); |
1da177e4 | 10110 | |
80096068 | 10111 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10112 | return; |
10113 | ||
f47c11ee | 10114 | tg3_full_lock(tp, 0); |
1da177e4 | 10115 | |
97bd8e49 | 10116 | tg3_dump_legacy_regs(tp, (u32 *)_p); |
1da177e4 | 10117 | |
f47c11ee | 10118 | tg3_full_unlock(tp); |
1da177e4 LT |
10119 | } |
10120 | ||
10121 | static int tg3_get_eeprom_len(struct net_device *dev) | |
10122 | { | |
10123 | struct tg3 *tp = netdev_priv(dev); | |
10124 | ||
10125 | return tp->nvram_size; | |
10126 | } | |
10127 | ||
1da177e4 LT |
10128 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
10129 | { | |
10130 | struct tg3 *tp = netdev_priv(dev); | |
10131 | int ret; | |
10132 | u8 *pd; | |
b9fc7dc5 | 10133 | u32 i, offset, len, b_offset, b_count; |
a9dc529d | 10134 | __be32 val; |
1da177e4 | 10135 | |
63c3a66f | 10136 | if (tg3_flag(tp, NO_NVRAM)) |
df259d8c MC |
10137 | return -EINVAL; |
10138 | ||
80096068 | 10139 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10140 | return -EAGAIN; |
10141 | ||
1da177e4 LT |
10142 | offset = eeprom->offset; |
10143 | len = eeprom->len; | |
10144 | eeprom->len = 0; | |
10145 | ||
10146 | eeprom->magic = TG3_EEPROM_MAGIC; | |
10147 | ||
10148 | if (offset & 3) { | |
10149 | /* adjustments to start on required 4 byte boundary */ | |
10150 | b_offset = offset & 3; | |
10151 | b_count = 4 - b_offset; | |
10152 | if (b_count > len) { | |
10153 | /* i.e. offset=1 len=2 */ | |
10154 | b_count = len; | |
10155 | } | |
a9dc529d | 10156 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); |
1da177e4 LT |
10157 | if (ret) |
10158 | return ret; | |
be98da6a | 10159 | memcpy(data, ((char *)&val) + b_offset, b_count); |
1da177e4 LT |
10160 | len -= b_count; |
10161 | offset += b_count; | |
c6cdf436 | 10162 | eeprom->len += b_count; |
1da177e4 LT |
10163 | } |
10164 | ||
25985edc | 10165 | /* read bytes up to the last 4 byte boundary */ |
1da177e4 LT |
10166 | pd = &data[eeprom->len]; |
10167 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
a9dc529d | 10168 | ret = tg3_nvram_read_be32(tp, offset + i, &val); |
1da177e4 LT |
10169 | if (ret) { |
10170 | eeprom->len += i; | |
10171 | return ret; | |
10172 | } | |
1da177e4 LT |
10173 | memcpy(pd + i, &val, 4); |
10174 | } | |
10175 | eeprom->len += i; | |
10176 | ||
10177 | if (len & 3) { | |
10178 | /* read last bytes not ending on 4 byte boundary */ | |
10179 | pd = &data[eeprom->len]; | |
10180 | b_count = len & 3; | |
10181 | b_offset = offset + len - b_count; | |
a9dc529d | 10182 | ret = tg3_nvram_read_be32(tp, b_offset, &val); |
1da177e4 LT |
10183 | if (ret) |
10184 | return ret; | |
b9fc7dc5 | 10185 | memcpy(pd, &val, b_count); |
1da177e4 LT |
10186 | eeprom->len += b_count; |
10187 | } | |
10188 | return 0; | |
10189 | } | |
10190 | ||
6aa20a22 | 10191 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); |
1da177e4 LT |
10192 | |
10193 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
10194 | { | |
10195 | struct tg3 *tp = netdev_priv(dev); | |
10196 | int ret; | |
b9fc7dc5 | 10197 | u32 offset, len, b_offset, odd_len; |
1da177e4 | 10198 | u8 *buf; |
a9dc529d | 10199 | __be32 start, end; |
1da177e4 | 10200 | |
80096068 | 10201 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10202 | return -EAGAIN; |
10203 | ||
63c3a66f | 10204 | if (tg3_flag(tp, NO_NVRAM) || |
df259d8c | 10205 | eeprom->magic != TG3_EEPROM_MAGIC) |
1da177e4 LT |
10206 | return -EINVAL; |
10207 | ||
10208 | offset = eeprom->offset; | |
10209 | len = eeprom->len; | |
10210 | ||
10211 | if ((b_offset = (offset & 3))) { | |
10212 | /* adjustments to start on required 4 byte boundary */ | |
a9dc529d | 10213 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); |
1da177e4 LT |
10214 | if (ret) |
10215 | return ret; | |
1da177e4 LT |
10216 | len += b_offset; |
10217 | offset &= ~3; | |
1c8594b4 MC |
10218 | if (len < 4) |
10219 | len = 4; | |
1da177e4 LT |
10220 | } |
10221 | ||
10222 | odd_len = 0; | |
1c8594b4 | 10223 | if (len & 3) { |
1da177e4 LT |
10224 | /* adjustments to end on required 4 byte boundary */ |
10225 | odd_len = 1; | |
10226 | len = (len + 3) & ~3; | |
a9dc529d | 10227 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); |
1da177e4 LT |
10228 | if (ret) |
10229 | return ret; | |
1da177e4 LT |
10230 | } |
10231 | ||
10232 | buf = data; | |
10233 | if (b_offset || odd_len) { | |
10234 | buf = kmalloc(len, GFP_KERNEL); | |
ab0049b4 | 10235 | if (!buf) |
1da177e4 LT |
10236 | return -ENOMEM; |
10237 | if (b_offset) | |
10238 | memcpy(buf, &start, 4); | |
10239 | if (odd_len) | |
10240 | memcpy(buf+len-4, &end, 4); | |
10241 | memcpy(buf + b_offset, data, eeprom->len); | |
10242 | } | |
10243 | ||
10244 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
10245 | ||
10246 | if (buf != data) | |
10247 | kfree(buf); | |
10248 | ||
10249 | return ret; | |
10250 | } | |
10251 | ||
10252 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
10253 | { | |
b02fd9e3 MC |
10254 | struct tg3 *tp = netdev_priv(dev); |
10255 | ||
63c3a66f | 10256 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 10257 | struct phy_device *phydev; |
f07e9af3 | 10258 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10259 | return -EAGAIN; |
3f0e3ad7 MC |
10260 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10261 | return phy_ethtool_gset(phydev, cmd); | |
b02fd9e3 | 10262 | } |
6aa20a22 | 10263 | |
1da177e4 LT |
10264 | cmd->supported = (SUPPORTED_Autoneg); |
10265 | ||
f07e9af3 | 10266 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
10267 | cmd->supported |= (SUPPORTED_1000baseT_Half | |
10268 | SUPPORTED_1000baseT_Full); | |
10269 | ||
f07e9af3 | 10270 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
1da177e4 LT |
10271 | cmd->supported |= (SUPPORTED_100baseT_Half | |
10272 | SUPPORTED_100baseT_Full | | |
10273 | SUPPORTED_10baseT_Half | | |
10274 | SUPPORTED_10baseT_Full | | |
3bebab59 | 10275 | SUPPORTED_TP); |
ef348144 KK |
10276 | cmd->port = PORT_TP; |
10277 | } else { | |
1da177e4 | 10278 | cmd->supported |= SUPPORTED_FIBRE; |
ef348144 KK |
10279 | cmd->port = PORT_FIBRE; |
10280 | } | |
6aa20a22 | 10281 | |
1da177e4 | 10282 | cmd->advertising = tp->link_config.advertising; |
5bb09778 MC |
10283 | if (tg3_flag(tp, PAUSE_AUTONEG)) { |
10284 | if (tp->link_config.flowctrl & FLOW_CTRL_RX) { | |
10285 | if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
10286 | cmd->advertising |= ADVERTISED_Pause; | |
10287 | } else { | |
10288 | cmd->advertising |= ADVERTISED_Pause | | |
10289 | ADVERTISED_Asym_Pause; | |
10290 | } | |
10291 | } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
10292 | cmd->advertising |= ADVERTISED_Asym_Pause; | |
10293 | } | |
10294 | } | |
1da177e4 | 10295 | if (netif_running(dev)) { |
70739497 | 10296 | ethtool_cmd_speed_set(cmd, tp->link_config.active_speed); |
1da177e4 | 10297 | cmd->duplex = tp->link_config.active_duplex; |
64c22182 | 10298 | } else { |
70739497 | 10299 | ethtool_cmd_speed_set(cmd, SPEED_INVALID); |
64c22182 | 10300 | cmd->duplex = DUPLEX_INVALID; |
1da177e4 | 10301 | } |
882e9793 | 10302 | cmd->phy_address = tp->phy_addr; |
7e5856bd | 10303 | cmd->transceiver = XCVR_INTERNAL; |
1da177e4 LT |
10304 | cmd->autoneg = tp->link_config.autoneg; |
10305 | cmd->maxtxpkt = 0; | |
10306 | cmd->maxrxpkt = 0; | |
10307 | return 0; | |
10308 | } | |
6aa20a22 | 10309 | |
1da177e4 LT |
10310 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
10311 | { | |
10312 | struct tg3 *tp = netdev_priv(dev); | |
25db0338 | 10313 | u32 speed = ethtool_cmd_speed(cmd); |
6aa20a22 | 10314 | |
63c3a66f | 10315 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 10316 | struct phy_device *phydev; |
f07e9af3 | 10317 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10318 | return -EAGAIN; |
3f0e3ad7 MC |
10319 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10320 | return phy_ethtool_sset(phydev, cmd); | |
b02fd9e3 MC |
10321 | } |
10322 | ||
7e5856bd MC |
10323 | if (cmd->autoneg != AUTONEG_ENABLE && |
10324 | cmd->autoneg != AUTONEG_DISABLE) | |
37ff238d | 10325 | return -EINVAL; |
7e5856bd MC |
10326 | |
10327 | if (cmd->autoneg == AUTONEG_DISABLE && | |
10328 | cmd->duplex != DUPLEX_FULL && | |
10329 | cmd->duplex != DUPLEX_HALF) | |
37ff238d | 10330 | return -EINVAL; |
1da177e4 | 10331 | |
7e5856bd MC |
10332 | if (cmd->autoneg == AUTONEG_ENABLE) { |
10333 | u32 mask = ADVERTISED_Autoneg | | |
10334 | ADVERTISED_Pause | | |
10335 | ADVERTISED_Asym_Pause; | |
10336 | ||
f07e9af3 | 10337 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
7e5856bd MC |
10338 | mask |= ADVERTISED_1000baseT_Half | |
10339 | ADVERTISED_1000baseT_Full; | |
10340 | ||
f07e9af3 | 10341 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
7e5856bd MC |
10342 | mask |= ADVERTISED_100baseT_Half | |
10343 | ADVERTISED_100baseT_Full | | |
10344 | ADVERTISED_10baseT_Half | | |
10345 | ADVERTISED_10baseT_Full | | |
10346 | ADVERTISED_TP; | |
10347 | else | |
10348 | mask |= ADVERTISED_FIBRE; | |
10349 | ||
10350 | if (cmd->advertising & ~mask) | |
10351 | return -EINVAL; | |
10352 | ||
10353 | mask &= (ADVERTISED_1000baseT_Half | | |
10354 | ADVERTISED_1000baseT_Full | | |
10355 | ADVERTISED_100baseT_Half | | |
10356 | ADVERTISED_100baseT_Full | | |
10357 | ADVERTISED_10baseT_Half | | |
10358 | ADVERTISED_10baseT_Full); | |
10359 | ||
10360 | cmd->advertising &= mask; | |
10361 | } else { | |
f07e9af3 | 10362 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { |
25db0338 | 10363 | if (speed != SPEED_1000) |
7e5856bd MC |
10364 | return -EINVAL; |
10365 | ||
10366 | if (cmd->duplex != DUPLEX_FULL) | |
10367 | return -EINVAL; | |
10368 | } else { | |
25db0338 DD |
10369 | if (speed != SPEED_100 && |
10370 | speed != SPEED_10) | |
7e5856bd MC |
10371 | return -EINVAL; |
10372 | } | |
10373 | } | |
10374 | ||
f47c11ee | 10375 | tg3_full_lock(tp, 0); |
1da177e4 LT |
10376 | |
10377 | tp->link_config.autoneg = cmd->autoneg; | |
10378 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
405d8e5c AG |
10379 | tp->link_config.advertising = (cmd->advertising | |
10380 | ADVERTISED_Autoneg); | |
1da177e4 LT |
10381 | tp->link_config.speed = SPEED_INVALID; |
10382 | tp->link_config.duplex = DUPLEX_INVALID; | |
10383 | } else { | |
10384 | tp->link_config.advertising = 0; | |
25db0338 | 10385 | tp->link_config.speed = speed; |
1da177e4 | 10386 | tp->link_config.duplex = cmd->duplex; |
b02fd9e3 | 10387 | } |
6aa20a22 | 10388 | |
24fcad6b MC |
10389 | tp->link_config.orig_speed = tp->link_config.speed; |
10390 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
10391 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
10392 | ||
1da177e4 LT |
10393 | if (netif_running(dev)) |
10394 | tg3_setup_phy(tp, 1); | |
10395 | ||
f47c11ee | 10396 | tg3_full_unlock(tp); |
6aa20a22 | 10397 | |
1da177e4 LT |
10398 | return 0; |
10399 | } | |
6aa20a22 | 10400 | |
1da177e4 LT |
10401 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
10402 | { | |
10403 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10404 | |
68aad78c RJ |
10405 | strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); |
10406 | strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); | |
10407 | strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); | |
10408 | strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); | |
1da177e4 | 10409 | } |
6aa20a22 | 10410 | |
1da177e4 LT |
10411 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
10412 | { | |
10413 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10414 | |
63c3a66f | 10415 | if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) |
a85feb8c GZ |
10416 | wol->supported = WAKE_MAGIC; |
10417 | else | |
10418 | wol->supported = 0; | |
1da177e4 | 10419 | wol->wolopts = 0; |
63c3a66f | 10420 | if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) |
1da177e4 LT |
10421 | wol->wolopts = WAKE_MAGIC; |
10422 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
10423 | } | |
6aa20a22 | 10424 | |
1da177e4 LT |
10425 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
10426 | { | |
10427 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 10428 | struct device *dp = &tp->pdev->dev; |
6aa20a22 | 10429 | |
1da177e4 LT |
10430 | if (wol->wolopts & ~WAKE_MAGIC) |
10431 | return -EINVAL; | |
10432 | if ((wol->wolopts & WAKE_MAGIC) && | |
63c3a66f | 10433 | !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) |
1da177e4 | 10434 | return -EINVAL; |
6aa20a22 | 10435 | |
f2dc0d18 RW |
10436 | device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); |
10437 | ||
f47c11ee | 10438 | spin_lock_bh(&tp->lock); |
f2dc0d18 | 10439 | if (device_may_wakeup(dp)) |
63c3a66f | 10440 | tg3_flag_set(tp, WOL_ENABLE); |
f2dc0d18 | 10441 | else |
63c3a66f | 10442 | tg3_flag_clear(tp, WOL_ENABLE); |
f47c11ee | 10443 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 10444 | |
1da177e4 LT |
10445 | return 0; |
10446 | } | |
6aa20a22 | 10447 | |
1da177e4 LT |
10448 | static u32 tg3_get_msglevel(struct net_device *dev) |
10449 | { | |
10450 | struct tg3 *tp = netdev_priv(dev); | |
10451 | return tp->msg_enable; | |
10452 | } | |
6aa20a22 | 10453 | |
1da177e4 LT |
10454 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
10455 | { | |
10456 | struct tg3 *tp = netdev_priv(dev); | |
10457 | tp->msg_enable = value; | |
10458 | } | |
6aa20a22 | 10459 | |
1da177e4 LT |
10460 | static int tg3_nway_reset(struct net_device *dev) |
10461 | { | |
10462 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 10463 | int r; |
6aa20a22 | 10464 | |
1da177e4 LT |
10465 | if (!netif_running(dev)) |
10466 | return -EAGAIN; | |
10467 | ||
f07e9af3 | 10468 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
c94e3941 MC |
10469 | return -EINVAL; |
10470 | ||
63c3a66f | 10471 | if (tg3_flag(tp, USE_PHYLIB)) { |
f07e9af3 | 10472 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10473 | return -EAGAIN; |
3f0e3ad7 | 10474 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
10475 | } else { |
10476 | u32 bmcr; | |
10477 | ||
10478 | spin_lock_bh(&tp->lock); | |
10479 | r = -EINVAL; | |
10480 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
10481 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
10482 | ((bmcr & BMCR_ANENABLE) || | |
f07e9af3 | 10483 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { |
b02fd9e3 MC |
10484 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | |
10485 | BMCR_ANENABLE); | |
10486 | r = 0; | |
10487 | } | |
10488 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 10489 | } |
6aa20a22 | 10490 | |
1da177e4 LT |
10491 | return r; |
10492 | } | |
6aa20a22 | 10493 | |
1da177e4 LT |
10494 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10495 | { | |
10496 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10497 | |
2c49a44d | 10498 | ering->rx_max_pending = tp->rx_std_ring_mask; |
63c3a66f | 10499 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
2c49a44d | 10500 | ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; |
4f81c32b MC |
10501 | else |
10502 | ering->rx_jumbo_max_pending = 0; | |
10503 | ||
10504 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
1da177e4 LT |
10505 | |
10506 | ering->rx_pending = tp->rx_pending; | |
63c3a66f | 10507 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
4f81c32b MC |
10508 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; |
10509 | else | |
10510 | ering->rx_jumbo_pending = 0; | |
10511 | ||
f3f3f27e | 10512 | ering->tx_pending = tp->napi[0].tx_pending; |
1da177e4 | 10513 | } |
6aa20a22 | 10514 | |
1da177e4 LT |
10515 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10516 | { | |
10517 | struct tg3 *tp = netdev_priv(dev); | |
646c9edd | 10518 | int i, irq_sync = 0, err = 0; |
6aa20a22 | 10519 | |
2c49a44d MC |
10520 | if ((ering->rx_pending > tp->rx_std_ring_mask) || |
10521 | (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || | |
bc3a9254 MC |
10522 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || |
10523 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
63c3a66f | 10524 | (tg3_flag(tp, TSO_BUG) && |
bc3a9254 | 10525 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) |
1da177e4 | 10526 | return -EINVAL; |
6aa20a22 | 10527 | |
bbe832c0 | 10528 | if (netif_running(dev)) { |
b02fd9e3 | 10529 | tg3_phy_stop(tp); |
1da177e4 | 10530 | tg3_netif_stop(tp); |
bbe832c0 MC |
10531 | irq_sync = 1; |
10532 | } | |
1da177e4 | 10533 | |
bbe832c0 | 10534 | tg3_full_lock(tp, irq_sync); |
6aa20a22 | 10535 | |
1da177e4 LT |
10536 | tp->rx_pending = ering->rx_pending; |
10537 | ||
63c3a66f | 10538 | if (tg3_flag(tp, MAX_RXPEND_64) && |
1da177e4 LT |
10539 | tp->rx_pending > 63) |
10540 | tp->rx_pending = 63; | |
10541 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
646c9edd | 10542 | |
6fd45cb8 | 10543 | for (i = 0; i < tp->irq_max; i++) |
646c9edd | 10544 | tp->napi[i].tx_pending = ering->tx_pending; |
1da177e4 LT |
10545 | |
10546 | if (netif_running(dev)) { | |
944d980e | 10547 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
b9ec6c1b MC |
10548 | err = tg3_restart_hw(tp, 1); |
10549 | if (!err) | |
10550 | tg3_netif_start(tp); | |
1da177e4 LT |
10551 | } |
10552 | ||
f47c11ee | 10553 | tg3_full_unlock(tp); |
6aa20a22 | 10554 | |
b02fd9e3 MC |
10555 | if (irq_sync && !err) |
10556 | tg3_phy_start(tp); | |
10557 | ||
b9ec6c1b | 10558 | return err; |
1da177e4 | 10559 | } |
6aa20a22 | 10560 | |
1da177e4 LT |
10561 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10562 | { | |
10563 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10564 | |
63c3a66f | 10565 | epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); |
8d018621 | 10566 | |
e18ce346 | 10567 | if (tp->link_config.active_flowctrl & FLOW_CTRL_RX) |
8d018621 MC |
10568 | epause->rx_pause = 1; |
10569 | else | |
10570 | epause->rx_pause = 0; | |
10571 | ||
e18ce346 | 10572 | if (tp->link_config.active_flowctrl & FLOW_CTRL_TX) |
8d018621 MC |
10573 | epause->tx_pause = 1; |
10574 | else | |
10575 | epause->tx_pause = 0; | |
1da177e4 | 10576 | } |
6aa20a22 | 10577 | |
1da177e4 LT |
10578 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10579 | { | |
10580 | struct tg3 *tp = netdev_priv(dev); | |
b02fd9e3 | 10581 | int err = 0; |
6aa20a22 | 10582 | |
63c3a66f | 10583 | if (tg3_flag(tp, USE_PHYLIB)) { |
2712168f MC |
10584 | u32 newadv; |
10585 | struct phy_device *phydev; | |
1da177e4 | 10586 | |
2712168f | 10587 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
f47c11ee | 10588 | |
2712168f MC |
10589 | if (!(phydev->supported & SUPPORTED_Pause) || |
10590 | (!(phydev->supported & SUPPORTED_Asym_Pause) && | |
2259dca3 | 10591 | (epause->rx_pause != epause->tx_pause))) |
2712168f | 10592 | return -EINVAL; |
1da177e4 | 10593 | |
2712168f MC |
10594 | tp->link_config.flowctrl = 0; |
10595 | if (epause->rx_pause) { | |
10596 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
10597 | ||
10598 | if (epause->tx_pause) { | |
10599 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10600 | newadv = ADVERTISED_Pause; | |
b02fd9e3 | 10601 | } else |
2712168f MC |
10602 | newadv = ADVERTISED_Pause | |
10603 | ADVERTISED_Asym_Pause; | |
10604 | } else if (epause->tx_pause) { | |
10605 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10606 | newadv = ADVERTISED_Asym_Pause; | |
10607 | } else | |
10608 | newadv = 0; | |
10609 | ||
10610 | if (epause->autoneg) | |
63c3a66f | 10611 | tg3_flag_set(tp, PAUSE_AUTONEG); |
2712168f | 10612 | else |
63c3a66f | 10613 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
2712168f | 10614 | |
f07e9af3 | 10615 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
2712168f MC |
10616 | u32 oldadv = phydev->advertising & |
10617 | (ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
10618 | if (oldadv != newadv) { | |
10619 | phydev->advertising &= | |
10620 | ~(ADVERTISED_Pause | | |
10621 | ADVERTISED_Asym_Pause); | |
10622 | phydev->advertising |= newadv; | |
10623 | if (phydev->autoneg) { | |
10624 | /* | |
10625 | * Always renegotiate the link to | |
10626 | * inform our link partner of our | |
10627 | * flow control settings, even if the | |
10628 | * flow control is forced. Let | |
10629 | * tg3_adjust_link() do the final | |
10630 | * flow control setup. | |
10631 | */ | |
10632 | return phy_start_aneg(phydev); | |
b02fd9e3 | 10633 | } |
b02fd9e3 | 10634 | } |
b02fd9e3 | 10635 | |
2712168f | 10636 | if (!epause->autoneg) |
b02fd9e3 | 10637 | tg3_setup_flow_control(tp, 0, 0); |
2712168f MC |
10638 | } else { |
10639 | tp->link_config.orig_advertising &= | |
10640 | ~(ADVERTISED_Pause | | |
10641 | ADVERTISED_Asym_Pause); | |
10642 | tp->link_config.orig_advertising |= newadv; | |
b02fd9e3 MC |
10643 | } |
10644 | } else { | |
10645 | int irq_sync = 0; | |
10646 | ||
10647 | if (netif_running(dev)) { | |
10648 | tg3_netif_stop(tp); | |
10649 | irq_sync = 1; | |
10650 | } | |
10651 | ||
10652 | tg3_full_lock(tp, irq_sync); | |
10653 | ||
10654 | if (epause->autoneg) | |
63c3a66f | 10655 | tg3_flag_set(tp, PAUSE_AUTONEG); |
b02fd9e3 | 10656 | else |
63c3a66f | 10657 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
b02fd9e3 | 10658 | if (epause->rx_pause) |
e18ce346 | 10659 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 10660 | else |
e18ce346 | 10661 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
b02fd9e3 | 10662 | if (epause->tx_pause) |
e18ce346 | 10663 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 10664 | else |
e18ce346 | 10665 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
10666 | |
10667 | if (netif_running(dev)) { | |
10668 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
10669 | err = tg3_restart_hw(tp, 1); | |
10670 | if (!err) | |
10671 | tg3_netif_start(tp); | |
10672 | } | |
10673 | ||
10674 | tg3_full_unlock(tp); | |
10675 | } | |
6aa20a22 | 10676 | |
b9ec6c1b | 10677 | return err; |
1da177e4 | 10678 | } |
6aa20a22 | 10679 | |
de6f31eb | 10680 | static int tg3_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 10681 | { |
b9f2c044 JG |
10682 | switch (sset) { |
10683 | case ETH_SS_TEST: | |
10684 | return TG3_NUM_TEST; | |
10685 | case ETH_SS_STATS: | |
10686 | return TG3_NUM_STATS; | |
10687 | default: | |
10688 | return -EOPNOTSUPP; | |
10689 | } | |
4cafd3f5 MC |
10690 | } |
10691 | ||
de6f31eb | 10692 | static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
1da177e4 LT |
10693 | { |
10694 | switch (stringset) { | |
10695 | case ETH_SS_STATS: | |
10696 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
10697 | break; | |
4cafd3f5 MC |
10698 | case ETH_SS_TEST: |
10699 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
10700 | break; | |
1da177e4 LT |
10701 | default: |
10702 | WARN_ON(1); /* we need a WARN() */ | |
10703 | break; | |
10704 | } | |
10705 | } | |
10706 | ||
81b8709c | 10707 | static int tg3_set_phys_id(struct net_device *dev, |
10708 | enum ethtool_phys_id_state state) | |
4009a93d MC |
10709 | { |
10710 | struct tg3 *tp = netdev_priv(dev); | |
4009a93d MC |
10711 | |
10712 | if (!netif_running(tp->dev)) | |
10713 | return -EAGAIN; | |
10714 | ||
81b8709c | 10715 | switch (state) { |
10716 | case ETHTOOL_ID_ACTIVE: | |
fce55922 | 10717 | return 1; /* cycle on/off once per second */ |
4009a93d | 10718 | |
81b8709c | 10719 | case ETHTOOL_ID_ON: |
10720 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10721 | LED_CTRL_1000MBPS_ON | | |
10722 | LED_CTRL_100MBPS_ON | | |
10723 | LED_CTRL_10MBPS_ON | | |
10724 | LED_CTRL_TRAFFIC_OVERRIDE | | |
10725 | LED_CTRL_TRAFFIC_BLINK | | |
10726 | LED_CTRL_TRAFFIC_LED); | |
10727 | break; | |
6aa20a22 | 10728 | |
81b8709c | 10729 | case ETHTOOL_ID_OFF: |
10730 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10731 | LED_CTRL_TRAFFIC_OVERRIDE); | |
10732 | break; | |
4009a93d | 10733 | |
81b8709c | 10734 | case ETHTOOL_ID_INACTIVE: |
10735 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
10736 | break; | |
4009a93d | 10737 | } |
81b8709c | 10738 | |
4009a93d MC |
10739 | return 0; |
10740 | } | |
10741 | ||
de6f31eb | 10742 | static void tg3_get_ethtool_stats(struct net_device *dev, |
1da177e4 LT |
10743 | struct ethtool_stats *estats, u64 *tmp_stats) |
10744 | { | |
10745 | struct tg3 *tp = netdev_priv(dev); | |
10746 | memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats)); | |
10747 | } | |
10748 | ||
535a490e | 10749 | static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen) |
c3e94500 MC |
10750 | { |
10751 | int i; | |
10752 | __be32 *buf; | |
10753 | u32 offset = 0, len = 0; | |
10754 | u32 magic, val; | |
10755 | ||
63c3a66f | 10756 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) |
c3e94500 MC |
10757 | return NULL; |
10758 | ||
10759 | if (magic == TG3_EEPROM_MAGIC) { | |
10760 | for (offset = TG3_NVM_DIR_START; | |
10761 | offset < TG3_NVM_DIR_END; | |
10762 | offset += TG3_NVM_DIRENT_SIZE) { | |
10763 | if (tg3_nvram_read(tp, offset, &val)) | |
10764 | return NULL; | |
10765 | ||
10766 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == | |
10767 | TG3_NVM_DIRTYPE_EXTVPD) | |
10768 | break; | |
10769 | } | |
10770 | ||
10771 | if (offset != TG3_NVM_DIR_END) { | |
10772 | len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4; | |
10773 | if (tg3_nvram_read(tp, offset + 4, &offset)) | |
10774 | return NULL; | |
10775 | ||
10776 | offset = tg3_nvram_logical_addr(tp, offset); | |
10777 | } | |
10778 | } | |
10779 | ||
10780 | if (!offset || !len) { | |
10781 | offset = TG3_NVM_VPD_OFF; | |
10782 | len = TG3_NVM_VPD_LEN; | |
10783 | } | |
10784 | ||
10785 | buf = kmalloc(len, GFP_KERNEL); | |
10786 | if (buf == NULL) | |
10787 | return NULL; | |
10788 | ||
10789 | if (magic == TG3_EEPROM_MAGIC) { | |
10790 | for (i = 0; i < len; i += 4) { | |
10791 | /* The data is in little-endian format in NVRAM. | |
10792 | * Use the big-endian read routines to preserve | |
10793 | * the byte order as it exists in NVRAM. | |
10794 | */ | |
10795 | if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) | |
10796 | goto error; | |
10797 | } | |
10798 | } else { | |
10799 | u8 *ptr; | |
10800 | ssize_t cnt; | |
10801 | unsigned int pos = 0; | |
10802 | ||
10803 | ptr = (u8 *)&buf[0]; | |
10804 | for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) { | |
10805 | cnt = pci_read_vpd(tp->pdev, pos, | |
10806 | len - pos, ptr); | |
10807 | if (cnt == -ETIMEDOUT || cnt == -EINTR) | |
10808 | cnt = 0; | |
10809 | else if (cnt < 0) | |
10810 | goto error; | |
10811 | } | |
10812 | if (pos != len) | |
10813 | goto error; | |
10814 | } | |
10815 | ||
535a490e MC |
10816 | *vpdlen = len; |
10817 | ||
c3e94500 MC |
10818 | return buf; |
10819 | ||
10820 | error: | |
10821 | kfree(buf); | |
10822 | return NULL; | |
10823 | } | |
10824 | ||
566f86ad | 10825 | #define NVRAM_TEST_SIZE 0x100 |
a5767dec MC |
10826 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
10827 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
10828 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
727a6d9f MC |
10829 | #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20 |
10830 | #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24 | |
bda18faf | 10831 | #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50 |
b16250e3 MC |
10832 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
10833 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
566f86ad MC |
10834 | |
10835 | static int tg3_test_nvram(struct tg3 *tp) | |
10836 | { | |
535a490e | 10837 | u32 csum, magic, len; |
a9dc529d | 10838 | __be32 *buf; |
ab0049b4 | 10839 | int i, j, k, err = 0, size; |
566f86ad | 10840 | |
63c3a66f | 10841 | if (tg3_flag(tp, NO_NVRAM)) |
df259d8c MC |
10842 | return 0; |
10843 | ||
e4f34110 | 10844 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1b27777a MC |
10845 | return -EIO; |
10846 | ||
1b27777a MC |
10847 | if (magic == TG3_EEPROM_MAGIC) |
10848 | size = NVRAM_TEST_SIZE; | |
b16250e3 | 10849 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
a5767dec MC |
10850 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
10851 | TG3_EEPROM_SB_FORMAT_1) { | |
10852 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
10853 | case TG3_EEPROM_SB_REVISION_0: | |
10854 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
10855 | break; | |
10856 | case TG3_EEPROM_SB_REVISION_2: | |
10857 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
10858 | break; | |
10859 | case TG3_EEPROM_SB_REVISION_3: | |
10860 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
10861 | break; | |
727a6d9f MC |
10862 | case TG3_EEPROM_SB_REVISION_4: |
10863 | size = NVRAM_SELFBOOT_FORMAT1_4_SIZE; | |
10864 | break; | |
10865 | case TG3_EEPROM_SB_REVISION_5: | |
10866 | size = NVRAM_SELFBOOT_FORMAT1_5_SIZE; | |
10867 | break; | |
10868 | case TG3_EEPROM_SB_REVISION_6: | |
10869 | size = NVRAM_SELFBOOT_FORMAT1_6_SIZE; | |
10870 | break; | |
a5767dec | 10871 | default: |
727a6d9f | 10872 | return -EIO; |
a5767dec MC |
10873 | } |
10874 | } else | |
1b27777a | 10875 | return 0; |
b16250e3 MC |
10876 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
10877 | size = NVRAM_SELFBOOT_HW_SIZE; | |
10878 | else | |
1b27777a MC |
10879 | return -EIO; |
10880 | ||
10881 | buf = kmalloc(size, GFP_KERNEL); | |
566f86ad MC |
10882 | if (buf == NULL) |
10883 | return -ENOMEM; | |
10884 | ||
1b27777a MC |
10885 | err = -EIO; |
10886 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
a9dc529d MC |
10887 | err = tg3_nvram_read_be32(tp, i, &buf[j]); |
10888 | if (err) | |
566f86ad | 10889 | break; |
566f86ad | 10890 | } |
1b27777a | 10891 | if (i < size) |
566f86ad MC |
10892 | goto out; |
10893 | ||
1b27777a | 10894 | /* Selfboot format */ |
a9dc529d | 10895 | magic = be32_to_cpu(buf[0]); |
b9fc7dc5 | 10896 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == |
b16250e3 | 10897 | TG3_EEPROM_MAGIC_FW) { |
1b27777a MC |
10898 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
10899 | ||
b9fc7dc5 | 10900 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == |
a5767dec MC |
10901 | TG3_EEPROM_SB_REVISION_2) { |
10902 | /* For rev 2, the csum doesn't include the MBA. */ | |
10903 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
10904 | csum8 += buf8[i]; | |
10905 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
10906 | csum8 += buf8[i]; | |
10907 | } else { | |
10908 | for (i = 0; i < size; i++) | |
10909 | csum8 += buf8[i]; | |
10910 | } | |
1b27777a | 10911 | |
ad96b485 AB |
10912 | if (csum8 == 0) { |
10913 | err = 0; | |
10914 | goto out; | |
10915 | } | |
10916 | ||
10917 | err = -EIO; | |
10918 | goto out; | |
1b27777a | 10919 | } |
566f86ad | 10920 | |
b9fc7dc5 | 10921 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == |
b16250e3 MC |
10922 | TG3_EEPROM_MAGIC_HW) { |
10923 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
a9dc529d | 10924 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; |
b16250e3 | 10925 | u8 *buf8 = (u8 *) buf; |
b16250e3 MC |
10926 | |
10927 | /* Separate the parity bits and the data bytes. */ | |
10928 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
10929 | if ((i == 0) || (i == 8)) { | |
10930 | int l; | |
10931 | u8 msk; | |
10932 | ||
10933 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
10934 | parity[k++] = buf8[i] & msk; | |
10935 | i++; | |
859a5887 | 10936 | } else if (i == 16) { |
b16250e3 MC |
10937 | int l; |
10938 | u8 msk; | |
10939 | ||
10940 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
10941 | parity[k++] = buf8[i] & msk; | |
10942 | i++; | |
10943 | ||
10944 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
10945 | parity[k++] = buf8[i] & msk; | |
10946 | i++; | |
10947 | } | |
10948 | data[j++] = buf8[i]; | |
10949 | } | |
10950 | ||
10951 | err = -EIO; | |
10952 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
10953 | u8 hw8 = hweight8(data[i]); | |
10954 | ||
10955 | if ((hw8 & 0x1) && parity[i]) | |
10956 | goto out; | |
10957 | else if (!(hw8 & 0x1) && !parity[i]) | |
10958 | goto out; | |
10959 | } | |
10960 | err = 0; | |
10961 | goto out; | |
10962 | } | |
10963 | ||
01c3a392 MC |
10964 | err = -EIO; |
10965 | ||
566f86ad MC |
10966 | /* Bootstrap checksum at offset 0x10 */ |
10967 | csum = calc_crc((unsigned char *) buf, 0x10); | |
01c3a392 | 10968 | if (csum != le32_to_cpu(buf[0x10/4])) |
566f86ad MC |
10969 | goto out; |
10970 | ||
10971 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
10972 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
01c3a392 | 10973 | if (csum != le32_to_cpu(buf[0xfc/4])) |
a9dc529d | 10974 | goto out; |
566f86ad | 10975 | |
c3e94500 MC |
10976 | kfree(buf); |
10977 | ||
535a490e | 10978 | buf = tg3_vpd_readblock(tp, &len); |
c3e94500 MC |
10979 | if (!buf) |
10980 | return -ENOMEM; | |
d4894f3e | 10981 | |
535a490e | 10982 | i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA); |
d4894f3e MC |
10983 | if (i > 0) { |
10984 | j = pci_vpd_lrdt_size(&((u8 *)buf)[i]); | |
10985 | if (j < 0) | |
10986 | goto out; | |
10987 | ||
535a490e | 10988 | if (i + PCI_VPD_LRDT_TAG_SIZE + j > len) |
d4894f3e MC |
10989 | goto out; |
10990 | ||
10991 | i += PCI_VPD_LRDT_TAG_SIZE; | |
10992 | j = pci_vpd_find_info_keyword((u8 *)buf, i, j, | |
10993 | PCI_VPD_RO_KEYWORD_CHKSUM); | |
10994 | if (j > 0) { | |
10995 | u8 csum8 = 0; | |
10996 | ||
10997 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
10998 | ||
10999 | for (i = 0; i <= j; i++) | |
11000 | csum8 += ((u8 *)buf)[i]; | |
11001 | ||
11002 | if (csum8) | |
11003 | goto out; | |
11004 | } | |
11005 | } | |
11006 | ||
566f86ad MC |
11007 | err = 0; |
11008 | ||
11009 | out: | |
11010 | kfree(buf); | |
11011 | return err; | |
11012 | } | |
11013 | ||
ca43007a MC |
11014 | #define TG3_SERDES_TIMEOUT_SEC 2 |
11015 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
11016 | ||
11017 | static int tg3_test_link(struct tg3 *tp) | |
11018 | { | |
11019 | int i, max; | |
11020 | ||
11021 | if (!netif_running(tp->dev)) | |
11022 | return -ENODEV; | |
11023 | ||
f07e9af3 | 11024 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
ca43007a MC |
11025 | max = TG3_SERDES_TIMEOUT_SEC; |
11026 | else | |
11027 | max = TG3_COPPER_TIMEOUT_SEC; | |
11028 | ||
11029 | for (i = 0; i < max; i++) { | |
11030 | if (netif_carrier_ok(tp->dev)) | |
11031 | return 0; | |
11032 | ||
11033 | if (msleep_interruptible(1000)) | |
11034 | break; | |
11035 | } | |
11036 | ||
11037 | return -EIO; | |
11038 | } | |
11039 | ||
a71116d1 | 11040 | /* Only test the commonly used registers */ |
30ca3e37 | 11041 | static int tg3_test_registers(struct tg3 *tp) |
a71116d1 | 11042 | { |
b16250e3 | 11043 | int i, is_5705, is_5750; |
a71116d1 MC |
11044 | u32 offset, read_mask, write_mask, val, save_val, read_val; |
11045 | static struct { | |
11046 | u16 offset; | |
11047 | u16 flags; | |
11048 | #define TG3_FL_5705 0x1 | |
11049 | #define TG3_FL_NOT_5705 0x2 | |
11050 | #define TG3_FL_NOT_5788 0x4 | |
b16250e3 | 11051 | #define TG3_FL_NOT_5750 0x8 |
a71116d1 MC |
11052 | u32 read_mask; |
11053 | u32 write_mask; | |
11054 | } reg_tbl[] = { | |
11055 | /* MAC Control Registers */ | |
11056 | { MAC_MODE, TG3_FL_NOT_5705, | |
11057 | 0x00000000, 0x00ef6f8c }, | |
11058 | { MAC_MODE, TG3_FL_5705, | |
11059 | 0x00000000, 0x01ef6b8c }, | |
11060 | { MAC_STATUS, TG3_FL_NOT_5705, | |
11061 | 0x03800107, 0x00000000 }, | |
11062 | { MAC_STATUS, TG3_FL_5705, | |
11063 | 0x03800100, 0x00000000 }, | |
11064 | { MAC_ADDR_0_HIGH, 0x0000, | |
11065 | 0x00000000, 0x0000ffff }, | |
11066 | { MAC_ADDR_0_LOW, 0x0000, | |
c6cdf436 | 11067 | 0x00000000, 0xffffffff }, |
a71116d1 MC |
11068 | { MAC_RX_MTU_SIZE, 0x0000, |
11069 | 0x00000000, 0x0000ffff }, | |
11070 | { MAC_TX_MODE, 0x0000, | |
11071 | 0x00000000, 0x00000070 }, | |
11072 | { MAC_TX_LENGTHS, 0x0000, | |
11073 | 0x00000000, 0x00003fff }, | |
11074 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
11075 | 0x00000000, 0x000007fc }, | |
11076 | { MAC_RX_MODE, TG3_FL_5705, | |
11077 | 0x00000000, 0x000007dc }, | |
11078 | { MAC_HASH_REG_0, 0x0000, | |
11079 | 0x00000000, 0xffffffff }, | |
11080 | { MAC_HASH_REG_1, 0x0000, | |
11081 | 0x00000000, 0xffffffff }, | |
11082 | { MAC_HASH_REG_2, 0x0000, | |
11083 | 0x00000000, 0xffffffff }, | |
11084 | { MAC_HASH_REG_3, 0x0000, | |
11085 | 0x00000000, 0xffffffff }, | |
11086 | ||
11087 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
11088 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
11089 | 0x00000000, 0xffffffff }, | |
11090 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
11091 | 0x00000000, 0xffffffff }, | |
11092 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
11093 | 0x00000000, 0x00000003 }, | |
11094 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
11095 | 0x00000000, 0xffffffff }, | |
11096 | { RCVDBDI_STD_BD+0, 0x0000, | |
11097 | 0x00000000, 0xffffffff }, | |
11098 | { RCVDBDI_STD_BD+4, 0x0000, | |
11099 | 0x00000000, 0xffffffff }, | |
11100 | { RCVDBDI_STD_BD+8, 0x0000, | |
11101 | 0x00000000, 0xffff0002 }, | |
11102 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
11103 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 11104 | |
a71116d1 MC |
11105 | /* Receive BD Initiator Control Registers. */ |
11106 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
11107 | 0x00000000, 0xffffffff }, | |
11108 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
11109 | 0x00000000, 0x000003ff }, | |
11110 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
11111 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 11112 | |
a71116d1 MC |
11113 | /* Host Coalescing Control Registers. */ |
11114 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
11115 | 0x00000000, 0x00000004 }, | |
11116 | { HOSTCC_MODE, TG3_FL_5705, | |
11117 | 0x00000000, 0x000000f6 }, | |
11118 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
11119 | 0x00000000, 0xffffffff }, | |
11120 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
11121 | 0x00000000, 0x000003ff }, | |
11122 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
11123 | 0x00000000, 0xffffffff }, | |
11124 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
11125 | 0x00000000, 0x000003ff }, | |
11126 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
11127 | 0x00000000, 0xffffffff }, | |
11128 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11129 | 0x00000000, 0x000000ff }, | |
11130 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
11131 | 0x00000000, 0xffffffff }, | |
11132 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11133 | 0x00000000, 0x000000ff }, | |
11134 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
11135 | 0x00000000, 0xffffffff }, | |
11136 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
11137 | 0x00000000, 0xffffffff }, | |
11138 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
11139 | 0x00000000, 0xffffffff }, | |
11140 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11141 | 0x00000000, 0x000000ff }, | |
11142 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
11143 | 0x00000000, 0xffffffff }, | |
11144 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11145 | 0x00000000, 0x000000ff }, | |
11146 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
11147 | 0x00000000, 0xffffffff }, | |
11148 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
11149 | 0x00000000, 0xffffffff }, | |
11150 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
11151 | 0x00000000, 0xffffffff }, | |
11152 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
11153 | 0x00000000, 0xffffffff }, | |
11154 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
11155 | 0x00000000, 0xffffffff }, | |
11156 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
11157 | 0xffffffff, 0x00000000 }, | |
11158 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
11159 | 0xffffffff, 0x00000000 }, | |
11160 | ||
11161 | /* Buffer Manager Control Registers. */ | |
b16250e3 | 11162 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, |
a71116d1 | 11163 | 0x00000000, 0x007fff80 }, |
b16250e3 | 11164 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, |
a71116d1 MC |
11165 | 0x00000000, 0x007fffff }, |
11166 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
11167 | 0x00000000, 0x0000003f }, | |
11168 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
11169 | 0x00000000, 0x000001ff }, | |
11170 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
11171 | 0x00000000, 0x000001ff }, | |
11172 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
11173 | 0xffffffff, 0x00000000 }, | |
11174 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
11175 | 0xffffffff, 0x00000000 }, | |
6aa20a22 | 11176 | |
a71116d1 MC |
11177 | /* Mailbox Registers */ |
11178 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
11179 | 0x00000000, 0x000001ff }, | |
11180 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
11181 | 0x00000000, 0x000001ff }, | |
11182 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
11183 | 0x00000000, 0x000007ff }, | |
11184 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
11185 | 0x00000000, 0x000001ff }, | |
11186 | ||
11187 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
11188 | }; | |
11189 | ||
b16250e3 | 11190 | is_5705 = is_5750 = 0; |
63c3a66f | 11191 | if (tg3_flag(tp, 5705_PLUS)) { |
a71116d1 | 11192 | is_5705 = 1; |
63c3a66f | 11193 | if (tg3_flag(tp, 5750_PLUS)) |
b16250e3 MC |
11194 | is_5750 = 1; |
11195 | } | |
a71116d1 MC |
11196 | |
11197 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
11198 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
11199 | continue; | |
11200 | ||
11201 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
11202 | continue; | |
11203 | ||
63c3a66f | 11204 | if (tg3_flag(tp, IS_5788) && |
a71116d1 MC |
11205 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) |
11206 | continue; | |
11207 | ||
b16250e3 MC |
11208 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) |
11209 | continue; | |
11210 | ||
a71116d1 MC |
11211 | offset = (u32) reg_tbl[i].offset; |
11212 | read_mask = reg_tbl[i].read_mask; | |
11213 | write_mask = reg_tbl[i].write_mask; | |
11214 | ||
11215 | /* Save the original register content */ | |
11216 | save_val = tr32(offset); | |
11217 | ||
11218 | /* Determine the read-only value. */ | |
11219 | read_val = save_val & read_mask; | |
11220 | ||
11221 | /* Write zero to the register, then make sure the read-only bits | |
11222 | * are not changed and the read/write bits are all zeros. | |
11223 | */ | |
11224 | tw32(offset, 0); | |
11225 | ||
11226 | val = tr32(offset); | |
11227 | ||
11228 | /* Test the read-only and read/write bits. */ | |
11229 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
11230 | goto out; | |
11231 | ||
11232 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
11233 | * make sure the read-only bits are not changed and the | |
11234 | * read/write bits are all ones. | |
11235 | */ | |
11236 | tw32(offset, read_mask | write_mask); | |
11237 | ||
11238 | val = tr32(offset); | |
11239 | ||
11240 | /* Test the read-only bits. */ | |
11241 | if ((val & read_mask) != read_val) | |
11242 | goto out; | |
11243 | ||
11244 | /* Test the read/write bits. */ | |
11245 | if ((val & write_mask) != write_mask) | |
11246 | goto out; | |
11247 | ||
11248 | tw32(offset, save_val); | |
11249 | } | |
11250 | ||
11251 | return 0; | |
11252 | ||
11253 | out: | |
9f88f29f | 11254 | if (netif_msg_hw(tp)) |
2445e461 MC |
11255 | netdev_err(tp->dev, |
11256 | "Register test failed at offset %x\n", offset); | |
a71116d1 MC |
11257 | tw32(offset, save_val); |
11258 | return -EIO; | |
11259 | } | |
11260 | ||
7942e1db MC |
11261 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) |
11262 | { | |
f71e1309 | 11263 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; |
7942e1db MC |
11264 | int i; |
11265 | u32 j; | |
11266 | ||
e9edda69 | 11267 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { |
7942e1db MC |
11268 | for (j = 0; j < len; j += 4) { |
11269 | u32 val; | |
11270 | ||
11271 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
11272 | tg3_read_mem(tp, offset + j, &val); | |
11273 | if (val != test_pattern[i]) | |
11274 | return -EIO; | |
11275 | } | |
11276 | } | |
11277 | return 0; | |
11278 | } | |
11279 | ||
11280 | static int tg3_test_memory(struct tg3 *tp) | |
11281 | { | |
11282 | static struct mem_entry { | |
11283 | u32 offset; | |
11284 | u32 len; | |
11285 | } mem_tbl_570x[] = { | |
38690194 | 11286 | { 0x00000000, 0x00b50}, |
7942e1db MC |
11287 | { 0x00002000, 0x1c000}, |
11288 | { 0xffffffff, 0x00000} | |
11289 | }, mem_tbl_5705[] = { | |
11290 | { 0x00000100, 0x0000c}, | |
11291 | { 0x00000200, 0x00008}, | |
7942e1db MC |
11292 | { 0x00004000, 0x00800}, |
11293 | { 0x00006000, 0x01000}, | |
11294 | { 0x00008000, 0x02000}, | |
11295 | { 0x00010000, 0x0e000}, | |
11296 | { 0xffffffff, 0x00000} | |
79f4d13a MC |
11297 | }, mem_tbl_5755[] = { |
11298 | { 0x00000200, 0x00008}, | |
11299 | { 0x00004000, 0x00800}, | |
11300 | { 0x00006000, 0x00800}, | |
11301 | { 0x00008000, 0x02000}, | |
11302 | { 0x00010000, 0x0c000}, | |
11303 | { 0xffffffff, 0x00000} | |
b16250e3 MC |
11304 | }, mem_tbl_5906[] = { |
11305 | { 0x00000200, 0x00008}, | |
11306 | { 0x00004000, 0x00400}, | |
11307 | { 0x00006000, 0x00400}, | |
11308 | { 0x00008000, 0x01000}, | |
11309 | { 0x00010000, 0x01000}, | |
11310 | { 0xffffffff, 0x00000} | |
8b5a6c42 MC |
11311 | }, mem_tbl_5717[] = { |
11312 | { 0x00000200, 0x00008}, | |
11313 | { 0x00010000, 0x0a000}, | |
11314 | { 0x00020000, 0x13c00}, | |
11315 | { 0xffffffff, 0x00000} | |
11316 | }, mem_tbl_57765[] = { | |
11317 | { 0x00000200, 0x00008}, | |
11318 | { 0x00004000, 0x00800}, | |
11319 | { 0x00006000, 0x09800}, | |
11320 | { 0x00010000, 0x0a000}, | |
11321 | { 0xffffffff, 0x00000} | |
7942e1db MC |
11322 | }; |
11323 | struct mem_entry *mem_tbl; | |
11324 | int err = 0; | |
11325 | int i; | |
11326 | ||
63c3a66f | 11327 | if (tg3_flag(tp, 5717_PLUS)) |
8b5a6c42 MC |
11328 | mem_tbl = mem_tbl_5717; |
11329 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
11330 | mem_tbl = mem_tbl_57765; | |
63c3a66f | 11331 | else if (tg3_flag(tp, 5755_PLUS)) |
321d32a0 MC |
11332 | mem_tbl = mem_tbl_5755; |
11333 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
11334 | mem_tbl = mem_tbl_5906; | |
63c3a66f | 11335 | else if (tg3_flag(tp, 5705_PLUS)) |
321d32a0 MC |
11336 | mem_tbl = mem_tbl_5705; |
11337 | else | |
7942e1db MC |
11338 | mem_tbl = mem_tbl_570x; |
11339 | ||
11340 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
be98da6a MC |
11341 | err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); |
11342 | if (err) | |
7942e1db MC |
11343 | break; |
11344 | } | |
6aa20a22 | 11345 | |
7942e1db MC |
11346 | return err; |
11347 | } | |
11348 | ||
bb158d69 MC |
11349 | #define TG3_TSO_MSS 500 |
11350 | ||
11351 | #define TG3_TSO_IP_HDR_LEN 20 | |
11352 | #define TG3_TSO_TCP_HDR_LEN 20 | |
11353 | #define TG3_TSO_TCP_OPT_LEN 12 | |
11354 | ||
11355 | static const u8 tg3_tso_header[] = { | |
11356 | 0x08, 0x00, | |
11357 | 0x45, 0x00, 0x00, 0x00, | |
11358 | 0x00, 0x00, 0x40, 0x00, | |
11359 | 0x40, 0x06, 0x00, 0x00, | |
11360 | 0x0a, 0x00, 0x00, 0x01, | |
11361 | 0x0a, 0x00, 0x00, 0x02, | |
11362 | 0x0d, 0x00, 0xe0, 0x00, | |
11363 | 0x00, 0x00, 0x01, 0x00, | |
11364 | 0x00, 0x00, 0x02, 0x00, | |
11365 | 0x80, 0x10, 0x10, 0x00, | |
11366 | 0x14, 0x09, 0x00, 0x00, | |
11367 | 0x01, 0x01, 0x08, 0x0a, | |
11368 | 0x11, 0x11, 0x11, 0x11, | |
11369 | 0x11, 0x11, 0x11, 0x11, | |
11370 | }; | |
9f40dead | 11371 | |
28a45957 | 11372 | static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback) |
c76949a6 | 11373 | { |
5e5a7f37 | 11374 | u32 rx_start_idx, rx_idx, tx_idx, opaque_key; |
bb158d69 | 11375 | u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val; |
84b67b27 | 11376 | u32 budget; |
c76949a6 MC |
11377 | struct sk_buff *skb, *rx_skb; |
11378 | u8 *tx_data; | |
11379 | dma_addr_t map; | |
11380 | int num_pkts, tx_len, rx_len, i, err; | |
11381 | struct tg3_rx_buffer_desc *desc; | |
898a56f8 | 11382 | struct tg3_napi *tnapi, *rnapi; |
8fea32b9 | 11383 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
c76949a6 | 11384 | |
c8873405 MC |
11385 | tnapi = &tp->napi[0]; |
11386 | rnapi = &tp->napi[0]; | |
0c1d0e2b | 11387 | if (tp->irq_cnt > 1) { |
63c3a66f | 11388 | if (tg3_flag(tp, ENABLE_RSS)) |
1da85aa3 | 11389 | rnapi = &tp->napi[1]; |
63c3a66f | 11390 | if (tg3_flag(tp, ENABLE_TSS)) |
c8873405 | 11391 | tnapi = &tp->napi[1]; |
0c1d0e2b | 11392 | } |
fd2ce37f | 11393 | coal_now = tnapi->coal_now | rnapi->coal_now; |
898a56f8 | 11394 | |
c76949a6 MC |
11395 | err = -EIO; |
11396 | ||
4852a861 | 11397 | tx_len = pktsz; |
a20e9c62 | 11398 | skb = netdev_alloc_skb(tp->dev, tx_len); |
a50bb7b9 JJ |
11399 | if (!skb) |
11400 | return -ENOMEM; | |
11401 | ||
c76949a6 MC |
11402 | tx_data = skb_put(skb, tx_len); |
11403 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
11404 | memset(tx_data + 6, 0x0, 8); | |
11405 | ||
4852a861 | 11406 | tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN); |
c76949a6 | 11407 | |
28a45957 | 11408 | if (tso_loopback) { |
bb158d69 MC |
11409 | struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN]; |
11410 | ||
11411 | u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN + | |
11412 | TG3_TSO_TCP_OPT_LEN; | |
11413 | ||
11414 | memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header, | |
11415 | sizeof(tg3_tso_header)); | |
11416 | mss = TG3_TSO_MSS; | |
11417 | ||
11418 | val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); | |
11419 | num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS); | |
11420 | ||
11421 | /* Set the total length field in the IP header */ | |
11422 | iph->tot_len = htons((u16)(mss + hdr_len)); | |
11423 | ||
11424 | base_flags = (TXD_FLAG_CPU_PRE_DMA | | |
11425 | TXD_FLAG_CPU_POST_DMA); | |
11426 | ||
63c3a66f JP |
11427 | if (tg3_flag(tp, HW_TSO_1) || |
11428 | tg3_flag(tp, HW_TSO_2) || | |
11429 | tg3_flag(tp, HW_TSO_3)) { | |
bb158d69 MC |
11430 | struct tcphdr *th; |
11431 | val = ETH_HLEN + TG3_TSO_IP_HDR_LEN; | |
11432 | th = (struct tcphdr *)&tx_data[val]; | |
11433 | th->check = 0; | |
11434 | } else | |
11435 | base_flags |= TXD_FLAG_TCPUDP_CSUM; | |
11436 | ||
63c3a66f | 11437 | if (tg3_flag(tp, HW_TSO_3)) { |
bb158d69 MC |
11438 | mss |= (hdr_len & 0xc) << 12; |
11439 | if (hdr_len & 0x10) | |
11440 | base_flags |= 0x00000010; | |
11441 | base_flags |= (hdr_len & 0x3e0) << 5; | |
63c3a66f | 11442 | } else if (tg3_flag(tp, HW_TSO_2)) |
bb158d69 | 11443 | mss |= hdr_len << 9; |
63c3a66f | 11444 | else if (tg3_flag(tp, HW_TSO_1) || |
bb158d69 MC |
11445 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
11446 | mss |= (TG3_TSO_TCP_OPT_LEN << 9); | |
11447 | } else { | |
11448 | base_flags |= (TG3_TSO_TCP_OPT_LEN << 10); | |
11449 | } | |
11450 | ||
11451 | data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header); | |
11452 | } else { | |
11453 | num_pkts = 1; | |
11454 | data_off = ETH_HLEN; | |
11455 | } | |
11456 | ||
11457 | for (i = data_off; i < tx_len; i++) | |
c76949a6 MC |
11458 | tx_data[i] = (u8) (i & 0xff); |
11459 | ||
f4188d8a AD |
11460 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); |
11461 | if (pci_dma_mapping_error(tp->pdev, map)) { | |
a21771dd MC |
11462 | dev_kfree_skb(skb); |
11463 | return -EIO; | |
11464 | } | |
c76949a6 | 11465 | |
0d681b27 MC |
11466 | val = tnapi->tx_prod; |
11467 | tnapi->tx_buffers[val].skb = skb; | |
11468 | dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map); | |
11469 | ||
c76949a6 | 11470 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 11471 | rnapi->coal_now); |
c76949a6 MC |
11472 | |
11473 | udelay(10); | |
11474 | ||
898a56f8 | 11475 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; |
c76949a6 | 11476 | |
84b67b27 MC |
11477 | budget = tg3_tx_avail(tnapi); |
11478 | if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len, | |
d1a3b737 MC |
11479 | base_flags | TXD_FLAG_END, mss, 0)) { |
11480 | tnapi->tx_buffers[val].skb = NULL; | |
11481 | dev_kfree_skb(skb); | |
11482 | return -EIO; | |
11483 | } | |
c76949a6 | 11484 | |
f3f3f27e | 11485 | tnapi->tx_prod++; |
c76949a6 | 11486 | |
f3f3f27e MC |
11487 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); |
11488 | tr32_mailbox(tnapi->prodmbox); | |
c76949a6 MC |
11489 | |
11490 | udelay(10); | |
11491 | ||
303fc921 MC |
11492 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ |
11493 | for (i = 0; i < 35; i++) { | |
c76949a6 | 11494 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 11495 | coal_now); |
c76949a6 MC |
11496 | |
11497 | udelay(10); | |
11498 | ||
898a56f8 MC |
11499 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; |
11500 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
f3f3f27e | 11501 | if ((tx_idx == tnapi->tx_prod) && |
c76949a6 MC |
11502 | (rx_idx == (rx_start_idx + num_pkts))) |
11503 | break; | |
11504 | } | |
11505 | ||
ba1142e4 | 11506 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1); |
c76949a6 MC |
11507 | dev_kfree_skb(skb); |
11508 | ||
f3f3f27e | 11509 | if (tx_idx != tnapi->tx_prod) |
c76949a6 MC |
11510 | goto out; |
11511 | ||
11512 | if (rx_idx != rx_start_idx + num_pkts) | |
11513 | goto out; | |
11514 | ||
bb158d69 MC |
11515 | val = data_off; |
11516 | while (rx_idx != rx_start_idx) { | |
11517 | desc = &rnapi->rx_rcb[rx_start_idx++]; | |
11518 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
11519 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
c76949a6 | 11520 | |
bb158d69 MC |
11521 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && |
11522 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
11523 | goto out; | |
c76949a6 | 11524 | |
bb158d69 MC |
11525 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) |
11526 | - ETH_FCS_LEN; | |
c76949a6 | 11527 | |
28a45957 | 11528 | if (!tso_loopback) { |
bb158d69 MC |
11529 | if (rx_len != tx_len) |
11530 | goto out; | |
4852a861 | 11531 | |
bb158d69 MC |
11532 | if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { |
11533 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
11534 | goto out; | |
11535 | } else { | |
11536 | if (opaque_key != RXD_OPAQUE_RING_JUMBO) | |
11537 | goto out; | |
11538 | } | |
11539 | } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
11540 | (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
54e0a67f | 11541 | >> RXD_TCPCSUM_SHIFT != 0xffff) { |
4852a861 | 11542 | goto out; |
bb158d69 | 11543 | } |
4852a861 | 11544 | |
bb158d69 MC |
11545 | if (opaque_key == RXD_OPAQUE_RING_STD) { |
11546 | rx_skb = tpr->rx_std_buffers[desc_idx].skb; | |
11547 | map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], | |
11548 | mapping); | |
11549 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { | |
11550 | rx_skb = tpr->rx_jmb_buffers[desc_idx].skb; | |
11551 | map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], | |
11552 | mapping); | |
11553 | } else | |
11554 | goto out; | |
c76949a6 | 11555 | |
bb158d69 MC |
11556 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, |
11557 | PCI_DMA_FROMDEVICE); | |
c76949a6 | 11558 | |
bb158d69 MC |
11559 | for (i = data_off; i < rx_len; i++, val++) { |
11560 | if (*(rx_skb->data + i) != (u8) (val & 0xff)) | |
11561 | goto out; | |
11562 | } | |
c76949a6 | 11563 | } |
bb158d69 | 11564 | |
c76949a6 | 11565 | err = 0; |
6aa20a22 | 11566 | |
c76949a6 MC |
11567 | /* tg3_free_rings will unmap and free the rx_skb */ |
11568 | out: | |
11569 | return err; | |
11570 | } | |
11571 | ||
00c266b7 MC |
11572 | #define TG3_STD_LOOPBACK_FAILED 1 |
11573 | #define TG3_JMB_LOOPBACK_FAILED 2 | |
bb158d69 | 11574 | #define TG3_TSO_LOOPBACK_FAILED 4 |
28a45957 MC |
11575 | #define TG3_LOOPBACK_FAILED \ |
11576 | (TG3_STD_LOOPBACK_FAILED | \ | |
11577 | TG3_JMB_LOOPBACK_FAILED | \ | |
11578 | TG3_TSO_LOOPBACK_FAILED) | |
00c266b7 | 11579 | |
941ec90f | 11580 | static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk) |
9f40dead | 11581 | { |
28a45957 | 11582 | int err = -EIO; |
2215e24c | 11583 | u32 eee_cap; |
9f40dead | 11584 | |
ab789046 MC |
11585 | eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; |
11586 | tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; | |
11587 | ||
28a45957 MC |
11588 | if (!netif_running(tp->dev)) { |
11589 | data[0] = TG3_LOOPBACK_FAILED; | |
11590 | data[1] = TG3_LOOPBACK_FAILED; | |
941ec90f MC |
11591 | if (do_extlpbk) |
11592 | data[2] = TG3_LOOPBACK_FAILED; | |
28a45957 MC |
11593 | goto done; |
11594 | } | |
11595 | ||
b9ec6c1b | 11596 | err = tg3_reset_hw(tp, 1); |
ab789046 | 11597 | if (err) { |
28a45957 MC |
11598 | data[0] = TG3_LOOPBACK_FAILED; |
11599 | data[1] = TG3_LOOPBACK_FAILED; | |
941ec90f MC |
11600 | if (do_extlpbk) |
11601 | data[2] = TG3_LOOPBACK_FAILED; | |
ab789046 MC |
11602 | goto done; |
11603 | } | |
9f40dead | 11604 | |
63c3a66f | 11605 | if (tg3_flag(tp, ENABLE_RSS)) { |
4a85f098 MC |
11606 | int i; |
11607 | ||
11608 | /* Reroute all rx packets to the 1st queue */ | |
11609 | for (i = MAC_RSS_INDIR_TBL_0; | |
11610 | i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4) | |
11611 | tw32(i, 0x0); | |
11612 | } | |
11613 | ||
6e01b20b MC |
11614 | /* HW errata - mac loopback fails in some cases on 5780. |
11615 | * Normal traffic and PHY loopback are not affected by | |
11616 | * errata. Also, the MAC loopback test is deprecated for | |
11617 | * all newer ASIC revisions. | |
11618 | */ | |
11619 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | |
11620 | !tg3_flag(tp, CPMU_PRESENT)) { | |
11621 | tg3_mac_loopback(tp, true); | |
9936bcf6 | 11622 | |
28a45957 MC |
11623 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) |
11624 | data[0] |= TG3_STD_LOOPBACK_FAILED; | |
6e01b20b MC |
11625 | |
11626 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && | |
28a45957 MC |
11627 | tg3_run_loopback(tp, 9000 + ETH_HLEN, false)) |
11628 | data[0] |= TG3_JMB_LOOPBACK_FAILED; | |
6e01b20b MC |
11629 | |
11630 | tg3_mac_loopback(tp, false); | |
11631 | } | |
4852a861 | 11632 | |
f07e9af3 | 11633 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
63c3a66f | 11634 | !tg3_flag(tp, USE_PHYLIB)) { |
5e5a7f37 MC |
11635 | int i; |
11636 | ||
941ec90f | 11637 | tg3_phy_lpbk_set(tp, 0, false); |
5e5a7f37 MC |
11638 | |
11639 | /* Wait for link */ | |
11640 | for (i = 0; i < 100; i++) { | |
11641 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
11642 | break; | |
11643 | mdelay(1); | |
11644 | } | |
11645 | ||
28a45957 MC |
11646 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) |
11647 | data[1] |= TG3_STD_LOOPBACK_FAILED; | |
63c3a66f | 11648 | if (tg3_flag(tp, TSO_CAPABLE) && |
28a45957 MC |
11649 | tg3_run_loopback(tp, ETH_FRAME_LEN, true)) |
11650 | data[1] |= TG3_TSO_LOOPBACK_FAILED; | |
63c3a66f | 11651 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && |
28a45957 MC |
11652 | tg3_run_loopback(tp, 9000 + ETH_HLEN, false)) |
11653 | data[1] |= TG3_JMB_LOOPBACK_FAILED; | |
9f40dead | 11654 | |
941ec90f MC |
11655 | if (do_extlpbk) { |
11656 | tg3_phy_lpbk_set(tp, 0, true); | |
11657 | ||
11658 | /* All link indications report up, but the hardware | |
11659 | * isn't really ready for about 20 msec. Double it | |
11660 | * to be sure. | |
11661 | */ | |
11662 | mdelay(40); | |
11663 | ||
11664 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) | |
11665 | data[2] |= TG3_STD_LOOPBACK_FAILED; | |
11666 | if (tg3_flag(tp, TSO_CAPABLE) && | |
11667 | tg3_run_loopback(tp, ETH_FRAME_LEN, true)) | |
11668 | data[2] |= TG3_TSO_LOOPBACK_FAILED; | |
11669 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && | |
11670 | tg3_run_loopback(tp, 9000 + ETH_HLEN, false)) | |
11671 | data[2] |= TG3_JMB_LOOPBACK_FAILED; | |
11672 | } | |
11673 | ||
5e5a7f37 MC |
11674 | /* Re-enable gphy autopowerdown. */ |
11675 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) | |
11676 | tg3_phy_toggle_apd(tp, true); | |
11677 | } | |
6833c043 | 11678 | |
941ec90f | 11679 | err = (data[0] | data[1] | data[2]) ? -EIO : 0; |
28a45957 | 11680 | |
ab789046 MC |
11681 | done: |
11682 | tp->phy_flags |= eee_cap; | |
11683 | ||
9f40dead MC |
11684 | return err; |
11685 | } | |
11686 | ||
4cafd3f5 MC |
11687 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, |
11688 | u64 *data) | |
11689 | { | |
566f86ad | 11690 | struct tg3 *tp = netdev_priv(dev); |
941ec90f | 11691 | bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB; |
566f86ad | 11692 | |
bed9829f MC |
11693 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && |
11694 | tg3_power_up(tp)) { | |
11695 | etest->flags |= ETH_TEST_FL_FAILED; | |
11696 | memset(data, 1, sizeof(u64) * TG3_NUM_TEST); | |
11697 | return; | |
11698 | } | |
bc1c7567 | 11699 | |
566f86ad MC |
11700 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); |
11701 | ||
11702 | if (tg3_test_nvram(tp) != 0) { | |
11703 | etest->flags |= ETH_TEST_FL_FAILED; | |
11704 | data[0] = 1; | |
11705 | } | |
941ec90f | 11706 | if (!doextlpbk && tg3_test_link(tp)) { |
ca43007a MC |
11707 | etest->flags |= ETH_TEST_FL_FAILED; |
11708 | data[1] = 1; | |
11709 | } | |
a71116d1 | 11710 | if (etest->flags & ETH_TEST_FL_OFFLINE) { |
b02fd9e3 | 11711 | int err, err2 = 0, irq_sync = 0; |
bbe832c0 MC |
11712 | |
11713 | if (netif_running(dev)) { | |
b02fd9e3 | 11714 | tg3_phy_stop(tp); |
a71116d1 | 11715 | tg3_netif_stop(tp); |
bbe832c0 MC |
11716 | irq_sync = 1; |
11717 | } | |
a71116d1 | 11718 | |
bbe832c0 | 11719 | tg3_full_lock(tp, irq_sync); |
a71116d1 MC |
11720 | |
11721 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
ec41c7df | 11722 | err = tg3_nvram_lock(tp); |
a71116d1 | 11723 | tg3_halt_cpu(tp, RX_CPU_BASE); |
63c3a66f | 11724 | if (!tg3_flag(tp, 5705_PLUS)) |
a71116d1 | 11725 | tg3_halt_cpu(tp, TX_CPU_BASE); |
ec41c7df MC |
11726 | if (!err) |
11727 | tg3_nvram_unlock(tp); | |
a71116d1 | 11728 | |
f07e9af3 | 11729 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
d9ab5ad1 MC |
11730 | tg3_phy_reset(tp); |
11731 | ||
a71116d1 MC |
11732 | if (tg3_test_registers(tp) != 0) { |
11733 | etest->flags |= ETH_TEST_FL_FAILED; | |
11734 | data[2] = 1; | |
11735 | } | |
28a45957 | 11736 | |
7942e1db MC |
11737 | if (tg3_test_memory(tp) != 0) { |
11738 | etest->flags |= ETH_TEST_FL_FAILED; | |
11739 | data[3] = 1; | |
11740 | } | |
28a45957 | 11741 | |
941ec90f MC |
11742 | if (doextlpbk) |
11743 | etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; | |
11744 | ||
11745 | if (tg3_test_loopback(tp, &data[4], doextlpbk)) | |
c76949a6 | 11746 | etest->flags |= ETH_TEST_FL_FAILED; |
a71116d1 | 11747 | |
f47c11ee DM |
11748 | tg3_full_unlock(tp); |
11749 | ||
d4bc3927 MC |
11750 | if (tg3_test_interrupt(tp) != 0) { |
11751 | etest->flags |= ETH_TEST_FL_FAILED; | |
941ec90f | 11752 | data[7] = 1; |
d4bc3927 | 11753 | } |
f47c11ee DM |
11754 | |
11755 | tg3_full_lock(tp, 0); | |
d4bc3927 | 11756 | |
a71116d1 MC |
11757 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
11758 | if (netif_running(dev)) { | |
63c3a66f | 11759 | tg3_flag_set(tp, INIT_COMPLETE); |
b02fd9e3 MC |
11760 | err2 = tg3_restart_hw(tp, 1); |
11761 | if (!err2) | |
b9ec6c1b | 11762 | tg3_netif_start(tp); |
a71116d1 | 11763 | } |
f47c11ee DM |
11764 | |
11765 | tg3_full_unlock(tp); | |
b02fd9e3 MC |
11766 | |
11767 | if (irq_sync && !err2) | |
11768 | tg3_phy_start(tp); | |
a71116d1 | 11769 | } |
80096068 | 11770 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
c866b7ea | 11771 | tg3_power_down(tp); |
bc1c7567 | 11772 | |
4cafd3f5 MC |
11773 | } |
11774 | ||
1da177e4 LT |
11775 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
11776 | { | |
11777 | struct mii_ioctl_data *data = if_mii(ifr); | |
11778 | struct tg3 *tp = netdev_priv(dev); | |
11779 | int err; | |
11780 | ||
63c3a66f | 11781 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 11782 | struct phy_device *phydev; |
f07e9af3 | 11783 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 11784 | return -EAGAIN; |
3f0e3ad7 | 11785 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
28b04113 | 11786 | return phy_mii_ioctl(phydev, ifr, cmd); |
b02fd9e3 MC |
11787 | } |
11788 | ||
33f401ae | 11789 | switch (cmd) { |
1da177e4 | 11790 | case SIOCGMIIPHY: |
882e9793 | 11791 | data->phy_id = tp->phy_addr; |
1da177e4 LT |
11792 | |
11793 | /* fallthru */ | |
11794 | case SIOCGMIIREG: { | |
11795 | u32 mii_regval; | |
11796 | ||
f07e9af3 | 11797 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11798 | break; /* We have no PHY */ |
11799 | ||
34eea5ac | 11800 | if (!netif_running(dev)) |
bc1c7567 MC |
11801 | return -EAGAIN; |
11802 | ||
f47c11ee | 11803 | spin_lock_bh(&tp->lock); |
1da177e4 | 11804 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); |
f47c11ee | 11805 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11806 | |
11807 | data->val_out = mii_regval; | |
11808 | ||
11809 | return err; | |
11810 | } | |
11811 | ||
11812 | case SIOCSMIIREG: | |
f07e9af3 | 11813 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11814 | break; /* We have no PHY */ |
11815 | ||
34eea5ac | 11816 | if (!netif_running(dev)) |
bc1c7567 MC |
11817 | return -EAGAIN; |
11818 | ||
f47c11ee | 11819 | spin_lock_bh(&tp->lock); |
1da177e4 | 11820 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); |
f47c11ee | 11821 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11822 | |
11823 | return err; | |
11824 | ||
11825 | default: | |
11826 | /* do nothing */ | |
11827 | break; | |
11828 | } | |
11829 | return -EOPNOTSUPP; | |
11830 | } | |
11831 | ||
15f9850d DM |
11832 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11833 | { | |
11834 | struct tg3 *tp = netdev_priv(dev); | |
11835 | ||
11836 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
11837 | return 0; | |
11838 | } | |
11839 | ||
d244c892 MC |
11840 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11841 | { | |
11842 | struct tg3 *tp = netdev_priv(dev); | |
11843 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
11844 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
11845 | ||
63c3a66f | 11846 | if (!tg3_flag(tp, 5705_PLUS)) { |
d244c892 MC |
11847 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; |
11848 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
11849 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
11850 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
11851 | } | |
11852 | ||
11853 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
11854 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
11855 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
11856 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
11857 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
11858 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
11859 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
11860 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
11861 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
11862 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
11863 | return -EINVAL; | |
11864 | ||
11865 | /* No rx interrupts will be generated if both are zero */ | |
11866 | if ((ec->rx_coalesce_usecs == 0) && | |
11867 | (ec->rx_max_coalesced_frames == 0)) | |
11868 | return -EINVAL; | |
11869 | ||
11870 | /* No tx interrupts will be generated if both are zero */ | |
11871 | if ((ec->tx_coalesce_usecs == 0) && | |
11872 | (ec->tx_max_coalesced_frames == 0)) | |
11873 | return -EINVAL; | |
11874 | ||
11875 | /* Only copy relevant parameters, ignore all others. */ | |
11876 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
11877 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
11878 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
11879 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
11880 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
11881 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
11882 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
11883 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
11884 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
11885 | ||
11886 | if (netif_running(dev)) { | |
11887 | tg3_full_lock(tp, 0); | |
11888 | __tg3_set_coalesce(tp, &tp->coal); | |
11889 | tg3_full_unlock(tp); | |
11890 | } | |
11891 | return 0; | |
11892 | } | |
11893 | ||
7282d491 | 11894 | static const struct ethtool_ops tg3_ethtool_ops = { |
1da177e4 LT |
11895 | .get_settings = tg3_get_settings, |
11896 | .set_settings = tg3_set_settings, | |
11897 | .get_drvinfo = tg3_get_drvinfo, | |
11898 | .get_regs_len = tg3_get_regs_len, | |
11899 | .get_regs = tg3_get_regs, | |
11900 | .get_wol = tg3_get_wol, | |
11901 | .set_wol = tg3_set_wol, | |
11902 | .get_msglevel = tg3_get_msglevel, | |
11903 | .set_msglevel = tg3_set_msglevel, | |
11904 | .nway_reset = tg3_nway_reset, | |
11905 | .get_link = ethtool_op_get_link, | |
11906 | .get_eeprom_len = tg3_get_eeprom_len, | |
11907 | .get_eeprom = tg3_get_eeprom, | |
11908 | .set_eeprom = tg3_set_eeprom, | |
11909 | .get_ringparam = tg3_get_ringparam, | |
11910 | .set_ringparam = tg3_set_ringparam, | |
11911 | .get_pauseparam = tg3_get_pauseparam, | |
11912 | .set_pauseparam = tg3_set_pauseparam, | |
4cafd3f5 | 11913 | .self_test = tg3_self_test, |
1da177e4 | 11914 | .get_strings = tg3_get_strings, |
81b8709c | 11915 | .set_phys_id = tg3_set_phys_id, |
1da177e4 | 11916 | .get_ethtool_stats = tg3_get_ethtool_stats, |
15f9850d | 11917 | .get_coalesce = tg3_get_coalesce, |
d244c892 | 11918 | .set_coalesce = tg3_set_coalesce, |
b9f2c044 | 11919 | .get_sset_count = tg3_get_sset_count, |
1da177e4 LT |
11920 | }; |
11921 | ||
11922 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |
11923 | { | |
1b27777a | 11924 | u32 cursize, val, magic; |
1da177e4 LT |
11925 | |
11926 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
11927 | ||
e4f34110 | 11928 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1da177e4 LT |
11929 | return; |
11930 | ||
b16250e3 MC |
11931 | if ((magic != TG3_EEPROM_MAGIC) && |
11932 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
11933 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
1da177e4 LT |
11934 | return; |
11935 | ||
11936 | /* | |
11937 | * Size the chip by reading offsets at increasing powers of two. | |
11938 | * When we encounter our validation signature, we know the addressing | |
11939 | * has wrapped around, and thus have our chip size. | |
11940 | */ | |
1b27777a | 11941 | cursize = 0x10; |
1da177e4 LT |
11942 | |
11943 | while (cursize < tp->nvram_size) { | |
e4f34110 | 11944 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
1da177e4 LT |
11945 | return; |
11946 | ||
1820180b | 11947 | if (val == magic) |
1da177e4 LT |
11948 | break; |
11949 | ||
11950 | cursize <<= 1; | |
11951 | } | |
11952 | ||
11953 | tp->nvram_size = cursize; | |
11954 | } | |
6aa20a22 | 11955 | |
1da177e4 LT |
11956 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) |
11957 | { | |
11958 | u32 val; | |
11959 | ||
63c3a66f | 11960 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) |
1b27777a MC |
11961 | return; |
11962 | ||
11963 | /* Selfboot format */ | |
1820180b | 11964 | if (val != TG3_EEPROM_MAGIC) { |
1b27777a MC |
11965 | tg3_get_eeprom_size(tp); |
11966 | return; | |
11967 | } | |
11968 | ||
6d348f2c | 11969 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { |
1da177e4 | 11970 | if (val != 0) { |
6d348f2c MC |
11971 | /* This is confusing. We want to operate on the |
11972 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
11973 | * call will read from NVRAM and byteswap the data | |
11974 | * according to the byteswapping settings for all | |
11975 | * other register accesses. This ensures the data we | |
11976 | * want will always reside in the lower 16-bits. | |
11977 | * However, the data in NVRAM is in LE format, which | |
11978 | * means the data from the NVRAM read will always be | |
11979 | * opposite the endianness of the CPU. The 16-bit | |
11980 | * byteswap then brings the data to CPU endianness. | |
11981 | */ | |
11982 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
1da177e4 LT |
11983 | return; |
11984 | } | |
11985 | } | |
fd1122a2 | 11986 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
1da177e4 LT |
11987 | } |
11988 | ||
11989 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
11990 | { | |
11991 | u32 nvcfg1; | |
11992 | ||
11993 | nvcfg1 = tr32(NVRAM_CFG1); | |
11994 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
63c3a66f | 11995 | tg3_flag_set(tp, FLASH); |
8590a603 | 11996 | } else { |
1da177e4 LT |
11997 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
11998 | tw32(NVRAM_CFG1, nvcfg1); | |
11999 | } | |
12000 | ||
6ff6f81d | 12001 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
63c3a66f | 12002 | tg3_flag(tp, 5780_CLASS)) { |
1da177e4 | 12003 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
8590a603 MC |
12004 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
12005 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12006 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
63c3a66f | 12007 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
12008 | break; |
12009 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
12010 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12011 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
12012 | break; | |
12013 | case FLASH_VENDOR_ATMEL_EEPROM: | |
12014 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12015 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
63c3a66f | 12016 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
12017 | break; |
12018 | case FLASH_VENDOR_ST: | |
12019 | tp->nvram_jedecnum = JEDEC_ST; | |
12020 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
63c3a66f | 12021 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
12022 | break; |
12023 | case FLASH_VENDOR_SAIFUN: | |
12024 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
12025 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
12026 | break; | |
12027 | case FLASH_VENDOR_SST_SMALL: | |
12028 | case FLASH_VENDOR_SST_LARGE: | |
12029 | tp->nvram_jedecnum = JEDEC_SST; | |
12030 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
12031 | break; | |
1da177e4 | 12032 | } |
8590a603 | 12033 | } else { |
1da177e4 LT |
12034 | tp->nvram_jedecnum = JEDEC_ATMEL; |
12035 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
63c3a66f | 12036 | tg3_flag_set(tp, NVRAM_BUFFERED); |
1da177e4 LT |
12037 | } |
12038 | } | |
12039 | ||
a1b950d5 MC |
12040 | static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) |
12041 | { | |
12042 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
12043 | case FLASH_5752PAGE_SIZE_256: | |
12044 | tp->nvram_pagesize = 256; | |
12045 | break; | |
12046 | case FLASH_5752PAGE_SIZE_512: | |
12047 | tp->nvram_pagesize = 512; | |
12048 | break; | |
12049 | case FLASH_5752PAGE_SIZE_1K: | |
12050 | tp->nvram_pagesize = 1024; | |
12051 | break; | |
12052 | case FLASH_5752PAGE_SIZE_2K: | |
12053 | tp->nvram_pagesize = 2048; | |
12054 | break; | |
12055 | case FLASH_5752PAGE_SIZE_4K: | |
12056 | tp->nvram_pagesize = 4096; | |
12057 | break; | |
12058 | case FLASH_5752PAGE_SIZE_264: | |
12059 | tp->nvram_pagesize = 264; | |
12060 | break; | |
12061 | case FLASH_5752PAGE_SIZE_528: | |
12062 | tp->nvram_pagesize = 528; | |
12063 | break; | |
12064 | } | |
12065 | } | |
12066 | ||
361b4ac2 MC |
12067 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) |
12068 | { | |
12069 | u32 nvcfg1; | |
12070 | ||
12071 | nvcfg1 = tr32(NVRAM_CFG1); | |
12072 | ||
e6af301b MC |
12073 | /* NVRAM protection for TPM */ |
12074 | if (nvcfg1 & (1 << 27)) | |
63c3a66f | 12075 | tg3_flag_set(tp, PROTECTED_NVRAM); |
e6af301b | 12076 | |
361b4ac2 | 12077 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
8590a603 MC |
12078 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: |
12079 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
12080 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12081 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
12082 | break; |
12083 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12084 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12085 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12086 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12087 | break; |
12088 | case FLASH_5752VENDOR_ST_M45PE10: | |
12089 | case FLASH_5752VENDOR_ST_M45PE20: | |
12090 | case FLASH_5752VENDOR_ST_M45PE40: | |
12091 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12092 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12093 | tg3_flag_set(tp, FLASH); | |
8590a603 | 12094 | break; |
361b4ac2 MC |
12095 | } |
12096 | ||
63c3a66f | 12097 | if (tg3_flag(tp, FLASH)) { |
a1b950d5 | 12098 | tg3_nvram_get_pagesize(tp, nvcfg1); |
8590a603 | 12099 | } else { |
361b4ac2 MC |
12100 | /* For eeprom, set pagesize to maximum eeprom size */ |
12101 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
12102 | ||
12103 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12104 | tw32(NVRAM_CFG1, nvcfg1); | |
12105 | } | |
12106 | } | |
12107 | ||
d3c7b886 MC |
12108 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) |
12109 | { | |
989a9d23 | 12110 | u32 nvcfg1, protect = 0; |
d3c7b886 MC |
12111 | |
12112 | nvcfg1 = tr32(NVRAM_CFG1); | |
12113 | ||
12114 | /* NVRAM protection for TPM */ | |
989a9d23 | 12115 | if (nvcfg1 & (1 << 27)) { |
63c3a66f | 12116 | tg3_flag_set(tp, PROTECTED_NVRAM); |
989a9d23 MC |
12117 | protect = 1; |
12118 | } | |
d3c7b886 | 12119 | |
989a9d23 MC |
12120 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
12121 | switch (nvcfg1) { | |
8590a603 MC |
12122 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
12123 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
12124 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
12125 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
12126 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12127 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12128 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12129 | tp->nvram_pagesize = 264; |
12130 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
12131 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
12132 | tp->nvram_size = (protect ? 0x3e200 : | |
12133 | TG3_NVRAM_SIZE_512KB); | |
12134 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
12135 | tp->nvram_size = (protect ? 0x1f200 : | |
12136 | TG3_NVRAM_SIZE_256KB); | |
12137 | else | |
12138 | tp->nvram_size = (protect ? 0x1f200 : | |
12139 | TG3_NVRAM_SIZE_128KB); | |
12140 | break; | |
12141 | case FLASH_5752VENDOR_ST_M45PE10: | |
12142 | case FLASH_5752VENDOR_ST_M45PE20: | |
12143 | case FLASH_5752VENDOR_ST_M45PE40: | |
12144 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12145 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12146 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12147 | tp->nvram_pagesize = 256; |
12148 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
12149 | tp->nvram_size = (protect ? | |
12150 | TG3_NVRAM_SIZE_64KB : | |
12151 | TG3_NVRAM_SIZE_128KB); | |
12152 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
12153 | tp->nvram_size = (protect ? | |
12154 | TG3_NVRAM_SIZE_64KB : | |
12155 | TG3_NVRAM_SIZE_256KB); | |
12156 | else | |
12157 | tp->nvram_size = (protect ? | |
12158 | TG3_NVRAM_SIZE_128KB : | |
12159 | TG3_NVRAM_SIZE_512KB); | |
12160 | break; | |
d3c7b886 MC |
12161 | } |
12162 | } | |
12163 | ||
1b27777a MC |
12164 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) |
12165 | { | |
12166 | u32 nvcfg1; | |
12167 | ||
12168 | nvcfg1 = tr32(NVRAM_CFG1); | |
12169 | ||
12170 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
8590a603 MC |
12171 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: |
12172 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
12173 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
12174 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
12175 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12176 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 | 12177 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
1b27777a | 12178 | |
8590a603 MC |
12179 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
12180 | tw32(NVRAM_CFG1, nvcfg1); | |
12181 | break; | |
12182 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12183 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
12184 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
12185 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
12186 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12187 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12188 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12189 | tp->nvram_pagesize = 264; |
12190 | break; | |
12191 | case FLASH_5752VENDOR_ST_M45PE10: | |
12192 | case FLASH_5752VENDOR_ST_M45PE20: | |
12193 | case FLASH_5752VENDOR_ST_M45PE40: | |
12194 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12195 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12196 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12197 | tp->nvram_pagesize = 256; |
12198 | break; | |
1b27777a MC |
12199 | } |
12200 | } | |
12201 | ||
6b91fa02 MC |
12202 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) |
12203 | { | |
12204 | u32 nvcfg1, protect = 0; | |
12205 | ||
12206 | nvcfg1 = tr32(NVRAM_CFG1); | |
12207 | ||
12208 | /* NVRAM protection for TPM */ | |
12209 | if (nvcfg1 & (1 << 27)) { | |
63c3a66f | 12210 | tg3_flag_set(tp, PROTECTED_NVRAM); |
6b91fa02 MC |
12211 | protect = 1; |
12212 | } | |
12213 | ||
12214 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
12215 | switch (nvcfg1) { | |
8590a603 MC |
12216 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
12217 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
12218 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
12219 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
12220 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
12221 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
12222 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
12223 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
12224 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12225 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12226 | tg3_flag_set(tp, FLASH); | |
12227 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); | |
8590a603 MC |
12228 | tp->nvram_pagesize = 256; |
12229 | break; | |
12230 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
12231 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
12232 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
12233 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
12234 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
12235 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
12236 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
12237 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
12238 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12239 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12240 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12241 | tp->nvram_pagesize = 256; |
12242 | break; | |
6b91fa02 MC |
12243 | } |
12244 | ||
12245 | if (protect) { | |
12246 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
12247 | } else { | |
12248 | switch (nvcfg1) { | |
8590a603 MC |
12249 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
12250 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
12251 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
12252 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
12253 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
12254 | break; | |
12255 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
12256 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
12257 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
12258 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
12259 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12260 | break; | |
12261 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
12262 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
12263 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
12264 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
12265 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12266 | break; | |
12267 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
12268 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
12269 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
12270 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
12271 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12272 | break; | |
6b91fa02 MC |
12273 | } |
12274 | } | |
12275 | } | |
12276 | ||
b5d3772c MC |
12277 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) |
12278 | { | |
12279 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12280 | tg3_flag_set(tp, NVRAM_BUFFERED); |
b5d3772c MC |
12281 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12282 | } | |
12283 | ||
321d32a0 MC |
12284 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) |
12285 | { | |
12286 | u32 nvcfg1; | |
12287 | ||
12288 | nvcfg1 = tr32(NVRAM_CFG1); | |
12289 | ||
12290 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12291 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
12292 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
12293 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12294 | tg3_flag_set(tp, NVRAM_BUFFERED); |
321d32a0 MC |
12295 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12296 | ||
12297 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12298 | tw32(NVRAM_CFG1, nvcfg1); | |
12299 | return; | |
12300 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12301 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
12302 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
12303 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
12304 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
12305 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
12306 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
12307 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12308 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12309 | tg3_flag_set(tp, FLASH); | |
321d32a0 MC |
12310 | |
12311 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12312 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12313 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
12314 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
12315 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12316 | break; | |
12317 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
12318 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
12319 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12320 | break; | |
12321 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
12322 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
12323 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12324 | break; | |
12325 | } | |
12326 | break; | |
12327 | case FLASH_5752VENDOR_ST_M45PE10: | |
12328 | case FLASH_5752VENDOR_ST_M45PE20: | |
12329 | case FLASH_5752VENDOR_ST_M45PE40: | |
12330 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12331 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12332 | tg3_flag_set(tp, FLASH); | |
321d32a0 MC |
12333 | |
12334 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12335 | case FLASH_5752VENDOR_ST_M45PE10: | |
12336 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12337 | break; | |
12338 | case FLASH_5752VENDOR_ST_M45PE20: | |
12339 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12340 | break; | |
12341 | case FLASH_5752VENDOR_ST_M45PE40: | |
12342 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12343 | break; | |
12344 | } | |
12345 | break; | |
12346 | default: | |
63c3a66f | 12347 | tg3_flag_set(tp, NO_NVRAM); |
321d32a0 MC |
12348 | return; |
12349 | } | |
12350 | ||
a1b950d5 MC |
12351 | tg3_nvram_get_pagesize(tp, nvcfg1); |
12352 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12353 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
a1b950d5 MC |
12354 | } |
12355 | ||
12356 | ||
12357 | static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp) | |
12358 | { | |
12359 | u32 nvcfg1; | |
12360 | ||
12361 | nvcfg1 = tr32(NVRAM_CFG1); | |
12362 | ||
12363 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12364 | case FLASH_5717VENDOR_ATMEL_EEPROM: | |
12365 | case FLASH_5717VENDOR_MICRO_EEPROM: | |
12366 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12367 | tg3_flag_set(tp, NVRAM_BUFFERED); |
a1b950d5 MC |
12368 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12369 | ||
12370 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12371 | tw32(NVRAM_CFG1, nvcfg1); | |
12372 | return; | |
12373 | case FLASH_5717VENDOR_ATMEL_MDB011D: | |
12374 | case FLASH_5717VENDOR_ATMEL_ADB011B: | |
12375 | case FLASH_5717VENDOR_ATMEL_ADB011D: | |
12376 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
12377 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
12378 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12379 | case FLASH_5717VENDOR_ATMEL_45USPT: | |
12380 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12381 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12382 | tg3_flag_set(tp, FLASH); | |
a1b950d5 MC |
12383 | |
12384 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12385 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
66ee33bf MC |
12386 | /* Detect size with tg3_nvram_get_size() */ |
12387 | break; | |
a1b950d5 MC |
12388 | case FLASH_5717VENDOR_ATMEL_ADB021B: |
12389 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12390 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12391 | break; | |
12392 | default: | |
12393 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12394 | break; | |
12395 | } | |
321d32a0 | 12396 | break; |
a1b950d5 MC |
12397 | case FLASH_5717VENDOR_ST_M_M25PE10: |
12398 | case FLASH_5717VENDOR_ST_A_M25PE10: | |
12399 | case FLASH_5717VENDOR_ST_M_M45PE10: | |
12400 | case FLASH_5717VENDOR_ST_A_M45PE10: | |
12401 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
12402 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
12403 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
12404 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
12405 | case FLASH_5717VENDOR_ST_25USPT: | |
12406 | case FLASH_5717VENDOR_ST_45USPT: | |
12407 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12408 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12409 | tg3_flag_set(tp, FLASH); | |
a1b950d5 MC |
12410 | |
12411 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12412 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
a1b950d5 | 12413 | case FLASH_5717VENDOR_ST_M_M45PE20: |
66ee33bf MC |
12414 | /* Detect size with tg3_nvram_get_size() */ |
12415 | break; | |
12416 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
a1b950d5 MC |
12417 | case FLASH_5717VENDOR_ST_A_M45PE20: |
12418 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12419 | break; | |
12420 | default: | |
12421 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12422 | break; | |
12423 | } | |
321d32a0 | 12424 | break; |
a1b950d5 | 12425 | default: |
63c3a66f | 12426 | tg3_flag_set(tp, NO_NVRAM); |
a1b950d5 | 12427 | return; |
321d32a0 | 12428 | } |
a1b950d5 MC |
12429 | |
12430 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12431 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12432 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
321d32a0 MC |
12433 | } |
12434 | ||
9b91b5f1 MC |
12435 | static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp) |
12436 | { | |
12437 | u32 nvcfg1, nvmpinstrp; | |
12438 | ||
12439 | nvcfg1 = tr32(NVRAM_CFG1); | |
12440 | nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK; | |
12441 | ||
12442 | switch (nvmpinstrp) { | |
12443 | case FLASH_5720_EEPROM_HD: | |
12444 | case FLASH_5720_EEPROM_LD: | |
12445 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12446 | tg3_flag_set(tp, NVRAM_BUFFERED); |
9b91b5f1 MC |
12447 | |
12448 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12449 | tw32(NVRAM_CFG1, nvcfg1); | |
12450 | if (nvmpinstrp == FLASH_5720_EEPROM_HD) | |
12451 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
12452 | else | |
12453 | tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; | |
12454 | return; | |
12455 | case FLASH_5720VENDOR_M_ATMEL_DB011D: | |
12456 | case FLASH_5720VENDOR_A_ATMEL_DB011B: | |
12457 | case FLASH_5720VENDOR_A_ATMEL_DB011D: | |
12458 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12459 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12460 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12461 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12462 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12463 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12464 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12465 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12466 | case FLASH_5720VENDOR_ATMEL_45USPT: | |
12467 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12468 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12469 | tg3_flag_set(tp, FLASH); | |
9b91b5f1 MC |
12470 | |
12471 | switch (nvmpinstrp) { | |
12472 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12473 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12474 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12475 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12476 | break; | |
12477 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12478 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12479 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12480 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12481 | break; | |
12482 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12483 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12484 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12485 | break; | |
12486 | default: | |
12487 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12488 | break; | |
12489 | } | |
12490 | break; | |
12491 | case FLASH_5720VENDOR_M_ST_M25PE10: | |
12492 | case FLASH_5720VENDOR_M_ST_M45PE10: | |
12493 | case FLASH_5720VENDOR_A_ST_M25PE10: | |
12494 | case FLASH_5720VENDOR_A_ST_M45PE10: | |
12495 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12496 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12497 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12498 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12499 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12500 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12501 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12502 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12503 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12504 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12505 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12506 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12507 | case FLASH_5720VENDOR_ST_25USPT: | |
12508 | case FLASH_5720VENDOR_ST_45USPT: | |
12509 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12510 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12511 | tg3_flag_set(tp, FLASH); | |
9b91b5f1 MC |
12512 | |
12513 | switch (nvmpinstrp) { | |
12514 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12515 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12516 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12517 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12518 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12519 | break; | |
12520 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12521 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12522 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12523 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12524 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12525 | break; | |
12526 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12527 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12528 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12529 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12530 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12531 | break; | |
12532 | default: | |
12533 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12534 | break; | |
12535 | } | |
12536 | break; | |
12537 | default: | |
63c3a66f | 12538 | tg3_flag_set(tp, NO_NVRAM); |
9b91b5f1 MC |
12539 | return; |
12540 | } | |
12541 | ||
12542 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12543 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12544 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
9b91b5f1 MC |
12545 | } |
12546 | ||
1da177e4 LT |
12547 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
12548 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
12549 | { | |
1da177e4 LT |
12550 | tw32_f(GRC_EEPROM_ADDR, |
12551 | (EEPROM_ADDR_FSM_RESET | | |
12552 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
12553 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
12554 | ||
9d57f01c | 12555 | msleep(1); |
1da177e4 LT |
12556 | |
12557 | /* Enable seeprom accesses. */ | |
12558 | tw32_f(GRC_LOCAL_CTRL, | |
12559 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
12560 | udelay(100); | |
12561 | ||
12562 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
12563 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
63c3a66f | 12564 | tg3_flag_set(tp, NVRAM); |
1da177e4 | 12565 | |
ec41c7df | 12566 | if (tg3_nvram_lock(tp)) { |
5129c3a3 MC |
12567 | netdev_warn(tp->dev, |
12568 | "Cannot get nvram lock, %s failed\n", | |
05dbe005 | 12569 | __func__); |
ec41c7df MC |
12570 | return; |
12571 | } | |
e6af301b | 12572 | tg3_enable_nvram_access(tp); |
1da177e4 | 12573 | |
989a9d23 MC |
12574 | tp->nvram_size = 0; |
12575 | ||
361b4ac2 MC |
12576 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
12577 | tg3_get_5752_nvram_info(tp); | |
d3c7b886 MC |
12578 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
12579 | tg3_get_5755_nvram_info(tp); | |
d30cdd28 | 12580 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
57e6983c MC |
12581 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
12582 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1b27777a | 12583 | tg3_get_5787_nvram_info(tp); |
6b91fa02 MC |
12584 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
12585 | tg3_get_5761_nvram_info(tp); | |
b5d3772c MC |
12586 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
12587 | tg3_get_5906_nvram_info(tp); | |
b703df6f MC |
12588 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
12589 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
321d32a0 | 12590 | tg3_get_57780_nvram_info(tp); |
9b91b5f1 MC |
12591 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
12592 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
a1b950d5 | 12593 | tg3_get_5717_nvram_info(tp); |
9b91b5f1 MC |
12594 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
12595 | tg3_get_5720_nvram_info(tp); | |
361b4ac2 MC |
12596 | else |
12597 | tg3_get_nvram_info(tp); | |
12598 | ||
989a9d23 MC |
12599 | if (tp->nvram_size == 0) |
12600 | tg3_get_nvram_size(tp); | |
1da177e4 | 12601 | |
e6af301b | 12602 | tg3_disable_nvram_access(tp); |
381291b7 | 12603 | tg3_nvram_unlock(tp); |
1da177e4 LT |
12604 | |
12605 | } else { | |
63c3a66f JP |
12606 | tg3_flag_clear(tp, NVRAM); |
12607 | tg3_flag_clear(tp, NVRAM_BUFFERED); | |
1da177e4 LT |
12608 | |
12609 | tg3_get_eeprom_size(tp); | |
12610 | } | |
12611 | } | |
12612 | ||
1da177e4 LT |
12613 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
12614 | u32 offset, u32 len, u8 *buf) | |
12615 | { | |
12616 | int i, j, rc = 0; | |
12617 | u32 val; | |
12618 | ||
12619 | for (i = 0; i < len; i += 4) { | |
b9fc7dc5 | 12620 | u32 addr; |
a9dc529d | 12621 | __be32 data; |
1da177e4 LT |
12622 | |
12623 | addr = offset + i; | |
12624 | ||
12625 | memcpy(&data, buf + i, 4); | |
12626 | ||
62cedd11 MC |
12627 | /* |
12628 | * The SEEPROM interface expects the data to always be opposite | |
12629 | * the native endian format. We accomplish this by reversing | |
12630 | * all the operations that would have been performed on the | |
12631 | * data from a call to tg3_nvram_read_be32(). | |
12632 | */ | |
12633 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
1da177e4 LT |
12634 | |
12635 | val = tr32(GRC_EEPROM_ADDR); | |
12636 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
12637 | ||
12638 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
12639 | EEPROM_ADDR_READ); | |
12640 | tw32(GRC_EEPROM_ADDR, val | | |
12641 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
12642 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
12643 | EEPROM_ADDR_START | | |
12644 | EEPROM_ADDR_WRITE); | |
6aa20a22 | 12645 | |
9d57f01c | 12646 | for (j = 0; j < 1000; j++) { |
1da177e4 LT |
12647 | val = tr32(GRC_EEPROM_ADDR); |
12648 | ||
12649 | if (val & EEPROM_ADDR_COMPLETE) | |
12650 | break; | |
9d57f01c | 12651 | msleep(1); |
1da177e4 LT |
12652 | } |
12653 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
12654 | rc = -EBUSY; | |
12655 | break; | |
12656 | } | |
12657 | } | |
12658 | ||
12659 | return rc; | |
12660 | } | |
12661 | ||
12662 | /* offset and length are dword aligned */ | |
12663 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
12664 | u8 *buf) | |
12665 | { | |
12666 | int ret = 0; | |
12667 | u32 pagesize = tp->nvram_pagesize; | |
12668 | u32 pagemask = pagesize - 1; | |
12669 | u32 nvram_cmd; | |
12670 | u8 *tmp; | |
12671 | ||
12672 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
12673 | if (tmp == NULL) | |
12674 | return -ENOMEM; | |
12675 | ||
12676 | while (len) { | |
12677 | int j; | |
e6af301b | 12678 | u32 phy_addr, page_off, size; |
1da177e4 LT |
12679 | |
12680 | phy_addr = offset & ~pagemask; | |
6aa20a22 | 12681 | |
1da177e4 | 12682 | for (j = 0; j < pagesize; j += 4) { |
a9dc529d MC |
12683 | ret = tg3_nvram_read_be32(tp, phy_addr + j, |
12684 | (__be32 *) (tmp + j)); | |
12685 | if (ret) | |
1da177e4 LT |
12686 | break; |
12687 | } | |
12688 | if (ret) | |
12689 | break; | |
12690 | ||
c6cdf436 | 12691 | page_off = offset & pagemask; |
1da177e4 LT |
12692 | size = pagesize; |
12693 | if (len < size) | |
12694 | size = len; | |
12695 | ||
12696 | len -= size; | |
12697 | ||
12698 | memcpy(tmp + page_off, buf, size); | |
12699 | ||
12700 | offset = offset + (pagesize - page_off); | |
12701 | ||
e6af301b | 12702 | tg3_enable_nvram_access(tp); |
1da177e4 LT |
12703 | |
12704 | /* | |
12705 | * Before we can erase the flash page, we need | |
12706 | * to issue a special "write enable" command. | |
12707 | */ | |
12708 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12709 | ||
12710 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12711 | break; | |
12712 | ||
12713 | /* Erase the target page */ | |
12714 | tw32(NVRAM_ADDR, phy_addr); | |
12715 | ||
12716 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
12717 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
12718 | ||
c6cdf436 | 12719 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) |
1da177e4 LT |
12720 | break; |
12721 | ||
12722 | /* Issue another write enable to start the write. */ | |
12723 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12724 | ||
12725 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12726 | break; | |
12727 | ||
12728 | for (j = 0; j < pagesize; j += 4) { | |
b9fc7dc5 | 12729 | __be32 data; |
1da177e4 | 12730 | |
b9fc7dc5 | 12731 | data = *((__be32 *) (tmp + j)); |
a9dc529d | 12732 | |
b9fc7dc5 | 12733 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 LT |
12734 | |
12735 | tw32(NVRAM_ADDR, phy_addr + j); | |
12736 | ||
12737 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
12738 | NVRAM_CMD_WR; | |
12739 | ||
12740 | if (j == 0) | |
12741 | nvram_cmd |= NVRAM_CMD_FIRST; | |
12742 | else if (j == (pagesize - 4)) | |
12743 | nvram_cmd |= NVRAM_CMD_LAST; | |
12744 | ||
12745 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12746 | break; | |
12747 | } | |
12748 | if (ret) | |
12749 | break; | |
12750 | } | |
12751 | ||
12752 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12753 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
12754 | ||
12755 | kfree(tmp); | |
12756 | ||
12757 | return ret; | |
12758 | } | |
12759 | ||
12760 | /* offset and length are dword aligned */ | |
12761 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
12762 | u8 *buf) | |
12763 | { | |
12764 | int i, ret = 0; | |
12765 | ||
12766 | for (i = 0; i < len; i += 4, offset += 4) { | |
b9fc7dc5 AV |
12767 | u32 page_off, phy_addr, nvram_cmd; |
12768 | __be32 data; | |
1da177e4 LT |
12769 | |
12770 | memcpy(&data, buf + i, 4); | |
b9fc7dc5 | 12771 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 | 12772 | |
c6cdf436 | 12773 | page_off = offset % tp->nvram_pagesize; |
1da177e4 | 12774 | |
1820180b | 12775 | phy_addr = tg3_nvram_phys_addr(tp, offset); |
1da177e4 LT |
12776 | |
12777 | tw32(NVRAM_ADDR, phy_addr); | |
12778 | ||
12779 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; | |
12780 | ||
c6cdf436 | 12781 | if (page_off == 0 || i == 0) |
1da177e4 | 12782 | nvram_cmd |= NVRAM_CMD_FIRST; |
f6d9a256 | 12783 | if (page_off == (tp->nvram_pagesize - 4)) |
1da177e4 LT |
12784 | nvram_cmd |= NVRAM_CMD_LAST; |
12785 | ||
12786 | if (i == (len - 4)) | |
12787 | nvram_cmd |= NVRAM_CMD_LAST; | |
12788 | ||
321d32a0 | 12789 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && |
63c3a66f | 12790 | !tg3_flag(tp, 5755_PLUS) && |
4c987487 MC |
12791 | (tp->nvram_jedecnum == JEDEC_ST) && |
12792 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
1da177e4 LT |
12793 | |
12794 | if ((ret = tg3_nvram_exec_cmd(tp, | |
12795 | NVRAM_CMD_WREN | NVRAM_CMD_GO | | |
12796 | NVRAM_CMD_DONE))) | |
12797 | ||
12798 | break; | |
12799 | } | |
63c3a66f | 12800 | if (!tg3_flag(tp, FLASH)) { |
1da177e4 LT |
12801 | /* We always do complete word writes to eeprom. */ |
12802 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
12803 | } | |
12804 | ||
12805 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12806 | break; | |
12807 | } | |
12808 | return ret; | |
12809 | } | |
12810 | ||
12811 | /* offset and length are dword aligned */ | |
12812 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
12813 | { | |
12814 | int ret; | |
12815 | ||
63c3a66f | 12816 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { |
314fba34 MC |
12817 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & |
12818 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
1da177e4 LT |
12819 | udelay(40); |
12820 | } | |
12821 | ||
63c3a66f | 12822 | if (!tg3_flag(tp, NVRAM)) { |
1da177e4 | 12823 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); |
859a5887 | 12824 | } else { |
1da177e4 LT |
12825 | u32 grc_mode; |
12826 | ||
ec41c7df MC |
12827 | ret = tg3_nvram_lock(tp); |
12828 | if (ret) | |
12829 | return ret; | |
1da177e4 | 12830 | |
e6af301b | 12831 | tg3_enable_nvram_access(tp); |
63c3a66f | 12832 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) |
1da177e4 | 12833 | tw32(NVRAM_WRITE1, 0x406); |
1da177e4 LT |
12834 | |
12835 | grc_mode = tr32(GRC_MODE); | |
12836 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
12837 | ||
63c3a66f | 12838 | if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { |
1da177e4 LT |
12839 | ret = tg3_nvram_write_block_buffered(tp, offset, len, |
12840 | buf); | |
859a5887 | 12841 | } else { |
1da177e4 LT |
12842 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, |
12843 | buf); | |
12844 | } | |
12845 | ||
12846 | grc_mode = tr32(GRC_MODE); | |
12847 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
12848 | ||
e6af301b | 12849 | tg3_disable_nvram_access(tp); |
1da177e4 LT |
12850 | tg3_nvram_unlock(tp); |
12851 | } | |
12852 | ||
63c3a66f | 12853 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { |
314fba34 | 12854 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
1da177e4 LT |
12855 | udelay(40); |
12856 | } | |
12857 | ||
12858 | return ret; | |
12859 | } | |
12860 | ||
12861 | struct subsys_tbl_ent { | |
12862 | u16 subsys_vendor, subsys_devid; | |
12863 | u32 phy_id; | |
12864 | }; | |
12865 | ||
24daf2b0 | 12866 | static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = { |
1da177e4 | 12867 | /* Broadcom boards. */ |
24daf2b0 | 12868 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12869 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12870 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12871 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12872 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12873 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 }, |
24daf2b0 MC |
12874 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12875 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 }, | |
12876 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12877 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12878 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12879 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12880 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12881 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 }, | |
12882 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12883 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12884 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12885 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12886 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12887 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 }, |
24daf2b0 | 12888 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12889 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 }, |
1da177e4 LT |
12890 | |
12891 | /* 3com boards. */ | |
24daf2b0 | 12892 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12893 | TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12894 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12895 | TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12896 | { TG3PCI_SUBVENDOR_ID_3COM, |
12897 | TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 }, | |
12898 | { TG3PCI_SUBVENDOR_ID_3COM, | |
79eb6904 | 12899 | TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12900 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12901 | TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12902 | |
12903 | /* DELL boards. */ | |
24daf2b0 | 12904 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12905 | TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12906 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12907 | TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12908 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12909 | TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 }, |
24daf2b0 | 12910 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12911 | TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 }, |
1da177e4 LT |
12912 | |
12913 | /* Compaq boards. */ | |
24daf2b0 | 12914 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12915 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12916 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12917 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12918 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
12919 | TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 }, | |
12920 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
79eb6904 | 12921 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12922 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12923 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12924 | |
12925 | /* IBM boards. */ | |
24daf2b0 MC |
12926 | { TG3PCI_SUBVENDOR_ID_IBM, |
12927 | TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 } | |
1da177e4 LT |
12928 | }; |
12929 | ||
24daf2b0 | 12930 | static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp) |
1da177e4 LT |
12931 | { |
12932 | int i; | |
12933 | ||
12934 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
12935 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
12936 | tp->pdev->subsystem_vendor) && | |
12937 | (subsys_id_to_phy_id[i].subsys_devid == | |
12938 | tp->pdev->subsystem_device)) | |
12939 | return &subsys_id_to_phy_id[i]; | |
12940 | } | |
12941 | return NULL; | |
12942 | } | |
12943 | ||
7d0c41ef | 12944 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) |
1da177e4 | 12945 | { |
1da177e4 | 12946 | u32 val; |
f49639e6 | 12947 | |
79eb6904 | 12948 | tp->phy_id = TG3_PHY_ID_INVALID; |
7d0c41ef MC |
12949 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
12950 | ||
a85feb8c | 12951 | /* Assume an onboard device and WOL capable by default. */ |
63c3a66f JP |
12952 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
12953 | tg3_flag_set(tp, WOL_CAP); | |
72b845e0 | 12954 | |
b5d3772c | 12955 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
9d26e213 | 12956 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
63c3a66f JP |
12957 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
12958 | tg3_flag_set(tp, IS_NIC); | |
9d26e213 | 12959 | } |
0527ba35 MC |
12960 | val = tr32(VCPU_CFGSHDW); |
12961 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
63c3a66f | 12962 | tg3_flag_set(tp, ASPM_WORKAROUND); |
0527ba35 | 12963 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && |
6fdbab9d | 12964 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) { |
63c3a66f | 12965 | tg3_flag_set(tp, WOL_ENABLE); |
6fdbab9d RW |
12966 | device_set_wakeup_enable(&tp->pdev->dev, true); |
12967 | } | |
05ac4cb7 | 12968 | goto done; |
b5d3772c MC |
12969 | } |
12970 | ||
1da177e4 LT |
12971 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
12972 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
12973 | u32 nic_cfg, led_cfg; | |
a9daf367 | 12974 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; |
7d0c41ef | 12975 | int eeprom_phy_serdes = 0; |
1da177e4 LT |
12976 | |
12977 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
12978 | tp->nic_sram_data_cfg = nic_cfg; | |
12979 | ||
12980 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
12981 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
6ff6f81d MC |
12982 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
12983 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
12984 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 && | |
1da177e4 LT |
12985 | (ver > 0) && (ver < 0x100)) |
12986 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
12987 | ||
a9daf367 MC |
12988 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
12989 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
12990 | ||
1da177e4 LT |
12991 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
12992 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
12993 | eeprom_phy_serdes = 1; | |
12994 | ||
12995 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
12996 | if (nic_phy_id != 0) { | |
12997 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
12998 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
12999 | ||
13000 | eeprom_phy_id = (id1 >> 16) << 10; | |
13001 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
13002 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
13003 | } else | |
13004 | eeprom_phy_id = 0; | |
13005 | ||
7d0c41ef | 13006 | tp->phy_id = eeprom_phy_id; |
747e8f8b | 13007 | if (eeprom_phy_serdes) { |
63c3a66f | 13008 | if (!tg3_flag(tp, 5705_PLUS)) |
f07e9af3 | 13009 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
a50d0796 | 13010 | else |
f07e9af3 | 13011 | tp->phy_flags |= TG3_PHYFLG_MII_SERDES; |
747e8f8b | 13012 | } |
7d0c41ef | 13013 | |
63c3a66f | 13014 | if (tg3_flag(tp, 5750_PLUS)) |
1da177e4 LT |
13015 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | |
13016 | SHASTA_EXT_LED_MODE_MASK); | |
cbf46853 | 13017 | else |
1da177e4 LT |
13018 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; |
13019 | ||
13020 | switch (led_cfg) { | |
13021 | default: | |
13022 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
13023 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
13024 | break; | |
13025 | ||
13026 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
13027 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
13028 | break; | |
13029 | ||
13030 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
13031 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
9ba27794 MC |
13032 | |
13033 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
13034 | * read on some older 5700/5701 bootcode. | |
13035 | */ | |
13036 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
13037 | ASIC_REV_5700 || | |
13038 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
13039 | ASIC_REV_5701) | |
13040 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
13041 | ||
1da177e4 LT |
13042 | break; |
13043 | ||
13044 | case SHASTA_EXT_LED_SHARED: | |
13045 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
13046 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
13047 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
13048 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
13049 | LED_CTRL_MODE_PHY_2); | |
13050 | break; | |
13051 | ||
13052 | case SHASTA_EXT_LED_MAC: | |
13053 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
13054 | break; | |
13055 | ||
13056 | case SHASTA_EXT_LED_COMBO: | |
13057 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
13058 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
13059 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
13060 | LED_CTRL_MODE_PHY_2); | |
13061 | break; | |
13062 | ||
855e1111 | 13063 | } |
1da177e4 LT |
13064 | |
13065 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13066 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
13067 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
13068 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
13069 | ||
b2a5c19c MC |
13070 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) |
13071 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
5f60891b | 13072 | |
9d26e213 | 13073 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
63c3a66f | 13074 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
9d26e213 MC |
13075 | if ((tp->pdev->subsystem_vendor == |
13076 | PCI_VENDOR_ID_ARIMA) && | |
13077 | (tp->pdev->subsystem_device == 0x205a || | |
13078 | tp->pdev->subsystem_device == 0x2063)) | |
63c3a66f | 13079 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
9d26e213 | 13080 | } else { |
63c3a66f JP |
13081 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
13082 | tg3_flag_set(tp, IS_NIC); | |
9d26e213 | 13083 | } |
1da177e4 LT |
13084 | |
13085 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
63c3a66f JP |
13086 | tg3_flag_set(tp, ENABLE_ASF); |
13087 | if (tg3_flag(tp, 5750_PLUS)) | |
13088 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 | 13089 | } |
b2b98d4a MC |
13090 | |
13091 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
63c3a66f JP |
13092 | tg3_flag(tp, 5750_PLUS)) |
13093 | tg3_flag_set(tp, ENABLE_APE); | |
b2b98d4a | 13094 | |
f07e9af3 | 13095 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && |
a85feb8c | 13096 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) |
63c3a66f | 13097 | tg3_flag_clear(tp, WOL_CAP); |
1da177e4 | 13098 | |
63c3a66f | 13099 | if (tg3_flag(tp, WOL_CAP) && |
6fdbab9d | 13100 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) { |
63c3a66f | 13101 | tg3_flag_set(tp, WOL_ENABLE); |
6fdbab9d RW |
13102 | device_set_wakeup_enable(&tp->pdev->dev, true); |
13103 | } | |
0527ba35 | 13104 | |
1da177e4 | 13105 | if (cfg2 & (1 << 17)) |
f07e9af3 | 13106 | tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; |
1da177e4 LT |
13107 | |
13108 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
13109 | /* bootcode if bit 18 is set */ | |
13110 | if (cfg2 & (1 << 18)) | |
f07e9af3 | 13111 | tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; |
8ed5d97e | 13112 | |
63c3a66f JP |
13113 | if ((tg3_flag(tp, 57765_PLUS) || |
13114 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
13115 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) && | |
6833c043 | 13116 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
f07e9af3 | 13117 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; |
6833c043 | 13118 | |
63c3a66f | 13119 | if (tg3_flag(tp, PCI_EXPRESS) && |
8c69b1e7 | 13120 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
63c3a66f | 13121 | !tg3_flag(tp, 57765_PLUS)) { |
8ed5d97e MC |
13122 | u32 cfg3; |
13123 | ||
13124 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
13125 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
63c3a66f | 13126 | tg3_flag_set(tp, ASPM_WORKAROUND); |
8ed5d97e | 13127 | } |
a9daf367 | 13128 | |
14417063 | 13129 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) |
63c3a66f | 13130 | tg3_flag_set(tp, RGMII_INBAND_DISABLE); |
a9daf367 | 13131 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) |
63c3a66f | 13132 | tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); |
a9daf367 | 13133 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) |
63c3a66f | 13134 | tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); |
1da177e4 | 13135 | } |
05ac4cb7 | 13136 | done: |
63c3a66f | 13137 | if (tg3_flag(tp, WOL_CAP)) |
43067ed8 | 13138 | device_set_wakeup_enable(&tp->pdev->dev, |
63c3a66f | 13139 | tg3_flag(tp, WOL_ENABLE)); |
43067ed8 RW |
13140 | else |
13141 | device_set_wakeup_capable(&tp->pdev->dev, false); | |
7d0c41ef MC |
13142 | } |
13143 | ||
b2a5c19c MC |
13144 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) |
13145 | { | |
13146 | int i; | |
13147 | u32 val; | |
13148 | ||
13149 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
13150 | tw32(OTP_CTRL, cmd); | |
13151 | ||
13152 | /* Wait for up to 1 ms for command to execute. */ | |
13153 | for (i = 0; i < 100; i++) { | |
13154 | val = tr32(OTP_STATUS); | |
13155 | if (val & OTP_STATUS_CMD_DONE) | |
13156 | break; | |
13157 | udelay(10); | |
13158 | } | |
13159 | ||
13160 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
13161 | } | |
13162 | ||
13163 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
13164 | * configuration is a 32-bit value that straddles the alignment boundary. | |
13165 | * We do two 32-bit reads and then shift and merge the results. | |
13166 | */ | |
13167 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
13168 | { | |
13169 | u32 bhalf_otp, thalf_otp; | |
13170 | ||
13171 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
13172 | ||
13173 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
13174 | return 0; | |
13175 | ||
13176 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
13177 | ||
13178 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
13179 | return 0; | |
13180 | ||
13181 | thalf_otp = tr32(OTP_READ_DATA); | |
13182 | ||
13183 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
13184 | ||
13185 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
13186 | return 0; | |
13187 | ||
13188 | bhalf_otp = tr32(OTP_READ_DATA); | |
13189 | ||
13190 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
13191 | } | |
13192 | ||
e256f8a3 MC |
13193 | static void __devinit tg3_phy_init_link_config(struct tg3 *tp) |
13194 | { | |
13195 | u32 adv = ADVERTISED_Autoneg | | |
13196 | ADVERTISED_Pause; | |
13197 | ||
13198 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) | |
13199 | adv |= ADVERTISED_1000baseT_Half | | |
13200 | ADVERTISED_1000baseT_Full; | |
13201 | ||
13202 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
13203 | adv |= ADVERTISED_100baseT_Half | | |
13204 | ADVERTISED_100baseT_Full | | |
13205 | ADVERTISED_10baseT_Half | | |
13206 | ADVERTISED_10baseT_Full | | |
13207 | ADVERTISED_TP; | |
13208 | else | |
13209 | adv |= ADVERTISED_FIBRE; | |
13210 | ||
13211 | tp->link_config.advertising = adv; | |
13212 | tp->link_config.speed = SPEED_INVALID; | |
13213 | tp->link_config.duplex = DUPLEX_INVALID; | |
13214 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
13215 | tp->link_config.active_speed = SPEED_INVALID; | |
13216 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
13217 | tp->link_config.orig_speed = SPEED_INVALID; | |
13218 | tp->link_config.orig_duplex = DUPLEX_INVALID; | |
13219 | tp->link_config.orig_autoneg = AUTONEG_INVALID; | |
13220 | } | |
13221 | ||
7d0c41ef MC |
13222 | static int __devinit tg3_phy_probe(struct tg3 *tp) |
13223 | { | |
13224 | u32 hw_phy_id_1, hw_phy_id_2; | |
13225 | u32 hw_phy_id, hw_phy_id_masked; | |
13226 | int err; | |
1da177e4 | 13227 | |
e256f8a3 | 13228 | /* flow control autonegotiation is default behavior */ |
63c3a66f | 13229 | tg3_flag_set(tp, PAUSE_AUTONEG); |
e256f8a3 MC |
13230 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; |
13231 | ||
63c3a66f | 13232 | if (tg3_flag(tp, USE_PHYLIB)) |
b02fd9e3 MC |
13233 | return tg3_phy_init(tp); |
13234 | ||
1da177e4 | 13235 | /* Reading the PHY ID register can conflict with ASF |
877d0310 | 13236 | * firmware access to the PHY hardware. |
1da177e4 LT |
13237 | */ |
13238 | err = 0; | |
63c3a66f | 13239 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { |
79eb6904 | 13240 | hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID; |
1da177e4 LT |
13241 | } else { |
13242 | /* Now read the physical PHY_ID from the chip and verify | |
13243 | * that it is sane. If it doesn't look good, we fall back | |
13244 | * to either the hard-coded table based PHY_ID and failing | |
13245 | * that the value found in the eeprom area. | |
13246 | */ | |
13247 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
13248 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
13249 | ||
13250 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
13251 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
13252 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
13253 | ||
79eb6904 | 13254 | hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK; |
1da177e4 LT |
13255 | } |
13256 | ||
79eb6904 | 13257 | if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) { |
1da177e4 | 13258 | tp->phy_id = hw_phy_id; |
79eb6904 | 13259 | if (hw_phy_id_masked == TG3_PHY_ID_BCM8002) |
f07e9af3 | 13260 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
da6b2d01 | 13261 | else |
f07e9af3 | 13262 | tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; |
1da177e4 | 13263 | } else { |
79eb6904 | 13264 | if (tp->phy_id != TG3_PHY_ID_INVALID) { |
7d0c41ef MC |
13265 | /* Do nothing, phy ID already set up in |
13266 | * tg3_get_eeprom_hw_cfg(). | |
13267 | */ | |
1da177e4 LT |
13268 | } else { |
13269 | struct subsys_tbl_ent *p; | |
13270 | ||
13271 | /* No eeprom signature? Try the hardcoded | |
13272 | * subsys device table. | |
13273 | */ | |
24daf2b0 | 13274 | p = tg3_lookup_by_subsys(tp); |
1da177e4 LT |
13275 | if (!p) |
13276 | return -ENODEV; | |
13277 | ||
13278 | tp->phy_id = p->phy_id; | |
13279 | if (!tp->phy_id || | |
79eb6904 | 13280 | tp->phy_id == TG3_PHY_ID_BCM8002) |
f07e9af3 | 13281 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
1da177e4 LT |
13282 | } |
13283 | } | |
13284 | ||
a6b68dab | 13285 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
5baa5e9a MC |
13286 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13287 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || | |
13288 | (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 && | |
a6b68dab MC |
13289 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) || |
13290 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
13291 | tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))) | |
52b02d04 MC |
13292 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; |
13293 | ||
e256f8a3 MC |
13294 | tg3_phy_init_link_config(tp); |
13295 | ||
f07e9af3 | 13296 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
63c3a66f JP |
13297 | !tg3_flag(tp, ENABLE_APE) && |
13298 | !tg3_flag(tp, ENABLE_ASF)) { | |
42b64a45 | 13299 | u32 bmsr, mask; |
1da177e4 LT |
13300 | |
13301 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
13302 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
13303 | (bmsr & BMSR_LSTATUS)) | |
13304 | goto skip_phy_reset; | |
6aa20a22 | 13305 | |
1da177e4 LT |
13306 | err = tg3_phy_reset(tp); |
13307 | if (err) | |
13308 | return err; | |
13309 | ||
42b64a45 | 13310 | tg3_phy_set_wirespeed(tp); |
1da177e4 | 13311 | |
3600d918 MC |
13312 | mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
13313 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
13314 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); | |
13315 | if (!tg3_copper_is_advertising_all(tp, mask)) { | |
42b64a45 MC |
13316 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, |
13317 | tp->link_config.flowctrl); | |
1da177e4 LT |
13318 | |
13319 | tg3_writephy(tp, MII_BMCR, | |
13320 | BMCR_ANENABLE | BMCR_ANRESTART); | |
13321 | } | |
1da177e4 LT |
13322 | } |
13323 | ||
13324 | skip_phy_reset: | |
79eb6904 | 13325 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
13326 | err = tg3_init_5401phy_dsp(tp); |
13327 | if (err) | |
13328 | return err; | |
1da177e4 | 13329 | |
1da177e4 LT |
13330 | err = tg3_init_5401phy_dsp(tp); |
13331 | } | |
13332 | ||
1da177e4 LT |
13333 | return err; |
13334 | } | |
13335 | ||
184b8904 | 13336 | static void __devinit tg3_read_vpd(struct tg3 *tp) |
1da177e4 | 13337 | { |
a4a8bb15 | 13338 | u8 *vpd_data; |
4181b2c8 | 13339 | unsigned int block_end, rosize, len; |
535a490e | 13340 | u32 vpdlen; |
184b8904 | 13341 | int j, i = 0; |
a4a8bb15 | 13342 | |
535a490e | 13343 | vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen); |
a4a8bb15 MC |
13344 | if (!vpd_data) |
13345 | goto out_no_vpd; | |
1da177e4 | 13346 | |
535a490e | 13347 | i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA); |
4181b2c8 MC |
13348 | if (i < 0) |
13349 | goto out_not_found; | |
1da177e4 | 13350 | |
4181b2c8 MC |
13351 | rosize = pci_vpd_lrdt_size(&vpd_data[i]); |
13352 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize; | |
13353 | i += PCI_VPD_LRDT_TAG_SIZE; | |
1da177e4 | 13354 | |
535a490e | 13355 | if (block_end > vpdlen) |
4181b2c8 | 13356 | goto out_not_found; |
af2c6a4a | 13357 | |
184b8904 MC |
13358 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
13359 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
13360 | if (j > 0) { | |
13361 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13362 | ||
13363 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13364 | if (j + len > block_end || len != 4 || | |
13365 | memcmp(&vpd_data[j], "1028", 4)) | |
13366 | goto partno; | |
13367 | ||
13368 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, | |
13369 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
13370 | if (j < 0) | |
13371 | goto partno; | |
13372 | ||
13373 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13374 | ||
13375 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13376 | if (j + len > block_end) | |
13377 | goto partno; | |
13378 | ||
13379 | memcpy(tp->fw_ver, &vpd_data[j], len); | |
535a490e | 13380 | strncat(tp->fw_ver, " bc ", vpdlen - len - 1); |
184b8904 MC |
13381 | } |
13382 | ||
13383 | partno: | |
4181b2c8 MC |
13384 | i = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
13385 | PCI_VPD_RO_KEYWORD_PARTNO); | |
13386 | if (i < 0) | |
13387 | goto out_not_found; | |
af2c6a4a | 13388 | |
4181b2c8 | 13389 | len = pci_vpd_info_field_size(&vpd_data[i]); |
1da177e4 | 13390 | |
4181b2c8 MC |
13391 | i += PCI_VPD_INFO_FLD_HDR_SIZE; |
13392 | if (len > TG3_BPN_SIZE || | |
535a490e | 13393 | (len + i) > vpdlen) |
4181b2c8 | 13394 | goto out_not_found; |
1da177e4 | 13395 | |
4181b2c8 | 13396 | memcpy(tp->board_part_number, &vpd_data[i], len); |
1da177e4 | 13397 | |
1da177e4 | 13398 | out_not_found: |
a4a8bb15 | 13399 | kfree(vpd_data); |
37a949c5 | 13400 | if (tp->board_part_number[0]) |
a4a8bb15 MC |
13401 | return; |
13402 | ||
13403 | out_no_vpd: | |
37a949c5 MC |
13404 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
13405 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717) | |
13406 | strcpy(tp->board_part_number, "BCM5717"); | |
13407 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) | |
13408 | strcpy(tp->board_part_number, "BCM5718"); | |
13409 | else | |
13410 | goto nomatch; | |
13411 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
13412 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
13413 | strcpy(tp->board_part_number, "BCM57780"); | |
13414 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
13415 | strcpy(tp->board_part_number, "BCM57760"); | |
13416 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
13417 | strcpy(tp->board_part_number, "BCM57790"); | |
13418 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
13419 | strcpy(tp->board_part_number, "BCM57788"); | |
13420 | else | |
13421 | goto nomatch; | |
13422 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
13423 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) | |
13424 | strcpy(tp->board_part_number, "BCM57761"); | |
13425 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) | |
13426 | strcpy(tp->board_part_number, "BCM57765"); | |
13427 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) | |
13428 | strcpy(tp->board_part_number, "BCM57781"); | |
13429 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) | |
13430 | strcpy(tp->board_part_number, "BCM57785"); | |
13431 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) | |
13432 | strcpy(tp->board_part_number, "BCM57791"); | |
13433 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13434 | strcpy(tp->board_part_number, "BCM57795"); | |
13435 | else | |
13436 | goto nomatch; | |
13437 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
b5d3772c | 13438 | strcpy(tp->board_part_number, "BCM95906"); |
37a949c5 MC |
13439 | } else { |
13440 | nomatch: | |
b5d3772c | 13441 | strcpy(tp->board_part_number, "none"); |
37a949c5 | 13442 | } |
1da177e4 LT |
13443 | } |
13444 | ||
9c8a620e MC |
13445 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) |
13446 | { | |
13447 | u32 val; | |
13448 | ||
e4f34110 | 13449 | if (tg3_nvram_read(tp, offset, &val) || |
9c8a620e | 13450 | (val & 0xfc000000) != 0x0c000000 || |
e4f34110 | 13451 | tg3_nvram_read(tp, offset + 4, &val) || |
9c8a620e MC |
13452 | val != 0) |
13453 | return 0; | |
13454 | ||
13455 | return 1; | |
13456 | } | |
13457 | ||
acd9c119 MC |
13458 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) |
13459 | { | |
ff3a7cb2 | 13460 | u32 val, offset, start, ver_offset; |
75f9936e | 13461 | int i, dst_off; |
ff3a7cb2 | 13462 | bool newver = false; |
acd9c119 MC |
13463 | |
13464 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
13465 | tg3_nvram_read(tp, 0x4, &start)) | |
13466 | return; | |
13467 | ||
13468 | offset = tg3_nvram_logical_addr(tp, offset); | |
13469 | ||
ff3a7cb2 | 13470 | if (tg3_nvram_read(tp, offset, &val)) |
acd9c119 MC |
13471 | return; |
13472 | ||
ff3a7cb2 MC |
13473 | if ((val & 0xfc000000) == 0x0c000000) { |
13474 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
acd9c119 MC |
13475 | return; |
13476 | ||
ff3a7cb2 MC |
13477 | if (val == 0) |
13478 | newver = true; | |
13479 | } | |
13480 | ||
75f9936e MC |
13481 | dst_off = strlen(tp->fw_ver); |
13482 | ||
ff3a7cb2 | 13483 | if (newver) { |
75f9936e MC |
13484 | if (TG3_VER_SIZE - dst_off < 16 || |
13485 | tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
ff3a7cb2 MC |
13486 | return; |
13487 | ||
13488 | offset = offset + ver_offset - start; | |
13489 | for (i = 0; i < 16; i += 4) { | |
13490 | __be32 v; | |
13491 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
13492 | return; | |
13493 | ||
75f9936e | 13494 | memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); |
ff3a7cb2 MC |
13495 | } |
13496 | } else { | |
13497 | u32 major, minor; | |
13498 | ||
13499 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
13500 | return; | |
13501 | ||
13502 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
13503 | TG3_NVM_BCVER_MAJSFT; | |
13504 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
75f9936e MC |
13505 | snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, |
13506 | "v%d.%02d", major, minor); | |
acd9c119 MC |
13507 | } |
13508 | } | |
13509 | ||
a6f6cb1c MC |
13510 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) |
13511 | { | |
13512 | u32 val, major, minor; | |
13513 | ||
13514 | /* Use native endian representation */ | |
13515 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
13516 | return; | |
13517 | ||
13518 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
13519 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
13520 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
13521 | TG3_NVM_HWSB_CFG1_MINSFT; | |
13522 | ||
13523 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
13524 | } | |
13525 | ||
dfe00d7d MC |
13526 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) |
13527 | { | |
13528 | u32 offset, major, minor, build; | |
13529 | ||
75f9936e | 13530 | strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); |
dfe00d7d MC |
13531 | |
13532 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
13533 | return; | |
13534 | ||
13535 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
13536 | case TG3_EEPROM_SB_REVISION_0: | |
13537 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
13538 | break; | |
13539 | case TG3_EEPROM_SB_REVISION_2: | |
13540 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
13541 | break; | |
13542 | case TG3_EEPROM_SB_REVISION_3: | |
13543 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
13544 | break; | |
a4153d40 MC |
13545 | case TG3_EEPROM_SB_REVISION_4: |
13546 | offset = TG3_EEPROM_SB_F1R4_EDH_OFF; | |
13547 | break; | |
13548 | case TG3_EEPROM_SB_REVISION_5: | |
13549 | offset = TG3_EEPROM_SB_F1R5_EDH_OFF; | |
13550 | break; | |
bba226ac MC |
13551 | case TG3_EEPROM_SB_REVISION_6: |
13552 | offset = TG3_EEPROM_SB_F1R6_EDH_OFF; | |
13553 | break; | |
dfe00d7d MC |
13554 | default: |
13555 | return; | |
13556 | } | |
13557 | ||
e4f34110 | 13558 | if (tg3_nvram_read(tp, offset, &val)) |
dfe00d7d MC |
13559 | return; |
13560 | ||
13561 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
13562 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
13563 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
13564 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
13565 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
13566 | ||
13567 | if (minor > 99 || build > 26) | |
13568 | return; | |
13569 | ||
75f9936e MC |
13570 | offset = strlen(tp->fw_ver); |
13571 | snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, | |
13572 | " v%d.%02d", major, minor); | |
dfe00d7d MC |
13573 | |
13574 | if (build > 0) { | |
75f9936e MC |
13575 | offset = strlen(tp->fw_ver); |
13576 | if (offset < TG3_VER_SIZE - 1) | |
13577 | tp->fw_ver[offset] = 'a' + build - 1; | |
dfe00d7d MC |
13578 | } |
13579 | } | |
13580 | ||
acd9c119 | 13581 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) |
c4e6575c MC |
13582 | { |
13583 | u32 val, offset, start; | |
acd9c119 | 13584 | int i, vlen; |
9c8a620e MC |
13585 | |
13586 | for (offset = TG3_NVM_DIR_START; | |
13587 | offset < TG3_NVM_DIR_END; | |
13588 | offset += TG3_NVM_DIRENT_SIZE) { | |
e4f34110 | 13589 | if (tg3_nvram_read(tp, offset, &val)) |
c4e6575c MC |
13590 | return; |
13591 | ||
9c8a620e MC |
13592 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
13593 | break; | |
13594 | } | |
13595 | ||
13596 | if (offset == TG3_NVM_DIR_END) | |
13597 | return; | |
13598 | ||
63c3a66f | 13599 | if (!tg3_flag(tp, 5705_PLUS)) |
9c8a620e | 13600 | start = 0x08000000; |
e4f34110 | 13601 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
9c8a620e MC |
13602 | return; |
13603 | ||
e4f34110 | 13604 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
9c8a620e | 13605 | !tg3_fw_img_is_valid(tp, offset) || |
e4f34110 | 13606 | tg3_nvram_read(tp, offset + 8, &val)) |
9c8a620e MC |
13607 | return; |
13608 | ||
13609 | offset += val - start; | |
13610 | ||
acd9c119 | 13611 | vlen = strlen(tp->fw_ver); |
9c8a620e | 13612 | |
acd9c119 MC |
13613 | tp->fw_ver[vlen++] = ','; |
13614 | tp->fw_ver[vlen++] = ' '; | |
9c8a620e MC |
13615 | |
13616 | for (i = 0; i < 4; i++) { | |
a9dc529d MC |
13617 | __be32 v; |
13618 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
c4e6575c MC |
13619 | return; |
13620 | ||
b9fc7dc5 | 13621 | offset += sizeof(v); |
c4e6575c | 13622 | |
acd9c119 MC |
13623 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
13624 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
9c8a620e | 13625 | break; |
c4e6575c | 13626 | } |
9c8a620e | 13627 | |
acd9c119 MC |
13628 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
13629 | vlen += sizeof(v); | |
c4e6575c | 13630 | } |
acd9c119 MC |
13631 | } |
13632 | ||
7fd76445 MC |
13633 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) |
13634 | { | |
13635 | int vlen; | |
13636 | u32 apedata; | |
ecc79648 | 13637 | char *fwtype; |
7fd76445 | 13638 | |
63c3a66f | 13639 | if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF)) |
7fd76445 MC |
13640 | return; |
13641 | ||
13642 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
13643 | if (apedata != APE_SEG_SIG_MAGIC) | |
13644 | return; | |
13645 | ||
13646 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
13647 | if (!(apedata & APE_FW_STATUS_READY)) | |
13648 | return; | |
13649 | ||
13650 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); | |
13651 | ||
dc6d0744 | 13652 | if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) { |
63c3a66f | 13653 | tg3_flag_set(tp, APE_HAS_NCSI); |
ecc79648 | 13654 | fwtype = "NCSI"; |
dc6d0744 | 13655 | } else { |
ecc79648 | 13656 | fwtype = "DASH"; |
dc6d0744 | 13657 | } |
ecc79648 | 13658 | |
7fd76445 MC |
13659 | vlen = strlen(tp->fw_ver); |
13660 | ||
ecc79648 MC |
13661 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", |
13662 | fwtype, | |
7fd76445 MC |
13663 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, |
13664 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
13665 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
13666 | (apedata & APE_FW_VERSION_BLDMSK)); | |
13667 | } | |
13668 | ||
acd9c119 MC |
13669 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) |
13670 | { | |
13671 | u32 val; | |
75f9936e | 13672 | bool vpd_vers = false; |
acd9c119 | 13673 | |
75f9936e MC |
13674 | if (tp->fw_ver[0] != 0) |
13675 | vpd_vers = true; | |
df259d8c | 13676 | |
63c3a66f | 13677 | if (tg3_flag(tp, NO_NVRAM)) { |
75f9936e | 13678 | strcat(tp->fw_ver, "sb"); |
df259d8c MC |
13679 | return; |
13680 | } | |
13681 | ||
acd9c119 MC |
13682 | if (tg3_nvram_read(tp, 0, &val)) |
13683 | return; | |
13684 | ||
13685 | if (val == TG3_EEPROM_MAGIC) | |
13686 | tg3_read_bc_ver(tp); | |
13687 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
13688 | tg3_read_sb_ver(tp, val); | |
a6f6cb1c MC |
13689 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
13690 | tg3_read_hwsb_ver(tp); | |
acd9c119 MC |
13691 | else |
13692 | return; | |
13693 | ||
c9cab24e | 13694 | if (vpd_vers) |
75f9936e | 13695 | goto done; |
acd9c119 | 13696 | |
c9cab24e MC |
13697 | if (tg3_flag(tp, ENABLE_APE)) { |
13698 | if (tg3_flag(tp, ENABLE_ASF)) | |
13699 | tg3_read_dash_ver(tp); | |
13700 | } else if (tg3_flag(tp, ENABLE_ASF)) { | |
13701 | tg3_read_mgmtfw_ver(tp); | |
13702 | } | |
9c8a620e | 13703 | |
75f9936e | 13704 | done: |
9c8a620e | 13705 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; |
c4e6575c MC |
13706 | } |
13707 | ||
7544b097 MC |
13708 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *); |
13709 | ||
7cb32cf2 MC |
13710 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) |
13711 | { | |
63c3a66f | 13712 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
de9f5230 | 13713 | return TG3_RX_RET_MAX_SIZE_5717; |
63c3a66f | 13714 | else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) |
de9f5230 | 13715 | return TG3_RX_RET_MAX_SIZE_5700; |
7cb32cf2 | 13716 | else |
de9f5230 | 13717 | return TG3_RX_RET_MAX_SIZE_5705; |
7cb32cf2 MC |
13718 | } |
13719 | ||
4143470c | 13720 | static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = { |
895950c2 JP |
13721 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) }, |
13722 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
13723 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) }, | |
13724 | { }, | |
13725 | }; | |
13726 | ||
1da177e4 LT |
13727 | static int __devinit tg3_get_invariants(struct tg3 *tp) |
13728 | { | |
1da177e4 | 13729 | u32 misc_ctrl_reg; |
1da177e4 LT |
13730 | u32 pci_state_reg, grc_misc_cfg; |
13731 | u32 val; | |
13732 | u16 pci_cmd; | |
5e7dfd0f | 13733 | int err; |
1da177e4 | 13734 | |
1da177e4 LT |
13735 | /* Force memory write invalidate off. If we leave it on, |
13736 | * then on 5700_BX chips we have to enable a workaround. | |
13737 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
13738 | * to match the cacheline size. The Broadcom driver have this | |
13739 | * workaround but turns MWI off all the times so never uses | |
13740 | * it. This seems to suggest that the workaround is insufficient. | |
13741 | */ | |
13742 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13743 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
13744 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13745 | ||
16821285 MC |
13746 | /* Important! -- Make sure register accesses are byteswapped |
13747 | * correctly. Also, for those chips that require it, make | |
13748 | * sure that indirect register accesses are enabled before | |
13749 | * the first operation. | |
1da177e4 LT |
13750 | */ |
13751 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13752 | &misc_ctrl_reg); | |
16821285 MC |
13753 | tp->misc_host_ctrl |= (misc_ctrl_reg & |
13754 | MISC_HOST_CTRL_CHIPREV); | |
13755 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13756 | tp->misc_host_ctrl); | |
1da177e4 LT |
13757 | |
13758 | tp->pci_chip_rev_id = (misc_ctrl_reg >> | |
13759 | MISC_HOST_CTRL_CHIPREV_SHIFT); | |
795d01c5 MC |
13760 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { |
13761 | u32 prod_id_asic_rev; | |
13762 | ||
5001e2f6 MC |
13763 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || |
13764 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
d78b59f5 MC |
13765 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || |
13766 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) | |
f6eb9b1f MC |
13767 | pci_read_config_dword(tp->pdev, |
13768 | TG3PCI_GEN2_PRODID_ASICREV, | |
13769 | &prod_id_asic_rev); | |
b703df6f MC |
13770 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || |
13771 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || | |
13772 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || | |
13773 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || | |
13774 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || | |
13775 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13776 | pci_read_config_dword(tp->pdev, | |
13777 | TG3PCI_GEN15_PRODID_ASICREV, | |
13778 | &prod_id_asic_rev); | |
f6eb9b1f MC |
13779 | else |
13780 | pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, | |
13781 | &prod_id_asic_rev); | |
13782 | ||
321d32a0 | 13783 | tp->pci_chip_rev_id = prod_id_asic_rev; |
795d01c5 | 13784 | } |
1da177e4 | 13785 | |
ff645bec MC |
13786 | /* Wrong chip ID in 5752 A0. This code can be removed later |
13787 | * as A0 is not in production. | |
13788 | */ | |
13789 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
13790 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
13791 | ||
6892914f MC |
13792 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, |
13793 | * we need to disable memory and use config. cycles | |
13794 | * only to access all registers. The 5702/03 chips | |
13795 | * can mistakenly decode the special cycles from the | |
13796 | * ICH chipsets as memory write cycles, causing corruption | |
13797 | * of register and memory space. Only certain ICH bridges | |
13798 | * will drive special cycles with non-zero data during the | |
13799 | * address phase which can fall within the 5703's address | |
13800 | * range. This is not an ICH bug as the PCI spec allows | |
13801 | * non-zero address during special cycles. However, only | |
13802 | * these ICH bridges are known to drive non-zero addresses | |
13803 | * during special cycles. | |
13804 | * | |
13805 | * Since special cycles do not cross PCI bridges, we only | |
13806 | * enable this workaround if the 5703 is on the secondary | |
13807 | * bus of these ICH bridges. | |
13808 | */ | |
13809 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
13810 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
13811 | static struct tg3_dev_id { | |
13812 | u32 vendor; | |
13813 | u32 device; | |
13814 | u32 rev; | |
13815 | } ich_chipsets[] = { | |
13816 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
13817 | PCI_ANY_ID }, | |
13818 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
13819 | PCI_ANY_ID }, | |
13820 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
13821 | 0xa }, | |
13822 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
13823 | PCI_ANY_ID }, | |
13824 | { }, | |
13825 | }; | |
13826 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
13827 | struct pci_dev *bridge = NULL; | |
13828 | ||
13829 | while (pci_id->vendor != 0) { | |
13830 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
13831 | bridge); | |
13832 | if (!bridge) { | |
13833 | pci_id++; | |
13834 | continue; | |
13835 | } | |
13836 | if (pci_id->rev != PCI_ANY_ID) { | |
44c10138 | 13837 | if (bridge->revision > pci_id->rev) |
6892914f MC |
13838 | continue; |
13839 | } | |
13840 | if (bridge->subordinate && | |
13841 | (bridge->subordinate->number == | |
13842 | tp->pdev->bus->number)) { | |
63c3a66f | 13843 | tg3_flag_set(tp, ICH_WORKAROUND); |
6892914f MC |
13844 | pci_dev_put(bridge); |
13845 | break; | |
13846 | } | |
13847 | } | |
13848 | } | |
13849 | ||
6ff6f81d | 13850 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { |
41588ba1 MC |
13851 | static struct tg3_dev_id { |
13852 | u32 vendor; | |
13853 | u32 device; | |
13854 | } bridge_chipsets[] = { | |
13855 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
13856 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
13857 | { }, | |
13858 | }; | |
13859 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
13860 | struct pci_dev *bridge = NULL; | |
13861 | ||
13862 | while (pci_id->vendor != 0) { | |
13863 | bridge = pci_get_device(pci_id->vendor, | |
13864 | pci_id->device, | |
13865 | bridge); | |
13866 | if (!bridge) { | |
13867 | pci_id++; | |
13868 | continue; | |
13869 | } | |
13870 | if (bridge->subordinate && | |
13871 | (bridge->subordinate->number <= | |
13872 | tp->pdev->bus->number) && | |
13873 | (bridge->subordinate->subordinate >= | |
13874 | tp->pdev->bus->number)) { | |
63c3a66f | 13875 | tg3_flag_set(tp, 5701_DMA_BUG); |
41588ba1 MC |
13876 | pci_dev_put(bridge); |
13877 | break; | |
13878 | } | |
13879 | } | |
13880 | } | |
13881 | ||
4a29cc2e MC |
13882 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support |
13883 | * DMA addresses > 40-bit. This bridge may have other additional | |
13884 | * 57xx devices behind it in some 4-port NIC designs for example. | |
13885 | * Any tg3 device found behind the bridge will also need the 40-bit | |
13886 | * DMA workaround. | |
13887 | */ | |
a4e2b347 MC |
13888 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
13889 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
63c3a66f JP |
13890 | tg3_flag_set(tp, 5780_CLASS); |
13891 | tg3_flag_set(tp, 40BIT_DMA_BUG); | |
4cf78e4f | 13892 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); |
859a5887 | 13893 | } else { |
4a29cc2e MC |
13894 | struct pci_dev *bridge = NULL; |
13895 | ||
13896 | do { | |
13897 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
13898 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
13899 | bridge); | |
13900 | if (bridge && bridge->subordinate && | |
13901 | (bridge->subordinate->number <= | |
13902 | tp->pdev->bus->number) && | |
13903 | (bridge->subordinate->subordinate >= | |
13904 | tp->pdev->bus->number)) { | |
63c3a66f | 13905 | tg3_flag_set(tp, 40BIT_DMA_BUG); |
4a29cc2e MC |
13906 | pci_dev_put(bridge); |
13907 | break; | |
13908 | } | |
13909 | } while (bridge); | |
13910 | } | |
4cf78e4f | 13911 | |
f6eb9b1f | 13912 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
3a1e19d3 | 13913 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) |
7544b097 MC |
13914 | tp->pdev_peer = tg3_find_peer(tp); |
13915 | ||
c885e824 | 13916 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
d78b59f5 MC |
13917 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13918 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
63c3a66f | 13919 | tg3_flag_set(tp, 5717_PLUS); |
0a58d668 MC |
13920 | |
13921 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || | |
63c3a66f JP |
13922 | tg3_flag(tp, 5717_PLUS)) |
13923 | tg3_flag_set(tp, 57765_PLUS); | |
c885e824 | 13924 | |
321d32a0 MC |
13925 | /* Intentionally exclude ASIC_REV_5906 */ |
13926 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
d9ab5ad1 | 13927 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
d30cdd28 | 13928 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
9936bcf6 | 13929 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c | 13930 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 13931 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
63c3a66f JP |
13932 | tg3_flag(tp, 57765_PLUS)) |
13933 | tg3_flag_set(tp, 5755_PLUS); | |
321d32a0 MC |
13934 | |
13935 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
13936 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
b5d3772c | 13937 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || |
63c3a66f JP |
13938 | tg3_flag(tp, 5755_PLUS) || |
13939 | tg3_flag(tp, 5780_CLASS)) | |
13940 | tg3_flag_set(tp, 5750_PLUS); | |
6708e5cc | 13941 | |
6ff6f81d | 13942 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
63c3a66f JP |
13943 | tg3_flag(tp, 5750_PLUS)) |
13944 | tg3_flag_set(tp, 5705_PLUS); | |
1b440c56 | 13945 | |
507399f1 | 13946 | /* Determine TSO capabilities */ |
a0512944 | 13947 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) |
4d163b75 | 13948 | ; /* Do nothing. HW bug. */ |
63c3a66f JP |
13949 | else if (tg3_flag(tp, 57765_PLUS)) |
13950 | tg3_flag_set(tp, HW_TSO_3); | |
13951 | else if (tg3_flag(tp, 5755_PLUS) || | |
e849cdc3 | 13952 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
63c3a66f JP |
13953 | tg3_flag_set(tp, HW_TSO_2); |
13954 | else if (tg3_flag(tp, 5750_PLUS)) { | |
13955 | tg3_flag_set(tp, HW_TSO_1); | |
13956 | tg3_flag_set(tp, TSO_BUG); | |
507399f1 MC |
13957 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && |
13958 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
63c3a66f | 13959 | tg3_flag_clear(tp, TSO_BUG); |
507399f1 MC |
13960 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
13961 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13962 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 13963 | tg3_flag_set(tp, TSO_BUG); |
507399f1 MC |
13964 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) |
13965 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
13966 | else | |
13967 | tp->fw_needed = FIRMWARE_TG3TSO; | |
13968 | } | |
13969 | ||
dabc5c67 | 13970 | /* Selectively allow TSO based on operating conditions */ |
6ff6f81d MC |
13971 | if (tg3_flag(tp, HW_TSO_1) || |
13972 | tg3_flag(tp, HW_TSO_2) || | |
13973 | tg3_flag(tp, HW_TSO_3) || | |
dabc5c67 MC |
13974 | (tp->fw_needed && !tg3_flag(tp, ENABLE_ASF))) |
13975 | tg3_flag_set(tp, TSO_CAPABLE); | |
13976 | else { | |
13977 | tg3_flag_clear(tp, TSO_CAPABLE); | |
13978 | tg3_flag_clear(tp, TSO_BUG); | |
13979 | tp->fw_needed = NULL; | |
13980 | } | |
13981 | ||
13982 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
13983 | tp->fw_needed = FIRMWARE_TG3; | |
13984 | ||
507399f1 MC |
13985 | tp->irq_max = 1; |
13986 | ||
63c3a66f JP |
13987 | if (tg3_flag(tp, 5750_PLUS)) { |
13988 | tg3_flag_set(tp, SUPPORT_MSI); | |
7544b097 MC |
13989 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || |
13990 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
13991 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
13992 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
13993 | tp->pdev_peer == tp->pdev)) | |
63c3a66f | 13994 | tg3_flag_clear(tp, SUPPORT_MSI); |
7544b097 | 13995 | |
63c3a66f | 13996 | if (tg3_flag(tp, 5755_PLUS) || |
b5d3772c | 13997 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
63c3a66f | 13998 | tg3_flag_set(tp, 1SHOT_MSI); |
52c0fd83 | 13999 | } |
4f125f42 | 14000 | |
63c3a66f JP |
14001 | if (tg3_flag(tp, 57765_PLUS)) { |
14002 | tg3_flag_set(tp, SUPPORT_MSIX); | |
507399f1 MC |
14003 | tp->irq_max = TG3_IRQ_MAX_VECS; |
14004 | } | |
f6eb9b1f | 14005 | } |
0e1406dd | 14006 | |
2ffcc981 | 14007 | if (tg3_flag(tp, 5755_PLUS)) |
63c3a66f | 14008 | tg3_flag_set(tp, SHORT_DMA_BUG); |
f6eb9b1f | 14009 | |
e31aa987 MC |
14010 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
14011 | tg3_flag_set(tp, 4K_FIFO_LIMIT); | |
14012 | ||
63c3a66f JP |
14013 | if (tg3_flag(tp, 5717_PLUS)) |
14014 | tg3_flag_set(tp, LRG_PROD_RING_CAP); | |
de9f5230 | 14015 | |
63c3a66f | 14016 | if (tg3_flag(tp, 57765_PLUS) && |
a0512944 | 14017 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0) |
63c3a66f | 14018 | tg3_flag_set(tp, USE_JUMBO_BDFLAG); |
b703df6f | 14019 | |
63c3a66f JP |
14020 | if (!tg3_flag(tp, 5705_PLUS) || |
14021 | tg3_flag(tp, 5780_CLASS) || | |
14022 | tg3_flag(tp, USE_JUMBO_BDFLAG)) | |
14023 | tg3_flag_set(tp, JUMBO_CAPABLE); | |
0f893dc6 | 14024 | |
52f4490c MC |
14025 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
14026 | &pci_state_reg); | |
14027 | ||
708ebb3a | 14028 | if (pci_is_pcie(tp->pdev)) { |
5e7dfd0f MC |
14029 | u16 lnkctl; |
14030 | ||
63c3a66f | 14031 | tg3_flag_set(tp, PCI_EXPRESS); |
5f5c51e3 | 14032 | |
cf79003d | 14033 | tp->pcie_readrq = 4096; |
d78b59f5 MC |
14034 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
14035 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
b4495ed8 | 14036 | tp->pcie_readrq = 2048; |
cf79003d MC |
14037 | |
14038 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); | |
5f5c51e3 | 14039 | |
5e7dfd0f | 14040 | pci_read_config_word(tp->pdev, |
708ebb3a | 14041 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
14042 | &lnkctl); |
14043 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | |
7196cd6c MC |
14044 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
14045 | ASIC_REV_5906) { | |
63c3a66f | 14046 | tg3_flag_clear(tp, HW_TSO_2); |
dabc5c67 | 14047 | tg3_flag_clear(tp, TSO_CAPABLE); |
7196cd6c | 14048 | } |
5e7dfd0f | 14049 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 | 14050 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9cf74ebb MC |
14051 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || |
14052 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
63c3a66f | 14053 | tg3_flag_set(tp, CLKREQ_BUG); |
614b0590 | 14054 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { |
63c3a66f | 14055 | tg3_flag_set(tp, L1PLLPD_EN); |
c7835a77 | 14056 | } |
52f4490c | 14057 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
708ebb3a JM |
14058 | /* BCM5785 devices are effectively PCIe devices, and should |
14059 | * follow PCIe codepaths, but do not have a PCIe capabilities | |
14060 | * section. | |
93a700a9 | 14061 | */ |
63c3a66f JP |
14062 | tg3_flag_set(tp, PCI_EXPRESS); |
14063 | } else if (!tg3_flag(tp, 5705_PLUS) || | |
14064 | tg3_flag(tp, 5780_CLASS)) { | |
52f4490c MC |
14065 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); |
14066 | if (!tp->pcix_cap) { | |
2445e461 MC |
14067 | dev_err(&tp->pdev->dev, |
14068 | "Cannot find PCI-X capability, aborting\n"); | |
52f4490c MC |
14069 | return -EIO; |
14070 | } | |
14071 | ||
14072 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
63c3a66f | 14073 | tg3_flag_set(tp, PCIX_MODE); |
52f4490c | 14074 | } |
1da177e4 | 14075 | |
399de50b MC |
14076 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
14077 | * reordering to the mailbox registers done by the host | |
14078 | * controller can cause major troubles. We read back from | |
14079 | * every mailbox register write to force the writes to be | |
14080 | * posted to the chip in order. | |
14081 | */ | |
4143470c | 14082 | if (pci_dev_present(tg3_write_reorder_chipsets) && |
63c3a66f JP |
14083 | !tg3_flag(tp, PCI_EXPRESS)) |
14084 | tg3_flag_set(tp, MBOX_WRITE_REORDER); | |
399de50b | 14085 | |
69fc4053 MC |
14086 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
14087 | &tp->pci_cacheline_sz); | |
14088 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
14089 | &tp->pci_lat_timer); | |
1da177e4 LT |
14090 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
14091 | tp->pci_lat_timer < 64) { | |
14092 | tp->pci_lat_timer = 64; | |
69fc4053 MC |
14093 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
14094 | tp->pci_lat_timer); | |
1da177e4 LT |
14095 | } |
14096 | ||
16821285 MC |
14097 | /* Important! -- It is critical that the PCI-X hw workaround |
14098 | * situation is decided before the first MMIO register access. | |
14099 | */ | |
52f4490c MC |
14100 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
14101 | /* 5700 BX chips need to have their TX producer index | |
14102 | * mailboxes written twice to workaround a bug. | |
14103 | */ | |
63c3a66f | 14104 | tg3_flag_set(tp, TXD_MBOX_HWBUG); |
1da177e4 | 14105 | |
52f4490c | 14106 | /* If we are in PCI-X mode, enable register write workaround. |
1da177e4 LT |
14107 | * |
14108 | * The workaround is to use indirect register accesses | |
14109 | * for all chip writes not to mailbox registers. | |
14110 | */ | |
63c3a66f | 14111 | if (tg3_flag(tp, PCIX_MODE)) { |
1da177e4 | 14112 | u32 pm_reg; |
1da177e4 | 14113 | |
63c3a66f | 14114 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
1da177e4 LT |
14115 | |
14116 | /* The chip can have it's power management PCI config | |
14117 | * space registers clobbered due to this bug. | |
14118 | * So explicitly force the chip into D0 here. | |
14119 | */ | |
9974a356 MC |
14120 | pci_read_config_dword(tp->pdev, |
14121 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
14122 | &pm_reg); |
14123 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
14124 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
9974a356 MC |
14125 | pci_write_config_dword(tp->pdev, |
14126 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
14127 | pm_reg); |
14128 | ||
14129 | /* Also, force SERR#/PERR# in PCI command. */ | |
14130 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
14131 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
14132 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
14133 | } | |
14134 | } | |
14135 | ||
1da177e4 | 14136 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) |
63c3a66f | 14137 | tg3_flag_set(tp, PCI_HIGH_SPEED); |
1da177e4 | 14138 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) |
63c3a66f | 14139 | tg3_flag_set(tp, PCI_32BIT); |
1da177e4 LT |
14140 | |
14141 | /* Chip-specific fixup from Broadcom driver */ | |
14142 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
14143 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
14144 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
14145 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
14146 | } | |
14147 | ||
1ee582d8 | 14148 | /* Default fast path register access methods */ |
20094930 | 14149 | tp->read32 = tg3_read32; |
1ee582d8 | 14150 | tp->write32 = tg3_write32; |
09ee929c | 14151 | tp->read32_mbox = tg3_read32; |
20094930 | 14152 | tp->write32_mbox = tg3_write32; |
1ee582d8 MC |
14153 | tp->write32_tx_mbox = tg3_write32; |
14154 | tp->write32_rx_mbox = tg3_write32; | |
14155 | ||
14156 | /* Various workaround register access methods */ | |
63c3a66f | 14157 | if (tg3_flag(tp, PCIX_TARGET_HWBUG)) |
1ee582d8 | 14158 | tp->write32 = tg3_write_indirect_reg32; |
98efd8a6 | 14159 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
63c3a66f | 14160 | (tg3_flag(tp, PCI_EXPRESS) && |
98efd8a6 MC |
14161 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { |
14162 | /* | |
14163 | * Back to back register writes can cause problems on these | |
14164 | * chips, the workaround is to read back all reg writes | |
14165 | * except those to mailbox regs. | |
14166 | * | |
14167 | * See tg3_write_indirect_reg32(). | |
14168 | */ | |
1ee582d8 | 14169 | tp->write32 = tg3_write_flush_reg32; |
98efd8a6 MC |
14170 | } |
14171 | ||
63c3a66f | 14172 | if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { |
1ee582d8 | 14173 | tp->write32_tx_mbox = tg3_write32_tx_mbox; |
63c3a66f | 14174 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
1ee582d8 MC |
14175 | tp->write32_rx_mbox = tg3_write_flush_reg32; |
14176 | } | |
20094930 | 14177 | |
63c3a66f | 14178 | if (tg3_flag(tp, ICH_WORKAROUND)) { |
6892914f MC |
14179 | tp->read32 = tg3_read_indirect_reg32; |
14180 | tp->write32 = tg3_write_indirect_reg32; | |
14181 | tp->read32_mbox = tg3_read_indirect_mbox; | |
14182 | tp->write32_mbox = tg3_write_indirect_mbox; | |
14183 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
14184 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
14185 | ||
14186 | iounmap(tp->regs); | |
22abe310 | 14187 | tp->regs = NULL; |
6892914f MC |
14188 | |
14189 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
14190 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
14191 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
14192 | } | |
b5d3772c MC |
14193 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
14194 | tp->read32_mbox = tg3_read32_mbox_5906; | |
14195 | tp->write32_mbox = tg3_write32_mbox_5906; | |
14196 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
14197 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
14198 | } | |
6892914f | 14199 | |
bbadf503 | 14200 | if (tp->write32 == tg3_write_indirect_reg32 || |
63c3a66f | 14201 | (tg3_flag(tp, PCIX_MODE) && |
bbadf503 | 14202 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
f49639e6 | 14203 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
63c3a66f | 14204 | tg3_flag_set(tp, SRAM_USE_CONFIG); |
bbadf503 | 14205 | |
16821285 MC |
14206 | /* The memory arbiter has to be enabled in order for SRAM accesses |
14207 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
14208 | * sure it is enabled, but other entities such as system netboot | |
14209 | * code might disable it. | |
14210 | */ | |
14211 | val = tr32(MEMARB_MODE); | |
14212 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
14213 | ||
9dc5e342 MC |
14214 | tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; |
14215 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
14216 | tg3_flag(tp, 5780_CLASS)) { | |
14217 | if (tg3_flag(tp, PCIX_MODE)) { | |
14218 | pci_read_config_dword(tp->pdev, | |
14219 | tp->pcix_cap + PCI_X_STATUS, | |
14220 | &val); | |
14221 | tp->pci_fn = val & 0x7; | |
14222 | } | |
14223 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { | |
14224 | tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); | |
14225 | if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) == | |
14226 | NIC_SRAM_CPMUSTAT_SIG) { | |
14227 | tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717; | |
14228 | tp->pci_fn = tp->pci_fn ? 1 : 0; | |
14229 | } | |
14230 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
14231 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
14232 | tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); | |
14233 | if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) == | |
14234 | NIC_SRAM_CPMUSTAT_SIG) { | |
14235 | tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> | |
14236 | TG3_CPMU_STATUS_FSHFT_5719; | |
14237 | } | |
69f11c99 MC |
14238 | } |
14239 | ||
7d0c41ef | 14240 | /* Get eeprom hw config before calling tg3_set_power_state(). |
63c3a66f | 14241 | * In particular, the TG3_FLAG_IS_NIC flag must be |
7d0c41ef MC |
14242 | * determined before calling tg3_set_power_state() so that |
14243 | * we know whether or not to switch out of Vaux power. | |
14244 | * When the flag is set, it means that GPIO1 is used for eeprom | |
14245 | * write protect and also implies that it is a LOM where GPIOs | |
14246 | * are not used to switch power. | |
6aa20a22 | 14247 | */ |
7d0c41ef MC |
14248 | tg3_get_eeprom_hw_cfg(tp); |
14249 | ||
63c3a66f | 14250 | if (tg3_flag(tp, ENABLE_APE)) { |
0d3031d9 MC |
14251 | /* Allow reads and writes to the |
14252 | * APE register and memory space. | |
14253 | */ | |
14254 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
14255 | PCISTATE_ALLOW_APE_SHMEM_WR | |
14256 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
14257 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, |
14258 | pci_state_reg); | |
c9cab24e MC |
14259 | |
14260 | tg3_ape_lock_init(tp); | |
0d3031d9 MC |
14261 | } |
14262 | ||
9936bcf6 | 14263 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
57e6983c | 14264 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
321d32a0 | 14265 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 14266 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
63c3a66f JP |
14267 | tg3_flag(tp, 57765_PLUS)) |
14268 | tg3_flag_set(tp, CPMU_PRESENT); | |
d30cdd28 | 14269 | |
16821285 MC |
14270 | /* Set up tp->grc_local_ctrl before calling |
14271 | * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high | |
14272 | * will bring 5700's external PHY out of reset. | |
314fba34 MC |
14273 | * It is also used as eeprom write protect on LOMs. |
14274 | */ | |
14275 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
6ff6f81d | 14276 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
63c3a66f | 14277 | tg3_flag(tp, EEPROM_WRITE_PROT)) |
314fba34 MC |
14278 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
14279 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
3e7d83bc MC |
14280 | /* Unused GPIO3 must be driven as output on 5752 because there |
14281 | * are no pull-up resistors on unused GPIO pins. | |
14282 | */ | |
14283 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
14284 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
314fba34 | 14285 | |
321d32a0 | 14286 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
cb4ed1fd MC |
14287 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
14288 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
af36e6b6 MC |
14289 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
14290 | ||
8d519ab2 MC |
14291 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
14292 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
14293 | /* Turn off the debug UART. */ |
14294 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
63c3a66f | 14295 | if (tg3_flag(tp, IS_NIC)) |
5f0c4a3c MC |
14296 | /* Keep VMain power. */ |
14297 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
14298 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
14299 | } | |
14300 | ||
16821285 MC |
14301 | /* Switch out of Vaux if it is a NIC */ |
14302 | tg3_pwrsrc_switch_to_vmain(tp); | |
1da177e4 | 14303 | |
1da177e4 LT |
14304 | /* Derive initial jumbo mode from MTU assigned in |
14305 | * ether_setup() via the alloc_etherdev() call | |
14306 | */ | |
63c3a66f JP |
14307 | if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) |
14308 | tg3_flag_set(tp, JUMBO_RING_ENABLE); | |
1da177e4 LT |
14309 | |
14310 | /* Determine WakeOnLan speed to use. */ | |
14311 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14312 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
14313 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
14314 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
63c3a66f | 14315 | tg3_flag_clear(tp, WOL_SPEED_100MB); |
1da177e4 | 14316 | } else { |
63c3a66f | 14317 | tg3_flag_set(tp, WOL_SPEED_100MB); |
1da177e4 LT |
14318 | } |
14319 | ||
7f97a4bd | 14320 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
f07e9af3 | 14321 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
7f97a4bd | 14322 | |
1da177e4 | 14323 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
6ff6f81d MC |
14324 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
14325 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
1da177e4 | 14326 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && |
747e8f8b | 14327 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
f07e9af3 MC |
14328 | (tp->phy_flags & TG3_PHYFLG_IS_FET) || |
14329 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
14330 | tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; | |
1da177e4 LT |
14331 | |
14332 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
14333 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
f07e9af3 | 14334 | tp->phy_flags |= TG3_PHYFLG_ADC_BUG; |
1da177e4 | 14335 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) |
f07e9af3 | 14336 | tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; |
1da177e4 | 14337 | |
63c3a66f | 14338 | if (tg3_flag(tp, 5705_PLUS) && |
f07e9af3 | 14339 | !(tp->phy_flags & TG3_PHYFLG_IS_FET) && |
321d32a0 | 14340 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
f6eb9b1f | 14341 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && |
63c3a66f | 14342 | !tg3_flag(tp, 57765_PLUS)) { |
c424cb24 | 14343 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
d30cdd28 | 14344 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
9936bcf6 MC |
14345 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
14346 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
d4011ada MC |
14347 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
14348 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
f07e9af3 | 14349 | tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; |
c1d2a196 | 14350 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) |
f07e9af3 | 14351 | tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; |
321d32a0 | 14352 | } else |
f07e9af3 | 14353 | tp->phy_flags |= TG3_PHYFLG_BER_BUG; |
c424cb24 | 14354 | } |
1da177e4 | 14355 | |
b2a5c19c MC |
14356 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
14357 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
14358 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
14359 | if (tp->phy_otp == 0) | |
14360 | tp->phy_otp = TG3_OTP_DEFAULT; | |
14361 | } | |
14362 | ||
63c3a66f | 14363 | if (tg3_flag(tp, CPMU_PRESENT)) |
8ef21428 MC |
14364 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
14365 | else | |
14366 | tp->mi_mode = MAC_MI_MODE_BASE; | |
14367 | ||
1da177e4 | 14368 | tp->coalesce_mode = 0; |
1da177e4 LT |
14369 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
14370 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
14371 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
14372 | ||
4d958473 MC |
14373 | /* Set these bits to enable statistics workaround. */ |
14374 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
14375 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
14376 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) { | |
14377 | tp->coalesce_mode |= HOSTCC_MODE_ATTN; | |
14378 | tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; | |
14379 | } | |
14380 | ||
321d32a0 MC |
14381 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
14382 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
63c3a66f | 14383 | tg3_flag_set(tp, USE_PHYLIB); |
57e6983c | 14384 | |
158d7abd MC |
14385 | err = tg3_mdio_init(tp); |
14386 | if (err) | |
14387 | return err; | |
1da177e4 LT |
14388 | |
14389 | /* Initialize data/descriptor byte/word swapping. */ | |
14390 | val = tr32(GRC_MODE); | |
f2096f94 MC |
14391 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
14392 | val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA | | |
14393 | GRC_MODE_WORD_SWAP_B2HRX_DATA | | |
14394 | GRC_MODE_B2HRX_ENABLE | | |
14395 | GRC_MODE_HTX2B_ENABLE | | |
14396 | GRC_MODE_HOST_STACKUP); | |
14397 | else | |
14398 | val &= GRC_MODE_HOST_STACKUP; | |
14399 | ||
1da177e4 LT |
14400 | tw32(GRC_MODE, val | tp->grc_mode); |
14401 | ||
14402 | tg3_switch_clocks(tp); | |
14403 | ||
14404 | /* Clear this out for sanity. */ | |
14405 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14406 | ||
14407 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
14408 | &pci_state_reg); | |
14409 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
63c3a66f | 14410 | !tg3_flag(tp, PCIX_TARGET_HWBUG)) { |
1da177e4 LT |
14411 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); |
14412 | ||
14413 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
14414 | chiprevid == CHIPREV_ID_5701_B0 || | |
14415 | chiprevid == CHIPREV_ID_5701_B2 || | |
14416 | chiprevid == CHIPREV_ID_5701_B5) { | |
14417 | void __iomem *sram_base; | |
14418 | ||
14419 | /* Write some dummy words into the SRAM status block | |
14420 | * area, see if it reads back correctly. If the return | |
14421 | * value is bad, force enable the PCIX workaround. | |
14422 | */ | |
14423 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
14424 | ||
14425 | writel(0x00000000, sram_base); | |
14426 | writel(0x00000000, sram_base + 4); | |
14427 | writel(0xffffffff, sram_base + 4); | |
14428 | if (readl(sram_base) != 0x00000000) | |
63c3a66f | 14429 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
1da177e4 LT |
14430 | } |
14431 | } | |
14432 | ||
14433 | udelay(50); | |
14434 | tg3_nvram_init(tp); | |
14435 | ||
14436 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
14437 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
14438 | ||
1da177e4 LT |
14439 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
14440 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
14441 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
63c3a66f | 14442 | tg3_flag_set(tp, IS_5788); |
1da177e4 | 14443 | |
63c3a66f | 14444 | if (!tg3_flag(tp, IS_5788) && |
6ff6f81d | 14445 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
63c3a66f JP |
14446 | tg3_flag_set(tp, TAGGED_STATUS); |
14447 | if (tg3_flag(tp, TAGGED_STATUS)) { | |
fac9b83e DM |
14448 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | |
14449 | HOSTCC_MODE_CLRTICK_TXBD); | |
14450 | ||
14451 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
14452 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
14453 | tp->misc_host_ctrl); | |
14454 | } | |
14455 | ||
3bda1258 | 14456 | /* Preserve the APE MAC_MODE bits */ |
63c3a66f | 14457 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b | 14458 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 | 14459 | else |
6e01b20b | 14460 | tp->mac_mode = 0; |
3bda1258 | 14461 | |
1da177e4 LT |
14462 | /* these are limited to 10/100 only */ |
14463 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
14464 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
14465 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
14466 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14467 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || | |
14468 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || | |
14469 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || | |
14470 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14471 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || | |
676917d4 MC |
14472 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || |
14473 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | |
321d32a0 | 14474 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || |
d1101142 MC |
14475 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || |
14476 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || | |
f07e9af3 MC |
14477 | (tp->phy_flags & TG3_PHYFLG_IS_FET)) |
14478 | tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; | |
1da177e4 LT |
14479 | |
14480 | err = tg3_phy_probe(tp); | |
14481 | if (err) { | |
2445e461 | 14482 | dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); |
1da177e4 | 14483 | /* ... but do not return immediately ... */ |
b02fd9e3 | 14484 | tg3_mdio_fini(tp); |
1da177e4 LT |
14485 | } |
14486 | ||
184b8904 | 14487 | tg3_read_vpd(tp); |
c4e6575c | 14488 | tg3_read_fw_ver(tp); |
1da177e4 | 14489 | |
f07e9af3 MC |
14490 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
14491 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; | |
1da177e4 LT |
14492 | } else { |
14493 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
f07e9af3 | 14494 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 | 14495 | else |
f07e9af3 | 14496 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 LT |
14497 | } |
14498 | ||
14499 | /* 5700 {AX,BX} chips have a broken status block link | |
14500 | * change bit implementation, so we must use the | |
14501 | * status register in those cases. | |
14502 | */ | |
14503 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
63c3a66f | 14504 | tg3_flag_set(tp, USE_LINKCHG_REG); |
1da177e4 | 14505 | else |
63c3a66f | 14506 | tg3_flag_clear(tp, USE_LINKCHG_REG); |
1da177e4 LT |
14507 | |
14508 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
14509 | * have to force the link status polling mechanism based | |
14510 | * upon subsystem IDs. | |
14511 | */ | |
14512 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
007a880d | 14513 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
f07e9af3 MC |
14514 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
14515 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; | |
63c3a66f | 14516 | tg3_flag_set(tp, USE_LINKCHG_REG); |
1da177e4 LT |
14517 | } |
14518 | ||
14519 | /* For all SERDES we poll the MAC status register. */ | |
f07e9af3 | 14520 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
63c3a66f | 14521 | tg3_flag_set(tp, POLL_SERDES); |
1da177e4 | 14522 | else |
63c3a66f | 14523 | tg3_flag_clear(tp, POLL_SERDES); |
1da177e4 | 14524 | |
bf933c80 | 14525 | tp->rx_offset = NET_IP_ALIGN; |
d2757fc4 | 14526 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; |
1da177e4 | 14527 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
63c3a66f | 14528 | tg3_flag(tp, PCIX_MODE)) { |
bf933c80 | 14529 | tp->rx_offset = 0; |
d2757fc4 | 14530 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
9dc7a113 | 14531 | tp->rx_copy_thresh = ~(u16)0; |
d2757fc4 MC |
14532 | #endif |
14533 | } | |
1da177e4 | 14534 | |
2c49a44d MC |
14535 | tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; |
14536 | tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; | |
7cb32cf2 MC |
14537 | tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; |
14538 | ||
2c49a44d | 14539 | tp->rx_std_max_post = tp->rx_std_ring_mask + 1; |
f92905de MC |
14540 | |
14541 | /* Increment the rx prod index on the rx std ring by at most | |
14542 | * 8 for these chips to workaround hw errata. | |
14543 | */ | |
14544 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
14545 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
14546 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
14547 | tp->rx_std_max_post = 8; | |
14548 | ||
63c3a66f | 14549 | if (tg3_flag(tp, ASPM_WORKAROUND)) |
8ed5d97e MC |
14550 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & |
14551 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
14552 | ||
1da177e4 LT |
14553 | return err; |
14554 | } | |
14555 | ||
49b6e95f | 14556 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14557 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) |
14558 | { | |
14559 | struct net_device *dev = tp->dev; | |
14560 | struct pci_dev *pdev = tp->pdev; | |
49b6e95f | 14561 | struct device_node *dp = pci_device_to_OF_node(pdev); |
374d4cac | 14562 | const unsigned char *addr; |
49b6e95f DM |
14563 | int len; |
14564 | ||
14565 | addr = of_get_property(dp, "local-mac-address", &len); | |
14566 | if (addr && len == 6) { | |
14567 | memcpy(dev->dev_addr, addr, 6); | |
14568 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
14569 | return 0; | |
1da177e4 LT |
14570 | } |
14571 | return -ENODEV; | |
14572 | } | |
14573 | ||
14574 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
14575 | { | |
14576 | struct net_device *dev = tp->dev; | |
14577 | ||
14578 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
2ff43697 | 14579 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); |
1da177e4 LT |
14580 | return 0; |
14581 | } | |
14582 | #endif | |
14583 | ||
14584 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
14585 | { | |
14586 | struct net_device *dev = tp->dev; | |
14587 | u32 hi, lo, mac_offset; | |
008652b3 | 14588 | int addr_ok = 0; |
1da177e4 | 14589 | |
49b6e95f | 14590 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14591 | if (!tg3_get_macaddr_sparc(tp)) |
14592 | return 0; | |
14593 | #endif | |
14594 | ||
14595 | mac_offset = 0x7c; | |
6ff6f81d | 14596 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
63c3a66f | 14597 | tg3_flag(tp, 5780_CLASS)) { |
1da177e4 LT |
14598 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
14599 | mac_offset = 0xcc; | |
14600 | if (tg3_nvram_lock(tp)) | |
14601 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
14602 | else | |
14603 | tg3_nvram_unlock(tp); | |
63c3a66f | 14604 | } else if (tg3_flag(tp, 5717_PLUS)) { |
69f11c99 | 14605 | if (tp->pci_fn & 1) |
a1b950d5 | 14606 | mac_offset = 0xcc; |
69f11c99 | 14607 | if (tp->pci_fn > 1) |
a50d0796 | 14608 | mac_offset += 0x18c; |
a1b950d5 | 14609 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
b5d3772c | 14610 | mac_offset = 0x10; |
1da177e4 LT |
14611 | |
14612 | /* First try to get it from MAC address mailbox. */ | |
14613 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
14614 | if ((hi >> 16) == 0x484b) { | |
14615 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14616 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
14617 | ||
14618 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
14619 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14620 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14621 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14622 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
1da177e4 | 14623 | |
008652b3 MC |
14624 | /* Some old bootcode may report a 0 MAC address in SRAM */ |
14625 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
14626 | } | |
14627 | if (!addr_ok) { | |
14628 | /* Next, try NVRAM. */ | |
63c3a66f | 14629 | if (!tg3_flag(tp, NO_NVRAM) && |
df259d8c | 14630 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && |
6d348f2c | 14631 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { |
62cedd11 MC |
14632 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); |
14633 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
008652b3 MC |
14634 | } |
14635 | /* Finally just fetch it out of the MAC control regs. */ | |
14636 | else { | |
14637 | hi = tr32(MAC_ADDR_0_HIGH); | |
14638 | lo = tr32(MAC_ADDR_0_LOW); | |
14639 | ||
14640 | dev->dev_addr[5] = lo & 0xff; | |
14641 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14642 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14643 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14644 | dev->dev_addr[1] = hi & 0xff; | |
14645 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14646 | } | |
1da177e4 LT |
14647 | } |
14648 | ||
14649 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
7582a335 | 14650 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14651 | if (!tg3_get_default_macaddr_sparc(tp)) |
14652 | return 0; | |
14653 | #endif | |
14654 | return -EINVAL; | |
14655 | } | |
2ff43697 | 14656 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
14657 | return 0; |
14658 | } | |
14659 | ||
59e6b434 DM |
14660 | #define BOUNDARY_SINGLE_CACHELINE 1 |
14661 | #define BOUNDARY_MULTI_CACHELINE 2 | |
14662 | ||
14663 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
14664 | { | |
14665 | int cacheline_size; | |
14666 | u8 byte; | |
14667 | int goal; | |
14668 | ||
14669 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
14670 | if (byte == 0) | |
14671 | cacheline_size = 1024; | |
14672 | else | |
14673 | cacheline_size = (int) byte * 4; | |
14674 | ||
14675 | /* On 5703 and later chips, the boundary bits have no | |
14676 | * effect. | |
14677 | */ | |
14678 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
14679 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
63c3a66f | 14680 | !tg3_flag(tp, PCI_EXPRESS)) |
59e6b434 DM |
14681 | goto out; |
14682 | ||
14683 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
14684 | goal = BOUNDARY_MULTI_CACHELINE; | |
14685 | #else | |
14686 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
14687 | goal = BOUNDARY_SINGLE_CACHELINE; | |
14688 | #else | |
14689 | goal = 0; | |
14690 | #endif | |
14691 | #endif | |
14692 | ||
63c3a66f | 14693 | if (tg3_flag(tp, 57765_PLUS)) { |
cbf9ca6c MC |
14694 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
14695 | goto out; | |
14696 | } | |
14697 | ||
59e6b434 DM |
14698 | if (!goal) |
14699 | goto out; | |
14700 | ||
14701 | /* PCI controllers on most RISC systems tend to disconnect | |
14702 | * when a device tries to burst across a cache-line boundary. | |
14703 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
14704 | * | |
14705 | * Unfortunately, for PCI-E there are only limited | |
14706 | * write-side controls for this, and thus for reads | |
14707 | * we will still get the disconnects. We'll also waste | |
14708 | * these PCI cycles for both read and write for chips | |
14709 | * other than 5700 and 5701 which do not implement the | |
14710 | * boundary bits. | |
14711 | */ | |
63c3a66f | 14712 | if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { |
59e6b434 DM |
14713 | switch (cacheline_size) { |
14714 | case 16: | |
14715 | case 32: | |
14716 | case 64: | |
14717 | case 128: | |
14718 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14719 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
14720 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
14721 | } else { | |
14722 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14723 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14724 | } | |
14725 | break; | |
14726 | ||
14727 | case 256: | |
14728 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
14729 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
14730 | break; | |
14731 | ||
14732 | default: | |
14733 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14734 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14735 | break; | |
855e1111 | 14736 | } |
63c3a66f | 14737 | } else if (tg3_flag(tp, PCI_EXPRESS)) { |
59e6b434 DM |
14738 | switch (cacheline_size) { |
14739 | case 16: | |
14740 | case 32: | |
14741 | case 64: | |
14742 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14743 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14744 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
14745 | break; | |
14746 | } | |
14747 | /* fallthrough */ | |
14748 | case 128: | |
14749 | default: | |
14750 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14751 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
14752 | break; | |
855e1111 | 14753 | } |
59e6b434 DM |
14754 | } else { |
14755 | switch (cacheline_size) { | |
14756 | case 16: | |
14757 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14758 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
14759 | DMA_RWCTRL_WRITE_BNDRY_16); | |
14760 | break; | |
14761 | } | |
14762 | /* fallthrough */ | |
14763 | case 32: | |
14764 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14765 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
14766 | DMA_RWCTRL_WRITE_BNDRY_32); | |
14767 | break; | |
14768 | } | |
14769 | /* fallthrough */ | |
14770 | case 64: | |
14771 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14772 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
14773 | DMA_RWCTRL_WRITE_BNDRY_64); | |
14774 | break; | |
14775 | } | |
14776 | /* fallthrough */ | |
14777 | case 128: | |
14778 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14779 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
14780 | DMA_RWCTRL_WRITE_BNDRY_128); | |
14781 | break; | |
14782 | } | |
14783 | /* fallthrough */ | |
14784 | case 256: | |
14785 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
14786 | DMA_RWCTRL_WRITE_BNDRY_256); | |
14787 | break; | |
14788 | case 512: | |
14789 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
14790 | DMA_RWCTRL_WRITE_BNDRY_512); | |
14791 | break; | |
14792 | case 1024: | |
14793 | default: | |
14794 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
14795 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
14796 | break; | |
855e1111 | 14797 | } |
59e6b434 DM |
14798 | } |
14799 | ||
14800 | out: | |
14801 | return val; | |
14802 | } | |
14803 | ||
1da177e4 LT |
14804 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) |
14805 | { | |
14806 | struct tg3_internal_buffer_desc test_desc; | |
14807 | u32 sram_dma_descs; | |
14808 | int i, ret; | |
14809 | ||
14810 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
14811 | ||
14812 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
14813 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
14814 | tw32(RDMAC_STATUS, 0); | |
14815 | tw32(WDMAC_STATUS, 0); | |
14816 | ||
14817 | tw32(BUFMGR_MODE, 0); | |
14818 | tw32(FTQ_RESET, 0); | |
14819 | ||
14820 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
14821 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
14822 | test_desc.nic_mbuf = 0x00002100; | |
14823 | test_desc.len = size; | |
14824 | ||
14825 | /* | |
14826 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
14827 | * the *second* time the tg3 driver was getting loaded after an | |
14828 | * initial scan. | |
14829 | * | |
14830 | * Broadcom tells me: | |
14831 | * ...the DMA engine is connected to the GRC block and a DMA | |
14832 | * reset may affect the GRC block in some unpredictable way... | |
14833 | * The behavior of resets to individual blocks has not been tested. | |
14834 | * | |
14835 | * Broadcom noted the GRC reset will also reset all sub-components. | |
14836 | */ | |
14837 | if (to_device) { | |
14838 | test_desc.cqid_sqid = (13 << 8) | 2; | |
14839 | ||
14840 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
14841 | udelay(40); | |
14842 | } else { | |
14843 | test_desc.cqid_sqid = (16 << 8) | 7; | |
14844 | ||
14845 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
14846 | udelay(40); | |
14847 | } | |
14848 | test_desc.flags = 0x00000005; | |
14849 | ||
14850 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
14851 | u32 val; | |
14852 | ||
14853 | val = *(((u32 *)&test_desc) + i); | |
14854 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
14855 | sram_dma_descs + (i * sizeof(u32))); | |
14856 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
14857 | } | |
14858 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14859 | ||
859a5887 | 14860 | if (to_device) |
1da177e4 | 14861 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); |
859a5887 | 14862 | else |
1da177e4 | 14863 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); |
1da177e4 LT |
14864 | |
14865 | ret = -ENODEV; | |
14866 | for (i = 0; i < 40; i++) { | |
14867 | u32 val; | |
14868 | ||
14869 | if (to_device) | |
14870 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
14871 | else | |
14872 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
14873 | if ((val & 0xffff) == sram_dma_descs) { | |
14874 | ret = 0; | |
14875 | break; | |
14876 | } | |
14877 | ||
14878 | udelay(100); | |
14879 | } | |
14880 | ||
14881 | return ret; | |
14882 | } | |
14883 | ||
ded7340d | 14884 | #define TEST_BUFFER_SIZE 0x2000 |
1da177e4 | 14885 | |
4143470c | 14886 | static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = { |
895950c2 JP |
14887 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, |
14888 | { }, | |
14889 | }; | |
14890 | ||
1da177e4 LT |
14891 | static int __devinit tg3_test_dma(struct tg3 *tp) |
14892 | { | |
14893 | dma_addr_t buf_dma; | |
59e6b434 | 14894 | u32 *buf, saved_dma_rwctrl; |
cbf9ca6c | 14895 | int ret = 0; |
1da177e4 | 14896 | |
4bae65c8 MC |
14897 | buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, |
14898 | &buf_dma, GFP_KERNEL); | |
1da177e4 LT |
14899 | if (!buf) { |
14900 | ret = -ENOMEM; | |
14901 | goto out_nofree; | |
14902 | } | |
14903 | ||
14904 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
14905 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
14906 | ||
59e6b434 | 14907 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
1da177e4 | 14908 | |
63c3a66f | 14909 | if (tg3_flag(tp, 57765_PLUS)) |
cbf9ca6c MC |
14910 | goto out; |
14911 | ||
63c3a66f | 14912 | if (tg3_flag(tp, PCI_EXPRESS)) { |
1da177e4 LT |
14913 | /* DMA read watermark not used on PCIE */ |
14914 | tp->dma_rwctrl |= 0x00180000; | |
63c3a66f | 14915 | } else if (!tg3_flag(tp, PCIX_MODE)) { |
85e94ced MC |
14916 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
14917 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
1da177e4 LT |
14918 | tp->dma_rwctrl |= 0x003f0000; |
14919 | else | |
14920 | tp->dma_rwctrl |= 0x003f000f; | |
14921 | } else { | |
14922 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14923 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
14924 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
49afdeb6 | 14925 | u32 read_water = 0x7; |
1da177e4 | 14926 | |
4a29cc2e MC |
14927 | /* If the 5704 is behind the EPB bridge, we can |
14928 | * do the less restrictive ONE_DMA workaround for | |
14929 | * better performance. | |
14930 | */ | |
63c3a66f | 14931 | if (tg3_flag(tp, 40BIT_DMA_BUG) && |
4a29cc2e MC |
14932 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) |
14933 | tp->dma_rwctrl |= 0x8000; | |
14934 | else if (ccval == 0x6 || ccval == 0x7) | |
1da177e4 LT |
14935 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
14936 | ||
49afdeb6 MC |
14937 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) |
14938 | read_water = 4; | |
59e6b434 | 14939 | /* Set bit 23 to enable PCIX hw bug fix */ |
49afdeb6 MC |
14940 | tp->dma_rwctrl |= |
14941 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
14942 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
14943 | (1 << 23); | |
4cf78e4f MC |
14944 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { |
14945 | /* 5780 always in PCIX mode */ | |
14946 | tp->dma_rwctrl |= 0x00144000; | |
a4e2b347 MC |
14947 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
14948 | /* 5714 always in PCIX mode */ | |
14949 | tp->dma_rwctrl |= 0x00148000; | |
1da177e4 LT |
14950 | } else { |
14951 | tp->dma_rwctrl |= 0x001b000f; | |
14952 | } | |
14953 | } | |
14954 | ||
14955 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14956 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
14957 | tp->dma_rwctrl &= 0xfffffff0; | |
14958 | ||
14959 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14960 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
14961 | /* Remove this if it causes problems for some boards. */ | |
14962 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
14963 | ||
14964 | /* On 5700/5701 chips, we need to set this bit. | |
14965 | * Otherwise the chip will issue cacheline transactions | |
14966 | * to streamable DMA memory with not all the byte | |
14967 | * enables turned on. This is an error on several | |
14968 | * RISC PCI controllers, in particular sparc64. | |
14969 | * | |
14970 | * On 5703/5704 chips, this bit has been reassigned | |
14971 | * a different meaning. In particular, it is used | |
14972 | * on those chips to enable a PCI-X workaround. | |
14973 | */ | |
14974 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
14975 | } | |
14976 | ||
14977 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14978 | ||
14979 | #if 0 | |
14980 | /* Unneeded, already done by tg3_get_invariants. */ | |
14981 | tg3_switch_clocks(tp); | |
14982 | #endif | |
14983 | ||
1da177e4 LT |
14984 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
14985 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
14986 | goto out; | |
14987 | ||
59e6b434 DM |
14988 | /* It is best to perform DMA test with maximum write burst size |
14989 | * to expose the 5700/5701 write DMA bug. | |
14990 | */ | |
14991 | saved_dma_rwctrl = tp->dma_rwctrl; | |
14992 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
14993 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14994 | ||
1da177e4 LT |
14995 | while (1) { |
14996 | u32 *p = buf, i; | |
14997 | ||
14998 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
14999 | p[i] = i; | |
15000 | ||
15001 | /* Send the buffer to the chip. */ | |
15002 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
15003 | if (ret) { | |
2445e461 MC |
15004 | dev_err(&tp->pdev->dev, |
15005 | "%s: Buffer write failed. err = %d\n", | |
15006 | __func__, ret); | |
1da177e4 LT |
15007 | break; |
15008 | } | |
15009 | ||
15010 | #if 0 | |
15011 | /* validate data reached card RAM correctly. */ | |
15012 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
15013 | u32 val; | |
15014 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
15015 | if (le32_to_cpu(val) != p[i]) { | |
2445e461 MC |
15016 | dev_err(&tp->pdev->dev, |
15017 | "%s: Buffer corrupted on device! " | |
15018 | "(%d != %d)\n", __func__, val, i); | |
1da177e4 LT |
15019 | /* ret = -ENODEV here? */ |
15020 | } | |
15021 | p[i] = 0; | |
15022 | } | |
15023 | #endif | |
15024 | /* Now read it back. */ | |
15025 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
15026 | if (ret) { | |
5129c3a3 MC |
15027 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " |
15028 | "err = %d\n", __func__, ret); | |
1da177e4 LT |
15029 | break; |
15030 | } | |
15031 | ||
15032 | /* Verify it. */ | |
15033 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
15034 | if (p[i] == i) | |
15035 | continue; | |
15036 | ||
59e6b434 DM |
15037 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
15038 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
15039 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
1da177e4 LT |
15040 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
15041 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
15042 | break; | |
15043 | } else { | |
2445e461 MC |
15044 | dev_err(&tp->pdev->dev, |
15045 | "%s: Buffer corrupted on read back! " | |
15046 | "(%d != %d)\n", __func__, p[i], i); | |
1da177e4 LT |
15047 | ret = -ENODEV; |
15048 | goto out; | |
15049 | } | |
15050 | } | |
15051 | ||
15052 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
15053 | /* Success. */ | |
15054 | ret = 0; | |
15055 | break; | |
15056 | } | |
15057 | } | |
59e6b434 DM |
15058 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
15059 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
15060 | /* DMA test passed without adjusting DMA boundary, | |
6d1cfbab MC |
15061 | * now look for chipsets that are known to expose the |
15062 | * DMA bug without failing the test. | |
59e6b434 | 15063 | */ |
4143470c | 15064 | if (pci_dev_present(tg3_dma_wait_state_chipsets)) { |
6d1cfbab MC |
15065 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; |
15066 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
859a5887 | 15067 | } else { |
6d1cfbab MC |
15068 | /* Safe to use the calculated DMA boundary. */ |
15069 | tp->dma_rwctrl = saved_dma_rwctrl; | |
859a5887 | 15070 | } |
6d1cfbab | 15071 | |
59e6b434 DM |
15072 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
15073 | } | |
1da177e4 LT |
15074 | |
15075 | out: | |
4bae65c8 | 15076 | dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); |
1da177e4 LT |
15077 | out_nofree: |
15078 | return ret; | |
15079 | } | |
15080 | ||
1da177e4 LT |
15081 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) |
15082 | { | |
63c3a66f | 15083 | if (tg3_flag(tp, 57765_PLUS)) { |
666bc831 MC |
15084 | tp->bufmgr_config.mbuf_read_dma_low_water = |
15085 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
15086 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15087 | DEFAULT_MB_MACRX_LOW_WATER_57765; | |
15088 | tp->bufmgr_config.mbuf_high_water = | |
15089 | DEFAULT_MB_HIGH_WATER_57765; | |
15090 | ||
15091 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
15092 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
15093 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
15094 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; | |
15095 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
15096 | DEFAULT_MB_HIGH_WATER_JUMBO_57765; | |
63c3a66f | 15097 | } else if (tg3_flag(tp, 5705_PLUS)) { |
fdfec172 MC |
15098 | tp->bufmgr_config.mbuf_read_dma_low_water = |
15099 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
15100 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15101 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
15102 | tp->bufmgr_config.mbuf_high_water = | |
15103 | DEFAULT_MB_HIGH_WATER_5705; | |
b5d3772c MC |
15104 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
15105 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15106 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
15107 | tp->bufmgr_config.mbuf_high_water = | |
15108 | DEFAULT_MB_HIGH_WATER_5906; | |
15109 | } | |
fdfec172 MC |
15110 | |
15111 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
15112 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
15113 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
15114 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
15115 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
15116 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
15117 | } else { | |
15118 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
15119 | DEFAULT_MB_RDMA_LOW_WATER; | |
15120 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15121 | DEFAULT_MB_MACRX_LOW_WATER; | |
15122 | tp->bufmgr_config.mbuf_high_water = | |
15123 | DEFAULT_MB_HIGH_WATER; | |
15124 | ||
15125 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
15126 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
15127 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
15128 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
15129 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
15130 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
15131 | } | |
1da177e4 LT |
15132 | |
15133 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
15134 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
15135 | } | |
15136 | ||
15137 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
15138 | { | |
79eb6904 MC |
15139 | switch (tp->phy_id & TG3_PHY_ID_MASK) { |
15140 | case TG3_PHY_ID_BCM5400: return "5400"; | |
15141 | case TG3_PHY_ID_BCM5401: return "5401"; | |
15142 | case TG3_PHY_ID_BCM5411: return "5411"; | |
15143 | case TG3_PHY_ID_BCM5701: return "5701"; | |
15144 | case TG3_PHY_ID_BCM5703: return "5703"; | |
15145 | case TG3_PHY_ID_BCM5704: return "5704"; | |
15146 | case TG3_PHY_ID_BCM5705: return "5705"; | |
15147 | case TG3_PHY_ID_BCM5750: return "5750"; | |
15148 | case TG3_PHY_ID_BCM5752: return "5752"; | |
15149 | case TG3_PHY_ID_BCM5714: return "5714"; | |
15150 | case TG3_PHY_ID_BCM5780: return "5780"; | |
15151 | case TG3_PHY_ID_BCM5755: return "5755"; | |
15152 | case TG3_PHY_ID_BCM5787: return "5787"; | |
15153 | case TG3_PHY_ID_BCM5784: return "5784"; | |
15154 | case TG3_PHY_ID_BCM5756: return "5722/5756"; | |
15155 | case TG3_PHY_ID_BCM5906: return "5906"; | |
15156 | case TG3_PHY_ID_BCM5761: return "5761"; | |
15157 | case TG3_PHY_ID_BCM5718C: return "5718C"; | |
15158 | case TG3_PHY_ID_BCM5718S: return "5718S"; | |
15159 | case TG3_PHY_ID_BCM57765: return "57765"; | |
302b500b | 15160 | case TG3_PHY_ID_BCM5719C: return "5719C"; |
6418f2c1 | 15161 | case TG3_PHY_ID_BCM5720C: return "5720C"; |
79eb6904 | 15162 | case TG3_PHY_ID_BCM8002: return "8002/serdes"; |
1da177e4 LT |
15163 | case 0: return "serdes"; |
15164 | default: return "unknown"; | |
855e1111 | 15165 | } |
1da177e4 LT |
15166 | } |
15167 | ||
f9804ddb MC |
15168 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |
15169 | { | |
63c3a66f | 15170 | if (tg3_flag(tp, PCI_EXPRESS)) { |
f9804ddb MC |
15171 | strcpy(str, "PCI Express"); |
15172 | return str; | |
63c3a66f | 15173 | } else if (tg3_flag(tp, PCIX_MODE)) { |
f9804ddb MC |
15174 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; |
15175 | ||
15176 | strcpy(str, "PCIX:"); | |
15177 | ||
15178 | if ((clock_ctrl == 7) || | |
15179 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
15180 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
15181 | strcat(str, "133MHz"); | |
15182 | else if (clock_ctrl == 0) | |
15183 | strcat(str, "33MHz"); | |
15184 | else if (clock_ctrl == 2) | |
15185 | strcat(str, "50MHz"); | |
15186 | else if (clock_ctrl == 4) | |
15187 | strcat(str, "66MHz"); | |
15188 | else if (clock_ctrl == 6) | |
15189 | strcat(str, "100MHz"); | |
f9804ddb MC |
15190 | } else { |
15191 | strcpy(str, "PCI:"); | |
63c3a66f | 15192 | if (tg3_flag(tp, PCI_HIGH_SPEED)) |
f9804ddb MC |
15193 | strcat(str, "66MHz"); |
15194 | else | |
15195 | strcat(str, "33MHz"); | |
15196 | } | |
63c3a66f | 15197 | if (tg3_flag(tp, PCI_32BIT)) |
f9804ddb MC |
15198 | strcat(str, ":32-bit"); |
15199 | else | |
15200 | strcat(str, ":64-bit"); | |
15201 | return str; | |
15202 | } | |
15203 | ||
8c2dc7e1 | 15204 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) |
1da177e4 LT |
15205 | { |
15206 | struct pci_dev *peer; | |
15207 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
15208 | ||
15209 | for (func = 0; func < 8; func++) { | |
15210 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
15211 | if (peer && peer != tp->pdev) | |
15212 | break; | |
15213 | pci_dev_put(peer); | |
15214 | } | |
16fe9d74 MC |
15215 | /* 5704 can be configured in single-port mode, set peer to |
15216 | * tp->pdev in that case. | |
15217 | */ | |
15218 | if (!peer) { | |
15219 | peer = tp->pdev; | |
15220 | return peer; | |
15221 | } | |
1da177e4 LT |
15222 | |
15223 | /* | |
15224 | * We don't need to keep the refcount elevated; there's no way | |
15225 | * to remove one half of this device without removing the other | |
15226 | */ | |
15227 | pci_dev_put(peer); | |
15228 | ||
15229 | return peer; | |
15230 | } | |
15231 | ||
15f9850d DM |
15232 | static void __devinit tg3_init_coal(struct tg3 *tp) |
15233 | { | |
15234 | struct ethtool_coalesce *ec = &tp->coal; | |
15235 | ||
15236 | memset(ec, 0, sizeof(*ec)); | |
15237 | ec->cmd = ETHTOOL_GCOALESCE; | |
15238 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
15239 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
15240 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
15241 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
15242 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
15243 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
15244 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
15245 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
15246 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
15247 | ||
15248 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
15249 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
15250 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
15251 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
15252 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
15253 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
15254 | } | |
d244c892 | 15255 | |
63c3a66f | 15256 | if (tg3_flag(tp, 5705_PLUS)) { |
d244c892 MC |
15257 | ec->rx_coalesce_usecs_irq = 0; |
15258 | ec->tx_coalesce_usecs_irq = 0; | |
15259 | ec->stats_block_coalesce_usecs = 0; | |
15260 | } | |
15f9850d DM |
15261 | } |
15262 | ||
7c7d64b8 SH |
15263 | static const struct net_device_ops tg3_netdev_ops = { |
15264 | .ndo_open = tg3_open, | |
15265 | .ndo_stop = tg3_close, | |
00829823 | 15266 | .ndo_start_xmit = tg3_start_xmit, |
511d2224 | 15267 | .ndo_get_stats64 = tg3_get_stats64, |
00829823 | 15268 | .ndo_validate_addr = eth_validate_addr, |
afc4b13d | 15269 | .ndo_set_rx_mode = tg3_set_rx_mode, |
00829823 SH |
15270 | .ndo_set_mac_address = tg3_set_mac_addr, |
15271 | .ndo_do_ioctl = tg3_ioctl, | |
15272 | .ndo_tx_timeout = tg3_tx_timeout, | |
15273 | .ndo_change_mtu = tg3_change_mtu, | |
dc668910 | 15274 | .ndo_fix_features = tg3_fix_features, |
06c03c02 | 15275 | .ndo_set_features = tg3_set_features, |
00829823 SH |
15276 | #ifdef CONFIG_NET_POLL_CONTROLLER |
15277 | .ndo_poll_controller = tg3_poll_controller, | |
15278 | #endif | |
15279 | }; | |
15280 | ||
1da177e4 LT |
15281 | static int __devinit tg3_init_one(struct pci_dev *pdev, |
15282 | const struct pci_device_id *ent) | |
15283 | { | |
1da177e4 LT |
15284 | struct net_device *dev; |
15285 | struct tg3 *tp; | |
646c9edd MC |
15286 | int i, err, pm_cap; |
15287 | u32 sndmbx, rcvmbx, intmbx; | |
f9804ddb | 15288 | char str[40]; |
72f2afb8 | 15289 | u64 dma_mask, persist_dma_mask; |
c8f44aff | 15290 | netdev_features_t features = 0; |
1da177e4 | 15291 | |
05dbe005 | 15292 | printk_once(KERN_INFO "%s\n", version); |
1da177e4 LT |
15293 | |
15294 | err = pci_enable_device(pdev); | |
15295 | if (err) { | |
2445e461 | 15296 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
1da177e4 LT |
15297 | return err; |
15298 | } | |
15299 | ||
1da177e4 LT |
15300 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
15301 | if (err) { | |
2445e461 | 15302 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
1da177e4 LT |
15303 | goto err_out_disable_pdev; |
15304 | } | |
15305 | ||
15306 | pci_set_master(pdev); | |
15307 | ||
15308 | /* Find power-management capability. */ | |
15309 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
15310 | if (pm_cap == 0) { | |
2445e461 MC |
15311 | dev_err(&pdev->dev, |
15312 | "Cannot find Power Management capability, aborting\n"); | |
1da177e4 LT |
15313 | err = -EIO; |
15314 | goto err_out_free_res; | |
15315 | } | |
15316 | ||
16821285 MC |
15317 | err = pci_set_power_state(pdev, PCI_D0); |
15318 | if (err) { | |
15319 | dev_err(&pdev->dev, "Transition to D0 failed, aborting\n"); | |
15320 | goto err_out_free_res; | |
15321 | } | |
15322 | ||
fe5f5787 | 15323 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); |
1da177e4 | 15324 | if (!dev) { |
2445e461 | 15325 | dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n"); |
1da177e4 | 15326 | err = -ENOMEM; |
16821285 | 15327 | goto err_out_power_down; |
1da177e4 LT |
15328 | } |
15329 | ||
1da177e4 LT |
15330 | SET_NETDEV_DEV(dev, &pdev->dev); |
15331 | ||
1da177e4 LT |
15332 | tp = netdev_priv(dev); |
15333 | tp->pdev = pdev; | |
15334 | tp->dev = dev; | |
15335 | tp->pm_cap = pm_cap; | |
1da177e4 LT |
15336 | tp->rx_mode = TG3_DEF_RX_MODE; |
15337 | tp->tx_mode = TG3_DEF_TX_MODE; | |
8ef21428 | 15338 | |
1da177e4 LT |
15339 | if (tg3_debug > 0) |
15340 | tp->msg_enable = tg3_debug; | |
15341 | else | |
15342 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
15343 | ||
15344 | /* The word/byte swap controls here control register access byte | |
15345 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
15346 | * setting below. | |
15347 | */ | |
15348 | tp->misc_host_ctrl = | |
15349 | MISC_HOST_CTRL_MASK_PCI_INT | | |
15350 | MISC_HOST_CTRL_WORD_SWAP | | |
15351 | MISC_HOST_CTRL_INDIR_ACCESS | | |
15352 | MISC_HOST_CTRL_PCISTATE_RW; | |
15353 | ||
15354 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
15355 | * on descriptor entries, anything which isn't packet data. | |
15356 | * | |
15357 | * The StrongARM chips on the board (one for tx, one for rx) | |
15358 | * are running in big-endian mode. | |
15359 | */ | |
15360 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
15361 | GRC_MODE_WSWAP_NONFRM_DATA); | |
15362 | #ifdef __BIG_ENDIAN | |
15363 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
15364 | #endif | |
15365 | spin_lock_init(&tp->lock); | |
1da177e4 | 15366 | spin_lock_init(&tp->indirect_lock); |
c4028958 | 15367 | INIT_WORK(&tp->reset_task, tg3_reset_task); |
1da177e4 | 15368 | |
d5fe488a | 15369 | tp->regs = pci_ioremap_bar(pdev, BAR_0); |
ab0049b4 | 15370 | if (!tp->regs) { |
ab96b241 | 15371 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); |
1da177e4 LT |
15372 | err = -ENOMEM; |
15373 | goto err_out_free_dev; | |
15374 | } | |
15375 | ||
c9cab24e MC |
15376 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
15377 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || | |
15378 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || | |
15379 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || | |
15380 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || | |
15381 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
15382 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || | |
15383 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) { | |
15384 | tg3_flag_set(tp, ENABLE_APE); | |
15385 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); | |
15386 | if (!tp->aperegs) { | |
15387 | dev_err(&pdev->dev, | |
15388 | "Cannot map APE registers, aborting\n"); | |
15389 | err = -ENOMEM; | |
15390 | goto err_out_iounmap; | |
15391 | } | |
15392 | } | |
15393 | ||
1da177e4 LT |
15394 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; |
15395 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
1da177e4 | 15396 | |
1da177e4 | 15397 | dev->ethtool_ops = &tg3_ethtool_ops; |
1da177e4 | 15398 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
2ffcc981 | 15399 | dev->netdev_ops = &tg3_netdev_ops; |
1da177e4 | 15400 | dev->irq = pdev->irq; |
1da177e4 LT |
15401 | |
15402 | err = tg3_get_invariants(tp); | |
15403 | if (err) { | |
ab96b241 MC |
15404 | dev_err(&pdev->dev, |
15405 | "Problem fetching invariants of chip, aborting\n"); | |
c9cab24e | 15406 | goto err_out_apeunmap; |
1da177e4 LT |
15407 | } |
15408 | ||
4a29cc2e MC |
15409 | /* The EPB bridge inside 5714, 5715, and 5780 and any |
15410 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
72f2afb8 MC |
15411 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. |
15412 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
15413 | * do DMA address check in tg3_start_xmit(). | |
15414 | */ | |
63c3a66f | 15415 | if (tg3_flag(tp, IS_5788)) |
284901a9 | 15416 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); |
63c3a66f | 15417 | else if (tg3_flag(tp, 40BIT_DMA_BUG)) { |
50cf156a | 15418 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
72f2afb8 | 15419 | #ifdef CONFIG_HIGHMEM |
6a35528a | 15420 | dma_mask = DMA_BIT_MASK(64); |
72f2afb8 | 15421 | #endif |
4a29cc2e | 15422 | } else |
6a35528a | 15423 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
72f2afb8 MC |
15424 | |
15425 | /* Configure DMA attributes. */ | |
284901a9 | 15426 | if (dma_mask > DMA_BIT_MASK(32)) { |
72f2afb8 MC |
15427 | err = pci_set_dma_mask(pdev, dma_mask); |
15428 | if (!err) { | |
0da0606f | 15429 | features |= NETIF_F_HIGHDMA; |
72f2afb8 MC |
15430 | err = pci_set_consistent_dma_mask(pdev, |
15431 | persist_dma_mask); | |
15432 | if (err < 0) { | |
ab96b241 MC |
15433 | dev_err(&pdev->dev, "Unable to obtain 64 bit " |
15434 | "DMA for consistent allocations\n"); | |
c9cab24e | 15435 | goto err_out_apeunmap; |
72f2afb8 MC |
15436 | } |
15437 | } | |
15438 | } | |
284901a9 YH |
15439 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
15440 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
72f2afb8 | 15441 | if (err) { |
ab96b241 MC |
15442 | dev_err(&pdev->dev, |
15443 | "No usable DMA configuration, aborting\n"); | |
c9cab24e | 15444 | goto err_out_apeunmap; |
72f2afb8 MC |
15445 | } |
15446 | } | |
15447 | ||
fdfec172 | 15448 | tg3_init_bufmgr_config(tp); |
1da177e4 | 15449 | |
0da0606f MC |
15450 | features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
15451 | ||
15452 | /* 5700 B0 chips do not support checksumming correctly due | |
15453 | * to hardware bugs. | |
15454 | */ | |
15455 | if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) { | |
15456 | features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; | |
15457 | ||
15458 | if (tg3_flag(tp, 5755_PLUS)) | |
15459 | features |= NETIF_F_IPV6_CSUM; | |
15460 | } | |
15461 | ||
4e3a7aaa MC |
15462 | /* TSO is on by default on chips that support hardware TSO. |
15463 | * Firmware TSO on older chips gives lower performance, so it | |
15464 | * is off by default, but can be enabled using ethtool. | |
15465 | */ | |
63c3a66f JP |
15466 | if ((tg3_flag(tp, HW_TSO_1) || |
15467 | tg3_flag(tp, HW_TSO_2) || | |
15468 | tg3_flag(tp, HW_TSO_3)) && | |
0da0606f MC |
15469 | (features & NETIF_F_IP_CSUM)) |
15470 | features |= NETIF_F_TSO; | |
63c3a66f | 15471 | if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { |
0da0606f MC |
15472 | if (features & NETIF_F_IPV6_CSUM) |
15473 | features |= NETIF_F_TSO6; | |
63c3a66f | 15474 | if (tg3_flag(tp, HW_TSO_3) || |
e849cdc3 | 15475 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c MC |
15476 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
15477 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
63c3a66f | 15478 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
dc668910 | 15479 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
0da0606f | 15480 | features |= NETIF_F_TSO_ECN; |
b0026624 | 15481 | } |
1da177e4 | 15482 | |
d542fe27 MC |
15483 | dev->features |= features; |
15484 | dev->vlan_features |= features; | |
15485 | ||
06c03c02 MB |
15486 | /* |
15487 | * Add loopback capability only for a subset of devices that support | |
15488 | * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY | |
15489 | * loopback for the remaining devices. | |
15490 | */ | |
15491 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | |
15492 | !tg3_flag(tp, CPMU_PRESENT)) | |
15493 | /* Add the loopback capability */ | |
0da0606f MC |
15494 | features |= NETIF_F_LOOPBACK; |
15495 | ||
0da0606f | 15496 | dev->hw_features |= features; |
06c03c02 | 15497 | |
1da177e4 | 15498 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && |
63c3a66f | 15499 | !tg3_flag(tp, TSO_CAPABLE) && |
1da177e4 | 15500 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { |
63c3a66f | 15501 | tg3_flag_set(tp, MAX_RXPEND_64); |
1da177e4 LT |
15502 | tp->rx_pending = 63; |
15503 | } | |
15504 | ||
1da177e4 LT |
15505 | err = tg3_get_device_address(tp); |
15506 | if (err) { | |
ab96b241 MC |
15507 | dev_err(&pdev->dev, |
15508 | "Could not obtain valid ethernet address, aborting\n"); | |
c9cab24e | 15509 | goto err_out_apeunmap; |
c88864df MC |
15510 | } |
15511 | ||
1da177e4 LT |
15512 | /* |
15513 | * Reset chip in case UNDI or EFI driver did not shutdown | |
15514 | * DMA self test will enable WDMAC and we'll see (spurious) | |
15515 | * pending DMA on the PCI bus at that point. | |
15516 | */ | |
15517 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
15518 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
1da177e4 | 15519 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); |
944d980e | 15520 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
15521 | } |
15522 | ||
15523 | err = tg3_test_dma(tp); | |
15524 | if (err) { | |
ab96b241 | 15525 | dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); |
c88864df | 15526 | goto err_out_apeunmap; |
1da177e4 LT |
15527 | } |
15528 | ||
78f90dcf MC |
15529 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
15530 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | |
15531 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
6fd45cb8 | 15532 | for (i = 0; i < tp->irq_max; i++) { |
78f90dcf MC |
15533 | struct tg3_napi *tnapi = &tp->napi[i]; |
15534 | ||
15535 | tnapi->tp = tp; | |
15536 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; | |
15537 | ||
15538 | tnapi->int_mbox = intmbx; | |
93a700a9 | 15539 | if (i <= 4) |
78f90dcf MC |
15540 | intmbx += 0x8; |
15541 | else | |
15542 | intmbx += 0x4; | |
15543 | ||
15544 | tnapi->consmbox = rcvmbx; | |
15545 | tnapi->prodmbox = sndmbx; | |
15546 | ||
66cfd1bd | 15547 | if (i) |
78f90dcf | 15548 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); |
66cfd1bd | 15549 | else |
78f90dcf | 15550 | tnapi->coal_now = HOSTCC_MODE_NOW; |
78f90dcf | 15551 | |
63c3a66f | 15552 | if (!tg3_flag(tp, SUPPORT_MSIX)) |
78f90dcf MC |
15553 | break; |
15554 | ||
15555 | /* | |
15556 | * If we support MSIX, we'll be using RSS. If we're using | |
15557 | * RSS, the first vector only handles link interrupts and the | |
15558 | * remaining vectors handle rx and tx interrupts. Reuse the | |
15559 | * mailbox values for the next iteration. The values we setup | |
15560 | * above are still useful for the single vectored mode. | |
15561 | */ | |
15562 | if (!i) | |
15563 | continue; | |
15564 | ||
15565 | rcvmbx += 0x8; | |
15566 | ||
15567 | if (sndmbx & 0x4) | |
15568 | sndmbx -= 0x4; | |
15569 | else | |
15570 | sndmbx += 0xc; | |
15571 | } | |
15572 | ||
15f9850d DM |
15573 | tg3_init_coal(tp); |
15574 | ||
c49a1561 MC |
15575 | pci_set_drvdata(pdev, dev); |
15576 | ||
cd0d7228 MC |
15577 | if (tg3_flag(tp, 5717_PLUS)) { |
15578 | /* Resume a low-power mode */ | |
15579 | tg3_frob_aux_power(tp, false); | |
15580 | } | |
15581 | ||
1da177e4 LT |
15582 | err = register_netdev(dev); |
15583 | if (err) { | |
ab96b241 | 15584 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); |
0d3031d9 | 15585 | goto err_out_apeunmap; |
1da177e4 LT |
15586 | } |
15587 | ||
05dbe005 JP |
15588 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
15589 | tp->board_part_number, | |
15590 | tp->pci_chip_rev_id, | |
15591 | tg3_bus_string(tp, str), | |
15592 | dev->dev_addr); | |
1da177e4 | 15593 | |
f07e9af3 | 15594 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 MC |
15595 | struct phy_device *phydev; |
15596 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
5129c3a3 MC |
15597 | netdev_info(dev, |
15598 | "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
05dbe005 | 15599 | phydev->drv->name, dev_name(&phydev->dev)); |
f07e9af3 MC |
15600 | } else { |
15601 | char *ethtype; | |
15602 | ||
15603 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
15604 | ethtype = "10/100Base-TX"; | |
15605 | else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | |
15606 | ethtype = "1000Base-SX"; | |
15607 | else | |
15608 | ethtype = "10/100/1000Base-T"; | |
15609 | ||
5129c3a3 | 15610 | netdev_info(dev, "attached PHY is %s (%s Ethernet) " |
47007831 MC |
15611 | "(WireSpeed[%d], EEE[%d])\n", |
15612 | tg3_phy_string(tp), ethtype, | |
15613 | (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, | |
15614 | (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); | |
f07e9af3 | 15615 | } |
05dbe005 JP |
15616 | |
15617 | netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
dc668910 | 15618 | (dev->features & NETIF_F_RXCSUM) != 0, |
63c3a66f | 15619 | tg3_flag(tp, USE_LINKCHG_REG) != 0, |
f07e9af3 | 15620 | (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, |
63c3a66f JP |
15621 | tg3_flag(tp, ENABLE_ASF) != 0, |
15622 | tg3_flag(tp, TSO_CAPABLE) != 0); | |
05dbe005 JP |
15623 | netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", |
15624 | tp->dma_rwctrl, | |
15625 | pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : | |
15626 | ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); | |
1da177e4 | 15627 | |
b45aa2f6 MC |
15628 | pci_save_state(pdev); |
15629 | ||
1da177e4 LT |
15630 | return 0; |
15631 | ||
0d3031d9 MC |
15632 | err_out_apeunmap: |
15633 | if (tp->aperegs) { | |
15634 | iounmap(tp->aperegs); | |
15635 | tp->aperegs = NULL; | |
15636 | } | |
15637 | ||
1da177e4 | 15638 | err_out_iounmap: |
6892914f MC |
15639 | if (tp->regs) { |
15640 | iounmap(tp->regs); | |
22abe310 | 15641 | tp->regs = NULL; |
6892914f | 15642 | } |
1da177e4 LT |
15643 | |
15644 | err_out_free_dev: | |
15645 | free_netdev(dev); | |
15646 | ||
16821285 MC |
15647 | err_out_power_down: |
15648 | pci_set_power_state(pdev, PCI_D3hot); | |
15649 | ||
1da177e4 LT |
15650 | err_out_free_res: |
15651 | pci_release_regions(pdev); | |
15652 | ||
15653 | err_out_disable_pdev: | |
15654 | pci_disable_device(pdev); | |
15655 | pci_set_drvdata(pdev, NULL); | |
15656 | return err; | |
15657 | } | |
15658 | ||
15659 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
15660 | { | |
15661 | struct net_device *dev = pci_get_drvdata(pdev); | |
15662 | ||
15663 | if (dev) { | |
15664 | struct tg3 *tp = netdev_priv(dev); | |
15665 | ||
077f849d JSR |
15666 | if (tp->fw) |
15667 | release_firmware(tp->fw); | |
15668 | ||
db219973 | 15669 | tg3_reset_task_cancel(tp); |
158d7abd | 15670 | |
e730c823 | 15671 | if (tg3_flag(tp, USE_PHYLIB)) { |
b02fd9e3 | 15672 | tg3_phy_fini(tp); |
158d7abd | 15673 | tg3_mdio_fini(tp); |
b02fd9e3 | 15674 | } |
158d7abd | 15675 | |
1da177e4 | 15676 | unregister_netdev(dev); |
0d3031d9 MC |
15677 | if (tp->aperegs) { |
15678 | iounmap(tp->aperegs); | |
15679 | tp->aperegs = NULL; | |
15680 | } | |
6892914f MC |
15681 | if (tp->regs) { |
15682 | iounmap(tp->regs); | |
22abe310 | 15683 | tp->regs = NULL; |
6892914f | 15684 | } |
1da177e4 LT |
15685 | free_netdev(dev); |
15686 | pci_release_regions(pdev); | |
15687 | pci_disable_device(pdev); | |
15688 | pci_set_drvdata(pdev, NULL); | |
15689 | } | |
15690 | } | |
15691 | ||
aa6027ca | 15692 | #ifdef CONFIG_PM_SLEEP |
c866b7ea | 15693 | static int tg3_suspend(struct device *device) |
1da177e4 | 15694 | { |
c866b7ea | 15695 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15696 | struct net_device *dev = pci_get_drvdata(pdev); |
15697 | struct tg3 *tp = netdev_priv(dev); | |
15698 | int err; | |
15699 | ||
15700 | if (!netif_running(dev)) | |
15701 | return 0; | |
15702 | ||
db219973 | 15703 | tg3_reset_task_cancel(tp); |
b02fd9e3 | 15704 | tg3_phy_stop(tp); |
1da177e4 LT |
15705 | tg3_netif_stop(tp); |
15706 | ||
15707 | del_timer_sync(&tp->timer); | |
15708 | ||
f47c11ee | 15709 | tg3_full_lock(tp, 1); |
1da177e4 | 15710 | tg3_disable_ints(tp); |
f47c11ee | 15711 | tg3_full_unlock(tp); |
1da177e4 LT |
15712 | |
15713 | netif_device_detach(dev); | |
15714 | ||
f47c11ee | 15715 | tg3_full_lock(tp, 0); |
944d980e | 15716 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
63c3a66f | 15717 | tg3_flag_clear(tp, INIT_COMPLETE); |
f47c11ee | 15718 | tg3_full_unlock(tp); |
1da177e4 | 15719 | |
c866b7ea | 15720 | err = tg3_power_down_prepare(tp); |
1da177e4 | 15721 | if (err) { |
b02fd9e3 MC |
15722 | int err2; |
15723 | ||
f47c11ee | 15724 | tg3_full_lock(tp, 0); |
1da177e4 | 15725 | |
63c3a66f | 15726 | tg3_flag_set(tp, INIT_COMPLETE); |
b02fd9e3 MC |
15727 | err2 = tg3_restart_hw(tp, 1); |
15728 | if (err2) | |
b9ec6c1b | 15729 | goto out; |
1da177e4 LT |
15730 | |
15731 | tp->timer.expires = jiffies + tp->timer_offset; | |
15732 | add_timer(&tp->timer); | |
15733 | ||
15734 | netif_device_attach(dev); | |
15735 | tg3_netif_start(tp); | |
15736 | ||
b9ec6c1b | 15737 | out: |
f47c11ee | 15738 | tg3_full_unlock(tp); |
b02fd9e3 MC |
15739 | |
15740 | if (!err2) | |
15741 | tg3_phy_start(tp); | |
1da177e4 LT |
15742 | } |
15743 | ||
15744 | return err; | |
15745 | } | |
15746 | ||
c866b7ea | 15747 | static int tg3_resume(struct device *device) |
1da177e4 | 15748 | { |
c866b7ea | 15749 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15750 | struct net_device *dev = pci_get_drvdata(pdev); |
15751 | struct tg3 *tp = netdev_priv(dev); | |
15752 | int err; | |
15753 | ||
15754 | if (!netif_running(dev)) | |
15755 | return 0; | |
15756 | ||
1da177e4 LT |
15757 | netif_device_attach(dev); |
15758 | ||
f47c11ee | 15759 | tg3_full_lock(tp, 0); |
1da177e4 | 15760 | |
63c3a66f | 15761 | tg3_flag_set(tp, INIT_COMPLETE); |
b9ec6c1b MC |
15762 | err = tg3_restart_hw(tp, 1); |
15763 | if (err) | |
15764 | goto out; | |
1da177e4 LT |
15765 | |
15766 | tp->timer.expires = jiffies + tp->timer_offset; | |
15767 | add_timer(&tp->timer); | |
15768 | ||
1da177e4 LT |
15769 | tg3_netif_start(tp); |
15770 | ||
b9ec6c1b | 15771 | out: |
f47c11ee | 15772 | tg3_full_unlock(tp); |
1da177e4 | 15773 | |
b02fd9e3 MC |
15774 | if (!err) |
15775 | tg3_phy_start(tp); | |
15776 | ||
b9ec6c1b | 15777 | return err; |
1da177e4 LT |
15778 | } |
15779 | ||
c866b7ea | 15780 | static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); |
aa6027ca ED |
15781 | #define TG3_PM_OPS (&tg3_pm_ops) |
15782 | ||
15783 | #else | |
15784 | ||
15785 | #define TG3_PM_OPS NULL | |
15786 | ||
15787 | #endif /* CONFIG_PM_SLEEP */ | |
c866b7ea | 15788 | |
b45aa2f6 MC |
15789 | /** |
15790 | * tg3_io_error_detected - called when PCI error is detected | |
15791 | * @pdev: Pointer to PCI device | |
15792 | * @state: The current pci connection state | |
15793 | * | |
15794 | * This function is called after a PCI bus error affecting | |
15795 | * this device has been detected. | |
15796 | */ | |
15797 | static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev, | |
15798 | pci_channel_state_t state) | |
15799 | { | |
15800 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15801 | struct tg3 *tp = netdev_priv(netdev); | |
15802 | pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET; | |
15803 | ||
15804 | netdev_info(netdev, "PCI I/O error detected\n"); | |
15805 | ||
15806 | rtnl_lock(); | |
15807 | ||
15808 | if (!netif_running(netdev)) | |
15809 | goto done; | |
15810 | ||
15811 | tg3_phy_stop(tp); | |
15812 | ||
15813 | tg3_netif_stop(tp); | |
15814 | ||
15815 | del_timer_sync(&tp->timer); | |
b45aa2f6 MC |
15816 | |
15817 | /* Want to make sure that the reset task doesn't run */ | |
db219973 | 15818 | tg3_reset_task_cancel(tp); |
63c3a66f | 15819 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); |
b45aa2f6 MC |
15820 | |
15821 | netif_device_detach(netdev); | |
15822 | ||
15823 | /* Clean up software state, even if MMIO is blocked */ | |
15824 | tg3_full_lock(tp, 0); | |
15825 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | |
15826 | tg3_full_unlock(tp); | |
15827 | ||
15828 | done: | |
15829 | if (state == pci_channel_io_perm_failure) | |
15830 | err = PCI_ERS_RESULT_DISCONNECT; | |
15831 | else | |
15832 | pci_disable_device(pdev); | |
15833 | ||
15834 | rtnl_unlock(); | |
15835 | ||
15836 | return err; | |
15837 | } | |
15838 | ||
15839 | /** | |
15840 | * tg3_io_slot_reset - called after the pci bus has been reset. | |
15841 | * @pdev: Pointer to PCI device | |
15842 | * | |
15843 | * Restart the card from scratch, as if from a cold-boot. | |
15844 | * At this point, the card has exprienced a hard reset, | |
15845 | * followed by fixups by BIOS, and has its config space | |
15846 | * set up identically to what it was at cold boot. | |
15847 | */ | |
15848 | static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev) | |
15849 | { | |
15850 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15851 | struct tg3 *tp = netdev_priv(netdev); | |
15852 | pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT; | |
15853 | int err; | |
15854 | ||
15855 | rtnl_lock(); | |
15856 | ||
15857 | if (pci_enable_device(pdev)) { | |
15858 | netdev_err(netdev, "Cannot re-enable PCI device after reset.\n"); | |
15859 | goto done; | |
15860 | } | |
15861 | ||
15862 | pci_set_master(pdev); | |
15863 | pci_restore_state(pdev); | |
15864 | pci_save_state(pdev); | |
15865 | ||
15866 | if (!netif_running(netdev)) { | |
15867 | rc = PCI_ERS_RESULT_RECOVERED; | |
15868 | goto done; | |
15869 | } | |
15870 | ||
15871 | err = tg3_power_up(tp); | |
bed9829f | 15872 | if (err) |
b45aa2f6 | 15873 | goto done; |
b45aa2f6 MC |
15874 | |
15875 | rc = PCI_ERS_RESULT_RECOVERED; | |
15876 | ||
15877 | done: | |
15878 | rtnl_unlock(); | |
15879 | ||
15880 | return rc; | |
15881 | } | |
15882 | ||
15883 | /** | |
15884 | * tg3_io_resume - called when traffic can start flowing again. | |
15885 | * @pdev: Pointer to PCI device | |
15886 | * | |
15887 | * This callback is called when the error recovery driver tells | |
15888 | * us that its OK to resume normal operation. | |
15889 | */ | |
15890 | static void tg3_io_resume(struct pci_dev *pdev) | |
15891 | { | |
15892 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15893 | struct tg3 *tp = netdev_priv(netdev); | |
15894 | int err; | |
15895 | ||
15896 | rtnl_lock(); | |
15897 | ||
15898 | if (!netif_running(netdev)) | |
15899 | goto done; | |
15900 | ||
15901 | tg3_full_lock(tp, 0); | |
63c3a66f | 15902 | tg3_flag_set(tp, INIT_COMPLETE); |
b45aa2f6 MC |
15903 | err = tg3_restart_hw(tp, 1); |
15904 | tg3_full_unlock(tp); | |
15905 | if (err) { | |
15906 | netdev_err(netdev, "Cannot restart hardware after reset.\n"); | |
15907 | goto done; | |
15908 | } | |
15909 | ||
15910 | netif_device_attach(netdev); | |
15911 | ||
15912 | tp->timer.expires = jiffies + tp->timer_offset; | |
15913 | add_timer(&tp->timer); | |
15914 | ||
15915 | tg3_netif_start(tp); | |
15916 | ||
15917 | tg3_phy_start(tp); | |
15918 | ||
15919 | done: | |
15920 | rtnl_unlock(); | |
15921 | } | |
15922 | ||
15923 | static struct pci_error_handlers tg3_err_handler = { | |
15924 | .error_detected = tg3_io_error_detected, | |
15925 | .slot_reset = tg3_io_slot_reset, | |
15926 | .resume = tg3_io_resume | |
15927 | }; | |
15928 | ||
1da177e4 LT |
15929 | static struct pci_driver tg3_driver = { |
15930 | .name = DRV_MODULE_NAME, | |
15931 | .id_table = tg3_pci_tbl, | |
15932 | .probe = tg3_init_one, | |
15933 | .remove = __devexit_p(tg3_remove_one), | |
b45aa2f6 | 15934 | .err_handler = &tg3_err_handler, |
aa6027ca | 15935 | .driver.pm = TG3_PM_OPS, |
1da177e4 LT |
15936 | }; |
15937 | ||
15938 | static int __init tg3_init(void) | |
15939 | { | |
29917620 | 15940 | return pci_register_driver(&tg3_driver); |
1da177e4 LT |
15941 | } |
15942 | ||
15943 | static void __exit tg3_cleanup(void) | |
15944 | { | |
15945 | pci_unregister_driver(&tg3_driver); | |
15946 | } | |
15947 | ||
15948 | module_init(tg3_init); | |
15949 | module_exit(tg3_cleanup); |