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tg3: Add function tg3_phy_shdw_write()
[deliverable/linux.git] / drivers / net / ethernet / broadcom / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
b681b65d 7 * Copyright (C) 2005-2013 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
6867c843 21#include <linux/stringify.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
14c85021 27#include <linux/in.h>
1da177e4 28#include <linux/init.h>
a6b7a407 29#include <linux/interrupt.h>
1da177e4
LT		 30#include <linux/ioport.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/ethtool.h>
3110f5f5 36#include <linux/mdio.h>
1da177e4 37#include <linux/mii.h>
158d7abd 38#include <linux/phy.h>
a9daf367 39#include <linux/brcmphy.h>
1da177e4
LT		 40#include <linux/if_vlan.h>
41#include <linux/ip.h>
42#include <linux/tcp.h>
43#include <linux/workqueue.h>
61487480 44#include <linux/prefetch.h>
f9a5f7d3 45#include <linux/dma-mapping.h>
077f849d 46#include <linux/firmware.h>
7e6c63f0 47#include <linux/ssb/ssb_driver_gige.h>
aed93e0b
MC		 48#include <linux/hwmon.h>
49#include <linux/hwmon-sysfs.h>
1da177e4
LT		 50
51#include <net/checksum.h>
c9bdd4b5 52#include <net/ip.h>
1da177e4 53
27fd9de8 54#include <linux/io.h>
1da177e4 55#include <asm/byteorder.h>
27fd9de8 56#include <linux/uaccess.h>
1da177e4 57
be947307
MC		 58#include <uapi/linux/net_tstamp.h>
59#include <linux/ptp_clock_kernel.h>
60
49b6e95f 61#ifdef CONFIG_SPARC
1da177e4 62#include <asm/idprom.h>
49b6e95f 63#include <asm/prom.h>
1da177e4
LT		 64#endif
65
63532394
MC		 66#define BAR_0 0
67#define BAR_2 2
68
1da177e4
LT		 69#include "tg3.h"
70
63c3a66f
JP		 71/* Functions & macros to verify TG3_FLAGS types */
72
73static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
74{
75 return test_bit(flag, bits);
76}
77
78static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
79{
80 set_bit(flag, bits);
81}
82
83static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
84{
85 clear_bit(flag, bits);
86}
87
88#define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90#define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92#define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
94
1da177e4 95#define DRV_MODULE_NAME "tg3"
6867c843 96#define TG3_MAJ_NUM 3
cd77b2eb 97#define TG3_MIN_NUM 133
6867c843
MC		 98#define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
cd77b2eb 100#define DRV_MODULE_RELDATE "Jul 29, 2013"
1da177e4 101
fd6d3f0e
MC		 102#define RESET_KIND_SHUTDOWN 0
103#define RESET_KIND_INIT 1
104#define RESET_KIND_SUSPEND 2
105
1da177e4
LT		 106#define TG3_DEF_RX_MODE 0
107#define TG3_DEF_TX_MODE 0
108#define TG3_DEF_MSG_ENABLE \
109 (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK | \
112 NETIF_MSG_TIMER | \
113 NETIF_MSG_IFDOWN | \
114 NETIF_MSG_IFUP | \
115 NETIF_MSG_RX_ERR | \
116 NETIF_MSG_TX_ERR)
117
520b2756
MC		 118#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
119
1da177e4
LT		 120/* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
122 */
63c3a66f 123
1da177e4
LT		 124#define TG3_TX_TIMEOUT (5 * HZ)
125
126/* hardware minimum and maximum for a single frame's data payload */
127#define TG3_MIN_MTU 60
128#define TG3_MAX_MTU(tp) \
63c3a66f 129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 130
131/* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
134 */
7cb32cf2 135#define TG3_RX_STD_RING_SIZE(tp) \
63c3a66f 136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
1da177e4 138#define TG3_DEF_RX_RING_PENDING 200
7cb32cf2 139#define TG3_RX_JMB_RING_SIZE(tp) \
63c3a66f 140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
1da177e4
LT		 142#define TG3_DEF_RX_JUMBO_RING_PENDING 100
143
144/* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
149 */
1da177e4
LT		 150
151#define TG3_TX_RING_SIZE 512
152#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
153
2c49a44d
MC		 154#define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156#define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158#define TG3_RX_RCB_RING_BYTES(tp) \
7cb32cf2 159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
1da177e4
LT		 160#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
161 TG3_TX_RING_SIZE)
1da177e4
LT		 162#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
163
287be12e
MC		 164#define TG3_DMA_BYTE_ENAB 64
165
166#define TG3_RX_STD_DMA_SZ 1536
167#define TG3_RX_JMB_DMA_SZ 9046
168
169#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
170
171#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 173
2c49a44d
MC		 174#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
2b2cdb65 176
2c49a44d
MC		 177#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
2b2cdb65 179
d2757fc4
MC		 180/* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
184 *
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
190 */
191#define TG3_RX_COPY_THRESHOLD 256
192#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
194#else
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
196#endif
197
81389f57
MC		 198#if (NET_IP_ALIGN != 0)
199#define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
200#else
9205fd9c 201#define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
81389f57
MC		 202#endif
203
1da177e4 204/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 205#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
55086ad9 206#define TG3_TX_BD_DMA_MAX_2K 2048
a4cb428d 207#define TG3_TX_BD_DMA_MAX_4K 4096
1da177e4 208
ad829268
MC		 209#define TG3_RAW_IP_ALIGN 2
210
c6cdf436 211#define TG3_FW_UPDATE_TIMEOUT_SEC 5
21f7638e 212#define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
c6cdf436 213
077f849d 214#define FIRMWARE_TG3 "tigon/tg3.bin"
c4dab506 215#define FIRMWARE_TG357766 "tigon/tg357766.bin"
077f849d
JSR		 216#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
217#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
218
229b1ad1 219static char version[] =
05dbe005 220 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 221
222MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
223MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
224MODULE_LICENSE("GPL");
225MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 226MODULE_FIRMWARE(FIRMWARE_TG3);
227MODULE_FIRMWARE(FIRMWARE_TG3TSO);
228MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
229
1da177e4
LT		 230static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
231module_param(tg3_debug, int, 0);
232MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
233
3d567e0e
NNS		 234#define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
235#define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
236
a3aa1884 237static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
3d567e0e
NNS		 256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
257 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
258 TG3_DRV_DATA_FLAG_5705_10_100},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
3d567e0e
NNS		 263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
264 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
265 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
7e6c63f0 268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
13185217 269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
13185217 270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
3d567e0e
NNS		 271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
272 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
3d567e0e
NNS		 277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
278 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
3d567e0e
NNS		 286 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
287 PCI_VENDOR_ID_LENOVO,
288 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
289 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217 290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
3d567e0e
NNS		 291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
3d567e0e
NNS		 311 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
312 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
313 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321d32a0
MC		 317 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
318 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
3d567e0e
NNS		 319 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
320 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
5e7ccf20 321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6 322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
79d49695 323 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
5001e2f6 324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
b0f75221
MC		 325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
3d567e0e
NNS		 329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
330 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
332 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
302b500b 333 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
ba1f3c76 334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
02eca3f5 335 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
d3f677af 336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
c86a8560
MC		 337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
13185217
HK		 340 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
341 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
342 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
343 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
344 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
345 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
346 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
1dcb14d9 347 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
13185217 348 {}
1da177e4
LT		 349};
350
351MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
352
50da859d 353static const struct {
1da177e4 354 const char string[ETH_GSTRING_LEN];
48fa55a0 355} ethtool_stats_keys[] = {
1da177e4
LT		 356 { "rx_octets" },
357 { "rx_fragments" },
358 { "rx_ucast_packets" },
359 { "rx_mcast_packets" },
360 { "rx_bcast_packets" },
361 { "rx_fcs_errors" },
362 { "rx_align_errors" },
363 { "rx_xon_pause_rcvd" },
364 { "rx_xoff_pause_rcvd" },
365 { "rx_mac_ctrl_rcvd" },
366 { "rx_xoff_entered" },
367 { "rx_frame_too_long_errors" },
368 { "rx_jabbers" },
369 { "rx_undersize_packets" },
370 { "rx_in_length_errors" },
371 { "rx_out_length_errors" },
372 { "rx_64_or_less_octet_packets" },
373 { "rx_65_to_127_octet_packets" },
374 { "rx_128_to_255_octet_packets" },
375 { "rx_256_to_511_octet_packets" },
376 { "rx_512_to_1023_octet_packets" },
377 { "rx_1024_to_1522_octet_packets" },
378 { "rx_1523_to_2047_octet_packets" },
379 { "rx_2048_to_4095_octet_packets" },
380 { "rx_4096_to_8191_octet_packets" },
381 { "rx_8192_to_9022_octet_packets" },
382
383 { "tx_octets" },
384 { "tx_collisions" },
385
386 { "tx_xon_sent" },
387 { "tx_xoff_sent" },
388 { "tx_flow_control" },
389 { "tx_mac_errors" },
390 { "tx_single_collisions" },
391 { "tx_mult_collisions" },
392 { "tx_deferred" },
393 { "tx_excessive_collisions" },
394 { "tx_late_collisions" },
395 { "tx_collide_2times" },
396 { "tx_collide_3times" },
397 { "tx_collide_4times" },
398 { "tx_collide_5times" },
399 { "tx_collide_6times" },
400 { "tx_collide_7times" },
401 { "tx_collide_8times" },
402 { "tx_collide_9times" },
403 { "tx_collide_10times" },
404 { "tx_collide_11times" },
405 { "tx_collide_12times" },
406 { "tx_collide_13times" },
407 { "tx_collide_14times" },
408 { "tx_collide_15times" },
409 { "tx_ucast_packets" },
410 { "tx_mcast_packets" },
411 { "tx_bcast_packets" },
412 { "tx_carrier_sense_errors" },
413 { "tx_discards" },
414 { "tx_errors" },
415
416 { "dma_writeq_full" },
417 { "dma_write_prioq_full" },
418 { "rxbds_empty" },
419 { "rx_discards" },
420 { "rx_errors" },
421 { "rx_threshold_hit" },
422
423 { "dma_readq_full" },
424 { "dma_read_prioq_full" },
425 { "tx_comp_queue_full" },
426
427 { "ring_set_send_prod_index" },
428 { "ring_status_update" },
429 { "nic_irqs" },
430 { "nic_avoided_irqs" },
4452d099
MC		 431 { "nic_tx_threshold_hit" },
432
433 { "mbuf_lwm_thresh_hit" },
1da177e4
LT		 434};
435
48fa55a0 436#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
93df8b8f
NNS		 437#define TG3_NVRAM_TEST 0
438#define TG3_LINK_TEST 1
439#define TG3_REGISTER_TEST 2
440#define TG3_MEMORY_TEST 3
441#define TG3_MAC_LOOPB_TEST 4
442#define TG3_PHY_LOOPB_TEST 5
443#define TG3_EXT_LOOPB_TEST 6
444#define TG3_INTERRUPT_TEST 7
48fa55a0
MC		 445
446
50da859d 447static const struct {
4cafd3f5 448 const char string[ETH_GSTRING_LEN];
48fa55a0 449} ethtool_test_keys[] = {
93df8b8f
NNS		 450 [TG3_NVRAM_TEST] = { "nvram test (online) " },
451 [TG3_LINK_TEST] = { "link test (online) " },
452 [TG3_REGISTER_TEST] = { "register test (offline)" },
453 [TG3_MEMORY_TEST] = { "memory test (offline)" },
454 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
455 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
456 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
457 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
4cafd3f5
MC		 458};
459
48fa55a0
MC		 460#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
461
462
b401e9e2
MC		 463static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
464{
465 writel(val, tp->regs + off);
466}
467
468static u32 tg3_read32(struct tg3 *tp, u32 off)
469{
de6f31eb 470 return readl(tp->regs + off);
b401e9e2
MC		 471}
472
0d3031d9
MC		 473static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
474{
475 writel(val, tp->aperegs + off);
476}
477
478static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
479{
de6f31eb 480 return readl(tp->aperegs + off);
0d3031d9
MC		 481}
482
1da177e4
LT		 483static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
484{
6892914f
MC		 485 unsigned long flags;
486
487 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 488 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
489 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 490 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 491}
492
493static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
494{
495 writel(val, tp->regs + off);
496 readl(tp->regs + off);
1da177e4
LT		 497}
498
6892914f 499static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 500{
6892914f
MC		 501 unsigned long flags;
502 u32 val;
503
504 spin_lock_irqsave(&tp->indirect_lock, flags);
505 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
506 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
508 return val;
509}
510
511static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
512{
513 unsigned long flags;
514
515 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
516 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
517 TG3_64BIT_REG_LOW, val);
518 return;
519 }
66711e66 520 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 521 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
522 TG3_64BIT_REG_LOW, val);
523 return;
1da177e4 524 }
6892914f
MC		 525
526 spin_lock_irqsave(&tp->indirect_lock, flags);
527 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
528 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
529 spin_unlock_irqrestore(&tp->indirect_lock, flags);
530
531 /* In indirect mode when disabling interrupts, we also need
532 * to clear the interrupt bit in the GRC local ctrl register.
533 */
534 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
535 (val == 0x1)) {
536 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
537 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
538 }
539}
540
541static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
542{
543 unsigned long flags;
544 u32 val;
545
546 spin_lock_irqsave(&tp->indirect_lock, flags);
547 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
548 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
549 spin_unlock_irqrestore(&tp->indirect_lock, flags);
550 return val;
551}
552
b401e9e2
MC		 553/* usec_wait specifies the wait time in usec when writing to certain registers
554 * where it is unsafe to read back the register without some delay.
555 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
556 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
557 */
558static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 559{
63c3a66f 560 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
b401e9e2
MC		 561 /* Non-posted methods */
562 tp->write32(tp, off, val);
563 else {
564 /* Posted method */
565 tg3_write32(tp, off, val);
566 if (usec_wait)
567 udelay(usec_wait);
568 tp->read32(tp, off);
569 }
570 /* Wait again after the read for the posted method to guarantee that
571 * the wait time is met.
572 */
573 if (usec_wait)
574 udelay(usec_wait);
1da177e4
LT		 575}
576
09ee929c
MC		 577static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
578{
579 tp->write32_mbox(tp, off, val);
7e6c63f0
HM		 580 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
581 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
582 !tg3_flag(tp, ICH_WORKAROUND)))
6892914f 583 tp->read32_mbox(tp, off);
09ee929c
MC		 584}
585
20094930 586static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 587{
588 void __iomem *mbox = tp->regs + off;
589 writel(val, mbox);
63c3a66f 590 if (tg3_flag(tp, TXD_MBOX_HWBUG))
1da177e4 591 writel(val, mbox);
7e6c63f0
HM		 592 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
593 tg3_flag(tp, FLUSH_POSTED_WRITES))
1da177e4
LT		 594 readl(mbox);
595}
596
b5d3772c
MC		 597static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
598{
de6f31eb 599 return readl(tp->regs + off + GRCMBOX_BASE);
b5d3772c
MC		 600}
601
602static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
603{
604 writel(val, tp->regs + off + GRCMBOX_BASE);
605}
606
c6cdf436 607#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 608#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
c6cdf436
MC		 609#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
610#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
611#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930 612
c6cdf436
MC		 613#define tw32(reg, val) tp->write32(tp, reg, val)
614#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
615#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
616#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 617
618static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
619{
6892914f
MC		 620 unsigned long flags;
621
4153577a 622 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 623 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
624 return;
625
6892914f 626 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 627 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 628 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
629 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 630
bbadf503
MC		 631 /* Always leave this as zero. */
632 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
633 } else {
634 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
635 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 636
bbadf503
MC		 637 /* Always leave this as zero. */
638 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
639 }
640 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 641}
642
1da177e4
LT		 643static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
644{
6892914f
MC		 645 unsigned long flags;
646
4153577a 647 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 648 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
649 *val = 0;
650 return;
651 }
652
6892914f 653 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 654 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 655 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
656 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 657
bbadf503
MC		 658 /* Always leave this as zero. */
659 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
660 } else {
661 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
662 *val = tr32(TG3PCI_MEM_WIN_DATA);
663
664 /* Always leave this as zero. */
665 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
666 }
6892914f 667 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 668}
669
0d3031d9
MC		 670static void tg3_ape_lock_init(struct tg3 *tp)
671{
672 int i;
6f5c8f83 673 u32 regbase, bit;
f92d9dc1 674
4153577a 675 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 676 regbase = TG3_APE_LOCK_GRANT;
677 else
678 regbase = TG3_APE_PER_LOCK_GRANT;
0d3031d9
MC		 679
680 /* Make sure the driver hasn't any stale locks. */
78f94dc7
MC		 681 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
682 switch (i) {
683 case TG3_APE_LOCK_PHY0:
684 case TG3_APE_LOCK_PHY1:
685 case TG3_APE_LOCK_PHY2:
686 case TG3_APE_LOCK_PHY3:
687 bit = APE_LOCK_GRANT_DRIVER;
688 break;
689 default:
690 if (!tp->pci_fn)
691 bit = APE_LOCK_GRANT_DRIVER;
692 else
693 bit = 1 << tp->pci_fn;
694 }
695 tg3_ape_write32(tp, regbase + 4 * i, bit);
6f5c8f83
MC		 696 }
697
0d3031d9
MC		 698}
699
700static int tg3_ape_lock(struct tg3 *tp, int locknum)
701{
702 int i, off;
703 int ret = 0;
6f5c8f83 704 u32 status, req, gnt, bit;
0d3031d9 705
63c3a66f 706 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 707 return 0;
708
709 switch (locknum) {
6f5c8f83 710 case TG3_APE_LOCK_GPIO:
4153577a 711 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 712 return 0;
33f401ae
MC		 713 case TG3_APE_LOCK_GRC:
714 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 715 if (!tp->pci_fn)
716 bit = APE_LOCK_REQ_DRIVER;
717 else
718 bit = 1 << tp->pci_fn;
33f401ae 719 break;
8151ad57
MC		 720 case TG3_APE_LOCK_PHY0:
721 case TG3_APE_LOCK_PHY1:
722 case TG3_APE_LOCK_PHY2:
723 case TG3_APE_LOCK_PHY3:
724 bit = APE_LOCK_REQ_DRIVER;
725 break;
33f401ae
MC		 726 default:
727 return -EINVAL;
0d3031d9
MC		 728 }
729
4153577a 730 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
f92d9dc1
MC		 731 req = TG3_APE_LOCK_REQ;
732 gnt = TG3_APE_LOCK_GRANT;
733 } else {
734 req = TG3_APE_PER_LOCK_REQ;
735 gnt = TG3_APE_PER_LOCK_GRANT;
736 }
737
0d3031d9
MC		 738 off = 4 * locknum;
739
6f5c8f83 740 tg3_ape_write32(tp, req + off, bit);
0d3031d9
MC		 741
742 /* Wait for up to 1 millisecond to acquire lock. */
743 for (i = 0; i < 100; i++) {
f92d9dc1 744 status = tg3_ape_read32(tp, gnt + off);
6f5c8f83 745 if (status == bit)
0d3031d9 746 break;
6d446ec3
GS		 747 if (pci_channel_offline(tp->pdev))
748 break;
749
0d3031d9
MC		 750 udelay(10);
751 }
752
6f5c8f83 753 if (status != bit) {
0d3031d9 754 /* Revoke the lock request. */
6f5c8f83 755 tg3_ape_write32(tp, gnt + off, bit);
0d3031d9
MC		 756 ret = -EBUSY;
757 }
758
759 return ret;
760}
761
762static void tg3_ape_unlock(struct tg3 *tp, int locknum)
763{
6f5c8f83 764 u32 gnt, bit;
0d3031d9 765
63c3a66f 766 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 767 return;
768
769 switch (locknum) {
6f5c8f83 770 case TG3_APE_LOCK_GPIO:
4153577a 771 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 772 return;
33f401ae
MC		 773 case TG3_APE_LOCK_GRC:
774 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 775 if (!tp->pci_fn)
776 bit = APE_LOCK_GRANT_DRIVER;
777 else
778 bit = 1 << tp->pci_fn;
33f401ae 779 break;
8151ad57
MC		 780 case TG3_APE_LOCK_PHY0:
781 case TG3_APE_LOCK_PHY1:
782 case TG3_APE_LOCK_PHY2:
783 case TG3_APE_LOCK_PHY3:
784 bit = APE_LOCK_GRANT_DRIVER;
785 break;
33f401ae
MC		 786 default:
787 return;
0d3031d9
MC		 788 }
789
4153577a 790 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 791 gnt = TG3_APE_LOCK_GRANT;
792 else
793 gnt = TG3_APE_PER_LOCK_GRANT;
794
6f5c8f83 795 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
0d3031d9
MC		 796}
797
b65a372b 798static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
fd6d3f0e 799{
fd6d3f0e
MC		 800 u32 apedata;
801
b65a372b
MC		 802 while (timeout_us) {
803 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
804 return -EBUSY;
805
806 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
807 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
808 break;
809
810 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
811
812 udelay(10);
813 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
814 }
815
816 return timeout_us ? 0 : -EBUSY;
817}
818
cf8d55ae
MC		 819static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
820{
821 u32 i, apedata;
822
823 for (i = 0; i < timeout_us / 10; i++) {
824 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
825
826 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
827 break;
828
829 udelay(10);
830 }
831
832 return i == timeout_us / 10;
833}
834
86449944
MC		 835static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
836 u32 len)
cf8d55ae
MC		 837{
838 int err;
839 u32 i, bufoff, msgoff, maxlen, apedata;
840
841 if (!tg3_flag(tp, APE_HAS_NCSI))
842 return 0;
843
844 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
845 if (apedata != APE_SEG_SIG_MAGIC)
846 return -ENODEV;
847
848 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
849 if (!(apedata & APE_FW_STATUS_READY))
850 return -EAGAIN;
851
852 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
853 TG3_APE_SHMEM_BASE;
854 msgoff = bufoff + 2 * sizeof(u32);
855 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
856
857 while (len) {
858 u32 length;
859
860 /* Cap xfer sizes to scratchpad limits. */
861 length = (len > maxlen) ? maxlen : len;
862 len -= length;
863
864 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
865 if (!(apedata & APE_FW_STATUS_READY))
866 return -EAGAIN;
867
868 /* Wait for up to 1 msec for APE to service previous event. */
869 err = tg3_ape_event_lock(tp, 1000);
870 if (err)
871 return err;
872
873 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
874 APE_EVENT_STATUS_SCRTCHPD_READ |
875 APE_EVENT_STATUS_EVENT_PENDING;
876 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
877
878 tg3_ape_write32(tp, bufoff, base_off);
879 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
880
881 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
882 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
883
884 base_off += length;
885
886 if (tg3_ape_wait_for_event(tp, 30000))
887 return -EAGAIN;
888
889 for (i = 0; length; i += 4, length -= 4) {
890 u32 val = tg3_ape_read32(tp, msgoff + i);
891 memcpy(data, &val, sizeof(u32));
892 data++;
893 }
894 }
895
896 return 0;
897}
898
b65a372b
MC		 899static int tg3_ape_send_event(struct tg3 *tp, u32 event)
900{
901 int err;
902 u32 apedata;
fd6d3f0e
MC		 903
904 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
905 if (apedata != APE_SEG_SIG_MAGIC)
b65a372b 906 return -EAGAIN;
fd6d3f0e
MC		 907
908 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
909 if (!(apedata & APE_FW_STATUS_READY))
b65a372b 910 return -EAGAIN;
fd6d3f0e
MC		 911
912 /* Wait for up to 1 millisecond for APE to service previous event. */
b65a372b
MC		 913 err = tg3_ape_event_lock(tp, 1000);
914 if (err)
915 return err;
fd6d3f0e 916
b65a372b
MC		 917 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
918 event | APE_EVENT_STATUS_EVENT_PENDING);
fd6d3f0e 919
b65a372b
MC		 920 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
921 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
fd6d3f0e 922
b65a372b 923 return 0;
fd6d3f0e
MC		 924}
925
926static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
927{
928 u32 event;
929 u32 apedata;
930
931 if (!tg3_flag(tp, ENABLE_APE))
932 return;
933
934 switch (kind) {
935 case RESET_KIND_INIT:
936 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
937 APE_HOST_SEG_SIG_MAGIC);
938 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
939 APE_HOST_SEG_LEN_MAGIC);
940 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
941 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
942 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
943 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
944 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
945 APE_HOST_BEHAV_NO_PHYLOCK);
946 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
947 TG3_APE_HOST_DRVR_STATE_START);
948
949 event = APE_EVENT_STATUS_STATE_START;
950 break;
951 case RESET_KIND_SHUTDOWN:
952 /* With the interface we are currently using,
953 * APE does not track driver state. Wiping
954 * out the HOST SEGMENT SIGNATURE forces
955 * the APE to assume OS absent status.
956 */
957 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
958
959 if (device_may_wakeup(&tp->pdev->dev) &&
960 tg3_flag(tp, WOL_ENABLE)) {
961 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
962 TG3_APE_HOST_WOL_SPEED_AUTO);
963 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
964 } else
965 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
966
967 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
968
969 event = APE_EVENT_STATUS_STATE_UNLOAD;
970 break;
fd6d3f0e
MC		 971 default:
972 return;
973 }
974
975 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
976
977 tg3_ape_send_event(tp, event);
978}
979
1da177e4
LT		 980static void tg3_disable_ints(struct tg3 *tp)
981{
89aeb3bc
MC		 982 int i;
983
1da177e4
LT		 984 tw32(TG3PCI_MISC_HOST_CTRL,
985 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 986 for (i = 0; i < tp->irq_max; i++)
987 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 988}
989
1da177e4
LT		 990static void tg3_enable_ints(struct tg3 *tp)
991{
89aeb3bc 992 int i;
89aeb3bc 993
bbe832c0
MC		 994 tp->irq_sync = 0;
995 wmb();
996
1da177e4
LT		 997 tw32(TG3PCI_MISC_HOST_CTRL,
998 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 999
f89f38b8 1000 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 1001 for (i = 0; i < tp->irq_cnt; i++) {
1002 struct tg3_napi *tnapi = &tp->napi[i];
c6cdf436 1003
898a56f8 1004 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
63c3a66f 1005 if (tg3_flag(tp, 1SHOT_MSI))
89aeb3bc 1006 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 1007
f89f38b8 1008 tp->coal_now |= tnapi->coal_now;
89aeb3bc 1009 }
f19af9c2
MC		 1010
1011 /* Force an initial interrupt */
63c3a66f 1012 if (!tg3_flag(tp, TAGGED_STATUS) &&
f19af9c2
MC		 1013 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1014 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1015 else
f89f38b8
MC		 1016 tw32(HOSTCC_MODE, tp->coal_now);
1017
1018 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 1019}
1020
17375d25 1021static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 1022{
17375d25 1023 struct tg3 *tp = tnapi->tp;
898a56f8 1024 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 1025 unsigned int work_exists = 0;
1026
1027 /* check for phy events */
63c3a66f 1028 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
04237ddd
MC		 1029 if (sblk->status & SD_STATUS_LINK_CHG)
1030 work_exists = 1;
1031 }
f891ea16
MC		 1032
1033 /* check for TX work to do */
1034 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1035 work_exists = 1;
1036
1037 /* check for RX work to do */
1038 if (tnapi->rx_rcb_prod_idx &&
8d9d7cfc 1039 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 1040 work_exists = 1;
1041
1042 return work_exists;
1043}
1044
17375d25 1045/* tg3_int_reenable
04237ddd
MC		 1046 * similar to tg3_enable_ints, but it accurately determines whether there
1047 * is new work pending and can return without flushing the PIO write
6aa20a22 1048 * which reenables interrupts
1da177e4 1049 */
17375d25 1050static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 1051{
17375d25
MC		 1052 struct tg3 *tp = tnapi->tp;
1053
898a56f8 1054 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 1055 mmiowb();
1056
fac9b83e
DM		 1057 /* When doing tagged status, this work check is unnecessary.
1058 * The last_tag we write above tells the chip which piece of
1059 * work we've completed.
1060 */
63c3a66f 1061 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
04237ddd 1062 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 1063 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 1064}
1065
1da177e4
LT		 1066static void tg3_switch_clocks(struct tg3 *tp)
1067{
f6eb9b1f 1068 u32 clock_ctrl;
1da177e4
LT		 1069 u32 orig_clock_ctrl;
1070
63c3a66f 1071 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
4cf78e4f
MC		 1072 return;
1073
f6eb9b1f
MC		 1074 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1075
1da177e4
LT		 1076 orig_clock_ctrl = clock_ctrl;
1077 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1078 CLOCK_CTRL_CLKRUN_OENABLE |
1079 0x1f);
1080 tp->pci_clock_ctrl = clock_ctrl;
1081
63c3a66f 1082 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4 1083 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 1084 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1085 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 1086 }
1087 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 1088 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1089 clock_ctrl |
1090 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1091 40);
1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1094 40);
1da177e4 1095 }
b401e9e2 1096 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 1097}
1098
1099#define PHY_BUSY_LOOPS 5000
1100
5c358045
HM		 1101static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1102 u32 *val)
1da177e4
LT		 1103{
1104 u32 frame_val;
1105 unsigned int loops;
1106 int ret;
1107
1108 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1109 tw32_f(MAC_MI_MODE,
1110 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1111 udelay(80);
1112 }
1113
8151ad57
MC		 1114 tg3_ape_lock(tp, tp->phy_ape_lock);
1115
1da177e4
LT		 1116 *val = 0x0;
1117
5c358045 1118 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1119 MI_COM_PHY_ADDR_MASK);
1120 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1121 MI_COM_REG_ADDR_MASK);
1122 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 1123
1da177e4
LT		 1124 tw32_f(MAC_MI_COM, frame_val);
1125
1126 loops = PHY_BUSY_LOOPS;
1127 while (loops != 0) {
1128 udelay(10);
1129 frame_val = tr32(MAC_MI_COM);
1130
1131 if ((frame_val & MI_COM_BUSY) == 0) {
1132 udelay(5);
1133 frame_val = tr32(MAC_MI_COM);
1134 break;
1135 }
1136 loops -= 1;
1137 }
1138
1139 ret = -EBUSY;
1140 if (loops != 0) {
1141 *val = frame_val & MI_COM_DATA_MASK;
1142 ret = 0;
1143 }
1144
1145 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1146 tw32_f(MAC_MI_MODE, tp->mi_mode);
1147 udelay(80);
1148 }
1149
8151ad57
MC		 1150 tg3_ape_unlock(tp, tp->phy_ape_lock);
1151
1da177e4
LT		 1152 return ret;
1153}
1154
5c358045
HM		 1155static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1156{
1157 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1158}
1159
1160static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1161 u32 val)
1da177e4
LT		 1162{
1163 u32 frame_val;
1164 unsigned int loops;
1165 int ret;
1166
f07e9af3 1167 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
221c5637 1168 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
b5d3772c
MC		 1169 return 0;
1170
1da177e4
LT		 1171 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1172 tw32_f(MAC_MI_MODE,
1173 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1174 udelay(80);
1175 }
1176
8151ad57
MC		 1177 tg3_ape_lock(tp, tp->phy_ape_lock);
1178
5c358045 1179 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1180 MI_COM_PHY_ADDR_MASK);
1181 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1182 MI_COM_REG_ADDR_MASK);
1183 frame_val |= (val & MI_COM_DATA_MASK);
1184 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 1185
1da177e4
LT		 1186 tw32_f(MAC_MI_COM, frame_val);
1187
1188 loops = PHY_BUSY_LOOPS;
1189 while (loops != 0) {
1190 udelay(10);
1191 frame_val = tr32(MAC_MI_COM);
1192 if ((frame_val & MI_COM_BUSY) == 0) {
1193 udelay(5);
1194 frame_val = tr32(MAC_MI_COM);
1195 break;
1196 }
1197 loops -= 1;
1198 }
1199
1200 ret = -EBUSY;
1201 if (loops != 0)
1202 ret = 0;
1203
1204 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1205 tw32_f(MAC_MI_MODE, tp->mi_mode);
1206 udelay(80);
1207 }
1208
8151ad57
MC		 1209 tg3_ape_unlock(tp, tp->phy_ape_lock);
1210
1da177e4
LT		 1211 return ret;
1212}
1213
5c358045
HM		 1214static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1215{
1216 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1217}
1218
b0988c15
MC		 1219static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1220{
1221 int err;
1222
1223 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1224 if (err)
1225 goto done;
1226
1227 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1228 if (err)
1229 goto done;
1230
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1232 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1233 if (err)
1234 goto done;
1235
1236 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1237
1238done:
1239 return err;
1240}
1241
1242static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1243{
1244 int err;
1245
1246 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1247 if (err)
1248 goto done;
1249
1250 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1251 if (err)
1252 goto done;
1253
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1255 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1256 if (err)
1257 goto done;
1258
1259 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1260
1261done:
1262 return err;
1263}
1264
1265static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1266{
1267 int err;
1268
1269 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1270 if (!err)
1271 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1272
1273 return err;
1274}
1275
1276static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1277{
1278 int err;
1279
1280 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1281 if (!err)
1282 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1283
1284 return err;
1285}
1286
15ee95c3
MC		 1287static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1288{
1289 int err;
1290
1291 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1292 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1293 MII_TG3_AUXCTL_SHDWSEL_MISC);
1294 if (!err)
1295 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1296
1297 return err;
1298}
1299
b4bd2929
MC		 1300static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1301{
1302 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1303 set |= MII_TG3_AUXCTL_MISC_WREN;
1304
1305 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1306}
1307
daf3ec68
NNS		 1308static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1309{
1310 u32 val;
1311 int err;
1d36ba45 1312
daf3ec68 1313 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1d36ba45 1314
daf3ec68
NNS		 1315 if (err)
1316 return err;
daf3ec68 1317
7c10ee32 1318 if (enable)
daf3ec68
NNS		 1319 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1320 else
1321 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1322
1323 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1324 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1325
1326 return err;
1327}
1d36ba45 1328
3ab71071
NS		 1329static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1330{
1331 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1332 reg | val | MII_TG3_MISC_SHDW_WREN);
1333}
1334
95e2869a
MC		 1335static int tg3_bmcr_reset(struct tg3 *tp)
1336{
1337 u32 phy_control;
1338 int limit, err;
1339
1340 /* OK, reset it, and poll the BMCR_RESET bit until it
1341 * clears or we time out.
1342 */
1343 phy_control = BMCR_RESET;
1344 err = tg3_writephy(tp, MII_BMCR, phy_control);
1345 if (err != 0)
1346 return -EBUSY;
1347
1348 limit = 5000;
1349 while (limit--) {
1350 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1351 if (err != 0)
1352 return -EBUSY;
1353
1354 if ((phy_control & BMCR_RESET) == 0) {
1355 udelay(40);
1356 break;
1357 }
1358 udelay(10);
1359 }
d4675b52 1360 if (limit < 0)
95e2869a
MC		 1361 return -EBUSY;
1362
1363 return 0;
1364}
1365
158d7abd
MC		 1366static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1367{
3d16543d 1368 struct tg3 *tp = bp->priv;
158d7abd
MC		 1369 u32 val;
1370
24bb4fb6 1371 spin_lock_bh(&tp->lock);
158d7abd
MC		 1372
1373 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 1374 val = -EIO;
1375
1376 spin_unlock_bh(&tp->lock);
158d7abd
MC		 1377
1378 return val;
1379}
1380
1381static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1382{
3d16543d 1383 struct tg3 *tp = bp->priv;
24bb4fb6 1384 u32 ret = 0;
158d7abd 1385
24bb4fb6 1386 spin_lock_bh(&tp->lock);
158d7abd
MC		 1387
1388 if (tg3_writephy(tp, reg, val))
24bb4fb6 1389 ret = -EIO;
158d7abd 1390
24bb4fb6
MC		 1391 spin_unlock_bh(&tp->lock);
1392
1393 return ret;
158d7abd
MC		 1394}
1395
1396static int tg3_mdio_reset(struct mii_bus *bp)
1397{
1398 return 0;
1399}
1400
9c61d6bc 1401static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 1402{
1403 u32 val;
fcb389df 1404 struct phy_device *phydev;
a9daf367 1405
3f0e3ad7 1406 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df 1407 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 1408 case PHY_ID_BCM50610:
1409 case PHY_ID_BCM50610M:
fcb389df
MC		 1410 val = MAC_PHYCFG2_50610_LED_MODES;
1411 break;
6a443a0f 1412 case PHY_ID_BCMAC131:
fcb389df
MC		 1413 val = MAC_PHYCFG2_AC131_LED_MODES;
1414 break;
6a443a0f 1415 case PHY_ID_RTL8211C:
fcb389df
MC		 1416 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1417 break;
6a443a0f 1418 case PHY_ID_RTL8201E:
fcb389df
MC		 1419 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1420 break;
1421 default:
a9daf367 1422 return;
fcb389df
MC		 1423 }
1424
1425 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1426 tw32(MAC_PHYCFG2, val);
1427
1428 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 1429 val &= ~(MAC_PHYCFG1_RGMII_INT |
1430 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1431 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 1432 tw32(MAC_PHYCFG1, val);
1433
1434 return;
1435 }
1436
63c3a66f 1437 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
fcb389df
MC		 1438 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1439 MAC_PHYCFG2_FMODE_MASK_MASK |
1440 MAC_PHYCFG2_GMODE_MASK_MASK |
1441 MAC_PHYCFG2_ACT_MASK_MASK |
1442 MAC_PHYCFG2_QUAL_MASK_MASK |
1443 MAC_PHYCFG2_INBAND_ENABLE;
1444
1445 tw32(MAC_PHYCFG2, val);
a9daf367 1446
bb85fbb6
MC		 1447 val = tr32(MAC_PHYCFG1);
1448 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1449 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
63c3a66f
JP		 1450 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1451 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1452 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
63c3a66f 1453 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1454 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1455 }
bb85fbb6
MC		 1456 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1457 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1458 tw32(MAC_PHYCFG1, val);
a9daf367 1459
a9daf367
MC		 1460 val = tr32(MAC_EXT_RGMII_MODE);
1461 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1462 MAC_RGMII_MODE_RX_QUALITY |
1463 MAC_RGMII_MODE_RX_ACTIVITY |
1464 MAC_RGMII_MODE_RX_ENG_DET |
1465 MAC_RGMII_MODE_TX_ENABLE |
1466 MAC_RGMII_MODE_TX_LOWPWR |
1467 MAC_RGMII_MODE_TX_RESET);
63c3a66f
JP		 1468 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1469 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367
MC		 1470 val |= MAC_RGMII_MODE_RX_INT_B |
1471 MAC_RGMII_MODE_RX_QUALITY |
1472 MAC_RGMII_MODE_RX_ACTIVITY |
1473 MAC_RGMII_MODE_RX_ENG_DET;
63c3a66f 1474 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1475 val |= MAC_RGMII_MODE_TX_ENABLE |
1476 MAC_RGMII_MODE_TX_LOWPWR |
1477 MAC_RGMII_MODE_TX_RESET;
1478 }
1479 tw32(MAC_EXT_RGMII_MODE, val);
1480}
1481
158d7abd
MC		 1482static void tg3_mdio_start(struct tg3 *tp)
1483{
158d7abd
MC		 1484 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1485 tw32_f(MAC_MI_MODE, tp->mi_mode);
1486 udelay(80);
a9daf367 1487
63c3a66f 1488 if (tg3_flag(tp, MDIOBUS_INITED) &&
4153577a 1489 tg3_asic_rev(tp) == ASIC_REV_5785)
9ea4818d
MC		 1490 tg3_mdio_config_5785(tp);
1491}
1492
1493static int tg3_mdio_init(struct tg3 *tp)
1494{
1495 int i;
1496 u32 reg;
1497 struct phy_device *phydev;
1498
63c3a66f 1499 if (tg3_flag(tp, 5717_PLUS)) {
9c7df915 1500 u32 is_serdes;
882e9793 1501
69f11c99 1502 tp->phy_addr = tp->pci_fn + 1;
882e9793 1503
4153577a 1504 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
d1ec96af
MC		 1505 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1506 else
1507 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1508 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1509 if (is_serdes)
1510 tp->phy_addr += 7;
1511 } else
3f0e3ad7 1512 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1513
158d7abd
MC		 1514 tg3_mdio_start(tp);
1515
63c3a66f 1516 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
158d7abd
MC		 1517 return 0;
1518
298cf9be
LB		 1519 tp->mdio_bus = mdiobus_alloc();
1520 if (tp->mdio_bus == NULL)
1521 return -ENOMEM;
158d7abd 1522
298cf9be
LB		 1523 tp->mdio_bus->name = "tg3 mdio bus";
1524 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1525 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1526 tp->mdio_bus->priv = tp;
1527 tp->mdio_bus->parent = &tp->pdev->dev;
1528 tp->mdio_bus->read = &tg3_mdio_read;
1529 tp->mdio_bus->write = &tg3_mdio_write;
1530 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1531 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1532 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1533
1534 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1535 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1536
1537 /* The bus registration will look for all the PHYs on the mdio bus.
1538 * Unfortunately, it does not ensure the PHY is powered up before
1539 * accessing the PHY ID registers. A chip reset is the
1540 * quickest way to bring the device back to an operational state..
1541 */
1542 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1543 tg3_bmcr_reset(tp);
1544
298cf9be 1545 i = mdiobus_register(tp->mdio_bus);
a9daf367 1546 if (i) {
ab96b241 1547 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1548 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1549 return i;
1550 }
158d7abd 1551
3f0e3ad7 1552 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1553
9c61d6bc 1554 if (!phydev || !phydev->drv) {
ab96b241 1555 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1556 mdiobus_unregister(tp->mdio_bus);
1557 mdiobus_free(tp->mdio_bus);
1558 return -ENODEV;
1559 }
1560
1561 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1562 case PHY_ID_BCM57780:
321d32a0 1563 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1564 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1565 break;
6a443a0f
MC		 1566 case PHY_ID_BCM50610:
1567 case PHY_ID_BCM50610M:
32e5a8d6 1568 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1569 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1570 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1571 PHY_BRCM_AUTO_PWRDWN_ENABLE;
63c3a66f 1572 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
a9daf367 1573 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
63c3a66f 1574 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1575 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
63c3a66f 1576 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367 1577 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1578 /* fallthru */
6a443a0f 1579 case PHY_ID_RTL8211C:
fcb389df 1580 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1581 break;
6a443a0f
MC		 1582 case PHY_ID_RTL8201E:
1583 case PHY_ID_BCMAC131:
a9daf367 1584 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1585 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
f07e9af3 1586 tp->phy_flags |= TG3_PHYFLG_IS_FET;
a9daf367
MC		 1587 break;
1588 }
1589
63c3a66f 1590 tg3_flag_set(tp, MDIOBUS_INITED);
9c61d6bc 1591
4153577a 1592 if (tg3_asic_rev(tp) == ASIC_REV_5785)
9c61d6bc 1593 tg3_mdio_config_5785(tp);
a9daf367
MC		 1594
1595 return 0;
158d7abd
MC		 1596}
1597
1598static void tg3_mdio_fini(struct tg3 *tp)
1599{
63c3a66f
JP		 1600 if (tg3_flag(tp, MDIOBUS_INITED)) {
1601 tg3_flag_clear(tp, MDIOBUS_INITED);
298cf9be
LB		 1602 mdiobus_unregister(tp->mdio_bus);
1603 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1604 }
1605}
1606
4ba526ce
MC		 1607/* tp->lock is held. */
1608static inline void tg3_generate_fw_event(struct tg3 *tp)
1609{
1610 u32 val;
1611
1612 val = tr32(GRC_RX_CPU_EVENT);
1613 val |= GRC_RX_CPU_DRIVER_EVENT;
1614 tw32_f(GRC_RX_CPU_EVENT, val);
1615
1616 tp->last_event_jiffies = jiffies;
1617}
1618
1619#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1620
95e2869a
MC		 1621/* tp->lock is held. */
1622static void tg3_wait_for_event_ack(struct tg3 *tp)
1623{
1624 int i;
4ba526ce
MC		 1625 unsigned int delay_cnt;
1626 long time_remain;
1627
1628 /* If enough time has passed, no wait is necessary. */
1629 time_remain = (long)(tp->last_event_jiffies + 1 +
1630 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1631 (long)jiffies;
1632 if (time_remain < 0)
1633 return;
1634
1635 /* Check if we can shorten the wait time. */
1636 delay_cnt = jiffies_to_usecs(time_remain);
1637 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1638 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1639 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1640
4ba526ce 1641 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1642 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1643 break;
6d446ec3
GS		 1644 if (pci_channel_offline(tp->pdev))
1645 break;
1646
4ba526ce 1647 udelay(8);
95e2869a
MC		 1648 }
1649}
1650
1651/* tp->lock is held. */
b28f389d 1652static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
95e2869a 1653{
b28f389d 1654 u32 reg, val;
95e2869a
MC		 1655
1656 val = 0;
1657 if (!tg3_readphy(tp, MII_BMCR, &reg))
1658 val = reg << 16;
1659 if (!tg3_readphy(tp, MII_BMSR, &reg))
1660 val |= (reg & 0xffff);
b28f389d 1661 *data++ = val;
95e2869a
MC		 1662
1663 val = 0;
1664 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1665 val = reg << 16;
1666 if (!tg3_readphy(tp, MII_LPA, &reg))
1667 val |= (reg & 0xffff);
b28f389d 1668 *data++ = val;
95e2869a
MC		 1669
1670 val = 0;
f07e9af3 1671 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
95e2869a
MC		 1672 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1673 val = reg << 16;
1674 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1675 val |= (reg & 0xffff);
1676 }
b28f389d 1677 *data++ = val;
95e2869a
MC		 1678
1679 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1680 val = reg << 16;
1681 else
1682 val = 0;
b28f389d
MC		 1683 *data++ = val;
1684}
1685
1686/* tp->lock is held. */
1687static void tg3_ump_link_report(struct tg3 *tp)
1688{
1689 u32 data[4];
1690
1691 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1692 return;
1693
1694 tg3_phy_gather_ump_data(tp, data);
1695
1696 tg3_wait_for_event_ack(tp);
1697
1698 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1699 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1700 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1701 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1702 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1703 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
95e2869a 1704
4ba526ce 1705 tg3_generate_fw_event(tp);
95e2869a
MC		 1706}
1707
8d5a89b3
MC		 1708/* tp->lock is held. */
1709static void tg3_stop_fw(struct tg3 *tp)
1710{
1711 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1712 /* Wait for RX cpu to ACK the previous event. */
1713 tg3_wait_for_event_ack(tp);
1714
1715 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1716
1717 tg3_generate_fw_event(tp);
1718
1719 /* Wait for RX cpu to ACK this event. */
1720 tg3_wait_for_event_ack(tp);
1721 }
1722}
1723
fd6d3f0e
MC		 1724/* tp->lock is held. */
1725static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1726{
1727 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1728 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1729
1730 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1731 switch (kind) {
1732 case RESET_KIND_INIT:
1733 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1734 DRV_STATE_START);
1735 break;
1736
1737 case RESET_KIND_SHUTDOWN:
1738 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1739 DRV_STATE_UNLOAD);
1740 break;
1741
1742 case RESET_KIND_SUSPEND:
1743 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1744 DRV_STATE_SUSPEND);
1745 break;
1746
1747 default:
1748 break;
1749 }
1750 }
fd6d3f0e
MC		 1751}
1752
1753/* tp->lock is held. */
1754static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1755{
1756 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1757 switch (kind) {
1758 case RESET_KIND_INIT:
1759 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1760 DRV_STATE_START_DONE);
1761 break;
1762
1763 case RESET_KIND_SHUTDOWN:
1764 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1765 DRV_STATE_UNLOAD_DONE);
1766 break;
1767
1768 default:
1769 break;
1770 }
1771 }
fd6d3f0e
MC		 1772}
1773
1774/* tp->lock is held. */
1775static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1776{
1777 if (tg3_flag(tp, ENABLE_ASF)) {
1778 switch (kind) {
1779 case RESET_KIND_INIT:
1780 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1781 DRV_STATE_START);
1782 break;
1783
1784 case RESET_KIND_SHUTDOWN:
1785 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1786 DRV_STATE_UNLOAD);
1787 break;
1788
1789 case RESET_KIND_SUSPEND:
1790 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1791 DRV_STATE_SUSPEND);
1792 break;
1793
1794 default:
1795 break;
1796 }
1797 }
1798}
1799
1800static int tg3_poll_fw(struct tg3 *tp)
1801{
1802 int i;
1803 u32 val;
1804
df465abf
NS		 1805 if (tg3_flag(tp, NO_FWARE_REPORTED))
1806 return 0;
1807
7e6c63f0
HM		 1808 if (tg3_flag(tp, IS_SSB_CORE)) {
1809 /* We don't use firmware. */
1810 return 0;
1811 }
1812
4153577a 1813 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
fd6d3f0e
MC		 1814 /* Wait up to 20ms for init done. */
1815 for (i = 0; i < 200; i++) {
1816 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1817 return 0;
6d446ec3
GS		 1818 if (pci_channel_offline(tp->pdev))
1819 return -ENODEV;
1820
fd6d3f0e
MC		 1821 udelay(100);
1822 }
1823 return -ENODEV;
1824 }
1825
1826 /* Wait for firmware initialization to complete. */
1827 for (i = 0; i < 100000; i++) {
1828 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1829 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1830 break;
6d446ec3
GS		 1831 if (pci_channel_offline(tp->pdev)) {
1832 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1833 tg3_flag_set(tp, NO_FWARE_REPORTED);
1834 netdev_info(tp->dev, "No firmware running\n");
1835 }
1836
1837 break;
1838 }
1839
fd6d3f0e
MC		 1840 udelay(10);
1841 }
1842
1843 /* Chip might not be fitted with firmware. Some Sun onboard
1844 * parts are configured like that. So don't signal the timeout
1845 * of the above loop as an error, but do report the lack of
1846 * running firmware once.
1847 */
1848 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1849 tg3_flag_set(tp, NO_FWARE_REPORTED);
1850
1851 netdev_info(tp->dev, "No firmware running\n");
1852 }
1853
4153577a 1854 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
fd6d3f0e
MC		 1855 /* The 57765 A0 needs a little more
1856 * time to do some important work.
1857 */
1858 mdelay(10);
1859 }
1860
1861 return 0;
1862}
1863
95e2869a
MC		 1864static void tg3_link_report(struct tg3 *tp)
1865{
1866 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1867 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1868 tg3_ump_link_report(tp);
1869 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1870 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1871 (tp->link_config.active_speed == SPEED_1000 ?
1872 1000 :
1873 (tp->link_config.active_speed == SPEED_100 ?
1874 100 : 10)),
1875 (tp->link_config.active_duplex == DUPLEX_FULL ?
1876 "full" : "half"));
1877
1878 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1879 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1880 "on" : "off",
1881 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1882 "on" : "off");
47007831
MC		 1883
1884 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1885 netdev_info(tp->dev, "EEE is %s\n",
1886 tp->setlpicnt ? "enabled" : "disabled");
1887
95e2869a
MC		 1888 tg3_ump_link_report(tp);
1889 }
84421b99
NS		 1890
1891 tp->link_up = netif_carrier_ok(tp->dev);
95e2869a
MC		 1892}
1893
fdad8de4
NS		 1894static u32 tg3_decode_flowctrl_1000T(u32 adv)
1895{
1896 u32 flowctrl = 0;
1897
1898 if (adv & ADVERTISE_PAUSE_CAP) {
1899 flowctrl |= FLOW_CTRL_RX;
1900 if (!(adv & ADVERTISE_PAUSE_ASYM))
1901 flowctrl |= FLOW_CTRL_TX;
1902 } else if (adv & ADVERTISE_PAUSE_ASYM)
1903 flowctrl |= FLOW_CTRL_TX;
1904
1905 return flowctrl;
1906}
1907
95e2869a
MC		 1908static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1909{
1910 u16 miireg;
1911
e18ce346 1912 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1913 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1914 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1915 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1916 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1917 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1918 else
1919 miireg = 0;
1920
1921 return miireg;
1922}
1923
fdad8de4
NS		 1924static u32 tg3_decode_flowctrl_1000X(u32 adv)
1925{
1926 u32 flowctrl = 0;
1927
1928 if (adv & ADVERTISE_1000XPAUSE) {
1929 flowctrl |= FLOW_CTRL_RX;
1930 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1931 flowctrl |= FLOW_CTRL_TX;
1932 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1933 flowctrl |= FLOW_CTRL_TX;
1934
1935 return flowctrl;
1936}
1937
95e2869a
MC		 1938static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1939{
1940 u8 cap = 0;
1941
f3791cdf
MC		 1942 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1943 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1944 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1945 if (lcladv & ADVERTISE_1000XPAUSE)
1946 cap = FLOW_CTRL_RX;
1947 if (rmtadv & ADVERTISE_1000XPAUSE)
e18ce346 1948 cap = FLOW_CTRL_TX;
95e2869a
MC		 1949 }
1950
1951 return cap;
1952}
1953
f51f3562 1954static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1955{
b02fd9e3 1956 u8 autoneg;
f51f3562 1957 u8 flowctrl = 0;
95e2869a
MC		 1958 u32 old_rx_mode = tp->rx_mode;
1959 u32 old_tx_mode = tp->tx_mode;
1960
63c3a66f 1961 if (tg3_flag(tp, USE_PHYLIB))
3f0e3ad7 1962 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1963 else
1964 autoneg = tp->link_config.autoneg;
1965
63c3a66f 1966 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
f07e9af3 1967 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
f51f3562 1968 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1969 else
bc02ff95 1970 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1971 } else
1972 flowctrl = tp->link_config.flowctrl;
95e2869a 1973
f51f3562 1974 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1975
e18ce346 1976 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1977 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1978 else
1979 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1980
f51f3562 1981 if (old_rx_mode != tp->rx_mode)
95e2869a 1982 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1983
e18ce346 1984 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1985 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1986 else
1987 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1988
f51f3562 1989 if (old_tx_mode != tp->tx_mode)
95e2869a 1990 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1991}
1992
b02fd9e3
MC		 1993static void tg3_adjust_link(struct net_device *dev)
1994{
1995 u8 oldflowctrl, linkmesg = 0;
1996 u32 mac_mode, lcl_adv, rmt_adv;
1997 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1998 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1999
24bb4fb6 2000 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 2001
2002 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2003 MAC_MODE_HALF_DUPLEX);
2004
2005 oldflowctrl = tp->link_config.active_flowctrl;
2006
2007 if (phydev->link) {
2008 lcl_adv = 0;
2009 rmt_adv = 0;
2010
2011 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2012 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748 2013 else if (phydev->speed == SPEED_1000 ||
4153577a 2014 tg3_asic_rev(tp) != ASIC_REV_5785)
b02fd9e3 2015 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 2016 else
2017 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 2018
2019 if (phydev->duplex == DUPLEX_HALF)
2020 mac_mode |= MAC_MODE_HALF_DUPLEX;
2021 else {
f88788f0 2022 lcl_adv = mii_advertise_flowctrl(
b02fd9e3
MC		 2023 tp->link_config.flowctrl);
2024
2025 if (phydev->pause)
2026 rmt_adv = LPA_PAUSE_CAP;
2027 if (phydev->asym_pause)
2028 rmt_adv |= LPA_PAUSE_ASYM;
2029 }
2030
2031 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2032 } else
2033 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2034
2035 if (mac_mode != tp->mac_mode) {
2036 tp->mac_mode = mac_mode;
2037 tw32_f(MAC_MODE, tp->mac_mode);
2038 udelay(40);
2039 }
2040
4153577a 2041 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
fcb389df
MC		 2042 if (phydev->speed == SPEED_10)
2043 tw32(MAC_MI_STAT,
2044 MAC_MI_STAT_10MBPS_MODE |
2045 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2046 else
2047 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2048 }
2049
b02fd9e3
MC		 2050 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2051 tw32(MAC_TX_LENGTHS,
2052 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2053 (6 << TX_LENGTHS_IPG_SHIFT) |
2054 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2055 else
2056 tw32(MAC_TX_LENGTHS,
2057 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2058 (6 << TX_LENGTHS_IPG_SHIFT) |
2059 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2060
34655ad6 2061 if (phydev->link != tp->old_link ||
b02fd9e3
MC		 2062 phydev->speed != tp->link_config.active_speed ||
2063 phydev->duplex != tp->link_config.active_duplex ||
2064 oldflowctrl != tp->link_config.active_flowctrl)
c6cdf436 2065 linkmesg = 1;
b02fd9e3 2066
34655ad6 2067 tp->old_link = phydev->link;
b02fd9e3
MC		 2068 tp->link_config.active_speed = phydev->speed;
2069 tp->link_config.active_duplex = phydev->duplex;
2070
24bb4fb6 2071 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 2072
2073 if (linkmesg)
2074 tg3_link_report(tp);
2075}
2076
2077static int tg3_phy_init(struct tg3 *tp)
2078{
2079 struct phy_device *phydev;
2080
f07e9af3 2081 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
b02fd9e3
MC		 2082 return 0;
2083
2084 /* Bring the PHY back to a known state. */
2085 tg3_bmcr_reset(tp);
2086
3f0e3ad7 2087 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2088
2089 /* Attach the MAC to the PHY. */
f9a8f83b
FF		 2090 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2091 tg3_adjust_link, phydev->interface);
b02fd9e3 2092 if (IS_ERR(phydev)) {
ab96b241 2093 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 2094 return PTR_ERR(phydev);
2095 }
2096
b02fd9e3 2097 /* Mask with MAC supported features. */
9c61d6bc
MC		 2098 switch (phydev->interface) {
2099 case PHY_INTERFACE_MODE_GMII:
2100 case PHY_INTERFACE_MODE_RGMII:
f07e9af3 2101 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
321d32a0
MC		 2102 phydev->supported &= (PHY_GBIT_FEATURES |
2103 SUPPORTED_Pause |
2104 SUPPORTED_Asym_Pause);
2105 break;
2106 }
2107 /* fallthru */
9c61d6bc
MC		 2108 case PHY_INTERFACE_MODE_MII:
2109 phydev->supported &= (PHY_BASIC_FEATURES |
2110 SUPPORTED_Pause |
2111 SUPPORTED_Asym_Pause);
2112 break;
2113 default:
3f0e3ad7 2114 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 2115 return -EINVAL;
2116 }
2117
f07e9af3 2118 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2119
2120 phydev->advertising = phydev->supported;
2121
b02fd9e3
MC		 2122 return 0;
2123}
2124
2125static void tg3_phy_start(struct tg3 *tp)
2126{
2127 struct phy_device *phydev;
2128
f07e9af3 2129 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2130 return;
2131
3f0e3ad7 2132 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 2133
80096068
MC		 2134 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2135 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
c6700ce2
MC		 2136 phydev->speed = tp->link_config.speed;
2137 phydev->duplex = tp->link_config.duplex;
2138 phydev->autoneg = tp->link_config.autoneg;
2139 phydev->advertising = tp->link_config.advertising;
b02fd9e3
MC		 2140 }
2141
2142 phy_start(phydev);
2143
2144 phy_start_aneg(phydev);
2145}
2146
2147static void tg3_phy_stop(struct tg3 *tp)
2148{
f07e9af3 2149 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2150 return;
2151
3f0e3ad7 2152 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 2153}
2154
2155static void tg3_phy_fini(struct tg3 *tp)
2156{
f07e9af3 2157 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7 2158 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
f07e9af3 2159 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2160 }
2161}
2162
941ec90f
MC		 2163static int tg3_phy_set_extloopbk(struct tg3 *tp)
2164{
2165 int err;
2166 u32 val;
2167
2168 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2169 return 0;
2170
2171 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2172 /* Cannot do read-modify-write on 5401 */
2173 err = tg3_phy_auxctl_write(tp,
2174 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2175 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2176 0x4c20);
2177 goto done;
2178 }
2179
2180 err = tg3_phy_auxctl_read(tp,
2181 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2182 if (err)
2183 return err;
2184
2185 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2186 err = tg3_phy_auxctl_write(tp,
2187 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2188
2189done:
2190 return err;
2191}
2192
7f97a4bd
MC		 2193static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2194{
2195 u32 phytest;
2196
2197 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2198 u32 phy;
2199
2200 tg3_writephy(tp, MII_TG3_FET_TEST,
2201 phytest | MII_TG3_FET_SHADOW_EN);
2202 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2203 if (enable)
2204 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2205 else
2206 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2207 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2208 }
2209 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2210 }
2211}
2212
6833c043
MC		 2213static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2214{
2215 u32 reg;
2216
63c3a66f
JP		 2217 if (!tg3_flag(tp, 5705_PLUS) ||
2218 (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2219 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
6833c043
MC		 2220 return;
2221
f07e9af3 2222 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7f97a4bd
MC		 2223 tg3_phy_fet_toggle_apd(tp, enable);
2224 return;
2225 }
2226
3ab71071 2227 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
6833c043
MC		 2228 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2229 MII_TG3_MISC_SHDW_SCR5_SDTL |
2230 MII_TG3_MISC_SHDW_SCR5_C125OE;
4153577a 2231 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
6833c043
MC		 2232 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2233
3ab71071 2234 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
6833c043
MC		 2235
2236
3ab71071 2237 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
6833c043
MC		 2238 if (enable)
2239 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2240
3ab71071 2241 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
6833c043
MC		 2242}
2243
953c96e0 2244static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
9ef8ca99
MC		 2245{
2246 u32 phy;
2247
63c3a66f 2248 if (!tg3_flag(tp, 5705_PLUS) ||
f07e9af3 2249 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9ef8ca99
MC		 2250 return;
2251
f07e9af3 2252 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
9ef8ca99
MC		 2253 u32 ephy;
2254
535ef6e1
MC		 2255 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2256 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2257
2258 tg3_writephy(tp, MII_TG3_FET_TEST,
2259 ephy | MII_TG3_FET_SHADOW_EN);
2260 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 2261 if (enable)
535ef6e1 2262 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 2263 else
535ef6e1
MC		 2264 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2265 tg3_writephy(tp, reg, phy);
9ef8ca99 2266 }
535ef6e1 2267 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 2268 }
2269 } else {
15ee95c3
MC		 2270 int ret;
2271
2272 ret = tg3_phy_auxctl_read(tp,
2273 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2274 if (!ret) {
9ef8ca99
MC		 2275 if (enable)
2276 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2277 else
2278 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
b4bd2929
MC		 2279 tg3_phy_auxctl_write(tp,
2280 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
9ef8ca99
MC		 2281 }
2282 }
2283}
2284
1da177e4
LT		 2285static void tg3_phy_set_wirespeed(struct tg3 *tp)
2286{
15ee95c3 2287 int ret;
1da177e4
LT		 2288 u32 val;
2289
f07e9af3 2290 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1da177e4
LT		 2291 return;
2292
15ee95c3
MC		 2293 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2294 if (!ret)
b4bd2929
MC		 2295 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2296 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1da177e4
LT		 2297}
2298
b2a5c19c
MC		 2299static void tg3_phy_apply_otp(struct tg3 *tp)
2300{
2301 u32 otp, phy;
2302
2303 if (!tp->phy_otp)
2304 return;
2305
2306 otp = tp->phy_otp;
2307
daf3ec68 2308 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
1d36ba45 2309 return;
b2a5c19c
MC		 2310
2311 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2312 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2313 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2314
2315 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2316 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2317 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2318
2319 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2320 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2321 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2322
2323 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2324 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2325
2326 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2327 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2328
2329 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2330 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2331 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2332
daf3ec68 2333 tg3_phy_toggle_auxctl_smdsp(tp, false);
b2a5c19c
MC		 2334}
2335
400dfbaa
NS		 2336static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2337{
2338 u32 val;
2339 struct ethtool_eee *dest = &tp->eee;
2340
2341 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2342 return;
2343
2344 if (eee)
2345 dest = eee;
2346
2347 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2348 return;
2349
2350 /* Pull eee_active */
2351 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2352 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2353 dest->eee_active = 1;
2354 } else
2355 dest->eee_active = 0;
2356
2357 /* Pull lp advertised settings */
2358 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2359 return;
2360 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2361
2362 /* Pull advertised and eee_enabled settings */
2363 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2364 return;
2365 dest->eee_enabled = !!val;
2366 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2367
2368 /* Pull tx_lpi_enabled */
2369 val = tr32(TG3_CPMU_EEE_MODE);
2370 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2371
2372 /* Pull lpi timer value */
2373 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2374}
2375
953c96e0 2376static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
52b02d04
MC		 2377{
2378 u32 val;
2379
2380 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2381 return;
2382
2383 tp->setlpicnt = 0;
2384
2385 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
953c96e0 2386 current_link_up &&
a6b68dab
MC		 2387 tp->link_config.active_duplex == DUPLEX_FULL &&
2388 (tp->link_config.active_speed == SPEED_100 ||
2389 tp->link_config.active_speed == SPEED_1000)) {
52b02d04
MC		 2390 u32 eeectl;
2391
2392 if (tp->link_config.active_speed == SPEED_1000)
2393 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2394 else
2395 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2396
2397 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2398
400dfbaa
NS		 2399 tg3_eee_pull_config(tp, NULL);
2400 if (tp->eee.eee_active)
52b02d04
MC		 2401 tp->setlpicnt = 2;
2402 }
2403
2404 if (!tp->setlpicnt) {
953c96e0 2405 if (current_link_up &&
daf3ec68 2406 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94 2407 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
daf3ec68 2408 tg3_phy_toggle_auxctl_smdsp(tp, false);
b715ce94
MC		 2409 }
2410
52b02d04
MC		 2411 val = tr32(TG3_CPMU_EEE_MODE);
2412 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2413 }
2414}
2415
b0c5943f
MC		 2416static void tg3_phy_eee_enable(struct tg3 *tp)
2417{
2418 u32 val;
2419
2420 if (tp->link_config.active_speed == SPEED_1000 &&
4153577a
JP		 2421 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2422 tg3_asic_rev(tp) == ASIC_REV_5719 ||
55086ad9 2423 tg3_flag(tp, 57765_CLASS)) &&
daf3ec68 2424 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94
MC		 2425 val = MII_TG3_DSP_TAP26_ALNOKO |
2426 MII_TG3_DSP_TAP26_RMRXSTO;
2427 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
daf3ec68 2428 tg3_phy_toggle_auxctl_smdsp(tp, false);
b0c5943f
MC		 2429 }
2430
2431 val = tr32(TG3_CPMU_EEE_MODE);
2432 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2433}
2434
1da177e4
LT		 2435static int tg3_wait_macro_done(struct tg3 *tp)
2436{
2437 int limit = 100;
2438
2439 while (limit--) {
2440 u32 tmp32;
2441
f08aa1a8 2442 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1da177e4
LT		 2443 if ((tmp32 & 0x1000) == 0)
2444 break;
2445 }
2446 }
d4675b52 2447 if (limit < 0)
1da177e4
LT		 2448 return -EBUSY;
2449
2450 return 0;
2451}
2452
2453static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2454{
2455 static const u32 test_pat[4][6] = {
2456 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2457 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2458 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2459 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2460 };
2461 int chan;
2462
2463 for (chan = 0; chan < 4; chan++) {
2464 int i;
2465
2466 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2467 (chan * 0x2000) | 0x0200);
f08aa1a8 2468 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2469
2470 for (i = 0; i < 6; i++)
2471 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2472 test_pat[chan][i]);
2473
f08aa1a8 2474 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2475 if (tg3_wait_macro_done(tp)) {
2476 *resetp = 1;
2477 return -EBUSY;
2478 }
2479
2480 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2481 (chan * 0x2000) | 0x0200);
f08aa1a8 2482 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1da177e4
LT		 2483 if (tg3_wait_macro_done(tp)) {
2484 *resetp = 1;
2485 return -EBUSY;
2486 }
2487
f08aa1a8 2488 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1da177e4
LT		 2489 if (tg3_wait_macro_done(tp)) {
2490 *resetp = 1;
2491 return -EBUSY;
2492 }
2493
2494 for (i = 0; i < 6; i += 2) {
2495 u32 low, high;
2496
2497 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2498 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2499 tg3_wait_macro_done(tp)) {
2500 *resetp = 1;
2501 return -EBUSY;
2502 }
2503 low &= 0x7fff;
2504 high &= 0x000f;
2505 if (low != test_pat[chan][i] ||
2506 high != test_pat[chan][i+1]) {
2507 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2508 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2509 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2510
2511 return -EBUSY;
2512 }
2513 }
2514 }
2515
2516 return 0;
2517}
2518
2519static int tg3_phy_reset_chanpat(struct tg3 *tp)
2520{
2521 int chan;
2522
2523 for (chan = 0; chan < 4; chan++) {
2524 int i;
2525
2526 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2527 (chan * 0x2000) | 0x0200);
f08aa1a8 2528 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2529 for (i = 0; i < 6; i++)
2530 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
f08aa1a8 2531 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2532 if (tg3_wait_macro_done(tp))
2533 return -EBUSY;
2534 }
2535
2536 return 0;
2537}
2538
2539static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2540{
2541 u32 reg32, phy9_orig;
2542 int retries, do_phy_reset, err;
2543
2544 retries = 10;
2545 do_phy_reset = 1;
2546 do {
2547 if (do_phy_reset) {
2548 err = tg3_bmcr_reset(tp);
2549 if (err)
2550 return err;
2551 do_phy_reset = 0;
2552 }
2553
2554 /* Disable transmitter and interrupt. */
2555 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2556 continue;
2557
2558 reg32 |= 0x3000;
2559 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2560
2561 /* Set full-duplex, 1000 mbps. */
2562 tg3_writephy(tp, MII_BMCR,
221c5637 2563 BMCR_FULLDPLX | BMCR_SPEED1000);
1da177e4
LT		 2564
2565 /* Set to master mode. */
221c5637 2566 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
1da177e4
LT		 2567 continue;
2568
221c5637
MC		 2569 tg3_writephy(tp, MII_CTRL1000,
2570 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
1da177e4 2571
daf3ec68 2572 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
1d36ba45
MC		 2573 if (err)
2574 return err;
1da177e4
LT		 2575
2576 /* Block the PHY control access. */
6ee7c0a0 2577 tg3_phydsp_write(tp, 0x8005, 0x0800);
1da177e4
LT		 2578
2579 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2580 if (!err)
2581 break;
2582 } while (--retries);
2583
2584 err = tg3_phy_reset_chanpat(tp);
2585 if (err)
2586 return err;
2587
6ee7c0a0 2588 tg3_phydsp_write(tp, 0x8005, 0x0000);
1da177e4
LT		 2589
2590 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
f08aa1a8 2591 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1da177e4 2592
daf3ec68 2593 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2594
221c5637 2595 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
1da177e4
LT		 2596
2597 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2598 reg32 &= ~0x3000;
2599 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2600 } else if (!err)
2601 err = -EBUSY;
2602
2603 return err;
2604}
2605
f4a46d1f
NNS		 2606static void tg3_carrier_off(struct tg3 *tp)
2607{
2608 netif_carrier_off(tp->dev);
2609 tp->link_up = false;
2610}
2611
ce20f161
NS		 2612static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2613{
2614 if (tg3_flag(tp, ENABLE_ASF))
2615 netdev_warn(tp->dev,
2616 "Management side-band traffic will be interrupted during phy settings change\n");
2617}
2618
1da177e4
LT		 2619/* This will reset the tigon3 PHY if there is no valid
2620 * link unless the FORCE argument is non-zero.
2621 */
2622static int tg3_phy_reset(struct tg3 *tp)
2623{
f833c4c1 2624 u32 val, cpmuctrl;
1da177e4
LT		 2625 int err;
2626
4153577a 2627 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 2628 val = tr32(GRC_MISC_CFG);
2629 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2630 udelay(40);
2631 }
f833c4c1
MC		 2632 err = tg3_readphy(tp, MII_BMSR, &val);
2633 err |= tg3_readphy(tp, MII_BMSR, &val);
1da177e4
LT		 2634 if (err != 0)
2635 return -EBUSY;
2636
f4a46d1f 2637 if (netif_running(tp->dev) && tp->link_up) {
84421b99 2638 netif_carrier_off(tp->dev);
c8e1e82b
MC		 2639 tg3_link_report(tp);
2640 }
2641
4153577a
JP		 2642 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2643 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2644 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 2645 err = tg3_phy_reset_5703_4_5(tp);
2646 if (err)
2647 return err;
2648 goto out;
2649 }
2650
b2a5c19c 2651 cpmuctrl = 0;
4153577a
JP		 2652 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2653 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 2654 cpmuctrl = tr32(TG3_CPMU_CTRL);
2655 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2656 tw32(TG3_CPMU_CTRL,
2657 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2658 }
2659
1da177e4
LT		 2660 err = tg3_bmcr_reset(tp);
2661 if (err)
2662 return err;
2663
b2a5c19c 2664 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
f833c4c1
MC		 2665 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2666 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
b2a5c19c
MC		 2667
2668 tw32(TG3_CPMU_CTRL, cpmuctrl);
2669 }
2670
4153577a
JP		 2671 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2672 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 2673 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2674 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2675 CPMU_LSPD_1000MB_MACCLK_12_5) {
2676 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2677 udelay(40);
2678 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2679 }
2680 }
2681
63c3a66f 2682 if (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2683 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
ecf1410b
MC		 2684 return 0;
2685
b2a5c19c
MC		 2686 tg3_phy_apply_otp(tp);
2687
f07e9af3 2688 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
6833c043
MC		 2689 tg3_phy_toggle_apd(tp, true);
2690 else
2691 tg3_phy_toggle_apd(tp, false);
2692
1da177e4 2693out:
1d36ba45 2694 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
daf3ec68 2695 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
6ee7c0a0
MC		 2696 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2697 tg3_phydsp_write(tp, 0x000a, 0x0323);
daf3ec68 2698 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2699 }
1d36ba45 2700
f07e9af3 2701 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
f08aa1a8
MC		 2702 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2703 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1da177e4 2704 }
1d36ba45 2705
f07e9af3 2706 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
daf3ec68 2707 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2708 tg3_phydsp_write(tp, 0x000a, 0x310b);
2709 tg3_phydsp_write(tp, 0x201f, 0x9506);
2710 tg3_phydsp_write(tp, 0x401f, 0x14e2);
daf3ec68 2711 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2712 }
f07e9af3 2713 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
daf3ec68 2714 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2715 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2716 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2717 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2718 tg3_writephy(tp, MII_TG3_TEST1,
2719 MII_TG3_TEST1_TRIM_EN | 0x4);
2720 } else
2721 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2722
daf3ec68 2723 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2724 }
c424cb24 2725 }
1d36ba45 2726
1da177e4
LT		 2727 /* Set Extended packet length bit (bit 14) on all chips that */
2728 /* support jumbo frames */
79eb6904 2729 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4 2730 /* Cannot do read-modify-write on 5401 */
b4bd2929 2731 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
63c3a66f 2732 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
1da177e4 2733 /* Set bit 14 with read-modify-write to preserve other bits */
15ee95c3
MC		 2734 err = tg3_phy_auxctl_read(tp,
2735 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2736 if (!err)
b4bd2929
MC		 2737 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2738 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
1da177e4
LT		 2739 }
2740
2741 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2742 * jumbo frames transmission.
2743 */
63c3a66f 2744 if (tg3_flag(tp, JUMBO_CAPABLE)) {
f833c4c1 2745 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
c6cdf436 2746 tg3_writephy(tp, MII_TG3_EXT_CTRL,
f833c4c1 2747 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1da177e4
LT		 2748 }
2749
4153577a 2750 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
715116a1 2751 /* adjust output voltage */
535ef6e1 2752 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2753 }
2754
4153577a 2755 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
c65a17f4
MC		 2756 tg3_phydsp_write(tp, 0xffb, 0x4000);
2757
953c96e0 2758 tg3_phy_toggle_automdix(tp, true);
1da177e4
LT		 2759 tg3_phy_set_wirespeed(tp);
2760 return 0;
2761}
2762
3a1e19d3
MC		 2763#define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2764#define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2765#define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2766 TG3_GPIO_MSG_NEED_VAUX)
2767#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2768 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2769 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2770 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2771 (TG3_GPIO_MSG_DRVR_PRES << 12))
2772
2773#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2774 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2775 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2776 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2777 (TG3_GPIO_MSG_NEED_VAUX << 12))
2778
2779static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2780{
2781 u32 status, shift;
2782
4153577a
JP		 2783 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2784 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2785 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2786 else
2787 status = tr32(TG3_CPMU_DRV_STATUS);
2788
2789 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2790 status &= ~(TG3_GPIO_MSG_MASK << shift);
2791 status |= (newstat << shift);
2792
4153577a
JP		 2793 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2794 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2795 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2796 else
2797 tw32(TG3_CPMU_DRV_STATUS, status);
2798
2799 return status >> TG3_APE_GPIO_MSG_SHIFT;
2800}
2801
520b2756
MC		 2802static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2803{
2804 if (!tg3_flag(tp, IS_NIC))
2805 return 0;
2806
4153577a
JP		 2807 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2808 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2809 tg3_asic_rev(tp) == ASIC_REV_5720) {
3a1e19d3
MC		 2810 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2811 return -EIO;
520b2756 2812
3a1e19d3
MC		 2813 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2814
2815 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2816 TG3_GRC_LCLCTL_PWRSW_DELAY);
2817
2818 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2819 } else {
2820 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2821 TG3_GRC_LCLCTL_PWRSW_DELAY);
2822 }
6f5c8f83 2823
520b2756
MC		 2824 return 0;
2825}
2826
2827static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2828{
2829 u32 grc_local_ctrl;
2830
2831 if (!tg3_flag(tp, IS_NIC) ||
4153577a
JP		 2832 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2833 tg3_asic_rev(tp) == ASIC_REV_5701)
520b2756
MC		 2834 return;
2835
2836 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2837
2838 tw32_wait_f(GRC_LOCAL_CTRL,
2839 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2840 TG3_GRC_LCLCTL_PWRSW_DELAY);
2841
2842 tw32_wait_f(GRC_LOCAL_CTRL,
2843 grc_local_ctrl,
2844 TG3_GRC_LCLCTL_PWRSW_DELAY);
2845
2846 tw32_wait_f(GRC_LOCAL_CTRL,
2847 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2848 TG3_GRC_LCLCTL_PWRSW_DELAY);
2849}
2850
2851static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2852{
2853 if (!tg3_flag(tp, IS_NIC))
2854 return;
2855
4153577a
JP		 2856 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2857 tg3_asic_rev(tp) == ASIC_REV_5701) {
520b2756
MC		 2858 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2859 (GRC_LCLCTRL_GPIO_OE0 |
2860 GRC_LCLCTRL_GPIO_OE1 |
2861 GRC_LCLCTRL_GPIO_OE2 |
2862 GRC_LCLCTRL_GPIO_OUTPUT0 |
2863 GRC_LCLCTRL_GPIO_OUTPUT1),
2864 TG3_GRC_LCLCTL_PWRSW_DELAY);
2865 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2866 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2867 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2868 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2869 GRC_LCLCTRL_GPIO_OE1 |
2870 GRC_LCLCTRL_GPIO_OE2 |
2871 GRC_LCLCTRL_GPIO_OUTPUT0 |
2872 GRC_LCLCTRL_GPIO_OUTPUT1 |
2873 tp->grc_local_ctrl;
2874 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2875 TG3_GRC_LCLCTL_PWRSW_DELAY);
2876
2877 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2878 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2879 TG3_GRC_LCLCTL_PWRSW_DELAY);
2880
2881 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2882 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2883 TG3_GRC_LCLCTL_PWRSW_DELAY);
2884 } else {
2885 u32 no_gpio2;
2886 u32 grc_local_ctrl = 0;
2887
2888 /* Workaround to prevent overdrawing Amps. */
4153577a 2889 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
520b2756
MC		 2890 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2891 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2892 grc_local_ctrl,
2893 TG3_GRC_LCLCTL_PWRSW_DELAY);
2894 }
2895
2896 /* On 5753 and variants, GPIO2 cannot be used. */
2897 no_gpio2 = tp->nic_sram_data_cfg &
2898 NIC_SRAM_DATA_CFG_NO_GPIO2;
2899
2900 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2901 GRC_LCLCTRL_GPIO_OE1 |
2902 GRC_LCLCTRL_GPIO_OE2 |
2903 GRC_LCLCTRL_GPIO_OUTPUT1 |
2904 GRC_LCLCTRL_GPIO_OUTPUT2;
2905 if (no_gpio2) {
2906 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2907 GRC_LCLCTRL_GPIO_OUTPUT2);
2908 }
2909 tw32_wait_f(GRC_LOCAL_CTRL,
2910 tp->grc_local_ctrl | grc_local_ctrl,
2911 TG3_GRC_LCLCTL_PWRSW_DELAY);
2912
2913 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2914
2915 tw32_wait_f(GRC_LOCAL_CTRL,
2916 tp->grc_local_ctrl | grc_local_ctrl,
2917 TG3_GRC_LCLCTL_PWRSW_DELAY);
2918
2919 if (!no_gpio2) {
2920 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2921 tw32_wait_f(GRC_LOCAL_CTRL,
2922 tp->grc_local_ctrl | grc_local_ctrl,
2923 TG3_GRC_LCLCTL_PWRSW_DELAY);
2924 }
2925 }
3a1e19d3
MC		 2926}
2927
cd0d7228 2928static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
3a1e19d3
MC		 2929{
2930 u32 msg = 0;
2931
2932 /* Serialize power state transitions */
2933 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2934 return;
2935
cd0d7228 2936 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
3a1e19d3
MC		 2937 msg = TG3_GPIO_MSG_NEED_VAUX;
2938
2939 msg = tg3_set_function_status(tp, msg);
2940
2941 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2942 goto done;
6f5c8f83 2943
3a1e19d3
MC		 2944 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2945 tg3_pwrsrc_switch_to_vaux(tp);
2946 else
2947 tg3_pwrsrc_die_with_vmain(tp);
2948
2949done:
6f5c8f83 2950 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
520b2756
MC		 2951}
2952
cd0d7228 2953static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
1da177e4 2954{
683644b7 2955 bool need_vaux = false;
1da177e4 2956
334355aa 2957 /* The GPIOs do something completely different on 57765. */
55086ad9 2958 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
1da177e4
LT		 2959 return;
2960
4153577a
JP		 2961 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2962 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2963 tg3_asic_rev(tp) == ASIC_REV_5720) {
cd0d7228
MC		 2964 tg3_frob_aux_power_5717(tp, include_wol ?
2965 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
3a1e19d3
MC		 2966 return;
2967 }
2968
2969 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
8c2dc7e1
MC		 2970 struct net_device *dev_peer;
2971
2972 dev_peer = pci_get_drvdata(tp->pdev_peer);
683644b7 2973
bc1c7567 2974 /* remove_one() may have been run on the peer. */
683644b7
MC		 2975 if (dev_peer) {
2976 struct tg3 *tp_peer = netdev_priv(dev_peer);
2977
63c3a66f 2978 if (tg3_flag(tp_peer, INIT_COMPLETE))
683644b7
MC		 2979 return;
2980
cd0d7228 2981 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
63c3a66f 2982 tg3_flag(tp_peer, ENABLE_ASF))
683644b7
MC		 2983 need_vaux = true;
2984 }
1da177e4
LT		 2985 }
2986
cd0d7228
MC		 2987 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2988 tg3_flag(tp, ENABLE_ASF))
683644b7
MC		 2989 need_vaux = true;
2990
520b2756
MC		 2991 if (need_vaux)
2992 tg3_pwrsrc_switch_to_vaux(tp);
2993 else
2994 tg3_pwrsrc_die_with_vmain(tp);
1da177e4
LT		 2995}
2996
e8f3f6ca
MC		 2997static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2998{
2999 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3000 return 1;
79eb6904 3001 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 3002 if (speed != SPEED_10)
3003 return 1;
3004 } else if (speed == SPEED_10)
3005 return 1;
3006
3007 return 0;
3008}
3009
44f3b503
NS		 3010static bool tg3_phy_power_bug(struct tg3 *tp)
3011{
3012 switch (tg3_asic_rev(tp)) {
3013 case ASIC_REV_5700:
3014 case ASIC_REV_5704:
3015 return true;
3016 case ASIC_REV_5780:
3017 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3018 return true;
3019 return false;
3020 case ASIC_REV_5717:
3021 if (!tp->pci_fn)
3022 return true;
3023 return false;
3024 case ASIC_REV_5719:
3025 case ASIC_REV_5720:
3026 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3027 !tp->pci_fn)
3028 return true;
3029 return false;
3030 }
3031
3032 return false;
3033}
3034
989038e2
NS		 3035static bool tg3_phy_led_bug(struct tg3 *tp)
3036{
3037 switch (tg3_asic_rev(tp)) {
3038 case ASIC_REV_5719:
300cf9b9 3039 case ASIC_REV_5720:
989038e2
NS		 3040 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3041 !tp->pci_fn)
3042 return true;
3043 return false;
3044 }
3045
3046 return false;
3047}
3048
0a459aac 3049static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 3050{
ce057f01
MC		 3051 u32 val;
3052
942d1af0
NS		 3053 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3054 return;
3055
f07e9af3 3056 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a 3057 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
5129724a
MC		 3058 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3059 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3060
3061 sg_dig_ctrl |=
3062 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3063 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3064 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3065 }
3f7045c1 3066 return;
5129724a 3067 }
3f7045c1 3068
4153577a 3069 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 3070 tg3_bmcr_reset(tp);
3071 val = tr32(GRC_MISC_CFG);
3072 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3073 udelay(40);
3074 return;
f07e9af3 3075 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
0e5f784c
MC		 3076 u32 phytest;
3077 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3078 u32 phy;
3079
3080 tg3_writephy(tp, MII_ADVERTISE, 0);
3081 tg3_writephy(tp, MII_BMCR,
3082 BMCR_ANENABLE | BMCR_ANRESTART);
3083
3084 tg3_writephy(tp, MII_TG3_FET_TEST,
3085 phytest | MII_TG3_FET_SHADOW_EN);
3086 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3087 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3088 tg3_writephy(tp,
3089 MII_TG3_FET_SHDW_AUXMODE4,
3090 phy);
3091 }
3092 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3093 }
3094 return;
0a459aac 3095 } else if (do_low_power) {
989038e2
NS		 3096 if (!tg3_phy_led_bug(tp))
3097 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3098 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac 3099
b4bd2929
MC		 3100 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3101 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3102 MII_TG3_AUXCTL_PCTL_VREG_11V;
3103 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
715116a1 3104 }
3f7045c1 3105
15c3b696
MC		 3106 /* The PHY should not be powered down on some chips because
3107 * of bugs.
3108 */
44f3b503 3109 if (tg3_phy_power_bug(tp))
15c3b696 3110 return;
ce057f01 3111
4153577a
JP		 3112 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3113 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 3114 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3115 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3116 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3117 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3118 }
3119
15c3b696
MC		 3120 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3121}
3122
ffbcfed4
MC		 3123/* tp->lock is held. */
3124static int tg3_nvram_lock(struct tg3 *tp)
3125{
63c3a66f 3126 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3127 int i;
3128
3129 if (tp->nvram_lock_cnt == 0) {
3130 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3131 for (i = 0; i < 8000; i++) {
3132 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3133 break;
3134 udelay(20);
3135 }
3136 if (i == 8000) {
3137 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3138 return -ENODEV;
3139 }
3140 }
3141 tp->nvram_lock_cnt++;
3142 }
3143 return 0;
3144}
3145
3146/* tp->lock is held. */
3147static void tg3_nvram_unlock(struct tg3 *tp)
3148{
63c3a66f 3149 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3150 if (tp->nvram_lock_cnt > 0)
3151 tp->nvram_lock_cnt--;
3152 if (tp->nvram_lock_cnt == 0)
3153 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3154 }
3155}
3156
3157/* tp->lock is held. */
3158static void tg3_enable_nvram_access(struct tg3 *tp)
3159{
63c3a66f 3160 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3161 u32 nvaccess = tr32(NVRAM_ACCESS);
3162
3163 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3164 }
3165}
3166
3167/* tp->lock is held. */
3168static void tg3_disable_nvram_access(struct tg3 *tp)
3169{
63c3a66f 3170 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3171 u32 nvaccess = tr32(NVRAM_ACCESS);
3172
3173 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3174 }
3175}
3176
3177static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3178 u32 offset, u32 *val)
3179{
3180 u32 tmp;
3181 int i;
3182
3183 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3184 return -EINVAL;
3185
3186 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3187 EEPROM_ADDR_DEVID_MASK |
3188 EEPROM_ADDR_READ);
3189 tw32(GRC_EEPROM_ADDR,
3190 tmp |
3191 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3192 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3193 EEPROM_ADDR_ADDR_MASK) |
3194 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3195
3196 for (i = 0; i < 1000; i++) {
3197 tmp = tr32(GRC_EEPROM_ADDR);
3198
3199 if (tmp & EEPROM_ADDR_COMPLETE)
3200 break;
3201 msleep(1);
3202 }
3203 if (!(tmp & EEPROM_ADDR_COMPLETE))
3204 return -EBUSY;
3205
62cedd11
MC		 3206 tmp = tr32(GRC_EEPROM_DATA);
3207
3208 /*
3209 * The data will always be opposite the native endian
3210 * format. Perform a blind byteswap to compensate.
3211 */
3212 *val = swab32(tmp);
3213
ffbcfed4
MC		 3214 return 0;
3215}
3216
3217#define NVRAM_CMD_TIMEOUT 10000
3218
3219static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3220{
3221 int i;
3222
3223 tw32(NVRAM_CMD, nvram_cmd);
3224 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3225 udelay(10);
3226 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3227 udelay(10);
3228 break;
3229 }
3230 }
3231
3232 if (i == NVRAM_CMD_TIMEOUT)
3233 return -EBUSY;
3234
3235 return 0;
3236}
3237
3238static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3239{
63c3a66f
JP		 3240 if (tg3_flag(tp, NVRAM) &&
3241 tg3_flag(tp, NVRAM_BUFFERED) &&
3242 tg3_flag(tp, FLASH) &&
3243 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3244 (tp->nvram_jedecnum == JEDEC_ATMEL))
3245
3246 addr = ((addr / tp->nvram_pagesize) <<
3247 ATMEL_AT45DB0X1B_PAGE_POS) +
3248 (addr % tp->nvram_pagesize);
3249
3250 return addr;
3251}
3252
3253static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3254{
63c3a66f
JP		 3255 if (tg3_flag(tp, NVRAM) &&
3256 tg3_flag(tp, NVRAM_BUFFERED) &&
3257 tg3_flag(tp, FLASH) &&
3258 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3259 (tp->nvram_jedecnum == JEDEC_ATMEL))
3260
3261 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3262 tp->nvram_pagesize) +
3263 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3264
3265 return addr;
3266}
3267
e4f34110
MC		 3268/* NOTE: Data read in from NVRAM is byteswapped according to
3269 * the byteswapping settings for all other register accesses.
3270 * tg3 devices are BE devices, so on a BE machine, the data
3271 * returned will be exactly as it is seen in NVRAM. On a LE
3272 * machine, the 32-bit value will be byteswapped.
3273 */
ffbcfed4
MC		 3274static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3275{
3276 int ret;
3277
63c3a66f 3278 if (!tg3_flag(tp, NVRAM))
ffbcfed4
MC		 3279 return tg3_nvram_read_using_eeprom(tp, offset, val);
3280
3281 offset = tg3_nvram_phys_addr(tp, offset);
3282
3283 if (offset > NVRAM_ADDR_MSK)
3284 return -EINVAL;
3285
3286 ret = tg3_nvram_lock(tp);
3287 if (ret)
3288 return ret;
3289
3290 tg3_enable_nvram_access(tp);
3291
3292 tw32(NVRAM_ADDR, offset);
3293 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3294 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3295
3296 if (ret == 0)
e4f34110 3297 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 3298
3299 tg3_disable_nvram_access(tp);
3300
3301 tg3_nvram_unlock(tp);
3302
3303 return ret;
3304}
3305
a9dc529d
MC		 3306/* Ensures NVRAM data is in bytestream format. */
3307static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 3308{
3309 u32 v;
a9dc529d 3310 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 3311 if (!res)
a9dc529d 3312 *val = cpu_to_be32(v);
ffbcfed4
MC		 3313 return res;
3314}
3315
dbe9b92a
MC		 3316static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3317 u32 offset, u32 len, u8 *buf)
3318{
3319 int i, j, rc = 0;
3320 u32 val;
3321
3322 for (i = 0; i < len; i += 4) {
3323 u32 addr;
3324 __be32 data;
3325
3326 addr = offset + i;
3327
3328 memcpy(&data, buf + i, 4);
3329
3330 /*
3331 * The SEEPROM interface expects the data to always be opposite
3332 * the native endian format. We accomplish this by reversing
3333 * all the operations that would have been performed on the
3334 * data from a call to tg3_nvram_read_be32().
3335 */
3336 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3337
3338 val = tr32(GRC_EEPROM_ADDR);
3339 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3340
3341 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3342 EEPROM_ADDR_READ);
3343 tw32(GRC_EEPROM_ADDR, val |
3344 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3345 (addr & EEPROM_ADDR_ADDR_MASK) |
3346 EEPROM_ADDR_START |
3347 EEPROM_ADDR_WRITE);
3348
3349 for (j = 0; j < 1000; j++) {
3350 val = tr32(GRC_EEPROM_ADDR);
3351
3352 if (val & EEPROM_ADDR_COMPLETE)
3353 break;
3354 msleep(1);
3355 }
3356 if (!(val & EEPROM_ADDR_COMPLETE)) {
3357 rc = -EBUSY;
3358 break;
3359 }
3360 }
3361
3362 return rc;
3363}
3364
3365/* offset and length are dword aligned */
3366static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3367 u8 *buf)
3368{
3369 int ret = 0;
3370 u32 pagesize = tp->nvram_pagesize;
3371 u32 pagemask = pagesize - 1;
3372 u32 nvram_cmd;
3373 u8 *tmp;
3374
3375 tmp = kmalloc(pagesize, GFP_KERNEL);
3376 if (tmp == NULL)
3377 return -ENOMEM;
3378
3379 while (len) {
3380 int j;
3381 u32 phy_addr, page_off, size;
3382
3383 phy_addr = offset & ~pagemask;
3384
3385 for (j = 0; j < pagesize; j += 4) {
3386 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3387 (__be32 *) (tmp + j));
3388 if (ret)
3389 break;
3390 }
3391 if (ret)
3392 break;
3393
3394 page_off = offset & pagemask;
3395 size = pagesize;
3396 if (len < size)
3397 size = len;
3398
3399 len -= size;
3400
3401 memcpy(tmp + page_off, buf, size);
3402
3403 offset = offset + (pagesize - page_off);
3404
3405 tg3_enable_nvram_access(tp);
3406
3407 /*
3408 * Before we can erase the flash page, we need
3409 * to issue a special "write enable" command.
3410 */
3411 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3412
3413 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3414 break;
3415
3416 /* Erase the target page */
3417 tw32(NVRAM_ADDR, phy_addr);
3418
3419 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3420 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3421
3422 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3423 break;
3424
3425 /* Issue another write enable to start the write. */
3426 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3427
3428 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3429 break;
3430
3431 for (j = 0; j < pagesize; j += 4) {
3432 __be32 data;
3433
3434 data = *((__be32 *) (tmp + j));
3435
3436 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3437
3438 tw32(NVRAM_ADDR, phy_addr + j);
3439
3440 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3441 NVRAM_CMD_WR;
3442
3443 if (j == 0)
3444 nvram_cmd |= NVRAM_CMD_FIRST;
3445 else if (j == (pagesize - 4))
3446 nvram_cmd |= NVRAM_CMD_LAST;
3447
3448 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3449 if (ret)
3450 break;
3451 }
3452 if (ret)
3453 break;
3454 }
3455
3456 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3457 tg3_nvram_exec_cmd(tp, nvram_cmd);
3458
3459 kfree(tmp);
3460
3461 return ret;
3462}
3463
3464/* offset and length are dword aligned */
3465static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3466 u8 *buf)
3467{
3468 int i, ret = 0;
3469
3470 for (i = 0; i < len; i += 4, offset += 4) {
3471 u32 page_off, phy_addr, nvram_cmd;
3472 __be32 data;
3473
3474 memcpy(&data, buf + i, 4);
3475 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3476
3477 page_off = offset % tp->nvram_pagesize;
3478
3479 phy_addr = tg3_nvram_phys_addr(tp, offset);
3480
dbe9b92a
MC		 3481 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3482
3483 if (page_off == 0 || i == 0)
3484 nvram_cmd |= NVRAM_CMD_FIRST;
3485 if (page_off == (tp->nvram_pagesize - 4))
3486 nvram_cmd |= NVRAM_CMD_LAST;
3487
3488 if (i == (len - 4))
3489 nvram_cmd |= NVRAM_CMD_LAST;
3490
42278224
MC		 3491 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3492 !tg3_flag(tp, FLASH) ||
3493 !tg3_flag(tp, 57765_PLUS))
3494 tw32(NVRAM_ADDR, phy_addr);
3495
4153577a 3496 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
dbe9b92a
MC		 3497 !tg3_flag(tp, 5755_PLUS) &&
3498 (tp->nvram_jedecnum == JEDEC_ST) &&
3499 (nvram_cmd & NVRAM_CMD_FIRST)) {
3500 u32 cmd;
3501
3502 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3503 ret = tg3_nvram_exec_cmd(tp, cmd);
3504 if (ret)
3505 break;
3506 }
3507 if (!tg3_flag(tp, FLASH)) {
3508 /* We always do complete word writes to eeprom. */
3509 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3510 }
3511
3512 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3513 if (ret)
3514 break;
3515 }
3516 return ret;
3517}
3518
3519/* offset and length are dword aligned */
3520static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3521{
3522 int ret;
3523
3524 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3525 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3526 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3527 udelay(40);
3528 }
3529
3530 if (!tg3_flag(tp, NVRAM)) {
3531 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3532 } else {
3533 u32 grc_mode;
3534
3535 ret = tg3_nvram_lock(tp);
3536 if (ret)
3537 return ret;
3538
3539 tg3_enable_nvram_access(tp);
3540 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3541 tw32(NVRAM_WRITE1, 0x406);
3542
3543 grc_mode = tr32(GRC_MODE);
3544 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3545
3546 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3547 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3548 buf);
3549 } else {
3550 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3551 buf);
3552 }
3553
3554 grc_mode = tr32(GRC_MODE);
3555 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3556
3557 tg3_disable_nvram_access(tp);
3558 tg3_nvram_unlock(tp);
3559 }
3560
3561 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3562 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3563 udelay(40);
3564 }
3565
3566 return ret;
3567}
3568
997b4f13
MC		 3569#define RX_CPU_SCRATCH_BASE 0x30000
3570#define RX_CPU_SCRATCH_SIZE 0x04000
3571#define TX_CPU_SCRATCH_BASE 0x34000
3572#define TX_CPU_SCRATCH_SIZE 0x04000
3573
3574/* tp->lock is held. */
837c45bb 3575static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
997b4f13
MC		 3576{
3577 int i;
837c45bb 3578 const int iters = 10000;
997b4f13 3579
837c45bb
NS		 3580 for (i = 0; i < iters; i++) {
3581 tw32(cpu_base + CPU_STATE, 0xffffffff);
3582 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3583 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3584 break;
6d446ec3
GS		 3585 if (pci_channel_offline(tp->pdev))
3586 return -EBUSY;
837c45bb
NS		 3587 }
3588
3589 return (i == iters) ? -EBUSY : 0;
3590}
3591
3592/* tp->lock is held. */
3593static int tg3_rxcpu_pause(struct tg3 *tp)
3594{
3595 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3596
3597 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3598 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3599 udelay(10);
3600
3601 return rc;
3602}
3603
3604/* tp->lock is held. */
3605static int tg3_txcpu_pause(struct tg3 *tp)
3606{
3607 return tg3_pause_cpu(tp, TX_CPU_BASE);
3608}
3609
3610/* tp->lock is held. */
3611static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3612{
3613 tw32(cpu_base + CPU_STATE, 0xffffffff);
3614 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3615}
3616
3617/* tp->lock is held. */
3618static void tg3_rxcpu_resume(struct tg3 *tp)
3619{
3620 tg3_resume_cpu(tp, RX_CPU_BASE);
3621}
3622
3623/* tp->lock is held. */
3624static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3625{
3626 int rc;
3627
3628 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
997b4f13 3629
4153577a 3630 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
997b4f13
MC		 3631 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3632
3633 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3634 return 0;
3635 }
837c45bb
NS		 3636 if (cpu_base == RX_CPU_BASE) {
3637 rc = tg3_rxcpu_pause(tp);
997b4f13 3638 } else {
7e6c63f0
HM		 3639 /*
3640 * There is only an Rx CPU for the 5750 derivative in the
3641 * BCM4785.
3642 */
3643 if (tg3_flag(tp, IS_SSB_CORE))
3644 return 0;
3645
837c45bb 3646 rc = tg3_txcpu_pause(tp);
997b4f13
MC		 3647 }
3648
837c45bb 3649 if (rc) {
997b4f13 3650 netdev_err(tp->dev, "%s timed out, %s CPU\n",
837c45bb 3651 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
997b4f13
MC		 3652 return -ENODEV;
3653 }
3654
3655 /* Clear firmware's nvram arbitration. */
3656 if (tg3_flag(tp, NVRAM))
3657 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3658 return 0;
3659}
3660
31f11a95
NS		 3661static int tg3_fw_data_len(struct tg3 *tp,
3662 const struct tg3_firmware_hdr *fw_hdr)
3663{
3664 int fw_len;
3665
3666 /* Non fragmented firmware have one firmware header followed by a
3667 * contiguous chunk of data to be written. The length field in that
3668 * header is not the length of data to be written but the complete
3669 * length of the bss. The data length is determined based on
3670 * tp->fw->size minus headers.
3671 *
3672 * Fragmented firmware have a main header followed by multiple
3673 * fragments. Each fragment is identical to non fragmented firmware
3674 * with a firmware header followed by a contiguous chunk of data. In
3675 * the main header, the length field is unused and set to 0xffffffff.
3676 * In each fragment header the length is the entire size of that
3677 * fragment i.e. fragment data + header length. Data length is
3678 * therefore length field in the header minus TG3_FW_HDR_LEN.
3679 */
3680 if (tp->fw_len == 0xffffffff)
3681 fw_len = be32_to_cpu(fw_hdr->len);
3682 else
3683 fw_len = tp->fw->size;
3684
3685 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3686}
3687
997b4f13
MC		 3688/* tp->lock is held. */
3689static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3690 u32 cpu_scratch_base, int cpu_scratch_size,
77997ea3 3691 const struct tg3_firmware_hdr *fw_hdr)
997b4f13 3692{
c4dab506 3693 int err, i;
997b4f13 3694 void (*write_op)(struct tg3 *, u32, u32);
31f11a95 3695 int total_len = tp->fw->size;
997b4f13
MC		 3696
3697 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3698 netdev_err(tp->dev,
3699 "%s: Trying to load TX cpu firmware which is 5705\n",
3700 __func__);
3701 return -EINVAL;
3702 }
3703
c4dab506 3704 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
997b4f13
MC		 3705 write_op = tg3_write_mem;
3706 else
3707 write_op = tg3_write_indirect_reg32;
3708
c4dab506
NS		 3709 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3710 /* It is possible that bootcode is still loading at this point.
3711 * Get the nvram lock first before halting the cpu.
3712 */
3713 int lock_err = tg3_nvram_lock(tp);
3714 err = tg3_halt_cpu(tp, cpu_base);
3715 if (!lock_err)
3716 tg3_nvram_unlock(tp);
3717 if (err)
3718 goto out;
997b4f13 3719
c4dab506
NS		 3720 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3721 write_op(tp, cpu_scratch_base + i, 0);
3722 tw32(cpu_base + CPU_STATE, 0xffffffff);
3723 tw32(cpu_base + CPU_MODE,
3724 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3725 } else {
3726 /* Subtract additional main header for fragmented firmware and
3727 * advance to the first fragment
3728 */
3729 total_len -= TG3_FW_HDR_LEN;
3730 fw_hdr++;
3731 }
77997ea3 3732
31f11a95
NS		 3733 do {
3734 u32 *fw_data = (u32 *)(fw_hdr + 1);
3735 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3736 write_op(tp, cpu_scratch_base +
3737 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3738 (i * sizeof(u32)),
3739 be32_to_cpu(fw_data[i]));
3740
3741 total_len -= be32_to_cpu(fw_hdr->len);
3742
3743 /* Advance to next fragment */
3744 fw_hdr = (struct tg3_firmware_hdr *)
3745 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3746 } while (total_len > 0);
997b4f13
MC		 3747
3748 err = 0;
3749
3750out:
3751 return err;
3752}
3753
f4bffb28
NS		 3754/* tp->lock is held. */
3755static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3756{
3757 int i;
3758 const int iters = 5;
3759
3760 tw32(cpu_base + CPU_STATE, 0xffffffff);
3761 tw32_f(cpu_base + CPU_PC, pc);
3762
3763 for (i = 0; i < iters; i++) {
3764 if (tr32(cpu_base + CPU_PC) == pc)
3765 break;
3766 tw32(cpu_base + CPU_STATE, 0xffffffff);
3767 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3768 tw32_f(cpu_base + CPU_PC, pc);
3769 udelay(1000);
3770 }
3771
3772 return (i == iters) ? -EBUSY : 0;
3773}
3774
997b4f13
MC		 3775/* tp->lock is held. */
3776static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3777{
77997ea3 3778 const struct tg3_firmware_hdr *fw_hdr;
f4bffb28 3779 int err;
997b4f13 3780
77997ea3 3781 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3782
3783 /* Firmware blob starts with version numbers, followed by
3784 start address and length. We are setting complete length.
3785 length = end_address_of_bss - start_address_of_text.
3786 Remainder is the blob to be loaded contiguously
3787 from start address. */
3788
997b4f13
MC		 3789 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3790 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
77997ea3 3791 fw_hdr);
997b4f13
MC		 3792 if (err)
3793 return err;
3794
3795 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3796 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
77997ea3 3797 fw_hdr);
997b4f13
MC		 3798 if (err)
3799 return err;
3800
3801 /* Now startup only the RX cpu. */
77997ea3
NS		 3802 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3803 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3804 if (err) {
997b4f13
MC		 3805 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3806 "should be %08x\n", __func__,
77997ea3
NS		 3807 tr32(RX_CPU_BASE + CPU_PC),
3808 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3809 return -ENODEV;
3810 }
837c45bb
NS		 3811
3812 tg3_rxcpu_resume(tp);
997b4f13
MC		 3813
3814 return 0;
3815}
3816
c4dab506
NS		 3817static int tg3_validate_rxcpu_state(struct tg3 *tp)
3818{
3819 const int iters = 1000;
3820 int i;
3821 u32 val;
3822
3823 /* Wait for boot code to complete initialization and enter service
3824 * loop. It is then safe to download service patches
3825 */
3826 for (i = 0; i < iters; i++) {
3827 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3828 break;
3829
3830 udelay(10);
3831 }
3832
3833 if (i == iters) {
3834 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3835 return -EBUSY;
3836 }
3837
3838 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3839 if (val & 0xff) {
3840 netdev_warn(tp->dev,
3841 "Other patches exist. Not downloading EEE patch\n");
3842 return -EEXIST;
3843 }
3844
3845 return 0;
3846}
3847
3848/* tp->lock is held. */
3849static void tg3_load_57766_firmware(struct tg3 *tp)
3850{
3851 struct tg3_firmware_hdr *fw_hdr;
3852
3853 if (!tg3_flag(tp, NO_NVRAM))
3854 return;
3855
3856 if (tg3_validate_rxcpu_state(tp))
3857 return;
3858
3859 if (!tp->fw)
3860 return;
3861
3862 /* This firmware blob has a different format than older firmware
3863 * releases as given below. The main difference is we have fragmented
3864 * data to be written to non-contiguous locations.
3865 *
3866 * In the beginning we have a firmware header identical to other
3867 * firmware which consists of version, base addr and length. The length
3868 * here is unused and set to 0xffffffff.
3869 *
3870 * This is followed by a series of firmware fragments which are
3871 * individually identical to previous firmware. i.e. they have the
3872 * firmware header and followed by data for that fragment. The version
3873 * field of the individual fragment header is unused.
3874 */
3875
3876 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3877 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3878 return;
3879
3880 if (tg3_rxcpu_pause(tp))
3881 return;
3882
3883 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3884 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3885
3886 tg3_rxcpu_resume(tp);
3887}
3888
997b4f13
MC		 3889/* tp->lock is held. */
3890static int tg3_load_tso_firmware(struct tg3 *tp)
3891{
77997ea3 3892 const struct tg3_firmware_hdr *fw_hdr;
997b4f13 3893 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
f4bffb28 3894 int err;
997b4f13 3895
1caf13eb 3896 if (!tg3_flag(tp, FW_TSO))
997b4f13
MC		 3897 return 0;
3898
77997ea3 3899 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3900
3901 /* Firmware blob starts with version numbers, followed by
3902 start address and length. We are setting complete length.
3903 length = end_address_of_bss - start_address_of_text.
3904 Remainder is the blob to be loaded contiguously
3905 from start address. */
3906
997b4f13 3907 cpu_scratch_size = tp->fw_len;
997b4f13 3908
4153577a 3909 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
997b4f13
MC		 3910 cpu_base = RX_CPU_BASE;
3911 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3912 } else {
3913 cpu_base = TX_CPU_BASE;
3914 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3915 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3916 }
3917
3918 err = tg3_load_firmware_cpu(tp, cpu_base,
3919 cpu_scratch_base, cpu_scratch_size,
77997ea3 3920 fw_hdr);
997b4f13
MC		 3921 if (err)
3922 return err;
3923
3924 /* Now startup the cpu. */
77997ea3
NS		 3925 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3926 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3927 if (err) {
997b4f13
MC		 3928 netdev_err(tp->dev,
3929 "%s fails to set CPU PC, is %08x should be %08x\n",
77997ea3
NS		 3930 __func__, tr32(cpu_base + CPU_PC),
3931 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3932 return -ENODEV;
3933 }
837c45bb
NS		 3934
3935 tg3_resume_cpu(tp, cpu_base);
997b4f13
MC		 3936 return 0;
3937}
3938
3939
3f007891 3940/* tp->lock is held. */
953c96e0 3941static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3f007891
MC		 3942{
3943 u32 addr_high, addr_low;
3944 int i;
3945
3946 addr_high = ((tp->dev->dev_addr[0] << 8) |
3947 tp->dev->dev_addr[1]);
3948 addr_low = ((tp->dev->dev_addr[2] << 24) |
3949 (tp->dev->dev_addr[3] << 16) |
3950 (tp->dev->dev_addr[4] << 8) |
3951 (tp->dev->dev_addr[5] << 0));
3952 for (i = 0; i < 4; i++) {
3953 if (i == 1 && skip_mac_1)
3954 continue;
3955 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3956 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3957 }
3958
4153577a
JP		 3959 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3960 tg3_asic_rev(tp) == ASIC_REV_5704) {
3f007891
MC		 3961 for (i = 0; i < 12; i++) {
3962 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3963 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3964 }
3965 }
3966
3967 addr_high = (tp->dev->dev_addr[0] +
3968 tp->dev->dev_addr[1] +
3969 tp->dev->dev_addr[2] +
3970 tp->dev->dev_addr[3] +
3971 tp->dev->dev_addr[4] +
3972 tp->dev->dev_addr[5]) &
3973 TX_BACKOFF_SEED_MASK;
3974 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3975}
3976
c866b7ea 3977static void tg3_enable_register_access(struct tg3 *tp)
1da177e4 3978{
c866b7ea
RW		 3979 /*
3980 * Make sure register accesses (indirect or otherwise) will function
3981 * correctly.
1da177e4
LT		 3982 */
3983 pci_write_config_dword(tp->pdev,
c866b7ea
RW		 3984 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3985}
1da177e4 3986
c866b7ea
RW		 3987static int tg3_power_up(struct tg3 *tp)
3988{
bed9829f 3989 int err;
8c6bda1a 3990
bed9829f 3991 tg3_enable_register_access(tp);
1da177e4 3992
bed9829f
MC		 3993 err = pci_set_power_state(tp->pdev, PCI_D0);
3994 if (!err) {
3995 /* Switch out of Vaux if it is a NIC */
3996 tg3_pwrsrc_switch_to_vmain(tp);
3997 } else {
3998 netdev_err(tp->dev, "Transition to D0 failed\n");
3999 }
1da177e4 4000
bed9829f 4001 return err;
c866b7ea 4002}
1da177e4 4003
953c96e0 4004static int tg3_setup_phy(struct tg3 *, bool);
4b409522 4005
c866b7ea
RW		 4006static int tg3_power_down_prepare(struct tg3 *tp)
4007{
4008 u32 misc_host_ctrl;
4009 bool device_should_wake, do_low_power;
4010
4011 tg3_enable_register_access(tp);
5e7dfd0f
MC		 4012
4013 /* Restore the CLKREQ setting. */
0f49bfbd
JL		 4014 if (tg3_flag(tp, CLKREQ_BUG))
4015 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4016 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 4017
1da177e4
LT		 4018 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4019 tw32(TG3PCI_MISC_HOST_CTRL,
4020 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4021
c866b7ea 4022 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
63c3a66f 4023 tg3_flag(tp, WOL_ENABLE);
05ac4cb7 4024
63c3a66f 4025 if (tg3_flag(tp, USE_PHYLIB)) {
0a459aac 4026 do_low_power = false;
f07e9af3 4027 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
80096068 4028 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
b02fd9e3 4029 struct phy_device *phydev;
0a459aac 4030 u32 phyid, advertising;
b02fd9e3 4031
3f0e3ad7 4032 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 4033
80096068 4034 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
b02fd9e3 4035
c6700ce2
MC		 4036 tp->link_config.speed = phydev->speed;
4037 tp->link_config.duplex = phydev->duplex;
4038 tp->link_config.autoneg = phydev->autoneg;
4039 tp->link_config.advertising = phydev->advertising;
b02fd9e3
MC		 4040
4041 advertising = ADVERTISED_TP |
4042 ADVERTISED_Pause |
4043 ADVERTISED_Autoneg |
4044 ADVERTISED_10baseT_Half;
4045
63c3a66f
JP		 4046 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4047 if (tg3_flag(tp, WOL_SPEED_100MB))
b02fd9e3
MC		 4048 advertising |=
4049 ADVERTISED_100baseT_Half |
4050 ADVERTISED_100baseT_Full |
4051 ADVERTISED_10baseT_Full;
4052 else
4053 advertising |= ADVERTISED_10baseT_Full;
4054 }
4055
4056 phydev->advertising = advertising;
4057
4058 phy_start_aneg(phydev);
0a459aac
MC		 4059
4060 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 4061 if (phyid != PHY_ID_BCMAC131) {
4062 phyid &= PHY_BCM_OUI_MASK;
4063 if (phyid == PHY_BCM_OUI_1 ||
4064 phyid == PHY_BCM_OUI_2 ||
4065 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 4066 do_low_power = true;
4067 }
b02fd9e3 4068 }
dd477003 4069 } else {
2023276e 4070 do_low_power = true;
0a459aac 4071
c6700ce2 4072 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
80096068 4073 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
1da177e4 4074
2855b9fe 4075 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
953c96e0 4076 tg3_setup_phy(tp, false);
1da177e4
LT		 4077 }
4078
4153577a 4079 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 4080 u32 val;
4081
4082 val = tr32(GRC_VCPU_EXT_CTRL);
4083 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
63c3a66f 4084 } else if (!tg3_flag(tp, ENABLE_ASF)) {
6921d201
MC		 4085 int i;
4086 u32 val;
4087
4088 for (i = 0; i < 200; i++) {
4089 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4090 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4091 break;
4092 msleep(1);
4093 }
4094 }
63c3a66f 4095 if (tg3_flag(tp, WOL_CAP))
a85feb8c
GZ		 4096 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4097 WOL_DRV_STATE_SHUTDOWN |
4098 WOL_DRV_WOL |
4099 WOL_SET_MAGIC_PKT);
6921d201 4100
05ac4cb7 4101 if (device_should_wake) {
1da177e4
LT		 4102 u32 mac_mode;
4103
f07e9af3 4104 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
b4bd2929
MC		 4105 if (do_low_power &&
4106 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4107 tg3_phy_auxctl_write(tp,
4108 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4109 MII_TG3_AUXCTL_PCTL_WOL_EN |
4110 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4111 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
dd477003
MC		 4112 udelay(40);
4113 }
1da177e4 4114
f07e9af3 4115 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3f7045c1 4116 mac_mode = MAC_MODE_PORT_MODE_GMII;
942d1af0
NS		 4117 else if (tp->phy_flags &
4118 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4119 if (tp->link_config.active_speed == SPEED_1000)
4120 mac_mode = MAC_MODE_PORT_MODE_GMII;
4121 else
4122 mac_mode = MAC_MODE_PORT_MODE_MII;
4123 } else
3f7045c1 4124 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 4125
e8f3f6ca 4126 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4153577a 4127 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
63c3a66f 4128 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
e8f3f6ca
MC		 4129 SPEED_100 : SPEED_10;
4130 if (tg3_5700_link_polarity(tp, speed))
4131 mac_mode |= MAC_MODE_LINK_POLARITY;
4132 else
4133 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4134 }
1da177e4
LT		 4135 } else {
4136 mac_mode = MAC_MODE_PORT_MODE_TBI;
4137 }
4138
63c3a66f 4139 if (!tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 4140 tw32(MAC_LED_CTRL, tp->led_ctrl);
4141
05ac4cb7 4142 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
63c3a66f
JP		 4143 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4144 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
05ac4cb7 4145 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 4146
63c3a66f 4147 if (tg3_flag(tp, ENABLE_APE))
d2394e6b
MC		 4148 mac_mode |= MAC_MODE_APE_TX_EN |
4149 MAC_MODE_APE_RX_EN |
4150 MAC_MODE_TDE_ENABLE;
3bda1258 4151
1da177e4
LT		 4152 tw32_f(MAC_MODE, mac_mode);
4153 udelay(100);
4154
4155 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4156 udelay(10);
4157 }
4158
63c3a66f 4159 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4153577a
JP		 4160 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4161 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 4162 u32 base_val;
4163
4164 base_val = tp->pci_clock_ctrl;
4165 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4166 CLOCK_CTRL_TXCLK_DISABLE);
4167
b401e9e2
MC		 4168 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4169 CLOCK_CTRL_PWRDOWN_PLL133, 40);
63c3a66f
JP		 4170 } else if (tg3_flag(tp, 5780_CLASS) ||
4171 tg3_flag(tp, CPMU_PRESENT) ||
4153577a 4172 tg3_asic_rev(tp) == ASIC_REV_5906) {
4cf78e4f 4173 /* do nothing */
63c3a66f 4174 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
1da177e4
LT		 4175 u32 newbits1, newbits2;
4176
4153577a
JP		 4177 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4178 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4179 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4180 CLOCK_CTRL_TXCLK_DISABLE |
4181 CLOCK_CTRL_ALTCLK);
4182 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
63c3a66f 4183 } else if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4184 newbits1 = CLOCK_CTRL_625_CORE;
4185 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4186 } else {
4187 newbits1 = CLOCK_CTRL_ALTCLK;
4188 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4189 }
4190
b401e9e2
MC		 4191 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4192 40);
1da177e4 4193
b401e9e2
MC		 4194 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4195 40);
1da177e4 4196
63c3a66f 4197 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4198 u32 newbits3;
4199
4153577a
JP		 4200 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4201 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4202 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4203 CLOCK_CTRL_TXCLK_DISABLE |
4204 CLOCK_CTRL_44MHZ_CORE);
4205 } else {
4206 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4207 }
4208
b401e9e2
MC		 4209 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4210 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 4211 }
4212 }
4213
63c3a66f 4214 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
0a459aac 4215 tg3_power_down_phy(tp, do_low_power);
6921d201 4216
cd0d7228 4217 tg3_frob_aux_power(tp, true);
1da177e4
LT		 4218
4219 /* Workaround for unstable PLL clock */
7e6c63f0 4220 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4153577a
JP		 4221 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4222 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
1da177e4
LT		 4223 u32 val = tr32(0x7d00);
4224
4225 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4226 tw32(0x7d00, val);
63c3a66f 4227 if (!tg3_flag(tp, ENABLE_ASF)) {
ec41c7df
MC		 4228 int err;
4229
4230 err = tg3_nvram_lock(tp);
1da177e4 4231 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 4232 if (!err)
4233 tg3_nvram_unlock(tp);
6921d201 4234 }
1da177e4
LT		 4235 }
4236
bbadf503
MC		 4237 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4238
2e460fc0
NS		 4239 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4240
c866b7ea
RW		 4241 return 0;
4242}
12dac075 4243
c866b7ea
RW		 4244static void tg3_power_down(struct tg3 *tp)
4245{
63c3a66f 4246 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
c866b7ea 4247 pci_set_power_state(tp->pdev, PCI_D3hot);
1da177e4
LT		 4248}
4249
1da177e4
LT		 4250static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4251{
4252 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4253 case MII_TG3_AUX_STAT_10HALF:
4254 *speed = SPEED_10;
4255 *duplex = DUPLEX_HALF;
4256 break;
4257
4258 case MII_TG3_AUX_STAT_10FULL:
4259 *speed = SPEED_10;
4260 *duplex = DUPLEX_FULL;
4261 break;
4262
4263 case MII_TG3_AUX_STAT_100HALF:
4264 *speed = SPEED_100;
4265 *duplex = DUPLEX_HALF;
4266 break;
4267
4268 case MII_TG3_AUX_STAT_100FULL:
4269 *speed = SPEED_100;
4270 *duplex = DUPLEX_FULL;
4271 break;
4272
4273 case MII_TG3_AUX_STAT_1000HALF:
4274 *speed = SPEED_1000;
4275 *duplex = DUPLEX_HALF;
4276 break;
4277
4278 case MII_TG3_AUX_STAT_1000FULL:
4279 *speed = SPEED_1000;
4280 *duplex = DUPLEX_FULL;
4281 break;
4282
4283 default:
f07e9af3 4284 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
715116a1
MC		 4285 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4286 SPEED_10;
4287 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4288 DUPLEX_HALF;
4289 break;
4290 }
e740522e
MC		 4291 *speed = SPEED_UNKNOWN;
4292 *duplex = DUPLEX_UNKNOWN;
1da177e4 4293 break;
855e1111 4294 }
1da177e4
LT		 4295}
4296
42b64a45 4297static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
1da177e4 4298{
42b64a45
MC		 4299 int err = 0;
4300 u32 val, new_adv;
1da177e4 4301
42b64a45 4302 new_adv = ADVERTISE_CSMA;
202ff1c2 4303 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
f88788f0 4304 new_adv |= mii_advertise_flowctrl(flowctrl);
1da177e4 4305
42b64a45
MC		 4306 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4307 if (err)
4308 goto done;
ba4d07a8 4309
4f272096
MC		 4310 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4311 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
ba4d07a8 4312
4153577a
JP		 4313 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4314 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4f272096 4315 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
ba4d07a8 4316
4f272096
MC		 4317 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4318 if (err)
4319 goto done;
4320 }
1da177e4 4321
42b64a45
MC		 4322 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4323 goto done;
52b02d04 4324
42b64a45
MC		 4325 tw32(TG3_CPMU_EEE_MODE,
4326 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
52b02d04 4327
daf3ec68 4328 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
42b64a45
MC		 4329 if (!err) {
4330 u32 err2;
52b02d04 4331
b715ce94
MC		 4332 val = 0;
4333 /* Advertise 100-BaseTX EEE ability */
4334 if (advertise & ADVERTISED_100baseT_Full)
4335 val |= MDIO_AN_EEE_ADV_100TX;
4336 /* Advertise 1000-BaseT EEE ability */
4337 if (advertise & ADVERTISED_1000baseT_Full)
4338 val |= MDIO_AN_EEE_ADV_1000T;
9e2ecbeb
NS		 4339
4340 if (!tp->eee.eee_enabled) {
4341 val = 0;
4342 tp->eee.advertised = 0;
4343 } else {
4344 tp->eee.advertised = advertise &
4345 (ADVERTISED_100baseT_Full |
4346 ADVERTISED_1000baseT_Full);
4347 }
4348
b715ce94
MC		 4349 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4350 if (err)
4351 val = 0;
4352
4153577a 4353 switch (tg3_asic_rev(tp)) {
21a00ab2
MC		 4354 case ASIC_REV_5717:
4355 case ASIC_REV_57765:
55086ad9 4356 case ASIC_REV_57766:
21a00ab2 4357 case ASIC_REV_5719:
b715ce94
MC		 4358 /* If we advertised any eee advertisements above... */
4359 if (val)
4360 val = MII_TG3_DSP_TAP26_ALNOKO |
4361 MII_TG3_DSP_TAP26_RMRXSTO |
4362 MII_TG3_DSP_TAP26_OPCSINPT;
21a00ab2 4363 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
be671947
MC		 4364 /* Fall through */
4365 case ASIC_REV_5720:
c65a17f4 4366 case ASIC_REV_5762:
be671947
MC		 4367 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4368 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4369 MII_TG3_DSP_CH34TP2_HIBW01);
21a00ab2 4370 }
52b02d04 4371
daf3ec68 4372 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
42b64a45
MC		 4373 if (!err)
4374 err = err2;
4375 }
4376
4377done:
4378 return err;
4379}
4380
4381static void tg3_phy_copper_begin(struct tg3 *tp)
4382{
d13ba512
MC		 4383 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4384 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4385 u32 adv, fc;
4386
942d1af0
NS		 4387 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4388 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
d13ba512
MC		 4389 adv = ADVERTISED_10baseT_Half |
4390 ADVERTISED_10baseT_Full;
4391 if (tg3_flag(tp, WOL_SPEED_100MB))
4392 adv |= ADVERTISED_100baseT_Half |
4393 ADVERTISED_100baseT_Full;
942d1af0
NS		 4394 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK)
4395 adv |= ADVERTISED_1000baseT_Half |
4396 ADVERTISED_1000baseT_Full;
d13ba512
MC		 4397
4398 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
42b64a45 4399 } else {
d13ba512
MC		 4400 adv = tp->link_config.advertising;
4401 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4402 adv &= ~(ADVERTISED_1000baseT_Half |
4403 ADVERTISED_1000baseT_Full);
4404
4405 fc = tp->link_config.flowctrl;
52b02d04 4406 }
52b02d04 4407
d13ba512 4408 tg3_phy_autoneg_cfg(tp, adv, fc);
52b02d04 4409
942d1af0
NS		 4410 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4411 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4412 /* Normally during power down we want to autonegotiate
4413 * the lowest possible speed for WOL. However, to avoid
4414 * link flap, we leave it untouched.
4415 */
4416 return;
4417 }
4418
d13ba512
MC		 4419 tg3_writephy(tp, MII_BMCR,
4420 BMCR_ANENABLE | BMCR_ANRESTART);
4421 } else {
4422 int i;
1da177e4
LT		 4423 u32 bmcr, orig_bmcr;
4424
4425 tp->link_config.active_speed = tp->link_config.speed;
4426 tp->link_config.active_duplex = tp->link_config.duplex;
4427
7c6cdead
NS		 4428 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4429 /* With autoneg disabled, 5715 only links up when the
4430 * advertisement register has the configured speed
4431 * enabled.
4432 */
4433 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4434 }
4435
1da177e4
LT		 4436 bmcr = 0;
4437 switch (tp->link_config.speed) {
4438 default:
4439 case SPEED_10:
4440 break;
4441
4442 case SPEED_100:
4443 bmcr |= BMCR_SPEED100;
4444 break;
4445
4446 case SPEED_1000:
221c5637 4447 bmcr |= BMCR_SPEED1000;
1da177e4 4448 break;
855e1111 4449 }
1da177e4
LT		 4450
4451 if (tp->link_config.duplex == DUPLEX_FULL)
4452 bmcr |= BMCR_FULLDPLX;
4453
4454 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4455 (bmcr != orig_bmcr)) {
4456 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4457 for (i = 0; i < 1500; i++) {
4458 u32 tmp;
4459
4460 udelay(10);
4461 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4462 tg3_readphy(tp, MII_BMSR, &tmp))
4463 continue;
4464 if (!(tmp & BMSR_LSTATUS)) {
4465 udelay(40);
4466 break;
4467 }
4468 }
4469 tg3_writephy(tp, MII_BMCR, bmcr);
4470 udelay(40);
4471 }
1da177e4
LT		 4472 }
4473}
4474
fdad8de4
NS		 4475static int tg3_phy_pull_config(struct tg3 *tp)
4476{
4477 int err;
4478 u32 val;
4479
4480 err = tg3_readphy(tp, MII_BMCR, &val);
4481 if (err)
4482 goto done;
4483
4484 if (!(val & BMCR_ANENABLE)) {
4485 tp->link_config.autoneg = AUTONEG_DISABLE;
4486 tp->link_config.advertising = 0;
4487 tg3_flag_clear(tp, PAUSE_AUTONEG);
4488
4489 err = -EIO;
4490
4491 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4492 case 0:
4493 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4494 goto done;
4495
4496 tp->link_config.speed = SPEED_10;
4497 break;
4498 case BMCR_SPEED100:
4499 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4500 goto done;
4501
4502 tp->link_config.speed = SPEED_100;
4503 break;
4504 case BMCR_SPEED1000:
4505 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4506 tp->link_config.speed = SPEED_1000;
4507 break;
4508 }
4509 /* Fall through */
4510 default:
4511 goto done;
4512 }
4513
4514 if (val & BMCR_FULLDPLX)
4515 tp->link_config.duplex = DUPLEX_FULL;
4516 else
4517 tp->link_config.duplex = DUPLEX_HALF;
4518
4519 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4520
4521 err = 0;
4522 goto done;
4523 }
4524
4525 tp->link_config.autoneg = AUTONEG_ENABLE;
4526 tp->link_config.advertising = ADVERTISED_Autoneg;
4527 tg3_flag_set(tp, PAUSE_AUTONEG);
4528
4529 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4530 u32 adv;
4531
4532 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4533 if (err)
4534 goto done;
4535
4536 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4537 tp->link_config.advertising |= adv | ADVERTISED_TP;
4538
4539 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4540 } else {
4541 tp->link_config.advertising |= ADVERTISED_FIBRE;
4542 }
4543
4544 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4545 u32 adv;
4546
4547 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4548 err = tg3_readphy(tp, MII_CTRL1000, &val);
4549 if (err)
4550 goto done;
4551
4552 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4553 } else {
4554 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4555 if (err)
4556 goto done;
4557
4558 adv = tg3_decode_flowctrl_1000X(val);
4559 tp->link_config.flowctrl = adv;
4560
4561 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4562 adv = mii_adv_to_ethtool_adv_x(val);
4563 }
4564
4565 tp->link_config.advertising |= adv;
4566 }
4567
4568done:
4569 return err;
4570}
4571
1da177e4
LT		 4572static int tg3_init_5401phy_dsp(struct tg3 *tp)
4573{
4574 int err;
4575
4576 /* Turn off tap power management. */
4577 /* Set Extended packet length bit */
b4bd2929 4578 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
1da177e4 4579
6ee7c0a0
MC		 4580 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4581 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4582 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4583 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4584 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
1da177e4
LT		 4585
4586 udelay(40);
4587
4588 return err;
4589}
4590
ed1ff5c3
NS		 4591static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4592{
5b6c273a 4593 struct ethtool_eee eee;
ed1ff5c3
NS		 4594
4595 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4596 return true;
4597
5b6c273a 4598 tg3_eee_pull_config(tp, &eee);
ed1ff5c3 4599
5b6c273a
NS		 4600 if (tp->eee.eee_enabled) {
4601 if (tp->eee.advertised != eee.advertised ||
4602 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4603 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4604 return false;
4605 } else {
4606 /* EEE is disabled but we're advertising */
4607 if (eee.advertised)
4608 return false;
4609 }
ed1ff5c3
NS		 4610
4611 return true;
4612}
4613
e2bf73e7 4614static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
1da177e4 4615{
e2bf73e7 4616 u32 advmsk, tgtadv, advertising;
3600d918 4617
e2bf73e7
MC		 4618 advertising = tp->link_config.advertising;
4619 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
1da177e4 4620
e2bf73e7
MC		 4621 advmsk = ADVERTISE_ALL;
4622 if (tp->link_config.active_duplex == DUPLEX_FULL) {
f88788f0 4623 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
e2bf73e7
MC		 4624 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4625 }
1da177e4 4626
e2bf73e7
MC		 4627 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4628 return false;
4629
4630 if ((*lcladv & advmsk) != tgtadv)
4631 return false;
b99d2a57 4632
f07e9af3 4633 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1da177e4
LT		 4634 u32 tg3_ctrl;
4635
e2bf73e7 4636 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
3600d918 4637
221c5637 4638 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
e2bf73e7 4639 return false;
1da177e4 4640
3198e07f 4641 if (tgtadv &&
4153577a
JP		 4642 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4643 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
3198e07f
MC		 4644 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4645 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4646 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4647 } else {
4648 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4649 }
4650
e2bf73e7
MC		 4651 if (tg3_ctrl != tgtadv)
4652 return false;
ef167e27
MC		 4653 }
4654
e2bf73e7 4655 return true;
ef167e27
MC		 4656}
4657
859edb26
MC		 4658static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4659{
4660 u32 lpeth = 0;
4661
4662 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4663 u32 val;
4664
4665 if (tg3_readphy(tp, MII_STAT1000, &val))
4666 return false;
4667
4668 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4669 }
4670
4671 if (tg3_readphy(tp, MII_LPA, rmtadv))
4672 return false;
4673
4674 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4675 tp->link_config.rmt_adv = lpeth;
4676
4677 return true;
4678}
4679
953c96e0 4680static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
f4a46d1f
NNS		 4681{
4682 if (curr_link_up != tp->link_up) {
4683 if (curr_link_up) {
84421b99 4684 netif_carrier_on(tp->dev);
f4a46d1f 4685 } else {
84421b99 4686 netif_carrier_off(tp->dev);
f4a46d1f
NNS		 4687 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4688 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4689 }
4690
4691 tg3_link_report(tp);
4692 return true;
4693 }
4694
4695 return false;
4696}
4697
3310e248
MC		 4698static void tg3_clear_mac_status(struct tg3 *tp)
4699{
4700 tw32(MAC_EVENT, 0);
4701
4702 tw32_f(MAC_STATUS,
4703 MAC_STATUS_SYNC_CHANGED |
4704 MAC_STATUS_CFG_CHANGED |
4705 MAC_STATUS_MI_COMPLETION |
4706 MAC_STATUS_LNKSTATE_CHANGED);
4707 udelay(40);
4708}
4709
9e2ecbeb
NS		 4710static void tg3_setup_eee(struct tg3 *tp)
4711{
4712 u32 val;
4713
4714 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4715 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4716 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4717 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4718
4719 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4720
4721 tw32_f(TG3_CPMU_EEE_CTRL,
4722 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4723
4724 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4725 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4726 TG3_CPMU_EEEMD_LPI_IN_RX |
4727 TG3_CPMU_EEEMD_EEE_ENABLE;
4728
4729 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4730 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4731
4732 if (tg3_flag(tp, ENABLE_APE))
4733 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4734
4735 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4736
4737 tw32_f(TG3_CPMU_EEE_DBTMR1,
4738 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4739 (tp->eee.tx_lpi_timer & 0xffff));
4740
4741 tw32_f(TG3_CPMU_EEE_DBTMR2,
4742 TG3_CPMU_DBTMR2_APE_TX_2047US |
4743 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4744}
4745
953c96e0 4746static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
1da177e4 4747{
953c96e0 4748 bool current_link_up;
f833c4c1 4749 u32 bmsr, val;
ef167e27 4750 u32 lcl_adv, rmt_adv;
1da177e4
LT		 4751 u16 current_speed;
4752 u8 current_duplex;
4753 int i, err;
4754
3310e248 4755 tg3_clear_mac_status(tp);
1da177e4 4756
8ef21428
MC		 4757 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4758 tw32_f(MAC_MI_MODE,
4759 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4760 udelay(80);
4761 }
1da177e4 4762
b4bd2929 4763 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
1da177e4
LT		 4764
4765 /* Some third-party PHYs need to be reset on link going
4766 * down.
4767 */
4153577a
JP		 4768 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4769 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4770 tg3_asic_rev(tp) == ASIC_REV_5705) &&
f4a46d1f 4771 tp->link_up) {
1da177e4
LT		 4772 tg3_readphy(tp, MII_BMSR, &bmsr);
4773 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4774 !(bmsr & BMSR_LSTATUS))
953c96e0 4775 force_reset = true;
1da177e4
LT		 4776 }
4777 if (force_reset)
4778 tg3_phy_reset(tp);
4779
79eb6904 4780 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 4781 tg3_readphy(tp, MII_BMSR, &bmsr);
4782 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
63c3a66f 4783 !tg3_flag(tp, INIT_COMPLETE))
1da177e4
LT		 4784 bmsr = 0;
4785
4786 if (!(bmsr & BMSR_LSTATUS)) {
4787 err = tg3_init_5401phy_dsp(tp);
4788 if (err)
4789 return err;
4790
4791 tg3_readphy(tp, MII_BMSR, &bmsr);
4792 for (i = 0; i < 1000; i++) {
4793 udelay(10);
4794 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4795 (bmsr & BMSR_LSTATUS)) {
4796 udelay(40);
4797 break;
4798 }
4799 }
4800
79eb6904
MC		 4801 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4802 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 4803 !(bmsr & BMSR_LSTATUS) &&
4804 tp->link_config.active_speed == SPEED_1000) {
4805 err = tg3_phy_reset(tp);
4806 if (!err)
4807 err = tg3_init_5401phy_dsp(tp);
4808 if (err)
4809 return err;
4810 }
4811 }
4153577a
JP		 4812 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4813 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
1da177e4
LT		 4814 /* 5701 {A0,B0} CRC bug workaround */
4815 tg3_writephy(tp, 0x15, 0x0a75);
f08aa1a8
MC		 4816 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4817 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4818 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
1da177e4
LT		 4819 }
4820
4821 /* Clear pending interrupts... */
f833c4c1
MC		 4822 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4823 tg3_readphy(tp, MII_TG3_ISTAT, &val);
1da177e4 4824
f07e9af3 4825 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
1da177e4 4826 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
f07e9af3 4827 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
1da177e4
LT		 4828 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4829
4153577a
JP		 4830 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4831 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4832 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4833 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4834 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4835 else
4836 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4837 }
4838
953c96e0 4839 current_link_up = false;
e740522e
MC		 4840 current_speed = SPEED_UNKNOWN;
4841 current_duplex = DUPLEX_UNKNOWN;
e348c5e7 4842 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
859edb26 4843 tp->link_config.rmt_adv = 0;
1da177e4 4844
f07e9af3 4845 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
15ee95c3
MC		 4846 err = tg3_phy_auxctl_read(tp,
4847 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4848 &val);
4849 if (!err && !(val & (1 << 10))) {
b4bd2929
MC		 4850 tg3_phy_auxctl_write(tp,
4851 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4852 val | (1 << 10));
1da177e4
LT		 4853 goto relink;
4854 }
4855 }
4856
4857 bmsr = 0;
4858 for (i = 0; i < 100; i++) {
4859 tg3_readphy(tp, MII_BMSR, &bmsr);
4860 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4861 (bmsr & BMSR_LSTATUS))
4862 break;
4863 udelay(40);
4864 }
4865
4866 if (bmsr & BMSR_LSTATUS) {
4867 u32 aux_stat, bmcr;
4868
4869 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4870 for (i = 0; i < 2000; i++) {
4871 udelay(10);
4872 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4873 aux_stat)
4874 break;
4875 }
4876
4877 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4878 &current_speed,
4879 &current_duplex);
4880
4881 bmcr = 0;
4882 for (i = 0; i < 200; i++) {
4883 tg3_readphy(tp, MII_BMCR, &bmcr);
4884 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4885 continue;
4886 if (bmcr && bmcr != 0x7fff)
4887 break;
4888 udelay(10);
4889 }
4890
ef167e27
MC		 4891 lcl_adv = 0;
4892 rmt_adv = 0;
1da177e4 4893
ef167e27
MC		 4894 tp->link_config.active_speed = current_speed;
4895 tp->link_config.active_duplex = current_duplex;
4896
4897 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
ed1ff5c3
NS		 4898 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4899
ef167e27 4900 if ((bmcr & BMCR_ANENABLE) &&
ed1ff5c3 4901 eee_config_ok &&
e2bf73e7 4902 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
859edb26 4903 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
953c96e0 4904 current_link_up = true;
ed1ff5c3
NS		 4905
4906 /* EEE settings changes take effect only after a phy
4907 * reset. If we have skipped a reset due to Link Flap
4908 * Avoidance being enabled, do it now.
4909 */
4910 if (!eee_config_ok &&
4911 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
5b6c273a
NS		 4912 !force_reset) {
4913 tg3_setup_eee(tp);
ed1ff5c3 4914 tg3_phy_reset(tp);
5b6c273a 4915 }
1da177e4
LT		 4916 } else {
4917 if (!(bmcr & BMCR_ANENABLE) &&
4918 tp->link_config.speed == current_speed &&
f0fcd7a9 4919 tp->link_config.duplex == current_duplex) {
953c96e0 4920 current_link_up = true;
1da177e4
LT		 4921 }
4922 }
4923
953c96e0 4924 if (current_link_up &&
e348c5e7
MC		 4925 tp->link_config.active_duplex == DUPLEX_FULL) {
4926 u32 reg, bit;
4927
4928 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4929 reg = MII_TG3_FET_GEN_STAT;
4930 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4931 } else {
4932 reg = MII_TG3_EXT_STAT;
4933 bit = MII_TG3_EXT_STAT_MDIX;
4934 }
4935
4936 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4937 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4938
ef167e27 4939 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
e348c5e7 4940 }
1da177e4
LT		 4941 }
4942
1da177e4 4943relink:
953c96e0 4944 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
1da177e4
LT		 4945 tg3_phy_copper_begin(tp);
4946
7e6c63f0 4947 if (tg3_flag(tp, ROBOSWITCH)) {
953c96e0 4948 current_link_up = true;
7e6c63f0
HM		 4949 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4950 current_speed = SPEED_1000;
4951 current_duplex = DUPLEX_FULL;
4952 tp->link_config.active_speed = current_speed;
4953 tp->link_config.active_duplex = current_duplex;
4954 }
4955
f833c4c1 4956 tg3_readphy(tp, MII_BMSR, &bmsr);
06c03c02
MB		 4957 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4958 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
953c96e0 4959 current_link_up = true;
1da177e4
LT		 4960 }
4961
4962 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
953c96e0 4963 if (current_link_up) {
1da177e4
LT		 4964 if (tp->link_config.active_speed == SPEED_100 ||
4965 tp->link_config.active_speed == SPEED_10)
4966 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4967 else
4968 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
f07e9af3 4969 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7f97a4bd
MC		 4970 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4971 else
1da177e4
LT		 4972 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4973
7e6c63f0
HM		 4974 /* In order for the 5750 core in BCM4785 chip to work properly
4975 * in RGMII mode, the Led Control Register must be set up.
4976 */
4977 if (tg3_flag(tp, RGMII_MODE)) {
4978 u32 led_ctrl = tr32(MAC_LED_CTRL);
4979 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
4980
4981 if (tp->link_config.active_speed == SPEED_10)
4982 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
4983 else if (tp->link_config.active_speed == SPEED_100)
4984 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
4985 LED_CTRL_100MBPS_ON);
4986 else if (tp->link_config.active_speed == SPEED_1000)
4987 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
4988 LED_CTRL_1000MBPS_ON);
4989
4990 tw32(MAC_LED_CTRL, led_ctrl);
4991 udelay(40);
4992 }
4993
1da177e4
LT		 4994 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4995 if (tp->link_config.active_duplex == DUPLEX_HALF)
4996 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4997
4153577a 4998 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
953c96e0 4999 if (current_link_up &&
e8f3f6ca 5000 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 5001 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 5002 else
5003 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 5004 }
5005
5006 /* ??? Without this setting Netgear GA302T PHY does not
5007 * ??? send/receive packets...
5008 */
79eb6904 5009 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4153577a 5010 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
1da177e4
LT		 5011 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5012 tw32_f(MAC_MI_MODE, tp->mi_mode);
5013 udelay(80);
5014 }
5015
5016 tw32_f(MAC_MODE, tp->mac_mode);
5017 udelay(40);
5018
52b02d04
MC		 5019 tg3_phy_eee_adjust(tp, current_link_up);
5020
63c3a66f 5021 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 5022 /* Polled via timer. */
5023 tw32_f(MAC_EVENT, 0);
5024 } else {
5025 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5026 }
5027 udelay(40);
5028
4153577a 5029 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
953c96e0 5030 current_link_up &&
1da177e4 5031 tp->link_config.active_speed == SPEED_1000 &&
63c3a66f 5032 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
1da177e4
LT		 5033 udelay(120);
5034 tw32_f(MAC_STATUS,
5035 (MAC_STATUS_SYNC_CHANGED |
5036 MAC_STATUS_CFG_CHANGED));
5037 udelay(40);
5038 tg3_write_mem(tp,
5039 NIC_SRAM_FIRMWARE_MBOX,
5040 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5041 }
5042
5e7dfd0f 5043 /* Prevent send BD corruption. */
63c3a66f 5044 if (tg3_flag(tp, CLKREQ_BUG)) {
5e7dfd0f
MC		 5045 if (tp->link_config.active_speed == SPEED_100 ||
5046 tp->link_config.active_speed == SPEED_10)
0f49bfbd
JL		 5047 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5048 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 5049 else
0f49bfbd
JL		 5050 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5051 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f
MC		 5052 }
5053
f4a46d1f 5054 tg3_test_and_report_link_chg(tp, current_link_up);
1da177e4
LT		 5055
5056 return 0;
5057}
5058
5059struct tg3_fiber_aneginfo {
5060 int state;
5061#define ANEG_STATE_UNKNOWN 0
5062#define ANEG_STATE_AN_ENABLE 1
5063#define ANEG_STATE_RESTART_INIT 2
5064#define ANEG_STATE_RESTART 3
5065#define ANEG_STATE_DISABLE_LINK_OK 4
5066#define ANEG_STATE_ABILITY_DETECT_INIT 5
5067#define ANEG_STATE_ABILITY_DETECT 6
5068#define ANEG_STATE_ACK_DETECT_INIT 7
5069#define ANEG_STATE_ACK_DETECT 8
5070#define ANEG_STATE_COMPLETE_ACK_INIT 9
5071#define ANEG_STATE_COMPLETE_ACK 10
5072#define ANEG_STATE_IDLE_DETECT_INIT 11
5073#define ANEG_STATE_IDLE_DETECT 12
5074#define ANEG_STATE_LINK_OK 13
5075#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5076#define ANEG_STATE_NEXT_PAGE_WAIT 15
5077
5078 u32 flags;
5079#define MR_AN_ENABLE 0x00000001
5080#define MR_RESTART_AN 0x00000002
5081#define MR_AN_COMPLETE 0x00000004
5082#define MR_PAGE_RX 0x00000008
5083#define MR_NP_LOADED 0x00000010
5084#define MR_TOGGLE_TX 0x00000020
5085#define MR_LP_ADV_FULL_DUPLEX 0x00000040
5086#define MR_LP_ADV_HALF_DUPLEX 0x00000080
5087#define MR_LP_ADV_SYM_PAUSE 0x00000100
5088#define MR_LP_ADV_ASYM_PAUSE 0x00000200
5089#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5090#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5091#define MR_LP_ADV_NEXT_PAGE 0x00001000
5092#define MR_TOGGLE_RX 0x00002000
5093#define MR_NP_RX 0x00004000
5094
5095#define MR_LINK_OK 0x80000000
5096
5097 unsigned long link_time, cur_time;
5098
5099 u32 ability_match_cfg;
5100 int ability_match_count;
5101
5102 char ability_match, idle_match, ack_match;
5103
5104 u32 txconfig, rxconfig;
5105#define ANEG_CFG_NP 0x00000080
5106#define ANEG_CFG_ACK 0x00000040
5107#define ANEG_CFG_RF2 0x00000020
5108#define ANEG_CFG_RF1 0x00000010
5109#define ANEG_CFG_PS2 0x00000001
5110#define ANEG_CFG_PS1 0x00008000
5111#define ANEG_CFG_HD 0x00004000
5112#define ANEG_CFG_FD 0x00002000
5113#define ANEG_CFG_INVAL 0x00001f06
5114
5115};
5116#define ANEG_OK 0
5117#define ANEG_DONE 1
5118#define ANEG_TIMER_ENAB 2
5119#define ANEG_FAILED -1
5120
5121#define ANEG_STATE_SETTLE_TIME 10000
5122
5123static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5124 struct tg3_fiber_aneginfo *ap)
5125{
5be73b47 5126 u16 flowctrl;
1da177e4
LT		 5127 unsigned long delta;
5128 u32 rx_cfg_reg;
5129 int ret;
5130
5131 if (ap->state == ANEG_STATE_UNKNOWN) {
5132 ap->rxconfig = 0;
5133 ap->link_time = 0;
5134 ap->cur_time = 0;
5135 ap->ability_match_cfg = 0;
5136 ap->ability_match_count = 0;
5137 ap->ability_match = 0;
5138 ap->idle_match = 0;
5139 ap->ack_match = 0;
5140 }
5141 ap->cur_time++;
5142
5143 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5144 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5145
5146 if (rx_cfg_reg != ap->ability_match_cfg) {
5147 ap->ability_match_cfg = rx_cfg_reg;
5148 ap->ability_match = 0;
5149 ap->ability_match_count = 0;
5150 } else {
5151 if (++ap->ability_match_count > 1) {
5152 ap->ability_match = 1;
5153 ap->ability_match_cfg = rx_cfg_reg;
5154 }
5155 }
5156 if (rx_cfg_reg & ANEG_CFG_ACK)
5157 ap->ack_match = 1;
5158 else
5159 ap->ack_match = 0;
5160
5161 ap->idle_match = 0;
5162 } else {
5163 ap->idle_match = 1;
5164 ap->ability_match_cfg = 0;
5165 ap->ability_match_count = 0;
5166 ap->ability_match = 0;
5167 ap->ack_match = 0;
5168
5169 rx_cfg_reg = 0;
5170 }
5171
5172 ap->rxconfig = rx_cfg_reg;
5173 ret = ANEG_OK;
5174
33f401ae 5175 switch (ap->state) {
1da177e4
LT		 5176 case ANEG_STATE_UNKNOWN:
5177 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5178 ap->state = ANEG_STATE_AN_ENABLE;
5179
5180 /* fallthru */
5181 case ANEG_STATE_AN_ENABLE:
5182 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5183 if (ap->flags & MR_AN_ENABLE) {
5184 ap->link_time = 0;
5185 ap->cur_time = 0;
5186 ap->ability_match_cfg = 0;
5187 ap->ability_match_count = 0;
5188 ap->ability_match = 0;
5189 ap->idle_match = 0;
5190 ap->ack_match = 0;
5191
5192 ap->state = ANEG_STATE_RESTART_INIT;
5193 } else {
5194 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5195 }
5196 break;
5197
5198 case ANEG_STATE_RESTART_INIT:
5199 ap->link_time = ap->cur_time;
5200 ap->flags &= ~(MR_NP_LOADED);
5201 ap->txconfig = 0;
5202 tw32(MAC_TX_AUTO_NEG, 0);
5203 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5204 tw32_f(MAC_MODE, tp->mac_mode);
5205 udelay(40);
5206
5207 ret = ANEG_TIMER_ENAB;
5208 ap->state = ANEG_STATE_RESTART;
5209
5210 /* fallthru */
5211 case ANEG_STATE_RESTART:
5212 delta = ap->cur_time - ap->link_time;
859a5887 5213 if (delta > ANEG_STATE_SETTLE_TIME)
1da177e4 5214 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
859a5887 5215 else
1da177e4 5216 ret = ANEG_TIMER_ENAB;
1da177e4
LT		 5217 break;
5218
5219 case ANEG_STATE_DISABLE_LINK_OK:
5220 ret = ANEG_DONE;
5221 break;
5222
5223 case ANEG_STATE_ABILITY_DETECT_INIT:
5224 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 5225 ap->txconfig = ANEG_CFG_FD;
5226 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5227 if (flowctrl & ADVERTISE_1000XPAUSE)
5228 ap->txconfig |= ANEG_CFG_PS1;
5229 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5230 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 5231 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5232 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5233 tw32_f(MAC_MODE, tp->mac_mode);
5234 udelay(40);
5235
5236 ap->state = ANEG_STATE_ABILITY_DETECT;
5237 break;
5238
5239 case ANEG_STATE_ABILITY_DETECT:
859a5887 5240 if (ap->ability_match != 0 && ap->rxconfig != 0)
1da177e4 5241 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1da177e4
LT		 5242 break;
5243
5244 case ANEG_STATE_ACK_DETECT_INIT:
5245 ap->txconfig |= ANEG_CFG_ACK;
5246 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5247 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5248 tw32_f(MAC_MODE, tp->mac_mode);
5249 udelay(40);
5250
5251 ap->state = ANEG_STATE_ACK_DETECT;
5252
5253 /* fallthru */
5254 case ANEG_STATE_ACK_DETECT:
5255 if (ap->ack_match != 0) {
5256 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5257 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5258 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5259 } else {
5260 ap->state = ANEG_STATE_AN_ENABLE;
5261 }
5262 } else if (ap->ability_match != 0 &&
5263 ap->rxconfig == 0) {
5264 ap->state = ANEG_STATE_AN_ENABLE;
5265 }
5266 break;
5267
5268 case ANEG_STATE_COMPLETE_ACK_INIT:
5269 if (ap->rxconfig & ANEG_CFG_INVAL) {
5270 ret = ANEG_FAILED;
5271 break;
5272 }
5273 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5274 MR_LP_ADV_HALF_DUPLEX |
5275 MR_LP_ADV_SYM_PAUSE |
5276 MR_LP_ADV_ASYM_PAUSE |
5277 MR_LP_ADV_REMOTE_FAULT1 |
5278 MR_LP_ADV_REMOTE_FAULT2 |
5279 MR_LP_ADV_NEXT_PAGE |
5280 MR_TOGGLE_RX |
5281 MR_NP_RX);
5282 if (ap->rxconfig & ANEG_CFG_FD)
5283 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5284 if (ap->rxconfig & ANEG_CFG_HD)
5285 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5286 if (ap->rxconfig & ANEG_CFG_PS1)
5287 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5288 if (ap->rxconfig & ANEG_CFG_PS2)
5289 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5290 if (ap->rxconfig & ANEG_CFG_RF1)
5291 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5292 if (ap->rxconfig & ANEG_CFG_RF2)
5293 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5294 if (ap->rxconfig & ANEG_CFG_NP)
5295 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5296
5297 ap->link_time = ap->cur_time;
5298
5299 ap->flags ^= (MR_TOGGLE_TX);
5300 if (ap->rxconfig & 0x0008)
5301 ap->flags |= MR_TOGGLE_RX;
5302 if (ap->rxconfig & ANEG_CFG_NP)
5303 ap->flags |= MR_NP_RX;
5304 ap->flags |= MR_PAGE_RX;
5305
5306 ap->state = ANEG_STATE_COMPLETE_ACK;
5307 ret = ANEG_TIMER_ENAB;
5308 break;
5309
5310 case ANEG_STATE_COMPLETE_ACK:
5311 if (ap->ability_match != 0 &&
5312 ap->rxconfig == 0) {
5313 ap->state = ANEG_STATE_AN_ENABLE;
5314 break;
5315 }
5316 delta = ap->cur_time - ap->link_time;
5317 if (delta > ANEG_STATE_SETTLE_TIME) {
5318 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5319 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5320 } else {
5321 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5322 !(ap->flags & MR_NP_RX)) {
5323 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5324 } else {
5325 ret = ANEG_FAILED;
5326 }
5327 }
5328 }
5329 break;
5330
5331 case ANEG_STATE_IDLE_DETECT_INIT:
5332 ap->link_time = ap->cur_time;
5333 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5334 tw32_f(MAC_MODE, tp->mac_mode);
5335 udelay(40);
5336
5337 ap->state = ANEG_STATE_IDLE_DETECT;
5338 ret = ANEG_TIMER_ENAB;
5339 break;
5340
5341 case ANEG_STATE_IDLE_DETECT:
5342 if (ap->ability_match != 0 &&
5343 ap->rxconfig == 0) {
5344 ap->state = ANEG_STATE_AN_ENABLE;
5345 break;
5346 }
5347 delta = ap->cur_time - ap->link_time;
5348 if (delta > ANEG_STATE_SETTLE_TIME) {
5349 /* XXX another gem from the Broadcom driver :( */
5350 ap->state = ANEG_STATE_LINK_OK;
5351 }
5352 break;
5353
5354 case ANEG_STATE_LINK_OK:
5355 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5356 ret = ANEG_DONE;
5357 break;
5358
5359 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5360 /* ??? unimplemented */
5361 break;
5362
5363 case ANEG_STATE_NEXT_PAGE_WAIT:
5364 /* ??? unimplemented */
5365 break;
5366
5367 default:
5368 ret = ANEG_FAILED;
5369 break;
855e1111 5370 }
1da177e4
LT		 5371
5372 return ret;
5373}
5374
5be73b47 5375static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 5376{
5377 int res = 0;
5378 struct tg3_fiber_aneginfo aninfo;
5379 int status = ANEG_FAILED;
5380 unsigned int tick;
5381 u32 tmp;
5382
5383 tw32_f(MAC_TX_AUTO_NEG, 0);
5384
5385 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5386 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5387 udelay(40);
5388
5389 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5390 udelay(40);
5391
5392 memset(&aninfo, 0, sizeof(aninfo));
5393 aninfo.flags |= MR_AN_ENABLE;
5394 aninfo.state = ANEG_STATE_UNKNOWN;
5395 aninfo.cur_time = 0;
5396 tick = 0;
5397 while (++tick < 195000) {
5398 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5399 if (status == ANEG_DONE || status == ANEG_FAILED)
5400 break;
5401
5402 udelay(1);
5403 }
5404
5405 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5406 tw32_f(MAC_MODE, tp->mac_mode);
5407 udelay(40);
5408
5be73b47
MC		 5409 *txflags = aninfo.txconfig;
5410 *rxflags = aninfo.flags;
1da177e4
LT		 5411
5412 if (status == ANEG_DONE &&
5413 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5414 MR_LP_ADV_FULL_DUPLEX)))
5415 res = 1;
5416
5417 return res;
5418}
5419
5420static void tg3_init_bcm8002(struct tg3 *tp)
5421{
5422 u32 mac_status = tr32(MAC_STATUS);
5423 int i;
5424
5425 /* Reset when initting first time or we have a link. */
63c3a66f 5426 if (tg3_flag(tp, INIT_COMPLETE) &&
1da177e4
LT		 5427 !(mac_status & MAC_STATUS_PCS_SYNCED))
5428 return;
5429
5430 /* Set PLL lock range. */
5431 tg3_writephy(tp, 0x16, 0x8007);
5432
5433 /* SW reset */
5434 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5435
5436 /* Wait for reset to complete. */
5437 /* XXX schedule_timeout() ... */
5438 for (i = 0; i < 500; i++)
5439 udelay(10);
5440
5441 /* Config mode; select PMA/Ch 1 regs. */
5442 tg3_writephy(tp, 0x10, 0x8411);
5443
5444 /* Enable auto-lock and comdet, select txclk for tx. */
5445 tg3_writephy(tp, 0x11, 0x0a10);
5446
5447 tg3_writephy(tp, 0x18, 0x00a0);
5448 tg3_writephy(tp, 0x16, 0x41ff);
5449
5450 /* Assert and deassert POR. */
5451 tg3_writephy(tp, 0x13, 0x0400);
5452 udelay(40);
5453 tg3_writephy(tp, 0x13, 0x0000);
5454
5455 tg3_writephy(tp, 0x11, 0x0a50);
5456 udelay(40);
5457 tg3_writephy(tp, 0x11, 0x0a10);
5458
5459 /* Wait for signal to stabilize */
5460 /* XXX schedule_timeout() ... */
5461 for (i = 0; i < 15000; i++)
5462 udelay(10);
5463
5464 /* Deselect the channel register so we can read the PHYID
5465 * later.
5466 */
5467 tg3_writephy(tp, 0x10, 0x8011);
5468}
5469
953c96e0 5470static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
1da177e4 5471{
82cd3d11 5472 u16 flowctrl;
953c96e0 5473 bool current_link_up;
1da177e4
LT		 5474 u32 sg_dig_ctrl, sg_dig_status;
5475 u32 serdes_cfg, expected_sg_dig_ctrl;
5476 int workaround, port_a;
1da177e4
LT		 5477
5478 serdes_cfg = 0;
5479 expected_sg_dig_ctrl = 0;
5480 workaround = 0;
5481 port_a = 1;
953c96e0 5482 current_link_up = false;
1da177e4 5483
4153577a
JP		 5484 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5485 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
1da177e4
LT		 5486 workaround = 1;
5487 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5488 port_a = 0;
5489
5490 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5491 /* preserve bits 20-23 for voltage regulator */
5492 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5493 }
5494
5495 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5496
5497 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 5498 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 5499 if (workaround) {
5500 u32 val = serdes_cfg;
5501
5502 if (port_a)
5503 val |= 0xc010000;
5504 else
5505 val |= 0x4010000;
5506 tw32_f(MAC_SERDES_CFG, val);
5507 }
c98f6e3b
MC		 5508
5509 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5510 }
5511 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5512 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5513 current_link_up = true;
1da177e4
LT		 5514 }
5515 goto out;
5516 }
5517
5518 /* Want auto-negotiation. */
c98f6e3b 5519 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 5520
82cd3d11
MC		 5521 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5522 if (flowctrl & ADVERTISE_1000XPAUSE)
5523 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5524 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5525 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 5526
5527 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
f07e9af3 5528 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3d3ebe74
MC		 5529 tp->serdes_counter &&
5530 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5531 MAC_STATUS_RCVD_CFG)) ==
5532 MAC_STATUS_PCS_SYNCED)) {
5533 tp->serdes_counter--;
953c96e0 5534 current_link_up = true;
3d3ebe74
MC		 5535 goto out;
5536 }
5537restart_autoneg:
1da177e4
LT		 5538 if (workaround)
5539 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 5540 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 5541 udelay(5);
5542 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5543
3d3ebe74 5544 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5545 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5546 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5547 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 5548 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 5549 mac_status = tr32(MAC_STATUS);
5550
c98f6e3b 5551 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 5552 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 5553 u32 local_adv = 0, remote_adv = 0;
5554
5555 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5556 local_adv |= ADVERTISE_1000XPAUSE;
5557 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5558 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 5559
c98f6e3b 5560 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 5561 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 5562 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 5563 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5564
859edb26
MC		 5565 tp->link_config.rmt_adv =
5566 mii_adv_to_ethtool_adv_x(remote_adv);
5567
1da177e4 5568 tg3_setup_flow_control(tp, local_adv, remote_adv);
953c96e0 5569 current_link_up = true;
3d3ebe74 5570 tp->serdes_counter = 0;
f07e9af3 5571 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c98f6e3b 5572 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 5573 if (tp->serdes_counter)
5574 tp->serdes_counter--;
1da177e4
LT		 5575 else {
5576 if (workaround) {
5577 u32 val = serdes_cfg;
5578
5579 if (port_a)
5580 val |= 0xc010000;
5581 else
5582 val |= 0x4010000;
5583
5584 tw32_f(MAC_SERDES_CFG, val);
5585 }
5586
c98f6e3b 5587 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5588 udelay(40);
5589
5590 /* Link parallel detection - link is up */
5591 /* only if we have PCS_SYNC and not */
5592 /* receiving config code words */
5593 mac_status = tr32(MAC_STATUS);
5594 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5595 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5596 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5597 current_link_up = true;
f07e9af3
MC		 5598 tp->phy_flags |=
5599 TG3_PHYFLG_PARALLEL_DETECT;
3d3ebe74
MC		 5600 tp->serdes_counter =
5601 SERDES_PARALLEL_DET_TIMEOUT;
5602 } else
5603 goto restart_autoneg;
1da177e4
LT		 5604 }
5605 }
3d3ebe74
MC		 5606 } else {
5607 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5608 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5609 }
5610
5611out:
5612 return current_link_up;
5613}
5614
953c96e0 5615static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
1da177e4 5616{
953c96e0 5617 bool current_link_up = false;
1da177e4 5618
5cf64b8a 5619 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 5620 goto out;
1da177e4
LT		 5621
5622 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 5623 u32 txflags, rxflags;
1da177e4 5624 int i;
6aa20a22 5625
5be73b47
MC		 5626 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5627 u32 local_adv = 0, remote_adv = 0;
1da177e4 5628
5be73b47
MC		 5629 if (txflags & ANEG_CFG_PS1)
5630 local_adv |= ADVERTISE_1000XPAUSE;
5631 if (txflags & ANEG_CFG_PS2)
5632 local_adv |= ADVERTISE_1000XPSE_ASYM;
5633
5634 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5635 remote_adv |= LPA_1000XPAUSE;
5636 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5637 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5638
859edb26
MC		 5639 tp->link_config.rmt_adv =
5640 mii_adv_to_ethtool_adv_x(remote_adv);
5641
1da177e4
LT		 5642 tg3_setup_flow_control(tp, local_adv, remote_adv);
5643
953c96e0 5644 current_link_up = true;
1da177e4
LT		 5645 }
5646 for (i = 0; i < 30; i++) {
5647 udelay(20);
5648 tw32_f(MAC_STATUS,
5649 (MAC_STATUS_SYNC_CHANGED |
5650 MAC_STATUS_CFG_CHANGED));
5651 udelay(40);
5652 if ((tr32(MAC_STATUS) &
5653 (MAC_STATUS_SYNC_CHANGED |
5654 MAC_STATUS_CFG_CHANGED)) == 0)
5655 break;
5656 }
5657
5658 mac_status = tr32(MAC_STATUS);
953c96e0 5659 if (!current_link_up &&
1da177e4
LT		 5660 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5661 !(mac_status & MAC_STATUS_RCVD_CFG))
953c96e0 5662 current_link_up = true;
1da177e4 5663 } else {
5be73b47
MC		 5664 tg3_setup_flow_control(tp, 0, 0);
5665
1da177e4 5666 /* Forcing 1000FD link up. */
953c96e0 5667 current_link_up = true;
1da177e4
LT		 5668
5669 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5670 udelay(40);
e8f3f6ca
MC		 5671
5672 tw32_f(MAC_MODE, tp->mac_mode);
5673 udelay(40);
1da177e4
LT		 5674 }
5675
5676out:
5677 return current_link_up;
5678}
5679
953c96e0 5680static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
1da177e4
LT		 5681{
5682 u32 orig_pause_cfg;
5683 u16 orig_active_speed;
5684 u8 orig_active_duplex;
5685 u32 mac_status;
953c96e0 5686 bool current_link_up;
1da177e4
LT		 5687 int i;
5688
8d018621 5689 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5690 orig_active_speed = tp->link_config.active_speed;
5691 orig_active_duplex = tp->link_config.active_duplex;
5692
63c3a66f 5693 if (!tg3_flag(tp, HW_AUTONEG) &&
f4a46d1f 5694 tp->link_up &&
63c3a66f 5695 tg3_flag(tp, INIT_COMPLETE)) {
1da177e4
LT		 5696 mac_status = tr32(MAC_STATUS);
5697 mac_status &= (MAC_STATUS_PCS_SYNCED |
5698 MAC_STATUS_SIGNAL_DET |
5699 MAC_STATUS_CFG_CHANGED |
5700 MAC_STATUS_RCVD_CFG);
5701 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5702 MAC_STATUS_SIGNAL_DET)) {
5703 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5704 MAC_STATUS_CFG_CHANGED));
5705 return 0;
5706 }
5707 }
5708
5709 tw32_f(MAC_TX_AUTO_NEG, 0);
5710
5711 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5712 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5713 tw32_f(MAC_MODE, tp->mac_mode);
5714 udelay(40);
5715
79eb6904 5716 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 5717 tg3_init_bcm8002(tp);
5718
5719 /* Enable link change event even when serdes polling. */
5720 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5721 udelay(40);
5722
953c96e0 5723 current_link_up = false;
859edb26 5724 tp->link_config.rmt_adv = 0;
1da177e4
LT		 5725 mac_status = tr32(MAC_STATUS);
5726
63c3a66f 5727 if (tg3_flag(tp, HW_AUTONEG))
1da177e4
LT		 5728 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5729 else
5730 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5731
898a56f8 5732 tp->napi[0].hw_status->status =
1da177e4 5733 (SD_STATUS_UPDATED |
898a56f8 5734 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 5735
5736 for (i = 0; i < 100; i++) {
5737 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5738 MAC_STATUS_CFG_CHANGED));
5739 udelay(5);
5740 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 5741 MAC_STATUS_CFG_CHANGED |
5742 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 5743 break;
5744 }
5745
5746 mac_status = tr32(MAC_STATUS);
5747 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
953c96e0 5748 current_link_up = false;
3d3ebe74
MC		 5749 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5750 tp->serdes_counter == 0) {
1da177e4
LT		 5751 tw32_f(MAC_MODE, (tp->mac_mode |
5752 MAC_MODE_SEND_CONFIGS));
5753 udelay(1);
5754 tw32_f(MAC_MODE, tp->mac_mode);
5755 }
5756 }
5757
953c96e0 5758 if (current_link_up) {
1da177e4
LT		 5759 tp->link_config.active_speed = SPEED_1000;
5760 tp->link_config.active_duplex = DUPLEX_FULL;
5761 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5762 LED_CTRL_LNKLED_OVERRIDE |
5763 LED_CTRL_1000MBPS_ON));
5764 } else {
e740522e
MC		 5765 tp->link_config.active_speed = SPEED_UNKNOWN;
5766 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 5767 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5768 LED_CTRL_LNKLED_OVERRIDE |
5769 LED_CTRL_TRAFFIC_OVERRIDE));
5770 }
5771
f4a46d1f 5772 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
8d018621 5773 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5774 if (orig_pause_cfg != now_pause_cfg ||
5775 orig_active_speed != tp->link_config.active_speed ||
5776 orig_active_duplex != tp->link_config.active_duplex)
5777 tg3_link_report(tp);
5778 }
5779
5780 return 0;
5781}
5782
953c96e0 5783static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
747e8f8b 5784{
953c96e0 5785 int err = 0;
747e8f8b 5786 u32 bmsr, bmcr;
85730a63
MC		 5787 u16 current_speed = SPEED_UNKNOWN;
5788 u8 current_duplex = DUPLEX_UNKNOWN;
953c96e0 5789 bool current_link_up = false;
85730a63
MC		 5790 u32 local_adv, remote_adv, sgsr;
5791
5792 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5793 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5794 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5795 (sgsr & SERDES_TG3_SGMII_MODE)) {
5796
5797 if (force_reset)
5798 tg3_phy_reset(tp);
5799
5800 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5801
5802 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5803 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5804 } else {
953c96e0 5805 current_link_up = true;
85730a63
MC		 5806 if (sgsr & SERDES_TG3_SPEED_1000) {
5807 current_speed = SPEED_1000;
5808 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5809 } else if (sgsr & SERDES_TG3_SPEED_100) {
5810 current_speed = SPEED_100;
5811 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5812 } else {
5813 current_speed = SPEED_10;
5814 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5815 }
5816
5817 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5818 current_duplex = DUPLEX_FULL;
5819 else
5820 current_duplex = DUPLEX_HALF;
5821 }
5822
5823 tw32_f(MAC_MODE, tp->mac_mode);
5824 udelay(40);
5825
5826 tg3_clear_mac_status(tp);
5827
5828 goto fiber_setup_done;
5829 }
747e8f8b
MC		 5830
5831 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5832 tw32_f(MAC_MODE, tp->mac_mode);
5833 udelay(40);
5834
3310e248 5835 tg3_clear_mac_status(tp);
747e8f8b
MC		 5836
5837 if (force_reset)
5838 tg3_phy_reset(tp);
5839
859edb26 5840 tp->link_config.rmt_adv = 0;
747e8f8b
MC		 5841
5842 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5843 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5844 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5845 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5846 bmsr |= BMSR_LSTATUS;
5847 else
5848 bmsr &= ~BMSR_LSTATUS;
5849 }
747e8f8b
MC		 5850
5851 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5852
5853 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
f07e9af3 5854 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 5855 /* do nothing, just check for link up at the end */
5856 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
28011cf1 5857 u32 adv, newadv;
747e8f8b
MC		 5858
5859 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
28011cf1
MC		 5860 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5861 ADVERTISE_1000XPAUSE |
5862 ADVERTISE_1000XPSE_ASYM |
5863 ADVERTISE_SLCT);
747e8f8b 5864
28011cf1 5865 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
37f07023 5866 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
747e8f8b 5867
28011cf1
MC		 5868 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5869 tg3_writephy(tp, MII_ADVERTISE, newadv);
747e8f8b
MC		 5870 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5871 tg3_writephy(tp, MII_BMCR, bmcr);
5872
5873 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 5874 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
f07e9af3 5875 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5876
5877 return err;
5878 }
5879 } else {
5880 u32 new_bmcr;
5881
5882 bmcr &= ~BMCR_SPEED1000;
5883 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5884
5885 if (tp->link_config.duplex == DUPLEX_FULL)
5886 new_bmcr |= BMCR_FULLDPLX;
5887
5888 if (new_bmcr != bmcr) {
5889 /* BMCR_SPEED1000 is a reserved bit that needs
5890 * to be set on write.
5891 */
5892 new_bmcr |= BMCR_SPEED1000;
5893
5894 /* Force a linkdown */
f4a46d1f 5895 if (tp->link_up) {
747e8f8b
MC		 5896 u32 adv;
5897
5898 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5899 adv &= ~(ADVERTISE_1000XFULL |
5900 ADVERTISE_1000XHALF |
5901 ADVERTISE_SLCT);
5902 tg3_writephy(tp, MII_ADVERTISE, adv);
5903 tg3_writephy(tp, MII_BMCR, bmcr |
5904 BMCR_ANRESTART |
5905 BMCR_ANENABLE);
5906 udelay(10);
f4a46d1f 5907 tg3_carrier_off(tp);
747e8f8b
MC		 5908 }
5909 tg3_writephy(tp, MII_BMCR, new_bmcr);
5910 bmcr = new_bmcr;
5911 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5912 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5913 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5914 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5915 bmsr |= BMSR_LSTATUS;
5916 else
5917 bmsr &= ~BMSR_LSTATUS;
5918 }
f07e9af3 5919 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5920 }
5921 }
5922
5923 if (bmsr & BMSR_LSTATUS) {
5924 current_speed = SPEED_1000;
953c96e0 5925 current_link_up = true;
747e8f8b
MC		 5926 if (bmcr & BMCR_FULLDPLX)
5927 current_duplex = DUPLEX_FULL;
5928 else
5929 current_duplex = DUPLEX_HALF;
5930
ef167e27
MC		 5931 local_adv = 0;
5932 remote_adv = 0;
5933
747e8f8b 5934 if (bmcr & BMCR_ANENABLE) {
ef167e27 5935 u32 common;
747e8f8b
MC		 5936
5937 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5938 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5939 common = local_adv & remote_adv;
5940 if (common & (ADVERTISE_1000XHALF |
5941 ADVERTISE_1000XFULL)) {
5942 if (common & ADVERTISE_1000XFULL)
5943 current_duplex = DUPLEX_FULL;
5944 else
5945 current_duplex = DUPLEX_HALF;
859edb26
MC		 5946
5947 tp->link_config.rmt_adv =
5948 mii_adv_to_ethtool_adv_x(remote_adv);
63c3a66f 5949 } else if (!tg3_flag(tp, 5780_CLASS)) {
57d8b880 5950 /* Link is up via parallel detect */
859a5887 5951 } else {
953c96e0 5952 current_link_up = false;
859a5887 5953 }
747e8f8b
MC		 5954 }
5955 }
5956
85730a63 5957fiber_setup_done:
953c96e0 5958 if (current_link_up && current_duplex == DUPLEX_FULL)
ef167e27
MC		 5959 tg3_setup_flow_control(tp, local_adv, remote_adv);
5960
747e8f8b
MC		 5961 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5962 if (tp->link_config.active_duplex == DUPLEX_HALF)
5963 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5964
5965 tw32_f(MAC_MODE, tp->mac_mode);
5966 udelay(40);
5967
5968 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5969
5970 tp->link_config.active_speed = current_speed;
5971 tp->link_config.active_duplex = current_duplex;
5972
f4a46d1f 5973 tg3_test_and_report_link_chg(tp, current_link_up);
747e8f8b
MC		 5974 return err;
5975}
5976
5977static void tg3_serdes_parallel_detect(struct tg3 *tp)
5978{
3d3ebe74 5979 if (tp->serdes_counter) {
747e8f8b 5980 /* Give autoneg time to complete. */
3d3ebe74 5981 tp->serdes_counter--;
747e8f8b
MC		 5982 return;
5983 }
c6cdf436 5984
f4a46d1f 5985 if (!tp->link_up &&
747e8f8b
MC		 5986 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5987 u32 bmcr;
5988
5989 tg3_readphy(tp, MII_BMCR, &bmcr);
5990 if (bmcr & BMCR_ANENABLE) {
5991 u32 phy1, phy2;
5992
5993 /* Select shadow register 0x1f */
f08aa1a8
MC		 5994 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5995 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
747e8f8b
MC		 5996
5997 /* Select expansion interrupt status register */
f08aa1a8
MC		 5998 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5999 MII_TG3_DSP_EXP1_INT_STAT);
6000 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6001 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6002
6003 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6004 /* We have signal detect and not receiving
6005 * config code words, link is up by parallel
6006 * detection.
6007 */
6008
6009 bmcr &= ~BMCR_ANENABLE;
6010 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6011 tg3_writephy(tp, MII_BMCR, bmcr);
f07e9af3 6012 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6013 }
6014 }
f4a46d1f 6015 } else if (tp->link_up &&
859a5887 6016 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
f07e9af3 6017 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 6018 u32 phy2;
6019
6020 /* Select expansion interrupt status register */
f08aa1a8
MC		 6021 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6022 MII_TG3_DSP_EXP1_INT_STAT);
6023 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6024 if (phy2 & 0x20) {
6025 u32 bmcr;
6026
6027 /* Config code words received, turn on autoneg. */
6028 tg3_readphy(tp, MII_BMCR, &bmcr);
6029 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6030
f07e9af3 6031 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6032
6033 }
6034 }
6035}
6036
953c96e0 6037static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
1da177e4 6038{
f2096f94 6039 u32 val;
1da177e4
LT		 6040 int err;
6041
f07e9af3 6042 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4 6043 err = tg3_setup_fiber_phy(tp, force_reset);
f07e9af3 6044 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
747e8f8b 6045 err = tg3_setup_fiber_mii_phy(tp, force_reset);
859a5887 6046 else
1da177e4 6047 err = tg3_setup_copper_phy(tp, force_reset);
1da177e4 6048
4153577a 6049 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
f2096f94 6050 u32 scale;
aa6c91fe
MC		 6051
6052 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6053 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6054 scale = 65;
6055 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6056 scale = 6;
6057 else
6058 scale = 12;
6059
6060 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6061 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6062 tw32(GRC_MISC_CFG, val);
6063 }
6064
f2096f94
MC		 6065 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6066 (6 << TX_LENGTHS_IPG_SHIFT);
4153577a
JP		 6067 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6068 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 6069 val |= tr32(MAC_TX_LENGTHS) &
6070 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6071 TX_LENGTHS_CNT_DWN_VAL_MSK);
6072
1da177e4
LT		 6073 if (tp->link_config.active_speed == SPEED_1000 &&
6074 tp->link_config.active_duplex == DUPLEX_HALF)
f2096f94
MC		 6075 tw32(MAC_TX_LENGTHS, val |
6076 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6077 else
f2096f94
MC		 6078 tw32(MAC_TX_LENGTHS, val |
6079 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6080
63c3a66f 6081 if (!tg3_flag(tp, 5705_PLUS)) {
f4a46d1f 6082 if (tp->link_up) {
1da177e4 6083 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 6084 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 6085 } else {
6086 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6087 }
6088 }
6089
63c3a66f 6090 if (tg3_flag(tp, ASPM_WORKAROUND)) {
f2096f94 6091 val = tr32(PCIE_PWR_MGMT_THRESH);
f4a46d1f 6092 if (!tp->link_up)
8ed5d97e
MC		 6093 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6094 tp->pwrmgmt_thresh;
6095 else
6096 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6097 tw32(PCIE_PWR_MGMT_THRESH, val);
6098 }
6099
1da177e4
LT		 6100 return err;
6101}
6102
7d41e49a
MC		 6103/* tp->lock must be held */
6104static u64 tg3_refclk_read(struct tg3 *tp)
6105{
6106 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6107 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6108}
6109
be947307
MC		 6110/* tp->lock must be held */
6111static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6112{
92e6457d
NS		 6113 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6114
6115 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
be947307
MC		 6116 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6117 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
92e6457d 6118 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
be947307
MC		 6119}
6120
7d41e49a
MC		 6121static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6122static inline void tg3_full_unlock(struct tg3 *tp);
6123static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6124{
6125 struct tg3 *tp = netdev_priv(dev);
6126
6127 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6128 SOF_TIMESTAMPING_RX_SOFTWARE |
f233a976
FL		 6129 SOF_TIMESTAMPING_SOFTWARE;
6130
6131 if (tg3_flag(tp, PTP_CAPABLE)) {
32e19272 6132 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
f233a976
FL		 6133 SOF_TIMESTAMPING_RX_HARDWARE |
6134 SOF_TIMESTAMPING_RAW_HARDWARE;
6135 }
7d41e49a
MC		 6136
6137 if (tp->ptp_clock)
6138 info->phc_index = ptp_clock_index(tp->ptp_clock);
6139 else
6140 info->phc_index = -1;
6141
6142 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6143
6144 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6145 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6146 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6147 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6148 return 0;
6149}
6150
6151static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6152{
6153 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6154 bool neg_adj = false;
6155 u32 correction = 0;
6156
6157 if (ppb < 0) {
6158 neg_adj = true;
6159 ppb = -ppb;
6160 }
6161
6162 /* Frequency adjustment is performed using hardware with a 24 bit
6163 * accumulator and a programmable correction value. On each clk, the
6164 * correction value gets added to the accumulator and when it
6165 * overflows, the time counter is incremented/decremented.
6166 *
6167 * So conversion from ppb to correction value is
6168 * ppb * (1 << 24) / 1000000000
6169 */
6170 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6171 TG3_EAV_REF_CLK_CORRECT_MASK;
6172
6173 tg3_full_lock(tp, 0);
6174
6175 if (correction)
6176 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6177 TG3_EAV_REF_CLK_CORRECT_EN |
6178 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6179 else
6180 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6181
6182 tg3_full_unlock(tp);
6183
6184 return 0;
6185}
6186
6187static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6188{
6189 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6190
6191 tg3_full_lock(tp, 0);
6192 tp->ptp_adjust += delta;
6193 tg3_full_unlock(tp);
6194
6195 return 0;
6196}
6197
6198static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6199{
6200 u64 ns;
6201 u32 remainder;
6202 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6203
6204 tg3_full_lock(tp, 0);
6205 ns = tg3_refclk_read(tp);
6206 ns += tp->ptp_adjust;
6207 tg3_full_unlock(tp);
6208
6209 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6210 ts->tv_nsec = remainder;
6211
6212 return 0;
6213}
6214
6215static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6216 const struct timespec *ts)
6217{
6218 u64 ns;
6219 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6220
6221 ns = timespec_to_ns(ts);
6222
6223 tg3_full_lock(tp, 0);
6224 tg3_refclk_write(tp, ns);
6225 tp->ptp_adjust = 0;
6226 tg3_full_unlock(tp);
6227
6228 return 0;
6229}
6230
6231static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6232 struct ptp_clock_request *rq, int on)
6233{
92e6457d
NS		 6234 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6235 u32 clock_ctl;
6236 int rval = 0;
6237
6238 switch (rq->type) {
6239 case PTP_CLK_REQ_PEROUT:
6240 if (rq->perout.index != 0)
6241 return -EINVAL;
6242
6243 tg3_full_lock(tp, 0);
6244 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6245 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6246
6247 if (on) {
6248 u64 nsec;
6249
6250 nsec = rq->perout.start.sec * 1000000000ULL +
6251 rq->perout.start.nsec;
6252
6253 if (rq->perout.period.sec || rq->perout.period.nsec) {
6254 netdev_warn(tp->dev,
6255 "Device supports only a one-shot timesync output, period must be 0\n");
6256 rval = -EINVAL;
6257 goto err_out;
6258 }
6259
6260 if (nsec & (1ULL << 63)) {
6261 netdev_warn(tp->dev,
6262 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6263 rval = -EINVAL;
6264 goto err_out;
6265 }
6266
6267 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6268 tw32(TG3_EAV_WATCHDOG0_MSB,
6269 TG3_EAV_WATCHDOG0_EN |
6270 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6271
6272 tw32(TG3_EAV_REF_CLCK_CTL,
6273 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6274 } else {
6275 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6276 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6277 }
6278
6279err_out:
6280 tg3_full_unlock(tp);
6281 return rval;
6282
6283 default:
6284 break;
6285 }
6286
7d41e49a
MC		 6287 return -EOPNOTSUPP;
6288}
6289
6290static const struct ptp_clock_info tg3_ptp_caps = {
6291 .owner = THIS_MODULE,
6292 .name = "tg3 clock",
6293 .max_adj = 250000000,
6294 .n_alarm = 0,
6295 .n_ext_ts = 0,
92e6457d 6296 .n_per_out = 1,
7d41e49a
MC		 6297 .pps = 0,
6298 .adjfreq = tg3_ptp_adjfreq,
6299 .adjtime = tg3_ptp_adjtime,
6300 .gettime = tg3_ptp_gettime,
6301 .settime = tg3_ptp_settime,
6302 .enable = tg3_ptp_enable,
6303};
6304
fb4ce8ad
MC		 6305static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6306 struct skb_shared_hwtstamps *timestamp)
6307{
6308 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6309 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6310 tp->ptp_adjust);
6311}
6312
be947307
MC		 6313/* tp->lock must be held */
6314static void tg3_ptp_init(struct tg3 *tp)
6315{
6316 if (!tg3_flag(tp, PTP_CAPABLE))
6317 return;
6318
6319 /* Initialize the hardware clock to the system time. */
6320 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6321 tp->ptp_adjust = 0;
7d41e49a 6322 tp->ptp_info = tg3_ptp_caps;
be947307
MC		 6323}
6324
6325/* tp->lock must be held */
6326static void tg3_ptp_resume(struct tg3 *tp)
6327{
6328 if (!tg3_flag(tp, PTP_CAPABLE))
6329 return;
6330
6331 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6332 tp->ptp_adjust = 0;
6333}
6334
6335static void tg3_ptp_fini(struct tg3 *tp)
6336{
6337 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6338 return;
6339
7d41e49a 6340 ptp_clock_unregister(tp->ptp_clock);
be947307
MC		 6341 tp->ptp_clock = NULL;
6342 tp->ptp_adjust = 0;
6343}
6344
66cfd1bd
MC		 6345static inline int tg3_irq_sync(struct tg3 *tp)
6346{
6347 return tp->irq_sync;
6348}
6349
97bd8e49
MC		 6350static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6351{
6352 int i;
6353
6354 dst = (u32 *)((u8 *)dst + off);
6355 for (i = 0; i < len; i += sizeof(u32))
6356 *dst++ = tr32(off + i);
6357}
6358
6359static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6360{
6361 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6362 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6363 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6364 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6365 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6366 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6367 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6368 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6369 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6370 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6371 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6372 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6373 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6374 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6375 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6376 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6377 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6378 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6379 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6380
63c3a66f 6381 if (tg3_flag(tp, SUPPORT_MSIX))
97bd8e49
MC		 6382 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6383
6384 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6385 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6386 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6387 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6388 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6389 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6390 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6391 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6392
63c3a66f 6393 if (!tg3_flag(tp, 5705_PLUS)) {
97bd8e49
MC		 6394 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6395 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6396 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6397 }
6398
6399 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6400 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6401 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6402 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6403 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6404
63c3a66f 6405 if (tg3_flag(tp, NVRAM))
97bd8e49
MC		 6406 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6407}
6408
6409static void tg3_dump_state(struct tg3 *tp)
6410{
6411 int i;
6412 u32 *regs;
6413
6414 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
b2adaca9 6415 if (!regs)
97bd8e49 6416 return;
97bd8e49 6417
63c3a66f 6418 if (tg3_flag(tp, PCI_EXPRESS)) {
97bd8e49
MC		 6419 /* Read up to but not including private PCI registers */
6420 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6421 regs[i / sizeof(u32)] = tr32(i);
6422 } else
6423 tg3_dump_legacy_regs(tp, regs);
6424
6425 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6426 if (!regs[i + 0] && !regs[i + 1] &&
6427 !regs[i + 2] && !regs[i + 3])
6428 continue;
6429
6430 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6431 i * 4,
6432 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6433 }
6434
6435 kfree(regs);
6436
6437 for (i = 0; i < tp->irq_cnt; i++) {
6438 struct tg3_napi *tnapi = &tp->napi[i];
6439
6440 /* SW status block */
6441 netdev_err(tp->dev,
6442 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6443 i,
6444 tnapi->hw_status->status,
6445 tnapi->hw_status->status_tag,
6446 tnapi->hw_status->rx_jumbo_consumer,
6447 tnapi->hw_status->rx_consumer,
6448 tnapi->hw_status->rx_mini_consumer,
6449 tnapi->hw_status->idx[0].rx_producer,
6450 tnapi->hw_status->idx[0].tx_consumer);
6451
6452 netdev_err(tp->dev,
6453 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6454 i,
6455 tnapi->last_tag, tnapi->last_irq_tag,
6456 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6457 tnapi->rx_rcb_ptr,
6458 tnapi->prodring.rx_std_prod_idx,
6459 tnapi->prodring.rx_std_cons_idx,
6460 tnapi->prodring.rx_jmb_prod_idx,
6461 tnapi->prodring.rx_jmb_cons_idx);
6462 }
6463}
6464
df3e6548
MC		 6465/* This is called whenever we suspect that the system chipset is re-
6466 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6467 * is bogus tx completions. We try to recover by setting the
6468 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6469 * in the workqueue.
6470 */
6471static void tg3_tx_recover(struct tg3 *tp)
6472{
63c3a66f 6473 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
df3e6548
MC		 6474 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6475
5129c3a3
MC		 6476 netdev_warn(tp->dev,
6477 "The system may be re-ordering memory-mapped I/O "
6478 "cycles to the network device, attempting to recover. "
6479 "Please report the problem to the driver maintainer "
6480 "and include system chipset information.\n");
df3e6548 6481
63c3a66f 6482 tg3_flag_set(tp, TX_RECOVERY_PENDING);
df3e6548
MC		 6483}
6484
f3f3f27e 6485static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205 6486{
f65aac16
MC		 6487 /* Tell compiler to fetch tx indices from memory. */
6488 barrier();
f3f3f27e
MC		 6489 return tnapi->tx_pending -
6490 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 6491}
6492
1da177e4
LT		 6493/* Tigon3 never reports partial packet sends. So we do not
6494 * need special logic to handle SKBs that have not had all
6495 * of their frags sent yet, like SunGEM does.
6496 */
17375d25 6497static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 6498{
17375d25 6499 struct tg3 *tp = tnapi->tp;
898a56f8 6500 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 6501 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 6502 struct netdev_queue *txq;
6503 int index = tnapi - tp->napi;
298376d3 6504 unsigned int pkts_compl = 0, bytes_compl = 0;
fe5f5787 6505
63c3a66f 6506 if (tg3_flag(tp, ENABLE_TSS))
fe5f5787
MC		 6507 index--;
6508
6509 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 6510
6511 while (sw_idx != hw_idx) {
df8944cf 6512 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 6513 struct sk_buff *skb = ri->skb;
df3e6548
MC		 6514 int i, tx_bug = 0;
6515
6516 if (unlikely(skb == NULL)) {
6517 tg3_tx_recover(tp);
6518 return;
6519 }
1da177e4 6520
fb4ce8ad
MC		 6521 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6522 struct skb_shared_hwtstamps timestamp;
6523 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6524 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6525
6526 tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);
6527
6528 skb_tstamp_tx(skb, &timestamp);
6529 }
6530
f4188d8a 6531 pci_unmap_single(tp->pdev,
4e5e4f0d 6532 dma_unmap_addr(ri, mapping),
f4188d8a
AD		 6533 skb_headlen(skb),
6534 PCI_DMA_TODEVICE);
1da177e4
LT		 6535
6536 ri->skb = NULL;
6537
e01ee14d
MC		 6538 while (ri->fragmented) {
6539 ri->fragmented = false;
6540 sw_idx = NEXT_TX(sw_idx);
6541 ri = &tnapi->tx_buffers[sw_idx];
6542 }
6543
1da177e4
LT		 6544 sw_idx = NEXT_TX(sw_idx);
6545
6546 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 6547 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 6548 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6549 tx_bug = 1;
f4188d8a
AD		 6550
6551 pci_unmap_page(tp->pdev,
4e5e4f0d 6552 dma_unmap_addr(ri, mapping),
9e903e08 6553 skb_frag_size(&skb_shinfo(skb)->frags[i]),
f4188d8a 6554 PCI_DMA_TODEVICE);
e01ee14d
MC		 6555
6556 while (ri->fragmented) {
6557 ri->fragmented = false;
6558 sw_idx = NEXT_TX(sw_idx);
6559 ri = &tnapi->tx_buffers[sw_idx];
6560 }
6561
1da177e4
LT		 6562 sw_idx = NEXT_TX(sw_idx);
6563 }
6564
298376d3
TH		 6565 pkts_compl++;
6566 bytes_compl += skb->len;
6567
f47c11ee 6568 dev_kfree_skb(skb);
df3e6548
MC		 6569
6570 if (unlikely(tx_bug)) {
6571 tg3_tx_recover(tp);
6572 return;
6573 }
1da177e4
LT		 6574 }
6575
5cb917bc 6576 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
298376d3 6577
f3f3f27e 6578 tnapi->tx_cons = sw_idx;
1da177e4 6579
1b2a7205
MC		 6580 /* Need to make the tx_cons update visible to tg3_start_xmit()
6581 * before checking for netif_queue_stopped(). Without the
6582 * memory barrier, there is a small possibility that tg3_start_xmit()
6583 * will miss it and cause the queue to be stopped forever.
6584 */
6585 smp_mb();
6586
fe5f5787 6587 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 6588 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 6589 __netif_tx_lock(txq, smp_processor_id());
6590 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 6591 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 6592 netif_tx_wake_queue(txq);
6593 __netif_tx_unlock(txq);
51b91468 6594 }
1da177e4
LT		 6595}
6596
8d4057a9
ED		 6597static void tg3_frag_free(bool is_frag, void *data)
6598{
6599 if (is_frag)
6600 put_page(virt_to_head_page(data));
6601 else
6602 kfree(data);
6603}
6604
9205fd9c 6605static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
2b2cdb65 6606{
8d4057a9
ED		 6607 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6608 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6609
9205fd9c 6610 if (!ri->data)
2b2cdb65
MC		 6611 return;
6612
4e5e4f0d 6613 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
2b2cdb65 6614 map_sz, PCI_DMA_FROMDEVICE);
a1e8b307 6615 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
9205fd9c 6616 ri->data = NULL;
2b2cdb65
MC		 6617}
6618
8d4057a9 6619
1da177e4
LT		 6620/* Returns size of skb allocated or < 0 on error.
6621 *
6622 * We only need to fill in the address because the other members
6623 * of the RX descriptor are invariant, see tg3_init_rings.
6624 *
6625 * Note the purposeful assymetry of cpu vs. chip accesses. For
6626 * posting buffers we only dirty the first cache line of the RX
6627 * descriptor (containing the address). Whereas for the RX status
6628 * buffers the cpu only reads the last cacheline of the RX descriptor
6629 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6630 */
9205fd9c 6631static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
8d4057a9
ED		 6632 u32 opaque_key, u32 dest_idx_unmasked,
6633 unsigned int *frag_size)
1da177e4
LT		 6634{
6635 struct tg3_rx_buffer_desc *desc;
f94e290e 6636 struct ring_info *map;
9205fd9c 6637 u8 *data;
1da177e4 6638 dma_addr_t mapping;
9205fd9c 6639 int skb_size, data_size, dest_idx;
1da177e4 6640
1da177e4
LT		 6641 switch (opaque_key) {
6642 case RXD_OPAQUE_RING_STD:
2c49a44d 6643 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
21f581a5
MC		 6644 desc = &tpr->rx_std[dest_idx];
6645 map = &tpr->rx_std_buffers[dest_idx];
9205fd9c 6646 data_size = tp->rx_pkt_map_sz;
1da177e4
LT		 6647 break;
6648
6649 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6650 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
79ed5ac7 6651 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 6652 map = &tpr->rx_jmb_buffers[dest_idx];
9205fd9c 6653 data_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 6654 break;
6655
6656 default:
6657 return -EINVAL;
855e1111 6658 }
1da177e4
LT		 6659
6660 /* Do not overwrite any of the map or rp information
6661 * until we are sure we can commit to a new buffer.
6662 *
6663 * Callers depend upon this behavior and assume that
6664 * we leave everything unchanged if we fail.
6665 */
9205fd9c
ED		 6666 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6667 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
a1e8b307
ED		 6668 if (skb_size <= PAGE_SIZE) {
6669 data = netdev_alloc_frag(skb_size);
6670 *frag_size = skb_size;
8d4057a9
ED		 6671 } else {
6672 data = kmalloc(skb_size, GFP_ATOMIC);
6673 *frag_size = 0;
6674 }
9205fd9c 6675 if (!data)
1da177e4
LT		 6676 return -ENOMEM;
6677
9205fd9c
ED		 6678 mapping = pci_map_single(tp->pdev,
6679 data + TG3_RX_OFFSET(tp),
6680 data_size,
1da177e4 6681 PCI_DMA_FROMDEVICE);
8d4057a9 6682 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
a1e8b307 6683 tg3_frag_free(skb_size <= PAGE_SIZE, data);
a21771dd
MC		 6684 return -EIO;
6685 }
1da177e4 6686
9205fd9c 6687 map->data = data;
4e5e4f0d 6688 dma_unmap_addr_set(map, mapping, mapping);
1da177e4 6689
1da177e4
LT		 6690 desc->addr_hi = ((u64)mapping >> 32);
6691 desc->addr_lo = ((u64)mapping & 0xffffffff);
6692
9205fd9c 6693 return data_size;
1da177e4
LT		 6694}
6695
6696/* We only need to move over in the address because the other
6697 * members of the RX descriptor are invariant. See notes above
9205fd9c 6698 * tg3_alloc_rx_data for full details.
1da177e4 6699 */
a3896167
MC		 6700static void tg3_recycle_rx(struct tg3_napi *tnapi,
6701 struct tg3_rx_prodring_set *dpr,
6702 u32 opaque_key, int src_idx,
6703 u32 dest_idx_unmasked)
1da177e4 6704{
17375d25 6705 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 6706 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6707 struct ring_info *src_map, *dest_map;
8fea32b9 6708 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
c6cdf436 6709 int dest_idx;
1da177e4
LT		 6710
6711 switch (opaque_key) {
6712 case RXD_OPAQUE_RING_STD:
2c49a44d 6713 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
a3896167
MC		 6714 dest_desc = &dpr->rx_std[dest_idx];
6715 dest_map = &dpr->rx_std_buffers[dest_idx];
6716 src_desc = &spr->rx_std[src_idx];
6717 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 6718 break;
6719
6720 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6721 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
a3896167
MC		 6722 dest_desc = &dpr->rx_jmb[dest_idx].std;
6723 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6724 src_desc = &spr->rx_jmb[src_idx].std;
6725 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 6726 break;
6727
6728 default:
6729 return;
855e1111 6730 }
1da177e4 6731
9205fd9c 6732 dest_map->data = src_map->data;
4e5e4f0d
FT		 6733 dma_unmap_addr_set(dest_map, mapping,
6734 dma_unmap_addr(src_map, mapping));
1da177e4
LT		 6735 dest_desc->addr_hi = src_desc->addr_hi;
6736 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 6737
6738 /* Ensure that the update to the skb happens after the physical
6739 * addresses have been transferred to the new BD location.
6740 */
6741 smp_wmb();
6742
9205fd9c 6743 src_map->data = NULL;
1da177e4
LT		 6744}
6745
1da177e4
LT		 6746/* The RX ring scheme is composed of multiple rings which post fresh
6747 * buffers to the chip, and one special ring the chip uses to report
6748 * status back to the host.
6749 *
6750 * The special ring reports the status of received packets to the
6751 * host. The chip does not write into the original descriptor the
6752 * RX buffer was obtained from. The chip simply takes the original
6753 * descriptor as provided by the host, updates the status and length
6754 * field, then writes this into the next status ring entry.
6755 *
6756 * Each ring the host uses to post buffers to the chip is described
6757 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6758 * it is first placed into the on-chip ram. When the packet's length
6759 * is known, it walks down the TG3_BDINFO entries to select the ring.
6760 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6761 * which is within the range of the new packet's length is chosen.
6762 *
6763 * The "separate ring for rx status" scheme may sound queer, but it makes
6764 * sense from a cache coherency perspective. If only the host writes
6765 * to the buffer post rings, and only the chip writes to the rx status
6766 * rings, then cache lines never move beyond shared-modified state.
6767 * If both the host and chip were to write into the same ring, cache line
6768 * eviction could occur since both entities want it in an exclusive state.
6769 */
17375d25 6770static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 6771{
17375d25 6772 struct tg3 *tp = tnapi->tp;
f92905de 6773 u32 work_mask, rx_std_posted = 0;
4361935a 6774 u32 std_prod_idx, jmb_prod_idx;
72334482 6775 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 6776 u16 hw_idx;
1da177e4 6777 int received;
8fea32b9 6778 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
1da177e4 6779
8d9d7cfc 6780 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 6781 /*
6782 * We need to order the read of hw_idx and the read of
6783 * the opaque cookie.
6784 */
6785 rmb();
1da177e4
LT		 6786 work_mask = 0;
6787 received = 0;
4361935a
MC		 6788 std_prod_idx = tpr->rx_std_prod_idx;
6789 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 6790 while (sw_idx != hw_idx && budget > 0) {
afc081f8 6791 struct ring_info *ri;
72334482 6792 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 6793 unsigned int len;
6794 struct sk_buff *skb;
6795 dma_addr_t dma_addr;
6796 u32 opaque_key, desc_idx, *post_ptr;
9205fd9c 6797 u8 *data;
fb4ce8ad 6798 u64 tstamp = 0;
1da177e4
LT		 6799
6800 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6801 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6802 if (opaque_key == RXD_OPAQUE_RING_STD) {
8fea32b9 6803 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4e5e4f0d 6804 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6805 data = ri->data;
4361935a 6806 post_ptr = &std_prod_idx;
f92905de 6807 rx_std_posted++;
1da177e4 6808 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
8fea32b9 6809 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4e5e4f0d 6810 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6811 data = ri->data;
4361935a 6812 post_ptr = &jmb_prod_idx;
21f581a5 6813 } else
1da177e4 6814 goto next_pkt_nopost;
1da177e4
LT		 6815
6816 work_mask |= opaque_key;
6817
6818 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
6819 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
6820 drop_it:
a3896167 6821 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6822 desc_idx, *post_ptr);
6823 drop_it_no_recycle:
6824 /* Other statistics kept track of by card. */
b0057c51 6825 tp->rx_dropped++;
1da177e4
LT		 6826 goto next_pkt;
6827 }
6828
9205fd9c 6829 prefetch(data + TG3_RX_OFFSET(tp));
ad829268
MC		 6830 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6831 ETH_FCS_LEN;
1da177e4 6832
fb4ce8ad
MC		 6833 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6834 RXD_FLAG_PTPSTAT_PTPV1 ||
6835 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6836 RXD_FLAG_PTPSTAT_PTPV2) {
6837 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6838 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6839 }
6840
d2757fc4 6841 if (len > TG3_RX_COPY_THRESH(tp)) {
1da177e4 6842 int skb_size;
8d4057a9 6843 unsigned int frag_size;
1da177e4 6844
9205fd9c 6845 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
8d4057a9 6846 *post_ptr, &frag_size);
1da177e4
LT		 6847 if (skb_size < 0)
6848 goto drop_it;
6849
287be12e 6850 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 6851 PCI_DMA_FROMDEVICE);
6852
8d4057a9 6853 skb = build_skb(data, frag_size);
9205fd9c 6854 if (!skb) {
8d4057a9 6855 tg3_frag_free(frag_size != 0, data);
9205fd9c
ED		 6856 goto drop_it_no_recycle;
6857 }
6858 skb_reserve(skb, TG3_RX_OFFSET(tp));
6859 /* Ensure that the update to the data happens
61e800cf
MC		 6860 * after the usage of the old DMA mapping.
6861 */
6862 smp_wmb();
6863
9205fd9c 6864 ri->data = NULL;
61e800cf 6865
1da177e4 6866 } else {
a3896167 6867 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6868 desc_idx, *post_ptr);
6869
9205fd9c
ED		 6870 skb = netdev_alloc_skb(tp->dev,
6871 len + TG3_RAW_IP_ALIGN);
6872 if (skb == NULL)
1da177e4
LT		 6873 goto drop_it_no_recycle;
6874
9205fd9c 6875 skb_reserve(skb, TG3_RAW_IP_ALIGN);
1da177e4 6876 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
9205fd9c
ED		 6877 memcpy(skb->data,
6878 data + TG3_RX_OFFSET(tp),
6879 len);
1da177e4 6880 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
1da177e4
LT		 6881 }
6882
9205fd9c 6883 skb_put(skb, len);
fb4ce8ad
MC		 6884 if (tstamp)
6885 tg3_hwclock_to_timestamp(tp, tstamp,
6886 skb_hwtstamps(skb));
6887
dc668910 6888 if ((tp->dev->features & NETIF_F_RXCSUM) &&
1da177e4
LT		 6889 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6890 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6891 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6892 skb->ip_summed = CHECKSUM_UNNECESSARY;
6893 else
bc8acf2c 6894 skb_checksum_none_assert(skb);
1da177e4
LT		 6895
6896 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 6897
6898 if (len > (tp->dev->mtu + ETH_HLEN) &&
6899 skb->protocol != htons(ETH_P_8021Q)) {
6900 dev_kfree_skb(skb);
b0057c51 6901 goto drop_it_no_recycle;
f7b493e0
MC		 6902 }
6903
9dc7a113 6904 if (desc->type_flags & RXD_FLAG_VLAN &&
bf933c80 6905 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
86a9bad3 6906 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
bf933c80 6907 desc->err_vlan & RXD_VLAN_MASK);
9dc7a113 6908
bf933c80 6909 napi_gro_receive(&tnapi->napi, skb);
1da177e4 6910
1da177e4
LT		 6911 received++;
6912 budget--;
6913
6914next_pkt:
6915 (*post_ptr)++;
f92905de
MC		 6916
6917 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
2c49a44d
MC		 6918 tpr->rx_std_prod_idx = std_prod_idx &
6919 tp->rx_std_ring_mask;
86cfe4ff
MC		 6920 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6921 tpr->rx_std_prod_idx);
f92905de
MC		 6922 work_mask &= ~RXD_OPAQUE_RING_STD;
6923 rx_std_posted = 0;
6924 }
1da177e4 6925next_pkt_nopost:
483ba50b 6926 sw_idx++;
7cb32cf2 6927 sw_idx &= tp->rx_ret_ring_mask;
52f6d697
MC		 6928
6929 /* Refresh hw_idx to see if there is new work */
6930 if (sw_idx == hw_idx) {
8d9d7cfc 6931 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 6932 rmb();
6933 }
1da177e4
LT		 6934 }
6935
6936 /* ACK the status ring. */
72334482
MC		 6937 tnapi->rx_rcb_ptr = sw_idx;
6938 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 6939
6940 /* Refill RX ring(s). */
63c3a66f 6941 if (!tg3_flag(tp, ENABLE_RSS)) {
6541b806
MC		 6942 /* Sync BD data before updating mailbox */
6943 wmb();
6944
b196c7e4 6945 if (work_mask & RXD_OPAQUE_RING_STD) {
2c49a44d
MC		 6946 tpr->rx_std_prod_idx = std_prod_idx &
6947 tp->rx_std_ring_mask;
b196c7e4
MC		 6948 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6949 tpr->rx_std_prod_idx);
6950 }
6951 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2c49a44d
MC		 6952 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6953 tp->rx_jmb_ring_mask;
b196c7e4
MC		 6954 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6955 tpr->rx_jmb_prod_idx);
6956 }
6957 mmiowb();
6958 } else if (work_mask) {
6959 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6960 * updated before the producer indices can be updated.
6961 */
6962 smp_wmb();
6963
2c49a44d
MC		 6964 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6965 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
b196c7e4 6966
7ae52890
MC		 6967 if (tnapi != &tp->napi[1]) {
6968 tp->rx_refill = true;
e4af1af9 6969 napi_schedule(&tp->napi[1].napi);
7ae52890 6970 }
1da177e4 6971 }
1da177e4
LT		 6972
6973 return received;
6974}
6975
35f2d7d0 6976static void tg3_poll_link(struct tg3 *tp)
1da177e4 6977{
1da177e4 6978 /* handle link change and other phy events */
63c3a66f 6979 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
35f2d7d0
MC		 6980 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
6981
1da177e4
LT		 6982 if (sblk->status & SD_STATUS_LINK_CHG) {
6983 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 6984 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 6985 spin_lock(&tp->lock);
63c3a66f 6986 if (tg3_flag(tp, USE_PHYLIB)) {
dd477003
MC		 6987 tw32_f(MAC_STATUS,
6988 (MAC_STATUS_SYNC_CHANGED |
6989 MAC_STATUS_CFG_CHANGED |
6990 MAC_STATUS_MI_COMPLETION |
6991 MAC_STATUS_LNKSTATE_CHANGED));
6992 udelay(40);
6993 } else
953c96e0 6994 tg3_setup_phy(tp, false);
f47c11ee 6995 spin_unlock(&tp->lock);
1da177e4
LT		 6996 }
6997 }
35f2d7d0
MC		 6998}
6999
f89f38b8
MC		 7000static int tg3_rx_prodring_xfer(struct tg3 *tp,
7001 struct tg3_rx_prodring_set *dpr,
7002 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 7003{
7004 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 7005 int i, err = 0;
b196c7e4
MC		 7006
7007 while (1) {
7008 src_prod_idx = spr->rx_std_prod_idx;
7009
7010 /* Make sure updates to the rx_std_buffers[] entries and the
7011 * standard producer index are seen in the correct order.
7012 */
7013 smp_rmb();
7014
7015 if (spr->rx_std_cons_idx == src_prod_idx)
7016 break;
7017
7018 if (spr->rx_std_cons_idx < src_prod_idx)
7019 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7020 else
2c49a44d
MC		 7021 cpycnt = tp->rx_std_ring_mask + 1 -
7022 spr->rx_std_cons_idx;
b196c7e4 7023
2c49a44d
MC		 7024 cpycnt = min(cpycnt,
7025 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
b196c7e4
MC		 7026
7027 si = spr->rx_std_cons_idx;
7028 di = dpr->rx_std_prod_idx;
7029
e92967bf 7030 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7031 if (dpr->rx_std_buffers[i].data) {
e92967bf 7032 cpycnt = i - di;
f89f38b8 7033 err = -ENOSPC;
e92967bf
MC		 7034 break;
7035 }
7036 }
7037
7038 if (!cpycnt)
7039 break;
7040
7041 /* Ensure that updates to the rx_std_buffers ring and the
7042 * shadowed hardware producer ring from tg3_recycle_skb() are
7043 * ordered correctly WRT the skb check above.
7044 */
7045 smp_rmb();
7046
b196c7e4
MC		 7047 memcpy(&dpr->rx_std_buffers[di],
7048 &spr->rx_std_buffers[si],
7049 cpycnt * sizeof(struct ring_info));
7050
7051 for (i = 0; i < cpycnt; i++, di++, si++) {
7052 struct tg3_rx_buffer_desc *sbd, *dbd;
7053 sbd = &spr->rx_std[si];
7054 dbd = &dpr->rx_std[di];
7055 dbd->addr_hi = sbd->addr_hi;
7056 dbd->addr_lo = sbd->addr_lo;
7057 }
7058
2c49a44d
MC		 7059 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7060 tp->rx_std_ring_mask;
7061 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7062 tp->rx_std_ring_mask;
b196c7e4
MC		 7063 }
7064
7065 while (1) {
7066 src_prod_idx = spr->rx_jmb_prod_idx;
7067
7068 /* Make sure updates to the rx_jmb_buffers[] entries and
7069 * the jumbo producer index are seen in the correct order.
7070 */
7071 smp_rmb();
7072
7073 if (spr->rx_jmb_cons_idx == src_prod_idx)
7074 break;
7075
7076 if (spr->rx_jmb_cons_idx < src_prod_idx)
7077 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7078 else
2c49a44d
MC		 7079 cpycnt = tp->rx_jmb_ring_mask + 1 -
7080 spr->rx_jmb_cons_idx;
b196c7e4
MC		 7081
7082 cpycnt = min(cpycnt,
2c49a44d 7083 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7084
7085 si = spr->rx_jmb_cons_idx;
7086 di = dpr->rx_jmb_prod_idx;
7087
e92967bf 7088 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7089 if (dpr->rx_jmb_buffers[i].data) {
e92967bf 7090 cpycnt = i - di;
f89f38b8 7091 err = -ENOSPC;
e92967bf
MC		 7092 break;
7093 }
7094 }
7095
7096 if (!cpycnt)
7097 break;
7098
7099 /* Ensure that updates to the rx_jmb_buffers ring and the
7100 * shadowed hardware producer ring from tg3_recycle_skb() are
7101 * ordered correctly WRT the skb check above.
7102 */
7103 smp_rmb();
7104
b196c7e4
MC		 7105 memcpy(&dpr->rx_jmb_buffers[di],
7106 &spr->rx_jmb_buffers[si],
7107 cpycnt * sizeof(struct ring_info));
7108
7109 for (i = 0; i < cpycnt; i++, di++, si++) {
7110 struct tg3_rx_buffer_desc *sbd, *dbd;
7111 sbd = &spr->rx_jmb[si].std;
7112 dbd = &dpr->rx_jmb[di].std;
7113 dbd->addr_hi = sbd->addr_hi;
7114 dbd->addr_lo = sbd->addr_lo;
7115 }
7116
2c49a44d
MC		 7117 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7118 tp->rx_jmb_ring_mask;
7119 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7120 tp->rx_jmb_ring_mask;
b196c7e4 7121 }
f89f38b8
MC		 7122
7123 return err;
b196c7e4
MC		 7124}
7125
35f2d7d0
MC		 7126static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7127{
7128 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 7129
7130 /* run TX completion thread */
f3f3f27e 7131 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 7132 tg3_tx(tnapi);
63c3a66f 7133 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
4fd7ab59 7134 return work_done;
1da177e4
LT		 7135 }
7136
f891ea16
MC		 7137 if (!tnapi->rx_rcb_prod_idx)
7138 return work_done;
7139
1da177e4
LT		 7140 /* run RX thread, within the bounds set by NAPI.
7141 * All RX "locking" is done by ensuring outside
bea3348e 7142 * code synchronizes with tg3->napi.poll()
1da177e4 7143 */
8d9d7cfc 7144 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 7145 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 7146
63c3a66f 7147 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
8fea32b9 7148 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
f89f38b8 7149 int i, err = 0;
e4af1af9
MC		 7150 u32 std_prod_idx = dpr->rx_std_prod_idx;
7151 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 7152
7ae52890 7153 tp->rx_refill = false;
9102426a 7154 for (i = 1; i <= tp->rxq_cnt; i++)
f89f38b8 7155 err |= tg3_rx_prodring_xfer(tp, dpr,
8fea32b9 7156 &tp->napi[i].prodring);
b196c7e4
MC		 7157
7158 wmb();
7159
e4af1af9
MC		 7160 if (std_prod_idx != dpr->rx_std_prod_idx)
7161 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7162 dpr->rx_std_prod_idx);
b196c7e4 7163
e4af1af9
MC		 7164 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7165 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7166 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7167
7168 mmiowb();
f89f38b8
MC		 7169
7170 if (err)
7171 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 7172 }
7173
6f535763
DM		 7174 return work_done;
7175}
7176
db219973
MC		 7177static inline void tg3_reset_task_schedule(struct tg3 *tp)
7178{
7179 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7180 schedule_work(&tp->reset_task);
7181}
7182
7183static inline void tg3_reset_task_cancel(struct tg3 *tp)
7184{
7185 cancel_work_sync(&tp->reset_task);
7186 tg3_flag_clear(tp, RESET_TASK_PENDING);
c7101359 7187 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
db219973
MC		 7188}
7189
35f2d7d0
MC		 7190static int tg3_poll_msix(struct napi_struct *napi, int budget)
7191{
7192 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7193 struct tg3 *tp = tnapi->tp;
7194 int work_done = 0;
7195 struct tg3_hw_status *sblk = tnapi->hw_status;
7196
7197 while (1) {
7198 work_done = tg3_poll_work(tnapi, work_done, budget);
7199
63c3a66f 7200 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
35f2d7d0
MC		 7201 goto tx_recovery;
7202
7203 if (unlikely(work_done >= budget))
7204 break;
7205
c6cdf436 7206 /* tp->last_tag is used in tg3_int_reenable() below
35f2d7d0
MC		 7207 * to tell the hw how much work has been processed,
7208 * so we must read it before checking for more work.
7209 */
7210 tnapi->last_tag = sblk->status_tag;
7211 tnapi->last_irq_tag = tnapi->last_tag;
7212 rmb();
7213
7214 /* check for RX/TX work to do */
6d40db7b
MC		 7215 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7216 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7ae52890
MC		 7217
7218 /* This test here is not race free, but will reduce
7219 * the number of interrupts by looping again.
7220 */
7221 if (tnapi == &tp->napi[1] && tp->rx_refill)
7222 continue;
7223
35f2d7d0
MC		 7224 napi_complete(napi);
7225 /* Reenable interrupts. */
7226 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7ae52890
MC		 7227
7228 /* This test here is synchronized by napi_schedule()
7229 * and napi_complete() to close the race condition.
7230 */
7231 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7232 tw32(HOSTCC_MODE, tp->coalesce_mode |
7233 HOSTCC_MODE_ENABLE |
7234 tnapi->coal_now);
7235 }
35f2d7d0
MC		 7236 mmiowb();
7237 break;
7238 }
7239 }
7240
7241 return work_done;
7242
7243tx_recovery:
7244 /* work_done is guaranteed to be less than budget. */
7245 napi_complete(napi);
db219973 7246 tg3_reset_task_schedule(tp);
35f2d7d0
MC		 7247 return work_done;
7248}
7249
e64de4e6
MC		 7250static void tg3_process_error(struct tg3 *tp)
7251{
7252 u32 val;
7253 bool real_error = false;
7254
63c3a66f 7255 if (tg3_flag(tp, ERROR_PROCESSED))
e64de4e6
MC		 7256 return;
7257
7258 /* Check Flow Attention register */
7259 val = tr32(HOSTCC_FLOW_ATTN);
7260 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7261 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7262 real_error = true;
7263 }
7264
7265 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7266 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7267 real_error = true;
7268 }
7269
7270 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7271 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7272 real_error = true;
7273 }
7274
7275 if (!real_error)
7276 return;
7277
7278 tg3_dump_state(tp);
7279
63c3a66f 7280 tg3_flag_set(tp, ERROR_PROCESSED);
db219973 7281 tg3_reset_task_schedule(tp);
e64de4e6
MC		 7282}
7283
6f535763
DM		 7284static int tg3_poll(struct napi_struct *napi, int budget)
7285{
8ef0442f
MC		 7286 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7287 struct tg3 *tp = tnapi->tp;
6f535763 7288 int work_done = 0;
898a56f8 7289 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 7290
7291 while (1) {
e64de4e6
MC		 7292 if (sblk->status & SD_STATUS_ERROR)
7293 tg3_process_error(tp);
7294
35f2d7d0
MC		 7295 tg3_poll_link(tp);
7296
17375d25 7297 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763 7298
63c3a66f 7299 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6f535763
DM		 7300 goto tx_recovery;
7301
7302 if (unlikely(work_done >= budget))
7303 break;
7304
63c3a66f 7305 if (tg3_flag(tp, TAGGED_STATUS)) {
17375d25 7306 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 7307 * to tell the hw how much work has been processed,
7308 * so we must read it before checking for more work.
7309 */
898a56f8
MC		 7310 tnapi->last_tag = sblk->status_tag;
7311 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 7312 rmb();
7313 } else
7314 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 7315
17375d25 7316 if (likely(!tg3_has_work(tnapi))) {
288379f0 7317 napi_complete(napi);
17375d25 7318 tg3_int_reenable(tnapi);
6f535763
DM		 7319 break;
7320 }
1da177e4
LT		 7321 }
7322
bea3348e 7323 return work_done;
6f535763
DM		 7324
7325tx_recovery:
4fd7ab59 7326 /* work_done is guaranteed to be less than budget. */
288379f0 7327 napi_complete(napi);
db219973 7328 tg3_reset_task_schedule(tp);
4fd7ab59 7329 return work_done;
1da177e4
LT		 7330}
7331
66cfd1bd
MC		 7332static void tg3_napi_disable(struct tg3 *tp)
7333{
7334 int i;
7335
7336 for (i = tp->irq_cnt - 1; i >= 0; i--)
7337 napi_disable(&tp->napi[i].napi);
7338}
7339
7340static void tg3_napi_enable(struct tg3 *tp)
7341{
7342 int i;
7343
7344 for (i = 0; i < tp->irq_cnt; i++)
7345 napi_enable(&tp->napi[i].napi);
7346}
7347
7348static void tg3_napi_init(struct tg3 *tp)
7349{
7350 int i;
7351
7352 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7353 for (i = 1; i < tp->irq_cnt; i++)
7354 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7355}
7356
7357static void tg3_napi_fini(struct tg3 *tp)
7358{
7359 int i;
7360
7361 for (i = 0; i < tp->irq_cnt; i++)
7362 netif_napi_del(&tp->napi[i].napi);
7363}
7364
7365static inline void tg3_netif_stop(struct tg3 *tp)
7366{
7367 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7368 tg3_napi_disable(tp);
f4a46d1f 7369 netif_carrier_off(tp->dev);
66cfd1bd
MC		 7370 netif_tx_disable(tp->dev);
7371}
7372
35763066 7373/* tp->lock must be held */
66cfd1bd
MC		 7374static inline void tg3_netif_start(struct tg3 *tp)
7375{
be947307
MC		 7376 tg3_ptp_resume(tp);
7377
66cfd1bd
MC		 7378 /* NOTE: unconditional netif_tx_wake_all_queues is only
7379 * appropriate so long as all callers are assured to
7380 * have free tx slots (such as after tg3_init_hw)
7381 */
7382 netif_tx_wake_all_queues(tp->dev);
7383
f4a46d1f
NNS		 7384 if (tp->link_up)
7385 netif_carrier_on(tp->dev);
7386
66cfd1bd
MC		 7387 tg3_napi_enable(tp);
7388 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7389 tg3_enable_ints(tp);
7390}
7391
f47c11ee
DM		 7392static void tg3_irq_quiesce(struct tg3 *tp)
7393{
4f125f42
MC		 7394 int i;
7395
f47c11ee
DM		 7396 BUG_ON(tp->irq_sync);
7397
7398 tp->irq_sync = 1;
7399 smp_mb();
7400
4f125f42
MC		 7401 for (i = 0; i < tp->irq_cnt; i++)
7402 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 7403}
7404
f47c11ee
DM		 7405/* Fully shutdown all tg3 driver activity elsewhere in the system.
7406 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7407 * with as well. Most of the time, this is not necessary except when
7408 * shutting down the device.
7409 */
7410static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7411{
46966545 7412 spin_lock_bh(&tp->lock);
f47c11ee
DM		 7413 if (irq_sync)
7414 tg3_irq_quiesce(tp);
f47c11ee
DM		 7415}
7416
7417static inline void tg3_full_unlock(struct tg3 *tp)
7418{
f47c11ee
DM		 7419 spin_unlock_bh(&tp->lock);
7420}
7421
fcfa0a32
MC		 7422/* One-shot MSI handler - Chip automatically disables interrupt
7423 * after sending MSI so driver doesn't have to do it.
7424 */
7d12e780 7425static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 7426{
09943a18
MC		 7427 struct tg3_napi *tnapi = dev_id;
7428 struct tg3 *tp = tnapi->tp;
fcfa0a32 7429
898a56f8 7430 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7431 if (tnapi->rx_rcb)
7432 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 7433
7434 if (likely(!tg3_irq_sync(tp)))
09943a18 7435 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 7436
7437 return IRQ_HANDLED;
7438}
7439
88b06bc2
MC		 7440/* MSI ISR - No need to check for interrupt sharing and no need to
7441 * flush status block and interrupt mailbox. PCI ordering rules
7442 * guarantee that MSI will arrive after the status block.
7443 */
7d12e780 7444static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 7445{
09943a18
MC		 7446 struct tg3_napi *tnapi = dev_id;
7447 struct tg3 *tp = tnapi->tp;
88b06bc2 7448
898a56f8 7449 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7450 if (tnapi->rx_rcb)
7451 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 7452 /*
fac9b83e 7453 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 7454 * chip-internal interrupt pending events.
fac9b83e 7455 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 7456 * NIC to stop sending us irqs, engaging "in-intr-handler"
7457 * event coalescing.
7458 */
5b39de91 7459 tw32_mailbox(tnapi->int_mbox, 0x00000001);
61487480 7460 if (likely(!tg3_irq_sync(tp)))
09943a18 7461 napi_schedule(&tnapi->napi);
61487480 7462
88b06bc2
MC		 7463 return IRQ_RETVAL(1);
7464}
7465
7d12e780 7466static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 7467{
09943a18
MC		 7468 struct tg3_napi *tnapi = dev_id;
7469 struct tg3 *tp = tnapi->tp;
898a56f8 7470 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 7471 unsigned int handled = 1;
7472
1da177e4
LT		 7473 /* In INTx mode, it is possible for the interrupt to arrive at
7474 * the CPU before the status block posted prior to the interrupt.
7475 * Reading the PCI State register will confirm whether the
7476 * interrupt is ours and will flush the status block.
7477 */
d18edcb2 7478 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
63c3a66f 7479 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7480 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7481 handled = 0;
f47c11ee 7482 goto out;
fac9b83e 7483 }
d18edcb2
MC		 7484 }
7485
7486 /*
7487 * Writing any value to intr-mbox-0 clears PCI INTA# and
7488 * chip-internal interrupt pending events.
7489 * Writing non-zero to intr-mbox-0 additional tells the
7490 * NIC to stop sending us irqs, engaging "in-intr-handler"
7491 * event coalescing.
c04cb347
MC		 7492 *
7493 * Flush the mailbox to de-assert the IRQ immediately to prevent
7494 * spurious interrupts. The flush impacts performance but
7495 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7496 */
c04cb347 7497 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 7498 if (tg3_irq_sync(tp))
7499 goto out;
7500 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 7501 if (likely(tg3_has_work(tnapi))) {
72334482 7502 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 7503 napi_schedule(&tnapi->napi);
d18edcb2
MC		 7504 } else {
7505 /* No work, shared interrupt perhaps? re-enable
7506 * interrupts, and flush that PCI write
7507 */
7508 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7509 0x00000000);
fac9b83e 7510 }
f47c11ee 7511out:
fac9b83e
DM		 7512 return IRQ_RETVAL(handled);
7513}
7514
7d12e780 7515static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 7516{
09943a18
MC		 7517 struct tg3_napi *tnapi = dev_id;
7518 struct tg3 *tp = tnapi->tp;
898a56f8 7519 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 7520 unsigned int handled = 1;
7521
fac9b83e
DM		 7522 /* In INTx mode, it is possible for the interrupt to arrive at
7523 * the CPU before the status block posted prior to the interrupt.
7524 * Reading the PCI State register will confirm whether the
7525 * interrupt is ours and will flush the status block.
7526 */
898a56f8 7527 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
63c3a66f 7528 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7529 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7530 handled = 0;
f47c11ee 7531 goto out;
1da177e4 7532 }
d18edcb2
MC		 7533 }
7534
7535 /*
7536 * writing any value to intr-mbox-0 clears PCI INTA# and
7537 * chip-internal interrupt pending events.
7538 * writing non-zero to intr-mbox-0 additional tells the
7539 * NIC to stop sending us irqs, engaging "in-intr-handler"
7540 * event coalescing.
c04cb347
MC		 7541 *
7542 * Flush the mailbox to de-assert the IRQ immediately to prevent
7543 * spurious interrupts. The flush impacts performance but
7544 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7545 */
c04cb347 7546 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 7547
7548 /*
7549 * In a shared interrupt configuration, sometimes other devices'
7550 * interrupts will scream. We record the current status tag here
7551 * so that the above check can report that the screaming interrupts
7552 * are unhandled. Eventually they will be silenced.
7553 */
898a56f8 7554 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 7555
d18edcb2
MC		 7556 if (tg3_irq_sync(tp))
7557 goto out;
624f8e50 7558
72334482 7559 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 7560
09943a18 7561 napi_schedule(&tnapi->napi);
624f8e50 7562
f47c11ee 7563out:
1da177e4
LT		 7564 return IRQ_RETVAL(handled);
7565}
7566
7938109f 7567/* ISR for interrupt test */
7d12e780 7568static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 7569{
09943a18
MC		 7570 struct tg3_napi *tnapi = dev_id;
7571 struct tg3 *tp = tnapi->tp;
898a56f8 7572 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 7573
f9804ddb
MC		 7574 if ((sblk->status & SD_STATUS_UPDATED) ||
7575 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 7576 tg3_disable_ints(tp);
7938109f
MC		 7577 return IRQ_RETVAL(1);
7578 }
7579 return IRQ_RETVAL(0);
7580}
7581
1da177e4
LT		 7582#ifdef CONFIG_NET_POLL_CONTROLLER
7583static void tg3_poll_controller(struct net_device *dev)
7584{
4f125f42 7585 int i;
88b06bc2
MC		 7586 struct tg3 *tp = netdev_priv(dev);
7587
9c13cb8b
NNS		 7588 if (tg3_irq_sync(tp))
7589 return;
7590
4f125f42 7591 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 7592 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 7593}
7594#endif
7595
1da177e4
LT		 7596static void tg3_tx_timeout(struct net_device *dev)
7597{
7598 struct tg3 *tp = netdev_priv(dev);
7599
b0408751 7600 if (netif_msg_tx_err(tp)) {
05dbe005 7601 netdev_err(dev, "transmit timed out, resetting\n");
97bd8e49 7602 tg3_dump_state(tp);
b0408751 7603 }
1da177e4 7604
db219973 7605 tg3_reset_task_schedule(tp);
1da177e4
LT		 7606}
7607
c58ec932
MC		 7608/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7609static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7610{
7611 u32 base = (u32) mapping & 0xffffffff;
7612
807540ba 7613 return (base > 0xffffdcc0) && (base + len + 8 < base);
c58ec932
MC		 7614}
7615
0f0d1510
MC		 7616/* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7617 * of any 4GB boundaries: 4G, 8G, etc
7618 */
7619static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7620 u32 len, u32 mss)
7621{
7622 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7623 u32 base = (u32) mapping & 0xffffffff;
7624
7625 return ((base + len + (mss & 0x3fff)) < base);
7626 }
7627 return 0;
7628}
7629
72f2afb8
MC		 7630/* Test for DMA addresses > 40-bit */
7631static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7632 int len)
7633{
7634#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
63c3a66f 7635 if (tg3_flag(tp, 40BIT_DMA_BUG))
807540ba 7636 return ((u64) mapping + len) > DMA_BIT_MASK(40);
72f2afb8
MC		 7637 return 0;
7638#else
7639 return 0;
7640#endif
7641}
7642
d1a3b737 7643static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
92cd3a17
MC		 7644 dma_addr_t mapping, u32 len, u32 flags,
7645 u32 mss, u32 vlan)
2ffcc981 7646{
92cd3a17
MC		 7647 txbd->addr_hi = ((u64) mapping >> 32);
7648 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7649 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7650 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
2ffcc981 7651}
1da177e4 7652
84b67b27 7653static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
d1a3b737
MC		 7654 dma_addr_t map, u32 len, u32 flags,
7655 u32 mss, u32 vlan)
7656{
7657 struct tg3 *tp = tnapi->tp;
7658 bool hwbug = false;
7659
7660 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
3db1cd5c 7661 hwbug = true;
d1a3b737
MC		 7662
7663 if (tg3_4g_overflow_test(map, len))
3db1cd5c 7664 hwbug = true;
d1a3b737 7665
0f0d1510
MC		 7666 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7667 hwbug = true;
7668
d1a3b737 7669 if (tg3_40bit_overflow_test(tp, map, len))
3db1cd5c 7670 hwbug = true;
d1a3b737 7671
a4cb428d 7672 if (tp->dma_limit) {
b9e45482 7673 u32 prvidx = *entry;
e31aa987 7674 u32 tmp_flag = flags & ~TXD_FLAG_END;
a4cb428d
MC		 7675 while (len > tp->dma_limit && *budget) {
7676 u32 frag_len = tp->dma_limit;
7677 len -= tp->dma_limit;
e31aa987 7678
b9e45482
MC		 7679 /* Avoid the 8byte DMA problem */
7680 if (len <= 8) {
a4cb428d
MC		 7681 len += tp->dma_limit / 2;
7682 frag_len = tp->dma_limit / 2;
e31aa987
MC		 7683 }
7684
b9e45482
MC		 7685 tnapi->tx_buffers[*entry].fragmented = true;
7686
7687 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7688 frag_len, tmp_flag, mss, vlan);
7689 *budget -= 1;
7690 prvidx = *entry;
7691 *entry = NEXT_TX(*entry);
7692
e31aa987
MC		 7693 map += frag_len;
7694 }
7695
7696 if (len) {
7697 if (*budget) {
7698 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7699 len, flags, mss, vlan);
b9e45482 7700 *budget -= 1;
e31aa987
MC		 7701 *entry = NEXT_TX(*entry);
7702 } else {
3db1cd5c 7703 hwbug = true;
b9e45482 7704 tnapi->tx_buffers[prvidx].fragmented = false;
e31aa987
MC		 7705 }
7706 }
7707 } else {
84b67b27
MC		 7708 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7709 len, flags, mss, vlan);
e31aa987
MC		 7710 *entry = NEXT_TX(*entry);
7711 }
d1a3b737
MC		 7712
7713 return hwbug;
7714}
7715
0d681b27 7716static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
432aa7ed
MC		 7717{
7718 int i;
0d681b27 7719 struct sk_buff *skb;
df8944cf 7720 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
432aa7ed 7721
0d681b27
MC		 7722 skb = txb->skb;
7723 txb->skb = NULL;
7724
432aa7ed
MC		 7725 pci_unmap_single(tnapi->tp->pdev,
7726 dma_unmap_addr(txb, mapping),
7727 skb_headlen(skb),
7728 PCI_DMA_TODEVICE);
e01ee14d
MC		 7729
7730 while (txb->fragmented) {
7731 txb->fragmented = false;
7732 entry = NEXT_TX(entry);
7733 txb = &tnapi->tx_buffers[entry];
7734 }
7735
ba1142e4 7736 for (i = 0; i <= last; i++) {
9e903e08 7737 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
432aa7ed
MC		 7738
7739 entry = NEXT_TX(entry);
7740 txb = &tnapi->tx_buffers[entry];
7741
7742 pci_unmap_page(tnapi->tp->pdev,
7743 dma_unmap_addr(txb, mapping),
9e903e08 7744 skb_frag_size(frag), PCI_DMA_TODEVICE);
e01ee14d
MC		 7745
7746 while (txb->fragmented) {
7747 txb->fragmented = false;
7748 entry = NEXT_TX(entry);
7749 txb = &tnapi->tx_buffers[entry];
7750 }
432aa7ed
MC		 7751 }
7752}
7753
72f2afb8 7754/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4 7755static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
f7ff1987 7756 struct sk_buff **pskb,
84b67b27 7757 u32 *entry, u32 *budget,
92cd3a17 7758 u32 base_flags, u32 mss, u32 vlan)
1da177e4 7759{
24f4efd4 7760 struct tg3 *tp = tnapi->tp;
f7ff1987 7761 struct sk_buff *new_skb, *skb = *pskb;
c58ec932 7762 dma_addr_t new_addr = 0;
432aa7ed 7763 int ret = 0;
1da177e4 7764
4153577a 7765 if (tg3_asic_rev(tp) != ASIC_REV_5701)
41588ba1
MC		 7766 new_skb = skb_copy(skb, GFP_ATOMIC);
7767 else {
7768 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7769
7770 new_skb = skb_copy_expand(skb,
7771 skb_headroom(skb) + more_headroom,
7772 skb_tailroom(skb), GFP_ATOMIC);
7773 }
7774
1da177e4 7775 if (!new_skb) {
c58ec932
MC		 7776 ret = -1;
7777 } else {
7778 /* New SKB is guaranteed to be linear. */
f4188d8a
AD		 7779 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7780 PCI_DMA_TODEVICE);
7781 /* Make sure the mapping succeeded */
7782 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
f4188d8a 7783 dev_kfree_skb(new_skb);
c58ec932 7784 ret = -1;
c58ec932 7785 } else {
b9e45482
MC		 7786 u32 save_entry = *entry;
7787
92cd3a17
MC		 7788 base_flags |= TXD_FLAG_END;
7789
84b67b27
MC		 7790 tnapi->tx_buffers[*entry].skb = new_skb;
7791 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
432aa7ed
MC		 7792 mapping, new_addr);
7793
84b67b27 7794 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
d1a3b737
MC		 7795 new_skb->len, base_flags,
7796 mss, vlan)) {
ba1142e4 7797 tg3_tx_skb_unmap(tnapi, save_entry, -1);
d1a3b737
MC		 7798 dev_kfree_skb(new_skb);
7799 ret = -1;
7800 }
f4188d8a 7801 }
1da177e4
LT		 7802 }
7803
7804 dev_kfree_skb(skb);
f7ff1987 7805 *pskb = new_skb;
c58ec932 7806 return ret;
1da177e4
LT		 7807}
7808
2ffcc981 7809static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
52c0fd83
MC		 7810
7811/* Use GSO to workaround a rare TSO bug that may be triggered when the
7812 * TSO header is greater than 80 bytes.
7813 */
7814static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
7815{
7816 struct sk_buff *segs, *nskb;
f3f3f27e 7817 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 7818
7819 /* Estimate the number of fragments in the worst case */
f3f3f27e 7820 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 7821 netif_stop_queue(tp->dev);
f65aac16
MC		 7822
7823 /* netif_tx_stop_queue() must be done before checking
7824 * checking tx index in tg3_tx_avail() below, because in
7825 * tg3_tx(), we update tx index before checking for
7826 * netif_tx_queue_stopped().
7827 */
7828 smp_mb();
f3f3f27e 7829 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 7830 return NETDEV_TX_BUSY;
7831
7832 netif_wake_queue(tp->dev);
52c0fd83
MC		 7833 }
7834
7835 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 7836 if (IS_ERR(segs))
52c0fd83
MC		 7837 goto tg3_tso_bug_end;
7838
7839 do {
7840 nskb = segs;
7841 segs = segs->next;
7842 nskb->next = NULL;
2ffcc981 7843 tg3_start_xmit(nskb, tp->dev);
52c0fd83
MC		 7844 } while (segs);
7845
7846tg3_tso_bug_end:
7847 dev_kfree_skb(skb);
7848
7849 return NETDEV_TX_OK;
7850}
52c0fd83 7851
5a6f3074 7852/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
63c3a66f 7853 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
5a6f3074 7854 */
2ffcc981 7855static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 7856{
7857 struct tg3 *tp = netdev_priv(dev);
92cd3a17 7858 u32 len, entry, base_flags, mss, vlan = 0;
84b67b27 7859 u32 budget;
432aa7ed 7860 int i = -1, would_hit_hwbug;
90079ce8 7861 dma_addr_t mapping;
24f4efd4
MC		 7862 struct tg3_napi *tnapi;
7863 struct netdev_queue *txq;
432aa7ed 7864 unsigned int last;
f4188d8a 7865
24f4efd4
MC		 7866 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7867 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
63c3a66f 7868 if (tg3_flag(tp, ENABLE_TSS))
24f4efd4 7869 tnapi++;
1da177e4 7870
84b67b27
MC		 7871 budget = tg3_tx_avail(tnapi);
7872
00b70504 7873 /* We are running in BH disabled context with netif_tx_lock
bea3348e 7874 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 7875 * interrupt. Furthermore, IRQ processing runs lockless so we have
7876 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 7877 */
84b67b27 7878 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 7879 if (!netif_tx_queue_stopped(txq)) {
7880 netif_tx_stop_queue(txq);
1f064a87
SH		 7881
7882 /* This is a hard error, log it. */
5129c3a3
MC		 7883 netdev_err(dev,
7884 "BUG! Tx Ring full when queue awake!\n");
1f064a87 7885 }
1da177e4
LT		 7886 return NETDEV_TX_BUSY;
7887 }
7888
f3f3f27e 7889 entry = tnapi->tx_prod;
1da177e4 7890 base_flags = 0;
84fa7933 7891 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 7892 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 7893
be98da6a
MC		 7894 mss = skb_shinfo(skb)->gso_size;
7895 if (mss) {
eddc9ec5 7896 struct iphdr *iph;
34195c3d 7897 u32 tcp_opt_len, hdr_len;
1da177e4
LT		 7898
7899 if (skb_header_cloned(skb) &&
48855432
ED		 7900 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7901 goto drop;
1da177e4 7902
34195c3d 7903 iph = ip_hdr(skb);
ab6a5bb6 7904 tcp_opt_len = tcp_optlen(skb);
1da177e4 7905
a5a11955 7906 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
34195c3d 7907
a5a11955 7908 if (!skb_is_gso_v6(skb)) {
34195c3d
MC		 7909 iph->check = 0;
7910 iph->tot_len = htons(mss + hdr_len);
7911 }
7912
52c0fd83 7913 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
63c3a66f 7914 tg3_flag(tp, TSO_BUG))
de6f31eb 7915 return tg3_tso_bug(tp, skb);
52c0fd83 7916
1da177e4
LT		 7917 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7918 TXD_FLAG_CPU_POST_DMA);
7919
63c3a66f
JP		 7920 if (tg3_flag(tp, HW_TSO_1) ||
7921 tg3_flag(tp, HW_TSO_2) ||
7922 tg3_flag(tp, HW_TSO_3)) {
aa8223c7 7923 tcp_hdr(skb)->check = 0;
1da177e4 7924 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 7925 } else
7926 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7927 iph->daddr, 0,
7928 IPPROTO_TCP,
7929 0);
1da177e4 7930
63c3a66f 7931 if (tg3_flag(tp, HW_TSO_3)) {
615774fe
MC		 7932 mss |= (hdr_len & 0xc) << 12;
7933 if (hdr_len & 0x10)
7934 base_flags |= 0x00000010;
7935 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 7936 } else if (tg3_flag(tp, HW_TSO_2))
92c6b8d1 7937 mss |= hdr_len << 9;
63c3a66f 7938 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 7939 tg3_asic_rev(tp) == ASIC_REV_5705) {
eddc9ec5 7940 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7941 int tsflags;
7942
eddc9ec5 7943 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7944 mss |= (tsflags << 11);
7945 }
7946 } else {
eddc9ec5 7947 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7948 int tsflags;
7949
eddc9ec5 7950 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7951 base_flags |= tsflags << 12;
7952 }
7953 }
7954 }
bf933c80 7955
93a700a9
MC		 7956 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7957 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7958 base_flags |= TXD_FLAG_JMB_PKT;
7959
92cd3a17
MC		 7960 if (vlan_tx_tag_present(skb)) {
7961 base_flags |= TXD_FLAG_VLAN;
7962 vlan = vlan_tx_tag_get(skb);
7963 }
1da177e4 7964
fb4ce8ad
MC		 7965 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
7966 tg3_flag(tp, TX_TSTAMP_EN)) {
7967 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7968 base_flags |= TXD_FLAG_HWTSTAMP;
7969 }
7970
f4188d8a
AD		 7971 len = skb_headlen(skb);
7972
7973 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
48855432
ED		 7974 if (pci_dma_mapping_error(tp->pdev, mapping))
7975 goto drop;
7976
90079ce8 7977
f3f3f27e 7978 tnapi->tx_buffers[entry].skb = skb;
4e5e4f0d 7979 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 7980
7981 would_hit_hwbug = 0;
7982
63c3a66f 7983 if (tg3_flag(tp, 5701_DMA_BUG))
c58ec932 7984 would_hit_hwbug = 1;
1da177e4 7985
84b67b27 7986 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
d1a3b737 7987 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
ba1142e4 7988 mss, vlan)) {
d1a3b737 7989 would_hit_hwbug = 1;
ba1142e4 7990 } else if (skb_shinfo(skb)->nr_frags > 0) {
92cd3a17
MC		 7991 u32 tmp_mss = mss;
7992
7993 if (!tg3_flag(tp, HW_TSO_1) &&
7994 !tg3_flag(tp, HW_TSO_2) &&
7995 !tg3_flag(tp, HW_TSO_3))
7996 tmp_mss = 0;
7997
c5665a53
MC		 7998 /* Now loop through additional data
7999 * fragments, and queue them.
8000 */
1da177e4
LT		 8001 last = skb_shinfo(skb)->nr_frags - 1;
8002 for (i = 0; i <= last; i++) {
8003 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8004
9e903e08 8005 len = skb_frag_size(frag);
dc234d0b 8006 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
5d6bcdfe 8007 len, DMA_TO_DEVICE);
1da177e4 8008
f3f3f27e 8009 tnapi->tx_buffers[entry].skb = NULL;
4e5e4f0d 8010 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
f4188d8a 8011 mapping);
5d6bcdfe 8012 if (dma_mapping_error(&tp->pdev->dev, mapping))
f4188d8a 8013 goto dma_error;
1da177e4 8014
b9e45482
MC		 8015 if (!budget ||
8016 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
84b67b27
MC		 8017 len, base_flags |
8018 ((i == last) ? TXD_FLAG_END : 0),
b9e45482 8019 tmp_mss, vlan)) {
72f2afb8 8020 would_hit_hwbug = 1;
b9e45482
MC		 8021 break;
8022 }
1da177e4
LT		 8023 }
8024 }
8025
8026 if (would_hit_hwbug) {
0d681b27 8027 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
1da177e4
LT		 8028
8029 /* If the workaround fails due to memory/mapping
8030 * failure, silently drop this packet.
8031 */
84b67b27
MC		 8032 entry = tnapi->tx_prod;
8033 budget = tg3_tx_avail(tnapi);
f7ff1987 8034 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
84b67b27 8035 base_flags, mss, vlan))
48855432 8036 goto drop_nofree;
1da177e4
LT		 8037 }
8038
d515b450 8039 skb_tx_timestamp(skb);
5cb917bc 8040 netdev_tx_sent_queue(txq, skb->len);
d515b450 8041
6541b806
MC		 8042 /* Sync BD data before updating mailbox */
8043 wmb();
8044
1da177e4 8045 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 8046 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 8047
f3f3f27e
MC		 8048 tnapi->tx_prod = entry;
8049 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 8050 netif_tx_stop_queue(txq);
f65aac16
MC		 8051
8052 /* netif_tx_stop_queue() must be done before checking
8053 * checking tx index in tg3_tx_avail() below, because in
8054 * tg3_tx(), we update tx index before checking for
8055 * netif_tx_queue_stopped().
8056 */
8057 smp_mb();
f3f3f27e 8058 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 8059 netif_tx_wake_queue(txq);
51b91468 8060 }
1da177e4 8061
cdd0db05 8062 mmiowb();
1da177e4 8063 return NETDEV_TX_OK;
f4188d8a
AD		 8064
8065dma_error:
ba1142e4 8066 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
432aa7ed 8067 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
48855432
ED		 8068drop:
8069 dev_kfree_skb(skb);
8070drop_nofree:
8071 tp->tx_dropped++;
f4188d8a 8072 return NETDEV_TX_OK;
1da177e4
LT		 8073}
8074
6e01b20b
MC		 8075static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8076{
8077 if (enable) {
8078 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8079 MAC_MODE_PORT_MODE_MASK);
8080
8081 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8082
8083 if (!tg3_flag(tp, 5705_PLUS))
8084 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8085
8086 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8087 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8088 else
8089 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8090 } else {
8091 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8092
8093 if (tg3_flag(tp, 5705_PLUS) ||
8094 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
4153577a 8095 tg3_asic_rev(tp) == ASIC_REV_5700)
6e01b20b
MC		 8096 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8097 }
8098
8099 tw32(MAC_MODE, tp->mac_mode);
8100 udelay(40);
8101}
8102
941ec90f 8103static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
5e5a7f37 8104{
941ec90f 8105 u32 val, bmcr, mac_mode, ptest = 0;
5e5a7f37
MC		 8106
8107 tg3_phy_toggle_apd(tp, false);
953c96e0 8108 tg3_phy_toggle_automdix(tp, false);
5e5a7f37 8109
941ec90f
MC		 8110 if (extlpbk && tg3_phy_set_extloopbk(tp))
8111 return -EIO;
8112
8113 bmcr = BMCR_FULLDPLX;
5e5a7f37
MC		 8114 switch (speed) {
8115 case SPEED_10:
8116 break;
8117 case SPEED_100:
8118 bmcr |= BMCR_SPEED100;
8119 break;
8120 case SPEED_1000:
8121 default:
8122 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8123 speed = SPEED_100;
8124 bmcr |= BMCR_SPEED100;
8125 } else {
8126 speed = SPEED_1000;
8127 bmcr |= BMCR_SPEED1000;
8128 }
8129 }
8130
941ec90f
MC		 8131 if (extlpbk) {
8132 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8133 tg3_readphy(tp, MII_CTRL1000, &val);
8134 val |= CTL1000_AS_MASTER |
8135 CTL1000_ENABLE_MASTER;
8136 tg3_writephy(tp, MII_CTRL1000, val);
8137 } else {
8138 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8139 MII_TG3_FET_PTEST_TRIM_2;
8140 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8141 }
8142 } else
8143 bmcr |= BMCR_LOOPBACK;
8144
5e5a7f37
MC		 8145 tg3_writephy(tp, MII_BMCR, bmcr);
8146
8147 /* The write needs to be flushed for the FETs */
8148 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8149 tg3_readphy(tp, MII_BMCR, &bmcr);
8150
8151 udelay(40);
8152
8153 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a 8154 tg3_asic_rev(tp) == ASIC_REV_5785) {
941ec90f 8155 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
5e5a7f37
MC		 8156 MII_TG3_FET_PTEST_FRC_TX_LINK |
8157 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8158
8159 /* The write needs to be flushed for the AC131 */
8160 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8161 }
8162
8163 /* Reset to prevent losing 1st rx packet intermittently */
8164 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8165 tg3_flag(tp, 5780_CLASS)) {
8166 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8167 udelay(10);
8168 tw32_f(MAC_RX_MODE, tp->rx_mode);
8169 }
8170
8171 mac_mode = tp->mac_mode &
8172 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8173 if (speed == SPEED_1000)
8174 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8175 else
8176 mac_mode |= MAC_MODE_PORT_MODE_MII;
8177
4153577a 8178 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5e5a7f37
MC		 8179 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8180
8181 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8182 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8183 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8184 mac_mode |= MAC_MODE_LINK_POLARITY;
8185
8186 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8187 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8188 }
8189
8190 tw32(MAC_MODE, mac_mode);
8191 udelay(40);
941ec90f
MC		 8192
8193 return 0;
5e5a7f37
MC		 8194}
8195
c8f44aff 8196static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
06c03c02
MB		 8197{
8198 struct tg3 *tp = netdev_priv(dev);
8199
8200 if (features & NETIF_F_LOOPBACK) {
8201 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8202 return;
8203
06c03c02 8204 spin_lock_bh(&tp->lock);
6e01b20b 8205 tg3_mac_loopback(tp, true);
06c03c02
MB		 8206 netif_carrier_on(tp->dev);
8207 spin_unlock_bh(&tp->lock);
8208 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8209 } else {
8210 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8211 return;
8212
06c03c02 8213 spin_lock_bh(&tp->lock);
6e01b20b 8214 tg3_mac_loopback(tp, false);
06c03c02 8215 /* Force link status check */
953c96e0 8216 tg3_setup_phy(tp, true);
06c03c02
MB		 8217 spin_unlock_bh(&tp->lock);
8218 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8219 }
8220}
8221
c8f44aff
MM		 8222static netdev_features_t tg3_fix_features(struct net_device *dev,
8223 netdev_features_t features)
dc668910
MM		 8224{
8225 struct tg3 *tp = netdev_priv(dev);
8226
63c3a66f 8227 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
dc668910
MM		 8228 features &= ~NETIF_F_ALL_TSO;
8229
8230 return features;
8231}
8232
c8f44aff 8233static int tg3_set_features(struct net_device *dev, netdev_features_t features)
06c03c02 8234{
c8f44aff 8235 netdev_features_t changed = dev->features ^ features;
06c03c02
MB		 8236
8237 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8238 tg3_set_loopback(dev, features);
8239
8240 return 0;
8241}
8242
21f581a5
MC		 8243static void tg3_rx_prodring_free(struct tg3 *tp,
8244 struct tg3_rx_prodring_set *tpr)
1da177e4 8245{
1da177e4
LT		 8246 int i;
8247
8fea32b9 8248 if (tpr != &tp->napi[0].prodring) {
b196c7e4 8249 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
2c49a44d 8250 i = (i + 1) & tp->rx_std_ring_mask)
9205fd9c 8251 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
b196c7e4
MC		 8252 tp->rx_pkt_map_sz);
8253
63c3a66f 8254 if (tg3_flag(tp, JUMBO_CAPABLE)) {
b196c7e4
MC		 8255 for (i = tpr->rx_jmb_cons_idx;
8256 i != tpr->rx_jmb_prod_idx;
2c49a44d 8257 i = (i + 1) & tp->rx_jmb_ring_mask) {
9205fd9c 8258 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
b196c7e4
MC		 8259 TG3_RX_JMB_MAP_SZ);
8260 }
8261 }
8262
2b2cdb65 8263 return;
b196c7e4 8264 }
1da177e4 8265
2c49a44d 8266 for (i = 0; i <= tp->rx_std_ring_mask; i++)
9205fd9c 8267 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
2b2cdb65 8268 tp->rx_pkt_map_sz);
1da177e4 8269
63c3a66f 8270 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8271 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
9205fd9c 8272 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
2b2cdb65 8273 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 8274 }
8275}
8276
c6cdf436 8277/* Initialize rx rings for packet processing.
1da177e4
LT		 8278 *
8279 * The chip has been shut down and the driver detached from
8280 * the networking, so no interrupts or new tx packets will
8281 * end up in the driver. tp->{tx,}lock are held and thus
8282 * we may not sleep.
8283 */
21f581a5
MC		 8284static int tg3_rx_prodring_alloc(struct tg3 *tp,
8285 struct tg3_rx_prodring_set *tpr)
1da177e4 8286{
287be12e 8287 u32 i, rx_pkt_dma_sz;
1da177e4 8288
b196c7e4
MC		 8289 tpr->rx_std_cons_idx = 0;
8290 tpr->rx_std_prod_idx = 0;
8291 tpr->rx_jmb_cons_idx = 0;
8292 tpr->rx_jmb_prod_idx = 0;
8293
8fea32b9 8294 if (tpr != &tp->napi[0].prodring) {
2c49a44d
MC		 8295 memset(&tpr->rx_std_buffers[0], 0,
8296 TG3_RX_STD_BUFF_RING_SIZE(tp));
48035728 8297 if (tpr->rx_jmb_buffers)
2b2cdb65 8298 memset(&tpr->rx_jmb_buffers[0], 0,
2c49a44d 8299 TG3_RX_JMB_BUFF_RING_SIZE(tp));
2b2cdb65
MC		 8300 goto done;
8301 }
8302
1da177e4 8303 /* Zero out all descriptors. */
2c49a44d 8304 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
1da177e4 8305
287be12e 8306 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
63c3a66f 8307 if (tg3_flag(tp, 5780_CLASS) &&
287be12e
MC		 8308 tp->dev->mtu > ETH_DATA_LEN)
8309 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8310 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 8311
1da177e4
LT		 8312 /* Initialize invariants of the rings, we only set this
8313 * stuff once. This works because the card does not
8314 * write into the rx buffer posting rings.
8315 */
2c49a44d 8316 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
1da177e4
LT		 8317 struct tg3_rx_buffer_desc *rxd;
8318
21f581a5 8319 rxd = &tpr->rx_std[i];
287be12e 8320 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 8321 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8322 rxd->opaque = (RXD_OPAQUE_RING_STD |
8323 (i << RXD_OPAQUE_INDEX_SHIFT));
8324 }
8325
1da177e4
LT		 8326 /* Now allocate fresh SKBs for each rx ring. */
8327 for (i = 0; i < tp->rx_pending; i++) {
8d4057a9
ED		 8328 unsigned int frag_size;
8329
8330 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8331 &frag_size) < 0) {
5129c3a3
MC		 8332 netdev_warn(tp->dev,
8333 "Using a smaller RX standard ring. Only "
8334 "%d out of %d buffers were allocated "
8335 "successfully\n", i, tp->rx_pending);
32d8c572 8336 if (i == 0)
cf7a7298 8337 goto initfail;
32d8c572 8338 tp->rx_pending = i;
1da177e4 8339 break;
32d8c572 8340 }
1da177e4
LT		 8341 }
8342
63c3a66f 8343 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
cf7a7298
MC		 8344 goto done;
8345
2c49a44d 8346 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
cf7a7298 8347
63c3a66f 8348 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
0d86df80 8349 goto done;
cf7a7298 8350
2c49a44d 8351 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
0d86df80
MC		 8352 struct tg3_rx_buffer_desc *rxd;
8353
8354 rxd = &tpr->rx_jmb[i].std;
8355 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8356 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8357 RXD_FLAG_JUMBO;
8358 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8359 (i << RXD_OPAQUE_INDEX_SHIFT));
8360 }
8361
8362 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8d4057a9
ED		 8363 unsigned int frag_size;
8364
8365 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8366 &frag_size) < 0) {
5129c3a3
MC		 8367 netdev_warn(tp->dev,
8368 "Using a smaller RX jumbo ring. Only %d "
8369 "out of %d buffers were allocated "
8370 "successfully\n", i, tp->rx_jumbo_pending);
0d86df80
MC		 8371 if (i == 0)
8372 goto initfail;
8373 tp->rx_jumbo_pending = i;
8374 break;
1da177e4
LT		 8375 }
8376 }
cf7a7298
MC		 8377
8378done:
32d8c572 8379 return 0;
cf7a7298
MC		 8380
8381initfail:
21f581a5 8382 tg3_rx_prodring_free(tp, tpr);
cf7a7298 8383 return -ENOMEM;
1da177e4
LT		 8384}
8385
21f581a5
MC		 8386static void tg3_rx_prodring_fini(struct tg3 *tp,
8387 struct tg3_rx_prodring_set *tpr)
1da177e4 8388{
21f581a5
MC		 8389 kfree(tpr->rx_std_buffers);
8390 tpr->rx_std_buffers = NULL;
8391 kfree(tpr->rx_jmb_buffers);
8392 tpr->rx_jmb_buffers = NULL;
8393 if (tpr->rx_std) {
4bae65c8
MC		 8394 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8395 tpr->rx_std, tpr->rx_std_mapping);
21f581a5 8396 tpr->rx_std = NULL;
1da177e4 8397 }
21f581a5 8398 if (tpr->rx_jmb) {
4bae65c8
MC		 8399 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8400 tpr->rx_jmb, tpr->rx_jmb_mapping);
21f581a5 8401 tpr->rx_jmb = NULL;
1da177e4 8402 }
cf7a7298
MC		 8403}
8404
21f581a5
MC		 8405static int tg3_rx_prodring_init(struct tg3 *tp,
8406 struct tg3_rx_prodring_set *tpr)
cf7a7298 8407{
2c49a44d
MC		 8408 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8409 GFP_KERNEL);
21f581a5 8410 if (!tpr->rx_std_buffers)
cf7a7298
MC		 8411 return -ENOMEM;
8412
4bae65c8
MC		 8413 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8414 TG3_RX_STD_RING_BYTES(tp),
8415 &tpr->rx_std_mapping,
8416 GFP_KERNEL);
21f581a5 8417 if (!tpr->rx_std)
cf7a7298
MC		 8418 goto err_out;
8419
63c3a66f 8420 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8421 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
21f581a5
MC		 8422 GFP_KERNEL);
8423 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 8424 goto err_out;
8425
4bae65c8
MC		 8426 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8427 TG3_RX_JMB_RING_BYTES(tp),
8428 &tpr->rx_jmb_mapping,
8429 GFP_KERNEL);
21f581a5 8430 if (!tpr->rx_jmb)
cf7a7298
MC		 8431 goto err_out;
8432 }
8433
8434 return 0;
8435
8436err_out:
21f581a5 8437 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 8438 return -ENOMEM;
8439}
8440
8441/* Free up pending packets in all rx/tx rings.
8442 *
8443 * The chip has been shut down and the driver detached from
8444 * the networking, so no interrupts or new tx packets will
8445 * end up in the driver. tp->{tx,}lock is not held and we are not
8446 * in an interrupt context and thus may sleep.
8447 */
8448static void tg3_free_rings(struct tg3 *tp)
8449{
f77a6a8e 8450 int i, j;
cf7a7298 8451
f77a6a8e
MC		 8452 for (j = 0; j < tp->irq_cnt; j++) {
8453 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 8454
8fea32b9 8455 tg3_rx_prodring_free(tp, &tnapi->prodring);
b28f6428 8456
0c1d0e2b
MC		 8457 if (!tnapi->tx_buffers)
8458 continue;
8459
0d681b27
MC		 8460 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8461 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
cf7a7298 8462
0d681b27 8463 if (!skb)
f77a6a8e 8464 continue;
cf7a7298 8465
ba1142e4
MC		 8466 tg3_tx_skb_unmap(tnapi, i,
8467 skb_shinfo(skb)->nr_frags - 1);
f77a6a8e
MC		 8468
8469 dev_kfree_skb_any(skb);
8470 }
5cb917bc 8471 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
2b2cdb65 8472 }
cf7a7298
MC		 8473}
8474
8475/* Initialize tx/rx rings for packet processing.
8476 *
8477 * The chip has been shut down and the driver detached from
8478 * the networking, so no interrupts or new tx packets will
8479 * end up in the driver. tp->{tx,}lock are held and thus
8480 * we may not sleep.
8481 */
8482static int tg3_init_rings(struct tg3 *tp)
8483{
f77a6a8e 8484 int i;
72334482 8485
cf7a7298
MC		 8486 /* Free up all the SKBs. */
8487 tg3_free_rings(tp);
8488
f77a6a8e
MC		 8489 for (i = 0; i < tp->irq_cnt; i++) {
8490 struct tg3_napi *tnapi = &tp->napi[i];
8491
8492 tnapi->last_tag = 0;
8493 tnapi->last_irq_tag = 0;
8494 tnapi->hw_status->status = 0;
8495 tnapi->hw_status->status_tag = 0;
8496 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 8497
f77a6a8e
MC		 8498 tnapi->tx_prod = 0;
8499 tnapi->tx_cons = 0;
0c1d0e2b
MC		 8500 if (tnapi->tx_ring)
8501 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 8502
8503 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 8504 if (tnapi->rx_rcb)
8505 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 8506
8fea32b9 8507 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
e4af1af9 8508 tg3_free_rings(tp);
2b2cdb65 8509 return -ENOMEM;
e4af1af9 8510 }
f77a6a8e 8511 }
72334482 8512
2b2cdb65 8513 return 0;
cf7a7298
MC		 8514}
8515
49a359e3 8516static void tg3_mem_tx_release(struct tg3 *tp)
cf7a7298 8517{
f77a6a8e 8518 int i;
898a56f8 8519
49a359e3 8520 for (i = 0; i < tp->irq_max; i++) {
f77a6a8e
MC		 8521 struct tg3_napi *tnapi = &tp->napi[i];
8522
8523 if (tnapi->tx_ring) {
4bae65c8 8524 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
f77a6a8e
MC		 8525 tnapi->tx_ring, tnapi->tx_desc_mapping);
8526 tnapi->tx_ring = NULL;
8527 }
8528
8529 kfree(tnapi->tx_buffers);
8530 tnapi->tx_buffers = NULL;
49a359e3
MC		 8531 }
8532}
f77a6a8e 8533
49a359e3
MC		 8534static int tg3_mem_tx_acquire(struct tg3 *tp)
8535{
8536 int i;
8537 struct tg3_napi *tnapi = &tp->napi[0];
8538
8539 /* If multivector TSS is enabled, vector 0 does not handle
8540 * tx interrupts. Don't allocate any resources for it.
8541 */
8542 if (tg3_flag(tp, ENABLE_TSS))
8543 tnapi++;
8544
8545 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8546 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8547 TG3_TX_RING_SIZE, GFP_KERNEL);
8548 if (!tnapi->tx_buffers)
8549 goto err_out;
8550
8551 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8552 TG3_TX_RING_BYTES,
8553 &tnapi->tx_desc_mapping,
8554 GFP_KERNEL);
8555 if (!tnapi->tx_ring)
8556 goto err_out;
8557 }
8558
8559 return 0;
8560
8561err_out:
8562 tg3_mem_tx_release(tp);
8563 return -ENOMEM;
8564}
8565
8566static void tg3_mem_rx_release(struct tg3 *tp)
8567{
8568 int i;
8569
8570 for (i = 0; i < tp->irq_max; i++) {
8571 struct tg3_napi *tnapi = &tp->napi[i];
f77a6a8e 8572
8fea32b9
MC		 8573 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8574
49a359e3
MC		 8575 if (!tnapi->rx_rcb)
8576 continue;
8577
8578 dma_free_coherent(&tp->pdev->dev,
8579 TG3_RX_RCB_RING_BYTES(tp),
8580 tnapi->rx_rcb,
8581 tnapi->rx_rcb_mapping);
8582 tnapi->rx_rcb = NULL;
8583 }
8584}
8585
8586static int tg3_mem_rx_acquire(struct tg3 *tp)
8587{
8588 unsigned int i, limit;
8589
8590 limit = tp->rxq_cnt;
8591
8592 /* If RSS is enabled, we need a (dummy) producer ring
8593 * set on vector zero. This is the true hw prodring.
8594 */
8595 if (tg3_flag(tp, ENABLE_RSS))
8596 limit++;
8597
8598 for (i = 0; i < limit; i++) {
8599 struct tg3_napi *tnapi = &tp->napi[i];
8600
8601 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8602 goto err_out;
8603
8604 /* If multivector RSS is enabled, vector 0
8605 * does not handle rx or tx interrupts.
8606 * Don't allocate any resources for it.
8607 */
8608 if (!i && tg3_flag(tp, ENABLE_RSS))
8609 continue;
8610
ede23fa8
JP		 8611 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8612 TG3_RX_RCB_RING_BYTES(tp),
8613 &tnapi->rx_rcb_mapping,
8614 GFP_KERNEL);
49a359e3
MC		 8615 if (!tnapi->rx_rcb)
8616 goto err_out;
49a359e3
MC		 8617 }
8618
8619 return 0;
8620
8621err_out:
8622 tg3_mem_rx_release(tp);
8623 return -ENOMEM;
8624}
8625
8626/*
8627 * Must not be invoked with interrupt sources disabled and
8628 * the hardware shutdown down.
8629 */
8630static void tg3_free_consistent(struct tg3 *tp)
8631{
8632 int i;
8633
8634 for (i = 0; i < tp->irq_cnt; i++) {
8635 struct tg3_napi *tnapi = &tp->napi[i];
8636
f77a6a8e 8637 if (tnapi->hw_status) {
4bae65c8
MC		 8638 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8639 tnapi->hw_status,
8640 tnapi->status_mapping);
f77a6a8e
MC		 8641 tnapi->hw_status = NULL;
8642 }
1da177e4 8643 }
f77a6a8e 8644
49a359e3
MC		 8645 tg3_mem_rx_release(tp);
8646 tg3_mem_tx_release(tp);
8647
1da177e4 8648 if (tp->hw_stats) {
4bae65c8
MC		 8649 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8650 tp->hw_stats, tp->stats_mapping);
1da177e4
LT		 8651 tp->hw_stats = NULL;
8652 }
8653}
8654
8655/*
8656 * Must not be invoked with interrupt sources disabled and
8657 * the hardware shutdown down. Can sleep.
8658 */
8659static int tg3_alloc_consistent(struct tg3 *tp)
8660{
f77a6a8e 8661 int i;
898a56f8 8662
ede23fa8
JP		 8663 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8664 sizeof(struct tg3_hw_stats),
8665 &tp->stats_mapping, GFP_KERNEL);
f77a6a8e 8666 if (!tp->hw_stats)
1da177e4
LT		 8667 goto err_out;
8668
f77a6a8e
MC		 8669 for (i = 0; i < tp->irq_cnt; i++) {
8670 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 8671 struct tg3_hw_status *sblk;
1da177e4 8672
ede23fa8
JP		 8673 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8674 TG3_HW_STATUS_SIZE,
8675 &tnapi->status_mapping,
8676 GFP_KERNEL);
f77a6a8e
MC		 8677 if (!tnapi->hw_status)
8678 goto err_out;
898a56f8 8679
8d9d7cfc
MC		 8680 sblk = tnapi->hw_status;
8681
49a359e3 8682 if (tg3_flag(tp, ENABLE_RSS)) {
86449944 8683 u16 *prodptr = NULL;
8fea32b9 8684
49a359e3
MC		 8685 /*
8686 * When RSS is enabled, the status block format changes
8687 * slightly. The "rx_jumbo_consumer", "reserved",
8688 * and "rx_mini_consumer" members get mapped to the
8689 * other three rx return ring producer indexes.
8690 */
8691 switch (i) {
8692 case 1:
8693 prodptr = &sblk->idx[0].rx_producer;
8694 break;
8695 case 2:
8696 prodptr = &sblk->rx_jumbo_consumer;
8697 break;
8698 case 3:
8699 prodptr = &sblk->reserved;
8700 break;
8701 case 4:
8702 prodptr = &sblk->rx_mini_consumer;
f891ea16
MC		 8703 break;
8704 }
49a359e3
MC		 8705 tnapi->rx_rcb_prod_idx = prodptr;
8706 } else {
8d9d7cfc 8707 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8d9d7cfc 8708 }
f77a6a8e 8709 }
1da177e4 8710
49a359e3
MC		 8711 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8712 goto err_out;
8713
1da177e4
LT		 8714 return 0;
8715
8716err_out:
8717 tg3_free_consistent(tp);
8718 return -ENOMEM;
8719}
8720
8721#define MAX_WAIT_CNT 1000
8722
8723/* To stop a block, clear the enable bit and poll till it
8724 * clears. tp->lock is held.
8725 */
953c96e0 8726static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
1da177e4
LT		 8727{
8728 unsigned int i;
8729 u32 val;
8730
63c3a66f 8731 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 8732 switch (ofs) {
8733 case RCVLSC_MODE:
8734 case DMAC_MODE:
8735 case MBFREE_MODE:
8736 case BUFMGR_MODE:
8737 case MEMARB_MODE:
8738 /* We can't enable/disable these bits of the
8739 * 5705/5750, just say success.
8740 */
8741 return 0;
8742
8743 default:
8744 break;
855e1111 8745 }
1da177e4
LT		 8746 }
8747
8748 val = tr32(ofs);
8749 val &= ~enable_bit;
8750 tw32_f(ofs, val);
8751
8752 for (i = 0; i < MAX_WAIT_CNT; i++) {
6d446ec3
GS		 8753 if (pci_channel_offline(tp->pdev)) {
8754 dev_err(&tp->pdev->dev,
8755 "tg3_stop_block device offline, "
8756 "ofs=%lx enable_bit=%x\n",
8757 ofs, enable_bit);
8758 return -ENODEV;
8759 }
8760
1da177e4
LT		 8761 udelay(100);
8762 val = tr32(ofs);
8763 if ((val & enable_bit) == 0)
8764 break;
8765 }
8766
b3b7d6be 8767 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 8768 dev_err(&tp->pdev->dev,
8769 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8770 ofs, enable_bit);
1da177e4
LT		 8771 return -ENODEV;
8772 }
8773
8774 return 0;
8775}
8776
8777/* tp->lock is held. */
953c96e0 8778static int tg3_abort_hw(struct tg3 *tp, bool silent)
1da177e4
LT		 8779{
8780 int i, err;
8781
8782 tg3_disable_ints(tp);
8783
6d446ec3
GS		 8784 if (pci_channel_offline(tp->pdev)) {
8785 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8786 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8787 err = -ENODEV;
8788 goto err_no_dev;
8789 }
8790
1da177e4
LT		 8791 tp->rx_mode &= ~RX_MODE_ENABLE;
8792 tw32_f(MAC_RX_MODE, tp->rx_mode);
8793 udelay(10);
8794
b3b7d6be
DM		 8795 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8796 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8797 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8798 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8799 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8800 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8801
8802 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8803 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8804 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8805 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8806 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8807 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8808 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 8809
8810 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8811 tw32_f(MAC_MODE, tp->mac_mode);
8812 udelay(40);
8813
8814 tp->tx_mode &= ~TX_MODE_ENABLE;
8815 tw32_f(MAC_TX_MODE, tp->tx_mode);
8816
8817 for (i = 0; i < MAX_WAIT_CNT; i++) {
8818 udelay(100);
8819 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8820 break;
8821 }
8822 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 8823 dev_err(&tp->pdev->dev,
8824 "%s timed out, TX_MODE_ENABLE will not clear "
8825 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 8826 err |= -ENODEV;
1da177e4
LT		 8827 }
8828
e6de8ad1 8829 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 8830 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8831 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 8832
8833 tw32(FTQ_RESET, 0xffffffff);
8834 tw32(FTQ_RESET, 0x00000000);
8835
b3b7d6be
DM		 8836 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8837 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 8838
6d446ec3 8839err_no_dev:
f77a6a8e
MC		 8840 for (i = 0; i < tp->irq_cnt; i++) {
8841 struct tg3_napi *tnapi = &tp->napi[i];
8842 if (tnapi->hw_status)
8843 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8844 }
1da177e4 8845
1da177e4
LT		 8846 return err;
8847}
8848
ee6a99b5
MC		 8849/* Save PCI command register before chip reset */
8850static void tg3_save_pci_state(struct tg3 *tp)
8851{
8a6eac90 8852 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 8853}
8854
8855/* Restore PCI state after chip reset */
8856static void tg3_restore_pci_state(struct tg3 *tp)
8857{
8858 u32 val;
8859
8860 /* Re-enable indirect register accesses. */
8861 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8862 tp->misc_host_ctrl);
8863
8864 /* Set MAX PCI retry to zero. */
8865 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4153577a 8866 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 8867 tg3_flag(tp, PCIX_MODE))
ee6a99b5 8868 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9 8869 /* Allow reads and writes to the APE register and memory space. */
63c3a66f 8870 if (tg3_flag(tp, ENABLE_APE))
0d3031d9 8871 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 8872 PCISTATE_ALLOW_APE_SHMEM_WR |
8873 PCISTATE_ALLOW_APE_PSPACE_WR;
ee6a99b5
MC		 8874 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8875
8a6eac90 8876 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 8877
2c55a3d0
MC		 8878 if (!tg3_flag(tp, PCI_EXPRESS)) {
8879 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8880 tp->pci_cacheline_sz);
8881 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8882 tp->pci_lat_timer);
114342f2 8883 }
5f5c51e3 8884
ee6a99b5 8885 /* Make sure PCI-X relaxed ordering bit is clear. */
63c3a66f 8886 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 8887 u16 pcix_cmd;
8888
8889 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8890 &pcix_cmd);
8891 pcix_cmd &= ~PCI_X_CMD_ERO;
8892 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8893 pcix_cmd);
8894 }
ee6a99b5 8895
63c3a66f 8896 if (tg3_flag(tp, 5780_CLASS)) {
ee6a99b5
MC		 8897
8898 /* Chip reset on 5780 will reset MSI enable bit,
8899 * so need to restore it.
8900 */
63c3a66f 8901 if (tg3_flag(tp, USING_MSI)) {
ee6a99b5
MC		 8902 u16 ctrl;
8903
8904 pci_read_config_word(tp->pdev,
8905 tp->msi_cap + PCI_MSI_FLAGS,
8906 &ctrl);
8907 pci_write_config_word(tp->pdev,
8908 tp->msi_cap + PCI_MSI_FLAGS,
8909 ctrl | PCI_MSI_FLAGS_ENABLE);
8910 val = tr32(MSGINT_MODE);
8911 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8912 }
8913 }
8914}
8915
1da177e4
LT		 8916/* tp->lock is held. */
8917static int tg3_chip_reset(struct tg3 *tp)
8918{
8919 u32 val;
1ee582d8 8920 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 8921 int i, err;
1da177e4 8922
f49639e6
DM		 8923 tg3_nvram_lock(tp);
8924
77b483f1
MC		 8925 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
8926
f49639e6
DM		 8927 /* No matching tg3_nvram_unlock() after this because
8928 * chip reset below will undo the nvram lock.
8929 */
8930 tp->nvram_lock_cnt = 0;
1da177e4 8931
ee6a99b5
MC		 8932 /* GRC_MISC_CFG core clock reset will clear the memory
8933 * enable bit in PCI register 4 and the MSI enable bit
8934 * on some chips, so we save relevant registers here.
8935 */
8936 tg3_save_pci_state(tp);
8937
4153577a 8938 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
63c3a66f 8939 tg3_flag(tp, 5755_PLUS))
d9ab5ad1
MC		 8940 tw32(GRC_FASTBOOT_PC, 0);
8941
1da177e4
LT		 8942 /*
8943 * We must avoid the readl() that normally takes place.
8944 * It locks machines, causes machine checks, and other
8945 * fun things. So, temporarily disable the 5701
8946 * hardware workaround, while we do the reset.
8947 */
1ee582d8
MC		 8948 write_op = tp->write32;
8949 if (write_op == tg3_write_flush_reg32)
8950 tp->write32 = tg3_write32;
1da177e4 8951
d18edcb2
MC		 8952 /* Prevent the irq handler from reading or writing PCI registers
8953 * during chip reset when the memory enable bit in the PCI command
8954 * register may be cleared. The chip does not generate interrupt
8955 * at this time, but the irq handler may still be called due to irq
8956 * sharing or irqpoll.
8957 */
63c3a66f 8958 tg3_flag_set(tp, CHIP_RESETTING);
f77a6a8e
MC		 8959 for (i = 0; i < tp->irq_cnt; i++) {
8960 struct tg3_napi *tnapi = &tp->napi[i];
8961 if (tnapi->hw_status) {
8962 tnapi->hw_status->status = 0;
8963 tnapi->hw_status->status_tag = 0;
8964 }
8965 tnapi->last_tag = 0;
8966 tnapi->last_irq_tag = 0;
b8fa2f3a 8967 }
d18edcb2 8968 smp_mb();
4f125f42
MC		 8969
8970 for (i = 0; i < tp->irq_cnt; i++)
8971 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 8972
4153577a 8973 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
255ca311
MC		 8974 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8975 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8976 }
8977
1da177e4
LT		 8978 /* do the reset */
8979 val = GRC_MISC_CFG_CORECLK_RESET;
8980
63c3a66f 8981 if (tg3_flag(tp, PCI_EXPRESS)) {
88075d91 8982 /* Force PCIe 1.0a mode */
4153577a 8983 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 8984 !tg3_flag(tp, 57765_PLUS) &&
88075d91
MC		 8985 tr32(TG3_PCIE_PHY_TSTCTL) ==
8986 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
8987 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
8988
4153577a 8989 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
1da177e4
LT		 8990 tw32(GRC_MISC_CFG, (1 << 29));
8991 val |= (1 << 29);
8992 }
8993 }
8994
4153577a 8995 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 8996 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
8997 tw32(GRC_VCPU_EXT_CTRL,
8998 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
8999 }
9000
f37500d3 9001 /* Manage gphy power for all CPMU absent PCIe devices. */
63c3a66f 9002 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
1da177e4 9003 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
f37500d3 9004
1da177e4
LT		 9005 tw32(GRC_MISC_CFG, val);
9006
1ee582d8
MC		 9007 /* restore 5701 hardware bug workaround write method */
9008 tp->write32 = write_op;
1da177e4
LT		 9009
9010 /* Unfortunately, we have to delay before the PCI read back.
9011 * Some 575X chips even will not respond to a PCI cfg access
9012 * when the reset command is given to the chip.
9013 *
9014 * How do these hardware designers expect things to work
9015 * properly if the PCI write is posted for a long period
9016 * of time? It is always necessary to have some method by
9017 * which a register read back can occur to push the write
9018 * out which does the reset.
9019 *
9020 * For most tg3 variants the trick below was working.
9021 * Ho hum...
9022 */
9023 udelay(120);
9024
9025 /* Flush PCI posted writes. The normal MMIO registers
9026 * are inaccessible at this time so this is the only
9027 * way to make this reliably (actually, this is no longer
9028 * the case, see above). I tried to use indirect
9029 * register read/write but this upset some 5701 variants.
9030 */
9031 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9032
9033 udelay(120);
9034
0f49bfbd 9035 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
e7126997
MC		 9036 u16 val16;
9037
4153577a 9038 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
86449944 9039 int j;
1da177e4
LT		 9040 u32 cfg_val;
9041
9042 /* Wait for link training to complete. */
86449944 9043 for (j = 0; j < 5000; j++)
1da177e4
LT		 9044 udelay(100);
9045
9046 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9047 pci_write_config_dword(tp->pdev, 0xc4,
9048 cfg_val | (1 << 15));
9049 }
5e7dfd0f 9050
e7126997 9051 /* Clear the "no snoop" and "relaxed ordering" bits. */
0f49bfbd 9052 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
e7126997
MC		 9053 /*
9054 * Older PCIe devices only support the 128 byte
9055 * MPS setting. Enforce the restriction.
5e7dfd0f 9056 */
63c3a66f 9057 if (!tg3_flag(tp, CPMU_PRESENT))
0f49bfbd
JL		 9058 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9059 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
5e7dfd0f 9060
5e7dfd0f 9061 /* Clear error status */
0f49bfbd 9062 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
5e7dfd0f
MC		 9063 PCI_EXP_DEVSTA_CED |
9064 PCI_EXP_DEVSTA_NFED |
9065 PCI_EXP_DEVSTA_FED |
9066 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 9067 }
9068
ee6a99b5 9069 tg3_restore_pci_state(tp);
1da177e4 9070
63c3a66f
JP		 9071 tg3_flag_clear(tp, CHIP_RESETTING);
9072 tg3_flag_clear(tp, ERROR_PROCESSED);
d18edcb2 9073
ee6a99b5 9074 val = 0;
63c3a66f 9075 if (tg3_flag(tp, 5780_CLASS))
4cf78e4f 9076 val = tr32(MEMARB_MODE);
ee6a99b5 9077 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4 9078
4153577a 9079 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
1da177e4
LT		 9080 tg3_stop_fw(tp);
9081 tw32(0x5000, 0x400);
9082 }
9083
7e6c63f0
HM		 9084 if (tg3_flag(tp, IS_SSB_CORE)) {
9085 /*
9086 * BCM4785: In order to avoid repercussions from using
9087 * potentially defective internal ROM, stop the Rx RISC CPU,
9088 * which is not required.
9089 */
9090 tg3_stop_fw(tp);
9091 tg3_halt_cpu(tp, RX_CPU_BASE);
9092 }
9093
fb03a43f
NS		 9094 err = tg3_poll_fw(tp);
9095 if (err)
9096 return err;
9097
1da177e4
LT		 9098 tw32(GRC_MODE, tp->grc_mode);
9099
4153577a 9100 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
ab0049b4 9101 val = tr32(0xc4);
1da177e4
LT		 9102
9103 tw32(0xc4, val | (1 << 15));
9104 }
9105
9106 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4153577a 9107 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4 9108 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4153577a 9109 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
1da177e4
LT		 9110 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9111 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9112 }
9113
f07e9af3 9114 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9e975cc2 9115 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
d2394e6b 9116 val = tp->mac_mode;
f07e9af3 9117 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9e975cc2 9118 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
d2394e6b 9119 val = tp->mac_mode;
1da177e4 9120 } else
d2394e6b
MC		 9121 val = 0;
9122
9123 tw32_f(MAC_MODE, val);
1da177e4
LT		 9124 udelay(40);
9125
77b483f1
MC		 9126 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9127
0a9140cf
MC		 9128 tg3_mdio_start(tp);
9129
63c3a66f 9130 if (tg3_flag(tp, PCI_EXPRESS) &&
4153577a
JP		 9131 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9132 tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9133 !tg3_flag(tp, 57765_PLUS)) {
ab0049b4 9134 val = tr32(0x7c00);
1da177e4
LT		 9135
9136 tw32(0x7c00, val | (1 << 25));
9137 }
9138
4153577a 9139 if (tg3_asic_rev(tp) == ASIC_REV_5720) {
d78b59f5
MC		 9140 val = tr32(TG3_CPMU_CLCK_ORIDE);
9141 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9142 }
9143
1da177e4 9144 /* Reprobe ASF enable state. */
63c3a66f 9145 tg3_flag_clear(tp, ENABLE_ASF);
942d1af0
NS		 9146 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9147 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9148
63c3a66f 9149 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
1da177e4
LT		 9150 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9151 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9152 u32 nic_cfg;
9153
9154 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9155 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f 9156 tg3_flag_set(tp, ENABLE_ASF);
4ba526ce 9157 tp->last_event_jiffies = jiffies;
63c3a66f
JP		 9158 if (tg3_flag(tp, 5750_PLUS))
9159 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
942d1af0
NS		 9160
9161 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9162 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9163 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9164 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9165 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
1da177e4
LT		 9166 }
9167 }
9168
9169 return 0;
9170}
9171
65ec698d
MC		 9172static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9173static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
92feeabf 9174
1da177e4 9175/* tp->lock is held. */
953c96e0 9176static int tg3_halt(struct tg3 *tp, int kind, bool silent)
1da177e4
LT		 9177{
9178 int err;
9179
9180 tg3_stop_fw(tp);
9181
944d980e 9182 tg3_write_sig_pre_reset(tp, kind);
1da177e4 9183
b3b7d6be 9184 tg3_abort_hw(tp, silent);
1da177e4
LT		 9185 err = tg3_chip_reset(tp);
9186
953c96e0 9187 __tg3_set_mac_addr(tp, false);
daba2a63 9188
944d980e
MC		 9189 tg3_write_sig_legacy(tp, kind);
9190 tg3_write_sig_post_reset(tp, kind);
1da177e4 9191
92feeabf
MC		 9192 if (tp->hw_stats) {
9193 /* Save the stats across chip resets... */
b4017c53 9194 tg3_get_nstats(tp, &tp->net_stats_prev);
92feeabf
MC		 9195 tg3_get_estats(tp, &tp->estats_prev);
9196
9197 /* And make sure the next sample is new data */
9198 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9199 }
9200
1da177e4
LT		 9201 if (err)
9202 return err;
9203
9204 return 0;
9205}
9206
1da177e4
LT		 9207static int tg3_set_mac_addr(struct net_device *dev, void *p)
9208{
9209 struct tg3 *tp = netdev_priv(dev);
9210 struct sockaddr *addr = p;
953c96e0
JP		 9211 int err = 0;
9212 bool skip_mac_1 = false;
1da177e4 9213
f9804ddb 9214 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 9215 return -EADDRNOTAVAIL;
f9804ddb 9216
1da177e4
LT		 9217 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9218
e75f7c90
MC		 9219 if (!netif_running(dev))
9220 return 0;
9221
63c3a66f 9222 if (tg3_flag(tp, ENABLE_ASF)) {
986e0aeb 9223 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 9224
986e0aeb
MC		 9225 addr0_high = tr32(MAC_ADDR_0_HIGH);
9226 addr0_low = tr32(MAC_ADDR_0_LOW);
9227 addr1_high = tr32(MAC_ADDR_1_HIGH);
9228 addr1_low = tr32(MAC_ADDR_1_LOW);
9229
9230 /* Skip MAC addr 1 if ASF is using it. */
9231 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9232 !(addr1_high == 0 && addr1_low == 0))
953c96e0 9233 skip_mac_1 = true;
58712ef9 9234 }
986e0aeb
MC		 9235 spin_lock_bh(&tp->lock);
9236 __tg3_set_mac_addr(tp, skip_mac_1);
9237 spin_unlock_bh(&tp->lock);
1da177e4 9238
b9ec6c1b 9239 return err;
1da177e4
LT		 9240}
9241
9242/* tp->lock is held. */
9243static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9244 dma_addr_t mapping, u32 maxlen_flags,
9245 u32 nic_addr)
9246{
9247 tg3_write_mem(tp,
9248 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9249 ((u64) mapping >> 32));
9250 tg3_write_mem(tp,
9251 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9252 ((u64) mapping & 0xffffffff));
9253 tg3_write_mem(tp,
9254 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9255 maxlen_flags);
9256
63c3a66f 9257 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 9258 tg3_write_mem(tp,
9259 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9260 nic_addr);
9261}
9262
a489b6d9
MC		 9263
9264static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 9265{
a489b6d9 9266 int i = 0;
b6080e12 9267
63c3a66f 9268 if (!tg3_flag(tp, ENABLE_TSS)) {
b6080e12
MC		 9269 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9270 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9271 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 9272 } else {
9273 tw32(HOSTCC_TXCOL_TICKS, 0);
9274 tw32(HOSTCC_TXMAX_FRAMES, 0);
9275 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
a489b6d9
MC		 9276
9277 for (; i < tp->txq_cnt; i++) {
9278 u32 reg;
9279
9280 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9281 tw32(reg, ec->tx_coalesce_usecs);
9282 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9283 tw32(reg, ec->tx_max_coalesced_frames);
9284 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9285 tw32(reg, ec->tx_max_coalesced_frames_irq);
9286 }
19cfaecc 9287 }
b6080e12 9288
a489b6d9
MC		 9289 for (; i < tp->irq_max - 1; i++) {
9290 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9291 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9292 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9293 }
9294}
9295
9296static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9297{
9298 int i = 0;
9299 u32 limit = tp->rxq_cnt;
9300
63c3a66f 9301 if (!tg3_flag(tp, ENABLE_RSS)) {
19cfaecc
MC		 9302 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9303 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9304 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
a489b6d9 9305 limit--;
19cfaecc 9306 } else {
b6080e12
MC		 9307 tw32(HOSTCC_RXCOL_TICKS, 0);
9308 tw32(HOSTCC_RXMAX_FRAMES, 0);
9309 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 9310 }
b6080e12 9311
a489b6d9 9312 for (; i < limit; i++) {
b6080e12
MC		 9313 u32 reg;
9314
9315 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9316 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 9317 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9318 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 9319 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9320 tw32(reg, ec->rx_max_coalesced_frames_irq);
b6080e12
MC		 9321 }
9322
9323 for (; i < tp->irq_max - 1; i++) {
9324 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 9325 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 9326 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
a489b6d9
MC		 9327 }
9328}
19cfaecc 9329
a489b6d9
MC		 9330static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9331{
9332 tg3_coal_tx_init(tp, ec);
9333 tg3_coal_rx_init(tp, ec);
9334
9335 if (!tg3_flag(tp, 5705_PLUS)) {
9336 u32 val = ec->stats_block_coalesce_usecs;
9337
9338 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9339 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9340
f4a46d1f 9341 if (!tp->link_up)
a489b6d9
MC		 9342 val = 0;
9343
9344 tw32(HOSTCC_STAT_COAL_TICKS, val);
b6080e12 9345 }
15f9850d 9346}
1da177e4 9347
328947ff
NS		 9348/* tp->lock is held. */
9349static void tg3_tx_rcbs_disable(struct tg3 *tp)
9350{
9351 u32 txrcb, limit;
9352
9353 /* Disable all transmit rings but the first. */
9354 if (!tg3_flag(tp, 5705_PLUS))
9355 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9356 else if (tg3_flag(tp, 5717_PLUS))
9357 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9358 else if (tg3_flag(tp, 57765_CLASS) ||
9359 tg3_asic_rev(tp) == ASIC_REV_5762)
9360 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9361 else
9362 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9363
9364 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9365 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9366 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9367 BDINFO_FLAGS_DISABLED);
9368}
9369
32ba19ef
NS		 9370/* tp->lock is held. */
9371static void tg3_tx_rcbs_init(struct tg3 *tp)
9372{
9373 int i = 0;
9374 u32 txrcb = NIC_SRAM_SEND_RCB;
9375
9376 if (tg3_flag(tp, ENABLE_TSS))
9377 i++;
9378
9379 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9380 struct tg3_napi *tnapi = &tp->napi[i];
9381
9382 if (!tnapi->tx_ring)
9383 continue;
9384
9385 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9386 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9387 NIC_SRAM_TX_BUFFER_DESC);
9388 }
9389}
9390
328947ff
NS		 9391/* tp->lock is held. */
9392static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9393{
9394 u32 rxrcb, limit;
9395
9396 /* Disable all receive return rings but the first. */
9397 if (tg3_flag(tp, 5717_PLUS))
9398 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9399 else if (!tg3_flag(tp, 5705_PLUS))
9400 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9401 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9402 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9403 tg3_flag(tp, 57765_CLASS))
9404 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9405 else
9406 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9407
9408 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9409 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9410 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9411 BDINFO_FLAGS_DISABLED);
9412}
9413
32ba19ef
NS		 9414/* tp->lock is held. */
9415static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9416{
9417 int i = 0;
9418 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9419
9420 if (tg3_flag(tp, ENABLE_RSS))
9421 i++;
9422
9423 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9424 struct tg3_napi *tnapi = &tp->napi[i];
9425
9426 if (!tnapi->rx_rcb)
9427 continue;
9428
9429 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9430 (tp->rx_ret_ring_mask + 1) <<
9431 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9432 }
9433}
9434
2d31ecaf
MC		 9435/* tp->lock is held. */
9436static void tg3_rings_reset(struct tg3 *tp)
9437{
9438 int i;
328947ff 9439 u32 stblk;
2d31ecaf
MC		 9440 struct tg3_napi *tnapi = &tp->napi[0];
9441
328947ff 9442 tg3_tx_rcbs_disable(tp);
2d31ecaf 9443
328947ff 9444 tg3_rx_ret_rcbs_disable(tp);
2d31ecaf
MC		 9445
9446 /* Disable interrupts */
9447 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
0e6cf6a9
MC		 9448 tp->napi[0].chk_msi_cnt = 0;
9449 tp->napi[0].last_rx_cons = 0;
9450 tp->napi[0].last_tx_cons = 0;
2d31ecaf
MC		 9451
9452 /* Zero mailbox registers. */
63c3a66f 9453 if (tg3_flag(tp, SUPPORT_MSIX)) {
6fd45cb8 9454 for (i = 1; i < tp->irq_max; i++) {
f77a6a8e
MC		 9455 tp->napi[i].tx_prod = 0;
9456 tp->napi[i].tx_cons = 0;
63c3a66f 9457 if (tg3_flag(tp, ENABLE_TSS))
c2353a32 9458 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 9459 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9460 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7f230735 9461 tp->napi[i].chk_msi_cnt = 0;
0e6cf6a9
MC		 9462 tp->napi[i].last_rx_cons = 0;
9463 tp->napi[i].last_tx_cons = 0;
f77a6a8e 9464 }
63c3a66f 9465 if (!tg3_flag(tp, ENABLE_TSS))
c2353a32 9466 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 9467 } else {
9468 tp->napi[0].tx_prod = 0;
9469 tp->napi[0].tx_cons = 0;
9470 tw32_mailbox(tp->napi[0].prodmbox, 0);
9471 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9472 }
2d31ecaf
MC		 9473
9474 /* Make sure the NIC-based send BD rings are disabled. */
63c3a66f 9475 if (!tg3_flag(tp, 5705_PLUS)) {
2d31ecaf
MC		 9476 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9477 for (i = 0; i < 16; i++)
9478 tw32_tx_mbox(mbox + i * 8, 0);
9479 }
9480
2d31ecaf
MC		 9481 /* Clear status block in ram. */
9482 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9483
9484 /* Set status block DMA address */
9485 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9486 ((u64) tnapi->status_mapping >> 32));
9487 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9488 ((u64) tnapi->status_mapping & 0xffffffff));
9489
f77a6a8e 9490 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 9491
f77a6a8e
MC		 9492 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9493 u64 mapping = (u64)tnapi->status_mapping;
9494 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9495 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
32ba19ef 9496 stblk += 8;
f77a6a8e
MC		 9497
9498 /* Clear status block in ram. */
9499 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
f77a6a8e 9500 }
32ba19ef
NS		 9501
9502 tg3_tx_rcbs_init(tp);
9503 tg3_rx_ret_rcbs_init(tp);
2d31ecaf
MC		 9504}
9505
eb07a940
MC		 9506static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9507{
9508 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9509
63c3a66f
JP		 9510 if (!tg3_flag(tp, 5750_PLUS) ||
9511 tg3_flag(tp, 5780_CLASS) ||
4153577a
JP		 9512 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9513 tg3_asic_rev(tp) == ASIC_REV_5752 ||
513aa6ea 9514 tg3_flag(tp, 57765_PLUS))
eb07a940 9515 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
4153577a
JP		 9516 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9517 tg3_asic_rev(tp) == ASIC_REV_5787)
eb07a940
MC		 9518 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9519 else
9520 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9521
9522 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9523 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9524
9525 val = min(nic_rep_thresh, host_rep_thresh);
9526 tw32(RCVBDI_STD_THRESH, val);
9527
63c3a66f 9528 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9529 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9530
63c3a66f 9531 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
eb07a940
MC		 9532 return;
9533
513aa6ea 9534 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
eb07a940
MC		 9535
9536 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9537
9538 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9539 tw32(RCVBDI_JUMBO_THRESH, val);
9540
63c3a66f 9541 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9542 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9543}
9544
ccd5ba9d
MC		 9545static inline u32 calc_crc(unsigned char *buf, int len)
9546{
9547 u32 reg;
9548 u32 tmp;
9549 int j, k;
9550
9551 reg = 0xffffffff;
9552
9553 for (j = 0; j < len; j++) {
9554 reg ^= buf[j];
9555
9556 for (k = 0; k < 8; k++) {
9557 tmp = reg & 0x01;
9558
9559 reg >>= 1;
9560
9561 if (tmp)
9562 reg ^= 0xedb88320;
9563 }
9564 }
9565
9566 return ~reg;
9567}
9568
9569static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9570{
9571 /* accept or reject all multicast frames */
9572 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9573 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9574 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9575 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9576}
9577
9578static void __tg3_set_rx_mode(struct net_device *dev)
9579{
9580 struct tg3 *tp = netdev_priv(dev);
9581 u32 rx_mode;
9582
9583 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9584 RX_MODE_KEEP_VLAN_TAG);
9585
9586#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9587 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9588 * flag clear.
9589 */
9590 if (!tg3_flag(tp, ENABLE_ASF))
9591 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9592#endif
9593
9594 if (dev->flags & IFF_PROMISC) {
9595 /* Promiscuous mode. */
9596 rx_mode |= RX_MODE_PROMISC;
9597 } else if (dev->flags & IFF_ALLMULTI) {
9598 /* Accept all multicast. */
9599 tg3_set_multi(tp, 1);
9600 } else if (netdev_mc_empty(dev)) {
9601 /* Reject all multicast. */
9602 tg3_set_multi(tp, 0);
9603 } else {
9604 /* Accept one or more multicast(s). */
9605 struct netdev_hw_addr *ha;
9606 u32 mc_filter[4] = { 0, };
9607 u32 regidx;
9608 u32 bit;
9609 u32 crc;
9610
9611 netdev_for_each_mc_addr(ha, dev) {
9612 crc = calc_crc(ha->addr, ETH_ALEN);
9613 bit = ~crc & 0x7f;
9614 regidx = (bit & 0x60) >> 5;
9615 bit &= 0x1f;
9616 mc_filter[regidx] |= (1 << bit);
9617 }
9618
9619 tw32(MAC_HASH_REG_0, mc_filter[0]);
9620 tw32(MAC_HASH_REG_1, mc_filter[1]);
9621 tw32(MAC_HASH_REG_2, mc_filter[2]);
9622 tw32(MAC_HASH_REG_3, mc_filter[3]);
9623 }
9624
9625 if (rx_mode != tp->rx_mode) {
9626 tp->rx_mode = rx_mode;
9627 tw32_f(MAC_RX_MODE, rx_mode);
9628 udelay(10);
9629 }
9630}
9631
9102426a 9632static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
90415477
MC		 9633{
9634 int i;
9635
9636 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9102426a 9637 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
90415477
MC		 9638}
9639
9640static void tg3_rss_check_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9641{
9642 int i;
9643
9644 if (!tg3_flag(tp, SUPPORT_MSIX))
9645 return;
9646
0b3ba055 9647 if (tp->rxq_cnt == 1) {
bcebcc46 9648 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
90415477
MC		 9649 return;
9650 }
9651
9652 /* Validate table against current IRQ count */
9653 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
0b3ba055 9654 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
90415477
MC		 9655 break;
9656 }
9657
9658 if (i != TG3_RSS_INDIR_TBL_SIZE)
9102426a 9659 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
bcebcc46
MC		 9660}
9661
90415477 9662static void tg3_rss_write_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9663{
9664 int i = 0;
9665 u32 reg = MAC_RSS_INDIR_TBL_0;
9666
9667 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9668 u32 val = tp->rss_ind_tbl[i];
9669 i++;
9670 for (; i % 8; i++) {
9671 val <<= 4;
9672 val |= tp->rss_ind_tbl[i];
9673 }
9674 tw32(reg, val);
9675 reg += 4;
9676 }
9677}
9678
9bc297ea
NS		 9679static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9680{
9681 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9682 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9683 else
9684 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9685}
9686
1da177e4 9687/* tp->lock is held. */
953c96e0 9688static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
1da177e4
LT		 9689{
9690 u32 val, rdmac_mode;
9691 int i, err, limit;
8fea32b9 9692 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
1da177e4
LT		 9693
9694 tg3_disable_ints(tp);
9695
9696 tg3_stop_fw(tp);
9697
9698 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9699
63c3a66f 9700 if (tg3_flag(tp, INIT_COMPLETE))
e6de8ad1 9701 tg3_abort_hw(tp, 1);
1da177e4 9702
fdad8de4
NS		 9703 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9704 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9705 tg3_phy_pull_config(tp);
400dfbaa 9706 tg3_eee_pull_config(tp, NULL);
fdad8de4
NS		 9707 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9708 }
9709
400dfbaa
NS		 9710 /* Enable MAC control of LPI */
9711 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9712 tg3_setup_eee(tp);
9713
603f1173 9714 if (reset_phy)
d4d2c558
MC		 9715 tg3_phy_reset(tp);
9716
1da177e4
LT		 9717 err = tg3_chip_reset(tp);
9718 if (err)
9719 return err;
9720
9721 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9722
4153577a 9723 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
d30cdd28
MC		 9724 val = tr32(TG3_CPMU_CTRL);
9725 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9726 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 9727
9728 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9729 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9730 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9731 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9732
9733 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9734 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9735 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9736 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9737
9738 val = tr32(TG3_CPMU_HST_ACC);
9739 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9740 val |= CPMU_HST_ACC_MACCLK_6_25;
9741 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 9742 }
9743
4153577a 9744 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
33466d93
MC		 9745 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9746 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9747 PCIE_PWR_MGMT_L1_THRESH_4MS;
9748 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 9749
9750 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9751 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9752
9753 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 9754
f40386c8
MC		 9755 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9756 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 9757 }
9758
63c3a66f 9759 if (tg3_flag(tp, L1PLLPD_EN)) {
614b0590
MC		 9760 u32 grc_mode = tr32(GRC_MODE);
9761
9762 /* Access the lower 1K of PL PCIE block registers. */
9763 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9764 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9765
9766 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9767 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9768 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9769
9770 tw32(GRC_MODE, grc_mode);
9771 }
9772
55086ad9 9773 if (tg3_flag(tp, 57765_CLASS)) {
4153577a 9774 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
5093eedc 9775 u32 grc_mode = tr32(GRC_MODE);
cea46462 9776
5093eedc
MC		 9777 /* Access the lower 1K of PL PCIE block registers. */
9778 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9779 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
cea46462 9780
5093eedc
MC		 9781 val = tr32(TG3_PCIE_TLDLPL_PORT +
9782 TG3_PCIE_PL_LO_PHYCTL5);
9783 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9784 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
cea46462 9785
5093eedc
MC		 9786 tw32(GRC_MODE, grc_mode);
9787 }
a977dbe8 9788
4153577a 9789 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
d3f677af
MC		 9790 u32 grc_mode;
9791
9792 /* Fix transmit hangs */
9793 val = tr32(TG3_CPMU_PADRNG_CTL);
9794 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9795 tw32(TG3_CPMU_PADRNG_CTL, val);
9796
9797 grc_mode = tr32(GRC_MODE);
1ff30a59
MC		 9798
9799 /* Access the lower 1K of DL PCIE block registers. */
9800 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9801 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9802
9803 val = tr32(TG3_PCIE_TLDLPL_PORT +
9804 TG3_PCIE_DL_LO_FTSMAX);
9805 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9806 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9807 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9808
9809 tw32(GRC_MODE, grc_mode);
9810 }
9811
a977dbe8
MC		 9812 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9813 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9814 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9815 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
cea46462
MC		 9816 }
9817
1da177e4
LT		 9818 /* This works around an issue with Athlon chipsets on
9819 * B3 tigon3 silicon. This bit has no effect on any
9820 * other revision. But do not set this on PCI Express
795d01c5 9821 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 9822 */
63c3a66f
JP		 9823 if (!tg3_flag(tp, CPMU_PRESENT)) {
9824 if (!tg3_flag(tp, PCI_EXPRESS))
795d01c5
MC		 9825 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9826 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9827 }
1da177e4 9828
4153577a 9829 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 9830 tg3_flag(tp, PCIX_MODE)) {
1da177e4
LT		 9831 val = tr32(TG3PCI_PCISTATE);
9832 val |= PCISTATE_RETRY_SAME_DMA;
9833 tw32(TG3PCI_PCISTATE, val);
9834 }
9835
63c3a66f 9836 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 9837 /* Allow reads and writes to the
9838 * APE register and memory space.
9839 */
9840 val = tr32(TG3PCI_PCISTATE);
9841 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 9842 PCISTATE_ALLOW_APE_SHMEM_WR |
9843 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 9844 tw32(TG3PCI_PCISTATE, val);
9845 }
9846
4153577a 9847 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
1da177e4
LT		 9848 /* Enable some hw fixes. */
9849 val = tr32(TG3PCI_MSI_DATA);
9850 val |= (1 << 26) | (1 << 28) | (1 << 29);
9851 tw32(TG3PCI_MSI_DATA, val);
9852 }
9853
9854 /* Descriptor ring init may make accesses to the
9855 * NIC SRAM area to setup the TX descriptors, so we
9856 * can only do this after the hardware has been
9857 * successfully reset.
9858 */
32d8c572
MC		 9859 err = tg3_init_rings(tp);
9860 if (err)
9861 return err;
1da177e4 9862
63c3a66f 9863 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 9864 val = tr32(TG3PCI_DMA_RW_CTRL) &
9865 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
4153577a 9866 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
1a319025 9867 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
55086ad9 9868 if (!tg3_flag(tp, 57765_CLASS) &&
4153577a
JP		 9869 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9870 tg3_asic_rev(tp) != ASIC_REV_5762)
0aebff48 9871 val |= DMA_RWCTRL_TAGGED_STAT_WA;
cbf9ca6c 9872 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
4153577a
JP		 9873 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9874 tg3_asic_rev(tp) != ASIC_REV_5761) {
d30cdd28
MC		 9875 /* This value is determined during the probe time DMA
9876 * engine test, tg3_test_dma.
9877 */
9878 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9879 }
1da177e4
LT		 9880
9881 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
9882 GRC_MODE_4X_NIC_SEND_RINGS |
9883 GRC_MODE_NO_TX_PHDR_CSUM |
9884 GRC_MODE_NO_RX_PHDR_CSUM);
9885 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 9886
9887 /* Pseudo-header checksum is done by hardware logic and not
9888 * the offload processers, so make the chip do the pseudo-
9889 * header checksums on receive. For transmit it is more
9890 * convenient to do the pseudo-header checksum in software
9891 * as Linux does that on transmit for us in all cases.
9892 */
9893 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4 9894
fb4ce8ad
MC		 9895 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
9896 if (tp->rxptpctl)
9897 tw32(TG3_RX_PTP_CTL,
9898 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
9899
9900 if (tg3_flag(tp, PTP_CAPABLE))
9901 val |= GRC_MODE_TIME_SYNC_ENABLE;
9902
9903 tw32(GRC_MODE, tp->grc_mode | val);
1da177e4
LT		 9904
9905 /* Setup the timer prescalar register. Clock is always 66Mhz. */
9906 val = tr32(GRC_MISC_CFG);
9907 val &= ~0xff;
9908 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
9909 tw32(GRC_MISC_CFG, val);
9910
9911 /* Initialize MBUF/DESC pool. */
63c3a66f 9912 if (tg3_flag(tp, 5750_PLUS)) {
1da177e4 9913 /* Do nothing. */
4153577a 9914 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
1da177e4 9915 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
4153577a 9916 if (tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 9917 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
9918 else
9919 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
9920 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
9921 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
63c3a66f 9922 } else if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 9923 int fw_len;
9924
077f849d 9925 fw_len = tp->fw_len;
1da177e4
LT		 9926 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
9927 tw32(BUFMGR_MB_POOL_ADDR,
9928 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
9929 tw32(BUFMGR_MB_POOL_SIZE,
9930 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
9931 }
1da177e4 9932
0f893dc6 9933 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 9934 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9935 tp->bufmgr_config.mbuf_read_dma_low_water);
9936 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9937 tp->bufmgr_config.mbuf_mac_rx_low_water);
9938 tw32(BUFMGR_MB_HIGH_WATER,
9939 tp->bufmgr_config.mbuf_high_water);
9940 } else {
9941 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9942 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
9943 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9944 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
9945 tw32(BUFMGR_MB_HIGH_WATER,
9946 tp->bufmgr_config.mbuf_high_water_jumbo);
9947 }
9948 tw32(BUFMGR_DMA_LOW_WATER,
9949 tp->bufmgr_config.dma_low_water);
9950 tw32(BUFMGR_DMA_HIGH_WATER,
9951 tp->bufmgr_config.dma_high_water);
9952
d309a46e 9953 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
4153577a 9954 if (tg3_asic_rev(tp) == ASIC_REV_5719)
d309a46e 9955 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
4153577a
JP		 9956 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
9957 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
9958 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
4d958473 9959 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
d309a46e 9960 tw32(BUFMGR_MODE, val);
1da177e4
LT		 9961 for (i = 0; i < 2000; i++) {
9962 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
9963 break;
9964 udelay(10);
9965 }
9966 if (i >= 2000) {
05dbe005 9967 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 9968 return -ENODEV;
9969 }
9970
4153577a 9971 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
eb07a940 9972 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
b5d3772c 9973
eb07a940 9974 tg3_setup_rxbd_thresholds(tp);
1da177e4
LT		 9975
9976 /* Initialize TG3_BDINFO's at:
9977 * RCVDBDI_STD_BD: standard eth size rx ring
9978 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
9979 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
9980 *
9981 * like so:
9982 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
9983 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
9984 * ring attribute flags
9985 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
9986 *
9987 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
9988 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
9989 *
9990 * The size of each ring is fixed in the firmware, but the location is
9991 * configurable.
9992 */
9993 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 9994 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 9995 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 9996 ((u64) tpr->rx_std_mapping & 0xffffffff));
63c3a66f 9997 if (!tg3_flag(tp, 5717_PLUS))
87668d35
MC		 9998 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
9999 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 10000
fdb72b38 10001 /* Disable the mini ring */
63c3a66f 10002 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10003 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10004 BDINFO_FLAGS_DISABLED);
10005
fdb72b38
MC		 10006 /* Program the jumbo buffer descriptor ring control
10007 * blocks on those devices that have them.
10008 */
4153577a 10009 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
63c3a66f 10010 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
1da177e4 10011
63c3a66f 10012 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
1da177e4 10013 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10014 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 10015 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10016 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
de9f5230
MC		 10017 val = TG3_RX_JMB_RING_SIZE(tp) <<
10018 BDINFO_FLAGS_MAXLEN_SHIFT;
1da177e4 10019 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
de9f5230 10020 val | BDINFO_FLAGS_USE_EXT_RECV);
63c3a66f 10021 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
c65a17f4 10022 tg3_flag(tp, 57765_CLASS) ||
4153577a 10023 tg3_asic_rev(tp) == ASIC_REV_5762)
87668d35
MC		 10024 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10025 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 10026 } else {
10027 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10028 BDINFO_FLAGS_DISABLED);
10029 }
10030
63c3a66f 10031 if (tg3_flag(tp, 57765_PLUS)) {
fa6b2aae 10032 val = TG3_RX_STD_RING_SIZE(tp);
7cb32cf2
MC		 10033 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10034 val |= (TG3_RX_STD_DMA_SZ << 2);
10035 } else
04380d40 10036 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38 10037 } else
de9f5230 10038 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 10039
10040 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 10041
411da640 10042 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 10043 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 10044
63c3a66f
JP		 10045 tpr->rx_jmb_prod_idx =
10046 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
66711e66 10047 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 10048
2d31ecaf
MC		 10049 tg3_rings_reset(tp);
10050
1da177e4 10051 /* Initialize MAC address and backoff seed. */
953c96e0 10052 __tg3_set_mac_addr(tp, false);
1da177e4
LT		 10053
10054 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 10055 tw32(MAC_RX_MTU_SIZE,
10056 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 10057
10058 /* The slot time is changed by tg3_setup_phy if we
10059 * run at gigabit with half duplex.
10060 */
f2096f94
MC		 10061 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10062 (6 << TX_LENGTHS_IPG_SHIFT) |
10063 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10064
4153577a
JP		 10065 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10066 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10067 val |= tr32(MAC_TX_LENGTHS) &
10068 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10069 TX_LENGTHS_CNT_DWN_VAL_MSK);
10070
10071 tw32(MAC_TX_LENGTHS, val);
1da177e4
LT		 10072
10073 /* Receive rules. */
10074 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10075 tw32(RCVLPC_CONFIG, 0x0181);
10076
10077 /* Calculate RDMAC_MODE setting early, we need it to determine
10078 * the RCVLPC_STATE_ENABLE mask.
10079 */
10080 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10081 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10082 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10083 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10084 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 10085
4153577a 10086 if (tg3_asic_rev(tp) == ASIC_REV_5717)
0339e4e3
MC		 10087 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10088
4153577a
JP		 10089 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10090 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10091 tg3_asic_rev(tp) == ASIC_REV_57780)
d30cdd28
MC		 10092 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10093 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10094 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10095
4153577a
JP		 10096 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10097 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10098 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a 10099 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 10100 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10101 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10102 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10103 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10104 }
10105 }
10106
63c3a66f 10107 if (tg3_flag(tp, PCI_EXPRESS))
85e94ced
MC		 10108 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10109
4153577a 10110 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
d3f677af
MC		 10111 tp->dma_limit = 0;
10112 if (tp->dev->mtu <= ETH_DATA_LEN) {
10113 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10114 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10115 }
10116 }
10117
63c3a66f
JP		 10118 if (tg3_flag(tp, HW_TSO_1) ||
10119 tg3_flag(tp, HW_TSO_2) ||
10120 tg3_flag(tp, HW_TSO_3))
027455ad
MC		 10121 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10122
108a6c16 10123 if (tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 10124 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10125 tg3_asic_rev(tp) == ASIC_REV_57780)
027455ad 10126 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4 10127
4153577a
JP		 10128 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10129 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10130 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10131
4153577a
JP		 10132 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10133 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10134 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10135 tg3_asic_rev(tp) == ASIC_REV_57780 ||
63c3a66f 10136 tg3_flag(tp, 57765_PLUS)) {
c65a17f4
MC		 10137 u32 tgtreg;
10138
4153577a 10139 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10140 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10141 else
10142 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10143
10144 val = tr32(tgtreg);
4153577a
JP		 10145 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10146 tg3_asic_rev(tp) == ASIC_REV_5762) {
b4495ed8
MC		 10147 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10148 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10149 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10150 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10151 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10152 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
b75cc0e4 10153 }
c65a17f4 10154 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
41a8a7ee
MC		 10155 }
10156
4153577a
JP		 10157 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10158 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10159 tg3_asic_rev(tp) == ASIC_REV_5762) {
c65a17f4
MC		 10160 u32 tgtreg;
10161
4153577a 10162 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10163 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10164 else
10165 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10166
10167 val = tr32(tgtreg);
10168 tw32(tgtreg, val |
d309a46e
MC		 10169 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10170 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10171 }
10172
1da177e4 10173 /* Receive/send statistics. */
63c3a66f 10174 if (tg3_flag(tp, 5750_PLUS)) {
1661394e
MC		 10175 val = tr32(RCVLPC_STATS_ENABLE);
10176 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10177 tw32(RCVLPC_STATS_ENABLE, val);
10178 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
63c3a66f 10179 tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10180 val = tr32(RCVLPC_STATS_ENABLE);
10181 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10182 tw32(RCVLPC_STATS_ENABLE, val);
10183 } else {
10184 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10185 }
10186 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10187 tw32(SNDDATAI_STATSENAB, 0xffffff);
10188 tw32(SNDDATAI_STATSCTRL,
10189 (SNDDATAI_SCTRL_ENABLE |
10190 SNDDATAI_SCTRL_FASTUPD));
10191
10192 /* Setup host coalescing engine. */
10193 tw32(HOSTCC_MODE, 0);
10194 for (i = 0; i < 2000; i++) {
10195 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10196 break;
10197 udelay(10);
10198 }
10199
d244c892 10200 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 10201
63c3a66f 10202 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10203 /* Status/statistics block address. See tg3_timer,
10204 * the tg3_periodic_fetch_stats call there, and
10205 * tg3_get_stats to see how this works for 5705/5750 chips.
10206 */
1da177e4
LT		 10207 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10208 ((u64) tp->stats_mapping >> 32));
10209 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10210 ((u64) tp->stats_mapping & 0xffffffff));
10211 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 10212
1da177e4 10213 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 10214
10215 /* Clear statistics and status block memory areas */
10216 for (i = NIC_SRAM_STATS_BLK;
10217 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10218 i += sizeof(u32)) {
10219 tg3_write_mem(tp, i, 0);
10220 udelay(40);
10221 }
1da177e4
LT		 10222 }
10223
10224 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10225
10226 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10227 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
63c3a66f 10228 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10229 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10230
f07e9af3
MC		 10231 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10232 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c94e3941
MC		 10233 /* reset to prevent losing 1st rx packet intermittently */
10234 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10235 udelay(10);
10236 }
10237
3bda1258 10238 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9e975cc2
MC		 10239 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10240 MAC_MODE_FHDE_ENABLE;
10241 if (tg3_flag(tp, ENABLE_APE))
10242 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
63c3a66f 10243 if (!tg3_flag(tp, 5705_PLUS) &&
f07e9af3 10244 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a 10245 tg3_asic_rev(tp) != ASIC_REV_5700)
e8f3f6ca 10246 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 10247 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10248 udelay(40);
10249
314fba34 10250 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
63c3a66f 10251 * If TG3_FLAG_IS_NIC is zero, we should read the
314fba34
MC		 10252 * register to preserve the GPIO settings for LOMs. The GPIOs,
10253 * whether used as inputs or outputs, are set by boot code after
10254 * reset.
10255 */
63c3a66f 10256 if (!tg3_flag(tp, IS_NIC)) {
314fba34
MC		 10257 u32 gpio_mask;
10258
9d26e213
MC		 10259 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10260 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10261 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc 10262
4153577a 10263 if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc
MC		 10264 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10265 GRC_LCLCTRL_GPIO_OUTPUT3;
10266
4153577a 10267 if (tg3_asic_rev(tp) == ASIC_REV_5755)
af36e6b6
MC		 10268 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10269
aaf84465 10270 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 10271 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10272
10273 /* GPIO1 must be driven high for eeprom write protect */
63c3a66f 10274 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9d26e213
MC		 10275 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10276 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 10277 }
1da177e4
LT		 10278 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10279 udelay(100);
10280
c3b5003b 10281 if (tg3_flag(tp, USING_MSIX)) {
baf8a94a 10282 val = tr32(MSGINT_MODE);
c3b5003b
MC		 10283 val |= MSGINT_MODE_ENABLE;
10284 if (tp->irq_cnt > 1)
10285 val |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 10286 if (!tg3_flag(tp, 1SHOT_MSI))
10287 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
baf8a94a
MC		 10288 tw32(MSGINT_MODE, val);
10289 }
10290
63c3a66f 10291 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10292 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10293 udelay(40);
10294 }
10295
10296 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10297 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10298 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10299 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10300 WDMAC_MODE_LNGREAD_ENAB);
10301
4153577a
JP		 10302 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10303 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10304 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a
JP		 10305 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10306 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
1da177e4
LT		 10307 /* nothing */
10308 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10309 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10310 val |= WDMAC_MODE_RX_ACCEL;
10311 }
10312 }
10313
d9ab5ad1 10314 /* Enable host coalescing bug fix */
63c3a66f 10315 if (tg3_flag(tp, 5755_PLUS))
f51f3562 10316 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 10317
4153577a 10318 if (tg3_asic_rev(tp) == ASIC_REV_5785)
788a035e
MC		 10319 val |= WDMAC_MODE_BURST_ALL_DATA;
10320
1da177e4
LT		 10321 tw32_f(WDMAC_MODE, val);
10322 udelay(40);
10323
63c3a66f 10324 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 10325 u16 pcix_cmd;
10326
10327 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10328 &pcix_cmd);
4153577a 10329 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
9974a356
MC		 10330 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10331 pcix_cmd |= PCI_X_CMD_READ_2K;
4153577a 10332 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
9974a356
MC		 10333 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10334 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 10335 }
9974a356
MC		 10336 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10337 pcix_cmd);
1da177e4
LT		 10338 }
10339
10340 tw32_f(RDMAC_MODE, rdmac_mode);
10341 udelay(40);
10342
9bc297ea
NS		 10343 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10344 tg3_asic_rev(tp) == ASIC_REV_5720) {
091f0ea3
MC		 10345 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10346 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10347 break;
10348 }
10349 if (i < TG3_NUM_RDMA_CHANNELS) {
10350 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10351 val |= tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10352 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10353 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
091f0ea3
MC		 10354 }
10355 }
10356
1da177e4 10357 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
63c3a66f 10358 if (!tg3_flag(tp, 5705_PLUS))
1da177e4 10359 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6 10360
4153577a 10361 if (tg3_asic_rev(tp) == ASIC_REV_5761)
9936bcf6
MC		 10362 tw32(SNDDATAC_MODE,
10363 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10364 else
10365 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10366
1da177e4
LT		 10367 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10368 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7cb32cf2 10369 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
63c3a66f 10370 if (tg3_flag(tp, LRG_PROD_RING_CAP))
7cb32cf2
MC		 10371 val |= RCVDBDI_MODE_LRG_RING_SZ;
10372 tw32(RCVDBDI_MODE, val);
1da177e4 10373 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
63c3a66f
JP		 10374 if (tg3_flag(tp, HW_TSO_1) ||
10375 tg3_flag(tp, HW_TSO_2) ||
10376 tg3_flag(tp, HW_TSO_3))
1da177e4 10377 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 10378 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
63c3a66f 10379 if (tg3_flag(tp, ENABLE_TSS))
baf8a94a
MC		 10380 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10381 tw32(SNDBDI_MODE, val);
1da177e4
LT		 10382 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10383
4153577a 10384 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
1da177e4
LT		 10385 err = tg3_load_5701_a0_firmware_fix(tp);
10386 if (err)
10387 return err;
10388 }
10389
c4dab506
NS		 10390 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10391 /* Ignore any errors for the firmware download. If download
10392 * fails, the device will operate with EEE disabled
10393 */
10394 tg3_load_57766_firmware(tp);
10395 }
10396
63c3a66f 10397 if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10398 err = tg3_load_tso_firmware(tp);
10399 if (err)
10400 return err;
10401 }
1da177e4
LT		 10402
10403 tp->tx_mode = TX_MODE_ENABLE;
f2096f94 10404
63c3a66f 10405 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 10406 tg3_asic_rev(tp) == ASIC_REV_5906)
b1d05210 10407 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
f2096f94 10408
4153577a
JP		 10409 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10410 tg3_asic_rev(tp) == ASIC_REV_5762) {
f2096f94
MC		 10411 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10412 tp->tx_mode &= ~val;
10413 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10414 }
10415
1da177e4
LT		 10416 tw32_f(MAC_TX_MODE, tp->tx_mode);
10417 udelay(100);
10418
63c3a66f 10419 if (tg3_flag(tp, ENABLE_RSS)) {
bcebcc46 10420 tg3_rss_write_indir_tbl(tp);
baf8a94a
MC		 10421
10422 /* Setup the "secret" hash key. */
10423 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10424 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10425 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10426 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10427 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10428 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10429 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10430 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10431 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10432 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10433 }
10434
1da177e4 10435 tp->rx_mode = RX_MODE_ENABLE;
63c3a66f 10436 if (tg3_flag(tp, 5755_PLUS))
af36e6b6
MC		 10437 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10438
378b72c8
NS		 10439 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10440 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10441
63c3a66f 10442 if (tg3_flag(tp, ENABLE_RSS))
baf8a94a
MC		 10443 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10444 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10445 RX_MODE_RSS_IPV6_HASH_EN |
10446 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10447 RX_MODE_RSS_IPV4_HASH_EN |
10448 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10449
1da177e4
LT		 10450 tw32_f(MAC_RX_MODE, tp->rx_mode);
10451 udelay(10);
10452
1da177e4
LT		 10453 tw32(MAC_LED_CTRL, tp->led_ctrl);
10454
10455 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
f07e9af3 10456 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
1da177e4
LT		 10457 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10458 udelay(10);
10459 }
10460 tw32_f(MAC_RX_MODE, tp->rx_mode);
10461 udelay(10);
10462
f07e9af3 10463 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a
JP		 10464 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10465 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
1da177e4
LT		 10466 /* Set drive transmission level to 1.2V */
10467 /* only if the signal pre-emphasis bit is not set */
10468 val = tr32(MAC_SERDES_CFG);
10469 val &= 0xfffff000;
10470 val |= 0x880;
10471 tw32(MAC_SERDES_CFG, val);
10472 }
4153577a 10473 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
1da177e4
LT		 10474 tw32(MAC_SERDES_CFG, 0x616000);
10475 }
10476
10477 /* Prevent chip from dropping frames when flow control
10478 * is enabled.
10479 */
55086ad9 10480 if (tg3_flag(tp, 57765_CLASS))
666bc831
MC		 10481 val = 1;
10482 else
10483 val = 2;
10484 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4 10485
4153577a 10486 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
f07e9af3 10487 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
1da177e4 10488 /* Use hardware link auto-negotiation */
63c3a66f 10489 tg3_flag_set(tp, HW_AUTONEG);
1da177e4
LT		 10490 }
10491
f07e9af3 10492 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
4153577a 10493 tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 10494 u32 tmp;
10495
10496 tmp = tr32(SERDES_RX_CTRL);
10497 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10498 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10499 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10500 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10501 }
10502
63c3a66f 10503 if (!tg3_flag(tp, USE_PHYLIB)) {
c6700ce2 10504 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
80096068 10505 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1da177e4 10506
953c96e0 10507 err = tg3_setup_phy(tp, false);
dd477003
MC		 10508 if (err)
10509 return err;
1da177e4 10510
f07e9af3
MC		 10511 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10512 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
dd477003
MC		 10513 u32 tmp;
10514
10515 /* Clear CRC stats. */
10516 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10517 tg3_writephy(tp, MII_TG3_TEST1,
10518 tmp | MII_TG3_TEST1_CRC_EN);
f08aa1a8 10519 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
dd477003 10520 }
1da177e4
LT		 10521 }
10522 }
10523
10524 __tg3_set_rx_mode(tp->dev);
10525
10526 /* Initialize receive rules. */
10527 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10528 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10529 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10530 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10531
63c3a66f 10532 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
1da177e4
LT		 10533 limit = 8;
10534 else
10535 limit = 16;
63c3a66f 10536 if (tg3_flag(tp, ENABLE_ASF))
1da177e4
LT		 10537 limit -= 4;
10538 switch (limit) {
10539 case 16:
10540 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10541 case 15:
10542 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10543 case 14:
10544 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10545 case 13:
10546 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10547 case 12:
10548 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10549 case 11:
10550 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10551 case 10:
10552 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10553 case 9:
10554 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10555 case 8:
10556 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10557 case 7:
10558 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10559 case 6:
10560 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10561 case 5:
10562 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10563 case 4:
10564 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10565 case 3:
10566 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10567 case 2:
10568 case 1:
10569
10570 default:
10571 break;
855e1111 10572 }
1da177e4 10573
63c3a66f 10574 if (tg3_flag(tp, ENABLE_APE))
9ce768ea
MC		 10575 /* Write our heartbeat update interval to APE. */
10576 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10577 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 10578
1da177e4
LT		 10579 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10580
1da177e4
LT		 10581 return 0;
10582}
10583
10584/* Called at device open time to get the chip ready for
10585 * packet processing. Invoked with tp->lock held.
10586 */
953c96e0 10587static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
1da177e4 10588{
df465abf
NS		 10589 /* Chip may have been just powered on. If so, the boot code may still
10590 * be running initialization. Wait for it to finish to avoid races in
10591 * accessing the hardware.
10592 */
10593 tg3_enable_register_access(tp);
10594 tg3_poll_fw(tp);
10595
1da177e4
LT		 10596 tg3_switch_clocks(tp);
10597
10598 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10599
2f751b67 10600 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 10601}
10602
aed93e0b
MC		 10603static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10604{
10605 int i;
10606
10607 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10608 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10609
10610 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10611 off += len;
10612
10613 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10614 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10615 memset(ocir, 0, TG3_OCIR_LEN);
10616 }
10617}
10618
10619/* sysfs attributes for hwmon */
10620static ssize_t tg3_show_temp(struct device *dev,
10621 struct device_attribute *devattr, char *buf)
10622{
10623 struct pci_dev *pdev = to_pci_dev(dev);
10624 struct net_device *netdev = pci_get_drvdata(pdev);
10625 struct tg3 *tp = netdev_priv(netdev);
10626 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10627 u32 temperature;
10628
10629 spin_lock_bh(&tp->lock);
10630 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10631 sizeof(temperature));
10632 spin_unlock_bh(&tp->lock);
10633 return sprintf(buf, "%u\n", temperature);
10634}
10635
10636
10637static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10638 TG3_TEMP_SENSOR_OFFSET);
10639static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10640 TG3_TEMP_CAUTION_OFFSET);
10641static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10642 TG3_TEMP_MAX_OFFSET);
10643
10644static struct attribute *tg3_attributes[] = {
10645 &sensor_dev_attr_temp1_input.dev_attr.attr,
10646 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10647 &sensor_dev_attr_temp1_max.dev_attr.attr,
10648 NULL
10649};
10650
10651static const struct attribute_group tg3_group = {
10652 .attrs = tg3_attributes,
10653};
10654
aed93e0b
MC		 10655static void tg3_hwmon_close(struct tg3 *tp)
10656{
aed93e0b
MC		 10657 if (tp->hwmon_dev) {
10658 hwmon_device_unregister(tp->hwmon_dev);
10659 tp->hwmon_dev = NULL;
10660 sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group);
10661 }
aed93e0b
MC		 10662}
10663
10664static void tg3_hwmon_open(struct tg3 *tp)
10665{
aed93e0b
MC		 10666 int i, err;
10667 u32 size = 0;
10668 struct pci_dev *pdev = tp->pdev;
10669 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10670
10671 tg3_sd_scan_scratchpad(tp, ocirs);
10672
10673 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10674 if (!ocirs[i].src_data_length)
10675 continue;
10676
10677 size += ocirs[i].src_hdr_length;
10678 size += ocirs[i].src_data_length;
10679 }
10680
10681 if (!size)
10682 return;
10683
10684 /* Register hwmon sysfs hooks */
10685 err = sysfs_create_group(&pdev->dev.kobj, &tg3_group);
10686 if (err) {
10687 dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n");
10688 return;
10689 }
10690
10691 tp->hwmon_dev = hwmon_device_register(&pdev->dev);
10692 if (IS_ERR(tp->hwmon_dev)) {
10693 tp->hwmon_dev = NULL;
10694 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10695 sysfs_remove_group(&pdev->dev.kobj, &tg3_group);
10696 }
aed93e0b
MC		 10697}
10698
10699
1da177e4
LT		 10700#define TG3_STAT_ADD32(PSTAT, REG) \
10701do { u32 __val = tr32(REG); \
10702 (PSTAT)->low += __val; \
10703 if ((PSTAT)->low < __val) \
10704 (PSTAT)->high += 1; \
10705} while (0)
10706
10707static void tg3_periodic_fetch_stats(struct tg3 *tp)
10708{
10709 struct tg3_hw_stats *sp = tp->hw_stats;
10710
f4a46d1f 10711 if (!tp->link_up)
1da177e4
LT		 10712 return;
10713
10714 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10715 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10716 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10717 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10718 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10719 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10720 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10721 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10722 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10723 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10724 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10725 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10726 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9bc297ea 10727 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
091f0ea3
MC		 10728 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10729 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10730 u32 val;
10731
10732 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10733 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10734 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10735 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
091f0ea3 10736 }
1da177e4
LT		 10737
10738 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10739 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10740 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10741 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10742 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10743 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10744 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10745 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10746 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10747 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10748 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10749 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10750 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10751 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 10752
10753 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
4153577a
JP		 10754 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10755 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10756 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
4d958473
MC		 10757 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10758 } else {
10759 u32 val = tr32(HOSTCC_FLOW_ATTN);
10760 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10761 if (val) {
10762 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10763 sp->rx_discards.low += val;
10764 if (sp->rx_discards.low < val)
10765 sp->rx_discards.high += 1;
10766 }
10767 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10768 }
463d305b 10769 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 10770}
10771
0e6cf6a9
MC		 10772static void tg3_chk_missed_msi(struct tg3 *tp)
10773{
10774 u32 i;
10775
10776 for (i = 0; i < tp->irq_cnt; i++) {
10777 struct tg3_napi *tnapi = &tp->napi[i];
10778
10779 if (tg3_has_work(tnapi)) {
10780 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10781 tnapi->last_tx_cons == tnapi->tx_cons) {
10782 if (tnapi->chk_msi_cnt < 1) {
10783 tnapi->chk_msi_cnt++;
10784 return;
10785 }
7f230735 10786 tg3_msi(0, tnapi);
0e6cf6a9
MC		 10787 }
10788 }
10789 tnapi->chk_msi_cnt = 0;
10790 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10791 tnapi->last_tx_cons = tnapi->tx_cons;
10792 }
10793}
10794
1da177e4
LT		 10795static void tg3_timer(unsigned long __opaque)
10796{
10797 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 10798
5b190624 10799 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
f475f163
MC		 10800 goto restart_timer;
10801
f47c11ee 10802 spin_lock(&tp->lock);
1da177e4 10803
4153577a 10804 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
55086ad9 10805 tg3_flag(tp, 57765_CLASS))
0e6cf6a9
MC		 10806 tg3_chk_missed_msi(tp);
10807
7e6c63f0
HM		 10808 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10809 /* BCM4785: Flush posted writes from GbE to host memory. */
10810 tr32(HOSTCC_MODE);
10811 }
10812
63c3a66f 10813 if (!tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 10814 /* All of this garbage is because when using non-tagged
10815 * IRQ status the mailbox/status_block protocol the chip
10816 * uses with the cpu is race prone.
10817 */
898a56f8 10818 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 10819 tw32(GRC_LOCAL_CTRL,
10820 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10821 } else {
10822 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 10823 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 10824 }
1da177e4 10825
fac9b83e 10826 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
f47c11ee 10827 spin_unlock(&tp->lock);
db219973 10828 tg3_reset_task_schedule(tp);
5b190624 10829 goto restart_timer;
fac9b83e 10830 }
1da177e4
LT		 10831 }
10832
1da177e4
LT		 10833 /* This part only runs once per second. */
10834 if (!--tp->timer_counter) {
63c3a66f 10835 if (tg3_flag(tp, 5705_PLUS))
fac9b83e
DM		 10836 tg3_periodic_fetch_stats(tp);
10837
b0c5943f
MC		 10838 if (tp->setlpicnt && !--tp->setlpicnt)
10839 tg3_phy_eee_enable(tp);
52b02d04 10840
63c3a66f 10841 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 10842 u32 mac_stat;
10843 int phy_event;
10844
10845 mac_stat = tr32(MAC_STATUS);
10846
10847 phy_event = 0;
f07e9af3 10848 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
1da177e4
LT		 10849 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10850 phy_event = 1;
10851 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10852 phy_event = 1;
10853
10854 if (phy_event)
953c96e0 10855 tg3_setup_phy(tp, false);
63c3a66f 10856 } else if (tg3_flag(tp, POLL_SERDES)) {
1da177e4
LT		 10857 u32 mac_stat = tr32(MAC_STATUS);
10858 int need_setup = 0;
10859
f4a46d1f 10860 if (tp->link_up &&
1da177e4
LT		 10861 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10862 need_setup = 1;
10863 }
f4a46d1f 10864 if (!tp->link_up &&
1da177e4
LT		 10865 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10866 MAC_STATUS_SIGNAL_DET))) {
10867 need_setup = 1;
10868 }
10869 if (need_setup) {
3d3ebe74
MC		 10870 if (!tp->serdes_counter) {
10871 tw32_f(MAC_MODE,
10872 (tp->mac_mode &
10873 ~MAC_MODE_PORT_MODE_MASK));
10874 udelay(40);
10875 tw32_f(MAC_MODE, tp->mac_mode);
10876 udelay(40);
10877 }
953c96e0 10878 tg3_setup_phy(tp, false);
1da177e4 10879 }
f07e9af3 10880 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
63c3a66f 10881 tg3_flag(tp, 5780_CLASS)) {
747e8f8b 10882 tg3_serdes_parallel_detect(tp);
57d8b880 10883 }
1da177e4
LT		 10884
10885 tp->timer_counter = tp->timer_multiplier;
10886 }
10887
130b8e4d
MC		 10888 /* Heartbeat is only sent once every 2 seconds.
10889 *
10890 * The heartbeat is to tell the ASF firmware that the host
10891 * driver is still alive. In the event that the OS crashes,
10892 * ASF needs to reset the hardware to free up the FIFO space
10893 * that may be filled with rx packets destined for the host.
10894 * If the FIFO is full, ASF will no longer function properly.
10895 *
10896 * Unintended resets have been reported on real time kernels
10897 * where the timer doesn't run on time. Netpoll will also have
10898 * same problem.
10899 *
10900 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
10901 * to check the ring condition when the heartbeat is expiring
10902 * before doing the reset. This will prevent most unintended
10903 * resets.
10904 */
1da177e4 10905 if (!--tp->asf_counter) {
63c3a66f 10906 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7c5026aa
MC		 10907 tg3_wait_for_event_ack(tp);
10908
bbadf503 10909 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 10910 FWCMD_NICDRV_ALIVE3);
bbadf503 10911 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
c6cdf436
MC		 10912 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
10913 TG3_FW_UPDATE_TIMEOUT_SEC);
4ba526ce
MC		 10914
10915 tg3_generate_fw_event(tp);
1da177e4
LT		 10916 }
10917 tp->asf_counter = tp->asf_multiplier;
10918 }
10919
f47c11ee 10920 spin_unlock(&tp->lock);
1da177e4 10921
f475f163 10922restart_timer:
1da177e4
LT		 10923 tp->timer.expires = jiffies + tp->timer_offset;
10924 add_timer(&tp->timer);
10925}
10926
229b1ad1 10927static void tg3_timer_init(struct tg3 *tp)
21f7638e
MC		 10928{
10929 if (tg3_flag(tp, TAGGED_STATUS) &&
4153577a 10930 tg3_asic_rev(tp) != ASIC_REV_5717 &&
21f7638e
MC		 10931 !tg3_flag(tp, 57765_CLASS))
10932 tp->timer_offset = HZ;
10933 else
10934 tp->timer_offset = HZ / 10;
10935
10936 BUG_ON(tp->timer_offset > HZ);
10937
10938 tp->timer_multiplier = (HZ / tp->timer_offset);
10939 tp->asf_multiplier = (HZ / tp->timer_offset) *
10940 TG3_FW_UPDATE_FREQ_SEC;
10941
10942 init_timer(&tp->timer);
10943 tp->timer.data = (unsigned long) tp;
10944 tp->timer.function = tg3_timer;
10945}
10946
10947static void tg3_timer_start(struct tg3 *tp)
10948{
10949 tp->asf_counter = tp->asf_multiplier;
10950 tp->timer_counter = tp->timer_multiplier;
10951
10952 tp->timer.expires = jiffies + tp->timer_offset;
10953 add_timer(&tp->timer);
10954}
10955
10956static void tg3_timer_stop(struct tg3 *tp)
10957{
10958 del_timer_sync(&tp->timer);
10959}
10960
10961/* Restart hardware after configuration changes, self-test, etc.
10962 * Invoked with tp->lock held.
10963 */
953c96e0 10964static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
21f7638e
MC		 10965 __releases(tp->lock)
10966 __acquires(tp->lock)
10967{
10968 int err;
10969
10970 err = tg3_init_hw(tp, reset_phy);
10971 if (err) {
10972 netdev_err(tp->dev,
10973 "Failed to re-initialize device, aborting\n");
10974 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10975 tg3_full_unlock(tp);
10976 tg3_timer_stop(tp);
10977 tp->irq_sync = 0;
10978 tg3_napi_enable(tp);
10979 dev_close(tp->dev);
10980 tg3_full_lock(tp, 0);
10981 }
10982 return err;
10983}
10984
10985static void tg3_reset_task(struct work_struct *work)
10986{
10987 struct tg3 *tp = container_of(work, struct tg3, reset_task);
10988 int err;
10989
10990 tg3_full_lock(tp, 0);
10991
10992 if (!netif_running(tp->dev)) {
10993 tg3_flag_clear(tp, RESET_TASK_PENDING);
10994 tg3_full_unlock(tp);
10995 return;
10996 }
10997
10998 tg3_full_unlock(tp);
10999
11000 tg3_phy_stop(tp);
11001
11002 tg3_netif_stop(tp);
11003
11004 tg3_full_lock(tp, 1);
11005
11006 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11007 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11008 tp->write32_rx_mbox = tg3_write_flush_reg32;
11009 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11010 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11011 }
11012
11013 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
953c96e0 11014 err = tg3_init_hw(tp, true);
21f7638e
MC		 11015 if (err)
11016 goto out;
11017
11018 tg3_netif_start(tp);
11019
11020out:
11021 tg3_full_unlock(tp);
11022
11023 if (!err)
11024 tg3_phy_start(tp);
11025
11026 tg3_flag_clear(tp, RESET_TASK_PENDING);
11027}
11028
4f125f42 11029static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 11030{
7d12e780 11031 irq_handler_t fn;
fcfa0a32 11032 unsigned long flags;
4f125f42
MC		 11033 char *name;
11034 struct tg3_napi *tnapi = &tp->napi[irq_num];
11035
11036 if (tp->irq_cnt == 1)
11037 name = tp->dev->name;
11038 else {
11039 name = &tnapi->irq_lbl[0];
11040 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
11041 name[IFNAMSIZ-1] = 0;
11042 }
fcfa0a32 11043
63c3a66f 11044 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
fcfa0a32 11045 fn = tg3_msi;
63c3a66f 11046 if (tg3_flag(tp, 1SHOT_MSI))
fcfa0a32 11047 fn = tg3_msi_1shot;
ab392d2d 11048 flags = 0;
fcfa0a32
MC		 11049 } else {
11050 fn = tg3_interrupt;
63c3a66f 11051 if (tg3_flag(tp, TAGGED_STATUS))
fcfa0a32 11052 fn = tg3_interrupt_tagged;
ab392d2d 11053 flags = IRQF_SHARED;
fcfa0a32 11054 }
4f125f42
MC		 11055
11056 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 11057}
11058
7938109f
MC		 11059static int tg3_test_interrupt(struct tg3 *tp)
11060{
09943a18 11061 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 11062 struct net_device *dev = tp->dev;
b16250e3 11063 int err, i, intr_ok = 0;
f6eb9b1f 11064 u32 val;
7938109f 11065
d4bc3927
MC		 11066 if (!netif_running(dev))
11067 return -ENODEV;
11068
7938109f
MC		 11069 tg3_disable_ints(tp);
11070
4f125f42 11071 free_irq(tnapi->irq_vec, tnapi);
7938109f 11072
f6eb9b1f
MC		 11073 /*
11074 * Turn off MSI one shot mode. Otherwise this test has no
11075 * observable way to know whether the interrupt was delivered.
11076 */
3aa1cdf8 11077 if (tg3_flag(tp, 57765_PLUS)) {
f6eb9b1f
MC		 11078 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11079 tw32(MSGINT_MODE, val);
11080 }
11081
4f125f42 11082 err = request_irq(tnapi->irq_vec, tg3_test_isr,
f274fd9a 11083 IRQF_SHARED, dev->name, tnapi);
7938109f
MC		 11084 if (err)
11085 return err;
11086
898a56f8 11087 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 11088 tg3_enable_ints(tp);
11089
11090 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 11091 tnapi->coal_now);
7938109f
MC		 11092
11093 for (i = 0; i < 5; i++) {
b16250e3
MC		 11094 u32 int_mbox, misc_host_ctrl;
11095
898a56f8 11096 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 11097 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11098
11099 if ((int_mbox != 0) ||
11100 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11101 intr_ok = 1;
7938109f 11102 break;
b16250e3
MC		 11103 }
11104
3aa1cdf8
MC		 11105 if (tg3_flag(tp, 57765_PLUS) &&
11106 tnapi->hw_status->status_tag != tnapi->last_tag)
11107 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11108
7938109f
MC		 11109 msleep(10);
11110 }
11111
11112 tg3_disable_ints(tp);
11113
4f125f42 11114 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 11115
4f125f42 11116 err = tg3_request_irq(tp, 0);
7938109f
MC		 11117
11118 if (err)
11119 return err;
11120
f6eb9b1f
MC		 11121 if (intr_ok) {
11122 /* Reenable MSI one shot mode. */
5b39de91 11123 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
f6eb9b1f
MC		 11124 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11125 tw32(MSGINT_MODE, val);
11126 }
7938109f 11127 return 0;
f6eb9b1f 11128 }
7938109f
MC		 11129
11130 return -EIO;
11131}
11132
11133/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11134 * successfully restored
11135 */
11136static int tg3_test_msi(struct tg3 *tp)
11137{
7938109f
MC		 11138 int err;
11139 u16 pci_cmd;
11140
63c3a66f 11141 if (!tg3_flag(tp, USING_MSI))
7938109f
MC		 11142 return 0;
11143
11144 /* Turn off SERR reporting in case MSI terminates with Master
11145 * Abort.
11146 */
11147 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11148 pci_write_config_word(tp->pdev, PCI_COMMAND,
11149 pci_cmd & ~PCI_COMMAND_SERR);
11150
11151 err = tg3_test_interrupt(tp);
11152
11153 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11154
11155 if (!err)
11156 return 0;
11157
11158 /* other failures */
11159 if (err != -EIO)
11160 return err;
11161
11162 /* MSI test failed, go back to INTx mode */
5129c3a3
MC		 11163 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11164 "to INTx mode. Please report this failure to the PCI "
11165 "maintainer and include system chipset information\n");
7938109f 11166
4f125f42 11167 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 11168
7938109f
MC		 11169 pci_disable_msi(tp->pdev);
11170
63c3a66f 11171 tg3_flag_clear(tp, USING_MSI);
dc8bf1b1 11172 tp->napi[0].irq_vec = tp->pdev->irq;
7938109f 11173
4f125f42 11174 err = tg3_request_irq(tp, 0);
7938109f
MC		 11175 if (err)
11176 return err;
11177
11178 /* Need to reset the chip because the MSI cycle may have terminated
11179 * with Master Abort.
11180 */
f47c11ee 11181 tg3_full_lock(tp, 1);
7938109f 11182
944d980e 11183 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 11184 err = tg3_init_hw(tp, true);
7938109f 11185
f47c11ee 11186 tg3_full_unlock(tp);
7938109f
MC		 11187
11188 if (err)
4f125f42 11189 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 11190
11191 return err;
11192}
11193
9e9fd12d
MC		 11194static int tg3_request_firmware(struct tg3 *tp)
11195{
77997ea3 11196 const struct tg3_firmware_hdr *fw_hdr;
9e9fd12d
MC		 11197
11198 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 11199 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11200 tp->fw_needed);
9e9fd12d
MC		 11201 return -ENOENT;
11202 }
11203
77997ea3 11204 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
9e9fd12d
MC		 11205
11206 /* Firmware blob starts with version numbers, followed by
11207 * start address and _full_ length including BSS sections
11208 * (which must be longer than the actual data, of course
11209 */
11210
77997ea3
NS		 11211 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11212 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
05dbe005
JP		 11213 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11214 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 11215 release_firmware(tp->fw);
11216 tp->fw = NULL;
11217 return -EINVAL;
11218 }
11219
11220 /* We no longer need firmware; we have it. */
11221 tp->fw_needed = NULL;
11222 return 0;
11223}
11224
9102426a 11225static u32 tg3_irq_count(struct tg3 *tp)
679563f4 11226{
9102426a 11227 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
679563f4 11228
9102426a 11229 if (irq_cnt > 1) {
c3b5003b
MC		 11230 /* We want as many rx rings enabled as there are cpus.
11231 * In multiqueue MSI-X mode, the first MSI-X vector
11232 * only deals with link interrupts, etc, so we add
11233 * one to the number of vectors we are requesting.
11234 */
9102426a 11235 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
c3b5003b 11236 }
679563f4 11237
9102426a
MC		 11238 return irq_cnt;
11239}
11240
11241static bool tg3_enable_msix(struct tg3 *tp)
11242{
11243 int i, rc;
86449944 11244 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
9102426a 11245
0968169c
MC		 11246 tp->txq_cnt = tp->txq_req;
11247 tp->rxq_cnt = tp->rxq_req;
11248 if (!tp->rxq_cnt)
11249 tp->rxq_cnt = netif_get_num_default_rss_queues();
9102426a
MC		 11250 if (tp->rxq_cnt > tp->rxq_max)
11251 tp->rxq_cnt = tp->rxq_max;
cf6d6ea6
MC		 11252
11253 /* Disable multiple TX rings by default. Simple round-robin hardware
11254 * scheduling of the TX rings can cause starvation of rings with
11255 * small packets when other rings have TSO or jumbo packets.
11256 */
11257 if (!tp->txq_req)
11258 tp->txq_cnt = 1;
9102426a
MC		 11259
11260 tp->irq_cnt = tg3_irq_count(tp);
11261
679563f4
MC		 11262 for (i = 0; i < tp->irq_max; i++) {
11263 msix_ent[i].entry = i;
11264 msix_ent[i].vector = 0;
11265 }
11266
11267 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
2430b031
MC		 11268 if (rc < 0) {
11269 return false;
11270 } else if (rc != 0) {
679563f4
MC		 11271 if (pci_enable_msix(tp->pdev, msix_ent, rc))
11272 return false;
05dbe005
JP		 11273 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11274 tp->irq_cnt, rc);
679563f4 11275 tp->irq_cnt = rc;
49a359e3 11276 tp->rxq_cnt = max(rc - 1, 1);
9102426a
MC		 11277 if (tp->txq_cnt)
11278 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
679563f4
MC		 11279 }
11280
11281 for (i = 0; i < tp->irq_max; i++)
11282 tp->napi[i].irq_vec = msix_ent[i].vector;
11283
49a359e3 11284 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
2ddaad39
BH		 11285 pci_disable_msix(tp->pdev);
11286 return false;
11287 }
b92b9040 11288
9102426a
MC		 11289 if (tp->irq_cnt == 1)
11290 return true;
d78b59f5 11291
9102426a
MC		 11292 tg3_flag_set(tp, ENABLE_RSS);
11293
11294 if (tp->txq_cnt > 1)
11295 tg3_flag_set(tp, ENABLE_TSS);
11296
11297 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
2430b031 11298
679563f4
MC		 11299 return true;
11300}
11301
07b0173c
MC		 11302static void tg3_ints_init(struct tg3 *tp)
11303{
63c3a66f
JP		 11304 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11305 !tg3_flag(tp, TAGGED_STATUS)) {
07b0173c
MC		 11306 /* All MSI supporting chips should support tagged
11307 * status. Assert that this is the case.
11308 */
5129c3a3
MC		 11309 netdev_warn(tp->dev,
11310 "MSI without TAGGED_STATUS? Not using MSI\n");
679563f4 11311 goto defcfg;
07b0173c 11312 }
4f125f42 11313
63c3a66f
JP		 11314 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11315 tg3_flag_set(tp, USING_MSIX);
11316 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11317 tg3_flag_set(tp, USING_MSI);
679563f4 11318
63c3a66f 11319 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
679563f4 11320 u32 msi_mode = tr32(MSGINT_MODE);
63c3a66f 11321 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
baf8a94a 11322 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 11323 if (!tg3_flag(tp, 1SHOT_MSI))
11324 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
679563f4
MC		 11325 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11326 }
11327defcfg:
63c3a66f 11328 if (!tg3_flag(tp, USING_MSIX)) {
679563f4
MC		 11329 tp->irq_cnt = 1;
11330 tp->napi[0].irq_vec = tp->pdev->irq;
49a359e3
MC		 11331 }
11332
11333 if (tp->irq_cnt == 1) {
11334 tp->txq_cnt = 1;
11335 tp->rxq_cnt = 1;
2ddaad39 11336 netif_set_real_num_tx_queues(tp->dev, 1);
85407885 11337 netif_set_real_num_rx_queues(tp->dev, 1);
679563f4 11338 }
07b0173c
MC		 11339}
11340
11341static void tg3_ints_fini(struct tg3 *tp)
11342{
63c3a66f 11343 if (tg3_flag(tp, USING_MSIX))
679563f4 11344 pci_disable_msix(tp->pdev);
63c3a66f 11345 else if (tg3_flag(tp, USING_MSI))
679563f4 11346 pci_disable_msi(tp->pdev);
63c3a66f
JP		 11347 tg3_flag_clear(tp, USING_MSI);
11348 tg3_flag_clear(tp, USING_MSIX);
11349 tg3_flag_clear(tp, ENABLE_RSS);
11350 tg3_flag_clear(tp, ENABLE_TSS);
07b0173c
MC		 11351}
11352
be947307
MC		 11353static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11354 bool init)
1da177e4 11355{
d8f4cd38 11356 struct net_device *dev = tp->dev;
4f125f42 11357 int i, err;
1da177e4 11358
679563f4
MC		 11359 /*
11360 * Setup interrupts first so we know how
11361 * many NAPI resources to allocate
11362 */
11363 tg3_ints_init(tp);
11364
90415477 11365 tg3_rss_check_indir_tbl(tp);
bcebcc46 11366
1da177e4
LT		 11367 /* The placement of this call is tied
11368 * to the setup and use of Host TX descriptors.
11369 */
11370 err = tg3_alloc_consistent(tp);
11371 if (err)
4a5f46f2 11372 goto out_ints_fini;
88b06bc2 11373
66cfd1bd
MC		 11374 tg3_napi_init(tp);
11375
fed97810 11376 tg3_napi_enable(tp);
1da177e4 11377
4f125f42
MC		 11378 for (i = 0; i < tp->irq_cnt; i++) {
11379 struct tg3_napi *tnapi = &tp->napi[i];
11380 err = tg3_request_irq(tp, i);
11381 if (err) {
5bc09186
MC		 11382 for (i--; i >= 0; i--) {
11383 tnapi = &tp->napi[i];
4f125f42 11384 free_irq(tnapi->irq_vec, tnapi);
5bc09186 11385 }
4a5f46f2 11386 goto out_napi_fini;
4f125f42
MC		 11387 }
11388 }
1da177e4 11389
f47c11ee 11390 tg3_full_lock(tp, 0);
1da177e4 11391
2e460fc0
NS		 11392 if (init)
11393 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11394
d8f4cd38 11395 err = tg3_init_hw(tp, reset_phy);
1da177e4 11396 if (err) {
944d980e 11397 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11398 tg3_free_rings(tp);
1da177e4
LT		 11399 }
11400
f47c11ee 11401 tg3_full_unlock(tp);
1da177e4 11402
07b0173c 11403 if (err)
4a5f46f2 11404 goto out_free_irq;
1da177e4 11405
d8f4cd38 11406 if (test_irq && tg3_flag(tp, USING_MSI)) {
7938109f 11407 err = tg3_test_msi(tp);
fac9b83e 11408
7938109f 11409 if (err) {
f47c11ee 11410 tg3_full_lock(tp, 0);
944d980e 11411 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 11412 tg3_free_rings(tp);
f47c11ee 11413 tg3_full_unlock(tp);
7938109f 11414
4a5f46f2 11415 goto out_napi_fini;
7938109f 11416 }
fcfa0a32 11417
63c3a66f 11418 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
f6eb9b1f 11419 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 11420
f6eb9b1f
MC		 11421 tw32(PCIE_TRANSACTION_CFG,
11422 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 11423 }
7938109f
MC		 11424 }
11425
b02fd9e3
MC		 11426 tg3_phy_start(tp);
11427
aed93e0b
MC		 11428 tg3_hwmon_open(tp);
11429
f47c11ee 11430 tg3_full_lock(tp, 0);
1da177e4 11431
21f7638e 11432 tg3_timer_start(tp);
63c3a66f 11433 tg3_flag_set(tp, INIT_COMPLETE);
1da177e4
LT		 11434 tg3_enable_ints(tp);
11435
be947307
MC		 11436 if (init)
11437 tg3_ptp_init(tp);
11438 else
11439 tg3_ptp_resume(tp);
11440
11441
f47c11ee 11442 tg3_full_unlock(tp);
1da177e4 11443
fe5f5787 11444 netif_tx_start_all_queues(dev);
1da177e4 11445
06c03c02
MB		 11446 /*
11447 * Reset loopback feature if it was turned on while the device was down
11448 * make sure that it's installed properly now.
11449 */
11450 if (dev->features & NETIF_F_LOOPBACK)
11451 tg3_set_loopback(dev, dev->features);
11452
1da177e4 11453 return 0;
07b0173c 11454
4a5f46f2 11455out_free_irq:
4f125f42
MC		 11456 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11457 struct tg3_napi *tnapi = &tp->napi[i];
11458 free_irq(tnapi->irq_vec, tnapi);
11459 }
07b0173c 11460
4a5f46f2 11461out_napi_fini:
fed97810 11462 tg3_napi_disable(tp);
66cfd1bd 11463 tg3_napi_fini(tp);
07b0173c 11464 tg3_free_consistent(tp);
679563f4 11465
4a5f46f2 11466out_ints_fini:
679563f4 11467 tg3_ints_fini(tp);
d8f4cd38 11468
07b0173c 11469 return err;
1da177e4
LT		 11470}
11471
65138594 11472static void tg3_stop(struct tg3 *tp)
1da177e4 11473{
4f125f42 11474 int i;
1da177e4 11475
db219973 11476 tg3_reset_task_cancel(tp);
bd473da3 11477 tg3_netif_stop(tp);
1da177e4 11478
21f7638e 11479 tg3_timer_stop(tp);
1da177e4 11480
aed93e0b
MC		 11481 tg3_hwmon_close(tp);
11482
24bb4fb6
MC		 11483 tg3_phy_stop(tp);
11484
f47c11ee 11485 tg3_full_lock(tp, 1);
1da177e4
LT		 11486
11487 tg3_disable_ints(tp);
11488
944d980e 11489 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11490 tg3_free_rings(tp);
63c3a66f 11491 tg3_flag_clear(tp, INIT_COMPLETE);
1da177e4 11492
f47c11ee 11493 tg3_full_unlock(tp);
1da177e4 11494
4f125f42
MC		 11495 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11496 struct tg3_napi *tnapi = &tp->napi[i];
11497 free_irq(tnapi->irq_vec, tnapi);
11498 }
07b0173c
MC		 11499
11500 tg3_ints_fini(tp);
1da177e4 11501
66cfd1bd
MC		 11502 tg3_napi_fini(tp);
11503
1da177e4 11504 tg3_free_consistent(tp);
65138594
MC		 11505}
11506
d8f4cd38
MC		 11507static int tg3_open(struct net_device *dev)
11508{
11509 struct tg3 *tp = netdev_priv(dev);
11510 int err;
11511
11512 if (tp->fw_needed) {
11513 err = tg3_request_firmware(tp);
c4dab506
NS		 11514 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11515 if (err) {
11516 netdev_warn(tp->dev, "EEE capability disabled\n");
11517 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11518 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11519 netdev_warn(tp->dev, "EEE capability restored\n");
11520 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11521 }
11522 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
d8f4cd38
MC		 11523 if (err)
11524 return err;
11525 } else if (err) {
11526 netdev_warn(tp->dev, "TSO capability disabled\n");
11527 tg3_flag_clear(tp, TSO_CAPABLE);
11528 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11529 netdev_notice(tp->dev, "TSO capability restored\n");
11530 tg3_flag_set(tp, TSO_CAPABLE);
11531 }
11532 }
11533
f4a46d1f 11534 tg3_carrier_off(tp);
d8f4cd38
MC		 11535
11536 err = tg3_power_up(tp);
11537 if (err)
11538 return err;
11539
11540 tg3_full_lock(tp, 0);
11541
11542 tg3_disable_ints(tp);
11543 tg3_flag_clear(tp, INIT_COMPLETE);
11544
11545 tg3_full_unlock(tp);
11546
942d1af0
NS		 11547 err = tg3_start(tp,
11548 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11549 true, true);
d8f4cd38
MC		 11550 if (err) {
11551 tg3_frob_aux_power(tp, false);
11552 pci_set_power_state(tp->pdev, PCI_D3hot);
11553 }
be947307 11554
7d41e49a
MC		 11555 if (tg3_flag(tp, PTP_CAPABLE)) {
11556 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11557 &tp->pdev->dev);
11558 if (IS_ERR(tp->ptp_clock))
11559 tp->ptp_clock = NULL;
11560 }
11561
07b0173c 11562 return err;
1da177e4
LT		 11563}
11564
1da177e4
LT		 11565static int tg3_close(struct net_device *dev)
11566{
11567 struct tg3 *tp = netdev_priv(dev);
11568
be947307
MC		 11569 tg3_ptp_fini(tp);
11570
65138594 11571 tg3_stop(tp);
1da177e4 11572
92feeabf
MC		 11573 /* Clear stats across close / open calls */
11574 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11575 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
1da177e4 11576
5137a2ee 11577 tg3_power_down_prepare(tp);
bc1c7567 11578
f4a46d1f 11579 tg3_carrier_off(tp);
bc1c7567 11580
1da177e4
LT		 11581 return 0;
11582}
11583
511d2224 11584static inline u64 get_stat64(tg3_stat64_t *val)
816f8b86
SB		 11585{
11586 return ((u64)val->high << 32) | ((u64)val->low);
11587}
11588
65ec698d 11589static u64 tg3_calc_crc_errors(struct tg3 *tp)
1da177e4
LT		 11590{
11591 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11592
f07e9af3 11593 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a
JP		 11594 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11595 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 11596 u32 val;
11597
569a5df8
MC		 11598 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11599 tg3_writephy(tp, MII_TG3_TEST1,
11600 val | MII_TG3_TEST1_CRC_EN);
f08aa1a8 11601 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
1da177e4
LT		 11602 } else
11603 val = 0;
1da177e4
LT		 11604
11605 tp->phy_crc_errors += val;
11606
11607 return tp->phy_crc_errors;
11608 }
11609
11610 return get_stat64(&hw_stats->rx_fcs_errors);
11611}
11612
11613#define ESTAT_ADD(member) \
11614 estats->member = old_estats->member + \
511d2224 11615 get_stat64(&hw_stats->member)
1da177e4 11616
65ec698d 11617static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
1da177e4 11618{
1da177e4
LT		 11619 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11620 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11621
1da177e4
LT		 11622 ESTAT_ADD(rx_octets);
11623 ESTAT_ADD(rx_fragments);
11624 ESTAT_ADD(rx_ucast_packets);
11625 ESTAT_ADD(rx_mcast_packets);
11626 ESTAT_ADD(rx_bcast_packets);
11627 ESTAT_ADD(rx_fcs_errors);
11628 ESTAT_ADD(rx_align_errors);
11629 ESTAT_ADD(rx_xon_pause_rcvd);
11630 ESTAT_ADD(rx_xoff_pause_rcvd);
11631 ESTAT_ADD(rx_mac_ctrl_rcvd);
11632 ESTAT_ADD(rx_xoff_entered);
11633 ESTAT_ADD(rx_frame_too_long_errors);
11634 ESTAT_ADD(rx_jabbers);
11635 ESTAT_ADD(rx_undersize_packets);
11636 ESTAT_ADD(rx_in_length_errors);
11637 ESTAT_ADD(rx_out_length_errors);
11638 ESTAT_ADD(rx_64_or_less_octet_packets);
11639 ESTAT_ADD(rx_65_to_127_octet_packets);
11640 ESTAT_ADD(rx_128_to_255_octet_packets);
11641 ESTAT_ADD(rx_256_to_511_octet_packets);
11642 ESTAT_ADD(rx_512_to_1023_octet_packets);
11643 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11644 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11645 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11646 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11647 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11648
11649 ESTAT_ADD(tx_octets);
11650 ESTAT_ADD(tx_collisions);
11651 ESTAT_ADD(tx_xon_sent);
11652 ESTAT_ADD(tx_xoff_sent);
11653 ESTAT_ADD(tx_flow_control);
11654 ESTAT_ADD(tx_mac_errors);
11655 ESTAT_ADD(tx_single_collisions);
11656 ESTAT_ADD(tx_mult_collisions);
11657 ESTAT_ADD(tx_deferred);
11658 ESTAT_ADD(tx_excessive_collisions);
11659 ESTAT_ADD(tx_late_collisions);
11660 ESTAT_ADD(tx_collide_2times);
11661 ESTAT_ADD(tx_collide_3times);
11662 ESTAT_ADD(tx_collide_4times);
11663 ESTAT_ADD(tx_collide_5times);
11664 ESTAT_ADD(tx_collide_6times);
11665 ESTAT_ADD(tx_collide_7times);
11666 ESTAT_ADD(tx_collide_8times);
11667 ESTAT_ADD(tx_collide_9times);
11668 ESTAT_ADD(tx_collide_10times);
11669 ESTAT_ADD(tx_collide_11times);
11670 ESTAT_ADD(tx_collide_12times);
11671 ESTAT_ADD(tx_collide_13times);
11672 ESTAT_ADD(tx_collide_14times);
11673 ESTAT_ADD(tx_collide_15times);
11674 ESTAT_ADD(tx_ucast_packets);
11675 ESTAT_ADD(tx_mcast_packets);
11676 ESTAT_ADD(tx_bcast_packets);
11677 ESTAT_ADD(tx_carrier_sense_errors);
11678 ESTAT_ADD(tx_discards);
11679 ESTAT_ADD(tx_errors);
11680
11681 ESTAT_ADD(dma_writeq_full);
11682 ESTAT_ADD(dma_write_prioq_full);
11683 ESTAT_ADD(rxbds_empty);
11684 ESTAT_ADD(rx_discards);
11685 ESTAT_ADD(rx_errors);
11686 ESTAT_ADD(rx_threshold_hit);
11687
11688 ESTAT_ADD(dma_readq_full);
11689 ESTAT_ADD(dma_read_prioq_full);
11690 ESTAT_ADD(tx_comp_queue_full);
11691
11692 ESTAT_ADD(ring_set_send_prod_index);
11693 ESTAT_ADD(ring_status_update);
11694 ESTAT_ADD(nic_irqs);
11695 ESTAT_ADD(nic_avoided_irqs);
11696 ESTAT_ADD(nic_tx_threshold_hit);
11697
4452d099 11698 ESTAT_ADD(mbuf_lwm_thresh_hit);
1da177e4
LT		 11699}
11700
65ec698d 11701static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
1da177e4 11702{
511d2224 11703 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
1da177e4
LT		 11704 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11705
1da177e4
LT		 11706 stats->rx_packets = old_stats->rx_packets +
11707 get_stat64(&hw_stats->rx_ucast_packets) +
11708 get_stat64(&hw_stats->rx_mcast_packets) +
11709 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 11710
1da177e4
LT		 11711 stats->tx_packets = old_stats->tx_packets +
11712 get_stat64(&hw_stats->tx_ucast_packets) +
11713 get_stat64(&hw_stats->tx_mcast_packets) +
11714 get_stat64(&hw_stats->tx_bcast_packets);
11715
11716 stats->rx_bytes = old_stats->rx_bytes +
11717 get_stat64(&hw_stats->rx_octets);
11718 stats->tx_bytes = old_stats->tx_bytes +
11719 get_stat64(&hw_stats->tx_octets);
11720
11721 stats->rx_errors = old_stats->rx_errors +
4f63b877 11722 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 11723 stats->tx_errors = old_stats->tx_errors +
11724 get_stat64(&hw_stats->tx_errors) +
11725 get_stat64(&hw_stats->tx_mac_errors) +
11726 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11727 get_stat64(&hw_stats->tx_discards);
11728
11729 stats->multicast = old_stats->multicast +
11730 get_stat64(&hw_stats->rx_mcast_packets);
11731 stats->collisions = old_stats->collisions +
11732 get_stat64(&hw_stats->tx_collisions);
11733
11734 stats->rx_length_errors = old_stats->rx_length_errors +
11735 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11736 get_stat64(&hw_stats->rx_undersize_packets);
11737
11738 stats->rx_over_errors = old_stats->rx_over_errors +
11739 get_stat64(&hw_stats->rxbds_empty);
11740 stats->rx_frame_errors = old_stats->rx_frame_errors +
11741 get_stat64(&hw_stats->rx_align_errors);
11742 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11743 get_stat64(&hw_stats->tx_discards);
11744 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11745 get_stat64(&hw_stats->tx_carrier_sense_errors);
11746
11747 stats->rx_crc_errors = old_stats->rx_crc_errors +
65ec698d 11748 tg3_calc_crc_errors(tp);
1da177e4 11749
4f63b877
JL		 11750 stats->rx_missed_errors = old_stats->rx_missed_errors +
11751 get_stat64(&hw_stats->rx_discards);
11752
b0057c51 11753 stats->rx_dropped = tp->rx_dropped;
48855432 11754 stats->tx_dropped = tp->tx_dropped;
1da177e4
LT		 11755}
11756
1da177e4
LT		 11757static int tg3_get_regs_len(struct net_device *dev)
11758{
97bd8e49 11759 return TG3_REG_BLK_SIZE;
1da177e4
LT		 11760}
11761
11762static void tg3_get_regs(struct net_device *dev,
11763 struct ethtool_regs *regs, void *_p)
11764{
1da177e4 11765 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 11766
11767 regs->version = 0;
11768
97bd8e49 11769 memset(_p, 0, TG3_REG_BLK_SIZE);
1da177e4 11770
80096068 11771 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
bc1c7567
MC		 11772 return;
11773
f47c11ee 11774 tg3_full_lock(tp, 0);
1da177e4 11775
97bd8e49 11776 tg3_dump_legacy_regs(tp, (u32 *)_p);
1da177e4 11777
f47c11ee 11778 tg3_full_unlock(tp);
1da177e4
LT		 11779}
11780
11781static int tg3_get_eeprom_len(struct net_device *dev)
11782{
11783 struct tg3 *tp = netdev_priv(dev);
11784
11785 return tp->nvram_size;
11786}
11787
1da177e4
LT		 11788static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11789{
11790 struct tg3 *tp = netdev_priv(dev);
11791 int ret;
11792 u8 *pd;
b9fc7dc5 11793 u32 i, offset, len, b_offset, b_count;
a9dc529d 11794 __be32 val;
1da177e4 11795
63c3a66f 11796 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 11797 return -EINVAL;
11798
1da177e4
LT		 11799 offset = eeprom->offset;
11800 len = eeprom->len;
11801 eeprom->len = 0;
11802
11803 eeprom->magic = TG3_EEPROM_MAGIC;
11804
11805 if (offset & 3) {
11806 /* adjustments to start on required 4 byte boundary */
11807 b_offset = offset & 3;
11808 b_count = 4 - b_offset;
11809 if (b_count > len) {
11810 /* i.e. offset=1 len=2 */
11811 b_count = len;
11812 }
a9dc529d 11813 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 11814 if (ret)
11815 return ret;
be98da6a 11816 memcpy(data, ((char *)&val) + b_offset, b_count);
1da177e4
LT		 11817 len -= b_count;
11818 offset += b_count;
c6cdf436 11819 eeprom->len += b_count;
1da177e4
LT		 11820 }
11821
25985edc 11822 /* read bytes up to the last 4 byte boundary */
1da177e4
LT		 11823 pd = &data[eeprom->len];
11824 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 11825 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 11826 if (ret) {
11827 eeprom->len += i;
11828 return ret;
11829 }
1da177e4
LT		 11830 memcpy(pd + i, &val, 4);
11831 }
11832 eeprom->len += i;
11833
11834 if (len & 3) {
11835 /* read last bytes not ending on 4 byte boundary */
11836 pd = &data[eeprom->len];
11837 b_count = len & 3;
11838 b_offset = offset + len - b_count;
a9dc529d 11839 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 11840 if (ret)
11841 return ret;
b9fc7dc5 11842 memcpy(pd, &val, b_count);
1da177e4
LT		 11843 eeprom->len += b_count;
11844 }
11845 return 0;
11846}
11847
1da177e4
LT		 11848static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11849{
11850 struct tg3 *tp = netdev_priv(dev);
11851 int ret;
b9fc7dc5 11852 u32 offset, len, b_offset, odd_len;
1da177e4 11853 u8 *buf;
a9dc529d 11854 __be32 start, end;
1da177e4 11855
63c3a66f 11856 if (tg3_flag(tp, NO_NVRAM) ||
df259d8c 11857 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 11858 return -EINVAL;
11859
11860 offset = eeprom->offset;
11861 len = eeprom->len;
11862
11863 if ((b_offset = (offset & 3))) {
11864 /* adjustments to start on required 4 byte boundary */
a9dc529d 11865 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 11866 if (ret)
11867 return ret;
1da177e4
LT		 11868 len += b_offset;
11869 offset &= ~3;
1c8594b4
MC		 11870 if (len < 4)
11871 len = 4;
1da177e4
LT		 11872 }
11873
11874 odd_len = 0;
1c8594b4 11875 if (len & 3) {
1da177e4
LT		 11876 /* adjustments to end on required 4 byte boundary */
11877 odd_len = 1;
11878 len = (len + 3) & ~3;
a9dc529d 11879 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 11880 if (ret)
11881 return ret;
1da177e4
LT		 11882 }
11883
11884 buf = data;
11885 if (b_offset || odd_len) {
11886 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 11887 if (!buf)
1da177e4
LT		 11888 return -ENOMEM;
11889 if (b_offset)
11890 memcpy(buf, &start, 4);
11891 if (odd_len)
11892 memcpy(buf+len-4, &end, 4);
11893 memcpy(buf + b_offset, data, eeprom->len);
11894 }
11895
11896 ret = tg3_nvram_write_block(tp, offset, len, buf);
11897
11898 if (buf != data)
11899 kfree(buf);
11900
11901 return ret;
11902}
11903
11904static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11905{
b02fd9e3
MC		 11906 struct tg3 *tp = netdev_priv(dev);
11907
63c3a66f 11908 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 11909 struct phy_device *phydev;
f07e9af3 11910 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 11911 return -EAGAIN;
3f0e3ad7
MC		 11912 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11913 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 11914 }
6aa20a22 11915
1da177e4
LT		 11916 cmd->supported = (SUPPORTED_Autoneg);
11917
f07e9af3 11918 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
1da177e4
LT		 11919 cmd->supported |= (SUPPORTED_1000baseT_Half |
11920 SUPPORTED_1000baseT_Full);
11921
f07e9af3 11922 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
1da177e4
LT		 11923 cmd->supported |= (SUPPORTED_100baseT_Half |
11924 SUPPORTED_100baseT_Full |
11925 SUPPORTED_10baseT_Half |
11926 SUPPORTED_10baseT_Full |
3bebab59 11927 SUPPORTED_TP);
ef348144
KK		 11928 cmd->port = PORT_TP;
11929 } else {
1da177e4 11930 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 11931 cmd->port = PORT_FIBRE;
11932 }
6aa20a22 11933
1da177e4 11934 cmd->advertising = tp->link_config.advertising;
5bb09778
MC		 11935 if (tg3_flag(tp, PAUSE_AUTONEG)) {
11936 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
11937 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11938 cmd->advertising |= ADVERTISED_Pause;
11939 } else {
11940 cmd->advertising |= ADVERTISED_Pause |
11941 ADVERTISED_Asym_Pause;
11942 }
11943 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11944 cmd->advertising |= ADVERTISED_Asym_Pause;
11945 }
11946 }
f4a46d1f 11947 if (netif_running(dev) && tp->link_up) {
70739497 11948 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
1da177e4 11949 cmd->duplex = tp->link_config.active_duplex;
859edb26 11950 cmd->lp_advertising = tp->link_config.rmt_adv;
e348c5e7
MC		 11951 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
11952 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
11953 cmd->eth_tp_mdix = ETH_TP_MDI_X;
11954 else
11955 cmd->eth_tp_mdix = ETH_TP_MDI;
11956 }
64c22182 11957 } else {
e740522e
MC		 11958 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
11959 cmd->duplex = DUPLEX_UNKNOWN;
e348c5e7 11960 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
1da177e4 11961 }
882e9793 11962 cmd->phy_address = tp->phy_addr;
7e5856bd 11963 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 11964 cmd->autoneg = tp->link_config.autoneg;
11965 cmd->maxtxpkt = 0;
11966 cmd->maxrxpkt = 0;
11967 return 0;
11968}
6aa20a22 11969
1da177e4
LT		 11970static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11971{
11972 struct tg3 *tp = netdev_priv(dev);
25db0338 11973 u32 speed = ethtool_cmd_speed(cmd);
6aa20a22 11974
63c3a66f 11975 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 11976 struct phy_device *phydev;
f07e9af3 11977 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 11978 return -EAGAIN;
3f0e3ad7
MC		 11979 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11980 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 11981 }
11982
7e5856bd
MC		 11983 if (cmd->autoneg != AUTONEG_ENABLE &&
11984 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 11985 return -EINVAL;
7e5856bd
MC		 11986
11987 if (cmd->autoneg == AUTONEG_DISABLE &&
11988 cmd->duplex != DUPLEX_FULL &&
11989 cmd->duplex != DUPLEX_HALF)
37ff238d 11990 return -EINVAL;
1da177e4 11991
7e5856bd
MC		 11992 if (cmd->autoneg == AUTONEG_ENABLE) {
11993 u32 mask = ADVERTISED_Autoneg |
11994 ADVERTISED_Pause |
11995 ADVERTISED_Asym_Pause;
11996
f07e9af3 11997 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
7e5856bd
MC		 11998 mask |= ADVERTISED_1000baseT_Half |
11999 ADVERTISED_1000baseT_Full;
12000
f07e9af3 12001 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
7e5856bd
MC		 12002 mask |= ADVERTISED_100baseT_Half |
12003 ADVERTISED_100baseT_Full |
12004 ADVERTISED_10baseT_Half |
12005 ADVERTISED_10baseT_Full |
12006 ADVERTISED_TP;
12007 else
12008 mask |= ADVERTISED_FIBRE;
12009
12010 if (cmd->advertising & ~mask)
12011 return -EINVAL;
12012
12013 mask &= (ADVERTISED_1000baseT_Half |
12014 ADVERTISED_1000baseT_Full |
12015 ADVERTISED_100baseT_Half |
12016 ADVERTISED_100baseT_Full |
12017 ADVERTISED_10baseT_Half |
12018 ADVERTISED_10baseT_Full);
12019
12020 cmd->advertising &= mask;
12021 } else {
f07e9af3 12022 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
25db0338 12023 if (speed != SPEED_1000)
7e5856bd
MC		 12024 return -EINVAL;
12025
12026 if (cmd->duplex != DUPLEX_FULL)
12027 return -EINVAL;
12028 } else {
25db0338
DD		 12029 if (speed != SPEED_100 &&
12030 speed != SPEED_10)
7e5856bd
MC		 12031 return -EINVAL;
12032 }
12033 }
12034
f47c11ee 12035 tg3_full_lock(tp, 0);
1da177e4
LT		 12036
12037 tp->link_config.autoneg = cmd->autoneg;
12038 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 12039 tp->link_config.advertising = (cmd->advertising |
12040 ADVERTISED_Autoneg);
e740522e
MC		 12041 tp->link_config.speed = SPEED_UNKNOWN;
12042 tp->link_config.duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 12043 } else {
12044 tp->link_config.advertising = 0;
25db0338 12045 tp->link_config.speed = speed;
1da177e4 12046 tp->link_config.duplex = cmd->duplex;
b02fd9e3 12047 }
6aa20a22 12048
fdad8de4
NS		 12049 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12050
ce20f161
NS		 12051 tg3_warn_mgmt_link_flap(tp);
12052
1da177e4 12053 if (netif_running(dev))
953c96e0 12054 tg3_setup_phy(tp, true);
1da177e4 12055
f47c11ee 12056 tg3_full_unlock(tp);
6aa20a22 12057
1da177e4
LT		 12058 return 0;
12059}
6aa20a22 12060
1da177e4
LT		 12061static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12062{
12063 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12064
68aad78c
RJ		 12065 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12066 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12067 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12068 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
1da177e4 12069}
6aa20a22 12070
1da177e4
LT		 12071static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12072{
12073 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12074
63c3a66f 12075 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 12076 wol->supported = WAKE_MAGIC;
12077 else
12078 wol->supported = 0;
1da177e4 12079 wol->wolopts = 0;
63c3a66f 12080 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 12081 wol->wolopts = WAKE_MAGIC;
12082 memset(&wol->sopass, 0, sizeof(wol->sopass));
12083}
6aa20a22 12084
1da177e4
LT		 12085static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12086{
12087 struct tg3 *tp = netdev_priv(dev);
12dac075 12088 struct device *dp = &tp->pdev->dev;
6aa20a22 12089
1da177e4
LT		 12090 if (wol->wolopts & ~WAKE_MAGIC)
12091 return -EINVAL;
12092 if ((wol->wolopts & WAKE_MAGIC) &&
63c3a66f 12093 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
1da177e4 12094 return -EINVAL;
6aa20a22 12095
f2dc0d18
RW		 12096 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12097
f47c11ee 12098 spin_lock_bh(&tp->lock);
f2dc0d18 12099 if (device_may_wakeup(dp))
63c3a66f 12100 tg3_flag_set(tp, WOL_ENABLE);
f2dc0d18 12101 else
63c3a66f 12102 tg3_flag_clear(tp, WOL_ENABLE);
f47c11ee 12103 spin_unlock_bh(&tp->lock);
6aa20a22 12104
1da177e4
LT		 12105 return 0;
12106}
6aa20a22 12107
1da177e4
LT		 12108static u32 tg3_get_msglevel(struct net_device *dev)
12109{
12110 struct tg3 *tp = netdev_priv(dev);
12111 return tp->msg_enable;
12112}
6aa20a22 12113
1da177e4
LT		 12114static void tg3_set_msglevel(struct net_device *dev, u32 value)
12115{
12116 struct tg3 *tp = netdev_priv(dev);
12117 tp->msg_enable = value;
12118}
6aa20a22 12119
1da177e4
LT		 12120static int tg3_nway_reset(struct net_device *dev)
12121{
12122 struct tg3 *tp = netdev_priv(dev);
1da177e4 12123 int r;
6aa20a22 12124
1da177e4
LT		 12125 if (!netif_running(dev))
12126 return -EAGAIN;
12127
f07e9af3 12128 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
c94e3941
MC		 12129 return -EINVAL;
12130
ce20f161
NS		 12131 tg3_warn_mgmt_link_flap(tp);
12132
63c3a66f 12133 if (tg3_flag(tp, USE_PHYLIB)) {
f07e9af3 12134 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12135 return -EAGAIN;
3f0e3ad7 12136 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 12137 } else {
12138 u32 bmcr;
12139
12140 spin_lock_bh(&tp->lock);
12141 r = -EINVAL;
12142 tg3_readphy(tp, MII_BMCR, &bmcr);
12143 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12144 ((bmcr & BMCR_ANENABLE) ||
f07e9af3 12145 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
b02fd9e3
MC		 12146 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12147 BMCR_ANENABLE);
12148 r = 0;
12149 }
12150 spin_unlock_bh(&tp->lock);
1da177e4 12151 }
6aa20a22 12152
1da177e4
LT		 12153 return r;
12154}
6aa20a22 12155
1da177e4
LT		 12156static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12157{
12158 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12159
2c49a44d 12160 ering->rx_max_pending = tp->rx_std_ring_mask;
63c3a66f 12161 if (tg3_flag(tp, JUMBO_RING_ENABLE))
2c49a44d 12162 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
4f81c32b
MC		 12163 else
12164 ering->rx_jumbo_max_pending = 0;
12165
12166 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 12167
12168 ering->rx_pending = tp->rx_pending;
63c3a66f 12169 if (tg3_flag(tp, JUMBO_RING_ENABLE))
4f81c32b
MC		 12170 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12171 else
12172 ering->rx_jumbo_pending = 0;
12173
f3f3f27e 12174 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 12175}
6aa20a22 12176
1da177e4
LT		 12177static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12178{
12179 struct tg3 *tp = netdev_priv(dev);
646c9edd 12180 int i, irq_sync = 0, err = 0;
6aa20a22 12181
2c49a44d
MC		 12182 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12183 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
bc3a9254
MC		 12184 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12185 (ering->tx_pending <= MAX_SKB_FRAGS) ||
63c3a66f 12186 (tg3_flag(tp, TSO_BUG) &&
bc3a9254 12187 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 12188 return -EINVAL;
6aa20a22 12189
bbe832c0 12190 if (netif_running(dev)) {
b02fd9e3 12191 tg3_phy_stop(tp);
1da177e4 12192 tg3_netif_stop(tp);
bbe832c0
MC		 12193 irq_sync = 1;
12194 }
1da177e4 12195
bbe832c0 12196 tg3_full_lock(tp, irq_sync);
6aa20a22 12197
1da177e4
LT		 12198 tp->rx_pending = ering->rx_pending;
12199
63c3a66f 12200 if (tg3_flag(tp, MAX_RXPEND_64) &&
1da177e4
LT		 12201 tp->rx_pending > 63)
12202 tp->rx_pending = 63;
12203 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd 12204
6fd45cb8 12205 for (i = 0; i < tp->irq_max; i++)
646c9edd 12206 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 12207
12208 if (netif_running(dev)) {
944d980e 12209 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12210 err = tg3_restart_hw(tp, false);
b9ec6c1b
MC		 12211 if (!err)
12212 tg3_netif_start(tp);
1da177e4
LT		 12213 }
12214
f47c11ee 12215 tg3_full_unlock(tp);
6aa20a22 12216
b02fd9e3
MC		 12217 if (irq_sync && !err)
12218 tg3_phy_start(tp);
12219
b9ec6c1b 12220 return err;
1da177e4 12221}
6aa20a22 12222
1da177e4
LT		 12223static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12224{
12225 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12226
63c3a66f 12227 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
8d018621 12228
4a2db503 12229 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
8d018621
MC		 12230 epause->rx_pause = 1;
12231 else
12232 epause->rx_pause = 0;
12233
4a2db503 12234 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
8d018621
MC		 12235 epause->tx_pause = 1;
12236 else
12237 epause->tx_pause = 0;
1da177e4 12238}
6aa20a22 12239
1da177e4
LT		 12240static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12241{
12242 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 12243 int err = 0;
6aa20a22 12244
ce20f161
NS		 12245 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12246 tg3_warn_mgmt_link_flap(tp);
12247
63c3a66f 12248 if (tg3_flag(tp, USE_PHYLIB)) {
2712168f
MC		 12249 u32 newadv;
12250 struct phy_device *phydev;
1da177e4 12251
2712168f 12252 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
f47c11ee 12253
2712168f
MC		 12254 if (!(phydev->supported & SUPPORTED_Pause) ||
12255 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
2259dca3 12256 (epause->rx_pause != epause->tx_pause)))
2712168f 12257 return -EINVAL;
1da177e4 12258
2712168f
MC		 12259 tp->link_config.flowctrl = 0;
12260 if (epause->rx_pause) {
12261 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12262
12263 if (epause->tx_pause) {
12264 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12265 newadv = ADVERTISED_Pause;
b02fd9e3 12266 } else
2712168f
MC		 12267 newadv = ADVERTISED_Pause |
12268 ADVERTISED_Asym_Pause;
12269 } else if (epause->tx_pause) {
12270 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12271 newadv = ADVERTISED_Asym_Pause;
12272 } else
12273 newadv = 0;
12274
12275 if (epause->autoneg)
63c3a66f 12276 tg3_flag_set(tp, PAUSE_AUTONEG);
2712168f 12277 else
63c3a66f 12278 tg3_flag_clear(tp, PAUSE_AUTONEG);
2712168f 12279
f07e9af3 12280 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2712168f
MC		 12281 u32 oldadv = phydev->advertising &
12282 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12283 if (oldadv != newadv) {
12284 phydev->advertising &=
12285 ~(ADVERTISED_Pause |
12286 ADVERTISED_Asym_Pause);
12287 phydev->advertising |= newadv;
12288 if (phydev->autoneg) {
12289 /*
12290 * Always renegotiate the link to
12291 * inform our link partner of our
12292 * flow control settings, even if the
12293 * flow control is forced. Let
12294 * tg3_adjust_link() do the final
12295 * flow control setup.
12296 */
12297 return phy_start_aneg(phydev);
b02fd9e3 12298 }
b02fd9e3 12299 }
b02fd9e3 12300
2712168f 12301 if (!epause->autoneg)
b02fd9e3 12302 tg3_setup_flow_control(tp, 0, 0);
2712168f 12303 } else {
c6700ce2 12304 tp->link_config.advertising &=
2712168f
MC		 12305 ~(ADVERTISED_Pause |
12306 ADVERTISED_Asym_Pause);
c6700ce2 12307 tp->link_config.advertising |= newadv;
b02fd9e3
MC		 12308 }
12309 } else {
12310 int irq_sync = 0;
12311
12312 if (netif_running(dev)) {
12313 tg3_netif_stop(tp);
12314 irq_sync = 1;
12315 }
12316
12317 tg3_full_lock(tp, irq_sync);
12318
12319 if (epause->autoneg)
63c3a66f 12320 tg3_flag_set(tp, PAUSE_AUTONEG);
b02fd9e3 12321 else
63c3a66f 12322 tg3_flag_clear(tp, PAUSE_AUTONEG);
b02fd9e3 12323 if (epause->rx_pause)
e18ce346 12324 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 12325 else
e18ce346 12326 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 12327 if (epause->tx_pause)
e18ce346 12328 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 12329 else
e18ce346 12330 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 12331
12332 if (netif_running(dev)) {
12333 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12334 err = tg3_restart_hw(tp, false);
b02fd9e3
MC		 12335 if (!err)
12336 tg3_netif_start(tp);
12337 }
12338
12339 tg3_full_unlock(tp);
12340 }
6aa20a22 12341
fdad8de4
NS		 12342 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12343
b9ec6c1b 12344 return err;
1da177e4 12345}
6aa20a22 12346
de6f31eb 12347static int tg3_get_sset_count(struct net_device *dev, int sset)
1da177e4 12348{
b9f2c044
JG		 12349 switch (sset) {
12350 case ETH_SS_TEST:
12351 return TG3_NUM_TEST;
12352 case ETH_SS_STATS:
12353 return TG3_NUM_STATS;
12354 default:
12355 return -EOPNOTSUPP;
12356 }
4cafd3f5
MC		 12357}
12358
90415477
MC		 12359static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12360 u32 *rules __always_unused)
12361{
12362 struct tg3 *tp = netdev_priv(dev);
12363
12364 if (!tg3_flag(tp, SUPPORT_MSIX))
12365 return -EOPNOTSUPP;
12366
12367 switch (info->cmd) {
12368 case ETHTOOL_GRXRINGS:
12369 if (netif_running(tp->dev))
9102426a 12370 info->data = tp->rxq_cnt;
90415477
MC		 12371 else {
12372 info->data = num_online_cpus();
9102426a
MC		 12373 if (info->data > TG3_RSS_MAX_NUM_QS)
12374 info->data = TG3_RSS_MAX_NUM_QS;
90415477
MC		 12375 }
12376
12377 /* The first interrupt vector only
12378 * handles link interrupts.
12379 */
12380 info->data -= 1;
12381 return 0;
12382
12383 default:
12384 return -EOPNOTSUPP;
12385 }
12386}
12387
12388static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12389{
12390 u32 size = 0;
12391 struct tg3 *tp = netdev_priv(dev);
12392
12393 if (tg3_flag(tp, SUPPORT_MSIX))
12394 size = TG3_RSS_INDIR_TBL_SIZE;
12395
12396 return size;
12397}
12398
12399static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
12400{
12401 struct tg3 *tp = netdev_priv(dev);
12402 int i;
12403
12404 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12405 indir[i] = tp->rss_ind_tbl[i];
12406
12407 return 0;
12408}
12409
12410static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
12411{
12412 struct tg3 *tp = netdev_priv(dev);
12413 size_t i;
12414
12415 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12416 tp->rss_ind_tbl[i] = indir[i];
12417
12418 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12419 return 0;
12420
12421 /* It is legal to write the indirection
12422 * table while the device is running.
12423 */
12424 tg3_full_lock(tp, 0);
12425 tg3_rss_write_indir_tbl(tp);
12426 tg3_full_unlock(tp);
12427
12428 return 0;
12429}
12430
0968169c
MC		 12431static void tg3_get_channels(struct net_device *dev,
12432 struct ethtool_channels *channel)
12433{
12434 struct tg3 *tp = netdev_priv(dev);
12435 u32 deflt_qs = netif_get_num_default_rss_queues();
12436
12437 channel->max_rx = tp->rxq_max;
12438 channel->max_tx = tp->txq_max;
12439
12440 if (netif_running(dev)) {
12441 channel->rx_count = tp->rxq_cnt;
12442 channel->tx_count = tp->txq_cnt;
12443 } else {
12444 if (tp->rxq_req)
12445 channel->rx_count = tp->rxq_req;
12446 else
12447 channel->rx_count = min(deflt_qs, tp->rxq_max);
12448
12449 if (tp->txq_req)
12450 channel->tx_count = tp->txq_req;
12451 else
12452 channel->tx_count = min(deflt_qs, tp->txq_max);
12453 }
12454}
12455
12456static int tg3_set_channels(struct net_device *dev,
12457 struct ethtool_channels *channel)
12458{
12459 struct tg3 *tp = netdev_priv(dev);
12460
12461 if (!tg3_flag(tp, SUPPORT_MSIX))
12462 return -EOPNOTSUPP;
12463
12464 if (channel->rx_count > tp->rxq_max ||
12465 channel->tx_count > tp->txq_max)
12466 return -EINVAL;
12467
12468 tp->rxq_req = channel->rx_count;
12469 tp->txq_req = channel->tx_count;
12470
12471 if (!netif_running(dev))
12472 return 0;
12473
12474 tg3_stop(tp);
12475
f4a46d1f 12476 tg3_carrier_off(tp);
0968169c 12477
be947307 12478 tg3_start(tp, true, false, false);
0968169c
MC		 12479
12480 return 0;
12481}
12482
de6f31eb 12483static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1da177e4
LT		 12484{
12485 switch (stringset) {
12486 case ETH_SS_STATS:
12487 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
12488 break;
4cafd3f5
MC		 12489 case ETH_SS_TEST:
12490 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
12491 break;
1da177e4
LT		 12492 default:
12493 WARN_ON(1); /* we need a WARN() */
12494 break;
12495 }
12496}
12497
81b8709c 12498static int tg3_set_phys_id(struct net_device *dev,
12499 enum ethtool_phys_id_state state)
4009a93d
MC		 12500{
12501 struct tg3 *tp = netdev_priv(dev);
4009a93d
MC		 12502
12503 if (!netif_running(tp->dev))
12504 return -EAGAIN;
12505
81b8709c 12506 switch (state) {
12507 case ETHTOOL_ID_ACTIVE:
fce55922 12508 return 1; /* cycle on/off once per second */
4009a93d 12509
81b8709c 12510 case ETHTOOL_ID_ON:
12511 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12512 LED_CTRL_1000MBPS_ON |
12513 LED_CTRL_100MBPS_ON |
12514 LED_CTRL_10MBPS_ON |
12515 LED_CTRL_TRAFFIC_OVERRIDE |
12516 LED_CTRL_TRAFFIC_BLINK |
12517 LED_CTRL_TRAFFIC_LED);
12518 break;
6aa20a22 12519
81b8709c 12520 case ETHTOOL_ID_OFF:
12521 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12522 LED_CTRL_TRAFFIC_OVERRIDE);
12523 break;
4009a93d 12524
81b8709c 12525 case ETHTOOL_ID_INACTIVE:
12526 tw32(MAC_LED_CTRL, tp->led_ctrl);
12527 break;
4009a93d 12528 }
81b8709c 12529
4009a93d
MC		 12530 return 0;
12531}
12532
de6f31eb 12533static void tg3_get_ethtool_stats(struct net_device *dev,
1da177e4
LT		 12534 struct ethtool_stats *estats, u64 *tmp_stats)
12535{
12536 struct tg3 *tp = netdev_priv(dev);
0e6c9da3 12537
b546e46f
MC		 12538 if (tp->hw_stats)
12539 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12540 else
12541 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
1da177e4
LT		 12542}
12543
535a490e 12544static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
c3e94500
MC		 12545{
12546 int i;
12547 __be32 *buf;
12548 u32 offset = 0, len = 0;
12549 u32 magic, val;
12550
63c3a66f 12551 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
c3e94500
MC		 12552 return NULL;
12553
12554 if (magic == TG3_EEPROM_MAGIC) {
12555 for (offset = TG3_NVM_DIR_START;
12556 offset < TG3_NVM_DIR_END;
12557 offset += TG3_NVM_DIRENT_SIZE) {
12558 if (tg3_nvram_read(tp, offset, &val))
12559 return NULL;
12560
12561 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12562 TG3_NVM_DIRTYPE_EXTVPD)
12563 break;
12564 }
12565
12566 if (offset != TG3_NVM_DIR_END) {
12567 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12568 if (tg3_nvram_read(tp, offset + 4, &offset))
12569 return NULL;
12570
12571 offset = tg3_nvram_logical_addr(tp, offset);
12572 }
12573 }
12574
12575 if (!offset || !len) {
12576 offset = TG3_NVM_VPD_OFF;
12577 len = TG3_NVM_VPD_LEN;
12578 }
12579
12580 buf = kmalloc(len, GFP_KERNEL);
12581 if (buf == NULL)
12582 return NULL;
12583
12584 if (magic == TG3_EEPROM_MAGIC) {
12585 for (i = 0; i < len; i += 4) {
12586 /* The data is in little-endian format in NVRAM.
12587 * Use the big-endian read routines to preserve
12588 * the byte order as it exists in NVRAM.
12589 */
12590 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12591 goto error;
12592 }
12593 } else {
12594 u8 *ptr;
12595 ssize_t cnt;
12596 unsigned int pos = 0;
12597
12598 ptr = (u8 *)&buf[0];
12599 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12600 cnt = pci_read_vpd(tp->pdev, pos,
12601 len - pos, ptr);
12602 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12603 cnt = 0;
12604 else if (cnt < 0)
12605 goto error;
12606 }
12607 if (pos != len)
12608 goto error;
12609 }
12610
535a490e
MC		 12611 *vpdlen = len;
12612
c3e94500
MC		 12613 return buf;
12614
12615error:
12616 kfree(buf);
12617 return NULL;
12618}
12619
566f86ad 12620#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 12621#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12622#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12623#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
727a6d9f
MC		 12624#define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12625#define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
bda18faf 12626#define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
b16250e3
MC		 12627#define NVRAM_SELFBOOT_HW_SIZE 0x20
12628#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 12629
12630static int tg3_test_nvram(struct tg3 *tp)
12631{
535a490e 12632 u32 csum, magic, len;
a9dc529d 12633 __be32 *buf;
ab0049b4 12634 int i, j, k, err = 0, size;
566f86ad 12635
63c3a66f 12636 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 12637 return 0;
12638
e4f34110 12639 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 12640 return -EIO;
12641
1b27777a
MC		 12642 if (magic == TG3_EEPROM_MAGIC)
12643 size = NVRAM_TEST_SIZE;
b16250e3 12644 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 12645 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12646 TG3_EEPROM_SB_FORMAT_1) {
12647 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12648 case TG3_EEPROM_SB_REVISION_0:
12649 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12650 break;
12651 case TG3_EEPROM_SB_REVISION_2:
12652 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12653 break;
12654 case TG3_EEPROM_SB_REVISION_3:
12655 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12656 break;
727a6d9f
MC		 12657 case TG3_EEPROM_SB_REVISION_4:
12658 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12659 break;
12660 case TG3_EEPROM_SB_REVISION_5:
12661 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12662 break;
12663 case TG3_EEPROM_SB_REVISION_6:
12664 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12665 break;
a5767dec 12666 default:
727a6d9f 12667 return -EIO;
a5767dec
MC		 12668 }
12669 } else
1b27777a 12670 return 0;
b16250e3
MC		 12671 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12672 size = NVRAM_SELFBOOT_HW_SIZE;
12673 else
1b27777a
MC		 12674 return -EIO;
12675
12676 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 12677 if (buf == NULL)
12678 return -ENOMEM;
12679
1b27777a
MC		 12680 err = -EIO;
12681 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 12682 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12683 if (err)
566f86ad 12684 break;
566f86ad 12685 }
1b27777a 12686 if (i < size)
566f86ad
MC		 12687 goto out;
12688
1b27777a 12689 /* Selfboot format */
a9dc529d 12690 magic = be32_to_cpu(buf[0]);
b9fc7dc5 12691 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 12692 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 12693 u8 *buf8 = (u8 *) buf, csum8 = 0;
12694
b9fc7dc5 12695 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 12696 TG3_EEPROM_SB_REVISION_2) {
12697 /* For rev 2, the csum doesn't include the MBA. */
12698 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12699 csum8 += buf8[i];
12700 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12701 csum8 += buf8[i];
12702 } else {
12703 for (i = 0; i < size; i++)
12704 csum8 += buf8[i];
12705 }
1b27777a 12706
ad96b485
AB		 12707 if (csum8 == 0) {
12708 err = 0;
12709 goto out;
12710 }
12711
12712 err = -EIO;
12713 goto out;
1b27777a 12714 }
566f86ad 12715
b9fc7dc5 12716 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 12717 TG3_EEPROM_MAGIC_HW) {
12718 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 12719 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 12720 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 12721
12722 /* Separate the parity bits and the data bytes. */
12723 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12724 if ((i == 0) || (i == 8)) {
12725 int l;
12726 u8 msk;
12727
12728 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12729 parity[k++] = buf8[i] & msk;
12730 i++;
859a5887 12731 } else if (i == 16) {
b16250e3
MC		 12732 int l;
12733 u8 msk;
12734
12735 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12736 parity[k++] = buf8[i] & msk;
12737 i++;
12738
12739 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12740 parity[k++] = buf8[i] & msk;
12741 i++;
12742 }
12743 data[j++] = buf8[i];
12744 }
12745
12746 err = -EIO;
12747 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12748 u8 hw8 = hweight8(data[i]);
12749
12750 if ((hw8 & 0x1) && parity[i])
12751 goto out;
12752 else if (!(hw8 & 0x1) && !parity[i])
12753 goto out;
12754 }
12755 err = 0;
12756 goto out;
12757 }
12758
01c3a392
MC		 12759 err = -EIO;
12760
566f86ad
MC		 12761 /* Bootstrap checksum at offset 0x10 */
12762 csum = calc_crc((unsigned char *) buf, 0x10);
01c3a392 12763 if (csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 12764 goto out;
12765
12766 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12767 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
01c3a392 12768 if (csum != le32_to_cpu(buf[0xfc/4]))
a9dc529d 12769 goto out;
566f86ad 12770
c3e94500
MC		 12771 kfree(buf);
12772
535a490e 12773 buf = tg3_vpd_readblock(tp, &len);
c3e94500
MC		 12774 if (!buf)
12775 return -ENOMEM;
d4894f3e 12776
535a490e 12777 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
d4894f3e
MC		 12778 if (i > 0) {
12779 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12780 if (j < 0)
12781 goto out;
12782
535a490e 12783 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
d4894f3e
MC		 12784 goto out;
12785
12786 i += PCI_VPD_LRDT_TAG_SIZE;
12787 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12788 PCI_VPD_RO_KEYWORD_CHKSUM);
12789 if (j > 0) {
12790 u8 csum8 = 0;
12791
12792 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12793
12794 for (i = 0; i <= j; i++)
12795 csum8 += ((u8 *)buf)[i];
12796
12797 if (csum8)
12798 goto out;
12799 }
12800 }
12801
566f86ad
MC		 12802 err = 0;
12803
12804out:
12805 kfree(buf);
12806 return err;
12807}
12808
ca43007a
MC		 12809#define TG3_SERDES_TIMEOUT_SEC 2
12810#define TG3_COPPER_TIMEOUT_SEC 6
12811
12812static int tg3_test_link(struct tg3 *tp)
12813{
12814 int i, max;
12815
12816 if (!netif_running(tp->dev))
12817 return -ENODEV;
12818
f07e9af3 12819 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
ca43007a
MC		 12820 max = TG3_SERDES_TIMEOUT_SEC;
12821 else
12822 max = TG3_COPPER_TIMEOUT_SEC;
12823
12824 for (i = 0; i < max; i++) {
f4a46d1f 12825 if (tp->link_up)
ca43007a
MC		 12826 return 0;
12827
12828 if (msleep_interruptible(1000))
12829 break;
12830 }
12831
12832 return -EIO;
12833}
12834
a71116d1 12835/* Only test the commonly used registers */
30ca3e37 12836static int tg3_test_registers(struct tg3 *tp)
a71116d1 12837{
b16250e3 12838 int i, is_5705, is_5750;
a71116d1
MC		 12839 u32 offset, read_mask, write_mask, val, save_val, read_val;
12840 static struct {
12841 u16 offset;
12842 u16 flags;
12843#define TG3_FL_5705 0x1
12844#define TG3_FL_NOT_5705 0x2
12845#define TG3_FL_NOT_5788 0x4
b16250e3 12846#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 12847 u32 read_mask;
12848 u32 write_mask;
12849 } reg_tbl[] = {
12850 /* MAC Control Registers */
12851 { MAC_MODE, TG3_FL_NOT_5705,
12852 0x00000000, 0x00ef6f8c },
12853 { MAC_MODE, TG3_FL_5705,
12854 0x00000000, 0x01ef6b8c },
12855 { MAC_STATUS, TG3_FL_NOT_5705,
12856 0x03800107, 0x00000000 },
12857 { MAC_STATUS, TG3_FL_5705,
12858 0x03800100, 0x00000000 },
12859 { MAC_ADDR_0_HIGH, 0x0000,
12860 0x00000000, 0x0000ffff },
12861 { MAC_ADDR_0_LOW, 0x0000,
c6cdf436 12862 0x00000000, 0xffffffff },
a71116d1
MC		 12863 { MAC_RX_MTU_SIZE, 0x0000,
12864 0x00000000, 0x0000ffff },
12865 { MAC_TX_MODE, 0x0000,
12866 0x00000000, 0x00000070 },
12867 { MAC_TX_LENGTHS, 0x0000,
12868 0x00000000, 0x00003fff },
12869 { MAC_RX_MODE, TG3_FL_NOT_5705,
12870 0x00000000, 0x000007fc },
12871 { MAC_RX_MODE, TG3_FL_5705,
12872 0x00000000, 0x000007dc },
12873 { MAC_HASH_REG_0, 0x0000,
12874 0x00000000, 0xffffffff },
12875 { MAC_HASH_REG_1, 0x0000,
12876 0x00000000, 0xffffffff },
12877 { MAC_HASH_REG_2, 0x0000,
12878 0x00000000, 0xffffffff },
12879 { MAC_HASH_REG_3, 0x0000,
12880 0x00000000, 0xffffffff },
12881
12882 /* Receive Data and Receive BD Initiator Control Registers. */
12883 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
12884 0x00000000, 0xffffffff },
12885 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
12886 0x00000000, 0xffffffff },
12887 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
12888 0x00000000, 0x00000003 },
12889 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
12890 0x00000000, 0xffffffff },
12891 { RCVDBDI_STD_BD+0, 0x0000,
12892 0x00000000, 0xffffffff },
12893 { RCVDBDI_STD_BD+4, 0x0000,
12894 0x00000000, 0xffffffff },
12895 { RCVDBDI_STD_BD+8, 0x0000,
12896 0x00000000, 0xffff0002 },
12897 { RCVDBDI_STD_BD+0xc, 0x0000,
12898 0x00000000, 0xffffffff },
6aa20a22 12899
a71116d1
MC		 12900 /* Receive BD Initiator Control Registers. */
12901 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
12902 0x00000000, 0xffffffff },
12903 { RCVBDI_STD_THRESH, TG3_FL_5705,
12904 0x00000000, 0x000003ff },
12905 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
12906 0x00000000, 0xffffffff },
6aa20a22 12907
a71116d1
MC		 12908 /* Host Coalescing Control Registers. */
12909 { HOSTCC_MODE, TG3_FL_NOT_5705,
12910 0x00000000, 0x00000004 },
12911 { HOSTCC_MODE, TG3_FL_5705,
12912 0x00000000, 0x000000f6 },
12913 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
12914 0x00000000, 0xffffffff },
12915 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
12916 0x00000000, 0x000003ff },
12917 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
12918 0x00000000, 0xffffffff },
12919 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
12920 0x00000000, 0x000003ff },
12921 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
12922 0x00000000, 0xffffffff },
12923 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12924 0x00000000, 0x000000ff },
12925 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
12926 0x00000000, 0xffffffff },
12927 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12928 0x00000000, 0x000000ff },
12929 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
12930 0x00000000, 0xffffffff },
12931 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
12932 0x00000000, 0xffffffff },
12933 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12934 0x00000000, 0xffffffff },
12935 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12936 0x00000000, 0x000000ff },
12937 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12938 0x00000000, 0xffffffff },
12939 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12940 0x00000000, 0x000000ff },
12941 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
12942 0x00000000, 0xffffffff },
12943 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
12944 0x00000000, 0xffffffff },
12945 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
12946 0x00000000, 0xffffffff },
12947 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
12948 0x00000000, 0xffffffff },
12949 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
12950 0x00000000, 0xffffffff },
12951 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
12952 0xffffffff, 0x00000000 },
12953 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
12954 0xffffffff, 0x00000000 },
12955
12956 /* Buffer Manager Control Registers. */
b16250e3 12957 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 12958 0x00000000, 0x007fff80 },
b16250e3 12959 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 12960 0x00000000, 0x007fffff },
12961 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
12962 0x00000000, 0x0000003f },
12963 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
12964 0x00000000, 0x000001ff },
12965 { BUFMGR_MB_HIGH_WATER, 0x0000,
12966 0x00000000, 0x000001ff },
12967 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
12968 0xffffffff, 0x00000000 },
12969 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
12970 0xffffffff, 0x00000000 },
6aa20a22 12971
a71116d1
MC		 12972 /* Mailbox Registers */
12973 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
12974 0x00000000, 0x000001ff },
12975 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
12976 0x00000000, 0x000001ff },
12977 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
12978 0x00000000, 0x000007ff },
12979 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
12980 0x00000000, 0x000001ff },
12981
12982 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
12983 };
12984
b16250e3 12985 is_5705 = is_5750 = 0;
63c3a66f 12986 if (tg3_flag(tp, 5705_PLUS)) {
a71116d1 12987 is_5705 = 1;
63c3a66f 12988 if (tg3_flag(tp, 5750_PLUS))
b16250e3
MC		 12989 is_5750 = 1;
12990 }
a71116d1
MC		 12991
12992 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
12993 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
12994 continue;
12995
12996 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
12997 continue;
12998
63c3a66f 12999 if (tg3_flag(tp, IS_5788) &&
a71116d1
MC		 13000 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13001 continue;
13002
b16250e3
MC		 13003 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13004 continue;
13005
a71116d1
MC		 13006 offset = (u32) reg_tbl[i].offset;
13007 read_mask = reg_tbl[i].read_mask;
13008 write_mask = reg_tbl[i].write_mask;
13009
13010 /* Save the original register content */
13011 save_val = tr32(offset);
13012
13013 /* Determine the read-only value. */
13014 read_val = save_val & read_mask;
13015
13016 /* Write zero to the register, then make sure the read-only bits
13017 * are not changed and the read/write bits are all zeros.
13018 */
13019 tw32(offset, 0);
13020
13021 val = tr32(offset);
13022
13023 /* Test the read-only and read/write bits. */
13024 if (((val & read_mask) != read_val) || (val & write_mask))
13025 goto out;
13026
13027 /* Write ones to all the bits defined by RdMask and WrMask, then
13028 * make sure the read-only bits are not changed and the
13029 * read/write bits are all ones.
13030 */
13031 tw32(offset, read_mask | write_mask);
13032
13033 val = tr32(offset);
13034
13035 /* Test the read-only bits. */
13036 if ((val & read_mask) != read_val)
13037 goto out;
13038
13039 /* Test the read/write bits. */
13040 if ((val & write_mask) != write_mask)
13041 goto out;
13042
13043 tw32(offset, save_val);
13044 }
13045
13046 return 0;
13047
13048out:
9f88f29f 13049 if (netif_msg_hw(tp))
2445e461
MC		 13050 netdev_err(tp->dev,
13051 "Register test failed at offset %x\n", offset);
a71116d1
MC		 13052 tw32(offset, save_val);
13053 return -EIO;
13054}
13055
7942e1db
MC		 13056static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13057{
f71e1309 13058 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 13059 int i;
13060 u32 j;
13061
e9edda69 13062 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 13063 for (j = 0; j < len; j += 4) {
13064 u32 val;
13065
13066 tg3_write_mem(tp, offset + j, test_pattern[i]);
13067 tg3_read_mem(tp, offset + j, &val);
13068 if (val != test_pattern[i])
13069 return -EIO;
13070 }
13071 }
13072 return 0;
13073}
13074
13075static int tg3_test_memory(struct tg3 *tp)
13076{
13077 static struct mem_entry {
13078 u32 offset;
13079 u32 len;
13080 } mem_tbl_570x[] = {
38690194 13081 { 0x00000000, 0x00b50},
7942e1db
MC		 13082 { 0x00002000, 0x1c000},
13083 { 0xffffffff, 0x00000}
13084 }, mem_tbl_5705[] = {
13085 { 0x00000100, 0x0000c},
13086 { 0x00000200, 0x00008},
7942e1db
MC		 13087 { 0x00004000, 0x00800},
13088 { 0x00006000, 0x01000},
13089 { 0x00008000, 0x02000},
13090 { 0x00010000, 0x0e000},
13091 { 0xffffffff, 0x00000}
79f4d13a
MC		 13092 }, mem_tbl_5755[] = {
13093 { 0x00000200, 0x00008},
13094 { 0x00004000, 0x00800},
13095 { 0x00006000, 0x00800},
13096 { 0x00008000, 0x02000},
13097 { 0x00010000, 0x0c000},
13098 { 0xffffffff, 0x00000}
b16250e3
MC		 13099 }, mem_tbl_5906[] = {
13100 { 0x00000200, 0x00008},
13101 { 0x00004000, 0x00400},
13102 { 0x00006000, 0x00400},
13103 { 0x00008000, 0x01000},
13104 { 0x00010000, 0x01000},
13105 { 0xffffffff, 0x00000}
8b5a6c42
MC		 13106 }, mem_tbl_5717[] = {
13107 { 0x00000200, 0x00008},
13108 { 0x00010000, 0x0a000},
13109 { 0x00020000, 0x13c00},
13110 { 0xffffffff, 0x00000}
13111 }, mem_tbl_57765[] = {
13112 { 0x00000200, 0x00008},
13113 { 0x00004000, 0x00800},
13114 { 0x00006000, 0x09800},
13115 { 0x00010000, 0x0a000},
13116 { 0xffffffff, 0x00000}
7942e1db
MC		 13117 };
13118 struct mem_entry *mem_tbl;
13119 int err = 0;
13120 int i;
13121
63c3a66f 13122 if (tg3_flag(tp, 5717_PLUS))
8b5a6c42 13123 mem_tbl = mem_tbl_5717;
c65a17f4 13124 else if (tg3_flag(tp, 57765_CLASS) ||
4153577a 13125 tg3_asic_rev(tp) == ASIC_REV_5762)
8b5a6c42 13126 mem_tbl = mem_tbl_57765;
63c3a66f 13127 else if (tg3_flag(tp, 5755_PLUS))
321d32a0 13128 mem_tbl = mem_tbl_5755;
4153577a 13129 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
321d32a0 13130 mem_tbl = mem_tbl_5906;
63c3a66f 13131 else if (tg3_flag(tp, 5705_PLUS))
321d32a0
MC		 13132 mem_tbl = mem_tbl_5705;
13133 else
7942e1db
MC		 13134 mem_tbl = mem_tbl_570x;
13135
13136 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
be98da6a
MC		 13137 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13138 if (err)
7942e1db
MC		 13139 break;
13140 }
6aa20a22 13141
7942e1db
MC		 13142 return err;
13143}
13144
bb158d69
MC		 13145#define TG3_TSO_MSS 500
13146
13147#define TG3_TSO_IP_HDR_LEN 20
13148#define TG3_TSO_TCP_HDR_LEN 20
13149#define TG3_TSO_TCP_OPT_LEN 12
13150
13151static const u8 tg3_tso_header[] = {
131520x08, 0x00,
131530x45, 0x00, 0x00, 0x00,
131540x00, 0x00, 0x40, 0x00,
131550x40, 0x06, 0x00, 0x00,
131560x0a, 0x00, 0x00, 0x01,
131570x0a, 0x00, 0x00, 0x02,
131580x0d, 0x00, 0xe0, 0x00,
131590x00, 0x00, 0x01, 0x00,
131600x00, 0x00, 0x02, 0x00,
131610x80, 0x10, 0x10, 0x00,
131620x14, 0x09, 0x00, 0x00,
131630x01, 0x01, 0x08, 0x0a,
131640x11, 0x11, 0x11, 0x11,
131650x11, 0x11, 0x11, 0x11,
13166};
9f40dead 13167
28a45957 13168static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
c76949a6 13169{
5e5a7f37 13170 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
bb158d69 13171 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
84b67b27 13172 u32 budget;
9205fd9c
ED		 13173 struct sk_buff *skb;
13174 u8 *tx_data, *rx_data;
c76949a6
MC		 13175 dma_addr_t map;
13176 int num_pkts, tx_len, rx_len, i, err;
13177 struct tg3_rx_buffer_desc *desc;
898a56f8 13178 struct tg3_napi *tnapi, *rnapi;
8fea32b9 13179 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
c76949a6 13180
c8873405
MC		 13181 tnapi = &tp->napi[0];
13182 rnapi = &tp->napi[0];
0c1d0e2b 13183 if (tp->irq_cnt > 1) {
63c3a66f 13184 if (tg3_flag(tp, ENABLE_RSS))
1da85aa3 13185 rnapi = &tp->napi[1];
63c3a66f 13186 if (tg3_flag(tp, ENABLE_TSS))
c8873405 13187 tnapi = &tp->napi[1];
0c1d0e2b 13188 }
fd2ce37f 13189 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 13190
c76949a6
MC		 13191 err = -EIO;
13192
4852a861 13193 tx_len = pktsz;
a20e9c62 13194 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 13195 if (!skb)
13196 return -ENOMEM;
13197
c76949a6
MC		 13198 tx_data = skb_put(skb, tx_len);
13199 memcpy(tx_data, tp->dev->dev_addr, 6);
13200 memset(tx_data + 6, 0x0, 8);
13201
4852a861 13202 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
c76949a6 13203
28a45957 13204 if (tso_loopback) {
bb158d69
MC		 13205 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13206
13207 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13208 TG3_TSO_TCP_OPT_LEN;
13209
13210 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13211 sizeof(tg3_tso_header));
13212 mss = TG3_TSO_MSS;
13213
13214 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13215 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13216
13217 /* Set the total length field in the IP header */
13218 iph->tot_len = htons((u16)(mss + hdr_len));
13219
13220 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13221 TXD_FLAG_CPU_POST_DMA);
13222
63c3a66f
JP		 13223 if (tg3_flag(tp, HW_TSO_1) ||
13224 tg3_flag(tp, HW_TSO_2) ||
13225 tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13226 struct tcphdr *th;
13227 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13228 th = (struct tcphdr *)&tx_data[val];
13229 th->check = 0;
13230 } else
13231 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13232
63c3a66f 13233 if (tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13234 mss |= (hdr_len & 0xc) << 12;
13235 if (hdr_len & 0x10)
13236 base_flags |= 0x00000010;
13237 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 13238 } else if (tg3_flag(tp, HW_TSO_2))
bb158d69 13239 mss |= hdr_len << 9;
63c3a66f 13240 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 13241 tg3_asic_rev(tp) == ASIC_REV_5705) {
bb158d69
MC		 13242 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13243 } else {
13244 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13245 }
13246
13247 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13248 } else {
13249 num_pkts = 1;
13250 data_off = ETH_HLEN;
c441b456
MC		 13251
13252 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13253 tx_len > VLAN_ETH_FRAME_LEN)
13254 base_flags |= TXD_FLAG_JMB_PKT;
bb158d69
MC		 13255 }
13256
13257 for (i = data_off; i < tx_len; i++)
c76949a6
MC		 13258 tx_data[i] = (u8) (i & 0xff);
13259
f4188d8a
AD		 13260 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13261 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 13262 dev_kfree_skb(skb);
13263 return -EIO;
13264 }
c76949a6 13265
0d681b27
MC		 13266 val = tnapi->tx_prod;
13267 tnapi->tx_buffers[val].skb = skb;
13268 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13269
c76949a6 13270 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13271 rnapi->coal_now);
c76949a6
MC		 13272
13273 udelay(10);
13274
898a56f8 13275 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 13276
84b67b27
MC		 13277 budget = tg3_tx_avail(tnapi);
13278 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
d1a3b737
MC		 13279 base_flags | TXD_FLAG_END, mss, 0)) {
13280 tnapi->tx_buffers[val].skb = NULL;
13281 dev_kfree_skb(skb);
13282 return -EIO;
13283 }
c76949a6 13284
f3f3f27e 13285 tnapi->tx_prod++;
c76949a6 13286
6541b806
MC		 13287 /* Sync BD data before updating mailbox */
13288 wmb();
13289
f3f3f27e
MC		 13290 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13291 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 13292
13293 udelay(10);
13294
303fc921
MC		 13295 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13296 for (i = 0; i < 35; i++) {
c76949a6 13297 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13298 coal_now);
c76949a6
MC		 13299
13300 udelay(10);
13301
898a56f8
MC		 13302 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13303 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 13304 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 13305 (rx_idx == (rx_start_idx + num_pkts)))
13306 break;
13307 }
13308
ba1142e4 13309 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
c76949a6
MC		 13310 dev_kfree_skb(skb);
13311
f3f3f27e 13312 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 13313 goto out;
13314
13315 if (rx_idx != rx_start_idx + num_pkts)
13316 goto out;
13317
bb158d69
MC		 13318 val = data_off;
13319 while (rx_idx != rx_start_idx) {
13320 desc = &rnapi->rx_rcb[rx_start_idx++];
13321 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13322 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
c76949a6 13323
bb158d69
MC		 13324 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13325 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13326 goto out;
c76949a6 13327
bb158d69
MC		 13328 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13329 - ETH_FCS_LEN;
c76949a6 13330
28a45957 13331 if (!tso_loopback) {
bb158d69
MC		 13332 if (rx_len != tx_len)
13333 goto out;
4852a861 13334
bb158d69
MC		 13335 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13336 if (opaque_key != RXD_OPAQUE_RING_STD)
13337 goto out;
13338 } else {
13339 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13340 goto out;
13341 }
13342 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13343 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
54e0a67f 13344 >> RXD_TCPCSUM_SHIFT != 0xffff) {
4852a861 13345 goto out;
bb158d69 13346 }
4852a861 13347
bb158d69 13348 if (opaque_key == RXD_OPAQUE_RING_STD) {
9205fd9c 13349 rx_data = tpr->rx_std_buffers[desc_idx].data;
bb158d69
MC		 13350 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13351 mapping);
13352 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
9205fd9c 13353 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
bb158d69
MC		 13354 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13355 mapping);
13356 } else
13357 goto out;
c76949a6 13358
bb158d69
MC		 13359 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13360 PCI_DMA_FROMDEVICE);
c76949a6 13361
9205fd9c 13362 rx_data += TG3_RX_OFFSET(tp);
bb158d69 13363 for (i = data_off; i < rx_len; i++, val++) {
9205fd9c 13364 if (*(rx_data + i) != (u8) (val & 0xff))
bb158d69
MC		 13365 goto out;
13366 }
c76949a6 13367 }
bb158d69 13368
c76949a6 13369 err = 0;
6aa20a22 13370
9205fd9c 13371 /* tg3_free_rings will unmap and free the rx_data */
c76949a6
MC		 13372out:
13373 return err;
13374}
13375
00c266b7
MC		 13376#define TG3_STD_LOOPBACK_FAILED 1
13377#define TG3_JMB_LOOPBACK_FAILED 2
bb158d69 13378#define TG3_TSO_LOOPBACK_FAILED 4
28a45957
MC		 13379#define TG3_LOOPBACK_FAILED \
13380 (TG3_STD_LOOPBACK_FAILED | \
13381 TG3_JMB_LOOPBACK_FAILED | \
13382 TG3_TSO_LOOPBACK_FAILED)
00c266b7 13383
941ec90f 13384static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
9f40dead 13385{
28a45957 13386 int err = -EIO;
2215e24c 13387 u32 eee_cap;
c441b456
MC		 13388 u32 jmb_pkt_sz = 9000;
13389
13390 if (tp->dma_limit)
13391 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
9f40dead 13392
ab789046
MC		 13393 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13394 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13395
28a45957 13396 if (!netif_running(tp->dev)) {
93df8b8f
NNS		 13397 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13398 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13399 if (do_extlpbk)
93df8b8f 13400 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
28a45957
MC		 13401 goto done;
13402 }
13403
953c96e0 13404 err = tg3_reset_hw(tp, true);
ab789046 13405 if (err) {
93df8b8f
NNS		 13406 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13407 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13408 if (do_extlpbk)
93df8b8f 13409 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
ab789046
MC		 13410 goto done;
13411 }
9f40dead 13412
63c3a66f 13413 if (tg3_flag(tp, ENABLE_RSS)) {
4a85f098
MC		 13414 int i;
13415
13416 /* Reroute all rx packets to the 1st queue */
13417 for (i = MAC_RSS_INDIR_TBL_0;
13418 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13419 tw32(i, 0x0);
13420 }
13421
6e01b20b
MC		 13422 /* HW errata - mac loopback fails in some cases on 5780.
13423 * Normal traffic and PHY loopback are not affected by
13424 * errata. Also, the MAC loopback test is deprecated for
13425 * all newer ASIC revisions.
13426 */
4153577a 13427 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
6e01b20b
MC		 13428 !tg3_flag(tp, CPMU_PRESENT)) {
13429 tg3_mac_loopback(tp, true);
9936bcf6 13430
28a45957 13431 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13432 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
6e01b20b
MC		 13433
13434 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13435 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13436 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
6e01b20b
MC		 13437
13438 tg3_mac_loopback(tp, false);
13439 }
4852a861 13440
f07e9af3 13441 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
63c3a66f 13442 !tg3_flag(tp, USE_PHYLIB)) {
5e5a7f37
MC		 13443 int i;
13444
941ec90f 13445 tg3_phy_lpbk_set(tp, 0, false);
5e5a7f37
MC		 13446
13447 /* Wait for link */
13448 for (i = 0; i < 100; i++) {
13449 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13450 break;
13451 mdelay(1);
13452 }
13453
28a45957 13454 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13455 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
63c3a66f 13456 if (tg3_flag(tp, TSO_CAPABLE) &&
28a45957 13457 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f 13458 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
63c3a66f 13459 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13460 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13461 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
9f40dead 13462
941ec90f
MC		 13463 if (do_extlpbk) {
13464 tg3_phy_lpbk_set(tp, 0, true);
13465
13466 /* All link indications report up, but the hardware
13467 * isn't really ready for about 20 msec. Double it
13468 * to be sure.
13469 */
13470 mdelay(40);
13471
13472 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f
NNS		 13473 data[TG3_EXT_LOOPB_TEST] |=
13474 TG3_STD_LOOPBACK_FAILED;
941ec90f
MC		 13475 if (tg3_flag(tp, TSO_CAPABLE) &&
13476 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f
NNS		 13477 data[TG3_EXT_LOOPB_TEST] |=
13478 TG3_TSO_LOOPBACK_FAILED;
941ec90f 13479 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13480 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f
NNS		 13481 data[TG3_EXT_LOOPB_TEST] |=
13482 TG3_JMB_LOOPBACK_FAILED;
941ec90f
MC		 13483 }
13484
5e5a7f37
MC		 13485 /* Re-enable gphy autopowerdown. */
13486 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13487 tg3_phy_toggle_apd(tp, true);
13488 }
6833c043 13489
93df8b8f
NNS		 13490 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13491 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
28a45957 13492
ab789046
MC		 13493done:
13494 tp->phy_flags |= eee_cap;
13495
9f40dead
MC		 13496 return err;
13497}
13498
4cafd3f5
MC		 13499static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13500 u64 *data)
13501{
566f86ad 13502 struct tg3 *tp = netdev_priv(dev);
941ec90f 13503 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
566f86ad 13504
2e460fc0
NS		 13505 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13506 if (tg3_power_up(tp)) {
13507 etest->flags |= ETH_TEST_FL_FAILED;
13508 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13509 return;
13510 }
13511 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
bed9829f 13512 }
bc1c7567 13513
566f86ad
MC		 13514 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13515
13516 if (tg3_test_nvram(tp) != 0) {
13517 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13518 data[TG3_NVRAM_TEST] = 1;
566f86ad 13519 }
941ec90f 13520 if (!doextlpbk && tg3_test_link(tp)) {
ca43007a 13521 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13522 data[TG3_LINK_TEST] = 1;
ca43007a 13523 }
a71116d1 13524 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 13525 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 13526
13527 if (netif_running(dev)) {
b02fd9e3 13528 tg3_phy_stop(tp);
a71116d1 13529 tg3_netif_stop(tp);
bbe832c0
MC		 13530 irq_sync = 1;
13531 }
a71116d1 13532
bbe832c0 13533 tg3_full_lock(tp, irq_sync);
a71116d1 13534 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 13535 err = tg3_nvram_lock(tp);
a71116d1 13536 tg3_halt_cpu(tp, RX_CPU_BASE);
63c3a66f 13537 if (!tg3_flag(tp, 5705_PLUS))
a71116d1 13538 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 13539 if (!err)
13540 tg3_nvram_unlock(tp);
a71116d1 13541
f07e9af3 13542 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
d9ab5ad1
MC		 13543 tg3_phy_reset(tp);
13544
a71116d1
MC		 13545 if (tg3_test_registers(tp) != 0) {
13546 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13547 data[TG3_REGISTER_TEST] = 1;
a71116d1 13548 }
28a45957 13549
7942e1db
MC		 13550 if (tg3_test_memory(tp) != 0) {
13551 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13552 data[TG3_MEMORY_TEST] = 1;
7942e1db 13553 }
28a45957 13554
941ec90f
MC		 13555 if (doextlpbk)
13556 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13557
93df8b8f 13558 if (tg3_test_loopback(tp, data, doextlpbk))
c76949a6 13559 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 13560
f47c11ee
DM		 13561 tg3_full_unlock(tp);
13562
d4bc3927
MC		 13563 if (tg3_test_interrupt(tp) != 0) {
13564 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13565 data[TG3_INTERRUPT_TEST] = 1;
d4bc3927 13566 }
f47c11ee
DM		 13567
13568 tg3_full_lock(tp, 0);
d4bc3927 13569
a71116d1
MC		 13570 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13571 if (netif_running(dev)) {
63c3a66f 13572 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 13573 err2 = tg3_restart_hw(tp, true);
b02fd9e3 13574 if (!err2)
b9ec6c1b 13575 tg3_netif_start(tp);
a71116d1 13576 }
f47c11ee
DM		 13577
13578 tg3_full_unlock(tp);
b02fd9e3
MC		 13579
13580 if (irq_sync && !err2)
13581 tg3_phy_start(tp);
a71116d1 13582 }
80096068 13583 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
5137a2ee 13584 tg3_power_down_prepare(tp);
bc1c7567 13585
4cafd3f5
MC		 13586}
13587
0a633ac2
MC		 13588static int tg3_hwtstamp_ioctl(struct net_device *dev,
13589 struct ifreq *ifr, int cmd)
13590{
13591 struct tg3 *tp = netdev_priv(dev);
13592 struct hwtstamp_config stmpconf;
13593
13594 if (!tg3_flag(tp, PTP_CAPABLE))
13595 return -EINVAL;
13596
13597 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13598 return -EFAULT;
13599
13600 if (stmpconf.flags)
13601 return -EINVAL;
13602
13603 switch (stmpconf.tx_type) {
13604 case HWTSTAMP_TX_ON:
13605 tg3_flag_set(tp, TX_TSTAMP_EN);
13606 break;
13607 case HWTSTAMP_TX_OFF:
13608 tg3_flag_clear(tp, TX_TSTAMP_EN);
13609 break;
13610 default:
13611 return -ERANGE;
13612 }
13613
13614 switch (stmpconf.rx_filter) {
13615 case HWTSTAMP_FILTER_NONE:
13616 tp->rxptpctl = 0;
13617 break;
13618 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13619 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13620 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13621 break;
13622 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13623 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13624 TG3_RX_PTP_CTL_SYNC_EVNT;
13625 break;
13626 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13627 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13628 TG3_RX_PTP_CTL_DELAY_REQ;
13629 break;
13630 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13631 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13632 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13633 break;
13634 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13635 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13636 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13637 break;
13638 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13639 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13640 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13641 break;
13642 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13643 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13644 TG3_RX_PTP_CTL_SYNC_EVNT;
13645 break;
13646 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13647 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13648 TG3_RX_PTP_CTL_SYNC_EVNT;
13649 break;
13650 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13651 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13652 TG3_RX_PTP_CTL_SYNC_EVNT;
13653 break;
13654 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13655 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13656 TG3_RX_PTP_CTL_DELAY_REQ;
13657 break;
13658 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13659 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13660 TG3_RX_PTP_CTL_DELAY_REQ;
13661 break;
13662 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13663 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13664 TG3_RX_PTP_CTL_DELAY_REQ;
13665 break;
13666 default:
13667 return -ERANGE;
13668 }
13669
13670 if (netif_running(dev) && tp->rxptpctl)
13671 tw32(TG3_RX_PTP_CTL,
13672 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13673
13674 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13675 -EFAULT : 0;
13676}
13677
1da177e4
LT		 13678static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13679{
13680 struct mii_ioctl_data *data = if_mii(ifr);
13681 struct tg3 *tp = netdev_priv(dev);
13682 int err;
13683
63c3a66f 13684 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 13685 struct phy_device *phydev;
f07e9af3 13686 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 13687 return -EAGAIN;
3f0e3ad7 13688 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
28b04113 13689 return phy_mii_ioctl(phydev, ifr, cmd);
b02fd9e3
MC		 13690 }
13691
33f401ae 13692 switch (cmd) {
1da177e4 13693 case SIOCGMIIPHY:
882e9793 13694 data->phy_id = tp->phy_addr;
1da177e4
LT		 13695
13696 /* fallthru */
13697 case SIOCGMIIREG: {
13698 u32 mii_regval;
13699
f07e9af3 13700 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13701 break; /* We have no PHY */
13702
34eea5ac 13703 if (!netif_running(dev))
bc1c7567
MC		 13704 return -EAGAIN;
13705
f47c11ee 13706 spin_lock_bh(&tp->lock);
5c358045
HM		 13707 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13708 data->reg_num & 0x1f, &mii_regval);
f47c11ee 13709 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13710
13711 data->val_out = mii_regval;
13712
13713 return err;
13714 }
13715
13716 case SIOCSMIIREG:
f07e9af3 13717 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13718 break; /* We have no PHY */
13719
34eea5ac 13720 if (!netif_running(dev))
bc1c7567
MC		 13721 return -EAGAIN;
13722
f47c11ee 13723 spin_lock_bh(&tp->lock);
5c358045
HM		 13724 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13725 data->reg_num & 0x1f, data->val_in);
f47c11ee 13726 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13727
13728 return err;
13729
0a633ac2
MC		 13730 case SIOCSHWTSTAMP:
13731 return tg3_hwtstamp_ioctl(dev, ifr, cmd);
13732
1da177e4
LT		 13733 default:
13734 /* do nothing */
13735 break;
13736 }
13737 return -EOPNOTSUPP;
13738}
13739
15f9850d
DM		 13740static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13741{
13742 struct tg3 *tp = netdev_priv(dev);
13743
13744 memcpy(ec, &tp->coal, sizeof(*ec));
13745 return 0;
13746}
13747
d244c892
MC		 13748static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13749{
13750 struct tg3 *tp = netdev_priv(dev);
13751 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13752 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13753
63c3a66f 13754 if (!tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 13755 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13756 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13757 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13758 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13759 }
13760
13761 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13762 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13763 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13764 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13765 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13766 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13767 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13768 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13769 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13770 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13771 return -EINVAL;
13772
13773 /* No rx interrupts will be generated if both are zero */
13774 if ((ec->rx_coalesce_usecs == 0) &&
13775 (ec->rx_max_coalesced_frames == 0))
13776 return -EINVAL;
13777
13778 /* No tx interrupts will be generated if both are zero */
13779 if ((ec->tx_coalesce_usecs == 0) &&
13780 (ec->tx_max_coalesced_frames == 0))
13781 return -EINVAL;
13782
13783 /* Only copy relevant parameters, ignore all others. */
13784 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
13785 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
13786 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
13787 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
13788 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
13789 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
13790 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
13791 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
13792 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
13793
13794 if (netif_running(dev)) {
13795 tg3_full_lock(tp, 0);
13796 __tg3_set_coalesce(tp, &tp->coal);
13797 tg3_full_unlock(tp);
13798 }
13799 return 0;
13800}
13801
1cbf9eb8
NS		 13802static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
13803{
13804 struct tg3 *tp = netdev_priv(dev);
13805
13806 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13807 netdev_warn(tp->dev, "Board does not support EEE!\n");
13808 return -EOPNOTSUPP;
13809 }
13810
13811 if (edata->advertised != tp->eee.advertised) {
13812 netdev_warn(tp->dev,
13813 "Direct manipulation of EEE advertisement is not supported\n");
13814 return -EINVAL;
13815 }
13816
13817 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
13818 netdev_warn(tp->dev,
13819 "Maximal Tx Lpi timer supported is %#x(u)\n",
13820 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
13821 return -EINVAL;
13822 }
13823
13824 tp->eee = *edata;
13825
13826 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
13827 tg3_warn_mgmt_link_flap(tp);
13828
13829 if (netif_running(tp->dev)) {
13830 tg3_full_lock(tp, 0);
13831 tg3_setup_eee(tp);
13832 tg3_phy_reset(tp);
13833 tg3_full_unlock(tp);
13834 }
13835
13836 return 0;
13837}
13838
13839static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
13840{
13841 struct tg3 *tp = netdev_priv(dev);
13842
13843 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13844 netdev_warn(tp->dev,
13845 "Board does not support EEE!\n");
13846 return -EOPNOTSUPP;
13847 }
13848
13849 *edata = tp->eee;
13850 return 0;
13851}
13852
7282d491 13853static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 13854 .get_settings = tg3_get_settings,
13855 .set_settings = tg3_set_settings,
13856 .get_drvinfo = tg3_get_drvinfo,
13857 .get_regs_len = tg3_get_regs_len,
13858 .get_regs = tg3_get_regs,
13859 .get_wol = tg3_get_wol,
13860 .set_wol = tg3_set_wol,
13861 .get_msglevel = tg3_get_msglevel,
13862 .set_msglevel = tg3_set_msglevel,
13863 .nway_reset = tg3_nway_reset,
13864 .get_link = ethtool_op_get_link,
13865 .get_eeprom_len = tg3_get_eeprom_len,
13866 .get_eeprom = tg3_get_eeprom,
13867 .set_eeprom = tg3_set_eeprom,
13868 .get_ringparam = tg3_get_ringparam,
13869 .set_ringparam = tg3_set_ringparam,
13870 .get_pauseparam = tg3_get_pauseparam,
13871 .set_pauseparam = tg3_set_pauseparam,
4cafd3f5 13872 .self_test = tg3_self_test,
1da177e4 13873 .get_strings = tg3_get_strings,
81b8709c 13874 .set_phys_id = tg3_set_phys_id,
1da177e4 13875 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 13876 .get_coalesce = tg3_get_coalesce,
d244c892 13877 .set_coalesce = tg3_set_coalesce,
b9f2c044 13878 .get_sset_count = tg3_get_sset_count,
90415477
MC		 13879 .get_rxnfc = tg3_get_rxnfc,
13880 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
13881 .get_rxfh_indir = tg3_get_rxfh_indir,
13882 .set_rxfh_indir = tg3_set_rxfh_indir,
0968169c
MC		 13883 .get_channels = tg3_get_channels,
13884 .set_channels = tg3_set_channels,
7d41e49a 13885 .get_ts_info = tg3_get_ts_info,
1cbf9eb8
NS		 13886 .get_eee = tg3_get_eee,
13887 .set_eee = tg3_set_eee,
1da177e4
LT		 13888};
13889
b4017c53
DM		 13890static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
13891 struct rtnl_link_stats64 *stats)
13892{
13893 struct tg3 *tp = netdev_priv(dev);
13894
0f566b20
MC		 13895 spin_lock_bh(&tp->lock);
13896 if (!tp->hw_stats) {
13897 spin_unlock_bh(&tp->lock);
b4017c53 13898 return &tp->net_stats_prev;
0f566b20 13899 }
b4017c53 13900
b4017c53
DM		 13901 tg3_get_nstats(tp, stats);
13902 spin_unlock_bh(&tp->lock);
13903
13904 return stats;
13905}
13906
ccd5ba9d
MC		 13907static void tg3_set_rx_mode(struct net_device *dev)
13908{
13909 struct tg3 *tp = netdev_priv(dev);
13910
13911 if (!netif_running(dev))
13912 return;
13913
13914 tg3_full_lock(tp, 0);
13915 __tg3_set_rx_mode(dev);
13916 tg3_full_unlock(tp);
13917}
13918
faf1627a
MC		 13919static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
13920 int new_mtu)
13921{
13922 dev->mtu = new_mtu;
13923
13924 if (new_mtu > ETH_DATA_LEN) {
13925 if (tg3_flag(tp, 5780_CLASS)) {
13926 netdev_update_features(dev);
13927 tg3_flag_clear(tp, TSO_CAPABLE);
13928 } else {
13929 tg3_flag_set(tp, JUMBO_RING_ENABLE);
13930 }
13931 } else {
13932 if (tg3_flag(tp, 5780_CLASS)) {
13933 tg3_flag_set(tp, TSO_CAPABLE);
13934 netdev_update_features(dev);
13935 }
13936 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
13937 }
13938}
13939
13940static int tg3_change_mtu(struct net_device *dev, int new_mtu)
13941{
13942 struct tg3 *tp = netdev_priv(dev);
953c96e0
JP		 13943 int err;
13944 bool reset_phy = false;
faf1627a
MC		 13945
13946 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
13947 return -EINVAL;
13948
13949 if (!netif_running(dev)) {
13950 /* We'll just catch it later when the
13951 * device is up'd.
13952 */
13953 tg3_set_mtu(dev, tp, new_mtu);
13954 return 0;
13955 }
13956
13957 tg3_phy_stop(tp);
13958
13959 tg3_netif_stop(tp);
13960
13961 tg3_full_lock(tp, 1);
13962
13963 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13964
13965 tg3_set_mtu(dev, tp, new_mtu);
13966
2fae5e36
MC		 13967 /* Reset PHY, otherwise the read DMA engine will be in a mode that
13968 * breaks all requests to 256 bytes.
13969 */
4153577a 13970 if (tg3_asic_rev(tp) == ASIC_REV_57766)
953c96e0 13971 reset_phy = true;
2fae5e36
MC		 13972
13973 err = tg3_restart_hw(tp, reset_phy);
faf1627a
MC		 13974
13975 if (!err)
13976 tg3_netif_start(tp);
13977
13978 tg3_full_unlock(tp);
13979
13980 if (!err)
13981 tg3_phy_start(tp);
13982
13983 return err;
13984}
13985
13986static const struct net_device_ops tg3_netdev_ops = {
13987 .ndo_open = tg3_open,
13988 .ndo_stop = tg3_close,
13989 .ndo_start_xmit = tg3_start_xmit,
13990 .ndo_get_stats64 = tg3_get_stats64,
13991 .ndo_validate_addr = eth_validate_addr,
13992 .ndo_set_rx_mode = tg3_set_rx_mode,
13993 .ndo_set_mac_address = tg3_set_mac_addr,
13994 .ndo_do_ioctl = tg3_ioctl,
13995 .ndo_tx_timeout = tg3_tx_timeout,
13996 .ndo_change_mtu = tg3_change_mtu,
13997 .ndo_fix_features = tg3_fix_features,
13998 .ndo_set_features = tg3_set_features,
13999#ifdef CONFIG_NET_POLL_CONTROLLER
14000 .ndo_poll_controller = tg3_poll_controller,
14001#endif
14002};
14003
229b1ad1 14004static void tg3_get_eeprom_size(struct tg3 *tp)
1da177e4 14005{
1b27777a 14006 u32 cursize, val, magic;
1da177e4
LT		 14007
14008 tp->nvram_size = EEPROM_CHIP_SIZE;
14009
e4f34110 14010 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 14011 return;
14012
b16250e3
MC		 14013 if ((magic != TG3_EEPROM_MAGIC) &&
14014 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14015 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 14016 return;
14017
14018 /*
14019 * Size the chip by reading offsets at increasing powers of two.
14020 * When we encounter our validation signature, we know the addressing
14021 * has wrapped around, and thus have our chip size.
14022 */
1b27777a 14023 cursize = 0x10;
1da177e4
LT		 14024
14025 while (cursize < tp->nvram_size) {
e4f34110 14026 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 14027 return;
14028
1820180b 14029 if (val == magic)
1da177e4
LT		 14030 break;
14031
14032 cursize <<= 1;
14033 }
14034
14035 tp->nvram_size = cursize;
14036}
6aa20a22 14037
229b1ad1 14038static void tg3_get_nvram_size(struct tg3 *tp)
1da177e4
LT		 14039{
14040 u32 val;
14041
63c3a66f 14042 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 14043 return;
14044
14045 /* Selfboot format */
1820180b 14046 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 14047 tg3_get_eeprom_size(tp);
14048 return;
14049 }
14050
6d348f2c 14051 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 14052 if (val != 0) {
6d348f2c
MC		 14053 /* This is confusing. We want to operate on the
14054 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14055 * call will read from NVRAM and byteswap the data
14056 * according to the byteswapping settings for all
14057 * other register accesses. This ensures the data we
14058 * want will always reside in the lower 16-bits.
14059 * However, the data in NVRAM is in LE format, which
14060 * means the data from the NVRAM read will always be
14061 * opposite the endianness of the CPU. The 16-bit
14062 * byteswap then brings the data to CPU endianness.
14063 */
14064 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 14065 return;
14066 }
14067 }
fd1122a2 14068 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 14069}
14070
229b1ad1 14071static void tg3_get_nvram_info(struct tg3 *tp)
1da177e4
LT		 14072{
14073 u32 nvcfg1;
14074
14075 nvcfg1 = tr32(NVRAM_CFG1);
14076 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
63c3a66f 14077 tg3_flag_set(tp, FLASH);
8590a603 14078 } else {
1da177e4
LT		 14079 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14080 tw32(NVRAM_CFG1, nvcfg1);
14081 }
14082
4153577a 14083 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
63c3a66f 14084 tg3_flag(tp, 5780_CLASS)) {
1da177e4 14085 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 14086 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14087 tp->nvram_jedecnum = JEDEC_ATMEL;
14088 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14089 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14090 break;
14091 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14092 tp->nvram_jedecnum = JEDEC_ATMEL;
14093 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14094 break;
14095 case FLASH_VENDOR_ATMEL_EEPROM:
14096 tp->nvram_jedecnum = JEDEC_ATMEL;
14097 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
63c3a66f 14098 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14099 break;
14100 case FLASH_VENDOR_ST:
14101 tp->nvram_jedecnum = JEDEC_ST;
14102 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
63c3a66f 14103 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14104 break;
14105 case FLASH_VENDOR_SAIFUN:
14106 tp->nvram_jedecnum = JEDEC_SAIFUN;
14107 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14108 break;
14109 case FLASH_VENDOR_SST_SMALL:
14110 case FLASH_VENDOR_SST_LARGE:
14111 tp->nvram_jedecnum = JEDEC_SST;
14112 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14113 break;
1da177e4 14114 }
8590a603 14115 } else {
1da177e4
LT		 14116 tp->nvram_jedecnum = JEDEC_ATMEL;
14117 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14118 tg3_flag_set(tp, NVRAM_BUFFERED);
1da177e4
LT		 14119 }
14120}
14121
229b1ad1 14122static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
a1b950d5
MC		 14123{
14124 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14125 case FLASH_5752PAGE_SIZE_256:
14126 tp->nvram_pagesize = 256;
14127 break;
14128 case FLASH_5752PAGE_SIZE_512:
14129 tp->nvram_pagesize = 512;
14130 break;
14131 case FLASH_5752PAGE_SIZE_1K:
14132 tp->nvram_pagesize = 1024;
14133 break;
14134 case FLASH_5752PAGE_SIZE_2K:
14135 tp->nvram_pagesize = 2048;
14136 break;
14137 case FLASH_5752PAGE_SIZE_4K:
14138 tp->nvram_pagesize = 4096;
14139 break;
14140 case FLASH_5752PAGE_SIZE_264:
14141 tp->nvram_pagesize = 264;
14142 break;
14143 case FLASH_5752PAGE_SIZE_528:
14144 tp->nvram_pagesize = 528;
14145 break;
14146 }
14147}
14148
229b1ad1 14149static void tg3_get_5752_nvram_info(struct tg3 *tp)
361b4ac2
MC		 14150{
14151 u32 nvcfg1;
14152
14153 nvcfg1 = tr32(NVRAM_CFG1);
14154
e6af301b
MC		 14155 /* NVRAM protection for TPM */
14156 if (nvcfg1 & (1 << 27))
63c3a66f 14157 tg3_flag_set(tp, PROTECTED_NVRAM);
e6af301b 14158
361b4ac2 14159 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14160 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14161 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14162 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14163 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14164 break;
14165 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14166 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14167 tg3_flag_set(tp, NVRAM_BUFFERED);
14168 tg3_flag_set(tp, FLASH);
8590a603
MC		 14169 break;
14170 case FLASH_5752VENDOR_ST_M45PE10:
14171 case FLASH_5752VENDOR_ST_M45PE20:
14172 case FLASH_5752VENDOR_ST_M45PE40:
14173 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14174 tg3_flag_set(tp, NVRAM_BUFFERED);
14175 tg3_flag_set(tp, FLASH);
8590a603 14176 break;
361b4ac2
MC		 14177 }
14178
63c3a66f 14179 if (tg3_flag(tp, FLASH)) {
a1b950d5 14180 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 14181 } else {
361b4ac2
MC		 14182 /* For eeprom, set pagesize to maximum eeprom size */
14183 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14184
14185 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14186 tw32(NVRAM_CFG1, nvcfg1);
14187 }
14188}
14189
229b1ad1 14190static void tg3_get_5755_nvram_info(struct tg3 *tp)
d3c7b886 14191{
989a9d23 14192 u32 nvcfg1, protect = 0;
d3c7b886
MC		 14193
14194 nvcfg1 = tr32(NVRAM_CFG1);
14195
14196 /* NVRAM protection for TPM */
989a9d23 14197 if (nvcfg1 & (1 << 27)) {
63c3a66f 14198 tg3_flag_set(tp, PROTECTED_NVRAM);
989a9d23
MC		 14199 protect = 1;
14200 }
d3c7b886 14201
989a9d23
MC		 14202 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14203 switch (nvcfg1) {
8590a603
MC		 14204 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14205 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14206 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14207 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14208 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14209 tg3_flag_set(tp, NVRAM_BUFFERED);
14210 tg3_flag_set(tp, FLASH);
8590a603
MC		 14211 tp->nvram_pagesize = 264;
14212 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14213 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14214 tp->nvram_size = (protect ? 0x3e200 :
14215 TG3_NVRAM_SIZE_512KB);
14216 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14217 tp->nvram_size = (protect ? 0x1f200 :
14218 TG3_NVRAM_SIZE_256KB);
14219 else
14220 tp->nvram_size = (protect ? 0x1f200 :
14221 TG3_NVRAM_SIZE_128KB);
14222 break;
14223 case FLASH_5752VENDOR_ST_M45PE10:
14224 case FLASH_5752VENDOR_ST_M45PE20:
14225 case FLASH_5752VENDOR_ST_M45PE40:
14226 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14227 tg3_flag_set(tp, NVRAM_BUFFERED);
14228 tg3_flag_set(tp, FLASH);
8590a603
MC		 14229 tp->nvram_pagesize = 256;
14230 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14231 tp->nvram_size = (protect ?
14232 TG3_NVRAM_SIZE_64KB :
14233 TG3_NVRAM_SIZE_128KB);
14234 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14235 tp->nvram_size = (protect ?
14236 TG3_NVRAM_SIZE_64KB :
14237 TG3_NVRAM_SIZE_256KB);
14238 else
14239 tp->nvram_size = (protect ?
14240 TG3_NVRAM_SIZE_128KB :
14241 TG3_NVRAM_SIZE_512KB);
14242 break;
d3c7b886
MC		 14243 }
14244}
14245
229b1ad1 14246static void tg3_get_5787_nvram_info(struct tg3 *tp)
1b27777a
MC		 14247{
14248 u32 nvcfg1;
14249
14250 nvcfg1 = tr32(NVRAM_CFG1);
14251
14252 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14253 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14254 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14255 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14256 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14257 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14258 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603 14259 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 14260
8590a603
MC		 14261 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14262 tw32(NVRAM_CFG1, nvcfg1);
14263 break;
14264 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14265 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14266 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14267 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14268 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14269 tg3_flag_set(tp, NVRAM_BUFFERED);
14270 tg3_flag_set(tp, FLASH);
8590a603
MC		 14271 tp->nvram_pagesize = 264;
14272 break;
14273 case FLASH_5752VENDOR_ST_M45PE10:
14274 case FLASH_5752VENDOR_ST_M45PE20:
14275 case FLASH_5752VENDOR_ST_M45PE40:
14276 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14277 tg3_flag_set(tp, NVRAM_BUFFERED);
14278 tg3_flag_set(tp, FLASH);
8590a603
MC		 14279 tp->nvram_pagesize = 256;
14280 break;
1b27777a
MC		 14281 }
14282}
14283
229b1ad1 14284static void tg3_get_5761_nvram_info(struct tg3 *tp)
6b91fa02
MC		 14285{
14286 u32 nvcfg1, protect = 0;
14287
14288 nvcfg1 = tr32(NVRAM_CFG1);
14289
14290 /* NVRAM protection for TPM */
14291 if (nvcfg1 & (1 << 27)) {
63c3a66f 14292 tg3_flag_set(tp, PROTECTED_NVRAM);
6b91fa02
MC		 14293 protect = 1;
14294 }
14295
14296 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14297 switch (nvcfg1) {
8590a603
MC		 14298 case FLASH_5761VENDOR_ATMEL_ADB021D:
14299 case FLASH_5761VENDOR_ATMEL_ADB041D:
14300 case FLASH_5761VENDOR_ATMEL_ADB081D:
14301 case FLASH_5761VENDOR_ATMEL_ADB161D:
14302 case FLASH_5761VENDOR_ATMEL_MDB021D:
14303 case FLASH_5761VENDOR_ATMEL_MDB041D:
14304 case FLASH_5761VENDOR_ATMEL_MDB081D:
14305 case FLASH_5761VENDOR_ATMEL_MDB161D:
14306 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14307 tg3_flag_set(tp, NVRAM_BUFFERED);
14308 tg3_flag_set(tp, FLASH);
14309 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
8590a603
MC		 14310 tp->nvram_pagesize = 256;
14311 break;
14312 case FLASH_5761VENDOR_ST_A_M45PE20:
14313 case FLASH_5761VENDOR_ST_A_M45PE40:
14314 case FLASH_5761VENDOR_ST_A_M45PE80:
14315 case FLASH_5761VENDOR_ST_A_M45PE16:
14316 case FLASH_5761VENDOR_ST_M_M45PE20:
14317 case FLASH_5761VENDOR_ST_M_M45PE40:
14318 case FLASH_5761VENDOR_ST_M_M45PE80:
14319 case FLASH_5761VENDOR_ST_M_M45PE16:
14320 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14321 tg3_flag_set(tp, NVRAM_BUFFERED);
14322 tg3_flag_set(tp, FLASH);
8590a603
MC		 14323 tp->nvram_pagesize = 256;
14324 break;
6b91fa02
MC		 14325 }
14326
14327 if (protect) {
14328 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14329 } else {
14330 switch (nvcfg1) {
8590a603
MC		 14331 case FLASH_5761VENDOR_ATMEL_ADB161D:
14332 case FLASH_5761VENDOR_ATMEL_MDB161D:
14333 case FLASH_5761VENDOR_ST_A_M45PE16:
14334 case FLASH_5761VENDOR_ST_M_M45PE16:
14335 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14336 break;
14337 case FLASH_5761VENDOR_ATMEL_ADB081D:
14338 case FLASH_5761VENDOR_ATMEL_MDB081D:
14339 case FLASH_5761VENDOR_ST_A_M45PE80:
14340 case FLASH_5761VENDOR_ST_M_M45PE80:
14341 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14342 break;
14343 case FLASH_5761VENDOR_ATMEL_ADB041D:
14344 case FLASH_5761VENDOR_ATMEL_MDB041D:
14345 case FLASH_5761VENDOR_ST_A_M45PE40:
14346 case FLASH_5761VENDOR_ST_M_M45PE40:
14347 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14348 break;
14349 case FLASH_5761VENDOR_ATMEL_ADB021D:
14350 case FLASH_5761VENDOR_ATMEL_MDB021D:
14351 case FLASH_5761VENDOR_ST_A_M45PE20:
14352 case FLASH_5761VENDOR_ST_M_M45PE20:
14353 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14354 break;
6b91fa02
MC		 14355 }
14356 }
14357}
14358
229b1ad1 14359static void tg3_get_5906_nvram_info(struct tg3 *tp)
b5d3772c
MC		 14360{
14361 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14362 tg3_flag_set(tp, NVRAM_BUFFERED);
b5d3772c
MC		 14363 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14364}
14365
229b1ad1 14366static void tg3_get_57780_nvram_info(struct tg3 *tp)
321d32a0
MC		 14367{
14368 u32 nvcfg1;
14369
14370 nvcfg1 = tr32(NVRAM_CFG1);
14371
14372 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14373 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14374 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14375 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14376 tg3_flag_set(tp, NVRAM_BUFFERED);
321d32a0
MC		 14377 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14378
14379 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14380 tw32(NVRAM_CFG1, nvcfg1);
14381 return;
14382 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14383 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14384 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14385 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14386 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14387 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14388 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14389 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14390 tg3_flag_set(tp, NVRAM_BUFFERED);
14391 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14392
14393 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14394 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14395 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14396 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14397 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14398 break;
14399 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14400 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14401 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14402 break;
14403 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14404 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14405 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14406 break;
14407 }
14408 break;
14409 case FLASH_5752VENDOR_ST_M45PE10:
14410 case FLASH_5752VENDOR_ST_M45PE20:
14411 case FLASH_5752VENDOR_ST_M45PE40:
14412 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14413 tg3_flag_set(tp, NVRAM_BUFFERED);
14414 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14415
14416 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14417 case FLASH_5752VENDOR_ST_M45PE10:
14418 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14419 break;
14420 case FLASH_5752VENDOR_ST_M45PE20:
14421 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14422 break;
14423 case FLASH_5752VENDOR_ST_M45PE40:
14424 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14425 break;
14426 }
14427 break;
14428 default:
63c3a66f 14429 tg3_flag_set(tp, NO_NVRAM);
321d32a0
MC		 14430 return;
14431 }
14432
a1b950d5
MC		 14433 tg3_nvram_get_pagesize(tp, nvcfg1);
14434 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14435 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
a1b950d5
MC		 14436}
14437
14438
229b1ad1 14439static void tg3_get_5717_nvram_info(struct tg3 *tp)
a1b950d5
MC		 14440{
14441 u32 nvcfg1;
14442
14443 nvcfg1 = tr32(NVRAM_CFG1);
14444
14445 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14446 case FLASH_5717VENDOR_ATMEL_EEPROM:
14447 case FLASH_5717VENDOR_MICRO_EEPROM:
14448 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14449 tg3_flag_set(tp, NVRAM_BUFFERED);
a1b950d5
MC		 14450 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14451
14452 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14453 tw32(NVRAM_CFG1, nvcfg1);
14454 return;
14455 case FLASH_5717VENDOR_ATMEL_MDB011D:
14456 case FLASH_5717VENDOR_ATMEL_ADB011B:
14457 case FLASH_5717VENDOR_ATMEL_ADB011D:
14458 case FLASH_5717VENDOR_ATMEL_MDB021D:
14459 case FLASH_5717VENDOR_ATMEL_ADB021B:
14460 case FLASH_5717VENDOR_ATMEL_ADB021D:
14461 case FLASH_5717VENDOR_ATMEL_45USPT:
14462 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14463 tg3_flag_set(tp, NVRAM_BUFFERED);
14464 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14465
14466 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14467 case FLASH_5717VENDOR_ATMEL_MDB021D:
66ee33bf
MC		 14468 /* Detect size with tg3_nvram_get_size() */
14469 break;
a1b950d5
MC		 14470 case FLASH_5717VENDOR_ATMEL_ADB021B:
14471 case FLASH_5717VENDOR_ATMEL_ADB021D:
14472 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14473 break;
14474 default:
14475 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14476 break;
14477 }
321d32a0 14478 break;
a1b950d5
MC		 14479 case FLASH_5717VENDOR_ST_M_M25PE10:
14480 case FLASH_5717VENDOR_ST_A_M25PE10:
14481 case FLASH_5717VENDOR_ST_M_M45PE10:
14482 case FLASH_5717VENDOR_ST_A_M45PE10:
14483 case FLASH_5717VENDOR_ST_M_M25PE20:
14484 case FLASH_5717VENDOR_ST_A_M25PE20:
14485 case FLASH_5717VENDOR_ST_M_M45PE20:
14486 case FLASH_5717VENDOR_ST_A_M45PE20:
14487 case FLASH_5717VENDOR_ST_25USPT:
14488 case FLASH_5717VENDOR_ST_45USPT:
14489 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14490 tg3_flag_set(tp, NVRAM_BUFFERED);
14491 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14492
14493 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14494 case FLASH_5717VENDOR_ST_M_M25PE20:
a1b950d5 14495 case FLASH_5717VENDOR_ST_M_M45PE20:
66ee33bf
MC		 14496 /* Detect size with tg3_nvram_get_size() */
14497 break;
14498 case FLASH_5717VENDOR_ST_A_M25PE20:
a1b950d5
MC		 14499 case FLASH_5717VENDOR_ST_A_M45PE20:
14500 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14501 break;
14502 default:
14503 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14504 break;
14505 }
321d32a0 14506 break;
a1b950d5 14507 default:
63c3a66f 14508 tg3_flag_set(tp, NO_NVRAM);
a1b950d5 14509 return;
321d32a0 14510 }
a1b950d5
MC		 14511
14512 tg3_nvram_get_pagesize(tp, nvcfg1);
14513 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14514 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
321d32a0
MC		 14515}
14516
229b1ad1 14517static void tg3_get_5720_nvram_info(struct tg3 *tp)
9b91b5f1
MC		 14518{
14519 u32 nvcfg1, nvmpinstrp;
14520
14521 nvcfg1 = tr32(NVRAM_CFG1);
14522 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14523
4153577a 14524 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14525 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14526 tg3_flag_set(tp, NO_NVRAM);
14527 return;
14528 }
14529
14530 switch (nvmpinstrp) {
14531 case FLASH_5762_EEPROM_HD:
14532 nvmpinstrp = FLASH_5720_EEPROM_HD;
17e1a42f 14533 break;
c86a8560
MC		 14534 case FLASH_5762_EEPROM_LD:
14535 nvmpinstrp = FLASH_5720_EEPROM_LD;
17e1a42f 14536 break;
f6334bb8
MC		 14537 case FLASH_5720VENDOR_M_ST_M45PE20:
14538 /* This pinstrap supports multiple sizes, so force it
14539 * to read the actual size from location 0xf0.
14540 */
14541 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14542 break;
c86a8560
MC		 14543 }
14544 }
14545
9b91b5f1
MC		 14546 switch (nvmpinstrp) {
14547 case FLASH_5720_EEPROM_HD:
14548 case FLASH_5720_EEPROM_LD:
14549 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14550 tg3_flag_set(tp, NVRAM_BUFFERED);
9b91b5f1
MC		 14551
14552 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14553 tw32(NVRAM_CFG1, nvcfg1);
14554 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14555 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14556 else
14557 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14558 return;
14559 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14560 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14561 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14562 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14563 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14564 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14565 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14566 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14567 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14568 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14569 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14570 case FLASH_5720VENDOR_ATMEL_45USPT:
14571 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14572 tg3_flag_set(tp, NVRAM_BUFFERED);
14573 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14574
14575 switch (nvmpinstrp) {
14576 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14577 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14578 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14579 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14580 break;
14581 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14582 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14583 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14584 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14585 break;
14586 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14587 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14588 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14589 break;
14590 default:
4153577a 14591 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14592 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14593 break;
14594 }
14595 break;
14596 case FLASH_5720VENDOR_M_ST_M25PE10:
14597 case FLASH_5720VENDOR_M_ST_M45PE10:
14598 case FLASH_5720VENDOR_A_ST_M25PE10:
14599 case FLASH_5720VENDOR_A_ST_M45PE10:
14600 case FLASH_5720VENDOR_M_ST_M25PE20:
14601 case FLASH_5720VENDOR_M_ST_M45PE20:
14602 case FLASH_5720VENDOR_A_ST_M25PE20:
14603 case FLASH_5720VENDOR_A_ST_M45PE20:
14604 case FLASH_5720VENDOR_M_ST_M25PE40:
14605 case FLASH_5720VENDOR_M_ST_M45PE40:
14606 case FLASH_5720VENDOR_A_ST_M25PE40:
14607 case FLASH_5720VENDOR_A_ST_M45PE40:
14608 case FLASH_5720VENDOR_M_ST_M25PE80:
14609 case FLASH_5720VENDOR_M_ST_M45PE80:
14610 case FLASH_5720VENDOR_A_ST_M25PE80:
14611 case FLASH_5720VENDOR_A_ST_M45PE80:
14612 case FLASH_5720VENDOR_ST_25USPT:
14613 case FLASH_5720VENDOR_ST_45USPT:
14614 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14615 tg3_flag_set(tp, NVRAM_BUFFERED);
14616 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14617
14618 switch (nvmpinstrp) {
14619 case FLASH_5720VENDOR_M_ST_M25PE20:
14620 case FLASH_5720VENDOR_M_ST_M45PE20:
14621 case FLASH_5720VENDOR_A_ST_M25PE20:
14622 case FLASH_5720VENDOR_A_ST_M45PE20:
14623 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14624 break;
14625 case FLASH_5720VENDOR_M_ST_M25PE40:
14626 case FLASH_5720VENDOR_M_ST_M45PE40:
14627 case FLASH_5720VENDOR_A_ST_M25PE40:
14628 case FLASH_5720VENDOR_A_ST_M45PE40:
14629 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14630 break;
14631 case FLASH_5720VENDOR_M_ST_M25PE80:
14632 case FLASH_5720VENDOR_M_ST_M45PE80:
14633 case FLASH_5720VENDOR_A_ST_M25PE80:
14634 case FLASH_5720VENDOR_A_ST_M45PE80:
14635 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14636 break;
14637 default:
4153577a 14638 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14639 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14640 break;
14641 }
14642 break;
14643 default:
63c3a66f 14644 tg3_flag_set(tp, NO_NVRAM);
9b91b5f1
MC		 14645 return;
14646 }
14647
14648 tg3_nvram_get_pagesize(tp, nvcfg1);
14649 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14650 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
c86a8560 14651
4153577a 14652 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14653 u32 val;
14654
14655 if (tg3_nvram_read(tp, 0, &val))
14656 return;
14657
14658 if (val != TG3_EEPROM_MAGIC &&
14659 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14660 tg3_flag_set(tp, NO_NVRAM);
14661 }
9b91b5f1
MC		 14662}
14663
1da177e4 14664/* Chips other than 5700/5701 use the NVRAM for fetching info. */
229b1ad1 14665static void tg3_nvram_init(struct tg3 *tp)
1da177e4 14666{
7e6c63f0
HM		 14667 if (tg3_flag(tp, IS_SSB_CORE)) {
14668 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14669 tg3_flag_clear(tp, NVRAM);
14670 tg3_flag_clear(tp, NVRAM_BUFFERED);
14671 tg3_flag_set(tp, NO_NVRAM);
14672 return;
14673 }
14674
1da177e4
LT		 14675 tw32_f(GRC_EEPROM_ADDR,
14676 (EEPROM_ADDR_FSM_RESET |
14677 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14678 EEPROM_ADDR_CLKPERD_SHIFT)));
14679
9d57f01c 14680 msleep(1);
1da177e4
LT		 14681
14682 /* Enable seeprom accesses. */
14683 tw32_f(GRC_LOCAL_CTRL,
14684 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14685 udelay(100);
14686
4153577a
JP		 14687 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14688 tg3_asic_rev(tp) != ASIC_REV_5701) {
63c3a66f 14689 tg3_flag_set(tp, NVRAM);
1da177e4 14690
ec41c7df 14691 if (tg3_nvram_lock(tp)) {
5129c3a3
MC		 14692 netdev_warn(tp->dev,
14693 "Cannot get nvram lock, %s failed\n",
05dbe005 14694 __func__);
ec41c7df
MC		 14695 return;
14696 }
e6af301b 14697 tg3_enable_nvram_access(tp);
1da177e4 14698
989a9d23
MC		 14699 tp->nvram_size = 0;
14700
4153577a 14701 if (tg3_asic_rev(tp) == ASIC_REV_5752)
361b4ac2 14702 tg3_get_5752_nvram_info(tp);
4153577a 14703 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
d3c7b886 14704 tg3_get_5755_nvram_info(tp);
4153577a
JP		 14705 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14706 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14707 tg3_asic_rev(tp) == ASIC_REV_5785)
1b27777a 14708 tg3_get_5787_nvram_info(tp);
4153577a 14709 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
6b91fa02 14710 tg3_get_5761_nvram_info(tp);
4153577a 14711 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 14712 tg3_get_5906_nvram_info(tp);
4153577a 14713 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 14714 tg3_flag(tp, 57765_CLASS))
321d32a0 14715 tg3_get_57780_nvram_info(tp);
4153577a
JP		 14716 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14717 tg3_asic_rev(tp) == ASIC_REV_5719)
a1b950d5 14718 tg3_get_5717_nvram_info(tp);
4153577a
JP		 14719 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14720 tg3_asic_rev(tp) == ASIC_REV_5762)
9b91b5f1 14721 tg3_get_5720_nvram_info(tp);
361b4ac2
MC		 14722 else
14723 tg3_get_nvram_info(tp);
14724
989a9d23
MC		 14725 if (tp->nvram_size == 0)
14726 tg3_get_nvram_size(tp);
1da177e4 14727
e6af301b 14728 tg3_disable_nvram_access(tp);
381291b7 14729 tg3_nvram_unlock(tp);
1da177e4
LT		 14730
14731 } else {
63c3a66f
JP		 14732 tg3_flag_clear(tp, NVRAM);
14733 tg3_flag_clear(tp, NVRAM_BUFFERED);
1da177e4
LT		 14734
14735 tg3_get_eeprom_size(tp);
14736 }
14737}
14738
1da177e4
LT		 14739struct subsys_tbl_ent {
14740 u16 subsys_vendor, subsys_devid;
14741 u32 phy_id;
14742};
14743
229b1ad1 14744static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
1da177e4 14745 /* Broadcom boards. */
24daf2b0 14746 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14747 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 14748 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14749 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 14750 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14751 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 14752 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14753 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14754 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14755 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 14756 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14757 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14758 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14759 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14760 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14761 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 14762 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14763 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 14764 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14765 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 14766 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14767 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 14768
14769 /* 3com boards. */
24daf2b0 14770 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14771 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 14772 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14773 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14774 { TG3PCI_SUBVENDOR_ID_3COM,
14775 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
14776 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14777 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 14778 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14779 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14780
14781 /* DELL boards. */
24daf2b0 14782 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14783 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 14784 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14785 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 14786 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14787 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 14788 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14789 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 14790
14791 /* Compaq boards. */
24daf2b0 14792 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14793 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 14794 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14795 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14796 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14797 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
14798 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14799 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 14800 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14801 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14802
14803 /* IBM boards. */
24daf2b0
MC		 14804 { TG3PCI_SUBVENDOR_ID_IBM,
14805 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 14806};
14807
229b1ad1 14808static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 14809{
14810 int i;
14811
14812 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
14813 if ((subsys_id_to_phy_id[i].subsys_vendor ==
14814 tp->pdev->subsystem_vendor) &&
14815 (subsys_id_to_phy_id[i].subsys_devid ==
14816 tp->pdev->subsystem_device))
14817 return &subsys_id_to_phy_id[i];
14818 }
14819 return NULL;
14820}
14821
229b1ad1 14822static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 14823{
1da177e4 14824 u32 val;
f49639e6 14825
79eb6904 14826 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 14827 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14828
a85feb8c 14829 /* Assume an onboard device and WOL capable by default. */
63c3a66f
JP		 14830 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14831 tg3_flag_set(tp, WOL_CAP);
72b845e0 14832
4153577a 14833 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9d26e213 14834 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
63c3a66f
JP		 14835 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14836 tg3_flag_set(tp, IS_NIC);
9d26e213 14837 }
0527ba35
MC		 14838 val = tr32(VCPU_CFGSHDW);
14839 if (val & VCPU_CFGSHDW_ASPM_DBNC)
63c3a66f 14840 tg3_flag_set(tp, ASPM_WORKAROUND);
0527ba35 14841 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
6fdbab9d 14842 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
63c3a66f 14843 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 14844 device_set_wakeup_enable(&tp->pdev->dev, true);
14845 }
05ac4cb7 14846 goto done;
b5d3772c
MC		 14847 }
14848
1da177e4
LT		 14849 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
14850 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
14851 u32 nic_cfg, led_cfg;
a9daf367 14852 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 14853 int eeprom_phy_serdes = 0;
1da177e4
LT		 14854
14855 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
14856 tp->nic_sram_data_cfg = nic_cfg;
14857
14858 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
14859 ver >>= NIC_SRAM_DATA_VER_SHIFT;
4153577a
JP		 14860 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14861 tg3_asic_rev(tp) != ASIC_REV_5701 &&
14862 tg3_asic_rev(tp) != ASIC_REV_5703 &&
1da177e4
LT		 14863 (ver > 0) && (ver < 0x100))
14864 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
14865
4153577a 14866 if (tg3_asic_rev(tp) == ASIC_REV_5785)
a9daf367
MC		 14867 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
14868
1da177e4
LT		 14869 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
14870 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
14871 eeprom_phy_serdes = 1;
14872
14873 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
14874 if (nic_phy_id != 0) {
14875 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
14876 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
14877
14878 eeprom_phy_id = (id1 >> 16) << 10;
14879 eeprom_phy_id |= (id2 & 0xfc00) << 16;
14880 eeprom_phy_id |= (id2 & 0x03ff) << 0;
14881 } else
14882 eeprom_phy_id = 0;
14883
7d0c41ef 14884 tp->phy_id = eeprom_phy_id;
747e8f8b 14885 if (eeprom_phy_serdes) {
63c3a66f 14886 if (!tg3_flag(tp, 5705_PLUS))
f07e9af3 14887 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
a50d0796 14888 else
f07e9af3 14889 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
747e8f8b 14890 }
7d0c41ef 14891
63c3a66f 14892 if (tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 14893 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
14894 SHASTA_EXT_LED_MODE_MASK);
cbf46853 14895 else
1da177e4
LT		 14896 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
14897
14898 switch (led_cfg) {
14899 default:
14900 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
14901 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14902 break;
14903
14904 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
14905 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14906 break;
14907
14908 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
14909 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 14910
14911 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
14912 * read on some older 5700/5701 bootcode.
14913 */
4153577a
JP		 14914 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
14915 tg3_asic_rev(tp) == ASIC_REV_5701)
9ba27794
MC		 14916 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14917
1da177e4
LT		 14918 break;
14919
14920 case SHASTA_EXT_LED_SHARED:
14921 tp->led_ctrl = LED_CTRL_MODE_SHARED;
4153577a
JP		 14922 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
14923 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
1da177e4
LT		 14924 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14925 LED_CTRL_MODE_PHY_2);
14926 break;
14927
14928 case SHASTA_EXT_LED_MAC:
14929 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
14930 break;
14931
14932 case SHASTA_EXT_LED_COMBO:
14933 tp->led_ctrl = LED_CTRL_MODE_COMBO;
4153577a 14934 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
1da177e4
LT		 14935 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14936 LED_CTRL_MODE_PHY_2);
14937 break;
14938
855e1111 14939 }
1da177e4 14940
4153577a
JP		 14941 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
14942 tg3_asic_rev(tp) == ASIC_REV_5701) &&
1da177e4
LT		 14943 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
14944 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14945
4153577a 14946 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
b2a5c19c 14947 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 14948
9d26e213 14949 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
63c3a66f 14950 tg3_flag_set(tp, EEPROM_WRITE_PROT);
9d26e213
MC		 14951 if ((tp->pdev->subsystem_vendor ==
14952 PCI_VENDOR_ID_ARIMA) &&
14953 (tp->pdev->subsystem_device == 0x205a ||
14954 tp->pdev->subsystem_device == 0x2063))
63c3a66f 14955 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
9d26e213 14956 } else {
63c3a66f
JP		 14957 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14958 tg3_flag_set(tp, IS_NIC);
9d26e213 14959 }
1da177e4
LT		 14960
14961 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f
JP		 14962 tg3_flag_set(tp, ENABLE_ASF);
14963 if (tg3_flag(tp, 5750_PLUS))
14964 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
1da177e4 14965 }
b2b98d4a
MC		 14966
14967 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
63c3a66f
JP		 14968 tg3_flag(tp, 5750_PLUS))
14969 tg3_flag_set(tp, ENABLE_APE);
b2b98d4a 14970
f07e9af3 14971 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
a85feb8c 14972 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
63c3a66f 14973 tg3_flag_clear(tp, WOL_CAP);
1da177e4 14974
63c3a66f 14975 if (tg3_flag(tp, WOL_CAP) &&
6fdbab9d 14976 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
63c3a66f 14977 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 14978 device_set_wakeup_enable(&tp->pdev->dev, true);
14979 }
0527ba35 14980
1da177e4 14981 if (cfg2 & (1 << 17))
f07e9af3 14982 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
1da177e4
LT		 14983
14984 /* serdes signal pre-emphasis in register 0x590 set by */
14985 /* bootcode if bit 18 is set */
14986 if (cfg2 & (1 << 18))
f07e9af3 14987 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
8ed5d97e 14988
63c3a66f 14989 if ((tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 14990 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
14991 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
6833c043 14992 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
f07e9af3 14993 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
6833c043 14994
942d1af0 14995 if (tg3_flag(tp, PCI_EXPRESS)) {
8ed5d97e
MC		 14996 u32 cfg3;
14997
14998 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
942d1af0
NS		 14999 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15000 !tg3_flag(tp, 57765_PLUS) &&
15001 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
63c3a66f 15002 tg3_flag_set(tp, ASPM_WORKAROUND);
942d1af0
NS		 15003 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15004 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15005 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15006 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
8ed5d97e 15007 }
a9daf367 15008
14417063 15009 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
63c3a66f 15010 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
a9daf367 15011 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
63c3a66f 15012 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
a9daf367 15013 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
63c3a66f 15014 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
1da177e4 15015 }
05ac4cb7 15016done:
63c3a66f 15017 if (tg3_flag(tp, WOL_CAP))
43067ed8 15018 device_set_wakeup_enable(&tp->pdev->dev,
63c3a66f 15019 tg3_flag(tp, WOL_ENABLE));
43067ed8
RW		 15020 else
15021 device_set_wakeup_capable(&tp->pdev->dev, false);
7d0c41ef
MC		 15022}
15023
c86a8560
MC		 15024static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15025{
15026 int i, err;
15027 u32 val2, off = offset * 8;
15028
15029 err = tg3_nvram_lock(tp);
15030 if (err)
15031 return err;
15032
15033 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15034 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15035 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15036 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15037 udelay(10);
15038
15039 for (i = 0; i < 100; i++) {
15040 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15041 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15042 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15043 break;
15044 }
15045 udelay(10);
15046 }
15047
15048 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15049
15050 tg3_nvram_unlock(tp);
15051 if (val2 & APE_OTP_STATUS_CMD_DONE)
15052 return 0;
15053
15054 return -EBUSY;
15055}
15056
229b1ad1 15057static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
b2a5c19c
MC		 15058{
15059 int i;
15060 u32 val;
15061
15062 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15063 tw32(OTP_CTRL, cmd);
15064
15065 /* Wait for up to 1 ms for command to execute. */
15066 for (i = 0; i < 100; i++) {
15067 val = tr32(OTP_STATUS);
15068 if (val & OTP_STATUS_CMD_DONE)
15069 break;
15070 udelay(10);
15071 }
15072
15073 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15074}
15075
15076/* Read the gphy configuration from the OTP region of the chip. The gphy
15077 * configuration is a 32-bit value that straddles the alignment boundary.
15078 * We do two 32-bit reads and then shift and merge the results.
15079 */
229b1ad1 15080static u32 tg3_read_otp_phycfg(struct tg3 *tp)
b2a5c19c
MC		 15081{
15082 u32 bhalf_otp, thalf_otp;
15083
15084 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15085
15086 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15087 return 0;
15088
15089 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15090
15091 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15092 return 0;
15093
15094 thalf_otp = tr32(OTP_READ_DATA);
15095
15096 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15097
15098 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15099 return 0;
15100
15101 bhalf_otp = tr32(OTP_READ_DATA);
15102
15103 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15104}
15105
229b1ad1 15106static void tg3_phy_init_link_config(struct tg3 *tp)
e256f8a3 15107{
202ff1c2 15108 u32 adv = ADVERTISED_Autoneg;
e256f8a3
MC		 15109
15110 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15111 adv |= ADVERTISED_1000baseT_Half |
15112 ADVERTISED_1000baseT_Full;
15113
15114 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15115 adv |= ADVERTISED_100baseT_Half |
15116 ADVERTISED_100baseT_Full |
15117 ADVERTISED_10baseT_Half |
15118 ADVERTISED_10baseT_Full |
15119 ADVERTISED_TP;
15120 else
15121 adv |= ADVERTISED_FIBRE;
15122
15123 tp->link_config.advertising = adv;
e740522e
MC		 15124 tp->link_config.speed = SPEED_UNKNOWN;
15125 tp->link_config.duplex = DUPLEX_UNKNOWN;
e256f8a3 15126 tp->link_config.autoneg = AUTONEG_ENABLE;
e740522e
MC		 15127 tp->link_config.active_speed = SPEED_UNKNOWN;
15128 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
34655ad6
MC		 15129
15130 tp->old_link = -1;
e256f8a3
MC		 15131}
15132
229b1ad1 15133static int tg3_phy_probe(struct tg3 *tp)
7d0c41ef
MC		 15134{
15135 u32 hw_phy_id_1, hw_phy_id_2;
15136 u32 hw_phy_id, hw_phy_id_masked;
15137 int err;
1da177e4 15138
e256f8a3 15139 /* flow control autonegotiation is default behavior */
63c3a66f 15140 tg3_flag_set(tp, PAUSE_AUTONEG);
e256f8a3
MC		 15141 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15142
8151ad57
MC		 15143 if (tg3_flag(tp, ENABLE_APE)) {
15144 switch (tp->pci_fn) {
15145 case 0:
15146 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15147 break;
15148 case 1:
15149 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15150 break;
15151 case 2:
15152 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15153 break;
15154 case 3:
15155 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15156 break;
15157 }
15158 }
15159
942d1af0
NS		 15160 if (!tg3_flag(tp, ENABLE_ASF) &&
15161 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15162 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15163 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15164 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15165
63c3a66f 15166 if (tg3_flag(tp, USE_PHYLIB))
b02fd9e3
MC		 15167 return tg3_phy_init(tp);
15168
1da177e4 15169 /* Reading the PHY ID register can conflict with ASF
877d0310 15170 * firmware access to the PHY hardware.
1da177e4
LT		 15171 */
15172 err = 0;
63c3a66f 15173 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
79eb6904 15174 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 15175 } else {
15176 /* Now read the physical PHY_ID from the chip and verify
15177 * that it is sane. If it doesn't look good, we fall back
15178 * to either the hard-coded table based PHY_ID and failing
15179 * that the value found in the eeprom area.
15180 */
15181 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15182 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15183
15184 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15185 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15186 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15187
79eb6904 15188 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 15189 }
15190
79eb6904 15191 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 15192 tp->phy_id = hw_phy_id;
79eb6904 15193 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
f07e9af3 15194 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
da6b2d01 15195 else
f07e9af3 15196 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
1da177e4 15197 } else {
79eb6904 15198 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 15199 /* Do nothing, phy ID already set up in
15200 * tg3_get_eeprom_hw_cfg().
15201 */
1da177e4
LT		 15202 } else {
15203 struct subsys_tbl_ent *p;
15204
15205 /* No eeprom signature? Try the hardcoded
15206 * subsys device table.
15207 */
24daf2b0 15208 p = tg3_lookup_by_subsys(tp);
7e6c63f0
HM		 15209 if (p) {
15210 tp->phy_id = p->phy_id;
15211 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15212 /* For now we saw the IDs 0xbc050cd0,
15213 * 0xbc050f80 and 0xbc050c30 on devices
15214 * connected to an BCM4785 and there are
15215 * probably more. Just assume that the phy is
15216 * supported when it is connected to a SSB core
15217 * for now.
15218 */
1da177e4 15219 return -ENODEV;
7e6c63f0 15220 }
1da177e4 15221
1da177e4 15222 if (!tp->phy_id ||
79eb6904 15223 tp->phy_id == TG3_PHY_ID_BCM8002)
f07e9af3 15224 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
1da177e4
LT		 15225 }
15226 }
15227
a6b68dab 15228 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
4153577a
JP		 15229 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15230 tg3_asic_rev(tp) == ASIC_REV_5720 ||
c4dab506 15231 tg3_asic_rev(tp) == ASIC_REV_57766 ||
4153577a
JP		 15232 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15233 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15234 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15235 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
9e2ecbeb 15236 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
52b02d04
MC		 15237 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15238
9e2ecbeb
NS		 15239 tp->eee.supported = SUPPORTED_100baseT_Full |
15240 SUPPORTED_1000baseT_Full;
15241 tp->eee.advertised = ADVERTISED_100baseT_Full |
15242 ADVERTISED_1000baseT_Full;
15243 tp->eee.eee_enabled = 1;
15244 tp->eee.tx_lpi_enabled = 1;
15245 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15246 }
15247
e256f8a3
MC		 15248 tg3_phy_init_link_config(tp);
15249
942d1af0
NS		 15250 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15251 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
63c3a66f
JP		 15252 !tg3_flag(tp, ENABLE_APE) &&
15253 !tg3_flag(tp, ENABLE_ASF)) {
e2bf73e7 15254 u32 bmsr, dummy;
1da177e4
LT		 15255
15256 tg3_readphy(tp, MII_BMSR, &bmsr);
15257 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15258 (bmsr & BMSR_LSTATUS))
15259 goto skip_phy_reset;
6aa20a22 15260
1da177e4
LT		 15261 err = tg3_phy_reset(tp);
15262 if (err)
15263 return err;
15264
42b64a45 15265 tg3_phy_set_wirespeed(tp);
1da177e4 15266
e2bf73e7 15267 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
42b64a45
MC		 15268 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15269 tp->link_config.flowctrl);
1da177e4
LT		 15270
15271 tg3_writephy(tp, MII_BMCR,
15272 BMCR_ANENABLE | BMCR_ANRESTART);
15273 }
1da177e4
LT		 15274 }
15275
15276skip_phy_reset:
79eb6904 15277 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 15278 err = tg3_init_5401phy_dsp(tp);
15279 if (err)
15280 return err;
1da177e4 15281
1da177e4
LT		 15282 err = tg3_init_5401phy_dsp(tp);
15283 }
15284
1da177e4
LT		 15285 return err;
15286}
15287
229b1ad1 15288static void tg3_read_vpd(struct tg3 *tp)
1da177e4 15289{
a4a8bb15 15290 u8 *vpd_data;
4181b2c8 15291 unsigned int block_end, rosize, len;
535a490e 15292 u32 vpdlen;
184b8904 15293 int j, i = 0;
a4a8bb15 15294
535a490e 15295 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
a4a8bb15
MC		 15296 if (!vpd_data)
15297 goto out_no_vpd;
1da177e4 15298
535a490e 15299 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
4181b2c8
MC		 15300 if (i < 0)
15301 goto out_not_found;
1da177e4 15302
4181b2c8
MC		 15303 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15304 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15305 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 15306
535a490e 15307 if (block_end > vpdlen)
4181b2c8 15308 goto out_not_found;
af2c6a4a 15309
184b8904
MC		 15310 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15311 PCI_VPD_RO_KEYWORD_MFR_ID);
15312 if (j > 0) {
15313 len = pci_vpd_info_field_size(&vpd_data[j]);
15314
15315 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15316 if (j + len > block_end || len != 4 ||
15317 memcmp(&vpd_data[j], "1028", 4))
15318 goto partno;
15319
15320 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15321 PCI_VPD_RO_KEYWORD_VENDOR0);
15322 if (j < 0)
15323 goto partno;
15324
15325 len = pci_vpd_info_field_size(&vpd_data[j]);
15326
15327 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15328 if (j + len > block_end)
15329 goto partno;
15330
715230a4
KC		 15331 if (len >= sizeof(tp->fw_ver))
15332 len = sizeof(tp->fw_ver) - 1;
15333 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15334 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15335 &vpd_data[j]);
184b8904
MC		 15336 }
15337
15338partno:
4181b2c8
MC		 15339 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15340 PCI_VPD_RO_KEYWORD_PARTNO);
15341 if (i < 0)
15342 goto out_not_found;
af2c6a4a 15343
4181b2c8 15344 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 15345
4181b2c8
MC		 15346 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15347 if (len > TG3_BPN_SIZE ||
535a490e 15348 (len + i) > vpdlen)
4181b2c8 15349 goto out_not_found;
1da177e4 15350
4181b2c8 15351 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 15352
1da177e4 15353out_not_found:
a4a8bb15 15354 kfree(vpd_data);
37a949c5 15355 if (tp->board_part_number[0])
a4a8bb15
MC		 15356 return;
15357
15358out_no_vpd:
4153577a 15359 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
79d49695
MC		 15360 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15361 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
37a949c5
MC		 15362 strcpy(tp->board_part_number, "BCM5717");
15363 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15364 strcpy(tp->board_part_number, "BCM5718");
15365 else
15366 goto nomatch;
4153577a 15367 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
37a949c5
MC		 15368 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15369 strcpy(tp->board_part_number, "BCM57780");
15370 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15371 strcpy(tp->board_part_number, "BCM57760");
15372 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15373 strcpy(tp->board_part_number, "BCM57790");
15374 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15375 strcpy(tp->board_part_number, "BCM57788");
15376 else
15377 goto nomatch;
4153577a 15378 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
37a949c5
MC		 15379 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15380 strcpy(tp->board_part_number, "BCM57761");
15381 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15382 strcpy(tp->board_part_number, "BCM57765");
15383 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15384 strcpy(tp->board_part_number, "BCM57781");
15385 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15386 strcpy(tp->board_part_number, "BCM57785");
15387 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15388 strcpy(tp->board_part_number, "BCM57791");
15389 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15390 strcpy(tp->board_part_number, "BCM57795");
15391 else
15392 goto nomatch;
4153577a 15393 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
55086ad9
MC		 15394 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15395 strcpy(tp->board_part_number, "BCM57762");
15396 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15397 strcpy(tp->board_part_number, "BCM57766");
15398 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15399 strcpy(tp->board_part_number, "BCM57782");
15400 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15401 strcpy(tp->board_part_number, "BCM57786");
15402 else
15403 goto nomatch;
4153577a 15404 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c 15405 strcpy(tp->board_part_number, "BCM95906");
37a949c5
MC		 15406 } else {
15407nomatch:
b5d3772c 15408 strcpy(tp->board_part_number, "none");
37a949c5 15409 }
1da177e4
LT		 15410}
15411
229b1ad1 15412static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
9c8a620e
MC		 15413{
15414 u32 val;
15415
e4f34110 15416 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 15417 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 15418 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 15419 val != 0)
15420 return 0;
15421
15422 return 1;
15423}
15424
229b1ad1 15425static void tg3_read_bc_ver(struct tg3 *tp)
acd9c119 15426{
ff3a7cb2 15427 u32 val, offset, start, ver_offset;
75f9936e 15428 int i, dst_off;
ff3a7cb2 15429 bool newver = false;
acd9c119
MC		 15430
15431 if (tg3_nvram_read(tp, 0xc, &offset) ||
15432 tg3_nvram_read(tp, 0x4, &start))
15433 return;
15434
15435 offset = tg3_nvram_logical_addr(tp, offset);
15436
ff3a7cb2 15437 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 15438 return;
15439
ff3a7cb2
MC		 15440 if ((val & 0xfc000000) == 0x0c000000) {
15441 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 15442 return;
15443
ff3a7cb2
MC		 15444 if (val == 0)
15445 newver = true;
15446 }
15447
75f9936e
MC		 15448 dst_off = strlen(tp->fw_ver);
15449
ff3a7cb2 15450 if (newver) {
75f9936e
MC		 15451 if (TG3_VER_SIZE - dst_off < 16 ||
15452 tg3_nvram_read(tp, offset + 8, &ver_offset))
ff3a7cb2
MC		 15453 return;
15454
15455 offset = offset + ver_offset - start;
15456 for (i = 0; i < 16; i += 4) {
15457 __be32 v;
15458 if (tg3_nvram_read_be32(tp, offset + i, &v))
15459 return;
15460
75f9936e 15461 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
ff3a7cb2
MC		 15462 }
15463 } else {
15464 u32 major, minor;
15465
15466 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15467 return;
15468
15469 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15470 TG3_NVM_BCVER_MAJSFT;
15471 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
75f9936e
MC		 15472 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15473 "v%d.%02d", major, minor);
acd9c119
MC		 15474 }
15475}
15476
229b1ad1 15477static void tg3_read_hwsb_ver(struct tg3 *tp)
a6f6cb1c
MC		 15478{
15479 u32 val, major, minor;
15480
15481 /* Use native endian representation */
15482 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15483 return;
15484
15485 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15486 TG3_NVM_HWSB_CFG1_MAJSFT;
15487 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15488 TG3_NVM_HWSB_CFG1_MINSFT;
15489
15490 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15491}
15492
229b1ad1 15493static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
dfe00d7d
MC		 15494{
15495 u32 offset, major, minor, build;
15496
75f9936e 15497 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
dfe00d7d
MC		 15498
15499 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15500 return;
15501
15502 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15503 case TG3_EEPROM_SB_REVISION_0:
15504 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15505 break;
15506 case TG3_EEPROM_SB_REVISION_2:
15507 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15508 break;
15509 case TG3_EEPROM_SB_REVISION_3:
15510 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15511 break;
a4153d40
MC		 15512 case TG3_EEPROM_SB_REVISION_4:
15513 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15514 break;
15515 case TG3_EEPROM_SB_REVISION_5:
15516 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15517 break;
bba226ac
MC		 15518 case TG3_EEPROM_SB_REVISION_6:
15519 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15520 break;
dfe00d7d
MC		 15521 default:
15522 return;
15523 }
15524
e4f34110 15525 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 15526 return;
15527
15528 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15529 TG3_EEPROM_SB_EDH_BLD_SHFT;
15530 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15531 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15532 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15533
15534 if (minor > 99 || build > 26)
15535 return;
15536
75f9936e
MC		 15537 offset = strlen(tp->fw_ver);
15538 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15539 " v%d.%02d", major, minor);
dfe00d7d
MC		 15540
15541 if (build > 0) {
75f9936e
MC		 15542 offset = strlen(tp->fw_ver);
15543 if (offset < TG3_VER_SIZE - 1)
15544 tp->fw_ver[offset] = 'a' + build - 1;
dfe00d7d
MC		 15545 }
15546}
15547
229b1ad1 15548static void tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 15549{
15550 u32 val, offset, start;
acd9c119 15551 int i, vlen;
9c8a620e
MC		 15552
15553 for (offset = TG3_NVM_DIR_START;
15554 offset < TG3_NVM_DIR_END;
15555 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 15556 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 15557 return;
15558
9c8a620e
MC		 15559 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15560 break;
15561 }
15562
15563 if (offset == TG3_NVM_DIR_END)
15564 return;
15565
63c3a66f 15566 if (!tg3_flag(tp, 5705_PLUS))
9c8a620e 15567 start = 0x08000000;
e4f34110 15568 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 15569 return;
15570
e4f34110 15571 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 15572 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 15573 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 15574 return;
15575
15576 offset += val - start;
15577
acd9c119 15578 vlen = strlen(tp->fw_ver);
9c8a620e 15579
acd9c119
MC		 15580 tp->fw_ver[vlen++] = ',';
15581 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 15582
15583 for (i = 0; i < 4; i++) {
a9dc529d
MC		 15584 __be32 v;
15585 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 15586 return;
15587
b9fc7dc5 15588 offset += sizeof(v);
c4e6575c 15589
acd9c119
MC		 15590 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15591 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 15592 break;
c4e6575c 15593 }
9c8a620e 15594
acd9c119
MC		 15595 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15596 vlen += sizeof(v);
c4e6575c 15597 }
acd9c119
MC		 15598}
15599
229b1ad1 15600static void tg3_probe_ncsi(struct tg3 *tp)
7fd76445 15601{
7fd76445 15602 u32 apedata;
7fd76445
MC		 15603
15604 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15605 if (apedata != APE_SEG_SIG_MAGIC)
15606 return;
15607
15608 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15609 if (!(apedata & APE_FW_STATUS_READY))
15610 return;
15611
165f4d1c
MC		 15612 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15613 tg3_flag_set(tp, APE_HAS_NCSI);
15614}
15615
229b1ad1 15616static void tg3_read_dash_ver(struct tg3 *tp)
165f4d1c
MC		 15617{
15618 int vlen;
15619 u32 apedata;
15620 char *fwtype;
15621
7fd76445
MC		 15622 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15623
165f4d1c 15624 if (tg3_flag(tp, APE_HAS_NCSI))
ecc79648 15625 fwtype = "NCSI";
c86a8560
MC		 15626 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15627 fwtype = "SMASH";
165f4d1c 15628 else
ecc79648
MC		 15629 fwtype = "DASH";
15630
7fd76445
MC		 15631 vlen = strlen(tp->fw_ver);
15632
ecc79648
MC		 15633 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15634 fwtype,
7fd76445
MC		 15635 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15636 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15637 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15638 (apedata & APE_FW_VERSION_BLDMSK));
15639}
15640
c86a8560
MC		 15641static void tg3_read_otp_ver(struct tg3 *tp)
15642{
15643 u32 val, val2;
15644
4153577a 15645 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c86a8560
MC		 15646 return;
15647
15648 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15649 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15650 TG3_OTP_MAGIC0_VALID(val)) {
15651 u64 val64 = (u64) val << 32 | val2;
15652 u32 ver = 0;
15653 int i, vlen;
15654
15655 for (i = 0; i < 7; i++) {
15656 if ((val64 & 0xff) == 0)
15657 break;
15658 ver = val64 & 0xff;
15659 val64 >>= 8;
15660 }
15661 vlen = strlen(tp->fw_ver);
15662 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15663 }
15664}
15665
229b1ad1 15666static void tg3_read_fw_ver(struct tg3 *tp)
acd9c119
MC		 15667{
15668 u32 val;
75f9936e 15669 bool vpd_vers = false;
acd9c119 15670
75f9936e
MC		 15671 if (tp->fw_ver[0] != 0)
15672 vpd_vers = true;
df259d8c 15673
63c3a66f 15674 if (tg3_flag(tp, NO_NVRAM)) {
75f9936e 15675 strcat(tp->fw_ver, "sb");
c86a8560 15676 tg3_read_otp_ver(tp);
df259d8c
MC		 15677 return;
15678 }
15679
acd9c119
MC		 15680 if (tg3_nvram_read(tp, 0, &val))
15681 return;
15682
15683 if (val == TG3_EEPROM_MAGIC)
15684 tg3_read_bc_ver(tp);
15685 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15686 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 15687 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15688 tg3_read_hwsb_ver(tp);
acd9c119 15689
165f4d1c
MC		 15690 if (tg3_flag(tp, ENABLE_ASF)) {
15691 if (tg3_flag(tp, ENABLE_APE)) {
15692 tg3_probe_ncsi(tp);
15693 if (!vpd_vers)
15694 tg3_read_dash_ver(tp);
15695 } else if (!vpd_vers) {
15696 tg3_read_mgmtfw_ver(tp);
15697 }
c9cab24e 15698 }
9c8a620e
MC		 15699
15700 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 15701}
15702
7cb32cf2
MC		 15703static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15704{
63c3a66f 15705 if (tg3_flag(tp, LRG_PROD_RING_CAP))
de9f5230 15706 return TG3_RX_RET_MAX_SIZE_5717;
63c3a66f 15707 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
de9f5230 15708 return TG3_RX_RET_MAX_SIZE_5700;
7cb32cf2 15709 else
de9f5230 15710 return TG3_RX_RET_MAX_SIZE_5705;
7cb32cf2
MC		 15711}
15712
4143470c 15713static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
895950c2
JP		 15714 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15715 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15716 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15717 { },
15718};
15719
229b1ad1 15720static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16c7fa7d
MC		 15721{
15722 struct pci_dev *peer;
15723 unsigned int func, devnr = tp->pdev->devfn & ~7;
15724
15725 for (func = 0; func < 8; func++) {
15726 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15727 if (peer && peer != tp->pdev)
15728 break;
15729 pci_dev_put(peer);
15730 }
15731 /* 5704 can be configured in single-port mode, set peer to
15732 * tp->pdev in that case.
15733 */
15734 if (!peer) {
15735 peer = tp->pdev;
15736 return peer;
15737 }
15738
15739 /*
15740 * We don't need to keep the refcount elevated; there's no way
15741 * to remove one half of this device without removing the other
15742 */
15743 pci_dev_put(peer);
15744
15745 return peer;
15746}
15747
229b1ad1 15748static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
42b123b1
MC		 15749{
15750 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
4153577a 15751 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
42b123b1
MC		 15752 u32 reg;
15753
15754 /* All devices that use the alternate
15755 * ASIC REV location have a CPMU.
15756 */
15757 tg3_flag_set(tp, CPMU_PRESENT);
15758
15759 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 15760 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
42b123b1
MC		 15761 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15762 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4
MC		 15763 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
15764 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
15765 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
15766 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727)
42b123b1
MC		 15767 reg = TG3PCI_GEN2_PRODID_ASICREV;
15768 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
15769 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
15770 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
15771 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
15772 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15773 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
15774 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
15775 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
15776 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
15777 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15778 reg = TG3PCI_GEN15_PRODID_ASICREV;
15779 else
15780 reg = TG3PCI_PRODID_ASICREV;
15781
15782 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
15783 }
15784
15785 /* Wrong chip ID in 5752 A0. This code can be removed later
15786 * as A0 is not in production.
15787 */
4153577a 15788 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
42b123b1
MC		 15789 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
15790
4153577a 15791 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
79d49695
MC		 15792 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
15793
4153577a
JP		 15794 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15795 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15796 tg3_asic_rev(tp) == ASIC_REV_5720)
42b123b1
MC		 15797 tg3_flag_set(tp, 5717_PLUS);
15798
4153577a
JP		 15799 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
15800 tg3_asic_rev(tp) == ASIC_REV_57766)
42b123b1
MC		 15801 tg3_flag_set(tp, 57765_CLASS);
15802
c65a17f4 15803 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
4153577a 15804 tg3_asic_rev(tp) == ASIC_REV_5762)
42b123b1
MC		 15805 tg3_flag_set(tp, 57765_PLUS);
15806
15807 /* Intentionally exclude ASIC_REV_5906 */
4153577a
JP		 15808 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
15809 tg3_asic_rev(tp) == ASIC_REV_5787 ||
15810 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15811 tg3_asic_rev(tp) == ASIC_REV_5761 ||
15812 tg3_asic_rev(tp) == ASIC_REV_5785 ||
15813 tg3_asic_rev(tp) == ASIC_REV_57780 ||
42b123b1
MC		 15814 tg3_flag(tp, 57765_PLUS))
15815 tg3_flag_set(tp, 5755_PLUS);
15816
4153577a
JP		 15817 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
15818 tg3_asic_rev(tp) == ASIC_REV_5714)
42b123b1
MC		 15819 tg3_flag_set(tp, 5780_CLASS);
15820
4153577a
JP		 15821 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
15822 tg3_asic_rev(tp) == ASIC_REV_5752 ||
15823 tg3_asic_rev(tp) == ASIC_REV_5906 ||
42b123b1
MC		 15824 tg3_flag(tp, 5755_PLUS) ||
15825 tg3_flag(tp, 5780_CLASS))
15826 tg3_flag_set(tp, 5750_PLUS);
15827
4153577a 15828 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
42b123b1
MC		 15829 tg3_flag(tp, 5750_PLUS))
15830 tg3_flag_set(tp, 5705_PLUS);
15831}
15832
3d567e0e
NNS		 15833static bool tg3_10_100_only_device(struct tg3 *tp,
15834 const struct pci_device_id *ent)
15835{
15836 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
15837
4153577a
JP		 15838 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
15839 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
3d567e0e
NNS		 15840 (tp->phy_flags & TG3_PHYFLG_IS_FET))
15841 return true;
15842
15843 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
4153577a 15844 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3d567e0e
NNS		 15845 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
15846 return true;
15847 } else {
15848 return true;
15849 }
15850 }
15851
15852 return false;
15853}
15854
1dd06ae8 15855static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
1da177e4 15856{
1da177e4 15857 u32 misc_ctrl_reg;
1da177e4
LT		 15858 u32 pci_state_reg, grc_misc_cfg;
15859 u32 val;
15860 u16 pci_cmd;
5e7dfd0f 15861 int err;
1da177e4 15862
1da177e4
LT		 15863 /* Force memory write invalidate off. If we leave it on,
15864 * then on 5700_BX chips we have to enable a workaround.
15865 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
15866 * to match the cacheline size. The Broadcom driver have this
15867 * workaround but turns MWI off all the times so never uses
15868 * it. This seems to suggest that the workaround is insufficient.
15869 */
15870 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
15871 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
15872 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
15873
16821285
MC		 15874 /* Important! -- Make sure register accesses are byteswapped
15875 * correctly. Also, for those chips that require it, make
15876 * sure that indirect register accesses are enabled before
15877 * the first operation.
1da177e4
LT		 15878 */
15879 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15880 &misc_ctrl_reg);
16821285
MC		 15881 tp->misc_host_ctrl |= (misc_ctrl_reg &
15882 MISC_HOST_CTRL_CHIPREV);
15883 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15884 tp->misc_host_ctrl);
1da177e4 15885
42b123b1 15886 tg3_detect_asic_rev(tp, misc_ctrl_reg);
ff645bec 15887
6892914f
MC		 15888 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
15889 * we need to disable memory and use config. cycles
15890 * only to access all registers. The 5702/03 chips
15891 * can mistakenly decode the special cycles from the
15892 * ICH chipsets as memory write cycles, causing corruption
15893 * of register and memory space. Only certain ICH bridges
15894 * will drive special cycles with non-zero data during the
15895 * address phase which can fall within the 5703's address
15896 * range. This is not an ICH bug as the PCI spec allows
15897 * non-zero address during special cycles. However, only
15898 * these ICH bridges are known to drive non-zero addresses
15899 * during special cycles.
15900 *
15901 * Since special cycles do not cross PCI bridges, we only
15902 * enable this workaround if the 5703 is on the secondary
15903 * bus of these ICH bridges.
15904 */
4153577a
JP		 15905 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
15906 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
6892914f
MC		 15907 static struct tg3_dev_id {
15908 u32 vendor;
15909 u32 device;
15910 u32 rev;
15911 } ich_chipsets[] = {
15912 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
15913 PCI_ANY_ID },
15914 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
15915 PCI_ANY_ID },
15916 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
15917 0xa },
15918 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
15919 PCI_ANY_ID },
15920 { },
15921 };
15922 struct tg3_dev_id *pci_id = &ich_chipsets[0];
15923 struct pci_dev *bridge = NULL;
15924
15925 while (pci_id->vendor != 0) {
15926 bridge = pci_get_device(pci_id->vendor, pci_id->device,
15927 bridge);
15928 if (!bridge) {
15929 pci_id++;
15930 continue;
15931 }
15932 if (pci_id->rev != PCI_ANY_ID) {
44c10138 15933 if (bridge->revision > pci_id->rev)
6892914f
MC		 15934 continue;
15935 }
15936 if (bridge->subordinate &&
15937 (bridge->subordinate->number ==
15938 tp->pdev->bus->number)) {
63c3a66f 15939 tg3_flag_set(tp, ICH_WORKAROUND);
6892914f
MC		 15940 pci_dev_put(bridge);
15941 break;
15942 }
15943 }
15944 }
15945
4153577a 15946 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
41588ba1
MC		 15947 static struct tg3_dev_id {
15948 u32 vendor;
15949 u32 device;
15950 } bridge_chipsets[] = {
15951 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
15952 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
15953 { },
15954 };
15955 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
15956 struct pci_dev *bridge = NULL;
15957
15958 while (pci_id->vendor != 0) {
15959 bridge = pci_get_device(pci_id->vendor,
15960 pci_id->device,
15961 bridge);
15962 if (!bridge) {
15963 pci_id++;
15964 continue;
15965 }
15966 if (bridge->subordinate &&
15967 (bridge->subordinate->number <=
15968 tp->pdev->bus->number) &&
b918c62e 15969 (bridge->subordinate->busn_res.end >=
41588ba1 15970 tp->pdev->bus->number)) {
63c3a66f 15971 tg3_flag_set(tp, 5701_DMA_BUG);
41588ba1
MC		 15972 pci_dev_put(bridge);
15973 break;
15974 }
15975 }
15976 }
15977
4a29cc2e
MC		 15978 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
15979 * DMA addresses > 40-bit. This bridge may have other additional
15980 * 57xx devices behind it in some 4-port NIC designs for example.
15981 * Any tg3 device found behind the bridge will also need the 40-bit
15982 * DMA workaround.
15983 */
42b123b1 15984 if (tg3_flag(tp, 5780_CLASS)) {
63c3a66f 15985 tg3_flag_set(tp, 40BIT_DMA_BUG);
0f847584 15986 tp->msi_cap = tp->pdev->msi_cap;
859a5887 15987 } else {
4a29cc2e
MC		 15988 struct pci_dev *bridge = NULL;
15989
15990 do {
15991 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
15992 PCI_DEVICE_ID_SERVERWORKS_EPB,
15993 bridge);
15994 if (bridge && bridge->subordinate &&
15995 (bridge->subordinate->number <=
15996 tp->pdev->bus->number) &&
b918c62e 15997 (bridge->subordinate->busn_res.end >=
4a29cc2e 15998 tp->pdev->bus->number)) {
63c3a66f 15999 tg3_flag_set(tp, 40BIT_DMA_BUG);
4a29cc2e
MC		 16000 pci_dev_put(bridge);
16001 break;
16002 }
16003 } while (bridge);
16004 }
4cf78e4f 16005
4153577a
JP		 16006 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16007 tg3_asic_rev(tp) == ASIC_REV_5714)
7544b097
MC		 16008 tp->pdev_peer = tg3_find_peer(tp);
16009
507399f1 16010 /* Determine TSO capabilities */
4153577a 16011 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
4d163b75 16012 ; /* Do nothing. HW bug. */
63c3a66f
JP		 16013 else if (tg3_flag(tp, 57765_PLUS))
16014 tg3_flag_set(tp, HW_TSO_3);
16015 else if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16016 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f
JP		 16017 tg3_flag_set(tp, HW_TSO_2);
16018 else if (tg3_flag(tp, 5750_PLUS)) {
16019 tg3_flag_set(tp, HW_TSO_1);
16020 tg3_flag_set(tp, TSO_BUG);
4153577a
JP		 16021 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16022 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
63c3a66f 16023 tg3_flag_clear(tp, TSO_BUG);
4153577a
JP		 16024 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16025 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16026 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
1caf13eb
MC		 16027 tg3_flag_set(tp, FW_TSO);
16028 tg3_flag_set(tp, TSO_BUG);
4153577a 16029 if (tg3_asic_rev(tp) == ASIC_REV_5705)
507399f1
MC		 16030 tp->fw_needed = FIRMWARE_TG3TSO5;
16031 else
16032 tp->fw_needed = FIRMWARE_TG3TSO;
16033 }
16034
dabc5c67 16035 /* Selectively allow TSO based on operating conditions */
6ff6f81d
MC		 16036 if (tg3_flag(tp, HW_TSO_1) ||
16037 tg3_flag(tp, HW_TSO_2) ||
16038 tg3_flag(tp, HW_TSO_3) ||
1caf13eb 16039 tg3_flag(tp, FW_TSO)) {
cf9ecf4b
MC		 16040 /* For firmware TSO, assume ASF is disabled.
16041 * We'll disable TSO later if we discover ASF
16042 * is enabled in tg3_get_eeprom_hw_cfg().
16043 */
dabc5c67 16044 tg3_flag_set(tp, TSO_CAPABLE);
cf9ecf4b 16045 } else {
dabc5c67
MC		 16046 tg3_flag_clear(tp, TSO_CAPABLE);
16047 tg3_flag_clear(tp, TSO_BUG);
16048 tp->fw_needed = NULL;
16049 }
16050
4153577a 16051 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
dabc5c67
MC		 16052 tp->fw_needed = FIRMWARE_TG3;
16053
c4dab506
NS		 16054 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16055 tp->fw_needed = FIRMWARE_TG357766;
16056
507399f1
MC		 16057 tp->irq_max = 1;
16058
63c3a66f
JP		 16059 if (tg3_flag(tp, 5750_PLUS)) {
16060 tg3_flag_set(tp, SUPPORT_MSI);
4153577a
JP		 16061 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16062 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16063 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16064 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
7544b097 16065 tp->pdev_peer == tp->pdev))
63c3a66f 16066 tg3_flag_clear(tp, SUPPORT_MSI);
7544b097 16067
63c3a66f 16068 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16069 tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16070 tg3_flag_set(tp, 1SHOT_MSI);
52c0fd83 16071 }
4f125f42 16072
63c3a66f
JP		 16073 if (tg3_flag(tp, 57765_PLUS)) {
16074 tg3_flag_set(tp, SUPPORT_MSIX);
507399f1
MC		 16075 tp->irq_max = TG3_IRQ_MAX_VECS;
16076 }
f6eb9b1f 16077 }
0e1406dd 16078
9102426a
MC		 16079 tp->txq_max = 1;
16080 tp->rxq_max = 1;
16081 if (tp->irq_max > 1) {
16082 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16083 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16084
4153577a
JP		 16085 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16086 tg3_asic_rev(tp) == ASIC_REV_5720)
9102426a
MC		 16087 tp->txq_max = tp->irq_max - 1;
16088 }
16089
b7abee6e 16090 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16091 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f 16092 tg3_flag_set(tp, SHORT_DMA_BUG);
f6eb9b1f 16093
4153577a 16094 if (tg3_asic_rev(tp) == ASIC_REV_5719)
a4cb428d 16095 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
e31aa987 16096
4153577a
JP		 16097 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16098 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16099 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16100 tg3_asic_rev(tp) == ASIC_REV_5762)
63c3a66f 16101 tg3_flag_set(tp, LRG_PROD_RING_CAP);
de9f5230 16102
63c3a66f 16103 if (tg3_flag(tp, 57765_PLUS) &&
4153577a 16104 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
63c3a66f 16105 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
b703df6f 16106
63c3a66f
JP		 16107 if (!tg3_flag(tp, 5705_PLUS) ||
16108 tg3_flag(tp, 5780_CLASS) ||
16109 tg3_flag(tp, USE_JUMBO_BDFLAG))
16110 tg3_flag_set(tp, JUMBO_CAPABLE);
0f893dc6 16111
52f4490c
MC		 16112 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16113 &pci_state_reg);
16114
708ebb3a 16115 if (pci_is_pcie(tp->pdev)) {
5e7dfd0f
MC		 16116 u16 lnkctl;
16117
63c3a66f 16118 tg3_flag_set(tp, PCI_EXPRESS);
5f5c51e3 16119
0f49bfbd 16120 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
5e7dfd0f 16121 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
4153577a 16122 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16123 tg3_flag_clear(tp, HW_TSO_2);
dabc5c67 16124 tg3_flag_clear(tp, TSO_CAPABLE);
7196cd6c 16125 }
4153577a
JP		 16126 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16127 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16128 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16129 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
63c3a66f 16130 tg3_flag_set(tp, CLKREQ_BUG);
4153577a 16131 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
63c3a66f 16132 tg3_flag_set(tp, L1PLLPD_EN);
c7835a77 16133 }
4153577a 16134 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
708ebb3a
JM		 16135 /* BCM5785 devices are effectively PCIe devices, and should
16136 * follow PCIe codepaths, but do not have a PCIe capabilities
16137 * section.
93a700a9 16138 */
63c3a66f
JP		 16139 tg3_flag_set(tp, PCI_EXPRESS);
16140 } else if (!tg3_flag(tp, 5705_PLUS) ||
16141 tg3_flag(tp, 5780_CLASS)) {
52f4490c
MC		 16142 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16143 if (!tp->pcix_cap) {
2445e461
MC		 16144 dev_err(&tp->pdev->dev,
16145 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 16146 return -EIO;
16147 }
16148
16149 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
63c3a66f 16150 tg3_flag_set(tp, PCIX_MODE);
52f4490c 16151 }
1da177e4 16152
399de50b
MC		 16153 /* If we have an AMD 762 or VIA K8T800 chipset, write
16154 * reordering to the mailbox registers done by the host
16155 * controller can cause major troubles. We read back from
16156 * every mailbox register write to force the writes to be
16157 * posted to the chip in order.
16158 */
4143470c 16159 if (pci_dev_present(tg3_write_reorder_chipsets) &&
63c3a66f
JP		 16160 !tg3_flag(tp, PCI_EXPRESS))
16161 tg3_flag_set(tp, MBOX_WRITE_REORDER);
399de50b 16162
69fc4053
MC		 16163 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16164 &tp->pci_cacheline_sz);
16165 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16166 &tp->pci_lat_timer);
4153577a 16167 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
1da177e4
LT		 16168 tp->pci_lat_timer < 64) {
16169 tp->pci_lat_timer = 64;
69fc4053
MC		 16170 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16171 tp->pci_lat_timer);
1da177e4
LT		 16172 }
16173
16821285
MC		 16174 /* Important! -- It is critical that the PCI-X hw workaround
16175 * situation is decided before the first MMIO register access.
16176 */
4153577a 16177 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
52f4490c
MC		 16178 /* 5700 BX chips need to have their TX producer index
16179 * mailboxes written twice to workaround a bug.
16180 */
63c3a66f 16181 tg3_flag_set(tp, TXD_MBOX_HWBUG);
1da177e4 16182
52f4490c 16183 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 16184 *
16185 * The workaround is to use indirect register accesses
16186 * for all chip writes not to mailbox registers.
16187 */
63c3a66f 16188 if (tg3_flag(tp, PCIX_MODE)) {
1da177e4 16189 u32 pm_reg;
1da177e4 16190
63c3a66f 16191 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16192
16193 /* The chip can have it's power management PCI config
16194 * space registers clobbered due to this bug.
16195 * So explicitly force the chip into D0 here.
16196 */
9974a356 16197 pci_read_config_dword(tp->pdev,
0319f30e 16198 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16199 &pm_reg);
16200 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16201 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356 16202 pci_write_config_dword(tp->pdev,
0319f30e 16203 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16204 pm_reg);
16205
16206 /* Also, force SERR#/PERR# in PCI command. */
16207 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16208 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16209 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16210 }
16211 }
16212
1da177e4 16213 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
63c3a66f 16214 tg3_flag_set(tp, PCI_HIGH_SPEED);
1da177e4 16215 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
63c3a66f 16216 tg3_flag_set(tp, PCI_32BIT);
1da177e4
LT		 16217
16218 /* Chip-specific fixup from Broadcom driver */
4153577a 16219 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
1da177e4
LT		 16220 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16221 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16222 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16223 }
16224
1ee582d8 16225 /* Default fast path register access methods */
20094930 16226 tp->read32 = tg3_read32;
1ee582d8 16227 tp->write32 = tg3_write32;
09ee929c 16228 tp->read32_mbox = tg3_read32;
20094930 16229 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 16230 tp->write32_tx_mbox = tg3_write32;
16231 tp->write32_rx_mbox = tg3_write32;
16232
16233 /* Various workaround register access methods */
63c3a66f 16234 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
1ee582d8 16235 tp->write32 = tg3_write_indirect_reg32;
4153577a 16236 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
63c3a66f 16237 (tg3_flag(tp, PCI_EXPRESS) &&
4153577a 16238 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
98efd8a6
MC		 16239 /*
16240 * Back to back register writes can cause problems on these
16241 * chips, the workaround is to read back all reg writes
16242 * except those to mailbox regs.
16243 *
16244 * See tg3_write_indirect_reg32().
16245 */
1ee582d8 16246 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 16247 }
16248
63c3a66f 16249 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
1ee582d8 16250 tp->write32_tx_mbox = tg3_write32_tx_mbox;
63c3a66f 16251 if (tg3_flag(tp, MBOX_WRITE_REORDER))
1ee582d8
MC		 16252 tp->write32_rx_mbox = tg3_write_flush_reg32;
16253 }
20094930 16254
63c3a66f 16255 if (tg3_flag(tp, ICH_WORKAROUND)) {
6892914f
MC		 16256 tp->read32 = tg3_read_indirect_reg32;
16257 tp->write32 = tg3_write_indirect_reg32;
16258 tp->read32_mbox = tg3_read_indirect_mbox;
16259 tp->write32_mbox = tg3_write_indirect_mbox;
16260 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16261 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16262
16263 iounmap(tp->regs);
22abe310 16264 tp->regs = NULL;
6892914f
MC		 16265
16266 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16267 pci_cmd &= ~PCI_COMMAND_MEMORY;
16268 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16269 }
4153577a 16270 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 16271 tp->read32_mbox = tg3_read32_mbox_5906;
16272 tp->write32_mbox = tg3_write32_mbox_5906;
16273 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16274 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16275 }
6892914f 16276
bbadf503 16277 if (tp->write32 == tg3_write_indirect_reg32 ||
63c3a66f 16278 (tg3_flag(tp, PCIX_MODE) &&
4153577a
JP		 16279 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16280 tg3_asic_rev(tp) == ASIC_REV_5701)))
63c3a66f 16281 tg3_flag_set(tp, SRAM_USE_CONFIG);
bbadf503 16282
16821285
MC		 16283 /* The memory arbiter has to be enabled in order for SRAM accesses
16284 * to succeed. Normally on powerup the tg3 chip firmware will make
16285 * sure it is enabled, but other entities such as system netboot
16286 * code might disable it.
16287 */
16288 val = tr32(MEMARB_MODE);
16289 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16290
9dc5e342 16291 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
4153577a 16292 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
9dc5e342
MC		 16293 tg3_flag(tp, 5780_CLASS)) {
16294 if (tg3_flag(tp, PCIX_MODE)) {
16295 pci_read_config_dword(tp->pdev,
16296 tp->pcix_cap + PCI_X_STATUS,
16297 &val);
16298 tp->pci_fn = val & 0x7;
16299 }
4153577a
JP		 16300 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16301 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16302 tg3_asic_rev(tp) == ASIC_REV_5720) {
9dc5e342 16303 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
857001f0
MC		 16304 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16305 val = tr32(TG3_CPMU_STATUS);
16306
4153577a 16307 if (tg3_asic_rev(tp) == ASIC_REV_5717)
857001f0
MC		 16308 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16309 else
9dc5e342
MC		 16310 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16311 TG3_CPMU_STATUS_FSHFT_5719;
69f11c99
MC		 16312 }
16313
7e6c63f0
HM		 16314 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16315 tp->write32_tx_mbox = tg3_write_flush_reg32;
16316 tp->write32_rx_mbox = tg3_write_flush_reg32;
16317 }
16318
7d0c41ef 16319 /* Get eeprom hw config before calling tg3_set_power_state().
63c3a66f 16320 * In particular, the TG3_FLAG_IS_NIC flag must be
7d0c41ef
MC		 16321 * determined before calling tg3_set_power_state() so that
16322 * we know whether or not to switch out of Vaux power.
16323 * When the flag is set, it means that GPIO1 is used for eeprom
16324 * write protect and also implies that it is a LOM where GPIOs
16325 * are not used to switch power.
6aa20a22 16326 */
7d0c41ef
MC		 16327 tg3_get_eeprom_hw_cfg(tp);
16328
1caf13eb 16329 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
cf9ecf4b
MC		 16330 tg3_flag_clear(tp, TSO_CAPABLE);
16331 tg3_flag_clear(tp, TSO_BUG);
16332 tp->fw_needed = NULL;
16333 }
16334
63c3a66f 16335 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 16336 /* Allow reads and writes to the
16337 * APE register and memory space.
16338 */
16339 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 16340 PCISTATE_ALLOW_APE_SHMEM_WR |
16341 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 16342 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16343 pci_state_reg);
c9cab24e
MC		 16344
16345 tg3_ape_lock_init(tp);
0d3031d9
MC		 16346 }
16347
16821285
MC		 16348 /* Set up tp->grc_local_ctrl before calling
16349 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16350 * will bring 5700's external PHY out of reset.
314fba34
MC		 16351 * It is also used as eeprom write protect on LOMs.
16352 */
16353 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
4153577a 16354 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
63c3a66f 16355 tg3_flag(tp, EEPROM_WRITE_PROT))
314fba34
MC		 16356 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16357 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 16358 /* Unused GPIO3 must be driven as output on 5752 because there
16359 * are no pull-up resistors on unused GPIO pins.
16360 */
4153577a 16361 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc 16362 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 16363
4153577a
JP		 16364 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16365 tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 16366 tg3_flag(tp, 57765_CLASS))
af36e6b6
MC		 16367 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16368
8d519ab2
MC		 16369 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16370 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 16371 /* Turn off the debug UART. */
16372 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
63c3a66f 16373 if (tg3_flag(tp, IS_NIC))
5f0c4a3c
MC		 16374 /* Keep VMain power. */
16375 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16376 GRC_LCLCTRL_GPIO_OUTPUT0;
16377 }
16378
4153577a 16379 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c86a8560
MC		 16380 tp->grc_local_ctrl |=
16381 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16382
16821285
MC		 16383 /* Switch out of Vaux if it is a NIC */
16384 tg3_pwrsrc_switch_to_vmain(tp);
1da177e4 16385
1da177e4
LT		 16386 /* Derive initial jumbo mode from MTU assigned in
16387 * ether_setup() via the alloc_etherdev() call
16388 */
63c3a66f
JP		 16389 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16390 tg3_flag_set(tp, JUMBO_RING_ENABLE);
1da177e4
LT		 16391
16392 /* Determine WakeOnLan speed to use. */
4153577a
JP		 16393 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16394 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16395 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16396 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
63c3a66f 16397 tg3_flag_clear(tp, WOL_SPEED_100MB);
1da177e4 16398 } else {
63c3a66f 16399 tg3_flag_set(tp, WOL_SPEED_100MB);
1da177e4
LT		 16400 }
16401
4153577a 16402 if (tg3_asic_rev(tp) == ASIC_REV_5906)
f07e9af3 16403 tp->phy_flags |= TG3_PHYFLG_IS_FET;
7f97a4bd 16404
1da177e4 16405 /* A few boards don't want Ethernet@WireSpeed phy feature */
4153577a
JP		 16406 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16407 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16408 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16409 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
f07e9af3
MC		 16410 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16411 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16412 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
1da177e4 16413
4153577a
JP		 16414 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16415 tg3_chip_rev(tp) == CHIPREV_5704_AX)
f07e9af3 16416 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
4153577a 16417 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
f07e9af3 16418 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
1da177e4 16419
63c3a66f 16420 if (tg3_flag(tp, 5705_PLUS) &&
f07e9af3 16421 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a
JP		 16422 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16423 tg3_asic_rev(tp) != ASIC_REV_57780 &&
63c3a66f 16424 !tg3_flag(tp, 57765_PLUS)) {
4153577a
JP		 16425 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16426 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16427 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16428 tg3_asic_rev(tp) == ASIC_REV_5761) {
d4011ada
MC		 16429 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16430 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
f07e9af3 16431 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
c1d2a196 16432 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
f07e9af3 16433 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
321d32a0 16434 } else
f07e9af3 16435 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
c424cb24 16436 }
1da177e4 16437
4153577a
JP		 16438 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16439 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 16440 tp->phy_otp = tg3_read_otp_phycfg(tp);
16441 if (tp->phy_otp == 0)
16442 tp->phy_otp = TG3_OTP_DEFAULT;
16443 }
16444
63c3a66f 16445 if (tg3_flag(tp, CPMU_PRESENT))
8ef21428
MC		 16446 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16447 else
16448 tp->mi_mode = MAC_MI_MODE_BASE;
16449
1da177e4 16450 tp->coalesce_mode = 0;
4153577a
JP		 16451 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16452 tg3_chip_rev(tp) != CHIPREV_5700_BX)
1da177e4
LT		 16453 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16454
4d958473 16455 /* Set these bits to enable statistics workaround. */
4153577a
JP		 16456 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16457 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16458 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
4d958473
MC		 16459 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16460 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16461 }
16462
4153577a
JP		 16463 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16464 tg3_asic_rev(tp) == ASIC_REV_57780)
63c3a66f 16465 tg3_flag_set(tp, USE_PHYLIB);
57e6983c 16466
158d7abd
MC		 16467 err = tg3_mdio_init(tp);
16468 if (err)
16469 return err;
1da177e4
LT		 16470
16471 /* Initialize data/descriptor byte/word swapping. */
16472 val = tr32(GRC_MODE);
4153577a
JP		 16473 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16474 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 16475 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16476 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16477 GRC_MODE_B2HRX_ENABLE |
16478 GRC_MODE_HTX2B_ENABLE |
16479 GRC_MODE_HOST_STACKUP);
16480 else
16481 val &= GRC_MODE_HOST_STACKUP;
16482
1da177e4
LT		 16483 tw32(GRC_MODE, val | tp->grc_mode);
16484
16485 tg3_switch_clocks(tp);
16486
16487 /* Clear this out for sanity. */
16488 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16489
16490 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16491 &pci_state_reg);
16492 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
63c3a66f 16493 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
4153577a
JP		 16494 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16495 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16496 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16497 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
1da177e4
LT		 16498 void __iomem *sram_base;
16499
16500 /* Write some dummy words into the SRAM status block
16501 * area, see if it reads back correctly. If the return
16502 * value is bad, force enable the PCIX workaround.
16503 */
16504 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16505
16506 writel(0x00000000, sram_base);
16507 writel(0x00000000, sram_base + 4);
16508 writel(0xffffffff, sram_base + 4);
16509 if (readl(sram_base) != 0x00000000)
63c3a66f 16510 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16511 }
16512 }
16513
16514 udelay(50);
16515 tg3_nvram_init(tp);
16516
c4dab506
NS		 16517 /* If the device has an NVRAM, no need to load patch firmware */
16518 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16519 !tg3_flag(tp, NO_NVRAM))
16520 tp->fw_needed = NULL;
16521
1da177e4
LT		 16522 grc_misc_cfg = tr32(GRC_MISC_CFG);
16523 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16524
4153577a 16525 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
1da177e4
LT		 16526 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16527 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
63c3a66f 16528 tg3_flag_set(tp, IS_5788);
1da177e4 16529
63c3a66f 16530 if (!tg3_flag(tp, IS_5788) &&
4153577a 16531 tg3_asic_rev(tp) != ASIC_REV_5700)
63c3a66f
JP		 16532 tg3_flag_set(tp, TAGGED_STATUS);
16533 if (tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 16534 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16535 HOSTCC_MODE_CLRTICK_TXBD);
16536
16537 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16538 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16539 tp->misc_host_ctrl);
16540 }
16541
3bda1258 16542 /* Preserve the APE MAC_MODE bits */
63c3a66f 16543 if (tg3_flag(tp, ENABLE_APE))
d2394e6b 16544 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
3bda1258 16545 else
6e01b20b 16546 tp->mac_mode = 0;
3bda1258 16547
3d567e0e 16548 if (tg3_10_100_only_device(tp, ent))
f07e9af3 16549 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
1da177e4
LT		 16550
16551 err = tg3_phy_probe(tp);
16552 if (err) {
2445e461 16553 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 16554 /* ... but do not return immediately ... */
b02fd9e3 16555 tg3_mdio_fini(tp);
1da177e4
LT		 16556 }
16557
184b8904 16558 tg3_read_vpd(tp);
c4e6575c 16559 tg3_read_fw_ver(tp);
1da177e4 16560
f07e9af3
MC		 16561 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16562 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16563 } else {
4153577a 16564 if (tg3_asic_rev(tp) == ASIC_REV_5700)
f07e9af3 16565 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16566 else
f07e9af3 16567 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4
LT		 16568 }
16569
16570 /* 5700 {AX,BX} chips have a broken status block link
16571 * change bit implementation, so we must use the
16572 * status register in those cases.
16573 */
4153577a 16574 if (tg3_asic_rev(tp) == ASIC_REV_5700)
63c3a66f 16575 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4 16576 else
63c3a66f 16577 tg3_flag_clear(tp, USE_LINKCHG_REG);
1da177e4
LT		 16578
16579 /* The led_ctrl is set during tg3_phy_probe, here we might
16580 * have to force the link status polling mechanism based
16581 * upon subsystem IDs.
16582 */
16583 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
4153577a 16584 tg3_asic_rev(tp) == ASIC_REV_5701 &&
f07e9af3
MC		 16585 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16586 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
63c3a66f 16587 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4
LT		 16588 }
16589
16590 /* For all SERDES we poll the MAC status register. */
f07e9af3 16591 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
63c3a66f 16592 tg3_flag_set(tp, POLL_SERDES);
1da177e4 16593 else
63c3a66f 16594 tg3_flag_clear(tp, POLL_SERDES);
1da177e4 16595
9205fd9c 16596 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
d2757fc4 16597 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
4153577a 16598 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
63c3a66f 16599 tg3_flag(tp, PCIX_MODE)) {
9205fd9c 16600 tp->rx_offset = NET_SKB_PAD;
d2757fc4 16601#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
9dc7a113 16602 tp->rx_copy_thresh = ~(u16)0;
d2757fc4
MC		 16603#endif
16604 }
1da177e4 16605
2c49a44d
MC		 16606 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16607 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
7cb32cf2
MC		 16608 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16609
2c49a44d 16610 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
f92905de
MC		 16611
16612 /* Increment the rx prod index on the rx std ring by at most
16613 * 8 for these chips to workaround hw errata.
16614 */
4153577a
JP		 16615 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16616 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16617 tg3_asic_rev(tp) == ASIC_REV_5755)
f92905de
MC		 16618 tp->rx_std_max_post = 8;
16619
63c3a66f 16620 if (tg3_flag(tp, ASPM_WORKAROUND))
8ed5d97e
MC		 16621 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16622 PCIE_PWR_MGMT_L1_THRESH_MSK;
16623
1da177e4
LT		 16624 return err;
16625}
16626
49b6e95f 16627#ifdef CONFIG_SPARC
229b1ad1 16628static int tg3_get_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16629{
16630 struct net_device *dev = tp->dev;
16631 struct pci_dev *pdev = tp->pdev;
49b6e95f 16632 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 16633 const unsigned char *addr;
49b6e95f
DM		 16634 int len;
16635
16636 addr = of_get_property(dp, "local-mac-address", &len);
16637 if (addr && len == 6) {
16638 memcpy(dev->dev_addr, addr, 6);
49b6e95f 16639 return 0;
1da177e4
LT		 16640 }
16641 return -ENODEV;
16642}
16643
229b1ad1 16644static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16645{
16646 struct net_device *dev = tp->dev;
16647
16648 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
16649 return 0;
16650}
16651#endif
16652
229b1ad1 16653static int tg3_get_device_address(struct tg3 *tp)
1da177e4
LT		 16654{
16655 struct net_device *dev = tp->dev;
16656 u32 hi, lo, mac_offset;
008652b3 16657 int addr_ok = 0;
7e6c63f0 16658 int err;
1da177e4 16659
49b6e95f 16660#ifdef CONFIG_SPARC
1da177e4
LT		 16661 if (!tg3_get_macaddr_sparc(tp))
16662 return 0;
16663#endif
16664
7e6c63f0
HM		 16665 if (tg3_flag(tp, IS_SSB_CORE)) {
16666 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16667 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16668 return 0;
16669 }
16670
1da177e4 16671 mac_offset = 0x7c;
4153577a 16672 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
63c3a66f 16673 tg3_flag(tp, 5780_CLASS)) {
1da177e4
LT		 16674 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16675 mac_offset = 0xcc;
16676 if (tg3_nvram_lock(tp))
16677 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16678 else
16679 tg3_nvram_unlock(tp);
63c3a66f 16680 } else if (tg3_flag(tp, 5717_PLUS)) {
69f11c99 16681 if (tp->pci_fn & 1)
a1b950d5 16682 mac_offset = 0xcc;
69f11c99 16683 if (tp->pci_fn > 1)
a50d0796 16684 mac_offset += 0x18c;
4153577a 16685 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 16686 mac_offset = 0x10;
1da177e4
LT		 16687
16688 /* First try to get it from MAC address mailbox. */
16689 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16690 if ((hi >> 16) == 0x484b) {
16691 dev->dev_addr[0] = (hi >> 8) & 0xff;
16692 dev->dev_addr[1] = (hi >> 0) & 0xff;
16693
16694 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16695 dev->dev_addr[2] = (lo >> 24) & 0xff;
16696 dev->dev_addr[3] = (lo >> 16) & 0xff;
16697 dev->dev_addr[4] = (lo >> 8) & 0xff;
16698 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 16699
008652b3
MC		 16700 /* Some old bootcode may report a 0 MAC address in SRAM */
16701 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16702 }
16703 if (!addr_ok) {
16704 /* Next, try NVRAM. */
63c3a66f 16705 if (!tg3_flag(tp, NO_NVRAM) &&
df259d8c 16706 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 16707 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 16708 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16709 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 16710 }
16711 /* Finally just fetch it out of the MAC control regs. */
16712 else {
16713 hi = tr32(MAC_ADDR_0_HIGH);
16714 lo = tr32(MAC_ADDR_0_LOW);
16715
16716 dev->dev_addr[5] = lo & 0xff;
16717 dev->dev_addr[4] = (lo >> 8) & 0xff;
16718 dev->dev_addr[3] = (lo >> 16) & 0xff;
16719 dev->dev_addr[2] = (lo >> 24) & 0xff;
16720 dev->dev_addr[1] = hi & 0xff;
16721 dev->dev_addr[0] = (hi >> 8) & 0xff;
16722 }
1da177e4
LT		 16723 }
16724
16725 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 16726#ifdef CONFIG_SPARC
1da177e4
LT		 16727 if (!tg3_get_default_macaddr_sparc(tp))
16728 return 0;
16729#endif
16730 return -EINVAL;
16731 }
16732 return 0;
16733}
16734
59e6b434
DM		 16735#define BOUNDARY_SINGLE_CACHELINE 1
16736#define BOUNDARY_MULTI_CACHELINE 2
16737
229b1ad1 16738static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
59e6b434
DM		 16739{
16740 int cacheline_size;
16741 u8 byte;
16742 int goal;
16743
16744 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
16745 if (byte == 0)
16746 cacheline_size = 1024;
16747 else
16748 cacheline_size = (int) byte * 4;
16749
16750 /* On 5703 and later chips, the boundary bits have no
16751 * effect.
16752 */
4153577a
JP		 16753 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16754 tg3_asic_rev(tp) != ASIC_REV_5701 &&
63c3a66f 16755 !tg3_flag(tp, PCI_EXPRESS))
59e6b434
DM		 16756 goto out;
16757
16758#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
16759 goal = BOUNDARY_MULTI_CACHELINE;
16760#else
16761#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
16762 goal = BOUNDARY_SINGLE_CACHELINE;
16763#else
16764 goal = 0;
16765#endif
16766#endif
16767
63c3a66f 16768 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 16769 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
16770 goto out;
16771 }
16772
59e6b434
DM		 16773 if (!goal)
16774 goto out;
16775
16776 /* PCI controllers on most RISC systems tend to disconnect
16777 * when a device tries to burst across a cache-line boundary.
16778 * Therefore, letting tg3 do so just wastes PCI bandwidth.
16779 *
16780 * Unfortunately, for PCI-E there are only limited
16781 * write-side controls for this, and thus for reads
16782 * we will still get the disconnects. We'll also waste
16783 * these PCI cycles for both read and write for chips
16784 * other than 5700 and 5701 which do not implement the
16785 * boundary bits.
16786 */
63c3a66f 16787 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16788 switch (cacheline_size) {
16789 case 16:
16790 case 32:
16791 case 64:
16792 case 128:
16793 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16794 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
16795 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
16796 } else {
16797 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16798 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16799 }
16800 break;
16801
16802 case 256:
16803 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
16804 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
16805 break;
16806
16807 default:
16808 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16809 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16810 break;
855e1111 16811 }
63c3a66f 16812 } else if (tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16813 switch (cacheline_size) {
16814 case 16:
16815 case 32:
16816 case 64:
16817 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16818 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16819 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
16820 break;
16821 }
16822 /* fallthrough */
16823 case 128:
16824 default:
16825 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16826 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
16827 break;
855e1111 16828 }
59e6b434
DM		 16829 } else {
16830 switch (cacheline_size) {
16831 case 16:
16832 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16833 val |= (DMA_RWCTRL_READ_BNDRY_16 |
16834 DMA_RWCTRL_WRITE_BNDRY_16);
16835 break;
16836 }
16837 /* fallthrough */
16838 case 32:
16839 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16840 val |= (DMA_RWCTRL_READ_BNDRY_32 |
16841 DMA_RWCTRL_WRITE_BNDRY_32);
16842 break;
16843 }
16844 /* fallthrough */
16845 case 64:
16846 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16847 val |= (DMA_RWCTRL_READ_BNDRY_64 |
16848 DMA_RWCTRL_WRITE_BNDRY_64);
16849 break;
16850 }
16851 /* fallthrough */
16852 case 128:
16853 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16854 val |= (DMA_RWCTRL_READ_BNDRY_128 |
16855 DMA_RWCTRL_WRITE_BNDRY_128);
16856 break;
16857 }
16858 /* fallthrough */
16859 case 256:
16860 val |= (DMA_RWCTRL_READ_BNDRY_256 |
16861 DMA_RWCTRL_WRITE_BNDRY_256);
16862 break;
16863 case 512:
16864 val |= (DMA_RWCTRL_READ_BNDRY_512 |
16865 DMA_RWCTRL_WRITE_BNDRY_512);
16866 break;
16867 case 1024:
16868 default:
16869 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
16870 DMA_RWCTRL_WRITE_BNDRY_1024);
16871 break;
855e1111 16872 }
59e6b434
DM		 16873 }
16874
16875out:
16876 return val;
16877}
16878
229b1ad1 16879static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
953c96e0 16880 int size, bool to_device)
1da177e4
LT		 16881{
16882 struct tg3_internal_buffer_desc test_desc;
16883 u32 sram_dma_descs;
16884 int i, ret;
16885
16886 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
16887
16888 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
16889 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
16890 tw32(RDMAC_STATUS, 0);
16891 tw32(WDMAC_STATUS, 0);
16892
16893 tw32(BUFMGR_MODE, 0);
16894 tw32(FTQ_RESET, 0);
16895
16896 test_desc.addr_hi = ((u64) buf_dma) >> 32;
16897 test_desc.addr_lo = buf_dma & 0xffffffff;
16898 test_desc.nic_mbuf = 0x00002100;
16899 test_desc.len = size;
16900
16901 /*
16902 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
16903 * the *second* time the tg3 driver was getting loaded after an
16904 * initial scan.
16905 *
16906 * Broadcom tells me:
16907 * ...the DMA engine is connected to the GRC block and a DMA
16908 * reset may affect the GRC block in some unpredictable way...
16909 * The behavior of resets to individual blocks has not been tested.
16910 *
16911 * Broadcom noted the GRC reset will also reset all sub-components.
16912 */
16913 if (to_device) {
16914 test_desc.cqid_sqid = (13 << 8) | 2;
16915
16916 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
16917 udelay(40);
16918 } else {
16919 test_desc.cqid_sqid = (16 << 8) | 7;
16920
16921 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
16922 udelay(40);
16923 }
16924 test_desc.flags = 0x00000005;
16925
16926 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
16927 u32 val;
16928
16929 val = *(((u32 *)&test_desc) + i);
16930 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
16931 sram_dma_descs + (i * sizeof(u32)));
16932 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
16933 }
16934 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
16935
859a5887 16936 if (to_device)
1da177e4 16937 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
859a5887 16938 else
1da177e4 16939 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
1da177e4
LT		 16940
16941 ret = -ENODEV;
16942 for (i = 0; i < 40; i++) {
16943 u32 val;
16944
16945 if (to_device)
16946 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
16947 else
16948 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
16949 if ((val & 0xffff) == sram_dma_descs) {
16950 ret = 0;
16951 break;
16952 }
16953
16954 udelay(100);
16955 }
16956
16957 return ret;
16958}
16959
ded7340d 16960#define TEST_BUFFER_SIZE 0x2000
1da177e4 16961
4143470c 16962static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
895950c2
JP		 16963 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
16964 { },
16965};
16966
229b1ad1 16967static int tg3_test_dma(struct tg3 *tp)
1da177e4
LT		 16968{
16969 dma_addr_t buf_dma;
59e6b434 16970 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 16971 int ret = 0;
1da177e4 16972
4bae65c8
MC		 16973 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
16974 &buf_dma, GFP_KERNEL);
1da177e4
LT		 16975 if (!buf) {
16976 ret = -ENOMEM;
16977 goto out_nofree;
16978 }
16979
16980 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
16981 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
16982
59e6b434 16983 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 16984
63c3a66f 16985 if (tg3_flag(tp, 57765_PLUS))
cbf9ca6c
MC		 16986 goto out;
16987
63c3a66f 16988 if (tg3_flag(tp, PCI_EXPRESS)) {
1da177e4
LT		 16989 /* DMA read watermark not used on PCIE */
16990 tp->dma_rwctrl |= 0x00180000;
63c3a66f 16991 } else if (!tg3_flag(tp, PCIX_MODE)) {
4153577a
JP		 16992 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
16993 tg3_asic_rev(tp) == ASIC_REV_5750)
1da177e4
LT		 16994 tp->dma_rwctrl |= 0x003f0000;
16995 else
16996 tp->dma_rwctrl |= 0x003f000f;
16997 } else {
4153577a
JP		 16998 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
16999 tg3_asic_rev(tp) == ASIC_REV_5704) {
1da177e4 17000 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 17001 u32 read_water = 0x7;
1da177e4 17002
4a29cc2e
MC		 17003 /* If the 5704 is behind the EPB bridge, we can
17004 * do the less restrictive ONE_DMA workaround for
17005 * better performance.
17006 */
63c3a66f 17007 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
4153577a 17008 tg3_asic_rev(tp) == ASIC_REV_5704)
4a29cc2e
MC		 17009 tp->dma_rwctrl |= 0x8000;
17010 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 17011 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17012
4153577a 17013 if (tg3_asic_rev(tp) == ASIC_REV_5703)
49afdeb6 17014 read_water = 4;
59e6b434 17015 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 17016 tp->dma_rwctrl |=
17017 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17018 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17019 (1 << 23);
4153577a 17020 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
4cf78e4f
MC		 17021 /* 5780 always in PCIX mode */
17022 tp->dma_rwctrl |= 0x00144000;
4153577a 17023 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
a4e2b347
MC		 17024 /* 5714 always in PCIX mode */
17025 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 17026 } else {
17027 tp->dma_rwctrl |= 0x001b000f;
17028 }
17029 }
7e6c63f0
HM		 17030 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17031 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
1da177e4 17032
4153577a
JP		 17033 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17034 tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 17035 tp->dma_rwctrl &= 0xfffffff0;
17036
4153577a
JP		 17037 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17038 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 17039 /* Remove this if it causes problems for some boards. */
17040 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17041
17042 /* On 5700/5701 chips, we need to set this bit.
17043 * Otherwise the chip will issue cacheline transactions
17044 * to streamable DMA memory with not all the byte
17045 * enables turned on. This is an error on several
17046 * RISC PCI controllers, in particular sparc64.
17047 *
17048 * On 5703/5704 chips, this bit has been reassigned
17049 * a different meaning. In particular, it is used
17050 * on those chips to enable a PCI-X workaround.
17051 */
17052 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17053 }
17054
17055 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17056
17057#if 0
17058 /* Unneeded, already done by tg3_get_invariants. */
17059 tg3_switch_clocks(tp);
17060#endif
17061
4153577a
JP		 17062 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17063 tg3_asic_rev(tp) != ASIC_REV_5701)
1da177e4
LT		 17064 goto out;
17065
59e6b434
DM		 17066 /* It is best to perform DMA test with maximum write burst size
17067 * to expose the 5700/5701 write DMA bug.
17068 */
17069 saved_dma_rwctrl = tp->dma_rwctrl;
17070 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17071 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17072
1da177e4
LT		 17073 while (1) {
17074 u32 *p = buf, i;
17075
17076 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17077 p[i] = i;
17078
17079 /* Send the buffer to the chip. */
953c96e0 17080 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
1da177e4 17081 if (ret) {
2445e461
MC		 17082 dev_err(&tp->pdev->dev,
17083 "%s: Buffer write failed. err = %d\n",
17084 __func__, ret);
1da177e4
LT		 17085 break;
17086 }
17087
17088#if 0
17089 /* validate data reached card RAM correctly. */
17090 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17091 u32 val;
17092 tg3_read_mem(tp, 0x2100 + (i*4), &val);
17093 if (le32_to_cpu(val) != p[i]) {
2445e461
MC		 17094 dev_err(&tp->pdev->dev,
17095 "%s: Buffer corrupted on device! "
17096 "(%d != %d)\n", __func__, val, i);
1da177e4
LT		 17097 /* ret = -ENODEV here? */
17098 }
17099 p[i] = 0;
17100 }
17101#endif
17102 /* Now read it back. */
953c96e0 17103 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
1da177e4 17104 if (ret) {
5129c3a3
MC		 17105 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17106 "err = %d\n", __func__, ret);
1da177e4
LT		 17107 break;
17108 }
17109
17110 /* Verify it. */
17111 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17112 if (p[i] == i)
17113 continue;
17114
59e6b434
DM		 17115 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17116 DMA_RWCTRL_WRITE_BNDRY_16) {
17117 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 17118 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17119 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17120 break;
17121 } else {
2445e461
MC		 17122 dev_err(&tp->pdev->dev,
17123 "%s: Buffer corrupted on read back! "
17124 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 17125 ret = -ENODEV;
17126 goto out;
17127 }
17128 }
17129
17130 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17131 /* Success. */
17132 ret = 0;
17133 break;
17134 }
17135 }
59e6b434
DM		 17136 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17137 DMA_RWCTRL_WRITE_BNDRY_16) {
17138 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 17139 * now look for chipsets that are known to expose the
17140 * DMA bug without failing the test.
59e6b434 17141 */
4143470c 17142 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
6d1cfbab
MC		 17143 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17144 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
859a5887 17145 } else {
6d1cfbab
MC		 17146 /* Safe to use the calculated DMA boundary. */
17147 tp->dma_rwctrl = saved_dma_rwctrl;
859a5887 17148 }
6d1cfbab 17149
59e6b434
DM		 17150 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17151 }
1da177e4
LT		 17152
17153out:
4bae65c8 17154 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
1da177e4
LT		 17155out_nofree:
17156 return ret;
17157}
17158
229b1ad1 17159static void tg3_init_bufmgr_config(struct tg3 *tp)
1da177e4 17160{
63c3a66f 17161 if (tg3_flag(tp, 57765_PLUS)) {
666bc831
MC		 17162 tp->bufmgr_config.mbuf_read_dma_low_water =
17163 DEFAULT_MB_RDMA_LOW_WATER_5705;
17164 tp->bufmgr_config.mbuf_mac_rx_low_water =
17165 DEFAULT_MB_MACRX_LOW_WATER_57765;
17166 tp->bufmgr_config.mbuf_high_water =
17167 DEFAULT_MB_HIGH_WATER_57765;
17168
17169 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17170 DEFAULT_MB_RDMA_LOW_WATER_5705;
17171 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17172 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17173 tp->bufmgr_config.mbuf_high_water_jumbo =
17174 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
63c3a66f 17175 } else if (tg3_flag(tp, 5705_PLUS)) {
fdfec172
MC		 17176 tp->bufmgr_config.mbuf_read_dma_low_water =
17177 DEFAULT_MB_RDMA_LOW_WATER_5705;
17178 tp->bufmgr_config.mbuf_mac_rx_low_water =
17179 DEFAULT_MB_MACRX_LOW_WATER_5705;
17180 tp->bufmgr_config.mbuf_high_water =
17181 DEFAULT_MB_HIGH_WATER_5705;
4153577a 17182 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 17183 tp->bufmgr_config.mbuf_mac_rx_low_water =
17184 DEFAULT_MB_MACRX_LOW_WATER_5906;
17185 tp->bufmgr_config.mbuf_high_water =
17186 DEFAULT_MB_HIGH_WATER_5906;
17187 }
fdfec172
MC		 17188
17189 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17190 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17191 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17192 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17193 tp->bufmgr_config.mbuf_high_water_jumbo =
17194 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17195 } else {
17196 tp->bufmgr_config.mbuf_read_dma_low_water =
17197 DEFAULT_MB_RDMA_LOW_WATER;
17198 tp->bufmgr_config.mbuf_mac_rx_low_water =
17199 DEFAULT_MB_MACRX_LOW_WATER;
17200 tp->bufmgr_config.mbuf_high_water =
17201 DEFAULT_MB_HIGH_WATER;
17202
17203 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17204 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17205 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17206 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17207 tp->bufmgr_config.mbuf_high_water_jumbo =
17208 DEFAULT_MB_HIGH_WATER_JUMBO;
17209 }
1da177e4
LT		 17210
17211 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17212 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17213}
17214
229b1ad1 17215static char *tg3_phy_string(struct tg3 *tp)
1da177e4 17216{
79eb6904
MC		 17217 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17218 case TG3_PHY_ID_BCM5400: return "5400";
17219 case TG3_PHY_ID_BCM5401: return "5401";
17220 case TG3_PHY_ID_BCM5411: return "5411";
17221 case TG3_PHY_ID_BCM5701: return "5701";
17222 case TG3_PHY_ID_BCM5703: return "5703";
17223 case TG3_PHY_ID_BCM5704: return "5704";
17224 case TG3_PHY_ID_BCM5705: return "5705";
17225 case TG3_PHY_ID_BCM5750: return "5750";
17226 case TG3_PHY_ID_BCM5752: return "5752";
17227 case TG3_PHY_ID_BCM5714: return "5714";
17228 case TG3_PHY_ID_BCM5780: return "5780";
17229 case TG3_PHY_ID_BCM5755: return "5755";
17230 case TG3_PHY_ID_BCM5787: return "5787";
17231 case TG3_PHY_ID_BCM5784: return "5784";
17232 case TG3_PHY_ID_BCM5756: return "5722/5756";
17233 case TG3_PHY_ID_BCM5906: return "5906";
17234 case TG3_PHY_ID_BCM5761: return "5761";
17235 case TG3_PHY_ID_BCM5718C: return "5718C";
17236 case TG3_PHY_ID_BCM5718S: return "5718S";
17237 case TG3_PHY_ID_BCM57765: return "57765";
302b500b 17238 case TG3_PHY_ID_BCM5719C: return "5719C";
6418f2c1 17239 case TG3_PHY_ID_BCM5720C: return "5720C";
c65a17f4 17240 case TG3_PHY_ID_BCM5762: return "5762C";
79eb6904 17241 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 17242 case 0: return "serdes";
17243 default: return "unknown";
855e1111 17244 }
1da177e4
LT		 17245}
17246
229b1ad1 17247static char *tg3_bus_string(struct tg3 *tp, char *str)
f9804ddb 17248{
63c3a66f 17249 if (tg3_flag(tp, PCI_EXPRESS)) {
f9804ddb
MC		 17250 strcpy(str, "PCI Express");
17251 return str;
63c3a66f 17252 } else if (tg3_flag(tp, PCIX_MODE)) {
f9804ddb
MC		 17253 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17254
17255 strcpy(str, "PCIX:");
17256
17257 if ((clock_ctrl == 7) ||
17258 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17259 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17260 strcat(str, "133MHz");
17261 else if (clock_ctrl == 0)
17262 strcat(str, "33MHz");
17263 else if (clock_ctrl == 2)
17264 strcat(str, "50MHz");
17265 else if (clock_ctrl == 4)
17266 strcat(str, "66MHz");
17267 else if (clock_ctrl == 6)
17268 strcat(str, "100MHz");
f9804ddb
MC		 17269 } else {
17270 strcpy(str, "PCI:");
63c3a66f 17271 if (tg3_flag(tp, PCI_HIGH_SPEED))
f9804ddb
MC		 17272 strcat(str, "66MHz");
17273 else
17274 strcat(str, "33MHz");
17275 }
63c3a66f 17276 if (tg3_flag(tp, PCI_32BIT))
f9804ddb
MC		 17277 strcat(str, ":32-bit");
17278 else
17279 strcat(str, ":64-bit");
17280 return str;
17281}
17282
229b1ad1 17283static void tg3_init_coal(struct tg3 *tp)
15f9850d
DM		 17284{
17285 struct ethtool_coalesce *ec = &tp->coal;
17286
17287 memset(ec, 0, sizeof(*ec));
17288 ec->cmd = ETHTOOL_GCOALESCE;
17289 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17290 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17291 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17292 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17293 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17294 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17295 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17296 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17297 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17298
17299 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17300 HOSTCC_MODE_CLRTICK_TXBD)) {
17301 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17302 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17303 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17304 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17305 }
d244c892 17306
63c3a66f 17307 if (tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 17308 ec->rx_coalesce_usecs_irq = 0;
17309 ec->tx_coalesce_usecs_irq = 0;
17310 ec->stats_block_coalesce_usecs = 0;
17311 }
15f9850d
DM		 17312}
17313
229b1ad1 17314static int tg3_init_one(struct pci_dev *pdev,
1da177e4
LT		 17315 const struct pci_device_id *ent)
17316{
1da177e4
LT		 17317 struct net_device *dev;
17318 struct tg3 *tp;
5865fc1b 17319 int i, err;
646c9edd 17320 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 17321 char str[40];
72f2afb8 17322 u64 dma_mask, persist_dma_mask;
c8f44aff 17323 netdev_features_t features = 0;
1da177e4 17324
05dbe005 17325 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 17326
17327 err = pci_enable_device(pdev);
17328 if (err) {
2445e461 17329 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 17330 return err;
17331 }
17332
1da177e4
LT		 17333 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17334 if (err) {
2445e461 17335 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 17336 goto err_out_disable_pdev;
17337 }
17338
17339 pci_set_master(pdev);
17340
fe5f5787 17341 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 17342 if (!dev) {
1da177e4 17343 err = -ENOMEM;
5865fc1b 17344 goto err_out_free_res;
1da177e4
LT		 17345 }
17346
1da177e4
LT		 17347 SET_NETDEV_DEV(dev, &pdev->dev);
17348
1da177e4
LT		 17349 tp = netdev_priv(dev);
17350 tp->pdev = pdev;
17351 tp->dev = dev;
1da177e4
LT		 17352 tp->rx_mode = TG3_DEF_RX_MODE;
17353 tp->tx_mode = TG3_DEF_TX_MODE;
9c13cb8b 17354 tp->irq_sync = 1;
8ef21428 17355
1da177e4
LT		 17356 if (tg3_debug > 0)
17357 tp->msg_enable = tg3_debug;
17358 else
17359 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17360
7e6c63f0
HM		 17361 if (pdev_is_ssb_gige_core(pdev)) {
17362 tg3_flag_set(tp, IS_SSB_CORE);
17363 if (ssb_gige_must_flush_posted_writes(pdev))
17364 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17365 if (ssb_gige_one_dma_at_once(pdev))
17366 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17367 if (ssb_gige_have_roboswitch(pdev))
17368 tg3_flag_set(tp, ROBOSWITCH);
17369 if (ssb_gige_is_rgmii(pdev))
17370 tg3_flag_set(tp, RGMII_MODE);
17371 }
17372
1da177e4
LT		 17373 /* The word/byte swap controls here control register access byte
17374 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17375 * setting below.
17376 */
17377 tp->misc_host_ctrl =
17378 MISC_HOST_CTRL_MASK_PCI_INT |
17379 MISC_HOST_CTRL_WORD_SWAP |
17380 MISC_HOST_CTRL_INDIR_ACCESS |
17381 MISC_HOST_CTRL_PCISTATE_RW;
17382
17383 /* The NONFRM (non-frame) byte/word swap controls take effect
17384 * on descriptor entries, anything which isn't packet data.
17385 *
17386 * The StrongARM chips on the board (one for tx, one for rx)
17387 * are running in big-endian mode.
17388 */
17389 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17390 GRC_MODE_WSWAP_NONFRM_DATA);
17391#ifdef __BIG_ENDIAN
17392 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17393#endif
17394 spin_lock_init(&tp->lock);
1da177e4 17395 spin_lock_init(&tp->indirect_lock);
c4028958 17396 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 17397
d5fe488a 17398 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 17399 if (!tp->regs) {
ab96b241 17400 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 17401 err = -ENOMEM;
17402 goto err_out_free_dev;
17403 }
17404
c9cab24e
MC		 17405 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17406 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17407 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17408 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17409 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 17410 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
c9cab24e
MC		 17411 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17412 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4
MC		 17413 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17414 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17415 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17416 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727) {
c9cab24e
MC		 17417 tg3_flag_set(tp, ENABLE_APE);
17418 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17419 if (!tp->aperegs) {
17420 dev_err(&pdev->dev,
17421 "Cannot map APE registers, aborting\n");
17422 err = -ENOMEM;
17423 goto err_out_iounmap;
17424 }
17425 }
17426
1da177e4
LT		 17427 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17428 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 17429
1da177e4 17430 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 17431 dev->watchdog_timeo = TG3_TX_TIMEOUT;
2ffcc981 17432 dev->netdev_ops = &tg3_netdev_ops;
1da177e4 17433 dev->irq = pdev->irq;
1da177e4 17434
3d567e0e 17435 err = tg3_get_invariants(tp, ent);
1da177e4 17436 if (err) {
ab96b241
MC		 17437 dev_err(&pdev->dev,
17438 "Problem fetching invariants of chip, aborting\n");
c9cab24e 17439 goto err_out_apeunmap;
1da177e4
LT		 17440 }
17441
4a29cc2e
MC		 17442 /* The EPB bridge inside 5714, 5715, and 5780 and any
17443 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 17444 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17445 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17446 * do DMA address check in tg3_start_xmit().
17447 */
63c3a66f 17448 if (tg3_flag(tp, IS_5788))
284901a9 17449 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
63c3a66f 17450 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
50cf156a 17451 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 17452#ifdef CONFIG_HIGHMEM
6a35528a 17453 dma_mask = DMA_BIT_MASK(64);
72f2afb8 17454#endif
4a29cc2e 17455 } else
6a35528a 17456 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 17457
17458 /* Configure DMA attributes. */
284901a9 17459 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 17460 err = pci_set_dma_mask(pdev, dma_mask);
17461 if (!err) {
0da0606f 17462 features |= NETIF_F_HIGHDMA;
72f2afb8
MC		 17463 err = pci_set_consistent_dma_mask(pdev,
17464 persist_dma_mask);
17465 if (err < 0) {
ab96b241
MC		 17466 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17467 "DMA for consistent allocations\n");
c9cab24e 17468 goto err_out_apeunmap;
72f2afb8
MC		 17469 }
17470 }
17471 }
284901a9
YH		 17472 if (err || dma_mask == DMA_BIT_MASK(32)) {
17473 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 17474 if (err) {
ab96b241
MC		 17475 dev_err(&pdev->dev,
17476 "No usable DMA configuration, aborting\n");
c9cab24e 17477 goto err_out_apeunmap;
72f2afb8
MC		 17478 }
17479 }
17480
fdfec172 17481 tg3_init_bufmgr_config(tp);
1da177e4 17482
f646968f 17483 features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
0da0606f
MC		 17484
17485 /* 5700 B0 chips do not support checksumming correctly due
17486 * to hardware bugs.
17487 */
4153577a 17488 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
0da0606f
MC		 17489 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17490
17491 if (tg3_flag(tp, 5755_PLUS))
17492 features |= NETIF_F_IPV6_CSUM;
17493 }
17494
4e3a7aaa
MC		 17495 /* TSO is on by default on chips that support hardware TSO.
17496 * Firmware TSO on older chips gives lower performance, so it
17497 * is off by default, but can be enabled using ethtool.
17498 */
63c3a66f
JP		 17499 if ((tg3_flag(tp, HW_TSO_1) ||
17500 tg3_flag(tp, HW_TSO_2) ||
17501 tg3_flag(tp, HW_TSO_3)) &&
0da0606f
MC		 17502 (features & NETIF_F_IP_CSUM))
17503 features |= NETIF_F_TSO;
63c3a66f 17504 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
0da0606f
MC		 17505 if (features & NETIF_F_IPV6_CSUM)
17506 features |= NETIF_F_TSO6;
63c3a66f 17507 if (tg3_flag(tp, HW_TSO_3) ||
4153577a
JP		 17508 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17509 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17510 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17511 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17512 tg3_asic_rev(tp) == ASIC_REV_57780)
0da0606f 17513 features |= NETIF_F_TSO_ECN;
b0026624 17514 }
1da177e4 17515
d542fe27
MC		 17516 dev->features |= features;
17517 dev->vlan_features |= features;
17518
06c03c02
MB		 17519 /*
17520 * Add loopback capability only for a subset of devices that support
17521 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17522 * loopback for the remaining devices.
17523 */
4153577a 17524 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
06c03c02
MB		 17525 !tg3_flag(tp, CPMU_PRESENT))
17526 /* Add the loopback capability */
0da0606f
MC		 17527 features |= NETIF_F_LOOPBACK;
17528
0da0606f 17529 dev->hw_features |= features;
06c03c02 17530
4153577a 17531 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
63c3a66f 17532 !tg3_flag(tp, TSO_CAPABLE) &&
1da177e4 17533 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
63c3a66f 17534 tg3_flag_set(tp, MAX_RXPEND_64);
1da177e4
LT		 17535 tp->rx_pending = 63;
17536 }
17537
1da177e4
LT		 17538 err = tg3_get_device_address(tp);
17539 if (err) {
ab96b241
MC		 17540 dev_err(&pdev->dev,
17541 "Could not obtain valid ethernet address, aborting\n");
c9cab24e 17542 goto err_out_apeunmap;
c88864df
MC		 17543 }
17544
1da177e4
LT		 17545 /*
17546 * Reset chip in case UNDI or EFI driver did not shutdown
17547 * DMA self test will enable WDMAC and we'll see (spurious)
17548 * pending DMA on the PCI bus at that point.
17549 */
17550 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17551 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 17552 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 17553 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 17554 }
17555
17556 err = tg3_test_dma(tp);
17557 if (err) {
ab96b241 17558 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
c88864df 17559 goto err_out_apeunmap;
1da177e4
LT		 17560 }
17561
78f90dcf
MC		 17562 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17563 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17564 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6fd45cb8 17565 for (i = 0; i < tp->irq_max; i++) {
78f90dcf
MC		 17566 struct tg3_napi *tnapi = &tp->napi[i];
17567
17568 tnapi->tp = tp;
17569 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17570
17571 tnapi->int_mbox = intmbx;
93a700a9 17572 if (i <= 4)
78f90dcf
MC		 17573 intmbx += 0x8;
17574 else
17575 intmbx += 0x4;
17576
17577 tnapi->consmbox = rcvmbx;
17578 tnapi->prodmbox = sndmbx;
17579
66cfd1bd 17580 if (i)
78f90dcf 17581 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
66cfd1bd 17582 else
78f90dcf 17583 tnapi->coal_now = HOSTCC_MODE_NOW;
78f90dcf 17584
63c3a66f 17585 if (!tg3_flag(tp, SUPPORT_MSIX))
78f90dcf
MC		 17586 break;
17587
17588 /*
17589 * If we support MSIX, we'll be using RSS. If we're using
17590 * RSS, the first vector only handles link interrupts and the
17591 * remaining vectors handle rx and tx interrupts. Reuse the
17592 * mailbox values for the next iteration. The values we setup
17593 * above are still useful for the single vectored mode.
17594 */
17595 if (!i)
17596 continue;
17597
17598 rcvmbx += 0x8;
17599
17600 if (sndmbx & 0x4)
17601 sndmbx -= 0x4;
17602 else
17603 sndmbx += 0xc;
17604 }
17605
15f9850d
DM		 17606 tg3_init_coal(tp);
17607
c49a1561
MC		 17608 pci_set_drvdata(pdev, dev);
17609
4153577a
JP		 17610 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17611 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17612 tg3_asic_rev(tp) == ASIC_REV_5762)
fb4ce8ad
MC		 17613 tg3_flag_set(tp, PTP_CAPABLE);
17614
21f7638e
MC		 17615 tg3_timer_init(tp);
17616
402e1398
MC		 17617 tg3_carrier_off(tp);
17618
1da177e4
LT		 17619 err = register_netdev(dev);
17620 if (err) {
ab96b241 17621 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 17622 goto err_out_apeunmap;
1da177e4
LT		 17623 }
17624
05dbe005
JP		 17625 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17626 tp->board_part_number,
4153577a 17627 tg3_chip_rev_id(tp),
05dbe005
JP		 17628 tg3_bus_string(tp, str),
17629 dev->dev_addr);
1da177e4 17630
f07e9af3 17631 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7
MC		 17632 struct phy_device *phydev;
17633 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
5129c3a3
MC		 17634 netdev_info(dev,
17635 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
05dbe005 17636 phydev->drv->name, dev_name(&phydev->dev));
f07e9af3
MC		 17637 } else {
17638 char *ethtype;
17639
17640 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17641 ethtype = "10/100Base-TX";
17642 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17643 ethtype = "1000Base-SX";
17644 else
17645 ethtype = "10/100/1000Base-T";
17646
5129c3a3 17647 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
47007831
MC		 17648 "(WireSpeed[%d], EEE[%d])\n",
17649 tg3_phy_string(tp), ethtype,
17650 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17651 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
f07e9af3 17652 }
05dbe005
JP		 17653
17654 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
dc668910 17655 (dev->features & NETIF_F_RXCSUM) != 0,
63c3a66f 17656 tg3_flag(tp, USE_LINKCHG_REG) != 0,
f07e9af3 17657 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
63c3a66f
JP		 17658 tg3_flag(tp, ENABLE_ASF) != 0,
17659 tg3_flag(tp, TSO_CAPABLE) != 0);
05dbe005
JP		 17660 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17661 tp->dma_rwctrl,
17662 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17663 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4 17664
b45aa2f6
MC		 17665 pci_save_state(pdev);
17666
1da177e4
LT		 17667 return 0;
17668
0d3031d9
MC		 17669err_out_apeunmap:
17670 if (tp->aperegs) {
17671 iounmap(tp->aperegs);
17672 tp->aperegs = NULL;
17673 }
17674
1da177e4 17675err_out_iounmap:
6892914f
MC		 17676 if (tp->regs) {
17677 iounmap(tp->regs);
22abe310 17678 tp->regs = NULL;
6892914f 17679 }
1da177e4
LT		 17680
17681err_out_free_dev:
17682 free_netdev(dev);
17683
17684err_out_free_res:
17685 pci_release_regions(pdev);
17686
17687err_out_disable_pdev:
c80dc13d
GS		 17688 if (pci_is_enabled(pdev))
17689 pci_disable_device(pdev);
1da177e4
LT		 17690 pci_set_drvdata(pdev, NULL);
17691 return err;
17692}
17693
229b1ad1 17694static void tg3_remove_one(struct pci_dev *pdev)
1da177e4
LT		 17695{
17696 struct net_device *dev = pci_get_drvdata(pdev);
17697
17698 if (dev) {
17699 struct tg3 *tp = netdev_priv(dev);
17700
e3c5530b 17701 release_firmware(tp->fw);
077f849d 17702
db219973 17703 tg3_reset_task_cancel(tp);
158d7abd 17704
e730c823 17705 if (tg3_flag(tp, USE_PHYLIB)) {
b02fd9e3 17706 tg3_phy_fini(tp);
158d7abd 17707 tg3_mdio_fini(tp);
b02fd9e3 17708 }
158d7abd 17709
1da177e4 17710 unregister_netdev(dev);
0d3031d9
MC		 17711 if (tp->aperegs) {
17712 iounmap(tp->aperegs);
17713 tp->aperegs = NULL;
17714 }
6892914f
MC		 17715 if (tp->regs) {
17716 iounmap(tp->regs);
22abe310 17717 tp->regs = NULL;
6892914f 17718 }
1da177e4
LT		 17719 free_netdev(dev);
17720 pci_release_regions(pdev);
17721 pci_disable_device(pdev);
17722 pci_set_drvdata(pdev, NULL);
17723 }
17724}
17725
aa6027ca 17726#ifdef CONFIG_PM_SLEEP
c866b7ea 17727static int tg3_suspend(struct device *device)
1da177e4 17728{
c866b7ea 17729 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17730 struct net_device *dev = pci_get_drvdata(pdev);
17731 struct tg3 *tp = netdev_priv(dev);
17732 int err;
17733
17734 if (!netif_running(dev))
17735 return 0;
17736
db219973 17737 tg3_reset_task_cancel(tp);
b02fd9e3 17738 tg3_phy_stop(tp);
1da177e4
LT		 17739 tg3_netif_stop(tp);
17740
21f7638e 17741 tg3_timer_stop(tp);
1da177e4 17742
f47c11ee 17743 tg3_full_lock(tp, 1);
1da177e4 17744 tg3_disable_ints(tp);
f47c11ee 17745 tg3_full_unlock(tp);
1da177e4
LT		 17746
17747 netif_device_detach(dev);
17748
f47c11ee 17749 tg3_full_lock(tp, 0);
944d980e 17750 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
63c3a66f 17751 tg3_flag_clear(tp, INIT_COMPLETE);
f47c11ee 17752 tg3_full_unlock(tp);
1da177e4 17753
c866b7ea 17754 err = tg3_power_down_prepare(tp);
1da177e4 17755 if (err) {
b02fd9e3
MC		 17756 int err2;
17757
f47c11ee 17758 tg3_full_lock(tp, 0);
1da177e4 17759
63c3a66f 17760 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 17761 err2 = tg3_restart_hw(tp, true);
b02fd9e3 17762 if (err2)
b9ec6c1b 17763 goto out;
1da177e4 17764
21f7638e 17765 tg3_timer_start(tp);
1da177e4
LT		 17766
17767 netif_device_attach(dev);
17768 tg3_netif_start(tp);
17769
b9ec6c1b 17770out:
f47c11ee 17771 tg3_full_unlock(tp);
b02fd9e3
MC		 17772
17773 if (!err2)
17774 tg3_phy_start(tp);
1da177e4
LT		 17775 }
17776
17777 return err;
17778}
17779
c866b7ea 17780static int tg3_resume(struct device *device)
1da177e4 17781{
c866b7ea 17782 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17783 struct net_device *dev = pci_get_drvdata(pdev);
17784 struct tg3 *tp = netdev_priv(dev);
17785 int err;
17786
17787 if (!netif_running(dev))
17788 return 0;
17789
1da177e4
LT		 17790 netif_device_attach(dev);
17791
f47c11ee 17792 tg3_full_lock(tp, 0);
1da177e4 17793
2e460fc0
NS		 17794 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
17795
63c3a66f 17796 tg3_flag_set(tp, INIT_COMPLETE);
942d1af0
NS		 17797 err = tg3_restart_hw(tp,
17798 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
b9ec6c1b
MC		 17799 if (err)
17800 goto out;
1da177e4 17801
21f7638e 17802 tg3_timer_start(tp);
1da177e4 17803
1da177e4
LT		 17804 tg3_netif_start(tp);
17805
b9ec6c1b 17806out:
f47c11ee 17807 tg3_full_unlock(tp);
1da177e4 17808
b02fd9e3
MC		 17809 if (!err)
17810 tg3_phy_start(tp);
17811
b9ec6c1b 17812 return err;
1da177e4 17813}
42df36a6 17814#endif /* CONFIG_PM_SLEEP */
1da177e4 17815
c866b7ea
RW		 17816static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
17817
4c305fa2
NS		 17818static void tg3_shutdown(struct pci_dev *pdev)
17819{
17820 struct net_device *dev = pci_get_drvdata(pdev);
17821 struct tg3 *tp = netdev_priv(dev);
17822
17823 rtnl_lock();
17824 netif_device_detach(dev);
17825
17826 if (netif_running(dev))
17827 dev_close(dev);
17828
17829 if (system_state == SYSTEM_POWER_OFF)
17830 tg3_power_down(tp);
17831
17832 rtnl_unlock();
17833}
17834
b45aa2f6
MC		 17835/**
17836 * tg3_io_error_detected - called when PCI error is detected
17837 * @pdev: Pointer to PCI device
17838 * @state: The current pci connection state
17839 *
17840 * This function is called after a PCI bus error affecting
17841 * this device has been detected.
17842 */
17843static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
17844 pci_channel_state_t state)
17845{
17846 struct net_device *netdev = pci_get_drvdata(pdev);
17847 struct tg3 *tp = netdev_priv(netdev);
17848 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
17849
17850 netdev_info(netdev, "PCI I/O error detected\n");
17851
17852 rtnl_lock();
17853
d8af4dfd
GS		 17854 /* We probably don't have netdev yet */
17855 if (!netdev || !netif_running(netdev))
b45aa2f6
MC		 17856 goto done;
17857
17858 tg3_phy_stop(tp);
17859
17860 tg3_netif_stop(tp);
17861
21f7638e 17862 tg3_timer_stop(tp);
b45aa2f6
MC		 17863
17864 /* Want to make sure that the reset task doesn't run */
db219973 17865 tg3_reset_task_cancel(tp);
b45aa2f6
MC		 17866
17867 netif_device_detach(netdev);
17868
17869 /* Clean up software state, even if MMIO is blocked */
17870 tg3_full_lock(tp, 0);
17871 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
17872 tg3_full_unlock(tp);
17873
17874done:
72bb72b0 17875 if (state == pci_channel_io_perm_failure) {
68293099
DB		 17876 if (netdev) {
17877 tg3_napi_enable(tp);
17878 dev_close(netdev);
17879 }
b45aa2f6 17880 err = PCI_ERS_RESULT_DISCONNECT;
72bb72b0 17881 } else {
b45aa2f6 17882 pci_disable_device(pdev);
72bb72b0 17883 }
b45aa2f6
MC		 17884
17885 rtnl_unlock();
17886
17887 return err;
17888}
17889
17890/**
17891 * tg3_io_slot_reset - called after the pci bus has been reset.
17892 * @pdev: Pointer to PCI device
17893 *
17894 * Restart the card from scratch, as if from a cold-boot.
17895 * At this point, the card has exprienced a hard reset,
17896 * followed by fixups by BIOS, and has its config space
17897 * set up identically to what it was at cold boot.
17898 */
17899static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
17900{
17901 struct net_device *netdev = pci_get_drvdata(pdev);
17902 struct tg3 *tp = netdev_priv(netdev);
17903 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
17904 int err;
17905
17906 rtnl_lock();
17907
17908 if (pci_enable_device(pdev)) {
68293099
DB		 17909 dev_err(&pdev->dev,
17910 "Cannot re-enable PCI device after reset.\n");
b45aa2f6
MC		 17911 goto done;
17912 }
17913
17914 pci_set_master(pdev);
17915 pci_restore_state(pdev);
17916 pci_save_state(pdev);
17917
68293099 17918 if (!netdev || !netif_running(netdev)) {
b45aa2f6
MC		 17919 rc = PCI_ERS_RESULT_RECOVERED;
17920 goto done;
17921 }
17922
17923 err = tg3_power_up(tp);
bed9829f 17924 if (err)
b45aa2f6 17925 goto done;
b45aa2f6
MC		 17926
17927 rc = PCI_ERS_RESULT_RECOVERED;
17928
17929done:
68293099 17930 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
72bb72b0
MC		 17931 tg3_napi_enable(tp);
17932 dev_close(netdev);
17933 }
b45aa2f6
MC		 17934 rtnl_unlock();
17935
17936 return rc;
17937}
17938
17939/**
17940 * tg3_io_resume - called when traffic can start flowing again.
17941 * @pdev: Pointer to PCI device
17942 *
17943 * This callback is called when the error recovery driver tells
17944 * us that its OK to resume normal operation.
17945 */
17946static void tg3_io_resume(struct pci_dev *pdev)
17947{
17948 struct net_device *netdev = pci_get_drvdata(pdev);
17949 struct tg3 *tp = netdev_priv(netdev);
17950 int err;
17951
17952 rtnl_lock();
17953
17954 if (!netif_running(netdev))
17955 goto done;
17956
17957 tg3_full_lock(tp, 0);
2e460fc0 17958 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
63c3a66f 17959 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 17960 err = tg3_restart_hw(tp, true);
b45aa2f6 17961 if (err) {
35763066 17962 tg3_full_unlock(tp);
b45aa2f6
MC		 17963 netdev_err(netdev, "Cannot restart hardware after reset.\n");
17964 goto done;
17965 }
17966
17967 netif_device_attach(netdev);
17968
21f7638e 17969 tg3_timer_start(tp);
b45aa2f6
MC		 17970
17971 tg3_netif_start(tp);
17972
35763066
NNS		 17973 tg3_full_unlock(tp);
17974
b45aa2f6
MC		 17975 tg3_phy_start(tp);
17976
17977done:
17978 rtnl_unlock();
17979}
17980
3646f0e5 17981static const struct pci_error_handlers tg3_err_handler = {
b45aa2f6
MC		 17982 .error_detected = tg3_io_error_detected,
17983 .slot_reset = tg3_io_slot_reset,
17984 .resume = tg3_io_resume
17985};
17986
1da177e4
LT		 17987static struct pci_driver tg3_driver = {
17988 .name = DRV_MODULE_NAME,
17989 .id_table = tg3_pci_tbl,
17990 .probe = tg3_init_one,
229b1ad1 17991 .remove = tg3_remove_one,
b45aa2f6 17992 .err_handler = &tg3_err_handler,
42df36a6 17993 .driver.pm = &tg3_pm_ops,
4c305fa2 17994 .shutdown = tg3_shutdown,
1da177e4
LT		 17995};
17996
8dbb0dc2 17997module_pci_driver(tg3_driver);
Linux kernel - Deliverables
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