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tg3: Remove redundant if check
[deliverable/linux.git] / drivers / net / ethernet / broadcom / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
b681b65d 7 * Copyright (C) 2005-2013 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
6867c843 21#include <linux/stringify.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
14c85021 27#include <linux/in.h>
1da177e4 28#include <linux/init.h>
a6b7a407 29#include <linux/interrupt.h>
1da177e4
LT		 30#include <linux/ioport.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/ethtool.h>
3110f5f5 36#include <linux/mdio.h>
1da177e4 37#include <linux/mii.h>
158d7abd 38#include <linux/phy.h>
a9daf367 39#include <linux/brcmphy.h>
1da177e4
LT		 40#include <linux/if_vlan.h>
41#include <linux/ip.h>
42#include <linux/tcp.h>
43#include <linux/workqueue.h>
61487480 44#include <linux/prefetch.h>
f9a5f7d3 45#include <linux/dma-mapping.h>
077f849d 46#include <linux/firmware.h>
7e6c63f0 47#include <linux/ssb/ssb_driver_gige.h>
aed93e0b
MC		 48#include <linux/hwmon.h>
49#include <linux/hwmon-sysfs.h>
1da177e4
LT		 50
51#include <net/checksum.h>
c9bdd4b5 52#include <net/ip.h>
1da177e4 53
27fd9de8 54#include <linux/io.h>
1da177e4 55#include <asm/byteorder.h>
27fd9de8 56#include <linux/uaccess.h>
1da177e4 57
be947307
MC		 58#include <uapi/linux/net_tstamp.h>
59#include <linux/ptp_clock_kernel.h>
60
49b6e95f 61#ifdef CONFIG_SPARC
1da177e4 62#include <asm/idprom.h>
49b6e95f 63#include <asm/prom.h>
1da177e4
LT		 64#endif
65
63532394
MC		 66#define BAR_0 0
67#define BAR_2 2
68
1da177e4
LT		 69#include "tg3.h"
70
63c3a66f
JP		 71/* Functions & macros to verify TG3_FLAGS types */
72
73static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
74{
75 return test_bit(flag, bits);
76}
77
78static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
79{
80 set_bit(flag, bits);
81}
82
83static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
84{
85 clear_bit(flag, bits);
86}
87
88#define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90#define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92#define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
94
1da177e4 95#define DRV_MODULE_NAME "tg3"
6867c843 96#define TG3_MAJ_NUM 3
cd77b2eb 97#define TG3_MIN_NUM 133
6867c843
MC		 98#define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
cd77b2eb 100#define DRV_MODULE_RELDATE "Jul 29, 2013"
1da177e4 101
fd6d3f0e
MC		 102#define RESET_KIND_SHUTDOWN 0
103#define RESET_KIND_INIT 1
104#define RESET_KIND_SUSPEND 2
105
1da177e4
LT		 106#define TG3_DEF_RX_MODE 0
107#define TG3_DEF_TX_MODE 0
108#define TG3_DEF_MSG_ENABLE \
109 (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK | \
112 NETIF_MSG_TIMER | \
113 NETIF_MSG_IFDOWN | \
114 NETIF_MSG_IFUP | \
115 NETIF_MSG_RX_ERR | \
116 NETIF_MSG_TX_ERR)
117
520b2756
MC		 118#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
119
1da177e4
LT		 120/* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
122 */
63c3a66f 123
1da177e4
LT		 124#define TG3_TX_TIMEOUT (5 * HZ)
125
126/* hardware minimum and maximum for a single frame's data payload */
127#define TG3_MIN_MTU 60
128#define TG3_MAX_MTU(tp) \
63c3a66f 129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 130
131/* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
134 */
7cb32cf2 135#define TG3_RX_STD_RING_SIZE(tp) \
63c3a66f 136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
1da177e4 138#define TG3_DEF_RX_RING_PENDING 200
7cb32cf2 139#define TG3_RX_JMB_RING_SIZE(tp) \
63c3a66f 140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
1da177e4
LT		 142#define TG3_DEF_RX_JUMBO_RING_PENDING 100
143
144/* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
149 */
1da177e4
LT		 150
151#define TG3_TX_RING_SIZE 512
152#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
153
2c49a44d
MC		 154#define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156#define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158#define TG3_RX_RCB_RING_BYTES(tp) \
7cb32cf2 159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
1da177e4
LT		 160#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
161 TG3_TX_RING_SIZE)
1da177e4
LT		 162#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
163
287be12e
MC		 164#define TG3_DMA_BYTE_ENAB 64
165
166#define TG3_RX_STD_DMA_SZ 1536
167#define TG3_RX_JMB_DMA_SZ 9046
168
169#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
170
171#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 173
2c49a44d
MC		 174#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
2b2cdb65 176
2c49a44d
MC		 177#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
2b2cdb65 179
d2757fc4
MC		 180/* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
184 *
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
190 */
191#define TG3_RX_COPY_THRESHOLD 256
192#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
194#else
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
196#endif
197
81389f57
MC		 198#if (NET_IP_ALIGN != 0)
199#define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
200#else
9205fd9c 201#define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
81389f57
MC		 202#endif
203
1da177e4 204/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 205#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
55086ad9 206#define TG3_TX_BD_DMA_MAX_2K 2048
a4cb428d 207#define TG3_TX_BD_DMA_MAX_4K 4096
1da177e4 208
ad829268
MC		 209#define TG3_RAW_IP_ALIGN 2
210
c6cdf436 211#define TG3_FW_UPDATE_TIMEOUT_SEC 5
21f7638e 212#define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
c6cdf436 213
077f849d 214#define FIRMWARE_TG3 "tigon/tg3.bin"
c4dab506 215#define FIRMWARE_TG357766 "tigon/tg357766.bin"
077f849d
JSR		 216#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
217#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
218
229b1ad1 219static char version[] =
05dbe005 220 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 221
222MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
223MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
224MODULE_LICENSE("GPL");
225MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 226MODULE_FIRMWARE(FIRMWARE_TG3);
227MODULE_FIRMWARE(FIRMWARE_TG3TSO);
228MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
229
1da177e4
LT		 230static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
231module_param(tg3_debug, int, 0);
232MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
233
3d567e0e
NNS		 234#define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
235#define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
236
a3aa1884 237static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
3d567e0e
NNS		 256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
257 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
258 TG3_DRV_DATA_FLAG_5705_10_100},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
3d567e0e
NNS		 263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
264 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
265 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
7e6c63f0 268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
13185217 269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
13185217 270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
3d567e0e
NNS		 271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
272 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
3d567e0e
NNS		 277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
278 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
3d567e0e
NNS		 286 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
287 PCI_VENDOR_ID_LENOVO,
288 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
289 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217 290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
3d567e0e
NNS		 291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
3d567e0e
NNS		 311 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
312 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
313 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321d32a0
MC		 317 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
318 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
3d567e0e
NNS		 319 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
320 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
5e7ccf20 321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6 322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
79d49695 323 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
5001e2f6 324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
b0f75221
MC		 325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
3d567e0e
NNS		 329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
330 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
332 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
302b500b 333 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
ba1f3c76 334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
02eca3f5 335 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
d3f677af 336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
c86a8560
MC		 337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
68273712
NS		 340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
13185217
HK		 345 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
346 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
347 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
348 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
349 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
351 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
1dcb14d9 352 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
13185217 353 {}
1da177e4
LT		 354};
355
356MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
357
50da859d 358static const struct {
1da177e4 359 const char string[ETH_GSTRING_LEN];
48fa55a0 360} ethtool_stats_keys[] = {
1da177e4
LT		 361 { "rx_octets" },
362 { "rx_fragments" },
363 { "rx_ucast_packets" },
364 { "rx_mcast_packets" },
365 { "rx_bcast_packets" },
366 { "rx_fcs_errors" },
367 { "rx_align_errors" },
368 { "rx_xon_pause_rcvd" },
369 { "rx_xoff_pause_rcvd" },
370 { "rx_mac_ctrl_rcvd" },
371 { "rx_xoff_entered" },
372 { "rx_frame_too_long_errors" },
373 { "rx_jabbers" },
374 { "rx_undersize_packets" },
375 { "rx_in_length_errors" },
376 { "rx_out_length_errors" },
377 { "rx_64_or_less_octet_packets" },
378 { "rx_65_to_127_octet_packets" },
379 { "rx_128_to_255_octet_packets" },
380 { "rx_256_to_511_octet_packets" },
381 { "rx_512_to_1023_octet_packets" },
382 { "rx_1024_to_1522_octet_packets" },
383 { "rx_1523_to_2047_octet_packets" },
384 { "rx_2048_to_4095_octet_packets" },
385 { "rx_4096_to_8191_octet_packets" },
386 { "rx_8192_to_9022_octet_packets" },
387
388 { "tx_octets" },
389 { "tx_collisions" },
390
391 { "tx_xon_sent" },
392 { "tx_xoff_sent" },
393 { "tx_flow_control" },
394 { "tx_mac_errors" },
395 { "tx_single_collisions" },
396 { "tx_mult_collisions" },
397 { "tx_deferred" },
398 { "tx_excessive_collisions" },
399 { "tx_late_collisions" },
400 { "tx_collide_2times" },
401 { "tx_collide_3times" },
402 { "tx_collide_4times" },
403 { "tx_collide_5times" },
404 { "tx_collide_6times" },
405 { "tx_collide_7times" },
406 { "tx_collide_8times" },
407 { "tx_collide_9times" },
408 { "tx_collide_10times" },
409 { "tx_collide_11times" },
410 { "tx_collide_12times" },
411 { "tx_collide_13times" },
412 { "tx_collide_14times" },
413 { "tx_collide_15times" },
414 { "tx_ucast_packets" },
415 { "tx_mcast_packets" },
416 { "tx_bcast_packets" },
417 { "tx_carrier_sense_errors" },
418 { "tx_discards" },
419 { "tx_errors" },
420
421 { "dma_writeq_full" },
422 { "dma_write_prioq_full" },
423 { "rxbds_empty" },
424 { "rx_discards" },
425 { "rx_errors" },
426 { "rx_threshold_hit" },
427
428 { "dma_readq_full" },
429 { "dma_read_prioq_full" },
430 { "tx_comp_queue_full" },
431
432 { "ring_set_send_prod_index" },
433 { "ring_status_update" },
434 { "nic_irqs" },
435 { "nic_avoided_irqs" },
4452d099
MC		 436 { "nic_tx_threshold_hit" },
437
438 { "mbuf_lwm_thresh_hit" },
1da177e4
LT		 439};
440
48fa55a0 441#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
93df8b8f
NNS		 442#define TG3_NVRAM_TEST 0
443#define TG3_LINK_TEST 1
444#define TG3_REGISTER_TEST 2
445#define TG3_MEMORY_TEST 3
446#define TG3_MAC_LOOPB_TEST 4
447#define TG3_PHY_LOOPB_TEST 5
448#define TG3_EXT_LOOPB_TEST 6
449#define TG3_INTERRUPT_TEST 7
48fa55a0
MC		 450
451
50da859d 452static const struct {
4cafd3f5 453 const char string[ETH_GSTRING_LEN];
48fa55a0 454} ethtool_test_keys[] = {
93df8b8f
NNS		 455 [TG3_NVRAM_TEST] = { "nvram test (online) " },
456 [TG3_LINK_TEST] = { "link test (online) " },
457 [TG3_REGISTER_TEST] = { "register test (offline)" },
458 [TG3_MEMORY_TEST] = { "memory test (offline)" },
459 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
460 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
461 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
462 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
4cafd3f5
MC		 463};
464
48fa55a0
MC		 465#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
466
467
b401e9e2
MC		 468static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
469{
470 writel(val, tp->regs + off);
471}
472
473static u32 tg3_read32(struct tg3 *tp, u32 off)
474{
de6f31eb 475 return readl(tp->regs + off);
b401e9e2
MC		 476}
477
0d3031d9
MC		 478static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
479{
480 writel(val, tp->aperegs + off);
481}
482
483static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
484{
de6f31eb 485 return readl(tp->aperegs + off);
0d3031d9
MC		 486}
487
1da177e4
LT		 488static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
489{
6892914f
MC		 490 unsigned long flags;
491
492 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 493 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
494 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 495 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 496}
497
498static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
499{
500 writel(val, tp->regs + off);
501 readl(tp->regs + off);
1da177e4
LT		 502}
503
6892914f 504static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 505{
6892914f
MC		 506 unsigned long flags;
507 u32 val;
508
509 spin_lock_irqsave(&tp->indirect_lock, flags);
510 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
511 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
512 spin_unlock_irqrestore(&tp->indirect_lock, flags);
513 return val;
514}
515
516static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
517{
518 unsigned long flags;
519
520 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
521 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
522 TG3_64BIT_REG_LOW, val);
523 return;
524 }
66711e66 525 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 526 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
527 TG3_64BIT_REG_LOW, val);
528 return;
1da177e4 529 }
6892914f
MC		 530
531 spin_lock_irqsave(&tp->indirect_lock, flags);
532 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
533 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
535
536 /* In indirect mode when disabling interrupts, we also need
537 * to clear the interrupt bit in the GRC local ctrl register.
538 */
539 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
540 (val == 0x1)) {
541 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
542 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
543 }
544}
545
546static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
547{
548 unsigned long flags;
549 u32 val;
550
551 spin_lock_irqsave(&tp->indirect_lock, flags);
552 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
553 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
554 spin_unlock_irqrestore(&tp->indirect_lock, flags);
555 return val;
556}
557
b401e9e2
MC		 558/* usec_wait specifies the wait time in usec when writing to certain registers
559 * where it is unsafe to read back the register without some delay.
560 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
561 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
562 */
563static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 564{
63c3a66f 565 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
b401e9e2
MC		 566 /* Non-posted methods */
567 tp->write32(tp, off, val);
568 else {
569 /* Posted method */
570 tg3_write32(tp, off, val);
571 if (usec_wait)
572 udelay(usec_wait);
573 tp->read32(tp, off);
574 }
575 /* Wait again after the read for the posted method to guarantee that
576 * the wait time is met.
577 */
578 if (usec_wait)
579 udelay(usec_wait);
1da177e4
LT		 580}
581
09ee929c
MC		 582static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
583{
584 tp->write32_mbox(tp, off, val);
7e6c63f0
HM		 585 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
586 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
587 !tg3_flag(tp, ICH_WORKAROUND)))
6892914f 588 tp->read32_mbox(tp, off);
09ee929c
MC		 589}
590
20094930 591static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 592{
593 void __iomem *mbox = tp->regs + off;
594 writel(val, mbox);
63c3a66f 595 if (tg3_flag(tp, TXD_MBOX_HWBUG))
1da177e4 596 writel(val, mbox);
7e6c63f0
HM		 597 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
598 tg3_flag(tp, FLUSH_POSTED_WRITES))
1da177e4
LT		 599 readl(mbox);
600}
601
b5d3772c
MC		 602static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
603{
de6f31eb 604 return readl(tp->regs + off + GRCMBOX_BASE);
b5d3772c
MC		 605}
606
607static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
608{
609 writel(val, tp->regs + off + GRCMBOX_BASE);
610}
611
c6cdf436 612#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 613#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
c6cdf436
MC		 614#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
615#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
616#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930 617
c6cdf436
MC		 618#define tw32(reg, val) tp->write32(tp, reg, val)
619#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
620#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
621#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 622
623static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
624{
6892914f
MC		 625 unsigned long flags;
626
4153577a 627 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 628 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
629 return;
630
6892914f 631 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 632 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 633 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
634 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 635
bbadf503
MC		 636 /* Always leave this as zero. */
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
638 } else {
639 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
640 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 641
bbadf503
MC		 642 /* Always leave this as zero. */
643 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
644 }
645 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 646}
647
1da177e4
LT		 648static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
649{
6892914f
MC		 650 unsigned long flags;
651
4153577a 652 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 653 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
654 *val = 0;
655 return;
656 }
657
6892914f 658 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 659 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 660 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
661 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 662
bbadf503
MC		 663 /* Always leave this as zero. */
664 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
665 } else {
666 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
667 *val = tr32(TG3PCI_MEM_WIN_DATA);
668
669 /* Always leave this as zero. */
670 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
671 }
6892914f 672 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 673}
674
0d3031d9
MC		 675static void tg3_ape_lock_init(struct tg3 *tp)
676{
677 int i;
6f5c8f83 678 u32 regbase, bit;
f92d9dc1 679
4153577a 680 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 681 regbase = TG3_APE_LOCK_GRANT;
682 else
683 regbase = TG3_APE_PER_LOCK_GRANT;
0d3031d9
MC		 684
685 /* Make sure the driver hasn't any stale locks. */
78f94dc7
MC		 686 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
687 switch (i) {
688 case TG3_APE_LOCK_PHY0:
689 case TG3_APE_LOCK_PHY1:
690 case TG3_APE_LOCK_PHY2:
691 case TG3_APE_LOCK_PHY3:
692 bit = APE_LOCK_GRANT_DRIVER;
693 break;
694 default:
695 if (!tp->pci_fn)
696 bit = APE_LOCK_GRANT_DRIVER;
697 else
698 bit = 1 << tp->pci_fn;
699 }
700 tg3_ape_write32(tp, regbase + 4 * i, bit);
6f5c8f83
MC		 701 }
702
0d3031d9
MC		 703}
704
705static int tg3_ape_lock(struct tg3 *tp, int locknum)
706{
707 int i, off;
708 int ret = 0;
6f5c8f83 709 u32 status, req, gnt, bit;
0d3031d9 710
63c3a66f 711 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 712 return 0;
713
714 switch (locknum) {
6f5c8f83 715 case TG3_APE_LOCK_GPIO:
4153577a 716 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 717 return 0;
33f401ae
MC		 718 case TG3_APE_LOCK_GRC:
719 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 720 if (!tp->pci_fn)
721 bit = APE_LOCK_REQ_DRIVER;
722 else
723 bit = 1 << tp->pci_fn;
33f401ae 724 break;
8151ad57
MC		 725 case TG3_APE_LOCK_PHY0:
726 case TG3_APE_LOCK_PHY1:
727 case TG3_APE_LOCK_PHY2:
728 case TG3_APE_LOCK_PHY3:
729 bit = APE_LOCK_REQ_DRIVER;
730 break;
33f401ae
MC		 731 default:
732 return -EINVAL;
0d3031d9
MC		 733 }
734
4153577a 735 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
f92d9dc1
MC		 736 req = TG3_APE_LOCK_REQ;
737 gnt = TG3_APE_LOCK_GRANT;
738 } else {
739 req = TG3_APE_PER_LOCK_REQ;
740 gnt = TG3_APE_PER_LOCK_GRANT;
741 }
742
0d3031d9
MC		 743 off = 4 * locknum;
744
6f5c8f83 745 tg3_ape_write32(tp, req + off, bit);
0d3031d9
MC		 746
747 /* Wait for up to 1 millisecond to acquire lock. */
748 for (i = 0; i < 100; i++) {
f92d9dc1 749 status = tg3_ape_read32(tp, gnt + off);
6f5c8f83 750 if (status == bit)
0d3031d9 751 break;
6d446ec3
GS		 752 if (pci_channel_offline(tp->pdev))
753 break;
754
0d3031d9
MC		 755 udelay(10);
756 }
757
6f5c8f83 758 if (status != bit) {
0d3031d9 759 /* Revoke the lock request. */
6f5c8f83 760 tg3_ape_write32(tp, gnt + off, bit);
0d3031d9
MC		 761 ret = -EBUSY;
762 }
763
764 return ret;
765}
766
767static void tg3_ape_unlock(struct tg3 *tp, int locknum)
768{
6f5c8f83 769 u32 gnt, bit;
0d3031d9 770
63c3a66f 771 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 772 return;
773
774 switch (locknum) {
6f5c8f83 775 case TG3_APE_LOCK_GPIO:
4153577a 776 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 777 return;
33f401ae
MC		 778 case TG3_APE_LOCK_GRC:
779 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 780 if (!tp->pci_fn)
781 bit = APE_LOCK_GRANT_DRIVER;
782 else
783 bit = 1 << tp->pci_fn;
33f401ae 784 break;
8151ad57
MC		 785 case TG3_APE_LOCK_PHY0:
786 case TG3_APE_LOCK_PHY1:
787 case TG3_APE_LOCK_PHY2:
788 case TG3_APE_LOCK_PHY3:
789 bit = APE_LOCK_GRANT_DRIVER;
790 break;
33f401ae
MC		 791 default:
792 return;
0d3031d9
MC		 793 }
794
4153577a 795 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 796 gnt = TG3_APE_LOCK_GRANT;
797 else
798 gnt = TG3_APE_PER_LOCK_GRANT;
799
6f5c8f83 800 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
0d3031d9
MC		 801}
802
b65a372b 803static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
fd6d3f0e 804{
fd6d3f0e
MC		 805 u32 apedata;
806
b65a372b
MC		 807 while (timeout_us) {
808 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
809 return -EBUSY;
810
811 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
812 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
813 break;
814
815 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
816
817 udelay(10);
818 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
819 }
820
821 return timeout_us ? 0 : -EBUSY;
822}
823
cf8d55ae
MC		 824static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
825{
826 u32 i, apedata;
827
828 for (i = 0; i < timeout_us / 10; i++) {
829 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
830
831 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
832 break;
833
834 udelay(10);
835 }
836
837 return i == timeout_us / 10;
838}
839
86449944
MC		 840static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
841 u32 len)
cf8d55ae
MC		 842{
843 int err;
844 u32 i, bufoff, msgoff, maxlen, apedata;
845
846 if (!tg3_flag(tp, APE_HAS_NCSI))
847 return 0;
848
849 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
850 if (apedata != APE_SEG_SIG_MAGIC)
851 return -ENODEV;
852
853 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
854 if (!(apedata & APE_FW_STATUS_READY))
855 return -EAGAIN;
856
857 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
858 TG3_APE_SHMEM_BASE;
859 msgoff = bufoff + 2 * sizeof(u32);
860 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
861
862 while (len) {
863 u32 length;
864
865 /* Cap xfer sizes to scratchpad limits. */
866 length = (len > maxlen) ? maxlen : len;
867 len -= length;
868
869 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
870 if (!(apedata & APE_FW_STATUS_READY))
871 return -EAGAIN;
872
873 /* Wait for up to 1 msec for APE to service previous event. */
874 err = tg3_ape_event_lock(tp, 1000);
875 if (err)
876 return err;
877
878 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
879 APE_EVENT_STATUS_SCRTCHPD_READ |
880 APE_EVENT_STATUS_EVENT_PENDING;
881 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
882
883 tg3_ape_write32(tp, bufoff, base_off);
884 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
885
886 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
887 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
888
889 base_off += length;
890
891 if (tg3_ape_wait_for_event(tp, 30000))
892 return -EAGAIN;
893
894 for (i = 0; length; i += 4, length -= 4) {
895 u32 val = tg3_ape_read32(tp, msgoff + i);
896 memcpy(data, &val, sizeof(u32));
897 data++;
898 }
899 }
900
901 return 0;
902}
903
b65a372b
MC		 904static int tg3_ape_send_event(struct tg3 *tp, u32 event)
905{
906 int err;
907 u32 apedata;
fd6d3f0e
MC		 908
909 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
910 if (apedata != APE_SEG_SIG_MAGIC)
b65a372b 911 return -EAGAIN;
fd6d3f0e
MC		 912
913 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
914 if (!(apedata & APE_FW_STATUS_READY))
b65a372b 915 return -EAGAIN;
fd6d3f0e
MC		 916
917 /* Wait for up to 1 millisecond for APE to service previous event. */
b65a372b
MC		 918 err = tg3_ape_event_lock(tp, 1000);
919 if (err)
920 return err;
fd6d3f0e 921
b65a372b
MC		 922 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
923 event | APE_EVENT_STATUS_EVENT_PENDING);
fd6d3f0e 924
b65a372b
MC		 925 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
926 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
fd6d3f0e 927
b65a372b 928 return 0;
fd6d3f0e
MC		 929}
930
931static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
932{
933 u32 event;
934 u32 apedata;
935
936 if (!tg3_flag(tp, ENABLE_APE))
937 return;
938
939 switch (kind) {
940 case RESET_KIND_INIT:
941 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
942 APE_HOST_SEG_SIG_MAGIC);
943 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
944 APE_HOST_SEG_LEN_MAGIC);
945 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
946 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
947 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
948 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
949 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
950 APE_HOST_BEHAV_NO_PHYLOCK);
951 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
952 TG3_APE_HOST_DRVR_STATE_START);
953
954 event = APE_EVENT_STATUS_STATE_START;
955 break;
956 case RESET_KIND_SHUTDOWN:
957 /* With the interface we are currently using,
958 * APE does not track driver state. Wiping
959 * out the HOST SEGMENT SIGNATURE forces
960 * the APE to assume OS absent status.
961 */
962 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
963
964 if (device_may_wakeup(&tp->pdev->dev) &&
965 tg3_flag(tp, WOL_ENABLE)) {
966 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
967 TG3_APE_HOST_WOL_SPEED_AUTO);
968 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
969 } else
970 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
971
972 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
973
974 event = APE_EVENT_STATUS_STATE_UNLOAD;
975 break;
fd6d3f0e
MC		 976 default:
977 return;
978 }
979
980 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
981
982 tg3_ape_send_event(tp, event);
983}
984
1da177e4
LT		 985static void tg3_disable_ints(struct tg3 *tp)
986{
89aeb3bc
MC		 987 int i;
988
1da177e4
LT		 989 tw32(TG3PCI_MISC_HOST_CTRL,
990 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 991 for (i = 0; i < tp->irq_max; i++)
992 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 993}
994
1da177e4
LT		 995static void tg3_enable_ints(struct tg3 *tp)
996{
89aeb3bc 997 int i;
89aeb3bc 998
bbe832c0
MC		 999 tp->irq_sync = 0;
1000 wmb();
1001
1da177e4
LT		 1002 tw32(TG3PCI_MISC_HOST_CTRL,
1003 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 1004
f89f38b8 1005 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 1006 for (i = 0; i < tp->irq_cnt; i++) {
1007 struct tg3_napi *tnapi = &tp->napi[i];
c6cdf436 1008
898a56f8 1009 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
63c3a66f 1010 if (tg3_flag(tp, 1SHOT_MSI))
89aeb3bc 1011 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 1012
f89f38b8 1013 tp->coal_now |= tnapi->coal_now;
89aeb3bc 1014 }
f19af9c2
MC		 1015
1016 /* Force an initial interrupt */
63c3a66f 1017 if (!tg3_flag(tp, TAGGED_STATUS) &&
f19af9c2
MC		 1018 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1019 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1020 else
f89f38b8
MC		 1021 tw32(HOSTCC_MODE, tp->coal_now);
1022
1023 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 1024}
1025
17375d25 1026static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 1027{
17375d25 1028 struct tg3 *tp = tnapi->tp;
898a56f8 1029 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 1030 unsigned int work_exists = 0;
1031
1032 /* check for phy events */
63c3a66f 1033 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
04237ddd
MC		 1034 if (sblk->status & SD_STATUS_LINK_CHG)
1035 work_exists = 1;
1036 }
f891ea16
MC		 1037
1038 /* check for TX work to do */
1039 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1040 work_exists = 1;
1041
1042 /* check for RX work to do */
1043 if (tnapi->rx_rcb_prod_idx &&
8d9d7cfc 1044 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 1045 work_exists = 1;
1046
1047 return work_exists;
1048}
1049
17375d25 1050/* tg3_int_reenable
04237ddd
MC		 1051 * similar to tg3_enable_ints, but it accurately determines whether there
1052 * is new work pending and can return without flushing the PIO write
6aa20a22 1053 * which reenables interrupts
1da177e4 1054 */
17375d25 1055static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 1056{
17375d25
MC		 1057 struct tg3 *tp = tnapi->tp;
1058
898a56f8 1059 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 1060 mmiowb();
1061
fac9b83e
DM		 1062 /* When doing tagged status, this work check is unnecessary.
1063 * The last_tag we write above tells the chip which piece of
1064 * work we've completed.
1065 */
63c3a66f 1066 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
04237ddd 1067 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 1068 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 1069}
1070
1da177e4
LT		 1071static void tg3_switch_clocks(struct tg3 *tp)
1072{
f6eb9b1f 1073 u32 clock_ctrl;
1da177e4
LT		 1074 u32 orig_clock_ctrl;
1075
63c3a66f 1076 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
4cf78e4f
MC		 1077 return;
1078
f6eb9b1f
MC		 1079 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1080
1da177e4
LT		 1081 orig_clock_ctrl = clock_ctrl;
1082 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1083 CLOCK_CTRL_CLKRUN_OENABLE |
1084 0x1f);
1085 tp->pci_clock_ctrl = clock_ctrl;
1086
63c3a66f 1087 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4 1088 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 1089 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1090 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 1091 }
1092 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 1093 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1094 clock_ctrl |
1095 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1096 40);
1097 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1098 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1099 40);
1da177e4 1100 }
b401e9e2 1101 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 1102}
1103
1104#define PHY_BUSY_LOOPS 5000
1105
5c358045
HM		 1106static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1107 u32 *val)
1da177e4
LT		 1108{
1109 u32 frame_val;
1110 unsigned int loops;
1111 int ret;
1112
1113 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1114 tw32_f(MAC_MI_MODE,
1115 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1116 udelay(80);
1117 }
1118
8151ad57
MC		 1119 tg3_ape_lock(tp, tp->phy_ape_lock);
1120
1da177e4
LT		 1121 *val = 0x0;
1122
5c358045 1123 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1124 MI_COM_PHY_ADDR_MASK);
1125 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1126 MI_COM_REG_ADDR_MASK);
1127 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 1128
1da177e4
LT		 1129 tw32_f(MAC_MI_COM, frame_val);
1130
1131 loops = PHY_BUSY_LOOPS;
1132 while (loops != 0) {
1133 udelay(10);
1134 frame_val = tr32(MAC_MI_COM);
1135
1136 if ((frame_val & MI_COM_BUSY) == 0) {
1137 udelay(5);
1138 frame_val = tr32(MAC_MI_COM);
1139 break;
1140 }
1141 loops -= 1;
1142 }
1143
1144 ret = -EBUSY;
1145 if (loops != 0) {
1146 *val = frame_val & MI_COM_DATA_MASK;
1147 ret = 0;
1148 }
1149
1150 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1151 tw32_f(MAC_MI_MODE, tp->mi_mode);
1152 udelay(80);
1153 }
1154
8151ad57
MC		 1155 tg3_ape_unlock(tp, tp->phy_ape_lock);
1156
1da177e4
LT		 1157 return ret;
1158}
1159
5c358045
HM		 1160static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1161{
1162 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1163}
1164
1165static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1166 u32 val)
1da177e4
LT		 1167{
1168 u32 frame_val;
1169 unsigned int loops;
1170 int ret;
1171
f07e9af3 1172 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
221c5637 1173 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
b5d3772c
MC		 1174 return 0;
1175
1da177e4
LT		 1176 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1177 tw32_f(MAC_MI_MODE,
1178 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1179 udelay(80);
1180 }
1181
8151ad57
MC		 1182 tg3_ape_lock(tp, tp->phy_ape_lock);
1183
5c358045 1184 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1185 MI_COM_PHY_ADDR_MASK);
1186 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1187 MI_COM_REG_ADDR_MASK);
1188 frame_val |= (val & MI_COM_DATA_MASK);
1189 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 1190
1da177e4
LT		 1191 tw32_f(MAC_MI_COM, frame_val);
1192
1193 loops = PHY_BUSY_LOOPS;
1194 while (loops != 0) {
1195 udelay(10);
1196 frame_val = tr32(MAC_MI_COM);
1197 if ((frame_val & MI_COM_BUSY) == 0) {
1198 udelay(5);
1199 frame_val = tr32(MAC_MI_COM);
1200 break;
1201 }
1202 loops -= 1;
1203 }
1204
1205 ret = -EBUSY;
1206 if (loops != 0)
1207 ret = 0;
1208
1209 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1210 tw32_f(MAC_MI_MODE, tp->mi_mode);
1211 udelay(80);
1212 }
1213
8151ad57
MC		 1214 tg3_ape_unlock(tp, tp->phy_ape_lock);
1215
1da177e4
LT		 1216 return ret;
1217}
1218
5c358045
HM		 1219static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1220{
1221 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1222}
1223
b0988c15
MC		 1224static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1225{
1226 int err;
1227
1228 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1229 if (err)
1230 goto done;
1231
1232 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1233 if (err)
1234 goto done;
1235
1236 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1237 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1238 if (err)
1239 goto done;
1240
1241 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1242
1243done:
1244 return err;
1245}
1246
1247static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1248{
1249 int err;
1250
1251 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1252 if (err)
1253 goto done;
1254
1255 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1256 if (err)
1257 goto done;
1258
1259 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1260 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1261 if (err)
1262 goto done;
1263
1264 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1265
1266done:
1267 return err;
1268}
1269
1270static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1271{
1272 int err;
1273
1274 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1275 if (!err)
1276 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1277
1278 return err;
1279}
1280
1281static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1282{
1283 int err;
1284
1285 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1286 if (!err)
1287 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1288
1289 return err;
1290}
1291
15ee95c3
MC		 1292static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1293{
1294 int err;
1295
1296 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1297 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1298 MII_TG3_AUXCTL_SHDWSEL_MISC);
1299 if (!err)
1300 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1301
1302 return err;
1303}
1304
b4bd2929
MC		 1305static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1306{
1307 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1308 set |= MII_TG3_AUXCTL_MISC_WREN;
1309
1310 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1311}
1312
daf3ec68
NNS		 1313static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1314{
1315 u32 val;
1316 int err;
1d36ba45 1317
daf3ec68 1318 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1d36ba45 1319
daf3ec68
NNS		 1320 if (err)
1321 return err;
daf3ec68 1322
7c10ee32 1323 if (enable)
daf3ec68
NNS		 1324 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1325 else
1326 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1327
1328 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1329 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1330
1331 return err;
1332}
1d36ba45 1333
3ab71071
NS		 1334static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1335{
1336 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1337 reg | val | MII_TG3_MISC_SHDW_WREN);
1338}
1339
95e2869a
MC		 1340static int tg3_bmcr_reset(struct tg3 *tp)
1341{
1342 u32 phy_control;
1343 int limit, err;
1344
1345 /* OK, reset it, and poll the BMCR_RESET bit until it
1346 * clears or we time out.
1347 */
1348 phy_control = BMCR_RESET;
1349 err = tg3_writephy(tp, MII_BMCR, phy_control);
1350 if (err != 0)
1351 return -EBUSY;
1352
1353 limit = 5000;
1354 while (limit--) {
1355 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1356 if (err != 0)
1357 return -EBUSY;
1358
1359 if ((phy_control & BMCR_RESET) == 0) {
1360 udelay(40);
1361 break;
1362 }
1363 udelay(10);
1364 }
d4675b52 1365 if (limit < 0)
95e2869a
MC		 1366 return -EBUSY;
1367
1368 return 0;
1369}
1370
158d7abd
MC		 1371static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1372{
3d16543d 1373 struct tg3 *tp = bp->priv;
158d7abd
MC		 1374 u32 val;
1375
24bb4fb6 1376 spin_lock_bh(&tp->lock);
158d7abd
MC		 1377
1378 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 1379 val = -EIO;
1380
1381 spin_unlock_bh(&tp->lock);
158d7abd
MC		 1382
1383 return val;
1384}
1385
1386static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1387{
3d16543d 1388 struct tg3 *tp = bp->priv;
24bb4fb6 1389 u32 ret = 0;
158d7abd 1390
24bb4fb6 1391 spin_lock_bh(&tp->lock);
158d7abd
MC		 1392
1393 if (tg3_writephy(tp, reg, val))
24bb4fb6 1394 ret = -EIO;
158d7abd 1395
24bb4fb6
MC		 1396 spin_unlock_bh(&tp->lock);
1397
1398 return ret;
158d7abd
MC		 1399}
1400
1401static int tg3_mdio_reset(struct mii_bus *bp)
1402{
1403 return 0;
1404}
1405
9c61d6bc 1406static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 1407{
1408 u32 val;
fcb389df 1409 struct phy_device *phydev;
a9daf367 1410
3f0e3ad7 1411 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df 1412 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 1413 case PHY_ID_BCM50610:
1414 case PHY_ID_BCM50610M:
fcb389df
MC		 1415 val = MAC_PHYCFG2_50610_LED_MODES;
1416 break;
6a443a0f 1417 case PHY_ID_BCMAC131:
fcb389df
MC		 1418 val = MAC_PHYCFG2_AC131_LED_MODES;
1419 break;
6a443a0f 1420 case PHY_ID_RTL8211C:
fcb389df
MC		 1421 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1422 break;
6a443a0f 1423 case PHY_ID_RTL8201E:
fcb389df
MC		 1424 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1425 break;
1426 default:
a9daf367 1427 return;
fcb389df
MC		 1428 }
1429
1430 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1431 tw32(MAC_PHYCFG2, val);
1432
1433 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 1434 val &= ~(MAC_PHYCFG1_RGMII_INT |
1435 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1436 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 1437 tw32(MAC_PHYCFG1, val);
1438
1439 return;
1440 }
1441
63c3a66f 1442 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
fcb389df
MC		 1443 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1444 MAC_PHYCFG2_FMODE_MASK_MASK |
1445 MAC_PHYCFG2_GMODE_MASK_MASK |
1446 MAC_PHYCFG2_ACT_MASK_MASK |
1447 MAC_PHYCFG2_QUAL_MASK_MASK |
1448 MAC_PHYCFG2_INBAND_ENABLE;
1449
1450 tw32(MAC_PHYCFG2, val);
a9daf367 1451
bb85fbb6
MC		 1452 val = tr32(MAC_PHYCFG1);
1453 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1454 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
63c3a66f
JP		 1455 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1456 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1457 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
63c3a66f 1458 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1459 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1460 }
bb85fbb6
MC		 1461 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1462 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1463 tw32(MAC_PHYCFG1, val);
a9daf367 1464
a9daf367
MC		 1465 val = tr32(MAC_EXT_RGMII_MODE);
1466 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1467 MAC_RGMII_MODE_RX_QUALITY |
1468 MAC_RGMII_MODE_RX_ACTIVITY |
1469 MAC_RGMII_MODE_RX_ENG_DET |
1470 MAC_RGMII_MODE_TX_ENABLE |
1471 MAC_RGMII_MODE_TX_LOWPWR |
1472 MAC_RGMII_MODE_TX_RESET);
63c3a66f
JP		 1473 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1474 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367
MC		 1475 val |= MAC_RGMII_MODE_RX_INT_B |
1476 MAC_RGMII_MODE_RX_QUALITY |
1477 MAC_RGMII_MODE_RX_ACTIVITY |
1478 MAC_RGMII_MODE_RX_ENG_DET;
63c3a66f 1479 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1480 val |= MAC_RGMII_MODE_TX_ENABLE |
1481 MAC_RGMII_MODE_TX_LOWPWR |
1482 MAC_RGMII_MODE_TX_RESET;
1483 }
1484 tw32(MAC_EXT_RGMII_MODE, val);
1485}
1486
158d7abd
MC		 1487static void tg3_mdio_start(struct tg3 *tp)
1488{
158d7abd
MC		 1489 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1490 tw32_f(MAC_MI_MODE, tp->mi_mode);
1491 udelay(80);
a9daf367 1492
63c3a66f 1493 if (tg3_flag(tp, MDIOBUS_INITED) &&
4153577a 1494 tg3_asic_rev(tp) == ASIC_REV_5785)
9ea4818d
MC		 1495 tg3_mdio_config_5785(tp);
1496}
1497
1498static int tg3_mdio_init(struct tg3 *tp)
1499{
1500 int i;
1501 u32 reg;
1502 struct phy_device *phydev;
1503
63c3a66f 1504 if (tg3_flag(tp, 5717_PLUS)) {
9c7df915 1505 u32 is_serdes;
882e9793 1506
69f11c99 1507 tp->phy_addr = tp->pci_fn + 1;
882e9793 1508
4153577a 1509 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
d1ec96af
MC		 1510 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1511 else
1512 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1513 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1514 if (is_serdes)
1515 tp->phy_addr += 7;
1516 } else
3f0e3ad7 1517 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1518
158d7abd
MC		 1519 tg3_mdio_start(tp);
1520
63c3a66f 1521 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
158d7abd
MC		 1522 return 0;
1523
298cf9be
LB		 1524 tp->mdio_bus = mdiobus_alloc();
1525 if (tp->mdio_bus == NULL)
1526 return -ENOMEM;
158d7abd 1527
298cf9be
LB		 1528 tp->mdio_bus->name = "tg3 mdio bus";
1529 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1530 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1531 tp->mdio_bus->priv = tp;
1532 tp->mdio_bus->parent = &tp->pdev->dev;
1533 tp->mdio_bus->read = &tg3_mdio_read;
1534 tp->mdio_bus->write = &tg3_mdio_write;
1535 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1536 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1537 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1538
1539 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1540 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1541
1542 /* The bus registration will look for all the PHYs on the mdio bus.
1543 * Unfortunately, it does not ensure the PHY is powered up before
1544 * accessing the PHY ID registers. A chip reset is the
1545 * quickest way to bring the device back to an operational state..
1546 */
1547 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1548 tg3_bmcr_reset(tp);
1549
298cf9be 1550 i = mdiobus_register(tp->mdio_bus);
a9daf367 1551 if (i) {
ab96b241 1552 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1553 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1554 return i;
1555 }
158d7abd 1556
3f0e3ad7 1557 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1558
9c61d6bc 1559 if (!phydev || !phydev->drv) {
ab96b241 1560 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1561 mdiobus_unregister(tp->mdio_bus);
1562 mdiobus_free(tp->mdio_bus);
1563 return -ENODEV;
1564 }
1565
1566 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1567 case PHY_ID_BCM57780:
321d32a0 1568 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1569 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1570 break;
6a443a0f
MC		 1571 case PHY_ID_BCM50610:
1572 case PHY_ID_BCM50610M:
32e5a8d6 1573 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1574 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1575 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1576 PHY_BRCM_AUTO_PWRDWN_ENABLE;
63c3a66f 1577 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
a9daf367 1578 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
63c3a66f 1579 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1580 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
63c3a66f 1581 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367 1582 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1583 /* fallthru */
6a443a0f 1584 case PHY_ID_RTL8211C:
fcb389df 1585 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1586 break;
6a443a0f
MC		 1587 case PHY_ID_RTL8201E:
1588 case PHY_ID_BCMAC131:
a9daf367 1589 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1590 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
f07e9af3 1591 tp->phy_flags |= TG3_PHYFLG_IS_FET;
a9daf367
MC		 1592 break;
1593 }
1594
63c3a66f 1595 tg3_flag_set(tp, MDIOBUS_INITED);
9c61d6bc 1596
4153577a 1597 if (tg3_asic_rev(tp) == ASIC_REV_5785)
9c61d6bc 1598 tg3_mdio_config_5785(tp);
a9daf367
MC		 1599
1600 return 0;
158d7abd
MC		 1601}
1602
1603static void tg3_mdio_fini(struct tg3 *tp)
1604{
63c3a66f
JP		 1605 if (tg3_flag(tp, MDIOBUS_INITED)) {
1606 tg3_flag_clear(tp, MDIOBUS_INITED);
298cf9be
LB		 1607 mdiobus_unregister(tp->mdio_bus);
1608 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1609 }
1610}
1611
4ba526ce
MC		 1612/* tp->lock is held. */
1613static inline void tg3_generate_fw_event(struct tg3 *tp)
1614{
1615 u32 val;
1616
1617 val = tr32(GRC_RX_CPU_EVENT);
1618 val |= GRC_RX_CPU_DRIVER_EVENT;
1619 tw32_f(GRC_RX_CPU_EVENT, val);
1620
1621 tp->last_event_jiffies = jiffies;
1622}
1623
1624#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1625
95e2869a
MC		 1626/* tp->lock is held. */
1627static void tg3_wait_for_event_ack(struct tg3 *tp)
1628{
1629 int i;
4ba526ce
MC		 1630 unsigned int delay_cnt;
1631 long time_remain;
1632
1633 /* If enough time has passed, no wait is necessary. */
1634 time_remain = (long)(tp->last_event_jiffies + 1 +
1635 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1636 (long)jiffies;
1637 if (time_remain < 0)
1638 return;
1639
1640 /* Check if we can shorten the wait time. */
1641 delay_cnt = jiffies_to_usecs(time_remain);
1642 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1643 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1644 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1645
4ba526ce 1646 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1647 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1648 break;
6d446ec3
GS		 1649 if (pci_channel_offline(tp->pdev))
1650 break;
1651
4ba526ce 1652 udelay(8);
95e2869a
MC		 1653 }
1654}
1655
1656/* tp->lock is held. */
b28f389d 1657static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
95e2869a 1658{
b28f389d 1659 u32 reg, val;
95e2869a
MC		 1660
1661 val = 0;
1662 if (!tg3_readphy(tp, MII_BMCR, &reg))
1663 val = reg << 16;
1664 if (!tg3_readphy(tp, MII_BMSR, &reg))
1665 val |= (reg & 0xffff);
b28f389d 1666 *data++ = val;
95e2869a
MC		 1667
1668 val = 0;
1669 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1670 val = reg << 16;
1671 if (!tg3_readphy(tp, MII_LPA, &reg))
1672 val |= (reg & 0xffff);
b28f389d 1673 *data++ = val;
95e2869a
MC		 1674
1675 val = 0;
f07e9af3 1676 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
95e2869a
MC		 1677 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1678 val = reg << 16;
1679 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1680 val |= (reg & 0xffff);
1681 }
b28f389d 1682 *data++ = val;
95e2869a
MC		 1683
1684 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1685 val = reg << 16;
1686 else
1687 val = 0;
b28f389d
MC		 1688 *data++ = val;
1689}
1690
1691/* tp->lock is held. */
1692static void tg3_ump_link_report(struct tg3 *tp)
1693{
1694 u32 data[4];
1695
1696 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1697 return;
1698
1699 tg3_phy_gather_ump_data(tp, data);
1700
1701 tg3_wait_for_event_ack(tp);
1702
1703 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1704 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1705 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1706 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
95e2869a 1709
4ba526ce 1710 tg3_generate_fw_event(tp);
95e2869a
MC		 1711}
1712
8d5a89b3
MC		 1713/* tp->lock is held. */
1714static void tg3_stop_fw(struct tg3 *tp)
1715{
1716 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1717 /* Wait for RX cpu to ACK the previous event. */
1718 tg3_wait_for_event_ack(tp);
1719
1720 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1721
1722 tg3_generate_fw_event(tp);
1723
1724 /* Wait for RX cpu to ACK this event. */
1725 tg3_wait_for_event_ack(tp);
1726 }
1727}
1728
fd6d3f0e
MC		 1729/* tp->lock is held. */
1730static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1731{
1732 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1733 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1734
1735 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1736 switch (kind) {
1737 case RESET_KIND_INIT:
1738 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1739 DRV_STATE_START);
1740 break;
1741
1742 case RESET_KIND_SHUTDOWN:
1743 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1744 DRV_STATE_UNLOAD);
1745 break;
1746
1747 case RESET_KIND_SUSPEND:
1748 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1749 DRV_STATE_SUSPEND);
1750 break;
1751
1752 default:
1753 break;
1754 }
1755 }
fd6d3f0e
MC		 1756}
1757
1758/* tp->lock is held. */
1759static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1760{
1761 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1762 switch (kind) {
1763 case RESET_KIND_INIT:
1764 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1765 DRV_STATE_START_DONE);
1766 break;
1767
1768 case RESET_KIND_SHUTDOWN:
1769 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1770 DRV_STATE_UNLOAD_DONE);
1771 break;
1772
1773 default:
1774 break;
1775 }
1776 }
fd6d3f0e
MC		 1777}
1778
1779/* tp->lock is held. */
1780static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1781{
1782 if (tg3_flag(tp, ENABLE_ASF)) {
1783 switch (kind) {
1784 case RESET_KIND_INIT:
1785 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1786 DRV_STATE_START);
1787 break;
1788
1789 case RESET_KIND_SHUTDOWN:
1790 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1791 DRV_STATE_UNLOAD);
1792 break;
1793
1794 case RESET_KIND_SUSPEND:
1795 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1796 DRV_STATE_SUSPEND);
1797 break;
1798
1799 default:
1800 break;
1801 }
1802 }
1803}
1804
1805static int tg3_poll_fw(struct tg3 *tp)
1806{
1807 int i;
1808 u32 val;
1809
df465abf
NS		 1810 if (tg3_flag(tp, NO_FWARE_REPORTED))
1811 return 0;
1812
7e6c63f0
HM		 1813 if (tg3_flag(tp, IS_SSB_CORE)) {
1814 /* We don't use firmware. */
1815 return 0;
1816 }
1817
4153577a 1818 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
fd6d3f0e
MC		 1819 /* Wait up to 20ms for init done. */
1820 for (i = 0; i < 200; i++) {
1821 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1822 return 0;
6d446ec3
GS		 1823 if (pci_channel_offline(tp->pdev))
1824 return -ENODEV;
1825
fd6d3f0e
MC		 1826 udelay(100);
1827 }
1828 return -ENODEV;
1829 }
1830
1831 /* Wait for firmware initialization to complete. */
1832 for (i = 0; i < 100000; i++) {
1833 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1834 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1835 break;
6d446ec3
GS		 1836 if (pci_channel_offline(tp->pdev)) {
1837 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1838 tg3_flag_set(tp, NO_FWARE_REPORTED);
1839 netdev_info(tp->dev, "No firmware running\n");
1840 }
1841
1842 break;
1843 }
1844
fd6d3f0e
MC		 1845 udelay(10);
1846 }
1847
1848 /* Chip might not be fitted with firmware. Some Sun onboard
1849 * parts are configured like that. So don't signal the timeout
1850 * of the above loop as an error, but do report the lack of
1851 * running firmware once.
1852 */
1853 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1854 tg3_flag_set(tp, NO_FWARE_REPORTED);
1855
1856 netdev_info(tp->dev, "No firmware running\n");
1857 }
1858
4153577a 1859 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
fd6d3f0e
MC		 1860 /* The 57765 A0 needs a little more
1861 * time to do some important work.
1862 */
1863 mdelay(10);
1864 }
1865
1866 return 0;
1867}
1868
95e2869a
MC		 1869static void tg3_link_report(struct tg3 *tp)
1870{
1871 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1872 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1873 tg3_ump_link_report(tp);
1874 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1875 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1876 (tp->link_config.active_speed == SPEED_1000 ?
1877 1000 :
1878 (tp->link_config.active_speed == SPEED_100 ?
1879 100 : 10)),
1880 (tp->link_config.active_duplex == DUPLEX_FULL ?
1881 "full" : "half"));
1882
1883 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1884 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1885 "on" : "off",
1886 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1887 "on" : "off");
47007831
MC		 1888
1889 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1890 netdev_info(tp->dev, "EEE is %s\n",
1891 tp->setlpicnt ? "enabled" : "disabled");
1892
95e2869a
MC		 1893 tg3_ump_link_report(tp);
1894 }
84421b99
NS		 1895
1896 tp->link_up = netif_carrier_ok(tp->dev);
95e2869a
MC		 1897}
1898
fdad8de4
NS		 1899static u32 tg3_decode_flowctrl_1000T(u32 adv)
1900{
1901 u32 flowctrl = 0;
1902
1903 if (adv & ADVERTISE_PAUSE_CAP) {
1904 flowctrl |= FLOW_CTRL_RX;
1905 if (!(adv & ADVERTISE_PAUSE_ASYM))
1906 flowctrl |= FLOW_CTRL_TX;
1907 } else if (adv & ADVERTISE_PAUSE_ASYM)
1908 flowctrl |= FLOW_CTRL_TX;
1909
1910 return flowctrl;
1911}
1912
95e2869a
MC		 1913static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1914{
1915 u16 miireg;
1916
e18ce346 1917 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1918 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1919 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1920 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1921 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1922 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1923 else
1924 miireg = 0;
1925
1926 return miireg;
1927}
1928
fdad8de4
NS		 1929static u32 tg3_decode_flowctrl_1000X(u32 adv)
1930{
1931 u32 flowctrl = 0;
1932
1933 if (adv & ADVERTISE_1000XPAUSE) {
1934 flowctrl |= FLOW_CTRL_RX;
1935 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1936 flowctrl |= FLOW_CTRL_TX;
1937 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1938 flowctrl |= FLOW_CTRL_TX;
1939
1940 return flowctrl;
1941}
1942
95e2869a
MC		 1943static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1944{
1945 u8 cap = 0;
1946
f3791cdf
MC		 1947 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1948 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1949 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1950 if (lcladv & ADVERTISE_1000XPAUSE)
1951 cap = FLOW_CTRL_RX;
1952 if (rmtadv & ADVERTISE_1000XPAUSE)
e18ce346 1953 cap = FLOW_CTRL_TX;
95e2869a
MC		 1954 }
1955
1956 return cap;
1957}
1958
f51f3562 1959static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1960{
b02fd9e3 1961 u8 autoneg;
f51f3562 1962 u8 flowctrl = 0;
95e2869a
MC		 1963 u32 old_rx_mode = tp->rx_mode;
1964 u32 old_tx_mode = tp->tx_mode;
1965
63c3a66f 1966 if (tg3_flag(tp, USE_PHYLIB))
3f0e3ad7 1967 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1968 else
1969 autoneg = tp->link_config.autoneg;
1970
63c3a66f 1971 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
f07e9af3 1972 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
f51f3562 1973 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1974 else
bc02ff95 1975 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1976 } else
1977 flowctrl = tp->link_config.flowctrl;
95e2869a 1978
f51f3562 1979 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1980
e18ce346 1981 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1982 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1983 else
1984 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1985
f51f3562 1986 if (old_rx_mode != tp->rx_mode)
95e2869a 1987 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1988
e18ce346 1989 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1990 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1991 else
1992 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1993
f51f3562 1994 if (old_tx_mode != tp->tx_mode)
95e2869a 1995 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1996}
1997
b02fd9e3
MC		 1998static void tg3_adjust_link(struct net_device *dev)
1999{
2000 u8 oldflowctrl, linkmesg = 0;
2001 u32 mac_mode, lcl_adv, rmt_adv;
2002 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 2003 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 2004
24bb4fb6 2005 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 2006
2007 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2008 MAC_MODE_HALF_DUPLEX);
2009
2010 oldflowctrl = tp->link_config.active_flowctrl;
2011
2012 if (phydev->link) {
2013 lcl_adv = 0;
2014 rmt_adv = 0;
2015
2016 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2017 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748 2018 else if (phydev->speed == SPEED_1000 ||
4153577a 2019 tg3_asic_rev(tp) != ASIC_REV_5785)
b02fd9e3 2020 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 2021 else
2022 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 2023
2024 if (phydev->duplex == DUPLEX_HALF)
2025 mac_mode |= MAC_MODE_HALF_DUPLEX;
2026 else {
f88788f0 2027 lcl_adv = mii_advertise_flowctrl(
b02fd9e3
MC		 2028 tp->link_config.flowctrl);
2029
2030 if (phydev->pause)
2031 rmt_adv = LPA_PAUSE_CAP;
2032 if (phydev->asym_pause)
2033 rmt_adv |= LPA_PAUSE_ASYM;
2034 }
2035
2036 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2037 } else
2038 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2039
2040 if (mac_mode != tp->mac_mode) {
2041 tp->mac_mode = mac_mode;
2042 tw32_f(MAC_MODE, tp->mac_mode);
2043 udelay(40);
2044 }
2045
4153577a 2046 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
fcb389df
MC		 2047 if (phydev->speed == SPEED_10)
2048 tw32(MAC_MI_STAT,
2049 MAC_MI_STAT_10MBPS_MODE |
2050 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2051 else
2052 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2053 }
2054
b02fd9e3
MC		 2055 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2056 tw32(MAC_TX_LENGTHS,
2057 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2058 (6 << TX_LENGTHS_IPG_SHIFT) |
2059 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2060 else
2061 tw32(MAC_TX_LENGTHS,
2062 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2063 (6 << TX_LENGTHS_IPG_SHIFT) |
2064 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2065
34655ad6 2066 if (phydev->link != tp->old_link ||
b02fd9e3
MC		 2067 phydev->speed != tp->link_config.active_speed ||
2068 phydev->duplex != tp->link_config.active_duplex ||
2069 oldflowctrl != tp->link_config.active_flowctrl)
c6cdf436 2070 linkmesg = 1;
b02fd9e3 2071
34655ad6 2072 tp->old_link = phydev->link;
b02fd9e3
MC		 2073 tp->link_config.active_speed = phydev->speed;
2074 tp->link_config.active_duplex = phydev->duplex;
2075
24bb4fb6 2076 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 2077
2078 if (linkmesg)
2079 tg3_link_report(tp);
2080}
2081
2082static int tg3_phy_init(struct tg3 *tp)
2083{
2084 struct phy_device *phydev;
2085
f07e9af3 2086 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
b02fd9e3
MC		 2087 return 0;
2088
2089 /* Bring the PHY back to a known state. */
2090 tg3_bmcr_reset(tp);
2091
3f0e3ad7 2092 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2093
2094 /* Attach the MAC to the PHY. */
f9a8f83b
FF		 2095 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2096 tg3_adjust_link, phydev->interface);
b02fd9e3 2097 if (IS_ERR(phydev)) {
ab96b241 2098 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 2099 return PTR_ERR(phydev);
2100 }
2101
b02fd9e3 2102 /* Mask with MAC supported features. */
9c61d6bc
MC		 2103 switch (phydev->interface) {
2104 case PHY_INTERFACE_MODE_GMII:
2105 case PHY_INTERFACE_MODE_RGMII:
f07e9af3 2106 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
321d32a0
MC		 2107 phydev->supported &= (PHY_GBIT_FEATURES |
2108 SUPPORTED_Pause |
2109 SUPPORTED_Asym_Pause);
2110 break;
2111 }
2112 /* fallthru */
9c61d6bc
MC		 2113 case PHY_INTERFACE_MODE_MII:
2114 phydev->supported &= (PHY_BASIC_FEATURES |
2115 SUPPORTED_Pause |
2116 SUPPORTED_Asym_Pause);
2117 break;
2118 default:
3f0e3ad7 2119 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 2120 return -EINVAL;
2121 }
2122
f07e9af3 2123 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2124
2125 phydev->advertising = phydev->supported;
2126
b02fd9e3
MC		 2127 return 0;
2128}
2129
2130static void tg3_phy_start(struct tg3 *tp)
2131{
2132 struct phy_device *phydev;
2133
f07e9af3 2134 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2135 return;
2136
3f0e3ad7 2137 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 2138
80096068
MC		 2139 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2140 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
c6700ce2
MC		 2141 phydev->speed = tp->link_config.speed;
2142 phydev->duplex = tp->link_config.duplex;
2143 phydev->autoneg = tp->link_config.autoneg;
2144 phydev->advertising = tp->link_config.advertising;
b02fd9e3
MC		 2145 }
2146
2147 phy_start(phydev);
2148
2149 phy_start_aneg(phydev);
2150}
2151
2152static void tg3_phy_stop(struct tg3 *tp)
2153{
f07e9af3 2154 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2155 return;
2156
3f0e3ad7 2157 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 2158}
2159
2160static void tg3_phy_fini(struct tg3 *tp)
2161{
f07e9af3 2162 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7 2163 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
f07e9af3 2164 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2165 }
2166}
2167
941ec90f
MC		 2168static int tg3_phy_set_extloopbk(struct tg3 *tp)
2169{
2170 int err;
2171 u32 val;
2172
2173 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2174 return 0;
2175
2176 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2177 /* Cannot do read-modify-write on 5401 */
2178 err = tg3_phy_auxctl_write(tp,
2179 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2180 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2181 0x4c20);
2182 goto done;
2183 }
2184
2185 err = tg3_phy_auxctl_read(tp,
2186 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2187 if (err)
2188 return err;
2189
2190 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2191 err = tg3_phy_auxctl_write(tp,
2192 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2193
2194done:
2195 return err;
2196}
2197
7f97a4bd
MC		 2198static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2199{
2200 u32 phytest;
2201
2202 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2203 u32 phy;
2204
2205 tg3_writephy(tp, MII_TG3_FET_TEST,
2206 phytest | MII_TG3_FET_SHADOW_EN);
2207 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2208 if (enable)
2209 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2210 else
2211 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2212 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2213 }
2214 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2215 }
2216}
2217
6833c043
MC		 2218static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2219{
2220 u32 reg;
2221
63c3a66f
JP		 2222 if (!tg3_flag(tp, 5705_PLUS) ||
2223 (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2224 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
6833c043
MC		 2225 return;
2226
f07e9af3 2227 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7f97a4bd
MC		 2228 tg3_phy_fet_toggle_apd(tp, enable);
2229 return;
2230 }
2231
3ab71071 2232 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
6833c043
MC		 2233 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2234 MII_TG3_MISC_SHDW_SCR5_SDTL |
2235 MII_TG3_MISC_SHDW_SCR5_C125OE;
4153577a 2236 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
6833c043
MC		 2237 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2238
3ab71071 2239 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
6833c043
MC		 2240
2241
3ab71071 2242 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
6833c043
MC		 2243 if (enable)
2244 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2245
3ab71071 2246 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
6833c043
MC		 2247}
2248
953c96e0 2249static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
9ef8ca99
MC		 2250{
2251 u32 phy;
2252
63c3a66f 2253 if (!tg3_flag(tp, 5705_PLUS) ||
f07e9af3 2254 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9ef8ca99
MC		 2255 return;
2256
f07e9af3 2257 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
9ef8ca99
MC		 2258 u32 ephy;
2259
535ef6e1
MC		 2260 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2261 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2262
2263 tg3_writephy(tp, MII_TG3_FET_TEST,
2264 ephy | MII_TG3_FET_SHADOW_EN);
2265 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 2266 if (enable)
535ef6e1 2267 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 2268 else
535ef6e1
MC		 2269 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2270 tg3_writephy(tp, reg, phy);
9ef8ca99 2271 }
535ef6e1 2272 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 2273 }
2274 } else {
15ee95c3
MC		 2275 int ret;
2276
2277 ret = tg3_phy_auxctl_read(tp,
2278 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2279 if (!ret) {
9ef8ca99
MC		 2280 if (enable)
2281 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2282 else
2283 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
b4bd2929
MC		 2284 tg3_phy_auxctl_write(tp,
2285 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
9ef8ca99
MC		 2286 }
2287 }
2288}
2289
1da177e4
LT		 2290static void tg3_phy_set_wirespeed(struct tg3 *tp)
2291{
15ee95c3 2292 int ret;
1da177e4
LT		 2293 u32 val;
2294
f07e9af3 2295 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1da177e4
LT		 2296 return;
2297
15ee95c3
MC		 2298 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2299 if (!ret)
b4bd2929
MC		 2300 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2301 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1da177e4
LT		 2302}
2303
b2a5c19c
MC		 2304static void tg3_phy_apply_otp(struct tg3 *tp)
2305{
2306 u32 otp, phy;
2307
2308 if (!tp->phy_otp)
2309 return;
2310
2311 otp = tp->phy_otp;
2312
daf3ec68 2313 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
1d36ba45 2314 return;
b2a5c19c
MC		 2315
2316 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2317 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2318 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2319
2320 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2321 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2322 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2323
2324 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2325 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2326 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2327
2328 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2329 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2330
2331 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2332 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2333
2334 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2335 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2337
daf3ec68 2338 tg3_phy_toggle_auxctl_smdsp(tp, false);
b2a5c19c
MC		 2339}
2340
400dfbaa
NS		 2341static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2342{
2343 u32 val;
2344 struct ethtool_eee *dest = &tp->eee;
2345
2346 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2347 return;
2348
2349 if (eee)
2350 dest = eee;
2351
2352 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2353 return;
2354
2355 /* Pull eee_active */
2356 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2357 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2358 dest->eee_active = 1;
2359 } else
2360 dest->eee_active = 0;
2361
2362 /* Pull lp advertised settings */
2363 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2364 return;
2365 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2366
2367 /* Pull advertised and eee_enabled settings */
2368 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2369 return;
2370 dest->eee_enabled = !!val;
2371 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2372
2373 /* Pull tx_lpi_enabled */
2374 val = tr32(TG3_CPMU_EEE_MODE);
2375 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2376
2377 /* Pull lpi timer value */
2378 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2379}
2380
953c96e0 2381static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
52b02d04
MC		 2382{
2383 u32 val;
2384
2385 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2386 return;
2387
2388 tp->setlpicnt = 0;
2389
2390 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
953c96e0 2391 current_link_up &&
a6b68dab
MC		 2392 tp->link_config.active_duplex == DUPLEX_FULL &&
2393 (tp->link_config.active_speed == SPEED_100 ||
2394 tp->link_config.active_speed == SPEED_1000)) {
52b02d04
MC		 2395 u32 eeectl;
2396
2397 if (tp->link_config.active_speed == SPEED_1000)
2398 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2399 else
2400 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2401
2402 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2403
400dfbaa
NS		 2404 tg3_eee_pull_config(tp, NULL);
2405 if (tp->eee.eee_active)
52b02d04
MC		 2406 tp->setlpicnt = 2;
2407 }
2408
2409 if (!tp->setlpicnt) {
953c96e0 2410 if (current_link_up &&
daf3ec68 2411 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94 2412 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
daf3ec68 2413 tg3_phy_toggle_auxctl_smdsp(tp, false);
b715ce94
MC		 2414 }
2415
52b02d04
MC		 2416 val = tr32(TG3_CPMU_EEE_MODE);
2417 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2418 }
2419}
2420
b0c5943f
MC		 2421static void tg3_phy_eee_enable(struct tg3 *tp)
2422{
2423 u32 val;
2424
2425 if (tp->link_config.active_speed == SPEED_1000 &&
4153577a
JP		 2426 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2427 tg3_asic_rev(tp) == ASIC_REV_5719 ||
55086ad9 2428 tg3_flag(tp, 57765_CLASS)) &&
daf3ec68 2429 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94
MC		 2430 val = MII_TG3_DSP_TAP26_ALNOKO |
2431 MII_TG3_DSP_TAP26_RMRXSTO;
2432 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
daf3ec68 2433 tg3_phy_toggle_auxctl_smdsp(tp, false);
b0c5943f
MC		 2434 }
2435
2436 val = tr32(TG3_CPMU_EEE_MODE);
2437 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2438}
2439
1da177e4
LT		 2440static int tg3_wait_macro_done(struct tg3 *tp)
2441{
2442 int limit = 100;
2443
2444 while (limit--) {
2445 u32 tmp32;
2446
f08aa1a8 2447 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1da177e4
LT		 2448 if ((tmp32 & 0x1000) == 0)
2449 break;
2450 }
2451 }
d4675b52 2452 if (limit < 0)
1da177e4
LT		 2453 return -EBUSY;
2454
2455 return 0;
2456}
2457
2458static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2459{
2460 static const u32 test_pat[4][6] = {
2461 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2462 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2463 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2464 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2465 };
2466 int chan;
2467
2468 for (chan = 0; chan < 4; chan++) {
2469 int i;
2470
2471 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2472 (chan * 0x2000) | 0x0200);
f08aa1a8 2473 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2474
2475 for (i = 0; i < 6; i++)
2476 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2477 test_pat[chan][i]);
2478
f08aa1a8 2479 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2480 if (tg3_wait_macro_done(tp)) {
2481 *resetp = 1;
2482 return -EBUSY;
2483 }
2484
2485 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2486 (chan * 0x2000) | 0x0200);
f08aa1a8 2487 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1da177e4
LT		 2488 if (tg3_wait_macro_done(tp)) {
2489 *resetp = 1;
2490 return -EBUSY;
2491 }
2492
f08aa1a8 2493 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1da177e4
LT		 2494 if (tg3_wait_macro_done(tp)) {
2495 *resetp = 1;
2496 return -EBUSY;
2497 }
2498
2499 for (i = 0; i < 6; i += 2) {
2500 u32 low, high;
2501
2502 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2503 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2504 tg3_wait_macro_done(tp)) {
2505 *resetp = 1;
2506 return -EBUSY;
2507 }
2508 low &= 0x7fff;
2509 high &= 0x000f;
2510 if (low != test_pat[chan][i] ||
2511 high != test_pat[chan][i+1]) {
2512 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2513 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2514 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2515
2516 return -EBUSY;
2517 }
2518 }
2519 }
2520
2521 return 0;
2522}
2523
2524static int tg3_phy_reset_chanpat(struct tg3 *tp)
2525{
2526 int chan;
2527
2528 for (chan = 0; chan < 4; chan++) {
2529 int i;
2530
2531 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2532 (chan * 0x2000) | 0x0200);
f08aa1a8 2533 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2534 for (i = 0; i < 6; i++)
2535 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
f08aa1a8 2536 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2537 if (tg3_wait_macro_done(tp))
2538 return -EBUSY;
2539 }
2540
2541 return 0;
2542}
2543
2544static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2545{
2546 u32 reg32, phy9_orig;
2547 int retries, do_phy_reset, err;
2548
2549 retries = 10;
2550 do_phy_reset = 1;
2551 do {
2552 if (do_phy_reset) {
2553 err = tg3_bmcr_reset(tp);
2554 if (err)
2555 return err;
2556 do_phy_reset = 0;
2557 }
2558
2559 /* Disable transmitter and interrupt. */
2560 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2561 continue;
2562
2563 reg32 |= 0x3000;
2564 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2565
2566 /* Set full-duplex, 1000 mbps. */
2567 tg3_writephy(tp, MII_BMCR,
221c5637 2568 BMCR_FULLDPLX | BMCR_SPEED1000);
1da177e4
LT		 2569
2570 /* Set to master mode. */
221c5637 2571 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
1da177e4
LT		 2572 continue;
2573
221c5637
MC		 2574 tg3_writephy(tp, MII_CTRL1000,
2575 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
1da177e4 2576
daf3ec68 2577 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
1d36ba45
MC		 2578 if (err)
2579 return err;
1da177e4
LT		 2580
2581 /* Block the PHY control access. */
6ee7c0a0 2582 tg3_phydsp_write(tp, 0x8005, 0x0800);
1da177e4
LT		 2583
2584 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2585 if (!err)
2586 break;
2587 } while (--retries);
2588
2589 err = tg3_phy_reset_chanpat(tp);
2590 if (err)
2591 return err;
2592
6ee7c0a0 2593 tg3_phydsp_write(tp, 0x8005, 0x0000);
1da177e4
LT		 2594
2595 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
f08aa1a8 2596 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1da177e4 2597
daf3ec68 2598 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2599
221c5637 2600 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
1da177e4
LT		 2601
2602 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2603 reg32 &= ~0x3000;
2604 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2605 } else if (!err)
2606 err = -EBUSY;
2607
2608 return err;
2609}
2610
f4a46d1f
NNS		 2611static void tg3_carrier_off(struct tg3 *tp)
2612{
2613 netif_carrier_off(tp->dev);
2614 tp->link_up = false;
2615}
2616
ce20f161
NS		 2617static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2618{
2619 if (tg3_flag(tp, ENABLE_ASF))
2620 netdev_warn(tp->dev,
2621 "Management side-band traffic will be interrupted during phy settings change\n");
2622}
2623
1da177e4
LT		 2624/* This will reset the tigon3 PHY if there is no valid
2625 * link unless the FORCE argument is non-zero.
2626 */
2627static int tg3_phy_reset(struct tg3 *tp)
2628{
f833c4c1 2629 u32 val, cpmuctrl;
1da177e4
LT		 2630 int err;
2631
4153577a 2632 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 2633 val = tr32(GRC_MISC_CFG);
2634 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2635 udelay(40);
2636 }
f833c4c1
MC		 2637 err = tg3_readphy(tp, MII_BMSR, &val);
2638 err |= tg3_readphy(tp, MII_BMSR, &val);
1da177e4
LT		 2639 if (err != 0)
2640 return -EBUSY;
2641
f4a46d1f 2642 if (netif_running(tp->dev) && tp->link_up) {
84421b99 2643 netif_carrier_off(tp->dev);
c8e1e82b
MC		 2644 tg3_link_report(tp);
2645 }
2646
4153577a
JP		 2647 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2648 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2649 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 2650 err = tg3_phy_reset_5703_4_5(tp);
2651 if (err)
2652 return err;
2653 goto out;
2654 }
2655
b2a5c19c 2656 cpmuctrl = 0;
4153577a
JP		 2657 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2658 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 2659 cpmuctrl = tr32(TG3_CPMU_CTRL);
2660 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2661 tw32(TG3_CPMU_CTRL,
2662 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2663 }
2664
1da177e4
LT		 2665 err = tg3_bmcr_reset(tp);
2666 if (err)
2667 return err;
2668
b2a5c19c 2669 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
f833c4c1
MC		 2670 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2671 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
b2a5c19c
MC		 2672
2673 tw32(TG3_CPMU_CTRL, cpmuctrl);
2674 }
2675
4153577a
JP		 2676 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2677 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 2678 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2679 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2680 CPMU_LSPD_1000MB_MACCLK_12_5) {
2681 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2682 udelay(40);
2683 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2684 }
2685 }
2686
63c3a66f 2687 if (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2688 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
ecf1410b
MC		 2689 return 0;
2690
b2a5c19c
MC		 2691 tg3_phy_apply_otp(tp);
2692
f07e9af3 2693 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
6833c043
MC		 2694 tg3_phy_toggle_apd(tp, true);
2695 else
2696 tg3_phy_toggle_apd(tp, false);
2697
1da177e4 2698out:
1d36ba45 2699 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
daf3ec68 2700 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
6ee7c0a0
MC		 2701 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2702 tg3_phydsp_write(tp, 0x000a, 0x0323);
daf3ec68 2703 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2704 }
1d36ba45 2705
f07e9af3 2706 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
f08aa1a8
MC		 2707 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2708 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1da177e4 2709 }
1d36ba45 2710
f07e9af3 2711 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
daf3ec68 2712 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2713 tg3_phydsp_write(tp, 0x000a, 0x310b);
2714 tg3_phydsp_write(tp, 0x201f, 0x9506);
2715 tg3_phydsp_write(tp, 0x401f, 0x14e2);
daf3ec68 2716 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2717 }
f07e9af3 2718 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
daf3ec68 2719 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2720 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2721 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2722 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2723 tg3_writephy(tp, MII_TG3_TEST1,
2724 MII_TG3_TEST1_TRIM_EN | 0x4);
2725 } else
2726 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2727
daf3ec68 2728 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2729 }
c424cb24 2730 }
1d36ba45 2731
1da177e4
LT		 2732 /* Set Extended packet length bit (bit 14) on all chips that */
2733 /* support jumbo frames */
79eb6904 2734 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4 2735 /* Cannot do read-modify-write on 5401 */
b4bd2929 2736 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
63c3a66f 2737 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
1da177e4 2738 /* Set bit 14 with read-modify-write to preserve other bits */
15ee95c3
MC		 2739 err = tg3_phy_auxctl_read(tp,
2740 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2741 if (!err)
b4bd2929
MC		 2742 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2743 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
1da177e4
LT		 2744 }
2745
2746 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2747 * jumbo frames transmission.
2748 */
63c3a66f 2749 if (tg3_flag(tp, JUMBO_CAPABLE)) {
f833c4c1 2750 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
c6cdf436 2751 tg3_writephy(tp, MII_TG3_EXT_CTRL,
f833c4c1 2752 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1da177e4
LT		 2753 }
2754
4153577a 2755 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
715116a1 2756 /* adjust output voltage */
535ef6e1 2757 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2758 }
2759
4153577a 2760 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
c65a17f4
MC		 2761 tg3_phydsp_write(tp, 0xffb, 0x4000);
2762
953c96e0 2763 tg3_phy_toggle_automdix(tp, true);
1da177e4
LT		 2764 tg3_phy_set_wirespeed(tp);
2765 return 0;
2766}
2767
3a1e19d3
MC		 2768#define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2769#define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2770#define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2771 TG3_GPIO_MSG_NEED_VAUX)
2772#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2773 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2774 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2775 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2776 (TG3_GPIO_MSG_DRVR_PRES << 12))
2777
2778#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2779 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2780 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2781 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2782 (TG3_GPIO_MSG_NEED_VAUX << 12))
2783
2784static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2785{
2786 u32 status, shift;
2787
4153577a
JP		 2788 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2789 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2790 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2791 else
2792 status = tr32(TG3_CPMU_DRV_STATUS);
2793
2794 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2795 status &= ~(TG3_GPIO_MSG_MASK << shift);
2796 status |= (newstat << shift);
2797
4153577a
JP		 2798 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2799 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2800 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2801 else
2802 tw32(TG3_CPMU_DRV_STATUS, status);
2803
2804 return status >> TG3_APE_GPIO_MSG_SHIFT;
2805}
2806
520b2756
MC		 2807static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2808{
2809 if (!tg3_flag(tp, IS_NIC))
2810 return 0;
2811
4153577a
JP		 2812 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2813 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2814 tg3_asic_rev(tp) == ASIC_REV_5720) {
3a1e19d3
MC		 2815 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2816 return -EIO;
520b2756 2817
3a1e19d3
MC		 2818 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2819
2820 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2821 TG3_GRC_LCLCTL_PWRSW_DELAY);
2822
2823 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2824 } else {
2825 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2826 TG3_GRC_LCLCTL_PWRSW_DELAY);
2827 }
6f5c8f83 2828
520b2756
MC		 2829 return 0;
2830}
2831
2832static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2833{
2834 u32 grc_local_ctrl;
2835
2836 if (!tg3_flag(tp, IS_NIC) ||
4153577a
JP		 2837 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2838 tg3_asic_rev(tp) == ASIC_REV_5701)
520b2756
MC		 2839 return;
2840
2841 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2842
2843 tw32_wait_f(GRC_LOCAL_CTRL,
2844 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2845 TG3_GRC_LCLCTL_PWRSW_DELAY);
2846
2847 tw32_wait_f(GRC_LOCAL_CTRL,
2848 grc_local_ctrl,
2849 TG3_GRC_LCLCTL_PWRSW_DELAY);
2850
2851 tw32_wait_f(GRC_LOCAL_CTRL,
2852 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2853 TG3_GRC_LCLCTL_PWRSW_DELAY);
2854}
2855
2856static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2857{
2858 if (!tg3_flag(tp, IS_NIC))
2859 return;
2860
4153577a
JP		 2861 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2862 tg3_asic_rev(tp) == ASIC_REV_5701) {
520b2756
MC		 2863 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2864 (GRC_LCLCTRL_GPIO_OE0 |
2865 GRC_LCLCTRL_GPIO_OE1 |
2866 GRC_LCLCTRL_GPIO_OE2 |
2867 GRC_LCLCTRL_GPIO_OUTPUT0 |
2868 GRC_LCLCTRL_GPIO_OUTPUT1),
2869 TG3_GRC_LCLCTL_PWRSW_DELAY);
2870 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2871 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2872 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2873 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2874 GRC_LCLCTRL_GPIO_OE1 |
2875 GRC_LCLCTRL_GPIO_OE2 |
2876 GRC_LCLCTRL_GPIO_OUTPUT0 |
2877 GRC_LCLCTRL_GPIO_OUTPUT1 |
2878 tp->grc_local_ctrl;
2879 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2880 TG3_GRC_LCLCTL_PWRSW_DELAY);
2881
2882 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2883 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2884 TG3_GRC_LCLCTL_PWRSW_DELAY);
2885
2886 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2887 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2888 TG3_GRC_LCLCTL_PWRSW_DELAY);
2889 } else {
2890 u32 no_gpio2;
2891 u32 grc_local_ctrl = 0;
2892
2893 /* Workaround to prevent overdrawing Amps. */
4153577a 2894 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
520b2756
MC		 2895 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2896 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2897 grc_local_ctrl,
2898 TG3_GRC_LCLCTL_PWRSW_DELAY);
2899 }
2900
2901 /* On 5753 and variants, GPIO2 cannot be used. */
2902 no_gpio2 = tp->nic_sram_data_cfg &
2903 NIC_SRAM_DATA_CFG_NO_GPIO2;
2904
2905 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2906 GRC_LCLCTRL_GPIO_OE1 |
2907 GRC_LCLCTRL_GPIO_OE2 |
2908 GRC_LCLCTRL_GPIO_OUTPUT1 |
2909 GRC_LCLCTRL_GPIO_OUTPUT2;
2910 if (no_gpio2) {
2911 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2912 GRC_LCLCTRL_GPIO_OUTPUT2);
2913 }
2914 tw32_wait_f(GRC_LOCAL_CTRL,
2915 tp->grc_local_ctrl | grc_local_ctrl,
2916 TG3_GRC_LCLCTL_PWRSW_DELAY);
2917
2918 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2919
2920 tw32_wait_f(GRC_LOCAL_CTRL,
2921 tp->grc_local_ctrl | grc_local_ctrl,
2922 TG3_GRC_LCLCTL_PWRSW_DELAY);
2923
2924 if (!no_gpio2) {
2925 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2926 tw32_wait_f(GRC_LOCAL_CTRL,
2927 tp->grc_local_ctrl | grc_local_ctrl,
2928 TG3_GRC_LCLCTL_PWRSW_DELAY);
2929 }
2930 }
3a1e19d3
MC		 2931}
2932
cd0d7228 2933static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
3a1e19d3
MC		 2934{
2935 u32 msg = 0;
2936
2937 /* Serialize power state transitions */
2938 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2939 return;
2940
cd0d7228 2941 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
3a1e19d3
MC		 2942 msg = TG3_GPIO_MSG_NEED_VAUX;
2943
2944 msg = tg3_set_function_status(tp, msg);
2945
2946 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2947 goto done;
6f5c8f83 2948
3a1e19d3
MC		 2949 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2950 tg3_pwrsrc_switch_to_vaux(tp);
2951 else
2952 tg3_pwrsrc_die_with_vmain(tp);
2953
2954done:
6f5c8f83 2955 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
520b2756
MC		 2956}
2957
cd0d7228 2958static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
1da177e4 2959{
683644b7 2960 bool need_vaux = false;
1da177e4 2961
334355aa 2962 /* The GPIOs do something completely different on 57765. */
55086ad9 2963 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
1da177e4
LT		 2964 return;
2965
4153577a
JP		 2966 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2967 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2968 tg3_asic_rev(tp) == ASIC_REV_5720) {
cd0d7228
MC		 2969 tg3_frob_aux_power_5717(tp, include_wol ?
2970 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
3a1e19d3
MC		 2971 return;
2972 }
2973
2974 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
8c2dc7e1
MC		 2975 struct net_device *dev_peer;
2976
2977 dev_peer = pci_get_drvdata(tp->pdev_peer);
683644b7 2978
bc1c7567 2979 /* remove_one() may have been run on the peer. */
683644b7
MC		 2980 if (dev_peer) {
2981 struct tg3 *tp_peer = netdev_priv(dev_peer);
2982
63c3a66f 2983 if (tg3_flag(tp_peer, INIT_COMPLETE))
683644b7
MC		 2984 return;
2985
cd0d7228 2986 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
63c3a66f 2987 tg3_flag(tp_peer, ENABLE_ASF))
683644b7
MC		 2988 need_vaux = true;
2989 }
1da177e4
LT		 2990 }
2991
cd0d7228
MC		 2992 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2993 tg3_flag(tp, ENABLE_ASF))
683644b7
MC		 2994 need_vaux = true;
2995
520b2756
MC		 2996 if (need_vaux)
2997 tg3_pwrsrc_switch_to_vaux(tp);
2998 else
2999 tg3_pwrsrc_die_with_vmain(tp);
1da177e4
LT		 3000}
3001
e8f3f6ca
MC		 3002static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3003{
3004 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3005 return 1;
79eb6904 3006 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 3007 if (speed != SPEED_10)
3008 return 1;
3009 } else if (speed == SPEED_10)
3010 return 1;
3011
3012 return 0;
3013}
3014
44f3b503
NS		 3015static bool tg3_phy_power_bug(struct tg3 *tp)
3016{
3017 switch (tg3_asic_rev(tp)) {
3018 case ASIC_REV_5700:
3019 case ASIC_REV_5704:
3020 return true;
3021 case ASIC_REV_5780:
3022 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3023 return true;
3024 return false;
3025 case ASIC_REV_5717:
3026 if (!tp->pci_fn)
3027 return true;
3028 return false;
3029 case ASIC_REV_5719:
3030 case ASIC_REV_5720:
3031 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3032 !tp->pci_fn)
3033 return true;
3034 return false;
3035 }
3036
3037 return false;
3038}
3039
989038e2
NS		 3040static bool tg3_phy_led_bug(struct tg3 *tp)
3041{
3042 switch (tg3_asic_rev(tp)) {
3043 case ASIC_REV_5719:
300cf9b9 3044 case ASIC_REV_5720:
989038e2
NS		 3045 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3046 !tp->pci_fn)
3047 return true;
3048 return false;
3049 }
3050
3051 return false;
3052}
3053
0a459aac 3054static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 3055{
ce057f01
MC		 3056 u32 val;
3057
942d1af0
NS		 3058 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3059 return;
3060
f07e9af3 3061 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a 3062 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
5129724a
MC		 3063 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3064 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3065
3066 sg_dig_ctrl |=
3067 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3068 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3069 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3070 }
3f7045c1 3071 return;
5129724a 3072 }
3f7045c1 3073
4153577a 3074 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 3075 tg3_bmcr_reset(tp);
3076 val = tr32(GRC_MISC_CFG);
3077 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3078 udelay(40);
3079 return;
f07e9af3 3080 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
0e5f784c
MC		 3081 u32 phytest;
3082 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3083 u32 phy;
3084
3085 tg3_writephy(tp, MII_ADVERTISE, 0);
3086 tg3_writephy(tp, MII_BMCR,
3087 BMCR_ANENABLE | BMCR_ANRESTART);
3088
3089 tg3_writephy(tp, MII_TG3_FET_TEST,
3090 phytest | MII_TG3_FET_SHADOW_EN);
3091 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3092 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3093 tg3_writephy(tp,
3094 MII_TG3_FET_SHDW_AUXMODE4,
3095 phy);
3096 }
3097 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3098 }
3099 return;
0a459aac 3100 } else if (do_low_power) {
989038e2
NS		 3101 if (!tg3_phy_led_bug(tp))
3102 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3103 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac 3104
b4bd2929
MC		 3105 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3106 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3107 MII_TG3_AUXCTL_PCTL_VREG_11V;
3108 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
715116a1 3109 }
3f7045c1 3110
15c3b696
MC		 3111 /* The PHY should not be powered down on some chips because
3112 * of bugs.
3113 */
44f3b503 3114 if (tg3_phy_power_bug(tp))
15c3b696 3115 return;
ce057f01 3116
4153577a
JP		 3117 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3118 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 3119 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3120 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3121 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3122 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3123 }
3124
15c3b696
MC		 3125 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3126}
3127
ffbcfed4
MC		 3128/* tp->lock is held. */
3129static int tg3_nvram_lock(struct tg3 *tp)
3130{
63c3a66f 3131 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3132 int i;
3133
3134 if (tp->nvram_lock_cnt == 0) {
3135 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3136 for (i = 0; i < 8000; i++) {
3137 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3138 break;
3139 udelay(20);
3140 }
3141 if (i == 8000) {
3142 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3143 return -ENODEV;
3144 }
3145 }
3146 tp->nvram_lock_cnt++;
3147 }
3148 return 0;
3149}
3150
3151/* tp->lock is held. */
3152static void tg3_nvram_unlock(struct tg3 *tp)
3153{
63c3a66f 3154 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3155 if (tp->nvram_lock_cnt > 0)
3156 tp->nvram_lock_cnt--;
3157 if (tp->nvram_lock_cnt == 0)
3158 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3159 }
3160}
3161
3162/* tp->lock is held. */
3163static void tg3_enable_nvram_access(struct tg3 *tp)
3164{
63c3a66f 3165 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3166 u32 nvaccess = tr32(NVRAM_ACCESS);
3167
3168 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3169 }
3170}
3171
3172/* tp->lock is held. */
3173static void tg3_disable_nvram_access(struct tg3 *tp)
3174{
63c3a66f 3175 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3176 u32 nvaccess = tr32(NVRAM_ACCESS);
3177
3178 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3179 }
3180}
3181
3182static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3183 u32 offset, u32 *val)
3184{
3185 u32 tmp;
3186 int i;
3187
3188 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3189 return -EINVAL;
3190
3191 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3192 EEPROM_ADDR_DEVID_MASK |
3193 EEPROM_ADDR_READ);
3194 tw32(GRC_EEPROM_ADDR,
3195 tmp |
3196 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3197 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3198 EEPROM_ADDR_ADDR_MASK) |
3199 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3200
3201 for (i = 0; i < 1000; i++) {
3202 tmp = tr32(GRC_EEPROM_ADDR);
3203
3204 if (tmp & EEPROM_ADDR_COMPLETE)
3205 break;
3206 msleep(1);
3207 }
3208 if (!(tmp & EEPROM_ADDR_COMPLETE))
3209 return -EBUSY;
3210
62cedd11
MC		 3211 tmp = tr32(GRC_EEPROM_DATA);
3212
3213 /*
3214 * The data will always be opposite the native endian
3215 * format. Perform a blind byteswap to compensate.
3216 */
3217 *val = swab32(tmp);
3218
ffbcfed4
MC		 3219 return 0;
3220}
3221
3222#define NVRAM_CMD_TIMEOUT 10000
3223
3224static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3225{
3226 int i;
3227
3228 tw32(NVRAM_CMD, nvram_cmd);
3229 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3230 udelay(10);
3231 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3232 udelay(10);
3233 break;
3234 }
3235 }
3236
3237 if (i == NVRAM_CMD_TIMEOUT)
3238 return -EBUSY;
3239
3240 return 0;
3241}
3242
3243static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3244{
63c3a66f
JP		 3245 if (tg3_flag(tp, NVRAM) &&
3246 tg3_flag(tp, NVRAM_BUFFERED) &&
3247 tg3_flag(tp, FLASH) &&
3248 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3249 (tp->nvram_jedecnum == JEDEC_ATMEL))
3250
3251 addr = ((addr / tp->nvram_pagesize) <<
3252 ATMEL_AT45DB0X1B_PAGE_POS) +
3253 (addr % tp->nvram_pagesize);
3254
3255 return addr;
3256}
3257
3258static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3259{
63c3a66f
JP		 3260 if (tg3_flag(tp, NVRAM) &&
3261 tg3_flag(tp, NVRAM_BUFFERED) &&
3262 tg3_flag(tp, FLASH) &&
3263 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3264 (tp->nvram_jedecnum == JEDEC_ATMEL))
3265
3266 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3267 tp->nvram_pagesize) +
3268 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3269
3270 return addr;
3271}
3272
e4f34110
MC		 3273/* NOTE: Data read in from NVRAM is byteswapped according to
3274 * the byteswapping settings for all other register accesses.
3275 * tg3 devices are BE devices, so on a BE machine, the data
3276 * returned will be exactly as it is seen in NVRAM. On a LE
3277 * machine, the 32-bit value will be byteswapped.
3278 */
ffbcfed4
MC		 3279static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3280{
3281 int ret;
3282
63c3a66f 3283 if (!tg3_flag(tp, NVRAM))
ffbcfed4
MC		 3284 return tg3_nvram_read_using_eeprom(tp, offset, val);
3285
3286 offset = tg3_nvram_phys_addr(tp, offset);
3287
3288 if (offset > NVRAM_ADDR_MSK)
3289 return -EINVAL;
3290
3291 ret = tg3_nvram_lock(tp);
3292 if (ret)
3293 return ret;
3294
3295 tg3_enable_nvram_access(tp);
3296
3297 tw32(NVRAM_ADDR, offset);
3298 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3299 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3300
3301 if (ret == 0)
e4f34110 3302 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 3303
3304 tg3_disable_nvram_access(tp);
3305
3306 tg3_nvram_unlock(tp);
3307
3308 return ret;
3309}
3310
a9dc529d
MC		 3311/* Ensures NVRAM data is in bytestream format. */
3312static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 3313{
3314 u32 v;
a9dc529d 3315 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 3316 if (!res)
a9dc529d 3317 *val = cpu_to_be32(v);
ffbcfed4
MC		 3318 return res;
3319}
3320
dbe9b92a
MC		 3321static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3322 u32 offset, u32 len, u8 *buf)
3323{
3324 int i, j, rc = 0;
3325 u32 val;
3326
3327 for (i = 0; i < len; i += 4) {
3328 u32 addr;
3329 __be32 data;
3330
3331 addr = offset + i;
3332
3333 memcpy(&data, buf + i, 4);
3334
3335 /*
3336 * The SEEPROM interface expects the data to always be opposite
3337 * the native endian format. We accomplish this by reversing
3338 * all the operations that would have been performed on the
3339 * data from a call to tg3_nvram_read_be32().
3340 */
3341 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3342
3343 val = tr32(GRC_EEPROM_ADDR);
3344 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3345
3346 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3347 EEPROM_ADDR_READ);
3348 tw32(GRC_EEPROM_ADDR, val |
3349 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3350 (addr & EEPROM_ADDR_ADDR_MASK) |
3351 EEPROM_ADDR_START |
3352 EEPROM_ADDR_WRITE);
3353
3354 for (j = 0; j < 1000; j++) {
3355 val = tr32(GRC_EEPROM_ADDR);
3356
3357 if (val & EEPROM_ADDR_COMPLETE)
3358 break;
3359 msleep(1);
3360 }
3361 if (!(val & EEPROM_ADDR_COMPLETE)) {
3362 rc = -EBUSY;
3363 break;
3364 }
3365 }
3366
3367 return rc;
3368}
3369
3370/* offset and length are dword aligned */
3371static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3372 u8 *buf)
3373{
3374 int ret = 0;
3375 u32 pagesize = tp->nvram_pagesize;
3376 u32 pagemask = pagesize - 1;
3377 u32 nvram_cmd;
3378 u8 *tmp;
3379
3380 tmp = kmalloc(pagesize, GFP_KERNEL);
3381 if (tmp == NULL)
3382 return -ENOMEM;
3383
3384 while (len) {
3385 int j;
3386 u32 phy_addr, page_off, size;
3387
3388 phy_addr = offset & ~pagemask;
3389
3390 for (j = 0; j < pagesize; j += 4) {
3391 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3392 (__be32 *) (tmp + j));
3393 if (ret)
3394 break;
3395 }
3396 if (ret)
3397 break;
3398
3399 page_off = offset & pagemask;
3400 size = pagesize;
3401 if (len < size)
3402 size = len;
3403
3404 len -= size;
3405
3406 memcpy(tmp + page_off, buf, size);
3407
3408 offset = offset + (pagesize - page_off);
3409
3410 tg3_enable_nvram_access(tp);
3411
3412 /*
3413 * Before we can erase the flash page, we need
3414 * to issue a special "write enable" command.
3415 */
3416 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3417
3418 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3419 break;
3420
3421 /* Erase the target page */
3422 tw32(NVRAM_ADDR, phy_addr);
3423
3424 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3425 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3426
3427 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3428 break;
3429
3430 /* Issue another write enable to start the write. */
3431 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3432
3433 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3434 break;
3435
3436 for (j = 0; j < pagesize; j += 4) {
3437 __be32 data;
3438
3439 data = *((__be32 *) (tmp + j));
3440
3441 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3442
3443 tw32(NVRAM_ADDR, phy_addr + j);
3444
3445 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3446 NVRAM_CMD_WR;
3447
3448 if (j == 0)
3449 nvram_cmd |= NVRAM_CMD_FIRST;
3450 else if (j == (pagesize - 4))
3451 nvram_cmd |= NVRAM_CMD_LAST;
3452
3453 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3454 if (ret)
3455 break;
3456 }
3457 if (ret)
3458 break;
3459 }
3460
3461 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3462 tg3_nvram_exec_cmd(tp, nvram_cmd);
3463
3464 kfree(tmp);
3465
3466 return ret;
3467}
3468
3469/* offset and length are dword aligned */
3470static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3471 u8 *buf)
3472{
3473 int i, ret = 0;
3474
3475 for (i = 0; i < len; i += 4, offset += 4) {
3476 u32 page_off, phy_addr, nvram_cmd;
3477 __be32 data;
3478
3479 memcpy(&data, buf + i, 4);
3480 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3481
3482 page_off = offset % tp->nvram_pagesize;
3483
3484 phy_addr = tg3_nvram_phys_addr(tp, offset);
3485
dbe9b92a
MC		 3486 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3487
3488 if (page_off == 0 || i == 0)
3489 nvram_cmd |= NVRAM_CMD_FIRST;
3490 if (page_off == (tp->nvram_pagesize - 4))
3491 nvram_cmd |= NVRAM_CMD_LAST;
3492
3493 if (i == (len - 4))
3494 nvram_cmd |= NVRAM_CMD_LAST;
3495
42278224
MC		 3496 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3497 !tg3_flag(tp, FLASH) ||
3498 !tg3_flag(tp, 57765_PLUS))
3499 tw32(NVRAM_ADDR, phy_addr);
3500
4153577a 3501 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
dbe9b92a
MC		 3502 !tg3_flag(tp, 5755_PLUS) &&
3503 (tp->nvram_jedecnum == JEDEC_ST) &&
3504 (nvram_cmd & NVRAM_CMD_FIRST)) {
3505 u32 cmd;
3506
3507 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3508 ret = tg3_nvram_exec_cmd(tp, cmd);
3509 if (ret)
3510 break;
3511 }
3512 if (!tg3_flag(tp, FLASH)) {
3513 /* We always do complete word writes to eeprom. */
3514 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3515 }
3516
3517 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3518 if (ret)
3519 break;
3520 }
3521 return ret;
3522}
3523
3524/* offset and length are dword aligned */
3525static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3526{
3527 int ret;
3528
3529 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3530 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3531 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3532 udelay(40);
3533 }
3534
3535 if (!tg3_flag(tp, NVRAM)) {
3536 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3537 } else {
3538 u32 grc_mode;
3539
3540 ret = tg3_nvram_lock(tp);
3541 if (ret)
3542 return ret;
3543
3544 tg3_enable_nvram_access(tp);
3545 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3546 tw32(NVRAM_WRITE1, 0x406);
3547
3548 grc_mode = tr32(GRC_MODE);
3549 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3550
3551 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3552 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3553 buf);
3554 } else {
3555 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3556 buf);
3557 }
3558
3559 grc_mode = tr32(GRC_MODE);
3560 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3561
3562 tg3_disable_nvram_access(tp);
3563 tg3_nvram_unlock(tp);
3564 }
3565
3566 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3567 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3568 udelay(40);
3569 }
3570
3571 return ret;
3572}
3573
997b4f13
MC		 3574#define RX_CPU_SCRATCH_BASE 0x30000
3575#define RX_CPU_SCRATCH_SIZE 0x04000
3576#define TX_CPU_SCRATCH_BASE 0x34000
3577#define TX_CPU_SCRATCH_SIZE 0x04000
3578
3579/* tp->lock is held. */
837c45bb 3580static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
997b4f13
MC		 3581{
3582 int i;
837c45bb 3583 const int iters = 10000;
997b4f13 3584
837c45bb
NS		 3585 for (i = 0; i < iters; i++) {
3586 tw32(cpu_base + CPU_STATE, 0xffffffff);
3587 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3588 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3589 break;
6d446ec3
GS		 3590 if (pci_channel_offline(tp->pdev))
3591 return -EBUSY;
837c45bb
NS		 3592 }
3593
3594 return (i == iters) ? -EBUSY : 0;
3595}
3596
3597/* tp->lock is held. */
3598static int tg3_rxcpu_pause(struct tg3 *tp)
3599{
3600 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3601
3602 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3603 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3604 udelay(10);
3605
3606 return rc;
3607}
3608
3609/* tp->lock is held. */
3610static int tg3_txcpu_pause(struct tg3 *tp)
3611{
3612 return tg3_pause_cpu(tp, TX_CPU_BASE);
3613}
3614
3615/* tp->lock is held. */
3616static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3617{
3618 tw32(cpu_base + CPU_STATE, 0xffffffff);
3619 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3620}
3621
3622/* tp->lock is held. */
3623static void tg3_rxcpu_resume(struct tg3 *tp)
3624{
3625 tg3_resume_cpu(tp, RX_CPU_BASE);
3626}
3627
3628/* tp->lock is held. */
3629static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3630{
3631 int rc;
3632
3633 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
997b4f13 3634
4153577a 3635 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
997b4f13
MC		 3636 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3637
3638 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3639 return 0;
3640 }
837c45bb
NS		 3641 if (cpu_base == RX_CPU_BASE) {
3642 rc = tg3_rxcpu_pause(tp);
997b4f13 3643 } else {
7e6c63f0
HM		 3644 /*
3645 * There is only an Rx CPU for the 5750 derivative in the
3646 * BCM4785.
3647 */
3648 if (tg3_flag(tp, IS_SSB_CORE))
3649 return 0;
3650
837c45bb 3651 rc = tg3_txcpu_pause(tp);
997b4f13
MC		 3652 }
3653
837c45bb 3654 if (rc) {
997b4f13 3655 netdev_err(tp->dev, "%s timed out, %s CPU\n",
837c45bb 3656 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
997b4f13
MC		 3657 return -ENODEV;
3658 }
3659
3660 /* Clear firmware's nvram arbitration. */
3661 if (tg3_flag(tp, NVRAM))
3662 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3663 return 0;
3664}
3665
31f11a95
NS		 3666static int tg3_fw_data_len(struct tg3 *tp,
3667 const struct tg3_firmware_hdr *fw_hdr)
3668{
3669 int fw_len;
3670
3671 /* Non fragmented firmware have one firmware header followed by a
3672 * contiguous chunk of data to be written. The length field in that
3673 * header is not the length of data to be written but the complete
3674 * length of the bss. The data length is determined based on
3675 * tp->fw->size minus headers.
3676 *
3677 * Fragmented firmware have a main header followed by multiple
3678 * fragments. Each fragment is identical to non fragmented firmware
3679 * with a firmware header followed by a contiguous chunk of data. In
3680 * the main header, the length field is unused and set to 0xffffffff.
3681 * In each fragment header the length is the entire size of that
3682 * fragment i.e. fragment data + header length. Data length is
3683 * therefore length field in the header minus TG3_FW_HDR_LEN.
3684 */
3685 if (tp->fw_len == 0xffffffff)
3686 fw_len = be32_to_cpu(fw_hdr->len);
3687 else
3688 fw_len = tp->fw->size;
3689
3690 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3691}
3692
997b4f13
MC		 3693/* tp->lock is held. */
3694static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3695 u32 cpu_scratch_base, int cpu_scratch_size,
77997ea3 3696 const struct tg3_firmware_hdr *fw_hdr)
997b4f13 3697{
c4dab506 3698 int err, i;
997b4f13 3699 void (*write_op)(struct tg3 *, u32, u32);
31f11a95 3700 int total_len = tp->fw->size;
997b4f13
MC		 3701
3702 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3703 netdev_err(tp->dev,
3704 "%s: Trying to load TX cpu firmware which is 5705\n",
3705 __func__);
3706 return -EINVAL;
3707 }
3708
c4dab506 3709 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
997b4f13
MC		 3710 write_op = tg3_write_mem;
3711 else
3712 write_op = tg3_write_indirect_reg32;
3713
c4dab506
NS		 3714 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3715 /* It is possible that bootcode is still loading at this point.
3716 * Get the nvram lock first before halting the cpu.
3717 */
3718 int lock_err = tg3_nvram_lock(tp);
3719 err = tg3_halt_cpu(tp, cpu_base);
3720 if (!lock_err)
3721 tg3_nvram_unlock(tp);
3722 if (err)
3723 goto out;
997b4f13 3724
c4dab506
NS		 3725 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3726 write_op(tp, cpu_scratch_base + i, 0);
3727 tw32(cpu_base + CPU_STATE, 0xffffffff);
3728 tw32(cpu_base + CPU_MODE,
3729 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3730 } else {
3731 /* Subtract additional main header for fragmented firmware and
3732 * advance to the first fragment
3733 */
3734 total_len -= TG3_FW_HDR_LEN;
3735 fw_hdr++;
3736 }
77997ea3 3737
31f11a95
NS		 3738 do {
3739 u32 *fw_data = (u32 *)(fw_hdr + 1);
3740 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3741 write_op(tp, cpu_scratch_base +
3742 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3743 (i * sizeof(u32)),
3744 be32_to_cpu(fw_data[i]));
3745
3746 total_len -= be32_to_cpu(fw_hdr->len);
3747
3748 /* Advance to next fragment */
3749 fw_hdr = (struct tg3_firmware_hdr *)
3750 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3751 } while (total_len > 0);
997b4f13
MC		 3752
3753 err = 0;
3754
3755out:
3756 return err;
3757}
3758
f4bffb28
NS		 3759/* tp->lock is held. */
3760static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3761{
3762 int i;
3763 const int iters = 5;
3764
3765 tw32(cpu_base + CPU_STATE, 0xffffffff);
3766 tw32_f(cpu_base + CPU_PC, pc);
3767
3768 for (i = 0; i < iters; i++) {
3769 if (tr32(cpu_base + CPU_PC) == pc)
3770 break;
3771 tw32(cpu_base + CPU_STATE, 0xffffffff);
3772 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3773 tw32_f(cpu_base + CPU_PC, pc);
3774 udelay(1000);
3775 }
3776
3777 return (i == iters) ? -EBUSY : 0;
3778}
3779
997b4f13
MC		 3780/* tp->lock is held. */
3781static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3782{
77997ea3 3783 const struct tg3_firmware_hdr *fw_hdr;
f4bffb28 3784 int err;
997b4f13 3785
77997ea3 3786 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3787
3788 /* Firmware blob starts with version numbers, followed by
3789 start address and length. We are setting complete length.
3790 length = end_address_of_bss - start_address_of_text.
3791 Remainder is the blob to be loaded contiguously
3792 from start address. */
3793
997b4f13
MC		 3794 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3795 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
77997ea3 3796 fw_hdr);
997b4f13
MC		 3797 if (err)
3798 return err;
3799
3800 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3801 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
77997ea3 3802 fw_hdr);
997b4f13
MC		 3803 if (err)
3804 return err;
3805
3806 /* Now startup only the RX cpu. */
77997ea3
NS		 3807 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3808 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3809 if (err) {
997b4f13
MC		 3810 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3811 "should be %08x\n", __func__,
77997ea3
NS		 3812 tr32(RX_CPU_BASE + CPU_PC),
3813 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3814 return -ENODEV;
3815 }
837c45bb
NS		 3816
3817 tg3_rxcpu_resume(tp);
997b4f13
MC		 3818
3819 return 0;
3820}
3821
c4dab506
NS		 3822static int tg3_validate_rxcpu_state(struct tg3 *tp)
3823{
3824 const int iters = 1000;
3825 int i;
3826 u32 val;
3827
3828 /* Wait for boot code to complete initialization and enter service
3829 * loop. It is then safe to download service patches
3830 */
3831 for (i = 0; i < iters; i++) {
3832 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3833 break;
3834
3835 udelay(10);
3836 }
3837
3838 if (i == iters) {
3839 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3840 return -EBUSY;
3841 }
3842
3843 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3844 if (val & 0xff) {
3845 netdev_warn(tp->dev,
3846 "Other patches exist. Not downloading EEE patch\n");
3847 return -EEXIST;
3848 }
3849
3850 return 0;
3851}
3852
3853/* tp->lock is held. */
3854static void tg3_load_57766_firmware(struct tg3 *tp)
3855{
3856 struct tg3_firmware_hdr *fw_hdr;
3857
3858 if (!tg3_flag(tp, NO_NVRAM))
3859 return;
3860
3861 if (tg3_validate_rxcpu_state(tp))
3862 return;
3863
3864 if (!tp->fw)
3865 return;
3866
3867 /* This firmware blob has a different format than older firmware
3868 * releases as given below. The main difference is we have fragmented
3869 * data to be written to non-contiguous locations.
3870 *
3871 * In the beginning we have a firmware header identical to other
3872 * firmware which consists of version, base addr and length. The length
3873 * here is unused and set to 0xffffffff.
3874 *
3875 * This is followed by a series of firmware fragments which are
3876 * individually identical to previous firmware. i.e. they have the
3877 * firmware header and followed by data for that fragment. The version
3878 * field of the individual fragment header is unused.
3879 */
3880
3881 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3882 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3883 return;
3884
3885 if (tg3_rxcpu_pause(tp))
3886 return;
3887
3888 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3889 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3890
3891 tg3_rxcpu_resume(tp);
3892}
3893
997b4f13
MC		 3894/* tp->lock is held. */
3895static int tg3_load_tso_firmware(struct tg3 *tp)
3896{
77997ea3 3897 const struct tg3_firmware_hdr *fw_hdr;
997b4f13 3898 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
f4bffb28 3899 int err;
997b4f13 3900
1caf13eb 3901 if (!tg3_flag(tp, FW_TSO))
997b4f13
MC		 3902 return 0;
3903
77997ea3 3904 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3905
3906 /* Firmware blob starts with version numbers, followed by
3907 start address and length. We are setting complete length.
3908 length = end_address_of_bss - start_address_of_text.
3909 Remainder is the blob to be loaded contiguously
3910 from start address. */
3911
997b4f13 3912 cpu_scratch_size = tp->fw_len;
997b4f13 3913
4153577a 3914 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
997b4f13
MC		 3915 cpu_base = RX_CPU_BASE;
3916 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3917 } else {
3918 cpu_base = TX_CPU_BASE;
3919 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3920 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3921 }
3922
3923 err = tg3_load_firmware_cpu(tp, cpu_base,
3924 cpu_scratch_base, cpu_scratch_size,
77997ea3 3925 fw_hdr);
997b4f13
MC		 3926 if (err)
3927 return err;
3928
3929 /* Now startup the cpu. */
77997ea3
NS		 3930 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3931 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3932 if (err) {
997b4f13
MC		 3933 netdev_err(tp->dev,
3934 "%s fails to set CPU PC, is %08x should be %08x\n",
77997ea3
NS		 3935 __func__, tr32(cpu_base + CPU_PC),
3936 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3937 return -ENODEV;
3938 }
837c45bb
NS		 3939
3940 tg3_resume_cpu(tp, cpu_base);
997b4f13
MC		 3941 return 0;
3942}
3943
3944
3f007891 3945/* tp->lock is held. */
953c96e0 3946static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3f007891
MC		 3947{
3948 u32 addr_high, addr_low;
3949 int i;
3950
3951 addr_high = ((tp->dev->dev_addr[0] << 8) |
3952 tp->dev->dev_addr[1]);
3953 addr_low = ((tp->dev->dev_addr[2] << 24) |
3954 (tp->dev->dev_addr[3] << 16) |
3955 (tp->dev->dev_addr[4] << 8) |
3956 (tp->dev->dev_addr[5] << 0));
3957 for (i = 0; i < 4; i++) {
3958 if (i == 1 && skip_mac_1)
3959 continue;
3960 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3961 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3962 }
3963
4153577a
JP		 3964 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3965 tg3_asic_rev(tp) == ASIC_REV_5704) {
3f007891
MC		 3966 for (i = 0; i < 12; i++) {
3967 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3968 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3969 }
3970 }
3971
3972 addr_high = (tp->dev->dev_addr[0] +
3973 tp->dev->dev_addr[1] +
3974 tp->dev->dev_addr[2] +
3975 tp->dev->dev_addr[3] +
3976 tp->dev->dev_addr[4] +
3977 tp->dev->dev_addr[5]) &
3978 TX_BACKOFF_SEED_MASK;
3979 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3980}
3981
c866b7ea 3982static void tg3_enable_register_access(struct tg3 *tp)
1da177e4 3983{
c866b7ea
RW		 3984 /*
3985 * Make sure register accesses (indirect or otherwise) will function
3986 * correctly.
1da177e4
LT		 3987 */
3988 pci_write_config_dword(tp->pdev,
c866b7ea
RW		 3989 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3990}
1da177e4 3991
c866b7ea
RW		 3992static int tg3_power_up(struct tg3 *tp)
3993{
bed9829f 3994 int err;
8c6bda1a 3995
bed9829f 3996 tg3_enable_register_access(tp);
1da177e4 3997
bed9829f
MC		 3998 err = pci_set_power_state(tp->pdev, PCI_D0);
3999 if (!err) {
4000 /* Switch out of Vaux if it is a NIC */
4001 tg3_pwrsrc_switch_to_vmain(tp);
4002 } else {
4003 netdev_err(tp->dev, "Transition to D0 failed\n");
4004 }
1da177e4 4005
bed9829f 4006 return err;
c866b7ea 4007}
1da177e4 4008
953c96e0 4009static int tg3_setup_phy(struct tg3 *, bool);
4b409522 4010
c866b7ea
RW		 4011static int tg3_power_down_prepare(struct tg3 *tp)
4012{
4013 u32 misc_host_ctrl;
4014 bool device_should_wake, do_low_power;
4015
4016 tg3_enable_register_access(tp);
5e7dfd0f
MC		 4017
4018 /* Restore the CLKREQ setting. */
0f49bfbd
JL		 4019 if (tg3_flag(tp, CLKREQ_BUG))
4020 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4021 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 4022
1da177e4
LT		 4023 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4024 tw32(TG3PCI_MISC_HOST_CTRL,
4025 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4026
c866b7ea 4027 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
63c3a66f 4028 tg3_flag(tp, WOL_ENABLE);
05ac4cb7 4029
63c3a66f 4030 if (tg3_flag(tp, USE_PHYLIB)) {
0a459aac 4031 do_low_power = false;
f07e9af3 4032 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
80096068 4033 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
b02fd9e3 4034 struct phy_device *phydev;
0a459aac 4035 u32 phyid, advertising;
b02fd9e3 4036
3f0e3ad7 4037 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 4038
80096068 4039 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
b02fd9e3 4040
c6700ce2
MC		 4041 tp->link_config.speed = phydev->speed;
4042 tp->link_config.duplex = phydev->duplex;
4043 tp->link_config.autoneg = phydev->autoneg;
4044 tp->link_config.advertising = phydev->advertising;
b02fd9e3
MC		 4045
4046 advertising = ADVERTISED_TP |
4047 ADVERTISED_Pause |
4048 ADVERTISED_Autoneg |
4049 ADVERTISED_10baseT_Half;
4050
63c3a66f
JP		 4051 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4052 if (tg3_flag(tp, WOL_SPEED_100MB))
b02fd9e3
MC		 4053 advertising |=
4054 ADVERTISED_100baseT_Half |
4055 ADVERTISED_100baseT_Full |
4056 ADVERTISED_10baseT_Full;
4057 else
4058 advertising |= ADVERTISED_10baseT_Full;
4059 }
4060
4061 phydev->advertising = advertising;
4062
4063 phy_start_aneg(phydev);
0a459aac
MC		 4064
4065 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 4066 if (phyid != PHY_ID_BCMAC131) {
4067 phyid &= PHY_BCM_OUI_MASK;
4068 if (phyid == PHY_BCM_OUI_1 ||
4069 phyid == PHY_BCM_OUI_2 ||
4070 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 4071 do_low_power = true;
4072 }
b02fd9e3 4073 }
dd477003 4074 } else {
2023276e 4075 do_low_power = true;
0a459aac 4076
c6700ce2 4077 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
80096068 4078 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
1da177e4 4079
2855b9fe 4080 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
953c96e0 4081 tg3_setup_phy(tp, false);
1da177e4
LT		 4082 }
4083
4153577a 4084 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 4085 u32 val;
4086
4087 val = tr32(GRC_VCPU_EXT_CTRL);
4088 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
63c3a66f 4089 } else if (!tg3_flag(tp, ENABLE_ASF)) {
6921d201
MC		 4090 int i;
4091 u32 val;
4092
4093 for (i = 0; i < 200; i++) {
4094 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4095 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4096 break;
4097 msleep(1);
4098 }
4099 }
63c3a66f 4100 if (tg3_flag(tp, WOL_CAP))
a85feb8c
GZ		 4101 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4102 WOL_DRV_STATE_SHUTDOWN |
4103 WOL_DRV_WOL |
4104 WOL_SET_MAGIC_PKT);
6921d201 4105
05ac4cb7 4106 if (device_should_wake) {
1da177e4
LT		 4107 u32 mac_mode;
4108
f07e9af3 4109 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
b4bd2929
MC		 4110 if (do_low_power &&
4111 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4112 tg3_phy_auxctl_write(tp,
4113 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4114 MII_TG3_AUXCTL_PCTL_WOL_EN |
4115 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4116 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
dd477003
MC		 4117 udelay(40);
4118 }
1da177e4 4119
f07e9af3 4120 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3f7045c1 4121 mac_mode = MAC_MODE_PORT_MODE_GMII;
942d1af0
NS		 4122 else if (tp->phy_flags &
4123 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4124 if (tp->link_config.active_speed == SPEED_1000)
4125 mac_mode = MAC_MODE_PORT_MODE_GMII;
4126 else
4127 mac_mode = MAC_MODE_PORT_MODE_MII;
4128 } else
3f7045c1 4129 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 4130
e8f3f6ca 4131 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4153577a 4132 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
63c3a66f 4133 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
e8f3f6ca
MC		 4134 SPEED_100 : SPEED_10;
4135 if (tg3_5700_link_polarity(tp, speed))
4136 mac_mode |= MAC_MODE_LINK_POLARITY;
4137 else
4138 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4139 }
1da177e4
LT		 4140 } else {
4141 mac_mode = MAC_MODE_PORT_MODE_TBI;
4142 }
4143
63c3a66f 4144 if (!tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 4145 tw32(MAC_LED_CTRL, tp->led_ctrl);
4146
05ac4cb7 4147 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
63c3a66f
JP		 4148 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4149 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
05ac4cb7 4150 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 4151
63c3a66f 4152 if (tg3_flag(tp, ENABLE_APE))
d2394e6b
MC		 4153 mac_mode |= MAC_MODE_APE_TX_EN |
4154 MAC_MODE_APE_RX_EN |
4155 MAC_MODE_TDE_ENABLE;
3bda1258 4156
1da177e4
LT		 4157 tw32_f(MAC_MODE, mac_mode);
4158 udelay(100);
4159
4160 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4161 udelay(10);
4162 }
4163
63c3a66f 4164 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4153577a
JP		 4165 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4166 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 4167 u32 base_val;
4168
4169 base_val = tp->pci_clock_ctrl;
4170 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4171 CLOCK_CTRL_TXCLK_DISABLE);
4172
b401e9e2
MC		 4173 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4174 CLOCK_CTRL_PWRDOWN_PLL133, 40);
63c3a66f
JP		 4175 } else if (tg3_flag(tp, 5780_CLASS) ||
4176 tg3_flag(tp, CPMU_PRESENT) ||
4153577a 4177 tg3_asic_rev(tp) == ASIC_REV_5906) {
4cf78e4f 4178 /* do nothing */
63c3a66f 4179 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
1da177e4
LT		 4180 u32 newbits1, newbits2;
4181
4153577a
JP		 4182 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4183 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4184 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4185 CLOCK_CTRL_TXCLK_DISABLE |
4186 CLOCK_CTRL_ALTCLK);
4187 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
63c3a66f 4188 } else if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4189 newbits1 = CLOCK_CTRL_625_CORE;
4190 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4191 } else {
4192 newbits1 = CLOCK_CTRL_ALTCLK;
4193 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4194 }
4195
b401e9e2
MC		 4196 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4197 40);
1da177e4 4198
b401e9e2
MC		 4199 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4200 40);
1da177e4 4201
63c3a66f 4202 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4203 u32 newbits3;
4204
4153577a
JP		 4205 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4206 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4207 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4208 CLOCK_CTRL_TXCLK_DISABLE |
4209 CLOCK_CTRL_44MHZ_CORE);
4210 } else {
4211 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4212 }
4213
b401e9e2
MC		 4214 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4215 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 4216 }
4217 }
4218
63c3a66f 4219 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
0a459aac 4220 tg3_power_down_phy(tp, do_low_power);
6921d201 4221
cd0d7228 4222 tg3_frob_aux_power(tp, true);
1da177e4
LT		 4223
4224 /* Workaround for unstable PLL clock */
7e6c63f0 4225 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4153577a
JP		 4226 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4227 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
1da177e4
LT		 4228 u32 val = tr32(0x7d00);
4229
4230 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4231 tw32(0x7d00, val);
63c3a66f 4232 if (!tg3_flag(tp, ENABLE_ASF)) {
ec41c7df
MC		 4233 int err;
4234
4235 err = tg3_nvram_lock(tp);
1da177e4 4236 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 4237 if (!err)
4238 tg3_nvram_unlock(tp);
6921d201 4239 }
1da177e4
LT		 4240 }
4241
bbadf503
MC		 4242 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4243
2e460fc0
NS		 4244 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4245
c866b7ea
RW		 4246 return 0;
4247}
12dac075 4248
c866b7ea
RW		 4249static void tg3_power_down(struct tg3 *tp)
4250{
63c3a66f 4251 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
c866b7ea 4252 pci_set_power_state(tp->pdev, PCI_D3hot);
1da177e4
LT		 4253}
4254
1da177e4
LT		 4255static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4256{
4257 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4258 case MII_TG3_AUX_STAT_10HALF:
4259 *speed = SPEED_10;
4260 *duplex = DUPLEX_HALF;
4261 break;
4262
4263 case MII_TG3_AUX_STAT_10FULL:
4264 *speed = SPEED_10;
4265 *duplex = DUPLEX_FULL;
4266 break;
4267
4268 case MII_TG3_AUX_STAT_100HALF:
4269 *speed = SPEED_100;
4270 *duplex = DUPLEX_HALF;
4271 break;
4272
4273 case MII_TG3_AUX_STAT_100FULL:
4274 *speed = SPEED_100;
4275 *duplex = DUPLEX_FULL;
4276 break;
4277
4278 case MII_TG3_AUX_STAT_1000HALF:
4279 *speed = SPEED_1000;
4280 *duplex = DUPLEX_HALF;
4281 break;
4282
4283 case MII_TG3_AUX_STAT_1000FULL:
4284 *speed = SPEED_1000;
4285 *duplex = DUPLEX_FULL;
4286 break;
4287
4288 default:
f07e9af3 4289 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
715116a1
MC		 4290 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4291 SPEED_10;
4292 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4293 DUPLEX_HALF;
4294 break;
4295 }
e740522e
MC		 4296 *speed = SPEED_UNKNOWN;
4297 *duplex = DUPLEX_UNKNOWN;
1da177e4 4298 break;
855e1111 4299 }
1da177e4
LT		 4300}
4301
42b64a45 4302static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
1da177e4 4303{
42b64a45
MC		 4304 int err = 0;
4305 u32 val, new_adv;
1da177e4 4306
42b64a45 4307 new_adv = ADVERTISE_CSMA;
202ff1c2 4308 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
f88788f0 4309 new_adv |= mii_advertise_flowctrl(flowctrl);
1da177e4 4310
42b64a45
MC		 4311 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4312 if (err)
4313 goto done;
ba4d07a8 4314
4f272096
MC		 4315 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4316 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
ba4d07a8 4317
4153577a
JP		 4318 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4319 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4f272096 4320 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
ba4d07a8 4321
4f272096
MC		 4322 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4323 if (err)
4324 goto done;
4325 }
1da177e4 4326
42b64a45
MC		 4327 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4328 goto done;
52b02d04 4329
42b64a45
MC		 4330 tw32(TG3_CPMU_EEE_MODE,
4331 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
52b02d04 4332
daf3ec68 4333 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
42b64a45
MC		 4334 if (!err) {
4335 u32 err2;
52b02d04 4336
b715ce94
MC		 4337 val = 0;
4338 /* Advertise 100-BaseTX EEE ability */
4339 if (advertise & ADVERTISED_100baseT_Full)
4340 val |= MDIO_AN_EEE_ADV_100TX;
4341 /* Advertise 1000-BaseT EEE ability */
4342 if (advertise & ADVERTISED_1000baseT_Full)
4343 val |= MDIO_AN_EEE_ADV_1000T;
9e2ecbeb
NS		 4344
4345 if (!tp->eee.eee_enabled) {
4346 val = 0;
4347 tp->eee.advertised = 0;
4348 } else {
4349 tp->eee.advertised = advertise &
4350 (ADVERTISED_100baseT_Full |
4351 ADVERTISED_1000baseT_Full);
4352 }
4353
b715ce94
MC		 4354 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4355 if (err)
4356 val = 0;
4357
4153577a 4358 switch (tg3_asic_rev(tp)) {
21a00ab2
MC		 4359 case ASIC_REV_5717:
4360 case ASIC_REV_57765:
55086ad9 4361 case ASIC_REV_57766:
21a00ab2 4362 case ASIC_REV_5719:
b715ce94
MC		 4363 /* If we advertised any eee advertisements above... */
4364 if (val)
4365 val = MII_TG3_DSP_TAP26_ALNOKO |
4366 MII_TG3_DSP_TAP26_RMRXSTO |
4367 MII_TG3_DSP_TAP26_OPCSINPT;
21a00ab2 4368 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
be671947
MC		 4369 /* Fall through */
4370 case ASIC_REV_5720:
c65a17f4 4371 case ASIC_REV_5762:
be671947
MC		 4372 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4373 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4374 MII_TG3_DSP_CH34TP2_HIBW01);
21a00ab2 4375 }
52b02d04 4376
daf3ec68 4377 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
42b64a45
MC		 4378 if (!err)
4379 err = err2;
4380 }
4381
4382done:
4383 return err;
4384}
4385
4386static void tg3_phy_copper_begin(struct tg3 *tp)
4387{
d13ba512
MC		 4388 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4389 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4390 u32 adv, fc;
4391
942d1af0
NS		 4392 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4393 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
d13ba512
MC		 4394 adv = ADVERTISED_10baseT_Half |
4395 ADVERTISED_10baseT_Full;
4396 if (tg3_flag(tp, WOL_SPEED_100MB))
4397 adv |= ADVERTISED_100baseT_Half |
4398 ADVERTISED_100baseT_Full;
942d1af0
NS		 4399 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK)
4400 adv |= ADVERTISED_1000baseT_Half |
4401 ADVERTISED_1000baseT_Full;
d13ba512
MC		 4402
4403 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
42b64a45 4404 } else {
d13ba512
MC		 4405 adv = tp->link_config.advertising;
4406 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4407 adv &= ~(ADVERTISED_1000baseT_Half |
4408 ADVERTISED_1000baseT_Full);
4409
4410 fc = tp->link_config.flowctrl;
52b02d04 4411 }
52b02d04 4412
d13ba512 4413 tg3_phy_autoneg_cfg(tp, adv, fc);
52b02d04 4414
942d1af0
NS		 4415 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4416 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4417 /* Normally during power down we want to autonegotiate
4418 * the lowest possible speed for WOL. However, to avoid
4419 * link flap, we leave it untouched.
4420 */
4421 return;
4422 }
4423
d13ba512
MC		 4424 tg3_writephy(tp, MII_BMCR,
4425 BMCR_ANENABLE | BMCR_ANRESTART);
4426 } else {
4427 int i;
1da177e4
LT		 4428 u32 bmcr, orig_bmcr;
4429
4430 tp->link_config.active_speed = tp->link_config.speed;
4431 tp->link_config.active_duplex = tp->link_config.duplex;
4432
7c6cdead
NS		 4433 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4434 /* With autoneg disabled, 5715 only links up when the
4435 * advertisement register has the configured speed
4436 * enabled.
4437 */
4438 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4439 }
4440
1da177e4
LT		 4441 bmcr = 0;
4442 switch (tp->link_config.speed) {
4443 default:
4444 case SPEED_10:
4445 break;
4446
4447 case SPEED_100:
4448 bmcr |= BMCR_SPEED100;
4449 break;
4450
4451 case SPEED_1000:
221c5637 4452 bmcr |= BMCR_SPEED1000;
1da177e4 4453 break;
855e1111 4454 }
1da177e4
LT		 4455
4456 if (tp->link_config.duplex == DUPLEX_FULL)
4457 bmcr |= BMCR_FULLDPLX;
4458
4459 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4460 (bmcr != orig_bmcr)) {
4461 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4462 for (i = 0; i < 1500; i++) {
4463 u32 tmp;
4464
4465 udelay(10);
4466 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4467 tg3_readphy(tp, MII_BMSR, &tmp))
4468 continue;
4469 if (!(tmp & BMSR_LSTATUS)) {
4470 udelay(40);
4471 break;
4472 }
4473 }
4474 tg3_writephy(tp, MII_BMCR, bmcr);
4475 udelay(40);
4476 }
1da177e4
LT		 4477 }
4478}
4479
fdad8de4
NS		 4480static int tg3_phy_pull_config(struct tg3 *tp)
4481{
4482 int err;
4483 u32 val;
4484
4485 err = tg3_readphy(tp, MII_BMCR, &val);
4486 if (err)
4487 goto done;
4488
4489 if (!(val & BMCR_ANENABLE)) {
4490 tp->link_config.autoneg = AUTONEG_DISABLE;
4491 tp->link_config.advertising = 0;
4492 tg3_flag_clear(tp, PAUSE_AUTONEG);
4493
4494 err = -EIO;
4495
4496 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4497 case 0:
4498 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4499 goto done;
4500
4501 tp->link_config.speed = SPEED_10;
4502 break;
4503 case BMCR_SPEED100:
4504 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4505 goto done;
4506
4507 tp->link_config.speed = SPEED_100;
4508 break;
4509 case BMCR_SPEED1000:
4510 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4511 tp->link_config.speed = SPEED_1000;
4512 break;
4513 }
4514 /* Fall through */
4515 default:
4516 goto done;
4517 }
4518
4519 if (val & BMCR_FULLDPLX)
4520 tp->link_config.duplex = DUPLEX_FULL;
4521 else
4522 tp->link_config.duplex = DUPLEX_HALF;
4523
4524 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4525
4526 err = 0;
4527 goto done;
4528 }
4529
4530 tp->link_config.autoneg = AUTONEG_ENABLE;
4531 tp->link_config.advertising = ADVERTISED_Autoneg;
4532 tg3_flag_set(tp, PAUSE_AUTONEG);
4533
4534 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4535 u32 adv;
4536
4537 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4538 if (err)
4539 goto done;
4540
4541 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4542 tp->link_config.advertising |= adv | ADVERTISED_TP;
4543
4544 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4545 } else {
4546 tp->link_config.advertising |= ADVERTISED_FIBRE;
4547 }
4548
4549 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4550 u32 adv;
4551
4552 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4553 err = tg3_readphy(tp, MII_CTRL1000, &val);
4554 if (err)
4555 goto done;
4556
4557 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4558 } else {
4559 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4560 if (err)
4561 goto done;
4562
4563 adv = tg3_decode_flowctrl_1000X(val);
4564 tp->link_config.flowctrl = adv;
4565
4566 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4567 adv = mii_adv_to_ethtool_adv_x(val);
4568 }
4569
4570 tp->link_config.advertising |= adv;
4571 }
4572
4573done:
4574 return err;
4575}
4576
1da177e4
LT		 4577static int tg3_init_5401phy_dsp(struct tg3 *tp)
4578{
4579 int err;
4580
4581 /* Turn off tap power management. */
4582 /* Set Extended packet length bit */
b4bd2929 4583 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
1da177e4 4584
6ee7c0a0
MC		 4585 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4586 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4587 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4588 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4589 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
1da177e4
LT		 4590
4591 udelay(40);
4592
4593 return err;
4594}
4595
ed1ff5c3
NS		 4596static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4597{
5b6c273a 4598 struct ethtool_eee eee;
ed1ff5c3
NS		 4599
4600 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4601 return true;
4602
5b6c273a 4603 tg3_eee_pull_config(tp, &eee);
ed1ff5c3 4604
5b6c273a
NS		 4605 if (tp->eee.eee_enabled) {
4606 if (tp->eee.advertised != eee.advertised ||
4607 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4608 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4609 return false;
4610 } else {
4611 /* EEE is disabled but we're advertising */
4612 if (eee.advertised)
4613 return false;
4614 }
ed1ff5c3
NS		 4615
4616 return true;
4617}
4618
e2bf73e7 4619static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
1da177e4 4620{
e2bf73e7 4621 u32 advmsk, tgtadv, advertising;
3600d918 4622
e2bf73e7
MC		 4623 advertising = tp->link_config.advertising;
4624 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
1da177e4 4625
e2bf73e7
MC		 4626 advmsk = ADVERTISE_ALL;
4627 if (tp->link_config.active_duplex == DUPLEX_FULL) {
f88788f0 4628 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
e2bf73e7
MC		 4629 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4630 }
1da177e4 4631
e2bf73e7
MC		 4632 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4633 return false;
4634
4635 if ((*lcladv & advmsk) != tgtadv)
4636 return false;
b99d2a57 4637
f07e9af3 4638 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1da177e4
LT		 4639 u32 tg3_ctrl;
4640
e2bf73e7 4641 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
3600d918 4642
221c5637 4643 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
e2bf73e7 4644 return false;
1da177e4 4645
3198e07f 4646 if (tgtadv &&
4153577a
JP		 4647 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4648 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
3198e07f
MC		 4649 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4650 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4651 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4652 } else {
4653 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4654 }
4655
e2bf73e7
MC		 4656 if (tg3_ctrl != tgtadv)
4657 return false;
ef167e27
MC		 4658 }
4659
e2bf73e7 4660 return true;
ef167e27
MC		 4661}
4662
859edb26
MC		 4663static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4664{
4665 u32 lpeth = 0;
4666
4667 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4668 u32 val;
4669
4670 if (tg3_readphy(tp, MII_STAT1000, &val))
4671 return false;
4672
4673 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4674 }
4675
4676 if (tg3_readphy(tp, MII_LPA, rmtadv))
4677 return false;
4678
4679 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4680 tp->link_config.rmt_adv = lpeth;
4681
4682 return true;
4683}
4684
953c96e0 4685static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
f4a46d1f
NNS		 4686{
4687 if (curr_link_up != tp->link_up) {
4688 if (curr_link_up) {
84421b99 4689 netif_carrier_on(tp->dev);
f4a46d1f 4690 } else {
84421b99 4691 netif_carrier_off(tp->dev);
f4a46d1f
NNS		 4692 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4693 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4694 }
4695
4696 tg3_link_report(tp);
4697 return true;
4698 }
4699
4700 return false;
4701}
4702
3310e248
MC		 4703static void tg3_clear_mac_status(struct tg3 *tp)
4704{
4705 tw32(MAC_EVENT, 0);
4706
4707 tw32_f(MAC_STATUS,
4708 MAC_STATUS_SYNC_CHANGED |
4709 MAC_STATUS_CFG_CHANGED |
4710 MAC_STATUS_MI_COMPLETION |
4711 MAC_STATUS_LNKSTATE_CHANGED);
4712 udelay(40);
4713}
4714
9e2ecbeb
NS		 4715static void tg3_setup_eee(struct tg3 *tp)
4716{
4717 u32 val;
4718
4719 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4720 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4721 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4722 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4723
4724 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4725
4726 tw32_f(TG3_CPMU_EEE_CTRL,
4727 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4728
4729 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4730 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4731 TG3_CPMU_EEEMD_LPI_IN_RX |
4732 TG3_CPMU_EEEMD_EEE_ENABLE;
4733
4734 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4735 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4736
4737 if (tg3_flag(tp, ENABLE_APE))
4738 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4739
4740 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4741
4742 tw32_f(TG3_CPMU_EEE_DBTMR1,
4743 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4744 (tp->eee.tx_lpi_timer & 0xffff));
4745
4746 tw32_f(TG3_CPMU_EEE_DBTMR2,
4747 TG3_CPMU_DBTMR2_APE_TX_2047US |
4748 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4749}
4750
953c96e0 4751static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
1da177e4 4752{
953c96e0 4753 bool current_link_up;
f833c4c1 4754 u32 bmsr, val;
ef167e27 4755 u32 lcl_adv, rmt_adv;
1da177e4
LT		 4756 u16 current_speed;
4757 u8 current_duplex;
4758 int i, err;
4759
3310e248 4760 tg3_clear_mac_status(tp);
1da177e4 4761
8ef21428
MC		 4762 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4763 tw32_f(MAC_MI_MODE,
4764 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4765 udelay(80);
4766 }
1da177e4 4767
b4bd2929 4768 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
1da177e4
LT		 4769
4770 /* Some third-party PHYs need to be reset on link going
4771 * down.
4772 */
4153577a
JP		 4773 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4774 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4775 tg3_asic_rev(tp) == ASIC_REV_5705) &&
f4a46d1f 4776 tp->link_up) {
1da177e4
LT		 4777 tg3_readphy(tp, MII_BMSR, &bmsr);
4778 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4779 !(bmsr & BMSR_LSTATUS))
953c96e0 4780 force_reset = true;
1da177e4
LT		 4781 }
4782 if (force_reset)
4783 tg3_phy_reset(tp);
4784
79eb6904 4785 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 4786 tg3_readphy(tp, MII_BMSR, &bmsr);
4787 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
63c3a66f 4788 !tg3_flag(tp, INIT_COMPLETE))
1da177e4
LT		 4789 bmsr = 0;
4790
4791 if (!(bmsr & BMSR_LSTATUS)) {
4792 err = tg3_init_5401phy_dsp(tp);
4793 if (err)
4794 return err;
4795
4796 tg3_readphy(tp, MII_BMSR, &bmsr);
4797 for (i = 0; i < 1000; i++) {
4798 udelay(10);
4799 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4800 (bmsr & BMSR_LSTATUS)) {
4801 udelay(40);
4802 break;
4803 }
4804 }
4805
79eb6904
MC		 4806 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4807 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 4808 !(bmsr & BMSR_LSTATUS) &&
4809 tp->link_config.active_speed == SPEED_1000) {
4810 err = tg3_phy_reset(tp);
4811 if (!err)
4812 err = tg3_init_5401phy_dsp(tp);
4813 if (err)
4814 return err;
4815 }
4816 }
4153577a
JP		 4817 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4818 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
1da177e4
LT		 4819 /* 5701 {A0,B0} CRC bug workaround */
4820 tg3_writephy(tp, 0x15, 0x0a75);
f08aa1a8
MC		 4821 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4822 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4823 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
1da177e4
LT		 4824 }
4825
4826 /* Clear pending interrupts... */
f833c4c1
MC		 4827 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4828 tg3_readphy(tp, MII_TG3_ISTAT, &val);
1da177e4 4829
f07e9af3 4830 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
1da177e4 4831 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
f07e9af3 4832 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
1da177e4
LT		 4833 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4834
4153577a
JP		 4835 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4836 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4837 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4838 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4839 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4840 else
4841 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4842 }
4843
953c96e0 4844 current_link_up = false;
e740522e
MC		 4845 current_speed = SPEED_UNKNOWN;
4846 current_duplex = DUPLEX_UNKNOWN;
e348c5e7 4847 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
859edb26 4848 tp->link_config.rmt_adv = 0;
1da177e4 4849
f07e9af3 4850 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
15ee95c3
MC		 4851 err = tg3_phy_auxctl_read(tp,
4852 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4853 &val);
4854 if (!err && !(val & (1 << 10))) {
b4bd2929
MC		 4855 tg3_phy_auxctl_write(tp,
4856 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4857 val | (1 << 10));
1da177e4
LT		 4858 goto relink;
4859 }
4860 }
4861
4862 bmsr = 0;
4863 for (i = 0; i < 100; i++) {
4864 tg3_readphy(tp, MII_BMSR, &bmsr);
4865 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4866 (bmsr & BMSR_LSTATUS))
4867 break;
4868 udelay(40);
4869 }
4870
4871 if (bmsr & BMSR_LSTATUS) {
4872 u32 aux_stat, bmcr;
4873
4874 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4875 for (i = 0; i < 2000; i++) {
4876 udelay(10);
4877 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4878 aux_stat)
4879 break;
4880 }
4881
4882 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4883 &current_speed,
4884 &current_duplex);
4885
4886 bmcr = 0;
4887 for (i = 0; i < 200; i++) {
4888 tg3_readphy(tp, MII_BMCR, &bmcr);
4889 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4890 continue;
4891 if (bmcr && bmcr != 0x7fff)
4892 break;
4893 udelay(10);
4894 }
4895
ef167e27
MC		 4896 lcl_adv = 0;
4897 rmt_adv = 0;
1da177e4 4898
ef167e27
MC		 4899 tp->link_config.active_speed = current_speed;
4900 tp->link_config.active_duplex = current_duplex;
4901
4902 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
ed1ff5c3
NS		 4903 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4904
ef167e27 4905 if ((bmcr & BMCR_ANENABLE) &&
ed1ff5c3 4906 eee_config_ok &&
e2bf73e7 4907 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
859edb26 4908 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
953c96e0 4909 current_link_up = true;
ed1ff5c3
NS		 4910
4911 /* EEE settings changes take effect only after a phy
4912 * reset. If we have skipped a reset due to Link Flap
4913 * Avoidance being enabled, do it now.
4914 */
4915 if (!eee_config_ok &&
4916 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
5b6c273a
NS		 4917 !force_reset) {
4918 tg3_setup_eee(tp);
ed1ff5c3 4919 tg3_phy_reset(tp);
5b6c273a 4920 }
1da177e4
LT		 4921 } else {
4922 if (!(bmcr & BMCR_ANENABLE) &&
4923 tp->link_config.speed == current_speed &&
f0fcd7a9 4924 tp->link_config.duplex == current_duplex) {
953c96e0 4925 current_link_up = true;
1da177e4
LT		 4926 }
4927 }
4928
953c96e0 4929 if (current_link_up &&
e348c5e7
MC		 4930 tp->link_config.active_duplex == DUPLEX_FULL) {
4931 u32 reg, bit;
4932
4933 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4934 reg = MII_TG3_FET_GEN_STAT;
4935 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4936 } else {
4937 reg = MII_TG3_EXT_STAT;
4938 bit = MII_TG3_EXT_STAT_MDIX;
4939 }
4940
4941 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4942 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4943
ef167e27 4944 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
e348c5e7 4945 }
1da177e4
LT		 4946 }
4947
1da177e4 4948relink:
953c96e0 4949 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
1da177e4
LT		 4950 tg3_phy_copper_begin(tp);
4951
7e6c63f0 4952 if (tg3_flag(tp, ROBOSWITCH)) {
953c96e0 4953 current_link_up = true;
7e6c63f0
HM		 4954 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4955 current_speed = SPEED_1000;
4956 current_duplex = DUPLEX_FULL;
4957 tp->link_config.active_speed = current_speed;
4958 tp->link_config.active_duplex = current_duplex;
4959 }
4960
f833c4c1 4961 tg3_readphy(tp, MII_BMSR, &bmsr);
06c03c02
MB		 4962 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4963 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
953c96e0 4964 current_link_up = true;
1da177e4
LT		 4965 }
4966
4967 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
953c96e0 4968 if (current_link_up) {
1da177e4
LT		 4969 if (tp->link_config.active_speed == SPEED_100 ||
4970 tp->link_config.active_speed == SPEED_10)
4971 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4972 else
4973 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
f07e9af3 4974 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7f97a4bd
MC		 4975 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4976 else
1da177e4
LT		 4977 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4978
7e6c63f0
HM		 4979 /* In order for the 5750 core in BCM4785 chip to work properly
4980 * in RGMII mode, the Led Control Register must be set up.
4981 */
4982 if (tg3_flag(tp, RGMII_MODE)) {
4983 u32 led_ctrl = tr32(MAC_LED_CTRL);
4984 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
4985
4986 if (tp->link_config.active_speed == SPEED_10)
4987 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
4988 else if (tp->link_config.active_speed == SPEED_100)
4989 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
4990 LED_CTRL_100MBPS_ON);
4991 else if (tp->link_config.active_speed == SPEED_1000)
4992 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
4993 LED_CTRL_1000MBPS_ON);
4994
4995 tw32(MAC_LED_CTRL, led_ctrl);
4996 udelay(40);
4997 }
4998
1da177e4
LT		 4999 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5000 if (tp->link_config.active_duplex == DUPLEX_HALF)
5001 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5002
4153577a 5003 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
953c96e0 5004 if (current_link_up &&
e8f3f6ca 5005 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 5006 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 5007 else
5008 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 5009 }
5010
5011 /* ??? Without this setting Netgear GA302T PHY does not
5012 * ??? send/receive packets...
5013 */
79eb6904 5014 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4153577a 5015 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
1da177e4
LT		 5016 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5017 tw32_f(MAC_MI_MODE, tp->mi_mode);
5018 udelay(80);
5019 }
5020
5021 tw32_f(MAC_MODE, tp->mac_mode);
5022 udelay(40);
5023
52b02d04
MC		 5024 tg3_phy_eee_adjust(tp, current_link_up);
5025
63c3a66f 5026 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 5027 /* Polled via timer. */
5028 tw32_f(MAC_EVENT, 0);
5029 } else {
5030 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5031 }
5032 udelay(40);
5033
4153577a 5034 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
953c96e0 5035 current_link_up &&
1da177e4 5036 tp->link_config.active_speed == SPEED_1000 &&
63c3a66f 5037 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
1da177e4
LT		 5038 udelay(120);
5039 tw32_f(MAC_STATUS,
5040 (MAC_STATUS_SYNC_CHANGED |
5041 MAC_STATUS_CFG_CHANGED));
5042 udelay(40);
5043 tg3_write_mem(tp,
5044 NIC_SRAM_FIRMWARE_MBOX,
5045 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5046 }
5047
5e7dfd0f 5048 /* Prevent send BD corruption. */
63c3a66f 5049 if (tg3_flag(tp, CLKREQ_BUG)) {
5e7dfd0f
MC		 5050 if (tp->link_config.active_speed == SPEED_100 ||
5051 tp->link_config.active_speed == SPEED_10)
0f49bfbd
JL		 5052 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5053 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 5054 else
0f49bfbd
JL		 5055 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5056 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f
MC		 5057 }
5058
f4a46d1f 5059 tg3_test_and_report_link_chg(tp, current_link_up);
1da177e4
LT		 5060
5061 return 0;
5062}
5063
5064struct tg3_fiber_aneginfo {
5065 int state;
5066#define ANEG_STATE_UNKNOWN 0
5067#define ANEG_STATE_AN_ENABLE 1
5068#define ANEG_STATE_RESTART_INIT 2
5069#define ANEG_STATE_RESTART 3
5070#define ANEG_STATE_DISABLE_LINK_OK 4
5071#define ANEG_STATE_ABILITY_DETECT_INIT 5
5072#define ANEG_STATE_ABILITY_DETECT 6
5073#define ANEG_STATE_ACK_DETECT_INIT 7
5074#define ANEG_STATE_ACK_DETECT 8
5075#define ANEG_STATE_COMPLETE_ACK_INIT 9
5076#define ANEG_STATE_COMPLETE_ACK 10
5077#define ANEG_STATE_IDLE_DETECT_INIT 11
5078#define ANEG_STATE_IDLE_DETECT 12
5079#define ANEG_STATE_LINK_OK 13
5080#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5081#define ANEG_STATE_NEXT_PAGE_WAIT 15
5082
5083 u32 flags;
5084#define MR_AN_ENABLE 0x00000001
5085#define MR_RESTART_AN 0x00000002
5086#define MR_AN_COMPLETE 0x00000004
5087#define MR_PAGE_RX 0x00000008
5088#define MR_NP_LOADED 0x00000010
5089#define MR_TOGGLE_TX 0x00000020
5090#define MR_LP_ADV_FULL_DUPLEX 0x00000040
5091#define MR_LP_ADV_HALF_DUPLEX 0x00000080
5092#define MR_LP_ADV_SYM_PAUSE 0x00000100
5093#define MR_LP_ADV_ASYM_PAUSE 0x00000200
5094#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5095#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5096#define MR_LP_ADV_NEXT_PAGE 0x00001000
5097#define MR_TOGGLE_RX 0x00002000
5098#define MR_NP_RX 0x00004000
5099
5100#define MR_LINK_OK 0x80000000
5101
5102 unsigned long link_time, cur_time;
5103
5104 u32 ability_match_cfg;
5105 int ability_match_count;
5106
5107 char ability_match, idle_match, ack_match;
5108
5109 u32 txconfig, rxconfig;
5110#define ANEG_CFG_NP 0x00000080
5111#define ANEG_CFG_ACK 0x00000040
5112#define ANEG_CFG_RF2 0x00000020
5113#define ANEG_CFG_RF1 0x00000010
5114#define ANEG_CFG_PS2 0x00000001
5115#define ANEG_CFG_PS1 0x00008000
5116#define ANEG_CFG_HD 0x00004000
5117#define ANEG_CFG_FD 0x00002000
5118#define ANEG_CFG_INVAL 0x00001f06
5119
5120};
5121#define ANEG_OK 0
5122#define ANEG_DONE 1
5123#define ANEG_TIMER_ENAB 2
5124#define ANEG_FAILED -1
5125
5126#define ANEG_STATE_SETTLE_TIME 10000
5127
5128static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5129 struct tg3_fiber_aneginfo *ap)
5130{
5be73b47 5131 u16 flowctrl;
1da177e4
LT		 5132 unsigned long delta;
5133 u32 rx_cfg_reg;
5134 int ret;
5135
5136 if (ap->state == ANEG_STATE_UNKNOWN) {
5137 ap->rxconfig = 0;
5138 ap->link_time = 0;
5139 ap->cur_time = 0;
5140 ap->ability_match_cfg = 0;
5141 ap->ability_match_count = 0;
5142 ap->ability_match = 0;
5143 ap->idle_match = 0;
5144 ap->ack_match = 0;
5145 }
5146 ap->cur_time++;
5147
5148 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5149 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5150
5151 if (rx_cfg_reg != ap->ability_match_cfg) {
5152 ap->ability_match_cfg = rx_cfg_reg;
5153 ap->ability_match = 0;
5154 ap->ability_match_count = 0;
5155 } else {
5156 if (++ap->ability_match_count > 1) {
5157 ap->ability_match = 1;
5158 ap->ability_match_cfg = rx_cfg_reg;
5159 }
5160 }
5161 if (rx_cfg_reg & ANEG_CFG_ACK)
5162 ap->ack_match = 1;
5163 else
5164 ap->ack_match = 0;
5165
5166 ap->idle_match = 0;
5167 } else {
5168 ap->idle_match = 1;
5169 ap->ability_match_cfg = 0;
5170 ap->ability_match_count = 0;
5171 ap->ability_match = 0;
5172 ap->ack_match = 0;
5173
5174 rx_cfg_reg = 0;
5175 }
5176
5177 ap->rxconfig = rx_cfg_reg;
5178 ret = ANEG_OK;
5179
33f401ae 5180 switch (ap->state) {
1da177e4
LT		 5181 case ANEG_STATE_UNKNOWN:
5182 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5183 ap->state = ANEG_STATE_AN_ENABLE;
5184
5185 /* fallthru */
5186 case ANEG_STATE_AN_ENABLE:
5187 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5188 if (ap->flags & MR_AN_ENABLE) {
5189 ap->link_time = 0;
5190 ap->cur_time = 0;
5191 ap->ability_match_cfg = 0;
5192 ap->ability_match_count = 0;
5193 ap->ability_match = 0;
5194 ap->idle_match = 0;
5195 ap->ack_match = 0;
5196
5197 ap->state = ANEG_STATE_RESTART_INIT;
5198 } else {
5199 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5200 }
5201 break;
5202
5203 case ANEG_STATE_RESTART_INIT:
5204 ap->link_time = ap->cur_time;
5205 ap->flags &= ~(MR_NP_LOADED);
5206 ap->txconfig = 0;
5207 tw32(MAC_TX_AUTO_NEG, 0);
5208 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5209 tw32_f(MAC_MODE, tp->mac_mode);
5210 udelay(40);
5211
5212 ret = ANEG_TIMER_ENAB;
5213 ap->state = ANEG_STATE_RESTART;
5214
5215 /* fallthru */
5216 case ANEG_STATE_RESTART:
5217 delta = ap->cur_time - ap->link_time;
859a5887 5218 if (delta > ANEG_STATE_SETTLE_TIME)
1da177e4 5219 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
859a5887 5220 else
1da177e4 5221 ret = ANEG_TIMER_ENAB;
1da177e4
LT		 5222 break;
5223
5224 case ANEG_STATE_DISABLE_LINK_OK:
5225 ret = ANEG_DONE;
5226 break;
5227
5228 case ANEG_STATE_ABILITY_DETECT_INIT:
5229 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 5230 ap->txconfig = ANEG_CFG_FD;
5231 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5232 if (flowctrl & ADVERTISE_1000XPAUSE)
5233 ap->txconfig |= ANEG_CFG_PS1;
5234 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5235 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 5236 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5237 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5238 tw32_f(MAC_MODE, tp->mac_mode);
5239 udelay(40);
5240
5241 ap->state = ANEG_STATE_ABILITY_DETECT;
5242 break;
5243
5244 case ANEG_STATE_ABILITY_DETECT:
859a5887 5245 if (ap->ability_match != 0 && ap->rxconfig != 0)
1da177e4 5246 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1da177e4
LT		 5247 break;
5248
5249 case ANEG_STATE_ACK_DETECT_INIT:
5250 ap->txconfig |= ANEG_CFG_ACK;
5251 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5252 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5253 tw32_f(MAC_MODE, tp->mac_mode);
5254 udelay(40);
5255
5256 ap->state = ANEG_STATE_ACK_DETECT;
5257
5258 /* fallthru */
5259 case ANEG_STATE_ACK_DETECT:
5260 if (ap->ack_match != 0) {
5261 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5262 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5263 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5264 } else {
5265 ap->state = ANEG_STATE_AN_ENABLE;
5266 }
5267 } else if (ap->ability_match != 0 &&
5268 ap->rxconfig == 0) {
5269 ap->state = ANEG_STATE_AN_ENABLE;
5270 }
5271 break;
5272
5273 case ANEG_STATE_COMPLETE_ACK_INIT:
5274 if (ap->rxconfig & ANEG_CFG_INVAL) {
5275 ret = ANEG_FAILED;
5276 break;
5277 }
5278 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5279 MR_LP_ADV_HALF_DUPLEX |
5280 MR_LP_ADV_SYM_PAUSE |
5281 MR_LP_ADV_ASYM_PAUSE |
5282 MR_LP_ADV_REMOTE_FAULT1 |
5283 MR_LP_ADV_REMOTE_FAULT2 |
5284 MR_LP_ADV_NEXT_PAGE |
5285 MR_TOGGLE_RX |
5286 MR_NP_RX);
5287 if (ap->rxconfig & ANEG_CFG_FD)
5288 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5289 if (ap->rxconfig & ANEG_CFG_HD)
5290 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5291 if (ap->rxconfig & ANEG_CFG_PS1)
5292 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5293 if (ap->rxconfig & ANEG_CFG_PS2)
5294 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5295 if (ap->rxconfig & ANEG_CFG_RF1)
5296 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5297 if (ap->rxconfig & ANEG_CFG_RF2)
5298 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5299 if (ap->rxconfig & ANEG_CFG_NP)
5300 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5301
5302 ap->link_time = ap->cur_time;
5303
5304 ap->flags ^= (MR_TOGGLE_TX);
5305 if (ap->rxconfig & 0x0008)
5306 ap->flags |= MR_TOGGLE_RX;
5307 if (ap->rxconfig & ANEG_CFG_NP)
5308 ap->flags |= MR_NP_RX;
5309 ap->flags |= MR_PAGE_RX;
5310
5311 ap->state = ANEG_STATE_COMPLETE_ACK;
5312 ret = ANEG_TIMER_ENAB;
5313 break;
5314
5315 case ANEG_STATE_COMPLETE_ACK:
5316 if (ap->ability_match != 0 &&
5317 ap->rxconfig == 0) {
5318 ap->state = ANEG_STATE_AN_ENABLE;
5319 break;
5320 }
5321 delta = ap->cur_time - ap->link_time;
5322 if (delta > ANEG_STATE_SETTLE_TIME) {
5323 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5324 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5325 } else {
5326 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5327 !(ap->flags & MR_NP_RX)) {
5328 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5329 } else {
5330 ret = ANEG_FAILED;
5331 }
5332 }
5333 }
5334 break;
5335
5336 case ANEG_STATE_IDLE_DETECT_INIT:
5337 ap->link_time = ap->cur_time;
5338 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5339 tw32_f(MAC_MODE, tp->mac_mode);
5340 udelay(40);
5341
5342 ap->state = ANEG_STATE_IDLE_DETECT;
5343 ret = ANEG_TIMER_ENAB;
5344 break;
5345
5346 case ANEG_STATE_IDLE_DETECT:
5347 if (ap->ability_match != 0 &&
5348 ap->rxconfig == 0) {
5349 ap->state = ANEG_STATE_AN_ENABLE;
5350 break;
5351 }
5352 delta = ap->cur_time - ap->link_time;
5353 if (delta > ANEG_STATE_SETTLE_TIME) {
5354 /* XXX another gem from the Broadcom driver :( */
5355 ap->state = ANEG_STATE_LINK_OK;
5356 }
5357 break;
5358
5359 case ANEG_STATE_LINK_OK:
5360 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5361 ret = ANEG_DONE;
5362 break;
5363
5364 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5365 /* ??? unimplemented */
5366 break;
5367
5368 case ANEG_STATE_NEXT_PAGE_WAIT:
5369 /* ??? unimplemented */
5370 break;
5371
5372 default:
5373 ret = ANEG_FAILED;
5374 break;
855e1111 5375 }
1da177e4
LT		 5376
5377 return ret;
5378}
5379
5be73b47 5380static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 5381{
5382 int res = 0;
5383 struct tg3_fiber_aneginfo aninfo;
5384 int status = ANEG_FAILED;
5385 unsigned int tick;
5386 u32 tmp;
5387
5388 tw32_f(MAC_TX_AUTO_NEG, 0);
5389
5390 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5391 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5392 udelay(40);
5393
5394 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5395 udelay(40);
5396
5397 memset(&aninfo, 0, sizeof(aninfo));
5398 aninfo.flags |= MR_AN_ENABLE;
5399 aninfo.state = ANEG_STATE_UNKNOWN;
5400 aninfo.cur_time = 0;
5401 tick = 0;
5402 while (++tick < 195000) {
5403 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5404 if (status == ANEG_DONE || status == ANEG_FAILED)
5405 break;
5406
5407 udelay(1);
5408 }
5409
5410 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5411 tw32_f(MAC_MODE, tp->mac_mode);
5412 udelay(40);
5413
5be73b47
MC		 5414 *txflags = aninfo.txconfig;
5415 *rxflags = aninfo.flags;
1da177e4
LT		 5416
5417 if (status == ANEG_DONE &&
5418 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5419 MR_LP_ADV_FULL_DUPLEX)))
5420 res = 1;
5421
5422 return res;
5423}
5424
5425static void tg3_init_bcm8002(struct tg3 *tp)
5426{
5427 u32 mac_status = tr32(MAC_STATUS);
5428 int i;
5429
5430 /* Reset when initting first time or we have a link. */
63c3a66f 5431 if (tg3_flag(tp, INIT_COMPLETE) &&
1da177e4
LT		 5432 !(mac_status & MAC_STATUS_PCS_SYNCED))
5433 return;
5434
5435 /* Set PLL lock range. */
5436 tg3_writephy(tp, 0x16, 0x8007);
5437
5438 /* SW reset */
5439 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5440
5441 /* Wait for reset to complete. */
5442 /* XXX schedule_timeout() ... */
5443 for (i = 0; i < 500; i++)
5444 udelay(10);
5445
5446 /* Config mode; select PMA/Ch 1 regs. */
5447 tg3_writephy(tp, 0x10, 0x8411);
5448
5449 /* Enable auto-lock and comdet, select txclk for tx. */
5450 tg3_writephy(tp, 0x11, 0x0a10);
5451
5452 tg3_writephy(tp, 0x18, 0x00a0);
5453 tg3_writephy(tp, 0x16, 0x41ff);
5454
5455 /* Assert and deassert POR. */
5456 tg3_writephy(tp, 0x13, 0x0400);
5457 udelay(40);
5458 tg3_writephy(tp, 0x13, 0x0000);
5459
5460 tg3_writephy(tp, 0x11, 0x0a50);
5461 udelay(40);
5462 tg3_writephy(tp, 0x11, 0x0a10);
5463
5464 /* Wait for signal to stabilize */
5465 /* XXX schedule_timeout() ... */
5466 for (i = 0; i < 15000; i++)
5467 udelay(10);
5468
5469 /* Deselect the channel register so we can read the PHYID
5470 * later.
5471 */
5472 tg3_writephy(tp, 0x10, 0x8011);
5473}
5474
953c96e0 5475static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
1da177e4 5476{
82cd3d11 5477 u16 flowctrl;
953c96e0 5478 bool current_link_up;
1da177e4
LT		 5479 u32 sg_dig_ctrl, sg_dig_status;
5480 u32 serdes_cfg, expected_sg_dig_ctrl;
5481 int workaround, port_a;
1da177e4
LT		 5482
5483 serdes_cfg = 0;
5484 expected_sg_dig_ctrl = 0;
5485 workaround = 0;
5486 port_a = 1;
953c96e0 5487 current_link_up = false;
1da177e4 5488
4153577a
JP		 5489 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5490 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
1da177e4
LT		 5491 workaround = 1;
5492 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5493 port_a = 0;
5494
5495 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5496 /* preserve bits 20-23 for voltage regulator */
5497 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5498 }
5499
5500 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5501
5502 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 5503 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 5504 if (workaround) {
5505 u32 val = serdes_cfg;
5506
5507 if (port_a)
5508 val |= 0xc010000;
5509 else
5510 val |= 0x4010000;
5511 tw32_f(MAC_SERDES_CFG, val);
5512 }
c98f6e3b
MC		 5513
5514 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5515 }
5516 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5517 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5518 current_link_up = true;
1da177e4
LT		 5519 }
5520 goto out;
5521 }
5522
5523 /* Want auto-negotiation. */
c98f6e3b 5524 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 5525
82cd3d11
MC		 5526 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5527 if (flowctrl & ADVERTISE_1000XPAUSE)
5528 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5529 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5530 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 5531
5532 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
f07e9af3 5533 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3d3ebe74
MC		 5534 tp->serdes_counter &&
5535 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5536 MAC_STATUS_RCVD_CFG)) ==
5537 MAC_STATUS_PCS_SYNCED)) {
5538 tp->serdes_counter--;
953c96e0 5539 current_link_up = true;
3d3ebe74
MC		 5540 goto out;
5541 }
5542restart_autoneg:
1da177e4
LT		 5543 if (workaround)
5544 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 5545 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 5546 udelay(5);
5547 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5548
3d3ebe74 5549 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5550 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5551 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5552 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 5553 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 5554 mac_status = tr32(MAC_STATUS);
5555
c98f6e3b 5556 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 5557 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 5558 u32 local_adv = 0, remote_adv = 0;
5559
5560 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5561 local_adv |= ADVERTISE_1000XPAUSE;
5562 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5563 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 5564
c98f6e3b 5565 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 5566 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 5567 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 5568 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5569
859edb26
MC		 5570 tp->link_config.rmt_adv =
5571 mii_adv_to_ethtool_adv_x(remote_adv);
5572
1da177e4 5573 tg3_setup_flow_control(tp, local_adv, remote_adv);
953c96e0 5574 current_link_up = true;
3d3ebe74 5575 tp->serdes_counter = 0;
f07e9af3 5576 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c98f6e3b 5577 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 5578 if (tp->serdes_counter)
5579 tp->serdes_counter--;
1da177e4
LT		 5580 else {
5581 if (workaround) {
5582 u32 val = serdes_cfg;
5583
5584 if (port_a)
5585 val |= 0xc010000;
5586 else
5587 val |= 0x4010000;
5588
5589 tw32_f(MAC_SERDES_CFG, val);
5590 }
5591
c98f6e3b 5592 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5593 udelay(40);
5594
5595 /* Link parallel detection - link is up */
5596 /* only if we have PCS_SYNC and not */
5597 /* receiving config code words */
5598 mac_status = tr32(MAC_STATUS);
5599 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5600 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5601 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5602 current_link_up = true;
f07e9af3
MC		 5603 tp->phy_flags |=
5604 TG3_PHYFLG_PARALLEL_DETECT;
3d3ebe74
MC		 5605 tp->serdes_counter =
5606 SERDES_PARALLEL_DET_TIMEOUT;
5607 } else
5608 goto restart_autoneg;
1da177e4
LT		 5609 }
5610 }
3d3ebe74
MC		 5611 } else {
5612 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5613 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5614 }
5615
5616out:
5617 return current_link_up;
5618}
5619
953c96e0 5620static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
1da177e4 5621{
953c96e0 5622 bool current_link_up = false;
1da177e4 5623
5cf64b8a 5624 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 5625 goto out;
1da177e4
LT		 5626
5627 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 5628 u32 txflags, rxflags;
1da177e4 5629 int i;
6aa20a22 5630
5be73b47
MC		 5631 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5632 u32 local_adv = 0, remote_adv = 0;
1da177e4 5633
5be73b47
MC		 5634 if (txflags & ANEG_CFG_PS1)
5635 local_adv |= ADVERTISE_1000XPAUSE;
5636 if (txflags & ANEG_CFG_PS2)
5637 local_adv |= ADVERTISE_1000XPSE_ASYM;
5638
5639 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5640 remote_adv |= LPA_1000XPAUSE;
5641 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5642 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5643
859edb26
MC		 5644 tp->link_config.rmt_adv =
5645 mii_adv_to_ethtool_adv_x(remote_adv);
5646
1da177e4
LT		 5647 tg3_setup_flow_control(tp, local_adv, remote_adv);
5648
953c96e0 5649 current_link_up = true;
1da177e4
LT		 5650 }
5651 for (i = 0; i < 30; i++) {
5652 udelay(20);
5653 tw32_f(MAC_STATUS,
5654 (MAC_STATUS_SYNC_CHANGED |
5655 MAC_STATUS_CFG_CHANGED));
5656 udelay(40);
5657 if ((tr32(MAC_STATUS) &
5658 (MAC_STATUS_SYNC_CHANGED |
5659 MAC_STATUS_CFG_CHANGED)) == 0)
5660 break;
5661 }
5662
5663 mac_status = tr32(MAC_STATUS);
953c96e0 5664 if (!current_link_up &&
1da177e4
LT		 5665 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5666 !(mac_status & MAC_STATUS_RCVD_CFG))
953c96e0 5667 current_link_up = true;
1da177e4 5668 } else {
5be73b47
MC		 5669 tg3_setup_flow_control(tp, 0, 0);
5670
1da177e4 5671 /* Forcing 1000FD link up. */
953c96e0 5672 current_link_up = true;
1da177e4
LT		 5673
5674 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5675 udelay(40);
e8f3f6ca
MC		 5676
5677 tw32_f(MAC_MODE, tp->mac_mode);
5678 udelay(40);
1da177e4
LT		 5679 }
5680
5681out:
5682 return current_link_up;
5683}
5684
953c96e0 5685static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
1da177e4
LT		 5686{
5687 u32 orig_pause_cfg;
5688 u16 orig_active_speed;
5689 u8 orig_active_duplex;
5690 u32 mac_status;
953c96e0 5691 bool current_link_up;
1da177e4
LT		 5692 int i;
5693
8d018621 5694 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5695 orig_active_speed = tp->link_config.active_speed;
5696 orig_active_duplex = tp->link_config.active_duplex;
5697
63c3a66f 5698 if (!tg3_flag(tp, HW_AUTONEG) &&
f4a46d1f 5699 tp->link_up &&
63c3a66f 5700 tg3_flag(tp, INIT_COMPLETE)) {
1da177e4
LT		 5701 mac_status = tr32(MAC_STATUS);
5702 mac_status &= (MAC_STATUS_PCS_SYNCED |
5703 MAC_STATUS_SIGNAL_DET |
5704 MAC_STATUS_CFG_CHANGED |
5705 MAC_STATUS_RCVD_CFG);
5706 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5707 MAC_STATUS_SIGNAL_DET)) {
5708 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5709 MAC_STATUS_CFG_CHANGED));
5710 return 0;
5711 }
5712 }
5713
5714 tw32_f(MAC_TX_AUTO_NEG, 0);
5715
5716 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5717 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5718 tw32_f(MAC_MODE, tp->mac_mode);
5719 udelay(40);
5720
79eb6904 5721 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 5722 tg3_init_bcm8002(tp);
5723
5724 /* Enable link change event even when serdes polling. */
5725 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5726 udelay(40);
5727
953c96e0 5728 current_link_up = false;
859edb26 5729 tp->link_config.rmt_adv = 0;
1da177e4
LT		 5730 mac_status = tr32(MAC_STATUS);
5731
63c3a66f 5732 if (tg3_flag(tp, HW_AUTONEG))
1da177e4
LT		 5733 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5734 else
5735 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5736
898a56f8 5737 tp->napi[0].hw_status->status =
1da177e4 5738 (SD_STATUS_UPDATED |
898a56f8 5739 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 5740
5741 for (i = 0; i < 100; i++) {
5742 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5743 MAC_STATUS_CFG_CHANGED));
5744 udelay(5);
5745 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 5746 MAC_STATUS_CFG_CHANGED |
5747 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 5748 break;
5749 }
5750
5751 mac_status = tr32(MAC_STATUS);
5752 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
953c96e0 5753 current_link_up = false;
3d3ebe74
MC		 5754 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5755 tp->serdes_counter == 0) {
1da177e4
LT		 5756 tw32_f(MAC_MODE, (tp->mac_mode |
5757 MAC_MODE_SEND_CONFIGS));
5758 udelay(1);
5759 tw32_f(MAC_MODE, tp->mac_mode);
5760 }
5761 }
5762
953c96e0 5763 if (current_link_up) {
1da177e4
LT		 5764 tp->link_config.active_speed = SPEED_1000;
5765 tp->link_config.active_duplex = DUPLEX_FULL;
5766 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5767 LED_CTRL_LNKLED_OVERRIDE |
5768 LED_CTRL_1000MBPS_ON));
5769 } else {
e740522e
MC		 5770 tp->link_config.active_speed = SPEED_UNKNOWN;
5771 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 5772 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5773 LED_CTRL_LNKLED_OVERRIDE |
5774 LED_CTRL_TRAFFIC_OVERRIDE));
5775 }
5776
f4a46d1f 5777 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
8d018621 5778 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5779 if (orig_pause_cfg != now_pause_cfg ||
5780 orig_active_speed != tp->link_config.active_speed ||
5781 orig_active_duplex != tp->link_config.active_duplex)
5782 tg3_link_report(tp);
5783 }
5784
5785 return 0;
5786}
5787
953c96e0 5788static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
747e8f8b 5789{
953c96e0 5790 int err = 0;
747e8f8b 5791 u32 bmsr, bmcr;
85730a63
MC		 5792 u16 current_speed = SPEED_UNKNOWN;
5793 u8 current_duplex = DUPLEX_UNKNOWN;
953c96e0 5794 bool current_link_up = false;
85730a63
MC		 5795 u32 local_adv, remote_adv, sgsr;
5796
5797 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5798 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5799 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5800 (sgsr & SERDES_TG3_SGMII_MODE)) {
5801
5802 if (force_reset)
5803 tg3_phy_reset(tp);
5804
5805 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5806
5807 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5808 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5809 } else {
953c96e0 5810 current_link_up = true;
85730a63
MC		 5811 if (sgsr & SERDES_TG3_SPEED_1000) {
5812 current_speed = SPEED_1000;
5813 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5814 } else if (sgsr & SERDES_TG3_SPEED_100) {
5815 current_speed = SPEED_100;
5816 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5817 } else {
5818 current_speed = SPEED_10;
5819 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5820 }
5821
5822 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5823 current_duplex = DUPLEX_FULL;
5824 else
5825 current_duplex = DUPLEX_HALF;
5826 }
5827
5828 tw32_f(MAC_MODE, tp->mac_mode);
5829 udelay(40);
5830
5831 tg3_clear_mac_status(tp);
5832
5833 goto fiber_setup_done;
5834 }
747e8f8b
MC		 5835
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5837 tw32_f(MAC_MODE, tp->mac_mode);
5838 udelay(40);
5839
3310e248 5840 tg3_clear_mac_status(tp);
747e8f8b
MC		 5841
5842 if (force_reset)
5843 tg3_phy_reset(tp);
5844
859edb26 5845 tp->link_config.rmt_adv = 0;
747e8f8b
MC		 5846
5847 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5848 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5849 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5850 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5851 bmsr |= BMSR_LSTATUS;
5852 else
5853 bmsr &= ~BMSR_LSTATUS;
5854 }
747e8f8b
MC		 5855
5856 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5857
5858 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
f07e9af3 5859 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 5860 /* do nothing, just check for link up at the end */
5861 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
28011cf1 5862 u32 adv, newadv;
747e8f8b
MC		 5863
5864 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
28011cf1
MC		 5865 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5866 ADVERTISE_1000XPAUSE |
5867 ADVERTISE_1000XPSE_ASYM |
5868 ADVERTISE_SLCT);
747e8f8b 5869
28011cf1 5870 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
37f07023 5871 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
747e8f8b 5872
28011cf1
MC		 5873 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5874 tg3_writephy(tp, MII_ADVERTISE, newadv);
747e8f8b
MC		 5875 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5876 tg3_writephy(tp, MII_BMCR, bmcr);
5877
5878 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 5879 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
f07e9af3 5880 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5881
5882 return err;
5883 }
5884 } else {
5885 u32 new_bmcr;
5886
5887 bmcr &= ~BMCR_SPEED1000;
5888 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5889
5890 if (tp->link_config.duplex == DUPLEX_FULL)
5891 new_bmcr |= BMCR_FULLDPLX;
5892
5893 if (new_bmcr != bmcr) {
5894 /* BMCR_SPEED1000 is a reserved bit that needs
5895 * to be set on write.
5896 */
5897 new_bmcr |= BMCR_SPEED1000;
5898
5899 /* Force a linkdown */
f4a46d1f 5900 if (tp->link_up) {
747e8f8b
MC		 5901 u32 adv;
5902
5903 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5904 adv &= ~(ADVERTISE_1000XFULL |
5905 ADVERTISE_1000XHALF |
5906 ADVERTISE_SLCT);
5907 tg3_writephy(tp, MII_ADVERTISE, adv);
5908 tg3_writephy(tp, MII_BMCR, bmcr |
5909 BMCR_ANRESTART |
5910 BMCR_ANENABLE);
5911 udelay(10);
f4a46d1f 5912 tg3_carrier_off(tp);
747e8f8b
MC		 5913 }
5914 tg3_writephy(tp, MII_BMCR, new_bmcr);
5915 bmcr = new_bmcr;
5916 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5917 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5918 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5919 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5920 bmsr |= BMSR_LSTATUS;
5921 else
5922 bmsr &= ~BMSR_LSTATUS;
5923 }
f07e9af3 5924 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5925 }
5926 }
5927
5928 if (bmsr & BMSR_LSTATUS) {
5929 current_speed = SPEED_1000;
953c96e0 5930 current_link_up = true;
747e8f8b
MC		 5931 if (bmcr & BMCR_FULLDPLX)
5932 current_duplex = DUPLEX_FULL;
5933 else
5934 current_duplex = DUPLEX_HALF;
5935
ef167e27
MC		 5936 local_adv = 0;
5937 remote_adv = 0;
5938
747e8f8b 5939 if (bmcr & BMCR_ANENABLE) {
ef167e27 5940 u32 common;
747e8f8b
MC		 5941
5942 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5943 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5944 common = local_adv & remote_adv;
5945 if (common & (ADVERTISE_1000XHALF |
5946 ADVERTISE_1000XFULL)) {
5947 if (common & ADVERTISE_1000XFULL)
5948 current_duplex = DUPLEX_FULL;
5949 else
5950 current_duplex = DUPLEX_HALF;
859edb26
MC		 5951
5952 tp->link_config.rmt_adv =
5953 mii_adv_to_ethtool_adv_x(remote_adv);
63c3a66f 5954 } else if (!tg3_flag(tp, 5780_CLASS)) {
57d8b880 5955 /* Link is up via parallel detect */
859a5887 5956 } else {
953c96e0 5957 current_link_up = false;
859a5887 5958 }
747e8f8b
MC		 5959 }
5960 }
5961
85730a63 5962fiber_setup_done:
953c96e0 5963 if (current_link_up && current_duplex == DUPLEX_FULL)
ef167e27
MC		 5964 tg3_setup_flow_control(tp, local_adv, remote_adv);
5965
747e8f8b
MC		 5966 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5967 if (tp->link_config.active_duplex == DUPLEX_HALF)
5968 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5969
5970 tw32_f(MAC_MODE, tp->mac_mode);
5971 udelay(40);
5972
5973 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5974
5975 tp->link_config.active_speed = current_speed;
5976 tp->link_config.active_duplex = current_duplex;
5977
f4a46d1f 5978 tg3_test_and_report_link_chg(tp, current_link_up);
747e8f8b
MC		 5979 return err;
5980}
5981
5982static void tg3_serdes_parallel_detect(struct tg3 *tp)
5983{
3d3ebe74 5984 if (tp->serdes_counter) {
747e8f8b 5985 /* Give autoneg time to complete. */
3d3ebe74 5986 tp->serdes_counter--;
747e8f8b
MC		 5987 return;
5988 }
c6cdf436 5989
f4a46d1f 5990 if (!tp->link_up &&
747e8f8b
MC		 5991 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5992 u32 bmcr;
5993
5994 tg3_readphy(tp, MII_BMCR, &bmcr);
5995 if (bmcr & BMCR_ANENABLE) {
5996 u32 phy1, phy2;
5997
5998 /* Select shadow register 0x1f */
f08aa1a8
MC		 5999 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6000 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
747e8f8b
MC		 6001
6002 /* Select expansion interrupt status register */
f08aa1a8
MC		 6003 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6004 MII_TG3_DSP_EXP1_INT_STAT);
6005 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6006 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6007
6008 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6009 /* We have signal detect and not receiving
6010 * config code words, link is up by parallel
6011 * detection.
6012 */
6013
6014 bmcr &= ~BMCR_ANENABLE;
6015 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6016 tg3_writephy(tp, MII_BMCR, bmcr);
f07e9af3 6017 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6018 }
6019 }
f4a46d1f 6020 } else if (tp->link_up &&
859a5887 6021 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
f07e9af3 6022 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 6023 u32 phy2;
6024
6025 /* Select expansion interrupt status register */
f08aa1a8
MC		 6026 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6027 MII_TG3_DSP_EXP1_INT_STAT);
6028 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6029 if (phy2 & 0x20) {
6030 u32 bmcr;
6031
6032 /* Config code words received, turn on autoneg. */
6033 tg3_readphy(tp, MII_BMCR, &bmcr);
6034 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6035
f07e9af3 6036 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6037
6038 }
6039 }
6040}
6041
953c96e0 6042static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
1da177e4 6043{
f2096f94 6044 u32 val;
1da177e4
LT		 6045 int err;
6046
f07e9af3 6047 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4 6048 err = tg3_setup_fiber_phy(tp, force_reset);
f07e9af3 6049 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
747e8f8b 6050 err = tg3_setup_fiber_mii_phy(tp, force_reset);
859a5887 6051 else
1da177e4 6052 err = tg3_setup_copper_phy(tp, force_reset);
1da177e4 6053
4153577a 6054 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
f2096f94 6055 u32 scale;
aa6c91fe
MC		 6056
6057 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6058 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6059 scale = 65;
6060 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6061 scale = 6;
6062 else
6063 scale = 12;
6064
6065 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6066 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6067 tw32(GRC_MISC_CFG, val);
6068 }
6069
f2096f94
MC		 6070 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6071 (6 << TX_LENGTHS_IPG_SHIFT);
4153577a
JP		 6072 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6073 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 6074 val |= tr32(MAC_TX_LENGTHS) &
6075 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6076 TX_LENGTHS_CNT_DWN_VAL_MSK);
6077
1da177e4
LT		 6078 if (tp->link_config.active_speed == SPEED_1000 &&
6079 tp->link_config.active_duplex == DUPLEX_HALF)
f2096f94
MC		 6080 tw32(MAC_TX_LENGTHS, val |
6081 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6082 else
f2096f94
MC		 6083 tw32(MAC_TX_LENGTHS, val |
6084 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6085
63c3a66f 6086 if (!tg3_flag(tp, 5705_PLUS)) {
f4a46d1f 6087 if (tp->link_up) {
1da177e4 6088 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 6089 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 6090 } else {
6091 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6092 }
6093 }
6094
63c3a66f 6095 if (tg3_flag(tp, ASPM_WORKAROUND)) {
f2096f94 6096 val = tr32(PCIE_PWR_MGMT_THRESH);
f4a46d1f 6097 if (!tp->link_up)
8ed5d97e
MC		 6098 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6099 tp->pwrmgmt_thresh;
6100 else
6101 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6102 tw32(PCIE_PWR_MGMT_THRESH, val);
6103 }
6104
1da177e4
LT		 6105 return err;
6106}
6107
7d41e49a
MC		 6108/* tp->lock must be held */
6109static u64 tg3_refclk_read(struct tg3 *tp)
6110{
6111 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6112 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6113}
6114
be947307
MC		 6115/* tp->lock must be held */
6116static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6117{
92e6457d
NS		 6118 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6119
6120 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
be947307
MC		 6121 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6122 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
92e6457d 6123 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
be947307
MC		 6124}
6125
7d41e49a
MC		 6126static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6127static inline void tg3_full_unlock(struct tg3 *tp);
6128static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6129{
6130 struct tg3 *tp = netdev_priv(dev);
6131
6132 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6133 SOF_TIMESTAMPING_RX_SOFTWARE |
f233a976
FL		 6134 SOF_TIMESTAMPING_SOFTWARE;
6135
6136 if (tg3_flag(tp, PTP_CAPABLE)) {
32e19272 6137 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
f233a976
FL		 6138 SOF_TIMESTAMPING_RX_HARDWARE |
6139 SOF_TIMESTAMPING_RAW_HARDWARE;
6140 }
7d41e49a
MC		 6141
6142 if (tp->ptp_clock)
6143 info->phc_index = ptp_clock_index(tp->ptp_clock);
6144 else
6145 info->phc_index = -1;
6146
6147 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6148
6149 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6150 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6151 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6152 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6153 return 0;
6154}
6155
6156static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6157{
6158 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6159 bool neg_adj = false;
6160 u32 correction = 0;
6161
6162 if (ppb < 0) {
6163 neg_adj = true;
6164 ppb = -ppb;
6165 }
6166
6167 /* Frequency adjustment is performed using hardware with a 24 bit
6168 * accumulator and a programmable correction value. On each clk, the
6169 * correction value gets added to the accumulator and when it
6170 * overflows, the time counter is incremented/decremented.
6171 *
6172 * So conversion from ppb to correction value is
6173 * ppb * (1 << 24) / 1000000000
6174 */
6175 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6176 TG3_EAV_REF_CLK_CORRECT_MASK;
6177
6178 tg3_full_lock(tp, 0);
6179
6180 if (correction)
6181 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6182 TG3_EAV_REF_CLK_CORRECT_EN |
6183 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6184 else
6185 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6186
6187 tg3_full_unlock(tp);
6188
6189 return 0;
6190}
6191
6192static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6193{
6194 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6195
6196 tg3_full_lock(tp, 0);
6197 tp->ptp_adjust += delta;
6198 tg3_full_unlock(tp);
6199
6200 return 0;
6201}
6202
6203static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6204{
6205 u64 ns;
6206 u32 remainder;
6207 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6208
6209 tg3_full_lock(tp, 0);
6210 ns = tg3_refclk_read(tp);
6211 ns += tp->ptp_adjust;
6212 tg3_full_unlock(tp);
6213
6214 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6215 ts->tv_nsec = remainder;
6216
6217 return 0;
6218}
6219
6220static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6221 const struct timespec *ts)
6222{
6223 u64 ns;
6224 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6225
6226 ns = timespec_to_ns(ts);
6227
6228 tg3_full_lock(tp, 0);
6229 tg3_refclk_write(tp, ns);
6230 tp->ptp_adjust = 0;
6231 tg3_full_unlock(tp);
6232
6233 return 0;
6234}
6235
6236static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6237 struct ptp_clock_request *rq, int on)
6238{
92e6457d
NS		 6239 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6240 u32 clock_ctl;
6241 int rval = 0;
6242
6243 switch (rq->type) {
6244 case PTP_CLK_REQ_PEROUT:
6245 if (rq->perout.index != 0)
6246 return -EINVAL;
6247
6248 tg3_full_lock(tp, 0);
6249 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6250 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6251
6252 if (on) {
6253 u64 nsec;
6254
6255 nsec = rq->perout.start.sec * 1000000000ULL +
6256 rq->perout.start.nsec;
6257
6258 if (rq->perout.period.sec || rq->perout.period.nsec) {
6259 netdev_warn(tp->dev,
6260 "Device supports only a one-shot timesync output, period must be 0\n");
6261 rval = -EINVAL;
6262 goto err_out;
6263 }
6264
6265 if (nsec & (1ULL << 63)) {
6266 netdev_warn(tp->dev,
6267 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6268 rval = -EINVAL;
6269 goto err_out;
6270 }
6271
6272 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6273 tw32(TG3_EAV_WATCHDOG0_MSB,
6274 TG3_EAV_WATCHDOG0_EN |
6275 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6276
6277 tw32(TG3_EAV_REF_CLCK_CTL,
6278 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6279 } else {
6280 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6281 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6282 }
6283
6284err_out:
6285 tg3_full_unlock(tp);
6286 return rval;
6287
6288 default:
6289 break;
6290 }
6291
7d41e49a
MC		 6292 return -EOPNOTSUPP;
6293}
6294
6295static const struct ptp_clock_info tg3_ptp_caps = {
6296 .owner = THIS_MODULE,
6297 .name = "tg3 clock",
6298 .max_adj = 250000000,
6299 .n_alarm = 0,
6300 .n_ext_ts = 0,
92e6457d 6301 .n_per_out = 1,
7d41e49a
MC		 6302 .pps = 0,
6303 .adjfreq = tg3_ptp_adjfreq,
6304 .adjtime = tg3_ptp_adjtime,
6305 .gettime = tg3_ptp_gettime,
6306 .settime = tg3_ptp_settime,
6307 .enable = tg3_ptp_enable,
6308};
6309
fb4ce8ad
MC		 6310static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6311 struct skb_shared_hwtstamps *timestamp)
6312{
6313 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6314 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6315 tp->ptp_adjust);
6316}
6317
be947307
MC		 6318/* tp->lock must be held */
6319static void tg3_ptp_init(struct tg3 *tp)
6320{
6321 if (!tg3_flag(tp, PTP_CAPABLE))
6322 return;
6323
6324 /* Initialize the hardware clock to the system time. */
6325 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6326 tp->ptp_adjust = 0;
7d41e49a 6327 tp->ptp_info = tg3_ptp_caps;
be947307
MC		 6328}
6329
6330/* tp->lock must be held */
6331static void tg3_ptp_resume(struct tg3 *tp)
6332{
6333 if (!tg3_flag(tp, PTP_CAPABLE))
6334 return;
6335
6336 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6337 tp->ptp_adjust = 0;
6338}
6339
6340static void tg3_ptp_fini(struct tg3 *tp)
6341{
6342 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6343 return;
6344
7d41e49a 6345 ptp_clock_unregister(tp->ptp_clock);
be947307
MC		 6346 tp->ptp_clock = NULL;
6347 tp->ptp_adjust = 0;
6348}
6349
66cfd1bd
MC		 6350static inline int tg3_irq_sync(struct tg3 *tp)
6351{
6352 return tp->irq_sync;
6353}
6354
97bd8e49
MC		 6355static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6356{
6357 int i;
6358
6359 dst = (u32 *)((u8 *)dst + off);
6360 for (i = 0; i < len; i += sizeof(u32))
6361 *dst++ = tr32(off + i);
6362}
6363
6364static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6365{
6366 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6367 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6368 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6369 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6370 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6371 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6372 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6373 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6374 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6375 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6376 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6377 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6378 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6379 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6380 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6381 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6382 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6383 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6384 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6385
63c3a66f 6386 if (tg3_flag(tp, SUPPORT_MSIX))
97bd8e49
MC		 6387 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6388
6389 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6390 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6391 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6392 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6393 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6394 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6395 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6396 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6397
63c3a66f 6398 if (!tg3_flag(tp, 5705_PLUS)) {
97bd8e49
MC		 6399 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6400 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6401 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6402 }
6403
6404 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6405 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6406 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6407 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6408 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6409
63c3a66f 6410 if (tg3_flag(tp, NVRAM))
97bd8e49
MC		 6411 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6412}
6413
6414static void tg3_dump_state(struct tg3 *tp)
6415{
6416 int i;
6417 u32 *regs;
6418
6419 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
b2adaca9 6420 if (!regs)
97bd8e49 6421 return;
97bd8e49 6422
63c3a66f 6423 if (tg3_flag(tp, PCI_EXPRESS)) {
97bd8e49
MC		 6424 /* Read up to but not including private PCI registers */
6425 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6426 regs[i / sizeof(u32)] = tr32(i);
6427 } else
6428 tg3_dump_legacy_regs(tp, regs);
6429
6430 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6431 if (!regs[i + 0] && !regs[i + 1] &&
6432 !regs[i + 2] && !regs[i + 3])
6433 continue;
6434
6435 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6436 i * 4,
6437 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6438 }
6439
6440 kfree(regs);
6441
6442 for (i = 0; i < tp->irq_cnt; i++) {
6443 struct tg3_napi *tnapi = &tp->napi[i];
6444
6445 /* SW status block */
6446 netdev_err(tp->dev,
6447 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6448 i,
6449 tnapi->hw_status->status,
6450 tnapi->hw_status->status_tag,
6451 tnapi->hw_status->rx_jumbo_consumer,
6452 tnapi->hw_status->rx_consumer,
6453 tnapi->hw_status->rx_mini_consumer,
6454 tnapi->hw_status->idx[0].rx_producer,
6455 tnapi->hw_status->idx[0].tx_consumer);
6456
6457 netdev_err(tp->dev,
6458 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6459 i,
6460 tnapi->last_tag, tnapi->last_irq_tag,
6461 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6462 tnapi->rx_rcb_ptr,
6463 tnapi->prodring.rx_std_prod_idx,
6464 tnapi->prodring.rx_std_cons_idx,
6465 tnapi->prodring.rx_jmb_prod_idx,
6466 tnapi->prodring.rx_jmb_cons_idx);
6467 }
6468}
6469
df3e6548
MC		 6470/* This is called whenever we suspect that the system chipset is re-
6471 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6472 * is bogus tx completions. We try to recover by setting the
6473 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6474 * in the workqueue.
6475 */
6476static void tg3_tx_recover(struct tg3 *tp)
6477{
63c3a66f 6478 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
df3e6548
MC		 6479 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6480
5129c3a3
MC		 6481 netdev_warn(tp->dev,
6482 "The system may be re-ordering memory-mapped I/O "
6483 "cycles to the network device, attempting to recover. "
6484 "Please report the problem to the driver maintainer "
6485 "and include system chipset information.\n");
df3e6548 6486
63c3a66f 6487 tg3_flag_set(tp, TX_RECOVERY_PENDING);
df3e6548
MC		 6488}
6489
f3f3f27e 6490static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205 6491{
f65aac16
MC		 6492 /* Tell compiler to fetch tx indices from memory. */
6493 barrier();
f3f3f27e
MC		 6494 return tnapi->tx_pending -
6495 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 6496}
6497
1da177e4
LT		 6498/* Tigon3 never reports partial packet sends. So we do not
6499 * need special logic to handle SKBs that have not had all
6500 * of their frags sent yet, like SunGEM does.
6501 */
17375d25 6502static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 6503{
17375d25 6504 struct tg3 *tp = tnapi->tp;
898a56f8 6505 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 6506 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 6507 struct netdev_queue *txq;
6508 int index = tnapi - tp->napi;
298376d3 6509 unsigned int pkts_compl = 0, bytes_compl = 0;
fe5f5787 6510
63c3a66f 6511 if (tg3_flag(tp, ENABLE_TSS))
fe5f5787
MC		 6512 index--;
6513
6514 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 6515
6516 while (sw_idx != hw_idx) {
df8944cf 6517 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 6518 struct sk_buff *skb = ri->skb;
df3e6548
MC		 6519 int i, tx_bug = 0;
6520
6521 if (unlikely(skb == NULL)) {
6522 tg3_tx_recover(tp);
6523 return;
6524 }
1da177e4 6525
fb4ce8ad
MC		 6526 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6527 struct skb_shared_hwtstamps timestamp;
6528 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6529 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6530
6531 tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);
6532
6533 skb_tstamp_tx(skb, &timestamp);
6534 }
6535
f4188d8a 6536 pci_unmap_single(tp->pdev,
4e5e4f0d 6537 dma_unmap_addr(ri, mapping),
f4188d8a
AD		 6538 skb_headlen(skb),
6539 PCI_DMA_TODEVICE);
1da177e4
LT		 6540
6541 ri->skb = NULL;
6542
e01ee14d
MC		 6543 while (ri->fragmented) {
6544 ri->fragmented = false;
6545 sw_idx = NEXT_TX(sw_idx);
6546 ri = &tnapi->tx_buffers[sw_idx];
6547 }
6548
1da177e4
LT		 6549 sw_idx = NEXT_TX(sw_idx);
6550
6551 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 6552 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 6553 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6554 tx_bug = 1;
f4188d8a
AD		 6555
6556 pci_unmap_page(tp->pdev,
4e5e4f0d 6557 dma_unmap_addr(ri, mapping),
9e903e08 6558 skb_frag_size(&skb_shinfo(skb)->frags[i]),
f4188d8a 6559 PCI_DMA_TODEVICE);
e01ee14d
MC		 6560
6561 while (ri->fragmented) {
6562 ri->fragmented = false;
6563 sw_idx = NEXT_TX(sw_idx);
6564 ri = &tnapi->tx_buffers[sw_idx];
6565 }
6566
1da177e4
LT		 6567 sw_idx = NEXT_TX(sw_idx);
6568 }
6569
298376d3
TH		 6570 pkts_compl++;
6571 bytes_compl += skb->len;
6572
f47c11ee 6573 dev_kfree_skb(skb);
df3e6548
MC		 6574
6575 if (unlikely(tx_bug)) {
6576 tg3_tx_recover(tp);
6577 return;
6578 }
1da177e4
LT		 6579 }
6580
5cb917bc 6581 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
298376d3 6582
f3f3f27e 6583 tnapi->tx_cons = sw_idx;
1da177e4 6584
1b2a7205
MC		 6585 /* Need to make the tx_cons update visible to tg3_start_xmit()
6586 * before checking for netif_queue_stopped(). Without the
6587 * memory barrier, there is a small possibility that tg3_start_xmit()
6588 * will miss it and cause the queue to be stopped forever.
6589 */
6590 smp_mb();
6591
fe5f5787 6592 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 6593 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 6594 __netif_tx_lock(txq, smp_processor_id());
6595 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 6596 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 6597 netif_tx_wake_queue(txq);
6598 __netif_tx_unlock(txq);
51b91468 6599 }
1da177e4
LT		 6600}
6601
8d4057a9
ED		 6602static void tg3_frag_free(bool is_frag, void *data)
6603{
6604 if (is_frag)
6605 put_page(virt_to_head_page(data));
6606 else
6607 kfree(data);
6608}
6609
9205fd9c 6610static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
2b2cdb65 6611{
8d4057a9
ED		 6612 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6613 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6614
9205fd9c 6615 if (!ri->data)
2b2cdb65
MC		 6616 return;
6617
4e5e4f0d 6618 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
2b2cdb65 6619 map_sz, PCI_DMA_FROMDEVICE);
a1e8b307 6620 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
9205fd9c 6621 ri->data = NULL;
2b2cdb65
MC		 6622}
6623
8d4057a9 6624
1da177e4
LT		 6625/* Returns size of skb allocated or < 0 on error.
6626 *
6627 * We only need to fill in the address because the other members
6628 * of the RX descriptor are invariant, see tg3_init_rings.
6629 *
6630 * Note the purposeful assymetry of cpu vs. chip accesses. For
6631 * posting buffers we only dirty the first cache line of the RX
6632 * descriptor (containing the address). Whereas for the RX status
6633 * buffers the cpu only reads the last cacheline of the RX descriptor
6634 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6635 */
9205fd9c 6636static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
8d4057a9
ED		 6637 u32 opaque_key, u32 dest_idx_unmasked,
6638 unsigned int *frag_size)
1da177e4
LT		 6639{
6640 struct tg3_rx_buffer_desc *desc;
f94e290e 6641 struct ring_info *map;
9205fd9c 6642 u8 *data;
1da177e4 6643 dma_addr_t mapping;
9205fd9c 6644 int skb_size, data_size, dest_idx;
1da177e4 6645
1da177e4
LT		 6646 switch (opaque_key) {
6647 case RXD_OPAQUE_RING_STD:
2c49a44d 6648 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
21f581a5
MC		 6649 desc = &tpr->rx_std[dest_idx];
6650 map = &tpr->rx_std_buffers[dest_idx];
9205fd9c 6651 data_size = tp->rx_pkt_map_sz;
1da177e4
LT		 6652 break;
6653
6654 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6655 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
79ed5ac7 6656 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 6657 map = &tpr->rx_jmb_buffers[dest_idx];
9205fd9c 6658 data_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 6659 break;
6660
6661 default:
6662 return -EINVAL;
855e1111 6663 }
1da177e4
LT		 6664
6665 /* Do not overwrite any of the map or rp information
6666 * until we are sure we can commit to a new buffer.
6667 *
6668 * Callers depend upon this behavior and assume that
6669 * we leave everything unchanged if we fail.
6670 */
9205fd9c
ED		 6671 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6672 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
a1e8b307
ED		 6673 if (skb_size <= PAGE_SIZE) {
6674 data = netdev_alloc_frag(skb_size);
6675 *frag_size = skb_size;
8d4057a9
ED		 6676 } else {
6677 data = kmalloc(skb_size, GFP_ATOMIC);
6678 *frag_size = 0;
6679 }
9205fd9c 6680 if (!data)
1da177e4
LT		 6681 return -ENOMEM;
6682
9205fd9c
ED		 6683 mapping = pci_map_single(tp->pdev,
6684 data + TG3_RX_OFFSET(tp),
6685 data_size,
1da177e4 6686 PCI_DMA_FROMDEVICE);
8d4057a9 6687 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
a1e8b307 6688 tg3_frag_free(skb_size <= PAGE_SIZE, data);
a21771dd
MC		 6689 return -EIO;
6690 }
1da177e4 6691
9205fd9c 6692 map->data = data;
4e5e4f0d 6693 dma_unmap_addr_set(map, mapping, mapping);
1da177e4 6694
1da177e4
LT		 6695 desc->addr_hi = ((u64)mapping >> 32);
6696 desc->addr_lo = ((u64)mapping & 0xffffffff);
6697
9205fd9c 6698 return data_size;
1da177e4
LT		 6699}
6700
6701/* We only need to move over in the address because the other
6702 * members of the RX descriptor are invariant. See notes above
9205fd9c 6703 * tg3_alloc_rx_data for full details.
1da177e4 6704 */
a3896167
MC		 6705static void tg3_recycle_rx(struct tg3_napi *tnapi,
6706 struct tg3_rx_prodring_set *dpr,
6707 u32 opaque_key, int src_idx,
6708 u32 dest_idx_unmasked)
1da177e4 6709{
17375d25 6710 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 6711 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6712 struct ring_info *src_map, *dest_map;
8fea32b9 6713 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
c6cdf436 6714 int dest_idx;
1da177e4
LT		 6715
6716 switch (opaque_key) {
6717 case RXD_OPAQUE_RING_STD:
2c49a44d 6718 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
a3896167
MC		 6719 dest_desc = &dpr->rx_std[dest_idx];
6720 dest_map = &dpr->rx_std_buffers[dest_idx];
6721 src_desc = &spr->rx_std[src_idx];
6722 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 6723 break;
6724
6725 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6726 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
a3896167
MC		 6727 dest_desc = &dpr->rx_jmb[dest_idx].std;
6728 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6729 src_desc = &spr->rx_jmb[src_idx].std;
6730 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 6731 break;
6732
6733 default:
6734 return;
855e1111 6735 }
1da177e4 6736
9205fd9c 6737 dest_map->data = src_map->data;
4e5e4f0d
FT		 6738 dma_unmap_addr_set(dest_map, mapping,
6739 dma_unmap_addr(src_map, mapping));
1da177e4
LT		 6740 dest_desc->addr_hi = src_desc->addr_hi;
6741 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 6742
6743 /* Ensure that the update to the skb happens after the physical
6744 * addresses have been transferred to the new BD location.
6745 */
6746 smp_wmb();
6747
9205fd9c 6748 src_map->data = NULL;
1da177e4
LT		 6749}
6750
1da177e4
LT		 6751/* The RX ring scheme is composed of multiple rings which post fresh
6752 * buffers to the chip, and one special ring the chip uses to report
6753 * status back to the host.
6754 *
6755 * The special ring reports the status of received packets to the
6756 * host. The chip does not write into the original descriptor the
6757 * RX buffer was obtained from. The chip simply takes the original
6758 * descriptor as provided by the host, updates the status and length
6759 * field, then writes this into the next status ring entry.
6760 *
6761 * Each ring the host uses to post buffers to the chip is described
6762 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6763 * it is first placed into the on-chip ram. When the packet's length
6764 * is known, it walks down the TG3_BDINFO entries to select the ring.
6765 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6766 * which is within the range of the new packet's length is chosen.
6767 *
6768 * The "separate ring for rx status" scheme may sound queer, but it makes
6769 * sense from a cache coherency perspective. If only the host writes
6770 * to the buffer post rings, and only the chip writes to the rx status
6771 * rings, then cache lines never move beyond shared-modified state.
6772 * If both the host and chip were to write into the same ring, cache line
6773 * eviction could occur since both entities want it in an exclusive state.
6774 */
17375d25 6775static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 6776{
17375d25 6777 struct tg3 *tp = tnapi->tp;
f92905de 6778 u32 work_mask, rx_std_posted = 0;
4361935a 6779 u32 std_prod_idx, jmb_prod_idx;
72334482 6780 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 6781 u16 hw_idx;
1da177e4 6782 int received;
8fea32b9 6783 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
1da177e4 6784
8d9d7cfc 6785 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 6786 /*
6787 * We need to order the read of hw_idx and the read of
6788 * the opaque cookie.
6789 */
6790 rmb();
1da177e4
LT		 6791 work_mask = 0;
6792 received = 0;
4361935a
MC		 6793 std_prod_idx = tpr->rx_std_prod_idx;
6794 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 6795 while (sw_idx != hw_idx && budget > 0) {
afc081f8 6796 struct ring_info *ri;
72334482 6797 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 6798 unsigned int len;
6799 struct sk_buff *skb;
6800 dma_addr_t dma_addr;
6801 u32 opaque_key, desc_idx, *post_ptr;
9205fd9c 6802 u8 *data;
fb4ce8ad 6803 u64 tstamp = 0;
1da177e4
LT		 6804
6805 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6806 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6807 if (opaque_key == RXD_OPAQUE_RING_STD) {
8fea32b9 6808 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4e5e4f0d 6809 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6810 data = ri->data;
4361935a 6811 post_ptr = &std_prod_idx;
f92905de 6812 rx_std_posted++;
1da177e4 6813 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
8fea32b9 6814 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4e5e4f0d 6815 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6816 data = ri->data;
4361935a 6817 post_ptr = &jmb_prod_idx;
21f581a5 6818 } else
1da177e4 6819 goto next_pkt_nopost;
1da177e4
LT		 6820
6821 work_mask |= opaque_key;
6822
6823 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
6824 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
6825 drop_it:
a3896167 6826 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6827 desc_idx, *post_ptr);
6828 drop_it_no_recycle:
6829 /* Other statistics kept track of by card. */
b0057c51 6830 tp->rx_dropped++;
1da177e4
LT		 6831 goto next_pkt;
6832 }
6833
9205fd9c 6834 prefetch(data + TG3_RX_OFFSET(tp));
ad829268
MC		 6835 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6836 ETH_FCS_LEN;
1da177e4 6837
fb4ce8ad
MC		 6838 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6839 RXD_FLAG_PTPSTAT_PTPV1 ||
6840 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6841 RXD_FLAG_PTPSTAT_PTPV2) {
6842 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6843 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6844 }
6845
d2757fc4 6846 if (len > TG3_RX_COPY_THRESH(tp)) {
1da177e4 6847 int skb_size;
8d4057a9 6848 unsigned int frag_size;
1da177e4 6849
9205fd9c 6850 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
8d4057a9 6851 *post_ptr, &frag_size);
1da177e4
LT		 6852 if (skb_size < 0)
6853 goto drop_it;
6854
287be12e 6855 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 6856 PCI_DMA_FROMDEVICE);
6857
8d4057a9 6858 skb = build_skb(data, frag_size);
9205fd9c 6859 if (!skb) {
8d4057a9 6860 tg3_frag_free(frag_size != 0, data);
9205fd9c
ED		 6861 goto drop_it_no_recycle;
6862 }
6863 skb_reserve(skb, TG3_RX_OFFSET(tp));
6864 /* Ensure that the update to the data happens
61e800cf
MC		 6865 * after the usage of the old DMA mapping.
6866 */
6867 smp_wmb();
6868
9205fd9c 6869 ri->data = NULL;
61e800cf 6870
1da177e4 6871 } else {
a3896167 6872 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6873 desc_idx, *post_ptr);
6874
9205fd9c
ED		 6875 skb = netdev_alloc_skb(tp->dev,
6876 len + TG3_RAW_IP_ALIGN);
6877 if (skb == NULL)
1da177e4
LT		 6878 goto drop_it_no_recycle;
6879
9205fd9c 6880 skb_reserve(skb, TG3_RAW_IP_ALIGN);
1da177e4 6881 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
9205fd9c
ED		 6882 memcpy(skb->data,
6883 data + TG3_RX_OFFSET(tp),
6884 len);
1da177e4 6885 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
1da177e4
LT		 6886 }
6887
9205fd9c 6888 skb_put(skb, len);
fb4ce8ad
MC		 6889 if (tstamp)
6890 tg3_hwclock_to_timestamp(tp, tstamp,
6891 skb_hwtstamps(skb));
6892
dc668910 6893 if ((tp->dev->features & NETIF_F_RXCSUM) &&
1da177e4
LT		 6894 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6895 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6896 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6897 skb->ip_summed = CHECKSUM_UNNECESSARY;
6898 else
bc8acf2c 6899 skb_checksum_none_assert(skb);
1da177e4
LT		 6900
6901 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 6902
6903 if (len > (tp->dev->mtu + ETH_HLEN) &&
6904 skb->protocol != htons(ETH_P_8021Q)) {
6905 dev_kfree_skb(skb);
b0057c51 6906 goto drop_it_no_recycle;
f7b493e0
MC		 6907 }
6908
9dc7a113 6909 if (desc->type_flags & RXD_FLAG_VLAN &&
bf933c80 6910 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
86a9bad3 6911 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
bf933c80 6912 desc->err_vlan & RXD_VLAN_MASK);
9dc7a113 6913
bf933c80 6914 napi_gro_receive(&tnapi->napi, skb);
1da177e4 6915
1da177e4
LT		 6916 received++;
6917 budget--;
6918
6919next_pkt:
6920 (*post_ptr)++;
f92905de
MC		 6921
6922 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
2c49a44d
MC		 6923 tpr->rx_std_prod_idx = std_prod_idx &
6924 tp->rx_std_ring_mask;
86cfe4ff
MC		 6925 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6926 tpr->rx_std_prod_idx);
f92905de
MC		 6927 work_mask &= ~RXD_OPAQUE_RING_STD;
6928 rx_std_posted = 0;
6929 }
1da177e4 6930next_pkt_nopost:
483ba50b 6931 sw_idx++;
7cb32cf2 6932 sw_idx &= tp->rx_ret_ring_mask;
52f6d697
MC		 6933
6934 /* Refresh hw_idx to see if there is new work */
6935 if (sw_idx == hw_idx) {
8d9d7cfc 6936 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 6937 rmb();
6938 }
1da177e4
LT		 6939 }
6940
6941 /* ACK the status ring. */
72334482
MC		 6942 tnapi->rx_rcb_ptr = sw_idx;
6943 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 6944
6945 /* Refill RX ring(s). */
63c3a66f 6946 if (!tg3_flag(tp, ENABLE_RSS)) {
6541b806
MC		 6947 /* Sync BD data before updating mailbox */
6948 wmb();
6949
b196c7e4 6950 if (work_mask & RXD_OPAQUE_RING_STD) {
2c49a44d
MC		 6951 tpr->rx_std_prod_idx = std_prod_idx &
6952 tp->rx_std_ring_mask;
b196c7e4
MC		 6953 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6954 tpr->rx_std_prod_idx);
6955 }
6956 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2c49a44d
MC		 6957 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6958 tp->rx_jmb_ring_mask;
b196c7e4
MC		 6959 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6960 tpr->rx_jmb_prod_idx);
6961 }
6962 mmiowb();
6963 } else if (work_mask) {
6964 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6965 * updated before the producer indices can be updated.
6966 */
6967 smp_wmb();
6968
2c49a44d
MC		 6969 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6970 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
b196c7e4 6971
7ae52890
MC		 6972 if (tnapi != &tp->napi[1]) {
6973 tp->rx_refill = true;
e4af1af9 6974 napi_schedule(&tp->napi[1].napi);
7ae52890 6975 }
1da177e4 6976 }
1da177e4
LT		 6977
6978 return received;
6979}
6980
35f2d7d0 6981static void tg3_poll_link(struct tg3 *tp)
1da177e4 6982{
1da177e4 6983 /* handle link change and other phy events */
63c3a66f 6984 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
35f2d7d0
MC		 6985 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
6986
1da177e4
LT		 6987 if (sblk->status & SD_STATUS_LINK_CHG) {
6988 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 6989 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 6990 spin_lock(&tp->lock);
63c3a66f 6991 if (tg3_flag(tp, USE_PHYLIB)) {
dd477003
MC		 6992 tw32_f(MAC_STATUS,
6993 (MAC_STATUS_SYNC_CHANGED |
6994 MAC_STATUS_CFG_CHANGED |
6995 MAC_STATUS_MI_COMPLETION |
6996 MAC_STATUS_LNKSTATE_CHANGED));
6997 udelay(40);
6998 } else
953c96e0 6999 tg3_setup_phy(tp, false);
f47c11ee 7000 spin_unlock(&tp->lock);
1da177e4
LT		 7001 }
7002 }
35f2d7d0
MC		 7003}
7004
f89f38b8
MC		 7005static int tg3_rx_prodring_xfer(struct tg3 *tp,
7006 struct tg3_rx_prodring_set *dpr,
7007 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 7008{
7009 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 7010 int i, err = 0;
b196c7e4
MC		 7011
7012 while (1) {
7013 src_prod_idx = spr->rx_std_prod_idx;
7014
7015 /* Make sure updates to the rx_std_buffers[] entries and the
7016 * standard producer index are seen in the correct order.
7017 */
7018 smp_rmb();
7019
7020 if (spr->rx_std_cons_idx == src_prod_idx)
7021 break;
7022
7023 if (spr->rx_std_cons_idx < src_prod_idx)
7024 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7025 else
2c49a44d
MC		 7026 cpycnt = tp->rx_std_ring_mask + 1 -
7027 spr->rx_std_cons_idx;
b196c7e4 7028
2c49a44d
MC		 7029 cpycnt = min(cpycnt,
7030 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
b196c7e4
MC		 7031
7032 si = spr->rx_std_cons_idx;
7033 di = dpr->rx_std_prod_idx;
7034
e92967bf 7035 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7036 if (dpr->rx_std_buffers[i].data) {
e92967bf 7037 cpycnt = i - di;
f89f38b8 7038 err = -ENOSPC;
e92967bf
MC		 7039 break;
7040 }
7041 }
7042
7043 if (!cpycnt)
7044 break;
7045
7046 /* Ensure that updates to the rx_std_buffers ring and the
7047 * shadowed hardware producer ring from tg3_recycle_skb() are
7048 * ordered correctly WRT the skb check above.
7049 */
7050 smp_rmb();
7051
b196c7e4
MC		 7052 memcpy(&dpr->rx_std_buffers[di],
7053 &spr->rx_std_buffers[si],
7054 cpycnt * sizeof(struct ring_info));
7055
7056 for (i = 0; i < cpycnt; i++, di++, si++) {
7057 struct tg3_rx_buffer_desc *sbd, *dbd;
7058 sbd = &spr->rx_std[si];
7059 dbd = &dpr->rx_std[di];
7060 dbd->addr_hi = sbd->addr_hi;
7061 dbd->addr_lo = sbd->addr_lo;
7062 }
7063
2c49a44d
MC		 7064 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7065 tp->rx_std_ring_mask;
7066 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7067 tp->rx_std_ring_mask;
b196c7e4
MC		 7068 }
7069
7070 while (1) {
7071 src_prod_idx = spr->rx_jmb_prod_idx;
7072
7073 /* Make sure updates to the rx_jmb_buffers[] entries and
7074 * the jumbo producer index are seen in the correct order.
7075 */
7076 smp_rmb();
7077
7078 if (spr->rx_jmb_cons_idx == src_prod_idx)
7079 break;
7080
7081 if (spr->rx_jmb_cons_idx < src_prod_idx)
7082 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7083 else
2c49a44d
MC		 7084 cpycnt = tp->rx_jmb_ring_mask + 1 -
7085 spr->rx_jmb_cons_idx;
b196c7e4
MC		 7086
7087 cpycnt = min(cpycnt,
2c49a44d 7088 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7089
7090 si = spr->rx_jmb_cons_idx;
7091 di = dpr->rx_jmb_prod_idx;
7092
e92967bf 7093 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7094 if (dpr->rx_jmb_buffers[i].data) {
e92967bf 7095 cpycnt = i - di;
f89f38b8 7096 err = -ENOSPC;
e92967bf
MC		 7097 break;
7098 }
7099 }
7100
7101 if (!cpycnt)
7102 break;
7103
7104 /* Ensure that updates to the rx_jmb_buffers ring and the
7105 * shadowed hardware producer ring from tg3_recycle_skb() are
7106 * ordered correctly WRT the skb check above.
7107 */
7108 smp_rmb();
7109
b196c7e4
MC		 7110 memcpy(&dpr->rx_jmb_buffers[di],
7111 &spr->rx_jmb_buffers[si],
7112 cpycnt * sizeof(struct ring_info));
7113
7114 for (i = 0; i < cpycnt; i++, di++, si++) {
7115 struct tg3_rx_buffer_desc *sbd, *dbd;
7116 sbd = &spr->rx_jmb[si].std;
7117 dbd = &dpr->rx_jmb[di].std;
7118 dbd->addr_hi = sbd->addr_hi;
7119 dbd->addr_lo = sbd->addr_lo;
7120 }
7121
2c49a44d
MC		 7122 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7123 tp->rx_jmb_ring_mask;
7124 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7125 tp->rx_jmb_ring_mask;
b196c7e4 7126 }
f89f38b8
MC		 7127
7128 return err;
b196c7e4
MC		 7129}
7130
35f2d7d0
MC		 7131static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7132{
7133 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 7134
7135 /* run TX completion thread */
f3f3f27e 7136 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 7137 tg3_tx(tnapi);
63c3a66f 7138 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
4fd7ab59 7139 return work_done;
1da177e4
LT		 7140 }
7141
f891ea16
MC		 7142 if (!tnapi->rx_rcb_prod_idx)
7143 return work_done;
7144
1da177e4
LT		 7145 /* run RX thread, within the bounds set by NAPI.
7146 * All RX "locking" is done by ensuring outside
bea3348e 7147 * code synchronizes with tg3->napi.poll()
1da177e4 7148 */
8d9d7cfc 7149 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 7150 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 7151
63c3a66f 7152 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
8fea32b9 7153 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
f89f38b8 7154 int i, err = 0;
e4af1af9
MC		 7155 u32 std_prod_idx = dpr->rx_std_prod_idx;
7156 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 7157
7ae52890 7158 tp->rx_refill = false;
9102426a 7159 for (i = 1; i <= tp->rxq_cnt; i++)
f89f38b8 7160 err |= tg3_rx_prodring_xfer(tp, dpr,
8fea32b9 7161 &tp->napi[i].prodring);
b196c7e4
MC		 7162
7163 wmb();
7164
e4af1af9
MC		 7165 if (std_prod_idx != dpr->rx_std_prod_idx)
7166 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7167 dpr->rx_std_prod_idx);
b196c7e4 7168
e4af1af9
MC		 7169 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7170 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7171 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7172
7173 mmiowb();
f89f38b8
MC		 7174
7175 if (err)
7176 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 7177 }
7178
6f535763
DM		 7179 return work_done;
7180}
7181
db219973
MC		 7182static inline void tg3_reset_task_schedule(struct tg3 *tp)
7183{
7184 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7185 schedule_work(&tp->reset_task);
7186}
7187
7188static inline void tg3_reset_task_cancel(struct tg3 *tp)
7189{
7190 cancel_work_sync(&tp->reset_task);
7191 tg3_flag_clear(tp, RESET_TASK_PENDING);
c7101359 7192 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
db219973
MC		 7193}
7194
35f2d7d0
MC		 7195static int tg3_poll_msix(struct napi_struct *napi, int budget)
7196{
7197 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7198 struct tg3 *tp = tnapi->tp;
7199 int work_done = 0;
7200 struct tg3_hw_status *sblk = tnapi->hw_status;
7201
7202 while (1) {
7203 work_done = tg3_poll_work(tnapi, work_done, budget);
7204
63c3a66f 7205 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
35f2d7d0
MC		 7206 goto tx_recovery;
7207
7208 if (unlikely(work_done >= budget))
7209 break;
7210
c6cdf436 7211 /* tp->last_tag is used in tg3_int_reenable() below
35f2d7d0
MC		 7212 * to tell the hw how much work has been processed,
7213 * so we must read it before checking for more work.
7214 */
7215 tnapi->last_tag = sblk->status_tag;
7216 tnapi->last_irq_tag = tnapi->last_tag;
7217 rmb();
7218
7219 /* check for RX/TX work to do */
6d40db7b
MC		 7220 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7221 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7ae52890
MC		 7222
7223 /* This test here is not race free, but will reduce
7224 * the number of interrupts by looping again.
7225 */
7226 if (tnapi == &tp->napi[1] && tp->rx_refill)
7227 continue;
7228
35f2d7d0
MC		 7229 napi_complete(napi);
7230 /* Reenable interrupts. */
7231 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7ae52890
MC		 7232
7233 /* This test here is synchronized by napi_schedule()
7234 * and napi_complete() to close the race condition.
7235 */
7236 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7237 tw32(HOSTCC_MODE, tp->coalesce_mode |
7238 HOSTCC_MODE_ENABLE |
7239 tnapi->coal_now);
7240 }
35f2d7d0
MC		 7241 mmiowb();
7242 break;
7243 }
7244 }
7245
7246 return work_done;
7247
7248tx_recovery:
7249 /* work_done is guaranteed to be less than budget. */
7250 napi_complete(napi);
db219973 7251 tg3_reset_task_schedule(tp);
35f2d7d0
MC		 7252 return work_done;
7253}
7254
e64de4e6
MC		 7255static void tg3_process_error(struct tg3 *tp)
7256{
7257 u32 val;
7258 bool real_error = false;
7259
63c3a66f 7260 if (tg3_flag(tp, ERROR_PROCESSED))
e64de4e6
MC		 7261 return;
7262
7263 /* Check Flow Attention register */
7264 val = tr32(HOSTCC_FLOW_ATTN);
7265 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7266 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7267 real_error = true;
7268 }
7269
7270 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7271 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7272 real_error = true;
7273 }
7274
7275 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7276 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7277 real_error = true;
7278 }
7279
7280 if (!real_error)
7281 return;
7282
7283 tg3_dump_state(tp);
7284
63c3a66f 7285 tg3_flag_set(tp, ERROR_PROCESSED);
db219973 7286 tg3_reset_task_schedule(tp);
e64de4e6
MC		 7287}
7288
6f535763
DM		 7289static int tg3_poll(struct napi_struct *napi, int budget)
7290{
8ef0442f
MC		 7291 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7292 struct tg3 *tp = tnapi->tp;
6f535763 7293 int work_done = 0;
898a56f8 7294 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 7295
7296 while (1) {
e64de4e6
MC		 7297 if (sblk->status & SD_STATUS_ERROR)
7298 tg3_process_error(tp);
7299
35f2d7d0
MC		 7300 tg3_poll_link(tp);
7301
17375d25 7302 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763 7303
63c3a66f 7304 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6f535763
DM		 7305 goto tx_recovery;
7306
7307 if (unlikely(work_done >= budget))
7308 break;
7309
63c3a66f 7310 if (tg3_flag(tp, TAGGED_STATUS)) {
17375d25 7311 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 7312 * to tell the hw how much work has been processed,
7313 * so we must read it before checking for more work.
7314 */
898a56f8
MC		 7315 tnapi->last_tag = sblk->status_tag;
7316 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 7317 rmb();
7318 } else
7319 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 7320
17375d25 7321 if (likely(!tg3_has_work(tnapi))) {
288379f0 7322 napi_complete(napi);
17375d25 7323 tg3_int_reenable(tnapi);
6f535763
DM		 7324 break;
7325 }
1da177e4
LT		 7326 }
7327
bea3348e 7328 return work_done;
6f535763
DM		 7329
7330tx_recovery:
4fd7ab59 7331 /* work_done is guaranteed to be less than budget. */
288379f0 7332 napi_complete(napi);
db219973 7333 tg3_reset_task_schedule(tp);
4fd7ab59 7334 return work_done;
1da177e4
LT		 7335}
7336
66cfd1bd
MC		 7337static void tg3_napi_disable(struct tg3 *tp)
7338{
7339 int i;
7340
7341 for (i = tp->irq_cnt - 1; i >= 0; i--)
7342 napi_disable(&tp->napi[i].napi);
7343}
7344
7345static void tg3_napi_enable(struct tg3 *tp)
7346{
7347 int i;
7348
7349 for (i = 0; i < tp->irq_cnt; i++)
7350 napi_enable(&tp->napi[i].napi);
7351}
7352
7353static void tg3_napi_init(struct tg3 *tp)
7354{
7355 int i;
7356
7357 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7358 for (i = 1; i < tp->irq_cnt; i++)
7359 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7360}
7361
7362static void tg3_napi_fini(struct tg3 *tp)
7363{
7364 int i;
7365
7366 for (i = 0; i < tp->irq_cnt; i++)
7367 netif_napi_del(&tp->napi[i].napi);
7368}
7369
7370static inline void tg3_netif_stop(struct tg3 *tp)
7371{
7372 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7373 tg3_napi_disable(tp);
f4a46d1f 7374 netif_carrier_off(tp->dev);
66cfd1bd
MC		 7375 netif_tx_disable(tp->dev);
7376}
7377
35763066 7378/* tp->lock must be held */
66cfd1bd
MC		 7379static inline void tg3_netif_start(struct tg3 *tp)
7380{
be947307
MC		 7381 tg3_ptp_resume(tp);
7382
66cfd1bd
MC		 7383 /* NOTE: unconditional netif_tx_wake_all_queues is only
7384 * appropriate so long as all callers are assured to
7385 * have free tx slots (such as after tg3_init_hw)
7386 */
7387 netif_tx_wake_all_queues(tp->dev);
7388
f4a46d1f
NNS		 7389 if (tp->link_up)
7390 netif_carrier_on(tp->dev);
7391
66cfd1bd
MC		 7392 tg3_napi_enable(tp);
7393 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7394 tg3_enable_ints(tp);
7395}
7396
f47c11ee
DM		 7397static void tg3_irq_quiesce(struct tg3 *tp)
7398{
4f125f42
MC		 7399 int i;
7400
f47c11ee
DM		 7401 BUG_ON(tp->irq_sync);
7402
7403 tp->irq_sync = 1;
7404 smp_mb();
7405
4f125f42
MC		 7406 for (i = 0; i < tp->irq_cnt; i++)
7407 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 7408}
7409
f47c11ee
DM		 7410/* Fully shutdown all tg3 driver activity elsewhere in the system.
7411 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7412 * with as well. Most of the time, this is not necessary except when
7413 * shutting down the device.
7414 */
7415static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7416{
46966545 7417 spin_lock_bh(&tp->lock);
f47c11ee
DM		 7418 if (irq_sync)
7419 tg3_irq_quiesce(tp);
f47c11ee
DM		 7420}
7421
7422static inline void tg3_full_unlock(struct tg3 *tp)
7423{
f47c11ee
DM		 7424 spin_unlock_bh(&tp->lock);
7425}
7426
fcfa0a32
MC		 7427/* One-shot MSI handler - Chip automatically disables interrupt
7428 * after sending MSI so driver doesn't have to do it.
7429 */
7d12e780 7430static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 7431{
09943a18
MC		 7432 struct tg3_napi *tnapi = dev_id;
7433 struct tg3 *tp = tnapi->tp;
fcfa0a32 7434
898a56f8 7435 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7436 if (tnapi->rx_rcb)
7437 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 7438
7439 if (likely(!tg3_irq_sync(tp)))
09943a18 7440 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 7441
7442 return IRQ_HANDLED;
7443}
7444
88b06bc2
MC		 7445/* MSI ISR - No need to check for interrupt sharing and no need to
7446 * flush status block and interrupt mailbox. PCI ordering rules
7447 * guarantee that MSI will arrive after the status block.
7448 */
7d12e780 7449static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 7450{
09943a18
MC		 7451 struct tg3_napi *tnapi = dev_id;
7452 struct tg3 *tp = tnapi->tp;
88b06bc2 7453
898a56f8 7454 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7455 if (tnapi->rx_rcb)
7456 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 7457 /*
fac9b83e 7458 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 7459 * chip-internal interrupt pending events.
fac9b83e 7460 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 7461 * NIC to stop sending us irqs, engaging "in-intr-handler"
7462 * event coalescing.
7463 */
5b39de91 7464 tw32_mailbox(tnapi->int_mbox, 0x00000001);
61487480 7465 if (likely(!tg3_irq_sync(tp)))
09943a18 7466 napi_schedule(&tnapi->napi);
61487480 7467
88b06bc2
MC		 7468 return IRQ_RETVAL(1);
7469}
7470
7d12e780 7471static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 7472{
09943a18
MC		 7473 struct tg3_napi *tnapi = dev_id;
7474 struct tg3 *tp = tnapi->tp;
898a56f8 7475 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 7476 unsigned int handled = 1;
7477
1da177e4
LT		 7478 /* In INTx mode, it is possible for the interrupt to arrive at
7479 * the CPU before the status block posted prior to the interrupt.
7480 * Reading the PCI State register will confirm whether the
7481 * interrupt is ours and will flush the status block.
7482 */
d18edcb2 7483 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
63c3a66f 7484 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7485 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7486 handled = 0;
f47c11ee 7487 goto out;
fac9b83e 7488 }
d18edcb2
MC		 7489 }
7490
7491 /*
7492 * Writing any value to intr-mbox-0 clears PCI INTA# and
7493 * chip-internal interrupt pending events.
7494 * Writing non-zero to intr-mbox-0 additional tells the
7495 * NIC to stop sending us irqs, engaging "in-intr-handler"
7496 * event coalescing.
c04cb347
MC		 7497 *
7498 * Flush the mailbox to de-assert the IRQ immediately to prevent
7499 * spurious interrupts. The flush impacts performance but
7500 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7501 */
c04cb347 7502 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 7503 if (tg3_irq_sync(tp))
7504 goto out;
7505 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 7506 if (likely(tg3_has_work(tnapi))) {
72334482 7507 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 7508 napi_schedule(&tnapi->napi);
d18edcb2
MC		 7509 } else {
7510 /* No work, shared interrupt perhaps? re-enable
7511 * interrupts, and flush that PCI write
7512 */
7513 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7514 0x00000000);
fac9b83e 7515 }
f47c11ee 7516out:
fac9b83e
DM		 7517 return IRQ_RETVAL(handled);
7518}
7519
7d12e780 7520static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 7521{
09943a18
MC		 7522 struct tg3_napi *tnapi = dev_id;
7523 struct tg3 *tp = tnapi->tp;
898a56f8 7524 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 7525 unsigned int handled = 1;
7526
fac9b83e
DM		 7527 /* In INTx mode, it is possible for the interrupt to arrive at
7528 * the CPU before the status block posted prior to the interrupt.
7529 * Reading the PCI State register will confirm whether the
7530 * interrupt is ours and will flush the status block.
7531 */
898a56f8 7532 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
63c3a66f 7533 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7534 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7535 handled = 0;
f47c11ee 7536 goto out;
1da177e4 7537 }
d18edcb2
MC		 7538 }
7539
7540 /*
7541 * writing any value to intr-mbox-0 clears PCI INTA# and
7542 * chip-internal interrupt pending events.
7543 * writing non-zero to intr-mbox-0 additional tells the
7544 * NIC to stop sending us irqs, engaging "in-intr-handler"
7545 * event coalescing.
c04cb347
MC		 7546 *
7547 * Flush the mailbox to de-assert the IRQ immediately to prevent
7548 * spurious interrupts. The flush impacts performance but
7549 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7550 */
c04cb347 7551 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 7552
7553 /*
7554 * In a shared interrupt configuration, sometimes other devices'
7555 * interrupts will scream. We record the current status tag here
7556 * so that the above check can report that the screaming interrupts
7557 * are unhandled. Eventually they will be silenced.
7558 */
898a56f8 7559 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 7560
d18edcb2
MC		 7561 if (tg3_irq_sync(tp))
7562 goto out;
624f8e50 7563
72334482 7564 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 7565
09943a18 7566 napi_schedule(&tnapi->napi);
624f8e50 7567
f47c11ee 7568out:
1da177e4
LT		 7569 return IRQ_RETVAL(handled);
7570}
7571
7938109f 7572/* ISR for interrupt test */
7d12e780 7573static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 7574{
09943a18
MC		 7575 struct tg3_napi *tnapi = dev_id;
7576 struct tg3 *tp = tnapi->tp;
898a56f8 7577 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 7578
f9804ddb
MC		 7579 if ((sblk->status & SD_STATUS_UPDATED) ||
7580 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 7581 tg3_disable_ints(tp);
7938109f
MC		 7582 return IRQ_RETVAL(1);
7583 }
7584 return IRQ_RETVAL(0);
7585}
7586
1da177e4
LT		 7587#ifdef CONFIG_NET_POLL_CONTROLLER
7588static void tg3_poll_controller(struct net_device *dev)
7589{
4f125f42 7590 int i;
88b06bc2
MC		 7591 struct tg3 *tp = netdev_priv(dev);
7592
9c13cb8b
NNS		 7593 if (tg3_irq_sync(tp))
7594 return;
7595
4f125f42 7596 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 7597 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 7598}
7599#endif
7600
1da177e4
LT		 7601static void tg3_tx_timeout(struct net_device *dev)
7602{
7603 struct tg3 *tp = netdev_priv(dev);
7604
b0408751 7605 if (netif_msg_tx_err(tp)) {
05dbe005 7606 netdev_err(dev, "transmit timed out, resetting\n");
97bd8e49 7607 tg3_dump_state(tp);
b0408751 7608 }
1da177e4 7609
db219973 7610 tg3_reset_task_schedule(tp);
1da177e4
LT		 7611}
7612
c58ec932
MC		 7613/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7614static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7615{
7616 u32 base = (u32) mapping & 0xffffffff;
7617
807540ba 7618 return (base > 0xffffdcc0) && (base + len + 8 < base);
c58ec932
MC		 7619}
7620
0f0d1510
MC		 7621/* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7622 * of any 4GB boundaries: 4G, 8G, etc
7623 */
7624static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7625 u32 len, u32 mss)
7626{
7627 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7628 u32 base = (u32) mapping & 0xffffffff;
7629
7630 return ((base + len + (mss & 0x3fff)) < base);
7631 }
7632 return 0;
7633}
7634
72f2afb8
MC		 7635/* Test for DMA addresses > 40-bit */
7636static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7637 int len)
7638{
7639#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
63c3a66f 7640 if (tg3_flag(tp, 40BIT_DMA_BUG))
807540ba 7641 return ((u64) mapping + len) > DMA_BIT_MASK(40);
72f2afb8
MC		 7642 return 0;
7643#else
7644 return 0;
7645#endif
7646}
7647
d1a3b737 7648static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
92cd3a17
MC		 7649 dma_addr_t mapping, u32 len, u32 flags,
7650 u32 mss, u32 vlan)
2ffcc981 7651{
92cd3a17
MC		 7652 txbd->addr_hi = ((u64) mapping >> 32);
7653 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7654 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7655 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
2ffcc981 7656}
1da177e4 7657
84b67b27 7658static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
d1a3b737
MC		 7659 dma_addr_t map, u32 len, u32 flags,
7660 u32 mss, u32 vlan)
7661{
7662 struct tg3 *tp = tnapi->tp;
7663 bool hwbug = false;
7664
7665 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
3db1cd5c 7666 hwbug = true;
d1a3b737
MC		 7667
7668 if (tg3_4g_overflow_test(map, len))
3db1cd5c 7669 hwbug = true;
d1a3b737 7670
0f0d1510
MC		 7671 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7672 hwbug = true;
7673
d1a3b737 7674 if (tg3_40bit_overflow_test(tp, map, len))
3db1cd5c 7675 hwbug = true;
d1a3b737 7676
a4cb428d 7677 if (tp->dma_limit) {
b9e45482 7678 u32 prvidx = *entry;
e31aa987 7679 u32 tmp_flag = flags & ~TXD_FLAG_END;
a4cb428d
MC		 7680 while (len > tp->dma_limit && *budget) {
7681 u32 frag_len = tp->dma_limit;
7682 len -= tp->dma_limit;
e31aa987 7683
b9e45482
MC		 7684 /* Avoid the 8byte DMA problem */
7685 if (len <= 8) {
a4cb428d
MC		 7686 len += tp->dma_limit / 2;
7687 frag_len = tp->dma_limit / 2;
e31aa987
MC		 7688 }
7689
b9e45482
MC		 7690 tnapi->tx_buffers[*entry].fragmented = true;
7691
7692 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7693 frag_len, tmp_flag, mss, vlan);
7694 *budget -= 1;
7695 prvidx = *entry;
7696 *entry = NEXT_TX(*entry);
7697
e31aa987
MC		 7698 map += frag_len;
7699 }
7700
7701 if (len) {
7702 if (*budget) {
7703 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7704 len, flags, mss, vlan);
b9e45482 7705 *budget -= 1;
e31aa987
MC		 7706 *entry = NEXT_TX(*entry);
7707 } else {
3db1cd5c 7708 hwbug = true;
b9e45482 7709 tnapi->tx_buffers[prvidx].fragmented = false;
e31aa987
MC		 7710 }
7711 }
7712 } else {
84b67b27
MC		 7713 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7714 len, flags, mss, vlan);
e31aa987
MC		 7715 *entry = NEXT_TX(*entry);
7716 }
d1a3b737
MC		 7717
7718 return hwbug;
7719}
7720
0d681b27 7721static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
432aa7ed
MC		 7722{
7723 int i;
0d681b27 7724 struct sk_buff *skb;
df8944cf 7725 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
432aa7ed 7726
0d681b27
MC		 7727 skb = txb->skb;
7728 txb->skb = NULL;
7729
432aa7ed
MC		 7730 pci_unmap_single(tnapi->tp->pdev,
7731 dma_unmap_addr(txb, mapping),
7732 skb_headlen(skb),
7733 PCI_DMA_TODEVICE);
e01ee14d
MC		 7734
7735 while (txb->fragmented) {
7736 txb->fragmented = false;
7737 entry = NEXT_TX(entry);
7738 txb = &tnapi->tx_buffers[entry];
7739 }
7740
ba1142e4 7741 for (i = 0; i <= last; i++) {
9e903e08 7742 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
432aa7ed
MC		 7743
7744 entry = NEXT_TX(entry);
7745 txb = &tnapi->tx_buffers[entry];
7746
7747 pci_unmap_page(tnapi->tp->pdev,
7748 dma_unmap_addr(txb, mapping),
9e903e08 7749 skb_frag_size(frag), PCI_DMA_TODEVICE);
e01ee14d
MC		 7750
7751 while (txb->fragmented) {
7752 txb->fragmented = false;
7753 entry = NEXT_TX(entry);
7754 txb = &tnapi->tx_buffers[entry];
7755 }
432aa7ed
MC		 7756 }
7757}
7758
72f2afb8 7759/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4 7760static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
f7ff1987 7761 struct sk_buff **pskb,
84b67b27 7762 u32 *entry, u32 *budget,
92cd3a17 7763 u32 base_flags, u32 mss, u32 vlan)
1da177e4 7764{
24f4efd4 7765 struct tg3 *tp = tnapi->tp;
f7ff1987 7766 struct sk_buff *new_skb, *skb = *pskb;
c58ec932 7767 dma_addr_t new_addr = 0;
432aa7ed 7768 int ret = 0;
1da177e4 7769
4153577a 7770 if (tg3_asic_rev(tp) != ASIC_REV_5701)
41588ba1
MC		 7771 new_skb = skb_copy(skb, GFP_ATOMIC);
7772 else {
7773 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7774
7775 new_skb = skb_copy_expand(skb,
7776 skb_headroom(skb) + more_headroom,
7777 skb_tailroom(skb), GFP_ATOMIC);
7778 }
7779
1da177e4 7780 if (!new_skb) {
c58ec932
MC		 7781 ret = -1;
7782 } else {
7783 /* New SKB is guaranteed to be linear. */
f4188d8a
AD		 7784 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7785 PCI_DMA_TODEVICE);
7786 /* Make sure the mapping succeeded */
7787 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
f4188d8a 7788 dev_kfree_skb(new_skb);
c58ec932 7789 ret = -1;
c58ec932 7790 } else {
b9e45482
MC		 7791 u32 save_entry = *entry;
7792
92cd3a17
MC		 7793 base_flags |= TXD_FLAG_END;
7794
84b67b27
MC		 7795 tnapi->tx_buffers[*entry].skb = new_skb;
7796 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
432aa7ed
MC		 7797 mapping, new_addr);
7798
84b67b27 7799 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
d1a3b737
MC		 7800 new_skb->len, base_flags,
7801 mss, vlan)) {
ba1142e4 7802 tg3_tx_skb_unmap(tnapi, save_entry, -1);
d1a3b737
MC		 7803 dev_kfree_skb(new_skb);
7804 ret = -1;
7805 }
f4188d8a 7806 }
1da177e4
LT		 7807 }
7808
7809 dev_kfree_skb(skb);
f7ff1987 7810 *pskb = new_skb;
c58ec932 7811 return ret;
1da177e4
LT		 7812}
7813
2ffcc981 7814static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
52c0fd83
MC		 7815
7816/* Use GSO to workaround a rare TSO bug that may be triggered when the
7817 * TSO header is greater than 80 bytes.
7818 */
7819static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
7820{
7821 struct sk_buff *segs, *nskb;
f3f3f27e 7822 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 7823
7824 /* Estimate the number of fragments in the worst case */
f3f3f27e 7825 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 7826 netif_stop_queue(tp->dev);
f65aac16
MC		 7827
7828 /* netif_tx_stop_queue() must be done before checking
7829 * checking tx index in tg3_tx_avail() below, because in
7830 * tg3_tx(), we update tx index before checking for
7831 * netif_tx_queue_stopped().
7832 */
7833 smp_mb();
f3f3f27e 7834 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 7835 return NETDEV_TX_BUSY;
7836
7837 netif_wake_queue(tp->dev);
52c0fd83
MC		 7838 }
7839
7840 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 7841 if (IS_ERR(segs))
52c0fd83
MC		 7842 goto tg3_tso_bug_end;
7843
7844 do {
7845 nskb = segs;
7846 segs = segs->next;
7847 nskb->next = NULL;
2ffcc981 7848 tg3_start_xmit(nskb, tp->dev);
52c0fd83
MC		 7849 } while (segs);
7850
7851tg3_tso_bug_end:
7852 dev_kfree_skb(skb);
7853
7854 return NETDEV_TX_OK;
7855}
52c0fd83 7856
5a6f3074 7857/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
63c3a66f 7858 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
5a6f3074 7859 */
2ffcc981 7860static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 7861{
7862 struct tg3 *tp = netdev_priv(dev);
92cd3a17 7863 u32 len, entry, base_flags, mss, vlan = 0;
84b67b27 7864 u32 budget;
432aa7ed 7865 int i = -1, would_hit_hwbug;
90079ce8 7866 dma_addr_t mapping;
24f4efd4
MC		 7867 struct tg3_napi *tnapi;
7868 struct netdev_queue *txq;
432aa7ed 7869 unsigned int last;
f4188d8a 7870
24f4efd4
MC		 7871 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7872 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
63c3a66f 7873 if (tg3_flag(tp, ENABLE_TSS))
24f4efd4 7874 tnapi++;
1da177e4 7875
84b67b27
MC		 7876 budget = tg3_tx_avail(tnapi);
7877
00b70504 7878 /* We are running in BH disabled context with netif_tx_lock
bea3348e 7879 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 7880 * interrupt. Furthermore, IRQ processing runs lockless so we have
7881 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 7882 */
84b67b27 7883 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 7884 if (!netif_tx_queue_stopped(txq)) {
7885 netif_tx_stop_queue(txq);
1f064a87
SH		 7886
7887 /* This is a hard error, log it. */
5129c3a3
MC		 7888 netdev_err(dev,
7889 "BUG! Tx Ring full when queue awake!\n");
1f064a87 7890 }
1da177e4
LT		 7891 return NETDEV_TX_BUSY;
7892 }
7893
f3f3f27e 7894 entry = tnapi->tx_prod;
1da177e4 7895 base_flags = 0;
84fa7933 7896 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 7897 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 7898
be98da6a
MC		 7899 mss = skb_shinfo(skb)->gso_size;
7900 if (mss) {
eddc9ec5 7901 struct iphdr *iph;
34195c3d 7902 u32 tcp_opt_len, hdr_len;
1da177e4
LT		 7903
7904 if (skb_header_cloned(skb) &&
48855432
ED		 7905 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7906 goto drop;
1da177e4 7907
34195c3d 7908 iph = ip_hdr(skb);
ab6a5bb6 7909 tcp_opt_len = tcp_optlen(skb);
1da177e4 7910
a5a11955 7911 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
34195c3d 7912
a5a11955 7913 if (!skb_is_gso_v6(skb)) {
34195c3d
MC		 7914 iph->check = 0;
7915 iph->tot_len = htons(mss + hdr_len);
7916 }
7917
52c0fd83 7918 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
63c3a66f 7919 tg3_flag(tp, TSO_BUG))
de6f31eb 7920 return tg3_tso_bug(tp, skb);
52c0fd83 7921
1da177e4
LT		 7922 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7923 TXD_FLAG_CPU_POST_DMA);
7924
63c3a66f
JP		 7925 if (tg3_flag(tp, HW_TSO_1) ||
7926 tg3_flag(tp, HW_TSO_2) ||
7927 tg3_flag(tp, HW_TSO_3)) {
aa8223c7 7928 tcp_hdr(skb)->check = 0;
1da177e4 7929 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 7930 } else
7931 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7932 iph->daddr, 0,
7933 IPPROTO_TCP,
7934 0);
1da177e4 7935
63c3a66f 7936 if (tg3_flag(tp, HW_TSO_3)) {
615774fe
MC		 7937 mss |= (hdr_len & 0xc) << 12;
7938 if (hdr_len & 0x10)
7939 base_flags |= 0x00000010;
7940 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 7941 } else if (tg3_flag(tp, HW_TSO_2))
92c6b8d1 7942 mss |= hdr_len << 9;
63c3a66f 7943 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 7944 tg3_asic_rev(tp) == ASIC_REV_5705) {
eddc9ec5 7945 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7946 int tsflags;
7947
eddc9ec5 7948 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7949 mss |= (tsflags << 11);
7950 }
7951 } else {
eddc9ec5 7952 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7953 int tsflags;
7954
eddc9ec5 7955 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7956 base_flags |= tsflags << 12;
7957 }
7958 }
7959 }
bf933c80 7960
93a700a9
MC		 7961 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7962 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7963 base_flags |= TXD_FLAG_JMB_PKT;
7964
92cd3a17
MC		 7965 if (vlan_tx_tag_present(skb)) {
7966 base_flags |= TXD_FLAG_VLAN;
7967 vlan = vlan_tx_tag_get(skb);
7968 }
1da177e4 7969
fb4ce8ad
MC		 7970 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
7971 tg3_flag(tp, TX_TSTAMP_EN)) {
7972 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7973 base_flags |= TXD_FLAG_HWTSTAMP;
7974 }
7975
f4188d8a
AD		 7976 len = skb_headlen(skb);
7977
7978 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
48855432
ED		 7979 if (pci_dma_mapping_error(tp->pdev, mapping))
7980 goto drop;
7981
90079ce8 7982
f3f3f27e 7983 tnapi->tx_buffers[entry].skb = skb;
4e5e4f0d 7984 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 7985
7986 would_hit_hwbug = 0;
7987
63c3a66f 7988 if (tg3_flag(tp, 5701_DMA_BUG))
c58ec932 7989 would_hit_hwbug = 1;
1da177e4 7990
84b67b27 7991 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
d1a3b737 7992 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
ba1142e4 7993 mss, vlan)) {
d1a3b737 7994 would_hit_hwbug = 1;
ba1142e4 7995 } else if (skb_shinfo(skb)->nr_frags > 0) {
92cd3a17
MC		 7996 u32 tmp_mss = mss;
7997
7998 if (!tg3_flag(tp, HW_TSO_1) &&
7999 !tg3_flag(tp, HW_TSO_2) &&
8000 !tg3_flag(tp, HW_TSO_3))
8001 tmp_mss = 0;
8002
c5665a53
MC		 8003 /* Now loop through additional data
8004 * fragments, and queue them.
8005 */
1da177e4
LT		 8006 last = skb_shinfo(skb)->nr_frags - 1;
8007 for (i = 0; i <= last; i++) {
8008 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8009
9e903e08 8010 len = skb_frag_size(frag);
dc234d0b 8011 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
5d6bcdfe 8012 len, DMA_TO_DEVICE);
1da177e4 8013
f3f3f27e 8014 tnapi->tx_buffers[entry].skb = NULL;
4e5e4f0d 8015 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
f4188d8a 8016 mapping);
5d6bcdfe 8017 if (dma_mapping_error(&tp->pdev->dev, mapping))
f4188d8a 8018 goto dma_error;
1da177e4 8019
b9e45482
MC		 8020 if (!budget ||
8021 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
84b67b27
MC		 8022 len, base_flags |
8023 ((i == last) ? TXD_FLAG_END : 0),
b9e45482 8024 tmp_mss, vlan)) {
72f2afb8 8025 would_hit_hwbug = 1;
b9e45482
MC		 8026 break;
8027 }
1da177e4
LT		 8028 }
8029 }
8030
8031 if (would_hit_hwbug) {
0d681b27 8032 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
1da177e4
LT		 8033
8034 /* If the workaround fails due to memory/mapping
8035 * failure, silently drop this packet.
8036 */
84b67b27
MC		 8037 entry = tnapi->tx_prod;
8038 budget = tg3_tx_avail(tnapi);
f7ff1987 8039 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
84b67b27 8040 base_flags, mss, vlan))
48855432 8041 goto drop_nofree;
1da177e4
LT		 8042 }
8043
d515b450 8044 skb_tx_timestamp(skb);
5cb917bc 8045 netdev_tx_sent_queue(txq, skb->len);
d515b450 8046
6541b806
MC		 8047 /* Sync BD data before updating mailbox */
8048 wmb();
8049
1da177e4 8050 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 8051 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 8052
f3f3f27e
MC		 8053 tnapi->tx_prod = entry;
8054 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 8055 netif_tx_stop_queue(txq);
f65aac16
MC		 8056
8057 /* netif_tx_stop_queue() must be done before checking
8058 * checking tx index in tg3_tx_avail() below, because in
8059 * tg3_tx(), we update tx index before checking for
8060 * netif_tx_queue_stopped().
8061 */
8062 smp_mb();
f3f3f27e 8063 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 8064 netif_tx_wake_queue(txq);
51b91468 8065 }
1da177e4 8066
cdd0db05 8067 mmiowb();
1da177e4 8068 return NETDEV_TX_OK;
f4188d8a
AD		 8069
8070dma_error:
ba1142e4 8071 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
432aa7ed 8072 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
48855432
ED		 8073drop:
8074 dev_kfree_skb(skb);
8075drop_nofree:
8076 tp->tx_dropped++;
f4188d8a 8077 return NETDEV_TX_OK;
1da177e4
LT		 8078}
8079
6e01b20b
MC		 8080static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8081{
8082 if (enable) {
8083 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8084 MAC_MODE_PORT_MODE_MASK);
8085
8086 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8087
8088 if (!tg3_flag(tp, 5705_PLUS))
8089 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8090
8091 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8092 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8093 else
8094 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8095 } else {
8096 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8097
8098 if (tg3_flag(tp, 5705_PLUS) ||
8099 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
4153577a 8100 tg3_asic_rev(tp) == ASIC_REV_5700)
6e01b20b
MC		 8101 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8102 }
8103
8104 tw32(MAC_MODE, tp->mac_mode);
8105 udelay(40);
8106}
8107
941ec90f 8108static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
5e5a7f37 8109{
941ec90f 8110 u32 val, bmcr, mac_mode, ptest = 0;
5e5a7f37
MC		 8111
8112 tg3_phy_toggle_apd(tp, false);
953c96e0 8113 tg3_phy_toggle_automdix(tp, false);
5e5a7f37 8114
941ec90f
MC		 8115 if (extlpbk && tg3_phy_set_extloopbk(tp))
8116 return -EIO;
8117
8118 bmcr = BMCR_FULLDPLX;
5e5a7f37
MC		 8119 switch (speed) {
8120 case SPEED_10:
8121 break;
8122 case SPEED_100:
8123 bmcr |= BMCR_SPEED100;
8124 break;
8125 case SPEED_1000:
8126 default:
8127 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8128 speed = SPEED_100;
8129 bmcr |= BMCR_SPEED100;
8130 } else {
8131 speed = SPEED_1000;
8132 bmcr |= BMCR_SPEED1000;
8133 }
8134 }
8135
941ec90f
MC		 8136 if (extlpbk) {
8137 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8138 tg3_readphy(tp, MII_CTRL1000, &val);
8139 val |= CTL1000_AS_MASTER |
8140 CTL1000_ENABLE_MASTER;
8141 tg3_writephy(tp, MII_CTRL1000, val);
8142 } else {
8143 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8144 MII_TG3_FET_PTEST_TRIM_2;
8145 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8146 }
8147 } else
8148 bmcr |= BMCR_LOOPBACK;
8149
5e5a7f37
MC		 8150 tg3_writephy(tp, MII_BMCR, bmcr);
8151
8152 /* The write needs to be flushed for the FETs */
8153 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8154 tg3_readphy(tp, MII_BMCR, &bmcr);
8155
8156 udelay(40);
8157
8158 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a 8159 tg3_asic_rev(tp) == ASIC_REV_5785) {
941ec90f 8160 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
5e5a7f37
MC		 8161 MII_TG3_FET_PTEST_FRC_TX_LINK |
8162 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8163
8164 /* The write needs to be flushed for the AC131 */
8165 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8166 }
8167
8168 /* Reset to prevent losing 1st rx packet intermittently */
8169 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8170 tg3_flag(tp, 5780_CLASS)) {
8171 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8172 udelay(10);
8173 tw32_f(MAC_RX_MODE, tp->rx_mode);
8174 }
8175
8176 mac_mode = tp->mac_mode &
8177 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8178 if (speed == SPEED_1000)
8179 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8180 else
8181 mac_mode |= MAC_MODE_PORT_MODE_MII;
8182
4153577a 8183 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5e5a7f37
MC		 8184 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8185
8186 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8187 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8188 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8189 mac_mode |= MAC_MODE_LINK_POLARITY;
8190
8191 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8192 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8193 }
8194
8195 tw32(MAC_MODE, mac_mode);
8196 udelay(40);
941ec90f
MC		 8197
8198 return 0;
5e5a7f37
MC		 8199}
8200
c8f44aff 8201static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
06c03c02
MB		 8202{
8203 struct tg3 *tp = netdev_priv(dev);
8204
8205 if (features & NETIF_F_LOOPBACK) {
8206 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8207 return;
8208
06c03c02 8209 spin_lock_bh(&tp->lock);
6e01b20b 8210 tg3_mac_loopback(tp, true);
06c03c02
MB		 8211 netif_carrier_on(tp->dev);
8212 spin_unlock_bh(&tp->lock);
8213 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8214 } else {
8215 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8216 return;
8217
06c03c02 8218 spin_lock_bh(&tp->lock);
6e01b20b 8219 tg3_mac_loopback(tp, false);
06c03c02 8220 /* Force link status check */
953c96e0 8221 tg3_setup_phy(tp, true);
06c03c02
MB		 8222 spin_unlock_bh(&tp->lock);
8223 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8224 }
8225}
8226
c8f44aff
MM		 8227static netdev_features_t tg3_fix_features(struct net_device *dev,
8228 netdev_features_t features)
dc668910
MM		 8229{
8230 struct tg3 *tp = netdev_priv(dev);
8231
63c3a66f 8232 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
dc668910
MM		 8233 features &= ~NETIF_F_ALL_TSO;
8234
8235 return features;
8236}
8237
c8f44aff 8238static int tg3_set_features(struct net_device *dev, netdev_features_t features)
06c03c02 8239{
c8f44aff 8240 netdev_features_t changed = dev->features ^ features;
06c03c02
MB		 8241
8242 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8243 tg3_set_loopback(dev, features);
8244
8245 return 0;
8246}
8247
21f581a5
MC		 8248static void tg3_rx_prodring_free(struct tg3 *tp,
8249 struct tg3_rx_prodring_set *tpr)
1da177e4 8250{
1da177e4
LT		 8251 int i;
8252
8fea32b9 8253 if (tpr != &tp->napi[0].prodring) {
b196c7e4 8254 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
2c49a44d 8255 i = (i + 1) & tp->rx_std_ring_mask)
9205fd9c 8256 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
b196c7e4
MC		 8257 tp->rx_pkt_map_sz);
8258
63c3a66f 8259 if (tg3_flag(tp, JUMBO_CAPABLE)) {
b196c7e4
MC		 8260 for (i = tpr->rx_jmb_cons_idx;
8261 i != tpr->rx_jmb_prod_idx;
2c49a44d 8262 i = (i + 1) & tp->rx_jmb_ring_mask) {
9205fd9c 8263 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
b196c7e4
MC		 8264 TG3_RX_JMB_MAP_SZ);
8265 }
8266 }
8267
2b2cdb65 8268 return;
b196c7e4 8269 }
1da177e4 8270
2c49a44d 8271 for (i = 0; i <= tp->rx_std_ring_mask; i++)
9205fd9c 8272 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
2b2cdb65 8273 tp->rx_pkt_map_sz);
1da177e4 8274
63c3a66f 8275 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8276 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
9205fd9c 8277 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
2b2cdb65 8278 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 8279 }
8280}
8281
c6cdf436 8282/* Initialize rx rings for packet processing.
1da177e4
LT		 8283 *
8284 * The chip has been shut down and the driver detached from
8285 * the networking, so no interrupts or new tx packets will
8286 * end up in the driver. tp->{tx,}lock are held and thus
8287 * we may not sleep.
8288 */
21f581a5
MC		 8289static int tg3_rx_prodring_alloc(struct tg3 *tp,
8290 struct tg3_rx_prodring_set *tpr)
1da177e4 8291{
287be12e 8292 u32 i, rx_pkt_dma_sz;
1da177e4 8293
b196c7e4
MC		 8294 tpr->rx_std_cons_idx = 0;
8295 tpr->rx_std_prod_idx = 0;
8296 tpr->rx_jmb_cons_idx = 0;
8297 tpr->rx_jmb_prod_idx = 0;
8298
8fea32b9 8299 if (tpr != &tp->napi[0].prodring) {
2c49a44d
MC		 8300 memset(&tpr->rx_std_buffers[0], 0,
8301 TG3_RX_STD_BUFF_RING_SIZE(tp));
48035728 8302 if (tpr->rx_jmb_buffers)
2b2cdb65 8303 memset(&tpr->rx_jmb_buffers[0], 0,
2c49a44d 8304 TG3_RX_JMB_BUFF_RING_SIZE(tp));
2b2cdb65
MC		 8305 goto done;
8306 }
8307
1da177e4 8308 /* Zero out all descriptors. */
2c49a44d 8309 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
1da177e4 8310
287be12e 8311 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
63c3a66f 8312 if (tg3_flag(tp, 5780_CLASS) &&
287be12e
MC		 8313 tp->dev->mtu > ETH_DATA_LEN)
8314 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8315 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 8316
1da177e4
LT		 8317 /* Initialize invariants of the rings, we only set this
8318 * stuff once. This works because the card does not
8319 * write into the rx buffer posting rings.
8320 */
2c49a44d 8321 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
1da177e4
LT		 8322 struct tg3_rx_buffer_desc *rxd;
8323
21f581a5 8324 rxd = &tpr->rx_std[i];
287be12e 8325 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 8326 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8327 rxd->opaque = (RXD_OPAQUE_RING_STD |
8328 (i << RXD_OPAQUE_INDEX_SHIFT));
8329 }
8330
1da177e4
LT		 8331 /* Now allocate fresh SKBs for each rx ring. */
8332 for (i = 0; i < tp->rx_pending; i++) {
8d4057a9
ED		 8333 unsigned int frag_size;
8334
8335 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8336 &frag_size) < 0) {
5129c3a3
MC		 8337 netdev_warn(tp->dev,
8338 "Using a smaller RX standard ring. Only "
8339 "%d out of %d buffers were allocated "
8340 "successfully\n", i, tp->rx_pending);
32d8c572 8341 if (i == 0)
cf7a7298 8342 goto initfail;
32d8c572 8343 tp->rx_pending = i;
1da177e4 8344 break;
32d8c572 8345 }
1da177e4
LT		 8346 }
8347
63c3a66f 8348 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
cf7a7298
MC		 8349 goto done;
8350
2c49a44d 8351 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
cf7a7298 8352
63c3a66f 8353 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
0d86df80 8354 goto done;
cf7a7298 8355
2c49a44d 8356 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
0d86df80
MC		 8357 struct tg3_rx_buffer_desc *rxd;
8358
8359 rxd = &tpr->rx_jmb[i].std;
8360 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8361 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8362 RXD_FLAG_JUMBO;
8363 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8364 (i << RXD_OPAQUE_INDEX_SHIFT));
8365 }
8366
8367 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8d4057a9
ED		 8368 unsigned int frag_size;
8369
8370 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8371 &frag_size) < 0) {
5129c3a3
MC		 8372 netdev_warn(tp->dev,
8373 "Using a smaller RX jumbo ring. Only %d "
8374 "out of %d buffers were allocated "
8375 "successfully\n", i, tp->rx_jumbo_pending);
0d86df80
MC		 8376 if (i == 0)
8377 goto initfail;
8378 tp->rx_jumbo_pending = i;
8379 break;
1da177e4
LT		 8380 }
8381 }
cf7a7298
MC		 8382
8383done:
32d8c572 8384 return 0;
cf7a7298
MC		 8385
8386initfail:
21f581a5 8387 tg3_rx_prodring_free(tp, tpr);
cf7a7298 8388 return -ENOMEM;
1da177e4
LT		 8389}
8390
21f581a5
MC		 8391static void tg3_rx_prodring_fini(struct tg3 *tp,
8392 struct tg3_rx_prodring_set *tpr)
1da177e4 8393{
21f581a5
MC		 8394 kfree(tpr->rx_std_buffers);
8395 tpr->rx_std_buffers = NULL;
8396 kfree(tpr->rx_jmb_buffers);
8397 tpr->rx_jmb_buffers = NULL;
8398 if (tpr->rx_std) {
4bae65c8
MC		 8399 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8400 tpr->rx_std, tpr->rx_std_mapping);
21f581a5 8401 tpr->rx_std = NULL;
1da177e4 8402 }
21f581a5 8403 if (tpr->rx_jmb) {
4bae65c8
MC		 8404 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8405 tpr->rx_jmb, tpr->rx_jmb_mapping);
21f581a5 8406 tpr->rx_jmb = NULL;
1da177e4 8407 }
cf7a7298
MC		 8408}
8409
21f581a5
MC		 8410static int tg3_rx_prodring_init(struct tg3 *tp,
8411 struct tg3_rx_prodring_set *tpr)
cf7a7298 8412{
2c49a44d
MC		 8413 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8414 GFP_KERNEL);
21f581a5 8415 if (!tpr->rx_std_buffers)
cf7a7298
MC		 8416 return -ENOMEM;
8417
4bae65c8
MC		 8418 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8419 TG3_RX_STD_RING_BYTES(tp),
8420 &tpr->rx_std_mapping,
8421 GFP_KERNEL);
21f581a5 8422 if (!tpr->rx_std)
cf7a7298
MC		 8423 goto err_out;
8424
63c3a66f 8425 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8426 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
21f581a5
MC		 8427 GFP_KERNEL);
8428 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 8429 goto err_out;
8430
4bae65c8
MC		 8431 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8432 TG3_RX_JMB_RING_BYTES(tp),
8433 &tpr->rx_jmb_mapping,
8434 GFP_KERNEL);
21f581a5 8435 if (!tpr->rx_jmb)
cf7a7298
MC		 8436 goto err_out;
8437 }
8438
8439 return 0;
8440
8441err_out:
21f581a5 8442 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 8443 return -ENOMEM;
8444}
8445
8446/* Free up pending packets in all rx/tx rings.
8447 *
8448 * The chip has been shut down and the driver detached from
8449 * the networking, so no interrupts or new tx packets will
8450 * end up in the driver. tp->{tx,}lock is not held and we are not
8451 * in an interrupt context and thus may sleep.
8452 */
8453static void tg3_free_rings(struct tg3 *tp)
8454{
f77a6a8e 8455 int i, j;
cf7a7298 8456
f77a6a8e
MC		 8457 for (j = 0; j < tp->irq_cnt; j++) {
8458 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 8459
8fea32b9 8460 tg3_rx_prodring_free(tp, &tnapi->prodring);
b28f6428 8461
0c1d0e2b
MC		 8462 if (!tnapi->tx_buffers)
8463 continue;
8464
0d681b27
MC		 8465 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8466 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
cf7a7298 8467
0d681b27 8468 if (!skb)
f77a6a8e 8469 continue;
cf7a7298 8470
ba1142e4
MC		 8471 tg3_tx_skb_unmap(tnapi, i,
8472 skb_shinfo(skb)->nr_frags - 1);
f77a6a8e
MC		 8473
8474 dev_kfree_skb_any(skb);
8475 }
5cb917bc 8476 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
2b2cdb65 8477 }
cf7a7298
MC		 8478}
8479
8480/* Initialize tx/rx rings for packet processing.
8481 *
8482 * The chip has been shut down and the driver detached from
8483 * the networking, so no interrupts or new tx packets will
8484 * end up in the driver. tp->{tx,}lock are held and thus
8485 * we may not sleep.
8486 */
8487static int tg3_init_rings(struct tg3 *tp)
8488{
f77a6a8e 8489 int i;
72334482 8490
cf7a7298
MC		 8491 /* Free up all the SKBs. */
8492 tg3_free_rings(tp);
8493
f77a6a8e
MC		 8494 for (i = 0; i < tp->irq_cnt; i++) {
8495 struct tg3_napi *tnapi = &tp->napi[i];
8496
8497 tnapi->last_tag = 0;
8498 tnapi->last_irq_tag = 0;
8499 tnapi->hw_status->status = 0;
8500 tnapi->hw_status->status_tag = 0;
8501 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 8502
f77a6a8e
MC		 8503 tnapi->tx_prod = 0;
8504 tnapi->tx_cons = 0;
0c1d0e2b
MC		 8505 if (tnapi->tx_ring)
8506 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 8507
8508 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 8509 if (tnapi->rx_rcb)
8510 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 8511
8fea32b9 8512 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
e4af1af9 8513 tg3_free_rings(tp);
2b2cdb65 8514 return -ENOMEM;
e4af1af9 8515 }
f77a6a8e 8516 }
72334482 8517
2b2cdb65 8518 return 0;
cf7a7298
MC		 8519}
8520
49a359e3 8521static void tg3_mem_tx_release(struct tg3 *tp)
cf7a7298 8522{
f77a6a8e 8523 int i;
898a56f8 8524
49a359e3 8525 for (i = 0; i < tp->irq_max; i++) {
f77a6a8e
MC		 8526 struct tg3_napi *tnapi = &tp->napi[i];
8527
8528 if (tnapi->tx_ring) {
4bae65c8 8529 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
f77a6a8e
MC		 8530 tnapi->tx_ring, tnapi->tx_desc_mapping);
8531 tnapi->tx_ring = NULL;
8532 }
8533
8534 kfree(tnapi->tx_buffers);
8535 tnapi->tx_buffers = NULL;
49a359e3
MC		 8536 }
8537}
f77a6a8e 8538
49a359e3
MC		 8539static int tg3_mem_tx_acquire(struct tg3 *tp)
8540{
8541 int i;
8542 struct tg3_napi *tnapi = &tp->napi[0];
8543
8544 /* If multivector TSS is enabled, vector 0 does not handle
8545 * tx interrupts. Don't allocate any resources for it.
8546 */
8547 if (tg3_flag(tp, ENABLE_TSS))
8548 tnapi++;
8549
8550 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8551 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8552 TG3_TX_RING_SIZE, GFP_KERNEL);
8553 if (!tnapi->tx_buffers)
8554 goto err_out;
8555
8556 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8557 TG3_TX_RING_BYTES,
8558 &tnapi->tx_desc_mapping,
8559 GFP_KERNEL);
8560 if (!tnapi->tx_ring)
8561 goto err_out;
8562 }
8563
8564 return 0;
8565
8566err_out:
8567 tg3_mem_tx_release(tp);
8568 return -ENOMEM;
8569}
8570
8571static void tg3_mem_rx_release(struct tg3 *tp)
8572{
8573 int i;
8574
8575 for (i = 0; i < tp->irq_max; i++) {
8576 struct tg3_napi *tnapi = &tp->napi[i];
f77a6a8e 8577
8fea32b9
MC		 8578 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8579
49a359e3
MC		 8580 if (!tnapi->rx_rcb)
8581 continue;
8582
8583 dma_free_coherent(&tp->pdev->dev,
8584 TG3_RX_RCB_RING_BYTES(tp),
8585 tnapi->rx_rcb,
8586 tnapi->rx_rcb_mapping);
8587 tnapi->rx_rcb = NULL;
8588 }
8589}
8590
8591static int tg3_mem_rx_acquire(struct tg3 *tp)
8592{
8593 unsigned int i, limit;
8594
8595 limit = tp->rxq_cnt;
8596
8597 /* If RSS is enabled, we need a (dummy) producer ring
8598 * set on vector zero. This is the true hw prodring.
8599 */
8600 if (tg3_flag(tp, ENABLE_RSS))
8601 limit++;
8602
8603 for (i = 0; i < limit; i++) {
8604 struct tg3_napi *tnapi = &tp->napi[i];
8605
8606 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8607 goto err_out;
8608
8609 /* If multivector RSS is enabled, vector 0
8610 * does not handle rx or tx interrupts.
8611 * Don't allocate any resources for it.
8612 */
8613 if (!i && tg3_flag(tp, ENABLE_RSS))
8614 continue;
8615
ede23fa8
JP		 8616 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8617 TG3_RX_RCB_RING_BYTES(tp),
8618 &tnapi->rx_rcb_mapping,
8619 GFP_KERNEL);
49a359e3
MC		 8620 if (!tnapi->rx_rcb)
8621 goto err_out;
49a359e3
MC		 8622 }
8623
8624 return 0;
8625
8626err_out:
8627 tg3_mem_rx_release(tp);
8628 return -ENOMEM;
8629}
8630
8631/*
8632 * Must not be invoked with interrupt sources disabled and
8633 * the hardware shutdown down.
8634 */
8635static void tg3_free_consistent(struct tg3 *tp)
8636{
8637 int i;
8638
8639 for (i = 0; i < tp->irq_cnt; i++) {
8640 struct tg3_napi *tnapi = &tp->napi[i];
8641
f77a6a8e 8642 if (tnapi->hw_status) {
4bae65c8
MC		 8643 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8644 tnapi->hw_status,
8645 tnapi->status_mapping);
f77a6a8e
MC		 8646 tnapi->hw_status = NULL;
8647 }
1da177e4 8648 }
f77a6a8e 8649
49a359e3
MC		 8650 tg3_mem_rx_release(tp);
8651 tg3_mem_tx_release(tp);
8652
1da177e4 8653 if (tp->hw_stats) {
4bae65c8
MC		 8654 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8655 tp->hw_stats, tp->stats_mapping);
1da177e4
LT		 8656 tp->hw_stats = NULL;
8657 }
8658}
8659
8660/*
8661 * Must not be invoked with interrupt sources disabled and
8662 * the hardware shutdown down. Can sleep.
8663 */
8664static int tg3_alloc_consistent(struct tg3 *tp)
8665{
f77a6a8e 8666 int i;
898a56f8 8667
ede23fa8
JP		 8668 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8669 sizeof(struct tg3_hw_stats),
8670 &tp->stats_mapping, GFP_KERNEL);
f77a6a8e 8671 if (!tp->hw_stats)
1da177e4
LT		 8672 goto err_out;
8673
f77a6a8e
MC		 8674 for (i = 0; i < tp->irq_cnt; i++) {
8675 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 8676 struct tg3_hw_status *sblk;
1da177e4 8677
ede23fa8
JP		 8678 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8679 TG3_HW_STATUS_SIZE,
8680 &tnapi->status_mapping,
8681 GFP_KERNEL);
f77a6a8e
MC		 8682 if (!tnapi->hw_status)
8683 goto err_out;
898a56f8 8684
8d9d7cfc
MC		 8685 sblk = tnapi->hw_status;
8686
49a359e3 8687 if (tg3_flag(tp, ENABLE_RSS)) {
86449944 8688 u16 *prodptr = NULL;
8fea32b9 8689
49a359e3
MC		 8690 /*
8691 * When RSS is enabled, the status block format changes
8692 * slightly. The "rx_jumbo_consumer", "reserved",
8693 * and "rx_mini_consumer" members get mapped to the
8694 * other three rx return ring producer indexes.
8695 */
8696 switch (i) {
8697 case 1:
8698 prodptr = &sblk->idx[0].rx_producer;
8699 break;
8700 case 2:
8701 prodptr = &sblk->rx_jumbo_consumer;
8702 break;
8703 case 3:
8704 prodptr = &sblk->reserved;
8705 break;
8706 case 4:
8707 prodptr = &sblk->rx_mini_consumer;
f891ea16
MC		 8708 break;
8709 }
49a359e3
MC		 8710 tnapi->rx_rcb_prod_idx = prodptr;
8711 } else {
8d9d7cfc 8712 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8d9d7cfc 8713 }
f77a6a8e 8714 }
1da177e4 8715
49a359e3
MC		 8716 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8717 goto err_out;
8718
1da177e4
LT		 8719 return 0;
8720
8721err_out:
8722 tg3_free_consistent(tp);
8723 return -ENOMEM;
8724}
8725
8726#define MAX_WAIT_CNT 1000
8727
8728/* To stop a block, clear the enable bit and poll till it
8729 * clears. tp->lock is held.
8730 */
953c96e0 8731static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
1da177e4
LT		 8732{
8733 unsigned int i;
8734 u32 val;
8735
63c3a66f 8736 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 8737 switch (ofs) {
8738 case RCVLSC_MODE:
8739 case DMAC_MODE:
8740 case MBFREE_MODE:
8741 case BUFMGR_MODE:
8742 case MEMARB_MODE:
8743 /* We can't enable/disable these bits of the
8744 * 5705/5750, just say success.
8745 */
8746 return 0;
8747
8748 default:
8749 break;
855e1111 8750 }
1da177e4
LT		 8751 }
8752
8753 val = tr32(ofs);
8754 val &= ~enable_bit;
8755 tw32_f(ofs, val);
8756
8757 for (i = 0; i < MAX_WAIT_CNT; i++) {
6d446ec3
GS		 8758 if (pci_channel_offline(tp->pdev)) {
8759 dev_err(&tp->pdev->dev,
8760 "tg3_stop_block device offline, "
8761 "ofs=%lx enable_bit=%x\n",
8762 ofs, enable_bit);
8763 return -ENODEV;
8764 }
8765
1da177e4
LT		 8766 udelay(100);
8767 val = tr32(ofs);
8768 if ((val & enable_bit) == 0)
8769 break;
8770 }
8771
b3b7d6be 8772 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 8773 dev_err(&tp->pdev->dev,
8774 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8775 ofs, enable_bit);
1da177e4
LT		 8776 return -ENODEV;
8777 }
8778
8779 return 0;
8780}
8781
8782/* tp->lock is held. */
953c96e0 8783static int tg3_abort_hw(struct tg3 *tp, bool silent)
1da177e4
LT		 8784{
8785 int i, err;
8786
8787 tg3_disable_ints(tp);
8788
6d446ec3
GS		 8789 if (pci_channel_offline(tp->pdev)) {
8790 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8791 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8792 err = -ENODEV;
8793 goto err_no_dev;
8794 }
8795
1da177e4
LT		 8796 tp->rx_mode &= ~RX_MODE_ENABLE;
8797 tw32_f(MAC_RX_MODE, tp->rx_mode);
8798 udelay(10);
8799
b3b7d6be
DM		 8800 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8801 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8802 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8803 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8804 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8805 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8806
8807 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8808 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8809 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8810 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8811 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8812 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8813 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 8814
8815 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8816 tw32_f(MAC_MODE, tp->mac_mode);
8817 udelay(40);
8818
8819 tp->tx_mode &= ~TX_MODE_ENABLE;
8820 tw32_f(MAC_TX_MODE, tp->tx_mode);
8821
8822 for (i = 0; i < MAX_WAIT_CNT; i++) {
8823 udelay(100);
8824 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8825 break;
8826 }
8827 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 8828 dev_err(&tp->pdev->dev,
8829 "%s timed out, TX_MODE_ENABLE will not clear "
8830 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 8831 err |= -ENODEV;
1da177e4
LT		 8832 }
8833
e6de8ad1 8834 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 8835 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8836 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 8837
8838 tw32(FTQ_RESET, 0xffffffff);
8839 tw32(FTQ_RESET, 0x00000000);
8840
b3b7d6be
DM		 8841 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8842 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 8843
6d446ec3 8844err_no_dev:
f77a6a8e
MC		 8845 for (i = 0; i < tp->irq_cnt; i++) {
8846 struct tg3_napi *tnapi = &tp->napi[i];
8847 if (tnapi->hw_status)
8848 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8849 }
1da177e4 8850
1da177e4
LT		 8851 return err;
8852}
8853
ee6a99b5
MC		 8854/* Save PCI command register before chip reset */
8855static void tg3_save_pci_state(struct tg3 *tp)
8856{
8a6eac90 8857 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 8858}
8859
8860/* Restore PCI state after chip reset */
8861static void tg3_restore_pci_state(struct tg3 *tp)
8862{
8863 u32 val;
8864
8865 /* Re-enable indirect register accesses. */
8866 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8867 tp->misc_host_ctrl);
8868
8869 /* Set MAX PCI retry to zero. */
8870 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4153577a 8871 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 8872 tg3_flag(tp, PCIX_MODE))
ee6a99b5 8873 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9 8874 /* Allow reads and writes to the APE register and memory space. */
63c3a66f 8875 if (tg3_flag(tp, ENABLE_APE))
0d3031d9 8876 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 8877 PCISTATE_ALLOW_APE_SHMEM_WR |
8878 PCISTATE_ALLOW_APE_PSPACE_WR;
ee6a99b5
MC		 8879 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8880
8a6eac90 8881 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 8882
2c55a3d0
MC		 8883 if (!tg3_flag(tp, PCI_EXPRESS)) {
8884 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8885 tp->pci_cacheline_sz);
8886 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8887 tp->pci_lat_timer);
114342f2 8888 }
5f5c51e3 8889
ee6a99b5 8890 /* Make sure PCI-X relaxed ordering bit is clear. */
63c3a66f 8891 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 8892 u16 pcix_cmd;
8893
8894 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8895 &pcix_cmd);
8896 pcix_cmd &= ~PCI_X_CMD_ERO;
8897 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8898 pcix_cmd);
8899 }
ee6a99b5 8900
63c3a66f 8901 if (tg3_flag(tp, 5780_CLASS)) {
ee6a99b5
MC		 8902
8903 /* Chip reset on 5780 will reset MSI enable bit,
8904 * so need to restore it.
8905 */
63c3a66f 8906 if (tg3_flag(tp, USING_MSI)) {
ee6a99b5
MC		 8907 u16 ctrl;
8908
8909 pci_read_config_word(tp->pdev,
8910 tp->msi_cap + PCI_MSI_FLAGS,
8911 &ctrl);
8912 pci_write_config_word(tp->pdev,
8913 tp->msi_cap + PCI_MSI_FLAGS,
8914 ctrl | PCI_MSI_FLAGS_ENABLE);
8915 val = tr32(MSGINT_MODE);
8916 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8917 }
8918 }
8919}
8920
1da177e4
LT		 8921/* tp->lock is held. */
8922static int tg3_chip_reset(struct tg3 *tp)
8923{
8924 u32 val;
1ee582d8 8925 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 8926 int i, err;
1da177e4 8927
f49639e6
DM		 8928 tg3_nvram_lock(tp);
8929
77b483f1
MC		 8930 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
8931
f49639e6
DM		 8932 /* No matching tg3_nvram_unlock() after this because
8933 * chip reset below will undo the nvram lock.
8934 */
8935 tp->nvram_lock_cnt = 0;
1da177e4 8936
ee6a99b5
MC		 8937 /* GRC_MISC_CFG core clock reset will clear the memory
8938 * enable bit in PCI register 4 and the MSI enable bit
8939 * on some chips, so we save relevant registers here.
8940 */
8941 tg3_save_pci_state(tp);
8942
4153577a 8943 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
63c3a66f 8944 tg3_flag(tp, 5755_PLUS))
d9ab5ad1
MC		 8945 tw32(GRC_FASTBOOT_PC, 0);
8946
1da177e4
LT		 8947 /*
8948 * We must avoid the readl() that normally takes place.
8949 * It locks machines, causes machine checks, and other
8950 * fun things. So, temporarily disable the 5701
8951 * hardware workaround, while we do the reset.
8952 */
1ee582d8
MC		 8953 write_op = tp->write32;
8954 if (write_op == tg3_write_flush_reg32)
8955 tp->write32 = tg3_write32;
1da177e4 8956
d18edcb2
MC		 8957 /* Prevent the irq handler from reading or writing PCI registers
8958 * during chip reset when the memory enable bit in the PCI command
8959 * register may be cleared. The chip does not generate interrupt
8960 * at this time, but the irq handler may still be called due to irq
8961 * sharing or irqpoll.
8962 */
63c3a66f 8963 tg3_flag_set(tp, CHIP_RESETTING);
f77a6a8e
MC		 8964 for (i = 0; i < tp->irq_cnt; i++) {
8965 struct tg3_napi *tnapi = &tp->napi[i];
8966 if (tnapi->hw_status) {
8967 tnapi->hw_status->status = 0;
8968 tnapi->hw_status->status_tag = 0;
8969 }
8970 tnapi->last_tag = 0;
8971 tnapi->last_irq_tag = 0;
b8fa2f3a 8972 }
d18edcb2 8973 smp_mb();
4f125f42
MC		 8974
8975 for (i = 0; i < tp->irq_cnt; i++)
8976 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 8977
4153577a 8978 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
255ca311
MC		 8979 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8980 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8981 }
8982
1da177e4
LT		 8983 /* do the reset */
8984 val = GRC_MISC_CFG_CORECLK_RESET;
8985
63c3a66f 8986 if (tg3_flag(tp, PCI_EXPRESS)) {
88075d91 8987 /* Force PCIe 1.0a mode */
4153577a 8988 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 8989 !tg3_flag(tp, 57765_PLUS) &&
88075d91
MC		 8990 tr32(TG3_PCIE_PHY_TSTCTL) ==
8991 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
8992 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
8993
4153577a 8994 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
1da177e4
LT		 8995 tw32(GRC_MISC_CFG, (1 << 29));
8996 val |= (1 << 29);
8997 }
8998 }
8999
4153577a 9000 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 9001 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9002 tw32(GRC_VCPU_EXT_CTRL,
9003 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9004 }
9005
f37500d3 9006 /* Manage gphy power for all CPMU absent PCIe devices. */
63c3a66f 9007 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
1da177e4 9008 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
f37500d3 9009
1da177e4
LT		 9010 tw32(GRC_MISC_CFG, val);
9011
1ee582d8
MC		 9012 /* restore 5701 hardware bug workaround write method */
9013 tp->write32 = write_op;
1da177e4
LT		 9014
9015 /* Unfortunately, we have to delay before the PCI read back.
9016 * Some 575X chips even will not respond to a PCI cfg access
9017 * when the reset command is given to the chip.
9018 *
9019 * How do these hardware designers expect things to work
9020 * properly if the PCI write is posted for a long period
9021 * of time? It is always necessary to have some method by
9022 * which a register read back can occur to push the write
9023 * out which does the reset.
9024 *
9025 * For most tg3 variants the trick below was working.
9026 * Ho hum...
9027 */
9028 udelay(120);
9029
9030 /* Flush PCI posted writes. The normal MMIO registers
9031 * are inaccessible at this time so this is the only
9032 * way to make this reliably (actually, this is no longer
9033 * the case, see above). I tried to use indirect
9034 * register read/write but this upset some 5701 variants.
9035 */
9036 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9037
9038 udelay(120);
9039
0f49bfbd 9040 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
e7126997
MC		 9041 u16 val16;
9042
4153577a 9043 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
86449944 9044 int j;
1da177e4
LT		 9045 u32 cfg_val;
9046
9047 /* Wait for link training to complete. */
86449944 9048 for (j = 0; j < 5000; j++)
1da177e4
LT		 9049 udelay(100);
9050
9051 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9052 pci_write_config_dword(tp->pdev, 0xc4,
9053 cfg_val | (1 << 15));
9054 }
5e7dfd0f 9055
e7126997 9056 /* Clear the "no snoop" and "relaxed ordering" bits. */
0f49bfbd 9057 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
e7126997
MC		 9058 /*
9059 * Older PCIe devices only support the 128 byte
9060 * MPS setting. Enforce the restriction.
5e7dfd0f 9061 */
63c3a66f 9062 if (!tg3_flag(tp, CPMU_PRESENT))
0f49bfbd
JL		 9063 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9064 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
5e7dfd0f 9065
5e7dfd0f 9066 /* Clear error status */
0f49bfbd 9067 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
5e7dfd0f
MC		 9068 PCI_EXP_DEVSTA_CED |
9069 PCI_EXP_DEVSTA_NFED |
9070 PCI_EXP_DEVSTA_FED |
9071 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 9072 }
9073
ee6a99b5 9074 tg3_restore_pci_state(tp);
1da177e4 9075
63c3a66f
JP		 9076 tg3_flag_clear(tp, CHIP_RESETTING);
9077 tg3_flag_clear(tp, ERROR_PROCESSED);
d18edcb2 9078
ee6a99b5 9079 val = 0;
63c3a66f 9080 if (tg3_flag(tp, 5780_CLASS))
4cf78e4f 9081 val = tr32(MEMARB_MODE);
ee6a99b5 9082 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4 9083
4153577a 9084 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
1da177e4
LT		 9085 tg3_stop_fw(tp);
9086 tw32(0x5000, 0x400);
9087 }
9088
7e6c63f0
HM		 9089 if (tg3_flag(tp, IS_SSB_CORE)) {
9090 /*
9091 * BCM4785: In order to avoid repercussions from using
9092 * potentially defective internal ROM, stop the Rx RISC CPU,
9093 * which is not required.
9094 */
9095 tg3_stop_fw(tp);
9096 tg3_halt_cpu(tp, RX_CPU_BASE);
9097 }
9098
fb03a43f
NS		 9099 err = tg3_poll_fw(tp);
9100 if (err)
9101 return err;
9102
1da177e4
LT		 9103 tw32(GRC_MODE, tp->grc_mode);
9104
4153577a 9105 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
ab0049b4 9106 val = tr32(0xc4);
1da177e4
LT		 9107
9108 tw32(0xc4, val | (1 << 15));
9109 }
9110
9111 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4153577a 9112 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4 9113 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4153577a 9114 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
1da177e4
LT		 9115 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9116 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9117 }
9118
f07e9af3 9119 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9e975cc2 9120 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
d2394e6b 9121 val = tp->mac_mode;
f07e9af3 9122 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9e975cc2 9123 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
d2394e6b 9124 val = tp->mac_mode;
1da177e4 9125 } else
d2394e6b
MC		 9126 val = 0;
9127
9128 tw32_f(MAC_MODE, val);
1da177e4
LT		 9129 udelay(40);
9130
77b483f1
MC		 9131 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9132
0a9140cf
MC		 9133 tg3_mdio_start(tp);
9134
63c3a66f 9135 if (tg3_flag(tp, PCI_EXPRESS) &&
4153577a
JP		 9136 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9137 tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9138 !tg3_flag(tp, 57765_PLUS)) {
ab0049b4 9139 val = tr32(0x7c00);
1da177e4
LT		 9140
9141 tw32(0x7c00, val | (1 << 25));
9142 }
9143
4153577a 9144 if (tg3_asic_rev(tp) == ASIC_REV_5720) {
d78b59f5
MC		 9145 val = tr32(TG3_CPMU_CLCK_ORIDE);
9146 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9147 }
9148
1da177e4 9149 /* Reprobe ASF enable state. */
63c3a66f 9150 tg3_flag_clear(tp, ENABLE_ASF);
942d1af0
NS		 9151 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9152 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9153
63c3a66f 9154 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
1da177e4
LT		 9155 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9156 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9157 u32 nic_cfg;
9158
9159 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9160 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f 9161 tg3_flag_set(tp, ENABLE_ASF);
4ba526ce 9162 tp->last_event_jiffies = jiffies;
63c3a66f
JP		 9163 if (tg3_flag(tp, 5750_PLUS))
9164 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
942d1af0
NS		 9165
9166 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9167 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9168 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9169 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9170 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
1da177e4
LT		 9171 }
9172 }
9173
9174 return 0;
9175}
9176
65ec698d
MC		 9177static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9178static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
92feeabf 9179
1da177e4 9180/* tp->lock is held. */
953c96e0 9181static int tg3_halt(struct tg3 *tp, int kind, bool silent)
1da177e4
LT		 9182{
9183 int err;
9184
9185 tg3_stop_fw(tp);
9186
944d980e 9187 tg3_write_sig_pre_reset(tp, kind);
1da177e4 9188
b3b7d6be 9189 tg3_abort_hw(tp, silent);
1da177e4
LT		 9190 err = tg3_chip_reset(tp);
9191
953c96e0 9192 __tg3_set_mac_addr(tp, false);
daba2a63 9193
944d980e
MC		 9194 tg3_write_sig_legacy(tp, kind);
9195 tg3_write_sig_post_reset(tp, kind);
1da177e4 9196
92feeabf
MC		 9197 if (tp->hw_stats) {
9198 /* Save the stats across chip resets... */
b4017c53 9199 tg3_get_nstats(tp, &tp->net_stats_prev);
92feeabf
MC		 9200 tg3_get_estats(tp, &tp->estats_prev);
9201
9202 /* And make sure the next sample is new data */
9203 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9204 }
9205
4bc814ab 9206 return err;
1da177e4
LT		 9207}
9208
1da177e4
LT		 9209static int tg3_set_mac_addr(struct net_device *dev, void *p)
9210{
9211 struct tg3 *tp = netdev_priv(dev);
9212 struct sockaddr *addr = p;
953c96e0
JP		 9213 int err = 0;
9214 bool skip_mac_1 = false;
1da177e4 9215
f9804ddb 9216 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 9217 return -EADDRNOTAVAIL;
f9804ddb 9218
1da177e4
LT		 9219 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9220
e75f7c90
MC		 9221 if (!netif_running(dev))
9222 return 0;
9223
63c3a66f 9224 if (tg3_flag(tp, ENABLE_ASF)) {
986e0aeb 9225 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 9226
986e0aeb
MC		 9227 addr0_high = tr32(MAC_ADDR_0_HIGH);
9228 addr0_low = tr32(MAC_ADDR_0_LOW);
9229 addr1_high = tr32(MAC_ADDR_1_HIGH);
9230 addr1_low = tr32(MAC_ADDR_1_LOW);
9231
9232 /* Skip MAC addr 1 if ASF is using it. */
9233 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9234 !(addr1_high == 0 && addr1_low == 0))
953c96e0 9235 skip_mac_1 = true;
58712ef9 9236 }
986e0aeb
MC		 9237 spin_lock_bh(&tp->lock);
9238 __tg3_set_mac_addr(tp, skip_mac_1);
9239 spin_unlock_bh(&tp->lock);
1da177e4 9240
b9ec6c1b 9241 return err;
1da177e4
LT		 9242}
9243
9244/* tp->lock is held. */
9245static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9246 dma_addr_t mapping, u32 maxlen_flags,
9247 u32 nic_addr)
9248{
9249 tg3_write_mem(tp,
9250 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9251 ((u64) mapping >> 32));
9252 tg3_write_mem(tp,
9253 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9254 ((u64) mapping & 0xffffffff));
9255 tg3_write_mem(tp,
9256 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9257 maxlen_flags);
9258
63c3a66f 9259 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 9260 tg3_write_mem(tp,
9261 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9262 nic_addr);
9263}
9264
a489b6d9
MC		 9265
9266static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 9267{
a489b6d9 9268 int i = 0;
b6080e12 9269
63c3a66f 9270 if (!tg3_flag(tp, ENABLE_TSS)) {
b6080e12
MC		 9271 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9272 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9273 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 9274 } else {
9275 tw32(HOSTCC_TXCOL_TICKS, 0);
9276 tw32(HOSTCC_TXMAX_FRAMES, 0);
9277 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
a489b6d9
MC		 9278
9279 for (; i < tp->txq_cnt; i++) {
9280 u32 reg;
9281
9282 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9283 tw32(reg, ec->tx_coalesce_usecs);
9284 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9285 tw32(reg, ec->tx_max_coalesced_frames);
9286 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9287 tw32(reg, ec->tx_max_coalesced_frames_irq);
9288 }
19cfaecc 9289 }
b6080e12 9290
a489b6d9
MC		 9291 for (; i < tp->irq_max - 1; i++) {
9292 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9293 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9294 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9295 }
9296}
9297
9298static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9299{
9300 int i = 0;
9301 u32 limit = tp->rxq_cnt;
9302
63c3a66f 9303 if (!tg3_flag(tp, ENABLE_RSS)) {
19cfaecc
MC		 9304 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9305 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9306 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
a489b6d9 9307 limit--;
19cfaecc 9308 } else {
b6080e12
MC		 9309 tw32(HOSTCC_RXCOL_TICKS, 0);
9310 tw32(HOSTCC_RXMAX_FRAMES, 0);
9311 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 9312 }
b6080e12 9313
a489b6d9 9314 for (; i < limit; i++) {
b6080e12
MC		 9315 u32 reg;
9316
9317 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9318 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 9319 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9320 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 9321 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9322 tw32(reg, ec->rx_max_coalesced_frames_irq);
b6080e12
MC		 9323 }
9324
9325 for (; i < tp->irq_max - 1; i++) {
9326 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 9327 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 9328 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
a489b6d9
MC		 9329 }
9330}
19cfaecc 9331
a489b6d9
MC		 9332static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9333{
9334 tg3_coal_tx_init(tp, ec);
9335 tg3_coal_rx_init(tp, ec);
9336
9337 if (!tg3_flag(tp, 5705_PLUS)) {
9338 u32 val = ec->stats_block_coalesce_usecs;
9339
9340 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9341 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9342
f4a46d1f 9343 if (!tp->link_up)
a489b6d9
MC		 9344 val = 0;
9345
9346 tw32(HOSTCC_STAT_COAL_TICKS, val);
b6080e12 9347 }
15f9850d 9348}
1da177e4 9349
328947ff
NS		 9350/* tp->lock is held. */
9351static void tg3_tx_rcbs_disable(struct tg3 *tp)
9352{
9353 u32 txrcb, limit;
9354
9355 /* Disable all transmit rings but the first. */
9356 if (!tg3_flag(tp, 5705_PLUS))
9357 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9358 else if (tg3_flag(tp, 5717_PLUS))
9359 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9360 else if (tg3_flag(tp, 57765_CLASS) ||
9361 tg3_asic_rev(tp) == ASIC_REV_5762)
9362 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9363 else
9364 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9365
9366 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9367 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9368 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9369 BDINFO_FLAGS_DISABLED);
9370}
9371
32ba19ef
NS		 9372/* tp->lock is held. */
9373static void tg3_tx_rcbs_init(struct tg3 *tp)
9374{
9375 int i = 0;
9376 u32 txrcb = NIC_SRAM_SEND_RCB;
9377
9378 if (tg3_flag(tp, ENABLE_TSS))
9379 i++;
9380
9381 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9382 struct tg3_napi *tnapi = &tp->napi[i];
9383
9384 if (!tnapi->tx_ring)
9385 continue;
9386
9387 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9388 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9389 NIC_SRAM_TX_BUFFER_DESC);
9390 }
9391}
9392
328947ff
NS		 9393/* tp->lock is held. */
9394static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9395{
9396 u32 rxrcb, limit;
9397
9398 /* Disable all receive return rings but the first. */
9399 if (tg3_flag(tp, 5717_PLUS))
9400 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9401 else if (!tg3_flag(tp, 5705_PLUS))
9402 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9403 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9404 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9405 tg3_flag(tp, 57765_CLASS))
9406 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9407 else
9408 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9409
9410 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9411 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9412 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9413 BDINFO_FLAGS_DISABLED);
9414}
9415
32ba19ef
NS		 9416/* tp->lock is held. */
9417static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9418{
9419 int i = 0;
9420 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9421
9422 if (tg3_flag(tp, ENABLE_RSS))
9423 i++;
9424
9425 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9426 struct tg3_napi *tnapi = &tp->napi[i];
9427
9428 if (!tnapi->rx_rcb)
9429 continue;
9430
9431 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9432 (tp->rx_ret_ring_mask + 1) <<
9433 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9434 }
9435}
9436
2d31ecaf
MC		 9437/* tp->lock is held. */
9438static void tg3_rings_reset(struct tg3 *tp)
9439{
9440 int i;
328947ff 9441 u32 stblk;
2d31ecaf
MC		 9442 struct tg3_napi *tnapi = &tp->napi[0];
9443
328947ff 9444 tg3_tx_rcbs_disable(tp);
2d31ecaf 9445
328947ff 9446 tg3_rx_ret_rcbs_disable(tp);
2d31ecaf
MC		 9447
9448 /* Disable interrupts */
9449 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
0e6cf6a9
MC		 9450 tp->napi[0].chk_msi_cnt = 0;
9451 tp->napi[0].last_rx_cons = 0;
9452 tp->napi[0].last_tx_cons = 0;
2d31ecaf
MC		 9453
9454 /* Zero mailbox registers. */
63c3a66f 9455 if (tg3_flag(tp, SUPPORT_MSIX)) {
6fd45cb8 9456 for (i = 1; i < tp->irq_max; i++) {
f77a6a8e
MC		 9457 tp->napi[i].tx_prod = 0;
9458 tp->napi[i].tx_cons = 0;
63c3a66f 9459 if (tg3_flag(tp, ENABLE_TSS))
c2353a32 9460 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 9461 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9462 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7f230735 9463 tp->napi[i].chk_msi_cnt = 0;
0e6cf6a9
MC		 9464 tp->napi[i].last_rx_cons = 0;
9465 tp->napi[i].last_tx_cons = 0;
f77a6a8e 9466 }
63c3a66f 9467 if (!tg3_flag(tp, ENABLE_TSS))
c2353a32 9468 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 9469 } else {
9470 tp->napi[0].tx_prod = 0;
9471 tp->napi[0].tx_cons = 0;
9472 tw32_mailbox(tp->napi[0].prodmbox, 0);
9473 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9474 }
2d31ecaf
MC		 9475
9476 /* Make sure the NIC-based send BD rings are disabled. */
63c3a66f 9477 if (!tg3_flag(tp, 5705_PLUS)) {
2d31ecaf
MC		 9478 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9479 for (i = 0; i < 16; i++)
9480 tw32_tx_mbox(mbox + i * 8, 0);
9481 }
9482
2d31ecaf
MC		 9483 /* Clear status block in ram. */
9484 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9485
9486 /* Set status block DMA address */
9487 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9488 ((u64) tnapi->status_mapping >> 32));
9489 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9490 ((u64) tnapi->status_mapping & 0xffffffff));
9491
f77a6a8e 9492 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 9493
f77a6a8e
MC		 9494 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9495 u64 mapping = (u64)tnapi->status_mapping;
9496 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9497 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
32ba19ef 9498 stblk += 8;
f77a6a8e
MC		 9499
9500 /* Clear status block in ram. */
9501 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
f77a6a8e 9502 }
32ba19ef
NS		 9503
9504 tg3_tx_rcbs_init(tp);
9505 tg3_rx_ret_rcbs_init(tp);
2d31ecaf
MC		 9506}
9507
eb07a940
MC		 9508static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9509{
9510 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9511
63c3a66f
JP		 9512 if (!tg3_flag(tp, 5750_PLUS) ||
9513 tg3_flag(tp, 5780_CLASS) ||
4153577a
JP		 9514 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9515 tg3_asic_rev(tp) == ASIC_REV_5752 ||
513aa6ea 9516 tg3_flag(tp, 57765_PLUS))
eb07a940 9517 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
4153577a
JP		 9518 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9519 tg3_asic_rev(tp) == ASIC_REV_5787)
eb07a940
MC		 9520 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9521 else
9522 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9523
9524 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9525 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9526
9527 val = min(nic_rep_thresh, host_rep_thresh);
9528 tw32(RCVBDI_STD_THRESH, val);
9529
63c3a66f 9530 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9531 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9532
63c3a66f 9533 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
eb07a940
MC		 9534 return;
9535
513aa6ea 9536 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
eb07a940
MC		 9537
9538 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9539
9540 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9541 tw32(RCVBDI_JUMBO_THRESH, val);
9542
63c3a66f 9543 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9544 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9545}
9546
ccd5ba9d
MC		 9547static inline u32 calc_crc(unsigned char *buf, int len)
9548{
9549 u32 reg;
9550 u32 tmp;
9551 int j, k;
9552
9553 reg = 0xffffffff;
9554
9555 for (j = 0; j < len; j++) {
9556 reg ^= buf[j];
9557
9558 for (k = 0; k < 8; k++) {
9559 tmp = reg & 0x01;
9560
9561 reg >>= 1;
9562
9563 if (tmp)
9564 reg ^= 0xedb88320;
9565 }
9566 }
9567
9568 return ~reg;
9569}
9570
9571static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9572{
9573 /* accept or reject all multicast frames */
9574 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9575 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9576 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9577 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9578}
9579
9580static void __tg3_set_rx_mode(struct net_device *dev)
9581{
9582 struct tg3 *tp = netdev_priv(dev);
9583 u32 rx_mode;
9584
9585 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9586 RX_MODE_KEEP_VLAN_TAG);
9587
9588#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9589 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9590 * flag clear.
9591 */
9592 if (!tg3_flag(tp, ENABLE_ASF))
9593 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9594#endif
9595
9596 if (dev->flags & IFF_PROMISC) {
9597 /* Promiscuous mode. */
9598 rx_mode |= RX_MODE_PROMISC;
9599 } else if (dev->flags & IFF_ALLMULTI) {
9600 /* Accept all multicast. */
9601 tg3_set_multi(tp, 1);
9602 } else if (netdev_mc_empty(dev)) {
9603 /* Reject all multicast. */
9604 tg3_set_multi(tp, 0);
9605 } else {
9606 /* Accept one or more multicast(s). */
9607 struct netdev_hw_addr *ha;
9608 u32 mc_filter[4] = { 0, };
9609 u32 regidx;
9610 u32 bit;
9611 u32 crc;
9612
9613 netdev_for_each_mc_addr(ha, dev) {
9614 crc = calc_crc(ha->addr, ETH_ALEN);
9615 bit = ~crc & 0x7f;
9616 regidx = (bit & 0x60) >> 5;
9617 bit &= 0x1f;
9618 mc_filter[regidx] |= (1 << bit);
9619 }
9620
9621 tw32(MAC_HASH_REG_0, mc_filter[0]);
9622 tw32(MAC_HASH_REG_1, mc_filter[1]);
9623 tw32(MAC_HASH_REG_2, mc_filter[2]);
9624 tw32(MAC_HASH_REG_3, mc_filter[3]);
9625 }
9626
9627 if (rx_mode != tp->rx_mode) {
9628 tp->rx_mode = rx_mode;
9629 tw32_f(MAC_RX_MODE, rx_mode);
9630 udelay(10);
9631 }
9632}
9633
9102426a 9634static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
90415477
MC		 9635{
9636 int i;
9637
9638 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9102426a 9639 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
90415477
MC		 9640}
9641
9642static void tg3_rss_check_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9643{
9644 int i;
9645
9646 if (!tg3_flag(tp, SUPPORT_MSIX))
9647 return;
9648
0b3ba055 9649 if (tp->rxq_cnt == 1) {
bcebcc46 9650 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
90415477
MC		 9651 return;
9652 }
9653
9654 /* Validate table against current IRQ count */
9655 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
0b3ba055 9656 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
90415477
MC		 9657 break;
9658 }
9659
9660 if (i != TG3_RSS_INDIR_TBL_SIZE)
9102426a 9661 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
bcebcc46
MC		 9662}
9663
90415477 9664static void tg3_rss_write_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9665{
9666 int i = 0;
9667 u32 reg = MAC_RSS_INDIR_TBL_0;
9668
9669 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9670 u32 val = tp->rss_ind_tbl[i];
9671 i++;
9672 for (; i % 8; i++) {
9673 val <<= 4;
9674 val |= tp->rss_ind_tbl[i];
9675 }
9676 tw32(reg, val);
9677 reg += 4;
9678 }
9679}
9680
9bc297ea
NS		 9681static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9682{
9683 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9684 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9685 else
9686 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9687}
9688
1da177e4 9689/* tp->lock is held. */
953c96e0 9690static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
1da177e4
LT		 9691{
9692 u32 val, rdmac_mode;
9693 int i, err, limit;
8fea32b9 9694 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
1da177e4
LT		 9695
9696 tg3_disable_ints(tp);
9697
9698 tg3_stop_fw(tp);
9699
9700 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9701
63c3a66f 9702 if (tg3_flag(tp, INIT_COMPLETE))
e6de8ad1 9703 tg3_abort_hw(tp, 1);
1da177e4 9704
fdad8de4
NS		 9705 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9706 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9707 tg3_phy_pull_config(tp);
400dfbaa 9708 tg3_eee_pull_config(tp, NULL);
fdad8de4
NS		 9709 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9710 }
9711
400dfbaa
NS		 9712 /* Enable MAC control of LPI */
9713 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9714 tg3_setup_eee(tp);
9715
603f1173 9716 if (reset_phy)
d4d2c558
MC		 9717 tg3_phy_reset(tp);
9718
1da177e4
LT		 9719 err = tg3_chip_reset(tp);
9720 if (err)
9721 return err;
9722
9723 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9724
4153577a 9725 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
d30cdd28
MC		 9726 val = tr32(TG3_CPMU_CTRL);
9727 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9728 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 9729
9730 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9731 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9732 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9733 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9734
9735 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9736 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9737 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9738 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9739
9740 val = tr32(TG3_CPMU_HST_ACC);
9741 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9742 val |= CPMU_HST_ACC_MACCLK_6_25;
9743 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 9744 }
9745
4153577a 9746 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
33466d93
MC		 9747 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9748 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9749 PCIE_PWR_MGMT_L1_THRESH_4MS;
9750 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 9751
9752 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9753 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9754
9755 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 9756
f40386c8
MC		 9757 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9758 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 9759 }
9760
63c3a66f 9761 if (tg3_flag(tp, L1PLLPD_EN)) {
614b0590
MC		 9762 u32 grc_mode = tr32(GRC_MODE);
9763
9764 /* Access the lower 1K of PL PCIE block registers. */
9765 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9766 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9767
9768 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9769 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9770 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9771
9772 tw32(GRC_MODE, grc_mode);
9773 }
9774
55086ad9 9775 if (tg3_flag(tp, 57765_CLASS)) {
4153577a 9776 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
5093eedc 9777 u32 grc_mode = tr32(GRC_MODE);
cea46462 9778
5093eedc
MC		 9779 /* Access the lower 1K of PL PCIE block registers. */
9780 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9781 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
cea46462 9782
5093eedc
MC		 9783 val = tr32(TG3_PCIE_TLDLPL_PORT +
9784 TG3_PCIE_PL_LO_PHYCTL5);
9785 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9786 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
cea46462 9787
5093eedc
MC		 9788 tw32(GRC_MODE, grc_mode);
9789 }
a977dbe8 9790
4153577a 9791 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
d3f677af
MC		 9792 u32 grc_mode;
9793
9794 /* Fix transmit hangs */
9795 val = tr32(TG3_CPMU_PADRNG_CTL);
9796 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9797 tw32(TG3_CPMU_PADRNG_CTL, val);
9798
9799 grc_mode = tr32(GRC_MODE);
1ff30a59
MC		 9800
9801 /* Access the lower 1K of DL PCIE block registers. */
9802 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9803 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9804
9805 val = tr32(TG3_PCIE_TLDLPL_PORT +
9806 TG3_PCIE_DL_LO_FTSMAX);
9807 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9808 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9809 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9810
9811 tw32(GRC_MODE, grc_mode);
9812 }
9813
a977dbe8
MC		 9814 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9815 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9816 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9817 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
cea46462
MC		 9818 }
9819
1da177e4
LT		 9820 /* This works around an issue with Athlon chipsets on
9821 * B3 tigon3 silicon. This bit has no effect on any
9822 * other revision. But do not set this on PCI Express
795d01c5 9823 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 9824 */
63c3a66f
JP		 9825 if (!tg3_flag(tp, CPMU_PRESENT)) {
9826 if (!tg3_flag(tp, PCI_EXPRESS))
795d01c5
MC		 9827 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9828 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9829 }
1da177e4 9830
4153577a 9831 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 9832 tg3_flag(tp, PCIX_MODE)) {
1da177e4
LT		 9833 val = tr32(TG3PCI_PCISTATE);
9834 val |= PCISTATE_RETRY_SAME_DMA;
9835 tw32(TG3PCI_PCISTATE, val);
9836 }
9837
63c3a66f 9838 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 9839 /* Allow reads and writes to the
9840 * APE register and memory space.
9841 */
9842 val = tr32(TG3PCI_PCISTATE);
9843 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 9844 PCISTATE_ALLOW_APE_SHMEM_WR |
9845 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 9846 tw32(TG3PCI_PCISTATE, val);
9847 }
9848
4153577a 9849 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
1da177e4
LT		 9850 /* Enable some hw fixes. */
9851 val = tr32(TG3PCI_MSI_DATA);
9852 val |= (1 << 26) | (1 << 28) | (1 << 29);
9853 tw32(TG3PCI_MSI_DATA, val);
9854 }
9855
9856 /* Descriptor ring init may make accesses to the
9857 * NIC SRAM area to setup the TX descriptors, so we
9858 * can only do this after the hardware has been
9859 * successfully reset.
9860 */
32d8c572
MC		 9861 err = tg3_init_rings(tp);
9862 if (err)
9863 return err;
1da177e4 9864
63c3a66f 9865 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 9866 val = tr32(TG3PCI_DMA_RW_CTRL) &
9867 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
4153577a 9868 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
1a319025 9869 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
55086ad9 9870 if (!tg3_flag(tp, 57765_CLASS) &&
4153577a
JP		 9871 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9872 tg3_asic_rev(tp) != ASIC_REV_5762)
0aebff48 9873 val |= DMA_RWCTRL_TAGGED_STAT_WA;
cbf9ca6c 9874 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
4153577a
JP		 9875 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9876 tg3_asic_rev(tp) != ASIC_REV_5761) {
d30cdd28
MC		 9877 /* This value is determined during the probe time DMA
9878 * engine test, tg3_test_dma.
9879 */
9880 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9881 }
1da177e4
LT		 9882
9883 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
9884 GRC_MODE_4X_NIC_SEND_RINGS |
9885 GRC_MODE_NO_TX_PHDR_CSUM |
9886 GRC_MODE_NO_RX_PHDR_CSUM);
9887 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 9888
9889 /* Pseudo-header checksum is done by hardware logic and not
9890 * the offload processers, so make the chip do the pseudo-
9891 * header checksums on receive. For transmit it is more
9892 * convenient to do the pseudo-header checksum in software
9893 * as Linux does that on transmit for us in all cases.
9894 */
9895 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4 9896
fb4ce8ad
MC		 9897 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
9898 if (tp->rxptpctl)
9899 tw32(TG3_RX_PTP_CTL,
9900 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
9901
9902 if (tg3_flag(tp, PTP_CAPABLE))
9903 val |= GRC_MODE_TIME_SYNC_ENABLE;
9904
9905 tw32(GRC_MODE, tp->grc_mode | val);
1da177e4
LT		 9906
9907 /* Setup the timer prescalar register. Clock is always 66Mhz. */
9908 val = tr32(GRC_MISC_CFG);
9909 val &= ~0xff;
9910 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
9911 tw32(GRC_MISC_CFG, val);
9912
9913 /* Initialize MBUF/DESC pool. */
63c3a66f 9914 if (tg3_flag(tp, 5750_PLUS)) {
1da177e4 9915 /* Do nothing. */
4153577a 9916 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
1da177e4 9917 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
4153577a 9918 if (tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 9919 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
9920 else
9921 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
9922 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
9923 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
63c3a66f 9924 } else if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 9925 int fw_len;
9926
077f849d 9927 fw_len = tp->fw_len;
1da177e4
LT		 9928 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
9929 tw32(BUFMGR_MB_POOL_ADDR,
9930 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
9931 tw32(BUFMGR_MB_POOL_SIZE,
9932 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
9933 }
1da177e4 9934
0f893dc6 9935 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 9936 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9937 tp->bufmgr_config.mbuf_read_dma_low_water);
9938 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9939 tp->bufmgr_config.mbuf_mac_rx_low_water);
9940 tw32(BUFMGR_MB_HIGH_WATER,
9941 tp->bufmgr_config.mbuf_high_water);
9942 } else {
9943 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9944 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
9945 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9946 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
9947 tw32(BUFMGR_MB_HIGH_WATER,
9948 tp->bufmgr_config.mbuf_high_water_jumbo);
9949 }
9950 tw32(BUFMGR_DMA_LOW_WATER,
9951 tp->bufmgr_config.dma_low_water);
9952 tw32(BUFMGR_DMA_HIGH_WATER,
9953 tp->bufmgr_config.dma_high_water);
9954
d309a46e 9955 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
4153577a 9956 if (tg3_asic_rev(tp) == ASIC_REV_5719)
d309a46e 9957 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
4153577a
JP		 9958 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
9959 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
9960 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
4d958473 9961 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
d309a46e 9962 tw32(BUFMGR_MODE, val);
1da177e4
LT		 9963 for (i = 0; i < 2000; i++) {
9964 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
9965 break;
9966 udelay(10);
9967 }
9968 if (i >= 2000) {
05dbe005 9969 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 9970 return -ENODEV;
9971 }
9972
4153577a 9973 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
eb07a940 9974 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
b5d3772c 9975
eb07a940 9976 tg3_setup_rxbd_thresholds(tp);
1da177e4
LT		 9977
9978 /* Initialize TG3_BDINFO's at:
9979 * RCVDBDI_STD_BD: standard eth size rx ring
9980 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
9981 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
9982 *
9983 * like so:
9984 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
9985 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
9986 * ring attribute flags
9987 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
9988 *
9989 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
9990 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
9991 *
9992 * The size of each ring is fixed in the firmware, but the location is
9993 * configurable.
9994 */
9995 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 9996 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 9997 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 9998 ((u64) tpr->rx_std_mapping & 0xffffffff));
63c3a66f 9999 if (!tg3_flag(tp, 5717_PLUS))
87668d35
MC		 10000 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10001 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 10002
fdb72b38 10003 /* Disable the mini ring */
63c3a66f 10004 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10005 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10006 BDINFO_FLAGS_DISABLED);
10007
fdb72b38
MC		 10008 /* Program the jumbo buffer descriptor ring control
10009 * blocks on those devices that have them.
10010 */
4153577a 10011 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
63c3a66f 10012 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
1da177e4 10013
63c3a66f 10014 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
1da177e4 10015 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10016 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 10017 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10018 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
de9f5230
MC		 10019 val = TG3_RX_JMB_RING_SIZE(tp) <<
10020 BDINFO_FLAGS_MAXLEN_SHIFT;
1da177e4 10021 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
de9f5230 10022 val | BDINFO_FLAGS_USE_EXT_RECV);
63c3a66f 10023 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
c65a17f4 10024 tg3_flag(tp, 57765_CLASS) ||
4153577a 10025 tg3_asic_rev(tp) == ASIC_REV_5762)
87668d35
MC		 10026 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10027 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 10028 } else {
10029 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10030 BDINFO_FLAGS_DISABLED);
10031 }
10032
63c3a66f 10033 if (tg3_flag(tp, 57765_PLUS)) {
fa6b2aae 10034 val = TG3_RX_STD_RING_SIZE(tp);
7cb32cf2
MC		 10035 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10036 val |= (TG3_RX_STD_DMA_SZ << 2);
10037 } else
04380d40 10038 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38 10039 } else
de9f5230 10040 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 10041
10042 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 10043
411da640 10044 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 10045 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 10046
63c3a66f
JP		 10047 tpr->rx_jmb_prod_idx =
10048 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
66711e66 10049 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 10050
2d31ecaf
MC		 10051 tg3_rings_reset(tp);
10052
1da177e4 10053 /* Initialize MAC address and backoff seed. */
953c96e0 10054 __tg3_set_mac_addr(tp, false);
1da177e4
LT		 10055
10056 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 10057 tw32(MAC_RX_MTU_SIZE,
10058 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 10059
10060 /* The slot time is changed by tg3_setup_phy if we
10061 * run at gigabit with half duplex.
10062 */
f2096f94
MC		 10063 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10064 (6 << TX_LENGTHS_IPG_SHIFT) |
10065 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10066
4153577a
JP		 10067 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10068 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10069 val |= tr32(MAC_TX_LENGTHS) &
10070 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10071 TX_LENGTHS_CNT_DWN_VAL_MSK);
10072
10073 tw32(MAC_TX_LENGTHS, val);
1da177e4
LT		 10074
10075 /* Receive rules. */
10076 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10077 tw32(RCVLPC_CONFIG, 0x0181);
10078
10079 /* Calculate RDMAC_MODE setting early, we need it to determine
10080 * the RCVLPC_STATE_ENABLE mask.
10081 */
10082 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10083 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10084 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10085 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10086 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 10087
4153577a 10088 if (tg3_asic_rev(tp) == ASIC_REV_5717)
0339e4e3
MC		 10089 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10090
4153577a
JP		 10091 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10092 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10093 tg3_asic_rev(tp) == ASIC_REV_57780)
d30cdd28
MC		 10094 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10095 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10096 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10097
4153577a
JP		 10098 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10099 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10100 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a 10101 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 10102 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10103 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10104 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10105 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10106 }
10107 }
10108
63c3a66f 10109 if (tg3_flag(tp, PCI_EXPRESS))
85e94ced
MC		 10110 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10111
4153577a 10112 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
d3f677af
MC		 10113 tp->dma_limit = 0;
10114 if (tp->dev->mtu <= ETH_DATA_LEN) {
10115 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10116 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10117 }
10118 }
10119
63c3a66f
JP		 10120 if (tg3_flag(tp, HW_TSO_1) ||
10121 tg3_flag(tp, HW_TSO_2) ||
10122 tg3_flag(tp, HW_TSO_3))
027455ad
MC		 10123 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10124
108a6c16 10125 if (tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 10126 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10127 tg3_asic_rev(tp) == ASIC_REV_57780)
027455ad 10128 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4 10129
4153577a
JP		 10130 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10131 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10132 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10133
4153577a
JP		 10134 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10135 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10136 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10137 tg3_asic_rev(tp) == ASIC_REV_57780 ||
63c3a66f 10138 tg3_flag(tp, 57765_PLUS)) {
c65a17f4
MC		 10139 u32 tgtreg;
10140
4153577a 10141 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10142 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10143 else
10144 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10145
10146 val = tr32(tgtreg);
4153577a
JP		 10147 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10148 tg3_asic_rev(tp) == ASIC_REV_5762) {
b4495ed8
MC		 10149 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10150 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10151 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10152 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10153 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10154 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
b75cc0e4 10155 }
c65a17f4 10156 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
41a8a7ee
MC		 10157 }
10158
4153577a
JP		 10159 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10160 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10161 tg3_asic_rev(tp) == ASIC_REV_5762) {
c65a17f4
MC		 10162 u32 tgtreg;
10163
4153577a 10164 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10165 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10166 else
10167 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10168
10169 val = tr32(tgtreg);
10170 tw32(tgtreg, val |
d309a46e
MC		 10171 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10172 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10173 }
10174
1da177e4 10175 /* Receive/send statistics. */
63c3a66f 10176 if (tg3_flag(tp, 5750_PLUS)) {
1661394e
MC		 10177 val = tr32(RCVLPC_STATS_ENABLE);
10178 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10179 tw32(RCVLPC_STATS_ENABLE, val);
10180 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
63c3a66f 10181 tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10182 val = tr32(RCVLPC_STATS_ENABLE);
10183 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10184 tw32(RCVLPC_STATS_ENABLE, val);
10185 } else {
10186 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10187 }
10188 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10189 tw32(SNDDATAI_STATSENAB, 0xffffff);
10190 tw32(SNDDATAI_STATSCTRL,
10191 (SNDDATAI_SCTRL_ENABLE |
10192 SNDDATAI_SCTRL_FASTUPD));
10193
10194 /* Setup host coalescing engine. */
10195 tw32(HOSTCC_MODE, 0);
10196 for (i = 0; i < 2000; i++) {
10197 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10198 break;
10199 udelay(10);
10200 }
10201
d244c892 10202 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 10203
63c3a66f 10204 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10205 /* Status/statistics block address. See tg3_timer,
10206 * the tg3_periodic_fetch_stats call there, and
10207 * tg3_get_stats to see how this works for 5705/5750 chips.
10208 */
1da177e4
LT		 10209 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10210 ((u64) tp->stats_mapping >> 32));
10211 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10212 ((u64) tp->stats_mapping & 0xffffffff));
10213 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 10214
1da177e4 10215 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 10216
10217 /* Clear statistics and status block memory areas */
10218 for (i = NIC_SRAM_STATS_BLK;
10219 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10220 i += sizeof(u32)) {
10221 tg3_write_mem(tp, i, 0);
10222 udelay(40);
10223 }
1da177e4
LT		 10224 }
10225
10226 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10227
10228 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10229 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
63c3a66f 10230 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10231 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10232
f07e9af3
MC		 10233 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10234 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c94e3941
MC		 10235 /* reset to prevent losing 1st rx packet intermittently */
10236 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10237 udelay(10);
10238 }
10239
3bda1258 10240 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9e975cc2
MC		 10241 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10242 MAC_MODE_FHDE_ENABLE;
10243 if (tg3_flag(tp, ENABLE_APE))
10244 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
63c3a66f 10245 if (!tg3_flag(tp, 5705_PLUS) &&
f07e9af3 10246 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a 10247 tg3_asic_rev(tp) != ASIC_REV_5700)
e8f3f6ca 10248 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 10249 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10250 udelay(40);
10251
314fba34 10252 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
63c3a66f 10253 * If TG3_FLAG_IS_NIC is zero, we should read the
314fba34
MC		 10254 * register to preserve the GPIO settings for LOMs. The GPIOs,
10255 * whether used as inputs or outputs, are set by boot code after
10256 * reset.
10257 */
63c3a66f 10258 if (!tg3_flag(tp, IS_NIC)) {
314fba34
MC		 10259 u32 gpio_mask;
10260
9d26e213
MC		 10261 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10262 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10263 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc 10264
4153577a 10265 if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc
MC		 10266 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10267 GRC_LCLCTRL_GPIO_OUTPUT3;
10268
4153577a 10269 if (tg3_asic_rev(tp) == ASIC_REV_5755)
af36e6b6
MC		 10270 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10271
aaf84465 10272 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 10273 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10274
10275 /* GPIO1 must be driven high for eeprom write protect */
63c3a66f 10276 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9d26e213
MC		 10277 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10278 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 10279 }
1da177e4
LT		 10280 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10281 udelay(100);
10282
c3b5003b 10283 if (tg3_flag(tp, USING_MSIX)) {
baf8a94a 10284 val = tr32(MSGINT_MODE);
c3b5003b
MC		 10285 val |= MSGINT_MODE_ENABLE;
10286 if (tp->irq_cnt > 1)
10287 val |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 10288 if (!tg3_flag(tp, 1SHOT_MSI))
10289 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
baf8a94a
MC		 10290 tw32(MSGINT_MODE, val);
10291 }
10292
63c3a66f 10293 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10294 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10295 udelay(40);
10296 }
10297
10298 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10299 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10300 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10301 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10302 WDMAC_MODE_LNGREAD_ENAB);
10303
4153577a
JP		 10304 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10305 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10306 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a
JP		 10307 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10308 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
1da177e4
LT		 10309 /* nothing */
10310 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10311 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10312 val |= WDMAC_MODE_RX_ACCEL;
10313 }
10314 }
10315
d9ab5ad1 10316 /* Enable host coalescing bug fix */
63c3a66f 10317 if (tg3_flag(tp, 5755_PLUS))
f51f3562 10318 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 10319
4153577a 10320 if (tg3_asic_rev(tp) == ASIC_REV_5785)
788a035e
MC		 10321 val |= WDMAC_MODE_BURST_ALL_DATA;
10322
1da177e4
LT		 10323 tw32_f(WDMAC_MODE, val);
10324 udelay(40);
10325
63c3a66f 10326 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 10327 u16 pcix_cmd;
10328
10329 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10330 &pcix_cmd);
4153577a 10331 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
9974a356
MC		 10332 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10333 pcix_cmd |= PCI_X_CMD_READ_2K;
4153577a 10334 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
9974a356
MC		 10335 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10336 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 10337 }
9974a356
MC		 10338 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10339 pcix_cmd);
1da177e4
LT		 10340 }
10341
10342 tw32_f(RDMAC_MODE, rdmac_mode);
10343 udelay(40);
10344
9bc297ea
NS		 10345 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10346 tg3_asic_rev(tp) == ASIC_REV_5720) {
091f0ea3
MC		 10347 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10348 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10349 break;
10350 }
10351 if (i < TG3_NUM_RDMA_CHANNELS) {
10352 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10353 val |= tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10354 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10355 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
091f0ea3
MC		 10356 }
10357 }
10358
1da177e4 10359 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
63c3a66f 10360 if (!tg3_flag(tp, 5705_PLUS))
1da177e4 10361 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6 10362
4153577a 10363 if (tg3_asic_rev(tp) == ASIC_REV_5761)
9936bcf6
MC		 10364 tw32(SNDDATAC_MODE,
10365 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10366 else
10367 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10368
1da177e4
LT		 10369 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10370 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7cb32cf2 10371 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
63c3a66f 10372 if (tg3_flag(tp, LRG_PROD_RING_CAP))
7cb32cf2
MC		 10373 val |= RCVDBDI_MODE_LRG_RING_SZ;
10374 tw32(RCVDBDI_MODE, val);
1da177e4 10375 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
63c3a66f
JP		 10376 if (tg3_flag(tp, HW_TSO_1) ||
10377 tg3_flag(tp, HW_TSO_2) ||
10378 tg3_flag(tp, HW_TSO_3))
1da177e4 10379 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 10380 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
63c3a66f 10381 if (tg3_flag(tp, ENABLE_TSS))
baf8a94a
MC		 10382 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10383 tw32(SNDBDI_MODE, val);
1da177e4
LT		 10384 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10385
4153577a 10386 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
1da177e4
LT		 10387 err = tg3_load_5701_a0_firmware_fix(tp);
10388 if (err)
10389 return err;
10390 }
10391
c4dab506
NS		 10392 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10393 /* Ignore any errors for the firmware download. If download
10394 * fails, the device will operate with EEE disabled
10395 */
10396 tg3_load_57766_firmware(tp);
10397 }
10398
63c3a66f 10399 if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10400 err = tg3_load_tso_firmware(tp);
10401 if (err)
10402 return err;
10403 }
1da177e4
LT		 10404
10405 tp->tx_mode = TX_MODE_ENABLE;
f2096f94 10406
63c3a66f 10407 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 10408 tg3_asic_rev(tp) == ASIC_REV_5906)
b1d05210 10409 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
f2096f94 10410
4153577a
JP		 10411 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10412 tg3_asic_rev(tp) == ASIC_REV_5762) {
f2096f94
MC		 10413 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10414 tp->tx_mode &= ~val;
10415 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10416 }
10417
1da177e4
LT		 10418 tw32_f(MAC_TX_MODE, tp->tx_mode);
10419 udelay(100);
10420
63c3a66f 10421 if (tg3_flag(tp, ENABLE_RSS)) {
bcebcc46 10422 tg3_rss_write_indir_tbl(tp);
baf8a94a
MC		 10423
10424 /* Setup the "secret" hash key. */
10425 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10426 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10427 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10428 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10429 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10430 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10431 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10432 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10433 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10434 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10435 }
10436
1da177e4 10437 tp->rx_mode = RX_MODE_ENABLE;
63c3a66f 10438 if (tg3_flag(tp, 5755_PLUS))
af36e6b6
MC		 10439 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10440
378b72c8
NS		 10441 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10442 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10443
63c3a66f 10444 if (tg3_flag(tp, ENABLE_RSS))
baf8a94a
MC		 10445 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10446 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10447 RX_MODE_RSS_IPV6_HASH_EN |
10448 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10449 RX_MODE_RSS_IPV4_HASH_EN |
10450 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10451
1da177e4
LT		 10452 tw32_f(MAC_RX_MODE, tp->rx_mode);
10453 udelay(10);
10454
1da177e4
LT		 10455 tw32(MAC_LED_CTRL, tp->led_ctrl);
10456
10457 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
f07e9af3 10458 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
1da177e4
LT		 10459 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10460 udelay(10);
10461 }
10462 tw32_f(MAC_RX_MODE, tp->rx_mode);
10463 udelay(10);
10464
f07e9af3 10465 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a
JP		 10466 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10467 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
1da177e4
LT		 10468 /* Set drive transmission level to 1.2V */
10469 /* only if the signal pre-emphasis bit is not set */
10470 val = tr32(MAC_SERDES_CFG);
10471 val &= 0xfffff000;
10472 val |= 0x880;
10473 tw32(MAC_SERDES_CFG, val);
10474 }
4153577a 10475 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
1da177e4
LT		 10476 tw32(MAC_SERDES_CFG, 0x616000);
10477 }
10478
10479 /* Prevent chip from dropping frames when flow control
10480 * is enabled.
10481 */
55086ad9 10482 if (tg3_flag(tp, 57765_CLASS))
666bc831
MC		 10483 val = 1;
10484 else
10485 val = 2;
10486 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4 10487
4153577a 10488 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
f07e9af3 10489 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
1da177e4 10490 /* Use hardware link auto-negotiation */
63c3a66f 10491 tg3_flag_set(tp, HW_AUTONEG);
1da177e4
LT		 10492 }
10493
f07e9af3 10494 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
4153577a 10495 tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 10496 u32 tmp;
10497
10498 tmp = tr32(SERDES_RX_CTRL);
10499 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10500 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10501 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10502 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10503 }
10504
63c3a66f 10505 if (!tg3_flag(tp, USE_PHYLIB)) {
c6700ce2 10506 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
80096068 10507 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1da177e4 10508
953c96e0 10509 err = tg3_setup_phy(tp, false);
dd477003
MC		 10510 if (err)
10511 return err;
1da177e4 10512
f07e9af3
MC		 10513 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10514 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
dd477003
MC		 10515 u32 tmp;
10516
10517 /* Clear CRC stats. */
10518 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10519 tg3_writephy(tp, MII_TG3_TEST1,
10520 tmp | MII_TG3_TEST1_CRC_EN);
f08aa1a8 10521 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
dd477003 10522 }
1da177e4
LT		 10523 }
10524 }
10525
10526 __tg3_set_rx_mode(tp->dev);
10527
10528 /* Initialize receive rules. */
10529 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10530 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10531 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10532 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10533
63c3a66f 10534 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
1da177e4
LT		 10535 limit = 8;
10536 else
10537 limit = 16;
63c3a66f 10538 if (tg3_flag(tp, ENABLE_ASF))
1da177e4
LT		 10539 limit -= 4;
10540 switch (limit) {
10541 case 16:
10542 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10543 case 15:
10544 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10545 case 14:
10546 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10547 case 13:
10548 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10549 case 12:
10550 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10551 case 11:
10552 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10553 case 10:
10554 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10555 case 9:
10556 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10557 case 8:
10558 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10559 case 7:
10560 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10561 case 6:
10562 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10563 case 5:
10564 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10565 case 4:
10566 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10567 case 3:
10568 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10569 case 2:
10570 case 1:
10571
10572 default:
10573 break;
855e1111 10574 }
1da177e4 10575
63c3a66f 10576 if (tg3_flag(tp, ENABLE_APE))
9ce768ea
MC		 10577 /* Write our heartbeat update interval to APE. */
10578 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10579 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 10580
1da177e4
LT		 10581 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10582
1da177e4
LT		 10583 return 0;
10584}
10585
10586/* Called at device open time to get the chip ready for
10587 * packet processing. Invoked with tp->lock held.
10588 */
953c96e0 10589static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
1da177e4 10590{
df465abf
NS		 10591 /* Chip may have been just powered on. If so, the boot code may still
10592 * be running initialization. Wait for it to finish to avoid races in
10593 * accessing the hardware.
10594 */
10595 tg3_enable_register_access(tp);
10596 tg3_poll_fw(tp);
10597
1da177e4
LT		 10598 tg3_switch_clocks(tp);
10599
10600 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10601
2f751b67 10602 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 10603}
10604
aed93e0b
MC		 10605static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10606{
10607 int i;
10608
10609 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10610 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10611
10612 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10613 off += len;
10614
10615 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10616 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10617 memset(ocir, 0, TG3_OCIR_LEN);
10618 }
10619}
10620
10621/* sysfs attributes for hwmon */
10622static ssize_t tg3_show_temp(struct device *dev,
10623 struct device_attribute *devattr, char *buf)
10624{
10625 struct pci_dev *pdev = to_pci_dev(dev);
10626 struct net_device *netdev = pci_get_drvdata(pdev);
10627 struct tg3 *tp = netdev_priv(netdev);
10628 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10629 u32 temperature;
10630
10631 spin_lock_bh(&tp->lock);
10632 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10633 sizeof(temperature));
10634 spin_unlock_bh(&tp->lock);
10635 return sprintf(buf, "%u\n", temperature);
10636}
10637
10638
10639static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10640 TG3_TEMP_SENSOR_OFFSET);
10641static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10642 TG3_TEMP_CAUTION_OFFSET);
10643static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10644 TG3_TEMP_MAX_OFFSET);
10645
10646static struct attribute *tg3_attributes[] = {
10647 &sensor_dev_attr_temp1_input.dev_attr.attr,
10648 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10649 &sensor_dev_attr_temp1_max.dev_attr.attr,
10650 NULL
10651};
10652
10653static const struct attribute_group tg3_group = {
10654 .attrs = tg3_attributes,
10655};
10656
aed93e0b
MC		 10657static void tg3_hwmon_close(struct tg3 *tp)
10658{
aed93e0b
MC		 10659 if (tp->hwmon_dev) {
10660 hwmon_device_unregister(tp->hwmon_dev);
10661 tp->hwmon_dev = NULL;
10662 sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group);
10663 }
aed93e0b
MC		 10664}
10665
10666static void tg3_hwmon_open(struct tg3 *tp)
10667{
aed93e0b
MC		 10668 int i, err;
10669 u32 size = 0;
10670 struct pci_dev *pdev = tp->pdev;
10671 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10672
10673 tg3_sd_scan_scratchpad(tp, ocirs);
10674
10675 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10676 if (!ocirs[i].src_data_length)
10677 continue;
10678
10679 size += ocirs[i].src_hdr_length;
10680 size += ocirs[i].src_data_length;
10681 }
10682
10683 if (!size)
10684 return;
10685
10686 /* Register hwmon sysfs hooks */
10687 err = sysfs_create_group(&pdev->dev.kobj, &tg3_group);
10688 if (err) {
10689 dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n");
10690 return;
10691 }
10692
10693 tp->hwmon_dev = hwmon_device_register(&pdev->dev);
10694 if (IS_ERR(tp->hwmon_dev)) {
10695 tp->hwmon_dev = NULL;
10696 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10697 sysfs_remove_group(&pdev->dev.kobj, &tg3_group);
10698 }
aed93e0b
MC		 10699}
10700
10701
1da177e4
LT		 10702#define TG3_STAT_ADD32(PSTAT, REG) \
10703do { u32 __val = tr32(REG); \
10704 (PSTAT)->low += __val; \
10705 if ((PSTAT)->low < __val) \
10706 (PSTAT)->high += 1; \
10707} while (0)
10708
10709static void tg3_periodic_fetch_stats(struct tg3 *tp)
10710{
10711 struct tg3_hw_stats *sp = tp->hw_stats;
10712
f4a46d1f 10713 if (!tp->link_up)
1da177e4
LT		 10714 return;
10715
10716 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10717 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10718 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10719 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10720 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10721 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10722 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10723 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10724 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10725 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10726 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10727 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10728 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9bc297ea 10729 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
091f0ea3
MC		 10730 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10731 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10732 u32 val;
10733
10734 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10735 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10736 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10737 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
091f0ea3 10738 }
1da177e4
LT		 10739
10740 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10741 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10742 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10743 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10744 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10745 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10746 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10747 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10748 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10749 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10750 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10751 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10752 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10753 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 10754
10755 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
4153577a
JP		 10756 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10757 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10758 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
4d958473
MC		 10759 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10760 } else {
10761 u32 val = tr32(HOSTCC_FLOW_ATTN);
10762 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10763 if (val) {
10764 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10765 sp->rx_discards.low += val;
10766 if (sp->rx_discards.low < val)
10767 sp->rx_discards.high += 1;
10768 }
10769 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10770 }
463d305b 10771 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 10772}
10773
0e6cf6a9
MC		 10774static void tg3_chk_missed_msi(struct tg3 *tp)
10775{
10776 u32 i;
10777
10778 for (i = 0; i < tp->irq_cnt; i++) {
10779 struct tg3_napi *tnapi = &tp->napi[i];
10780
10781 if (tg3_has_work(tnapi)) {
10782 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10783 tnapi->last_tx_cons == tnapi->tx_cons) {
10784 if (tnapi->chk_msi_cnt < 1) {
10785 tnapi->chk_msi_cnt++;
10786 return;
10787 }
7f230735 10788 tg3_msi(0, tnapi);
0e6cf6a9
MC		 10789 }
10790 }
10791 tnapi->chk_msi_cnt = 0;
10792 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10793 tnapi->last_tx_cons = tnapi->tx_cons;
10794 }
10795}
10796
1da177e4
LT		 10797static void tg3_timer(unsigned long __opaque)
10798{
10799 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 10800
5b190624 10801 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
f475f163
MC		 10802 goto restart_timer;
10803
f47c11ee 10804 spin_lock(&tp->lock);
1da177e4 10805
4153577a 10806 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
55086ad9 10807 tg3_flag(tp, 57765_CLASS))
0e6cf6a9
MC		 10808 tg3_chk_missed_msi(tp);
10809
7e6c63f0
HM		 10810 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10811 /* BCM4785: Flush posted writes from GbE to host memory. */
10812 tr32(HOSTCC_MODE);
10813 }
10814
63c3a66f 10815 if (!tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 10816 /* All of this garbage is because when using non-tagged
10817 * IRQ status the mailbox/status_block protocol the chip
10818 * uses with the cpu is race prone.
10819 */
898a56f8 10820 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 10821 tw32(GRC_LOCAL_CTRL,
10822 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10823 } else {
10824 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 10825 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 10826 }
1da177e4 10827
fac9b83e 10828 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
f47c11ee 10829 spin_unlock(&tp->lock);
db219973 10830 tg3_reset_task_schedule(tp);
5b190624 10831 goto restart_timer;
fac9b83e 10832 }
1da177e4
LT		 10833 }
10834
1da177e4
LT		 10835 /* This part only runs once per second. */
10836 if (!--tp->timer_counter) {
63c3a66f 10837 if (tg3_flag(tp, 5705_PLUS))
fac9b83e
DM		 10838 tg3_periodic_fetch_stats(tp);
10839
b0c5943f
MC		 10840 if (tp->setlpicnt && !--tp->setlpicnt)
10841 tg3_phy_eee_enable(tp);
52b02d04 10842
63c3a66f 10843 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 10844 u32 mac_stat;
10845 int phy_event;
10846
10847 mac_stat = tr32(MAC_STATUS);
10848
10849 phy_event = 0;
f07e9af3 10850 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
1da177e4
LT		 10851 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10852 phy_event = 1;
10853 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10854 phy_event = 1;
10855
10856 if (phy_event)
953c96e0 10857 tg3_setup_phy(tp, false);
63c3a66f 10858 } else if (tg3_flag(tp, POLL_SERDES)) {
1da177e4
LT		 10859 u32 mac_stat = tr32(MAC_STATUS);
10860 int need_setup = 0;
10861
f4a46d1f 10862 if (tp->link_up &&
1da177e4
LT		 10863 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10864 need_setup = 1;
10865 }
f4a46d1f 10866 if (!tp->link_up &&
1da177e4
LT		 10867 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10868 MAC_STATUS_SIGNAL_DET))) {
10869 need_setup = 1;
10870 }
10871 if (need_setup) {
3d3ebe74
MC		 10872 if (!tp->serdes_counter) {
10873 tw32_f(MAC_MODE,
10874 (tp->mac_mode &
10875 ~MAC_MODE_PORT_MODE_MASK));
10876 udelay(40);
10877 tw32_f(MAC_MODE, tp->mac_mode);
10878 udelay(40);
10879 }
953c96e0 10880 tg3_setup_phy(tp, false);
1da177e4 10881 }
f07e9af3 10882 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
63c3a66f 10883 tg3_flag(tp, 5780_CLASS)) {
747e8f8b 10884 tg3_serdes_parallel_detect(tp);
57d8b880 10885 }
1da177e4
LT		 10886
10887 tp->timer_counter = tp->timer_multiplier;
10888 }
10889
130b8e4d
MC		 10890 /* Heartbeat is only sent once every 2 seconds.
10891 *
10892 * The heartbeat is to tell the ASF firmware that the host
10893 * driver is still alive. In the event that the OS crashes,
10894 * ASF needs to reset the hardware to free up the FIFO space
10895 * that may be filled with rx packets destined for the host.
10896 * If the FIFO is full, ASF will no longer function properly.
10897 *
10898 * Unintended resets have been reported on real time kernels
10899 * where the timer doesn't run on time. Netpoll will also have
10900 * same problem.
10901 *
10902 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
10903 * to check the ring condition when the heartbeat is expiring
10904 * before doing the reset. This will prevent most unintended
10905 * resets.
10906 */
1da177e4 10907 if (!--tp->asf_counter) {
63c3a66f 10908 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7c5026aa
MC		 10909 tg3_wait_for_event_ack(tp);
10910
bbadf503 10911 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 10912 FWCMD_NICDRV_ALIVE3);
bbadf503 10913 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
c6cdf436
MC		 10914 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
10915 TG3_FW_UPDATE_TIMEOUT_SEC);
4ba526ce
MC		 10916
10917 tg3_generate_fw_event(tp);
1da177e4
LT		 10918 }
10919 tp->asf_counter = tp->asf_multiplier;
10920 }
10921
f47c11ee 10922 spin_unlock(&tp->lock);
1da177e4 10923
f475f163 10924restart_timer:
1da177e4
LT		 10925 tp->timer.expires = jiffies + tp->timer_offset;
10926 add_timer(&tp->timer);
10927}
10928
229b1ad1 10929static void tg3_timer_init(struct tg3 *tp)
21f7638e
MC		 10930{
10931 if (tg3_flag(tp, TAGGED_STATUS) &&
4153577a 10932 tg3_asic_rev(tp) != ASIC_REV_5717 &&
21f7638e
MC		 10933 !tg3_flag(tp, 57765_CLASS))
10934 tp->timer_offset = HZ;
10935 else
10936 tp->timer_offset = HZ / 10;
10937
10938 BUG_ON(tp->timer_offset > HZ);
10939
10940 tp->timer_multiplier = (HZ / tp->timer_offset);
10941 tp->asf_multiplier = (HZ / tp->timer_offset) *
10942 TG3_FW_UPDATE_FREQ_SEC;
10943
10944 init_timer(&tp->timer);
10945 tp->timer.data = (unsigned long) tp;
10946 tp->timer.function = tg3_timer;
10947}
10948
10949static void tg3_timer_start(struct tg3 *tp)
10950{
10951 tp->asf_counter = tp->asf_multiplier;
10952 tp->timer_counter = tp->timer_multiplier;
10953
10954 tp->timer.expires = jiffies + tp->timer_offset;
10955 add_timer(&tp->timer);
10956}
10957
10958static void tg3_timer_stop(struct tg3 *tp)
10959{
10960 del_timer_sync(&tp->timer);
10961}
10962
10963/* Restart hardware after configuration changes, self-test, etc.
10964 * Invoked with tp->lock held.
10965 */
953c96e0 10966static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
21f7638e
MC		 10967 __releases(tp->lock)
10968 __acquires(tp->lock)
10969{
10970 int err;
10971
10972 err = tg3_init_hw(tp, reset_phy);
10973 if (err) {
10974 netdev_err(tp->dev,
10975 "Failed to re-initialize device, aborting\n");
10976 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10977 tg3_full_unlock(tp);
10978 tg3_timer_stop(tp);
10979 tp->irq_sync = 0;
10980 tg3_napi_enable(tp);
10981 dev_close(tp->dev);
10982 tg3_full_lock(tp, 0);
10983 }
10984 return err;
10985}
10986
10987static void tg3_reset_task(struct work_struct *work)
10988{
10989 struct tg3 *tp = container_of(work, struct tg3, reset_task);
10990 int err;
10991
10992 tg3_full_lock(tp, 0);
10993
10994 if (!netif_running(tp->dev)) {
10995 tg3_flag_clear(tp, RESET_TASK_PENDING);
10996 tg3_full_unlock(tp);
10997 return;
10998 }
10999
11000 tg3_full_unlock(tp);
11001
11002 tg3_phy_stop(tp);
11003
11004 tg3_netif_stop(tp);
11005
11006 tg3_full_lock(tp, 1);
11007
11008 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11009 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11010 tp->write32_rx_mbox = tg3_write_flush_reg32;
11011 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11012 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11013 }
11014
11015 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
953c96e0 11016 err = tg3_init_hw(tp, true);
21f7638e
MC		 11017 if (err)
11018 goto out;
11019
11020 tg3_netif_start(tp);
11021
11022out:
11023 tg3_full_unlock(tp);
11024
11025 if (!err)
11026 tg3_phy_start(tp);
11027
11028 tg3_flag_clear(tp, RESET_TASK_PENDING);
11029}
11030
4f125f42 11031static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 11032{
7d12e780 11033 irq_handler_t fn;
fcfa0a32 11034 unsigned long flags;
4f125f42
MC		 11035 char *name;
11036 struct tg3_napi *tnapi = &tp->napi[irq_num];
11037
11038 if (tp->irq_cnt == 1)
11039 name = tp->dev->name;
11040 else {
11041 name = &tnapi->irq_lbl[0];
11042 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
11043 name[IFNAMSIZ-1] = 0;
11044 }
fcfa0a32 11045
63c3a66f 11046 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
fcfa0a32 11047 fn = tg3_msi;
63c3a66f 11048 if (tg3_flag(tp, 1SHOT_MSI))
fcfa0a32 11049 fn = tg3_msi_1shot;
ab392d2d 11050 flags = 0;
fcfa0a32
MC		 11051 } else {
11052 fn = tg3_interrupt;
63c3a66f 11053 if (tg3_flag(tp, TAGGED_STATUS))
fcfa0a32 11054 fn = tg3_interrupt_tagged;
ab392d2d 11055 flags = IRQF_SHARED;
fcfa0a32 11056 }
4f125f42
MC		 11057
11058 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 11059}
11060
7938109f
MC		 11061static int tg3_test_interrupt(struct tg3 *tp)
11062{
09943a18 11063 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 11064 struct net_device *dev = tp->dev;
b16250e3 11065 int err, i, intr_ok = 0;
f6eb9b1f 11066 u32 val;
7938109f 11067
d4bc3927
MC		 11068 if (!netif_running(dev))
11069 return -ENODEV;
11070
7938109f
MC		 11071 tg3_disable_ints(tp);
11072
4f125f42 11073 free_irq(tnapi->irq_vec, tnapi);
7938109f 11074
f6eb9b1f
MC		 11075 /*
11076 * Turn off MSI one shot mode. Otherwise this test has no
11077 * observable way to know whether the interrupt was delivered.
11078 */
3aa1cdf8 11079 if (tg3_flag(tp, 57765_PLUS)) {
f6eb9b1f
MC		 11080 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11081 tw32(MSGINT_MODE, val);
11082 }
11083
4f125f42 11084 err = request_irq(tnapi->irq_vec, tg3_test_isr,
f274fd9a 11085 IRQF_SHARED, dev->name, tnapi);
7938109f
MC		 11086 if (err)
11087 return err;
11088
898a56f8 11089 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 11090 tg3_enable_ints(tp);
11091
11092 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 11093 tnapi->coal_now);
7938109f
MC		 11094
11095 for (i = 0; i < 5; i++) {
b16250e3
MC		 11096 u32 int_mbox, misc_host_ctrl;
11097
898a56f8 11098 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 11099 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11100
11101 if ((int_mbox != 0) ||
11102 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11103 intr_ok = 1;
7938109f 11104 break;
b16250e3
MC		 11105 }
11106
3aa1cdf8
MC		 11107 if (tg3_flag(tp, 57765_PLUS) &&
11108 tnapi->hw_status->status_tag != tnapi->last_tag)
11109 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11110
7938109f
MC		 11111 msleep(10);
11112 }
11113
11114 tg3_disable_ints(tp);
11115
4f125f42 11116 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 11117
4f125f42 11118 err = tg3_request_irq(tp, 0);
7938109f
MC		 11119
11120 if (err)
11121 return err;
11122
f6eb9b1f
MC		 11123 if (intr_ok) {
11124 /* Reenable MSI one shot mode. */
5b39de91 11125 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
f6eb9b1f
MC		 11126 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11127 tw32(MSGINT_MODE, val);
11128 }
7938109f 11129 return 0;
f6eb9b1f 11130 }
7938109f
MC		 11131
11132 return -EIO;
11133}
11134
11135/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11136 * successfully restored
11137 */
11138static int tg3_test_msi(struct tg3 *tp)
11139{
7938109f
MC		 11140 int err;
11141 u16 pci_cmd;
11142
63c3a66f 11143 if (!tg3_flag(tp, USING_MSI))
7938109f
MC		 11144 return 0;
11145
11146 /* Turn off SERR reporting in case MSI terminates with Master
11147 * Abort.
11148 */
11149 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11150 pci_write_config_word(tp->pdev, PCI_COMMAND,
11151 pci_cmd & ~PCI_COMMAND_SERR);
11152
11153 err = tg3_test_interrupt(tp);
11154
11155 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11156
11157 if (!err)
11158 return 0;
11159
11160 /* other failures */
11161 if (err != -EIO)
11162 return err;
11163
11164 /* MSI test failed, go back to INTx mode */
5129c3a3
MC		 11165 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11166 "to INTx mode. Please report this failure to the PCI "
11167 "maintainer and include system chipset information\n");
7938109f 11168
4f125f42 11169 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 11170
7938109f
MC		 11171 pci_disable_msi(tp->pdev);
11172
63c3a66f 11173 tg3_flag_clear(tp, USING_MSI);
dc8bf1b1 11174 tp->napi[0].irq_vec = tp->pdev->irq;
7938109f 11175
4f125f42 11176 err = tg3_request_irq(tp, 0);
7938109f
MC		 11177 if (err)
11178 return err;
11179
11180 /* Need to reset the chip because the MSI cycle may have terminated
11181 * with Master Abort.
11182 */
f47c11ee 11183 tg3_full_lock(tp, 1);
7938109f 11184
944d980e 11185 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 11186 err = tg3_init_hw(tp, true);
7938109f 11187
f47c11ee 11188 tg3_full_unlock(tp);
7938109f
MC		 11189
11190 if (err)
4f125f42 11191 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 11192
11193 return err;
11194}
11195
9e9fd12d
MC		 11196static int tg3_request_firmware(struct tg3 *tp)
11197{
77997ea3 11198 const struct tg3_firmware_hdr *fw_hdr;
9e9fd12d
MC		 11199
11200 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 11201 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11202 tp->fw_needed);
9e9fd12d
MC		 11203 return -ENOENT;
11204 }
11205
77997ea3 11206 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
9e9fd12d
MC		 11207
11208 /* Firmware blob starts with version numbers, followed by
11209 * start address and _full_ length including BSS sections
11210 * (which must be longer than the actual data, of course
11211 */
11212
77997ea3
NS		 11213 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11214 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
05dbe005
JP		 11215 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11216 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 11217 release_firmware(tp->fw);
11218 tp->fw = NULL;
11219 return -EINVAL;
11220 }
11221
11222 /* We no longer need firmware; we have it. */
11223 tp->fw_needed = NULL;
11224 return 0;
11225}
11226
9102426a 11227static u32 tg3_irq_count(struct tg3 *tp)
679563f4 11228{
9102426a 11229 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
679563f4 11230
9102426a 11231 if (irq_cnt > 1) {
c3b5003b
MC		 11232 /* We want as many rx rings enabled as there are cpus.
11233 * In multiqueue MSI-X mode, the first MSI-X vector
11234 * only deals with link interrupts, etc, so we add
11235 * one to the number of vectors we are requesting.
11236 */
9102426a 11237 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
c3b5003b 11238 }
679563f4 11239
9102426a
MC		 11240 return irq_cnt;
11241}
11242
11243static bool tg3_enable_msix(struct tg3 *tp)
11244{
11245 int i, rc;
86449944 11246 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
9102426a 11247
0968169c
MC		 11248 tp->txq_cnt = tp->txq_req;
11249 tp->rxq_cnt = tp->rxq_req;
11250 if (!tp->rxq_cnt)
11251 tp->rxq_cnt = netif_get_num_default_rss_queues();
9102426a
MC		 11252 if (tp->rxq_cnt > tp->rxq_max)
11253 tp->rxq_cnt = tp->rxq_max;
cf6d6ea6
MC		 11254
11255 /* Disable multiple TX rings by default. Simple round-robin hardware
11256 * scheduling of the TX rings can cause starvation of rings with
11257 * small packets when other rings have TSO or jumbo packets.
11258 */
11259 if (!tp->txq_req)
11260 tp->txq_cnt = 1;
9102426a
MC		 11261
11262 tp->irq_cnt = tg3_irq_count(tp);
11263
679563f4
MC		 11264 for (i = 0; i < tp->irq_max; i++) {
11265 msix_ent[i].entry = i;
11266 msix_ent[i].vector = 0;
11267 }
11268
11269 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
2430b031
MC		 11270 if (rc < 0) {
11271 return false;
11272 } else if (rc != 0) {
679563f4
MC		 11273 if (pci_enable_msix(tp->pdev, msix_ent, rc))
11274 return false;
05dbe005
JP		 11275 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11276 tp->irq_cnt, rc);
679563f4 11277 tp->irq_cnt = rc;
49a359e3 11278 tp->rxq_cnt = max(rc - 1, 1);
9102426a
MC		 11279 if (tp->txq_cnt)
11280 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
679563f4
MC		 11281 }
11282
11283 for (i = 0; i < tp->irq_max; i++)
11284 tp->napi[i].irq_vec = msix_ent[i].vector;
11285
49a359e3 11286 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
2ddaad39
BH		 11287 pci_disable_msix(tp->pdev);
11288 return false;
11289 }
b92b9040 11290
9102426a
MC		 11291 if (tp->irq_cnt == 1)
11292 return true;
d78b59f5 11293
9102426a
MC		 11294 tg3_flag_set(tp, ENABLE_RSS);
11295
11296 if (tp->txq_cnt > 1)
11297 tg3_flag_set(tp, ENABLE_TSS);
11298
11299 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
2430b031 11300
679563f4
MC		 11301 return true;
11302}
11303
07b0173c
MC		 11304static void tg3_ints_init(struct tg3 *tp)
11305{
63c3a66f
JP		 11306 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11307 !tg3_flag(tp, TAGGED_STATUS)) {
07b0173c
MC		 11308 /* All MSI supporting chips should support tagged
11309 * status. Assert that this is the case.
11310 */
5129c3a3
MC		 11311 netdev_warn(tp->dev,
11312 "MSI without TAGGED_STATUS? Not using MSI\n");
679563f4 11313 goto defcfg;
07b0173c 11314 }
4f125f42 11315
63c3a66f
JP		 11316 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11317 tg3_flag_set(tp, USING_MSIX);
11318 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11319 tg3_flag_set(tp, USING_MSI);
679563f4 11320
63c3a66f 11321 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
679563f4 11322 u32 msi_mode = tr32(MSGINT_MODE);
63c3a66f 11323 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
baf8a94a 11324 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 11325 if (!tg3_flag(tp, 1SHOT_MSI))
11326 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
679563f4
MC		 11327 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11328 }
11329defcfg:
63c3a66f 11330 if (!tg3_flag(tp, USING_MSIX)) {
679563f4
MC		 11331 tp->irq_cnt = 1;
11332 tp->napi[0].irq_vec = tp->pdev->irq;
49a359e3
MC		 11333 }
11334
11335 if (tp->irq_cnt == 1) {
11336 tp->txq_cnt = 1;
11337 tp->rxq_cnt = 1;
2ddaad39 11338 netif_set_real_num_tx_queues(tp->dev, 1);
85407885 11339 netif_set_real_num_rx_queues(tp->dev, 1);
679563f4 11340 }
07b0173c
MC		 11341}
11342
11343static void tg3_ints_fini(struct tg3 *tp)
11344{
63c3a66f 11345 if (tg3_flag(tp, USING_MSIX))
679563f4 11346 pci_disable_msix(tp->pdev);
63c3a66f 11347 else if (tg3_flag(tp, USING_MSI))
679563f4 11348 pci_disable_msi(tp->pdev);
63c3a66f
JP		 11349 tg3_flag_clear(tp, USING_MSI);
11350 tg3_flag_clear(tp, USING_MSIX);
11351 tg3_flag_clear(tp, ENABLE_RSS);
11352 tg3_flag_clear(tp, ENABLE_TSS);
07b0173c
MC		 11353}
11354
be947307
MC		 11355static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11356 bool init)
1da177e4 11357{
d8f4cd38 11358 struct net_device *dev = tp->dev;
4f125f42 11359 int i, err;
1da177e4 11360
679563f4
MC		 11361 /*
11362 * Setup interrupts first so we know how
11363 * many NAPI resources to allocate
11364 */
11365 tg3_ints_init(tp);
11366
90415477 11367 tg3_rss_check_indir_tbl(tp);
bcebcc46 11368
1da177e4
LT		 11369 /* The placement of this call is tied
11370 * to the setup and use of Host TX descriptors.
11371 */
11372 err = tg3_alloc_consistent(tp);
11373 if (err)
4a5f46f2 11374 goto out_ints_fini;
88b06bc2 11375
66cfd1bd
MC		 11376 tg3_napi_init(tp);
11377
fed97810 11378 tg3_napi_enable(tp);
1da177e4 11379
4f125f42
MC		 11380 for (i = 0; i < tp->irq_cnt; i++) {
11381 struct tg3_napi *tnapi = &tp->napi[i];
11382 err = tg3_request_irq(tp, i);
11383 if (err) {
5bc09186
MC		 11384 for (i--; i >= 0; i--) {
11385 tnapi = &tp->napi[i];
4f125f42 11386 free_irq(tnapi->irq_vec, tnapi);
5bc09186 11387 }
4a5f46f2 11388 goto out_napi_fini;
4f125f42
MC		 11389 }
11390 }
1da177e4 11391
f47c11ee 11392 tg3_full_lock(tp, 0);
1da177e4 11393
2e460fc0
NS		 11394 if (init)
11395 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11396
d8f4cd38 11397 err = tg3_init_hw(tp, reset_phy);
1da177e4 11398 if (err) {
944d980e 11399 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11400 tg3_free_rings(tp);
1da177e4
LT		 11401 }
11402
f47c11ee 11403 tg3_full_unlock(tp);
1da177e4 11404
07b0173c 11405 if (err)
4a5f46f2 11406 goto out_free_irq;
1da177e4 11407
d8f4cd38 11408 if (test_irq && tg3_flag(tp, USING_MSI)) {
7938109f 11409 err = tg3_test_msi(tp);
fac9b83e 11410
7938109f 11411 if (err) {
f47c11ee 11412 tg3_full_lock(tp, 0);
944d980e 11413 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 11414 tg3_free_rings(tp);
f47c11ee 11415 tg3_full_unlock(tp);
7938109f 11416
4a5f46f2 11417 goto out_napi_fini;
7938109f 11418 }
fcfa0a32 11419
63c3a66f 11420 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
f6eb9b1f 11421 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 11422
f6eb9b1f
MC		 11423 tw32(PCIE_TRANSACTION_CFG,
11424 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 11425 }
7938109f
MC		 11426 }
11427
b02fd9e3
MC		 11428 tg3_phy_start(tp);
11429
aed93e0b
MC		 11430 tg3_hwmon_open(tp);
11431
f47c11ee 11432 tg3_full_lock(tp, 0);
1da177e4 11433
21f7638e 11434 tg3_timer_start(tp);
63c3a66f 11435 tg3_flag_set(tp, INIT_COMPLETE);
1da177e4
LT		 11436 tg3_enable_ints(tp);
11437
be947307
MC		 11438 if (init)
11439 tg3_ptp_init(tp);
11440 else
11441 tg3_ptp_resume(tp);
11442
11443
f47c11ee 11444 tg3_full_unlock(tp);
1da177e4 11445
fe5f5787 11446 netif_tx_start_all_queues(dev);
1da177e4 11447
06c03c02
MB		 11448 /*
11449 * Reset loopback feature if it was turned on while the device was down
11450 * make sure that it's installed properly now.
11451 */
11452 if (dev->features & NETIF_F_LOOPBACK)
11453 tg3_set_loopback(dev, dev->features);
11454
1da177e4 11455 return 0;
07b0173c 11456
4a5f46f2 11457out_free_irq:
4f125f42
MC		 11458 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11459 struct tg3_napi *tnapi = &tp->napi[i];
11460 free_irq(tnapi->irq_vec, tnapi);
11461 }
07b0173c 11462
4a5f46f2 11463out_napi_fini:
fed97810 11464 tg3_napi_disable(tp);
66cfd1bd 11465 tg3_napi_fini(tp);
07b0173c 11466 tg3_free_consistent(tp);
679563f4 11467
4a5f46f2 11468out_ints_fini:
679563f4 11469 tg3_ints_fini(tp);
d8f4cd38 11470
07b0173c 11471 return err;
1da177e4
LT		 11472}
11473
65138594 11474static void tg3_stop(struct tg3 *tp)
1da177e4 11475{
4f125f42 11476 int i;
1da177e4 11477
db219973 11478 tg3_reset_task_cancel(tp);
bd473da3 11479 tg3_netif_stop(tp);
1da177e4 11480
21f7638e 11481 tg3_timer_stop(tp);
1da177e4 11482
aed93e0b
MC		 11483 tg3_hwmon_close(tp);
11484
24bb4fb6
MC		 11485 tg3_phy_stop(tp);
11486
f47c11ee 11487 tg3_full_lock(tp, 1);
1da177e4
LT		 11488
11489 tg3_disable_ints(tp);
11490
944d980e 11491 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11492 tg3_free_rings(tp);
63c3a66f 11493 tg3_flag_clear(tp, INIT_COMPLETE);
1da177e4 11494
f47c11ee 11495 tg3_full_unlock(tp);
1da177e4 11496
4f125f42
MC		 11497 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11498 struct tg3_napi *tnapi = &tp->napi[i];
11499 free_irq(tnapi->irq_vec, tnapi);
11500 }
07b0173c
MC		 11501
11502 tg3_ints_fini(tp);
1da177e4 11503
66cfd1bd
MC		 11504 tg3_napi_fini(tp);
11505
1da177e4 11506 tg3_free_consistent(tp);
65138594
MC		 11507}
11508
d8f4cd38
MC		 11509static int tg3_open(struct net_device *dev)
11510{
11511 struct tg3 *tp = netdev_priv(dev);
11512 int err;
11513
11514 if (tp->fw_needed) {
11515 err = tg3_request_firmware(tp);
c4dab506
NS		 11516 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11517 if (err) {
11518 netdev_warn(tp->dev, "EEE capability disabled\n");
11519 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11520 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11521 netdev_warn(tp->dev, "EEE capability restored\n");
11522 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11523 }
11524 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
d8f4cd38
MC		 11525 if (err)
11526 return err;
11527 } else if (err) {
11528 netdev_warn(tp->dev, "TSO capability disabled\n");
11529 tg3_flag_clear(tp, TSO_CAPABLE);
11530 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11531 netdev_notice(tp->dev, "TSO capability restored\n");
11532 tg3_flag_set(tp, TSO_CAPABLE);
11533 }
11534 }
11535
f4a46d1f 11536 tg3_carrier_off(tp);
d8f4cd38
MC		 11537
11538 err = tg3_power_up(tp);
11539 if (err)
11540 return err;
11541
11542 tg3_full_lock(tp, 0);
11543
11544 tg3_disable_ints(tp);
11545 tg3_flag_clear(tp, INIT_COMPLETE);
11546
11547 tg3_full_unlock(tp);
11548
942d1af0
NS		 11549 err = tg3_start(tp,
11550 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11551 true, true);
d8f4cd38
MC		 11552 if (err) {
11553 tg3_frob_aux_power(tp, false);
11554 pci_set_power_state(tp->pdev, PCI_D3hot);
11555 }
be947307 11556
7d41e49a
MC		 11557 if (tg3_flag(tp, PTP_CAPABLE)) {
11558 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11559 &tp->pdev->dev);
11560 if (IS_ERR(tp->ptp_clock))
11561 tp->ptp_clock = NULL;
11562 }
11563
07b0173c 11564 return err;
1da177e4
LT		 11565}
11566
1da177e4
LT		 11567static int tg3_close(struct net_device *dev)
11568{
11569 struct tg3 *tp = netdev_priv(dev);
11570
be947307
MC		 11571 tg3_ptp_fini(tp);
11572
65138594 11573 tg3_stop(tp);
1da177e4 11574
92feeabf
MC		 11575 /* Clear stats across close / open calls */
11576 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11577 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
1da177e4 11578
5137a2ee 11579 tg3_power_down_prepare(tp);
bc1c7567 11580
f4a46d1f 11581 tg3_carrier_off(tp);
bc1c7567 11582
1da177e4
LT		 11583 return 0;
11584}
11585
511d2224 11586static inline u64 get_stat64(tg3_stat64_t *val)
816f8b86
SB		 11587{
11588 return ((u64)val->high << 32) | ((u64)val->low);
11589}
11590
65ec698d 11591static u64 tg3_calc_crc_errors(struct tg3 *tp)
1da177e4
LT		 11592{
11593 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11594
f07e9af3 11595 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a
JP		 11596 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11597 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 11598 u32 val;
11599
569a5df8
MC		 11600 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11601 tg3_writephy(tp, MII_TG3_TEST1,
11602 val | MII_TG3_TEST1_CRC_EN);
f08aa1a8 11603 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
1da177e4
LT		 11604 } else
11605 val = 0;
1da177e4
LT		 11606
11607 tp->phy_crc_errors += val;
11608
11609 return tp->phy_crc_errors;
11610 }
11611
11612 return get_stat64(&hw_stats->rx_fcs_errors);
11613}
11614
11615#define ESTAT_ADD(member) \
11616 estats->member = old_estats->member + \
511d2224 11617 get_stat64(&hw_stats->member)
1da177e4 11618
65ec698d 11619static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
1da177e4 11620{
1da177e4
LT		 11621 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11622 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11623
1da177e4
LT		 11624 ESTAT_ADD(rx_octets);
11625 ESTAT_ADD(rx_fragments);
11626 ESTAT_ADD(rx_ucast_packets);
11627 ESTAT_ADD(rx_mcast_packets);
11628 ESTAT_ADD(rx_bcast_packets);
11629 ESTAT_ADD(rx_fcs_errors);
11630 ESTAT_ADD(rx_align_errors);
11631 ESTAT_ADD(rx_xon_pause_rcvd);
11632 ESTAT_ADD(rx_xoff_pause_rcvd);
11633 ESTAT_ADD(rx_mac_ctrl_rcvd);
11634 ESTAT_ADD(rx_xoff_entered);
11635 ESTAT_ADD(rx_frame_too_long_errors);
11636 ESTAT_ADD(rx_jabbers);
11637 ESTAT_ADD(rx_undersize_packets);
11638 ESTAT_ADD(rx_in_length_errors);
11639 ESTAT_ADD(rx_out_length_errors);
11640 ESTAT_ADD(rx_64_or_less_octet_packets);
11641 ESTAT_ADD(rx_65_to_127_octet_packets);
11642 ESTAT_ADD(rx_128_to_255_octet_packets);
11643 ESTAT_ADD(rx_256_to_511_octet_packets);
11644 ESTAT_ADD(rx_512_to_1023_octet_packets);
11645 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11646 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11647 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11648 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11649 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11650
11651 ESTAT_ADD(tx_octets);
11652 ESTAT_ADD(tx_collisions);
11653 ESTAT_ADD(tx_xon_sent);
11654 ESTAT_ADD(tx_xoff_sent);
11655 ESTAT_ADD(tx_flow_control);
11656 ESTAT_ADD(tx_mac_errors);
11657 ESTAT_ADD(tx_single_collisions);
11658 ESTAT_ADD(tx_mult_collisions);
11659 ESTAT_ADD(tx_deferred);
11660 ESTAT_ADD(tx_excessive_collisions);
11661 ESTAT_ADD(tx_late_collisions);
11662 ESTAT_ADD(tx_collide_2times);
11663 ESTAT_ADD(tx_collide_3times);
11664 ESTAT_ADD(tx_collide_4times);
11665 ESTAT_ADD(tx_collide_5times);
11666 ESTAT_ADD(tx_collide_6times);
11667 ESTAT_ADD(tx_collide_7times);
11668 ESTAT_ADD(tx_collide_8times);
11669 ESTAT_ADD(tx_collide_9times);
11670 ESTAT_ADD(tx_collide_10times);
11671 ESTAT_ADD(tx_collide_11times);
11672 ESTAT_ADD(tx_collide_12times);
11673 ESTAT_ADD(tx_collide_13times);
11674 ESTAT_ADD(tx_collide_14times);
11675 ESTAT_ADD(tx_collide_15times);
11676 ESTAT_ADD(tx_ucast_packets);
11677 ESTAT_ADD(tx_mcast_packets);
11678 ESTAT_ADD(tx_bcast_packets);
11679 ESTAT_ADD(tx_carrier_sense_errors);
11680 ESTAT_ADD(tx_discards);
11681 ESTAT_ADD(tx_errors);
11682
11683 ESTAT_ADD(dma_writeq_full);
11684 ESTAT_ADD(dma_write_prioq_full);
11685 ESTAT_ADD(rxbds_empty);
11686 ESTAT_ADD(rx_discards);
11687 ESTAT_ADD(rx_errors);
11688 ESTAT_ADD(rx_threshold_hit);
11689
11690 ESTAT_ADD(dma_readq_full);
11691 ESTAT_ADD(dma_read_prioq_full);
11692 ESTAT_ADD(tx_comp_queue_full);
11693
11694 ESTAT_ADD(ring_set_send_prod_index);
11695 ESTAT_ADD(ring_status_update);
11696 ESTAT_ADD(nic_irqs);
11697 ESTAT_ADD(nic_avoided_irqs);
11698 ESTAT_ADD(nic_tx_threshold_hit);
11699
4452d099 11700 ESTAT_ADD(mbuf_lwm_thresh_hit);
1da177e4
LT		 11701}
11702
65ec698d 11703static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
1da177e4 11704{
511d2224 11705 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
1da177e4
LT		 11706 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11707
1da177e4
LT		 11708 stats->rx_packets = old_stats->rx_packets +
11709 get_stat64(&hw_stats->rx_ucast_packets) +
11710 get_stat64(&hw_stats->rx_mcast_packets) +
11711 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 11712
1da177e4
LT		 11713 stats->tx_packets = old_stats->tx_packets +
11714 get_stat64(&hw_stats->tx_ucast_packets) +
11715 get_stat64(&hw_stats->tx_mcast_packets) +
11716 get_stat64(&hw_stats->tx_bcast_packets);
11717
11718 stats->rx_bytes = old_stats->rx_bytes +
11719 get_stat64(&hw_stats->rx_octets);
11720 stats->tx_bytes = old_stats->tx_bytes +
11721 get_stat64(&hw_stats->tx_octets);
11722
11723 stats->rx_errors = old_stats->rx_errors +
4f63b877 11724 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 11725 stats->tx_errors = old_stats->tx_errors +
11726 get_stat64(&hw_stats->tx_errors) +
11727 get_stat64(&hw_stats->tx_mac_errors) +
11728 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11729 get_stat64(&hw_stats->tx_discards);
11730
11731 stats->multicast = old_stats->multicast +
11732 get_stat64(&hw_stats->rx_mcast_packets);
11733 stats->collisions = old_stats->collisions +
11734 get_stat64(&hw_stats->tx_collisions);
11735
11736 stats->rx_length_errors = old_stats->rx_length_errors +
11737 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11738 get_stat64(&hw_stats->rx_undersize_packets);
11739
11740 stats->rx_over_errors = old_stats->rx_over_errors +
11741 get_stat64(&hw_stats->rxbds_empty);
11742 stats->rx_frame_errors = old_stats->rx_frame_errors +
11743 get_stat64(&hw_stats->rx_align_errors);
11744 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11745 get_stat64(&hw_stats->tx_discards);
11746 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11747 get_stat64(&hw_stats->tx_carrier_sense_errors);
11748
11749 stats->rx_crc_errors = old_stats->rx_crc_errors +
65ec698d 11750 tg3_calc_crc_errors(tp);
1da177e4 11751
4f63b877
JL		 11752 stats->rx_missed_errors = old_stats->rx_missed_errors +
11753 get_stat64(&hw_stats->rx_discards);
11754
b0057c51 11755 stats->rx_dropped = tp->rx_dropped;
48855432 11756 stats->tx_dropped = tp->tx_dropped;
1da177e4
LT		 11757}
11758
1da177e4
LT		 11759static int tg3_get_regs_len(struct net_device *dev)
11760{
97bd8e49 11761 return TG3_REG_BLK_SIZE;
1da177e4
LT		 11762}
11763
11764static void tg3_get_regs(struct net_device *dev,
11765 struct ethtool_regs *regs, void *_p)
11766{
1da177e4 11767 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 11768
11769 regs->version = 0;
11770
97bd8e49 11771 memset(_p, 0, TG3_REG_BLK_SIZE);
1da177e4 11772
80096068 11773 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
bc1c7567
MC		 11774 return;
11775
f47c11ee 11776 tg3_full_lock(tp, 0);
1da177e4 11777
97bd8e49 11778 tg3_dump_legacy_regs(tp, (u32 *)_p);
1da177e4 11779
f47c11ee 11780 tg3_full_unlock(tp);
1da177e4
LT		 11781}
11782
11783static int tg3_get_eeprom_len(struct net_device *dev)
11784{
11785 struct tg3 *tp = netdev_priv(dev);
11786
11787 return tp->nvram_size;
11788}
11789
1da177e4
LT		 11790static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11791{
11792 struct tg3 *tp = netdev_priv(dev);
11793 int ret;
11794 u8 *pd;
b9fc7dc5 11795 u32 i, offset, len, b_offset, b_count;
a9dc529d 11796 __be32 val;
1da177e4 11797
63c3a66f 11798 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 11799 return -EINVAL;
11800
1da177e4
LT		 11801 offset = eeprom->offset;
11802 len = eeprom->len;
11803 eeprom->len = 0;
11804
11805 eeprom->magic = TG3_EEPROM_MAGIC;
11806
11807 if (offset & 3) {
11808 /* adjustments to start on required 4 byte boundary */
11809 b_offset = offset & 3;
11810 b_count = 4 - b_offset;
11811 if (b_count > len) {
11812 /* i.e. offset=1 len=2 */
11813 b_count = len;
11814 }
a9dc529d 11815 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 11816 if (ret)
11817 return ret;
be98da6a 11818 memcpy(data, ((char *)&val) + b_offset, b_count);
1da177e4
LT		 11819 len -= b_count;
11820 offset += b_count;
c6cdf436 11821 eeprom->len += b_count;
1da177e4
LT		 11822 }
11823
25985edc 11824 /* read bytes up to the last 4 byte boundary */
1da177e4
LT		 11825 pd = &data[eeprom->len];
11826 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 11827 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 11828 if (ret) {
11829 eeprom->len += i;
11830 return ret;
11831 }
1da177e4
LT		 11832 memcpy(pd + i, &val, 4);
11833 }
11834 eeprom->len += i;
11835
11836 if (len & 3) {
11837 /* read last bytes not ending on 4 byte boundary */
11838 pd = &data[eeprom->len];
11839 b_count = len & 3;
11840 b_offset = offset + len - b_count;
a9dc529d 11841 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 11842 if (ret)
11843 return ret;
b9fc7dc5 11844 memcpy(pd, &val, b_count);
1da177e4
LT		 11845 eeprom->len += b_count;
11846 }
11847 return 0;
11848}
11849
1da177e4
LT		 11850static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11851{
11852 struct tg3 *tp = netdev_priv(dev);
11853 int ret;
b9fc7dc5 11854 u32 offset, len, b_offset, odd_len;
1da177e4 11855 u8 *buf;
a9dc529d 11856 __be32 start, end;
1da177e4 11857
63c3a66f 11858 if (tg3_flag(tp, NO_NVRAM) ||
df259d8c 11859 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 11860 return -EINVAL;
11861
11862 offset = eeprom->offset;
11863 len = eeprom->len;
11864
11865 if ((b_offset = (offset & 3))) {
11866 /* adjustments to start on required 4 byte boundary */
a9dc529d 11867 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 11868 if (ret)
11869 return ret;
1da177e4
LT		 11870 len += b_offset;
11871 offset &= ~3;
1c8594b4
MC		 11872 if (len < 4)
11873 len = 4;
1da177e4
LT		 11874 }
11875
11876 odd_len = 0;
1c8594b4 11877 if (len & 3) {
1da177e4
LT		 11878 /* adjustments to end on required 4 byte boundary */
11879 odd_len = 1;
11880 len = (len + 3) & ~3;
a9dc529d 11881 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 11882 if (ret)
11883 return ret;
1da177e4
LT		 11884 }
11885
11886 buf = data;
11887 if (b_offset || odd_len) {
11888 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 11889 if (!buf)
1da177e4
LT		 11890 return -ENOMEM;
11891 if (b_offset)
11892 memcpy(buf, &start, 4);
11893 if (odd_len)
11894 memcpy(buf+len-4, &end, 4);
11895 memcpy(buf + b_offset, data, eeprom->len);
11896 }
11897
11898 ret = tg3_nvram_write_block(tp, offset, len, buf);
11899
11900 if (buf != data)
11901 kfree(buf);
11902
11903 return ret;
11904}
11905
11906static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11907{
b02fd9e3
MC		 11908 struct tg3 *tp = netdev_priv(dev);
11909
63c3a66f 11910 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 11911 struct phy_device *phydev;
f07e9af3 11912 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 11913 return -EAGAIN;
3f0e3ad7
MC		 11914 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11915 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 11916 }
6aa20a22 11917
1da177e4
LT		 11918 cmd->supported = (SUPPORTED_Autoneg);
11919
f07e9af3 11920 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
1da177e4
LT		 11921 cmd->supported |= (SUPPORTED_1000baseT_Half |
11922 SUPPORTED_1000baseT_Full);
11923
f07e9af3 11924 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
1da177e4
LT		 11925 cmd->supported |= (SUPPORTED_100baseT_Half |
11926 SUPPORTED_100baseT_Full |
11927 SUPPORTED_10baseT_Half |
11928 SUPPORTED_10baseT_Full |
3bebab59 11929 SUPPORTED_TP);
ef348144
KK		 11930 cmd->port = PORT_TP;
11931 } else {
1da177e4 11932 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 11933 cmd->port = PORT_FIBRE;
11934 }
6aa20a22 11935
1da177e4 11936 cmd->advertising = tp->link_config.advertising;
5bb09778
MC		 11937 if (tg3_flag(tp, PAUSE_AUTONEG)) {
11938 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
11939 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11940 cmd->advertising |= ADVERTISED_Pause;
11941 } else {
11942 cmd->advertising |= ADVERTISED_Pause |
11943 ADVERTISED_Asym_Pause;
11944 }
11945 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11946 cmd->advertising |= ADVERTISED_Asym_Pause;
11947 }
11948 }
f4a46d1f 11949 if (netif_running(dev) && tp->link_up) {
70739497 11950 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
1da177e4 11951 cmd->duplex = tp->link_config.active_duplex;
859edb26 11952 cmd->lp_advertising = tp->link_config.rmt_adv;
e348c5e7
MC		 11953 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
11954 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
11955 cmd->eth_tp_mdix = ETH_TP_MDI_X;
11956 else
11957 cmd->eth_tp_mdix = ETH_TP_MDI;
11958 }
64c22182 11959 } else {
e740522e
MC		 11960 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
11961 cmd->duplex = DUPLEX_UNKNOWN;
e348c5e7 11962 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
1da177e4 11963 }
882e9793 11964 cmd->phy_address = tp->phy_addr;
7e5856bd 11965 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 11966 cmd->autoneg = tp->link_config.autoneg;
11967 cmd->maxtxpkt = 0;
11968 cmd->maxrxpkt = 0;
11969 return 0;
11970}
6aa20a22 11971
1da177e4
LT		 11972static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11973{
11974 struct tg3 *tp = netdev_priv(dev);
25db0338 11975 u32 speed = ethtool_cmd_speed(cmd);
6aa20a22 11976
63c3a66f 11977 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 11978 struct phy_device *phydev;
f07e9af3 11979 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 11980 return -EAGAIN;
3f0e3ad7
MC		 11981 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11982 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 11983 }
11984
7e5856bd
MC		 11985 if (cmd->autoneg != AUTONEG_ENABLE &&
11986 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 11987 return -EINVAL;
7e5856bd
MC		 11988
11989 if (cmd->autoneg == AUTONEG_DISABLE &&
11990 cmd->duplex != DUPLEX_FULL &&
11991 cmd->duplex != DUPLEX_HALF)
37ff238d 11992 return -EINVAL;
1da177e4 11993
7e5856bd
MC		 11994 if (cmd->autoneg == AUTONEG_ENABLE) {
11995 u32 mask = ADVERTISED_Autoneg |
11996 ADVERTISED_Pause |
11997 ADVERTISED_Asym_Pause;
11998
f07e9af3 11999 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
7e5856bd
MC		 12000 mask |= ADVERTISED_1000baseT_Half |
12001 ADVERTISED_1000baseT_Full;
12002
f07e9af3 12003 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
7e5856bd
MC		 12004 mask |= ADVERTISED_100baseT_Half |
12005 ADVERTISED_100baseT_Full |
12006 ADVERTISED_10baseT_Half |
12007 ADVERTISED_10baseT_Full |
12008 ADVERTISED_TP;
12009 else
12010 mask |= ADVERTISED_FIBRE;
12011
12012 if (cmd->advertising & ~mask)
12013 return -EINVAL;
12014
12015 mask &= (ADVERTISED_1000baseT_Half |
12016 ADVERTISED_1000baseT_Full |
12017 ADVERTISED_100baseT_Half |
12018 ADVERTISED_100baseT_Full |
12019 ADVERTISED_10baseT_Half |
12020 ADVERTISED_10baseT_Full);
12021
12022 cmd->advertising &= mask;
12023 } else {
f07e9af3 12024 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
25db0338 12025 if (speed != SPEED_1000)
7e5856bd
MC		 12026 return -EINVAL;
12027
12028 if (cmd->duplex != DUPLEX_FULL)
12029 return -EINVAL;
12030 } else {
25db0338
DD		 12031 if (speed != SPEED_100 &&
12032 speed != SPEED_10)
7e5856bd
MC		 12033 return -EINVAL;
12034 }
12035 }
12036
f47c11ee 12037 tg3_full_lock(tp, 0);
1da177e4
LT		 12038
12039 tp->link_config.autoneg = cmd->autoneg;
12040 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 12041 tp->link_config.advertising = (cmd->advertising |
12042 ADVERTISED_Autoneg);
e740522e
MC		 12043 tp->link_config.speed = SPEED_UNKNOWN;
12044 tp->link_config.duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 12045 } else {
12046 tp->link_config.advertising = 0;
25db0338 12047 tp->link_config.speed = speed;
1da177e4 12048 tp->link_config.duplex = cmd->duplex;
b02fd9e3 12049 }
6aa20a22 12050
fdad8de4
NS		 12051 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12052
ce20f161
NS		 12053 tg3_warn_mgmt_link_flap(tp);
12054
1da177e4 12055 if (netif_running(dev))
953c96e0 12056 tg3_setup_phy(tp, true);
1da177e4 12057
f47c11ee 12058 tg3_full_unlock(tp);
6aa20a22 12059
1da177e4
LT		 12060 return 0;
12061}
6aa20a22 12062
1da177e4
LT		 12063static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12064{
12065 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12066
68aad78c
RJ		 12067 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12068 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12069 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12070 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
1da177e4 12071}
6aa20a22 12072
1da177e4
LT		 12073static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12074{
12075 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12076
63c3a66f 12077 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 12078 wol->supported = WAKE_MAGIC;
12079 else
12080 wol->supported = 0;
1da177e4 12081 wol->wolopts = 0;
63c3a66f 12082 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 12083 wol->wolopts = WAKE_MAGIC;
12084 memset(&wol->sopass, 0, sizeof(wol->sopass));
12085}
6aa20a22 12086
1da177e4
LT		 12087static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12088{
12089 struct tg3 *tp = netdev_priv(dev);
12dac075 12090 struct device *dp = &tp->pdev->dev;
6aa20a22 12091
1da177e4
LT		 12092 if (wol->wolopts & ~WAKE_MAGIC)
12093 return -EINVAL;
12094 if ((wol->wolopts & WAKE_MAGIC) &&
63c3a66f 12095 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
1da177e4 12096 return -EINVAL;
6aa20a22 12097
f2dc0d18
RW		 12098 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12099
f47c11ee 12100 spin_lock_bh(&tp->lock);
f2dc0d18 12101 if (device_may_wakeup(dp))
63c3a66f 12102 tg3_flag_set(tp, WOL_ENABLE);
f2dc0d18 12103 else
63c3a66f 12104 tg3_flag_clear(tp, WOL_ENABLE);
f47c11ee 12105 spin_unlock_bh(&tp->lock);
6aa20a22 12106
1da177e4
LT		 12107 return 0;
12108}
6aa20a22 12109
1da177e4
LT		 12110static u32 tg3_get_msglevel(struct net_device *dev)
12111{
12112 struct tg3 *tp = netdev_priv(dev);
12113 return tp->msg_enable;
12114}
6aa20a22 12115
1da177e4
LT		 12116static void tg3_set_msglevel(struct net_device *dev, u32 value)
12117{
12118 struct tg3 *tp = netdev_priv(dev);
12119 tp->msg_enable = value;
12120}
6aa20a22 12121
1da177e4
LT		 12122static int tg3_nway_reset(struct net_device *dev)
12123{
12124 struct tg3 *tp = netdev_priv(dev);
1da177e4 12125 int r;
6aa20a22 12126
1da177e4
LT		 12127 if (!netif_running(dev))
12128 return -EAGAIN;
12129
f07e9af3 12130 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
c94e3941
MC		 12131 return -EINVAL;
12132
ce20f161
NS		 12133 tg3_warn_mgmt_link_flap(tp);
12134
63c3a66f 12135 if (tg3_flag(tp, USE_PHYLIB)) {
f07e9af3 12136 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12137 return -EAGAIN;
3f0e3ad7 12138 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 12139 } else {
12140 u32 bmcr;
12141
12142 spin_lock_bh(&tp->lock);
12143 r = -EINVAL;
12144 tg3_readphy(tp, MII_BMCR, &bmcr);
12145 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12146 ((bmcr & BMCR_ANENABLE) ||
f07e9af3 12147 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
b02fd9e3
MC		 12148 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12149 BMCR_ANENABLE);
12150 r = 0;
12151 }
12152 spin_unlock_bh(&tp->lock);
1da177e4 12153 }
6aa20a22 12154
1da177e4
LT		 12155 return r;
12156}
6aa20a22 12157
1da177e4
LT		 12158static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12159{
12160 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12161
2c49a44d 12162 ering->rx_max_pending = tp->rx_std_ring_mask;
63c3a66f 12163 if (tg3_flag(tp, JUMBO_RING_ENABLE))
2c49a44d 12164 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
4f81c32b
MC		 12165 else
12166 ering->rx_jumbo_max_pending = 0;
12167
12168 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 12169
12170 ering->rx_pending = tp->rx_pending;
63c3a66f 12171 if (tg3_flag(tp, JUMBO_RING_ENABLE))
4f81c32b
MC		 12172 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12173 else
12174 ering->rx_jumbo_pending = 0;
12175
f3f3f27e 12176 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 12177}
6aa20a22 12178
1da177e4
LT		 12179static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12180{
12181 struct tg3 *tp = netdev_priv(dev);
646c9edd 12182 int i, irq_sync = 0, err = 0;
6aa20a22 12183
2c49a44d
MC		 12184 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12185 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
bc3a9254
MC		 12186 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12187 (ering->tx_pending <= MAX_SKB_FRAGS) ||
63c3a66f 12188 (tg3_flag(tp, TSO_BUG) &&
bc3a9254 12189 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 12190 return -EINVAL;
6aa20a22 12191
bbe832c0 12192 if (netif_running(dev)) {
b02fd9e3 12193 tg3_phy_stop(tp);
1da177e4 12194 tg3_netif_stop(tp);
bbe832c0
MC		 12195 irq_sync = 1;
12196 }
1da177e4 12197
bbe832c0 12198 tg3_full_lock(tp, irq_sync);
6aa20a22 12199
1da177e4
LT		 12200 tp->rx_pending = ering->rx_pending;
12201
63c3a66f 12202 if (tg3_flag(tp, MAX_RXPEND_64) &&
1da177e4
LT		 12203 tp->rx_pending > 63)
12204 tp->rx_pending = 63;
12205 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd 12206
6fd45cb8 12207 for (i = 0; i < tp->irq_max; i++)
646c9edd 12208 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 12209
12210 if (netif_running(dev)) {
944d980e 12211 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12212 err = tg3_restart_hw(tp, false);
b9ec6c1b
MC		 12213 if (!err)
12214 tg3_netif_start(tp);
1da177e4
LT		 12215 }
12216
f47c11ee 12217 tg3_full_unlock(tp);
6aa20a22 12218
b02fd9e3
MC		 12219 if (irq_sync && !err)
12220 tg3_phy_start(tp);
12221
b9ec6c1b 12222 return err;
1da177e4 12223}
6aa20a22 12224
1da177e4
LT		 12225static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12226{
12227 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12228
63c3a66f 12229 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
8d018621 12230
4a2db503 12231 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
8d018621
MC		 12232 epause->rx_pause = 1;
12233 else
12234 epause->rx_pause = 0;
12235
4a2db503 12236 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
8d018621
MC		 12237 epause->tx_pause = 1;
12238 else
12239 epause->tx_pause = 0;
1da177e4 12240}
6aa20a22 12241
1da177e4
LT		 12242static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12243{
12244 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 12245 int err = 0;
6aa20a22 12246
ce20f161
NS		 12247 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12248 tg3_warn_mgmt_link_flap(tp);
12249
63c3a66f 12250 if (tg3_flag(tp, USE_PHYLIB)) {
2712168f
MC		 12251 u32 newadv;
12252 struct phy_device *phydev;
1da177e4 12253
2712168f 12254 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
f47c11ee 12255
2712168f
MC		 12256 if (!(phydev->supported & SUPPORTED_Pause) ||
12257 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
2259dca3 12258 (epause->rx_pause != epause->tx_pause)))
2712168f 12259 return -EINVAL;
1da177e4 12260
2712168f
MC		 12261 tp->link_config.flowctrl = 0;
12262 if (epause->rx_pause) {
12263 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12264
12265 if (epause->tx_pause) {
12266 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12267 newadv = ADVERTISED_Pause;
b02fd9e3 12268 } else
2712168f
MC		 12269 newadv = ADVERTISED_Pause |
12270 ADVERTISED_Asym_Pause;
12271 } else if (epause->tx_pause) {
12272 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12273 newadv = ADVERTISED_Asym_Pause;
12274 } else
12275 newadv = 0;
12276
12277 if (epause->autoneg)
63c3a66f 12278 tg3_flag_set(tp, PAUSE_AUTONEG);
2712168f 12279 else
63c3a66f 12280 tg3_flag_clear(tp, PAUSE_AUTONEG);
2712168f 12281
f07e9af3 12282 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2712168f
MC		 12283 u32 oldadv = phydev->advertising &
12284 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12285 if (oldadv != newadv) {
12286 phydev->advertising &=
12287 ~(ADVERTISED_Pause |
12288 ADVERTISED_Asym_Pause);
12289 phydev->advertising |= newadv;
12290 if (phydev->autoneg) {
12291 /*
12292 * Always renegotiate the link to
12293 * inform our link partner of our
12294 * flow control settings, even if the
12295 * flow control is forced. Let
12296 * tg3_adjust_link() do the final
12297 * flow control setup.
12298 */
12299 return phy_start_aneg(phydev);
b02fd9e3 12300 }
b02fd9e3 12301 }
b02fd9e3 12302
2712168f 12303 if (!epause->autoneg)
b02fd9e3 12304 tg3_setup_flow_control(tp, 0, 0);
2712168f 12305 } else {
c6700ce2 12306 tp->link_config.advertising &=
2712168f
MC		 12307 ~(ADVERTISED_Pause |
12308 ADVERTISED_Asym_Pause);
c6700ce2 12309 tp->link_config.advertising |= newadv;
b02fd9e3
MC		 12310 }
12311 } else {
12312 int irq_sync = 0;
12313
12314 if (netif_running(dev)) {
12315 tg3_netif_stop(tp);
12316 irq_sync = 1;
12317 }
12318
12319 tg3_full_lock(tp, irq_sync);
12320
12321 if (epause->autoneg)
63c3a66f 12322 tg3_flag_set(tp, PAUSE_AUTONEG);
b02fd9e3 12323 else
63c3a66f 12324 tg3_flag_clear(tp, PAUSE_AUTONEG);
b02fd9e3 12325 if (epause->rx_pause)
e18ce346 12326 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 12327 else
e18ce346 12328 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 12329 if (epause->tx_pause)
e18ce346 12330 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 12331 else
e18ce346 12332 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 12333
12334 if (netif_running(dev)) {
12335 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12336 err = tg3_restart_hw(tp, false);
b02fd9e3
MC		 12337 if (!err)
12338 tg3_netif_start(tp);
12339 }
12340
12341 tg3_full_unlock(tp);
12342 }
6aa20a22 12343
fdad8de4
NS		 12344 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12345
b9ec6c1b 12346 return err;
1da177e4 12347}
6aa20a22 12348
de6f31eb 12349static int tg3_get_sset_count(struct net_device *dev, int sset)
1da177e4 12350{
b9f2c044
JG		 12351 switch (sset) {
12352 case ETH_SS_TEST:
12353 return TG3_NUM_TEST;
12354 case ETH_SS_STATS:
12355 return TG3_NUM_STATS;
12356 default:
12357 return -EOPNOTSUPP;
12358 }
4cafd3f5
MC		 12359}
12360
90415477
MC		 12361static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12362 u32 *rules __always_unused)
12363{
12364 struct tg3 *tp = netdev_priv(dev);
12365
12366 if (!tg3_flag(tp, SUPPORT_MSIX))
12367 return -EOPNOTSUPP;
12368
12369 switch (info->cmd) {
12370 case ETHTOOL_GRXRINGS:
12371 if (netif_running(tp->dev))
9102426a 12372 info->data = tp->rxq_cnt;
90415477
MC		 12373 else {
12374 info->data = num_online_cpus();
9102426a
MC		 12375 if (info->data > TG3_RSS_MAX_NUM_QS)
12376 info->data = TG3_RSS_MAX_NUM_QS;
90415477
MC		 12377 }
12378
12379 /* The first interrupt vector only
12380 * handles link interrupts.
12381 */
12382 info->data -= 1;
12383 return 0;
12384
12385 default:
12386 return -EOPNOTSUPP;
12387 }
12388}
12389
12390static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12391{
12392 u32 size = 0;
12393 struct tg3 *tp = netdev_priv(dev);
12394
12395 if (tg3_flag(tp, SUPPORT_MSIX))
12396 size = TG3_RSS_INDIR_TBL_SIZE;
12397
12398 return size;
12399}
12400
12401static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
12402{
12403 struct tg3 *tp = netdev_priv(dev);
12404 int i;
12405
12406 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12407 indir[i] = tp->rss_ind_tbl[i];
12408
12409 return 0;
12410}
12411
12412static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
12413{
12414 struct tg3 *tp = netdev_priv(dev);
12415 size_t i;
12416
12417 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12418 tp->rss_ind_tbl[i] = indir[i];
12419
12420 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12421 return 0;
12422
12423 /* It is legal to write the indirection
12424 * table while the device is running.
12425 */
12426 tg3_full_lock(tp, 0);
12427 tg3_rss_write_indir_tbl(tp);
12428 tg3_full_unlock(tp);
12429
12430 return 0;
12431}
12432
0968169c
MC		 12433static void tg3_get_channels(struct net_device *dev,
12434 struct ethtool_channels *channel)
12435{
12436 struct tg3 *tp = netdev_priv(dev);
12437 u32 deflt_qs = netif_get_num_default_rss_queues();
12438
12439 channel->max_rx = tp->rxq_max;
12440 channel->max_tx = tp->txq_max;
12441
12442 if (netif_running(dev)) {
12443 channel->rx_count = tp->rxq_cnt;
12444 channel->tx_count = tp->txq_cnt;
12445 } else {
12446 if (tp->rxq_req)
12447 channel->rx_count = tp->rxq_req;
12448 else
12449 channel->rx_count = min(deflt_qs, tp->rxq_max);
12450
12451 if (tp->txq_req)
12452 channel->tx_count = tp->txq_req;
12453 else
12454 channel->tx_count = min(deflt_qs, tp->txq_max);
12455 }
12456}
12457
12458static int tg3_set_channels(struct net_device *dev,
12459 struct ethtool_channels *channel)
12460{
12461 struct tg3 *tp = netdev_priv(dev);
12462
12463 if (!tg3_flag(tp, SUPPORT_MSIX))
12464 return -EOPNOTSUPP;
12465
12466 if (channel->rx_count > tp->rxq_max ||
12467 channel->tx_count > tp->txq_max)
12468 return -EINVAL;
12469
12470 tp->rxq_req = channel->rx_count;
12471 tp->txq_req = channel->tx_count;
12472
12473 if (!netif_running(dev))
12474 return 0;
12475
12476 tg3_stop(tp);
12477
f4a46d1f 12478 tg3_carrier_off(tp);
0968169c 12479
be947307 12480 tg3_start(tp, true, false, false);
0968169c
MC		 12481
12482 return 0;
12483}
12484
de6f31eb 12485static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1da177e4
LT		 12486{
12487 switch (stringset) {
12488 case ETH_SS_STATS:
12489 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
12490 break;
4cafd3f5
MC		 12491 case ETH_SS_TEST:
12492 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
12493 break;
1da177e4
LT		 12494 default:
12495 WARN_ON(1); /* we need a WARN() */
12496 break;
12497 }
12498}
12499
81b8709c 12500static int tg3_set_phys_id(struct net_device *dev,
12501 enum ethtool_phys_id_state state)
4009a93d
MC		 12502{
12503 struct tg3 *tp = netdev_priv(dev);
4009a93d
MC		 12504
12505 if (!netif_running(tp->dev))
12506 return -EAGAIN;
12507
81b8709c 12508 switch (state) {
12509 case ETHTOOL_ID_ACTIVE:
fce55922 12510 return 1; /* cycle on/off once per second */
4009a93d 12511
81b8709c 12512 case ETHTOOL_ID_ON:
12513 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12514 LED_CTRL_1000MBPS_ON |
12515 LED_CTRL_100MBPS_ON |
12516 LED_CTRL_10MBPS_ON |
12517 LED_CTRL_TRAFFIC_OVERRIDE |
12518 LED_CTRL_TRAFFIC_BLINK |
12519 LED_CTRL_TRAFFIC_LED);
12520 break;
6aa20a22 12521
81b8709c 12522 case ETHTOOL_ID_OFF:
12523 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12524 LED_CTRL_TRAFFIC_OVERRIDE);
12525 break;
4009a93d 12526
81b8709c 12527 case ETHTOOL_ID_INACTIVE:
12528 tw32(MAC_LED_CTRL, tp->led_ctrl);
12529 break;
4009a93d 12530 }
81b8709c 12531
4009a93d
MC		 12532 return 0;
12533}
12534
de6f31eb 12535static void tg3_get_ethtool_stats(struct net_device *dev,
1da177e4
LT		 12536 struct ethtool_stats *estats, u64 *tmp_stats)
12537{
12538 struct tg3 *tp = netdev_priv(dev);
0e6c9da3 12539
b546e46f
MC		 12540 if (tp->hw_stats)
12541 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12542 else
12543 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
1da177e4
LT		 12544}
12545
535a490e 12546static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
c3e94500
MC		 12547{
12548 int i;
12549 __be32 *buf;
12550 u32 offset = 0, len = 0;
12551 u32 magic, val;
12552
63c3a66f 12553 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
c3e94500
MC		 12554 return NULL;
12555
12556 if (magic == TG3_EEPROM_MAGIC) {
12557 for (offset = TG3_NVM_DIR_START;
12558 offset < TG3_NVM_DIR_END;
12559 offset += TG3_NVM_DIRENT_SIZE) {
12560 if (tg3_nvram_read(tp, offset, &val))
12561 return NULL;
12562
12563 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12564 TG3_NVM_DIRTYPE_EXTVPD)
12565 break;
12566 }
12567
12568 if (offset != TG3_NVM_DIR_END) {
12569 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12570 if (tg3_nvram_read(tp, offset + 4, &offset))
12571 return NULL;
12572
12573 offset = tg3_nvram_logical_addr(tp, offset);
12574 }
12575 }
12576
12577 if (!offset || !len) {
12578 offset = TG3_NVM_VPD_OFF;
12579 len = TG3_NVM_VPD_LEN;
12580 }
12581
12582 buf = kmalloc(len, GFP_KERNEL);
12583 if (buf == NULL)
12584 return NULL;
12585
12586 if (magic == TG3_EEPROM_MAGIC) {
12587 for (i = 0; i < len; i += 4) {
12588 /* The data is in little-endian format in NVRAM.
12589 * Use the big-endian read routines to preserve
12590 * the byte order as it exists in NVRAM.
12591 */
12592 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12593 goto error;
12594 }
12595 } else {
12596 u8 *ptr;
12597 ssize_t cnt;
12598 unsigned int pos = 0;
12599
12600 ptr = (u8 *)&buf[0];
12601 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12602 cnt = pci_read_vpd(tp->pdev, pos,
12603 len - pos, ptr);
12604 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12605 cnt = 0;
12606 else if (cnt < 0)
12607 goto error;
12608 }
12609 if (pos != len)
12610 goto error;
12611 }
12612
535a490e
MC		 12613 *vpdlen = len;
12614
c3e94500
MC		 12615 return buf;
12616
12617error:
12618 kfree(buf);
12619 return NULL;
12620}
12621
566f86ad 12622#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 12623#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12624#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12625#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
727a6d9f
MC		 12626#define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12627#define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
bda18faf 12628#define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
b16250e3
MC		 12629#define NVRAM_SELFBOOT_HW_SIZE 0x20
12630#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 12631
12632static int tg3_test_nvram(struct tg3 *tp)
12633{
535a490e 12634 u32 csum, magic, len;
a9dc529d 12635 __be32 *buf;
ab0049b4 12636 int i, j, k, err = 0, size;
566f86ad 12637
63c3a66f 12638 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 12639 return 0;
12640
e4f34110 12641 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 12642 return -EIO;
12643
1b27777a
MC		 12644 if (magic == TG3_EEPROM_MAGIC)
12645 size = NVRAM_TEST_SIZE;
b16250e3 12646 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 12647 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12648 TG3_EEPROM_SB_FORMAT_1) {
12649 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12650 case TG3_EEPROM_SB_REVISION_0:
12651 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12652 break;
12653 case TG3_EEPROM_SB_REVISION_2:
12654 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12655 break;
12656 case TG3_EEPROM_SB_REVISION_3:
12657 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12658 break;
727a6d9f
MC		 12659 case TG3_EEPROM_SB_REVISION_4:
12660 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12661 break;
12662 case TG3_EEPROM_SB_REVISION_5:
12663 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12664 break;
12665 case TG3_EEPROM_SB_REVISION_6:
12666 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12667 break;
a5767dec 12668 default:
727a6d9f 12669 return -EIO;
a5767dec
MC		 12670 }
12671 } else
1b27777a 12672 return 0;
b16250e3
MC		 12673 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12674 size = NVRAM_SELFBOOT_HW_SIZE;
12675 else
1b27777a
MC		 12676 return -EIO;
12677
12678 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 12679 if (buf == NULL)
12680 return -ENOMEM;
12681
1b27777a
MC		 12682 err = -EIO;
12683 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 12684 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12685 if (err)
566f86ad 12686 break;
566f86ad 12687 }
1b27777a 12688 if (i < size)
566f86ad
MC		 12689 goto out;
12690
1b27777a 12691 /* Selfboot format */
a9dc529d 12692 magic = be32_to_cpu(buf[0]);
b9fc7dc5 12693 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 12694 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 12695 u8 *buf8 = (u8 *) buf, csum8 = 0;
12696
b9fc7dc5 12697 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 12698 TG3_EEPROM_SB_REVISION_2) {
12699 /* For rev 2, the csum doesn't include the MBA. */
12700 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12701 csum8 += buf8[i];
12702 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12703 csum8 += buf8[i];
12704 } else {
12705 for (i = 0; i < size; i++)
12706 csum8 += buf8[i];
12707 }
1b27777a 12708
ad96b485
AB		 12709 if (csum8 == 0) {
12710 err = 0;
12711 goto out;
12712 }
12713
12714 err = -EIO;
12715 goto out;
1b27777a 12716 }
566f86ad 12717
b9fc7dc5 12718 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 12719 TG3_EEPROM_MAGIC_HW) {
12720 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 12721 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 12722 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 12723
12724 /* Separate the parity bits and the data bytes. */
12725 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12726 if ((i == 0) || (i == 8)) {
12727 int l;
12728 u8 msk;
12729
12730 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12731 parity[k++] = buf8[i] & msk;
12732 i++;
859a5887 12733 } else if (i == 16) {
b16250e3
MC		 12734 int l;
12735 u8 msk;
12736
12737 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12738 parity[k++] = buf8[i] & msk;
12739 i++;
12740
12741 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12742 parity[k++] = buf8[i] & msk;
12743 i++;
12744 }
12745 data[j++] = buf8[i];
12746 }
12747
12748 err = -EIO;
12749 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12750 u8 hw8 = hweight8(data[i]);
12751
12752 if ((hw8 & 0x1) && parity[i])
12753 goto out;
12754 else if (!(hw8 & 0x1) && !parity[i])
12755 goto out;
12756 }
12757 err = 0;
12758 goto out;
12759 }
12760
01c3a392
MC		 12761 err = -EIO;
12762
566f86ad
MC		 12763 /* Bootstrap checksum at offset 0x10 */
12764 csum = calc_crc((unsigned char *) buf, 0x10);
01c3a392 12765 if (csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 12766 goto out;
12767
12768 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12769 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
01c3a392 12770 if (csum != le32_to_cpu(buf[0xfc/4]))
a9dc529d 12771 goto out;
566f86ad 12772
c3e94500
MC		 12773 kfree(buf);
12774
535a490e 12775 buf = tg3_vpd_readblock(tp, &len);
c3e94500
MC		 12776 if (!buf)
12777 return -ENOMEM;
d4894f3e 12778
535a490e 12779 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
d4894f3e
MC		 12780 if (i > 0) {
12781 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12782 if (j < 0)
12783 goto out;
12784
535a490e 12785 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
d4894f3e
MC		 12786 goto out;
12787
12788 i += PCI_VPD_LRDT_TAG_SIZE;
12789 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12790 PCI_VPD_RO_KEYWORD_CHKSUM);
12791 if (j > 0) {
12792 u8 csum8 = 0;
12793
12794 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12795
12796 for (i = 0; i <= j; i++)
12797 csum8 += ((u8 *)buf)[i];
12798
12799 if (csum8)
12800 goto out;
12801 }
12802 }
12803
566f86ad
MC		 12804 err = 0;
12805
12806out:
12807 kfree(buf);
12808 return err;
12809}
12810
ca43007a
MC		 12811#define TG3_SERDES_TIMEOUT_SEC 2
12812#define TG3_COPPER_TIMEOUT_SEC 6
12813
12814static int tg3_test_link(struct tg3 *tp)
12815{
12816 int i, max;
12817
12818 if (!netif_running(tp->dev))
12819 return -ENODEV;
12820
f07e9af3 12821 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
ca43007a
MC		 12822 max = TG3_SERDES_TIMEOUT_SEC;
12823 else
12824 max = TG3_COPPER_TIMEOUT_SEC;
12825
12826 for (i = 0; i < max; i++) {
f4a46d1f 12827 if (tp->link_up)
ca43007a
MC		 12828 return 0;
12829
12830 if (msleep_interruptible(1000))
12831 break;
12832 }
12833
12834 return -EIO;
12835}
12836
a71116d1 12837/* Only test the commonly used registers */
30ca3e37 12838static int tg3_test_registers(struct tg3 *tp)
a71116d1 12839{
b16250e3 12840 int i, is_5705, is_5750;
a71116d1
MC		 12841 u32 offset, read_mask, write_mask, val, save_val, read_val;
12842 static struct {
12843 u16 offset;
12844 u16 flags;
12845#define TG3_FL_5705 0x1
12846#define TG3_FL_NOT_5705 0x2
12847#define TG3_FL_NOT_5788 0x4
b16250e3 12848#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 12849 u32 read_mask;
12850 u32 write_mask;
12851 } reg_tbl[] = {
12852 /* MAC Control Registers */
12853 { MAC_MODE, TG3_FL_NOT_5705,
12854 0x00000000, 0x00ef6f8c },
12855 { MAC_MODE, TG3_FL_5705,
12856 0x00000000, 0x01ef6b8c },
12857 { MAC_STATUS, TG3_FL_NOT_5705,
12858 0x03800107, 0x00000000 },
12859 { MAC_STATUS, TG3_FL_5705,
12860 0x03800100, 0x00000000 },
12861 { MAC_ADDR_0_HIGH, 0x0000,
12862 0x00000000, 0x0000ffff },
12863 { MAC_ADDR_0_LOW, 0x0000,
c6cdf436 12864 0x00000000, 0xffffffff },
a71116d1
MC		 12865 { MAC_RX_MTU_SIZE, 0x0000,
12866 0x00000000, 0x0000ffff },
12867 { MAC_TX_MODE, 0x0000,
12868 0x00000000, 0x00000070 },
12869 { MAC_TX_LENGTHS, 0x0000,
12870 0x00000000, 0x00003fff },
12871 { MAC_RX_MODE, TG3_FL_NOT_5705,
12872 0x00000000, 0x000007fc },
12873 { MAC_RX_MODE, TG3_FL_5705,
12874 0x00000000, 0x000007dc },
12875 { MAC_HASH_REG_0, 0x0000,
12876 0x00000000, 0xffffffff },
12877 { MAC_HASH_REG_1, 0x0000,
12878 0x00000000, 0xffffffff },
12879 { MAC_HASH_REG_2, 0x0000,
12880 0x00000000, 0xffffffff },
12881 { MAC_HASH_REG_3, 0x0000,
12882 0x00000000, 0xffffffff },
12883
12884 /* Receive Data and Receive BD Initiator Control Registers. */
12885 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
12886 0x00000000, 0xffffffff },
12887 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
12888 0x00000000, 0xffffffff },
12889 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
12890 0x00000000, 0x00000003 },
12891 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
12892 0x00000000, 0xffffffff },
12893 { RCVDBDI_STD_BD+0, 0x0000,
12894 0x00000000, 0xffffffff },
12895 { RCVDBDI_STD_BD+4, 0x0000,
12896 0x00000000, 0xffffffff },
12897 { RCVDBDI_STD_BD+8, 0x0000,
12898 0x00000000, 0xffff0002 },
12899 { RCVDBDI_STD_BD+0xc, 0x0000,
12900 0x00000000, 0xffffffff },
6aa20a22 12901
a71116d1
MC		 12902 /* Receive BD Initiator Control Registers. */
12903 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
12904 0x00000000, 0xffffffff },
12905 { RCVBDI_STD_THRESH, TG3_FL_5705,
12906 0x00000000, 0x000003ff },
12907 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
12908 0x00000000, 0xffffffff },
6aa20a22 12909
a71116d1
MC		 12910 /* Host Coalescing Control Registers. */
12911 { HOSTCC_MODE, TG3_FL_NOT_5705,
12912 0x00000000, 0x00000004 },
12913 { HOSTCC_MODE, TG3_FL_5705,
12914 0x00000000, 0x000000f6 },
12915 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
12916 0x00000000, 0xffffffff },
12917 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
12918 0x00000000, 0x000003ff },
12919 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
12920 0x00000000, 0xffffffff },
12921 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
12922 0x00000000, 0x000003ff },
12923 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
12924 0x00000000, 0xffffffff },
12925 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12926 0x00000000, 0x000000ff },
12927 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
12928 0x00000000, 0xffffffff },
12929 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12930 0x00000000, 0x000000ff },
12931 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
12932 0x00000000, 0xffffffff },
12933 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
12934 0x00000000, 0xffffffff },
12935 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12936 0x00000000, 0xffffffff },
12937 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12938 0x00000000, 0x000000ff },
12939 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12940 0x00000000, 0xffffffff },
12941 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12942 0x00000000, 0x000000ff },
12943 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
12944 0x00000000, 0xffffffff },
12945 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
12946 0x00000000, 0xffffffff },
12947 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
12948 0x00000000, 0xffffffff },
12949 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
12950 0x00000000, 0xffffffff },
12951 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
12952 0x00000000, 0xffffffff },
12953 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
12954 0xffffffff, 0x00000000 },
12955 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
12956 0xffffffff, 0x00000000 },
12957
12958 /* Buffer Manager Control Registers. */
b16250e3 12959 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 12960 0x00000000, 0x007fff80 },
b16250e3 12961 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 12962 0x00000000, 0x007fffff },
12963 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
12964 0x00000000, 0x0000003f },
12965 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
12966 0x00000000, 0x000001ff },
12967 { BUFMGR_MB_HIGH_WATER, 0x0000,
12968 0x00000000, 0x000001ff },
12969 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
12970 0xffffffff, 0x00000000 },
12971 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
12972 0xffffffff, 0x00000000 },
6aa20a22 12973
a71116d1
MC		 12974 /* Mailbox Registers */
12975 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
12976 0x00000000, 0x000001ff },
12977 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
12978 0x00000000, 0x000001ff },
12979 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
12980 0x00000000, 0x000007ff },
12981 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
12982 0x00000000, 0x000001ff },
12983
12984 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
12985 };
12986
b16250e3 12987 is_5705 = is_5750 = 0;
63c3a66f 12988 if (tg3_flag(tp, 5705_PLUS)) {
a71116d1 12989 is_5705 = 1;
63c3a66f 12990 if (tg3_flag(tp, 5750_PLUS))
b16250e3
MC		 12991 is_5750 = 1;
12992 }
a71116d1
MC		 12993
12994 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
12995 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
12996 continue;
12997
12998 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
12999 continue;
13000
63c3a66f 13001 if (tg3_flag(tp, IS_5788) &&
a71116d1
MC		 13002 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13003 continue;
13004
b16250e3
MC		 13005 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13006 continue;
13007
a71116d1
MC		 13008 offset = (u32) reg_tbl[i].offset;
13009 read_mask = reg_tbl[i].read_mask;
13010 write_mask = reg_tbl[i].write_mask;
13011
13012 /* Save the original register content */
13013 save_val = tr32(offset);
13014
13015 /* Determine the read-only value. */
13016 read_val = save_val & read_mask;
13017
13018 /* Write zero to the register, then make sure the read-only bits
13019 * are not changed and the read/write bits are all zeros.
13020 */
13021 tw32(offset, 0);
13022
13023 val = tr32(offset);
13024
13025 /* Test the read-only and read/write bits. */
13026 if (((val & read_mask) != read_val) || (val & write_mask))
13027 goto out;
13028
13029 /* Write ones to all the bits defined by RdMask and WrMask, then
13030 * make sure the read-only bits are not changed and the
13031 * read/write bits are all ones.
13032 */
13033 tw32(offset, read_mask | write_mask);
13034
13035 val = tr32(offset);
13036
13037 /* Test the read-only bits. */
13038 if ((val & read_mask) != read_val)
13039 goto out;
13040
13041 /* Test the read/write bits. */
13042 if ((val & write_mask) != write_mask)
13043 goto out;
13044
13045 tw32(offset, save_val);
13046 }
13047
13048 return 0;
13049
13050out:
9f88f29f 13051 if (netif_msg_hw(tp))
2445e461
MC		 13052 netdev_err(tp->dev,
13053 "Register test failed at offset %x\n", offset);
a71116d1
MC		 13054 tw32(offset, save_val);
13055 return -EIO;
13056}
13057
7942e1db
MC		 13058static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13059{
f71e1309 13060 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 13061 int i;
13062 u32 j;
13063
e9edda69 13064 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 13065 for (j = 0; j < len; j += 4) {
13066 u32 val;
13067
13068 tg3_write_mem(tp, offset + j, test_pattern[i]);
13069 tg3_read_mem(tp, offset + j, &val);
13070 if (val != test_pattern[i])
13071 return -EIO;
13072 }
13073 }
13074 return 0;
13075}
13076
13077static int tg3_test_memory(struct tg3 *tp)
13078{
13079 static struct mem_entry {
13080 u32 offset;
13081 u32 len;
13082 } mem_tbl_570x[] = {
38690194 13083 { 0x00000000, 0x00b50},
7942e1db
MC		 13084 { 0x00002000, 0x1c000},
13085 { 0xffffffff, 0x00000}
13086 }, mem_tbl_5705[] = {
13087 { 0x00000100, 0x0000c},
13088 { 0x00000200, 0x00008},
7942e1db
MC		 13089 { 0x00004000, 0x00800},
13090 { 0x00006000, 0x01000},
13091 { 0x00008000, 0x02000},
13092 { 0x00010000, 0x0e000},
13093 { 0xffffffff, 0x00000}
79f4d13a
MC		 13094 }, mem_tbl_5755[] = {
13095 { 0x00000200, 0x00008},
13096 { 0x00004000, 0x00800},
13097 { 0x00006000, 0x00800},
13098 { 0x00008000, 0x02000},
13099 { 0x00010000, 0x0c000},
13100 { 0xffffffff, 0x00000}
b16250e3
MC		 13101 }, mem_tbl_5906[] = {
13102 { 0x00000200, 0x00008},
13103 { 0x00004000, 0x00400},
13104 { 0x00006000, 0x00400},
13105 { 0x00008000, 0x01000},
13106 { 0x00010000, 0x01000},
13107 { 0xffffffff, 0x00000}
8b5a6c42
MC		 13108 }, mem_tbl_5717[] = {
13109 { 0x00000200, 0x00008},
13110 { 0x00010000, 0x0a000},
13111 { 0x00020000, 0x13c00},
13112 { 0xffffffff, 0x00000}
13113 }, mem_tbl_57765[] = {
13114 { 0x00000200, 0x00008},
13115 { 0x00004000, 0x00800},
13116 { 0x00006000, 0x09800},
13117 { 0x00010000, 0x0a000},
13118 { 0xffffffff, 0x00000}
7942e1db
MC		 13119 };
13120 struct mem_entry *mem_tbl;
13121 int err = 0;
13122 int i;
13123
63c3a66f 13124 if (tg3_flag(tp, 5717_PLUS))
8b5a6c42 13125 mem_tbl = mem_tbl_5717;
c65a17f4 13126 else if (tg3_flag(tp, 57765_CLASS) ||
4153577a 13127 tg3_asic_rev(tp) == ASIC_REV_5762)
8b5a6c42 13128 mem_tbl = mem_tbl_57765;
63c3a66f 13129 else if (tg3_flag(tp, 5755_PLUS))
321d32a0 13130 mem_tbl = mem_tbl_5755;
4153577a 13131 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
321d32a0 13132 mem_tbl = mem_tbl_5906;
63c3a66f 13133 else if (tg3_flag(tp, 5705_PLUS))
321d32a0
MC		 13134 mem_tbl = mem_tbl_5705;
13135 else
7942e1db
MC		 13136 mem_tbl = mem_tbl_570x;
13137
13138 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
be98da6a
MC		 13139 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13140 if (err)
7942e1db
MC		 13141 break;
13142 }
6aa20a22 13143
7942e1db
MC		 13144 return err;
13145}
13146
bb158d69
MC		 13147#define TG3_TSO_MSS 500
13148
13149#define TG3_TSO_IP_HDR_LEN 20
13150#define TG3_TSO_TCP_HDR_LEN 20
13151#define TG3_TSO_TCP_OPT_LEN 12
13152
13153static const u8 tg3_tso_header[] = {
131540x08, 0x00,
131550x45, 0x00, 0x00, 0x00,
131560x00, 0x00, 0x40, 0x00,
131570x40, 0x06, 0x00, 0x00,
131580x0a, 0x00, 0x00, 0x01,
131590x0a, 0x00, 0x00, 0x02,
131600x0d, 0x00, 0xe0, 0x00,
131610x00, 0x00, 0x01, 0x00,
131620x00, 0x00, 0x02, 0x00,
131630x80, 0x10, 0x10, 0x00,
131640x14, 0x09, 0x00, 0x00,
131650x01, 0x01, 0x08, 0x0a,
131660x11, 0x11, 0x11, 0x11,
131670x11, 0x11, 0x11, 0x11,
13168};
9f40dead 13169
28a45957 13170static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
c76949a6 13171{
5e5a7f37 13172 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
bb158d69 13173 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
84b67b27 13174 u32 budget;
9205fd9c
ED		 13175 struct sk_buff *skb;
13176 u8 *tx_data, *rx_data;
c76949a6
MC		 13177 dma_addr_t map;
13178 int num_pkts, tx_len, rx_len, i, err;
13179 struct tg3_rx_buffer_desc *desc;
898a56f8 13180 struct tg3_napi *tnapi, *rnapi;
8fea32b9 13181 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
c76949a6 13182
c8873405
MC		 13183 tnapi = &tp->napi[0];
13184 rnapi = &tp->napi[0];
0c1d0e2b 13185 if (tp->irq_cnt > 1) {
63c3a66f 13186 if (tg3_flag(tp, ENABLE_RSS))
1da85aa3 13187 rnapi = &tp->napi[1];
63c3a66f 13188 if (tg3_flag(tp, ENABLE_TSS))
c8873405 13189 tnapi = &tp->napi[1];
0c1d0e2b 13190 }
fd2ce37f 13191 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 13192
c76949a6
MC		 13193 err = -EIO;
13194
4852a861 13195 tx_len = pktsz;
a20e9c62 13196 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 13197 if (!skb)
13198 return -ENOMEM;
13199
c76949a6
MC		 13200 tx_data = skb_put(skb, tx_len);
13201 memcpy(tx_data, tp->dev->dev_addr, 6);
13202 memset(tx_data + 6, 0x0, 8);
13203
4852a861 13204 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
c76949a6 13205
28a45957 13206 if (tso_loopback) {
bb158d69
MC		 13207 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13208
13209 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13210 TG3_TSO_TCP_OPT_LEN;
13211
13212 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13213 sizeof(tg3_tso_header));
13214 mss = TG3_TSO_MSS;
13215
13216 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13217 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13218
13219 /* Set the total length field in the IP header */
13220 iph->tot_len = htons((u16)(mss + hdr_len));
13221
13222 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13223 TXD_FLAG_CPU_POST_DMA);
13224
63c3a66f
JP		 13225 if (tg3_flag(tp, HW_TSO_1) ||
13226 tg3_flag(tp, HW_TSO_2) ||
13227 tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13228 struct tcphdr *th;
13229 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13230 th = (struct tcphdr *)&tx_data[val];
13231 th->check = 0;
13232 } else
13233 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13234
63c3a66f 13235 if (tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13236 mss |= (hdr_len & 0xc) << 12;
13237 if (hdr_len & 0x10)
13238 base_flags |= 0x00000010;
13239 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 13240 } else if (tg3_flag(tp, HW_TSO_2))
bb158d69 13241 mss |= hdr_len << 9;
63c3a66f 13242 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 13243 tg3_asic_rev(tp) == ASIC_REV_5705) {
bb158d69
MC		 13244 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13245 } else {
13246 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13247 }
13248
13249 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13250 } else {
13251 num_pkts = 1;
13252 data_off = ETH_HLEN;
c441b456
MC		 13253
13254 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13255 tx_len > VLAN_ETH_FRAME_LEN)
13256 base_flags |= TXD_FLAG_JMB_PKT;
bb158d69
MC		 13257 }
13258
13259 for (i = data_off; i < tx_len; i++)
c76949a6
MC		 13260 tx_data[i] = (u8) (i & 0xff);
13261
f4188d8a
AD		 13262 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13263 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 13264 dev_kfree_skb(skb);
13265 return -EIO;
13266 }
c76949a6 13267
0d681b27
MC		 13268 val = tnapi->tx_prod;
13269 tnapi->tx_buffers[val].skb = skb;
13270 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13271
c76949a6 13272 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13273 rnapi->coal_now);
c76949a6
MC		 13274
13275 udelay(10);
13276
898a56f8 13277 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 13278
84b67b27
MC		 13279 budget = tg3_tx_avail(tnapi);
13280 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
d1a3b737
MC		 13281 base_flags | TXD_FLAG_END, mss, 0)) {
13282 tnapi->tx_buffers[val].skb = NULL;
13283 dev_kfree_skb(skb);
13284 return -EIO;
13285 }
c76949a6 13286
f3f3f27e 13287 tnapi->tx_prod++;
c76949a6 13288
6541b806
MC		 13289 /* Sync BD data before updating mailbox */
13290 wmb();
13291
f3f3f27e
MC		 13292 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13293 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 13294
13295 udelay(10);
13296
303fc921
MC		 13297 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13298 for (i = 0; i < 35; i++) {
c76949a6 13299 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13300 coal_now);
c76949a6
MC		 13301
13302 udelay(10);
13303
898a56f8
MC		 13304 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13305 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 13306 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 13307 (rx_idx == (rx_start_idx + num_pkts)))
13308 break;
13309 }
13310
ba1142e4 13311 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
c76949a6
MC		 13312 dev_kfree_skb(skb);
13313
f3f3f27e 13314 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 13315 goto out;
13316
13317 if (rx_idx != rx_start_idx + num_pkts)
13318 goto out;
13319
bb158d69
MC		 13320 val = data_off;
13321 while (rx_idx != rx_start_idx) {
13322 desc = &rnapi->rx_rcb[rx_start_idx++];
13323 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13324 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
c76949a6 13325
bb158d69
MC		 13326 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13327 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13328 goto out;
c76949a6 13329
bb158d69
MC		 13330 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13331 - ETH_FCS_LEN;
c76949a6 13332
28a45957 13333 if (!tso_loopback) {
bb158d69
MC		 13334 if (rx_len != tx_len)
13335 goto out;
4852a861 13336
bb158d69
MC		 13337 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13338 if (opaque_key != RXD_OPAQUE_RING_STD)
13339 goto out;
13340 } else {
13341 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13342 goto out;
13343 }
13344 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13345 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
54e0a67f 13346 >> RXD_TCPCSUM_SHIFT != 0xffff) {
4852a861 13347 goto out;
bb158d69 13348 }
4852a861 13349
bb158d69 13350 if (opaque_key == RXD_OPAQUE_RING_STD) {
9205fd9c 13351 rx_data = tpr->rx_std_buffers[desc_idx].data;
bb158d69
MC		 13352 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13353 mapping);
13354 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
9205fd9c 13355 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
bb158d69
MC		 13356 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13357 mapping);
13358 } else
13359 goto out;
c76949a6 13360
bb158d69
MC		 13361 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13362 PCI_DMA_FROMDEVICE);
c76949a6 13363
9205fd9c 13364 rx_data += TG3_RX_OFFSET(tp);
bb158d69 13365 for (i = data_off; i < rx_len; i++, val++) {
9205fd9c 13366 if (*(rx_data + i) != (u8) (val & 0xff))
bb158d69
MC		 13367 goto out;
13368 }
c76949a6 13369 }
bb158d69 13370
c76949a6 13371 err = 0;
6aa20a22 13372
9205fd9c 13373 /* tg3_free_rings will unmap and free the rx_data */
c76949a6
MC		 13374out:
13375 return err;
13376}
13377
00c266b7
MC		 13378#define TG3_STD_LOOPBACK_FAILED 1
13379#define TG3_JMB_LOOPBACK_FAILED 2
bb158d69 13380#define TG3_TSO_LOOPBACK_FAILED 4
28a45957
MC		 13381#define TG3_LOOPBACK_FAILED \
13382 (TG3_STD_LOOPBACK_FAILED | \
13383 TG3_JMB_LOOPBACK_FAILED | \
13384 TG3_TSO_LOOPBACK_FAILED)
00c266b7 13385
941ec90f 13386static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
9f40dead 13387{
28a45957 13388 int err = -EIO;
2215e24c 13389 u32 eee_cap;
c441b456
MC		 13390 u32 jmb_pkt_sz = 9000;
13391
13392 if (tp->dma_limit)
13393 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
9f40dead 13394
ab789046
MC		 13395 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13396 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13397
28a45957 13398 if (!netif_running(tp->dev)) {
93df8b8f
NNS		 13399 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13400 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13401 if (do_extlpbk)
93df8b8f 13402 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
28a45957
MC		 13403 goto done;
13404 }
13405
953c96e0 13406 err = tg3_reset_hw(tp, true);
ab789046 13407 if (err) {
93df8b8f
NNS		 13408 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13409 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13410 if (do_extlpbk)
93df8b8f 13411 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
ab789046
MC		 13412 goto done;
13413 }
9f40dead 13414
63c3a66f 13415 if (tg3_flag(tp, ENABLE_RSS)) {
4a85f098
MC		 13416 int i;
13417
13418 /* Reroute all rx packets to the 1st queue */
13419 for (i = MAC_RSS_INDIR_TBL_0;
13420 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13421 tw32(i, 0x0);
13422 }
13423
6e01b20b
MC		 13424 /* HW errata - mac loopback fails in some cases on 5780.
13425 * Normal traffic and PHY loopback are not affected by
13426 * errata. Also, the MAC loopback test is deprecated for
13427 * all newer ASIC revisions.
13428 */
4153577a 13429 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
6e01b20b
MC		 13430 !tg3_flag(tp, CPMU_PRESENT)) {
13431 tg3_mac_loopback(tp, true);
9936bcf6 13432
28a45957 13433 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13434 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
6e01b20b
MC		 13435
13436 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13437 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13438 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
6e01b20b
MC		 13439
13440 tg3_mac_loopback(tp, false);
13441 }
4852a861 13442
f07e9af3 13443 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
63c3a66f 13444 !tg3_flag(tp, USE_PHYLIB)) {
5e5a7f37
MC		 13445 int i;
13446
941ec90f 13447 tg3_phy_lpbk_set(tp, 0, false);
5e5a7f37
MC		 13448
13449 /* Wait for link */
13450 for (i = 0; i < 100; i++) {
13451 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13452 break;
13453 mdelay(1);
13454 }
13455
28a45957 13456 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13457 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
63c3a66f 13458 if (tg3_flag(tp, TSO_CAPABLE) &&
28a45957 13459 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f 13460 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
63c3a66f 13461 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13462 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13463 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
9f40dead 13464
941ec90f
MC		 13465 if (do_extlpbk) {
13466 tg3_phy_lpbk_set(tp, 0, true);
13467
13468 /* All link indications report up, but the hardware
13469 * isn't really ready for about 20 msec. Double it
13470 * to be sure.
13471 */
13472 mdelay(40);
13473
13474 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f
NNS		 13475 data[TG3_EXT_LOOPB_TEST] |=
13476 TG3_STD_LOOPBACK_FAILED;
941ec90f
MC		 13477 if (tg3_flag(tp, TSO_CAPABLE) &&
13478 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f
NNS		 13479 data[TG3_EXT_LOOPB_TEST] |=
13480 TG3_TSO_LOOPBACK_FAILED;
941ec90f 13481 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13482 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f
NNS		 13483 data[TG3_EXT_LOOPB_TEST] |=
13484 TG3_JMB_LOOPBACK_FAILED;
941ec90f
MC		 13485 }
13486
5e5a7f37
MC		 13487 /* Re-enable gphy autopowerdown. */
13488 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13489 tg3_phy_toggle_apd(tp, true);
13490 }
6833c043 13491
93df8b8f
NNS		 13492 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13493 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
28a45957 13494
ab789046
MC		 13495done:
13496 tp->phy_flags |= eee_cap;
13497
9f40dead
MC		 13498 return err;
13499}
13500
4cafd3f5
MC		 13501static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13502 u64 *data)
13503{
566f86ad 13504 struct tg3 *tp = netdev_priv(dev);
941ec90f 13505 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
566f86ad 13506
2e460fc0
NS		 13507 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13508 if (tg3_power_up(tp)) {
13509 etest->flags |= ETH_TEST_FL_FAILED;
13510 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13511 return;
13512 }
13513 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
bed9829f 13514 }
bc1c7567 13515
566f86ad
MC		 13516 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13517
13518 if (tg3_test_nvram(tp) != 0) {
13519 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13520 data[TG3_NVRAM_TEST] = 1;
566f86ad 13521 }
941ec90f 13522 if (!doextlpbk && tg3_test_link(tp)) {
ca43007a 13523 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13524 data[TG3_LINK_TEST] = 1;
ca43007a 13525 }
a71116d1 13526 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 13527 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 13528
13529 if (netif_running(dev)) {
b02fd9e3 13530 tg3_phy_stop(tp);
a71116d1 13531 tg3_netif_stop(tp);
bbe832c0
MC		 13532 irq_sync = 1;
13533 }
a71116d1 13534
bbe832c0 13535 tg3_full_lock(tp, irq_sync);
a71116d1 13536 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 13537 err = tg3_nvram_lock(tp);
a71116d1 13538 tg3_halt_cpu(tp, RX_CPU_BASE);
63c3a66f 13539 if (!tg3_flag(tp, 5705_PLUS))
a71116d1 13540 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 13541 if (!err)
13542 tg3_nvram_unlock(tp);
a71116d1 13543
f07e9af3 13544 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
d9ab5ad1
MC		 13545 tg3_phy_reset(tp);
13546
a71116d1
MC		 13547 if (tg3_test_registers(tp) != 0) {
13548 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13549 data[TG3_REGISTER_TEST] = 1;
a71116d1 13550 }
28a45957 13551
7942e1db
MC		 13552 if (tg3_test_memory(tp) != 0) {
13553 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13554 data[TG3_MEMORY_TEST] = 1;
7942e1db 13555 }
28a45957 13556
941ec90f
MC		 13557 if (doextlpbk)
13558 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13559
93df8b8f 13560 if (tg3_test_loopback(tp, data, doextlpbk))
c76949a6 13561 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 13562
f47c11ee
DM		 13563 tg3_full_unlock(tp);
13564
d4bc3927
MC		 13565 if (tg3_test_interrupt(tp) != 0) {
13566 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13567 data[TG3_INTERRUPT_TEST] = 1;
d4bc3927 13568 }
f47c11ee
DM		 13569
13570 tg3_full_lock(tp, 0);
d4bc3927 13571
a71116d1
MC		 13572 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13573 if (netif_running(dev)) {
63c3a66f 13574 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 13575 err2 = tg3_restart_hw(tp, true);
b02fd9e3 13576 if (!err2)
b9ec6c1b 13577 tg3_netif_start(tp);
a71116d1 13578 }
f47c11ee
DM		 13579
13580 tg3_full_unlock(tp);
b02fd9e3
MC		 13581
13582 if (irq_sync && !err2)
13583 tg3_phy_start(tp);
a71116d1 13584 }
80096068 13585 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
5137a2ee 13586 tg3_power_down_prepare(tp);
bc1c7567 13587
4cafd3f5
MC		 13588}
13589
0a633ac2
MC		 13590static int tg3_hwtstamp_ioctl(struct net_device *dev,
13591 struct ifreq *ifr, int cmd)
13592{
13593 struct tg3 *tp = netdev_priv(dev);
13594 struct hwtstamp_config stmpconf;
13595
13596 if (!tg3_flag(tp, PTP_CAPABLE))
13597 return -EINVAL;
13598
13599 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13600 return -EFAULT;
13601
13602 if (stmpconf.flags)
13603 return -EINVAL;
13604
13605 switch (stmpconf.tx_type) {
13606 case HWTSTAMP_TX_ON:
13607 tg3_flag_set(tp, TX_TSTAMP_EN);
13608 break;
13609 case HWTSTAMP_TX_OFF:
13610 tg3_flag_clear(tp, TX_TSTAMP_EN);
13611 break;
13612 default:
13613 return -ERANGE;
13614 }
13615
13616 switch (stmpconf.rx_filter) {
13617 case HWTSTAMP_FILTER_NONE:
13618 tp->rxptpctl = 0;
13619 break;
13620 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13621 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13622 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13623 break;
13624 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13625 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13626 TG3_RX_PTP_CTL_SYNC_EVNT;
13627 break;
13628 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13629 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13630 TG3_RX_PTP_CTL_DELAY_REQ;
13631 break;
13632 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13633 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13634 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13635 break;
13636 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13637 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13638 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13639 break;
13640 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13641 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13642 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13643 break;
13644 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13645 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13646 TG3_RX_PTP_CTL_SYNC_EVNT;
13647 break;
13648 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13649 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13650 TG3_RX_PTP_CTL_SYNC_EVNT;
13651 break;
13652 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13653 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13654 TG3_RX_PTP_CTL_SYNC_EVNT;
13655 break;
13656 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13657 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13658 TG3_RX_PTP_CTL_DELAY_REQ;
13659 break;
13660 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13661 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13662 TG3_RX_PTP_CTL_DELAY_REQ;
13663 break;
13664 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13665 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13666 TG3_RX_PTP_CTL_DELAY_REQ;
13667 break;
13668 default:
13669 return -ERANGE;
13670 }
13671
13672 if (netif_running(dev) && tp->rxptpctl)
13673 tw32(TG3_RX_PTP_CTL,
13674 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13675
13676 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13677 -EFAULT : 0;
13678}
13679
1da177e4
LT		 13680static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13681{
13682 struct mii_ioctl_data *data = if_mii(ifr);
13683 struct tg3 *tp = netdev_priv(dev);
13684 int err;
13685
63c3a66f 13686 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 13687 struct phy_device *phydev;
f07e9af3 13688 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 13689 return -EAGAIN;
3f0e3ad7 13690 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
28b04113 13691 return phy_mii_ioctl(phydev, ifr, cmd);
b02fd9e3
MC		 13692 }
13693
33f401ae 13694 switch (cmd) {
1da177e4 13695 case SIOCGMIIPHY:
882e9793 13696 data->phy_id = tp->phy_addr;
1da177e4
LT		 13697
13698 /* fallthru */
13699 case SIOCGMIIREG: {
13700 u32 mii_regval;
13701
f07e9af3 13702 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13703 break; /* We have no PHY */
13704
34eea5ac 13705 if (!netif_running(dev))
bc1c7567
MC		 13706 return -EAGAIN;
13707
f47c11ee 13708 spin_lock_bh(&tp->lock);
5c358045
HM		 13709 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13710 data->reg_num & 0x1f, &mii_regval);
f47c11ee 13711 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13712
13713 data->val_out = mii_regval;
13714
13715 return err;
13716 }
13717
13718 case SIOCSMIIREG:
f07e9af3 13719 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13720 break; /* We have no PHY */
13721
34eea5ac 13722 if (!netif_running(dev))
bc1c7567
MC		 13723 return -EAGAIN;
13724
f47c11ee 13725 spin_lock_bh(&tp->lock);
5c358045
HM		 13726 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13727 data->reg_num & 0x1f, data->val_in);
f47c11ee 13728 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13729
13730 return err;
13731
0a633ac2
MC		 13732 case SIOCSHWTSTAMP:
13733 return tg3_hwtstamp_ioctl(dev, ifr, cmd);
13734
1da177e4
LT		 13735 default:
13736 /* do nothing */
13737 break;
13738 }
13739 return -EOPNOTSUPP;
13740}
13741
15f9850d
DM		 13742static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13743{
13744 struct tg3 *tp = netdev_priv(dev);
13745
13746 memcpy(ec, &tp->coal, sizeof(*ec));
13747 return 0;
13748}
13749
d244c892
MC		 13750static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13751{
13752 struct tg3 *tp = netdev_priv(dev);
13753 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13754 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13755
63c3a66f 13756 if (!tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 13757 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13758 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13759 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13760 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13761 }
13762
13763 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13764 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13765 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13766 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13767 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13768 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13769 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13770 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13771 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13772 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13773 return -EINVAL;
13774
13775 /* No rx interrupts will be generated if both are zero */
13776 if ((ec->rx_coalesce_usecs == 0) &&
13777 (ec->rx_max_coalesced_frames == 0))
13778 return -EINVAL;
13779
13780 /* No tx interrupts will be generated if both are zero */
13781 if ((ec->tx_coalesce_usecs == 0) &&
13782 (ec->tx_max_coalesced_frames == 0))
13783 return -EINVAL;
13784
13785 /* Only copy relevant parameters, ignore all others. */
13786 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
13787 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
13788 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
13789 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
13790 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
13791 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
13792 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
13793 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
13794 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
13795
13796 if (netif_running(dev)) {
13797 tg3_full_lock(tp, 0);
13798 __tg3_set_coalesce(tp, &tp->coal);
13799 tg3_full_unlock(tp);
13800 }
13801 return 0;
13802}
13803
1cbf9eb8
NS		 13804static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
13805{
13806 struct tg3 *tp = netdev_priv(dev);
13807
13808 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13809 netdev_warn(tp->dev, "Board does not support EEE!\n");
13810 return -EOPNOTSUPP;
13811 }
13812
13813 if (edata->advertised != tp->eee.advertised) {
13814 netdev_warn(tp->dev,
13815 "Direct manipulation of EEE advertisement is not supported\n");
13816 return -EINVAL;
13817 }
13818
13819 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
13820 netdev_warn(tp->dev,
13821 "Maximal Tx Lpi timer supported is %#x(u)\n",
13822 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
13823 return -EINVAL;
13824 }
13825
13826 tp->eee = *edata;
13827
13828 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
13829 tg3_warn_mgmt_link_flap(tp);
13830
13831 if (netif_running(tp->dev)) {
13832 tg3_full_lock(tp, 0);
13833 tg3_setup_eee(tp);
13834 tg3_phy_reset(tp);
13835 tg3_full_unlock(tp);
13836 }
13837
13838 return 0;
13839}
13840
13841static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
13842{
13843 struct tg3 *tp = netdev_priv(dev);
13844
13845 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13846 netdev_warn(tp->dev,
13847 "Board does not support EEE!\n");
13848 return -EOPNOTSUPP;
13849 }
13850
13851 *edata = tp->eee;
13852 return 0;
13853}
13854
7282d491 13855static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 13856 .get_settings = tg3_get_settings,
13857 .set_settings = tg3_set_settings,
13858 .get_drvinfo = tg3_get_drvinfo,
13859 .get_regs_len = tg3_get_regs_len,
13860 .get_regs = tg3_get_regs,
13861 .get_wol = tg3_get_wol,
13862 .set_wol = tg3_set_wol,
13863 .get_msglevel = tg3_get_msglevel,
13864 .set_msglevel = tg3_set_msglevel,
13865 .nway_reset = tg3_nway_reset,
13866 .get_link = ethtool_op_get_link,
13867 .get_eeprom_len = tg3_get_eeprom_len,
13868 .get_eeprom = tg3_get_eeprom,
13869 .set_eeprom = tg3_set_eeprom,
13870 .get_ringparam = tg3_get_ringparam,
13871 .set_ringparam = tg3_set_ringparam,
13872 .get_pauseparam = tg3_get_pauseparam,
13873 .set_pauseparam = tg3_set_pauseparam,
4cafd3f5 13874 .self_test = tg3_self_test,
1da177e4 13875 .get_strings = tg3_get_strings,
81b8709c 13876 .set_phys_id = tg3_set_phys_id,
1da177e4 13877 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 13878 .get_coalesce = tg3_get_coalesce,
d244c892 13879 .set_coalesce = tg3_set_coalesce,
b9f2c044 13880 .get_sset_count = tg3_get_sset_count,
90415477
MC		 13881 .get_rxnfc = tg3_get_rxnfc,
13882 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
13883 .get_rxfh_indir = tg3_get_rxfh_indir,
13884 .set_rxfh_indir = tg3_set_rxfh_indir,
0968169c
MC		 13885 .get_channels = tg3_get_channels,
13886 .set_channels = tg3_set_channels,
7d41e49a 13887 .get_ts_info = tg3_get_ts_info,
1cbf9eb8
NS		 13888 .get_eee = tg3_get_eee,
13889 .set_eee = tg3_set_eee,
1da177e4
LT		 13890};
13891
b4017c53
DM		 13892static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
13893 struct rtnl_link_stats64 *stats)
13894{
13895 struct tg3 *tp = netdev_priv(dev);
13896
0f566b20
MC		 13897 spin_lock_bh(&tp->lock);
13898 if (!tp->hw_stats) {
13899 spin_unlock_bh(&tp->lock);
b4017c53 13900 return &tp->net_stats_prev;
0f566b20 13901 }
b4017c53 13902
b4017c53
DM		 13903 tg3_get_nstats(tp, stats);
13904 spin_unlock_bh(&tp->lock);
13905
13906 return stats;
13907}
13908
ccd5ba9d
MC		 13909static void tg3_set_rx_mode(struct net_device *dev)
13910{
13911 struct tg3 *tp = netdev_priv(dev);
13912
13913 if (!netif_running(dev))
13914 return;
13915
13916 tg3_full_lock(tp, 0);
13917 __tg3_set_rx_mode(dev);
13918 tg3_full_unlock(tp);
13919}
13920
faf1627a
MC		 13921static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
13922 int new_mtu)
13923{
13924 dev->mtu = new_mtu;
13925
13926 if (new_mtu > ETH_DATA_LEN) {
13927 if (tg3_flag(tp, 5780_CLASS)) {
13928 netdev_update_features(dev);
13929 tg3_flag_clear(tp, TSO_CAPABLE);
13930 } else {
13931 tg3_flag_set(tp, JUMBO_RING_ENABLE);
13932 }
13933 } else {
13934 if (tg3_flag(tp, 5780_CLASS)) {
13935 tg3_flag_set(tp, TSO_CAPABLE);
13936 netdev_update_features(dev);
13937 }
13938 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
13939 }
13940}
13941
13942static int tg3_change_mtu(struct net_device *dev, int new_mtu)
13943{
13944 struct tg3 *tp = netdev_priv(dev);
953c96e0
JP		 13945 int err;
13946 bool reset_phy = false;
faf1627a
MC		 13947
13948 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
13949 return -EINVAL;
13950
13951 if (!netif_running(dev)) {
13952 /* We'll just catch it later when the
13953 * device is up'd.
13954 */
13955 tg3_set_mtu(dev, tp, new_mtu);
13956 return 0;
13957 }
13958
13959 tg3_phy_stop(tp);
13960
13961 tg3_netif_stop(tp);
13962
13963 tg3_full_lock(tp, 1);
13964
13965 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13966
13967 tg3_set_mtu(dev, tp, new_mtu);
13968
2fae5e36
MC		 13969 /* Reset PHY, otherwise the read DMA engine will be in a mode that
13970 * breaks all requests to 256 bytes.
13971 */
4153577a 13972 if (tg3_asic_rev(tp) == ASIC_REV_57766)
953c96e0 13973 reset_phy = true;
2fae5e36
MC		 13974
13975 err = tg3_restart_hw(tp, reset_phy);
faf1627a
MC		 13976
13977 if (!err)
13978 tg3_netif_start(tp);
13979
13980 tg3_full_unlock(tp);
13981
13982 if (!err)
13983 tg3_phy_start(tp);
13984
13985 return err;
13986}
13987
13988static const struct net_device_ops tg3_netdev_ops = {
13989 .ndo_open = tg3_open,
13990 .ndo_stop = tg3_close,
13991 .ndo_start_xmit = tg3_start_xmit,
13992 .ndo_get_stats64 = tg3_get_stats64,
13993 .ndo_validate_addr = eth_validate_addr,
13994 .ndo_set_rx_mode = tg3_set_rx_mode,
13995 .ndo_set_mac_address = tg3_set_mac_addr,
13996 .ndo_do_ioctl = tg3_ioctl,
13997 .ndo_tx_timeout = tg3_tx_timeout,
13998 .ndo_change_mtu = tg3_change_mtu,
13999 .ndo_fix_features = tg3_fix_features,
14000 .ndo_set_features = tg3_set_features,
14001#ifdef CONFIG_NET_POLL_CONTROLLER
14002 .ndo_poll_controller = tg3_poll_controller,
14003#endif
14004};
14005
229b1ad1 14006static void tg3_get_eeprom_size(struct tg3 *tp)
1da177e4 14007{
1b27777a 14008 u32 cursize, val, magic;
1da177e4
LT		 14009
14010 tp->nvram_size = EEPROM_CHIP_SIZE;
14011
e4f34110 14012 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 14013 return;
14014
b16250e3
MC		 14015 if ((magic != TG3_EEPROM_MAGIC) &&
14016 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14017 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 14018 return;
14019
14020 /*
14021 * Size the chip by reading offsets at increasing powers of two.
14022 * When we encounter our validation signature, we know the addressing
14023 * has wrapped around, and thus have our chip size.
14024 */
1b27777a 14025 cursize = 0x10;
1da177e4
LT		 14026
14027 while (cursize < tp->nvram_size) {
e4f34110 14028 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 14029 return;
14030
1820180b 14031 if (val == magic)
1da177e4
LT		 14032 break;
14033
14034 cursize <<= 1;
14035 }
14036
14037 tp->nvram_size = cursize;
14038}
6aa20a22 14039
229b1ad1 14040static void tg3_get_nvram_size(struct tg3 *tp)
1da177e4
LT		 14041{
14042 u32 val;
14043
63c3a66f 14044 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 14045 return;
14046
14047 /* Selfboot format */
1820180b 14048 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 14049 tg3_get_eeprom_size(tp);
14050 return;
14051 }
14052
6d348f2c 14053 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 14054 if (val != 0) {
6d348f2c
MC		 14055 /* This is confusing. We want to operate on the
14056 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14057 * call will read from NVRAM and byteswap the data
14058 * according to the byteswapping settings for all
14059 * other register accesses. This ensures the data we
14060 * want will always reside in the lower 16-bits.
14061 * However, the data in NVRAM is in LE format, which
14062 * means the data from the NVRAM read will always be
14063 * opposite the endianness of the CPU. The 16-bit
14064 * byteswap then brings the data to CPU endianness.
14065 */
14066 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 14067 return;
14068 }
14069 }
fd1122a2 14070 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 14071}
14072
229b1ad1 14073static void tg3_get_nvram_info(struct tg3 *tp)
1da177e4
LT		 14074{
14075 u32 nvcfg1;
14076
14077 nvcfg1 = tr32(NVRAM_CFG1);
14078 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
63c3a66f 14079 tg3_flag_set(tp, FLASH);
8590a603 14080 } else {
1da177e4
LT		 14081 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14082 tw32(NVRAM_CFG1, nvcfg1);
14083 }
14084
4153577a 14085 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
63c3a66f 14086 tg3_flag(tp, 5780_CLASS)) {
1da177e4 14087 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 14088 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14089 tp->nvram_jedecnum = JEDEC_ATMEL;
14090 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14091 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14092 break;
14093 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14094 tp->nvram_jedecnum = JEDEC_ATMEL;
14095 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14096 break;
14097 case FLASH_VENDOR_ATMEL_EEPROM:
14098 tp->nvram_jedecnum = JEDEC_ATMEL;
14099 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
63c3a66f 14100 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14101 break;
14102 case FLASH_VENDOR_ST:
14103 tp->nvram_jedecnum = JEDEC_ST;
14104 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
63c3a66f 14105 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14106 break;
14107 case FLASH_VENDOR_SAIFUN:
14108 tp->nvram_jedecnum = JEDEC_SAIFUN;
14109 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14110 break;
14111 case FLASH_VENDOR_SST_SMALL:
14112 case FLASH_VENDOR_SST_LARGE:
14113 tp->nvram_jedecnum = JEDEC_SST;
14114 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14115 break;
1da177e4 14116 }
8590a603 14117 } else {
1da177e4
LT		 14118 tp->nvram_jedecnum = JEDEC_ATMEL;
14119 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14120 tg3_flag_set(tp, NVRAM_BUFFERED);
1da177e4
LT		 14121 }
14122}
14123
229b1ad1 14124static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
a1b950d5
MC		 14125{
14126 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14127 case FLASH_5752PAGE_SIZE_256:
14128 tp->nvram_pagesize = 256;
14129 break;
14130 case FLASH_5752PAGE_SIZE_512:
14131 tp->nvram_pagesize = 512;
14132 break;
14133 case FLASH_5752PAGE_SIZE_1K:
14134 tp->nvram_pagesize = 1024;
14135 break;
14136 case FLASH_5752PAGE_SIZE_2K:
14137 tp->nvram_pagesize = 2048;
14138 break;
14139 case FLASH_5752PAGE_SIZE_4K:
14140 tp->nvram_pagesize = 4096;
14141 break;
14142 case FLASH_5752PAGE_SIZE_264:
14143 tp->nvram_pagesize = 264;
14144 break;
14145 case FLASH_5752PAGE_SIZE_528:
14146 tp->nvram_pagesize = 528;
14147 break;
14148 }
14149}
14150
229b1ad1 14151static void tg3_get_5752_nvram_info(struct tg3 *tp)
361b4ac2
MC		 14152{
14153 u32 nvcfg1;
14154
14155 nvcfg1 = tr32(NVRAM_CFG1);
14156
e6af301b
MC		 14157 /* NVRAM protection for TPM */
14158 if (nvcfg1 & (1 << 27))
63c3a66f 14159 tg3_flag_set(tp, PROTECTED_NVRAM);
e6af301b 14160
361b4ac2 14161 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14162 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14163 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14164 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14165 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14166 break;
14167 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14168 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14169 tg3_flag_set(tp, NVRAM_BUFFERED);
14170 tg3_flag_set(tp, FLASH);
8590a603
MC		 14171 break;
14172 case FLASH_5752VENDOR_ST_M45PE10:
14173 case FLASH_5752VENDOR_ST_M45PE20:
14174 case FLASH_5752VENDOR_ST_M45PE40:
14175 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14176 tg3_flag_set(tp, NVRAM_BUFFERED);
14177 tg3_flag_set(tp, FLASH);
8590a603 14178 break;
361b4ac2
MC		 14179 }
14180
63c3a66f 14181 if (tg3_flag(tp, FLASH)) {
a1b950d5 14182 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 14183 } else {
361b4ac2
MC		 14184 /* For eeprom, set pagesize to maximum eeprom size */
14185 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14186
14187 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14188 tw32(NVRAM_CFG1, nvcfg1);
14189 }
14190}
14191
229b1ad1 14192static void tg3_get_5755_nvram_info(struct tg3 *tp)
d3c7b886 14193{
989a9d23 14194 u32 nvcfg1, protect = 0;
d3c7b886
MC		 14195
14196 nvcfg1 = tr32(NVRAM_CFG1);
14197
14198 /* NVRAM protection for TPM */
989a9d23 14199 if (nvcfg1 & (1 << 27)) {
63c3a66f 14200 tg3_flag_set(tp, PROTECTED_NVRAM);
989a9d23
MC		 14201 protect = 1;
14202 }
d3c7b886 14203
989a9d23
MC		 14204 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14205 switch (nvcfg1) {
8590a603
MC		 14206 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14207 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14208 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14209 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14210 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14211 tg3_flag_set(tp, NVRAM_BUFFERED);
14212 tg3_flag_set(tp, FLASH);
8590a603
MC		 14213 tp->nvram_pagesize = 264;
14214 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14215 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14216 tp->nvram_size = (protect ? 0x3e200 :
14217 TG3_NVRAM_SIZE_512KB);
14218 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14219 tp->nvram_size = (protect ? 0x1f200 :
14220 TG3_NVRAM_SIZE_256KB);
14221 else
14222 tp->nvram_size = (protect ? 0x1f200 :
14223 TG3_NVRAM_SIZE_128KB);
14224 break;
14225 case FLASH_5752VENDOR_ST_M45PE10:
14226 case FLASH_5752VENDOR_ST_M45PE20:
14227 case FLASH_5752VENDOR_ST_M45PE40:
14228 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14229 tg3_flag_set(tp, NVRAM_BUFFERED);
14230 tg3_flag_set(tp, FLASH);
8590a603
MC		 14231 tp->nvram_pagesize = 256;
14232 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14233 tp->nvram_size = (protect ?
14234 TG3_NVRAM_SIZE_64KB :
14235 TG3_NVRAM_SIZE_128KB);
14236 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14237 tp->nvram_size = (protect ?
14238 TG3_NVRAM_SIZE_64KB :
14239 TG3_NVRAM_SIZE_256KB);
14240 else
14241 tp->nvram_size = (protect ?
14242 TG3_NVRAM_SIZE_128KB :
14243 TG3_NVRAM_SIZE_512KB);
14244 break;
d3c7b886
MC		 14245 }
14246}
14247
229b1ad1 14248static void tg3_get_5787_nvram_info(struct tg3 *tp)
1b27777a
MC		 14249{
14250 u32 nvcfg1;
14251
14252 nvcfg1 = tr32(NVRAM_CFG1);
14253
14254 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14255 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14256 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14257 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14258 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14259 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14260 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603 14261 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 14262
8590a603
MC		 14263 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14264 tw32(NVRAM_CFG1, nvcfg1);
14265 break;
14266 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14267 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14268 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14269 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14270 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14271 tg3_flag_set(tp, NVRAM_BUFFERED);
14272 tg3_flag_set(tp, FLASH);
8590a603
MC		 14273 tp->nvram_pagesize = 264;
14274 break;
14275 case FLASH_5752VENDOR_ST_M45PE10:
14276 case FLASH_5752VENDOR_ST_M45PE20:
14277 case FLASH_5752VENDOR_ST_M45PE40:
14278 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14279 tg3_flag_set(tp, NVRAM_BUFFERED);
14280 tg3_flag_set(tp, FLASH);
8590a603
MC		 14281 tp->nvram_pagesize = 256;
14282 break;
1b27777a
MC		 14283 }
14284}
14285
229b1ad1 14286static void tg3_get_5761_nvram_info(struct tg3 *tp)
6b91fa02
MC		 14287{
14288 u32 nvcfg1, protect = 0;
14289
14290 nvcfg1 = tr32(NVRAM_CFG1);
14291
14292 /* NVRAM protection for TPM */
14293 if (nvcfg1 & (1 << 27)) {
63c3a66f 14294 tg3_flag_set(tp, PROTECTED_NVRAM);
6b91fa02
MC		 14295 protect = 1;
14296 }
14297
14298 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14299 switch (nvcfg1) {
8590a603
MC		 14300 case FLASH_5761VENDOR_ATMEL_ADB021D:
14301 case FLASH_5761VENDOR_ATMEL_ADB041D:
14302 case FLASH_5761VENDOR_ATMEL_ADB081D:
14303 case FLASH_5761VENDOR_ATMEL_ADB161D:
14304 case FLASH_5761VENDOR_ATMEL_MDB021D:
14305 case FLASH_5761VENDOR_ATMEL_MDB041D:
14306 case FLASH_5761VENDOR_ATMEL_MDB081D:
14307 case FLASH_5761VENDOR_ATMEL_MDB161D:
14308 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14309 tg3_flag_set(tp, NVRAM_BUFFERED);
14310 tg3_flag_set(tp, FLASH);
14311 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
8590a603
MC		 14312 tp->nvram_pagesize = 256;
14313 break;
14314 case FLASH_5761VENDOR_ST_A_M45PE20:
14315 case FLASH_5761VENDOR_ST_A_M45PE40:
14316 case FLASH_5761VENDOR_ST_A_M45PE80:
14317 case FLASH_5761VENDOR_ST_A_M45PE16:
14318 case FLASH_5761VENDOR_ST_M_M45PE20:
14319 case FLASH_5761VENDOR_ST_M_M45PE40:
14320 case FLASH_5761VENDOR_ST_M_M45PE80:
14321 case FLASH_5761VENDOR_ST_M_M45PE16:
14322 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14323 tg3_flag_set(tp, NVRAM_BUFFERED);
14324 tg3_flag_set(tp, FLASH);
8590a603
MC		 14325 tp->nvram_pagesize = 256;
14326 break;
6b91fa02
MC		 14327 }
14328
14329 if (protect) {
14330 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14331 } else {
14332 switch (nvcfg1) {
8590a603
MC		 14333 case FLASH_5761VENDOR_ATMEL_ADB161D:
14334 case FLASH_5761VENDOR_ATMEL_MDB161D:
14335 case FLASH_5761VENDOR_ST_A_M45PE16:
14336 case FLASH_5761VENDOR_ST_M_M45PE16:
14337 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14338 break;
14339 case FLASH_5761VENDOR_ATMEL_ADB081D:
14340 case FLASH_5761VENDOR_ATMEL_MDB081D:
14341 case FLASH_5761VENDOR_ST_A_M45PE80:
14342 case FLASH_5761VENDOR_ST_M_M45PE80:
14343 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14344 break;
14345 case FLASH_5761VENDOR_ATMEL_ADB041D:
14346 case FLASH_5761VENDOR_ATMEL_MDB041D:
14347 case FLASH_5761VENDOR_ST_A_M45PE40:
14348 case FLASH_5761VENDOR_ST_M_M45PE40:
14349 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14350 break;
14351 case FLASH_5761VENDOR_ATMEL_ADB021D:
14352 case FLASH_5761VENDOR_ATMEL_MDB021D:
14353 case FLASH_5761VENDOR_ST_A_M45PE20:
14354 case FLASH_5761VENDOR_ST_M_M45PE20:
14355 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14356 break;
6b91fa02
MC		 14357 }
14358 }
14359}
14360
229b1ad1 14361static void tg3_get_5906_nvram_info(struct tg3 *tp)
b5d3772c
MC		 14362{
14363 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14364 tg3_flag_set(tp, NVRAM_BUFFERED);
b5d3772c
MC		 14365 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14366}
14367
229b1ad1 14368static void tg3_get_57780_nvram_info(struct tg3 *tp)
321d32a0
MC		 14369{
14370 u32 nvcfg1;
14371
14372 nvcfg1 = tr32(NVRAM_CFG1);
14373
14374 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14375 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14376 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14377 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14378 tg3_flag_set(tp, NVRAM_BUFFERED);
321d32a0
MC		 14379 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14380
14381 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14382 tw32(NVRAM_CFG1, nvcfg1);
14383 return;
14384 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14385 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14386 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14387 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14388 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14389 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14390 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14391 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14392 tg3_flag_set(tp, NVRAM_BUFFERED);
14393 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14394
14395 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14396 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14397 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14398 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14399 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14400 break;
14401 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14402 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14403 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14404 break;
14405 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14406 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14407 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14408 break;
14409 }
14410 break;
14411 case FLASH_5752VENDOR_ST_M45PE10:
14412 case FLASH_5752VENDOR_ST_M45PE20:
14413 case FLASH_5752VENDOR_ST_M45PE40:
14414 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14415 tg3_flag_set(tp, NVRAM_BUFFERED);
14416 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14417
14418 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14419 case FLASH_5752VENDOR_ST_M45PE10:
14420 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14421 break;
14422 case FLASH_5752VENDOR_ST_M45PE20:
14423 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14424 break;
14425 case FLASH_5752VENDOR_ST_M45PE40:
14426 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14427 break;
14428 }
14429 break;
14430 default:
63c3a66f 14431 tg3_flag_set(tp, NO_NVRAM);
321d32a0
MC		 14432 return;
14433 }
14434
a1b950d5
MC		 14435 tg3_nvram_get_pagesize(tp, nvcfg1);
14436 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14437 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
a1b950d5
MC		 14438}
14439
14440
229b1ad1 14441static void tg3_get_5717_nvram_info(struct tg3 *tp)
a1b950d5
MC		 14442{
14443 u32 nvcfg1;
14444
14445 nvcfg1 = tr32(NVRAM_CFG1);
14446
14447 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14448 case FLASH_5717VENDOR_ATMEL_EEPROM:
14449 case FLASH_5717VENDOR_MICRO_EEPROM:
14450 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14451 tg3_flag_set(tp, NVRAM_BUFFERED);
a1b950d5
MC		 14452 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14453
14454 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14455 tw32(NVRAM_CFG1, nvcfg1);
14456 return;
14457 case FLASH_5717VENDOR_ATMEL_MDB011D:
14458 case FLASH_5717VENDOR_ATMEL_ADB011B:
14459 case FLASH_5717VENDOR_ATMEL_ADB011D:
14460 case FLASH_5717VENDOR_ATMEL_MDB021D:
14461 case FLASH_5717VENDOR_ATMEL_ADB021B:
14462 case FLASH_5717VENDOR_ATMEL_ADB021D:
14463 case FLASH_5717VENDOR_ATMEL_45USPT:
14464 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14465 tg3_flag_set(tp, NVRAM_BUFFERED);
14466 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14467
14468 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14469 case FLASH_5717VENDOR_ATMEL_MDB021D:
66ee33bf
MC		 14470 /* Detect size with tg3_nvram_get_size() */
14471 break;
a1b950d5
MC		 14472 case FLASH_5717VENDOR_ATMEL_ADB021B:
14473 case FLASH_5717VENDOR_ATMEL_ADB021D:
14474 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14475 break;
14476 default:
14477 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14478 break;
14479 }
321d32a0 14480 break;
a1b950d5
MC		 14481 case FLASH_5717VENDOR_ST_M_M25PE10:
14482 case FLASH_5717VENDOR_ST_A_M25PE10:
14483 case FLASH_5717VENDOR_ST_M_M45PE10:
14484 case FLASH_5717VENDOR_ST_A_M45PE10:
14485 case FLASH_5717VENDOR_ST_M_M25PE20:
14486 case FLASH_5717VENDOR_ST_A_M25PE20:
14487 case FLASH_5717VENDOR_ST_M_M45PE20:
14488 case FLASH_5717VENDOR_ST_A_M45PE20:
14489 case FLASH_5717VENDOR_ST_25USPT:
14490 case FLASH_5717VENDOR_ST_45USPT:
14491 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14492 tg3_flag_set(tp, NVRAM_BUFFERED);
14493 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14494
14495 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14496 case FLASH_5717VENDOR_ST_M_M25PE20:
a1b950d5 14497 case FLASH_5717VENDOR_ST_M_M45PE20:
66ee33bf
MC		 14498 /* Detect size with tg3_nvram_get_size() */
14499 break;
14500 case FLASH_5717VENDOR_ST_A_M25PE20:
a1b950d5
MC		 14501 case FLASH_5717VENDOR_ST_A_M45PE20:
14502 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14503 break;
14504 default:
14505 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14506 break;
14507 }
321d32a0 14508 break;
a1b950d5 14509 default:
63c3a66f 14510 tg3_flag_set(tp, NO_NVRAM);
a1b950d5 14511 return;
321d32a0 14512 }
a1b950d5
MC		 14513
14514 tg3_nvram_get_pagesize(tp, nvcfg1);
14515 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14516 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
321d32a0
MC		 14517}
14518
229b1ad1 14519static void tg3_get_5720_nvram_info(struct tg3 *tp)
9b91b5f1
MC		 14520{
14521 u32 nvcfg1, nvmpinstrp;
14522
14523 nvcfg1 = tr32(NVRAM_CFG1);
14524 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14525
4153577a 14526 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14527 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14528 tg3_flag_set(tp, NO_NVRAM);
14529 return;
14530 }
14531
14532 switch (nvmpinstrp) {
14533 case FLASH_5762_EEPROM_HD:
14534 nvmpinstrp = FLASH_5720_EEPROM_HD;
17e1a42f 14535 break;
c86a8560
MC		 14536 case FLASH_5762_EEPROM_LD:
14537 nvmpinstrp = FLASH_5720_EEPROM_LD;
17e1a42f 14538 break;
f6334bb8
MC		 14539 case FLASH_5720VENDOR_M_ST_M45PE20:
14540 /* This pinstrap supports multiple sizes, so force it
14541 * to read the actual size from location 0xf0.
14542 */
14543 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14544 break;
c86a8560
MC		 14545 }
14546 }
14547
9b91b5f1
MC		 14548 switch (nvmpinstrp) {
14549 case FLASH_5720_EEPROM_HD:
14550 case FLASH_5720_EEPROM_LD:
14551 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14552 tg3_flag_set(tp, NVRAM_BUFFERED);
9b91b5f1
MC		 14553
14554 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14555 tw32(NVRAM_CFG1, nvcfg1);
14556 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14557 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14558 else
14559 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14560 return;
14561 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14562 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14563 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14564 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14565 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14566 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14567 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14568 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14569 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14570 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14571 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14572 case FLASH_5720VENDOR_ATMEL_45USPT:
14573 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14574 tg3_flag_set(tp, NVRAM_BUFFERED);
14575 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14576
14577 switch (nvmpinstrp) {
14578 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14579 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14580 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14581 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14582 break;
14583 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14584 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14585 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14586 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14587 break;
14588 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14589 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14590 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14591 break;
14592 default:
4153577a 14593 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14594 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14595 break;
14596 }
14597 break;
14598 case FLASH_5720VENDOR_M_ST_M25PE10:
14599 case FLASH_5720VENDOR_M_ST_M45PE10:
14600 case FLASH_5720VENDOR_A_ST_M25PE10:
14601 case FLASH_5720VENDOR_A_ST_M45PE10:
14602 case FLASH_5720VENDOR_M_ST_M25PE20:
14603 case FLASH_5720VENDOR_M_ST_M45PE20:
14604 case FLASH_5720VENDOR_A_ST_M25PE20:
14605 case FLASH_5720VENDOR_A_ST_M45PE20:
14606 case FLASH_5720VENDOR_M_ST_M25PE40:
14607 case FLASH_5720VENDOR_M_ST_M45PE40:
14608 case FLASH_5720VENDOR_A_ST_M25PE40:
14609 case FLASH_5720VENDOR_A_ST_M45PE40:
14610 case FLASH_5720VENDOR_M_ST_M25PE80:
14611 case FLASH_5720VENDOR_M_ST_M45PE80:
14612 case FLASH_5720VENDOR_A_ST_M25PE80:
14613 case FLASH_5720VENDOR_A_ST_M45PE80:
14614 case FLASH_5720VENDOR_ST_25USPT:
14615 case FLASH_5720VENDOR_ST_45USPT:
14616 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14617 tg3_flag_set(tp, NVRAM_BUFFERED);
14618 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14619
14620 switch (nvmpinstrp) {
14621 case FLASH_5720VENDOR_M_ST_M25PE20:
14622 case FLASH_5720VENDOR_M_ST_M45PE20:
14623 case FLASH_5720VENDOR_A_ST_M25PE20:
14624 case FLASH_5720VENDOR_A_ST_M45PE20:
14625 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14626 break;
14627 case FLASH_5720VENDOR_M_ST_M25PE40:
14628 case FLASH_5720VENDOR_M_ST_M45PE40:
14629 case FLASH_5720VENDOR_A_ST_M25PE40:
14630 case FLASH_5720VENDOR_A_ST_M45PE40:
14631 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14632 break;
14633 case FLASH_5720VENDOR_M_ST_M25PE80:
14634 case FLASH_5720VENDOR_M_ST_M45PE80:
14635 case FLASH_5720VENDOR_A_ST_M25PE80:
14636 case FLASH_5720VENDOR_A_ST_M45PE80:
14637 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14638 break;
14639 default:
4153577a 14640 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14641 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14642 break;
14643 }
14644 break;
14645 default:
63c3a66f 14646 tg3_flag_set(tp, NO_NVRAM);
9b91b5f1
MC		 14647 return;
14648 }
14649
14650 tg3_nvram_get_pagesize(tp, nvcfg1);
14651 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14652 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
c86a8560 14653
4153577a 14654 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14655 u32 val;
14656
14657 if (tg3_nvram_read(tp, 0, &val))
14658 return;
14659
14660 if (val != TG3_EEPROM_MAGIC &&
14661 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14662 tg3_flag_set(tp, NO_NVRAM);
14663 }
9b91b5f1
MC		 14664}
14665
1da177e4 14666/* Chips other than 5700/5701 use the NVRAM for fetching info. */
229b1ad1 14667static void tg3_nvram_init(struct tg3 *tp)
1da177e4 14668{
7e6c63f0
HM		 14669 if (tg3_flag(tp, IS_SSB_CORE)) {
14670 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14671 tg3_flag_clear(tp, NVRAM);
14672 tg3_flag_clear(tp, NVRAM_BUFFERED);
14673 tg3_flag_set(tp, NO_NVRAM);
14674 return;
14675 }
14676
1da177e4
LT		 14677 tw32_f(GRC_EEPROM_ADDR,
14678 (EEPROM_ADDR_FSM_RESET |
14679 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14680 EEPROM_ADDR_CLKPERD_SHIFT)));
14681
9d57f01c 14682 msleep(1);
1da177e4
LT		 14683
14684 /* Enable seeprom accesses. */
14685 tw32_f(GRC_LOCAL_CTRL,
14686 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14687 udelay(100);
14688
4153577a
JP		 14689 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14690 tg3_asic_rev(tp) != ASIC_REV_5701) {
63c3a66f 14691 tg3_flag_set(tp, NVRAM);
1da177e4 14692
ec41c7df 14693 if (tg3_nvram_lock(tp)) {
5129c3a3
MC		 14694 netdev_warn(tp->dev,
14695 "Cannot get nvram lock, %s failed\n",
05dbe005 14696 __func__);
ec41c7df
MC		 14697 return;
14698 }
e6af301b 14699 tg3_enable_nvram_access(tp);
1da177e4 14700
989a9d23
MC		 14701 tp->nvram_size = 0;
14702
4153577a 14703 if (tg3_asic_rev(tp) == ASIC_REV_5752)
361b4ac2 14704 tg3_get_5752_nvram_info(tp);
4153577a 14705 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
d3c7b886 14706 tg3_get_5755_nvram_info(tp);
4153577a
JP		 14707 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14708 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14709 tg3_asic_rev(tp) == ASIC_REV_5785)
1b27777a 14710 tg3_get_5787_nvram_info(tp);
4153577a 14711 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
6b91fa02 14712 tg3_get_5761_nvram_info(tp);
4153577a 14713 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 14714 tg3_get_5906_nvram_info(tp);
4153577a 14715 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 14716 tg3_flag(tp, 57765_CLASS))
321d32a0 14717 tg3_get_57780_nvram_info(tp);
4153577a
JP		 14718 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14719 tg3_asic_rev(tp) == ASIC_REV_5719)
a1b950d5 14720 tg3_get_5717_nvram_info(tp);
4153577a
JP		 14721 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14722 tg3_asic_rev(tp) == ASIC_REV_5762)
9b91b5f1 14723 tg3_get_5720_nvram_info(tp);
361b4ac2
MC		 14724 else
14725 tg3_get_nvram_info(tp);
14726
989a9d23
MC		 14727 if (tp->nvram_size == 0)
14728 tg3_get_nvram_size(tp);
1da177e4 14729
e6af301b 14730 tg3_disable_nvram_access(tp);
381291b7 14731 tg3_nvram_unlock(tp);
1da177e4
LT		 14732
14733 } else {
63c3a66f
JP		 14734 tg3_flag_clear(tp, NVRAM);
14735 tg3_flag_clear(tp, NVRAM_BUFFERED);
1da177e4
LT		 14736
14737 tg3_get_eeprom_size(tp);
14738 }
14739}
14740
1da177e4
LT		 14741struct subsys_tbl_ent {
14742 u16 subsys_vendor, subsys_devid;
14743 u32 phy_id;
14744};
14745
229b1ad1 14746static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
1da177e4 14747 /* Broadcom boards. */
24daf2b0 14748 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14749 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 14750 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14751 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 14752 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14753 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 14754 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14755 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14756 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14757 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 14758 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14759 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14760 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14761 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14762 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14763 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 14764 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14765 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 14766 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14767 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 14768 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14769 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 14770
14771 /* 3com boards. */
24daf2b0 14772 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14773 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 14774 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14775 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14776 { TG3PCI_SUBVENDOR_ID_3COM,
14777 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
14778 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14779 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 14780 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14781 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14782
14783 /* DELL boards. */
24daf2b0 14784 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14785 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 14786 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14787 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 14788 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14789 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 14790 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14791 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 14792
14793 /* Compaq boards. */
24daf2b0 14794 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14795 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 14796 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14797 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14798 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14799 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
14800 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14801 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 14802 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14803 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14804
14805 /* IBM boards. */
24daf2b0
MC		 14806 { TG3PCI_SUBVENDOR_ID_IBM,
14807 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 14808};
14809
229b1ad1 14810static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 14811{
14812 int i;
14813
14814 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
14815 if ((subsys_id_to_phy_id[i].subsys_vendor ==
14816 tp->pdev->subsystem_vendor) &&
14817 (subsys_id_to_phy_id[i].subsys_devid ==
14818 tp->pdev->subsystem_device))
14819 return &subsys_id_to_phy_id[i];
14820 }
14821 return NULL;
14822}
14823
229b1ad1 14824static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 14825{
1da177e4 14826 u32 val;
f49639e6 14827
79eb6904 14828 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 14829 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14830
a85feb8c 14831 /* Assume an onboard device and WOL capable by default. */
63c3a66f
JP		 14832 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14833 tg3_flag_set(tp, WOL_CAP);
72b845e0 14834
4153577a 14835 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9d26e213 14836 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
63c3a66f
JP		 14837 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14838 tg3_flag_set(tp, IS_NIC);
9d26e213 14839 }
0527ba35
MC		 14840 val = tr32(VCPU_CFGSHDW);
14841 if (val & VCPU_CFGSHDW_ASPM_DBNC)
63c3a66f 14842 tg3_flag_set(tp, ASPM_WORKAROUND);
0527ba35 14843 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
6fdbab9d 14844 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
63c3a66f 14845 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 14846 device_set_wakeup_enable(&tp->pdev->dev, true);
14847 }
05ac4cb7 14848 goto done;
b5d3772c
MC		 14849 }
14850
1da177e4
LT		 14851 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
14852 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
14853 u32 nic_cfg, led_cfg;
a9daf367 14854 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 14855 int eeprom_phy_serdes = 0;
1da177e4
LT		 14856
14857 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
14858 tp->nic_sram_data_cfg = nic_cfg;
14859
14860 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
14861 ver >>= NIC_SRAM_DATA_VER_SHIFT;
4153577a
JP		 14862 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14863 tg3_asic_rev(tp) != ASIC_REV_5701 &&
14864 tg3_asic_rev(tp) != ASIC_REV_5703 &&
1da177e4
LT		 14865 (ver > 0) && (ver < 0x100))
14866 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
14867
4153577a 14868 if (tg3_asic_rev(tp) == ASIC_REV_5785)
a9daf367
MC		 14869 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
14870
1da177e4
LT		 14871 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
14872 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
14873 eeprom_phy_serdes = 1;
14874
14875 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
14876 if (nic_phy_id != 0) {
14877 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
14878 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
14879
14880 eeprom_phy_id = (id1 >> 16) << 10;
14881 eeprom_phy_id |= (id2 & 0xfc00) << 16;
14882 eeprom_phy_id |= (id2 & 0x03ff) << 0;
14883 } else
14884 eeprom_phy_id = 0;
14885
7d0c41ef 14886 tp->phy_id = eeprom_phy_id;
747e8f8b 14887 if (eeprom_phy_serdes) {
63c3a66f 14888 if (!tg3_flag(tp, 5705_PLUS))
f07e9af3 14889 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
a50d0796 14890 else
f07e9af3 14891 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
747e8f8b 14892 }
7d0c41ef 14893
63c3a66f 14894 if (tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 14895 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
14896 SHASTA_EXT_LED_MODE_MASK);
cbf46853 14897 else
1da177e4
LT		 14898 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
14899
14900 switch (led_cfg) {
14901 default:
14902 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
14903 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14904 break;
14905
14906 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
14907 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14908 break;
14909
14910 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
14911 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 14912
14913 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
14914 * read on some older 5700/5701 bootcode.
14915 */
4153577a
JP		 14916 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
14917 tg3_asic_rev(tp) == ASIC_REV_5701)
9ba27794
MC		 14918 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14919
1da177e4
LT		 14920 break;
14921
14922 case SHASTA_EXT_LED_SHARED:
14923 tp->led_ctrl = LED_CTRL_MODE_SHARED;
4153577a
JP		 14924 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
14925 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
1da177e4
LT		 14926 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14927 LED_CTRL_MODE_PHY_2);
89f67978
NS		 14928
14929 if (tg3_flag(tp, 5717_PLUS) ||
14930 tg3_asic_rev(tp) == ASIC_REV_5762)
14931 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
14932 LED_CTRL_BLINK_RATE_MASK;
14933
1da177e4
LT		 14934 break;
14935
14936 case SHASTA_EXT_LED_MAC:
14937 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
14938 break;
14939
14940 case SHASTA_EXT_LED_COMBO:
14941 tp->led_ctrl = LED_CTRL_MODE_COMBO;
4153577a 14942 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
1da177e4
LT		 14943 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14944 LED_CTRL_MODE_PHY_2);
14945 break;
14946
855e1111 14947 }
1da177e4 14948
4153577a
JP		 14949 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
14950 tg3_asic_rev(tp) == ASIC_REV_5701) &&
1da177e4
LT		 14951 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
14952 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14953
4153577a 14954 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
b2a5c19c 14955 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 14956
9d26e213 14957 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
63c3a66f 14958 tg3_flag_set(tp, EEPROM_WRITE_PROT);
9d26e213
MC		 14959 if ((tp->pdev->subsystem_vendor ==
14960 PCI_VENDOR_ID_ARIMA) &&
14961 (tp->pdev->subsystem_device == 0x205a ||
14962 tp->pdev->subsystem_device == 0x2063))
63c3a66f 14963 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
9d26e213 14964 } else {
63c3a66f
JP		 14965 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14966 tg3_flag_set(tp, IS_NIC);
9d26e213 14967 }
1da177e4
LT		 14968
14969 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f
JP		 14970 tg3_flag_set(tp, ENABLE_ASF);
14971 if (tg3_flag(tp, 5750_PLUS))
14972 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
1da177e4 14973 }
b2b98d4a
MC		 14974
14975 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
63c3a66f
JP		 14976 tg3_flag(tp, 5750_PLUS))
14977 tg3_flag_set(tp, ENABLE_APE);
b2b98d4a 14978
f07e9af3 14979 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
a85feb8c 14980 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
63c3a66f 14981 tg3_flag_clear(tp, WOL_CAP);
1da177e4 14982
63c3a66f 14983 if (tg3_flag(tp, WOL_CAP) &&
6fdbab9d 14984 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
63c3a66f 14985 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 14986 device_set_wakeup_enable(&tp->pdev->dev, true);
14987 }
0527ba35 14988
1da177e4 14989 if (cfg2 & (1 << 17))
f07e9af3 14990 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
1da177e4
LT		 14991
14992 /* serdes signal pre-emphasis in register 0x590 set by */
14993 /* bootcode if bit 18 is set */
14994 if (cfg2 & (1 << 18))
f07e9af3 14995 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
8ed5d97e 14996
63c3a66f 14997 if ((tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 14998 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
14999 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
6833c043 15000 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
f07e9af3 15001 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
6833c043 15002
942d1af0 15003 if (tg3_flag(tp, PCI_EXPRESS)) {
8ed5d97e
MC		 15004 u32 cfg3;
15005
15006 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
942d1af0
NS		 15007 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15008 !tg3_flag(tp, 57765_PLUS) &&
15009 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
63c3a66f 15010 tg3_flag_set(tp, ASPM_WORKAROUND);
942d1af0
NS		 15011 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15012 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15013 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15014 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
8ed5d97e 15015 }
a9daf367 15016
14417063 15017 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
63c3a66f 15018 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
a9daf367 15019 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
63c3a66f 15020 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
a9daf367 15021 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
63c3a66f 15022 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
1da177e4 15023 }
05ac4cb7 15024done:
63c3a66f 15025 if (tg3_flag(tp, WOL_CAP))
43067ed8 15026 device_set_wakeup_enable(&tp->pdev->dev,
63c3a66f 15027 tg3_flag(tp, WOL_ENABLE));
43067ed8
RW		 15028 else
15029 device_set_wakeup_capable(&tp->pdev->dev, false);
7d0c41ef
MC		 15030}
15031
c86a8560
MC		 15032static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15033{
15034 int i, err;
15035 u32 val2, off = offset * 8;
15036
15037 err = tg3_nvram_lock(tp);
15038 if (err)
15039 return err;
15040
15041 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15042 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15043 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15044 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15045 udelay(10);
15046
15047 for (i = 0; i < 100; i++) {
15048 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15049 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15050 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15051 break;
15052 }
15053 udelay(10);
15054 }
15055
15056 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15057
15058 tg3_nvram_unlock(tp);
15059 if (val2 & APE_OTP_STATUS_CMD_DONE)
15060 return 0;
15061
15062 return -EBUSY;
15063}
15064
229b1ad1 15065static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
b2a5c19c
MC		 15066{
15067 int i;
15068 u32 val;
15069
15070 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15071 tw32(OTP_CTRL, cmd);
15072
15073 /* Wait for up to 1 ms for command to execute. */
15074 for (i = 0; i < 100; i++) {
15075 val = tr32(OTP_STATUS);
15076 if (val & OTP_STATUS_CMD_DONE)
15077 break;
15078 udelay(10);
15079 }
15080
15081 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15082}
15083
15084/* Read the gphy configuration from the OTP region of the chip. The gphy
15085 * configuration is a 32-bit value that straddles the alignment boundary.
15086 * We do two 32-bit reads and then shift and merge the results.
15087 */
229b1ad1 15088static u32 tg3_read_otp_phycfg(struct tg3 *tp)
b2a5c19c
MC		 15089{
15090 u32 bhalf_otp, thalf_otp;
15091
15092 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15093
15094 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15095 return 0;
15096
15097 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15098
15099 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15100 return 0;
15101
15102 thalf_otp = tr32(OTP_READ_DATA);
15103
15104 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15105
15106 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15107 return 0;
15108
15109 bhalf_otp = tr32(OTP_READ_DATA);
15110
15111 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15112}
15113
229b1ad1 15114static void tg3_phy_init_link_config(struct tg3 *tp)
e256f8a3 15115{
202ff1c2 15116 u32 adv = ADVERTISED_Autoneg;
e256f8a3
MC		 15117
15118 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15119 adv |= ADVERTISED_1000baseT_Half |
15120 ADVERTISED_1000baseT_Full;
15121
15122 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15123 adv |= ADVERTISED_100baseT_Half |
15124 ADVERTISED_100baseT_Full |
15125 ADVERTISED_10baseT_Half |
15126 ADVERTISED_10baseT_Full |
15127 ADVERTISED_TP;
15128 else
15129 adv |= ADVERTISED_FIBRE;
15130
15131 tp->link_config.advertising = adv;
e740522e
MC		 15132 tp->link_config.speed = SPEED_UNKNOWN;
15133 tp->link_config.duplex = DUPLEX_UNKNOWN;
e256f8a3 15134 tp->link_config.autoneg = AUTONEG_ENABLE;
e740522e
MC		 15135 tp->link_config.active_speed = SPEED_UNKNOWN;
15136 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
34655ad6
MC		 15137
15138 tp->old_link = -1;
e256f8a3
MC		 15139}
15140
229b1ad1 15141static int tg3_phy_probe(struct tg3 *tp)
7d0c41ef
MC		 15142{
15143 u32 hw_phy_id_1, hw_phy_id_2;
15144 u32 hw_phy_id, hw_phy_id_masked;
15145 int err;
1da177e4 15146
e256f8a3 15147 /* flow control autonegotiation is default behavior */
63c3a66f 15148 tg3_flag_set(tp, PAUSE_AUTONEG);
e256f8a3
MC		 15149 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15150
8151ad57
MC		 15151 if (tg3_flag(tp, ENABLE_APE)) {
15152 switch (tp->pci_fn) {
15153 case 0:
15154 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15155 break;
15156 case 1:
15157 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15158 break;
15159 case 2:
15160 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15161 break;
15162 case 3:
15163 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15164 break;
15165 }
15166 }
15167
942d1af0
NS		 15168 if (!tg3_flag(tp, ENABLE_ASF) &&
15169 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15170 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15171 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15172 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15173
63c3a66f 15174 if (tg3_flag(tp, USE_PHYLIB))
b02fd9e3
MC		 15175 return tg3_phy_init(tp);
15176
1da177e4 15177 /* Reading the PHY ID register can conflict with ASF
877d0310 15178 * firmware access to the PHY hardware.
1da177e4
LT		 15179 */
15180 err = 0;
63c3a66f 15181 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
79eb6904 15182 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 15183 } else {
15184 /* Now read the physical PHY_ID from the chip and verify
15185 * that it is sane. If it doesn't look good, we fall back
15186 * to either the hard-coded table based PHY_ID and failing
15187 * that the value found in the eeprom area.
15188 */
15189 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15190 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15191
15192 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15193 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15194 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15195
79eb6904 15196 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 15197 }
15198
79eb6904 15199 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 15200 tp->phy_id = hw_phy_id;
79eb6904 15201 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
f07e9af3 15202 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
da6b2d01 15203 else
f07e9af3 15204 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
1da177e4 15205 } else {
79eb6904 15206 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 15207 /* Do nothing, phy ID already set up in
15208 * tg3_get_eeprom_hw_cfg().
15209 */
1da177e4
LT		 15210 } else {
15211 struct subsys_tbl_ent *p;
15212
15213 /* No eeprom signature? Try the hardcoded
15214 * subsys device table.
15215 */
24daf2b0 15216 p = tg3_lookup_by_subsys(tp);
7e6c63f0
HM		 15217 if (p) {
15218 tp->phy_id = p->phy_id;
15219 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15220 /* For now we saw the IDs 0xbc050cd0,
15221 * 0xbc050f80 and 0xbc050c30 on devices
15222 * connected to an BCM4785 and there are
15223 * probably more. Just assume that the phy is
15224 * supported when it is connected to a SSB core
15225 * for now.
15226 */
1da177e4 15227 return -ENODEV;
7e6c63f0 15228 }
1da177e4 15229
1da177e4 15230 if (!tp->phy_id ||
79eb6904 15231 tp->phy_id == TG3_PHY_ID_BCM8002)
f07e9af3 15232 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
1da177e4
LT		 15233 }
15234 }
15235
a6b68dab 15236 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
4153577a
JP		 15237 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15238 tg3_asic_rev(tp) == ASIC_REV_5720 ||
c4dab506 15239 tg3_asic_rev(tp) == ASIC_REV_57766 ||
4153577a
JP		 15240 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15241 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15242 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15243 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
9e2ecbeb 15244 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
52b02d04
MC		 15245 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15246
9e2ecbeb
NS		 15247 tp->eee.supported = SUPPORTED_100baseT_Full |
15248 SUPPORTED_1000baseT_Full;
15249 tp->eee.advertised = ADVERTISED_100baseT_Full |
15250 ADVERTISED_1000baseT_Full;
15251 tp->eee.eee_enabled = 1;
15252 tp->eee.tx_lpi_enabled = 1;
15253 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15254 }
15255
e256f8a3
MC		 15256 tg3_phy_init_link_config(tp);
15257
942d1af0
NS		 15258 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15259 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
63c3a66f
JP		 15260 !tg3_flag(tp, ENABLE_APE) &&
15261 !tg3_flag(tp, ENABLE_ASF)) {
e2bf73e7 15262 u32 bmsr, dummy;
1da177e4
LT		 15263
15264 tg3_readphy(tp, MII_BMSR, &bmsr);
15265 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15266 (bmsr & BMSR_LSTATUS))
15267 goto skip_phy_reset;
6aa20a22 15268
1da177e4
LT		 15269 err = tg3_phy_reset(tp);
15270 if (err)
15271 return err;
15272
42b64a45 15273 tg3_phy_set_wirespeed(tp);
1da177e4 15274
e2bf73e7 15275 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
42b64a45
MC		 15276 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15277 tp->link_config.flowctrl);
1da177e4
LT		 15278
15279 tg3_writephy(tp, MII_BMCR,
15280 BMCR_ANENABLE | BMCR_ANRESTART);
15281 }
1da177e4
LT		 15282 }
15283
15284skip_phy_reset:
79eb6904 15285 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 15286 err = tg3_init_5401phy_dsp(tp);
15287 if (err)
15288 return err;
1da177e4 15289
1da177e4
LT		 15290 err = tg3_init_5401phy_dsp(tp);
15291 }
15292
1da177e4
LT		 15293 return err;
15294}
15295
229b1ad1 15296static void tg3_read_vpd(struct tg3 *tp)
1da177e4 15297{
a4a8bb15 15298 u8 *vpd_data;
4181b2c8 15299 unsigned int block_end, rosize, len;
535a490e 15300 u32 vpdlen;
184b8904 15301 int j, i = 0;
a4a8bb15 15302
535a490e 15303 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
a4a8bb15
MC		 15304 if (!vpd_data)
15305 goto out_no_vpd;
1da177e4 15306
535a490e 15307 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
4181b2c8
MC		 15308 if (i < 0)
15309 goto out_not_found;
1da177e4 15310
4181b2c8
MC		 15311 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15312 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15313 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 15314
535a490e 15315 if (block_end > vpdlen)
4181b2c8 15316 goto out_not_found;
af2c6a4a 15317
184b8904
MC		 15318 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15319 PCI_VPD_RO_KEYWORD_MFR_ID);
15320 if (j > 0) {
15321 len = pci_vpd_info_field_size(&vpd_data[j]);
15322
15323 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15324 if (j + len > block_end || len != 4 ||
15325 memcmp(&vpd_data[j], "1028", 4))
15326 goto partno;
15327
15328 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15329 PCI_VPD_RO_KEYWORD_VENDOR0);
15330 if (j < 0)
15331 goto partno;
15332
15333 len = pci_vpd_info_field_size(&vpd_data[j]);
15334
15335 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15336 if (j + len > block_end)
15337 goto partno;
15338
715230a4
KC		 15339 if (len >= sizeof(tp->fw_ver))
15340 len = sizeof(tp->fw_ver) - 1;
15341 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15342 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15343 &vpd_data[j]);
184b8904
MC		 15344 }
15345
15346partno:
4181b2c8
MC		 15347 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15348 PCI_VPD_RO_KEYWORD_PARTNO);
15349 if (i < 0)
15350 goto out_not_found;
af2c6a4a 15351
4181b2c8 15352 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 15353
4181b2c8
MC		 15354 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15355 if (len > TG3_BPN_SIZE ||
535a490e 15356 (len + i) > vpdlen)
4181b2c8 15357 goto out_not_found;
1da177e4 15358
4181b2c8 15359 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 15360
1da177e4 15361out_not_found:
a4a8bb15 15362 kfree(vpd_data);
37a949c5 15363 if (tp->board_part_number[0])
a4a8bb15
MC		 15364 return;
15365
15366out_no_vpd:
4153577a 15367 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
79d49695
MC		 15368 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15369 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
37a949c5
MC		 15370 strcpy(tp->board_part_number, "BCM5717");
15371 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15372 strcpy(tp->board_part_number, "BCM5718");
15373 else
15374 goto nomatch;
4153577a 15375 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
37a949c5
MC		 15376 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15377 strcpy(tp->board_part_number, "BCM57780");
15378 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15379 strcpy(tp->board_part_number, "BCM57760");
15380 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15381 strcpy(tp->board_part_number, "BCM57790");
15382 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15383 strcpy(tp->board_part_number, "BCM57788");
15384 else
15385 goto nomatch;
4153577a 15386 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
37a949c5
MC		 15387 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15388 strcpy(tp->board_part_number, "BCM57761");
15389 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15390 strcpy(tp->board_part_number, "BCM57765");
15391 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15392 strcpy(tp->board_part_number, "BCM57781");
15393 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15394 strcpy(tp->board_part_number, "BCM57785");
15395 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15396 strcpy(tp->board_part_number, "BCM57791");
15397 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15398 strcpy(tp->board_part_number, "BCM57795");
15399 else
15400 goto nomatch;
4153577a 15401 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
55086ad9
MC		 15402 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15403 strcpy(tp->board_part_number, "BCM57762");
15404 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15405 strcpy(tp->board_part_number, "BCM57766");
15406 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15407 strcpy(tp->board_part_number, "BCM57782");
15408 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15409 strcpy(tp->board_part_number, "BCM57786");
15410 else
15411 goto nomatch;
4153577a 15412 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c 15413 strcpy(tp->board_part_number, "BCM95906");
37a949c5
MC		 15414 } else {
15415nomatch:
b5d3772c 15416 strcpy(tp->board_part_number, "none");
37a949c5 15417 }
1da177e4
LT		 15418}
15419
229b1ad1 15420static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
9c8a620e
MC		 15421{
15422 u32 val;
15423
e4f34110 15424 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 15425 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 15426 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 15427 val != 0)
15428 return 0;
15429
15430 return 1;
15431}
15432
229b1ad1 15433static void tg3_read_bc_ver(struct tg3 *tp)
acd9c119 15434{
ff3a7cb2 15435 u32 val, offset, start, ver_offset;
75f9936e 15436 int i, dst_off;
ff3a7cb2 15437 bool newver = false;
acd9c119
MC		 15438
15439 if (tg3_nvram_read(tp, 0xc, &offset) ||
15440 tg3_nvram_read(tp, 0x4, &start))
15441 return;
15442
15443 offset = tg3_nvram_logical_addr(tp, offset);
15444
ff3a7cb2 15445 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 15446 return;
15447
ff3a7cb2
MC		 15448 if ((val & 0xfc000000) == 0x0c000000) {
15449 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 15450 return;
15451
ff3a7cb2
MC		 15452 if (val == 0)
15453 newver = true;
15454 }
15455
75f9936e
MC		 15456 dst_off = strlen(tp->fw_ver);
15457
ff3a7cb2 15458 if (newver) {
75f9936e
MC		 15459 if (TG3_VER_SIZE - dst_off < 16 ||
15460 tg3_nvram_read(tp, offset + 8, &ver_offset))
ff3a7cb2
MC		 15461 return;
15462
15463 offset = offset + ver_offset - start;
15464 for (i = 0; i < 16; i += 4) {
15465 __be32 v;
15466 if (tg3_nvram_read_be32(tp, offset + i, &v))
15467 return;
15468
75f9936e 15469 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
ff3a7cb2
MC		 15470 }
15471 } else {
15472 u32 major, minor;
15473
15474 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15475 return;
15476
15477 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15478 TG3_NVM_BCVER_MAJSFT;
15479 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
75f9936e
MC		 15480 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15481 "v%d.%02d", major, minor);
acd9c119
MC		 15482 }
15483}
15484
229b1ad1 15485static void tg3_read_hwsb_ver(struct tg3 *tp)
a6f6cb1c
MC		 15486{
15487 u32 val, major, minor;
15488
15489 /* Use native endian representation */
15490 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15491 return;
15492
15493 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15494 TG3_NVM_HWSB_CFG1_MAJSFT;
15495 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15496 TG3_NVM_HWSB_CFG1_MINSFT;
15497
15498 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15499}
15500
229b1ad1 15501static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
dfe00d7d
MC		 15502{
15503 u32 offset, major, minor, build;
15504
75f9936e 15505 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
dfe00d7d
MC		 15506
15507 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15508 return;
15509
15510 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15511 case TG3_EEPROM_SB_REVISION_0:
15512 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15513 break;
15514 case TG3_EEPROM_SB_REVISION_2:
15515 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15516 break;
15517 case TG3_EEPROM_SB_REVISION_3:
15518 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15519 break;
a4153d40
MC		 15520 case TG3_EEPROM_SB_REVISION_4:
15521 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15522 break;
15523 case TG3_EEPROM_SB_REVISION_5:
15524 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15525 break;
bba226ac
MC		 15526 case TG3_EEPROM_SB_REVISION_6:
15527 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15528 break;
dfe00d7d
MC		 15529 default:
15530 return;
15531 }
15532
e4f34110 15533 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 15534 return;
15535
15536 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15537 TG3_EEPROM_SB_EDH_BLD_SHFT;
15538 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15539 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15540 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15541
15542 if (minor > 99 || build > 26)
15543 return;
15544
75f9936e
MC		 15545 offset = strlen(tp->fw_ver);
15546 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15547 " v%d.%02d", major, minor);
dfe00d7d
MC		 15548
15549 if (build > 0) {
75f9936e
MC		 15550 offset = strlen(tp->fw_ver);
15551 if (offset < TG3_VER_SIZE - 1)
15552 tp->fw_ver[offset] = 'a' + build - 1;
dfe00d7d
MC		 15553 }
15554}
15555
229b1ad1 15556static void tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 15557{
15558 u32 val, offset, start;
acd9c119 15559 int i, vlen;
9c8a620e
MC		 15560
15561 for (offset = TG3_NVM_DIR_START;
15562 offset < TG3_NVM_DIR_END;
15563 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 15564 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 15565 return;
15566
9c8a620e
MC		 15567 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15568 break;
15569 }
15570
15571 if (offset == TG3_NVM_DIR_END)
15572 return;
15573
63c3a66f 15574 if (!tg3_flag(tp, 5705_PLUS))
9c8a620e 15575 start = 0x08000000;
e4f34110 15576 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 15577 return;
15578
e4f34110 15579 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 15580 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 15581 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 15582 return;
15583
15584 offset += val - start;
15585
acd9c119 15586 vlen = strlen(tp->fw_ver);
9c8a620e 15587
acd9c119
MC		 15588 tp->fw_ver[vlen++] = ',';
15589 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 15590
15591 for (i = 0; i < 4; i++) {
a9dc529d
MC		 15592 __be32 v;
15593 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 15594 return;
15595
b9fc7dc5 15596 offset += sizeof(v);
c4e6575c 15597
acd9c119
MC		 15598 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15599 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 15600 break;
c4e6575c 15601 }
9c8a620e 15602
acd9c119
MC		 15603 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15604 vlen += sizeof(v);
c4e6575c 15605 }
acd9c119
MC		 15606}
15607
229b1ad1 15608static void tg3_probe_ncsi(struct tg3 *tp)
7fd76445 15609{
7fd76445 15610 u32 apedata;
7fd76445
MC		 15611
15612 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15613 if (apedata != APE_SEG_SIG_MAGIC)
15614 return;
15615
15616 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15617 if (!(apedata & APE_FW_STATUS_READY))
15618 return;
15619
165f4d1c
MC		 15620 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15621 tg3_flag_set(tp, APE_HAS_NCSI);
15622}
15623
229b1ad1 15624static void tg3_read_dash_ver(struct tg3 *tp)
165f4d1c
MC		 15625{
15626 int vlen;
15627 u32 apedata;
15628 char *fwtype;
15629
7fd76445
MC		 15630 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15631
165f4d1c 15632 if (tg3_flag(tp, APE_HAS_NCSI))
ecc79648 15633 fwtype = "NCSI";
c86a8560
MC		 15634 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15635 fwtype = "SMASH";
165f4d1c 15636 else
ecc79648
MC		 15637 fwtype = "DASH";
15638
7fd76445
MC		 15639 vlen = strlen(tp->fw_ver);
15640
ecc79648
MC		 15641 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15642 fwtype,
7fd76445
MC		 15643 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15644 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15645 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15646 (apedata & APE_FW_VERSION_BLDMSK));
15647}
15648
c86a8560
MC		 15649static void tg3_read_otp_ver(struct tg3 *tp)
15650{
15651 u32 val, val2;
15652
4153577a 15653 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c86a8560
MC		 15654 return;
15655
15656 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15657 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15658 TG3_OTP_MAGIC0_VALID(val)) {
15659 u64 val64 = (u64) val << 32 | val2;
15660 u32 ver = 0;
15661 int i, vlen;
15662
15663 for (i = 0; i < 7; i++) {
15664 if ((val64 & 0xff) == 0)
15665 break;
15666 ver = val64 & 0xff;
15667 val64 >>= 8;
15668 }
15669 vlen = strlen(tp->fw_ver);
15670 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15671 }
15672}
15673
229b1ad1 15674static void tg3_read_fw_ver(struct tg3 *tp)
acd9c119
MC		 15675{
15676 u32 val;
75f9936e 15677 bool vpd_vers = false;
acd9c119 15678
75f9936e
MC		 15679 if (tp->fw_ver[0] != 0)
15680 vpd_vers = true;
df259d8c 15681
63c3a66f 15682 if (tg3_flag(tp, NO_NVRAM)) {
75f9936e 15683 strcat(tp->fw_ver, "sb");
c86a8560 15684 tg3_read_otp_ver(tp);
df259d8c
MC		 15685 return;
15686 }
15687
acd9c119
MC		 15688 if (tg3_nvram_read(tp, 0, &val))
15689 return;
15690
15691 if (val == TG3_EEPROM_MAGIC)
15692 tg3_read_bc_ver(tp);
15693 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15694 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 15695 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15696 tg3_read_hwsb_ver(tp);
acd9c119 15697
165f4d1c
MC		 15698 if (tg3_flag(tp, ENABLE_ASF)) {
15699 if (tg3_flag(tp, ENABLE_APE)) {
15700 tg3_probe_ncsi(tp);
15701 if (!vpd_vers)
15702 tg3_read_dash_ver(tp);
15703 } else if (!vpd_vers) {
15704 tg3_read_mgmtfw_ver(tp);
15705 }
c9cab24e 15706 }
9c8a620e
MC		 15707
15708 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 15709}
15710
7cb32cf2
MC		 15711static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15712{
63c3a66f 15713 if (tg3_flag(tp, LRG_PROD_RING_CAP))
de9f5230 15714 return TG3_RX_RET_MAX_SIZE_5717;
63c3a66f 15715 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
de9f5230 15716 return TG3_RX_RET_MAX_SIZE_5700;
7cb32cf2 15717 else
de9f5230 15718 return TG3_RX_RET_MAX_SIZE_5705;
7cb32cf2
MC		 15719}
15720
4143470c 15721static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
895950c2
JP		 15722 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15723 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15724 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15725 { },
15726};
15727
229b1ad1 15728static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16c7fa7d
MC		 15729{
15730 struct pci_dev *peer;
15731 unsigned int func, devnr = tp->pdev->devfn & ~7;
15732
15733 for (func = 0; func < 8; func++) {
15734 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15735 if (peer && peer != tp->pdev)
15736 break;
15737 pci_dev_put(peer);
15738 }
15739 /* 5704 can be configured in single-port mode, set peer to
15740 * tp->pdev in that case.
15741 */
15742 if (!peer) {
15743 peer = tp->pdev;
15744 return peer;
15745 }
15746
15747 /*
15748 * We don't need to keep the refcount elevated; there's no way
15749 * to remove one half of this device without removing the other
15750 */
15751 pci_dev_put(peer);
15752
15753 return peer;
15754}
15755
229b1ad1 15756static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
42b123b1
MC		 15757{
15758 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
4153577a 15759 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
42b123b1
MC		 15760 u32 reg;
15761
15762 /* All devices that use the alternate
15763 * ASIC REV location have a CPMU.
15764 */
15765 tg3_flag_set(tp, CPMU_PRESENT);
15766
15767 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 15768 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
42b123b1
MC		 15769 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15770 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 15771 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 15772 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
15773 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 15774 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
15775 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 15776 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
15777 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
42b123b1
MC		 15778 reg = TG3PCI_GEN2_PRODID_ASICREV;
15779 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
15780 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
15781 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
15782 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
15783 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15784 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
15785 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
15786 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
15787 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
15788 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15789 reg = TG3PCI_GEN15_PRODID_ASICREV;
15790 else
15791 reg = TG3PCI_PRODID_ASICREV;
15792
15793 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
15794 }
15795
15796 /* Wrong chip ID in 5752 A0. This code can be removed later
15797 * as A0 is not in production.
15798 */
4153577a 15799 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
42b123b1
MC		 15800 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
15801
4153577a 15802 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
79d49695
MC		 15803 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
15804
4153577a
JP		 15805 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15806 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15807 tg3_asic_rev(tp) == ASIC_REV_5720)
42b123b1
MC		 15808 tg3_flag_set(tp, 5717_PLUS);
15809
4153577a
JP		 15810 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
15811 tg3_asic_rev(tp) == ASIC_REV_57766)
42b123b1
MC		 15812 tg3_flag_set(tp, 57765_CLASS);
15813
c65a17f4 15814 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
4153577a 15815 tg3_asic_rev(tp) == ASIC_REV_5762)
42b123b1
MC		 15816 tg3_flag_set(tp, 57765_PLUS);
15817
15818 /* Intentionally exclude ASIC_REV_5906 */
4153577a
JP		 15819 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
15820 tg3_asic_rev(tp) == ASIC_REV_5787 ||
15821 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15822 tg3_asic_rev(tp) == ASIC_REV_5761 ||
15823 tg3_asic_rev(tp) == ASIC_REV_5785 ||
15824 tg3_asic_rev(tp) == ASIC_REV_57780 ||
42b123b1
MC		 15825 tg3_flag(tp, 57765_PLUS))
15826 tg3_flag_set(tp, 5755_PLUS);
15827
4153577a
JP		 15828 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
15829 tg3_asic_rev(tp) == ASIC_REV_5714)
42b123b1
MC		 15830 tg3_flag_set(tp, 5780_CLASS);
15831
4153577a
JP		 15832 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
15833 tg3_asic_rev(tp) == ASIC_REV_5752 ||
15834 tg3_asic_rev(tp) == ASIC_REV_5906 ||
42b123b1
MC		 15835 tg3_flag(tp, 5755_PLUS) ||
15836 tg3_flag(tp, 5780_CLASS))
15837 tg3_flag_set(tp, 5750_PLUS);
15838
4153577a 15839 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
42b123b1
MC		 15840 tg3_flag(tp, 5750_PLUS))
15841 tg3_flag_set(tp, 5705_PLUS);
15842}
15843
3d567e0e
NNS		 15844static bool tg3_10_100_only_device(struct tg3 *tp,
15845 const struct pci_device_id *ent)
15846{
15847 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
15848
4153577a
JP		 15849 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
15850 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
3d567e0e
NNS		 15851 (tp->phy_flags & TG3_PHYFLG_IS_FET))
15852 return true;
15853
15854 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
4153577a 15855 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3d567e0e
NNS		 15856 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
15857 return true;
15858 } else {
15859 return true;
15860 }
15861 }
15862
15863 return false;
15864}
15865
1dd06ae8 15866static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
1da177e4 15867{
1da177e4 15868 u32 misc_ctrl_reg;
1da177e4
LT		 15869 u32 pci_state_reg, grc_misc_cfg;
15870 u32 val;
15871 u16 pci_cmd;
5e7dfd0f 15872 int err;
1da177e4 15873
1da177e4
LT		 15874 /* Force memory write invalidate off. If we leave it on,
15875 * then on 5700_BX chips we have to enable a workaround.
15876 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
15877 * to match the cacheline size. The Broadcom driver have this
15878 * workaround but turns MWI off all the times so never uses
15879 * it. This seems to suggest that the workaround is insufficient.
15880 */
15881 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
15882 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
15883 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
15884
16821285
MC		 15885 /* Important! -- Make sure register accesses are byteswapped
15886 * correctly. Also, for those chips that require it, make
15887 * sure that indirect register accesses are enabled before
15888 * the first operation.
1da177e4
LT		 15889 */
15890 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15891 &misc_ctrl_reg);
16821285
MC		 15892 tp->misc_host_ctrl |= (misc_ctrl_reg &
15893 MISC_HOST_CTRL_CHIPREV);
15894 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15895 tp->misc_host_ctrl);
1da177e4 15896
42b123b1 15897 tg3_detect_asic_rev(tp, misc_ctrl_reg);
ff645bec 15898
6892914f
MC		 15899 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
15900 * we need to disable memory and use config. cycles
15901 * only to access all registers. The 5702/03 chips
15902 * can mistakenly decode the special cycles from the
15903 * ICH chipsets as memory write cycles, causing corruption
15904 * of register and memory space. Only certain ICH bridges
15905 * will drive special cycles with non-zero data during the
15906 * address phase which can fall within the 5703's address
15907 * range. This is not an ICH bug as the PCI spec allows
15908 * non-zero address during special cycles. However, only
15909 * these ICH bridges are known to drive non-zero addresses
15910 * during special cycles.
15911 *
15912 * Since special cycles do not cross PCI bridges, we only
15913 * enable this workaround if the 5703 is on the secondary
15914 * bus of these ICH bridges.
15915 */
4153577a
JP		 15916 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
15917 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
6892914f
MC		 15918 static struct tg3_dev_id {
15919 u32 vendor;
15920 u32 device;
15921 u32 rev;
15922 } ich_chipsets[] = {
15923 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
15924 PCI_ANY_ID },
15925 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
15926 PCI_ANY_ID },
15927 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
15928 0xa },
15929 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
15930 PCI_ANY_ID },
15931 { },
15932 };
15933 struct tg3_dev_id *pci_id = &ich_chipsets[0];
15934 struct pci_dev *bridge = NULL;
15935
15936 while (pci_id->vendor != 0) {
15937 bridge = pci_get_device(pci_id->vendor, pci_id->device,
15938 bridge);
15939 if (!bridge) {
15940 pci_id++;
15941 continue;
15942 }
15943 if (pci_id->rev != PCI_ANY_ID) {
44c10138 15944 if (bridge->revision > pci_id->rev)
6892914f
MC		 15945 continue;
15946 }
15947 if (bridge->subordinate &&
15948 (bridge->subordinate->number ==
15949 tp->pdev->bus->number)) {
63c3a66f 15950 tg3_flag_set(tp, ICH_WORKAROUND);
6892914f
MC		 15951 pci_dev_put(bridge);
15952 break;
15953 }
15954 }
15955 }
15956
4153577a 15957 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
41588ba1
MC		 15958 static struct tg3_dev_id {
15959 u32 vendor;
15960 u32 device;
15961 } bridge_chipsets[] = {
15962 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
15963 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
15964 { },
15965 };
15966 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
15967 struct pci_dev *bridge = NULL;
15968
15969 while (pci_id->vendor != 0) {
15970 bridge = pci_get_device(pci_id->vendor,
15971 pci_id->device,
15972 bridge);
15973 if (!bridge) {
15974 pci_id++;
15975 continue;
15976 }
15977 if (bridge->subordinate &&
15978 (bridge->subordinate->number <=
15979 tp->pdev->bus->number) &&
b918c62e 15980 (bridge->subordinate->busn_res.end >=
41588ba1 15981 tp->pdev->bus->number)) {
63c3a66f 15982 tg3_flag_set(tp, 5701_DMA_BUG);
41588ba1
MC		 15983 pci_dev_put(bridge);
15984 break;
15985 }
15986 }
15987 }
15988
4a29cc2e
MC		 15989 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
15990 * DMA addresses > 40-bit. This bridge may have other additional
15991 * 57xx devices behind it in some 4-port NIC designs for example.
15992 * Any tg3 device found behind the bridge will also need the 40-bit
15993 * DMA workaround.
15994 */
42b123b1 15995 if (tg3_flag(tp, 5780_CLASS)) {
63c3a66f 15996 tg3_flag_set(tp, 40BIT_DMA_BUG);
0f847584 15997 tp->msi_cap = tp->pdev->msi_cap;
859a5887 15998 } else {
4a29cc2e
MC		 15999 struct pci_dev *bridge = NULL;
16000
16001 do {
16002 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16003 PCI_DEVICE_ID_SERVERWORKS_EPB,
16004 bridge);
16005 if (bridge && bridge->subordinate &&
16006 (bridge->subordinate->number <=
16007 tp->pdev->bus->number) &&
b918c62e 16008 (bridge->subordinate->busn_res.end >=
4a29cc2e 16009 tp->pdev->bus->number)) {
63c3a66f 16010 tg3_flag_set(tp, 40BIT_DMA_BUG);
4a29cc2e
MC		 16011 pci_dev_put(bridge);
16012 break;
16013 }
16014 } while (bridge);
16015 }
4cf78e4f 16016
4153577a
JP		 16017 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16018 tg3_asic_rev(tp) == ASIC_REV_5714)
7544b097
MC		 16019 tp->pdev_peer = tg3_find_peer(tp);
16020
507399f1 16021 /* Determine TSO capabilities */
4153577a 16022 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
4d163b75 16023 ; /* Do nothing. HW bug. */
63c3a66f
JP		 16024 else if (tg3_flag(tp, 57765_PLUS))
16025 tg3_flag_set(tp, HW_TSO_3);
16026 else if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16027 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f
JP		 16028 tg3_flag_set(tp, HW_TSO_2);
16029 else if (tg3_flag(tp, 5750_PLUS)) {
16030 tg3_flag_set(tp, HW_TSO_1);
16031 tg3_flag_set(tp, TSO_BUG);
4153577a
JP		 16032 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16033 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
63c3a66f 16034 tg3_flag_clear(tp, TSO_BUG);
4153577a
JP		 16035 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16036 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16037 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
1caf13eb
MC		 16038 tg3_flag_set(tp, FW_TSO);
16039 tg3_flag_set(tp, TSO_BUG);
4153577a 16040 if (tg3_asic_rev(tp) == ASIC_REV_5705)
507399f1
MC		 16041 tp->fw_needed = FIRMWARE_TG3TSO5;
16042 else
16043 tp->fw_needed = FIRMWARE_TG3TSO;
16044 }
16045
dabc5c67 16046 /* Selectively allow TSO based on operating conditions */
6ff6f81d
MC		 16047 if (tg3_flag(tp, HW_TSO_1) ||
16048 tg3_flag(tp, HW_TSO_2) ||
16049 tg3_flag(tp, HW_TSO_3) ||
1caf13eb 16050 tg3_flag(tp, FW_TSO)) {
cf9ecf4b
MC		 16051 /* For firmware TSO, assume ASF is disabled.
16052 * We'll disable TSO later if we discover ASF
16053 * is enabled in tg3_get_eeprom_hw_cfg().
16054 */
dabc5c67 16055 tg3_flag_set(tp, TSO_CAPABLE);
cf9ecf4b 16056 } else {
dabc5c67
MC		 16057 tg3_flag_clear(tp, TSO_CAPABLE);
16058 tg3_flag_clear(tp, TSO_BUG);
16059 tp->fw_needed = NULL;
16060 }
16061
4153577a 16062 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
dabc5c67
MC		 16063 tp->fw_needed = FIRMWARE_TG3;
16064
c4dab506
NS		 16065 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16066 tp->fw_needed = FIRMWARE_TG357766;
16067
507399f1
MC		 16068 tp->irq_max = 1;
16069
63c3a66f
JP		 16070 if (tg3_flag(tp, 5750_PLUS)) {
16071 tg3_flag_set(tp, SUPPORT_MSI);
4153577a
JP		 16072 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16073 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16074 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16075 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
7544b097 16076 tp->pdev_peer == tp->pdev))
63c3a66f 16077 tg3_flag_clear(tp, SUPPORT_MSI);
7544b097 16078
63c3a66f 16079 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16080 tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16081 tg3_flag_set(tp, 1SHOT_MSI);
52c0fd83 16082 }
4f125f42 16083
63c3a66f
JP		 16084 if (tg3_flag(tp, 57765_PLUS)) {
16085 tg3_flag_set(tp, SUPPORT_MSIX);
507399f1
MC		 16086 tp->irq_max = TG3_IRQ_MAX_VECS;
16087 }
f6eb9b1f 16088 }
0e1406dd 16089
9102426a
MC		 16090 tp->txq_max = 1;
16091 tp->rxq_max = 1;
16092 if (tp->irq_max > 1) {
16093 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16094 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16095
4153577a
JP		 16096 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16097 tg3_asic_rev(tp) == ASIC_REV_5720)
9102426a
MC		 16098 tp->txq_max = tp->irq_max - 1;
16099 }
16100
b7abee6e 16101 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16102 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f 16103 tg3_flag_set(tp, SHORT_DMA_BUG);
f6eb9b1f 16104
4153577a 16105 if (tg3_asic_rev(tp) == ASIC_REV_5719)
a4cb428d 16106 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
e31aa987 16107
4153577a
JP		 16108 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16109 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16110 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16111 tg3_asic_rev(tp) == ASIC_REV_5762)
63c3a66f 16112 tg3_flag_set(tp, LRG_PROD_RING_CAP);
de9f5230 16113
63c3a66f 16114 if (tg3_flag(tp, 57765_PLUS) &&
4153577a 16115 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
63c3a66f 16116 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
b703df6f 16117
63c3a66f
JP		 16118 if (!tg3_flag(tp, 5705_PLUS) ||
16119 tg3_flag(tp, 5780_CLASS) ||
16120 tg3_flag(tp, USE_JUMBO_BDFLAG))
16121 tg3_flag_set(tp, JUMBO_CAPABLE);
0f893dc6 16122
52f4490c
MC		 16123 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16124 &pci_state_reg);
16125
708ebb3a 16126 if (pci_is_pcie(tp->pdev)) {
5e7dfd0f
MC		 16127 u16 lnkctl;
16128
63c3a66f 16129 tg3_flag_set(tp, PCI_EXPRESS);
5f5c51e3 16130
0f49bfbd 16131 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
5e7dfd0f 16132 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
4153577a 16133 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16134 tg3_flag_clear(tp, HW_TSO_2);
dabc5c67 16135 tg3_flag_clear(tp, TSO_CAPABLE);
7196cd6c 16136 }
4153577a
JP		 16137 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16138 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16139 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16140 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
63c3a66f 16141 tg3_flag_set(tp, CLKREQ_BUG);
4153577a 16142 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
63c3a66f 16143 tg3_flag_set(tp, L1PLLPD_EN);
c7835a77 16144 }
4153577a 16145 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
708ebb3a
JM		 16146 /* BCM5785 devices are effectively PCIe devices, and should
16147 * follow PCIe codepaths, but do not have a PCIe capabilities
16148 * section.
93a700a9 16149 */
63c3a66f
JP		 16150 tg3_flag_set(tp, PCI_EXPRESS);
16151 } else if (!tg3_flag(tp, 5705_PLUS) ||
16152 tg3_flag(tp, 5780_CLASS)) {
52f4490c
MC		 16153 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16154 if (!tp->pcix_cap) {
2445e461
MC		 16155 dev_err(&tp->pdev->dev,
16156 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 16157 return -EIO;
16158 }
16159
16160 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
63c3a66f 16161 tg3_flag_set(tp, PCIX_MODE);
52f4490c 16162 }
1da177e4 16163
399de50b
MC		 16164 /* If we have an AMD 762 or VIA K8T800 chipset, write
16165 * reordering to the mailbox registers done by the host
16166 * controller can cause major troubles. We read back from
16167 * every mailbox register write to force the writes to be
16168 * posted to the chip in order.
16169 */
4143470c 16170 if (pci_dev_present(tg3_write_reorder_chipsets) &&
63c3a66f
JP		 16171 !tg3_flag(tp, PCI_EXPRESS))
16172 tg3_flag_set(tp, MBOX_WRITE_REORDER);
399de50b 16173
69fc4053
MC		 16174 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16175 &tp->pci_cacheline_sz);
16176 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16177 &tp->pci_lat_timer);
4153577a 16178 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
1da177e4
LT		 16179 tp->pci_lat_timer < 64) {
16180 tp->pci_lat_timer = 64;
69fc4053
MC		 16181 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16182 tp->pci_lat_timer);
1da177e4
LT		 16183 }
16184
16821285
MC		 16185 /* Important! -- It is critical that the PCI-X hw workaround
16186 * situation is decided before the first MMIO register access.
16187 */
4153577a 16188 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
52f4490c
MC		 16189 /* 5700 BX chips need to have their TX producer index
16190 * mailboxes written twice to workaround a bug.
16191 */
63c3a66f 16192 tg3_flag_set(tp, TXD_MBOX_HWBUG);
1da177e4 16193
52f4490c 16194 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 16195 *
16196 * The workaround is to use indirect register accesses
16197 * for all chip writes not to mailbox registers.
16198 */
63c3a66f 16199 if (tg3_flag(tp, PCIX_MODE)) {
1da177e4 16200 u32 pm_reg;
1da177e4 16201
63c3a66f 16202 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16203
16204 /* The chip can have it's power management PCI config
16205 * space registers clobbered due to this bug.
16206 * So explicitly force the chip into D0 here.
16207 */
9974a356 16208 pci_read_config_dword(tp->pdev,
0319f30e 16209 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16210 &pm_reg);
16211 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16212 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356 16213 pci_write_config_dword(tp->pdev,
0319f30e 16214 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16215 pm_reg);
16216
16217 /* Also, force SERR#/PERR# in PCI command. */
16218 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16219 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16220 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16221 }
16222 }
16223
1da177e4 16224 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
63c3a66f 16225 tg3_flag_set(tp, PCI_HIGH_SPEED);
1da177e4 16226 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
63c3a66f 16227 tg3_flag_set(tp, PCI_32BIT);
1da177e4
LT		 16228
16229 /* Chip-specific fixup from Broadcom driver */
4153577a 16230 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
1da177e4
LT		 16231 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16232 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16233 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16234 }
16235
1ee582d8 16236 /* Default fast path register access methods */
20094930 16237 tp->read32 = tg3_read32;
1ee582d8 16238 tp->write32 = tg3_write32;
09ee929c 16239 tp->read32_mbox = tg3_read32;
20094930 16240 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 16241 tp->write32_tx_mbox = tg3_write32;
16242 tp->write32_rx_mbox = tg3_write32;
16243
16244 /* Various workaround register access methods */
63c3a66f 16245 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
1ee582d8 16246 tp->write32 = tg3_write_indirect_reg32;
4153577a 16247 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
63c3a66f 16248 (tg3_flag(tp, PCI_EXPRESS) &&
4153577a 16249 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
98efd8a6
MC		 16250 /*
16251 * Back to back register writes can cause problems on these
16252 * chips, the workaround is to read back all reg writes
16253 * except those to mailbox regs.
16254 *
16255 * See tg3_write_indirect_reg32().
16256 */
1ee582d8 16257 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 16258 }
16259
63c3a66f 16260 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
1ee582d8 16261 tp->write32_tx_mbox = tg3_write32_tx_mbox;
63c3a66f 16262 if (tg3_flag(tp, MBOX_WRITE_REORDER))
1ee582d8
MC		 16263 tp->write32_rx_mbox = tg3_write_flush_reg32;
16264 }
20094930 16265
63c3a66f 16266 if (tg3_flag(tp, ICH_WORKAROUND)) {
6892914f
MC		 16267 tp->read32 = tg3_read_indirect_reg32;
16268 tp->write32 = tg3_write_indirect_reg32;
16269 tp->read32_mbox = tg3_read_indirect_mbox;
16270 tp->write32_mbox = tg3_write_indirect_mbox;
16271 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16272 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16273
16274 iounmap(tp->regs);
22abe310 16275 tp->regs = NULL;
6892914f
MC		 16276
16277 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16278 pci_cmd &= ~PCI_COMMAND_MEMORY;
16279 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16280 }
4153577a 16281 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 16282 tp->read32_mbox = tg3_read32_mbox_5906;
16283 tp->write32_mbox = tg3_write32_mbox_5906;
16284 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16285 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16286 }
6892914f 16287
bbadf503 16288 if (tp->write32 == tg3_write_indirect_reg32 ||
63c3a66f 16289 (tg3_flag(tp, PCIX_MODE) &&
4153577a
JP		 16290 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16291 tg3_asic_rev(tp) == ASIC_REV_5701)))
63c3a66f 16292 tg3_flag_set(tp, SRAM_USE_CONFIG);
bbadf503 16293
16821285
MC		 16294 /* The memory arbiter has to be enabled in order for SRAM accesses
16295 * to succeed. Normally on powerup the tg3 chip firmware will make
16296 * sure it is enabled, but other entities such as system netboot
16297 * code might disable it.
16298 */
16299 val = tr32(MEMARB_MODE);
16300 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16301
9dc5e342 16302 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
4153577a 16303 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
9dc5e342
MC		 16304 tg3_flag(tp, 5780_CLASS)) {
16305 if (tg3_flag(tp, PCIX_MODE)) {
16306 pci_read_config_dword(tp->pdev,
16307 tp->pcix_cap + PCI_X_STATUS,
16308 &val);
16309 tp->pci_fn = val & 0x7;
16310 }
4153577a
JP		 16311 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16312 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16313 tg3_asic_rev(tp) == ASIC_REV_5720) {
9dc5e342 16314 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
857001f0
MC		 16315 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16316 val = tr32(TG3_CPMU_STATUS);
16317
4153577a 16318 if (tg3_asic_rev(tp) == ASIC_REV_5717)
857001f0
MC		 16319 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16320 else
9dc5e342
MC		 16321 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16322 TG3_CPMU_STATUS_FSHFT_5719;
69f11c99
MC		 16323 }
16324
7e6c63f0
HM		 16325 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16326 tp->write32_tx_mbox = tg3_write_flush_reg32;
16327 tp->write32_rx_mbox = tg3_write_flush_reg32;
16328 }
16329
7d0c41ef 16330 /* Get eeprom hw config before calling tg3_set_power_state().
63c3a66f 16331 * In particular, the TG3_FLAG_IS_NIC flag must be
7d0c41ef
MC		 16332 * determined before calling tg3_set_power_state() so that
16333 * we know whether or not to switch out of Vaux power.
16334 * When the flag is set, it means that GPIO1 is used for eeprom
16335 * write protect and also implies that it is a LOM where GPIOs
16336 * are not used to switch power.
6aa20a22 16337 */
7d0c41ef
MC		 16338 tg3_get_eeprom_hw_cfg(tp);
16339
1caf13eb 16340 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
cf9ecf4b
MC		 16341 tg3_flag_clear(tp, TSO_CAPABLE);
16342 tg3_flag_clear(tp, TSO_BUG);
16343 tp->fw_needed = NULL;
16344 }
16345
63c3a66f 16346 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 16347 /* Allow reads and writes to the
16348 * APE register and memory space.
16349 */
16350 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 16351 PCISTATE_ALLOW_APE_SHMEM_WR |
16352 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 16353 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16354 pci_state_reg);
c9cab24e
MC		 16355
16356 tg3_ape_lock_init(tp);
0d3031d9
MC		 16357 }
16358
16821285
MC		 16359 /* Set up tp->grc_local_ctrl before calling
16360 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16361 * will bring 5700's external PHY out of reset.
314fba34
MC		 16362 * It is also used as eeprom write protect on LOMs.
16363 */
16364 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
4153577a 16365 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
63c3a66f 16366 tg3_flag(tp, EEPROM_WRITE_PROT))
314fba34
MC		 16367 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16368 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 16369 /* Unused GPIO3 must be driven as output on 5752 because there
16370 * are no pull-up resistors on unused GPIO pins.
16371 */
4153577a 16372 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc 16373 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 16374
4153577a
JP		 16375 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16376 tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 16377 tg3_flag(tp, 57765_CLASS))
af36e6b6
MC		 16378 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16379
8d519ab2
MC		 16380 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16381 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 16382 /* Turn off the debug UART. */
16383 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
63c3a66f 16384 if (tg3_flag(tp, IS_NIC))
5f0c4a3c
MC		 16385 /* Keep VMain power. */
16386 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16387 GRC_LCLCTRL_GPIO_OUTPUT0;
16388 }
16389
4153577a 16390 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c86a8560
MC		 16391 tp->grc_local_ctrl |=
16392 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16393
16821285
MC		 16394 /* Switch out of Vaux if it is a NIC */
16395 tg3_pwrsrc_switch_to_vmain(tp);
1da177e4 16396
1da177e4
LT		 16397 /* Derive initial jumbo mode from MTU assigned in
16398 * ether_setup() via the alloc_etherdev() call
16399 */
63c3a66f
JP		 16400 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16401 tg3_flag_set(tp, JUMBO_RING_ENABLE);
1da177e4
LT		 16402
16403 /* Determine WakeOnLan speed to use. */
4153577a
JP		 16404 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16405 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16406 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16407 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
63c3a66f 16408 tg3_flag_clear(tp, WOL_SPEED_100MB);
1da177e4 16409 } else {
63c3a66f 16410 tg3_flag_set(tp, WOL_SPEED_100MB);
1da177e4
LT		 16411 }
16412
4153577a 16413 if (tg3_asic_rev(tp) == ASIC_REV_5906)
f07e9af3 16414 tp->phy_flags |= TG3_PHYFLG_IS_FET;
7f97a4bd 16415
1da177e4 16416 /* A few boards don't want Ethernet@WireSpeed phy feature */
4153577a
JP		 16417 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16418 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16419 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16420 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
f07e9af3
MC		 16421 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16422 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16423 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
1da177e4 16424
4153577a
JP		 16425 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16426 tg3_chip_rev(tp) == CHIPREV_5704_AX)
f07e9af3 16427 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
4153577a 16428 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
f07e9af3 16429 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
1da177e4 16430
63c3a66f 16431 if (tg3_flag(tp, 5705_PLUS) &&
f07e9af3 16432 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a
JP		 16433 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16434 tg3_asic_rev(tp) != ASIC_REV_57780 &&
63c3a66f 16435 !tg3_flag(tp, 57765_PLUS)) {
4153577a
JP		 16436 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16437 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16438 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16439 tg3_asic_rev(tp) == ASIC_REV_5761) {
d4011ada
MC		 16440 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16441 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
f07e9af3 16442 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
c1d2a196 16443 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
f07e9af3 16444 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
321d32a0 16445 } else
f07e9af3 16446 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
c424cb24 16447 }
1da177e4 16448
4153577a
JP		 16449 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16450 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 16451 tp->phy_otp = tg3_read_otp_phycfg(tp);
16452 if (tp->phy_otp == 0)
16453 tp->phy_otp = TG3_OTP_DEFAULT;
16454 }
16455
63c3a66f 16456 if (tg3_flag(tp, CPMU_PRESENT))
8ef21428
MC		 16457 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16458 else
16459 tp->mi_mode = MAC_MI_MODE_BASE;
16460
1da177e4 16461 tp->coalesce_mode = 0;
4153577a
JP		 16462 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16463 tg3_chip_rev(tp) != CHIPREV_5700_BX)
1da177e4
LT		 16464 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16465
4d958473 16466 /* Set these bits to enable statistics workaround. */
4153577a
JP		 16467 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16468 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16469 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
4d958473
MC		 16470 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16471 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16472 }
16473
4153577a
JP		 16474 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16475 tg3_asic_rev(tp) == ASIC_REV_57780)
63c3a66f 16476 tg3_flag_set(tp, USE_PHYLIB);
57e6983c 16477
158d7abd
MC		 16478 err = tg3_mdio_init(tp);
16479 if (err)
16480 return err;
1da177e4
LT		 16481
16482 /* Initialize data/descriptor byte/word swapping. */
16483 val = tr32(GRC_MODE);
4153577a
JP		 16484 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16485 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 16486 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16487 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16488 GRC_MODE_B2HRX_ENABLE |
16489 GRC_MODE_HTX2B_ENABLE |
16490 GRC_MODE_HOST_STACKUP);
16491 else
16492 val &= GRC_MODE_HOST_STACKUP;
16493
1da177e4
LT		 16494 tw32(GRC_MODE, val | tp->grc_mode);
16495
16496 tg3_switch_clocks(tp);
16497
16498 /* Clear this out for sanity. */
16499 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16500
16501 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16502 &pci_state_reg);
16503 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
63c3a66f 16504 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
4153577a
JP		 16505 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16506 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16507 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16508 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
1da177e4
LT		 16509 void __iomem *sram_base;
16510
16511 /* Write some dummy words into the SRAM status block
16512 * area, see if it reads back correctly. If the return
16513 * value is bad, force enable the PCIX workaround.
16514 */
16515 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16516
16517 writel(0x00000000, sram_base);
16518 writel(0x00000000, sram_base + 4);
16519 writel(0xffffffff, sram_base + 4);
16520 if (readl(sram_base) != 0x00000000)
63c3a66f 16521 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16522 }
16523 }
16524
16525 udelay(50);
16526 tg3_nvram_init(tp);
16527
c4dab506
NS		 16528 /* If the device has an NVRAM, no need to load patch firmware */
16529 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16530 !tg3_flag(tp, NO_NVRAM))
16531 tp->fw_needed = NULL;
16532
1da177e4
LT		 16533 grc_misc_cfg = tr32(GRC_MISC_CFG);
16534 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16535
4153577a 16536 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
1da177e4
LT		 16537 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16538 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
63c3a66f 16539 tg3_flag_set(tp, IS_5788);
1da177e4 16540
63c3a66f 16541 if (!tg3_flag(tp, IS_5788) &&
4153577a 16542 tg3_asic_rev(tp) != ASIC_REV_5700)
63c3a66f
JP		 16543 tg3_flag_set(tp, TAGGED_STATUS);
16544 if (tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 16545 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16546 HOSTCC_MODE_CLRTICK_TXBD);
16547
16548 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16549 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16550 tp->misc_host_ctrl);
16551 }
16552
3bda1258 16553 /* Preserve the APE MAC_MODE bits */
63c3a66f 16554 if (tg3_flag(tp, ENABLE_APE))
d2394e6b 16555 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
3bda1258 16556 else
6e01b20b 16557 tp->mac_mode = 0;
3bda1258 16558
3d567e0e 16559 if (tg3_10_100_only_device(tp, ent))
f07e9af3 16560 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
1da177e4
LT		 16561
16562 err = tg3_phy_probe(tp);
16563 if (err) {
2445e461 16564 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 16565 /* ... but do not return immediately ... */
b02fd9e3 16566 tg3_mdio_fini(tp);
1da177e4
LT		 16567 }
16568
184b8904 16569 tg3_read_vpd(tp);
c4e6575c 16570 tg3_read_fw_ver(tp);
1da177e4 16571
f07e9af3
MC		 16572 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16573 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16574 } else {
4153577a 16575 if (tg3_asic_rev(tp) == ASIC_REV_5700)
f07e9af3 16576 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16577 else
f07e9af3 16578 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4
LT		 16579 }
16580
16581 /* 5700 {AX,BX} chips have a broken status block link
16582 * change bit implementation, so we must use the
16583 * status register in those cases.
16584 */
4153577a 16585 if (tg3_asic_rev(tp) == ASIC_REV_5700)
63c3a66f 16586 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4 16587 else
63c3a66f 16588 tg3_flag_clear(tp, USE_LINKCHG_REG);
1da177e4
LT		 16589
16590 /* The led_ctrl is set during tg3_phy_probe, here we might
16591 * have to force the link status polling mechanism based
16592 * upon subsystem IDs.
16593 */
16594 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
4153577a 16595 tg3_asic_rev(tp) == ASIC_REV_5701 &&
f07e9af3
MC		 16596 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16597 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
63c3a66f 16598 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4
LT		 16599 }
16600
16601 /* For all SERDES we poll the MAC status register. */
f07e9af3 16602 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
63c3a66f 16603 tg3_flag_set(tp, POLL_SERDES);
1da177e4 16604 else
63c3a66f 16605 tg3_flag_clear(tp, POLL_SERDES);
1da177e4 16606
9205fd9c 16607 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
d2757fc4 16608 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
4153577a 16609 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
63c3a66f 16610 tg3_flag(tp, PCIX_MODE)) {
9205fd9c 16611 tp->rx_offset = NET_SKB_PAD;
d2757fc4 16612#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
9dc7a113 16613 tp->rx_copy_thresh = ~(u16)0;
d2757fc4
MC		 16614#endif
16615 }
1da177e4 16616
2c49a44d
MC		 16617 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16618 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
7cb32cf2
MC		 16619 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16620
2c49a44d 16621 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
f92905de
MC		 16622
16623 /* Increment the rx prod index on the rx std ring by at most
16624 * 8 for these chips to workaround hw errata.
16625 */
4153577a
JP		 16626 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16627 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16628 tg3_asic_rev(tp) == ASIC_REV_5755)
f92905de
MC		 16629 tp->rx_std_max_post = 8;
16630
63c3a66f 16631 if (tg3_flag(tp, ASPM_WORKAROUND))
8ed5d97e
MC		 16632 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16633 PCIE_PWR_MGMT_L1_THRESH_MSK;
16634
1da177e4
LT		 16635 return err;
16636}
16637
49b6e95f 16638#ifdef CONFIG_SPARC
229b1ad1 16639static int tg3_get_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16640{
16641 struct net_device *dev = tp->dev;
16642 struct pci_dev *pdev = tp->pdev;
49b6e95f 16643 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 16644 const unsigned char *addr;
49b6e95f
DM		 16645 int len;
16646
16647 addr = of_get_property(dp, "local-mac-address", &len);
16648 if (addr && len == 6) {
16649 memcpy(dev->dev_addr, addr, 6);
49b6e95f 16650 return 0;
1da177e4
LT		 16651 }
16652 return -ENODEV;
16653}
16654
229b1ad1 16655static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16656{
16657 struct net_device *dev = tp->dev;
16658
16659 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
16660 return 0;
16661}
16662#endif
16663
229b1ad1 16664static int tg3_get_device_address(struct tg3 *tp)
1da177e4
LT		 16665{
16666 struct net_device *dev = tp->dev;
16667 u32 hi, lo, mac_offset;
008652b3 16668 int addr_ok = 0;
7e6c63f0 16669 int err;
1da177e4 16670
49b6e95f 16671#ifdef CONFIG_SPARC
1da177e4
LT		 16672 if (!tg3_get_macaddr_sparc(tp))
16673 return 0;
16674#endif
16675
7e6c63f0
HM		 16676 if (tg3_flag(tp, IS_SSB_CORE)) {
16677 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16678 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16679 return 0;
16680 }
16681
1da177e4 16682 mac_offset = 0x7c;
4153577a 16683 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
63c3a66f 16684 tg3_flag(tp, 5780_CLASS)) {
1da177e4
LT		 16685 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16686 mac_offset = 0xcc;
16687 if (tg3_nvram_lock(tp))
16688 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16689 else
16690 tg3_nvram_unlock(tp);
63c3a66f 16691 } else if (tg3_flag(tp, 5717_PLUS)) {
69f11c99 16692 if (tp->pci_fn & 1)
a1b950d5 16693 mac_offset = 0xcc;
69f11c99 16694 if (tp->pci_fn > 1)
a50d0796 16695 mac_offset += 0x18c;
4153577a 16696 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 16697 mac_offset = 0x10;
1da177e4
LT		 16698
16699 /* First try to get it from MAC address mailbox. */
16700 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16701 if ((hi >> 16) == 0x484b) {
16702 dev->dev_addr[0] = (hi >> 8) & 0xff;
16703 dev->dev_addr[1] = (hi >> 0) & 0xff;
16704
16705 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16706 dev->dev_addr[2] = (lo >> 24) & 0xff;
16707 dev->dev_addr[3] = (lo >> 16) & 0xff;
16708 dev->dev_addr[4] = (lo >> 8) & 0xff;
16709 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 16710
008652b3
MC		 16711 /* Some old bootcode may report a 0 MAC address in SRAM */
16712 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16713 }
16714 if (!addr_ok) {
16715 /* Next, try NVRAM. */
63c3a66f 16716 if (!tg3_flag(tp, NO_NVRAM) &&
df259d8c 16717 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 16718 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 16719 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16720 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 16721 }
16722 /* Finally just fetch it out of the MAC control regs. */
16723 else {
16724 hi = tr32(MAC_ADDR_0_HIGH);
16725 lo = tr32(MAC_ADDR_0_LOW);
16726
16727 dev->dev_addr[5] = lo & 0xff;
16728 dev->dev_addr[4] = (lo >> 8) & 0xff;
16729 dev->dev_addr[3] = (lo >> 16) & 0xff;
16730 dev->dev_addr[2] = (lo >> 24) & 0xff;
16731 dev->dev_addr[1] = hi & 0xff;
16732 dev->dev_addr[0] = (hi >> 8) & 0xff;
16733 }
1da177e4
LT		 16734 }
16735
16736 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 16737#ifdef CONFIG_SPARC
1da177e4
LT		 16738 if (!tg3_get_default_macaddr_sparc(tp))
16739 return 0;
16740#endif
16741 return -EINVAL;
16742 }
16743 return 0;
16744}
16745
59e6b434
DM		 16746#define BOUNDARY_SINGLE_CACHELINE 1
16747#define BOUNDARY_MULTI_CACHELINE 2
16748
229b1ad1 16749static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
59e6b434
DM		 16750{
16751 int cacheline_size;
16752 u8 byte;
16753 int goal;
16754
16755 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
16756 if (byte == 0)
16757 cacheline_size = 1024;
16758 else
16759 cacheline_size = (int) byte * 4;
16760
16761 /* On 5703 and later chips, the boundary bits have no
16762 * effect.
16763 */
4153577a
JP		 16764 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16765 tg3_asic_rev(tp) != ASIC_REV_5701 &&
63c3a66f 16766 !tg3_flag(tp, PCI_EXPRESS))
59e6b434
DM		 16767 goto out;
16768
16769#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
16770 goal = BOUNDARY_MULTI_CACHELINE;
16771#else
16772#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
16773 goal = BOUNDARY_SINGLE_CACHELINE;
16774#else
16775 goal = 0;
16776#endif
16777#endif
16778
63c3a66f 16779 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 16780 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
16781 goto out;
16782 }
16783
59e6b434
DM		 16784 if (!goal)
16785 goto out;
16786
16787 /* PCI controllers on most RISC systems tend to disconnect
16788 * when a device tries to burst across a cache-line boundary.
16789 * Therefore, letting tg3 do so just wastes PCI bandwidth.
16790 *
16791 * Unfortunately, for PCI-E there are only limited
16792 * write-side controls for this, and thus for reads
16793 * we will still get the disconnects. We'll also waste
16794 * these PCI cycles for both read and write for chips
16795 * other than 5700 and 5701 which do not implement the
16796 * boundary bits.
16797 */
63c3a66f 16798 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16799 switch (cacheline_size) {
16800 case 16:
16801 case 32:
16802 case 64:
16803 case 128:
16804 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16805 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
16806 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
16807 } else {
16808 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16809 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16810 }
16811 break;
16812
16813 case 256:
16814 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
16815 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
16816 break;
16817
16818 default:
16819 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16820 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16821 break;
855e1111 16822 }
63c3a66f 16823 } else if (tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16824 switch (cacheline_size) {
16825 case 16:
16826 case 32:
16827 case 64:
16828 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16829 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16830 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
16831 break;
16832 }
16833 /* fallthrough */
16834 case 128:
16835 default:
16836 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16837 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
16838 break;
855e1111 16839 }
59e6b434
DM		 16840 } else {
16841 switch (cacheline_size) {
16842 case 16:
16843 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16844 val |= (DMA_RWCTRL_READ_BNDRY_16 |
16845 DMA_RWCTRL_WRITE_BNDRY_16);
16846 break;
16847 }
16848 /* fallthrough */
16849 case 32:
16850 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16851 val |= (DMA_RWCTRL_READ_BNDRY_32 |
16852 DMA_RWCTRL_WRITE_BNDRY_32);
16853 break;
16854 }
16855 /* fallthrough */
16856 case 64:
16857 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16858 val |= (DMA_RWCTRL_READ_BNDRY_64 |
16859 DMA_RWCTRL_WRITE_BNDRY_64);
16860 break;
16861 }
16862 /* fallthrough */
16863 case 128:
16864 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16865 val |= (DMA_RWCTRL_READ_BNDRY_128 |
16866 DMA_RWCTRL_WRITE_BNDRY_128);
16867 break;
16868 }
16869 /* fallthrough */
16870 case 256:
16871 val |= (DMA_RWCTRL_READ_BNDRY_256 |
16872 DMA_RWCTRL_WRITE_BNDRY_256);
16873 break;
16874 case 512:
16875 val |= (DMA_RWCTRL_READ_BNDRY_512 |
16876 DMA_RWCTRL_WRITE_BNDRY_512);
16877 break;
16878 case 1024:
16879 default:
16880 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
16881 DMA_RWCTRL_WRITE_BNDRY_1024);
16882 break;
855e1111 16883 }
59e6b434
DM		 16884 }
16885
16886out:
16887 return val;
16888}
16889
229b1ad1 16890static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
953c96e0 16891 int size, bool to_device)
1da177e4
LT		 16892{
16893 struct tg3_internal_buffer_desc test_desc;
16894 u32 sram_dma_descs;
16895 int i, ret;
16896
16897 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
16898
16899 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
16900 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
16901 tw32(RDMAC_STATUS, 0);
16902 tw32(WDMAC_STATUS, 0);
16903
16904 tw32(BUFMGR_MODE, 0);
16905 tw32(FTQ_RESET, 0);
16906
16907 test_desc.addr_hi = ((u64) buf_dma) >> 32;
16908 test_desc.addr_lo = buf_dma & 0xffffffff;
16909 test_desc.nic_mbuf = 0x00002100;
16910 test_desc.len = size;
16911
16912 /*
16913 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
16914 * the *second* time the tg3 driver was getting loaded after an
16915 * initial scan.
16916 *
16917 * Broadcom tells me:
16918 * ...the DMA engine is connected to the GRC block and a DMA
16919 * reset may affect the GRC block in some unpredictable way...
16920 * The behavior of resets to individual blocks has not been tested.
16921 *
16922 * Broadcom noted the GRC reset will also reset all sub-components.
16923 */
16924 if (to_device) {
16925 test_desc.cqid_sqid = (13 << 8) | 2;
16926
16927 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
16928 udelay(40);
16929 } else {
16930 test_desc.cqid_sqid = (16 << 8) | 7;
16931
16932 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
16933 udelay(40);
16934 }
16935 test_desc.flags = 0x00000005;
16936
16937 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
16938 u32 val;
16939
16940 val = *(((u32 *)&test_desc) + i);
16941 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
16942 sram_dma_descs + (i * sizeof(u32)));
16943 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
16944 }
16945 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
16946
859a5887 16947 if (to_device)
1da177e4 16948 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
859a5887 16949 else
1da177e4 16950 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
1da177e4
LT		 16951
16952 ret = -ENODEV;
16953 for (i = 0; i < 40; i++) {
16954 u32 val;
16955
16956 if (to_device)
16957 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
16958 else
16959 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
16960 if ((val & 0xffff) == sram_dma_descs) {
16961 ret = 0;
16962 break;
16963 }
16964
16965 udelay(100);
16966 }
16967
16968 return ret;
16969}
16970
ded7340d 16971#define TEST_BUFFER_SIZE 0x2000
1da177e4 16972
4143470c 16973static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
895950c2
JP		 16974 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
16975 { },
16976};
16977
229b1ad1 16978static int tg3_test_dma(struct tg3 *tp)
1da177e4
LT		 16979{
16980 dma_addr_t buf_dma;
59e6b434 16981 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 16982 int ret = 0;
1da177e4 16983
4bae65c8
MC		 16984 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
16985 &buf_dma, GFP_KERNEL);
1da177e4
LT		 16986 if (!buf) {
16987 ret = -ENOMEM;
16988 goto out_nofree;
16989 }
16990
16991 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
16992 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
16993
59e6b434 16994 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 16995
63c3a66f 16996 if (tg3_flag(tp, 57765_PLUS))
cbf9ca6c
MC		 16997 goto out;
16998
63c3a66f 16999 if (tg3_flag(tp, PCI_EXPRESS)) {
1da177e4
LT		 17000 /* DMA read watermark not used on PCIE */
17001 tp->dma_rwctrl |= 0x00180000;
63c3a66f 17002 } else if (!tg3_flag(tp, PCIX_MODE)) {
4153577a
JP		 17003 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17004 tg3_asic_rev(tp) == ASIC_REV_5750)
1da177e4
LT		 17005 tp->dma_rwctrl |= 0x003f0000;
17006 else
17007 tp->dma_rwctrl |= 0x003f000f;
17008 } else {
4153577a
JP		 17009 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17010 tg3_asic_rev(tp) == ASIC_REV_5704) {
1da177e4 17011 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 17012 u32 read_water = 0x7;
1da177e4 17013
4a29cc2e
MC		 17014 /* If the 5704 is behind the EPB bridge, we can
17015 * do the less restrictive ONE_DMA workaround for
17016 * better performance.
17017 */
63c3a66f 17018 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
4153577a 17019 tg3_asic_rev(tp) == ASIC_REV_5704)
4a29cc2e
MC		 17020 tp->dma_rwctrl |= 0x8000;
17021 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 17022 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17023
4153577a 17024 if (tg3_asic_rev(tp) == ASIC_REV_5703)
49afdeb6 17025 read_water = 4;
59e6b434 17026 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 17027 tp->dma_rwctrl |=
17028 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17029 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17030 (1 << 23);
4153577a 17031 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
4cf78e4f
MC		 17032 /* 5780 always in PCIX mode */
17033 tp->dma_rwctrl |= 0x00144000;
4153577a 17034 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
a4e2b347
MC		 17035 /* 5714 always in PCIX mode */
17036 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 17037 } else {
17038 tp->dma_rwctrl |= 0x001b000f;
17039 }
17040 }
7e6c63f0
HM		 17041 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17042 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
1da177e4 17043
4153577a
JP		 17044 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17045 tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 17046 tp->dma_rwctrl &= 0xfffffff0;
17047
4153577a
JP		 17048 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17049 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 17050 /* Remove this if it causes problems for some boards. */
17051 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17052
17053 /* On 5700/5701 chips, we need to set this bit.
17054 * Otherwise the chip will issue cacheline transactions
17055 * to streamable DMA memory with not all the byte
17056 * enables turned on. This is an error on several
17057 * RISC PCI controllers, in particular sparc64.
17058 *
17059 * On 5703/5704 chips, this bit has been reassigned
17060 * a different meaning. In particular, it is used
17061 * on those chips to enable a PCI-X workaround.
17062 */
17063 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17064 }
17065
17066 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17067
1da177e4 17068
4153577a
JP		 17069 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17070 tg3_asic_rev(tp) != ASIC_REV_5701)
1da177e4
LT		 17071 goto out;
17072
59e6b434
DM		 17073 /* It is best to perform DMA test with maximum write burst size
17074 * to expose the 5700/5701 write DMA bug.
17075 */
17076 saved_dma_rwctrl = tp->dma_rwctrl;
17077 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17078 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17079
1da177e4
LT		 17080 while (1) {
17081 u32 *p = buf, i;
17082
17083 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17084 p[i] = i;
17085
17086 /* Send the buffer to the chip. */
953c96e0 17087 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
1da177e4 17088 if (ret) {
2445e461
MC		 17089 dev_err(&tp->pdev->dev,
17090 "%s: Buffer write failed. err = %d\n",
17091 __func__, ret);
1da177e4
LT		 17092 break;
17093 }
17094
1da177e4 17095 /* Now read it back. */
953c96e0 17096 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
1da177e4 17097 if (ret) {
5129c3a3
MC		 17098 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17099 "err = %d\n", __func__, ret);
1da177e4
LT		 17100 break;
17101 }
17102
17103 /* Verify it. */
17104 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17105 if (p[i] == i)
17106 continue;
17107
59e6b434
DM		 17108 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17109 DMA_RWCTRL_WRITE_BNDRY_16) {
17110 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 17111 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17112 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17113 break;
17114 } else {
2445e461
MC		 17115 dev_err(&tp->pdev->dev,
17116 "%s: Buffer corrupted on read back! "
17117 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 17118 ret = -ENODEV;
17119 goto out;
17120 }
17121 }
17122
17123 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17124 /* Success. */
17125 ret = 0;
17126 break;
17127 }
17128 }
59e6b434
DM		 17129 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17130 DMA_RWCTRL_WRITE_BNDRY_16) {
17131 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 17132 * now look for chipsets that are known to expose the
17133 * DMA bug without failing the test.
59e6b434 17134 */
4143470c 17135 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
6d1cfbab
MC		 17136 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17137 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
859a5887 17138 } else {
6d1cfbab
MC		 17139 /* Safe to use the calculated DMA boundary. */
17140 tp->dma_rwctrl = saved_dma_rwctrl;
859a5887 17141 }
6d1cfbab 17142
59e6b434
DM		 17143 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17144 }
1da177e4
LT		 17145
17146out:
4bae65c8 17147 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
1da177e4
LT		 17148out_nofree:
17149 return ret;
17150}
17151
229b1ad1 17152static void tg3_init_bufmgr_config(struct tg3 *tp)
1da177e4 17153{
63c3a66f 17154 if (tg3_flag(tp, 57765_PLUS)) {
666bc831
MC		 17155 tp->bufmgr_config.mbuf_read_dma_low_water =
17156 DEFAULT_MB_RDMA_LOW_WATER_5705;
17157 tp->bufmgr_config.mbuf_mac_rx_low_water =
17158 DEFAULT_MB_MACRX_LOW_WATER_57765;
17159 tp->bufmgr_config.mbuf_high_water =
17160 DEFAULT_MB_HIGH_WATER_57765;
17161
17162 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17163 DEFAULT_MB_RDMA_LOW_WATER_5705;
17164 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17165 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17166 tp->bufmgr_config.mbuf_high_water_jumbo =
17167 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
63c3a66f 17168 } else if (tg3_flag(tp, 5705_PLUS)) {
fdfec172
MC		 17169 tp->bufmgr_config.mbuf_read_dma_low_water =
17170 DEFAULT_MB_RDMA_LOW_WATER_5705;
17171 tp->bufmgr_config.mbuf_mac_rx_low_water =
17172 DEFAULT_MB_MACRX_LOW_WATER_5705;
17173 tp->bufmgr_config.mbuf_high_water =
17174 DEFAULT_MB_HIGH_WATER_5705;
4153577a 17175 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 17176 tp->bufmgr_config.mbuf_mac_rx_low_water =
17177 DEFAULT_MB_MACRX_LOW_WATER_5906;
17178 tp->bufmgr_config.mbuf_high_water =
17179 DEFAULT_MB_HIGH_WATER_5906;
17180 }
fdfec172
MC		 17181
17182 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17183 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17184 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17185 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17186 tp->bufmgr_config.mbuf_high_water_jumbo =
17187 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17188 } else {
17189 tp->bufmgr_config.mbuf_read_dma_low_water =
17190 DEFAULT_MB_RDMA_LOW_WATER;
17191 tp->bufmgr_config.mbuf_mac_rx_low_water =
17192 DEFAULT_MB_MACRX_LOW_WATER;
17193 tp->bufmgr_config.mbuf_high_water =
17194 DEFAULT_MB_HIGH_WATER;
17195
17196 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17197 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17198 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17199 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17200 tp->bufmgr_config.mbuf_high_water_jumbo =
17201 DEFAULT_MB_HIGH_WATER_JUMBO;
17202 }
1da177e4
LT		 17203
17204 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17205 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17206}
17207
229b1ad1 17208static char *tg3_phy_string(struct tg3 *tp)
1da177e4 17209{
79eb6904
MC		 17210 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17211 case TG3_PHY_ID_BCM5400: return "5400";
17212 case TG3_PHY_ID_BCM5401: return "5401";
17213 case TG3_PHY_ID_BCM5411: return "5411";
17214 case TG3_PHY_ID_BCM5701: return "5701";
17215 case TG3_PHY_ID_BCM5703: return "5703";
17216 case TG3_PHY_ID_BCM5704: return "5704";
17217 case TG3_PHY_ID_BCM5705: return "5705";
17218 case TG3_PHY_ID_BCM5750: return "5750";
17219 case TG3_PHY_ID_BCM5752: return "5752";
17220 case TG3_PHY_ID_BCM5714: return "5714";
17221 case TG3_PHY_ID_BCM5780: return "5780";
17222 case TG3_PHY_ID_BCM5755: return "5755";
17223 case TG3_PHY_ID_BCM5787: return "5787";
17224 case TG3_PHY_ID_BCM5784: return "5784";
17225 case TG3_PHY_ID_BCM5756: return "5722/5756";
17226 case TG3_PHY_ID_BCM5906: return "5906";
17227 case TG3_PHY_ID_BCM5761: return "5761";
17228 case TG3_PHY_ID_BCM5718C: return "5718C";
17229 case TG3_PHY_ID_BCM5718S: return "5718S";
17230 case TG3_PHY_ID_BCM57765: return "57765";
302b500b 17231 case TG3_PHY_ID_BCM5719C: return "5719C";
6418f2c1 17232 case TG3_PHY_ID_BCM5720C: return "5720C";
c65a17f4 17233 case TG3_PHY_ID_BCM5762: return "5762C";
79eb6904 17234 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 17235 case 0: return "serdes";
17236 default: return "unknown";
855e1111 17237 }
1da177e4
LT		 17238}
17239
229b1ad1 17240static char *tg3_bus_string(struct tg3 *tp, char *str)
f9804ddb 17241{
63c3a66f 17242 if (tg3_flag(tp, PCI_EXPRESS)) {
f9804ddb
MC		 17243 strcpy(str, "PCI Express");
17244 return str;
63c3a66f 17245 } else if (tg3_flag(tp, PCIX_MODE)) {
f9804ddb
MC		 17246 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17247
17248 strcpy(str, "PCIX:");
17249
17250 if ((clock_ctrl == 7) ||
17251 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17252 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17253 strcat(str, "133MHz");
17254 else if (clock_ctrl == 0)
17255 strcat(str, "33MHz");
17256 else if (clock_ctrl == 2)
17257 strcat(str, "50MHz");
17258 else if (clock_ctrl == 4)
17259 strcat(str, "66MHz");
17260 else if (clock_ctrl == 6)
17261 strcat(str, "100MHz");
f9804ddb
MC		 17262 } else {
17263 strcpy(str, "PCI:");
63c3a66f 17264 if (tg3_flag(tp, PCI_HIGH_SPEED))
f9804ddb
MC		 17265 strcat(str, "66MHz");
17266 else
17267 strcat(str, "33MHz");
17268 }
63c3a66f 17269 if (tg3_flag(tp, PCI_32BIT))
f9804ddb
MC		 17270 strcat(str, ":32-bit");
17271 else
17272 strcat(str, ":64-bit");
17273 return str;
17274}
17275
229b1ad1 17276static void tg3_init_coal(struct tg3 *tp)
15f9850d
DM		 17277{
17278 struct ethtool_coalesce *ec = &tp->coal;
17279
17280 memset(ec, 0, sizeof(*ec));
17281 ec->cmd = ETHTOOL_GCOALESCE;
17282 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17283 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17284 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17285 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17286 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17287 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17288 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17289 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17290 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17291
17292 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17293 HOSTCC_MODE_CLRTICK_TXBD)) {
17294 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17295 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17296 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17297 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17298 }
d244c892 17299
63c3a66f 17300 if (tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 17301 ec->rx_coalesce_usecs_irq = 0;
17302 ec->tx_coalesce_usecs_irq = 0;
17303 ec->stats_block_coalesce_usecs = 0;
17304 }
15f9850d
DM		 17305}
17306
229b1ad1 17307static int tg3_init_one(struct pci_dev *pdev,
1da177e4
LT		 17308 const struct pci_device_id *ent)
17309{
1da177e4
LT		 17310 struct net_device *dev;
17311 struct tg3 *tp;
5865fc1b 17312 int i, err;
646c9edd 17313 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 17314 char str[40];
72f2afb8 17315 u64 dma_mask, persist_dma_mask;
c8f44aff 17316 netdev_features_t features = 0;
1da177e4 17317
05dbe005 17318 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 17319
17320 err = pci_enable_device(pdev);
17321 if (err) {
2445e461 17322 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 17323 return err;
17324 }
17325
1da177e4
LT		 17326 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17327 if (err) {
2445e461 17328 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 17329 goto err_out_disable_pdev;
17330 }
17331
17332 pci_set_master(pdev);
17333
fe5f5787 17334 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 17335 if (!dev) {
1da177e4 17336 err = -ENOMEM;
5865fc1b 17337 goto err_out_free_res;
1da177e4
LT		 17338 }
17339
1da177e4
LT		 17340 SET_NETDEV_DEV(dev, &pdev->dev);
17341
1da177e4
LT		 17342 tp = netdev_priv(dev);
17343 tp->pdev = pdev;
17344 tp->dev = dev;
1da177e4
LT		 17345 tp->rx_mode = TG3_DEF_RX_MODE;
17346 tp->tx_mode = TG3_DEF_TX_MODE;
9c13cb8b 17347 tp->irq_sync = 1;
8ef21428 17348
1da177e4
LT		 17349 if (tg3_debug > 0)
17350 tp->msg_enable = tg3_debug;
17351 else
17352 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17353
7e6c63f0
HM		 17354 if (pdev_is_ssb_gige_core(pdev)) {
17355 tg3_flag_set(tp, IS_SSB_CORE);
17356 if (ssb_gige_must_flush_posted_writes(pdev))
17357 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17358 if (ssb_gige_one_dma_at_once(pdev))
17359 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17360 if (ssb_gige_have_roboswitch(pdev))
17361 tg3_flag_set(tp, ROBOSWITCH);
17362 if (ssb_gige_is_rgmii(pdev))
17363 tg3_flag_set(tp, RGMII_MODE);
17364 }
17365
1da177e4
LT		 17366 /* The word/byte swap controls here control register access byte
17367 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17368 * setting below.
17369 */
17370 tp->misc_host_ctrl =
17371 MISC_HOST_CTRL_MASK_PCI_INT |
17372 MISC_HOST_CTRL_WORD_SWAP |
17373 MISC_HOST_CTRL_INDIR_ACCESS |
17374 MISC_HOST_CTRL_PCISTATE_RW;
17375
17376 /* The NONFRM (non-frame) byte/word swap controls take effect
17377 * on descriptor entries, anything which isn't packet data.
17378 *
17379 * The StrongARM chips on the board (one for tx, one for rx)
17380 * are running in big-endian mode.
17381 */
17382 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17383 GRC_MODE_WSWAP_NONFRM_DATA);
17384#ifdef __BIG_ENDIAN
17385 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17386#endif
17387 spin_lock_init(&tp->lock);
1da177e4 17388 spin_lock_init(&tp->indirect_lock);
c4028958 17389 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 17390
d5fe488a 17391 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 17392 if (!tp->regs) {
ab96b241 17393 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 17394 err = -ENOMEM;
17395 goto err_out_free_dev;
17396 }
17397
c9cab24e
MC		 17398 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17399 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17400 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17401 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17402 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 17403 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
c9cab24e
MC		 17404 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17405 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 17406 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 17407 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17408 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 17409 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17410 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 17411 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17412 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
c9cab24e
MC		 17413 tg3_flag_set(tp, ENABLE_APE);
17414 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17415 if (!tp->aperegs) {
17416 dev_err(&pdev->dev,
17417 "Cannot map APE registers, aborting\n");
17418 err = -ENOMEM;
17419 goto err_out_iounmap;
17420 }
17421 }
17422
1da177e4
LT		 17423 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17424 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 17425
1da177e4 17426 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 17427 dev->watchdog_timeo = TG3_TX_TIMEOUT;
2ffcc981 17428 dev->netdev_ops = &tg3_netdev_ops;
1da177e4 17429 dev->irq = pdev->irq;
1da177e4 17430
3d567e0e 17431 err = tg3_get_invariants(tp, ent);
1da177e4 17432 if (err) {
ab96b241
MC		 17433 dev_err(&pdev->dev,
17434 "Problem fetching invariants of chip, aborting\n");
c9cab24e 17435 goto err_out_apeunmap;
1da177e4
LT		 17436 }
17437
4a29cc2e
MC		 17438 /* The EPB bridge inside 5714, 5715, and 5780 and any
17439 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 17440 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17441 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17442 * do DMA address check in tg3_start_xmit().
17443 */
63c3a66f 17444 if (tg3_flag(tp, IS_5788))
284901a9 17445 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
63c3a66f 17446 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
50cf156a 17447 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 17448#ifdef CONFIG_HIGHMEM
6a35528a 17449 dma_mask = DMA_BIT_MASK(64);
72f2afb8 17450#endif
4a29cc2e 17451 } else
6a35528a 17452 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 17453
17454 /* Configure DMA attributes. */
284901a9 17455 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 17456 err = pci_set_dma_mask(pdev, dma_mask);
17457 if (!err) {
0da0606f 17458 features |= NETIF_F_HIGHDMA;
72f2afb8
MC		 17459 err = pci_set_consistent_dma_mask(pdev,
17460 persist_dma_mask);
17461 if (err < 0) {
ab96b241
MC		 17462 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17463 "DMA for consistent allocations\n");
c9cab24e 17464 goto err_out_apeunmap;
72f2afb8
MC		 17465 }
17466 }
17467 }
284901a9
YH		 17468 if (err || dma_mask == DMA_BIT_MASK(32)) {
17469 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 17470 if (err) {
ab96b241
MC		 17471 dev_err(&pdev->dev,
17472 "No usable DMA configuration, aborting\n");
c9cab24e 17473 goto err_out_apeunmap;
72f2afb8
MC		 17474 }
17475 }
17476
fdfec172 17477 tg3_init_bufmgr_config(tp);
1da177e4 17478
f646968f 17479 features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
0da0606f
MC		 17480
17481 /* 5700 B0 chips do not support checksumming correctly due
17482 * to hardware bugs.
17483 */
4153577a 17484 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
0da0606f
MC		 17485 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17486
17487 if (tg3_flag(tp, 5755_PLUS))
17488 features |= NETIF_F_IPV6_CSUM;
17489 }
17490
4e3a7aaa
MC		 17491 /* TSO is on by default on chips that support hardware TSO.
17492 * Firmware TSO on older chips gives lower performance, so it
17493 * is off by default, but can be enabled using ethtool.
17494 */
63c3a66f
JP		 17495 if ((tg3_flag(tp, HW_TSO_1) ||
17496 tg3_flag(tp, HW_TSO_2) ||
17497 tg3_flag(tp, HW_TSO_3)) &&
0da0606f
MC		 17498 (features & NETIF_F_IP_CSUM))
17499 features |= NETIF_F_TSO;
63c3a66f 17500 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
0da0606f
MC		 17501 if (features & NETIF_F_IPV6_CSUM)
17502 features |= NETIF_F_TSO6;
63c3a66f 17503 if (tg3_flag(tp, HW_TSO_3) ||
4153577a
JP		 17504 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17505 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17506 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17507 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17508 tg3_asic_rev(tp) == ASIC_REV_57780)
0da0606f 17509 features |= NETIF_F_TSO_ECN;
b0026624 17510 }
1da177e4 17511
d542fe27
MC		 17512 dev->features |= features;
17513 dev->vlan_features |= features;
17514
06c03c02
MB		 17515 /*
17516 * Add loopback capability only for a subset of devices that support
17517 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17518 * loopback for the remaining devices.
17519 */
4153577a 17520 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
06c03c02
MB		 17521 !tg3_flag(tp, CPMU_PRESENT))
17522 /* Add the loopback capability */
0da0606f
MC		 17523 features |= NETIF_F_LOOPBACK;
17524
0da0606f 17525 dev->hw_features |= features;
06c03c02 17526
4153577a 17527 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
63c3a66f 17528 !tg3_flag(tp, TSO_CAPABLE) &&
1da177e4 17529 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
63c3a66f 17530 tg3_flag_set(tp, MAX_RXPEND_64);
1da177e4
LT		 17531 tp->rx_pending = 63;
17532 }
17533
1da177e4
LT		 17534 err = tg3_get_device_address(tp);
17535 if (err) {
ab96b241
MC		 17536 dev_err(&pdev->dev,
17537 "Could not obtain valid ethernet address, aborting\n");
c9cab24e 17538 goto err_out_apeunmap;
c88864df
MC		 17539 }
17540
1da177e4
LT		 17541 /*
17542 * Reset chip in case UNDI or EFI driver did not shutdown
17543 * DMA self test will enable WDMAC and we'll see (spurious)
17544 * pending DMA on the PCI bus at that point.
17545 */
17546 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17547 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 17548 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 17549 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 17550 }
17551
17552 err = tg3_test_dma(tp);
17553 if (err) {
ab96b241 17554 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
c88864df 17555 goto err_out_apeunmap;
1da177e4
LT		 17556 }
17557
78f90dcf
MC		 17558 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17559 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17560 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6fd45cb8 17561 for (i = 0; i < tp->irq_max; i++) {
78f90dcf
MC		 17562 struct tg3_napi *tnapi = &tp->napi[i];
17563
17564 tnapi->tp = tp;
17565 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17566
17567 tnapi->int_mbox = intmbx;
93a700a9 17568 if (i <= 4)
78f90dcf
MC		 17569 intmbx += 0x8;
17570 else
17571 intmbx += 0x4;
17572
17573 tnapi->consmbox = rcvmbx;
17574 tnapi->prodmbox = sndmbx;
17575
66cfd1bd 17576 if (i)
78f90dcf 17577 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
66cfd1bd 17578 else
78f90dcf 17579 tnapi->coal_now = HOSTCC_MODE_NOW;
78f90dcf 17580
63c3a66f 17581 if (!tg3_flag(tp, SUPPORT_MSIX))
78f90dcf
MC		 17582 break;
17583
17584 /*
17585 * If we support MSIX, we'll be using RSS. If we're using
17586 * RSS, the first vector only handles link interrupts and the
17587 * remaining vectors handle rx and tx interrupts. Reuse the
17588 * mailbox values for the next iteration. The values we setup
17589 * above are still useful for the single vectored mode.
17590 */
17591 if (!i)
17592 continue;
17593
17594 rcvmbx += 0x8;
17595
17596 if (sndmbx & 0x4)
17597 sndmbx -= 0x4;
17598 else
17599 sndmbx += 0xc;
17600 }
17601
15f9850d
DM		 17602 tg3_init_coal(tp);
17603
c49a1561
MC		 17604 pci_set_drvdata(pdev, dev);
17605
4153577a
JP		 17606 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17607 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17608 tg3_asic_rev(tp) == ASIC_REV_5762)
fb4ce8ad
MC		 17609 tg3_flag_set(tp, PTP_CAPABLE);
17610
21f7638e
MC		 17611 tg3_timer_init(tp);
17612
402e1398
MC		 17613 tg3_carrier_off(tp);
17614
1da177e4
LT		 17615 err = register_netdev(dev);
17616 if (err) {
ab96b241 17617 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 17618 goto err_out_apeunmap;
1da177e4
LT		 17619 }
17620
05dbe005
JP		 17621 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17622 tp->board_part_number,
4153577a 17623 tg3_chip_rev_id(tp),
05dbe005
JP		 17624 tg3_bus_string(tp, str),
17625 dev->dev_addr);
1da177e4 17626
f07e9af3 17627 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7
MC		 17628 struct phy_device *phydev;
17629 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
5129c3a3
MC		 17630 netdev_info(dev,
17631 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
05dbe005 17632 phydev->drv->name, dev_name(&phydev->dev));
f07e9af3
MC		 17633 } else {
17634 char *ethtype;
17635
17636 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17637 ethtype = "10/100Base-TX";
17638 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17639 ethtype = "1000Base-SX";
17640 else
17641 ethtype = "10/100/1000Base-T";
17642
5129c3a3 17643 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
47007831
MC		 17644 "(WireSpeed[%d], EEE[%d])\n",
17645 tg3_phy_string(tp), ethtype,
17646 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17647 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
f07e9af3 17648 }
05dbe005
JP		 17649
17650 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
dc668910 17651 (dev->features & NETIF_F_RXCSUM) != 0,
63c3a66f 17652 tg3_flag(tp, USE_LINKCHG_REG) != 0,
f07e9af3 17653 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
63c3a66f
JP		 17654 tg3_flag(tp, ENABLE_ASF) != 0,
17655 tg3_flag(tp, TSO_CAPABLE) != 0);
05dbe005
JP		 17656 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17657 tp->dma_rwctrl,
17658 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17659 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4 17660
b45aa2f6
MC		 17661 pci_save_state(pdev);
17662
1da177e4
LT		 17663 return 0;
17664
0d3031d9
MC		 17665err_out_apeunmap:
17666 if (tp->aperegs) {
17667 iounmap(tp->aperegs);
17668 tp->aperegs = NULL;
17669 }
17670
1da177e4 17671err_out_iounmap:
6892914f
MC		 17672 if (tp->regs) {
17673 iounmap(tp->regs);
22abe310 17674 tp->regs = NULL;
6892914f 17675 }
1da177e4
LT		 17676
17677err_out_free_dev:
17678 free_netdev(dev);
17679
17680err_out_free_res:
17681 pci_release_regions(pdev);
17682
17683err_out_disable_pdev:
c80dc13d
GS		 17684 if (pci_is_enabled(pdev))
17685 pci_disable_device(pdev);
1da177e4
LT		 17686 pci_set_drvdata(pdev, NULL);
17687 return err;
17688}
17689
229b1ad1 17690static void tg3_remove_one(struct pci_dev *pdev)
1da177e4
LT		 17691{
17692 struct net_device *dev = pci_get_drvdata(pdev);
17693
17694 if (dev) {
17695 struct tg3 *tp = netdev_priv(dev);
17696
e3c5530b 17697 release_firmware(tp->fw);
077f849d 17698
db219973 17699 tg3_reset_task_cancel(tp);
158d7abd 17700
e730c823 17701 if (tg3_flag(tp, USE_PHYLIB)) {
b02fd9e3 17702 tg3_phy_fini(tp);
158d7abd 17703 tg3_mdio_fini(tp);
b02fd9e3 17704 }
158d7abd 17705
1da177e4 17706 unregister_netdev(dev);
0d3031d9
MC		 17707 if (tp->aperegs) {
17708 iounmap(tp->aperegs);
17709 tp->aperegs = NULL;
17710 }
6892914f
MC		 17711 if (tp->regs) {
17712 iounmap(tp->regs);
22abe310 17713 tp->regs = NULL;
6892914f 17714 }
1da177e4
LT		 17715 free_netdev(dev);
17716 pci_release_regions(pdev);
17717 pci_disable_device(pdev);
17718 pci_set_drvdata(pdev, NULL);
17719 }
17720}
17721
aa6027ca 17722#ifdef CONFIG_PM_SLEEP
c866b7ea 17723static int tg3_suspend(struct device *device)
1da177e4 17724{
c866b7ea 17725 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17726 struct net_device *dev = pci_get_drvdata(pdev);
17727 struct tg3 *tp = netdev_priv(dev);
17728 int err;
17729
17730 if (!netif_running(dev))
17731 return 0;
17732
db219973 17733 tg3_reset_task_cancel(tp);
b02fd9e3 17734 tg3_phy_stop(tp);
1da177e4
LT		 17735 tg3_netif_stop(tp);
17736
21f7638e 17737 tg3_timer_stop(tp);
1da177e4 17738
f47c11ee 17739 tg3_full_lock(tp, 1);
1da177e4 17740 tg3_disable_ints(tp);
f47c11ee 17741 tg3_full_unlock(tp);
1da177e4
LT		 17742
17743 netif_device_detach(dev);
17744
f47c11ee 17745 tg3_full_lock(tp, 0);
944d980e 17746 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
63c3a66f 17747 tg3_flag_clear(tp, INIT_COMPLETE);
f47c11ee 17748 tg3_full_unlock(tp);
1da177e4 17749
c866b7ea 17750 err = tg3_power_down_prepare(tp);
1da177e4 17751 if (err) {
b02fd9e3
MC		 17752 int err2;
17753
f47c11ee 17754 tg3_full_lock(tp, 0);
1da177e4 17755
63c3a66f 17756 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 17757 err2 = tg3_restart_hw(tp, true);
b02fd9e3 17758 if (err2)
b9ec6c1b 17759 goto out;
1da177e4 17760
21f7638e 17761 tg3_timer_start(tp);
1da177e4
LT		 17762
17763 netif_device_attach(dev);
17764 tg3_netif_start(tp);
17765
b9ec6c1b 17766out:
f47c11ee 17767 tg3_full_unlock(tp);
b02fd9e3
MC		 17768
17769 if (!err2)
17770 tg3_phy_start(tp);
1da177e4
LT		 17771 }
17772
17773 return err;
17774}
17775
c866b7ea 17776static int tg3_resume(struct device *device)
1da177e4 17777{
c866b7ea 17778 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17779 struct net_device *dev = pci_get_drvdata(pdev);
17780 struct tg3 *tp = netdev_priv(dev);
17781 int err;
17782
17783 if (!netif_running(dev))
17784 return 0;
17785
1da177e4
LT		 17786 netif_device_attach(dev);
17787
f47c11ee 17788 tg3_full_lock(tp, 0);
1da177e4 17789
2e460fc0
NS		 17790 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
17791
63c3a66f 17792 tg3_flag_set(tp, INIT_COMPLETE);
942d1af0
NS		 17793 err = tg3_restart_hw(tp,
17794 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
b9ec6c1b
MC		 17795 if (err)
17796 goto out;
1da177e4 17797
21f7638e 17798 tg3_timer_start(tp);
1da177e4 17799
1da177e4
LT		 17800 tg3_netif_start(tp);
17801
b9ec6c1b 17802out:
f47c11ee 17803 tg3_full_unlock(tp);
1da177e4 17804
b02fd9e3
MC		 17805 if (!err)
17806 tg3_phy_start(tp);
17807
b9ec6c1b 17808 return err;
1da177e4 17809}
42df36a6 17810#endif /* CONFIG_PM_SLEEP */
1da177e4 17811
c866b7ea
RW		 17812static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
17813
4c305fa2
NS		 17814static void tg3_shutdown(struct pci_dev *pdev)
17815{
17816 struct net_device *dev = pci_get_drvdata(pdev);
17817 struct tg3 *tp = netdev_priv(dev);
17818
17819 rtnl_lock();
17820 netif_device_detach(dev);
17821
17822 if (netif_running(dev))
17823 dev_close(dev);
17824
17825 if (system_state == SYSTEM_POWER_OFF)
17826 tg3_power_down(tp);
17827
17828 rtnl_unlock();
17829}
17830
b45aa2f6
MC		 17831/**
17832 * tg3_io_error_detected - called when PCI error is detected
17833 * @pdev: Pointer to PCI device
17834 * @state: The current pci connection state
17835 *
17836 * This function is called after a PCI bus error affecting
17837 * this device has been detected.
17838 */
17839static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
17840 pci_channel_state_t state)
17841{
17842 struct net_device *netdev = pci_get_drvdata(pdev);
17843 struct tg3 *tp = netdev_priv(netdev);
17844 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
17845
17846 netdev_info(netdev, "PCI I/O error detected\n");
17847
17848 rtnl_lock();
17849
d8af4dfd
GS		 17850 /* We probably don't have netdev yet */
17851 if (!netdev || !netif_running(netdev))
b45aa2f6
MC		 17852 goto done;
17853
17854 tg3_phy_stop(tp);
17855
17856 tg3_netif_stop(tp);
17857
21f7638e 17858 tg3_timer_stop(tp);
b45aa2f6
MC		 17859
17860 /* Want to make sure that the reset task doesn't run */
db219973 17861 tg3_reset_task_cancel(tp);
b45aa2f6
MC		 17862
17863 netif_device_detach(netdev);
17864
17865 /* Clean up software state, even if MMIO is blocked */
17866 tg3_full_lock(tp, 0);
17867 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
17868 tg3_full_unlock(tp);
17869
17870done:
72bb72b0 17871 if (state == pci_channel_io_perm_failure) {
68293099
DB		 17872 if (netdev) {
17873 tg3_napi_enable(tp);
17874 dev_close(netdev);
17875 }
b45aa2f6 17876 err = PCI_ERS_RESULT_DISCONNECT;
72bb72b0 17877 } else {
b45aa2f6 17878 pci_disable_device(pdev);
72bb72b0 17879 }
b45aa2f6
MC		 17880
17881 rtnl_unlock();
17882
17883 return err;
17884}
17885
17886/**
17887 * tg3_io_slot_reset - called after the pci bus has been reset.
17888 * @pdev: Pointer to PCI device
17889 *
17890 * Restart the card from scratch, as if from a cold-boot.
17891 * At this point, the card has exprienced a hard reset,
17892 * followed by fixups by BIOS, and has its config space
17893 * set up identically to what it was at cold boot.
17894 */
17895static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
17896{
17897 struct net_device *netdev = pci_get_drvdata(pdev);
17898 struct tg3 *tp = netdev_priv(netdev);
17899 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
17900 int err;
17901
17902 rtnl_lock();
17903
17904 if (pci_enable_device(pdev)) {
68293099
DB		 17905 dev_err(&pdev->dev,
17906 "Cannot re-enable PCI device after reset.\n");
b45aa2f6
MC		 17907 goto done;
17908 }
17909
17910 pci_set_master(pdev);
17911 pci_restore_state(pdev);
17912 pci_save_state(pdev);
17913
68293099 17914 if (!netdev || !netif_running(netdev)) {
b45aa2f6
MC		 17915 rc = PCI_ERS_RESULT_RECOVERED;
17916 goto done;
17917 }
17918
17919 err = tg3_power_up(tp);
bed9829f 17920 if (err)
b45aa2f6 17921 goto done;
b45aa2f6
MC		 17922
17923 rc = PCI_ERS_RESULT_RECOVERED;
17924
17925done:
68293099 17926 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
72bb72b0
MC		 17927 tg3_napi_enable(tp);
17928 dev_close(netdev);
17929 }
b45aa2f6
MC		 17930 rtnl_unlock();
17931
17932 return rc;
17933}
17934
17935/**
17936 * tg3_io_resume - called when traffic can start flowing again.
17937 * @pdev: Pointer to PCI device
17938 *
17939 * This callback is called when the error recovery driver tells
17940 * us that its OK to resume normal operation.
17941 */
17942static void tg3_io_resume(struct pci_dev *pdev)
17943{
17944 struct net_device *netdev = pci_get_drvdata(pdev);
17945 struct tg3 *tp = netdev_priv(netdev);
17946 int err;
17947
17948 rtnl_lock();
17949
17950 if (!netif_running(netdev))
17951 goto done;
17952
17953 tg3_full_lock(tp, 0);
2e460fc0 17954 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
63c3a66f 17955 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 17956 err = tg3_restart_hw(tp, true);
b45aa2f6 17957 if (err) {
35763066 17958 tg3_full_unlock(tp);
b45aa2f6
MC		 17959 netdev_err(netdev, "Cannot restart hardware after reset.\n");
17960 goto done;
17961 }
17962
17963 netif_device_attach(netdev);
17964
21f7638e 17965 tg3_timer_start(tp);
b45aa2f6
MC		 17966
17967 tg3_netif_start(tp);
17968
35763066
NNS		 17969 tg3_full_unlock(tp);
17970
b45aa2f6
MC		 17971 tg3_phy_start(tp);
17972
17973done:
17974 rtnl_unlock();
17975}
17976
3646f0e5 17977static const struct pci_error_handlers tg3_err_handler = {
b45aa2f6
MC		 17978 .error_detected = tg3_io_error_detected,
17979 .slot_reset = tg3_io_slot_reset,
17980 .resume = tg3_io_resume
17981};
17982
1da177e4
LT		 17983static struct pci_driver tg3_driver = {
17984 .name = DRV_MODULE_NAME,
17985 .id_table = tg3_pci_tbl,
17986 .probe = tg3_init_one,
229b1ad1 17987 .remove = tg3_remove_one,
b45aa2f6 17988 .err_handler = &tg3_err_handler,
42df36a6 17989 .driver.pm = &tg3_pm_ops,
4c305fa2 17990 .shutdown = tg3_shutdown,
1da177e4
LT		 17991};
17992
8dbb0dc2 17993module_pci_driver(tg3_driver);
Linux kernel - Deliverables
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