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tg3: make it possible to provide phy_id in ioctl
[deliverable/linux.git] / drivers / net / ethernet / broadcom / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
b681b65d 7 * Copyright (C) 2005-2013 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
6867c843 21#include <linux/stringify.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
14c85021 27#include <linux/in.h>
1da177e4 28#include <linux/init.h>
a6b7a407 29#include <linux/interrupt.h>
1da177e4
LT		 30#include <linux/ioport.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/ethtool.h>
3110f5f5 36#include <linux/mdio.h>
1da177e4 37#include <linux/mii.h>
158d7abd 38#include <linux/phy.h>
a9daf367 39#include <linux/brcmphy.h>
1da177e4
LT		 40#include <linux/if_vlan.h>
41#include <linux/ip.h>
42#include <linux/tcp.h>
43#include <linux/workqueue.h>
61487480 44#include <linux/prefetch.h>
f9a5f7d3 45#include <linux/dma-mapping.h>
077f849d 46#include <linux/firmware.h>
aed93e0b
MC		 47#include <linux/hwmon.h>
48#include <linux/hwmon-sysfs.h>
1da177e4
LT		 49
50#include <net/checksum.h>
c9bdd4b5 51#include <net/ip.h>
1da177e4 52
27fd9de8 53#include <linux/io.h>
1da177e4 54#include <asm/byteorder.h>
27fd9de8 55#include <linux/uaccess.h>
1da177e4 56
be947307
MC		 57#include <uapi/linux/net_tstamp.h>
58#include <linux/ptp_clock_kernel.h>
59
49b6e95f 60#ifdef CONFIG_SPARC
1da177e4 61#include <asm/idprom.h>
49b6e95f 62#include <asm/prom.h>
1da177e4
LT		 63#endif
64
63532394
MC		 65#define BAR_0 0
66#define BAR_2 2
67
1da177e4
LT		 68#include "tg3.h"
69
63c3a66f
JP		 70/* Functions & macros to verify TG3_FLAGS types */
71
72static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
73{
74 return test_bit(flag, bits);
75}
76
77static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
78{
79 set_bit(flag, bits);
80}
81
82static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
83{
84 clear_bit(flag, bits);
85}
86
87#define tg3_flag(tp, flag) \
88 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
89#define tg3_flag_set(tp, flag) \
90 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
91#define tg3_flag_clear(tp, flag) \
92 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
93
1da177e4 94#define DRV_MODULE_NAME "tg3"
6867c843 95#define TG3_MAJ_NUM 3
b681b65d 96#define TG3_MIN_NUM 129
6867c843
MC		 97#define DRV_MODULE_VERSION \
98 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
b681b65d 99#define DRV_MODULE_RELDATE "January 06, 2013"
1da177e4 100
fd6d3f0e
MC		 101#define RESET_KIND_SHUTDOWN 0
102#define RESET_KIND_INIT 1
103#define RESET_KIND_SUSPEND 2
104
1da177e4
LT		 105#define TG3_DEF_RX_MODE 0
106#define TG3_DEF_TX_MODE 0
107#define TG3_DEF_MSG_ENABLE \
108 (NETIF_MSG_DRV | \
109 NETIF_MSG_PROBE | \
110 NETIF_MSG_LINK | \
111 NETIF_MSG_TIMER | \
112 NETIF_MSG_IFDOWN | \
113 NETIF_MSG_IFUP | \
114 NETIF_MSG_RX_ERR | \
115 NETIF_MSG_TX_ERR)
116
520b2756
MC		 117#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
118
1da177e4
LT		 119/* length of time before we decide the hardware is borked,
120 * and dev->tx_timeout() should be called to fix the problem
121 */
63c3a66f 122
1da177e4
LT		 123#define TG3_TX_TIMEOUT (5 * HZ)
124
125/* hardware minimum and maximum for a single frame's data payload */
126#define TG3_MIN_MTU 60
127#define TG3_MAX_MTU(tp) \
63c3a66f 128 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 129
130/* These numbers seem to be hard coded in the NIC firmware somehow.
131 * You can't change the ring sizes, but you can change where you place
132 * them in the NIC onboard memory.
133 */
7cb32cf2 134#define TG3_RX_STD_RING_SIZE(tp) \
63c3a66f 135 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 136 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
1da177e4 137#define TG3_DEF_RX_RING_PENDING 200
7cb32cf2 138#define TG3_RX_JMB_RING_SIZE(tp) \
63c3a66f 139 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 140 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
1da177e4
LT		 141#define TG3_DEF_RX_JUMBO_RING_PENDING 100
142
143/* Do not place this n-ring entries value into the tp struct itself,
144 * we really want to expose these constants to GCC so that modulo et
145 * al. operations are done with shifts and masks instead of with
146 * hw multiply/modulo instructions. Another solution would be to
147 * replace things like '% foo' with '& (foo - 1)'.
148 */
1da177e4
LT		 149
150#define TG3_TX_RING_SIZE 512
151#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
152
2c49a44d
MC		 153#define TG3_RX_STD_RING_BYTES(tp) \
154 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
155#define TG3_RX_JMB_RING_BYTES(tp) \
156 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
157#define TG3_RX_RCB_RING_BYTES(tp) \
7cb32cf2 158 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
1da177e4
LT		 159#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
160 TG3_TX_RING_SIZE)
1da177e4
LT		 161#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
162
287be12e
MC		 163#define TG3_DMA_BYTE_ENAB 64
164
165#define TG3_RX_STD_DMA_SZ 1536
166#define TG3_RX_JMB_DMA_SZ 9046
167
168#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
169
170#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
171#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 172
2c49a44d
MC		 173#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
174 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
2b2cdb65 175
2c49a44d
MC		 176#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
177 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
2b2cdb65 178
d2757fc4
MC		 179/* Due to a hardware bug, the 5701 can only DMA to memory addresses
180 * that are at least dword aligned when used in PCIX mode. The driver
181 * works around this bug by double copying the packet. This workaround
182 * is built into the normal double copy length check for efficiency.
183 *
184 * However, the double copy is only necessary on those architectures
185 * where unaligned memory accesses are inefficient. For those architectures
186 * where unaligned memory accesses incur little penalty, we can reintegrate
187 * the 5701 in the normal rx path. Doing so saves a device structure
188 * dereference by hardcoding the double copy threshold in place.
189 */
190#define TG3_RX_COPY_THRESHOLD 256
191#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
192 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
193#else
194 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
195#endif
196
81389f57
MC		 197#if (NET_IP_ALIGN != 0)
198#define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
199#else
9205fd9c 200#define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
81389f57
MC		 201#endif
202
1da177e4 203/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 204#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
55086ad9 205#define TG3_TX_BD_DMA_MAX_2K 2048
a4cb428d 206#define TG3_TX_BD_DMA_MAX_4K 4096
1da177e4 207
ad829268
MC		 208#define TG3_RAW_IP_ALIGN 2
209
c6cdf436 210#define TG3_FW_UPDATE_TIMEOUT_SEC 5
21f7638e 211#define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
c6cdf436 212
077f849d
JSR		 213#define FIRMWARE_TG3 "tigon/tg3.bin"
214#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
215#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
216
229b1ad1 217static char version[] =
05dbe005 218 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 219
220MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
221MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
222MODULE_LICENSE("GPL");
223MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 224MODULE_FIRMWARE(FIRMWARE_TG3);
225MODULE_FIRMWARE(FIRMWARE_TG3TSO);
226MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
227
1da177e4
LT		 228static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
229module_param(tg3_debug, int, 0);
230MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
231
3d567e0e
NNS		 232#define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
233#define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
234
a3aa1884 235static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
3d567e0e
NNS		 254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
255 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
256 TG3_DRV_DATA_FLAG_5705_10_100},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
258 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
259 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
3d567e0e
NNS		 261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
262 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
263 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217 266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
13185217 267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
3d567e0e
NNS		 268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
269 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
3d567e0e
NNS		 274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
275 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
3d567e0e
NNS		 283 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
284 PCI_VENDOR_ID_LENOVO,
285 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
286 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217 287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
3d567e0e
NNS		 288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
289 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
292 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
3d567e0e
NNS		 308 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
309 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
310 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
311 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
312 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
313 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321d32a0
MC		 314 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
315 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
3d567e0e
NNS		 316 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
317 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
5e7ccf20 318 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6 319 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
79d49695 320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
5001e2f6 321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
b0f75221
MC		 322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
323 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
3d567e0e
NNS		 326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
327 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
329 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
302b500b 330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
ba1f3c76 331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
02eca3f5 332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
c86a8560
MC		 333 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
335 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
13185217
HK		 336 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
337 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
338 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
339 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
340 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
341 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
342 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
1dcb14d9 343 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
13185217 344 {}
1da177e4
LT		 345};
346
347MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
348
50da859d 349static const struct {
1da177e4 350 const char string[ETH_GSTRING_LEN];
48fa55a0 351} ethtool_stats_keys[] = {
1da177e4
LT		 352 { "rx_octets" },
353 { "rx_fragments" },
354 { "rx_ucast_packets" },
355 { "rx_mcast_packets" },
356 { "rx_bcast_packets" },
357 { "rx_fcs_errors" },
358 { "rx_align_errors" },
359 { "rx_xon_pause_rcvd" },
360 { "rx_xoff_pause_rcvd" },
361 { "rx_mac_ctrl_rcvd" },
362 { "rx_xoff_entered" },
363 { "rx_frame_too_long_errors" },
364 { "rx_jabbers" },
365 { "rx_undersize_packets" },
366 { "rx_in_length_errors" },
367 { "rx_out_length_errors" },
368 { "rx_64_or_less_octet_packets" },
369 { "rx_65_to_127_octet_packets" },
370 { "rx_128_to_255_octet_packets" },
371 { "rx_256_to_511_octet_packets" },
372 { "rx_512_to_1023_octet_packets" },
373 { "rx_1024_to_1522_octet_packets" },
374 { "rx_1523_to_2047_octet_packets" },
375 { "rx_2048_to_4095_octet_packets" },
376 { "rx_4096_to_8191_octet_packets" },
377 { "rx_8192_to_9022_octet_packets" },
378
379 { "tx_octets" },
380 { "tx_collisions" },
381
382 { "tx_xon_sent" },
383 { "tx_xoff_sent" },
384 { "tx_flow_control" },
385 { "tx_mac_errors" },
386 { "tx_single_collisions" },
387 { "tx_mult_collisions" },
388 { "tx_deferred" },
389 { "tx_excessive_collisions" },
390 { "tx_late_collisions" },
391 { "tx_collide_2times" },
392 { "tx_collide_3times" },
393 { "tx_collide_4times" },
394 { "tx_collide_5times" },
395 { "tx_collide_6times" },
396 { "tx_collide_7times" },
397 { "tx_collide_8times" },
398 { "tx_collide_9times" },
399 { "tx_collide_10times" },
400 { "tx_collide_11times" },
401 { "tx_collide_12times" },
402 { "tx_collide_13times" },
403 { "tx_collide_14times" },
404 { "tx_collide_15times" },
405 { "tx_ucast_packets" },
406 { "tx_mcast_packets" },
407 { "tx_bcast_packets" },
408 { "tx_carrier_sense_errors" },
409 { "tx_discards" },
410 { "tx_errors" },
411
412 { "dma_writeq_full" },
413 { "dma_write_prioq_full" },
414 { "rxbds_empty" },
415 { "rx_discards" },
416 { "rx_errors" },
417 { "rx_threshold_hit" },
418
419 { "dma_readq_full" },
420 { "dma_read_prioq_full" },
421 { "tx_comp_queue_full" },
422
423 { "ring_set_send_prod_index" },
424 { "ring_status_update" },
425 { "nic_irqs" },
426 { "nic_avoided_irqs" },
4452d099
MC		 427 { "nic_tx_threshold_hit" },
428
429 { "mbuf_lwm_thresh_hit" },
1da177e4
LT		 430};
431
48fa55a0 432#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
93df8b8f
NNS		 433#define TG3_NVRAM_TEST 0
434#define TG3_LINK_TEST 1
435#define TG3_REGISTER_TEST 2
436#define TG3_MEMORY_TEST 3
437#define TG3_MAC_LOOPB_TEST 4
438#define TG3_PHY_LOOPB_TEST 5
439#define TG3_EXT_LOOPB_TEST 6
440#define TG3_INTERRUPT_TEST 7
48fa55a0
MC		 441
442
50da859d 443static const struct {
4cafd3f5 444 const char string[ETH_GSTRING_LEN];
48fa55a0 445} ethtool_test_keys[] = {
93df8b8f
NNS		 446 [TG3_NVRAM_TEST] = { "nvram test (online) " },
447 [TG3_LINK_TEST] = { "link test (online) " },
448 [TG3_REGISTER_TEST] = { "register test (offline)" },
449 [TG3_MEMORY_TEST] = { "memory test (offline)" },
450 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
451 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
452 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
453 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
4cafd3f5
MC		 454};
455
48fa55a0
MC		 456#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
457
458
b401e9e2
MC		 459static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
460{
461 writel(val, tp->regs + off);
462}
463
464static u32 tg3_read32(struct tg3 *tp, u32 off)
465{
de6f31eb 466 return readl(tp->regs + off);
b401e9e2
MC		 467}
468
0d3031d9
MC		 469static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
470{
471 writel(val, tp->aperegs + off);
472}
473
474static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
475{
de6f31eb 476 return readl(tp->aperegs + off);
0d3031d9
MC		 477}
478
1da177e4
LT		 479static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
480{
6892914f
MC		 481 unsigned long flags;
482
483 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 484 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
485 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 486 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 487}
488
489static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
490{
491 writel(val, tp->regs + off);
492 readl(tp->regs + off);
1da177e4
LT		 493}
494
6892914f 495static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 496{
6892914f
MC		 497 unsigned long flags;
498 u32 val;
499
500 spin_lock_irqsave(&tp->indirect_lock, flags);
501 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
502 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
503 spin_unlock_irqrestore(&tp->indirect_lock, flags);
504 return val;
505}
506
507static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
508{
509 unsigned long flags;
510
511 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
512 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
513 TG3_64BIT_REG_LOW, val);
514 return;
515 }
66711e66 516 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 517 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
518 TG3_64BIT_REG_LOW, val);
519 return;
1da177e4 520 }
6892914f
MC		 521
522 spin_lock_irqsave(&tp->indirect_lock, flags);
523 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
524 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
525 spin_unlock_irqrestore(&tp->indirect_lock, flags);
526
527 /* In indirect mode when disabling interrupts, we also need
528 * to clear the interrupt bit in the GRC local ctrl register.
529 */
530 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
531 (val == 0x1)) {
532 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
533 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
534 }
535}
536
537static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
538{
539 unsigned long flags;
540 u32 val;
541
542 spin_lock_irqsave(&tp->indirect_lock, flags);
543 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
544 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
545 spin_unlock_irqrestore(&tp->indirect_lock, flags);
546 return val;
547}
548
b401e9e2
MC		 549/* usec_wait specifies the wait time in usec when writing to certain registers
550 * where it is unsafe to read back the register without some delay.
551 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
552 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
553 */
554static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 555{
63c3a66f 556 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
b401e9e2
MC		 557 /* Non-posted methods */
558 tp->write32(tp, off, val);
559 else {
560 /* Posted method */
561 tg3_write32(tp, off, val);
562 if (usec_wait)
563 udelay(usec_wait);
564 tp->read32(tp, off);
565 }
566 /* Wait again after the read for the posted method to guarantee that
567 * the wait time is met.
568 */
569 if (usec_wait)
570 udelay(usec_wait);
1da177e4
LT		 571}
572
09ee929c
MC		 573static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
574{
575 tp->write32_mbox(tp, off, val);
63c3a66f 576 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
6892914f 577 tp->read32_mbox(tp, off);
09ee929c
MC		 578}
579
20094930 580static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 581{
582 void __iomem *mbox = tp->regs + off;
583 writel(val, mbox);
63c3a66f 584 if (tg3_flag(tp, TXD_MBOX_HWBUG))
1da177e4 585 writel(val, mbox);
63c3a66f 586 if (tg3_flag(tp, MBOX_WRITE_REORDER))
1da177e4
LT		 587 readl(mbox);
588}
589
b5d3772c
MC		 590static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
591{
de6f31eb 592 return readl(tp->regs + off + GRCMBOX_BASE);
b5d3772c
MC		 593}
594
595static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
596{
597 writel(val, tp->regs + off + GRCMBOX_BASE);
598}
599
c6cdf436 600#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 601#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
c6cdf436
MC		 602#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
603#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
604#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930 605
c6cdf436
MC		 606#define tw32(reg, val) tp->write32(tp, reg, val)
607#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
608#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
609#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 610
611static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
612{
6892914f
MC		 613 unsigned long flags;
614
6ff6f81d 615 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
b5d3772c
MC		 616 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
617 return;
618
6892914f 619 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 620 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 621 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
622 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 623
bbadf503
MC		 624 /* Always leave this as zero. */
625 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
626 } else {
627 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
628 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 629
bbadf503
MC		 630 /* Always leave this as zero. */
631 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
632 }
633 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 634}
635
1da177e4
LT		 636static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
637{
6892914f
MC		 638 unsigned long flags;
639
6ff6f81d 640 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
b5d3772c
MC		 641 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
642 *val = 0;
643 return;
644 }
645
6892914f 646 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 647 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 648 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
649 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 650
bbadf503
MC		 651 /* Always leave this as zero. */
652 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
653 } else {
654 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
655 *val = tr32(TG3PCI_MEM_WIN_DATA);
656
657 /* Always leave this as zero. */
658 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
659 }
6892914f 660 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 661}
662
0d3031d9
MC		 663static void tg3_ape_lock_init(struct tg3 *tp)
664{
665 int i;
6f5c8f83 666 u32 regbase, bit;
f92d9dc1
MC		 667
668 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
669 regbase = TG3_APE_LOCK_GRANT;
670 else
671 regbase = TG3_APE_PER_LOCK_GRANT;
0d3031d9
MC		 672
673 /* Make sure the driver hasn't any stale locks. */
78f94dc7
MC		 674 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
675 switch (i) {
676 case TG3_APE_LOCK_PHY0:
677 case TG3_APE_LOCK_PHY1:
678 case TG3_APE_LOCK_PHY2:
679 case TG3_APE_LOCK_PHY3:
680 bit = APE_LOCK_GRANT_DRIVER;
681 break;
682 default:
683 if (!tp->pci_fn)
684 bit = APE_LOCK_GRANT_DRIVER;
685 else
686 bit = 1 << tp->pci_fn;
687 }
688 tg3_ape_write32(tp, regbase + 4 * i, bit);
6f5c8f83
MC		 689 }
690
0d3031d9
MC		 691}
692
693static int tg3_ape_lock(struct tg3 *tp, int locknum)
694{
695 int i, off;
696 int ret = 0;
6f5c8f83 697 u32 status, req, gnt, bit;
0d3031d9 698
63c3a66f 699 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 700 return 0;
701
702 switch (locknum) {
6f5c8f83
MC		 703 case TG3_APE_LOCK_GPIO:
704 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
705 return 0;
33f401ae
MC		 706 case TG3_APE_LOCK_GRC:
707 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 708 if (!tp->pci_fn)
709 bit = APE_LOCK_REQ_DRIVER;
710 else
711 bit = 1 << tp->pci_fn;
33f401ae 712 break;
8151ad57
MC		 713 case TG3_APE_LOCK_PHY0:
714 case TG3_APE_LOCK_PHY1:
715 case TG3_APE_LOCK_PHY2:
716 case TG3_APE_LOCK_PHY3:
717 bit = APE_LOCK_REQ_DRIVER;
718 break;
33f401ae
MC		 719 default:
720 return -EINVAL;
0d3031d9
MC		 721 }
722
f92d9dc1
MC		 723 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
724 req = TG3_APE_LOCK_REQ;
725 gnt = TG3_APE_LOCK_GRANT;
726 } else {
727 req = TG3_APE_PER_LOCK_REQ;
728 gnt = TG3_APE_PER_LOCK_GRANT;
729 }
730
0d3031d9
MC		 731 off = 4 * locknum;
732
6f5c8f83 733 tg3_ape_write32(tp, req + off, bit);
0d3031d9
MC		 734
735 /* Wait for up to 1 millisecond to acquire lock. */
736 for (i = 0; i < 100; i++) {
f92d9dc1 737 status = tg3_ape_read32(tp, gnt + off);
6f5c8f83 738 if (status == bit)
0d3031d9
MC		 739 break;
740 udelay(10);
741 }
742
6f5c8f83 743 if (status != bit) {
0d3031d9 744 /* Revoke the lock request. */
6f5c8f83 745 tg3_ape_write32(tp, gnt + off, bit);
0d3031d9
MC		 746 ret = -EBUSY;
747 }
748
749 return ret;
750}
751
752static void tg3_ape_unlock(struct tg3 *tp, int locknum)
753{
6f5c8f83 754 u32 gnt, bit;
0d3031d9 755
63c3a66f 756 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 757 return;
758
759 switch (locknum) {
6f5c8f83
MC		 760 case TG3_APE_LOCK_GPIO:
761 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
762 return;
33f401ae
MC		 763 case TG3_APE_LOCK_GRC:
764 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 765 if (!tp->pci_fn)
766 bit = APE_LOCK_GRANT_DRIVER;
767 else
768 bit = 1 << tp->pci_fn;
33f401ae 769 break;
8151ad57
MC		 770 case TG3_APE_LOCK_PHY0:
771 case TG3_APE_LOCK_PHY1:
772 case TG3_APE_LOCK_PHY2:
773 case TG3_APE_LOCK_PHY3:
774 bit = APE_LOCK_GRANT_DRIVER;
775 break;
33f401ae
MC		 776 default:
777 return;
0d3031d9
MC		 778 }
779
f92d9dc1
MC		 780 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
781 gnt = TG3_APE_LOCK_GRANT;
782 else
783 gnt = TG3_APE_PER_LOCK_GRANT;
784
6f5c8f83 785 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
0d3031d9
MC		 786}
787
b65a372b 788static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
fd6d3f0e 789{
fd6d3f0e
MC		 790 u32 apedata;
791
b65a372b
MC		 792 while (timeout_us) {
793 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
794 return -EBUSY;
795
796 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
797 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
798 break;
799
800 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
801
802 udelay(10);
803 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
804 }
805
806 return timeout_us ? 0 : -EBUSY;
807}
808
cf8d55ae
MC		 809static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
810{
811 u32 i, apedata;
812
813 for (i = 0; i < timeout_us / 10; i++) {
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
815
816 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
817 break;
818
819 udelay(10);
820 }
821
822 return i == timeout_us / 10;
823}
824
86449944
MC		 825static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
826 u32 len)
cf8d55ae
MC		 827{
828 int err;
829 u32 i, bufoff, msgoff, maxlen, apedata;
830
831 if (!tg3_flag(tp, APE_HAS_NCSI))
832 return 0;
833
834 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
835 if (apedata != APE_SEG_SIG_MAGIC)
836 return -ENODEV;
837
838 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
839 if (!(apedata & APE_FW_STATUS_READY))
840 return -EAGAIN;
841
842 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
843 TG3_APE_SHMEM_BASE;
844 msgoff = bufoff + 2 * sizeof(u32);
845 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
846
847 while (len) {
848 u32 length;
849
850 /* Cap xfer sizes to scratchpad limits. */
851 length = (len > maxlen) ? maxlen : len;
852 len -= length;
853
854 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
855 if (!(apedata & APE_FW_STATUS_READY))
856 return -EAGAIN;
857
858 /* Wait for up to 1 msec for APE to service previous event. */
859 err = tg3_ape_event_lock(tp, 1000);
860 if (err)
861 return err;
862
863 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
864 APE_EVENT_STATUS_SCRTCHPD_READ |
865 APE_EVENT_STATUS_EVENT_PENDING;
866 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
867
868 tg3_ape_write32(tp, bufoff, base_off);
869 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
870
871 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
872 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
873
874 base_off += length;
875
876 if (tg3_ape_wait_for_event(tp, 30000))
877 return -EAGAIN;
878
879 for (i = 0; length; i += 4, length -= 4) {
880 u32 val = tg3_ape_read32(tp, msgoff + i);
881 memcpy(data, &val, sizeof(u32));
882 data++;
883 }
884 }
885
886 return 0;
887}
888
b65a372b
MC		 889static int tg3_ape_send_event(struct tg3 *tp, u32 event)
890{
891 int err;
892 u32 apedata;
fd6d3f0e
MC		 893
894 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
895 if (apedata != APE_SEG_SIG_MAGIC)
b65a372b 896 return -EAGAIN;
fd6d3f0e
MC		 897
898 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
899 if (!(apedata & APE_FW_STATUS_READY))
b65a372b 900 return -EAGAIN;
fd6d3f0e
MC		 901
902 /* Wait for up to 1 millisecond for APE to service previous event. */
b65a372b
MC		 903 err = tg3_ape_event_lock(tp, 1000);
904 if (err)
905 return err;
fd6d3f0e 906
b65a372b
MC		 907 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
908 event | APE_EVENT_STATUS_EVENT_PENDING);
fd6d3f0e 909
b65a372b
MC		 910 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
911 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
fd6d3f0e 912
b65a372b 913 return 0;
fd6d3f0e
MC		 914}
915
916static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
917{
918 u32 event;
919 u32 apedata;
920
921 if (!tg3_flag(tp, ENABLE_APE))
922 return;
923
924 switch (kind) {
925 case RESET_KIND_INIT:
926 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
927 APE_HOST_SEG_SIG_MAGIC);
928 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
929 APE_HOST_SEG_LEN_MAGIC);
930 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
931 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
932 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
933 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
934 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
935 APE_HOST_BEHAV_NO_PHYLOCK);
936 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
937 TG3_APE_HOST_DRVR_STATE_START);
938
939 event = APE_EVENT_STATUS_STATE_START;
940 break;
941 case RESET_KIND_SHUTDOWN:
942 /* With the interface we are currently using,
943 * APE does not track driver state. Wiping
944 * out the HOST SEGMENT SIGNATURE forces
945 * the APE to assume OS absent status.
946 */
947 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
948
949 if (device_may_wakeup(&tp->pdev->dev) &&
950 tg3_flag(tp, WOL_ENABLE)) {
951 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
952 TG3_APE_HOST_WOL_SPEED_AUTO);
953 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
954 } else
955 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
956
957 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
958
959 event = APE_EVENT_STATUS_STATE_UNLOAD;
960 break;
961 case RESET_KIND_SUSPEND:
962 event = APE_EVENT_STATUS_STATE_SUSPEND;
963 break;
964 default:
965 return;
966 }
967
968 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
969
970 tg3_ape_send_event(tp, event);
971}
972
1da177e4
LT		 973static void tg3_disable_ints(struct tg3 *tp)
974{
89aeb3bc
MC		 975 int i;
976
1da177e4
LT		 977 tw32(TG3PCI_MISC_HOST_CTRL,
978 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 979 for (i = 0; i < tp->irq_max; i++)
980 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 981}
982
1da177e4
LT		 983static void tg3_enable_ints(struct tg3 *tp)
984{
89aeb3bc 985 int i;
89aeb3bc 986
bbe832c0
MC		 987 tp->irq_sync = 0;
988 wmb();
989
1da177e4
LT		 990 tw32(TG3PCI_MISC_HOST_CTRL,
991 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 992
f89f38b8 993 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 994 for (i = 0; i < tp->irq_cnt; i++) {
995 struct tg3_napi *tnapi = &tp->napi[i];
c6cdf436 996
898a56f8 997 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
63c3a66f 998 if (tg3_flag(tp, 1SHOT_MSI))
89aeb3bc 999 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 1000
f89f38b8 1001 tp->coal_now |= tnapi->coal_now;
89aeb3bc 1002 }
f19af9c2
MC		 1003
1004 /* Force an initial interrupt */
63c3a66f 1005 if (!tg3_flag(tp, TAGGED_STATUS) &&
f19af9c2
MC		 1006 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1007 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1008 else
f89f38b8
MC		 1009 tw32(HOSTCC_MODE, tp->coal_now);
1010
1011 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 1012}
1013
17375d25 1014static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 1015{
17375d25 1016 struct tg3 *tp = tnapi->tp;
898a56f8 1017 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 1018 unsigned int work_exists = 0;
1019
1020 /* check for phy events */
63c3a66f 1021 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
04237ddd
MC		 1022 if (sblk->status & SD_STATUS_LINK_CHG)
1023 work_exists = 1;
1024 }
f891ea16
MC		 1025
1026 /* check for TX work to do */
1027 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1028 work_exists = 1;
1029
1030 /* check for RX work to do */
1031 if (tnapi->rx_rcb_prod_idx &&
8d9d7cfc 1032 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 1033 work_exists = 1;
1034
1035 return work_exists;
1036}
1037
17375d25 1038/* tg3_int_reenable
04237ddd
MC		 1039 * similar to tg3_enable_ints, but it accurately determines whether there
1040 * is new work pending and can return without flushing the PIO write
6aa20a22 1041 * which reenables interrupts
1da177e4 1042 */
17375d25 1043static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 1044{
17375d25
MC		 1045 struct tg3 *tp = tnapi->tp;
1046
898a56f8 1047 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 1048 mmiowb();
1049
fac9b83e
DM		 1050 /* When doing tagged status, this work check is unnecessary.
1051 * The last_tag we write above tells the chip which piece of
1052 * work we've completed.
1053 */
63c3a66f 1054 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
04237ddd 1055 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 1056 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 1057}
1058
1da177e4
LT		 1059static void tg3_switch_clocks(struct tg3 *tp)
1060{
f6eb9b1f 1061 u32 clock_ctrl;
1da177e4
LT		 1062 u32 orig_clock_ctrl;
1063
63c3a66f 1064 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
4cf78e4f
MC		 1065 return;
1066
f6eb9b1f
MC		 1067 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1068
1da177e4
LT		 1069 orig_clock_ctrl = clock_ctrl;
1070 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1071 CLOCK_CTRL_CLKRUN_OENABLE |
1072 0x1f);
1073 tp->pci_clock_ctrl = clock_ctrl;
1074
63c3a66f 1075 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4 1076 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 1077 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1078 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 1079 }
1080 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 1081 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1082 clock_ctrl |
1083 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1084 40);
1085 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1086 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1087 40);
1da177e4 1088 }
b401e9e2 1089 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 1090}
1091
1092#define PHY_BUSY_LOOPS 5000
1093
5c358045
HM		 1094static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1095 u32 *val)
1da177e4
LT		 1096{
1097 u32 frame_val;
1098 unsigned int loops;
1099 int ret;
1100
1101 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1102 tw32_f(MAC_MI_MODE,
1103 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1104 udelay(80);
1105 }
1106
8151ad57
MC		 1107 tg3_ape_lock(tp, tp->phy_ape_lock);
1108
1da177e4
LT		 1109 *val = 0x0;
1110
5c358045 1111 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1112 MI_COM_PHY_ADDR_MASK);
1113 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1114 MI_COM_REG_ADDR_MASK);
1115 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 1116
1da177e4
LT		 1117 tw32_f(MAC_MI_COM, frame_val);
1118
1119 loops = PHY_BUSY_LOOPS;
1120 while (loops != 0) {
1121 udelay(10);
1122 frame_val = tr32(MAC_MI_COM);
1123
1124 if ((frame_val & MI_COM_BUSY) == 0) {
1125 udelay(5);
1126 frame_val = tr32(MAC_MI_COM);
1127 break;
1128 }
1129 loops -= 1;
1130 }
1131
1132 ret = -EBUSY;
1133 if (loops != 0) {
1134 *val = frame_val & MI_COM_DATA_MASK;
1135 ret = 0;
1136 }
1137
1138 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1139 tw32_f(MAC_MI_MODE, tp->mi_mode);
1140 udelay(80);
1141 }
1142
8151ad57
MC		 1143 tg3_ape_unlock(tp, tp->phy_ape_lock);
1144
1da177e4
LT		 1145 return ret;
1146}
1147
5c358045
HM		 1148static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1149{
1150 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1151}
1152
1153static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1154 u32 val)
1da177e4
LT		 1155{
1156 u32 frame_val;
1157 unsigned int loops;
1158 int ret;
1159
f07e9af3 1160 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
221c5637 1161 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
b5d3772c
MC		 1162 return 0;
1163
1da177e4
LT		 1164 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1165 tw32_f(MAC_MI_MODE,
1166 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1167 udelay(80);
1168 }
1169
8151ad57
MC		 1170 tg3_ape_lock(tp, tp->phy_ape_lock);
1171
5c358045 1172 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1173 MI_COM_PHY_ADDR_MASK);
1174 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1175 MI_COM_REG_ADDR_MASK);
1176 frame_val |= (val & MI_COM_DATA_MASK);
1177 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 1178
1da177e4
LT		 1179 tw32_f(MAC_MI_COM, frame_val);
1180
1181 loops = PHY_BUSY_LOOPS;
1182 while (loops != 0) {
1183 udelay(10);
1184 frame_val = tr32(MAC_MI_COM);
1185 if ((frame_val & MI_COM_BUSY) == 0) {
1186 udelay(5);
1187 frame_val = tr32(MAC_MI_COM);
1188 break;
1189 }
1190 loops -= 1;
1191 }
1192
1193 ret = -EBUSY;
1194 if (loops != 0)
1195 ret = 0;
1196
1197 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1198 tw32_f(MAC_MI_MODE, tp->mi_mode);
1199 udelay(80);
1200 }
1201
8151ad57
MC		 1202 tg3_ape_unlock(tp, tp->phy_ape_lock);
1203
1da177e4
LT		 1204 return ret;
1205}
1206
5c358045
HM		 1207static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1208{
1209 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1210}
1211
b0988c15
MC		 1212static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1213{
1214 int err;
1215
1216 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1217 if (err)
1218 goto done;
1219
1220 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1221 if (err)
1222 goto done;
1223
1224 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1225 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1226 if (err)
1227 goto done;
1228
1229 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1230
1231done:
1232 return err;
1233}
1234
1235static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1236{
1237 int err;
1238
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1240 if (err)
1241 goto done;
1242
1243 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1244 if (err)
1245 goto done;
1246
1247 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1248 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1249 if (err)
1250 goto done;
1251
1252 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1253
1254done:
1255 return err;
1256}
1257
1258static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1259{
1260 int err;
1261
1262 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1263 if (!err)
1264 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1265
1266 return err;
1267}
1268
1269static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1270{
1271 int err;
1272
1273 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1274 if (!err)
1275 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1276
1277 return err;
1278}
1279
15ee95c3
MC		 1280static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1281{
1282 int err;
1283
1284 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1285 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1286 MII_TG3_AUXCTL_SHDWSEL_MISC);
1287 if (!err)
1288 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1289
1290 return err;
1291}
1292
b4bd2929
MC		 1293static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1294{
1295 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1296 set |= MII_TG3_AUXCTL_MISC_WREN;
1297
1298 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1299}
1300
daf3ec68
NNS		 1301static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1302{
1303 u32 val;
1304 int err;
1d36ba45 1305
daf3ec68 1306 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1d36ba45 1307
daf3ec68
NNS		 1308 if (err)
1309 return err;
1310 if (enable)
1311
1312 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1313 else
1314 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1315
1316 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1317 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1318
1319 return err;
1320}
1d36ba45 1321
95e2869a
MC		 1322static int tg3_bmcr_reset(struct tg3 *tp)
1323{
1324 u32 phy_control;
1325 int limit, err;
1326
1327 /* OK, reset it, and poll the BMCR_RESET bit until it
1328 * clears or we time out.
1329 */
1330 phy_control = BMCR_RESET;
1331 err = tg3_writephy(tp, MII_BMCR, phy_control);
1332 if (err != 0)
1333 return -EBUSY;
1334
1335 limit = 5000;
1336 while (limit--) {
1337 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1338 if (err != 0)
1339 return -EBUSY;
1340
1341 if ((phy_control & BMCR_RESET) == 0) {
1342 udelay(40);
1343 break;
1344 }
1345 udelay(10);
1346 }
d4675b52 1347 if (limit < 0)
95e2869a
MC		 1348 return -EBUSY;
1349
1350 return 0;
1351}
1352
158d7abd
MC		 1353static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1354{
3d16543d 1355 struct tg3 *tp = bp->priv;
158d7abd
MC		 1356 u32 val;
1357
24bb4fb6 1358 spin_lock_bh(&tp->lock);
158d7abd
MC		 1359
1360 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 1361 val = -EIO;
1362
1363 spin_unlock_bh(&tp->lock);
158d7abd
MC		 1364
1365 return val;
1366}
1367
1368static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1369{
3d16543d 1370 struct tg3 *tp = bp->priv;
24bb4fb6 1371 u32 ret = 0;
158d7abd 1372
24bb4fb6 1373 spin_lock_bh(&tp->lock);
158d7abd
MC		 1374
1375 if (tg3_writephy(tp, reg, val))
24bb4fb6 1376 ret = -EIO;
158d7abd 1377
24bb4fb6
MC		 1378 spin_unlock_bh(&tp->lock);
1379
1380 return ret;
158d7abd
MC		 1381}
1382
1383static int tg3_mdio_reset(struct mii_bus *bp)
1384{
1385 return 0;
1386}
1387
9c61d6bc 1388static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 1389{
1390 u32 val;
fcb389df 1391 struct phy_device *phydev;
a9daf367 1392
3f0e3ad7 1393 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df 1394 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 1395 case PHY_ID_BCM50610:
1396 case PHY_ID_BCM50610M:
fcb389df
MC		 1397 val = MAC_PHYCFG2_50610_LED_MODES;
1398 break;
6a443a0f 1399 case PHY_ID_BCMAC131:
fcb389df
MC		 1400 val = MAC_PHYCFG2_AC131_LED_MODES;
1401 break;
6a443a0f 1402 case PHY_ID_RTL8211C:
fcb389df
MC		 1403 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1404 break;
6a443a0f 1405 case PHY_ID_RTL8201E:
fcb389df
MC		 1406 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1407 break;
1408 default:
a9daf367 1409 return;
fcb389df
MC		 1410 }
1411
1412 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1413 tw32(MAC_PHYCFG2, val);
1414
1415 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 1416 val &= ~(MAC_PHYCFG1_RGMII_INT |
1417 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1418 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 1419 tw32(MAC_PHYCFG1, val);
1420
1421 return;
1422 }
1423
63c3a66f 1424 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
fcb389df
MC		 1425 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1426 MAC_PHYCFG2_FMODE_MASK_MASK |
1427 MAC_PHYCFG2_GMODE_MASK_MASK |
1428 MAC_PHYCFG2_ACT_MASK_MASK |
1429 MAC_PHYCFG2_QUAL_MASK_MASK |
1430 MAC_PHYCFG2_INBAND_ENABLE;
1431
1432 tw32(MAC_PHYCFG2, val);
a9daf367 1433
bb85fbb6
MC		 1434 val = tr32(MAC_PHYCFG1);
1435 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1436 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
63c3a66f
JP		 1437 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1438 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1439 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
63c3a66f 1440 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1441 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1442 }
bb85fbb6
MC		 1443 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1444 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1445 tw32(MAC_PHYCFG1, val);
a9daf367 1446
a9daf367
MC		 1447 val = tr32(MAC_EXT_RGMII_MODE);
1448 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1449 MAC_RGMII_MODE_RX_QUALITY |
1450 MAC_RGMII_MODE_RX_ACTIVITY |
1451 MAC_RGMII_MODE_RX_ENG_DET |
1452 MAC_RGMII_MODE_TX_ENABLE |
1453 MAC_RGMII_MODE_TX_LOWPWR |
1454 MAC_RGMII_MODE_TX_RESET);
63c3a66f
JP		 1455 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1456 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367
MC		 1457 val |= MAC_RGMII_MODE_RX_INT_B |
1458 MAC_RGMII_MODE_RX_QUALITY |
1459 MAC_RGMII_MODE_RX_ACTIVITY |
1460 MAC_RGMII_MODE_RX_ENG_DET;
63c3a66f 1461 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1462 val |= MAC_RGMII_MODE_TX_ENABLE |
1463 MAC_RGMII_MODE_TX_LOWPWR |
1464 MAC_RGMII_MODE_TX_RESET;
1465 }
1466 tw32(MAC_EXT_RGMII_MODE, val);
1467}
1468
158d7abd
MC		 1469static void tg3_mdio_start(struct tg3 *tp)
1470{
158d7abd
MC		 1471 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1472 tw32_f(MAC_MI_MODE, tp->mi_mode);
1473 udelay(80);
a9daf367 1474
63c3a66f 1475 if (tg3_flag(tp, MDIOBUS_INITED) &&
9ea4818d
MC		 1476 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1477 tg3_mdio_config_5785(tp);
1478}
1479
1480static int tg3_mdio_init(struct tg3 *tp)
1481{
1482 int i;
1483 u32 reg;
1484 struct phy_device *phydev;
1485
63c3a66f 1486 if (tg3_flag(tp, 5717_PLUS)) {
9c7df915 1487 u32 is_serdes;
882e9793 1488
69f11c99 1489 tp->phy_addr = tp->pci_fn + 1;
882e9793 1490
d1ec96af
MC		 1491 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1492 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1493 else
1494 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1495 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1496 if (is_serdes)
1497 tp->phy_addr += 7;
1498 } else
3f0e3ad7 1499 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1500
158d7abd
MC		 1501 tg3_mdio_start(tp);
1502
63c3a66f 1503 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
158d7abd
MC		 1504 return 0;
1505
298cf9be
LB		 1506 tp->mdio_bus = mdiobus_alloc();
1507 if (tp->mdio_bus == NULL)
1508 return -ENOMEM;
158d7abd 1509
298cf9be
LB		 1510 tp->mdio_bus->name = "tg3 mdio bus";
1511 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1512 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1513 tp->mdio_bus->priv = tp;
1514 tp->mdio_bus->parent = &tp->pdev->dev;
1515 tp->mdio_bus->read = &tg3_mdio_read;
1516 tp->mdio_bus->write = &tg3_mdio_write;
1517 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1518 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1519 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1520
1521 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1522 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1523
1524 /* The bus registration will look for all the PHYs on the mdio bus.
1525 * Unfortunately, it does not ensure the PHY is powered up before
1526 * accessing the PHY ID registers. A chip reset is the
1527 * quickest way to bring the device back to an operational state..
1528 */
1529 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1530 tg3_bmcr_reset(tp);
1531
298cf9be 1532 i = mdiobus_register(tp->mdio_bus);
a9daf367 1533 if (i) {
ab96b241 1534 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1535 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1536 return i;
1537 }
158d7abd 1538
3f0e3ad7 1539 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1540
9c61d6bc 1541 if (!phydev || !phydev->drv) {
ab96b241 1542 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1543 mdiobus_unregister(tp->mdio_bus);
1544 mdiobus_free(tp->mdio_bus);
1545 return -ENODEV;
1546 }
1547
1548 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1549 case PHY_ID_BCM57780:
321d32a0 1550 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1551 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1552 break;
6a443a0f
MC		 1553 case PHY_ID_BCM50610:
1554 case PHY_ID_BCM50610M:
32e5a8d6 1555 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1556 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1557 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1558 PHY_BRCM_AUTO_PWRDWN_ENABLE;
63c3a66f 1559 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
a9daf367 1560 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
63c3a66f 1561 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1562 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
63c3a66f 1563 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367 1564 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1565 /* fallthru */
6a443a0f 1566 case PHY_ID_RTL8211C:
fcb389df 1567 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1568 break;
6a443a0f
MC		 1569 case PHY_ID_RTL8201E:
1570 case PHY_ID_BCMAC131:
a9daf367 1571 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1572 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
f07e9af3 1573 tp->phy_flags |= TG3_PHYFLG_IS_FET;
a9daf367
MC		 1574 break;
1575 }
1576
63c3a66f 1577 tg3_flag_set(tp, MDIOBUS_INITED);
9c61d6bc
MC		 1578
1579 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1580 tg3_mdio_config_5785(tp);
a9daf367
MC		 1581
1582 return 0;
158d7abd
MC		 1583}
1584
1585static void tg3_mdio_fini(struct tg3 *tp)
1586{
63c3a66f
JP		 1587 if (tg3_flag(tp, MDIOBUS_INITED)) {
1588 tg3_flag_clear(tp, MDIOBUS_INITED);
298cf9be
LB		 1589 mdiobus_unregister(tp->mdio_bus);
1590 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1591 }
1592}
1593
4ba526ce
MC		 1594/* tp->lock is held. */
1595static inline void tg3_generate_fw_event(struct tg3 *tp)
1596{
1597 u32 val;
1598
1599 val = tr32(GRC_RX_CPU_EVENT);
1600 val |= GRC_RX_CPU_DRIVER_EVENT;
1601 tw32_f(GRC_RX_CPU_EVENT, val);
1602
1603 tp->last_event_jiffies = jiffies;
1604}
1605
1606#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1607
95e2869a
MC		 1608/* tp->lock is held. */
1609static void tg3_wait_for_event_ack(struct tg3 *tp)
1610{
1611 int i;
4ba526ce
MC		 1612 unsigned int delay_cnt;
1613 long time_remain;
1614
1615 /* If enough time has passed, no wait is necessary. */
1616 time_remain = (long)(tp->last_event_jiffies + 1 +
1617 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1618 (long)jiffies;
1619 if (time_remain < 0)
1620 return;
1621
1622 /* Check if we can shorten the wait time. */
1623 delay_cnt = jiffies_to_usecs(time_remain);
1624 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1625 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1626 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1627
4ba526ce 1628 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1629 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1630 break;
4ba526ce 1631 udelay(8);
95e2869a
MC		 1632 }
1633}
1634
1635/* tp->lock is held. */
b28f389d 1636static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
95e2869a 1637{
b28f389d 1638 u32 reg, val;
95e2869a
MC		 1639
1640 val = 0;
1641 if (!tg3_readphy(tp, MII_BMCR, &reg))
1642 val = reg << 16;
1643 if (!tg3_readphy(tp, MII_BMSR, &reg))
1644 val |= (reg & 0xffff);
b28f389d 1645 *data++ = val;
95e2869a
MC		 1646
1647 val = 0;
1648 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1649 val = reg << 16;
1650 if (!tg3_readphy(tp, MII_LPA, &reg))
1651 val |= (reg & 0xffff);
b28f389d 1652 *data++ = val;
95e2869a
MC		 1653
1654 val = 0;
f07e9af3 1655 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
95e2869a
MC		 1656 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1657 val = reg << 16;
1658 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1659 val |= (reg & 0xffff);
1660 }
b28f389d 1661 *data++ = val;
95e2869a
MC		 1662
1663 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1664 val = reg << 16;
1665 else
1666 val = 0;
b28f389d
MC		 1667 *data++ = val;
1668}
1669
1670/* tp->lock is held. */
1671static void tg3_ump_link_report(struct tg3 *tp)
1672{
1673 u32 data[4];
1674
1675 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1676 return;
1677
1678 tg3_phy_gather_ump_data(tp, data);
1679
1680 tg3_wait_for_event_ack(tp);
1681
1682 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1683 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1684 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1685 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1686 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1687 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
95e2869a 1688
4ba526ce 1689 tg3_generate_fw_event(tp);
95e2869a
MC		 1690}
1691
8d5a89b3
MC		 1692/* tp->lock is held. */
1693static void tg3_stop_fw(struct tg3 *tp)
1694{
1695 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1696 /* Wait for RX cpu to ACK the previous event. */
1697 tg3_wait_for_event_ack(tp);
1698
1699 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1700
1701 tg3_generate_fw_event(tp);
1702
1703 /* Wait for RX cpu to ACK this event. */
1704 tg3_wait_for_event_ack(tp);
1705 }
1706}
1707
fd6d3f0e
MC		 1708/* tp->lock is held. */
1709static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1710{
1711 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1712 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1713
1714 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1715 switch (kind) {
1716 case RESET_KIND_INIT:
1717 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1718 DRV_STATE_START);
1719 break;
1720
1721 case RESET_KIND_SHUTDOWN:
1722 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1723 DRV_STATE_UNLOAD);
1724 break;
1725
1726 case RESET_KIND_SUSPEND:
1727 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1728 DRV_STATE_SUSPEND);
1729 break;
1730
1731 default:
1732 break;
1733 }
1734 }
1735
1736 if (kind == RESET_KIND_INIT ||
1737 kind == RESET_KIND_SUSPEND)
1738 tg3_ape_driver_state_change(tp, kind);
1739}
1740
1741/* tp->lock is held. */
1742static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1743{
1744 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1745 switch (kind) {
1746 case RESET_KIND_INIT:
1747 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1748 DRV_STATE_START_DONE);
1749 break;
1750
1751 case RESET_KIND_SHUTDOWN:
1752 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1753 DRV_STATE_UNLOAD_DONE);
1754 break;
1755
1756 default:
1757 break;
1758 }
1759 }
1760
1761 if (kind == RESET_KIND_SHUTDOWN)
1762 tg3_ape_driver_state_change(tp, kind);
1763}
1764
1765/* tp->lock is held. */
1766static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1767{
1768 if (tg3_flag(tp, ENABLE_ASF)) {
1769 switch (kind) {
1770 case RESET_KIND_INIT:
1771 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1772 DRV_STATE_START);
1773 break;
1774
1775 case RESET_KIND_SHUTDOWN:
1776 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1777 DRV_STATE_UNLOAD);
1778 break;
1779
1780 case RESET_KIND_SUSPEND:
1781 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1782 DRV_STATE_SUSPEND);
1783 break;
1784
1785 default:
1786 break;
1787 }
1788 }
1789}
1790
1791static int tg3_poll_fw(struct tg3 *tp)
1792{
1793 int i;
1794 u32 val;
1795
1796 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1797 /* Wait up to 20ms for init done. */
1798 for (i = 0; i < 200; i++) {
1799 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1800 return 0;
1801 udelay(100);
1802 }
1803 return -ENODEV;
1804 }
1805
1806 /* Wait for firmware initialization to complete. */
1807 for (i = 0; i < 100000; i++) {
1808 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1809 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1810 break;
1811 udelay(10);
1812 }
1813
1814 /* Chip might not be fitted with firmware. Some Sun onboard
1815 * parts are configured like that. So don't signal the timeout
1816 * of the above loop as an error, but do report the lack of
1817 * running firmware once.
1818 */
1819 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1820 tg3_flag_set(tp, NO_FWARE_REPORTED);
1821
1822 netdev_info(tp->dev, "No firmware running\n");
1823 }
1824
1825 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1826 /* The 57765 A0 needs a little more
1827 * time to do some important work.
1828 */
1829 mdelay(10);
1830 }
1831
1832 return 0;
1833}
1834
95e2869a
MC		 1835static void tg3_link_report(struct tg3 *tp)
1836{
1837 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1838 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1839 tg3_ump_link_report(tp);
1840 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1841 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1842 (tp->link_config.active_speed == SPEED_1000 ?
1843 1000 :
1844 (tp->link_config.active_speed == SPEED_100 ?
1845 100 : 10)),
1846 (tp->link_config.active_duplex == DUPLEX_FULL ?
1847 "full" : "half"));
1848
1849 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1850 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1851 "on" : "off",
1852 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1853 "on" : "off");
47007831
MC		 1854
1855 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1856 netdev_info(tp->dev, "EEE is %s\n",
1857 tp->setlpicnt ? "enabled" : "disabled");
1858
95e2869a
MC		 1859 tg3_ump_link_report(tp);
1860 }
1861}
1862
95e2869a
MC		 1863static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1864{
1865 u16 miireg;
1866
e18ce346 1867 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1868 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1869 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1870 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1871 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1872 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1873 else
1874 miireg = 0;
1875
1876 return miireg;
1877}
1878
95e2869a
MC		 1879static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1880{
1881 u8 cap = 0;
1882
f3791cdf
MC		 1883 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1884 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1885 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1886 if (lcladv & ADVERTISE_1000XPAUSE)
1887 cap = FLOW_CTRL_RX;
1888 if (rmtadv & ADVERTISE_1000XPAUSE)
e18ce346 1889 cap = FLOW_CTRL_TX;
95e2869a
MC		 1890 }
1891
1892 return cap;
1893}
1894
f51f3562 1895static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1896{
b02fd9e3 1897 u8 autoneg;
f51f3562 1898 u8 flowctrl = 0;
95e2869a
MC		 1899 u32 old_rx_mode = tp->rx_mode;
1900 u32 old_tx_mode = tp->tx_mode;
1901
63c3a66f 1902 if (tg3_flag(tp, USE_PHYLIB))
3f0e3ad7 1903 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1904 else
1905 autoneg = tp->link_config.autoneg;
1906
63c3a66f 1907 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
f07e9af3 1908 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
f51f3562 1909 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1910 else
bc02ff95 1911 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1912 } else
1913 flowctrl = tp->link_config.flowctrl;
95e2869a 1914
f51f3562 1915 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1916
e18ce346 1917 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1918 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1919 else
1920 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1921
f51f3562 1922 if (old_rx_mode != tp->rx_mode)
95e2869a 1923 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1924
e18ce346 1925 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1926 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1927 else
1928 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1929
f51f3562 1930 if (old_tx_mode != tp->tx_mode)
95e2869a 1931 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1932}
1933
b02fd9e3
MC		 1934static void tg3_adjust_link(struct net_device *dev)
1935{
1936 u8 oldflowctrl, linkmesg = 0;
1937 u32 mac_mode, lcl_adv, rmt_adv;
1938 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1939 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1940
24bb4fb6 1941 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1942
1943 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1944 MAC_MODE_HALF_DUPLEX);
1945
1946 oldflowctrl = tp->link_config.active_flowctrl;
1947
1948 if (phydev->link) {
1949 lcl_adv = 0;
1950 rmt_adv = 0;
1951
1952 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1953 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1954 else if (phydev->speed == SPEED_1000 ||
1955 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1956 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1957 else
1958 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1959
1960 if (phydev->duplex == DUPLEX_HALF)
1961 mac_mode |= MAC_MODE_HALF_DUPLEX;
1962 else {
f88788f0 1963 lcl_adv = mii_advertise_flowctrl(
b02fd9e3
MC		 1964 tp->link_config.flowctrl);
1965
1966 if (phydev->pause)
1967 rmt_adv = LPA_PAUSE_CAP;
1968 if (phydev->asym_pause)
1969 rmt_adv |= LPA_PAUSE_ASYM;
1970 }
1971
1972 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1973 } else
1974 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1975
1976 if (mac_mode != tp->mac_mode) {
1977 tp->mac_mode = mac_mode;
1978 tw32_f(MAC_MODE, tp->mac_mode);
1979 udelay(40);
1980 }
1981
fcb389df
MC		 1982 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1983 if (phydev->speed == SPEED_10)
1984 tw32(MAC_MI_STAT,
1985 MAC_MI_STAT_10MBPS_MODE |
1986 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1987 else
1988 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1989 }
1990
b02fd9e3
MC		 1991 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1992 tw32(MAC_TX_LENGTHS,
1993 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1994 (6 << TX_LENGTHS_IPG_SHIFT) |
1995 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1996 else
1997 tw32(MAC_TX_LENGTHS,
1998 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1999 (6 << TX_LENGTHS_IPG_SHIFT) |
2000 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2001
34655ad6 2002 if (phydev->link != tp->old_link ||
b02fd9e3
MC		 2003 phydev->speed != tp->link_config.active_speed ||
2004 phydev->duplex != tp->link_config.active_duplex ||
2005 oldflowctrl != tp->link_config.active_flowctrl)
c6cdf436 2006 linkmesg = 1;
b02fd9e3 2007
34655ad6 2008 tp->old_link = phydev->link;
b02fd9e3
MC		 2009 tp->link_config.active_speed = phydev->speed;
2010 tp->link_config.active_duplex = phydev->duplex;
2011
24bb4fb6 2012 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 2013
2014 if (linkmesg)
2015 tg3_link_report(tp);
2016}
2017
2018static int tg3_phy_init(struct tg3 *tp)
2019{
2020 struct phy_device *phydev;
2021
f07e9af3 2022 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
b02fd9e3
MC		 2023 return 0;
2024
2025 /* Bring the PHY back to a known state. */
2026 tg3_bmcr_reset(tp);
2027
3f0e3ad7 2028 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2029
2030 /* Attach the MAC to the PHY. */
f9a8f83b
FF		 2031 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2032 tg3_adjust_link, phydev->interface);
b02fd9e3 2033 if (IS_ERR(phydev)) {
ab96b241 2034 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 2035 return PTR_ERR(phydev);
2036 }
2037
b02fd9e3 2038 /* Mask with MAC supported features. */
9c61d6bc
MC		 2039 switch (phydev->interface) {
2040 case PHY_INTERFACE_MODE_GMII:
2041 case PHY_INTERFACE_MODE_RGMII:
f07e9af3 2042 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
321d32a0
MC		 2043 phydev->supported &= (PHY_GBIT_FEATURES |
2044 SUPPORTED_Pause |
2045 SUPPORTED_Asym_Pause);
2046 break;
2047 }
2048 /* fallthru */
9c61d6bc
MC		 2049 case PHY_INTERFACE_MODE_MII:
2050 phydev->supported &= (PHY_BASIC_FEATURES |
2051 SUPPORTED_Pause |
2052 SUPPORTED_Asym_Pause);
2053 break;
2054 default:
3f0e3ad7 2055 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 2056 return -EINVAL;
2057 }
2058
f07e9af3 2059 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2060
2061 phydev->advertising = phydev->supported;
2062
b02fd9e3
MC		 2063 return 0;
2064}
2065
2066static void tg3_phy_start(struct tg3 *tp)
2067{
2068 struct phy_device *phydev;
2069
f07e9af3 2070 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2071 return;
2072
3f0e3ad7 2073 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 2074
80096068
MC		 2075 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2076 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
c6700ce2
MC		 2077 phydev->speed = tp->link_config.speed;
2078 phydev->duplex = tp->link_config.duplex;
2079 phydev->autoneg = tp->link_config.autoneg;
2080 phydev->advertising = tp->link_config.advertising;
b02fd9e3
MC		 2081 }
2082
2083 phy_start(phydev);
2084
2085 phy_start_aneg(phydev);
2086}
2087
2088static void tg3_phy_stop(struct tg3 *tp)
2089{
f07e9af3 2090 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2091 return;
2092
3f0e3ad7 2093 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 2094}
2095
2096static void tg3_phy_fini(struct tg3 *tp)
2097{
f07e9af3 2098 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7 2099 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
f07e9af3 2100 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2101 }
2102}
2103
941ec90f
MC		 2104static int tg3_phy_set_extloopbk(struct tg3 *tp)
2105{
2106 int err;
2107 u32 val;
2108
2109 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2110 return 0;
2111
2112 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2113 /* Cannot do read-modify-write on 5401 */
2114 err = tg3_phy_auxctl_write(tp,
2115 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2116 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2117 0x4c20);
2118 goto done;
2119 }
2120
2121 err = tg3_phy_auxctl_read(tp,
2122 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2123 if (err)
2124 return err;
2125
2126 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2127 err = tg3_phy_auxctl_write(tp,
2128 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2129
2130done:
2131 return err;
2132}
2133
7f97a4bd
MC		 2134static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2135{
2136 u32 phytest;
2137
2138 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2139 u32 phy;
2140
2141 tg3_writephy(tp, MII_TG3_FET_TEST,
2142 phytest | MII_TG3_FET_SHADOW_EN);
2143 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2144 if (enable)
2145 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2146 else
2147 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2148 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2149 }
2150 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2151 }
2152}
2153
6833c043
MC		 2154static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2155{
2156 u32 reg;
2157
63c3a66f
JP		 2158 if (!tg3_flag(tp, 5705_PLUS) ||
2159 (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2160 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
6833c043
MC		 2161 return;
2162
f07e9af3 2163 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7f97a4bd
MC		 2164 tg3_phy_fet_toggle_apd(tp, enable);
2165 return;
2166 }
2167
6833c043
MC		 2168 reg = MII_TG3_MISC_SHDW_WREN |
2169 MII_TG3_MISC_SHDW_SCR5_SEL |
2170 MII_TG3_MISC_SHDW_SCR5_LPED |
2171 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2172 MII_TG3_MISC_SHDW_SCR5_SDTL |
2173 MII_TG3_MISC_SHDW_SCR5_C125OE;
2174 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
2175 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2176
2177 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2178
2179
2180 reg = MII_TG3_MISC_SHDW_WREN |
2181 MII_TG3_MISC_SHDW_APD_SEL |
2182 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2183 if (enable)
2184 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2185
2186 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2187}
2188
9ef8ca99
MC		 2189static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2190{
2191 u32 phy;
2192
63c3a66f 2193 if (!tg3_flag(tp, 5705_PLUS) ||
f07e9af3 2194 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9ef8ca99
MC		 2195 return;
2196
f07e9af3 2197 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
9ef8ca99
MC		 2198 u32 ephy;
2199
535ef6e1
MC		 2200 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2201 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2202
2203 tg3_writephy(tp, MII_TG3_FET_TEST,
2204 ephy | MII_TG3_FET_SHADOW_EN);
2205 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 2206 if (enable)
535ef6e1 2207 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 2208 else
535ef6e1
MC		 2209 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2210 tg3_writephy(tp, reg, phy);
9ef8ca99 2211 }
535ef6e1 2212 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 2213 }
2214 } else {
15ee95c3
MC		 2215 int ret;
2216
2217 ret = tg3_phy_auxctl_read(tp,
2218 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2219 if (!ret) {
9ef8ca99
MC		 2220 if (enable)
2221 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2222 else
2223 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
b4bd2929
MC		 2224 tg3_phy_auxctl_write(tp,
2225 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
9ef8ca99
MC		 2226 }
2227 }
2228}
2229
1da177e4
LT		 2230static void tg3_phy_set_wirespeed(struct tg3 *tp)
2231{
15ee95c3 2232 int ret;
1da177e4
LT		 2233 u32 val;
2234
f07e9af3 2235 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1da177e4
LT		 2236 return;
2237
15ee95c3
MC		 2238 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2239 if (!ret)
b4bd2929
MC		 2240 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2241 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1da177e4
LT		 2242}
2243
b2a5c19c
MC		 2244static void tg3_phy_apply_otp(struct tg3 *tp)
2245{
2246 u32 otp, phy;
2247
2248 if (!tp->phy_otp)
2249 return;
2250
2251 otp = tp->phy_otp;
2252
daf3ec68 2253 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
1d36ba45 2254 return;
b2a5c19c
MC		 2255
2256 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2257 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2258 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2259
2260 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2261 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2262 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2263
2264 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2265 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2266 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2267
2268 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2269 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2270
2271 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2272 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2273
2274 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2275 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2276 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2277
daf3ec68 2278 tg3_phy_toggle_auxctl_smdsp(tp, false);
b2a5c19c
MC		 2279}
2280
52b02d04
MC		 2281static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2282{
2283 u32 val;
2284
2285 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2286 return;
2287
2288 tp->setlpicnt = 0;
2289
2290 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2291 current_link_up == 1 &&
a6b68dab
MC		 2292 tp->link_config.active_duplex == DUPLEX_FULL &&
2293 (tp->link_config.active_speed == SPEED_100 ||
2294 tp->link_config.active_speed == SPEED_1000)) {
52b02d04
MC		 2295 u32 eeectl;
2296
2297 if (tp->link_config.active_speed == SPEED_1000)
2298 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2299 else
2300 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2301
2302 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2303
3110f5f5
MC		 2304 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2305 TG3_CL45_D7_EEERES_STAT, &val);
52b02d04 2306
b0c5943f
MC		 2307 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2308 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
52b02d04
MC		 2309 tp->setlpicnt = 2;
2310 }
2311
2312 if (!tp->setlpicnt) {
b715ce94 2313 if (current_link_up == 1 &&
daf3ec68 2314 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94 2315 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
daf3ec68 2316 tg3_phy_toggle_auxctl_smdsp(tp, false);
b715ce94
MC		 2317 }
2318
52b02d04
MC		 2319 val = tr32(TG3_CPMU_EEE_MODE);
2320 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2321 }
2322}
2323
b0c5943f
MC		 2324static void tg3_phy_eee_enable(struct tg3 *tp)
2325{
2326 u32 val;
2327
2328 if (tp->link_config.active_speed == SPEED_1000 &&
2329 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2330 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
55086ad9 2331 tg3_flag(tp, 57765_CLASS)) &&
daf3ec68 2332 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94
MC		 2333 val = MII_TG3_DSP_TAP26_ALNOKO |
2334 MII_TG3_DSP_TAP26_RMRXSTO;
2335 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
daf3ec68 2336 tg3_phy_toggle_auxctl_smdsp(tp, false);
b0c5943f
MC		 2337 }
2338
2339 val = tr32(TG3_CPMU_EEE_MODE);
2340 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2341}
2342
1da177e4
LT		 2343static int tg3_wait_macro_done(struct tg3 *tp)
2344{
2345 int limit = 100;
2346
2347 while (limit--) {
2348 u32 tmp32;
2349
f08aa1a8 2350 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1da177e4
LT		 2351 if ((tmp32 & 0x1000) == 0)
2352 break;
2353 }
2354 }
d4675b52 2355 if (limit < 0)
1da177e4
LT		 2356 return -EBUSY;
2357
2358 return 0;
2359}
2360
2361static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2362{
2363 static const u32 test_pat[4][6] = {
2364 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2365 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2366 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2367 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2368 };
2369 int chan;
2370
2371 for (chan = 0; chan < 4; chan++) {
2372 int i;
2373
2374 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2375 (chan * 0x2000) | 0x0200);
f08aa1a8 2376 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2377
2378 for (i = 0; i < 6; i++)
2379 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2380 test_pat[chan][i]);
2381
f08aa1a8 2382 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2383 if (tg3_wait_macro_done(tp)) {
2384 *resetp = 1;
2385 return -EBUSY;
2386 }
2387
2388 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2389 (chan * 0x2000) | 0x0200);
f08aa1a8 2390 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1da177e4
LT		 2391 if (tg3_wait_macro_done(tp)) {
2392 *resetp = 1;
2393 return -EBUSY;
2394 }
2395
f08aa1a8 2396 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1da177e4
LT		 2397 if (tg3_wait_macro_done(tp)) {
2398 *resetp = 1;
2399 return -EBUSY;
2400 }
2401
2402 for (i = 0; i < 6; i += 2) {
2403 u32 low, high;
2404
2405 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2406 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2407 tg3_wait_macro_done(tp)) {
2408 *resetp = 1;
2409 return -EBUSY;
2410 }
2411 low &= 0x7fff;
2412 high &= 0x000f;
2413 if (low != test_pat[chan][i] ||
2414 high != test_pat[chan][i+1]) {
2415 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2416 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2417 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2418
2419 return -EBUSY;
2420 }
2421 }
2422 }
2423
2424 return 0;
2425}
2426
2427static int tg3_phy_reset_chanpat(struct tg3 *tp)
2428{
2429 int chan;
2430
2431 for (chan = 0; chan < 4; chan++) {
2432 int i;
2433
2434 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2435 (chan * 0x2000) | 0x0200);
f08aa1a8 2436 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2437 for (i = 0; i < 6; i++)
2438 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
f08aa1a8 2439 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2440 if (tg3_wait_macro_done(tp))
2441 return -EBUSY;
2442 }
2443
2444 return 0;
2445}
2446
2447static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2448{
2449 u32 reg32, phy9_orig;
2450 int retries, do_phy_reset, err;
2451
2452 retries = 10;
2453 do_phy_reset = 1;
2454 do {
2455 if (do_phy_reset) {
2456 err = tg3_bmcr_reset(tp);
2457 if (err)
2458 return err;
2459 do_phy_reset = 0;
2460 }
2461
2462 /* Disable transmitter and interrupt. */
2463 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2464 continue;
2465
2466 reg32 |= 0x3000;
2467 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2468
2469 /* Set full-duplex, 1000 mbps. */
2470 tg3_writephy(tp, MII_BMCR,
221c5637 2471 BMCR_FULLDPLX | BMCR_SPEED1000);
1da177e4
LT		 2472
2473 /* Set to master mode. */
221c5637 2474 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
1da177e4
LT		 2475 continue;
2476
221c5637
MC		 2477 tg3_writephy(tp, MII_CTRL1000,
2478 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
1da177e4 2479
daf3ec68 2480 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
1d36ba45
MC		 2481 if (err)
2482 return err;
1da177e4
LT		 2483
2484 /* Block the PHY control access. */
6ee7c0a0 2485 tg3_phydsp_write(tp, 0x8005, 0x0800);
1da177e4
LT		 2486
2487 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2488 if (!err)
2489 break;
2490 } while (--retries);
2491
2492 err = tg3_phy_reset_chanpat(tp);
2493 if (err)
2494 return err;
2495
6ee7c0a0 2496 tg3_phydsp_write(tp, 0x8005, 0x0000);
1da177e4
LT		 2497
2498 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
f08aa1a8 2499 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1da177e4 2500
daf3ec68 2501 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2502
221c5637 2503 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
1da177e4
LT		 2504
2505 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2506 reg32 &= ~0x3000;
2507 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2508 } else if (!err)
2509 err = -EBUSY;
2510
2511 return err;
2512}
2513
f4a46d1f
NNS		 2514static void tg3_carrier_on(struct tg3 *tp)
2515{
2516 netif_carrier_on(tp->dev);
2517 tp->link_up = true;
2518}
2519
2520static void tg3_carrier_off(struct tg3 *tp)
2521{
2522 netif_carrier_off(tp->dev);
2523 tp->link_up = false;
2524}
2525
1da177e4
LT		 2526/* This will reset the tigon3 PHY if there is no valid
2527 * link unless the FORCE argument is non-zero.
2528 */
2529static int tg3_phy_reset(struct tg3 *tp)
2530{
f833c4c1 2531 u32 val, cpmuctrl;
1da177e4
LT		 2532 int err;
2533
60189ddf 2534 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2535 val = tr32(GRC_MISC_CFG);
2536 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2537 udelay(40);
2538 }
f833c4c1
MC		 2539 err = tg3_readphy(tp, MII_BMSR, &val);
2540 err |= tg3_readphy(tp, MII_BMSR, &val);
1da177e4
LT		 2541 if (err != 0)
2542 return -EBUSY;
2543
f4a46d1f
NNS		 2544 if (netif_running(tp->dev) && tp->link_up) {
2545 tg3_carrier_off(tp);
c8e1e82b
MC		 2546 tg3_link_report(tp);
2547 }
2548
1da177e4
LT		 2549 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2550 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2551 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2552 err = tg3_phy_reset_5703_4_5(tp);
2553 if (err)
2554 return err;
2555 goto out;
2556 }
2557
b2a5c19c
MC		 2558 cpmuctrl = 0;
2559 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2560 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2561 cpmuctrl = tr32(TG3_CPMU_CTRL);
2562 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2563 tw32(TG3_CPMU_CTRL,
2564 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2565 }
2566
1da177e4
LT		 2567 err = tg3_bmcr_reset(tp);
2568 if (err)
2569 return err;
2570
b2a5c19c 2571 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
f833c4c1
MC		 2572 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2573 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
b2a5c19c
MC		 2574
2575 tw32(TG3_CPMU_CTRL, cpmuctrl);
2576 }
2577
bcb37f6c
MC		 2578 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2579 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2580 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2581 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2582 CPMU_LSPD_1000MB_MACCLK_12_5) {
2583 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2584 udelay(40);
2585 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2586 }
2587 }
2588
63c3a66f 2589 if (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2590 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
ecf1410b
MC		 2591 return 0;
2592
b2a5c19c
MC		 2593 tg3_phy_apply_otp(tp);
2594
f07e9af3 2595 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
6833c043
MC		 2596 tg3_phy_toggle_apd(tp, true);
2597 else
2598 tg3_phy_toggle_apd(tp, false);
2599
1da177e4 2600out:
1d36ba45 2601 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
daf3ec68 2602 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
6ee7c0a0
MC		 2603 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2604 tg3_phydsp_write(tp, 0x000a, 0x0323);
daf3ec68 2605 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2606 }
1d36ba45 2607
f07e9af3 2608 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
f08aa1a8
MC		 2609 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2610 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1da177e4 2611 }
1d36ba45 2612
f07e9af3 2613 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
daf3ec68 2614 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2615 tg3_phydsp_write(tp, 0x000a, 0x310b);
2616 tg3_phydsp_write(tp, 0x201f, 0x9506);
2617 tg3_phydsp_write(tp, 0x401f, 0x14e2);
daf3ec68 2618 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2619 }
f07e9af3 2620 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
daf3ec68 2621 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2622 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2623 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2624 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2625 tg3_writephy(tp, MII_TG3_TEST1,
2626 MII_TG3_TEST1_TRIM_EN | 0x4);
2627 } else
2628 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2629
daf3ec68 2630 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2631 }
c424cb24 2632 }
1d36ba45 2633
1da177e4
LT		 2634 /* Set Extended packet length bit (bit 14) on all chips that */
2635 /* support jumbo frames */
79eb6904 2636 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4 2637 /* Cannot do read-modify-write on 5401 */
b4bd2929 2638 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
63c3a66f 2639 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
1da177e4 2640 /* Set bit 14 with read-modify-write to preserve other bits */
15ee95c3
MC		 2641 err = tg3_phy_auxctl_read(tp,
2642 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2643 if (!err)
b4bd2929
MC		 2644 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2645 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
1da177e4
LT		 2646 }
2647
2648 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2649 * jumbo frames transmission.
2650 */
63c3a66f 2651 if (tg3_flag(tp, JUMBO_CAPABLE)) {
f833c4c1 2652 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
c6cdf436 2653 tg3_writephy(tp, MII_TG3_EXT_CTRL,
f833c4c1 2654 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1da177e4
LT		 2655 }
2656
715116a1 2657 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 2658 /* adjust output voltage */
535ef6e1 2659 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2660 }
2661
c65a17f4
MC		 2662 if (tp->pci_chip_rev_id == CHIPREV_ID_5762_A0)
2663 tg3_phydsp_write(tp, 0xffb, 0x4000);
2664
9ef8ca99 2665 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2666 tg3_phy_set_wirespeed(tp);
2667 return 0;
2668}
2669
3a1e19d3
MC		 2670#define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2671#define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2672#define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2673 TG3_GPIO_MSG_NEED_VAUX)
2674#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2675 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2676 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2677 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2678 (TG3_GPIO_MSG_DRVR_PRES << 12))
2679
2680#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2681 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2682 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2683 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2684 (TG3_GPIO_MSG_NEED_VAUX << 12))
2685
2686static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2687{
2688 u32 status, shift;
2689
2690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2691 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2692 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2693 else
2694 status = tr32(TG3_CPMU_DRV_STATUS);
2695
2696 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2697 status &= ~(TG3_GPIO_MSG_MASK << shift);
2698 status |= (newstat << shift);
2699
2700 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2701 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2702 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2703 else
2704 tw32(TG3_CPMU_DRV_STATUS, status);
2705
2706 return status >> TG3_APE_GPIO_MSG_SHIFT;
2707}
2708
520b2756
MC		 2709static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2710{
2711 if (!tg3_flag(tp, IS_NIC))
2712 return 0;
2713
3a1e19d3
MC		 2714 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2715 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2716 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2717 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2718 return -EIO;
520b2756 2719
3a1e19d3
MC		 2720 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2721
2722 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2723 TG3_GRC_LCLCTL_PWRSW_DELAY);
2724
2725 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2726 } else {
2727 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2728 TG3_GRC_LCLCTL_PWRSW_DELAY);
2729 }
6f5c8f83 2730
520b2756
MC		 2731 return 0;
2732}
2733
2734static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2735{
2736 u32 grc_local_ctrl;
2737
2738 if (!tg3_flag(tp, IS_NIC) ||
2739 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2740 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2741 return;
2742
2743 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2744
2745 tw32_wait_f(GRC_LOCAL_CTRL,
2746 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2747 TG3_GRC_LCLCTL_PWRSW_DELAY);
2748
2749 tw32_wait_f(GRC_LOCAL_CTRL,
2750 grc_local_ctrl,
2751 TG3_GRC_LCLCTL_PWRSW_DELAY);
2752
2753 tw32_wait_f(GRC_LOCAL_CTRL,
2754 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2755 TG3_GRC_LCLCTL_PWRSW_DELAY);
2756}
2757
2758static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2759{
2760 if (!tg3_flag(tp, IS_NIC))
2761 return;
2762
2763 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2764 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2765 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2766 (GRC_LCLCTRL_GPIO_OE0 |
2767 GRC_LCLCTRL_GPIO_OE1 |
2768 GRC_LCLCTRL_GPIO_OE2 |
2769 GRC_LCLCTRL_GPIO_OUTPUT0 |
2770 GRC_LCLCTRL_GPIO_OUTPUT1),
2771 TG3_GRC_LCLCTL_PWRSW_DELAY);
2772 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2773 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2774 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2775 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2776 GRC_LCLCTRL_GPIO_OE1 |
2777 GRC_LCLCTRL_GPIO_OE2 |
2778 GRC_LCLCTRL_GPIO_OUTPUT0 |
2779 GRC_LCLCTRL_GPIO_OUTPUT1 |
2780 tp->grc_local_ctrl;
2781 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2782 TG3_GRC_LCLCTL_PWRSW_DELAY);
2783
2784 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2785 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2786 TG3_GRC_LCLCTL_PWRSW_DELAY);
2787
2788 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2789 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2790 TG3_GRC_LCLCTL_PWRSW_DELAY);
2791 } else {
2792 u32 no_gpio2;
2793 u32 grc_local_ctrl = 0;
2794
2795 /* Workaround to prevent overdrawing Amps. */
2796 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2797 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2798 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2799 grc_local_ctrl,
2800 TG3_GRC_LCLCTL_PWRSW_DELAY);
2801 }
2802
2803 /* On 5753 and variants, GPIO2 cannot be used. */
2804 no_gpio2 = tp->nic_sram_data_cfg &
2805 NIC_SRAM_DATA_CFG_NO_GPIO2;
2806
2807 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2808 GRC_LCLCTRL_GPIO_OE1 |
2809 GRC_LCLCTRL_GPIO_OE2 |
2810 GRC_LCLCTRL_GPIO_OUTPUT1 |
2811 GRC_LCLCTRL_GPIO_OUTPUT2;
2812 if (no_gpio2) {
2813 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2814 GRC_LCLCTRL_GPIO_OUTPUT2);
2815 }
2816 tw32_wait_f(GRC_LOCAL_CTRL,
2817 tp->grc_local_ctrl | grc_local_ctrl,
2818 TG3_GRC_LCLCTL_PWRSW_DELAY);
2819
2820 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2821
2822 tw32_wait_f(GRC_LOCAL_CTRL,
2823 tp->grc_local_ctrl | grc_local_ctrl,
2824 TG3_GRC_LCLCTL_PWRSW_DELAY);
2825
2826 if (!no_gpio2) {
2827 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2828 tw32_wait_f(GRC_LOCAL_CTRL,
2829 tp->grc_local_ctrl | grc_local_ctrl,
2830 TG3_GRC_LCLCTL_PWRSW_DELAY);
2831 }
2832 }
3a1e19d3
MC		 2833}
2834
cd0d7228 2835static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
3a1e19d3
MC		 2836{
2837 u32 msg = 0;
2838
2839 /* Serialize power state transitions */
2840 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2841 return;
2842
cd0d7228 2843 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
3a1e19d3
MC		 2844 msg = TG3_GPIO_MSG_NEED_VAUX;
2845
2846 msg = tg3_set_function_status(tp, msg);
2847
2848 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2849 goto done;
6f5c8f83 2850
3a1e19d3
MC		 2851 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2852 tg3_pwrsrc_switch_to_vaux(tp);
2853 else
2854 tg3_pwrsrc_die_with_vmain(tp);
2855
2856done:
6f5c8f83 2857 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
520b2756
MC		 2858}
2859
cd0d7228 2860static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
1da177e4 2861{
683644b7 2862 bool need_vaux = false;
1da177e4 2863
334355aa 2864 /* The GPIOs do something completely different on 57765. */
55086ad9 2865 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
1da177e4
LT		 2866 return;
2867
3a1e19d3
MC		 2868 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2869 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2870 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
cd0d7228
MC		 2871 tg3_frob_aux_power_5717(tp, include_wol ?
2872 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
3a1e19d3
MC		 2873 return;
2874 }
2875
2876 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
8c2dc7e1
MC		 2877 struct net_device *dev_peer;
2878
2879 dev_peer = pci_get_drvdata(tp->pdev_peer);
683644b7 2880
bc1c7567 2881 /* remove_one() may have been run on the peer. */
683644b7
MC		 2882 if (dev_peer) {
2883 struct tg3 *tp_peer = netdev_priv(dev_peer);
2884
63c3a66f 2885 if (tg3_flag(tp_peer, INIT_COMPLETE))
683644b7
MC		 2886 return;
2887
cd0d7228 2888 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
63c3a66f 2889 tg3_flag(tp_peer, ENABLE_ASF))
683644b7
MC		 2890 need_vaux = true;
2891 }
1da177e4
LT		 2892 }
2893
cd0d7228
MC		 2894 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2895 tg3_flag(tp, ENABLE_ASF))
683644b7
MC		 2896 need_vaux = true;
2897
520b2756
MC		 2898 if (need_vaux)
2899 tg3_pwrsrc_switch_to_vaux(tp);
2900 else
2901 tg3_pwrsrc_die_with_vmain(tp);
1da177e4
LT		 2902}
2903
e8f3f6ca
MC		 2904static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2905{
2906 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2907 return 1;
79eb6904 2908 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 2909 if (speed != SPEED_10)
2910 return 1;
2911 } else if (speed == SPEED_10)
2912 return 1;
2913
2914 return 0;
2915}
2916
0a459aac 2917static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2918{
ce057f01
MC		 2919 u32 val;
2920
f07e9af3 2921 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
5129724a
MC		 2922 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2923 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2924 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2925
2926 sg_dig_ctrl |=
2927 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2928 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2929 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2930 }
3f7045c1 2931 return;
5129724a 2932 }
3f7045c1 2933
60189ddf 2934 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2935 tg3_bmcr_reset(tp);
2936 val = tr32(GRC_MISC_CFG);
2937 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2938 udelay(40);
2939 return;
f07e9af3 2940 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
0e5f784c
MC		 2941 u32 phytest;
2942 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2943 u32 phy;
2944
2945 tg3_writephy(tp, MII_ADVERTISE, 0);
2946 tg3_writephy(tp, MII_BMCR,
2947 BMCR_ANENABLE | BMCR_ANRESTART);
2948
2949 tg3_writephy(tp, MII_TG3_FET_TEST,
2950 phytest | MII_TG3_FET_SHADOW_EN);
2951 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2952 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2953 tg3_writephy(tp,
2954 MII_TG3_FET_SHDW_AUXMODE4,
2955 phy);
2956 }
2957 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2958 }
2959 return;
0a459aac 2960 } else if (do_low_power) {
715116a1
MC		 2961 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2962 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac 2963
b4bd2929
MC		 2964 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2965 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2966 MII_TG3_AUXCTL_PCTL_VREG_11V;
2967 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
715116a1 2968 }
3f7045c1 2969
15c3b696
MC		 2970 /* The PHY should not be powered down on some chips because
2971 * of bugs.
2972 */
2973 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2974 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2975 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
085f1afc
MC		 2976 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
2977 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
2978 !tp->pci_fn))
15c3b696 2979 return;
ce057f01 2980
bcb37f6c
MC		 2981 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2982 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2983 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2984 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2985 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2986 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2987 }
2988
15c3b696
MC		 2989 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2990}
2991
ffbcfed4
MC		 2992/* tp->lock is held. */
2993static int tg3_nvram_lock(struct tg3 *tp)
2994{
63c3a66f 2995 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 2996 int i;
2997
2998 if (tp->nvram_lock_cnt == 0) {
2999 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3000 for (i = 0; i < 8000; i++) {
3001 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3002 break;
3003 udelay(20);
3004 }
3005 if (i == 8000) {
3006 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3007 return -ENODEV;
3008 }
3009 }
3010 tp->nvram_lock_cnt++;
3011 }
3012 return 0;
3013}
3014
3015/* tp->lock is held. */
3016static void tg3_nvram_unlock(struct tg3 *tp)
3017{
63c3a66f 3018 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3019 if (tp->nvram_lock_cnt > 0)
3020 tp->nvram_lock_cnt--;
3021 if (tp->nvram_lock_cnt == 0)
3022 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3023 }
3024}
3025
3026/* tp->lock is held. */
3027static void tg3_enable_nvram_access(struct tg3 *tp)
3028{
63c3a66f 3029 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3030 u32 nvaccess = tr32(NVRAM_ACCESS);
3031
3032 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3033 }
3034}
3035
3036/* tp->lock is held. */
3037static void tg3_disable_nvram_access(struct tg3 *tp)
3038{
63c3a66f 3039 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3040 u32 nvaccess = tr32(NVRAM_ACCESS);
3041
3042 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3043 }
3044}
3045
3046static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3047 u32 offset, u32 *val)
3048{
3049 u32 tmp;
3050 int i;
3051
3052 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3053 return -EINVAL;
3054
3055 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3056 EEPROM_ADDR_DEVID_MASK |
3057 EEPROM_ADDR_READ);
3058 tw32(GRC_EEPROM_ADDR,
3059 tmp |
3060 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3061 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3062 EEPROM_ADDR_ADDR_MASK) |
3063 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3064
3065 for (i = 0; i < 1000; i++) {
3066 tmp = tr32(GRC_EEPROM_ADDR);
3067
3068 if (tmp & EEPROM_ADDR_COMPLETE)
3069 break;
3070 msleep(1);
3071 }
3072 if (!(tmp & EEPROM_ADDR_COMPLETE))
3073 return -EBUSY;
3074
62cedd11
MC		 3075 tmp = tr32(GRC_EEPROM_DATA);
3076
3077 /*
3078 * The data will always be opposite the native endian
3079 * format. Perform a blind byteswap to compensate.
3080 */
3081 *val = swab32(tmp);
3082
ffbcfed4
MC		 3083 return 0;
3084}
3085
3086#define NVRAM_CMD_TIMEOUT 10000
3087
3088static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3089{
3090 int i;
3091
3092 tw32(NVRAM_CMD, nvram_cmd);
3093 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3094 udelay(10);
3095 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3096 udelay(10);
3097 break;
3098 }
3099 }
3100
3101 if (i == NVRAM_CMD_TIMEOUT)
3102 return -EBUSY;
3103
3104 return 0;
3105}
3106
3107static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3108{
63c3a66f
JP		 3109 if (tg3_flag(tp, NVRAM) &&
3110 tg3_flag(tp, NVRAM_BUFFERED) &&
3111 tg3_flag(tp, FLASH) &&
3112 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3113 (tp->nvram_jedecnum == JEDEC_ATMEL))
3114
3115 addr = ((addr / tp->nvram_pagesize) <<
3116 ATMEL_AT45DB0X1B_PAGE_POS) +
3117 (addr % tp->nvram_pagesize);
3118
3119 return addr;
3120}
3121
3122static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3123{
63c3a66f
JP		 3124 if (tg3_flag(tp, NVRAM) &&
3125 tg3_flag(tp, NVRAM_BUFFERED) &&
3126 tg3_flag(tp, FLASH) &&
3127 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3128 (tp->nvram_jedecnum == JEDEC_ATMEL))
3129
3130 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3131 tp->nvram_pagesize) +
3132 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3133
3134 return addr;
3135}
3136
e4f34110
MC		 3137/* NOTE: Data read in from NVRAM is byteswapped according to
3138 * the byteswapping settings for all other register accesses.
3139 * tg3 devices are BE devices, so on a BE machine, the data
3140 * returned will be exactly as it is seen in NVRAM. On a LE
3141 * machine, the 32-bit value will be byteswapped.
3142 */
ffbcfed4
MC		 3143static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3144{
3145 int ret;
3146
63c3a66f 3147 if (!tg3_flag(tp, NVRAM))
ffbcfed4
MC		 3148 return tg3_nvram_read_using_eeprom(tp, offset, val);
3149
3150 offset = tg3_nvram_phys_addr(tp, offset);
3151
3152 if (offset > NVRAM_ADDR_MSK)
3153 return -EINVAL;
3154
3155 ret = tg3_nvram_lock(tp);
3156 if (ret)
3157 return ret;
3158
3159 tg3_enable_nvram_access(tp);
3160
3161 tw32(NVRAM_ADDR, offset);
3162 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3163 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3164
3165 if (ret == 0)
e4f34110 3166 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 3167
3168 tg3_disable_nvram_access(tp);
3169
3170 tg3_nvram_unlock(tp);
3171
3172 return ret;
3173}
3174
a9dc529d
MC		 3175/* Ensures NVRAM data is in bytestream format. */
3176static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 3177{
3178 u32 v;
a9dc529d 3179 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 3180 if (!res)
a9dc529d 3181 *val = cpu_to_be32(v);
ffbcfed4
MC		 3182 return res;
3183}
3184
dbe9b92a
MC		 3185static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3186 u32 offset, u32 len, u8 *buf)
3187{
3188 int i, j, rc = 0;
3189 u32 val;
3190
3191 for (i = 0; i < len; i += 4) {
3192 u32 addr;
3193 __be32 data;
3194
3195 addr = offset + i;
3196
3197 memcpy(&data, buf + i, 4);
3198
3199 /*
3200 * The SEEPROM interface expects the data to always be opposite
3201 * the native endian format. We accomplish this by reversing
3202 * all the operations that would have been performed on the
3203 * data from a call to tg3_nvram_read_be32().
3204 */
3205 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3206
3207 val = tr32(GRC_EEPROM_ADDR);
3208 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3209
3210 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3211 EEPROM_ADDR_READ);
3212 tw32(GRC_EEPROM_ADDR, val |
3213 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3214 (addr & EEPROM_ADDR_ADDR_MASK) |
3215 EEPROM_ADDR_START |
3216 EEPROM_ADDR_WRITE);
3217
3218 for (j = 0; j < 1000; j++) {
3219 val = tr32(GRC_EEPROM_ADDR);
3220
3221 if (val & EEPROM_ADDR_COMPLETE)
3222 break;
3223 msleep(1);
3224 }
3225 if (!(val & EEPROM_ADDR_COMPLETE)) {
3226 rc = -EBUSY;
3227 break;
3228 }
3229 }
3230
3231 return rc;
3232}
3233
3234/* offset and length are dword aligned */
3235static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3236 u8 *buf)
3237{
3238 int ret = 0;
3239 u32 pagesize = tp->nvram_pagesize;
3240 u32 pagemask = pagesize - 1;
3241 u32 nvram_cmd;
3242 u8 *tmp;
3243
3244 tmp = kmalloc(pagesize, GFP_KERNEL);
3245 if (tmp == NULL)
3246 return -ENOMEM;
3247
3248 while (len) {
3249 int j;
3250 u32 phy_addr, page_off, size;
3251
3252 phy_addr = offset & ~pagemask;
3253
3254 for (j = 0; j < pagesize; j += 4) {
3255 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3256 (__be32 *) (tmp + j));
3257 if (ret)
3258 break;
3259 }
3260 if (ret)
3261 break;
3262
3263 page_off = offset & pagemask;
3264 size = pagesize;
3265 if (len < size)
3266 size = len;
3267
3268 len -= size;
3269
3270 memcpy(tmp + page_off, buf, size);
3271
3272 offset = offset + (pagesize - page_off);
3273
3274 tg3_enable_nvram_access(tp);
3275
3276 /*
3277 * Before we can erase the flash page, we need
3278 * to issue a special "write enable" command.
3279 */
3280 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3281
3282 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3283 break;
3284
3285 /* Erase the target page */
3286 tw32(NVRAM_ADDR, phy_addr);
3287
3288 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3289 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3290
3291 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3292 break;
3293
3294 /* Issue another write enable to start the write. */
3295 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3296
3297 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3298 break;
3299
3300 for (j = 0; j < pagesize; j += 4) {
3301 __be32 data;
3302
3303 data = *((__be32 *) (tmp + j));
3304
3305 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3306
3307 tw32(NVRAM_ADDR, phy_addr + j);
3308
3309 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3310 NVRAM_CMD_WR;
3311
3312 if (j == 0)
3313 nvram_cmd |= NVRAM_CMD_FIRST;
3314 else if (j == (pagesize - 4))
3315 nvram_cmd |= NVRAM_CMD_LAST;
3316
3317 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3318 if (ret)
3319 break;
3320 }
3321 if (ret)
3322 break;
3323 }
3324
3325 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3326 tg3_nvram_exec_cmd(tp, nvram_cmd);
3327
3328 kfree(tmp);
3329
3330 return ret;
3331}
3332
3333/* offset and length are dword aligned */
3334static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3335 u8 *buf)
3336{
3337 int i, ret = 0;
3338
3339 for (i = 0; i < len; i += 4, offset += 4) {
3340 u32 page_off, phy_addr, nvram_cmd;
3341 __be32 data;
3342
3343 memcpy(&data, buf + i, 4);
3344 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3345
3346 page_off = offset % tp->nvram_pagesize;
3347
3348 phy_addr = tg3_nvram_phys_addr(tp, offset);
3349
dbe9b92a
MC		 3350 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3351
3352 if (page_off == 0 || i == 0)
3353 nvram_cmd |= NVRAM_CMD_FIRST;
3354 if (page_off == (tp->nvram_pagesize - 4))
3355 nvram_cmd |= NVRAM_CMD_LAST;
3356
3357 if (i == (len - 4))
3358 nvram_cmd |= NVRAM_CMD_LAST;
3359
42278224
MC		 3360 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3361 !tg3_flag(tp, FLASH) ||
3362 !tg3_flag(tp, 57765_PLUS))
3363 tw32(NVRAM_ADDR, phy_addr);
3364
dbe9b92a
MC		 3365 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
3366 !tg3_flag(tp, 5755_PLUS) &&
3367 (tp->nvram_jedecnum == JEDEC_ST) &&
3368 (nvram_cmd & NVRAM_CMD_FIRST)) {
3369 u32 cmd;
3370
3371 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3372 ret = tg3_nvram_exec_cmd(tp, cmd);
3373 if (ret)
3374 break;
3375 }
3376 if (!tg3_flag(tp, FLASH)) {
3377 /* We always do complete word writes to eeprom. */
3378 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3379 }
3380
3381 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3382 if (ret)
3383 break;
3384 }
3385 return ret;
3386}
3387
3388/* offset and length are dword aligned */
3389static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3390{
3391 int ret;
3392
3393 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3394 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3395 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3396 udelay(40);
3397 }
3398
3399 if (!tg3_flag(tp, NVRAM)) {
3400 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3401 } else {
3402 u32 grc_mode;
3403
3404 ret = tg3_nvram_lock(tp);
3405 if (ret)
3406 return ret;
3407
3408 tg3_enable_nvram_access(tp);
3409 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3410 tw32(NVRAM_WRITE1, 0x406);
3411
3412 grc_mode = tr32(GRC_MODE);
3413 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3414
3415 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3416 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3417 buf);
3418 } else {
3419 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3420 buf);
3421 }
3422
3423 grc_mode = tr32(GRC_MODE);
3424 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3425
3426 tg3_disable_nvram_access(tp);
3427 tg3_nvram_unlock(tp);
3428 }
3429
3430 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3431 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3432 udelay(40);
3433 }
3434
3435 return ret;
3436}
3437
997b4f13
MC		 3438#define RX_CPU_SCRATCH_BASE 0x30000
3439#define RX_CPU_SCRATCH_SIZE 0x04000
3440#define TX_CPU_SCRATCH_BASE 0x34000
3441#define TX_CPU_SCRATCH_SIZE 0x04000
3442
3443/* tp->lock is held. */
3444static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
3445{
3446 int i;
3447
3448 BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3449
3450 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3451 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3452
3453 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3454 return 0;
3455 }
3456 if (offset == RX_CPU_BASE) {
3457 for (i = 0; i < 10000; i++) {
3458 tw32(offset + CPU_STATE, 0xffffffff);
3459 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3460 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3461 break;
3462 }
3463
3464 tw32(offset + CPU_STATE, 0xffffffff);
3465 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
3466 udelay(10);
3467 } else {
3468 for (i = 0; i < 10000; i++) {
3469 tw32(offset + CPU_STATE, 0xffffffff);
3470 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3471 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3472 break;
3473 }
3474 }
3475
3476 if (i >= 10000) {
3477 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3478 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
3479 return -ENODEV;
3480 }
3481
3482 /* Clear firmware's nvram arbitration. */
3483 if (tg3_flag(tp, NVRAM))
3484 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3485 return 0;
3486}
3487
3488struct fw_info {
3489 unsigned int fw_base;
3490 unsigned int fw_len;
3491 const __be32 *fw_data;
3492};
3493
3494/* tp->lock is held. */
3495static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3496 u32 cpu_scratch_base, int cpu_scratch_size,
3497 struct fw_info *info)
3498{
3499 int err, lock_err, i;
3500 void (*write_op)(struct tg3 *, u32, u32);
3501
3502 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3503 netdev_err(tp->dev,
3504 "%s: Trying to load TX cpu firmware which is 5705\n",
3505 __func__);
3506 return -EINVAL;
3507 }
3508
3509 if (tg3_flag(tp, 5705_PLUS))
3510 write_op = tg3_write_mem;
3511 else
3512 write_op = tg3_write_indirect_reg32;
3513
3514 /* It is possible that bootcode is still loading at this point.
3515 * Get the nvram lock first before halting the cpu.
3516 */
3517 lock_err = tg3_nvram_lock(tp);
3518 err = tg3_halt_cpu(tp, cpu_base);
3519 if (!lock_err)
3520 tg3_nvram_unlock(tp);
3521 if (err)
3522 goto out;
3523
3524 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3525 write_op(tp, cpu_scratch_base + i, 0);
3526 tw32(cpu_base + CPU_STATE, 0xffffffff);
3527 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
3528 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
3529 write_op(tp, (cpu_scratch_base +
3530 (info->fw_base & 0xffff) +
3531 (i * sizeof(u32))),
3532 be32_to_cpu(info->fw_data[i]));
3533
3534 err = 0;
3535
3536out:
3537 return err;
3538}
3539
3540/* tp->lock is held. */
3541static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3542{
3543 struct fw_info info;
3544 const __be32 *fw_data;
3545 int err, i;
3546
3547 fw_data = (void *)tp->fw->data;
3548
3549 /* Firmware blob starts with version numbers, followed by
3550 start address and length. We are setting complete length.
3551 length = end_address_of_bss - start_address_of_text.
3552 Remainder is the blob to be loaded contiguously
3553 from start address. */
3554
3555 info.fw_base = be32_to_cpu(fw_data[1]);
3556 info.fw_len = tp->fw->size - 12;
3557 info.fw_data = &fw_data[3];
3558
3559 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3560 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3561 &info);
3562 if (err)
3563 return err;
3564
3565 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3566 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3567 &info);
3568 if (err)
3569 return err;
3570
3571 /* Now startup only the RX cpu. */
3572 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3573 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3574
3575 for (i = 0; i < 5; i++) {
3576 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
3577 break;
3578 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3579 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3580 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3581 udelay(1000);
3582 }
3583 if (i >= 5) {
3584 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3585 "should be %08x\n", __func__,
3586 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
3587 return -ENODEV;
3588 }
3589 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3590 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
3591
3592 return 0;
3593}
3594
3595/* tp->lock is held. */
3596static int tg3_load_tso_firmware(struct tg3 *tp)
3597{
3598 struct fw_info info;
3599 const __be32 *fw_data;
3600 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3601 int err, i;
3602
3603 if (tg3_flag(tp, HW_TSO_1) ||
3604 tg3_flag(tp, HW_TSO_2) ||
3605 tg3_flag(tp, HW_TSO_3))
3606 return 0;
3607
3608 fw_data = (void *)tp->fw->data;
3609
3610 /* Firmware blob starts with version numbers, followed by
3611 start address and length. We are setting complete length.
3612 length = end_address_of_bss - start_address_of_text.
3613 Remainder is the blob to be loaded contiguously
3614 from start address. */
3615
3616 info.fw_base = be32_to_cpu(fw_data[1]);
3617 cpu_scratch_size = tp->fw_len;
3618 info.fw_len = tp->fw->size - 12;
3619 info.fw_data = &fw_data[3];
3620
3621 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3622 cpu_base = RX_CPU_BASE;
3623 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3624 } else {
3625 cpu_base = TX_CPU_BASE;
3626 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3627 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3628 }
3629
3630 err = tg3_load_firmware_cpu(tp, cpu_base,
3631 cpu_scratch_base, cpu_scratch_size,
3632 &info);
3633 if (err)
3634 return err;
3635
3636 /* Now startup the cpu. */
3637 tw32(cpu_base + CPU_STATE, 0xffffffff);
3638 tw32_f(cpu_base + CPU_PC, info.fw_base);
3639
3640 for (i = 0; i < 5; i++) {
3641 if (tr32(cpu_base + CPU_PC) == info.fw_base)
3642 break;
3643 tw32(cpu_base + CPU_STATE, 0xffffffff);
3644 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3645 tw32_f(cpu_base + CPU_PC, info.fw_base);
3646 udelay(1000);
3647 }
3648 if (i >= 5) {
3649 netdev_err(tp->dev,
3650 "%s fails to set CPU PC, is %08x should be %08x\n",
3651 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
3652 return -ENODEV;
3653 }
3654 tw32(cpu_base + CPU_STATE, 0xffffffff);
3655 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3656 return 0;
3657}
3658
3659
3f007891
MC		 3660/* tp->lock is held. */
3661static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
3662{
3663 u32 addr_high, addr_low;
3664 int i;
3665
3666 addr_high = ((tp->dev->dev_addr[0] << 8) |
3667 tp->dev->dev_addr[1]);
3668 addr_low = ((tp->dev->dev_addr[2] << 24) |
3669 (tp->dev->dev_addr[3] << 16) |
3670 (tp->dev->dev_addr[4] << 8) |
3671 (tp->dev->dev_addr[5] << 0));
3672 for (i = 0; i < 4; i++) {
3673 if (i == 1 && skip_mac_1)
3674 continue;
3675 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3676 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3677 }
3678
3679 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3680 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
3681 for (i = 0; i < 12; i++) {
3682 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3683 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3684 }
3685 }
3686
3687 addr_high = (tp->dev->dev_addr[0] +
3688 tp->dev->dev_addr[1] +
3689 tp->dev->dev_addr[2] +
3690 tp->dev->dev_addr[3] +
3691 tp->dev->dev_addr[4] +
3692 tp->dev->dev_addr[5]) &
3693 TX_BACKOFF_SEED_MASK;
3694 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3695}
3696
c866b7ea 3697static void tg3_enable_register_access(struct tg3 *tp)
1da177e4 3698{
c866b7ea
RW		 3699 /*
3700 * Make sure register accesses (indirect or otherwise) will function
3701 * correctly.
1da177e4
LT		 3702 */
3703 pci_write_config_dword(tp->pdev,
c866b7ea
RW		 3704 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3705}
1da177e4 3706
c866b7ea
RW		 3707static int tg3_power_up(struct tg3 *tp)
3708{
bed9829f 3709 int err;
8c6bda1a 3710
bed9829f 3711 tg3_enable_register_access(tp);
1da177e4 3712
bed9829f
MC		 3713 err = pci_set_power_state(tp->pdev, PCI_D0);
3714 if (!err) {
3715 /* Switch out of Vaux if it is a NIC */
3716 tg3_pwrsrc_switch_to_vmain(tp);
3717 } else {
3718 netdev_err(tp->dev, "Transition to D0 failed\n");
3719 }
1da177e4 3720
bed9829f 3721 return err;
c866b7ea 3722}
1da177e4 3723
4b409522
MC		 3724static int tg3_setup_phy(struct tg3 *, int);
3725
c866b7ea
RW		 3726static int tg3_power_down_prepare(struct tg3 *tp)
3727{
3728 u32 misc_host_ctrl;
3729 bool device_should_wake, do_low_power;
3730
3731 tg3_enable_register_access(tp);
5e7dfd0f
MC		 3732
3733 /* Restore the CLKREQ setting. */
0f49bfbd
JL		 3734 if (tg3_flag(tp, CLKREQ_BUG))
3735 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
3736 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 3737
1da177e4
LT		 3738 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
3739 tw32(TG3PCI_MISC_HOST_CTRL,
3740 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
3741
c866b7ea 3742 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
63c3a66f 3743 tg3_flag(tp, WOL_ENABLE);
05ac4cb7 3744
63c3a66f 3745 if (tg3_flag(tp, USE_PHYLIB)) {
0a459aac 3746 do_low_power = false;
f07e9af3 3747 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
80096068 3748 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
b02fd9e3 3749 struct phy_device *phydev;
0a459aac 3750 u32 phyid, advertising;
b02fd9e3 3751
3f0e3ad7 3752 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 3753
80096068 3754 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
b02fd9e3 3755
c6700ce2
MC		 3756 tp->link_config.speed = phydev->speed;
3757 tp->link_config.duplex = phydev->duplex;
3758 tp->link_config.autoneg = phydev->autoneg;
3759 tp->link_config.advertising = phydev->advertising;
b02fd9e3
MC		 3760
3761 advertising = ADVERTISED_TP |
3762 ADVERTISED_Pause |
3763 ADVERTISED_Autoneg |
3764 ADVERTISED_10baseT_Half;
3765
63c3a66f
JP		 3766 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
3767 if (tg3_flag(tp, WOL_SPEED_100MB))
b02fd9e3
MC		 3768 advertising |=
3769 ADVERTISED_100baseT_Half |
3770 ADVERTISED_100baseT_Full |
3771 ADVERTISED_10baseT_Full;
3772 else
3773 advertising |= ADVERTISED_10baseT_Full;
3774 }
3775
3776 phydev->advertising = advertising;
3777
3778 phy_start_aneg(phydev);
0a459aac
MC		 3779
3780 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 3781 if (phyid != PHY_ID_BCMAC131) {
3782 phyid &= PHY_BCM_OUI_MASK;
3783 if (phyid == PHY_BCM_OUI_1 ||
3784 phyid == PHY_BCM_OUI_2 ||
3785 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 3786 do_low_power = true;
3787 }
b02fd9e3 3788 }
dd477003 3789 } else {
2023276e 3790 do_low_power = true;
0a459aac 3791
c6700ce2 3792 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
80096068 3793 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
1da177e4 3794
2855b9fe 3795 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
dd477003 3796 tg3_setup_phy(tp, 0);
1da177e4
LT		 3797 }
3798
b5d3772c
MC		 3799 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3800 u32 val;
3801
3802 val = tr32(GRC_VCPU_EXT_CTRL);
3803 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
63c3a66f 3804 } else if (!tg3_flag(tp, ENABLE_ASF)) {
6921d201
MC		 3805 int i;
3806 u32 val;
3807
3808 for (i = 0; i < 200; i++) {
3809 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
3810 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3811 break;
3812 msleep(1);
3813 }
3814 }
63c3a66f 3815 if (tg3_flag(tp, WOL_CAP))
a85feb8c
GZ		 3816 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
3817 WOL_DRV_STATE_SHUTDOWN |
3818 WOL_DRV_WOL |
3819 WOL_SET_MAGIC_PKT);
6921d201 3820
05ac4cb7 3821 if (device_should_wake) {
1da177e4
LT		 3822 u32 mac_mode;
3823
f07e9af3 3824 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
b4bd2929
MC		 3825 if (do_low_power &&
3826 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
3827 tg3_phy_auxctl_write(tp,
3828 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
3829 MII_TG3_AUXCTL_PCTL_WOL_EN |
3830 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3831 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
dd477003
MC		 3832 udelay(40);
3833 }
1da177e4 3834
f07e9af3 3835 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3f7045c1
MC		 3836 mac_mode = MAC_MODE_PORT_MODE_GMII;
3837 else
3838 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 3839
e8f3f6ca
MC		 3840 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
3841 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3842 ASIC_REV_5700) {
63c3a66f 3843 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
e8f3f6ca
MC		 3844 SPEED_100 : SPEED_10;
3845 if (tg3_5700_link_polarity(tp, speed))
3846 mac_mode |= MAC_MODE_LINK_POLARITY;
3847 else
3848 mac_mode &= ~MAC_MODE_LINK_POLARITY;
3849 }
1da177e4
LT		 3850 } else {
3851 mac_mode = MAC_MODE_PORT_MODE_TBI;
3852 }
3853
63c3a66f 3854 if (!tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 3855 tw32(MAC_LED_CTRL, tp->led_ctrl);
3856
05ac4cb7 3857 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
63c3a66f
JP		 3858 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
3859 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
05ac4cb7 3860 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 3861
63c3a66f 3862 if (tg3_flag(tp, ENABLE_APE))
d2394e6b
MC		 3863 mac_mode |= MAC_MODE_APE_TX_EN |
3864 MAC_MODE_APE_RX_EN |
3865 MAC_MODE_TDE_ENABLE;
3bda1258 3866
1da177e4
LT		 3867 tw32_f(MAC_MODE, mac_mode);
3868 udelay(100);
3869
3870 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
3871 udelay(10);
3872 }
3873
63c3a66f 3874 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
1da177e4
LT		 3875 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3876 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
3877 u32 base_val;
3878
3879 base_val = tp->pci_clock_ctrl;
3880 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
3881 CLOCK_CTRL_TXCLK_DISABLE);
3882
b401e9e2
MC		 3883 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
3884 CLOCK_CTRL_PWRDOWN_PLL133, 40);
63c3a66f
JP		 3885 } else if (tg3_flag(tp, 5780_CLASS) ||
3886 tg3_flag(tp, CPMU_PRESENT) ||
6ff6f81d 3887 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4cf78e4f 3888 /* do nothing */
63c3a66f 3889 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
1da177e4
LT		 3890 u32 newbits1, newbits2;
3891
3892 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3893 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3894 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
3895 CLOCK_CTRL_TXCLK_DISABLE |
3896 CLOCK_CTRL_ALTCLK);
3897 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
63c3a66f 3898 } else if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 3899 newbits1 = CLOCK_CTRL_625_CORE;
3900 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
3901 } else {
3902 newbits1 = CLOCK_CTRL_ALTCLK;
3903 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3904 }
3905
b401e9e2
MC		 3906 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
3907 40);
1da177e4 3908
b401e9e2
MC		 3909 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
3910 40);
1da177e4 3911
63c3a66f 3912 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 3913 u32 newbits3;
3914
3915 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3916 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3917 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
3918 CLOCK_CTRL_TXCLK_DISABLE |
3919 CLOCK_CTRL_44MHZ_CORE);
3920 } else {
3921 newbits3 = CLOCK_CTRL_44MHZ_CORE;
3922 }
3923
b401e9e2
MC		 3924 tw32_wait_f(TG3PCI_CLOCK_CTRL,
3925 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 3926 }
3927 }
3928
63c3a66f 3929 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
0a459aac 3930 tg3_power_down_phy(tp, do_low_power);
6921d201 3931
cd0d7228 3932 tg3_frob_aux_power(tp, true);
1da177e4
LT		 3933
3934 /* Workaround for unstable PLL clock */
3935 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
3936 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
3937 u32 val = tr32(0x7d00);
3938
3939 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3940 tw32(0x7d00, val);
63c3a66f 3941 if (!tg3_flag(tp, ENABLE_ASF)) {
ec41c7df
MC		 3942 int err;
3943
3944 err = tg3_nvram_lock(tp);
1da177e4 3945 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 3946 if (!err)
3947 tg3_nvram_unlock(tp);
6921d201 3948 }
1da177e4
LT		 3949 }
3950
bbadf503
MC		 3951 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3952
c866b7ea
RW		 3953 return 0;
3954}
12dac075 3955
c866b7ea
RW		 3956static void tg3_power_down(struct tg3 *tp)
3957{
3958 tg3_power_down_prepare(tp);
1da177e4 3959
63c3a66f 3960 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
c866b7ea 3961 pci_set_power_state(tp->pdev, PCI_D3hot);
1da177e4
LT		 3962}
3963
1da177e4
LT		 3964static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3965{
3966 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3967 case MII_TG3_AUX_STAT_10HALF:
3968 *speed = SPEED_10;
3969 *duplex = DUPLEX_HALF;
3970 break;
3971
3972 case MII_TG3_AUX_STAT_10FULL:
3973 *speed = SPEED_10;
3974 *duplex = DUPLEX_FULL;
3975 break;
3976
3977 case MII_TG3_AUX_STAT_100HALF:
3978 *speed = SPEED_100;
3979 *duplex = DUPLEX_HALF;
3980 break;
3981
3982 case MII_TG3_AUX_STAT_100FULL:
3983 *speed = SPEED_100;
3984 *duplex = DUPLEX_FULL;
3985 break;
3986
3987 case MII_TG3_AUX_STAT_1000HALF:
3988 *speed = SPEED_1000;
3989 *duplex = DUPLEX_HALF;
3990 break;
3991
3992 case MII_TG3_AUX_STAT_1000FULL:
3993 *speed = SPEED_1000;
3994 *duplex = DUPLEX_FULL;
3995 break;
3996
3997 default:
f07e9af3 3998 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
715116a1
MC		 3999 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4000 SPEED_10;
4001 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4002 DUPLEX_HALF;
4003 break;
4004 }
e740522e
MC		 4005 *speed = SPEED_UNKNOWN;
4006 *duplex = DUPLEX_UNKNOWN;
1da177e4 4007 break;
855e1111 4008 }
1da177e4
LT		 4009}
4010
42b64a45 4011static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
1da177e4 4012{
42b64a45
MC		 4013 int err = 0;
4014 u32 val, new_adv;
1da177e4 4015
42b64a45 4016 new_adv = ADVERTISE_CSMA;
202ff1c2 4017 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
f88788f0 4018 new_adv |= mii_advertise_flowctrl(flowctrl);
1da177e4 4019
42b64a45
MC		 4020 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4021 if (err)
4022 goto done;
ba4d07a8 4023
4f272096
MC		 4024 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4025 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
ba4d07a8 4026
4f272096
MC		 4027 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4028 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
4029 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
ba4d07a8 4030
4f272096
MC		 4031 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4032 if (err)
4033 goto done;
4034 }
1da177e4 4035
42b64a45
MC		 4036 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4037 goto done;
52b02d04 4038
42b64a45
MC		 4039 tw32(TG3_CPMU_EEE_MODE,
4040 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
52b02d04 4041
daf3ec68 4042 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
42b64a45
MC		 4043 if (!err) {
4044 u32 err2;
52b02d04 4045
b715ce94
MC		 4046 val = 0;
4047 /* Advertise 100-BaseTX EEE ability */
4048 if (advertise & ADVERTISED_100baseT_Full)
4049 val |= MDIO_AN_EEE_ADV_100TX;
4050 /* Advertise 1000-BaseT EEE ability */
4051 if (advertise & ADVERTISED_1000baseT_Full)
4052 val |= MDIO_AN_EEE_ADV_1000T;
4053 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4054 if (err)
4055 val = 0;
4056
21a00ab2
MC		 4057 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
4058 case ASIC_REV_5717:
4059 case ASIC_REV_57765:
55086ad9 4060 case ASIC_REV_57766:
21a00ab2 4061 case ASIC_REV_5719:
b715ce94
MC		 4062 /* If we advertised any eee advertisements above... */
4063 if (val)
4064 val = MII_TG3_DSP_TAP26_ALNOKO |
4065 MII_TG3_DSP_TAP26_RMRXSTO |
4066 MII_TG3_DSP_TAP26_OPCSINPT;
21a00ab2 4067 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
be671947
MC		 4068 /* Fall through */
4069 case ASIC_REV_5720:
c65a17f4 4070 case ASIC_REV_5762:
be671947
MC		 4071 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4072 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4073 MII_TG3_DSP_CH34TP2_HIBW01);
21a00ab2 4074 }
52b02d04 4075
daf3ec68 4076 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
42b64a45
MC		 4077 if (!err)
4078 err = err2;
4079 }
4080
4081done:
4082 return err;
4083}
4084
4085static void tg3_phy_copper_begin(struct tg3 *tp)
4086{
d13ba512
MC		 4087 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4088 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4089 u32 adv, fc;
4090
4091 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
4092 adv = ADVERTISED_10baseT_Half |
4093 ADVERTISED_10baseT_Full;
4094 if (tg3_flag(tp, WOL_SPEED_100MB))
4095 adv |= ADVERTISED_100baseT_Half |
4096 ADVERTISED_100baseT_Full;
4097
4098 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
42b64a45 4099 } else {
d13ba512
MC		 4100 adv = tp->link_config.advertising;
4101 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4102 adv &= ~(ADVERTISED_1000baseT_Half |
4103 ADVERTISED_1000baseT_Full);
4104
4105 fc = tp->link_config.flowctrl;
52b02d04 4106 }
52b02d04 4107
d13ba512 4108 tg3_phy_autoneg_cfg(tp, adv, fc);
52b02d04 4109
d13ba512
MC		 4110 tg3_writephy(tp, MII_BMCR,
4111 BMCR_ANENABLE | BMCR_ANRESTART);
4112 } else {
4113 int i;
1da177e4
LT		 4114 u32 bmcr, orig_bmcr;
4115
4116 tp->link_config.active_speed = tp->link_config.speed;
4117 tp->link_config.active_duplex = tp->link_config.duplex;
4118
4119 bmcr = 0;
4120 switch (tp->link_config.speed) {
4121 default:
4122 case SPEED_10:
4123 break;
4124
4125 case SPEED_100:
4126 bmcr |= BMCR_SPEED100;
4127 break;
4128
4129 case SPEED_1000:
221c5637 4130 bmcr |= BMCR_SPEED1000;
1da177e4 4131 break;
855e1111 4132 }
1da177e4
LT		 4133
4134 if (tp->link_config.duplex == DUPLEX_FULL)
4135 bmcr |= BMCR_FULLDPLX;
4136
4137 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4138 (bmcr != orig_bmcr)) {
4139 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4140 for (i = 0; i < 1500; i++) {
4141 u32 tmp;
4142
4143 udelay(10);
4144 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4145 tg3_readphy(tp, MII_BMSR, &tmp))
4146 continue;
4147 if (!(tmp & BMSR_LSTATUS)) {
4148 udelay(40);
4149 break;
4150 }
4151 }
4152 tg3_writephy(tp, MII_BMCR, bmcr);
4153 udelay(40);
4154 }
1da177e4
LT		 4155 }
4156}
4157
4158static int tg3_init_5401phy_dsp(struct tg3 *tp)
4159{
4160 int err;
4161
4162 /* Turn off tap power management. */
4163 /* Set Extended packet length bit */
b4bd2929 4164 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
1da177e4 4165
6ee7c0a0
MC		 4166 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4167 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4168 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4169 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4170 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
1da177e4
LT		 4171
4172 udelay(40);
4173
4174 return err;
4175}
4176
e2bf73e7 4177static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
1da177e4 4178{
e2bf73e7 4179 u32 advmsk, tgtadv, advertising;
3600d918 4180
e2bf73e7
MC		 4181 advertising = tp->link_config.advertising;
4182 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
1da177e4 4183
e2bf73e7
MC		 4184 advmsk = ADVERTISE_ALL;
4185 if (tp->link_config.active_duplex == DUPLEX_FULL) {
f88788f0 4186 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
e2bf73e7
MC		 4187 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4188 }
1da177e4 4189
e2bf73e7
MC		 4190 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4191 return false;
4192
4193 if ((*lcladv & advmsk) != tgtadv)
4194 return false;
b99d2a57 4195
f07e9af3 4196 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1da177e4
LT		 4197 u32 tg3_ctrl;
4198
e2bf73e7 4199 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
3600d918 4200
221c5637 4201 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
e2bf73e7 4202 return false;
1da177e4 4203
3198e07f
MC		 4204 if (tgtadv &&
4205 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4206 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) {
4207 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4208 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4209 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4210 } else {
4211 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4212 }
4213
e2bf73e7
MC		 4214 if (tg3_ctrl != tgtadv)
4215 return false;
ef167e27
MC		 4216 }
4217
e2bf73e7 4218 return true;
ef167e27
MC		 4219}
4220
859edb26
MC		 4221static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4222{
4223 u32 lpeth = 0;
4224
4225 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4226 u32 val;
4227
4228 if (tg3_readphy(tp, MII_STAT1000, &val))
4229 return false;
4230
4231 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4232 }
4233
4234 if (tg3_readphy(tp, MII_LPA, rmtadv))
4235 return false;
4236
4237 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4238 tp->link_config.rmt_adv = lpeth;
4239
4240 return true;
4241}
4242
f4a46d1f
NNS		 4243static bool tg3_test_and_report_link_chg(struct tg3 *tp, int curr_link_up)
4244{
4245 if (curr_link_up != tp->link_up) {
4246 if (curr_link_up) {
4247 tg3_carrier_on(tp);
4248 } else {
4249 tg3_carrier_off(tp);
4250 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4251 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4252 }
4253
4254 tg3_link_report(tp);
4255 return true;
4256 }
4257
4258 return false;
4259}
4260
1da177e4
LT		 4261static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
4262{
4263 int current_link_up;
f833c4c1 4264 u32 bmsr, val;
ef167e27 4265 u32 lcl_adv, rmt_adv;
1da177e4
LT		 4266 u16 current_speed;
4267 u8 current_duplex;
4268 int i, err;
4269
4270 tw32(MAC_EVENT, 0);
4271
4272 tw32_f(MAC_STATUS,
4273 (MAC_STATUS_SYNC_CHANGED |
4274 MAC_STATUS_CFG_CHANGED |
4275 MAC_STATUS_MI_COMPLETION |
4276 MAC_STATUS_LNKSTATE_CHANGED));
4277 udelay(40);
4278
8ef21428
MC		 4279 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4280 tw32_f(MAC_MI_MODE,
4281 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4282 udelay(80);
4283 }
1da177e4 4284
b4bd2929 4285 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
1da177e4
LT		 4286
4287 /* Some third-party PHYs need to be reset on link going
4288 * down.
4289 */
4290 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
4291 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
4292 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
f4a46d1f 4293 tp->link_up) {
1da177e4
LT		 4294 tg3_readphy(tp, MII_BMSR, &bmsr);
4295 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4296 !(bmsr & BMSR_LSTATUS))
4297 force_reset = 1;
4298 }
4299 if (force_reset)
4300 tg3_phy_reset(tp);
4301
79eb6904 4302 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 4303 tg3_readphy(tp, MII_BMSR, &bmsr);
4304 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
63c3a66f 4305 !tg3_flag(tp, INIT_COMPLETE))
1da177e4
LT		 4306 bmsr = 0;
4307
4308 if (!(bmsr & BMSR_LSTATUS)) {
4309 err = tg3_init_5401phy_dsp(tp);
4310 if (err)
4311 return err;
4312
4313 tg3_readphy(tp, MII_BMSR, &bmsr);
4314 for (i = 0; i < 1000; i++) {
4315 udelay(10);
4316 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4317 (bmsr & BMSR_LSTATUS)) {
4318 udelay(40);
4319 break;
4320 }
4321 }
4322
79eb6904
MC		 4323 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4324 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 4325 !(bmsr & BMSR_LSTATUS) &&
4326 tp->link_config.active_speed == SPEED_1000) {
4327 err = tg3_phy_reset(tp);
4328 if (!err)
4329 err = tg3_init_5401phy_dsp(tp);
4330 if (err)
4331 return err;
4332 }
4333 }
4334 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4335 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
4336 /* 5701 {A0,B0} CRC bug workaround */
4337 tg3_writephy(tp, 0x15, 0x0a75);
f08aa1a8
MC		 4338 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4339 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4340 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
1da177e4
LT		 4341 }
4342
4343 /* Clear pending interrupts... */
f833c4c1
MC		 4344 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4345 tg3_readphy(tp, MII_TG3_ISTAT, &val);
1da177e4 4346
f07e9af3 4347 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
1da177e4 4348 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
f07e9af3 4349 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
1da177e4
LT		 4350 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4351
4352 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
4353 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
4354 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4355 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4356 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4357 else
4358 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4359 }
4360
4361 current_link_up = 0;
e740522e
MC		 4362 current_speed = SPEED_UNKNOWN;
4363 current_duplex = DUPLEX_UNKNOWN;
e348c5e7 4364 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
859edb26 4365 tp->link_config.rmt_adv = 0;
1da177e4 4366
f07e9af3 4367 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
15ee95c3
MC		 4368 err = tg3_phy_auxctl_read(tp,
4369 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4370 &val);
4371 if (!err && !(val & (1 << 10))) {
b4bd2929
MC		 4372 tg3_phy_auxctl_write(tp,
4373 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4374 val | (1 << 10));
1da177e4
LT		 4375 goto relink;
4376 }
4377 }
4378
4379 bmsr = 0;
4380 for (i = 0; i < 100; i++) {
4381 tg3_readphy(tp, MII_BMSR, &bmsr);
4382 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4383 (bmsr & BMSR_LSTATUS))
4384 break;
4385 udelay(40);
4386 }
4387
4388 if (bmsr & BMSR_LSTATUS) {
4389 u32 aux_stat, bmcr;
4390
4391 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4392 for (i = 0; i < 2000; i++) {
4393 udelay(10);
4394 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4395 aux_stat)
4396 break;
4397 }
4398
4399 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4400 &current_speed,
4401 &current_duplex);
4402
4403 bmcr = 0;
4404 for (i = 0; i < 200; i++) {
4405 tg3_readphy(tp, MII_BMCR, &bmcr);
4406 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4407 continue;
4408 if (bmcr && bmcr != 0x7fff)
4409 break;
4410 udelay(10);
4411 }
4412
ef167e27
MC		 4413 lcl_adv = 0;
4414 rmt_adv = 0;
1da177e4 4415
ef167e27
MC		 4416 tp->link_config.active_speed = current_speed;
4417 tp->link_config.active_duplex = current_duplex;
4418
4419 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4420 if ((bmcr & BMCR_ANENABLE) &&
e2bf73e7 4421 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
859edb26 4422 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
e2bf73e7 4423 current_link_up = 1;
1da177e4
LT		 4424 } else {
4425 if (!(bmcr & BMCR_ANENABLE) &&
4426 tp->link_config.speed == current_speed &&
ef167e27
MC		 4427 tp->link_config.duplex == current_duplex &&
4428 tp->link_config.flowctrl ==
4429 tp->link_config.active_flowctrl) {
1da177e4 4430 current_link_up = 1;
1da177e4
LT		 4431 }
4432 }
4433
ef167e27 4434 if (current_link_up == 1 &&
e348c5e7
MC		 4435 tp->link_config.active_duplex == DUPLEX_FULL) {
4436 u32 reg, bit;
4437
4438 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4439 reg = MII_TG3_FET_GEN_STAT;
4440 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4441 } else {
4442 reg = MII_TG3_EXT_STAT;
4443 bit = MII_TG3_EXT_STAT_MDIX;
4444 }
4445
4446 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4447 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4448
ef167e27 4449 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
e348c5e7 4450 }
1da177e4
LT		 4451 }
4452
1da177e4 4453relink:
80096068 4454 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
1da177e4
LT		 4455 tg3_phy_copper_begin(tp);
4456
f833c4c1 4457 tg3_readphy(tp, MII_BMSR, &bmsr);
06c03c02
MB		 4458 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4459 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
1da177e4
LT		 4460 current_link_up = 1;
4461 }
4462
4463 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4464 if (current_link_up == 1) {
4465 if (tp->link_config.active_speed == SPEED_100 ||
4466 tp->link_config.active_speed == SPEED_10)
4467 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4468 else
4469 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
f07e9af3 4470 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7f97a4bd
MC		 4471 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4472 else
1da177e4
LT		 4473 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4474
4475 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4476 if (tp->link_config.active_duplex == DUPLEX_HALF)
4477 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4478
1da177e4 4479 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 4480 if (current_link_up == 1 &&
4481 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 4482 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 4483 else
4484 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 4485 }
4486
4487 /* ??? Without this setting Netgear GA302T PHY does not
4488 * ??? send/receive packets...
4489 */
79eb6904 4490 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
1da177e4
LT		 4491 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
4492 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
4493 tw32_f(MAC_MI_MODE, tp->mi_mode);
4494 udelay(80);
4495 }
4496
4497 tw32_f(MAC_MODE, tp->mac_mode);
4498 udelay(40);
4499
52b02d04
MC		 4500 tg3_phy_eee_adjust(tp, current_link_up);
4501
63c3a66f 4502 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 4503 /* Polled via timer. */
4504 tw32_f(MAC_EVENT, 0);
4505 } else {
4506 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4507 }
4508 udelay(40);
4509
4510 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
4511 current_link_up == 1 &&
4512 tp->link_config.active_speed == SPEED_1000 &&
63c3a66f 4513 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
1da177e4
LT		 4514 udelay(120);
4515 tw32_f(MAC_STATUS,
4516 (MAC_STATUS_SYNC_CHANGED |
4517 MAC_STATUS_CFG_CHANGED));
4518 udelay(40);
4519 tg3_write_mem(tp,
4520 NIC_SRAM_FIRMWARE_MBOX,
4521 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
4522 }
4523
5e7dfd0f 4524 /* Prevent send BD corruption. */
63c3a66f 4525 if (tg3_flag(tp, CLKREQ_BUG)) {
5e7dfd0f
MC		 4526 if (tp->link_config.active_speed == SPEED_100 ||
4527 tp->link_config.active_speed == SPEED_10)
0f49bfbd
JL		 4528 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
4529 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 4530 else
0f49bfbd
JL		 4531 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4532 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f
MC		 4533 }
4534
f4a46d1f 4535 tg3_test_and_report_link_chg(tp, current_link_up);
1da177e4
LT		 4536
4537 return 0;
4538}
4539
4540struct tg3_fiber_aneginfo {
4541 int state;
4542#define ANEG_STATE_UNKNOWN 0
4543#define ANEG_STATE_AN_ENABLE 1
4544#define ANEG_STATE_RESTART_INIT 2
4545#define ANEG_STATE_RESTART 3
4546#define ANEG_STATE_DISABLE_LINK_OK 4
4547#define ANEG_STATE_ABILITY_DETECT_INIT 5
4548#define ANEG_STATE_ABILITY_DETECT 6
4549#define ANEG_STATE_ACK_DETECT_INIT 7
4550#define ANEG_STATE_ACK_DETECT 8
4551#define ANEG_STATE_COMPLETE_ACK_INIT 9
4552#define ANEG_STATE_COMPLETE_ACK 10
4553#define ANEG_STATE_IDLE_DETECT_INIT 11
4554#define ANEG_STATE_IDLE_DETECT 12
4555#define ANEG_STATE_LINK_OK 13
4556#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
4557#define ANEG_STATE_NEXT_PAGE_WAIT 15
4558
4559 u32 flags;
4560#define MR_AN_ENABLE 0x00000001
4561#define MR_RESTART_AN 0x00000002
4562#define MR_AN_COMPLETE 0x00000004
4563#define MR_PAGE_RX 0x00000008
4564#define MR_NP_LOADED 0x00000010
4565#define MR_TOGGLE_TX 0x00000020
4566#define MR_LP_ADV_FULL_DUPLEX 0x00000040
4567#define MR_LP_ADV_HALF_DUPLEX 0x00000080
4568#define MR_LP_ADV_SYM_PAUSE 0x00000100
4569#define MR_LP_ADV_ASYM_PAUSE 0x00000200
4570#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
4571#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
4572#define MR_LP_ADV_NEXT_PAGE 0x00001000
4573#define MR_TOGGLE_RX 0x00002000
4574#define MR_NP_RX 0x00004000
4575
4576#define MR_LINK_OK 0x80000000
4577
4578 unsigned long link_time, cur_time;
4579
4580 u32 ability_match_cfg;
4581 int ability_match_count;
4582
4583 char ability_match, idle_match, ack_match;
4584
4585 u32 txconfig, rxconfig;
4586#define ANEG_CFG_NP 0x00000080
4587#define ANEG_CFG_ACK 0x00000040
4588#define ANEG_CFG_RF2 0x00000020
4589#define ANEG_CFG_RF1 0x00000010
4590#define ANEG_CFG_PS2 0x00000001
4591#define ANEG_CFG_PS1 0x00008000
4592#define ANEG_CFG_HD 0x00004000
4593#define ANEG_CFG_FD 0x00002000
4594#define ANEG_CFG_INVAL 0x00001f06
4595
4596};
4597#define ANEG_OK 0
4598#define ANEG_DONE 1
4599#define ANEG_TIMER_ENAB 2
4600#define ANEG_FAILED -1
4601
4602#define ANEG_STATE_SETTLE_TIME 10000
4603
4604static int tg3_fiber_aneg_smachine(struct tg3 *tp,
4605 struct tg3_fiber_aneginfo *ap)
4606{
5be73b47 4607 u16 flowctrl;
1da177e4
LT		 4608 unsigned long delta;
4609 u32 rx_cfg_reg;
4610 int ret;
4611
4612 if (ap->state == ANEG_STATE_UNKNOWN) {
4613 ap->rxconfig = 0;
4614 ap->link_time = 0;
4615 ap->cur_time = 0;
4616 ap->ability_match_cfg = 0;
4617 ap->ability_match_count = 0;
4618 ap->ability_match = 0;
4619 ap->idle_match = 0;
4620 ap->ack_match = 0;
4621 }
4622 ap->cur_time++;
4623
4624 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
4625 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
4626
4627 if (rx_cfg_reg != ap->ability_match_cfg) {
4628 ap->ability_match_cfg = rx_cfg_reg;
4629 ap->ability_match = 0;
4630 ap->ability_match_count = 0;
4631 } else {
4632 if (++ap->ability_match_count > 1) {
4633 ap->ability_match = 1;
4634 ap->ability_match_cfg = rx_cfg_reg;
4635 }
4636 }
4637 if (rx_cfg_reg & ANEG_CFG_ACK)
4638 ap->ack_match = 1;
4639 else
4640 ap->ack_match = 0;
4641
4642 ap->idle_match = 0;
4643 } else {
4644 ap->idle_match = 1;
4645 ap->ability_match_cfg = 0;
4646 ap->ability_match_count = 0;
4647 ap->ability_match = 0;
4648 ap->ack_match = 0;
4649
4650 rx_cfg_reg = 0;
4651 }
4652
4653 ap->rxconfig = rx_cfg_reg;
4654 ret = ANEG_OK;
4655
33f401ae 4656 switch (ap->state) {
1da177e4
LT		 4657 case ANEG_STATE_UNKNOWN:
4658 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
4659 ap->state = ANEG_STATE_AN_ENABLE;
4660
4661 /* fallthru */
4662 case ANEG_STATE_AN_ENABLE:
4663 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
4664 if (ap->flags & MR_AN_ENABLE) {
4665 ap->link_time = 0;
4666 ap->cur_time = 0;
4667 ap->ability_match_cfg = 0;
4668 ap->ability_match_count = 0;
4669 ap->ability_match = 0;
4670 ap->idle_match = 0;
4671 ap->ack_match = 0;
4672
4673 ap->state = ANEG_STATE_RESTART_INIT;
4674 } else {
4675 ap->state = ANEG_STATE_DISABLE_LINK_OK;
4676 }
4677 break;
4678
4679 case ANEG_STATE_RESTART_INIT:
4680 ap->link_time = ap->cur_time;
4681 ap->flags &= ~(MR_NP_LOADED);
4682 ap->txconfig = 0;
4683 tw32(MAC_TX_AUTO_NEG, 0);
4684 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4685 tw32_f(MAC_MODE, tp->mac_mode);
4686 udelay(40);
4687
4688 ret = ANEG_TIMER_ENAB;
4689 ap->state = ANEG_STATE_RESTART;
4690
4691 /* fallthru */
4692 case ANEG_STATE_RESTART:
4693 delta = ap->cur_time - ap->link_time;
859a5887 4694 if (delta > ANEG_STATE_SETTLE_TIME)
1da177e4 4695 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
859a5887 4696 else
1da177e4 4697 ret = ANEG_TIMER_ENAB;
1da177e4
LT		 4698 break;
4699
4700 case ANEG_STATE_DISABLE_LINK_OK:
4701 ret = ANEG_DONE;
4702 break;
4703
4704 case ANEG_STATE_ABILITY_DETECT_INIT:
4705 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 4706 ap->txconfig = ANEG_CFG_FD;
4707 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4708 if (flowctrl & ADVERTISE_1000XPAUSE)
4709 ap->txconfig |= ANEG_CFG_PS1;
4710 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4711 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 4712 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4713 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4714 tw32_f(MAC_MODE, tp->mac_mode);
4715 udelay(40);
4716
4717 ap->state = ANEG_STATE_ABILITY_DETECT;
4718 break;
4719
4720 case ANEG_STATE_ABILITY_DETECT:
859a5887 4721 if (ap->ability_match != 0 && ap->rxconfig != 0)
1da177e4 4722 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1da177e4
LT		 4723 break;
4724
4725 case ANEG_STATE_ACK_DETECT_INIT:
4726 ap->txconfig |= ANEG_CFG_ACK;
4727 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4728 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4729 tw32_f(MAC_MODE, tp->mac_mode);
4730 udelay(40);
4731
4732 ap->state = ANEG_STATE_ACK_DETECT;
4733
4734 /* fallthru */
4735 case ANEG_STATE_ACK_DETECT:
4736 if (ap->ack_match != 0) {
4737 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
4738 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
4739 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
4740 } else {
4741 ap->state = ANEG_STATE_AN_ENABLE;
4742 }
4743 } else if (ap->ability_match != 0 &&
4744 ap->rxconfig == 0) {
4745 ap->state = ANEG_STATE_AN_ENABLE;
4746 }
4747 break;
4748
4749 case ANEG_STATE_COMPLETE_ACK_INIT:
4750 if (ap->rxconfig & ANEG_CFG_INVAL) {
4751 ret = ANEG_FAILED;
4752 break;
4753 }
4754 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
4755 MR_LP_ADV_HALF_DUPLEX |
4756 MR_LP_ADV_SYM_PAUSE |
4757 MR_LP_ADV_ASYM_PAUSE |
4758 MR_LP_ADV_REMOTE_FAULT1 |
4759 MR_LP_ADV_REMOTE_FAULT2 |
4760 MR_LP_ADV_NEXT_PAGE |
4761 MR_TOGGLE_RX |
4762 MR_NP_RX);
4763 if (ap->rxconfig & ANEG_CFG_FD)
4764 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
4765 if (ap->rxconfig & ANEG_CFG_HD)
4766 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
4767 if (ap->rxconfig & ANEG_CFG_PS1)
4768 ap->flags |= MR_LP_ADV_SYM_PAUSE;
4769 if (ap->rxconfig & ANEG_CFG_PS2)
4770 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
4771 if (ap->rxconfig & ANEG_CFG_RF1)
4772 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
4773 if (ap->rxconfig & ANEG_CFG_RF2)
4774 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
4775 if (ap->rxconfig & ANEG_CFG_NP)
4776 ap->flags |= MR_LP_ADV_NEXT_PAGE;
4777
4778 ap->link_time = ap->cur_time;
4779
4780 ap->flags ^= (MR_TOGGLE_TX);
4781 if (ap->rxconfig & 0x0008)
4782 ap->flags |= MR_TOGGLE_RX;
4783 if (ap->rxconfig & ANEG_CFG_NP)
4784 ap->flags |= MR_NP_RX;
4785 ap->flags |= MR_PAGE_RX;
4786
4787 ap->state = ANEG_STATE_COMPLETE_ACK;
4788 ret = ANEG_TIMER_ENAB;
4789 break;
4790
4791 case ANEG_STATE_COMPLETE_ACK:
4792 if (ap->ability_match != 0 &&
4793 ap->rxconfig == 0) {
4794 ap->state = ANEG_STATE_AN_ENABLE;
4795 break;
4796 }
4797 delta = ap->cur_time - ap->link_time;
4798 if (delta > ANEG_STATE_SETTLE_TIME) {
4799 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
4800 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4801 } else {
4802 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
4803 !(ap->flags & MR_NP_RX)) {
4804 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4805 } else {
4806 ret = ANEG_FAILED;
4807 }
4808 }
4809 }
4810 break;
4811
4812 case ANEG_STATE_IDLE_DETECT_INIT:
4813 ap->link_time = ap->cur_time;
4814 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4815 tw32_f(MAC_MODE, tp->mac_mode);
4816 udelay(40);
4817
4818 ap->state = ANEG_STATE_IDLE_DETECT;
4819 ret = ANEG_TIMER_ENAB;
4820 break;
4821
4822 case ANEG_STATE_IDLE_DETECT:
4823 if (ap->ability_match != 0 &&
4824 ap->rxconfig == 0) {
4825 ap->state = ANEG_STATE_AN_ENABLE;
4826 break;
4827 }
4828 delta = ap->cur_time - ap->link_time;
4829 if (delta > ANEG_STATE_SETTLE_TIME) {
4830 /* XXX another gem from the Broadcom driver :( */
4831 ap->state = ANEG_STATE_LINK_OK;
4832 }
4833 break;
4834
4835 case ANEG_STATE_LINK_OK:
4836 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
4837 ret = ANEG_DONE;
4838 break;
4839
4840 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
4841 /* ??? unimplemented */
4842 break;
4843
4844 case ANEG_STATE_NEXT_PAGE_WAIT:
4845 /* ??? unimplemented */
4846 break;
4847
4848 default:
4849 ret = ANEG_FAILED;
4850 break;
855e1111 4851 }
1da177e4
LT		 4852
4853 return ret;
4854}
4855
5be73b47 4856static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 4857{
4858 int res = 0;
4859 struct tg3_fiber_aneginfo aninfo;
4860 int status = ANEG_FAILED;
4861 unsigned int tick;
4862 u32 tmp;
4863
4864 tw32_f(MAC_TX_AUTO_NEG, 0);
4865
4866 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
4867 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
4868 udelay(40);
4869
4870 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
4871 udelay(40);
4872
4873 memset(&aninfo, 0, sizeof(aninfo));
4874 aninfo.flags |= MR_AN_ENABLE;
4875 aninfo.state = ANEG_STATE_UNKNOWN;
4876 aninfo.cur_time = 0;
4877 tick = 0;
4878 while (++tick < 195000) {
4879 status = tg3_fiber_aneg_smachine(tp, &aninfo);
4880 if (status == ANEG_DONE || status == ANEG_FAILED)
4881 break;
4882
4883 udelay(1);
4884 }
4885
4886 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4887 tw32_f(MAC_MODE, tp->mac_mode);
4888 udelay(40);
4889
5be73b47
MC		 4890 *txflags = aninfo.txconfig;
4891 *rxflags = aninfo.flags;
1da177e4
LT		 4892
4893 if (status == ANEG_DONE &&
4894 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
4895 MR_LP_ADV_FULL_DUPLEX)))
4896 res = 1;
4897
4898 return res;
4899}
4900
4901static void tg3_init_bcm8002(struct tg3 *tp)
4902{
4903 u32 mac_status = tr32(MAC_STATUS);
4904 int i;
4905
4906 /* Reset when initting first time or we have a link. */
63c3a66f 4907 if (tg3_flag(tp, INIT_COMPLETE) &&
1da177e4
LT		 4908 !(mac_status & MAC_STATUS_PCS_SYNCED))
4909 return;
4910
4911 /* Set PLL lock range. */
4912 tg3_writephy(tp, 0x16, 0x8007);
4913
4914 /* SW reset */
4915 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4916
4917 /* Wait for reset to complete. */
4918 /* XXX schedule_timeout() ... */
4919 for (i = 0; i < 500; i++)
4920 udelay(10);
4921
4922 /* Config mode; select PMA/Ch 1 regs. */
4923 tg3_writephy(tp, 0x10, 0x8411);
4924
4925 /* Enable auto-lock and comdet, select txclk for tx. */
4926 tg3_writephy(tp, 0x11, 0x0a10);
4927
4928 tg3_writephy(tp, 0x18, 0x00a0);
4929 tg3_writephy(tp, 0x16, 0x41ff);
4930
4931 /* Assert and deassert POR. */
4932 tg3_writephy(tp, 0x13, 0x0400);
4933 udelay(40);
4934 tg3_writephy(tp, 0x13, 0x0000);
4935
4936 tg3_writephy(tp, 0x11, 0x0a50);
4937 udelay(40);
4938 tg3_writephy(tp, 0x11, 0x0a10);
4939
4940 /* Wait for signal to stabilize */
4941 /* XXX schedule_timeout() ... */
4942 for (i = 0; i < 15000; i++)
4943 udelay(10);
4944
4945 /* Deselect the channel register so we can read the PHYID
4946 * later.
4947 */
4948 tg3_writephy(tp, 0x10, 0x8011);
4949}
4950
4951static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4952{
82cd3d11 4953 u16 flowctrl;
1da177e4
LT		 4954 u32 sg_dig_ctrl, sg_dig_status;
4955 u32 serdes_cfg, expected_sg_dig_ctrl;
4956 int workaround, port_a;
4957 int current_link_up;
4958
4959 serdes_cfg = 0;
4960 expected_sg_dig_ctrl = 0;
4961 workaround = 0;
4962 port_a = 1;
4963 current_link_up = 0;
4964
4965 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4966 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
4967 workaround = 1;
4968 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
4969 port_a = 0;
4970
4971 /* preserve bits 0-11,13,14 for signal pre-emphasis */
4972 /* preserve bits 20-23 for voltage regulator */
4973 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4974 }
4975
4976 sg_dig_ctrl = tr32(SG_DIG_CTRL);
4977
4978 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 4979 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 4980 if (workaround) {
4981 u32 val = serdes_cfg;
4982
4983 if (port_a)
4984 val |= 0xc010000;
4985 else
4986 val |= 0x4010000;
4987 tw32_f(MAC_SERDES_CFG, val);
4988 }
c98f6e3b
MC		 4989
4990 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 4991 }
4992 if (mac_status & MAC_STATUS_PCS_SYNCED) {
4993 tg3_setup_flow_control(tp, 0, 0);
4994 current_link_up = 1;
4995 }
4996 goto out;
4997 }
4998
4999 /* Want auto-negotiation. */
c98f6e3b 5000 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 5001
82cd3d11
MC		 5002 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5003 if (flowctrl & ADVERTISE_1000XPAUSE)
5004 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5005 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5006 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 5007
5008 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
f07e9af3 5009 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3d3ebe74
MC		 5010 tp->serdes_counter &&
5011 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5012 MAC_STATUS_RCVD_CFG)) ==
5013 MAC_STATUS_PCS_SYNCED)) {
5014 tp->serdes_counter--;
5015 current_link_up = 1;
5016 goto out;
5017 }
5018restart_autoneg:
1da177e4
LT		 5019 if (workaround)
5020 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 5021 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 5022 udelay(5);
5023 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5024
3d3ebe74 5025 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5026 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5027 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5028 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 5029 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 5030 mac_status = tr32(MAC_STATUS);
5031
c98f6e3b 5032 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 5033 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 5034 u32 local_adv = 0, remote_adv = 0;
5035
5036 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5037 local_adv |= ADVERTISE_1000XPAUSE;
5038 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5039 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 5040
c98f6e3b 5041 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 5042 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 5043 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 5044 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5045
859edb26
MC		 5046 tp->link_config.rmt_adv =
5047 mii_adv_to_ethtool_adv_x(remote_adv);
5048
1da177e4
LT		 5049 tg3_setup_flow_control(tp, local_adv, remote_adv);
5050 current_link_up = 1;
3d3ebe74 5051 tp->serdes_counter = 0;
f07e9af3 5052 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c98f6e3b 5053 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 5054 if (tp->serdes_counter)
5055 tp->serdes_counter--;
1da177e4
LT		 5056 else {
5057 if (workaround) {
5058 u32 val = serdes_cfg;
5059
5060 if (port_a)
5061 val |= 0xc010000;
5062 else
5063 val |= 0x4010000;
5064
5065 tw32_f(MAC_SERDES_CFG, val);
5066 }
5067
c98f6e3b 5068 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5069 udelay(40);
5070
5071 /* Link parallel detection - link is up */
5072 /* only if we have PCS_SYNC and not */
5073 /* receiving config code words */
5074 mac_status = tr32(MAC_STATUS);
5075 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5076 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5077 tg3_setup_flow_control(tp, 0, 0);
5078 current_link_up = 1;
f07e9af3
MC		 5079 tp->phy_flags |=
5080 TG3_PHYFLG_PARALLEL_DETECT;
3d3ebe74
MC		 5081 tp->serdes_counter =
5082 SERDES_PARALLEL_DET_TIMEOUT;
5083 } else
5084 goto restart_autoneg;
1da177e4
LT		 5085 }
5086 }
3d3ebe74
MC		 5087 } else {
5088 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5089 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5090 }
5091
5092out:
5093 return current_link_up;
5094}
5095
5096static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5097{
5098 int current_link_up = 0;
5099
5cf64b8a 5100 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 5101 goto out;
1da177e4
LT		 5102
5103 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 5104 u32 txflags, rxflags;
1da177e4 5105 int i;
6aa20a22 5106
5be73b47
MC		 5107 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5108 u32 local_adv = 0, remote_adv = 0;
1da177e4 5109
5be73b47
MC		 5110 if (txflags & ANEG_CFG_PS1)
5111 local_adv |= ADVERTISE_1000XPAUSE;
5112 if (txflags & ANEG_CFG_PS2)
5113 local_adv |= ADVERTISE_1000XPSE_ASYM;
5114
5115 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5116 remote_adv |= LPA_1000XPAUSE;
5117 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5118 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5119
859edb26
MC		 5120 tp->link_config.rmt_adv =
5121 mii_adv_to_ethtool_adv_x(remote_adv);
5122
1da177e4
LT		 5123 tg3_setup_flow_control(tp, local_adv, remote_adv);
5124
1da177e4
LT		 5125 current_link_up = 1;
5126 }
5127 for (i = 0; i < 30; i++) {
5128 udelay(20);
5129 tw32_f(MAC_STATUS,
5130 (MAC_STATUS_SYNC_CHANGED |
5131 MAC_STATUS_CFG_CHANGED));
5132 udelay(40);
5133 if ((tr32(MAC_STATUS) &
5134 (MAC_STATUS_SYNC_CHANGED |
5135 MAC_STATUS_CFG_CHANGED)) == 0)
5136 break;
5137 }
5138
5139 mac_status = tr32(MAC_STATUS);
5140 if (current_link_up == 0 &&
5141 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5142 !(mac_status & MAC_STATUS_RCVD_CFG))
5143 current_link_up = 1;
5144 } else {
5be73b47
MC		 5145 tg3_setup_flow_control(tp, 0, 0);
5146
1da177e4
LT		 5147 /* Forcing 1000FD link up. */
5148 current_link_up = 1;
1da177e4
LT		 5149
5150 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5151 udelay(40);
e8f3f6ca
MC		 5152
5153 tw32_f(MAC_MODE, tp->mac_mode);
5154 udelay(40);
1da177e4
LT		 5155 }
5156
5157out:
5158 return current_link_up;
5159}
5160
5161static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
5162{
5163 u32 orig_pause_cfg;
5164 u16 orig_active_speed;
5165 u8 orig_active_duplex;
5166 u32 mac_status;
5167 int current_link_up;
5168 int i;
5169
8d018621 5170 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5171 orig_active_speed = tp->link_config.active_speed;
5172 orig_active_duplex = tp->link_config.active_duplex;
5173
63c3a66f 5174 if (!tg3_flag(tp, HW_AUTONEG) &&
f4a46d1f 5175 tp->link_up &&
63c3a66f 5176 tg3_flag(tp, INIT_COMPLETE)) {
1da177e4
LT		 5177 mac_status = tr32(MAC_STATUS);
5178 mac_status &= (MAC_STATUS_PCS_SYNCED |
5179 MAC_STATUS_SIGNAL_DET |
5180 MAC_STATUS_CFG_CHANGED |
5181 MAC_STATUS_RCVD_CFG);
5182 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5183 MAC_STATUS_SIGNAL_DET)) {
5184 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5185 MAC_STATUS_CFG_CHANGED));
5186 return 0;
5187 }
5188 }
5189
5190 tw32_f(MAC_TX_AUTO_NEG, 0);
5191
5192 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5193 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5194 tw32_f(MAC_MODE, tp->mac_mode);
5195 udelay(40);
5196
79eb6904 5197 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 5198 tg3_init_bcm8002(tp);
5199
5200 /* Enable link change event even when serdes polling. */
5201 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5202 udelay(40);
5203
5204 current_link_up = 0;
859edb26 5205 tp->link_config.rmt_adv = 0;
1da177e4
LT		 5206 mac_status = tr32(MAC_STATUS);
5207
63c3a66f 5208 if (tg3_flag(tp, HW_AUTONEG))
1da177e4
LT		 5209 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5210 else
5211 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5212
898a56f8 5213 tp->napi[0].hw_status->status =
1da177e4 5214 (SD_STATUS_UPDATED |
898a56f8 5215 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 5216
5217 for (i = 0; i < 100; i++) {
5218 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5219 MAC_STATUS_CFG_CHANGED));
5220 udelay(5);
5221 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 5222 MAC_STATUS_CFG_CHANGED |
5223 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 5224 break;
5225 }
5226
5227 mac_status = tr32(MAC_STATUS);
5228 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5229 current_link_up = 0;
3d3ebe74
MC		 5230 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5231 tp->serdes_counter == 0) {
1da177e4
LT		 5232 tw32_f(MAC_MODE, (tp->mac_mode |
5233 MAC_MODE_SEND_CONFIGS));
5234 udelay(1);
5235 tw32_f(MAC_MODE, tp->mac_mode);
5236 }
5237 }
5238
5239 if (current_link_up == 1) {
5240 tp->link_config.active_speed = SPEED_1000;
5241 tp->link_config.active_duplex = DUPLEX_FULL;
5242 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5243 LED_CTRL_LNKLED_OVERRIDE |
5244 LED_CTRL_1000MBPS_ON));
5245 } else {
e740522e
MC		 5246 tp->link_config.active_speed = SPEED_UNKNOWN;
5247 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 5248 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5249 LED_CTRL_LNKLED_OVERRIDE |
5250 LED_CTRL_TRAFFIC_OVERRIDE));
5251 }
5252
f4a46d1f 5253 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
8d018621 5254 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5255 if (orig_pause_cfg != now_pause_cfg ||
5256 orig_active_speed != tp->link_config.active_speed ||
5257 orig_active_duplex != tp->link_config.active_duplex)
5258 tg3_link_report(tp);
5259 }
5260
5261 return 0;
5262}
5263
747e8f8b
MC		 5264static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
5265{
5266 int current_link_up, err = 0;
5267 u32 bmsr, bmcr;
5268 u16 current_speed;
5269 u8 current_duplex;
ef167e27 5270 u32 local_adv, remote_adv;
747e8f8b
MC		 5271
5272 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5273 tw32_f(MAC_MODE, tp->mac_mode);
5274 udelay(40);
5275
5276 tw32(MAC_EVENT, 0);
5277
5278 tw32_f(MAC_STATUS,
5279 (MAC_STATUS_SYNC_CHANGED |
5280 MAC_STATUS_CFG_CHANGED |
5281 MAC_STATUS_MI_COMPLETION |
5282 MAC_STATUS_LNKSTATE_CHANGED));
5283 udelay(40);
5284
5285 if (force_reset)
5286 tg3_phy_reset(tp);
5287
5288 current_link_up = 0;
e740522e
MC		 5289 current_speed = SPEED_UNKNOWN;
5290 current_duplex = DUPLEX_UNKNOWN;
859edb26 5291 tp->link_config.rmt_adv = 0;
747e8f8b
MC		 5292
5293 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5294 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 5295 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
5296 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5297 bmsr |= BMSR_LSTATUS;
5298 else
5299 bmsr &= ~BMSR_LSTATUS;
5300 }
747e8f8b
MC		 5301
5302 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5303
5304 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
f07e9af3 5305 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 5306 /* do nothing, just check for link up at the end */
5307 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
28011cf1 5308 u32 adv, newadv;
747e8f8b
MC		 5309
5310 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
28011cf1
MC		 5311 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5312 ADVERTISE_1000XPAUSE |
5313 ADVERTISE_1000XPSE_ASYM |
5314 ADVERTISE_SLCT);
747e8f8b 5315
28011cf1 5316 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
37f07023 5317 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
747e8f8b 5318
28011cf1
MC		 5319 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5320 tg3_writephy(tp, MII_ADVERTISE, newadv);
747e8f8b
MC		 5321 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5322 tg3_writephy(tp, MII_BMCR, bmcr);
5323
5324 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 5325 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
f07e9af3 5326 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5327
5328 return err;
5329 }
5330 } else {
5331 u32 new_bmcr;
5332
5333 bmcr &= ~BMCR_SPEED1000;
5334 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5335
5336 if (tp->link_config.duplex == DUPLEX_FULL)
5337 new_bmcr |= BMCR_FULLDPLX;
5338
5339 if (new_bmcr != bmcr) {
5340 /* BMCR_SPEED1000 is a reserved bit that needs
5341 * to be set on write.
5342 */
5343 new_bmcr |= BMCR_SPEED1000;
5344
5345 /* Force a linkdown */
f4a46d1f 5346 if (tp->link_up) {
747e8f8b
MC		 5347 u32 adv;
5348
5349 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5350 adv &= ~(ADVERTISE_1000XFULL |
5351 ADVERTISE_1000XHALF |
5352 ADVERTISE_SLCT);
5353 tg3_writephy(tp, MII_ADVERTISE, adv);
5354 tg3_writephy(tp, MII_BMCR, bmcr |
5355 BMCR_ANRESTART |
5356 BMCR_ANENABLE);
5357 udelay(10);
f4a46d1f 5358 tg3_carrier_off(tp);
747e8f8b
MC		 5359 }
5360 tg3_writephy(tp, MII_BMCR, new_bmcr);
5361 bmcr = new_bmcr;
5362 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5363 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 5364 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
5365 ASIC_REV_5714) {
5366 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5367 bmsr |= BMSR_LSTATUS;
5368 else
5369 bmsr &= ~BMSR_LSTATUS;
5370 }
f07e9af3 5371 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5372 }
5373 }
5374
5375 if (bmsr & BMSR_LSTATUS) {
5376 current_speed = SPEED_1000;
5377 current_link_up = 1;
5378 if (bmcr & BMCR_FULLDPLX)
5379 current_duplex = DUPLEX_FULL;
5380 else
5381 current_duplex = DUPLEX_HALF;
5382
ef167e27
MC		 5383 local_adv = 0;
5384 remote_adv = 0;
5385
747e8f8b 5386 if (bmcr & BMCR_ANENABLE) {
ef167e27 5387 u32 common;
747e8f8b
MC		 5388
5389 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5390 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5391 common = local_adv & remote_adv;
5392 if (common & (ADVERTISE_1000XHALF |
5393 ADVERTISE_1000XFULL)) {
5394 if (common & ADVERTISE_1000XFULL)
5395 current_duplex = DUPLEX_FULL;
5396 else
5397 current_duplex = DUPLEX_HALF;
859edb26
MC		 5398
5399 tp->link_config.rmt_adv =
5400 mii_adv_to_ethtool_adv_x(remote_adv);
63c3a66f 5401 } else if (!tg3_flag(tp, 5780_CLASS)) {
57d8b880 5402 /* Link is up via parallel detect */
859a5887 5403 } else {
747e8f8b 5404 current_link_up = 0;
859a5887 5405 }
747e8f8b
MC		 5406 }
5407 }
5408
ef167e27
MC		 5409 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
5410 tg3_setup_flow_control(tp, local_adv, remote_adv);
5411
747e8f8b
MC		 5412 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5413 if (tp->link_config.active_duplex == DUPLEX_HALF)
5414 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5415
5416 tw32_f(MAC_MODE, tp->mac_mode);
5417 udelay(40);
5418
5419 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5420
5421 tp->link_config.active_speed = current_speed;
5422 tp->link_config.active_duplex = current_duplex;
5423
f4a46d1f 5424 tg3_test_and_report_link_chg(tp, current_link_up);
747e8f8b
MC		 5425 return err;
5426}
5427
5428static void tg3_serdes_parallel_detect(struct tg3 *tp)
5429{
3d3ebe74 5430 if (tp->serdes_counter) {
747e8f8b 5431 /* Give autoneg time to complete. */
3d3ebe74 5432 tp->serdes_counter--;
747e8f8b
MC		 5433 return;
5434 }
c6cdf436 5435
f4a46d1f 5436 if (!tp->link_up &&
747e8f8b
MC		 5437 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5438 u32 bmcr;
5439
5440 tg3_readphy(tp, MII_BMCR, &bmcr);
5441 if (bmcr & BMCR_ANENABLE) {
5442 u32 phy1, phy2;
5443
5444 /* Select shadow register 0x1f */
f08aa1a8
MC		 5445 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5446 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
747e8f8b
MC		 5447
5448 /* Select expansion interrupt status register */
f08aa1a8
MC		 5449 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5450 MII_TG3_DSP_EXP1_INT_STAT);
5451 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5452 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 5453
5454 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5455 /* We have signal detect and not receiving
5456 * config code words, link is up by parallel
5457 * detection.
5458 */
5459
5460 bmcr &= ~BMCR_ANENABLE;
5461 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5462 tg3_writephy(tp, MII_BMCR, bmcr);
f07e9af3 5463 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5464 }
5465 }
f4a46d1f 5466 } else if (tp->link_up &&
859a5887 5467 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
f07e9af3 5468 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 5469 u32 phy2;
5470
5471 /* Select expansion interrupt status register */
f08aa1a8
MC		 5472 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5473 MII_TG3_DSP_EXP1_INT_STAT);
5474 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 5475 if (phy2 & 0x20) {
5476 u32 bmcr;
5477
5478 /* Config code words received, turn on autoneg. */
5479 tg3_readphy(tp, MII_BMCR, &bmcr);
5480 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
5481
f07e9af3 5482 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5483
5484 }
5485 }
5486}
5487
1da177e4
LT		 5488static int tg3_setup_phy(struct tg3 *tp, int force_reset)
5489{
f2096f94 5490 u32 val;
1da177e4
LT		 5491 int err;
5492
f07e9af3 5493 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4 5494 err = tg3_setup_fiber_phy(tp, force_reset);
f07e9af3 5495 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
747e8f8b 5496 err = tg3_setup_fiber_mii_phy(tp, force_reset);
859a5887 5497 else
1da177e4 5498 err = tg3_setup_copper_phy(tp, force_reset);
1da177e4 5499
bcb37f6c 5500 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
f2096f94 5501 u32 scale;
aa6c91fe
MC		 5502
5503 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
5504 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
5505 scale = 65;
5506 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
5507 scale = 6;
5508 else
5509 scale = 12;
5510
5511 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
5512 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
5513 tw32(GRC_MISC_CFG, val);
5514 }
5515
f2096f94
MC		 5516 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5517 (6 << TX_LENGTHS_IPG_SHIFT);
c65a17f4
MC		 5518 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
5519 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762)
f2096f94
MC		 5520 val |= tr32(MAC_TX_LENGTHS) &
5521 (TX_LENGTHS_JMB_FRM_LEN_MSK |
5522 TX_LENGTHS_CNT_DWN_VAL_MSK);
5523
1da177e4
LT		 5524 if (tp->link_config.active_speed == SPEED_1000 &&
5525 tp->link_config.active_duplex == DUPLEX_HALF)
f2096f94
MC		 5526 tw32(MAC_TX_LENGTHS, val |
5527 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 5528 else
f2096f94
MC		 5529 tw32(MAC_TX_LENGTHS, val |
5530 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 5531
63c3a66f 5532 if (!tg3_flag(tp, 5705_PLUS)) {
f4a46d1f 5533 if (tp->link_up) {
1da177e4 5534 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 5535 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 5536 } else {
5537 tw32(HOSTCC_STAT_COAL_TICKS, 0);
5538 }
5539 }
5540
63c3a66f 5541 if (tg3_flag(tp, ASPM_WORKAROUND)) {
f2096f94 5542 val = tr32(PCIE_PWR_MGMT_THRESH);
f4a46d1f 5543 if (!tp->link_up)
8ed5d97e
MC		 5544 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
5545 tp->pwrmgmt_thresh;
5546 else
5547 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
5548 tw32(PCIE_PWR_MGMT_THRESH, val);
5549 }
5550
1da177e4
LT		 5551 return err;
5552}
5553
7d41e49a
MC		 5554/* tp->lock must be held */
5555static u64 tg3_refclk_read(struct tg3 *tp)
5556{
5557 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
5558 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
5559}
5560
be947307
MC		 5561/* tp->lock must be held */
5562static void tg3_refclk_write(struct tg3 *tp, u64 newval)
5563{
5564 tw32(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_STOP);
5565 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
5566 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
5567 tw32_f(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_RESUME);
5568}
5569
7d41e49a
MC		 5570static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
5571static inline void tg3_full_unlock(struct tg3 *tp);
5572static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
5573{
5574 struct tg3 *tp = netdev_priv(dev);
5575
5576 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
5577 SOF_TIMESTAMPING_RX_SOFTWARE |
5578 SOF_TIMESTAMPING_SOFTWARE |
5579 SOF_TIMESTAMPING_TX_HARDWARE |
5580 SOF_TIMESTAMPING_RX_HARDWARE |
5581 SOF_TIMESTAMPING_RAW_HARDWARE;
5582
5583 if (tp->ptp_clock)
5584 info->phc_index = ptp_clock_index(tp->ptp_clock);
5585 else
5586 info->phc_index = -1;
5587
5588 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
5589
5590 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
5591 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
5592 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
5593 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
5594 return 0;
5595}
5596
5597static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
5598{
5599 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
5600 bool neg_adj = false;
5601 u32 correction = 0;
5602
5603 if (ppb < 0) {
5604 neg_adj = true;
5605 ppb = -ppb;
5606 }
5607
5608 /* Frequency adjustment is performed using hardware with a 24 bit
5609 * accumulator and a programmable correction value. On each clk, the
5610 * correction value gets added to the accumulator and when it
5611 * overflows, the time counter is incremented/decremented.
5612 *
5613 * So conversion from ppb to correction value is
5614 * ppb * (1 << 24) / 1000000000
5615 */
5616 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
5617 TG3_EAV_REF_CLK_CORRECT_MASK;
5618
5619 tg3_full_lock(tp, 0);
5620
5621 if (correction)
5622 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
5623 TG3_EAV_REF_CLK_CORRECT_EN |
5624 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
5625 else
5626 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
5627
5628 tg3_full_unlock(tp);
5629
5630 return 0;
5631}
5632
5633static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
5634{
5635 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
5636
5637 tg3_full_lock(tp, 0);
5638 tp->ptp_adjust += delta;
5639 tg3_full_unlock(tp);
5640
5641 return 0;
5642}
5643
5644static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
5645{
5646 u64 ns;
5647 u32 remainder;
5648 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
5649
5650 tg3_full_lock(tp, 0);
5651 ns = tg3_refclk_read(tp);
5652 ns += tp->ptp_adjust;
5653 tg3_full_unlock(tp);
5654
5655 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
5656 ts->tv_nsec = remainder;
5657
5658 return 0;
5659}
5660
5661static int tg3_ptp_settime(struct ptp_clock_info *ptp,
5662 const struct timespec *ts)
5663{
5664 u64 ns;
5665 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
5666
5667 ns = timespec_to_ns(ts);
5668
5669 tg3_full_lock(tp, 0);
5670 tg3_refclk_write(tp, ns);
5671 tp->ptp_adjust = 0;
5672 tg3_full_unlock(tp);
5673
5674 return 0;
5675}
5676
5677static int tg3_ptp_enable(struct ptp_clock_info *ptp,
5678 struct ptp_clock_request *rq, int on)
5679{
5680 return -EOPNOTSUPP;
5681}
5682
5683static const struct ptp_clock_info tg3_ptp_caps = {
5684 .owner = THIS_MODULE,
5685 .name = "tg3 clock",
5686 .max_adj = 250000000,
5687 .n_alarm = 0,
5688 .n_ext_ts = 0,
5689 .n_per_out = 0,
5690 .pps = 0,
5691 .adjfreq = tg3_ptp_adjfreq,
5692 .adjtime = tg3_ptp_adjtime,
5693 .gettime = tg3_ptp_gettime,
5694 .settime = tg3_ptp_settime,
5695 .enable = tg3_ptp_enable,
5696};
5697
fb4ce8ad
MC		 5698static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
5699 struct skb_shared_hwtstamps *timestamp)
5700{
5701 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
5702 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
5703 tp->ptp_adjust);
5704}
5705
be947307
MC		 5706/* tp->lock must be held */
5707static void tg3_ptp_init(struct tg3 *tp)
5708{
5709 if (!tg3_flag(tp, PTP_CAPABLE))
5710 return;
5711
5712 /* Initialize the hardware clock to the system time. */
5713 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
5714 tp->ptp_adjust = 0;
7d41e49a 5715 tp->ptp_info = tg3_ptp_caps;
be947307
MC		 5716}
5717
5718/* tp->lock must be held */
5719static void tg3_ptp_resume(struct tg3 *tp)
5720{
5721 if (!tg3_flag(tp, PTP_CAPABLE))
5722 return;
5723
5724 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
5725 tp->ptp_adjust = 0;
5726}
5727
5728static void tg3_ptp_fini(struct tg3 *tp)
5729{
5730 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
5731 return;
5732
7d41e49a 5733 ptp_clock_unregister(tp->ptp_clock);
be947307
MC		 5734 tp->ptp_clock = NULL;
5735 tp->ptp_adjust = 0;
5736}
5737
66cfd1bd
MC		 5738static inline int tg3_irq_sync(struct tg3 *tp)
5739{
5740 return tp->irq_sync;
5741}
5742
97bd8e49
MC		 5743static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
5744{
5745 int i;
5746
5747 dst = (u32 *)((u8 *)dst + off);
5748 for (i = 0; i < len; i += sizeof(u32))
5749 *dst++ = tr32(off + i);
5750}
5751
5752static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
5753{
5754 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
5755 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
5756 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
5757 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
5758 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
5759 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
5760 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
5761 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
5762 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
5763 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
5764 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
5765 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
5766 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
5767 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
5768 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
5769 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
5770 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
5771 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
5772 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
5773
63c3a66f 5774 if (tg3_flag(tp, SUPPORT_MSIX))
97bd8e49
MC		 5775 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
5776
5777 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
5778 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
5779 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
5780 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
5781 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
5782 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
5783 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
5784 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
5785
63c3a66f 5786 if (!tg3_flag(tp, 5705_PLUS)) {
97bd8e49
MC		 5787 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
5788 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
5789 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
5790 }
5791
5792 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
5793 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
5794 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
5795 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
5796 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
5797
63c3a66f 5798 if (tg3_flag(tp, NVRAM))
97bd8e49
MC		 5799 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
5800}
5801
5802static void tg3_dump_state(struct tg3 *tp)
5803{
5804 int i;
5805 u32 *regs;
5806
5807 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
b2adaca9 5808 if (!regs)
97bd8e49 5809 return;
97bd8e49 5810
63c3a66f 5811 if (tg3_flag(tp, PCI_EXPRESS)) {
97bd8e49
MC		 5812 /* Read up to but not including private PCI registers */
5813 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
5814 regs[i / sizeof(u32)] = tr32(i);
5815 } else
5816 tg3_dump_legacy_regs(tp, regs);
5817
5818 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
5819 if (!regs[i + 0] && !regs[i + 1] &&
5820 !regs[i + 2] && !regs[i + 3])
5821 continue;
5822
5823 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
5824 i * 4,
5825 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
5826 }
5827
5828 kfree(regs);
5829
5830 for (i = 0; i < tp->irq_cnt; i++) {
5831 struct tg3_napi *tnapi = &tp->napi[i];
5832
5833 /* SW status block */
5834 netdev_err(tp->dev,
5835 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5836 i,
5837 tnapi->hw_status->status,
5838 tnapi->hw_status->status_tag,
5839 tnapi->hw_status->rx_jumbo_consumer,
5840 tnapi->hw_status->rx_consumer,
5841 tnapi->hw_status->rx_mini_consumer,
5842 tnapi->hw_status->idx[0].rx_producer,
5843 tnapi->hw_status->idx[0].tx_consumer);
5844
5845 netdev_err(tp->dev,
5846 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
5847 i,
5848 tnapi->last_tag, tnapi->last_irq_tag,
5849 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
5850 tnapi->rx_rcb_ptr,
5851 tnapi->prodring.rx_std_prod_idx,
5852 tnapi->prodring.rx_std_cons_idx,
5853 tnapi->prodring.rx_jmb_prod_idx,
5854 tnapi->prodring.rx_jmb_cons_idx);
5855 }
5856}
5857
df3e6548
MC		 5858/* This is called whenever we suspect that the system chipset is re-
5859 * ordering the sequence of MMIO to the tx send mailbox. The symptom
5860 * is bogus tx completions. We try to recover by setting the
5861 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
5862 * in the workqueue.
5863 */
5864static void tg3_tx_recover(struct tg3 *tp)
5865{
63c3a66f 5866 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
df3e6548
MC		 5867 tp->write32_tx_mbox == tg3_write_indirect_mbox);
5868
5129c3a3
MC		 5869 netdev_warn(tp->dev,
5870 "The system may be re-ordering memory-mapped I/O "
5871 "cycles to the network device, attempting to recover. "
5872 "Please report the problem to the driver maintainer "
5873 "and include system chipset information.\n");
df3e6548
MC		 5874
5875 spin_lock(&tp->lock);
63c3a66f 5876 tg3_flag_set(tp, TX_RECOVERY_PENDING);
df3e6548
MC		 5877 spin_unlock(&tp->lock);
5878}
5879
f3f3f27e 5880static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205 5881{
f65aac16
MC		 5882 /* Tell compiler to fetch tx indices from memory. */
5883 barrier();
f3f3f27e
MC		 5884 return tnapi->tx_pending -
5885 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 5886}
5887
1da177e4
LT		 5888/* Tigon3 never reports partial packet sends. So we do not
5889 * need special logic to handle SKBs that have not had all
5890 * of their frags sent yet, like SunGEM does.
5891 */
17375d25 5892static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 5893{
17375d25 5894 struct tg3 *tp = tnapi->tp;
898a56f8 5895 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 5896 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 5897 struct netdev_queue *txq;
5898 int index = tnapi - tp->napi;
298376d3 5899 unsigned int pkts_compl = 0, bytes_compl = 0;
fe5f5787 5900
63c3a66f 5901 if (tg3_flag(tp, ENABLE_TSS))
fe5f5787
MC		 5902 index--;
5903
5904 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 5905
5906 while (sw_idx != hw_idx) {
df8944cf 5907 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 5908 struct sk_buff *skb = ri->skb;
df3e6548
MC		 5909 int i, tx_bug = 0;
5910
5911 if (unlikely(skb == NULL)) {
5912 tg3_tx_recover(tp);
5913 return;
5914 }
1da177e4 5915
fb4ce8ad
MC		 5916 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
5917 struct skb_shared_hwtstamps timestamp;
5918 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
5919 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
5920
5921 tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);
5922
5923 skb_tstamp_tx(skb, &timestamp);
5924 }
5925
f4188d8a 5926 pci_unmap_single(tp->pdev,
4e5e4f0d 5927 dma_unmap_addr(ri, mapping),
f4188d8a
AD		 5928 skb_headlen(skb),
5929 PCI_DMA_TODEVICE);
1da177e4
LT		 5930
5931 ri->skb = NULL;
5932
e01ee14d
MC		 5933 while (ri->fragmented) {
5934 ri->fragmented = false;
5935 sw_idx = NEXT_TX(sw_idx);
5936 ri = &tnapi->tx_buffers[sw_idx];
5937 }
5938
1da177e4
LT		 5939 sw_idx = NEXT_TX(sw_idx);
5940
5941 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 5942 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 5943 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
5944 tx_bug = 1;
f4188d8a
AD		 5945
5946 pci_unmap_page(tp->pdev,
4e5e4f0d 5947 dma_unmap_addr(ri, mapping),
9e903e08 5948 skb_frag_size(&skb_shinfo(skb)->frags[i]),
f4188d8a 5949 PCI_DMA_TODEVICE);
e01ee14d
MC		 5950
5951 while (ri->fragmented) {
5952 ri->fragmented = false;
5953 sw_idx = NEXT_TX(sw_idx);
5954 ri = &tnapi->tx_buffers[sw_idx];
5955 }
5956
1da177e4
LT		 5957 sw_idx = NEXT_TX(sw_idx);
5958 }
5959
298376d3
TH		 5960 pkts_compl++;
5961 bytes_compl += skb->len;
5962
f47c11ee 5963 dev_kfree_skb(skb);
df3e6548
MC		 5964
5965 if (unlikely(tx_bug)) {
5966 tg3_tx_recover(tp);
5967 return;
5968 }
1da177e4
LT		 5969 }
5970
5cb917bc 5971 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
298376d3 5972
f3f3f27e 5973 tnapi->tx_cons = sw_idx;
1da177e4 5974
1b2a7205
MC		 5975 /* Need to make the tx_cons update visible to tg3_start_xmit()
5976 * before checking for netif_queue_stopped(). Without the
5977 * memory barrier, there is a small possibility that tg3_start_xmit()
5978 * will miss it and cause the queue to be stopped forever.
5979 */
5980 smp_mb();
5981
fe5f5787 5982 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 5983 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 5984 __netif_tx_lock(txq, smp_processor_id());
5985 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 5986 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 5987 netif_tx_wake_queue(txq);
5988 __netif_tx_unlock(txq);
51b91468 5989 }
1da177e4
LT		 5990}
5991
8d4057a9
ED		 5992static void tg3_frag_free(bool is_frag, void *data)
5993{
5994 if (is_frag)
5995 put_page(virt_to_head_page(data));
5996 else
5997 kfree(data);
5998}
5999
9205fd9c 6000static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
2b2cdb65 6001{
8d4057a9
ED		 6002 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6003 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6004
9205fd9c 6005 if (!ri->data)
2b2cdb65
MC		 6006 return;
6007
4e5e4f0d 6008 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
2b2cdb65 6009 map_sz, PCI_DMA_FROMDEVICE);
a1e8b307 6010 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
9205fd9c 6011 ri->data = NULL;
2b2cdb65
MC		 6012}
6013
8d4057a9 6014
1da177e4
LT		 6015/* Returns size of skb allocated or < 0 on error.
6016 *
6017 * We only need to fill in the address because the other members
6018 * of the RX descriptor are invariant, see tg3_init_rings.
6019 *
6020 * Note the purposeful assymetry of cpu vs. chip accesses. For
6021 * posting buffers we only dirty the first cache line of the RX
6022 * descriptor (containing the address). Whereas for the RX status
6023 * buffers the cpu only reads the last cacheline of the RX descriptor
6024 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6025 */
9205fd9c 6026static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
8d4057a9
ED		 6027 u32 opaque_key, u32 dest_idx_unmasked,
6028 unsigned int *frag_size)
1da177e4
LT		 6029{
6030 struct tg3_rx_buffer_desc *desc;
f94e290e 6031 struct ring_info *map;
9205fd9c 6032 u8 *data;
1da177e4 6033 dma_addr_t mapping;
9205fd9c 6034 int skb_size, data_size, dest_idx;
1da177e4 6035
1da177e4
LT		 6036 switch (opaque_key) {
6037 case RXD_OPAQUE_RING_STD:
2c49a44d 6038 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
21f581a5
MC		 6039 desc = &tpr->rx_std[dest_idx];
6040 map = &tpr->rx_std_buffers[dest_idx];
9205fd9c 6041 data_size = tp->rx_pkt_map_sz;
1da177e4
LT		 6042 break;
6043
6044 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6045 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
79ed5ac7 6046 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 6047 map = &tpr->rx_jmb_buffers[dest_idx];
9205fd9c 6048 data_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 6049 break;
6050
6051 default:
6052 return -EINVAL;
855e1111 6053 }
1da177e4
LT		 6054
6055 /* Do not overwrite any of the map or rp information
6056 * until we are sure we can commit to a new buffer.
6057 *
6058 * Callers depend upon this behavior and assume that
6059 * we leave everything unchanged if we fail.
6060 */
9205fd9c
ED		 6061 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6062 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
a1e8b307
ED		 6063 if (skb_size <= PAGE_SIZE) {
6064 data = netdev_alloc_frag(skb_size);
6065 *frag_size = skb_size;
8d4057a9
ED		 6066 } else {
6067 data = kmalloc(skb_size, GFP_ATOMIC);
6068 *frag_size = 0;
6069 }
9205fd9c 6070 if (!data)
1da177e4
LT		 6071 return -ENOMEM;
6072
9205fd9c
ED		 6073 mapping = pci_map_single(tp->pdev,
6074 data + TG3_RX_OFFSET(tp),
6075 data_size,
1da177e4 6076 PCI_DMA_FROMDEVICE);
8d4057a9 6077 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
a1e8b307 6078 tg3_frag_free(skb_size <= PAGE_SIZE, data);
a21771dd
MC		 6079 return -EIO;
6080 }
1da177e4 6081
9205fd9c 6082 map->data = data;
4e5e4f0d 6083 dma_unmap_addr_set(map, mapping, mapping);
1da177e4 6084
1da177e4
LT		 6085 desc->addr_hi = ((u64)mapping >> 32);
6086 desc->addr_lo = ((u64)mapping & 0xffffffff);
6087
9205fd9c 6088 return data_size;
1da177e4
LT		 6089}
6090
6091/* We only need to move over in the address because the other
6092 * members of the RX descriptor are invariant. See notes above
9205fd9c 6093 * tg3_alloc_rx_data for full details.
1da177e4 6094 */
a3896167
MC		 6095static void tg3_recycle_rx(struct tg3_napi *tnapi,
6096 struct tg3_rx_prodring_set *dpr,
6097 u32 opaque_key, int src_idx,
6098 u32 dest_idx_unmasked)
1da177e4 6099{
17375d25 6100 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 6101 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6102 struct ring_info *src_map, *dest_map;
8fea32b9 6103 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
c6cdf436 6104 int dest_idx;
1da177e4
LT		 6105
6106 switch (opaque_key) {
6107 case RXD_OPAQUE_RING_STD:
2c49a44d 6108 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
a3896167
MC		 6109 dest_desc = &dpr->rx_std[dest_idx];
6110 dest_map = &dpr->rx_std_buffers[dest_idx];
6111 src_desc = &spr->rx_std[src_idx];
6112 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 6113 break;
6114
6115 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6116 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
a3896167
MC		 6117 dest_desc = &dpr->rx_jmb[dest_idx].std;
6118 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6119 src_desc = &spr->rx_jmb[src_idx].std;
6120 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 6121 break;
6122
6123 default:
6124 return;
855e1111 6125 }
1da177e4 6126
9205fd9c 6127 dest_map->data = src_map->data;
4e5e4f0d
FT		 6128 dma_unmap_addr_set(dest_map, mapping,
6129 dma_unmap_addr(src_map, mapping));
1da177e4
LT		 6130 dest_desc->addr_hi = src_desc->addr_hi;
6131 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 6132
6133 /* Ensure that the update to the skb happens after the physical
6134 * addresses have been transferred to the new BD location.
6135 */
6136 smp_wmb();
6137
9205fd9c 6138 src_map->data = NULL;
1da177e4
LT		 6139}
6140
1da177e4
LT		 6141/* The RX ring scheme is composed of multiple rings which post fresh
6142 * buffers to the chip, and one special ring the chip uses to report
6143 * status back to the host.
6144 *
6145 * The special ring reports the status of received packets to the
6146 * host. The chip does not write into the original descriptor the
6147 * RX buffer was obtained from. The chip simply takes the original
6148 * descriptor as provided by the host, updates the status and length
6149 * field, then writes this into the next status ring entry.
6150 *
6151 * Each ring the host uses to post buffers to the chip is described
6152 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6153 * it is first placed into the on-chip ram. When the packet's length
6154 * is known, it walks down the TG3_BDINFO entries to select the ring.
6155 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6156 * which is within the range of the new packet's length is chosen.
6157 *
6158 * The "separate ring for rx status" scheme may sound queer, but it makes
6159 * sense from a cache coherency perspective. If only the host writes
6160 * to the buffer post rings, and only the chip writes to the rx status
6161 * rings, then cache lines never move beyond shared-modified state.
6162 * If both the host and chip were to write into the same ring, cache line
6163 * eviction could occur since both entities want it in an exclusive state.
6164 */
17375d25 6165static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 6166{
17375d25 6167 struct tg3 *tp = tnapi->tp;
f92905de 6168 u32 work_mask, rx_std_posted = 0;
4361935a 6169 u32 std_prod_idx, jmb_prod_idx;
72334482 6170 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 6171 u16 hw_idx;
1da177e4 6172 int received;
8fea32b9 6173 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
1da177e4 6174
8d9d7cfc 6175 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 6176 /*
6177 * We need to order the read of hw_idx and the read of
6178 * the opaque cookie.
6179 */
6180 rmb();
1da177e4
LT		 6181 work_mask = 0;
6182 received = 0;
4361935a
MC		 6183 std_prod_idx = tpr->rx_std_prod_idx;
6184 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 6185 while (sw_idx != hw_idx && budget > 0) {
afc081f8 6186 struct ring_info *ri;
72334482 6187 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 6188 unsigned int len;
6189 struct sk_buff *skb;
6190 dma_addr_t dma_addr;
6191 u32 opaque_key, desc_idx, *post_ptr;
9205fd9c 6192 u8 *data;
fb4ce8ad 6193 u64 tstamp = 0;
1da177e4
LT		 6194
6195 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6196 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6197 if (opaque_key == RXD_OPAQUE_RING_STD) {
8fea32b9 6198 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4e5e4f0d 6199 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6200 data = ri->data;
4361935a 6201 post_ptr = &std_prod_idx;
f92905de 6202 rx_std_posted++;
1da177e4 6203 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
8fea32b9 6204 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4e5e4f0d 6205 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6206 data = ri->data;
4361935a 6207 post_ptr = &jmb_prod_idx;
21f581a5 6208 } else
1da177e4 6209 goto next_pkt_nopost;
1da177e4
LT		 6210
6211 work_mask |= opaque_key;
6212
6213 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
6214 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
6215 drop_it:
a3896167 6216 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6217 desc_idx, *post_ptr);
6218 drop_it_no_recycle:
6219 /* Other statistics kept track of by card. */
b0057c51 6220 tp->rx_dropped++;
1da177e4
LT		 6221 goto next_pkt;
6222 }
6223
9205fd9c 6224 prefetch(data + TG3_RX_OFFSET(tp));
ad829268
MC		 6225 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6226 ETH_FCS_LEN;
1da177e4 6227
fb4ce8ad
MC		 6228 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6229 RXD_FLAG_PTPSTAT_PTPV1 ||
6230 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6231 RXD_FLAG_PTPSTAT_PTPV2) {
6232 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6233 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6234 }
6235
d2757fc4 6236 if (len > TG3_RX_COPY_THRESH(tp)) {
1da177e4 6237 int skb_size;
8d4057a9 6238 unsigned int frag_size;
1da177e4 6239
9205fd9c 6240 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
8d4057a9 6241 *post_ptr, &frag_size);
1da177e4
LT		 6242 if (skb_size < 0)
6243 goto drop_it;
6244
287be12e 6245 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 6246 PCI_DMA_FROMDEVICE);
6247
8d4057a9 6248 skb = build_skb(data, frag_size);
9205fd9c 6249 if (!skb) {
8d4057a9 6250 tg3_frag_free(frag_size != 0, data);
9205fd9c
ED		 6251 goto drop_it_no_recycle;
6252 }
6253 skb_reserve(skb, TG3_RX_OFFSET(tp));
6254 /* Ensure that the update to the data happens
61e800cf
MC		 6255 * after the usage of the old DMA mapping.
6256 */
6257 smp_wmb();
6258
9205fd9c 6259 ri->data = NULL;
61e800cf 6260
1da177e4 6261 } else {
a3896167 6262 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6263 desc_idx, *post_ptr);
6264
9205fd9c
ED		 6265 skb = netdev_alloc_skb(tp->dev,
6266 len + TG3_RAW_IP_ALIGN);
6267 if (skb == NULL)
1da177e4
LT		 6268 goto drop_it_no_recycle;
6269
9205fd9c 6270 skb_reserve(skb, TG3_RAW_IP_ALIGN);
1da177e4 6271 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
9205fd9c
ED		 6272 memcpy(skb->data,
6273 data + TG3_RX_OFFSET(tp),
6274 len);
1da177e4 6275 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
1da177e4
LT		 6276 }
6277
9205fd9c 6278 skb_put(skb, len);
fb4ce8ad
MC		 6279 if (tstamp)
6280 tg3_hwclock_to_timestamp(tp, tstamp,
6281 skb_hwtstamps(skb));
6282
dc668910 6283 if ((tp->dev->features & NETIF_F_RXCSUM) &&
1da177e4
LT		 6284 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6285 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6286 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6287 skb->ip_summed = CHECKSUM_UNNECESSARY;
6288 else
bc8acf2c 6289 skb_checksum_none_assert(skb);
1da177e4
LT		 6290
6291 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 6292
6293 if (len > (tp->dev->mtu + ETH_HLEN) &&
6294 skb->protocol != htons(ETH_P_8021Q)) {
6295 dev_kfree_skb(skb);
b0057c51 6296 goto drop_it_no_recycle;
f7b493e0
MC		 6297 }
6298
9dc7a113 6299 if (desc->type_flags & RXD_FLAG_VLAN &&
bf933c80
MC		 6300 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6301 __vlan_hwaccel_put_tag(skb,
6302 desc->err_vlan & RXD_VLAN_MASK);
9dc7a113 6303
bf933c80 6304 napi_gro_receive(&tnapi->napi, skb);
1da177e4 6305
1da177e4
LT		 6306 received++;
6307 budget--;
6308
6309next_pkt:
6310 (*post_ptr)++;
f92905de
MC		 6311
6312 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
2c49a44d
MC		 6313 tpr->rx_std_prod_idx = std_prod_idx &
6314 tp->rx_std_ring_mask;
86cfe4ff
MC		 6315 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6316 tpr->rx_std_prod_idx);
f92905de
MC		 6317 work_mask &= ~RXD_OPAQUE_RING_STD;
6318 rx_std_posted = 0;
6319 }
1da177e4 6320next_pkt_nopost:
483ba50b 6321 sw_idx++;
7cb32cf2 6322 sw_idx &= tp->rx_ret_ring_mask;
52f6d697
MC		 6323
6324 /* Refresh hw_idx to see if there is new work */
6325 if (sw_idx == hw_idx) {
8d9d7cfc 6326 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 6327 rmb();
6328 }
1da177e4
LT		 6329 }
6330
6331 /* ACK the status ring. */
72334482
MC		 6332 tnapi->rx_rcb_ptr = sw_idx;
6333 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 6334
6335 /* Refill RX ring(s). */
63c3a66f 6336 if (!tg3_flag(tp, ENABLE_RSS)) {
6541b806
MC		 6337 /* Sync BD data before updating mailbox */
6338 wmb();
6339
b196c7e4 6340 if (work_mask & RXD_OPAQUE_RING_STD) {
2c49a44d
MC		 6341 tpr->rx_std_prod_idx = std_prod_idx &
6342 tp->rx_std_ring_mask;
b196c7e4
MC		 6343 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6344 tpr->rx_std_prod_idx);
6345 }
6346 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2c49a44d
MC		 6347 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6348 tp->rx_jmb_ring_mask;
b196c7e4
MC		 6349 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6350 tpr->rx_jmb_prod_idx);
6351 }
6352 mmiowb();
6353 } else if (work_mask) {
6354 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6355 * updated before the producer indices can be updated.
6356 */
6357 smp_wmb();
6358
2c49a44d
MC		 6359 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6360 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
b196c7e4 6361
7ae52890
MC		 6362 if (tnapi != &tp->napi[1]) {
6363 tp->rx_refill = true;
e4af1af9 6364 napi_schedule(&tp->napi[1].napi);
7ae52890 6365 }
1da177e4 6366 }
1da177e4
LT		 6367
6368 return received;
6369}
6370
35f2d7d0 6371static void tg3_poll_link(struct tg3 *tp)
1da177e4 6372{
1da177e4 6373 /* handle link change and other phy events */
63c3a66f 6374 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
35f2d7d0
MC		 6375 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
6376
1da177e4
LT		 6377 if (sblk->status & SD_STATUS_LINK_CHG) {
6378 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 6379 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 6380 spin_lock(&tp->lock);
63c3a66f 6381 if (tg3_flag(tp, USE_PHYLIB)) {
dd477003
MC		 6382 tw32_f(MAC_STATUS,
6383 (MAC_STATUS_SYNC_CHANGED |
6384 MAC_STATUS_CFG_CHANGED |
6385 MAC_STATUS_MI_COMPLETION |
6386 MAC_STATUS_LNKSTATE_CHANGED));
6387 udelay(40);
6388 } else
6389 tg3_setup_phy(tp, 0);
f47c11ee 6390 spin_unlock(&tp->lock);
1da177e4
LT		 6391 }
6392 }
35f2d7d0
MC		 6393}
6394
f89f38b8
MC		 6395static int tg3_rx_prodring_xfer(struct tg3 *tp,
6396 struct tg3_rx_prodring_set *dpr,
6397 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 6398{
6399 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 6400 int i, err = 0;
b196c7e4
MC		 6401
6402 while (1) {
6403 src_prod_idx = spr->rx_std_prod_idx;
6404
6405 /* Make sure updates to the rx_std_buffers[] entries and the
6406 * standard producer index are seen in the correct order.
6407 */
6408 smp_rmb();
6409
6410 if (spr->rx_std_cons_idx == src_prod_idx)
6411 break;
6412
6413 if (spr->rx_std_cons_idx < src_prod_idx)
6414 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
6415 else
2c49a44d
MC		 6416 cpycnt = tp->rx_std_ring_mask + 1 -
6417 spr->rx_std_cons_idx;
b196c7e4 6418
2c49a44d
MC		 6419 cpycnt = min(cpycnt,
6420 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
b196c7e4
MC		 6421
6422 si = spr->rx_std_cons_idx;
6423 di = dpr->rx_std_prod_idx;
6424
e92967bf 6425 for (i = di; i < di + cpycnt; i++) {
9205fd9c 6426 if (dpr->rx_std_buffers[i].data) {
e92967bf 6427 cpycnt = i - di;
f89f38b8 6428 err = -ENOSPC;
e92967bf
MC		 6429 break;
6430 }
6431 }
6432
6433 if (!cpycnt)
6434 break;
6435
6436 /* Ensure that updates to the rx_std_buffers ring and the
6437 * shadowed hardware producer ring from tg3_recycle_skb() are
6438 * ordered correctly WRT the skb check above.
6439 */
6440 smp_rmb();
6441
b196c7e4
MC		 6442 memcpy(&dpr->rx_std_buffers[di],
6443 &spr->rx_std_buffers[si],
6444 cpycnt * sizeof(struct ring_info));
6445
6446 for (i = 0; i < cpycnt; i++, di++, si++) {
6447 struct tg3_rx_buffer_desc *sbd, *dbd;
6448 sbd = &spr->rx_std[si];
6449 dbd = &dpr->rx_std[di];
6450 dbd->addr_hi = sbd->addr_hi;
6451 dbd->addr_lo = sbd->addr_lo;
6452 }
6453
2c49a44d
MC		 6454 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
6455 tp->rx_std_ring_mask;
6456 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
6457 tp->rx_std_ring_mask;
b196c7e4
MC		 6458 }
6459
6460 while (1) {
6461 src_prod_idx = spr->rx_jmb_prod_idx;
6462
6463 /* Make sure updates to the rx_jmb_buffers[] entries and
6464 * the jumbo producer index are seen in the correct order.
6465 */
6466 smp_rmb();
6467
6468 if (spr->rx_jmb_cons_idx == src_prod_idx)
6469 break;
6470
6471 if (spr->rx_jmb_cons_idx < src_prod_idx)
6472 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
6473 else
2c49a44d
MC		 6474 cpycnt = tp->rx_jmb_ring_mask + 1 -
6475 spr->rx_jmb_cons_idx;
b196c7e4
MC		 6476
6477 cpycnt = min(cpycnt,
2c49a44d 6478 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
b196c7e4
MC		 6479
6480 si = spr->rx_jmb_cons_idx;
6481 di = dpr->rx_jmb_prod_idx;
6482
e92967bf 6483 for (i = di; i < di + cpycnt; i++) {
9205fd9c 6484 if (dpr->rx_jmb_buffers[i].data) {
e92967bf 6485 cpycnt = i - di;
f89f38b8 6486 err = -ENOSPC;
e92967bf
MC		 6487 break;
6488 }
6489 }
6490
6491 if (!cpycnt)
6492 break;
6493
6494 /* Ensure that updates to the rx_jmb_buffers ring and the
6495 * shadowed hardware producer ring from tg3_recycle_skb() are
6496 * ordered correctly WRT the skb check above.
6497 */
6498 smp_rmb();
6499
b196c7e4
MC		 6500 memcpy(&dpr->rx_jmb_buffers[di],
6501 &spr->rx_jmb_buffers[si],
6502 cpycnt * sizeof(struct ring_info));
6503
6504 for (i = 0; i < cpycnt; i++, di++, si++) {
6505 struct tg3_rx_buffer_desc *sbd, *dbd;
6506 sbd = &spr->rx_jmb[si].std;
6507 dbd = &dpr->rx_jmb[di].std;
6508 dbd->addr_hi = sbd->addr_hi;
6509 dbd->addr_lo = sbd->addr_lo;
6510 }
6511
2c49a44d
MC		 6512 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
6513 tp->rx_jmb_ring_mask;
6514 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
6515 tp->rx_jmb_ring_mask;
b196c7e4 6516 }
f89f38b8
MC		 6517
6518 return err;
b196c7e4
MC		 6519}
6520
35f2d7d0
MC		 6521static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
6522{
6523 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 6524
6525 /* run TX completion thread */
f3f3f27e 6526 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 6527 tg3_tx(tnapi);
63c3a66f 6528 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
4fd7ab59 6529 return work_done;
1da177e4
LT		 6530 }
6531
f891ea16
MC		 6532 if (!tnapi->rx_rcb_prod_idx)
6533 return work_done;
6534
1da177e4
LT		 6535 /* run RX thread, within the bounds set by NAPI.
6536 * All RX "locking" is done by ensuring outside
bea3348e 6537 * code synchronizes with tg3->napi.poll()
1da177e4 6538 */
8d9d7cfc 6539 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 6540 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 6541
63c3a66f 6542 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
8fea32b9 6543 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
f89f38b8 6544 int i, err = 0;
e4af1af9
MC		 6545 u32 std_prod_idx = dpr->rx_std_prod_idx;
6546 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 6547
7ae52890 6548 tp->rx_refill = false;
9102426a 6549 for (i = 1; i <= tp->rxq_cnt; i++)
f89f38b8 6550 err |= tg3_rx_prodring_xfer(tp, dpr,
8fea32b9 6551 &tp->napi[i].prodring);
b196c7e4
MC		 6552
6553 wmb();
6554
e4af1af9
MC		 6555 if (std_prod_idx != dpr->rx_std_prod_idx)
6556 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6557 dpr->rx_std_prod_idx);
b196c7e4 6558
e4af1af9
MC		 6559 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
6560 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6561 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 6562
6563 mmiowb();
f89f38b8
MC		 6564
6565 if (err)
6566 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 6567 }
6568
6f535763
DM		 6569 return work_done;
6570}
6571
db219973
MC		 6572static inline void tg3_reset_task_schedule(struct tg3 *tp)
6573{
6574 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
6575 schedule_work(&tp->reset_task);
6576}
6577
6578static inline void tg3_reset_task_cancel(struct tg3 *tp)
6579{
6580 cancel_work_sync(&tp->reset_task);
6581 tg3_flag_clear(tp, RESET_TASK_PENDING);
c7101359 6582 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
db219973
MC		 6583}
6584
35f2d7d0
MC		 6585static int tg3_poll_msix(struct napi_struct *napi, int budget)
6586{
6587 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6588 struct tg3 *tp = tnapi->tp;
6589 int work_done = 0;
6590 struct tg3_hw_status *sblk = tnapi->hw_status;
6591
6592 while (1) {
6593 work_done = tg3_poll_work(tnapi, work_done, budget);
6594
63c3a66f 6595 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
35f2d7d0
MC		 6596 goto tx_recovery;
6597
6598 if (unlikely(work_done >= budget))
6599 break;
6600
c6cdf436 6601 /* tp->last_tag is used in tg3_int_reenable() below
35f2d7d0
MC		 6602 * to tell the hw how much work has been processed,
6603 * so we must read it before checking for more work.
6604 */
6605 tnapi->last_tag = sblk->status_tag;
6606 tnapi->last_irq_tag = tnapi->last_tag;
6607 rmb();
6608
6609 /* check for RX/TX work to do */
6d40db7b
MC		 6610 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
6611 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7ae52890
MC		 6612
6613 /* This test here is not race free, but will reduce
6614 * the number of interrupts by looping again.
6615 */
6616 if (tnapi == &tp->napi[1] && tp->rx_refill)
6617 continue;
6618
35f2d7d0
MC		 6619 napi_complete(napi);
6620 /* Reenable interrupts. */
6621 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7ae52890
MC		 6622
6623 /* This test here is synchronized by napi_schedule()
6624 * and napi_complete() to close the race condition.
6625 */
6626 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
6627 tw32(HOSTCC_MODE, tp->coalesce_mode |
6628 HOSTCC_MODE_ENABLE |
6629 tnapi->coal_now);
6630 }
35f2d7d0
MC		 6631 mmiowb();
6632 break;
6633 }
6634 }
6635
6636 return work_done;
6637
6638tx_recovery:
6639 /* work_done is guaranteed to be less than budget. */
6640 napi_complete(napi);
db219973 6641 tg3_reset_task_schedule(tp);
35f2d7d0
MC		 6642 return work_done;
6643}
6644
e64de4e6
MC		 6645static void tg3_process_error(struct tg3 *tp)
6646{
6647 u32 val;
6648 bool real_error = false;
6649
63c3a66f 6650 if (tg3_flag(tp, ERROR_PROCESSED))
e64de4e6
MC		 6651 return;
6652
6653 /* Check Flow Attention register */
6654 val = tr32(HOSTCC_FLOW_ATTN);
6655 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
6656 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
6657 real_error = true;
6658 }
6659
6660 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
6661 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
6662 real_error = true;
6663 }
6664
6665 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
6666 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
6667 real_error = true;
6668 }
6669
6670 if (!real_error)
6671 return;
6672
6673 tg3_dump_state(tp);
6674
63c3a66f 6675 tg3_flag_set(tp, ERROR_PROCESSED);
db219973 6676 tg3_reset_task_schedule(tp);
e64de4e6
MC		 6677}
6678
6f535763
DM		 6679static int tg3_poll(struct napi_struct *napi, int budget)
6680{
8ef0442f
MC		 6681 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6682 struct tg3 *tp = tnapi->tp;
6f535763 6683 int work_done = 0;
898a56f8 6684 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 6685
6686 while (1) {
e64de4e6
MC		 6687 if (sblk->status & SD_STATUS_ERROR)
6688 tg3_process_error(tp);
6689
35f2d7d0
MC		 6690 tg3_poll_link(tp);
6691
17375d25 6692 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763 6693
63c3a66f 6694 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6f535763
DM		 6695 goto tx_recovery;
6696
6697 if (unlikely(work_done >= budget))
6698 break;
6699
63c3a66f 6700 if (tg3_flag(tp, TAGGED_STATUS)) {
17375d25 6701 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 6702 * to tell the hw how much work has been processed,
6703 * so we must read it before checking for more work.
6704 */
898a56f8
MC		 6705 tnapi->last_tag = sblk->status_tag;
6706 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 6707 rmb();
6708 } else
6709 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 6710
17375d25 6711 if (likely(!tg3_has_work(tnapi))) {
288379f0 6712 napi_complete(napi);
17375d25 6713 tg3_int_reenable(tnapi);
6f535763
DM		 6714 break;
6715 }
1da177e4
LT		 6716 }
6717
bea3348e 6718 return work_done;
6f535763
DM		 6719
6720tx_recovery:
4fd7ab59 6721 /* work_done is guaranteed to be less than budget. */
288379f0 6722 napi_complete(napi);
db219973 6723 tg3_reset_task_schedule(tp);
4fd7ab59 6724 return work_done;
1da177e4
LT		 6725}
6726
66cfd1bd
MC		 6727static void tg3_napi_disable(struct tg3 *tp)
6728{
6729 int i;
6730
6731 for (i = tp->irq_cnt - 1; i >= 0; i--)
6732 napi_disable(&tp->napi[i].napi);
6733}
6734
6735static void tg3_napi_enable(struct tg3 *tp)
6736{
6737 int i;
6738
6739 for (i = 0; i < tp->irq_cnt; i++)
6740 napi_enable(&tp->napi[i].napi);
6741}
6742
6743static void tg3_napi_init(struct tg3 *tp)
6744{
6745 int i;
6746
6747 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
6748 for (i = 1; i < tp->irq_cnt; i++)
6749 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
6750}
6751
6752static void tg3_napi_fini(struct tg3 *tp)
6753{
6754 int i;
6755
6756 for (i = 0; i < tp->irq_cnt; i++)
6757 netif_napi_del(&tp->napi[i].napi);
6758}
6759
6760static inline void tg3_netif_stop(struct tg3 *tp)
6761{
6762 tp->dev->trans_start = jiffies; /* prevent tx timeout */
6763 tg3_napi_disable(tp);
f4a46d1f 6764 netif_carrier_off(tp->dev);
66cfd1bd
MC		 6765 netif_tx_disable(tp->dev);
6766}
6767
35763066 6768/* tp->lock must be held */
66cfd1bd
MC		 6769static inline void tg3_netif_start(struct tg3 *tp)
6770{
be947307
MC		 6771 tg3_ptp_resume(tp);
6772
66cfd1bd
MC		 6773 /* NOTE: unconditional netif_tx_wake_all_queues is only
6774 * appropriate so long as all callers are assured to
6775 * have free tx slots (such as after tg3_init_hw)
6776 */
6777 netif_tx_wake_all_queues(tp->dev);
6778
f4a46d1f
NNS		 6779 if (tp->link_up)
6780 netif_carrier_on(tp->dev);
6781
66cfd1bd
MC		 6782 tg3_napi_enable(tp);
6783 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
6784 tg3_enable_ints(tp);
6785}
6786
f47c11ee
DM		 6787static void tg3_irq_quiesce(struct tg3 *tp)
6788{
4f125f42
MC		 6789 int i;
6790
f47c11ee
DM		 6791 BUG_ON(tp->irq_sync);
6792
6793 tp->irq_sync = 1;
6794 smp_mb();
6795
4f125f42
MC		 6796 for (i = 0; i < tp->irq_cnt; i++)
6797 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 6798}
6799
f47c11ee
DM		 6800/* Fully shutdown all tg3 driver activity elsewhere in the system.
6801 * If irq_sync is non-zero, then the IRQ handler must be synchronized
6802 * with as well. Most of the time, this is not necessary except when
6803 * shutting down the device.
6804 */
6805static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
6806{
46966545 6807 spin_lock_bh(&tp->lock);
f47c11ee
DM		 6808 if (irq_sync)
6809 tg3_irq_quiesce(tp);
f47c11ee
DM		 6810}
6811
6812static inline void tg3_full_unlock(struct tg3 *tp)
6813{
f47c11ee
DM		 6814 spin_unlock_bh(&tp->lock);
6815}
6816
fcfa0a32
MC		 6817/* One-shot MSI handler - Chip automatically disables interrupt
6818 * after sending MSI so driver doesn't have to do it.
6819 */
7d12e780 6820static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 6821{
09943a18
MC		 6822 struct tg3_napi *tnapi = dev_id;
6823 struct tg3 *tp = tnapi->tp;
fcfa0a32 6824
898a56f8 6825 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 6826 if (tnapi->rx_rcb)
6827 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 6828
6829 if (likely(!tg3_irq_sync(tp)))
09943a18 6830 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 6831
6832 return IRQ_HANDLED;
6833}
6834
88b06bc2
MC		 6835/* MSI ISR - No need to check for interrupt sharing and no need to
6836 * flush status block and interrupt mailbox. PCI ordering rules
6837 * guarantee that MSI will arrive after the status block.
6838 */
7d12e780 6839static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 6840{
09943a18
MC		 6841 struct tg3_napi *tnapi = dev_id;
6842 struct tg3 *tp = tnapi->tp;
88b06bc2 6843
898a56f8 6844 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 6845 if (tnapi->rx_rcb)
6846 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 6847 /*
fac9b83e 6848 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 6849 * chip-internal interrupt pending events.
fac9b83e 6850 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 6851 * NIC to stop sending us irqs, engaging "in-intr-handler"
6852 * event coalescing.
6853 */
5b39de91 6854 tw32_mailbox(tnapi->int_mbox, 0x00000001);
61487480 6855 if (likely(!tg3_irq_sync(tp)))
09943a18 6856 napi_schedule(&tnapi->napi);
61487480 6857
88b06bc2
MC		 6858 return IRQ_RETVAL(1);
6859}
6860
7d12e780 6861static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 6862{
09943a18
MC		 6863 struct tg3_napi *tnapi = dev_id;
6864 struct tg3 *tp = tnapi->tp;
898a56f8 6865 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 6866 unsigned int handled = 1;
6867
1da177e4
LT		 6868 /* In INTx mode, it is possible for the interrupt to arrive at
6869 * the CPU before the status block posted prior to the interrupt.
6870 * Reading the PCI State register will confirm whether the
6871 * interrupt is ours and will flush the status block.
6872 */
d18edcb2 6873 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
63c3a66f 6874 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 6875 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6876 handled = 0;
f47c11ee 6877 goto out;
fac9b83e 6878 }
d18edcb2
MC		 6879 }
6880
6881 /*
6882 * Writing any value to intr-mbox-0 clears PCI INTA# and
6883 * chip-internal interrupt pending events.
6884 * Writing non-zero to intr-mbox-0 additional tells the
6885 * NIC to stop sending us irqs, engaging "in-intr-handler"
6886 * event coalescing.
c04cb347
MC		 6887 *
6888 * Flush the mailbox to de-assert the IRQ immediately to prevent
6889 * spurious interrupts. The flush impacts performance but
6890 * excessive spurious interrupts can be worse in some cases.
d18edcb2 6891 */
c04cb347 6892 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 6893 if (tg3_irq_sync(tp))
6894 goto out;
6895 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 6896 if (likely(tg3_has_work(tnapi))) {
72334482 6897 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 6898 napi_schedule(&tnapi->napi);
d18edcb2
MC		 6899 } else {
6900 /* No work, shared interrupt perhaps? re-enable
6901 * interrupts, and flush that PCI write
6902 */
6903 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
6904 0x00000000);
fac9b83e 6905 }
f47c11ee 6906out:
fac9b83e
DM		 6907 return IRQ_RETVAL(handled);
6908}
6909
7d12e780 6910static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 6911{
09943a18
MC		 6912 struct tg3_napi *tnapi = dev_id;
6913 struct tg3 *tp = tnapi->tp;
898a56f8 6914 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 6915 unsigned int handled = 1;
6916
fac9b83e
DM		 6917 /* In INTx mode, it is possible for the interrupt to arrive at
6918 * the CPU before the status block posted prior to the interrupt.
6919 * Reading the PCI State register will confirm whether the
6920 * interrupt is ours and will flush the status block.
6921 */
898a56f8 6922 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
63c3a66f 6923 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 6924 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6925 handled = 0;
f47c11ee 6926 goto out;
1da177e4 6927 }
d18edcb2
MC		 6928 }
6929
6930 /*
6931 * writing any value to intr-mbox-0 clears PCI INTA# and
6932 * chip-internal interrupt pending events.
6933 * writing non-zero to intr-mbox-0 additional tells the
6934 * NIC to stop sending us irqs, engaging "in-intr-handler"
6935 * event coalescing.
c04cb347
MC		 6936 *
6937 * Flush the mailbox to de-assert the IRQ immediately to prevent
6938 * spurious interrupts. The flush impacts performance but
6939 * excessive spurious interrupts can be worse in some cases.
d18edcb2 6940 */
c04cb347 6941 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 6942
6943 /*
6944 * In a shared interrupt configuration, sometimes other devices'
6945 * interrupts will scream. We record the current status tag here
6946 * so that the above check can report that the screaming interrupts
6947 * are unhandled. Eventually they will be silenced.
6948 */
898a56f8 6949 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 6950
d18edcb2
MC		 6951 if (tg3_irq_sync(tp))
6952 goto out;
624f8e50 6953
72334482 6954 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 6955
09943a18 6956 napi_schedule(&tnapi->napi);
624f8e50 6957
f47c11ee 6958out:
1da177e4
LT		 6959 return IRQ_RETVAL(handled);
6960}
6961
7938109f 6962/* ISR for interrupt test */
7d12e780 6963static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 6964{
09943a18
MC		 6965 struct tg3_napi *tnapi = dev_id;
6966 struct tg3 *tp = tnapi->tp;
898a56f8 6967 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 6968
f9804ddb
MC		 6969 if ((sblk->status & SD_STATUS_UPDATED) ||
6970 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 6971 tg3_disable_ints(tp);
7938109f
MC		 6972 return IRQ_RETVAL(1);
6973 }
6974 return IRQ_RETVAL(0);
6975}
6976
1da177e4
LT		 6977#ifdef CONFIG_NET_POLL_CONTROLLER
6978static void tg3_poll_controller(struct net_device *dev)
6979{
4f125f42 6980 int i;
88b06bc2
MC		 6981 struct tg3 *tp = netdev_priv(dev);
6982
9c13cb8b
NNS		 6983 if (tg3_irq_sync(tp))
6984 return;
6985
4f125f42 6986 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 6987 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 6988}
6989#endif
6990
1da177e4
LT		 6991static void tg3_tx_timeout(struct net_device *dev)
6992{
6993 struct tg3 *tp = netdev_priv(dev);
6994
b0408751 6995 if (netif_msg_tx_err(tp)) {
05dbe005 6996 netdev_err(dev, "transmit timed out, resetting\n");
97bd8e49 6997 tg3_dump_state(tp);
b0408751 6998 }
1da177e4 6999
db219973 7000 tg3_reset_task_schedule(tp);
1da177e4
LT		 7001}
7002
c58ec932
MC		 7003/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7004static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7005{
7006 u32 base = (u32) mapping & 0xffffffff;
7007
807540ba 7008 return (base > 0xffffdcc0) && (base + len + 8 < base);
c58ec932
MC		 7009}
7010
72f2afb8
MC		 7011/* Test for DMA addresses > 40-bit */
7012static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7013 int len)
7014{
7015#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
63c3a66f 7016 if (tg3_flag(tp, 40BIT_DMA_BUG))
807540ba 7017 return ((u64) mapping + len) > DMA_BIT_MASK(40);
72f2afb8
MC		 7018 return 0;
7019#else
7020 return 0;
7021#endif
7022}
7023
d1a3b737 7024static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
92cd3a17
MC		 7025 dma_addr_t mapping, u32 len, u32 flags,
7026 u32 mss, u32 vlan)
2ffcc981 7027{
92cd3a17
MC		 7028 txbd->addr_hi = ((u64) mapping >> 32);
7029 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7030 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7031 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
2ffcc981 7032}
1da177e4 7033
84b67b27 7034static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
d1a3b737
MC		 7035 dma_addr_t map, u32 len, u32 flags,
7036 u32 mss, u32 vlan)
7037{
7038 struct tg3 *tp = tnapi->tp;
7039 bool hwbug = false;
7040
7041 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
3db1cd5c 7042 hwbug = true;
d1a3b737
MC		 7043
7044 if (tg3_4g_overflow_test(map, len))
3db1cd5c 7045 hwbug = true;
d1a3b737
MC		 7046
7047 if (tg3_40bit_overflow_test(tp, map, len))
3db1cd5c 7048 hwbug = true;
d1a3b737 7049
a4cb428d 7050 if (tp->dma_limit) {
b9e45482 7051 u32 prvidx = *entry;
e31aa987 7052 u32 tmp_flag = flags & ~TXD_FLAG_END;
a4cb428d
MC		 7053 while (len > tp->dma_limit && *budget) {
7054 u32 frag_len = tp->dma_limit;
7055 len -= tp->dma_limit;
e31aa987 7056
b9e45482
MC		 7057 /* Avoid the 8byte DMA problem */
7058 if (len <= 8) {
a4cb428d
MC		 7059 len += tp->dma_limit / 2;
7060 frag_len = tp->dma_limit / 2;
e31aa987
MC		 7061 }
7062
b9e45482
MC		 7063 tnapi->tx_buffers[*entry].fragmented = true;
7064
7065 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7066 frag_len, tmp_flag, mss, vlan);
7067 *budget -= 1;
7068 prvidx = *entry;
7069 *entry = NEXT_TX(*entry);
7070
e31aa987
MC		 7071 map += frag_len;
7072 }
7073
7074 if (len) {
7075 if (*budget) {
7076 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7077 len, flags, mss, vlan);
b9e45482 7078 *budget -= 1;
e31aa987
MC		 7079 *entry = NEXT_TX(*entry);
7080 } else {
3db1cd5c 7081 hwbug = true;
b9e45482 7082 tnapi->tx_buffers[prvidx].fragmented = false;
e31aa987
MC		 7083 }
7084 }
7085 } else {
84b67b27
MC		 7086 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7087 len, flags, mss, vlan);
e31aa987
MC		 7088 *entry = NEXT_TX(*entry);
7089 }
d1a3b737
MC		 7090
7091 return hwbug;
7092}
7093
0d681b27 7094static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
432aa7ed
MC		 7095{
7096 int i;
0d681b27 7097 struct sk_buff *skb;
df8944cf 7098 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
432aa7ed 7099
0d681b27
MC		 7100 skb = txb->skb;
7101 txb->skb = NULL;
7102
432aa7ed
MC		 7103 pci_unmap_single(tnapi->tp->pdev,
7104 dma_unmap_addr(txb, mapping),
7105 skb_headlen(skb),
7106 PCI_DMA_TODEVICE);
e01ee14d
MC		 7107
7108 while (txb->fragmented) {
7109 txb->fragmented = false;
7110 entry = NEXT_TX(entry);
7111 txb = &tnapi->tx_buffers[entry];
7112 }
7113
ba1142e4 7114 for (i = 0; i <= last; i++) {
9e903e08 7115 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
432aa7ed
MC		 7116
7117 entry = NEXT_TX(entry);
7118 txb = &tnapi->tx_buffers[entry];
7119
7120 pci_unmap_page(tnapi->tp->pdev,
7121 dma_unmap_addr(txb, mapping),
9e903e08 7122 skb_frag_size(frag), PCI_DMA_TODEVICE);
e01ee14d
MC		 7123
7124 while (txb->fragmented) {
7125 txb->fragmented = false;
7126 entry = NEXT_TX(entry);
7127 txb = &tnapi->tx_buffers[entry];
7128 }
432aa7ed
MC		 7129 }
7130}
7131
72f2afb8 7132/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4 7133static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
f7ff1987 7134 struct sk_buff **pskb,
84b67b27 7135 u32 *entry, u32 *budget,
92cd3a17 7136 u32 base_flags, u32 mss, u32 vlan)
1da177e4 7137{
24f4efd4 7138 struct tg3 *tp = tnapi->tp;
f7ff1987 7139 struct sk_buff *new_skb, *skb = *pskb;
c58ec932 7140 dma_addr_t new_addr = 0;
432aa7ed 7141 int ret = 0;
1da177e4 7142
41588ba1
MC		 7143 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
7144 new_skb = skb_copy(skb, GFP_ATOMIC);
7145 else {
7146 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7147
7148 new_skb = skb_copy_expand(skb,
7149 skb_headroom(skb) + more_headroom,
7150 skb_tailroom(skb), GFP_ATOMIC);
7151 }
7152
1da177e4 7153 if (!new_skb) {
c58ec932
MC		 7154 ret = -1;
7155 } else {
7156 /* New SKB is guaranteed to be linear. */
f4188d8a
AD		 7157 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7158 PCI_DMA_TODEVICE);
7159 /* Make sure the mapping succeeded */
7160 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
f4188d8a 7161 dev_kfree_skb(new_skb);
c58ec932 7162 ret = -1;
c58ec932 7163 } else {
b9e45482
MC		 7164 u32 save_entry = *entry;
7165
92cd3a17
MC		 7166 base_flags |= TXD_FLAG_END;
7167
84b67b27
MC		 7168 tnapi->tx_buffers[*entry].skb = new_skb;
7169 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
432aa7ed
MC		 7170 mapping, new_addr);
7171
84b67b27 7172 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
d1a3b737
MC		 7173 new_skb->len, base_flags,
7174 mss, vlan)) {
ba1142e4 7175 tg3_tx_skb_unmap(tnapi, save_entry, -1);
d1a3b737
MC		 7176 dev_kfree_skb(new_skb);
7177 ret = -1;
7178 }
f4188d8a 7179 }
1da177e4
LT		 7180 }
7181
7182 dev_kfree_skb(skb);
f7ff1987 7183 *pskb = new_skb;
c58ec932 7184 return ret;
1da177e4
LT		 7185}
7186
2ffcc981 7187static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
52c0fd83
MC		 7188
7189/* Use GSO to workaround a rare TSO bug that may be triggered when the
7190 * TSO header is greater than 80 bytes.
7191 */
7192static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
7193{
7194 struct sk_buff *segs, *nskb;
f3f3f27e 7195 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 7196
7197 /* Estimate the number of fragments in the worst case */
f3f3f27e 7198 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 7199 netif_stop_queue(tp->dev);
f65aac16
MC		 7200
7201 /* netif_tx_stop_queue() must be done before checking
7202 * checking tx index in tg3_tx_avail() below, because in
7203 * tg3_tx(), we update tx index before checking for
7204 * netif_tx_queue_stopped().
7205 */
7206 smp_mb();
f3f3f27e 7207 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 7208 return NETDEV_TX_BUSY;
7209
7210 netif_wake_queue(tp->dev);
52c0fd83
MC		 7211 }
7212
7213 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 7214 if (IS_ERR(segs))
52c0fd83
MC		 7215 goto tg3_tso_bug_end;
7216
7217 do {
7218 nskb = segs;
7219 segs = segs->next;
7220 nskb->next = NULL;
2ffcc981 7221 tg3_start_xmit(nskb, tp->dev);
52c0fd83
MC		 7222 } while (segs);
7223
7224tg3_tso_bug_end:
7225 dev_kfree_skb(skb);
7226
7227 return NETDEV_TX_OK;
7228}
52c0fd83 7229
5a6f3074 7230/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
63c3a66f 7231 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
5a6f3074 7232 */
2ffcc981 7233static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 7234{
7235 struct tg3 *tp = netdev_priv(dev);
92cd3a17 7236 u32 len, entry, base_flags, mss, vlan = 0;
84b67b27 7237 u32 budget;
432aa7ed 7238 int i = -1, would_hit_hwbug;
90079ce8 7239 dma_addr_t mapping;
24f4efd4
MC		 7240 struct tg3_napi *tnapi;
7241 struct netdev_queue *txq;
432aa7ed 7242 unsigned int last;
f4188d8a 7243
24f4efd4
MC		 7244 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7245 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
63c3a66f 7246 if (tg3_flag(tp, ENABLE_TSS))
24f4efd4 7247 tnapi++;
1da177e4 7248
84b67b27
MC		 7249 budget = tg3_tx_avail(tnapi);
7250
00b70504 7251 /* We are running in BH disabled context with netif_tx_lock
bea3348e 7252 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 7253 * interrupt. Furthermore, IRQ processing runs lockless so we have
7254 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 7255 */
84b67b27 7256 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 7257 if (!netif_tx_queue_stopped(txq)) {
7258 netif_tx_stop_queue(txq);
1f064a87
SH		 7259
7260 /* This is a hard error, log it. */
5129c3a3
MC		 7261 netdev_err(dev,
7262 "BUG! Tx Ring full when queue awake!\n");
1f064a87 7263 }
1da177e4
LT		 7264 return NETDEV_TX_BUSY;
7265 }
7266
f3f3f27e 7267 entry = tnapi->tx_prod;
1da177e4 7268 base_flags = 0;
84fa7933 7269 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 7270 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 7271
be98da6a
MC		 7272 mss = skb_shinfo(skb)->gso_size;
7273 if (mss) {
eddc9ec5 7274 struct iphdr *iph;
34195c3d 7275 u32 tcp_opt_len, hdr_len;
1da177e4
LT		 7276
7277 if (skb_header_cloned(skb) &&
48855432
ED		 7278 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7279 goto drop;
1da177e4 7280
34195c3d 7281 iph = ip_hdr(skb);
ab6a5bb6 7282 tcp_opt_len = tcp_optlen(skb);
1da177e4 7283
a5a11955 7284 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
34195c3d 7285
a5a11955 7286 if (!skb_is_gso_v6(skb)) {
34195c3d
MC		 7287 iph->check = 0;
7288 iph->tot_len = htons(mss + hdr_len);
7289 }
7290
52c0fd83 7291 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
63c3a66f 7292 tg3_flag(tp, TSO_BUG))
de6f31eb 7293 return tg3_tso_bug(tp, skb);
52c0fd83 7294
1da177e4
LT		 7295 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7296 TXD_FLAG_CPU_POST_DMA);
7297
63c3a66f
JP		 7298 if (tg3_flag(tp, HW_TSO_1) ||
7299 tg3_flag(tp, HW_TSO_2) ||
7300 tg3_flag(tp, HW_TSO_3)) {
aa8223c7 7301 tcp_hdr(skb)->check = 0;
1da177e4 7302 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 7303 } else
7304 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7305 iph->daddr, 0,
7306 IPPROTO_TCP,
7307 0);
1da177e4 7308
63c3a66f 7309 if (tg3_flag(tp, HW_TSO_3)) {
615774fe
MC		 7310 mss |= (hdr_len & 0xc) << 12;
7311 if (hdr_len & 0x10)
7312 base_flags |= 0x00000010;
7313 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 7314 } else if (tg3_flag(tp, HW_TSO_2))
92c6b8d1 7315 mss |= hdr_len << 9;
63c3a66f 7316 else if (tg3_flag(tp, HW_TSO_1) ||
92c6b8d1 7317 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 7318 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7319 int tsflags;
7320
eddc9ec5 7321 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7322 mss |= (tsflags << 11);
7323 }
7324 } else {
eddc9ec5 7325 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7326 int tsflags;
7327
eddc9ec5 7328 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7329 base_flags |= tsflags << 12;
7330 }
7331 }
7332 }
bf933c80 7333
93a700a9
MC		 7334 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7335 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7336 base_flags |= TXD_FLAG_JMB_PKT;
7337
92cd3a17
MC		 7338 if (vlan_tx_tag_present(skb)) {
7339 base_flags |= TXD_FLAG_VLAN;
7340 vlan = vlan_tx_tag_get(skb);
7341 }
1da177e4 7342
fb4ce8ad
MC		 7343 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
7344 tg3_flag(tp, TX_TSTAMP_EN)) {
7345 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7346 base_flags |= TXD_FLAG_HWTSTAMP;
7347 }
7348
f4188d8a
AD		 7349 len = skb_headlen(skb);
7350
7351 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
48855432
ED		 7352 if (pci_dma_mapping_error(tp->pdev, mapping))
7353 goto drop;
7354
90079ce8 7355
f3f3f27e 7356 tnapi->tx_buffers[entry].skb = skb;
4e5e4f0d 7357 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 7358
7359 would_hit_hwbug = 0;
7360
63c3a66f 7361 if (tg3_flag(tp, 5701_DMA_BUG))
c58ec932 7362 would_hit_hwbug = 1;
1da177e4 7363
84b67b27 7364 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
d1a3b737 7365 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
ba1142e4 7366 mss, vlan)) {
d1a3b737 7367 would_hit_hwbug = 1;
ba1142e4 7368 } else if (skb_shinfo(skb)->nr_frags > 0) {
92cd3a17
MC		 7369 u32 tmp_mss = mss;
7370
7371 if (!tg3_flag(tp, HW_TSO_1) &&
7372 !tg3_flag(tp, HW_TSO_2) &&
7373 !tg3_flag(tp, HW_TSO_3))
7374 tmp_mss = 0;
7375
c5665a53
MC		 7376 /* Now loop through additional data
7377 * fragments, and queue them.
7378 */
1da177e4
LT		 7379 last = skb_shinfo(skb)->nr_frags - 1;
7380 for (i = 0; i <= last; i++) {
7381 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7382
9e903e08 7383 len = skb_frag_size(frag);
dc234d0b 7384 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
5d6bcdfe 7385 len, DMA_TO_DEVICE);
1da177e4 7386
f3f3f27e 7387 tnapi->tx_buffers[entry].skb = NULL;
4e5e4f0d 7388 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
f4188d8a 7389 mapping);
5d6bcdfe 7390 if (dma_mapping_error(&tp->pdev->dev, mapping))
f4188d8a 7391 goto dma_error;
1da177e4 7392
b9e45482
MC		 7393 if (!budget ||
7394 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
84b67b27
MC		 7395 len, base_flags |
7396 ((i == last) ? TXD_FLAG_END : 0),
b9e45482 7397 tmp_mss, vlan)) {
72f2afb8 7398 would_hit_hwbug = 1;
b9e45482
MC		 7399 break;
7400 }
1da177e4
LT		 7401 }
7402 }
7403
7404 if (would_hit_hwbug) {
0d681b27 7405 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
1da177e4
LT		 7406
7407 /* If the workaround fails due to memory/mapping
7408 * failure, silently drop this packet.
7409 */
84b67b27
MC		 7410 entry = tnapi->tx_prod;
7411 budget = tg3_tx_avail(tnapi);
f7ff1987 7412 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
84b67b27 7413 base_flags, mss, vlan))
48855432 7414 goto drop_nofree;
1da177e4
LT		 7415 }
7416
d515b450 7417 skb_tx_timestamp(skb);
5cb917bc 7418 netdev_tx_sent_queue(txq, skb->len);
d515b450 7419
6541b806
MC		 7420 /* Sync BD data before updating mailbox */
7421 wmb();
7422
1da177e4 7423 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 7424 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 7425
f3f3f27e
MC		 7426 tnapi->tx_prod = entry;
7427 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 7428 netif_tx_stop_queue(txq);
f65aac16
MC		 7429
7430 /* netif_tx_stop_queue() must be done before checking
7431 * checking tx index in tg3_tx_avail() below, because in
7432 * tg3_tx(), we update tx index before checking for
7433 * netif_tx_queue_stopped().
7434 */
7435 smp_mb();
f3f3f27e 7436 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 7437 netif_tx_wake_queue(txq);
51b91468 7438 }
1da177e4 7439
cdd0db05 7440 mmiowb();
1da177e4 7441 return NETDEV_TX_OK;
f4188d8a
AD		 7442
7443dma_error:
ba1142e4 7444 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
432aa7ed 7445 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
48855432
ED		 7446drop:
7447 dev_kfree_skb(skb);
7448drop_nofree:
7449 tp->tx_dropped++;
f4188d8a 7450 return NETDEV_TX_OK;
1da177e4
LT		 7451}
7452
6e01b20b
MC		 7453static void tg3_mac_loopback(struct tg3 *tp, bool enable)
7454{
7455 if (enable) {
7456 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
7457 MAC_MODE_PORT_MODE_MASK);
7458
7459 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
7460
7461 if (!tg3_flag(tp, 5705_PLUS))
7462 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7463
7464 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
7465 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
7466 else
7467 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7468 } else {
7469 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
7470
7471 if (tg3_flag(tp, 5705_PLUS) ||
7472 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
7473 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
7474 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
7475 }
7476
7477 tw32(MAC_MODE, tp->mac_mode);
7478 udelay(40);
7479}
7480
941ec90f 7481static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
5e5a7f37 7482{
941ec90f 7483 u32 val, bmcr, mac_mode, ptest = 0;
5e5a7f37
MC		 7484
7485 tg3_phy_toggle_apd(tp, false);
7486 tg3_phy_toggle_automdix(tp, 0);
7487
941ec90f
MC		 7488 if (extlpbk && tg3_phy_set_extloopbk(tp))
7489 return -EIO;
7490
7491 bmcr = BMCR_FULLDPLX;
5e5a7f37
MC		 7492 switch (speed) {
7493 case SPEED_10:
7494 break;
7495 case SPEED_100:
7496 bmcr |= BMCR_SPEED100;
7497 break;
7498 case SPEED_1000:
7499 default:
7500 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7501 speed = SPEED_100;
7502 bmcr |= BMCR_SPEED100;
7503 } else {
7504 speed = SPEED_1000;
7505 bmcr |= BMCR_SPEED1000;
7506 }
7507 }
7508
941ec90f
MC		 7509 if (extlpbk) {
7510 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
7511 tg3_readphy(tp, MII_CTRL1000, &val);
7512 val |= CTL1000_AS_MASTER |
7513 CTL1000_ENABLE_MASTER;
7514 tg3_writephy(tp, MII_CTRL1000, val);
7515 } else {
7516 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
7517 MII_TG3_FET_PTEST_TRIM_2;
7518 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
7519 }
7520 } else
7521 bmcr |= BMCR_LOOPBACK;
7522
5e5a7f37
MC		 7523 tg3_writephy(tp, MII_BMCR, bmcr);
7524
7525 /* The write needs to be flushed for the FETs */
7526 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7527 tg3_readphy(tp, MII_BMCR, &bmcr);
7528
7529 udelay(40);
7530
7531 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
7532 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
941ec90f 7533 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
5e5a7f37
MC		 7534 MII_TG3_FET_PTEST_FRC_TX_LINK |
7535 MII_TG3_FET_PTEST_FRC_TX_LOCK);
7536
7537 /* The write needs to be flushed for the AC131 */
7538 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
7539 }
7540
7541 /* Reset to prevent losing 1st rx packet intermittently */
7542 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
7543 tg3_flag(tp, 5780_CLASS)) {
7544 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7545 udelay(10);
7546 tw32_f(MAC_RX_MODE, tp->rx_mode);
7547 }
7548
7549 mac_mode = tp->mac_mode &
7550 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
7551 if (speed == SPEED_1000)
7552 mac_mode |= MAC_MODE_PORT_MODE_GMII;
7553 else
7554 mac_mode |= MAC_MODE_PORT_MODE_MII;
7555
7556 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
7557 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
7558
7559 if (masked_phy_id == TG3_PHY_ID_BCM5401)
7560 mac_mode &= ~MAC_MODE_LINK_POLARITY;
7561 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
7562 mac_mode |= MAC_MODE_LINK_POLARITY;
7563
7564 tg3_writephy(tp, MII_TG3_EXT_CTRL,
7565 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
7566 }
7567
7568 tw32(MAC_MODE, mac_mode);
7569 udelay(40);
941ec90f
MC		 7570
7571 return 0;
5e5a7f37
MC		 7572}
7573
c8f44aff 7574static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
06c03c02
MB		 7575{
7576 struct tg3 *tp = netdev_priv(dev);
7577
7578 if (features & NETIF_F_LOOPBACK) {
7579 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
7580 return;
7581
06c03c02 7582 spin_lock_bh(&tp->lock);
6e01b20b 7583 tg3_mac_loopback(tp, true);
06c03c02
MB		 7584 netif_carrier_on(tp->dev);
7585 spin_unlock_bh(&tp->lock);
7586 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
7587 } else {
7588 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
7589 return;
7590
06c03c02 7591 spin_lock_bh(&tp->lock);
6e01b20b 7592 tg3_mac_loopback(tp, false);
06c03c02
MB		 7593 /* Force link status check */
7594 tg3_setup_phy(tp, 1);
7595 spin_unlock_bh(&tp->lock);
7596 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
7597 }
7598}
7599
c8f44aff
MM		 7600static netdev_features_t tg3_fix_features(struct net_device *dev,
7601 netdev_features_t features)
dc668910
MM		 7602{
7603 struct tg3 *tp = netdev_priv(dev);
7604
63c3a66f 7605 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
dc668910
MM		 7606 features &= ~NETIF_F_ALL_TSO;
7607
7608 return features;
7609}
7610
c8f44aff 7611static int tg3_set_features(struct net_device *dev, netdev_features_t features)
06c03c02 7612{
c8f44aff 7613 netdev_features_t changed = dev->features ^ features;
06c03c02
MB		 7614
7615 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
7616 tg3_set_loopback(dev, features);
7617
7618 return 0;
7619}
7620
21f581a5
MC		 7621static void tg3_rx_prodring_free(struct tg3 *tp,
7622 struct tg3_rx_prodring_set *tpr)
1da177e4 7623{
1da177e4
LT		 7624 int i;
7625
8fea32b9 7626 if (tpr != &tp->napi[0].prodring) {
b196c7e4 7627 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
2c49a44d 7628 i = (i + 1) & tp->rx_std_ring_mask)
9205fd9c 7629 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
b196c7e4
MC		 7630 tp->rx_pkt_map_sz);
7631
63c3a66f 7632 if (tg3_flag(tp, JUMBO_CAPABLE)) {
b196c7e4
MC		 7633 for (i = tpr->rx_jmb_cons_idx;
7634 i != tpr->rx_jmb_prod_idx;
2c49a44d 7635 i = (i + 1) & tp->rx_jmb_ring_mask) {
9205fd9c 7636 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
b196c7e4
MC		 7637 TG3_RX_JMB_MAP_SZ);
7638 }
7639 }
7640
2b2cdb65 7641 return;
b196c7e4 7642 }
1da177e4 7643
2c49a44d 7644 for (i = 0; i <= tp->rx_std_ring_mask; i++)
9205fd9c 7645 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
2b2cdb65 7646 tp->rx_pkt_map_sz);
1da177e4 7647
63c3a66f 7648 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 7649 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
9205fd9c 7650 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
2b2cdb65 7651 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 7652 }
7653}
7654
c6cdf436 7655/* Initialize rx rings for packet processing.
1da177e4
LT		 7656 *
7657 * The chip has been shut down and the driver detached from
7658 * the networking, so no interrupts or new tx packets will
7659 * end up in the driver. tp->{tx,}lock are held and thus
7660 * we may not sleep.
7661 */
21f581a5
MC		 7662static int tg3_rx_prodring_alloc(struct tg3 *tp,
7663 struct tg3_rx_prodring_set *tpr)
1da177e4 7664{
287be12e 7665 u32 i, rx_pkt_dma_sz;
1da177e4 7666
b196c7e4
MC		 7667 tpr->rx_std_cons_idx = 0;
7668 tpr->rx_std_prod_idx = 0;
7669 tpr->rx_jmb_cons_idx = 0;
7670 tpr->rx_jmb_prod_idx = 0;
7671
8fea32b9 7672 if (tpr != &tp->napi[0].prodring) {
2c49a44d
MC		 7673 memset(&tpr->rx_std_buffers[0], 0,
7674 TG3_RX_STD_BUFF_RING_SIZE(tp));
48035728 7675 if (tpr->rx_jmb_buffers)
2b2cdb65 7676 memset(&tpr->rx_jmb_buffers[0], 0,
2c49a44d 7677 TG3_RX_JMB_BUFF_RING_SIZE(tp));
2b2cdb65
MC		 7678 goto done;
7679 }
7680
1da177e4 7681 /* Zero out all descriptors. */
2c49a44d 7682 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
1da177e4 7683
287be12e 7684 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
63c3a66f 7685 if (tg3_flag(tp, 5780_CLASS) &&
287be12e
MC		 7686 tp->dev->mtu > ETH_DATA_LEN)
7687 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
7688 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 7689
1da177e4
LT		 7690 /* Initialize invariants of the rings, we only set this
7691 * stuff once. This works because the card does not
7692 * write into the rx buffer posting rings.
7693 */
2c49a44d 7694 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
1da177e4
LT		 7695 struct tg3_rx_buffer_desc *rxd;
7696
21f581a5 7697 rxd = &tpr->rx_std[i];
287be12e 7698 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 7699 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
7700 rxd->opaque = (RXD_OPAQUE_RING_STD |
7701 (i << RXD_OPAQUE_INDEX_SHIFT));
7702 }
7703
1da177e4
LT		 7704 /* Now allocate fresh SKBs for each rx ring. */
7705 for (i = 0; i < tp->rx_pending; i++) {
8d4057a9
ED		 7706 unsigned int frag_size;
7707
7708 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
7709 &frag_size) < 0) {
5129c3a3
MC		 7710 netdev_warn(tp->dev,
7711 "Using a smaller RX standard ring. Only "
7712 "%d out of %d buffers were allocated "
7713 "successfully\n", i, tp->rx_pending);
32d8c572 7714 if (i == 0)
cf7a7298 7715 goto initfail;
32d8c572 7716 tp->rx_pending = i;
1da177e4 7717 break;
32d8c572 7718 }
1da177e4
LT		 7719 }
7720
63c3a66f 7721 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
cf7a7298
MC		 7722 goto done;
7723
2c49a44d 7724 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
cf7a7298 7725
63c3a66f 7726 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
0d86df80 7727 goto done;
cf7a7298 7728
2c49a44d 7729 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
0d86df80
MC		 7730 struct tg3_rx_buffer_desc *rxd;
7731
7732 rxd = &tpr->rx_jmb[i].std;
7733 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
7734 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
7735 RXD_FLAG_JUMBO;
7736 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
7737 (i << RXD_OPAQUE_INDEX_SHIFT));
7738 }
7739
7740 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8d4057a9
ED		 7741 unsigned int frag_size;
7742
7743 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
7744 &frag_size) < 0) {
5129c3a3
MC		 7745 netdev_warn(tp->dev,
7746 "Using a smaller RX jumbo ring. Only %d "
7747 "out of %d buffers were allocated "
7748 "successfully\n", i, tp->rx_jumbo_pending);
0d86df80
MC		 7749 if (i == 0)
7750 goto initfail;
7751 tp->rx_jumbo_pending = i;
7752 break;
1da177e4
LT		 7753 }
7754 }
cf7a7298
MC		 7755
7756done:
32d8c572 7757 return 0;
cf7a7298
MC		 7758
7759initfail:
21f581a5 7760 tg3_rx_prodring_free(tp, tpr);
cf7a7298 7761 return -ENOMEM;
1da177e4
LT		 7762}
7763
21f581a5
MC		 7764static void tg3_rx_prodring_fini(struct tg3 *tp,
7765 struct tg3_rx_prodring_set *tpr)
1da177e4 7766{
21f581a5
MC		 7767 kfree(tpr->rx_std_buffers);
7768 tpr->rx_std_buffers = NULL;
7769 kfree(tpr->rx_jmb_buffers);
7770 tpr->rx_jmb_buffers = NULL;
7771 if (tpr->rx_std) {
4bae65c8
MC		 7772 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
7773 tpr->rx_std, tpr->rx_std_mapping);
21f581a5 7774 tpr->rx_std = NULL;
1da177e4 7775 }
21f581a5 7776 if (tpr->rx_jmb) {
4bae65c8
MC		 7777 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
7778 tpr->rx_jmb, tpr->rx_jmb_mapping);
21f581a5 7779 tpr->rx_jmb = NULL;
1da177e4 7780 }
cf7a7298
MC		 7781}
7782
21f581a5
MC		 7783static int tg3_rx_prodring_init(struct tg3 *tp,
7784 struct tg3_rx_prodring_set *tpr)
cf7a7298 7785{
2c49a44d
MC		 7786 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
7787 GFP_KERNEL);
21f581a5 7788 if (!tpr->rx_std_buffers)
cf7a7298
MC		 7789 return -ENOMEM;
7790
4bae65c8
MC		 7791 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
7792 TG3_RX_STD_RING_BYTES(tp),
7793 &tpr->rx_std_mapping,
7794 GFP_KERNEL);
21f581a5 7795 if (!tpr->rx_std)
cf7a7298
MC		 7796 goto err_out;
7797
63c3a66f 7798 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 7799 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
21f581a5
MC		 7800 GFP_KERNEL);
7801 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 7802 goto err_out;
7803
4bae65c8
MC		 7804 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
7805 TG3_RX_JMB_RING_BYTES(tp),
7806 &tpr->rx_jmb_mapping,
7807 GFP_KERNEL);
21f581a5 7808 if (!tpr->rx_jmb)
cf7a7298
MC		 7809 goto err_out;
7810 }
7811
7812 return 0;
7813
7814err_out:
21f581a5 7815 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 7816 return -ENOMEM;
7817}
7818
7819/* Free up pending packets in all rx/tx rings.
7820 *
7821 * The chip has been shut down and the driver detached from
7822 * the networking, so no interrupts or new tx packets will
7823 * end up in the driver. tp->{tx,}lock is not held and we are not
7824 * in an interrupt context and thus may sleep.
7825 */
7826static void tg3_free_rings(struct tg3 *tp)
7827{
f77a6a8e 7828 int i, j;
cf7a7298 7829
f77a6a8e
MC		 7830 for (j = 0; j < tp->irq_cnt; j++) {
7831 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 7832
8fea32b9 7833 tg3_rx_prodring_free(tp, &tnapi->prodring);
b28f6428 7834
0c1d0e2b
MC		 7835 if (!tnapi->tx_buffers)
7836 continue;
7837
0d681b27
MC		 7838 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
7839 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
cf7a7298 7840
0d681b27 7841 if (!skb)
f77a6a8e 7842 continue;
cf7a7298 7843
ba1142e4
MC		 7844 tg3_tx_skb_unmap(tnapi, i,
7845 skb_shinfo(skb)->nr_frags - 1);
f77a6a8e
MC		 7846
7847 dev_kfree_skb_any(skb);
7848 }
5cb917bc 7849 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
2b2cdb65 7850 }
cf7a7298
MC		 7851}
7852
7853/* Initialize tx/rx rings for packet processing.
7854 *
7855 * The chip has been shut down and the driver detached from
7856 * the networking, so no interrupts or new tx packets will
7857 * end up in the driver. tp->{tx,}lock are held and thus
7858 * we may not sleep.
7859 */
7860static int tg3_init_rings(struct tg3 *tp)
7861{
f77a6a8e 7862 int i;
72334482 7863
cf7a7298
MC		 7864 /* Free up all the SKBs. */
7865 tg3_free_rings(tp);
7866
f77a6a8e
MC		 7867 for (i = 0; i < tp->irq_cnt; i++) {
7868 struct tg3_napi *tnapi = &tp->napi[i];
7869
7870 tnapi->last_tag = 0;
7871 tnapi->last_irq_tag = 0;
7872 tnapi->hw_status->status = 0;
7873 tnapi->hw_status->status_tag = 0;
7874 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 7875
f77a6a8e
MC		 7876 tnapi->tx_prod = 0;
7877 tnapi->tx_cons = 0;
0c1d0e2b
MC		 7878 if (tnapi->tx_ring)
7879 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 7880
7881 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 7882 if (tnapi->rx_rcb)
7883 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 7884
8fea32b9 7885 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
e4af1af9 7886 tg3_free_rings(tp);
2b2cdb65 7887 return -ENOMEM;
e4af1af9 7888 }
f77a6a8e 7889 }
72334482 7890
2b2cdb65 7891 return 0;
cf7a7298
MC		 7892}
7893
49a359e3 7894static void tg3_mem_tx_release(struct tg3 *tp)
cf7a7298 7895{
f77a6a8e 7896 int i;
898a56f8 7897
49a359e3 7898 for (i = 0; i < tp->irq_max; i++) {
f77a6a8e
MC		 7899 struct tg3_napi *tnapi = &tp->napi[i];
7900
7901 if (tnapi->tx_ring) {
4bae65c8 7902 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
f77a6a8e
MC		 7903 tnapi->tx_ring, tnapi->tx_desc_mapping);
7904 tnapi->tx_ring = NULL;
7905 }
7906
7907 kfree(tnapi->tx_buffers);
7908 tnapi->tx_buffers = NULL;
49a359e3
MC		 7909 }
7910}
f77a6a8e 7911
49a359e3
MC		 7912static int tg3_mem_tx_acquire(struct tg3 *tp)
7913{
7914 int i;
7915 struct tg3_napi *tnapi = &tp->napi[0];
7916
7917 /* If multivector TSS is enabled, vector 0 does not handle
7918 * tx interrupts. Don't allocate any resources for it.
7919 */
7920 if (tg3_flag(tp, ENABLE_TSS))
7921 tnapi++;
7922
7923 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
7924 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
7925 TG3_TX_RING_SIZE, GFP_KERNEL);
7926 if (!tnapi->tx_buffers)
7927 goto err_out;
7928
7929 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
7930 TG3_TX_RING_BYTES,
7931 &tnapi->tx_desc_mapping,
7932 GFP_KERNEL);
7933 if (!tnapi->tx_ring)
7934 goto err_out;
7935 }
7936
7937 return 0;
7938
7939err_out:
7940 tg3_mem_tx_release(tp);
7941 return -ENOMEM;
7942}
7943
7944static void tg3_mem_rx_release(struct tg3 *tp)
7945{
7946 int i;
7947
7948 for (i = 0; i < tp->irq_max; i++) {
7949 struct tg3_napi *tnapi = &tp->napi[i];
f77a6a8e 7950
8fea32b9
MC		 7951 tg3_rx_prodring_fini(tp, &tnapi->prodring);
7952
49a359e3
MC		 7953 if (!tnapi->rx_rcb)
7954 continue;
7955
7956 dma_free_coherent(&tp->pdev->dev,
7957 TG3_RX_RCB_RING_BYTES(tp),
7958 tnapi->rx_rcb,
7959 tnapi->rx_rcb_mapping);
7960 tnapi->rx_rcb = NULL;
7961 }
7962}
7963
7964static int tg3_mem_rx_acquire(struct tg3 *tp)
7965{
7966 unsigned int i, limit;
7967
7968 limit = tp->rxq_cnt;
7969
7970 /* If RSS is enabled, we need a (dummy) producer ring
7971 * set on vector zero. This is the true hw prodring.
7972 */
7973 if (tg3_flag(tp, ENABLE_RSS))
7974 limit++;
7975
7976 for (i = 0; i < limit; i++) {
7977 struct tg3_napi *tnapi = &tp->napi[i];
7978
7979 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
7980 goto err_out;
7981
7982 /* If multivector RSS is enabled, vector 0
7983 * does not handle rx or tx interrupts.
7984 * Don't allocate any resources for it.
7985 */
7986 if (!i && tg3_flag(tp, ENABLE_RSS))
7987 continue;
7988
7989 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
7990 TG3_RX_RCB_RING_BYTES(tp),
7991 &tnapi->rx_rcb_mapping,
7992 GFP_KERNEL);
7993 if (!tnapi->rx_rcb)
7994 goto err_out;
7995
7996 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7997 }
7998
7999 return 0;
8000
8001err_out:
8002 tg3_mem_rx_release(tp);
8003 return -ENOMEM;
8004}
8005
8006/*
8007 * Must not be invoked with interrupt sources disabled and
8008 * the hardware shutdown down.
8009 */
8010static void tg3_free_consistent(struct tg3 *tp)
8011{
8012 int i;
8013
8014 for (i = 0; i < tp->irq_cnt; i++) {
8015 struct tg3_napi *tnapi = &tp->napi[i];
8016
f77a6a8e 8017 if (tnapi->hw_status) {
4bae65c8
MC		 8018 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8019 tnapi->hw_status,
8020 tnapi->status_mapping);
f77a6a8e
MC		 8021 tnapi->hw_status = NULL;
8022 }
1da177e4 8023 }
f77a6a8e 8024
49a359e3
MC		 8025 tg3_mem_rx_release(tp);
8026 tg3_mem_tx_release(tp);
8027
1da177e4 8028 if (tp->hw_stats) {
4bae65c8
MC		 8029 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8030 tp->hw_stats, tp->stats_mapping);
1da177e4
LT		 8031 tp->hw_stats = NULL;
8032 }
8033}
8034
8035/*
8036 * Must not be invoked with interrupt sources disabled and
8037 * the hardware shutdown down. Can sleep.
8038 */
8039static int tg3_alloc_consistent(struct tg3 *tp)
8040{
f77a6a8e 8041 int i;
898a56f8 8042
4bae65c8
MC		 8043 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
8044 sizeof(struct tg3_hw_stats),
8045 &tp->stats_mapping,
8046 GFP_KERNEL);
f77a6a8e 8047 if (!tp->hw_stats)
1da177e4
LT		 8048 goto err_out;
8049
f77a6a8e 8050 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 8051
f77a6a8e
MC		 8052 for (i = 0; i < tp->irq_cnt; i++) {
8053 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 8054 struct tg3_hw_status *sblk;
1da177e4 8055
4bae65c8
MC		 8056 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
8057 TG3_HW_STATUS_SIZE,
8058 &tnapi->status_mapping,
8059 GFP_KERNEL);
f77a6a8e
MC		 8060 if (!tnapi->hw_status)
8061 goto err_out;
898a56f8 8062
f77a6a8e 8063 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 8064 sblk = tnapi->hw_status;
8065
49a359e3 8066 if (tg3_flag(tp, ENABLE_RSS)) {
86449944 8067 u16 *prodptr = NULL;
8fea32b9 8068
49a359e3
MC		 8069 /*
8070 * When RSS is enabled, the status block format changes
8071 * slightly. The "rx_jumbo_consumer", "reserved",
8072 * and "rx_mini_consumer" members get mapped to the
8073 * other three rx return ring producer indexes.
8074 */
8075 switch (i) {
8076 case 1:
8077 prodptr = &sblk->idx[0].rx_producer;
8078 break;
8079 case 2:
8080 prodptr = &sblk->rx_jumbo_consumer;
8081 break;
8082 case 3:
8083 prodptr = &sblk->reserved;
8084 break;
8085 case 4:
8086 prodptr = &sblk->rx_mini_consumer;
f891ea16
MC		 8087 break;
8088 }
49a359e3
MC		 8089 tnapi->rx_rcb_prod_idx = prodptr;
8090 } else {
8d9d7cfc 8091 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8d9d7cfc 8092 }
f77a6a8e 8093 }
1da177e4 8094
49a359e3
MC		 8095 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8096 goto err_out;
8097
1da177e4
LT		 8098 return 0;
8099
8100err_out:
8101 tg3_free_consistent(tp);
8102 return -ENOMEM;
8103}
8104
8105#define MAX_WAIT_CNT 1000
8106
8107/* To stop a block, clear the enable bit and poll till it
8108 * clears. tp->lock is held.
8109 */
b3b7d6be 8110static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 8111{
8112 unsigned int i;
8113 u32 val;
8114
63c3a66f 8115 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 8116 switch (ofs) {
8117 case RCVLSC_MODE:
8118 case DMAC_MODE:
8119 case MBFREE_MODE:
8120 case BUFMGR_MODE:
8121 case MEMARB_MODE:
8122 /* We can't enable/disable these bits of the
8123 * 5705/5750, just say success.
8124 */
8125 return 0;
8126
8127 default:
8128 break;
855e1111 8129 }
1da177e4
LT		 8130 }
8131
8132 val = tr32(ofs);
8133 val &= ~enable_bit;
8134 tw32_f(ofs, val);
8135
8136 for (i = 0; i < MAX_WAIT_CNT; i++) {
8137 udelay(100);
8138 val = tr32(ofs);
8139 if ((val & enable_bit) == 0)
8140 break;
8141 }
8142
b3b7d6be 8143 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 8144 dev_err(&tp->pdev->dev,
8145 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8146 ofs, enable_bit);
1da177e4
LT		 8147 return -ENODEV;
8148 }
8149
8150 return 0;
8151}
8152
8153/* tp->lock is held. */
b3b7d6be 8154static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 8155{
8156 int i, err;
8157
8158 tg3_disable_ints(tp);
8159
8160 tp->rx_mode &= ~RX_MODE_ENABLE;
8161 tw32_f(MAC_RX_MODE, tp->rx_mode);
8162 udelay(10);
8163
b3b7d6be
DM		 8164 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8165 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8166 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8167 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8168 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8169 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8170
8171 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8172 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8173 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8174 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8175 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8176 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8177 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 8178
8179 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8180 tw32_f(MAC_MODE, tp->mac_mode);
8181 udelay(40);
8182
8183 tp->tx_mode &= ~TX_MODE_ENABLE;
8184 tw32_f(MAC_TX_MODE, tp->tx_mode);
8185
8186 for (i = 0; i < MAX_WAIT_CNT; i++) {
8187 udelay(100);
8188 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8189 break;
8190 }
8191 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 8192 dev_err(&tp->pdev->dev,
8193 "%s timed out, TX_MODE_ENABLE will not clear "
8194 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 8195 err |= -ENODEV;
1da177e4
LT		 8196 }
8197
e6de8ad1 8198 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 8199 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8200 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 8201
8202 tw32(FTQ_RESET, 0xffffffff);
8203 tw32(FTQ_RESET, 0x00000000);
8204
b3b7d6be
DM		 8205 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8206 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 8207
f77a6a8e
MC		 8208 for (i = 0; i < tp->irq_cnt; i++) {
8209 struct tg3_napi *tnapi = &tp->napi[i];
8210 if (tnapi->hw_status)
8211 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8212 }
1da177e4 8213
1da177e4
LT		 8214 return err;
8215}
8216
ee6a99b5
MC		 8217/* Save PCI command register before chip reset */
8218static void tg3_save_pci_state(struct tg3 *tp)
8219{
8a6eac90 8220 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 8221}
8222
8223/* Restore PCI state after chip reset */
8224static void tg3_restore_pci_state(struct tg3 *tp)
8225{
8226 u32 val;
8227
8228 /* Re-enable indirect register accesses. */
8229 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8230 tp->misc_host_ctrl);
8231
8232 /* Set MAX PCI retry to zero. */
8233 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
8234 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
63c3a66f 8235 tg3_flag(tp, PCIX_MODE))
ee6a99b5 8236 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9 8237 /* Allow reads and writes to the APE register and memory space. */
63c3a66f 8238 if (tg3_flag(tp, ENABLE_APE))
0d3031d9 8239 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 8240 PCISTATE_ALLOW_APE_SHMEM_WR |
8241 PCISTATE_ALLOW_APE_PSPACE_WR;
ee6a99b5
MC		 8242 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8243
8a6eac90 8244 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 8245
2c55a3d0
MC		 8246 if (!tg3_flag(tp, PCI_EXPRESS)) {
8247 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8248 tp->pci_cacheline_sz);
8249 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8250 tp->pci_lat_timer);
114342f2 8251 }
5f5c51e3 8252
ee6a99b5 8253 /* Make sure PCI-X relaxed ordering bit is clear. */
63c3a66f 8254 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 8255 u16 pcix_cmd;
8256
8257 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8258 &pcix_cmd);
8259 pcix_cmd &= ~PCI_X_CMD_ERO;
8260 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8261 pcix_cmd);
8262 }
ee6a99b5 8263
63c3a66f 8264 if (tg3_flag(tp, 5780_CLASS)) {
ee6a99b5
MC		 8265
8266 /* Chip reset on 5780 will reset MSI enable bit,
8267 * so need to restore it.
8268 */
63c3a66f 8269 if (tg3_flag(tp, USING_MSI)) {
ee6a99b5
MC		 8270 u16 ctrl;
8271
8272 pci_read_config_word(tp->pdev,
8273 tp->msi_cap + PCI_MSI_FLAGS,
8274 &ctrl);
8275 pci_write_config_word(tp->pdev,
8276 tp->msi_cap + PCI_MSI_FLAGS,
8277 ctrl | PCI_MSI_FLAGS_ENABLE);
8278 val = tr32(MSGINT_MODE);
8279 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8280 }
8281 }
8282}
8283
1da177e4
LT		 8284/* tp->lock is held. */
8285static int tg3_chip_reset(struct tg3 *tp)
8286{
8287 u32 val;
1ee582d8 8288 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 8289 int i, err;
1da177e4 8290
f49639e6
DM		 8291 tg3_nvram_lock(tp);
8292
77b483f1
MC		 8293 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
8294
f49639e6
DM		 8295 /* No matching tg3_nvram_unlock() after this because
8296 * chip reset below will undo the nvram lock.
8297 */
8298 tp->nvram_lock_cnt = 0;
1da177e4 8299
ee6a99b5
MC		 8300 /* GRC_MISC_CFG core clock reset will clear the memory
8301 * enable bit in PCI register 4 and the MSI enable bit
8302 * on some chips, so we save relevant registers here.
8303 */
8304 tg3_save_pci_state(tp);
8305
d9ab5ad1 8306 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
63c3a66f 8307 tg3_flag(tp, 5755_PLUS))
d9ab5ad1
MC		 8308 tw32(GRC_FASTBOOT_PC, 0);
8309
1da177e4
LT		 8310 /*
8311 * We must avoid the readl() that normally takes place.
8312 * It locks machines, causes machine checks, and other
8313 * fun things. So, temporarily disable the 5701
8314 * hardware workaround, while we do the reset.
8315 */
1ee582d8
MC		 8316 write_op = tp->write32;
8317 if (write_op == tg3_write_flush_reg32)
8318 tp->write32 = tg3_write32;
1da177e4 8319
d18edcb2
MC		 8320 /* Prevent the irq handler from reading or writing PCI registers
8321 * during chip reset when the memory enable bit in the PCI command
8322 * register may be cleared. The chip does not generate interrupt
8323 * at this time, but the irq handler may still be called due to irq
8324 * sharing or irqpoll.
8325 */
63c3a66f 8326 tg3_flag_set(tp, CHIP_RESETTING);
f77a6a8e
MC		 8327 for (i = 0; i < tp->irq_cnt; i++) {
8328 struct tg3_napi *tnapi = &tp->napi[i];
8329 if (tnapi->hw_status) {
8330 tnapi->hw_status->status = 0;
8331 tnapi->hw_status->status_tag = 0;
8332 }
8333 tnapi->last_tag = 0;
8334 tnapi->last_irq_tag = 0;
b8fa2f3a 8335 }
d18edcb2 8336 smp_mb();
4f125f42
MC		 8337
8338 for (i = 0; i < tp->irq_cnt; i++)
8339 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 8340
255ca311
MC		 8341 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8342 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8343 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8344 }
8345
1da177e4
LT		 8346 /* do the reset */
8347 val = GRC_MISC_CFG_CORECLK_RESET;
8348
63c3a66f 8349 if (tg3_flag(tp, PCI_EXPRESS)) {
88075d91
MC		 8350 /* Force PCIe 1.0a mode */
8351 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
63c3a66f 8352 !tg3_flag(tp, 57765_PLUS) &&
88075d91
MC		 8353 tr32(TG3_PCIE_PHY_TSTCTL) ==
8354 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
8355 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
8356
1da177e4
LT		 8357 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
8358 tw32(GRC_MISC_CFG, (1 << 29));
8359 val |= (1 << 29);
8360 }
8361 }
8362
b5d3772c
MC		 8363 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8364 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
8365 tw32(GRC_VCPU_EXT_CTRL,
8366 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
8367 }
8368
f37500d3 8369 /* Manage gphy power for all CPMU absent PCIe devices. */
63c3a66f 8370 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
1da177e4 8371 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
f37500d3 8372
1da177e4
LT		 8373 tw32(GRC_MISC_CFG, val);
8374
1ee582d8
MC		 8375 /* restore 5701 hardware bug workaround write method */
8376 tp->write32 = write_op;
1da177e4
LT		 8377
8378 /* Unfortunately, we have to delay before the PCI read back.
8379 * Some 575X chips even will not respond to a PCI cfg access
8380 * when the reset command is given to the chip.
8381 *
8382 * How do these hardware designers expect things to work
8383 * properly if the PCI write is posted for a long period
8384 * of time? It is always necessary to have some method by
8385 * which a register read back can occur to push the write
8386 * out which does the reset.
8387 *
8388 * For most tg3 variants the trick below was working.
8389 * Ho hum...
8390 */
8391 udelay(120);
8392
8393 /* Flush PCI posted writes. The normal MMIO registers
8394 * are inaccessible at this time so this is the only
8395 * way to make this reliably (actually, this is no longer
8396 * the case, see above). I tried to use indirect
8397 * register read/write but this upset some 5701 variants.
8398 */
8399 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
8400
8401 udelay(120);
8402
0f49bfbd 8403 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
e7126997
MC		 8404 u16 val16;
8405
1da177e4 8406 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
86449944 8407 int j;
1da177e4
LT		 8408 u32 cfg_val;
8409
8410 /* Wait for link training to complete. */
86449944 8411 for (j = 0; j < 5000; j++)
1da177e4
LT		 8412 udelay(100);
8413
8414 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
8415 pci_write_config_dword(tp->pdev, 0xc4,
8416 cfg_val | (1 << 15));
8417 }
5e7dfd0f 8418
e7126997 8419 /* Clear the "no snoop" and "relaxed ordering" bits. */
0f49bfbd 8420 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
e7126997
MC		 8421 /*
8422 * Older PCIe devices only support the 128 byte
8423 * MPS setting. Enforce the restriction.
5e7dfd0f 8424 */
63c3a66f 8425 if (!tg3_flag(tp, CPMU_PRESENT))
0f49bfbd
JL		 8426 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
8427 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
5e7dfd0f 8428
5e7dfd0f 8429 /* Clear error status */
0f49bfbd 8430 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
5e7dfd0f
MC		 8431 PCI_EXP_DEVSTA_CED |
8432 PCI_EXP_DEVSTA_NFED |
8433 PCI_EXP_DEVSTA_FED |
8434 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 8435 }
8436
ee6a99b5 8437 tg3_restore_pci_state(tp);
1da177e4 8438
63c3a66f
JP		 8439 tg3_flag_clear(tp, CHIP_RESETTING);
8440 tg3_flag_clear(tp, ERROR_PROCESSED);
d18edcb2 8441
ee6a99b5 8442 val = 0;
63c3a66f 8443 if (tg3_flag(tp, 5780_CLASS))
4cf78e4f 8444 val = tr32(MEMARB_MODE);
ee6a99b5 8445 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 8446
8447 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
8448 tg3_stop_fw(tp);
8449 tw32(0x5000, 0x400);
8450 }
8451
8452 tw32(GRC_MODE, tp->grc_mode);
8453
8454 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 8455 val = tr32(0xc4);
1da177e4
LT		 8456
8457 tw32(0xc4, val | (1 << 15));
8458 }
8459
8460 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
8461 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8462 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
8463 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
8464 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
8465 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8466 }
8467
f07e9af3 8468 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9e975cc2 8469 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
d2394e6b 8470 val = tp->mac_mode;
f07e9af3 8471 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9e975cc2 8472 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
d2394e6b 8473 val = tp->mac_mode;
1da177e4 8474 } else
d2394e6b
MC		 8475 val = 0;
8476
8477 tw32_f(MAC_MODE, val);
1da177e4
LT		 8478 udelay(40);
8479
77b483f1
MC		 8480 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
8481
7a6f4369
MC		 8482 err = tg3_poll_fw(tp);
8483 if (err)
8484 return err;
1da177e4 8485
0a9140cf
MC		 8486 tg3_mdio_start(tp);
8487
63c3a66f 8488 if (tg3_flag(tp, PCI_EXPRESS) &&
f6eb9b1f
MC		 8489 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
8490 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
63c3a66f 8491 !tg3_flag(tp, 57765_PLUS)) {
ab0049b4 8492 val = tr32(0x7c00);
1da177e4
LT		 8493
8494 tw32(0x7c00, val | (1 << 25));
8495 }
8496
d78b59f5
MC		 8497 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8498 val = tr32(TG3_CPMU_CLCK_ORIDE);
8499 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8500 }
8501
1da177e4 8502 /* Reprobe ASF enable state. */
63c3a66f
JP		 8503 tg3_flag_clear(tp, ENABLE_ASF);
8504 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
1da177e4
LT		 8505 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
8506 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
8507 u32 nic_cfg;
8508
8509 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
8510 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f 8511 tg3_flag_set(tp, ENABLE_ASF);
4ba526ce 8512 tp->last_event_jiffies = jiffies;
63c3a66f
JP		 8513 if (tg3_flag(tp, 5750_PLUS))
8514 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
1da177e4
LT		 8515 }
8516 }
8517
8518 return 0;
8519}
8520
65ec698d
MC		 8521static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
8522static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
92feeabf 8523
1da177e4 8524/* tp->lock is held. */
944d980e 8525static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 8526{
8527 int err;
8528
8529 tg3_stop_fw(tp);
8530
944d980e 8531 tg3_write_sig_pre_reset(tp, kind);
1da177e4 8532
b3b7d6be 8533 tg3_abort_hw(tp, silent);
1da177e4
LT		 8534 err = tg3_chip_reset(tp);
8535
daba2a63
MC		 8536 __tg3_set_mac_addr(tp, 0);
8537
944d980e
MC		 8538 tg3_write_sig_legacy(tp, kind);
8539 tg3_write_sig_post_reset(tp, kind);
1da177e4 8540
92feeabf
MC		 8541 if (tp->hw_stats) {
8542 /* Save the stats across chip resets... */
b4017c53 8543 tg3_get_nstats(tp, &tp->net_stats_prev);
92feeabf
MC		 8544 tg3_get_estats(tp, &tp->estats_prev);
8545
8546 /* And make sure the next sample is new data */
8547 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
8548 }
8549
1da177e4
LT		 8550 if (err)
8551 return err;
8552
8553 return 0;
8554}
8555
1da177e4
LT		 8556static int tg3_set_mac_addr(struct net_device *dev, void *p)
8557{
8558 struct tg3 *tp = netdev_priv(dev);
8559 struct sockaddr *addr = p;
986e0aeb 8560 int err = 0, skip_mac_1 = 0;
1da177e4 8561
f9804ddb 8562 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 8563 return -EADDRNOTAVAIL;
f9804ddb 8564
1da177e4
LT		 8565 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
8566
e75f7c90
MC		 8567 if (!netif_running(dev))
8568 return 0;
8569
63c3a66f 8570 if (tg3_flag(tp, ENABLE_ASF)) {
986e0aeb 8571 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 8572
986e0aeb
MC		 8573 addr0_high = tr32(MAC_ADDR_0_HIGH);
8574 addr0_low = tr32(MAC_ADDR_0_LOW);
8575 addr1_high = tr32(MAC_ADDR_1_HIGH);
8576 addr1_low = tr32(MAC_ADDR_1_LOW);
8577
8578 /* Skip MAC addr 1 if ASF is using it. */
8579 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
8580 !(addr1_high == 0 && addr1_low == 0))
8581 skip_mac_1 = 1;
58712ef9 8582 }
986e0aeb
MC		 8583 spin_lock_bh(&tp->lock);
8584 __tg3_set_mac_addr(tp, skip_mac_1);
8585 spin_unlock_bh(&tp->lock);
1da177e4 8586
b9ec6c1b 8587 return err;
1da177e4
LT		 8588}
8589
8590/* tp->lock is held. */
8591static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
8592 dma_addr_t mapping, u32 maxlen_flags,
8593 u32 nic_addr)
8594{
8595 tg3_write_mem(tp,
8596 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
8597 ((u64) mapping >> 32));
8598 tg3_write_mem(tp,
8599 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
8600 ((u64) mapping & 0xffffffff));
8601 tg3_write_mem(tp,
8602 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
8603 maxlen_flags);
8604
63c3a66f 8605 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 8606 tg3_write_mem(tp,
8607 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
8608 nic_addr);
8609}
8610
a489b6d9
MC		 8611
8612static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 8613{
a489b6d9 8614 int i = 0;
b6080e12 8615
63c3a66f 8616 if (!tg3_flag(tp, ENABLE_TSS)) {
b6080e12
MC		 8617 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
8618 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
8619 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 8620 } else {
8621 tw32(HOSTCC_TXCOL_TICKS, 0);
8622 tw32(HOSTCC_TXMAX_FRAMES, 0);
8623 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
a489b6d9
MC		 8624
8625 for (; i < tp->txq_cnt; i++) {
8626 u32 reg;
8627
8628 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
8629 tw32(reg, ec->tx_coalesce_usecs);
8630 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
8631 tw32(reg, ec->tx_max_coalesced_frames);
8632 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
8633 tw32(reg, ec->tx_max_coalesced_frames_irq);
8634 }
19cfaecc 8635 }
b6080e12 8636
a489b6d9
MC		 8637 for (; i < tp->irq_max - 1; i++) {
8638 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
8639 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
8640 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8641 }
8642}
8643
8644static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
8645{
8646 int i = 0;
8647 u32 limit = tp->rxq_cnt;
8648
63c3a66f 8649 if (!tg3_flag(tp, ENABLE_RSS)) {
19cfaecc
MC		 8650 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
8651 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
8652 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
a489b6d9 8653 limit--;
19cfaecc 8654 } else {
b6080e12
MC		 8655 tw32(HOSTCC_RXCOL_TICKS, 0);
8656 tw32(HOSTCC_RXMAX_FRAMES, 0);
8657 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 8658 }
b6080e12 8659
a489b6d9 8660 for (; i < limit; i++) {
b6080e12
MC		 8661 u32 reg;
8662
8663 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
8664 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 8665 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
8666 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 8667 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
8668 tw32(reg, ec->rx_max_coalesced_frames_irq);
b6080e12
MC		 8669 }
8670
8671 for (; i < tp->irq_max - 1; i++) {
8672 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 8673 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 8674 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
a489b6d9
MC		 8675 }
8676}
19cfaecc 8677
a489b6d9
MC		 8678static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
8679{
8680 tg3_coal_tx_init(tp, ec);
8681 tg3_coal_rx_init(tp, ec);
8682
8683 if (!tg3_flag(tp, 5705_PLUS)) {
8684 u32 val = ec->stats_block_coalesce_usecs;
8685
8686 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
8687 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
8688
f4a46d1f 8689 if (!tp->link_up)
a489b6d9
MC		 8690 val = 0;
8691
8692 tw32(HOSTCC_STAT_COAL_TICKS, val);
b6080e12 8693 }
15f9850d 8694}
1da177e4 8695
2d31ecaf
MC		 8696/* tp->lock is held. */
8697static void tg3_rings_reset(struct tg3 *tp)
8698{
8699 int i;
f77a6a8e 8700 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 8701 struct tg3_napi *tnapi = &tp->napi[0];
8702
8703 /* Disable all transmit rings but the first. */
63c3a66f 8704 if (!tg3_flag(tp, 5705_PLUS))
2d31ecaf 8705 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
63c3a66f 8706 else if (tg3_flag(tp, 5717_PLUS))
3d37728b 8707 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
c65a17f4
MC		 8708 else if (tg3_flag(tp, 57765_CLASS) ||
8709 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762)
b703df6f 8710 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
2d31ecaf
MC		 8711 else
8712 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8713
8714 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8715 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
8716 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
8717 BDINFO_FLAGS_DISABLED);
8718
8719
8720 /* Disable all receive return rings but the first. */
63c3a66f 8721 if (tg3_flag(tp, 5717_PLUS))
f6eb9b1f 8722 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
63c3a66f 8723 else if (!tg3_flag(tp, 5705_PLUS))
2d31ecaf 8724 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
b703df6f 8725 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
c65a17f4 8726 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762 ||
55086ad9 8727 tg3_flag(tp, 57765_CLASS))
2d31ecaf
MC		 8728 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
8729 else
8730 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8731
8732 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8733 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
8734 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
8735 BDINFO_FLAGS_DISABLED);
8736
8737 /* Disable interrupts */
8738 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
0e6cf6a9
MC		 8739 tp->napi[0].chk_msi_cnt = 0;
8740 tp->napi[0].last_rx_cons = 0;
8741 tp->napi[0].last_tx_cons = 0;
2d31ecaf
MC		 8742
8743 /* Zero mailbox registers. */
63c3a66f 8744 if (tg3_flag(tp, SUPPORT_MSIX)) {
6fd45cb8 8745 for (i = 1; i < tp->irq_max; i++) {
f77a6a8e
MC		 8746 tp->napi[i].tx_prod = 0;
8747 tp->napi[i].tx_cons = 0;
63c3a66f 8748 if (tg3_flag(tp, ENABLE_TSS))
c2353a32 8749 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 8750 tw32_rx_mbox(tp->napi[i].consmbox, 0);
8751 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7f230735 8752 tp->napi[i].chk_msi_cnt = 0;
0e6cf6a9
MC		 8753 tp->napi[i].last_rx_cons = 0;
8754 tp->napi[i].last_tx_cons = 0;
f77a6a8e 8755 }
63c3a66f 8756 if (!tg3_flag(tp, ENABLE_TSS))
c2353a32 8757 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 8758 } else {
8759 tp->napi[0].tx_prod = 0;
8760 tp->napi[0].tx_cons = 0;
8761 tw32_mailbox(tp->napi[0].prodmbox, 0);
8762 tw32_rx_mbox(tp->napi[0].consmbox, 0);
8763 }
2d31ecaf
MC		 8764
8765 /* Make sure the NIC-based send BD rings are disabled. */
63c3a66f 8766 if (!tg3_flag(tp, 5705_PLUS)) {
2d31ecaf
MC		 8767 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
8768 for (i = 0; i < 16; i++)
8769 tw32_tx_mbox(mbox + i * 8, 0);
8770 }
8771
8772 txrcb = NIC_SRAM_SEND_RCB;
8773 rxrcb = NIC_SRAM_RCV_RET_RCB;
8774
8775 /* Clear status block in ram. */
8776 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8777
8778 /* Set status block DMA address */
8779 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8780 ((u64) tnapi->status_mapping >> 32));
8781 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8782 ((u64) tnapi->status_mapping & 0xffffffff));
8783
f77a6a8e
MC		 8784 if (tnapi->tx_ring) {
8785 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8786 (TG3_TX_RING_SIZE <<
8787 BDINFO_FLAGS_MAXLEN_SHIFT),
8788 NIC_SRAM_TX_BUFFER_DESC);
8789 txrcb += TG3_BDINFO_SIZE;
8790 }
8791
8792 if (tnapi->rx_rcb) {
8793 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7cb32cf2
MC		 8794 (tp->rx_ret_ring_mask + 1) <<
8795 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
f77a6a8e
MC		 8796 rxrcb += TG3_BDINFO_SIZE;
8797 }
8798
8799 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 8800
f77a6a8e
MC		 8801 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
8802 u64 mapping = (u64)tnapi->status_mapping;
8803 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
8804 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
8805
8806 /* Clear status block in ram. */
8807 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8808
19cfaecc
MC		 8809 if (tnapi->tx_ring) {
8810 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8811 (TG3_TX_RING_SIZE <<
8812 BDINFO_FLAGS_MAXLEN_SHIFT),
8813 NIC_SRAM_TX_BUFFER_DESC);
8814 txrcb += TG3_BDINFO_SIZE;
8815 }
f77a6a8e
MC		 8816
8817 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7cb32cf2 8818 ((tp->rx_ret_ring_mask + 1) <<
f77a6a8e
MC		 8819 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
8820
8821 stblk += 8;
f77a6a8e
MC		 8822 rxrcb += TG3_BDINFO_SIZE;
8823 }
2d31ecaf
MC		 8824}
8825
eb07a940
MC		 8826static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
8827{
8828 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
8829
63c3a66f
JP		 8830 if (!tg3_flag(tp, 5750_PLUS) ||
8831 tg3_flag(tp, 5780_CLASS) ||
eb07a940 8832 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
513aa6ea
MC		 8833 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
8834 tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 8835 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
8836 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8837 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8838 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
8839 else
8840 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
8841
8842 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
8843 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
8844
8845 val = min(nic_rep_thresh, host_rep_thresh);
8846 tw32(RCVBDI_STD_THRESH, val);
8847
63c3a66f 8848 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 8849 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
8850
63c3a66f 8851 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
eb07a940
MC		 8852 return;
8853
513aa6ea 8854 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
eb07a940
MC		 8855
8856 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
8857
8858 val = min(bdcache_maxcnt / 2, host_rep_thresh);
8859 tw32(RCVBDI_JUMBO_THRESH, val);
8860
63c3a66f 8861 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 8862 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
8863}
8864
ccd5ba9d
MC		 8865static inline u32 calc_crc(unsigned char *buf, int len)
8866{
8867 u32 reg;
8868 u32 tmp;
8869 int j, k;
8870
8871 reg = 0xffffffff;
8872
8873 for (j = 0; j < len; j++) {
8874 reg ^= buf[j];
8875
8876 for (k = 0; k < 8; k++) {
8877 tmp = reg & 0x01;
8878
8879 reg >>= 1;
8880
8881 if (tmp)
8882 reg ^= 0xedb88320;
8883 }
8884 }
8885
8886 return ~reg;
8887}
8888
8889static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8890{
8891 /* accept or reject all multicast frames */
8892 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8893 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8894 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8895 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8896}
8897
8898static void __tg3_set_rx_mode(struct net_device *dev)
8899{
8900 struct tg3 *tp = netdev_priv(dev);
8901 u32 rx_mode;
8902
8903 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8904 RX_MODE_KEEP_VLAN_TAG);
8905
8906#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
8907 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8908 * flag clear.
8909 */
8910 if (!tg3_flag(tp, ENABLE_ASF))
8911 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8912#endif
8913
8914 if (dev->flags & IFF_PROMISC) {
8915 /* Promiscuous mode. */
8916 rx_mode |= RX_MODE_PROMISC;
8917 } else if (dev->flags & IFF_ALLMULTI) {
8918 /* Accept all multicast. */
8919 tg3_set_multi(tp, 1);
8920 } else if (netdev_mc_empty(dev)) {
8921 /* Reject all multicast. */
8922 tg3_set_multi(tp, 0);
8923 } else {
8924 /* Accept one or more multicast(s). */
8925 struct netdev_hw_addr *ha;
8926 u32 mc_filter[4] = { 0, };
8927 u32 regidx;
8928 u32 bit;
8929 u32 crc;
8930
8931 netdev_for_each_mc_addr(ha, dev) {
8932 crc = calc_crc(ha->addr, ETH_ALEN);
8933 bit = ~crc & 0x7f;
8934 regidx = (bit & 0x60) >> 5;
8935 bit &= 0x1f;
8936 mc_filter[regidx] |= (1 << bit);
8937 }
8938
8939 tw32(MAC_HASH_REG_0, mc_filter[0]);
8940 tw32(MAC_HASH_REG_1, mc_filter[1]);
8941 tw32(MAC_HASH_REG_2, mc_filter[2]);
8942 tw32(MAC_HASH_REG_3, mc_filter[3]);
8943 }
8944
8945 if (rx_mode != tp->rx_mode) {
8946 tp->rx_mode = rx_mode;
8947 tw32_f(MAC_RX_MODE, rx_mode);
8948 udelay(10);
8949 }
8950}
8951
9102426a 8952static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
90415477
MC		 8953{
8954 int i;
8955
8956 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9102426a 8957 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
90415477
MC		 8958}
8959
8960static void tg3_rss_check_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 8961{
8962 int i;
8963
8964 if (!tg3_flag(tp, SUPPORT_MSIX))
8965 return;
8966
0b3ba055 8967 if (tp->rxq_cnt == 1) {
bcebcc46 8968 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
90415477
MC		 8969 return;
8970 }
8971
8972 /* Validate table against current IRQ count */
8973 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
0b3ba055 8974 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
90415477
MC		 8975 break;
8976 }
8977
8978 if (i != TG3_RSS_INDIR_TBL_SIZE)
9102426a 8979 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
bcebcc46
MC		 8980}
8981
90415477 8982static void tg3_rss_write_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 8983{
8984 int i = 0;
8985 u32 reg = MAC_RSS_INDIR_TBL_0;
8986
8987 while (i < TG3_RSS_INDIR_TBL_SIZE) {
8988 u32 val = tp->rss_ind_tbl[i];
8989 i++;
8990 for (; i % 8; i++) {
8991 val <<= 4;
8992 val |= tp->rss_ind_tbl[i];
8993 }
8994 tw32(reg, val);
8995 reg += 4;
8996 }
8997}
8998
1da177e4 8999/* tp->lock is held. */
8e7a22e3 9000static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 9001{
9002 u32 val, rdmac_mode;
9003 int i, err, limit;
8fea32b9 9004 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
1da177e4
LT		 9005
9006 tg3_disable_ints(tp);
9007
9008 tg3_stop_fw(tp);
9009
9010 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9011
63c3a66f 9012 if (tg3_flag(tp, INIT_COMPLETE))
e6de8ad1 9013 tg3_abort_hw(tp, 1);
1da177e4 9014
699c0193
MC		 9015 /* Enable MAC control of LPI */
9016 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
c65a17f4
MC		 9017 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
9018 TG3_CPMU_EEE_LNKIDL_UART_IDL;
9019 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
9020 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
9021
9022 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
699c0193
MC		 9023
9024 tw32_f(TG3_CPMU_EEE_CTRL,
9025 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
9026
a386b901
MC		 9027 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
9028 TG3_CPMU_EEEMD_LPI_IN_TX |
9029 TG3_CPMU_EEEMD_LPI_IN_RX |
9030 TG3_CPMU_EEEMD_EEE_ENABLE;
9031
9032 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
9033 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
9034
63c3a66f 9035 if (tg3_flag(tp, ENABLE_APE))
a386b901
MC		 9036 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
9037
9038 tw32_f(TG3_CPMU_EEE_MODE, val);
9039
9040 tw32_f(TG3_CPMU_EEE_DBTMR1,
9041 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
9042 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
9043
9044 tw32_f(TG3_CPMU_EEE_DBTMR2,
d7f2ab20 9045 TG3_CPMU_DBTMR2_APE_TX_2047US |
a386b901 9046 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
699c0193
MC		 9047 }
9048
603f1173 9049 if (reset_phy)
d4d2c558
MC		 9050 tg3_phy_reset(tp);
9051
1da177e4
LT		 9052 err = tg3_chip_reset(tp);
9053 if (err)
9054 return err;
9055
9056 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9057
bcb37f6c 9058 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 9059 val = tr32(TG3_CPMU_CTRL);
9060 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9061 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 9062
9063 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9064 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9065 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9066 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9067
9068 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9069 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9070 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9071 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9072
9073 val = tr32(TG3_CPMU_HST_ACC);
9074 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9075 val |= CPMU_HST_ACC_MACCLK_6_25;
9076 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 9077 }
9078
33466d93
MC		 9079 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
9080 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9081 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9082 PCIE_PWR_MGMT_L1_THRESH_4MS;
9083 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 9084
9085 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9086 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9087
9088 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 9089
f40386c8
MC		 9090 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9091 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 9092 }
9093
63c3a66f 9094 if (tg3_flag(tp, L1PLLPD_EN)) {
614b0590
MC		 9095 u32 grc_mode = tr32(GRC_MODE);
9096
9097 /* Access the lower 1K of PL PCIE block registers. */
9098 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9099 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9100
9101 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9102 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9103 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9104
9105 tw32(GRC_MODE, grc_mode);
9106 }
9107
55086ad9 9108 if (tg3_flag(tp, 57765_CLASS)) {
5093eedc
MC		 9109 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
9110 u32 grc_mode = tr32(GRC_MODE);
cea46462 9111
5093eedc
MC		 9112 /* Access the lower 1K of PL PCIE block registers. */
9113 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9114 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
cea46462 9115
5093eedc
MC		 9116 val = tr32(TG3_PCIE_TLDLPL_PORT +
9117 TG3_PCIE_PL_LO_PHYCTL5);
9118 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9119 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
cea46462 9120
5093eedc
MC		 9121 tw32(GRC_MODE, grc_mode);
9122 }
a977dbe8 9123
1ff30a59
MC		 9124 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
9125 u32 grc_mode = tr32(GRC_MODE);
9126
9127 /* Access the lower 1K of DL PCIE block registers. */
9128 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9129 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9130
9131 val = tr32(TG3_PCIE_TLDLPL_PORT +
9132 TG3_PCIE_DL_LO_FTSMAX);
9133 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9134 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9135 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9136
9137 tw32(GRC_MODE, grc_mode);
9138 }
9139
a977dbe8
MC		 9140 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9141 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9142 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9143 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
cea46462
MC		 9144 }
9145
1da177e4
LT		 9146 /* This works around an issue with Athlon chipsets on
9147 * B3 tigon3 silicon. This bit has no effect on any
9148 * other revision. But do not set this on PCI Express
795d01c5 9149 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 9150 */
63c3a66f
JP		 9151 if (!tg3_flag(tp, CPMU_PRESENT)) {
9152 if (!tg3_flag(tp, PCI_EXPRESS))
795d01c5
MC		 9153 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9154 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9155 }
1da177e4
LT		 9156
9157 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
63c3a66f 9158 tg3_flag(tp, PCIX_MODE)) {
1da177e4
LT		 9159 val = tr32(TG3PCI_PCISTATE);
9160 val |= PCISTATE_RETRY_SAME_DMA;
9161 tw32(TG3PCI_PCISTATE, val);
9162 }
9163
63c3a66f 9164 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 9165 /* Allow reads and writes to the
9166 * APE register and memory space.
9167 */
9168 val = tr32(TG3PCI_PCISTATE);
9169 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 9170 PCISTATE_ALLOW_APE_SHMEM_WR |
9171 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 9172 tw32(TG3PCI_PCISTATE, val);
9173 }
9174
1da177e4
LT		 9175 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
9176 /* Enable some hw fixes. */
9177 val = tr32(TG3PCI_MSI_DATA);
9178 val |= (1 << 26) | (1 << 28) | (1 << 29);
9179 tw32(TG3PCI_MSI_DATA, val);
9180 }
9181
9182 /* Descriptor ring init may make accesses to the
9183 * NIC SRAM area to setup the TX descriptors, so we
9184 * can only do this after the hardware has been
9185 * successfully reset.
9186 */
32d8c572
MC		 9187 err = tg3_init_rings(tp);
9188 if (err)
9189 return err;
1da177e4 9190
63c3a66f 9191 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 9192 val = tr32(TG3PCI_DMA_RW_CTRL) &
9193 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
1a319025
MC		 9194 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
9195 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
55086ad9 9196 if (!tg3_flag(tp, 57765_CLASS) &&
c65a17f4
MC		 9197 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9198 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5762)
0aebff48 9199 val |= DMA_RWCTRL_TAGGED_STAT_WA;
cbf9ca6c
MC		 9200 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
9201 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
9202 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 9203 /* This value is determined during the probe time DMA
9204 * engine test, tg3_test_dma.
9205 */
9206 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9207 }
1da177e4
LT		 9208
9209 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
9210 GRC_MODE_4X_NIC_SEND_RINGS |
9211 GRC_MODE_NO_TX_PHDR_CSUM |
9212 GRC_MODE_NO_RX_PHDR_CSUM);
9213 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 9214
9215 /* Pseudo-header checksum is done by hardware logic and not
9216 * the offload processers, so make the chip do the pseudo-
9217 * header checksums on receive. For transmit it is more
9218 * convenient to do the pseudo-header checksum in software
9219 * as Linux does that on transmit for us in all cases.
9220 */
9221 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4 9222
fb4ce8ad
MC		 9223 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
9224 if (tp->rxptpctl)
9225 tw32(TG3_RX_PTP_CTL,
9226 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
9227
9228 if (tg3_flag(tp, PTP_CAPABLE))
9229 val |= GRC_MODE_TIME_SYNC_ENABLE;
9230
9231 tw32(GRC_MODE, tp->grc_mode | val);
1da177e4
LT		 9232
9233 /* Setup the timer prescalar register. Clock is always 66Mhz. */
9234 val = tr32(GRC_MISC_CFG);
9235 val &= ~0xff;
9236 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
9237 tw32(GRC_MISC_CFG, val);
9238
9239 /* Initialize MBUF/DESC pool. */
63c3a66f 9240 if (tg3_flag(tp, 5750_PLUS)) {
1da177e4
LT		 9241 /* Do nothing. */
9242 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
9243 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
9244 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
9245 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
9246 else
9247 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
9248 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
9249 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
63c3a66f 9250 } else if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 9251 int fw_len;
9252
077f849d 9253 fw_len = tp->fw_len;
1da177e4
LT		 9254 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
9255 tw32(BUFMGR_MB_POOL_ADDR,
9256 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
9257 tw32(BUFMGR_MB_POOL_SIZE,
9258 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
9259 }
1da177e4 9260
0f893dc6 9261 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 9262 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9263 tp->bufmgr_config.mbuf_read_dma_low_water);
9264 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9265 tp->bufmgr_config.mbuf_mac_rx_low_water);
9266 tw32(BUFMGR_MB_HIGH_WATER,
9267 tp->bufmgr_config.mbuf_high_water);
9268 } else {
9269 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9270 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
9271 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9272 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
9273 tw32(BUFMGR_MB_HIGH_WATER,
9274 tp->bufmgr_config.mbuf_high_water_jumbo);
9275 }
9276 tw32(BUFMGR_DMA_LOW_WATER,
9277 tp->bufmgr_config.dma_low_water);
9278 tw32(BUFMGR_DMA_HIGH_WATER,
9279 tp->bufmgr_config.dma_high_water);
9280
d309a46e
MC		 9281 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
9282 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
9283 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
4d958473
MC		 9284 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
9285 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
9286 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
9287 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
d309a46e 9288 tw32(BUFMGR_MODE, val);
1da177e4
LT		 9289 for (i = 0; i < 2000; i++) {
9290 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
9291 break;
9292 udelay(10);
9293 }
9294 if (i >= 2000) {
05dbe005 9295 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 9296 return -ENODEV;
9297 }
9298
eb07a940
MC		 9299 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
9300 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
b5d3772c 9301
eb07a940 9302 tg3_setup_rxbd_thresholds(tp);
1da177e4
LT		 9303
9304 /* Initialize TG3_BDINFO's at:
9305 * RCVDBDI_STD_BD: standard eth size rx ring
9306 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
9307 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
9308 *
9309 * like so:
9310 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
9311 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
9312 * ring attribute flags
9313 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
9314 *
9315 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
9316 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
9317 *
9318 * The size of each ring is fixed in the firmware, but the location is
9319 * configurable.
9320 */
9321 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 9322 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 9323 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 9324 ((u64) tpr->rx_std_mapping & 0xffffffff));
63c3a66f 9325 if (!tg3_flag(tp, 5717_PLUS))
87668d35
MC		 9326 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
9327 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 9328
fdb72b38 9329 /* Disable the mini ring */
63c3a66f 9330 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 9331 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
9332 BDINFO_FLAGS_DISABLED);
9333
fdb72b38
MC		 9334 /* Program the jumbo buffer descriptor ring control
9335 * blocks on those devices that have them.
9336 */
a0512944 9337 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
63c3a66f 9338 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
1da177e4 9339
63c3a66f 9340 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
1da177e4 9341 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 9342 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 9343 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 9344 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
de9f5230
MC		 9345 val = TG3_RX_JMB_RING_SIZE(tp) <<
9346 BDINFO_FLAGS_MAXLEN_SHIFT;
1da177e4 9347 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
de9f5230 9348 val | BDINFO_FLAGS_USE_EXT_RECV);
63c3a66f 9349 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
c65a17f4
MC		 9350 tg3_flag(tp, 57765_CLASS) ||
9351 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762)
87668d35
MC		 9352 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
9353 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 9354 } else {
9355 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
9356 BDINFO_FLAGS_DISABLED);
9357 }
9358
63c3a66f 9359 if (tg3_flag(tp, 57765_PLUS)) {
fa6b2aae 9360 val = TG3_RX_STD_RING_SIZE(tp);
7cb32cf2
MC		 9361 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
9362 val |= (TG3_RX_STD_DMA_SZ << 2);
9363 } else
04380d40 9364 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38 9365 } else
de9f5230 9366 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 9367
9368 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 9369
411da640 9370 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 9371 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 9372
63c3a66f
JP		 9373 tpr->rx_jmb_prod_idx =
9374 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
66711e66 9375 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 9376
2d31ecaf
MC		 9377 tg3_rings_reset(tp);
9378
1da177e4 9379 /* Initialize MAC address and backoff seed. */
986e0aeb 9380 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 9381
9382 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 9383 tw32(MAC_RX_MTU_SIZE,
9384 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 9385
9386 /* The slot time is changed by tg3_setup_phy if we
9387 * run at gigabit with half duplex.
9388 */
f2096f94
MC		 9389 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
9390 (6 << TX_LENGTHS_IPG_SHIFT) |
9391 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
9392
c65a17f4
MC		 9393 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
9394 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762)
f2096f94
MC		 9395 val |= tr32(MAC_TX_LENGTHS) &
9396 (TX_LENGTHS_JMB_FRM_LEN_MSK |
9397 TX_LENGTHS_CNT_DWN_VAL_MSK);
9398
9399 tw32(MAC_TX_LENGTHS, val);
1da177e4
LT		 9400
9401 /* Receive rules. */
9402 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
9403 tw32(RCVLPC_CONFIG, 0x0181);
9404
9405 /* Calculate RDMAC_MODE setting early, we need it to determine
9406 * the RCVLPC_STATE_ENABLE mask.
9407 */
9408 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
9409 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
9410 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
9411 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
9412 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 9413
deabaac8 9414 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
0339e4e3
MC		 9415 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
9416
57e6983c 9417 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 9418 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9419 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 9420 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
9421 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
9422 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
9423
c5908939
MC		 9424 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9425 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
63c3a66f 9426 if (tg3_flag(tp, TSO_CAPABLE) &&
c13e3713 9427 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 9428 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
9429 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 9430 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 9431 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
9432 }
9433 }
9434
63c3a66f 9435 if (tg3_flag(tp, PCI_EXPRESS))
85e94ced
MC		 9436 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
9437
63c3a66f
JP		 9438 if (tg3_flag(tp, HW_TSO_1) ||
9439 tg3_flag(tp, HW_TSO_2) ||
9440 tg3_flag(tp, HW_TSO_3))
027455ad
MC		 9441 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
9442
108a6c16 9443 if (tg3_flag(tp, 57765_PLUS) ||
e849cdc3 9444 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
027455ad
MC		 9445 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9446 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4 9447
c65a17f4
MC		 9448 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
9449 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762)
f2096f94
MC		 9450 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
9451
41a8a7ee
MC		 9452 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9453 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9454 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9455 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
63c3a66f 9456 tg3_flag(tp, 57765_PLUS)) {
c65a17f4
MC		 9457 u32 tgtreg;
9458
9459 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762)
9460 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
9461 else
9462 tgtreg = TG3_RDMA_RSRVCTRL_REG;
9463
9464 val = tr32(tgtreg);
9465 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
9466 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) {
b4495ed8
MC		 9467 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
9468 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
9469 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
9470 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
9471 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
9472 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
b75cc0e4 9473 }
c65a17f4 9474 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
41a8a7ee
MC		 9475 }
9476
d78b59f5 9477 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
c65a17f4
MC		 9478 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
9479 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) {
9480 u32 tgtreg;
9481
9482 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762)
9483 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
9484 else
9485 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
9486
9487 val = tr32(tgtreg);
9488 tw32(tgtreg, val |
d309a46e
MC		 9489 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
9490 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
9491 }
9492
1da177e4 9493 /* Receive/send statistics. */
63c3a66f 9494 if (tg3_flag(tp, 5750_PLUS)) {
1661394e
MC		 9495 val = tr32(RCVLPC_STATS_ENABLE);
9496 val &= ~RCVLPC_STATSENAB_DACK_FIX;
9497 tw32(RCVLPC_STATS_ENABLE, val);
9498 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
63c3a66f 9499 tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 9500 val = tr32(RCVLPC_STATS_ENABLE);
9501 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
9502 tw32(RCVLPC_STATS_ENABLE, val);
9503 } else {
9504 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
9505 }
9506 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
9507 tw32(SNDDATAI_STATSENAB, 0xffffff);
9508 tw32(SNDDATAI_STATSCTRL,
9509 (SNDDATAI_SCTRL_ENABLE |
9510 SNDDATAI_SCTRL_FASTUPD));
9511
9512 /* Setup host coalescing engine. */
9513 tw32(HOSTCC_MODE, 0);
9514 for (i = 0; i < 2000; i++) {
9515 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
9516 break;
9517 udelay(10);
9518 }
9519
d244c892 9520 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 9521
63c3a66f 9522 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 9523 /* Status/statistics block address. See tg3_timer,
9524 * the tg3_periodic_fetch_stats call there, and
9525 * tg3_get_stats to see how this works for 5705/5750 chips.
9526 */
1da177e4
LT		 9527 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9528 ((u64) tp->stats_mapping >> 32));
9529 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9530 ((u64) tp->stats_mapping & 0xffffffff));
9531 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 9532
1da177e4 9533 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 9534
9535 /* Clear statistics and status block memory areas */
9536 for (i = NIC_SRAM_STATS_BLK;
9537 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
9538 i += sizeof(u32)) {
9539 tg3_write_mem(tp, i, 0);
9540 udelay(40);
9541 }
1da177e4
LT		 9542 }
9543
9544 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
9545
9546 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
9547 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
63c3a66f 9548 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 9549 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
9550
f07e9af3
MC		 9551 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9552 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c94e3941
MC		 9553 /* reset to prevent losing 1st rx packet intermittently */
9554 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9555 udelay(10);
9556 }
9557
3bda1258 9558 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9e975cc2
MC		 9559 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
9560 MAC_MODE_FHDE_ENABLE;
9561 if (tg3_flag(tp, ENABLE_APE))
9562 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
63c3a66f 9563 if (!tg3_flag(tp, 5705_PLUS) &&
f07e9af3 9564 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
e8f3f6ca
MC		 9565 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
9566 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 9567 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
9568 udelay(40);
9569
314fba34 9570 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
63c3a66f 9571 * If TG3_FLAG_IS_NIC is zero, we should read the
314fba34
MC		 9572 * register to preserve the GPIO settings for LOMs. The GPIOs,
9573 * whether used as inputs or outputs, are set by boot code after
9574 * reset.
9575 */
63c3a66f 9576 if (!tg3_flag(tp, IS_NIC)) {
314fba34
MC		 9577 u32 gpio_mask;
9578
9d26e213
MC		 9579 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
9580 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
9581 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 9582
9583 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9584 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
9585 GRC_LCLCTRL_GPIO_OUTPUT3;
9586
af36e6b6
MC		 9587 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9588 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
9589
aaf84465 9590 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 9591 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
9592
9593 /* GPIO1 must be driven high for eeprom write protect */
63c3a66f 9594 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9d26e213
MC		 9595 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9596 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 9597 }
1da177e4
LT		 9598 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9599 udelay(100);
9600
c3b5003b 9601 if (tg3_flag(tp, USING_MSIX)) {
baf8a94a 9602 val = tr32(MSGINT_MODE);
c3b5003b
MC		 9603 val |= MSGINT_MODE_ENABLE;
9604 if (tp->irq_cnt > 1)
9605 val |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 9606 if (!tg3_flag(tp, 1SHOT_MSI))
9607 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
baf8a94a
MC		 9608 tw32(MSGINT_MODE, val);
9609 }
9610
63c3a66f 9611 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 9612 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
9613 udelay(40);
9614 }
9615
9616 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
9617 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
9618 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
9619 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
9620 WDMAC_MODE_LNGREAD_ENAB);
9621
c5908939
MC		 9622 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9623 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
63c3a66f 9624 if (tg3_flag(tp, TSO_CAPABLE) &&
1da177e4
LT		 9625 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
9626 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
9627 /* nothing */
9628 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 9629 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 9630 val |= WDMAC_MODE_RX_ACCEL;
9631 }
9632 }
9633
d9ab5ad1 9634 /* Enable host coalescing bug fix */
63c3a66f 9635 if (tg3_flag(tp, 5755_PLUS))
f51f3562 9636 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 9637
788a035e
MC		 9638 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9639 val |= WDMAC_MODE_BURST_ALL_DATA;
9640
1da177e4
LT		 9641 tw32_f(WDMAC_MODE, val);
9642 udelay(40);
9643
63c3a66f 9644 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 9645 u16 pcix_cmd;
9646
9647 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
9648 &pcix_cmd);
1da177e4 9649 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 9650 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
9651 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 9652 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 9653 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
9654 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 9655 }
9974a356
MC		 9656 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
9657 pcix_cmd);
1da177e4
LT		 9658 }
9659
9660 tw32_f(RDMAC_MODE, rdmac_mode);
9661 udelay(40);
9662
091f0ea3
MC		 9663 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
9664 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
9665 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
9666 break;
9667 }
9668 if (i < TG3_NUM_RDMA_CHANNELS) {
9669 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9670 val |= TG3_LSO_RD_DMA_TX_LENGTH_WA;
9671 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9672 tg3_flag_set(tp, 5719_RDMA_BUG);
9673 }
9674 }
9675
1da177e4 9676 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
63c3a66f 9677 if (!tg3_flag(tp, 5705_PLUS))
1da177e4 9678 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 9679
9680 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
9681 tw32(SNDDATAC_MODE,
9682 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
9683 else
9684 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
9685
1da177e4
LT		 9686 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
9687 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7cb32cf2 9688 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
63c3a66f 9689 if (tg3_flag(tp, LRG_PROD_RING_CAP))
7cb32cf2
MC		 9690 val |= RCVDBDI_MODE_LRG_RING_SZ;
9691 tw32(RCVDBDI_MODE, val);
1da177e4 9692 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
63c3a66f
JP		 9693 if (tg3_flag(tp, HW_TSO_1) ||
9694 tg3_flag(tp, HW_TSO_2) ||
9695 tg3_flag(tp, HW_TSO_3))
1da177e4 9696 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 9697 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
63c3a66f 9698 if (tg3_flag(tp, ENABLE_TSS))
baf8a94a
MC		 9699 val |= SNDBDI_MODE_MULTI_TXQ_EN;
9700 tw32(SNDBDI_MODE, val);
1da177e4
LT		 9701 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
9702
9703 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9704 err = tg3_load_5701_a0_firmware_fix(tp);
9705 if (err)
9706 return err;
9707 }
9708
63c3a66f 9709 if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 9710 err = tg3_load_tso_firmware(tp);
9711 if (err)
9712 return err;
9713 }
1da177e4
LT		 9714
9715 tp->tx_mode = TX_MODE_ENABLE;
f2096f94 9716
63c3a66f 9717 if (tg3_flag(tp, 5755_PLUS) ||
b1d05210
MC		 9718 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9719 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
f2096f94 9720
c65a17f4
MC		 9721 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
9722 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) {
f2096f94
MC		 9723 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
9724 tp->tx_mode &= ~val;
9725 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
9726 }
9727
1da177e4
LT		 9728 tw32_f(MAC_TX_MODE, tp->tx_mode);
9729 udelay(100);
9730
63c3a66f 9731 if (tg3_flag(tp, ENABLE_RSS)) {
bcebcc46 9732 tg3_rss_write_indir_tbl(tp);
baf8a94a
MC		 9733
9734 /* Setup the "secret" hash key. */
9735 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
9736 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
9737 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
9738 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
9739 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
9740 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
9741 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
9742 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
9743 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
9744 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
9745 }
9746
1da177e4 9747 tp->rx_mode = RX_MODE_ENABLE;
63c3a66f 9748 if (tg3_flag(tp, 5755_PLUS))
af36e6b6
MC		 9749 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
9750
63c3a66f 9751 if (tg3_flag(tp, ENABLE_RSS))
baf8a94a
MC		 9752 tp->rx_mode |= RX_MODE_RSS_ENABLE |
9753 RX_MODE_RSS_ITBL_HASH_BITS_7 |
9754 RX_MODE_RSS_IPV6_HASH_EN |
9755 RX_MODE_RSS_TCP_IPV6_HASH_EN |
9756 RX_MODE_RSS_IPV4_HASH_EN |
9757 RX_MODE_RSS_TCP_IPV4_HASH_EN;
9758
1da177e4
LT		 9759 tw32_f(MAC_RX_MODE, tp->rx_mode);
9760 udelay(10);
9761
1da177e4
LT		 9762 tw32(MAC_LED_CTRL, tp->led_ctrl);
9763
9764 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
f07e9af3 9765 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
1da177e4
LT		 9766 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9767 udelay(10);
9768 }
9769 tw32_f(MAC_RX_MODE, tp->rx_mode);
9770 udelay(10);
9771
f07e9af3 9772 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
1da177e4 9773 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
f07e9af3 9774 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
1da177e4
LT		 9775 /* Set drive transmission level to 1.2V */
9776 /* only if the signal pre-emphasis bit is not set */
9777 val = tr32(MAC_SERDES_CFG);
9778 val &= 0xfffff000;
9779 val |= 0x880;
9780 tw32(MAC_SERDES_CFG, val);
9781 }
9782 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
9783 tw32(MAC_SERDES_CFG, 0x616000);
9784 }
9785
9786 /* Prevent chip from dropping frames when flow control
9787 * is enabled.
9788 */
55086ad9 9789 if (tg3_flag(tp, 57765_CLASS))
666bc831
MC		 9790 val = 1;
9791 else
9792 val = 2;
9793 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4
LT		 9794
9795 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
f07e9af3 9796 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
1da177e4 9797 /* Use hardware link auto-negotiation */
63c3a66f 9798 tg3_flag_set(tp, HW_AUTONEG);
1da177e4
LT		 9799 }
9800
f07e9af3 9801 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
6ff6f81d 9802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
d4d2c558
MC		 9803 u32 tmp;
9804
9805 tmp = tr32(SERDES_RX_CTRL);
9806 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
9807 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
9808 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
9809 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9810 }
9811
63c3a66f 9812 if (!tg3_flag(tp, USE_PHYLIB)) {
c6700ce2 9813 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
80096068 9814 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1da177e4 9815
dd477003
MC		 9816 err = tg3_setup_phy(tp, 0);
9817 if (err)
9818 return err;
1da177e4 9819
f07e9af3
MC		 9820 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9821 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
dd477003
MC		 9822 u32 tmp;
9823
9824 /* Clear CRC stats. */
9825 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
9826 tg3_writephy(tp, MII_TG3_TEST1,
9827 tmp | MII_TG3_TEST1_CRC_EN);
f08aa1a8 9828 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
dd477003 9829 }
1da177e4
LT		 9830 }
9831 }
9832
9833 __tg3_set_rx_mode(tp->dev);
9834
9835 /* Initialize receive rules. */
9836 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
9837 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
9838 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
9839 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
9840
63c3a66f 9841 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
1da177e4
LT		 9842 limit = 8;
9843 else
9844 limit = 16;
63c3a66f 9845 if (tg3_flag(tp, ENABLE_ASF))
1da177e4
LT		 9846 limit -= 4;
9847 switch (limit) {
9848 case 16:
9849 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
9850 case 15:
9851 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
9852 case 14:
9853 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
9854 case 13:
9855 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
9856 case 12:
9857 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
9858 case 11:
9859 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
9860 case 10:
9861 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
9862 case 9:
9863 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
9864 case 8:
9865 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
9866 case 7:
9867 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
9868 case 6:
9869 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
9870 case 5:
9871 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
9872 case 4:
9873 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
9874 case 3:
9875 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
9876 case 2:
9877 case 1:
9878
9879 default:
9880 break;
855e1111 9881 }
1da177e4 9882
63c3a66f 9883 if (tg3_flag(tp, ENABLE_APE))
9ce768ea
MC		 9884 /* Write our heartbeat update interval to APE. */
9885 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
9886 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 9887
1da177e4
LT		 9888 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
9889
1da177e4
LT		 9890 return 0;
9891}
9892
9893/* Called at device open time to get the chip ready for
9894 * packet processing. Invoked with tp->lock held.
9895 */
8e7a22e3 9896static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 9897{
1da177e4
LT		 9898 tg3_switch_clocks(tp);
9899
9900 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9901
2f751b67 9902 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 9903}
9904
aed93e0b
MC		 9905static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
9906{
9907 int i;
9908
9909 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
9910 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
9911
9912 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
9913 off += len;
9914
9915 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
9916 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
9917 memset(ocir, 0, TG3_OCIR_LEN);
9918 }
9919}
9920
9921/* sysfs attributes for hwmon */
9922static ssize_t tg3_show_temp(struct device *dev,
9923 struct device_attribute *devattr, char *buf)
9924{
9925 struct pci_dev *pdev = to_pci_dev(dev);
9926 struct net_device *netdev = pci_get_drvdata(pdev);
9927 struct tg3 *tp = netdev_priv(netdev);
9928 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
9929 u32 temperature;
9930
9931 spin_lock_bh(&tp->lock);
9932 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
9933 sizeof(temperature));
9934 spin_unlock_bh(&tp->lock);
9935 return sprintf(buf, "%u\n", temperature);
9936}
9937
9938
9939static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
9940 TG3_TEMP_SENSOR_OFFSET);
9941static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
9942 TG3_TEMP_CAUTION_OFFSET);
9943static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
9944 TG3_TEMP_MAX_OFFSET);
9945
9946static struct attribute *tg3_attributes[] = {
9947 &sensor_dev_attr_temp1_input.dev_attr.attr,
9948 &sensor_dev_attr_temp1_crit.dev_attr.attr,
9949 &sensor_dev_attr_temp1_max.dev_attr.attr,
9950 NULL
9951};
9952
9953static const struct attribute_group tg3_group = {
9954 .attrs = tg3_attributes,
9955};
9956
aed93e0b
MC		 9957static void tg3_hwmon_close(struct tg3 *tp)
9958{
aed93e0b
MC		 9959 if (tp->hwmon_dev) {
9960 hwmon_device_unregister(tp->hwmon_dev);
9961 tp->hwmon_dev = NULL;
9962 sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group);
9963 }
aed93e0b
MC		 9964}
9965
9966static void tg3_hwmon_open(struct tg3 *tp)
9967{
aed93e0b
MC		 9968 int i, err;
9969 u32 size = 0;
9970 struct pci_dev *pdev = tp->pdev;
9971 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
9972
9973 tg3_sd_scan_scratchpad(tp, ocirs);
9974
9975 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
9976 if (!ocirs[i].src_data_length)
9977 continue;
9978
9979 size += ocirs[i].src_hdr_length;
9980 size += ocirs[i].src_data_length;
9981 }
9982
9983 if (!size)
9984 return;
9985
9986 /* Register hwmon sysfs hooks */
9987 err = sysfs_create_group(&pdev->dev.kobj, &tg3_group);
9988 if (err) {
9989 dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n");
9990 return;
9991 }
9992
9993 tp->hwmon_dev = hwmon_device_register(&pdev->dev);
9994 if (IS_ERR(tp->hwmon_dev)) {
9995 tp->hwmon_dev = NULL;
9996 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
9997 sysfs_remove_group(&pdev->dev.kobj, &tg3_group);
9998 }
aed93e0b
MC		 9999}
10000
10001
1da177e4
LT		 10002#define TG3_STAT_ADD32(PSTAT, REG) \
10003do { u32 __val = tr32(REG); \
10004 (PSTAT)->low += __val; \
10005 if ((PSTAT)->low < __val) \
10006 (PSTAT)->high += 1; \
10007} while (0)
10008
10009static void tg3_periodic_fetch_stats(struct tg3 *tp)
10010{
10011 struct tg3_hw_stats *sp = tp->hw_stats;
10012
f4a46d1f 10013 if (!tp->link_up)
1da177e4
LT		 10014 return;
10015
10016 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10017 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10018 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10019 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10020 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10021 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10022 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10023 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10024 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10025 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10026 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10027 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10028 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
091f0ea3
MC		 10029 if (unlikely(tg3_flag(tp, 5719_RDMA_BUG) &&
10030 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10031 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10032 u32 val;
10033
10034 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10035 val &= ~TG3_LSO_RD_DMA_TX_LENGTH_WA;
10036 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10037 tg3_flag_clear(tp, 5719_RDMA_BUG);
10038 }
1da177e4
LT		 10039
10040 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10041 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10042 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10043 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10044 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10045 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10046 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10047 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10048 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10049 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10050 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10051 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10052 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10053 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 10054
10055 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
310050fa
MC		 10056 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
10057 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
10058 tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
4d958473
MC		 10059 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10060 } else {
10061 u32 val = tr32(HOSTCC_FLOW_ATTN);
10062 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10063 if (val) {
10064 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10065 sp->rx_discards.low += val;
10066 if (sp->rx_discards.low < val)
10067 sp->rx_discards.high += 1;
10068 }
10069 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10070 }
463d305b 10071 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 10072}
10073
0e6cf6a9
MC		 10074static void tg3_chk_missed_msi(struct tg3 *tp)
10075{
10076 u32 i;
10077
10078 for (i = 0; i < tp->irq_cnt; i++) {
10079 struct tg3_napi *tnapi = &tp->napi[i];
10080
10081 if (tg3_has_work(tnapi)) {
10082 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10083 tnapi->last_tx_cons == tnapi->tx_cons) {
10084 if (tnapi->chk_msi_cnt < 1) {
10085 tnapi->chk_msi_cnt++;
10086 return;
10087 }
7f230735 10088 tg3_msi(0, tnapi);
0e6cf6a9
MC		 10089 }
10090 }
10091 tnapi->chk_msi_cnt = 0;
10092 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10093 tnapi->last_tx_cons = tnapi->tx_cons;
10094 }
10095}
10096
1da177e4
LT		 10097static void tg3_timer(unsigned long __opaque)
10098{
10099 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 10100
5b190624 10101 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
f475f163
MC		 10102 goto restart_timer;
10103
f47c11ee 10104 spin_lock(&tp->lock);
1da177e4 10105
0e6cf6a9 10106 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
55086ad9 10107 tg3_flag(tp, 57765_CLASS))
0e6cf6a9
MC		 10108 tg3_chk_missed_msi(tp);
10109
63c3a66f 10110 if (!tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 10111 /* All of this garbage is because when using non-tagged
10112 * IRQ status the mailbox/status_block protocol the chip
10113 * uses with the cpu is race prone.
10114 */
898a56f8 10115 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 10116 tw32(GRC_LOCAL_CTRL,
10117 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10118 } else {
10119 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 10120 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 10121 }
1da177e4 10122
fac9b83e 10123 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
f47c11ee 10124 spin_unlock(&tp->lock);
db219973 10125 tg3_reset_task_schedule(tp);
5b190624 10126 goto restart_timer;
fac9b83e 10127 }
1da177e4
LT		 10128 }
10129
1da177e4
LT		 10130 /* This part only runs once per second. */
10131 if (!--tp->timer_counter) {
63c3a66f 10132 if (tg3_flag(tp, 5705_PLUS))
fac9b83e
DM		 10133 tg3_periodic_fetch_stats(tp);
10134
b0c5943f
MC		 10135 if (tp->setlpicnt && !--tp->setlpicnt)
10136 tg3_phy_eee_enable(tp);
52b02d04 10137
63c3a66f 10138 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 10139 u32 mac_stat;
10140 int phy_event;
10141
10142 mac_stat = tr32(MAC_STATUS);
10143
10144 phy_event = 0;
f07e9af3 10145 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
1da177e4
LT		 10146 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10147 phy_event = 1;
10148 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10149 phy_event = 1;
10150
10151 if (phy_event)
10152 tg3_setup_phy(tp, 0);
63c3a66f 10153 } else if (tg3_flag(tp, POLL_SERDES)) {
1da177e4
LT		 10154 u32 mac_stat = tr32(MAC_STATUS);
10155 int need_setup = 0;
10156
f4a46d1f 10157 if (tp->link_up &&
1da177e4
LT		 10158 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10159 need_setup = 1;
10160 }
f4a46d1f 10161 if (!tp->link_up &&
1da177e4
LT		 10162 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10163 MAC_STATUS_SIGNAL_DET))) {
10164 need_setup = 1;
10165 }
10166 if (need_setup) {
3d3ebe74
MC		 10167 if (!tp->serdes_counter) {
10168 tw32_f(MAC_MODE,
10169 (tp->mac_mode &
10170 ~MAC_MODE_PORT_MODE_MASK));
10171 udelay(40);
10172 tw32_f(MAC_MODE, tp->mac_mode);
10173 udelay(40);
10174 }
1da177e4
LT		 10175 tg3_setup_phy(tp, 0);
10176 }
f07e9af3 10177 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
63c3a66f 10178 tg3_flag(tp, 5780_CLASS)) {
747e8f8b 10179 tg3_serdes_parallel_detect(tp);
57d8b880 10180 }
1da177e4
LT		 10181
10182 tp->timer_counter = tp->timer_multiplier;
10183 }
10184
130b8e4d
MC		 10185 /* Heartbeat is only sent once every 2 seconds.
10186 *
10187 * The heartbeat is to tell the ASF firmware that the host
10188 * driver is still alive. In the event that the OS crashes,
10189 * ASF needs to reset the hardware to free up the FIFO space
10190 * that may be filled with rx packets destined for the host.
10191 * If the FIFO is full, ASF will no longer function properly.
10192 *
10193 * Unintended resets have been reported on real time kernels
10194 * where the timer doesn't run on time. Netpoll will also have
10195 * same problem.
10196 *
10197 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
10198 * to check the ring condition when the heartbeat is expiring
10199 * before doing the reset. This will prevent most unintended
10200 * resets.
10201 */
1da177e4 10202 if (!--tp->asf_counter) {
63c3a66f 10203 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7c5026aa
MC		 10204 tg3_wait_for_event_ack(tp);
10205
bbadf503 10206 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 10207 FWCMD_NICDRV_ALIVE3);
bbadf503 10208 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
c6cdf436
MC		 10209 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
10210 TG3_FW_UPDATE_TIMEOUT_SEC);
4ba526ce
MC		 10211
10212 tg3_generate_fw_event(tp);
1da177e4
LT		 10213 }
10214 tp->asf_counter = tp->asf_multiplier;
10215 }
10216
f47c11ee 10217 spin_unlock(&tp->lock);
1da177e4 10218
f475f163 10219restart_timer:
1da177e4
LT		 10220 tp->timer.expires = jiffies + tp->timer_offset;
10221 add_timer(&tp->timer);
10222}
10223
229b1ad1 10224static void tg3_timer_init(struct tg3 *tp)
21f7638e
MC		 10225{
10226 if (tg3_flag(tp, TAGGED_STATUS) &&
10227 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
10228 !tg3_flag(tp, 57765_CLASS))
10229 tp->timer_offset = HZ;
10230 else
10231 tp->timer_offset = HZ / 10;
10232
10233 BUG_ON(tp->timer_offset > HZ);
10234
10235 tp->timer_multiplier = (HZ / tp->timer_offset);
10236 tp->asf_multiplier = (HZ / tp->timer_offset) *
10237 TG3_FW_UPDATE_FREQ_SEC;
10238
10239 init_timer(&tp->timer);
10240 tp->timer.data = (unsigned long) tp;
10241 tp->timer.function = tg3_timer;
10242}
10243
10244static void tg3_timer_start(struct tg3 *tp)
10245{
10246 tp->asf_counter = tp->asf_multiplier;
10247 tp->timer_counter = tp->timer_multiplier;
10248
10249 tp->timer.expires = jiffies + tp->timer_offset;
10250 add_timer(&tp->timer);
10251}
10252
10253static void tg3_timer_stop(struct tg3 *tp)
10254{
10255 del_timer_sync(&tp->timer);
10256}
10257
10258/* Restart hardware after configuration changes, self-test, etc.
10259 * Invoked with tp->lock held.
10260 */
10261static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
10262 __releases(tp->lock)
10263 __acquires(tp->lock)
10264{
10265 int err;
10266
10267 err = tg3_init_hw(tp, reset_phy);
10268 if (err) {
10269 netdev_err(tp->dev,
10270 "Failed to re-initialize device, aborting\n");
10271 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10272 tg3_full_unlock(tp);
10273 tg3_timer_stop(tp);
10274 tp->irq_sync = 0;
10275 tg3_napi_enable(tp);
10276 dev_close(tp->dev);
10277 tg3_full_lock(tp, 0);
10278 }
10279 return err;
10280}
10281
10282static void tg3_reset_task(struct work_struct *work)
10283{
10284 struct tg3 *tp = container_of(work, struct tg3, reset_task);
10285 int err;
10286
10287 tg3_full_lock(tp, 0);
10288
10289 if (!netif_running(tp->dev)) {
10290 tg3_flag_clear(tp, RESET_TASK_PENDING);
10291 tg3_full_unlock(tp);
10292 return;
10293 }
10294
10295 tg3_full_unlock(tp);
10296
10297 tg3_phy_stop(tp);
10298
10299 tg3_netif_stop(tp);
10300
10301 tg3_full_lock(tp, 1);
10302
10303 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
10304 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10305 tp->write32_rx_mbox = tg3_write_flush_reg32;
10306 tg3_flag_set(tp, MBOX_WRITE_REORDER);
10307 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
10308 }
10309
10310 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
10311 err = tg3_init_hw(tp, 1);
10312 if (err)
10313 goto out;
10314
10315 tg3_netif_start(tp);
10316
10317out:
10318 tg3_full_unlock(tp);
10319
10320 if (!err)
10321 tg3_phy_start(tp);
10322
10323 tg3_flag_clear(tp, RESET_TASK_PENDING);
10324}
10325
4f125f42 10326static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 10327{
7d12e780 10328 irq_handler_t fn;
fcfa0a32 10329 unsigned long flags;
4f125f42
MC		 10330 char *name;
10331 struct tg3_napi *tnapi = &tp->napi[irq_num];
10332
10333 if (tp->irq_cnt == 1)
10334 name = tp->dev->name;
10335 else {
10336 name = &tnapi->irq_lbl[0];
10337 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
10338 name[IFNAMSIZ-1] = 0;
10339 }
fcfa0a32 10340
63c3a66f 10341 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
fcfa0a32 10342 fn = tg3_msi;
63c3a66f 10343 if (tg3_flag(tp, 1SHOT_MSI))
fcfa0a32 10344 fn = tg3_msi_1shot;
ab392d2d 10345 flags = 0;
fcfa0a32
MC		 10346 } else {
10347 fn = tg3_interrupt;
63c3a66f 10348 if (tg3_flag(tp, TAGGED_STATUS))
fcfa0a32 10349 fn = tg3_interrupt_tagged;
ab392d2d 10350 flags = IRQF_SHARED;
fcfa0a32 10351 }
4f125f42
MC		 10352
10353 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 10354}
10355
7938109f
MC		 10356static int tg3_test_interrupt(struct tg3 *tp)
10357{
09943a18 10358 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 10359 struct net_device *dev = tp->dev;
b16250e3 10360 int err, i, intr_ok = 0;
f6eb9b1f 10361 u32 val;
7938109f 10362
d4bc3927
MC		 10363 if (!netif_running(dev))
10364 return -ENODEV;
10365
7938109f
MC		 10366 tg3_disable_ints(tp);
10367
4f125f42 10368 free_irq(tnapi->irq_vec, tnapi);
7938109f 10369
f6eb9b1f
MC		 10370 /*
10371 * Turn off MSI one shot mode. Otherwise this test has no
10372 * observable way to know whether the interrupt was delivered.
10373 */
3aa1cdf8 10374 if (tg3_flag(tp, 57765_PLUS)) {
f6eb9b1f
MC		 10375 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
10376 tw32(MSGINT_MODE, val);
10377 }
10378
4f125f42 10379 err = request_irq(tnapi->irq_vec, tg3_test_isr,
f274fd9a 10380 IRQF_SHARED, dev->name, tnapi);
7938109f
MC		 10381 if (err)
10382 return err;
10383
898a56f8 10384 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 10385 tg3_enable_ints(tp);
10386
10387 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10388 tnapi->coal_now);
7938109f
MC		 10389
10390 for (i = 0; i < 5; i++) {
b16250e3
MC		 10391 u32 int_mbox, misc_host_ctrl;
10392
898a56f8 10393 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 10394 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
10395
10396 if ((int_mbox != 0) ||
10397 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
10398 intr_ok = 1;
7938109f 10399 break;
b16250e3
MC		 10400 }
10401
3aa1cdf8
MC		 10402 if (tg3_flag(tp, 57765_PLUS) &&
10403 tnapi->hw_status->status_tag != tnapi->last_tag)
10404 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
10405
7938109f
MC		 10406 msleep(10);
10407 }
10408
10409 tg3_disable_ints(tp);
10410
4f125f42 10411 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 10412
4f125f42 10413 err = tg3_request_irq(tp, 0);
7938109f
MC		 10414
10415 if (err)
10416 return err;
10417
f6eb9b1f
MC		 10418 if (intr_ok) {
10419 /* Reenable MSI one shot mode. */
5b39de91 10420 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
f6eb9b1f
MC		 10421 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
10422 tw32(MSGINT_MODE, val);
10423 }
7938109f 10424 return 0;
f6eb9b1f 10425 }
7938109f
MC		 10426
10427 return -EIO;
10428}
10429
10430/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
10431 * successfully restored
10432 */
10433static int tg3_test_msi(struct tg3 *tp)
10434{
7938109f
MC		 10435 int err;
10436 u16 pci_cmd;
10437
63c3a66f 10438 if (!tg3_flag(tp, USING_MSI))
7938109f
MC		 10439 return 0;
10440
10441 /* Turn off SERR reporting in case MSI terminates with Master
10442 * Abort.
10443 */
10444 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10445 pci_write_config_word(tp->pdev, PCI_COMMAND,
10446 pci_cmd & ~PCI_COMMAND_SERR);
10447
10448 err = tg3_test_interrupt(tp);
10449
10450 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10451
10452 if (!err)
10453 return 0;
10454
10455 /* other failures */
10456 if (err != -EIO)
10457 return err;
10458
10459 /* MSI test failed, go back to INTx mode */
5129c3a3
MC		 10460 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
10461 "to INTx mode. Please report this failure to the PCI "
10462 "maintainer and include system chipset information\n");
7938109f 10463
4f125f42 10464 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 10465
7938109f
MC		 10466 pci_disable_msi(tp->pdev);
10467
63c3a66f 10468 tg3_flag_clear(tp, USING_MSI);
dc8bf1b1 10469 tp->napi[0].irq_vec = tp->pdev->irq;
7938109f 10470
4f125f42 10471 err = tg3_request_irq(tp, 0);
7938109f
MC		 10472 if (err)
10473 return err;
10474
10475 /* Need to reset the chip because the MSI cycle may have terminated
10476 * with Master Abort.
10477 */
f47c11ee 10478 tg3_full_lock(tp, 1);
7938109f 10479
944d980e 10480 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 10481 err = tg3_init_hw(tp, 1);
7938109f 10482
f47c11ee 10483 tg3_full_unlock(tp);
7938109f
MC		 10484
10485 if (err)
4f125f42 10486 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 10487
10488 return err;
10489}
10490
9e9fd12d
MC		 10491static int tg3_request_firmware(struct tg3 *tp)
10492{
10493 const __be32 *fw_data;
10494
10495 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 10496 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
10497 tp->fw_needed);
9e9fd12d
MC		 10498 return -ENOENT;
10499 }
10500
10501 fw_data = (void *)tp->fw->data;
10502
10503 /* Firmware blob starts with version numbers, followed by
10504 * start address and _full_ length including BSS sections
10505 * (which must be longer than the actual data, of course
10506 */
10507
10508 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
10509 if (tp->fw_len < (tp->fw->size - 12)) {
05dbe005
JP		 10510 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
10511 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 10512 release_firmware(tp->fw);
10513 tp->fw = NULL;
10514 return -EINVAL;
10515 }
10516
10517 /* We no longer need firmware; we have it. */
10518 tp->fw_needed = NULL;
10519 return 0;
10520}
10521
9102426a 10522static u32 tg3_irq_count(struct tg3 *tp)
679563f4 10523{
9102426a 10524 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
679563f4 10525
9102426a 10526 if (irq_cnt > 1) {
c3b5003b
MC		 10527 /* We want as many rx rings enabled as there are cpus.
10528 * In multiqueue MSI-X mode, the first MSI-X vector
10529 * only deals with link interrupts, etc, so we add
10530 * one to the number of vectors we are requesting.
10531 */
9102426a 10532 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
c3b5003b 10533 }
679563f4 10534
9102426a
MC		 10535 return irq_cnt;
10536}
10537
10538static bool tg3_enable_msix(struct tg3 *tp)
10539{
10540 int i, rc;
86449944 10541 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
9102426a 10542
0968169c
MC		 10543 tp->txq_cnt = tp->txq_req;
10544 tp->rxq_cnt = tp->rxq_req;
10545 if (!tp->rxq_cnt)
10546 tp->rxq_cnt = netif_get_num_default_rss_queues();
9102426a
MC		 10547 if (tp->rxq_cnt > tp->rxq_max)
10548 tp->rxq_cnt = tp->rxq_max;
cf6d6ea6
MC		 10549
10550 /* Disable multiple TX rings by default. Simple round-robin hardware
10551 * scheduling of the TX rings can cause starvation of rings with
10552 * small packets when other rings have TSO or jumbo packets.
10553 */
10554 if (!tp->txq_req)
10555 tp->txq_cnt = 1;
9102426a
MC		 10556
10557 tp->irq_cnt = tg3_irq_count(tp);
10558
679563f4
MC		 10559 for (i = 0; i < tp->irq_max; i++) {
10560 msix_ent[i].entry = i;
10561 msix_ent[i].vector = 0;
10562 }
10563
10564 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
2430b031
MC		 10565 if (rc < 0) {
10566 return false;
10567 } else if (rc != 0) {
679563f4
MC		 10568 if (pci_enable_msix(tp->pdev, msix_ent, rc))
10569 return false;
05dbe005
JP		 10570 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
10571 tp->irq_cnt, rc);
679563f4 10572 tp->irq_cnt = rc;
49a359e3 10573 tp->rxq_cnt = max(rc - 1, 1);
9102426a
MC		 10574 if (tp->txq_cnt)
10575 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
679563f4
MC		 10576 }
10577
10578 for (i = 0; i < tp->irq_max; i++)
10579 tp->napi[i].irq_vec = msix_ent[i].vector;
10580
49a359e3 10581 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
2ddaad39
BH		 10582 pci_disable_msix(tp->pdev);
10583 return false;
10584 }
b92b9040 10585
9102426a
MC		 10586 if (tp->irq_cnt == 1)
10587 return true;
d78b59f5 10588
9102426a
MC		 10589 tg3_flag_set(tp, ENABLE_RSS);
10590
10591 if (tp->txq_cnt > 1)
10592 tg3_flag_set(tp, ENABLE_TSS);
10593
10594 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
2430b031 10595
679563f4
MC		 10596 return true;
10597}
10598
07b0173c
MC		 10599static void tg3_ints_init(struct tg3 *tp)
10600{
63c3a66f
JP		 10601 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
10602 !tg3_flag(tp, TAGGED_STATUS)) {
07b0173c
MC		 10603 /* All MSI supporting chips should support tagged
10604 * status. Assert that this is the case.
10605 */
5129c3a3
MC		 10606 netdev_warn(tp->dev,
10607 "MSI without TAGGED_STATUS? Not using MSI\n");
679563f4 10608 goto defcfg;
07b0173c 10609 }
4f125f42 10610
63c3a66f
JP		 10611 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
10612 tg3_flag_set(tp, USING_MSIX);
10613 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
10614 tg3_flag_set(tp, USING_MSI);
679563f4 10615
63c3a66f 10616 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
679563f4 10617 u32 msi_mode = tr32(MSGINT_MODE);
63c3a66f 10618 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
baf8a94a 10619 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 10620 if (!tg3_flag(tp, 1SHOT_MSI))
10621 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
679563f4
MC		 10622 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
10623 }
10624defcfg:
63c3a66f 10625 if (!tg3_flag(tp, USING_MSIX)) {
679563f4
MC		 10626 tp->irq_cnt = 1;
10627 tp->napi[0].irq_vec = tp->pdev->irq;
49a359e3
MC		 10628 }
10629
10630 if (tp->irq_cnt == 1) {
10631 tp->txq_cnt = 1;
10632 tp->rxq_cnt = 1;
2ddaad39 10633 netif_set_real_num_tx_queues(tp->dev, 1);
85407885 10634 netif_set_real_num_rx_queues(tp->dev, 1);
679563f4 10635 }
07b0173c
MC		 10636}
10637
10638static void tg3_ints_fini(struct tg3 *tp)
10639{
63c3a66f 10640 if (tg3_flag(tp, USING_MSIX))
679563f4 10641 pci_disable_msix(tp->pdev);
63c3a66f 10642 else if (tg3_flag(tp, USING_MSI))
679563f4 10643 pci_disable_msi(tp->pdev);
63c3a66f
JP		 10644 tg3_flag_clear(tp, USING_MSI);
10645 tg3_flag_clear(tp, USING_MSIX);
10646 tg3_flag_clear(tp, ENABLE_RSS);
10647 tg3_flag_clear(tp, ENABLE_TSS);
07b0173c
MC		 10648}
10649
be947307
MC		 10650static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
10651 bool init)
1da177e4 10652{
d8f4cd38 10653 struct net_device *dev = tp->dev;
4f125f42 10654 int i, err;
1da177e4 10655
679563f4
MC		 10656 /*
10657 * Setup interrupts first so we know how
10658 * many NAPI resources to allocate
10659 */
10660 tg3_ints_init(tp);
10661
90415477 10662 tg3_rss_check_indir_tbl(tp);
bcebcc46 10663
1da177e4
LT		 10664 /* The placement of this call is tied
10665 * to the setup and use of Host TX descriptors.
10666 */
10667 err = tg3_alloc_consistent(tp);
10668 if (err)
679563f4 10669 goto err_out1;
88b06bc2 10670
66cfd1bd
MC		 10671 tg3_napi_init(tp);
10672
fed97810 10673 tg3_napi_enable(tp);
1da177e4 10674
4f125f42
MC		 10675 for (i = 0; i < tp->irq_cnt; i++) {
10676 struct tg3_napi *tnapi = &tp->napi[i];
10677 err = tg3_request_irq(tp, i);
10678 if (err) {
5bc09186
MC		 10679 for (i--; i >= 0; i--) {
10680 tnapi = &tp->napi[i];
4f125f42 10681 free_irq(tnapi->irq_vec, tnapi);
5bc09186
MC		 10682 }
10683 goto err_out2;
4f125f42
MC		 10684 }
10685 }
1da177e4 10686
f47c11ee 10687 tg3_full_lock(tp, 0);
1da177e4 10688
d8f4cd38 10689 err = tg3_init_hw(tp, reset_phy);
1da177e4 10690 if (err) {
944d980e 10691 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 10692 tg3_free_rings(tp);
1da177e4
LT		 10693 }
10694
f47c11ee 10695 tg3_full_unlock(tp);
1da177e4 10696
07b0173c 10697 if (err)
679563f4 10698 goto err_out3;
1da177e4 10699
d8f4cd38 10700 if (test_irq && tg3_flag(tp, USING_MSI)) {
7938109f 10701 err = tg3_test_msi(tp);
fac9b83e 10702
7938109f 10703 if (err) {
f47c11ee 10704 tg3_full_lock(tp, 0);
944d980e 10705 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 10706 tg3_free_rings(tp);
f47c11ee 10707 tg3_full_unlock(tp);
7938109f 10708
679563f4 10709 goto err_out2;
7938109f 10710 }
fcfa0a32 10711
63c3a66f 10712 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
f6eb9b1f 10713 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 10714
f6eb9b1f
MC		 10715 tw32(PCIE_TRANSACTION_CFG,
10716 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 10717 }
7938109f
MC		 10718 }
10719
b02fd9e3
MC		 10720 tg3_phy_start(tp);
10721
aed93e0b
MC		 10722 tg3_hwmon_open(tp);
10723
f47c11ee 10724 tg3_full_lock(tp, 0);
1da177e4 10725
21f7638e 10726 tg3_timer_start(tp);
63c3a66f 10727 tg3_flag_set(tp, INIT_COMPLETE);
1da177e4
LT		 10728 tg3_enable_ints(tp);
10729
be947307
MC		 10730 if (init)
10731 tg3_ptp_init(tp);
10732 else
10733 tg3_ptp_resume(tp);
10734
10735
f47c11ee 10736 tg3_full_unlock(tp);
1da177e4 10737
fe5f5787 10738 netif_tx_start_all_queues(dev);
1da177e4 10739
06c03c02
MB		 10740 /*
10741 * Reset loopback feature if it was turned on while the device was down
10742 * make sure that it's installed properly now.
10743 */
10744 if (dev->features & NETIF_F_LOOPBACK)
10745 tg3_set_loopback(dev, dev->features);
10746
1da177e4 10747 return 0;
07b0173c 10748
679563f4 10749err_out3:
4f125f42
MC		 10750 for (i = tp->irq_cnt - 1; i >= 0; i--) {
10751 struct tg3_napi *tnapi = &tp->napi[i];
10752 free_irq(tnapi->irq_vec, tnapi);
10753 }
07b0173c 10754
679563f4 10755err_out2:
fed97810 10756 tg3_napi_disable(tp);
66cfd1bd 10757 tg3_napi_fini(tp);
07b0173c 10758 tg3_free_consistent(tp);
679563f4
MC		 10759
10760err_out1:
10761 tg3_ints_fini(tp);
d8f4cd38 10762
07b0173c 10763 return err;
1da177e4
LT		 10764}
10765
65138594 10766static void tg3_stop(struct tg3 *tp)
1da177e4 10767{
4f125f42 10768 int i;
1da177e4 10769
db219973 10770 tg3_reset_task_cancel(tp);
bd473da3 10771 tg3_netif_stop(tp);
1da177e4 10772
21f7638e 10773 tg3_timer_stop(tp);
1da177e4 10774
aed93e0b
MC		 10775 tg3_hwmon_close(tp);
10776
24bb4fb6
MC		 10777 tg3_phy_stop(tp);
10778
f47c11ee 10779 tg3_full_lock(tp, 1);
1da177e4
LT		 10780
10781 tg3_disable_ints(tp);
10782
944d980e 10783 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 10784 tg3_free_rings(tp);
63c3a66f 10785 tg3_flag_clear(tp, INIT_COMPLETE);
1da177e4 10786
f47c11ee 10787 tg3_full_unlock(tp);
1da177e4 10788
4f125f42
MC		 10789 for (i = tp->irq_cnt - 1; i >= 0; i--) {
10790 struct tg3_napi *tnapi = &tp->napi[i];
10791 free_irq(tnapi->irq_vec, tnapi);
10792 }
07b0173c
MC		 10793
10794 tg3_ints_fini(tp);
1da177e4 10795
66cfd1bd
MC		 10796 tg3_napi_fini(tp);
10797
1da177e4 10798 tg3_free_consistent(tp);
65138594
MC		 10799}
10800
d8f4cd38
MC		 10801static int tg3_open(struct net_device *dev)
10802{
10803 struct tg3 *tp = netdev_priv(dev);
10804 int err;
10805
10806 if (tp->fw_needed) {
10807 err = tg3_request_firmware(tp);
10808 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
10809 if (err)
10810 return err;
10811 } else if (err) {
10812 netdev_warn(tp->dev, "TSO capability disabled\n");
10813 tg3_flag_clear(tp, TSO_CAPABLE);
10814 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
10815 netdev_notice(tp->dev, "TSO capability restored\n");
10816 tg3_flag_set(tp, TSO_CAPABLE);
10817 }
10818 }
10819
f4a46d1f 10820 tg3_carrier_off(tp);
d8f4cd38
MC		 10821
10822 err = tg3_power_up(tp);
10823 if (err)
10824 return err;
10825
10826 tg3_full_lock(tp, 0);
10827
10828 tg3_disable_ints(tp);
10829 tg3_flag_clear(tp, INIT_COMPLETE);
10830
10831 tg3_full_unlock(tp);
10832
be947307 10833 err = tg3_start(tp, true, true, true);
d8f4cd38
MC		 10834 if (err) {
10835 tg3_frob_aux_power(tp, false);
10836 pci_set_power_state(tp->pdev, PCI_D3hot);
10837 }
be947307 10838
7d41e49a
MC		 10839 if (tg3_flag(tp, PTP_CAPABLE)) {
10840 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
10841 &tp->pdev->dev);
10842 if (IS_ERR(tp->ptp_clock))
10843 tp->ptp_clock = NULL;
10844 }
10845
07b0173c 10846 return err;
1da177e4
LT		 10847}
10848
1da177e4
LT		 10849static int tg3_close(struct net_device *dev)
10850{
10851 struct tg3 *tp = netdev_priv(dev);
10852
be947307
MC		 10853 tg3_ptp_fini(tp);
10854
65138594 10855 tg3_stop(tp);
1da177e4 10856
92feeabf
MC		 10857 /* Clear stats across close / open calls */
10858 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
10859 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
1da177e4 10860
c866b7ea 10861 tg3_power_down(tp);
bc1c7567 10862
f4a46d1f 10863 tg3_carrier_off(tp);
bc1c7567 10864
1da177e4
LT		 10865 return 0;
10866}
10867
511d2224 10868static inline u64 get_stat64(tg3_stat64_t *val)
816f8b86
SB		 10869{
10870 return ((u64)val->high << 32) | ((u64)val->low);
10871}
10872
65ec698d 10873static u64 tg3_calc_crc_errors(struct tg3 *tp)
1da177e4
LT		 10874{
10875 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10876
f07e9af3 10877 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
1da177e4
LT		 10878 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10879 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 10880 u32 val;
10881
569a5df8
MC		 10882 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
10883 tg3_writephy(tp, MII_TG3_TEST1,
10884 val | MII_TG3_TEST1_CRC_EN);
f08aa1a8 10885 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
1da177e4
LT		 10886 } else
10887 val = 0;
1da177e4
LT		 10888
10889 tp->phy_crc_errors += val;
10890
10891 return tp->phy_crc_errors;
10892 }
10893
10894 return get_stat64(&hw_stats->rx_fcs_errors);
10895}
10896
10897#define ESTAT_ADD(member) \
10898 estats->member = old_estats->member + \
511d2224 10899 get_stat64(&hw_stats->member)
1da177e4 10900
65ec698d 10901static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
1da177e4 10902{
1da177e4
LT		 10903 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
10904 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10905
1da177e4
LT		 10906 ESTAT_ADD(rx_octets);
10907 ESTAT_ADD(rx_fragments);
10908 ESTAT_ADD(rx_ucast_packets);
10909 ESTAT_ADD(rx_mcast_packets);
10910 ESTAT_ADD(rx_bcast_packets);
10911 ESTAT_ADD(rx_fcs_errors);
10912 ESTAT_ADD(rx_align_errors);
10913 ESTAT_ADD(rx_xon_pause_rcvd);
10914 ESTAT_ADD(rx_xoff_pause_rcvd);
10915 ESTAT_ADD(rx_mac_ctrl_rcvd);
10916 ESTAT_ADD(rx_xoff_entered);
10917 ESTAT_ADD(rx_frame_too_long_errors);
10918 ESTAT_ADD(rx_jabbers);
10919 ESTAT_ADD(rx_undersize_packets);
10920 ESTAT_ADD(rx_in_length_errors);
10921 ESTAT_ADD(rx_out_length_errors);
10922 ESTAT_ADD(rx_64_or_less_octet_packets);
10923 ESTAT_ADD(rx_65_to_127_octet_packets);
10924 ESTAT_ADD(rx_128_to_255_octet_packets);
10925 ESTAT_ADD(rx_256_to_511_octet_packets);
10926 ESTAT_ADD(rx_512_to_1023_octet_packets);
10927 ESTAT_ADD(rx_1024_to_1522_octet_packets);
10928 ESTAT_ADD(rx_1523_to_2047_octet_packets);
10929 ESTAT_ADD(rx_2048_to_4095_octet_packets);
10930 ESTAT_ADD(rx_4096_to_8191_octet_packets);
10931 ESTAT_ADD(rx_8192_to_9022_octet_packets);
10932
10933 ESTAT_ADD(tx_octets);
10934 ESTAT_ADD(tx_collisions);
10935 ESTAT_ADD(tx_xon_sent);
10936 ESTAT_ADD(tx_xoff_sent);
10937 ESTAT_ADD(tx_flow_control);
10938 ESTAT_ADD(tx_mac_errors);
10939 ESTAT_ADD(tx_single_collisions);
10940 ESTAT_ADD(tx_mult_collisions);
10941 ESTAT_ADD(tx_deferred);
10942 ESTAT_ADD(tx_excessive_collisions);
10943 ESTAT_ADD(tx_late_collisions);
10944 ESTAT_ADD(tx_collide_2times);
10945 ESTAT_ADD(tx_collide_3times);
10946 ESTAT_ADD(tx_collide_4times);
10947 ESTAT_ADD(tx_collide_5times);
10948 ESTAT_ADD(tx_collide_6times);
10949 ESTAT_ADD(tx_collide_7times);
10950 ESTAT_ADD(tx_collide_8times);
10951 ESTAT_ADD(tx_collide_9times);
10952 ESTAT_ADD(tx_collide_10times);
10953 ESTAT_ADD(tx_collide_11times);
10954 ESTAT_ADD(tx_collide_12times);
10955 ESTAT_ADD(tx_collide_13times);
10956 ESTAT_ADD(tx_collide_14times);
10957 ESTAT_ADD(tx_collide_15times);
10958 ESTAT_ADD(tx_ucast_packets);
10959 ESTAT_ADD(tx_mcast_packets);
10960 ESTAT_ADD(tx_bcast_packets);
10961 ESTAT_ADD(tx_carrier_sense_errors);
10962 ESTAT_ADD(tx_discards);
10963 ESTAT_ADD(tx_errors);
10964
10965 ESTAT_ADD(dma_writeq_full);
10966 ESTAT_ADD(dma_write_prioq_full);
10967 ESTAT_ADD(rxbds_empty);
10968 ESTAT_ADD(rx_discards);
10969 ESTAT_ADD(rx_errors);
10970 ESTAT_ADD(rx_threshold_hit);
10971
10972 ESTAT_ADD(dma_readq_full);
10973 ESTAT_ADD(dma_read_prioq_full);
10974 ESTAT_ADD(tx_comp_queue_full);
10975
10976 ESTAT_ADD(ring_set_send_prod_index);
10977 ESTAT_ADD(ring_status_update);
10978 ESTAT_ADD(nic_irqs);
10979 ESTAT_ADD(nic_avoided_irqs);
10980 ESTAT_ADD(nic_tx_threshold_hit);
10981
4452d099 10982 ESTAT_ADD(mbuf_lwm_thresh_hit);
1da177e4
LT		 10983}
10984
65ec698d 10985static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
1da177e4 10986{
511d2224 10987 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
1da177e4
LT		 10988 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10989
1da177e4
LT		 10990 stats->rx_packets = old_stats->rx_packets +
10991 get_stat64(&hw_stats->rx_ucast_packets) +
10992 get_stat64(&hw_stats->rx_mcast_packets) +
10993 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 10994
1da177e4
LT		 10995 stats->tx_packets = old_stats->tx_packets +
10996 get_stat64(&hw_stats->tx_ucast_packets) +
10997 get_stat64(&hw_stats->tx_mcast_packets) +
10998 get_stat64(&hw_stats->tx_bcast_packets);
10999
11000 stats->rx_bytes = old_stats->rx_bytes +
11001 get_stat64(&hw_stats->rx_octets);
11002 stats->tx_bytes = old_stats->tx_bytes +
11003 get_stat64(&hw_stats->tx_octets);
11004
11005 stats->rx_errors = old_stats->rx_errors +
4f63b877 11006 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 11007 stats->tx_errors = old_stats->tx_errors +
11008 get_stat64(&hw_stats->tx_errors) +
11009 get_stat64(&hw_stats->tx_mac_errors) +
11010 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11011 get_stat64(&hw_stats->tx_discards);
11012
11013 stats->multicast = old_stats->multicast +
11014 get_stat64(&hw_stats->rx_mcast_packets);
11015 stats->collisions = old_stats->collisions +
11016 get_stat64(&hw_stats->tx_collisions);
11017
11018 stats->rx_length_errors = old_stats->rx_length_errors +
11019 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11020 get_stat64(&hw_stats->rx_undersize_packets);
11021
11022 stats->rx_over_errors = old_stats->rx_over_errors +
11023 get_stat64(&hw_stats->rxbds_empty);
11024 stats->rx_frame_errors = old_stats->rx_frame_errors +
11025 get_stat64(&hw_stats->rx_align_errors);
11026 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11027 get_stat64(&hw_stats->tx_discards);
11028 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11029 get_stat64(&hw_stats->tx_carrier_sense_errors);
11030
11031 stats->rx_crc_errors = old_stats->rx_crc_errors +
65ec698d 11032 tg3_calc_crc_errors(tp);
1da177e4 11033
4f63b877
JL		 11034 stats->rx_missed_errors = old_stats->rx_missed_errors +
11035 get_stat64(&hw_stats->rx_discards);
11036
b0057c51 11037 stats->rx_dropped = tp->rx_dropped;
48855432 11038 stats->tx_dropped = tp->tx_dropped;
1da177e4
LT		 11039}
11040
1da177e4
LT		 11041static int tg3_get_regs_len(struct net_device *dev)
11042{
97bd8e49 11043 return TG3_REG_BLK_SIZE;
1da177e4
LT		 11044}
11045
11046static void tg3_get_regs(struct net_device *dev,
11047 struct ethtool_regs *regs, void *_p)
11048{
1da177e4 11049 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 11050
11051 regs->version = 0;
11052
97bd8e49 11053 memset(_p, 0, TG3_REG_BLK_SIZE);
1da177e4 11054
80096068 11055 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
bc1c7567
MC		 11056 return;
11057
f47c11ee 11058 tg3_full_lock(tp, 0);
1da177e4 11059
97bd8e49 11060 tg3_dump_legacy_regs(tp, (u32 *)_p);
1da177e4 11061
f47c11ee 11062 tg3_full_unlock(tp);
1da177e4
LT		 11063}
11064
11065static int tg3_get_eeprom_len(struct net_device *dev)
11066{
11067 struct tg3 *tp = netdev_priv(dev);
11068
11069 return tp->nvram_size;
11070}
11071
1da177e4
LT		 11072static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11073{
11074 struct tg3 *tp = netdev_priv(dev);
11075 int ret;
11076 u8 *pd;
b9fc7dc5 11077 u32 i, offset, len, b_offset, b_count;
a9dc529d 11078 __be32 val;
1da177e4 11079
63c3a66f 11080 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 11081 return -EINVAL;
11082
80096068 11083 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
bc1c7567
MC		 11084 return -EAGAIN;
11085
1da177e4
LT		 11086 offset = eeprom->offset;
11087 len = eeprom->len;
11088 eeprom->len = 0;
11089
11090 eeprom->magic = TG3_EEPROM_MAGIC;
11091
11092 if (offset & 3) {
11093 /* adjustments to start on required 4 byte boundary */
11094 b_offset = offset & 3;
11095 b_count = 4 - b_offset;
11096 if (b_count > len) {
11097 /* i.e. offset=1 len=2 */
11098 b_count = len;
11099 }
a9dc529d 11100 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 11101 if (ret)
11102 return ret;
be98da6a 11103 memcpy(data, ((char *)&val) + b_offset, b_count);
1da177e4
LT		 11104 len -= b_count;
11105 offset += b_count;
c6cdf436 11106 eeprom->len += b_count;
1da177e4
LT		 11107 }
11108
25985edc 11109 /* read bytes up to the last 4 byte boundary */
1da177e4
LT		 11110 pd = &data[eeprom->len];
11111 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 11112 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 11113 if (ret) {
11114 eeprom->len += i;
11115 return ret;
11116 }
1da177e4
LT		 11117 memcpy(pd + i, &val, 4);
11118 }
11119 eeprom->len += i;
11120
11121 if (len & 3) {
11122 /* read last bytes not ending on 4 byte boundary */
11123 pd = &data[eeprom->len];
11124 b_count = len & 3;
11125 b_offset = offset + len - b_count;
a9dc529d 11126 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 11127 if (ret)
11128 return ret;
b9fc7dc5 11129 memcpy(pd, &val, b_count);
1da177e4
LT		 11130 eeprom->len += b_count;
11131 }
11132 return 0;
11133}
11134
1da177e4
LT		 11135static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11136{
11137 struct tg3 *tp = netdev_priv(dev);
11138 int ret;
b9fc7dc5 11139 u32 offset, len, b_offset, odd_len;
1da177e4 11140 u8 *buf;
a9dc529d 11141 __be32 start, end;
1da177e4 11142
80096068 11143 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
bc1c7567
MC		 11144 return -EAGAIN;
11145
63c3a66f 11146 if (tg3_flag(tp, NO_NVRAM) ||
df259d8c 11147 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 11148 return -EINVAL;
11149
11150 offset = eeprom->offset;
11151 len = eeprom->len;
11152
11153 if ((b_offset = (offset & 3))) {
11154 /* adjustments to start on required 4 byte boundary */
a9dc529d 11155 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 11156 if (ret)
11157 return ret;
1da177e4
LT		 11158 len += b_offset;
11159 offset &= ~3;
1c8594b4
MC		 11160 if (len < 4)
11161 len = 4;
1da177e4
LT		 11162 }
11163
11164 odd_len = 0;
1c8594b4 11165 if (len & 3) {
1da177e4
LT		 11166 /* adjustments to end on required 4 byte boundary */
11167 odd_len = 1;
11168 len = (len + 3) & ~3;
a9dc529d 11169 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 11170 if (ret)
11171 return ret;
1da177e4
LT		 11172 }
11173
11174 buf = data;
11175 if (b_offset || odd_len) {
11176 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 11177 if (!buf)
1da177e4
LT		 11178 return -ENOMEM;
11179 if (b_offset)
11180 memcpy(buf, &start, 4);
11181 if (odd_len)
11182 memcpy(buf+len-4, &end, 4);
11183 memcpy(buf + b_offset, data, eeprom->len);
11184 }
11185
11186 ret = tg3_nvram_write_block(tp, offset, len, buf);
11187
11188 if (buf != data)
11189 kfree(buf);
11190
11191 return ret;
11192}
11193
11194static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11195{
b02fd9e3
MC		 11196 struct tg3 *tp = netdev_priv(dev);
11197
63c3a66f 11198 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 11199 struct phy_device *phydev;
f07e9af3 11200 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 11201 return -EAGAIN;
3f0e3ad7
MC		 11202 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11203 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 11204 }
6aa20a22 11205
1da177e4
LT		 11206 cmd->supported = (SUPPORTED_Autoneg);
11207
f07e9af3 11208 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
1da177e4
LT		 11209 cmd->supported |= (SUPPORTED_1000baseT_Half |
11210 SUPPORTED_1000baseT_Full);
11211
f07e9af3 11212 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
1da177e4
LT		 11213 cmd->supported |= (SUPPORTED_100baseT_Half |
11214 SUPPORTED_100baseT_Full |
11215 SUPPORTED_10baseT_Half |
11216 SUPPORTED_10baseT_Full |
3bebab59 11217 SUPPORTED_TP);
ef348144
KK		 11218 cmd->port = PORT_TP;
11219 } else {
1da177e4 11220 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 11221 cmd->port = PORT_FIBRE;
11222 }
6aa20a22 11223
1da177e4 11224 cmd->advertising = tp->link_config.advertising;
5bb09778
MC		 11225 if (tg3_flag(tp, PAUSE_AUTONEG)) {
11226 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
11227 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11228 cmd->advertising |= ADVERTISED_Pause;
11229 } else {
11230 cmd->advertising |= ADVERTISED_Pause |
11231 ADVERTISED_Asym_Pause;
11232 }
11233 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11234 cmd->advertising |= ADVERTISED_Asym_Pause;
11235 }
11236 }
f4a46d1f 11237 if (netif_running(dev) && tp->link_up) {
70739497 11238 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
1da177e4 11239 cmd->duplex = tp->link_config.active_duplex;
859edb26 11240 cmd->lp_advertising = tp->link_config.rmt_adv;
e348c5e7
MC		 11241 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
11242 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
11243 cmd->eth_tp_mdix = ETH_TP_MDI_X;
11244 else
11245 cmd->eth_tp_mdix = ETH_TP_MDI;
11246 }
64c22182 11247 } else {
e740522e
MC		 11248 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
11249 cmd->duplex = DUPLEX_UNKNOWN;
e348c5e7 11250 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
1da177e4 11251 }
882e9793 11252 cmd->phy_address = tp->phy_addr;
7e5856bd 11253 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 11254 cmd->autoneg = tp->link_config.autoneg;
11255 cmd->maxtxpkt = 0;
11256 cmd->maxrxpkt = 0;
11257 return 0;
11258}
6aa20a22 11259
1da177e4
LT		 11260static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11261{
11262 struct tg3 *tp = netdev_priv(dev);
25db0338 11263 u32 speed = ethtool_cmd_speed(cmd);
6aa20a22 11264
63c3a66f 11265 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 11266 struct phy_device *phydev;
f07e9af3 11267 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 11268 return -EAGAIN;
3f0e3ad7
MC		 11269 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11270 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 11271 }
11272
7e5856bd
MC		 11273 if (cmd->autoneg != AUTONEG_ENABLE &&
11274 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 11275 return -EINVAL;
7e5856bd
MC		 11276
11277 if (cmd->autoneg == AUTONEG_DISABLE &&
11278 cmd->duplex != DUPLEX_FULL &&
11279 cmd->duplex != DUPLEX_HALF)
37ff238d 11280 return -EINVAL;
1da177e4 11281
7e5856bd
MC		 11282 if (cmd->autoneg == AUTONEG_ENABLE) {
11283 u32 mask = ADVERTISED_Autoneg |
11284 ADVERTISED_Pause |
11285 ADVERTISED_Asym_Pause;
11286
f07e9af3 11287 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
7e5856bd
MC		 11288 mask |= ADVERTISED_1000baseT_Half |
11289 ADVERTISED_1000baseT_Full;
11290
f07e9af3 11291 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
7e5856bd
MC		 11292 mask |= ADVERTISED_100baseT_Half |
11293 ADVERTISED_100baseT_Full |
11294 ADVERTISED_10baseT_Half |
11295 ADVERTISED_10baseT_Full |
11296 ADVERTISED_TP;
11297 else
11298 mask |= ADVERTISED_FIBRE;
11299
11300 if (cmd->advertising & ~mask)
11301 return -EINVAL;
11302
11303 mask &= (ADVERTISED_1000baseT_Half |
11304 ADVERTISED_1000baseT_Full |
11305 ADVERTISED_100baseT_Half |
11306 ADVERTISED_100baseT_Full |
11307 ADVERTISED_10baseT_Half |
11308 ADVERTISED_10baseT_Full);
11309
11310 cmd->advertising &= mask;
11311 } else {
f07e9af3 11312 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
25db0338 11313 if (speed != SPEED_1000)
7e5856bd
MC		 11314 return -EINVAL;
11315
11316 if (cmd->duplex != DUPLEX_FULL)
11317 return -EINVAL;
11318 } else {
25db0338
DD		 11319 if (speed != SPEED_100 &&
11320 speed != SPEED_10)
7e5856bd
MC		 11321 return -EINVAL;
11322 }
11323 }
11324
f47c11ee 11325 tg3_full_lock(tp, 0);
1da177e4
LT		 11326
11327 tp->link_config.autoneg = cmd->autoneg;
11328 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 11329 tp->link_config.advertising = (cmd->advertising |
11330 ADVERTISED_Autoneg);
e740522e
MC		 11331 tp->link_config.speed = SPEED_UNKNOWN;
11332 tp->link_config.duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 11333 } else {
11334 tp->link_config.advertising = 0;
25db0338 11335 tp->link_config.speed = speed;
1da177e4 11336 tp->link_config.duplex = cmd->duplex;
b02fd9e3 11337 }
6aa20a22 11338
1da177e4
LT		 11339 if (netif_running(dev))
11340 tg3_setup_phy(tp, 1);
11341
f47c11ee 11342 tg3_full_unlock(tp);
6aa20a22 11343
1da177e4
LT		 11344 return 0;
11345}
6aa20a22 11346
1da177e4
LT		 11347static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
11348{
11349 struct tg3 *tp = netdev_priv(dev);
6aa20a22 11350
68aad78c
RJ		 11351 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
11352 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
11353 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
11354 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
1da177e4 11355}
6aa20a22 11356
1da177e4
LT		 11357static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
11358{
11359 struct tg3 *tp = netdev_priv(dev);
6aa20a22 11360
63c3a66f 11361 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 11362 wol->supported = WAKE_MAGIC;
11363 else
11364 wol->supported = 0;
1da177e4 11365 wol->wolopts = 0;
63c3a66f 11366 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 11367 wol->wolopts = WAKE_MAGIC;
11368 memset(&wol->sopass, 0, sizeof(wol->sopass));
11369}
6aa20a22 11370
1da177e4
LT		 11371static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
11372{
11373 struct tg3 *tp = netdev_priv(dev);
12dac075 11374 struct device *dp = &tp->pdev->dev;
6aa20a22 11375
1da177e4
LT		 11376 if (wol->wolopts & ~WAKE_MAGIC)
11377 return -EINVAL;
11378 if ((wol->wolopts & WAKE_MAGIC) &&
63c3a66f 11379 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
1da177e4 11380 return -EINVAL;
6aa20a22 11381
f2dc0d18
RW		 11382 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
11383
f47c11ee 11384 spin_lock_bh(&tp->lock);
f2dc0d18 11385 if (device_may_wakeup(dp))
63c3a66f 11386 tg3_flag_set(tp, WOL_ENABLE);
f2dc0d18 11387 else
63c3a66f 11388 tg3_flag_clear(tp, WOL_ENABLE);
f47c11ee 11389 spin_unlock_bh(&tp->lock);
6aa20a22 11390
1da177e4
LT		 11391 return 0;
11392}
6aa20a22 11393
1da177e4
LT		 11394static u32 tg3_get_msglevel(struct net_device *dev)
11395{
11396 struct tg3 *tp = netdev_priv(dev);
11397 return tp->msg_enable;
11398}
6aa20a22 11399
1da177e4
LT		 11400static void tg3_set_msglevel(struct net_device *dev, u32 value)
11401{
11402 struct tg3 *tp = netdev_priv(dev);
11403 tp->msg_enable = value;
11404}
6aa20a22 11405
1da177e4
LT		 11406static int tg3_nway_reset(struct net_device *dev)
11407{
11408 struct tg3 *tp = netdev_priv(dev);
1da177e4 11409 int r;
6aa20a22 11410
1da177e4
LT		 11411 if (!netif_running(dev))
11412 return -EAGAIN;
11413
f07e9af3 11414 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
c94e3941
MC		 11415 return -EINVAL;
11416
63c3a66f 11417 if (tg3_flag(tp, USE_PHYLIB)) {
f07e9af3 11418 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 11419 return -EAGAIN;
3f0e3ad7 11420 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 11421 } else {
11422 u32 bmcr;
11423
11424 spin_lock_bh(&tp->lock);
11425 r = -EINVAL;
11426 tg3_readphy(tp, MII_BMCR, &bmcr);
11427 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
11428 ((bmcr & BMCR_ANENABLE) ||
f07e9af3 11429 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
b02fd9e3
MC		 11430 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
11431 BMCR_ANENABLE);
11432 r = 0;
11433 }
11434 spin_unlock_bh(&tp->lock);
1da177e4 11435 }
6aa20a22 11436
1da177e4
LT		 11437 return r;
11438}
6aa20a22 11439
1da177e4
LT		 11440static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
11441{
11442 struct tg3 *tp = netdev_priv(dev);
6aa20a22 11443
2c49a44d 11444 ering->rx_max_pending = tp->rx_std_ring_mask;
63c3a66f 11445 if (tg3_flag(tp, JUMBO_RING_ENABLE))
2c49a44d 11446 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
4f81c32b
MC		 11447 else
11448 ering->rx_jumbo_max_pending = 0;
11449
11450 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 11451
11452 ering->rx_pending = tp->rx_pending;
63c3a66f 11453 if (tg3_flag(tp, JUMBO_RING_ENABLE))
4f81c32b
MC		 11454 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
11455 else
11456 ering->rx_jumbo_pending = 0;
11457
f3f3f27e 11458 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 11459}
6aa20a22 11460
1da177e4
LT		 11461static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
11462{
11463 struct tg3 *tp = netdev_priv(dev);
646c9edd 11464 int i, irq_sync = 0, err = 0;
6aa20a22 11465
2c49a44d
MC		 11466 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
11467 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
bc3a9254
MC		 11468 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
11469 (ering->tx_pending <= MAX_SKB_FRAGS) ||
63c3a66f 11470 (tg3_flag(tp, TSO_BUG) &&
bc3a9254 11471 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 11472 return -EINVAL;
6aa20a22 11473
bbe832c0 11474 if (netif_running(dev)) {
b02fd9e3 11475 tg3_phy_stop(tp);
1da177e4 11476 tg3_netif_stop(tp);
bbe832c0
MC		 11477 irq_sync = 1;
11478 }
1da177e4 11479
bbe832c0 11480 tg3_full_lock(tp, irq_sync);
6aa20a22 11481
1da177e4
LT		 11482 tp->rx_pending = ering->rx_pending;
11483
63c3a66f 11484 if (tg3_flag(tp, MAX_RXPEND_64) &&
1da177e4
LT		 11485 tp->rx_pending > 63)
11486 tp->rx_pending = 63;
11487 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd 11488
6fd45cb8 11489 for (i = 0; i < tp->irq_max; i++)
646c9edd 11490 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 11491
11492 if (netif_running(dev)) {
944d980e 11493 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 11494 err = tg3_restart_hw(tp, 1);
11495 if (!err)
11496 tg3_netif_start(tp);
1da177e4
LT		 11497 }
11498
f47c11ee 11499 tg3_full_unlock(tp);
6aa20a22 11500
b02fd9e3
MC		 11501 if (irq_sync && !err)
11502 tg3_phy_start(tp);
11503
b9ec6c1b 11504 return err;
1da177e4 11505}
6aa20a22 11506
1da177e4
LT		 11507static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
11508{
11509 struct tg3 *tp = netdev_priv(dev);
6aa20a22 11510
63c3a66f 11511 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
8d018621 11512
4a2db503 11513 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
8d018621
MC		 11514 epause->rx_pause = 1;
11515 else
11516 epause->rx_pause = 0;
11517
4a2db503 11518 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
8d018621
MC		 11519 epause->tx_pause = 1;
11520 else
11521 epause->tx_pause = 0;
1da177e4 11522}
6aa20a22 11523
1da177e4
LT		 11524static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
11525{
11526 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 11527 int err = 0;
6aa20a22 11528
63c3a66f 11529 if (tg3_flag(tp, USE_PHYLIB)) {
2712168f
MC		 11530 u32 newadv;
11531 struct phy_device *phydev;
1da177e4 11532
2712168f 11533 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
f47c11ee 11534
2712168f
MC		 11535 if (!(phydev->supported & SUPPORTED_Pause) ||
11536 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
2259dca3 11537 (epause->rx_pause != epause->tx_pause)))
2712168f 11538 return -EINVAL;
1da177e4 11539
2712168f
MC		 11540 tp->link_config.flowctrl = 0;
11541 if (epause->rx_pause) {
11542 tp->link_config.flowctrl |= FLOW_CTRL_RX;
11543
11544 if (epause->tx_pause) {
11545 tp->link_config.flowctrl |= FLOW_CTRL_TX;
11546 newadv = ADVERTISED_Pause;
b02fd9e3 11547 } else
2712168f
MC		 11548 newadv = ADVERTISED_Pause |
11549 ADVERTISED_Asym_Pause;
11550 } else if (epause->tx_pause) {
11551 tp->link_config.flowctrl |= FLOW_CTRL_TX;
11552 newadv = ADVERTISED_Asym_Pause;
11553 } else
11554 newadv = 0;
11555
11556 if (epause->autoneg)
63c3a66f 11557 tg3_flag_set(tp, PAUSE_AUTONEG);
2712168f 11558 else
63c3a66f 11559 tg3_flag_clear(tp, PAUSE_AUTONEG);
2712168f 11560
f07e9af3 11561 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2712168f
MC		 11562 u32 oldadv = phydev->advertising &
11563 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
11564 if (oldadv != newadv) {
11565 phydev->advertising &=
11566 ~(ADVERTISED_Pause |
11567 ADVERTISED_Asym_Pause);
11568 phydev->advertising |= newadv;
11569 if (phydev->autoneg) {
11570 /*
11571 * Always renegotiate the link to
11572 * inform our link partner of our
11573 * flow control settings, even if the
11574 * flow control is forced. Let
11575 * tg3_adjust_link() do the final
11576 * flow control setup.
11577 */
11578 return phy_start_aneg(phydev);
b02fd9e3 11579 }
b02fd9e3 11580 }
b02fd9e3 11581
2712168f 11582 if (!epause->autoneg)
b02fd9e3 11583 tg3_setup_flow_control(tp, 0, 0);
2712168f 11584 } else {
c6700ce2 11585 tp->link_config.advertising &=
2712168f
MC		 11586 ~(ADVERTISED_Pause |
11587 ADVERTISED_Asym_Pause);
c6700ce2 11588 tp->link_config.advertising |= newadv;
b02fd9e3
MC		 11589 }
11590 } else {
11591 int irq_sync = 0;
11592
11593 if (netif_running(dev)) {
11594 tg3_netif_stop(tp);
11595 irq_sync = 1;
11596 }
11597
11598 tg3_full_lock(tp, irq_sync);
11599
11600 if (epause->autoneg)
63c3a66f 11601 tg3_flag_set(tp, PAUSE_AUTONEG);
b02fd9e3 11602 else
63c3a66f 11603 tg3_flag_clear(tp, PAUSE_AUTONEG);
b02fd9e3 11604 if (epause->rx_pause)
e18ce346 11605 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 11606 else
e18ce346 11607 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 11608 if (epause->tx_pause)
e18ce346 11609 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 11610 else
e18ce346 11611 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 11612
11613 if (netif_running(dev)) {
11614 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11615 err = tg3_restart_hw(tp, 1);
11616 if (!err)
11617 tg3_netif_start(tp);
11618 }
11619
11620 tg3_full_unlock(tp);
11621 }
6aa20a22 11622
b9ec6c1b 11623 return err;
1da177e4 11624}
6aa20a22 11625
de6f31eb 11626static int tg3_get_sset_count(struct net_device *dev, int sset)
1da177e4 11627{
b9f2c044
JG		 11628 switch (sset) {
11629 case ETH_SS_TEST:
11630 return TG3_NUM_TEST;
11631 case ETH_SS_STATS:
11632 return TG3_NUM_STATS;
11633 default:
11634 return -EOPNOTSUPP;
11635 }
4cafd3f5
MC		 11636}
11637
90415477
MC		 11638static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
11639 u32 *rules __always_unused)
11640{
11641 struct tg3 *tp = netdev_priv(dev);
11642
11643 if (!tg3_flag(tp, SUPPORT_MSIX))
11644 return -EOPNOTSUPP;
11645
11646 switch (info->cmd) {
11647 case ETHTOOL_GRXRINGS:
11648 if (netif_running(tp->dev))
9102426a 11649 info->data = tp->rxq_cnt;
90415477
MC		 11650 else {
11651 info->data = num_online_cpus();
9102426a
MC		 11652 if (info->data > TG3_RSS_MAX_NUM_QS)
11653 info->data = TG3_RSS_MAX_NUM_QS;
90415477
MC		 11654 }
11655
11656 /* The first interrupt vector only
11657 * handles link interrupts.
11658 */
11659 info->data -= 1;
11660 return 0;
11661
11662 default:
11663 return -EOPNOTSUPP;
11664 }
11665}
11666
11667static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
11668{
11669 u32 size = 0;
11670 struct tg3 *tp = netdev_priv(dev);
11671
11672 if (tg3_flag(tp, SUPPORT_MSIX))
11673 size = TG3_RSS_INDIR_TBL_SIZE;
11674
11675 return size;
11676}
11677
11678static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
11679{
11680 struct tg3 *tp = netdev_priv(dev);
11681 int i;
11682
11683 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
11684 indir[i] = tp->rss_ind_tbl[i];
11685
11686 return 0;
11687}
11688
11689static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
11690{
11691 struct tg3 *tp = netdev_priv(dev);
11692 size_t i;
11693
11694 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
11695 tp->rss_ind_tbl[i] = indir[i];
11696
11697 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
11698 return 0;
11699
11700 /* It is legal to write the indirection
11701 * table while the device is running.
11702 */
11703 tg3_full_lock(tp, 0);
11704 tg3_rss_write_indir_tbl(tp);
11705 tg3_full_unlock(tp);
11706
11707 return 0;
11708}
11709
0968169c
MC		 11710static void tg3_get_channels(struct net_device *dev,
11711 struct ethtool_channels *channel)
11712{
11713 struct tg3 *tp = netdev_priv(dev);
11714 u32 deflt_qs = netif_get_num_default_rss_queues();
11715
11716 channel->max_rx = tp->rxq_max;
11717 channel->max_tx = tp->txq_max;
11718
11719 if (netif_running(dev)) {
11720 channel->rx_count = tp->rxq_cnt;
11721 channel->tx_count = tp->txq_cnt;
11722 } else {
11723 if (tp->rxq_req)
11724 channel->rx_count = tp->rxq_req;
11725 else
11726 channel->rx_count = min(deflt_qs, tp->rxq_max);
11727
11728 if (tp->txq_req)
11729 channel->tx_count = tp->txq_req;
11730 else
11731 channel->tx_count = min(deflt_qs, tp->txq_max);
11732 }
11733}
11734
11735static int tg3_set_channels(struct net_device *dev,
11736 struct ethtool_channels *channel)
11737{
11738 struct tg3 *tp = netdev_priv(dev);
11739
11740 if (!tg3_flag(tp, SUPPORT_MSIX))
11741 return -EOPNOTSUPP;
11742
11743 if (channel->rx_count > tp->rxq_max ||
11744 channel->tx_count > tp->txq_max)
11745 return -EINVAL;
11746
11747 tp->rxq_req = channel->rx_count;
11748 tp->txq_req = channel->tx_count;
11749
11750 if (!netif_running(dev))
11751 return 0;
11752
11753 tg3_stop(tp);
11754
f4a46d1f 11755 tg3_carrier_off(tp);
0968169c 11756
be947307 11757 tg3_start(tp, true, false, false);
0968169c
MC		 11758
11759 return 0;
11760}
11761
de6f31eb 11762static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1da177e4
LT		 11763{
11764 switch (stringset) {
11765 case ETH_SS_STATS:
11766 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
11767 break;
4cafd3f5
MC		 11768 case ETH_SS_TEST:
11769 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
11770 break;
1da177e4
LT		 11771 default:
11772 WARN_ON(1); /* we need a WARN() */
11773 break;
11774 }
11775}
11776
81b8709c 11777static int tg3_set_phys_id(struct net_device *dev,
11778 enum ethtool_phys_id_state state)
4009a93d
MC		 11779{
11780 struct tg3 *tp = netdev_priv(dev);
4009a93d
MC		 11781
11782 if (!netif_running(tp->dev))
11783 return -EAGAIN;
11784
81b8709c 11785 switch (state) {
11786 case ETHTOOL_ID_ACTIVE:
fce55922 11787 return 1; /* cycle on/off once per second */
4009a93d 11788
81b8709c 11789 case ETHTOOL_ID_ON:
11790 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
11791 LED_CTRL_1000MBPS_ON |
11792 LED_CTRL_100MBPS_ON |
11793 LED_CTRL_10MBPS_ON |
11794 LED_CTRL_TRAFFIC_OVERRIDE |
11795 LED_CTRL_TRAFFIC_BLINK |
11796 LED_CTRL_TRAFFIC_LED);
11797 break;
6aa20a22 11798
81b8709c 11799 case ETHTOOL_ID_OFF:
11800 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
11801 LED_CTRL_TRAFFIC_OVERRIDE);
11802 break;
4009a93d 11803
81b8709c 11804 case ETHTOOL_ID_INACTIVE:
11805 tw32(MAC_LED_CTRL, tp->led_ctrl);
11806 break;
4009a93d 11807 }
81b8709c 11808
4009a93d
MC		 11809 return 0;
11810}
11811
de6f31eb 11812static void tg3_get_ethtool_stats(struct net_device *dev,
1da177e4
LT		 11813 struct ethtool_stats *estats, u64 *tmp_stats)
11814{
11815 struct tg3 *tp = netdev_priv(dev);
0e6c9da3 11816
b546e46f
MC		 11817 if (tp->hw_stats)
11818 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
11819 else
11820 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
1da177e4
LT		 11821}
11822
535a490e 11823static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
c3e94500
MC		 11824{
11825 int i;
11826 __be32 *buf;
11827 u32 offset = 0, len = 0;
11828 u32 magic, val;
11829
63c3a66f 11830 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
c3e94500
MC		 11831 return NULL;
11832
11833 if (magic == TG3_EEPROM_MAGIC) {
11834 for (offset = TG3_NVM_DIR_START;
11835 offset < TG3_NVM_DIR_END;
11836 offset += TG3_NVM_DIRENT_SIZE) {
11837 if (tg3_nvram_read(tp, offset, &val))
11838 return NULL;
11839
11840 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
11841 TG3_NVM_DIRTYPE_EXTVPD)
11842 break;
11843 }
11844
11845 if (offset != TG3_NVM_DIR_END) {
11846 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
11847 if (tg3_nvram_read(tp, offset + 4, &offset))
11848 return NULL;
11849
11850 offset = tg3_nvram_logical_addr(tp, offset);
11851 }
11852 }
11853
11854 if (!offset || !len) {
11855 offset = TG3_NVM_VPD_OFF;
11856 len = TG3_NVM_VPD_LEN;
11857 }
11858
11859 buf = kmalloc(len, GFP_KERNEL);
11860 if (buf == NULL)
11861 return NULL;
11862
11863 if (magic == TG3_EEPROM_MAGIC) {
11864 for (i = 0; i < len; i += 4) {
11865 /* The data is in little-endian format in NVRAM.
11866 * Use the big-endian read routines to preserve
11867 * the byte order as it exists in NVRAM.
11868 */
11869 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
11870 goto error;
11871 }
11872 } else {
11873 u8 *ptr;
11874 ssize_t cnt;
11875 unsigned int pos = 0;
11876
11877 ptr = (u8 *)&buf[0];
11878 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
11879 cnt = pci_read_vpd(tp->pdev, pos,
11880 len - pos, ptr);
11881 if (cnt == -ETIMEDOUT || cnt == -EINTR)
11882 cnt = 0;
11883 else if (cnt < 0)
11884 goto error;
11885 }
11886 if (pos != len)
11887 goto error;
11888 }
11889
535a490e
MC		 11890 *vpdlen = len;
11891
c3e94500
MC		 11892 return buf;
11893
11894error:
11895 kfree(buf);
11896 return NULL;
11897}
11898
566f86ad 11899#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 11900#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
11901#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
11902#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
727a6d9f
MC		 11903#define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
11904#define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
bda18faf 11905#define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
b16250e3
MC		 11906#define NVRAM_SELFBOOT_HW_SIZE 0x20
11907#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 11908
11909static int tg3_test_nvram(struct tg3 *tp)
11910{
535a490e 11911 u32 csum, magic, len;
a9dc529d 11912 __be32 *buf;
ab0049b4 11913 int i, j, k, err = 0, size;
566f86ad 11914
63c3a66f 11915 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 11916 return 0;
11917
e4f34110 11918 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 11919 return -EIO;
11920
1b27777a
MC		 11921 if (magic == TG3_EEPROM_MAGIC)
11922 size = NVRAM_TEST_SIZE;
b16250e3 11923 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 11924 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
11925 TG3_EEPROM_SB_FORMAT_1) {
11926 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
11927 case TG3_EEPROM_SB_REVISION_0:
11928 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
11929 break;
11930 case TG3_EEPROM_SB_REVISION_2:
11931 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
11932 break;
11933 case TG3_EEPROM_SB_REVISION_3:
11934 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
11935 break;
727a6d9f
MC		 11936 case TG3_EEPROM_SB_REVISION_4:
11937 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
11938 break;
11939 case TG3_EEPROM_SB_REVISION_5:
11940 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
11941 break;
11942 case TG3_EEPROM_SB_REVISION_6:
11943 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
11944 break;
a5767dec 11945 default:
727a6d9f 11946 return -EIO;
a5767dec
MC		 11947 }
11948 } else
1b27777a 11949 return 0;
b16250e3
MC		 11950 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11951 size = NVRAM_SELFBOOT_HW_SIZE;
11952 else
1b27777a
MC		 11953 return -EIO;
11954
11955 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 11956 if (buf == NULL)
11957 return -ENOMEM;
11958
1b27777a
MC		 11959 err = -EIO;
11960 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 11961 err = tg3_nvram_read_be32(tp, i, &buf[j]);
11962 if (err)
566f86ad 11963 break;
566f86ad 11964 }
1b27777a 11965 if (i < size)
566f86ad
MC		 11966 goto out;
11967
1b27777a 11968 /* Selfboot format */
a9dc529d 11969 magic = be32_to_cpu(buf[0]);
b9fc7dc5 11970 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 11971 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 11972 u8 *buf8 = (u8 *) buf, csum8 = 0;
11973
b9fc7dc5 11974 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 11975 TG3_EEPROM_SB_REVISION_2) {
11976 /* For rev 2, the csum doesn't include the MBA. */
11977 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
11978 csum8 += buf8[i];
11979 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
11980 csum8 += buf8[i];
11981 } else {
11982 for (i = 0; i < size; i++)
11983 csum8 += buf8[i];
11984 }
1b27777a 11985
ad96b485
AB		 11986 if (csum8 == 0) {
11987 err = 0;
11988 goto out;
11989 }
11990
11991 err = -EIO;
11992 goto out;
1b27777a 11993 }
566f86ad 11994
b9fc7dc5 11995 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 11996 TG3_EEPROM_MAGIC_HW) {
11997 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 11998 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 11999 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 12000
12001 /* Separate the parity bits and the data bytes. */
12002 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12003 if ((i == 0) || (i == 8)) {
12004 int l;
12005 u8 msk;
12006
12007 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12008 parity[k++] = buf8[i] & msk;
12009 i++;
859a5887 12010 } else if (i == 16) {
b16250e3
MC		 12011 int l;
12012 u8 msk;
12013
12014 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12015 parity[k++] = buf8[i] & msk;
12016 i++;
12017
12018 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12019 parity[k++] = buf8[i] & msk;
12020 i++;
12021 }
12022 data[j++] = buf8[i];
12023 }
12024
12025 err = -EIO;
12026 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12027 u8 hw8 = hweight8(data[i]);
12028
12029 if ((hw8 & 0x1) && parity[i])
12030 goto out;
12031 else if (!(hw8 & 0x1) && !parity[i])
12032 goto out;
12033 }
12034 err = 0;
12035 goto out;
12036 }
12037
01c3a392
MC		 12038 err = -EIO;
12039
566f86ad
MC		 12040 /* Bootstrap checksum at offset 0x10 */
12041 csum = calc_crc((unsigned char *) buf, 0x10);
01c3a392 12042 if (csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 12043 goto out;
12044
12045 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12046 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
01c3a392 12047 if (csum != le32_to_cpu(buf[0xfc/4]))
a9dc529d 12048 goto out;
566f86ad 12049
c3e94500
MC		 12050 kfree(buf);
12051
535a490e 12052 buf = tg3_vpd_readblock(tp, &len);
c3e94500
MC		 12053 if (!buf)
12054 return -ENOMEM;
d4894f3e 12055
535a490e 12056 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
d4894f3e
MC		 12057 if (i > 0) {
12058 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12059 if (j < 0)
12060 goto out;
12061
535a490e 12062 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
d4894f3e
MC		 12063 goto out;
12064
12065 i += PCI_VPD_LRDT_TAG_SIZE;
12066 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12067 PCI_VPD_RO_KEYWORD_CHKSUM);
12068 if (j > 0) {
12069 u8 csum8 = 0;
12070
12071 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12072
12073 for (i = 0; i <= j; i++)
12074 csum8 += ((u8 *)buf)[i];
12075
12076 if (csum8)
12077 goto out;
12078 }
12079 }
12080
566f86ad
MC		 12081 err = 0;
12082
12083out:
12084 kfree(buf);
12085 return err;
12086}
12087
ca43007a
MC		 12088#define TG3_SERDES_TIMEOUT_SEC 2
12089#define TG3_COPPER_TIMEOUT_SEC 6
12090
12091static int tg3_test_link(struct tg3 *tp)
12092{
12093 int i, max;
12094
12095 if (!netif_running(tp->dev))
12096 return -ENODEV;
12097
f07e9af3 12098 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
ca43007a
MC		 12099 max = TG3_SERDES_TIMEOUT_SEC;
12100 else
12101 max = TG3_COPPER_TIMEOUT_SEC;
12102
12103 for (i = 0; i < max; i++) {
f4a46d1f 12104 if (tp->link_up)
ca43007a
MC		 12105 return 0;
12106
12107 if (msleep_interruptible(1000))
12108 break;
12109 }
12110
12111 return -EIO;
12112}
12113
a71116d1 12114/* Only test the commonly used registers */
30ca3e37 12115static int tg3_test_registers(struct tg3 *tp)
a71116d1 12116{
b16250e3 12117 int i, is_5705, is_5750;
a71116d1
MC		 12118 u32 offset, read_mask, write_mask, val, save_val, read_val;
12119 static struct {
12120 u16 offset;
12121 u16 flags;
12122#define TG3_FL_5705 0x1
12123#define TG3_FL_NOT_5705 0x2
12124#define TG3_FL_NOT_5788 0x4
b16250e3 12125#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 12126 u32 read_mask;
12127 u32 write_mask;
12128 } reg_tbl[] = {
12129 /* MAC Control Registers */
12130 { MAC_MODE, TG3_FL_NOT_5705,
12131 0x00000000, 0x00ef6f8c },
12132 { MAC_MODE, TG3_FL_5705,
12133 0x00000000, 0x01ef6b8c },
12134 { MAC_STATUS, TG3_FL_NOT_5705,
12135 0x03800107, 0x00000000 },
12136 { MAC_STATUS, TG3_FL_5705,
12137 0x03800100, 0x00000000 },
12138 { MAC_ADDR_0_HIGH, 0x0000,
12139 0x00000000, 0x0000ffff },
12140 { MAC_ADDR_0_LOW, 0x0000,
c6cdf436 12141 0x00000000, 0xffffffff },
a71116d1
MC		 12142 { MAC_RX_MTU_SIZE, 0x0000,
12143 0x00000000, 0x0000ffff },
12144 { MAC_TX_MODE, 0x0000,
12145 0x00000000, 0x00000070 },
12146 { MAC_TX_LENGTHS, 0x0000,
12147 0x00000000, 0x00003fff },
12148 { MAC_RX_MODE, TG3_FL_NOT_5705,
12149 0x00000000, 0x000007fc },
12150 { MAC_RX_MODE, TG3_FL_5705,
12151 0x00000000, 0x000007dc },
12152 { MAC_HASH_REG_0, 0x0000,
12153 0x00000000, 0xffffffff },
12154 { MAC_HASH_REG_1, 0x0000,
12155 0x00000000, 0xffffffff },
12156 { MAC_HASH_REG_2, 0x0000,
12157 0x00000000, 0xffffffff },
12158 { MAC_HASH_REG_3, 0x0000,
12159 0x00000000, 0xffffffff },
12160
12161 /* Receive Data and Receive BD Initiator Control Registers. */
12162 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
12163 0x00000000, 0xffffffff },
12164 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
12165 0x00000000, 0xffffffff },
12166 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
12167 0x00000000, 0x00000003 },
12168 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
12169 0x00000000, 0xffffffff },
12170 { RCVDBDI_STD_BD+0, 0x0000,
12171 0x00000000, 0xffffffff },
12172 { RCVDBDI_STD_BD+4, 0x0000,
12173 0x00000000, 0xffffffff },
12174 { RCVDBDI_STD_BD+8, 0x0000,
12175 0x00000000, 0xffff0002 },
12176 { RCVDBDI_STD_BD+0xc, 0x0000,
12177 0x00000000, 0xffffffff },
6aa20a22 12178
a71116d1
MC		 12179 /* Receive BD Initiator Control Registers. */
12180 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
12181 0x00000000, 0xffffffff },
12182 { RCVBDI_STD_THRESH, TG3_FL_5705,
12183 0x00000000, 0x000003ff },
12184 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
12185 0x00000000, 0xffffffff },
6aa20a22 12186
a71116d1
MC		 12187 /* Host Coalescing Control Registers. */
12188 { HOSTCC_MODE, TG3_FL_NOT_5705,
12189 0x00000000, 0x00000004 },
12190 { HOSTCC_MODE, TG3_FL_5705,
12191 0x00000000, 0x000000f6 },
12192 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
12193 0x00000000, 0xffffffff },
12194 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
12195 0x00000000, 0x000003ff },
12196 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
12197 0x00000000, 0xffffffff },
12198 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
12199 0x00000000, 0x000003ff },
12200 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
12201 0x00000000, 0xffffffff },
12202 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12203 0x00000000, 0x000000ff },
12204 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
12205 0x00000000, 0xffffffff },
12206 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12207 0x00000000, 0x000000ff },
12208 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
12209 0x00000000, 0xffffffff },
12210 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
12211 0x00000000, 0xffffffff },
12212 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12213 0x00000000, 0xffffffff },
12214 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12215 0x00000000, 0x000000ff },
12216 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12217 0x00000000, 0xffffffff },
12218 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12219 0x00000000, 0x000000ff },
12220 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
12221 0x00000000, 0xffffffff },
12222 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
12223 0x00000000, 0xffffffff },
12224 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
12225 0x00000000, 0xffffffff },
12226 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
12227 0x00000000, 0xffffffff },
12228 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
12229 0x00000000, 0xffffffff },
12230 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
12231 0xffffffff, 0x00000000 },
12232 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
12233 0xffffffff, 0x00000000 },
12234
12235 /* Buffer Manager Control Registers. */
b16250e3 12236 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 12237 0x00000000, 0x007fff80 },
b16250e3 12238 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 12239 0x00000000, 0x007fffff },
12240 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
12241 0x00000000, 0x0000003f },
12242 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
12243 0x00000000, 0x000001ff },
12244 { BUFMGR_MB_HIGH_WATER, 0x0000,
12245 0x00000000, 0x000001ff },
12246 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
12247 0xffffffff, 0x00000000 },
12248 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
12249 0xffffffff, 0x00000000 },
6aa20a22 12250
a71116d1
MC		 12251 /* Mailbox Registers */
12252 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
12253 0x00000000, 0x000001ff },
12254 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
12255 0x00000000, 0x000001ff },
12256 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
12257 0x00000000, 0x000007ff },
12258 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
12259 0x00000000, 0x000001ff },
12260
12261 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
12262 };
12263
b16250e3 12264 is_5705 = is_5750 = 0;
63c3a66f 12265 if (tg3_flag(tp, 5705_PLUS)) {
a71116d1 12266 is_5705 = 1;
63c3a66f 12267 if (tg3_flag(tp, 5750_PLUS))
b16250e3
MC		 12268 is_5750 = 1;
12269 }
a71116d1
MC		 12270
12271 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
12272 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
12273 continue;
12274
12275 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
12276 continue;
12277
63c3a66f 12278 if (tg3_flag(tp, IS_5788) &&
a71116d1
MC		 12279 (reg_tbl[i].flags & TG3_FL_NOT_5788))
12280 continue;
12281
b16250e3
MC		 12282 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
12283 continue;
12284
a71116d1
MC		 12285 offset = (u32) reg_tbl[i].offset;
12286 read_mask = reg_tbl[i].read_mask;
12287 write_mask = reg_tbl[i].write_mask;
12288
12289 /* Save the original register content */
12290 save_val = tr32(offset);
12291
12292 /* Determine the read-only value. */
12293 read_val = save_val & read_mask;
12294
12295 /* Write zero to the register, then make sure the read-only bits
12296 * are not changed and the read/write bits are all zeros.
12297 */
12298 tw32(offset, 0);
12299
12300 val = tr32(offset);
12301
12302 /* Test the read-only and read/write bits. */
12303 if (((val & read_mask) != read_val) || (val & write_mask))
12304 goto out;
12305
12306 /* Write ones to all the bits defined by RdMask and WrMask, then
12307 * make sure the read-only bits are not changed and the
12308 * read/write bits are all ones.
12309 */
12310 tw32(offset, read_mask | write_mask);
12311
12312 val = tr32(offset);
12313
12314 /* Test the read-only bits. */
12315 if ((val & read_mask) != read_val)
12316 goto out;
12317
12318 /* Test the read/write bits. */
12319 if ((val & write_mask) != write_mask)
12320 goto out;
12321
12322 tw32(offset, save_val);
12323 }
12324
12325 return 0;
12326
12327out:
9f88f29f 12328 if (netif_msg_hw(tp))
2445e461
MC		 12329 netdev_err(tp->dev,
12330 "Register test failed at offset %x\n", offset);
a71116d1
MC		 12331 tw32(offset, save_val);
12332 return -EIO;
12333}
12334
7942e1db
MC		 12335static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
12336{
f71e1309 12337 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 12338 int i;
12339 u32 j;
12340
e9edda69 12341 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 12342 for (j = 0; j < len; j += 4) {
12343 u32 val;
12344
12345 tg3_write_mem(tp, offset + j, test_pattern[i]);
12346 tg3_read_mem(tp, offset + j, &val);
12347 if (val != test_pattern[i])
12348 return -EIO;
12349 }
12350 }
12351 return 0;
12352}
12353
12354static int tg3_test_memory(struct tg3 *tp)
12355{
12356 static struct mem_entry {
12357 u32 offset;
12358 u32 len;
12359 } mem_tbl_570x[] = {
38690194 12360 { 0x00000000, 0x00b50},
7942e1db
MC		 12361 { 0x00002000, 0x1c000},
12362 { 0xffffffff, 0x00000}
12363 }, mem_tbl_5705[] = {
12364 { 0x00000100, 0x0000c},
12365 { 0x00000200, 0x00008},
7942e1db
MC		 12366 { 0x00004000, 0x00800},
12367 { 0x00006000, 0x01000},
12368 { 0x00008000, 0x02000},
12369 { 0x00010000, 0x0e000},
12370 { 0xffffffff, 0x00000}
79f4d13a
MC		 12371 }, mem_tbl_5755[] = {
12372 { 0x00000200, 0x00008},
12373 { 0x00004000, 0x00800},
12374 { 0x00006000, 0x00800},
12375 { 0x00008000, 0x02000},
12376 { 0x00010000, 0x0c000},
12377 { 0xffffffff, 0x00000}
b16250e3
MC		 12378 }, mem_tbl_5906[] = {
12379 { 0x00000200, 0x00008},
12380 { 0x00004000, 0x00400},
12381 { 0x00006000, 0x00400},
12382 { 0x00008000, 0x01000},
12383 { 0x00010000, 0x01000},
12384 { 0xffffffff, 0x00000}
8b5a6c42
MC		 12385 }, mem_tbl_5717[] = {
12386 { 0x00000200, 0x00008},
12387 { 0x00010000, 0x0a000},
12388 { 0x00020000, 0x13c00},
12389 { 0xffffffff, 0x00000}
12390 }, mem_tbl_57765[] = {
12391 { 0x00000200, 0x00008},
12392 { 0x00004000, 0x00800},
12393 { 0x00006000, 0x09800},
12394 { 0x00010000, 0x0a000},
12395 { 0xffffffff, 0x00000}
7942e1db
MC		 12396 };
12397 struct mem_entry *mem_tbl;
12398 int err = 0;
12399 int i;
12400
63c3a66f 12401 if (tg3_flag(tp, 5717_PLUS))
8b5a6c42 12402 mem_tbl = mem_tbl_5717;
c65a17f4
MC		 12403 else if (tg3_flag(tp, 57765_CLASS) ||
12404 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762)
8b5a6c42 12405 mem_tbl = mem_tbl_57765;
63c3a66f 12406 else if (tg3_flag(tp, 5755_PLUS))
321d32a0
MC		 12407 mem_tbl = mem_tbl_5755;
12408 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12409 mem_tbl = mem_tbl_5906;
63c3a66f 12410 else if (tg3_flag(tp, 5705_PLUS))
321d32a0
MC		 12411 mem_tbl = mem_tbl_5705;
12412 else
7942e1db
MC		 12413 mem_tbl = mem_tbl_570x;
12414
12415 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
be98da6a
MC		 12416 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
12417 if (err)
7942e1db
MC		 12418 break;
12419 }
6aa20a22 12420
7942e1db
MC		 12421 return err;
12422}
12423
bb158d69
MC		 12424#define TG3_TSO_MSS 500
12425
12426#define TG3_TSO_IP_HDR_LEN 20
12427#define TG3_TSO_TCP_HDR_LEN 20
12428#define TG3_TSO_TCP_OPT_LEN 12
12429
12430static const u8 tg3_tso_header[] = {
124310x08, 0x00,
124320x45, 0x00, 0x00, 0x00,
124330x00, 0x00, 0x40, 0x00,
124340x40, 0x06, 0x00, 0x00,
124350x0a, 0x00, 0x00, 0x01,
124360x0a, 0x00, 0x00, 0x02,
124370x0d, 0x00, 0xe0, 0x00,
124380x00, 0x00, 0x01, 0x00,
124390x00, 0x00, 0x02, 0x00,
124400x80, 0x10, 0x10, 0x00,
124410x14, 0x09, 0x00, 0x00,
124420x01, 0x01, 0x08, 0x0a,
124430x11, 0x11, 0x11, 0x11,
124440x11, 0x11, 0x11, 0x11,
12445};
9f40dead 12446
28a45957 12447static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
c76949a6 12448{
5e5a7f37 12449 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
bb158d69 12450 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
84b67b27 12451 u32 budget;
9205fd9c
ED		 12452 struct sk_buff *skb;
12453 u8 *tx_data, *rx_data;
c76949a6
MC		 12454 dma_addr_t map;
12455 int num_pkts, tx_len, rx_len, i, err;
12456 struct tg3_rx_buffer_desc *desc;
898a56f8 12457 struct tg3_napi *tnapi, *rnapi;
8fea32b9 12458 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
c76949a6 12459
c8873405
MC		 12460 tnapi = &tp->napi[0];
12461 rnapi = &tp->napi[0];
0c1d0e2b 12462 if (tp->irq_cnt > 1) {
63c3a66f 12463 if (tg3_flag(tp, ENABLE_RSS))
1da85aa3 12464 rnapi = &tp->napi[1];
63c3a66f 12465 if (tg3_flag(tp, ENABLE_TSS))
c8873405 12466 tnapi = &tp->napi[1];
0c1d0e2b 12467 }
fd2ce37f 12468 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 12469
c76949a6
MC		 12470 err = -EIO;
12471
4852a861 12472 tx_len = pktsz;
a20e9c62 12473 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 12474 if (!skb)
12475 return -ENOMEM;
12476
c76949a6
MC		 12477 tx_data = skb_put(skb, tx_len);
12478 memcpy(tx_data, tp->dev->dev_addr, 6);
12479 memset(tx_data + 6, 0x0, 8);
12480
4852a861 12481 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
c76949a6 12482
28a45957 12483 if (tso_loopback) {
bb158d69
MC		 12484 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
12485
12486 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
12487 TG3_TSO_TCP_OPT_LEN;
12488
12489 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
12490 sizeof(tg3_tso_header));
12491 mss = TG3_TSO_MSS;
12492
12493 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
12494 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
12495
12496 /* Set the total length field in the IP header */
12497 iph->tot_len = htons((u16)(mss + hdr_len));
12498
12499 base_flags = (TXD_FLAG_CPU_PRE_DMA |
12500 TXD_FLAG_CPU_POST_DMA);
12501
63c3a66f
JP		 12502 if (tg3_flag(tp, HW_TSO_1) ||
12503 tg3_flag(tp, HW_TSO_2) ||
12504 tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 12505 struct tcphdr *th;
12506 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
12507 th = (struct tcphdr *)&tx_data[val];
12508 th->check = 0;
12509 } else
12510 base_flags |= TXD_FLAG_TCPUDP_CSUM;
12511
63c3a66f 12512 if (tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 12513 mss |= (hdr_len & 0xc) << 12;
12514 if (hdr_len & 0x10)
12515 base_flags |= 0x00000010;
12516 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 12517 } else if (tg3_flag(tp, HW_TSO_2))
bb158d69 12518 mss |= hdr_len << 9;
63c3a66f 12519 else if (tg3_flag(tp, HW_TSO_1) ||
bb158d69
MC		 12520 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
12521 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
12522 } else {
12523 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
12524 }
12525
12526 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
12527 } else {
12528 num_pkts = 1;
12529 data_off = ETH_HLEN;
c441b456
MC		 12530
12531 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
12532 tx_len > VLAN_ETH_FRAME_LEN)
12533 base_flags |= TXD_FLAG_JMB_PKT;
bb158d69
MC		 12534 }
12535
12536 for (i = data_off; i < tx_len; i++)
c76949a6
MC		 12537 tx_data[i] = (u8) (i & 0xff);
12538
f4188d8a
AD		 12539 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
12540 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 12541 dev_kfree_skb(skb);
12542 return -EIO;
12543 }
c76949a6 12544
0d681b27
MC		 12545 val = tnapi->tx_prod;
12546 tnapi->tx_buffers[val].skb = skb;
12547 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
12548
c76949a6 12549 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 12550 rnapi->coal_now);
c76949a6
MC		 12551
12552 udelay(10);
12553
898a56f8 12554 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 12555
84b67b27
MC		 12556 budget = tg3_tx_avail(tnapi);
12557 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
d1a3b737
MC		 12558 base_flags | TXD_FLAG_END, mss, 0)) {
12559 tnapi->tx_buffers[val].skb = NULL;
12560 dev_kfree_skb(skb);
12561 return -EIO;
12562 }
c76949a6 12563
f3f3f27e 12564 tnapi->tx_prod++;
c76949a6 12565
6541b806
MC		 12566 /* Sync BD data before updating mailbox */
12567 wmb();
12568
f3f3f27e
MC		 12569 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
12570 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 12571
12572 udelay(10);
12573
303fc921
MC		 12574 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
12575 for (i = 0; i < 35; i++) {
c76949a6 12576 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 12577 coal_now);
c76949a6
MC		 12578
12579 udelay(10);
12580
898a56f8
MC		 12581 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
12582 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 12583 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 12584 (rx_idx == (rx_start_idx + num_pkts)))
12585 break;
12586 }
12587
ba1142e4 12588 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
c76949a6
MC		 12589 dev_kfree_skb(skb);
12590
f3f3f27e 12591 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 12592 goto out;
12593
12594 if (rx_idx != rx_start_idx + num_pkts)
12595 goto out;
12596
bb158d69
MC		 12597 val = data_off;
12598 while (rx_idx != rx_start_idx) {
12599 desc = &rnapi->rx_rcb[rx_start_idx++];
12600 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
12601 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
c76949a6 12602
bb158d69
MC		 12603 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
12604 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
12605 goto out;
c76949a6 12606
bb158d69
MC		 12607 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
12608 - ETH_FCS_LEN;
c76949a6 12609
28a45957 12610 if (!tso_loopback) {
bb158d69
MC		 12611 if (rx_len != tx_len)
12612 goto out;
4852a861 12613
bb158d69
MC		 12614 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
12615 if (opaque_key != RXD_OPAQUE_RING_STD)
12616 goto out;
12617 } else {
12618 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
12619 goto out;
12620 }
12621 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
12622 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
54e0a67f 12623 >> RXD_TCPCSUM_SHIFT != 0xffff) {
4852a861 12624 goto out;
bb158d69 12625 }
4852a861 12626
bb158d69 12627 if (opaque_key == RXD_OPAQUE_RING_STD) {
9205fd9c 12628 rx_data = tpr->rx_std_buffers[desc_idx].data;
bb158d69
MC		 12629 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
12630 mapping);
12631 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
9205fd9c 12632 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
bb158d69
MC		 12633 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
12634 mapping);
12635 } else
12636 goto out;
c76949a6 12637
bb158d69
MC		 12638 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
12639 PCI_DMA_FROMDEVICE);
c76949a6 12640
9205fd9c 12641 rx_data += TG3_RX_OFFSET(tp);
bb158d69 12642 for (i = data_off; i < rx_len; i++, val++) {
9205fd9c 12643 if (*(rx_data + i) != (u8) (val & 0xff))
bb158d69
MC		 12644 goto out;
12645 }
c76949a6 12646 }
bb158d69 12647
c76949a6 12648 err = 0;
6aa20a22 12649
9205fd9c 12650 /* tg3_free_rings will unmap and free the rx_data */
c76949a6
MC		 12651out:
12652 return err;
12653}
12654
00c266b7
MC		 12655#define TG3_STD_LOOPBACK_FAILED 1
12656#define TG3_JMB_LOOPBACK_FAILED 2
bb158d69 12657#define TG3_TSO_LOOPBACK_FAILED 4
28a45957
MC		 12658#define TG3_LOOPBACK_FAILED \
12659 (TG3_STD_LOOPBACK_FAILED | \
12660 TG3_JMB_LOOPBACK_FAILED | \
12661 TG3_TSO_LOOPBACK_FAILED)
00c266b7 12662
941ec90f 12663static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
9f40dead 12664{
28a45957 12665 int err = -EIO;
2215e24c 12666 u32 eee_cap;
c441b456
MC		 12667 u32 jmb_pkt_sz = 9000;
12668
12669 if (tp->dma_limit)
12670 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
9f40dead 12671
ab789046
MC		 12672 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
12673 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
12674
28a45957 12675 if (!netif_running(tp->dev)) {
93df8b8f
NNS		 12676 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
12677 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 12678 if (do_extlpbk)
93df8b8f 12679 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
28a45957
MC		 12680 goto done;
12681 }
12682
b9ec6c1b 12683 err = tg3_reset_hw(tp, 1);
ab789046 12684 if (err) {
93df8b8f
NNS		 12685 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
12686 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 12687 if (do_extlpbk)
93df8b8f 12688 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
ab789046
MC		 12689 goto done;
12690 }
9f40dead 12691
63c3a66f 12692 if (tg3_flag(tp, ENABLE_RSS)) {
4a85f098
MC		 12693 int i;
12694
12695 /* Reroute all rx packets to the 1st queue */
12696 for (i = MAC_RSS_INDIR_TBL_0;
12697 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
12698 tw32(i, 0x0);
12699 }
12700
6e01b20b
MC		 12701 /* HW errata - mac loopback fails in some cases on 5780.
12702 * Normal traffic and PHY loopback are not affected by
12703 * errata. Also, the MAC loopback test is deprecated for
12704 * all newer ASIC revisions.
12705 */
12706 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
12707 !tg3_flag(tp, CPMU_PRESENT)) {
12708 tg3_mac_loopback(tp, true);
9936bcf6 12709
28a45957 12710 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 12711 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
6e01b20b
MC		 12712
12713 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 12714 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 12715 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
6e01b20b
MC		 12716
12717 tg3_mac_loopback(tp, false);
12718 }
4852a861 12719
f07e9af3 12720 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
63c3a66f 12721 !tg3_flag(tp, USE_PHYLIB)) {
5e5a7f37
MC		 12722 int i;
12723
941ec90f 12724 tg3_phy_lpbk_set(tp, 0, false);
5e5a7f37
MC		 12725
12726 /* Wait for link */
12727 for (i = 0; i < 100; i++) {
12728 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
12729 break;
12730 mdelay(1);
12731 }
12732
28a45957 12733 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 12734 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
63c3a66f 12735 if (tg3_flag(tp, TSO_CAPABLE) &&
28a45957 12736 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f 12737 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
63c3a66f 12738 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 12739 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 12740 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
9f40dead 12741
941ec90f
MC		 12742 if (do_extlpbk) {
12743 tg3_phy_lpbk_set(tp, 0, true);
12744
12745 /* All link indications report up, but the hardware
12746 * isn't really ready for about 20 msec. Double it
12747 * to be sure.
12748 */
12749 mdelay(40);
12750
12751 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f
NNS		 12752 data[TG3_EXT_LOOPB_TEST] |=
12753 TG3_STD_LOOPBACK_FAILED;
941ec90f
MC		 12754 if (tg3_flag(tp, TSO_CAPABLE) &&
12755 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f
NNS		 12756 data[TG3_EXT_LOOPB_TEST] |=
12757 TG3_TSO_LOOPBACK_FAILED;
941ec90f 12758 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 12759 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f
NNS		 12760 data[TG3_EXT_LOOPB_TEST] |=
12761 TG3_JMB_LOOPBACK_FAILED;
941ec90f
MC		 12762 }
12763
5e5a7f37
MC		 12764 /* Re-enable gphy autopowerdown. */
12765 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
12766 tg3_phy_toggle_apd(tp, true);
12767 }
6833c043 12768
93df8b8f
NNS		 12769 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
12770 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
28a45957 12771
ab789046
MC		 12772done:
12773 tp->phy_flags |= eee_cap;
12774
9f40dead
MC		 12775 return err;
12776}
12777
4cafd3f5
MC		 12778static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
12779 u64 *data)
12780{
566f86ad 12781 struct tg3 *tp = netdev_priv(dev);
941ec90f 12782 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
566f86ad 12783
bed9829f
MC		 12784 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
12785 tg3_power_up(tp)) {
12786 etest->flags |= ETH_TEST_FL_FAILED;
12787 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
12788 return;
12789 }
bc1c7567 12790
566f86ad
MC		 12791 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
12792
12793 if (tg3_test_nvram(tp) != 0) {
12794 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 12795 data[TG3_NVRAM_TEST] = 1;
566f86ad 12796 }
941ec90f 12797 if (!doextlpbk && tg3_test_link(tp)) {
ca43007a 12798 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 12799 data[TG3_LINK_TEST] = 1;
ca43007a 12800 }
a71116d1 12801 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 12802 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 12803
12804 if (netif_running(dev)) {
b02fd9e3 12805 tg3_phy_stop(tp);
a71116d1 12806 tg3_netif_stop(tp);
bbe832c0
MC		 12807 irq_sync = 1;
12808 }
a71116d1 12809
bbe832c0 12810 tg3_full_lock(tp, irq_sync);
a71116d1 12811 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 12812 err = tg3_nvram_lock(tp);
a71116d1 12813 tg3_halt_cpu(tp, RX_CPU_BASE);
63c3a66f 12814 if (!tg3_flag(tp, 5705_PLUS))
a71116d1 12815 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 12816 if (!err)
12817 tg3_nvram_unlock(tp);
a71116d1 12818
f07e9af3 12819 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
d9ab5ad1
MC		 12820 tg3_phy_reset(tp);
12821
a71116d1
MC		 12822 if (tg3_test_registers(tp) != 0) {
12823 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 12824 data[TG3_REGISTER_TEST] = 1;
a71116d1 12825 }
28a45957 12826
7942e1db
MC		 12827 if (tg3_test_memory(tp) != 0) {
12828 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 12829 data[TG3_MEMORY_TEST] = 1;
7942e1db 12830 }
28a45957 12831
941ec90f
MC		 12832 if (doextlpbk)
12833 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
12834
93df8b8f 12835 if (tg3_test_loopback(tp, data, doextlpbk))
c76949a6 12836 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 12837
f47c11ee
DM		 12838 tg3_full_unlock(tp);
12839
d4bc3927
MC		 12840 if (tg3_test_interrupt(tp) != 0) {
12841 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 12842 data[TG3_INTERRUPT_TEST] = 1;
d4bc3927 12843 }
f47c11ee
DM		 12844
12845 tg3_full_lock(tp, 0);
d4bc3927 12846
a71116d1
MC		 12847 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12848 if (netif_running(dev)) {
63c3a66f 12849 tg3_flag_set(tp, INIT_COMPLETE);
b02fd9e3
MC		 12850 err2 = tg3_restart_hw(tp, 1);
12851 if (!err2)
b9ec6c1b 12852 tg3_netif_start(tp);
a71116d1 12853 }
f47c11ee
DM		 12854
12855 tg3_full_unlock(tp);
b02fd9e3
MC		 12856
12857 if (irq_sync && !err2)
12858 tg3_phy_start(tp);
a71116d1 12859 }
80096068 12860 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
c866b7ea 12861 tg3_power_down(tp);
bc1c7567 12862
4cafd3f5
MC		 12863}
12864
0a633ac2
MC		 12865static int tg3_hwtstamp_ioctl(struct net_device *dev,
12866 struct ifreq *ifr, int cmd)
12867{
12868 struct tg3 *tp = netdev_priv(dev);
12869 struct hwtstamp_config stmpconf;
12870
12871 if (!tg3_flag(tp, PTP_CAPABLE))
12872 return -EINVAL;
12873
12874 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
12875 return -EFAULT;
12876
12877 if (stmpconf.flags)
12878 return -EINVAL;
12879
12880 switch (stmpconf.tx_type) {
12881 case HWTSTAMP_TX_ON:
12882 tg3_flag_set(tp, TX_TSTAMP_EN);
12883 break;
12884 case HWTSTAMP_TX_OFF:
12885 tg3_flag_clear(tp, TX_TSTAMP_EN);
12886 break;
12887 default:
12888 return -ERANGE;
12889 }
12890
12891 switch (stmpconf.rx_filter) {
12892 case HWTSTAMP_FILTER_NONE:
12893 tp->rxptpctl = 0;
12894 break;
12895 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
12896 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
12897 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
12898 break;
12899 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
12900 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
12901 TG3_RX_PTP_CTL_SYNC_EVNT;
12902 break;
12903 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
12904 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
12905 TG3_RX_PTP_CTL_DELAY_REQ;
12906 break;
12907 case HWTSTAMP_FILTER_PTP_V2_EVENT:
12908 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
12909 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
12910 break;
12911 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
12912 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
12913 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
12914 break;
12915 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
12916 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
12917 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
12918 break;
12919 case HWTSTAMP_FILTER_PTP_V2_SYNC:
12920 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
12921 TG3_RX_PTP_CTL_SYNC_EVNT;
12922 break;
12923 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
12924 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
12925 TG3_RX_PTP_CTL_SYNC_EVNT;
12926 break;
12927 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
12928 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
12929 TG3_RX_PTP_CTL_SYNC_EVNT;
12930 break;
12931 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
12932 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
12933 TG3_RX_PTP_CTL_DELAY_REQ;
12934 break;
12935 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
12936 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
12937 TG3_RX_PTP_CTL_DELAY_REQ;
12938 break;
12939 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
12940 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
12941 TG3_RX_PTP_CTL_DELAY_REQ;
12942 break;
12943 default:
12944 return -ERANGE;
12945 }
12946
12947 if (netif_running(dev) && tp->rxptpctl)
12948 tw32(TG3_RX_PTP_CTL,
12949 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
12950
12951 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
12952 -EFAULT : 0;
12953}
12954
1da177e4
LT		 12955static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12956{
12957 struct mii_ioctl_data *data = if_mii(ifr);
12958 struct tg3 *tp = netdev_priv(dev);
12959 int err;
12960
63c3a66f 12961 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 12962 struct phy_device *phydev;
f07e9af3 12963 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12964 return -EAGAIN;
3f0e3ad7 12965 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
28b04113 12966 return phy_mii_ioctl(phydev, ifr, cmd);
b02fd9e3
MC		 12967 }
12968
33f401ae 12969 switch (cmd) {
1da177e4 12970 case SIOCGMIIPHY:
882e9793 12971 data->phy_id = tp->phy_addr;
1da177e4
LT		 12972
12973 /* fallthru */
12974 case SIOCGMIIREG: {
12975 u32 mii_regval;
12976
f07e9af3 12977 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 12978 break; /* We have no PHY */
12979
34eea5ac 12980 if (!netif_running(dev))
bc1c7567
MC		 12981 return -EAGAIN;
12982
f47c11ee 12983 spin_lock_bh(&tp->lock);
5c358045
HM		 12984 err = __tg3_readphy(tp, data->phy_id & 0x1f,
12985 data->reg_num & 0x1f, &mii_regval);
f47c11ee 12986 spin_unlock_bh(&tp->lock);
1da177e4
LT		 12987
12988 data->val_out = mii_regval;
12989
12990 return err;
12991 }
12992
12993 case SIOCSMIIREG:
f07e9af3 12994 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 12995 break; /* We have no PHY */
12996
34eea5ac 12997 if (!netif_running(dev))
bc1c7567
MC		 12998 return -EAGAIN;
12999
f47c11ee 13000 spin_lock_bh(&tp->lock);
5c358045
HM		 13001 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13002 data->reg_num & 0x1f, data->val_in);
f47c11ee 13003 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13004
13005 return err;
13006
0a633ac2
MC		 13007 case SIOCSHWTSTAMP:
13008 return tg3_hwtstamp_ioctl(dev, ifr, cmd);
13009
1da177e4
LT		 13010 default:
13011 /* do nothing */
13012 break;
13013 }
13014 return -EOPNOTSUPP;
13015}
13016
15f9850d
DM		 13017static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13018{
13019 struct tg3 *tp = netdev_priv(dev);
13020
13021 memcpy(ec, &tp->coal, sizeof(*ec));
13022 return 0;
13023}
13024
d244c892
MC		 13025static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13026{
13027 struct tg3 *tp = netdev_priv(dev);
13028 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13029 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13030
63c3a66f 13031 if (!tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 13032 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13033 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13034 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13035 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13036 }
13037
13038 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13039 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13040 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13041 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13042 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13043 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13044 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13045 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13046 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13047 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13048 return -EINVAL;
13049
13050 /* No rx interrupts will be generated if both are zero */
13051 if ((ec->rx_coalesce_usecs == 0) &&
13052 (ec->rx_max_coalesced_frames == 0))
13053 return -EINVAL;
13054
13055 /* No tx interrupts will be generated if both are zero */
13056 if ((ec->tx_coalesce_usecs == 0) &&
13057 (ec->tx_max_coalesced_frames == 0))
13058 return -EINVAL;
13059
13060 /* Only copy relevant parameters, ignore all others. */
13061 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
13062 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
13063 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
13064 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
13065 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
13066 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
13067 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
13068 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
13069 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
13070
13071 if (netif_running(dev)) {
13072 tg3_full_lock(tp, 0);
13073 __tg3_set_coalesce(tp, &tp->coal);
13074 tg3_full_unlock(tp);
13075 }
13076 return 0;
13077}
13078
7282d491 13079static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 13080 .get_settings = tg3_get_settings,
13081 .set_settings = tg3_set_settings,
13082 .get_drvinfo = tg3_get_drvinfo,
13083 .get_regs_len = tg3_get_regs_len,
13084 .get_regs = tg3_get_regs,
13085 .get_wol = tg3_get_wol,
13086 .set_wol = tg3_set_wol,
13087 .get_msglevel = tg3_get_msglevel,
13088 .set_msglevel = tg3_set_msglevel,
13089 .nway_reset = tg3_nway_reset,
13090 .get_link = ethtool_op_get_link,
13091 .get_eeprom_len = tg3_get_eeprom_len,
13092 .get_eeprom = tg3_get_eeprom,
13093 .set_eeprom = tg3_set_eeprom,
13094 .get_ringparam = tg3_get_ringparam,
13095 .set_ringparam = tg3_set_ringparam,
13096 .get_pauseparam = tg3_get_pauseparam,
13097 .set_pauseparam = tg3_set_pauseparam,
4cafd3f5 13098 .self_test = tg3_self_test,
1da177e4 13099 .get_strings = tg3_get_strings,
81b8709c 13100 .set_phys_id = tg3_set_phys_id,
1da177e4 13101 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 13102 .get_coalesce = tg3_get_coalesce,
d244c892 13103 .set_coalesce = tg3_set_coalesce,
b9f2c044 13104 .get_sset_count = tg3_get_sset_count,
90415477
MC		 13105 .get_rxnfc = tg3_get_rxnfc,
13106 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
13107 .get_rxfh_indir = tg3_get_rxfh_indir,
13108 .set_rxfh_indir = tg3_set_rxfh_indir,
0968169c
MC		 13109 .get_channels = tg3_get_channels,
13110 .set_channels = tg3_set_channels,
7d41e49a 13111 .get_ts_info = tg3_get_ts_info,
1da177e4
LT		 13112};
13113
b4017c53
DM		 13114static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
13115 struct rtnl_link_stats64 *stats)
13116{
13117 struct tg3 *tp = netdev_priv(dev);
13118
0f566b20
MC		 13119 spin_lock_bh(&tp->lock);
13120 if (!tp->hw_stats) {
13121 spin_unlock_bh(&tp->lock);
b4017c53 13122 return &tp->net_stats_prev;
0f566b20 13123 }
b4017c53 13124
b4017c53
DM		 13125 tg3_get_nstats(tp, stats);
13126 spin_unlock_bh(&tp->lock);
13127
13128 return stats;
13129}
13130
ccd5ba9d
MC		 13131static void tg3_set_rx_mode(struct net_device *dev)
13132{
13133 struct tg3 *tp = netdev_priv(dev);
13134
13135 if (!netif_running(dev))
13136 return;
13137
13138 tg3_full_lock(tp, 0);
13139 __tg3_set_rx_mode(dev);
13140 tg3_full_unlock(tp);
13141}
13142
faf1627a
MC		 13143static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
13144 int new_mtu)
13145{
13146 dev->mtu = new_mtu;
13147
13148 if (new_mtu > ETH_DATA_LEN) {
13149 if (tg3_flag(tp, 5780_CLASS)) {
13150 netdev_update_features(dev);
13151 tg3_flag_clear(tp, TSO_CAPABLE);
13152 } else {
13153 tg3_flag_set(tp, JUMBO_RING_ENABLE);
13154 }
13155 } else {
13156 if (tg3_flag(tp, 5780_CLASS)) {
13157 tg3_flag_set(tp, TSO_CAPABLE);
13158 netdev_update_features(dev);
13159 }
13160 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
13161 }
13162}
13163
13164static int tg3_change_mtu(struct net_device *dev, int new_mtu)
13165{
13166 struct tg3 *tp = netdev_priv(dev);
2fae5e36 13167 int err, reset_phy = 0;
faf1627a
MC		 13168
13169 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
13170 return -EINVAL;
13171
13172 if (!netif_running(dev)) {
13173 /* We'll just catch it later when the
13174 * device is up'd.
13175 */
13176 tg3_set_mtu(dev, tp, new_mtu);
13177 return 0;
13178 }
13179
13180 tg3_phy_stop(tp);
13181
13182 tg3_netif_stop(tp);
13183
13184 tg3_full_lock(tp, 1);
13185
13186 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13187
13188 tg3_set_mtu(dev, tp, new_mtu);
13189
2fae5e36
MC		 13190 /* Reset PHY, otherwise the read DMA engine will be in a mode that
13191 * breaks all requests to 256 bytes.
13192 */
13193 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
13194 reset_phy = 1;
13195
13196 err = tg3_restart_hw(tp, reset_phy);
faf1627a
MC		 13197
13198 if (!err)
13199 tg3_netif_start(tp);
13200
13201 tg3_full_unlock(tp);
13202
13203 if (!err)
13204 tg3_phy_start(tp);
13205
13206 return err;
13207}
13208
13209static const struct net_device_ops tg3_netdev_ops = {
13210 .ndo_open = tg3_open,
13211 .ndo_stop = tg3_close,
13212 .ndo_start_xmit = tg3_start_xmit,
13213 .ndo_get_stats64 = tg3_get_stats64,
13214 .ndo_validate_addr = eth_validate_addr,
13215 .ndo_set_rx_mode = tg3_set_rx_mode,
13216 .ndo_set_mac_address = tg3_set_mac_addr,
13217 .ndo_do_ioctl = tg3_ioctl,
13218 .ndo_tx_timeout = tg3_tx_timeout,
13219 .ndo_change_mtu = tg3_change_mtu,
13220 .ndo_fix_features = tg3_fix_features,
13221 .ndo_set_features = tg3_set_features,
13222#ifdef CONFIG_NET_POLL_CONTROLLER
13223 .ndo_poll_controller = tg3_poll_controller,
13224#endif
13225};
13226
229b1ad1 13227static void tg3_get_eeprom_size(struct tg3 *tp)
1da177e4 13228{
1b27777a 13229 u32 cursize, val, magic;
1da177e4
LT		 13230
13231 tp->nvram_size = EEPROM_CHIP_SIZE;
13232
e4f34110 13233 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 13234 return;
13235
b16250e3
MC		 13236 if ((magic != TG3_EEPROM_MAGIC) &&
13237 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
13238 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 13239 return;
13240
13241 /*
13242 * Size the chip by reading offsets at increasing powers of two.
13243 * When we encounter our validation signature, we know the addressing
13244 * has wrapped around, and thus have our chip size.
13245 */
1b27777a 13246 cursize = 0x10;
1da177e4
LT		 13247
13248 while (cursize < tp->nvram_size) {
e4f34110 13249 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 13250 return;
13251
1820180b 13252 if (val == magic)
1da177e4
LT		 13253 break;
13254
13255 cursize <<= 1;
13256 }
13257
13258 tp->nvram_size = cursize;
13259}
6aa20a22 13260
229b1ad1 13261static void tg3_get_nvram_size(struct tg3 *tp)
1da177e4
LT		 13262{
13263 u32 val;
13264
63c3a66f 13265 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 13266 return;
13267
13268 /* Selfboot format */
1820180b 13269 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 13270 tg3_get_eeprom_size(tp);
13271 return;
13272 }
13273
6d348f2c 13274 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 13275 if (val != 0) {
6d348f2c
MC		 13276 /* This is confusing. We want to operate on the
13277 * 16-bit value at offset 0xf2. The tg3_nvram_read()
13278 * call will read from NVRAM and byteswap the data
13279 * according to the byteswapping settings for all
13280 * other register accesses. This ensures the data we
13281 * want will always reside in the lower 16-bits.
13282 * However, the data in NVRAM is in LE format, which
13283 * means the data from the NVRAM read will always be
13284 * opposite the endianness of the CPU. The 16-bit
13285 * byteswap then brings the data to CPU endianness.
13286 */
13287 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 13288 return;
13289 }
13290 }
fd1122a2 13291 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 13292}
13293
229b1ad1 13294static void tg3_get_nvram_info(struct tg3 *tp)
1da177e4
LT		 13295{
13296 u32 nvcfg1;
13297
13298 nvcfg1 = tr32(NVRAM_CFG1);
13299 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
63c3a66f 13300 tg3_flag_set(tp, FLASH);
8590a603 13301 } else {
1da177e4
LT		 13302 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13303 tw32(NVRAM_CFG1, nvcfg1);
13304 }
13305
6ff6f81d 13306 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
63c3a66f 13307 tg3_flag(tp, 5780_CLASS)) {
1da177e4 13308 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 13309 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
13310 tp->nvram_jedecnum = JEDEC_ATMEL;
13311 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 13312 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 13313 break;
13314 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
13315 tp->nvram_jedecnum = JEDEC_ATMEL;
13316 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
13317 break;
13318 case FLASH_VENDOR_ATMEL_EEPROM:
13319 tp->nvram_jedecnum = JEDEC_ATMEL;
13320 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
63c3a66f 13321 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 13322 break;
13323 case FLASH_VENDOR_ST:
13324 tp->nvram_jedecnum = JEDEC_ST;
13325 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
63c3a66f 13326 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 13327 break;
13328 case FLASH_VENDOR_SAIFUN:
13329 tp->nvram_jedecnum = JEDEC_SAIFUN;
13330 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
13331 break;
13332 case FLASH_VENDOR_SST_SMALL:
13333 case FLASH_VENDOR_SST_LARGE:
13334 tp->nvram_jedecnum = JEDEC_SST;
13335 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
13336 break;
1da177e4 13337 }
8590a603 13338 } else {
1da177e4
LT		 13339 tp->nvram_jedecnum = JEDEC_ATMEL;
13340 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 13341 tg3_flag_set(tp, NVRAM_BUFFERED);
1da177e4
LT		 13342 }
13343}
13344
229b1ad1 13345static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
a1b950d5
MC		 13346{
13347 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
13348 case FLASH_5752PAGE_SIZE_256:
13349 tp->nvram_pagesize = 256;
13350 break;
13351 case FLASH_5752PAGE_SIZE_512:
13352 tp->nvram_pagesize = 512;
13353 break;
13354 case FLASH_5752PAGE_SIZE_1K:
13355 tp->nvram_pagesize = 1024;
13356 break;
13357 case FLASH_5752PAGE_SIZE_2K:
13358 tp->nvram_pagesize = 2048;
13359 break;
13360 case FLASH_5752PAGE_SIZE_4K:
13361 tp->nvram_pagesize = 4096;
13362 break;
13363 case FLASH_5752PAGE_SIZE_264:
13364 tp->nvram_pagesize = 264;
13365 break;
13366 case FLASH_5752PAGE_SIZE_528:
13367 tp->nvram_pagesize = 528;
13368 break;
13369 }
13370}
13371
229b1ad1 13372static void tg3_get_5752_nvram_info(struct tg3 *tp)
361b4ac2
MC		 13373{
13374 u32 nvcfg1;
13375
13376 nvcfg1 = tr32(NVRAM_CFG1);
13377
e6af301b
MC		 13378 /* NVRAM protection for TPM */
13379 if (nvcfg1 & (1 << 27))
63c3a66f 13380 tg3_flag_set(tp, PROTECTED_NVRAM);
e6af301b 13381
361b4ac2 13382 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 13383 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
13384 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
13385 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 13386 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 13387 break;
13388 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
13389 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 13390 tg3_flag_set(tp, NVRAM_BUFFERED);
13391 tg3_flag_set(tp, FLASH);
8590a603
MC		 13392 break;
13393 case FLASH_5752VENDOR_ST_M45PE10:
13394 case FLASH_5752VENDOR_ST_M45PE20:
13395 case FLASH_5752VENDOR_ST_M45PE40:
13396 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 13397 tg3_flag_set(tp, NVRAM_BUFFERED);
13398 tg3_flag_set(tp, FLASH);
8590a603 13399 break;
361b4ac2
MC		 13400 }
13401
63c3a66f 13402 if (tg3_flag(tp, FLASH)) {
a1b950d5 13403 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 13404 } else {
361b4ac2
MC		 13405 /* For eeprom, set pagesize to maximum eeprom size */
13406 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13407
13408 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13409 tw32(NVRAM_CFG1, nvcfg1);
13410 }
13411}
13412
229b1ad1 13413static void tg3_get_5755_nvram_info(struct tg3 *tp)
d3c7b886 13414{
989a9d23 13415 u32 nvcfg1, protect = 0;
d3c7b886
MC		 13416
13417 nvcfg1 = tr32(NVRAM_CFG1);
13418
13419 /* NVRAM protection for TPM */
989a9d23 13420 if (nvcfg1 & (1 << 27)) {
63c3a66f 13421 tg3_flag_set(tp, PROTECTED_NVRAM);
989a9d23
MC		 13422 protect = 1;
13423 }
d3c7b886 13424
989a9d23
MC		 13425 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
13426 switch (nvcfg1) {
8590a603
MC		 13427 case FLASH_5755VENDOR_ATMEL_FLASH_1:
13428 case FLASH_5755VENDOR_ATMEL_FLASH_2:
13429 case FLASH_5755VENDOR_ATMEL_FLASH_3:
13430 case FLASH_5755VENDOR_ATMEL_FLASH_5:
13431 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 13432 tg3_flag_set(tp, NVRAM_BUFFERED);
13433 tg3_flag_set(tp, FLASH);
8590a603
MC		 13434 tp->nvram_pagesize = 264;
13435 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
13436 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
13437 tp->nvram_size = (protect ? 0x3e200 :
13438 TG3_NVRAM_SIZE_512KB);
13439 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
13440 tp->nvram_size = (protect ? 0x1f200 :
13441 TG3_NVRAM_SIZE_256KB);
13442 else
13443 tp->nvram_size = (protect ? 0x1f200 :
13444 TG3_NVRAM_SIZE_128KB);
13445 break;
13446 case FLASH_5752VENDOR_ST_M45PE10:
13447 case FLASH_5752VENDOR_ST_M45PE20:
13448 case FLASH_5752VENDOR_ST_M45PE40:
13449 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 13450 tg3_flag_set(tp, NVRAM_BUFFERED);
13451 tg3_flag_set(tp, FLASH);
8590a603
MC		 13452 tp->nvram_pagesize = 256;
13453 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
13454 tp->nvram_size = (protect ?
13455 TG3_NVRAM_SIZE_64KB :
13456 TG3_NVRAM_SIZE_128KB);
13457 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
13458 tp->nvram_size = (protect ?
13459 TG3_NVRAM_SIZE_64KB :
13460 TG3_NVRAM_SIZE_256KB);
13461 else
13462 tp->nvram_size = (protect ?
13463 TG3_NVRAM_SIZE_128KB :
13464 TG3_NVRAM_SIZE_512KB);
13465 break;
d3c7b886
MC		 13466 }
13467}
13468
229b1ad1 13469static void tg3_get_5787_nvram_info(struct tg3 *tp)
1b27777a
MC		 13470{
13471 u32 nvcfg1;
13472
13473 nvcfg1 = tr32(NVRAM_CFG1);
13474
13475 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 13476 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
13477 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
13478 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
13479 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
13480 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 13481 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603 13482 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 13483
8590a603
MC		 13484 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13485 tw32(NVRAM_CFG1, nvcfg1);
13486 break;
13487 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
13488 case FLASH_5755VENDOR_ATMEL_FLASH_1:
13489 case FLASH_5755VENDOR_ATMEL_FLASH_2:
13490 case FLASH_5755VENDOR_ATMEL_FLASH_3:
13491 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 13492 tg3_flag_set(tp, NVRAM_BUFFERED);
13493 tg3_flag_set(tp, FLASH);
8590a603
MC		 13494 tp->nvram_pagesize = 264;
13495 break;
13496 case FLASH_5752VENDOR_ST_M45PE10:
13497 case FLASH_5752VENDOR_ST_M45PE20:
13498 case FLASH_5752VENDOR_ST_M45PE40:
13499 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 13500 tg3_flag_set(tp, NVRAM_BUFFERED);
13501 tg3_flag_set(tp, FLASH);
8590a603
MC		 13502 tp->nvram_pagesize = 256;
13503 break;
1b27777a
MC		 13504 }
13505}
13506
229b1ad1 13507static void tg3_get_5761_nvram_info(struct tg3 *tp)
6b91fa02
MC		 13508{
13509 u32 nvcfg1, protect = 0;
13510
13511 nvcfg1 = tr32(NVRAM_CFG1);
13512
13513 /* NVRAM protection for TPM */
13514 if (nvcfg1 & (1 << 27)) {
63c3a66f 13515 tg3_flag_set(tp, PROTECTED_NVRAM);
6b91fa02
MC		 13516 protect = 1;
13517 }
13518
13519 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
13520 switch (nvcfg1) {
8590a603
MC		 13521 case FLASH_5761VENDOR_ATMEL_ADB021D:
13522 case FLASH_5761VENDOR_ATMEL_ADB041D:
13523 case FLASH_5761VENDOR_ATMEL_ADB081D:
13524 case FLASH_5761VENDOR_ATMEL_ADB161D:
13525 case FLASH_5761VENDOR_ATMEL_MDB021D:
13526 case FLASH_5761VENDOR_ATMEL_MDB041D:
13527 case FLASH_5761VENDOR_ATMEL_MDB081D:
13528 case FLASH_5761VENDOR_ATMEL_MDB161D:
13529 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 13530 tg3_flag_set(tp, NVRAM_BUFFERED);
13531 tg3_flag_set(tp, FLASH);
13532 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
8590a603
MC		 13533 tp->nvram_pagesize = 256;
13534 break;
13535 case FLASH_5761VENDOR_ST_A_M45PE20:
13536 case FLASH_5761VENDOR_ST_A_M45PE40:
13537 case FLASH_5761VENDOR_ST_A_M45PE80:
13538 case FLASH_5761VENDOR_ST_A_M45PE16:
13539 case FLASH_5761VENDOR_ST_M_M45PE20:
13540 case FLASH_5761VENDOR_ST_M_M45PE40:
13541 case FLASH_5761VENDOR_ST_M_M45PE80:
13542 case FLASH_5761VENDOR_ST_M_M45PE16:
13543 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 13544 tg3_flag_set(tp, NVRAM_BUFFERED);
13545 tg3_flag_set(tp, FLASH);
8590a603
MC		 13546 tp->nvram_pagesize = 256;
13547 break;
6b91fa02
MC		 13548 }
13549
13550 if (protect) {
13551 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
13552 } else {
13553 switch (nvcfg1) {
8590a603
MC		 13554 case FLASH_5761VENDOR_ATMEL_ADB161D:
13555 case FLASH_5761VENDOR_ATMEL_MDB161D:
13556 case FLASH_5761VENDOR_ST_A_M45PE16:
13557 case FLASH_5761VENDOR_ST_M_M45PE16:
13558 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
13559 break;
13560 case FLASH_5761VENDOR_ATMEL_ADB081D:
13561 case FLASH_5761VENDOR_ATMEL_MDB081D:
13562 case FLASH_5761VENDOR_ST_A_M45PE80:
13563 case FLASH_5761VENDOR_ST_M_M45PE80:
13564 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
13565 break;
13566 case FLASH_5761VENDOR_ATMEL_ADB041D:
13567 case FLASH_5761VENDOR_ATMEL_MDB041D:
13568 case FLASH_5761VENDOR_ST_A_M45PE40:
13569 case FLASH_5761VENDOR_ST_M_M45PE40:
13570 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13571 break;
13572 case FLASH_5761VENDOR_ATMEL_ADB021D:
13573 case FLASH_5761VENDOR_ATMEL_MDB021D:
13574 case FLASH_5761VENDOR_ST_A_M45PE20:
13575 case FLASH_5761VENDOR_ST_M_M45PE20:
13576 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13577 break;
6b91fa02
MC		 13578 }
13579 }
13580}
13581
229b1ad1 13582static void tg3_get_5906_nvram_info(struct tg3 *tp)
b5d3772c
MC		 13583{
13584 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 13585 tg3_flag_set(tp, NVRAM_BUFFERED);
b5d3772c
MC		 13586 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13587}
13588
229b1ad1 13589static void tg3_get_57780_nvram_info(struct tg3 *tp)
321d32a0
MC		 13590{
13591 u32 nvcfg1;
13592
13593 nvcfg1 = tr32(NVRAM_CFG1);
13594
13595 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13596 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
13597 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
13598 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 13599 tg3_flag_set(tp, NVRAM_BUFFERED);
321d32a0
MC		 13600 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13601
13602 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13603 tw32(NVRAM_CFG1, nvcfg1);
13604 return;
13605 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
13606 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
13607 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
13608 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
13609 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
13610 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
13611 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
13612 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 13613 tg3_flag_set(tp, NVRAM_BUFFERED);
13614 tg3_flag_set(tp, FLASH);
321d32a0
MC		 13615
13616 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13617 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
13618 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
13619 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
13620 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13621 break;
13622 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
13623 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
13624 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13625 break;
13626 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
13627 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
13628 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13629 break;
13630 }
13631 break;
13632 case FLASH_5752VENDOR_ST_M45PE10:
13633 case FLASH_5752VENDOR_ST_M45PE20:
13634 case FLASH_5752VENDOR_ST_M45PE40:
13635 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 13636 tg3_flag_set(tp, NVRAM_BUFFERED);
13637 tg3_flag_set(tp, FLASH);
321d32a0
MC		 13638
13639 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13640 case FLASH_5752VENDOR_ST_M45PE10:
13641 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13642 break;
13643 case FLASH_5752VENDOR_ST_M45PE20:
13644 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13645 break;
13646 case FLASH_5752VENDOR_ST_M45PE40:
13647 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13648 break;
13649 }
13650 break;
13651 default:
63c3a66f 13652 tg3_flag_set(tp, NO_NVRAM);
321d32a0
MC		 13653 return;
13654 }
13655
a1b950d5
MC		 13656 tg3_nvram_get_pagesize(tp, nvcfg1);
13657 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 13658 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
a1b950d5
MC		 13659}
13660
13661
229b1ad1 13662static void tg3_get_5717_nvram_info(struct tg3 *tp)
a1b950d5
MC		 13663{
13664 u32 nvcfg1;
13665
13666 nvcfg1 = tr32(NVRAM_CFG1);
13667
13668 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13669 case FLASH_5717VENDOR_ATMEL_EEPROM:
13670 case FLASH_5717VENDOR_MICRO_EEPROM:
13671 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 13672 tg3_flag_set(tp, NVRAM_BUFFERED);
a1b950d5
MC		 13673 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13674
13675 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13676 tw32(NVRAM_CFG1, nvcfg1);
13677 return;
13678 case FLASH_5717VENDOR_ATMEL_MDB011D:
13679 case FLASH_5717VENDOR_ATMEL_ADB011B:
13680 case FLASH_5717VENDOR_ATMEL_ADB011D:
13681 case FLASH_5717VENDOR_ATMEL_MDB021D:
13682 case FLASH_5717VENDOR_ATMEL_ADB021B:
13683 case FLASH_5717VENDOR_ATMEL_ADB021D:
13684 case FLASH_5717VENDOR_ATMEL_45USPT:
13685 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 13686 tg3_flag_set(tp, NVRAM_BUFFERED);
13687 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 13688
13689 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13690 case FLASH_5717VENDOR_ATMEL_MDB021D:
66ee33bf
MC		 13691 /* Detect size with tg3_nvram_get_size() */
13692 break;
a1b950d5
MC		 13693 case FLASH_5717VENDOR_ATMEL_ADB021B:
13694 case FLASH_5717VENDOR_ATMEL_ADB021D:
13695 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13696 break;
13697 default:
13698 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13699 break;
13700 }
321d32a0 13701 break;
a1b950d5
MC		 13702 case FLASH_5717VENDOR_ST_M_M25PE10:
13703 case FLASH_5717VENDOR_ST_A_M25PE10:
13704 case FLASH_5717VENDOR_ST_M_M45PE10:
13705 case FLASH_5717VENDOR_ST_A_M45PE10:
13706 case FLASH_5717VENDOR_ST_M_M25PE20:
13707 case FLASH_5717VENDOR_ST_A_M25PE20:
13708 case FLASH_5717VENDOR_ST_M_M45PE20:
13709 case FLASH_5717VENDOR_ST_A_M45PE20:
13710 case FLASH_5717VENDOR_ST_25USPT:
13711 case FLASH_5717VENDOR_ST_45USPT:
13712 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 13713 tg3_flag_set(tp, NVRAM_BUFFERED);
13714 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 13715
13716 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13717 case FLASH_5717VENDOR_ST_M_M25PE20:
a1b950d5 13718 case FLASH_5717VENDOR_ST_M_M45PE20:
66ee33bf
MC		 13719 /* Detect size with tg3_nvram_get_size() */
13720 break;
13721 case FLASH_5717VENDOR_ST_A_M25PE20:
a1b950d5
MC		 13722 case FLASH_5717VENDOR_ST_A_M45PE20:
13723 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13724 break;
13725 default:
13726 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13727 break;
13728 }
321d32a0 13729 break;
a1b950d5 13730 default:
63c3a66f 13731 tg3_flag_set(tp, NO_NVRAM);
a1b950d5 13732 return;
321d32a0 13733 }
a1b950d5
MC		 13734
13735 tg3_nvram_get_pagesize(tp, nvcfg1);
13736 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 13737 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
321d32a0
MC		 13738}
13739
229b1ad1 13740static void tg3_get_5720_nvram_info(struct tg3 *tp)
9b91b5f1
MC		 13741{
13742 u32 nvcfg1, nvmpinstrp;
13743
13744 nvcfg1 = tr32(NVRAM_CFG1);
13745 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
13746
c86a8560
MC		 13747 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) {
13748 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
13749 tg3_flag_set(tp, NO_NVRAM);
13750 return;
13751 }
13752
13753 switch (nvmpinstrp) {
13754 case FLASH_5762_EEPROM_HD:
13755 nvmpinstrp = FLASH_5720_EEPROM_HD;
17e1a42f 13756 break;
c86a8560
MC		 13757 case FLASH_5762_EEPROM_LD:
13758 nvmpinstrp = FLASH_5720_EEPROM_LD;
17e1a42f 13759 break;
c86a8560
MC		 13760 }
13761 }
13762
9b91b5f1
MC		 13763 switch (nvmpinstrp) {
13764 case FLASH_5720_EEPROM_HD:
13765 case FLASH_5720_EEPROM_LD:
13766 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 13767 tg3_flag_set(tp, NVRAM_BUFFERED);
9b91b5f1
MC		 13768
13769 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13770 tw32(NVRAM_CFG1, nvcfg1);
13771 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
13772 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13773 else
13774 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
13775 return;
13776 case FLASH_5720VENDOR_M_ATMEL_DB011D:
13777 case FLASH_5720VENDOR_A_ATMEL_DB011B:
13778 case FLASH_5720VENDOR_A_ATMEL_DB011D:
13779 case FLASH_5720VENDOR_M_ATMEL_DB021D:
13780 case FLASH_5720VENDOR_A_ATMEL_DB021B:
13781 case FLASH_5720VENDOR_A_ATMEL_DB021D:
13782 case FLASH_5720VENDOR_M_ATMEL_DB041D:
13783 case FLASH_5720VENDOR_A_ATMEL_DB041B:
13784 case FLASH_5720VENDOR_A_ATMEL_DB041D:
13785 case FLASH_5720VENDOR_M_ATMEL_DB081D:
13786 case FLASH_5720VENDOR_A_ATMEL_DB081D:
13787 case FLASH_5720VENDOR_ATMEL_45USPT:
13788 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 13789 tg3_flag_set(tp, NVRAM_BUFFERED);
13790 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 13791
13792 switch (nvmpinstrp) {
13793 case FLASH_5720VENDOR_M_ATMEL_DB021D:
13794 case FLASH_5720VENDOR_A_ATMEL_DB021B:
13795 case FLASH_5720VENDOR_A_ATMEL_DB021D:
13796 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13797 break;
13798 case FLASH_5720VENDOR_M_ATMEL_DB041D:
13799 case FLASH_5720VENDOR_A_ATMEL_DB041B:
13800 case FLASH_5720VENDOR_A_ATMEL_DB041D:
13801 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13802 break;
13803 case FLASH_5720VENDOR_M_ATMEL_DB081D:
13804 case FLASH_5720VENDOR_A_ATMEL_DB081D:
13805 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
13806 break;
13807 default:
13808 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13809 break;
13810 }
13811 break;
13812 case FLASH_5720VENDOR_M_ST_M25PE10:
13813 case FLASH_5720VENDOR_M_ST_M45PE10:
13814 case FLASH_5720VENDOR_A_ST_M25PE10:
13815 case FLASH_5720VENDOR_A_ST_M45PE10:
13816 case FLASH_5720VENDOR_M_ST_M25PE20:
13817 case FLASH_5720VENDOR_M_ST_M45PE20:
13818 case FLASH_5720VENDOR_A_ST_M25PE20:
13819 case FLASH_5720VENDOR_A_ST_M45PE20:
13820 case FLASH_5720VENDOR_M_ST_M25PE40:
13821 case FLASH_5720VENDOR_M_ST_M45PE40:
13822 case FLASH_5720VENDOR_A_ST_M25PE40:
13823 case FLASH_5720VENDOR_A_ST_M45PE40:
13824 case FLASH_5720VENDOR_M_ST_M25PE80:
13825 case FLASH_5720VENDOR_M_ST_M45PE80:
13826 case FLASH_5720VENDOR_A_ST_M25PE80:
13827 case FLASH_5720VENDOR_A_ST_M45PE80:
13828 case FLASH_5720VENDOR_ST_25USPT:
13829 case FLASH_5720VENDOR_ST_45USPT:
13830 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 13831 tg3_flag_set(tp, NVRAM_BUFFERED);
13832 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 13833
13834 switch (nvmpinstrp) {
13835 case FLASH_5720VENDOR_M_ST_M25PE20:
13836 case FLASH_5720VENDOR_M_ST_M45PE20:
13837 case FLASH_5720VENDOR_A_ST_M25PE20:
13838 case FLASH_5720VENDOR_A_ST_M45PE20:
13839 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13840 break;
13841 case FLASH_5720VENDOR_M_ST_M25PE40:
13842 case FLASH_5720VENDOR_M_ST_M45PE40:
13843 case FLASH_5720VENDOR_A_ST_M25PE40:
13844 case FLASH_5720VENDOR_A_ST_M45PE40:
13845 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13846 break;
13847 case FLASH_5720VENDOR_M_ST_M25PE80:
13848 case FLASH_5720VENDOR_M_ST_M45PE80:
13849 case FLASH_5720VENDOR_A_ST_M25PE80:
13850 case FLASH_5720VENDOR_A_ST_M45PE80:
13851 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
13852 break;
13853 default:
13854 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13855 break;
13856 }
13857 break;
13858 default:
63c3a66f 13859 tg3_flag_set(tp, NO_NVRAM);
9b91b5f1
MC		 13860 return;
13861 }
13862
13863 tg3_nvram_get_pagesize(tp, nvcfg1);
13864 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 13865 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
c86a8560
MC		 13866
13867 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) {
13868 u32 val;
13869
13870 if (tg3_nvram_read(tp, 0, &val))
13871 return;
13872
13873 if (val != TG3_EEPROM_MAGIC &&
13874 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
13875 tg3_flag_set(tp, NO_NVRAM);
13876 }
9b91b5f1
MC		 13877}
13878
1da177e4 13879/* Chips other than 5700/5701 use the NVRAM for fetching info. */
229b1ad1 13880static void tg3_nvram_init(struct tg3 *tp)
1da177e4 13881{
1da177e4
LT		 13882 tw32_f(GRC_EEPROM_ADDR,
13883 (EEPROM_ADDR_FSM_RESET |
13884 (EEPROM_DEFAULT_CLOCK_PERIOD <<
13885 EEPROM_ADDR_CLKPERD_SHIFT)));
13886
9d57f01c 13887 msleep(1);
1da177e4
LT		 13888
13889 /* Enable seeprom accesses. */
13890 tw32_f(GRC_LOCAL_CTRL,
13891 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
13892 udelay(100);
13893
13894 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13895 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
63c3a66f 13896 tg3_flag_set(tp, NVRAM);
1da177e4 13897
ec41c7df 13898 if (tg3_nvram_lock(tp)) {
5129c3a3
MC		 13899 netdev_warn(tp->dev,
13900 "Cannot get nvram lock, %s failed\n",
05dbe005 13901 __func__);
ec41c7df
MC		 13902 return;
13903 }
e6af301b 13904 tg3_enable_nvram_access(tp);
1da177e4 13905
989a9d23
MC		 13906 tp->nvram_size = 0;
13907
361b4ac2
MC		 13908 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13909 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 13910 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13911 tg3_get_5755_nvram_info(tp);
d30cdd28 13912 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 13913 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13914 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 13915 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 13916 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
13917 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 13918 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13919 tg3_get_5906_nvram_info(tp);
b703df6f 13920 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
55086ad9 13921 tg3_flag(tp, 57765_CLASS))
321d32a0 13922 tg3_get_57780_nvram_info(tp);
9b91b5f1
MC		 13923 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13924 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
a1b950d5 13925 tg3_get_5717_nvram_info(tp);
c86a8560
MC		 13926 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
13927 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762)
9b91b5f1 13928 tg3_get_5720_nvram_info(tp);
361b4ac2
MC		 13929 else
13930 tg3_get_nvram_info(tp);
13931
989a9d23
MC		 13932 if (tp->nvram_size == 0)
13933 tg3_get_nvram_size(tp);
1da177e4 13934
e6af301b 13935 tg3_disable_nvram_access(tp);
381291b7 13936 tg3_nvram_unlock(tp);
1da177e4
LT		 13937
13938 } else {
63c3a66f
JP		 13939 tg3_flag_clear(tp, NVRAM);
13940 tg3_flag_clear(tp, NVRAM_BUFFERED);
1da177e4
LT		 13941
13942 tg3_get_eeprom_size(tp);
13943 }
13944}
13945
1da177e4
LT		 13946struct subsys_tbl_ent {
13947 u16 subsys_vendor, subsys_devid;
13948 u32 phy_id;
13949};
13950
229b1ad1 13951static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
1da177e4 13952 /* Broadcom boards. */
24daf2b0 13953 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 13954 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 13955 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 13956 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 13957 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 13958 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 13959 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13960 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
13961 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 13962 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 13963 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 13964 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 13965 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13966 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
13967 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 13968 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 13969 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 13970 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 13971 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 13972 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 13973 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 13974 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 13975
13976 /* 3com boards. */
24daf2b0 13977 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 13978 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 13979 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 13980 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 13981 { TG3PCI_SUBVENDOR_ID_3COM,
13982 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
13983 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 13984 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 13985 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 13986 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 13987
13988 /* DELL boards. */
24daf2b0 13989 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 13990 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 13991 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 13992 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 13993 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 13994 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 13995 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 13996 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 13997
13998 /* Compaq boards. */
24daf2b0 13999 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14000 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 14001 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14002 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14003 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14004 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
14005 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14006 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 14007 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14008 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14009
14010 /* IBM boards. */
24daf2b0
MC		 14011 { TG3PCI_SUBVENDOR_ID_IBM,
14012 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 14013};
14014
229b1ad1 14015static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 14016{
14017 int i;
14018
14019 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
14020 if ((subsys_id_to_phy_id[i].subsys_vendor ==
14021 tp->pdev->subsystem_vendor) &&
14022 (subsys_id_to_phy_id[i].subsys_devid ==
14023 tp->pdev->subsystem_device))
14024 return &subsys_id_to_phy_id[i];
14025 }
14026 return NULL;
14027}
14028
229b1ad1 14029static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 14030{
1da177e4 14031 u32 val;
f49639e6 14032
79eb6904 14033 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 14034 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14035
a85feb8c 14036 /* Assume an onboard device and WOL capable by default. */
63c3a66f
JP		 14037 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14038 tg3_flag_set(tp, WOL_CAP);
72b845e0 14039
b5d3772c 14040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 14041 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
63c3a66f
JP		 14042 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14043 tg3_flag_set(tp, IS_NIC);
9d26e213 14044 }
0527ba35
MC		 14045 val = tr32(VCPU_CFGSHDW);
14046 if (val & VCPU_CFGSHDW_ASPM_DBNC)
63c3a66f 14047 tg3_flag_set(tp, ASPM_WORKAROUND);
0527ba35 14048 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
6fdbab9d 14049 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
63c3a66f 14050 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 14051 device_set_wakeup_enable(&tp->pdev->dev, true);
14052 }
05ac4cb7 14053 goto done;
b5d3772c
MC		 14054 }
14055
1da177e4
LT		 14056 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
14057 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
14058 u32 nic_cfg, led_cfg;
a9daf367 14059 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 14060 int eeprom_phy_serdes = 0;
1da177e4
LT		 14061
14062 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
14063 tp->nic_sram_data_cfg = nic_cfg;
14064
14065 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
14066 ver >>= NIC_SRAM_DATA_VER_SHIFT;
6ff6f81d
MC		 14067 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14068 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14069 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
1da177e4
LT		 14070 (ver > 0) && (ver < 0x100))
14071 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
14072
a9daf367
MC		 14073 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
14074 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
14075
1da177e4
LT		 14076 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
14077 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
14078 eeprom_phy_serdes = 1;
14079
14080 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
14081 if (nic_phy_id != 0) {
14082 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
14083 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
14084
14085 eeprom_phy_id = (id1 >> 16) << 10;
14086 eeprom_phy_id |= (id2 & 0xfc00) << 16;
14087 eeprom_phy_id |= (id2 & 0x03ff) << 0;
14088 } else
14089 eeprom_phy_id = 0;
14090
7d0c41ef 14091 tp->phy_id = eeprom_phy_id;
747e8f8b 14092 if (eeprom_phy_serdes) {
63c3a66f 14093 if (!tg3_flag(tp, 5705_PLUS))
f07e9af3 14094 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
a50d0796 14095 else
f07e9af3 14096 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
747e8f8b 14097 }
7d0c41ef 14098
63c3a66f 14099 if (tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 14100 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
14101 SHASTA_EXT_LED_MODE_MASK);
cbf46853 14102 else
1da177e4
LT		 14103 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
14104
14105 switch (led_cfg) {
14106 default:
14107 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
14108 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14109 break;
14110
14111 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
14112 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14113 break;
14114
14115 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
14116 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 14117
14118 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
14119 * read on some older 5700/5701 bootcode.
14120 */
14121 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
14122 ASIC_REV_5700 ||
14123 GET_ASIC_REV(tp->pci_chip_rev_id) ==
14124 ASIC_REV_5701)
14125 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14126
1da177e4
LT		 14127 break;
14128
14129 case SHASTA_EXT_LED_SHARED:
14130 tp->led_ctrl = LED_CTRL_MODE_SHARED;
14131 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
14132 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
14133 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14134 LED_CTRL_MODE_PHY_2);
14135 break;
14136
14137 case SHASTA_EXT_LED_MAC:
14138 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
14139 break;
14140
14141 case SHASTA_EXT_LED_COMBO:
14142 tp->led_ctrl = LED_CTRL_MODE_COMBO;
14143 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
14144 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14145 LED_CTRL_MODE_PHY_2);
14146 break;
14147
855e1111 14148 }
1da177e4
LT		 14149
14150 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14151 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
14152 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
14153 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14154
b2a5c19c
MC		 14155 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
14156 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 14157
9d26e213 14158 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
63c3a66f 14159 tg3_flag_set(tp, EEPROM_WRITE_PROT);
9d26e213
MC		 14160 if ((tp->pdev->subsystem_vendor ==
14161 PCI_VENDOR_ID_ARIMA) &&
14162 (tp->pdev->subsystem_device == 0x205a ||
14163 tp->pdev->subsystem_device == 0x2063))
63c3a66f 14164 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
9d26e213 14165 } else {
63c3a66f
JP		 14166 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14167 tg3_flag_set(tp, IS_NIC);
9d26e213 14168 }
1da177e4
LT		 14169
14170 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f
JP		 14171 tg3_flag_set(tp, ENABLE_ASF);
14172 if (tg3_flag(tp, 5750_PLUS))
14173 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
1da177e4 14174 }
b2b98d4a
MC		 14175
14176 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
63c3a66f
JP		 14177 tg3_flag(tp, 5750_PLUS))
14178 tg3_flag_set(tp, ENABLE_APE);
b2b98d4a 14179
f07e9af3 14180 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
a85feb8c 14181 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
63c3a66f 14182 tg3_flag_clear(tp, WOL_CAP);
1da177e4 14183
63c3a66f 14184 if (tg3_flag(tp, WOL_CAP) &&
6fdbab9d 14185 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
63c3a66f 14186 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 14187 device_set_wakeup_enable(&tp->pdev->dev, true);
14188 }
0527ba35 14189
1da177e4 14190 if (cfg2 & (1 << 17))
f07e9af3 14191 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
1da177e4
LT		 14192
14193 /* serdes signal pre-emphasis in register 0x590 set by */
14194 /* bootcode if bit 18 is set */
14195 if (cfg2 & (1 << 18))
f07e9af3 14196 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
8ed5d97e 14197
63c3a66f
JP		 14198 if ((tg3_flag(tp, 57765_PLUS) ||
14199 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14200 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043 14201 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
f07e9af3 14202 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
6833c043 14203
63c3a66f 14204 if (tg3_flag(tp, PCI_EXPRESS) &&
8c69b1e7 14205 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
63c3a66f 14206 !tg3_flag(tp, 57765_PLUS)) {
8ed5d97e
MC		 14207 u32 cfg3;
14208
14209 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
14210 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
63c3a66f 14211 tg3_flag_set(tp, ASPM_WORKAROUND);
8ed5d97e 14212 }
a9daf367 14213
14417063 14214 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
63c3a66f 14215 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
a9daf367 14216 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
63c3a66f 14217 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
a9daf367 14218 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
63c3a66f 14219 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
1da177e4 14220 }
05ac4cb7 14221done:
63c3a66f 14222 if (tg3_flag(tp, WOL_CAP))
43067ed8 14223 device_set_wakeup_enable(&tp->pdev->dev,
63c3a66f 14224 tg3_flag(tp, WOL_ENABLE));
43067ed8
RW		 14225 else
14226 device_set_wakeup_capable(&tp->pdev->dev, false);
7d0c41ef
MC		 14227}
14228
c86a8560
MC		 14229static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
14230{
14231 int i, err;
14232 u32 val2, off = offset * 8;
14233
14234 err = tg3_nvram_lock(tp);
14235 if (err)
14236 return err;
14237
14238 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
14239 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
14240 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
14241 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
14242 udelay(10);
14243
14244 for (i = 0; i < 100; i++) {
14245 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
14246 if (val2 & APE_OTP_STATUS_CMD_DONE) {
14247 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
14248 break;
14249 }
14250 udelay(10);
14251 }
14252
14253 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
14254
14255 tg3_nvram_unlock(tp);
14256 if (val2 & APE_OTP_STATUS_CMD_DONE)
14257 return 0;
14258
14259 return -EBUSY;
14260}
14261
229b1ad1 14262static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
b2a5c19c
MC		 14263{
14264 int i;
14265 u32 val;
14266
14267 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
14268 tw32(OTP_CTRL, cmd);
14269
14270 /* Wait for up to 1 ms for command to execute. */
14271 for (i = 0; i < 100; i++) {
14272 val = tr32(OTP_STATUS);
14273 if (val & OTP_STATUS_CMD_DONE)
14274 break;
14275 udelay(10);
14276 }
14277
14278 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
14279}
14280
14281/* Read the gphy configuration from the OTP region of the chip. The gphy
14282 * configuration is a 32-bit value that straddles the alignment boundary.
14283 * We do two 32-bit reads and then shift and merge the results.
14284 */
229b1ad1 14285static u32 tg3_read_otp_phycfg(struct tg3 *tp)
b2a5c19c
MC		 14286{
14287 u32 bhalf_otp, thalf_otp;
14288
14289 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
14290
14291 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
14292 return 0;
14293
14294 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
14295
14296 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
14297 return 0;
14298
14299 thalf_otp = tr32(OTP_READ_DATA);
14300
14301 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
14302
14303 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
14304 return 0;
14305
14306 bhalf_otp = tr32(OTP_READ_DATA);
14307
14308 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
14309}
14310
229b1ad1 14311static void tg3_phy_init_link_config(struct tg3 *tp)
e256f8a3 14312{
202ff1c2 14313 u32 adv = ADVERTISED_Autoneg;
e256f8a3
MC		 14314
14315 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
14316 adv |= ADVERTISED_1000baseT_Half |
14317 ADVERTISED_1000baseT_Full;
14318
14319 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
14320 adv |= ADVERTISED_100baseT_Half |
14321 ADVERTISED_100baseT_Full |
14322 ADVERTISED_10baseT_Half |
14323 ADVERTISED_10baseT_Full |
14324 ADVERTISED_TP;
14325 else
14326 adv |= ADVERTISED_FIBRE;
14327
14328 tp->link_config.advertising = adv;
e740522e
MC		 14329 tp->link_config.speed = SPEED_UNKNOWN;
14330 tp->link_config.duplex = DUPLEX_UNKNOWN;
e256f8a3 14331 tp->link_config.autoneg = AUTONEG_ENABLE;
e740522e
MC		 14332 tp->link_config.active_speed = SPEED_UNKNOWN;
14333 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
34655ad6
MC		 14334
14335 tp->old_link = -1;
e256f8a3
MC		 14336}
14337
229b1ad1 14338static int tg3_phy_probe(struct tg3 *tp)
7d0c41ef
MC		 14339{
14340 u32 hw_phy_id_1, hw_phy_id_2;
14341 u32 hw_phy_id, hw_phy_id_masked;
14342 int err;
1da177e4 14343
e256f8a3 14344 /* flow control autonegotiation is default behavior */
63c3a66f 14345 tg3_flag_set(tp, PAUSE_AUTONEG);
e256f8a3
MC		 14346 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14347
8151ad57
MC		 14348 if (tg3_flag(tp, ENABLE_APE)) {
14349 switch (tp->pci_fn) {
14350 case 0:
14351 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
14352 break;
14353 case 1:
14354 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
14355 break;
14356 case 2:
14357 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
14358 break;
14359 case 3:
14360 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
14361 break;
14362 }
14363 }
14364
63c3a66f 14365 if (tg3_flag(tp, USE_PHYLIB))
b02fd9e3
MC		 14366 return tg3_phy_init(tp);
14367
1da177e4 14368 /* Reading the PHY ID register can conflict with ASF
877d0310 14369 * firmware access to the PHY hardware.
1da177e4
LT		 14370 */
14371 err = 0;
63c3a66f 14372 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
79eb6904 14373 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 14374 } else {
14375 /* Now read the physical PHY_ID from the chip and verify
14376 * that it is sane. If it doesn't look good, we fall back
14377 * to either the hard-coded table based PHY_ID and failing
14378 * that the value found in the eeprom area.
14379 */
14380 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
14381 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
14382
14383 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
14384 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
14385 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
14386
79eb6904 14387 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 14388 }
14389
79eb6904 14390 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 14391 tp->phy_id = hw_phy_id;
79eb6904 14392 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
f07e9af3 14393 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
da6b2d01 14394 else
f07e9af3 14395 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
1da177e4 14396 } else {
79eb6904 14397 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 14398 /* Do nothing, phy ID already set up in
14399 * tg3_get_eeprom_hw_cfg().
14400 */
1da177e4
LT		 14401 } else {
14402 struct subsys_tbl_ent *p;
14403
14404 /* No eeprom signature? Try the hardcoded
14405 * subsys device table.
14406 */
24daf2b0 14407 p = tg3_lookup_by_subsys(tp);
1da177e4
LT		 14408 if (!p)
14409 return -ENODEV;
14410
14411 tp->phy_id = p->phy_id;
14412 if (!tp->phy_id ||
79eb6904 14413 tp->phy_id == TG3_PHY_ID_BCM8002)
f07e9af3 14414 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
1da177e4
LT		 14415 }
14416 }
14417
a6b68dab 14418 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
5baa5e9a
MC		 14419 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14420 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
c65a17f4 14421 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762 ||
5baa5e9a 14422 (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
a6b68dab
MC		 14423 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
14424 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
14425 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
52b02d04
MC		 14426 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
14427
e256f8a3
MC		 14428 tg3_phy_init_link_config(tp);
14429
f07e9af3 14430 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
63c3a66f
JP		 14431 !tg3_flag(tp, ENABLE_APE) &&
14432 !tg3_flag(tp, ENABLE_ASF)) {
e2bf73e7 14433 u32 bmsr, dummy;
1da177e4
LT		 14434
14435 tg3_readphy(tp, MII_BMSR, &bmsr);
14436 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
14437 (bmsr & BMSR_LSTATUS))
14438 goto skip_phy_reset;
6aa20a22 14439
1da177e4
LT		 14440 err = tg3_phy_reset(tp);
14441 if (err)
14442 return err;
14443
42b64a45 14444 tg3_phy_set_wirespeed(tp);
1da177e4 14445
e2bf73e7 14446 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
42b64a45
MC		 14447 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
14448 tp->link_config.flowctrl);
1da177e4
LT		 14449
14450 tg3_writephy(tp, MII_BMCR,
14451 BMCR_ANENABLE | BMCR_ANRESTART);
14452 }
1da177e4
LT		 14453 }
14454
14455skip_phy_reset:
79eb6904 14456 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 14457 err = tg3_init_5401phy_dsp(tp);
14458 if (err)
14459 return err;
1da177e4 14460
1da177e4
LT		 14461 err = tg3_init_5401phy_dsp(tp);
14462 }
14463
1da177e4
LT		 14464 return err;
14465}
14466
229b1ad1 14467static void tg3_read_vpd(struct tg3 *tp)
1da177e4 14468{
a4a8bb15 14469 u8 *vpd_data;
4181b2c8 14470 unsigned int block_end, rosize, len;
535a490e 14471 u32 vpdlen;
184b8904 14472 int j, i = 0;
a4a8bb15 14473
535a490e 14474 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
a4a8bb15
MC		 14475 if (!vpd_data)
14476 goto out_no_vpd;
1da177e4 14477
535a490e 14478 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
4181b2c8
MC		 14479 if (i < 0)
14480 goto out_not_found;
1da177e4 14481
4181b2c8
MC		 14482 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
14483 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
14484 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 14485
535a490e 14486 if (block_end > vpdlen)
4181b2c8 14487 goto out_not_found;
af2c6a4a 14488
184b8904
MC		 14489 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
14490 PCI_VPD_RO_KEYWORD_MFR_ID);
14491 if (j > 0) {
14492 len = pci_vpd_info_field_size(&vpd_data[j]);
14493
14494 j += PCI_VPD_INFO_FLD_HDR_SIZE;
14495 if (j + len > block_end || len != 4 ||
14496 memcmp(&vpd_data[j], "1028", 4))
14497 goto partno;
14498
14499 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
14500 PCI_VPD_RO_KEYWORD_VENDOR0);
14501 if (j < 0)
14502 goto partno;
14503
14504 len = pci_vpd_info_field_size(&vpd_data[j]);
14505
14506 j += PCI_VPD_INFO_FLD_HDR_SIZE;
14507 if (j + len > block_end)
14508 goto partno;
14509
14510 memcpy(tp->fw_ver, &vpd_data[j], len);
535a490e 14511 strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
184b8904
MC		 14512 }
14513
14514partno:
4181b2c8
MC		 14515 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
14516 PCI_VPD_RO_KEYWORD_PARTNO);
14517 if (i < 0)
14518 goto out_not_found;
af2c6a4a 14519
4181b2c8 14520 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 14521
4181b2c8
MC		 14522 i += PCI_VPD_INFO_FLD_HDR_SIZE;
14523 if (len > TG3_BPN_SIZE ||
535a490e 14524 (len + i) > vpdlen)
4181b2c8 14525 goto out_not_found;
1da177e4 14526
4181b2c8 14527 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 14528
1da177e4 14529out_not_found:
a4a8bb15 14530 kfree(vpd_data);
37a949c5 14531 if (tp->board_part_number[0])
a4a8bb15
MC		 14532 return;
14533
14534out_no_vpd:
37a949c5 14535 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
79d49695
MC		 14536 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
14537 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
37a949c5
MC		 14538 strcpy(tp->board_part_number, "BCM5717");
14539 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
14540 strcpy(tp->board_part_number, "BCM5718");
14541 else
14542 goto nomatch;
14543 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14544 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
14545 strcpy(tp->board_part_number, "BCM57780");
14546 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
14547 strcpy(tp->board_part_number, "BCM57760");
14548 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
14549 strcpy(tp->board_part_number, "BCM57790");
14550 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
14551 strcpy(tp->board_part_number, "BCM57788");
14552 else
14553 goto nomatch;
14554 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14555 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
14556 strcpy(tp->board_part_number, "BCM57761");
14557 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
14558 strcpy(tp->board_part_number, "BCM57765");
14559 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
14560 strcpy(tp->board_part_number, "BCM57781");
14561 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
14562 strcpy(tp->board_part_number, "BCM57785");
14563 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
14564 strcpy(tp->board_part_number, "BCM57791");
14565 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
14566 strcpy(tp->board_part_number, "BCM57795");
14567 else
14568 goto nomatch;
55086ad9
MC		 14569 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) {
14570 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
14571 strcpy(tp->board_part_number, "BCM57762");
14572 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
14573 strcpy(tp->board_part_number, "BCM57766");
14574 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
14575 strcpy(tp->board_part_number, "BCM57782");
14576 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
14577 strcpy(tp->board_part_number, "BCM57786");
14578 else
14579 goto nomatch;
37a949c5 14580 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
b5d3772c 14581 strcpy(tp->board_part_number, "BCM95906");
37a949c5
MC		 14582 } else {
14583nomatch:
b5d3772c 14584 strcpy(tp->board_part_number, "none");
37a949c5 14585 }
1da177e4
LT		 14586}
14587
229b1ad1 14588static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
9c8a620e
MC		 14589{
14590 u32 val;
14591
e4f34110 14592 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 14593 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 14594 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 14595 val != 0)
14596 return 0;
14597
14598 return 1;
14599}
14600
229b1ad1 14601static void tg3_read_bc_ver(struct tg3 *tp)
acd9c119 14602{
ff3a7cb2 14603 u32 val, offset, start, ver_offset;
75f9936e 14604 int i, dst_off;
ff3a7cb2 14605 bool newver = false;
acd9c119
MC		 14606
14607 if (tg3_nvram_read(tp, 0xc, &offset) ||
14608 tg3_nvram_read(tp, 0x4, &start))
14609 return;
14610
14611 offset = tg3_nvram_logical_addr(tp, offset);
14612
ff3a7cb2 14613 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 14614 return;
14615
ff3a7cb2
MC		 14616 if ((val & 0xfc000000) == 0x0c000000) {
14617 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 14618 return;
14619
ff3a7cb2
MC		 14620 if (val == 0)
14621 newver = true;
14622 }
14623
75f9936e
MC		 14624 dst_off = strlen(tp->fw_ver);
14625
ff3a7cb2 14626 if (newver) {
75f9936e
MC		 14627 if (TG3_VER_SIZE - dst_off < 16 ||
14628 tg3_nvram_read(tp, offset + 8, &ver_offset))
ff3a7cb2
MC		 14629 return;
14630
14631 offset = offset + ver_offset - start;
14632 for (i = 0; i < 16; i += 4) {
14633 __be32 v;
14634 if (tg3_nvram_read_be32(tp, offset + i, &v))
14635 return;
14636
75f9936e 14637 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
ff3a7cb2
MC		 14638 }
14639 } else {
14640 u32 major, minor;
14641
14642 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
14643 return;
14644
14645 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
14646 TG3_NVM_BCVER_MAJSFT;
14647 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
75f9936e
MC		 14648 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
14649 "v%d.%02d", major, minor);
acd9c119
MC		 14650 }
14651}
14652
229b1ad1 14653static void tg3_read_hwsb_ver(struct tg3 *tp)
a6f6cb1c
MC		 14654{
14655 u32 val, major, minor;
14656
14657 /* Use native endian representation */
14658 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
14659 return;
14660
14661 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
14662 TG3_NVM_HWSB_CFG1_MAJSFT;
14663 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
14664 TG3_NVM_HWSB_CFG1_MINSFT;
14665
14666 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
14667}
14668
229b1ad1 14669static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
dfe00d7d
MC		 14670{
14671 u32 offset, major, minor, build;
14672
75f9936e 14673 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
dfe00d7d
MC		 14674
14675 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
14676 return;
14677
14678 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
14679 case TG3_EEPROM_SB_REVISION_0:
14680 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
14681 break;
14682 case TG3_EEPROM_SB_REVISION_2:
14683 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
14684 break;
14685 case TG3_EEPROM_SB_REVISION_3:
14686 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
14687 break;
a4153d40
MC		 14688 case TG3_EEPROM_SB_REVISION_4:
14689 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
14690 break;
14691 case TG3_EEPROM_SB_REVISION_5:
14692 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
14693 break;
bba226ac
MC		 14694 case TG3_EEPROM_SB_REVISION_6:
14695 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
14696 break;
dfe00d7d
MC		 14697 default:
14698 return;
14699 }
14700
e4f34110 14701 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 14702 return;
14703
14704 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
14705 TG3_EEPROM_SB_EDH_BLD_SHFT;
14706 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
14707 TG3_EEPROM_SB_EDH_MAJ_SHFT;
14708 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
14709
14710 if (minor > 99 || build > 26)
14711 return;
14712
75f9936e
MC		 14713 offset = strlen(tp->fw_ver);
14714 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
14715 " v%d.%02d", major, minor);
dfe00d7d
MC		 14716
14717 if (build > 0) {
75f9936e
MC		 14718 offset = strlen(tp->fw_ver);
14719 if (offset < TG3_VER_SIZE - 1)
14720 tp->fw_ver[offset] = 'a' + build - 1;
dfe00d7d
MC		 14721 }
14722}
14723
229b1ad1 14724static void tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 14725{
14726 u32 val, offset, start;
acd9c119 14727 int i, vlen;
9c8a620e
MC		 14728
14729 for (offset = TG3_NVM_DIR_START;
14730 offset < TG3_NVM_DIR_END;
14731 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 14732 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 14733 return;
14734
9c8a620e
MC		 14735 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
14736 break;
14737 }
14738
14739 if (offset == TG3_NVM_DIR_END)
14740 return;
14741
63c3a66f 14742 if (!tg3_flag(tp, 5705_PLUS))
9c8a620e 14743 start = 0x08000000;
e4f34110 14744 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 14745 return;
14746
e4f34110 14747 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 14748 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 14749 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 14750 return;
14751
14752 offset += val - start;
14753
acd9c119 14754 vlen = strlen(tp->fw_ver);
9c8a620e 14755
acd9c119
MC		 14756 tp->fw_ver[vlen++] = ',';
14757 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 14758
14759 for (i = 0; i < 4; i++) {
a9dc529d
MC		 14760 __be32 v;
14761 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 14762 return;
14763
b9fc7dc5 14764 offset += sizeof(v);
c4e6575c 14765
acd9c119
MC		 14766 if (vlen > TG3_VER_SIZE - sizeof(v)) {
14767 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 14768 break;
c4e6575c 14769 }
9c8a620e 14770
acd9c119
MC		 14771 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
14772 vlen += sizeof(v);
c4e6575c 14773 }
acd9c119
MC		 14774}
14775
229b1ad1 14776static void tg3_probe_ncsi(struct tg3 *tp)
7fd76445 14777{
7fd76445 14778 u32 apedata;
7fd76445
MC		 14779
14780 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
14781 if (apedata != APE_SEG_SIG_MAGIC)
14782 return;
14783
14784 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
14785 if (!(apedata & APE_FW_STATUS_READY))
14786 return;
14787
165f4d1c
MC		 14788 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
14789 tg3_flag_set(tp, APE_HAS_NCSI);
14790}
14791
229b1ad1 14792static void tg3_read_dash_ver(struct tg3 *tp)
165f4d1c
MC		 14793{
14794 int vlen;
14795 u32 apedata;
14796 char *fwtype;
14797
7fd76445
MC		 14798 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
14799
165f4d1c 14800 if (tg3_flag(tp, APE_HAS_NCSI))
ecc79648 14801 fwtype = "NCSI";
c86a8560
MC		 14802 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
14803 fwtype = "SMASH";
165f4d1c 14804 else
ecc79648
MC		 14805 fwtype = "DASH";
14806
7fd76445
MC		 14807 vlen = strlen(tp->fw_ver);
14808
ecc79648
MC		 14809 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
14810 fwtype,
7fd76445
MC		 14811 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
14812 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
14813 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
14814 (apedata & APE_FW_VERSION_BLDMSK));
14815}
14816
c86a8560
MC		 14817static void tg3_read_otp_ver(struct tg3 *tp)
14818{
14819 u32 val, val2;
14820
14821 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5762)
14822 return;
14823
14824 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
14825 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
14826 TG3_OTP_MAGIC0_VALID(val)) {
14827 u64 val64 = (u64) val << 32 | val2;
14828 u32 ver = 0;
14829 int i, vlen;
14830
14831 for (i = 0; i < 7; i++) {
14832 if ((val64 & 0xff) == 0)
14833 break;
14834 ver = val64 & 0xff;
14835 val64 >>= 8;
14836 }
14837 vlen = strlen(tp->fw_ver);
14838 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
14839 }
14840}
14841
229b1ad1 14842static void tg3_read_fw_ver(struct tg3 *tp)
acd9c119
MC		 14843{
14844 u32 val;
75f9936e 14845 bool vpd_vers = false;
acd9c119 14846
75f9936e
MC		 14847 if (tp->fw_ver[0] != 0)
14848 vpd_vers = true;
df259d8c 14849
63c3a66f 14850 if (tg3_flag(tp, NO_NVRAM)) {
75f9936e 14851 strcat(tp->fw_ver, "sb");
c86a8560 14852 tg3_read_otp_ver(tp);
df259d8c
MC		 14853 return;
14854 }
14855
acd9c119
MC		 14856 if (tg3_nvram_read(tp, 0, &val))
14857 return;
14858
14859 if (val == TG3_EEPROM_MAGIC)
14860 tg3_read_bc_ver(tp);
14861 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
14862 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 14863 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
14864 tg3_read_hwsb_ver(tp);
acd9c119 14865
165f4d1c
MC		 14866 if (tg3_flag(tp, ENABLE_ASF)) {
14867 if (tg3_flag(tp, ENABLE_APE)) {
14868 tg3_probe_ncsi(tp);
14869 if (!vpd_vers)
14870 tg3_read_dash_ver(tp);
14871 } else if (!vpd_vers) {
14872 tg3_read_mgmtfw_ver(tp);
14873 }
c9cab24e 14874 }
9c8a620e
MC		 14875
14876 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 14877}
14878
7cb32cf2
MC		 14879static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
14880{
63c3a66f 14881 if (tg3_flag(tp, LRG_PROD_RING_CAP))
de9f5230 14882 return TG3_RX_RET_MAX_SIZE_5717;
63c3a66f 14883 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
de9f5230 14884 return TG3_RX_RET_MAX_SIZE_5700;
7cb32cf2 14885 else
de9f5230 14886 return TG3_RX_RET_MAX_SIZE_5705;
7cb32cf2
MC		 14887}
14888
4143470c 14889static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
895950c2
JP		 14890 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
14891 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
14892 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
14893 { },
14894};
14895
229b1ad1 14896static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16c7fa7d
MC		 14897{
14898 struct pci_dev *peer;
14899 unsigned int func, devnr = tp->pdev->devfn & ~7;
14900
14901 for (func = 0; func < 8; func++) {
14902 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14903 if (peer && peer != tp->pdev)
14904 break;
14905 pci_dev_put(peer);
14906 }
14907 /* 5704 can be configured in single-port mode, set peer to
14908 * tp->pdev in that case.
14909 */
14910 if (!peer) {
14911 peer = tp->pdev;
14912 return peer;
14913 }
14914
14915 /*
14916 * We don't need to keep the refcount elevated; there's no way
14917 * to remove one half of this device without removing the other
14918 */
14919 pci_dev_put(peer);
14920
14921 return peer;
14922}
14923
229b1ad1 14924static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
42b123b1
MC		 14925{
14926 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
14927 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
14928 u32 reg;
14929
14930 /* All devices that use the alternate
14931 * ASIC REV location have a CPMU.
14932 */
14933 tg3_flag_set(tp, CPMU_PRESENT);
14934
14935 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 14936 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
42b123b1
MC		 14937 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
14938 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4
MC		 14939 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
14940 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
14941 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
14942 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727)
42b123b1
MC		 14943 reg = TG3PCI_GEN2_PRODID_ASICREV;
14944 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
14945 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
14946 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
14947 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
14948 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14949 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14950 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
14951 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
14952 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
14953 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
14954 reg = TG3PCI_GEN15_PRODID_ASICREV;
14955 else
14956 reg = TG3PCI_PRODID_ASICREV;
14957
14958 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
14959 }
14960
14961 /* Wrong chip ID in 5752 A0. This code can be removed later
14962 * as A0 is not in production.
14963 */
14964 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
14965 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
14966
79d49695
MC		 14967 if (tp->pci_chip_rev_id == CHIPREV_ID_5717_C0)
14968 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
14969
42b123b1
MC		 14970 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14971 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14972 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14973 tg3_flag_set(tp, 5717_PLUS);
14974
14975 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
14976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
14977 tg3_flag_set(tp, 57765_CLASS);
14978
c65a17f4
MC		 14979 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
14980 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762)
42b123b1
MC		 14981 tg3_flag_set(tp, 57765_PLUS);
14982
14983 /* Intentionally exclude ASIC_REV_5906 */
14984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14985 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14988 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14989 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14990 tg3_flag(tp, 57765_PLUS))
14991 tg3_flag_set(tp, 5755_PLUS);
14992
14993 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
14994 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
14995 tg3_flag_set(tp, 5780_CLASS);
14996
14997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14999 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
15000 tg3_flag(tp, 5755_PLUS) ||
15001 tg3_flag(tp, 5780_CLASS))
15002 tg3_flag_set(tp, 5750_PLUS);
15003
15004 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
15005 tg3_flag(tp, 5750_PLUS))
15006 tg3_flag_set(tp, 5705_PLUS);
15007}
15008
3d567e0e
NNS		 15009static bool tg3_10_100_only_device(struct tg3 *tp,
15010 const struct pci_device_id *ent)
15011{
15012 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
15013
15014 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
15015 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
15016 (tp->phy_flags & TG3_PHYFLG_IS_FET))
15017 return true;
15018
15019 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
15020 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
15021 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
15022 return true;
15023 } else {
15024 return true;
15025 }
15026 }
15027
15028 return false;
15029}
15030
1dd06ae8 15031static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
1da177e4 15032{
1da177e4 15033 u32 misc_ctrl_reg;
1da177e4
LT		 15034 u32 pci_state_reg, grc_misc_cfg;
15035 u32 val;
15036 u16 pci_cmd;
5e7dfd0f 15037 int err;
1da177e4 15038
1da177e4
LT		 15039 /* Force memory write invalidate off. If we leave it on,
15040 * then on 5700_BX chips we have to enable a workaround.
15041 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
15042 * to match the cacheline size. The Broadcom driver have this
15043 * workaround but turns MWI off all the times so never uses
15044 * it. This seems to suggest that the workaround is insufficient.
15045 */
15046 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
15047 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
15048 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
15049
16821285
MC		 15050 /* Important! -- Make sure register accesses are byteswapped
15051 * correctly. Also, for those chips that require it, make
15052 * sure that indirect register accesses are enabled before
15053 * the first operation.
1da177e4
LT		 15054 */
15055 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15056 &misc_ctrl_reg);
16821285
MC		 15057 tp->misc_host_ctrl |= (misc_ctrl_reg &
15058 MISC_HOST_CTRL_CHIPREV);
15059 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15060 tp->misc_host_ctrl);
1da177e4 15061
42b123b1 15062 tg3_detect_asic_rev(tp, misc_ctrl_reg);
ff645bec 15063
6892914f
MC		 15064 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
15065 * we need to disable memory and use config. cycles
15066 * only to access all registers. The 5702/03 chips
15067 * can mistakenly decode the special cycles from the
15068 * ICH chipsets as memory write cycles, causing corruption
15069 * of register and memory space. Only certain ICH bridges
15070 * will drive special cycles with non-zero data during the
15071 * address phase which can fall within the 5703's address
15072 * range. This is not an ICH bug as the PCI spec allows
15073 * non-zero address during special cycles. However, only
15074 * these ICH bridges are known to drive non-zero addresses
15075 * during special cycles.
15076 *
15077 * Since special cycles do not cross PCI bridges, we only
15078 * enable this workaround if the 5703 is on the secondary
15079 * bus of these ICH bridges.
15080 */
15081 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
15082 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
15083 static struct tg3_dev_id {
15084 u32 vendor;
15085 u32 device;
15086 u32 rev;
15087 } ich_chipsets[] = {
15088 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
15089 PCI_ANY_ID },
15090 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
15091 PCI_ANY_ID },
15092 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
15093 0xa },
15094 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
15095 PCI_ANY_ID },
15096 { },
15097 };
15098 struct tg3_dev_id *pci_id = &ich_chipsets[0];
15099 struct pci_dev *bridge = NULL;
15100
15101 while (pci_id->vendor != 0) {
15102 bridge = pci_get_device(pci_id->vendor, pci_id->device,
15103 bridge);
15104 if (!bridge) {
15105 pci_id++;
15106 continue;
15107 }
15108 if (pci_id->rev != PCI_ANY_ID) {
44c10138 15109 if (bridge->revision > pci_id->rev)
6892914f
MC		 15110 continue;
15111 }
15112 if (bridge->subordinate &&
15113 (bridge->subordinate->number ==
15114 tp->pdev->bus->number)) {
63c3a66f 15115 tg3_flag_set(tp, ICH_WORKAROUND);
6892914f
MC		 15116 pci_dev_put(bridge);
15117 break;
15118 }
15119 }
15120 }
15121
6ff6f81d 15122 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
41588ba1
MC		 15123 static struct tg3_dev_id {
15124 u32 vendor;
15125 u32 device;
15126 } bridge_chipsets[] = {
15127 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
15128 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
15129 { },
15130 };
15131 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
15132 struct pci_dev *bridge = NULL;
15133
15134 while (pci_id->vendor != 0) {
15135 bridge = pci_get_device(pci_id->vendor,
15136 pci_id->device,
15137 bridge);
15138 if (!bridge) {
15139 pci_id++;
15140 continue;
15141 }
15142 if (bridge->subordinate &&
15143 (bridge->subordinate->number <=
15144 tp->pdev->bus->number) &&
b918c62e 15145 (bridge->subordinate->busn_res.end >=
41588ba1 15146 tp->pdev->bus->number)) {
63c3a66f 15147 tg3_flag_set(tp, 5701_DMA_BUG);
41588ba1
MC		 15148 pci_dev_put(bridge);
15149 break;
15150 }
15151 }
15152 }
15153
4a29cc2e
MC		 15154 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
15155 * DMA addresses > 40-bit. This bridge may have other additional
15156 * 57xx devices behind it in some 4-port NIC designs for example.
15157 * Any tg3 device found behind the bridge will also need the 40-bit
15158 * DMA workaround.
15159 */
42b123b1 15160 if (tg3_flag(tp, 5780_CLASS)) {
63c3a66f 15161 tg3_flag_set(tp, 40BIT_DMA_BUG);
4cf78e4f 15162 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
859a5887 15163 } else {
4a29cc2e
MC		 15164 struct pci_dev *bridge = NULL;
15165
15166 do {
15167 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
15168 PCI_DEVICE_ID_SERVERWORKS_EPB,
15169 bridge);
15170 if (bridge && bridge->subordinate &&
15171 (bridge->subordinate->number <=
15172 tp->pdev->bus->number) &&
b918c62e 15173 (bridge->subordinate->busn_res.end >=
4a29cc2e 15174 tp->pdev->bus->number)) {
63c3a66f 15175 tg3_flag_set(tp, 40BIT_DMA_BUG);
4a29cc2e
MC		 15176 pci_dev_put(bridge);
15177 break;
15178 }
15179 } while (bridge);
15180 }
4cf78e4f 15181
f6eb9b1f 15182 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3a1e19d3 15183 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
7544b097
MC		 15184 tp->pdev_peer = tg3_find_peer(tp);
15185
507399f1 15186 /* Determine TSO capabilities */
a0512944 15187 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
4d163b75 15188 ; /* Do nothing. HW bug. */
63c3a66f
JP		 15189 else if (tg3_flag(tp, 57765_PLUS))
15190 tg3_flag_set(tp, HW_TSO_3);
15191 else if (tg3_flag(tp, 5755_PLUS) ||
e849cdc3 15192 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
63c3a66f
JP		 15193 tg3_flag_set(tp, HW_TSO_2);
15194 else if (tg3_flag(tp, 5750_PLUS)) {
15195 tg3_flag_set(tp, HW_TSO_1);
15196 tg3_flag_set(tp, TSO_BUG);
507399f1
MC		 15197 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
15198 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
63c3a66f 15199 tg3_flag_clear(tp, TSO_BUG);
507399f1
MC		 15200 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15201 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
15202 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
63c3a66f 15203 tg3_flag_set(tp, TSO_BUG);
507399f1
MC		 15204 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
15205 tp->fw_needed = FIRMWARE_TG3TSO5;
15206 else
15207 tp->fw_needed = FIRMWARE_TG3TSO;
15208 }
15209
dabc5c67 15210 /* Selectively allow TSO based on operating conditions */
6ff6f81d
MC		 15211 if (tg3_flag(tp, HW_TSO_1) ||
15212 tg3_flag(tp, HW_TSO_2) ||
15213 tg3_flag(tp, HW_TSO_3) ||
cf9ecf4b
MC		 15214 tp->fw_needed) {
15215 /* For firmware TSO, assume ASF is disabled.
15216 * We'll disable TSO later if we discover ASF
15217 * is enabled in tg3_get_eeprom_hw_cfg().
15218 */
dabc5c67 15219 tg3_flag_set(tp, TSO_CAPABLE);
cf9ecf4b 15220 } else {
dabc5c67
MC		 15221 tg3_flag_clear(tp, TSO_CAPABLE);
15222 tg3_flag_clear(tp, TSO_BUG);
15223 tp->fw_needed = NULL;
15224 }
15225
15226 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
15227 tp->fw_needed = FIRMWARE_TG3;
15228
507399f1
MC		 15229 tp->irq_max = 1;
15230
63c3a66f
JP		 15231 if (tg3_flag(tp, 5750_PLUS)) {
15232 tg3_flag_set(tp, SUPPORT_MSI);
7544b097
MC		 15233 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
15234 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
15235 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
15236 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
15237 tp->pdev_peer == tp->pdev))
63c3a66f 15238 tg3_flag_clear(tp, SUPPORT_MSI);
7544b097 15239
63c3a66f 15240 if (tg3_flag(tp, 5755_PLUS) ||
b5d3772c 15241 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
63c3a66f 15242 tg3_flag_set(tp, 1SHOT_MSI);
52c0fd83 15243 }
4f125f42 15244
63c3a66f
JP		 15245 if (tg3_flag(tp, 57765_PLUS)) {
15246 tg3_flag_set(tp, SUPPORT_MSIX);
507399f1
MC		 15247 tp->irq_max = TG3_IRQ_MAX_VECS;
15248 }
f6eb9b1f 15249 }
0e1406dd 15250
9102426a
MC		 15251 tp->txq_max = 1;
15252 tp->rxq_max = 1;
15253 if (tp->irq_max > 1) {
15254 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
15255 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
15256
15257 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
15258 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
15259 tp->txq_max = tp->irq_max - 1;
15260 }
15261
b7abee6e
MC		 15262 if (tg3_flag(tp, 5755_PLUS) ||
15263 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
63c3a66f 15264 tg3_flag_set(tp, SHORT_DMA_BUG);
f6eb9b1f 15265
e31aa987 15266 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
a4cb428d 15267 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
e31aa987 15268
fa6b2aae
MC		 15269 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
15270 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
c65a17f4
MC		 15271 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
15272 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762)
63c3a66f 15273 tg3_flag_set(tp, LRG_PROD_RING_CAP);
de9f5230 15274
63c3a66f 15275 if (tg3_flag(tp, 57765_PLUS) &&
a0512944 15276 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
63c3a66f 15277 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
b703df6f 15278
63c3a66f
JP		 15279 if (!tg3_flag(tp, 5705_PLUS) ||
15280 tg3_flag(tp, 5780_CLASS) ||
15281 tg3_flag(tp, USE_JUMBO_BDFLAG))
15282 tg3_flag_set(tp, JUMBO_CAPABLE);
0f893dc6 15283
52f4490c
MC		 15284 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
15285 &pci_state_reg);
15286
708ebb3a 15287 if (pci_is_pcie(tp->pdev)) {
5e7dfd0f
MC		 15288 u16 lnkctl;
15289
63c3a66f 15290 tg3_flag_set(tp, PCI_EXPRESS);
5f5c51e3 15291
0f49bfbd 15292 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
5e7dfd0f 15293 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
7196cd6c
MC		 15294 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
15295 ASIC_REV_5906) {
63c3a66f 15296 tg3_flag_clear(tp, HW_TSO_2);
dabc5c67 15297 tg3_flag_clear(tp, TSO_CAPABLE);
7196cd6c 15298 }
5e7dfd0f 15299 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 15300 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 15301 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
15302 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
63c3a66f 15303 tg3_flag_set(tp, CLKREQ_BUG);
614b0590 15304 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
63c3a66f 15305 tg3_flag_set(tp, L1PLLPD_EN);
c7835a77 15306 }
52f4490c 15307 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
708ebb3a
JM		 15308 /* BCM5785 devices are effectively PCIe devices, and should
15309 * follow PCIe codepaths, but do not have a PCIe capabilities
15310 * section.
93a700a9 15311 */
63c3a66f
JP		 15312 tg3_flag_set(tp, PCI_EXPRESS);
15313 } else if (!tg3_flag(tp, 5705_PLUS) ||
15314 tg3_flag(tp, 5780_CLASS)) {
52f4490c
MC		 15315 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
15316 if (!tp->pcix_cap) {
2445e461
MC		 15317 dev_err(&tp->pdev->dev,
15318 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 15319 return -EIO;
15320 }
15321
15322 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
63c3a66f 15323 tg3_flag_set(tp, PCIX_MODE);
52f4490c 15324 }
1da177e4 15325
399de50b
MC		 15326 /* If we have an AMD 762 or VIA K8T800 chipset, write
15327 * reordering to the mailbox registers done by the host
15328 * controller can cause major troubles. We read back from
15329 * every mailbox register write to force the writes to be
15330 * posted to the chip in order.
15331 */
4143470c 15332 if (pci_dev_present(tg3_write_reorder_chipsets) &&
63c3a66f
JP		 15333 !tg3_flag(tp, PCI_EXPRESS))
15334 tg3_flag_set(tp, MBOX_WRITE_REORDER);
399de50b 15335
69fc4053
MC		 15336 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
15337 &tp->pci_cacheline_sz);
15338 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
15339 &tp->pci_lat_timer);
1da177e4
LT		 15340 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
15341 tp->pci_lat_timer < 64) {
15342 tp->pci_lat_timer = 64;
69fc4053
MC		 15343 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
15344 tp->pci_lat_timer);
1da177e4
LT		 15345 }
15346
16821285
MC		 15347 /* Important! -- It is critical that the PCI-X hw workaround
15348 * situation is decided before the first MMIO register access.
15349 */
52f4490c
MC		 15350 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
15351 /* 5700 BX chips need to have their TX producer index
15352 * mailboxes written twice to workaround a bug.
15353 */
63c3a66f 15354 tg3_flag_set(tp, TXD_MBOX_HWBUG);
1da177e4 15355
52f4490c 15356 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 15357 *
15358 * The workaround is to use indirect register accesses
15359 * for all chip writes not to mailbox registers.
15360 */
63c3a66f 15361 if (tg3_flag(tp, PCIX_MODE)) {
1da177e4 15362 u32 pm_reg;
1da177e4 15363
63c3a66f 15364 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 15365
15366 /* The chip can have it's power management PCI config
15367 * space registers clobbered due to this bug.
15368 * So explicitly force the chip into D0 here.
15369 */
9974a356
MC		 15370 pci_read_config_dword(tp->pdev,
15371 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 15372 &pm_reg);
15373 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
15374 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 15375 pci_write_config_dword(tp->pdev,
15376 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 15377 pm_reg);
15378
15379 /* Also, force SERR#/PERR# in PCI command. */
15380 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
15381 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
15382 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
15383 }
15384 }
15385
1da177e4 15386 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
63c3a66f 15387 tg3_flag_set(tp, PCI_HIGH_SPEED);
1da177e4 15388 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
63c3a66f 15389 tg3_flag_set(tp, PCI_32BIT);
1da177e4
LT		 15390
15391 /* Chip-specific fixup from Broadcom driver */
15392 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
15393 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
15394 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
15395 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
15396 }
15397
1ee582d8 15398 /* Default fast path register access methods */
20094930 15399 tp->read32 = tg3_read32;
1ee582d8 15400 tp->write32 = tg3_write32;
09ee929c 15401 tp->read32_mbox = tg3_read32;
20094930 15402 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 15403 tp->write32_tx_mbox = tg3_write32;
15404 tp->write32_rx_mbox = tg3_write32;
15405
15406 /* Various workaround register access methods */
63c3a66f 15407 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
1ee582d8 15408 tp->write32 = tg3_write_indirect_reg32;
98efd8a6 15409 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
63c3a66f 15410 (tg3_flag(tp, PCI_EXPRESS) &&
98efd8a6
MC		 15411 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
15412 /*
15413 * Back to back register writes can cause problems on these
15414 * chips, the workaround is to read back all reg writes
15415 * except those to mailbox regs.
15416 *
15417 * See tg3_write_indirect_reg32().
15418 */
1ee582d8 15419 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 15420 }
15421
63c3a66f 15422 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
1ee582d8 15423 tp->write32_tx_mbox = tg3_write32_tx_mbox;
63c3a66f 15424 if (tg3_flag(tp, MBOX_WRITE_REORDER))
1ee582d8
MC		 15425 tp->write32_rx_mbox = tg3_write_flush_reg32;
15426 }
20094930 15427
63c3a66f 15428 if (tg3_flag(tp, ICH_WORKAROUND)) {
6892914f
MC		 15429 tp->read32 = tg3_read_indirect_reg32;
15430 tp->write32 = tg3_write_indirect_reg32;
15431 tp->read32_mbox = tg3_read_indirect_mbox;
15432 tp->write32_mbox = tg3_write_indirect_mbox;
15433 tp->write32_tx_mbox = tg3_write_indirect_mbox;
15434 tp->write32_rx_mbox = tg3_write_indirect_mbox;
15435
15436 iounmap(tp->regs);
22abe310 15437 tp->regs = NULL;
6892914f
MC		 15438
15439 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
15440 pci_cmd &= ~PCI_COMMAND_MEMORY;
15441 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
15442 }
b5d3772c
MC		 15443 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
15444 tp->read32_mbox = tg3_read32_mbox_5906;
15445 tp->write32_mbox = tg3_write32_mbox_5906;
15446 tp->write32_tx_mbox = tg3_write32_mbox_5906;
15447 tp->write32_rx_mbox = tg3_write32_mbox_5906;
15448 }
6892914f 15449
bbadf503 15450 if (tp->write32 == tg3_write_indirect_reg32 ||
63c3a66f 15451 (tg3_flag(tp, PCIX_MODE) &&
bbadf503 15452 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 15453 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
63c3a66f 15454 tg3_flag_set(tp, SRAM_USE_CONFIG);
bbadf503 15455
16821285
MC		 15456 /* The memory arbiter has to be enabled in order for SRAM accesses
15457 * to succeed. Normally on powerup the tg3 chip firmware will make
15458 * sure it is enabled, but other entities such as system netboot
15459 * code might disable it.
15460 */
15461 val = tr32(MEMARB_MODE);
15462 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
15463
9dc5e342
MC		 15464 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
15465 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
15466 tg3_flag(tp, 5780_CLASS)) {
15467 if (tg3_flag(tp, PCIX_MODE)) {
15468 pci_read_config_dword(tp->pdev,
15469 tp->pcix_cap + PCI_X_STATUS,
15470 &val);
15471 tp->pci_fn = val & 0x7;
15472 }
857001f0
MC		 15473 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
15474 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9dc5e342
MC		 15475 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
15476 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
857001f0
MC		 15477 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
15478 val = tr32(TG3_CPMU_STATUS);
15479
15480 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
15481 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
15482 else
9dc5e342
MC		 15483 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
15484 TG3_CPMU_STATUS_FSHFT_5719;
69f11c99
MC		 15485 }
15486
7d0c41ef 15487 /* Get eeprom hw config before calling tg3_set_power_state().
63c3a66f 15488 * In particular, the TG3_FLAG_IS_NIC flag must be
7d0c41ef
MC		 15489 * determined before calling tg3_set_power_state() so that
15490 * we know whether or not to switch out of Vaux power.
15491 * When the flag is set, it means that GPIO1 is used for eeprom
15492 * write protect and also implies that it is a LOM where GPIOs
15493 * are not used to switch power.
6aa20a22 15494 */
7d0c41ef
MC		 15495 tg3_get_eeprom_hw_cfg(tp);
15496
cf9ecf4b
MC		 15497 if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) {
15498 tg3_flag_clear(tp, TSO_CAPABLE);
15499 tg3_flag_clear(tp, TSO_BUG);
15500 tp->fw_needed = NULL;
15501 }
15502
63c3a66f 15503 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 15504 /* Allow reads and writes to the
15505 * APE register and memory space.
15506 */
15507 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 15508 PCISTATE_ALLOW_APE_SHMEM_WR |
15509 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 15510 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
15511 pci_state_reg);
c9cab24e
MC		 15512
15513 tg3_ape_lock_init(tp);
0d3031d9
MC		 15514 }
15515
16821285
MC		 15516 /* Set up tp->grc_local_ctrl before calling
15517 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
15518 * will bring 5700's external PHY out of reset.
314fba34
MC		 15519 * It is also used as eeprom write protect on LOMs.
15520 */
15521 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
6ff6f81d 15522 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
63c3a66f 15523 tg3_flag(tp, EEPROM_WRITE_PROT))
314fba34
MC		 15524 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
15525 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 15526 /* Unused GPIO3 must be driven as output on 5752 because there
15527 * are no pull-up resistors on unused GPIO pins.
15528 */
15529 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
15530 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 15531
321d32a0 15532 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
cb4ed1fd 15533 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
55086ad9 15534 tg3_flag(tp, 57765_CLASS))
af36e6b6
MC		 15535 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
15536
8d519ab2
MC		 15537 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
15538 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 15539 /* Turn off the debug UART. */
15540 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
63c3a66f 15541 if (tg3_flag(tp, IS_NIC))
5f0c4a3c
MC		 15542 /* Keep VMain power. */
15543 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
15544 GRC_LCLCTRL_GPIO_OUTPUT0;
15545 }
15546
c86a8560
MC		 15547 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762)
15548 tp->grc_local_ctrl |=
15549 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
15550
16821285
MC		 15551 /* Switch out of Vaux if it is a NIC */
15552 tg3_pwrsrc_switch_to_vmain(tp);
1da177e4 15553
1da177e4
LT		 15554 /* Derive initial jumbo mode from MTU assigned in
15555 * ether_setup() via the alloc_etherdev() call
15556 */
63c3a66f
JP		 15557 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
15558 tg3_flag_set(tp, JUMBO_RING_ENABLE);
1da177e4
LT		 15559
15560 /* Determine WakeOnLan speed to use. */
15561 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
15562 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
15563 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
15564 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
63c3a66f 15565 tg3_flag_clear(tp, WOL_SPEED_100MB);
1da177e4 15566 } else {
63c3a66f 15567 tg3_flag_set(tp, WOL_SPEED_100MB);
1da177e4
LT		 15568 }
15569
7f97a4bd 15570 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
f07e9af3 15571 tp->phy_flags |= TG3_PHYFLG_IS_FET;
7f97a4bd 15572
1da177e4 15573 /* A few boards don't want Ethernet@WireSpeed phy feature */
6ff6f81d
MC		 15574 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
15575 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
1da177e4 15576 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 15577 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
f07e9af3
MC		 15578 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
15579 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15580 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
1da177e4
LT		 15581
15582 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
15583 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
f07e9af3 15584 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
1da177e4 15585 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
f07e9af3 15586 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
1da177e4 15587
63c3a66f 15588 if (tg3_flag(tp, 5705_PLUS) &&
f07e9af3 15589 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
321d32a0 15590 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f 15591 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
63c3a66f 15592 !tg3_flag(tp, 57765_PLUS)) {
c424cb24 15593 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 15594 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 15595 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
15596 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 15597 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
15598 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
f07e9af3 15599 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
c1d2a196 15600 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
f07e9af3 15601 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
321d32a0 15602 } else
f07e9af3 15603 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
c424cb24 15604 }
1da177e4 15605
b2a5c19c
MC		 15606 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15607 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
15608 tp->phy_otp = tg3_read_otp_phycfg(tp);
15609 if (tp->phy_otp == 0)
15610 tp->phy_otp = TG3_OTP_DEFAULT;
15611 }
15612
63c3a66f 15613 if (tg3_flag(tp, CPMU_PRESENT))
8ef21428
MC		 15614 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
15615 else
15616 tp->mi_mode = MAC_MI_MODE_BASE;
15617
1da177e4 15618 tp->coalesce_mode = 0;
1da177e4
LT		 15619 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
15620 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
15621 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
15622
4d958473
MC		 15623 /* Set these bits to enable statistics workaround. */
15624 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
15625 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
15626 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
15627 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
15628 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
15629 }
15630
321d32a0
MC		 15631 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15632 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
63c3a66f 15633 tg3_flag_set(tp, USE_PHYLIB);
57e6983c 15634
158d7abd
MC		 15635 err = tg3_mdio_init(tp);
15636 if (err)
15637 return err;
1da177e4
LT		 15638
15639 /* Initialize data/descriptor byte/word swapping. */
15640 val = tr32(GRC_MODE);
c65a17f4
MC		 15641 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
15642 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762)
f2096f94
MC		 15643 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
15644 GRC_MODE_WORD_SWAP_B2HRX_DATA |
15645 GRC_MODE_B2HRX_ENABLE |
15646 GRC_MODE_HTX2B_ENABLE |
15647 GRC_MODE_HOST_STACKUP);
15648 else
15649 val &= GRC_MODE_HOST_STACKUP;
15650
1da177e4
LT		 15651 tw32(GRC_MODE, val | tp->grc_mode);
15652
15653 tg3_switch_clocks(tp);
15654
15655 /* Clear this out for sanity. */
15656 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
15657
15658 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
15659 &pci_state_reg);
15660 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
63c3a66f 15661 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
1da177e4
LT		 15662 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
15663
15664 if (chiprevid == CHIPREV_ID_5701_A0 ||
15665 chiprevid == CHIPREV_ID_5701_B0 ||
15666 chiprevid == CHIPREV_ID_5701_B2 ||
15667 chiprevid == CHIPREV_ID_5701_B5) {
15668 void __iomem *sram_base;
15669
15670 /* Write some dummy words into the SRAM status block
15671 * area, see if it reads back correctly. If the return
15672 * value is bad, force enable the PCIX workaround.
15673 */
15674 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
15675
15676 writel(0x00000000, sram_base);
15677 writel(0x00000000, sram_base + 4);
15678 writel(0xffffffff, sram_base + 4);
15679 if (readl(sram_base) != 0x00000000)
63c3a66f 15680 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 15681 }
15682 }
15683
15684 udelay(50);
15685 tg3_nvram_init(tp);
15686
15687 grc_misc_cfg = tr32(GRC_MISC_CFG);
15688 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
15689
1da177e4
LT		 15690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
15691 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
15692 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
63c3a66f 15693 tg3_flag_set(tp, IS_5788);
1da177e4 15694
63c3a66f 15695 if (!tg3_flag(tp, IS_5788) &&
6ff6f81d 15696 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
63c3a66f
JP		 15697 tg3_flag_set(tp, TAGGED_STATUS);
15698 if (tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 15699 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
15700 HOSTCC_MODE_CLRTICK_TXBD);
15701
15702 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
15703 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15704 tp->misc_host_ctrl);
15705 }
15706
3bda1258 15707 /* Preserve the APE MAC_MODE bits */
63c3a66f 15708 if (tg3_flag(tp, ENABLE_APE))
d2394e6b 15709 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
3bda1258 15710 else
6e01b20b 15711 tp->mac_mode = 0;
3bda1258 15712
3d567e0e 15713 if (tg3_10_100_only_device(tp, ent))
f07e9af3 15714 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
1da177e4
LT		 15715
15716 err = tg3_phy_probe(tp);
15717 if (err) {
2445e461 15718 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 15719 /* ... but do not return immediately ... */
b02fd9e3 15720 tg3_mdio_fini(tp);
1da177e4
LT		 15721 }
15722
184b8904 15723 tg3_read_vpd(tp);
c4e6575c 15724 tg3_read_fw_ver(tp);
1da177e4 15725
f07e9af3
MC		 15726 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
15727 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4
LT		 15728 } else {
15729 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
f07e9af3 15730 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 15731 else
f07e9af3 15732 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4
LT		 15733 }
15734
15735 /* 5700 {AX,BX} chips have a broken status block link
15736 * change bit implementation, so we must use the
15737 * status register in those cases.
15738 */
15739 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
63c3a66f 15740 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4 15741 else
63c3a66f 15742 tg3_flag_clear(tp, USE_LINKCHG_REG);
1da177e4
LT		 15743
15744 /* The led_ctrl is set during tg3_phy_probe, here we might
15745 * have to force the link status polling mechanism based
15746 * upon subsystem IDs.
15747 */
15748 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 15749 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
f07e9af3
MC		 15750 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
15751 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
63c3a66f 15752 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4
LT		 15753 }
15754
15755 /* For all SERDES we poll the MAC status register. */
f07e9af3 15756 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
63c3a66f 15757 tg3_flag_set(tp, POLL_SERDES);
1da177e4 15758 else
63c3a66f 15759 tg3_flag_clear(tp, POLL_SERDES);
1da177e4 15760
9205fd9c 15761 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
d2757fc4 15762 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
1da177e4 15763 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
63c3a66f 15764 tg3_flag(tp, PCIX_MODE)) {
9205fd9c 15765 tp->rx_offset = NET_SKB_PAD;
d2757fc4 15766#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
9dc7a113 15767 tp->rx_copy_thresh = ~(u16)0;
d2757fc4
MC		 15768#endif
15769 }
1da177e4 15770
2c49a44d
MC		 15771 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
15772 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
7cb32cf2
MC		 15773 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
15774
2c49a44d 15775 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
f92905de
MC		 15776
15777 /* Increment the rx prod index on the rx std ring by at most
15778 * 8 for these chips to workaround hw errata.
15779 */
15780 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
15781 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
15782 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
15783 tp->rx_std_max_post = 8;
15784
63c3a66f 15785 if (tg3_flag(tp, ASPM_WORKAROUND))
8ed5d97e
MC		 15786 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
15787 PCIE_PWR_MGMT_L1_THRESH_MSK;
15788
1da177e4
LT		 15789 return err;
15790}
15791
49b6e95f 15792#ifdef CONFIG_SPARC
229b1ad1 15793static int tg3_get_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 15794{
15795 struct net_device *dev = tp->dev;
15796 struct pci_dev *pdev = tp->pdev;
49b6e95f 15797 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 15798 const unsigned char *addr;
49b6e95f
DM		 15799 int len;
15800
15801 addr = of_get_property(dp, "local-mac-address", &len);
15802 if (addr && len == 6) {
15803 memcpy(dev->dev_addr, addr, 6);
49b6e95f 15804 return 0;
1da177e4
LT		 15805 }
15806 return -ENODEV;
15807}
15808
229b1ad1 15809static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 15810{
15811 struct net_device *dev = tp->dev;
15812
15813 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
15814 return 0;
15815}
15816#endif
15817
229b1ad1 15818static int tg3_get_device_address(struct tg3 *tp)
1da177e4
LT		 15819{
15820 struct net_device *dev = tp->dev;
15821 u32 hi, lo, mac_offset;
008652b3 15822 int addr_ok = 0;
1da177e4 15823
49b6e95f 15824#ifdef CONFIG_SPARC
1da177e4
LT		 15825 if (!tg3_get_macaddr_sparc(tp))
15826 return 0;
15827#endif
15828
15829 mac_offset = 0x7c;
6ff6f81d 15830 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
63c3a66f 15831 tg3_flag(tp, 5780_CLASS)) {
1da177e4
LT		 15832 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
15833 mac_offset = 0xcc;
15834 if (tg3_nvram_lock(tp))
15835 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
15836 else
15837 tg3_nvram_unlock(tp);
63c3a66f 15838 } else if (tg3_flag(tp, 5717_PLUS)) {
69f11c99 15839 if (tp->pci_fn & 1)
a1b950d5 15840 mac_offset = 0xcc;
69f11c99 15841 if (tp->pci_fn > 1)
a50d0796 15842 mac_offset += 0x18c;
a1b950d5 15843 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 15844 mac_offset = 0x10;
1da177e4
LT		 15845
15846 /* First try to get it from MAC address mailbox. */
15847 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
15848 if ((hi >> 16) == 0x484b) {
15849 dev->dev_addr[0] = (hi >> 8) & 0xff;
15850 dev->dev_addr[1] = (hi >> 0) & 0xff;
15851
15852 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
15853 dev->dev_addr[2] = (lo >> 24) & 0xff;
15854 dev->dev_addr[3] = (lo >> 16) & 0xff;
15855 dev->dev_addr[4] = (lo >> 8) & 0xff;
15856 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 15857
008652b3
MC		 15858 /* Some old bootcode may report a 0 MAC address in SRAM */
15859 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
15860 }
15861 if (!addr_ok) {
15862 /* Next, try NVRAM. */
63c3a66f 15863 if (!tg3_flag(tp, NO_NVRAM) &&
df259d8c 15864 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 15865 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 15866 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
15867 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 15868 }
15869 /* Finally just fetch it out of the MAC control regs. */
15870 else {
15871 hi = tr32(MAC_ADDR_0_HIGH);
15872 lo = tr32(MAC_ADDR_0_LOW);
15873
15874 dev->dev_addr[5] = lo & 0xff;
15875 dev->dev_addr[4] = (lo >> 8) & 0xff;
15876 dev->dev_addr[3] = (lo >> 16) & 0xff;
15877 dev->dev_addr[2] = (lo >> 24) & 0xff;
15878 dev->dev_addr[1] = hi & 0xff;
15879 dev->dev_addr[0] = (hi >> 8) & 0xff;
15880 }
1da177e4
LT		 15881 }
15882
15883 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 15884#ifdef CONFIG_SPARC
1da177e4
LT		 15885 if (!tg3_get_default_macaddr_sparc(tp))
15886 return 0;
15887#endif
15888 return -EINVAL;
15889 }
15890 return 0;
15891}
15892
59e6b434
DM		 15893#define BOUNDARY_SINGLE_CACHELINE 1
15894#define BOUNDARY_MULTI_CACHELINE 2
15895
229b1ad1 15896static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
59e6b434
DM		 15897{
15898 int cacheline_size;
15899 u8 byte;
15900 int goal;
15901
15902 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
15903 if (byte == 0)
15904 cacheline_size = 1024;
15905 else
15906 cacheline_size = (int) byte * 4;
15907
15908 /* On 5703 and later chips, the boundary bits have no
15909 * effect.
15910 */
15911 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15912 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
63c3a66f 15913 !tg3_flag(tp, PCI_EXPRESS))
59e6b434
DM		 15914 goto out;
15915
15916#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
15917 goal = BOUNDARY_MULTI_CACHELINE;
15918#else
15919#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
15920 goal = BOUNDARY_SINGLE_CACHELINE;
15921#else
15922 goal = 0;
15923#endif
15924#endif
15925
63c3a66f 15926 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 15927 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
15928 goto out;
15929 }
15930
59e6b434
DM		 15931 if (!goal)
15932 goto out;
15933
15934 /* PCI controllers on most RISC systems tend to disconnect
15935 * when a device tries to burst across a cache-line boundary.
15936 * Therefore, letting tg3 do so just wastes PCI bandwidth.
15937 *
15938 * Unfortunately, for PCI-E there are only limited
15939 * write-side controls for this, and thus for reads
15940 * we will still get the disconnects. We'll also waste
15941 * these PCI cycles for both read and write for chips
15942 * other than 5700 and 5701 which do not implement the
15943 * boundary bits.
15944 */
63c3a66f 15945 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 15946 switch (cacheline_size) {
15947 case 16:
15948 case 32:
15949 case 64:
15950 case 128:
15951 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15952 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
15953 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
15954 } else {
15955 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
15956 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
15957 }
15958 break;
15959
15960 case 256:
15961 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
15962 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
15963 break;
15964
15965 default:
15966 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
15967 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
15968 break;
855e1111 15969 }
63c3a66f 15970 } else if (tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 15971 switch (cacheline_size) {
15972 case 16:
15973 case 32:
15974 case 64:
15975 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15976 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
15977 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
15978 break;
15979 }
15980 /* fallthrough */
15981 case 128:
15982 default:
15983 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
15984 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
15985 break;
855e1111 15986 }
59e6b434
DM		 15987 } else {
15988 switch (cacheline_size) {
15989 case 16:
15990 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15991 val |= (DMA_RWCTRL_READ_BNDRY_16 |
15992 DMA_RWCTRL_WRITE_BNDRY_16);
15993 break;
15994 }
15995 /* fallthrough */
15996 case 32:
15997 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15998 val |= (DMA_RWCTRL_READ_BNDRY_32 |
15999 DMA_RWCTRL_WRITE_BNDRY_32);
16000 break;
16001 }
16002 /* fallthrough */
16003 case 64:
16004 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16005 val |= (DMA_RWCTRL_READ_BNDRY_64 |
16006 DMA_RWCTRL_WRITE_BNDRY_64);
16007 break;
16008 }
16009 /* fallthrough */
16010 case 128:
16011 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16012 val |= (DMA_RWCTRL_READ_BNDRY_128 |
16013 DMA_RWCTRL_WRITE_BNDRY_128);
16014 break;
16015 }
16016 /* fallthrough */
16017 case 256:
16018 val |= (DMA_RWCTRL_READ_BNDRY_256 |
16019 DMA_RWCTRL_WRITE_BNDRY_256);
16020 break;
16021 case 512:
16022 val |= (DMA_RWCTRL_READ_BNDRY_512 |
16023 DMA_RWCTRL_WRITE_BNDRY_512);
16024 break;
16025 case 1024:
16026 default:
16027 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
16028 DMA_RWCTRL_WRITE_BNDRY_1024);
16029 break;
855e1111 16030 }
59e6b434
DM		 16031 }
16032
16033out:
16034 return val;
16035}
16036
229b1ad1
BP		 16037static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
16038 int size, int to_device)
1da177e4
LT		 16039{
16040 struct tg3_internal_buffer_desc test_desc;
16041 u32 sram_dma_descs;
16042 int i, ret;
16043
16044 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
16045
16046 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
16047 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
16048 tw32(RDMAC_STATUS, 0);
16049 tw32(WDMAC_STATUS, 0);
16050
16051 tw32(BUFMGR_MODE, 0);
16052 tw32(FTQ_RESET, 0);
16053
16054 test_desc.addr_hi = ((u64) buf_dma) >> 32;
16055 test_desc.addr_lo = buf_dma & 0xffffffff;
16056 test_desc.nic_mbuf = 0x00002100;
16057 test_desc.len = size;
16058
16059 /*
16060 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
16061 * the *second* time the tg3 driver was getting loaded after an
16062 * initial scan.
16063 *
16064 * Broadcom tells me:
16065 * ...the DMA engine is connected to the GRC block and a DMA
16066 * reset may affect the GRC block in some unpredictable way...
16067 * The behavior of resets to individual blocks has not been tested.
16068 *
16069 * Broadcom noted the GRC reset will also reset all sub-components.
16070 */
16071 if (to_device) {
16072 test_desc.cqid_sqid = (13 << 8) | 2;
16073
16074 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
16075 udelay(40);
16076 } else {
16077 test_desc.cqid_sqid = (16 << 8) | 7;
16078
16079 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
16080 udelay(40);
16081 }
16082 test_desc.flags = 0x00000005;
16083
16084 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
16085 u32 val;
16086
16087 val = *(((u32 *)&test_desc) + i);
16088 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
16089 sram_dma_descs + (i * sizeof(u32)));
16090 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
16091 }
16092 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
16093
859a5887 16094 if (to_device)
1da177e4 16095 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
859a5887 16096 else
1da177e4 16097 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
1da177e4
LT		 16098
16099 ret = -ENODEV;
16100 for (i = 0; i < 40; i++) {
16101 u32 val;
16102
16103 if (to_device)
16104 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
16105 else
16106 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
16107 if ((val & 0xffff) == sram_dma_descs) {
16108 ret = 0;
16109 break;
16110 }
16111
16112 udelay(100);
16113 }
16114
16115 return ret;
16116}
16117
ded7340d 16118#define TEST_BUFFER_SIZE 0x2000
1da177e4 16119
4143470c 16120static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
895950c2
JP		 16121 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
16122 { },
16123};
16124
229b1ad1 16125static int tg3_test_dma(struct tg3 *tp)
1da177e4
LT		 16126{
16127 dma_addr_t buf_dma;
59e6b434 16128 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 16129 int ret = 0;
1da177e4 16130
4bae65c8
MC		 16131 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
16132 &buf_dma, GFP_KERNEL);
1da177e4
LT		 16133 if (!buf) {
16134 ret = -ENOMEM;
16135 goto out_nofree;
16136 }
16137
16138 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
16139 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
16140
59e6b434 16141 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 16142
63c3a66f 16143 if (tg3_flag(tp, 57765_PLUS))
cbf9ca6c
MC		 16144 goto out;
16145
63c3a66f 16146 if (tg3_flag(tp, PCI_EXPRESS)) {
1da177e4
LT		 16147 /* DMA read watermark not used on PCIE */
16148 tp->dma_rwctrl |= 0x00180000;
63c3a66f 16149 } else if (!tg3_flag(tp, PCIX_MODE)) {
85e94ced
MC		 16150 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
16151 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 16152 tp->dma_rwctrl |= 0x003f0000;
16153 else
16154 tp->dma_rwctrl |= 0x003f000f;
16155 } else {
16156 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
16157 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
16158 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 16159 u32 read_water = 0x7;
1da177e4 16160
4a29cc2e
MC		 16161 /* If the 5704 is behind the EPB bridge, we can
16162 * do the less restrictive ONE_DMA workaround for
16163 * better performance.
16164 */
63c3a66f 16165 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
4a29cc2e
MC		 16166 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
16167 tp->dma_rwctrl |= 0x8000;
16168 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 16169 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
16170
49afdeb6
MC		 16171 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
16172 read_water = 4;
59e6b434 16173 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 16174 tp->dma_rwctrl |=
16175 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
16176 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
16177 (1 << 23);
4cf78e4f
MC		 16178 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
16179 /* 5780 always in PCIX mode */
16180 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 16181 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
16182 /* 5714 always in PCIX mode */
16183 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 16184 } else {
16185 tp->dma_rwctrl |= 0x001b000f;
16186 }
16187 }
16188
16189 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
16190 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
16191 tp->dma_rwctrl &= 0xfffffff0;
16192
16193 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
16194 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
16195 /* Remove this if it causes problems for some boards. */
16196 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
16197
16198 /* On 5700/5701 chips, we need to set this bit.
16199 * Otherwise the chip will issue cacheline transactions
16200 * to streamable DMA memory with not all the byte
16201 * enables turned on. This is an error on several
16202 * RISC PCI controllers, in particular sparc64.
16203 *
16204 * On 5703/5704 chips, this bit has been reassigned
16205 * a different meaning. In particular, it is used
16206 * on those chips to enable a PCI-X workaround.
16207 */
16208 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
16209 }
16210
16211 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
16212
16213#if 0
16214 /* Unneeded, already done by tg3_get_invariants. */
16215 tg3_switch_clocks(tp);
16216#endif
16217
1da177e4
LT		 16218 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
16219 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
16220 goto out;
16221
59e6b434
DM		 16222 /* It is best to perform DMA test with maximum write burst size
16223 * to expose the 5700/5701 write DMA bug.
16224 */
16225 saved_dma_rwctrl = tp->dma_rwctrl;
16226 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
16227 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
16228
1da177e4
LT		 16229 while (1) {
16230 u32 *p = buf, i;
16231
16232 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
16233 p[i] = i;
16234
16235 /* Send the buffer to the chip. */
16236 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
16237 if (ret) {
2445e461
MC		 16238 dev_err(&tp->pdev->dev,
16239 "%s: Buffer write failed. err = %d\n",
16240 __func__, ret);
1da177e4
LT		 16241 break;
16242 }
16243
16244#if 0
16245 /* validate data reached card RAM correctly. */
16246 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
16247 u32 val;
16248 tg3_read_mem(tp, 0x2100 + (i*4), &val);
16249 if (le32_to_cpu(val) != p[i]) {
2445e461
MC		 16250 dev_err(&tp->pdev->dev,
16251 "%s: Buffer corrupted on device! "
16252 "(%d != %d)\n", __func__, val, i);
1da177e4
LT		 16253 /* ret = -ENODEV here? */
16254 }
16255 p[i] = 0;
16256 }
16257#endif
16258 /* Now read it back. */
16259 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
16260 if (ret) {
5129c3a3
MC		 16261 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
16262 "err = %d\n", __func__, ret);
1da177e4
LT		 16263 break;
16264 }
16265
16266 /* Verify it. */
16267 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
16268 if (p[i] == i)
16269 continue;
16270
59e6b434
DM		 16271 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
16272 DMA_RWCTRL_WRITE_BNDRY_16) {
16273 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 16274 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
16275 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
16276 break;
16277 } else {
2445e461
MC		 16278 dev_err(&tp->pdev->dev,
16279 "%s: Buffer corrupted on read back! "
16280 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 16281 ret = -ENODEV;
16282 goto out;
16283 }
16284 }
16285
16286 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
16287 /* Success. */
16288 ret = 0;
16289 break;
16290 }
16291 }
59e6b434
DM		 16292 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
16293 DMA_RWCTRL_WRITE_BNDRY_16) {
16294 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 16295 * now look for chipsets that are known to expose the
16296 * DMA bug without failing the test.
59e6b434 16297 */
4143470c 16298 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
6d1cfbab
MC		 16299 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
16300 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
859a5887 16301 } else {
6d1cfbab
MC		 16302 /* Safe to use the calculated DMA boundary. */
16303 tp->dma_rwctrl = saved_dma_rwctrl;
859a5887 16304 }
6d1cfbab 16305
59e6b434
DM		 16306 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
16307 }
1da177e4
LT		 16308
16309out:
4bae65c8 16310 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
1da177e4
LT		 16311out_nofree:
16312 return ret;
16313}
16314
229b1ad1 16315static void tg3_init_bufmgr_config(struct tg3 *tp)
1da177e4 16316{
63c3a66f 16317 if (tg3_flag(tp, 57765_PLUS)) {
666bc831
MC		 16318 tp->bufmgr_config.mbuf_read_dma_low_water =
16319 DEFAULT_MB_RDMA_LOW_WATER_5705;
16320 tp->bufmgr_config.mbuf_mac_rx_low_water =
16321 DEFAULT_MB_MACRX_LOW_WATER_57765;
16322 tp->bufmgr_config.mbuf_high_water =
16323 DEFAULT_MB_HIGH_WATER_57765;
16324
16325 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
16326 DEFAULT_MB_RDMA_LOW_WATER_5705;
16327 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
16328 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
16329 tp->bufmgr_config.mbuf_high_water_jumbo =
16330 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
63c3a66f 16331 } else if (tg3_flag(tp, 5705_PLUS)) {
fdfec172
MC		 16332 tp->bufmgr_config.mbuf_read_dma_low_water =
16333 DEFAULT_MB_RDMA_LOW_WATER_5705;
16334 tp->bufmgr_config.mbuf_mac_rx_low_water =
16335 DEFAULT_MB_MACRX_LOW_WATER_5705;
16336 tp->bufmgr_config.mbuf_high_water =
16337 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 16338 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
16339 tp->bufmgr_config.mbuf_mac_rx_low_water =
16340 DEFAULT_MB_MACRX_LOW_WATER_5906;
16341 tp->bufmgr_config.mbuf_high_water =
16342 DEFAULT_MB_HIGH_WATER_5906;
16343 }
fdfec172
MC		 16344
16345 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
16346 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
16347 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
16348 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
16349 tp->bufmgr_config.mbuf_high_water_jumbo =
16350 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
16351 } else {
16352 tp->bufmgr_config.mbuf_read_dma_low_water =
16353 DEFAULT_MB_RDMA_LOW_WATER;
16354 tp->bufmgr_config.mbuf_mac_rx_low_water =
16355 DEFAULT_MB_MACRX_LOW_WATER;
16356 tp->bufmgr_config.mbuf_high_water =
16357 DEFAULT_MB_HIGH_WATER;
16358
16359 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
16360 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
16361 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
16362 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
16363 tp->bufmgr_config.mbuf_high_water_jumbo =
16364 DEFAULT_MB_HIGH_WATER_JUMBO;
16365 }
1da177e4
LT		 16366
16367 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
16368 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
16369}
16370
229b1ad1 16371static char *tg3_phy_string(struct tg3 *tp)
1da177e4 16372{
79eb6904
MC		 16373 switch (tp->phy_id & TG3_PHY_ID_MASK) {
16374 case TG3_PHY_ID_BCM5400: return "5400";
16375 case TG3_PHY_ID_BCM5401: return "5401";
16376 case TG3_PHY_ID_BCM5411: return "5411";
16377 case TG3_PHY_ID_BCM5701: return "5701";
16378 case TG3_PHY_ID_BCM5703: return "5703";
16379 case TG3_PHY_ID_BCM5704: return "5704";
16380 case TG3_PHY_ID_BCM5705: return "5705";
16381 case TG3_PHY_ID_BCM5750: return "5750";
16382 case TG3_PHY_ID_BCM5752: return "5752";
16383 case TG3_PHY_ID_BCM5714: return "5714";
16384 case TG3_PHY_ID_BCM5780: return "5780";
16385 case TG3_PHY_ID_BCM5755: return "5755";
16386 case TG3_PHY_ID_BCM5787: return "5787";
16387 case TG3_PHY_ID_BCM5784: return "5784";
16388 case TG3_PHY_ID_BCM5756: return "5722/5756";
16389 case TG3_PHY_ID_BCM5906: return "5906";
16390 case TG3_PHY_ID_BCM5761: return "5761";
16391 case TG3_PHY_ID_BCM5718C: return "5718C";
16392 case TG3_PHY_ID_BCM5718S: return "5718S";
16393 case TG3_PHY_ID_BCM57765: return "57765";
302b500b 16394 case TG3_PHY_ID_BCM5719C: return "5719C";
6418f2c1 16395 case TG3_PHY_ID_BCM5720C: return "5720C";
c65a17f4 16396 case TG3_PHY_ID_BCM5762: return "5762C";
79eb6904 16397 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 16398 case 0: return "serdes";
16399 default: return "unknown";
855e1111 16400 }
1da177e4
LT		 16401}
16402
229b1ad1 16403static char *tg3_bus_string(struct tg3 *tp, char *str)
f9804ddb 16404{
63c3a66f 16405 if (tg3_flag(tp, PCI_EXPRESS)) {
f9804ddb
MC		 16406 strcpy(str, "PCI Express");
16407 return str;
63c3a66f 16408 } else if (tg3_flag(tp, PCIX_MODE)) {
f9804ddb
MC		 16409 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
16410
16411 strcpy(str, "PCIX:");
16412
16413 if ((clock_ctrl == 7) ||
16414 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
16415 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
16416 strcat(str, "133MHz");
16417 else if (clock_ctrl == 0)
16418 strcat(str, "33MHz");
16419 else if (clock_ctrl == 2)
16420 strcat(str, "50MHz");
16421 else if (clock_ctrl == 4)
16422 strcat(str, "66MHz");
16423 else if (clock_ctrl == 6)
16424 strcat(str, "100MHz");
f9804ddb
MC		 16425 } else {
16426 strcpy(str, "PCI:");
63c3a66f 16427 if (tg3_flag(tp, PCI_HIGH_SPEED))
f9804ddb
MC		 16428 strcat(str, "66MHz");
16429 else
16430 strcat(str, "33MHz");
16431 }
63c3a66f 16432 if (tg3_flag(tp, PCI_32BIT))
f9804ddb
MC		 16433 strcat(str, ":32-bit");
16434 else
16435 strcat(str, ":64-bit");
16436 return str;
16437}
16438
229b1ad1 16439static void tg3_init_coal(struct tg3 *tp)
15f9850d
DM		 16440{
16441 struct ethtool_coalesce *ec = &tp->coal;
16442
16443 memset(ec, 0, sizeof(*ec));
16444 ec->cmd = ETHTOOL_GCOALESCE;
16445 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
16446 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
16447 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
16448 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
16449 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
16450 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
16451 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
16452 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
16453 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
16454
16455 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
16456 HOSTCC_MODE_CLRTICK_TXBD)) {
16457 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
16458 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
16459 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
16460 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
16461 }
d244c892 16462
63c3a66f 16463 if (tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 16464 ec->rx_coalesce_usecs_irq = 0;
16465 ec->tx_coalesce_usecs_irq = 0;
16466 ec->stats_block_coalesce_usecs = 0;
16467 }
15f9850d
DM		 16468}
16469
229b1ad1 16470static int tg3_init_one(struct pci_dev *pdev,
1da177e4
LT		 16471 const struct pci_device_id *ent)
16472{
1da177e4
LT		 16473 struct net_device *dev;
16474 struct tg3 *tp;
646c9edd
MC		 16475 int i, err, pm_cap;
16476 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 16477 char str[40];
72f2afb8 16478 u64 dma_mask, persist_dma_mask;
c8f44aff 16479 netdev_features_t features = 0;
1da177e4 16480
05dbe005 16481 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 16482
16483 err = pci_enable_device(pdev);
16484 if (err) {
2445e461 16485 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 16486 return err;
16487 }
16488
1da177e4
LT		 16489 err = pci_request_regions(pdev, DRV_MODULE_NAME);
16490 if (err) {
2445e461 16491 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 16492 goto err_out_disable_pdev;
16493 }
16494
16495 pci_set_master(pdev);
16496
16497 /* Find power-management capability. */
16498 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
16499 if (pm_cap == 0) {
2445e461
MC		 16500 dev_err(&pdev->dev,
16501 "Cannot find Power Management capability, aborting\n");
1da177e4
LT		 16502 err = -EIO;
16503 goto err_out_free_res;
16504 }
16505
16821285
MC		 16506 err = pci_set_power_state(pdev, PCI_D0);
16507 if (err) {
16508 dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
16509 goto err_out_free_res;
16510 }
16511
fe5f5787 16512 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 16513 if (!dev) {
1da177e4 16514 err = -ENOMEM;
16821285 16515 goto err_out_power_down;
1da177e4
LT		 16516 }
16517
1da177e4
LT		 16518 SET_NETDEV_DEV(dev, &pdev->dev);
16519
1da177e4
LT		 16520 tp = netdev_priv(dev);
16521 tp->pdev = pdev;
16522 tp->dev = dev;
16523 tp->pm_cap = pm_cap;
1da177e4
LT		 16524 tp->rx_mode = TG3_DEF_RX_MODE;
16525 tp->tx_mode = TG3_DEF_TX_MODE;
9c13cb8b 16526 tp->irq_sync = 1;
8ef21428 16527
1da177e4
LT		 16528 if (tg3_debug > 0)
16529 tp->msg_enable = tg3_debug;
16530 else
16531 tp->msg_enable = TG3_DEF_MSG_ENABLE;
16532
16533 /* The word/byte swap controls here control register access byte
16534 * swapping. DMA data byte swapping is controlled in the GRC_MODE
16535 * setting below.
16536 */
16537 tp->misc_host_ctrl =
16538 MISC_HOST_CTRL_MASK_PCI_INT |
16539 MISC_HOST_CTRL_WORD_SWAP |
16540 MISC_HOST_CTRL_INDIR_ACCESS |
16541 MISC_HOST_CTRL_PCISTATE_RW;
16542
16543 /* The NONFRM (non-frame) byte/word swap controls take effect
16544 * on descriptor entries, anything which isn't packet data.
16545 *
16546 * The StrongARM chips on the board (one for tx, one for rx)
16547 * are running in big-endian mode.
16548 */
16549 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
16550 GRC_MODE_WSWAP_NONFRM_DATA);
16551#ifdef __BIG_ENDIAN
16552 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
16553#endif
16554 spin_lock_init(&tp->lock);
1da177e4 16555 spin_lock_init(&tp->indirect_lock);
c4028958 16556 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 16557
d5fe488a 16558 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 16559 if (!tp->regs) {
ab96b241 16560 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 16561 err = -ENOMEM;
16562 goto err_out_free_dev;
16563 }
16564
c9cab24e
MC		 16565 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16566 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
16567 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
16568 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
16569 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 16570 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
c9cab24e
MC		 16571 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
16572 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4
MC		 16573 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
16574 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
16575 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
16576 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727) {
c9cab24e
MC		 16577 tg3_flag_set(tp, ENABLE_APE);
16578 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
16579 if (!tp->aperegs) {
16580 dev_err(&pdev->dev,
16581 "Cannot map APE registers, aborting\n");
16582 err = -ENOMEM;
16583 goto err_out_iounmap;
16584 }
16585 }
16586
1da177e4
LT		 16587 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
16588 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 16589
1da177e4 16590 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 16591 dev->watchdog_timeo = TG3_TX_TIMEOUT;
2ffcc981 16592 dev->netdev_ops = &tg3_netdev_ops;
1da177e4 16593 dev->irq = pdev->irq;
1da177e4 16594
3d567e0e 16595 err = tg3_get_invariants(tp, ent);
1da177e4 16596 if (err) {
ab96b241
MC		 16597 dev_err(&pdev->dev,
16598 "Problem fetching invariants of chip, aborting\n");
c9cab24e 16599 goto err_out_apeunmap;
1da177e4
LT		 16600 }
16601
4a29cc2e
MC		 16602 /* The EPB bridge inside 5714, 5715, and 5780 and any
16603 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 16604 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
16605 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
16606 * do DMA address check in tg3_start_xmit().
16607 */
63c3a66f 16608 if (tg3_flag(tp, IS_5788))
284901a9 16609 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
63c3a66f 16610 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
50cf156a 16611 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 16612#ifdef CONFIG_HIGHMEM
6a35528a 16613 dma_mask = DMA_BIT_MASK(64);
72f2afb8 16614#endif
4a29cc2e 16615 } else
6a35528a 16616 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 16617
16618 /* Configure DMA attributes. */
284901a9 16619 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 16620 err = pci_set_dma_mask(pdev, dma_mask);
16621 if (!err) {
0da0606f 16622 features |= NETIF_F_HIGHDMA;
72f2afb8
MC		 16623 err = pci_set_consistent_dma_mask(pdev,
16624 persist_dma_mask);
16625 if (err < 0) {
ab96b241
MC		 16626 dev_err(&pdev->dev, "Unable to obtain 64 bit "
16627 "DMA for consistent allocations\n");
c9cab24e 16628 goto err_out_apeunmap;
72f2afb8
MC		 16629 }
16630 }
16631 }
284901a9
YH		 16632 if (err || dma_mask == DMA_BIT_MASK(32)) {
16633 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 16634 if (err) {
ab96b241
MC		 16635 dev_err(&pdev->dev,
16636 "No usable DMA configuration, aborting\n");
c9cab24e 16637 goto err_out_apeunmap;
72f2afb8
MC		 16638 }
16639 }
16640
fdfec172 16641 tg3_init_bufmgr_config(tp);
1da177e4 16642
0da0606f
MC		 16643 features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
16644
16645 /* 5700 B0 chips do not support checksumming correctly due
16646 * to hardware bugs.
16647 */
16648 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
16649 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
16650
16651 if (tg3_flag(tp, 5755_PLUS))
16652 features |= NETIF_F_IPV6_CSUM;
16653 }
16654
4e3a7aaa
MC		 16655 /* TSO is on by default on chips that support hardware TSO.
16656 * Firmware TSO on older chips gives lower performance, so it
16657 * is off by default, but can be enabled using ethtool.
16658 */
63c3a66f
JP		 16659 if ((tg3_flag(tp, HW_TSO_1) ||
16660 tg3_flag(tp, HW_TSO_2) ||
16661 tg3_flag(tp, HW_TSO_3)) &&
0da0606f
MC		 16662 (features & NETIF_F_IP_CSUM))
16663 features |= NETIF_F_TSO;
63c3a66f 16664 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
0da0606f
MC		 16665 if (features & NETIF_F_IPV6_CSUM)
16666 features |= NETIF_F_TSO6;
63c3a66f 16667 if (tg3_flag(tp, HW_TSO_3) ||
e849cdc3 16668 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 16669 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
16670 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
63c3a66f 16671 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
dc668910 16672 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
0da0606f 16673 features |= NETIF_F_TSO_ECN;
b0026624 16674 }
1da177e4 16675
d542fe27
MC		 16676 dev->features |= features;
16677 dev->vlan_features |= features;
16678
06c03c02
MB		 16679 /*
16680 * Add loopback capability only for a subset of devices that support
16681 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
16682 * loopback for the remaining devices.
16683 */
16684 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
16685 !tg3_flag(tp, CPMU_PRESENT))
16686 /* Add the loopback capability */
0da0606f
MC		 16687 features |= NETIF_F_LOOPBACK;
16688
0da0606f 16689 dev->hw_features |= features;
06c03c02 16690
1da177e4 16691 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
63c3a66f 16692 !tg3_flag(tp, TSO_CAPABLE) &&
1da177e4 16693 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
63c3a66f 16694 tg3_flag_set(tp, MAX_RXPEND_64);
1da177e4
LT		 16695 tp->rx_pending = 63;
16696 }
16697
1da177e4
LT		 16698 err = tg3_get_device_address(tp);
16699 if (err) {
ab96b241
MC		 16700 dev_err(&pdev->dev,
16701 "Could not obtain valid ethernet address, aborting\n");
c9cab24e 16702 goto err_out_apeunmap;
c88864df
MC		 16703 }
16704
1da177e4
LT		 16705 /*
16706 * Reset chip in case UNDI or EFI driver did not shutdown
16707 * DMA self test will enable WDMAC and we'll see (spurious)
16708 * pending DMA on the PCI bus at that point.
16709 */
16710 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
16711 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 16712 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 16713 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 16714 }
16715
16716 err = tg3_test_dma(tp);
16717 if (err) {
ab96b241 16718 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
c88864df 16719 goto err_out_apeunmap;
1da177e4
LT		 16720 }
16721
78f90dcf
MC		 16722 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
16723 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
16724 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6fd45cb8 16725 for (i = 0; i < tp->irq_max; i++) {
78f90dcf
MC		 16726 struct tg3_napi *tnapi = &tp->napi[i];
16727
16728 tnapi->tp = tp;
16729 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
16730
16731 tnapi->int_mbox = intmbx;
93a700a9 16732 if (i <= 4)
78f90dcf
MC		 16733 intmbx += 0x8;
16734 else
16735 intmbx += 0x4;
16736
16737 tnapi->consmbox = rcvmbx;
16738 tnapi->prodmbox = sndmbx;
16739
66cfd1bd 16740 if (i)
78f90dcf 16741 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
66cfd1bd 16742 else
78f90dcf 16743 tnapi->coal_now = HOSTCC_MODE_NOW;
78f90dcf 16744
63c3a66f 16745 if (!tg3_flag(tp, SUPPORT_MSIX))
78f90dcf
MC		 16746 break;
16747
16748 /*
16749 * If we support MSIX, we'll be using RSS. If we're using
16750 * RSS, the first vector only handles link interrupts and the
16751 * remaining vectors handle rx and tx interrupts. Reuse the
16752 * mailbox values for the next iteration. The values we setup
16753 * above are still useful for the single vectored mode.
16754 */
16755 if (!i)
16756 continue;
16757
16758 rcvmbx += 0x8;
16759
16760 if (sndmbx & 0x4)
16761 sndmbx -= 0x4;
16762 else
16763 sndmbx += 0xc;
16764 }
16765
15f9850d
DM		 16766 tg3_init_coal(tp);
16767
c49a1561
MC		 16768 pci_set_drvdata(pdev, dev);
16769
fb4ce8ad 16770 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
c65a17f4
MC		 16771 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
16772 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762)
fb4ce8ad
MC		 16773 tg3_flag_set(tp, PTP_CAPABLE);
16774
cd0d7228
MC		 16775 if (tg3_flag(tp, 5717_PLUS)) {
16776 /* Resume a low-power mode */
16777 tg3_frob_aux_power(tp, false);
16778 }
16779
21f7638e
MC		 16780 tg3_timer_init(tp);
16781
1da177e4
LT		 16782 err = register_netdev(dev);
16783 if (err) {
ab96b241 16784 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 16785 goto err_out_apeunmap;
1da177e4
LT		 16786 }
16787
05dbe005
JP		 16788 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
16789 tp->board_part_number,
16790 tp->pci_chip_rev_id,
16791 tg3_bus_string(tp, str),
16792 dev->dev_addr);
1da177e4 16793
f07e9af3 16794 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7
MC		 16795 struct phy_device *phydev;
16796 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
5129c3a3
MC		 16797 netdev_info(dev,
16798 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
05dbe005 16799 phydev->drv->name, dev_name(&phydev->dev));
f07e9af3
MC		 16800 } else {
16801 char *ethtype;
16802
16803 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
16804 ethtype = "10/100Base-TX";
16805 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
16806 ethtype = "1000Base-SX";
16807 else
16808 ethtype = "10/100/1000Base-T";
16809
5129c3a3 16810 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
47007831
MC		 16811 "(WireSpeed[%d], EEE[%d])\n",
16812 tg3_phy_string(tp), ethtype,
16813 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
16814 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
f07e9af3 16815 }
05dbe005
JP		 16816
16817 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
dc668910 16818 (dev->features & NETIF_F_RXCSUM) != 0,
63c3a66f 16819 tg3_flag(tp, USE_LINKCHG_REG) != 0,
f07e9af3 16820 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
63c3a66f
JP		 16821 tg3_flag(tp, ENABLE_ASF) != 0,
16822 tg3_flag(tp, TSO_CAPABLE) != 0);
05dbe005
JP		 16823 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
16824 tp->dma_rwctrl,
16825 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
16826 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4 16827
b45aa2f6
MC		 16828 pci_save_state(pdev);
16829
1da177e4
LT		 16830 return 0;
16831
0d3031d9
MC		 16832err_out_apeunmap:
16833 if (tp->aperegs) {
16834 iounmap(tp->aperegs);
16835 tp->aperegs = NULL;
16836 }
16837
1da177e4 16838err_out_iounmap:
6892914f
MC		 16839 if (tp->regs) {
16840 iounmap(tp->regs);
22abe310 16841 tp->regs = NULL;
6892914f 16842 }
1da177e4
LT		 16843
16844err_out_free_dev:
16845 free_netdev(dev);
16846
16821285
MC		 16847err_out_power_down:
16848 pci_set_power_state(pdev, PCI_D3hot);
16849
1da177e4
LT		 16850err_out_free_res:
16851 pci_release_regions(pdev);
16852
16853err_out_disable_pdev:
16854 pci_disable_device(pdev);
16855 pci_set_drvdata(pdev, NULL);
16856 return err;
16857}
16858
229b1ad1 16859static void tg3_remove_one(struct pci_dev *pdev)
1da177e4
LT		 16860{
16861 struct net_device *dev = pci_get_drvdata(pdev);
16862
16863 if (dev) {
16864 struct tg3 *tp = netdev_priv(dev);
16865
e3c5530b 16866 release_firmware(tp->fw);
077f849d 16867
db219973 16868 tg3_reset_task_cancel(tp);
158d7abd 16869
e730c823 16870 if (tg3_flag(tp, USE_PHYLIB)) {
b02fd9e3 16871 tg3_phy_fini(tp);
158d7abd 16872 tg3_mdio_fini(tp);
b02fd9e3 16873 }
158d7abd 16874
1da177e4 16875 unregister_netdev(dev);
0d3031d9
MC		 16876 if (tp->aperegs) {
16877 iounmap(tp->aperegs);
16878 tp->aperegs = NULL;
16879 }
6892914f
MC		 16880 if (tp->regs) {
16881 iounmap(tp->regs);
22abe310 16882 tp->regs = NULL;
6892914f 16883 }
1da177e4
LT		 16884 free_netdev(dev);
16885 pci_release_regions(pdev);
16886 pci_disable_device(pdev);
16887 pci_set_drvdata(pdev, NULL);
16888 }
16889}
16890
aa6027ca 16891#ifdef CONFIG_PM_SLEEP
c866b7ea 16892static int tg3_suspend(struct device *device)
1da177e4 16893{
c866b7ea 16894 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 16895 struct net_device *dev = pci_get_drvdata(pdev);
16896 struct tg3 *tp = netdev_priv(dev);
16897 int err;
16898
16899 if (!netif_running(dev))
16900 return 0;
16901
db219973 16902 tg3_reset_task_cancel(tp);
b02fd9e3 16903 tg3_phy_stop(tp);
1da177e4
LT		 16904 tg3_netif_stop(tp);
16905
21f7638e 16906 tg3_timer_stop(tp);
1da177e4 16907
f47c11ee 16908 tg3_full_lock(tp, 1);
1da177e4 16909 tg3_disable_ints(tp);
f47c11ee 16910 tg3_full_unlock(tp);
1da177e4
LT		 16911
16912 netif_device_detach(dev);
16913
f47c11ee 16914 tg3_full_lock(tp, 0);
944d980e 16915 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
63c3a66f 16916 tg3_flag_clear(tp, INIT_COMPLETE);
f47c11ee 16917 tg3_full_unlock(tp);
1da177e4 16918
c866b7ea 16919 err = tg3_power_down_prepare(tp);
1da177e4 16920 if (err) {
b02fd9e3
MC		 16921 int err2;
16922
f47c11ee 16923 tg3_full_lock(tp, 0);
1da177e4 16924
63c3a66f 16925 tg3_flag_set(tp, INIT_COMPLETE);
b02fd9e3
MC		 16926 err2 = tg3_restart_hw(tp, 1);
16927 if (err2)
b9ec6c1b 16928 goto out;
1da177e4 16929
21f7638e 16930 tg3_timer_start(tp);
1da177e4
LT		 16931
16932 netif_device_attach(dev);
16933 tg3_netif_start(tp);
16934
b9ec6c1b 16935out:
f47c11ee 16936 tg3_full_unlock(tp);
b02fd9e3
MC		 16937
16938 if (!err2)
16939 tg3_phy_start(tp);
1da177e4
LT		 16940 }
16941
16942 return err;
16943}
16944
c866b7ea 16945static int tg3_resume(struct device *device)
1da177e4 16946{
c866b7ea 16947 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 16948 struct net_device *dev = pci_get_drvdata(pdev);
16949 struct tg3 *tp = netdev_priv(dev);
16950 int err;
16951
16952 if (!netif_running(dev))
16953 return 0;
16954
1da177e4
LT		 16955 netif_device_attach(dev);
16956
f47c11ee 16957 tg3_full_lock(tp, 0);
1da177e4 16958
63c3a66f 16959 tg3_flag_set(tp, INIT_COMPLETE);
b9ec6c1b
MC		 16960 err = tg3_restart_hw(tp, 1);
16961 if (err)
16962 goto out;
1da177e4 16963
21f7638e 16964 tg3_timer_start(tp);
1da177e4 16965
1da177e4
LT		 16966 tg3_netif_start(tp);
16967
b9ec6c1b 16968out:
f47c11ee 16969 tg3_full_unlock(tp);
1da177e4 16970
b02fd9e3
MC		 16971 if (!err)
16972 tg3_phy_start(tp);
16973
b9ec6c1b 16974 return err;
1da177e4
LT		 16975}
16976
c866b7ea 16977static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
aa6027ca
ED		 16978#define TG3_PM_OPS (&tg3_pm_ops)
16979
16980#else
16981
16982#define TG3_PM_OPS NULL
16983
16984#endif /* CONFIG_PM_SLEEP */
c866b7ea 16985
b45aa2f6
MC		 16986/**
16987 * tg3_io_error_detected - called when PCI error is detected
16988 * @pdev: Pointer to PCI device
16989 * @state: The current pci connection state
16990 *
16991 * This function is called after a PCI bus error affecting
16992 * this device has been detected.
16993 */
16994static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
16995 pci_channel_state_t state)
16996{
16997 struct net_device *netdev = pci_get_drvdata(pdev);
16998 struct tg3 *tp = netdev_priv(netdev);
16999 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
17000
17001 netdev_info(netdev, "PCI I/O error detected\n");
17002
17003 rtnl_lock();
17004
17005 if (!netif_running(netdev))
17006 goto done;
17007
17008 tg3_phy_stop(tp);
17009
17010 tg3_netif_stop(tp);
17011
21f7638e 17012 tg3_timer_stop(tp);
b45aa2f6
MC		 17013
17014 /* Want to make sure that the reset task doesn't run */
db219973 17015 tg3_reset_task_cancel(tp);
b45aa2f6
MC		 17016
17017 netif_device_detach(netdev);
17018
17019 /* Clean up software state, even if MMIO is blocked */
17020 tg3_full_lock(tp, 0);
17021 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
17022 tg3_full_unlock(tp);
17023
17024done:
17025 if (state == pci_channel_io_perm_failure)
17026 err = PCI_ERS_RESULT_DISCONNECT;
17027 else
17028 pci_disable_device(pdev);
17029
17030 rtnl_unlock();
17031
17032 return err;
17033}
17034
17035/**
17036 * tg3_io_slot_reset - called after the pci bus has been reset.
17037 * @pdev: Pointer to PCI device
17038 *
17039 * Restart the card from scratch, as if from a cold-boot.
17040 * At this point, the card has exprienced a hard reset,
17041 * followed by fixups by BIOS, and has its config space
17042 * set up identically to what it was at cold boot.
17043 */
17044static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
17045{
17046 struct net_device *netdev = pci_get_drvdata(pdev);
17047 struct tg3 *tp = netdev_priv(netdev);
17048 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
17049 int err;
17050
17051 rtnl_lock();
17052
17053 if (pci_enable_device(pdev)) {
17054 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
17055 goto done;
17056 }
17057
17058 pci_set_master(pdev);
17059 pci_restore_state(pdev);
17060 pci_save_state(pdev);
17061
17062 if (!netif_running(netdev)) {
17063 rc = PCI_ERS_RESULT_RECOVERED;
17064 goto done;
17065 }
17066
17067 err = tg3_power_up(tp);
bed9829f 17068 if (err)
b45aa2f6 17069 goto done;
b45aa2f6
MC		 17070
17071 rc = PCI_ERS_RESULT_RECOVERED;
17072
17073done:
17074 rtnl_unlock();
17075
17076 return rc;
17077}
17078
17079/**
17080 * tg3_io_resume - called when traffic can start flowing again.
17081 * @pdev: Pointer to PCI device
17082 *
17083 * This callback is called when the error recovery driver tells
17084 * us that its OK to resume normal operation.
17085 */
17086static void tg3_io_resume(struct pci_dev *pdev)
17087{
17088 struct net_device *netdev = pci_get_drvdata(pdev);
17089 struct tg3 *tp = netdev_priv(netdev);
17090 int err;
17091
17092 rtnl_lock();
17093
17094 if (!netif_running(netdev))
17095 goto done;
17096
17097 tg3_full_lock(tp, 0);
63c3a66f 17098 tg3_flag_set(tp, INIT_COMPLETE);
b45aa2f6 17099 err = tg3_restart_hw(tp, 1);
b45aa2f6 17100 if (err) {
35763066 17101 tg3_full_unlock(tp);
b45aa2f6
MC		 17102 netdev_err(netdev, "Cannot restart hardware after reset.\n");
17103 goto done;
17104 }
17105
17106 netif_device_attach(netdev);
17107
21f7638e 17108 tg3_timer_start(tp);
b45aa2f6
MC		 17109
17110 tg3_netif_start(tp);
17111
35763066
NNS		 17112 tg3_full_unlock(tp);
17113
b45aa2f6
MC		 17114 tg3_phy_start(tp);
17115
17116done:
17117 rtnl_unlock();
17118}
17119
3646f0e5 17120static const struct pci_error_handlers tg3_err_handler = {
b45aa2f6
MC		 17121 .error_detected = tg3_io_error_detected,
17122 .slot_reset = tg3_io_slot_reset,
17123 .resume = tg3_io_resume
17124};
17125
1da177e4
LT		 17126static struct pci_driver tg3_driver = {
17127 .name = DRV_MODULE_NAME,
17128 .id_table = tg3_pci_tbl,
17129 .probe = tg3_init_one,
229b1ad1 17130 .remove = tg3_remove_one,
b45aa2f6 17131 .err_handler = &tg3_err_handler,
aa6027ca 17132 .driver.pm = TG3_PM_OPS,
1da177e4
LT		 17133};
17134
17135static int __init tg3_init(void)
17136{
29917620 17137 return pci_register_driver(&tg3_driver);
1da177e4
LT		 17138}
17139
17140static void __exit tg3_cleanup(void)
17141{
17142 pci_unregister_driver(&tg3_driver);
17143}
17144
17145module_init(tg3_init);
17146module_exit(tg3_cleanup);
Linux kernel - Deliverables
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