Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
b86fb2cf | 7 | * Copyright (C) 2005-2011 Broadcom Corporation. |
1da177e4 LT |
8 | * |
9 | * Firmware is: | |
49cabf49 MC |
10 | * Derived from proprietary unpublished source code, |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | |
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
6867c843 | 21 | #include <linux/stringify.h> |
1da177e4 LT |
22 | #include <linux/kernel.h> |
23 | #include <linux/types.h> | |
24 | #include <linux/compiler.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
14c85021 | 27 | #include <linux/in.h> |
1da177e4 | 28 | #include <linux/init.h> |
a6b7a407 | 29 | #include <linux/interrupt.h> |
1da177e4 LT |
30 | #include <linux/ioport.h> |
31 | #include <linux/pci.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/ethtool.h> | |
3110f5f5 | 36 | #include <linux/mdio.h> |
1da177e4 | 37 | #include <linux/mii.h> |
158d7abd | 38 | #include <linux/phy.h> |
a9daf367 | 39 | #include <linux/brcmphy.h> |
1da177e4 LT |
40 | #include <linux/if_vlan.h> |
41 | #include <linux/ip.h> | |
42 | #include <linux/tcp.h> | |
43 | #include <linux/workqueue.h> | |
61487480 | 44 | #include <linux/prefetch.h> |
f9a5f7d3 | 45 | #include <linux/dma-mapping.h> |
077f849d | 46 | #include <linux/firmware.h> |
1da177e4 LT |
47 | |
48 | #include <net/checksum.h> | |
c9bdd4b5 | 49 | #include <net/ip.h> |
1da177e4 LT |
50 | |
51 | #include <asm/system.h> | |
27fd9de8 | 52 | #include <linux/io.h> |
1da177e4 | 53 | #include <asm/byteorder.h> |
27fd9de8 | 54 | #include <linux/uaccess.h> |
1da177e4 | 55 | |
49b6e95f | 56 | #ifdef CONFIG_SPARC |
1da177e4 | 57 | #include <asm/idprom.h> |
49b6e95f | 58 | #include <asm/prom.h> |
1da177e4 LT |
59 | #endif |
60 | ||
63532394 MC |
61 | #define BAR_0 0 |
62 | #define BAR_2 2 | |
63 | ||
1da177e4 LT |
64 | #include "tg3.h" |
65 | ||
63c3a66f JP |
66 | /* Functions & macros to verify TG3_FLAGS types */ |
67 | ||
68 | static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits) | |
69 | { | |
70 | return test_bit(flag, bits); | |
71 | } | |
72 | ||
73 | static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits) | |
74 | { | |
75 | set_bit(flag, bits); | |
76 | } | |
77 | ||
78 | static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits) | |
79 | { | |
80 | clear_bit(flag, bits); | |
81 | } | |
82 | ||
83 | #define tg3_flag(tp, flag) \ | |
84 | _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags) | |
85 | #define tg3_flag_set(tp, flag) \ | |
86 | _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags) | |
87 | #define tg3_flag_clear(tp, flag) \ | |
88 | _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags) | |
89 | ||
1da177e4 | 90 | #define DRV_MODULE_NAME "tg3" |
6867c843 | 91 | #define TG3_MAJ_NUM 3 |
43a5f002 | 92 | #define TG3_MIN_NUM 119 |
6867c843 MC |
93 | #define DRV_MODULE_VERSION \ |
94 | __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) | |
43a5f002 | 95 | #define DRV_MODULE_RELDATE "May 18, 2011" |
1da177e4 | 96 | |
1da177e4 LT |
97 | #define TG3_DEF_RX_MODE 0 |
98 | #define TG3_DEF_TX_MODE 0 | |
99 | #define TG3_DEF_MSG_ENABLE \ | |
100 | (NETIF_MSG_DRV | \ | |
101 | NETIF_MSG_PROBE | \ | |
102 | NETIF_MSG_LINK | \ | |
103 | NETIF_MSG_TIMER | \ | |
104 | NETIF_MSG_IFDOWN | \ | |
105 | NETIF_MSG_IFUP | \ | |
106 | NETIF_MSG_RX_ERR | \ | |
107 | NETIF_MSG_TX_ERR) | |
108 | ||
520b2756 MC |
109 | #define TG3_GRC_LCLCTL_PWRSW_DELAY 100 |
110 | ||
1da177e4 LT |
111 | /* length of time before we decide the hardware is borked, |
112 | * and dev->tx_timeout() should be called to fix the problem | |
113 | */ | |
63c3a66f | 114 | |
1da177e4 LT |
115 | #define TG3_TX_TIMEOUT (5 * HZ) |
116 | ||
117 | /* hardware minimum and maximum for a single frame's data payload */ | |
118 | #define TG3_MIN_MTU 60 | |
119 | #define TG3_MAX_MTU(tp) \ | |
63c3a66f | 120 | (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500) |
1da177e4 LT |
121 | |
122 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
123 | * You can't change the ring sizes, but you can change where you place | |
124 | * them in the NIC onboard memory. | |
125 | */ | |
7cb32cf2 | 126 | #define TG3_RX_STD_RING_SIZE(tp) \ |
63c3a66f | 127 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
de9f5230 | 128 | TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700) |
1da177e4 | 129 | #define TG3_DEF_RX_RING_PENDING 200 |
7cb32cf2 | 130 | #define TG3_RX_JMB_RING_SIZE(tp) \ |
63c3a66f | 131 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
de9f5230 | 132 | TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700) |
1da177e4 | 133 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 |
c6cdf436 | 134 | #define TG3_RSS_INDIR_TBL_SIZE 128 |
1da177e4 LT |
135 | |
136 | /* Do not place this n-ring entries value into the tp struct itself, | |
137 | * we really want to expose these constants to GCC so that modulo et | |
138 | * al. operations are done with shifts and masks instead of with | |
139 | * hw multiply/modulo instructions. Another solution would be to | |
140 | * replace things like '% foo' with '& (foo - 1)'. | |
141 | */ | |
1da177e4 LT |
142 | |
143 | #define TG3_TX_RING_SIZE 512 | |
144 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
145 | ||
2c49a44d MC |
146 | #define TG3_RX_STD_RING_BYTES(tp) \ |
147 | (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp)) | |
148 | #define TG3_RX_JMB_RING_BYTES(tp) \ | |
149 | (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp)) | |
150 | #define TG3_RX_RCB_RING_BYTES(tp) \ | |
7cb32cf2 | 151 | (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1)) |
1da177e4 LT |
152 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ |
153 | TG3_TX_RING_SIZE) | |
1da177e4 LT |
154 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
155 | ||
287be12e MC |
156 | #define TG3_DMA_BYTE_ENAB 64 |
157 | ||
158 | #define TG3_RX_STD_DMA_SZ 1536 | |
159 | #define TG3_RX_JMB_DMA_SZ 9046 | |
160 | ||
161 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
162 | ||
163 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
164 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
1da177e4 | 165 | |
2c49a44d MC |
166 | #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ |
167 | (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp)) | |
2b2cdb65 | 168 | |
2c49a44d MC |
169 | #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ |
170 | (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp)) | |
2b2cdb65 | 171 | |
d2757fc4 MC |
172 | /* Due to a hardware bug, the 5701 can only DMA to memory addresses |
173 | * that are at least dword aligned when used in PCIX mode. The driver | |
174 | * works around this bug by double copying the packet. This workaround | |
175 | * is built into the normal double copy length check for efficiency. | |
176 | * | |
177 | * However, the double copy is only necessary on those architectures | |
178 | * where unaligned memory accesses are inefficient. For those architectures | |
179 | * where unaligned memory accesses incur little penalty, we can reintegrate | |
180 | * the 5701 in the normal rx path. Doing so saves a device structure | |
181 | * dereference by hardcoding the double copy threshold in place. | |
182 | */ | |
183 | #define TG3_RX_COPY_THRESHOLD 256 | |
184 | #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) | |
185 | #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD | |
186 | #else | |
187 | #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) | |
188 | #endif | |
189 | ||
1da177e4 | 190 | /* minimum number of free TX descriptors required to wake up TX process */ |
f3f3f27e | 191 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
e31aa987 | 192 | #define TG3_TX_BD_DMA_MAX 4096 |
1da177e4 | 193 | |
ad829268 MC |
194 | #define TG3_RAW_IP_ALIGN 2 |
195 | ||
c6cdf436 MC |
196 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 |
197 | ||
077f849d JSR |
198 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
199 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
200 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
201 | ||
1da177e4 | 202 | static char version[] __devinitdata = |
05dbe005 | 203 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")"; |
1da177e4 LT |
204 | |
205 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
206 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
207 | MODULE_LICENSE("GPL"); | |
208 | MODULE_VERSION(DRV_MODULE_VERSION); | |
077f849d JSR |
209 | MODULE_FIRMWARE(FIRMWARE_TG3); |
210 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
211 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
212 | ||
1da177e4 LT |
213 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ |
214 | module_param(tg3_debug, int, 0); | |
215 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
216 | ||
a3aa1884 | 217 | static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = { |
13185217 HK |
218 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, |
219 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
220 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
221 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
222 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
223 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
224 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
225 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
226 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
227 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
228 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
229 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
230 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
231 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
232 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
235 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, | |
237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, | |
238 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, | |
239 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, | |
13185217 | 240 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, |
126a3368 | 241 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, |
13185217 | 242 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, |
13185217 HK |
243 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, |
244 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, | |
245 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, | |
246 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
247 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
248 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
249 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, | |
250 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, | |
251 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
252 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
253 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
126a3368 | 254 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, |
13185217 HK |
255 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, |
256 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
257 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, | |
676917d4 | 258 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, |
13185217 HK |
259 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, |
260 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
261 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
262 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
263 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
264 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
265 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
b5d3772c MC |
266 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, |
267 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
d30cdd28 MC |
268 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, |
269 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
6c7af27c | 270 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, |
9936bcf6 MC |
271 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, |
272 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
c88e668b MC |
273 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, |
274 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
2befdcea MC |
275 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, |
276 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
321d32a0 MC |
277 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, |
278 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
279 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, | |
5e7ccf20 | 280 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, |
5001e2f6 MC |
281 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)}, |
282 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)}, | |
b0f75221 MC |
283 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)}, |
284 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)}, | |
285 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)}, | |
286 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)}, | |
287 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)}, | |
288 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)}, | |
302b500b | 289 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)}, |
ba1f3c76 | 290 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)}, |
13185217 HK |
291 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, |
292 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
293 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
294 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
295 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
296 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
297 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
1dcb14d9 | 298 | {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */ |
13185217 | 299 | {} |
1da177e4 LT |
300 | }; |
301 | ||
302 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
303 | ||
50da859d | 304 | static const struct { |
1da177e4 | 305 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 306 | } ethtool_stats_keys[] = { |
1da177e4 LT |
307 | { "rx_octets" }, |
308 | { "rx_fragments" }, | |
309 | { "rx_ucast_packets" }, | |
310 | { "rx_mcast_packets" }, | |
311 | { "rx_bcast_packets" }, | |
312 | { "rx_fcs_errors" }, | |
313 | { "rx_align_errors" }, | |
314 | { "rx_xon_pause_rcvd" }, | |
315 | { "rx_xoff_pause_rcvd" }, | |
316 | { "rx_mac_ctrl_rcvd" }, | |
317 | { "rx_xoff_entered" }, | |
318 | { "rx_frame_too_long_errors" }, | |
319 | { "rx_jabbers" }, | |
320 | { "rx_undersize_packets" }, | |
321 | { "rx_in_length_errors" }, | |
322 | { "rx_out_length_errors" }, | |
323 | { "rx_64_or_less_octet_packets" }, | |
324 | { "rx_65_to_127_octet_packets" }, | |
325 | { "rx_128_to_255_octet_packets" }, | |
326 | { "rx_256_to_511_octet_packets" }, | |
327 | { "rx_512_to_1023_octet_packets" }, | |
328 | { "rx_1024_to_1522_octet_packets" }, | |
329 | { "rx_1523_to_2047_octet_packets" }, | |
330 | { "rx_2048_to_4095_octet_packets" }, | |
331 | { "rx_4096_to_8191_octet_packets" }, | |
332 | { "rx_8192_to_9022_octet_packets" }, | |
333 | ||
334 | { "tx_octets" }, | |
335 | { "tx_collisions" }, | |
336 | ||
337 | { "tx_xon_sent" }, | |
338 | { "tx_xoff_sent" }, | |
339 | { "tx_flow_control" }, | |
340 | { "tx_mac_errors" }, | |
341 | { "tx_single_collisions" }, | |
342 | { "tx_mult_collisions" }, | |
343 | { "tx_deferred" }, | |
344 | { "tx_excessive_collisions" }, | |
345 | { "tx_late_collisions" }, | |
346 | { "tx_collide_2times" }, | |
347 | { "tx_collide_3times" }, | |
348 | { "tx_collide_4times" }, | |
349 | { "tx_collide_5times" }, | |
350 | { "tx_collide_6times" }, | |
351 | { "tx_collide_7times" }, | |
352 | { "tx_collide_8times" }, | |
353 | { "tx_collide_9times" }, | |
354 | { "tx_collide_10times" }, | |
355 | { "tx_collide_11times" }, | |
356 | { "tx_collide_12times" }, | |
357 | { "tx_collide_13times" }, | |
358 | { "tx_collide_14times" }, | |
359 | { "tx_collide_15times" }, | |
360 | { "tx_ucast_packets" }, | |
361 | { "tx_mcast_packets" }, | |
362 | { "tx_bcast_packets" }, | |
363 | { "tx_carrier_sense_errors" }, | |
364 | { "tx_discards" }, | |
365 | { "tx_errors" }, | |
366 | ||
367 | { "dma_writeq_full" }, | |
368 | { "dma_write_prioq_full" }, | |
369 | { "rxbds_empty" }, | |
370 | { "rx_discards" }, | |
371 | { "rx_errors" }, | |
372 | { "rx_threshold_hit" }, | |
373 | ||
374 | { "dma_readq_full" }, | |
375 | { "dma_read_prioq_full" }, | |
376 | { "tx_comp_queue_full" }, | |
377 | ||
378 | { "ring_set_send_prod_index" }, | |
379 | { "ring_status_update" }, | |
380 | { "nic_irqs" }, | |
381 | { "nic_avoided_irqs" }, | |
4452d099 MC |
382 | { "nic_tx_threshold_hit" }, |
383 | ||
384 | { "mbuf_lwm_thresh_hit" }, | |
1da177e4 LT |
385 | }; |
386 | ||
48fa55a0 MC |
387 | #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys) |
388 | ||
389 | ||
50da859d | 390 | static const struct { |
4cafd3f5 | 391 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 392 | } ethtool_test_keys[] = { |
4cafd3f5 MC |
393 | { "nvram test (online) " }, |
394 | { "link test (online) " }, | |
395 | { "register test (offline)" }, | |
396 | { "memory test (offline)" }, | |
397 | { "loopback test (offline)" }, | |
398 | { "interrupt test (offline)" }, | |
399 | }; | |
400 | ||
48fa55a0 MC |
401 | #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys) |
402 | ||
403 | ||
b401e9e2 MC |
404 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) |
405 | { | |
406 | writel(val, tp->regs + off); | |
407 | } | |
408 | ||
409 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
410 | { | |
de6f31eb | 411 | return readl(tp->regs + off); |
b401e9e2 MC |
412 | } |
413 | ||
0d3031d9 MC |
414 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) |
415 | { | |
416 | writel(val, tp->aperegs + off); | |
417 | } | |
418 | ||
419 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
420 | { | |
de6f31eb | 421 | return readl(tp->aperegs + off); |
0d3031d9 MC |
422 | } |
423 | ||
1da177e4 LT |
424 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
425 | { | |
6892914f MC |
426 | unsigned long flags; |
427 | ||
428 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
1ee582d8 MC |
429 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
430 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
6892914f | 431 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1ee582d8 MC |
432 | } |
433 | ||
434 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
435 | { | |
436 | writel(val, tp->regs + off); | |
437 | readl(tp->regs + off); | |
1da177e4 LT |
438 | } |
439 | ||
6892914f | 440 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) |
1da177e4 | 441 | { |
6892914f MC |
442 | unsigned long flags; |
443 | u32 val; | |
444 | ||
445 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
446 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
447 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
448 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
449 | return val; | |
450 | } | |
451 | ||
452 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
453 | { | |
454 | unsigned long flags; | |
455 | ||
456 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
457 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
458 | TG3_64BIT_REG_LOW, val); | |
459 | return; | |
460 | } | |
66711e66 | 461 | if (off == TG3_RX_STD_PROD_IDX_REG) { |
6892914f MC |
462 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + |
463 | TG3_64BIT_REG_LOW, val); | |
464 | return; | |
1da177e4 | 465 | } |
6892914f MC |
466 | |
467 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
468 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
469 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
470 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
471 | ||
472 | /* In indirect mode when disabling interrupts, we also need | |
473 | * to clear the interrupt bit in the GRC local ctrl register. | |
474 | */ | |
475 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
476 | (val == 0x1)) { | |
477 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
478 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
479 | } | |
480 | } | |
481 | ||
482 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
483 | { | |
484 | unsigned long flags; | |
485 | u32 val; | |
486 | ||
487 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
488 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
489 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
490 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
491 | return val; | |
492 | } | |
493 | ||
b401e9e2 MC |
494 | /* usec_wait specifies the wait time in usec when writing to certain registers |
495 | * where it is unsafe to read back the register without some delay. | |
496 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
497 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
498 | */ | |
499 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
6892914f | 500 | { |
63c3a66f | 501 | if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) |
b401e9e2 MC |
502 | /* Non-posted methods */ |
503 | tp->write32(tp, off, val); | |
504 | else { | |
505 | /* Posted method */ | |
506 | tg3_write32(tp, off, val); | |
507 | if (usec_wait) | |
508 | udelay(usec_wait); | |
509 | tp->read32(tp, off); | |
510 | } | |
511 | /* Wait again after the read for the posted method to guarantee that | |
512 | * the wait time is met. | |
513 | */ | |
514 | if (usec_wait) | |
515 | udelay(usec_wait); | |
1da177e4 LT |
516 | } |
517 | ||
09ee929c MC |
518 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
519 | { | |
520 | tp->write32_mbox(tp, off, val); | |
63c3a66f | 521 | if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)) |
6892914f | 522 | tp->read32_mbox(tp, off); |
09ee929c MC |
523 | } |
524 | ||
20094930 | 525 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
1da177e4 LT |
526 | { |
527 | void __iomem *mbox = tp->regs + off; | |
528 | writel(val, mbox); | |
63c3a66f | 529 | if (tg3_flag(tp, TXD_MBOX_HWBUG)) |
1da177e4 | 530 | writel(val, mbox); |
63c3a66f | 531 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
1da177e4 LT |
532 | readl(mbox); |
533 | } | |
534 | ||
b5d3772c MC |
535 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) |
536 | { | |
de6f31eb | 537 | return readl(tp->regs + off + GRCMBOX_BASE); |
b5d3772c MC |
538 | } |
539 | ||
540 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
541 | { | |
542 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
543 | } | |
544 | ||
c6cdf436 | 545 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
09ee929c | 546 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
c6cdf436 MC |
547 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
548 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
549 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | |
20094930 | 550 | |
c6cdf436 MC |
551 | #define tw32(reg, val) tp->write32(tp, reg, val) |
552 | #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) | |
553 | #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) | |
554 | #define tr32(reg) tp->read32(tp, reg) | |
1da177e4 LT |
555 | |
556 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
557 | { | |
6892914f MC |
558 | unsigned long flags; |
559 | ||
6ff6f81d | 560 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
b5d3772c MC |
561 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) |
562 | return; | |
563 | ||
6892914f | 564 | spin_lock_irqsave(&tp->indirect_lock, flags); |
63c3a66f | 565 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
bbadf503 MC |
566 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
567 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 568 | |
bbadf503 MC |
569 | /* Always leave this as zero. */ |
570 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
571 | } else { | |
572 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
573 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
28fbef78 | 574 | |
bbadf503 MC |
575 | /* Always leave this as zero. */ |
576 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
577 | } | |
578 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
758a6139 DM |
579 | } |
580 | ||
1da177e4 LT |
581 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) |
582 | { | |
6892914f MC |
583 | unsigned long flags; |
584 | ||
6ff6f81d | 585 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
b5d3772c MC |
586 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { |
587 | *val = 0; | |
588 | return; | |
589 | } | |
590 | ||
6892914f | 591 | spin_lock_irqsave(&tp->indirect_lock, flags); |
63c3a66f | 592 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
bbadf503 MC |
593 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
594 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 595 | |
bbadf503 MC |
596 | /* Always leave this as zero. */ |
597 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
598 | } else { | |
599 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
600 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
601 | ||
602 | /* Always leave this as zero. */ | |
603 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
604 | } | |
6892914f | 605 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1da177e4 LT |
606 | } |
607 | ||
0d3031d9 MC |
608 | static void tg3_ape_lock_init(struct tg3 *tp) |
609 | { | |
610 | int i; | |
6f5c8f83 | 611 | u32 regbase, bit; |
f92d9dc1 MC |
612 | |
613 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
614 | regbase = TG3_APE_LOCK_GRANT; | |
615 | else | |
616 | regbase = TG3_APE_PER_LOCK_GRANT; | |
0d3031d9 MC |
617 | |
618 | /* Make sure the driver hasn't any stale locks. */ | |
6f5c8f83 MC |
619 | for (i = 0; i < 8; i++) { |
620 | if (i == TG3_APE_LOCK_GPIO) | |
621 | continue; | |
f92d9dc1 | 622 | tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER); |
6f5c8f83 MC |
623 | } |
624 | ||
625 | /* Clear the correct bit of the GPIO lock too. */ | |
626 | if (!tp->pci_fn) | |
627 | bit = APE_LOCK_GRANT_DRIVER; | |
628 | else | |
629 | bit = 1 << tp->pci_fn; | |
630 | ||
631 | tg3_ape_write32(tp, regbase + 4 * TG3_APE_LOCK_GPIO, bit); | |
0d3031d9 MC |
632 | } |
633 | ||
634 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
635 | { | |
636 | int i, off; | |
637 | int ret = 0; | |
6f5c8f83 | 638 | u32 status, req, gnt, bit; |
0d3031d9 | 639 | |
63c3a66f | 640 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
641 | return 0; |
642 | ||
643 | switch (locknum) { | |
6f5c8f83 MC |
644 | case TG3_APE_LOCK_GPIO: |
645 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
646 | return 0; | |
33f401ae MC |
647 | case TG3_APE_LOCK_GRC: |
648 | case TG3_APE_LOCK_MEM: | |
649 | break; | |
650 | default: | |
651 | return -EINVAL; | |
0d3031d9 MC |
652 | } |
653 | ||
f92d9dc1 MC |
654 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { |
655 | req = TG3_APE_LOCK_REQ; | |
656 | gnt = TG3_APE_LOCK_GRANT; | |
657 | } else { | |
658 | req = TG3_APE_PER_LOCK_REQ; | |
659 | gnt = TG3_APE_PER_LOCK_GRANT; | |
660 | } | |
661 | ||
0d3031d9 MC |
662 | off = 4 * locknum; |
663 | ||
6f5c8f83 MC |
664 | if (locknum != TG3_APE_LOCK_GPIO || !tp->pci_fn) |
665 | bit = APE_LOCK_REQ_DRIVER; | |
666 | else | |
667 | bit = 1 << tp->pci_fn; | |
668 | ||
669 | tg3_ape_write32(tp, req + off, bit); | |
0d3031d9 MC |
670 | |
671 | /* Wait for up to 1 millisecond to acquire lock. */ | |
672 | for (i = 0; i < 100; i++) { | |
f92d9dc1 | 673 | status = tg3_ape_read32(tp, gnt + off); |
6f5c8f83 | 674 | if (status == bit) |
0d3031d9 MC |
675 | break; |
676 | udelay(10); | |
677 | } | |
678 | ||
6f5c8f83 | 679 | if (status != bit) { |
0d3031d9 | 680 | /* Revoke the lock request. */ |
6f5c8f83 | 681 | tg3_ape_write32(tp, gnt + off, bit); |
0d3031d9 MC |
682 | ret = -EBUSY; |
683 | } | |
684 | ||
685 | return ret; | |
686 | } | |
687 | ||
688 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
689 | { | |
6f5c8f83 | 690 | u32 gnt, bit; |
0d3031d9 | 691 | |
63c3a66f | 692 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
693 | return; |
694 | ||
695 | switch (locknum) { | |
6f5c8f83 MC |
696 | case TG3_APE_LOCK_GPIO: |
697 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
698 | return; | |
33f401ae MC |
699 | case TG3_APE_LOCK_GRC: |
700 | case TG3_APE_LOCK_MEM: | |
701 | break; | |
702 | default: | |
703 | return; | |
0d3031d9 MC |
704 | } |
705 | ||
f92d9dc1 MC |
706 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
707 | gnt = TG3_APE_LOCK_GRANT; | |
708 | else | |
709 | gnt = TG3_APE_PER_LOCK_GRANT; | |
710 | ||
6f5c8f83 MC |
711 | if (locknum != TG3_APE_LOCK_GPIO || !tp->pci_fn) |
712 | bit = APE_LOCK_GRANT_DRIVER; | |
713 | else | |
714 | bit = 1 << tp->pci_fn; | |
715 | ||
716 | tg3_ape_write32(tp, gnt + 4 * locknum, bit); | |
0d3031d9 MC |
717 | } |
718 | ||
1da177e4 LT |
719 | static void tg3_disable_ints(struct tg3 *tp) |
720 | { | |
89aeb3bc MC |
721 | int i; |
722 | ||
1da177e4 LT |
723 | tw32(TG3PCI_MISC_HOST_CTRL, |
724 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc MC |
725 | for (i = 0; i < tp->irq_max; i++) |
726 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); | |
1da177e4 LT |
727 | } |
728 | ||
1da177e4 LT |
729 | static void tg3_enable_ints(struct tg3 *tp) |
730 | { | |
89aeb3bc | 731 | int i; |
89aeb3bc | 732 | |
bbe832c0 MC |
733 | tp->irq_sync = 0; |
734 | wmb(); | |
735 | ||
1da177e4 LT |
736 | tw32(TG3PCI_MISC_HOST_CTRL, |
737 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc | 738 | |
f89f38b8 | 739 | tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; |
89aeb3bc MC |
740 | for (i = 0; i < tp->irq_cnt; i++) { |
741 | struct tg3_napi *tnapi = &tp->napi[i]; | |
c6cdf436 | 742 | |
898a56f8 | 743 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
63c3a66f | 744 | if (tg3_flag(tp, 1SHOT_MSI)) |
89aeb3bc | 745 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
f19af9c2 | 746 | |
f89f38b8 | 747 | tp->coal_now |= tnapi->coal_now; |
89aeb3bc | 748 | } |
f19af9c2 MC |
749 | |
750 | /* Force an initial interrupt */ | |
63c3a66f | 751 | if (!tg3_flag(tp, TAGGED_STATUS) && |
f19af9c2 MC |
752 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) |
753 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
754 | else | |
f89f38b8 MC |
755 | tw32(HOSTCC_MODE, tp->coal_now); |
756 | ||
757 | tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); | |
1da177e4 LT |
758 | } |
759 | ||
17375d25 | 760 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) |
04237ddd | 761 | { |
17375d25 | 762 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 763 | struct tg3_hw_status *sblk = tnapi->hw_status; |
04237ddd MC |
764 | unsigned int work_exists = 0; |
765 | ||
766 | /* check for phy events */ | |
63c3a66f | 767 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
04237ddd MC |
768 | if (sblk->status & SD_STATUS_LINK_CHG) |
769 | work_exists = 1; | |
770 | } | |
771 | /* check for RX/TX work to do */ | |
f3f3f27e | 772 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons || |
8d9d7cfc | 773 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
04237ddd MC |
774 | work_exists = 1; |
775 | ||
776 | return work_exists; | |
777 | } | |
778 | ||
17375d25 | 779 | /* tg3_int_reenable |
04237ddd MC |
780 | * similar to tg3_enable_ints, but it accurately determines whether there |
781 | * is new work pending and can return without flushing the PIO write | |
6aa20a22 | 782 | * which reenables interrupts |
1da177e4 | 783 | */ |
17375d25 | 784 | static void tg3_int_reenable(struct tg3_napi *tnapi) |
1da177e4 | 785 | { |
17375d25 MC |
786 | struct tg3 *tp = tnapi->tp; |
787 | ||
898a56f8 | 788 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
1da177e4 LT |
789 | mmiowb(); |
790 | ||
fac9b83e DM |
791 | /* When doing tagged status, this work check is unnecessary. |
792 | * The last_tag we write above tells the chip which piece of | |
793 | * work we've completed. | |
794 | */ | |
63c3a66f | 795 | if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) |
04237ddd | 796 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
fd2ce37f | 797 | HOSTCC_MODE_ENABLE | tnapi->coal_now); |
1da177e4 LT |
798 | } |
799 | ||
1da177e4 LT |
800 | static void tg3_switch_clocks(struct tg3 *tp) |
801 | { | |
f6eb9b1f | 802 | u32 clock_ctrl; |
1da177e4 LT |
803 | u32 orig_clock_ctrl; |
804 | ||
63c3a66f | 805 | if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) |
4cf78e4f MC |
806 | return; |
807 | ||
f6eb9b1f MC |
808 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); |
809 | ||
1da177e4 LT |
810 | orig_clock_ctrl = clock_ctrl; |
811 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
812 | CLOCK_CTRL_CLKRUN_OENABLE | | |
813 | 0x1f); | |
814 | tp->pci_clock_ctrl = clock_ctrl; | |
815 | ||
63c3a66f | 816 | if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 | 817 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { |
b401e9e2 MC |
818 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
819 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
1da177e4 LT |
820 | } |
821 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
b401e9e2 MC |
822 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
823 | clock_ctrl | | |
824 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
825 | 40); | |
826 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
827 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
828 | 40); | |
1da177e4 | 829 | } |
b401e9e2 | 830 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); |
1da177e4 LT |
831 | } |
832 | ||
833 | #define PHY_BUSY_LOOPS 5000 | |
834 | ||
835 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
836 | { | |
837 | u32 frame_val; | |
838 | unsigned int loops; | |
839 | int ret; | |
840 | ||
841 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
842 | tw32_f(MAC_MI_MODE, | |
843 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
844 | udelay(80); | |
845 | } | |
846 | ||
847 | *val = 0x0; | |
848 | ||
882e9793 | 849 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
850 | MI_COM_PHY_ADDR_MASK); |
851 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
852 | MI_COM_REG_ADDR_MASK); | |
853 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
6aa20a22 | 854 | |
1da177e4 LT |
855 | tw32_f(MAC_MI_COM, frame_val); |
856 | ||
857 | loops = PHY_BUSY_LOOPS; | |
858 | while (loops != 0) { | |
859 | udelay(10); | |
860 | frame_val = tr32(MAC_MI_COM); | |
861 | ||
862 | if ((frame_val & MI_COM_BUSY) == 0) { | |
863 | udelay(5); | |
864 | frame_val = tr32(MAC_MI_COM); | |
865 | break; | |
866 | } | |
867 | loops -= 1; | |
868 | } | |
869 | ||
870 | ret = -EBUSY; | |
871 | if (loops != 0) { | |
872 | *val = frame_val & MI_COM_DATA_MASK; | |
873 | ret = 0; | |
874 | } | |
875 | ||
876 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
877 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
878 | udelay(80); | |
879 | } | |
880 | ||
881 | return ret; | |
882 | } | |
883 | ||
884 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
885 | { | |
886 | u32 frame_val; | |
887 | unsigned int loops; | |
888 | int ret; | |
889 | ||
f07e9af3 | 890 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && |
221c5637 | 891 | (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL)) |
b5d3772c MC |
892 | return 0; |
893 | ||
1da177e4 LT |
894 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
895 | tw32_f(MAC_MI_MODE, | |
896 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
897 | udelay(80); | |
898 | } | |
899 | ||
882e9793 | 900 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
901 | MI_COM_PHY_ADDR_MASK); |
902 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
903 | MI_COM_REG_ADDR_MASK); | |
904 | frame_val |= (val & MI_COM_DATA_MASK); | |
905 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
6aa20a22 | 906 | |
1da177e4 LT |
907 | tw32_f(MAC_MI_COM, frame_val); |
908 | ||
909 | loops = PHY_BUSY_LOOPS; | |
910 | while (loops != 0) { | |
911 | udelay(10); | |
912 | frame_val = tr32(MAC_MI_COM); | |
913 | if ((frame_val & MI_COM_BUSY) == 0) { | |
914 | udelay(5); | |
915 | frame_val = tr32(MAC_MI_COM); | |
916 | break; | |
917 | } | |
918 | loops -= 1; | |
919 | } | |
920 | ||
921 | ret = -EBUSY; | |
922 | if (loops != 0) | |
923 | ret = 0; | |
924 | ||
925 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
926 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
927 | udelay(80); | |
928 | } | |
929 | ||
930 | return ret; | |
931 | } | |
932 | ||
b0988c15 MC |
933 | static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) |
934 | { | |
935 | int err; | |
936 | ||
937 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
938 | if (err) | |
939 | goto done; | |
940 | ||
941 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
942 | if (err) | |
943 | goto done; | |
944 | ||
945 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
946 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
947 | if (err) | |
948 | goto done; | |
949 | ||
950 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); | |
951 | ||
952 | done: | |
953 | return err; | |
954 | } | |
955 | ||
956 | static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) | |
957 | { | |
958 | int err; | |
959 | ||
960 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
961 | if (err) | |
962 | goto done; | |
963 | ||
964 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
965 | if (err) | |
966 | goto done; | |
967 | ||
968 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
969 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
970 | if (err) | |
971 | goto done; | |
972 | ||
973 | err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); | |
974 | ||
975 | done: | |
976 | return err; | |
977 | } | |
978 | ||
979 | static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) | |
980 | { | |
981 | int err; | |
982 | ||
983 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
984 | if (!err) | |
985 | err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); | |
986 | ||
987 | return err; | |
988 | } | |
989 | ||
990 | static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) | |
991 | { | |
992 | int err; | |
993 | ||
994 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
995 | if (!err) | |
996 | err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
997 | ||
998 | return err; | |
999 | } | |
1000 | ||
15ee95c3 MC |
1001 | static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) |
1002 | { | |
1003 | int err; | |
1004 | ||
1005 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
1006 | (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) | | |
1007 | MII_TG3_AUXCTL_SHDWSEL_MISC); | |
1008 | if (!err) | |
1009 | err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); | |
1010 | ||
1011 | return err; | |
1012 | } | |
1013 | ||
b4bd2929 MC |
1014 | static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) |
1015 | { | |
1016 | if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) | |
1017 | set |= MII_TG3_AUXCTL_MISC_WREN; | |
1018 | ||
1019 | return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); | |
1020 | } | |
1021 | ||
1d36ba45 MC |
1022 | #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \ |
1023 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1024 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \ | |
1025 | MII_TG3_AUXCTL_ACTL_TX_6DB) | |
1026 | ||
1027 | #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \ | |
1028 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1029 | MII_TG3_AUXCTL_ACTL_TX_6DB); | |
1030 | ||
95e2869a MC |
1031 | static int tg3_bmcr_reset(struct tg3 *tp) |
1032 | { | |
1033 | u32 phy_control; | |
1034 | int limit, err; | |
1035 | ||
1036 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
1037 | * clears or we time out. | |
1038 | */ | |
1039 | phy_control = BMCR_RESET; | |
1040 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
1041 | if (err != 0) | |
1042 | return -EBUSY; | |
1043 | ||
1044 | limit = 5000; | |
1045 | while (limit--) { | |
1046 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
1047 | if (err != 0) | |
1048 | return -EBUSY; | |
1049 | ||
1050 | if ((phy_control & BMCR_RESET) == 0) { | |
1051 | udelay(40); | |
1052 | break; | |
1053 | } | |
1054 | udelay(10); | |
1055 | } | |
d4675b52 | 1056 | if (limit < 0) |
95e2869a MC |
1057 | return -EBUSY; |
1058 | ||
1059 | return 0; | |
1060 | } | |
1061 | ||
158d7abd MC |
1062 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) |
1063 | { | |
3d16543d | 1064 | struct tg3 *tp = bp->priv; |
158d7abd MC |
1065 | u32 val; |
1066 | ||
24bb4fb6 | 1067 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1068 | |
1069 | if (tg3_readphy(tp, reg, &val)) | |
24bb4fb6 MC |
1070 | val = -EIO; |
1071 | ||
1072 | spin_unlock_bh(&tp->lock); | |
158d7abd MC |
1073 | |
1074 | return val; | |
1075 | } | |
1076 | ||
1077 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
1078 | { | |
3d16543d | 1079 | struct tg3 *tp = bp->priv; |
24bb4fb6 | 1080 | u32 ret = 0; |
158d7abd | 1081 | |
24bb4fb6 | 1082 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1083 | |
1084 | if (tg3_writephy(tp, reg, val)) | |
24bb4fb6 | 1085 | ret = -EIO; |
158d7abd | 1086 | |
24bb4fb6 MC |
1087 | spin_unlock_bh(&tp->lock); |
1088 | ||
1089 | return ret; | |
158d7abd MC |
1090 | } |
1091 | ||
1092 | static int tg3_mdio_reset(struct mii_bus *bp) | |
1093 | { | |
1094 | return 0; | |
1095 | } | |
1096 | ||
9c61d6bc | 1097 | static void tg3_mdio_config_5785(struct tg3 *tp) |
a9daf367 MC |
1098 | { |
1099 | u32 val; | |
fcb389df | 1100 | struct phy_device *phydev; |
a9daf367 | 1101 | |
3f0e3ad7 | 1102 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
fcb389df | 1103 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
6a443a0f MC |
1104 | case PHY_ID_BCM50610: |
1105 | case PHY_ID_BCM50610M: | |
fcb389df MC |
1106 | val = MAC_PHYCFG2_50610_LED_MODES; |
1107 | break; | |
6a443a0f | 1108 | case PHY_ID_BCMAC131: |
fcb389df MC |
1109 | val = MAC_PHYCFG2_AC131_LED_MODES; |
1110 | break; | |
6a443a0f | 1111 | case PHY_ID_RTL8211C: |
fcb389df MC |
1112 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; |
1113 | break; | |
6a443a0f | 1114 | case PHY_ID_RTL8201E: |
fcb389df MC |
1115 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; |
1116 | break; | |
1117 | default: | |
a9daf367 | 1118 | return; |
fcb389df MC |
1119 | } |
1120 | ||
1121 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
1122 | tw32(MAC_PHYCFG2, val); | |
1123 | ||
1124 | val = tr32(MAC_PHYCFG1); | |
bb85fbb6 MC |
1125 | val &= ~(MAC_PHYCFG1_RGMII_INT | |
1126 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
1127 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
fcb389df MC |
1128 | tw32(MAC_PHYCFG1, val); |
1129 | ||
1130 | return; | |
1131 | } | |
1132 | ||
63c3a66f | 1133 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) |
fcb389df MC |
1134 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | |
1135 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
1136 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
1137 | MAC_PHYCFG2_ACT_MASK_MASK | | |
1138 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
1139 | MAC_PHYCFG2_INBAND_ENABLE; | |
1140 | ||
1141 | tw32(MAC_PHYCFG2, val); | |
a9daf367 | 1142 | |
bb85fbb6 MC |
1143 | val = tr32(MAC_PHYCFG1); |
1144 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
1145 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
63c3a66f JP |
1146 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
1147 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
a9daf367 | 1148 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; |
63c3a66f | 1149 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 MC |
1150 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; |
1151 | } | |
bb85fbb6 MC |
1152 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | |
1153 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
1154 | tw32(MAC_PHYCFG1, val); | |
a9daf367 | 1155 | |
a9daf367 MC |
1156 | val = tr32(MAC_EXT_RGMII_MODE); |
1157 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
1158 | MAC_RGMII_MODE_RX_QUALITY | | |
1159 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1160 | MAC_RGMII_MODE_RX_ENG_DET | | |
1161 | MAC_RGMII_MODE_TX_ENABLE | | |
1162 | MAC_RGMII_MODE_TX_LOWPWR | | |
1163 | MAC_RGMII_MODE_TX_RESET); | |
63c3a66f JP |
1164 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
1165 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
a9daf367 MC |
1166 | val |= MAC_RGMII_MODE_RX_INT_B | |
1167 | MAC_RGMII_MODE_RX_QUALITY | | |
1168 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1169 | MAC_RGMII_MODE_RX_ENG_DET; | |
63c3a66f | 1170 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 MC |
1171 | val |= MAC_RGMII_MODE_TX_ENABLE | |
1172 | MAC_RGMII_MODE_TX_LOWPWR | | |
1173 | MAC_RGMII_MODE_TX_RESET; | |
1174 | } | |
1175 | tw32(MAC_EXT_RGMII_MODE, val); | |
1176 | } | |
1177 | ||
158d7abd MC |
1178 | static void tg3_mdio_start(struct tg3 *tp) |
1179 | { | |
158d7abd MC |
1180 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; |
1181 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1182 | udelay(80); | |
a9daf367 | 1183 | |
63c3a66f | 1184 | if (tg3_flag(tp, MDIOBUS_INITED) && |
9ea4818d MC |
1185 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
1186 | tg3_mdio_config_5785(tp); | |
1187 | } | |
1188 | ||
1189 | static int tg3_mdio_init(struct tg3 *tp) | |
1190 | { | |
1191 | int i; | |
1192 | u32 reg; | |
1193 | struct phy_device *phydev; | |
1194 | ||
63c3a66f | 1195 | if (tg3_flag(tp, 5717_PLUS)) { |
9c7df915 | 1196 | u32 is_serdes; |
882e9793 | 1197 | |
69f11c99 | 1198 | tp->phy_addr = tp->pci_fn + 1; |
882e9793 | 1199 | |
d1ec96af MC |
1200 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) |
1201 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | |
1202 | else | |
1203 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & | |
1204 | TG3_CPMU_PHY_STRAP_IS_SERDES; | |
882e9793 MC |
1205 | if (is_serdes) |
1206 | tp->phy_addr += 7; | |
1207 | } else | |
3f0e3ad7 | 1208 | tp->phy_addr = TG3_PHY_MII_ADDR; |
882e9793 | 1209 | |
158d7abd MC |
1210 | tg3_mdio_start(tp); |
1211 | ||
63c3a66f | 1212 | if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) |
158d7abd MC |
1213 | return 0; |
1214 | ||
298cf9be LB |
1215 | tp->mdio_bus = mdiobus_alloc(); |
1216 | if (tp->mdio_bus == NULL) | |
1217 | return -ENOMEM; | |
158d7abd | 1218 | |
298cf9be LB |
1219 | tp->mdio_bus->name = "tg3 mdio bus"; |
1220 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
158d7abd | 1221 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); |
298cf9be LB |
1222 | tp->mdio_bus->priv = tp; |
1223 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1224 | tp->mdio_bus->read = &tg3_mdio_read; | |
1225 | tp->mdio_bus->write = &tg3_mdio_write; | |
1226 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
3f0e3ad7 | 1227 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); |
298cf9be | 1228 | tp->mdio_bus->irq = &tp->mdio_irq[0]; |
158d7abd MC |
1229 | |
1230 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
298cf9be | 1231 | tp->mdio_bus->irq[i] = PHY_POLL; |
158d7abd MC |
1232 | |
1233 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1234 | * Unfortunately, it does not ensure the PHY is powered up before | |
1235 | * accessing the PHY ID registers. A chip reset is the | |
1236 | * quickest way to bring the device back to an operational state.. | |
1237 | */ | |
1238 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1239 | tg3_bmcr_reset(tp); | |
1240 | ||
298cf9be | 1241 | i = mdiobus_register(tp->mdio_bus); |
a9daf367 | 1242 | if (i) { |
ab96b241 | 1243 | dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); |
9c61d6bc | 1244 | mdiobus_free(tp->mdio_bus); |
a9daf367 MC |
1245 | return i; |
1246 | } | |
158d7abd | 1247 | |
3f0e3ad7 | 1248 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
a9daf367 | 1249 | |
9c61d6bc | 1250 | if (!phydev || !phydev->drv) { |
ab96b241 | 1251 | dev_warn(&tp->pdev->dev, "No PHY devices\n"); |
9c61d6bc MC |
1252 | mdiobus_unregister(tp->mdio_bus); |
1253 | mdiobus_free(tp->mdio_bus); | |
1254 | return -ENODEV; | |
1255 | } | |
1256 | ||
1257 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
6a443a0f | 1258 | case PHY_ID_BCM57780: |
321d32a0 | 1259 | phydev->interface = PHY_INTERFACE_MODE_GMII; |
c704dc23 | 1260 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
321d32a0 | 1261 | break; |
6a443a0f MC |
1262 | case PHY_ID_BCM50610: |
1263 | case PHY_ID_BCM50610M: | |
32e5a8d6 | 1264 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | |
c704dc23 | 1265 | PHY_BRCM_RX_REFCLK_UNUSED | |
52fae083 | 1266 | PHY_BRCM_DIS_TXCRXC_NOENRGY | |
c704dc23 | 1267 | PHY_BRCM_AUTO_PWRDWN_ENABLE; |
63c3a66f | 1268 | if (tg3_flag(tp, RGMII_INBAND_DISABLE)) |
a9daf367 | 1269 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; |
63c3a66f | 1270 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) |
a9daf367 | 1271 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; |
63c3a66f | 1272 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 | 1273 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; |
fcb389df | 1274 | /* fallthru */ |
6a443a0f | 1275 | case PHY_ID_RTL8211C: |
fcb389df | 1276 | phydev->interface = PHY_INTERFACE_MODE_RGMII; |
a9daf367 | 1277 | break; |
6a443a0f MC |
1278 | case PHY_ID_RTL8201E: |
1279 | case PHY_ID_BCMAC131: | |
a9daf367 | 1280 | phydev->interface = PHY_INTERFACE_MODE_MII; |
cdd4e09d | 1281 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
f07e9af3 | 1282 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
a9daf367 MC |
1283 | break; |
1284 | } | |
1285 | ||
63c3a66f | 1286 | tg3_flag_set(tp, MDIOBUS_INITED); |
9c61d6bc MC |
1287 | |
1288 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1289 | tg3_mdio_config_5785(tp); | |
a9daf367 MC |
1290 | |
1291 | return 0; | |
158d7abd MC |
1292 | } |
1293 | ||
1294 | static void tg3_mdio_fini(struct tg3 *tp) | |
1295 | { | |
63c3a66f JP |
1296 | if (tg3_flag(tp, MDIOBUS_INITED)) { |
1297 | tg3_flag_clear(tp, MDIOBUS_INITED); | |
298cf9be LB |
1298 | mdiobus_unregister(tp->mdio_bus); |
1299 | mdiobus_free(tp->mdio_bus); | |
158d7abd MC |
1300 | } |
1301 | } | |
1302 | ||
4ba526ce MC |
1303 | /* tp->lock is held. */ |
1304 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1305 | { | |
1306 | u32 val; | |
1307 | ||
1308 | val = tr32(GRC_RX_CPU_EVENT); | |
1309 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1310 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1311 | ||
1312 | tp->last_event_jiffies = jiffies; | |
1313 | } | |
1314 | ||
1315 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1316 | ||
95e2869a MC |
1317 | /* tp->lock is held. */ |
1318 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1319 | { | |
1320 | int i; | |
4ba526ce MC |
1321 | unsigned int delay_cnt; |
1322 | long time_remain; | |
1323 | ||
1324 | /* If enough time has passed, no wait is necessary. */ | |
1325 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1326 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1327 | (long)jiffies; | |
1328 | if (time_remain < 0) | |
1329 | return; | |
1330 | ||
1331 | /* Check if we can shorten the wait time. */ | |
1332 | delay_cnt = jiffies_to_usecs(time_remain); | |
1333 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1334 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1335 | delay_cnt = (delay_cnt >> 3) + 1; | |
95e2869a | 1336 | |
4ba526ce | 1337 | for (i = 0; i < delay_cnt; i++) { |
95e2869a MC |
1338 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) |
1339 | break; | |
4ba526ce | 1340 | udelay(8); |
95e2869a MC |
1341 | } |
1342 | } | |
1343 | ||
1344 | /* tp->lock is held. */ | |
1345 | static void tg3_ump_link_report(struct tg3 *tp) | |
1346 | { | |
1347 | u32 reg; | |
1348 | u32 val; | |
1349 | ||
63c3a66f | 1350 | if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) |
95e2869a MC |
1351 | return; |
1352 | ||
1353 | tg3_wait_for_event_ack(tp); | |
1354 | ||
1355 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1356 | ||
1357 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1358 | ||
1359 | val = 0; | |
1360 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1361 | val = reg << 16; | |
1362 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1363 | val |= (reg & 0xffff); | |
1364 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val); | |
1365 | ||
1366 | val = 0; | |
1367 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1368 | val = reg << 16; | |
1369 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1370 | val |= (reg & 0xffff); | |
1371 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val); | |
1372 | ||
1373 | val = 0; | |
f07e9af3 | 1374 | if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { |
95e2869a MC |
1375 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) |
1376 | val = reg << 16; | |
1377 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1378 | val |= (reg & 0xffff); | |
1379 | } | |
1380 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val); | |
1381 | ||
1382 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1383 | val = reg << 16; | |
1384 | else | |
1385 | val = 0; | |
1386 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); | |
1387 | ||
4ba526ce | 1388 | tg3_generate_fw_event(tp); |
95e2869a MC |
1389 | } |
1390 | ||
1391 | static void tg3_link_report(struct tg3 *tp) | |
1392 | { | |
1393 | if (!netif_carrier_ok(tp->dev)) { | |
05dbe005 | 1394 | netif_info(tp, link, tp->dev, "Link is down\n"); |
95e2869a MC |
1395 | tg3_ump_link_report(tp); |
1396 | } else if (netif_msg_link(tp)) { | |
05dbe005 JP |
1397 | netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", |
1398 | (tp->link_config.active_speed == SPEED_1000 ? | |
1399 | 1000 : | |
1400 | (tp->link_config.active_speed == SPEED_100 ? | |
1401 | 100 : 10)), | |
1402 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1403 | "full" : "half")); | |
1404 | ||
1405 | netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", | |
1406 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? | |
1407 | "on" : "off", | |
1408 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? | |
1409 | "on" : "off"); | |
47007831 MC |
1410 | |
1411 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) | |
1412 | netdev_info(tp->dev, "EEE is %s\n", | |
1413 | tp->setlpicnt ? "enabled" : "disabled"); | |
1414 | ||
95e2869a MC |
1415 | tg3_ump_link_report(tp); |
1416 | } | |
1417 | } | |
1418 | ||
1419 | static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl) | |
1420 | { | |
1421 | u16 miireg; | |
1422 | ||
e18ce346 | 1423 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1424 | miireg = ADVERTISE_PAUSE_CAP; |
e18ce346 | 1425 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1426 | miireg = ADVERTISE_PAUSE_ASYM; |
e18ce346 | 1427 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1428 | miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1429 | else | |
1430 | miireg = 0; | |
1431 | ||
1432 | return miireg; | |
1433 | } | |
1434 | ||
1435 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) | |
1436 | { | |
1437 | u16 miireg; | |
1438 | ||
e18ce346 | 1439 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1440 | miireg = ADVERTISE_1000XPAUSE; |
e18ce346 | 1441 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1442 | miireg = ADVERTISE_1000XPSE_ASYM; |
e18ce346 | 1443 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1444 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1445 | else | |
1446 | miireg = 0; | |
1447 | ||
1448 | return miireg; | |
1449 | } | |
1450 | ||
95e2869a MC |
1451 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
1452 | { | |
1453 | u8 cap = 0; | |
1454 | ||
1455 | if (lcladv & ADVERTISE_1000XPAUSE) { | |
1456 | if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1457 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1458 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a | 1459 | else if (rmtadv & LPA_1000XPAUSE_ASYM) |
e18ce346 | 1460 | cap = FLOW_CTRL_RX; |
95e2869a MC |
1461 | } else { |
1462 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1463 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a MC |
1464 | } |
1465 | } else if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1466 | if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM)) | |
e18ce346 | 1467 | cap = FLOW_CTRL_TX; |
95e2869a MC |
1468 | } |
1469 | ||
1470 | return cap; | |
1471 | } | |
1472 | ||
f51f3562 | 1473 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
95e2869a | 1474 | { |
b02fd9e3 | 1475 | u8 autoneg; |
f51f3562 | 1476 | u8 flowctrl = 0; |
95e2869a MC |
1477 | u32 old_rx_mode = tp->rx_mode; |
1478 | u32 old_tx_mode = tp->tx_mode; | |
1479 | ||
63c3a66f | 1480 | if (tg3_flag(tp, USE_PHYLIB)) |
3f0e3ad7 | 1481 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; |
b02fd9e3 MC |
1482 | else |
1483 | autoneg = tp->link_config.autoneg; | |
1484 | ||
63c3a66f | 1485 | if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { |
f07e9af3 | 1486 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
f51f3562 | 1487 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
95e2869a | 1488 | else |
bc02ff95 | 1489 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
f51f3562 MC |
1490 | } else |
1491 | flowctrl = tp->link_config.flowctrl; | |
95e2869a | 1492 | |
f51f3562 | 1493 | tp->link_config.active_flowctrl = flowctrl; |
95e2869a | 1494 | |
e18ce346 | 1495 | if (flowctrl & FLOW_CTRL_RX) |
95e2869a MC |
1496 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
1497 | else | |
1498 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1499 | ||
f51f3562 | 1500 | if (old_rx_mode != tp->rx_mode) |
95e2869a | 1501 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
95e2869a | 1502 | |
e18ce346 | 1503 | if (flowctrl & FLOW_CTRL_TX) |
95e2869a MC |
1504 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1505 | else | |
1506 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1507 | ||
f51f3562 | 1508 | if (old_tx_mode != tp->tx_mode) |
95e2869a | 1509 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
95e2869a MC |
1510 | } |
1511 | ||
b02fd9e3 MC |
1512 | static void tg3_adjust_link(struct net_device *dev) |
1513 | { | |
1514 | u8 oldflowctrl, linkmesg = 0; | |
1515 | u32 mac_mode, lcl_adv, rmt_adv; | |
1516 | struct tg3 *tp = netdev_priv(dev); | |
3f0e3ad7 | 1517 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1518 | |
24bb4fb6 | 1519 | spin_lock_bh(&tp->lock); |
b02fd9e3 MC |
1520 | |
1521 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1522 | MAC_MODE_HALF_DUPLEX); | |
1523 | ||
1524 | oldflowctrl = tp->link_config.active_flowctrl; | |
1525 | ||
1526 | if (phydev->link) { | |
1527 | lcl_adv = 0; | |
1528 | rmt_adv = 0; | |
1529 | ||
1530 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1531 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
c3df0748 MC |
1532 | else if (phydev->speed == SPEED_1000 || |
1533 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | |
b02fd9e3 | 1534 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
c3df0748 MC |
1535 | else |
1536 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
b02fd9e3 MC |
1537 | |
1538 | if (phydev->duplex == DUPLEX_HALF) | |
1539 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1540 | else { | |
1541 | lcl_adv = tg3_advert_flowctrl_1000T( | |
1542 | tp->link_config.flowctrl); | |
1543 | ||
1544 | if (phydev->pause) | |
1545 | rmt_adv = LPA_PAUSE_CAP; | |
1546 | if (phydev->asym_pause) | |
1547 | rmt_adv |= LPA_PAUSE_ASYM; | |
1548 | } | |
1549 | ||
1550 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1551 | } else | |
1552 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1553 | ||
1554 | if (mac_mode != tp->mac_mode) { | |
1555 | tp->mac_mode = mac_mode; | |
1556 | tw32_f(MAC_MODE, tp->mac_mode); | |
1557 | udelay(40); | |
1558 | } | |
1559 | ||
fcb389df MC |
1560 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
1561 | if (phydev->speed == SPEED_10) | |
1562 | tw32(MAC_MI_STAT, | |
1563 | MAC_MI_STAT_10MBPS_MODE | | |
1564 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1565 | else | |
1566 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1567 | } | |
1568 | ||
b02fd9e3 MC |
1569 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) |
1570 | tw32(MAC_TX_LENGTHS, | |
1571 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1572 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1573 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1574 | else | |
1575 | tw32(MAC_TX_LENGTHS, | |
1576 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1577 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1578 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1579 | ||
1580 | if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || | |
1581 | (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) || | |
1582 | phydev->speed != tp->link_config.active_speed || | |
1583 | phydev->duplex != tp->link_config.active_duplex || | |
1584 | oldflowctrl != tp->link_config.active_flowctrl) | |
c6cdf436 | 1585 | linkmesg = 1; |
b02fd9e3 MC |
1586 | |
1587 | tp->link_config.active_speed = phydev->speed; | |
1588 | tp->link_config.active_duplex = phydev->duplex; | |
1589 | ||
24bb4fb6 | 1590 | spin_unlock_bh(&tp->lock); |
b02fd9e3 MC |
1591 | |
1592 | if (linkmesg) | |
1593 | tg3_link_report(tp); | |
1594 | } | |
1595 | ||
1596 | static int tg3_phy_init(struct tg3 *tp) | |
1597 | { | |
1598 | struct phy_device *phydev; | |
1599 | ||
f07e9af3 | 1600 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) |
b02fd9e3 MC |
1601 | return 0; |
1602 | ||
1603 | /* Bring the PHY back to a known state. */ | |
1604 | tg3_bmcr_reset(tp); | |
1605 | ||
3f0e3ad7 | 1606 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
1607 | |
1608 | /* Attach the MAC to the PHY. */ | |
fb28ad35 | 1609 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, |
a9daf367 | 1610 | phydev->dev_flags, phydev->interface); |
b02fd9e3 | 1611 | if (IS_ERR(phydev)) { |
ab96b241 | 1612 | dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); |
b02fd9e3 MC |
1613 | return PTR_ERR(phydev); |
1614 | } | |
1615 | ||
b02fd9e3 | 1616 | /* Mask with MAC supported features. */ |
9c61d6bc MC |
1617 | switch (phydev->interface) { |
1618 | case PHY_INTERFACE_MODE_GMII: | |
1619 | case PHY_INTERFACE_MODE_RGMII: | |
f07e9af3 | 1620 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
321d32a0 MC |
1621 | phydev->supported &= (PHY_GBIT_FEATURES | |
1622 | SUPPORTED_Pause | | |
1623 | SUPPORTED_Asym_Pause); | |
1624 | break; | |
1625 | } | |
1626 | /* fallthru */ | |
9c61d6bc MC |
1627 | case PHY_INTERFACE_MODE_MII: |
1628 | phydev->supported &= (PHY_BASIC_FEATURES | | |
1629 | SUPPORTED_Pause | | |
1630 | SUPPORTED_Asym_Pause); | |
1631 | break; | |
1632 | default: | |
3f0e3ad7 | 1633 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
9c61d6bc MC |
1634 | return -EINVAL; |
1635 | } | |
1636 | ||
f07e9af3 | 1637 | tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1638 | |
1639 | phydev->advertising = phydev->supported; | |
1640 | ||
b02fd9e3 MC |
1641 | return 0; |
1642 | } | |
1643 | ||
1644 | static void tg3_phy_start(struct tg3 *tp) | |
1645 | { | |
1646 | struct phy_device *phydev; | |
1647 | ||
f07e9af3 | 1648 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1649 | return; |
1650 | ||
3f0e3ad7 | 1651 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1652 | |
80096068 MC |
1653 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
1654 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
b02fd9e3 MC |
1655 | phydev->speed = tp->link_config.orig_speed; |
1656 | phydev->duplex = tp->link_config.orig_duplex; | |
1657 | phydev->autoneg = tp->link_config.orig_autoneg; | |
1658 | phydev->advertising = tp->link_config.orig_advertising; | |
1659 | } | |
1660 | ||
1661 | phy_start(phydev); | |
1662 | ||
1663 | phy_start_aneg(phydev); | |
1664 | } | |
1665 | ||
1666 | static void tg3_phy_stop(struct tg3 *tp) | |
1667 | { | |
f07e9af3 | 1668 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1669 | return; |
1670 | ||
3f0e3ad7 | 1671 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
1672 | } |
1673 | ||
1674 | static void tg3_phy_fini(struct tg3 *tp) | |
1675 | { | |
f07e9af3 | 1676 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 | 1677 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
f07e9af3 | 1678 | tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1679 | } |
1680 | } | |
1681 | ||
7f97a4bd MC |
1682 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) |
1683 | { | |
1684 | u32 phytest; | |
1685 | ||
1686 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
1687 | u32 phy; | |
1688 | ||
1689 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1690 | phytest | MII_TG3_FET_SHADOW_EN); | |
1691 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
1692 | if (enable) | |
1693 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1694 | else | |
1695 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1696 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
1697 | } | |
1698 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
1699 | } | |
1700 | } | |
1701 | ||
6833c043 MC |
1702 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
1703 | { | |
1704 | u32 reg; | |
1705 | ||
63c3a66f JP |
1706 | if (!tg3_flag(tp, 5705_PLUS) || |
1707 | (tg3_flag(tp, 5717_PLUS) && | |
f07e9af3 | 1708 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
6833c043 MC |
1709 | return; |
1710 | ||
f07e9af3 | 1711 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd MC |
1712 | tg3_phy_fet_toggle_apd(tp, enable); |
1713 | return; | |
1714 | } | |
1715 | ||
6833c043 MC |
1716 | reg = MII_TG3_MISC_SHDW_WREN | |
1717 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
1718 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
1719 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
1720 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
1721 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
1722 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
1723 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
1724 | ||
1725 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1726 | ||
1727 | ||
1728 | reg = MII_TG3_MISC_SHDW_WREN | | |
1729 | MII_TG3_MISC_SHDW_APD_SEL | | |
1730 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
1731 | if (enable) | |
1732 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
1733 | ||
1734 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1735 | } | |
1736 | ||
9ef8ca99 MC |
1737 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) |
1738 | { | |
1739 | u32 phy; | |
1740 | ||
63c3a66f | 1741 | if (!tg3_flag(tp, 5705_PLUS) || |
f07e9af3 | 1742 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
9ef8ca99 MC |
1743 | return; |
1744 | ||
f07e9af3 | 1745 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
9ef8ca99 MC |
1746 | u32 ephy; |
1747 | ||
535ef6e1 MC |
1748 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
1749 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
1750 | ||
1751 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1752 | ephy | MII_TG3_FET_SHADOW_EN); | |
1753 | if (!tg3_readphy(tp, reg, &phy)) { | |
9ef8ca99 | 1754 | if (enable) |
535ef6e1 | 1755 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
9ef8ca99 | 1756 | else |
535ef6e1 MC |
1757 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
1758 | tg3_writephy(tp, reg, phy); | |
9ef8ca99 | 1759 | } |
535ef6e1 | 1760 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); |
9ef8ca99 MC |
1761 | } |
1762 | } else { | |
15ee95c3 MC |
1763 | int ret; |
1764 | ||
1765 | ret = tg3_phy_auxctl_read(tp, | |
1766 | MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); | |
1767 | if (!ret) { | |
9ef8ca99 MC |
1768 | if (enable) |
1769 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1770 | else | |
1771 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
b4bd2929 MC |
1772 | tg3_phy_auxctl_write(tp, |
1773 | MII_TG3_AUXCTL_SHDWSEL_MISC, phy); | |
9ef8ca99 MC |
1774 | } |
1775 | } | |
1776 | } | |
1777 | ||
1da177e4 LT |
1778 | static void tg3_phy_set_wirespeed(struct tg3 *tp) |
1779 | { | |
15ee95c3 | 1780 | int ret; |
1da177e4 LT |
1781 | u32 val; |
1782 | ||
f07e9af3 | 1783 | if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) |
1da177e4 LT |
1784 | return; |
1785 | ||
15ee95c3 MC |
1786 | ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); |
1787 | if (!ret) | |
b4bd2929 MC |
1788 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, |
1789 | val | MII_TG3_AUXCTL_MISC_WIRESPD_EN); | |
1da177e4 LT |
1790 | } |
1791 | ||
b2a5c19c MC |
1792 | static void tg3_phy_apply_otp(struct tg3 *tp) |
1793 | { | |
1794 | u32 otp, phy; | |
1795 | ||
1796 | if (!tp->phy_otp) | |
1797 | return; | |
1798 | ||
1799 | otp = tp->phy_otp; | |
1800 | ||
1d36ba45 MC |
1801 | if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) |
1802 | return; | |
b2a5c19c MC |
1803 | |
1804 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
1805 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
1806 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
1807 | ||
1808 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
1809 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
1810 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
1811 | ||
1812 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
1813 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
1814 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
1815 | ||
1816 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
1817 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
1818 | ||
1819 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
1820 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
1821 | ||
1822 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
1823 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
1824 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
1825 | ||
1d36ba45 | 1826 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
b2a5c19c MC |
1827 | } |
1828 | ||
52b02d04 MC |
1829 | static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) |
1830 | { | |
1831 | u32 val; | |
1832 | ||
1833 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) | |
1834 | return; | |
1835 | ||
1836 | tp->setlpicnt = 0; | |
1837 | ||
1838 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | |
1839 | current_link_up == 1 && | |
a6b68dab MC |
1840 | tp->link_config.active_duplex == DUPLEX_FULL && |
1841 | (tp->link_config.active_speed == SPEED_100 || | |
1842 | tp->link_config.active_speed == SPEED_1000)) { | |
52b02d04 MC |
1843 | u32 eeectl; |
1844 | ||
1845 | if (tp->link_config.active_speed == SPEED_1000) | |
1846 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US; | |
1847 | else | |
1848 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US; | |
1849 | ||
1850 | tw32(TG3_CPMU_EEE_CTRL, eeectl); | |
1851 | ||
3110f5f5 MC |
1852 | tg3_phy_cl45_read(tp, MDIO_MMD_AN, |
1853 | TG3_CL45_D7_EEERES_STAT, &val); | |
52b02d04 | 1854 | |
b0c5943f MC |
1855 | if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T || |
1856 | val == TG3_CL45_D7_EEERES_STAT_LP_100TX) | |
52b02d04 MC |
1857 | tp->setlpicnt = 2; |
1858 | } | |
1859 | ||
1860 | if (!tp->setlpicnt) { | |
b715ce94 MC |
1861 | if (current_link_up == 1 && |
1862 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
1863 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); | |
1864 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
1865 | } | |
1866 | ||
52b02d04 MC |
1867 | val = tr32(TG3_CPMU_EEE_MODE); |
1868 | tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
1869 | } | |
1870 | } | |
1871 | ||
b0c5943f MC |
1872 | static void tg3_phy_eee_enable(struct tg3 *tp) |
1873 | { | |
1874 | u32 val; | |
1875 | ||
1876 | if (tp->link_config.active_speed == SPEED_1000 && | |
1877 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
1878 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
1879 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) && | |
1880 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
b715ce94 MC |
1881 | val = MII_TG3_DSP_TAP26_ALNOKO | |
1882 | MII_TG3_DSP_TAP26_RMRXSTO; | |
1883 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); | |
b0c5943f MC |
1884 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1885 | } | |
1886 | ||
1887 | val = tr32(TG3_CPMU_EEE_MODE); | |
1888 | tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE); | |
1889 | } | |
1890 | ||
1da177e4 LT |
1891 | static int tg3_wait_macro_done(struct tg3 *tp) |
1892 | { | |
1893 | int limit = 100; | |
1894 | ||
1895 | while (limit--) { | |
1896 | u32 tmp32; | |
1897 | ||
f08aa1a8 | 1898 | if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { |
1da177e4 LT |
1899 | if ((tmp32 & 0x1000) == 0) |
1900 | break; | |
1901 | } | |
1902 | } | |
d4675b52 | 1903 | if (limit < 0) |
1da177e4 LT |
1904 | return -EBUSY; |
1905 | ||
1906 | return 0; | |
1907 | } | |
1908 | ||
1909 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
1910 | { | |
1911 | static const u32 test_pat[4][6] = { | |
1912 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
1913 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
1914 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
1915 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
1916 | }; | |
1917 | int chan; | |
1918 | ||
1919 | for (chan = 0; chan < 4; chan++) { | |
1920 | int i; | |
1921 | ||
1922 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1923 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1924 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
1925 | |
1926 | for (i = 0; i < 6; i++) | |
1927 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
1928 | test_pat[chan][i]); | |
1929 | ||
f08aa1a8 | 1930 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
1931 | if (tg3_wait_macro_done(tp)) { |
1932 | *resetp = 1; | |
1933 | return -EBUSY; | |
1934 | } | |
1935 | ||
1936 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1937 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1938 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); |
1da177e4 LT |
1939 | if (tg3_wait_macro_done(tp)) { |
1940 | *resetp = 1; | |
1941 | return -EBUSY; | |
1942 | } | |
1943 | ||
f08aa1a8 | 1944 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); |
1da177e4 LT |
1945 | if (tg3_wait_macro_done(tp)) { |
1946 | *resetp = 1; | |
1947 | return -EBUSY; | |
1948 | } | |
1949 | ||
1950 | for (i = 0; i < 6; i += 2) { | |
1951 | u32 low, high; | |
1952 | ||
1953 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
1954 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
1955 | tg3_wait_macro_done(tp)) { | |
1956 | *resetp = 1; | |
1957 | return -EBUSY; | |
1958 | } | |
1959 | low &= 0x7fff; | |
1960 | high &= 0x000f; | |
1961 | if (low != test_pat[chan][i] || | |
1962 | high != test_pat[chan][i+1]) { | |
1963 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
1964 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
1965 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
1966 | ||
1967 | return -EBUSY; | |
1968 | } | |
1969 | } | |
1970 | } | |
1971 | ||
1972 | return 0; | |
1973 | } | |
1974 | ||
1975 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
1976 | { | |
1977 | int chan; | |
1978 | ||
1979 | for (chan = 0; chan < 4; chan++) { | |
1980 | int i; | |
1981 | ||
1982 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1983 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1984 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
1985 | for (i = 0; i < 6; i++) |
1986 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
f08aa1a8 | 1987 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
1988 | if (tg3_wait_macro_done(tp)) |
1989 | return -EBUSY; | |
1990 | } | |
1991 | ||
1992 | return 0; | |
1993 | } | |
1994 | ||
1995 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
1996 | { | |
1997 | u32 reg32, phy9_orig; | |
1998 | int retries, do_phy_reset, err; | |
1999 | ||
2000 | retries = 10; | |
2001 | do_phy_reset = 1; | |
2002 | do { | |
2003 | if (do_phy_reset) { | |
2004 | err = tg3_bmcr_reset(tp); | |
2005 | if (err) | |
2006 | return err; | |
2007 | do_phy_reset = 0; | |
2008 | } | |
2009 | ||
2010 | /* Disable transmitter and interrupt. */ | |
2011 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
2012 | continue; | |
2013 | ||
2014 | reg32 |= 0x3000; | |
2015 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2016 | ||
2017 | /* Set full-duplex, 1000 mbps. */ | |
2018 | tg3_writephy(tp, MII_BMCR, | |
221c5637 | 2019 | BMCR_FULLDPLX | BMCR_SPEED1000); |
1da177e4 LT |
2020 | |
2021 | /* Set to master mode. */ | |
221c5637 | 2022 | if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) |
1da177e4 LT |
2023 | continue; |
2024 | ||
221c5637 MC |
2025 | tg3_writephy(tp, MII_CTRL1000, |
2026 | CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER); | |
1da177e4 | 2027 | |
1d36ba45 MC |
2028 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
2029 | if (err) | |
2030 | return err; | |
1da177e4 LT |
2031 | |
2032 | /* Block the PHY control access. */ | |
6ee7c0a0 | 2033 | tg3_phydsp_write(tp, 0x8005, 0x0800); |
1da177e4 LT |
2034 | |
2035 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
2036 | if (!err) | |
2037 | break; | |
2038 | } while (--retries); | |
2039 | ||
2040 | err = tg3_phy_reset_chanpat(tp); | |
2041 | if (err) | |
2042 | return err; | |
2043 | ||
6ee7c0a0 | 2044 | tg3_phydsp_write(tp, 0x8005, 0x0000); |
1da177e4 LT |
2045 | |
2046 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
f08aa1a8 | 2047 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); |
1da177e4 | 2048 | |
1d36ba45 | 2049 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2050 | |
221c5637 | 2051 | tg3_writephy(tp, MII_CTRL1000, phy9_orig); |
1da177e4 LT |
2052 | |
2053 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
2054 | reg32 &= ~0x3000; | |
2055 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2056 | } else if (!err) | |
2057 | err = -EBUSY; | |
2058 | ||
2059 | return err; | |
2060 | } | |
2061 | ||
2062 | /* This will reset the tigon3 PHY if there is no valid | |
2063 | * link unless the FORCE argument is non-zero. | |
2064 | */ | |
2065 | static int tg3_phy_reset(struct tg3 *tp) | |
2066 | { | |
f833c4c1 | 2067 | u32 val, cpmuctrl; |
1da177e4 LT |
2068 | int err; |
2069 | ||
60189ddf | 2070 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2071 | val = tr32(GRC_MISC_CFG); |
2072 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
2073 | udelay(40); | |
2074 | } | |
f833c4c1 MC |
2075 | err = tg3_readphy(tp, MII_BMSR, &val); |
2076 | err |= tg3_readphy(tp, MII_BMSR, &val); | |
1da177e4 LT |
2077 | if (err != 0) |
2078 | return -EBUSY; | |
2079 | ||
c8e1e82b MC |
2080 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { |
2081 | netif_carrier_off(tp->dev); | |
2082 | tg3_link_report(tp); | |
2083 | } | |
2084 | ||
1da177e4 LT |
2085 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
2086 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2087 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
2088 | err = tg3_phy_reset_5703_4_5(tp); | |
2089 | if (err) | |
2090 | return err; | |
2091 | goto out; | |
2092 | } | |
2093 | ||
b2a5c19c MC |
2094 | cpmuctrl = 0; |
2095 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
2096 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
2097 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
2098 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
2099 | tw32(TG3_CPMU_CTRL, | |
2100 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
2101 | } | |
2102 | ||
1da177e4 LT |
2103 | err = tg3_bmcr_reset(tp); |
2104 | if (err) | |
2105 | return err; | |
2106 | ||
b2a5c19c | 2107 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { |
f833c4c1 MC |
2108 | val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; |
2109 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); | |
b2a5c19c MC |
2110 | |
2111 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
2112 | } | |
2113 | ||
bcb37f6c MC |
2114 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2115 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2116 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2117 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
2118 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
2119 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2120 | udelay(40); | |
2121 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2122 | } | |
2123 | } | |
2124 | ||
63c3a66f | 2125 | if (tg3_flag(tp, 5717_PLUS) && |
f07e9af3 | 2126 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) |
ecf1410b MC |
2127 | return 0; |
2128 | ||
b2a5c19c MC |
2129 | tg3_phy_apply_otp(tp); |
2130 | ||
f07e9af3 | 2131 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
2132 | tg3_phy_toggle_apd(tp, true); |
2133 | else | |
2134 | tg3_phy_toggle_apd(tp, false); | |
2135 | ||
1da177e4 | 2136 | out: |
1d36ba45 MC |
2137 | if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && |
2138 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
6ee7c0a0 MC |
2139 | tg3_phydsp_write(tp, 0x201f, 0x2aaa); |
2140 | tg3_phydsp_write(tp, 0x000a, 0x0323); | |
1d36ba45 | 2141 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2142 | } |
1d36ba45 | 2143 | |
f07e9af3 | 2144 | if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { |
f08aa1a8 MC |
2145 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); |
2146 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
1da177e4 | 2147 | } |
1d36ba45 | 2148 | |
f07e9af3 | 2149 | if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { |
1d36ba45 MC |
2150 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2151 | tg3_phydsp_write(tp, 0x000a, 0x310b); | |
2152 | tg3_phydsp_write(tp, 0x201f, 0x9506); | |
2153 | tg3_phydsp_write(tp, 0x401f, 0x14e2); | |
2154 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2155 | } | |
f07e9af3 | 2156 | } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { |
1d36ba45 MC |
2157 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2158 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
2159 | if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { | |
2160 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); | |
2161 | tg3_writephy(tp, MII_TG3_TEST1, | |
2162 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
2163 | } else | |
2164 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
2165 | ||
2166 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2167 | } | |
c424cb24 | 2168 | } |
1d36ba45 | 2169 | |
1da177e4 LT |
2170 | /* Set Extended packet length bit (bit 14) on all chips that */ |
2171 | /* support jumbo frames */ | |
79eb6904 | 2172 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 | 2173 | /* Cannot do read-modify-write on 5401 */ |
b4bd2929 | 2174 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
63c3a66f | 2175 | } else if (tg3_flag(tp, JUMBO_CAPABLE)) { |
1da177e4 | 2176 | /* Set bit 14 with read-modify-write to preserve other bits */ |
15ee95c3 MC |
2177 | err = tg3_phy_auxctl_read(tp, |
2178 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); | |
2179 | if (!err) | |
b4bd2929 MC |
2180 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, |
2181 | val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN); | |
1da177e4 LT |
2182 | } |
2183 | ||
2184 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
2185 | * jumbo frames transmission. | |
2186 | */ | |
63c3a66f | 2187 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
f833c4c1 | 2188 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) |
c6cdf436 | 2189 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
f833c4c1 | 2190 | val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); |
1da177e4 LT |
2191 | } |
2192 | ||
715116a1 | 2193 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
715116a1 | 2194 | /* adjust output voltage */ |
535ef6e1 | 2195 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
715116a1 MC |
2196 | } |
2197 | ||
9ef8ca99 | 2198 | tg3_phy_toggle_automdix(tp, 1); |
1da177e4 LT |
2199 | tg3_phy_set_wirespeed(tp); |
2200 | return 0; | |
2201 | } | |
2202 | ||
3a1e19d3 MC |
2203 | #define TG3_GPIO_MSG_DRVR_PRES 0x00000001 |
2204 | #define TG3_GPIO_MSG_NEED_VAUX 0x00000002 | |
2205 | #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \ | |
2206 | TG3_GPIO_MSG_NEED_VAUX) | |
2207 | #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \ | |
2208 | ((TG3_GPIO_MSG_DRVR_PRES << 0) | \ | |
2209 | (TG3_GPIO_MSG_DRVR_PRES << 4) | \ | |
2210 | (TG3_GPIO_MSG_DRVR_PRES << 8) | \ | |
2211 | (TG3_GPIO_MSG_DRVR_PRES << 12)) | |
2212 | ||
2213 | #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \ | |
2214 | ((TG3_GPIO_MSG_NEED_VAUX << 0) | \ | |
2215 | (TG3_GPIO_MSG_NEED_VAUX << 4) | \ | |
2216 | (TG3_GPIO_MSG_NEED_VAUX << 8) | \ | |
2217 | (TG3_GPIO_MSG_NEED_VAUX << 12)) | |
2218 | ||
2219 | static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) | |
2220 | { | |
2221 | u32 status, shift; | |
2222 | ||
2223 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2224 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
2225 | status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG); | |
2226 | else | |
2227 | status = tr32(TG3_CPMU_DRV_STATUS); | |
2228 | ||
2229 | shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; | |
2230 | status &= ~(TG3_GPIO_MSG_MASK << shift); | |
2231 | status |= (newstat << shift); | |
2232 | ||
2233 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2234 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
2235 | tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status); | |
2236 | else | |
2237 | tw32(TG3_CPMU_DRV_STATUS, status); | |
2238 | ||
2239 | return status >> TG3_APE_GPIO_MSG_SHIFT; | |
2240 | } | |
2241 | ||
520b2756 MC |
2242 | static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) |
2243 | { | |
2244 | if (!tg3_flag(tp, IS_NIC)) | |
2245 | return 0; | |
2246 | ||
3a1e19d3 MC |
2247 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2248 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
2249 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
2250 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | |
2251 | return -EIO; | |
520b2756 | 2252 | |
3a1e19d3 MC |
2253 | tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES); |
2254 | ||
2255 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, | |
2256 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2257 | ||
2258 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); | |
2259 | } else { | |
2260 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, | |
2261 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2262 | } | |
6f5c8f83 | 2263 | |
520b2756 MC |
2264 | return 0; |
2265 | } | |
2266 | ||
2267 | static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) | |
2268 | { | |
2269 | u32 grc_local_ctrl; | |
2270 | ||
2271 | if (!tg3_flag(tp, IS_NIC) || | |
2272 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2273 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) | |
2274 | return; | |
2275 | ||
2276 | grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; | |
2277 | ||
2278 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2279 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, | |
2280 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2281 | ||
2282 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2283 | grc_local_ctrl, | |
2284 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2285 | ||
2286 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2287 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, | |
2288 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2289 | } | |
2290 | ||
2291 | static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) | |
2292 | { | |
2293 | if (!tg3_flag(tp, IS_NIC)) | |
2294 | return; | |
2295 | ||
2296 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2297 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2298 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2299 | (GRC_LCLCTRL_GPIO_OE0 | | |
2300 | GRC_LCLCTRL_GPIO_OE1 | | |
2301 | GRC_LCLCTRL_GPIO_OE2 | | |
2302 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2303 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
2304 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2305 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || | |
2306 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
2307 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ | |
2308 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
2309 | GRC_LCLCTRL_GPIO_OE1 | | |
2310 | GRC_LCLCTRL_GPIO_OE2 | | |
2311 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2312 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2313 | tp->grc_local_ctrl; | |
2314 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2315 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2316 | ||
2317 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2318 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2319 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2320 | ||
2321 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2322 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2323 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2324 | } else { | |
2325 | u32 no_gpio2; | |
2326 | u32 grc_local_ctrl = 0; | |
2327 | ||
2328 | /* Workaround to prevent overdrawing Amps. */ | |
2329 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
2330 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
2331 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2332 | grc_local_ctrl, | |
2333 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2334 | } | |
2335 | ||
2336 | /* On 5753 and variants, GPIO2 cannot be used. */ | |
2337 | no_gpio2 = tp->nic_sram_data_cfg & | |
2338 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2339 | ||
2340 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
2341 | GRC_LCLCTRL_GPIO_OE1 | | |
2342 | GRC_LCLCTRL_GPIO_OE2 | | |
2343 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2344 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2345 | if (no_gpio2) { | |
2346 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2347 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2348 | } | |
2349 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2350 | tp->grc_local_ctrl | grc_local_ctrl, | |
2351 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2352 | ||
2353 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2354 | ||
2355 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2356 | tp->grc_local_ctrl | grc_local_ctrl, | |
2357 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2358 | ||
2359 | if (!no_gpio2) { | |
2360 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
2361 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2362 | tp->grc_local_ctrl | grc_local_ctrl, | |
2363 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2364 | } | |
2365 | } | |
3a1e19d3 MC |
2366 | } |
2367 | ||
cd0d7228 | 2368 | static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable) |
3a1e19d3 MC |
2369 | { |
2370 | u32 msg = 0; | |
2371 | ||
2372 | /* Serialize power state transitions */ | |
2373 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | |
2374 | return; | |
2375 | ||
cd0d7228 | 2376 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable) |
3a1e19d3 MC |
2377 | msg = TG3_GPIO_MSG_NEED_VAUX; |
2378 | ||
2379 | msg = tg3_set_function_status(tp, msg); | |
2380 | ||
2381 | if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK) | |
2382 | goto done; | |
6f5c8f83 | 2383 | |
3a1e19d3 MC |
2384 | if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK) |
2385 | tg3_pwrsrc_switch_to_vaux(tp); | |
2386 | else | |
2387 | tg3_pwrsrc_die_with_vmain(tp); | |
2388 | ||
2389 | done: | |
6f5c8f83 | 2390 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); |
520b2756 MC |
2391 | } |
2392 | ||
cd0d7228 | 2393 | static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol) |
1da177e4 | 2394 | { |
683644b7 | 2395 | bool need_vaux = false; |
1da177e4 | 2396 | |
334355aa | 2397 | /* The GPIOs do something completely different on 57765. */ |
63c3a66f | 2398 | if (!tg3_flag(tp, IS_NIC) || |
334355aa | 2399 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
1da177e4 LT |
2400 | return; |
2401 | ||
3a1e19d3 MC |
2402 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2403 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
2404 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
cd0d7228 MC |
2405 | tg3_frob_aux_power_5717(tp, include_wol ? |
2406 | tg3_flag(tp, WOL_ENABLE) != 0 : 0); | |
3a1e19d3 MC |
2407 | return; |
2408 | } | |
2409 | ||
2410 | if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { | |
8c2dc7e1 MC |
2411 | struct net_device *dev_peer; |
2412 | ||
2413 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
683644b7 | 2414 | |
bc1c7567 | 2415 | /* remove_one() may have been run on the peer. */ |
683644b7 MC |
2416 | if (dev_peer) { |
2417 | struct tg3 *tp_peer = netdev_priv(dev_peer); | |
2418 | ||
63c3a66f | 2419 | if (tg3_flag(tp_peer, INIT_COMPLETE)) |
683644b7 MC |
2420 | return; |
2421 | ||
cd0d7228 | 2422 | if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) || |
63c3a66f | 2423 | tg3_flag(tp_peer, ENABLE_ASF)) |
683644b7 MC |
2424 | need_vaux = true; |
2425 | } | |
1da177e4 LT |
2426 | } |
2427 | ||
cd0d7228 MC |
2428 | if ((include_wol && tg3_flag(tp, WOL_ENABLE)) || |
2429 | tg3_flag(tp, ENABLE_ASF)) | |
683644b7 MC |
2430 | need_vaux = true; |
2431 | ||
520b2756 MC |
2432 | if (need_vaux) |
2433 | tg3_pwrsrc_switch_to_vaux(tp); | |
2434 | else | |
2435 | tg3_pwrsrc_die_with_vmain(tp); | |
1da177e4 LT |
2436 | } |
2437 | ||
e8f3f6ca MC |
2438 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) |
2439 | { | |
2440 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2441 | return 1; | |
79eb6904 | 2442 | else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { |
e8f3f6ca MC |
2443 | if (speed != SPEED_10) |
2444 | return 1; | |
2445 | } else if (speed == SPEED_10) | |
2446 | return 1; | |
2447 | ||
2448 | return 0; | |
2449 | } | |
2450 | ||
1da177e4 LT |
2451 | static int tg3_setup_phy(struct tg3 *, int); |
2452 | ||
2453 | #define RESET_KIND_SHUTDOWN 0 | |
2454 | #define RESET_KIND_INIT 1 | |
2455 | #define RESET_KIND_SUSPEND 2 | |
2456 | ||
2457 | static void tg3_write_sig_post_reset(struct tg3 *, int); | |
2458 | static int tg3_halt_cpu(struct tg3 *, u32); | |
2459 | ||
0a459aac | 2460 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
15c3b696 | 2461 | { |
ce057f01 MC |
2462 | u32 val; |
2463 | ||
f07e9af3 | 2464 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
5129724a MC |
2465 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
2466 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2467 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2468 | ||
2469 | sg_dig_ctrl |= | |
2470 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2471 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2472 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2473 | } | |
3f7045c1 | 2474 | return; |
5129724a | 2475 | } |
3f7045c1 | 2476 | |
60189ddf | 2477 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2478 | tg3_bmcr_reset(tp); |
2479 | val = tr32(GRC_MISC_CFG); | |
2480 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2481 | udelay(40); | |
2482 | return; | |
f07e9af3 | 2483 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
0e5f784c MC |
2484 | u32 phytest; |
2485 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2486 | u32 phy; | |
2487 | ||
2488 | tg3_writephy(tp, MII_ADVERTISE, 0); | |
2489 | tg3_writephy(tp, MII_BMCR, | |
2490 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2491 | ||
2492 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2493 | phytest | MII_TG3_FET_SHADOW_EN); | |
2494 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | |
2495 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | |
2496 | tg3_writephy(tp, | |
2497 | MII_TG3_FET_SHDW_AUXMODE4, | |
2498 | phy); | |
2499 | } | |
2500 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2501 | } | |
2502 | return; | |
0a459aac | 2503 | } else if (do_low_power) { |
715116a1 MC |
2504 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2505 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
0a459aac | 2506 | |
b4bd2929 MC |
2507 | val = MII_TG3_AUXCTL_PCTL_100TX_LPWR | |
2508 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2509 | MII_TG3_AUXCTL_PCTL_VREG_11V; | |
2510 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); | |
715116a1 | 2511 | } |
3f7045c1 | 2512 | |
15c3b696 MC |
2513 | /* The PHY should not be powered down on some chips because |
2514 | * of bugs. | |
2515 | */ | |
2516 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2517 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2518 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
f07e9af3 | 2519 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
15c3b696 | 2520 | return; |
ce057f01 | 2521 | |
bcb37f6c MC |
2522 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2523 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2524 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2525 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2526 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2527 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2528 | } | |
2529 | ||
15c3b696 MC |
2530 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); |
2531 | } | |
2532 | ||
ffbcfed4 MC |
2533 | /* tp->lock is held. */ |
2534 | static int tg3_nvram_lock(struct tg3 *tp) | |
2535 | { | |
63c3a66f | 2536 | if (tg3_flag(tp, NVRAM)) { |
ffbcfed4 MC |
2537 | int i; |
2538 | ||
2539 | if (tp->nvram_lock_cnt == 0) { | |
2540 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2541 | for (i = 0; i < 8000; i++) { | |
2542 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2543 | break; | |
2544 | udelay(20); | |
2545 | } | |
2546 | if (i == 8000) { | |
2547 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2548 | return -ENODEV; | |
2549 | } | |
2550 | } | |
2551 | tp->nvram_lock_cnt++; | |
2552 | } | |
2553 | return 0; | |
2554 | } | |
2555 | ||
2556 | /* tp->lock is held. */ | |
2557 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2558 | { | |
63c3a66f | 2559 | if (tg3_flag(tp, NVRAM)) { |
ffbcfed4 MC |
2560 | if (tp->nvram_lock_cnt > 0) |
2561 | tp->nvram_lock_cnt--; | |
2562 | if (tp->nvram_lock_cnt == 0) | |
2563 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2564 | } | |
2565 | } | |
2566 | ||
2567 | /* tp->lock is held. */ | |
2568 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2569 | { | |
63c3a66f | 2570 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2571 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2572 | ||
2573 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
2574 | } | |
2575 | } | |
2576 | ||
2577 | /* tp->lock is held. */ | |
2578 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
2579 | { | |
63c3a66f | 2580 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2581 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2582 | ||
2583 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
2584 | } | |
2585 | } | |
2586 | ||
2587 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
2588 | u32 offset, u32 *val) | |
2589 | { | |
2590 | u32 tmp; | |
2591 | int i; | |
2592 | ||
2593 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
2594 | return -EINVAL; | |
2595 | ||
2596 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
2597 | EEPROM_ADDR_DEVID_MASK | | |
2598 | EEPROM_ADDR_READ); | |
2599 | tw32(GRC_EEPROM_ADDR, | |
2600 | tmp | | |
2601 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
2602 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
2603 | EEPROM_ADDR_ADDR_MASK) | | |
2604 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
2605 | ||
2606 | for (i = 0; i < 1000; i++) { | |
2607 | tmp = tr32(GRC_EEPROM_ADDR); | |
2608 | ||
2609 | if (tmp & EEPROM_ADDR_COMPLETE) | |
2610 | break; | |
2611 | msleep(1); | |
2612 | } | |
2613 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
2614 | return -EBUSY; | |
2615 | ||
62cedd11 MC |
2616 | tmp = tr32(GRC_EEPROM_DATA); |
2617 | ||
2618 | /* | |
2619 | * The data will always be opposite the native endian | |
2620 | * format. Perform a blind byteswap to compensate. | |
2621 | */ | |
2622 | *val = swab32(tmp); | |
2623 | ||
ffbcfed4 MC |
2624 | return 0; |
2625 | } | |
2626 | ||
2627 | #define NVRAM_CMD_TIMEOUT 10000 | |
2628 | ||
2629 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
2630 | { | |
2631 | int i; | |
2632 | ||
2633 | tw32(NVRAM_CMD, nvram_cmd); | |
2634 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
2635 | udelay(10); | |
2636 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
2637 | udelay(10); | |
2638 | break; | |
2639 | } | |
2640 | } | |
2641 | ||
2642 | if (i == NVRAM_CMD_TIMEOUT) | |
2643 | return -EBUSY; | |
2644 | ||
2645 | return 0; | |
2646 | } | |
2647 | ||
2648 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
2649 | { | |
63c3a66f JP |
2650 | if (tg3_flag(tp, NVRAM) && |
2651 | tg3_flag(tp, NVRAM_BUFFERED) && | |
2652 | tg3_flag(tp, FLASH) && | |
2653 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
ffbcfed4 MC |
2654 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
2655 | ||
2656 | addr = ((addr / tp->nvram_pagesize) << | |
2657 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
2658 | (addr % tp->nvram_pagesize); | |
2659 | ||
2660 | return addr; | |
2661 | } | |
2662 | ||
2663 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
2664 | { | |
63c3a66f JP |
2665 | if (tg3_flag(tp, NVRAM) && |
2666 | tg3_flag(tp, NVRAM_BUFFERED) && | |
2667 | tg3_flag(tp, FLASH) && | |
2668 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
ffbcfed4 MC |
2669 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
2670 | ||
2671 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
2672 | tp->nvram_pagesize) + | |
2673 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
2674 | ||
2675 | return addr; | |
2676 | } | |
2677 | ||
e4f34110 MC |
2678 | /* NOTE: Data read in from NVRAM is byteswapped according to |
2679 | * the byteswapping settings for all other register accesses. | |
2680 | * tg3 devices are BE devices, so on a BE machine, the data | |
2681 | * returned will be exactly as it is seen in NVRAM. On a LE | |
2682 | * machine, the 32-bit value will be byteswapped. | |
2683 | */ | |
ffbcfed4 MC |
2684 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
2685 | { | |
2686 | int ret; | |
2687 | ||
63c3a66f | 2688 | if (!tg3_flag(tp, NVRAM)) |
ffbcfed4 MC |
2689 | return tg3_nvram_read_using_eeprom(tp, offset, val); |
2690 | ||
2691 | offset = tg3_nvram_phys_addr(tp, offset); | |
2692 | ||
2693 | if (offset > NVRAM_ADDR_MSK) | |
2694 | return -EINVAL; | |
2695 | ||
2696 | ret = tg3_nvram_lock(tp); | |
2697 | if (ret) | |
2698 | return ret; | |
2699 | ||
2700 | tg3_enable_nvram_access(tp); | |
2701 | ||
2702 | tw32(NVRAM_ADDR, offset); | |
2703 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
2704 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
2705 | ||
2706 | if (ret == 0) | |
e4f34110 | 2707 | *val = tr32(NVRAM_RDDATA); |
ffbcfed4 MC |
2708 | |
2709 | tg3_disable_nvram_access(tp); | |
2710 | ||
2711 | tg3_nvram_unlock(tp); | |
2712 | ||
2713 | return ret; | |
2714 | } | |
2715 | ||
a9dc529d MC |
2716 | /* Ensures NVRAM data is in bytestream format. */ |
2717 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
ffbcfed4 MC |
2718 | { |
2719 | u32 v; | |
a9dc529d | 2720 | int res = tg3_nvram_read(tp, offset, &v); |
ffbcfed4 | 2721 | if (!res) |
a9dc529d | 2722 | *val = cpu_to_be32(v); |
ffbcfed4 MC |
2723 | return res; |
2724 | } | |
2725 | ||
3f007891 MC |
2726 | /* tp->lock is held. */ |
2727 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
2728 | { | |
2729 | u32 addr_high, addr_low; | |
2730 | int i; | |
2731 | ||
2732 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
2733 | tp->dev->dev_addr[1]); | |
2734 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
2735 | (tp->dev->dev_addr[3] << 16) | | |
2736 | (tp->dev->dev_addr[4] << 8) | | |
2737 | (tp->dev->dev_addr[5] << 0)); | |
2738 | for (i = 0; i < 4; i++) { | |
2739 | if (i == 1 && skip_mac_1) | |
2740 | continue; | |
2741 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
2742 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
2743 | } | |
2744 | ||
2745 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
2746 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2747 | for (i = 0; i < 12; i++) { | |
2748 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
2749 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
2750 | } | |
2751 | } | |
2752 | ||
2753 | addr_high = (tp->dev->dev_addr[0] + | |
2754 | tp->dev->dev_addr[1] + | |
2755 | tp->dev->dev_addr[2] + | |
2756 | tp->dev->dev_addr[3] + | |
2757 | tp->dev->dev_addr[4] + | |
2758 | tp->dev->dev_addr[5]) & | |
2759 | TX_BACKOFF_SEED_MASK; | |
2760 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
2761 | } | |
2762 | ||
c866b7ea | 2763 | static void tg3_enable_register_access(struct tg3 *tp) |
1da177e4 | 2764 | { |
c866b7ea RW |
2765 | /* |
2766 | * Make sure register accesses (indirect or otherwise) will function | |
2767 | * correctly. | |
1da177e4 LT |
2768 | */ |
2769 | pci_write_config_dword(tp->pdev, | |
c866b7ea RW |
2770 | TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); |
2771 | } | |
1da177e4 | 2772 | |
c866b7ea RW |
2773 | static int tg3_power_up(struct tg3 *tp) |
2774 | { | |
bed9829f | 2775 | int err; |
8c6bda1a | 2776 | |
bed9829f | 2777 | tg3_enable_register_access(tp); |
1da177e4 | 2778 | |
bed9829f MC |
2779 | err = pci_set_power_state(tp->pdev, PCI_D0); |
2780 | if (!err) { | |
2781 | /* Switch out of Vaux if it is a NIC */ | |
2782 | tg3_pwrsrc_switch_to_vmain(tp); | |
2783 | } else { | |
2784 | netdev_err(tp->dev, "Transition to D0 failed\n"); | |
2785 | } | |
1da177e4 | 2786 | |
bed9829f | 2787 | return err; |
c866b7ea | 2788 | } |
1da177e4 | 2789 | |
c866b7ea RW |
2790 | static int tg3_power_down_prepare(struct tg3 *tp) |
2791 | { | |
2792 | u32 misc_host_ctrl; | |
2793 | bool device_should_wake, do_low_power; | |
2794 | ||
2795 | tg3_enable_register_access(tp); | |
5e7dfd0f MC |
2796 | |
2797 | /* Restore the CLKREQ setting. */ | |
63c3a66f | 2798 | if (tg3_flag(tp, CLKREQ_BUG)) { |
5e7dfd0f MC |
2799 | u16 lnkctl; |
2800 | ||
2801 | pci_read_config_word(tp->pdev, | |
708ebb3a | 2802 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
2803 | &lnkctl); |
2804 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
2805 | pci_write_config_word(tp->pdev, | |
708ebb3a | 2806 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
2807 | lnkctl); |
2808 | } | |
2809 | ||
1da177e4 LT |
2810 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
2811 | tw32(TG3PCI_MISC_HOST_CTRL, | |
2812 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
2813 | ||
c866b7ea | 2814 | device_should_wake = device_may_wakeup(&tp->pdev->dev) && |
63c3a66f | 2815 | tg3_flag(tp, WOL_ENABLE); |
05ac4cb7 | 2816 | |
63c3a66f | 2817 | if (tg3_flag(tp, USE_PHYLIB)) { |
0a459aac | 2818 | do_low_power = false; |
f07e9af3 | 2819 | if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && |
80096068 | 2820 | !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
b02fd9e3 | 2821 | struct phy_device *phydev; |
0a459aac | 2822 | u32 phyid, advertising; |
b02fd9e3 | 2823 | |
3f0e3ad7 | 2824 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 2825 | |
80096068 | 2826 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
b02fd9e3 MC |
2827 | |
2828 | tp->link_config.orig_speed = phydev->speed; | |
2829 | tp->link_config.orig_duplex = phydev->duplex; | |
2830 | tp->link_config.orig_autoneg = phydev->autoneg; | |
2831 | tp->link_config.orig_advertising = phydev->advertising; | |
2832 | ||
2833 | advertising = ADVERTISED_TP | | |
2834 | ADVERTISED_Pause | | |
2835 | ADVERTISED_Autoneg | | |
2836 | ADVERTISED_10baseT_Half; | |
2837 | ||
63c3a66f JP |
2838 | if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { |
2839 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
b02fd9e3 MC |
2840 | advertising |= |
2841 | ADVERTISED_100baseT_Half | | |
2842 | ADVERTISED_100baseT_Full | | |
2843 | ADVERTISED_10baseT_Full; | |
2844 | else | |
2845 | advertising |= ADVERTISED_10baseT_Full; | |
2846 | } | |
2847 | ||
2848 | phydev->advertising = advertising; | |
2849 | ||
2850 | phy_start_aneg(phydev); | |
0a459aac MC |
2851 | |
2852 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
6a443a0f MC |
2853 | if (phyid != PHY_ID_BCMAC131) { |
2854 | phyid &= PHY_BCM_OUI_MASK; | |
2855 | if (phyid == PHY_BCM_OUI_1 || | |
2856 | phyid == PHY_BCM_OUI_2 || | |
2857 | phyid == PHY_BCM_OUI_3) | |
0a459aac MC |
2858 | do_low_power = true; |
2859 | } | |
b02fd9e3 | 2860 | } |
dd477003 | 2861 | } else { |
2023276e | 2862 | do_low_power = true; |
0a459aac | 2863 | |
80096068 MC |
2864 | if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
2865 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
2866 | tp->link_config.orig_speed = tp->link_config.speed; |
2867 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
2868 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
2869 | } | |
1da177e4 | 2870 | |
f07e9af3 | 2871 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
dd477003 MC |
2872 | tp->link_config.speed = SPEED_10; |
2873 | tp->link_config.duplex = DUPLEX_HALF; | |
2874 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
2875 | tg3_setup_phy(tp, 0); | |
2876 | } | |
1da177e4 LT |
2877 | } |
2878 | ||
b5d3772c MC |
2879 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
2880 | u32 val; | |
2881 | ||
2882 | val = tr32(GRC_VCPU_EXT_CTRL); | |
2883 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
63c3a66f | 2884 | } else if (!tg3_flag(tp, ENABLE_ASF)) { |
6921d201 MC |
2885 | int i; |
2886 | u32 val; | |
2887 | ||
2888 | for (i = 0; i < 200; i++) { | |
2889 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
2890 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
2891 | break; | |
2892 | msleep(1); | |
2893 | } | |
2894 | } | |
63c3a66f | 2895 | if (tg3_flag(tp, WOL_CAP)) |
a85feb8c GZ |
2896 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | |
2897 | WOL_DRV_STATE_SHUTDOWN | | |
2898 | WOL_DRV_WOL | | |
2899 | WOL_SET_MAGIC_PKT); | |
6921d201 | 2900 | |
05ac4cb7 | 2901 | if (device_should_wake) { |
1da177e4 LT |
2902 | u32 mac_mode; |
2903 | ||
f07e9af3 | 2904 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
b4bd2929 MC |
2905 | if (do_low_power && |
2906 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
2907 | tg3_phy_auxctl_write(tp, | |
2908 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL, | |
2909 | MII_TG3_AUXCTL_PCTL_WOL_EN | | |
2910 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
2911 | MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC); | |
dd477003 MC |
2912 | udelay(40); |
2913 | } | |
1da177e4 | 2914 | |
f07e9af3 | 2915 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
3f7045c1 MC |
2916 | mac_mode = MAC_MODE_PORT_MODE_GMII; |
2917 | else | |
2918 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
1da177e4 | 2919 | |
e8f3f6ca MC |
2920 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
2921 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2922 | ASIC_REV_5700) { | |
63c3a66f | 2923 | u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? |
e8f3f6ca MC |
2924 | SPEED_100 : SPEED_10; |
2925 | if (tg3_5700_link_polarity(tp, speed)) | |
2926 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
2927 | else | |
2928 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
2929 | } | |
1da177e4 LT |
2930 | } else { |
2931 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
2932 | } | |
2933 | ||
63c3a66f | 2934 | if (!tg3_flag(tp, 5750_PLUS)) |
1da177e4 LT |
2935 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
2936 | ||
05ac4cb7 | 2937 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; |
63c3a66f JP |
2938 | if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && |
2939 | (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE))) | |
05ac4cb7 | 2940 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; |
1da177e4 | 2941 | |
63c3a66f | 2942 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b MC |
2943 | mac_mode |= MAC_MODE_APE_TX_EN | |
2944 | MAC_MODE_APE_RX_EN | | |
2945 | MAC_MODE_TDE_ENABLE; | |
3bda1258 | 2946 | |
1da177e4 LT |
2947 | tw32_f(MAC_MODE, mac_mode); |
2948 | udelay(100); | |
2949 | ||
2950 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
2951 | udelay(10); | |
2952 | } | |
2953 | ||
63c3a66f | 2954 | if (!tg3_flag(tp, WOL_SPEED_100MB) && |
1da177e4 LT |
2955 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
2956 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
2957 | u32 base_val; | |
2958 | ||
2959 | base_val = tp->pci_clock_ctrl; | |
2960 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
2961 | CLOCK_CTRL_TXCLK_DISABLE); | |
2962 | ||
b401e9e2 MC |
2963 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | |
2964 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
63c3a66f JP |
2965 | } else if (tg3_flag(tp, 5780_CLASS) || |
2966 | tg3_flag(tp, CPMU_PRESENT) || | |
6ff6f81d | 2967 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
4cf78e4f | 2968 | /* do nothing */ |
63c3a66f | 2969 | } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { |
1da177e4 LT |
2970 | u32 newbits1, newbits2; |
2971 | ||
2972 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2973 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2974 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2975 | CLOCK_CTRL_TXCLK_DISABLE | | |
2976 | CLOCK_CTRL_ALTCLK); | |
2977 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
63c3a66f | 2978 | } else if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
2979 | newbits1 = CLOCK_CTRL_625_CORE; |
2980 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
2981 | } else { | |
2982 | newbits1 = CLOCK_CTRL_ALTCLK; | |
2983 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2984 | } | |
2985 | ||
b401e9e2 MC |
2986 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, |
2987 | 40); | |
1da177e4 | 2988 | |
b401e9e2 MC |
2989 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, |
2990 | 40); | |
1da177e4 | 2991 | |
63c3a66f | 2992 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
2993 | u32 newbits3; |
2994 | ||
2995 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2996 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2997 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2998 | CLOCK_CTRL_TXCLK_DISABLE | | |
2999 | CLOCK_CTRL_44MHZ_CORE); | |
3000 | } else { | |
3001 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
3002 | } | |
3003 | ||
b401e9e2 MC |
3004 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
3005 | tp->pci_clock_ctrl | newbits3, 40); | |
1da177e4 LT |
3006 | } |
3007 | } | |
3008 | ||
63c3a66f | 3009 | if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) |
0a459aac | 3010 | tg3_power_down_phy(tp, do_low_power); |
6921d201 | 3011 | |
cd0d7228 | 3012 | tg3_frob_aux_power(tp, true); |
1da177e4 LT |
3013 | |
3014 | /* Workaround for unstable PLL clock */ | |
3015 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
3016 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
3017 | u32 val = tr32(0x7d00); | |
3018 | ||
3019 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
3020 | tw32(0x7d00, val); | |
63c3a66f | 3021 | if (!tg3_flag(tp, ENABLE_ASF)) { |
ec41c7df MC |
3022 | int err; |
3023 | ||
3024 | err = tg3_nvram_lock(tp); | |
1da177e4 | 3025 | tg3_halt_cpu(tp, RX_CPU_BASE); |
ec41c7df MC |
3026 | if (!err) |
3027 | tg3_nvram_unlock(tp); | |
6921d201 | 3028 | } |
1da177e4 LT |
3029 | } |
3030 | ||
bbadf503 MC |
3031 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); |
3032 | ||
c866b7ea RW |
3033 | return 0; |
3034 | } | |
12dac075 | 3035 | |
c866b7ea RW |
3036 | static void tg3_power_down(struct tg3 *tp) |
3037 | { | |
3038 | tg3_power_down_prepare(tp); | |
1da177e4 | 3039 | |
63c3a66f | 3040 | pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); |
c866b7ea | 3041 | pci_set_power_state(tp->pdev, PCI_D3hot); |
1da177e4 LT |
3042 | } |
3043 | ||
1da177e4 LT |
3044 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) |
3045 | { | |
3046 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
3047 | case MII_TG3_AUX_STAT_10HALF: | |
3048 | *speed = SPEED_10; | |
3049 | *duplex = DUPLEX_HALF; | |
3050 | break; | |
3051 | ||
3052 | case MII_TG3_AUX_STAT_10FULL: | |
3053 | *speed = SPEED_10; | |
3054 | *duplex = DUPLEX_FULL; | |
3055 | break; | |
3056 | ||
3057 | case MII_TG3_AUX_STAT_100HALF: | |
3058 | *speed = SPEED_100; | |
3059 | *duplex = DUPLEX_HALF; | |
3060 | break; | |
3061 | ||
3062 | case MII_TG3_AUX_STAT_100FULL: | |
3063 | *speed = SPEED_100; | |
3064 | *duplex = DUPLEX_FULL; | |
3065 | break; | |
3066 | ||
3067 | case MII_TG3_AUX_STAT_1000HALF: | |
3068 | *speed = SPEED_1000; | |
3069 | *duplex = DUPLEX_HALF; | |
3070 | break; | |
3071 | ||
3072 | case MII_TG3_AUX_STAT_1000FULL: | |
3073 | *speed = SPEED_1000; | |
3074 | *duplex = DUPLEX_FULL; | |
3075 | break; | |
3076 | ||
3077 | default: | |
f07e9af3 | 3078 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
715116a1 MC |
3079 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
3080 | SPEED_10; | |
3081 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
3082 | DUPLEX_HALF; | |
3083 | break; | |
3084 | } | |
1da177e4 LT |
3085 | *speed = SPEED_INVALID; |
3086 | *duplex = DUPLEX_INVALID; | |
3087 | break; | |
855e1111 | 3088 | } |
1da177e4 LT |
3089 | } |
3090 | ||
42b64a45 | 3091 | static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) |
1da177e4 | 3092 | { |
42b64a45 MC |
3093 | int err = 0; |
3094 | u32 val, new_adv; | |
1da177e4 | 3095 | |
42b64a45 MC |
3096 | new_adv = ADVERTISE_CSMA; |
3097 | if (advertise & ADVERTISED_10baseT_Half) | |
3098 | new_adv |= ADVERTISE_10HALF; | |
3099 | if (advertise & ADVERTISED_10baseT_Full) | |
3100 | new_adv |= ADVERTISE_10FULL; | |
3101 | if (advertise & ADVERTISED_100baseT_Half) | |
3102 | new_adv |= ADVERTISE_100HALF; | |
3103 | if (advertise & ADVERTISED_100baseT_Full) | |
3104 | new_adv |= ADVERTISE_100FULL; | |
1da177e4 | 3105 | |
42b64a45 | 3106 | new_adv |= tg3_advert_flowctrl_1000T(flowctrl); |
1da177e4 | 3107 | |
42b64a45 MC |
3108 | err = tg3_writephy(tp, MII_ADVERTISE, new_adv); |
3109 | if (err) | |
3110 | goto done; | |
ba4d07a8 | 3111 | |
42b64a45 MC |
3112 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
3113 | goto done; | |
1da177e4 | 3114 | |
42b64a45 MC |
3115 | new_adv = 0; |
3116 | if (advertise & ADVERTISED_1000baseT_Half) | |
221c5637 | 3117 | new_adv |= ADVERTISE_1000HALF; |
42b64a45 | 3118 | if (advertise & ADVERTISED_1000baseT_Full) |
221c5637 | 3119 | new_adv |= ADVERTISE_1000FULL; |
ba4d07a8 | 3120 | |
42b64a45 MC |
3121 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || |
3122 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
221c5637 | 3123 | new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; |
ba4d07a8 | 3124 | |
221c5637 | 3125 | err = tg3_writephy(tp, MII_CTRL1000, new_adv); |
42b64a45 MC |
3126 | if (err) |
3127 | goto done; | |
1da177e4 | 3128 | |
42b64a45 MC |
3129 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) |
3130 | goto done; | |
52b02d04 | 3131 | |
42b64a45 MC |
3132 | tw32(TG3_CPMU_EEE_MODE, |
3133 | tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
52b02d04 | 3134 | |
42b64a45 MC |
3135 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
3136 | if (!err) { | |
3137 | u32 err2; | |
52b02d04 | 3138 | |
b715ce94 MC |
3139 | val = 0; |
3140 | /* Advertise 100-BaseTX EEE ability */ | |
3141 | if (advertise & ADVERTISED_100baseT_Full) | |
3142 | val |= MDIO_AN_EEE_ADV_100TX; | |
3143 | /* Advertise 1000-BaseT EEE ability */ | |
3144 | if (advertise & ADVERTISED_1000baseT_Full) | |
3145 | val |= MDIO_AN_EEE_ADV_1000T; | |
3146 | err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
3147 | if (err) | |
3148 | val = 0; | |
3149 | ||
21a00ab2 MC |
3150 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { |
3151 | case ASIC_REV_5717: | |
3152 | case ASIC_REV_57765: | |
21a00ab2 | 3153 | case ASIC_REV_5719: |
b715ce94 MC |
3154 | /* If we advertised any eee advertisements above... */ |
3155 | if (val) | |
3156 | val = MII_TG3_DSP_TAP26_ALNOKO | | |
3157 | MII_TG3_DSP_TAP26_RMRXSTO | | |
3158 | MII_TG3_DSP_TAP26_OPCSINPT; | |
21a00ab2 | 3159 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); |
be671947 MC |
3160 | /* Fall through */ |
3161 | case ASIC_REV_5720: | |
3162 | if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) | |
3163 | tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | | |
3164 | MII_TG3_DSP_CH34TP2_HIBW01); | |
21a00ab2 | 3165 | } |
52b02d04 | 3166 | |
42b64a45 MC |
3167 | err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
3168 | if (!err) | |
3169 | err = err2; | |
3170 | } | |
3171 | ||
3172 | done: | |
3173 | return err; | |
3174 | } | |
3175 | ||
3176 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
3177 | { | |
3178 | u32 new_adv; | |
3179 | int i; | |
3180 | ||
3181 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { | |
3182 | new_adv = ADVERTISED_10baseT_Half | | |
3183 | ADVERTISED_10baseT_Full; | |
3184 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
3185 | new_adv |= ADVERTISED_100baseT_Half | | |
3186 | ADVERTISED_100baseT_Full; | |
3187 | ||
3188 | tg3_phy_autoneg_cfg(tp, new_adv, | |
3189 | FLOW_CTRL_TX | FLOW_CTRL_RX); | |
3190 | } else if (tp->link_config.speed == SPEED_INVALID) { | |
3191 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
3192 | tp->link_config.advertising &= | |
3193 | ~(ADVERTISED_1000baseT_Half | | |
3194 | ADVERTISED_1000baseT_Full); | |
3195 | ||
3196 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, | |
3197 | tp->link_config.flowctrl); | |
3198 | } else { | |
3199 | /* Asking for a specific link mode. */ | |
3200 | if (tp->link_config.speed == SPEED_1000) { | |
3201 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3202 | new_adv = ADVERTISED_1000baseT_Full; | |
3203 | else | |
3204 | new_adv = ADVERTISED_1000baseT_Half; | |
3205 | } else if (tp->link_config.speed == SPEED_100) { | |
3206 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3207 | new_adv = ADVERTISED_100baseT_Full; | |
3208 | else | |
3209 | new_adv = ADVERTISED_100baseT_Half; | |
3210 | } else { | |
3211 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3212 | new_adv = ADVERTISED_10baseT_Full; | |
3213 | else | |
3214 | new_adv = ADVERTISED_10baseT_Half; | |
52b02d04 | 3215 | } |
52b02d04 | 3216 | |
42b64a45 MC |
3217 | tg3_phy_autoneg_cfg(tp, new_adv, |
3218 | tp->link_config.flowctrl); | |
52b02d04 MC |
3219 | } |
3220 | ||
1da177e4 LT |
3221 | if (tp->link_config.autoneg == AUTONEG_DISABLE && |
3222 | tp->link_config.speed != SPEED_INVALID) { | |
3223 | u32 bmcr, orig_bmcr; | |
3224 | ||
3225 | tp->link_config.active_speed = tp->link_config.speed; | |
3226 | tp->link_config.active_duplex = tp->link_config.duplex; | |
3227 | ||
3228 | bmcr = 0; | |
3229 | switch (tp->link_config.speed) { | |
3230 | default: | |
3231 | case SPEED_10: | |
3232 | break; | |
3233 | ||
3234 | case SPEED_100: | |
3235 | bmcr |= BMCR_SPEED100; | |
3236 | break; | |
3237 | ||
3238 | case SPEED_1000: | |
221c5637 | 3239 | bmcr |= BMCR_SPEED1000; |
1da177e4 | 3240 | break; |
855e1111 | 3241 | } |
1da177e4 LT |
3242 | |
3243 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3244 | bmcr |= BMCR_FULLDPLX; | |
3245 | ||
3246 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
3247 | (bmcr != orig_bmcr)) { | |
3248 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
3249 | for (i = 0; i < 1500; i++) { | |
3250 | u32 tmp; | |
3251 | ||
3252 | udelay(10); | |
3253 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
3254 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
3255 | continue; | |
3256 | if (!(tmp & BMSR_LSTATUS)) { | |
3257 | udelay(40); | |
3258 | break; | |
3259 | } | |
3260 | } | |
3261 | tg3_writephy(tp, MII_BMCR, bmcr); | |
3262 | udelay(40); | |
3263 | } | |
3264 | } else { | |
3265 | tg3_writephy(tp, MII_BMCR, | |
3266 | BMCR_ANENABLE | BMCR_ANRESTART); | |
3267 | } | |
3268 | } | |
3269 | ||
3270 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
3271 | { | |
3272 | int err; | |
3273 | ||
3274 | /* Turn off tap power management. */ | |
3275 | /* Set Extended packet length bit */ | |
b4bd2929 | 3276 | err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
1da177e4 | 3277 | |
6ee7c0a0 MC |
3278 | err |= tg3_phydsp_write(tp, 0x0012, 0x1804); |
3279 | err |= tg3_phydsp_write(tp, 0x0013, 0x1204); | |
3280 | err |= tg3_phydsp_write(tp, 0x8006, 0x0132); | |
3281 | err |= tg3_phydsp_write(tp, 0x8006, 0x0232); | |
3282 | err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); | |
1da177e4 LT |
3283 | |
3284 | udelay(40); | |
3285 | ||
3286 | return err; | |
3287 | } | |
3288 | ||
3600d918 | 3289 | static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask) |
1da177e4 | 3290 | { |
3600d918 MC |
3291 | u32 adv_reg, all_mask = 0; |
3292 | ||
3293 | if (mask & ADVERTISED_10baseT_Half) | |
3294 | all_mask |= ADVERTISE_10HALF; | |
3295 | if (mask & ADVERTISED_10baseT_Full) | |
3296 | all_mask |= ADVERTISE_10FULL; | |
3297 | if (mask & ADVERTISED_100baseT_Half) | |
3298 | all_mask |= ADVERTISE_100HALF; | |
3299 | if (mask & ADVERTISED_100baseT_Full) | |
3300 | all_mask |= ADVERTISE_100FULL; | |
1da177e4 LT |
3301 | |
3302 | if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg)) | |
3303 | return 0; | |
3304 | ||
1da177e4 LT |
3305 | if ((adv_reg & all_mask) != all_mask) |
3306 | return 0; | |
f07e9af3 | 3307 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
1da177e4 LT |
3308 | u32 tg3_ctrl; |
3309 | ||
3600d918 MC |
3310 | all_mask = 0; |
3311 | if (mask & ADVERTISED_1000baseT_Half) | |
3312 | all_mask |= ADVERTISE_1000HALF; | |
3313 | if (mask & ADVERTISED_1000baseT_Full) | |
3314 | all_mask |= ADVERTISE_1000FULL; | |
3315 | ||
221c5637 | 3316 | if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) |
1da177e4 LT |
3317 | return 0; |
3318 | ||
1da177e4 LT |
3319 | if ((tg3_ctrl & all_mask) != all_mask) |
3320 | return 0; | |
3321 | } | |
3322 | return 1; | |
3323 | } | |
3324 | ||
ef167e27 MC |
3325 | static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv) |
3326 | { | |
3327 | u32 curadv, reqadv; | |
3328 | ||
3329 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) | |
3330 | return 1; | |
3331 | ||
3332 | curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
3333 | reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
3334 | ||
3335 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
3336 | if (curadv != reqadv) | |
3337 | return 0; | |
3338 | ||
63c3a66f | 3339 | if (tg3_flag(tp, PAUSE_AUTONEG)) |
ef167e27 MC |
3340 | tg3_readphy(tp, MII_LPA, rmtadv); |
3341 | } else { | |
3342 | /* Reprogram the advertisement register, even if it | |
3343 | * does not affect the current link. If the link | |
3344 | * gets renegotiated in the future, we can save an | |
3345 | * additional renegotiation cycle by advertising | |
3346 | * it correctly in the first place. | |
3347 | */ | |
3348 | if (curadv != reqadv) { | |
3349 | *lcladv &= ~(ADVERTISE_PAUSE_CAP | | |
3350 | ADVERTISE_PAUSE_ASYM); | |
3351 | tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv); | |
3352 | } | |
3353 | } | |
3354 | ||
3355 | return 1; | |
3356 | } | |
3357 | ||
1da177e4 LT |
3358 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) |
3359 | { | |
3360 | int current_link_up; | |
f833c4c1 | 3361 | u32 bmsr, val; |
ef167e27 | 3362 | u32 lcl_adv, rmt_adv; |
1da177e4 LT |
3363 | u16 current_speed; |
3364 | u8 current_duplex; | |
3365 | int i, err; | |
3366 | ||
3367 | tw32(MAC_EVENT, 0); | |
3368 | ||
3369 | tw32_f(MAC_STATUS, | |
3370 | (MAC_STATUS_SYNC_CHANGED | | |
3371 | MAC_STATUS_CFG_CHANGED | | |
3372 | MAC_STATUS_MI_COMPLETION | | |
3373 | MAC_STATUS_LNKSTATE_CHANGED)); | |
3374 | udelay(40); | |
3375 | ||
8ef21428 MC |
3376 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
3377 | tw32_f(MAC_MI_MODE, | |
3378 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
3379 | udelay(80); | |
3380 | } | |
1da177e4 | 3381 | |
b4bd2929 | 3382 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); |
1da177e4 LT |
3383 | |
3384 | /* Some third-party PHYs need to be reset on link going | |
3385 | * down. | |
3386 | */ | |
3387 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3388 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
3389 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
3390 | netif_carrier_ok(tp->dev)) { | |
3391 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3392 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3393 | !(bmsr & BMSR_LSTATUS)) | |
3394 | force_reset = 1; | |
3395 | } | |
3396 | if (force_reset) | |
3397 | tg3_phy_reset(tp); | |
3398 | ||
79eb6904 | 3399 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
3400 | tg3_readphy(tp, MII_BMSR, &bmsr); |
3401 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
63c3a66f | 3402 | !tg3_flag(tp, INIT_COMPLETE)) |
1da177e4 LT |
3403 | bmsr = 0; |
3404 | ||
3405 | if (!(bmsr & BMSR_LSTATUS)) { | |
3406 | err = tg3_init_5401phy_dsp(tp); | |
3407 | if (err) | |
3408 | return err; | |
3409 | ||
3410 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3411 | for (i = 0; i < 1000; i++) { | |
3412 | udelay(10); | |
3413 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3414 | (bmsr & BMSR_LSTATUS)) { | |
3415 | udelay(40); | |
3416 | break; | |
3417 | } | |
3418 | } | |
3419 | ||
79eb6904 MC |
3420 | if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == |
3421 | TG3_PHY_REV_BCM5401_B0 && | |
1da177e4 LT |
3422 | !(bmsr & BMSR_LSTATUS) && |
3423 | tp->link_config.active_speed == SPEED_1000) { | |
3424 | err = tg3_phy_reset(tp); | |
3425 | if (!err) | |
3426 | err = tg3_init_5401phy_dsp(tp); | |
3427 | if (err) | |
3428 | return err; | |
3429 | } | |
3430 | } | |
3431 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
3432 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
3433 | /* 5701 {A0,B0} CRC bug workaround */ | |
3434 | tg3_writephy(tp, 0x15, 0x0a75); | |
f08aa1a8 MC |
3435 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); |
3436 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
3437 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); | |
1da177e4 LT |
3438 | } |
3439 | ||
3440 | /* Clear pending interrupts... */ | |
f833c4c1 MC |
3441 | tg3_readphy(tp, MII_TG3_ISTAT, &val); |
3442 | tg3_readphy(tp, MII_TG3_ISTAT, &val); | |
1da177e4 | 3443 | |
f07e9af3 | 3444 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) |
1da177e4 | 3445 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); |
f07e9af3 | 3446 | else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) |
1da177e4 LT |
3447 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
3448 | ||
3449 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3450 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3451 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
3452 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
3453 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
3454 | else | |
3455 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
3456 | } | |
3457 | ||
3458 | current_link_up = 0; | |
3459 | current_speed = SPEED_INVALID; | |
3460 | current_duplex = DUPLEX_INVALID; | |
3461 | ||
f07e9af3 | 3462 | if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { |
15ee95c3 MC |
3463 | err = tg3_phy_auxctl_read(tp, |
3464 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
3465 | &val); | |
3466 | if (!err && !(val & (1 << 10))) { | |
b4bd2929 MC |
3467 | tg3_phy_auxctl_write(tp, |
3468 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
3469 | val | (1 << 10)); | |
1da177e4 LT |
3470 | goto relink; |
3471 | } | |
3472 | } | |
3473 | ||
3474 | bmsr = 0; | |
3475 | for (i = 0; i < 100; i++) { | |
3476 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3477 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3478 | (bmsr & BMSR_LSTATUS)) | |
3479 | break; | |
3480 | udelay(40); | |
3481 | } | |
3482 | ||
3483 | if (bmsr & BMSR_LSTATUS) { | |
3484 | u32 aux_stat, bmcr; | |
3485 | ||
3486 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
3487 | for (i = 0; i < 2000; i++) { | |
3488 | udelay(10); | |
3489 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
3490 | aux_stat) | |
3491 | break; | |
3492 | } | |
3493 | ||
3494 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
3495 | ¤t_speed, | |
3496 | ¤t_duplex); | |
3497 | ||
3498 | bmcr = 0; | |
3499 | for (i = 0; i < 200; i++) { | |
3500 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
3501 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
3502 | continue; | |
3503 | if (bmcr && bmcr != 0x7fff) | |
3504 | break; | |
3505 | udelay(10); | |
3506 | } | |
3507 | ||
ef167e27 MC |
3508 | lcl_adv = 0; |
3509 | rmt_adv = 0; | |
1da177e4 | 3510 | |
ef167e27 MC |
3511 | tp->link_config.active_speed = current_speed; |
3512 | tp->link_config.active_duplex = current_duplex; | |
3513 | ||
3514 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3515 | if ((bmcr & BMCR_ANENABLE) && | |
3516 | tg3_copper_is_advertising_all(tp, | |
3517 | tp->link_config.advertising)) { | |
3518 | if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv, | |
3519 | &rmt_adv)) | |
3520 | current_link_up = 1; | |
1da177e4 LT |
3521 | } |
3522 | } else { | |
3523 | if (!(bmcr & BMCR_ANENABLE) && | |
3524 | tp->link_config.speed == current_speed && | |
ef167e27 MC |
3525 | tp->link_config.duplex == current_duplex && |
3526 | tp->link_config.flowctrl == | |
3527 | tp->link_config.active_flowctrl) { | |
1da177e4 | 3528 | current_link_up = 1; |
1da177e4 LT |
3529 | } |
3530 | } | |
3531 | ||
ef167e27 MC |
3532 | if (current_link_up == 1 && |
3533 | tp->link_config.active_duplex == DUPLEX_FULL) | |
3534 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1da177e4 LT |
3535 | } |
3536 | ||
1da177e4 | 3537 | relink: |
80096068 | 3538 | if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
1da177e4 LT |
3539 | tg3_phy_copper_begin(tp); |
3540 | ||
f833c4c1 | 3541 | tg3_readphy(tp, MII_BMSR, &bmsr); |
06c03c02 MB |
3542 | if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || |
3543 | (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
1da177e4 LT |
3544 | current_link_up = 1; |
3545 | } | |
3546 | ||
3547 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
3548 | if (current_link_up == 1) { | |
3549 | if (tp->link_config.active_speed == SPEED_100 || | |
3550 | tp->link_config.active_speed == SPEED_10) | |
3551 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3552 | else | |
3553 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
f07e9af3 | 3554 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) |
7f97a4bd MC |
3555 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
3556 | else | |
1da177e4 LT |
3557 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
3558 | ||
3559 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
3560 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
3561 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
3562 | ||
1da177e4 | 3563 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
e8f3f6ca MC |
3564 | if (current_link_up == 1 && |
3565 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
1da177e4 | 3566 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
e8f3f6ca MC |
3567 | else |
3568 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
3569 | } |
3570 | ||
3571 | /* ??? Without this setting Netgear GA302T PHY does not | |
3572 | * ??? send/receive packets... | |
3573 | */ | |
79eb6904 | 3574 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && |
1da177e4 LT |
3575 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { |
3576 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
3577 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
3578 | udelay(80); | |
3579 | } | |
3580 | ||
3581 | tw32_f(MAC_MODE, tp->mac_mode); | |
3582 | udelay(40); | |
3583 | ||
52b02d04 MC |
3584 | tg3_phy_eee_adjust(tp, current_link_up); |
3585 | ||
63c3a66f | 3586 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
1da177e4 LT |
3587 | /* Polled via timer. */ |
3588 | tw32_f(MAC_EVENT, 0); | |
3589 | } else { | |
3590 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3591 | } | |
3592 | udelay(40); | |
3593 | ||
3594 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
3595 | current_link_up == 1 && | |
3596 | tp->link_config.active_speed == SPEED_1000 && | |
63c3a66f | 3597 | (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { |
1da177e4 LT |
3598 | udelay(120); |
3599 | tw32_f(MAC_STATUS, | |
3600 | (MAC_STATUS_SYNC_CHANGED | | |
3601 | MAC_STATUS_CFG_CHANGED)); | |
3602 | udelay(40); | |
3603 | tg3_write_mem(tp, | |
3604 | NIC_SRAM_FIRMWARE_MBOX, | |
3605 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
3606 | } | |
3607 | ||
5e7dfd0f | 3608 | /* Prevent send BD corruption. */ |
63c3a66f | 3609 | if (tg3_flag(tp, CLKREQ_BUG)) { |
5e7dfd0f MC |
3610 | u16 oldlnkctl, newlnkctl; |
3611 | ||
3612 | pci_read_config_word(tp->pdev, | |
708ebb3a | 3613 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
3614 | &oldlnkctl); |
3615 | if (tp->link_config.active_speed == SPEED_100 || | |
3616 | tp->link_config.active_speed == SPEED_10) | |
3617 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
3618 | else | |
3619 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; | |
3620 | if (newlnkctl != oldlnkctl) | |
3621 | pci_write_config_word(tp->pdev, | |
708ebb3a | 3622 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
3623 | newlnkctl); |
3624 | } | |
3625 | ||
1da177e4 LT |
3626 | if (current_link_up != netif_carrier_ok(tp->dev)) { |
3627 | if (current_link_up) | |
3628 | netif_carrier_on(tp->dev); | |
3629 | else | |
3630 | netif_carrier_off(tp->dev); | |
3631 | tg3_link_report(tp); | |
3632 | } | |
3633 | ||
3634 | return 0; | |
3635 | } | |
3636 | ||
3637 | struct tg3_fiber_aneginfo { | |
3638 | int state; | |
3639 | #define ANEG_STATE_UNKNOWN 0 | |
3640 | #define ANEG_STATE_AN_ENABLE 1 | |
3641 | #define ANEG_STATE_RESTART_INIT 2 | |
3642 | #define ANEG_STATE_RESTART 3 | |
3643 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
3644 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
3645 | #define ANEG_STATE_ABILITY_DETECT 6 | |
3646 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
3647 | #define ANEG_STATE_ACK_DETECT 8 | |
3648 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
3649 | #define ANEG_STATE_COMPLETE_ACK 10 | |
3650 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
3651 | #define ANEG_STATE_IDLE_DETECT 12 | |
3652 | #define ANEG_STATE_LINK_OK 13 | |
3653 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
3654 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
3655 | ||
3656 | u32 flags; | |
3657 | #define MR_AN_ENABLE 0x00000001 | |
3658 | #define MR_RESTART_AN 0x00000002 | |
3659 | #define MR_AN_COMPLETE 0x00000004 | |
3660 | #define MR_PAGE_RX 0x00000008 | |
3661 | #define MR_NP_LOADED 0x00000010 | |
3662 | #define MR_TOGGLE_TX 0x00000020 | |
3663 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
3664 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
3665 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
3666 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
3667 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
3668 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
3669 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
3670 | #define MR_TOGGLE_RX 0x00002000 | |
3671 | #define MR_NP_RX 0x00004000 | |
3672 | ||
3673 | #define MR_LINK_OK 0x80000000 | |
3674 | ||
3675 | unsigned long link_time, cur_time; | |
3676 | ||
3677 | u32 ability_match_cfg; | |
3678 | int ability_match_count; | |
3679 | ||
3680 | char ability_match, idle_match, ack_match; | |
3681 | ||
3682 | u32 txconfig, rxconfig; | |
3683 | #define ANEG_CFG_NP 0x00000080 | |
3684 | #define ANEG_CFG_ACK 0x00000040 | |
3685 | #define ANEG_CFG_RF2 0x00000020 | |
3686 | #define ANEG_CFG_RF1 0x00000010 | |
3687 | #define ANEG_CFG_PS2 0x00000001 | |
3688 | #define ANEG_CFG_PS1 0x00008000 | |
3689 | #define ANEG_CFG_HD 0x00004000 | |
3690 | #define ANEG_CFG_FD 0x00002000 | |
3691 | #define ANEG_CFG_INVAL 0x00001f06 | |
3692 | ||
3693 | }; | |
3694 | #define ANEG_OK 0 | |
3695 | #define ANEG_DONE 1 | |
3696 | #define ANEG_TIMER_ENAB 2 | |
3697 | #define ANEG_FAILED -1 | |
3698 | ||
3699 | #define ANEG_STATE_SETTLE_TIME 10000 | |
3700 | ||
3701 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
3702 | struct tg3_fiber_aneginfo *ap) | |
3703 | { | |
5be73b47 | 3704 | u16 flowctrl; |
1da177e4 LT |
3705 | unsigned long delta; |
3706 | u32 rx_cfg_reg; | |
3707 | int ret; | |
3708 | ||
3709 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
3710 | ap->rxconfig = 0; | |
3711 | ap->link_time = 0; | |
3712 | ap->cur_time = 0; | |
3713 | ap->ability_match_cfg = 0; | |
3714 | ap->ability_match_count = 0; | |
3715 | ap->ability_match = 0; | |
3716 | ap->idle_match = 0; | |
3717 | ap->ack_match = 0; | |
3718 | } | |
3719 | ap->cur_time++; | |
3720 | ||
3721 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
3722 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
3723 | ||
3724 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
3725 | ap->ability_match_cfg = rx_cfg_reg; | |
3726 | ap->ability_match = 0; | |
3727 | ap->ability_match_count = 0; | |
3728 | } else { | |
3729 | if (++ap->ability_match_count > 1) { | |
3730 | ap->ability_match = 1; | |
3731 | ap->ability_match_cfg = rx_cfg_reg; | |
3732 | } | |
3733 | } | |
3734 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
3735 | ap->ack_match = 1; | |
3736 | else | |
3737 | ap->ack_match = 0; | |
3738 | ||
3739 | ap->idle_match = 0; | |
3740 | } else { | |
3741 | ap->idle_match = 1; | |
3742 | ap->ability_match_cfg = 0; | |
3743 | ap->ability_match_count = 0; | |
3744 | ap->ability_match = 0; | |
3745 | ap->ack_match = 0; | |
3746 | ||
3747 | rx_cfg_reg = 0; | |
3748 | } | |
3749 | ||
3750 | ap->rxconfig = rx_cfg_reg; | |
3751 | ret = ANEG_OK; | |
3752 | ||
33f401ae | 3753 | switch (ap->state) { |
1da177e4 LT |
3754 | case ANEG_STATE_UNKNOWN: |
3755 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
3756 | ap->state = ANEG_STATE_AN_ENABLE; | |
3757 | ||
3758 | /* fallthru */ | |
3759 | case ANEG_STATE_AN_ENABLE: | |
3760 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
3761 | if (ap->flags & MR_AN_ENABLE) { | |
3762 | ap->link_time = 0; | |
3763 | ap->cur_time = 0; | |
3764 | ap->ability_match_cfg = 0; | |
3765 | ap->ability_match_count = 0; | |
3766 | ap->ability_match = 0; | |
3767 | ap->idle_match = 0; | |
3768 | ap->ack_match = 0; | |
3769 | ||
3770 | ap->state = ANEG_STATE_RESTART_INIT; | |
3771 | } else { | |
3772 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
3773 | } | |
3774 | break; | |
3775 | ||
3776 | case ANEG_STATE_RESTART_INIT: | |
3777 | ap->link_time = ap->cur_time; | |
3778 | ap->flags &= ~(MR_NP_LOADED); | |
3779 | ap->txconfig = 0; | |
3780 | tw32(MAC_TX_AUTO_NEG, 0); | |
3781 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3782 | tw32_f(MAC_MODE, tp->mac_mode); | |
3783 | udelay(40); | |
3784 | ||
3785 | ret = ANEG_TIMER_ENAB; | |
3786 | ap->state = ANEG_STATE_RESTART; | |
3787 | ||
3788 | /* fallthru */ | |
3789 | case ANEG_STATE_RESTART: | |
3790 | delta = ap->cur_time - ap->link_time; | |
859a5887 | 3791 | if (delta > ANEG_STATE_SETTLE_TIME) |
1da177e4 | 3792 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; |
859a5887 | 3793 | else |
1da177e4 | 3794 | ret = ANEG_TIMER_ENAB; |
1da177e4 LT |
3795 | break; |
3796 | ||
3797 | case ANEG_STATE_DISABLE_LINK_OK: | |
3798 | ret = ANEG_DONE; | |
3799 | break; | |
3800 | ||
3801 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
3802 | ap->flags &= ~(MR_TOGGLE_TX); | |
5be73b47 MC |
3803 | ap->txconfig = ANEG_CFG_FD; |
3804 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3805 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3806 | ap->txconfig |= ANEG_CFG_PS1; | |
3807 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3808 | ap->txconfig |= ANEG_CFG_PS2; | |
1da177e4 LT |
3809 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
3810 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3811 | tw32_f(MAC_MODE, tp->mac_mode); | |
3812 | udelay(40); | |
3813 | ||
3814 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
3815 | break; | |
3816 | ||
3817 | case ANEG_STATE_ABILITY_DETECT: | |
859a5887 | 3818 | if (ap->ability_match != 0 && ap->rxconfig != 0) |
1da177e4 | 3819 | ap->state = ANEG_STATE_ACK_DETECT_INIT; |
1da177e4 LT |
3820 | break; |
3821 | ||
3822 | case ANEG_STATE_ACK_DETECT_INIT: | |
3823 | ap->txconfig |= ANEG_CFG_ACK; | |
3824 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
3825 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3826 | tw32_f(MAC_MODE, tp->mac_mode); | |
3827 | udelay(40); | |
3828 | ||
3829 | ap->state = ANEG_STATE_ACK_DETECT; | |
3830 | ||
3831 | /* fallthru */ | |
3832 | case ANEG_STATE_ACK_DETECT: | |
3833 | if (ap->ack_match != 0) { | |
3834 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
3835 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
3836 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
3837 | } else { | |
3838 | ap->state = ANEG_STATE_AN_ENABLE; | |
3839 | } | |
3840 | } else if (ap->ability_match != 0 && | |
3841 | ap->rxconfig == 0) { | |
3842 | ap->state = ANEG_STATE_AN_ENABLE; | |
3843 | } | |
3844 | break; | |
3845 | ||
3846 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
3847 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
3848 | ret = ANEG_FAILED; | |
3849 | break; | |
3850 | } | |
3851 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
3852 | MR_LP_ADV_HALF_DUPLEX | | |
3853 | MR_LP_ADV_SYM_PAUSE | | |
3854 | MR_LP_ADV_ASYM_PAUSE | | |
3855 | MR_LP_ADV_REMOTE_FAULT1 | | |
3856 | MR_LP_ADV_REMOTE_FAULT2 | | |
3857 | MR_LP_ADV_NEXT_PAGE | | |
3858 | MR_TOGGLE_RX | | |
3859 | MR_NP_RX); | |
3860 | if (ap->rxconfig & ANEG_CFG_FD) | |
3861 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
3862 | if (ap->rxconfig & ANEG_CFG_HD) | |
3863 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
3864 | if (ap->rxconfig & ANEG_CFG_PS1) | |
3865 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
3866 | if (ap->rxconfig & ANEG_CFG_PS2) | |
3867 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
3868 | if (ap->rxconfig & ANEG_CFG_RF1) | |
3869 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
3870 | if (ap->rxconfig & ANEG_CFG_RF2) | |
3871 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
3872 | if (ap->rxconfig & ANEG_CFG_NP) | |
3873 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
3874 | ||
3875 | ap->link_time = ap->cur_time; | |
3876 | ||
3877 | ap->flags ^= (MR_TOGGLE_TX); | |
3878 | if (ap->rxconfig & 0x0008) | |
3879 | ap->flags |= MR_TOGGLE_RX; | |
3880 | if (ap->rxconfig & ANEG_CFG_NP) | |
3881 | ap->flags |= MR_NP_RX; | |
3882 | ap->flags |= MR_PAGE_RX; | |
3883 | ||
3884 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
3885 | ret = ANEG_TIMER_ENAB; | |
3886 | break; | |
3887 | ||
3888 | case ANEG_STATE_COMPLETE_ACK: | |
3889 | if (ap->ability_match != 0 && | |
3890 | ap->rxconfig == 0) { | |
3891 | ap->state = ANEG_STATE_AN_ENABLE; | |
3892 | break; | |
3893 | } | |
3894 | delta = ap->cur_time - ap->link_time; | |
3895 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3896 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
3897 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3898 | } else { | |
3899 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
3900 | !(ap->flags & MR_NP_RX)) { | |
3901 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3902 | } else { | |
3903 | ret = ANEG_FAILED; | |
3904 | } | |
3905 | } | |
3906 | } | |
3907 | break; | |
3908 | ||
3909 | case ANEG_STATE_IDLE_DETECT_INIT: | |
3910 | ap->link_time = ap->cur_time; | |
3911 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3912 | tw32_f(MAC_MODE, tp->mac_mode); | |
3913 | udelay(40); | |
3914 | ||
3915 | ap->state = ANEG_STATE_IDLE_DETECT; | |
3916 | ret = ANEG_TIMER_ENAB; | |
3917 | break; | |
3918 | ||
3919 | case ANEG_STATE_IDLE_DETECT: | |
3920 | if (ap->ability_match != 0 && | |
3921 | ap->rxconfig == 0) { | |
3922 | ap->state = ANEG_STATE_AN_ENABLE; | |
3923 | break; | |
3924 | } | |
3925 | delta = ap->cur_time - ap->link_time; | |
3926 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3927 | /* XXX another gem from the Broadcom driver :( */ | |
3928 | ap->state = ANEG_STATE_LINK_OK; | |
3929 | } | |
3930 | break; | |
3931 | ||
3932 | case ANEG_STATE_LINK_OK: | |
3933 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
3934 | ret = ANEG_DONE; | |
3935 | break; | |
3936 | ||
3937 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
3938 | /* ??? unimplemented */ | |
3939 | break; | |
3940 | ||
3941 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
3942 | /* ??? unimplemented */ | |
3943 | break; | |
3944 | ||
3945 | default: | |
3946 | ret = ANEG_FAILED; | |
3947 | break; | |
855e1111 | 3948 | } |
1da177e4 LT |
3949 | |
3950 | return ret; | |
3951 | } | |
3952 | ||
5be73b47 | 3953 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) |
1da177e4 LT |
3954 | { |
3955 | int res = 0; | |
3956 | struct tg3_fiber_aneginfo aninfo; | |
3957 | int status = ANEG_FAILED; | |
3958 | unsigned int tick; | |
3959 | u32 tmp; | |
3960 | ||
3961 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3962 | ||
3963 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
3964 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
3965 | udelay(40); | |
3966 | ||
3967 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
3968 | udelay(40); | |
3969 | ||
3970 | memset(&aninfo, 0, sizeof(aninfo)); | |
3971 | aninfo.flags |= MR_AN_ENABLE; | |
3972 | aninfo.state = ANEG_STATE_UNKNOWN; | |
3973 | aninfo.cur_time = 0; | |
3974 | tick = 0; | |
3975 | while (++tick < 195000) { | |
3976 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
3977 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
3978 | break; | |
3979 | ||
3980 | udelay(1); | |
3981 | } | |
3982 | ||
3983 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3984 | tw32_f(MAC_MODE, tp->mac_mode); | |
3985 | udelay(40); | |
3986 | ||
5be73b47 MC |
3987 | *txflags = aninfo.txconfig; |
3988 | *rxflags = aninfo.flags; | |
1da177e4 LT |
3989 | |
3990 | if (status == ANEG_DONE && | |
3991 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
3992 | MR_LP_ADV_FULL_DUPLEX))) | |
3993 | res = 1; | |
3994 | ||
3995 | return res; | |
3996 | } | |
3997 | ||
3998 | static void tg3_init_bcm8002(struct tg3 *tp) | |
3999 | { | |
4000 | u32 mac_status = tr32(MAC_STATUS); | |
4001 | int i; | |
4002 | ||
4003 | /* Reset when initting first time or we have a link. */ | |
63c3a66f | 4004 | if (tg3_flag(tp, INIT_COMPLETE) && |
1da177e4 LT |
4005 | !(mac_status & MAC_STATUS_PCS_SYNCED)) |
4006 | return; | |
4007 | ||
4008 | /* Set PLL lock range. */ | |
4009 | tg3_writephy(tp, 0x16, 0x8007); | |
4010 | ||
4011 | /* SW reset */ | |
4012 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
4013 | ||
4014 | /* Wait for reset to complete. */ | |
4015 | /* XXX schedule_timeout() ... */ | |
4016 | for (i = 0; i < 500; i++) | |
4017 | udelay(10); | |
4018 | ||
4019 | /* Config mode; select PMA/Ch 1 regs. */ | |
4020 | tg3_writephy(tp, 0x10, 0x8411); | |
4021 | ||
4022 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
4023 | tg3_writephy(tp, 0x11, 0x0a10); | |
4024 | ||
4025 | tg3_writephy(tp, 0x18, 0x00a0); | |
4026 | tg3_writephy(tp, 0x16, 0x41ff); | |
4027 | ||
4028 | /* Assert and deassert POR. */ | |
4029 | tg3_writephy(tp, 0x13, 0x0400); | |
4030 | udelay(40); | |
4031 | tg3_writephy(tp, 0x13, 0x0000); | |
4032 | ||
4033 | tg3_writephy(tp, 0x11, 0x0a50); | |
4034 | udelay(40); | |
4035 | tg3_writephy(tp, 0x11, 0x0a10); | |
4036 | ||
4037 | /* Wait for signal to stabilize */ | |
4038 | /* XXX schedule_timeout() ... */ | |
4039 | for (i = 0; i < 15000; i++) | |
4040 | udelay(10); | |
4041 | ||
4042 | /* Deselect the channel register so we can read the PHYID | |
4043 | * later. | |
4044 | */ | |
4045 | tg3_writephy(tp, 0x10, 0x8011); | |
4046 | } | |
4047 | ||
4048 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
4049 | { | |
82cd3d11 | 4050 | u16 flowctrl; |
1da177e4 LT |
4051 | u32 sg_dig_ctrl, sg_dig_status; |
4052 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
4053 | int workaround, port_a; | |
4054 | int current_link_up; | |
4055 | ||
4056 | serdes_cfg = 0; | |
4057 | expected_sg_dig_ctrl = 0; | |
4058 | workaround = 0; | |
4059 | port_a = 1; | |
4060 | current_link_up = 0; | |
4061 | ||
4062 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
4063 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
4064 | workaround = 1; | |
4065 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
4066 | port_a = 0; | |
4067 | ||
4068 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
4069 | /* preserve bits 20-23 for voltage regulator */ | |
4070 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
4071 | } | |
4072 | ||
4073 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
4074 | ||
4075 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
c98f6e3b | 4076 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { |
1da177e4 LT |
4077 | if (workaround) { |
4078 | u32 val = serdes_cfg; | |
4079 | ||
4080 | if (port_a) | |
4081 | val |= 0xc010000; | |
4082 | else | |
4083 | val |= 0x4010000; | |
4084 | tw32_f(MAC_SERDES_CFG, val); | |
4085 | } | |
c98f6e3b MC |
4086 | |
4087 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
1da177e4 LT |
4088 | } |
4089 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
4090 | tg3_setup_flow_control(tp, 0, 0); | |
4091 | current_link_up = 1; | |
4092 | } | |
4093 | goto out; | |
4094 | } | |
4095 | ||
4096 | /* Want auto-negotiation. */ | |
c98f6e3b | 4097 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; |
1da177e4 | 4098 | |
82cd3d11 MC |
4099 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
4100 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
4101 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
4102 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
4103 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
1da177e4 LT |
4104 | |
4105 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
f07e9af3 | 4106 | if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && |
3d3ebe74 MC |
4107 | tp->serdes_counter && |
4108 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
4109 | MAC_STATUS_RCVD_CFG)) == | |
4110 | MAC_STATUS_PCS_SYNCED)) { | |
4111 | tp->serdes_counter--; | |
4112 | current_link_up = 1; | |
4113 | goto out; | |
4114 | } | |
4115 | restart_autoneg: | |
1da177e4 LT |
4116 | if (workaround) |
4117 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
c98f6e3b | 4118 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); |
1da177e4 LT |
4119 | udelay(5); |
4120 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
4121 | ||
3d3ebe74 | 4122 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
f07e9af3 | 4123 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
4124 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | |
4125 | MAC_STATUS_SIGNAL_DET)) { | |
3d3ebe74 | 4126 | sg_dig_status = tr32(SG_DIG_STATUS); |
1da177e4 LT |
4127 | mac_status = tr32(MAC_STATUS); |
4128 | ||
c98f6e3b | 4129 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && |
1da177e4 | 4130 | (mac_status & MAC_STATUS_PCS_SYNCED)) { |
82cd3d11 MC |
4131 | u32 local_adv = 0, remote_adv = 0; |
4132 | ||
4133 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
4134 | local_adv |= ADVERTISE_1000XPAUSE; | |
4135 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
4136 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
1da177e4 | 4137 | |
c98f6e3b | 4138 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) |
82cd3d11 | 4139 | remote_adv |= LPA_1000XPAUSE; |
c98f6e3b | 4140 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) |
82cd3d11 | 4141 | remote_adv |= LPA_1000XPAUSE_ASYM; |
1da177e4 LT |
4142 | |
4143 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4144 | current_link_up = 1; | |
3d3ebe74 | 4145 | tp->serdes_counter = 0; |
f07e9af3 | 4146 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
c98f6e3b | 4147 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
3d3ebe74 MC |
4148 | if (tp->serdes_counter) |
4149 | tp->serdes_counter--; | |
1da177e4 LT |
4150 | else { |
4151 | if (workaround) { | |
4152 | u32 val = serdes_cfg; | |
4153 | ||
4154 | if (port_a) | |
4155 | val |= 0xc010000; | |
4156 | else | |
4157 | val |= 0x4010000; | |
4158 | ||
4159 | tw32_f(MAC_SERDES_CFG, val); | |
4160 | } | |
4161 | ||
c98f6e3b | 4162 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
1da177e4 LT |
4163 | udelay(40); |
4164 | ||
4165 | /* Link parallel detection - link is up */ | |
4166 | /* only if we have PCS_SYNC and not */ | |
4167 | /* receiving config code words */ | |
4168 | mac_status = tr32(MAC_STATUS); | |
4169 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
4170 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
4171 | tg3_setup_flow_control(tp, 0, 0); | |
4172 | current_link_up = 1; | |
f07e9af3 MC |
4173 | tp->phy_flags |= |
4174 | TG3_PHYFLG_PARALLEL_DETECT; | |
3d3ebe74 MC |
4175 | tp->serdes_counter = |
4176 | SERDES_PARALLEL_DET_TIMEOUT; | |
4177 | } else | |
4178 | goto restart_autoneg; | |
1da177e4 LT |
4179 | } |
4180 | } | |
3d3ebe74 MC |
4181 | } else { |
4182 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
f07e9af3 | 4183 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
4184 | } |
4185 | ||
4186 | out: | |
4187 | return current_link_up; | |
4188 | } | |
4189 | ||
4190 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
4191 | { | |
4192 | int current_link_up = 0; | |
4193 | ||
5cf64b8a | 4194 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
1da177e4 | 4195 | goto out; |
1da177e4 LT |
4196 | |
4197 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
5be73b47 | 4198 | u32 txflags, rxflags; |
1da177e4 | 4199 | int i; |
6aa20a22 | 4200 | |
5be73b47 MC |
4201 | if (fiber_autoneg(tp, &txflags, &rxflags)) { |
4202 | u32 local_adv = 0, remote_adv = 0; | |
1da177e4 | 4203 | |
5be73b47 MC |
4204 | if (txflags & ANEG_CFG_PS1) |
4205 | local_adv |= ADVERTISE_1000XPAUSE; | |
4206 | if (txflags & ANEG_CFG_PS2) | |
4207 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
4208 | ||
4209 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
4210 | remote_adv |= LPA_1000XPAUSE; | |
4211 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
4212 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
1da177e4 LT |
4213 | |
4214 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4215 | ||
1da177e4 LT |
4216 | current_link_up = 1; |
4217 | } | |
4218 | for (i = 0; i < 30; i++) { | |
4219 | udelay(20); | |
4220 | tw32_f(MAC_STATUS, | |
4221 | (MAC_STATUS_SYNC_CHANGED | | |
4222 | MAC_STATUS_CFG_CHANGED)); | |
4223 | udelay(40); | |
4224 | if ((tr32(MAC_STATUS) & | |
4225 | (MAC_STATUS_SYNC_CHANGED | | |
4226 | MAC_STATUS_CFG_CHANGED)) == 0) | |
4227 | break; | |
4228 | } | |
4229 | ||
4230 | mac_status = tr32(MAC_STATUS); | |
4231 | if (current_link_up == 0 && | |
4232 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
4233 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
4234 | current_link_up = 1; | |
4235 | } else { | |
5be73b47 MC |
4236 | tg3_setup_flow_control(tp, 0, 0); |
4237 | ||
1da177e4 LT |
4238 | /* Forcing 1000FD link up. */ |
4239 | current_link_up = 1; | |
1da177e4 LT |
4240 | |
4241 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
4242 | udelay(40); | |
e8f3f6ca MC |
4243 | |
4244 | tw32_f(MAC_MODE, tp->mac_mode); | |
4245 | udelay(40); | |
1da177e4 LT |
4246 | } |
4247 | ||
4248 | out: | |
4249 | return current_link_up; | |
4250 | } | |
4251 | ||
4252 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
4253 | { | |
4254 | u32 orig_pause_cfg; | |
4255 | u16 orig_active_speed; | |
4256 | u8 orig_active_duplex; | |
4257 | u32 mac_status; | |
4258 | int current_link_up; | |
4259 | int i; | |
4260 | ||
8d018621 | 4261 | orig_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4262 | orig_active_speed = tp->link_config.active_speed; |
4263 | orig_active_duplex = tp->link_config.active_duplex; | |
4264 | ||
63c3a66f | 4265 | if (!tg3_flag(tp, HW_AUTONEG) && |
1da177e4 | 4266 | netif_carrier_ok(tp->dev) && |
63c3a66f | 4267 | tg3_flag(tp, INIT_COMPLETE)) { |
1da177e4 LT |
4268 | mac_status = tr32(MAC_STATUS); |
4269 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
4270 | MAC_STATUS_SIGNAL_DET | | |
4271 | MAC_STATUS_CFG_CHANGED | | |
4272 | MAC_STATUS_RCVD_CFG); | |
4273 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
4274 | MAC_STATUS_SIGNAL_DET)) { | |
4275 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4276 | MAC_STATUS_CFG_CHANGED)); | |
4277 | return 0; | |
4278 | } | |
4279 | } | |
4280 | ||
4281 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
4282 | ||
4283 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
4284 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
4285 | tw32_f(MAC_MODE, tp->mac_mode); | |
4286 | udelay(40); | |
4287 | ||
79eb6904 | 4288 | if (tp->phy_id == TG3_PHY_ID_BCM8002) |
1da177e4 LT |
4289 | tg3_init_bcm8002(tp); |
4290 | ||
4291 | /* Enable link change event even when serdes polling. */ | |
4292 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4293 | udelay(40); | |
4294 | ||
4295 | current_link_up = 0; | |
4296 | mac_status = tr32(MAC_STATUS); | |
4297 | ||
63c3a66f | 4298 | if (tg3_flag(tp, HW_AUTONEG)) |
1da177e4 LT |
4299 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); |
4300 | else | |
4301 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
4302 | ||
898a56f8 | 4303 | tp->napi[0].hw_status->status = |
1da177e4 | 4304 | (SD_STATUS_UPDATED | |
898a56f8 | 4305 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); |
1da177e4 LT |
4306 | |
4307 | for (i = 0; i < 100; i++) { | |
4308 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4309 | MAC_STATUS_CFG_CHANGED)); | |
4310 | udelay(5); | |
4311 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3d3ebe74 MC |
4312 | MAC_STATUS_CFG_CHANGED | |
4313 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
1da177e4 LT |
4314 | break; |
4315 | } | |
4316 | ||
4317 | mac_status = tr32(MAC_STATUS); | |
4318 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
4319 | current_link_up = 0; | |
3d3ebe74 MC |
4320 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
4321 | tp->serdes_counter == 0) { | |
1da177e4 LT |
4322 | tw32_f(MAC_MODE, (tp->mac_mode | |
4323 | MAC_MODE_SEND_CONFIGS)); | |
4324 | udelay(1); | |
4325 | tw32_f(MAC_MODE, tp->mac_mode); | |
4326 | } | |
4327 | } | |
4328 | ||
4329 | if (current_link_up == 1) { | |
4330 | tp->link_config.active_speed = SPEED_1000; | |
4331 | tp->link_config.active_duplex = DUPLEX_FULL; | |
4332 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4333 | LED_CTRL_LNKLED_OVERRIDE | | |
4334 | LED_CTRL_1000MBPS_ON)); | |
4335 | } else { | |
4336 | tp->link_config.active_speed = SPEED_INVALID; | |
4337 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
4338 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4339 | LED_CTRL_LNKLED_OVERRIDE | | |
4340 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
4341 | } | |
4342 | ||
4343 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4344 | if (current_link_up) | |
4345 | netif_carrier_on(tp->dev); | |
4346 | else | |
4347 | netif_carrier_off(tp->dev); | |
4348 | tg3_link_report(tp); | |
4349 | } else { | |
8d018621 | 4350 | u32 now_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4351 | if (orig_pause_cfg != now_pause_cfg || |
4352 | orig_active_speed != tp->link_config.active_speed || | |
4353 | orig_active_duplex != tp->link_config.active_duplex) | |
4354 | tg3_link_report(tp); | |
4355 | } | |
4356 | ||
4357 | return 0; | |
4358 | } | |
4359 | ||
747e8f8b MC |
4360 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) |
4361 | { | |
4362 | int current_link_up, err = 0; | |
4363 | u32 bmsr, bmcr; | |
4364 | u16 current_speed; | |
4365 | u8 current_duplex; | |
ef167e27 | 4366 | u32 local_adv, remote_adv; |
747e8f8b MC |
4367 | |
4368 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
4369 | tw32_f(MAC_MODE, tp->mac_mode); | |
4370 | udelay(40); | |
4371 | ||
4372 | tw32(MAC_EVENT, 0); | |
4373 | ||
4374 | tw32_f(MAC_STATUS, | |
4375 | (MAC_STATUS_SYNC_CHANGED | | |
4376 | MAC_STATUS_CFG_CHANGED | | |
4377 | MAC_STATUS_MI_COMPLETION | | |
4378 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4379 | udelay(40); | |
4380 | ||
4381 | if (force_reset) | |
4382 | tg3_phy_reset(tp); | |
4383 | ||
4384 | current_link_up = 0; | |
4385 | current_speed = SPEED_INVALID; | |
4386 | current_duplex = DUPLEX_INVALID; | |
4387 | ||
4388 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4389 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4390 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
4391 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4392 | bmsr |= BMSR_LSTATUS; | |
4393 | else | |
4394 | bmsr &= ~BMSR_LSTATUS; | |
4395 | } | |
747e8f8b MC |
4396 | |
4397 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
4398 | ||
4399 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
f07e9af3 | 4400 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
4401 | /* do nothing, just check for link up at the end */ |
4402 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
4403 | u32 adv, new_adv; | |
4404 | ||
4405 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4406 | new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | | |
4407 | ADVERTISE_1000XPAUSE | | |
4408 | ADVERTISE_1000XPSE_ASYM | | |
4409 | ADVERTISE_SLCT); | |
4410 | ||
ba4d07a8 | 4411 | new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
747e8f8b MC |
4412 | |
4413 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
4414 | new_adv |= ADVERTISE_1000XHALF; | |
4415 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
4416 | new_adv |= ADVERTISE_1000XFULL; | |
4417 | ||
4418 | if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) { | |
4419 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
4420 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; | |
4421 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4422 | ||
4423 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3d3ebe74 | 4424 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; |
f07e9af3 | 4425 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4426 | |
4427 | return err; | |
4428 | } | |
4429 | } else { | |
4430 | u32 new_bmcr; | |
4431 | ||
4432 | bmcr &= ~BMCR_SPEED1000; | |
4433 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
4434 | ||
4435 | if (tp->link_config.duplex == DUPLEX_FULL) | |
4436 | new_bmcr |= BMCR_FULLDPLX; | |
4437 | ||
4438 | if (new_bmcr != bmcr) { | |
4439 | /* BMCR_SPEED1000 is a reserved bit that needs | |
4440 | * to be set on write. | |
4441 | */ | |
4442 | new_bmcr |= BMCR_SPEED1000; | |
4443 | ||
4444 | /* Force a linkdown */ | |
4445 | if (netif_carrier_ok(tp->dev)) { | |
4446 | u32 adv; | |
4447 | ||
4448 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4449 | adv &= ~(ADVERTISE_1000XFULL | | |
4450 | ADVERTISE_1000XHALF | | |
4451 | ADVERTISE_SLCT); | |
4452 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
4453 | tg3_writephy(tp, MII_BMCR, bmcr | | |
4454 | BMCR_ANRESTART | | |
4455 | BMCR_ANENABLE); | |
4456 | udelay(10); | |
4457 | netif_carrier_off(tp->dev); | |
4458 | } | |
4459 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
4460 | bmcr = new_bmcr; | |
4461 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4462 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4463 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
4464 | ASIC_REV_5714) { | |
4465 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4466 | bmsr |= BMSR_LSTATUS; | |
4467 | else | |
4468 | bmsr &= ~BMSR_LSTATUS; | |
4469 | } | |
f07e9af3 | 4470 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4471 | } |
4472 | } | |
4473 | ||
4474 | if (bmsr & BMSR_LSTATUS) { | |
4475 | current_speed = SPEED_1000; | |
4476 | current_link_up = 1; | |
4477 | if (bmcr & BMCR_FULLDPLX) | |
4478 | current_duplex = DUPLEX_FULL; | |
4479 | else | |
4480 | current_duplex = DUPLEX_HALF; | |
4481 | ||
ef167e27 MC |
4482 | local_adv = 0; |
4483 | remote_adv = 0; | |
4484 | ||
747e8f8b | 4485 | if (bmcr & BMCR_ANENABLE) { |
ef167e27 | 4486 | u32 common; |
747e8f8b MC |
4487 | |
4488 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
4489 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
4490 | common = local_adv & remote_adv; | |
4491 | if (common & (ADVERTISE_1000XHALF | | |
4492 | ADVERTISE_1000XFULL)) { | |
4493 | if (common & ADVERTISE_1000XFULL) | |
4494 | current_duplex = DUPLEX_FULL; | |
4495 | else | |
4496 | current_duplex = DUPLEX_HALF; | |
63c3a66f | 4497 | } else if (!tg3_flag(tp, 5780_CLASS)) { |
57d8b880 | 4498 | /* Link is up via parallel detect */ |
859a5887 | 4499 | } else { |
747e8f8b | 4500 | current_link_up = 0; |
859a5887 | 4501 | } |
747e8f8b MC |
4502 | } |
4503 | } | |
4504 | ||
ef167e27 MC |
4505 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) |
4506 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4507 | ||
747e8f8b MC |
4508 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
4509 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4510 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4511 | ||
4512 | tw32_f(MAC_MODE, tp->mac_mode); | |
4513 | udelay(40); | |
4514 | ||
4515 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4516 | ||
4517 | tp->link_config.active_speed = current_speed; | |
4518 | tp->link_config.active_duplex = current_duplex; | |
4519 | ||
4520 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4521 | if (current_link_up) | |
4522 | netif_carrier_on(tp->dev); | |
4523 | else { | |
4524 | netif_carrier_off(tp->dev); | |
f07e9af3 | 4525 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4526 | } |
4527 | tg3_link_report(tp); | |
4528 | } | |
4529 | return err; | |
4530 | } | |
4531 | ||
4532 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
4533 | { | |
3d3ebe74 | 4534 | if (tp->serdes_counter) { |
747e8f8b | 4535 | /* Give autoneg time to complete. */ |
3d3ebe74 | 4536 | tp->serdes_counter--; |
747e8f8b MC |
4537 | return; |
4538 | } | |
c6cdf436 | 4539 | |
747e8f8b MC |
4540 | if (!netif_carrier_ok(tp->dev) && |
4541 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { | |
4542 | u32 bmcr; | |
4543 | ||
4544 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4545 | if (bmcr & BMCR_ANENABLE) { | |
4546 | u32 phy1, phy2; | |
4547 | ||
4548 | /* Select shadow register 0x1f */ | |
f08aa1a8 MC |
4549 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); |
4550 | tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); | |
747e8f8b MC |
4551 | |
4552 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
4553 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
4554 | MII_TG3_DSP_EXP1_INT_STAT); | |
4555 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
4556 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
4557 | |
4558 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
4559 | /* We have signal detect and not receiving | |
4560 | * config code words, link is up by parallel | |
4561 | * detection. | |
4562 | */ | |
4563 | ||
4564 | bmcr &= ~BMCR_ANENABLE; | |
4565 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
4566 | tg3_writephy(tp, MII_BMCR, bmcr); | |
f07e9af3 | 4567 | tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4568 | } |
4569 | } | |
859a5887 MC |
4570 | } else if (netif_carrier_ok(tp->dev) && |
4571 | (tp->link_config.autoneg == AUTONEG_ENABLE) && | |
f07e9af3 | 4572 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
4573 | u32 phy2; |
4574 | ||
4575 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
4576 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
4577 | MII_TG3_DSP_EXP1_INT_STAT); | |
4578 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
4579 | if (phy2 & 0x20) { |
4580 | u32 bmcr; | |
4581 | ||
4582 | /* Config code words received, turn on autoneg. */ | |
4583 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4584 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
4585 | ||
f07e9af3 | 4586 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4587 | |
4588 | } | |
4589 | } | |
4590 | } | |
4591 | ||
1da177e4 LT |
4592 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) |
4593 | { | |
f2096f94 | 4594 | u32 val; |
1da177e4 LT |
4595 | int err; |
4596 | ||
f07e9af3 | 4597 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 | 4598 | err = tg3_setup_fiber_phy(tp, force_reset); |
f07e9af3 | 4599 | else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
747e8f8b | 4600 | err = tg3_setup_fiber_mii_phy(tp, force_reset); |
859a5887 | 4601 | else |
1da177e4 | 4602 | err = tg3_setup_copper_phy(tp, force_reset); |
1da177e4 | 4603 | |
bcb37f6c | 4604 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
f2096f94 | 4605 | u32 scale; |
aa6c91fe MC |
4606 | |
4607 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
4608 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
4609 | scale = 65; | |
4610 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
4611 | scale = 6; | |
4612 | else | |
4613 | scale = 12; | |
4614 | ||
4615 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
4616 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
4617 | tw32(GRC_MISC_CFG, val); | |
4618 | } | |
4619 | ||
f2096f94 MC |
4620 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
4621 | (6 << TX_LENGTHS_IPG_SHIFT); | |
4622 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
4623 | val |= tr32(MAC_TX_LENGTHS) & | |
4624 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
4625 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
4626 | ||
1da177e4 LT |
4627 | if (tp->link_config.active_speed == SPEED_1000 && |
4628 | tp->link_config.active_duplex == DUPLEX_HALF) | |
f2096f94 MC |
4629 | tw32(MAC_TX_LENGTHS, val | |
4630 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 4631 | else |
f2096f94 MC |
4632 | tw32(MAC_TX_LENGTHS, val | |
4633 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 4634 | |
63c3a66f | 4635 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
4636 | if (netif_carrier_ok(tp->dev)) { |
4637 | tw32(HOSTCC_STAT_COAL_TICKS, | |
15f9850d | 4638 | tp->coal.stats_block_coalesce_usecs); |
1da177e4 LT |
4639 | } else { |
4640 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
4641 | } | |
4642 | } | |
4643 | ||
63c3a66f | 4644 | if (tg3_flag(tp, ASPM_WORKAROUND)) { |
f2096f94 | 4645 | val = tr32(PCIE_PWR_MGMT_THRESH); |
8ed5d97e MC |
4646 | if (!netif_carrier_ok(tp->dev)) |
4647 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | | |
4648 | tp->pwrmgmt_thresh; | |
4649 | else | |
4650 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
4651 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
4652 | } | |
4653 | ||
1da177e4 LT |
4654 | return err; |
4655 | } | |
4656 | ||
66cfd1bd MC |
4657 | static inline int tg3_irq_sync(struct tg3 *tp) |
4658 | { | |
4659 | return tp->irq_sync; | |
4660 | } | |
4661 | ||
97bd8e49 MC |
4662 | static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) |
4663 | { | |
4664 | int i; | |
4665 | ||
4666 | dst = (u32 *)((u8 *)dst + off); | |
4667 | for (i = 0; i < len; i += sizeof(u32)) | |
4668 | *dst++ = tr32(off + i); | |
4669 | } | |
4670 | ||
4671 | static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) | |
4672 | { | |
4673 | tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); | |
4674 | tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); | |
4675 | tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); | |
4676 | tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); | |
4677 | tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); | |
4678 | tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); | |
4679 | tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); | |
4680 | tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); | |
4681 | tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); | |
4682 | tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); | |
4683 | tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); | |
4684 | tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); | |
4685 | tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); | |
4686 | tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); | |
4687 | tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); | |
4688 | tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); | |
4689 | tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); | |
4690 | tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); | |
4691 | tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); | |
4692 | ||
63c3a66f | 4693 | if (tg3_flag(tp, SUPPORT_MSIX)) |
97bd8e49 MC |
4694 | tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); |
4695 | ||
4696 | tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); | |
4697 | tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); | |
4698 | tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); | |
4699 | tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); | |
4700 | tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); | |
4701 | tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); | |
4702 | tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); | |
4703 | tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); | |
4704 | ||
63c3a66f | 4705 | if (!tg3_flag(tp, 5705_PLUS)) { |
97bd8e49 MC |
4706 | tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); |
4707 | tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); | |
4708 | tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); | |
4709 | } | |
4710 | ||
4711 | tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); | |
4712 | tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); | |
4713 | tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); | |
4714 | tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); | |
4715 | tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); | |
4716 | ||
63c3a66f | 4717 | if (tg3_flag(tp, NVRAM)) |
97bd8e49 MC |
4718 | tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); |
4719 | } | |
4720 | ||
4721 | static void tg3_dump_state(struct tg3 *tp) | |
4722 | { | |
4723 | int i; | |
4724 | u32 *regs; | |
4725 | ||
4726 | regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC); | |
4727 | if (!regs) { | |
4728 | netdev_err(tp->dev, "Failed allocating register dump buffer\n"); | |
4729 | return; | |
4730 | } | |
4731 | ||
63c3a66f | 4732 | if (tg3_flag(tp, PCI_EXPRESS)) { |
97bd8e49 MC |
4733 | /* Read up to but not including private PCI registers */ |
4734 | for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) | |
4735 | regs[i / sizeof(u32)] = tr32(i); | |
4736 | } else | |
4737 | tg3_dump_legacy_regs(tp, regs); | |
4738 | ||
4739 | for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) { | |
4740 | if (!regs[i + 0] && !regs[i + 1] && | |
4741 | !regs[i + 2] && !regs[i + 3]) | |
4742 | continue; | |
4743 | ||
4744 | netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", | |
4745 | i * 4, | |
4746 | regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]); | |
4747 | } | |
4748 | ||
4749 | kfree(regs); | |
4750 | ||
4751 | for (i = 0; i < tp->irq_cnt; i++) { | |
4752 | struct tg3_napi *tnapi = &tp->napi[i]; | |
4753 | ||
4754 | /* SW status block */ | |
4755 | netdev_err(tp->dev, | |
4756 | "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", | |
4757 | i, | |
4758 | tnapi->hw_status->status, | |
4759 | tnapi->hw_status->status_tag, | |
4760 | tnapi->hw_status->rx_jumbo_consumer, | |
4761 | tnapi->hw_status->rx_consumer, | |
4762 | tnapi->hw_status->rx_mini_consumer, | |
4763 | tnapi->hw_status->idx[0].rx_producer, | |
4764 | tnapi->hw_status->idx[0].tx_consumer); | |
4765 | ||
4766 | netdev_err(tp->dev, | |
4767 | "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n", | |
4768 | i, | |
4769 | tnapi->last_tag, tnapi->last_irq_tag, | |
4770 | tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, | |
4771 | tnapi->rx_rcb_ptr, | |
4772 | tnapi->prodring.rx_std_prod_idx, | |
4773 | tnapi->prodring.rx_std_cons_idx, | |
4774 | tnapi->prodring.rx_jmb_prod_idx, | |
4775 | tnapi->prodring.rx_jmb_cons_idx); | |
4776 | } | |
4777 | } | |
4778 | ||
df3e6548 MC |
4779 | /* This is called whenever we suspect that the system chipset is re- |
4780 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
4781 | * is bogus tx completions. We try to recover by setting the | |
4782 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
4783 | * in the workqueue. | |
4784 | */ | |
4785 | static void tg3_tx_recover(struct tg3 *tp) | |
4786 | { | |
63c3a66f | 4787 | BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) || |
df3e6548 MC |
4788 | tp->write32_tx_mbox == tg3_write_indirect_mbox); |
4789 | ||
5129c3a3 MC |
4790 | netdev_warn(tp->dev, |
4791 | "The system may be re-ordering memory-mapped I/O " | |
4792 | "cycles to the network device, attempting to recover. " | |
4793 | "Please report the problem to the driver maintainer " | |
4794 | "and include system chipset information.\n"); | |
df3e6548 MC |
4795 | |
4796 | spin_lock(&tp->lock); | |
63c3a66f | 4797 | tg3_flag_set(tp, TX_RECOVERY_PENDING); |
df3e6548 MC |
4798 | spin_unlock(&tp->lock); |
4799 | } | |
4800 | ||
f3f3f27e | 4801 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) |
1b2a7205 | 4802 | { |
f65aac16 MC |
4803 | /* Tell compiler to fetch tx indices from memory. */ |
4804 | barrier(); | |
f3f3f27e MC |
4805 | return tnapi->tx_pending - |
4806 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
1b2a7205 MC |
4807 | } |
4808 | ||
1da177e4 LT |
4809 | /* Tigon3 never reports partial packet sends. So we do not |
4810 | * need special logic to handle SKBs that have not had all | |
4811 | * of their frags sent yet, like SunGEM does. | |
4812 | */ | |
17375d25 | 4813 | static void tg3_tx(struct tg3_napi *tnapi) |
1da177e4 | 4814 | { |
17375d25 | 4815 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 4816 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; |
f3f3f27e | 4817 | u32 sw_idx = tnapi->tx_cons; |
fe5f5787 MC |
4818 | struct netdev_queue *txq; |
4819 | int index = tnapi - tp->napi; | |
4820 | ||
63c3a66f | 4821 | if (tg3_flag(tp, ENABLE_TSS)) |
fe5f5787 MC |
4822 | index--; |
4823 | ||
4824 | txq = netdev_get_tx_queue(tp->dev, index); | |
1da177e4 LT |
4825 | |
4826 | while (sw_idx != hw_idx) { | |
df8944cf | 4827 | struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; |
1da177e4 | 4828 | struct sk_buff *skb = ri->skb; |
df3e6548 MC |
4829 | int i, tx_bug = 0; |
4830 | ||
4831 | if (unlikely(skb == NULL)) { | |
4832 | tg3_tx_recover(tp); | |
4833 | return; | |
4834 | } | |
1da177e4 | 4835 | |
f4188d8a | 4836 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 4837 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
4838 | skb_headlen(skb), |
4839 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
4840 | |
4841 | ri->skb = NULL; | |
4842 | ||
e01ee14d MC |
4843 | while (ri->fragmented) { |
4844 | ri->fragmented = false; | |
4845 | sw_idx = NEXT_TX(sw_idx); | |
4846 | ri = &tnapi->tx_buffers[sw_idx]; | |
4847 | } | |
4848 | ||
1da177e4 LT |
4849 | sw_idx = NEXT_TX(sw_idx); |
4850 | ||
4851 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
f3f3f27e | 4852 | ri = &tnapi->tx_buffers[sw_idx]; |
df3e6548 MC |
4853 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) |
4854 | tx_bug = 1; | |
f4188d8a AD |
4855 | |
4856 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 4857 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
4858 | skb_shinfo(skb)->frags[i].size, |
4859 | PCI_DMA_TODEVICE); | |
e01ee14d MC |
4860 | |
4861 | while (ri->fragmented) { | |
4862 | ri->fragmented = false; | |
4863 | sw_idx = NEXT_TX(sw_idx); | |
4864 | ri = &tnapi->tx_buffers[sw_idx]; | |
4865 | } | |
4866 | ||
1da177e4 LT |
4867 | sw_idx = NEXT_TX(sw_idx); |
4868 | } | |
4869 | ||
f47c11ee | 4870 | dev_kfree_skb(skb); |
df3e6548 MC |
4871 | |
4872 | if (unlikely(tx_bug)) { | |
4873 | tg3_tx_recover(tp); | |
4874 | return; | |
4875 | } | |
1da177e4 LT |
4876 | } |
4877 | ||
f3f3f27e | 4878 | tnapi->tx_cons = sw_idx; |
1da177e4 | 4879 | |
1b2a7205 MC |
4880 | /* Need to make the tx_cons update visible to tg3_start_xmit() |
4881 | * before checking for netif_queue_stopped(). Without the | |
4882 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
4883 | * will miss it and cause the queue to be stopped forever. | |
4884 | */ | |
4885 | smp_mb(); | |
4886 | ||
fe5f5787 | 4887 | if (unlikely(netif_tx_queue_stopped(txq) && |
f3f3f27e | 4888 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { |
fe5f5787 MC |
4889 | __netif_tx_lock(txq, smp_processor_id()); |
4890 | if (netif_tx_queue_stopped(txq) && | |
f3f3f27e | 4891 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) |
fe5f5787 MC |
4892 | netif_tx_wake_queue(txq); |
4893 | __netif_tx_unlock(txq); | |
51b91468 | 4894 | } |
1da177e4 LT |
4895 | } |
4896 | ||
2b2cdb65 MC |
4897 | static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) |
4898 | { | |
4899 | if (!ri->skb) | |
4900 | return; | |
4901 | ||
4e5e4f0d | 4902 | pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), |
2b2cdb65 MC |
4903 | map_sz, PCI_DMA_FROMDEVICE); |
4904 | dev_kfree_skb_any(ri->skb); | |
4905 | ri->skb = NULL; | |
4906 | } | |
4907 | ||
1da177e4 LT |
4908 | /* Returns size of skb allocated or < 0 on error. |
4909 | * | |
4910 | * We only need to fill in the address because the other members | |
4911 | * of the RX descriptor are invariant, see tg3_init_rings. | |
4912 | * | |
4913 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
4914 | * posting buffers we only dirty the first cache line of the RX | |
4915 | * descriptor (containing the address). Whereas for the RX status | |
4916 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
4917 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
4918 | */ | |
86b21e59 | 4919 | static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, |
a3896167 | 4920 | u32 opaque_key, u32 dest_idx_unmasked) |
1da177e4 LT |
4921 | { |
4922 | struct tg3_rx_buffer_desc *desc; | |
f94e290e | 4923 | struct ring_info *map; |
1da177e4 LT |
4924 | struct sk_buff *skb; |
4925 | dma_addr_t mapping; | |
4926 | int skb_size, dest_idx; | |
4927 | ||
1da177e4 LT |
4928 | switch (opaque_key) { |
4929 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 4930 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
21f581a5 MC |
4931 | desc = &tpr->rx_std[dest_idx]; |
4932 | map = &tpr->rx_std_buffers[dest_idx]; | |
287be12e | 4933 | skb_size = tp->rx_pkt_map_sz; |
1da177e4 LT |
4934 | break; |
4935 | ||
4936 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 4937 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
79ed5ac7 | 4938 | desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 4939 | map = &tpr->rx_jmb_buffers[dest_idx]; |
287be12e | 4940 | skb_size = TG3_RX_JMB_MAP_SZ; |
1da177e4 LT |
4941 | break; |
4942 | ||
4943 | default: | |
4944 | return -EINVAL; | |
855e1111 | 4945 | } |
1da177e4 LT |
4946 | |
4947 | /* Do not overwrite any of the map or rp information | |
4948 | * until we are sure we can commit to a new buffer. | |
4949 | * | |
4950 | * Callers depend upon this behavior and assume that | |
4951 | * we leave everything unchanged if we fail. | |
4952 | */ | |
287be12e | 4953 | skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset); |
1da177e4 LT |
4954 | if (skb == NULL) |
4955 | return -ENOMEM; | |
4956 | ||
1da177e4 LT |
4957 | skb_reserve(skb, tp->rx_offset); |
4958 | ||
287be12e | 4959 | mapping = pci_map_single(tp->pdev, skb->data, skb_size, |
1da177e4 | 4960 | PCI_DMA_FROMDEVICE); |
a21771dd MC |
4961 | if (pci_dma_mapping_error(tp->pdev, mapping)) { |
4962 | dev_kfree_skb(skb); | |
4963 | return -EIO; | |
4964 | } | |
1da177e4 LT |
4965 | |
4966 | map->skb = skb; | |
4e5e4f0d | 4967 | dma_unmap_addr_set(map, mapping, mapping); |
1da177e4 | 4968 | |
1da177e4 LT |
4969 | desc->addr_hi = ((u64)mapping >> 32); |
4970 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
4971 | ||
4972 | return skb_size; | |
4973 | } | |
4974 | ||
4975 | /* We only need to move over in the address because the other | |
4976 | * members of the RX descriptor are invariant. See notes above | |
4977 | * tg3_alloc_rx_skb for full details. | |
4978 | */ | |
a3896167 MC |
4979 | static void tg3_recycle_rx(struct tg3_napi *tnapi, |
4980 | struct tg3_rx_prodring_set *dpr, | |
4981 | u32 opaque_key, int src_idx, | |
4982 | u32 dest_idx_unmasked) | |
1da177e4 | 4983 | { |
17375d25 | 4984 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
4985 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; |
4986 | struct ring_info *src_map, *dest_map; | |
8fea32b9 | 4987 | struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; |
c6cdf436 | 4988 | int dest_idx; |
1da177e4 LT |
4989 | |
4990 | switch (opaque_key) { | |
4991 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 4992 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
a3896167 MC |
4993 | dest_desc = &dpr->rx_std[dest_idx]; |
4994 | dest_map = &dpr->rx_std_buffers[dest_idx]; | |
4995 | src_desc = &spr->rx_std[src_idx]; | |
4996 | src_map = &spr->rx_std_buffers[src_idx]; | |
1da177e4 LT |
4997 | break; |
4998 | ||
4999 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 5000 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
a3896167 MC |
5001 | dest_desc = &dpr->rx_jmb[dest_idx].std; |
5002 | dest_map = &dpr->rx_jmb_buffers[dest_idx]; | |
5003 | src_desc = &spr->rx_jmb[src_idx].std; | |
5004 | src_map = &spr->rx_jmb_buffers[src_idx]; | |
1da177e4 LT |
5005 | break; |
5006 | ||
5007 | default: | |
5008 | return; | |
855e1111 | 5009 | } |
1da177e4 LT |
5010 | |
5011 | dest_map->skb = src_map->skb; | |
4e5e4f0d FT |
5012 | dma_unmap_addr_set(dest_map, mapping, |
5013 | dma_unmap_addr(src_map, mapping)); | |
1da177e4 LT |
5014 | dest_desc->addr_hi = src_desc->addr_hi; |
5015 | dest_desc->addr_lo = src_desc->addr_lo; | |
e92967bf MC |
5016 | |
5017 | /* Ensure that the update to the skb happens after the physical | |
5018 | * addresses have been transferred to the new BD location. | |
5019 | */ | |
5020 | smp_wmb(); | |
5021 | ||
1da177e4 LT |
5022 | src_map->skb = NULL; |
5023 | } | |
5024 | ||
1da177e4 LT |
5025 | /* The RX ring scheme is composed of multiple rings which post fresh |
5026 | * buffers to the chip, and one special ring the chip uses to report | |
5027 | * status back to the host. | |
5028 | * | |
5029 | * The special ring reports the status of received packets to the | |
5030 | * host. The chip does not write into the original descriptor the | |
5031 | * RX buffer was obtained from. The chip simply takes the original | |
5032 | * descriptor as provided by the host, updates the status and length | |
5033 | * field, then writes this into the next status ring entry. | |
5034 | * | |
5035 | * Each ring the host uses to post buffers to the chip is described | |
5036 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
5037 | * it is first placed into the on-chip ram. When the packet's length | |
5038 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
5039 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
5040 | * which is within the range of the new packet's length is chosen. | |
5041 | * | |
5042 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
5043 | * sense from a cache coherency perspective. If only the host writes | |
5044 | * to the buffer post rings, and only the chip writes to the rx status | |
5045 | * rings, then cache lines never move beyond shared-modified state. | |
5046 | * If both the host and chip were to write into the same ring, cache line | |
5047 | * eviction could occur since both entities want it in an exclusive state. | |
5048 | */ | |
17375d25 | 5049 | static int tg3_rx(struct tg3_napi *tnapi, int budget) |
1da177e4 | 5050 | { |
17375d25 | 5051 | struct tg3 *tp = tnapi->tp; |
f92905de | 5052 | u32 work_mask, rx_std_posted = 0; |
4361935a | 5053 | u32 std_prod_idx, jmb_prod_idx; |
72334482 | 5054 | u32 sw_idx = tnapi->rx_rcb_ptr; |
483ba50b | 5055 | u16 hw_idx; |
1da177e4 | 5056 | int received; |
8fea32b9 | 5057 | struct tg3_rx_prodring_set *tpr = &tnapi->prodring; |
1da177e4 | 5058 | |
8d9d7cfc | 5059 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
1da177e4 LT |
5060 | /* |
5061 | * We need to order the read of hw_idx and the read of | |
5062 | * the opaque cookie. | |
5063 | */ | |
5064 | rmb(); | |
1da177e4 LT |
5065 | work_mask = 0; |
5066 | received = 0; | |
4361935a MC |
5067 | std_prod_idx = tpr->rx_std_prod_idx; |
5068 | jmb_prod_idx = tpr->rx_jmb_prod_idx; | |
1da177e4 | 5069 | while (sw_idx != hw_idx && budget > 0) { |
afc081f8 | 5070 | struct ring_info *ri; |
72334482 | 5071 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
1da177e4 LT |
5072 | unsigned int len; |
5073 | struct sk_buff *skb; | |
5074 | dma_addr_t dma_addr; | |
5075 | u32 opaque_key, desc_idx, *post_ptr; | |
5076 | ||
5077 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
5078 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
5079 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
8fea32b9 | 5080 | ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; |
4e5e4f0d | 5081 | dma_addr = dma_unmap_addr(ri, mapping); |
21f581a5 | 5082 | skb = ri->skb; |
4361935a | 5083 | post_ptr = &std_prod_idx; |
f92905de | 5084 | rx_std_posted++; |
1da177e4 | 5085 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
8fea32b9 | 5086 | ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; |
4e5e4f0d | 5087 | dma_addr = dma_unmap_addr(ri, mapping); |
21f581a5 | 5088 | skb = ri->skb; |
4361935a | 5089 | post_ptr = &jmb_prod_idx; |
21f581a5 | 5090 | } else |
1da177e4 | 5091 | goto next_pkt_nopost; |
1da177e4 LT |
5092 | |
5093 | work_mask |= opaque_key; | |
5094 | ||
5095 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
5096 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
5097 | drop_it: | |
a3896167 | 5098 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
5099 | desc_idx, *post_ptr); |
5100 | drop_it_no_recycle: | |
5101 | /* Other statistics kept track of by card. */ | |
b0057c51 | 5102 | tp->rx_dropped++; |
1da177e4 LT |
5103 | goto next_pkt; |
5104 | } | |
5105 | ||
ad829268 MC |
5106 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - |
5107 | ETH_FCS_LEN; | |
1da177e4 | 5108 | |
d2757fc4 | 5109 | if (len > TG3_RX_COPY_THRESH(tp)) { |
1da177e4 LT |
5110 | int skb_size; |
5111 | ||
86b21e59 | 5112 | skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key, |
afc081f8 | 5113 | *post_ptr); |
1da177e4 LT |
5114 | if (skb_size < 0) |
5115 | goto drop_it; | |
5116 | ||
287be12e | 5117 | pci_unmap_single(tp->pdev, dma_addr, skb_size, |
1da177e4 LT |
5118 | PCI_DMA_FROMDEVICE); |
5119 | ||
61e800cf MC |
5120 | /* Ensure that the update to the skb happens |
5121 | * after the usage of the old DMA mapping. | |
5122 | */ | |
5123 | smp_wmb(); | |
5124 | ||
5125 | ri->skb = NULL; | |
5126 | ||
1da177e4 LT |
5127 | skb_put(skb, len); |
5128 | } else { | |
5129 | struct sk_buff *copy_skb; | |
5130 | ||
a3896167 | 5131 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
5132 | desc_idx, *post_ptr); |
5133 | ||
bf933c80 | 5134 | copy_skb = netdev_alloc_skb(tp->dev, len + |
9dc7a113 | 5135 | TG3_RAW_IP_ALIGN); |
1da177e4 LT |
5136 | if (copy_skb == NULL) |
5137 | goto drop_it_no_recycle; | |
5138 | ||
bf933c80 | 5139 | skb_reserve(copy_skb, TG3_RAW_IP_ALIGN); |
1da177e4 LT |
5140 | skb_put(copy_skb, len); |
5141 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
d626f62b | 5142 | skb_copy_from_linear_data(skb, copy_skb->data, len); |
1da177e4 LT |
5143 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
5144 | ||
5145 | /* We'll reuse the original ring buffer. */ | |
5146 | skb = copy_skb; | |
5147 | } | |
5148 | ||
dc668910 | 5149 | if ((tp->dev->features & NETIF_F_RXCSUM) && |
1da177e4 LT |
5150 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && |
5151 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
5152 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
5153 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
5154 | else | |
bc8acf2c | 5155 | skb_checksum_none_assert(skb); |
1da177e4 LT |
5156 | |
5157 | skb->protocol = eth_type_trans(skb, tp->dev); | |
f7b493e0 MC |
5158 | |
5159 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
5160 | skb->protocol != htons(ETH_P_8021Q)) { | |
5161 | dev_kfree_skb(skb); | |
b0057c51 | 5162 | goto drop_it_no_recycle; |
f7b493e0 MC |
5163 | } |
5164 | ||
9dc7a113 | 5165 | if (desc->type_flags & RXD_FLAG_VLAN && |
bf933c80 MC |
5166 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) |
5167 | __vlan_hwaccel_put_tag(skb, | |
5168 | desc->err_vlan & RXD_VLAN_MASK); | |
9dc7a113 | 5169 | |
bf933c80 | 5170 | napi_gro_receive(&tnapi->napi, skb); |
1da177e4 | 5171 | |
1da177e4 LT |
5172 | received++; |
5173 | budget--; | |
5174 | ||
5175 | next_pkt: | |
5176 | (*post_ptr)++; | |
f92905de MC |
5177 | |
5178 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
2c49a44d MC |
5179 | tpr->rx_std_prod_idx = std_prod_idx & |
5180 | tp->rx_std_ring_mask; | |
86cfe4ff MC |
5181 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
5182 | tpr->rx_std_prod_idx); | |
f92905de MC |
5183 | work_mask &= ~RXD_OPAQUE_RING_STD; |
5184 | rx_std_posted = 0; | |
5185 | } | |
1da177e4 | 5186 | next_pkt_nopost: |
483ba50b | 5187 | sw_idx++; |
7cb32cf2 | 5188 | sw_idx &= tp->rx_ret_ring_mask; |
52f6d697 MC |
5189 | |
5190 | /* Refresh hw_idx to see if there is new work */ | |
5191 | if (sw_idx == hw_idx) { | |
8d9d7cfc | 5192 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
52f6d697 MC |
5193 | rmb(); |
5194 | } | |
1da177e4 LT |
5195 | } |
5196 | ||
5197 | /* ACK the status ring. */ | |
72334482 MC |
5198 | tnapi->rx_rcb_ptr = sw_idx; |
5199 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
1da177e4 LT |
5200 | |
5201 | /* Refill RX ring(s). */ | |
63c3a66f | 5202 | if (!tg3_flag(tp, ENABLE_RSS)) { |
b196c7e4 | 5203 | if (work_mask & RXD_OPAQUE_RING_STD) { |
2c49a44d MC |
5204 | tpr->rx_std_prod_idx = std_prod_idx & |
5205 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
5206 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
5207 | tpr->rx_std_prod_idx); | |
5208 | } | |
5209 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
2c49a44d MC |
5210 | tpr->rx_jmb_prod_idx = jmb_prod_idx & |
5211 | tp->rx_jmb_ring_mask; | |
b196c7e4 MC |
5212 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, |
5213 | tpr->rx_jmb_prod_idx); | |
5214 | } | |
5215 | mmiowb(); | |
5216 | } else if (work_mask) { | |
5217 | /* rx_std_buffers[] and rx_jmb_buffers[] entries must be | |
5218 | * updated before the producer indices can be updated. | |
5219 | */ | |
5220 | smp_wmb(); | |
5221 | ||
2c49a44d MC |
5222 | tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; |
5223 | tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; | |
b196c7e4 | 5224 | |
e4af1af9 MC |
5225 | if (tnapi != &tp->napi[1]) |
5226 | napi_schedule(&tp->napi[1].napi); | |
1da177e4 | 5227 | } |
1da177e4 LT |
5228 | |
5229 | return received; | |
5230 | } | |
5231 | ||
35f2d7d0 | 5232 | static void tg3_poll_link(struct tg3 *tp) |
1da177e4 | 5233 | { |
1da177e4 | 5234 | /* handle link change and other phy events */ |
63c3a66f | 5235 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
35f2d7d0 MC |
5236 | struct tg3_hw_status *sblk = tp->napi[0].hw_status; |
5237 | ||
1da177e4 LT |
5238 | if (sblk->status & SD_STATUS_LINK_CHG) { |
5239 | sblk->status = SD_STATUS_UPDATED | | |
35f2d7d0 | 5240 | (sblk->status & ~SD_STATUS_LINK_CHG); |
f47c11ee | 5241 | spin_lock(&tp->lock); |
63c3a66f | 5242 | if (tg3_flag(tp, USE_PHYLIB)) { |
dd477003 MC |
5243 | tw32_f(MAC_STATUS, |
5244 | (MAC_STATUS_SYNC_CHANGED | | |
5245 | MAC_STATUS_CFG_CHANGED | | |
5246 | MAC_STATUS_MI_COMPLETION | | |
5247 | MAC_STATUS_LNKSTATE_CHANGED)); | |
5248 | udelay(40); | |
5249 | } else | |
5250 | tg3_setup_phy(tp, 0); | |
f47c11ee | 5251 | spin_unlock(&tp->lock); |
1da177e4 LT |
5252 | } |
5253 | } | |
35f2d7d0 MC |
5254 | } |
5255 | ||
f89f38b8 MC |
5256 | static int tg3_rx_prodring_xfer(struct tg3 *tp, |
5257 | struct tg3_rx_prodring_set *dpr, | |
5258 | struct tg3_rx_prodring_set *spr) | |
b196c7e4 MC |
5259 | { |
5260 | u32 si, di, cpycnt, src_prod_idx; | |
f89f38b8 | 5261 | int i, err = 0; |
b196c7e4 MC |
5262 | |
5263 | while (1) { | |
5264 | src_prod_idx = spr->rx_std_prod_idx; | |
5265 | ||
5266 | /* Make sure updates to the rx_std_buffers[] entries and the | |
5267 | * standard producer index are seen in the correct order. | |
5268 | */ | |
5269 | smp_rmb(); | |
5270 | ||
5271 | if (spr->rx_std_cons_idx == src_prod_idx) | |
5272 | break; | |
5273 | ||
5274 | if (spr->rx_std_cons_idx < src_prod_idx) | |
5275 | cpycnt = src_prod_idx - spr->rx_std_cons_idx; | |
5276 | else | |
2c49a44d MC |
5277 | cpycnt = tp->rx_std_ring_mask + 1 - |
5278 | spr->rx_std_cons_idx; | |
b196c7e4 | 5279 | |
2c49a44d MC |
5280 | cpycnt = min(cpycnt, |
5281 | tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); | |
b196c7e4 MC |
5282 | |
5283 | si = spr->rx_std_cons_idx; | |
5284 | di = dpr->rx_std_prod_idx; | |
5285 | ||
e92967bf MC |
5286 | for (i = di; i < di + cpycnt; i++) { |
5287 | if (dpr->rx_std_buffers[i].skb) { | |
5288 | cpycnt = i - di; | |
f89f38b8 | 5289 | err = -ENOSPC; |
e92967bf MC |
5290 | break; |
5291 | } | |
5292 | } | |
5293 | ||
5294 | if (!cpycnt) | |
5295 | break; | |
5296 | ||
5297 | /* Ensure that updates to the rx_std_buffers ring and the | |
5298 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5299 | * ordered correctly WRT the skb check above. | |
5300 | */ | |
5301 | smp_rmb(); | |
5302 | ||
b196c7e4 MC |
5303 | memcpy(&dpr->rx_std_buffers[di], |
5304 | &spr->rx_std_buffers[si], | |
5305 | cpycnt * sizeof(struct ring_info)); | |
5306 | ||
5307 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5308 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5309 | sbd = &spr->rx_std[si]; | |
5310 | dbd = &dpr->rx_std[di]; | |
5311 | dbd->addr_hi = sbd->addr_hi; | |
5312 | dbd->addr_lo = sbd->addr_lo; | |
5313 | } | |
5314 | ||
2c49a44d MC |
5315 | spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & |
5316 | tp->rx_std_ring_mask; | |
5317 | dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & | |
5318 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
5319 | } |
5320 | ||
5321 | while (1) { | |
5322 | src_prod_idx = spr->rx_jmb_prod_idx; | |
5323 | ||
5324 | /* Make sure updates to the rx_jmb_buffers[] entries and | |
5325 | * the jumbo producer index are seen in the correct order. | |
5326 | */ | |
5327 | smp_rmb(); | |
5328 | ||
5329 | if (spr->rx_jmb_cons_idx == src_prod_idx) | |
5330 | break; | |
5331 | ||
5332 | if (spr->rx_jmb_cons_idx < src_prod_idx) | |
5333 | cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; | |
5334 | else | |
2c49a44d MC |
5335 | cpycnt = tp->rx_jmb_ring_mask + 1 - |
5336 | spr->rx_jmb_cons_idx; | |
b196c7e4 MC |
5337 | |
5338 | cpycnt = min(cpycnt, | |
2c49a44d | 5339 | tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); |
b196c7e4 MC |
5340 | |
5341 | si = spr->rx_jmb_cons_idx; | |
5342 | di = dpr->rx_jmb_prod_idx; | |
5343 | ||
e92967bf MC |
5344 | for (i = di; i < di + cpycnt; i++) { |
5345 | if (dpr->rx_jmb_buffers[i].skb) { | |
5346 | cpycnt = i - di; | |
f89f38b8 | 5347 | err = -ENOSPC; |
e92967bf MC |
5348 | break; |
5349 | } | |
5350 | } | |
5351 | ||
5352 | if (!cpycnt) | |
5353 | break; | |
5354 | ||
5355 | /* Ensure that updates to the rx_jmb_buffers ring and the | |
5356 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5357 | * ordered correctly WRT the skb check above. | |
5358 | */ | |
5359 | smp_rmb(); | |
5360 | ||
b196c7e4 MC |
5361 | memcpy(&dpr->rx_jmb_buffers[di], |
5362 | &spr->rx_jmb_buffers[si], | |
5363 | cpycnt * sizeof(struct ring_info)); | |
5364 | ||
5365 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5366 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5367 | sbd = &spr->rx_jmb[si].std; | |
5368 | dbd = &dpr->rx_jmb[di].std; | |
5369 | dbd->addr_hi = sbd->addr_hi; | |
5370 | dbd->addr_lo = sbd->addr_lo; | |
5371 | } | |
5372 | ||
2c49a44d MC |
5373 | spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & |
5374 | tp->rx_jmb_ring_mask; | |
5375 | dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & | |
5376 | tp->rx_jmb_ring_mask; | |
b196c7e4 | 5377 | } |
f89f38b8 MC |
5378 | |
5379 | return err; | |
b196c7e4 MC |
5380 | } |
5381 | ||
35f2d7d0 MC |
5382 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) |
5383 | { | |
5384 | struct tg3 *tp = tnapi->tp; | |
1da177e4 LT |
5385 | |
5386 | /* run TX completion thread */ | |
f3f3f27e | 5387 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { |
17375d25 | 5388 | tg3_tx(tnapi); |
63c3a66f | 5389 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
4fd7ab59 | 5390 | return work_done; |
1da177e4 LT |
5391 | } |
5392 | ||
1da177e4 LT |
5393 | /* run RX thread, within the bounds set by NAPI. |
5394 | * All RX "locking" is done by ensuring outside | |
bea3348e | 5395 | * code synchronizes with tg3->napi.poll() |
1da177e4 | 5396 | */ |
8d9d7cfc | 5397 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
17375d25 | 5398 | work_done += tg3_rx(tnapi, budget - work_done); |
1da177e4 | 5399 | |
63c3a66f | 5400 | if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { |
8fea32b9 | 5401 | struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; |
f89f38b8 | 5402 | int i, err = 0; |
e4af1af9 MC |
5403 | u32 std_prod_idx = dpr->rx_std_prod_idx; |
5404 | u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; | |
b196c7e4 | 5405 | |
e4af1af9 | 5406 | for (i = 1; i < tp->irq_cnt; i++) |
f89f38b8 | 5407 | err |= tg3_rx_prodring_xfer(tp, dpr, |
8fea32b9 | 5408 | &tp->napi[i].prodring); |
b196c7e4 MC |
5409 | |
5410 | wmb(); | |
5411 | ||
e4af1af9 MC |
5412 | if (std_prod_idx != dpr->rx_std_prod_idx) |
5413 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
5414 | dpr->rx_std_prod_idx); | |
b196c7e4 | 5415 | |
e4af1af9 MC |
5416 | if (jmb_prod_idx != dpr->rx_jmb_prod_idx) |
5417 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
5418 | dpr->rx_jmb_prod_idx); | |
b196c7e4 MC |
5419 | |
5420 | mmiowb(); | |
f89f38b8 MC |
5421 | |
5422 | if (err) | |
5423 | tw32_f(HOSTCC_MODE, tp->coal_now); | |
b196c7e4 MC |
5424 | } |
5425 | ||
6f535763 DM |
5426 | return work_done; |
5427 | } | |
5428 | ||
35f2d7d0 MC |
5429 | static int tg3_poll_msix(struct napi_struct *napi, int budget) |
5430 | { | |
5431 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
5432 | struct tg3 *tp = tnapi->tp; | |
5433 | int work_done = 0; | |
5434 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5435 | ||
5436 | while (1) { | |
5437 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
5438 | ||
63c3a66f | 5439 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
35f2d7d0 MC |
5440 | goto tx_recovery; |
5441 | ||
5442 | if (unlikely(work_done >= budget)) | |
5443 | break; | |
5444 | ||
c6cdf436 | 5445 | /* tp->last_tag is used in tg3_int_reenable() below |
35f2d7d0 MC |
5446 | * to tell the hw how much work has been processed, |
5447 | * so we must read it before checking for more work. | |
5448 | */ | |
5449 | tnapi->last_tag = sblk->status_tag; | |
5450 | tnapi->last_irq_tag = tnapi->last_tag; | |
5451 | rmb(); | |
5452 | ||
5453 | /* check for RX/TX work to do */ | |
6d40db7b MC |
5454 | if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && |
5455 | *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { | |
35f2d7d0 MC |
5456 | napi_complete(napi); |
5457 | /* Reenable interrupts. */ | |
5458 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
5459 | mmiowb(); | |
5460 | break; | |
5461 | } | |
5462 | } | |
5463 | ||
5464 | return work_done; | |
5465 | ||
5466 | tx_recovery: | |
5467 | /* work_done is guaranteed to be less than budget. */ | |
5468 | napi_complete(napi); | |
5469 | schedule_work(&tp->reset_task); | |
5470 | return work_done; | |
5471 | } | |
5472 | ||
e64de4e6 MC |
5473 | static void tg3_process_error(struct tg3 *tp) |
5474 | { | |
5475 | u32 val; | |
5476 | bool real_error = false; | |
5477 | ||
63c3a66f | 5478 | if (tg3_flag(tp, ERROR_PROCESSED)) |
e64de4e6 MC |
5479 | return; |
5480 | ||
5481 | /* Check Flow Attention register */ | |
5482 | val = tr32(HOSTCC_FLOW_ATTN); | |
5483 | if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) { | |
5484 | netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); | |
5485 | real_error = true; | |
5486 | } | |
5487 | ||
5488 | if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { | |
5489 | netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); | |
5490 | real_error = true; | |
5491 | } | |
5492 | ||
5493 | if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { | |
5494 | netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); | |
5495 | real_error = true; | |
5496 | } | |
5497 | ||
5498 | if (!real_error) | |
5499 | return; | |
5500 | ||
5501 | tg3_dump_state(tp); | |
5502 | ||
63c3a66f | 5503 | tg3_flag_set(tp, ERROR_PROCESSED); |
e64de4e6 MC |
5504 | schedule_work(&tp->reset_task); |
5505 | } | |
5506 | ||
6f535763 DM |
5507 | static int tg3_poll(struct napi_struct *napi, int budget) |
5508 | { | |
8ef0442f MC |
5509 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
5510 | struct tg3 *tp = tnapi->tp; | |
6f535763 | 5511 | int work_done = 0; |
898a56f8 | 5512 | struct tg3_hw_status *sblk = tnapi->hw_status; |
6f535763 DM |
5513 | |
5514 | while (1) { | |
e64de4e6 MC |
5515 | if (sblk->status & SD_STATUS_ERROR) |
5516 | tg3_process_error(tp); | |
5517 | ||
35f2d7d0 MC |
5518 | tg3_poll_link(tp); |
5519 | ||
17375d25 | 5520 | work_done = tg3_poll_work(tnapi, work_done, budget); |
6f535763 | 5521 | |
63c3a66f | 5522 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
6f535763 DM |
5523 | goto tx_recovery; |
5524 | ||
5525 | if (unlikely(work_done >= budget)) | |
5526 | break; | |
5527 | ||
63c3a66f | 5528 | if (tg3_flag(tp, TAGGED_STATUS)) { |
17375d25 | 5529 | /* tp->last_tag is used in tg3_int_reenable() below |
4fd7ab59 MC |
5530 | * to tell the hw how much work has been processed, |
5531 | * so we must read it before checking for more work. | |
5532 | */ | |
898a56f8 MC |
5533 | tnapi->last_tag = sblk->status_tag; |
5534 | tnapi->last_irq_tag = tnapi->last_tag; | |
4fd7ab59 MC |
5535 | rmb(); |
5536 | } else | |
5537 | sblk->status &= ~SD_STATUS_UPDATED; | |
6f535763 | 5538 | |
17375d25 | 5539 | if (likely(!tg3_has_work(tnapi))) { |
288379f0 | 5540 | napi_complete(napi); |
17375d25 | 5541 | tg3_int_reenable(tnapi); |
6f535763 DM |
5542 | break; |
5543 | } | |
1da177e4 LT |
5544 | } |
5545 | ||
bea3348e | 5546 | return work_done; |
6f535763 DM |
5547 | |
5548 | tx_recovery: | |
4fd7ab59 | 5549 | /* work_done is guaranteed to be less than budget. */ |
288379f0 | 5550 | napi_complete(napi); |
6f535763 | 5551 | schedule_work(&tp->reset_task); |
4fd7ab59 | 5552 | return work_done; |
1da177e4 LT |
5553 | } |
5554 | ||
66cfd1bd MC |
5555 | static void tg3_napi_disable(struct tg3 *tp) |
5556 | { | |
5557 | int i; | |
5558 | ||
5559 | for (i = tp->irq_cnt - 1; i >= 0; i--) | |
5560 | napi_disable(&tp->napi[i].napi); | |
5561 | } | |
5562 | ||
5563 | static void tg3_napi_enable(struct tg3 *tp) | |
5564 | { | |
5565 | int i; | |
5566 | ||
5567 | for (i = 0; i < tp->irq_cnt; i++) | |
5568 | napi_enable(&tp->napi[i].napi); | |
5569 | } | |
5570 | ||
5571 | static void tg3_napi_init(struct tg3 *tp) | |
5572 | { | |
5573 | int i; | |
5574 | ||
5575 | netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); | |
5576 | for (i = 1; i < tp->irq_cnt; i++) | |
5577 | netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); | |
5578 | } | |
5579 | ||
5580 | static void tg3_napi_fini(struct tg3 *tp) | |
5581 | { | |
5582 | int i; | |
5583 | ||
5584 | for (i = 0; i < tp->irq_cnt; i++) | |
5585 | netif_napi_del(&tp->napi[i].napi); | |
5586 | } | |
5587 | ||
5588 | static inline void tg3_netif_stop(struct tg3 *tp) | |
5589 | { | |
5590 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
5591 | tg3_napi_disable(tp); | |
5592 | netif_tx_disable(tp->dev); | |
5593 | } | |
5594 | ||
5595 | static inline void tg3_netif_start(struct tg3 *tp) | |
5596 | { | |
5597 | /* NOTE: unconditional netif_tx_wake_all_queues is only | |
5598 | * appropriate so long as all callers are assured to | |
5599 | * have free tx slots (such as after tg3_init_hw) | |
5600 | */ | |
5601 | netif_tx_wake_all_queues(tp->dev); | |
5602 | ||
5603 | tg3_napi_enable(tp); | |
5604 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; | |
5605 | tg3_enable_ints(tp); | |
5606 | } | |
5607 | ||
f47c11ee DM |
5608 | static void tg3_irq_quiesce(struct tg3 *tp) |
5609 | { | |
4f125f42 MC |
5610 | int i; |
5611 | ||
f47c11ee DM |
5612 | BUG_ON(tp->irq_sync); |
5613 | ||
5614 | tp->irq_sync = 1; | |
5615 | smp_mb(); | |
5616 | ||
4f125f42 MC |
5617 | for (i = 0; i < tp->irq_cnt; i++) |
5618 | synchronize_irq(tp->napi[i].irq_vec); | |
f47c11ee DM |
5619 | } |
5620 | ||
f47c11ee DM |
5621 | /* Fully shutdown all tg3 driver activity elsewhere in the system. |
5622 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
5623 | * with as well. Most of the time, this is not necessary except when | |
5624 | * shutting down the device. | |
5625 | */ | |
5626 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
5627 | { | |
46966545 | 5628 | spin_lock_bh(&tp->lock); |
f47c11ee DM |
5629 | if (irq_sync) |
5630 | tg3_irq_quiesce(tp); | |
f47c11ee DM |
5631 | } |
5632 | ||
5633 | static inline void tg3_full_unlock(struct tg3 *tp) | |
5634 | { | |
f47c11ee DM |
5635 | spin_unlock_bh(&tp->lock); |
5636 | } | |
5637 | ||
fcfa0a32 MC |
5638 | /* One-shot MSI handler - Chip automatically disables interrupt |
5639 | * after sending MSI so driver doesn't have to do it. | |
5640 | */ | |
7d12e780 | 5641 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) |
fcfa0a32 | 5642 | { |
09943a18 MC |
5643 | struct tg3_napi *tnapi = dev_id; |
5644 | struct tg3 *tp = tnapi->tp; | |
fcfa0a32 | 5645 | |
898a56f8 | 5646 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
5647 | if (tnapi->rx_rcb) |
5648 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
fcfa0a32 MC |
5649 | |
5650 | if (likely(!tg3_irq_sync(tp))) | |
09943a18 | 5651 | napi_schedule(&tnapi->napi); |
fcfa0a32 MC |
5652 | |
5653 | return IRQ_HANDLED; | |
5654 | } | |
5655 | ||
88b06bc2 MC |
5656 | /* MSI ISR - No need to check for interrupt sharing and no need to |
5657 | * flush status block and interrupt mailbox. PCI ordering rules | |
5658 | * guarantee that MSI will arrive after the status block. | |
5659 | */ | |
7d12e780 | 5660 | static irqreturn_t tg3_msi(int irq, void *dev_id) |
88b06bc2 | 5661 | { |
09943a18 MC |
5662 | struct tg3_napi *tnapi = dev_id; |
5663 | struct tg3 *tp = tnapi->tp; | |
88b06bc2 | 5664 | |
898a56f8 | 5665 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
5666 | if (tnapi->rx_rcb) |
5667 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
88b06bc2 | 5668 | /* |
fac9b83e | 5669 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
88b06bc2 | 5670 | * chip-internal interrupt pending events. |
fac9b83e | 5671 | * Writing non-zero to intr-mbox-0 additional tells the |
88b06bc2 MC |
5672 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
5673 | * event coalescing. | |
5674 | */ | |
5675 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
61487480 | 5676 | if (likely(!tg3_irq_sync(tp))) |
09943a18 | 5677 | napi_schedule(&tnapi->napi); |
61487480 | 5678 | |
88b06bc2 MC |
5679 | return IRQ_RETVAL(1); |
5680 | } | |
5681 | ||
7d12e780 | 5682 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) |
1da177e4 | 5683 | { |
09943a18 MC |
5684 | struct tg3_napi *tnapi = dev_id; |
5685 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5686 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 LT |
5687 | unsigned int handled = 1; |
5688 | ||
1da177e4 LT |
5689 | /* In INTx mode, it is possible for the interrupt to arrive at |
5690 | * the CPU before the status block posted prior to the interrupt. | |
5691 | * Reading the PCI State register will confirm whether the | |
5692 | * interrupt is ours and will flush the status block. | |
5693 | */ | |
d18edcb2 | 5694 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { |
63c3a66f | 5695 | if (tg3_flag(tp, CHIP_RESETTING) || |
d18edcb2 MC |
5696 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
5697 | handled = 0; | |
f47c11ee | 5698 | goto out; |
fac9b83e | 5699 | } |
d18edcb2 MC |
5700 | } |
5701 | ||
5702 | /* | |
5703 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
5704 | * chip-internal interrupt pending events. | |
5705 | * Writing non-zero to intr-mbox-0 additional tells the | |
5706 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5707 | * event coalescing. | |
c04cb347 MC |
5708 | * |
5709 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5710 | * spurious interrupts. The flush impacts performance but | |
5711 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 5712 | */ |
c04cb347 | 5713 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
d18edcb2 MC |
5714 | if (tg3_irq_sync(tp)) |
5715 | goto out; | |
5716 | sblk->status &= ~SD_STATUS_UPDATED; | |
17375d25 | 5717 | if (likely(tg3_has_work(tnapi))) { |
72334482 | 5718 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
09943a18 | 5719 | napi_schedule(&tnapi->napi); |
d18edcb2 MC |
5720 | } else { |
5721 | /* No work, shared interrupt perhaps? re-enable | |
5722 | * interrupts, and flush that PCI write | |
5723 | */ | |
5724 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
5725 | 0x00000000); | |
fac9b83e | 5726 | } |
f47c11ee | 5727 | out: |
fac9b83e DM |
5728 | return IRQ_RETVAL(handled); |
5729 | } | |
5730 | ||
7d12e780 | 5731 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) |
fac9b83e | 5732 | { |
09943a18 MC |
5733 | struct tg3_napi *tnapi = dev_id; |
5734 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5735 | struct tg3_hw_status *sblk = tnapi->hw_status; |
fac9b83e DM |
5736 | unsigned int handled = 1; |
5737 | ||
fac9b83e DM |
5738 | /* In INTx mode, it is possible for the interrupt to arrive at |
5739 | * the CPU before the status block posted prior to the interrupt. | |
5740 | * Reading the PCI State register will confirm whether the | |
5741 | * interrupt is ours and will flush the status block. | |
5742 | */ | |
898a56f8 | 5743 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { |
63c3a66f | 5744 | if (tg3_flag(tp, CHIP_RESETTING) || |
d18edcb2 MC |
5745 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
5746 | handled = 0; | |
f47c11ee | 5747 | goto out; |
1da177e4 | 5748 | } |
d18edcb2 MC |
5749 | } |
5750 | ||
5751 | /* | |
5752 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
5753 | * chip-internal interrupt pending events. | |
5754 | * writing non-zero to intr-mbox-0 additional tells the | |
5755 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5756 | * event coalescing. | |
c04cb347 MC |
5757 | * |
5758 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5759 | * spurious interrupts. The flush impacts performance but | |
5760 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 5761 | */ |
c04cb347 | 5762 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
624f8e50 MC |
5763 | |
5764 | /* | |
5765 | * In a shared interrupt configuration, sometimes other devices' | |
5766 | * interrupts will scream. We record the current status tag here | |
5767 | * so that the above check can report that the screaming interrupts | |
5768 | * are unhandled. Eventually they will be silenced. | |
5769 | */ | |
898a56f8 | 5770 | tnapi->last_irq_tag = sblk->status_tag; |
624f8e50 | 5771 | |
d18edcb2 MC |
5772 | if (tg3_irq_sync(tp)) |
5773 | goto out; | |
624f8e50 | 5774 | |
72334482 | 5775 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
624f8e50 | 5776 | |
09943a18 | 5777 | napi_schedule(&tnapi->napi); |
624f8e50 | 5778 | |
f47c11ee | 5779 | out: |
1da177e4 LT |
5780 | return IRQ_RETVAL(handled); |
5781 | } | |
5782 | ||
7938109f | 5783 | /* ISR for interrupt test */ |
7d12e780 | 5784 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) |
7938109f | 5785 | { |
09943a18 MC |
5786 | struct tg3_napi *tnapi = dev_id; |
5787 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5788 | struct tg3_hw_status *sblk = tnapi->hw_status; |
7938109f | 5789 | |
f9804ddb MC |
5790 | if ((sblk->status & SD_STATUS_UPDATED) || |
5791 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
b16250e3 | 5792 | tg3_disable_ints(tp); |
7938109f MC |
5793 | return IRQ_RETVAL(1); |
5794 | } | |
5795 | return IRQ_RETVAL(0); | |
5796 | } | |
5797 | ||
8e7a22e3 | 5798 | static int tg3_init_hw(struct tg3 *, int); |
944d980e | 5799 | static int tg3_halt(struct tg3 *, int, int); |
1da177e4 | 5800 | |
b9ec6c1b MC |
5801 | /* Restart hardware after configuration changes, self-test, etc. |
5802 | * Invoked with tp->lock held. | |
5803 | */ | |
5804 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
78c6146f ED |
5805 | __releases(tp->lock) |
5806 | __acquires(tp->lock) | |
b9ec6c1b MC |
5807 | { |
5808 | int err; | |
5809 | ||
5810 | err = tg3_init_hw(tp, reset_phy); | |
5811 | if (err) { | |
5129c3a3 MC |
5812 | netdev_err(tp->dev, |
5813 | "Failed to re-initialize device, aborting\n"); | |
b9ec6c1b MC |
5814 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
5815 | tg3_full_unlock(tp); | |
5816 | del_timer_sync(&tp->timer); | |
5817 | tp->irq_sync = 0; | |
fed97810 | 5818 | tg3_napi_enable(tp); |
b9ec6c1b MC |
5819 | dev_close(tp->dev); |
5820 | tg3_full_lock(tp, 0); | |
5821 | } | |
5822 | return err; | |
5823 | } | |
5824 | ||
1da177e4 LT |
5825 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5826 | static void tg3_poll_controller(struct net_device *dev) | |
5827 | { | |
4f125f42 | 5828 | int i; |
88b06bc2 MC |
5829 | struct tg3 *tp = netdev_priv(dev); |
5830 | ||
4f125f42 | 5831 | for (i = 0; i < tp->irq_cnt; i++) |
fe234f0e | 5832 | tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); |
1da177e4 LT |
5833 | } |
5834 | #endif | |
5835 | ||
c4028958 | 5836 | static void tg3_reset_task(struct work_struct *work) |
1da177e4 | 5837 | { |
c4028958 | 5838 | struct tg3 *tp = container_of(work, struct tg3, reset_task); |
b02fd9e3 | 5839 | int err; |
1da177e4 LT |
5840 | unsigned int restart_timer; |
5841 | ||
7faa006f | 5842 | tg3_full_lock(tp, 0); |
7faa006f MC |
5843 | |
5844 | if (!netif_running(tp->dev)) { | |
7faa006f MC |
5845 | tg3_full_unlock(tp); |
5846 | return; | |
5847 | } | |
5848 | ||
5849 | tg3_full_unlock(tp); | |
5850 | ||
b02fd9e3 MC |
5851 | tg3_phy_stop(tp); |
5852 | ||
1da177e4 LT |
5853 | tg3_netif_stop(tp); |
5854 | ||
f47c11ee | 5855 | tg3_full_lock(tp, 1); |
1da177e4 | 5856 | |
63c3a66f JP |
5857 | restart_timer = tg3_flag(tp, RESTART_TIMER); |
5858 | tg3_flag_clear(tp, RESTART_TIMER); | |
1da177e4 | 5859 | |
63c3a66f | 5860 | if (tg3_flag(tp, TX_RECOVERY_PENDING)) { |
df3e6548 MC |
5861 | tp->write32_tx_mbox = tg3_write32_tx_mbox; |
5862 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
63c3a66f JP |
5863 | tg3_flag_set(tp, MBOX_WRITE_REORDER); |
5864 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); | |
df3e6548 MC |
5865 | } |
5866 | ||
944d980e | 5867 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); |
b02fd9e3 MC |
5868 | err = tg3_init_hw(tp, 1); |
5869 | if (err) | |
b9ec6c1b | 5870 | goto out; |
1da177e4 LT |
5871 | |
5872 | tg3_netif_start(tp); | |
5873 | ||
1da177e4 LT |
5874 | if (restart_timer) |
5875 | mod_timer(&tp->timer, jiffies + 1); | |
7faa006f | 5876 | |
b9ec6c1b | 5877 | out: |
7faa006f | 5878 | tg3_full_unlock(tp); |
b02fd9e3 MC |
5879 | |
5880 | if (!err) | |
5881 | tg3_phy_start(tp); | |
1da177e4 LT |
5882 | } |
5883 | ||
5884 | static void tg3_tx_timeout(struct net_device *dev) | |
5885 | { | |
5886 | struct tg3 *tp = netdev_priv(dev); | |
5887 | ||
b0408751 | 5888 | if (netif_msg_tx_err(tp)) { |
05dbe005 | 5889 | netdev_err(dev, "transmit timed out, resetting\n"); |
97bd8e49 | 5890 | tg3_dump_state(tp); |
b0408751 | 5891 | } |
1da177e4 LT |
5892 | |
5893 | schedule_work(&tp->reset_task); | |
5894 | } | |
5895 | ||
c58ec932 MC |
5896 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ |
5897 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
5898 | { | |
5899 | u32 base = (u32) mapping & 0xffffffff; | |
5900 | ||
807540ba | 5901 | return (base > 0xffffdcc0) && (base + len + 8 < base); |
c58ec932 MC |
5902 | } |
5903 | ||
72f2afb8 MC |
5904 | /* Test for DMA addresses > 40-bit */ |
5905 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
5906 | int len) | |
5907 | { | |
5908 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
63c3a66f | 5909 | if (tg3_flag(tp, 40BIT_DMA_BUG)) |
807540ba | 5910 | return ((u64) mapping + len) > DMA_BIT_MASK(40); |
72f2afb8 MC |
5911 | return 0; |
5912 | #else | |
5913 | return 0; | |
5914 | #endif | |
5915 | } | |
5916 | ||
d1a3b737 | 5917 | static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd, |
92cd3a17 MC |
5918 | dma_addr_t mapping, u32 len, u32 flags, |
5919 | u32 mss, u32 vlan) | |
2ffcc981 | 5920 | { |
92cd3a17 MC |
5921 | txbd->addr_hi = ((u64) mapping >> 32); |
5922 | txbd->addr_lo = ((u64) mapping & 0xffffffff); | |
5923 | txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff); | |
5924 | txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT); | |
2ffcc981 | 5925 | } |
1da177e4 | 5926 | |
84b67b27 | 5927 | static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget, |
d1a3b737 MC |
5928 | dma_addr_t map, u32 len, u32 flags, |
5929 | u32 mss, u32 vlan) | |
5930 | { | |
5931 | struct tg3 *tp = tnapi->tp; | |
5932 | bool hwbug = false; | |
5933 | ||
5934 | if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) | |
5935 | hwbug = 1; | |
5936 | ||
5937 | if (tg3_4g_overflow_test(map, len)) | |
5938 | hwbug = 1; | |
5939 | ||
5940 | if (tg3_40bit_overflow_test(tp, map, len)) | |
5941 | hwbug = 1; | |
5942 | ||
e31aa987 MC |
5943 | if (tg3_flag(tp, 4K_FIFO_LIMIT)) { |
5944 | u32 tmp_flag = flags & ~TXD_FLAG_END; | |
5945 | while (len > TG3_TX_BD_DMA_MAX) { | |
5946 | u32 frag_len = TG3_TX_BD_DMA_MAX; | |
5947 | len -= TG3_TX_BD_DMA_MAX; | |
5948 | ||
5949 | if (len) { | |
5950 | tnapi->tx_buffers[*entry].fragmented = true; | |
5951 | /* Avoid the 8byte DMA problem */ | |
5952 | if (len <= 8) { | |
5953 | len += TG3_TX_BD_DMA_MAX / 2; | |
5954 | frag_len = TG3_TX_BD_DMA_MAX / 2; | |
5955 | } | |
5956 | } else | |
5957 | tmp_flag = flags; | |
5958 | ||
5959 | if (*budget) { | |
5960 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, | |
5961 | frag_len, tmp_flag, mss, vlan); | |
5962 | (*budget)--; | |
5963 | *entry = NEXT_TX(*entry); | |
5964 | } else { | |
5965 | hwbug = 1; | |
5966 | break; | |
5967 | } | |
5968 | ||
5969 | map += frag_len; | |
5970 | } | |
5971 | ||
5972 | if (len) { | |
5973 | if (*budget) { | |
5974 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, | |
5975 | len, flags, mss, vlan); | |
5976 | (*budget)--; | |
5977 | *entry = NEXT_TX(*entry); | |
5978 | } else { | |
5979 | hwbug = 1; | |
5980 | } | |
5981 | } | |
5982 | } else { | |
84b67b27 MC |
5983 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, |
5984 | len, flags, mss, vlan); | |
e31aa987 MC |
5985 | *entry = NEXT_TX(*entry); |
5986 | } | |
d1a3b737 MC |
5987 | |
5988 | return hwbug; | |
5989 | } | |
5990 | ||
0d681b27 | 5991 | static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last) |
432aa7ed MC |
5992 | { |
5993 | int i; | |
0d681b27 | 5994 | struct sk_buff *skb; |
df8944cf | 5995 | struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry]; |
432aa7ed | 5996 | |
0d681b27 MC |
5997 | skb = txb->skb; |
5998 | txb->skb = NULL; | |
5999 | ||
432aa7ed MC |
6000 | pci_unmap_single(tnapi->tp->pdev, |
6001 | dma_unmap_addr(txb, mapping), | |
6002 | skb_headlen(skb), | |
6003 | PCI_DMA_TODEVICE); | |
e01ee14d MC |
6004 | |
6005 | while (txb->fragmented) { | |
6006 | txb->fragmented = false; | |
6007 | entry = NEXT_TX(entry); | |
6008 | txb = &tnapi->tx_buffers[entry]; | |
6009 | } | |
6010 | ||
9a2e0fb0 | 6011 | for (i = 0; i < last; i++) { |
432aa7ed MC |
6012 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
6013 | ||
6014 | entry = NEXT_TX(entry); | |
6015 | txb = &tnapi->tx_buffers[entry]; | |
6016 | ||
6017 | pci_unmap_page(tnapi->tp->pdev, | |
6018 | dma_unmap_addr(txb, mapping), | |
6019 | frag->size, PCI_DMA_TODEVICE); | |
e01ee14d MC |
6020 | |
6021 | while (txb->fragmented) { | |
6022 | txb->fragmented = false; | |
6023 | entry = NEXT_TX(entry); | |
6024 | txb = &tnapi->tx_buffers[entry]; | |
6025 | } | |
432aa7ed MC |
6026 | } |
6027 | } | |
6028 | ||
72f2afb8 | 6029 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ |
24f4efd4 | 6030 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, |
432aa7ed | 6031 | struct sk_buff *skb, |
84b67b27 | 6032 | u32 *entry, u32 *budget, |
92cd3a17 | 6033 | u32 base_flags, u32 mss, u32 vlan) |
1da177e4 | 6034 | { |
24f4efd4 | 6035 | struct tg3 *tp = tnapi->tp; |
41588ba1 | 6036 | struct sk_buff *new_skb; |
c58ec932 | 6037 | dma_addr_t new_addr = 0; |
432aa7ed | 6038 | int ret = 0; |
1da177e4 | 6039 | |
41588ba1 MC |
6040 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
6041 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
6042 | else { | |
6043 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
6044 | ||
6045 | new_skb = skb_copy_expand(skb, | |
6046 | skb_headroom(skb) + more_headroom, | |
6047 | skb_tailroom(skb), GFP_ATOMIC); | |
6048 | } | |
6049 | ||
1da177e4 | 6050 | if (!new_skb) { |
c58ec932 MC |
6051 | ret = -1; |
6052 | } else { | |
6053 | /* New SKB is guaranteed to be linear. */ | |
f4188d8a AD |
6054 | new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, |
6055 | PCI_DMA_TODEVICE); | |
6056 | /* Make sure the mapping succeeded */ | |
6057 | if (pci_dma_mapping_error(tp->pdev, new_addr)) { | |
f4188d8a | 6058 | dev_kfree_skb(new_skb); |
c58ec932 | 6059 | ret = -1; |
c58ec932 | 6060 | } else { |
92cd3a17 MC |
6061 | base_flags |= TXD_FLAG_END; |
6062 | ||
84b67b27 MC |
6063 | tnapi->tx_buffers[*entry].skb = new_skb; |
6064 | dma_unmap_addr_set(&tnapi->tx_buffers[*entry], | |
432aa7ed MC |
6065 | mapping, new_addr); |
6066 | ||
84b67b27 | 6067 | if (tg3_tx_frag_set(tnapi, entry, budget, new_addr, |
d1a3b737 MC |
6068 | new_skb->len, base_flags, |
6069 | mss, vlan)) { | |
84b67b27 | 6070 | tg3_tx_skb_unmap(tnapi, *entry, 0); |
d1a3b737 MC |
6071 | dev_kfree_skb(new_skb); |
6072 | ret = -1; | |
6073 | } | |
f4188d8a | 6074 | } |
1da177e4 LT |
6075 | } |
6076 | ||
6077 | dev_kfree_skb(skb); | |
6078 | ||
c58ec932 | 6079 | return ret; |
1da177e4 LT |
6080 | } |
6081 | ||
2ffcc981 | 6082 | static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *); |
52c0fd83 MC |
6083 | |
6084 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
6085 | * TSO header is greater than 80 bytes. | |
6086 | */ | |
6087 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
6088 | { | |
6089 | struct sk_buff *segs, *nskb; | |
f3f3f27e | 6090 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; |
52c0fd83 MC |
6091 | |
6092 | /* Estimate the number of fragments in the worst case */ | |
f3f3f27e | 6093 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { |
52c0fd83 | 6094 | netif_stop_queue(tp->dev); |
f65aac16 MC |
6095 | |
6096 | /* netif_tx_stop_queue() must be done before checking | |
6097 | * checking tx index in tg3_tx_avail() below, because in | |
6098 | * tg3_tx(), we update tx index before checking for | |
6099 | * netif_tx_queue_stopped(). | |
6100 | */ | |
6101 | smp_mb(); | |
f3f3f27e | 6102 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) |
7f62ad5d MC |
6103 | return NETDEV_TX_BUSY; |
6104 | ||
6105 | netif_wake_queue(tp->dev); | |
52c0fd83 MC |
6106 | } |
6107 | ||
6108 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
801678c5 | 6109 | if (IS_ERR(segs)) |
52c0fd83 MC |
6110 | goto tg3_tso_bug_end; |
6111 | ||
6112 | do { | |
6113 | nskb = segs; | |
6114 | segs = segs->next; | |
6115 | nskb->next = NULL; | |
2ffcc981 | 6116 | tg3_start_xmit(nskb, tp->dev); |
52c0fd83 MC |
6117 | } while (segs); |
6118 | ||
6119 | tg3_tso_bug_end: | |
6120 | dev_kfree_skb(skb); | |
6121 | ||
6122 | return NETDEV_TX_OK; | |
6123 | } | |
52c0fd83 | 6124 | |
5a6f3074 | 6125 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and |
63c3a66f | 6126 | * support TG3_FLAG_HW_TSO_1 or firmware TSO only. |
5a6f3074 | 6127 | */ |
2ffcc981 | 6128 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 LT |
6129 | { |
6130 | struct tg3 *tp = netdev_priv(dev); | |
92cd3a17 | 6131 | u32 len, entry, base_flags, mss, vlan = 0; |
84b67b27 | 6132 | u32 budget; |
432aa7ed | 6133 | int i = -1, would_hit_hwbug; |
90079ce8 | 6134 | dma_addr_t mapping; |
24f4efd4 MC |
6135 | struct tg3_napi *tnapi; |
6136 | struct netdev_queue *txq; | |
432aa7ed | 6137 | unsigned int last; |
f4188d8a | 6138 | |
24f4efd4 MC |
6139 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
6140 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
63c3a66f | 6141 | if (tg3_flag(tp, ENABLE_TSS)) |
24f4efd4 | 6142 | tnapi++; |
1da177e4 | 6143 | |
84b67b27 MC |
6144 | budget = tg3_tx_avail(tnapi); |
6145 | ||
00b70504 | 6146 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 6147 | * and TX reclaim runs via tp->napi.poll inside of a software |
f47c11ee DM |
6148 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
6149 | * no IRQ context deadlocks to worry about either. Rejoice! | |
1da177e4 | 6150 | */ |
84b67b27 | 6151 | if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { |
24f4efd4 MC |
6152 | if (!netif_tx_queue_stopped(txq)) { |
6153 | netif_tx_stop_queue(txq); | |
1f064a87 SH |
6154 | |
6155 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
6156 | netdev_err(dev, |
6157 | "BUG! Tx Ring full when queue awake!\n"); | |
1f064a87 | 6158 | } |
1da177e4 LT |
6159 | return NETDEV_TX_BUSY; |
6160 | } | |
6161 | ||
f3f3f27e | 6162 | entry = tnapi->tx_prod; |
1da177e4 | 6163 | base_flags = 0; |
84fa7933 | 6164 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
1da177e4 | 6165 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
24f4efd4 | 6166 | |
be98da6a MC |
6167 | mss = skb_shinfo(skb)->gso_size; |
6168 | if (mss) { | |
eddc9ec5 | 6169 | struct iphdr *iph; |
34195c3d | 6170 | u32 tcp_opt_len, hdr_len; |
1da177e4 LT |
6171 | |
6172 | if (skb_header_cloned(skb) && | |
6173 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
6174 | dev_kfree_skb(skb); | |
6175 | goto out_unlock; | |
6176 | } | |
6177 | ||
34195c3d | 6178 | iph = ip_hdr(skb); |
ab6a5bb6 | 6179 | tcp_opt_len = tcp_optlen(skb); |
1da177e4 | 6180 | |
02e96080 | 6181 | if (skb_is_gso_v6(skb)) { |
34195c3d MC |
6182 | hdr_len = skb_headlen(skb) - ETH_HLEN; |
6183 | } else { | |
6184 | u32 ip_tcp_len; | |
6185 | ||
6186 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); | |
6187 | hdr_len = ip_tcp_len + tcp_opt_len; | |
6188 | ||
6189 | iph->check = 0; | |
6190 | iph->tot_len = htons(mss + hdr_len); | |
6191 | } | |
6192 | ||
52c0fd83 | 6193 | if (unlikely((ETH_HLEN + hdr_len) > 80) && |
63c3a66f | 6194 | tg3_flag(tp, TSO_BUG)) |
de6f31eb | 6195 | return tg3_tso_bug(tp, skb); |
52c0fd83 | 6196 | |
1da177e4 LT |
6197 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
6198 | TXD_FLAG_CPU_POST_DMA); | |
6199 | ||
63c3a66f JP |
6200 | if (tg3_flag(tp, HW_TSO_1) || |
6201 | tg3_flag(tp, HW_TSO_2) || | |
6202 | tg3_flag(tp, HW_TSO_3)) { | |
aa8223c7 | 6203 | tcp_hdr(skb)->check = 0; |
1da177e4 | 6204 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; |
aa8223c7 ACM |
6205 | } else |
6206 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
6207 | iph->daddr, 0, | |
6208 | IPPROTO_TCP, | |
6209 | 0); | |
1da177e4 | 6210 | |
63c3a66f | 6211 | if (tg3_flag(tp, HW_TSO_3)) { |
615774fe MC |
6212 | mss |= (hdr_len & 0xc) << 12; |
6213 | if (hdr_len & 0x10) | |
6214 | base_flags |= 0x00000010; | |
6215 | base_flags |= (hdr_len & 0x3e0) << 5; | |
63c3a66f | 6216 | } else if (tg3_flag(tp, HW_TSO_2)) |
92c6b8d1 | 6217 | mss |= hdr_len << 9; |
63c3a66f | 6218 | else if (tg3_flag(tp, HW_TSO_1) || |
92c6b8d1 | 6219 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
eddc9ec5 | 6220 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
6221 | int tsflags; |
6222 | ||
eddc9ec5 | 6223 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
6224 | mss |= (tsflags << 11); |
6225 | } | |
6226 | } else { | |
eddc9ec5 | 6227 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
6228 | int tsflags; |
6229 | ||
eddc9ec5 | 6230 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
6231 | base_flags |= tsflags << 12; |
6232 | } | |
6233 | } | |
6234 | } | |
bf933c80 | 6235 | |
92cd3a17 MC |
6236 | #ifdef BCM_KERNEL_SUPPORTS_8021Q |
6237 | if (vlan_tx_tag_present(skb)) { | |
6238 | base_flags |= TXD_FLAG_VLAN; | |
6239 | vlan = vlan_tx_tag_get(skb); | |
6240 | } | |
6241 | #endif | |
1da177e4 | 6242 | |
63c3a66f | 6243 | if (tg3_flag(tp, USE_JUMBO_BDFLAG) && |
8fc2f995 | 6244 | !mss && skb->len > VLAN_ETH_FRAME_LEN) |
615774fe MC |
6245 | base_flags |= TXD_FLAG_JMB_PKT; |
6246 | ||
f4188d8a AD |
6247 | len = skb_headlen(skb); |
6248 | ||
6249 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
6250 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
90079ce8 DM |
6251 | dev_kfree_skb(skb); |
6252 | goto out_unlock; | |
6253 | } | |
6254 | ||
f3f3f27e | 6255 | tnapi->tx_buffers[entry].skb = skb; |
4e5e4f0d | 6256 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
1da177e4 LT |
6257 | |
6258 | would_hit_hwbug = 0; | |
6259 | ||
63c3a66f | 6260 | if (tg3_flag(tp, 5701_DMA_BUG)) |
c58ec932 | 6261 | would_hit_hwbug = 1; |
1da177e4 | 6262 | |
84b67b27 | 6263 | if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags | |
d1a3b737 MC |
6264 | ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0), |
6265 | mss, vlan)) | |
6266 | would_hit_hwbug = 1; | |
1da177e4 | 6267 | |
1da177e4 LT |
6268 | /* Now loop through additional data fragments, and queue them. */ |
6269 | if (skb_shinfo(skb)->nr_frags > 0) { | |
92cd3a17 MC |
6270 | u32 tmp_mss = mss; |
6271 | ||
6272 | if (!tg3_flag(tp, HW_TSO_1) && | |
6273 | !tg3_flag(tp, HW_TSO_2) && | |
6274 | !tg3_flag(tp, HW_TSO_3)) | |
6275 | tmp_mss = 0; | |
6276 | ||
1da177e4 LT |
6277 | last = skb_shinfo(skb)->nr_frags - 1; |
6278 | for (i = 0; i <= last; i++) { | |
6279 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6280 | ||
6281 | len = frag->size; | |
f4188d8a AD |
6282 | mapping = pci_map_page(tp->pdev, |
6283 | frag->page, | |
6284 | frag->page_offset, | |
6285 | len, PCI_DMA_TODEVICE); | |
1da177e4 | 6286 | |
f3f3f27e | 6287 | tnapi->tx_buffers[entry].skb = NULL; |
4e5e4f0d | 6288 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a AD |
6289 | mapping); |
6290 | if (pci_dma_mapping_error(tp->pdev, mapping)) | |
6291 | goto dma_error; | |
1da177e4 | 6292 | |
84b67b27 MC |
6293 | if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, |
6294 | len, base_flags | | |
6295 | ((i == last) ? TXD_FLAG_END : 0), | |
d1a3b737 | 6296 | tmp_mss, vlan)) |
72f2afb8 | 6297 | would_hit_hwbug = 1; |
1da177e4 LT |
6298 | } |
6299 | } | |
6300 | ||
6301 | if (would_hit_hwbug) { | |
0d681b27 | 6302 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i); |
1da177e4 LT |
6303 | |
6304 | /* If the workaround fails due to memory/mapping | |
6305 | * failure, silently drop this packet. | |
6306 | */ | |
84b67b27 MC |
6307 | entry = tnapi->tx_prod; |
6308 | budget = tg3_tx_avail(tnapi); | |
6309 | if (tigon3_dma_hwbug_workaround(tnapi, skb, &entry, &budget, | |
6310 | base_flags, mss, vlan)) | |
1da177e4 | 6311 | goto out_unlock; |
1da177e4 LT |
6312 | } |
6313 | ||
d515b450 RC |
6314 | skb_tx_timestamp(skb); |
6315 | ||
1da177e4 | 6316 | /* Packets are ready, update Tx producer idx local and on card. */ |
24f4efd4 | 6317 | tw32_tx_mbox(tnapi->prodmbox, entry); |
1da177e4 | 6318 | |
f3f3f27e MC |
6319 | tnapi->tx_prod = entry; |
6320 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
24f4efd4 | 6321 | netif_tx_stop_queue(txq); |
f65aac16 MC |
6322 | |
6323 | /* netif_tx_stop_queue() must be done before checking | |
6324 | * checking tx index in tg3_tx_avail() below, because in | |
6325 | * tg3_tx(), we update tx index before checking for | |
6326 | * netif_tx_queue_stopped(). | |
6327 | */ | |
6328 | smp_mb(); | |
f3f3f27e | 6329 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
24f4efd4 | 6330 | netif_tx_wake_queue(txq); |
51b91468 | 6331 | } |
1da177e4 LT |
6332 | |
6333 | out_unlock: | |
cdd0db05 | 6334 | mmiowb(); |
1da177e4 LT |
6335 | |
6336 | return NETDEV_TX_OK; | |
f4188d8a AD |
6337 | |
6338 | dma_error: | |
0d681b27 | 6339 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i); |
f4188d8a | 6340 | dev_kfree_skb(skb); |
432aa7ed | 6341 | tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; |
f4188d8a | 6342 | return NETDEV_TX_OK; |
1da177e4 LT |
6343 | } |
6344 | ||
6e01b20b MC |
6345 | static void tg3_mac_loopback(struct tg3 *tp, bool enable) |
6346 | { | |
6347 | if (enable) { | |
6348 | tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | | |
6349 | MAC_MODE_PORT_MODE_MASK); | |
6350 | ||
6351 | tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; | |
6352 | ||
6353 | if (!tg3_flag(tp, 5705_PLUS)) | |
6354 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
6355 | ||
6356 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
6357 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
6358 | else | |
6359 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
6360 | } else { | |
6361 | tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; | |
6362 | ||
6363 | if (tg3_flag(tp, 5705_PLUS) || | |
6364 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || | |
6365 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
6366 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
6367 | } | |
6368 | ||
6369 | tw32(MAC_MODE, tp->mac_mode); | |
6370 | udelay(40); | |
6371 | } | |
6372 | ||
06c03c02 MB |
6373 | static void tg3_set_loopback(struct net_device *dev, u32 features) |
6374 | { | |
6375 | struct tg3 *tp = netdev_priv(dev); | |
6376 | ||
6377 | if (features & NETIF_F_LOOPBACK) { | |
6378 | if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) | |
6379 | return; | |
6380 | ||
06c03c02 | 6381 | spin_lock_bh(&tp->lock); |
6e01b20b | 6382 | tg3_mac_loopback(tp, true); |
06c03c02 MB |
6383 | netif_carrier_on(tp->dev); |
6384 | spin_unlock_bh(&tp->lock); | |
6385 | netdev_info(dev, "Internal MAC loopback mode enabled.\n"); | |
6386 | } else { | |
6387 | if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
6388 | return; | |
6389 | ||
06c03c02 | 6390 | spin_lock_bh(&tp->lock); |
6e01b20b | 6391 | tg3_mac_loopback(tp, false); |
06c03c02 MB |
6392 | /* Force link status check */ |
6393 | tg3_setup_phy(tp, 1); | |
6394 | spin_unlock_bh(&tp->lock); | |
6395 | netdev_info(dev, "Internal MAC loopback mode disabled.\n"); | |
6396 | } | |
6397 | } | |
6398 | ||
dc668910 MM |
6399 | static u32 tg3_fix_features(struct net_device *dev, u32 features) |
6400 | { | |
6401 | struct tg3 *tp = netdev_priv(dev); | |
6402 | ||
63c3a66f | 6403 | if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) |
dc668910 MM |
6404 | features &= ~NETIF_F_ALL_TSO; |
6405 | ||
6406 | return features; | |
6407 | } | |
6408 | ||
06c03c02 MB |
6409 | static int tg3_set_features(struct net_device *dev, u32 features) |
6410 | { | |
6411 | u32 changed = dev->features ^ features; | |
6412 | ||
6413 | if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) | |
6414 | tg3_set_loopback(dev, features); | |
6415 | ||
6416 | return 0; | |
6417 | } | |
6418 | ||
1da177e4 LT |
6419 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, |
6420 | int new_mtu) | |
6421 | { | |
6422 | dev->mtu = new_mtu; | |
6423 | ||
ef7f5ec0 | 6424 | if (new_mtu > ETH_DATA_LEN) { |
63c3a66f | 6425 | if (tg3_flag(tp, 5780_CLASS)) { |
dc668910 | 6426 | netdev_update_features(dev); |
63c3a66f | 6427 | tg3_flag_clear(tp, TSO_CAPABLE); |
859a5887 | 6428 | } else { |
63c3a66f | 6429 | tg3_flag_set(tp, JUMBO_RING_ENABLE); |
859a5887 | 6430 | } |
ef7f5ec0 | 6431 | } else { |
63c3a66f JP |
6432 | if (tg3_flag(tp, 5780_CLASS)) { |
6433 | tg3_flag_set(tp, TSO_CAPABLE); | |
dc668910 MM |
6434 | netdev_update_features(dev); |
6435 | } | |
63c3a66f | 6436 | tg3_flag_clear(tp, JUMBO_RING_ENABLE); |
ef7f5ec0 | 6437 | } |
1da177e4 LT |
6438 | } |
6439 | ||
6440 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
6441 | { | |
6442 | struct tg3 *tp = netdev_priv(dev); | |
b9ec6c1b | 6443 | int err; |
1da177e4 LT |
6444 | |
6445 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
6446 | return -EINVAL; | |
6447 | ||
6448 | if (!netif_running(dev)) { | |
6449 | /* We'll just catch it later when the | |
6450 | * device is up'd. | |
6451 | */ | |
6452 | tg3_set_mtu(dev, tp, new_mtu); | |
6453 | return 0; | |
6454 | } | |
6455 | ||
b02fd9e3 MC |
6456 | tg3_phy_stop(tp); |
6457 | ||
1da177e4 | 6458 | tg3_netif_stop(tp); |
f47c11ee DM |
6459 | |
6460 | tg3_full_lock(tp, 1); | |
1da177e4 | 6461 | |
944d980e | 6462 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
6463 | |
6464 | tg3_set_mtu(dev, tp, new_mtu); | |
6465 | ||
b9ec6c1b | 6466 | err = tg3_restart_hw(tp, 0); |
1da177e4 | 6467 | |
b9ec6c1b MC |
6468 | if (!err) |
6469 | tg3_netif_start(tp); | |
1da177e4 | 6470 | |
f47c11ee | 6471 | tg3_full_unlock(tp); |
1da177e4 | 6472 | |
b02fd9e3 MC |
6473 | if (!err) |
6474 | tg3_phy_start(tp); | |
6475 | ||
b9ec6c1b | 6476 | return err; |
1da177e4 LT |
6477 | } |
6478 | ||
21f581a5 MC |
6479 | static void tg3_rx_prodring_free(struct tg3 *tp, |
6480 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6481 | { |
1da177e4 LT |
6482 | int i; |
6483 | ||
8fea32b9 | 6484 | if (tpr != &tp->napi[0].prodring) { |
b196c7e4 | 6485 | for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; |
2c49a44d | 6486 | i = (i + 1) & tp->rx_std_ring_mask) |
b196c7e4 MC |
6487 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], |
6488 | tp->rx_pkt_map_sz); | |
6489 | ||
63c3a66f | 6490 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
b196c7e4 MC |
6491 | for (i = tpr->rx_jmb_cons_idx; |
6492 | i != tpr->rx_jmb_prod_idx; | |
2c49a44d | 6493 | i = (i + 1) & tp->rx_jmb_ring_mask) { |
b196c7e4 MC |
6494 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], |
6495 | TG3_RX_JMB_MAP_SZ); | |
6496 | } | |
6497 | } | |
6498 | ||
2b2cdb65 | 6499 | return; |
b196c7e4 | 6500 | } |
1da177e4 | 6501 | |
2c49a44d | 6502 | for (i = 0; i <= tp->rx_std_ring_mask; i++) |
2b2cdb65 MC |
6503 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], |
6504 | tp->rx_pkt_map_sz); | |
1da177e4 | 6505 | |
63c3a66f | 6506 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
2c49a44d | 6507 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) |
2b2cdb65 MC |
6508 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], |
6509 | TG3_RX_JMB_MAP_SZ); | |
1da177e4 LT |
6510 | } |
6511 | } | |
6512 | ||
c6cdf436 | 6513 | /* Initialize rx rings for packet processing. |
1da177e4 LT |
6514 | * |
6515 | * The chip has been shut down and the driver detached from | |
6516 | * the networking, so no interrupts or new tx packets will | |
6517 | * end up in the driver. tp->{tx,}lock are held and thus | |
6518 | * we may not sleep. | |
6519 | */ | |
21f581a5 MC |
6520 | static int tg3_rx_prodring_alloc(struct tg3 *tp, |
6521 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6522 | { |
287be12e | 6523 | u32 i, rx_pkt_dma_sz; |
1da177e4 | 6524 | |
b196c7e4 MC |
6525 | tpr->rx_std_cons_idx = 0; |
6526 | tpr->rx_std_prod_idx = 0; | |
6527 | tpr->rx_jmb_cons_idx = 0; | |
6528 | tpr->rx_jmb_prod_idx = 0; | |
6529 | ||
8fea32b9 | 6530 | if (tpr != &tp->napi[0].prodring) { |
2c49a44d MC |
6531 | memset(&tpr->rx_std_buffers[0], 0, |
6532 | TG3_RX_STD_BUFF_RING_SIZE(tp)); | |
48035728 | 6533 | if (tpr->rx_jmb_buffers) |
2b2cdb65 | 6534 | memset(&tpr->rx_jmb_buffers[0], 0, |
2c49a44d | 6535 | TG3_RX_JMB_BUFF_RING_SIZE(tp)); |
2b2cdb65 MC |
6536 | goto done; |
6537 | } | |
6538 | ||
1da177e4 | 6539 | /* Zero out all descriptors. */ |
2c49a44d | 6540 | memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); |
1da177e4 | 6541 | |
287be12e | 6542 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; |
63c3a66f | 6543 | if (tg3_flag(tp, 5780_CLASS) && |
287be12e MC |
6544 | tp->dev->mtu > ETH_DATA_LEN) |
6545 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
6546 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
7e72aad4 | 6547 | |
1da177e4 LT |
6548 | /* Initialize invariants of the rings, we only set this |
6549 | * stuff once. This works because the card does not | |
6550 | * write into the rx buffer posting rings. | |
6551 | */ | |
2c49a44d | 6552 | for (i = 0; i <= tp->rx_std_ring_mask; i++) { |
1da177e4 LT |
6553 | struct tg3_rx_buffer_desc *rxd; |
6554 | ||
21f581a5 | 6555 | rxd = &tpr->rx_std[i]; |
287be12e | 6556 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; |
1da177e4 LT |
6557 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); |
6558 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
6559 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6560 | } | |
6561 | ||
1da177e4 LT |
6562 | /* Now allocate fresh SKBs for each rx ring. */ |
6563 | for (i = 0; i < tp->rx_pending; i++) { | |
86b21e59 | 6564 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) { |
5129c3a3 MC |
6565 | netdev_warn(tp->dev, |
6566 | "Using a smaller RX standard ring. Only " | |
6567 | "%d out of %d buffers were allocated " | |
6568 | "successfully\n", i, tp->rx_pending); | |
32d8c572 | 6569 | if (i == 0) |
cf7a7298 | 6570 | goto initfail; |
32d8c572 | 6571 | tp->rx_pending = i; |
1da177e4 | 6572 | break; |
32d8c572 | 6573 | } |
1da177e4 LT |
6574 | } |
6575 | ||
63c3a66f | 6576 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
cf7a7298 MC |
6577 | goto done; |
6578 | ||
2c49a44d | 6579 | memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); |
cf7a7298 | 6580 | |
63c3a66f | 6581 | if (!tg3_flag(tp, JUMBO_RING_ENABLE)) |
0d86df80 | 6582 | goto done; |
cf7a7298 | 6583 | |
2c49a44d | 6584 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { |
0d86df80 MC |
6585 | struct tg3_rx_buffer_desc *rxd; |
6586 | ||
6587 | rxd = &tpr->rx_jmb[i].std; | |
6588 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; | |
6589 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
6590 | RXD_FLAG_JUMBO; | |
6591 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
6592 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6593 | } | |
6594 | ||
6595 | for (i = 0; i < tp->rx_jumbo_pending; i++) { | |
6596 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) { | |
5129c3a3 MC |
6597 | netdev_warn(tp->dev, |
6598 | "Using a smaller RX jumbo ring. Only %d " | |
6599 | "out of %d buffers were allocated " | |
6600 | "successfully\n", i, tp->rx_jumbo_pending); | |
0d86df80 MC |
6601 | if (i == 0) |
6602 | goto initfail; | |
6603 | tp->rx_jumbo_pending = i; | |
6604 | break; | |
1da177e4 LT |
6605 | } |
6606 | } | |
cf7a7298 MC |
6607 | |
6608 | done: | |
32d8c572 | 6609 | return 0; |
cf7a7298 MC |
6610 | |
6611 | initfail: | |
21f581a5 | 6612 | tg3_rx_prodring_free(tp, tpr); |
cf7a7298 | 6613 | return -ENOMEM; |
1da177e4 LT |
6614 | } |
6615 | ||
21f581a5 MC |
6616 | static void tg3_rx_prodring_fini(struct tg3 *tp, |
6617 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6618 | { |
21f581a5 MC |
6619 | kfree(tpr->rx_std_buffers); |
6620 | tpr->rx_std_buffers = NULL; | |
6621 | kfree(tpr->rx_jmb_buffers); | |
6622 | tpr->rx_jmb_buffers = NULL; | |
6623 | if (tpr->rx_std) { | |
4bae65c8 MC |
6624 | dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), |
6625 | tpr->rx_std, tpr->rx_std_mapping); | |
21f581a5 | 6626 | tpr->rx_std = NULL; |
1da177e4 | 6627 | } |
21f581a5 | 6628 | if (tpr->rx_jmb) { |
4bae65c8 MC |
6629 | dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), |
6630 | tpr->rx_jmb, tpr->rx_jmb_mapping); | |
21f581a5 | 6631 | tpr->rx_jmb = NULL; |
1da177e4 | 6632 | } |
cf7a7298 MC |
6633 | } |
6634 | ||
21f581a5 MC |
6635 | static int tg3_rx_prodring_init(struct tg3 *tp, |
6636 | struct tg3_rx_prodring_set *tpr) | |
cf7a7298 | 6637 | { |
2c49a44d MC |
6638 | tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), |
6639 | GFP_KERNEL); | |
21f581a5 | 6640 | if (!tpr->rx_std_buffers) |
cf7a7298 MC |
6641 | return -ENOMEM; |
6642 | ||
4bae65c8 MC |
6643 | tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, |
6644 | TG3_RX_STD_RING_BYTES(tp), | |
6645 | &tpr->rx_std_mapping, | |
6646 | GFP_KERNEL); | |
21f581a5 | 6647 | if (!tpr->rx_std) |
cf7a7298 MC |
6648 | goto err_out; |
6649 | ||
63c3a66f | 6650 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
2c49a44d | 6651 | tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), |
21f581a5 MC |
6652 | GFP_KERNEL); |
6653 | if (!tpr->rx_jmb_buffers) | |
cf7a7298 MC |
6654 | goto err_out; |
6655 | ||
4bae65c8 MC |
6656 | tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, |
6657 | TG3_RX_JMB_RING_BYTES(tp), | |
6658 | &tpr->rx_jmb_mapping, | |
6659 | GFP_KERNEL); | |
21f581a5 | 6660 | if (!tpr->rx_jmb) |
cf7a7298 MC |
6661 | goto err_out; |
6662 | } | |
6663 | ||
6664 | return 0; | |
6665 | ||
6666 | err_out: | |
21f581a5 | 6667 | tg3_rx_prodring_fini(tp, tpr); |
cf7a7298 MC |
6668 | return -ENOMEM; |
6669 | } | |
6670 | ||
6671 | /* Free up pending packets in all rx/tx rings. | |
6672 | * | |
6673 | * The chip has been shut down and the driver detached from | |
6674 | * the networking, so no interrupts or new tx packets will | |
6675 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
6676 | * in an interrupt context and thus may sleep. | |
6677 | */ | |
6678 | static void tg3_free_rings(struct tg3 *tp) | |
6679 | { | |
f77a6a8e | 6680 | int i, j; |
cf7a7298 | 6681 | |
f77a6a8e MC |
6682 | for (j = 0; j < tp->irq_cnt; j++) { |
6683 | struct tg3_napi *tnapi = &tp->napi[j]; | |
cf7a7298 | 6684 | |
8fea32b9 | 6685 | tg3_rx_prodring_free(tp, &tnapi->prodring); |
b28f6428 | 6686 | |
0c1d0e2b MC |
6687 | if (!tnapi->tx_buffers) |
6688 | continue; | |
6689 | ||
0d681b27 MC |
6690 | for (i = 0; i < TG3_TX_RING_SIZE; i++) { |
6691 | struct sk_buff *skb = tnapi->tx_buffers[i].skb; | |
cf7a7298 | 6692 | |
0d681b27 | 6693 | if (!skb) |
f77a6a8e | 6694 | continue; |
cf7a7298 | 6695 | |
0d681b27 | 6696 | tg3_tx_skb_unmap(tnapi, i, skb_shinfo(skb)->nr_frags); |
f77a6a8e MC |
6697 | |
6698 | dev_kfree_skb_any(skb); | |
6699 | } | |
2b2cdb65 | 6700 | } |
cf7a7298 MC |
6701 | } |
6702 | ||
6703 | /* Initialize tx/rx rings for packet processing. | |
6704 | * | |
6705 | * The chip has been shut down and the driver detached from | |
6706 | * the networking, so no interrupts or new tx packets will | |
6707 | * end up in the driver. tp->{tx,}lock are held and thus | |
6708 | * we may not sleep. | |
6709 | */ | |
6710 | static int tg3_init_rings(struct tg3 *tp) | |
6711 | { | |
f77a6a8e | 6712 | int i; |
72334482 | 6713 | |
cf7a7298 MC |
6714 | /* Free up all the SKBs. */ |
6715 | tg3_free_rings(tp); | |
6716 | ||
f77a6a8e MC |
6717 | for (i = 0; i < tp->irq_cnt; i++) { |
6718 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6719 | ||
6720 | tnapi->last_tag = 0; | |
6721 | tnapi->last_irq_tag = 0; | |
6722 | tnapi->hw_status->status = 0; | |
6723 | tnapi->hw_status->status_tag = 0; | |
6724 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
cf7a7298 | 6725 | |
f77a6a8e MC |
6726 | tnapi->tx_prod = 0; |
6727 | tnapi->tx_cons = 0; | |
0c1d0e2b MC |
6728 | if (tnapi->tx_ring) |
6729 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); | |
f77a6a8e MC |
6730 | |
6731 | tnapi->rx_rcb_ptr = 0; | |
0c1d0e2b MC |
6732 | if (tnapi->rx_rcb) |
6733 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
2b2cdb65 | 6734 | |
8fea32b9 | 6735 | if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { |
e4af1af9 | 6736 | tg3_free_rings(tp); |
2b2cdb65 | 6737 | return -ENOMEM; |
e4af1af9 | 6738 | } |
f77a6a8e | 6739 | } |
72334482 | 6740 | |
2b2cdb65 | 6741 | return 0; |
cf7a7298 MC |
6742 | } |
6743 | ||
6744 | /* | |
6745 | * Must not be invoked with interrupt sources disabled and | |
6746 | * the hardware shutdown down. | |
6747 | */ | |
6748 | static void tg3_free_consistent(struct tg3 *tp) | |
6749 | { | |
f77a6a8e | 6750 | int i; |
898a56f8 | 6751 | |
f77a6a8e MC |
6752 | for (i = 0; i < tp->irq_cnt; i++) { |
6753 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6754 | ||
6755 | if (tnapi->tx_ring) { | |
4bae65c8 | 6756 | dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, |
f77a6a8e MC |
6757 | tnapi->tx_ring, tnapi->tx_desc_mapping); |
6758 | tnapi->tx_ring = NULL; | |
6759 | } | |
6760 | ||
6761 | kfree(tnapi->tx_buffers); | |
6762 | tnapi->tx_buffers = NULL; | |
6763 | ||
6764 | if (tnapi->rx_rcb) { | |
4bae65c8 MC |
6765 | dma_free_coherent(&tp->pdev->dev, |
6766 | TG3_RX_RCB_RING_BYTES(tp), | |
6767 | tnapi->rx_rcb, | |
6768 | tnapi->rx_rcb_mapping); | |
f77a6a8e MC |
6769 | tnapi->rx_rcb = NULL; |
6770 | } | |
6771 | ||
8fea32b9 MC |
6772 | tg3_rx_prodring_fini(tp, &tnapi->prodring); |
6773 | ||
f77a6a8e | 6774 | if (tnapi->hw_status) { |
4bae65c8 MC |
6775 | dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, |
6776 | tnapi->hw_status, | |
6777 | tnapi->status_mapping); | |
f77a6a8e MC |
6778 | tnapi->hw_status = NULL; |
6779 | } | |
1da177e4 | 6780 | } |
f77a6a8e | 6781 | |
1da177e4 | 6782 | if (tp->hw_stats) { |
4bae65c8 MC |
6783 | dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), |
6784 | tp->hw_stats, tp->stats_mapping); | |
1da177e4 LT |
6785 | tp->hw_stats = NULL; |
6786 | } | |
6787 | } | |
6788 | ||
6789 | /* | |
6790 | * Must not be invoked with interrupt sources disabled and | |
6791 | * the hardware shutdown down. Can sleep. | |
6792 | */ | |
6793 | static int tg3_alloc_consistent(struct tg3 *tp) | |
6794 | { | |
f77a6a8e | 6795 | int i; |
898a56f8 | 6796 | |
4bae65c8 MC |
6797 | tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, |
6798 | sizeof(struct tg3_hw_stats), | |
6799 | &tp->stats_mapping, | |
6800 | GFP_KERNEL); | |
f77a6a8e | 6801 | if (!tp->hw_stats) |
1da177e4 LT |
6802 | goto err_out; |
6803 | ||
f77a6a8e | 6804 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
1da177e4 | 6805 | |
f77a6a8e MC |
6806 | for (i = 0; i < tp->irq_cnt; i++) { |
6807 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8d9d7cfc | 6808 | struct tg3_hw_status *sblk; |
1da177e4 | 6809 | |
4bae65c8 MC |
6810 | tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, |
6811 | TG3_HW_STATUS_SIZE, | |
6812 | &tnapi->status_mapping, | |
6813 | GFP_KERNEL); | |
f77a6a8e MC |
6814 | if (!tnapi->hw_status) |
6815 | goto err_out; | |
898a56f8 | 6816 | |
f77a6a8e | 6817 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
8d9d7cfc MC |
6818 | sblk = tnapi->hw_status; |
6819 | ||
8fea32b9 MC |
6820 | if (tg3_rx_prodring_init(tp, &tnapi->prodring)) |
6821 | goto err_out; | |
6822 | ||
19cfaecc MC |
6823 | /* If multivector TSS is enabled, vector 0 does not handle |
6824 | * tx interrupts. Don't allocate any resources for it. | |
6825 | */ | |
63c3a66f JP |
6826 | if ((!i && !tg3_flag(tp, ENABLE_TSS)) || |
6827 | (i && tg3_flag(tp, ENABLE_TSS))) { | |
df8944cf MC |
6828 | tnapi->tx_buffers = kzalloc( |
6829 | sizeof(struct tg3_tx_ring_info) * | |
6830 | TG3_TX_RING_SIZE, GFP_KERNEL); | |
19cfaecc MC |
6831 | if (!tnapi->tx_buffers) |
6832 | goto err_out; | |
6833 | ||
4bae65c8 MC |
6834 | tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, |
6835 | TG3_TX_RING_BYTES, | |
6836 | &tnapi->tx_desc_mapping, | |
6837 | GFP_KERNEL); | |
19cfaecc MC |
6838 | if (!tnapi->tx_ring) |
6839 | goto err_out; | |
6840 | } | |
6841 | ||
8d9d7cfc MC |
6842 | /* |
6843 | * When RSS is enabled, the status block format changes | |
6844 | * slightly. The "rx_jumbo_consumer", "reserved", | |
6845 | * and "rx_mini_consumer" members get mapped to the | |
6846 | * other three rx return ring producer indexes. | |
6847 | */ | |
6848 | switch (i) { | |
6849 | default: | |
6850 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; | |
6851 | break; | |
6852 | case 2: | |
6853 | tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer; | |
6854 | break; | |
6855 | case 3: | |
6856 | tnapi->rx_rcb_prod_idx = &sblk->reserved; | |
6857 | break; | |
6858 | case 4: | |
6859 | tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer; | |
6860 | break; | |
6861 | } | |
72334482 | 6862 | |
0c1d0e2b MC |
6863 | /* |
6864 | * If multivector RSS is enabled, vector 0 does not handle | |
6865 | * rx or tx interrupts. Don't allocate any resources for it. | |
6866 | */ | |
63c3a66f | 6867 | if (!i && tg3_flag(tp, ENABLE_RSS)) |
0c1d0e2b MC |
6868 | continue; |
6869 | ||
4bae65c8 MC |
6870 | tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, |
6871 | TG3_RX_RCB_RING_BYTES(tp), | |
6872 | &tnapi->rx_rcb_mapping, | |
6873 | GFP_KERNEL); | |
f77a6a8e MC |
6874 | if (!tnapi->rx_rcb) |
6875 | goto err_out; | |
72334482 | 6876 | |
f77a6a8e | 6877 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); |
f77a6a8e | 6878 | } |
1da177e4 LT |
6879 | |
6880 | return 0; | |
6881 | ||
6882 | err_out: | |
6883 | tg3_free_consistent(tp); | |
6884 | return -ENOMEM; | |
6885 | } | |
6886 | ||
6887 | #define MAX_WAIT_CNT 1000 | |
6888 | ||
6889 | /* To stop a block, clear the enable bit and poll till it | |
6890 | * clears. tp->lock is held. | |
6891 | */ | |
b3b7d6be | 6892 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) |
1da177e4 LT |
6893 | { |
6894 | unsigned int i; | |
6895 | u32 val; | |
6896 | ||
63c3a66f | 6897 | if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
6898 | switch (ofs) { |
6899 | case RCVLSC_MODE: | |
6900 | case DMAC_MODE: | |
6901 | case MBFREE_MODE: | |
6902 | case BUFMGR_MODE: | |
6903 | case MEMARB_MODE: | |
6904 | /* We can't enable/disable these bits of the | |
6905 | * 5705/5750, just say success. | |
6906 | */ | |
6907 | return 0; | |
6908 | ||
6909 | default: | |
6910 | break; | |
855e1111 | 6911 | } |
1da177e4 LT |
6912 | } |
6913 | ||
6914 | val = tr32(ofs); | |
6915 | val &= ~enable_bit; | |
6916 | tw32_f(ofs, val); | |
6917 | ||
6918 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6919 | udelay(100); | |
6920 | val = tr32(ofs); | |
6921 | if ((val & enable_bit) == 0) | |
6922 | break; | |
6923 | } | |
6924 | ||
b3b7d6be | 6925 | if (i == MAX_WAIT_CNT && !silent) { |
2445e461 MC |
6926 | dev_err(&tp->pdev->dev, |
6927 | "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", | |
6928 | ofs, enable_bit); | |
1da177e4 LT |
6929 | return -ENODEV; |
6930 | } | |
6931 | ||
6932 | return 0; | |
6933 | } | |
6934 | ||
6935 | /* tp->lock is held. */ | |
b3b7d6be | 6936 | static int tg3_abort_hw(struct tg3 *tp, int silent) |
1da177e4 LT |
6937 | { |
6938 | int i, err; | |
6939 | ||
6940 | tg3_disable_ints(tp); | |
6941 | ||
6942 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
6943 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
6944 | udelay(10); | |
6945 | ||
b3b7d6be DM |
6946 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); |
6947 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
6948 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
6949 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
6950 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
6951 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
6952 | ||
6953 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
6954 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
6955 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
6956 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
6957 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
6958 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
6959 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
1da177e4 LT |
6960 | |
6961 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
6962 | tw32_f(MAC_MODE, tp->mac_mode); | |
6963 | udelay(40); | |
6964 | ||
6965 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
6966 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
6967 | ||
6968 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6969 | udelay(100); | |
6970 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
6971 | break; | |
6972 | } | |
6973 | if (i >= MAX_WAIT_CNT) { | |
ab96b241 MC |
6974 | dev_err(&tp->pdev->dev, |
6975 | "%s timed out, TX_MODE_ENABLE will not clear " | |
6976 | "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); | |
e6de8ad1 | 6977 | err |= -ENODEV; |
1da177e4 LT |
6978 | } |
6979 | ||
e6de8ad1 | 6980 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); |
b3b7d6be DM |
6981 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); |
6982 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
1da177e4 LT |
6983 | |
6984 | tw32(FTQ_RESET, 0xffffffff); | |
6985 | tw32(FTQ_RESET, 0x00000000); | |
6986 | ||
b3b7d6be DM |
6987 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); |
6988 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
1da177e4 | 6989 | |
f77a6a8e MC |
6990 | for (i = 0; i < tp->irq_cnt; i++) { |
6991 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6992 | if (tnapi->hw_status) | |
6993 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
6994 | } | |
1da177e4 LT |
6995 | if (tp->hw_stats) |
6996 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
6997 | ||
1da177e4 LT |
6998 | return err; |
6999 | } | |
7000 | ||
0d3031d9 MC |
7001 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) |
7002 | { | |
7003 | int i; | |
7004 | u32 apedata; | |
7005 | ||
dc6d0744 | 7006 | /* NCSI does not support APE events */ |
63c3a66f | 7007 | if (tg3_flag(tp, APE_HAS_NCSI)) |
dc6d0744 MC |
7008 | return; |
7009 | ||
0d3031d9 MC |
7010 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); |
7011 | if (apedata != APE_SEG_SIG_MAGIC) | |
7012 | return; | |
7013 | ||
7014 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
731fd79c | 7015 | if (!(apedata & APE_FW_STATUS_READY)) |
0d3031d9 MC |
7016 | return; |
7017 | ||
7018 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
7019 | for (i = 0; i < 10; i++) { | |
7020 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
7021 | return; | |
7022 | ||
7023 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
7024 | ||
7025 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
7026 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, | |
7027 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
7028 | ||
7029 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
7030 | ||
7031 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
7032 | break; | |
7033 | ||
7034 | udelay(100); | |
7035 | } | |
7036 | ||
7037 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
7038 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
7039 | } | |
7040 | ||
7041 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
7042 | { | |
7043 | u32 event; | |
7044 | u32 apedata; | |
7045 | ||
63c3a66f | 7046 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
7047 | return; |
7048 | ||
7049 | switch (kind) { | |
33f401ae MC |
7050 | case RESET_KIND_INIT: |
7051 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
7052 | APE_HOST_SEG_SIG_MAGIC); | |
7053 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
7054 | APE_HOST_SEG_LEN_MAGIC); | |
7055 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
7056 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
7057 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
6867c843 | 7058 | APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM)); |
33f401ae MC |
7059 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, |
7060 | APE_HOST_BEHAV_NO_PHYLOCK); | |
dc6d0744 MC |
7061 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, |
7062 | TG3_APE_HOST_DRVR_STATE_START); | |
33f401ae MC |
7063 | |
7064 | event = APE_EVENT_STATUS_STATE_START; | |
7065 | break; | |
7066 | case RESET_KIND_SHUTDOWN: | |
7067 | /* With the interface we are currently using, | |
7068 | * APE does not track driver state. Wiping | |
7069 | * out the HOST SEGMENT SIGNATURE forces | |
7070 | * the APE to assume OS absent status. | |
7071 | */ | |
7072 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
b2aee154 | 7073 | |
dc6d0744 | 7074 | if (device_may_wakeup(&tp->pdev->dev) && |
63c3a66f | 7075 | tg3_flag(tp, WOL_ENABLE)) { |
dc6d0744 MC |
7076 | tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, |
7077 | TG3_APE_HOST_WOL_SPEED_AUTO); | |
7078 | apedata = TG3_APE_HOST_DRVR_STATE_WOL; | |
7079 | } else | |
7080 | apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD; | |
7081 | ||
7082 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); | |
7083 | ||
33f401ae MC |
7084 | event = APE_EVENT_STATUS_STATE_UNLOAD; |
7085 | break; | |
7086 | case RESET_KIND_SUSPEND: | |
7087 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
7088 | break; | |
7089 | default: | |
7090 | return; | |
0d3031d9 MC |
7091 | } |
7092 | ||
7093 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
7094 | ||
7095 | tg3_ape_send_event(tp, event); | |
7096 | } | |
7097 | ||
1da177e4 LT |
7098 | /* tp->lock is held. */ |
7099 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
7100 | { | |
f49639e6 DM |
7101 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, |
7102 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
1da177e4 | 7103 | |
63c3a66f | 7104 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { |
1da177e4 LT |
7105 | switch (kind) { |
7106 | case RESET_KIND_INIT: | |
7107 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7108 | DRV_STATE_START); | |
7109 | break; | |
7110 | ||
7111 | case RESET_KIND_SHUTDOWN: | |
7112 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7113 | DRV_STATE_UNLOAD); | |
7114 | break; | |
7115 | ||
7116 | case RESET_KIND_SUSPEND: | |
7117 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7118 | DRV_STATE_SUSPEND); | |
7119 | break; | |
7120 | ||
7121 | default: | |
7122 | break; | |
855e1111 | 7123 | } |
1da177e4 | 7124 | } |
0d3031d9 MC |
7125 | |
7126 | if (kind == RESET_KIND_INIT || | |
7127 | kind == RESET_KIND_SUSPEND) | |
7128 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
7129 | } |
7130 | ||
7131 | /* tp->lock is held. */ | |
7132 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
7133 | { | |
63c3a66f | 7134 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { |
1da177e4 LT |
7135 | switch (kind) { |
7136 | case RESET_KIND_INIT: | |
7137 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7138 | DRV_STATE_START_DONE); | |
7139 | break; | |
7140 | ||
7141 | case RESET_KIND_SHUTDOWN: | |
7142 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7143 | DRV_STATE_UNLOAD_DONE); | |
7144 | break; | |
7145 | ||
7146 | default: | |
7147 | break; | |
855e1111 | 7148 | } |
1da177e4 | 7149 | } |
0d3031d9 MC |
7150 | |
7151 | if (kind == RESET_KIND_SHUTDOWN) | |
7152 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
7153 | } |
7154 | ||
7155 | /* tp->lock is held. */ | |
7156 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
7157 | { | |
63c3a66f | 7158 | if (tg3_flag(tp, ENABLE_ASF)) { |
1da177e4 LT |
7159 | switch (kind) { |
7160 | case RESET_KIND_INIT: | |
7161 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7162 | DRV_STATE_START); | |
7163 | break; | |
7164 | ||
7165 | case RESET_KIND_SHUTDOWN: | |
7166 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7167 | DRV_STATE_UNLOAD); | |
7168 | break; | |
7169 | ||
7170 | case RESET_KIND_SUSPEND: | |
7171 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7172 | DRV_STATE_SUSPEND); | |
7173 | break; | |
7174 | ||
7175 | default: | |
7176 | break; | |
855e1111 | 7177 | } |
1da177e4 LT |
7178 | } |
7179 | } | |
7180 | ||
7a6f4369 MC |
7181 | static int tg3_poll_fw(struct tg3 *tp) |
7182 | { | |
7183 | int i; | |
7184 | u32 val; | |
7185 | ||
b5d3772c | 7186 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
0ccead18 GZ |
7187 | /* Wait up to 20ms for init done. */ |
7188 | for (i = 0; i < 200; i++) { | |
b5d3772c MC |
7189 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) |
7190 | return 0; | |
0ccead18 | 7191 | udelay(100); |
b5d3772c MC |
7192 | } |
7193 | return -ENODEV; | |
7194 | } | |
7195 | ||
7a6f4369 MC |
7196 | /* Wait for firmware initialization to complete. */ |
7197 | for (i = 0; i < 100000; i++) { | |
7198 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
7199 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
7200 | break; | |
7201 | udelay(10); | |
7202 | } | |
7203 | ||
7204 | /* Chip might not be fitted with firmware. Some Sun onboard | |
7205 | * parts are configured like that. So don't signal the timeout | |
7206 | * of the above loop as an error, but do report the lack of | |
7207 | * running firmware once. | |
7208 | */ | |
63c3a66f JP |
7209 | if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { |
7210 | tg3_flag_set(tp, NO_FWARE_REPORTED); | |
7a6f4369 | 7211 | |
05dbe005 | 7212 | netdev_info(tp->dev, "No firmware running\n"); |
7a6f4369 MC |
7213 | } |
7214 | ||
6b10c165 MC |
7215 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { |
7216 | /* The 57765 A0 needs a little more | |
7217 | * time to do some important work. | |
7218 | */ | |
7219 | mdelay(10); | |
7220 | } | |
7221 | ||
7a6f4369 MC |
7222 | return 0; |
7223 | } | |
7224 | ||
ee6a99b5 MC |
7225 | /* Save PCI command register before chip reset */ |
7226 | static void tg3_save_pci_state(struct tg3 *tp) | |
7227 | { | |
8a6eac90 | 7228 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); |
ee6a99b5 MC |
7229 | } |
7230 | ||
7231 | /* Restore PCI state after chip reset */ | |
7232 | static void tg3_restore_pci_state(struct tg3 *tp) | |
7233 | { | |
7234 | u32 val; | |
7235 | ||
7236 | /* Re-enable indirect register accesses. */ | |
7237 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
7238 | tp->misc_host_ctrl); | |
7239 | ||
7240 | /* Set MAX PCI retry to zero. */ | |
7241 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
7242 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
63c3a66f | 7243 | tg3_flag(tp, PCIX_MODE)) |
ee6a99b5 | 7244 | val |= PCISTATE_RETRY_SAME_DMA; |
0d3031d9 | 7245 | /* Allow reads and writes to the APE register and memory space. */ |
63c3a66f | 7246 | if (tg3_flag(tp, ENABLE_APE)) |
0d3031d9 | 7247 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | |
f92d9dc1 MC |
7248 | PCISTATE_ALLOW_APE_SHMEM_WR | |
7249 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
ee6a99b5 MC |
7250 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); |
7251 | ||
8a6eac90 | 7252 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); |
ee6a99b5 | 7253 | |
fcb389df | 7254 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) { |
63c3a66f | 7255 | if (tg3_flag(tp, PCI_EXPRESS)) |
cf79003d | 7256 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); |
fcb389df MC |
7257 | else { |
7258 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
7259 | tp->pci_cacheline_sz); | |
7260 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
7261 | tp->pci_lat_timer); | |
7262 | } | |
114342f2 | 7263 | } |
5f5c51e3 | 7264 | |
ee6a99b5 | 7265 | /* Make sure PCI-X relaxed ordering bit is clear. */ |
63c3a66f | 7266 | if (tg3_flag(tp, PCIX_MODE)) { |
9974a356 MC |
7267 | u16 pcix_cmd; |
7268 | ||
7269 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7270 | &pcix_cmd); | |
7271 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
7272 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7273 | pcix_cmd); | |
7274 | } | |
ee6a99b5 | 7275 | |
63c3a66f | 7276 | if (tg3_flag(tp, 5780_CLASS)) { |
ee6a99b5 MC |
7277 | |
7278 | /* Chip reset on 5780 will reset MSI enable bit, | |
7279 | * so need to restore it. | |
7280 | */ | |
63c3a66f | 7281 | if (tg3_flag(tp, USING_MSI)) { |
ee6a99b5 MC |
7282 | u16 ctrl; |
7283 | ||
7284 | pci_read_config_word(tp->pdev, | |
7285 | tp->msi_cap + PCI_MSI_FLAGS, | |
7286 | &ctrl); | |
7287 | pci_write_config_word(tp->pdev, | |
7288 | tp->msi_cap + PCI_MSI_FLAGS, | |
7289 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
7290 | val = tr32(MSGINT_MODE); | |
7291 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
7292 | } | |
7293 | } | |
7294 | } | |
7295 | ||
1da177e4 LT |
7296 | static void tg3_stop_fw(struct tg3 *); |
7297 | ||
7298 | /* tp->lock is held. */ | |
7299 | static int tg3_chip_reset(struct tg3 *tp) | |
7300 | { | |
7301 | u32 val; | |
1ee582d8 | 7302 | void (*write_op)(struct tg3 *, u32, u32); |
4f125f42 | 7303 | int i, err; |
1da177e4 | 7304 | |
f49639e6 DM |
7305 | tg3_nvram_lock(tp); |
7306 | ||
77b483f1 MC |
7307 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); |
7308 | ||
f49639e6 DM |
7309 | /* No matching tg3_nvram_unlock() after this because |
7310 | * chip reset below will undo the nvram lock. | |
7311 | */ | |
7312 | tp->nvram_lock_cnt = 0; | |
1da177e4 | 7313 | |
ee6a99b5 MC |
7314 | /* GRC_MISC_CFG core clock reset will clear the memory |
7315 | * enable bit in PCI register 4 and the MSI enable bit | |
7316 | * on some chips, so we save relevant registers here. | |
7317 | */ | |
7318 | tg3_save_pci_state(tp); | |
7319 | ||
d9ab5ad1 | 7320 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
63c3a66f | 7321 | tg3_flag(tp, 5755_PLUS)) |
d9ab5ad1 MC |
7322 | tw32(GRC_FASTBOOT_PC, 0); |
7323 | ||
1da177e4 LT |
7324 | /* |
7325 | * We must avoid the readl() that normally takes place. | |
7326 | * It locks machines, causes machine checks, and other | |
7327 | * fun things. So, temporarily disable the 5701 | |
7328 | * hardware workaround, while we do the reset. | |
7329 | */ | |
1ee582d8 MC |
7330 | write_op = tp->write32; |
7331 | if (write_op == tg3_write_flush_reg32) | |
7332 | tp->write32 = tg3_write32; | |
1da177e4 | 7333 | |
d18edcb2 MC |
7334 | /* Prevent the irq handler from reading or writing PCI registers |
7335 | * during chip reset when the memory enable bit in the PCI command | |
7336 | * register may be cleared. The chip does not generate interrupt | |
7337 | * at this time, but the irq handler may still be called due to irq | |
7338 | * sharing or irqpoll. | |
7339 | */ | |
63c3a66f | 7340 | tg3_flag_set(tp, CHIP_RESETTING); |
f77a6a8e MC |
7341 | for (i = 0; i < tp->irq_cnt; i++) { |
7342 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7343 | if (tnapi->hw_status) { | |
7344 | tnapi->hw_status->status = 0; | |
7345 | tnapi->hw_status->status_tag = 0; | |
7346 | } | |
7347 | tnapi->last_tag = 0; | |
7348 | tnapi->last_irq_tag = 0; | |
b8fa2f3a | 7349 | } |
d18edcb2 | 7350 | smp_mb(); |
4f125f42 MC |
7351 | |
7352 | for (i = 0; i < tp->irq_cnt; i++) | |
7353 | synchronize_irq(tp->napi[i].irq_vec); | |
d18edcb2 | 7354 | |
255ca311 MC |
7355 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
7356 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
7357 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
7358 | } | |
7359 | ||
1da177e4 LT |
7360 | /* do the reset */ |
7361 | val = GRC_MISC_CFG_CORECLK_RESET; | |
7362 | ||
63c3a66f | 7363 | if (tg3_flag(tp, PCI_EXPRESS)) { |
88075d91 MC |
7364 | /* Force PCIe 1.0a mode */ |
7365 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
63c3a66f | 7366 | !tg3_flag(tp, 57765_PLUS) && |
88075d91 MC |
7367 | tr32(TG3_PCIE_PHY_TSTCTL) == |
7368 | (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) | |
7369 | tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); | |
7370 | ||
1da177e4 LT |
7371 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { |
7372 | tw32(GRC_MISC_CFG, (1 << 29)); | |
7373 | val |= (1 << 29); | |
7374 | } | |
7375 | } | |
7376 | ||
b5d3772c MC |
7377 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7378 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
7379 | tw32(GRC_VCPU_EXT_CTRL, | |
7380 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7381 | } | |
7382 | ||
f37500d3 | 7383 | /* Manage gphy power for all CPMU absent PCIe devices. */ |
63c3a66f | 7384 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) |
1da177e4 | 7385 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; |
f37500d3 | 7386 | |
1da177e4 LT |
7387 | tw32(GRC_MISC_CFG, val); |
7388 | ||
1ee582d8 MC |
7389 | /* restore 5701 hardware bug workaround write method */ |
7390 | tp->write32 = write_op; | |
1da177e4 LT |
7391 | |
7392 | /* Unfortunately, we have to delay before the PCI read back. | |
7393 | * Some 575X chips even will not respond to a PCI cfg access | |
7394 | * when the reset command is given to the chip. | |
7395 | * | |
7396 | * How do these hardware designers expect things to work | |
7397 | * properly if the PCI write is posted for a long period | |
7398 | * of time? It is always necessary to have some method by | |
7399 | * which a register read back can occur to push the write | |
7400 | * out which does the reset. | |
7401 | * | |
7402 | * For most tg3 variants the trick below was working. | |
7403 | * Ho hum... | |
7404 | */ | |
7405 | udelay(120); | |
7406 | ||
7407 | /* Flush PCI posted writes. The normal MMIO registers | |
7408 | * are inaccessible at this time so this is the only | |
7409 | * way to make this reliably (actually, this is no longer | |
7410 | * the case, see above). I tried to use indirect | |
7411 | * register read/write but this upset some 5701 variants. | |
7412 | */ | |
7413 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
7414 | ||
7415 | udelay(120); | |
7416 | ||
708ebb3a | 7417 | if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) { |
e7126997 MC |
7418 | u16 val16; |
7419 | ||
1da177e4 LT |
7420 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { |
7421 | int i; | |
7422 | u32 cfg_val; | |
7423 | ||
7424 | /* Wait for link training to complete. */ | |
7425 | for (i = 0; i < 5000; i++) | |
7426 | udelay(100); | |
7427 | ||
7428 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
7429 | pci_write_config_dword(tp->pdev, 0xc4, | |
7430 | cfg_val | (1 << 15)); | |
7431 | } | |
5e7dfd0f | 7432 | |
e7126997 MC |
7433 | /* Clear the "no snoop" and "relaxed ordering" bits. */ |
7434 | pci_read_config_word(tp->pdev, | |
708ebb3a | 7435 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL, |
e7126997 MC |
7436 | &val16); |
7437 | val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | | |
7438 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
7439 | /* | |
7440 | * Older PCIe devices only support the 128 byte | |
7441 | * MPS setting. Enforce the restriction. | |
5e7dfd0f | 7442 | */ |
63c3a66f | 7443 | if (!tg3_flag(tp, CPMU_PRESENT)) |
e7126997 | 7444 | val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; |
5e7dfd0f | 7445 | pci_write_config_word(tp->pdev, |
708ebb3a | 7446 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL, |
e7126997 | 7447 | val16); |
5e7dfd0f | 7448 | |
cf79003d | 7449 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); |
5e7dfd0f MC |
7450 | |
7451 | /* Clear error status */ | |
7452 | pci_write_config_word(tp->pdev, | |
708ebb3a | 7453 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA, |
5e7dfd0f MC |
7454 | PCI_EXP_DEVSTA_CED | |
7455 | PCI_EXP_DEVSTA_NFED | | |
7456 | PCI_EXP_DEVSTA_FED | | |
7457 | PCI_EXP_DEVSTA_URD); | |
1da177e4 LT |
7458 | } |
7459 | ||
ee6a99b5 | 7460 | tg3_restore_pci_state(tp); |
1da177e4 | 7461 | |
63c3a66f JP |
7462 | tg3_flag_clear(tp, CHIP_RESETTING); |
7463 | tg3_flag_clear(tp, ERROR_PROCESSED); | |
d18edcb2 | 7464 | |
ee6a99b5 | 7465 | val = 0; |
63c3a66f | 7466 | if (tg3_flag(tp, 5780_CLASS)) |
4cf78e4f | 7467 | val = tr32(MEMARB_MODE); |
ee6a99b5 | 7468 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
1da177e4 LT |
7469 | |
7470 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
7471 | tg3_stop_fw(tp); | |
7472 | tw32(0x5000, 0x400); | |
7473 | } | |
7474 | ||
7475 | tw32(GRC_MODE, tp->grc_mode); | |
7476 | ||
7477 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
ab0049b4 | 7478 | val = tr32(0xc4); |
1da177e4 LT |
7479 | |
7480 | tw32(0xc4, val | (1 << 15)); | |
7481 | } | |
7482 | ||
7483 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
7484 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
7485 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
7486 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
7487 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
7488 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
7489 | } | |
7490 | ||
f07e9af3 | 7491 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
9e975cc2 | 7492 | tp->mac_mode = MAC_MODE_PORT_MODE_TBI; |
d2394e6b | 7493 | val = tp->mac_mode; |
f07e9af3 | 7494 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
9e975cc2 | 7495 | tp->mac_mode = MAC_MODE_PORT_MODE_GMII; |
d2394e6b | 7496 | val = tp->mac_mode; |
1da177e4 | 7497 | } else |
d2394e6b MC |
7498 | val = 0; |
7499 | ||
7500 | tw32_f(MAC_MODE, val); | |
1da177e4 LT |
7501 | udelay(40); |
7502 | ||
77b483f1 MC |
7503 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); |
7504 | ||
7a6f4369 MC |
7505 | err = tg3_poll_fw(tp); |
7506 | if (err) | |
7507 | return err; | |
1da177e4 | 7508 | |
0a9140cf MC |
7509 | tg3_mdio_start(tp); |
7510 | ||
63c3a66f | 7511 | if (tg3_flag(tp, PCI_EXPRESS) && |
f6eb9b1f MC |
7512 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
7513 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
63c3a66f | 7514 | !tg3_flag(tp, 57765_PLUS)) { |
ab0049b4 | 7515 | val = tr32(0x7c00); |
1da177e4 LT |
7516 | |
7517 | tw32(0x7c00, val | (1 << 25)); | |
7518 | } | |
7519 | ||
d78b59f5 MC |
7520 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
7521 | val = tr32(TG3_CPMU_CLCK_ORIDE); | |
7522 | tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); | |
7523 | } | |
7524 | ||
1da177e4 | 7525 | /* Reprobe ASF enable state. */ |
63c3a66f JP |
7526 | tg3_flag_clear(tp, ENABLE_ASF); |
7527 | tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 LT |
7528 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
7529 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
7530 | u32 nic_cfg; | |
7531 | ||
7532 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
7533 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
63c3a66f | 7534 | tg3_flag_set(tp, ENABLE_ASF); |
4ba526ce | 7535 | tp->last_event_jiffies = jiffies; |
63c3a66f JP |
7536 | if (tg3_flag(tp, 5750_PLUS)) |
7537 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 LT |
7538 | } |
7539 | } | |
7540 | ||
7541 | return 0; | |
7542 | } | |
7543 | ||
7544 | /* tp->lock is held. */ | |
7545 | static void tg3_stop_fw(struct tg3 *tp) | |
7546 | { | |
63c3a66f | 7547 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { |
7c5026aa MC |
7548 | /* Wait for RX cpu to ACK the previous event. */ |
7549 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
7550 | |
7551 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
4ba526ce MC |
7552 | |
7553 | tg3_generate_fw_event(tp); | |
1da177e4 | 7554 | |
7c5026aa MC |
7555 | /* Wait for RX cpu to ACK this event. */ |
7556 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
7557 | } |
7558 | } | |
7559 | ||
7560 | /* tp->lock is held. */ | |
944d980e | 7561 | static int tg3_halt(struct tg3 *tp, int kind, int silent) |
1da177e4 LT |
7562 | { |
7563 | int err; | |
7564 | ||
7565 | tg3_stop_fw(tp); | |
7566 | ||
944d980e | 7567 | tg3_write_sig_pre_reset(tp, kind); |
1da177e4 | 7568 | |
b3b7d6be | 7569 | tg3_abort_hw(tp, silent); |
1da177e4 LT |
7570 | err = tg3_chip_reset(tp); |
7571 | ||
daba2a63 MC |
7572 | __tg3_set_mac_addr(tp, 0); |
7573 | ||
944d980e MC |
7574 | tg3_write_sig_legacy(tp, kind); |
7575 | tg3_write_sig_post_reset(tp, kind); | |
1da177e4 LT |
7576 | |
7577 | if (err) | |
7578 | return err; | |
7579 | ||
7580 | return 0; | |
7581 | } | |
7582 | ||
1da177e4 LT |
7583 | #define RX_CPU_SCRATCH_BASE 0x30000 |
7584 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
7585 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
7586 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
7587 | ||
7588 | /* tp->lock is held. */ | |
7589 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
7590 | { | |
7591 | int i; | |
7592 | ||
63c3a66f | 7593 | BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); |
1da177e4 | 7594 | |
b5d3772c MC |
7595 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7596 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
7597 | ||
7598 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7599 | return 0; | |
7600 | } | |
1da177e4 LT |
7601 | if (offset == RX_CPU_BASE) { |
7602 | for (i = 0; i < 10000; i++) { | |
7603 | tw32(offset + CPU_STATE, 0xffffffff); | |
7604 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7605 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7606 | break; | |
7607 | } | |
7608 | ||
7609 | tw32(offset + CPU_STATE, 0xffffffff); | |
7610 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
7611 | udelay(10); | |
7612 | } else { | |
7613 | for (i = 0; i < 10000; i++) { | |
7614 | tw32(offset + CPU_STATE, 0xffffffff); | |
7615 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7616 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7617 | break; | |
7618 | } | |
7619 | } | |
7620 | ||
7621 | if (i >= 10000) { | |
05dbe005 JP |
7622 | netdev_err(tp->dev, "%s timed out, %s CPU\n", |
7623 | __func__, offset == RX_CPU_BASE ? "RX" : "TX"); | |
1da177e4 LT |
7624 | return -ENODEV; |
7625 | } | |
ec41c7df MC |
7626 | |
7627 | /* Clear firmware's nvram arbitration. */ | |
63c3a66f | 7628 | if (tg3_flag(tp, NVRAM)) |
ec41c7df | 7629 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); |
1da177e4 LT |
7630 | return 0; |
7631 | } | |
7632 | ||
7633 | struct fw_info { | |
077f849d JSR |
7634 | unsigned int fw_base; |
7635 | unsigned int fw_len; | |
7636 | const __be32 *fw_data; | |
1da177e4 LT |
7637 | }; |
7638 | ||
7639 | /* tp->lock is held. */ | |
7640 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base, | |
7641 | int cpu_scratch_size, struct fw_info *info) | |
7642 | { | |
ec41c7df | 7643 | int err, lock_err, i; |
1da177e4 LT |
7644 | void (*write_op)(struct tg3 *, u32, u32); |
7645 | ||
63c3a66f | 7646 | if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { |
5129c3a3 MC |
7647 | netdev_err(tp->dev, |
7648 | "%s: Trying to load TX cpu firmware which is 5705\n", | |
05dbe005 | 7649 | __func__); |
1da177e4 LT |
7650 | return -EINVAL; |
7651 | } | |
7652 | ||
63c3a66f | 7653 | if (tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
7654 | write_op = tg3_write_mem; |
7655 | else | |
7656 | write_op = tg3_write_indirect_reg32; | |
7657 | ||
1b628151 MC |
7658 | /* It is possible that bootcode is still loading at this point. |
7659 | * Get the nvram lock first before halting the cpu. | |
7660 | */ | |
ec41c7df | 7661 | lock_err = tg3_nvram_lock(tp); |
1da177e4 | 7662 | err = tg3_halt_cpu(tp, cpu_base); |
ec41c7df MC |
7663 | if (!lock_err) |
7664 | tg3_nvram_unlock(tp); | |
1da177e4 LT |
7665 | if (err) |
7666 | goto out; | |
7667 | ||
7668 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
7669 | write_op(tp, cpu_scratch_base + i, 0); | |
7670 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7671 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
077f849d | 7672 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) |
1da177e4 | 7673 | write_op(tp, (cpu_scratch_base + |
077f849d | 7674 | (info->fw_base & 0xffff) + |
1da177e4 | 7675 | (i * sizeof(u32))), |
077f849d | 7676 | be32_to_cpu(info->fw_data[i])); |
1da177e4 LT |
7677 | |
7678 | err = 0; | |
7679 | ||
7680 | out: | |
1da177e4 LT |
7681 | return err; |
7682 | } | |
7683 | ||
7684 | /* tp->lock is held. */ | |
7685 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
7686 | { | |
7687 | struct fw_info info; | |
077f849d | 7688 | const __be32 *fw_data; |
1da177e4 LT |
7689 | int err, i; |
7690 | ||
077f849d JSR |
7691 | fw_data = (void *)tp->fw->data; |
7692 | ||
7693 | /* Firmware blob starts with version numbers, followed by | |
7694 | start address and length. We are setting complete length. | |
7695 | length = end_address_of_bss - start_address_of_text. | |
7696 | Remainder is the blob to be loaded contiguously | |
7697 | from start address. */ | |
7698 | ||
7699 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7700 | info.fw_len = tp->fw->size - 12; | |
7701 | info.fw_data = &fw_data[3]; | |
1da177e4 LT |
7702 | |
7703 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
7704 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
7705 | &info); | |
7706 | if (err) | |
7707 | return err; | |
7708 | ||
7709 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
7710 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
7711 | &info); | |
7712 | if (err) | |
7713 | return err; | |
7714 | ||
7715 | /* Now startup only the RX cpu. */ | |
7716 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
077f849d | 7717 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
7718 | |
7719 | for (i = 0; i < 5; i++) { | |
077f849d | 7720 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) |
1da177e4 LT |
7721 | break; |
7722 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7723 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 7724 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
7725 | udelay(1000); |
7726 | } | |
7727 | if (i >= 5) { | |
5129c3a3 MC |
7728 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " |
7729 | "should be %08x\n", __func__, | |
05dbe005 | 7730 | tr32(RX_CPU_BASE + CPU_PC), info.fw_base); |
1da177e4 LT |
7731 | return -ENODEV; |
7732 | } | |
7733 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7734 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
7735 | ||
7736 | return 0; | |
7737 | } | |
7738 | ||
1da177e4 LT |
7739 | /* tp->lock is held. */ |
7740 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
7741 | { | |
7742 | struct fw_info info; | |
077f849d | 7743 | const __be32 *fw_data; |
1da177e4 LT |
7744 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; |
7745 | int err, i; | |
7746 | ||
63c3a66f JP |
7747 | if (tg3_flag(tp, HW_TSO_1) || |
7748 | tg3_flag(tp, HW_TSO_2) || | |
7749 | tg3_flag(tp, HW_TSO_3)) | |
1da177e4 LT |
7750 | return 0; |
7751 | ||
077f849d JSR |
7752 | fw_data = (void *)tp->fw->data; |
7753 | ||
7754 | /* Firmware blob starts with version numbers, followed by | |
7755 | start address and length. We are setting complete length. | |
7756 | length = end_address_of_bss - start_address_of_text. | |
7757 | Remainder is the blob to be loaded contiguously | |
7758 | from start address. */ | |
7759 | ||
7760 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7761 | cpu_scratch_size = tp->fw_len; | |
7762 | info.fw_len = tp->fw->size - 12; | |
7763 | info.fw_data = &fw_data[3]; | |
7764 | ||
1da177e4 | 7765 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
7766 | cpu_base = RX_CPU_BASE; |
7767 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
1da177e4 | 7768 | } else { |
1da177e4 LT |
7769 | cpu_base = TX_CPU_BASE; |
7770 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
7771 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
7772 | } | |
7773 | ||
7774 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
7775 | cpu_scratch_base, cpu_scratch_size, | |
7776 | &info); | |
7777 | if (err) | |
7778 | return err; | |
7779 | ||
7780 | /* Now startup the cpu. */ | |
7781 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
077f849d | 7782 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
7783 | |
7784 | for (i = 0; i < 5; i++) { | |
077f849d | 7785 | if (tr32(cpu_base + CPU_PC) == info.fw_base) |
1da177e4 LT |
7786 | break; |
7787 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7788 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 7789 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
7790 | udelay(1000); |
7791 | } | |
7792 | if (i >= 5) { | |
5129c3a3 MC |
7793 | netdev_err(tp->dev, |
7794 | "%s fails to set CPU PC, is %08x should be %08x\n", | |
05dbe005 | 7795 | __func__, tr32(cpu_base + CPU_PC), info.fw_base); |
1da177e4 LT |
7796 | return -ENODEV; |
7797 | } | |
7798 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7799 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
7800 | return 0; | |
7801 | } | |
7802 | ||
1da177e4 | 7803 | |
1da177e4 LT |
7804 | static int tg3_set_mac_addr(struct net_device *dev, void *p) |
7805 | { | |
7806 | struct tg3 *tp = netdev_priv(dev); | |
7807 | struct sockaddr *addr = p; | |
986e0aeb | 7808 | int err = 0, skip_mac_1 = 0; |
1da177e4 | 7809 | |
f9804ddb MC |
7810 | if (!is_valid_ether_addr(addr->sa_data)) |
7811 | return -EINVAL; | |
7812 | ||
1da177e4 LT |
7813 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
7814 | ||
e75f7c90 MC |
7815 | if (!netif_running(dev)) |
7816 | return 0; | |
7817 | ||
63c3a66f | 7818 | if (tg3_flag(tp, ENABLE_ASF)) { |
986e0aeb | 7819 | u32 addr0_high, addr0_low, addr1_high, addr1_low; |
58712ef9 | 7820 | |
986e0aeb MC |
7821 | addr0_high = tr32(MAC_ADDR_0_HIGH); |
7822 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
7823 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
7824 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
7825 | ||
7826 | /* Skip MAC addr 1 if ASF is using it. */ | |
7827 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
7828 | !(addr1_high == 0 && addr1_low == 0)) | |
7829 | skip_mac_1 = 1; | |
58712ef9 | 7830 | } |
986e0aeb MC |
7831 | spin_lock_bh(&tp->lock); |
7832 | __tg3_set_mac_addr(tp, skip_mac_1); | |
7833 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 7834 | |
b9ec6c1b | 7835 | return err; |
1da177e4 LT |
7836 | } |
7837 | ||
7838 | /* tp->lock is held. */ | |
7839 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
7840 | dma_addr_t mapping, u32 maxlen_flags, | |
7841 | u32 nic_addr) | |
7842 | { | |
7843 | tg3_write_mem(tp, | |
7844 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
7845 | ((u64) mapping >> 32)); | |
7846 | tg3_write_mem(tp, | |
7847 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
7848 | ((u64) mapping & 0xffffffff)); | |
7849 | tg3_write_mem(tp, | |
7850 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
7851 | maxlen_flags); | |
7852 | ||
63c3a66f | 7853 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
7854 | tg3_write_mem(tp, |
7855 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
7856 | nic_addr); | |
7857 | } | |
7858 | ||
7859 | static void __tg3_set_rx_mode(struct net_device *); | |
d244c892 | 7860 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) |
15f9850d | 7861 | { |
b6080e12 MC |
7862 | int i; |
7863 | ||
63c3a66f | 7864 | if (!tg3_flag(tp, ENABLE_TSS)) { |
b6080e12 MC |
7865 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); |
7866 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
7867 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
b6080e12 MC |
7868 | } else { |
7869 | tw32(HOSTCC_TXCOL_TICKS, 0); | |
7870 | tw32(HOSTCC_TXMAX_FRAMES, 0); | |
7871 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | |
19cfaecc | 7872 | } |
b6080e12 | 7873 | |
63c3a66f | 7874 | if (!tg3_flag(tp, ENABLE_RSS)) { |
19cfaecc MC |
7875 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); |
7876 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
7877 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
7878 | } else { | |
b6080e12 MC |
7879 | tw32(HOSTCC_RXCOL_TICKS, 0); |
7880 | tw32(HOSTCC_RXMAX_FRAMES, 0); | |
7881 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); | |
15f9850d | 7882 | } |
b6080e12 | 7883 | |
63c3a66f | 7884 | if (!tg3_flag(tp, 5705_PLUS)) { |
15f9850d DM |
7885 | u32 val = ec->stats_block_coalesce_usecs; |
7886 | ||
b6080e12 MC |
7887 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); |
7888 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
7889 | ||
15f9850d DM |
7890 | if (!netif_carrier_ok(tp->dev)) |
7891 | val = 0; | |
7892 | ||
7893 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
7894 | } | |
b6080e12 MC |
7895 | |
7896 | for (i = 0; i < tp->irq_cnt - 1; i++) { | |
7897 | u32 reg; | |
7898 | ||
7899 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; | |
7900 | tw32(reg, ec->rx_coalesce_usecs); | |
b6080e12 MC |
7901 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; |
7902 | tw32(reg, ec->rx_max_coalesced_frames); | |
b6080e12 MC |
7903 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; |
7904 | tw32(reg, ec->rx_max_coalesced_frames_irq); | |
19cfaecc | 7905 | |
63c3a66f | 7906 | if (tg3_flag(tp, ENABLE_TSS)) { |
19cfaecc MC |
7907 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; |
7908 | tw32(reg, ec->tx_coalesce_usecs); | |
7909 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; | |
7910 | tw32(reg, ec->tx_max_coalesced_frames); | |
7911 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
7912 | tw32(reg, ec->tx_max_coalesced_frames_irq); | |
7913 | } | |
b6080e12 MC |
7914 | } |
7915 | ||
7916 | for (; i < tp->irq_max - 1; i++) { | |
7917 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); | |
b6080e12 | 7918 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); |
b6080e12 | 7919 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); |
19cfaecc | 7920 | |
63c3a66f | 7921 | if (tg3_flag(tp, ENABLE_TSS)) { |
19cfaecc MC |
7922 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); |
7923 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
7924 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
7925 | } | |
b6080e12 | 7926 | } |
15f9850d | 7927 | } |
1da177e4 | 7928 | |
2d31ecaf MC |
7929 | /* tp->lock is held. */ |
7930 | static void tg3_rings_reset(struct tg3 *tp) | |
7931 | { | |
7932 | int i; | |
f77a6a8e | 7933 | u32 stblk, txrcb, rxrcb, limit; |
2d31ecaf MC |
7934 | struct tg3_napi *tnapi = &tp->napi[0]; |
7935 | ||
7936 | /* Disable all transmit rings but the first. */ | |
63c3a66f | 7937 | if (!tg3_flag(tp, 5705_PLUS)) |
2d31ecaf | 7938 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; |
63c3a66f | 7939 | else if (tg3_flag(tp, 5717_PLUS)) |
3d37728b | 7940 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; |
b703df6f MC |
7941 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
7942 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; | |
2d31ecaf MC |
7943 | else |
7944 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7945 | ||
7946 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7947 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) | |
7948 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7949 | BDINFO_FLAGS_DISABLED); | |
7950 | ||
7951 | ||
7952 | /* Disable all receive return rings but the first. */ | |
63c3a66f | 7953 | if (tg3_flag(tp, 5717_PLUS)) |
f6eb9b1f | 7954 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; |
63c3a66f | 7955 | else if (!tg3_flag(tp, 5705_PLUS)) |
2d31ecaf | 7956 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; |
b703df6f MC |
7957 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
7958 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
2d31ecaf MC |
7959 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; |
7960 | else | |
7961 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7962 | ||
7963 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7964 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) | |
7965 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7966 | BDINFO_FLAGS_DISABLED); | |
7967 | ||
7968 | /* Disable interrupts */ | |
7969 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); | |
0e6cf6a9 MC |
7970 | tp->napi[0].chk_msi_cnt = 0; |
7971 | tp->napi[0].last_rx_cons = 0; | |
7972 | tp->napi[0].last_tx_cons = 0; | |
2d31ecaf MC |
7973 | |
7974 | /* Zero mailbox registers. */ | |
63c3a66f | 7975 | if (tg3_flag(tp, SUPPORT_MSIX)) { |
6fd45cb8 | 7976 | for (i = 1; i < tp->irq_max; i++) { |
f77a6a8e MC |
7977 | tp->napi[i].tx_prod = 0; |
7978 | tp->napi[i].tx_cons = 0; | |
63c3a66f | 7979 | if (tg3_flag(tp, ENABLE_TSS)) |
c2353a32 | 7980 | tw32_mailbox(tp->napi[i].prodmbox, 0); |
f77a6a8e MC |
7981 | tw32_rx_mbox(tp->napi[i].consmbox, 0); |
7982 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); | |
0e6cf6a9 MC |
7983 | tp->napi[0].chk_msi_cnt = 0; |
7984 | tp->napi[i].last_rx_cons = 0; | |
7985 | tp->napi[i].last_tx_cons = 0; | |
f77a6a8e | 7986 | } |
63c3a66f | 7987 | if (!tg3_flag(tp, ENABLE_TSS)) |
c2353a32 | 7988 | tw32_mailbox(tp->napi[0].prodmbox, 0); |
f77a6a8e MC |
7989 | } else { |
7990 | tp->napi[0].tx_prod = 0; | |
7991 | tp->napi[0].tx_cons = 0; | |
7992 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
7993 | tw32_rx_mbox(tp->napi[0].consmbox, 0); | |
7994 | } | |
2d31ecaf MC |
7995 | |
7996 | /* Make sure the NIC-based send BD rings are disabled. */ | |
63c3a66f | 7997 | if (!tg3_flag(tp, 5705_PLUS)) { |
2d31ecaf MC |
7998 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; |
7999 | for (i = 0; i < 16; i++) | |
8000 | tw32_tx_mbox(mbox + i * 8, 0); | |
8001 | } | |
8002 | ||
8003 | txrcb = NIC_SRAM_SEND_RCB; | |
8004 | rxrcb = NIC_SRAM_RCV_RET_RCB; | |
8005 | ||
8006 | /* Clear status block in ram. */ | |
8007 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
8008 | ||
8009 | /* Set status block DMA address */ | |
8010 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
8011 | ((u64) tnapi->status_mapping >> 32)); | |
8012 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8013 | ((u64) tnapi->status_mapping & 0xffffffff)); | |
8014 | ||
f77a6a8e MC |
8015 | if (tnapi->tx_ring) { |
8016 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
8017 | (TG3_TX_RING_SIZE << | |
8018 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
8019 | NIC_SRAM_TX_BUFFER_DESC); | |
8020 | txrcb += TG3_BDINFO_SIZE; | |
8021 | } | |
8022 | ||
8023 | if (tnapi->rx_rcb) { | |
8024 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 MC |
8025 | (tp->rx_ret_ring_mask + 1) << |
8026 | BDINFO_FLAGS_MAXLEN_SHIFT, 0); | |
f77a6a8e MC |
8027 | rxrcb += TG3_BDINFO_SIZE; |
8028 | } | |
8029 | ||
8030 | stblk = HOSTCC_STATBLCK_RING1; | |
2d31ecaf | 8031 | |
f77a6a8e MC |
8032 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { |
8033 | u64 mapping = (u64)tnapi->status_mapping; | |
8034 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); | |
8035 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); | |
8036 | ||
8037 | /* Clear status block in ram. */ | |
8038 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
8039 | ||
19cfaecc MC |
8040 | if (tnapi->tx_ring) { |
8041 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
8042 | (TG3_TX_RING_SIZE << | |
8043 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
8044 | NIC_SRAM_TX_BUFFER_DESC); | |
8045 | txrcb += TG3_BDINFO_SIZE; | |
8046 | } | |
f77a6a8e MC |
8047 | |
8048 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 | 8049 | ((tp->rx_ret_ring_mask + 1) << |
f77a6a8e MC |
8050 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); |
8051 | ||
8052 | stblk += 8; | |
f77a6a8e MC |
8053 | rxrcb += TG3_BDINFO_SIZE; |
8054 | } | |
2d31ecaf MC |
8055 | } |
8056 | ||
eb07a940 MC |
8057 | static void tg3_setup_rxbd_thresholds(struct tg3 *tp) |
8058 | { | |
8059 | u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh; | |
8060 | ||
63c3a66f JP |
8061 | if (!tg3_flag(tp, 5750_PLUS) || |
8062 | tg3_flag(tp, 5780_CLASS) || | |
eb07a940 MC |
8063 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
8064 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
8065 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700; | |
8066 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
8067 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) | |
8068 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755; | |
8069 | else | |
8070 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906; | |
8071 | ||
8072 | nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); | |
8073 | host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); | |
8074 | ||
8075 | val = min(nic_rep_thresh, host_rep_thresh); | |
8076 | tw32(RCVBDI_STD_THRESH, val); | |
8077 | ||
63c3a66f | 8078 | if (tg3_flag(tp, 57765_PLUS)) |
eb07a940 MC |
8079 | tw32(STD_REPLENISH_LWM, bdcache_maxcnt); |
8080 | ||
63c3a66f | 8081 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
eb07a940 MC |
8082 | return; |
8083 | ||
63c3a66f | 8084 | if (!tg3_flag(tp, 5705_PLUS)) |
eb07a940 MC |
8085 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700; |
8086 | else | |
8087 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717; | |
8088 | ||
8089 | host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); | |
8090 | ||
8091 | val = min(bdcache_maxcnt / 2, host_rep_thresh); | |
8092 | tw32(RCVBDI_JUMBO_THRESH, val); | |
8093 | ||
63c3a66f | 8094 | if (tg3_flag(tp, 57765_PLUS)) |
eb07a940 MC |
8095 | tw32(JMB_REPLENISH_LWM, bdcache_maxcnt); |
8096 | } | |
8097 | ||
1da177e4 | 8098 | /* tp->lock is held. */ |
8e7a22e3 | 8099 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) |
1da177e4 LT |
8100 | { |
8101 | u32 val, rdmac_mode; | |
8102 | int i, err, limit; | |
8fea32b9 | 8103 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
1da177e4 LT |
8104 | |
8105 | tg3_disable_ints(tp); | |
8106 | ||
8107 | tg3_stop_fw(tp); | |
8108 | ||
8109 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
8110 | ||
63c3a66f | 8111 | if (tg3_flag(tp, INIT_COMPLETE)) |
e6de8ad1 | 8112 | tg3_abort_hw(tp, 1); |
1da177e4 | 8113 | |
699c0193 MC |
8114 | /* Enable MAC control of LPI */ |
8115 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { | |
8116 | tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, | |
8117 | TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | | |
8118 | TG3_CPMU_EEE_LNKIDL_UART_IDL); | |
8119 | ||
8120 | tw32_f(TG3_CPMU_EEE_CTRL, | |
8121 | TG3_CPMU_EEE_CTRL_EXIT_20_1_US); | |
8122 | ||
a386b901 MC |
8123 | val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET | |
8124 | TG3_CPMU_EEEMD_LPI_IN_TX | | |
8125 | TG3_CPMU_EEEMD_LPI_IN_RX | | |
8126 | TG3_CPMU_EEEMD_EEE_ENABLE; | |
8127 | ||
8128 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
8129 | val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; | |
8130 | ||
63c3a66f | 8131 | if (tg3_flag(tp, ENABLE_APE)) |
a386b901 MC |
8132 | val |= TG3_CPMU_EEEMD_APE_TX_DET_EN; |
8133 | ||
8134 | tw32_f(TG3_CPMU_EEE_MODE, val); | |
8135 | ||
8136 | tw32_f(TG3_CPMU_EEE_DBTMR1, | |
8137 | TG3_CPMU_DBTMR1_PCIEXIT_2047US | | |
8138 | TG3_CPMU_DBTMR1_LNKIDLE_2047US); | |
8139 | ||
8140 | tw32_f(TG3_CPMU_EEE_DBTMR2, | |
d7f2ab20 | 8141 | TG3_CPMU_DBTMR2_APE_TX_2047US | |
a386b901 | 8142 | TG3_CPMU_DBTMR2_TXIDXEQ_2047US); |
699c0193 MC |
8143 | } |
8144 | ||
603f1173 | 8145 | if (reset_phy) |
d4d2c558 MC |
8146 | tg3_phy_reset(tp); |
8147 | ||
1da177e4 LT |
8148 | err = tg3_chip_reset(tp); |
8149 | if (err) | |
8150 | return err; | |
8151 | ||
8152 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
8153 | ||
bcb37f6c | 8154 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
d30cdd28 MC |
8155 | val = tr32(TG3_CPMU_CTRL); |
8156 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
8157 | tw32(TG3_CPMU_CTRL, val); | |
9acb961e MC |
8158 | |
8159 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
8160 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8161 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8162 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
8163 | ||
8164 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
8165 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
8166 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
8167 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
8168 | ||
8169 | val = tr32(TG3_CPMU_HST_ACC); | |
8170 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
8171 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
8172 | tw32(TG3_CPMU_HST_ACC, val); | |
d30cdd28 MC |
8173 | } |
8174 | ||
33466d93 MC |
8175 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
8176 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
8177 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
8178 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
8179 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
521e6b90 MC |
8180 | |
8181 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
8182 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
8183 | ||
8184 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
33466d93 | 8185 | |
f40386c8 MC |
8186 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
8187 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
255ca311 MC |
8188 | } |
8189 | ||
63c3a66f | 8190 | if (tg3_flag(tp, L1PLLPD_EN)) { |
614b0590 MC |
8191 | u32 grc_mode = tr32(GRC_MODE); |
8192 | ||
8193 | /* Access the lower 1K of PL PCIE block registers. */ | |
8194 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8195 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
8196 | ||
8197 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); | |
8198 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, | |
8199 | val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); | |
8200 | ||
8201 | tw32(GRC_MODE, grc_mode); | |
8202 | } | |
8203 | ||
5093eedc MC |
8204 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { |
8205 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | |
8206 | u32 grc_mode = tr32(GRC_MODE); | |
cea46462 | 8207 | |
5093eedc MC |
8208 | /* Access the lower 1K of PL PCIE block registers. */ |
8209 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8210 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
cea46462 | 8211 | |
5093eedc MC |
8212 | val = tr32(TG3_PCIE_TLDLPL_PORT + |
8213 | TG3_PCIE_PL_LO_PHYCTL5); | |
8214 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, | |
8215 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); | |
cea46462 | 8216 | |
5093eedc MC |
8217 | tw32(GRC_MODE, grc_mode); |
8218 | } | |
a977dbe8 | 8219 | |
1ff30a59 MC |
8220 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) { |
8221 | u32 grc_mode = tr32(GRC_MODE); | |
8222 | ||
8223 | /* Access the lower 1K of DL PCIE block registers. */ | |
8224 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8225 | tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL); | |
8226 | ||
8227 | val = tr32(TG3_PCIE_TLDLPL_PORT + | |
8228 | TG3_PCIE_DL_LO_FTSMAX); | |
8229 | val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK; | |
8230 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, | |
8231 | val | TG3_PCIE_DL_LO_FTSMAX_VAL); | |
8232 | ||
8233 | tw32(GRC_MODE, grc_mode); | |
8234 | } | |
8235 | ||
a977dbe8 MC |
8236 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); |
8237 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8238 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8239 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
cea46462 MC |
8240 | } |
8241 | ||
1da177e4 LT |
8242 | /* This works around an issue with Athlon chipsets on |
8243 | * B3 tigon3 silicon. This bit has no effect on any | |
8244 | * other revision. But do not set this on PCI Express | |
795d01c5 | 8245 | * chips and don't even touch the clocks if the CPMU is present. |
1da177e4 | 8246 | */ |
63c3a66f JP |
8247 | if (!tg3_flag(tp, CPMU_PRESENT)) { |
8248 | if (!tg3_flag(tp, PCI_EXPRESS)) | |
795d01c5 MC |
8249 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; |
8250 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
8251 | } | |
1da177e4 LT |
8252 | |
8253 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
63c3a66f | 8254 | tg3_flag(tp, PCIX_MODE)) { |
1da177e4 LT |
8255 | val = tr32(TG3PCI_PCISTATE); |
8256 | val |= PCISTATE_RETRY_SAME_DMA; | |
8257 | tw32(TG3PCI_PCISTATE, val); | |
8258 | } | |
8259 | ||
63c3a66f | 8260 | if (tg3_flag(tp, ENABLE_APE)) { |
0d3031d9 MC |
8261 | /* Allow reads and writes to the |
8262 | * APE register and memory space. | |
8263 | */ | |
8264 | val = tr32(TG3PCI_PCISTATE); | |
8265 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
8266 | PCISTATE_ALLOW_APE_SHMEM_WR | |
8267 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
8268 | tw32(TG3PCI_PCISTATE, val); |
8269 | } | |
8270 | ||
1da177e4 LT |
8271 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { |
8272 | /* Enable some hw fixes. */ | |
8273 | val = tr32(TG3PCI_MSI_DATA); | |
8274 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
8275 | tw32(TG3PCI_MSI_DATA, val); | |
8276 | } | |
8277 | ||
8278 | /* Descriptor ring init may make accesses to the | |
8279 | * NIC SRAM area to setup the TX descriptors, so we | |
8280 | * can only do this after the hardware has been | |
8281 | * successfully reset. | |
8282 | */ | |
32d8c572 MC |
8283 | err = tg3_init_rings(tp); |
8284 | if (err) | |
8285 | return err; | |
1da177e4 | 8286 | |
63c3a66f | 8287 | if (tg3_flag(tp, 57765_PLUS)) { |
cbf9ca6c MC |
8288 | val = tr32(TG3PCI_DMA_RW_CTRL) & |
8289 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
1a319025 MC |
8290 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) |
8291 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; | |
0aebff48 MC |
8292 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 && |
8293 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
8294 | val |= DMA_RWCTRL_TAGGED_STAT_WA; | |
cbf9ca6c MC |
8295 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); |
8296 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | |
8297 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | |
d30cdd28 MC |
8298 | /* This value is determined during the probe time DMA |
8299 | * engine test, tg3_test_dma. | |
8300 | */ | |
8301 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
8302 | } | |
1da177e4 LT |
8303 | |
8304 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
8305 | GRC_MODE_4X_NIC_SEND_RINGS | | |
8306 | GRC_MODE_NO_TX_PHDR_CSUM | | |
8307 | GRC_MODE_NO_RX_PHDR_CSUM); | |
8308 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
d2d746f8 MC |
8309 | |
8310 | /* Pseudo-header checksum is done by hardware logic and not | |
8311 | * the offload processers, so make the chip do the pseudo- | |
8312 | * header checksums on receive. For transmit it is more | |
8313 | * convenient to do the pseudo-header checksum in software | |
8314 | * as Linux does that on transmit for us in all cases. | |
8315 | */ | |
8316 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
1da177e4 LT |
8317 | |
8318 | tw32(GRC_MODE, | |
8319 | tp->grc_mode | | |
8320 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
8321 | ||
8322 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
8323 | val = tr32(GRC_MISC_CFG); | |
8324 | val &= ~0xff; | |
8325 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
8326 | tw32(GRC_MISC_CFG, val); | |
8327 | ||
8328 | /* Initialize MBUF/DESC pool. */ | |
63c3a66f | 8329 | if (tg3_flag(tp, 5750_PLUS)) { |
1da177e4 LT |
8330 | /* Do nothing. */ |
8331 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
8332 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
8333 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
8334 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
8335 | else | |
8336 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
8337 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
8338 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
63c3a66f | 8339 | } else if (tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8340 | int fw_len; |
8341 | ||
077f849d | 8342 | fw_len = tp->fw_len; |
1da177e4 LT |
8343 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); |
8344 | tw32(BUFMGR_MB_POOL_ADDR, | |
8345 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
8346 | tw32(BUFMGR_MB_POOL_SIZE, | |
8347 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
8348 | } | |
1da177e4 | 8349 | |
0f893dc6 | 8350 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
1da177e4 LT |
8351 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
8352 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
8353 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8354 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
8355 | tw32(BUFMGR_MB_HIGH_WATER, | |
8356 | tp->bufmgr_config.mbuf_high_water); | |
8357 | } else { | |
8358 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
8359 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
8360 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8361 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
8362 | tw32(BUFMGR_MB_HIGH_WATER, | |
8363 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
8364 | } | |
8365 | tw32(BUFMGR_DMA_LOW_WATER, | |
8366 | tp->bufmgr_config.dma_low_water); | |
8367 | tw32(BUFMGR_DMA_HIGH_WATER, | |
8368 | tp->bufmgr_config.dma_high_water); | |
8369 | ||
d309a46e MC |
8370 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; |
8371 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
8372 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; | |
4d958473 MC |
8373 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
8374 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
8375 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) | |
8376 | val |= BUFMGR_MODE_MBLOW_ATTN_ENAB; | |
d309a46e | 8377 | tw32(BUFMGR_MODE, val); |
1da177e4 LT |
8378 | for (i = 0; i < 2000; i++) { |
8379 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
8380 | break; | |
8381 | udelay(10); | |
8382 | } | |
8383 | if (i >= 2000) { | |
05dbe005 | 8384 | netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); |
1da177e4 LT |
8385 | return -ENODEV; |
8386 | } | |
8387 | ||
eb07a940 MC |
8388 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) |
8389 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
b5d3772c | 8390 | |
eb07a940 | 8391 | tg3_setup_rxbd_thresholds(tp); |
1da177e4 LT |
8392 | |
8393 | /* Initialize TG3_BDINFO's at: | |
8394 | * RCVDBDI_STD_BD: standard eth size rx ring | |
8395 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
8396 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
8397 | * | |
8398 | * like so: | |
8399 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
8400 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
8401 | * ring attribute flags | |
8402 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
8403 | * | |
8404 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
8405 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
8406 | * | |
8407 | * The size of each ring is fixed in the firmware, but the location is | |
8408 | * configurable. | |
8409 | */ | |
8410 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
21f581a5 | 8411 | ((u64) tpr->rx_std_mapping >> 32)); |
1da177e4 | 8412 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8413 | ((u64) tpr->rx_std_mapping & 0xffffffff)); |
63c3a66f | 8414 | if (!tg3_flag(tp, 5717_PLUS)) |
87668d35 MC |
8415 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, |
8416 | NIC_SRAM_RX_BUFFER_DESC); | |
1da177e4 | 8417 | |
fdb72b38 | 8418 | /* Disable the mini ring */ |
63c3a66f | 8419 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
8420 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, |
8421 | BDINFO_FLAGS_DISABLED); | |
8422 | ||
fdb72b38 MC |
8423 | /* Program the jumbo buffer descriptor ring control |
8424 | * blocks on those devices that have them. | |
8425 | */ | |
a0512944 | 8426 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || |
63c3a66f | 8427 | (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { |
1da177e4 | 8428 | |
63c3a66f | 8429 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) { |
1da177e4 | 8430 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
21f581a5 | 8431 | ((u64) tpr->rx_jmb_mapping >> 32)); |
1da177e4 | 8432 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8433 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
de9f5230 MC |
8434 | val = TG3_RX_JMB_RING_SIZE(tp) << |
8435 | BDINFO_FLAGS_MAXLEN_SHIFT; | |
1da177e4 | 8436 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
de9f5230 | 8437 | val | BDINFO_FLAGS_USE_EXT_RECV); |
63c3a66f | 8438 | if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || |
a50d0796 | 8439 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
87668d35 MC |
8440 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
8441 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
1da177e4 LT |
8442 | } else { |
8443 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
8444 | BDINFO_FLAGS_DISABLED); | |
8445 | } | |
8446 | ||
63c3a66f | 8447 | if (tg3_flag(tp, 57765_PLUS)) { |
7cb32cf2 | 8448 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
de9f5230 | 8449 | val = TG3_RX_STD_MAX_SIZE_5700; |
7cb32cf2 | 8450 | else |
de9f5230 | 8451 | val = TG3_RX_STD_MAX_SIZE_5717; |
7cb32cf2 MC |
8452 | val <<= BDINFO_FLAGS_MAXLEN_SHIFT; |
8453 | val |= (TG3_RX_STD_DMA_SZ << 2); | |
8454 | } else | |
04380d40 | 8455 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 | 8456 | } else |
de9f5230 | 8457 | val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 MC |
8458 | |
8459 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
1da177e4 | 8460 | |
411da640 | 8461 | tpr->rx_std_prod_idx = tp->rx_pending; |
66711e66 | 8462 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); |
1da177e4 | 8463 | |
63c3a66f JP |
8464 | tpr->rx_jmb_prod_idx = |
8465 | tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; | |
66711e66 | 8466 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); |
1da177e4 | 8467 | |
2d31ecaf MC |
8468 | tg3_rings_reset(tp); |
8469 | ||
1da177e4 | 8470 | /* Initialize MAC address and backoff seed. */ |
986e0aeb | 8471 | __tg3_set_mac_addr(tp, 0); |
1da177e4 LT |
8472 | |
8473 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
f7b493e0 MC |
8474 | tw32(MAC_RX_MTU_SIZE, |
8475 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
1da177e4 LT |
8476 | |
8477 | /* The slot time is changed by tg3_setup_phy if we | |
8478 | * run at gigabit with half duplex. | |
8479 | */ | |
f2096f94 MC |
8480 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
8481 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
8482 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT); | |
8483 | ||
8484 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
8485 | val |= tr32(MAC_TX_LENGTHS) & | |
8486 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
8487 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
8488 | ||
8489 | tw32(MAC_TX_LENGTHS, val); | |
1da177e4 LT |
8490 | |
8491 | /* Receive rules. */ | |
8492 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
8493 | tw32(RCVLPC_CONFIG, 0x0181); | |
8494 | ||
8495 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
8496 | * the RCVLPC_STATE_ENABLE mask. | |
8497 | */ | |
8498 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
8499 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
8500 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
8501 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
8502 | RDMAC_MODE_LNGREAD_ENAB); | |
85e94ced | 8503 | |
deabaac8 | 8504 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
0339e4e3 MC |
8505 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; |
8506 | ||
57e6983c | 8507 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 MC |
8508 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
8509 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
d30cdd28 MC |
8510 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
8511 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
8512 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
8513 | ||
c5908939 MC |
8514 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8515 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 8516 | if (tg3_flag(tp, TSO_CAPABLE) && |
c13e3713 | 8517 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
8518 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
8519 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
63c3a66f | 8520 | !tg3_flag(tp, IS_5788)) { |
1da177e4 LT |
8521 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
8522 | } | |
8523 | } | |
8524 | ||
63c3a66f | 8525 | if (tg3_flag(tp, PCI_EXPRESS)) |
85e94ced MC |
8526 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
8527 | ||
63c3a66f JP |
8528 | if (tg3_flag(tp, HW_TSO_1) || |
8529 | tg3_flag(tp, HW_TSO_2) || | |
8530 | tg3_flag(tp, HW_TSO_3)) | |
027455ad MC |
8531 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
8532 | ||
108a6c16 | 8533 | if (tg3_flag(tp, 57765_PLUS) || |
e849cdc3 | 8534 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
027455ad MC |
8535 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
8536 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
1da177e4 | 8537 | |
f2096f94 MC |
8538 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
8539 | rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; | |
8540 | ||
41a8a7ee MC |
8541 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
8542 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
8543 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
8544 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
63c3a66f | 8545 | tg3_flag(tp, 57765_PLUS)) { |
41a8a7ee | 8546 | val = tr32(TG3_RDMA_RSRVCTRL_REG); |
d78b59f5 MC |
8547 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8548 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
b4495ed8 MC |
8549 | val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | |
8550 | TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK | | |
8551 | TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK); | |
8552 | val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B | | |
8553 | TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K | | |
8554 | TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K; | |
b75cc0e4 | 8555 | } |
41a8a7ee MC |
8556 | tw32(TG3_RDMA_RSRVCTRL_REG, |
8557 | val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); | |
8558 | } | |
8559 | ||
d78b59f5 MC |
8560 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8561 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
d309a46e MC |
8562 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); |
8563 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val | | |
8564 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K | | |
8565 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K); | |
8566 | } | |
8567 | ||
1da177e4 | 8568 | /* Receive/send statistics. */ |
63c3a66f | 8569 | if (tg3_flag(tp, 5750_PLUS)) { |
1661394e MC |
8570 | val = tr32(RCVLPC_STATS_ENABLE); |
8571 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
8572 | tw32(RCVLPC_STATS_ENABLE, val); | |
8573 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
63c3a66f | 8574 | tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8575 | val = tr32(RCVLPC_STATS_ENABLE); |
8576 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
8577 | tw32(RCVLPC_STATS_ENABLE, val); | |
8578 | } else { | |
8579 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
8580 | } | |
8581 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
8582 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
8583 | tw32(SNDDATAI_STATSCTRL, | |
8584 | (SNDDATAI_SCTRL_ENABLE | | |
8585 | SNDDATAI_SCTRL_FASTUPD)); | |
8586 | ||
8587 | /* Setup host coalescing engine. */ | |
8588 | tw32(HOSTCC_MODE, 0); | |
8589 | for (i = 0; i < 2000; i++) { | |
8590 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
8591 | break; | |
8592 | udelay(10); | |
8593 | } | |
8594 | ||
d244c892 | 8595 | __tg3_set_coalesce(tp, &tp->coal); |
1da177e4 | 8596 | |
63c3a66f | 8597 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
8598 | /* Status/statistics block address. See tg3_timer, |
8599 | * the tg3_periodic_fetch_stats call there, and | |
8600 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
8601 | */ | |
1da177e4 LT |
8602 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
8603 | ((u64) tp->stats_mapping >> 32)); | |
8604 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8605 | ((u64) tp->stats_mapping & 0xffffffff)); | |
8606 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
2d31ecaf | 8607 | |
1da177e4 | 8608 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); |
2d31ecaf MC |
8609 | |
8610 | /* Clear statistics and status block memory areas */ | |
8611 | for (i = NIC_SRAM_STATS_BLK; | |
8612 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
8613 | i += sizeof(u32)) { | |
8614 | tg3_write_mem(tp, i, 0); | |
8615 | udelay(40); | |
8616 | } | |
1da177e4 LT |
8617 | } |
8618 | ||
8619 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
8620 | ||
8621 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
8622 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
63c3a66f | 8623 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
8624 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); |
8625 | ||
f07e9af3 MC |
8626 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
8627 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
c94e3941 MC |
8628 | /* reset to prevent losing 1st rx packet intermittently */ |
8629 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
8630 | udelay(10); | |
8631 | } | |
8632 | ||
3bda1258 | 8633 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | |
9e975cc2 MC |
8634 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | |
8635 | MAC_MODE_FHDE_ENABLE; | |
8636 | if (tg3_flag(tp, ENABLE_APE)) | |
8637 | tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
63c3a66f | 8638 | if (!tg3_flag(tp, 5705_PLUS) && |
f07e9af3 | 8639 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
e8f3f6ca MC |
8640 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
8641 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
8642 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
8643 | udelay(40); | |
8644 | ||
314fba34 | 8645 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
63c3a66f | 8646 | * If TG3_FLAG_IS_NIC is zero, we should read the |
314fba34 MC |
8647 | * register to preserve the GPIO settings for LOMs. The GPIOs, |
8648 | * whether used as inputs or outputs, are set by boot code after | |
8649 | * reset. | |
8650 | */ | |
63c3a66f | 8651 | if (!tg3_flag(tp, IS_NIC)) { |
314fba34 MC |
8652 | u32 gpio_mask; |
8653 | ||
9d26e213 MC |
8654 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | |
8655 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
8656 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
3e7d83bc MC |
8657 | |
8658 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
8659 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
8660 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
8661 | ||
af36e6b6 MC |
8662 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
8663 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
8664 | ||
aaf84465 | 8665 | tp->grc_local_ctrl &= ~gpio_mask; |
314fba34 MC |
8666 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; |
8667 | ||
8668 | /* GPIO1 must be driven high for eeprom write protect */ | |
63c3a66f | 8669 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) |
9d26e213 MC |
8670 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
8671 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
314fba34 | 8672 | } |
1da177e4 LT |
8673 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
8674 | udelay(100); | |
8675 | ||
63c3a66f | 8676 | if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) { |
baf8a94a MC |
8677 | val = tr32(MSGINT_MODE); |
8678 | val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE; | |
8679 | tw32(MSGINT_MODE, val); | |
8680 | } | |
8681 | ||
63c3a66f | 8682 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
8683 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); |
8684 | udelay(40); | |
8685 | } | |
8686 | ||
8687 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
8688 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
8689 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
8690 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
8691 | WDMAC_MODE_LNGREAD_ENAB); | |
8692 | ||
c5908939 MC |
8693 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8694 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 8695 | if (tg3_flag(tp, TSO_CAPABLE) && |
1da177e4 LT |
8696 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
8697 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
8698 | /* nothing */ | |
8699 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
63c3a66f | 8700 | !tg3_flag(tp, IS_5788)) { |
1da177e4 LT |
8701 | val |= WDMAC_MODE_RX_ACCEL; |
8702 | } | |
8703 | } | |
8704 | ||
d9ab5ad1 | 8705 | /* Enable host coalescing bug fix */ |
63c3a66f | 8706 | if (tg3_flag(tp, 5755_PLUS)) |
f51f3562 | 8707 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
d9ab5ad1 | 8708 | |
788a035e MC |
8709 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
8710 | val |= WDMAC_MODE_BURST_ALL_DATA; | |
8711 | ||
1da177e4 LT |
8712 | tw32_f(WDMAC_MODE, val); |
8713 | udelay(40); | |
8714 | ||
63c3a66f | 8715 | if (tg3_flag(tp, PCIX_MODE)) { |
9974a356 MC |
8716 | u16 pcix_cmd; |
8717 | ||
8718 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8719 | &pcix_cmd); | |
1da177e4 | 8720 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { |
9974a356 MC |
8721 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
8722 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8723 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
9974a356 MC |
8724 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
8725 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8726 | } |
9974a356 MC |
8727 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
8728 | pcix_cmd); | |
1da177e4 LT |
8729 | } |
8730 | ||
8731 | tw32_f(RDMAC_MODE, rdmac_mode); | |
8732 | udelay(40); | |
8733 | ||
8734 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); | |
63c3a66f | 8735 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 | 8736 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); |
9936bcf6 MC |
8737 | |
8738 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
8739 | tw32(SNDDATAC_MODE, | |
8740 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
8741 | else | |
8742 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
8743 | ||
1da177e4 LT |
8744 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
8745 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
7cb32cf2 | 8746 | val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; |
63c3a66f | 8747 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
7cb32cf2 MC |
8748 | val |= RCVDBDI_MODE_LRG_RING_SZ; |
8749 | tw32(RCVDBDI_MODE, val); | |
1da177e4 | 8750 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); |
63c3a66f JP |
8751 | if (tg3_flag(tp, HW_TSO_1) || |
8752 | tg3_flag(tp, HW_TSO_2) || | |
8753 | tg3_flag(tp, HW_TSO_3)) | |
1da177e4 | 8754 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); |
baf8a94a | 8755 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; |
63c3a66f | 8756 | if (tg3_flag(tp, ENABLE_TSS)) |
baf8a94a MC |
8757 | val |= SNDBDI_MODE_MULTI_TXQ_EN; |
8758 | tw32(SNDBDI_MODE, val); | |
1da177e4 LT |
8759 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); |
8760 | ||
8761 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
8762 | err = tg3_load_5701_a0_firmware_fix(tp); | |
8763 | if (err) | |
8764 | return err; | |
8765 | } | |
8766 | ||
63c3a66f | 8767 | if (tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8768 | err = tg3_load_tso_firmware(tp); |
8769 | if (err) | |
8770 | return err; | |
8771 | } | |
1da177e4 LT |
8772 | |
8773 | tp->tx_mode = TX_MODE_ENABLE; | |
f2096f94 | 8774 | |
63c3a66f | 8775 | if (tg3_flag(tp, 5755_PLUS) || |
b1d05210 MC |
8776 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
8777 | tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; | |
f2096f94 MC |
8778 | |
8779 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
8780 | val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE; | |
8781 | tp->tx_mode &= ~val; | |
8782 | tp->tx_mode |= tr32(MAC_TX_MODE) & val; | |
8783 | } | |
8784 | ||
1da177e4 LT |
8785 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
8786 | udelay(100); | |
8787 | ||
63c3a66f | 8788 | if (tg3_flag(tp, ENABLE_RSS)) { |
9d53fa12 | 8789 | int i = 0; |
baf8a94a | 8790 | u32 reg = MAC_RSS_INDIR_TBL_0; |
baf8a94a | 8791 | |
9d53fa12 MC |
8792 | if (tp->irq_cnt == 2) { |
8793 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i += 8) { | |
8794 | tw32(reg, 0x0); | |
8795 | reg += 4; | |
8796 | } | |
8797 | } else { | |
8798 | u32 val; | |
baf8a94a | 8799 | |
9d53fa12 MC |
8800 | while (i < TG3_RSS_INDIR_TBL_SIZE) { |
8801 | val = i % (tp->irq_cnt - 1); | |
8802 | i++; | |
8803 | for (; i % 8; i++) { | |
8804 | val <<= 4; | |
8805 | val |= (i % (tp->irq_cnt - 1)); | |
8806 | } | |
baf8a94a MC |
8807 | tw32(reg, val); |
8808 | reg += 4; | |
8809 | } | |
8810 | } | |
8811 | ||
8812 | /* Setup the "secret" hash key. */ | |
8813 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); | |
8814 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); | |
8815 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); | |
8816 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); | |
8817 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); | |
8818 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); | |
8819 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); | |
8820 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); | |
8821 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); | |
8822 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); | |
8823 | } | |
8824 | ||
1da177e4 | 8825 | tp->rx_mode = RX_MODE_ENABLE; |
63c3a66f | 8826 | if (tg3_flag(tp, 5755_PLUS)) |
af36e6b6 MC |
8827 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; |
8828 | ||
63c3a66f | 8829 | if (tg3_flag(tp, ENABLE_RSS)) |
baf8a94a MC |
8830 | tp->rx_mode |= RX_MODE_RSS_ENABLE | |
8831 | RX_MODE_RSS_ITBL_HASH_BITS_7 | | |
8832 | RX_MODE_RSS_IPV6_HASH_EN | | |
8833 | RX_MODE_RSS_TCP_IPV6_HASH_EN | | |
8834 | RX_MODE_RSS_IPV4_HASH_EN | | |
8835 | RX_MODE_RSS_TCP_IPV4_HASH_EN; | |
8836 | ||
1da177e4 LT |
8837 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
8838 | udelay(10); | |
8839 | ||
1da177e4 LT |
8840 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
8841 | ||
8842 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
f07e9af3 | 8843 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 LT |
8844 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
8845 | udelay(10); | |
8846 | } | |
8847 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
8848 | udelay(10); | |
8849 | ||
f07e9af3 | 8850 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 | 8851 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && |
f07e9af3 | 8852 | !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { |
1da177e4 LT |
8853 | /* Set drive transmission level to 1.2V */ |
8854 | /* only if the signal pre-emphasis bit is not set */ | |
8855 | val = tr32(MAC_SERDES_CFG); | |
8856 | val &= 0xfffff000; | |
8857 | val |= 0x880; | |
8858 | tw32(MAC_SERDES_CFG, val); | |
8859 | } | |
8860 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
8861 | tw32(MAC_SERDES_CFG, 0x616000); | |
8862 | } | |
8863 | ||
8864 | /* Prevent chip from dropping frames when flow control | |
8865 | * is enabled. | |
8866 | */ | |
666bc831 MC |
8867 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
8868 | val = 1; | |
8869 | else | |
8870 | val = 2; | |
8871 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); | |
1da177e4 LT |
8872 | |
8873 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
f07e9af3 | 8874 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
1da177e4 | 8875 | /* Use hardware link auto-negotiation */ |
63c3a66f | 8876 | tg3_flag_set(tp, HW_AUTONEG); |
1da177e4 LT |
8877 | } |
8878 | ||
f07e9af3 | 8879 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
6ff6f81d | 8880 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
d4d2c558 MC |
8881 | u32 tmp; |
8882 | ||
8883 | tmp = tr32(SERDES_RX_CTRL); | |
8884 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
8885 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
8886 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
8887 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
8888 | } | |
8889 | ||
63c3a66f | 8890 | if (!tg3_flag(tp, USE_PHYLIB)) { |
80096068 MC |
8891 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
8892 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
8893 | tp->link_config.speed = tp->link_config.orig_speed; |
8894 | tp->link_config.duplex = tp->link_config.orig_duplex; | |
8895 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | |
8896 | } | |
1da177e4 | 8897 | |
dd477003 MC |
8898 | err = tg3_setup_phy(tp, 0); |
8899 | if (err) | |
8900 | return err; | |
1da177e4 | 8901 | |
f07e9af3 MC |
8902 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
8903 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
dd477003 MC |
8904 | u32 tmp; |
8905 | ||
8906 | /* Clear CRC stats. */ | |
8907 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
8908 | tg3_writephy(tp, MII_TG3_TEST1, | |
8909 | tmp | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 8910 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); |
dd477003 | 8911 | } |
1da177e4 LT |
8912 | } |
8913 | } | |
8914 | ||
8915 | __tg3_set_rx_mode(tp->dev); | |
8916 | ||
8917 | /* Initialize receive rules. */ | |
8918 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
8919 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8920 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
8921 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8922 | ||
63c3a66f | 8923 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) |
1da177e4 LT |
8924 | limit = 8; |
8925 | else | |
8926 | limit = 16; | |
63c3a66f | 8927 | if (tg3_flag(tp, ENABLE_ASF)) |
1da177e4 LT |
8928 | limit -= 4; |
8929 | switch (limit) { | |
8930 | case 16: | |
8931 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
8932 | case 15: | |
8933 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
8934 | case 14: | |
8935 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
8936 | case 13: | |
8937 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
8938 | case 12: | |
8939 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
8940 | case 11: | |
8941 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
8942 | case 10: | |
8943 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
8944 | case 9: | |
8945 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
8946 | case 8: | |
8947 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
8948 | case 7: | |
8949 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
8950 | case 6: | |
8951 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
8952 | case 5: | |
8953 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
8954 | case 4: | |
8955 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
8956 | case 3: | |
8957 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
8958 | case 2: | |
8959 | case 1: | |
8960 | ||
8961 | default: | |
8962 | break; | |
855e1111 | 8963 | } |
1da177e4 | 8964 | |
63c3a66f | 8965 | if (tg3_flag(tp, ENABLE_APE)) |
9ce768ea MC |
8966 | /* Write our heartbeat update interval to APE. */ |
8967 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
8968 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
0d3031d9 | 8969 | |
1da177e4 LT |
8970 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); |
8971 | ||
1da177e4 LT |
8972 | return 0; |
8973 | } | |
8974 | ||
8975 | /* Called at device open time to get the chip ready for | |
8976 | * packet processing. Invoked with tp->lock held. | |
8977 | */ | |
8e7a22e3 | 8978 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
1da177e4 | 8979 | { |
1da177e4 LT |
8980 | tg3_switch_clocks(tp); |
8981 | ||
8982 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
8983 | ||
2f751b67 | 8984 | return tg3_reset_hw(tp, reset_phy); |
1da177e4 LT |
8985 | } |
8986 | ||
8987 | #define TG3_STAT_ADD32(PSTAT, REG) \ | |
8988 | do { u32 __val = tr32(REG); \ | |
8989 | (PSTAT)->low += __val; \ | |
8990 | if ((PSTAT)->low < __val) \ | |
8991 | (PSTAT)->high += 1; \ | |
8992 | } while (0) | |
8993 | ||
8994 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
8995 | { | |
8996 | struct tg3_hw_stats *sp = tp->hw_stats; | |
8997 | ||
8998 | if (!netif_carrier_ok(tp->dev)) | |
8999 | return; | |
9000 | ||
9001 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
9002 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
9003 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
9004 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
9005 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
9006 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
9007 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
9008 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
9009 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
9010 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
9011 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
9012 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
9013 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
9014 | ||
9015 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
9016 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
9017 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
9018 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
9019 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
9020 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
9021 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
9022 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
9023 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
9024 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
9025 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
9026 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
9027 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
9028 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
463d305b MC |
9029 | |
9030 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
310050fa MC |
9031 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
9032 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 && | |
9033 | tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) { | |
4d958473 MC |
9034 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); |
9035 | } else { | |
9036 | u32 val = tr32(HOSTCC_FLOW_ATTN); | |
9037 | val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0; | |
9038 | if (val) { | |
9039 | tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM); | |
9040 | sp->rx_discards.low += val; | |
9041 | if (sp->rx_discards.low < val) | |
9042 | sp->rx_discards.high += 1; | |
9043 | } | |
9044 | sp->mbuf_lwm_thresh_hit = sp->rx_discards; | |
9045 | } | |
463d305b | 9046 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); |
1da177e4 LT |
9047 | } |
9048 | ||
0e6cf6a9 MC |
9049 | static void tg3_chk_missed_msi(struct tg3 *tp) |
9050 | { | |
9051 | u32 i; | |
9052 | ||
9053 | for (i = 0; i < tp->irq_cnt; i++) { | |
9054 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9055 | ||
9056 | if (tg3_has_work(tnapi)) { | |
9057 | if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && | |
9058 | tnapi->last_tx_cons == tnapi->tx_cons) { | |
9059 | if (tnapi->chk_msi_cnt < 1) { | |
9060 | tnapi->chk_msi_cnt++; | |
9061 | return; | |
9062 | } | |
9063 | tw32_mailbox(tnapi->int_mbox, | |
9064 | tnapi->last_tag << 24); | |
9065 | } | |
9066 | } | |
9067 | tnapi->chk_msi_cnt = 0; | |
9068 | tnapi->last_rx_cons = tnapi->rx_rcb_ptr; | |
9069 | tnapi->last_tx_cons = tnapi->tx_cons; | |
9070 | } | |
9071 | } | |
9072 | ||
1da177e4 LT |
9073 | static void tg3_timer(unsigned long __opaque) |
9074 | { | |
9075 | struct tg3 *tp = (struct tg3 *) __opaque; | |
1da177e4 | 9076 | |
f475f163 MC |
9077 | if (tp->irq_sync) |
9078 | goto restart_timer; | |
9079 | ||
f47c11ee | 9080 | spin_lock(&tp->lock); |
1da177e4 | 9081 | |
0e6cf6a9 MC |
9082 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
9083 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
9084 | tg3_chk_missed_msi(tp); | |
9085 | ||
63c3a66f | 9086 | if (!tg3_flag(tp, TAGGED_STATUS)) { |
fac9b83e DM |
9087 | /* All of this garbage is because when using non-tagged |
9088 | * IRQ status the mailbox/status_block protocol the chip | |
9089 | * uses with the cpu is race prone. | |
9090 | */ | |
898a56f8 | 9091 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { |
fac9b83e DM |
9092 | tw32(GRC_LOCAL_CTRL, |
9093 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
9094 | } else { | |
9095 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
fd2ce37f | 9096 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); |
fac9b83e | 9097 | } |
1da177e4 | 9098 | |
fac9b83e | 9099 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
63c3a66f | 9100 | tg3_flag_set(tp, RESTART_TIMER); |
f47c11ee | 9101 | spin_unlock(&tp->lock); |
fac9b83e DM |
9102 | schedule_work(&tp->reset_task); |
9103 | return; | |
9104 | } | |
1da177e4 LT |
9105 | } |
9106 | ||
1da177e4 LT |
9107 | /* This part only runs once per second. */ |
9108 | if (!--tp->timer_counter) { | |
63c3a66f | 9109 | if (tg3_flag(tp, 5705_PLUS)) |
fac9b83e DM |
9110 | tg3_periodic_fetch_stats(tp); |
9111 | ||
b0c5943f MC |
9112 | if (tp->setlpicnt && !--tp->setlpicnt) |
9113 | tg3_phy_eee_enable(tp); | |
52b02d04 | 9114 | |
63c3a66f | 9115 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
1da177e4 LT |
9116 | u32 mac_stat; |
9117 | int phy_event; | |
9118 | ||
9119 | mac_stat = tr32(MAC_STATUS); | |
9120 | ||
9121 | phy_event = 0; | |
f07e9af3 | 9122 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { |
1da177e4 LT |
9123 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) |
9124 | phy_event = 1; | |
9125 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
9126 | phy_event = 1; | |
9127 | ||
9128 | if (phy_event) | |
9129 | tg3_setup_phy(tp, 0); | |
63c3a66f | 9130 | } else if (tg3_flag(tp, POLL_SERDES)) { |
1da177e4 LT |
9131 | u32 mac_stat = tr32(MAC_STATUS); |
9132 | int need_setup = 0; | |
9133 | ||
9134 | if (netif_carrier_ok(tp->dev) && | |
9135 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { | |
9136 | need_setup = 1; | |
9137 | } | |
be98da6a | 9138 | if (!netif_carrier_ok(tp->dev) && |
1da177e4 LT |
9139 | (mac_stat & (MAC_STATUS_PCS_SYNCED | |
9140 | MAC_STATUS_SIGNAL_DET))) { | |
9141 | need_setup = 1; | |
9142 | } | |
9143 | if (need_setup) { | |
3d3ebe74 MC |
9144 | if (!tp->serdes_counter) { |
9145 | tw32_f(MAC_MODE, | |
9146 | (tp->mac_mode & | |
9147 | ~MAC_MODE_PORT_MODE_MASK)); | |
9148 | udelay(40); | |
9149 | tw32_f(MAC_MODE, tp->mac_mode); | |
9150 | udelay(40); | |
9151 | } | |
1da177e4 LT |
9152 | tg3_setup_phy(tp, 0); |
9153 | } | |
f07e9af3 | 9154 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
63c3a66f | 9155 | tg3_flag(tp, 5780_CLASS)) { |
747e8f8b | 9156 | tg3_serdes_parallel_detect(tp); |
57d8b880 | 9157 | } |
1da177e4 LT |
9158 | |
9159 | tp->timer_counter = tp->timer_multiplier; | |
9160 | } | |
9161 | ||
130b8e4d MC |
9162 | /* Heartbeat is only sent once every 2 seconds. |
9163 | * | |
9164 | * The heartbeat is to tell the ASF firmware that the host | |
9165 | * driver is still alive. In the event that the OS crashes, | |
9166 | * ASF needs to reset the hardware to free up the FIFO space | |
9167 | * that may be filled with rx packets destined for the host. | |
9168 | * If the FIFO is full, ASF will no longer function properly. | |
9169 | * | |
9170 | * Unintended resets have been reported on real time kernels | |
9171 | * where the timer doesn't run on time. Netpoll will also have | |
9172 | * same problem. | |
9173 | * | |
9174 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
9175 | * to check the ring condition when the heartbeat is expiring | |
9176 | * before doing the reset. This will prevent most unintended | |
9177 | * resets. | |
9178 | */ | |
1da177e4 | 9179 | if (!--tp->asf_counter) { |
63c3a66f | 9180 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { |
7c5026aa MC |
9181 | tg3_wait_for_event_ack(tp); |
9182 | ||
bbadf503 | 9183 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, |
130b8e4d | 9184 | FWCMD_NICDRV_ALIVE3); |
bbadf503 | 9185 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); |
c6cdf436 MC |
9186 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, |
9187 | TG3_FW_UPDATE_TIMEOUT_SEC); | |
4ba526ce MC |
9188 | |
9189 | tg3_generate_fw_event(tp); | |
1da177e4 LT |
9190 | } |
9191 | tp->asf_counter = tp->asf_multiplier; | |
9192 | } | |
9193 | ||
f47c11ee | 9194 | spin_unlock(&tp->lock); |
1da177e4 | 9195 | |
f475f163 | 9196 | restart_timer: |
1da177e4 LT |
9197 | tp->timer.expires = jiffies + tp->timer_offset; |
9198 | add_timer(&tp->timer); | |
9199 | } | |
9200 | ||
4f125f42 | 9201 | static int tg3_request_irq(struct tg3 *tp, int irq_num) |
fcfa0a32 | 9202 | { |
7d12e780 | 9203 | irq_handler_t fn; |
fcfa0a32 | 9204 | unsigned long flags; |
4f125f42 MC |
9205 | char *name; |
9206 | struct tg3_napi *tnapi = &tp->napi[irq_num]; | |
9207 | ||
9208 | if (tp->irq_cnt == 1) | |
9209 | name = tp->dev->name; | |
9210 | else { | |
9211 | name = &tnapi->irq_lbl[0]; | |
9212 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); | |
9213 | name[IFNAMSIZ-1] = 0; | |
9214 | } | |
fcfa0a32 | 9215 | |
63c3a66f | 9216 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
fcfa0a32 | 9217 | fn = tg3_msi; |
63c3a66f | 9218 | if (tg3_flag(tp, 1SHOT_MSI)) |
fcfa0a32 | 9219 | fn = tg3_msi_1shot; |
ab392d2d | 9220 | flags = 0; |
fcfa0a32 MC |
9221 | } else { |
9222 | fn = tg3_interrupt; | |
63c3a66f | 9223 | if (tg3_flag(tp, TAGGED_STATUS)) |
fcfa0a32 | 9224 | fn = tg3_interrupt_tagged; |
ab392d2d | 9225 | flags = IRQF_SHARED; |
fcfa0a32 | 9226 | } |
4f125f42 MC |
9227 | |
9228 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); | |
fcfa0a32 MC |
9229 | } |
9230 | ||
7938109f MC |
9231 | static int tg3_test_interrupt(struct tg3 *tp) |
9232 | { | |
09943a18 | 9233 | struct tg3_napi *tnapi = &tp->napi[0]; |
7938109f | 9234 | struct net_device *dev = tp->dev; |
b16250e3 | 9235 | int err, i, intr_ok = 0; |
f6eb9b1f | 9236 | u32 val; |
7938109f | 9237 | |
d4bc3927 MC |
9238 | if (!netif_running(dev)) |
9239 | return -ENODEV; | |
9240 | ||
7938109f MC |
9241 | tg3_disable_ints(tp); |
9242 | ||
4f125f42 | 9243 | free_irq(tnapi->irq_vec, tnapi); |
7938109f | 9244 | |
f6eb9b1f MC |
9245 | /* |
9246 | * Turn off MSI one shot mode. Otherwise this test has no | |
9247 | * observable way to know whether the interrupt was delivered. | |
9248 | */ | |
3aa1cdf8 | 9249 | if (tg3_flag(tp, 57765_PLUS)) { |
f6eb9b1f MC |
9250 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; |
9251 | tw32(MSGINT_MODE, val); | |
9252 | } | |
9253 | ||
4f125f42 | 9254 | err = request_irq(tnapi->irq_vec, tg3_test_isr, |
09943a18 | 9255 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi); |
7938109f MC |
9256 | if (err) |
9257 | return err; | |
9258 | ||
898a56f8 | 9259 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; |
7938109f MC |
9260 | tg3_enable_ints(tp); |
9261 | ||
9262 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 9263 | tnapi->coal_now); |
7938109f MC |
9264 | |
9265 | for (i = 0; i < 5; i++) { | |
b16250e3 MC |
9266 | u32 int_mbox, misc_host_ctrl; |
9267 | ||
898a56f8 | 9268 | int_mbox = tr32_mailbox(tnapi->int_mbox); |
b16250e3 MC |
9269 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
9270 | ||
9271 | if ((int_mbox != 0) || | |
9272 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
9273 | intr_ok = 1; | |
7938109f | 9274 | break; |
b16250e3 MC |
9275 | } |
9276 | ||
3aa1cdf8 MC |
9277 | if (tg3_flag(tp, 57765_PLUS) && |
9278 | tnapi->hw_status->status_tag != tnapi->last_tag) | |
9279 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | |
9280 | ||
7938109f MC |
9281 | msleep(10); |
9282 | } | |
9283 | ||
9284 | tg3_disable_ints(tp); | |
9285 | ||
4f125f42 | 9286 | free_irq(tnapi->irq_vec, tnapi); |
6aa20a22 | 9287 | |
4f125f42 | 9288 | err = tg3_request_irq(tp, 0); |
7938109f MC |
9289 | |
9290 | if (err) | |
9291 | return err; | |
9292 | ||
f6eb9b1f MC |
9293 | if (intr_ok) { |
9294 | /* Reenable MSI one shot mode. */ | |
3aa1cdf8 | 9295 | if (tg3_flag(tp, 57765_PLUS)) { |
f6eb9b1f MC |
9296 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; |
9297 | tw32(MSGINT_MODE, val); | |
9298 | } | |
7938109f | 9299 | return 0; |
f6eb9b1f | 9300 | } |
7938109f MC |
9301 | |
9302 | return -EIO; | |
9303 | } | |
9304 | ||
9305 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
9306 | * successfully restored | |
9307 | */ | |
9308 | static int tg3_test_msi(struct tg3 *tp) | |
9309 | { | |
7938109f MC |
9310 | int err; |
9311 | u16 pci_cmd; | |
9312 | ||
63c3a66f | 9313 | if (!tg3_flag(tp, USING_MSI)) |
7938109f MC |
9314 | return 0; |
9315 | ||
9316 | /* Turn off SERR reporting in case MSI terminates with Master | |
9317 | * Abort. | |
9318 | */ | |
9319 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
9320 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
9321 | pci_cmd & ~PCI_COMMAND_SERR); | |
9322 | ||
9323 | err = tg3_test_interrupt(tp); | |
9324 | ||
9325 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
9326 | ||
9327 | if (!err) | |
9328 | return 0; | |
9329 | ||
9330 | /* other failures */ | |
9331 | if (err != -EIO) | |
9332 | return err; | |
9333 | ||
9334 | /* MSI test failed, go back to INTx mode */ | |
5129c3a3 MC |
9335 | netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " |
9336 | "to INTx mode. Please report this failure to the PCI " | |
9337 | "maintainer and include system chipset information\n"); | |
7938109f | 9338 | |
4f125f42 | 9339 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
09943a18 | 9340 | |
7938109f MC |
9341 | pci_disable_msi(tp->pdev); |
9342 | ||
63c3a66f | 9343 | tg3_flag_clear(tp, USING_MSI); |
dc8bf1b1 | 9344 | tp->napi[0].irq_vec = tp->pdev->irq; |
7938109f | 9345 | |
4f125f42 | 9346 | err = tg3_request_irq(tp, 0); |
7938109f MC |
9347 | if (err) |
9348 | return err; | |
9349 | ||
9350 | /* Need to reset the chip because the MSI cycle may have terminated | |
9351 | * with Master Abort. | |
9352 | */ | |
f47c11ee | 9353 | tg3_full_lock(tp, 1); |
7938109f | 9354 | |
944d980e | 9355 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
8e7a22e3 | 9356 | err = tg3_init_hw(tp, 1); |
7938109f | 9357 | |
f47c11ee | 9358 | tg3_full_unlock(tp); |
7938109f MC |
9359 | |
9360 | if (err) | |
4f125f42 | 9361 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
7938109f MC |
9362 | |
9363 | return err; | |
9364 | } | |
9365 | ||
9e9fd12d MC |
9366 | static int tg3_request_firmware(struct tg3 *tp) |
9367 | { | |
9368 | const __be32 *fw_data; | |
9369 | ||
9370 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
05dbe005 JP |
9371 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", |
9372 | tp->fw_needed); | |
9e9fd12d MC |
9373 | return -ENOENT; |
9374 | } | |
9375 | ||
9376 | fw_data = (void *)tp->fw->data; | |
9377 | ||
9378 | /* Firmware blob starts with version numbers, followed by | |
9379 | * start address and _full_ length including BSS sections | |
9380 | * (which must be longer than the actual data, of course | |
9381 | */ | |
9382 | ||
9383 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
9384 | if (tp->fw_len < (tp->fw->size - 12)) { | |
05dbe005 JP |
9385 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", |
9386 | tp->fw_len, tp->fw_needed); | |
9e9fd12d MC |
9387 | release_firmware(tp->fw); |
9388 | tp->fw = NULL; | |
9389 | return -EINVAL; | |
9390 | } | |
9391 | ||
9392 | /* We no longer need firmware; we have it. */ | |
9393 | tp->fw_needed = NULL; | |
9394 | return 0; | |
9395 | } | |
9396 | ||
679563f4 MC |
9397 | static bool tg3_enable_msix(struct tg3 *tp) |
9398 | { | |
9399 | int i, rc, cpus = num_online_cpus(); | |
9400 | struct msix_entry msix_ent[tp->irq_max]; | |
9401 | ||
9402 | if (cpus == 1) | |
9403 | /* Just fallback to the simpler MSI mode. */ | |
9404 | return false; | |
9405 | ||
9406 | /* | |
9407 | * We want as many rx rings enabled as there are cpus. | |
9408 | * The first MSIX vector only deals with link interrupts, etc, | |
9409 | * so we add one to the number of vectors we are requesting. | |
9410 | */ | |
9411 | tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max); | |
9412 | ||
9413 | for (i = 0; i < tp->irq_max; i++) { | |
9414 | msix_ent[i].entry = i; | |
9415 | msix_ent[i].vector = 0; | |
9416 | } | |
9417 | ||
9418 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); | |
2430b031 MC |
9419 | if (rc < 0) { |
9420 | return false; | |
9421 | } else if (rc != 0) { | |
679563f4 MC |
9422 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) |
9423 | return false; | |
05dbe005 JP |
9424 | netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", |
9425 | tp->irq_cnt, rc); | |
679563f4 MC |
9426 | tp->irq_cnt = rc; |
9427 | } | |
9428 | ||
9429 | for (i = 0; i < tp->irq_max; i++) | |
9430 | tp->napi[i].irq_vec = msix_ent[i].vector; | |
9431 | ||
2ddaad39 BH |
9432 | netif_set_real_num_tx_queues(tp->dev, 1); |
9433 | rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1; | |
9434 | if (netif_set_real_num_rx_queues(tp->dev, rc)) { | |
9435 | pci_disable_msix(tp->pdev); | |
9436 | return false; | |
9437 | } | |
b92b9040 MC |
9438 | |
9439 | if (tp->irq_cnt > 1) { | |
63c3a66f | 9440 | tg3_flag_set(tp, ENABLE_RSS); |
d78b59f5 MC |
9441 | |
9442 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
9443 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
63c3a66f | 9444 | tg3_flag_set(tp, ENABLE_TSS); |
b92b9040 MC |
9445 | netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1); |
9446 | } | |
9447 | } | |
2430b031 | 9448 | |
679563f4 MC |
9449 | return true; |
9450 | } | |
9451 | ||
07b0173c MC |
9452 | static void tg3_ints_init(struct tg3 *tp) |
9453 | { | |
63c3a66f JP |
9454 | if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && |
9455 | !tg3_flag(tp, TAGGED_STATUS)) { | |
07b0173c MC |
9456 | /* All MSI supporting chips should support tagged |
9457 | * status. Assert that this is the case. | |
9458 | */ | |
5129c3a3 MC |
9459 | netdev_warn(tp->dev, |
9460 | "MSI without TAGGED_STATUS? Not using MSI\n"); | |
679563f4 | 9461 | goto defcfg; |
07b0173c | 9462 | } |
4f125f42 | 9463 | |
63c3a66f JP |
9464 | if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) |
9465 | tg3_flag_set(tp, USING_MSIX); | |
9466 | else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) | |
9467 | tg3_flag_set(tp, USING_MSI); | |
679563f4 | 9468 | |
63c3a66f | 9469 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
679563f4 | 9470 | u32 msi_mode = tr32(MSGINT_MODE); |
63c3a66f | 9471 | if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) |
baf8a94a | 9472 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; |
679563f4 MC |
9473 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); |
9474 | } | |
9475 | defcfg: | |
63c3a66f | 9476 | if (!tg3_flag(tp, USING_MSIX)) { |
679563f4 MC |
9477 | tp->irq_cnt = 1; |
9478 | tp->napi[0].irq_vec = tp->pdev->irq; | |
2ddaad39 | 9479 | netif_set_real_num_tx_queues(tp->dev, 1); |
85407885 | 9480 | netif_set_real_num_rx_queues(tp->dev, 1); |
679563f4 | 9481 | } |
07b0173c MC |
9482 | } |
9483 | ||
9484 | static void tg3_ints_fini(struct tg3 *tp) | |
9485 | { | |
63c3a66f | 9486 | if (tg3_flag(tp, USING_MSIX)) |
679563f4 | 9487 | pci_disable_msix(tp->pdev); |
63c3a66f | 9488 | else if (tg3_flag(tp, USING_MSI)) |
679563f4 | 9489 | pci_disable_msi(tp->pdev); |
63c3a66f JP |
9490 | tg3_flag_clear(tp, USING_MSI); |
9491 | tg3_flag_clear(tp, USING_MSIX); | |
9492 | tg3_flag_clear(tp, ENABLE_RSS); | |
9493 | tg3_flag_clear(tp, ENABLE_TSS); | |
07b0173c MC |
9494 | } |
9495 | ||
1da177e4 LT |
9496 | static int tg3_open(struct net_device *dev) |
9497 | { | |
9498 | struct tg3 *tp = netdev_priv(dev); | |
4f125f42 | 9499 | int i, err; |
1da177e4 | 9500 | |
9e9fd12d MC |
9501 | if (tp->fw_needed) { |
9502 | err = tg3_request_firmware(tp); | |
9503 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
9504 | if (err) | |
9505 | return err; | |
9506 | } else if (err) { | |
05dbe005 | 9507 | netdev_warn(tp->dev, "TSO capability disabled\n"); |
63c3a66f JP |
9508 | tg3_flag_clear(tp, TSO_CAPABLE); |
9509 | } else if (!tg3_flag(tp, TSO_CAPABLE)) { | |
05dbe005 | 9510 | netdev_notice(tp->dev, "TSO capability restored\n"); |
63c3a66f | 9511 | tg3_flag_set(tp, TSO_CAPABLE); |
9e9fd12d MC |
9512 | } |
9513 | } | |
9514 | ||
c49a1561 MC |
9515 | netif_carrier_off(tp->dev); |
9516 | ||
c866b7ea | 9517 | err = tg3_power_up(tp); |
2f751b67 | 9518 | if (err) |
bc1c7567 | 9519 | return err; |
2f751b67 MC |
9520 | |
9521 | tg3_full_lock(tp, 0); | |
bc1c7567 | 9522 | |
1da177e4 | 9523 | tg3_disable_ints(tp); |
63c3a66f | 9524 | tg3_flag_clear(tp, INIT_COMPLETE); |
1da177e4 | 9525 | |
f47c11ee | 9526 | tg3_full_unlock(tp); |
1da177e4 | 9527 | |
679563f4 MC |
9528 | /* |
9529 | * Setup interrupts first so we know how | |
9530 | * many NAPI resources to allocate | |
9531 | */ | |
9532 | tg3_ints_init(tp); | |
9533 | ||
1da177e4 LT |
9534 | /* The placement of this call is tied |
9535 | * to the setup and use of Host TX descriptors. | |
9536 | */ | |
9537 | err = tg3_alloc_consistent(tp); | |
9538 | if (err) | |
679563f4 | 9539 | goto err_out1; |
88b06bc2 | 9540 | |
66cfd1bd MC |
9541 | tg3_napi_init(tp); |
9542 | ||
fed97810 | 9543 | tg3_napi_enable(tp); |
1da177e4 | 9544 | |
4f125f42 MC |
9545 | for (i = 0; i < tp->irq_cnt; i++) { |
9546 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9547 | err = tg3_request_irq(tp, i); | |
9548 | if (err) { | |
9549 | for (i--; i >= 0; i--) | |
9550 | free_irq(tnapi->irq_vec, tnapi); | |
9551 | break; | |
9552 | } | |
9553 | } | |
1da177e4 | 9554 | |
07b0173c | 9555 | if (err) |
679563f4 | 9556 | goto err_out2; |
bea3348e | 9557 | |
f47c11ee | 9558 | tg3_full_lock(tp, 0); |
1da177e4 | 9559 | |
8e7a22e3 | 9560 | err = tg3_init_hw(tp, 1); |
1da177e4 | 9561 | if (err) { |
944d980e | 9562 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
9563 | tg3_free_rings(tp); |
9564 | } else { | |
0e6cf6a9 MC |
9565 | if (tg3_flag(tp, TAGGED_STATUS) && |
9566 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | |
9567 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) | |
fac9b83e DM |
9568 | tp->timer_offset = HZ; |
9569 | else | |
9570 | tp->timer_offset = HZ / 10; | |
9571 | ||
9572 | BUG_ON(tp->timer_offset > HZ); | |
9573 | tp->timer_counter = tp->timer_multiplier = | |
9574 | (HZ / tp->timer_offset); | |
9575 | tp->asf_counter = tp->asf_multiplier = | |
28fbef78 | 9576 | ((HZ / tp->timer_offset) * 2); |
1da177e4 LT |
9577 | |
9578 | init_timer(&tp->timer); | |
9579 | tp->timer.expires = jiffies + tp->timer_offset; | |
9580 | tp->timer.data = (unsigned long) tp; | |
9581 | tp->timer.function = tg3_timer; | |
1da177e4 LT |
9582 | } |
9583 | ||
f47c11ee | 9584 | tg3_full_unlock(tp); |
1da177e4 | 9585 | |
07b0173c | 9586 | if (err) |
679563f4 | 9587 | goto err_out3; |
1da177e4 | 9588 | |
63c3a66f | 9589 | if (tg3_flag(tp, USING_MSI)) { |
7938109f | 9590 | err = tg3_test_msi(tp); |
fac9b83e | 9591 | |
7938109f | 9592 | if (err) { |
f47c11ee | 9593 | tg3_full_lock(tp, 0); |
944d980e | 9594 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
7938109f | 9595 | tg3_free_rings(tp); |
f47c11ee | 9596 | tg3_full_unlock(tp); |
7938109f | 9597 | |
679563f4 | 9598 | goto err_out2; |
7938109f | 9599 | } |
fcfa0a32 | 9600 | |
63c3a66f | 9601 | if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { |
f6eb9b1f | 9602 | u32 val = tr32(PCIE_TRANSACTION_CFG); |
fcfa0a32 | 9603 | |
f6eb9b1f MC |
9604 | tw32(PCIE_TRANSACTION_CFG, |
9605 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
fcfa0a32 | 9606 | } |
7938109f MC |
9607 | } |
9608 | ||
b02fd9e3 MC |
9609 | tg3_phy_start(tp); |
9610 | ||
f47c11ee | 9611 | tg3_full_lock(tp, 0); |
1da177e4 | 9612 | |
7938109f | 9613 | add_timer(&tp->timer); |
63c3a66f | 9614 | tg3_flag_set(tp, INIT_COMPLETE); |
1da177e4 LT |
9615 | tg3_enable_ints(tp); |
9616 | ||
f47c11ee | 9617 | tg3_full_unlock(tp); |
1da177e4 | 9618 | |
fe5f5787 | 9619 | netif_tx_start_all_queues(dev); |
1da177e4 | 9620 | |
06c03c02 MB |
9621 | /* |
9622 | * Reset loopback feature if it was turned on while the device was down | |
9623 | * make sure that it's installed properly now. | |
9624 | */ | |
9625 | if (dev->features & NETIF_F_LOOPBACK) | |
9626 | tg3_set_loopback(dev, dev->features); | |
9627 | ||
1da177e4 | 9628 | return 0; |
07b0173c | 9629 | |
679563f4 | 9630 | err_out3: |
4f125f42 MC |
9631 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9632 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9633 | free_irq(tnapi->irq_vec, tnapi); | |
9634 | } | |
07b0173c | 9635 | |
679563f4 | 9636 | err_out2: |
fed97810 | 9637 | tg3_napi_disable(tp); |
66cfd1bd | 9638 | tg3_napi_fini(tp); |
07b0173c | 9639 | tg3_free_consistent(tp); |
679563f4 MC |
9640 | |
9641 | err_out1: | |
9642 | tg3_ints_fini(tp); | |
cd0d7228 MC |
9643 | tg3_frob_aux_power(tp, false); |
9644 | pci_set_power_state(tp->pdev, PCI_D3hot); | |
07b0173c | 9645 | return err; |
1da177e4 LT |
9646 | } |
9647 | ||
511d2224 ED |
9648 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *, |
9649 | struct rtnl_link_stats64 *); | |
1da177e4 LT |
9650 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *); |
9651 | ||
9652 | static int tg3_close(struct net_device *dev) | |
9653 | { | |
4f125f42 | 9654 | int i; |
1da177e4 LT |
9655 | struct tg3 *tp = netdev_priv(dev); |
9656 | ||
fed97810 | 9657 | tg3_napi_disable(tp); |
28e53bdd | 9658 | cancel_work_sync(&tp->reset_task); |
7faa006f | 9659 | |
fe5f5787 | 9660 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
9661 | |
9662 | del_timer_sync(&tp->timer); | |
9663 | ||
24bb4fb6 MC |
9664 | tg3_phy_stop(tp); |
9665 | ||
f47c11ee | 9666 | tg3_full_lock(tp, 1); |
1da177e4 LT |
9667 | |
9668 | tg3_disable_ints(tp); | |
9669 | ||
944d980e | 9670 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 9671 | tg3_free_rings(tp); |
63c3a66f | 9672 | tg3_flag_clear(tp, INIT_COMPLETE); |
1da177e4 | 9673 | |
f47c11ee | 9674 | tg3_full_unlock(tp); |
1da177e4 | 9675 | |
4f125f42 MC |
9676 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9677 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9678 | free_irq(tnapi->irq_vec, tnapi); | |
9679 | } | |
07b0173c MC |
9680 | |
9681 | tg3_ints_fini(tp); | |
1da177e4 | 9682 | |
511d2224 ED |
9683 | tg3_get_stats64(tp->dev, &tp->net_stats_prev); |
9684 | ||
1da177e4 LT |
9685 | memcpy(&tp->estats_prev, tg3_get_estats(tp), |
9686 | sizeof(tp->estats_prev)); | |
9687 | ||
66cfd1bd MC |
9688 | tg3_napi_fini(tp); |
9689 | ||
1da177e4 LT |
9690 | tg3_free_consistent(tp); |
9691 | ||
c866b7ea | 9692 | tg3_power_down(tp); |
bc1c7567 MC |
9693 | |
9694 | netif_carrier_off(tp->dev); | |
9695 | ||
1da177e4 LT |
9696 | return 0; |
9697 | } | |
9698 | ||
511d2224 | 9699 | static inline u64 get_stat64(tg3_stat64_t *val) |
816f8b86 SB |
9700 | { |
9701 | return ((u64)val->high << 32) | ((u64)val->low); | |
9702 | } | |
9703 | ||
511d2224 | 9704 | static u64 calc_crc_errors(struct tg3 *tp) |
1da177e4 LT |
9705 | { |
9706 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9707 | ||
f07e9af3 | 9708 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
1da177e4 LT |
9709 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
9710 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
1da177e4 LT |
9711 | u32 val; |
9712 | ||
f47c11ee | 9713 | spin_lock_bh(&tp->lock); |
569a5df8 MC |
9714 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
9715 | tg3_writephy(tp, MII_TG3_TEST1, | |
9716 | val | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 9717 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); |
1da177e4 LT |
9718 | } else |
9719 | val = 0; | |
f47c11ee | 9720 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
9721 | |
9722 | tp->phy_crc_errors += val; | |
9723 | ||
9724 | return tp->phy_crc_errors; | |
9725 | } | |
9726 | ||
9727 | return get_stat64(&hw_stats->rx_fcs_errors); | |
9728 | } | |
9729 | ||
9730 | #define ESTAT_ADD(member) \ | |
9731 | estats->member = old_estats->member + \ | |
511d2224 | 9732 | get_stat64(&hw_stats->member) |
1da177e4 LT |
9733 | |
9734 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) | |
9735 | { | |
9736 | struct tg3_ethtool_stats *estats = &tp->estats; | |
9737 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; | |
9738 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9739 | ||
9740 | if (!hw_stats) | |
9741 | return old_estats; | |
9742 | ||
9743 | ESTAT_ADD(rx_octets); | |
9744 | ESTAT_ADD(rx_fragments); | |
9745 | ESTAT_ADD(rx_ucast_packets); | |
9746 | ESTAT_ADD(rx_mcast_packets); | |
9747 | ESTAT_ADD(rx_bcast_packets); | |
9748 | ESTAT_ADD(rx_fcs_errors); | |
9749 | ESTAT_ADD(rx_align_errors); | |
9750 | ESTAT_ADD(rx_xon_pause_rcvd); | |
9751 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
9752 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
9753 | ESTAT_ADD(rx_xoff_entered); | |
9754 | ESTAT_ADD(rx_frame_too_long_errors); | |
9755 | ESTAT_ADD(rx_jabbers); | |
9756 | ESTAT_ADD(rx_undersize_packets); | |
9757 | ESTAT_ADD(rx_in_length_errors); | |
9758 | ESTAT_ADD(rx_out_length_errors); | |
9759 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
9760 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
9761 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
9762 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
9763 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
9764 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
9765 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
9766 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
9767 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
9768 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
9769 | ||
9770 | ESTAT_ADD(tx_octets); | |
9771 | ESTAT_ADD(tx_collisions); | |
9772 | ESTAT_ADD(tx_xon_sent); | |
9773 | ESTAT_ADD(tx_xoff_sent); | |
9774 | ESTAT_ADD(tx_flow_control); | |
9775 | ESTAT_ADD(tx_mac_errors); | |
9776 | ESTAT_ADD(tx_single_collisions); | |
9777 | ESTAT_ADD(tx_mult_collisions); | |
9778 | ESTAT_ADD(tx_deferred); | |
9779 | ESTAT_ADD(tx_excessive_collisions); | |
9780 | ESTAT_ADD(tx_late_collisions); | |
9781 | ESTAT_ADD(tx_collide_2times); | |
9782 | ESTAT_ADD(tx_collide_3times); | |
9783 | ESTAT_ADD(tx_collide_4times); | |
9784 | ESTAT_ADD(tx_collide_5times); | |
9785 | ESTAT_ADD(tx_collide_6times); | |
9786 | ESTAT_ADD(tx_collide_7times); | |
9787 | ESTAT_ADD(tx_collide_8times); | |
9788 | ESTAT_ADD(tx_collide_9times); | |
9789 | ESTAT_ADD(tx_collide_10times); | |
9790 | ESTAT_ADD(tx_collide_11times); | |
9791 | ESTAT_ADD(tx_collide_12times); | |
9792 | ESTAT_ADD(tx_collide_13times); | |
9793 | ESTAT_ADD(tx_collide_14times); | |
9794 | ESTAT_ADD(tx_collide_15times); | |
9795 | ESTAT_ADD(tx_ucast_packets); | |
9796 | ESTAT_ADD(tx_mcast_packets); | |
9797 | ESTAT_ADD(tx_bcast_packets); | |
9798 | ESTAT_ADD(tx_carrier_sense_errors); | |
9799 | ESTAT_ADD(tx_discards); | |
9800 | ESTAT_ADD(tx_errors); | |
9801 | ||
9802 | ESTAT_ADD(dma_writeq_full); | |
9803 | ESTAT_ADD(dma_write_prioq_full); | |
9804 | ESTAT_ADD(rxbds_empty); | |
9805 | ESTAT_ADD(rx_discards); | |
9806 | ESTAT_ADD(rx_errors); | |
9807 | ESTAT_ADD(rx_threshold_hit); | |
9808 | ||
9809 | ESTAT_ADD(dma_readq_full); | |
9810 | ESTAT_ADD(dma_read_prioq_full); | |
9811 | ESTAT_ADD(tx_comp_queue_full); | |
9812 | ||
9813 | ESTAT_ADD(ring_set_send_prod_index); | |
9814 | ESTAT_ADD(ring_status_update); | |
9815 | ESTAT_ADD(nic_irqs); | |
9816 | ESTAT_ADD(nic_avoided_irqs); | |
9817 | ESTAT_ADD(nic_tx_threshold_hit); | |
9818 | ||
4452d099 MC |
9819 | ESTAT_ADD(mbuf_lwm_thresh_hit); |
9820 | ||
1da177e4 LT |
9821 | return estats; |
9822 | } | |
9823 | ||
511d2224 ED |
9824 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev, |
9825 | struct rtnl_link_stats64 *stats) | |
1da177e4 LT |
9826 | { |
9827 | struct tg3 *tp = netdev_priv(dev); | |
511d2224 | 9828 | struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; |
1da177e4 LT |
9829 | struct tg3_hw_stats *hw_stats = tp->hw_stats; |
9830 | ||
9831 | if (!hw_stats) | |
9832 | return old_stats; | |
9833 | ||
9834 | stats->rx_packets = old_stats->rx_packets + | |
9835 | get_stat64(&hw_stats->rx_ucast_packets) + | |
9836 | get_stat64(&hw_stats->rx_mcast_packets) + | |
9837 | get_stat64(&hw_stats->rx_bcast_packets); | |
6aa20a22 | 9838 | |
1da177e4 LT |
9839 | stats->tx_packets = old_stats->tx_packets + |
9840 | get_stat64(&hw_stats->tx_ucast_packets) + | |
9841 | get_stat64(&hw_stats->tx_mcast_packets) + | |
9842 | get_stat64(&hw_stats->tx_bcast_packets); | |
9843 | ||
9844 | stats->rx_bytes = old_stats->rx_bytes + | |
9845 | get_stat64(&hw_stats->rx_octets); | |
9846 | stats->tx_bytes = old_stats->tx_bytes + | |
9847 | get_stat64(&hw_stats->tx_octets); | |
9848 | ||
9849 | stats->rx_errors = old_stats->rx_errors + | |
4f63b877 | 9850 | get_stat64(&hw_stats->rx_errors); |
1da177e4 LT |
9851 | stats->tx_errors = old_stats->tx_errors + |
9852 | get_stat64(&hw_stats->tx_errors) + | |
9853 | get_stat64(&hw_stats->tx_mac_errors) + | |
9854 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
9855 | get_stat64(&hw_stats->tx_discards); | |
9856 | ||
9857 | stats->multicast = old_stats->multicast + | |
9858 | get_stat64(&hw_stats->rx_mcast_packets); | |
9859 | stats->collisions = old_stats->collisions + | |
9860 | get_stat64(&hw_stats->tx_collisions); | |
9861 | ||
9862 | stats->rx_length_errors = old_stats->rx_length_errors + | |
9863 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
9864 | get_stat64(&hw_stats->rx_undersize_packets); | |
9865 | ||
9866 | stats->rx_over_errors = old_stats->rx_over_errors + | |
9867 | get_stat64(&hw_stats->rxbds_empty); | |
9868 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
9869 | get_stat64(&hw_stats->rx_align_errors); | |
9870 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
9871 | get_stat64(&hw_stats->tx_discards); | |
9872 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
9873 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
9874 | ||
9875 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
9876 | calc_crc_errors(tp); | |
9877 | ||
4f63b877 JL |
9878 | stats->rx_missed_errors = old_stats->rx_missed_errors + |
9879 | get_stat64(&hw_stats->rx_discards); | |
9880 | ||
b0057c51 ED |
9881 | stats->rx_dropped = tp->rx_dropped; |
9882 | ||
1da177e4 LT |
9883 | return stats; |
9884 | } | |
9885 | ||
9886 | static inline u32 calc_crc(unsigned char *buf, int len) | |
9887 | { | |
9888 | u32 reg; | |
9889 | u32 tmp; | |
9890 | int j, k; | |
9891 | ||
9892 | reg = 0xffffffff; | |
9893 | ||
9894 | for (j = 0; j < len; j++) { | |
9895 | reg ^= buf[j]; | |
9896 | ||
9897 | for (k = 0; k < 8; k++) { | |
9898 | tmp = reg & 0x01; | |
9899 | ||
9900 | reg >>= 1; | |
9901 | ||
859a5887 | 9902 | if (tmp) |
1da177e4 | 9903 | reg ^= 0xedb88320; |
1da177e4 LT |
9904 | } |
9905 | } | |
9906 | ||
9907 | return ~reg; | |
9908 | } | |
9909 | ||
9910 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
9911 | { | |
9912 | /* accept or reject all multicast frames */ | |
9913 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
9914 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
9915 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
9916 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
9917 | } | |
9918 | ||
9919 | static void __tg3_set_rx_mode(struct net_device *dev) | |
9920 | { | |
9921 | struct tg3 *tp = netdev_priv(dev); | |
9922 | u32 rx_mode; | |
9923 | ||
9924 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
9925 | RX_MODE_KEEP_VLAN_TAG); | |
9926 | ||
bf933c80 | 9927 | #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE) |
1da177e4 LT |
9928 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG |
9929 | * flag clear. | |
9930 | */ | |
63c3a66f | 9931 | if (!tg3_flag(tp, ENABLE_ASF)) |
1da177e4 LT |
9932 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; |
9933 | #endif | |
9934 | ||
9935 | if (dev->flags & IFF_PROMISC) { | |
9936 | /* Promiscuous mode. */ | |
9937 | rx_mode |= RX_MODE_PROMISC; | |
9938 | } else if (dev->flags & IFF_ALLMULTI) { | |
9939 | /* Accept all multicast. */ | |
de6f31eb | 9940 | tg3_set_multi(tp, 1); |
4cd24eaf | 9941 | } else if (netdev_mc_empty(dev)) { |
1da177e4 | 9942 | /* Reject all multicast. */ |
de6f31eb | 9943 | tg3_set_multi(tp, 0); |
1da177e4 LT |
9944 | } else { |
9945 | /* Accept one or more multicast(s). */ | |
22bedad3 | 9946 | struct netdev_hw_addr *ha; |
1da177e4 LT |
9947 | u32 mc_filter[4] = { 0, }; |
9948 | u32 regidx; | |
9949 | u32 bit; | |
9950 | u32 crc; | |
9951 | ||
22bedad3 JP |
9952 | netdev_for_each_mc_addr(ha, dev) { |
9953 | crc = calc_crc(ha->addr, ETH_ALEN); | |
1da177e4 LT |
9954 | bit = ~crc & 0x7f; |
9955 | regidx = (bit & 0x60) >> 5; | |
9956 | bit &= 0x1f; | |
9957 | mc_filter[regidx] |= (1 << bit); | |
9958 | } | |
9959 | ||
9960 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
9961 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
9962 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
9963 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
9964 | } | |
9965 | ||
9966 | if (rx_mode != tp->rx_mode) { | |
9967 | tp->rx_mode = rx_mode; | |
9968 | tw32_f(MAC_RX_MODE, rx_mode); | |
9969 | udelay(10); | |
9970 | } | |
9971 | } | |
9972 | ||
9973 | static void tg3_set_rx_mode(struct net_device *dev) | |
9974 | { | |
9975 | struct tg3 *tp = netdev_priv(dev); | |
9976 | ||
e75f7c90 MC |
9977 | if (!netif_running(dev)) |
9978 | return; | |
9979 | ||
f47c11ee | 9980 | tg3_full_lock(tp, 0); |
1da177e4 | 9981 | __tg3_set_rx_mode(dev); |
f47c11ee | 9982 | tg3_full_unlock(tp); |
1da177e4 LT |
9983 | } |
9984 | ||
1da177e4 LT |
9985 | static int tg3_get_regs_len(struct net_device *dev) |
9986 | { | |
97bd8e49 | 9987 | return TG3_REG_BLK_SIZE; |
1da177e4 LT |
9988 | } |
9989 | ||
9990 | static void tg3_get_regs(struct net_device *dev, | |
9991 | struct ethtool_regs *regs, void *_p) | |
9992 | { | |
1da177e4 | 9993 | struct tg3 *tp = netdev_priv(dev); |
1da177e4 LT |
9994 | |
9995 | regs->version = 0; | |
9996 | ||
97bd8e49 | 9997 | memset(_p, 0, TG3_REG_BLK_SIZE); |
1da177e4 | 9998 | |
80096068 | 9999 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10000 | return; |
10001 | ||
f47c11ee | 10002 | tg3_full_lock(tp, 0); |
1da177e4 | 10003 | |
97bd8e49 | 10004 | tg3_dump_legacy_regs(tp, (u32 *)_p); |
1da177e4 | 10005 | |
f47c11ee | 10006 | tg3_full_unlock(tp); |
1da177e4 LT |
10007 | } |
10008 | ||
10009 | static int tg3_get_eeprom_len(struct net_device *dev) | |
10010 | { | |
10011 | struct tg3 *tp = netdev_priv(dev); | |
10012 | ||
10013 | return tp->nvram_size; | |
10014 | } | |
10015 | ||
1da177e4 LT |
10016 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
10017 | { | |
10018 | struct tg3 *tp = netdev_priv(dev); | |
10019 | int ret; | |
10020 | u8 *pd; | |
b9fc7dc5 | 10021 | u32 i, offset, len, b_offset, b_count; |
a9dc529d | 10022 | __be32 val; |
1da177e4 | 10023 | |
63c3a66f | 10024 | if (tg3_flag(tp, NO_NVRAM)) |
df259d8c MC |
10025 | return -EINVAL; |
10026 | ||
80096068 | 10027 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10028 | return -EAGAIN; |
10029 | ||
1da177e4 LT |
10030 | offset = eeprom->offset; |
10031 | len = eeprom->len; | |
10032 | eeprom->len = 0; | |
10033 | ||
10034 | eeprom->magic = TG3_EEPROM_MAGIC; | |
10035 | ||
10036 | if (offset & 3) { | |
10037 | /* adjustments to start on required 4 byte boundary */ | |
10038 | b_offset = offset & 3; | |
10039 | b_count = 4 - b_offset; | |
10040 | if (b_count > len) { | |
10041 | /* i.e. offset=1 len=2 */ | |
10042 | b_count = len; | |
10043 | } | |
a9dc529d | 10044 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); |
1da177e4 LT |
10045 | if (ret) |
10046 | return ret; | |
be98da6a | 10047 | memcpy(data, ((char *)&val) + b_offset, b_count); |
1da177e4 LT |
10048 | len -= b_count; |
10049 | offset += b_count; | |
c6cdf436 | 10050 | eeprom->len += b_count; |
1da177e4 LT |
10051 | } |
10052 | ||
25985edc | 10053 | /* read bytes up to the last 4 byte boundary */ |
1da177e4 LT |
10054 | pd = &data[eeprom->len]; |
10055 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
a9dc529d | 10056 | ret = tg3_nvram_read_be32(tp, offset + i, &val); |
1da177e4 LT |
10057 | if (ret) { |
10058 | eeprom->len += i; | |
10059 | return ret; | |
10060 | } | |
1da177e4 LT |
10061 | memcpy(pd + i, &val, 4); |
10062 | } | |
10063 | eeprom->len += i; | |
10064 | ||
10065 | if (len & 3) { | |
10066 | /* read last bytes not ending on 4 byte boundary */ | |
10067 | pd = &data[eeprom->len]; | |
10068 | b_count = len & 3; | |
10069 | b_offset = offset + len - b_count; | |
a9dc529d | 10070 | ret = tg3_nvram_read_be32(tp, b_offset, &val); |
1da177e4 LT |
10071 | if (ret) |
10072 | return ret; | |
b9fc7dc5 | 10073 | memcpy(pd, &val, b_count); |
1da177e4 LT |
10074 | eeprom->len += b_count; |
10075 | } | |
10076 | return 0; | |
10077 | } | |
10078 | ||
6aa20a22 | 10079 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); |
1da177e4 LT |
10080 | |
10081 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
10082 | { | |
10083 | struct tg3 *tp = netdev_priv(dev); | |
10084 | int ret; | |
b9fc7dc5 | 10085 | u32 offset, len, b_offset, odd_len; |
1da177e4 | 10086 | u8 *buf; |
a9dc529d | 10087 | __be32 start, end; |
1da177e4 | 10088 | |
80096068 | 10089 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10090 | return -EAGAIN; |
10091 | ||
63c3a66f | 10092 | if (tg3_flag(tp, NO_NVRAM) || |
df259d8c | 10093 | eeprom->magic != TG3_EEPROM_MAGIC) |
1da177e4 LT |
10094 | return -EINVAL; |
10095 | ||
10096 | offset = eeprom->offset; | |
10097 | len = eeprom->len; | |
10098 | ||
10099 | if ((b_offset = (offset & 3))) { | |
10100 | /* adjustments to start on required 4 byte boundary */ | |
a9dc529d | 10101 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); |
1da177e4 LT |
10102 | if (ret) |
10103 | return ret; | |
1da177e4 LT |
10104 | len += b_offset; |
10105 | offset &= ~3; | |
1c8594b4 MC |
10106 | if (len < 4) |
10107 | len = 4; | |
1da177e4 LT |
10108 | } |
10109 | ||
10110 | odd_len = 0; | |
1c8594b4 | 10111 | if (len & 3) { |
1da177e4 LT |
10112 | /* adjustments to end on required 4 byte boundary */ |
10113 | odd_len = 1; | |
10114 | len = (len + 3) & ~3; | |
a9dc529d | 10115 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); |
1da177e4 LT |
10116 | if (ret) |
10117 | return ret; | |
1da177e4 LT |
10118 | } |
10119 | ||
10120 | buf = data; | |
10121 | if (b_offset || odd_len) { | |
10122 | buf = kmalloc(len, GFP_KERNEL); | |
ab0049b4 | 10123 | if (!buf) |
1da177e4 LT |
10124 | return -ENOMEM; |
10125 | if (b_offset) | |
10126 | memcpy(buf, &start, 4); | |
10127 | if (odd_len) | |
10128 | memcpy(buf+len-4, &end, 4); | |
10129 | memcpy(buf + b_offset, data, eeprom->len); | |
10130 | } | |
10131 | ||
10132 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
10133 | ||
10134 | if (buf != data) | |
10135 | kfree(buf); | |
10136 | ||
10137 | return ret; | |
10138 | } | |
10139 | ||
10140 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
10141 | { | |
b02fd9e3 MC |
10142 | struct tg3 *tp = netdev_priv(dev); |
10143 | ||
63c3a66f | 10144 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 10145 | struct phy_device *phydev; |
f07e9af3 | 10146 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10147 | return -EAGAIN; |
3f0e3ad7 MC |
10148 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10149 | return phy_ethtool_gset(phydev, cmd); | |
b02fd9e3 | 10150 | } |
6aa20a22 | 10151 | |
1da177e4 LT |
10152 | cmd->supported = (SUPPORTED_Autoneg); |
10153 | ||
f07e9af3 | 10154 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
10155 | cmd->supported |= (SUPPORTED_1000baseT_Half | |
10156 | SUPPORTED_1000baseT_Full); | |
10157 | ||
f07e9af3 | 10158 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
1da177e4 LT |
10159 | cmd->supported |= (SUPPORTED_100baseT_Half | |
10160 | SUPPORTED_100baseT_Full | | |
10161 | SUPPORTED_10baseT_Half | | |
10162 | SUPPORTED_10baseT_Full | | |
3bebab59 | 10163 | SUPPORTED_TP); |
ef348144 KK |
10164 | cmd->port = PORT_TP; |
10165 | } else { | |
1da177e4 | 10166 | cmd->supported |= SUPPORTED_FIBRE; |
ef348144 KK |
10167 | cmd->port = PORT_FIBRE; |
10168 | } | |
6aa20a22 | 10169 | |
1da177e4 | 10170 | cmd->advertising = tp->link_config.advertising; |
5bb09778 MC |
10171 | if (tg3_flag(tp, PAUSE_AUTONEG)) { |
10172 | if (tp->link_config.flowctrl & FLOW_CTRL_RX) { | |
10173 | if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
10174 | cmd->advertising |= ADVERTISED_Pause; | |
10175 | } else { | |
10176 | cmd->advertising |= ADVERTISED_Pause | | |
10177 | ADVERTISED_Asym_Pause; | |
10178 | } | |
10179 | } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
10180 | cmd->advertising |= ADVERTISED_Asym_Pause; | |
10181 | } | |
10182 | } | |
1da177e4 | 10183 | if (netif_running(dev)) { |
70739497 | 10184 | ethtool_cmd_speed_set(cmd, tp->link_config.active_speed); |
1da177e4 | 10185 | cmd->duplex = tp->link_config.active_duplex; |
64c22182 | 10186 | } else { |
70739497 | 10187 | ethtool_cmd_speed_set(cmd, SPEED_INVALID); |
64c22182 | 10188 | cmd->duplex = DUPLEX_INVALID; |
1da177e4 | 10189 | } |
882e9793 | 10190 | cmd->phy_address = tp->phy_addr; |
7e5856bd | 10191 | cmd->transceiver = XCVR_INTERNAL; |
1da177e4 LT |
10192 | cmd->autoneg = tp->link_config.autoneg; |
10193 | cmd->maxtxpkt = 0; | |
10194 | cmd->maxrxpkt = 0; | |
10195 | return 0; | |
10196 | } | |
6aa20a22 | 10197 | |
1da177e4 LT |
10198 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
10199 | { | |
10200 | struct tg3 *tp = netdev_priv(dev); | |
25db0338 | 10201 | u32 speed = ethtool_cmd_speed(cmd); |
6aa20a22 | 10202 | |
63c3a66f | 10203 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 10204 | struct phy_device *phydev; |
f07e9af3 | 10205 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10206 | return -EAGAIN; |
3f0e3ad7 MC |
10207 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10208 | return phy_ethtool_sset(phydev, cmd); | |
b02fd9e3 MC |
10209 | } |
10210 | ||
7e5856bd MC |
10211 | if (cmd->autoneg != AUTONEG_ENABLE && |
10212 | cmd->autoneg != AUTONEG_DISABLE) | |
37ff238d | 10213 | return -EINVAL; |
7e5856bd MC |
10214 | |
10215 | if (cmd->autoneg == AUTONEG_DISABLE && | |
10216 | cmd->duplex != DUPLEX_FULL && | |
10217 | cmd->duplex != DUPLEX_HALF) | |
37ff238d | 10218 | return -EINVAL; |
1da177e4 | 10219 | |
7e5856bd MC |
10220 | if (cmd->autoneg == AUTONEG_ENABLE) { |
10221 | u32 mask = ADVERTISED_Autoneg | | |
10222 | ADVERTISED_Pause | | |
10223 | ADVERTISED_Asym_Pause; | |
10224 | ||
f07e9af3 | 10225 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
7e5856bd MC |
10226 | mask |= ADVERTISED_1000baseT_Half | |
10227 | ADVERTISED_1000baseT_Full; | |
10228 | ||
f07e9af3 | 10229 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
7e5856bd MC |
10230 | mask |= ADVERTISED_100baseT_Half | |
10231 | ADVERTISED_100baseT_Full | | |
10232 | ADVERTISED_10baseT_Half | | |
10233 | ADVERTISED_10baseT_Full | | |
10234 | ADVERTISED_TP; | |
10235 | else | |
10236 | mask |= ADVERTISED_FIBRE; | |
10237 | ||
10238 | if (cmd->advertising & ~mask) | |
10239 | return -EINVAL; | |
10240 | ||
10241 | mask &= (ADVERTISED_1000baseT_Half | | |
10242 | ADVERTISED_1000baseT_Full | | |
10243 | ADVERTISED_100baseT_Half | | |
10244 | ADVERTISED_100baseT_Full | | |
10245 | ADVERTISED_10baseT_Half | | |
10246 | ADVERTISED_10baseT_Full); | |
10247 | ||
10248 | cmd->advertising &= mask; | |
10249 | } else { | |
f07e9af3 | 10250 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { |
25db0338 | 10251 | if (speed != SPEED_1000) |
7e5856bd MC |
10252 | return -EINVAL; |
10253 | ||
10254 | if (cmd->duplex != DUPLEX_FULL) | |
10255 | return -EINVAL; | |
10256 | } else { | |
25db0338 DD |
10257 | if (speed != SPEED_100 && |
10258 | speed != SPEED_10) | |
7e5856bd MC |
10259 | return -EINVAL; |
10260 | } | |
10261 | } | |
10262 | ||
f47c11ee | 10263 | tg3_full_lock(tp, 0); |
1da177e4 LT |
10264 | |
10265 | tp->link_config.autoneg = cmd->autoneg; | |
10266 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
405d8e5c AG |
10267 | tp->link_config.advertising = (cmd->advertising | |
10268 | ADVERTISED_Autoneg); | |
1da177e4 LT |
10269 | tp->link_config.speed = SPEED_INVALID; |
10270 | tp->link_config.duplex = DUPLEX_INVALID; | |
10271 | } else { | |
10272 | tp->link_config.advertising = 0; | |
25db0338 | 10273 | tp->link_config.speed = speed; |
1da177e4 | 10274 | tp->link_config.duplex = cmd->duplex; |
b02fd9e3 | 10275 | } |
6aa20a22 | 10276 | |
24fcad6b MC |
10277 | tp->link_config.orig_speed = tp->link_config.speed; |
10278 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
10279 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
10280 | ||
1da177e4 LT |
10281 | if (netif_running(dev)) |
10282 | tg3_setup_phy(tp, 1); | |
10283 | ||
f47c11ee | 10284 | tg3_full_unlock(tp); |
6aa20a22 | 10285 | |
1da177e4 LT |
10286 | return 0; |
10287 | } | |
6aa20a22 | 10288 | |
1da177e4 LT |
10289 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
10290 | { | |
10291 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10292 | |
1da177e4 LT |
10293 | strcpy(info->driver, DRV_MODULE_NAME); |
10294 | strcpy(info->version, DRV_MODULE_VERSION); | |
c4e6575c | 10295 | strcpy(info->fw_version, tp->fw_ver); |
1da177e4 LT |
10296 | strcpy(info->bus_info, pci_name(tp->pdev)); |
10297 | } | |
6aa20a22 | 10298 | |
1da177e4 LT |
10299 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
10300 | { | |
10301 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10302 | |
63c3a66f | 10303 | if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) |
a85feb8c GZ |
10304 | wol->supported = WAKE_MAGIC; |
10305 | else | |
10306 | wol->supported = 0; | |
1da177e4 | 10307 | wol->wolopts = 0; |
63c3a66f | 10308 | if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) |
1da177e4 LT |
10309 | wol->wolopts = WAKE_MAGIC; |
10310 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
10311 | } | |
6aa20a22 | 10312 | |
1da177e4 LT |
10313 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
10314 | { | |
10315 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 10316 | struct device *dp = &tp->pdev->dev; |
6aa20a22 | 10317 | |
1da177e4 LT |
10318 | if (wol->wolopts & ~WAKE_MAGIC) |
10319 | return -EINVAL; | |
10320 | if ((wol->wolopts & WAKE_MAGIC) && | |
63c3a66f | 10321 | !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) |
1da177e4 | 10322 | return -EINVAL; |
6aa20a22 | 10323 | |
f2dc0d18 RW |
10324 | device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); |
10325 | ||
f47c11ee | 10326 | spin_lock_bh(&tp->lock); |
f2dc0d18 | 10327 | if (device_may_wakeup(dp)) |
63c3a66f | 10328 | tg3_flag_set(tp, WOL_ENABLE); |
f2dc0d18 | 10329 | else |
63c3a66f | 10330 | tg3_flag_clear(tp, WOL_ENABLE); |
f47c11ee | 10331 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 10332 | |
1da177e4 LT |
10333 | return 0; |
10334 | } | |
6aa20a22 | 10335 | |
1da177e4 LT |
10336 | static u32 tg3_get_msglevel(struct net_device *dev) |
10337 | { | |
10338 | struct tg3 *tp = netdev_priv(dev); | |
10339 | return tp->msg_enable; | |
10340 | } | |
6aa20a22 | 10341 | |
1da177e4 LT |
10342 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
10343 | { | |
10344 | struct tg3 *tp = netdev_priv(dev); | |
10345 | tp->msg_enable = value; | |
10346 | } | |
6aa20a22 | 10347 | |
1da177e4 LT |
10348 | static int tg3_nway_reset(struct net_device *dev) |
10349 | { | |
10350 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 10351 | int r; |
6aa20a22 | 10352 | |
1da177e4 LT |
10353 | if (!netif_running(dev)) |
10354 | return -EAGAIN; | |
10355 | ||
f07e9af3 | 10356 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
c94e3941 MC |
10357 | return -EINVAL; |
10358 | ||
63c3a66f | 10359 | if (tg3_flag(tp, USE_PHYLIB)) { |
f07e9af3 | 10360 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10361 | return -EAGAIN; |
3f0e3ad7 | 10362 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
10363 | } else { |
10364 | u32 bmcr; | |
10365 | ||
10366 | spin_lock_bh(&tp->lock); | |
10367 | r = -EINVAL; | |
10368 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
10369 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
10370 | ((bmcr & BMCR_ANENABLE) || | |
f07e9af3 | 10371 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { |
b02fd9e3 MC |
10372 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | |
10373 | BMCR_ANENABLE); | |
10374 | r = 0; | |
10375 | } | |
10376 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 10377 | } |
6aa20a22 | 10378 | |
1da177e4 LT |
10379 | return r; |
10380 | } | |
6aa20a22 | 10381 | |
1da177e4 LT |
10382 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10383 | { | |
10384 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10385 | |
2c49a44d | 10386 | ering->rx_max_pending = tp->rx_std_ring_mask; |
1da177e4 | 10387 | ering->rx_mini_max_pending = 0; |
63c3a66f | 10388 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
2c49a44d | 10389 | ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; |
4f81c32b MC |
10390 | else |
10391 | ering->rx_jumbo_max_pending = 0; | |
10392 | ||
10393 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
1da177e4 LT |
10394 | |
10395 | ering->rx_pending = tp->rx_pending; | |
10396 | ering->rx_mini_pending = 0; | |
63c3a66f | 10397 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
4f81c32b MC |
10398 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; |
10399 | else | |
10400 | ering->rx_jumbo_pending = 0; | |
10401 | ||
f3f3f27e | 10402 | ering->tx_pending = tp->napi[0].tx_pending; |
1da177e4 | 10403 | } |
6aa20a22 | 10404 | |
1da177e4 LT |
10405 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10406 | { | |
10407 | struct tg3 *tp = netdev_priv(dev); | |
646c9edd | 10408 | int i, irq_sync = 0, err = 0; |
6aa20a22 | 10409 | |
2c49a44d MC |
10410 | if ((ering->rx_pending > tp->rx_std_ring_mask) || |
10411 | (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || | |
bc3a9254 MC |
10412 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || |
10413 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
63c3a66f | 10414 | (tg3_flag(tp, TSO_BUG) && |
bc3a9254 | 10415 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) |
1da177e4 | 10416 | return -EINVAL; |
6aa20a22 | 10417 | |
bbe832c0 | 10418 | if (netif_running(dev)) { |
b02fd9e3 | 10419 | tg3_phy_stop(tp); |
1da177e4 | 10420 | tg3_netif_stop(tp); |
bbe832c0 MC |
10421 | irq_sync = 1; |
10422 | } | |
1da177e4 | 10423 | |
bbe832c0 | 10424 | tg3_full_lock(tp, irq_sync); |
6aa20a22 | 10425 | |
1da177e4 LT |
10426 | tp->rx_pending = ering->rx_pending; |
10427 | ||
63c3a66f | 10428 | if (tg3_flag(tp, MAX_RXPEND_64) && |
1da177e4 LT |
10429 | tp->rx_pending > 63) |
10430 | tp->rx_pending = 63; | |
10431 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
646c9edd | 10432 | |
6fd45cb8 | 10433 | for (i = 0; i < tp->irq_max; i++) |
646c9edd | 10434 | tp->napi[i].tx_pending = ering->tx_pending; |
1da177e4 LT |
10435 | |
10436 | if (netif_running(dev)) { | |
944d980e | 10437 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
b9ec6c1b MC |
10438 | err = tg3_restart_hw(tp, 1); |
10439 | if (!err) | |
10440 | tg3_netif_start(tp); | |
1da177e4 LT |
10441 | } |
10442 | ||
f47c11ee | 10443 | tg3_full_unlock(tp); |
6aa20a22 | 10444 | |
b02fd9e3 MC |
10445 | if (irq_sync && !err) |
10446 | tg3_phy_start(tp); | |
10447 | ||
b9ec6c1b | 10448 | return err; |
1da177e4 | 10449 | } |
6aa20a22 | 10450 | |
1da177e4 LT |
10451 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10452 | { | |
10453 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10454 | |
63c3a66f | 10455 | epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); |
8d018621 | 10456 | |
e18ce346 | 10457 | if (tp->link_config.active_flowctrl & FLOW_CTRL_RX) |
8d018621 MC |
10458 | epause->rx_pause = 1; |
10459 | else | |
10460 | epause->rx_pause = 0; | |
10461 | ||
e18ce346 | 10462 | if (tp->link_config.active_flowctrl & FLOW_CTRL_TX) |
8d018621 MC |
10463 | epause->tx_pause = 1; |
10464 | else | |
10465 | epause->tx_pause = 0; | |
1da177e4 | 10466 | } |
6aa20a22 | 10467 | |
1da177e4 LT |
10468 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10469 | { | |
10470 | struct tg3 *tp = netdev_priv(dev); | |
b02fd9e3 | 10471 | int err = 0; |
6aa20a22 | 10472 | |
63c3a66f | 10473 | if (tg3_flag(tp, USE_PHYLIB)) { |
2712168f MC |
10474 | u32 newadv; |
10475 | struct phy_device *phydev; | |
1da177e4 | 10476 | |
2712168f | 10477 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
f47c11ee | 10478 | |
2712168f MC |
10479 | if (!(phydev->supported & SUPPORTED_Pause) || |
10480 | (!(phydev->supported & SUPPORTED_Asym_Pause) && | |
2259dca3 | 10481 | (epause->rx_pause != epause->tx_pause))) |
2712168f | 10482 | return -EINVAL; |
1da177e4 | 10483 | |
2712168f MC |
10484 | tp->link_config.flowctrl = 0; |
10485 | if (epause->rx_pause) { | |
10486 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
10487 | ||
10488 | if (epause->tx_pause) { | |
10489 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10490 | newadv = ADVERTISED_Pause; | |
b02fd9e3 | 10491 | } else |
2712168f MC |
10492 | newadv = ADVERTISED_Pause | |
10493 | ADVERTISED_Asym_Pause; | |
10494 | } else if (epause->tx_pause) { | |
10495 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10496 | newadv = ADVERTISED_Asym_Pause; | |
10497 | } else | |
10498 | newadv = 0; | |
10499 | ||
10500 | if (epause->autoneg) | |
63c3a66f | 10501 | tg3_flag_set(tp, PAUSE_AUTONEG); |
2712168f | 10502 | else |
63c3a66f | 10503 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
2712168f | 10504 | |
f07e9af3 | 10505 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
2712168f MC |
10506 | u32 oldadv = phydev->advertising & |
10507 | (ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
10508 | if (oldadv != newadv) { | |
10509 | phydev->advertising &= | |
10510 | ~(ADVERTISED_Pause | | |
10511 | ADVERTISED_Asym_Pause); | |
10512 | phydev->advertising |= newadv; | |
10513 | if (phydev->autoneg) { | |
10514 | /* | |
10515 | * Always renegotiate the link to | |
10516 | * inform our link partner of our | |
10517 | * flow control settings, even if the | |
10518 | * flow control is forced. Let | |
10519 | * tg3_adjust_link() do the final | |
10520 | * flow control setup. | |
10521 | */ | |
10522 | return phy_start_aneg(phydev); | |
b02fd9e3 | 10523 | } |
b02fd9e3 | 10524 | } |
b02fd9e3 | 10525 | |
2712168f | 10526 | if (!epause->autoneg) |
b02fd9e3 | 10527 | tg3_setup_flow_control(tp, 0, 0); |
2712168f MC |
10528 | } else { |
10529 | tp->link_config.orig_advertising &= | |
10530 | ~(ADVERTISED_Pause | | |
10531 | ADVERTISED_Asym_Pause); | |
10532 | tp->link_config.orig_advertising |= newadv; | |
b02fd9e3 MC |
10533 | } |
10534 | } else { | |
10535 | int irq_sync = 0; | |
10536 | ||
10537 | if (netif_running(dev)) { | |
10538 | tg3_netif_stop(tp); | |
10539 | irq_sync = 1; | |
10540 | } | |
10541 | ||
10542 | tg3_full_lock(tp, irq_sync); | |
10543 | ||
10544 | if (epause->autoneg) | |
63c3a66f | 10545 | tg3_flag_set(tp, PAUSE_AUTONEG); |
b02fd9e3 | 10546 | else |
63c3a66f | 10547 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
b02fd9e3 | 10548 | if (epause->rx_pause) |
e18ce346 | 10549 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 10550 | else |
e18ce346 | 10551 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
b02fd9e3 | 10552 | if (epause->tx_pause) |
e18ce346 | 10553 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 10554 | else |
e18ce346 | 10555 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
10556 | |
10557 | if (netif_running(dev)) { | |
10558 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
10559 | err = tg3_restart_hw(tp, 1); | |
10560 | if (!err) | |
10561 | tg3_netif_start(tp); | |
10562 | } | |
10563 | ||
10564 | tg3_full_unlock(tp); | |
10565 | } | |
6aa20a22 | 10566 | |
b9ec6c1b | 10567 | return err; |
1da177e4 | 10568 | } |
6aa20a22 | 10569 | |
de6f31eb | 10570 | static int tg3_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 10571 | { |
b9f2c044 JG |
10572 | switch (sset) { |
10573 | case ETH_SS_TEST: | |
10574 | return TG3_NUM_TEST; | |
10575 | case ETH_SS_STATS: | |
10576 | return TG3_NUM_STATS; | |
10577 | default: | |
10578 | return -EOPNOTSUPP; | |
10579 | } | |
4cafd3f5 MC |
10580 | } |
10581 | ||
de6f31eb | 10582 | static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
1da177e4 LT |
10583 | { |
10584 | switch (stringset) { | |
10585 | case ETH_SS_STATS: | |
10586 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
10587 | break; | |
4cafd3f5 MC |
10588 | case ETH_SS_TEST: |
10589 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
10590 | break; | |
1da177e4 LT |
10591 | default: |
10592 | WARN_ON(1); /* we need a WARN() */ | |
10593 | break; | |
10594 | } | |
10595 | } | |
10596 | ||
81b8709c | 10597 | static int tg3_set_phys_id(struct net_device *dev, |
10598 | enum ethtool_phys_id_state state) | |
4009a93d MC |
10599 | { |
10600 | struct tg3 *tp = netdev_priv(dev); | |
4009a93d MC |
10601 | |
10602 | if (!netif_running(tp->dev)) | |
10603 | return -EAGAIN; | |
10604 | ||
81b8709c | 10605 | switch (state) { |
10606 | case ETHTOOL_ID_ACTIVE: | |
fce55922 | 10607 | return 1; /* cycle on/off once per second */ |
4009a93d | 10608 | |
81b8709c | 10609 | case ETHTOOL_ID_ON: |
10610 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10611 | LED_CTRL_1000MBPS_ON | | |
10612 | LED_CTRL_100MBPS_ON | | |
10613 | LED_CTRL_10MBPS_ON | | |
10614 | LED_CTRL_TRAFFIC_OVERRIDE | | |
10615 | LED_CTRL_TRAFFIC_BLINK | | |
10616 | LED_CTRL_TRAFFIC_LED); | |
10617 | break; | |
6aa20a22 | 10618 | |
81b8709c | 10619 | case ETHTOOL_ID_OFF: |
10620 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10621 | LED_CTRL_TRAFFIC_OVERRIDE); | |
10622 | break; | |
4009a93d | 10623 | |
81b8709c | 10624 | case ETHTOOL_ID_INACTIVE: |
10625 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
10626 | break; | |
4009a93d | 10627 | } |
81b8709c | 10628 | |
4009a93d MC |
10629 | return 0; |
10630 | } | |
10631 | ||
de6f31eb | 10632 | static void tg3_get_ethtool_stats(struct net_device *dev, |
1da177e4 LT |
10633 | struct ethtool_stats *estats, u64 *tmp_stats) |
10634 | { | |
10635 | struct tg3 *tp = netdev_priv(dev); | |
10636 | memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats)); | |
10637 | } | |
10638 | ||
535a490e | 10639 | static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen) |
c3e94500 MC |
10640 | { |
10641 | int i; | |
10642 | __be32 *buf; | |
10643 | u32 offset = 0, len = 0; | |
10644 | u32 magic, val; | |
10645 | ||
63c3a66f | 10646 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) |
c3e94500 MC |
10647 | return NULL; |
10648 | ||
10649 | if (magic == TG3_EEPROM_MAGIC) { | |
10650 | for (offset = TG3_NVM_DIR_START; | |
10651 | offset < TG3_NVM_DIR_END; | |
10652 | offset += TG3_NVM_DIRENT_SIZE) { | |
10653 | if (tg3_nvram_read(tp, offset, &val)) | |
10654 | return NULL; | |
10655 | ||
10656 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == | |
10657 | TG3_NVM_DIRTYPE_EXTVPD) | |
10658 | break; | |
10659 | } | |
10660 | ||
10661 | if (offset != TG3_NVM_DIR_END) { | |
10662 | len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4; | |
10663 | if (tg3_nvram_read(tp, offset + 4, &offset)) | |
10664 | return NULL; | |
10665 | ||
10666 | offset = tg3_nvram_logical_addr(tp, offset); | |
10667 | } | |
10668 | } | |
10669 | ||
10670 | if (!offset || !len) { | |
10671 | offset = TG3_NVM_VPD_OFF; | |
10672 | len = TG3_NVM_VPD_LEN; | |
10673 | } | |
10674 | ||
10675 | buf = kmalloc(len, GFP_KERNEL); | |
10676 | if (buf == NULL) | |
10677 | return NULL; | |
10678 | ||
10679 | if (magic == TG3_EEPROM_MAGIC) { | |
10680 | for (i = 0; i < len; i += 4) { | |
10681 | /* The data is in little-endian format in NVRAM. | |
10682 | * Use the big-endian read routines to preserve | |
10683 | * the byte order as it exists in NVRAM. | |
10684 | */ | |
10685 | if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) | |
10686 | goto error; | |
10687 | } | |
10688 | } else { | |
10689 | u8 *ptr; | |
10690 | ssize_t cnt; | |
10691 | unsigned int pos = 0; | |
10692 | ||
10693 | ptr = (u8 *)&buf[0]; | |
10694 | for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) { | |
10695 | cnt = pci_read_vpd(tp->pdev, pos, | |
10696 | len - pos, ptr); | |
10697 | if (cnt == -ETIMEDOUT || cnt == -EINTR) | |
10698 | cnt = 0; | |
10699 | else if (cnt < 0) | |
10700 | goto error; | |
10701 | } | |
10702 | if (pos != len) | |
10703 | goto error; | |
10704 | } | |
10705 | ||
535a490e MC |
10706 | *vpdlen = len; |
10707 | ||
c3e94500 MC |
10708 | return buf; |
10709 | ||
10710 | error: | |
10711 | kfree(buf); | |
10712 | return NULL; | |
10713 | } | |
10714 | ||
566f86ad | 10715 | #define NVRAM_TEST_SIZE 0x100 |
a5767dec MC |
10716 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
10717 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
10718 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
727a6d9f MC |
10719 | #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20 |
10720 | #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24 | |
bda18faf | 10721 | #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50 |
b16250e3 MC |
10722 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
10723 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
566f86ad MC |
10724 | |
10725 | static int tg3_test_nvram(struct tg3 *tp) | |
10726 | { | |
535a490e | 10727 | u32 csum, magic, len; |
a9dc529d | 10728 | __be32 *buf; |
ab0049b4 | 10729 | int i, j, k, err = 0, size; |
566f86ad | 10730 | |
63c3a66f | 10731 | if (tg3_flag(tp, NO_NVRAM)) |
df259d8c MC |
10732 | return 0; |
10733 | ||
e4f34110 | 10734 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1b27777a MC |
10735 | return -EIO; |
10736 | ||
1b27777a MC |
10737 | if (magic == TG3_EEPROM_MAGIC) |
10738 | size = NVRAM_TEST_SIZE; | |
b16250e3 | 10739 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
a5767dec MC |
10740 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
10741 | TG3_EEPROM_SB_FORMAT_1) { | |
10742 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
10743 | case TG3_EEPROM_SB_REVISION_0: | |
10744 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
10745 | break; | |
10746 | case TG3_EEPROM_SB_REVISION_2: | |
10747 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
10748 | break; | |
10749 | case TG3_EEPROM_SB_REVISION_3: | |
10750 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
10751 | break; | |
727a6d9f MC |
10752 | case TG3_EEPROM_SB_REVISION_4: |
10753 | size = NVRAM_SELFBOOT_FORMAT1_4_SIZE; | |
10754 | break; | |
10755 | case TG3_EEPROM_SB_REVISION_5: | |
10756 | size = NVRAM_SELFBOOT_FORMAT1_5_SIZE; | |
10757 | break; | |
10758 | case TG3_EEPROM_SB_REVISION_6: | |
10759 | size = NVRAM_SELFBOOT_FORMAT1_6_SIZE; | |
10760 | break; | |
a5767dec | 10761 | default: |
727a6d9f | 10762 | return -EIO; |
a5767dec MC |
10763 | } |
10764 | } else | |
1b27777a | 10765 | return 0; |
b16250e3 MC |
10766 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
10767 | size = NVRAM_SELFBOOT_HW_SIZE; | |
10768 | else | |
1b27777a MC |
10769 | return -EIO; |
10770 | ||
10771 | buf = kmalloc(size, GFP_KERNEL); | |
566f86ad MC |
10772 | if (buf == NULL) |
10773 | return -ENOMEM; | |
10774 | ||
1b27777a MC |
10775 | err = -EIO; |
10776 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
a9dc529d MC |
10777 | err = tg3_nvram_read_be32(tp, i, &buf[j]); |
10778 | if (err) | |
566f86ad | 10779 | break; |
566f86ad | 10780 | } |
1b27777a | 10781 | if (i < size) |
566f86ad MC |
10782 | goto out; |
10783 | ||
1b27777a | 10784 | /* Selfboot format */ |
a9dc529d | 10785 | magic = be32_to_cpu(buf[0]); |
b9fc7dc5 | 10786 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == |
b16250e3 | 10787 | TG3_EEPROM_MAGIC_FW) { |
1b27777a MC |
10788 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
10789 | ||
b9fc7dc5 | 10790 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == |
a5767dec MC |
10791 | TG3_EEPROM_SB_REVISION_2) { |
10792 | /* For rev 2, the csum doesn't include the MBA. */ | |
10793 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
10794 | csum8 += buf8[i]; | |
10795 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
10796 | csum8 += buf8[i]; | |
10797 | } else { | |
10798 | for (i = 0; i < size; i++) | |
10799 | csum8 += buf8[i]; | |
10800 | } | |
1b27777a | 10801 | |
ad96b485 AB |
10802 | if (csum8 == 0) { |
10803 | err = 0; | |
10804 | goto out; | |
10805 | } | |
10806 | ||
10807 | err = -EIO; | |
10808 | goto out; | |
1b27777a | 10809 | } |
566f86ad | 10810 | |
b9fc7dc5 | 10811 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == |
b16250e3 MC |
10812 | TG3_EEPROM_MAGIC_HW) { |
10813 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
a9dc529d | 10814 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; |
b16250e3 | 10815 | u8 *buf8 = (u8 *) buf; |
b16250e3 MC |
10816 | |
10817 | /* Separate the parity bits and the data bytes. */ | |
10818 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
10819 | if ((i == 0) || (i == 8)) { | |
10820 | int l; | |
10821 | u8 msk; | |
10822 | ||
10823 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
10824 | parity[k++] = buf8[i] & msk; | |
10825 | i++; | |
859a5887 | 10826 | } else if (i == 16) { |
b16250e3 MC |
10827 | int l; |
10828 | u8 msk; | |
10829 | ||
10830 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
10831 | parity[k++] = buf8[i] & msk; | |
10832 | i++; | |
10833 | ||
10834 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
10835 | parity[k++] = buf8[i] & msk; | |
10836 | i++; | |
10837 | } | |
10838 | data[j++] = buf8[i]; | |
10839 | } | |
10840 | ||
10841 | err = -EIO; | |
10842 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
10843 | u8 hw8 = hweight8(data[i]); | |
10844 | ||
10845 | if ((hw8 & 0x1) && parity[i]) | |
10846 | goto out; | |
10847 | else if (!(hw8 & 0x1) && !parity[i]) | |
10848 | goto out; | |
10849 | } | |
10850 | err = 0; | |
10851 | goto out; | |
10852 | } | |
10853 | ||
01c3a392 MC |
10854 | err = -EIO; |
10855 | ||
566f86ad MC |
10856 | /* Bootstrap checksum at offset 0x10 */ |
10857 | csum = calc_crc((unsigned char *) buf, 0x10); | |
01c3a392 | 10858 | if (csum != le32_to_cpu(buf[0x10/4])) |
566f86ad MC |
10859 | goto out; |
10860 | ||
10861 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
10862 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
01c3a392 | 10863 | if (csum != le32_to_cpu(buf[0xfc/4])) |
a9dc529d | 10864 | goto out; |
566f86ad | 10865 | |
c3e94500 MC |
10866 | kfree(buf); |
10867 | ||
535a490e | 10868 | buf = tg3_vpd_readblock(tp, &len); |
c3e94500 MC |
10869 | if (!buf) |
10870 | return -ENOMEM; | |
d4894f3e | 10871 | |
535a490e | 10872 | i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA); |
d4894f3e MC |
10873 | if (i > 0) { |
10874 | j = pci_vpd_lrdt_size(&((u8 *)buf)[i]); | |
10875 | if (j < 0) | |
10876 | goto out; | |
10877 | ||
535a490e | 10878 | if (i + PCI_VPD_LRDT_TAG_SIZE + j > len) |
d4894f3e MC |
10879 | goto out; |
10880 | ||
10881 | i += PCI_VPD_LRDT_TAG_SIZE; | |
10882 | j = pci_vpd_find_info_keyword((u8 *)buf, i, j, | |
10883 | PCI_VPD_RO_KEYWORD_CHKSUM); | |
10884 | if (j > 0) { | |
10885 | u8 csum8 = 0; | |
10886 | ||
10887 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
10888 | ||
10889 | for (i = 0; i <= j; i++) | |
10890 | csum8 += ((u8 *)buf)[i]; | |
10891 | ||
10892 | if (csum8) | |
10893 | goto out; | |
10894 | } | |
10895 | } | |
10896 | ||
566f86ad MC |
10897 | err = 0; |
10898 | ||
10899 | out: | |
10900 | kfree(buf); | |
10901 | return err; | |
10902 | } | |
10903 | ||
ca43007a MC |
10904 | #define TG3_SERDES_TIMEOUT_SEC 2 |
10905 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
10906 | ||
10907 | static int tg3_test_link(struct tg3 *tp) | |
10908 | { | |
10909 | int i, max; | |
10910 | ||
10911 | if (!netif_running(tp->dev)) | |
10912 | return -ENODEV; | |
10913 | ||
f07e9af3 | 10914 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
ca43007a MC |
10915 | max = TG3_SERDES_TIMEOUT_SEC; |
10916 | else | |
10917 | max = TG3_COPPER_TIMEOUT_SEC; | |
10918 | ||
10919 | for (i = 0; i < max; i++) { | |
10920 | if (netif_carrier_ok(tp->dev)) | |
10921 | return 0; | |
10922 | ||
10923 | if (msleep_interruptible(1000)) | |
10924 | break; | |
10925 | } | |
10926 | ||
10927 | return -EIO; | |
10928 | } | |
10929 | ||
a71116d1 | 10930 | /* Only test the commonly used registers */ |
30ca3e37 | 10931 | static int tg3_test_registers(struct tg3 *tp) |
a71116d1 | 10932 | { |
b16250e3 | 10933 | int i, is_5705, is_5750; |
a71116d1 MC |
10934 | u32 offset, read_mask, write_mask, val, save_val, read_val; |
10935 | static struct { | |
10936 | u16 offset; | |
10937 | u16 flags; | |
10938 | #define TG3_FL_5705 0x1 | |
10939 | #define TG3_FL_NOT_5705 0x2 | |
10940 | #define TG3_FL_NOT_5788 0x4 | |
b16250e3 | 10941 | #define TG3_FL_NOT_5750 0x8 |
a71116d1 MC |
10942 | u32 read_mask; |
10943 | u32 write_mask; | |
10944 | } reg_tbl[] = { | |
10945 | /* MAC Control Registers */ | |
10946 | { MAC_MODE, TG3_FL_NOT_5705, | |
10947 | 0x00000000, 0x00ef6f8c }, | |
10948 | { MAC_MODE, TG3_FL_5705, | |
10949 | 0x00000000, 0x01ef6b8c }, | |
10950 | { MAC_STATUS, TG3_FL_NOT_5705, | |
10951 | 0x03800107, 0x00000000 }, | |
10952 | { MAC_STATUS, TG3_FL_5705, | |
10953 | 0x03800100, 0x00000000 }, | |
10954 | { MAC_ADDR_0_HIGH, 0x0000, | |
10955 | 0x00000000, 0x0000ffff }, | |
10956 | { MAC_ADDR_0_LOW, 0x0000, | |
c6cdf436 | 10957 | 0x00000000, 0xffffffff }, |
a71116d1 MC |
10958 | { MAC_RX_MTU_SIZE, 0x0000, |
10959 | 0x00000000, 0x0000ffff }, | |
10960 | { MAC_TX_MODE, 0x0000, | |
10961 | 0x00000000, 0x00000070 }, | |
10962 | { MAC_TX_LENGTHS, 0x0000, | |
10963 | 0x00000000, 0x00003fff }, | |
10964 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
10965 | 0x00000000, 0x000007fc }, | |
10966 | { MAC_RX_MODE, TG3_FL_5705, | |
10967 | 0x00000000, 0x000007dc }, | |
10968 | { MAC_HASH_REG_0, 0x0000, | |
10969 | 0x00000000, 0xffffffff }, | |
10970 | { MAC_HASH_REG_1, 0x0000, | |
10971 | 0x00000000, 0xffffffff }, | |
10972 | { MAC_HASH_REG_2, 0x0000, | |
10973 | 0x00000000, 0xffffffff }, | |
10974 | { MAC_HASH_REG_3, 0x0000, | |
10975 | 0x00000000, 0xffffffff }, | |
10976 | ||
10977 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
10978 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
10979 | 0x00000000, 0xffffffff }, | |
10980 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
10981 | 0x00000000, 0xffffffff }, | |
10982 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
10983 | 0x00000000, 0x00000003 }, | |
10984 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
10985 | 0x00000000, 0xffffffff }, | |
10986 | { RCVDBDI_STD_BD+0, 0x0000, | |
10987 | 0x00000000, 0xffffffff }, | |
10988 | { RCVDBDI_STD_BD+4, 0x0000, | |
10989 | 0x00000000, 0xffffffff }, | |
10990 | { RCVDBDI_STD_BD+8, 0x0000, | |
10991 | 0x00000000, 0xffff0002 }, | |
10992 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
10993 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10994 | |
a71116d1 MC |
10995 | /* Receive BD Initiator Control Registers. */ |
10996 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
10997 | 0x00000000, 0xffffffff }, | |
10998 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
10999 | 0x00000000, 0x000003ff }, | |
11000 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
11001 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 11002 | |
a71116d1 MC |
11003 | /* Host Coalescing Control Registers. */ |
11004 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
11005 | 0x00000000, 0x00000004 }, | |
11006 | { HOSTCC_MODE, TG3_FL_5705, | |
11007 | 0x00000000, 0x000000f6 }, | |
11008 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
11009 | 0x00000000, 0xffffffff }, | |
11010 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
11011 | 0x00000000, 0x000003ff }, | |
11012 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
11013 | 0x00000000, 0xffffffff }, | |
11014 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
11015 | 0x00000000, 0x000003ff }, | |
11016 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
11017 | 0x00000000, 0xffffffff }, | |
11018 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11019 | 0x00000000, 0x000000ff }, | |
11020 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
11021 | 0x00000000, 0xffffffff }, | |
11022 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11023 | 0x00000000, 0x000000ff }, | |
11024 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
11025 | 0x00000000, 0xffffffff }, | |
11026 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
11027 | 0x00000000, 0xffffffff }, | |
11028 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
11029 | 0x00000000, 0xffffffff }, | |
11030 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11031 | 0x00000000, 0x000000ff }, | |
11032 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
11033 | 0x00000000, 0xffffffff }, | |
11034 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11035 | 0x00000000, 0x000000ff }, | |
11036 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
11037 | 0x00000000, 0xffffffff }, | |
11038 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
11039 | 0x00000000, 0xffffffff }, | |
11040 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
11041 | 0x00000000, 0xffffffff }, | |
11042 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
11043 | 0x00000000, 0xffffffff }, | |
11044 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
11045 | 0x00000000, 0xffffffff }, | |
11046 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
11047 | 0xffffffff, 0x00000000 }, | |
11048 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
11049 | 0xffffffff, 0x00000000 }, | |
11050 | ||
11051 | /* Buffer Manager Control Registers. */ | |
b16250e3 | 11052 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, |
a71116d1 | 11053 | 0x00000000, 0x007fff80 }, |
b16250e3 | 11054 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, |
a71116d1 MC |
11055 | 0x00000000, 0x007fffff }, |
11056 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
11057 | 0x00000000, 0x0000003f }, | |
11058 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
11059 | 0x00000000, 0x000001ff }, | |
11060 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
11061 | 0x00000000, 0x000001ff }, | |
11062 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
11063 | 0xffffffff, 0x00000000 }, | |
11064 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
11065 | 0xffffffff, 0x00000000 }, | |
6aa20a22 | 11066 | |
a71116d1 MC |
11067 | /* Mailbox Registers */ |
11068 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
11069 | 0x00000000, 0x000001ff }, | |
11070 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
11071 | 0x00000000, 0x000001ff }, | |
11072 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
11073 | 0x00000000, 0x000007ff }, | |
11074 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
11075 | 0x00000000, 0x000001ff }, | |
11076 | ||
11077 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
11078 | }; | |
11079 | ||
b16250e3 | 11080 | is_5705 = is_5750 = 0; |
63c3a66f | 11081 | if (tg3_flag(tp, 5705_PLUS)) { |
a71116d1 | 11082 | is_5705 = 1; |
63c3a66f | 11083 | if (tg3_flag(tp, 5750_PLUS)) |
b16250e3 MC |
11084 | is_5750 = 1; |
11085 | } | |
a71116d1 MC |
11086 | |
11087 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
11088 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
11089 | continue; | |
11090 | ||
11091 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
11092 | continue; | |
11093 | ||
63c3a66f | 11094 | if (tg3_flag(tp, IS_5788) && |
a71116d1 MC |
11095 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) |
11096 | continue; | |
11097 | ||
b16250e3 MC |
11098 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) |
11099 | continue; | |
11100 | ||
a71116d1 MC |
11101 | offset = (u32) reg_tbl[i].offset; |
11102 | read_mask = reg_tbl[i].read_mask; | |
11103 | write_mask = reg_tbl[i].write_mask; | |
11104 | ||
11105 | /* Save the original register content */ | |
11106 | save_val = tr32(offset); | |
11107 | ||
11108 | /* Determine the read-only value. */ | |
11109 | read_val = save_val & read_mask; | |
11110 | ||
11111 | /* Write zero to the register, then make sure the read-only bits | |
11112 | * are not changed and the read/write bits are all zeros. | |
11113 | */ | |
11114 | tw32(offset, 0); | |
11115 | ||
11116 | val = tr32(offset); | |
11117 | ||
11118 | /* Test the read-only and read/write bits. */ | |
11119 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
11120 | goto out; | |
11121 | ||
11122 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
11123 | * make sure the read-only bits are not changed and the | |
11124 | * read/write bits are all ones. | |
11125 | */ | |
11126 | tw32(offset, read_mask | write_mask); | |
11127 | ||
11128 | val = tr32(offset); | |
11129 | ||
11130 | /* Test the read-only bits. */ | |
11131 | if ((val & read_mask) != read_val) | |
11132 | goto out; | |
11133 | ||
11134 | /* Test the read/write bits. */ | |
11135 | if ((val & write_mask) != write_mask) | |
11136 | goto out; | |
11137 | ||
11138 | tw32(offset, save_val); | |
11139 | } | |
11140 | ||
11141 | return 0; | |
11142 | ||
11143 | out: | |
9f88f29f | 11144 | if (netif_msg_hw(tp)) |
2445e461 MC |
11145 | netdev_err(tp->dev, |
11146 | "Register test failed at offset %x\n", offset); | |
a71116d1 MC |
11147 | tw32(offset, save_val); |
11148 | return -EIO; | |
11149 | } | |
11150 | ||
7942e1db MC |
11151 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) |
11152 | { | |
f71e1309 | 11153 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; |
7942e1db MC |
11154 | int i; |
11155 | u32 j; | |
11156 | ||
e9edda69 | 11157 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { |
7942e1db MC |
11158 | for (j = 0; j < len; j += 4) { |
11159 | u32 val; | |
11160 | ||
11161 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
11162 | tg3_read_mem(tp, offset + j, &val); | |
11163 | if (val != test_pattern[i]) | |
11164 | return -EIO; | |
11165 | } | |
11166 | } | |
11167 | return 0; | |
11168 | } | |
11169 | ||
11170 | static int tg3_test_memory(struct tg3 *tp) | |
11171 | { | |
11172 | static struct mem_entry { | |
11173 | u32 offset; | |
11174 | u32 len; | |
11175 | } mem_tbl_570x[] = { | |
38690194 | 11176 | { 0x00000000, 0x00b50}, |
7942e1db MC |
11177 | { 0x00002000, 0x1c000}, |
11178 | { 0xffffffff, 0x00000} | |
11179 | }, mem_tbl_5705[] = { | |
11180 | { 0x00000100, 0x0000c}, | |
11181 | { 0x00000200, 0x00008}, | |
7942e1db MC |
11182 | { 0x00004000, 0x00800}, |
11183 | { 0x00006000, 0x01000}, | |
11184 | { 0x00008000, 0x02000}, | |
11185 | { 0x00010000, 0x0e000}, | |
11186 | { 0xffffffff, 0x00000} | |
79f4d13a MC |
11187 | }, mem_tbl_5755[] = { |
11188 | { 0x00000200, 0x00008}, | |
11189 | { 0x00004000, 0x00800}, | |
11190 | { 0x00006000, 0x00800}, | |
11191 | { 0x00008000, 0x02000}, | |
11192 | { 0x00010000, 0x0c000}, | |
11193 | { 0xffffffff, 0x00000} | |
b16250e3 MC |
11194 | }, mem_tbl_5906[] = { |
11195 | { 0x00000200, 0x00008}, | |
11196 | { 0x00004000, 0x00400}, | |
11197 | { 0x00006000, 0x00400}, | |
11198 | { 0x00008000, 0x01000}, | |
11199 | { 0x00010000, 0x01000}, | |
11200 | { 0xffffffff, 0x00000} | |
8b5a6c42 MC |
11201 | }, mem_tbl_5717[] = { |
11202 | { 0x00000200, 0x00008}, | |
11203 | { 0x00010000, 0x0a000}, | |
11204 | { 0x00020000, 0x13c00}, | |
11205 | { 0xffffffff, 0x00000} | |
11206 | }, mem_tbl_57765[] = { | |
11207 | { 0x00000200, 0x00008}, | |
11208 | { 0x00004000, 0x00800}, | |
11209 | { 0x00006000, 0x09800}, | |
11210 | { 0x00010000, 0x0a000}, | |
11211 | { 0xffffffff, 0x00000} | |
7942e1db MC |
11212 | }; |
11213 | struct mem_entry *mem_tbl; | |
11214 | int err = 0; | |
11215 | int i; | |
11216 | ||
63c3a66f | 11217 | if (tg3_flag(tp, 5717_PLUS)) |
8b5a6c42 MC |
11218 | mem_tbl = mem_tbl_5717; |
11219 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
11220 | mem_tbl = mem_tbl_57765; | |
63c3a66f | 11221 | else if (tg3_flag(tp, 5755_PLUS)) |
321d32a0 MC |
11222 | mem_tbl = mem_tbl_5755; |
11223 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
11224 | mem_tbl = mem_tbl_5906; | |
63c3a66f | 11225 | else if (tg3_flag(tp, 5705_PLUS)) |
321d32a0 MC |
11226 | mem_tbl = mem_tbl_5705; |
11227 | else | |
7942e1db MC |
11228 | mem_tbl = mem_tbl_570x; |
11229 | ||
11230 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
be98da6a MC |
11231 | err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); |
11232 | if (err) | |
7942e1db MC |
11233 | break; |
11234 | } | |
6aa20a22 | 11235 | |
7942e1db MC |
11236 | return err; |
11237 | } | |
11238 | ||
9f40dead MC |
11239 | #define TG3_MAC_LOOPBACK 0 |
11240 | #define TG3_PHY_LOOPBACK 1 | |
bb158d69 MC |
11241 | #define TG3_TSO_LOOPBACK 2 |
11242 | ||
11243 | #define TG3_TSO_MSS 500 | |
11244 | ||
11245 | #define TG3_TSO_IP_HDR_LEN 20 | |
11246 | #define TG3_TSO_TCP_HDR_LEN 20 | |
11247 | #define TG3_TSO_TCP_OPT_LEN 12 | |
11248 | ||
11249 | static const u8 tg3_tso_header[] = { | |
11250 | 0x08, 0x00, | |
11251 | 0x45, 0x00, 0x00, 0x00, | |
11252 | 0x00, 0x00, 0x40, 0x00, | |
11253 | 0x40, 0x06, 0x00, 0x00, | |
11254 | 0x0a, 0x00, 0x00, 0x01, | |
11255 | 0x0a, 0x00, 0x00, 0x02, | |
11256 | 0x0d, 0x00, 0xe0, 0x00, | |
11257 | 0x00, 0x00, 0x01, 0x00, | |
11258 | 0x00, 0x00, 0x02, 0x00, | |
11259 | 0x80, 0x10, 0x10, 0x00, | |
11260 | 0x14, 0x09, 0x00, 0x00, | |
11261 | 0x01, 0x01, 0x08, 0x0a, | |
11262 | 0x11, 0x11, 0x11, 0x11, | |
11263 | 0x11, 0x11, 0x11, 0x11, | |
11264 | }; | |
9f40dead | 11265 | |
4852a861 | 11266 | static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode) |
c76949a6 | 11267 | { |
9f40dead | 11268 | u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key; |
bb158d69 | 11269 | u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val; |
84b67b27 | 11270 | u32 budget; |
c76949a6 MC |
11271 | struct sk_buff *skb, *rx_skb; |
11272 | u8 *tx_data; | |
11273 | dma_addr_t map; | |
11274 | int num_pkts, tx_len, rx_len, i, err; | |
11275 | struct tg3_rx_buffer_desc *desc; | |
898a56f8 | 11276 | struct tg3_napi *tnapi, *rnapi; |
8fea32b9 | 11277 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
c76949a6 | 11278 | |
c8873405 MC |
11279 | tnapi = &tp->napi[0]; |
11280 | rnapi = &tp->napi[0]; | |
0c1d0e2b | 11281 | if (tp->irq_cnt > 1) { |
63c3a66f | 11282 | if (tg3_flag(tp, ENABLE_RSS)) |
1da85aa3 | 11283 | rnapi = &tp->napi[1]; |
63c3a66f | 11284 | if (tg3_flag(tp, ENABLE_TSS)) |
c8873405 | 11285 | tnapi = &tp->napi[1]; |
0c1d0e2b | 11286 | } |
fd2ce37f | 11287 | coal_now = tnapi->coal_now | rnapi->coal_now; |
898a56f8 | 11288 | |
6e01b20b | 11289 | if (loopback_mode != TG3_MAC_LOOPBACK) { |
f07e9af3 | 11290 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd | 11291 | tg3_phy_fet_toggle_apd(tp, false); |
5d64ad34 MC |
11292 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; |
11293 | } else | |
11294 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; | |
3f7045c1 | 11295 | |
9ef8ca99 MC |
11296 | tg3_phy_toggle_automdix(tp, 0); |
11297 | ||
3f7045c1 | 11298 | tg3_writephy(tp, MII_BMCR, val); |
c94e3941 | 11299 | udelay(40); |
5d64ad34 | 11300 | |
49692ca1 MC |
11301 | mac_mode = tp->mac_mode & |
11302 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
f07e9af3 | 11303 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
1061b7c5 MC |
11304 | tg3_writephy(tp, MII_TG3_FET_PTEST, |
11305 | MII_TG3_FET_PTEST_FRC_TX_LINK | | |
11306 | MII_TG3_FET_PTEST_FRC_TX_LOCK); | |
11307 | /* The write needs to be flushed for the AC131 */ | |
11308 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
11309 | tg3_readphy(tp, MII_TG3_FET_PTEST, &val); | |
5d64ad34 MC |
11310 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
11311 | } else | |
11312 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
b16250e3 | 11313 | |
c94e3941 | 11314 | /* reset to prevent losing 1st rx packet intermittently */ |
f07e9af3 | 11315 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
c94e3941 MC |
11316 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
11317 | udelay(10); | |
11318 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
11319 | } | |
e8f3f6ca | 11320 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
79eb6904 MC |
11321 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; |
11322 | if (masked_phy_id == TG3_PHY_ID_BCM5401) | |
e8f3f6ca | 11323 | mac_mode &= ~MAC_MODE_LINK_POLARITY; |
79eb6904 | 11324 | else if (masked_phy_id == TG3_PHY_ID_BCM5411) |
e8f3f6ca | 11325 | mac_mode |= MAC_MODE_LINK_POLARITY; |
ff18ff02 MC |
11326 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
11327 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
11328 | } | |
9f40dead | 11329 | tw32(MAC_MODE, mac_mode); |
49692ca1 MC |
11330 | |
11331 | /* Wait for link */ | |
11332 | for (i = 0; i < 100; i++) { | |
11333 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
11334 | break; | |
11335 | mdelay(1); | |
11336 | } | |
859a5887 | 11337 | } |
c76949a6 MC |
11338 | |
11339 | err = -EIO; | |
11340 | ||
4852a861 | 11341 | tx_len = pktsz; |
a20e9c62 | 11342 | skb = netdev_alloc_skb(tp->dev, tx_len); |
a50bb7b9 JJ |
11343 | if (!skb) |
11344 | return -ENOMEM; | |
11345 | ||
c76949a6 MC |
11346 | tx_data = skb_put(skb, tx_len); |
11347 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
11348 | memset(tx_data + 6, 0x0, 8); | |
11349 | ||
4852a861 | 11350 | tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN); |
c76949a6 | 11351 | |
bb158d69 MC |
11352 | if (loopback_mode == TG3_TSO_LOOPBACK) { |
11353 | struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN]; | |
11354 | ||
11355 | u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN + | |
11356 | TG3_TSO_TCP_OPT_LEN; | |
11357 | ||
11358 | memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header, | |
11359 | sizeof(tg3_tso_header)); | |
11360 | mss = TG3_TSO_MSS; | |
11361 | ||
11362 | val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); | |
11363 | num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS); | |
11364 | ||
11365 | /* Set the total length field in the IP header */ | |
11366 | iph->tot_len = htons((u16)(mss + hdr_len)); | |
11367 | ||
11368 | base_flags = (TXD_FLAG_CPU_PRE_DMA | | |
11369 | TXD_FLAG_CPU_POST_DMA); | |
11370 | ||
63c3a66f JP |
11371 | if (tg3_flag(tp, HW_TSO_1) || |
11372 | tg3_flag(tp, HW_TSO_2) || | |
11373 | tg3_flag(tp, HW_TSO_3)) { | |
bb158d69 MC |
11374 | struct tcphdr *th; |
11375 | val = ETH_HLEN + TG3_TSO_IP_HDR_LEN; | |
11376 | th = (struct tcphdr *)&tx_data[val]; | |
11377 | th->check = 0; | |
11378 | } else | |
11379 | base_flags |= TXD_FLAG_TCPUDP_CSUM; | |
11380 | ||
63c3a66f | 11381 | if (tg3_flag(tp, HW_TSO_3)) { |
bb158d69 MC |
11382 | mss |= (hdr_len & 0xc) << 12; |
11383 | if (hdr_len & 0x10) | |
11384 | base_flags |= 0x00000010; | |
11385 | base_flags |= (hdr_len & 0x3e0) << 5; | |
63c3a66f | 11386 | } else if (tg3_flag(tp, HW_TSO_2)) |
bb158d69 | 11387 | mss |= hdr_len << 9; |
63c3a66f | 11388 | else if (tg3_flag(tp, HW_TSO_1) || |
bb158d69 MC |
11389 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
11390 | mss |= (TG3_TSO_TCP_OPT_LEN << 9); | |
11391 | } else { | |
11392 | base_flags |= (TG3_TSO_TCP_OPT_LEN << 10); | |
11393 | } | |
11394 | ||
11395 | data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header); | |
11396 | } else { | |
11397 | num_pkts = 1; | |
11398 | data_off = ETH_HLEN; | |
11399 | } | |
11400 | ||
11401 | for (i = data_off; i < tx_len; i++) | |
c76949a6 MC |
11402 | tx_data[i] = (u8) (i & 0xff); |
11403 | ||
f4188d8a AD |
11404 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); |
11405 | if (pci_dma_mapping_error(tp->pdev, map)) { | |
a21771dd MC |
11406 | dev_kfree_skb(skb); |
11407 | return -EIO; | |
11408 | } | |
c76949a6 | 11409 | |
0d681b27 MC |
11410 | val = tnapi->tx_prod; |
11411 | tnapi->tx_buffers[val].skb = skb; | |
11412 | dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map); | |
11413 | ||
c76949a6 | 11414 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 11415 | rnapi->coal_now); |
c76949a6 MC |
11416 | |
11417 | udelay(10); | |
11418 | ||
898a56f8 | 11419 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; |
c76949a6 | 11420 | |
84b67b27 MC |
11421 | budget = tg3_tx_avail(tnapi); |
11422 | if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len, | |
d1a3b737 MC |
11423 | base_flags | TXD_FLAG_END, mss, 0)) { |
11424 | tnapi->tx_buffers[val].skb = NULL; | |
11425 | dev_kfree_skb(skb); | |
11426 | return -EIO; | |
11427 | } | |
c76949a6 | 11428 | |
f3f3f27e | 11429 | tnapi->tx_prod++; |
c76949a6 | 11430 | |
f3f3f27e MC |
11431 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); |
11432 | tr32_mailbox(tnapi->prodmbox); | |
c76949a6 MC |
11433 | |
11434 | udelay(10); | |
11435 | ||
303fc921 MC |
11436 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ |
11437 | for (i = 0; i < 35; i++) { | |
c76949a6 | 11438 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 11439 | coal_now); |
c76949a6 MC |
11440 | |
11441 | udelay(10); | |
11442 | ||
898a56f8 MC |
11443 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; |
11444 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
f3f3f27e | 11445 | if ((tx_idx == tnapi->tx_prod) && |
c76949a6 MC |
11446 | (rx_idx == (rx_start_idx + num_pkts))) |
11447 | break; | |
11448 | } | |
11449 | ||
0d681b27 | 11450 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, 0); |
c76949a6 MC |
11451 | dev_kfree_skb(skb); |
11452 | ||
f3f3f27e | 11453 | if (tx_idx != tnapi->tx_prod) |
c76949a6 MC |
11454 | goto out; |
11455 | ||
11456 | if (rx_idx != rx_start_idx + num_pkts) | |
11457 | goto out; | |
11458 | ||
bb158d69 MC |
11459 | val = data_off; |
11460 | while (rx_idx != rx_start_idx) { | |
11461 | desc = &rnapi->rx_rcb[rx_start_idx++]; | |
11462 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
11463 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
c76949a6 | 11464 | |
bb158d69 MC |
11465 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && |
11466 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
11467 | goto out; | |
c76949a6 | 11468 | |
bb158d69 MC |
11469 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) |
11470 | - ETH_FCS_LEN; | |
c76949a6 | 11471 | |
bb158d69 MC |
11472 | if (loopback_mode != TG3_TSO_LOOPBACK) { |
11473 | if (rx_len != tx_len) | |
11474 | goto out; | |
4852a861 | 11475 | |
bb158d69 MC |
11476 | if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { |
11477 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
11478 | goto out; | |
11479 | } else { | |
11480 | if (opaque_key != RXD_OPAQUE_RING_JUMBO) | |
11481 | goto out; | |
11482 | } | |
11483 | } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
11484 | (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
54e0a67f | 11485 | >> RXD_TCPCSUM_SHIFT != 0xffff) { |
4852a861 | 11486 | goto out; |
bb158d69 | 11487 | } |
4852a861 | 11488 | |
bb158d69 MC |
11489 | if (opaque_key == RXD_OPAQUE_RING_STD) { |
11490 | rx_skb = tpr->rx_std_buffers[desc_idx].skb; | |
11491 | map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], | |
11492 | mapping); | |
11493 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { | |
11494 | rx_skb = tpr->rx_jmb_buffers[desc_idx].skb; | |
11495 | map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], | |
11496 | mapping); | |
11497 | } else | |
11498 | goto out; | |
c76949a6 | 11499 | |
bb158d69 MC |
11500 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, |
11501 | PCI_DMA_FROMDEVICE); | |
c76949a6 | 11502 | |
bb158d69 MC |
11503 | for (i = data_off; i < rx_len; i++, val++) { |
11504 | if (*(rx_skb->data + i) != (u8) (val & 0xff)) | |
11505 | goto out; | |
11506 | } | |
c76949a6 | 11507 | } |
bb158d69 | 11508 | |
c76949a6 | 11509 | err = 0; |
6aa20a22 | 11510 | |
c76949a6 MC |
11511 | /* tg3_free_rings will unmap and free the rx_skb */ |
11512 | out: | |
11513 | return err; | |
11514 | } | |
11515 | ||
00c266b7 MC |
11516 | #define TG3_STD_LOOPBACK_FAILED 1 |
11517 | #define TG3_JMB_LOOPBACK_FAILED 2 | |
bb158d69 | 11518 | #define TG3_TSO_LOOPBACK_FAILED 4 |
00c266b7 MC |
11519 | |
11520 | #define TG3_MAC_LOOPBACK_SHIFT 0 | |
11521 | #define TG3_PHY_LOOPBACK_SHIFT 4 | |
bb158d69 | 11522 | #define TG3_LOOPBACK_FAILED 0x00000077 |
9f40dead MC |
11523 | |
11524 | static int tg3_test_loopback(struct tg3 *tp) | |
11525 | { | |
11526 | int err = 0; | |
2215e24c | 11527 | u32 eee_cap; |
9f40dead MC |
11528 | |
11529 | if (!netif_running(tp->dev)) | |
11530 | return TG3_LOOPBACK_FAILED; | |
11531 | ||
ab789046 MC |
11532 | eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; |
11533 | tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; | |
11534 | ||
b9ec6c1b | 11535 | err = tg3_reset_hw(tp, 1); |
ab789046 MC |
11536 | if (err) { |
11537 | err = TG3_LOOPBACK_FAILED; | |
11538 | goto done; | |
11539 | } | |
9f40dead | 11540 | |
63c3a66f | 11541 | if (tg3_flag(tp, ENABLE_RSS)) { |
4a85f098 MC |
11542 | int i; |
11543 | ||
11544 | /* Reroute all rx packets to the 1st queue */ | |
11545 | for (i = MAC_RSS_INDIR_TBL_0; | |
11546 | i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4) | |
11547 | tw32(i, 0x0); | |
11548 | } | |
11549 | ||
6833c043 | 11550 | /* Turn off gphy autopowerdown. */ |
f07e9af3 | 11551 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
11552 | tg3_phy_toggle_apd(tp, false); |
11553 | ||
6e01b20b MC |
11554 | /* HW errata - mac loopback fails in some cases on 5780. |
11555 | * Normal traffic and PHY loopback are not affected by | |
11556 | * errata. Also, the MAC loopback test is deprecated for | |
11557 | * all newer ASIC revisions. | |
11558 | */ | |
11559 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | |
11560 | !tg3_flag(tp, CPMU_PRESENT)) { | |
11561 | tg3_mac_loopback(tp, true); | |
9936bcf6 | 11562 | |
6e01b20b MC |
11563 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_MAC_LOOPBACK)) |
11564 | err |= TG3_STD_LOOPBACK_FAILED << | |
11565 | TG3_MAC_LOOPBACK_SHIFT; | |
11566 | ||
11567 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && | |
11568 | tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_MAC_LOOPBACK)) | |
11569 | err |= TG3_JMB_LOOPBACK_FAILED << | |
11570 | TG3_MAC_LOOPBACK_SHIFT; | |
11571 | ||
11572 | tg3_mac_loopback(tp, false); | |
11573 | } | |
4852a861 | 11574 | |
f07e9af3 | 11575 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
63c3a66f | 11576 | !tg3_flag(tp, USE_PHYLIB)) { |
4852a861 | 11577 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_PHY_LOOPBACK)) |
00c266b7 MC |
11578 | err |= TG3_STD_LOOPBACK_FAILED << |
11579 | TG3_PHY_LOOPBACK_SHIFT; | |
63c3a66f | 11580 | if (tg3_flag(tp, TSO_CAPABLE) && |
bb158d69 MC |
11581 | tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_TSO_LOOPBACK)) |
11582 | err |= TG3_TSO_LOOPBACK_FAILED << | |
11583 | TG3_PHY_LOOPBACK_SHIFT; | |
63c3a66f | 11584 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && |
4852a861 | 11585 | tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_PHY_LOOPBACK)) |
00c266b7 MC |
11586 | err |= TG3_JMB_LOOPBACK_FAILED << |
11587 | TG3_PHY_LOOPBACK_SHIFT; | |
9f40dead MC |
11588 | } |
11589 | ||
6833c043 | 11590 | /* Re-enable gphy autopowerdown. */ |
f07e9af3 | 11591 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
11592 | tg3_phy_toggle_apd(tp, true); |
11593 | ||
ab789046 MC |
11594 | done: |
11595 | tp->phy_flags |= eee_cap; | |
11596 | ||
9f40dead MC |
11597 | return err; |
11598 | } | |
11599 | ||
4cafd3f5 MC |
11600 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, |
11601 | u64 *data) | |
11602 | { | |
566f86ad MC |
11603 | struct tg3 *tp = netdev_priv(dev); |
11604 | ||
bed9829f MC |
11605 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && |
11606 | tg3_power_up(tp)) { | |
11607 | etest->flags |= ETH_TEST_FL_FAILED; | |
11608 | memset(data, 1, sizeof(u64) * TG3_NUM_TEST); | |
11609 | return; | |
11610 | } | |
bc1c7567 | 11611 | |
566f86ad MC |
11612 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); |
11613 | ||
11614 | if (tg3_test_nvram(tp) != 0) { | |
11615 | etest->flags |= ETH_TEST_FL_FAILED; | |
11616 | data[0] = 1; | |
11617 | } | |
ca43007a MC |
11618 | if (tg3_test_link(tp) != 0) { |
11619 | etest->flags |= ETH_TEST_FL_FAILED; | |
11620 | data[1] = 1; | |
11621 | } | |
a71116d1 | 11622 | if (etest->flags & ETH_TEST_FL_OFFLINE) { |
b02fd9e3 | 11623 | int err, err2 = 0, irq_sync = 0; |
bbe832c0 MC |
11624 | |
11625 | if (netif_running(dev)) { | |
b02fd9e3 | 11626 | tg3_phy_stop(tp); |
a71116d1 | 11627 | tg3_netif_stop(tp); |
bbe832c0 MC |
11628 | irq_sync = 1; |
11629 | } | |
a71116d1 | 11630 | |
bbe832c0 | 11631 | tg3_full_lock(tp, irq_sync); |
a71116d1 MC |
11632 | |
11633 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
ec41c7df | 11634 | err = tg3_nvram_lock(tp); |
a71116d1 | 11635 | tg3_halt_cpu(tp, RX_CPU_BASE); |
63c3a66f | 11636 | if (!tg3_flag(tp, 5705_PLUS)) |
a71116d1 | 11637 | tg3_halt_cpu(tp, TX_CPU_BASE); |
ec41c7df MC |
11638 | if (!err) |
11639 | tg3_nvram_unlock(tp); | |
a71116d1 | 11640 | |
f07e9af3 | 11641 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
d9ab5ad1 MC |
11642 | tg3_phy_reset(tp); |
11643 | ||
a71116d1 MC |
11644 | if (tg3_test_registers(tp) != 0) { |
11645 | etest->flags |= ETH_TEST_FL_FAILED; | |
11646 | data[2] = 1; | |
11647 | } | |
7942e1db MC |
11648 | if (tg3_test_memory(tp) != 0) { |
11649 | etest->flags |= ETH_TEST_FL_FAILED; | |
11650 | data[3] = 1; | |
11651 | } | |
9f40dead | 11652 | if ((data[4] = tg3_test_loopback(tp)) != 0) |
c76949a6 | 11653 | etest->flags |= ETH_TEST_FL_FAILED; |
a71116d1 | 11654 | |
f47c11ee DM |
11655 | tg3_full_unlock(tp); |
11656 | ||
d4bc3927 MC |
11657 | if (tg3_test_interrupt(tp) != 0) { |
11658 | etest->flags |= ETH_TEST_FL_FAILED; | |
11659 | data[5] = 1; | |
11660 | } | |
f47c11ee DM |
11661 | |
11662 | tg3_full_lock(tp, 0); | |
d4bc3927 | 11663 | |
a71116d1 MC |
11664 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
11665 | if (netif_running(dev)) { | |
63c3a66f | 11666 | tg3_flag_set(tp, INIT_COMPLETE); |
b02fd9e3 MC |
11667 | err2 = tg3_restart_hw(tp, 1); |
11668 | if (!err2) | |
b9ec6c1b | 11669 | tg3_netif_start(tp); |
a71116d1 | 11670 | } |
f47c11ee DM |
11671 | |
11672 | tg3_full_unlock(tp); | |
b02fd9e3 MC |
11673 | |
11674 | if (irq_sync && !err2) | |
11675 | tg3_phy_start(tp); | |
a71116d1 | 11676 | } |
80096068 | 11677 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
c866b7ea | 11678 | tg3_power_down(tp); |
bc1c7567 | 11679 | |
4cafd3f5 MC |
11680 | } |
11681 | ||
1da177e4 LT |
11682 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
11683 | { | |
11684 | struct mii_ioctl_data *data = if_mii(ifr); | |
11685 | struct tg3 *tp = netdev_priv(dev); | |
11686 | int err; | |
11687 | ||
63c3a66f | 11688 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 11689 | struct phy_device *phydev; |
f07e9af3 | 11690 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 11691 | return -EAGAIN; |
3f0e3ad7 | 11692 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
28b04113 | 11693 | return phy_mii_ioctl(phydev, ifr, cmd); |
b02fd9e3 MC |
11694 | } |
11695 | ||
33f401ae | 11696 | switch (cmd) { |
1da177e4 | 11697 | case SIOCGMIIPHY: |
882e9793 | 11698 | data->phy_id = tp->phy_addr; |
1da177e4 LT |
11699 | |
11700 | /* fallthru */ | |
11701 | case SIOCGMIIREG: { | |
11702 | u32 mii_regval; | |
11703 | ||
f07e9af3 | 11704 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11705 | break; /* We have no PHY */ |
11706 | ||
34eea5ac | 11707 | if (!netif_running(dev)) |
bc1c7567 MC |
11708 | return -EAGAIN; |
11709 | ||
f47c11ee | 11710 | spin_lock_bh(&tp->lock); |
1da177e4 | 11711 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); |
f47c11ee | 11712 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11713 | |
11714 | data->val_out = mii_regval; | |
11715 | ||
11716 | return err; | |
11717 | } | |
11718 | ||
11719 | case SIOCSMIIREG: | |
f07e9af3 | 11720 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11721 | break; /* We have no PHY */ |
11722 | ||
34eea5ac | 11723 | if (!netif_running(dev)) |
bc1c7567 MC |
11724 | return -EAGAIN; |
11725 | ||
f47c11ee | 11726 | spin_lock_bh(&tp->lock); |
1da177e4 | 11727 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); |
f47c11ee | 11728 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11729 | |
11730 | return err; | |
11731 | ||
11732 | default: | |
11733 | /* do nothing */ | |
11734 | break; | |
11735 | } | |
11736 | return -EOPNOTSUPP; | |
11737 | } | |
11738 | ||
15f9850d DM |
11739 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11740 | { | |
11741 | struct tg3 *tp = netdev_priv(dev); | |
11742 | ||
11743 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
11744 | return 0; | |
11745 | } | |
11746 | ||
d244c892 MC |
11747 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11748 | { | |
11749 | struct tg3 *tp = netdev_priv(dev); | |
11750 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
11751 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
11752 | ||
63c3a66f | 11753 | if (!tg3_flag(tp, 5705_PLUS)) { |
d244c892 MC |
11754 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; |
11755 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
11756 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
11757 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
11758 | } | |
11759 | ||
11760 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
11761 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
11762 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
11763 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
11764 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
11765 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
11766 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
11767 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
11768 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
11769 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
11770 | return -EINVAL; | |
11771 | ||
11772 | /* No rx interrupts will be generated if both are zero */ | |
11773 | if ((ec->rx_coalesce_usecs == 0) && | |
11774 | (ec->rx_max_coalesced_frames == 0)) | |
11775 | return -EINVAL; | |
11776 | ||
11777 | /* No tx interrupts will be generated if both are zero */ | |
11778 | if ((ec->tx_coalesce_usecs == 0) && | |
11779 | (ec->tx_max_coalesced_frames == 0)) | |
11780 | return -EINVAL; | |
11781 | ||
11782 | /* Only copy relevant parameters, ignore all others. */ | |
11783 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
11784 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
11785 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
11786 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
11787 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
11788 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
11789 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
11790 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
11791 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
11792 | ||
11793 | if (netif_running(dev)) { | |
11794 | tg3_full_lock(tp, 0); | |
11795 | __tg3_set_coalesce(tp, &tp->coal); | |
11796 | tg3_full_unlock(tp); | |
11797 | } | |
11798 | return 0; | |
11799 | } | |
11800 | ||
7282d491 | 11801 | static const struct ethtool_ops tg3_ethtool_ops = { |
1da177e4 LT |
11802 | .get_settings = tg3_get_settings, |
11803 | .set_settings = tg3_set_settings, | |
11804 | .get_drvinfo = tg3_get_drvinfo, | |
11805 | .get_regs_len = tg3_get_regs_len, | |
11806 | .get_regs = tg3_get_regs, | |
11807 | .get_wol = tg3_get_wol, | |
11808 | .set_wol = tg3_set_wol, | |
11809 | .get_msglevel = tg3_get_msglevel, | |
11810 | .set_msglevel = tg3_set_msglevel, | |
11811 | .nway_reset = tg3_nway_reset, | |
11812 | .get_link = ethtool_op_get_link, | |
11813 | .get_eeprom_len = tg3_get_eeprom_len, | |
11814 | .get_eeprom = tg3_get_eeprom, | |
11815 | .set_eeprom = tg3_set_eeprom, | |
11816 | .get_ringparam = tg3_get_ringparam, | |
11817 | .set_ringparam = tg3_set_ringparam, | |
11818 | .get_pauseparam = tg3_get_pauseparam, | |
11819 | .set_pauseparam = tg3_set_pauseparam, | |
4cafd3f5 | 11820 | .self_test = tg3_self_test, |
1da177e4 | 11821 | .get_strings = tg3_get_strings, |
81b8709c | 11822 | .set_phys_id = tg3_set_phys_id, |
1da177e4 | 11823 | .get_ethtool_stats = tg3_get_ethtool_stats, |
15f9850d | 11824 | .get_coalesce = tg3_get_coalesce, |
d244c892 | 11825 | .set_coalesce = tg3_set_coalesce, |
b9f2c044 | 11826 | .get_sset_count = tg3_get_sset_count, |
1da177e4 LT |
11827 | }; |
11828 | ||
11829 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |
11830 | { | |
1b27777a | 11831 | u32 cursize, val, magic; |
1da177e4 LT |
11832 | |
11833 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
11834 | ||
e4f34110 | 11835 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1da177e4 LT |
11836 | return; |
11837 | ||
b16250e3 MC |
11838 | if ((magic != TG3_EEPROM_MAGIC) && |
11839 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
11840 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
1da177e4 LT |
11841 | return; |
11842 | ||
11843 | /* | |
11844 | * Size the chip by reading offsets at increasing powers of two. | |
11845 | * When we encounter our validation signature, we know the addressing | |
11846 | * has wrapped around, and thus have our chip size. | |
11847 | */ | |
1b27777a | 11848 | cursize = 0x10; |
1da177e4 LT |
11849 | |
11850 | while (cursize < tp->nvram_size) { | |
e4f34110 | 11851 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
1da177e4 LT |
11852 | return; |
11853 | ||
1820180b | 11854 | if (val == magic) |
1da177e4 LT |
11855 | break; |
11856 | ||
11857 | cursize <<= 1; | |
11858 | } | |
11859 | ||
11860 | tp->nvram_size = cursize; | |
11861 | } | |
6aa20a22 | 11862 | |
1da177e4 LT |
11863 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) |
11864 | { | |
11865 | u32 val; | |
11866 | ||
63c3a66f | 11867 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) |
1b27777a MC |
11868 | return; |
11869 | ||
11870 | /* Selfboot format */ | |
1820180b | 11871 | if (val != TG3_EEPROM_MAGIC) { |
1b27777a MC |
11872 | tg3_get_eeprom_size(tp); |
11873 | return; | |
11874 | } | |
11875 | ||
6d348f2c | 11876 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { |
1da177e4 | 11877 | if (val != 0) { |
6d348f2c MC |
11878 | /* This is confusing. We want to operate on the |
11879 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
11880 | * call will read from NVRAM and byteswap the data | |
11881 | * according to the byteswapping settings for all | |
11882 | * other register accesses. This ensures the data we | |
11883 | * want will always reside in the lower 16-bits. | |
11884 | * However, the data in NVRAM is in LE format, which | |
11885 | * means the data from the NVRAM read will always be | |
11886 | * opposite the endianness of the CPU. The 16-bit | |
11887 | * byteswap then brings the data to CPU endianness. | |
11888 | */ | |
11889 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
1da177e4 LT |
11890 | return; |
11891 | } | |
11892 | } | |
fd1122a2 | 11893 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
1da177e4 LT |
11894 | } |
11895 | ||
11896 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
11897 | { | |
11898 | u32 nvcfg1; | |
11899 | ||
11900 | nvcfg1 = tr32(NVRAM_CFG1); | |
11901 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
63c3a66f | 11902 | tg3_flag_set(tp, FLASH); |
8590a603 | 11903 | } else { |
1da177e4 LT |
11904 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
11905 | tw32(NVRAM_CFG1, nvcfg1); | |
11906 | } | |
11907 | ||
6ff6f81d | 11908 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
63c3a66f | 11909 | tg3_flag(tp, 5780_CLASS)) { |
1da177e4 | 11910 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
8590a603 MC |
11911 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
11912 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11913 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
63c3a66f | 11914 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
11915 | break; |
11916 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
11917 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11918 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
11919 | break; | |
11920 | case FLASH_VENDOR_ATMEL_EEPROM: | |
11921 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11922 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
63c3a66f | 11923 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
11924 | break; |
11925 | case FLASH_VENDOR_ST: | |
11926 | tp->nvram_jedecnum = JEDEC_ST; | |
11927 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
63c3a66f | 11928 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
11929 | break; |
11930 | case FLASH_VENDOR_SAIFUN: | |
11931 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
11932 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
11933 | break; | |
11934 | case FLASH_VENDOR_SST_SMALL: | |
11935 | case FLASH_VENDOR_SST_LARGE: | |
11936 | tp->nvram_jedecnum = JEDEC_SST; | |
11937 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
11938 | break; | |
1da177e4 | 11939 | } |
8590a603 | 11940 | } else { |
1da177e4 LT |
11941 | tp->nvram_jedecnum = JEDEC_ATMEL; |
11942 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
63c3a66f | 11943 | tg3_flag_set(tp, NVRAM_BUFFERED); |
1da177e4 LT |
11944 | } |
11945 | } | |
11946 | ||
a1b950d5 MC |
11947 | static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) |
11948 | { | |
11949 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
11950 | case FLASH_5752PAGE_SIZE_256: | |
11951 | tp->nvram_pagesize = 256; | |
11952 | break; | |
11953 | case FLASH_5752PAGE_SIZE_512: | |
11954 | tp->nvram_pagesize = 512; | |
11955 | break; | |
11956 | case FLASH_5752PAGE_SIZE_1K: | |
11957 | tp->nvram_pagesize = 1024; | |
11958 | break; | |
11959 | case FLASH_5752PAGE_SIZE_2K: | |
11960 | tp->nvram_pagesize = 2048; | |
11961 | break; | |
11962 | case FLASH_5752PAGE_SIZE_4K: | |
11963 | tp->nvram_pagesize = 4096; | |
11964 | break; | |
11965 | case FLASH_5752PAGE_SIZE_264: | |
11966 | tp->nvram_pagesize = 264; | |
11967 | break; | |
11968 | case FLASH_5752PAGE_SIZE_528: | |
11969 | tp->nvram_pagesize = 528; | |
11970 | break; | |
11971 | } | |
11972 | } | |
11973 | ||
361b4ac2 MC |
11974 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) |
11975 | { | |
11976 | u32 nvcfg1; | |
11977 | ||
11978 | nvcfg1 = tr32(NVRAM_CFG1); | |
11979 | ||
e6af301b MC |
11980 | /* NVRAM protection for TPM */ |
11981 | if (nvcfg1 & (1 << 27)) | |
63c3a66f | 11982 | tg3_flag_set(tp, PROTECTED_NVRAM); |
e6af301b | 11983 | |
361b4ac2 | 11984 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
8590a603 MC |
11985 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: |
11986 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
11987 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 11988 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
11989 | break; |
11990 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11991 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
11992 | tg3_flag_set(tp, NVRAM_BUFFERED); |
11993 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
11994 | break; |
11995 | case FLASH_5752VENDOR_ST_M45PE10: | |
11996 | case FLASH_5752VENDOR_ST_M45PE20: | |
11997 | case FLASH_5752VENDOR_ST_M45PE40: | |
11998 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
11999 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12000 | tg3_flag_set(tp, FLASH); | |
8590a603 | 12001 | break; |
361b4ac2 MC |
12002 | } |
12003 | ||
63c3a66f | 12004 | if (tg3_flag(tp, FLASH)) { |
a1b950d5 | 12005 | tg3_nvram_get_pagesize(tp, nvcfg1); |
8590a603 | 12006 | } else { |
361b4ac2 MC |
12007 | /* For eeprom, set pagesize to maximum eeprom size */ |
12008 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
12009 | ||
12010 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12011 | tw32(NVRAM_CFG1, nvcfg1); | |
12012 | } | |
12013 | } | |
12014 | ||
d3c7b886 MC |
12015 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) |
12016 | { | |
989a9d23 | 12017 | u32 nvcfg1, protect = 0; |
d3c7b886 MC |
12018 | |
12019 | nvcfg1 = tr32(NVRAM_CFG1); | |
12020 | ||
12021 | /* NVRAM protection for TPM */ | |
989a9d23 | 12022 | if (nvcfg1 & (1 << 27)) { |
63c3a66f | 12023 | tg3_flag_set(tp, PROTECTED_NVRAM); |
989a9d23 MC |
12024 | protect = 1; |
12025 | } | |
d3c7b886 | 12026 | |
989a9d23 MC |
12027 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
12028 | switch (nvcfg1) { | |
8590a603 MC |
12029 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
12030 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
12031 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
12032 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
12033 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12034 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12035 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12036 | tp->nvram_pagesize = 264; |
12037 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
12038 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
12039 | tp->nvram_size = (protect ? 0x3e200 : | |
12040 | TG3_NVRAM_SIZE_512KB); | |
12041 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
12042 | tp->nvram_size = (protect ? 0x1f200 : | |
12043 | TG3_NVRAM_SIZE_256KB); | |
12044 | else | |
12045 | tp->nvram_size = (protect ? 0x1f200 : | |
12046 | TG3_NVRAM_SIZE_128KB); | |
12047 | break; | |
12048 | case FLASH_5752VENDOR_ST_M45PE10: | |
12049 | case FLASH_5752VENDOR_ST_M45PE20: | |
12050 | case FLASH_5752VENDOR_ST_M45PE40: | |
12051 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12052 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12053 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12054 | tp->nvram_pagesize = 256; |
12055 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
12056 | tp->nvram_size = (protect ? | |
12057 | TG3_NVRAM_SIZE_64KB : | |
12058 | TG3_NVRAM_SIZE_128KB); | |
12059 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
12060 | tp->nvram_size = (protect ? | |
12061 | TG3_NVRAM_SIZE_64KB : | |
12062 | TG3_NVRAM_SIZE_256KB); | |
12063 | else | |
12064 | tp->nvram_size = (protect ? | |
12065 | TG3_NVRAM_SIZE_128KB : | |
12066 | TG3_NVRAM_SIZE_512KB); | |
12067 | break; | |
d3c7b886 MC |
12068 | } |
12069 | } | |
12070 | ||
1b27777a MC |
12071 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) |
12072 | { | |
12073 | u32 nvcfg1; | |
12074 | ||
12075 | nvcfg1 = tr32(NVRAM_CFG1); | |
12076 | ||
12077 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
8590a603 MC |
12078 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: |
12079 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
12080 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
12081 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
12082 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12083 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 | 12084 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
1b27777a | 12085 | |
8590a603 MC |
12086 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
12087 | tw32(NVRAM_CFG1, nvcfg1); | |
12088 | break; | |
12089 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12090 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
12091 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
12092 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
12093 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12094 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12095 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12096 | tp->nvram_pagesize = 264; |
12097 | break; | |
12098 | case FLASH_5752VENDOR_ST_M45PE10: | |
12099 | case FLASH_5752VENDOR_ST_M45PE20: | |
12100 | case FLASH_5752VENDOR_ST_M45PE40: | |
12101 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12102 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12103 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12104 | tp->nvram_pagesize = 256; |
12105 | break; | |
1b27777a MC |
12106 | } |
12107 | } | |
12108 | ||
6b91fa02 MC |
12109 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) |
12110 | { | |
12111 | u32 nvcfg1, protect = 0; | |
12112 | ||
12113 | nvcfg1 = tr32(NVRAM_CFG1); | |
12114 | ||
12115 | /* NVRAM protection for TPM */ | |
12116 | if (nvcfg1 & (1 << 27)) { | |
63c3a66f | 12117 | tg3_flag_set(tp, PROTECTED_NVRAM); |
6b91fa02 MC |
12118 | protect = 1; |
12119 | } | |
12120 | ||
12121 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
12122 | switch (nvcfg1) { | |
8590a603 MC |
12123 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
12124 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
12125 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
12126 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
12127 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
12128 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
12129 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
12130 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
12131 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12132 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12133 | tg3_flag_set(tp, FLASH); | |
12134 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); | |
8590a603 MC |
12135 | tp->nvram_pagesize = 256; |
12136 | break; | |
12137 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
12138 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
12139 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
12140 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
12141 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
12142 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
12143 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
12144 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
12145 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12146 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12147 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12148 | tp->nvram_pagesize = 256; |
12149 | break; | |
6b91fa02 MC |
12150 | } |
12151 | ||
12152 | if (protect) { | |
12153 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
12154 | } else { | |
12155 | switch (nvcfg1) { | |
8590a603 MC |
12156 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
12157 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
12158 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
12159 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
12160 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
12161 | break; | |
12162 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
12163 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
12164 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
12165 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
12166 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12167 | break; | |
12168 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
12169 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
12170 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
12171 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
12172 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12173 | break; | |
12174 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
12175 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
12176 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
12177 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
12178 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12179 | break; | |
6b91fa02 MC |
12180 | } |
12181 | } | |
12182 | } | |
12183 | ||
b5d3772c MC |
12184 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) |
12185 | { | |
12186 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12187 | tg3_flag_set(tp, NVRAM_BUFFERED); |
b5d3772c MC |
12188 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12189 | } | |
12190 | ||
321d32a0 MC |
12191 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) |
12192 | { | |
12193 | u32 nvcfg1; | |
12194 | ||
12195 | nvcfg1 = tr32(NVRAM_CFG1); | |
12196 | ||
12197 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12198 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
12199 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
12200 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12201 | tg3_flag_set(tp, NVRAM_BUFFERED); |
321d32a0 MC |
12202 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12203 | ||
12204 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12205 | tw32(NVRAM_CFG1, nvcfg1); | |
12206 | return; | |
12207 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12208 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
12209 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
12210 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
12211 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
12212 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
12213 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
12214 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12215 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12216 | tg3_flag_set(tp, FLASH); | |
321d32a0 MC |
12217 | |
12218 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12219 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12220 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
12221 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
12222 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12223 | break; | |
12224 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
12225 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
12226 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12227 | break; | |
12228 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
12229 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
12230 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12231 | break; | |
12232 | } | |
12233 | break; | |
12234 | case FLASH_5752VENDOR_ST_M45PE10: | |
12235 | case FLASH_5752VENDOR_ST_M45PE20: | |
12236 | case FLASH_5752VENDOR_ST_M45PE40: | |
12237 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12238 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12239 | tg3_flag_set(tp, FLASH); | |
321d32a0 MC |
12240 | |
12241 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12242 | case FLASH_5752VENDOR_ST_M45PE10: | |
12243 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12244 | break; | |
12245 | case FLASH_5752VENDOR_ST_M45PE20: | |
12246 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12247 | break; | |
12248 | case FLASH_5752VENDOR_ST_M45PE40: | |
12249 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12250 | break; | |
12251 | } | |
12252 | break; | |
12253 | default: | |
63c3a66f | 12254 | tg3_flag_set(tp, NO_NVRAM); |
321d32a0 MC |
12255 | return; |
12256 | } | |
12257 | ||
a1b950d5 MC |
12258 | tg3_nvram_get_pagesize(tp, nvcfg1); |
12259 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12260 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
a1b950d5 MC |
12261 | } |
12262 | ||
12263 | ||
12264 | static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp) | |
12265 | { | |
12266 | u32 nvcfg1; | |
12267 | ||
12268 | nvcfg1 = tr32(NVRAM_CFG1); | |
12269 | ||
12270 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12271 | case FLASH_5717VENDOR_ATMEL_EEPROM: | |
12272 | case FLASH_5717VENDOR_MICRO_EEPROM: | |
12273 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12274 | tg3_flag_set(tp, NVRAM_BUFFERED); |
a1b950d5 MC |
12275 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12276 | ||
12277 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12278 | tw32(NVRAM_CFG1, nvcfg1); | |
12279 | return; | |
12280 | case FLASH_5717VENDOR_ATMEL_MDB011D: | |
12281 | case FLASH_5717VENDOR_ATMEL_ADB011B: | |
12282 | case FLASH_5717VENDOR_ATMEL_ADB011D: | |
12283 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
12284 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
12285 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12286 | case FLASH_5717VENDOR_ATMEL_45USPT: | |
12287 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12288 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12289 | tg3_flag_set(tp, FLASH); | |
a1b950d5 MC |
12290 | |
12291 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12292 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
66ee33bf MC |
12293 | /* Detect size with tg3_nvram_get_size() */ |
12294 | break; | |
a1b950d5 MC |
12295 | case FLASH_5717VENDOR_ATMEL_ADB021B: |
12296 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12297 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12298 | break; | |
12299 | default: | |
12300 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12301 | break; | |
12302 | } | |
321d32a0 | 12303 | break; |
a1b950d5 MC |
12304 | case FLASH_5717VENDOR_ST_M_M25PE10: |
12305 | case FLASH_5717VENDOR_ST_A_M25PE10: | |
12306 | case FLASH_5717VENDOR_ST_M_M45PE10: | |
12307 | case FLASH_5717VENDOR_ST_A_M45PE10: | |
12308 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
12309 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
12310 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
12311 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
12312 | case FLASH_5717VENDOR_ST_25USPT: | |
12313 | case FLASH_5717VENDOR_ST_45USPT: | |
12314 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12315 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12316 | tg3_flag_set(tp, FLASH); | |
a1b950d5 MC |
12317 | |
12318 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12319 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
a1b950d5 | 12320 | case FLASH_5717VENDOR_ST_M_M45PE20: |
66ee33bf MC |
12321 | /* Detect size with tg3_nvram_get_size() */ |
12322 | break; | |
12323 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
a1b950d5 MC |
12324 | case FLASH_5717VENDOR_ST_A_M45PE20: |
12325 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12326 | break; | |
12327 | default: | |
12328 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12329 | break; | |
12330 | } | |
321d32a0 | 12331 | break; |
a1b950d5 | 12332 | default: |
63c3a66f | 12333 | tg3_flag_set(tp, NO_NVRAM); |
a1b950d5 | 12334 | return; |
321d32a0 | 12335 | } |
a1b950d5 MC |
12336 | |
12337 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12338 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12339 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
321d32a0 MC |
12340 | } |
12341 | ||
9b91b5f1 MC |
12342 | static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp) |
12343 | { | |
12344 | u32 nvcfg1, nvmpinstrp; | |
12345 | ||
12346 | nvcfg1 = tr32(NVRAM_CFG1); | |
12347 | nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK; | |
12348 | ||
12349 | switch (nvmpinstrp) { | |
12350 | case FLASH_5720_EEPROM_HD: | |
12351 | case FLASH_5720_EEPROM_LD: | |
12352 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12353 | tg3_flag_set(tp, NVRAM_BUFFERED); |
9b91b5f1 MC |
12354 | |
12355 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12356 | tw32(NVRAM_CFG1, nvcfg1); | |
12357 | if (nvmpinstrp == FLASH_5720_EEPROM_HD) | |
12358 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
12359 | else | |
12360 | tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; | |
12361 | return; | |
12362 | case FLASH_5720VENDOR_M_ATMEL_DB011D: | |
12363 | case FLASH_5720VENDOR_A_ATMEL_DB011B: | |
12364 | case FLASH_5720VENDOR_A_ATMEL_DB011D: | |
12365 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12366 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12367 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12368 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12369 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12370 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12371 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12372 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12373 | case FLASH_5720VENDOR_ATMEL_45USPT: | |
12374 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12375 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12376 | tg3_flag_set(tp, FLASH); | |
9b91b5f1 MC |
12377 | |
12378 | switch (nvmpinstrp) { | |
12379 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12380 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12381 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12382 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12383 | break; | |
12384 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12385 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12386 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12387 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12388 | break; | |
12389 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12390 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12391 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12392 | break; | |
12393 | default: | |
12394 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12395 | break; | |
12396 | } | |
12397 | break; | |
12398 | case FLASH_5720VENDOR_M_ST_M25PE10: | |
12399 | case FLASH_5720VENDOR_M_ST_M45PE10: | |
12400 | case FLASH_5720VENDOR_A_ST_M25PE10: | |
12401 | case FLASH_5720VENDOR_A_ST_M45PE10: | |
12402 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12403 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12404 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12405 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12406 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12407 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12408 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12409 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12410 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12411 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12412 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12413 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12414 | case FLASH_5720VENDOR_ST_25USPT: | |
12415 | case FLASH_5720VENDOR_ST_45USPT: | |
12416 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12417 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12418 | tg3_flag_set(tp, FLASH); | |
9b91b5f1 MC |
12419 | |
12420 | switch (nvmpinstrp) { | |
12421 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12422 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12423 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12424 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12425 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12426 | break; | |
12427 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12428 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12429 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12430 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12431 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12432 | break; | |
12433 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12434 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12435 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12436 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12437 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12438 | break; | |
12439 | default: | |
12440 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12441 | break; | |
12442 | } | |
12443 | break; | |
12444 | default: | |
63c3a66f | 12445 | tg3_flag_set(tp, NO_NVRAM); |
9b91b5f1 MC |
12446 | return; |
12447 | } | |
12448 | ||
12449 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12450 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12451 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
9b91b5f1 MC |
12452 | } |
12453 | ||
1da177e4 LT |
12454 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
12455 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
12456 | { | |
1da177e4 LT |
12457 | tw32_f(GRC_EEPROM_ADDR, |
12458 | (EEPROM_ADDR_FSM_RESET | | |
12459 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
12460 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
12461 | ||
9d57f01c | 12462 | msleep(1); |
1da177e4 LT |
12463 | |
12464 | /* Enable seeprom accesses. */ | |
12465 | tw32_f(GRC_LOCAL_CTRL, | |
12466 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
12467 | udelay(100); | |
12468 | ||
12469 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
12470 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
63c3a66f | 12471 | tg3_flag_set(tp, NVRAM); |
1da177e4 | 12472 | |
ec41c7df | 12473 | if (tg3_nvram_lock(tp)) { |
5129c3a3 MC |
12474 | netdev_warn(tp->dev, |
12475 | "Cannot get nvram lock, %s failed\n", | |
05dbe005 | 12476 | __func__); |
ec41c7df MC |
12477 | return; |
12478 | } | |
e6af301b | 12479 | tg3_enable_nvram_access(tp); |
1da177e4 | 12480 | |
989a9d23 MC |
12481 | tp->nvram_size = 0; |
12482 | ||
361b4ac2 MC |
12483 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
12484 | tg3_get_5752_nvram_info(tp); | |
d3c7b886 MC |
12485 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
12486 | tg3_get_5755_nvram_info(tp); | |
d30cdd28 | 12487 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
57e6983c MC |
12488 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
12489 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1b27777a | 12490 | tg3_get_5787_nvram_info(tp); |
6b91fa02 MC |
12491 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
12492 | tg3_get_5761_nvram_info(tp); | |
b5d3772c MC |
12493 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
12494 | tg3_get_5906_nvram_info(tp); | |
b703df6f MC |
12495 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
12496 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
321d32a0 | 12497 | tg3_get_57780_nvram_info(tp); |
9b91b5f1 MC |
12498 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
12499 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
a1b950d5 | 12500 | tg3_get_5717_nvram_info(tp); |
9b91b5f1 MC |
12501 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
12502 | tg3_get_5720_nvram_info(tp); | |
361b4ac2 MC |
12503 | else |
12504 | tg3_get_nvram_info(tp); | |
12505 | ||
989a9d23 MC |
12506 | if (tp->nvram_size == 0) |
12507 | tg3_get_nvram_size(tp); | |
1da177e4 | 12508 | |
e6af301b | 12509 | tg3_disable_nvram_access(tp); |
381291b7 | 12510 | tg3_nvram_unlock(tp); |
1da177e4 LT |
12511 | |
12512 | } else { | |
63c3a66f JP |
12513 | tg3_flag_clear(tp, NVRAM); |
12514 | tg3_flag_clear(tp, NVRAM_BUFFERED); | |
1da177e4 LT |
12515 | |
12516 | tg3_get_eeprom_size(tp); | |
12517 | } | |
12518 | } | |
12519 | ||
1da177e4 LT |
12520 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
12521 | u32 offset, u32 len, u8 *buf) | |
12522 | { | |
12523 | int i, j, rc = 0; | |
12524 | u32 val; | |
12525 | ||
12526 | for (i = 0; i < len; i += 4) { | |
b9fc7dc5 | 12527 | u32 addr; |
a9dc529d | 12528 | __be32 data; |
1da177e4 LT |
12529 | |
12530 | addr = offset + i; | |
12531 | ||
12532 | memcpy(&data, buf + i, 4); | |
12533 | ||
62cedd11 MC |
12534 | /* |
12535 | * The SEEPROM interface expects the data to always be opposite | |
12536 | * the native endian format. We accomplish this by reversing | |
12537 | * all the operations that would have been performed on the | |
12538 | * data from a call to tg3_nvram_read_be32(). | |
12539 | */ | |
12540 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
1da177e4 LT |
12541 | |
12542 | val = tr32(GRC_EEPROM_ADDR); | |
12543 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
12544 | ||
12545 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
12546 | EEPROM_ADDR_READ); | |
12547 | tw32(GRC_EEPROM_ADDR, val | | |
12548 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
12549 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
12550 | EEPROM_ADDR_START | | |
12551 | EEPROM_ADDR_WRITE); | |
6aa20a22 | 12552 | |
9d57f01c | 12553 | for (j = 0; j < 1000; j++) { |
1da177e4 LT |
12554 | val = tr32(GRC_EEPROM_ADDR); |
12555 | ||
12556 | if (val & EEPROM_ADDR_COMPLETE) | |
12557 | break; | |
9d57f01c | 12558 | msleep(1); |
1da177e4 LT |
12559 | } |
12560 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
12561 | rc = -EBUSY; | |
12562 | break; | |
12563 | } | |
12564 | } | |
12565 | ||
12566 | return rc; | |
12567 | } | |
12568 | ||
12569 | /* offset and length are dword aligned */ | |
12570 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
12571 | u8 *buf) | |
12572 | { | |
12573 | int ret = 0; | |
12574 | u32 pagesize = tp->nvram_pagesize; | |
12575 | u32 pagemask = pagesize - 1; | |
12576 | u32 nvram_cmd; | |
12577 | u8 *tmp; | |
12578 | ||
12579 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
12580 | if (tmp == NULL) | |
12581 | return -ENOMEM; | |
12582 | ||
12583 | while (len) { | |
12584 | int j; | |
e6af301b | 12585 | u32 phy_addr, page_off, size; |
1da177e4 LT |
12586 | |
12587 | phy_addr = offset & ~pagemask; | |
6aa20a22 | 12588 | |
1da177e4 | 12589 | for (j = 0; j < pagesize; j += 4) { |
a9dc529d MC |
12590 | ret = tg3_nvram_read_be32(tp, phy_addr + j, |
12591 | (__be32 *) (tmp + j)); | |
12592 | if (ret) | |
1da177e4 LT |
12593 | break; |
12594 | } | |
12595 | if (ret) | |
12596 | break; | |
12597 | ||
c6cdf436 | 12598 | page_off = offset & pagemask; |
1da177e4 LT |
12599 | size = pagesize; |
12600 | if (len < size) | |
12601 | size = len; | |
12602 | ||
12603 | len -= size; | |
12604 | ||
12605 | memcpy(tmp + page_off, buf, size); | |
12606 | ||
12607 | offset = offset + (pagesize - page_off); | |
12608 | ||
e6af301b | 12609 | tg3_enable_nvram_access(tp); |
1da177e4 LT |
12610 | |
12611 | /* | |
12612 | * Before we can erase the flash page, we need | |
12613 | * to issue a special "write enable" command. | |
12614 | */ | |
12615 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12616 | ||
12617 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12618 | break; | |
12619 | ||
12620 | /* Erase the target page */ | |
12621 | tw32(NVRAM_ADDR, phy_addr); | |
12622 | ||
12623 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
12624 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
12625 | ||
c6cdf436 | 12626 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) |
1da177e4 LT |
12627 | break; |
12628 | ||
12629 | /* Issue another write enable to start the write. */ | |
12630 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12631 | ||
12632 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12633 | break; | |
12634 | ||
12635 | for (j = 0; j < pagesize; j += 4) { | |
b9fc7dc5 | 12636 | __be32 data; |
1da177e4 | 12637 | |
b9fc7dc5 | 12638 | data = *((__be32 *) (tmp + j)); |
a9dc529d | 12639 | |
b9fc7dc5 | 12640 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 LT |
12641 | |
12642 | tw32(NVRAM_ADDR, phy_addr + j); | |
12643 | ||
12644 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
12645 | NVRAM_CMD_WR; | |
12646 | ||
12647 | if (j == 0) | |
12648 | nvram_cmd |= NVRAM_CMD_FIRST; | |
12649 | else if (j == (pagesize - 4)) | |
12650 | nvram_cmd |= NVRAM_CMD_LAST; | |
12651 | ||
12652 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12653 | break; | |
12654 | } | |
12655 | if (ret) | |
12656 | break; | |
12657 | } | |
12658 | ||
12659 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12660 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
12661 | ||
12662 | kfree(tmp); | |
12663 | ||
12664 | return ret; | |
12665 | } | |
12666 | ||
12667 | /* offset and length are dword aligned */ | |
12668 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
12669 | u8 *buf) | |
12670 | { | |
12671 | int i, ret = 0; | |
12672 | ||
12673 | for (i = 0; i < len; i += 4, offset += 4) { | |
b9fc7dc5 AV |
12674 | u32 page_off, phy_addr, nvram_cmd; |
12675 | __be32 data; | |
1da177e4 LT |
12676 | |
12677 | memcpy(&data, buf + i, 4); | |
b9fc7dc5 | 12678 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 | 12679 | |
c6cdf436 | 12680 | page_off = offset % tp->nvram_pagesize; |
1da177e4 | 12681 | |
1820180b | 12682 | phy_addr = tg3_nvram_phys_addr(tp, offset); |
1da177e4 LT |
12683 | |
12684 | tw32(NVRAM_ADDR, phy_addr); | |
12685 | ||
12686 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; | |
12687 | ||
c6cdf436 | 12688 | if (page_off == 0 || i == 0) |
1da177e4 | 12689 | nvram_cmd |= NVRAM_CMD_FIRST; |
f6d9a256 | 12690 | if (page_off == (tp->nvram_pagesize - 4)) |
1da177e4 LT |
12691 | nvram_cmd |= NVRAM_CMD_LAST; |
12692 | ||
12693 | if (i == (len - 4)) | |
12694 | nvram_cmd |= NVRAM_CMD_LAST; | |
12695 | ||
321d32a0 | 12696 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && |
63c3a66f | 12697 | !tg3_flag(tp, 5755_PLUS) && |
4c987487 MC |
12698 | (tp->nvram_jedecnum == JEDEC_ST) && |
12699 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
1da177e4 LT |
12700 | |
12701 | if ((ret = tg3_nvram_exec_cmd(tp, | |
12702 | NVRAM_CMD_WREN | NVRAM_CMD_GO | | |
12703 | NVRAM_CMD_DONE))) | |
12704 | ||
12705 | break; | |
12706 | } | |
63c3a66f | 12707 | if (!tg3_flag(tp, FLASH)) { |
1da177e4 LT |
12708 | /* We always do complete word writes to eeprom. */ |
12709 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
12710 | } | |
12711 | ||
12712 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12713 | break; | |
12714 | } | |
12715 | return ret; | |
12716 | } | |
12717 | ||
12718 | /* offset and length are dword aligned */ | |
12719 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
12720 | { | |
12721 | int ret; | |
12722 | ||
63c3a66f | 12723 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { |
314fba34 MC |
12724 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & |
12725 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
1da177e4 LT |
12726 | udelay(40); |
12727 | } | |
12728 | ||
63c3a66f | 12729 | if (!tg3_flag(tp, NVRAM)) { |
1da177e4 | 12730 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); |
859a5887 | 12731 | } else { |
1da177e4 LT |
12732 | u32 grc_mode; |
12733 | ||
ec41c7df MC |
12734 | ret = tg3_nvram_lock(tp); |
12735 | if (ret) | |
12736 | return ret; | |
1da177e4 | 12737 | |
e6af301b | 12738 | tg3_enable_nvram_access(tp); |
63c3a66f | 12739 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) |
1da177e4 | 12740 | tw32(NVRAM_WRITE1, 0x406); |
1da177e4 LT |
12741 | |
12742 | grc_mode = tr32(GRC_MODE); | |
12743 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
12744 | ||
63c3a66f | 12745 | if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { |
1da177e4 LT |
12746 | ret = tg3_nvram_write_block_buffered(tp, offset, len, |
12747 | buf); | |
859a5887 | 12748 | } else { |
1da177e4 LT |
12749 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, |
12750 | buf); | |
12751 | } | |
12752 | ||
12753 | grc_mode = tr32(GRC_MODE); | |
12754 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
12755 | ||
e6af301b | 12756 | tg3_disable_nvram_access(tp); |
1da177e4 LT |
12757 | tg3_nvram_unlock(tp); |
12758 | } | |
12759 | ||
63c3a66f | 12760 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { |
314fba34 | 12761 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
1da177e4 LT |
12762 | udelay(40); |
12763 | } | |
12764 | ||
12765 | return ret; | |
12766 | } | |
12767 | ||
12768 | struct subsys_tbl_ent { | |
12769 | u16 subsys_vendor, subsys_devid; | |
12770 | u32 phy_id; | |
12771 | }; | |
12772 | ||
24daf2b0 | 12773 | static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = { |
1da177e4 | 12774 | /* Broadcom boards. */ |
24daf2b0 | 12775 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12776 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12777 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12778 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12779 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12780 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 }, |
24daf2b0 MC |
12781 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12782 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 }, | |
12783 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12784 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12785 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12786 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12787 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12788 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 }, | |
12789 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12790 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12791 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12792 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12793 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12794 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 }, |
24daf2b0 | 12795 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12796 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 }, |
1da177e4 LT |
12797 | |
12798 | /* 3com boards. */ | |
24daf2b0 | 12799 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12800 | TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12801 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12802 | TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12803 | { TG3PCI_SUBVENDOR_ID_3COM, |
12804 | TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 }, | |
12805 | { TG3PCI_SUBVENDOR_ID_3COM, | |
79eb6904 | 12806 | TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12807 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12808 | TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12809 | |
12810 | /* DELL boards. */ | |
24daf2b0 | 12811 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12812 | TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12813 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12814 | TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12815 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12816 | TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 }, |
24daf2b0 | 12817 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12818 | TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 }, |
1da177e4 LT |
12819 | |
12820 | /* Compaq boards. */ | |
24daf2b0 | 12821 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12822 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12823 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12824 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12825 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
12826 | TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 }, | |
12827 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
79eb6904 | 12828 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12829 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12830 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12831 | |
12832 | /* IBM boards. */ | |
24daf2b0 MC |
12833 | { TG3PCI_SUBVENDOR_ID_IBM, |
12834 | TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 } | |
1da177e4 LT |
12835 | }; |
12836 | ||
24daf2b0 | 12837 | static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp) |
1da177e4 LT |
12838 | { |
12839 | int i; | |
12840 | ||
12841 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
12842 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
12843 | tp->pdev->subsystem_vendor) && | |
12844 | (subsys_id_to_phy_id[i].subsys_devid == | |
12845 | tp->pdev->subsystem_device)) | |
12846 | return &subsys_id_to_phy_id[i]; | |
12847 | } | |
12848 | return NULL; | |
12849 | } | |
12850 | ||
7d0c41ef | 12851 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) |
1da177e4 | 12852 | { |
1da177e4 | 12853 | u32 val; |
f49639e6 | 12854 | |
79eb6904 | 12855 | tp->phy_id = TG3_PHY_ID_INVALID; |
7d0c41ef MC |
12856 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
12857 | ||
a85feb8c | 12858 | /* Assume an onboard device and WOL capable by default. */ |
63c3a66f JP |
12859 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
12860 | tg3_flag_set(tp, WOL_CAP); | |
72b845e0 | 12861 | |
b5d3772c | 12862 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
9d26e213 | 12863 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
63c3a66f JP |
12864 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
12865 | tg3_flag_set(tp, IS_NIC); | |
9d26e213 | 12866 | } |
0527ba35 MC |
12867 | val = tr32(VCPU_CFGSHDW); |
12868 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
63c3a66f | 12869 | tg3_flag_set(tp, ASPM_WORKAROUND); |
0527ba35 | 12870 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && |
6fdbab9d | 12871 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) { |
63c3a66f | 12872 | tg3_flag_set(tp, WOL_ENABLE); |
6fdbab9d RW |
12873 | device_set_wakeup_enable(&tp->pdev->dev, true); |
12874 | } | |
05ac4cb7 | 12875 | goto done; |
b5d3772c MC |
12876 | } |
12877 | ||
1da177e4 LT |
12878 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
12879 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
12880 | u32 nic_cfg, led_cfg; | |
a9daf367 | 12881 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; |
7d0c41ef | 12882 | int eeprom_phy_serdes = 0; |
1da177e4 LT |
12883 | |
12884 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
12885 | tp->nic_sram_data_cfg = nic_cfg; | |
12886 | ||
12887 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
12888 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
6ff6f81d MC |
12889 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
12890 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
12891 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 && | |
1da177e4 LT |
12892 | (ver > 0) && (ver < 0x100)) |
12893 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
12894 | ||
a9daf367 MC |
12895 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
12896 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
12897 | ||
1da177e4 LT |
12898 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
12899 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
12900 | eeprom_phy_serdes = 1; | |
12901 | ||
12902 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
12903 | if (nic_phy_id != 0) { | |
12904 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
12905 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
12906 | ||
12907 | eeprom_phy_id = (id1 >> 16) << 10; | |
12908 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
12909 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
12910 | } else | |
12911 | eeprom_phy_id = 0; | |
12912 | ||
7d0c41ef | 12913 | tp->phy_id = eeprom_phy_id; |
747e8f8b | 12914 | if (eeprom_phy_serdes) { |
63c3a66f | 12915 | if (!tg3_flag(tp, 5705_PLUS)) |
f07e9af3 | 12916 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
a50d0796 | 12917 | else |
f07e9af3 | 12918 | tp->phy_flags |= TG3_PHYFLG_MII_SERDES; |
747e8f8b | 12919 | } |
7d0c41ef | 12920 | |
63c3a66f | 12921 | if (tg3_flag(tp, 5750_PLUS)) |
1da177e4 LT |
12922 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | |
12923 | SHASTA_EXT_LED_MODE_MASK); | |
cbf46853 | 12924 | else |
1da177e4 LT |
12925 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; |
12926 | ||
12927 | switch (led_cfg) { | |
12928 | default: | |
12929 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
12930 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12931 | break; | |
12932 | ||
12933 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
12934 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12935 | break; | |
12936 | ||
12937 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
12938 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
9ba27794 MC |
12939 | |
12940 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
12941 | * read on some older 5700/5701 bootcode. | |
12942 | */ | |
12943 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12944 | ASIC_REV_5700 || | |
12945 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12946 | ASIC_REV_5701) | |
12947 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12948 | ||
1da177e4 LT |
12949 | break; |
12950 | ||
12951 | case SHASTA_EXT_LED_SHARED: | |
12952 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
12953 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
12954 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
12955 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12956 | LED_CTRL_MODE_PHY_2); | |
12957 | break; | |
12958 | ||
12959 | case SHASTA_EXT_LED_MAC: | |
12960 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
12961 | break; | |
12962 | ||
12963 | case SHASTA_EXT_LED_COMBO: | |
12964 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
12965 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
12966 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12967 | LED_CTRL_MODE_PHY_2); | |
12968 | break; | |
12969 | ||
855e1111 | 12970 | } |
1da177e4 LT |
12971 | |
12972 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
12973 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
12974 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
12975 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12976 | ||
b2a5c19c MC |
12977 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) |
12978 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
5f60891b | 12979 | |
9d26e213 | 12980 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
63c3a66f | 12981 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
9d26e213 MC |
12982 | if ((tp->pdev->subsystem_vendor == |
12983 | PCI_VENDOR_ID_ARIMA) && | |
12984 | (tp->pdev->subsystem_device == 0x205a || | |
12985 | tp->pdev->subsystem_device == 0x2063)) | |
63c3a66f | 12986 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
9d26e213 | 12987 | } else { |
63c3a66f JP |
12988 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
12989 | tg3_flag_set(tp, IS_NIC); | |
9d26e213 | 12990 | } |
1da177e4 LT |
12991 | |
12992 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
63c3a66f JP |
12993 | tg3_flag_set(tp, ENABLE_ASF); |
12994 | if (tg3_flag(tp, 5750_PLUS)) | |
12995 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 | 12996 | } |
b2b98d4a MC |
12997 | |
12998 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
63c3a66f JP |
12999 | tg3_flag(tp, 5750_PLUS)) |
13000 | tg3_flag_set(tp, ENABLE_APE); | |
b2b98d4a | 13001 | |
f07e9af3 | 13002 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && |
a85feb8c | 13003 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) |
63c3a66f | 13004 | tg3_flag_clear(tp, WOL_CAP); |
1da177e4 | 13005 | |
63c3a66f | 13006 | if (tg3_flag(tp, WOL_CAP) && |
6fdbab9d | 13007 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) { |
63c3a66f | 13008 | tg3_flag_set(tp, WOL_ENABLE); |
6fdbab9d RW |
13009 | device_set_wakeup_enable(&tp->pdev->dev, true); |
13010 | } | |
0527ba35 | 13011 | |
1da177e4 | 13012 | if (cfg2 & (1 << 17)) |
f07e9af3 | 13013 | tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; |
1da177e4 LT |
13014 | |
13015 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
13016 | /* bootcode if bit 18 is set */ | |
13017 | if (cfg2 & (1 << 18)) | |
f07e9af3 | 13018 | tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; |
8ed5d97e | 13019 | |
63c3a66f JP |
13020 | if ((tg3_flag(tp, 57765_PLUS) || |
13021 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
13022 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) && | |
6833c043 | 13023 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
f07e9af3 | 13024 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; |
6833c043 | 13025 | |
63c3a66f | 13026 | if (tg3_flag(tp, PCI_EXPRESS) && |
8c69b1e7 | 13027 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
63c3a66f | 13028 | !tg3_flag(tp, 57765_PLUS)) { |
8ed5d97e MC |
13029 | u32 cfg3; |
13030 | ||
13031 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
13032 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
63c3a66f | 13033 | tg3_flag_set(tp, ASPM_WORKAROUND); |
8ed5d97e | 13034 | } |
a9daf367 | 13035 | |
14417063 | 13036 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) |
63c3a66f | 13037 | tg3_flag_set(tp, RGMII_INBAND_DISABLE); |
a9daf367 | 13038 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) |
63c3a66f | 13039 | tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); |
a9daf367 | 13040 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) |
63c3a66f | 13041 | tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); |
1da177e4 | 13042 | } |
05ac4cb7 | 13043 | done: |
63c3a66f | 13044 | if (tg3_flag(tp, WOL_CAP)) |
43067ed8 | 13045 | device_set_wakeup_enable(&tp->pdev->dev, |
63c3a66f | 13046 | tg3_flag(tp, WOL_ENABLE)); |
43067ed8 RW |
13047 | else |
13048 | device_set_wakeup_capable(&tp->pdev->dev, false); | |
7d0c41ef MC |
13049 | } |
13050 | ||
b2a5c19c MC |
13051 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) |
13052 | { | |
13053 | int i; | |
13054 | u32 val; | |
13055 | ||
13056 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
13057 | tw32(OTP_CTRL, cmd); | |
13058 | ||
13059 | /* Wait for up to 1 ms for command to execute. */ | |
13060 | for (i = 0; i < 100; i++) { | |
13061 | val = tr32(OTP_STATUS); | |
13062 | if (val & OTP_STATUS_CMD_DONE) | |
13063 | break; | |
13064 | udelay(10); | |
13065 | } | |
13066 | ||
13067 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
13068 | } | |
13069 | ||
13070 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
13071 | * configuration is a 32-bit value that straddles the alignment boundary. | |
13072 | * We do two 32-bit reads and then shift and merge the results. | |
13073 | */ | |
13074 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
13075 | { | |
13076 | u32 bhalf_otp, thalf_otp; | |
13077 | ||
13078 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
13079 | ||
13080 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
13081 | return 0; | |
13082 | ||
13083 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
13084 | ||
13085 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
13086 | return 0; | |
13087 | ||
13088 | thalf_otp = tr32(OTP_READ_DATA); | |
13089 | ||
13090 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
13091 | ||
13092 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
13093 | return 0; | |
13094 | ||
13095 | bhalf_otp = tr32(OTP_READ_DATA); | |
13096 | ||
13097 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
13098 | } | |
13099 | ||
e256f8a3 MC |
13100 | static void __devinit tg3_phy_init_link_config(struct tg3 *tp) |
13101 | { | |
13102 | u32 adv = ADVERTISED_Autoneg | | |
13103 | ADVERTISED_Pause; | |
13104 | ||
13105 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) | |
13106 | adv |= ADVERTISED_1000baseT_Half | | |
13107 | ADVERTISED_1000baseT_Full; | |
13108 | ||
13109 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
13110 | adv |= ADVERTISED_100baseT_Half | | |
13111 | ADVERTISED_100baseT_Full | | |
13112 | ADVERTISED_10baseT_Half | | |
13113 | ADVERTISED_10baseT_Full | | |
13114 | ADVERTISED_TP; | |
13115 | else | |
13116 | adv |= ADVERTISED_FIBRE; | |
13117 | ||
13118 | tp->link_config.advertising = adv; | |
13119 | tp->link_config.speed = SPEED_INVALID; | |
13120 | tp->link_config.duplex = DUPLEX_INVALID; | |
13121 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
13122 | tp->link_config.active_speed = SPEED_INVALID; | |
13123 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
13124 | tp->link_config.orig_speed = SPEED_INVALID; | |
13125 | tp->link_config.orig_duplex = DUPLEX_INVALID; | |
13126 | tp->link_config.orig_autoneg = AUTONEG_INVALID; | |
13127 | } | |
13128 | ||
7d0c41ef MC |
13129 | static int __devinit tg3_phy_probe(struct tg3 *tp) |
13130 | { | |
13131 | u32 hw_phy_id_1, hw_phy_id_2; | |
13132 | u32 hw_phy_id, hw_phy_id_masked; | |
13133 | int err; | |
1da177e4 | 13134 | |
e256f8a3 | 13135 | /* flow control autonegotiation is default behavior */ |
63c3a66f | 13136 | tg3_flag_set(tp, PAUSE_AUTONEG); |
e256f8a3 MC |
13137 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; |
13138 | ||
63c3a66f | 13139 | if (tg3_flag(tp, USE_PHYLIB)) |
b02fd9e3 MC |
13140 | return tg3_phy_init(tp); |
13141 | ||
1da177e4 | 13142 | /* Reading the PHY ID register can conflict with ASF |
877d0310 | 13143 | * firmware access to the PHY hardware. |
1da177e4 LT |
13144 | */ |
13145 | err = 0; | |
63c3a66f | 13146 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { |
79eb6904 | 13147 | hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID; |
1da177e4 LT |
13148 | } else { |
13149 | /* Now read the physical PHY_ID from the chip and verify | |
13150 | * that it is sane. If it doesn't look good, we fall back | |
13151 | * to either the hard-coded table based PHY_ID and failing | |
13152 | * that the value found in the eeprom area. | |
13153 | */ | |
13154 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
13155 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
13156 | ||
13157 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
13158 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
13159 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
13160 | ||
79eb6904 | 13161 | hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK; |
1da177e4 LT |
13162 | } |
13163 | ||
79eb6904 | 13164 | if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) { |
1da177e4 | 13165 | tp->phy_id = hw_phy_id; |
79eb6904 | 13166 | if (hw_phy_id_masked == TG3_PHY_ID_BCM8002) |
f07e9af3 | 13167 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
da6b2d01 | 13168 | else |
f07e9af3 | 13169 | tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; |
1da177e4 | 13170 | } else { |
79eb6904 | 13171 | if (tp->phy_id != TG3_PHY_ID_INVALID) { |
7d0c41ef MC |
13172 | /* Do nothing, phy ID already set up in |
13173 | * tg3_get_eeprom_hw_cfg(). | |
13174 | */ | |
1da177e4 LT |
13175 | } else { |
13176 | struct subsys_tbl_ent *p; | |
13177 | ||
13178 | /* No eeprom signature? Try the hardcoded | |
13179 | * subsys device table. | |
13180 | */ | |
24daf2b0 | 13181 | p = tg3_lookup_by_subsys(tp); |
1da177e4 LT |
13182 | if (!p) |
13183 | return -ENODEV; | |
13184 | ||
13185 | tp->phy_id = p->phy_id; | |
13186 | if (!tp->phy_id || | |
79eb6904 | 13187 | tp->phy_id == TG3_PHY_ID_BCM8002) |
f07e9af3 | 13188 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
1da177e4 LT |
13189 | } |
13190 | } | |
13191 | ||
a6b68dab | 13192 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
5baa5e9a MC |
13193 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13194 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || | |
13195 | (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 && | |
a6b68dab MC |
13196 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) || |
13197 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
13198 | tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))) | |
52b02d04 MC |
13199 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; |
13200 | ||
e256f8a3 MC |
13201 | tg3_phy_init_link_config(tp); |
13202 | ||
f07e9af3 | 13203 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
63c3a66f JP |
13204 | !tg3_flag(tp, ENABLE_APE) && |
13205 | !tg3_flag(tp, ENABLE_ASF)) { | |
42b64a45 | 13206 | u32 bmsr, mask; |
1da177e4 LT |
13207 | |
13208 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
13209 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
13210 | (bmsr & BMSR_LSTATUS)) | |
13211 | goto skip_phy_reset; | |
6aa20a22 | 13212 | |
1da177e4 LT |
13213 | err = tg3_phy_reset(tp); |
13214 | if (err) | |
13215 | return err; | |
13216 | ||
42b64a45 | 13217 | tg3_phy_set_wirespeed(tp); |
1da177e4 | 13218 | |
3600d918 MC |
13219 | mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
13220 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
13221 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); | |
13222 | if (!tg3_copper_is_advertising_all(tp, mask)) { | |
42b64a45 MC |
13223 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, |
13224 | tp->link_config.flowctrl); | |
1da177e4 LT |
13225 | |
13226 | tg3_writephy(tp, MII_BMCR, | |
13227 | BMCR_ANENABLE | BMCR_ANRESTART); | |
13228 | } | |
1da177e4 LT |
13229 | } |
13230 | ||
13231 | skip_phy_reset: | |
79eb6904 | 13232 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
13233 | err = tg3_init_5401phy_dsp(tp); |
13234 | if (err) | |
13235 | return err; | |
1da177e4 | 13236 | |
1da177e4 LT |
13237 | err = tg3_init_5401phy_dsp(tp); |
13238 | } | |
13239 | ||
1da177e4 LT |
13240 | return err; |
13241 | } | |
13242 | ||
184b8904 | 13243 | static void __devinit tg3_read_vpd(struct tg3 *tp) |
1da177e4 | 13244 | { |
a4a8bb15 | 13245 | u8 *vpd_data; |
4181b2c8 | 13246 | unsigned int block_end, rosize, len; |
535a490e | 13247 | u32 vpdlen; |
184b8904 | 13248 | int j, i = 0; |
a4a8bb15 | 13249 | |
535a490e | 13250 | vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen); |
a4a8bb15 MC |
13251 | if (!vpd_data) |
13252 | goto out_no_vpd; | |
1da177e4 | 13253 | |
535a490e | 13254 | i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA); |
4181b2c8 MC |
13255 | if (i < 0) |
13256 | goto out_not_found; | |
1da177e4 | 13257 | |
4181b2c8 MC |
13258 | rosize = pci_vpd_lrdt_size(&vpd_data[i]); |
13259 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize; | |
13260 | i += PCI_VPD_LRDT_TAG_SIZE; | |
1da177e4 | 13261 | |
535a490e | 13262 | if (block_end > vpdlen) |
4181b2c8 | 13263 | goto out_not_found; |
af2c6a4a | 13264 | |
184b8904 MC |
13265 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
13266 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
13267 | if (j > 0) { | |
13268 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13269 | ||
13270 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13271 | if (j + len > block_end || len != 4 || | |
13272 | memcmp(&vpd_data[j], "1028", 4)) | |
13273 | goto partno; | |
13274 | ||
13275 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, | |
13276 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
13277 | if (j < 0) | |
13278 | goto partno; | |
13279 | ||
13280 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13281 | ||
13282 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13283 | if (j + len > block_end) | |
13284 | goto partno; | |
13285 | ||
13286 | memcpy(tp->fw_ver, &vpd_data[j], len); | |
535a490e | 13287 | strncat(tp->fw_ver, " bc ", vpdlen - len - 1); |
184b8904 MC |
13288 | } |
13289 | ||
13290 | partno: | |
4181b2c8 MC |
13291 | i = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
13292 | PCI_VPD_RO_KEYWORD_PARTNO); | |
13293 | if (i < 0) | |
13294 | goto out_not_found; | |
af2c6a4a | 13295 | |
4181b2c8 | 13296 | len = pci_vpd_info_field_size(&vpd_data[i]); |
1da177e4 | 13297 | |
4181b2c8 MC |
13298 | i += PCI_VPD_INFO_FLD_HDR_SIZE; |
13299 | if (len > TG3_BPN_SIZE || | |
535a490e | 13300 | (len + i) > vpdlen) |
4181b2c8 | 13301 | goto out_not_found; |
1da177e4 | 13302 | |
4181b2c8 | 13303 | memcpy(tp->board_part_number, &vpd_data[i], len); |
1da177e4 | 13304 | |
1da177e4 | 13305 | out_not_found: |
a4a8bb15 | 13306 | kfree(vpd_data); |
37a949c5 | 13307 | if (tp->board_part_number[0]) |
a4a8bb15 MC |
13308 | return; |
13309 | ||
13310 | out_no_vpd: | |
37a949c5 MC |
13311 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
13312 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717) | |
13313 | strcpy(tp->board_part_number, "BCM5717"); | |
13314 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) | |
13315 | strcpy(tp->board_part_number, "BCM5718"); | |
13316 | else | |
13317 | goto nomatch; | |
13318 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
13319 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
13320 | strcpy(tp->board_part_number, "BCM57780"); | |
13321 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
13322 | strcpy(tp->board_part_number, "BCM57760"); | |
13323 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
13324 | strcpy(tp->board_part_number, "BCM57790"); | |
13325 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
13326 | strcpy(tp->board_part_number, "BCM57788"); | |
13327 | else | |
13328 | goto nomatch; | |
13329 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
13330 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) | |
13331 | strcpy(tp->board_part_number, "BCM57761"); | |
13332 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) | |
13333 | strcpy(tp->board_part_number, "BCM57765"); | |
13334 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) | |
13335 | strcpy(tp->board_part_number, "BCM57781"); | |
13336 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) | |
13337 | strcpy(tp->board_part_number, "BCM57785"); | |
13338 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) | |
13339 | strcpy(tp->board_part_number, "BCM57791"); | |
13340 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13341 | strcpy(tp->board_part_number, "BCM57795"); | |
13342 | else | |
13343 | goto nomatch; | |
13344 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
b5d3772c | 13345 | strcpy(tp->board_part_number, "BCM95906"); |
37a949c5 MC |
13346 | } else { |
13347 | nomatch: | |
b5d3772c | 13348 | strcpy(tp->board_part_number, "none"); |
37a949c5 | 13349 | } |
1da177e4 LT |
13350 | } |
13351 | ||
9c8a620e MC |
13352 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) |
13353 | { | |
13354 | u32 val; | |
13355 | ||
e4f34110 | 13356 | if (tg3_nvram_read(tp, offset, &val) || |
9c8a620e | 13357 | (val & 0xfc000000) != 0x0c000000 || |
e4f34110 | 13358 | tg3_nvram_read(tp, offset + 4, &val) || |
9c8a620e MC |
13359 | val != 0) |
13360 | return 0; | |
13361 | ||
13362 | return 1; | |
13363 | } | |
13364 | ||
acd9c119 MC |
13365 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) |
13366 | { | |
ff3a7cb2 | 13367 | u32 val, offset, start, ver_offset; |
75f9936e | 13368 | int i, dst_off; |
ff3a7cb2 | 13369 | bool newver = false; |
acd9c119 MC |
13370 | |
13371 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
13372 | tg3_nvram_read(tp, 0x4, &start)) | |
13373 | return; | |
13374 | ||
13375 | offset = tg3_nvram_logical_addr(tp, offset); | |
13376 | ||
ff3a7cb2 | 13377 | if (tg3_nvram_read(tp, offset, &val)) |
acd9c119 MC |
13378 | return; |
13379 | ||
ff3a7cb2 MC |
13380 | if ((val & 0xfc000000) == 0x0c000000) { |
13381 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
acd9c119 MC |
13382 | return; |
13383 | ||
ff3a7cb2 MC |
13384 | if (val == 0) |
13385 | newver = true; | |
13386 | } | |
13387 | ||
75f9936e MC |
13388 | dst_off = strlen(tp->fw_ver); |
13389 | ||
ff3a7cb2 | 13390 | if (newver) { |
75f9936e MC |
13391 | if (TG3_VER_SIZE - dst_off < 16 || |
13392 | tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
ff3a7cb2 MC |
13393 | return; |
13394 | ||
13395 | offset = offset + ver_offset - start; | |
13396 | for (i = 0; i < 16; i += 4) { | |
13397 | __be32 v; | |
13398 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
13399 | return; | |
13400 | ||
75f9936e | 13401 | memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); |
ff3a7cb2 MC |
13402 | } |
13403 | } else { | |
13404 | u32 major, minor; | |
13405 | ||
13406 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
13407 | return; | |
13408 | ||
13409 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
13410 | TG3_NVM_BCVER_MAJSFT; | |
13411 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
75f9936e MC |
13412 | snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, |
13413 | "v%d.%02d", major, minor); | |
acd9c119 MC |
13414 | } |
13415 | } | |
13416 | ||
a6f6cb1c MC |
13417 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) |
13418 | { | |
13419 | u32 val, major, minor; | |
13420 | ||
13421 | /* Use native endian representation */ | |
13422 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
13423 | return; | |
13424 | ||
13425 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
13426 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
13427 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
13428 | TG3_NVM_HWSB_CFG1_MINSFT; | |
13429 | ||
13430 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
13431 | } | |
13432 | ||
dfe00d7d MC |
13433 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) |
13434 | { | |
13435 | u32 offset, major, minor, build; | |
13436 | ||
75f9936e | 13437 | strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); |
dfe00d7d MC |
13438 | |
13439 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
13440 | return; | |
13441 | ||
13442 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
13443 | case TG3_EEPROM_SB_REVISION_0: | |
13444 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
13445 | break; | |
13446 | case TG3_EEPROM_SB_REVISION_2: | |
13447 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
13448 | break; | |
13449 | case TG3_EEPROM_SB_REVISION_3: | |
13450 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
13451 | break; | |
a4153d40 MC |
13452 | case TG3_EEPROM_SB_REVISION_4: |
13453 | offset = TG3_EEPROM_SB_F1R4_EDH_OFF; | |
13454 | break; | |
13455 | case TG3_EEPROM_SB_REVISION_5: | |
13456 | offset = TG3_EEPROM_SB_F1R5_EDH_OFF; | |
13457 | break; | |
bba226ac MC |
13458 | case TG3_EEPROM_SB_REVISION_6: |
13459 | offset = TG3_EEPROM_SB_F1R6_EDH_OFF; | |
13460 | break; | |
dfe00d7d MC |
13461 | default: |
13462 | return; | |
13463 | } | |
13464 | ||
e4f34110 | 13465 | if (tg3_nvram_read(tp, offset, &val)) |
dfe00d7d MC |
13466 | return; |
13467 | ||
13468 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
13469 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
13470 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
13471 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
13472 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
13473 | ||
13474 | if (minor > 99 || build > 26) | |
13475 | return; | |
13476 | ||
75f9936e MC |
13477 | offset = strlen(tp->fw_ver); |
13478 | snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, | |
13479 | " v%d.%02d", major, minor); | |
dfe00d7d MC |
13480 | |
13481 | if (build > 0) { | |
75f9936e MC |
13482 | offset = strlen(tp->fw_ver); |
13483 | if (offset < TG3_VER_SIZE - 1) | |
13484 | tp->fw_ver[offset] = 'a' + build - 1; | |
dfe00d7d MC |
13485 | } |
13486 | } | |
13487 | ||
acd9c119 | 13488 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) |
c4e6575c MC |
13489 | { |
13490 | u32 val, offset, start; | |
acd9c119 | 13491 | int i, vlen; |
9c8a620e MC |
13492 | |
13493 | for (offset = TG3_NVM_DIR_START; | |
13494 | offset < TG3_NVM_DIR_END; | |
13495 | offset += TG3_NVM_DIRENT_SIZE) { | |
e4f34110 | 13496 | if (tg3_nvram_read(tp, offset, &val)) |
c4e6575c MC |
13497 | return; |
13498 | ||
9c8a620e MC |
13499 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
13500 | break; | |
13501 | } | |
13502 | ||
13503 | if (offset == TG3_NVM_DIR_END) | |
13504 | return; | |
13505 | ||
63c3a66f | 13506 | if (!tg3_flag(tp, 5705_PLUS)) |
9c8a620e | 13507 | start = 0x08000000; |
e4f34110 | 13508 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
9c8a620e MC |
13509 | return; |
13510 | ||
e4f34110 | 13511 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
9c8a620e | 13512 | !tg3_fw_img_is_valid(tp, offset) || |
e4f34110 | 13513 | tg3_nvram_read(tp, offset + 8, &val)) |
9c8a620e MC |
13514 | return; |
13515 | ||
13516 | offset += val - start; | |
13517 | ||
acd9c119 | 13518 | vlen = strlen(tp->fw_ver); |
9c8a620e | 13519 | |
acd9c119 MC |
13520 | tp->fw_ver[vlen++] = ','; |
13521 | tp->fw_ver[vlen++] = ' '; | |
9c8a620e MC |
13522 | |
13523 | for (i = 0; i < 4; i++) { | |
a9dc529d MC |
13524 | __be32 v; |
13525 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
c4e6575c MC |
13526 | return; |
13527 | ||
b9fc7dc5 | 13528 | offset += sizeof(v); |
c4e6575c | 13529 | |
acd9c119 MC |
13530 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
13531 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
9c8a620e | 13532 | break; |
c4e6575c | 13533 | } |
9c8a620e | 13534 | |
acd9c119 MC |
13535 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
13536 | vlen += sizeof(v); | |
c4e6575c | 13537 | } |
acd9c119 MC |
13538 | } |
13539 | ||
7fd76445 MC |
13540 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) |
13541 | { | |
13542 | int vlen; | |
13543 | u32 apedata; | |
ecc79648 | 13544 | char *fwtype; |
7fd76445 | 13545 | |
63c3a66f | 13546 | if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF)) |
7fd76445 MC |
13547 | return; |
13548 | ||
13549 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
13550 | if (apedata != APE_SEG_SIG_MAGIC) | |
13551 | return; | |
13552 | ||
13553 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
13554 | if (!(apedata & APE_FW_STATUS_READY)) | |
13555 | return; | |
13556 | ||
13557 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); | |
13558 | ||
dc6d0744 | 13559 | if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) { |
63c3a66f | 13560 | tg3_flag_set(tp, APE_HAS_NCSI); |
ecc79648 | 13561 | fwtype = "NCSI"; |
dc6d0744 | 13562 | } else { |
ecc79648 | 13563 | fwtype = "DASH"; |
dc6d0744 | 13564 | } |
ecc79648 | 13565 | |
7fd76445 MC |
13566 | vlen = strlen(tp->fw_ver); |
13567 | ||
ecc79648 MC |
13568 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", |
13569 | fwtype, | |
7fd76445 MC |
13570 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, |
13571 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
13572 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
13573 | (apedata & APE_FW_VERSION_BLDMSK)); | |
13574 | } | |
13575 | ||
acd9c119 MC |
13576 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) |
13577 | { | |
13578 | u32 val; | |
75f9936e | 13579 | bool vpd_vers = false; |
acd9c119 | 13580 | |
75f9936e MC |
13581 | if (tp->fw_ver[0] != 0) |
13582 | vpd_vers = true; | |
df259d8c | 13583 | |
63c3a66f | 13584 | if (tg3_flag(tp, NO_NVRAM)) { |
75f9936e | 13585 | strcat(tp->fw_ver, "sb"); |
df259d8c MC |
13586 | return; |
13587 | } | |
13588 | ||
acd9c119 MC |
13589 | if (tg3_nvram_read(tp, 0, &val)) |
13590 | return; | |
13591 | ||
13592 | if (val == TG3_EEPROM_MAGIC) | |
13593 | tg3_read_bc_ver(tp); | |
13594 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
13595 | tg3_read_sb_ver(tp, val); | |
a6f6cb1c MC |
13596 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
13597 | tg3_read_hwsb_ver(tp); | |
acd9c119 MC |
13598 | else |
13599 | return; | |
13600 | ||
c9cab24e | 13601 | if (vpd_vers) |
75f9936e | 13602 | goto done; |
acd9c119 | 13603 | |
c9cab24e MC |
13604 | if (tg3_flag(tp, ENABLE_APE)) { |
13605 | if (tg3_flag(tp, ENABLE_ASF)) | |
13606 | tg3_read_dash_ver(tp); | |
13607 | } else if (tg3_flag(tp, ENABLE_ASF)) { | |
13608 | tg3_read_mgmtfw_ver(tp); | |
13609 | } | |
9c8a620e | 13610 | |
75f9936e | 13611 | done: |
9c8a620e | 13612 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; |
c4e6575c MC |
13613 | } |
13614 | ||
7544b097 MC |
13615 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *); |
13616 | ||
7cb32cf2 MC |
13617 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) |
13618 | { | |
63c3a66f | 13619 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
de9f5230 | 13620 | return TG3_RX_RET_MAX_SIZE_5717; |
63c3a66f | 13621 | else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) |
de9f5230 | 13622 | return TG3_RX_RET_MAX_SIZE_5700; |
7cb32cf2 | 13623 | else |
de9f5230 | 13624 | return TG3_RX_RET_MAX_SIZE_5705; |
7cb32cf2 MC |
13625 | } |
13626 | ||
4143470c | 13627 | static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = { |
895950c2 JP |
13628 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) }, |
13629 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
13630 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) }, | |
13631 | { }, | |
13632 | }; | |
13633 | ||
1da177e4 LT |
13634 | static int __devinit tg3_get_invariants(struct tg3 *tp) |
13635 | { | |
1da177e4 | 13636 | u32 misc_ctrl_reg; |
1da177e4 LT |
13637 | u32 pci_state_reg, grc_misc_cfg; |
13638 | u32 val; | |
13639 | u16 pci_cmd; | |
5e7dfd0f | 13640 | int err; |
1da177e4 | 13641 | |
1da177e4 LT |
13642 | /* Force memory write invalidate off. If we leave it on, |
13643 | * then on 5700_BX chips we have to enable a workaround. | |
13644 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
13645 | * to match the cacheline size. The Broadcom driver have this | |
13646 | * workaround but turns MWI off all the times so never uses | |
13647 | * it. This seems to suggest that the workaround is insufficient. | |
13648 | */ | |
13649 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13650 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
13651 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13652 | ||
16821285 MC |
13653 | /* Important! -- Make sure register accesses are byteswapped |
13654 | * correctly. Also, for those chips that require it, make | |
13655 | * sure that indirect register accesses are enabled before | |
13656 | * the first operation. | |
1da177e4 LT |
13657 | */ |
13658 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13659 | &misc_ctrl_reg); | |
16821285 MC |
13660 | tp->misc_host_ctrl |= (misc_ctrl_reg & |
13661 | MISC_HOST_CTRL_CHIPREV); | |
13662 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13663 | tp->misc_host_ctrl); | |
1da177e4 LT |
13664 | |
13665 | tp->pci_chip_rev_id = (misc_ctrl_reg >> | |
13666 | MISC_HOST_CTRL_CHIPREV_SHIFT); | |
795d01c5 MC |
13667 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { |
13668 | u32 prod_id_asic_rev; | |
13669 | ||
5001e2f6 MC |
13670 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || |
13671 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
d78b59f5 MC |
13672 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || |
13673 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) | |
f6eb9b1f MC |
13674 | pci_read_config_dword(tp->pdev, |
13675 | TG3PCI_GEN2_PRODID_ASICREV, | |
13676 | &prod_id_asic_rev); | |
b703df6f MC |
13677 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || |
13678 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || | |
13679 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || | |
13680 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || | |
13681 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || | |
13682 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13683 | pci_read_config_dword(tp->pdev, | |
13684 | TG3PCI_GEN15_PRODID_ASICREV, | |
13685 | &prod_id_asic_rev); | |
f6eb9b1f MC |
13686 | else |
13687 | pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, | |
13688 | &prod_id_asic_rev); | |
13689 | ||
321d32a0 | 13690 | tp->pci_chip_rev_id = prod_id_asic_rev; |
795d01c5 | 13691 | } |
1da177e4 | 13692 | |
ff645bec MC |
13693 | /* Wrong chip ID in 5752 A0. This code can be removed later |
13694 | * as A0 is not in production. | |
13695 | */ | |
13696 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
13697 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
13698 | ||
6892914f MC |
13699 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, |
13700 | * we need to disable memory and use config. cycles | |
13701 | * only to access all registers. The 5702/03 chips | |
13702 | * can mistakenly decode the special cycles from the | |
13703 | * ICH chipsets as memory write cycles, causing corruption | |
13704 | * of register and memory space. Only certain ICH bridges | |
13705 | * will drive special cycles with non-zero data during the | |
13706 | * address phase which can fall within the 5703's address | |
13707 | * range. This is not an ICH bug as the PCI spec allows | |
13708 | * non-zero address during special cycles. However, only | |
13709 | * these ICH bridges are known to drive non-zero addresses | |
13710 | * during special cycles. | |
13711 | * | |
13712 | * Since special cycles do not cross PCI bridges, we only | |
13713 | * enable this workaround if the 5703 is on the secondary | |
13714 | * bus of these ICH bridges. | |
13715 | */ | |
13716 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
13717 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
13718 | static struct tg3_dev_id { | |
13719 | u32 vendor; | |
13720 | u32 device; | |
13721 | u32 rev; | |
13722 | } ich_chipsets[] = { | |
13723 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
13724 | PCI_ANY_ID }, | |
13725 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
13726 | PCI_ANY_ID }, | |
13727 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
13728 | 0xa }, | |
13729 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
13730 | PCI_ANY_ID }, | |
13731 | { }, | |
13732 | }; | |
13733 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
13734 | struct pci_dev *bridge = NULL; | |
13735 | ||
13736 | while (pci_id->vendor != 0) { | |
13737 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
13738 | bridge); | |
13739 | if (!bridge) { | |
13740 | pci_id++; | |
13741 | continue; | |
13742 | } | |
13743 | if (pci_id->rev != PCI_ANY_ID) { | |
44c10138 | 13744 | if (bridge->revision > pci_id->rev) |
6892914f MC |
13745 | continue; |
13746 | } | |
13747 | if (bridge->subordinate && | |
13748 | (bridge->subordinate->number == | |
13749 | tp->pdev->bus->number)) { | |
63c3a66f | 13750 | tg3_flag_set(tp, ICH_WORKAROUND); |
6892914f MC |
13751 | pci_dev_put(bridge); |
13752 | break; | |
13753 | } | |
13754 | } | |
13755 | } | |
13756 | ||
6ff6f81d | 13757 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { |
41588ba1 MC |
13758 | static struct tg3_dev_id { |
13759 | u32 vendor; | |
13760 | u32 device; | |
13761 | } bridge_chipsets[] = { | |
13762 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
13763 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
13764 | { }, | |
13765 | }; | |
13766 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
13767 | struct pci_dev *bridge = NULL; | |
13768 | ||
13769 | while (pci_id->vendor != 0) { | |
13770 | bridge = pci_get_device(pci_id->vendor, | |
13771 | pci_id->device, | |
13772 | bridge); | |
13773 | if (!bridge) { | |
13774 | pci_id++; | |
13775 | continue; | |
13776 | } | |
13777 | if (bridge->subordinate && | |
13778 | (bridge->subordinate->number <= | |
13779 | tp->pdev->bus->number) && | |
13780 | (bridge->subordinate->subordinate >= | |
13781 | tp->pdev->bus->number)) { | |
63c3a66f | 13782 | tg3_flag_set(tp, 5701_DMA_BUG); |
41588ba1 MC |
13783 | pci_dev_put(bridge); |
13784 | break; | |
13785 | } | |
13786 | } | |
13787 | } | |
13788 | ||
4a29cc2e MC |
13789 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support |
13790 | * DMA addresses > 40-bit. This bridge may have other additional | |
13791 | * 57xx devices behind it in some 4-port NIC designs for example. | |
13792 | * Any tg3 device found behind the bridge will also need the 40-bit | |
13793 | * DMA workaround. | |
13794 | */ | |
a4e2b347 MC |
13795 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
13796 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
63c3a66f JP |
13797 | tg3_flag_set(tp, 5780_CLASS); |
13798 | tg3_flag_set(tp, 40BIT_DMA_BUG); | |
4cf78e4f | 13799 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); |
859a5887 | 13800 | } else { |
4a29cc2e MC |
13801 | struct pci_dev *bridge = NULL; |
13802 | ||
13803 | do { | |
13804 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
13805 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
13806 | bridge); | |
13807 | if (bridge && bridge->subordinate && | |
13808 | (bridge->subordinate->number <= | |
13809 | tp->pdev->bus->number) && | |
13810 | (bridge->subordinate->subordinate >= | |
13811 | tp->pdev->bus->number)) { | |
63c3a66f | 13812 | tg3_flag_set(tp, 40BIT_DMA_BUG); |
4a29cc2e MC |
13813 | pci_dev_put(bridge); |
13814 | break; | |
13815 | } | |
13816 | } while (bridge); | |
13817 | } | |
4cf78e4f | 13818 | |
f6eb9b1f | 13819 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
3a1e19d3 | 13820 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) |
7544b097 MC |
13821 | tp->pdev_peer = tg3_find_peer(tp); |
13822 | ||
c885e824 | 13823 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
d78b59f5 MC |
13824 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13825 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
63c3a66f | 13826 | tg3_flag_set(tp, 5717_PLUS); |
0a58d668 MC |
13827 | |
13828 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || | |
63c3a66f JP |
13829 | tg3_flag(tp, 5717_PLUS)) |
13830 | tg3_flag_set(tp, 57765_PLUS); | |
c885e824 | 13831 | |
321d32a0 MC |
13832 | /* Intentionally exclude ASIC_REV_5906 */ |
13833 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
d9ab5ad1 | 13834 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
d30cdd28 | 13835 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
9936bcf6 | 13836 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c | 13837 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 13838 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
63c3a66f JP |
13839 | tg3_flag(tp, 57765_PLUS)) |
13840 | tg3_flag_set(tp, 5755_PLUS); | |
321d32a0 MC |
13841 | |
13842 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
13843 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
b5d3772c | 13844 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || |
63c3a66f JP |
13845 | tg3_flag(tp, 5755_PLUS) || |
13846 | tg3_flag(tp, 5780_CLASS)) | |
13847 | tg3_flag_set(tp, 5750_PLUS); | |
6708e5cc | 13848 | |
6ff6f81d | 13849 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
63c3a66f JP |
13850 | tg3_flag(tp, 5750_PLUS)) |
13851 | tg3_flag_set(tp, 5705_PLUS); | |
1b440c56 | 13852 | |
507399f1 | 13853 | /* Determine TSO capabilities */ |
a0512944 | 13854 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) |
4d163b75 | 13855 | ; /* Do nothing. HW bug. */ |
63c3a66f JP |
13856 | else if (tg3_flag(tp, 57765_PLUS)) |
13857 | tg3_flag_set(tp, HW_TSO_3); | |
13858 | else if (tg3_flag(tp, 5755_PLUS) || | |
e849cdc3 | 13859 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
63c3a66f JP |
13860 | tg3_flag_set(tp, HW_TSO_2); |
13861 | else if (tg3_flag(tp, 5750_PLUS)) { | |
13862 | tg3_flag_set(tp, HW_TSO_1); | |
13863 | tg3_flag_set(tp, TSO_BUG); | |
507399f1 MC |
13864 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && |
13865 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
63c3a66f | 13866 | tg3_flag_clear(tp, TSO_BUG); |
507399f1 MC |
13867 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
13868 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13869 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 13870 | tg3_flag_set(tp, TSO_BUG); |
507399f1 MC |
13871 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) |
13872 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
13873 | else | |
13874 | tp->fw_needed = FIRMWARE_TG3TSO; | |
13875 | } | |
13876 | ||
dabc5c67 | 13877 | /* Selectively allow TSO based on operating conditions */ |
6ff6f81d MC |
13878 | if (tg3_flag(tp, HW_TSO_1) || |
13879 | tg3_flag(tp, HW_TSO_2) || | |
13880 | tg3_flag(tp, HW_TSO_3) || | |
dabc5c67 MC |
13881 | (tp->fw_needed && !tg3_flag(tp, ENABLE_ASF))) |
13882 | tg3_flag_set(tp, TSO_CAPABLE); | |
13883 | else { | |
13884 | tg3_flag_clear(tp, TSO_CAPABLE); | |
13885 | tg3_flag_clear(tp, TSO_BUG); | |
13886 | tp->fw_needed = NULL; | |
13887 | } | |
13888 | ||
13889 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
13890 | tp->fw_needed = FIRMWARE_TG3; | |
13891 | ||
507399f1 MC |
13892 | tp->irq_max = 1; |
13893 | ||
63c3a66f JP |
13894 | if (tg3_flag(tp, 5750_PLUS)) { |
13895 | tg3_flag_set(tp, SUPPORT_MSI); | |
7544b097 MC |
13896 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || |
13897 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
13898 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
13899 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
13900 | tp->pdev_peer == tp->pdev)) | |
63c3a66f | 13901 | tg3_flag_clear(tp, SUPPORT_MSI); |
7544b097 | 13902 | |
63c3a66f | 13903 | if (tg3_flag(tp, 5755_PLUS) || |
b5d3772c | 13904 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
63c3a66f | 13905 | tg3_flag_set(tp, 1SHOT_MSI); |
52c0fd83 | 13906 | } |
4f125f42 | 13907 | |
63c3a66f JP |
13908 | if (tg3_flag(tp, 57765_PLUS)) { |
13909 | tg3_flag_set(tp, SUPPORT_MSIX); | |
507399f1 MC |
13910 | tp->irq_max = TG3_IRQ_MAX_VECS; |
13911 | } | |
f6eb9b1f | 13912 | } |
0e1406dd | 13913 | |
2ffcc981 | 13914 | if (tg3_flag(tp, 5755_PLUS)) |
63c3a66f | 13915 | tg3_flag_set(tp, SHORT_DMA_BUG); |
f6eb9b1f | 13916 | |
e31aa987 MC |
13917 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
13918 | tg3_flag_set(tp, 4K_FIFO_LIMIT); | |
13919 | ||
63c3a66f JP |
13920 | if (tg3_flag(tp, 5717_PLUS)) |
13921 | tg3_flag_set(tp, LRG_PROD_RING_CAP); | |
de9f5230 | 13922 | |
63c3a66f | 13923 | if (tg3_flag(tp, 57765_PLUS) && |
a0512944 | 13924 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0) |
63c3a66f | 13925 | tg3_flag_set(tp, USE_JUMBO_BDFLAG); |
b703df6f | 13926 | |
63c3a66f JP |
13927 | if (!tg3_flag(tp, 5705_PLUS) || |
13928 | tg3_flag(tp, 5780_CLASS) || | |
13929 | tg3_flag(tp, USE_JUMBO_BDFLAG)) | |
13930 | tg3_flag_set(tp, JUMBO_CAPABLE); | |
0f893dc6 | 13931 | |
52f4490c MC |
13932 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
13933 | &pci_state_reg); | |
13934 | ||
708ebb3a | 13935 | if (pci_is_pcie(tp->pdev)) { |
5e7dfd0f MC |
13936 | u16 lnkctl; |
13937 | ||
63c3a66f | 13938 | tg3_flag_set(tp, PCI_EXPRESS); |
5f5c51e3 | 13939 | |
cf79003d | 13940 | tp->pcie_readrq = 4096; |
d78b59f5 MC |
13941 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13942 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
b4495ed8 | 13943 | tp->pcie_readrq = 2048; |
cf79003d MC |
13944 | |
13945 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); | |
5f5c51e3 | 13946 | |
5e7dfd0f | 13947 | pci_read_config_word(tp->pdev, |
708ebb3a | 13948 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
13949 | &lnkctl); |
13950 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | |
7196cd6c MC |
13951 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
13952 | ASIC_REV_5906) { | |
63c3a66f | 13953 | tg3_flag_clear(tp, HW_TSO_2); |
dabc5c67 | 13954 | tg3_flag_clear(tp, TSO_CAPABLE); |
7196cd6c | 13955 | } |
5e7dfd0f | 13956 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 | 13957 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9cf74ebb MC |
13958 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || |
13959 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
63c3a66f | 13960 | tg3_flag_set(tp, CLKREQ_BUG); |
614b0590 | 13961 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { |
63c3a66f | 13962 | tg3_flag_set(tp, L1PLLPD_EN); |
c7835a77 | 13963 | } |
52f4490c | 13964 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
708ebb3a JM |
13965 | /* BCM5785 devices are effectively PCIe devices, and should |
13966 | * follow PCIe codepaths, but do not have a PCIe capabilities | |
13967 | * section. | |
13968 | */ | |
63c3a66f JP |
13969 | tg3_flag_set(tp, PCI_EXPRESS); |
13970 | } else if (!tg3_flag(tp, 5705_PLUS) || | |
13971 | tg3_flag(tp, 5780_CLASS)) { | |
52f4490c MC |
13972 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); |
13973 | if (!tp->pcix_cap) { | |
2445e461 MC |
13974 | dev_err(&tp->pdev->dev, |
13975 | "Cannot find PCI-X capability, aborting\n"); | |
52f4490c MC |
13976 | return -EIO; |
13977 | } | |
13978 | ||
13979 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
63c3a66f | 13980 | tg3_flag_set(tp, PCIX_MODE); |
52f4490c | 13981 | } |
1da177e4 | 13982 | |
399de50b MC |
13983 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
13984 | * reordering to the mailbox registers done by the host | |
13985 | * controller can cause major troubles. We read back from | |
13986 | * every mailbox register write to force the writes to be | |
13987 | * posted to the chip in order. | |
13988 | */ | |
4143470c | 13989 | if (pci_dev_present(tg3_write_reorder_chipsets) && |
63c3a66f JP |
13990 | !tg3_flag(tp, PCI_EXPRESS)) |
13991 | tg3_flag_set(tp, MBOX_WRITE_REORDER); | |
399de50b | 13992 | |
69fc4053 MC |
13993 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
13994 | &tp->pci_cacheline_sz); | |
13995 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
13996 | &tp->pci_lat_timer); | |
1da177e4 LT |
13997 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
13998 | tp->pci_lat_timer < 64) { | |
13999 | tp->pci_lat_timer = 64; | |
69fc4053 MC |
14000 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
14001 | tp->pci_lat_timer); | |
1da177e4 LT |
14002 | } |
14003 | ||
16821285 MC |
14004 | /* Important! -- It is critical that the PCI-X hw workaround |
14005 | * situation is decided before the first MMIO register access. | |
14006 | */ | |
52f4490c MC |
14007 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
14008 | /* 5700 BX chips need to have their TX producer index | |
14009 | * mailboxes written twice to workaround a bug. | |
14010 | */ | |
63c3a66f | 14011 | tg3_flag_set(tp, TXD_MBOX_HWBUG); |
1da177e4 | 14012 | |
52f4490c | 14013 | /* If we are in PCI-X mode, enable register write workaround. |
1da177e4 LT |
14014 | * |
14015 | * The workaround is to use indirect register accesses | |
14016 | * for all chip writes not to mailbox registers. | |
14017 | */ | |
63c3a66f | 14018 | if (tg3_flag(tp, PCIX_MODE)) { |
1da177e4 | 14019 | u32 pm_reg; |
1da177e4 | 14020 | |
63c3a66f | 14021 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
1da177e4 LT |
14022 | |
14023 | /* The chip can have it's power management PCI config | |
14024 | * space registers clobbered due to this bug. | |
14025 | * So explicitly force the chip into D0 here. | |
14026 | */ | |
9974a356 MC |
14027 | pci_read_config_dword(tp->pdev, |
14028 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
14029 | &pm_reg); |
14030 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
14031 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
9974a356 MC |
14032 | pci_write_config_dword(tp->pdev, |
14033 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
14034 | pm_reg); |
14035 | ||
14036 | /* Also, force SERR#/PERR# in PCI command. */ | |
14037 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
14038 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
14039 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
14040 | } | |
14041 | } | |
14042 | ||
1da177e4 | 14043 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) |
63c3a66f | 14044 | tg3_flag_set(tp, PCI_HIGH_SPEED); |
1da177e4 | 14045 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) |
63c3a66f | 14046 | tg3_flag_set(tp, PCI_32BIT); |
1da177e4 LT |
14047 | |
14048 | /* Chip-specific fixup from Broadcom driver */ | |
14049 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
14050 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
14051 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
14052 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
14053 | } | |
14054 | ||
1ee582d8 | 14055 | /* Default fast path register access methods */ |
20094930 | 14056 | tp->read32 = tg3_read32; |
1ee582d8 | 14057 | tp->write32 = tg3_write32; |
09ee929c | 14058 | tp->read32_mbox = tg3_read32; |
20094930 | 14059 | tp->write32_mbox = tg3_write32; |
1ee582d8 MC |
14060 | tp->write32_tx_mbox = tg3_write32; |
14061 | tp->write32_rx_mbox = tg3_write32; | |
14062 | ||
14063 | /* Various workaround register access methods */ | |
63c3a66f | 14064 | if (tg3_flag(tp, PCIX_TARGET_HWBUG)) |
1ee582d8 | 14065 | tp->write32 = tg3_write_indirect_reg32; |
98efd8a6 | 14066 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
63c3a66f | 14067 | (tg3_flag(tp, PCI_EXPRESS) && |
98efd8a6 MC |
14068 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { |
14069 | /* | |
14070 | * Back to back register writes can cause problems on these | |
14071 | * chips, the workaround is to read back all reg writes | |
14072 | * except those to mailbox regs. | |
14073 | * | |
14074 | * See tg3_write_indirect_reg32(). | |
14075 | */ | |
1ee582d8 | 14076 | tp->write32 = tg3_write_flush_reg32; |
98efd8a6 MC |
14077 | } |
14078 | ||
63c3a66f | 14079 | if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { |
1ee582d8 | 14080 | tp->write32_tx_mbox = tg3_write32_tx_mbox; |
63c3a66f | 14081 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
1ee582d8 MC |
14082 | tp->write32_rx_mbox = tg3_write_flush_reg32; |
14083 | } | |
20094930 | 14084 | |
63c3a66f | 14085 | if (tg3_flag(tp, ICH_WORKAROUND)) { |
6892914f MC |
14086 | tp->read32 = tg3_read_indirect_reg32; |
14087 | tp->write32 = tg3_write_indirect_reg32; | |
14088 | tp->read32_mbox = tg3_read_indirect_mbox; | |
14089 | tp->write32_mbox = tg3_write_indirect_mbox; | |
14090 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
14091 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
14092 | ||
14093 | iounmap(tp->regs); | |
22abe310 | 14094 | tp->regs = NULL; |
6892914f MC |
14095 | |
14096 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
14097 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
14098 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
14099 | } | |
b5d3772c MC |
14100 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
14101 | tp->read32_mbox = tg3_read32_mbox_5906; | |
14102 | tp->write32_mbox = tg3_write32_mbox_5906; | |
14103 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
14104 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
14105 | } | |
6892914f | 14106 | |
bbadf503 | 14107 | if (tp->write32 == tg3_write_indirect_reg32 || |
63c3a66f | 14108 | (tg3_flag(tp, PCIX_MODE) && |
bbadf503 | 14109 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
f49639e6 | 14110 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
63c3a66f | 14111 | tg3_flag_set(tp, SRAM_USE_CONFIG); |
bbadf503 | 14112 | |
16821285 MC |
14113 | /* The memory arbiter has to be enabled in order for SRAM accesses |
14114 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
14115 | * sure it is enabled, but other entities such as system netboot | |
14116 | * code might disable it. | |
14117 | */ | |
14118 | val = tr32(MEMARB_MODE); | |
14119 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
14120 | ||
69f11c99 MC |
14121 | if (tg3_flag(tp, PCIX_MODE)) { |
14122 | pci_read_config_dword(tp->pdev, | |
14123 | tp->pcix_cap + PCI_X_STATUS, &val); | |
14124 | tp->pci_fn = val & 0x7; | |
14125 | } else { | |
14126 | tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; | |
14127 | } | |
14128 | ||
7d0c41ef | 14129 | /* Get eeprom hw config before calling tg3_set_power_state(). |
63c3a66f | 14130 | * In particular, the TG3_FLAG_IS_NIC flag must be |
7d0c41ef MC |
14131 | * determined before calling tg3_set_power_state() so that |
14132 | * we know whether or not to switch out of Vaux power. | |
14133 | * When the flag is set, it means that GPIO1 is used for eeprom | |
14134 | * write protect and also implies that it is a LOM where GPIOs | |
14135 | * are not used to switch power. | |
6aa20a22 | 14136 | */ |
7d0c41ef MC |
14137 | tg3_get_eeprom_hw_cfg(tp); |
14138 | ||
63c3a66f | 14139 | if (tg3_flag(tp, ENABLE_APE)) { |
0d3031d9 MC |
14140 | /* Allow reads and writes to the |
14141 | * APE register and memory space. | |
14142 | */ | |
14143 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
14144 | PCISTATE_ALLOW_APE_SHMEM_WR | |
14145 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
14146 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, |
14147 | pci_state_reg); | |
c9cab24e MC |
14148 | |
14149 | tg3_ape_lock_init(tp); | |
0d3031d9 MC |
14150 | } |
14151 | ||
9936bcf6 | 14152 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
57e6983c | 14153 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
321d32a0 | 14154 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 14155 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
63c3a66f JP |
14156 | tg3_flag(tp, 57765_PLUS)) |
14157 | tg3_flag_set(tp, CPMU_PRESENT); | |
d30cdd28 | 14158 | |
16821285 MC |
14159 | /* Set up tp->grc_local_ctrl before calling |
14160 | * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high | |
14161 | * will bring 5700's external PHY out of reset. | |
314fba34 MC |
14162 | * It is also used as eeprom write protect on LOMs. |
14163 | */ | |
14164 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
6ff6f81d | 14165 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
63c3a66f | 14166 | tg3_flag(tp, EEPROM_WRITE_PROT)) |
314fba34 MC |
14167 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
14168 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
3e7d83bc MC |
14169 | /* Unused GPIO3 must be driven as output on 5752 because there |
14170 | * are no pull-up resistors on unused GPIO pins. | |
14171 | */ | |
14172 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
14173 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
314fba34 | 14174 | |
321d32a0 | 14175 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
cb4ed1fd MC |
14176 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
14177 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
af36e6b6 MC |
14178 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
14179 | ||
8d519ab2 MC |
14180 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
14181 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
14182 | /* Turn off the debug UART. */ |
14183 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
63c3a66f | 14184 | if (tg3_flag(tp, IS_NIC)) |
5f0c4a3c MC |
14185 | /* Keep VMain power. */ |
14186 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
14187 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
14188 | } | |
14189 | ||
16821285 MC |
14190 | /* Switch out of Vaux if it is a NIC */ |
14191 | tg3_pwrsrc_switch_to_vmain(tp); | |
1da177e4 | 14192 | |
1da177e4 LT |
14193 | /* Derive initial jumbo mode from MTU assigned in |
14194 | * ether_setup() via the alloc_etherdev() call | |
14195 | */ | |
63c3a66f JP |
14196 | if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) |
14197 | tg3_flag_set(tp, JUMBO_RING_ENABLE); | |
1da177e4 LT |
14198 | |
14199 | /* Determine WakeOnLan speed to use. */ | |
14200 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14201 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
14202 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
14203 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
63c3a66f | 14204 | tg3_flag_clear(tp, WOL_SPEED_100MB); |
1da177e4 | 14205 | } else { |
63c3a66f | 14206 | tg3_flag_set(tp, WOL_SPEED_100MB); |
1da177e4 LT |
14207 | } |
14208 | ||
7f97a4bd | 14209 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
f07e9af3 | 14210 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
7f97a4bd | 14211 | |
1da177e4 | 14212 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
6ff6f81d MC |
14213 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
14214 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
1da177e4 | 14215 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && |
747e8f8b | 14216 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
f07e9af3 MC |
14217 | (tp->phy_flags & TG3_PHYFLG_IS_FET) || |
14218 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
14219 | tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; | |
1da177e4 LT |
14220 | |
14221 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
14222 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
f07e9af3 | 14223 | tp->phy_flags |= TG3_PHYFLG_ADC_BUG; |
1da177e4 | 14224 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) |
f07e9af3 | 14225 | tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; |
1da177e4 | 14226 | |
63c3a66f | 14227 | if (tg3_flag(tp, 5705_PLUS) && |
f07e9af3 | 14228 | !(tp->phy_flags & TG3_PHYFLG_IS_FET) && |
321d32a0 | 14229 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
f6eb9b1f | 14230 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && |
63c3a66f | 14231 | !tg3_flag(tp, 57765_PLUS)) { |
c424cb24 | 14232 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
d30cdd28 | 14233 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
9936bcf6 MC |
14234 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
14235 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
d4011ada MC |
14236 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
14237 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
f07e9af3 | 14238 | tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; |
c1d2a196 | 14239 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) |
f07e9af3 | 14240 | tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; |
321d32a0 | 14241 | } else |
f07e9af3 | 14242 | tp->phy_flags |= TG3_PHYFLG_BER_BUG; |
c424cb24 | 14243 | } |
1da177e4 | 14244 | |
b2a5c19c MC |
14245 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
14246 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
14247 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
14248 | if (tp->phy_otp == 0) | |
14249 | tp->phy_otp = TG3_OTP_DEFAULT; | |
14250 | } | |
14251 | ||
63c3a66f | 14252 | if (tg3_flag(tp, CPMU_PRESENT)) |
8ef21428 MC |
14253 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
14254 | else | |
14255 | tp->mi_mode = MAC_MI_MODE_BASE; | |
14256 | ||
1da177e4 | 14257 | tp->coalesce_mode = 0; |
1da177e4 LT |
14258 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
14259 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
14260 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
14261 | ||
4d958473 MC |
14262 | /* Set these bits to enable statistics workaround. */ |
14263 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
14264 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
14265 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) { | |
14266 | tp->coalesce_mode |= HOSTCC_MODE_ATTN; | |
14267 | tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; | |
14268 | } | |
14269 | ||
321d32a0 MC |
14270 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
14271 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
63c3a66f | 14272 | tg3_flag_set(tp, USE_PHYLIB); |
57e6983c | 14273 | |
158d7abd MC |
14274 | err = tg3_mdio_init(tp); |
14275 | if (err) | |
14276 | return err; | |
1da177e4 LT |
14277 | |
14278 | /* Initialize data/descriptor byte/word swapping. */ | |
14279 | val = tr32(GRC_MODE); | |
f2096f94 MC |
14280 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
14281 | val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA | | |
14282 | GRC_MODE_WORD_SWAP_B2HRX_DATA | | |
14283 | GRC_MODE_B2HRX_ENABLE | | |
14284 | GRC_MODE_HTX2B_ENABLE | | |
14285 | GRC_MODE_HOST_STACKUP); | |
14286 | else | |
14287 | val &= GRC_MODE_HOST_STACKUP; | |
14288 | ||
1da177e4 LT |
14289 | tw32(GRC_MODE, val | tp->grc_mode); |
14290 | ||
14291 | tg3_switch_clocks(tp); | |
14292 | ||
14293 | /* Clear this out for sanity. */ | |
14294 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14295 | ||
14296 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
14297 | &pci_state_reg); | |
14298 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
63c3a66f | 14299 | !tg3_flag(tp, PCIX_TARGET_HWBUG)) { |
1da177e4 LT |
14300 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); |
14301 | ||
14302 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
14303 | chiprevid == CHIPREV_ID_5701_B0 || | |
14304 | chiprevid == CHIPREV_ID_5701_B2 || | |
14305 | chiprevid == CHIPREV_ID_5701_B5) { | |
14306 | void __iomem *sram_base; | |
14307 | ||
14308 | /* Write some dummy words into the SRAM status block | |
14309 | * area, see if it reads back correctly. If the return | |
14310 | * value is bad, force enable the PCIX workaround. | |
14311 | */ | |
14312 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
14313 | ||
14314 | writel(0x00000000, sram_base); | |
14315 | writel(0x00000000, sram_base + 4); | |
14316 | writel(0xffffffff, sram_base + 4); | |
14317 | if (readl(sram_base) != 0x00000000) | |
63c3a66f | 14318 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
1da177e4 LT |
14319 | } |
14320 | } | |
14321 | ||
14322 | udelay(50); | |
14323 | tg3_nvram_init(tp); | |
14324 | ||
14325 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
14326 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
14327 | ||
1da177e4 LT |
14328 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
14329 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
14330 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
63c3a66f | 14331 | tg3_flag_set(tp, IS_5788); |
1da177e4 | 14332 | |
63c3a66f | 14333 | if (!tg3_flag(tp, IS_5788) && |
6ff6f81d | 14334 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
63c3a66f JP |
14335 | tg3_flag_set(tp, TAGGED_STATUS); |
14336 | if (tg3_flag(tp, TAGGED_STATUS)) { | |
fac9b83e DM |
14337 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | |
14338 | HOSTCC_MODE_CLRTICK_TXBD); | |
14339 | ||
14340 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
14341 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
14342 | tp->misc_host_ctrl); | |
14343 | } | |
14344 | ||
3bda1258 | 14345 | /* Preserve the APE MAC_MODE bits */ |
63c3a66f | 14346 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b | 14347 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 | 14348 | else |
6e01b20b | 14349 | tp->mac_mode = 0; |
3bda1258 | 14350 | |
1da177e4 LT |
14351 | /* these are limited to 10/100 only */ |
14352 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
14353 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
14354 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
14355 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14356 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || | |
14357 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || | |
14358 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || | |
14359 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14360 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || | |
676917d4 MC |
14361 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || |
14362 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | |
321d32a0 | 14363 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || |
d1101142 MC |
14364 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || |
14365 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || | |
f07e9af3 MC |
14366 | (tp->phy_flags & TG3_PHYFLG_IS_FET)) |
14367 | tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; | |
1da177e4 LT |
14368 | |
14369 | err = tg3_phy_probe(tp); | |
14370 | if (err) { | |
2445e461 | 14371 | dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); |
1da177e4 | 14372 | /* ... but do not return immediately ... */ |
b02fd9e3 | 14373 | tg3_mdio_fini(tp); |
1da177e4 LT |
14374 | } |
14375 | ||
184b8904 | 14376 | tg3_read_vpd(tp); |
c4e6575c | 14377 | tg3_read_fw_ver(tp); |
1da177e4 | 14378 | |
f07e9af3 MC |
14379 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
14380 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; | |
1da177e4 LT |
14381 | } else { |
14382 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
f07e9af3 | 14383 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 | 14384 | else |
f07e9af3 | 14385 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 LT |
14386 | } |
14387 | ||
14388 | /* 5700 {AX,BX} chips have a broken status block link | |
14389 | * change bit implementation, so we must use the | |
14390 | * status register in those cases. | |
14391 | */ | |
14392 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
63c3a66f | 14393 | tg3_flag_set(tp, USE_LINKCHG_REG); |
1da177e4 | 14394 | else |
63c3a66f | 14395 | tg3_flag_clear(tp, USE_LINKCHG_REG); |
1da177e4 LT |
14396 | |
14397 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
14398 | * have to force the link status polling mechanism based | |
14399 | * upon subsystem IDs. | |
14400 | */ | |
14401 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
007a880d | 14402 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
f07e9af3 MC |
14403 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
14404 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; | |
63c3a66f | 14405 | tg3_flag_set(tp, USE_LINKCHG_REG); |
1da177e4 LT |
14406 | } |
14407 | ||
14408 | /* For all SERDES we poll the MAC status register. */ | |
f07e9af3 | 14409 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
63c3a66f | 14410 | tg3_flag_set(tp, POLL_SERDES); |
1da177e4 | 14411 | else |
63c3a66f | 14412 | tg3_flag_clear(tp, POLL_SERDES); |
1da177e4 | 14413 | |
bf933c80 | 14414 | tp->rx_offset = NET_IP_ALIGN; |
d2757fc4 | 14415 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; |
1da177e4 | 14416 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
63c3a66f | 14417 | tg3_flag(tp, PCIX_MODE)) { |
bf933c80 | 14418 | tp->rx_offset = 0; |
d2757fc4 | 14419 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
9dc7a113 | 14420 | tp->rx_copy_thresh = ~(u16)0; |
d2757fc4 MC |
14421 | #endif |
14422 | } | |
1da177e4 | 14423 | |
2c49a44d MC |
14424 | tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; |
14425 | tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; | |
7cb32cf2 MC |
14426 | tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; |
14427 | ||
2c49a44d | 14428 | tp->rx_std_max_post = tp->rx_std_ring_mask + 1; |
f92905de MC |
14429 | |
14430 | /* Increment the rx prod index on the rx std ring by at most | |
14431 | * 8 for these chips to workaround hw errata. | |
14432 | */ | |
14433 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
14434 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
14435 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
14436 | tp->rx_std_max_post = 8; | |
14437 | ||
63c3a66f | 14438 | if (tg3_flag(tp, ASPM_WORKAROUND)) |
8ed5d97e MC |
14439 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & |
14440 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
14441 | ||
1da177e4 LT |
14442 | return err; |
14443 | } | |
14444 | ||
49b6e95f | 14445 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14446 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) |
14447 | { | |
14448 | struct net_device *dev = tp->dev; | |
14449 | struct pci_dev *pdev = tp->pdev; | |
49b6e95f | 14450 | struct device_node *dp = pci_device_to_OF_node(pdev); |
374d4cac | 14451 | const unsigned char *addr; |
49b6e95f DM |
14452 | int len; |
14453 | ||
14454 | addr = of_get_property(dp, "local-mac-address", &len); | |
14455 | if (addr && len == 6) { | |
14456 | memcpy(dev->dev_addr, addr, 6); | |
14457 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
14458 | return 0; | |
1da177e4 LT |
14459 | } |
14460 | return -ENODEV; | |
14461 | } | |
14462 | ||
14463 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
14464 | { | |
14465 | struct net_device *dev = tp->dev; | |
14466 | ||
14467 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
2ff43697 | 14468 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); |
1da177e4 LT |
14469 | return 0; |
14470 | } | |
14471 | #endif | |
14472 | ||
14473 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
14474 | { | |
14475 | struct net_device *dev = tp->dev; | |
14476 | u32 hi, lo, mac_offset; | |
008652b3 | 14477 | int addr_ok = 0; |
1da177e4 | 14478 | |
49b6e95f | 14479 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14480 | if (!tg3_get_macaddr_sparc(tp)) |
14481 | return 0; | |
14482 | #endif | |
14483 | ||
14484 | mac_offset = 0x7c; | |
6ff6f81d | 14485 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
63c3a66f | 14486 | tg3_flag(tp, 5780_CLASS)) { |
1da177e4 LT |
14487 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
14488 | mac_offset = 0xcc; | |
14489 | if (tg3_nvram_lock(tp)) | |
14490 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
14491 | else | |
14492 | tg3_nvram_unlock(tp); | |
63c3a66f | 14493 | } else if (tg3_flag(tp, 5717_PLUS)) { |
69f11c99 | 14494 | if (tp->pci_fn & 1) |
a1b950d5 | 14495 | mac_offset = 0xcc; |
69f11c99 | 14496 | if (tp->pci_fn > 1) |
a50d0796 | 14497 | mac_offset += 0x18c; |
a1b950d5 | 14498 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
b5d3772c | 14499 | mac_offset = 0x10; |
1da177e4 LT |
14500 | |
14501 | /* First try to get it from MAC address mailbox. */ | |
14502 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
14503 | if ((hi >> 16) == 0x484b) { | |
14504 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14505 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
14506 | ||
14507 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
14508 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14509 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14510 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14511 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
1da177e4 | 14512 | |
008652b3 MC |
14513 | /* Some old bootcode may report a 0 MAC address in SRAM */ |
14514 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
14515 | } | |
14516 | if (!addr_ok) { | |
14517 | /* Next, try NVRAM. */ | |
63c3a66f | 14518 | if (!tg3_flag(tp, NO_NVRAM) && |
df259d8c | 14519 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && |
6d348f2c | 14520 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { |
62cedd11 MC |
14521 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); |
14522 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
008652b3 MC |
14523 | } |
14524 | /* Finally just fetch it out of the MAC control regs. */ | |
14525 | else { | |
14526 | hi = tr32(MAC_ADDR_0_HIGH); | |
14527 | lo = tr32(MAC_ADDR_0_LOW); | |
14528 | ||
14529 | dev->dev_addr[5] = lo & 0xff; | |
14530 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14531 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14532 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14533 | dev->dev_addr[1] = hi & 0xff; | |
14534 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14535 | } | |
1da177e4 LT |
14536 | } |
14537 | ||
14538 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
7582a335 | 14539 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14540 | if (!tg3_get_default_macaddr_sparc(tp)) |
14541 | return 0; | |
14542 | #endif | |
14543 | return -EINVAL; | |
14544 | } | |
2ff43697 | 14545 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
14546 | return 0; |
14547 | } | |
14548 | ||
59e6b434 DM |
14549 | #define BOUNDARY_SINGLE_CACHELINE 1 |
14550 | #define BOUNDARY_MULTI_CACHELINE 2 | |
14551 | ||
14552 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
14553 | { | |
14554 | int cacheline_size; | |
14555 | u8 byte; | |
14556 | int goal; | |
14557 | ||
14558 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
14559 | if (byte == 0) | |
14560 | cacheline_size = 1024; | |
14561 | else | |
14562 | cacheline_size = (int) byte * 4; | |
14563 | ||
14564 | /* On 5703 and later chips, the boundary bits have no | |
14565 | * effect. | |
14566 | */ | |
14567 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
14568 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
63c3a66f | 14569 | !tg3_flag(tp, PCI_EXPRESS)) |
59e6b434 DM |
14570 | goto out; |
14571 | ||
14572 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
14573 | goal = BOUNDARY_MULTI_CACHELINE; | |
14574 | #else | |
14575 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
14576 | goal = BOUNDARY_SINGLE_CACHELINE; | |
14577 | #else | |
14578 | goal = 0; | |
14579 | #endif | |
14580 | #endif | |
14581 | ||
63c3a66f | 14582 | if (tg3_flag(tp, 57765_PLUS)) { |
cbf9ca6c MC |
14583 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
14584 | goto out; | |
14585 | } | |
14586 | ||
59e6b434 DM |
14587 | if (!goal) |
14588 | goto out; | |
14589 | ||
14590 | /* PCI controllers on most RISC systems tend to disconnect | |
14591 | * when a device tries to burst across a cache-line boundary. | |
14592 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
14593 | * | |
14594 | * Unfortunately, for PCI-E there are only limited | |
14595 | * write-side controls for this, and thus for reads | |
14596 | * we will still get the disconnects. We'll also waste | |
14597 | * these PCI cycles for both read and write for chips | |
14598 | * other than 5700 and 5701 which do not implement the | |
14599 | * boundary bits. | |
14600 | */ | |
63c3a66f | 14601 | if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { |
59e6b434 DM |
14602 | switch (cacheline_size) { |
14603 | case 16: | |
14604 | case 32: | |
14605 | case 64: | |
14606 | case 128: | |
14607 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14608 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
14609 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
14610 | } else { | |
14611 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14612 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14613 | } | |
14614 | break; | |
14615 | ||
14616 | case 256: | |
14617 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
14618 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
14619 | break; | |
14620 | ||
14621 | default: | |
14622 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14623 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14624 | break; | |
855e1111 | 14625 | } |
63c3a66f | 14626 | } else if (tg3_flag(tp, PCI_EXPRESS)) { |
59e6b434 DM |
14627 | switch (cacheline_size) { |
14628 | case 16: | |
14629 | case 32: | |
14630 | case 64: | |
14631 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14632 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14633 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
14634 | break; | |
14635 | } | |
14636 | /* fallthrough */ | |
14637 | case 128: | |
14638 | default: | |
14639 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14640 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
14641 | break; | |
855e1111 | 14642 | } |
59e6b434 DM |
14643 | } else { |
14644 | switch (cacheline_size) { | |
14645 | case 16: | |
14646 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14647 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
14648 | DMA_RWCTRL_WRITE_BNDRY_16); | |
14649 | break; | |
14650 | } | |
14651 | /* fallthrough */ | |
14652 | case 32: | |
14653 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14654 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
14655 | DMA_RWCTRL_WRITE_BNDRY_32); | |
14656 | break; | |
14657 | } | |
14658 | /* fallthrough */ | |
14659 | case 64: | |
14660 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14661 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
14662 | DMA_RWCTRL_WRITE_BNDRY_64); | |
14663 | break; | |
14664 | } | |
14665 | /* fallthrough */ | |
14666 | case 128: | |
14667 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14668 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
14669 | DMA_RWCTRL_WRITE_BNDRY_128); | |
14670 | break; | |
14671 | } | |
14672 | /* fallthrough */ | |
14673 | case 256: | |
14674 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
14675 | DMA_RWCTRL_WRITE_BNDRY_256); | |
14676 | break; | |
14677 | case 512: | |
14678 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
14679 | DMA_RWCTRL_WRITE_BNDRY_512); | |
14680 | break; | |
14681 | case 1024: | |
14682 | default: | |
14683 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
14684 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
14685 | break; | |
855e1111 | 14686 | } |
59e6b434 DM |
14687 | } |
14688 | ||
14689 | out: | |
14690 | return val; | |
14691 | } | |
14692 | ||
1da177e4 LT |
14693 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) |
14694 | { | |
14695 | struct tg3_internal_buffer_desc test_desc; | |
14696 | u32 sram_dma_descs; | |
14697 | int i, ret; | |
14698 | ||
14699 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
14700 | ||
14701 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
14702 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
14703 | tw32(RDMAC_STATUS, 0); | |
14704 | tw32(WDMAC_STATUS, 0); | |
14705 | ||
14706 | tw32(BUFMGR_MODE, 0); | |
14707 | tw32(FTQ_RESET, 0); | |
14708 | ||
14709 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
14710 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
14711 | test_desc.nic_mbuf = 0x00002100; | |
14712 | test_desc.len = size; | |
14713 | ||
14714 | /* | |
14715 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
14716 | * the *second* time the tg3 driver was getting loaded after an | |
14717 | * initial scan. | |
14718 | * | |
14719 | * Broadcom tells me: | |
14720 | * ...the DMA engine is connected to the GRC block and a DMA | |
14721 | * reset may affect the GRC block in some unpredictable way... | |
14722 | * The behavior of resets to individual blocks has not been tested. | |
14723 | * | |
14724 | * Broadcom noted the GRC reset will also reset all sub-components. | |
14725 | */ | |
14726 | if (to_device) { | |
14727 | test_desc.cqid_sqid = (13 << 8) | 2; | |
14728 | ||
14729 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
14730 | udelay(40); | |
14731 | } else { | |
14732 | test_desc.cqid_sqid = (16 << 8) | 7; | |
14733 | ||
14734 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
14735 | udelay(40); | |
14736 | } | |
14737 | test_desc.flags = 0x00000005; | |
14738 | ||
14739 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
14740 | u32 val; | |
14741 | ||
14742 | val = *(((u32 *)&test_desc) + i); | |
14743 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
14744 | sram_dma_descs + (i * sizeof(u32))); | |
14745 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
14746 | } | |
14747 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14748 | ||
859a5887 | 14749 | if (to_device) |
1da177e4 | 14750 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); |
859a5887 | 14751 | else |
1da177e4 | 14752 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); |
1da177e4 LT |
14753 | |
14754 | ret = -ENODEV; | |
14755 | for (i = 0; i < 40; i++) { | |
14756 | u32 val; | |
14757 | ||
14758 | if (to_device) | |
14759 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
14760 | else | |
14761 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
14762 | if ((val & 0xffff) == sram_dma_descs) { | |
14763 | ret = 0; | |
14764 | break; | |
14765 | } | |
14766 | ||
14767 | udelay(100); | |
14768 | } | |
14769 | ||
14770 | return ret; | |
14771 | } | |
14772 | ||
ded7340d | 14773 | #define TEST_BUFFER_SIZE 0x2000 |
1da177e4 | 14774 | |
4143470c | 14775 | static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = { |
895950c2 JP |
14776 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, |
14777 | { }, | |
14778 | }; | |
14779 | ||
1da177e4 LT |
14780 | static int __devinit tg3_test_dma(struct tg3 *tp) |
14781 | { | |
14782 | dma_addr_t buf_dma; | |
59e6b434 | 14783 | u32 *buf, saved_dma_rwctrl; |
cbf9ca6c | 14784 | int ret = 0; |
1da177e4 | 14785 | |
4bae65c8 MC |
14786 | buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, |
14787 | &buf_dma, GFP_KERNEL); | |
1da177e4 LT |
14788 | if (!buf) { |
14789 | ret = -ENOMEM; | |
14790 | goto out_nofree; | |
14791 | } | |
14792 | ||
14793 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
14794 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
14795 | ||
59e6b434 | 14796 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
1da177e4 | 14797 | |
63c3a66f | 14798 | if (tg3_flag(tp, 57765_PLUS)) |
cbf9ca6c MC |
14799 | goto out; |
14800 | ||
63c3a66f | 14801 | if (tg3_flag(tp, PCI_EXPRESS)) { |
1da177e4 LT |
14802 | /* DMA read watermark not used on PCIE */ |
14803 | tp->dma_rwctrl |= 0x00180000; | |
63c3a66f | 14804 | } else if (!tg3_flag(tp, PCIX_MODE)) { |
85e94ced MC |
14805 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
14806 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
1da177e4 LT |
14807 | tp->dma_rwctrl |= 0x003f0000; |
14808 | else | |
14809 | tp->dma_rwctrl |= 0x003f000f; | |
14810 | } else { | |
14811 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14812 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
14813 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
49afdeb6 | 14814 | u32 read_water = 0x7; |
1da177e4 | 14815 | |
4a29cc2e MC |
14816 | /* If the 5704 is behind the EPB bridge, we can |
14817 | * do the less restrictive ONE_DMA workaround for | |
14818 | * better performance. | |
14819 | */ | |
63c3a66f | 14820 | if (tg3_flag(tp, 40BIT_DMA_BUG) && |
4a29cc2e MC |
14821 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) |
14822 | tp->dma_rwctrl |= 0x8000; | |
14823 | else if (ccval == 0x6 || ccval == 0x7) | |
1da177e4 LT |
14824 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
14825 | ||
49afdeb6 MC |
14826 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) |
14827 | read_water = 4; | |
59e6b434 | 14828 | /* Set bit 23 to enable PCIX hw bug fix */ |
49afdeb6 MC |
14829 | tp->dma_rwctrl |= |
14830 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
14831 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
14832 | (1 << 23); | |
4cf78e4f MC |
14833 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { |
14834 | /* 5780 always in PCIX mode */ | |
14835 | tp->dma_rwctrl |= 0x00144000; | |
a4e2b347 MC |
14836 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
14837 | /* 5714 always in PCIX mode */ | |
14838 | tp->dma_rwctrl |= 0x00148000; | |
1da177e4 LT |
14839 | } else { |
14840 | tp->dma_rwctrl |= 0x001b000f; | |
14841 | } | |
14842 | } | |
14843 | ||
14844 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14845 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
14846 | tp->dma_rwctrl &= 0xfffffff0; | |
14847 | ||
14848 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14849 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
14850 | /* Remove this if it causes problems for some boards. */ | |
14851 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
14852 | ||
14853 | /* On 5700/5701 chips, we need to set this bit. | |
14854 | * Otherwise the chip will issue cacheline transactions | |
14855 | * to streamable DMA memory with not all the byte | |
14856 | * enables turned on. This is an error on several | |
14857 | * RISC PCI controllers, in particular sparc64. | |
14858 | * | |
14859 | * On 5703/5704 chips, this bit has been reassigned | |
14860 | * a different meaning. In particular, it is used | |
14861 | * on those chips to enable a PCI-X workaround. | |
14862 | */ | |
14863 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
14864 | } | |
14865 | ||
14866 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14867 | ||
14868 | #if 0 | |
14869 | /* Unneeded, already done by tg3_get_invariants. */ | |
14870 | tg3_switch_clocks(tp); | |
14871 | #endif | |
14872 | ||
1da177e4 LT |
14873 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
14874 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
14875 | goto out; | |
14876 | ||
59e6b434 DM |
14877 | /* It is best to perform DMA test with maximum write burst size |
14878 | * to expose the 5700/5701 write DMA bug. | |
14879 | */ | |
14880 | saved_dma_rwctrl = tp->dma_rwctrl; | |
14881 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
14882 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14883 | ||
1da177e4 LT |
14884 | while (1) { |
14885 | u32 *p = buf, i; | |
14886 | ||
14887 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
14888 | p[i] = i; | |
14889 | ||
14890 | /* Send the buffer to the chip. */ | |
14891 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
14892 | if (ret) { | |
2445e461 MC |
14893 | dev_err(&tp->pdev->dev, |
14894 | "%s: Buffer write failed. err = %d\n", | |
14895 | __func__, ret); | |
1da177e4 LT |
14896 | break; |
14897 | } | |
14898 | ||
14899 | #if 0 | |
14900 | /* validate data reached card RAM correctly. */ | |
14901 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14902 | u32 val; | |
14903 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
14904 | if (le32_to_cpu(val) != p[i]) { | |
2445e461 MC |
14905 | dev_err(&tp->pdev->dev, |
14906 | "%s: Buffer corrupted on device! " | |
14907 | "(%d != %d)\n", __func__, val, i); | |
1da177e4 LT |
14908 | /* ret = -ENODEV here? */ |
14909 | } | |
14910 | p[i] = 0; | |
14911 | } | |
14912 | #endif | |
14913 | /* Now read it back. */ | |
14914 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
14915 | if (ret) { | |
5129c3a3 MC |
14916 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " |
14917 | "err = %d\n", __func__, ret); | |
1da177e4 LT |
14918 | break; |
14919 | } | |
14920 | ||
14921 | /* Verify it. */ | |
14922 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14923 | if (p[i] == i) | |
14924 | continue; | |
14925 | ||
59e6b434 DM |
14926 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
14927 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
14928 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
1da177e4 LT |
14929 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
14930 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14931 | break; | |
14932 | } else { | |
2445e461 MC |
14933 | dev_err(&tp->pdev->dev, |
14934 | "%s: Buffer corrupted on read back! " | |
14935 | "(%d != %d)\n", __func__, p[i], i); | |
1da177e4 LT |
14936 | ret = -ENODEV; |
14937 | goto out; | |
14938 | } | |
14939 | } | |
14940 | ||
14941 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
14942 | /* Success. */ | |
14943 | ret = 0; | |
14944 | break; | |
14945 | } | |
14946 | } | |
59e6b434 DM |
14947 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
14948 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
14949 | /* DMA test passed without adjusting DMA boundary, | |
6d1cfbab MC |
14950 | * now look for chipsets that are known to expose the |
14951 | * DMA bug without failing the test. | |
59e6b434 | 14952 | */ |
4143470c | 14953 | if (pci_dev_present(tg3_dma_wait_state_chipsets)) { |
6d1cfbab MC |
14954 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; |
14955 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
859a5887 | 14956 | } else { |
6d1cfbab MC |
14957 | /* Safe to use the calculated DMA boundary. */ |
14958 | tp->dma_rwctrl = saved_dma_rwctrl; | |
859a5887 | 14959 | } |
6d1cfbab | 14960 | |
59e6b434 DM |
14961 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
14962 | } | |
1da177e4 LT |
14963 | |
14964 | out: | |
4bae65c8 | 14965 | dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); |
1da177e4 LT |
14966 | out_nofree: |
14967 | return ret; | |
14968 | } | |
14969 | ||
1da177e4 LT |
14970 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) |
14971 | { | |
63c3a66f | 14972 | if (tg3_flag(tp, 57765_PLUS)) { |
666bc831 MC |
14973 | tp->bufmgr_config.mbuf_read_dma_low_water = |
14974 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14975 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14976 | DEFAULT_MB_MACRX_LOW_WATER_57765; | |
14977 | tp->bufmgr_config.mbuf_high_water = | |
14978 | DEFAULT_MB_HIGH_WATER_57765; | |
14979 | ||
14980 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14981 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14982 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14983 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; | |
14984 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14985 | DEFAULT_MB_HIGH_WATER_JUMBO_57765; | |
63c3a66f | 14986 | } else if (tg3_flag(tp, 5705_PLUS)) { |
fdfec172 MC |
14987 | tp->bufmgr_config.mbuf_read_dma_low_water = |
14988 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14989 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14990 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
14991 | tp->bufmgr_config.mbuf_high_water = | |
14992 | DEFAULT_MB_HIGH_WATER_5705; | |
b5d3772c MC |
14993 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
14994 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14995 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
14996 | tp->bufmgr_config.mbuf_high_water = | |
14997 | DEFAULT_MB_HIGH_WATER_5906; | |
14998 | } | |
fdfec172 MC |
14999 | |
15000 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
15001 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
15002 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
15003 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
15004 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
15005 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
15006 | } else { | |
15007 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
15008 | DEFAULT_MB_RDMA_LOW_WATER; | |
15009 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15010 | DEFAULT_MB_MACRX_LOW_WATER; | |
15011 | tp->bufmgr_config.mbuf_high_water = | |
15012 | DEFAULT_MB_HIGH_WATER; | |
15013 | ||
15014 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
15015 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
15016 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
15017 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
15018 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
15019 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
15020 | } | |
1da177e4 LT |
15021 | |
15022 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
15023 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
15024 | } | |
15025 | ||
15026 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
15027 | { | |
79eb6904 MC |
15028 | switch (tp->phy_id & TG3_PHY_ID_MASK) { |
15029 | case TG3_PHY_ID_BCM5400: return "5400"; | |
15030 | case TG3_PHY_ID_BCM5401: return "5401"; | |
15031 | case TG3_PHY_ID_BCM5411: return "5411"; | |
15032 | case TG3_PHY_ID_BCM5701: return "5701"; | |
15033 | case TG3_PHY_ID_BCM5703: return "5703"; | |
15034 | case TG3_PHY_ID_BCM5704: return "5704"; | |
15035 | case TG3_PHY_ID_BCM5705: return "5705"; | |
15036 | case TG3_PHY_ID_BCM5750: return "5750"; | |
15037 | case TG3_PHY_ID_BCM5752: return "5752"; | |
15038 | case TG3_PHY_ID_BCM5714: return "5714"; | |
15039 | case TG3_PHY_ID_BCM5780: return "5780"; | |
15040 | case TG3_PHY_ID_BCM5755: return "5755"; | |
15041 | case TG3_PHY_ID_BCM5787: return "5787"; | |
15042 | case TG3_PHY_ID_BCM5784: return "5784"; | |
15043 | case TG3_PHY_ID_BCM5756: return "5722/5756"; | |
15044 | case TG3_PHY_ID_BCM5906: return "5906"; | |
15045 | case TG3_PHY_ID_BCM5761: return "5761"; | |
15046 | case TG3_PHY_ID_BCM5718C: return "5718C"; | |
15047 | case TG3_PHY_ID_BCM5718S: return "5718S"; | |
15048 | case TG3_PHY_ID_BCM57765: return "57765"; | |
302b500b | 15049 | case TG3_PHY_ID_BCM5719C: return "5719C"; |
6418f2c1 | 15050 | case TG3_PHY_ID_BCM5720C: return "5720C"; |
79eb6904 | 15051 | case TG3_PHY_ID_BCM8002: return "8002/serdes"; |
1da177e4 LT |
15052 | case 0: return "serdes"; |
15053 | default: return "unknown"; | |
855e1111 | 15054 | } |
1da177e4 LT |
15055 | } |
15056 | ||
f9804ddb MC |
15057 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |
15058 | { | |
63c3a66f | 15059 | if (tg3_flag(tp, PCI_EXPRESS)) { |
f9804ddb MC |
15060 | strcpy(str, "PCI Express"); |
15061 | return str; | |
63c3a66f | 15062 | } else if (tg3_flag(tp, PCIX_MODE)) { |
f9804ddb MC |
15063 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; |
15064 | ||
15065 | strcpy(str, "PCIX:"); | |
15066 | ||
15067 | if ((clock_ctrl == 7) || | |
15068 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
15069 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
15070 | strcat(str, "133MHz"); | |
15071 | else if (clock_ctrl == 0) | |
15072 | strcat(str, "33MHz"); | |
15073 | else if (clock_ctrl == 2) | |
15074 | strcat(str, "50MHz"); | |
15075 | else if (clock_ctrl == 4) | |
15076 | strcat(str, "66MHz"); | |
15077 | else if (clock_ctrl == 6) | |
15078 | strcat(str, "100MHz"); | |
f9804ddb MC |
15079 | } else { |
15080 | strcpy(str, "PCI:"); | |
63c3a66f | 15081 | if (tg3_flag(tp, PCI_HIGH_SPEED)) |
f9804ddb MC |
15082 | strcat(str, "66MHz"); |
15083 | else | |
15084 | strcat(str, "33MHz"); | |
15085 | } | |
63c3a66f | 15086 | if (tg3_flag(tp, PCI_32BIT)) |
f9804ddb MC |
15087 | strcat(str, ":32-bit"); |
15088 | else | |
15089 | strcat(str, ":64-bit"); | |
15090 | return str; | |
15091 | } | |
15092 | ||
8c2dc7e1 | 15093 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) |
1da177e4 LT |
15094 | { |
15095 | struct pci_dev *peer; | |
15096 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
15097 | ||
15098 | for (func = 0; func < 8; func++) { | |
15099 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
15100 | if (peer && peer != tp->pdev) | |
15101 | break; | |
15102 | pci_dev_put(peer); | |
15103 | } | |
16fe9d74 MC |
15104 | /* 5704 can be configured in single-port mode, set peer to |
15105 | * tp->pdev in that case. | |
15106 | */ | |
15107 | if (!peer) { | |
15108 | peer = tp->pdev; | |
15109 | return peer; | |
15110 | } | |
1da177e4 LT |
15111 | |
15112 | /* | |
15113 | * We don't need to keep the refcount elevated; there's no way | |
15114 | * to remove one half of this device without removing the other | |
15115 | */ | |
15116 | pci_dev_put(peer); | |
15117 | ||
15118 | return peer; | |
15119 | } | |
15120 | ||
15f9850d DM |
15121 | static void __devinit tg3_init_coal(struct tg3 *tp) |
15122 | { | |
15123 | struct ethtool_coalesce *ec = &tp->coal; | |
15124 | ||
15125 | memset(ec, 0, sizeof(*ec)); | |
15126 | ec->cmd = ETHTOOL_GCOALESCE; | |
15127 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
15128 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
15129 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
15130 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
15131 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
15132 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
15133 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
15134 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
15135 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
15136 | ||
15137 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
15138 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
15139 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
15140 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
15141 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
15142 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
15143 | } | |
d244c892 | 15144 | |
63c3a66f | 15145 | if (tg3_flag(tp, 5705_PLUS)) { |
d244c892 MC |
15146 | ec->rx_coalesce_usecs_irq = 0; |
15147 | ec->tx_coalesce_usecs_irq = 0; | |
15148 | ec->stats_block_coalesce_usecs = 0; | |
15149 | } | |
15f9850d DM |
15150 | } |
15151 | ||
7c7d64b8 SH |
15152 | static const struct net_device_ops tg3_netdev_ops = { |
15153 | .ndo_open = tg3_open, | |
15154 | .ndo_stop = tg3_close, | |
00829823 | 15155 | .ndo_start_xmit = tg3_start_xmit, |
511d2224 | 15156 | .ndo_get_stats64 = tg3_get_stats64, |
00829823 | 15157 | .ndo_validate_addr = eth_validate_addr, |
afc4b13d | 15158 | .ndo_set_rx_mode = tg3_set_rx_mode, |
00829823 SH |
15159 | .ndo_set_mac_address = tg3_set_mac_addr, |
15160 | .ndo_do_ioctl = tg3_ioctl, | |
15161 | .ndo_tx_timeout = tg3_tx_timeout, | |
15162 | .ndo_change_mtu = tg3_change_mtu, | |
dc668910 | 15163 | .ndo_fix_features = tg3_fix_features, |
06c03c02 | 15164 | .ndo_set_features = tg3_set_features, |
00829823 SH |
15165 | #ifdef CONFIG_NET_POLL_CONTROLLER |
15166 | .ndo_poll_controller = tg3_poll_controller, | |
15167 | #endif | |
15168 | }; | |
15169 | ||
1da177e4 LT |
15170 | static int __devinit tg3_init_one(struct pci_dev *pdev, |
15171 | const struct pci_device_id *ent) | |
15172 | { | |
1da177e4 LT |
15173 | struct net_device *dev; |
15174 | struct tg3 *tp; | |
646c9edd MC |
15175 | int i, err, pm_cap; |
15176 | u32 sndmbx, rcvmbx, intmbx; | |
f9804ddb | 15177 | char str[40]; |
72f2afb8 | 15178 | u64 dma_mask, persist_dma_mask; |
0da0606f | 15179 | u32 features = 0; |
1da177e4 | 15180 | |
05dbe005 | 15181 | printk_once(KERN_INFO "%s\n", version); |
1da177e4 LT |
15182 | |
15183 | err = pci_enable_device(pdev); | |
15184 | if (err) { | |
2445e461 | 15185 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
1da177e4 LT |
15186 | return err; |
15187 | } | |
15188 | ||
1da177e4 LT |
15189 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
15190 | if (err) { | |
2445e461 | 15191 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
1da177e4 LT |
15192 | goto err_out_disable_pdev; |
15193 | } | |
15194 | ||
15195 | pci_set_master(pdev); | |
15196 | ||
15197 | /* Find power-management capability. */ | |
15198 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
15199 | if (pm_cap == 0) { | |
2445e461 MC |
15200 | dev_err(&pdev->dev, |
15201 | "Cannot find Power Management capability, aborting\n"); | |
1da177e4 LT |
15202 | err = -EIO; |
15203 | goto err_out_free_res; | |
15204 | } | |
15205 | ||
16821285 MC |
15206 | err = pci_set_power_state(pdev, PCI_D0); |
15207 | if (err) { | |
15208 | dev_err(&pdev->dev, "Transition to D0 failed, aborting\n"); | |
15209 | goto err_out_free_res; | |
15210 | } | |
15211 | ||
fe5f5787 | 15212 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); |
1da177e4 | 15213 | if (!dev) { |
2445e461 | 15214 | dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n"); |
1da177e4 | 15215 | err = -ENOMEM; |
16821285 | 15216 | goto err_out_power_down; |
1da177e4 LT |
15217 | } |
15218 | ||
1da177e4 LT |
15219 | SET_NETDEV_DEV(dev, &pdev->dev); |
15220 | ||
1da177e4 LT |
15221 | tp = netdev_priv(dev); |
15222 | tp->pdev = pdev; | |
15223 | tp->dev = dev; | |
15224 | tp->pm_cap = pm_cap; | |
1da177e4 LT |
15225 | tp->rx_mode = TG3_DEF_RX_MODE; |
15226 | tp->tx_mode = TG3_DEF_TX_MODE; | |
8ef21428 | 15227 | |
1da177e4 LT |
15228 | if (tg3_debug > 0) |
15229 | tp->msg_enable = tg3_debug; | |
15230 | else | |
15231 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
15232 | ||
15233 | /* The word/byte swap controls here control register access byte | |
15234 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
15235 | * setting below. | |
15236 | */ | |
15237 | tp->misc_host_ctrl = | |
15238 | MISC_HOST_CTRL_MASK_PCI_INT | | |
15239 | MISC_HOST_CTRL_WORD_SWAP | | |
15240 | MISC_HOST_CTRL_INDIR_ACCESS | | |
15241 | MISC_HOST_CTRL_PCISTATE_RW; | |
15242 | ||
15243 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
15244 | * on descriptor entries, anything which isn't packet data. | |
15245 | * | |
15246 | * The StrongARM chips on the board (one for tx, one for rx) | |
15247 | * are running in big-endian mode. | |
15248 | */ | |
15249 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
15250 | GRC_MODE_WSWAP_NONFRM_DATA); | |
15251 | #ifdef __BIG_ENDIAN | |
15252 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
15253 | #endif | |
15254 | spin_lock_init(&tp->lock); | |
1da177e4 | 15255 | spin_lock_init(&tp->indirect_lock); |
c4028958 | 15256 | INIT_WORK(&tp->reset_task, tg3_reset_task); |
1da177e4 | 15257 | |
d5fe488a | 15258 | tp->regs = pci_ioremap_bar(pdev, BAR_0); |
ab0049b4 | 15259 | if (!tp->regs) { |
ab96b241 | 15260 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); |
1da177e4 LT |
15261 | err = -ENOMEM; |
15262 | goto err_out_free_dev; | |
15263 | } | |
15264 | ||
c9cab24e MC |
15265 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
15266 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || | |
15267 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || | |
15268 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || | |
15269 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || | |
15270 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
15271 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || | |
15272 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) { | |
15273 | tg3_flag_set(tp, ENABLE_APE); | |
15274 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); | |
15275 | if (!tp->aperegs) { | |
15276 | dev_err(&pdev->dev, | |
15277 | "Cannot map APE registers, aborting\n"); | |
15278 | err = -ENOMEM; | |
15279 | goto err_out_iounmap; | |
15280 | } | |
15281 | } | |
15282 | ||
1da177e4 LT |
15283 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; |
15284 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
1da177e4 | 15285 | |
1da177e4 | 15286 | dev->ethtool_ops = &tg3_ethtool_ops; |
1da177e4 | 15287 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
2ffcc981 | 15288 | dev->netdev_ops = &tg3_netdev_ops; |
1da177e4 | 15289 | dev->irq = pdev->irq; |
1da177e4 LT |
15290 | |
15291 | err = tg3_get_invariants(tp); | |
15292 | if (err) { | |
ab96b241 MC |
15293 | dev_err(&pdev->dev, |
15294 | "Problem fetching invariants of chip, aborting\n"); | |
c9cab24e | 15295 | goto err_out_apeunmap; |
1da177e4 LT |
15296 | } |
15297 | ||
4a29cc2e MC |
15298 | /* The EPB bridge inside 5714, 5715, and 5780 and any |
15299 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
72f2afb8 MC |
15300 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. |
15301 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
15302 | * do DMA address check in tg3_start_xmit(). | |
15303 | */ | |
63c3a66f | 15304 | if (tg3_flag(tp, IS_5788)) |
284901a9 | 15305 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); |
63c3a66f | 15306 | else if (tg3_flag(tp, 40BIT_DMA_BUG)) { |
50cf156a | 15307 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
72f2afb8 | 15308 | #ifdef CONFIG_HIGHMEM |
6a35528a | 15309 | dma_mask = DMA_BIT_MASK(64); |
72f2afb8 | 15310 | #endif |
4a29cc2e | 15311 | } else |
6a35528a | 15312 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
72f2afb8 MC |
15313 | |
15314 | /* Configure DMA attributes. */ | |
284901a9 | 15315 | if (dma_mask > DMA_BIT_MASK(32)) { |
72f2afb8 MC |
15316 | err = pci_set_dma_mask(pdev, dma_mask); |
15317 | if (!err) { | |
0da0606f | 15318 | features |= NETIF_F_HIGHDMA; |
72f2afb8 MC |
15319 | err = pci_set_consistent_dma_mask(pdev, |
15320 | persist_dma_mask); | |
15321 | if (err < 0) { | |
ab96b241 MC |
15322 | dev_err(&pdev->dev, "Unable to obtain 64 bit " |
15323 | "DMA for consistent allocations\n"); | |
c9cab24e | 15324 | goto err_out_apeunmap; |
72f2afb8 MC |
15325 | } |
15326 | } | |
15327 | } | |
284901a9 YH |
15328 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
15329 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
72f2afb8 | 15330 | if (err) { |
ab96b241 MC |
15331 | dev_err(&pdev->dev, |
15332 | "No usable DMA configuration, aborting\n"); | |
c9cab24e | 15333 | goto err_out_apeunmap; |
72f2afb8 MC |
15334 | } |
15335 | } | |
15336 | ||
fdfec172 | 15337 | tg3_init_bufmgr_config(tp); |
1da177e4 | 15338 | |
0da0606f MC |
15339 | features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
15340 | ||
15341 | /* 5700 B0 chips do not support checksumming correctly due | |
15342 | * to hardware bugs. | |
15343 | */ | |
15344 | if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) { | |
15345 | features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; | |
15346 | ||
15347 | if (tg3_flag(tp, 5755_PLUS)) | |
15348 | features |= NETIF_F_IPV6_CSUM; | |
15349 | } | |
15350 | ||
4e3a7aaa MC |
15351 | /* TSO is on by default on chips that support hardware TSO. |
15352 | * Firmware TSO on older chips gives lower performance, so it | |
15353 | * is off by default, but can be enabled using ethtool. | |
15354 | */ | |
63c3a66f JP |
15355 | if ((tg3_flag(tp, HW_TSO_1) || |
15356 | tg3_flag(tp, HW_TSO_2) || | |
15357 | tg3_flag(tp, HW_TSO_3)) && | |
0da0606f MC |
15358 | (features & NETIF_F_IP_CSUM)) |
15359 | features |= NETIF_F_TSO; | |
63c3a66f | 15360 | if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { |
0da0606f MC |
15361 | if (features & NETIF_F_IPV6_CSUM) |
15362 | features |= NETIF_F_TSO6; | |
63c3a66f | 15363 | if (tg3_flag(tp, HW_TSO_3) || |
e849cdc3 | 15364 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c MC |
15365 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
15366 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
63c3a66f | 15367 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
dc668910 | 15368 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
0da0606f | 15369 | features |= NETIF_F_TSO_ECN; |
b0026624 | 15370 | } |
1da177e4 | 15371 | |
d542fe27 MC |
15372 | dev->features |= features; |
15373 | dev->vlan_features |= features; | |
15374 | ||
06c03c02 MB |
15375 | /* |
15376 | * Add loopback capability only for a subset of devices that support | |
15377 | * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY | |
15378 | * loopback for the remaining devices. | |
15379 | */ | |
15380 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | |
15381 | !tg3_flag(tp, CPMU_PRESENT)) | |
15382 | /* Add the loopback capability */ | |
0da0606f MC |
15383 | features |= NETIF_F_LOOPBACK; |
15384 | ||
0da0606f | 15385 | dev->hw_features |= features; |
06c03c02 | 15386 | |
1da177e4 | 15387 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && |
63c3a66f | 15388 | !tg3_flag(tp, TSO_CAPABLE) && |
1da177e4 | 15389 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { |
63c3a66f | 15390 | tg3_flag_set(tp, MAX_RXPEND_64); |
1da177e4 LT |
15391 | tp->rx_pending = 63; |
15392 | } | |
15393 | ||
1da177e4 LT |
15394 | err = tg3_get_device_address(tp); |
15395 | if (err) { | |
ab96b241 MC |
15396 | dev_err(&pdev->dev, |
15397 | "Could not obtain valid ethernet address, aborting\n"); | |
c9cab24e | 15398 | goto err_out_apeunmap; |
c88864df MC |
15399 | } |
15400 | ||
1da177e4 LT |
15401 | /* |
15402 | * Reset chip in case UNDI or EFI driver did not shutdown | |
15403 | * DMA self test will enable WDMAC and we'll see (spurious) | |
15404 | * pending DMA on the PCI bus at that point. | |
15405 | */ | |
15406 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
15407 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
1da177e4 | 15408 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); |
944d980e | 15409 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
15410 | } |
15411 | ||
15412 | err = tg3_test_dma(tp); | |
15413 | if (err) { | |
ab96b241 | 15414 | dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); |
c88864df | 15415 | goto err_out_apeunmap; |
1da177e4 LT |
15416 | } |
15417 | ||
78f90dcf MC |
15418 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
15419 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | |
15420 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
6fd45cb8 | 15421 | for (i = 0; i < tp->irq_max; i++) { |
78f90dcf MC |
15422 | struct tg3_napi *tnapi = &tp->napi[i]; |
15423 | ||
15424 | tnapi->tp = tp; | |
15425 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; | |
15426 | ||
15427 | tnapi->int_mbox = intmbx; | |
15428 | if (i < 4) | |
15429 | intmbx += 0x8; | |
15430 | else | |
15431 | intmbx += 0x4; | |
15432 | ||
15433 | tnapi->consmbox = rcvmbx; | |
15434 | tnapi->prodmbox = sndmbx; | |
15435 | ||
66cfd1bd | 15436 | if (i) |
78f90dcf | 15437 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); |
66cfd1bd | 15438 | else |
78f90dcf | 15439 | tnapi->coal_now = HOSTCC_MODE_NOW; |
78f90dcf | 15440 | |
63c3a66f | 15441 | if (!tg3_flag(tp, SUPPORT_MSIX)) |
78f90dcf MC |
15442 | break; |
15443 | ||
15444 | /* | |
15445 | * If we support MSIX, we'll be using RSS. If we're using | |
15446 | * RSS, the first vector only handles link interrupts and the | |
15447 | * remaining vectors handle rx and tx interrupts. Reuse the | |
15448 | * mailbox values for the next iteration. The values we setup | |
15449 | * above are still useful for the single vectored mode. | |
15450 | */ | |
15451 | if (!i) | |
15452 | continue; | |
15453 | ||
15454 | rcvmbx += 0x8; | |
15455 | ||
15456 | if (sndmbx & 0x4) | |
15457 | sndmbx -= 0x4; | |
15458 | else | |
15459 | sndmbx += 0xc; | |
15460 | } | |
15461 | ||
15f9850d DM |
15462 | tg3_init_coal(tp); |
15463 | ||
c49a1561 MC |
15464 | pci_set_drvdata(pdev, dev); |
15465 | ||
cd0d7228 MC |
15466 | if (tg3_flag(tp, 5717_PLUS)) { |
15467 | /* Resume a low-power mode */ | |
15468 | tg3_frob_aux_power(tp, false); | |
15469 | } | |
15470 | ||
1da177e4 LT |
15471 | err = register_netdev(dev); |
15472 | if (err) { | |
ab96b241 | 15473 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); |
0d3031d9 | 15474 | goto err_out_apeunmap; |
1da177e4 LT |
15475 | } |
15476 | ||
05dbe005 JP |
15477 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
15478 | tp->board_part_number, | |
15479 | tp->pci_chip_rev_id, | |
15480 | tg3_bus_string(tp, str), | |
15481 | dev->dev_addr); | |
1da177e4 | 15482 | |
f07e9af3 | 15483 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 MC |
15484 | struct phy_device *phydev; |
15485 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
5129c3a3 MC |
15486 | netdev_info(dev, |
15487 | "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
05dbe005 | 15488 | phydev->drv->name, dev_name(&phydev->dev)); |
f07e9af3 MC |
15489 | } else { |
15490 | char *ethtype; | |
15491 | ||
15492 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
15493 | ethtype = "10/100Base-TX"; | |
15494 | else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | |
15495 | ethtype = "1000Base-SX"; | |
15496 | else | |
15497 | ethtype = "10/100/1000Base-T"; | |
15498 | ||
5129c3a3 | 15499 | netdev_info(dev, "attached PHY is %s (%s Ethernet) " |
47007831 MC |
15500 | "(WireSpeed[%d], EEE[%d])\n", |
15501 | tg3_phy_string(tp), ethtype, | |
15502 | (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, | |
15503 | (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); | |
f07e9af3 | 15504 | } |
05dbe005 JP |
15505 | |
15506 | netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
dc668910 | 15507 | (dev->features & NETIF_F_RXCSUM) != 0, |
63c3a66f | 15508 | tg3_flag(tp, USE_LINKCHG_REG) != 0, |
f07e9af3 | 15509 | (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, |
63c3a66f JP |
15510 | tg3_flag(tp, ENABLE_ASF) != 0, |
15511 | tg3_flag(tp, TSO_CAPABLE) != 0); | |
05dbe005 JP |
15512 | netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", |
15513 | tp->dma_rwctrl, | |
15514 | pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : | |
15515 | ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); | |
1da177e4 | 15516 | |
b45aa2f6 MC |
15517 | pci_save_state(pdev); |
15518 | ||
1da177e4 LT |
15519 | return 0; |
15520 | ||
0d3031d9 MC |
15521 | err_out_apeunmap: |
15522 | if (tp->aperegs) { | |
15523 | iounmap(tp->aperegs); | |
15524 | tp->aperegs = NULL; | |
15525 | } | |
15526 | ||
1da177e4 | 15527 | err_out_iounmap: |
6892914f MC |
15528 | if (tp->regs) { |
15529 | iounmap(tp->regs); | |
22abe310 | 15530 | tp->regs = NULL; |
6892914f | 15531 | } |
1da177e4 LT |
15532 | |
15533 | err_out_free_dev: | |
15534 | free_netdev(dev); | |
15535 | ||
16821285 MC |
15536 | err_out_power_down: |
15537 | pci_set_power_state(pdev, PCI_D3hot); | |
15538 | ||
1da177e4 LT |
15539 | err_out_free_res: |
15540 | pci_release_regions(pdev); | |
15541 | ||
15542 | err_out_disable_pdev: | |
15543 | pci_disable_device(pdev); | |
15544 | pci_set_drvdata(pdev, NULL); | |
15545 | return err; | |
15546 | } | |
15547 | ||
15548 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
15549 | { | |
15550 | struct net_device *dev = pci_get_drvdata(pdev); | |
15551 | ||
15552 | if (dev) { | |
15553 | struct tg3 *tp = netdev_priv(dev); | |
15554 | ||
077f849d JSR |
15555 | if (tp->fw) |
15556 | release_firmware(tp->fw); | |
15557 | ||
23f333a2 | 15558 | cancel_work_sync(&tp->reset_task); |
158d7abd | 15559 | |
63c3a66f | 15560 | if (!tg3_flag(tp, USE_PHYLIB)) { |
b02fd9e3 | 15561 | tg3_phy_fini(tp); |
158d7abd | 15562 | tg3_mdio_fini(tp); |
b02fd9e3 | 15563 | } |
158d7abd | 15564 | |
1da177e4 | 15565 | unregister_netdev(dev); |
0d3031d9 MC |
15566 | if (tp->aperegs) { |
15567 | iounmap(tp->aperegs); | |
15568 | tp->aperegs = NULL; | |
15569 | } | |
6892914f MC |
15570 | if (tp->regs) { |
15571 | iounmap(tp->regs); | |
22abe310 | 15572 | tp->regs = NULL; |
6892914f | 15573 | } |
1da177e4 LT |
15574 | free_netdev(dev); |
15575 | pci_release_regions(pdev); | |
15576 | pci_disable_device(pdev); | |
15577 | pci_set_drvdata(pdev, NULL); | |
15578 | } | |
15579 | } | |
15580 | ||
aa6027ca | 15581 | #ifdef CONFIG_PM_SLEEP |
c866b7ea | 15582 | static int tg3_suspend(struct device *device) |
1da177e4 | 15583 | { |
c866b7ea | 15584 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15585 | struct net_device *dev = pci_get_drvdata(pdev); |
15586 | struct tg3 *tp = netdev_priv(dev); | |
15587 | int err; | |
15588 | ||
15589 | if (!netif_running(dev)) | |
15590 | return 0; | |
15591 | ||
23f333a2 | 15592 | flush_work_sync(&tp->reset_task); |
b02fd9e3 | 15593 | tg3_phy_stop(tp); |
1da177e4 LT |
15594 | tg3_netif_stop(tp); |
15595 | ||
15596 | del_timer_sync(&tp->timer); | |
15597 | ||
f47c11ee | 15598 | tg3_full_lock(tp, 1); |
1da177e4 | 15599 | tg3_disable_ints(tp); |
f47c11ee | 15600 | tg3_full_unlock(tp); |
1da177e4 LT |
15601 | |
15602 | netif_device_detach(dev); | |
15603 | ||
f47c11ee | 15604 | tg3_full_lock(tp, 0); |
944d980e | 15605 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
63c3a66f | 15606 | tg3_flag_clear(tp, INIT_COMPLETE); |
f47c11ee | 15607 | tg3_full_unlock(tp); |
1da177e4 | 15608 | |
c866b7ea | 15609 | err = tg3_power_down_prepare(tp); |
1da177e4 | 15610 | if (err) { |
b02fd9e3 MC |
15611 | int err2; |
15612 | ||
f47c11ee | 15613 | tg3_full_lock(tp, 0); |
1da177e4 | 15614 | |
63c3a66f | 15615 | tg3_flag_set(tp, INIT_COMPLETE); |
b02fd9e3 MC |
15616 | err2 = tg3_restart_hw(tp, 1); |
15617 | if (err2) | |
b9ec6c1b | 15618 | goto out; |
1da177e4 LT |
15619 | |
15620 | tp->timer.expires = jiffies + tp->timer_offset; | |
15621 | add_timer(&tp->timer); | |
15622 | ||
15623 | netif_device_attach(dev); | |
15624 | tg3_netif_start(tp); | |
15625 | ||
b9ec6c1b | 15626 | out: |
f47c11ee | 15627 | tg3_full_unlock(tp); |
b02fd9e3 MC |
15628 | |
15629 | if (!err2) | |
15630 | tg3_phy_start(tp); | |
1da177e4 LT |
15631 | } |
15632 | ||
15633 | return err; | |
15634 | } | |
15635 | ||
c866b7ea | 15636 | static int tg3_resume(struct device *device) |
1da177e4 | 15637 | { |
c866b7ea | 15638 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15639 | struct net_device *dev = pci_get_drvdata(pdev); |
15640 | struct tg3 *tp = netdev_priv(dev); | |
15641 | int err; | |
15642 | ||
15643 | if (!netif_running(dev)) | |
15644 | return 0; | |
15645 | ||
1da177e4 LT |
15646 | netif_device_attach(dev); |
15647 | ||
f47c11ee | 15648 | tg3_full_lock(tp, 0); |
1da177e4 | 15649 | |
63c3a66f | 15650 | tg3_flag_set(tp, INIT_COMPLETE); |
b9ec6c1b MC |
15651 | err = tg3_restart_hw(tp, 1); |
15652 | if (err) | |
15653 | goto out; | |
1da177e4 LT |
15654 | |
15655 | tp->timer.expires = jiffies + tp->timer_offset; | |
15656 | add_timer(&tp->timer); | |
15657 | ||
1da177e4 LT |
15658 | tg3_netif_start(tp); |
15659 | ||
b9ec6c1b | 15660 | out: |
f47c11ee | 15661 | tg3_full_unlock(tp); |
1da177e4 | 15662 | |
b02fd9e3 MC |
15663 | if (!err) |
15664 | tg3_phy_start(tp); | |
15665 | ||
b9ec6c1b | 15666 | return err; |
1da177e4 LT |
15667 | } |
15668 | ||
c866b7ea | 15669 | static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); |
aa6027ca ED |
15670 | #define TG3_PM_OPS (&tg3_pm_ops) |
15671 | ||
15672 | #else | |
15673 | ||
15674 | #define TG3_PM_OPS NULL | |
15675 | ||
15676 | #endif /* CONFIG_PM_SLEEP */ | |
c866b7ea | 15677 | |
b45aa2f6 MC |
15678 | /** |
15679 | * tg3_io_error_detected - called when PCI error is detected | |
15680 | * @pdev: Pointer to PCI device | |
15681 | * @state: The current pci connection state | |
15682 | * | |
15683 | * This function is called after a PCI bus error affecting | |
15684 | * this device has been detected. | |
15685 | */ | |
15686 | static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev, | |
15687 | pci_channel_state_t state) | |
15688 | { | |
15689 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15690 | struct tg3 *tp = netdev_priv(netdev); | |
15691 | pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET; | |
15692 | ||
15693 | netdev_info(netdev, "PCI I/O error detected\n"); | |
15694 | ||
15695 | rtnl_lock(); | |
15696 | ||
15697 | if (!netif_running(netdev)) | |
15698 | goto done; | |
15699 | ||
15700 | tg3_phy_stop(tp); | |
15701 | ||
15702 | tg3_netif_stop(tp); | |
15703 | ||
15704 | del_timer_sync(&tp->timer); | |
63c3a66f | 15705 | tg3_flag_clear(tp, RESTART_TIMER); |
b45aa2f6 MC |
15706 | |
15707 | /* Want to make sure that the reset task doesn't run */ | |
15708 | cancel_work_sync(&tp->reset_task); | |
63c3a66f JP |
15709 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); |
15710 | tg3_flag_clear(tp, RESTART_TIMER); | |
b45aa2f6 MC |
15711 | |
15712 | netif_device_detach(netdev); | |
15713 | ||
15714 | /* Clean up software state, even if MMIO is blocked */ | |
15715 | tg3_full_lock(tp, 0); | |
15716 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | |
15717 | tg3_full_unlock(tp); | |
15718 | ||
15719 | done: | |
15720 | if (state == pci_channel_io_perm_failure) | |
15721 | err = PCI_ERS_RESULT_DISCONNECT; | |
15722 | else | |
15723 | pci_disable_device(pdev); | |
15724 | ||
15725 | rtnl_unlock(); | |
15726 | ||
15727 | return err; | |
15728 | } | |
15729 | ||
15730 | /** | |
15731 | * tg3_io_slot_reset - called after the pci bus has been reset. | |
15732 | * @pdev: Pointer to PCI device | |
15733 | * | |
15734 | * Restart the card from scratch, as if from a cold-boot. | |
15735 | * At this point, the card has exprienced a hard reset, | |
15736 | * followed by fixups by BIOS, and has its config space | |
15737 | * set up identically to what it was at cold boot. | |
15738 | */ | |
15739 | static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev) | |
15740 | { | |
15741 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15742 | struct tg3 *tp = netdev_priv(netdev); | |
15743 | pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT; | |
15744 | int err; | |
15745 | ||
15746 | rtnl_lock(); | |
15747 | ||
15748 | if (pci_enable_device(pdev)) { | |
15749 | netdev_err(netdev, "Cannot re-enable PCI device after reset.\n"); | |
15750 | goto done; | |
15751 | } | |
15752 | ||
15753 | pci_set_master(pdev); | |
15754 | pci_restore_state(pdev); | |
15755 | pci_save_state(pdev); | |
15756 | ||
15757 | if (!netif_running(netdev)) { | |
15758 | rc = PCI_ERS_RESULT_RECOVERED; | |
15759 | goto done; | |
15760 | } | |
15761 | ||
15762 | err = tg3_power_up(tp); | |
bed9829f | 15763 | if (err) |
b45aa2f6 | 15764 | goto done; |
b45aa2f6 MC |
15765 | |
15766 | rc = PCI_ERS_RESULT_RECOVERED; | |
15767 | ||
15768 | done: | |
15769 | rtnl_unlock(); | |
15770 | ||
15771 | return rc; | |
15772 | } | |
15773 | ||
15774 | /** | |
15775 | * tg3_io_resume - called when traffic can start flowing again. | |
15776 | * @pdev: Pointer to PCI device | |
15777 | * | |
15778 | * This callback is called when the error recovery driver tells | |
15779 | * us that its OK to resume normal operation. | |
15780 | */ | |
15781 | static void tg3_io_resume(struct pci_dev *pdev) | |
15782 | { | |
15783 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15784 | struct tg3 *tp = netdev_priv(netdev); | |
15785 | int err; | |
15786 | ||
15787 | rtnl_lock(); | |
15788 | ||
15789 | if (!netif_running(netdev)) | |
15790 | goto done; | |
15791 | ||
15792 | tg3_full_lock(tp, 0); | |
63c3a66f | 15793 | tg3_flag_set(tp, INIT_COMPLETE); |
b45aa2f6 MC |
15794 | err = tg3_restart_hw(tp, 1); |
15795 | tg3_full_unlock(tp); | |
15796 | if (err) { | |
15797 | netdev_err(netdev, "Cannot restart hardware after reset.\n"); | |
15798 | goto done; | |
15799 | } | |
15800 | ||
15801 | netif_device_attach(netdev); | |
15802 | ||
15803 | tp->timer.expires = jiffies + tp->timer_offset; | |
15804 | add_timer(&tp->timer); | |
15805 | ||
15806 | tg3_netif_start(tp); | |
15807 | ||
15808 | tg3_phy_start(tp); | |
15809 | ||
15810 | done: | |
15811 | rtnl_unlock(); | |
15812 | } | |
15813 | ||
15814 | static struct pci_error_handlers tg3_err_handler = { | |
15815 | .error_detected = tg3_io_error_detected, | |
15816 | .slot_reset = tg3_io_slot_reset, | |
15817 | .resume = tg3_io_resume | |
15818 | }; | |
15819 | ||
1da177e4 LT |
15820 | static struct pci_driver tg3_driver = { |
15821 | .name = DRV_MODULE_NAME, | |
15822 | .id_table = tg3_pci_tbl, | |
15823 | .probe = tg3_init_one, | |
15824 | .remove = __devexit_p(tg3_remove_one), | |
b45aa2f6 | 15825 | .err_handler = &tg3_err_handler, |
aa6027ca | 15826 | .driver.pm = TG3_PM_OPS, |
1da177e4 LT |
15827 | }; |
15828 | ||
15829 | static int __init tg3_init(void) | |
15830 | { | |
29917620 | 15831 | return pci_register_driver(&tg3_driver); |
1da177e4 LT |
15832 | } |
15833 | ||
15834 | static void __exit tg3_cleanup(void) | |
15835 | { | |
15836 | pci_unregister_driver(&tg3_driver); | |
15837 | } | |
15838 | ||
15839 | module_init(tg3_init); | |
15840 | module_exit(tg3_cleanup); |