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p8022.h: Remove extern from function prototypes
[deliverable/linux.git] / drivers / net / ethernet / broadcom / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
b681b65d 7 * Copyright (C) 2005-2013 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
6867c843 21#include <linux/stringify.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
14c85021 27#include <linux/in.h>
1da177e4 28#include <linux/init.h>
a6b7a407 29#include <linux/interrupt.h>
1da177e4
LT		 30#include <linux/ioport.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/ethtool.h>
3110f5f5 36#include <linux/mdio.h>
1da177e4 37#include <linux/mii.h>
158d7abd 38#include <linux/phy.h>
a9daf367 39#include <linux/brcmphy.h>
1da177e4
LT		 40#include <linux/if_vlan.h>
41#include <linux/ip.h>
42#include <linux/tcp.h>
43#include <linux/workqueue.h>
61487480 44#include <linux/prefetch.h>
f9a5f7d3 45#include <linux/dma-mapping.h>
077f849d 46#include <linux/firmware.h>
7e6c63f0 47#include <linux/ssb/ssb_driver_gige.h>
aed93e0b
MC		 48#include <linux/hwmon.h>
49#include <linux/hwmon-sysfs.h>
1da177e4
LT		 50
51#include <net/checksum.h>
c9bdd4b5 52#include <net/ip.h>
1da177e4 53
27fd9de8 54#include <linux/io.h>
1da177e4 55#include <asm/byteorder.h>
27fd9de8 56#include <linux/uaccess.h>
1da177e4 57
be947307
MC		 58#include <uapi/linux/net_tstamp.h>
59#include <linux/ptp_clock_kernel.h>
60
49b6e95f 61#ifdef CONFIG_SPARC
1da177e4 62#include <asm/idprom.h>
49b6e95f 63#include <asm/prom.h>
1da177e4
LT		 64#endif
65
63532394
MC		 66#define BAR_0 0
67#define BAR_2 2
68
1da177e4
LT		 69#include "tg3.h"
70
63c3a66f
JP		 71/* Functions & macros to verify TG3_FLAGS types */
72
73static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
74{
75 return test_bit(flag, bits);
76}
77
78static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
79{
80 set_bit(flag, bits);
81}
82
83static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
84{
85 clear_bit(flag, bits);
86}
87
88#define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90#define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92#define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
94
1da177e4 95#define DRV_MODULE_NAME "tg3"
6867c843 96#define TG3_MAJ_NUM 3
cd77b2eb 97#define TG3_MIN_NUM 133
6867c843
MC		 98#define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
cd77b2eb 100#define DRV_MODULE_RELDATE "Jul 29, 2013"
1da177e4 101
fd6d3f0e
MC		 102#define RESET_KIND_SHUTDOWN 0
103#define RESET_KIND_INIT 1
104#define RESET_KIND_SUSPEND 2
105
1da177e4
LT		 106#define TG3_DEF_RX_MODE 0
107#define TG3_DEF_TX_MODE 0
108#define TG3_DEF_MSG_ENABLE \
109 (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK | \
112 NETIF_MSG_TIMER | \
113 NETIF_MSG_IFDOWN | \
114 NETIF_MSG_IFUP | \
115 NETIF_MSG_RX_ERR | \
116 NETIF_MSG_TX_ERR)
117
520b2756
MC		 118#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
119
1da177e4
LT		 120/* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
122 */
63c3a66f 123
1da177e4
LT		 124#define TG3_TX_TIMEOUT (5 * HZ)
125
126/* hardware minimum and maximum for a single frame's data payload */
127#define TG3_MIN_MTU 60
128#define TG3_MAX_MTU(tp) \
63c3a66f 129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 130
131/* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
134 */
7cb32cf2 135#define TG3_RX_STD_RING_SIZE(tp) \
63c3a66f 136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
1da177e4 138#define TG3_DEF_RX_RING_PENDING 200
7cb32cf2 139#define TG3_RX_JMB_RING_SIZE(tp) \
63c3a66f 140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
1da177e4
LT		 142#define TG3_DEF_RX_JUMBO_RING_PENDING 100
143
144/* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
149 */
1da177e4
LT		 150
151#define TG3_TX_RING_SIZE 512
152#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
153
2c49a44d
MC		 154#define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156#define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158#define TG3_RX_RCB_RING_BYTES(tp) \
7cb32cf2 159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
1da177e4
LT		 160#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
161 TG3_TX_RING_SIZE)
1da177e4
LT		 162#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
163
287be12e
MC		 164#define TG3_DMA_BYTE_ENAB 64
165
166#define TG3_RX_STD_DMA_SZ 1536
167#define TG3_RX_JMB_DMA_SZ 9046
168
169#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
170
171#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 173
2c49a44d
MC		 174#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
2b2cdb65 176
2c49a44d
MC		 177#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
2b2cdb65 179
d2757fc4
MC		 180/* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
184 *
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
190 */
191#define TG3_RX_COPY_THRESHOLD 256
192#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
194#else
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
196#endif
197
81389f57
MC		 198#if (NET_IP_ALIGN != 0)
199#define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
200#else
9205fd9c 201#define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
81389f57
MC		 202#endif
203
1da177e4 204/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 205#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
55086ad9 206#define TG3_TX_BD_DMA_MAX_2K 2048
a4cb428d 207#define TG3_TX_BD_DMA_MAX_4K 4096
1da177e4 208
ad829268
MC		 209#define TG3_RAW_IP_ALIGN 2
210
c6cdf436 211#define TG3_FW_UPDATE_TIMEOUT_SEC 5
21f7638e 212#define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
c6cdf436 213
077f849d 214#define FIRMWARE_TG3 "tigon/tg3.bin"
c4dab506 215#define FIRMWARE_TG357766 "tigon/tg357766.bin"
077f849d
JSR		 216#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
217#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
218
229b1ad1 219static char version[] =
05dbe005 220 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 221
222MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
223MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
224MODULE_LICENSE("GPL");
225MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 226MODULE_FIRMWARE(FIRMWARE_TG3);
227MODULE_FIRMWARE(FIRMWARE_TG3TSO);
228MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
229
1da177e4
LT		 230static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
231module_param(tg3_debug, int, 0);
232MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
233
3d567e0e
NNS		 234#define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
235#define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
236
a3aa1884 237static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
3d567e0e
NNS		 256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
257 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
258 TG3_DRV_DATA_FLAG_5705_10_100},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
3d567e0e
NNS		 263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
264 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
265 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
7e6c63f0 268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
13185217 269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
13185217 270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
3d567e0e
NNS		 271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
272 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
3d567e0e
NNS		 277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
278 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
3d567e0e
NNS		 286 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
287 PCI_VENDOR_ID_LENOVO,
288 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
289 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217 290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
3d567e0e
NNS		 291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
3d567e0e
NNS		 311 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
312 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
313 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321d32a0
MC		 317 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
318 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
3d567e0e
NNS		 319 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
320 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
5e7ccf20 321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6 322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
79d49695 323 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
5001e2f6 324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
b0f75221
MC		 325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
3d567e0e
NNS		 329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
330 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
332 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
302b500b 333 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
ba1f3c76 334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
02eca3f5 335 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
d3f677af 336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
c86a8560
MC		 337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
13185217
HK		 340 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
341 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
342 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
343 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
344 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
345 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
346 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
1dcb14d9 347 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
13185217 348 {}
1da177e4
LT		 349};
350
351MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
352
50da859d 353static const struct {
1da177e4 354 const char string[ETH_GSTRING_LEN];
48fa55a0 355} ethtool_stats_keys[] = {
1da177e4
LT		 356 { "rx_octets" },
357 { "rx_fragments" },
358 { "rx_ucast_packets" },
359 { "rx_mcast_packets" },
360 { "rx_bcast_packets" },
361 { "rx_fcs_errors" },
362 { "rx_align_errors" },
363 { "rx_xon_pause_rcvd" },
364 { "rx_xoff_pause_rcvd" },
365 { "rx_mac_ctrl_rcvd" },
366 { "rx_xoff_entered" },
367 { "rx_frame_too_long_errors" },
368 { "rx_jabbers" },
369 { "rx_undersize_packets" },
370 { "rx_in_length_errors" },
371 { "rx_out_length_errors" },
372 { "rx_64_or_less_octet_packets" },
373 { "rx_65_to_127_octet_packets" },
374 { "rx_128_to_255_octet_packets" },
375 { "rx_256_to_511_octet_packets" },
376 { "rx_512_to_1023_octet_packets" },
377 { "rx_1024_to_1522_octet_packets" },
378 { "rx_1523_to_2047_octet_packets" },
379 { "rx_2048_to_4095_octet_packets" },
380 { "rx_4096_to_8191_octet_packets" },
381 { "rx_8192_to_9022_octet_packets" },
382
383 { "tx_octets" },
384 { "tx_collisions" },
385
386 { "tx_xon_sent" },
387 { "tx_xoff_sent" },
388 { "tx_flow_control" },
389 { "tx_mac_errors" },
390 { "tx_single_collisions" },
391 { "tx_mult_collisions" },
392 { "tx_deferred" },
393 { "tx_excessive_collisions" },
394 { "tx_late_collisions" },
395 { "tx_collide_2times" },
396 { "tx_collide_3times" },
397 { "tx_collide_4times" },
398 { "tx_collide_5times" },
399 { "tx_collide_6times" },
400 { "tx_collide_7times" },
401 { "tx_collide_8times" },
402 { "tx_collide_9times" },
403 { "tx_collide_10times" },
404 { "tx_collide_11times" },
405 { "tx_collide_12times" },
406 { "tx_collide_13times" },
407 { "tx_collide_14times" },
408 { "tx_collide_15times" },
409 { "tx_ucast_packets" },
410 { "tx_mcast_packets" },
411 { "tx_bcast_packets" },
412 { "tx_carrier_sense_errors" },
413 { "tx_discards" },
414 { "tx_errors" },
415
416 { "dma_writeq_full" },
417 { "dma_write_prioq_full" },
418 { "rxbds_empty" },
419 { "rx_discards" },
420 { "rx_errors" },
421 { "rx_threshold_hit" },
422
423 { "dma_readq_full" },
424 { "dma_read_prioq_full" },
425 { "tx_comp_queue_full" },
426
427 { "ring_set_send_prod_index" },
428 { "ring_status_update" },
429 { "nic_irqs" },
430 { "nic_avoided_irqs" },
4452d099
MC		 431 { "nic_tx_threshold_hit" },
432
433 { "mbuf_lwm_thresh_hit" },
1da177e4
LT		 434};
435
48fa55a0 436#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
93df8b8f
NNS		 437#define TG3_NVRAM_TEST 0
438#define TG3_LINK_TEST 1
439#define TG3_REGISTER_TEST 2
440#define TG3_MEMORY_TEST 3
441#define TG3_MAC_LOOPB_TEST 4
442#define TG3_PHY_LOOPB_TEST 5
443#define TG3_EXT_LOOPB_TEST 6
444#define TG3_INTERRUPT_TEST 7
48fa55a0
MC		 445
446
50da859d 447static const struct {
4cafd3f5 448 const char string[ETH_GSTRING_LEN];
48fa55a0 449} ethtool_test_keys[] = {
93df8b8f
NNS		 450 [TG3_NVRAM_TEST] = { "nvram test (online) " },
451 [TG3_LINK_TEST] = { "link test (online) " },
452 [TG3_REGISTER_TEST] = { "register test (offline)" },
453 [TG3_MEMORY_TEST] = { "memory test (offline)" },
454 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
455 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
456 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
457 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
4cafd3f5
MC		 458};
459
48fa55a0
MC		 460#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
461
462
b401e9e2
MC		 463static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
464{
465 writel(val, tp->regs + off);
466}
467
468static u32 tg3_read32(struct tg3 *tp, u32 off)
469{
de6f31eb 470 return readl(tp->regs + off);
b401e9e2
MC		 471}
472
0d3031d9
MC		 473static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
474{
475 writel(val, tp->aperegs + off);
476}
477
478static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
479{
de6f31eb 480 return readl(tp->aperegs + off);
0d3031d9
MC		 481}
482
1da177e4
LT		 483static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
484{
6892914f
MC		 485 unsigned long flags;
486
487 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 488 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
489 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 490 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 491}
492
493static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
494{
495 writel(val, tp->regs + off);
496 readl(tp->regs + off);
1da177e4
LT		 497}
498
6892914f 499static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 500{
6892914f
MC		 501 unsigned long flags;
502 u32 val;
503
504 spin_lock_irqsave(&tp->indirect_lock, flags);
505 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
506 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
508 return val;
509}
510
511static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
512{
513 unsigned long flags;
514
515 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
516 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
517 TG3_64BIT_REG_LOW, val);
518 return;
519 }
66711e66 520 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 521 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
522 TG3_64BIT_REG_LOW, val);
523 return;
1da177e4 524 }
6892914f
MC		 525
526 spin_lock_irqsave(&tp->indirect_lock, flags);
527 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
528 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
529 spin_unlock_irqrestore(&tp->indirect_lock, flags);
530
531 /* In indirect mode when disabling interrupts, we also need
532 * to clear the interrupt bit in the GRC local ctrl register.
533 */
534 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
535 (val == 0x1)) {
536 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
537 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
538 }
539}
540
541static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
542{
543 unsigned long flags;
544 u32 val;
545
546 spin_lock_irqsave(&tp->indirect_lock, flags);
547 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
548 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
549 spin_unlock_irqrestore(&tp->indirect_lock, flags);
550 return val;
551}
552
b401e9e2
MC		 553/* usec_wait specifies the wait time in usec when writing to certain registers
554 * where it is unsafe to read back the register without some delay.
555 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
556 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
557 */
558static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 559{
63c3a66f 560 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
b401e9e2
MC		 561 /* Non-posted methods */
562 tp->write32(tp, off, val);
563 else {
564 /* Posted method */
565 tg3_write32(tp, off, val);
566 if (usec_wait)
567 udelay(usec_wait);
568 tp->read32(tp, off);
569 }
570 /* Wait again after the read for the posted method to guarantee that
571 * the wait time is met.
572 */
573 if (usec_wait)
574 udelay(usec_wait);
1da177e4
LT		 575}
576
09ee929c
MC		 577static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
578{
579 tp->write32_mbox(tp, off, val);
7e6c63f0
HM		 580 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
581 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
582 !tg3_flag(tp, ICH_WORKAROUND)))
6892914f 583 tp->read32_mbox(tp, off);
09ee929c
MC		 584}
585
20094930 586static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 587{
588 void __iomem *mbox = tp->regs + off;
589 writel(val, mbox);
63c3a66f 590 if (tg3_flag(tp, TXD_MBOX_HWBUG))
1da177e4 591 writel(val, mbox);
7e6c63f0
HM		 592 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
593 tg3_flag(tp, FLUSH_POSTED_WRITES))
1da177e4
LT		 594 readl(mbox);
595}
596
b5d3772c
MC		 597static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
598{
de6f31eb 599 return readl(tp->regs + off + GRCMBOX_BASE);
b5d3772c
MC		 600}
601
602static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
603{
604 writel(val, tp->regs + off + GRCMBOX_BASE);
605}
606
c6cdf436 607#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 608#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
c6cdf436
MC		 609#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
610#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
611#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930 612
c6cdf436
MC		 613#define tw32(reg, val) tp->write32(tp, reg, val)
614#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
615#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
616#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 617
618static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
619{
6892914f
MC		 620 unsigned long flags;
621
4153577a 622 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 623 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
624 return;
625
6892914f 626 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 627 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 628 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
629 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 630
bbadf503
MC		 631 /* Always leave this as zero. */
632 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
633 } else {
634 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
635 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 636
bbadf503
MC		 637 /* Always leave this as zero. */
638 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
639 }
640 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 641}
642
1da177e4
LT		 643static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
644{
6892914f
MC		 645 unsigned long flags;
646
4153577a 647 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 648 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
649 *val = 0;
650 return;
651 }
652
6892914f 653 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 654 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 655 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
656 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 657
bbadf503
MC		 658 /* Always leave this as zero. */
659 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
660 } else {
661 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
662 *val = tr32(TG3PCI_MEM_WIN_DATA);
663
664 /* Always leave this as zero. */
665 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
666 }
6892914f 667 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 668}
669
0d3031d9
MC		 670static void tg3_ape_lock_init(struct tg3 *tp)
671{
672 int i;
6f5c8f83 673 u32 regbase, bit;
f92d9dc1 674
4153577a 675 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 676 regbase = TG3_APE_LOCK_GRANT;
677 else
678 regbase = TG3_APE_PER_LOCK_GRANT;
0d3031d9
MC		 679
680 /* Make sure the driver hasn't any stale locks. */
78f94dc7
MC		 681 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
682 switch (i) {
683 case TG3_APE_LOCK_PHY0:
684 case TG3_APE_LOCK_PHY1:
685 case TG3_APE_LOCK_PHY2:
686 case TG3_APE_LOCK_PHY3:
687 bit = APE_LOCK_GRANT_DRIVER;
688 break;
689 default:
690 if (!tp->pci_fn)
691 bit = APE_LOCK_GRANT_DRIVER;
692 else
693 bit = 1 << tp->pci_fn;
694 }
695 tg3_ape_write32(tp, regbase + 4 * i, bit);
6f5c8f83
MC		 696 }
697
0d3031d9
MC		 698}
699
700static int tg3_ape_lock(struct tg3 *tp, int locknum)
701{
702 int i, off;
703 int ret = 0;
6f5c8f83 704 u32 status, req, gnt, bit;
0d3031d9 705
63c3a66f 706 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 707 return 0;
708
709 switch (locknum) {
6f5c8f83 710 case TG3_APE_LOCK_GPIO:
4153577a 711 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 712 return 0;
33f401ae
MC		 713 case TG3_APE_LOCK_GRC:
714 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 715 if (!tp->pci_fn)
716 bit = APE_LOCK_REQ_DRIVER;
717 else
718 bit = 1 << tp->pci_fn;
33f401ae 719 break;
8151ad57
MC		 720 case TG3_APE_LOCK_PHY0:
721 case TG3_APE_LOCK_PHY1:
722 case TG3_APE_LOCK_PHY2:
723 case TG3_APE_LOCK_PHY3:
724 bit = APE_LOCK_REQ_DRIVER;
725 break;
33f401ae
MC		 726 default:
727 return -EINVAL;
0d3031d9
MC		 728 }
729
4153577a 730 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
f92d9dc1
MC		 731 req = TG3_APE_LOCK_REQ;
732 gnt = TG3_APE_LOCK_GRANT;
733 } else {
734 req = TG3_APE_PER_LOCK_REQ;
735 gnt = TG3_APE_PER_LOCK_GRANT;
736 }
737
0d3031d9
MC		 738 off = 4 * locknum;
739
6f5c8f83 740 tg3_ape_write32(tp, req + off, bit);
0d3031d9
MC		 741
742 /* Wait for up to 1 millisecond to acquire lock. */
743 for (i = 0; i < 100; i++) {
f92d9dc1 744 status = tg3_ape_read32(tp, gnt + off);
6f5c8f83 745 if (status == bit)
0d3031d9 746 break;
6d446ec3
GS		 747 if (pci_channel_offline(tp->pdev))
748 break;
749
0d3031d9
MC		 750 udelay(10);
751 }
752
6f5c8f83 753 if (status != bit) {
0d3031d9 754 /* Revoke the lock request. */
6f5c8f83 755 tg3_ape_write32(tp, gnt + off, bit);
0d3031d9
MC		 756 ret = -EBUSY;
757 }
758
759 return ret;
760}
761
762static void tg3_ape_unlock(struct tg3 *tp, int locknum)
763{
6f5c8f83 764 u32 gnt, bit;
0d3031d9 765
63c3a66f 766 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 767 return;
768
769 switch (locknum) {
6f5c8f83 770 case TG3_APE_LOCK_GPIO:
4153577a 771 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 772 return;
33f401ae
MC		 773 case TG3_APE_LOCK_GRC:
774 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 775 if (!tp->pci_fn)
776 bit = APE_LOCK_GRANT_DRIVER;
777 else
778 bit = 1 << tp->pci_fn;
33f401ae 779 break;
8151ad57
MC		 780 case TG3_APE_LOCK_PHY0:
781 case TG3_APE_LOCK_PHY1:
782 case TG3_APE_LOCK_PHY2:
783 case TG3_APE_LOCK_PHY3:
784 bit = APE_LOCK_GRANT_DRIVER;
785 break;
33f401ae
MC		 786 default:
787 return;
0d3031d9
MC		 788 }
789
4153577a 790 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 791 gnt = TG3_APE_LOCK_GRANT;
792 else
793 gnt = TG3_APE_PER_LOCK_GRANT;
794
6f5c8f83 795 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
0d3031d9
MC		 796}
797
b65a372b 798static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
fd6d3f0e 799{
fd6d3f0e
MC		 800 u32 apedata;
801
b65a372b
MC		 802 while (timeout_us) {
803 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
804 return -EBUSY;
805
806 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
807 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
808 break;
809
810 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
811
812 udelay(10);
813 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
814 }
815
816 return timeout_us ? 0 : -EBUSY;
817}
818
cf8d55ae
MC		 819static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
820{
821 u32 i, apedata;
822
823 for (i = 0; i < timeout_us / 10; i++) {
824 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
825
826 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
827 break;
828
829 udelay(10);
830 }
831
832 return i == timeout_us / 10;
833}
834
86449944
MC		 835static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
836 u32 len)
cf8d55ae
MC		 837{
838 int err;
839 u32 i, bufoff, msgoff, maxlen, apedata;
840
841 if (!tg3_flag(tp, APE_HAS_NCSI))
842 return 0;
843
844 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
845 if (apedata != APE_SEG_SIG_MAGIC)
846 return -ENODEV;
847
848 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
849 if (!(apedata & APE_FW_STATUS_READY))
850 return -EAGAIN;
851
852 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
853 TG3_APE_SHMEM_BASE;
854 msgoff = bufoff + 2 * sizeof(u32);
855 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
856
857 while (len) {
858 u32 length;
859
860 /* Cap xfer sizes to scratchpad limits. */
861 length = (len > maxlen) ? maxlen : len;
862 len -= length;
863
864 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
865 if (!(apedata & APE_FW_STATUS_READY))
866 return -EAGAIN;
867
868 /* Wait for up to 1 msec for APE to service previous event. */
869 err = tg3_ape_event_lock(tp, 1000);
870 if (err)
871 return err;
872
873 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
874 APE_EVENT_STATUS_SCRTCHPD_READ |
875 APE_EVENT_STATUS_EVENT_PENDING;
876 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
877
878 tg3_ape_write32(tp, bufoff, base_off);
879 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
880
881 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
882 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
883
884 base_off += length;
885
886 if (tg3_ape_wait_for_event(tp, 30000))
887 return -EAGAIN;
888
889 for (i = 0; length; i += 4, length -= 4) {
890 u32 val = tg3_ape_read32(tp, msgoff + i);
891 memcpy(data, &val, sizeof(u32));
892 data++;
893 }
894 }
895
896 return 0;
897}
898
b65a372b
MC		 899static int tg3_ape_send_event(struct tg3 *tp, u32 event)
900{
901 int err;
902 u32 apedata;
fd6d3f0e
MC		 903
904 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
905 if (apedata != APE_SEG_SIG_MAGIC)
b65a372b 906 return -EAGAIN;
fd6d3f0e
MC		 907
908 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
909 if (!(apedata & APE_FW_STATUS_READY))
b65a372b 910 return -EAGAIN;
fd6d3f0e
MC		 911
912 /* Wait for up to 1 millisecond for APE to service previous event. */
b65a372b
MC		 913 err = tg3_ape_event_lock(tp, 1000);
914 if (err)
915 return err;
fd6d3f0e 916
b65a372b
MC		 917 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
918 event | APE_EVENT_STATUS_EVENT_PENDING);
fd6d3f0e 919
b65a372b
MC		 920 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
921 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
fd6d3f0e 922
b65a372b 923 return 0;
fd6d3f0e
MC		 924}
925
926static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
927{
928 u32 event;
929 u32 apedata;
930
931 if (!tg3_flag(tp, ENABLE_APE))
932 return;
933
934 switch (kind) {
935 case RESET_KIND_INIT:
936 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
937 APE_HOST_SEG_SIG_MAGIC);
938 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
939 APE_HOST_SEG_LEN_MAGIC);
940 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
941 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
942 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
943 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
944 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
945 APE_HOST_BEHAV_NO_PHYLOCK);
946 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
947 TG3_APE_HOST_DRVR_STATE_START);
948
949 event = APE_EVENT_STATUS_STATE_START;
950 break;
951 case RESET_KIND_SHUTDOWN:
952 /* With the interface we are currently using,
953 * APE does not track driver state. Wiping
954 * out the HOST SEGMENT SIGNATURE forces
955 * the APE to assume OS absent status.
956 */
957 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
958
959 if (device_may_wakeup(&tp->pdev->dev) &&
960 tg3_flag(tp, WOL_ENABLE)) {
961 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
962 TG3_APE_HOST_WOL_SPEED_AUTO);
963 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
964 } else
965 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
966
967 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
968
969 event = APE_EVENT_STATUS_STATE_UNLOAD;
970 break;
fd6d3f0e
MC		 971 default:
972 return;
973 }
974
975 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
976
977 tg3_ape_send_event(tp, event);
978}
979
1da177e4
LT		 980static void tg3_disable_ints(struct tg3 *tp)
981{
89aeb3bc
MC		 982 int i;
983
1da177e4
LT		 984 tw32(TG3PCI_MISC_HOST_CTRL,
985 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 986 for (i = 0; i < tp->irq_max; i++)
987 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 988}
989
1da177e4
LT		 990static void tg3_enable_ints(struct tg3 *tp)
991{
89aeb3bc 992 int i;
89aeb3bc 993
bbe832c0
MC		 994 tp->irq_sync = 0;
995 wmb();
996
1da177e4
LT		 997 tw32(TG3PCI_MISC_HOST_CTRL,
998 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 999
f89f38b8 1000 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 1001 for (i = 0; i < tp->irq_cnt; i++) {
1002 struct tg3_napi *tnapi = &tp->napi[i];
c6cdf436 1003
898a56f8 1004 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
63c3a66f 1005 if (tg3_flag(tp, 1SHOT_MSI))
89aeb3bc 1006 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 1007
f89f38b8 1008 tp->coal_now |= tnapi->coal_now;
89aeb3bc 1009 }
f19af9c2
MC		 1010
1011 /* Force an initial interrupt */
63c3a66f 1012 if (!tg3_flag(tp, TAGGED_STATUS) &&
f19af9c2
MC		 1013 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1014 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1015 else
f89f38b8
MC		 1016 tw32(HOSTCC_MODE, tp->coal_now);
1017
1018 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 1019}
1020
17375d25 1021static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 1022{
17375d25 1023 struct tg3 *tp = tnapi->tp;
898a56f8 1024 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 1025 unsigned int work_exists = 0;
1026
1027 /* check for phy events */
63c3a66f 1028 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
04237ddd
MC		 1029 if (sblk->status & SD_STATUS_LINK_CHG)
1030 work_exists = 1;
1031 }
f891ea16
MC		 1032
1033 /* check for TX work to do */
1034 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1035 work_exists = 1;
1036
1037 /* check for RX work to do */
1038 if (tnapi->rx_rcb_prod_idx &&
8d9d7cfc 1039 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 1040 work_exists = 1;
1041
1042 return work_exists;
1043}
1044
17375d25 1045/* tg3_int_reenable
04237ddd
MC		 1046 * similar to tg3_enable_ints, but it accurately determines whether there
1047 * is new work pending and can return without flushing the PIO write
6aa20a22 1048 * which reenables interrupts
1da177e4 1049 */
17375d25 1050static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 1051{
17375d25
MC		 1052 struct tg3 *tp = tnapi->tp;
1053
898a56f8 1054 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 1055 mmiowb();
1056
fac9b83e
DM		 1057 /* When doing tagged status, this work check is unnecessary.
1058 * The last_tag we write above tells the chip which piece of
1059 * work we've completed.
1060 */
63c3a66f 1061 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
04237ddd 1062 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 1063 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 1064}
1065
1da177e4
LT		 1066static void tg3_switch_clocks(struct tg3 *tp)
1067{
f6eb9b1f 1068 u32 clock_ctrl;
1da177e4
LT		 1069 u32 orig_clock_ctrl;
1070
63c3a66f 1071 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
4cf78e4f
MC		 1072 return;
1073
f6eb9b1f
MC		 1074 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1075
1da177e4
LT		 1076 orig_clock_ctrl = clock_ctrl;
1077 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1078 CLOCK_CTRL_CLKRUN_OENABLE |
1079 0x1f);
1080 tp->pci_clock_ctrl = clock_ctrl;
1081
63c3a66f 1082 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4 1083 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 1084 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1085 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 1086 }
1087 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 1088 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1089 clock_ctrl |
1090 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1091 40);
1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1094 40);
1da177e4 1095 }
b401e9e2 1096 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 1097}
1098
1099#define PHY_BUSY_LOOPS 5000
1100
5c358045
HM		 1101static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1102 u32 *val)
1da177e4
LT		 1103{
1104 u32 frame_val;
1105 unsigned int loops;
1106 int ret;
1107
1108 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1109 tw32_f(MAC_MI_MODE,
1110 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1111 udelay(80);
1112 }
1113
8151ad57
MC		 1114 tg3_ape_lock(tp, tp->phy_ape_lock);
1115
1da177e4
LT		 1116 *val = 0x0;
1117
5c358045 1118 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1119 MI_COM_PHY_ADDR_MASK);
1120 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1121 MI_COM_REG_ADDR_MASK);
1122 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 1123
1da177e4
LT		 1124 tw32_f(MAC_MI_COM, frame_val);
1125
1126 loops = PHY_BUSY_LOOPS;
1127 while (loops != 0) {
1128 udelay(10);
1129 frame_val = tr32(MAC_MI_COM);
1130
1131 if ((frame_val & MI_COM_BUSY) == 0) {
1132 udelay(5);
1133 frame_val = tr32(MAC_MI_COM);
1134 break;
1135 }
1136 loops -= 1;
1137 }
1138
1139 ret = -EBUSY;
1140 if (loops != 0) {
1141 *val = frame_val & MI_COM_DATA_MASK;
1142 ret = 0;
1143 }
1144
1145 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1146 tw32_f(MAC_MI_MODE, tp->mi_mode);
1147 udelay(80);
1148 }
1149
8151ad57
MC		 1150 tg3_ape_unlock(tp, tp->phy_ape_lock);
1151
1da177e4
LT		 1152 return ret;
1153}
1154
5c358045
HM		 1155static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1156{
1157 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1158}
1159
1160static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1161 u32 val)
1da177e4
LT		 1162{
1163 u32 frame_val;
1164 unsigned int loops;
1165 int ret;
1166
f07e9af3 1167 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
221c5637 1168 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
b5d3772c
MC		 1169 return 0;
1170
1da177e4
LT		 1171 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1172 tw32_f(MAC_MI_MODE,
1173 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1174 udelay(80);
1175 }
1176
8151ad57
MC		 1177 tg3_ape_lock(tp, tp->phy_ape_lock);
1178
5c358045 1179 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1180 MI_COM_PHY_ADDR_MASK);
1181 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1182 MI_COM_REG_ADDR_MASK);
1183 frame_val |= (val & MI_COM_DATA_MASK);
1184 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 1185
1da177e4
LT		 1186 tw32_f(MAC_MI_COM, frame_val);
1187
1188 loops = PHY_BUSY_LOOPS;
1189 while (loops != 0) {
1190 udelay(10);
1191 frame_val = tr32(MAC_MI_COM);
1192 if ((frame_val & MI_COM_BUSY) == 0) {
1193 udelay(5);
1194 frame_val = tr32(MAC_MI_COM);
1195 break;
1196 }
1197 loops -= 1;
1198 }
1199
1200 ret = -EBUSY;
1201 if (loops != 0)
1202 ret = 0;
1203
1204 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1205 tw32_f(MAC_MI_MODE, tp->mi_mode);
1206 udelay(80);
1207 }
1208
8151ad57
MC		 1209 tg3_ape_unlock(tp, tp->phy_ape_lock);
1210
1da177e4
LT		 1211 return ret;
1212}
1213
5c358045
HM		 1214static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1215{
1216 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1217}
1218
b0988c15
MC		 1219static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1220{
1221 int err;
1222
1223 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1224 if (err)
1225 goto done;
1226
1227 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1228 if (err)
1229 goto done;
1230
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1232 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1233 if (err)
1234 goto done;
1235
1236 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1237
1238done:
1239 return err;
1240}
1241
1242static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1243{
1244 int err;
1245
1246 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1247 if (err)
1248 goto done;
1249
1250 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1251 if (err)
1252 goto done;
1253
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1255 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1256 if (err)
1257 goto done;
1258
1259 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1260
1261done:
1262 return err;
1263}
1264
1265static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1266{
1267 int err;
1268
1269 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1270 if (!err)
1271 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1272
1273 return err;
1274}
1275
1276static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1277{
1278 int err;
1279
1280 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1281 if (!err)
1282 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1283
1284 return err;
1285}
1286
15ee95c3
MC		 1287static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1288{
1289 int err;
1290
1291 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1292 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1293 MII_TG3_AUXCTL_SHDWSEL_MISC);
1294 if (!err)
1295 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1296
1297 return err;
1298}
1299
b4bd2929
MC		 1300static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1301{
1302 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1303 set |= MII_TG3_AUXCTL_MISC_WREN;
1304
1305 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1306}
1307
daf3ec68
NNS		 1308static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1309{
1310 u32 val;
1311 int err;
1d36ba45 1312
daf3ec68 1313 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1d36ba45 1314
daf3ec68
NNS		 1315 if (err)
1316 return err;
daf3ec68 1317
7c10ee32 1318 if (enable)
daf3ec68
NNS		 1319 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1320 else
1321 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1322
1323 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1324 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1325
1326 return err;
1327}
1d36ba45 1328
95e2869a
MC		 1329static int tg3_bmcr_reset(struct tg3 *tp)
1330{
1331 u32 phy_control;
1332 int limit, err;
1333
1334 /* OK, reset it, and poll the BMCR_RESET bit until it
1335 * clears or we time out.
1336 */
1337 phy_control = BMCR_RESET;
1338 err = tg3_writephy(tp, MII_BMCR, phy_control);
1339 if (err != 0)
1340 return -EBUSY;
1341
1342 limit = 5000;
1343 while (limit--) {
1344 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1345 if (err != 0)
1346 return -EBUSY;
1347
1348 if ((phy_control & BMCR_RESET) == 0) {
1349 udelay(40);
1350 break;
1351 }
1352 udelay(10);
1353 }
d4675b52 1354 if (limit < 0)
95e2869a
MC		 1355 return -EBUSY;
1356
1357 return 0;
1358}
1359
158d7abd
MC		 1360static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1361{
3d16543d 1362 struct tg3 *tp = bp->priv;
158d7abd
MC		 1363 u32 val;
1364
24bb4fb6 1365 spin_lock_bh(&tp->lock);
158d7abd
MC		 1366
1367 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 1368 val = -EIO;
1369
1370 spin_unlock_bh(&tp->lock);
158d7abd
MC		 1371
1372 return val;
1373}
1374
1375static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1376{
3d16543d 1377 struct tg3 *tp = bp->priv;
24bb4fb6 1378 u32 ret = 0;
158d7abd 1379
24bb4fb6 1380 spin_lock_bh(&tp->lock);
158d7abd
MC		 1381
1382 if (tg3_writephy(tp, reg, val))
24bb4fb6 1383 ret = -EIO;
158d7abd 1384
24bb4fb6
MC		 1385 spin_unlock_bh(&tp->lock);
1386
1387 return ret;
158d7abd
MC		 1388}
1389
1390static int tg3_mdio_reset(struct mii_bus *bp)
1391{
1392 return 0;
1393}
1394
9c61d6bc 1395static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 1396{
1397 u32 val;
fcb389df 1398 struct phy_device *phydev;
a9daf367 1399
3f0e3ad7 1400 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df 1401 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 1402 case PHY_ID_BCM50610:
1403 case PHY_ID_BCM50610M:
fcb389df
MC		 1404 val = MAC_PHYCFG2_50610_LED_MODES;
1405 break;
6a443a0f 1406 case PHY_ID_BCMAC131:
fcb389df
MC		 1407 val = MAC_PHYCFG2_AC131_LED_MODES;
1408 break;
6a443a0f 1409 case PHY_ID_RTL8211C:
fcb389df
MC		 1410 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1411 break;
6a443a0f 1412 case PHY_ID_RTL8201E:
fcb389df
MC		 1413 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1414 break;
1415 default:
a9daf367 1416 return;
fcb389df
MC		 1417 }
1418
1419 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1420 tw32(MAC_PHYCFG2, val);
1421
1422 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 1423 val &= ~(MAC_PHYCFG1_RGMII_INT |
1424 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1425 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 1426 tw32(MAC_PHYCFG1, val);
1427
1428 return;
1429 }
1430
63c3a66f 1431 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
fcb389df
MC		 1432 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1433 MAC_PHYCFG2_FMODE_MASK_MASK |
1434 MAC_PHYCFG2_GMODE_MASK_MASK |
1435 MAC_PHYCFG2_ACT_MASK_MASK |
1436 MAC_PHYCFG2_QUAL_MASK_MASK |
1437 MAC_PHYCFG2_INBAND_ENABLE;
1438
1439 tw32(MAC_PHYCFG2, val);
a9daf367 1440
bb85fbb6
MC		 1441 val = tr32(MAC_PHYCFG1);
1442 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1443 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
63c3a66f
JP		 1444 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1445 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1446 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
63c3a66f 1447 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1448 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1449 }
bb85fbb6
MC		 1450 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1451 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1452 tw32(MAC_PHYCFG1, val);
a9daf367 1453
a9daf367
MC		 1454 val = tr32(MAC_EXT_RGMII_MODE);
1455 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1456 MAC_RGMII_MODE_RX_QUALITY |
1457 MAC_RGMII_MODE_RX_ACTIVITY |
1458 MAC_RGMII_MODE_RX_ENG_DET |
1459 MAC_RGMII_MODE_TX_ENABLE |
1460 MAC_RGMII_MODE_TX_LOWPWR |
1461 MAC_RGMII_MODE_TX_RESET);
63c3a66f
JP		 1462 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1463 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367
MC		 1464 val |= MAC_RGMII_MODE_RX_INT_B |
1465 MAC_RGMII_MODE_RX_QUALITY |
1466 MAC_RGMII_MODE_RX_ACTIVITY |
1467 MAC_RGMII_MODE_RX_ENG_DET;
63c3a66f 1468 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1469 val |= MAC_RGMII_MODE_TX_ENABLE |
1470 MAC_RGMII_MODE_TX_LOWPWR |
1471 MAC_RGMII_MODE_TX_RESET;
1472 }
1473 tw32(MAC_EXT_RGMII_MODE, val);
1474}
1475
158d7abd
MC		 1476static void tg3_mdio_start(struct tg3 *tp)
1477{
158d7abd
MC		 1478 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1479 tw32_f(MAC_MI_MODE, tp->mi_mode);
1480 udelay(80);
a9daf367 1481
63c3a66f 1482 if (tg3_flag(tp, MDIOBUS_INITED) &&
4153577a 1483 tg3_asic_rev(tp) == ASIC_REV_5785)
9ea4818d
MC		 1484 tg3_mdio_config_5785(tp);
1485}
1486
1487static int tg3_mdio_init(struct tg3 *tp)
1488{
1489 int i;
1490 u32 reg;
1491 struct phy_device *phydev;
1492
63c3a66f 1493 if (tg3_flag(tp, 5717_PLUS)) {
9c7df915 1494 u32 is_serdes;
882e9793 1495
69f11c99 1496 tp->phy_addr = tp->pci_fn + 1;
882e9793 1497
4153577a 1498 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
d1ec96af
MC		 1499 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1500 else
1501 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1502 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1503 if (is_serdes)
1504 tp->phy_addr += 7;
1505 } else
3f0e3ad7 1506 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1507
158d7abd
MC		 1508 tg3_mdio_start(tp);
1509
63c3a66f 1510 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
158d7abd
MC		 1511 return 0;
1512
298cf9be
LB		 1513 tp->mdio_bus = mdiobus_alloc();
1514 if (tp->mdio_bus == NULL)
1515 return -ENOMEM;
158d7abd 1516
298cf9be
LB		 1517 tp->mdio_bus->name = "tg3 mdio bus";
1518 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1519 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1520 tp->mdio_bus->priv = tp;
1521 tp->mdio_bus->parent = &tp->pdev->dev;
1522 tp->mdio_bus->read = &tg3_mdio_read;
1523 tp->mdio_bus->write = &tg3_mdio_write;
1524 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1525 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1526 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1527
1528 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1529 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1530
1531 /* The bus registration will look for all the PHYs on the mdio bus.
1532 * Unfortunately, it does not ensure the PHY is powered up before
1533 * accessing the PHY ID registers. A chip reset is the
1534 * quickest way to bring the device back to an operational state..
1535 */
1536 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1537 tg3_bmcr_reset(tp);
1538
298cf9be 1539 i = mdiobus_register(tp->mdio_bus);
a9daf367 1540 if (i) {
ab96b241 1541 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1542 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1543 return i;
1544 }
158d7abd 1545
3f0e3ad7 1546 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1547
9c61d6bc 1548 if (!phydev || !phydev->drv) {
ab96b241 1549 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1550 mdiobus_unregister(tp->mdio_bus);
1551 mdiobus_free(tp->mdio_bus);
1552 return -ENODEV;
1553 }
1554
1555 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1556 case PHY_ID_BCM57780:
321d32a0 1557 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1558 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1559 break;
6a443a0f
MC		 1560 case PHY_ID_BCM50610:
1561 case PHY_ID_BCM50610M:
32e5a8d6 1562 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1563 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1564 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1565 PHY_BRCM_AUTO_PWRDWN_ENABLE;
63c3a66f 1566 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
a9daf367 1567 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
63c3a66f 1568 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1569 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
63c3a66f 1570 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367 1571 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1572 /* fallthru */
6a443a0f 1573 case PHY_ID_RTL8211C:
fcb389df 1574 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1575 break;
6a443a0f
MC		 1576 case PHY_ID_RTL8201E:
1577 case PHY_ID_BCMAC131:
a9daf367 1578 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1579 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
f07e9af3 1580 tp->phy_flags |= TG3_PHYFLG_IS_FET;
a9daf367
MC		 1581 break;
1582 }
1583
63c3a66f 1584 tg3_flag_set(tp, MDIOBUS_INITED);
9c61d6bc 1585
4153577a 1586 if (tg3_asic_rev(tp) == ASIC_REV_5785)
9c61d6bc 1587 tg3_mdio_config_5785(tp);
a9daf367
MC		 1588
1589 return 0;
158d7abd
MC		 1590}
1591
1592static void tg3_mdio_fini(struct tg3 *tp)
1593{
63c3a66f
JP		 1594 if (tg3_flag(tp, MDIOBUS_INITED)) {
1595 tg3_flag_clear(tp, MDIOBUS_INITED);
298cf9be
LB		 1596 mdiobus_unregister(tp->mdio_bus);
1597 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1598 }
1599}
1600
4ba526ce
MC		 1601/* tp->lock is held. */
1602static inline void tg3_generate_fw_event(struct tg3 *tp)
1603{
1604 u32 val;
1605
1606 val = tr32(GRC_RX_CPU_EVENT);
1607 val |= GRC_RX_CPU_DRIVER_EVENT;
1608 tw32_f(GRC_RX_CPU_EVENT, val);
1609
1610 tp->last_event_jiffies = jiffies;
1611}
1612
1613#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1614
95e2869a
MC		 1615/* tp->lock is held. */
1616static void tg3_wait_for_event_ack(struct tg3 *tp)
1617{
1618 int i;
4ba526ce
MC		 1619 unsigned int delay_cnt;
1620 long time_remain;
1621
1622 /* If enough time has passed, no wait is necessary. */
1623 time_remain = (long)(tp->last_event_jiffies + 1 +
1624 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1625 (long)jiffies;
1626 if (time_remain < 0)
1627 return;
1628
1629 /* Check if we can shorten the wait time. */
1630 delay_cnt = jiffies_to_usecs(time_remain);
1631 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1632 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1633 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1634
4ba526ce 1635 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1636 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1637 break;
6d446ec3
GS		 1638 if (pci_channel_offline(tp->pdev))
1639 break;
1640
4ba526ce 1641 udelay(8);
95e2869a
MC		 1642 }
1643}
1644
1645/* tp->lock is held. */
b28f389d 1646static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
95e2869a 1647{
b28f389d 1648 u32 reg, val;
95e2869a
MC		 1649
1650 val = 0;
1651 if (!tg3_readphy(tp, MII_BMCR, &reg))
1652 val = reg << 16;
1653 if (!tg3_readphy(tp, MII_BMSR, &reg))
1654 val |= (reg & 0xffff);
b28f389d 1655 *data++ = val;
95e2869a
MC		 1656
1657 val = 0;
1658 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1659 val = reg << 16;
1660 if (!tg3_readphy(tp, MII_LPA, &reg))
1661 val |= (reg & 0xffff);
b28f389d 1662 *data++ = val;
95e2869a
MC		 1663
1664 val = 0;
f07e9af3 1665 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
95e2869a
MC		 1666 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1667 val = reg << 16;
1668 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1669 val |= (reg & 0xffff);
1670 }
b28f389d 1671 *data++ = val;
95e2869a
MC		 1672
1673 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1674 val = reg << 16;
1675 else
1676 val = 0;
b28f389d
MC		 1677 *data++ = val;
1678}
1679
1680/* tp->lock is held. */
1681static void tg3_ump_link_report(struct tg3 *tp)
1682{
1683 u32 data[4];
1684
1685 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1686 return;
1687
1688 tg3_phy_gather_ump_data(tp, data);
1689
1690 tg3_wait_for_event_ack(tp);
1691
1692 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1693 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1694 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1695 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1696 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1697 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
95e2869a 1698
4ba526ce 1699 tg3_generate_fw_event(tp);
95e2869a
MC		 1700}
1701
8d5a89b3
MC		 1702/* tp->lock is held. */
1703static void tg3_stop_fw(struct tg3 *tp)
1704{
1705 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1706 /* Wait for RX cpu to ACK the previous event. */
1707 tg3_wait_for_event_ack(tp);
1708
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1710
1711 tg3_generate_fw_event(tp);
1712
1713 /* Wait for RX cpu to ACK this event. */
1714 tg3_wait_for_event_ack(tp);
1715 }
1716}
1717
fd6d3f0e
MC		 1718/* tp->lock is held. */
1719static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1720{
1721 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1722 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1723
1724 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1725 switch (kind) {
1726 case RESET_KIND_INIT:
1727 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1728 DRV_STATE_START);
1729 break;
1730
1731 case RESET_KIND_SHUTDOWN:
1732 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1733 DRV_STATE_UNLOAD);
1734 break;
1735
1736 case RESET_KIND_SUSPEND:
1737 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1738 DRV_STATE_SUSPEND);
1739 break;
1740
1741 default:
1742 break;
1743 }
1744 }
fd6d3f0e
MC		 1745}
1746
1747/* tp->lock is held. */
1748static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1749{
1750 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1751 switch (kind) {
1752 case RESET_KIND_INIT:
1753 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1754 DRV_STATE_START_DONE);
1755 break;
1756
1757 case RESET_KIND_SHUTDOWN:
1758 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1759 DRV_STATE_UNLOAD_DONE);
1760 break;
1761
1762 default:
1763 break;
1764 }
1765 }
fd6d3f0e
MC		 1766}
1767
1768/* tp->lock is held. */
1769static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1770{
1771 if (tg3_flag(tp, ENABLE_ASF)) {
1772 switch (kind) {
1773 case RESET_KIND_INIT:
1774 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1775 DRV_STATE_START);
1776 break;
1777
1778 case RESET_KIND_SHUTDOWN:
1779 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1780 DRV_STATE_UNLOAD);
1781 break;
1782
1783 case RESET_KIND_SUSPEND:
1784 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1785 DRV_STATE_SUSPEND);
1786 break;
1787
1788 default:
1789 break;
1790 }
1791 }
1792}
1793
1794static int tg3_poll_fw(struct tg3 *tp)
1795{
1796 int i;
1797 u32 val;
1798
df465abf
NS		 1799 if (tg3_flag(tp, NO_FWARE_REPORTED))
1800 return 0;
1801
7e6c63f0
HM		 1802 if (tg3_flag(tp, IS_SSB_CORE)) {
1803 /* We don't use firmware. */
1804 return 0;
1805 }
1806
4153577a 1807 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
fd6d3f0e
MC		 1808 /* Wait up to 20ms for init done. */
1809 for (i = 0; i < 200; i++) {
1810 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1811 return 0;
6d446ec3
GS		 1812 if (pci_channel_offline(tp->pdev))
1813 return -ENODEV;
1814
fd6d3f0e
MC		 1815 udelay(100);
1816 }
1817 return -ENODEV;
1818 }
1819
1820 /* Wait for firmware initialization to complete. */
1821 for (i = 0; i < 100000; i++) {
1822 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1823 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1824 break;
6d446ec3
GS		 1825 if (pci_channel_offline(tp->pdev)) {
1826 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1827 tg3_flag_set(tp, NO_FWARE_REPORTED);
1828 netdev_info(tp->dev, "No firmware running\n");
1829 }
1830
1831 break;
1832 }
1833
fd6d3f0e
MC		 1834 udelay(10);
1835 }
1836
1837 /* Chip might not be fitted with firmware. Some Sun onboard
1838 * parts are configured like that. So don't signal the timeout
1839 * of the above loop as an error, but do report the lack of
1840 * running firmware once.
1841 */
1842 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1843 tg3_flag_set(tp, NO_FWARE_REPORTED);
1844
1845 netdev_info(tp->dev, "No firmware running\n");
1846 }
1847
4153577a 1848 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
fd6d3f0e
MC		 1849 /* The 57765 A0 needs a little more
1850 * time to do some important work.
1851 */
1852 mdelay(10);
1853 }
1854
1855 return 0;
1856}
1857
95e2869a
MC		 1858static void tg3_link_report(struct tg3 *tp)
1859{
1860 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1861 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1862 tg3_ump_link_report(tp);
1863 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1864 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1865 (tp->link_config.active_speed == SPEED_1000 ?
1866 1000 :
1867 (tp->link_config.active_speed == SPEED_100 ?
1868 100 : 10)),
1869 (tp->link_config.active_duplex == DUPLEX_FULL ?
1870 "full" : "half"));
1871
1872 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1873 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1874 "on" : "off",
1875 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1876 "on" : "off");
47007831
MC		 1877
1878 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1879 netdev_info(tp->dev, "EEE is %s\n",
1880 tp->setlpicnt ? "enabled" : "disabled");
1881
95e2869a
MC		 1882 tg3_ump_link_report(tp);
1883 }
84421b99
NS		 1884
1885 tp->link_up = netif_carrier_ok(tp->dev);
95e2869a
MC		 1886}
1887
fdad8de4
NS		 1888static u32 tg3_decode_flowctrl_1000T(u32 adv)
1889{
1890 u32 flowctrl = 0;
1891
1892 if (adv & ADVERTISE_PAUSE_CAP) {
1893 flowctrl |= FLOW_CTRL_RX;
1894 if (!(adv & ADVERTISE_PAUSE_ASYM))
1895 flowctrl |= FLOW_CTRL_TX;
1896 } else if (adv & ADVERTISE_PAUSE_ASYM)
1897 flowctrl |= FLOW_CTRL_TX;
1898
1899 return flowctrl;
1900}
1901
95e2869a
MC		 1902static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1903{
1904 u16 miireg;
1905
e18ce346 1906 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1907 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1908 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1909 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1910 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1911 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1912 else
1913 miireg = 0;
1914
1915 return miireg;
1916}
1917
fdad8de4
NS		 1918static u32 tg3_decode_flowctrl_1000X(u32 adv)
1919{
1920 u32 flowctrl = 0;
1921
1922 if (adv & ADVERTISE_1000XPAUSE) {
1923 flowctrl |= FLOW_CTRL_RX;
1924 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1925 flowctrl |= FLOW_CTRL_TX;
1926 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1927 flowctrl |= FLOW_CTRL_TX;
1928
1929 return flowctrl;
1930}
1931
95e2869a
MC		 1932static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1933{
1934 u8 cap = 0;
1935
f3791cdf
MC		 1936 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1937 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1938 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1939 if (lcladv & ADVERTISE_1000XPAUSE)
1940 cap = FLOW_CTRL_RX;
1941 if (rmtadv & ADVERTISE_1000XPAUSE)
e18ce346 1942 cap = FLOW_CTRL_TX;
95e2869a
MC		 1943 }
1944
1945 return cap;
1946}
1947
f51f3562 1948static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1949{
b02fd9e3 1950 u8 autoneg;
f51f3562 1951 u8 flowctrl = 0;
95e2869a
MC		 1952 u32 old_rx_mode = tp->rx_mode;
1953 u32 old_tx_mode = tp->tx_mode;
1954
63c3a66f 1955 if (tg3_flag(tp, USE_PHYLIB))
3f0e3ad7 1956 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1957 else
1958 autoneg = tp->link_config.autoneg;
1959
63c3a66f 1960 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
f07e9af3 1961 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
f51f3562 1962 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1963 else
bc02ff95 1964 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1965 } else
1966 flowctrl = tp->link_config.flowctrl;
95e2869a 1967
f51f3562 1968 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1969
e18ce346 1970 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1971 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1972 else
1973 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1974
f51f3562 1975 if (old_rx_mode != tp->rx_mode)
95e2869a 1976 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1977
e18ce346 1978 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1979 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1980 else
1981 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1982
f51f3562 1983 if (old_tx_mode != tp->tx_mode)
95e2869a 1984 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1985}
1986
b02fd9e3
MC		 1987static void tg3_adjust_link(struct net_device *dev)
1988{
1989 u8 oldflowctrl, linkmesg = 0;
1990 u32 mac_mode, lcl_adv, rmt_adv;
1991 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1992 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1993
24bb4fb6 1994 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1995
1996 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1997 MAC_MODE_HALF_DUPLEX);
1998
1999 oldflowctrl = tp->link_config.active_flowctrl;
2000
2001 if (phydev->link) {
2002 lcl_adv = 0;
2003 rmt_adv = 0;
2004
2005 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2006 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748 2007 else if (phydev->speed == SPEED_1000 ||
4153577a 2008 tg3_asic_rev(tp) != ASIC_REV_5785)
b02fd9e3 2009 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 2010 else
2011 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 2012
2013 if (phydev->duplex == DUPLEX_HALF)
2014 mac_mode |= MAC_MODE_HALF_DUPLEX;
2015 else {
f88788f0 2016 lcl_adv = mii_advertise_flowctrl(
b02fd9e3
MC		 2017 tp->link_config.flowctrl);
2018
2019 if (phydev->pause)
2020 rmt_adv = LPA_PAUSE_CAP;
2021 if (phydev->asym_pause)
2022 rmt_adv |= LPA_PAUSE_ASYM;
2023 }
2024
2025 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2026 } else
2027 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2028
2029 if (mac_mode != tp->mac_mode) {
2030 tp->mac_mode = mac_mode;
2031 tw32_f(MAC_MODE, tp->mac_mode);
2032 udelay(40);
2033 }
2034
4153577a 2035 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
fcb389df
MC		 2036 if (phydev->speed == SPEED_10)
2037 tw32(MAC_MI_STAT,
2038 MAC_MI_STAT_10MBPS_MODE |
2039 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2040 else
2041 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2042 }
2043
b02fd9e3
MC		 2044 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2045 tw32(MAC_TX_LENGTHS,
2046 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2047 (6 << TX_LENGTHS_IPG_SHIFT) |
2048 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2049 else
2050 tw32(MAC_TX_LENGTHS,
2051 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2052 (6 << TX_LENGTHS_IPG_SHIFT) |
2053 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2054
34655ad6 2055 if (phydev->link != tp->old_link ||
b02fd9e3
MC		 2056 phydev->speed != tp->link_config.active_speed ||
2057 phydev->duplex != tp->link_config.active_duplex ||
2058 oldflowctrl != tp->link_config.active_flowctrl)
c6cdf436 2059 linkmesg = 1;
b02fd9e3 2060
34655ad6 2061 tp->old_link = phydev->link;
b02fd9e3
MC		 2062 tp->link_config.active_speed = phydev->speed;
2063 tp->link_config.active_duplex = phydev->duplex;
2064
24bb4fb6 2065 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 2066
2067 if (linkmesg)
2068 tg3_link_report(tp);
2069}
2070
2071static int tg3_phy_init(struct tg3 *tp)
2072{
2073 struct phy_device *phydev;
2074
f07e9af3 2075 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
b02fd9e3
MC		 2076 return 0;
2077
2078 /* Bring the PHY back to a known state. */
2079 tg3_bmcr_reset(tp);
2080
3f0e3ad7 2081 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2082
2083 /* Attach the MAC to the PHY. */
f9a8f83b
FF		 2084 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2085 tg3_adjust_link, phydev->interface);
b02fd9e3 2086 if (IS_ERR(phydev)) {
ab96b241 2087 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 2088 return PTR_ERR(phydev);
2089 }
2090
b02fd9e3 2091 /* Mask with MAC supported features. */
9c61d6bc
MC		 2092 switch (phydev->interface) {
2093 case PHY_INTERFACE_MODE_GMII:
2094 case PHY_INTERFACE_MODE_RGMII:
f07e9af3 2095 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
321d32a0
MC		 2096 phydev->supported &= (PHY_GBIT_FEATURES |
2097 SUPPORTED_Pause |
2098 SUPPORTED_Asym_Pause);
2099 break;
2100 }
2101 /* fallthru */
9c61d6bc
MC		 2102 case PHY_INTERFACE_MODE_MII:
2103 phydev->supported &= (PHY_BASIC_FEATURES |
2104 SUPPORTED_Pause |
2105 SUPPORTED_Asym_Pause);
2106 break;
2107 default:
3f0e3ad7 2108 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 2109 return -EINVAL;
2110 }
2111
f07e9af3 2112 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2113
2114 phydev->advertising = phydev->supported;
2115
b02fd9e3
MC		 2116 return 0;
2117}
2118
2119static void tg3_phy_start(struct tg3 *tp)
2120{
2121 struct phy_device *phydev;
2122
f07e9af3 2123 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2124 return;
2125
3f0e3ad7 2126 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 2127
80096068
MC		 2128 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2129 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
c6700ce2
MC		 2130 phydev->speed = tp->link_config.speed;
2131 phydev->duplex = tp->link_config.duplex;
2132 phydev->autoneg = tp->link_config.autoneg;
2133 phydev->advertising = tp->link_config.advertising;
b02fd9e3
MC		 2134 }
2135
2136 phy_start(phydev);
2137
2138 phy_start_aneg(phydev);
2139}
2140
2141static void tg3_phy_stop(struct tg3 *tp)
2142{
f07e9af3 2143 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2144 return;
2145
3f0e3ad7 2146 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 2147}
2148
2149static void tg3_phy_fini(struct tg3 *tp)
2150{
f07e9af3 2151 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7 2152 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
f07e9af3 2153 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2154 }
2155}
2156
941ec90f
MC		 2157static int tg3_phy_set_extloopbk(struct tg3 *tp)
2158{
2159 int err;
2160 u32 val;
2161
2162 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2163 return 0;
2164
2165 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2166 /* Cannot do read-modify-write on 5401 */
2167 err = tg3_phy_auxctl_write(tp,
2168 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2169 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2170 0x4c20);
2171 goto done;
2172 }
2173
2174 err = tg3_phy_auxctl_read(tp,
2175 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2176 if (err)
2177 return err;
2178
2179 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2180 err = tg3_phy_auxctl_write(tp,
2181 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2182
2183done:
2184 return err;
2185}
2186
7f97a4bd
MC		 2187static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2188{
2189 u32 phytest;
2190
2191 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2192 u32 phy;
2193
2194 tg3_writephy(tp, MII_TG3_FET_TEST,
2195 phytest | MII_TG3_FET_SHADOW_EN);
2196 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2197 if (enable)
2198 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2199 else
2200 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2201 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2202 }
2203 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2204 }
2205}
2206
6833c043
MC		 2207static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2208{
2209 u32 reg;
2210
63c3a66f
JP		 2211 if (!tg3_flag(tp, 5705_PLUS) ||
2212 (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2213 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
6833c043
MC		 2214 return;
2215
f07e9af3 2216 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7f97a4bd
MC		 2217 tg3_phy_fet_toggle_apd(tp, enable);
2218 return;
2219 }
2220
6833c043
MC		 2221 reg = MII_TG3_MISC_SHDW_WREN |
2222 MII_TG3_MISC_SHDW_SCR5_SEL |
2223 MII_TG3_MISC_SHDW_SCR5_LPED |
2224 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2225 MII_TG3_MISC_SHDW_SCR5_SDTL |
2226 MII_TG3_MISC_SHDW_SCR5_C125OE;
4153577a 2227 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
6833c043
MC		 2228 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2229
2230 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2231
2232
2233 reg = MII_TG3_MISC_SHDW_WREN |
2234 MII_TG3_MISC_SHDW_APD_SEL |
2235 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2236 if (enable)
2237 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2238
2239 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2240}
2241
953c96e0 2242static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
9ef8ca99
MC		 2243{
2244 u32 phy;
2245
63c3a66f 2246 if (!tg3_flag(tp, 5705_PLUS) ||
f07e9af3 2247 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9ef8ca99
MC		 2248 return;
2249
f07e9af3 2250 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
9ef8ca99
MC		 2251 u32 ephy;
2252
535ef6e1
MC		 2253 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2254 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2255
2256 tg3_writephy(tp, MII_TG3_FET_TEST,
2257 ephy | MII_TG3_FET_SHADOW_EN);
2258 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 2259 if (enable)
535ef6e1 2260 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 2261 else
535ef6e1
MC		 2262 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2263 tg3_writephy(tp, reg, phy);
9ef8ca99 2264 }
535ef6e1 2265 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 2266 }
2267 } else {
15ee95c3
MC		 2268 int ret;
2269
2270 ret = tg3_phy_auxctl_read(tp,
2271 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2272 if (!ret) {
9ef8ca99
MC		 2273 if (enable)
2274 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2275 else
2276 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
b4bd2929
MC		 2277 tg3_phy_auxctl_write(tp,
2278 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
9ef8ca99
MC		 2279 }
2280 }
2281}
2282
1da177e4
LT		 2283static void tg3_phy_set_wirespeed(struct tg3 *tp)
2284{
15ee95c3 2285 int ret;
1da177e4
LT		 2286 u32 val;
2287
f07e9af3 2288 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1da177e4
LT		 2289 return;
2290
15ee95c3
MC		 2291 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2292 if (!ret)
b4bd2929
MC		 2293 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2294 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1da177e4
LT		 2295}
2296
b2a5c19c
MC		 2297static void tg3_phy_apply_otp(struct tg3 *tp)
2298{
2299 u32 otp, phy;
2300
2301 if (!tp->phy_otp)
2302 return;
2303
2304 otp = tp->phy_otp;
2305
daf3ec68 2306 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
1d36ba45 2307 return;
b2a5c19c
MC		 2308
2309 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2310 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2311 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2312
2313 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2314 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2315 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2316
2317 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2318 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2319 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2320
2321 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2322 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2323
2324 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2325 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2326
2327 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2328 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2329 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2330
daf3ec68 2331 tg3_phy_toggle_auxctl_smdsp(tp, false);
b2a5c19c
MC		 2332}
2333
400dfbaa
NS		 2334static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2335{
2336 u32 val;
2337 struct ethtool_eee *dest = &tp->eee;
2338
2339 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2340 return;
2341
2342 if (eee)
2343 dest = eee;
2344
2345 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2346 return;
2347
2348 /* Pull eee_active */
2349 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2350 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2351 dest->eee_active = 1;
2352 } else
2353 dest->eee_active = 0;
2354
2355 /* Pull lp advertised settings */
2356 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2357 return;
2358 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2359
2360 /* Pull advertised and eee_enabled settings */
2361 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2362 return;
2363 dest->eee_enabled = !!val;
2364 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2365
2366 /* Pull tx_lpi_enabled */
2367 val = tr32(TG3_CPMU_EEE_MODE);
2368 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2369
2370 /* Pull lpi timer value */
2371 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2372}
2373
953c96e0 2374static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
52b02d04
MC		 2375{
2376 u32 val;
2377
2378 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2379 return;
2380
2381 tp->setlpicnt = 0;
2382
2383 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
953c96e0 2384 current_link_up &&
a6b68dab
MC		 2385 tp->link_config.active_duplex == DUPLEX_FULL &&
2386 (tp->link_config.active_speed == SPEED_100 ||
2387 tp->link_config.active_speed == SPEED_1000)) {
52b02d04
MC		 2388 u32 eeectl;
2389
2390 if (tp->link_config.active_speed == SPEED_1000)
2391 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2392 else
2393 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2394
2395 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2396
400dfbaa
NS		 2397 tg3_eee_pull_config(tp, NULL);
2398 if (tp->eee.eee_active)
52b02d04
MC		 2399 tp->setlpicnt = 2;
2400 }
2401
2402 if (!tp->setlpicnt) {
953c96e0 2403 if (current_link_up &&
daf3ec68 2404 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94 2405 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
daf3ec68 2406 tg3_phy_toggle_auxctl_smdsp(tp, false);
b715ce94
MC		 2407 }
2408
52b02d04
MC		 2409 val = tr32(TG3_CPMU_EEE_MODE);
2410 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2411 }
2412}
2413
b0c5943f
MC		 2414static void tg3_phy_eee_enable(struct tg3 *tp)
2415{
2416 u32 val;
2417
2418 if (tp->link_config.active_speed == SPEED_1000 &&
4153577a
JP		 2419 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2420 tg3_asic_rev(tp) == ASIC_REV_5719 ||
55086ad9 2421 tg3_flag(tp, 57765_CLASS)) &&
daf3ec68 2422 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94
MC		 2423 val = MII_TG3_DSP_TAP26_ALNOKO |
2424 MII_TG3_DSP_TAP26_RMRXSTO;
2425 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
daf3ec68 2426 tg3_phy_toggle_auxctl_smdsp(tp, false);
b0c5943f
MC		 2427 }
2428
2429 val = tr32(TG3_CPMU_EEE_MODE);
2430 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2431}
2432
1da177e4
LT		 2433static int tg3_wait_macro_done(struct tg3 *tp)
2434{
2435 int limit = 100;
2436
2437 while (limit--) {
2438 u32 tmp32;
2439
f08aa1a8 2440 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1da177e4
LT		 2441 if ((tmp32 & 0x1000) == 0)
2442 break;
2443 }
2444 }
d4675b52 2445 if (limit < 0)
1da177e4
LT		 2446 return -EBUSY;
2447
2448 return 0;
2449}
2450
2451static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2452{
2453 static const u32 test_pat[4][6] = {
2454 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2455 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2456 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2457 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2458 };
2459 int chan;
2460
2461 for (chan = 0; chan < 4; chan++) {
2462 int i;
2463
2464 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2465 (chan * 0x2000) | 0x0200);
f08aa1a8 2466 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2467
2468 for (i = 0; i < 6; i++)
2469 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2470 test_pat[chan][i]);
2471
f08aa1a8 2472 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2473 if (tg3_wait_macro_done(tp)) {
2474 *resetp = 1;
2475 return -EBUSY;
2476 }
2477
2478 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2479 (chan * 0x2000) | 0x0200);
f08aa1a8 2480 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1da177e4
LT		 2481 if (tg3_wait_macro_done(tp)) {
2482 *resetp = 1;
2483 return -EBUSY;
2484 }
2485
f08aa1a8 2486 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1da177e4
LT		 2487 if (tg3_wait_macro_done(tp)) {
2488 *resetp = 1;
2489 return -EBUSY;
2490 }
2491
2492 for (i = 0; i < 6; i += 2) {
2493 u32 low, high;
2494
2495 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2496 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2497 tg3_wait_macro_done(tp)) {
2498 *resetp = 1;
2499 return -EBUSY;
2500 }
2501 low &= 0x7fff;
2502 high &= 0x000f;
2503 if (low != test_pat[chan][i] ||
2504 high != test_pat[chan][i+1]) {
2505 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2506 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2507 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2508
2509 return -EBUSY;
2510 }
2511 }
2512 }
2513
2514 return 0;
2515}
2516
2517static int tg3_phy_reset_chanpat(struct tg3 *tp)
2518{
2519 int chan;
2520
2521 for (chan = 0; chan < 4; chan++) {
2522 int i;
2523
2524 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2525 (chan * 0x2000) | 0x0200);
f08aa1a8 2526 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2527 for (i = 0; i < 6; i++)
2528 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
f08aa1a8 2529 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2530 if (tg3_wait_macro_done(tp))
2531 return -EBUSY;
2532 }
2533
2534 return 0;
2535}
2536
2537static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2538{
2539 u32 reg32, phy9_orig;
2540 int retries, do_phy_reset, err;
2541
2542 retries = 10;
2543 do_phy_reset = 1;
2544 do {
2545 if (do_phy_reset) {
2546 err = tg3_bmcr_reset(tp);
2547 if (err)
2548 return err;
2549 do_phy_reset = 0;
2550 }
2551
2552 /* Disable transmitter and interrupt. */
2553 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2554 continue;
2555
2556 reg32 |= 0x3000;
2557 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2558
2559 /* Set full-duplex, 1000 mbps. */
2560 tg3_writephy(tp, MII_BMCR,
221c5637 2561 BMCR_FULLDPLX | BMCR_SPEED1000);
1da177e4
LT		 2562
2563 /* Set to master mode. */
221c5637 2564 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
1da177e4
LT		 2565 continue;
2566
221c5637
MC		 2567 tg3_writephy(tp, MII_CTRL1000,
2568 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
1da177e4 2569
daf3ec68 2570 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
1d36ba45
MC		 2571 if (err)
2572 return err;
1da177e4
LT		 2573
2574 /* Block the PHY control access. */
6ee7c0a0 2575 tg3_phydsp_write(tp, 0x8005, 0x0800);
1da177e4
LT		 2576
2577 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2578 if (!err)
2579 break;
2580 } while (--retries);
2581
2582 err = tg3_phy_reset_chanpat(tp);
2583 if (err)
2584 return err;
2585
6ee7c0a0 2586 tg3_phydsp_write(tp, 0x8005, 0x0000);
1da177e4
LT		 2587
2588 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
f08aa1a8 2589 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1da177e4 2590
daf3ec68 2591 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2592
221c5637 2593 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
1da177e4
LT		 2594
2595 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2596 reg32 &= ~0x3000;
2597 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2598 } else if (!err)
2599 err = -EBUSY;
2600
2601 return err;
2602}
2603
f4a46d1f
NNS		 2604static void tg3_carrier_off(struct tg3 *tp)
2605{
2606 netif_carrier_off(tp->dev);
2607 tp->link_up = false;
2608}
2609
ce20f161
NS		 2610static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2611{
2612 if (tg3_flag(tp, ENABLE_ASF))
2613 netdev_warn(tp->dev,
2614 "Management side-band traffic will be interrupted during phy settings change\n");
2615}
2616
1da177e4
LT		 2617/* This will reset the tigon3 PHY if there is no valid
2618 * link unless the FORCE argument is non-zero.
2619 */
2620static int tg3_phy_reset(struct tg3 *tp)
2621{
f833c4c1 2622 u32 val, cpmuctrl;
1da177e4
LT		 2623 int err;
2624
4153577a 2625 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 2626 val = tr32(GRC_MISC_CFG);
2627 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2628 udelay(40);
2629 }
f833c4c1
MC		 2630 err = tg3_readphy(tp, MII_BMSR, &val);
2631 err |= tg3_readphy(tp, MII_BMSR, &val);
1da177e4
LT		 2632 if (err != 0)
2633 return -EBUSY;
2634
f4a46d1f 2635 if (netif_running(tp->dev) && tp->link_up) {
84421b99 2636 netif_carrier_off(tp->dev);
c8e1e82b
MC		 2637 tg3_link_report(tp);
2638 }
2639
4153577a
JP		 2640 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2641 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2642 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 2643 err = tg3_phy_reset_5703_4_5(tp);
2644 if (err)
2645 return err;
2646 goto out;
2647 }
2648
b2a5c19c 2649 cpmuctrl = 0;
4153577a
JP		 2650 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2651 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 2652 cpmuctrl = tr32(TG3_CPMU_CTRL);
2653 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2654 tw32(TG3_CPMU_CTRL,
2655 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2656 }
2657
1da177e4
LT		 2658 err = tg3_bmcr_reset(tp);
2659 if (err)
2660 return err;
2661
b2a5c19c 2662 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
f833c4c1
MC		 2663 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2664 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
b2a5c19c
MC		 2665
2666 tw32(TG3_CPMU_CTRL, cpmuctrl);
2667 }
2668
4153577a
JP		 2669 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2670 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 2671 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2672 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2673 CPMU_LSPD_1000MB_MACCLK_12_5) {
2674 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2675 udelay(40);
2676 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2677 }
2678 }
2679
63c3a66f 2680 if (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2681 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
ecf1410b
MC		 2682 return 0;
2683
b2a5c19c
MC		 2684 tg3_phy_apply_otp(tp);
2685
f07e9af3 2686 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
6833c043
MC		 2687 tg3_phy_toggle_apd(tp, true);
2688 else
2689 tg3_phy_toggle_apd(tp, false);
2690
1da177e4 2691out:
1d36ba45 2692 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
daf3ec68 2693 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
6ee7c0a0
MC		 2694 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2695 tg3_phydsp_write(tp, 0x000a, 0x0323);
daf3ec68 2696 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2697 }
1d36ba45 2698
f07e9af3 2699 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
f08aa1a8
MC		 2700 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2701 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1da177e4 2702 }
1d36ba45 2703
f07e9af3 2704 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
daf3ec68 2705 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2706 tg3_phydsp_write(tp, 0x000a, 0x310b);
2707 tg3_phydsp_write(tp, 0x201f, 0x9506);
2708 tg3_phydsp_write(tp, 0x401f, 0x14e2);
daf3ec68 2709 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2710 }
f07e9af3 2711 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
daf3ec68 2712 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2713 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2714 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2715 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2716 tg3_writephy(tp, MII_TG3_TEST1,
2717 MII_TG3_TEST1_TRIM_EN | 0x4);
2718 } else
2719 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2720
daf3ec68 2721 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2722 }
c424cb24 2723 }
1d36ba45 2724
1da177e4
LT		 2725 /* Set Extended packet length bit (bit 14) on all chips that */
2726 /* support jumbo frames */
79eb6904 2727 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4 2728 /* Cannot do read-modify-write on 5401 */
b4bd2929 2729 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
63c3a66f 2730 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
1da177e4 2731 /* Set bit 14 with read-modify-write to preserve other bits */
15ee95c3
MC		 2732 err = tg3_phy_auxctl_read(tp,
2733 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2734 if (!err)
b4bd2929
MC		 2735 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2736 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
1da177e4
LT		 2737 }
2738
2739 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2740 * jumbo frames transmission.
2741 */
63c3a66f 2742 if (tg3_flag(tp, JUMBO_CAPABLE)) {
f833c4c1 2743 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
c6cdf436 2744 tg3_writephy(tp, MII_TG3_EXT_CTRL,
f833c4c1 2745 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1da177e4
LT		 2746 }
2747
4153577a 2748 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
715116a1 2749 /* adjust output voltage */
535ef6e1 2750 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2751 }
2752
4153577a 2753 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
c65a17f4
MC		 2754 tg3_phydsp_write(tp, 0xffb, 0x4000);
2755
953c96e0 2756 tg3_phy_toggle_automdix(tp, true);
1da177e4
LT		 2757 tg3_phy_set_wirespeed(tp);
2758 return 0;
2759}
2760
3a1e19d3
MC		 2761#define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2762#define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2763#define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2764 TG3_GPIO_MSG_NEED_VAUX)
2765#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2766 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2767 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2768 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2769 (TG3_GPIO_MSG_DRVR_PRES << 12))
2770
2771#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2772 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2773 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2774 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2775 (TG3_GPIO_MSG_NEED_VAUX << 12))
2776
2777static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2778{
2779 u32 status, shift;
2780
4153577a
JP		 2781 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2782 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2783 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2784 else
2785 status = tr32(TG3_CPMU_DRV_STATUS);
2786
2787 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2788 status &= ~(TG3_GPIO_MSG_MASK << shift);
2789 status |= (newstat << shift);
2790
4153577a
JP		 2791 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2792 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2793 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2794 else
2795 tw32(TG3_CPMU_DRV_STATUS, status);
2796
2797 return status >> TG3_APE_GPIO_MSG_SHIFT;
2798}
2799
520b2756
MC		 2800static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2801{
2802 if (!tg3_flag(tp, IS_NIC))
2803 return 0;
2804
4153577a
JP		 2805 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2806 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2807 tg3_asic_rev(tp) == ASIC_REV_5720) {
3a1e19d3
MC		 2808 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2809 return -EIO;
520b2756 2810
3a1e19d3
MC		 2811 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2812
2813 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2814 TG3_GRC_LCLCTL_PWRSW_DELAY);
2815
2816 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2817 } else {
2818 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2819 TG3_GRC_LCLCTL_PWRSW_DELAY);
2820 }
6f5c8f83 2821
520b2756
MC		 2822 return 0;
2823}
2824
2825static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2826{
2827 u32 grc_local_ctrl;
2828
2829 if (!tg3_flag(tp, IS_NIC) ||
4153577a
JP		 2830 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2831 tg3_asic_rev(tp) == ASIC_REV_5701)
520b2756
MC		 2832 return;
2833
2834 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2835
2836 tw32_wait_f(GRC_LOCAL_CTRL,
2837 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2838 TG3_GRC_LCLCTL_PWRSW_DELAY);
2839
2840 tw32_wait_f(GRC_LOCAL_CTRL,
2841 grc_local_ctrl,
2842 TG3_GRC_LCLCTL_PWRSW_DELAY);
2843
2844 tw32_wait_f(GRC_LOCAL_CTRL,
2845 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2846 TG3_GRC_LCLCTL_PWRSW_DELAY);
2847}
2848
2849static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2850{
2851 if (!tg3_flag(tp, IS_NIC))
2852 return;
2853
4153577a
JP		 2854 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2855 tg3_asic_rev(tp) == ASIC_REV_5701) {
520b2756
MC		 2856 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2857 (GRC_LCLCTRL_GPIO_OE0 |
2858 GRC_LCLCTRL_GPIO_OE1 |
2859 GRC_LCLCTRL_GPIO_OE2 |
2860 GRC_LCLCTRL_GPIO_OUTPUT0 |
2861 GRC_LCLCTRL_GPIO_OUTPUT1),
2862 TG3_GRC_LCLCTL_PWRSW_DELAY);
2863 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2864 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2865 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2866 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2867 GRC_LCLCTRL_GPIO_OE1 |
2868 GRC_LCLCTRL_GPIO_OE2 |
2869 GRC_LCLCTRL_GPIO_OUTPUT0 |
2870 GRC_LCLCTRL_GPIO_OUTPUT1 |
2871 tp->grc_local_ctrl;
2872 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2873 TG3_GRC_LCLCTL_PWRSW_DELAY);
2874
2875 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2876 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2877 TG3_GRC_LCLCTL_PWRSW_DELAY);
2878
2879 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2880 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2881 TG3_GRC_LCLCTL_PWRSW_DELAY);
2882 } else {
2883 u32 no_gpio2;
2884 u32 grc_local_ctrl = 0;
2885
2886 /* Workaround to prevent overdrawing Amps. */
4153577a 2887 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
520b2756
MC		 2888 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2889 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2890 grc_local_ctrl,
2891 TG3_GRC_LCLCTL_PWRSW_DELAY);
2892 }
2893
2894 /* On 5753 and variants, GPIO2 cannot be used. */
2895 no_gpio2 = tp->nic_sram_data_cfg &
2896 NIC_SRAM_DATA_CFG_NO_GPIO2;
2897
2898 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2899 GRC_LCLCTRL_GPIO_OE1 |
2900 GRC_LCLCTRL_GPIO_OE2 |
2901 GRC_LCLCTRL_GPIO_OUTPUT1 |
2902 GRC_LCLCTRL_GPIO_OUTPUT2;
2903 if (no_gpio2) {
2904 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2905 GRC_LCLCTRL_GPIO_OUTPUT2);
2906 }
2907 tw32_wait_f(GRC_LOCAL_CTRL,
2908 tp->grc_local_ctrl | grc_local_ctrl,
2909 TG3_GRC_LCLCTL_PWRSW_DELAY);
2910
2911 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2912
2913 tw32_wait_f(GRC_LOCAL_CTRL,
2914 tp->grc_local_ctrl | grc_local_ctrl,
2915 TG3_GRC_LCLCTL_PWRSW_DELAY);
2916
2917 if (!no_gpio2) {
2918 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2919 tw32_wait_f(GRC_LOCAL_CTRL,
2920 tp->grc_local_ctrl | grc_local_ctrl,
2921 TG3_GRC_LCLCTL_PWRSW_DELAY);
2922 }
2923 }
3a1e19d3
MC		 2924}
2925
cd0d7228 2926static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
3a1e19d3
MC		 2927{
2928 u32 msg = 0;
2929
2930 /* Serialize power state transitions */
2931 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2932 return;
2933
cd0d7228 2934 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
3a1e19d3
MC		 2935 msg = TG3_GPIO_MSG_NEED_VAUX;
2936
2937 msg = tg3_set_function_status(tp, msg);
2938
2939 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2940 goto done;
6f5c8f83 2941
3a1e19d3
MC		 2942 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2943 tg3_pwrsrc_switch_to_vaux(tp);
2944 else
2945 tg3_pwrsrc_die_with_vmain(tp);
2946
2947done:
6f5c8f83 2948 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
520b2756
MC		 2949}
2950
cd0d7228 2951static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
1da177e4 2952{
683644b7 2953 bool need_vaux = false;
1da177e4 2954
334355aa 2955 /* The GPIOs do something completely different on 57765. */
55086ad9 2956 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
1da177e4
LT		 2957 return;
2958
4153577a
JP		 2959 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2960 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2961 tg3_asic_rev(tp) == ASIC_REV_5720) {
cd0d7228
MC		 2962 tg3_frob_aux_power_5717(tp, include_wol ?
2963 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
3a1e19d3
MC		 2964 return;
2965 }
2966
2967 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
8c2dc7e1
MC		 2968 struct net_device *dev_peer;
2969
2970 dev_peer = pci_get_drvdata(tp->pdev_peer);
683644b7 2971
bc1c7567 2972 /* remove_one() may have been run on the peer. */
683644b7
MC		 2973 if (dev_peer) {
2974 struct tg3 *tp_peer = netdev_priv(dev_peer);
2975
63c3a66f 2976 if (tg3_flag(tp_peer, INIT_COMPLETE))
683644b7
MC		 2977 return;
2978
cd0d7228 2979 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
63c3a66f 2980 tg3_flag(tp_peer, ENABLE_ASF))
683644b7
MC		 2981 need_vaux = true;
2982 }
1da177e4
LT		 2983 }
2984
cd0d7228
MC		 2985 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2986 tg3_flag(tp, ENABLE_ASF))
683644b7
MC		 2987 need_vaux = true;
2988
520b2756
MC		 2989 if (need_vaux)
2990 tg3_pwrsrc_switch_to_vaux(tp);
2991 else
2992 tg3_pwrsrc_die_with_vmain(tp);
1da177e4
LT		 2993}
2994
e8f3f6ca
MC		 2995static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2996{
2997 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2998 return 1;
79eb6904 2999 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 3000 if (speed != SPEED_10)
3001 return 1;
3002 } else if (speed == SPEED_10)
3003 return 1;
3004
3005 return 0;
3006}
3007
44f3b503
NS		 3008static bool tg3_phy_power_bug(struct tg3 *tp)
3009{
3010 switch (tg3_asic_rev(tp)) {
3011 case ASIC_REV_5700:
3012 case ASIC_REV_5704:
3013 return true;
3014 case ASIC_REV_5780:
3015 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3016 return true;
3017 return false;
3018 case ASIC_REV_5717:
3019 if (!tp->pci_fn)
3020 return true;
3021 return false;
3022 case ASIC_REV_5719:
3023 case ASIC_REV_5720:
3024 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3025 !tp->pci_fn)
3026 return true;
3027 return false;
3028 }
3029
3030 return false;
3031}
3032
989038e2
NS		 3033static bool tg3_phy_led_bug(struct tg3 *tp)
3034{
3035 switch (tg3_asic_rev(tp)) {
3036 case ASIC_REV_5719:
300cf9b9 3037 case ASIC_REV_5720:
989038e2
NS		 3038 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3039 !tp->pci_fn)
3040 return true;
3041 return false;
3042 }
3043
3044 return false;
3045}
3046
0a459aac 3047static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 3048{
ce057f01
MC		 3049 u32 val;
3050
942d1af0
NS		 3051 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3052 return;
3053
f07e9af3 3054 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a 3055 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
5129724a
MC		 3056 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3057 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3058
3059 sg_dig_ctrl |=
3060 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3061 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3062 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3063 }
3f7045c1 3064 return;
5129724a 3065 }
3f7045c1 3066
4153577a 3067 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 3068 tg3_bmcr_reset(tp);
3069 val = tr32(GRC_MISC_CFG);
3070 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3071 udelay(40);
3072 return;
f07e9af3 3073 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
0e5f784c
MC		 3074 u32 phytest;
3075 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3076 u32 phy;
3077
3078 tg3_writephy(tp, MII_ADVERTISE, 0);
3079 tg3_writephy(tp, MII_BMCR,
3080 BMCR_ANENABLE | BMCR_ANRESTART);
3081
3082 tg3_writephy(tp, MII_TG3_FET_TEST,
3083 phytest | MII_TG3_FET_SHADOW_EN);
3084 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3085 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3086 tg3_writephy(tp,
3087 MII_TG3_FET_SHDW_AUXMODE4,
3088 phy);
3089 }
3090 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3091 }
3092 return;
0a459aac 3093 } else if (do_low_power) {
989038e2
NS		 3094 if (!tg3_phy_led_bug(tp))
3095 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3096 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac 3097
b4bd2929
MC		 3098 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3099 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3100 MII_TG3_AUXCTL_PCTL_VREG_11V;
3101 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
715116a1 3102 }
3f7045c1 3103
15c3b696
MC		 3104 /* The PHY should not be powered down on some chips because
3105 * of bugs.
3106 */
44f3b503 3107 if (tg3_phy_power_bug(tp))
15c3b696 3108 return;
ce057f01 3109
4153577a
JP		 3110 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3111 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 3112 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3113 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3114 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3115 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3116 }
3117
15c3b696
MC		 3118 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3119}
3120
ffbcfed4
MC		 3121/* tp->lock is held. */
3122static int tg3_nvram_lock(struct tg3 *tp)
3123{
63c3a66f 3124 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3125 int i;
3126
3127 if (tp->nvram_lock_cnt == 0) {
3128 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3129 for (i = 0; i < 8000; i++) {
3130 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3131 break;
3132 udelay(20);
3133 }
3134 if (i == 8000) {
3135 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3136 return -ENODEV;
3137 }
3138 }
3139 tp->nvram_lock_cnt++;
3140 }
3141 return 0;
3142}
3143
3144/* tp->lock is held. */
3145static void tg3_nvram_unlock(struct tg3 *tp)
3146{
63c3a66f 3147 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3148 if (tp->nvram_lock_cnt > 0)
3149 tp->nvram_lock_cnt--;
3150 if (tp->nvram_lock_cnt == 0)
3151 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3152 }
3153}
3154
3155/* tp->lock is held. */
3156static void tg3_enable_nvram_access(struct tg3 *tp)
3157{
63c3a66f 3158 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3159 u32 nvaccess = tr32(NVRAM_ACCESS);
3160
3161 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3162 }
3163}
3164
3165/* tp->lock is held. */
3166static void tg3_disable_nvram_access(struct tg3 *tp)
3167{
63c3a66f 3168 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3169 u32 nvaccess = tr32(NVRAM_ACCESS);
3170
3171 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3172 }
3173}
3174
3175static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3176 u32 offset, u32 *val)
3177{
3178 u32 tmp;
3179 int i;
3180
3181 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3182 return -EINVAL;
3183
3184 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3185 EEPROM_ADDR_DEVID_MASK |
3186 EEPROM_ADDR_READ);
3187 tw32(GRC_EEPROM_ADDR,
3188 tmp |
3189 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3190 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3191 EEPROM_ADDR_ADDR_MASK) |
3192 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3193
3194 for (i = 0; i < 1000; i++) {
3195 tmp = tr32(GRC_EEPROM_ADDR);
3196
3197 if (tmp & EEPROM_ADDR_COMPLETE)
3198 break;
3199 msleep(1);
3200 }
3201 if (!(tmp & EEPROM_ADDR_COMPLETE))
3202 return -EBUSY;
3203
62cedd11
MC		 3204 tmp = tr32(GRC_EEPROM_DATA);
3205
3206 /*
3207 * The data will always be opposite the native endian
3208 * format. Perform a blind byteswap to compensate.
3209 */
3210 *val = swab32(tmp);
3211
ffbcfed4
MC		 3212 return 0;
3213}
3214
3215#define NVRAM_CMD_TIMEOUT 10000
3216
3217static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3218{
3219 int i;
3220
3221 tw32(NVRAM_CMD, nvram_cmd);
3222 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3223 udelay(10);
3224 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3225 udelay(10);
3226 break;
3227 }
3228 }
3229
3230 if (i == NVRAM_CMD_TIMEOUT)
3231 return -EBUSY;
3232
3233 return 0;
3234}
3235
3236static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3237{
63c3a66f
JP		 3238 if (tg3_flag(tp, NVRAM) &&
3239 tg3_flag(tp, NVRAM_BUFFERED) &&
3240 tg3_flag(tp, FLASH) &&
3241 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3242 (tp->nvram_jedecnum == JEDEC_ATMEL))
3243
3244 addr = ((addr / tp->nvram_pagesize) <<
3245 ATMEL_AT45DB0X1B_PAGE_POS) +
3246 (addr % tp->nvram_pagesize);
3247
3248 return addr;
3249}
3250
3251static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3252{
63c3a66f
JP		 3253 if (tg3_flag(tp, NVRAM) &&
3254 tg3_flag(tp, NVRAM_BUFFERED) &&
3255 tg3_flag(tp, FLASH) &&
3256 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3257 (tp->nvram_jedecnum == JEDEC_ATMEL))
3258
3259 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3260 tp->nvram_pagesize) +
3261 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3262
3263 return addr;
3264}
3265
e4f34110
MC		 3266/* NOTE: Data read in from NVRAM is byteswapped according to
3267 * the byteswapping settings for all other register accesses.
3268 * tg3 devices are BE devices, so on a BE machine, the data
3269 * returned will be exactly as it is seen in NVRAM. On a LE
3270 * machine, the 32-bit value will be byteswapped.
3271 */
ffbcfed4
MC		 3272static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3273{
3274 int ret;
3275
63c3a66f 3276 if (!tg3_flag(tp, NVRAM))
ffbcfed4
MC		 3277 return tg3_nvram_read_using_eeprom(tp, offset, val);
3278
3279 offset = tg3_nvram_phys_addr(tp, offset);
3280
3281 if (offset > NVRAM_ADDR_MSK)
3282 return -EINVAL;
3283
3284 ret = tg3_nvram_lock(tp);
3285 if (ret)
3286 return ret;
3287
3288 tg3_enable_nvram_access(tp);
3289
3290 tw32(NVRAM_ADDR, offset);
3291 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3292 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3293
3294 if (ret == 0)
e4f34110 3295 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 3296
3297 tg3_disable_nvram_access(tp);
3298
3299 tg3_nvram_unlock(tp);
3300
3301 return ret;
3302}
3303
a9dc529d
MC		 3304/* Ensures NVRAM data is in bytestream format. */
3305static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 3306{
3307 u32 v;
a9dc529d 3308 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 3309 if (!res)
a9dc529d 3310 *val = cpu_to_be32(v);
ffbcfed4
MC		 3311 return res;
3312}
3313
dbe9b92a
MC		 3314static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3315 u32 offset, u32 len, u8 *buf)
3316{
3317 int i, j, rc = 0;
3318 u32 val;
3319
3320 for (i = 0; i < len; i += 4) {
3321 u32 addr;
3322 __be32 data;
3323
3324 addr = offset + i;
3325
3326 memcpy(&data, buf + i, 4);
3327
3328 /*
3329 * The SEEPROM interface expects the data to always be opposite
3330 * the native endian format. We accomplish this by reversing
3331 * all the operations that would have been performed on the
3332 * data from a call to tg3_nvram_read_be32().
3333 */
3334 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3335
3336 val = tr32(GRC_EEPROM_ADDR);
3337 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3338
3339 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3340 EEPROM_ADDR_READ);
3341 tw32(GRC_EEPROM_ADDR, val |
3342 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3343 (addr & EEPROM_ADDR_ADDR_MASK) |
3344 EEPROM_ADDR_START |
3345 EEPROM_ADDR_WRITE);
3346
3347 for (j = 0; j < 1000; j++) {
3348 val = tr32(GRC_EEPROM_ADDR);
3349
3350 if (val & EEPROM_ADDR_COMPLETE)
3351 break;
3352 msleep(1);
3353 }
3354 if (!(val & EEPROM_ADDR_COMPLETE)) {
3355 rc = -EBUSY;
3356 break;
3357 }
3358 }
3359
3360 return rc;
3361}
3362
3363/* offset and length are dword aligned */
3364static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3365 u8 *buf)
3366{
3367 int ret = 0;
3368 u32 pagesize = tp->nvram_pagesize;
3369 u32 pagemask = pagesize - 1;
3370 u32 nvram_cmd;
3371 u8 *tmp;
3372
3373 tmp = kmalloc(pagesize, GFP_KERNEL);
3374 if (tmp == NULL)
3375 return -ENOMEM;
3376
3377 while (len) {
3378 int j;
3379 u32 phy_addr, page_off, size;
3380
3381 phy_addr = offset & ~pagemask;
3382
3383 for (j = 0; j < pagesize; j += 4) {
3384 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3385 (__be32 *) (tmp + j));
3386 if (ret)
3387 break;
3388 }
3389 if (ret)
3390 break;
3391
3392 page_off = offset & pagemask;
3393 size = pagesize;
3394 if (len < size)
3395 size = len;
3396
3397 len -= size;
3398
3399 memcpy(tmp + page_off, buf, size);
3400
3401 offset = offset + (pagesize - page_off);
3402
3403 tg3_enable_nvram_access(tp);
3404
3405 /*
3406 * Before we can erase the flash page, we need
3407 * to issue a special "write enable" command.
3408 */
3409 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3410
3411 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3412 break;
3413
3414 /* Erase the target page */
3415 tw32(NVRAM_ADDR, phy_addr);
3416
3417 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3418 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3419
3420 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3421 break;
3422
3423 /* Issue another write enable to start the write. */
3424 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3425
3426 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3427 break;
3428
3429 for (j = 0; j < pagesize; j += 4) {
3430 __be32 data;
3431
3432 data = *((__be32 *) (tmp + j));
3433
3434 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3435
3436 tw32(NVRAM_ADDR, phy_addr + j);
3437
3438 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3439 NVRAM_CMD_WR;
3440
3441 if (j == 0)
3442 nvram_cmd |= NVRAM_CMD_FIRST;
3443 else if (j == (pagesize - 4))
3444 nvram_cmd |= NVRAM_CMD_LAST;
3445
3446 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3447 if (ret)
3448 break;
3449 }
3450 if (ret)
3451 break;
3452 }
3453
3454 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3455 tg3_nvram_exec_cmd(tp, nvram_cmd);
3456
3457 kfree(tmp);
3458
3459 return ret;
3460}
3461
3462/* offset and length are dword aligned */
3463static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3464 u8 *buf)
3465{
3466 int i, ret = 0;
3467
3468 for (i = 0; i < len; i += 4, offset += 4) {
3469 u32 page_off, phy_addr, nvram_cmd;
3470 __be32 data;
3471
3472 memcpy(&data, buf + i, 4);
3473 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3474
3475 page_off = offset % tp->nvram_pagesize;
3476
3477 phy_addr = tg3_nvram_phys_addr(tp, offset);
3478
dbe9b92a
MC		 3479 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3480
3481 if (page_off == 0 || i == 0)
3482 nvram_cmd |= NVRAM_CMD_FIRST;
3483 if (page_off == (tp->nvram_pagesize - 4))
3484 nvram_cmd |= NVRAM_CMD_LAST;
3485
3486 if (i == (len - 4))
3487 nvram_cmd |= NVRAM_CMD_LAST;
3488
42278224
MC		 3489 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3490 !tg3_flag(tp, FLASH) ||
3491 !tg3_flag(tp, 57765_PLUS))
3492 tw32(NVRAM_ADDR, phy_addr);
3493
4153577a 3494 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
dbe9b92a
MC		 3495 !tg3_flag(tp, 5755_PLUS) &&
3496 (tp->nvram_jedecnum == JEDEC_ST) &&
3497 (nvram_cmd & NVRAM_CMD_FIRST)) {
3498 u32 cmd;
3499
3500 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3501 ret = tg3_nvram_exec_cmd(tp, cmd);
3502 if (ret)
3503 break;
3504 }
3505 if (!tg3_flag(tp, FLASH)) {
3506 /* We always do complete word writes to eeprom. */
3507 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3508 }
3509
3510 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3511 if (ret)
3512 break;
3513 }
3514 return ret;
3515}
3516
3517/* offset and length are dword aligned */
3518static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3519{
3520 int ret;
3521
3522 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3523 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3524 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3525 udelay(40);
3526 }
3527
3528 if (!tg3_flag(tp, NVRAM)) {
3529 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3530 } else {
3531 u32 grc_mode;
3532
3533 ret = tg3_nvram_lock(tp);
3534 if (ret)
3535 return ret;
3536
3537 tg3_enable_nvram_access(tp);
3538 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3539 tw32(NVRAM_WRITE1, 0x406);
3540
3541 grc_mode = tr32(GRC_MODE);
3542 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3543
3544 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3545 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3546 buf);
3547 } else {
3548 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3549 buf);
3550 }
3551
3552 grc_mode = tr32(GRC_MODE);
3553 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3554
3555 tg3_disable_nvram_access(tp);
3556 tg3_nvram_unlock(tp);
3557 }
3558
3559 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3560 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3561 udelay(40);
3562 }
3563
3564 return ret;
3565}
3566
997b4f13
MC		 3567#define RX_CPU_SCRATCH_BASE 0x30000
3568#define RX_CPU_SCRATCH_SIZE 0x04000
3569#define TX_CPU_SCRATCH_BASE 0x34000
3570#define TX_CPU_SCRATCH_SIZE 0x04000
3571
3572/* tp->lock is held. */
837c45bb 3573static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
997b4f13
MC		 3574{
3575 int i;
837c45bb 3576 const int iters = 10000;
997b4f13 3577
837c45bb
NS		 3578 for (i = 0; i < iters; i++) {
3579 tw32(cpu_base + CPU_STATE, 0xffffffff);
3580 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3581 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3582 break;
6d446ec3
GS		 3583 if (pci_channel_offline(tp->pdev))
3584 return -EBUSY;
837c45bb
NS		 3585 }
3586
3587 return (i == iters) ? -EBUSY : 0;
3588}
3589
3590/* tp->lock is held. */
3591static int tg3_rxcpu_pause(struct tg3 *tp)
3592{
3593 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3594
3595 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3596 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3597 udelay(10);
3598
3599 return rc;
3600}
3601
3602/* tp->lock is held. */
3603static int tg3_txcpu_pause(struct tg3 *tp)
3604{
3605 return tg3_pause_cpu(tp, TX_CPU_BASE);
3606}
3607
3608/* tp->lock is held. */
3609static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3610{
3611 tw32(cpu_base + CPU_STATE, 0xffffffff);
3612 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3613}
3614
3615/* tp->lock is held. */
3616static void tg3_rxcpu_resume(struct tg3 *tp)
3617{
3618 tg3_resume_cpu(tp, RX_CPU_BASE);
3619}
3620
3621/* tp->lock is held. */
3622static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3623{
3624 int rc;
3625
3626 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
997b4f13 3627
4153577a 3628 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
997b4f13
MC		 3629 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3630
3631 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3632 return 0;
3633 }
837c45bb
NS		 3634 if (cpu_base == RX_CPU_BASE) {
3635 rc = tg3_rxcpu_pause(tp);
997b4f13 3636 } else {
7e6c63f0
HM		 3637 /*
3638 * There is only an Rx CPU for the 5750 derivative in the
3639 * BCM4785.
3640 */
3641 if (tg3_flag(tp, IS_SSB_CORE))
3642 return 0;
3643
837c45bb 3644 rc = tg3_txcpu_pause(tp);
997b4f13
MC		 3645 }
3646
837c45bb 3647 if (rc) {
997b4f13 3648 netdev_err(tp->dev, "%s timed out, %s CPU\n",
837c45bb 3649 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
997b4f13
MC		 3650 return -ENODEV;
3651 }
3652
3653 /* Clear firmware's nvram arbitration. */
3654 if (tg3_flag(tp, NVRAM))
3655 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3656 return 0;
3657}
3658
31f11a95
NS		 3659static int tg3_fw_data_len(struct tg3 *tp,
3660 const struct tg3_firmware_hdr *fw_hdr)
3661{
3662 int fw_len;
3663
3664 /* Non fragmented firmware have one firmware header followed by a
3665 * contiguous chunk of data to be written. The length field in that
3666 * header is not the length of data to be written but the complete
3667 * length of the bss. The data length is determined based on
3668 * tp->fw->size minus headers.
3669 *
3670 * Fragmented firmware have a main header followed by multiple
3671 * fragments. Each fragment is identical to non fragmented firmware
3672 * with a firmware header followed by a contiguous chunk of data. In
3673 * the main header, the length field is unused and set to 0xffffffff.
3674 * In each fragment header the length is the entire size of that
3675 * fragment i.e. fragment data + header length. Data length is
3676 * therefore length field in the header minus TG3_FW_HDR_LEN.
3677 */
3678 if (tp->fw_len == 0xffffffff)
3679 fw_len = be32_to_cpu(fw_hdr->len);
3680 else
3681 fw_len = tp->fw->size;
3682
3683 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3684}
3685
997b4f13
MC		 3686/* tp->lock is held. */
3687static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3688 u32 cpu_scratch_base, int cpu_scratch_size,
77997ea3 3689 const struct tg3_firmware_hdr *fw_hdr)
997b4f13 3690{
c4dab506 3691 int err, i;
997b4f13 3692 void (*write_op)(struct tg3 *, u32, u32);
31f11a95 3693 int total_len = tp->fw->size;
997b4f13
MC		 3694
3695 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3696 netdev_err(tp->dev,
3697 "%s: Trying to load TX cpu firmware which is 5705\n",
3698 __func__);
3699 return -EINVAL;
3700 }
3701
c4dab506 3702 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
997b4f13
MC		 3703 write_op = tg3_write_mem;
3704 else
3705 write_op = tg3_write_indirect_reg32;
3706
c4dab506
NS		 3707 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3708 /* It is possible that bootcode is still loading at this point.
3709 * Get the nvram lock first before halting the cpu.
3710 */
3711 int lock_err = tg3_nvram_lock(tp);
3712 err = tg3_halt_cpu(tp, cpu_base);
3713 if (!lock_err)
3714 tg3_nvram_unlock(tp);
3715 if (err)
3716 goto out;
997b4f13 3717
c4dab506
NS		 3718 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3719 write_op(tp, cpu_scratch_base + i, 0);
3720 tw32(cpu_base + CPU_STATE, 0xffffffff);
3721 tw32(cpu_base + CPU_MODE,
3722 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3723 } else {
3724 /* Subtract additional main header for fragmented firmware and
3725 * advance to the first fragment
3726 */
3727 total_len -= TG3_FW_HDR_LEN;
3728 fw_hdr++;
3729 }
77997ea3 3730
31f11a95
NS		 3731 do {
3732 u32 *fw_data = (u32 *)(fw_hdr + 1);
3733 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3734 write_op(tp, cpu_scratch_base +
3735 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3736 (i * sizeof(u32)),
3737 be32_to_cpu(fw_data[i]));
3738
3739 total_len -= be32_to_cpu(fw_hdr->len);
3740
3741 /* Advance to next fragment */
3742 fw_hdr = (struct tg3_firmware_hdr *)
3743 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3744 } while (total_len > 0);
997b4f13
MC		 3745
3746 err = 0;
3747
3748out:
3749 return err;
3750}
3751
f4bffb28
NS		 3752/* tp->lock is held. */
3753static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3754{
3755 int i;
3756 const int iters = 5;
3757
3758 tw32(cpu_base + CPU_STATE, 0xffffffff);
3759 tw32_f(cpu_base + CPU_PC, pc);
3760
3761 for (i = 0; i < iters; i++) {
3762 if (tr32(cpu_base + CPU_PC) == pc)
3763 break;
3764 tw32(cpu_base + CPU_STATE, 0xffffffff);
3765 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3766 tw32_f(cpu_base + CPU_PC, pc);
3767 udelay(1000);
3768 }
3769
3770 return (i == iters) ? -EBUSY : 0;
3771}
3772
997b4f13
MC		 3773/* tp->lock is held. */
3774static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3775{
77997ea3 3776 const struct tg3_firmware_hdr *fw_hdr;
f4bffb28 3777 int err;
997b4f13 3778
77997ea3 3779 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3780
3781 /* Firmware blob starts with version numbers, followed by
3782 start address and length. We are setting complete length.
3783 length = end_address_of_bss - start_address_of_text.
3784 Remainder is the blob to be loaded contiguously
3785 from start address. */
3786
997b4f13
MC		 3787 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3788 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
77997ea3 3789 fw_hdr);
997b4f13
MC		 3790 if (err)
3791 return err;
3792
3793 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3794 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
77997ea3 3795 fw_hdr);
997b4f13
MC		 3796 if (err)
3797 return err;
3798
3799 /* Now startup only the RX cpu. */
77997ea3
NS		 3800 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3801 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3802 if (err) {
997b4f13
MC		 3803 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3804 "should be %08x\n", __func__,
77997ea3
NS		 3805 tr32(RX_CPU_BASE + CPU_PC),
3806 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3807 return -ENODEV;
3808 }
837c45bb
NS		 3809
3810 tg3_rxcpu_resume(tp);
997b4f13
MC		 3811
3812 return 0;
3813}
3814
c4dab506
NS		 3815static int tg3_validate_rxcpu_state(struct tg3 *tp)
3816{
3817 const int iters = 1000;
3818 int i;
3819 u32 val;
3820
3821 /* Wait for boot code to complete initialization and enter service
3822 * loop. It is then safe to download service patches
3823 */
3824 for (i = 0; i < iters; i++) {
3825 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3826 break;
3827
3828 udelay(10);
3829 }
3830
3831 if (i == iters) {
3832 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3833 return -EBUSY;
3834 }
3835
3836 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3837 if (val & 0xff) {
3838 netdev_warn(tp->dev,
3839 "Other patches exist. Not downloading EEE patch\n");
3840 return -EEXIST;
3841 }
3842
3843 return 0;
3844}
3845
3846/* tp->lock is held. */
3847static void tg3_load_57766_firmware(struct tg3 *tp)
3848{
3849 struct tg3_firmware_hdr *fw_hdr;
3850
3851 if (!tg3_flag(tp, NO_NVRAM))
3852 return;
3853
3854 if (tg3_validate_rxcpu_state(tp))
3855 return;
3856
3857 if (!tp->fw)
3858 return;
3859
3860 /* This firmware blob has a different format than older firmware
3861 * releases as given below. The main difference is we have fragmented
3862 * data to be written to non-contiguous locations.
3863 *
3864 * In the beginning we have a firmware header identical to other
3865 * firmware which consists of version, base addr and length. The length
3866 * here is unused and set to 0xffffffff.
3867 *
3868 * This is followed by a series of firmware fragments which are
3869 * individually identical to previous firmware. i.e. they have the
3870 * firmware header and followed by data for that fragment. The version
3871 * field of the individual fragment header is unused.
3872 */
3873
3874 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3875 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3876 return;
3877
3878 if (tg3_rxcpu_pause(tp))
3879 return;
3880
3881 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3882 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3883
3884 tg3_rxcpu_resume(tp);
3885}
3886
997b4f13
MC		 3887/* tp->lock is held. */
3888static int tg3_load_tso_firmware(struct tg3 *tp)
3889{
77997ea3 3890 const struct tg3_firmware_hdr *fw_hdr;
997b4f13 3891 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
f4bffb28 3892 int err;
997b4f13 3893
1caf13eb 3894 if (!tg3_flag(tp, FW_TSO))
997b4f13
MC		 3895 return 0;
3896
77997ea3 3897 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3898
3899 /* Firmware blob starts with version numbers, followed by
3900 start address and length. We are setting complete length.
3901 length = end_address_of_bss - start_address_of_text.
3902 Remainder is the blob to be loaded contiguously
3903 from start address. */
3904
997b4f13 3905 cpu_scratch_size = tp->fw_len;
997b4f13 3906
4153577a 3907 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
997b4f13
MC		 3908 cpu_base = RX_CPU_BASE;
3909 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3910 } else {
3911 cpu_base = TX_CPU_BASE;
3912 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3913 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3914 }
3915
3916 err = tg3_load_firmware_cpu(tp, cpu_base,
3917 cpu_scratch_base, cpu_scratch_size,
77997ea3 3918 fw_hdr);
997b4f13
MC		 3919 if (err)
3920 return err;
3921
3922 /* Now startup the cpu. */
77997ea3
NS		 3923 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3924 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3925 if (err) {
997b4f13
MC		 3926 netdev_err(tp->dev,
3927 "%s fails to set CPU PC, is %08x should be %08x\n",
77997ea3
NS		 3928 __func__, tr32(cpu_base + CPU_PC),
3929 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3930 return -ENODEV;
3931 }
837c45bb
NS		 3932
3933 tg3_resume_cpu(tp, cpu_base);
997b4f13
MC		 3934 return 0;
3935}
3936
3937
3f007891 3938/* tp->lock is held. */
953c96e0 3939static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3f007891
MC		 3940{
3941 u32 addr_high, addr_low;
3942 int i;
3943
3944 addr_high = ((tp->dev->dev_addr[0] << 8) |
3945 tp->dev->dev_addr[1]);
3946 addr_low = ((tp->dev->dev_addr[2] << 24) |
3947 (tp->dev->dev_addr[3] << 16) |
3948 (tp->dev->dev_addr[4] << 8) |
3949 (tp->dev->dev_addr[5] << 0));
3950 for (i = 0; i < 4; i++) {
3951 if (i == 1 && skip_mac_1)
3952 continue;
3953 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3954 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3955 }
3956
4153577a
JP		 3957 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3958 tg3_asic_rev(tp) == ASIC_REV_5704) {
3f007891
MC		 3959 for (i = 0; i < 12; i++) {
3960 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3961 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3962 }
3963 }
3964
3965 addr_high = (tp->dev->dev_addr[0] +
3966 tp->dev->dev_addr[1] +
3967 tp->dev->dev_addr[2] +
3968 tp->dev->dev_addr[3] +
3969 tp->dev->dev_addr[4] +
3970 tp->dev->dev_addr[5]) &
3971 TX_BACKOFF_SEED_MASK;
3972 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3973}
3974
c866b7ea 3975static void tg3_enable_register_access(struct tg3 *tp)
1da177e4 3976{
c866b7ea
RW		 3977 /*
3978 * Make sure register accesses (indirect or otherwise) will function
3979 * correctly.
1da177e4
LT		 3980 */
3981 pci_write_config_dword(tp->pdev,
c866b7ea
RW		 3982 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3983}
1da177e4 3984
c866b7ea
RW		 3985static int tg3_power_up(struct tg3 *tp)
3986{
bed9829f 3987 int err;
8c6bda1a 3988
bed9829f 3989 tg3_enable_register_access(tp);
1da177e4 3990
bed9829f
MC		 3991 err = pci_set_power_state(tp->pdev, PCI_D0);
3992 if (!err) {
3993 /* Switch out of Vaux if it is a NIC */
3994 tg3_pwrsrc_switch_to_vmain(tp);
3995 } else {
3996 netdev_err(tp->dev, "Transition to D0 failed\n");
3997 }
1da177e4 3998
bed9829f 3999 return err;
c866b7ea 4000}
1da177e4 4001
953c96e0 4002static int tg3_setup_phy(struct tg3 *, bool);
4b409522 4003
c866b7ea
RW		 4004static int tg3_power_down_prepare(struct tg3 *tp)
4005{
4006 u32 misc_host_ctrl;
4007 bool device_should_wake, do_low_power;
4008
4009 tg3_enable_register_access(tp);
5e7dfd0f
MC		 4010
4011 /* Restore the CLKREQ setting. */
0f49bfbd
JL		 4012 if (tg3_flag(tp, CLKREQ_BUG))
4013 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4014 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 4015
1da177e4
LT		 4016 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4017 tw32(TG3PCI_MISC_HOST_CTRL,
4018 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4019
c866b7ea 4020 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
63c3a66f 4021 tg3_flag(tp, WOL_ENABLE);
05ac4cb7 4022
63c3a66f 4023 if (tg3_flag(tp, USE_PHYLIB)) {
0a459aac 4024 do_low_power = false;
f07e9af3 4025 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
80096068 4026 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
b02fd9e3 4027 struct phy_device *phydev;
0a459aac 4028 u32 phyid, advertising;
b02fd9e3 4029
3f0e3ad7 4030 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 4031
80096068 4032 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
b02fd9e3 4033
c6700ce2
MC		 4034 tp->link_config.speed = phydev->speed;
4035 tp->link_config.duplex = phydev->duplex;
4036 tp->link_config.autoneg = phydev->autoneg;
4037 tp->link_config.advertising = phydev->advertising;
b02fd9e3
MC		 4038
4039 advertising = ADVERTISED_TP |
4040 ADVERTISED_Pause |
4041 ADVERTISED_Autoneg |
4042 ADVERTISED_10baseT_Half;
4043
63c3a66f
JP		 4044 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4045 if (tg3_flag(tp, WOL_SPEED_100MB))
b02fd9e3
MC		 4046 advertising |=
4047 ADVERTISED_100baseT_Half |
4048 ADVERTISED_100baseT_Full |
4049 ADVERTISED_10baseT_Full;
4050 else
4051 advertising |= ADVERTISED_10baseT_Full;
4052 }
4053
4054 phydev->advertising = advertising;
4055
4056 phy_start_aneg(phydev);
0a459aac
MC		 4057
4058 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 4059 if (phyid != PHY_ID_BCMAC131) {
4060 phyid &= PHY_BCM_OUI_MASK;
4061 if (phyid == PHY_BCM_OUI_1 ||
4062 phyid == PHY_BCM_OUI_2 ||
4063 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 4064 do_low_power = true;
4065 }
b02fd9e3 4066 }
dd477003 4067 } else {
2023276e 4068 do_low_power = true;
0a459aac 4069
c6700ce2 4070 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
80096068 4071 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
1da177e4 4072
2855b9fe 4073 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
953c96e0 4074 tg3_setup_phy(tp, false);
1da177e4
LT		 4075 }
4076
4153577a 4077 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 4078 u32 val;
4079
4080 val = tr32(GRC_VCPU_EXT_CTRL);
4081 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
63c3a66f 4082 } else if (!tg3_flag(tp, ENABLE_ASF)) {
6921d201
MC		 4083 int i;
4084 u32 val;
4085
4086 for (i = 0; i < 200; i++) {
4087 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4088 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4089 break;
4090 msleep(1);
4091 }
4092 }
63c3a66f 4093 if (tg3_flag(tp, WOL_CAP))
a85feb8c
GZ		 4094 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4095 WOL_DRV_STATE_SHUTDOWN |
4096 WOL_DRV_WOL |
4097 WOL_SET_MAGIC_PKT);
6921d201 4098
05ac4cb7 4099 if (device_should_wake) {
1da177e4
LT		 4100 u32 mac_mode;
4101
f07e9af3 4102 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
b4bd2929
MC		 4103 if (do_low_power &&
4104 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4105 tg3_phy_auxctl_write(tp,
4106 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4107 MII_TG3_AUXCTL_PCTL_WOL_EN |
4108 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4109 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
dd477003
MC		 4110 udelay(40);
4111 }
1da177e4 4112
f07e9af3 4113 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3f7045c1 4114 mac_mode = MAC_MODE_PORT_MODE_GMII;
942d1af0
NS		 4115 else if (tp->phy_flags &
4116 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4117 if (tp->link_config.active_speed == SPEED_1000)
4118 mac_mode = MAC_MODE_PORT_MODE_GMII;
4119 else
4120 mac_mode = MAC_MODE_PORT_MODE_MII;
4121 } else
3f7045c1 4122 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 4123
e8f3f6ca 4124 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4153577a 4125 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
63c3a66f 4126 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
e8f3f6ca
MC		 4127 SPEED_100 : SPEED_10;
4128 if (tg3_5700_link_polarity(tp, speed))
4129 mac_mode |= MAC_MODE_LINK_POLARITY;
4130 else
4131 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4132 }
1da177e4
LT		 4133 } else {
4134 mac_mode = MAC_MODE_PORT_MODE_TBI;
4135 }
4136
63c3a66f 4137 if (!tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 4138 tw32(MAC_LED_CTRL, tp->led_ctrl);
4139
05ac4cb7 4140 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
63c3a66f
JP		 4141 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4142 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
05ac4cb7 4143 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 4144
63c3a66f 4145 if (tg3_flag(tp, ENABLE_APE))
d2394e6b
MC		 4146 mac_mode |= MAC_MODE_APE_TX_EN |
4147 MAC_MODE_APE_RX_EN |
4148 MAC_MODE_TDE_ENABLE;
3bda1258 4149
1da177e4
LT		 4150 tw32_f(MAC_MODE, mac_mode);
4151 udelay(100);
4152
4153 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4154 udelay(10);
4155 }
4156
63c3a66f 4157 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4153577a
JP		 4158 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4159 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 4160 u32 base_val;
4161
4162 base_val = tp->pci_clock_ctrl;
4163 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4164 CLOCK_CTRL_TXCLK_DISABLE);
4165
b401e9e2
MC		 4166 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4167 CLOCK_CTRL_PWRDOWN_PLL133, 40);
63c3a66f
JP		 4168 } else if (tg3_flag(tp, 5780_CLASS) ||
4169 tg3_flag(tp, CPMU_PRESENT) ||
4153577a 4170 tg3_asic_rev(tp) == ASIC_REV_5906) {
4cf78e4f 4171 /* do nothing */
63c3a66f 4172 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
1da177e4
LT		 4173 u32 newbits1, newbits2;
4174
4153577a
JP		 4175 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4176 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4177 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4178 CLOCK_CTRL_TXCLK_DISABLE |
4179 CLOCK_CTRL_ALTCLK);
4180 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
63c3a66f 4181 } else if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4182 newbits1 = CLOCK_CTRL_625_CORE;
4183 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4184 } else {
4185 newbits1 = CLOCK_CTRL_ALTCLK;
4186 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4187 }
4188
b401e9e2
MC		 4189 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4190 40);
1da177e4 4191
b401e9e2
MC		 4192 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4193 40);
1da177e4 4194
63c3a66f 4195 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4196 u32 newbits3;
4197
4153577a
JP		 4198 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4199 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4200 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4201 CLOCK_CTRL_TXCLK_DISABLE |
4202 CLOCK_CTRL_44MHZ_CORE);
4203 } else {
4204 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4205 }
4206
b401e9e2
MC		 4207 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4208 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 4209 }
4210 }
4211
63c3a66f 4212 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
0a459aac 4213 tg3_power_down_phy(tp, do_low_power);
6921d201 4214
cd0d7228 4215 tg3_frob_aux_power(tp, true);
1da177e4
LT		 4216
4217 /* Workaround for unstable PLL clock */
7e6c63f0 4218 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4153577a
JP		 4219 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4220 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
1da177e4
LT		 4221 u32 val = tr32(0x7d00);
4222
4223 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4224 tw32(0x7d00, val);
63c3a66f 4225 if (!tg3_flag(tp, ENABLE_ASF)) {
ec41c7df
MC		 4226 int err;
4227
4228 err = tg3_nvram_lock(tp);
1da177e4 4229 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 4230 if (!err)
4231 tg3_nvram_unlock(tp);
6921d201 4232 }
1da177e4
LT		 4233 }
4234
bbadf503
MC		 4235 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4236
2e460fc0
NS		 4237 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4238
c866b7ea
RW		 4239 return 0;
4240}
12dac075 4241
c866b7ea
RW		 4242static void tg3_power_down(struct tg3 *tp)
4243{
63c3a66f 4244 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
c866b7ea 4245 pci_set_power_state(tp->pdev, PCI_D3hot);
1da177e4
LT		 4246}
4247
1da177e4
LT		 4248static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4249{
4250 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4251 case MII_TG3_AUX_STAT_10HALF:
4252 *speed = SPEED_10;
4253 *duplex = DUPLEX_HALF;
4254 break;
4255
4256 case MII_TG3_AUX_STAT_10FULL:
4257 *speed = SPEED_10;
4258 *duplex = DUPLEX_FULL;
4259 break;
4260
4261 case MII_TG3_AUX_STAT_100HALF:
4262 *speed = SPEED_100;
4263 *duplex = DUPLEX_HALF;
4264 break;
4265
4266 case MII_TG3_AUX_STAT_100FULL:
4267 *speed = SPEED_100;
4268 *duplex = DUPLEX_FULL;
4269 break;
4270
4271 case MII_TG3_AUX_STAT_1000HALF:
4272 *speed = SPEED_1000;
4273 *duplex = DUPLEX_HALF;
4274 break;
4275
4276 case MII_TG3_AUX_STAT_1000FULL:
4277 *speed = SPEED_1000;
4278 *duplex = DUPLEX_FULL;
4279 break;
4280
4281 default:
f07e9af3 4282 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
715116a1
MC		 4283 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4284 SPEED_10;
4285 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4286 DUPLEX_HALF;
4287 break;
4288 }
e740522e
MC		 4289 *speed = SPEED_UNKNOWN;
4290 *duplex = DUPLEX_UNKNOWN;
1da177e4 4291 break;
855e1111 4292 }
1da177e4
LT		 4293}
4294
42b64a45 4295static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
1da177e4 4296{
42b64a45
MC		 4297 int err = 0;
4298 u32 val, new_adv;
1da177e4 4299
42b64a45 4300 new_adv = ADVERTISE_CSMA;
202ff1c2 4301 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
f88788f0 4302 new_adv |= mii_advertise_flowctrl(flowctrl);
1da177e4 4303
42b64a45
MC		 4304 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4305 if (err)
4306 goto done;
ba4d07a8 4307
4f272096
MC		 4308 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4309 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
ba4d07a8 4310
4153577a
JP		 4311 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4312 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4f272096 4313 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
ba4d07a8 4314
4f272096
MC		 4315 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4316 if (err)
4317 goto done;
4318 }
1da177e4 4319
42b64a45
MC		 4320 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4321 goto done;
52b02d04 4322
42b64a45
MC		 4323 tw32(TG3_CPMU_EEE_MODE,
4324 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
52b02d04 4325
daf3ec68 4326 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
42b64a45
MC		 4327 if (!err) {
4328 u32 err2;
52b02d04 4329
b715ce94
MC		 4330 val = 0;
4331 /* Advertise 100-BaseTX EEE ability */
4332 if (advertise & ADVERTISED_100baseT_Full)
4333 val |= MDIO_AN_EEE_ADV_100TX;
4334 /* Advertise 1000-BaseT EEE ability */
4335 if (advertise & ADVERTISED_1000baseT_Full)
4336 val |= MDIO_AN_EEE_ADV_1000T;
9e2ecbeb
NS		 4337
4338 if (!tp->eee.eee_enabled) {
4339 val = 0;
4340 tp->eee.advertised = 0;
4341 } else {
4342 tp->eee.advertised = advertise &
4343 (ADVERTISED_100baseT_Full |
4344 ADVERTISED_1000baseT_Full);
4345 }
4346
b715ce94
MC		 4347 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4348 if (err)
4349 val = 0;
4350
4153577a 4351 switch (tg3_asic_rev(tp)) {
21a00ab2
MC		 4352 case ASIC_REV_5717:
4353 case ASIC_REV_57765:
55086ad9 4354 case ASIC_REV_57766:
21a00ab2 4355 case ASIC_REV_5719:
b715ce94
MC		 4356 /* If we advertised any eee advertisements above... */
4357 if (val)
4358 val = MII_TG3_DSP_TAP26_ALNOKO |
4359 MII_TG3_DSP_TAP26_RMRXSTO |
4360 MII_TG3_DSP_TAP26_OPCSINPT;
21a00ab2 4361 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
be671947
MC		 4362 /* Fall through */
4363 case ASIC_REV_5720:
c65a17f4 4364 case ASIC_REV_5762:
be671947
MC		 4365 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4366 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4367 MII_TG3_DSP_CH34TP2_HIBW01);
21a00ab2 4368 }
52b02d04 4369
daf3ec68 4370 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
42b64a45
MC		 4371 if (!err)
4372 err = err2;
4373 }
4374
4375done:
4376 return err;
4377}
4378
4379static void tg3_phy_copper_begin(struct tg3 *tp)
4380{
d13ba512
MC		 4381 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4382 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4383 u32 adv, fc;
4384
942d1af0
NS		 4385 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4386 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
d13ba512
MC		 4387 adv = ADVERTISED_10baseT_Half |
4388 ADVERTISED_10baseT_Full;
4389 if (tg3_flag(tp, WOL_SPEED_100MB))
4390 adv |= ADVERTISED_100baseT_Half |
4391 ADVERTISED_100baseT_Full;
942d1af0
NS		 4392 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK)
4393 adv |= ADVERTISED_1000baseT_Half |
4394 ADVERTISED_1000baseT_Full;
d13ba512
MC		 4395
4396 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
42b64a45 4397 } else {
d13ba512
MC		 4398 adv = tp->link_config.advertising;
4399 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4400 adv &= ~(ADVERTISED_1000baseT_Half |
4401 ADVERTISED_1000baseT_Full);
4402
4403 fc = tp->link_config.flowctrl;
52b02d04 4404 }
52b02d04 4405
d13ba512 4406 tg3_phy_autoneg_cfg(tp, adv, fc);
52b02d04 4407
942d1af0
NS		 4408 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4409 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4410 /* Normally during power down we want to autonegotiate
4411 * the lowest possible speed for WOL. However, to avoid
4412 * link flap, we leave it untouched.
4413 */
4414 return;
4415 }
4416
d13ba512
MC		 4417 tg3_writephy(tp, MII_BMCR,
4418 BMCR_ANENABLE | BMCR_ANRESTART);
4419 } else {
4420 int i;
1da177e4
LT		 4421 u32 bmcr, orig_bmcr;
4422
4423 tp->link_config.active_speed = tp->link_config.speed;
4424 tp->link_config.active_duplex = tp->link_config.duplex;
4425
7c6cdead
NS		 4426 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4427 /* With autoneg disabled, 5715 only links up when the
4428 * advertisement register has the configured speed
4429 * enabled.
4430 */
4431 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4432 }
4433
1da177e4
LT		 4434 bmcr = 0;
4435 switch (tp->link_config.speed) {
4436 default:
4437 case SPEED_10:
4438 break;
4439
4440 case SPEED_100:
4441 bmcr |= BMCR_SPEED100;
4442 break;
4443
4444 case SPEED_1000:
221c5637 4445 bmcr |= BMCR_SPEED1000;
1da177e4 4446 break;
855e1111 4447 }
1da177e4
LT		 4448
4449 if (tp->link_config.duplex == DUPLEX_FULL)
4450 bmcr |= BMCR_FULLDPLX;
4451
4452 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4453 (bmcr != orig_bmcr)) {
4454 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4455 for (i = 0; i < 1500; i++) {
4456 u32 tmp;
4457
4458 udelay(10);
4459 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4460 tg3_readphy(tp, MII_BMSR, &tmp))
4461 continue;
4462 if (!(tmp & BMSR_LSTATUS)) {
4463 udelay(40);
4464 break;
4465 }
4466 }
4467 tg3_writephy(tp, MII_BMCR, bmcr);
4468 udelay(40);
4469 }
1da177e4
LT		 4470 }
4471}
4472
fdad8de4
NS		 4473static int tg3_phy_pull_config(struct tg3 *tp)
4474{
4475 int err;
4476 u32 val;
4477
4478 err = tg3_readphy(tp, MII_BMCR, &val);
4479 if (err)
4480 goto done;
4481
4482 if (!(val & BMCR_ANENABLE)) {
4483 tp->link_config.autoneg = AUTONEG_DISABLE;
4484 tp->link_config.advertising = 0;
4485 tg3_flag_clear(tp, PAUSE_AUTONEG);
4486
4487 err = -EIO;
4488
4489 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4490 case 0:
4491 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4492 goto done;
4493
4494 tp->link_config.speed = SPEED_10;
4495 break;
4496 case BMCR_SPEED100:
4497 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4498 goto done;
4499
4500 tp->link_config.speed = SPEED_100;
4501 break;
4502 case BMCR_SPEED1000:
4503 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4504 tp->link_config.speed = SPEED_1000;
4505 break;
4506 }
4507 /* Fall through */
4508 default:
4509 goto done;
4510 }
4511
4512 if (val & BMCR_FULLDPLX)
4513 tp->link_config.duplex = DUPLEX_FULL;
4514 else
4515 tp->link_config.duplex = DUPLEX_HALF;
4516
4517 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4518
4519 err = 0;
4520 goto done;
4521 }
4522
4523 tp->link_config.autoneg = AUTONEG_ENABLE;
4524 tp->link_config.advertising = ADVERTISED_Autoneg;
4525 tg3_flag_set(tp, PAUSE_AUTONEG);
4526
4527 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4528 u32 adv;
4529
4530 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4531 if (err)
4532 goto done;
4533
4534 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4535 tp->link_config.advertising |= adv | ADVERTISED_TP;
4536
4537 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4538 } else {
4539 tp->link_config.advertising |= ADVERTISED_FIBRE;
4540 }
4541
4542 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4543 u32 adv;
4544
4545 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4546 err = tg3_readphy(tp, MII_CTRL1000, &val);
4547 if (err)
4548 goto done;
4549
4550 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4551 } else {
4552 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4553 if (err)
4554 goto done;
4555
4556 adv = tg3_decode_flowctrl_1000X(val);
4557 tp->link_config.flowctrl = adv;
4558
4559 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4560 adv = mii_adv_to_ethtool_adv_x(val);
4561 }
4562
4563 tp->link_config.advertising |= adv;
4564 }
4565
4566done:
4567 return err;
4568}
4569
1da177e4
LT		 4570static int tg3_init_5401phy_dsp(struct tg3 *tp)
4571{
4572 int err;
4573
4574 /* Turn off tap power management. */
4575 /* Set Extended packet length bit */
b4bd2929 4576 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
1da177e4 4577
6ee7c0a0
MC		 4578 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4579 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4580 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4581 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4582 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
1da177e4
LT		 4583
4584 udelay(40);
4585
4586 return err;
4587}
4588
ed1ff5c3
NS		 4589static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4590{
5b6c273a 4591 struct ethtool_eee eee;
ed1ff5c3
NS		 4592
4593 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4594 return true;
4595
5b6c273a 4596 tg3_eee_pull_config(tp, &eee);
ed1ff5c3 4597
5b6c273a
NS		 4598 if (tp->eee.eee_enabled) {
4599 if (tp->eee.advertised != eee.advertised ||
4600 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4601 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4602 return false;
4603 } else {
4604 /* EEE is disabled but we're advertising */
4605 if (eee.advertised)
4606 return false;
4607 }
ed1ff5c3
NS		 4608
4609 return true;
4610}
4611
e2bf73e7 4612static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
1da177e4 4613{
e2bf73e7 4614 u32 advmsk, tgtadv, advertising;
3600d918 4615
e2bf73e7
MC		 4616 advertising = tp->link_config.advertising;
4617 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
1da177e4 4618
e2bf73e7
MC		 4619 advmsk = ADVERTISE_ALL;
4620 if (tp->link_config.active_duplex == DUPLEX_FULL) {
f88788f0 4621 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
e2bf73e7
MC		 4622 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4623 }
1da177e4 4624
e2bf73e7
MC		 4625 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4626 return false;
4627
4628 if ((*lcladv & advmsk) != tgtadv)
4629 return false;
b99d2a57 4630
f07e9af3 4631 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1da177e4
LT		 4632 u32 tg3_ctrl;
4633
e2bf73e7 4634 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
3600d918 4635
221c5637 4636 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
e2bf73e7 4637 return false;
1da177e4 4638
3198e07f 4639 if (tgtadv &&
4153577a
JP		 4640 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4641 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
3198e07f
MC		 4642 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4643 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4644 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4645 } else {
4646 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4647 }
4648
e2bf73e7
MC		 4649 if (tg3_ctrl != tgtadv)
4650 return false;
ef167e27
MC		 4651 }
4652
e2bf73e7 4653 return true;
ef167e27
MC		 4654}
4655
859edb26
MC		 4656static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4657{
4658 u32 lpeth = 0;
4659
4660 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4661 u32 val;
4662
4663 if (tg3_readphy(tp, MII_STAT1000, &val))
4664 return false;
4665
4666 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4667 }
4668
4669 if (tg3_readphy(tp, MII_LPA, rmtadv))
4670 return false;
4671
4672 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4673 tp->link_config.rmt_adv = lpeth;
4674
4675 return true;
4676}
4677
953c96e0 4678static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
f4a46d1f
NNS		 4679{
4680 if (curr_link_up != tp->link_up) {
4681 if (curr_link_up) {
84421b99 4682 netif_carrier_on(tp->dev);
f4a46d1f 4683 } else {
84421b99 4684 netif_carrier_off(tp->dev);
f4a46d1f
NNS		 4685 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4686 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4687 }
4688
4689 tg3_link_report(tp);
4690 return true;
4691 }
4692
4693 return false;
4694}
4695
3310e248
MC		 4696static void tg3_clear_mac_status(struct tg3 *tp)
4697{
4698 tw32(MAC_EVENT, 0);
4699
4700 tw32_f(MAC_STATUS,
4701 MAC_STATUS_SYNC_CHANGED |
4702 MAC_STATUS_CFG_CHANGED |
4703 MAC_STATUS_MI_COMPLETION |
4704 MAC_STATUS_LNKSTATE_CHANGED);
4705 udelay(40);
4706}
4707
9e2ecbeb
NS		 4708static void tg3_setup_eee(struct tg3 *tp)
4709{
4710 u32 val;
4711
4712 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4713 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4714 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4715 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4716
4717 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4718
4719 tw32_f(TG3_CPMU_EEE_CTRL,
4720 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4721
4722 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4723 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4724 TG3_CPMU_EEEMD_LPI_IN_RX |
4725 TG3_CPMU_EEEMD_EEE_ENABLE;
4726
4727 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4728 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4729
4730 if (tg3_flag(tp, ENABLE_APE))
4731 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4732
4733 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4734
4735 tw32_f(TG3_CPMU_EEE_DBTMR1,
4736 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4737 (tp->eee.tx_lpi_timer & 0xffff));
4738
4739 tw32_f(TG3_CPMU_EEE_DBTMR2,
4740 TG3_CPMU_DBTMR2_APE_TX_2047US |
4741 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4742}
4743
953c96e0 4744static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
1da177e4 4745{
953c96e0 4746 bool current_link_up;
f833c4c1 4747 u32 bmsr, val;
ef167e27 4748 u32 lcl_adv, rmt_adv;
1da177e4
LT		 4749 u16 current_speed;
4750 u8 current_duplex;
4751 int i, err;
4752
3310e248 4753 tg3_clear_mac_status(tp);
1da177e4 4754
8ef21428
MC		 4755 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4756 tw32_f(MAC_MI_MODE,
4757 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4758 udelay(80);
4759 }
1da177e4 4760
b4bd2929 4761 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
1da177e4
LT		 4762
4763 /* Some third-party PHYs need to be reset on link going
4764 * down.
4765 */
4153577a
JP		 4766 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4767 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4768 tg3_asic_rev(tp) == ASIC_REV_5705) &&
f4a46d1f 4769 tp->link_up) {
1da177e4
LT		 4770 tg3_readphy(tp, MII_BMSR, &bmsr);
4771 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4772 !(bmsr & BMSR_LSTATUS))
953c96e0 4773 force_reset = true;
1da177e4
LT		 4774 }
4775 if (force_reset)
4776 tg3_phy_reset(tp);
4777
79eb6904 4778 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 4779 tg3_readphy(tp, MII_BMSR, &bmsr);
4780 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
63c3a66f 4781 !tg3_flag(tp, INIT_COMPLETE))
1da177e4
LT		 4782 bmsr = 0;
4783
4784 if (!(bmsr & BMSR_LSTATUS)) {
4785 err = tg3_init_5401phy_dsp(tp);
4786 if (err)
4787 return err;
4788
4789 tg3_readphy(tp, MII_BMSR, &bmsr);
4790 for (i = 0; i < 1000; i++) {
4791 udelay(10);
4792 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4793 (bmsr & BMSR_LSTATUS)) {
4794 udelay(40);
4795 break;
4796 }
4797 }
4798
79eb6904
MC		 4799 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4800 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 4801 !(bmsr & BMSR_LSTATUS) &&
4802 tp->link_config.active_speed == SPEED_1000) {
4803 err = tg3_phy_reset(tp);
4804 if (!err)
4805 err = tg3_init_5401phy_dsp(tp);
4806 if (err)
4807 return err;
4808 }
4809 }
4153577a
JP		 4810 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4811 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
1da177e4
LT		 4812 /* 5701 {A0,B0} CRC bug workaround */
4813 tg3_writephy(tp, 0x15, 0x0a75);
f08aa1a8
MC		 4814 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4815 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4816 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
1da177e4
LT		 4817 }
4818
4819 /* Clear pending interrupts... */
f833c4c1
MC		 4820 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4821 tg3_readphy(tp, MII_TG3_ISTAT, &val);
1da177e4 4822
f07e9af3 4823 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
1da177e4 4824 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
f07e9af3 4825 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
1da177e4
LT		 4826 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4827
4153577a
JP		 4828 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4829 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4830 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4831 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4832 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4833 else
4834 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4835 }
4836
953c96e0 4837 current_link_up = false;
e740522e
MC		 4838 current_speed = SPEED_UNKNOWN;
4839 current_duplex = DUPLEX_UNKNOWN;
e348c5e7 4840 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
859edb26 4841 tp->link_config.rmt_adv = 0;
1da177e4 4842
f07e9af3 4843 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
15ee95c3
MC		 4844 err = tg3_phy_auxctl_read(tp,
4845 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4846 &val);
4847 if (!err && !(val & (1 << 10))) {
b4bd2929
MC		 4848 tg3_phy_auxctl_write(tp,
4849 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4850 val | (1 << 10));
1da177e4
LT		 4851 goto relink;
4852 }
4853 }
4854
4855 bmsr = 0;
4856 for (i = 0; i < 100; i++) {
4857 tg3_readphy(tp, MII_BMSR, &bmsr);
4858 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4859 (bmsr & BMSR_LSTATUS))
4860 break;
4861 udelay(40);
4862 }
4863
4864 if (bmsr & BMSR_LSTATUS) {
4865 u32 aux_stat, bmcr;
4866
4867 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4868 for (i = 0; i < 2000; i++) {
4869 udelay(10);
4870 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4871 aux_stat)
4872 break;
4873 }
4874
4875 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4876 &current_speed,
4877 &current_duplex);
4878
4879 bmcr = 0;
4880 for (i = 0; i < 200; i++) {
4881 tg3_readphy(tp, MII_BMCR, &bmcr);
4882 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4883 continue;
4884 if (bmcr && bmcr != 0x7fff)
4885 break;
4886 udelay(10);
4887 }
4888
ef167e27
MC		 4889 lcl_adv = 0;
4890 rmt_adv = 0;
1da177e4 4891
ef167e27
MC		 4892 tp->link_config.active_speed = current_speed;
4893 tp->link_config.active_duplex = current_duplex;
4894
4895 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
ed1ff5c3
NS		 4896 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4897
ef167e27 4898 if ((bmcr & BMCR_ANENABLE) &&
ed1ff5c3 4899 eee_config_ok &&
e2bf73e7 4900 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
859edb26 4901 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
953c96e0 4902 current_link_up = true;
ed1ff5c3
NS		 4903
4904 /* EEE settings changes take effect only after a phy
4905 * reset. If we have skipped a reset due to Link Flap
4906 * Avoidance being enabled, do it now.
4907 */
4908 if (!eee_config_ok &&
4909 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
5b6c273a
NS		 4910 !force_reset) {
4911 tg3_setup_eee(tp);
ed1ff5c3 4912 tg3_phy_reset(tp);
5b6c273a 4913 }
1da177e4
LT		 4914 } else {
4915 if (!(bmcr & BMCR_ANENABLE) &&
4916 tp->link_config.speed == current_speed &&
f0fcd7a9 4917 tp->link_config.duplex == current_duplex) {
953c96e0 4918 current_link_up = true;
1da177e4
LT		 4919 }
4920 }
4921
953c96e0 4922 if (current_link_up &&
e348c5e7
MC		 4923 tp->link_config.active_duplex == DUPLEX_FULL) {
4924 u32 reg, bit;
4925
4926 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4927 reg = MII_TG3_FET_GEN_STAT;
4928 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4929 } else {
4930 reg = MII_TG3_EXT_STAT;
4931 bit = MII_TG3_EXT_STAT_MDIX;
4932 }
4933
4934 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4935 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4936
ef167e27 4937 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
e348c5e7 4938 }
1da177e4
LT		 4939 }
4940
1da177e4 4941relink:
953c96e0 4942 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
1da177e4
LT		 4943 tg3_phy_copper_begin(tp);
4944
7e6c63f0 4945 if (tg3_flag(tp, ROBOSWITCH)) {
953c96e0 4946 current_link_up = true;
7e6c63f0
HM		 4947 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4948 current_speed = SPEED_1000;
4949 current_duplex = DUPLEX_FULL;
4950 tp->link_config.active_speed = current_speed;
4951 tp->link_config.active_duplex = current_duplex;
4952 }
4953
f833c4c1 4954 tg3_readphy(tp, MII_BMSR, &bmsr);
06c03c02
MB		 4955 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4956 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
953c96e0 4957 current_link_up = true;
1da177e4
LT		 4958 }
4959
4960 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
953c96e0 4961 if (current_link_up) {
1da177e4
LT		 4962 if (tp->link_config.active_speed == SPEED_100 ||
4963 tp->link_config.active_speed == SPEED_10)
4964 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4965 else
4966 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
f07e9af3 4967 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7f97a4bd
MC		 4968 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4969 else
1da177e4
LT		 4970 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4971
7e6c63f0
HM		 4972 /* In order for the 5750 core in BCM4785 chip to work properly
4973 * in RGMII mode, the Led Control Register must be set up.
4974 */
4975 if (tg3_flag(tp, RGMII_MODE)) {
4976 u32 led_ctrl = tr32(MAC_LED_CTRL);
4977 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
4978
4979 if (tp->link_config.active_speed == SPEED_10)
4980 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
4981 else if (tp->link_config.active_speed == SPEED_100)
4982 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
4983 LED_CTRL_100MBPS_ON);
4984 else if (tp->link_config.active_speed == SPEED_1000)
4985 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
4986 LED_CTRL_1000MBPS_ON);
4987
4988 tw32(MAC_LED_CTRL, led_ctrl);
4989 udelay(40);
4990 }
4991
1da177e4
LT		 4992 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4993 if (tp->link_config.active_duplex == DUPLEX_HALF)
4994 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4995
4153577a 4996 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
953c96e0 4997 if (current_link_up &&
e8f3f6ca 4998 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 4999 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 5000 else
5001 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 5002 }
5003
5004 /* ??? Without this setting Netgear GA302T PHY does not
5005 * ??? send/receive packets...
5006 */
79eb6904 5007 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4153577a 5008 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
1da177e4
LT		 5009 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5010 tw32_f(MAC_MI_MODE, tp->mi_mode);
5011 udelay(80);
5012 }
5013
5014 tw32_f(MAC_MODE, tp->mac_mode);
5015 udelay(40);
5016
52b02d04
MC		 5017 tg3_phy_eee_adjust(tp, current_link_up);
5018
63c3a66f 5019 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 5020 /* Polled via timer. */
5021 tw32_f(MAC_EVENT, 0);
5022 } else {
5023 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5024 }
5025 udelay(40);
5026
4153577a 5027 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
953c96e0 5028 current_link_up &&
1da177e4 5029 tp->link_config.active_speed == SPEED_1000 &&
63c3a66f 5030 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
1da177e4
LT		 5031 udelay(120);
5032 tw32_f(MAC_STATUS,
5033 (MAC_STATUS_SYNC_CHANGED |
5034 MAC_STATUS_CFG_CHANGED));
5035 udelay(40);
5036 tg3_write_mem(tp,
5037 NIC_SRAM_FIRMWARE_MBOX,
5038 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5039 }
5040
5e7dfd0f 5041 /* Prevent send BD corruption. */
63c3a66f 5042 if (tg3_flag(tp, CLKREQ_BUG)) {
5e7dfd0f
MC		 5043 if (tp->link_config.active_speed == SPEED_100 ||
5044 tp->link_config.active_speed == SPEED_10)
0f49bfbd
JL		 5045 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5046 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 5047 else
0f49bfbd
JL		 5048 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5049 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f
MC		 5050 }
5051
f4a46d1f 5052 tg3_test_and_report_link_chg(tp, current_link_up);
1da177e4
LT		 5053
5054 return 0;
5055}
5056
5057struct tg3_fiber_aneginfo {
5058 int state;
5059#define ANEG_STATE_UNKNOWN 0
5060#define ANEG_STATE_AN_ENABLE 1
5061#define ANEG_STATE_RESTART_INIT 2
5062#define ANEG_STATE_RESTART 3
5063#define ANEG_STATE_DISABLE_LINK_OK 4
5064#define ANEG_STATE_ABILITY_DETECT_INIT 5
5065#define ANEG_STATE_ABILITY_DETECT 6
5066#define ANEG_STATE_ACK_DETECT_INIT 7
5067#define ANEG_STATE_ACK_DETECT 8
5068#define ANEG_STATE_COMPLETE_ACK_INIT 9
5069#define ANEG_STATE_COMPLETE_ACK 10
5070#define ANEG_STATE_IDLE_DETECT_INIT 11
5071#define ANEG_STATE_IDLE_DETECT 12
5072#define ANEG_STATE_LINK_OK 13
5073#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5074#define ANEG_STATE_NEXT_PAGE_WAIT 15
5075
5076 u32 flags;
5077#define MR_AN_ENABLE 0x00000001
5078#define MR_RESTART_AN 0x00000002
5079#define MR_AN_COMPLETE 0x00000004
5080#define MR_PAGE_RX 0x00000008
5081#define MR_NP_LOADED 0x00000010
5082#define MR_TOGGLE_TX 0x00000020
5083#define MR_LP_ADV_FULL_DUPLEX 0x00000040
5084#define MR_LP_ADV_HALF_DUPLEX 0x00000080
5085#define MR_LP_ADV_SYM_PAUSE 0x00000100
5086#define MR_LP_ADV_ASYM_PAUSE 0x00000200
5087#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5088#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5089#define MR_LP_ADV_NEXT_PAGE 0x00001000
5090#define MR_TOGGLE_RX 0x00002000
5091#define MR_NP_RX 0x00004000
5092
5093#define MR_LINK_OK 0x80000000
5094
5095 unsigned long link_time, cur_time;
5096
5097 u32 ability_match_cfg;
5098 int ability_match_count;
5099
5100 char ability_match, idle_match, ack_match;
5101
5102 u32 txconfig, rxconfig;
5103#define ANEG_CFG_NP 0x00000080
5104#define ANEG_CFG_ACK 0x00000040
5105#define ANEG_CFG_RF2 0x00000020
5106#define ANEG_CFG_RF1 0x00000010
5107#define ANEG_CFG_PS2 0x00000001
5108#define ANEG_CFG_PS1 0x00008000
5109#define ANEG_CFG_HD 0x00004000
5110#define ANEG_CFG_FD 0x00002000
5111#define ANEG_CFG_INVAL 0x00001f06
5112
5113};
5114#define ANEG_OK 0
5115#define ANEG_DONE 1
5116#define ANEG_TIMER_ENAB 2
5117#define ANEG_FAILED -1
5118
5119#define ANEG_STATE_SETTLE_TIME 10000
5120
5121static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5122 struct tg3_fiber_aneginfo *ap)
5123{
5be73b47 5124 u16 flowctrl;
1da177e4
LT		 5125 unsigned long delta;
5126 u32 rx_cfg_reg;
5127 int ret;
5128
5129 if (ap->state == ANEG_STATE_UNKNOWN) {
5130 ap->rxconfig = 0;
5131 ap->link_time = 0;
5132 ap->cur_time = 0;
5133 ap->ability_match_cfg = 0;
5134 ap->ability_match_count = 0;
5135 ap->ability_match = 0;
5136 ap->idle_match = 0;
5137 ap->ack_match = 0;
5138 }
5139 ap->cur_time++;
5140
5141 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5142 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5143
5144 if (rx_cfg_reg != ap->ability_match_cfg) {
5145 ap->ability_match_cfg = rx_cfg_reg;
5146 ap->ability_match = 0;
5147 ap->ability_match_count = 0;
5148 } else {
5149 if (++ap->ability_match_count > 1) {
5150 ap->ability_match = 1;
5151 ap->ability_match_cfg = rx_cfg_reg;
5152 }
5153 }
5154 if (rx_cfg_reg & ANEG_CFG_ACK)
5155 ap->ack_match = 1;
5156 else
5157 ap->ack_match = 0;
5158
5159 ap->idle_match = 0;
5160 } else {
5161 ap->idle_match = 1;
5162 ap->ability_match_cfg = 0;
5163 ap->ability_match_count = 0;
5164 ap->ability_match = 0;
5165 ap->ack_match = 0;
5166
5167 rx_cfg_reg = 0;
5168 }
5169
5170 ap->rxconfig = rx_cfg_reg;
5171 ret = ANEG_OK;
5172
33f401ae 5173 switch (ap->state) {
1da177e4
LT		 5174 case ANEG_STATE_UNKNOWN:
5175 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5176 ap->state = ANEG_STATE_AN_ENABLE;
5177
5178 /* fallthru */
5179 case ANEG_STATE_AN_ENABLE:
5180 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5181 if (ap->flags & MR_AN_ENABLE) {
5182 ap->link_time = 0;
5183 ap->cur_time = 0;
5184 ap->ability_match_cfg = 0;
5185 ap->ability_match_count = 0;
5186 ap->ability_match = 0;
5187 ap->idle_match = 0;
5188 ap->ack_match = 0;
5189
5190 ap->state = ANEG_STATE_RESTART_INIT;
5191 } else {
5192 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5193 }
5194 break;
5195
5196 case ANEG_STATE_RESTART_INIT:
5197 ap->link_time = ap->cur_time;
5198 ap->flags &= ~(MR_NP_LOADED);
5199 ap->txconfig = 0;
5200 tw32(MAC_TX_AUTO_NEG, 0);
5201 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5202 tw32_f(MAC_MODE, tp->mac_mode);
5203 udelay(40);
5204
5205 ret = ANEG_TIMER_ENAB;
5206 ap->state = ANEG_STATE_RESTART;
5207
5208 /* fallthru */
5209 case ANEG_STATE_RESTART:
5210 delta = ap->cur_time - ap->link_time;
859a5887 5211 if (delta > ANEG_STATE_SETTLE_TIME)
1da177e4 5212 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
859a5887 5213 else
1da177e4 5214 ret = ANEG_TIMER_ENAB;
1da177e4
LT		 5215 break;
5216
5217 case ANEG_STATE_DISABLE_LINK_OK:
5218 ret = ANEG_DONE;
5219 break;
5220
5221 case ANEG_STATE_ABILITY_DETECT_INIT:
5222 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 5223 ap->txconfig = ANEG_CFG_FD;
5224 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5225 if (flowctrl & ADVERTISE_1000XPAUSE)
5226 ap->txconfig |= ANEG_CFG_PS1;
5227 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5228 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 5229 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5230 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5231 tw32_f(MAC_MODE, tp->mac_mode);
5232 udelay(40);
5233
5234 ap->state = ANEG_STATE_ABILITY_DETECT;
5235 break;
5236
5237 case ANEG_STATE_ABILITY_DETECT:
859a5887 5238 if (ap->ability_match != 0 && ap->rxconfig != 0)
1da177e4 5239 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1da177e4
LT		 5240 break;
5241
5242 case ANEG_STATE_ACK_DETECT_INIT:
5243 ap->txconfig |= ANEG_CFG_ACK;
5244 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5245 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5246 tw32_f(MAC_MODE, tp->mac_mode);
5247 udelay(40);
5248
5249 ap->state = ANEG_STATE_ACK_DETECT;
5250
5251 /* fallthru */
5252 case ANEG_STATE_ACK_DETECT:
5253 if (ap->ack_match != 0) {
5254 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5255 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5256 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5257 } else {
5258 ap->state = ANEG_STATE_AN_ENABLE;
5259 }
5260 } else if (ap->ability_match != 0 &&
5261 ap->rxconfig == 0) {
5262 ap->state = ANEG_STATE_AN_ENABLE;
5263 }
5264 break;
5265
5266 case ANEG_STATE_COMPLETE_ACK_INIT:
5267 if (ap->rxconfig & ANEG_CFG_INVAL) {
5268 ret = ANEG_FAILED;
5269 break;
5270 }
5271 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5272 MR_LP_ADV_HALF_DUPLEX |
5273 MR_LP_ADV_SYM_PAUSE |
5274 MR_LP_ADV_ASYM_PAUSE |
5275 MR_LP_ADV_REMOTE_FAULT1 |
5276 MR_LP_ADV_REMOTE_FAULT2 |
5277 MR_LP_ADV_NEXT_PAGE |
5278 MR_TOGGLE_RX |
5279 MR_NP_RX);
5280 if (ap->rxconfig & ANEG_CFG_FD)
5281 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5282 if (ap->rxconfig & ANEG_CFG_HD)
5283 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5284 if (ap->rxconfig & ANEG_CFG_PS1)
5285 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5286 if (ap->rxconfig & ANEG_CFG_PS2)
5287 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5288 if (ap->rxconfig & ANEG_CFG_RF1)
5289 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5290 if (ap->rxconfig & ANEG_CFG_RF2)
5291 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5292 if (ap->rxconfig & ANEG_CFG_NP)
5293 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5294
5295 ap->link_time = ap->cur_time;
5296
5297 ap->flags ^= (MR_TOGGLE_TX);
5298 if (ap->rxconfig & 0x0008)
5299 ap->flags |= MR_TOGGLE_RX;
5300 if (ap->rxconfig & ANEG_CFG_NP)
5301 ap->flags |= MR_NP_RX;
5302 ap->flags |= MR_PAGE_RX;
5303
5304 ap->state = ANEG_STATE_COMPLETE_ACK;
5305 ret = ANEG_TIMER_ENAB;
5306 break;
5307
5308 case ANEG_STATE_COMPLETE_ACK:
5309 if (ap->ability_match != 0 &&
5310 ap->rxconfig == 0) {
5311 ap->state = ANEG_STATE_AN_ENABLE;
5312 break;
5313 }
5314 delta = ap->cur_time - ap->link_time;
5315 if (delta > ANEG_STATE_SETTLE_TIME) {
5316 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5317 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5318 } else {
5319 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5320 !(ap->flags & MR_NP_RX)) {
5321 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5322 } else {
5323 ret = ANEG_FAILED;
5324 }
5325 }
5326 }
5327 break;
5328
5329 case ANEG_STATE_IDLE_DETECT_INIT:
5330 ap->link_time = ap->cur_time;
5331 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5332 tw32_f(MAC_MODE, tp->mac_mode);
5333 udelay(40);
5334
5335 ap->state = ANEG_STATE_IDLE_DETECT;
5336 ret = ANEG_TIMER_ENAB;
5337 break;
5338
5339 case ANEG_STATE_IDLE_DETECT:
5340 if (ap->ability_match != 0 &&
5341 ap->rxconfig == 0) {
5342 ap->state = ANEG_STATE_AN_ENABLE;
5343 break;
5344 }
5345 delta = ap->cur_time - ap->link_time;
5346 if (delta > ANEG_STATE_SETTLE_TIME) {
5347 /* XXX another gem from the Broadcom driver :( */
5348 ap->state = ANEG_STATE_LINK_OK;
5349 }
5350 break;
5351
5352 case ANEG_STATE_LINK_OK:
5353 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5354 ret = ANEG_DONE;
5355 break;
5356
5357 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5358 /* ??? unimplemented */
5359 break;
5360
5361 case ANEG_STATE_NEXT_PAGE_WAIT:
5362 /* ??? unimplemented */
5363 break;
5364
5365 default:
5366 ret = ANEG_FAILED;
5367 break;
855e1111 5368 }
1da177e4
LT		 5369
5370 return ret;
5371}
5372
5be73b47 5373static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 5374{
5375 int res = 0;
5376 struct tg3_fiber_aneginfo aninfo;
5377 int status = ANEG_FAILED;
5378 unsigned int tick;
5379 u32 tmp;
5380
5381 tw32_f(MAC_TX_AUTO_NEG, 0);
5382
5383 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5384 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5385 udelay(40);
5386
5387 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5388 udelay(40);
5389
5390 memset(&aninfo, 0, sizeof(aninfo));
5391 aninfo.flags |= MR_AN_ENABLE;
5392 aninfo.state = ANEG_STATE_UNKNOWN;
5393 aninfo.cur_time = 0;
5394 tick = 0;
5395 while (++tick < 195000) {
5396 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5397 if (status == ANEG_DONE || status == ANEG_FAILED)
5398 break;
5399
5400 udelay(1);
5401 }
5402
5403 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5404 tw32_f(MAC_MODE, tp->mac_mode);
5405 udelay(40);
5406
5be73b47
MC		 5407 *txflags = aninfo.txconfig;
5408 *rxflags = aninfo.flags;
1da177e4
LT		 5409
5410 if (status == ANEG_DONE &&
5411 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5412 MR_LP_ADV_FULL_DUPLEX)))
5413 res = 1;
5414
5415 return res;
5416}
5417
5418static void tg3_init_bcm8002(struct tg3 *tp)
5419{
5420 u32 mac_status = tr32(MAC_STATUS);
5421 int i;
5422
5423 /* Reset when initting first time or we have a link. */
63c3a66f 5424 if (tg3_flag(tp, INIT_COMPLETE) &&
1da177e4
LT		 5425 !(mac_status & MAC_STATUS_PCS_SYNCED))
5426 return;
5427
5428 /* Set PLL lock range. */
5429 tg3_writephy(tp, 0x16, 0x8007);
5430
5431 /* SW reset */
5432 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5433
5434 /* Wait for reset to complete. */
5435 /* XXX schedule_timeout() ... */
5436 for (i = 0; i < 500; i++)
5437 udelay(10);
5438
5439 /* Config mode; select PMA/Ch 1 regs. */
5440 tg3_writephy(tp, 0x10, 0x8411);
5441
5442 /* Enable auto-lock and comdet, select txclk for tx. */
5443 tg3_writephy(tp, 0x11, 0x0a10);
5444
5445 tg3_writephy(tp, 0x18, 0x00a0);
5446 tg3_writephy(tp, 0x16, 0x41ff);
5447
5448 /* Assert and deassert POR. */
5449 tg3_writephy(tp, 0x13, 0x0400);
5450 udelay(40);
5451 tg3_writephy(tp, 0x13, 0x0000);
5452
5453 tg3_writephy(tp, 0x11, 0x0a50);
5454 udelay(40);
5455 tg3_writephy(tp, 0x11, 0x0a10);
5456
5457 /* Wait for signal to stabilize */
5458 /* XXX schedule_timeout() ... */
5459 for (i = 0; i < 15000; i++)
5460 udelay(10);
5461
5462 /* Deselect the channel register so we can read the PHYID
5463 * later.
5464 */
5465 tg3_writephy(tp, 0x10, 0x8011);
5466}
5467
953c96e0 5468static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
1da177e4 5469{
82cd3d11 5470 u16 flowctrl;
953c96e0 5471 bool current_link_up;
1da177e4
LT		 5472 u32 sg_dig_ctrl, sg_dig_status;
5473 u32 serdes_cfg, expected_sg_dig_ctrl;
5474 int workaround, port_a;
1da177e4
LT		 5475
5476 serdes_cfg = 0;
5477 expected_sg_dig_ctrl = 0;
5478 workaround = 0;
5479 port_a = 1;
953c96e0 5480 current_link_up = false;
1da177e4 5481
4153577a
JP		 5482 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5483 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
1da177e4
LT		 5484 workaround = 1;
5485 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5486 port_a = 0;
5487
5488 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5489 /* preserve bits 20-23 for voltage regulator */
5490 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5491 }
5492
5493 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5494
5495 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 5496 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 5497 if (workaround) {
5498 u32 val = serdes_cfg;
5499
5500 if (port_a)
5501 val |= 0xc010000;
5502 else
5503 val |= 0x4010000;
5504 tw32_f(MAC_SERDES_CFG, val);
5505 }
c98f6e3b
MC		 5506
5507 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5508 }
5509 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5510 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5511 current_link_up = true;
1da177e4
LT		 5512 }
5513 goto out;
5514 }
5515
5516 /* Want auto-negotiation. */
c98f6e3b 5517 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 5518
82cd3d11
MC		 5519 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5520 if (flowctrl & ADVERTISE_1000XPAUSE)
5521 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5522 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5523 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 5524
5525 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
f07e9af3 5526 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3d3ebe74
MC		 5527 tp->serdes_counter &&
5528 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5529 MAC_STATUS_RCVD_CFG)) ==
5530 MAC_STATUS_PCS_SYNCED)) {
5531 tp->serdes_counter--;
953c96e0 5532 current_link_up = true;
3d3ebe74
MC		 5533 goto out;
5534 }
5535restart_autoneg:
1da177e4
LT		 5536 if (workaround)
5537 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 5538 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 5539 udelay(5);
5540 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5541
3d3ebe74 5542 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5543 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5544 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5545 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 5546 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 5547 mac_status = tr32(MAC_STATUS);
5548
c98f6e3b 5549 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 5550 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 5551 u32 local_adv = 0, remote_adv = 0;
5552
5553 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5554 local_adv |= ADVERTISE_1000XPAUSE;
5555 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5556 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 5557
c98f6e3b 5558 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 5559 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 5560 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 5561 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5562
859edb26
MC		 5563 tp->link_config.rmt_adv =
5564 mii_adv_to_ethtool_adv_x(remote_adv);
5565
1da177e4 5566 tg3_setup_flow_control(tp, local_adv, remote_adv);
953c96e0 5567 current_link_up = true;
3d3ebe74 5568 tp->serdes_counter = 0;
f07e9af3 5569 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c98f6e3b 5570 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 5571 if (tp->serdes_counter)
5572 tp->serdes_counter--;
1da177e4
LT		 5573 else {
5574 if (workaround) {
5575 u32 val = serdes_cfg;
5576
5577 if (port_a)
5578 val |= 0xc010000;
5579 else
5580 val |= 0x4010000;
5581
5582 tw32_f(MAC_SERDES_CFG, val);
5583 }
5584
c98f6e3b 5585 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5586 udelay(40);
5587
5588 /* Link parallel detection - link is up */
5589 /* only if we have PCS_SYNC and not */
5590 /* receiving config code words */
5591 mac_status = tr32(MAC_STATUS);
5592 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5593 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5594 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5595 current_link_up = true;
f07e9af3
MC		 5596 tp->phy_flags |=
5597 TG3_PHYFLG_PARALLEL_DETECT;
3d3ebe74
MC		 5598 tp->serdes_counter =
5599 SERDES_PARALLEL_DET_TIMEOUT;
5600 } else
5601 goto restart_autoneg;
1da177e4
LT		 5602 }
5603 }
3d3ebe74
MC		 5604 } else {
5605 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5606 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5607 }
5608
5609out:
5610 return current_link_up;
5611}
5612
953c96e0 5613static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
1da177e4 5614{
953c96e0 5615 bool current_link_up = false;
1da177e4 5616
5cf64b8a 5617 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 5618 goto out;
1da177e4
LT		 5619
5620 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 5621 u32 txflags, rxflags;
1da177e4 5622 int i;
6aa20a22 5623
5be73b47
MC		 5624 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5625 u32 local_adv = 0, remote_adv = 0;
1da177e4 5626
5be73b47
MC		 5627 if (txflags & ANEG_CFG_PS1)
5628 local_adv |= ADVERTISE_1000XPAUSE;
5629 if (txflags & ANEG_CFG_PS2)
5630 local_adv |= ADVERTISE_1000XPSE_ASYM;
5631
5632 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5633 remote_adv |= LPA_1000XPAUSE;
5634 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5635 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5636
859edb26
MC		 5637 tp->link_config.rmt_adv =
5638 mii_adv_to_ethtool_adv_x(remote_adv);
5639
1da177e4
LT		 5640 tg3_setup_flow_control(tp, local_adv, remote_adv);
5641
953c96e0 5642 current_link_up = true;
1da177e4
LT		 5643 }
5644 for (i = 0; i < 30; i++) {
5645 udelay(20);
5646 tw32_f(MAC_STATUS,
5647 (MAC_STATUS_SYNC_CHANGED |
5648 MAC_STATUS_CFG_CHANGED));
5649 udelay(40);
5650 if ((tr32(MAC_STATUS) &
5651 (MAC_STATUS_SYNC_CHANGED |
5652 MAC_STATUS_CFG_CHANGED)) == 0)
5653 break;
5654 }
5655
5656 mac_status = tr32(MAC_STATUS);
953c96e0 5657 if (!current_link_up &&
1da177e4
LT		 5658 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5659 !(mac_status & MAC_STATUS_RCVD_CFG))
953c96e0 5660 current_link_up = true;
1da177e4 5661 } else {
5be73b47
MC		 5662 tg3_setup_flow_control(tp, 0, 0);
5663
1da177e4 5664 /* Forcing 1000FD link up. */
953c96e0 5665 current_link_up = true;
1da177e4
LT		 5666
5667 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5668 udelay(40);
e8f3f6ca
MC		 5669
5670 tw32_f(MAC_MODE, tp->mac_mode);
5671 udelay(40);
1da177e4
LT		 5672 }
5673
5674out:
5675 return current_link_up;
5676}
5677
953c96e0 5678static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
1da177e4
LT		 5679{
5680 u32 orig_pause_cfg;
5681 u16 orig_active_speed;
5682 u8 orig_active_duplex;
5683 u32 mac_status;
953c96e0 5684 bool current_link_up;
1da177e4
LT		 5685 int i;
5686
8d018621 5687 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5688 orig_active_speed = tp->link_config.active_speed;
5689 orig_active_duplex = tp->link_config.active_duplex;
5690
63c3a66f 5691 if (!tg3_flag(tp, HW_AUTONEG) &&
f4a46d1f 5692 tp->link_up &&
63c3a66f 5693 tg3_flag(tp, INIT_COMPLETE)) {
1da177e4
LT		 5694 mac_status = tr32(MAC_STATUS);
5695 mac_status &= (MAC_STATUS_PCS_SYNCED |
5696 MAC_STATUS_SIGNAL_DET |
5697 MAC_STATUS_CFG_CHANGED |
5698 MAC_STATUS_RCVD_CFG);
5699 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5700 MAC_STATUS_SIGNAL_DET)) {
5701 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5702 MAC_STATUS_CFG_CHANGED));
5703 return 0;
5704 }
5705 }
5706
5707 tw32_f(MAC_TX_AUTO_NEG, 0);
5708
5709 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5710 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5711 tw32_f(MAC_MODE, tp->mac_mode);
5712 udelay(40);
5713
79eb6904 5714 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 5715 tg3_init_bcm8002(tp);
5716
5717 /* Enable link change event even when serdes polling. */
5718 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5719 udelay(40);
5720
953c96e0 5721 current_link_up = false;
859edb26 5722 tp->link_config.rmt_adv = 0;
1da177e4
LT		 5723 mac_status = tr32(MAC_STATUS);
5724
63c3a66f 5725 if (tg3_flag(tp, HW_AUTONEG))
1da177e4
LT		 5726 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5727 else
5728 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5729
898a56f8 5730 tp->napi[0].hw_status->status =
1da177e4 5731 (SD_STATUS_UPDATED |
898a56f8 5732 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 5733
5734 for (i = 0; i < 100; i++) {
5735 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5736 MAC_STATUS_CFG_CHANGED));
5737 udelay(5);
5738 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 5739 MAC_STATUS_CFG_CHANGED |
5740 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 5741 break;
5742 }
5743
5744 mac_status = tr32(MAC_STATUS);
5745 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
953c96e0 5746 current_link_up = false;
3d3ebe74
MC		 5747 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5748 tp->serdes_counter == 0) {
1da177e4
LT		 5749 tw32_f(MAC_MODE, (tp->mac_mode |
5750 MAC_MODE_SEND_CONFIGS));
5751 udelay(1);
5752 tw32_f(MAC_MODE, tp->mac_mode);
5753 }
5754 }
5755
953c96e0 5756 if (current_link_up) {
1da177e4
LT		 5757 tp->link_config.active_speed = SPEED_1000;
5758 tp->link_config.active_duplex = DUPLEX_FULL;
5759 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5760 LED_CTRL_LNKLED_OVERRIDE |
5761 LED_CTRL_1000MBPS_ON));
5762 } else {
e740522e
MC		 5763 tp->link_config.active_speed = SPEED_UNKNOWN;
5764 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 5765 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5766 LED_CTRL_LNKLED_OVERRIDE |
5767 LED_CTRL_TRAFFIC_OVERRIDE));
5768 }
5769
f4a46d1f 5770 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
8d018621 5771 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5772 if (orig_pause_cfg != now_pause_cfg ||
5773 orig_active_speed != tp->link_config.active_speed ||
5774 orig_active_duplex != tp->link_config.active_duplex)
5775 tg3_link_report(tp);
5776 }
5777
5778 return 0;
5779}
5780
953c96e0 5781static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
747e8f8b 5782{
953c96e0 5783 int err = 0;
747e8f8b 5784 u32 bmsr, bmcr;
85730a63
MC		 5785 u16 current_speed = SPEED_UNKNOWN;
5786 u8 current_duplex = DUPLEX_UNKNOWN;
953c96e0 5787 bool current_link_up = false;
85730a63
MC		 5788 u32 local_adv, remote_adv, sgsr;
5789
5790 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5791 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5792 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5793 (sgsr & SERDES_TG3_SGMII_MODE)) {
5794
5795 if (force_reset)
5796 tg3_phy_reset(tp);
5797
5798 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5799
5800 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5801 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5802 } else {
953c96e0 5803 current_link_up = true;
85730a63
MC		 5804 if (sgsr & SERDES_TG3_SPEED_1000) {
5805 current_speed = SPEED_1000;
5806 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5807 } else if (sgsr & SERDES_TG3_SPEED_100) {
5808 current_speed = SPEED_100;
5809 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5810 } else {
5811 current_speed = SPEED_10;
5812 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5813 }
5814
5815 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5816 current_duplex = DUPLEX_FULL;
5817 else
5818 current_duplex = DUPLEX_HALF;
5819 }
5820
5821 tw32_f(MAC_MODE, tp->mac_mode);
5822 udelay(40);
5823
5824 tg3_clear_mac_status(tp);
5825
5826 goto fiber_setup_done;
5827 }
747e8f8b
MC		 5828
5829 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5830 tw32_f(MAC_MODE, tp->mac_mode);
5831 udelay(40);
5832
3310e248 5833 tg3_clear_mac_status(tp);
747e8f8b
MC		 5834
5835 if (force_reset)
5836 tg3_phy_reset(tp);
5837
859edb26 5838 tp->link_config.rmt_adv = 0;
747e8f8b
MC		 5839
5840 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5841 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5842 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5843 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5844 bmsr |= BMSR_LSTATUS;
5845 else
5846 bmsr &= ~BMSR_LSTATUS;
5847 }
747e8f8b
MC		 5848
5849 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5850
5851 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
f07e9af3 5852 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 5853 /* do nothing, just check for link up at the end */
5854 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
28011cf1 5855 u32 adv, newadv;
747e8f8b
MC		 5856
5857 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
28011cf1
MC		 5858 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5859 ADVERTISE_1000XPAUSE |
5860 ADVERTISE_1000XPSE_ASYM |
5861 ADVERTISE_SLCT);
747e8f8b 5862
28011cf1 5863 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
37f07023 5864 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
747e8f8b 5865
28011cf1
MC		 5866 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5867 tg3_writephy(tp, MII_ADVERTISE, newadv);
747e8f8b
MC		 5868 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5869 tg3_writephy(tp, MII_BMCR, bmcr);
5870
5871 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 5872 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
f07e9af3 5873 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5874
5875 return err;
5876 }
5877 } else {
5878 u32 new_bmcr;
5879
5880 bmcr &= ~BMCR_SPEED1000;
5881 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5882
5883 if (tp->link_config.duplex == DUPLEX_FULL)
5884 new_bmcr |= BMCR_FULLDPLX;
5885
5886 if (new_bmcr != bmcr) {
5887 /* BMCR_SPEED1000 is a reserved bit that needs
5888 * to be set on write.
5889 */
5890 new_bmcr |= BMCR_SPEED1000;
5891
5892 /* Force a linkdown */
f4a46d1f 5893 if (tp->link_up) {
747e8f8b
MC		 5894 u32 adv;
5895
5896 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5897 adv &= ~(ADVERTISE_1000XFULL |
5898 ADVERTISE_1000XHALF |
5899 ADVERTISE_SLCT);
5900 tg3_writephy(tp, MII_ADVERTISE, adv);
5901 tg3_writephy(tp, MII_BMCR, bmcr |
5902 BMCR_ANRESTART |
5903 BMCR_ANENABLE);
5904 udelay(10);
f4a46d1f 5905 tg3_carrier_off(tp);
747e8f8b
MC		 5906 }
5907 tg3_writephy(tp, MII_BMCR, new_bmcr);
5908 bmcr = new_bmcr;
5909 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5910 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5911 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5912 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5913 bmsr |= BMSR_LSTATUS;
5914 else
5915 bmsr &= ~BMSR_LSTATUS;
5916 }
f07e9af3 5917 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5918 }
5919 }
5920
5921 if (bmsr & BMSR_LSTATUS) {
5922 current_speed = SPEED_1000;
953c96e0 5923 current_link_up = true;
747e8f8b
MC		 5924 if (bmcr & BMCR_FULLDPLX)
5925 current_duplex = DUPLEX_FULL;
5926 else
5927 current_duplex = DUPLEX_HALF;
5928
ef167e27
MC		 5929 local_adv = 0;
5930 remote_adv = 0;
5931
747e8f8b 5932 if (bmcr & BMCR_ANENABLE) {
ef167e27 5933 u32 common;
747e8f8b
MC		 5934
5935 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5936 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5937 common = local_adv & remote_adv;
5938 if (common & (ADVERTISE_1000XHALF |
5939 ADVERTISE_1000XFULL)) {
5940 if (common & ADVERTISE_1000XFULL)
5941 current_duplex = DUPLEX_FULL;
5942 else
5943 current_duplex = DUPLEX_HALF;
859edb26
MC		 5944
5945 tp->link_config.rmt_adv =
5946 mii_adv_to_ethtool_adv_x(remote_adv);
63c3a66f 5947 } else if (!tg3_flag(tp, 5780_CLASS)) {
57d8b880 5948 /* Link is up via parallel detect */
859a5887 5949 } else {
953c96e0 5950 current_link_up = false;
859a5887 5951 }
747e8f8b
MC		 5952 }
5953 }
5954
85730a63 5955fiber_setup_done:
953c96e0 5956 if (current_link_up && current_duplex == DUPLEX_FULL)
ef167e27
MC		 5957 tg3_setup_flow_control(tp, local_adv, remote_adv);
5958
747e8f8b
MC		 5959 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5960 if (tp->link_config.active_duplex == DUPLEX_HALF)
5961 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5962
5963 tw32_f(MAC_MODE, tp->mac_mode);
5964 udelay(40);
5965
5966 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5967
5968 tp->link_config.active_speed = current_speed;
5969 tp->link_config.active_duplex = current_duplex;
5970
f4a46d1f 5971 tg3_test_and_report_link_chg(tp, current_link_up);
747e8f8b
MC		 5972 return err;
5973}
5974
5975static void tg3_serdes_parallel_detect(struct tg3 *tp)
5976{
3d3ebe74 5977 if (tp->serdes_counter) {
747e8f8b 5978 /* Give autoneg time to complete. */
3d3ebe74 5979 tp->serdes_counter--;
747e8f8b
MC		 5980 return;
5981 }
c6cdf436 5982
f4a46d1f 5983 if (!tp->link_up &&
747e8f8b
MC		 5984 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5985 u32 bmcr;
5986
5987 tg3_readphy(tp, MII_BMCR, &bmcr);
5988 if (bmcr & BMCR_ANENABLE) {
5989 u32 phy1, phy2;
5990
5991 /* Select shadow register 0x1f */
f08aa1a8
MC		 5992 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5993 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
747e8f8b
MC		 5994
5995 /* Select expansion interrupt status register */
f08aa1a8
MC		 5996 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5997 MII_TG3_DSP_EXP1_INT_STAT);
5998 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5999 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6000
6001 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6002 /* We have signal detect and not receiving
6003 * config code words, link is up by parallel
6004 * detection.
6005 */
6006
6007 bmcr &= ~BMCR_ANENABLE;
6008 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6009 tg3_writephy(tp, MII_BMCR, bmcr);
f07e9af3 6010 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6011 }
6012 }
f4a46d1f 6013 } else if (tp->link_up &&
859a5887 6014 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
f07e9af3 6015 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 6016 u32 phy2;
6017
6018 /* Select expansion interrupt status register */
f08aa1a8
MC		 6019 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6020 MII_TG3_DSP_EXP1_INT_STAT);
6021 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6022 if (phy2 & 0x20) {
6023 u32 bmcr;
6024
6025 /* Config code words received, turn on autoneg. */
6026 tg3_readphy(tp, MII_BMCR, &bmcr);
6027 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6028
f07e9af3 6029 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6030
6031 }
6032 }
6033}
6034
953c96e0 6035static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
1da177e4 6036{
f2096f94 6037 u32 val;
1da177e4
LT		 6038 int err;
6039
f07e9af3 6040 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4 6041 err = tg3_setup_fiber_phy(tp, force_reset);
f07e9af3 6042 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
747e8f8b 6043 err = tg3_setup_fiber_mii_phy(tp, force_reset);
859a5887 6044 else
1da177e4 6045 err = tg3_setup_copper_phy(tp, force_reset);
1da177e4 6046
4153577a 6047 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
f2096f94 6048 u32 scale;
aa6c91fe
MC		 6049
6050 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6051 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6052 scale = 65;
6053 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6054 scale = 6;
6055 else
6056 scale = 12;
6057
6058 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6059 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6060 tw32(GRC_MISC_CFG, val);
6061 }
6062
f2096f94
MC		 6063 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6064 (6 << TX_LENGTHS_IPG_SHIFT);
4153577a
JP		 6065 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6066 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 6067 val |= tr32(MAC_TX_LENGTHS) &
6068 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6069 TX_LENGTHS_CNT_DWN_VAL_MSK);
6070
1da177e4
LT		 6071 if (tp->link_config.active_speed == SPEED_1000 &&
6072 tp->link_config.active_duplex == DUPLEX_HALF)
f2096f94
MC		 6073 tw32(MAC_TX_LENGTHS, val |
6074 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6075 else
f2096f94
MC		 6076 tw32(MAC_TX_LENGTHS, val |
6077 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6078
63c3a66f 6079 if (!tg3_flag(tp, 5705_PLUS)) {
f4a46d1f 6080 if (tp->link_up) {
1da177e4 6081 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 6082 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 6083 } else {
6084 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6085 }
6086 }
6087
63c3a66f 6088 if (tg3_flag(tp, ASPM_WORKAROUND)) {
f2096f94 6089 val = tr32(PCIE_PWR_MGMT_THRESH);
f4a46d1f 6090 if (!tp->link_up)
8ed5d97e
MC		 6091 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6092 tp->pwrmgmt_thresh;
6093 else
6094 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6095 tw32(PCIE_PWR_MGMT_THRESH, val);
6096 }
6097
1da177e4
LT		 6098 return err;
6099}
6100
7d41e49a
MC		 6101/* tp->lock must be held */
6102static u64 tg3_refclk_read(struct tg3 *tp)
6103{
6104 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6105 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6106}
6107
be947307
MC		 6108/* tp->lock must be held */
6109static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6110{
92e6457d
NS		 6111 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6112
6113 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
be947307
MC		 6114 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6115 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
92e6457d 6116 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
be947307
MC		 6117}
6118
7d41e49a
MC		 6119static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6120static inline void tg3_full_unlock(struct tg3 *tp);
6121static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6122{
6123 struct tg3 *tp = netdev_priv(dev);
6124
6125 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6126 SOF_TIMESTAMPING_RX_SOFTWARE |
f233a976
FL		 6127 SOF_TIMESTAMPING_SOFTWARE;
6128
6129 if (tg3_flag(tp, PTP_CAPABLE)) {
32e19272 6130 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
f233a976
FL		 6131 SOF_TIMESTAMPING_RX_HARDWARE |
6132 SOF_TIMESTAMPING_RAW_HARDWARE;
6133 }
7d41e49a
MC		 6134
6135 if (tp->ptp_clock)
6136 info->phc_index = ptp_clock_index(tp->ptp_clock);
6137 else
6138 info->phc_index = -1;
6139
6140 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6141
6142 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6143 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6144 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6145 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6146 return 0;
6147}
6148
6149static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6150{
6151 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6152 bool neg_adj = false;
6153 u32 correction = 0;
6154
6155 if (ppb < 0) {
6156 neg_adj = true;
6157 ppb = -ppb;
6158 }
6159
6160 /* Frequency adjustment is performed using hardware with a 24 bit
6161 * accumulator and a programmable correction value. On each clk, the
6162 * correction value gets added to the accumulator and when it
6163 * overflows, the time counter is incremented/decremented.
6164 *
6165 * So conversion from ppb to correction value is
6166 * ppb * (1 << 24) / 1000000000
6167 */
6168 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6169 TG3_EAV_REF_CLK_CORRECT_MASK;
6170
6171 tg3_full_lock(tp, 0);
6172
6173 if (correction)
6174 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6175 TG3_EAV_REF_CLK_CORRECT_EN |
6176 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6177 else
6178 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6179
6180 tg3_full_unlock(tp);
6181
6182 return 0;
6183}
6184
6185static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6186{
6187 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6188
6189 tg3_full_lock(tp, 0);
6190 tp->ptp_adjust += delta;
6191 tg3_full_unlock(tp);
6192
6193 return 0;
6194}
6195
6196static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6197{
6198 u64 ns;
6199 u32 remainder;
6200 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6201
6202 tg3_full_lock(tp, 0);
6203 ns = tg3_refclk_read(tp);
6204 ns += tp->ptp_adjust;
6205 tg3_full_unlock(tp);
6206
6207 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6208 ts->tv_nsec = remainder;
6209
6210 return 0;
6211}
6212
6213static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6214 const struct timespec *ts)
6215{
6216 u64 ns;
6217 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6218
6219 ns = timespec_to_ns(ts);
6220
6221 tg3_full_lock(tp, 0);
6222 tg3_refclk_write(tp, ns);
6223 tp->ptp_adjust = 0;
6224 tg3_full_unlock(tp);
6225
6226 return 0;
6227}
6228
6229static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6230 struct ptp_clock_request *rq, int on)
6231{
92e6457d
NS		 6232 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6233 u32 clock_ctl;
6234 int rval = 0;
6235
6236 switch (rq->type) {
6237 case PTP_CLK_REQ_PEROUT:
6238 if (rq->perout.index != 0)
6239 return -EINVAL;
6240
6241 tg3_full_lock(tp, 0);
6242 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6243 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6244
6245 if (on) {
6246 u64 nsec;
6247
6248 nsec = rq->perout.start.sec * 1000000000ULL +
6249 rq->perout.start.nsec;
6250
6251 if (rq->perout.period.sec || rq->perout.period.nsec) {
6252 netdev_warn(tp->dev,
6253 "Device supports only a one-shot timesync output, period must be 0\n");
6254 rval = -EINVAL;
6255 goto err_out;
6256 }
6257
6258 if (nsec & (1ULL << 63)) {
6259 netdev_warn(tp->dev,
6260 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6261 rval = -EINVAL;
6262 goto err_out;
6263 }
6264
6265 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6266 tw32(TG3_EAV_WATCHDOG0_MSB,
6267 TG3_EAV_WATCHDOG0_EN |
6268 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6269
6270 tw32(TG3_EAV_REF_CLCK_CTL,
6271 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6272 } else {
6273 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6274 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6275 }
6276
6277err_out:
6278 tg3_full_unlock(tp);
6279 return rval;
6280
6281 default:
6282 break;
6283 }
6284
7d41e49a
MC		 6285 return -EOPNOTSUPP;
6286}
6287
6288static const struct ptp_clock_info tg3_ptp_caps = {
6289 .owner = THIS_MODULE,
6290 .name = "tg3 clock",
6291 .max_adj = 250000000,
6292 .n_alarm = 0,
6293 .n_ext_ts = 0,
92e6457d 6294 .n_per_out = 1,
7d41e49a
MC		 6295 .pps = 0,
6296 .adjfreq = tg3_ptp_adjfreq,
6297 .adjtime = tg3_ptp_adjtime,
6298 .gettime = tg3_ptp_gettime,
6299 .settime = tg3_ptp_settime,
6300 .enable = tg3_ptp_enable,
6301};
6302
fb4ce8ad
MC		 6303static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6304 struct skb_shared_hwtstamps *timestamp)
6305{
6306 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6307 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6308 tp->ptp_adjust);
6309}
6310
be947307
MC		 6311/* tp->lock must be held */
6312static void tg3_ptp_init(struct tg3 *tp)
6313{
6314 if (!tg3_flag(tp, PTP_CAPABLE))
6315 return;
6316
6317 /* Initialize the hardware clock to the system time. */
6318 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6319 tp->ptp_adjust = 0;
7d41e49a 6320 tp->ptp_info = tg3_ptp_caps;
be947307
MC		 6321}
6322
6323/* tp->lock must be held */
6324static void tg3_ptp_resume(struct tg3 *tp)
6325{
6326 if (!tg3_flag(tp, PTP_CAPABLE))
6327 return;
6328
6329 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6330 tp->ptp_adjust = 0;
6331}
6332
6333static void tg3_ptp_fini(struct tg3 *tp)
6334{
6335 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6336 return;
6337
7d41e49a 6338 ptp_clock_unregister(tp->ptp_clock);
be947307
MC		 6339 tp->ptp_clock = NULL;
6340 tp->ptp_adjust = 0;
6341}
6342
66cfd1bd
MC		 6343static inline int tg3_irq_sync(struct tg3 *tp)
6344{
6345 return tp->irq_sync;
6346}
6347
97bd8e49
MC		 6348static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6349{
6350 int i;
6351
6352 dst = (u32 *)((u8 *)dst + off);
6353 for (i = 0; i < len; i += sizeof(u32))
6354 *dst++ = tr32(off + i);
6355}
6356
6357static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6358{
6359 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6360 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6361 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6362 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6363 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6364 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6365 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6366 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6367 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6368 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6369 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6370 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6371 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6372 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6373 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6374 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6375 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6376 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6377 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6378
63c3a66f 6379 if (tg3_flag(tp, SUPPORT_MSIX))
97bd8e49
MC		 6380 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6381
6382 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6383 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6384 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6385 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6386 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6387 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6388 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6389 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6390
63c3a66f 6391 if (!tg3_flag(tp, 5705_PLUS)) {
97bd8e49
MC		 6392 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6393 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6394 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6395 }
6396
6397 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6398 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6399 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6400 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6401 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6402
63c3a66f 6403 if (tg3_flag(tp, NVRAM))
97bd8e49
MC		 6404 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6405}
6406
6407static void tg3_dump_state(struct tg3 *tp)
6408{
6409 int i;
6410 u32 *regs;
6411
6412 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
b2adaca9 6413 if (!regs)
97bd8e49 6414 return;
97bd8e49 6415
63c3a66f 6416 if (tg3_flag(tp, PCI_EXPRESS)) {
97bd8e49
MC		 6417 /* Read up to but not including private PCI registers */
6418 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6419 regs[i / sizeof(u32)] = tr32(i);
6420 } else
6421 tg3_dump_legacy_regs(tp, regs);
6422
6423 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6424 if (!regs[i + 0] && !regs[i + 1] &&
6425 !regs[i + 2] && !regs[i + 3])
6426 continue;
6427
6428 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6429 i * 4,
6430 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6431 }
6432
6433 kfree(regs);
6434
6435 for (i = 0; i < tp->irq_cnt; i++) {
6436 struct tg3_napi *tnapi = &tp->napi[i];
6437
6438 /* SW status block */
6439 netdev_err(tp->dev,
6440 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6441 i,
6442 tnapi->hw_status->status,
6443 tnapi->hw_status->status_tag,
6444 tnapi->hw_status->rx_jumbo_consumer,
6445 tnapi->hw_status->rx_consumer,
6446 tnapi->hw_status->rx_mini_consumer,
6447 tnapi->hw_status->idx[0].rx_producer,
6448 tnapi->hw_status->idx[0].tx_consumer);
6449
6450 netdev_err(tp->dev,
6451 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6452 i,
6453 tnapi->last_tag, tnapi->last_irq_tag,
6454 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6455 tnapi->rx_rcb_ptr,
6456 tnapi->prodring.rx_std_prod_idx,
6457 tnapi->prodring.rx_std_cons_idx,
6458 tnapi->prodring.rx_jmb_prod_idx,
6459 tnapi->prodring.rx_jmb_cons_idx);
6460 }
6461}
6462
df3e6548
MC		 6463/* This is called whenever we suspect that the system chipset is re-
6464 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6465 * is bogus tx completions. We try to recover by setting the
6466 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6467 * in the workqueue.
6468 */
6469static void tg3_tx_recover(struct tg3 *tp)
6470{
63c3a66f 6471 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
df3e6548
MC		 6472 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6473
5129c3a3
MC		 6474 netdev_warn(tp->dev,
6475 "The system may be re-ordering memory-mapped I/O "
6476 "cycles to the network device, attempting to recover. "
6477 "Please report the problem to the driver maintainer "
6478 "and include system chipset information.\n");
df3e6548 6479
63c3a66f 6480 tg3_flag_set(tp, TX_RECOVERY_PENDING);
df3e6548
MC		 6481}
6482
f3f3f27e 6483static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205 6484{
f65aac16
MC		 6485 /* Tell compiler to fetch tx indices from memory. */
6486 barrier();
f3f3f27e
MC		 6487 return tnapi->tx_pending -
6488 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 6489}
6490
1da177e4
LT		 6491/* Tigon3 never reports partial packet sends. So we do not
6492 * need special logic to handle SKBs that have not had all
6493 * of their frags sent yet, like SunGEM does.
6494 */
17375d25 6495static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 6496{
17375d25 6497 struct tg3 *tp = tnapi->tp;
898a56f8 6498 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 6499 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 6500 struct netdev_queue *txq;
6501 int index = tnapi - tp->napi;
298376d3 6502 unsigned int pkts_compl = 0, bytes_compl = 0;
fe5f5787 6503
63c3a66f 6504 if (tg3_flag(tp, ENABLE_TSS))
fe5f5787
MC		 6505 index--;
6506
6507 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 6508
6509 while (sw_idx != hw_idx) {
df8944cf 6510 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 6511 struct sk_buff *skb = ri->skb;
df3e6548
MC		 6512 int i, tx_bug = 0;
6513
6514 if (unlikely(skb == NULL)) {
6515 tg3_tx_recover(tp);
6516 return;
6517 }
1da177e4 6518
fb4ce8ad
MC		 6519 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6520 struct skb_shared_hwtstamps timestamp;
6521 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6522 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6523
6524 tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);
6525
6526 skb_tstamp_tx(skb, &timestamp);
6527 }
6528
f4188d8a 6529 pci_unmap_single(tp->pdev,
4e5e4f0d 6530 dma_unmap_addr(ri, mapping),
f4188d8a
AD		 6531 skb_headlen(skb),
6532 PCI_DMA_TODEVICE);
1da177e4
LT		 6533
6534 ri->skb = NULL;
6535
e01ee14d
MC		 6536 while (ri->fragmented) {
6537 ri->fragmented = false;
6538 sw_idx = NEXT_TX(sw_idx);
6539 ri = &tnapi->tx_buffers[sw_idx];
6540 }
6541
1da177e4
LT		 6542 sw_idx = NEXT_TX(sw_idx);
6543
6544 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 6545 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 6546 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6547 tx_bug = 1;
f4188d8a
AD		 6548
6549 pci_unmap_page(tp->pdev,
4e5e4f0d 6550 dma_unmap_addr(ri, mapping),
9e903e08 6551 skb_frag_size(&skb_shinfo(skb)->frags[i]),
f4188d8a 6552 PCI_DMA_TODEVICE);
e01ee14d
MC		 6553
6554 while (ri->fragmented) {
6555 ri->fragmented = false;
6556 sw_idx = NEXT_TX(sw_idx);
6557 ri = &tnapi->tx_buffers[sw_idx];
6558 }
6559
1da177e4
LT		 6560 sw_idx = NEXT_TX(sw_idx);
6561 }
6562
298376d3
TH		 6563 pkts_compl++;
6564 bytes_compl += skb->len;
6565
f47c11ee 6566 dev_kfree_skb(skb);
df3e6548
MC		 6567
6568 if (unlikely(tx_bug)) {
6569 tg3_tx_recover(tp);
6570 return;
6571 }
1da177e4
LT		 6572 }
6573
5cb917bc 6574 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
298376d3 6575
f3f3f27e 6576 tnapi->tx_cons = sw_idx;
1da177e4 6577
1b2a7205
MC		 6578 /* Need to make the tx_cons update visible to tg3_start_xmit()
6579 * before checking for netif_queue_stopped(). Without the
6580 * memory barrier, there is a small possibility that tg3_start_xmit()
6581 * will miss it and cause the queue to be stopped forever.
6582 */
6583 smp_mb();
6584
fe5f5787 6585 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 6586 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 6587 __netif_tx_lock(txq, smp_processor_id());
6588 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 6589 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 6590 netif_tx_wake_queue(txq);
6591 __netif_tx_unlock(txq);
51b91468 6592 }
1da177e4
LT		 6593}
6594
8d4057a9
ED		 6595static void tg3_frag_free(bool is_frag, void *data)
6596{
6597 if (is_frag)
6598 put_page(virt_to_head_page(data));
6599 else
6600 kfree(data);
6601}
6602
9205fd9c 6603static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
2b2cdb65 6604{
8d4057a9
ED		 6605 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6606 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6607
9205fd9c 6608 if (!ri->data)
2b2cdb65
MC		 6609 return;
6610
4e5e4f0d 6611 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
2b2cdb65 6612 map_sz, PCI_DMA_FROMDEVICE);
a1e8b307 6613 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
9205fd9c 6614 ri->data = NULL;
2b2cdb65
MC		 6615}
6616
8d4057a9 6617
1da177e4
LT		 6618/* Returns size of skb allocated or < 0 on error.
6619 *
6620 * We only need to fill in the address because the other members
6621 * of the RX descriptor are invariant, see tg3_init_rings.
6622 *
6623 * Note the purposeful assymetry of cpu vs. chip accesses. For
6624 * posting buffers we only dirty the first cache line of the RX
6625 * descriptor (containing the address). Whereas for the RX status
6626 * buffers the cpu only reads the last cacheline of the RX descriptor
6627 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6628 */
9205fd9c 6629static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
8d4057a9
ED		 6630 u32 opaque_key, u32 dest_idx_unmasked,
6631 unsigned int *frag_size)
1da177e4
LT		 6632{
6633 struct tg3_rx_buffer_desc *desc;
f94e290e 6634 struct ring_info *map;
9205fd9c 6635 u8 *data;
1da177e4 6636 dma_addr_t mapping;
9205fd9c 6637 int skb_size, data_size, dest_idx;
1da177e4 6638
1da177e4
LT		 6639 switch (opaque_key) {
6640 case RXD_OPAQUE_RING_STD:
2c49a44d 6641 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
21f581a5
MC		 6642 desc = &tpr->rx_std[dest_idx];
6643 map = &tpr->rx_std_buffers[dest_idx];
9205fd9c 6644 data_size = tp->rx_pkt_map_sz;
1da177e4
LT		 6645 break;
6646
6647 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6648 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
79ed5ac7 6649 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 6650 map = &tpr->rx_jmb_buffers[dest_idx];
9205fd9c 6651 data_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 6652 break;
6653
6654 default:
6655 return -EINVAL;
855e1111 6656 }
1da177e4
LT		 6657
6658 /* Do not overwrite any of the map or rp information
6659 * until we are sure we can commit to a new buffer.
6660 *
6661 * Callers depend upon this behavior and assume that
6662 * we leave everything unchanged if we fail.
6663 */
9205fd9c
ED		 6664 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6665 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
a1e8b307
ED		 6666 if (skb_size <= PAGE_SIZE) {
6667 data = netdev_alloc_frag(skb_size);
6668 *frag_size = skb_size;
8d4057a9
ED		 6669 } else {
6670 data = kmalloc(skb_size, GFP_ATOMIC);
6671 *frag_size = 0;
6672 }
9205fd9c 6673 if (!data)
1da177e4
LT		 6674 return -ENOMEM;
6675
9205fd9c
ED		 6676 mapping = pci_map_single(tp->pdev,
6677 data + TG3_RX_OFFSET(tp),
6678 data_size,
1da177e4 6679 PCI_DMA_FROMDEVICE);
8d4057a9 6680 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
a1e8b307 6681 tg3_frag_free(skb_size <= PAGE_SIZE, data);
a21771dd
MC		 6682 return -EIO;
6683 }
1da177e4 6684
9205fd9c 6685 map->data = data;
4e5e4f0d 6686 dma_unmap_addr_set(map, mapping, mapping);
1da177e4 6687
1da177e4
LT		 6688 desc->addr_hi = ((u64)mapping >> 32);
6689 desc->addr_lo = ((u64)mapping & 0xffffffff);
6690
9205fd9c 6691 return data_size;
1da177e4
LT		 6692}
6693
6694/* We only need to move over in the address because the other
6695 * members of the RX descriptor are invariant. See notes above
9205fd9c 6696 * tg3_alloc_rx_data for full details.
1da177e4 6697 */
a3896167
MC		 6698static void tg3_recycle_rx(struct tg3_napi *tnapi,
6699 struct tg3_rx_prodring_set *dpr,
6700 u32 opaque_key, int src_idx,
6701 u32 dest_idx_unmasked)
1da177e4 6702{
17375d25 6703 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 6704 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6705 struct ring_info *src_map, *dest_map;
8fea32b9 6706 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
c6cdf436 6707 int dest_idx;
1da177e4
LT		 6708
6709 switch (opaque_key) {
6710 case RXD_OPAQUE_RING_STD:
2c49a44d 6711 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
a3896167
MC		 6712 dest_desc = &dpr->rx_std[dest_idx];
6713 dest_map = &dpr->rx_std_buffers[dest_idx];
6714 src_desc = &spr->rx_std[src_idx];
6715 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 6716 break;
6717
6718 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6719 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
a3896167
MC		 6720 dest_desc = &dpr->rx_jmb[dest_idx].std;
6721 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6722 src_desc = &spr->rx_jmb[src_idx].std;
6723 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 6724 break;
6725
6726 default:
6727 return;
855e1111 6728 }
1da177e4 6729
9205fd9c 6730 dest_map->data = src_map->data;
4e5e4f0d
FT		 6731 dma_unmap_addr_set(dest_map, mapping,
6732 dma_unmap_addr(src_map, mapping));
1da177e4
LT		 6733 dest_desc->addr_hi = src_desc->addr_hi;
6734 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 6735
6736 /* Ensure that the update to the skb happens after the physical
6737 * addresses have been transferred to the new BD location.
6738 */
6739 smp_wmb();
6740
9205fd9c 6741 src_map->data = NULL;
1da177e4
LT		 6742}
6743
1da177e4
LT		 6744/* The RX ring scheme is composed of multiple rings which post fresh
6745 * buffers to the chip, and one special ring the chip uses to report
6746 * status back to the host.
6747 *
6748 * The special ring reports the status of received packets to the
6749 * host. The chip does not write into the original descriptor the
6750 * RX buffer was obtained from. The chip simply takes the original
6751 * descriptor as provided by the host, updates the status and length
6752 * field, then writes this into the next status ring entry.
6753 *
6754 * Each ring the host uses to post buffers to the chip is described
6755 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6756 * it is first placed into the on-chip ram. When the packet's length
6757 * is known, it walks down the TG3_BDINFO entries to select the ring.
6758 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6759 * which is within the range of the new packet's length is chosen.
6760 *
6761 * The "separate ring for rx status" scheme may sound queer, but it makes
6762 * sense from a cache coherency perspective. If only the host writes
6763 * to the buffer post rings, and only the chip writes to the rx status
6764 * rings, then cache lines never move beyond shared-modified state.
6765 * If both the host and chip were to write into the same ring, cache line
6766 * eviction could occur since both entities want it in an exclusive state.
6767 */
17375d25 6768static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 6769{
17375d25 6770 struct tg3 *tp = tnapi->tp;
f92905de 6771 u32 work_mask, rx_std_posted = 0;
4361935a 6772 u32 std_prod_idx, jmb_prod_idx;
72334482 6773 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 6774 u16 hw_idx;
1da177e4 6775 int received;
8fea32b9 6776 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
1da177e4 6777
8d9d7cfc 6778 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 6779 /*
6780 * We need to order the read of hw_idx and the read of
6781 * the opaque cookie.
6782 */
6783 rmb();
1da177e4
LT		 6784 work_mask = 0;
6785 received = 0;
4361935a
MC		 6786 std_prod_idx = tpr->rx_std_prod_idx;
6787 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 6788 while (sw_idx != hw_idx && budget > 0) {
afc081f8 6789 struct ring_info *ri;
72334482 6790 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 6791 unsigned int len;
6792 struct sk_buff *skb;
6793 dma_addr_t dma_addr;
6794 u32 opaque_key, desc_idx, *post_ptr;
9205fd9c 6795 u8 *data;
fb4ce8ad 6796 u64 tstamp = 0;
1da177e4
LT		 6797
6798 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6799 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6800 if (opaque_key == RXD_OPAQUE_RING_STD) {
8fea32b9 6801 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4e5e4f0d 6802 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6803 data = ri->data;
4361935a 6804 post_ptr = &std_prod_idx;
f92905de 6805 rx_std_posted++;
1da177e4 6806 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
8fea32b9 6807 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4e5e4f0d 6808 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6809 data = ri->data;
4361935a 6810 post_ptr = &jmb_prod_idx;
21f581a5 6811 } else
1da177e4 6812 goto next_pkt_nopost;
1da177e4
LT		 6813
6814 work_mask |= opaque_key;
6815
6816 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
6817 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
6818 drop_it:
a3896167 6819 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6820 desc_idx, *post_ptr);
6821 drop_it_no_recycle:
6822 /* Other statistics kept track of by card. */
b0057c51 6823 tp->rx_dropped++;
1da177e4
LT		 6824 goto next_pkt;
6825 }
6826
9205fd9c 6827 prefetch(data + TG3_RX_OFFSET(tp));
ad829268
MC		 6828 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6829 ETH_FCS_LEN;
1da177e4 6830
fb4ce8ad
MC		 6831 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6832 RXD_FLAG_PTPSTAT_PTPV1 ||
6833 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6834 RXD_FLAG_PTPSTAT_PTPV2) {
6835 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6836 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6837 }
6838
d2757fc4 6839 if (len > TG3_RX_COPY_THRESH(tp)) {
1da177e4 6840 int skb_size;
8d4057a9 6841 unsigned int frag_size;
1da177e4 6842
9205fd9c 6843 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
8d4057a9 6844 *post_ptr, &frag_size);
1da177e4
LT		 6845 if (skb_size < 0)
6846 goto drop_it;
6847
287be12e 6848 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 6849 PCI_DMA_FROMDEVICE);
6850
8d4057a9 6851 skb = build_skb(data, frag_size);
9205fd9c 6852 if (!skb) {
8d4057a9 6853 tg3_frag_free(frag_size != 0, data);
9205fd9c
ED		 6854 goto drop_it_no_recycle;
6855 }
6856 skb_reserve(skb, TG3_RX_OFFSET(tp));
6857 /* Ensure that the update to the data happens
61e800cf
MC		 6858 * after the usage of the old DMA mapping.
6859 */
6860 smp_wmb();
6861
9205fd9c 6862 ri->data = NULL;
61e800cf 6863
1da177e4 6864 } else {
a3896167 6865 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6866 desc_idx, *post_ptr);
6867
9205fd9c
ED		 6868 skb = netdev_alloc_skb(tp->dev,
6869 len + TG3_RAW_IP_ALIGN);
6870 if (skb == NULL)
1da177e4
LT		 6871 goto drop_it_no_recycle;
6872
9205fd9c 6873 skb_reserve(skb, TG3_RAW_IP_ALIGN);
1da177e4 6874 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
9205fd9c
ED		 6875 memcpy(skb->data,
6876 data + TG3_RX_OFFSET(tp),
6877 len);
1da177e4 6878 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
1da177e4
LT		 6879 }
6880
9205fd9c 6881 skb_put(skb, len);
fb4ce8ad
MC		 6882 if (tstamp)
6883 tg3_hwclock_to_timestamp(tp, tstamp,
6884 skb_hwtstamps(skb));
6885
dc668910 6886 if ((tp->dev->features & NETIF_F_RXCSUM) &&
1da177e4
LT		 6887 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6888 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6889 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6890 skb->ip_summed = CHECKSUM_UNNECESSARY;
6891 else
bc8acf2c 6892 skb_checksum_none_assert(skb);
1da177e4
LT		 6893
6894 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 6895
6896 if (len > (tp->dev->mtu + ETH_HLEN) &&
6897 skb->protocol != htons(ETH_P_8021Q)) {
6898 dev_kfree_skb(skb);
b0057c51 6899 goto drop_it_no_recycle;
f7b493e0
MC		 6900 }
6901
9dc7a113 6902 if (desc->type_flags & RXD_FLAG_VLAN &&
bf933c80 6903 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
86a9bad3 6904 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
bf933c80 6905 desc->err_vlan & RXD_VLAN_MASK);
9dc7a113 6906
bf933c80 6907 napi_gro_receive(&tnapi->napi, skb);
1da177e4 6908
1da177e4
LT		 6909 received++;
6910 budget--;
6911
6912next_pkt:
6913 (*post_ptr)++;
f92905de
MC		 6914
6915 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
2c49a44d
MC		 6916 tpr->rx_std_prod_idx = std_prod_idx &
6917 tp->rx_std_ring_mask;
86cfe4ff
MC		 6918 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6919 tpr->rx_std_prod_idx);
f92905de
MC		 6920 work_mask &= ~RXD_OPAQUE_RING_STD;
6921 rx_std_posted = 0;
6922 }
1da177e4 6923next_pkt_nopost:
483ba50b 6924 sw_idx++;
7cb32cf2 6925 sw_idx &= tp->rx_ret_ring_mask;
52f6d697
MC		 6926
6927 /* Refresh hw_idx to see if there is new work */
6928 if (sw_idx == hw_idx) {
8d9d7cfc 6929 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 6930 rmb();
6931 }
1da177e4
LT		 6932 }
6933
6934 /* ACK the status ring. */
72334482
MC		 6935 tnapi->rx_rcb_ptr = sw_idx;
6936 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 6937
6938 /* Refill RX ring(s). */
63c3a66f 6939 if (!tg3_flag(tp, ENABLE_RSS)) {
6541b806
MC		 6940 /* Sync BD data before updating mailbox */
6941 wmb();
6942
b196c7e4 6943 if (work_mask & RXD_OPAQUE_RING_STD) {
2c49a44d
MC		 6944 tpr->rx_std_prod_idx = std_prod_idx &
6945 tp->rx_std_ring_mask;
b196c7e4
MC		 6946 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6947 tpr->rx_std_prod_idx);
6948 }
6949 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2c49a44d
MC		 6950 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6951 tp->rx_jmb_ring_mask;
b196c7e4
MC		 6952 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6953 tpr->rx_jmb_prod_idx);
6954 }
6955 mmiowb();
6956 } else if (work_mask) {
6957 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6958 * updated before the producer indices can be updated.
6959 */
6960 smp_wmb();
6961
2c49a44d
MC		 6962 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6963 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
b196c7e4 6964
7ae52890
MC		 6965 if (tnapi != &tp->napi[1]) {
6966 tp->rx_refill = true;
e4af1af9 6967 napi_schedule(&tp->napi[1].napi);
7ae52890 6968 }
1da177e4 6969 }
1da177e4
LT		 6970
6971 return received;
6972}
6973
35f2d7d0 6974static void tg3_poll_link(struct tg3 *tp)
1da177e4 6975{
1da177e4 6976 /* handle link change and other phy events */
63c3a66f 6977 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
35f2d7d0
MC		 6978 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
6979
1da177e4
LT		 6980 if (sblk->status & SD_STATUS_LINK_CHG) {
6981 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 6982 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 6983 spin_lock(&tp->lock);
63c3a66f 6984 if (tg3_flag(tp, USE_PHYLIB)) {
dd477003
MC		 6985 tw32_f(MAC_STATUS,
6986 (MAC_STATUS_SYNC_CHANGED |
6987 MAC_STATUS_CFG_CHANGED |
6988 MAC_STATUS_MI_COMPLETION |
6989 MAC_STATUS_LNKSTATE_CHANGED));
6990 udelay(40);
6991 } else
953c96e0 6992 tg3_setup_phy(tp, false);
f47c11ee 6993 spin_unlock(&tp->lock);
1da177e4
LT		 6994 }
6995 }
35f2d7d0
MC		 6996}
6997
f89f38b8
MC		 6998static int tg3_rx_prodring_xfer(struct tg3 *tp,
6999 struct tg3_rx_prodring_set *dpr,
7000 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 7001{
7002 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 7003 int i, err = 0;
b196c7e4
MC		 7004
7005 while (1) {
7006 src_prod_idx = spr->rx_std_prod_idx;
7007
7008 /* Make sure updates to the rx_std_buffers[] entries and the
7009 * standard producer index are seen in the correct order.
7010 */
7011 smp_rmb();
7012
7013 if (spr->rx_std_cons_idx == src_prod_idx)
7014 break;
7015
7016 if (spr->rx_std_cons_idx < src_prod_idx)
7017 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7018 else
2c49a44d
MC		 7019 cpycnt = tp->rx_std_ring_mask + 1 -
7020 spr->rx_std_cons_idx;
b196c7e4 7021
2c49a44d
MC		 7022 cpycnt = min(cpycnt,
7023 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
b196c7e4
MC		 7024
7025 si = spr->rx_std_cons_idx;
7026 di = dpr->rx_std_prod_idx;
7027
e92967bf 7028 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7029 if (dpr->rx_std_buffers[i].data) {
e92967bf 7030 cpycnt = i - di;
f89f38b8 7031 err = -ENOSPC;
e92967bf
MC		 7032 break;
7033 }
7034 }
7035
7036 if (!cpycnt)
7037 break;
7038
7039 /* Ensure that updates to the rx_std_buffers ring and the
7040 * shadowed hardware producer ring from tg3_recycle_skb() are
7041 * ordered correctly WRT the skb check above.
7042 */
7043 smp_rmb();
7044
b196c7e4
MC		 7045 memcpy(&dpr->rx_std_buffers[di],
7046 &spr->rx_std_buffers[si],
7047 cpycnt * sizeof(struct ring_info));
7048
7049 for (i = 0; i < cpycnt; i++, di++, si++) {
7050 struct tg3_rx_buffer_desc *sbd, *dbd;
7051 sbd = &spr->rx_std[si];
7052 dbd = &dpr->rx_std[di];
7053 dbd->addr_hi = sbd->addr_hi;
7054 dbd->addr_lo = sbd->addr_lo;
7055 }
7056
2c49a44d
MC		 7057 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7058 tp->rx_std_ring_mask;
7059 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7060 tp->rx_std_ring_mask;
b196c7e4
MC		 7061 }
7062
7063 while (1) {
7064 src_prod_idx = spr->rx_jmb_prod_idx;
7065
7066 /* Make sure updates to the rx_jmb_buffers[] entries and
7067 * the jumbo producer index are seen in the correct order.
7068 */
7069 smp_rmb();
7070
7071 if (spr->rx_jmb_cons_idx == src_prod_idx)
7072 break;
7073
7074 if (spr->rx_jmb_cons_idx < src_prod_idx)
7075 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7076 else
2c49a44d
MC		 7077 cpycnt = tp->rx_jmb_ring_mask + 1 -
7078 spr->rx_jmb_cons_idx;
b196c7e4
MC		 7079
7080 cpycnt = min(cpycnt,
2c49a44d 7081 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7082
7083 si = spr->rx_jmb_cons_idx;
7084 di = dpr->rx_jmb_prod_idx;
7085
e92967bf 7086 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7087 if (dpr->rx_jmb_buffers[i].data) {
e92967bf 7088 cpycnt = i - di;
f89f38b8 7089 err = -ENOSPC;
e92967bf
MC		 7090 break;
7091 }
7092 }
7093
7094 if (!cpycnt)
7095 break;
7096
7097 /* Ensure that updates to the rx_jmb_buffers ring and the
7098 * shadowed hardware producer ring from tg3_recycle_skb() are
7099 * ordered correctly WRT the skb check above.
7100 */
7101 smp_rmb();
7102
b196c7e4
MC		 7103 memcpy(&dpr->rx_jmb_buffers[di],
7104 &spr->rx_jmb_buffers[si],
7105 cpycnt * sizeof(struct ring_info));
7106
7107 for (i = 0; i < cpycnt; i++, di++, si++) {
7108 struct tg3_rx_buffer_desc *sbd, *dbd;
7109 sbd = &spr->rx_jmb[si].std;
7110 dbd = &dpr->rx_jmb[di].std;
7111 dbd->addr_hi = sbd->addr_hi;
7112 dbd->addr_lo = sbd->addr_lo;
7113 }
7114
2c49a44d
MC		 7115 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7116 tp->rx_jmb_ring_mask;
7117 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7118 tp->rx_jmb_ring_mask;
b196c7e4 7119 }
f89f38b8
MC		 7120
7121 return err;
b196c7e4
MC		 7122}
7123
35f2d7d0
MC		 7124static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7125{
7126 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 7127
7128 /* run TX completion thread */
f3f3f27e 7129 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 7130 tg3_tx(tnapi);
63c3a66f 7131 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
4fd7ab59 7132 return work_done;
1da177e4
LT		 7133 }
7134
f891ea16
MC		 7135 if (!tnapi->rx_rcb_prod_idx)
7136 return work_done;
7137
1da177e4
LT		 7138 /* run RX thread, within the bounds set by NAPI.
7139 * All RX "locking" is done by ensuring outside
bea3348e 7140 * code synchronizes with tg3->napi.poll()
1da177e4 7141 */
8d9d7cfc 7142 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 7143 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 7144
63c3a66f 7145 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
8fea32b9 7146 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
f89f38b8 7147 int i, err = 0;
e4af1af9
MC		 7148 u32 std_prod_idx = dpr->rx_std_prod_idx;
7149 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 7150
7ae52890 7151 tp->rx_refill = false;
9102426a 7152 for (i = 1; i <= tp->rxq_cnt; i++)
f89f38b8 7153 err |= tg3_rx_prodring_xfer(tp, dpr,
8fea32b9 7154 &tp->napi[i].prodring);
b196c7e4
MC		 7155
7156 wmb();
7157
e4af1af9
MC		 7158 if (std_prod_idx != dpr->rx_std_prod_idx)
7159 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7160 dpr->rx_std_prod_idx);
b196c7e4 7161
e4af1af9
MC		 7162 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7163 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7164 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7165
7166 mmiowb();
f89f38b8
MC		 7167
7168 if (err)
7169 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 7170 }
7171
6f535763
DM		 7172 return work_done;
7173}
7174
db219973
MC		 7175static inline void tg3_reset_task_schedule(struct tg3 *tp)
7176{
7177 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7178 schedule_work(&tp->reset_task);
7179}
7180
7181static inline void tg3_reset_task_cancel(struct tg3 *tp)
7182{
7183 cancel_work_sync(&tp->reset_task);
7184 tg3_flag_clear(tp, RESET_TASK_PENDING);
c7101359 7185 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
db219973
MC		 7186}
7187
35f2d7d0
MC		 7188static int tg3_poll_msix(struct napi_struct *napi, int budget)
7189{
7190 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7191 struct tg3 *tp = tnapi->tp;
7192 int work_done = 0;
7193 struct tg3_hw_status *sblk = tnapi->hw_status;
7194
7195 while (1) {
7196 work_done = tg3_poll_work(tnapi, work_done, budget);
7197
63c3a66f 7198 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
35f2d7d0
MC		 7199 goto tx_recovery;
7200
7201 if (unlikely(work_done >= budget))
7202 break;
7203
c6cdf436 7204 /* tp->last_tag is used in tg3_int_reenable() below
35f2d7d0
MC		 7205 * to tell the hw how much work has been processed,
7206 * so we must read it before checking for more work.
7207 */
7208 tnapi->last_tag = sblk->status_tag;
7209 tnapi->last_irq_tag = tnapi->last_tag;
7210 rmb();
7211
7212 /* check for RX/TX work to do */
6d40db7b
MC		 7213 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7214 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7ae52890
MC		 7215
7216 /* This test here is not race free, but will reduce
7217 * the number of interrupts by looping again.
7218 */
7219 if (tnapi == &tp->napi[1] && tp->rx_refill)
7220 continue;
7221
35f2d7d0
MC		 7222 napi_complete(napi);
7223 /* Reenable interrupts. */
7224 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7ae52890
MC		 7225
7226 /* This test here is synchronized by napi_schedule()
7227 * and napi_complete() to close the race condition.
7228 */
7229 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7230 tw32(HOSTCC_MODE, tp->coalesce_mode |
7231 HOSTCC_MODE_ENABLE |
7232 tnapi->coal_now);
7233 }
35f2d7d0
MC		 7234 mmiowb();
7235 break;
7236 }
7237 }
7238
7239 return work_done;
7240
7241tx_recovery:
7242 /* work_done is guaranteed to be less than budget. */
7243 napi_complete(napi);
db219973 7244 tg3_reset_task_schedule(tp);
35f2d7d0
MC		 7245 return work_done;
7246}
7247
e64de4e6
MC		 7248static void tg3_process_error(struct tg3 *tp)
7249{
7250 u32 val;
7251 bool real_error = false;
7252
63c3a66f 7253 if (tg3_flag(tp, ERROR_PROCESSED))
e64de4e6
MC		 7254 return;
7255
7256 /* Check Flow Attention register */
7257 val = tr32(HOSTCC_FLOW_ATTN);
7258 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7259 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7260 real_error = true;
7261 }
7262
7263 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7264 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7265 real_error = true;
7266 }
7267
7268 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7269 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7270 real_error = true;
7271 }
7272
7273 if (!real_error)
7274 return;
7275
7276 tg3_dump_state(tp);
7277
63c3a66f 7278 tg3_flag_set(tp, ERROR_PROCESSED);
db219973 7279 tg3_reset_task_schedule(tp);
e64de4e6
MC		 7280}
7281
6f535763
DM		 7282static int tg3_poll(struct napi_struct *napi, int budget)
7283{
8ef0442f
MC		 7284 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7285 struct tg3 *tp = tnapi->tp;
6f535763 7286 int work_done = 0;
898a56f8 7287 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 7288
7289 while (1) {
e64de4e6
MC		 7290 if (sblk->status & SD_STATUS_ERROR)
7291 tg3_process_error(tp);
7292
35f2d7d0
MC		 7293 tg3_poll_link(tp);
7294
17375d25 7295 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763 7296
63c3a66f 7297 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6f535763
DM		 7298 goto tx_recovery;
7299
7300 if (unlikely(work_done >= budget))
7301 break;
7302
63c3a66f 7303 if (tg3_flag(tp, TAGGED_STATUS)) {
17375d25 7304 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 7305 * to tell the hw how much work has been processed,
7306 * so we must read it before checking for more work.
7307 */
898a56f8
MC		 7308 tnapi->last_tag = sblk->status_tag;
7309 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 7310 rmb();
7311 } else
7312 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 7313
17375d25 7314 if (likely(!tg3_has_work(tnapi))) {
288379f0 7315 napi_complete(napi);
17375d25 7316 tg3_int_reenable(tnapi);
6f535763
DM		 7317 break;
7318 }
1da177e4
LT		 7319 }
7320
bea3348e 7321 return work_done;
6f535763
DM		 7322
7323tx_recovery:
4fd7ab59 7324 /* work_done is guaranteed to be less than budget. */
288379f0 7325 napi_complete(napi);
db219973 7326 tg3_reset_task_schedule(tp);
4fd7ab59 7327 return work_done;
1da177e4
LT		 7328}
7329
66cfd1bd
MC		 7330static void tg3_napi_disable(struct tg3 *tp)
7331{
7332 int i;
7333
7334 for (i = tp->irq_cnt - 1; i >= 0; i--)
7335 napi_disable(&tp->napi[i].napi);
7336}
7337
7338static void tg3_napi_enable(struct tg3 *tp)
7339{
7340 int i;
7341
7342 for (i = 0; i < tp->irq_cnt; i++)
7343 napi_enable(&tp->napi[i].napi);
7344}
7345
7346static void tg3_napi_init(struct tg3 *tp)
7347{
7348 int i;
7349
7350 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7351 for (i = 1; i < tp->irq_cnt; i++)
7352 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7353}
7354
7355static void tg3_napi_fini(struct tg3 *tp)
7356{
7357 int i;
7358
7359 for (i = 0; i < tp->irq_cnt; i++)
7360 netif_napi_del(&tp->napi[i].napi);
7361}
7362
7363static inline void tg3_netif_stop(struct tg3 *tp)
7364{
7365 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7366 tg3_napi_disable(tp);
f4a46d1f 7367 netif_carrier_off(tp->dev);
66cfd1bd
MC		 7368 netif_tx_disable(tp->dev);
7369}
7370
35763066 7371/* tp->lock must be held */
66cfd1bd
MC		 7372static inline void tg3_netif_start(struct tg3 *tp)
7373{
be947307
MC		 7374 tg3_ptp_resume(tp);
7375
66cfd1bd
MC		 7376 /* NOTE: unconditional netif_tx_wake_all_queues is only
7377 * appropriate so long as all callers are assured to
7378 * have free tx slots (such as after tg3_init_hw)
7379 */
7380 netif_tx_wake_all_queues(tp->dev);
7381
f4a46d1f
NNS		 7382 if (tp->link_up)
7383 netif_carrier_on(tp->dev);
7384
66cfd1bd
MC		 7385 tg3_napi_enable(tp);
7386 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7387 tg3_enable_ints(tp);
7388}
7389
f47c11ee
DM		 7390static void tg3_irq_quiesce(struct tg3 *tp)
7391{
4f125f42
MC		 7392 int i;
7393
f47c11ee
DM		 7394 BUG_ON(tp->irq_sync);
7395
7396 tp->irq_sync = 1;
7397 smp_mb();
7398
4f125f42
MC		 7399 for (i = 0; i < tp->irq_cnt; i++)
7400 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 7401}
7402
f47c11ee
DM		 7403/* Fully shutdown all tg3 driver activity elsewhere in the system.
7404 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7405 * with as well. Most of the time, this is not necessary except when
7406 * shutting down the device.
7407 */
7408static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7409{
46966545 7410 spin_lock_bh(&tp->lock);
f47c11ee
DM		 7411 if (irq_sync)
7412 tg3_irq_quiesce(tp);
f47c11ee
DM		 7413}
7414
7415static inline void tg3_full_unlock(struct tg3 *tp)
7416{
f47c11ee
DM		 7417 spin_unlock_bh(&tp->lock);
7418}
7419
fcfa0a32
MC		 7420/* One-shot MSI handler - Chip automatically disables interrupt
7421 * after sending MSI so driver doesn't have to do it.
7422 */
7d12e780 7423static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 7424{
09943a18
MC		 7425 struct tg3_napi *tnapi = dev_id;
7426 struct tg3 *tp = tnapi->tp;
fcfa0a32 7427
898a56f8 7428 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7429 if (tnapi->rx_rcb)
7430 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 7431
7432 if (likely(!tg3_irq_sync(tp)))
09943a18 7433 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 7434
7435 return IRQ_HANDLED;
7436}
7437
88b06bc2
MC		 7438/* MSI ISR - No need to check for interrupt sharing and no need to
7439 * flush status block and interrupt mailbox. PCI ordering rules
7440 * guarantee that MSI will arrive after the status block.
7441 */
7d12e780 7442static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 7443{
09943a18
MC		 7444 struct tg3_napi *tnapi = dev_id;
7445 struct tg3 *tp = tnapi->tp;
88b06bc2 7446
898a56f8 7447 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7448 if (tnapi->rx_rcb)
7449 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 7450 /*
fac9b83e 7451 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 7452 * chip-internal interrupt pending events.
fac9b83e 7453 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 7454 * NIC to stop sending us irqs, engaging "in-intr-handler"
7455 * event coalescing.
7456 */
5b39de91 7457 tw32_mailbox(tnapi->int_mbox, 0x00000001);
61487480 7458 if (likely(!tg3_irq_sync(tp)))
09943a18 7459 napi_schedule(&tnapi->napi);
61487480 7460
88b06bc2
MC		 7461 return IRQ_RETVAL(1);
7462}
7463
7d12e780 7464static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 7465{
09943a18
MC		 7466 struct tg3_napi *tnapi = dev_id;
7467 struct tg3 *tp = tnapi->tp;
898a56f8 7468 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 7469 unsigned int handled = 1;
7470
1da177e4
LT		 7471 /* In INTx mode, it is possible for the interrupt to arrive at
7472 * the CPU before the status block posted prior to the interrupt.
7473 * Reading the PCI State register will confirm whether the
7474 * interrupt is ours and will flush the status block.
7475 */
d18edcb2 7476 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
63c3a66f 7477 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7478 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7479 handled = 0;
f47c11ee 7480 goto out;
fac9b83e 7481 }
d18edcb2
MC		 7482 }
7483
7484 /*
7485 * Writing any value to intr-mbox-0 clears PCI INTA# and
7486 * chip-internal interrupt pending events.
7487 * Writing non-zero to intr-mbox-0 additional tells the
7488 * NIC to stop sending us irqs, engaging "in-intr-handler"
7489 * event coalescing.
c04cb347
MC		 7490 *
7491 * Flush the mailbox to de-assert the IRQ immediately to prevent
7492 * spurious interrupts. The flush impacts performance but
7493 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7494 */
c04cb347 7495 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 7496 if (tg3_irq_sync(tp))
7497 goto out;
7498 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 7499 if (likely(tg3_has_work(tnapi))) {
72334482 7500 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 7501 napi_schedule(&tnapi->napi);
d18edcb2
MC		 7502 } else {
7503 /* No work, shared interrupt perhaps? re-enable
7504 * interrupts, and flush that PCI write
7505 */
7506 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7507 0x00000000);
fac9b83e 7508 }
f47c11ee 7509out:
fac9b83e
DM		 7510 return IRQ_RETVAL(handled);
7511}
7512
7d12e780 7513static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 7514{
09943a18
MC		 7515 struct tg3_napi *tnapi = dev_id;
7516 struct tg3 *tp = tnapi->tp;
898a56f8 7517 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 7518 unsigned int handled = 1;
7519
fac9b83e
DM		 7520 /* In INTx mode, it is possible for the interrupt to arrive at
7521 * the CPU before the status block posted prior to the interrupt.
7522 * Reading the PCI State register will confirm whether the
7523 * interrupt is ours and will flush the status block.
7524 */
898a56f8 7525 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
63c3a66f 7526 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7527 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7528 handled = 0;
f47c11ee 7529 goto out;
1da177e4 7530 }
d18edcb2
MC		 7531 }
7532
7533 /*
7534 * writing any value to intr-mbox-0 clears PCI INTA# and
7535 * chip-internal interrupt pending events.
7536 * writing non-zero to intr-mbox-0 additional tells the
7537 * NIC to stop sending us irqs, engaging "in-intr-handler"
7538 * event coalescing.
c04cb347
MC		 7539 *
7540 * Flush the mailbox to de-assert the IRQ immediately to prevent
7541 * spurious interrupts. The flush impacts performance but
7542 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7543 */
c04cb347 7544 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 7545
7546 /*
7547 * In a shared interrupt configuration, sometimes other devices'
7548 * interrupts will scream. We record the current status tag here
7549 * so that the above check can report that the screaming interrupts
7550 * are unhandled. Eventually they will be silenced.
7551 */
898a56f8 7552 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 7553
d18edcb2
MC		 7554 if (tg3_irq_sync(tp))
7555 goto out;
624f8e50 7556
72334482 7557 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 7558
09943a18 7559 napi_schedule(&tnapi->napi);
624f8e50 7560
f47c11ee 7561out:
1da177e4
LT		 7562 return IRQ_RETVAL(handled);
7563}
7564
7938109f 7565/* ISR for interrupt test */
7d12e780 7566static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 7567{
09943a18
MC		 7568 struct tg3_napi *tnapi = dev_id;
7569 struct tg3 *tp = tnapi->tp;
898a56f8 7570 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 7571
f9804ddb
MC		 7572 if ((sblk->status & SD_STATUS_UPDATED) ||
7573 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 7574 tg3_disable_ints(tp);
7938109f
MC		 7575 return IRQ_RETVAL(1);
7576 }
7577 return IRQ_RETVAL(0);
7578}
7579
1da177e4
LT		 7580#ifdef CONFIG_NET_POLL_CONTROLLER
7581static void tg3_poll_controller(struct net_device *dev)
7582{
4f125f42 7583 int i;
88b06bc2
MC		 7584 struct tg3 *tp = netdev_priv(dev);
7585
9c13cb8b
NNS		 7586 if (tg3_irq_sync(tp))
7587 return;
7588
4f125f42 7589 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 7590 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 7591}
7592#endif
7593
1da177e4
LT		 7594static void tg3_tx_timeout(struct net_device *dev)
7595{
7596 struct tg3 *tp = netdev_priv(dev);
7597
b0408751 7598 if (netif_msg_tx_err(tp)) {
05dbe005 7599 netdev_err(dev, "transmit timed out, resetting\n");
97bd8e49 7600 tg3_dump_state(tp);
b0408751 7601 }
1da177e4 7602
db219973 7603 tg3_reset_task_schedule(tp);
1da177e4
LT		 7604}
7605
c58ec932
MC		 7606/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7607static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7608{
7609 u32 base = (u32) mapping & 0xffffffff;
7610
807540ba 7611 return (base > 0xffffdcc0) && (base + len + 8 < base);
c58ec932
MC		 7612}
7613
0f0d1510
MC		 7614/* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7615 * of any 4GB boundaries: 4G, 8G, etc
7616 */
7617static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7618 u32 len, u32 mss)
7619{
7620 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7621 u32 base = (u32) mapping & 0xffffffff;
7622
7623 return ((base + len + (mss & 0x3fff)) < base);
7624 }
7625 return 0;
7626}
7627
72f2afb8
MC		 7628/* Test for DMA addresses > 40-bit */
7629static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7630 int len)
7631{
7632#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
63c3a66f 7633 if (tg3_flag(tp, 40BIT_DMA_BUG))
807540ba 7634 return ((u64) mapping + len) > DMA_BIT_MASK(40);
72f2afb8
MC		 7635 return 0;
7636#else
7637 return 0;
7638#endif
7639}
7640
d1a3b737 7641static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
92cd3a17
MC		 7642 dma_addr_t mapping, u32 len, u32 flags,
7643 u32 mss, u32 vlan)
2ffcc981 7644{
92cd3a17
MC		 7645 txbd->addr_hi = ((u64) mapping >> 32);
7646 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7647 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7648 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
2ffcc981 7649}
1da177e4 7650
84b67b27 7651static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
d1a3b737
MC		 7652 dma_addr_t map, u32 len, u32 flags,
7653 u32 mss, u32 vlan)
7654{
7655 struct tg3 *tp = tnapi->tp;
7656 bool hwbug = false;
7657
7658 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
3db1cd5c 7659 hwbug = true;
d1a3b737
MC		 7660
7661 if (tg3_4g_overflow_test(map, len))
3db1cd5c 7662 hwbug = true;
d1a3b737 7663
0f0d1510
MC		 7664 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7665 hwbug = true;
7666
d1a3b737 7667 if (tg3_40bit_overflow_test(tp, map, len))
3db1cd5c 7668 hwbug = true;
d1a3b737 7669
a4cb428d 7670 if (tp->dma_limit) {
b9e45482 7671 u32 prvidx = *entry;
e31aa987 7672 u32 tmp_flag = flags & ~TXD_FLAG_END;
a4cb428d
MC		 7673 while (len > tp->dma_limit && *budget) {
7674 u32 frag_len = tp->dma_limit;
7675 len -= tp->dma_limit;
e31aa987 7676
b9e45482
MC		 7677 /* Avoid the 8byte DMA problem */
7678 if (len <= 8) {
a4cb428d
MC		 7679 len += tp->dma_limit / 2;
7680 frag_len = tp->dma_limit / 2;
e31aa987
MC		 7681 }
7682
b9e45482
MC		 7683 tnapi->tx_buffers[*entry].fragmented = true;
7684
7685 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7686 frag_len, tmp_flag, mss, vlan);
7687 *budget -= 1;
7688 prvidx = *entry;
7689 *entry = NEXT_TX(*entry);
7690
e31aa987
MC		 7691 map += frag_len;
7692 }
7693
7694 if (len) {
7695 if (*budget) {
7696 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7697 len, flags, mss, vlan);
b9e45482 7698 *budget -= 1;
e31aa987
MC		 7699 *entry = NEXT_TX(*entry);
7700 } else {
3db1cd5c 7701 hwbug = true;
b9e45482 7702 tnapi->tx_buffers[prvidx].fragmented = false;
e31aa987
MC		 7703 }
7704 }
7705 } else {
84b67b27
MC		 7706 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7707 len, flags, mss, vlan);
e31aa987
MC		 7708 *entry = NEXT_TX(*entry);
7709 }
d1a3b737
MC		 7710
7711 return hwbug;
7712}
7713
0d681b27 7714static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
432aa7ed
MC		 7715{
7716 int i;
0d681b27 7717 struct sk_buff *skb;
df8944cf 7718 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
432aa7ed 7719
0d681b27
MC		 7720 skb = txb->skb;
7721 txb->skb = NULL;
7722
432aa7ed
MC		 7723 pci_unmap_single(tnapi->tp->pdev,
7724 dma_unmap_addr(txb, mapping),
7725 skb_headlen(skb),
7726 PCI_DMA_TODEVICE);
e01ee14d
MC		 7727
7728 while (txb->fragmented) {
7729 txb->fragmented = false;
7730 entry = NEXT_TX(entry);
7731 txb = &tnapi->tx_buffers[entry];
7732 }
7733
ba1142e4 7734 for (i = 0; i <= last; i++) {
9e903e08 7735 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
432aa7ed
MC		 7736
7737 entry = NEXT_TX(entry);
7738 txb = &tnapi->tx_buffers[entry];
7739
7740 pci_unmap_page(tnapi->tp->pdev,
7741 dma_unmap_addr(txb, mapping),
9e903e08 7742 skb_frag_size(frag), PCI_DMA_TODEVICE);
e01ee14d
MC		 7743
7744 while (txb->fragmented) {
7745 txb->fragmented = false;
7746 entry = NEXT_TX(entry);
7747 txb = &tnapi->tx_buffers[entry];
7748 }
432aa7ed
MC		 7749 }
7750}
7751
72f2afb8 7752/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4 7753static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
f7ff1987 7754 struct sk_buff **pskb,
84b67b27 7755 u32 *entry, u32 *budget,
92cd3a17 7756 u32 base_flags, u32 mss, u32 vlan)
1da177e4 7757{
24f4efd4 7758 struct tg3 *tp = tnapi->tp;
f7ff1987 7759 struct sk_buff *new_skb, *skb = *pskb;
c58ec932 7760 dma_addr_t new_addr = 0;
432aa7ed 7761 int ret = 0;
1da177e4 7762
4153577a 7763 if (tg3_asic_rev(tp) != ASIC_REV_5701)
41588ba1
MC		 7764 new_skb = skb_copy(skb, GFP_ATOMIC);
7765 else {
7766 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7767
7768 new_skb = skb_copy_expand(skb,
7769 skb_headroom(skb) + more_headroom,
7770 skb_tailroom(skb), GFP_ATOMIC);
7771 }
7772
1da177e4 7773 if (!new_skb) {
c58ec932
MC		 7774 ret = -1;
7775 } else {
7776 /* New SKB is guaranteed to be linear. */
f4188d8a
AD		 7777 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7778 PCI_DMA_TODEVICE);
7779 /* Make sure the mapping succeeded */
7780 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
f4188d8a 7781 dev_kfree_skb(new_skb);
c58ec932 7782 ret = -1;
c58ec932 7783 } else {
b9e45482
MC		 7784 u32 save_entry = *entry;
7785
92cd3a17
MC		 7786 base_flags |= TXD_FLAG_END;
7787
84b67b27
MC		 7788 tnapi->tx_buffers[*entry].skb = new_skb;
7789 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
432aa7ed
MC		 7790 mapping, new_addr);
7791
84b67b27 7792 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
d1a3b737
MC		 7793 new_skb->len, base_flags,
7794 mss, vlan)) {
ba1142e4 7795 tg3_tx_skb_unmap(tnapi, save_entry, -1);
d1a3b737
MC		 7796 dev_kfree_skb(new_skb);
7797 ret = -1;
7798 }
f4188d8a 7799 }
1da177e4
LT		 7800 }
7801
7802 dev_kfree_skb(skb);
f7ff1987 7803 *pskb = new_skb;
c58ec932 7804 return ret;
1da177e4
LT		 7805}
7806
2ffcc981 7807static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
52c0fd83
MC		 7808
7809/* Use GSO to workaround a rare TSO bug that may be triggered when the
7810 * TSO header is greater than 80 bytes.
7811 */
7812static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
7813{
7814 struct sk_buff *segs, *nskb;
f3f3f27e 7815 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 7816
7817 /* Estimate the number of fragments in the worst case */
f3f3f27e 7818 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 7819 netif_stop_queue(tp->dev);
f65aac16
MC		 7820
7821 /* netif_tx_stop_queue() must be done before checking
7822 * checking tx index in tg3_tx_avail() below, because in
7823 * tg3_tx(), we update tx index before checking for
7824 * netif_tx_queue_stopped().
7825 */
7826 smp_mb();
f3f3f27e 7827 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 7828 return NETDEV_TX_BUSY;
7829
7830 netif_wake_queue(tp->dev);
52c0fd83
MC		 7831 }
7832
7833 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 7834 if (IS_ERR(segs))
52c0fd83
MC		 7835 goto tg3_tso_bug_end;
7836
7837 do {
7838 nskb = segs;
7839 segs = segs->next;
7840 nskb->next = NULL;
2ffcc981 7841 tg3_start_xmit(nskb, tp->dev);
52c0fd83
MC		 7842 } while (segs);
7843
7844tg3_tso_bug_end:
7845 dev_kfree_skb(skb);
7846
7847 return NETDEV_TX_OK;
7848}
52c0fd83 7849
5a6f3074 7850/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
63c3a66f 7851 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
5a6f3074 7852 */
2ffcc981 7853static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 7854{
7855 struct tg3 *tp = netdev_priv(dev);
92cd3a17 7856 u32 len, entry, base_flags, mss, vlan = 0;
84b67b27 7857 u32 budget;
432aa7ed 7858 int i = -1, would_hit_hwbug;
90079ce8 7859 dma_addr_t mapping;
24f4efd4
MC		 7860 struct tg3_napi *tnapi;
7861 struct netdev_queue *txq;
432aa7ed 7862 unsigned int last;
f4188d8a 7863
24f4efd4
MC		 7864 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7865 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
63c3a66f 7866 if (tg3_flag(tp, ENABLE_TSS))
24f4efd4 7867 tnapi++;
1da177e4 7868
84b67b27
MC		 7869 budget = tg3_tx_avail(tnapi);
7870
00b70504 7871 /* We are running in BH disabled context with netif_tx_lock
bea3348e 7872 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 7873 * interrupt. Furthermore, IRQ processing runs lockless so we have
7874 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 7875 */
84b67b27 7876 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 7877 if (!netif_tx_queue_stopped(txq)) {
7878 netif_tx_stop_queue(txq);
1f064a87
SH		 7879
7880 /* This is a hard error, log it. */
5129c3a3
MC		 7881 netdev_err(dev,
7882 "BUG! Tx Ring full when queue awake!\n");
1f064a87 7883 }
1da177e4
LT		 7884 return NETDEV_TX_BUSY;
7885 }
7886
f3f3f27e 7887 entry = tnapi->tx_prod;
1da177e4 7888 base_flags = 0;
84fa7933 7889 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 7890 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 7891
be98da6a
MC		 7892 mss = skb_shinfo(skb)->gso_size;
7893 if (mss) {
eddc9ec5 7894 struct iphdr *iph;
34195c3d 7895 u32 tcp_opt_len, hdr_len;
1da177e4
LT		 7896
7897 if (skb_header_cloned(skb) &&
48855432
ED		 7898 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7899 goto drop;
1da177e4 7900
34195c3d 7901 iph = ip_hdr(skb);
ab6a5bb6 7902 tcp_opt_len = tcp_optlen(skb);
1da177e4 7903
a5a11955 7904 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
34195c3d 7905
a5a11955 7906 if (!skb_is_gso_v6(skb)) {
34195c3d
MC		 7907 iph->check = 0;
7908 iph->tot_len = htons(mss + hdr_len);
7909 }
7910
52c0fd83 7911 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
63c3a66f 7912 tg3_flag(tp, TSO_BUG))
de6f31eb 7913 return tg3_tso_bug(tp, skb);
52c0fd83 7914
1da177e4
LT		 7915 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7916 TXD_FLAG_CPU_POST_DMA);
7917
63c3a66f
JP		 7918 if (tg3_flag(tp, HW_TSO_1) ||
7919 tg3_flag(tp, HW_TSO_2) ||
7920 tg3_flag(tp, HW_TSO_3)) {
aa8223c7 7921 tcp_hdr(skb)->check = 0;
1da177e4 7922 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 7923 } else
7924 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7925 iph->daddr, 0,
7926 IPPROTO_TCP,
7927 0);
1da177e4 7928
63c3a66f 7929 if (tg3_flag(tp, HW_TSO_3)) {
615774fe
MC		 7930 mss |= (hdr_len & 0xc) << 12;
7931 if (hdr_len & 0x10)
7932 base_flags |= 0x00000010;
7933 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 7934 } else if (tg3_flag(tp, HW_TSO_2))
92c6b8d1 7935 mss |= hdr_len << 9;
63c3a66f 7936 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 7937 tg3_asic_rev(tp) == ASIC_REV_5705) {
eddc9ec5 7938 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7939 int tsflags;
7940
eddc9ec5 7941 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7942 mss |= (tsflags << 11);
7943 }
7944 } else {
eddc9ec5 7945 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7946 int tsflags;
7947
eddc9ec5 7948 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7949 base_flags |= tsflags << 12;
7950 }
7951 }
7952 }
bf933c80 7953
93a700a9
MC		 7954 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7955 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7956 base_flags |= TXD_FLAG_JMB_PKT;
7957
92cd3a17
MC		 7958 if (vlan_tx_tag_present(skb)) {
7959 base_flags |= TXD_FLAG_VLAN;
7960 vlan = vlan_tx_tag_get(skb);
7961 }
1da177e4 7962
fb4ce8ad
MC		 7963 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
7964 tg3_flag(tp, TX_TSTAMP_EN)) {
7965 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7966 base_flags |= TXD_FLAG_HWTSTAMP;
7967 }
7968
f4188d8a
AD		 7969 len = skb_headlen(skb);
7970
7971 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
48855432
ED		 7972 if (pci_dma_mapping_error(tp->pdev, mapping))
7973 goto drop;
7974
90079ce8 7975
f3f3f27e 7976 tnapi->tx_buffers[entry].skb = skb;
4e5e4f0d 7977 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 7978
7979 would_hit_hwbug = 0;
7980
63c3a66f 7981 if (tg3_flag(tp, 5701_DMA_BUG))
c58ec932 7982 would_hit_hwbug = 1;
1da177e4 7983
84b67b27 7984 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
d1a3b737 7985 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
ba1142e4 7986 mss, vlan)) {
d1a3b737 7987 would_hit_hwbug = 1;
ba1142e4 7988 } else if (skb_shinfo(skb)->nr_frags > 0) {
92cd3a17
MC		 7989 u32 tmp_mss = mss;
7990
7991 if (!tg3_flag(tp, HW_TSO_1) &&
7992 !tg3_flag(tp, HW_TSO_2) &&
7993 !tg3_flag(tp, HW_TSO_3))
7994 tmp_mss = 0;
7995
c5665a53
MC		 7996 /* Now loop through additional data
7997 * fragments, and queue them.
7998 */
1da177e4
LT		 7999 last = skb_shinfo(skb)->nr_frags - 1;
8000 for (i = 0; i <= last; i++) {
8001 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8002
9e903e08 8003 len = skb_frag_size(frag);
dc234d0b 8004 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
5d6bcdfe 8005 len, DMA_TO_DEVICE);
1da177e4 8006
f3f3f27e 8007 tnapi->tx_buffers[entry].skb = NULL;
4e5e4f0d 8008 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
f4188d8a 8009 mapping);
5d6bcdfe 8010 if (dma_mapping_error(&tp->pdev->dev, mapping))
f4188d8a 8011 goto dma_error;
1da177e4 8012
b9e45482
MC		 8013 if (!budget ||
8014 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
84b67b27
MC		 8015 len, base_flags |
8016 ((i == last) ? TXD_FLAG_END : 0),
b9e45482 8017 tmp_mss, vlan)) {
72f2afb8 8018 would_hit_hwbug = 1;
b9e45482
MC		 8019 break;
8020 }
1da177e4
LT		 8021 }
8022 }
8023
8024 if (would_hit_hwbug) {
0d681b27 8025 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
1da177e4
LT		 8026
8027 /* If the workaround fails due to memory/mapping
8028 * failure, silently drop this packet.
8029 */
84b67b27
MC		 8030 entry = tnapi->tx_prod;
8031 budget = tg3_tx_avail(tnapi);
f7ff1987 8032 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
84b67b27 8033 base_flags, mss, vlan))
48855432 8034 goto drop_nofree;
1da177e4
LT		 8035 }
8036
d515b450 8037 skb_tx_timestamp(skb);
5cb917bc 8038 netdev_tx_sent_queue(txq, skb->len);
d515b450 8039
6541b806
MC		 8040 /* Sync BD data before updating mailbox */
8041 wmb();
8042
1da177e4 8043 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 8044 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 8045
f3f3f27e
MC		 8046 tnapi->tx_prod = entry;
8047 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 8048 netif_tx_stop_queue(txq);
f65aac16
MC		 8049
8050 /* netif_tx_stop_queue() must be done before checking
8051 * checking tx index in tg3_tx_avail() below, because in
8052 * tg3_tx(), we update tx index before checking for
8053 * netif_tx_queue_stopped().
8054 */
8055 smp_mb();
f3f3f27e 8056 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 8057 netif_tx_wake_queue(txq);
51b91468 8058 }
1da177e4 8059
cdd0db05 8060 mmiowb();
1da177e4 8061 return NETDEV_TX_OK;
f4188d8a
AD		 8062
8063dma_error:
ba1142e4 8064 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
432aa7ed 8065 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
48855432
ED		 8066drop:
8067 dev_kfree_skb(skb);
8068drop_nofree:
8069 tp->tx_dropped++;
f4188d8a 8070 return NETDEV_TX_OK;
1da177e4
LT		 8071}
8072
6e01b20b
MC		 8073static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8074{
8075 if (enable) {
8076 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8077 MAC_MODE_PORT_MODE_MASK);
8078
8079 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8080
8081 if (!tg3_flag(tp, 5705_PLUS))
8082 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8083
8084 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8085 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8086 else
8087 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8088 } else {
8089 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8090
8091 if (tg3_flag(tp, 5705_PLUS) ||
8092 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
4153577a 8093 tg3_asic_rev(tp) == ASIC_REV_5700)
6e01b20b
MC		 8094 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8095 }
8096
8097 tw32(MAC_MODE, tp->mac_mode);
8098 udelay(40);
8099}
8100
941ec90f 8101static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
5e5a7f37 8102{
941ec90f 8103 u32 val, bmcr, mac_mode, ptest = 0;
5e5a7f37
MC		 8104
8105 tg3_phy_toggle_apd(tp, false);
953c96e0 8106 tg3_phy_toggle_automdix(tp, false);
5e5a7f37 8107
941ec90f
MC		 8108 if (extlpbk && tg3_phy_set_extloopbk(tp))
8109 return -EIO;
8110
8111 bmcr = BMCR_FULLDPLX;
5e5a7f37
MC		 8112 switch (speed) {
8113 case SPEED_10:
8114 break;
8115 case SPEED_100:
8116 bmcr |= BMCR_SPEED100;
8117 break;
8118 case SPEED_1000:
8119 default:
8120 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8121 speed = SPEED_100;
8122 bmcr |= BMCR_SPEED100;
8123 } else {
8124 speed = SPEED_1000;
8125 bmcr |= BMCR_SPEED1000;
8126 }
8127 }
8128
941ec90f
MC		 8129 if (extlpbk) {
8130 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8131 tg3_readphy(tp, MII_CTRL1000, &val);
8132 val |= CTL1000_AS_MASTER |
8133 CTL1000_ENABLE_MASTER;
8134 tg3_writephy(tp, MII_CTRL1000, val);
8135 } else {
8136 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8137 MII_TG3_FET_PTEST_TRIM_2;
8138 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8139 }
8140 } else
8141 bmcr |= BMCR_LOOPBACK;
8142
5e5a7f37
MC		 8143 tg3_writephy(tp, MII_BMCR, bmcr);
8144
8145 /* The write needs to be flushed for the FETs */
8146 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8147 tg3_readphy(tp, MII_BMCR, &bmcr);
8148
8149 udelay(40);
8150
8151 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a 8152 tg3_asic_rev(tp) == ASIC_REV_5785) {
941ec90f 8153 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
5e5a7f37
MC		 8154 MII_TG3_FET_PTEST_FRC_TX_LINK |
8155 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8156
8157 /* The write needs to be flushed for the AC131 */
8158 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8159 }
8160
8161 /* Reset to prevent losing 1st rx packet intermittently */
8162 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8163 tg3_flag(tp, 5780_CLASS)) {
8164 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8165 udelay(10);
8166 tw32_f(MAC_RX_MODE, tp->rx_mode);
8167 }
8168
8169 mac_mode = tp->mac_mode &
8170 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8171 if (speed == SPEED_1000)
8172 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8173 else
8174 mac_mode |= MAC_MODE_PORT_MODE_MII;
8175
4153577a 8176 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5e5a7f37
MC		 8177 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8178
8179 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8180 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8181 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8182 mac_mode |= MAC_MODE_LINK_POLARITY;
8183
8184 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8185 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8186 }
8187
8188 tw32(MAC_MODE, mac_mode);
8189 udelay(40);
941ec90f
MC		 8190
8191 return 0;
5e5a7f37
MC		 8192}
8193
c8f44aff 8194static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
06c03c02
MB		 8195{
8196 struct tg3 *tp = netdev_priv(dev);
8197
8198 if (features & NETIF_F_LOOPBACK) {
8199 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8200 return;
8201
06c03c02 8202 spin_lock_bh(&tp->lock);
6e01b20b 8203 tg3_mac_loopback(tp, true);
06c03c02
MB		 8204 netif_carrier_on(tp->dev);
8205 spin_unlock_bh(&tp->lock);
8206 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8207 } else {
8208 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8209 return;
8210
06c03c02 8211 spin_lock_bh(&tp->lock);
6e01b20b 8212 tg3_mac_loopback(tp, false);
06c03c02 8213 /* Force link status check */
953c96e0 8214 tg3_setup_phy(tp, true);
06c03c02
MB		 8215 spin_unlock_bh(&tp->lock);
8216 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8217 }
8218}
8219
c8f44aff
MM		 8220static netdev_features_t tg3_fix_features(struct net_device *dev,
8221 netdev_features_t features)
dc668910
MM		 8222{
8223 struct tg3 *tp = netdev_priv(dev);
8224
63c3a66f 8225 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
dc668910
MM		 8226 features &= ~NETIF_F_ALL_TSO;
8227
8228 return features;
8229}
8230
c8f44aff 8231static int tg3_set_features(struct net_device *dev, netdev_features_t features)
06c03c02 8232{
c8f44aff 8233 netdev_features_t changed = dev->features ^ features;
06c03c02
MB		 8234
8235 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8236 tg3_set_loopback(dev, features);
8237
8238 return 0;
8239}
8240
21f581a5
MC		 8241static void tg3_rx_prodring_free(struct tg3 *tp,
8242 struct tg3_rx_prodring_set *tpr)
1da177e4 8243{
1da177e4
LT		 8244 int i;
8245
8fea32b9 8246 if (tpr != &tp->napi[0].prodring) {
b196c7e4 8247 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
2c49a44d 8248 i = (i + 1) & tp->rx_std_ring_mask)
9205fd9c 8249 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
b196c7e4
MC		 8250 tp->rx_pkt_map_sz);
8251
63c3a66f 8252 if (tg3_flag(tp, JUMBO_CAPABLE)) {
b196c7e4
MC		 8253 for (i = tpr->rx_jmb_cons_idx;
8254 i != tpr->rx_jmb_prod_idx;
2c49a44d 8255 i = (i + 1) & tp->rx_jmb_ring_mask) {
9205fd9c 8256 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
b196c7e4
MC		 8257 TG3_RX_JMB_MAP_SZ);
8258 }
8259 }
8260
2b2cdb65 8261 return;
b196c7e4 8262 }
1da177e4 8263
2c49a44d 8264 for (i = 0; i <= tp->rx_std_ring_mask; i++)
9205fd9c 8265 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
2b2cdb65 8266 tp->rx_pkt_map_sz);
1da177e4 8267
63c3a66f 8268 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8269 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
9205fd9c 8270 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
2b2cdb65 8271 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 8272 }
8273}
8274
c6cdf436 8275/* Initialize rx rings for packet processing.
1da177e4
LT		 8276 *
8277 * The chip has been shut down and the driver detached from
8278 * the networking, so no interrupts or new tx packets will
8279 * end up in the driver. tp->{tx,}lock are held and thus
8280 * we may not sleep.
8281 */
21f581a5
MC		 8282static int tg3_rx_prodring_alloc(struct tg3 *tp,
8283 struct tg3_rx_prodring_set *tpr)
1da177e4 8284{
287be12e 8285 u32 i, rx_pkt_dma_sz;
1da177e4 8286
b196c7e4
MC		 8287 tpr->rx_std_cons_idx = 0;
8288 tpr->rx_std_prod_idx = 0;
8289 tpr->rx_jmb_cons_idx = 0;
8290 tpr->rx_jmb_prod_idx = 0;
8291
8fea32b9 8292 if (tpr != &tp->napi[0].prodring) {
2c49a44d
MC		 8293 memset(&tpr->rx_std_buffers[0], 0,
8294 TG3_RX_STD_BUFF_RING_SIZE(tp));
48035728 8295 if (tpr->rx_jmb_buffers)
2b2cdb65 8296 memset(&tpr->rx_jmb_buffers[0], 0,
2c49a44d 8297 TG3_RX_JMB_BUFF_RING_SIZE(tp));
2b2cdb65
MC		 8298 goto done;
8299 }
8300
1da177e4 8301 /* Zero out all descriptors. */
2c49a44d 8302 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
1da177e4 8303
287be12e 8304 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
63c3a66f 8305 if (tg3_flag(tp, 5780_CLASS) &&
287be12e
MC		 8306 tp->dev->mtu > ETH_DATA_LEN)
8307 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8308 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 8309
1da177e4
LT		 8310 /* Initialize invariants of the rings, we only set this
8311 * stuff once. This works because the card does not
8312 * write into the rx buffer posting rings.
8313 */
2c49a44d 8314 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
1da177e4
LT		 8315 struct tg3_rx_buffer_desc *rxd;
8316
21f581a5 8317 rxd = &tpr->rx_std[i];
287be12e 8318 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 8319 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8320 rxd->opaque = (RXD_OPAQUE_RING_STD |
8321 (i << RXD_OPAQUE_INDEX_SHIFT));
8322 }
8323
1da177e4
LT		 8324 /* Now allocate fresh SKBs for each rx ring. */
8325 for (i = 0; i < tp->rx_pending; i++) {
8d4057a9
ED		 8326 unsigned int frag_size;
8327
8328 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8329 &frag_size) < 0) {
5129c3a3
MC		 8330 netdev_warn(tp->dev,
8331 "Using a smaller RX standard ring. Only "
8332 "%d out of %d buffers were allocated "
8333 "successfully\n", i, tp->rx_pending);
32d8c572 8334 if (i == 0)
cf7a7298 8335 goto initfail;
32d8c572 8336 tp->rx_pending = i;
1da177e4 8337 break;
32d8c572 8338 }
1da177e4
LT		 8339 }
8340
63c3a66f 8341 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
cf7a7298
MC		 8342 goto done;
8343
2c49a44d 8344 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
cf7a7298 8345
63c3a66f 8346 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
0d86df80 8347 goto done;
cf7a7298 8348
2c49a44d 8349 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
0d86df80
MC		 8350 struct tg3_rx_buffer_desc *rxd;
8351
8352 rxd = &tpr->rx_jmb[i].std;
8353 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8354 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8355 RXD_FLAG_JUMBO;
8356 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8357 (i << RXD_OPAQUE_INDEX_SHIFT));
8358 }
8359
8360 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8d4057a9
ED		 8361 unsigned int frag_size;
8362
8363 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8364 &frag_size) < 0) {
5129c3a3
MC		 8365 netdev_warn(tp->dev,
8366 "Using a smaller RX jumbo ring. Only %d "
8367 "out of %d buffers were allocated "
8368 "successfully\n", i, tp->rx_jumbo_pending);
0d86df80
MC		 8369 if (i == 0)
8370 goto initfail;
8371 tp->rx_jumbo_pending = i;
8372 break;
1da177e4
LT		 8373 }
8374 }
cf7a7298
MC		 8375
8376done:
32d8c572 8377 return 0;
cf7a7298
MC		 8378
8379initfail:
21f581a5 8380 tg3_rx_prodring_free(tp, tpr);
cf7a7298 8381 return -ENOMEM;
1da177e4
LT		 8382}
8383
21f581a5
MC		 8384static void tg3_rx_prodring_fini(struct tg3 *tp,
8385 struct tg3_rx_prodring_set *tpr)
1da177e4 8386{
21f581a5
MC		 8387 kfree(tpr->rx_std_buffers);
8388 tpr->rx_std_buffers = NULL;
8389 kfree(tpr->rx_jmb_buffers);
8390 tpr->rx_jmb_buffers = NULL;
8391 if (tpr->rx_std) {
4bae65c8
MC		 8392 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8393 tpr->rx_std, tpr->rx_std_mapping);
21f581a5 8394 tpr->rx_std = NULL;
1da177e4 8395 }
21f581a5 8396 if (tpr->rx_jmb) {
4bae65c8
MC		 8397 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8398 tpr->rx_jmb, tpr->rx_jmb_mapping);
21f581a5 8399 tpr->rx_jmb = NULL;
1da177e4 8400 }
cf7a7298
MC		 8401}
8402
21f581a5
MC		 8403static int tg3_rx_prodring_init(struct tg3 *tp,
8404 struct tg3_rx_prodring_set *tpr)
cf7a7298 8405{
2c49a44d
MC		 8406 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8407 GFP_KERNEL);
21f581a5 8408 if (!tpr->rx_std_buffers)
cf7a7298
MC		 8409 return -ENOMEM;
8410
4bae65c8
MC		 8411 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8412 TG3_RX_STD_RING_BYTES(tp),
8413 &tpr->rx_std_mapping,
8414 GFP_KERNEL);
21f581a5 8415 if (!tpr->rx_std)
cf7a7298
MC		 8416 goto err_out;
8417
63c3a66f 8418 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8419 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
21f581a5
MC		 8420 GFP_KERNEL);
8421 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 8422 goto err_out;
8423
4bae65c8
MC		 8424 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8425 TG3_RX_JMB_RING_BYTES(tp),
8426 &tpr->rx_jmb_mapping,
8427 GFP_KERNEL);
21f581a5 8428 if (!tpr->rx_jmb)
cf7a7298
MC		 8429 goto err_out;
8430 }
8431
8432 return 0;
8433
8434err_out:
21f581a5 8435 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 8436 return -ENOMEM;
8437}
8438
8439/* Free up pending packets in all rx/tx rings.
8440 *
8441 * The chip has been shut down and the driver detached from
8442 * the networking, so no interrupts or new tx packets will
8443 * end up in the driver. tp->{tx,}lock is not held and we are not
8444 * in an interrupt context and thus may sleep.
8445 */
8446static void tg3_free_rings(struct tg3 *tp)
8447{
f77a6a8e 8448 int i, j;
cf7a7298 8449
f77a6a8e
MC		 8450 for (j = 0; j < tp->irq_cnt; j++) {
8451 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 8452
8fea32b9 8453 tg3_rx_prodring_free(tp, &tnapi->prodring);
b28f6428 8454
0c1d0e2b
MC		 8455 if (!tnapi->tx_buffers)
8456 continue;
8457
0d681b27
MC		 8458 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8459 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
cf7a7298 8460
0d681b27 8461 if (!skb)
f77a6a8e 8462 continue;
cf7a7298 8463
ba1142e4
MC		 8464 tg3_tx_skb_unmap(tnapi, i,
8465 skb_shinfo(skb)->nr_frags - 1);
f77a6a8e
MC		 8466
8467 dev_kfree_skb_any(skb);
8468 }
5cb917bc 8469 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
2b2cdb65 8470 }
cf7a7298
MC		 8471}
8472
8473/* Initialize tx/rx rings for packet processing.
8474 *
8475 * The chip has been shut down and the driver detached from
8476 * the networking, so no interrupts or new tx packets will
8477 * end up in the driver. tp->{tx,}lock are held and thus
8478 * we may not sleep.
8479 */
8480static int tg3_init_rings(struct tg3 *tp)
8481{
f77a6a8e 8482 int i;
72334482 8483
cf7a7298
MC		 8484 /* Free up all the SKBs. */
8485 tg3_free_rings(tp);
8486
f77a6a8e
MC		 8487 for (i = 0; i < tp->irq_cnt; i++) {
8488 struct tg3_napi *tnapi = &tp->napi[i];
8489
8490 tnapi->last_tag = 0;
8491 tnapi->last_irq_tag = 0;
8492 tnapi->hw_status->status = 0;
8493 tnapi->hw_status->status_tag = 0;
8494 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 8495
f77a6a8e
MC		 8496 tnapi->tx_prod = 0;
8497 tnapi->tx_cons = 0;
0c1d0e2b
MC		 8498 if (tnapi->tx_ring)
8499 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 8500
8501 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 8502 if (tnapi->rx_rcb)
8503 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 8504
8fea32b9 8505 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
e4af1af9 8506 tg3_free_rings(tp);
2b2cdb65 8507 return -ENOMEM;
e4af1af9 8508 }
f77a6a8e 8509 }
72334482 8510
2b2cdb65 8511 return 0;
cf7a7298
MC		 8512}
8513
49a359e3 8514static void tg3_mem_tx_release(struct tg3 *tp)
cf7a7298 8515{
f77a6a8e 8516 int i;
898a56f8 8517
49a359e3 8518 for (i = 0; i < tp->irq_max; i++) {
f77a6a8e
MC		 8519 struct tg3_napi *tnapi = &tp->napi[i];
8520
8521 if (tnapi->tx_ring) {
4bae65c8 8522 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
f77a6a8e
MC		 8523 tnapi->tx_ring, tnapi->tx_desc_mapping);
8524 tnapi->tx_ring = NULL;
8525 }
8526
8527 kfree(tnapi->tx_buffers);
8528 tnapi->tx_buffers = NULL;
49a359e3
MC		 8529 }
8530}
f77a6a8e 8531
49a359e3
MC		 8532static int tg3_mem_tx_acquire(struct tg3 *tp)
8533{
8534 int i;
8535 struct tg3_napi *tnapi = &tp->napi[0];
8536
8537 /* If multivector TSS is enabled, vector 0 does not handle
8538 * tx interrupts. Don't allocate any resources for it.
8539 */
8540 if (tg3_flag(tp, ENABLE_TSS))
8541 tnapi++;
8542
8543 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8544 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8545 TG3_TX_RING_SIZE, GFP_KERNEL);
8546 if (!tnapi->tx_buffers)
8547 goto err_out;
8548
8549 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8550 TG3_TX_RING_BYTES,
8551 &tnapi->tx_desc_mapping,
8552 GFP_KERNEL);
8553 if (!tnapi->tx_ring)
8554 goto err_out;
8555 }
8556
8557 return 0;
8558
8559err_out:
8560 tg3_mem_tx_release(tp);
8561 return -ENOMEM;
8562}
8563
8564static void tg3_mem_rx_release(struct tg3 *tp)
8565{
8566 int i;
8567
8568 for (i = 0; i < tp->irq_max; i++) {
8569 struct tg3_napi *tnapi = &tp->napi[i];
f77a6a8e 8570
8fea32b9
MC		 8571 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8572
49a359e3
MC		 8573 if (!tnapi->rx_rcb)
8574 continue;
8575
8576 dma_free_coherent(&tp->pdev->dev,
8577 TG3_RX_RCB_RING_BYTES(tp),
8578 tnapi->rx_rcb,
8579 tnapi->rx_rcb_mapping);
8580 tnapi->rx_rcb = NULL;
8581 }
8582}
8583
8584static int tg3_mem_rx_acquire(struct tg3 *tp)
8585{
8586 unsigned int i, limit;
8587
8588 limit = tp->rxq_cnt;
8589
8590 /* If RSS is enabled, we need a (dummy) producer ring
8591 * set on vector zero. This is the true hw prodring.
8592 */
8593 if (tg3_flag(tp, ENABLE_RSS))
8594 limit++;
8595
8596 for (i = 0; i < limit; i++) {
8597 struct tg3_napi *tnapi = &tp->napi[i];
8598
8599 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8600 goto err_out;
8601
8602 /* If multivector RSS is enabled, vector 0
8603 * does not handle rx or tx interrupts.
8604 * Don't allocate any resources for it.
8605 */
8606 if (!i && tg3_flag(tp, ENABLE_RSS))
8607 continue;
8608
ede23fa8
JP		 8609 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8610 TG3_RX_RCB_RING_BYTES(tp),
8611 &tnapi->rx_rcb_mapping,
8612 GFP_KERNEL);
49a359e3
MC		 8613 if (!tnapi->rx_rcb)
8614 goto err_out;
49a359e3
MC		 8615 }
8616
8617 return 0;
8618
8619err_out:
8620 tg3_mem_rx_release(tp);
8621 return -ENOMEM;
8622}
8623
8624/*
8625 * Must not be invoked with interrupt sources disabled and
8626 * the hardware shutdown down.
8627 */
8628static void tg3_free_consistent(struct tg3 *tp)
8629{
8630 int i;
8631
8632 for (i = 0; i < tp->irq_cnt; i++) {
8633 struct tg3_napi *tnapi = &tp->napi[i];
8634
f77a6a8e 8635 if (tnapi->hw_status) {
4bae65c8
MC		 8636 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8637 tnapi->hw_status,
8638 tnapi->status_mapping);
f77a6a8e
MC		 8639 tnapi->hw_status = NULL;
8640 }
1da177e4 8641 }
f77a6a8e 8642
49a359e3
MC		 8643 tg3_mem_rx_release(tp);
8644 tg3_mem_tx_release(tp);
8645
1da177e4 8646 if (tp->hw_stats) {
4bae65c8
MC		 8647 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8648 tp->hw_stats, tp->stats_mapping);
1da177e4
LT		 8649 tp->hw_stats = NULL;
8650 }
8651}
8652
8653/*
8654 * Must not be invoked with interrupt sources disabled and
8655 * the hardware shutdown down. Can sleep.
8656 */
8657static int tg3_alloc_consistent(struct tg3 *tp)
8658{
f77a6a8e 8659 int i;
898a56f8 8660
ede23fa8
JP		 8661 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8662 sizeof(struct tg3_hw_stats),
8663 &tp->stats_mapping, GFP_KERNEL);
f77a6a8e 8664 if (!tp->hw_stats)
1da177e4
LT		 8665 goto err_out;
8666
f77a6a8e
MC		 8667 for (i = 0; i < tp->irq_cnt; i++) {
8668 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 8669 struct tg3_hw_status *sblk;
1da177e4 8670
ede23fa8
JP		 8671 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8672 TG3_HW_STATUS_SIZE,
8673 &tnapi->status_mapping,
8674 GFP_KERNEL);
f77a6a8e
MC		 8675 if (!tnapi->hw_status)
8676 goto err_out;
898a56f8 8677
8d9d7cfc
MC		 8678 sblk = tnapi->hw_status;
8679
49a359e3 8680 if (tg3_flag(tp, ENABLE_RSS)) {
86449944 8681 u16 *prodptr = NULL;
8fea32b9 8682
49a359e3
MC		 8683 /*
8684 * When RSS is enabled, the status block format changes
8685 * slightly. The "rx_jumbo_consumer", "reserved",
8686 * and "rx_mini_consumer" members get mapped to the
8687 * other three rx return ring producer indexes.
8688 */
8689 switch (i) {
8690 case 1:
8691 prodptr = &sblk->idx[0].rx_producer;
8692 break;
8693 case 2:
8694 prodptr = &sblk->rx_jumbo_consumer;
8695 break;
8696 case 3:
8697 prodptr = &sblk->reserved;
8698 break;
8699 case 4:
8700 prodptr = &sblk->rx_mini_consumer;
f891ea16
MC		 8701 break;
8702 }
49a359e3
MC		 8703 tnapi->rx_rcb_prod_idx = prodptr;
8704 } else {
8d9d7cfc 8705 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8d9d7cfc 8706 }
f77a6a8e 8707 }
1da177e4 8708
49a359e3
MC		 8709 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8710 goto err_out;
8711
1da177e4
LT		 8712 return 0;
8713
8714err_out:
8715 tg3_free_consistent(tp);
8716 return -ENOMEM;
8717}
8718
8719#define MAX_WAIT_CNT 1000
8720
8721/* To stop a block, clear the enable bit and poll till it
8722 * clears. tp->lock is held.
8723 */
953c96e0 8724static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
1da177e4
LT		 8725{
8726 unsigned int i;
8727 u32 val;
8728
63c3a66f 8729 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 8730 switch (ofs) {
8731 case RCVLSC_MODE:
8732 case DMAC_MODE:
8733 case MBFREE_MODE:
8734 case BUFMGR_MODE:
8735 case MEMARB_MODE:
8736 /* We can't enable/disable these bits of the
8737 * 5705/5750, just say success.
8738 */
8739 return 0;
8740
8741 default:
8742 break;
855e1111 8743 }
1da177e4
LT		 8744 }
8745
8746 val = tr32(ofs);
8747 val &= ~enable_bit;
8748 tw32_f(ofs, val);
8749
8750 for (i = 0; i < MAX_WAIT_CNT; i++) {
6d446ec3
GS		 8751 if (pci_channel_offline(tp->pdev)) {
8752 dev_err(&tp->pdev->dev,
8753 "tg3_stop_block device offline, "
8754 "ofs=%lx enable_bit=%x\n",
8755 ofs, enable_bit);
8756 return -ENODEV;
8757 }
8758
1da177e4
LT		 8759 udelay(100);
8760 val = tr32(ofs);
8761 if ((val & enable_bit) == 0)
8762 break;
8763 }
8764
b3b7d6be 8765 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 8766 dev_err(&tp->pdev->dev,
8767 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8768 ofs, enable_bit);
1da177e4
LT		 8769 return -ENODEV;
8770 }
8771
8772 return 0;
8773}
8774
8775/* tp->lock is held. */
953c96e0 8776static int tg3_abort_hw(struct tg3 *tp, bool silent)
1da177e4
LT		 8777{
8778 int i, err;
8779
8780 tg3_disable_ints(tp);
8781
6d446ec3
GS		 8782 if (pci_channel_offline(tp->pdev)) {
8783 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8784 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8785 err = -ENODEV;
8786 goto err_no_dev;
8787 }
8788
1da177e4
LT		 8789 tp->rx_mode &= ~RX_MODE_ENABLE;
8790 tw32_f(MAC_RX_MODE, tp->rx_mode);
8791 udelay(10);
8792
b3b7d6be
DM		 8793 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8794 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8795 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8796 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8797 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8798 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8799
8800 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8801 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8802 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8803 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8804 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8805 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8806 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 8807
8808 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8809 tw32_f(MAC_MODE, tp->mac_mode);
8810 udelay(40);
8811
8812 tp->tx_mode &= ~TX_MODE_ENABLE;
8813 tw32_f(MAC_TX_MODE, tp->tx_mode);
8814
8815 for (i = 0; i < MAX_WAIT_CNT; i++) {
8816 udelay(100);
8817 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8818 break;
8819 }
8820 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 8821 dev_err(&tp->pdev->dev,
8822 "%s timed out, TX_MODE_ENABLE will not clear "
8823 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 8824 err |= -ENODEV;
1da177e4
LT		 8825 }
8826
e6de8ad1 8827 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 8828 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8829 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 8830
8831 tw32(FTQ_RESET, 0xffffffff);
8832 tw32(FTQ_RESET, 0x00000000);
8833
b3b7d6be
DM		 8834 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8835 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 8836
6d446ec3 8837err_no_dev:
f77a6a8e
MC		 8838 for (i = 0; i < tp->irq_cnt; i++) {
8839 struct tg3_napi *tnapi = &tp->napi[i];
8840 if (tnapi->hw_status)
8841 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8842 }
1da177e4 8843
1da177e4
LT		 8844 return err;
8845}
8846
ee6a99b5
MC		 8847/* Save PCI command register before chip reset */
8848static void tg3_save_pci_state(struct tg3 *tp)
8849{
8a6eac90 8850 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 8851}
8852
8853/* Restore PCI state after chip reset */
8854static void tg3_restore_pci_state(struct tg3 *tp)
8855{
8856 u32 val;
8857
8858 /* Re-enable indirect register accesses. */
8859 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8860 tp->misc_host_ctrl);
8861
8862 /* Set MAX PCI retry to zero. */
8863 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4153577a 8864 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 8865 tg3_flag(tp, PCIX_MODE))
ee6a99b5 8866 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9 8867 /* Allow reads and writes to the APE register and memory space. */
63c3a66f 8868 if (tg3_flag(tp, ENABLE_APE))
0d3031d9 8869 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 8870 PCISTATE_ALLOW_APE_SHMEM_WR |
8871 PCISTATE_ALLOW_APE_PSPACE_WR;
ee6a99b5
MC		 8872 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8873
8a6eac90 8874 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 8875
2c55a3d0
MC		 8876 if (!tg3_flag(tp, PCI_EXPRESS)) {
8877 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8878 tp->pci_cacheline_sz);
8879 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8880 tp->pci_lat_timer);
114342f2 8881 }
5f5c51e3 8882
ee6a99b5 8883 /* Make sure PCI-X relaxed ordering bit is clear. */
63c3a66f 8884 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 8885 u16 pcix_cmd;
8886
8887 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8888 &pcix_cmd);
8889 pcix_cmd &= ~PCI_X_CMD_ERO;
8890 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8891 pcix_cmd);
8892 }
ee6a99b5 8893
63c3a66f 8894 if (tg3_flag(tp, 5780_CLASS)) {
ee6a99b5
MC		 8895
8896 /* Chip reset on 5780 will reset MSI enable bit,
8897 * so need to restore it.
8898 */
63c3a66f 8899 if (tg3_flag(tp, USING_MSI)) {
ee6a99b5
MC		 8900 u16 ctrl;
8901
8902 pci_read_config_word(tp->pdev,
8903 tp->msi_cap + PCI_MSI_FLAGS,
8904 &ctrl);
8905 pci_write_config_word(tp->pdev,
8906 tp->msi_cap + PCI_MSI_FLAGS,
8907 ctrl | PCI_MSI_FLAGS_ENABLE);
8908 val = tr32(MSGINT_MODE);
8909 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8910 }
8911 }
8912}
8913
1da177e4
LT		 8914/* tp->lock is held. */
8915static int tg3_chip_reset(struct tg3 *tp)
8916{
8917 u32 val;
1ee582d8 8918 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 8919 int i, err;
1da177e4 8920
f49639e6
DM		 8921 tg3_nvram_lock(tp);
8922
77b483f1
MC		 8923 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
8924
f49639e6
DM		 8925 /* No matching tg3_nvram_unlock() after this because
8926 * chip reset below will undo the nvram lock.
8927 */
8928 tp->nvram_lock_cnt = 0;
1da177e4 8929
ee6a99b5
MC		 8930 /* GRC_MISC_CFG core clock reset will clear the memory
8931 * enable bit in PCI register 4 and the MSI enable bit
8932 * on some chips, so we save relevant registers here.
8933 */
8934 tg3_save_pci_state(tp);
8935
4153577a 8936 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
63c3a66f 8937 tg3_flag(tp, 5755_PLUS))
d9ab5ad1
MC		 8938 tw32(GRC_FASTBOOT_PC, 0);
8939
1da177e4
LT		 8940 /*
8941 * We must avoid the readl() that normally takes place.
8942 * It locks machines, causes machine checks, and other
8943 * fun things. So, temporarily disable the 5701
8944 * hardware workaround, while we do the reset.
8945 */
1ee582d8
MC		 8946 write_op = tp->write32;
8947 if (write_op == tg3_write_flush_reg32)
8948 tp->write32 = tg3_write32;
1da177e4 8949
d18edcb2
MC		 8950 /* Prevent the irq handler from reading or writing PCI registers
8951 * during chip reset when the memory enable bit in the PCI command
8952 * register may be cleared. The chip does not generate interrupt
8953 * at this time, but the irq handler may still be called due to irq
8954 * sharing or irqpoll.
8955 */
63c3a66f 8956 tg3_flag_set(tp, CHIP_RESETTING);
f77a6a8e
MC		 8957 for (i = 0; i < tp->irq_cnt; i++) {
8958 struct tg3_napi *tnapi = &tp->napi[i];
8959 if (tnapi->hw_status) {
8960 tnapi->hw_status->status = 0;
8961 tnapi->hw_status->status_tag = 0;
8962 }
8963 tnapi->last_tag = 0;
8964 tnapi->last_irq_tag = 0;
b8fa2f3a 8965 }
d18edcb2 8966 smp_mb();
4f125f42
MC		 8967
8968 for (i = 0; i < tp->irq_cnt; i++)
8969 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 8970
4153577a 8971 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
255ca311
MC		 8972 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8973 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8974 }
8975
1da177e4
LT		 8976 /* do the reset */
8977 val = GRC_MISC_CFG_CORECLK_RESET;
8978
63c3a66f 8979 if (tg3_flag(tp, PCI_EXPRESS)) {
88075d91 8980 /* Force PCIe 1.0a mode */
4153577a 8981 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 8982 !tg3_flag(tp, 57765_PLUS) &&
88075d91
MC		 8983 tr32(TG3_PCIE_PHY_TSTCTL) ==
8984 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
8985 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
8986
4153577a 8987 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
1da177e4
LT		 8988 tw32(GRC_MISC_CFG, (1 << 29));
8989 val |= (1 << 29);
8990 }
8991 }
8992
4153577a 8993 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 8994 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
8995 tw32(GRC_VCPU_EXT_CTRL,
8996 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
8997 }
8998
f37500d3 8999 /* Manage gphy power for all CPMU absent PCIe devices. */
63c3a66f 9000 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
1da177e4 9001 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
f37500d3 9002
1da177e4
LT		 9003 tw32(GRC_MISC_CFG, val);
9004
1ee582d8
MC		 9005 /* restore 5701 hardware bug workaround write method */
9006 tp->write32 = write_op;
1da177e4
LT		 9007
9008 /* Unfortunately, we have to delay before the PCI read back.
9009 * Some 575X chips even will not respond to a PCI cfg access
9010 * when the reset command is given to the chip.
9011 *
9012 * How do these hardware designers expect things to work
9013 * properly if the PCI write is posted for a long period
9014 * of time? It is always necessary to have some method by
9015 * which a register read back can occur to push the write
9016 * out which does the reset.
9017 *
9018 * For most tg3 variants the trick below was working.
9019 * Ho hum...
9020 */
9021 udelay(120);
9022
9023 /* Flush PCI posted writes. The normal MMIO registers
9024 * are inaccessible at this time so this is the only
9025 * way to make this reliably (actually, this is no longer
9026 * the case, see above). I tried to use indirect
9027 * register read/write but this upset some 5701 variants.
9028 */
9029 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9030
9031 udelay(120);
9032
0f49bfbd 9033 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
e7126997
MC		 9034 u16 val16;
9035
4153577a 9036 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
86449944 9037 int j;
1da177e4
LT		 9038 u32 cfg_val;
9039
9040 /* Wait for link training to complete. */
86449944 9041 for (j = 0; j < 5000; j++)
1da177e4
LT		 9042 udelay(100);
9043
9044 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9045 pci_write_config_dword(tp->pdev, 0xc4,
9046 cfg_val | (1 << 15));
9047 }
5e7dfd0f 9048
e7126997 9049 /* Clear the "no snoop" and "relaxed ordering" bits. */
0f49bfbd 9050 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
e7126997
MC		 9051 /*
9052 * Older PCIe devices only support the 128 byte
9053 * MPS setting. Enforce the restriction.
5e7dfd0f 9054 */
63c3a66f 9055 if (!tg3_flag(tp, CPMU_PRESENT))
0f49bfbd
JL		 9056 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9057 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
5e7dfd0f 9058
5e7dfd0f 9059 /* Clear error status */
0f49bfbd 9060 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
5e7dfd0f
MC		 9061 PCI_EXP_DEVSTA_CED |
9062 PCI_EXP_DEVSTA_NFED |
9063 PCI_EXP_DEVSTA_FED |
9064 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 9065 }
9066
ee6a99b5 9067 tg3_restore_pci_state(tp);
1da177e4 9068
63c3a66f
JP		 9069 tg3_flag_clear(tp, CHIP_RESETTING);
9070 tg3_flag_clear(tp, ERROR_PROCESSED);
d18edcb2 9071
ee6a99b5 9072 val = 0;
63c3a66f 9073 if (tg3_flag(tp, 5780_CLASS))
4cf78e4f 9074 val = tr32(MEMARB_MODE);
ee6a99b5 9075 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4 9076
4153577a 9077 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
1da177e4
LT		 9078 tg3_stop_fw(tp);
9079 tw32(0x5000, 0x400);
9080 }
9081
7e6c63f0
HM		 9082 if (tg3_flag(tp, IS_SSB_CORE)) {
9083 /*
9084 * BCM4785: In order to avoid repercussions from using
9085 * potentially defective internal ROM, stop the Rx RISC CPU,
9086 * which is not required.
9087 */
9088 tg3_stop_fw(tp);
9089 tg3_halt_cpu(tp, RX_CPU_BASE);
9090 }
9091
fb03a43f
NS		 9092 err = tg3_poll_fw(tp);
9093 if (err)
9094 return err;
9095
1da177e4
LT		 9096 tw32(GRC_MODE, tp->grc_mode);
9097
4153577a 9098 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
ab0049b4 9099 val = tr32(0xc4);
1da177e4
LT		 9100
9101 tw32(0xc4, val | (1 << 15));
9102 }
9103
9104 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4153577a 9105 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4 9106 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4153577a 9107 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
1da177e4
LT		 9108 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9109 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9110 }
9111
f07e9af3 9112 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9e975cc2 9113 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
d2394e6b 9114 val = tp->mac_mode;
f07e9af3 9115 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9e975cc2 9116 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
d2394e6b 9117 val = tp->mac_mode;
1da177e4 9118 } else
d2394e6b
MC		 9119 val = 0;
9120
9121 tw32_f(MAC_MODE, val);
1da177e4
LT		 9122 udelay(40);
9123
77b483f1
MC		 9124 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9125
0a9140cf
MC		 9126 tg3_mdio_start(tp);
9127
63c3a66f 9128 if (tg3_flag(tp, PCI_EXPRESS) &&
4153577a
JP		 9129 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9130 tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9131 !tg3_flag(tp, 57765_PLUS)) {
ab0049b4 9132 val = tr32(0x7c00);
1da177e4
LT		 9133
9134 tw32(0x7c00, val | (1 << 25));
9135 }
9136
4153577a 9137 if (tg3_asic_rev(tp) == ASIC_REV_5720) {
d78b59f5
MC		 9138 val = tr32(TG3_CPMU_CLCK_ORIDE);
9139 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9140 }
9141
1da177e4 9142 /* Reprobe ASF enable state. */
63c3a66f 9143 tg3_flag_clear(tp, ENABLE_ASF);
942d1af0
NS		 9144 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9145 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9146
63c3a66f 9147 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
1da177e4
LT		 9148 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9149 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9150 u32 nic_cfg;
9151
9152 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9153 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f 9154 tg3_flag_set(tp, ENABLE_ASF);
4ba526ce 9155 tp->last_event_jiffies = jiffies;
63c3a66f
JP		 9156 if (tg3_flag(tp, 5750_PLUS))
9157 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
942d1af0
NS		 9158
9159 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9160 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9161 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9162 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9163 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
1da177e4
LT		 9164 }
9165 }
9166
9167 return 0;
9168}
9169
65ec698d
MC		 9170static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9171static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
92feeabf 9172
1da177e4 9173/* tp->lock is held. */
953c96e0 9174static int tg3_halt(struct tg3 *tp, int kind, bool silent)
1da177e4
LT		 9175{
9176 int err;
9177
9178 tg3_stop_fw(tp);
9179
944d980e 9180 tg3_write_sig_pre_reset(tp, kind);
1da177e4 9181
b3b7d6be 9182 tg3_abort_hw(tp, silent);
1da177e4
LT		 9183 err = tg3_chip_reset(tp);
9184
953c96e0 9185 __tg3_set_mac_addr(tp, false);
daba2a63 9186
944d980e
MC		 9187 tg3_write_sig_legacy(tp, kind);
9188 tg3_write_sig_post_reset(tp, kind);
1da177e4 9189
92feeabf
MC		 9190 if (tp->hw_stats) {
9191 /* Save the stats across chip resets... */
b4017c53 9192 tg3_get_nstats(tp, &tp->net_stats_prev);
92feeabf
MC		 9193 tg3_get_estats(tp, &tp->estats_prev);
9194
9195 /* And make sure the next sample is new data */
9196 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9197 }
9198
1da177e4
LT		 9199 if (err)
9200 return err;
9201
9202 return 0;
9203}
9204
1da177e4
LT		 9205static int tg3_set_mac_addr(struct net_device *dev, void *p)
9206{
9207 struct tg3 *tp = netdev_priv(dev);
9208 struct sockaddr *addr = p;
953c96e0
JP		 9209 int err = 0;
9210 bool skip_mac_1 = false;
1da177e4 9211
f9804ddb 9212 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 9213 return -EADDRNOTAVAIL;
f9804ddb 9214
1da177e4
LT		 9215 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9216
e75f7c90
MC		 9217 if (!netif_running(dev))
9218 return 0;
9219
63c3a66f 9220 if (tg3_flag(tp, ENABLE_ASF)) {
986e0aeb 9221 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 9222
986e0aeb
MC		 9223 addr0_high = tr32(MAC_ADDR_0_HIGH);
9224 addr0_low = tr32(MAC_ADDR_0_LOW);
9225 addr1_high = tr32(MAC_ADDR_1_HIGH);
9226 addr1_low = tr32(MAC_ADDR_1_LOW);
9227
9228 /* Skip MAC addr 1 if ASF is using it. */
9229 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9230 !(addr1_high == 0 && addr1_low == 0))
953c96e0 9231 skip_mac_1 = true;
58712ef9 9232 }
986e0aeb
MC		 9233 spin_lock_bh(&tp->lock);
9234 __tg3_set_mac_addr(tp, skip_mac_1);
9235 spin_unlock_bh(&tp->lock);
1da177e4 9236
b9ec6c1b 9237 return err;
1da177e4
LT		 9238}
9239
9240/* tp->lock is held. */
9241static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9242 dma_addr_t mapping, u32 maxlen_flags,
9243 u32 nic_addr)
9244{
9245 tg3_write_mem(tp,
9246 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9247 ((u64) mapping >> 32));
9248 tg3_write_mem(tp,
9249 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9250 ((u64) mapping & 0xffffffff));
9251 tg3_write_mem(tp,
9252 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9253 maxlen_flags);
9254
63c3a66f 9255 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 9256 tg3_write_mem(tp,
9257 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9258 nic_addr);
9259}
9260
a489b6d9
MC		 9261
9262static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 9263{
a489b6d9 9264 int i = 0;
b6080e12 9265
63c3a66f 9266 if (!tg3_flag(tp, ENABLE_TSS)) {
b6080e12
MC		 9267 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9268 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9269 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 9270 } else {
9271 tw32(HOSTCC_TXCOL_TICKS, 0);
9272 tw32(HOSTCC_TXMAX_FRAMES, 0);
9273 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
a489b6d9
MC		 9274
9275 for (; i < tp->txq_cnt; i++) {
9276 u32 reg;
9277
9278 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9279 tw32(reg, ec->tx_coalesce_usecs);
9280 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9281 tw32(reg, ec->tx_max_coalesced_frames);
9282 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9283 tw32(reg, ec->tx_max_coalesced_frames_irq);
9284 }
19cfaecc 9285 }
b6080e12 9286
a489b6d9
MC		 9287 for (; i < tp->irq_max - 1; i++) {
9288 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9289 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9290 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9291 }
9292}
9293
9294static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9295{
9296 int i = 0;
9297 u32 limit = tp->rxq_cnt;
9298
63c3a66f 9299 if (!tg3_flag(tp, ENABLE_RSS)) {
19cfaecc
MC		 9300 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9301 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9302 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
a489b6d9 9303 limit--;
19cfaecc 9304 } else {
b6080e12
MC		 9305 tw32(HOSTCC_RXCOL_TICKS, 0);
9306 tw32(HOSTCC_RXMAX_FRAMES, 0);
9307 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 9308 }
b6080e12 9309
a489b6d9 9310 for (; i < limit; i++) {
b6080e12
MC		 9311 u32 reg;
9312
9313 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9314 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 9315 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9316 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 9317 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9318 tw32(reg, ec->rx_max_coalesced_frames_irq);
b6080e12
MC		 9319 }
9320
9321 for (; i < tp->irq_max - 1; i++) {
9322 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 9323 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 9324 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
a489b6d9
MC		 9325 }
9326}
19cfaecc 9327
a489b6d9
MC		 9328static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9329{
9330 tg3_coal_tx_init(tp, ec);
9331 tg3_coal_rx_init(tp, ec);
9332
9333 if (!tg3_flag(tp, 5705_PLUS)) {
9334 u32 val = ec->stats_block_coalesce_usecs;
9335
9336 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9337 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9338
f4a46d1f 9339 if (!tp->link_up)
a489b6d9
MC		 9340 val = 0;
9341
9342 tw32(HOSTCC_STAT_COAL_TICKS, val);
b6080e12 9343 }
15f9850d 9344}
1da177e4 9345
328947ff
NS		 9346/* tp->lock is held. */
9347static void tg3_tx_rcbs_disable(struct tg3 *tp)
9348{
9349 u32 txrcb, limit;
9350
9351 /* Disable all transmit rings but the first. */
9352 if (!tg3_flag(tp, 5705_PLUS))
9353 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9354 else if (tg3_flag(tp, 5717_PLUS))
9355 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9356 else if (tg3_flag(tp, 57765_CLASS) ||
9357 tg3_asic_rev(tp) == ASIC_REV_5762)
9358 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9359 else
9360 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9361
9362 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9363 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9364 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9365 BDINFO_FLAGS_DISABLED);
9366}
9367
32ba19ef
NS		 9368/* tp->lock is held. */
9369static void tg3_tx_rcbs_init(struct tg3 *tp)
9370{
9371 int i = 0;
9372 u32 txrcb = NIC_SRAM_SEND_RCB;
9373
9374 if (tg3_flag(tp, ENABLE_TSS))
9375 i++;
9376
9377 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9378 struct tg3_napi *tnapi = &tp->napi[i];
9379
9380 if (!tnapi->tx_ring)
9381 continue;
9382
9383 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9384 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9385 NIC_SRAM_TX_BUFFER_DESC);
9386 }
9387}
9388
328947ff
NS		 9389/* tp->lock is held. */
9390static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9391{
9392 u32 rxrcb, limit;
9393
9394 /* Disable all receive return rings but the first. */
9395 if (tg3_flag(tp, 5717_PLUS))
9396 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9397 else if (!tg3_flag(tp, 5705_PLUS))
9398 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9399 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9400 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9401 tg3_flag(tp, 57765_CLASS))
9402 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9403 else
9404 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9405
9406 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9407 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9408 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9409 BDINFO_FLAGS_DISABLED);
9410}
9411
32ba19ef
NS		 9412/* tp->lock is held. */
9413static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9414{
9415 int i = 0;
9416 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9417
9418 if (tg3_flag(tp, ENABLE_RSS))
9419 i++;
9420
9421 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9422 struct tg3_napi *tnapi = &tp->napi[i];
9423
9424 if (!tnapi->rx_rcb)
9425 continue;
9426
9427 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9428 (tp->rx_ret_ring_mask + 1) <<
9429 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9430 }
9431}
9432
2d31ecaf
MC		 9433/* tp->lock is held. */
9434static void tg3_rings_reset(struct tg3 *tp)
9435{
9436 int i;
328947ff 9437 u32 stblk;
2d31ecaf
MC		 9438 struct tg3_napi *tnapi = &tp->napi[0];
9439
328947ff 9440 tg3_tx_rcbs_disable(tp);
2d31ecaf 9441
328947ff 9442 tg3_rx_ret_rcbs_disable(tp);
2d31ecaf
MC		 9443
9444 /* Disable interrupts */
9445 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
0e6cf6a9
MC		 9446 tp->napi[0].chk_msi_cnt = 0;
9447 tp->napi[0].last_rx_cons = 0;
9448 tp->napi[0].last_tx_cons = 0;
2d31ecaf
MC		 9449
9450 /* Zero mailbox registers. */
63c3a66f 9451 if (tg3_flag(tp, SUPPORT_MSIX)) {
6fd45cb8 9452 for (i = 1; i < tp->irq_max; i++) {
f77a6a8e
MC		 9453 tp->napi[i].tx_prod = 0;
9454 tp->napi[i].tx_cons = 0;
63c3a66f 9455 if (tg3_flag(tp, ENABLE_TSS))
c2353a32 9456 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 9457 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9458 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7f230735 9459 tp->napi[i].chk_msi_cnt = 0;
0e6cf6a9
MC		 9460 tp->napi[i].last_rx_cons = 0;
9461 tp->napi[i].last_tx_cons = 0;
f77a6a8e 9462 }
63c3a66f 9463 if (!tg3_flag(tp, ENABLE_TSS))
c2353a32 9464 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 9465 } else {
9466 tp->napi[0].tx_prod = 0;
9467 tp->napi[0].tx_cons = 0;
9468 tw32_mailbox(tp->napi[0].prodmbox, 0);
9469 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9470 }
2d31ecaf
MC		 9471
9472 /* Make sure the NIC-based send BD rings are disabled. */
63c3a66f 9473 if (!tg3_flag(tp, 5705_PLUS)) {
2d31ecaf
MC		 9474 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9475 for (i = 0; i < 16; i++)
9476 tw32_tx_mbox(mbox + i * 8, 0);
9477 }
9478
2d31ecaf
MC		 9479 /* Clear status block in ram. */
9480 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9481
9482 /* Set status block DMA address */
9483 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9484 ((u64) tnapi->status_mapping >> 32));
9485 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9486 ((u64) tnapi->status_mapping & 0xffffffff));
9487
f77a6a8e 9488 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 9489
f77a6a8e
MC		 9490 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9491 u64 mapping = (u64)tnapi->status_mapping;
9492 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9493 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
32ba19ef 9494 stblk += 8;
f77a6a8e
MC		 9495
9496 /* Clear status block in ram. */
9497 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
f77a6a8e 9498 }
32ba19ef
NS		 9499
9500 tg3_tx_rcbs_init(tp);
9501 tg3_rx_ret_rcbs_init(tp);
2d31ecaf
MC		 9502}
9503
eb07a940
MC		 9504static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9505{
9506 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9507
63c3a66f
JP		 9508 if (!tg3_flag(tp, 5750_PLUS) ||
9509 tg3_flag(tp, 5780_CLASS) ||
4153577a
JP		 9510 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9511 tg3_asic_rev(tp) == ASIC_REV_5752 ||
513aa6ea 9512 tg3_flag(tp, 57765_PLUS))
eb07a940 9513 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
4153577a
JP		 9514 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9515 tg3_asic_rev(tp) == ASIC_REV_5787)
eb07a940
MC		 9516 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9517 else
9518 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9519
9520 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9521 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9522
9523 val = min(nic_rep_thresh, host_rep_thresh);
9524 tw32(RCVBDI_STD_THRESH, val);
9525
63c3a66f 9526 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9527 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9528
63c3a66f 9529 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
eb07a940
MC		 9530 return;
9531
513aa6ea 9532 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
eb07a940
MC		 9533
9534 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9535
9536 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9537 tw32(RCVBDI_JUMBO_THRESH, val);
9538
63c3a66f 9539 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9540 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9541}
9542
ccd5ba9d
MC		 9543static inline u32 calc_crc(unsigned char *buf, int len)
9544{
9545 u32 reg;
9546 u32 tmp;
9547 int j, k;
9548
9549 reg = 0xffffffff;
9550
9551 for (j = 0; j < len; j++) {
9552 reg ^= buf[j];
9553
9554 for (k = 0; k < 8; k++) {
9555 tmp = reg & 0x01;
9556
9557 reg >>= 1;
9558
9559 if (tmp)
9560 reg ^= 0xedb88320;
9561 }
9562 }
9563
9564 return ~reg;
9565}
9566
9567static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9568{
9569 /* accept or reject all multicast frames */
9570 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9571 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9572 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9573 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9574}
9575
9576static void __tg3_set_rx_mode(struct net_device *dev)
9577{
9578 struct tg3 *tp = netdev_priv(dev);
9579 u32 rx_mode;
9580
9581 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9582 RX_MODE_KEEP_VLAN_TAG);
9583
9584#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9585 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9586 * flag clear.
9587 */
9588 if (!tg3_flag(tp, ENABLE_ASF))
9589 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9590#endif
9591
9592 if (dev->flags & IFF_PROMISC) {
9593 /* Promiscuous mode. */
9594 rx_mode |= RX_MODE_PROMISC;
9595 } else if (dev->flags & IFF_ALLMULTI) {
9596 /* Accept all multicast. */
9597 tg3_set_multi(tp, 1);
9598 } else if (netdev_mc_empty(dev)) {
9599 /* Reject all multicast. */
9600 tg3_set_multi(tp, 0);
9601 } else {
9602 /* Accept one or more multicast(s). */
9603 struct netdev_hw_addr *ha;
9604 u32 mc_filter[4] = { 0, };
9605 u32 regidx;
9606 u32 bit;
9607 u32 crc;
9608
9609 netdev_for_each_mc_addr(ha, dev) {
9610 crc = calc_crc(ha->addr, ETH_ALEN);
9611 bit = ~crc & 0x7f;
9612 regidx = (bit & 0x60) >> 5;
9613 bit &= 0x1f;
9614 mc_filter[regidx] |= (1 << bit);
9615 }
9616
9617 tw32(MAC_HASH_REG_0, mc_filter[0]);
9618 tw32(MAC_HASH_REG_1, mc_filter[1]);
9619 tw32(MAC_HASH_REG_2, mc_filter[2]);
9620 tw32(MAC_HASH_REG_3, mc_filter[3]);
9621 }
9622
9623 if (rx_mode != tp->rx_mode) {
9624 tp->rx_mode = rx_mode;
9625 tw32_f(MAC_RX_MODE, rx_mode);
9626 udelay(10);
9627 }
9628}
9629
9102426a 9630static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
90415477
MC		 9631{
9632 int i;
9633
9634 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9102426a 9635 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
90415477
MC		 9636}
9637
9638static void tg3_rss_check_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9639{
9640 int i;
9641
9642 if (!tg3_flag(tp, SUPPORT_MSIX))
9643 return;
9644
0b3ba055 9645 if (tp->rxq_cnt == 1) {
bcebcc46 9646 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
90415477
MC		 9647 return;
9648 }
9649
9650 /* Validate table against current IRQ count */
9651 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
0b3ba055 9652 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
90415477
MC		 9653 break;
9654 }
9655
9656 if (i != TG3_RSS_INDIR_TBL_SIZE)
9102426a 9657 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
bcebcc46
MC		 9658}
9659
90415477 9660static void tg3_rss_write_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9661{
9662 int i = 0;
9663 u32 reg = MAC_RSS_INDIR_TBL_0;
9664
9665 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9666 u32 val = tp->rss_ind_tbl[i];
9667 i++;
9668 for (; i % 8; i++) {
9669 val <<= 4;
9670 val |= tp->rss_ind_tbl[i];
9671 }
9672 tw32(reg, val);
9673 reg += 4;
9674 }
9675}
9676
9bc297ea
NS		 9677static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9678{
9679 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9680 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9681 else
9682 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9683}
9684
1da177e4 9685/* tp->lock is held. */
953c96e0 9686static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
1da177e4
LT		 9687{
9688 u32 val, rdmac_mode;
9689 int i, err, limit;
8fea32b9 9690 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
1da177e4
LT		 9691
9692 tg3_disable_ints(tp);
9693
9694 tg3_stop_fw(tp);
9695
9696 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9697
63c3a66f 9698 if (tg3_flag(tp, INIT_COMPLETE))
e6de8ad1 9699 tg3_abort_hw(tp, 1);
1da177e4 9700
fdad8de4
NS		 9701 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9702 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9703 tg3_phy_pull_config(tp);
400dfbaa 9704 tg3_eee_pull_config(tp, NULL);
fdad8de4
NS		 9705 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9706 }
9707
400dfbaa
NS		 9708 /* Enable MAC control of LPI */
9709 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9710 tg3_setup_eee(tp);
9711
603f1173 9712 if (reset_phy)
d4d2c558
MC		 9713 tg3_phy_reset(tp);
9714
1da177e4
LT		 9715 err = tg3_chip_reset(tp);
9716 if (err)
9717 return err;
9718
9719 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9720
4153577a 9721 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
d30cdd28
MC		 9722 val = tr32(TG3_CPMU_CTRL);
9723 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9724 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 9725
9726 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9727 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9728 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9729 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9730
9731 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9732 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9733 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9734 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9735
9736 val = tr32(TG3_CPMU_HST_ACC);
9737 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9738 val |= CPMU_HST_ACC_MACCLK_6_25;
9739 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 9740 }
9741
4153577a 9742 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
33466d93
MC		 9743 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9744 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9745 PCIE_PWR_MGMT_L1_THRESH_4MS;
9746 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 9747
9748 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9749 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9750
9751 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 9752
f40386c8
MC		 9753 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9754 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 9755 }
9756
63c3a66f 9757 if (tg3_flag(tp, L1PLLPD_EN)) {
614b0590
MC		 9758 u32 grc_mode = tr32(GRC_MODE);
9759
9760 /* Access the lower 1K of PL PCIE block registers. */
9761 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9762 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9763
9764 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9765 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9766 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9767
9768 tw32(GRC_MODE, grc_mode);
9769 }
9770
55086ad9 9771 if (tg3_flag(tp, 57765_CLASS)) {
4153577a 9772 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
5093eedc 9773 u32 grc_mode = tr32(GRC_MODE);
cea46462 9774
5093eedc
MC		 9775 /* Access the lower 1K of PL PCIE block registers. */
9776 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9777 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
cea46462 9778
5093eedc
MC		 9779 val = tr32(TG3_PCIE_TLDLPL_PORT +
9780 TG3_PCIE_PL_LO_PHYCTL5);
9781 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9782 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
cea46462 9783
5093eedc
MC		 9784 tw32(GRC_MODE, grc_mode);
9785 }
a977dbe8 9786
4153577a 9787 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
d3f677af
MC		 9788 u32 grc_mode;
9789
9790 /* Fix transmit hangs */
9791 val = tr32(TG3_CPMU_PADRNG_CTL);
9792 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9793 tw32(TG3_CPMU_PADRNG_CTL, val);
9794
9795 grc_mode = tr32(GRC_MODE);
1ff30a59
MC		 9796
9797 /* Access the lower 1K of DL PCIE block registers. */
9798 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9799 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9800
9801 val = tr32(TG3_PCIE_TLDLPL_PORT +
9802 TG3_PCIE_DL_LO_FTSMAX);
9803 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9804 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9805 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9806
9807 tw32(GRC_MODE, grc_mode);
9808 }
9809
a977dbe8
MC		 9810 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9811 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9812 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9813 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
cea46462
MC		 9814 }
9815
1da177e4
LT		 9816 /* This works around an issue with Athlon chipsets on
9817 * B3 tigon3 silicon. This bit has no effect on any
9818 * other revision. But do not set this on PCI Express
795d01c5 9819 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 9820 */
63c3a66f
JP		 9821 if (!tg3_flag(tp, CPMU_PRESENT)) {
9822 if (!tg3_flag(tp, PCI_EXPRESS))
795d01c5
MC		 9823 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9824 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9825 }
1da177e4 9826
4153577a 9827 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 9828 tg3_flag(tp, PCIX_MODE)) {
1da177e4
LT		 9829 val = tr32(TG3PCI_PCISTATE);
9830 val |= PCISTATE_RETRY_SAME_DMA;
9831 tw32(TG3PCI_PCISTATE, val);
9832 }
9833
63c3a66f 9834 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 9835 /* Allow reads and writes to the
9836 * APE register and memory space.
9837 */
9838 val = tr32(TG3PCI_PCISTATE);
9839 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 9840 PCISTATE_ALLOW_APE_SHMEM_WR |
9841 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 9842 tw32(TG3PCI_PCISTATE, val);
9843 }
9844
4153577a 9845 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
1da177e4
LT		 9846 /* Enable some hw fixes. */
9847 val = tr32(TG3PCI_MSI_DATA);
9848 val |= (1 << 26) | (1 << 28) | (1 << 29);
9849 tw32(TG3PCI_MSI_DATA, val);
9850 }
9851
9852 /* Descriptor ring init may make accesses to the
9853 * NIC SRAM area to setup the TX descriptors, so we
9854 * can only do this after the hardware has been
9855 * successfully reset.
9856 */
32d8c572
MC		 9857 err = tg3_init_rings(tp);
9858 if (err)
9859 return err;
1da177e4 9860
63c3a66f 9861 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 9862 val = tr32(TG3PCI_DMA_RW_CTRL) &
9863 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
4153577a 9864 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
1a319025 9865 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
55086ad9 9866 if (!tg3_flag(tp, 57765_CLASS) &&
4153577a
JP		 9867 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9868 tg3_asic_rev(tp) != ASIC_REV_5762)
0aebff48 9869 val |= DMA_RWCTRL_TAGGED_STAT_WA;
cbf9ca6c 9870 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
4153577a
JP		 9871 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9872 tg3_asic_rev(tp) != ASIC_REV_5761) {
d30cdd28
MC		 9873 /* This value is determined during the probe time DMA
9874 * engine test, tg3_test_dma.
9875 */
9876 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9877 }
1da177e4
LT		 9878
9879 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
9880 GRC_MODE_4X_NIC_SEND_RINGS |
9881 GRC_MODE_NO_TX_PHDR_CSUM |
9882 GRC_MODE_NO_RX_PHDR_CSUM);
9883 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 9884
9885 /* Pseudo-header checksum is done by hardware logic and not
9886 * the offload processers, so make the chip do the pseudo-
9887 * header checksums on receive. For transmit it is more
9888 * convenient to do the pseudo-header checksum in software
9889 * as Linux does that on transmit for us in all cases.
9890 */
9891 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4 9892
fb4ce8ad
MC		 9893 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
9894 if (tp->rxptpctl)
9895 tw32(TG3_RX_PTP_CTL,
9896 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
9897
9898 if (tg3_flag(tp, PTP_CAPABLE))
9899 val |= GRC_MODE_TIME_SYNC_ENABLE;
9900
9901 tw32(GRC_MODE, tp->grc_mode | val);
1da177e4
LT		 9902
9903 /* Setup the timer prescalar register. Clock is always 66Mhz. */
9904 val = tr32(GRC_MISC_CFG);
9905 val &= ~0xff;
9906 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
9907 tw32(GRC_MISC_CFG, val);
9908
9909 /* Initialize MBUF/DESC pool. */
63c3a66f 9910 if (tg3_flag(tp, 5750_PLUS)) {
1da177e4 9911 /* Do nothing. */
4153577a 9912 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
1da177e4 9913 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
4153577a 9914 if (tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 9915 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
9916 else
9917 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
9918 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
9919 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
63c3a66f 9920 } else if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 9921 int fw_len;
9922
077f849d 9923 fw_len = tp->fw_len;
1da177e4
LT		 9924 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
9925 tw32(BUFMGR_MB_POOL_ADDR,
9926 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
9927 tw32(BUFMGR_MB_POOL_SIZE,
9928 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
9929 }
1da177e4 9930
0f893dc6 9931 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 9932 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9933 tp->bufmgr_config.mbuf_read_dma_low_water);
9934 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9935 tp->bufmgr_config.mbuf_mac_rx_low_water);
9936 tw32(BUFMGR_MB_HIGH_WATER,
9937 tp->bufmgr_config.mbuf_high_water);
9938 } else {
9939 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9940 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
9941 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9942 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
9943 tw32(BUFMGR_MB_HIGH_WATER,
9944 tp->bufmgr_config.mbuf_high_water_jumbo);
9945 }
9946 tw32(BUFMGR_DMA_LOW_WATER,
9947 tp->bufmgr_config.dma_low_water);
9948 tw32(BUFMGR_DMA_HIGH_WATER,
9949 tp->bufmgr_config.dma_high_water);
9950
d309a46e 9951 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
4153577a 9952 if (tg3_asic_rev(tp) == ASIC_REV_5719)
d309a46e 9953 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
4153577a
JP		 9954 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
9955 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
9956 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
4d958473 9957 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
d309a46e 9958 tw32(BUFMGR_MODE, val);
1da177e4
LT		 9959 for (i = 0; i < 2000; i++) {
9960 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
9961 break;
9962 udelay(10);
9963 }
9964 if (i >= 2000) {
05dbe005 9965 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 9966 return -ENODEV;
9967 }
9968
4153577a 9969 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
eb07a940 9970 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
b5d3772c 9971
eb07a940 9972 tg3_setup_rxbd_thresholds(tp);
1da177e4
LT		 9973
9974 /* Initialize TG3_BDINFO's at:
9975 * RCVDBDI_STD_BD: standard eth size rx ring
9976 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
9977 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
9978 *
9979 * like so:
9980 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
9981 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
9982 * ring attribute flags
9983 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
9984 *
9985 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
9986 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
9987 *
9988 * The size of each ring is fixed in the firmware, but the location is
9989 * configurable.
9990 */
9991 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 9992 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 9993 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 9994 ((u64) tpr->rx_std_mapping & 0xffffffff));
63c3a66f 9995 if (!tg3_flag(tp, 5717_PLUS))
87668d35
MC		 9996 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
9997 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 9998
fdb72b38 9999 /* Disable the mini ring */
63c3a66f 10000 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10001 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10002 BDINFO_FLAGS_DISABLED);
10003
fdb72b38
MC		 10004 /* Program the jumbo buffer descriptor ring control
10005 * blocks on those devices that have them.
10006 */
4153577a 10007 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
63c3a66f 10008 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
1da177e4 10009
63c3a66f 10010 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
1da177e4 10011 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10012 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 10013 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10014 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
de9f5230
MC		 10015 val = TG3_RX_JMB_RING_SIZE(tp) <<
10016 BDINFO_FLAGS_MAXLEN_SHIFT;
1da177e4 10017 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
de9f5230 10018 val | BDINFO_FLAGS_USE_EXT_RECV);
63c3a66f 10019 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
c65a17f4 10020 tg3_flag(tp, 57765_CLASS) ||
4153577a 10021 tg3_asic_rev(tp) == ASIC_REV_5762)
87668d35
MC		 10022 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10023 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 10024 } else {
10025 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10026 BDINFO_FLAGS_DISABLED);
10027 }
10028
63c3a66f 10029 if (tg3_flag(tp, 57765_PLUS)) {
fa6b2aae 10030 val = TG3_RX_STD_RING_SIZE(tp);
7cb32cf2
MC		 10031 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10032 val |= (TG3_RX_STD_DMA_SZ << 2);
10033 } else
04380d40 10034 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38 10035 } else
de9f5230 10036 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 10037
10038 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 10039
411da640 10040 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 10041 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 10042
63c3a66f
JP		 10043 tpr->rx_jmb_prod_idx =
10044 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
66711e66 10045 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 10046
2d31ecaf
MC		 10047 tg3_rings_reset(tp);
10048
1da177e4 10049 /* Initialize MAC address and backoff seed. */
953c96e0 10050 __tg3_set_mac_addr(tp, false);
1da177e4
LT		 10051
10052 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 10053 tw32(MAC_RX_MTU_SIZE,
10054 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 10055
10056 /* The slot time is changed by tg3_setup_phy if we
10057 * run at gigabit with half duplex.
10058 */
f2096f94
MC		 10059 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10060 (6 << TX_LENGTHS_IPG_SHIFT) |
10061 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10062
4153577a
JP		 10063 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10064 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10065 val |= tr32(MAC_TX_LENGTHS) &
10066 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10067 TX_LENGTHS_CNT_DWN_VAL_MSK);
10068
10069 tw32(MAC_TX_LENGTHS, val);
1da177e4
LT		 10070
10071 /* Receive rules. */
10072 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10073 tw32(RCVLPC_CONFIG, 0x0181);
10074
10075 /* Calculate RDMAC_MODE setting early, we need it to determine
10076 * the RCVLPC_STATE_ENABLE mask.
10077 */
10078 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10079 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10080 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10081 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10082 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 10083
4153577a 10084 if (tg3_asic_rev(tp) == ASIC_REV_5717)
0339e4e3
MC		 10085 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10086
4153577a
JP		 10087 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10088 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10089 tg3_asic_rev(tp) == ASIC_REV_57780)
d30cdd28
MC		 10090 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10091 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10092 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10093
4153577a
JP		 10094 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10095 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10096 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a 10097 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 10098 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10099 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10100 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10101 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10102 }
10103 }
10104
63c3a66f 10105 if (tg3_flag(tp, PCI_EXPRESS))
85e94ced
MC		 10106 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10107
4153577a 10108 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
d3f677af
MC		 10109 tp->dma_limit = 0;
10110 if (tp->dev->mtu <= ETH_DATA_LEN) {
10111 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10112 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10113 }
10114 }
10115
63c3a66f
JP		 10116 if (tg3_flag(tp, HW_TSO_1) ||
10117 tg3_flag(tp, HW_TSO_2) ||
10118 tg3_flag(tp, HW_TSO_3))
027455ad
MC		 10119 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10120
108a6c16 10121 if (tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 10122 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10123 tg3_asic_rev(tp) == ASIC_REV_57780)
027455ad 10124 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4 10125
4153577a
JP		 10126 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10127 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10128 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10129
4153577a
JP		 10130 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10131 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10132 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10133 tg3_asic_rev(tp) == ASIC_REV_57780 ||
63c3a66f 10134 tg3_flag(tp, 57765_PLUS)) {
c65a17f4
MC		 10135 u32 tgtreg;
10136
4153577a 10137 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10138 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10139 else
10140 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10141
10142 val = tr32(tgtreg);
4153577a
JP		 10143 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10144 tg3_asic_rev(tp) == ASIC_REV_5762) {
b4495ed8
MC		 10145 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10146 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10147 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10148 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10149 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10150 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
b75cc0e4 10151 }
c65a17f4 10152 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
41a8a7ee
MC		 10153 }
10154
4153577a
JP		 10155 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10156 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10157 tg3_asic_rev(tp) == ASIC_REV_5762) {
c65a17f4
MC		 10158 u32 tgtreg;
10159
4153577a 10160 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10161 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10162 else
10163 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10164
10165 val = tr32(tgtreg);
10166 tw32(tgtreg, val |
d309a46e
MC		 10167 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10168 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10169 }
10170
1da177e4 10171 /* Receive/send statistics. */
63c3a66f 10172 if (tg3_flag(tp, 5750_PLUS)) {
1661394e
MC		 10173 val = tr32(RCVLPC_STATS_ENABLE);
10174 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10175 tw32(RCVLPC_STATS_ENABLE, val);
10176 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
63c3a66f 10177 tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10178 val = tr32(RCVLPC_STATS_ENABLE);
10179 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10180 tw32(RCVLPC_STATS_ENABLE, val);
10181 } else {
10182 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10183 }
10184 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10185 tw32(SNDDATAI_STATSENAB, 0xffffff);
10186 tw32(SNDDATAI_STATSCTRL,
10187 (SNDDATAI_SCTRL_ENABLE |
10188 SNDDATAI_SCTRL_FASTUPD));
10189
10190 /* Setup host coalescing engine. */
10191 tw32(HOSTCC_MODE, 0);
10192 for (i = 0; i < 2000; i++) {
10193 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10194 break;
10195 udelay(10);
10196 }
10197
d244c892 10198 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 10199
63c3a66f 10200 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10201 /* Status/statistics block address. See tg3_timer,
10202 * the tg3_periodic_fetch_stats call there, and
10203 * tg3_get_stats to see how this works for 5705/5750 chips.
10204 */
1da177e4
LT		 10205 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10206 ((u64) tp->stats_mapping >> 32));
10207 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10208 ((u64) tp->stats_mapping & 0xffffffff));
10209 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 10210
1da177e4 10211 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 10212
10213 /* Clear statistics and status block memory areas */
10214 for (i = NIC_SRAM_STATS_BLK;
10215 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10216 i += sizeof(u32)) {
10217 tg3_write_mem(tp, i, 0);
10218 udelay(40);
10219 }
1da177e4
LT		 10220 }
10221
10222 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10223
10224 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10225 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
63c3a66f 10226 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10227 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10228
f07e9af3
MC		 10229 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10230 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c94e3941
MC		 10231 /* reset to prevent losing 1st rx packet intermittently */
10232 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10233 udelay(10);
10234 }
10235
3bda1258 10236 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9e975cc2
MC		 10237 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10238 MAC_MODE_FHDE_ENABLE;
10239 if (tg3_flag(tp, ENABLE_APE))
10240 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
63c3a66f 10241 if (!tg3_flag(tp, 5705_PLUS) &&
f07e9af3 10242 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a 10243 tg3_asic_rev(tp) != ASIC_REV_5700)
e8f3f6ca 10244 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 10245 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10246 udelay(40);
10247
314fba34 10248 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
63c3a66f 10249 * If TG3_FLAG_IS_NIC is zero, we should read the
314fba34
MC		 10250 * register to preserve the GPIO settings for LOMs. The GPIOs,
10251 * whether used as inputs or outputs, are set by boot code after
10252 * reset.
10253 */
63c3a66f 10254 if (!tg3_flag(tp, IS_NIC)) {
314fba34
MC		 10255 u32 gpio_mask;
10256
9d26e213
MC		 10257 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10258 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10259 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc 10260
4153577a 10261 if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc
MC		 10262 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10263 GRC_LCLCTRL_GPIO_OUTPUT3;
10264
4153577a 10265 if (tg3_asic_rev(tp) == ASIC_REV_5755)
af36e6b6
MC		 10266 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10267
aaf84465 10268 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 10269 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10270
10271 /* GPIO1 must be driven high for eeprom write protect */
63c3a66f 10272 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9d26e213
MC		 10273 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10274 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 10275 }
1da177e4
LT		 10276 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10277 udelay(100);
10278
c3b5003b 10279 if (tg3_flag(tp, USING_MSIX)) {
baf8a94a 10280 val = tr32(MSGINT_MODE);
c3b5003b
MC		 10281 val |= MSGINT_MODE_ENABLE;
10282 if (tp->irq_cnt > 1)
10283 val |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 10284 if (!tg3_flag(tp, 1SHOT_MSI))
10285 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
baf8a94a
MC		 10286 tw32(MSGINT_MODE, val);
10287 }
10288
63c3a66f 10289 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10290 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10291 udelay(40);
10292 }
10293
10294 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10295 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10296 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10297 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10298 WDMAC_MODE_LNGREAD_ENAB);
10299
4153577a
JP		 10300 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10301 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10302 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a
JP		 10303 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10304 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
1da177e4
LT		 10305 /* nothing */
10306 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10307 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10308 val |= WDMAC_MODE_RX_ACCEL;
10309 }
10310 }
10311
d9ab5ad1 10312 /* Enable host coalescing bug fix */
63c3a66f 10313 if (tg3_flag(tp, 5755_PLUS))
f51f3562 10314 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 10315
4153577a 10316 if (tg3_asic_rev(tp) == ASIC_REV_5785)
788a035e
MC		 10317 val |= WDMAC_MODE_BURST_ALL_DATA;
10318
1da177e4
LT		 10319 tw32_f(WDMAC_MODE, val);
10320 udelay(40);
10321
63c3a66f 10322 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 10323 u16 pcix_cmd;
10324
10325 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10326 &pcix_cmd);
4153577a 10327 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
9974a356
MC		 10328 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10329 pcix_cmd |= PCI_X_CMD_READ_2K;
4153577a 10330 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
9974a356
MC		 10331 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10332 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 10333 }
9974a356
MC		 10334 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10335 pcix_cmd);
1da177e4
LT		 10336 }
10337
10338 tw32_f(RDMAC_MODE, rdmac_mode);
10339 udelay(40);
10340
9bc297ea
NS		 10341 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10342 tg3_asic_rev(tp) == ASIC_REV_5720) {
091f0ea3
MC		 10343 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10344 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10345 break;
10346 }
10347 if (i < TG3_NUM_RDMA_CHANNELS) {
10348 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10349 val |= tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10350 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10351 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
091f0ea3
MC		 10352 }
10353 }
10354
1da177e4 10355 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
63c3a66f 10356 if (!tg3_flag(tp, 5705_PLUS))
1da177e4 10357 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6 10358
4153577a 10359 if (tg3_asic_rev(tp) == ASIC_REV_5761)
9936bcf6
MC		 10360 tw32(SNDDATAC_MODE,
10361 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10362 else
10363 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10364
1da177e4
LT		 10365 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10366 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7cb32cf2 10367 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
63c3a66f 10368 if (tg3_flag(tp, LRG_PROD_RING_CAP))
7cb32cf2
MC		 10369 val |= RCVDBDI_MODE_LRG_RING_SZ;
10370 tw32(RCVDBDI_MODE, val);
1da177e4 10371 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
63c3a66f
JP		 10372 if (tg3_flag(tp, HW_TSO_1) ||
10373 tg3_flag(tp, HW_TSO_2) ||
10374 tg3_flag(tp, HW_TSO_3))
1da177e4 10375 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 10376 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
63c3a66f 10377 if (tg3_flag(tp, ENABLE_TSS))
baf8a94a
MC		 10378 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10379 tw32(SNDBDI_MODE, val);
1da177e4
LT		 10380 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10381
4153577a 10382 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
1da177e4
LT		 10383 err = tg3_load_5701_a0_firmware_fix(tp);
10384 if (err)
10385 return err;
10386 }
10387
c4dab506
NS		 10388 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10389 /* Ignore any errors for the firmware download. If download
10390 * fails, the device will operate with EEE disabled
10391 */
10392 tg3_load_57766_firmware(tp);
10393 }
10394
63c3a66f 10395 if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10396 err = tg3_load_tso_firmware(tp);
10397 if (err)
10398 return err;
10399 }
1da177e4
LT		 10400
10401 tp->tx_mode = TX_MODE_ENABLE;
f2096f94 10402
63c3a66f 10403 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 10404 tg3_asic_rev(tp) == ASIC_REV_5906)
b1d05210 10405 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
f2096f94 10406
4153577a
JP		 10407 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10408 tg3_asic_rev(tp) == ASIC_REV_5762) {
f2096f94
MC		 10409 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10410 tp->tx_mode &= ~val;
10411 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10412 }
10413
1da177e4
LT		 10414 tw32_f(MAC_TX_MODE, tp->tx_mode);
10415 udelay(100);
10416
63c3a66f 10417 if (tg3_flag(tp, ENABLE_RSS)) {
bcebcc46 10418 tg3_rss_write_indir_tbl(tp);
baf8a94a
MC		 10419
10420 /* Setup the "secret" hash key. */
10421 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10422 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10423 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10424 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10425 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10426 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10427 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10428 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10429 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10430 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10431 }
10432
1da177e4 10433 tp->rx_mode = RX_MODE_ENABLE;
63c3a66f 10434 if (tg3_flag(tp, 5755_PLUS))
af36e6b6
MC		 10435 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10436
378b72c8
NS		 10437 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10438 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10439
63c3a66f 10440 if (tg3_flag(tp, ENABLE_RSS))
baf8a94a
MC		 10441 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10442 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10443 RX_MODE_RSS_IPV6_HASH_EN |
10444 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10445 RX_MODE_RSS_IPV4_HASH_EN |
10446 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10447
1da177e4
LT		 10448 tw32_f(MAC_RX_MODE, tp->rx_mode);
10449 udelay(10);
10450
1da177e4
LT		 10451 tw32(MAC_LED_CTRL, tp->led_ctrl);
10452
10453 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
f07e9af3 10454 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
1da177e4
LT		 10455 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10456 udelay(10);
10457 }
10458 tw32_f(MAC_RX_MODE, tp->rx_mode);
10459 udelay(10);
10460
f07e9af3 10461 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a
JP		 10462 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10463 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
1da177e4
LT		 10464 /* Set drive transmission level to 1.2V */
10465 /* only if the signal pre-emphasis bit is not set */
10466 val = tr32(MAC_SERDES_CFG);
10467 val &= 0xfffff000;
10468 val |= 0x880;
10469 tw32(MAC_SERDES_CFG, val);
10470 }
4153577a 10471 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
1da177e4
LT		 10472 tw32(MAC_SERDES_CFG, 0x616000);
10473 }
10474
10475 /* Prevent chip from dropping frames when flow control
10476 * is enabled.
10477 */
55086ad9 10478 if (tg3_flag(tp, 57765_CLASS))
666bc831
MC		 10479 val = 1;
10480 else
10481 val = 2;
10482 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4 10483
4153577a 10484 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
f07e9af3 10485 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
1da177e4 10486 /* Use hardware link auto-negotiation */
63c3a66f 10487 tg3_flag_set(tp, HW_AUTONEG);
1da177e4
LT		 10488 }
10489
f07e9af3 10490 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
4153577a 10491 tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 10492 u32 tmp;
10493
10494 tmp = tr32(SERDES_RX_CTRL);
10495 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10496 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10497 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10498 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10499 }
10500
63c3a66f 10501 if (!tg3_flag(tp, USE_PHYLIB)) {
c6700ce2 10502 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
80096068 10503 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1da177e4 10504
953c96e0 10505 err = tg3_setup_phy(tp, false);
dd477003
MC		 10506 if (err)
10507 return err;
1da177e4 10508
f07e9af3
MC		 10509 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10510 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
dd477003
MC		 10511 u32 tmp;
10512
10513 /* Clear CRC stats. */
10514 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10515 tg3_writephy(tp, MII_TG3_TEST1,
10516 tmp | MII_TG3_TEST1_CRC_EN);
f08aa1a8 10517 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
dd477003 10518 }
1da177e4
LT		 10519 }
10520 }
10521
10522 __tg3_set_rx_mode(tp->dev);
10523
10524 /* Initialize receive rules. */
10525 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10526 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10527 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10528 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10529
63c3a66f 10530 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
1da177e4
LT		 10531 limit = 8;
10532 else
10533 limit = 16;
63c3a66f 10534 if (tg3_flag(tp, ENABLE_ASF))
1da177e4
LT		 10535 limit -= 4;
10536 switch (limit) {
10537 case 16:
10538 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10539 case 15:
10540 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10541 case 14:
10542 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10543 case 13:
10544 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10545 case 12:
10546 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10547 case 11:
10548 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10549 case 10:
10550 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10551 case 9:
10552 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10553 case 8:
10554 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10555 case 7:
10556 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10557 case 6:
10558 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10559 case 5:
10560 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10561 case 4:
10562 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10563 case 3:
10564 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10565 case 2:
10566 case 1:
10567
10568 default:
10569 break;
855e1111 10570 }
1da177e4 10571
63c3a66f 10572 if (tg3_flag(tp, ENABLE_APE))
9ce768ea
MC		 10573 /* Write our heartbeat update interval to APE. */
10574 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10575 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 10576
1da177e4
LT		 10577 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10578
1da177e4
LT		 10579 return 0;
10580}
10581
10582/* Called at device open time to get the chip ready for
10583 * packet processing. Invoked with tp->lock held.
10584 */
953c96e0 10585static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
1da177e4 10586{
df465abf
NS		 10587 /* Chip may have been just powered on. If so, the boot code may still
10588 * be running initialization. Wait for it to finish to avoid races in
10589 * accessing the hardware.
10590 */
10591 tg3_enable_register_access(tp);
10592 tg3_poll_fw(tp);
10593
1da177e4
LT		 10594 tg3_switch_clocks(tp);
10595
10596 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10597
2f751b67 10598 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 10599}
10600
aed93e0b
MC		 10601static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10602{
10603 int i;
10604
10605 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10606 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10607
10608 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10609 off += len;
10610
10611 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10612 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10613 memset(ocir, 0, TG3_OCIR_LEN);
10614 }
10615}
10616
10617/* sysfs attributes for hwmon */
10618static ssize_t tg3_show_temp(struct device *dev,
10619 struct device_attribute *devattr, char *buf)
10620{
10621 struct pci_dev *pdev = to_pci_dev(dev);
10622 struct net_device *netdev = pci_get_drvdata(pdev);
10623 struct tg3 *tp = netdev_priv(netdev);
10624 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10625 u32 temperature;
10626
10627 spin_lock_bh(&tp->lock);
10628 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10629 sizeof(temperature));
10630 spin_unlock_bh(&tp->lock);
10631 return sprintf(buf, "%u\n", temperature);
10632}
10633
10634
10635static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10636 TG3_TEMP_SENSOR_OFFSET);
10637static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10638 TG3_TEMP_CAUTION_OFFSET);
10639static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10640 TG3_TEMP_MAX_OFFSET);
10641
10642static struct attribute *tg3_attributes[] = {
10643 &sensor_dev_attr_temp1_input.dev_attr.attr,
10644 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10645 &sensor_dev_attr_temp1_max.dev_attr.attr,
10646 NULL
10647};
10648
10649static const struct attribute_group tg3_group = {
10650 .attrs = tg3_attributes,
10651};
10652
aed93e0b
MC		 10653static void tg3_hwmon_close(struct tg3 *tp)
10654{
aed93e0b
MC		 10655 if (tp->hwmon_dev) {
10656 hwmon_device_unregister(tp->hwmon_dev);
10657 tp->hwmon_dev = NULL;
10658 sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group);
10659 }
aed93e0b
MC		 10660}
10661
10662static void tg3_hwmon_open(struct tg3 *tp)
10663{
aed93e0b
MC		 10664 int i, err;
10665 u32 size = 0;
10666 struct pci_dev *pdev = tp->pdev;
10667 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10668
10669 tg3_sd_scan_scratchpad(tp, ocirs);
10670
10671 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10672 if (!ocirs[i].src_data_length)
10673 continue;
10674
10675 size += ocirs[i].src_hdr_length;
10676 size += ocirs[i].src_data_length;
10677 }
10678
10679 if (!size)
10680 return;
10681
10682 /* Register hwmon sysfs hooks */
10683 err = sysfs_create_group(&pdev->dev.kobj, &tg3_group);
10684 if (err) {
10685 dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n");
10686 return;
10687 }
10688
10689 tp->hwmon_dev = hwmon_device_register(&pdev->dev);
10690 if (IS_ERR(tp->hwmon_dev)) {
10691 tp->hwmon_dev = NULL;
10692 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10693 sysfs_remove_group(&pdev->dev.kobj, &tg3_group);
10694 }
aed93e0b
MC		 10695}
10696
10697
1da177e4
LT		 10698#define TG3_STAT_ADD32(PSTAT, REG) \
10699do { u32 __val = tr32(REG); \
10700 (PSTAT)->low += __val; \
10701 if ((PSTAT)->low < __val) \
10702 (PSTAT)->high += 1; \
10703} while (0)
10704
10705static void tg3_periodic_fetch_stats(struct tg3 *tp)
10706{
10707 struct tg3_hw_stats *sp = tp->hw_stats;
10708
f4a46d1f 10709 if (!tp->link_up)
1da177e4
LT		 10710 return;
10711
10712 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10713 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10714 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10715 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10716 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10717 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10718 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10719 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10720 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10721 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10722 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10723 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10724 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9bc297ea 10725 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
091f0ea3
MC		 10726 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10727 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10728 u32 val;
10729
10730 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10731 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10732 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10733 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
091f0ea3 10734 }
1da177e4
LT		 10735
10736 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10737 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10738 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10739 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10740 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10741 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10742 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10743 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10744 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10745 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10746 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10747 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10748 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10749 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 10750
10751 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
4153577a
JP		 10752 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10753 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10754 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
4d958473
MC		 10755 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10756 } else {
10757 u32 val = tr32(HOSTCC_FLOW_ATTN);
10758 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10759 if (val) {
10760 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10761 sp->rx_discards.low += val;
10762 if (sp->rx_discards.low < val)
10763 sp->rx_discards.high += 1;
10764 }
10765 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10766 }
463d305b 10767 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 10768}
10769
0e6cf6a9
MC		 10770static void tg3_chk_missed_msi(struct tg3 *tp)
10771{
10772 u32 i;
10773
10774 for (i = 0; i < tp->irq_cnt; i++) {
10775 struct tg3_napi *tnapi = &tp->napi[i];
10776
10777 if (tg3_has_work(tnapi)) {
10778 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10779 tnapi->last_tx_cons == tnapi->tx_cons) {
10780 if (tnapi->chk_msi_cnt < 1) {
10781 tnapi->chk_msi_cnt++;
10782 return;
10783 }
7f230735 10784 tg3_msi(0, tnapi);
0e6cf6a9
MC		 10785 }
10786 }
10787 tnapi->chk_msi_cnt = 0;
10788 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10789 tnapi->last_tx_cons = tnapi->tx_cons;
10790 }
10791}
10792
1da177e4
LT		 10793static void tg3_timer(unsigned long __opaque)
10794{
10795 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 10796
5b190624 10797 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
f475f163
MC		 10798 goto restart_timer;
10799
f47c11ee 10800 spin_lock(&tp->lock);
1da177e4 10801
4153577a 10802 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
55086ad9 10803 tg3_flag(tp, 57765_CLASS))
0e6cf6a9
MC		 10804 tg3_chk_missed_msi(tp);
10805
7e6c63f0
HM		 10806 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10807 /* BCM4785: Flush posted writes from GbE to host memory. */
10808 tr32(HOSTCC_MODE);
10809 }
10810
63c3a66f 10811 if (!tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 10812 /* All of this garbage is because when using non-tagged
10813 * IRQ status the mailbox/status_block protocol the chip
10814 * uses with the cpu is race prone.
10815 */
898a56f8 10816 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 10817 tw32(GRC_LOCAL_CTRL,
10818 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10819 } else {
10820 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 10821 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 10822 }
1da177e4 10823
fac9b83e 10824 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
f47c11ee 10825 spin_unlock(&tp->lock);
db219973 10826 tg3_reset_task_schedule(tp);
5b190624 10827 goto restart_timer;
fac9b83e 10828 }
1da177e4
LT		 10829 }
10830
1da177e4
LT		 10831 /* This part only runs once per second. */
10832 if (!--tp->timer_counter) {
63c3a66f 10833 if (tg3_flag(tp, 5705_PLUS))
fac9b83e
DM		 10834 tg3_periodic_fetch_stats(tp);
10835
b0c5943f
MC		 10836 if (tp->setlpicnt && !--tp->setlpicnt)
10837 tg3_phy_eee_enable(tp);
52b02d04 10838
63c3a66f 10839 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 10840 u32 mac_stat;
10841 int phy_event;
10842
10843 mac_stat = tr32(MAC_STATUS);
10844
10845 phy_event = 0;
f07e9af3 10846 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
1da177e4
LT		 10847 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10848 phy_event = 1;
10849 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10850 phy_event = 1;
10851
10852 if (phy_event)
953c96e0 10853 tg3_setup_phy(tp, false);
63c3a66f 10854 } else if (tg3_flag(tp, POLL_SERDES)) {
1da177e4
LT		 10855 u32 mac_stat = tr32(MAC_STATUS);
10856 int need_setup = 0;
10857
f4a46d1f 10858 if (tp->link_up &&
1da177e4
LT		 10859 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10860 need_setup = 1;
10861 }
f4a46d1f 10862 if (!tp->link_up &&
1da177e4
LT		 10863 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10864 MAC_STATUS_SIGNAL_DET))) {
10865 need_setup = 1;
10866 }
10867 if (need_setup) {
3d3ebe74
MC		 10868 if (!tp->serdes_counter) {
10869 tw32_f(MAC_MODE,
10870 (tp->mac_mode &
10871 ~MAC_MODE_PORT_MODE_MASK));
10872 udelay(40);
10873 tw32_f(MAC_MODE, tp->mac_mode);
10874 udelay(40);
10875 }
953c96e0 10876 tg3_setup_phy(tp, false);
1da177e4 10877 }
f07e9af3 10878 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
63c3a66f 10879 tg3_flag(tp, 5780_CLASS)) {
747e8f8b 10880 tg3_serdes_parallel_detect(tp);
57d8b880 10881 }
1da177e4
LT		 10882
10883 tp->timer_counter = tp->timer_multiplier;
10884 }
10885
130b8e4d
MC		 10886 /* Heartbeat is only sent once every 2 seconds.
10887 *
10888 * The heartbeat is to tell the ASF firmware that the host
10889 * driver is still alive. In the event that the OS crashes,
10890 * ASF needs to reset the hardware to free up the FIFO space
10891 * that may be filled with rx packets destined for the host.
10892 * If the FIFO is full, ASF will no longer function properly.
10893 *
10894 * Unintended resets have been reported on real time kernels
10895 * where the timer doesn't run on time. Netpoll will also have
10896 * same problem.
10897 *
10898 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
10899 * to check the ring condition when the heartbeat is expiring
10900 * before doing the reset. This will prevent most unintended
10901 * resets.
10902 */
1da177e4 10903 if (!--tp->asf_counter) {
63c3a66f 10904 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7c5026aa
MC		 10905 tg3_wait_for_event_ack(tp);
10906
bbadf503 10907 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 10908 FWCMD_NICDRV_ALIVE3);
bbadf503 10909 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
c6cdf436
MC		 10910 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
10911 TG3_FW_UPDATE_TIMEOUT_SEC);
4ba526ce
MC		 10912
10913 tg3_generate_fw_event(tp);
1da177e4
LT		 10914 }
10915 tp->asf_counter = tp->asf_multiplier;
10916 }
10917
f47c11ee 10918 spin_unlock(&tp->lock);
1da177e4 10919
f475f163 10920restart_timer:
1da177e4
LT		 10921 tp->timer.expires = jiffies + tp->timer_offset;
10922 add_timer(&tp->timer);
10923}
10924
229b1ad1 10925static void tg3_timer_init(struct tg3 *tp)
21f7638e
MC		 10926{
10927 if (tg3_flag(tp, TAGGED_STATUS) &&
4153577a 10928 tg3_asic_rev(tp) != ASIC_REV_5717 &&
21f7638e
MC		 10929 !tg3_flag(tp, 57765_CLASS))
10930 tp->timer_offset = HZ;
10931 else
10932 tp->timer_offset = HZ / 10;
10933
10934 BUG_ON(tp->timer_offset > HZ);
10935
10936 tp->timer_multiplier = (HZ / tp->timer_offset);
10937 tp->asf_multiplier = (HZ / tp->timer_offset) *
10938 TG3_FW_UPDATE_FREQ_SEC;
10939
10940 init_timer(&tp->timer);
10941 tp->timer.data = (unsigned long) tp;
10942 tp->timer.function = tg3_timer;
10943}
10944
10945static void tg3_timer_start(struct tg3 *tp)
10946{
10947 tp->asf_counter = tp->asf_multiplier;
10948 tp->timer_counter = tp->timer_multiplier;
10949
10950 tp->timer.expires = jiffies + tp->timer_offset;
10951 add_timer(&tp->timer);
10952}
10953
10954static void tg3_timer_stop(struct tg3 *tp)
10955{
10956 del_timer_sync(&tp->timer);
10957}
10958
10959/* Restart hardware after configuration changes, self-test, etc.
10960 * Invoked with tp->lock held.
10961 */
953c96e0 10962static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
21f7638e
MC		 10963 __releases(tp->lock)
10964 __acquires(tp->lock)
10965{
10966 int err;
10967
10968 err = tg3_init_hw(tp, reset_phy);
10969 if (err) {
10970 netdev_err(tp->dev,
10971 "Failed to re-initialize device, aborting\n");
10972 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10973 tg3_full_unlock(tp);
10974 tg3_timer_stop(tp);
10975 tp->irq_sync = 0;
10976 tg3_napi_enable(tp);
10977 dev_close(tp->dev);
10978 tg3_full_lock(tp, 0);
10979 }
10980 return err;
10981}
10982
10983static void tg3_reset_task(struct work_struct *work)
10984{
10985 struct tg3 *tp = container_of(work, struct tg3, reset_task);
10986 int err;
10987
10988 tg3_full_lock(tp, 0);
10989
10990 if (!netif_running(tp->dev)) {
10991 tg3_flag_clear(tp, RESET_TASK_PENDING);
10992 tg3_full_unlock(tp);
10993 return;
10994 }
10995
10996 tg3_full_unlock(tp);
10997
10998 tg3_phy_stop(tp);
10999
11000 tg3_netif_stop(tp);
11001
11002 tg3_full_lock(tp, 1);
11003
11004 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11005 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11006 tp->write32_rx_mbox = tg3_write_flush_reg32;
11007 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11008 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11009 }
11010
11011 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
953c96e0 11012 err = tg3_init_hw(tp, true);
21f7638e
MC		 11013 if (err)
11014 goto out;
11015
11016 tg3_netif_start(tp);
11017
11018out:
11019 tg3_full_unlock(tp);
11020
11021 if (!err)
11022 tg3_phy_start(tp);
11023
11024 tg3_flag_clear(tp, RESET_TASK_PENDING);
11025}
11026
4f125f42 11027static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 11028{
7d12e780 11029 irq_handler_t fn;
fcfa0a32 11030 unsigned long flags;
4f125f42
MC		 11031 char *name;
11032 struct tg3_napi *tnapi = &tp->napi[irq_num];
11033
11034 if (tp->irq_cnt == 1)
11035 name = tp->dev->name;
11036 else {
11037 name = &tnapi->irq_lbl[0];
11038 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
11039 name[IFNAMSIZ-1] = 0;
11040 }
fcfa0a32 11041
63c3a66f 11042 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
fcfa0a32 11043 fn = tg3_msi;
63c3a66f 11044 if (tg3_flag(tp, 1SHOT_MSI))
fcfa0a32 11045 fn = tg3_msi_1shot;
ab392d2d 11046 flags = 0;
fcfa0a32
MC		 11047 } else {
11048 fn = tg3_interrupt;
63c3a66f 11049 if (tg3_flag(tp, TAGGED_STATUS))
fcfa0a32 11050 fn = tg3_interrupt_tagged;
ab392d2d 11051 flags = IRQF_SHARED;
fcfa0a32 11052 }
4f125f42
MC		 11053
11054 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 11055}
11056
7938109f
MC		 11057static int tg3_test_interrupt(struct tg3 *tp)
11058{
09943a18 11059 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 11060 struct net_device *dev = tp->dev;
b16250e3 11061 int err, i, intr_ok = 0;
f6eb9b1f 11062 u32 val;
7938109f 11063
d4bc3927
MC		 11064 if (!netif_running(dev))
11065 return -ENODEV;
11066
7938109f
MC		 11067 tg3_disable_ints(tp);
11068
4f125f42 11069 free_irq(tnapi->irq_vec, tnapi);
7938109f 11070
f6eb9b1f
MC		 11071 /*
11072 * Turn off MSI one shot mode. Otherwise this test has no
11073 * observable way to know whether the interrupt was delivered.
11074 */
3aa1cdf8 11075 if (tg3_flag(tp, 57765_PLUS)) {
f6eb9b1f
MC		 11076 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11077 tw32(MSGINT_MODE, val);
11078 }
11079
4f125f42 11080 err = request_irq(tnapi->irq_vec, tg3_test_isr,
f274fd9a 11081 IRQF_SHARED, dev->name, tnapi);
7938109f
MC		 11082 if (err)
11083 return err;
11084
898a56f8 11085 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 11086 tg3_enable_ints(tp);
11087
11088 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 11089 tnapi->coal_now);
7938109f
MC		 11090
11091 for (i = 0; i < 5; i++) {
b16250e3
MC		 11092 u32 int_mbox, misc_host_ctrl;
11093
898a56f8 11094 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 11095 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11096
11097 if ((int_mbox != 0) ||
11098 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11099 intr_ok = 1;
7938109f 11100 break;
b16250e3
MC		 11101 }
11102
3aa1cdf8
MC		 11103 if (tg3_flag(tp, 57765_PLUS) &&
11104 tnapi->hw_status->status_tag != tnapi->last_tag)
11105 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11106
7938109f
MC		 11107 msleep(10);
11108 }
11109
11110 tg3_disable_ints(tp);
11111
4f125f42 11112 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 11113
4f125f42 11114 err = tg3_request_irq(tp, 0);
7938109f
MC		 11115
11116 if (err)
11117 return err;
11118
f6eb9b1f
MC		 11119 if (intr_ok) {
11120 /* Reenable MSI one shot mode. */
5b39de91 11121 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
f6eb9b1f
MC		 11122 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11123 tw32(MSGINT_MODE, val);
11124 }
7938109f 11125 return 0;
f6eb9b1f 11126 }
7938109f
MC		 11127
11128 return -EIO;
11129}
11130
11131/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11132 * successfully restored
11133 */
11134static int tg3_test_msi(struct tg3 *tp)
11135{
7938109f
MC		 11136 int err;
11137 u16 pci_cmd;
11138
63c3a66f 11139 if (!tg3_flag(tp, USING_MSI))
7938109f
MC		 11140 return 0;
11141
11142 /* Turn off SERR reporting in case MSI terminates with Master
11143 * Abort.
11144 */
11145 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11146 pci_write_config_word(tp->pdev, PCI_COMMAND,
11147 pci_cmd & ~PCI_COMMAND_SERR);
11148
11149 err = tg3_test_interrupt(tp);
11150
11151 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11152
11153 if (!err)
11154 return 0;
11155
11156 /* other failures */
11157 if (err != -EIO)
11158 return err;
11159
11160 /* MSI test failed, go back to INTx mode */
5129c3a3
MC		 11161 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11162 "to INTx mode. Please report this failure to the PCI "
11163 "maintainer and include system chipset information\n");
7938109f 11164
4f125f42 11165 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 11166
7938109f
MC		 11167 pci_disable_msi(tp->pdev);
11168
63c3a66f 11169 tg3_flag_clear(tp, USING_MSI);
dc8bf1b1 11170 tp->napi[0].irq_vec = tp->pdev->irq;
7938109f 11171
4f125f42 11172 err = tg3_request_irq(tp, 0);
7938109f
MC		 11173 if (err)
11174 return err;
11175
11176 /* Need to reset the chip because the MSI cycle may have terminated
11177 * with Master Abort.
11178 */
f47c11ee 11179 tg3_full_lock(tp, 1);
7938109f 11180
944d980e 11181 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 11182 err = tg3_init_hw(tp, true);
7938109f 11183
f47c11ee 11184 tg3_full_unlock(tp);
7938109f
MC		 11185
11186 if (err)
4f125f42 11187 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 11188
11189 return err;
11190}
11191
9e9fd12d
MC		 11192static int tg3_request_firmware(struct tg3 *tp)
11193{
77997ea3 11194 const struct tg3_firmware_hdr *fw_hdr;
9e9fd12d
MC		 11195
11196 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 11197 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11198 tp->fw_needed);
9e9fd12d
MC		 11199 return -ENOENT;
11200 }
11201
77997ea3 11202 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
9e9fd12d
MC		 11203
11204 /* Firmware blob starts with version numbers, followed by
11205 * start address and _full_ length including BSS sections
11206 * (which must be longer than the actual data, of course
11207 */
11208
77997ea3
NS		 11209 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11210 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
05dbe005
JP		 11211 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11212 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 11213 release_firmware(tp->fw);
11214 tp->fw = NULL;
11215 return -EINVAL;
11216 }
11217
11218 /* We no longer need firmware; we have it. */
11219 tp->fw_needed = NULL;
11220 return 0;
11221}
11222
9102426a 11223static u32 tg3_irq_count(struct tg3 *tp)
679563f4 11224{
9102426a 11225 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
679563f4 11226
9102426a 11227 if (irq_cnt > 1) {
c3b5003b
MC		 11228 /* We want as many rx rings enabled as there are cpus.
11229 * In multiqueue MSI-X mode, the first MSI-X vector
11230 * only deals with link interrupts, etc, so we add
11231 * one to the number of vectors we are requesting.
11232 */
9102426a 11233 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
c3b5003b 11234 }
679563f4 11235
9102426a
MC		 11236 return irq_cnt;
11237}
11238
11239static bool tg3_enable_msix(struct tg3 *tp)
11240{
11241 int i, rc;
86449944 11242 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
9102426a 11243
0968169c
MC		 11244 tp->txq_cnt = tp->txq_req;
11245 tp->rxq_cnt = tp->rxq_req;
11246 if (!tp->rxq_cnt)
11247 tp->rxq_cnt = netif_get_num_default_rss_queues();
9102426a
MC		 11248 if (tp->rxq_cnt > tp->rxq_max)
11249 tp->rxq_cnt = tp->rxq_max;
cf6d6ea6
MC		 11250
11251 /* Disable multiple TX rings by default. Simple round-robin hardware
11252 * scheduling of the TX rings can cause starvation of rings with
11253 * small packets when other rings have TSO or jumbo packets.
11254 */
11255 if (!tp->txq_req)
11256 tp->txq_cnt = 1;
9102426a
MC		 11257
11258 tp->irq_cnt = tg3_irq_count(tp);
11259
679563f4
MC		 11260 for (i = 0; i < tp->irq_max; i++) {
11261 msix_ent[i].entry = i;
11262 msix_ent[i].vector = 0;
11263 }
11264
11265 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
2430b031
MC		 11266 if (rc < 0) {
11267 return false;
11268 } else if (rc != 0) {
679563f4
MC		 11269 if (pci_enable_msix(tp->pdev, msix_ent, rc))
11270 return false;
05dbe005
JP		 11271 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11272 tp->irq_cnt, rc);
679563f4 11273 tp->irq_cnt = rc;
49a359e3 11274 tp->rxq_cnt = max(rc - 1, 1);
9102426a
MC		 11275 if (tp->txq_cnt)
11276 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
679563f4
MC		 11277 }
11278
11279 for (i = 0; i < tp->irq_max; i++)
11280 tp->napi[i].irq_vec = msix_ent[i].vector;
11281
49a359e3 11282 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
2ddaad39
BH		 11283 pci_disable_msix(tp->pdev);
11284 return false;
11285 }
b92b9040 11286
9102426a
MC		 11287 if (tp->irq_cnt == 1)
11288 return true;
d78b59f5 11289
9102426a
MC		 11290 tg3_flag_set(tp, ENABLE_RSS);
11291
11292 if (tp->txq_cnt > 1)
11293 tg3_flag_set(tp, ENABLE_TSS);
11294
11295 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
2430b031 11296
679563f4
MC		 11297 return true;
11298}
11299
07b0173c
MC		 11300static void tg3_ints_init(struct tg3 *tp)
11301{
63c3a66f
JP		 11302 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11303 !tg3_flag(tp, TAGGED_STATUS)) {
07b0173c
MC		 11304 /* All MSI supporting chips should support tagged
11305 * status. Assert that this is the case.
11306 */
5129c3a3
MC		 11307 netdev_warn(tp->dev,
11308 "MSI without TAGGED_STATUS? Not using MSI\n");
679563f4 11309 goto defcfg;
07b0173c 11310 }
4f125f42 11311
63c3a66f
JP		 11312 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11313 tg3_flag_set(tp, USING_MSIX);
11314 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11315 tg3_flag_set(tp, USING_MSI);
679563f4 11316
63c3a66f 11317 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
679563f4 11318 u32 msi_mode = tr32(MSGINT_MODE);
63c3a66f 11319 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
baf8a94a 11320 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 11321 if (!tg3_flag(tp, 1SHOT_MSI))
11322 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
679563f4
MC		 11323 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11324 }
11325defcfg:
63c3a66f 11326 if (!tg3_flag(tp, USING_MSIX)) {
679563f4
MC		 11327 tp->irq_cnt = 1;
11328 tp->napi[0].irq_vec = tp->pdev->irq;
49a359e3
MC		 11329 }
11330
11331 if (tp->irq_cnt == 1) {
11332 tp->txq_cnt = 1;
11333 tp->rxq_cnt = 1;
2ddaad39 11334 netif_set_real_num_tx_queues(tp->dev, 1);
85407885 11335 netif_set_real_num_rx_queues(tp->dev, 1);
679563f4 11336 }
07b0173c
MC		 11337}
11338
11339static void tg3_ints_fini(struct tg3 *tp)
11340{
63c3a66f 11341 if (tg3_flag(tp, USING_MSIX))
679563f4 11342 pci_disable_msix(tp->pdev);
63c3a66f 11343 else if (tg3_flag(tp, USING_MSI))
679563f4 11344 pci_disable_msi(tp->pdev);
63c3a66f
JP		 11345 tg3_flag_clear(tp, USING_MSI);
11346 tg3_flag_clear(tp, USING_MSIX);
11347 tg3_flag_clear(tp, ENABLE_RSS);
11348 tg3_flag_clear(tp, ENABLE_TSS);
07b0173c
MC		 11349}
11350
be947307
MC		 11351static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11352 bool init)
1da177e4 11353{
d8f4cd38 11354 struct net_device *dev = tp->dev;
4f125f42 11355 int i, err;
1da177e4 11356
679563f4
MC		 11357 /*
11358 * Setup interrupts first so we know how
11359 * many NAPI resources to allocate
11360 */
11361 tg3_ints_init(tp);
11362
90415477 11363 tg3_rss_check_indir_tbl(tp);
bcebcc46 11364
1da177e4
LT		 11365 /* The placement of this call is tied
11366 * to the setup and use of Host TX descriptors.
11367 */
11368 err = tg3_alloc_consistent(tp);
11369 if (err)
4a5f46f2 11370 goto out_ints_fini;
88b06bc2 11371
66cfd1bd
MC		 11372 tg3_napi_init(tp);
11373
fed97810 11374 tg3_napi_enable(tp);
1da177e4 11375
4f125f42
MC		 11376 for (i = 0; i < tp->irq_cnt; i++) {
11377 struct tg3_napi *tnapi = &tp->napi[i];
11378 err = tg3_request_irq(tp, i);
11379 if (err) {
5bc09186
MC		 11380 for (i--; i >= 0; i--) {
11381 tnapi = &tp->napi[i];
4f125f42 11382 free_irq(tnapi->irq_vec, tnapi);
5bc09186 11383 }
4a5f46f2 11384 goto out_napi_fini;
4f125f42
MC		 11385 }
11386 }
1da177e4 11387
f47c11ee 11388 tg3_full_lock(tp, 0);
1da177e4 11389
2e460fc0
NS		 11390 if (init)
11391 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11392
d8f4cd38 11393 err = tg3_init_hw(tp, reset_phy);
1da177e4 11394 if (err) {
944d980e 11395 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11396 tg3_free_rings(tp);
1da177e4
LT		 11397 }
11398
f47c11ee 11399 tg3_full_unlock(tp);
1da177e4 11400
07b0173c 11401 if (err)
4a5f46f2 11402 goto out_free_irq;
1da177e4 11403
d8f4cd38 11404 if (test_irq && tg3_flag(tp, USING_MSI)) {
7938109f 11405 err = tg3_test_msi(tp);
fac9b83e 11406
7938109f 11407 if (err) {
f47c11ee 11408 tg3_full_lock(tp, 0);
944d980e 11409 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 11410 tg3_free_rings(tp);
f47c11ee 11411 tg3_full_unlock(tp);
7938109f 11412
4a5f46f2 11413 goto out_napi_fini;
7938109f 11414 }
fcfa0a32 11415
63c3a66f 11416 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
f6eb9b1f 11417 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 11418
f6eb9b1f
MC		 11419 tw32(PCIE_TRANSACTION_CFG,
11420 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 11421 }
7938109f
MC		 11422 }
11423
b02fd9e3
MC		 11424 tg3_phy_start(tp);
11425
aed93e0b
MC		 11426 tg3_hwmon_open(tp);
11427
f47c11ee 11428 tg3_full_lock(tp, 0);
1da177e4 11429
21f7638e 11430 tg3_timer_start(tp);
63c3a66f 11431 tg3_flag_set(tp, INIT_COMPLETE);
1da177e4
LT		 11432 tg3_enable_ints(tp);
11433
be947307
MC		 11434 if (init)
11435 tg3_ptp_init(tp);
11436 else
11437 tg3_ptp_resume(tp);
11438
11439
f47c11ee 11440 tg3_full_unlock(tp);
1da177e4 11441
fe5f5787 11442 netif_tx_start_all_queues(dev);
1da177e4 11443
06c03c02
MB		 11444 /*
11445 * Reset loopback feature if it was turned on while the device was down
11446 * make sure that it's installed properly now.
11447 */
11448 if (dev->features & NETIF_F_LOOPBACK)
11449 tg3_set_loopback(dev, dev->features);
11450
1da177e4 11451 return 0;
07b0173c 11452
4a5f46f2 11453out_free_irq:
4f125f42
MC		 11454 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11455 struct tg3_napi *tnapi = &tp->napi[i];
11456 free_irq(tnapi->irq_vec, tnapi);
11457 }
07b0173c 11458
4a5f46f2 11459out_napi_fini:
fed97810 11460 tg3_napi_disable(tp);
66cfd1bd 11461 tg3_napi_fini(tp);
07b0173c 11462 tg3_free_consistent(tp);
679563f4 11463
4a5f46f2 11464out_ints_fini:
679563f4 11465 tg3_ints_fini(tp);
d8f4cd38 11466
07b0173c 11467 return err;
1da177e4
LT		 11468}
11469
65138594 11470static void tg3_stop(struct tg3 *tp)
1da177e4 11471{
4f125f42 11472 int i;
1da177e4 11473
db219973 11474 tg3_reset_task_cancel(tp);
bd473da3 11475 tg3_netif_stop(tp);
1da177e4 11476
21f7638e 11477 tg3_timer_stop(tp);
1da177e4 11478
aed93e0b
MC		 11479 tg3_hwmon_close(tp);
11480
24bb4fb6
MC		 11481 tg3_phy_stop(tp);
11482
f47c11ee 11483 tg3_full_lock(tp, 1);
1da177e4
LT		 11484
11485 tg3_disable_ints(tp);
11486
944d980e 11487 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11488 tg3_free_rings(tp);
63c3a66f 11489 tg3_flag_clear(tp, INIT_COMPLETE);
1da177e4 11490
f47c11ee 11491 tg3_full_unlock(tp);
1da177e4 11492
4f125f42
MC		 11493 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11494 struct tg3_napi *tnapi = &tp->napi[i];
11495 free_irq(tnapi->irq_vec, tnapi);
11496 }
07b0173c
MC		 11497
11498 tg3_ints_fini(tp);
1da177e4 11499
66cfd1bd
MC		 11500 tg3_napi_fini(tp);
11501
1da177e4 11502 tg3_free_consistent(tp);
65138594
MC		 11503}
11504
d8f4cd38
MC		 11505static int tg3_open(struct net_device *dev)
11506{
11507 struct tg3 *tp = netdev_priv(dev);
11508 int err;
11509
11510 if (tp->fw_needed) {
11511 err = tg3_request_firmware(tp);
c4dab506
NS		 11512 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11513 if (err) {
11514 netdev_warn(tp->dev, "EEE capability disabled\n");
11515 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11516 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11517 netdev_warn(tp->dev, "EEE capability restored\n");
11518 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11519 }
11520 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
d8f4cd38
MC		 11521 if (err)
11522 return err;
11523 } else if (err) {
11524 netdev_warn(tp->dev, "TSO capability disabled\n");
11525 tg3_flag_clear(tp, TSO_CAPABLE);
11526 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11527 netdev_notice(tp->dev, "TSO capability restored\n");
11528 tg3_flag_set(tp, TSO_CAPABLE);
11529 }
11530 }
11531
f4a46d1f 11532 tg3_carrier_off(tp);
d8f4cd38
MC		 11533
11534 err = tg3_power_up(tp);
11535 if (err)
11536 return err;
11537
11538 tg3_full_lock(tp, 0);
11539
11540 tg3_disable_ints(tp);
11541 tg3_flag_clear(tp, INIT_COMPLETE);
11542
11543 tg3_full_unlock(tp);
11544
942d1af0
NS		 11545 err = tg3_start(tp,
11546 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11547 true, true);
d8f4cd38
MC		 11548 if (err) {
11549 tg3_frob_aux_power(tp, false);
11550 pci_set_power_state(tp->pdev, PCI_D3hot);
11551 }
be947307 11552
7d41e49a
MC		 11553 if (tg3_flag(tp, PTP_CAPABLE)) {
11554 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11555 &tp->pdev->dev);
11556 if (IS_ERR(tp->ptp_clock))
11557 tp->ptp_clock = NULL;
11558 }
11559
07b0173c 11560 return err;
1da177e4
LT		 11561}
11562
1da177e4
LT		 11563static int tg3_close(struct net_device *dev)
11564{
11565 struct tg3 *tp = netdev_priv(dev);
11566
be947307
MC		 11567 tg3_ptp_fini(tp);
11568
65138594 11569 tg3_stop(tp);
1da177e4 11570
92feeabf
MC		 11571 /* Clear stats across close / open calls */
11572 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11573 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
1da177e4 11574
5137a2ee 11575 tg3_power_down_prepare(tp);
bc1c7567 11576
f4a46d1f 11577 tg3_carrier_off(tp);
bc1c7567 11578
1da177e4
LT		 11579 return 0;
11580}
11581
511d2224 11582static inline u64 get_stat64(tg3_stat64_t *val)
816f8b86
SB		 11583{
11584 return ((u64)val->high << 32) | ((u64)val->low);
11585}
11586
65ec698d 11587static u64 tg3_calc_crc_errors(struct tg3 *tp)
1da177e4
LT		 11588{
11589 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11590
f07e9af3 11591 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a
JP		 11592 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11593 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 11594 u32 val;
11595
569a5df8
MC		 11596 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11597 tg3_writephy(tp, MII_TG3_TEST1,
11598 val | MII_TG3_TEST1_CRC_EN);
f08aa1a8 11599 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
1da177e4
LT		 11600 } else
11601 val = 0;
1da177e4
LT		 11602
11603 tp->phy_crc_errors += val;
11604
11605 return tp->phy_crc_errors;
11606 }
11607
11608 return get_stat64(&hw_stats->rx_fcs_errors);
11609}
11610
11611#define ESTAT_ADD(member) \
11612 estats->member = old_estats->member + \
511d2224 11613 get_stat64(&hw_stats->member)
1da177e4 11614
65ec698d 11615static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
1da177e4 11616{
1da177e4
LT		 11617 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11618 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11619
1da177e4
LT		 11620 ESTAT_ADD(rx_octets);
11621 ESTAT_ADD(rx_fragments);
11622 ESTAT_ADD(rx_ucast_packets);
11623 ESTAT_ADD(rx_mcast_packets);
11624 ESTAT_ADD(rx_bcast_packets);
11625 ESTAT_ADD(rx_fcs_errors);
11626 ESTAT_ADD(rx_align_errors);
11627 ESTAT_ADD(rx_xon_pause_rcvd);
11628 ESTAT_ADD(rx_xoff_pause_rcvd);
11629 ESTAT_ADD(rx_mac_ctrl_rcvd);
11630 ESTAT_ADD(rx_xoff_entered);
11631 ESTAT_ADD(rx_frame_too_long_errors);
11632 ESTAT_ADD(rx_jabbers);
11633 ESTAT_ADD(rx_undersize_packets);
11634 ESTAT_ADD(rx_in_length_errors);
11635 ESTAT_ADD(rx_out_length_errors);
11636 ESTAT_ADD(rx_64_or_less_octet_packets);
11637 ESTAT_ADD(rx_65_to_127_octet_packets);
11638 ESTAT_ADD(rx_128_to_255_octet_packets);
11639 ESTAT_ADD(rx_256_to_511_octet_packets);
11640 ESTAT_ADD(rx_512_to_1023_octet_packets);
11641 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11642 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11643 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11644 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11645 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11646
11647 ESTAT_ADD(tx_octets);
11648 ESTAT_ADD(tx_collisions);
11649 ESTAT_ADD(tx_xon_sent);
11650 ESTAT_ADD(tx_xoff_sent);
11651 ESTAT_ADD(tx_flow_control);
11652 ESTAT_ADD(tx_mac_errors);
11653 ESTAT_ADD(tx_single_collisions);
11654 ESTAT_ADD(tx_mult_collisions);
11655 ESTAT_ADD(tx_deferred);
11656 ESTAT_ADD(tx_excessive_collisions);
11657 ESTAT_ADD(tx_late_collisions);
11658 ESTAT_ADD(tx_collide_2times);
11659 ESTAT_ADD(tx_collide_3times);
11660 ESTAT_ADD(tx_collide_4times);
11661 ESTAT_ADD(tx_collide_5times);
11662 ESTAT_ADD(tx_collide_6times);
11663 ESTAT_ADD(tx_collide_7times);
11664 ESTAT_ADD(tx_collide_8times);
11665 ESTAT_ADD(tx_collide_9times);
11666 ESTAT_ADD(tx_collide_10times);
11667 ESTAT_ADD(tx_collide_11times);
11668 ESTAT_ADD(tx_collide_12times);
11669 ESTAT_ADD(tx_collide_13times);
11670 ESTAT_ADD(tx_collide_14times);
11671 ESTAT_ADD(tx_collide_15times);
11672 ESTAT_ADD(tx_ucast_packets);
11673 ESTAT_ADD(tx_mcast_packets);
11674 ESTAT_ADD(tx_bcast_packets);
11675 ESTAT_ADD(tx_carrier_sense_errors);
11676 ESTAT_ADD(tx_discards);
11677 ESTAT_ADD(tx_errors);
11678
11679 ESTAT_ADD(dma_writeq_full);
11680 ESTAT_ADD(dma_write_prioq_full);
11681 ESTAT_ADD(rxbds_empty);
11682 ESTAT_ADD(rx_discards);
11683 ESTAT_ADD(rx_errors);
11684 ESTAT_ADD(rx_threshold_hit);
11685
11686 ESTAT_ADD(dma_readq_full);
11687 ESTAT_ADD(dma_read_prioq_full);
11688 ESTAT_ADD(tx_comp_queue_full);
11689
11690 ESTAT_ADD(ring_set_send_prod_index);
11691 ESTAT_ADD(ring_status_update);
11692 ESTAT_ADD(nic_irqs);
11693 ESTAT_ADD(nic_avoided_irqs);
11694 ESTAT_ADD(nic_tx_threshold_hit);
11695
4452d099 11696 ESTAT_ADD(mbuf_lwm_thresh_hit);
1da177e4
LT		 11697}
11698
65ec698d 11699static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
1da177e4 11700{
511d2224 11701 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
1da177e4
LT		 11702 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11703
1da177e4
LT		 11704 stats->rx_packets = old_stats->rx_packets +
11705 get_stat64(&hw_stats->rx_ucast_packets) +
11706 get_stat64(&hw_stats->rx_mcast_packets) +
11707 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 11708
1da177e4
LT		 11709 stats->tx_packets = old_stats->tx_packets +
11710 get_stat64(&hw_stats->tx_ucast_packets) +
11711 get_stat64(&hw_stats->tx_mcast_packets) +
11712 get_stat64(&hw_stats->tx_bcast_packets);
11713
11714 stats->rx_bytes = old_stats->rx_bytes +
11715 get_stat64(&hw_stats->rx_octets);
11716 stats->tx_bytes = old_stats->tx_bytes +
11717 get_stat64(&hw_stats->tx_octets);
11718
11719 stats->rx_errors = old_stats->rx_errors +
4f63b877 11720 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 11721 stats->tx_errors = old_stats->tx_errors +
11722 get_stat64(&hw_stats->tx_errors) +
11723 get_stat64(&hw_stats->tx_mac_errors) +
11724 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11725 get_stat64(&hw_stats->tx_discards);
11726
11727 stats->multicast = old_stats->multicast +
11728 get_stat64(&hw_stats->rx_mcast_packets);
11729 stats->collisions = old_stats->collisions +
11730 get_stat64(&hw_stats->tx_collisions);
11731
11732 stats->rx_length_errors = old_stats->rx_length_errors +
11733 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11734 get_stat64(&hw_stats->rx_undersize_packets);
11735
11736 stats->rx_over_errors = old_stats->rx_over_errors +
11737 get_stat64(&hw_stats->rxbds_empty);
11738 stats->rx_frame_errors = old_stats->rx_frame_errors +
11739 get_stat64(&hw_stats->rx_align_errors);
11740 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11741 get_stat64(&hw_stats->tx_discards);
11742 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11743 get_stat64(&hw_stats->tx_carrier_sense_errors);
11744
11745 stats->rx_crc_errors = old_stats->rx_crc_errors +
65ec698d 11746 tg3_calc_crc_errors(tp);
1da177e4 11747
4f63b877
JL		 11748 stats->rx_missed_errors = old_stats->rx_missed_errors +
11749 get_stat64(&hw_stats->rx_discards);
11750
b0057c51 11751 stats->rx_dropped = tp->rx_dropped;
48855432 11752 stats->tx_dropped = tp->tx_dropped;
1da177e4
LT		 11753}
11754
1da177e4
LT		 11755static int tg3_get_regs_len(struct net_device *dev)
11756{
97bd8e49 11757 return TG3_REG_BLK_SIZE;
1da177e4
LT		 11758}
11759
11760static void tg3_get_regs(struct net_device *dev,
11761 struct ethtool_regs *regs, void *_p)
11762{
1da177e4 11763 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 11764
11765 regs->version = 0;
11766
97bd8e49 11767 memset(_p, 0, TG3_REG_BLK_SIZE);
1da177e4 11768
80096068 11769 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
bc1c7567
MC		 11770 return;
11771
f47c11ee 11772 tg3_full_lock(tp, 0);
1da177e4 11773
97bd8e49 11774 tg3_dump_legacy_regs(tp, (u32 *)_p);
1da177e4 11775
f47c11ee 11776 tg3_full_unlock(tp);
1da177e4
LT		 11777}
11778
11779static int tg3_get_eeprom_len(struct net_device *dev)
11780{
11781 struct tg3 *tp = netdev_priv(dev);
11782
11783 return tp->nvram_size;
11784}
11785
1da177e4
LT		 11786static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11787{
11788 struct tg3 *tp = netdev_priv(dev);
11789 int ret;
11790 u8 *pd;
b9fc7dc5 11791 u32 i, offset, len, b_offset, b_count;
a9dc529d 11792 __be32 val;
1da177e4 11793
63c3a66f 11794 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 11795 return -EINVAL;
11796
1da177e4
LT		 11797 offset = eeprom->offset;
11798 len = eeprom->len;
11799 eeprom->len = 0;
11800
11801 eeprom->magic = TG3_EEPROM_MAGIC;
11802
11803 if (offset & 3) {
11804 /* adjustments to start on required 4 byte boundary */
11805 b_offset = offset & 3;
11806 b_count = 4 - b_offset;
11807 if (b_count > len) {
11808 /* i.e. offset=1 len=2 */
11809 b_count = len;
11810 }
a9dc529d 11811 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 11812 if (ret)
11813 return ret;
be98da6a 11814 memcpy(data, ((char *)&val) + b_offset, b_count);
1da177e4
LT		 11815 len -= b_count;
11816 offset += b_count;
c6cdf436 11817 eeprom->len += b_count;
1da177e4
LT		 11818 }
11819
25985edc 11820 /* read bytes up to the last 4 byte boundary */
1da177e4
LT		 11821 pd = &data[eeprom->len];
11822 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 11823 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 11824 if (ret) {
11825 eeprom->len += i;
11826 return ret;
11827 }
1da177e4
LT		 11828 memcpy(pd + i, &val, 4);
11829 }
11830 eeprom->len += i;
11831
11832 if (len & 3) {
11833 /* read last bytes not ending on 4 byte boundary */
11834 pd = &data[eeprom->len];
11835 b_count = len & 3;
11836 b_offset = offset + len - b_count;
a9dc529d 11837 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 11838 if (ret)
11839 return ret;
b9fc7dc5 11840 memcpy(pd, &val, b_count);
1da177e4
LT		 11841 eeprom->len += b_count;
11842 }
11843 return 0;
11844}
11845
1da177e4
LT		 11846static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11847{
11848 struct tg3 *tp = netdev_priv(dev);
11849 int ret;
b9fc7dc5 11850 u32 offset, len, b_offset, odd_len;
1da177e4 11851 u8 *buf;
a9dc529d 11852 __be32 start, end;
1da177e4 11853
63c3a66f 11854 if (tg3_flag(tp, NO_NVRAM) ||
df259d8c 11855 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 11856 return -EINVAL;
11857
11858 offset = eeprom->offset;
11859 len = eeprom->len;
11860
11861 if ((b_offset = (offset & 3))) {
11862 /* adjustments to start on required 4 byte boundary */
a9dc529d 11863 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 11864 if (ret)
11865 return ret;
1da177e4
LT		 11866 len += b_offset;
11867 offset &= ~3;
1c8594b4
MC		 11868 if (len < 4)
11869 len = 4;
1da177e4
LT		 11870 }
11871
11872 odd_len = 0;
1c8594b4 11873 if (len & 3) {
1da177e4
LT		 11874 /* adjustments to end on required 4 byte boundary */
11875 odd_len = 1;
11876 len = (len + 3) & ~3;
a9dc529d 11877 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 11878 if (ret)
11879 return ret;
1da177e4
LT		 11880 }
11881
11882 buf = data;
11883 if (b_offset || odd_len) {
11884 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 11885 if (!buf)
1da177e4
LT		 11886 return -ENOMEM;
11887 if (b_offset)
11888 memcpy(buf, &start, 4);
11889 if (odd_len)
11890 memcpy(buf+len-4, &end, 4);
11891 memcpy(buf + b_offset, data, eeprom->len);
11892 }
11893
11894 ret = tg3_nvram_write_block(tp, offset, len, buf);
11895
11896 if (buf != data)
11897 kfree(buf);
11898
11899 return ret;
11900}
11901
11902static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11903{
b02fd9e3
MC		 11904 struct tg3 *tp = netdev_priv(dev);
11905
63c3a66f 11906 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 11907 struct phy_device *phydev;
f07e9af3 11908 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 11909 return -EAGAIN;
3f0e3ad7
MC		 11910 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11911 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 11912 }
6aa20a22 11913
1da177e4
LT		 11914 cmd->supported = (SUPPORTED_Autoneg);
11915
f07e9af3 11916 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
1da177e4
LT		 11917 cmd->supported |= (SUPPORTED_1000baseT_Half |
11918 SUPPORTED_1000baseT_Full);
11919
f07e9af3 11920 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
1da177e4
LT		 11921 cmd->supported |= (SUPPORTED_100baseT_Half |
11922 SUPPORTED_100baseT_Full |
11923 SUPPORTED_10baseT_Half |
11924 SUPPORTED_10baseT_Full |
3bebab59 11925 SUPPORTED_TP);
ef348144
KK		 11926 cmd->port = PORT_TP;
11927 } else {
1da177e4 11928 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 11929 cmd->port = PORT_FIBRE;
11930 }
6aa20a22 11931
1da177e4 11932 cmd->advertising = tp->link_config.advertising;
5bb09778
MC		 11933 if (tg3_flag(tp, PAUSE_AUTONEG)) {
11934 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
11935 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11936 cmd->advertising |= ADVERTISED_Pause;
11937 } else {
11938 cmd->advertising |= ADVERTISED_Pause |
11939 ADVERTISED_Asym_Pause;
11940 }
11941 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11942 cmd->advertising |= ADVERTISED_Asym_Pause;
11943 }
11944 }
f4a46d1f 11945 if (netif_running(dev) && tp->link_up) {
70739497 11946 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
1da177e4 11947 cmd->duplex = tp->link_config.active_duplex;
859edb26 11948 cmd->lp_advertising = tp->link_config.rmt_adv;
e348c5e7
MC		 11949 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
11950 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
11951 cmd->eth_tp_mdix = ETH_TP_MDI_X;
11952 else
11953 cmd->eth_tp_mdix = ETH_TP_MDI;
11954 }
64c22182 11955 } else {
e740522e
MC		 11956 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
11957 cmd->duplex = DUPLEX_UNKNOWN;
e348c5e7 11958 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
1da177e4 11959 }
882e9793 11960 cmd->phy_address = tp->phy_addr;
7e5856bd 11961 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 11962 cmd->autoneg = tp->link_config.autoneg;
11963 cmd->maxtxpkt = 0;
11964 cmd->maxrxpkt = 0;
11965 return 0;
11966}
6aa20a22 11967
1da177e4
LT		 11968static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11969{
11970 struct tg3 *tp = netdev_priv(dev);
25db0338 11971 u32 speed = ethtool_cmd_speed(cmd);
6aa20a22 11972
63c3a66f 11973 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 11974 struct phy_device *phydev;
f07e9af3 11975 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 11976 return -EAGAIN;
3f0e3ad7
MC		 11977 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11978 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 11979 }
11980
7e5856bd
MC		 11981 if (cmd->autoneg != AUTONEG_ENABLE &&
11982 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 11983 return -EINVAL;
7e5856bd
MC		 11984
11985 if (cmd->autoneg == AUTONEG_DISABLE &&
11986 cmd->duplex != DUPLEX_FULL &&
11987 cmd->duplex != DUPLEX_HALF)
37ff238d 11988 return -EINVAL;
1da177e4 11989
7e5856bd
MC		 11990 if (cmd->autoneg == AUTONEG_ENABLE) {
11991 u32 mask = ADVERTISED_Autoneg |
11992 ADVERTISED_Pause |
11993 ADVERTISED_Asym_Pause;
11994
f07e9af3 11995 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
7e5856bd
MC		 11996 mask |= ADVERTISED_1000baseT_Half |
11997 ADVERTISED_1000baseT_Full;
11998
f07e9af3 11999 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
7e5856bd
MC		 12000 mask |= ADVERTISED_100baseT_Half |
12001 ADVERTISED_100baseT_Full |
12002 ADVERTISED_10baseT_Half |
12003 ADVERTISED_10baseT_Full |
12004 ADVERTISED_TP;
12005 else
12006 mask |= ADVERTISED_FIBRE;
12007
12008 if (cmd->advertising & ~mask)
12009 return -EINVAL;
12010
12011 mask &= (ADVERTISED_1000baseT_Half |
12012 ADVERTISED_1000baseT_Full |
12013 ADVERTISED_100baseT_Half |
12014 ADVERTISED_100baseT_Full |
12015 ADVERTISED_10baseT_Half |
12016 ADVERTISED_10baseT_Full);
12017
12018 cmd->advertising &= mask;
12019 } else {
f07e9af3 12020 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
25db0338 12021 if (speed != SPEED_1000)
7e5856bd
MC		 12022 return -EINVAL;
12023
12024 if (cmd->duplex != DUPLEX_FULL)
12025 return -EINVAL;
12026 } else {
25db0338
DD		 12027 if (speed != SPEED_100 &&
12028 speed != SPEED_10)
7e5856bd
MC		 12029 return -EINVAL;
12030 }
12031 }
12032
f47c11ee 12033 tg3_full_lock(tp, 0);
1da177e4
LT		 12034
12035 tp->link_config.autoneg = cmd->autoneg;
12036 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 12037 tp->link_config.advertising = (cmd->advertising |
12038 ADVERTISED_Autoneg);
e740522e
MC		 12039 tp->link_config.speed = SPEED_UNKNOWN;
12040 tp->link_config.duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 12041 } else {
12042 tp->link_config.advertising = 0;
25db0338 12043 tp->link_config.speed = speed;
1da177e4 12044 tp->link_config.duplex = cmd->duplex;
b02fd9e3 12045 }
6aa20a22 12046
fdad8de4
NS		 12047 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12048
ce20f161
NS		 12049 tg3_warn_mgmt_link_flap(tp);
12050
1da177e4 12051 if (netif_running(dev))
953c96e0 12052 tg3_setup_phy(tp, true);
1da177e4 12053
f47c11ee 12054 tg3_full_unlock(tp);
6aa20a22 12055
1da177e4
LT		 12056 return 0;
12057}
6aa20a22 12058
1da177e4
LT		 12059static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12060{
12061 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12062
68aad78c
RJ		 12063 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12064 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12065 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12066 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
1da177e4 12067}
6aa20a22 12068
1da177e4
LT		 12069static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12070{
12071 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12072
63c3a66f 12073 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 12074 wol->supported = WAKE_MAGIC;
12075 else
12076 wol->supported = 0;
1da177e4 12077 wol->wolopts = 0;
63c3a66f 12078 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 12079 wol->wolopts = WAKE_MAGIC;
12080 memset(&wol->sopass, 0, sizeof(wol->sopass));
12081}
6aa20a22 12082
1da177e4
LT		 12083static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12084{
12085 struct tg3 *tp = netdev_priv(dev);
12dac075 12086 struct device *dp = &tp->pdev->dev;
6aa20a22 12087
1da177e4
LT		 12088 if (wol->wolopts & ~WAKE_MAGIC)
12089 return -EINVAL;
12090 if ((wol->wolopts & WAKE_MAGIC) &&
63c3a66f 12091 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
1da177e4 12092 return -EINVAL;
6aa20a22 12093
f2dc0d18
RW		 12094 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12095
f47c11ee 12096 spin_lock_bh(&tp->lock);
f2dc0d18 12097 if (device_may_wakeup(dp))
63c3a66f 12098 tg3_flag_set(tp, WOL_ENABLE);
f2dc0d18 12099 else
63c3a66f 12100 tg3_flag_clear(tp, WOL_ENABLE);
f47c11ee 12101 spin_unlock_bh(&tp->lock);
6aa20a22 12102
1da177e4
LT		 12103 return 0;
12104}
6aa20a22 12105
1da177e4
LT		 12106static u32 tg3_get_msglevel(struct net_device *dev)
12107{
12108 struct tg3 *tp = netdev_priv(dev);
12109 return tp->msg_enable;
12110}
6aa20a22 12111
1da177e4
LT		 12112static void tg3_set_msglevel(struct net_device *dev, u32 value)
12113{
12114 struct tg3 *tp = netdev_priv(dev);
12115 tp->msg_enable = value;
12116}
6aa20a22 12117
1da177e4
LT		 12118static int tg3_nway_reset(struct net_device *dev)
12119{
12120 struct tg3 *tp = netdev_priv(dev);
1da177e4 12121 int r;
6aa20a22 12122
1da177e4
LT		 12123 if (!netif_running(dev))
12124 return -EAGAIN;
12125
f07e9af3 12126 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
c94e3941
MC		 12127 return -EINVAL;
12128
ce20f161
NS		 12129 tg3_warn_mgmt_link_flap(tp);
12130
63c3a66f 12131 if (tg3_flag(tp, USE_PHYLIB)) {
f07e9af3 12132 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12133 return -EAGAIN;
3f0e3ad7 12134 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 12135 } else {
12136 u32 bmcr;
12137
12138 spin_lock_bh(&tp->lock);
12139 r = -EINVAL;
12140 tg3_readphy(tp, MII_BMCR, &bmcr);
12141 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12142 ((bmcr & BMCR_ANENABLE) ||
f07e9af3 12143 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
b02fd9e3
MC		 12144 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12145 BMCR_ANENABLE);
12146 r = 0;
12147 }
12148 spin_unlock_bh(&tp->lock);
1da177e4 12149 }
6aa20a22 12150
1da177e4
LT		 12151 return r;
12152}
6aa20a22 12153
1da177e4
LT		 12154static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12155{
12156 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12157
2c49a44d 12158 ering->rx_max_pending = tp->rx_std_ring_mask;
63c3a66f 12159 if (tg3_flag(tp, JUMBO_RING_ENABLE))
2c49a44d 12160 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
4f81c32b
MC		 12161 else
12162 ering->rx_jumbo_max_pending = 0;
12163
12164 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 12165
12166 ering->rx_pending = tp->rx_pending;
63c3a66f 12167 if (tg3_flag(tp, JUMBO_RING_ENABLE))
4f81c32b
MC		 12168 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12169 else
12170 ering->rx_jumbo_pending = 0;
12171
f3f3f27e 12172 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 12173}
6aa20a22 12174
1da177e4
LT		 12175static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12176{
12177 struct tg3 *tp = netdev_priv(dev);
646c9edd 12178 int i, irq_sync = 0, err = 0;
6aa20a22 12179
2c49a44d
MC		 12180 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12181 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
bc3a9254
MC		 12182 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12183 (ering->tx_pending <= MAX_SKB_FRAGS) ||
63c3a66f 12184 (tg3_flag(tp, TSO_BUG) &&
bc3a9254 12185 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 12186 return -EINVAL;
6aa20a22 12187
bbe832c0 12188 if (netif_running(dev)) {
b02fd9e3 12189 tg3_phy_stop(tp);
1da177e4 12190 tg3_netif_stop(tp);
bbe832c0
MC		 12191 irq_sync = 1;
12192 }
1da177e4 12193
bbe832c0 12194 tg3_full_lock(tp, irq_sync);
6aa20a22 12195
1da177e4
LT		 12196 tp->rx_pending = ering->rx_pending;
12197
63c3a66f 12198 if (tg3_flag(tp, MAX_RXPEND_64) &&
1da177e4
LT		 12199 tp->rx_pending > 63)
12200 tp->rx_pending = 63;
12201 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd 12202
6fd45cb8 12203 for (i = 0; i < tp->irq_max; i++)
646c9edd 12204 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 12205
12206 if (netif_running(dev)) {
944d980e 12207 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12208 err = tg3_restart_hw(tp, false);
b9ec6c1b
MC		 12209 if (!err)
12210 tg3_netif_start(tp);
1da177e4
LT		 12211 }
12212
f47c11ee 12213 tg3_full_unlock(tp);
6aa20a22 12214
b02fd9e3
MC		 12215 if (irq_sync && !err)
12216 tg3_phy_start(tp);
12217
b9ec6c1b 12218 return err;
1da177e4 12219}
6aa20a22 12220
1da177e4
LT		 12221static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12222{
12223 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12224
63c3a66f 12225 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
8d018621 12226
4a2db503 12227 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
8d018621
MC		 12228 epause->rx_pause = 1;
12229 else
12230 epause->rx_pause = 0;
12231
4a2db503 12232 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
8d018621
MC		 12233 epause->tx_pause = 1;
12234 else
12235 epause->tx_pause = 0;
1da177e4 12236}
6aa20a22 12237
1da177e4
LT		 12238static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12239{
12240 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 12241 int err = 0;
6aa20a22 12242
ce20f161
NS		 12243 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12244 tg3_warn_mgmt_link_flap(tp);
12245
63c3a66f 12246 if (tg3_flag(tp, USE_PHYLIB)) {
2712168f
MC		 12247 u32 newadv;
12248 struct phy_device *phydev;
1da177e4 12249
2712168f 12250 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
f47c11ee 12251
2712168f
MC		 12252 if (!(phydev->supported & SUPPORTED_Pause) ||
12253 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
2259dca3 12254 (epause->rx_pause != epause->tx_pause)))
2712168f 12255 return -EINVAL;
1da177e4 12256
2712168f
MC		 12257 tp->link_config.flowctrl = 0;
12258 if (epause->rx_pause) {
12259 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12260
12261 if (epause->tx_pause) {
12262 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12263 newadv = ADVERTISED_Pause;
b02fd9e3 12264 } else
2712168f
MC		 12265 newadv = ADVERTISED_Pause |
12266 ADVERTISED_Asym_Pause;
12267 } else if (epause->tx_pause) {
12268 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12269 newadv = ADVERTISED_Asym_Pause;
12270 } else
12271 newadv = 0;
12272
12273 if (epause->autoneg)
63c3a66f 12274 tg3_flag_set(tp, PAUSE_AUTONEG);
2712168f 12275 else
63c3a66f 12276 tg3_flag_clear(tp, PAUSE_AUTONEG);
2712168f 12277
f07e9af3 12278 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2712168f
MC		 12279 u32 oldadv = phydev->advertising &
12280 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12281 if (oldadv != newadv) {
12282 phydev->advertising &=
12283 ~(ADVERTISED_Pause |
12284 ADVERTISED_Asym_Pause);
12285 phydev->advertising |= newadv;
12286 if (phydev->autoneg) {
12287 /*
12288 * Always renegotiate the link to
12289 * inform our link partner of our
12290 * flow control settings, even if the
12291 * flow control is forced. Let
12292 * tg3_adjust_link() do the final
12293 * flow control setup.
12294 */
12295 return phy_start_aneg(phydev);
b02fd9e3 12296 }
b02fd9e3 12297 }
b02fd9e3 12298
2712168f 12299 if (!epause->autoneg)
b02fd9e3 12300 tg3_setup_flow_control(tp, 0, 0);
2712168f 12301 } else {
c6700ce2 12302 tp->link_config.advertising &=
2712168f
MC		 12303 ~(ADVERTISED_Pause |
12304 ADVERTISED_Asym_Pause);
c6700ce2 12305 tp->link_config.advertising |= newadv;
b02fd9e3
MC		 12306 }
12307 } else {
12308 int irq_sync = 0;
12309
12310 if (netif_running(dev)) {
12311 tg3_netif_stop(tp);
12312 irq_sync = 1;
12313 }
12314
12315 tg3_full_lock(tp, irq_sync);
12316
12317 if (epause->autoneg)
63c3a66f 12318 tg3_flag_set(tp, PAUSE_AUTONEG);
b02fd9e3 12319 else
63c3a66f 12320 tg3_flag_clear(tp, PAUSE_AUTONEG);
b02fd9e3 12321 if (epause->rx_pause)
e18ce346 12322 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 12323 else
e18ce346 12324 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 12325 if (epause->tx_pause)
e18ce346 12326 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 12327 else
e18ce346 12328 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 12329
12330 if (netif_running(dev)) {
12331 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12332 err = tg3_restart_hw(tp, false);
b02fd9e3
MC		 12333 if (!err)
12334 tg3_netif_start(tp);
12335 }
12336
12337 tg3_full_unlock(tp);
12338 }
6aa20a22 12339
fdad8de4
NS		 12340 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12341
b9ec6c1b 12342 return err;
1da177e4 12343}
6aa20a22 12344
de6f31eb 12345static int tg3_get_sset_count(struct net_device *dev, int sset)
1da177e4 12346{
b9f2c044
JG		 12347 switch (sset) {
12348 case ETH_SS_TEST:
12349 return TG3_NUM_TEST;
12350 case ETH_SS_STATS:
12351 return TG3_NUM_STATS;
12352 default:
12353 return -EOPNOTSUPP;
12354 }
4cafd3f5
MC		 12355}
12356
90415477
MC		 12357static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12358 u32 *rules __always_unused)
12359{
12360 struct tg3 *tp = netdev_priv(dev);
12361
12362 if (!tg3_flag(tp, SUPPORT_MSIX))
12363 return -EOPNOTSUPP;
12364
12365 switch (info->cmd) {
12366 case ETHTOOL_GRXRINGS:
12367 if (netif_running(tp->dev))
9102426a 12368 info->data = tp->rxq_cnt;
90415477
MC		 12369 else {
12370 info->data = num_online_cpus();
9102426a
MC		 12371 if (info->data > TG3_RSS_MAX_NUM_QS)
12372 info->data = TG3_RSS_MAX_NUM_QS;
90415477
MC		 12373 }
12374
12375 /* The first interrupt vector only
12376 * handles link interrupts.
12377 */
12378 info->data -= 1;
12379 return 0;
12380
12381 default:
12382 return -EOPNOTSUPP;
12383 }
12384}
12385
12386static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12387{
12388 u32 size = 0;
12389 struct tg3 *tp = netdev_priv(dev);
12390
12391 if (tg3_flag(tp, SUPPORT_MSIX))
12392 size = TG3_RSS_INDIR_TBL_SIZE;
12393
12394 return size;
12395}
12396
12397static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
12398{
12399 struct tg3 *tp = netdev_priv(dev);
12400 int i;
12401
12402 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12403 indir[i] = tp->rss_ind_tbl[i];
12404
12405 return 0;
12406}
12407
12408static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
12409{
12410 struct tg3 *tp = netdev_priv(dev);
12411 size_t i;
12412
12413 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12414 tp->rss_ind_tbl[i] = indir[i];
12415
12416 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12417 return 0;
12418
12419 /* It is legal to write the indirection
12420 * table while the device is running.
12421 */
12422 tg3_full_lock(tp, 0);
12423 tg3_rss_write_indir_tbl(tp);
12424 tg3_full_unlock(tp);
12425
12426 return 0;
12427}
12428
0968169c
MC		 12429static void tg3_get_channels(struct net_device *dev,
12430 struct ethtool_channels *channel)
12431{
12432 struct tg3 *tp = netdev_priv(dev);
12433 u32 deflt_qs = netif_get_num_default_rss_queues();
12434
12435 channel->max_rx = tp->rxq_max;
12436 channel->max_tx = tp->txq_max;
12437
12438 if (netif_running(dev)) {
12439 channel->rx_count = tp->rxq_cnt;
12440 channel->tx_count = tp->txq_cnt;
12441 } else {
12442 if (tp->rxq_req)
12443 channel->rx_count = tp->rxq_req;
12444 else
12445 channel->rx_count = min(deflt_qs, tp->rxq_max);
12446
12447 if (tp->txq_req)
12448 channel->tx_count = tp->txq_req;
12449 else
12450 channel->tx_count = min(deflt_qs, tp->txq_max);
12451 }
12452}
12453
12454static int tg3_set_channels(struct net_device *dev,
12455 struct ethtool_channels *channel)
12456{
12457 struct tg3 *tp = netdev_priv(dev);
12458
12459 if (!tg3_flag(tp, SUPPORT_MSIX))
12460 return -EOPNOTSUPP;
12461
12462 if (channel->rx_count > tp->rxq_max ||
12463 channel->tx_count > tp->txq_max)
12464 return -EINVAL;
12465
12466 tp->rxq_req = channel->rx_count;
12467 tp->txq_req = channel->tx_count;
12468
12469 if (!netif_running(dev))
12470 return 0;
12471
12472 tg3_stop(tp);
12473
f4a46d1f 12474 tg3_carrier_off(tp);
0968169c 12475
be947307 12476 tg3_start(tp, true, false, false);
0968169c
MC		 12477
12478 return 0;
12479}
12480
de6f31eb 12481static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1da177e4
LT		 12482{
12483 switch (stringset) {
12484 case ETH_SS_STATS:
12485 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
12486 break;
4cafd3f5
MC		 12487 case ETH_SS_TEST:
12488 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
12489 break;
1da177e4
LT		 12490 default:
12491 WARN_ON(1); /* we need a WARN() */
12492 break;
12493 }
12494}
12495
81b8709c 12496static int tg3_set_phys_id(struct net_device *dev,
12497 enum ethtool_phys_id_state state)
4009a93d
MC		 12498{
12499 struct tg3 *tp = netdev_priv(dev);
4009a93d
MC		 12500
12501 if (!netif_running(tp->dev))
12502 return -EAGAIN;
12503
81b8709c 12504 switch (state) {
12505 case ETHTOOL_ID_ACTIVE:
fce55922 12506 return 1; /* cycle on/off once per second */
4009a93d 12507
81b8709c 12508 case ETHTOOL_ID_ON:
12509 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12510 LED_CTRL_1000MBPS_ON |
12511 LED_CTRL_100MBPS_ON |
12512 LED_CTRL_10MBPS_ON |
12513 LED_CTRL_TRAFFIC_OVERRIDE |
12514 LED_CTRL_TRAFFIC_BLINK |
12515 LED_CTRL_TRAFFIC_LED);
12516 break;
6aa20a22 12517
81b8709c 12518 case ETHTOOL_ID_OFF:
12519 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12520 LED_CTRL_TRAFFIC_OVERRIDE);
12521 break;
4009a93d 12522
81b8709c 12523 case ETHTOOL_ID_INACTIVE:
12524 tw32(MAC_LED_CTRL, tp->led_ctrl);
12525 break;
4009a93d 12526 }
81b8709c 12527
4009a93d
MC		 12528 return 0;
12529}
12530
de6f31eb 12531static void tg3_get_ethtool_stats(struct net_device *dev,
1da177e4
LT		 12532 struct ethtool_stats *estats, u64 *tmp_stats)
12533{
12534 struct tg3 *tp = netdev_priv(dev);
0e6c9da3 12535
b546e46f
MC		 12536 if (tp->hw_stats)
12537 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12538 else
12539 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
1da177e4
LT		 12540}
12541
535a490e 12542static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
c3e94500
MC		 12543{
12544 int i;
12545 __be32 *buf;
12546 u32 offset = 0, len = 0;
12547 u32 magic, val;
12548
63c3a66f 12549 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
c3e94500
MC		 12550 return NULL;
12551
12552 if (magic == TG3_EEPROM_MAGIC) {
12553 for (offset = TG3_NVM_DIR_START;
12554 offset < TG3_NVM_DIR_END;
12555 offset += TG3_NVM_DIRENT_SIZE) {
12556 if (tg3_nvram_read(tp, offset, &val))
12557 return NULL;
12558
12559 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12560 TG3_NVM_DIRTYPE_EXTVPD)
12561 break;
12562 }
12563
12564 if (offset != TG3_NVM_DIR_END) {
12565 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12566 if (tg3_nvram_read(tp, offset + 4, &offset))
12567 return NULL;
12568
12569 offset = tg3_nvram_logical_addr(tp, offset);
12570 }
12571 }
12572
12573 if (!offset || !len) {
12574 offset = TG3_NVM_VPD_OFF;
12575 len = TG3_NVM_VPD_LEN;
12576 }
12577
12578 buf = kmalloc(len, GFP_KERNEL);
12579 if (buf == NULL)
12580 return NULL;
12581
12582 if (magic == TG3_EEPROM_MAGIC) {
12583 for (i = 0; i < len; i += 4) {
12584 /* The data is in little-endian format in NVRAM.
12585 * Use the big-endian read routines to preserve
12586 * the byte order as it exists in NVRAM.
12587 */
12588 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12589 goto error;
12590 }
12591 } else {
12592 u8 *ptr;
12593 ssize_t cnt;
12594 unsigned int pos = 0;
12595
12596 ptr = (u8 *)&buf[0];
12597 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12598 cnt = pci_read_vpd(tp->pdev, pos,
12599 len - pos, ptr);
12600 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12601 cnt = 0;
12602 else if (cnt < 0)
12603 goto error;
12604 }
12605 if (pos != len)
12606 goto error;
12607 }
12608
535a490e
MC		 12609 *vpdlen = len;
12610
c3e94500
MC		 12611 return buf;
12612
12613error:
12614 kfree(buf);
12615 return NULL;
12616}
12617
566f86ad 12618#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 12619#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12620#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12621#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
727a6d9f
MC		 12622#define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12623#define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
bda18faf 12624#define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
b16250e3
MC		 12625#define NVRAM_SELFBOOT_HW_SIZE 0x20
12626#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 12627
12628static int tg3_test_nvram(struct tg3 *tp)
12629{
535a490e 12630 u32 csum, magic, len;
a9dc529d 12631 __be32 *buf;
ab0049b4 12632 int i, j, k, err = 0, size;
566f86ad 12633
63c3a66f 12634 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 12635 return 0;
12636
e4f34110 12637 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 12638 return -EIO;
12639
1b27777a
MC		 12640 if (magic == TG3_EEPROM_MAGIC)
12641 size = NVRAM_TEST_SIZE;
b16250e3 12642 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 12643 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12644 TG3_EEPROM_SB_FORMAT_1) {
12645 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12646 case TG3_EEPROM_SB_REVISION_0:
12647 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12648 break;
12649 case TG3_EEPROM_SB_REVISION_2:
12650 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12651 break;
12652 case TG3_EEPROM_SB_REVISION_3:
12653 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12654 break;
727a6d9f
MC		 12655 case TG3_EEPROM_SB_REVISION_4:
12656 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12657 break;
12658 case TG3_EEPROM_SB_REVISION_5:
12659 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12660 break;
12661 case TG3_EEPROM_SB_REVISION_6:
12662 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12663 break;
a5767dec 12664 default:
727a6d9f 12665 return -EIO;
a5767dec
MC		 12666 }
12667 } else
1b27777a 12668 return 0;
b16250e3
MC		 12669 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12670 size = NVRAM_SELFBOOT_HW_SIZE;
12671 else
1b27777a
MC		 12672 return -EIO;
12673
12674 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 12675 if (buf == NULL)
12676 return -ENOMEM;
12677
1b27777a
MC		 12678 err = -EIO;
12679 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 12680 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12681 if (err)
566f86ad 12682 break;
566f86ad 12683 }
1b27777a 12684 if (i < size)
566f86ad
MC		 12685 goto out;
12686
1b27777a 12687 /* Selfboot format */
a9dc529d 12688 magic = be32_to_cpu(buf[0]);
b9fc7dc5 12689 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 12690 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 12691 u8 *buf8 = (u8 *) buf, csum8 = 0;
12692
b9fc7dc5 12693 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 12694 TG3_EEPROM_SB_REVISION_2) {
12695 /* For rev 2, the csum doesn't include the MBA. */
12696 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12697 csum8 += buf8[i];
12698 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12699 csum8 += buf8[i];
12700 } else {
12701 for (i = 0; i < size; i++)
12702 csum8 += buf8[i];
12703 }
1b27777a 12704
ad96b485
AB		 12705 if (csum8 == 0) {
12706 err = 0;
12707 goto out;
12708 }
12709
12710 err = -EIO;
12711 goto out;
1b27777a 12712 }
566f86ad 12713
b9fc7dc5 12714 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 12715 TG3_EEPROM_MAGIC_HW) {
12716 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 12717 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 12718 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 12719
12720 /* Separate the parity bits and the data bytes. */
12721 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12722 if ((i == 0) || (i == 8)) {
12723 int l;
12724 u8 msk;
12725
12726 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12727 parity[k++] = buf8[i] & msk;
12728 i++;
859a5887 12729 } else if (i == 16) {
b16250e3
MC		 12730 int l;
12731 u8 msk;
12732
12733 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12734 parity[k++] = buf8[i] & msk;
12735 i++;
12736
12737 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12738 parity[k++] = buf8[i] & msk;
12739 i++;
12740 }
12741 data[j++] = buf8[i];
12742 }
12743
12744 err = -EIO;
12745 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12746 u8 hw8 = hweight8(data[i]);
12747
12748 if ((hw8 & 0x1) && parity[i])
12749 goto out;
12750 else if (!(hw8 & 0x1) && !parity[i])
12751 goto out;
12752 }
12753 err = 0;
12754 goto out;
12755 }
12756
01c3a392
MC		 12757 err = -EIO;
12758
566f86ad
MC		 12759 /* Bootstrap checksum at offset 0x10 */
12760 csum = calc_crc((unsigned char *) buf, 0x10);
01c3a392 12761 if (csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 12762 goto out;
12763
12764 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12765 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
01c3a392 12766 if (csum != le32_to_cpu(buf[0xfc/4]))
a9dc529d 12767 goto out;
566f86ad 12768
c3e94500
MC		 12769 kfree(buf);
12770
535a490e 12771 buf = tg3_vpd_readblock(tp, &len);
c3e94500
MC		 12772 if (!buf)
12773 return -ENOMEM;
d4894f3e 12774
535a490e 12775 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
d4894f3e
MC		 12776 if (i > 0) {
12777 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12778 if (j < 0)
12779 goto out;
12780
535a490e 12781 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
d4894f3e
MC		 12782 goto out;
12783
12784 i += PCI_VPD_LRDT_TAG_SIZE;
12785 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12786 PCI_VPD_RO_KEYWORD_CHKSUM);
12787 if (j > 0) {
12788 u8 csum8 = 0;
12789
12790 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12791
12792 for (i = 0; i <= j; i++)
12793 csum8 += ((u8 *)buf)[i];
12794
12795 if (csum8)
12796 goto out;
12797 }
12798 }
12799
566f86ad
MC		 12800 err = 0;
12801
12802out:
12803 kfree(buf);
12804 return err;
12805}
12806
ca43007a
MC		 12807#define TG3_SERDES_TIMEOUT_SEC 2
12808#define TG3_COPPER_TIMEOUT_SEC 6
12809
12810static int tg3_test_link(struct tg3 *tp)
12811{
12812 int i, max;
12813
12814 if (!netif_running(tp->dev))
12815 return -ENODEV;
12816
f07e9af3 12817 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
ca43007a
MC		 12818 max = TG3_SERDES_TIMEOUT_SEC;
12819 else
12820 max = TG3_COPPER_TIMEOUT_SEC;
12821
12822 for (i = 0; i < max; i++) {
f4a46d1f 12823 if (tp->link_up)
ca43007a
MC		 12824 return 0;
12825
12826 if (msleep_interruptible(1000))
12827 break;
12828 }
12829
12830 return -EIO;
12831}
12832
a71116d1 12833/* Only test the commonly used registers */
30ca3e37 12834static int tg3_test_registers(struct tg3 *tp)
a71116d1 12835{
b16250e3 12836 int i, is_5705, is_5750;
a71116d1
MC		 12837 u32 offset, read_mask, write_mask, val, save_val, read_val;
12838 static struct {
12839 u16 offset;
12840 u16 flags;
12841#define TG3_FL_5705 0x1
12842#define TG3_FL_NOT_5705 0x2
12843#define TG3_FL_NOT_5788 0x4
b16250e3 12844#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 12845 u32 read_mask;
12846 u32 write_mask;
12847 } reg_tbl[] = {
12848 /* MAC Control Registers */
12849 { MAC_MODE, TG3_FL_NOT_5705,
12850 0x00000000, 0x00ef6f8c },
12851 { MAC_MODE, TG3_FL_5705,
12852 0x00000000, 0x01ef6b8c },
12853 { MAC_STATUS, TG3_FL_NOT_5705,
12854 0x03800107, 0x00000000 },
12855 { MAC_STATUS, TG3_FL_5705,
12856 0x03800100, 0x00000000 },
12857 { MAC_ADDR_0_HIGH, 0x0000,
12858 0x00000000, 0x0000ffff },
12859 { MAC_ADDR_0_LOW, 0x0000,
c6cdf436 12860 0x00000000, 0xffffffff },
a71116d1
MC		 12861 { MAC_RX_MTU_SIZE, 0x0000,
12862 0x00000000, 0x0000ffff },
12863 { MAC_TX_MODE, 0x0000,
12864 0x00000000, 0x00000070 },
12865 { MAC_TX_LENGTHS, 0x0000,
12866 0x00000000, 0x00003fff },
12867 { MAC_RX_MODE, TG3_FL_NOT_5705,
12868 0x00000000, 0x000007fc },
12869 { MAC_RX_MODE, TG3_FL_5705,
12870 0x00000000, 0x000007dc },
12871 { MAC_HASH_REG_0, 0x0000,
12872 0x00000000, 0xffffffff },
12873 { MAC_HASH_REG_1, 0x0000,
12874 0x00000000, 0xffffffff },
12875 { MAC_HASH_REG_2, 0x0000,
12876 0x00000000, 0xffffffff },
12877 { MAC_HASH_REG_3, 0x0000,
12878 0x00000000, 0xffffffff },
12879
12880 /* Receive Data and Receive BD Initiator Control Registers. */
12881 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
12882 0x00000000, 0xffffffff },
12883 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
12884 0x00000000, 0xffffffff },
12885 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
12886 0x00000000, 0x00000003 },
12887 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
12888 0x00000000, 0xffffffff },
12889 { RCVDBDI_STD_BD+0, 0x0000,
12890 0x00000000, 0xffffffff },
12891 { RCVDBDI_STD_BD+4, 0x0000,
12892 0x00000000, 0xffffffff },
12893 { RCVDBDI_STD_BD+8, 0x0000,
12894 0x00000000, 0xffff0002 },
12895 { RCVDBDI_STD_BD+0xc, 0x0000,
12896 0x00000000, 0xffffffff },
6aa20a22 12897
a71116d1
MC		 12898 /* Receive BD Initiator Control Registers. */
12899 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
12900 0x00000000, 0xffffffff },
12901 { RCVBDI_STD_THRESH, TG3_FL_5705,
12902 0x00000000, 0x000003ff },
12903 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
12904 0x00000000, 0xffffffff },
6aa20a22 12905
a71116d1
MC		 12906 /* Host Coalescing Control Registers. */
12907 { HOSTCC_MODE, TG3_FL_NOT_5705,
12908 0x00000000, 0x00000004 },
12909 { HOSTCC_MODE, TG3_FL_5705,
12910 0x00000000, 0x000000f6 },
12911 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
12912 0x00000000, 0xffffffff },
12913 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
12914 0x00000000, 0x000003ff },
12915 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
12916 0x00000000, 0xffffffff },
12917 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
12918 0x00000000, 0x000003ff },
12919 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
12920 0x00000000, 0xffffffff },
12921 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12922 0x00000000, 0x000000ff },
12923 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
12924 0x00000000, 0xffffffff },
12925 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12926 0x00000000, 0x000000ff },
12927 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
12928 0x00000000, 0xffffffff },
12929 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
12930 0x00000000, 0xffffffff },
12931 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12932 0x00000000, 0xffffffff },
12933 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12934 0x00000000, 0x000000ff },
12935 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12936 0x00000000, 0xffffffff },
12937 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12938 0x00000000, 0x000000ff },
12939 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
12940 0x00000000, 0xffffffff },
12941 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
12942 0x00000000, 0xffffffff },
12943 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
12944 0x00000000, 0xffffffff },
12945 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
12946 0x00000000, 0xffffffff },
12947 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
12948 0x00000000, 0xffffffff },
12949 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
12950 0xffffffff, 0x00000000 },
12951 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
12952 0xffffffff, 0x00000000 },
12953
12954 /* Buffer Manager Control Registers. */
b16250e3 12955 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 12956 0x00000000, 0x007fff80 },
b16250e3 12957 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 12958 0x00000000, 0x007fffff },
12959 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
12960 0x00000000, 0x0000003f },
12961 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
12962 0x00000000, 0x000001ff },
12963 { BUFMGR_MB_HIGH_WATER, 0x0000,
12964 0x00000000, 0x000001ff },
12965 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
12966 0xffffffff, 0x00000000 },
12967 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
12968 0xffffffff, 0x00000000 },
6aa20a22 12969
a71116d1
MC		 12970 /* Mailbox Registers */
12971 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
12972 0x00000000, 0x000001ff },
12973 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
12974 0x00000000, 0x000001ff },
12975 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
12976 0x00000000, 0x000007ff },
12977 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
12978 0x00000000, 0x000001ff },
12979
12980 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
12981 };
12982
b16250e3 12983 is_5705 = is_5750 = 0;
63c3a66f 12984 if (tg3_flag(tp, 5705_PLUS)) {
a71116d1 12985 is_5705 = 1;
63c3a66f 12986 if (tg3_flag(tp, 5750_PLUS))
b16250e3
MC		 12987 is_5750 = 1;
12988 }
a71116d1
MC		 12989
12990 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
12991 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
12992 continue;
12993
12994 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
12995 continue;
12996
63c3a66f 12997 if (tg3_flag(tp, IS_5788) &&
a71116d1
MC		 12998 (reg_tbl[i].flags & TG3_FL_NOT_5788))
12999 continue;
13000
b16250e3
MC		 13001 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13002 continue;
13003
a71116d1
MC		 13004 offset = (u32) reg_tbl[i].offset;
13005 read_mask = reg_tbl[i].read_mask;
13006 write_mask = reg_tbl[i].write_mask;
13007
13008 /* Save the original register content */
13009 save_val = tr32(offset);
13010
13011 /* Determine the read-only value. */
13012 read_val = save_val & read_mask;
13013
13014 /* Write zero to the register, then make sure the read-only bits
13015 * are not changed and the read/write bits are all zeros.
13016 */
13017 tw32(offset, 0);
13018
13019 val = tr32(offset);
13020
13021 /* Test the read-only and read/write bits. */
13022 if (((val & read_mask) != read_val) || (val & write_mask))
13023 goto out;
13024
13025 /* Write ones to all the bits defined by RdMask and WrMask, then
13026 * make sure the read-only bits are not changed and the
13027 * read/write bits are all ones.
13028 */
13029 tw32(offset, read_mask | write_mask);
13030
13031 val = tr32(offset);
13032
13033 /* Test the read-only bits. */
13034 if ((val & read_mask) != read_val)
13035 goto out;
13036
13037 /* Test the read/write bits. */
13038 if ((val & write_mask) != write_mask)
13039 goto out;
13040
13041 tw32(offset, save_val);
13042 }
13043
13044 return 0;
13045
13046out:
9f88f29f 13047 if (netif_msg_hw(tp))
2445e461
MC		 13048 netdev_err(tp->dev,
13049 "Register test failed at offset %x\n", offset);
a71116d1
MC		 13050 tw32(offset, save_val);
13051 return -EIO;
13052}
13053
7942e1db
MC		 13054static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13055{
f71e1309 13056 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 13057 int i;
13058 u32 j;
13059
e9edda69 13060 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 13061 for (j = 0; j < len; j += 4) {
13062 u32 val;
13063
13064 tg3_write_mem(tp, offset + j, test_pattern[i]);
13065 tg3_read_mem(tp, offset + j, &val);
13066 if (val != test_pattern[i])
13067 return -EIO;
13068 }
13069 }
13070 return 0;
13071}
13072
13073static int tg3_test_memory(struct tg3 *tp)
13074{
13075 static struct mem_entry {
13076 u32 offset;
13077 u32 len;
13078 } mem_tbl_570x[] = {
38690194 13079 { 0x00000000, 0x00b50},
7942e1db
MC		 13080 { 0x00002000, 0x1c000},
13081 { 0xffffffff, 0x00000}
13082 }, mem_tbl_5705[] = {
13083 { 0x00000100, 0x0000c},
13084 { 0x00000200, 0x00008},
7942e1db
MC		 13085 { 0x00004000, 0x00800},
13086 { 0x00006000, 0x01000},
13087 { 0x00008000, 0x02000},
13088 { 0x00010000, 0x0e000},
13089 { 0xffffffff, 0x00000}
79f4d13a
MC		 13090 }, mem_tbl_5755[] = {
13091 { 0x00000200, 0x00008},
13092 { 0x00004000, 0x00800},
13093 { 0x00006000, 0x00800},
13094 { 0x00008000, 0x02000},
13095 { 0x00010000, 0x0c000},
13096 { 0xffffffff, 0x00000}
b16250e3
MC		 13097 }, mem_tbl_5906[] = {
13098 { 0x00000200, 0x00008},
13099 { 0x00004000, 0x00400},
13100 { 0x00006000, 0x00400},
13101 { 0x00008000, 0x01000},
13102 { 0x00010000, 0x01000},
13103 { 0xffffffff, 0x00000}
8b5a6c42
MC		 13104 }, mem_tbl_5717[] = {
13105 { 0x00000200, 0x00008},
13106 { 0x00010000, 0x0a000},
13107 { 0x00020000, 0x13c00},
13108 { 0xffffffff, 0x00000}
13109 }, mem_tbl_57765[] = {
13110 { 0x00000200, 0x00008},
13111 { 0x00004000, 0x00800},
13112 { 0x00006000, 0x09800},
13113 { 0x00010000, 0x0a000},
13114 { 0xffffffff, 0x00000}
7942e1db
MC		 13115 };
13116 struct mem_entry *mem_tbl;
13117 int err = 0;
13118 int i;
13119
63c3a66f 13120 if (tg3_flag(tp, 5717_PLUS))
8b5a6c42 13121 mem_tbl = mem_tbl_5717;
c65a17f4 13122 else if (tg3_flag(tp, 57765_CLASS) ||
4153577a 13123 tg3_asic_rev(tp) == ASIC_REV_5762)
8b5a6c42 13124 mem_tbl = mem_tbl_57765;
63c3a66f 13125 else if (tg3_flag(tp, 5755_PLUS))
321d32a0 13126 mem_tbl = mem_tbl_5755;
4153577a 13127 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
321d32a0 13128 mem_tbl = mem_tbl_5906;
63c3a66f 13129 else if (tg3_flag(tp, 5705_PLUS))
321d32a0
MC		 13130 mem_tbl = mem_tbl_5705;
13131 else
7942e1db
MC		 13132 mem_tbl = mem_tbl_570x;
13133
13134 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
be98da6a
MC		 13135 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13136 if (err)
7942e1db
MC		 13137 break;
13138 }
6aa20a22 13139
7942e1db
MC		 13140 return err;
13141}
13142
bb158d69
MC		 13143#define TG3_TSO_MSS 500
13144
13145#define TG3_TSO_IP_HDR_LEN 20
13146#define TG3_TSO_TCP_HDR_LEN 20
13147#define TG3_TSO_TCP_OPT_LEN 12
13148
13149static const u8 tg3_tso_header[] = {
131500x08, 0x00,
131510x45, 0x00, 0x00, 0x00,
131520x00, 0x00, 0x40, 0x00,
131530x40, 0x06, 0x00, 0x00,
131540x0a, 0x00, 0x00, 0x01,
131550x0a, 0x00, 0x00, 0x02,
131560x0d, 0x00, 0xe0, 0x00,
131570x00, 0x00, 0x01, 0x00,
131580x00, 0x00, 0x02, 0x00,
131590x80, 0x10, 0x10, 0x00,
131600x14, 0x09, 0x00, 0x00,
131610x01, 0x01, 0x08, 0x0a,
131620x11, 0x11, 0x11, 0x11,
131630x11, 0x11, 0x11, 0x11,
13164};
9f40dead 13165
28a45957 13166static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
c76949a6 13167{
5e5a7f37 13168 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
bb158d69 13169 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
84b67b27 13170 u32 budget;
9205fd9c
ED		 13171 struct sk_buff *skb;
13172 u8 *tx_data, *rx_data;
c76949a6
MC		 13173 dma_addr_t map;
13174 int num_pkts, tx_len, rx_len, i, err;
13175 struct tg3_rx_buffer_desc *desc;
898a56f8 13176 struct tg3_napi *tnapi, *rnapi;
8fea32b9 13177 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
c76949a6 13178
c8873405
MC		 13179 tnapi = &tp->napi[0];
13180 rnapi = &tp->napi[0];
0c1d0e2b 13181 if (tp->irq_cnt > 1) {
63c3a66f 13182 if (tg3_flag(tp, ENABLE_RSS))
1da85aa3 13183 rnapi = &tp->napi[1];
63c3a66f 13184 if (tg3_flag(tp, ENABLE_TSS))
c8873405 13185 tnapi = &tp->napi[1];
0c1d0e2b 13186 }
fd2ce37f 13187 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 13188
c76949a6
MC		 13189 err = -EIO;
13190
4852a861 13191 tx_len = pktsz;
a20e9c62 13192 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 13193 if (!skb)
13194 return -ENOMEM;
13195
c76949a6
MC		 13196 tx_data = skb_put(skb, tx_len);
13197 memcpy(tx_data, tp->dev->dev_addr, 6);
13198 memset(tx_data + 6, 0x0, 8);
13199
4852a861 13200 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
c76949a6 13201
28a45957 13202 if (tso_loopback) {
bb158d69
MC		 13203 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13204
13205 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13206 TG3_TSO_TCP_OPT_LEN;
13207
13208 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13209 sizeof(tg3_tso_header));
13210 mss = TG3_TSO_MSS;
13211
13212 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13213 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13214
13215 /* Set the total length field in the IP header */
13216 iph->tot_len = htons((u16)(mss + hdr_len));
13217
13218 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13219 TXD_FLAG_CPU_POST_DMA);
13220
63c3a66f
JP		 13221 if (tg3_flag(tp, HW_TSO_1) ||
13222 tg3_flag(tp, HW_TSO_2) ||
13223 tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13224 struct tcphdr *th;
13225 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13226 th = (struct tcphdr *)&tx_data[val];
13227 th->check = 0;
13228 } else
13229 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13230
63c3a66f 13231 if (tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13232 mss |= (hdr_len & 0xc) << 12;
13233 if (hdr_len & 0x10)
13234 base_flags |= 0x00000010;
13235 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 13236 } else if (tg3_flag(tp, HW_TSO_2))
bb158d69 13237 mss |= hdr_len << 9;
63c3a66f 13238 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 13239 tg3_asic_rev(tp) == ASIC_REV_5705) {
bb158d69
MC		 13240 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13241 } else {
13242 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13243 }
13244
13245 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13246 } else {
13247 num_pkts = 1;
13248 data_off = ETH_HLEN;
c441b456
MC		 13249
13250 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13251 tx_len > VLAN_ETH_FRAME_LEN)
13252 base_flags |= TXD_FLAG_JMB_PKT;
bb158d69
MC		 13253 }
13254
13255 for (i = data_off; i < tx_len; i++)
c76949a6
MC		 13256 tx_data[i] = (u8) (i & 0xff);
13257
f4188d8a
AD		 13258 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13259 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 13260 dev_kfree_skb(skb);
13261 return -EIO;
13262 }
c76949a6 13263
0d681b27
MC		 13264 val = tnapi->tx_prod;
13265 tnapi->tx_buffers[val].skb = skb;
13266 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13267
c76949a6 13268 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13269 rnapi->coal_now);
c76949a6
MC		 13270
13271 udelay(10);
13272
898a56f8 13273 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 13274
84b67b27
MC		 13275 budget = tg3_tx_avail(tnapi);
13276 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
d1a3b737
MC		 13277 base_flags | TXD_FLAG_END, mss, 0)) {
13278 tnapi->tx_buffers[val].skb = NULL;
13279 dev_kfree_skb(skb);
13280 return -EIO;
13281 }
c76949a6 13282
f3f3f27e 13283 tnapi->tx_prod++;
c76949a6 13284
6541b806
MC		 13285 /* Sync BD data before updating mailbox */
13286 wmb();
13287
f3f3f27e
MC		 13288 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13289 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 13290
13291 udelay(10);
13292
303fc921
MC		 13293 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13294 for (i = 0; i < 35; i++) {
c76949a6 13295 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13296 coal_now);
c76949a6
MC		 13297
13298 udelay(10);
13299
898a56f8
MC		 13300 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13301 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 13302 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 13303 (rx_idx == (rx_start_idx + num_pkts)))
13304 break;
13305 }
13306
ba1142e4 13307 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
c76949a6
MC		 13308 dev_kfree_skb(skb);
13309
f3f3f27e 13310 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 13311 goto out;
13312
13313 if (rx_idx != rx_start_idx + num_pkts)
13314 goto out;
13315
bb158d69
MC		 13316 val = data_off;
13317 while (rx_idx != rx_start_idx) {
13318 desc = &rnapi->rx_rcb[rx_start_idx++];
13319 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13320 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
c76949a6 13321
bb158d69
MC		 13322 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13323 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13324 goto out;
c76949a6 13325
bb158d69
MC		 13326 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13327 - ETH_FCS_LEN;
c76949a6 13328
28a45957 13329 if (!tso_loopback) {
bb158d69
MC		 13330 if (rx_len != tx_len)
13331 goto out;
4852a861 13332
bb158d69
MC		 13333 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13334 if (opaque_key != RXD_OPAQUE_RING_STD)
13335 goto out;
13336 } else {
13337 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13338 goto out;
13339 }
13340 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13341 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
54e0a67f 13342 >> RXD_TCPCSUM_SHIFT != 0xffff) {
4852a861 13343 goto out;
bb158d69 13344 }
4852a861 13345
bb158d69 13346 if (opaque_key == RXD_OPAQUE_RING_STD) {
9205fd9c 13347 rx_data = tpr->rx_std_buffers[desc_idx].data;
bb158d69
MC		 13348 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13349 mapping);
13350 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
9205fd9c 13351 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
bb158d69
MC		 13352 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13353 mapping);
13354 } else
13355 goto out;
c76949a6 13356
bb158d69
MC		 13357 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13358 PCI_DMA_FROMDEVICE);
c76949a6 13359
9205fd9c 13360 rx_data += TG3_RX_OFFSET(tp);
bb158d69 13361 for (i = data_off; i < rx_len; i++, val++) {
9205fd9c 13362 if (*(rx_data + i) != (u8) (val & 0xff))
bb158d69
MC		 13363 goto out;
13364 }
c76949a6 13365 }
bb158d69 13366
c76949a6 13367 err = 0;
6aa20a22 13368
9205fd9c 13369 /* tg3_free_rings will unmap and free the rx_data */
c76949a6
MC		 13370out:
13371 return err;
13372}
13373
00c266b7
MC		 13374#define TG3_STD_LOOPBACK_FAILED 1
13375#define TG3_JMB_LOOPBACK_FAILED 2
bb158d69 13376#define TG3_TSO_LOOPBACK_FAILED 4
28a45957
MC		 13377#define TG3_LOOPBACK_FAILED \
13378 (TG3_STD_LOOPBACK_FAILED | \
13379 TG3_JMB_LOOPBACK_FAILED | \
13380 TG3_TSO_LOOPBACK_FAILED)
00c266b7 13381
941ec90f 13382static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
9f40dead 13383{
28a45957 13384 int err = -EIO;
2215e24c 13385 u32 eee_cap;
c441b456
MC		 13386 u32 jmb_pkt_sz = 9000;
13387
13388 if (tp->dma_limit)
13389 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
9f40dead 13390
ab789046
MC		 13391 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13392 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13393
28a45957 13394 if (!netif_running(tp->dev)) {
93df8b8f
NNS		 13395 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13396 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13397 if (do_extlpbk)
93df8b8f 13398 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
28a45957
MC		 13399 goto done;
13400 }
13401
953c96e0 13402 err = tg3_reset_hw(tp, true);
ab789046 13403 if (err) {
93df8b8f
NNS		 13404 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13405 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13406 if (do_extlpbk)
93df8b8f 13407 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
ab789046
MC		 13408 goto done;
13409 }
9f40dead 13410
63c3a66f 13411 if (tg3_flag(tp, ENABLE_RSS)) {
4a85f098
MC		 13412 int i;
13413
13414 /* Reroute all rx packets to the 1st queue */
13415 for (i = MAC_RSS_INDIR_TBL_0;
13416 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13417 tw32(i, 0x0);
13418 }
13419
6e01b20b
MC		 13420 /* HW errata - mac loopback fails in some cases on 5780.
13421 * Normal traffic and PHY loopback are not affected by
13422 * errata. Also, the MAC loopback test is deprecated for
13423 * all newer ASIC revisions.
13424 */
4153577a 13425 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
6e01b20b
MC		 13426 !tg3_flag(tp, CPMU_PRESENT)) {
13427 tg3_mac_loopback(tp, true);
9936bcf6 13428
28a45957 13429 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13430 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
6e01b20b
MC		 13431
13432 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13433 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13434 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
6e01b20b
MC		 13435
13436 tg3_mac_loopback(tp, false);
13437 }
4852a861 13438
f07e9af3 13439 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
63c3a66f 13440 !tg3_flag(tp, USE_PHYLIB)) {
5e5a7f37
MC		 13441 int i;
13442
941ec90f 13443 tg3_phy_lpbk_set(tp, 0, false);
5e5a7f37
MC		 13444
13445 /* Wait for link */
13446 for (i = 0; i < 100; i++) {
13447 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13448 break;
13449 mdelay(1);
13450 }
13451
28a45957 13452 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13453 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
63c3a66f 13454 if (tg3_flag(tp, TSO_CAPABLE) &&
28a45957 13455 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f 13456 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
63c3a66f 13457 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13458 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13459 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
9f40dead 13460
941ec90f
MC		 13461 if (do_extlpbk) {
13462 tg3_phy_lpbk_set(tp, 0, true);
13463
13464 /* All link indications report up, but the hardware
13465 * isn't really ready for about 20 msec. Double it
13466 * to be sure.
13467 */
13468 mdelay(40);
13469
13470 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f
NNS		 13471 data[TG3_EXT_LOOPB_TEST] |=
13472 TG3_STD_LOOPBACK_FAILED;
941ec90f
MC		 13473 if (tg3_flag(tp, TSO_CAPABLE) &&
13474 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f
NNS		 13475 data[TG3_EXT_LOOPB_TEST] |=
13476 TG3_TSO_LOOPBACK_FAILED;
941ec90f 13477 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13478 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f
NNS		 13479 data[TG3_EXT_LOOPB_TEST] |=
13480 TG3_JMB_LOOPBACK_FAILED;
941ec90f
MC		 13481 }
13482
5e5a7f37
MC		 13483 /* Re-enable gphy autopowerdown. */
13484 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13485 tg3_phy_toggle_apd(tp, true);
13486 }
6833c043 13487
93df8b8f
NNS		 13488 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13489 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
28a45957 13490
ab789046
MC		 13491done:
13492 tp->phy_flags |= eee_cap;
13493
9f40dead
MC		 13494 return err;
13495}
13496
4cafd3f5
MC		 13497static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13498 u64 *data)
13499{
566f86ad 13500 struct tg3 *tp = netdev_priv(dev);
941ec90f 13501 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
566f86ad 13502
2e460fc0
NS		 13503 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13504 if (tg3_power_up(tp)) {
13505 etest->flags |= ETH_TEST_FL_FAILED;
13506 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13507 return;
13508 }
13509 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
bed9829f 13510 }
bc1c7567 13511
566f86ad
MC		 13512 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13513
13514 if (tg3_test_nvram(tp) != 0) {
13515 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13516 data[TG3_NVRAM_TEST] = 1;
566f86ad 13517 }
941ec90f 13518 if (!doextlpbk && tg3_test_link(tp)) {
ca43007a 13519 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13520 data[TG3_LINK_TEST] = 1;
ca43007a 13521 }
a71116d1 13522 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 13523 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 13524
13525 if (netif_running(dev)) {
b02fd9e3 13526 tg3_phy_stop(tp);
a71116d1 13527 tg3_netif_stop(tp);
bbe832c0
MC		 13528 irq_sync = 1;
13529 }
a71116d1 13530
bbe832c0 13531 tg3_full_lock(tp, irq_sync);
a71116d1 13532 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 13533 err = tg3_nvram_lock(tp);
a71116d1 13534 tg3_halt_cpu(tp, RX_CPU_BASE);
63c3a66f 13535 if (!tg3_flag(tp, 5705_PLUS))
a71116d1 13536 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 13537 if (!err)
13538 tg3_nvram_unlock(tp);
a71116d1 13539
f07e9af3 13540 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
d9ab5ad1
MC		 13541 tg3_phy_reset(tp);
13542
a71116d1
MC		 13543 if (tg3_test_registers(tp) != 0) {
13544 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13545 data[TG3_REGISTER_TEST] = 1;
a71116d1 13546 }
28a45957 13547
7942e1db
MC		 13548 if (tg3_test_memory(tp) != 0) {
13549 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13550 data[TG3_MEMORY_TEST] = 1;
7942e1db 13551 }
28a45957 13552
941ec90f
MC		 13553 if (doextlpbk)
13554 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13555
93df8b8f 13556 if (tg3_test_loopback(tp, data, doextlpbk))
c76949a6 13557 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 13558
f47c11ee
DM		 13559 tg3_full_unlock(tp);
13560
d4bc3927
MC		 13561 if (tg3_test_interrupt(tp) != 0) {
13562 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13563 data[TG3_INTERRUPT_TEST] = 1;
d4bc3927 13564 }
f47c11ee
DM		 13565
13566 tg3_full_lock(tp, 0);
d4bc3927 13567
a71116d1
MC		 13568 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13569 if (netif_running(dev)) {
63c3a66f 13570 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 13571 err2 = tg3_restart_hw(tp, true);
b02fd9e3 13572 if (!err2)
b9ec6c1b 13573 tg3_netif_start(tp);
a71116d1 13574 }
f47c11ee
DM		 13575
13576 tg3_full_unlock(tp);
b02fd9e3
MC		 13577
13578 if (irq_sync && !err2)
13579 tg3_phy_start(tp);
a71116d1 13580 }
80096068 13581 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
5137a2ee 13582 tg3_power_down_prepare(tp);
bc1c7567 13583
4cafd3f5
MC		 13584}
13585
0a633ac2
MC		 13586static int tg3_hwtstamp_ioctl(struct net_device *dev,
13587 struct ifreq *ifr, int cmd)
13588{
13589 struct tg3 *tp = netdev_priv(dev);
13590 struct hwtstamp_config stmpconf;
13591
13592 if (!tg3_flag(tp, PTP_CAPABLE))
13593 return -EINVAL;
13594
13595 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13596 return -EFAULT;
13597
13598 if (stmpconf.flags)
13599 return -EINVAL;
13600
13601 switch (stmpconf.tx_type) {
13602 case HWTSTAMP_TX_ON:
13603 tg3_flag_set(tp, TX_TSTAMP_EN);
13604 break;
13605 case HWTSTAMP_TX_OFF:
13606 tg3_flag_clear(tp, TX_TSTAMP_EN);
13607 break;
13608 default:
13609 return -ERANGE;
13610 }
13611
13612 switch (stmpconf.rx_filter) {
13613 case HWTSTAMP_FILTER_NONE:
13614 tp->rxptpctl = 0;
13615 break;
13616 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13617 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13618 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13619 break;
13620 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13621 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13622 TG3_RX_PTP_CTL_SYNC_EVNT;
13623 break;
13624 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13625 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13626 TG3_RX_PTP_CTL_DELAY_REQ;
13627 break;
13628 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13629 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13630 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13631 break;
13632 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13633 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13634 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13635 break;
13636 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13637 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13638 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13639 break;
13640 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13641 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13642 TG3_RX_PTP_CTL_SYNC_EVNT;
13643 break;
13644 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13645 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13646 TG3_RX_PTP_CTL_SYNC_EVNT;
13647 break;
13648 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13649 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13650 TG3_RX_PTP_CTL_SYNC_EVNT;
13651 break;
13652 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13653 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13654 TG3_RX_PTP_CTL_DELAY_REQ;
13655 break;
13656 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13657 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13658 TG3_RX_PTP_CTL_DELAY_REQ;
13659 break;
13660 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13661 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13662 TG3_RX_PTP_CTL_DELAY_REQ;
13663 break;
13664 default:
13665 return -ERANGE;
13666 }
13667
13668 if (netif_running(dev) && tp->rxptpctl)
13669 tw32(TG3_RX_PTP_CTL,
13670 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13671
13672 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13673 -EFAULT : 0;
13674}
13675
1da177e4
LT		 13676static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13677{
13678 struct mii_ioctl_data *data = if_mii(ifr);
13679 struct tg3 *tp = netdev_priv(dev);
13680 int err;
13681
63c3a66f 13682 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 13683 struct phy_device *phydev;
f07e9af3 13684 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 13685 return -EAGAIN;
3f0e3ad7 13686 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
28b04113 13687 return phy_mii_ioctl(phydev, ifr, cmd);
b02fd9e3
MC		 13688 }
13689
33f401ae 13690 switch (cmd) {
1da177e4 13691 case SIOCGMIIPHY:
882e9793 13692 data->phy_id = tp->phy_addr;
1da177e4
LT		 13693
13694 /* fallthru */
13695 case SIOCGMIIREG: {
13696 u32 mii_regval;
13697
f07e9af3 13698 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13699 break; /* We have no PHY */
13700
34eea5ac 13701 if (!netif_running(dev))
bc1c7567
MC		 13702 return -EAGAIN;
13703
f47c11ee 13704 spin_lock_bh(&tp->lock);
5c358045
HM		 13705 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13706 data->reg_num & 0x1f, &mii_regval);
f47c11ee 13707 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13708
13709 data->val_out = mii_regval;
13710
13711 return err;
13712 }
13713
13714 case SIOCSMIIREG:
f07e9af3 13715 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13716 break; /* We have no PHY */
13717
34eea5ac 13718 if (!netif_running(dev))
bc1c7567
MC		 13719 return -EAGAIN;
13720
f47c11ee 13721 spin_lock_bh(&tp->lock);
5c358045
HM		 13722 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13723 data->reg_num & 0x1f, data->val_in);
f47c11ee 13724 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13725
13726 return err;
13727
0a633ac2
MC		 13728 case SIOCSHWTSTAMP:
13729 return tg3_hwtstamp_ioctl(dev, ifr, cmd);
13730
1da177e4
LT		 13731 default:
13732 /* do nothing */
13733 break;
13734 }
13735 return -EOPNOTSUPP;
13736}
13737
15f9850d
DM		 13738static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13739{
13740 struct tg3 *tp = netdev_priv(dev);
13741
13742 memcpy(ec, &tp->coal, sizeof(*ec));
13743 return 0;
13744}
13745
d244c892
MC		 13746static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13747{
13748 struct tg3 *tp = netdev_priv(dev);
13749 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13750 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13751
63c3a66f 13752 if (!tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 13753 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13754 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13755 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13756 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13757 }
13758
13759 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13760 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13761 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13762 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13763 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13764 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13765 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13766 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13767 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13768 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13769 return -EINVAL;
13770
13771 /* No rx interrupts will be generated if both are zero */
13772 if ((ec->rx_coalesce_usecs == 0) &&
13773 (ec->rx_max_coalesced_frames == 0))
13774 return -EINVAL;
13775
13776 /* No tx interrupts will be generated if both are zero */
13777 if ((ec->tx_coalesce_usecs == 0) &&
13778 (ec->tx_max_coalesced_frames == 0))
13779 return -EINVAL;
13780
13781 /* Only copy relevant parameters, ignore all others. */
13782 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
13783 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
13784 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
13785 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
13786 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
13787 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
13788 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
13789 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
13790 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
13791
13792 if (netif_running(dev)) {
13793 tg3_full_lock(tp, 0);
13794 __tg3_set_coalesce(tp, &tp->coal);
13795 tg3_full_unlock(tp);
13796 }
13797 return 0;
13798}
13799
1cbf9eb8
NS		 13800static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
13801{
13802 struct tg3 *tp = netdev_priv(dev);
13803
13804 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13805 netdev_warn(tp->dev, "Board does not support EEE!\n");
13806 return -EOPNOTSUPP;
13807 }
13808
13809 if (edata->advertised != tp->eee.advertised) {
13810 netdev_warn(tp->dev,
13811 "Direct manipulation of EEE advertisement is not supported\n");
13812 return -EINVAL;
13813 }
13814
13815 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
13816 netdev_warn(tp->dev,
13817 "Maximal Tx Lpi timer supported is %#x(u)\n",
13818 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
13819 return -EINVAL;
13820 }
13821
13822 tp->eee = *edata;
13823
13824 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
13825 tg3_warn_mgmt_link_flap(tp);
13826
13827 if (netif_running(tp->dev)) {
13828 tg3_full_lock(tp, 0);
13829 tg3_setup_eee(tp);
13830 tg3_phy_reset(tp);
13831 tg3_full_unlock(tp);
13832 }
13833
13834 return 0;
13835}
13836
13837static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
13838{
13839 struct tg3 *tp = netdev_priv(dev);
13840
13841 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13842 netdev_warn(tp->dev,
13843 "Board does not support EEE!\n");
13844 return -EOPNOTSUPP;
13845 }
13846
13847 *edata = tp->eee;
13848 return 0;
13849}
13850
7282d491 13851static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 13852 .get_settings = tg3_get_settings,
13853 .set_settings = tg3_set_settings,
13854 .get_drvinfo = tg3_get_drvinfo,
13855 .get_regs_len = tg3_get_regs_len,
13856 .get_regs = tg3_get_regs,
13857 .get_wol = tg3_get_wol,
13858 .set_wol = tg3_set_wol,
13859 .get_msglevel = tg3_get_msglevel,
13860 .set_msglevel = tg3_set_msglevel,
13861 .nway_reset = tg3_nway_reset,
13862 .get_link = ethtool_op_get_link,
13863 .get_eeprom_len = tg3_get_eeprom_len,
13864 .get_eeprom = tg3_get_eeprom,
13865 .set_eeprom = tg3_set_eeprom,
13866 .get_ringparam = tg3_get_ringparam,
13867 .set_ringparam = tg3_set_ringparam,
13868 .get_pauseparam = tg3_get_pauseparam,
13869 .set_pauseparam = tg3_set_pauseparam,
4cafd3f5 13870 .self_test = tg3_self_test,
1da177e4 13871 .get_strings = tg3_get_strings,
81b8709c 13872 .set_phys_id = tg3_set_phys_id,
1da177e4 13873 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 13874 .get_coalesce = tg3_get_coalesce,
d244c892 13875 .set_coalesce = tg3_set_coalesce,
b9f2c044 13876 .get_sset_count = tg3_get_sset_count,
90415477
MC		 13877 .get_rxnfc = tg3_get_rxnfc,
13878 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
13879 .get_rxfh_indir = tg3_get_rxfh_indir,
13880 .set_rxfh_indir = tg3_set_rxfh_indir,
0968169c
MC		 13881 .get_channels = tg3_get_channels,
13882 .set_channels = tg3_set_channels,
7d41e49a 13883 .get_ts_info = tg3_get_ts_info,
1cbf9eb8
NS		 13884 .get_eee = tg3_get_eee,
13885 .set_eee = tg3_set_eee,
1da177e4
LT		 13886};
13887
b4017c53
DM		 13888static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
13889 struct rtnl_link_stats64 *stats)
13890{
13891 struct tg3 *tp = netdev_priv(dev);
13892
0f566b20
MC		 13893 spin_lock_bh(&tp->lock);
13894 if (!tp->hw_stats) {
13895 spin_unlock_bh(&tp->lock);
b4017c53 13896 return &tp->net_stats_prev;
0f566b20 13897 }
b4017c53 13898
b4017c53
DM		 13899 tg3_get_nstats(tp, stats);
13900 spin_unlock_bh(&tp->lock);
13901
13902 return stats;
13903}
13904
ccd5ba9d
MC		 13905static void tg3_set_rx_mode(struct net_device *dev)
13906{
13907 struct tg3 *tp = netdev_priv(dev);
13908
13909 if (!netif_running(dev))
13910 return;
13911
13912 tg3_full_lock(tp, 0);
13913 __tg3_set_rx_mode(dev);
13914 tg3_full_unlock(tp);
13915}
13916
faf1627a
MC		 13917static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
13918 int new_mtu)
13919{
13920 dev->mtu = new_mtu;
13921
13922 if (new_mtu > ETH_DATA_LEN) {
13923 if (tg3_flag(tp, 5780_CLASS)) {
13924 netdev_update_features(dev);
13925 tg3_flag_clear(tp, TSO_CAPABLE);
13926 } else {
13927 tg3_flag_set(tp, JUMBO_RING_ENABLE);
13928 }
13929 } else {
13930 if (tg3_flag(tp, 5780_CLASS)) {
13931 tg3_flag_set(tp, TSO_CAPABLE);
13932 netdev_update_features(dev);
13933 }
13934 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
13935 }
13936}
13937
13938static int tg3_change_mtu(struct net_device *dev, int new_mtu)
13939{
13940 struct tg3 *tp = netdev_priv(dev);
953c96e0
JP		 13941 int err;
13942 bool reset_phy = false;
faf1627a
MC		 13943
13944 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
13945 return -EINVAL;
13946
13947 if (!netif_running(dev)) {
13948 /* We'll just catch it later when the
13949 * device is up'd.
13950 */
13951 tg3_set_mtu(dev, tp, new_mtu);
13952 return 0;
13953 }
13954
13955 tg3_phy_stop(tp);
13956
13957 tg3_netif_stop(tp);
13958
13959 tg3_full_lock(tp, 1);
13960
13961 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13962
13963 tg3_set_mtu(dev, tp, new_mtu);
13964
2fae5e36
MC		 13965 /* Reset PHY, otherwise the read DMA engine will be in a mode that
13966 * breaks all requests to 256 bytes.
13967 */
4153577a 13968 if (tg3_asic_rev(tp) == ASIC_REV_57766)
953c96e0 13969 reset_phy = true;
2fae5e36
MC		 13970
13971 err = tg3_restart_hw(tp, reset_phy);
faf1627a
MC		 13972
13973 if (!err)
13974 tg3_netif_start(tp);
13975
13976 tg3_full_unlock(tp);
13977
13978 if (!err)
13979 tg3_phy_start(tp);
13980
13981 return err;
13982}
13983
13984static const struct net_device_ops tg3_netdev_ops = {
13985 .ndo_open = tg3_open,
13986 .ndo_stop = tg3_close,
13987 .ndo_start_xmit = tg3_start_xmit,
13988 .ndo_get_stats64 = tg3_get_stats64,
13989 .ndo_validate_addr = eth_validate_addr,
13990 .ndo_set_rx_mode = tg3_set_rx_mode,
13991 .ndo_set_mac_address = tg3_set_mac_addr,
13992 .ndo_do_ioctl = tg3_ioctl,
13993 .ndo_tx_timeout = tg3_tx_timeout,
13994 .ndo_change_mtu = tg3_change_mtu,
13995 .ndo_fix_features = tg3_fix_features,
13996 .ndo_set_features = tg3_set_features,
13997#ifdef CONFIG_NET_POLL_CONTROLLER
13998 .ndo_poll_controller = tg3_poll_controller,
13999#endif
14000};
14001
229b1ad1 14002static void tg3_get_eeprom_size(struct tg3 *tp)
1da177e4 14003{
1b27777a 14004 u32 cursize, val, magic;
1da177e4
LT		 14005
14006 tp->nvram_size = EEPROM_CHIP_SIZE;
14007
e4f34110 14008 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 14009 return;
14010
b16250e3
MC		 14011 if ((magic != TG3_EEPROM_MAGIC) &&
14012 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14013 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 14014 return;
14015
14016 /*
14017 * Size the chip by reading offsets at increasing powers of two.
14018 * When we encounter our validation signature, we know the addressing
14019 * has wrapped around, and thus have our chip size.
14020 */
1b27777a 14021 cursize = 0x10;
1da177e4
LT		 14022
14023 while (cursize < tp->nvram_size) {
e4f34110 14024 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 14025 return;
14026
1820180b 14027 if (val == magic)
1da177e4
LT		 14028 break;
14029
14030 cursize <<= 1;
14031 }
14032
14033 tp->nvram_size = cursize;
14034}
6aa20a22 14035
229b1ad1 14036static void tg3_get_nvram_size(struct tg3 *tp)
1da177e4
LT		 14037{
14038 u32 val;
14039
63c3a66f 14040 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 14041 return;
14042
14043 /* Selfboot format */
1820180b 14044 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 14045 tg3_get_eeprom_size(tp);
14046 return;
14047 }
14048
6d348f2c 14049 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 14050 if (val != 0) {
6d348f2c
MC		 14051 /* This is confusing. We want to operate on the
14052 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14053 * call will read from NVRAM and byteswap the data
14054 * according to the byteswapping settings for all
14055 * other register accesses. This ensures the data we
14056 * want will always reside in the lower 16-bits.
14057 * However, the data in NVRAM is in LE format, which
14058 * means the data from the NVRAM read will always be
14059 * opposite the endianness of the CPU. The 16-bit
14060 * byteswap then brings the data to CPU endianness.
14061 */
14062 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 14063 return;
14064 }
14065 }
fd1122a2 14066 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 14067}
14068
229b1ad1 14069static void tg3_get_nvram_info(struct tg3 *tp)
1da177e4
LT		 14070{
14071 u32 nvcfg1;
14072
14073 nvcfg1 = tr32(NVRAM_CFG1);
14074 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
63c3a66f 14075 tg3_flag_set(tp, FLASH);
8590a603 14076 } else {
1da177e4
LT		 14077 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14078 tw32(NVRAM_CFG1, nvcfg1);
14079 }
14080
4153577a 14081 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
63c3a66f 14082 tg3_flag(tp, 5780_CLASS)) {
1da177e4 14083 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 14084 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14085 tp->nvram_jedecnum = JEDEC_ATMEL;
14086 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14087 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14088 break;
14089 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14090 tp->nvram_jedecnum = JEDEC_ATMEL;
14091 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14092 break;
14093 case FLASH_VENDOR_ATMEL_EEPROM:
14094 tp->nvram_jedecnum = JEDEC_ATMEL;
14095 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
63c3a66f 14096 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14097 break;
14098 case FLASH_VENDOR_ST:
14099 tp->nvram_jedecnum = JEDEC_ST;
14100 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
63c3a66f 14101 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14102 break;
14103 case FLASH_VENDOR_SAIFUN:
14104 tp->nvram_jedecnum = JEDEC_SAIFUN;
14105 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14106 break;
14107 case FLASH_VENDOR_SST_SMALL:
14108 case FLASH_VENDOR_SST_LARGE:
14109 tp->nvram_jedecnum = JEDEC_SST;
14110 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14111 break;
1da177e4 14112 }
8590a603 14113 } else {
1da177e4
LT		 14114 tp->nvram_jedecnum = JEDEC_ATMEL;
14115 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14116 tg3_flag_set(tp, NVRAM_BUFFERED);
1da177e4
LT		 14117 }
14118}
14119
229b1ad1 14120static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
a1b950d5
MC		 14121{
14122 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14123 case FLASH_5752PAGE_SIZE_256:
14124 tp->nvram_pagesize = 256;
14125 break;
14126 case FLASH_5752PAGE_SIZE_512:
14127 tp->nvram_pagesize = 512;
14128 break;
14129 case FLASH_5752PAGE_SIZE_1K:
14130 tp->nvram_pagesize = 1024;
14131 break;
14132 case FLASH_5752PAGE_SIZE_2K:
14133 tp->nvram_pagesize = 2048;
14134 break;
14135 case FLASH_5752PAGE_SIZE_4K:
14136 tp->nvram_pagesize = 4096;
14137 break;
14138 case FLASH_5752PAGE_SIZE_264:
14139 tp->nvram_pagesize = 264;
14140 break;
14141 case FLASH_5752PAGE_SIZE_528:
14142 tp->nvram_pagesize = 528;
14143 break;
14144 }
14145}
14146
229b1ad1 14147static void tg3_get_5752_nvram_info(struct tg3 *tp)
361b4ac2
MC		 14148{
14149 u32 nvcfg1;
14150
14151 nvcfg1 = tr32(NVRAM_CFG1);
14152
e6af301b
MC		 14153 /* NVRAM protection for TPM */
14154 if (nvcfg1 & (1 << 27))
63c3a66f 14155 tg3_flag_set(tp, PROTECTED_NVRAM);
e6af301b 14156
361b4ac2 14157 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14158 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14159 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14160 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14161 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14162 break;
14163 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14164 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14165 tg3_flag_set(tp, NVRAM_BUFFERED);
14166 tg3_flag_set(tp, FLASH);
8590a603
MC		 14167 break;
14168 case FLASH_5752VENDOR_ST_M45PE10:
14169 case FLASH_5752VENDOR_ST_M45PE20:
14170 case FLASH_5752VENDOR_ST_M45PE40:
14171 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14172 tg3_flag_set(tp, NVRAM_BUFFERED);
14173 tg3_flag_set(tp, FLASH);
8590a603 14174 break;
361b4ac2
MC		 14175 }
14176
63c3a66f 14177 if (tg3_flag(tp, FLASH)) {
a1b950d5 14178 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 14179 } else {
361b4ac2
MC		 14180 /* For eeprom, set pagesize to maximum eeprom size */
14181 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14182
14183 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14184 tw32(NVRAM_CFG1, nvcfg1);
14185 }
14186}
14187
229b1ad1 14188static void tg3_get_5755_nvram_info(struct tg3 *tp)
d3c7b886 14189{
989a9d23 14190 u32 nvcfg1, protect = 0;
d3c7b886
MC		 14191
14192 nvcfg1 = tr32(NVRAM_CFG1);
14193
14194 /* NVRAM protection for TPM */
989a9d23 14195 if (nvcfg1 & (1 << 27)) {
63c3a66f 14196 tg3_flag_set(tp, PROTECTED_NVRAM);
989a9d23
MC		 14197 protect = 1;
14198 }
d3c7b886 14199
989a9d23
MC		 14200 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14201 switch (nvcfg1) {
8590a603
MC		 14202 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14203 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14204 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14205 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14206 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14207 tg3_flag_set(tp, NVRAM_BUFFERED);
14208 tg3_flag_set(tp, FLASH);
8590a603
MC		 14209 tp->nvram_pagesize = 264;
14210 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14211 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14212 tp->nvram_size = (protect ? 0x3e200 :
14213 TG3_NVRAM_SIZE_512KB);
14214 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14215 tp->nvram_size = (protect ? 0x1f200 :
14216 TG3_NVRAM_SIZE_256KB);
14217 else
14218 tp->nvram_size = (protect ? 0x1f200 :
14219 TG3_NVRAM_SIZE_128KB);
14220 break;
14221 case FLASH_5752VENDOR_ST_M45PE10:
14222 case FLASH_5752VENDOR_ST_M45PE20:
14223 case FLASH_5752VENDOR_ST_M45PE40:
14224 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14225 tg3_flag_set(tp, NVRAM_BUFFERED);
14226 tg3_flag_set(tp, FLASH);
8590a603
MC		 14227 tp->nvram_pagesize = 256;
14228 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14229 tp->nvram_size = (protect ?
14230 TG3_NVRAM_SIZE_64KB :
14231 TG3_NVRAM_SIZE_128KB);
14232 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14233 tp->nvram_size = (protect ?
14234 TG3_NVRAM_SIZE_64KB :
14235 TG3_NVRAM_SIZE_256KB);
14236 else
14237 tp->nvram_size = (protect ?
14238 TG3_NVRAM_SIZE_128KB :
14239 TG3_NVRAM_SIZE_512KB);
14240 break;
d3c7b886
MC		 14241 }
14242}
14243
229b1ad1 14244static void tg3_get_5787_nvram_info(struct tg3 *tp)
1b27777a
MC		 14245{
14246 u32 nvcfg1;
14247
14248 nvcfg1 = tr32(NVRAM_CFG1);
14249
14250 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14251 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14252 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14253 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14254 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14255 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14256 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603 14257 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 14258
8590a603
MC		 14259 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14260 tw32(NVRAM_CFG1, nvcfg1);
14261 break;
14262 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14263 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14264 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14265 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14266 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14267 tg3_flag_set(tp, NVRAM_BUFFERED);
14268 tg3_flag_set(tp, FLASH);
8590a603
MC		 14269 tp->nvram_pagesize = 264;
14270 break;
14271 case FLASH_5752VENDOR_ST_M45PE10:
14272 case FLASH_5752VENDOR_ST_M45PE20:
14273 case FLASH_5752VENDOR_ST_M45PE40:
14274 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14275 tg3_flag_set(tp, NVRAM_BUFFERED);
14276 tg3_flag_set(tp, FLASH);
8590a603
MC		 14277 tp->nvram_pagesize = 256;
14278 break;
1b27777a
MC		 14279 }
14280}
14281
229b1ad1 14282static void tg3_get_5761_nvram_info(struct tg3 *tp)
6b91fa02
MC		 14283{
14284 u32 nvcfg1, protect = 0;
14285
14286 nvcfg1 = tr32(NVRAM_CFG1);
14287
14288 /* NVRAM protection for TPM */
14289 if (nvcfg1 & (1 << 27)) {
63c3a66f 14290 tg3_flag_set(tp, PROTECTED_NVRAM);
6b91fa02
MC		 14291 protect = 1;
14292 }
14293
14294 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14295 switch (nvcfg1) {
8590a603
MC		 14296 case FLASH_5761VENDOR_ATMEL_ADB021D:
14297 case FLASH_5761VENDOR_ATMEL_ADB041D:
14298 case FLASH_5761VENDOR_ATMEL_ADB081D:
14299 case FLASH_5761VENDOR_ATMEL_ADB161D:
14300 case FLASH_5761VENDOR_ATMEL_MDB021D:
14301 case FLASH_5761VENDOR_ATMEL_MDB041D:
14302 case FLASH_5761VENDOR_ATMEL_MDB081D:
14303 case FLASH_5761VENDOR_ATMEL_MDB161D:
14304 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14305 tg3_flag_set(tp, NVRAM_BUFFERED);
14306 tg3_flag_set(tp, FLASH);
14307 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
8590a603
MC		 14308 tp->nvram_pagesize = 256;
14309 break;
14310 case FLASH_5761VENDOR_ST_A_M45PE20:
14311 case FLASH_5761VENDOR_ST_A_M45PE40:
14312 case FLASH_5761VENDOR_ST_A_M45PE80:
14313 case FLASH_5761VENDOR_ST_A_M45PE16:
14314 case FLASH_5761VENDOR_ST_M_M45PE20:
14315 case FLASH_5761VENDOR_ST_M_M45PE40:
14316 case FLASH_5761VENDOR_ST_M_M45PE80:
14317 case FLASH_5761VENDOR_ST_M_M45PE16:
14318 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14319 tg3_flag_set(tp, NVRAM_BUFFERED);
14320 tg3_flag_set(tp, FLASH);
8590a603
MC		 14321 tp->nvram_pagesize = 256;
14322 break;
6b91fa02
MC		 14323 }
14324
14325 if (protect) {
14326 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14327 } else {
14328 switch (nvcfg1) {
8590a603
MC		 14329 case FLASH_5761VENDOR_ATMEL_ADB161D:
14330 case FLASH_5761VENDOR_ATMEL_MDB161D:
14331 case FLASH_5761VENDOR_ST_A_M45PE16:
14332 case FLASH_5761VENDOR_ST_M_M45PE16:
14333 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14334 break;
14335 case FLASH_5761VENDOR_ATMEL_ADB081D:
14336 case FLASH_5761VENDOR_ATMEL_MDB081D:
14337 case FLASH_5761VENDOR_ST_A_M45PE80:
14338 case FLASH_5761VENDOR_ST_M_M45PE80:
14339 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14340 break;
14341 case FLASH_5761VENDOR_ATMEL_ADB041D:
14342 case FLASH_5761VENDOR_ATMEL_MDB041D:
14343 case FLASH_5761VENDOR_ST_A_M45PE40:
14344 case FLASH_5761VENDOR_ST_M_M45PE40:
14345 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14346 break;
14347 case FLASH_5761VENDOR_ATMEL_ADB021D:
14348 case FLASH_5761VENDOR_ATMEL_MDB021D:
14349 case FLASH_5761VENDOR_ST_A_M45PE20:
14350 case FLASH_5761VENDOR_ST_M_M45PE20:
14351 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14352 break;
6b91fa02
MC		 14353 }
14354 }
14355}
14356
229b1ad1 14357static void tg3_get_5906_nvram_info(struct tg3 *tp)
b5d3772c
MC		 14358{
14359 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14360 tg3_flag_set(tp, NVRAM_BUFFERED);
b5d3772c
MC		 14361 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14362}
14363
229b1ad1 14364static void tg3_get_57780_nvram_info(struct tg3 *tp)
321d32a0
MC		 14365{
14366 u32 nvcfg1;
14367
14368 nvcfg1 = tr32(NVRAM_CFG1);
14369
14370 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14371 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14372 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14373 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14374 tg3_flag_set(tp, NVRAM_BUFFERED);
321d32a0
MC		 14375 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14376
14377 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14378 tw32(NVRAM_CFG1, nvcfg1);
14379 return;
14380 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14381 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14382 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14383 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14384 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14385 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14386 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14387 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14388 tg3_flag_set(tp, NVRAM_BUFFERED);
14389 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14390
14391 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14392 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14393 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14394 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14395 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14396 break;
14397 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14398 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14399 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14400 break;
14401 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14402 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14403 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14404 break;
14405 }
14406 break;
14407 case FLASH_5752VENDOR_ST_M45PE10:
14408 case FLASH_5752VENDOR_ST_M45PE20:
14409 case FLASH_5752VENDOR_ST_M45PE40:
14410 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14411 tg3_flag_set(tp, NVRAM_BUFFERED);
14412 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14413
14414 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14415 case FLASH_5752VENDOR_ST_M45PE10:
14416 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14417 break;
14418 case FLASH_5752VENDOR_ST_M45PE20:
14419 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14420 break;
14421 case FLASH_5752VENDOR_ST_M45PE40:
14422 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14423 break;
14424 }
14425 break;
14426 default:
63c3a66f 14427 tg3_flag_set(tp, NO_NVRAM);
321d32a0
MC		 14428 return;
14429 }
14430
a1b950d5
MC		 14431 tg3_nvram_get_pagesize(tp, nvcfg1);
14432 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14433 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
a1b950d5
MC		 14434}
14435
14436
229b1ad1 14437static void tg3_get_5717_nvram_info(struct tg3 *tp)
a1b950d5
MC		 14438{
14439 u32 nvcfg1;
14440
14441 nvcfg1 = tr32(NVRAM_CFG1);
14442
14443 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14444 case FLASH_5717VENDOR_ATMEL_EEPROM:
14445 case FLASH_5717VENDOR_MICRO_EEPROM:
14446 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14447 tg3_flag_set(tp, NVRAM_BUFFERED);
a1b950d5
MC		 14448 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14449
14450 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14451 tw32(NVRAM_CFG1, nvcfg1);
14452 return;
14453 case FLASH_5717VENDOR_ATMEL_MDB011D:
14454 case FLASH_5717VENDOR_ATMEL_ADB011B:
14455 case FLASH_5717VENDOR_ATMEL_ADB011D:
14456 case FLASH_5717VENDOR_ATMEL_MDB021D:
14457 case FLASH_5717VENDOR_ATMEL_ADB021B:
14458 case FLASH_5717VENDOR_ATMEL_ADB021D:
14459 case FLASH_5717VENDOR_ATMEL_45USPT:
14460 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14461 tg3_flag_set(tp, NVRAM_BUFFERED);
14462 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14463
14464 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14465 case FLASH_5717VENDOR_ATMEL_MDB021D:
66ee33bf
MC		 14466 /* Detect size with tg3_nvram_get_size() */
14467 break;
a1b950d5
MC		 14468 case FLASH_5717VENDOR_ATMEL_ADB021B:
14469 case FLASH_5717VENDOR_ATMEL_ADB021D:
14470 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14471 break;
14472 default:
14473 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14474 break;
14475 }
321d32a0 14476 break;
a1b950d5
MC		 14477 case FLASH_5717VENDOR_ST_M_M25PE10:
14478 case FLASH_5717VENDOR_ST_A_M25PE10:
14479 case FLASH_5717VENDOR_ST_M_M45PE10:
14480 case FLASH_5717VENDOR_ST_A_M45PE10:
14481 case FLASH_5717VENDOR_ST_M_M25PE20:
14482 case FLASH_5717VENDOR_ST_A_M25PE20:
14483 case FLASH_5717VENDOR_ST_M_M45PE20:
14484 case FLASH_5717VENDOR_ST_A_M45PE20:
14485 case FLASH_5717VENDOR_ST_25USPT:
14486 case FLASH_5717VENDOR_ST_45USPT:
14487 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14488 tg3_flag_set(tp, NVRAM_BUFFERED);
14489 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14490
14491 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14492 case FLASH_5717VENDOR_ST_M_M25PE20:
a1b950d5 14493 case FLASH_5717VENDOR_ST_M_M45PE20:
66ee33bf
MC		 14494 /* Detect size with tg3_nvram_get_size() */
14495 break;
14496 case FLASH_5717VENDOR_ST_A_M25PE20:
a1b950d5
MC		 14497 case FLASH_5717VENDOR_ST_A_M45PE20:
14498 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14499 break;
14500 default:
14501 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14502 break;
14503 }
321d32a0 14504 break;
a1b950d5 14505 default:
63c3a66f 14506 tg3_flag_set(tp, NO_NVRAM);
a1b950d5 14507 return;
321d32a0 14508 }
a1b950d5
MC		 14509
14510 tg3_nvram_get_pagesize(tp, nvcfg1);
14511 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14512 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
321d32a0
MC		 14513}
14514
229b1ad1 14515static void tg3_get_5720_nvram_info(struct tg3 *tp)
9b91b5f1
MC		 14516{
14517 u32 nvcfg1, nvmpinstrp;
14518
14519 nvcfg1 = tr32(NVRAM_CFG1);
14520 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14521
4153577a 14522 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14523 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14524 tg3_flag_set(tp, NO_NVRAM);
14525 return;
14526 }
14527
14528 switch (nvmpinstrp) {
14529 case FLASH_5762_EEPROM_HD:
14530 nvmpinstrp = FLASH_5720_EEPROM_HD;
17e1a42f 14531 break;
c86a8560
MC		 14532 case FLASH_5762_EEPROM_LD:
14533 nvmpinstrp = FLASH_5720_EEPROM_LD;
17e1a42f 14534 break;
f6334bb8
MC		 14535 case FLASH_5720VENDOR_M_ST_M45PE20:
14536 /* This pinstrap supports multiple sizes, so force it
14537 * to read the actual size from location 0xf0.
14538 */
14539 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14540 break;
c86a8560
MC		 14541 }
14542 }
14543
9b91b5f1
MC		 14544 switch (nvmpinstrp) {
14545 case FLASH_5720_EEPROM_HD:
14546 case FLASH_5720_EEPROM_LD:
14547 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14548 tg3_flag_set(tp, NVRAM_BUFFERED);
9b91b5f1
MC		 14549
14550 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14551 tw32(NVRAM_CFG1, nvcfg1);
14552 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14553 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14554 else
14555 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14556 return;
14557 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14558 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14559 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14560 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14561 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14562 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14563 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14564 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14565 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14566 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14567 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14568 case FLASH_5720VENDOR_ATMEL_45USPT:
14569 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14570 tg3_flag_set(tp, NVRAM_BUFFERED);
14571 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14572
14573 switch (nvmpinstrp) {
14574 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14575 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14576 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14577 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14578 break;
14579 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14580 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14581 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14582 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14583 break;
14584 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14585 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14586 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14587 break;
14588 default:
4153577a 14589 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14590 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14591 break;
14592 }
14593 break;
14594 case FLASH_5720VENDOR_M_ST_M25PE10:
14595 case FLASH_5720VENDOR_M_ST_M45PE10:
14596 case FLASH_5720VENDOR_A_ST_M25PE10:
14597 case FLASH_5720VENDOR_A_ST_M45PE10:
14598 case FLASH_5720VENDOR_M_ST_M25PE20:
14599 case FLASH_5720VENDOR_M_ST_M45PE20:
14600 case FLASH_5720VENDOR_A_ST_M25PE20:
14601 case FLASH_5720VENDOR_A_ST_M45PE20:
14602 case FLASH_5720VENDOR_M_ST_M25PE40:
14603 case FLASH_5720VENDOR_M_ST_M45PE40:
14604 case FLASH_5720VENDOR_A_ST_M25PE40:
14605 case FLASH_5720VENDOR_A_ST_M45PE40:
14606 case FLASH_5720VENDOR_M_ST_M25PE80:
14607 case FLASH_5720VENDOR_M_ST_M45PE80:
14608 case FLASH_5720VENDOR_A_ST_M25PE80:
14609 case FLASH_5720VENDOR_A_ST_M45PE80:
14610 case FLASH_5720VENDOR_ST_25USPT:
14611 case FLASH_5720VENDOR_ST_45USPT:
14612 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14613 tg3_flag_set(tp, NVRAM_BUFFERED);
14614 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14615
14616 switch (nvmpinstrp) {
14617 case FLASH_5720VENDOR_M_ST_M25PE20:
14618 case FLASH_5720VENDOR_M_ST_M45PE20:
14619 case FLASH_5720VENDOR_A_ST_M25PE20:
14620 case FLASH_5720VENDOR_A_ST_M45PE20:
14621 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14622 break;
14623 case FLASH_5720VENDOR_M_ST_M25PE40:
14624 case FLASH_5720VENDOR_M_ST_M45PE40:
14625 case FLASH_5720VENDOR_A_ST_M25PE40:
14626 case FLASH_5720VENDOR_A_ST_M45PE40:
14627 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14628 break;
14629 case FLASH_5720VENDOR_M_ST_M25PE80:
14630 case FLASH_5720VENDOR_M_ST_M45PE80:
14631 case FLASH_5720VENDOR_A_ST_M25PE80:
14632 case FLASH_5720VENDOR_A_ST_M45PE80:
14633 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14634 break;
14635 default:
4153577a 14636 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14637 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14638 break;
14639 }
14640 break;
14641 default:
63c3a66f 14642 tg3_flag_set(tp, NO_NVRAM);
9b91b5f1
MC		 14643 return;
14644 }
14645
14646 tg3_nvram_get_pagesize(tp, nvcfg1);
14647 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14648 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
c86a8560 14649
4153577a 14650 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14651 u32 val;
14652
14653 if (tg3_nvram_read(tp, 0, &val))
14654 return;
14655
14656 if (val != TG3_EEPROM_MAGIC &&
14657 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14658 tg3_flag_set(tp, NO_NVRAM);
14659 }
9b91b5f1
MC		 14660}
14661
1da177e4 14662/* Chips other than 5700/5701 use the NVRAM for fetching info. */
229b1ad1 14663static void tg3_nvram_init(struct tg3 *tp)
1da177e4 14664{
7e6c63f0
HM		 14665 if (tg3_flag(tp, IS_SSB_CORE)) {
14666 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14667 tg3_flag_clear(tp, NVRAM);
14668 tg3_flag_clear(tp, NVRAM_BUFFERED);
14669 tg3_flag_set(tp, NO_NVRAM);
14670 return;
14671 }
14672
1da177e4
LT		 14673 tw32_f(GRC_EEPROM_ADDR,
14674 (EEPROM_ADDR_FSM_RESET |
14675 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14676 EEPROM_ADDR_CLKPERD_SHIFT)));
14677
9d57f01c 14678 msleep(1);
1da177e4
LT		 14679
14680 /* Enable seeprom accesses. */
14681 tw32_f(GRC_LOCAL_CTRL,
14682 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14683 udelay(100);
14684
4153577a
JP		 14685 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14686 tg3_asic_rev(tp) != ASIC_REV_5701) {
63c3a66f 14687 tg3_flag_set(tp, NVRAM);
1da177e4 14688
ec41c7df 14689 if (tg3_nvram_lock(tp)) {
5129c3a3
MC		 14690 netdev_warn(tp->dev,
14691 "Cannot get nvram lock, %s failed\n",
05dbe005 14692 __func__);
ec41c7df
MC		 14693 return;
14694 }
e6af301b 14695 tg3_enable_nvram_access(tp);
1da177e4 14696
989a9d23
MC		 14697 tp->nvram_size = 0;
14698
4153577a 14699 if (tg3_asic_rev(tp) == ASIC_REV_5752)
361b4ac2 14700 tg3_get_5752_nvram_info(tp);
4153577a 14701 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
d3c7b886 14702 tg3_get_5755_nvram_info(tp);
4153577a
JP		 14703 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14704 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14705 tg3_asic_rev(tp) == ASIC_REV_5785)
1b27777a 14706 tg3_get_5787_nvram_info(tp);
4153577a 14707 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
6b91fa02 14708 tg3_get_5761_nvram_info(tp);
4153577a 14709 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 14710 tg3_get_5906_nvram_info(tp);
4153577a 14711 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 14712 tg3_flag(tp, 57765_CLASS))
321d32a0 14713 tg3_get_57780_nvram_info(tp);
4153577a
JP		 14714 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14715 tg3_asic_rev(tp) == ASIC_REV_5719)
a1b950d5 14716 tg3_get_5717_nvram_info(tp);
4153577a
JP		 14717 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14718 tg3_asic_rev(tp) == ASIC_REV_5762)
9b91b5f1 14719 tg3_get_5720_nvram_info(tp);
361b4ac2
MC		 14720 else
14721 tg3_get_nvram_info(tp);
14722
989a9d23
MC		 14723 if (tp->nvram_size == 0)
14724 tg3_get_nvram_size(tp);
1da177e4 14725
e6af301b 14726 tg3_disable_nvram_access(tp);
381291b7 14727 tg3_nvram_unlock(tp);
1da177e4
LT		 14728
14729 } else {
63c3a66f
JP		 14730 tg3_flag_clear(tp, NVRAM);
14731 tg3_flag_clear(tp, NVRAM_BUFFERED);
1da177e4
LT		 14732
14733 tg3_get_eeprom_size(tp);
14734 }
14735}
14736
1da177e4
LT		 14737struct subsys_tbl_ent {
14738 u16 subsys_vendor, subsys_devid;
14739 u32 phy_id;
14740};
14741
229b1ad1 14742static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
1da177e4 14743 /* Broadcom boards. */
24daf2b0 14744 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14745 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 14746 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14747 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 14748 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14749 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 14750 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14751 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14752 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14753 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 14754 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14755 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14756 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14757 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14758 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14759 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 14760 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14761 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 14762 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14763 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 14764 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14765 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 14766
14767 /* 3com boards. */
24daf2b0 14768 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14769 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 14770 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14771 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14772 { TG3PCI_SUBVENDOR_ID_3COM,
14773 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
14774 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14775 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 14776 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14777 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14778
14779 /* DELL boards. */
24daf2b0 14780 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14781 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 14782 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14783 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 14784 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14785 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 14786 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14787 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 14788
14789 /* Compaq boards. */
24daf2b0 14790 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14791 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 14792 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14793 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14794 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14795 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
14796 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14797 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 14798 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14799 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14800
14801 /* IBM boards. */
24daf2b0
MC		 14802 { TG3PCI_SUBVENDOR_ID_IBM,
14803 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 14804};
14805
229b1ad1 14806static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 14807{
14808 int i;
14809
14810 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
14811 if ((subsys_id_to_phy_id[i].subsys_vendor ==
14812 tp->pdev->subsystem_vendor) &&
14813 (subsys_id_to_phy_id[i].subsys_devid ==
14814 tp->pdev->subsystem_device))
14815 return &subsys_id_to_phy_id[i];
14816 }
14817 return NULL;
14818}
14819
229b1ad1 14820static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 14821{
1da177e4 14822 u32 val;
f49639e6 14823
79eb6904 14824 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 14825 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14826
a85feb8c 14827 /* Assume an onboard device and WOL capable by default. */
63c3a66f
JP		 14828 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14829 tg3_flag_set(tp, WOL_CAP);
72b845e0 14830
4153577a 14831 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9d26e213 14832 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
63c3a66f
JP		 14833 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14834 tg3_flag_set(tp, IS_NIC);
9d26e213 14835 }
0527ba35
MC		 14836 val = tr32(VCPU_CFGSHDW);
14837 if (val & VCPU_CFGSHDW_ASPM_DBNC)
63c3a66f 14838 tg3_flag_set(tp, ASPM_WORKAROUND);
0527ba35 14839 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
6fdbab9d 14840 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
63c3a66f 14841 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 14842 device_set_wakeup_enable(&tp->pdev->dev, true);
14843 }
05ac4cb7 14844 goto done;
b5d3772c
MC		 14845 }
14846
1da177e4
LT		 14847 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
14848 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
14849 u32 nic_cfg, led_cfg;
a9daf367 14850 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 14851 int eeprom_phy_serdes = 0;
1da177e4
LT		 14852
14853 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
14854 tp->nic_sram_data_cfg = nic_cfg;
14855
14856 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
14857 ver >>= NIC_SRAM_DATA_VER_SHIFT;
4153577a
JP		 14858 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14859 tg3_asic_rev(tp) != ASIC_REV_5701 &&
14860 tg3_asic_rev(tp) != ASIC_REV_5703 &&
1da177e4
LT		 14861 (ver > 0) && (ver < 0x100))
14862 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
14863
4153577a 14864 if (tg3_asic_rev(tp) == ASIC_REV_5785)
a9daf367
MC		 14865 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
14866
1da177e4
LT		 14867 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
14868 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
14869 eeprom_phy_serdes = 1;
14870
14871 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
14872 if (nic_phy_id != 0) {
14873 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
14874 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
14875
14876 eeprom_phy_id = (id1 >> 16) << 10;
14877 eeprom_phy_id |= (id2 & 0xfc00) << 16;
14878 eeprom_phy_id |= (id2 & 0x03ff) << 0;
14879 } else
14880 eeprom_phy_id = 0;
14881
7d0c41ef 14882 tp->phy_id = eeprom_phy_id;
747e8f8b 14883 if (eeprom_phy_serdes) {
63c3a66f 14884 if (!tg3_flag(tp, 5705_PLUS))
f07e9af3 14885 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
a50d0796 14886 else
f07e9af3 14887 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
747e8f8b 14888 }
7d0c41ef 14889
63c3a66f 14890 if (tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 14891 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
14892 SHASTA_EXT_LED_MODE_MASK);
cbf46853 14893 else
1da177e4
LT		 14894 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
14895
14896 switch (led_cfg) {
14897 default:
14898 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
14899 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14900 break;
14901
14902 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
14903 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14904 break;
14905
14906 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
14907 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 14908
14909 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
14910 * read on some older 5700/5701 bootcode.
14911 */
4153577a
JP		 14912 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
14913 tg3_asic_rev(tp) == ASIC_REV_5701)
9ba27794
MC		 14914 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14915
1da177e4
LT		 14916 break;
14917
14918 case SHASTA_EXT_LED_SHARED:
14919 tp->led_ctrl = LED_CTRL_MODE_SHARED;
4153577a
JP		 14920 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
14921 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
1da177e4
LT		 14922 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14923 LED_CTRL_MODE_PHY_2);
14924 break;
14925
14926 case SHASTA_EXT_LED_MAC:
14927 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
14928 break;
14929
14930 case SHASTA_EXT_LED_COMBO:
14931 tp->led_ctrl = LED_CTRL_MODE_COMBO;
4153577a 14932 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
1da177e4
LT		 14933 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14934 LED_CTRL_MODE_PHY_2);
14935 break;
14936
855e1111 14937 }
1da177e4 14938
4153577a
JP		 14939 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
14940 tg3_asic_rev(tp) == ASIC_REV_5701) &&
1da177e4
LT		 14941 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
14942 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14943
4153577a 14944 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
b2a5c19c 14945 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 14946
9d26e213 14947 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
63c3a66f 14948 tg3_flag_set(tp, EEPROM_WRITE_PROT);
9d26e213
MC		 14949 if ((tp->pdev->subsystem_vendor ==
14950 PCI_VENDOR_ID_ARIMA) &&
14951 (tp->pdev->subsystem_device == 0x205a ||
14952 tp->pdev->subsystem_device == 0x2063))
63c3a66f 14953 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
9d26e213 14954 } else {
63c3a66f
JP		 14955 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14956 tg3_flag_set(tp, IS_NIC);
9d26e213 14957 }
1da177e4
LT		 14958
14959 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f
JP		 14960 tg3_flag_set(tp, ENABLE_ASF);
14961 if (tg3_flag(tp, 5750_PLUS))
14962 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
1da177e4 14963 }
b2b98d4a
MC		 14964
14965 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
63c3a66f
JP		 14966 tg3_flag(tp, 5750_PLUS))
14967 tg3_flag_set(tp, ENABLE_APE);
b2b98d4a 14968
f07e9af3 14969 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
a85feb8c 14970 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
63c3a66f 14971 tg3_flag_clear(tp, WOL_CAP);
1da177e4 14972
63c3a66f 14973 if (tg3_flag(tp, WOL_CAP) &&
6fdbab9d 14974 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
63c3a66f 14975 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 14976 device_set_wakeup_enable(&tp->pdev->dev, true);
14977 }
0527ba35 14978
1da177e4 14979 if (cfg2 & (1 << 17))
f07e9af3 14980 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
1da177e4
LT		 14981
14982 /* serdes signal pre-emphasis in register 0x590 set by */
14983 /* bootcode if bit 18 is set */
14984 if (cfg2 & (1 << 18))
f07e9af3 14985 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
8ed5d97e 14986
63c3a66f 14987 if ((tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 14988 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
14989 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
6833c043 14990 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
f07e9af3 14991 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
6833c043 14992
942d1af0 14993 if (tg3_flag(tp, PCI_EXPRESS)) {
8ed5d97e
MC		 14994 u32 cfg3;
14995
14996 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
942d1af0
NS		 14997 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
14998 !tg3_flag(tp, 57765_PLUS) &&
14999 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
63c3a66f 15000 tg3_flag_set(tp, ASPM_WORKAROUND);
942d1af0
NS		 15001 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15002 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15003 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15004 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
8ed5d97e 15005 }
a9daf367 15006
14417063 15007 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
63c3a66f 15008 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
a9daf367 15009 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
63c3a66f 15010 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
a9daf367 15011 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
63c3a66f 15012 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
1da177e4 15013 }
05ac4cb7 15014done:
63c3a66f 15015 if (tg3_flag(tp, WOL_CAP))
43067ed8 15016 device_set_wakeup_enable(&tp->pdev->dev,
63c3a66f 15017 tg3_flag(tp, WOL_ENABLE));
43067ed8
RW		 15018 else
15019 device_set_wakeup_capable(&tp->pdev->dev, false);
7d0c41ef
MC		 15020}
15021
c86a8560
MC		 15022static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15023{
15024 int i, err;
15025 u32 val2, off = offset * 8;
15026
15027 err = tg3_nvram_lock(tp);
15028 if (err)
15029 return err;
15030
15031 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15032 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15033 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15034 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15035 udelay(10);
15036
15037 for (i = 0; i < 100; i++) {
15038 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15039 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15040 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15041 break;
15042 }
15043 udelay(10);
15044 }
15045
15046 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15047
15048 tg3_nvram_unlock(tp);
15049 if (val2 & APE_OTP_STATUS_CMD_DONE)
15050 return 0;
15051
15052 return -EBUSY;
15053}
15054
229b1ad1 15055static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
b2a5c19c
MC		 15056{
15057 int i;
15058 u32 val;
15059
15060 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15061 tw32(OTP_CTRL, cmd);
15062
15063 /* Wait for up to 1 ms for command to execute. */
15064 for (i = 0; i < 100; i++) {
15065 val = tr32(OTP_STATUS);
15066 if (val & OTP_STATUS_CMD_DONE)
15067 break;
15068 udelay(10);
15069 }
15070
15071 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15072}
15073
15074/* Read the gphy configuration from the OTP region of the chip. The gphy
15075 * configuration is a 32-bit value that straddles the alignment boundary.
15076 * We do two 32-bit reads and then shift and merge the results.
15077 */
229b1ad1 15078static u32 tg3_read_otp_phycfg(struct tg3 *tp)
b2a5c19c
MC		 15079{
15080 u32 bhalf_otp, thalf_otp;
15081
15082 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15083
15084 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15085 return 0;
15086
15087 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15088
15089 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15090 return 0;
15091
15092 thalf_otp = tr32(OTP_READ_DATA);
15093
15094 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15095
15096 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15097 return 0;
15098
15099 bhalf_otp = tr32(OTP_READ_DATA);
15100
15101 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15102}
15103
229b1ad1 15104static void tg3_phy_init_link_config(struct tg3 *tp)
e256f8a3 15105{
202ff1c2 15106 u32 adv = ADVERTISED_Autoneg;
e256f8a3
MC		 15107
15108 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15109 adv |= ADVERTISED_1000baseT_Half |
15110 ADVERTISED_1000baseT_Full;
15111
15112 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15113 adv |= ADVERTISED_100baseT_Half |
15114 ADVERTISED_100baseT_Full |
15115 ADVERTISED_10baseT_Half |
15116 ADVERTISED_10baseT_Full |
15117 ADVERTISED_TP;
15118 else
15119 adv |= ADVERTISED_FIBRE;
15120
15121 tp->link_config.advertising = adv;
e740522e
MC		 15122 tp->link_config.speed = SPEED_UNKNOWN;
15123 tp->link_config.duplex = DUPLEX_UNKNOWN;
e256f8a3 15124 tp->link_config.autoneg = AUTONEG_ENABLE;
e740522e
MC		 15125 tp->link_config.active_speed = SPEED_UNKNOWN;
15126 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
34655ad6
MC		 15127
15128 tp->old_link = -1;
e256f8a3
MC		 15129}
15130
229b1ad1 15131static int tg3_phy_probe(struct tg3 *tp)
7d0c41ef
MC		 15132{
15133 u32 hw_phy_id_1, hw_phy_id_2;
15134 u32 hw_phy_id, hw_phy_id_masked;
15135 int err;
1da177e4 15136
e256f8a3 15137 /* flow control autonegotiation is default behavior */
63c3a66f 15138 tg3_flag_set(tp, PAUSE_AUTONEG);
e256f8a3
MC		 15139 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15140
8151ad57
MC		 15141 if (tg3_flag(tp, ENABLE_APE)) {
15142 switch (tp->pci_fn) {
15143 case 0:
15144 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15145 break;
15146 case 1:
15147 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15148 break;
15149 case 2:
15150 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15151 break;
15152 case 3:
15153 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15154 break;
15155 }
15156 }
15157
942d1af0
NS		 15158 if (!tg3_flag(tp, ENABLE_ASF) &&
15159 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15160 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15161 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15162 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15163
63c3a66f 15164 if (tg3_flag(tp, USE_PHYLIB))
b02fd9e3
MC		 15165 return tg3_phy_init(tp);
15166
1da177e4 15167 /* Reading the PHY ID register can conflict with ASF
877d0310 15168 * firmware access to the PHY hardware.
1da177e4
LT		 15169 */
15170 err = 0;
63c3a66f 15171 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
79eb6904 15172 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 15173 } else {
15174 /* Now read the physical PHY_ID from the chip and verify
15175 * that it is sane. If it doesn't look good, we fall back
15176 * to either the hard-coded table based PHY_ID and failing
15177 * that the value found in the eeprom area.
15178 */
15179 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15180 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15181
15182 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15183 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15184 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15185
79eb6904 15186 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 15187 }
15188
79eb6904 15189 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 15190 tp->phy_id = hw_phy_id;
79eb6904 15191 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
f07e9af3 15192 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
da6b2d01 15193 else
f07e9af3 15194 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
1da177e4 15195 } else {
79eb6904 15196 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 15197 /* Do nothing, phy ID already set up in
15198 * tg3_get_eeprom_hw_cfg().
15199 */
1da177e4
LT		 15200 } else {
15201 struct subsys_tbl_ent *p;
15202
15203 /* No eeprom signature? Try the hardcoded
15204 * subsys device table.
15205 */
24daf2b0 15206 p = tg3_lookup_by_subsys(tp);
7e6c63f0
HM		 15207 if (p) {
15208 tp->phy_id = p->phy_id;
15209 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15210 /* For now we saw the IDs 0xbc050cd0,
15211 * 0xbc050f80 and 0xbc050c30 on devices
15212 * connected to an BCM4785 and there are
15213 * probably more. Just assume that the phy is
15214 * supported when it is connected to a SSB core
15215 * for now.
15216 */
1da177e4 15217 return -ENODEV;
7e6c63f0 15218 }
1da177e4 15219
1da177e4 15220 if (!tp->phy_id ||
79eb6904 15221 tp->phy_id == TG3_PHY_ID_BCM8002)
f07e9af3 15222 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
1da177e4
LT		 15223 }
15224 }
15225
a6b68dab 15226 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
4153577a
JP		 15227 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15228 tg3_asic_rev(tp) == ASIC_REV_5720 ||
c4dab506 15229 tg3_asic_rev(tp) == ASIC_REV_57766 ||
4153577a
JP		 15230 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15231 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15232 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15233 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
9e2ecbeb 15234 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
52b02d04
MC		 15235 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15236
9e2ecbeb
NS		 15237 tp->eee.supported = SUPPORTED_100baseT_Full |
15238 SUPPORTED_1000baseT_Full;
15239 tp->eee.advertised = ADVERTISED_100baseT_Full |
15240 ADVERTISED_1000baseT_Full;
15241 tp->eee.eee_enabled = 1;
15242 tp->eee.tx_lpi_enabled = 1;
15243 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15244 }
15245
e256f8a3
MC		 15246 tg3_phy_init_link_config(tp);
15247
942d1af0
NS		 15248 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15249 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
63c3a66f
JP		 15250 !tg3_flag(tp, ENABLE_APE) &&
15251 !tg3_flag(tp, ENABLE_ASF)) {
e2bf73e7 15252 u32 bmsr, dummy;
1da177e4
LT		 15253
15254 tg3_readphy(tp, MII_BMSR, &bmsr);
15255 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15256 (bmsr & BMSR_LSTATUS))
15257 goto skip_phy_reset;
6aa20a22 15258
1da177e4
LT		 15259 err = tg3_phy_reset(tp);
15260 if (err)
15261 return err;
15262
42b64a45 15263 tg3_phy_set_wirespeed(tp);
1da177e4 15264
e2bf73e7 15265 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
42b64a45
MC		 15266 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15267 tp->link_config.flowctrl);
1da177e4
LT		 15268
15269 tg3_writephy(tp, MII_BMCR,
15270 BMCR_ANENABLE | BMCR_ANRESTART);
15271 }
1da177e4
LT		 15272 }
15273
15274skip_phy_reset:
79eb6904 15275 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 15276 err = tg3_init_5401phy_dsp(tp);
15277 if (err)
15278 return err;
1da177e4 15279
1da177e4
LT		 15280 err = tg3_init_5401phy_dsp(tp);
15281 }
15282
1da177e4
LT		 15283 return err;
15284}
15285
229b1ad1 15286static void tg3_read_vpd(struct tg3 *tp)
1da177e4 15287{
a4a8bb15 15288 u8 *vpd_data;
4181b2c8 15289 unsigned int block_end, rosize, len;
535a490e 15290 u32 vpdlen;
184b8904 15291 int j, i = 0;
a4a8bb15 15292
535a490e 15293 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
a4a8bb15
MC		 15294 if (!vpd_data)
15295 goto out_no_vpd;
1da177e4 15296
535a490e 15297 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
4181b2c8
MC		 15298 if (i < 0)
15299 goto out_not_found;
1da177e4 15300
4181b2c8
MC		 15301 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15302 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15303 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 15304
535a490e 15305 if (block_end > vpdlen)
4181b2c8 15306 goto out_not_found;
af2c6a4a 15307
184b8904
MC		 15308 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15309 PCI_VPD_RO_KEYWORD_MFR_ID);
15310 if (j > 0) {
15311 len = pci_vpd_info_field_size(&vpd_data[j]);
15312
15313 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15314 if (j + len > block_end || len != 4 ||
15315 memcmp(&vpd_data[j], "1028", 4))
15316 goto partno;
15317
15318 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15319 PCI_VPD_RO_KEYWORD_VENDOR0);
15320 if (j < 0)
15321 goto partno;
15322
15323 len = pci_vpd_info_field_size(&vpd_data[j]);
15324
15325 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15326 if (j + len > block_end)
15327 goto partno;
15328
715230a4
KC		 15329 if (len >= sizeof(tp->fw_ver))
15330 len = sizeof(tp->fw_ver) - 1;
15331 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15332 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15333 &vpd_data[j]);
184b8904
MC		 15334 }
15335
15336partno:
4181b2c8
MC		 15337 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15338 PCI_VPD_RO_KEYWORD_PARTNO);
15339 if (i < 0)
15340 goto out_not_found;
af2c6a4a 15341
4181b2c8 15342 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 15343
4181b2c8
MC		 15344 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15345 if (len > TG3_BPN_SIZE ||
535a490e 15346 (len + i) > vpdlen)
4181b2c8 15347 goto out_not_found;
1da177e4 15348
4181b2c8 15349 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 15350
1da177e4 15351out_not_found:
a4a8bb15 15352 kfree(vpd_data);
37a949c5 15353 if (tp->board_part_number[0])
a4a8bb15
MC		 15354 return;
15355
15356out_no_vpd:
4153577a 15357 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
79d49695
MC		 15358 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15359 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
37a949c5
MC		 15360 strcpy(tp->board_part_number, "BCM5717");
15361 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15362 strcpy(tp->board_part_number, "BCM5718");
15363 else
15364 goto nomatch;
4153577a 15365 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
37a949c5
MC		 15366 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15367 strcpy(tp->board_part_number, "BCM57780");
15368 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15369 strcpy(tp->board_part_number, "BCM57760");
15370 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15371 strcpy(tp->board_part_number, "BCM57790");
15372 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15373 strcpy(tp->board_part_number, "BCM57788");
15374 else
15375 goto nomatch;
4153577a 15376 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
37a949c5
MC		 15377 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15378 strcpy(tp->board_part_number, "BCM57761");
15379 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15380 strcpy(tp->board_part_number, "BCM57765");
15381 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15382 strcpy(tp->board_part_number, "BCM57781");
15383 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15384 strcpy(tp->board_part_number, "BCM57785");
15385 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15386 strcpy(tp->board_part_number, "BCM57791");
15387 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15388 strcpy(tp->board_part_number, "BCM57795");
15389 else
15390 goto nomatch;
4153577a 15391 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
55086ad9
MC		 15392 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15393 strcpy(tp->board_part_number, "BCM57762");
15394 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15395 strcpy(tp->board_part_number, "BCM57766");
15396 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15397 strcpy(tp->board_part_number, "BCM57782");
15398 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15399 strcpy(tp->board_part_number, "BCM57786");
15400 else
15401 goto nomatch;
4153577a 15402 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c 15403 strcpy(tp->board_part_number, "BCM95906");
37a949c5
MC		 15404 } else {
15405nomatch:
b5d3772c 15406 strcpy(tp->board_part_number, "none");
37a949c5 15407 }
1da177e4
LT		 15408}
15409
229b1ad1 15410static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
9c8a620e
MC		 15411{
15412 u32 val;
15413
e4f34110 15414 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 15415 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 15416 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 15417 val != 0)
15418 return 0;
15419
15420 return 1;
15421}
15422
229b1ad1 15423static void tg3_read_bc_ver(struct tg3 *tp)
acd9c119 15424{
ff3a7cb2 15425 u32 val, offset, start, ver_offset;
75f9936e 15426 int i, dst_off;
ff3a7cb2 15427 bool newver = false;
acd9c119
MC		 15428
15429 if (tg3_nvram_read(tp, 0xc, &offset) ||
15430 tg3_nvram_read(tp, 0x4, &start))
15431 return;
15432
15433 offset = tg3_nvram_logical_addr(tp, offset);
15434
ff3a7cb2 15435 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 15436 return;
15437
ff3a7cb2
MC		 15438 if ((val & 0xfc000000) == 0x0c000000) {
15439 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 15440 return;
15441
ff3a7cb2
MC		 15442 if (val == 0)
15443 newver = true;
15444 }
15445
75f9936e
MC		 15446 dst_off = strlen(tp->fw_ver);
15447
ff3a7cb2 15448 if (newver) {
75f9936e
MC		 15449 if (TG3_VER_SIZE - dst_off < 16 ||
15450 tg3_nvram_read(tp, offset + 8, &ver_offset))
ff3a7cb2
MC		 15451 return;
15452
15453 offset = offset + ver_offset - start;
15454 for (i = 0; i < 16; i += 4) {
15455 __be32 v;
15456 if (tg3_nvram_read_be32(tp, offset + i, &v))
15457 return;
15458
75f9936e 15459 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
ff3a7cb2
MC		 15460 }
15461 } else {
15462 u32 major, minor;
15463
15464 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15465 return;
15466
15467 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15468 TG3_NVM_BCVER_MAJSFT;
15469 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
75f9936e
MC		 15470 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15471 "v%d.%02d", major, minor);
acd9c119
MC		 15472 }
15473}
15474
229b1ad1 15475static void tg3_read_hwsb_ver(struct tg3 *tp)
a6f6cb1c
MC		 15476{
15477 u32 val, major, minor;
15478
15479 /* Use native endian representation */
15480 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15481 return;
15482
15483 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15484 TG3_NVM_HWSB_CFG1_MAJSFT;
15485 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15486 TG3_NVM_HWSB_CFG1_MINSFT;
15487
15488 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15489}
15490
229b1ad1 15491static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
dfe00d7d
MC		 15492{
15493 u32 offset, major, minor, build;
15494
75f9936e 15495 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
dfe00d7d
MC		 15496
15497 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15498 return;
15499
15500 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15501 case TG3_EEPROM_SB_REVISION_0:
15502 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15503 break;
15504 case TG3_EEPROM_SB_REVISION_2:
15505 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15506 break;
15507 case TG3_EEPROM_SB_REVISION_3:
15508 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15509 break;
a4153d40
MC		 15510 case TG3_EEPROM_SB_REVISION_4:
15511 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15512 break;
15513 case TG3_EEPROM_SB_REVISION_5:
15514 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15515 break;
bba226ac
MC		 15516 case TG3_EEPROM_SB_REVISION_6:
15517 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15518 break;
dfe00d7d
MC		 15519 default:
15520 return;
15521 }
15522
e4f34110 15523 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 15524 return;
15525
15526 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15527 TG3_EEPROM_SB_EDH_BLD_SHFT;
15528 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15529 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15530 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15531
15532 if (minor > 99 || build > 26)
15533 return;
15534
75f9936e
MC		 15535 offset = strlen(tp->fw_ver);
15536 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15537 " v%d.%02d", major, minor);
dfe00d7d
MC		 15538
15539 if (build > 0) {
75f9936e
MC		 15540 offset = strlen(tp->fw_ver);
15541 if (offset < TG3_VER_SIZE - 1)
15542 tp->fw_ver[offset] = 'a' + build - 1;
dfe00d7d
MC		 15543 }
15544}
15545
229b1ad1 15546static void tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 15547{
15548 u32 val, offset, start;
acd9c119 15549 int i, vlen;
9c8a620e
MC		 15550
15551 for (offset = TG3_NVM_DIR_START;
15552 offset < TG3_NVM_DIR_END;
15553 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 15554 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 15555 return;
15556
9c8a620e
MC		 15557 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15558 break;
15559 }
15560
15561 if (offset == TG3_NVM_DIR_END)
15562 return;
15563
63c3a66f 15564 if (!tg3_flag(tp, 5705_PLUS))
9c8a620e 15565 start = 0x08000000;
e4f34110 15566 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 15567 return;
15568
e4f34110 15569 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 15570 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 15571 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 15572 return;
15573
15574 offset += val - start;
15575
acd9c119 15576 vlen = strlen(tp->fw_ver);
9c8a620e 15577
acd9c119
MC		 15578 tp->fw_ver[vlen++] = ',';
15579 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 15580
15581 for (i = 0; i < 4; i++) {
a9dc529d
MC		 15582 __be32 v;
15583 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 15584 return;
15585
b9fc7dc5 15586 offset += sizeof(v);
c4e6575c 15587
acd9c119
MC		 15588 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15589 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 15590 break;
c4e6575c 15591 }
9c8a620e 15592
acd9c119
MC		 15593 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15594 vlen += sizeof(v);
c4e6575c 15595 }
acd9c119
MC		 15596}
15597
229b1ad1 15598static void tg3_probe_ncsi(struct tg3 *tp)
7fd76445 15599{
7fd76445 15600 u32 apedata;
7fd76445
MC		 15601
15602 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15603 if (apedata != APE_SEG_SIG_MAGIC)
15604 return;
15605
15606 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15607 if (!(apedata & APE_FW_STATUS_READY))
15608 return;
15609
165f4d1c
MC		 15610 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15611 tg3_flag_set(tp, APE_HAS_NCSI);
15612}
15613
229b1ad1 15614static void tg3_read_dash_ver(struct tg3 *tp)
165f4d1c
MC		 15615{
15616 int vlen;
15617 u32 apedata;
15618 char *fwtype;
15619
7fd76445
MC		 15620 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15621
165f4d1c 15622 if (tg3_flag(tp, APE_HAS_NCSI))
ecc79648 15623 fwtype = "NCSI";
c86a8560
MC		 15624 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15625 fwtype = "SMASH";
165f4d1c 15626 else
ecc79648
MC		 15627 fwtype = "DASH";
15628
7fd76445
MC		 15629 vlen = strlen(tp->fw_ver);
15630
ecc79648
MC		 15631 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15632 fwtype,
7fd76445
MC		 15633 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15634 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15635 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15636 (apedata & APE_FW_VERSION_BLDMSK));
15637}
15638
c86a8560
MC		 15639static void tg3_read_otp_ver(struct tg3 *tp)
15640{
15641 u32 val, val2;
15642
4153577a 15643 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c86a8560
MC		 15644 return;
15645
15646 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15647 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15648 TG3_OTP_MAGIC0_VALID(val)) {
15649 u64 val64 = (u64) val << 32 | val2;
15650 u32 ver = 0;
15651 int i, vlen;
15652
15653 for (i = 0; i < 7; i++) {
15654 if ((val64 & 0xff) == 0)
15655 break;
15656 ver = val64 & 0xff;
15657 val64 >>= 8;
15658 }
15659 vlen = strlen(tp->fw_ver);
15660 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15661 }
15662}
15663
229b1ad1 15664static void tg3_read_fw_ver(struct tg3 *tp)
acd9c119
MC		 15665{
15666 u32 val;
75f9936e 15667 bool vpd_vers = false;
acd9c119 15668
75f9936e
MC		 15669 if (tp->fw_ver[0] != 0)
15670 vpd_vers = true;
df259d8c 15671
63c3a66f 15672 if (tg3_flag(tp, NO_NVRAM)) {
75f9936e 15673 strcat(tp->fw_ver, "sb");
c86a8560 15674 tg3_read_otp_ver(tp);
df259d8c
MC		 15675 return;
15676 }
15677
acd9c119
MC		 15678 if (tg3_nvram_read(tp, 0, &val))
15679 return;
15680
15681 if (val == TG3_EEPROM_MAGIC)
15682 tg3_read_bc_ver(tp);
15683 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15684 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 15685 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15686 tg3_read_hwsb_ver(tp);
acd9c119 15687
165f4d1c
MC		 15688 if (tg3_flag(tp, ENABLE_ASF)) {
15689 if (tg3_flag(tp, ENABLE_APE)) {
15690 tg3_probe_ncsi(tp);
15691 if (!vpd_vers)
15692 tg3_read_dash_ver(tp);
15693 } else if (!vpd_vers) {
15694 tg3_read_mgmtfw_ver(tp);
15695 }
c9cab24e 15696 }
9c8a620e
MC		 15697
15698 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 15699}
15700
7cb32cf2
MC		 15701static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15702{
63c3a66f 15703 if (tg3_flag(tp, LRG_PROD_RING_CAP))
de9f5230 15704 return TG3_RX_RET_MAX_SIZE_5717;
63c3a66f 15705 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
de9f5230 15706 return TG3_RX_RET_MAX_SIZE_5700;
7cb32cf2 15707 else
de9f5230 15708 return TG3_RX_RET_MAX_SIZE_5705;
7cb32cf2
MC		 15709}
15710
4143470c 15711static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
895950c2
JP		 15712 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15713 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15714 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15715 { },
15716};
15717
229b1ad1 15718static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16c7fa7d
MC		 15719{
15720 struct pci_dev *peer;
15721 unsigned int func, devnr = tp->pdev->devfn & ~7;
15722
15723 for (func = 0; func < 8; func++) {
15724 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15725 if (peer && peer != tp->pdev)
15726 break;
15727 pci_dev_put(peer);
15728 }
15729 /* 5704 can be configured in single-port mode, set peer to
15730 * tp->pdev in that case.
15731 */
15732 if (!peer) {
15733 peer = tp->pdev;
15734 return peer;
15735 }
15736
15737 /*
15738 * We don't need to keep the refcount elevated; there's no way
15739 * to remove one half of this device without removing the other
15740 */
15741 pci_dev_put(peer);
15742
15743 return peer;
15744}
15745
229b1ad1 15746static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
42b123b1
MC		 15747{
15748 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
4153577a 15749 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
42b123b1
MC		 15750 u32 reg;
15751
15752 /* All devices that use the alternate
15753 * ASIC REV location have a CPMU.
15754 */
15755 tg3_flag_set(tp, CPMU_PRESENT);
15756
15757 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 15758 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
42b123b1
MC		 15759 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15760 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4
MC		 15761 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
15762 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
15763 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
15764 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727)
42b123b1
MC		 15765 reg = TG3PCI_GEN2_PRODID_ASICREV;
15766 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
15767 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
15768 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
15769 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
15770 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15771 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
15772 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
15773 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
15774 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
15775 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15776 reg = TG3PCI_GEN15_PRODID_ASICREV;
15777 else
15778 reg = TG3PCI_PRODID_ASICREV;
15779
15780 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
15781 }
15782
15783 /* Wrong chip ID in 5752 A0. This code can be removed later
15784 * as A0 is not in production.
15785 */
4153577a 15786 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
42b123b1
MC		 15787 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
15788
4153577a 15789 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
79d49695
MC		 15790 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
15791
4153577a
JP		 15792 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15793 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15794 tg3_asic_rev(tp) == ASIC_REV_5720)
42b123b1
MC		 15795 tg3_flag_set(tp, 5717_PLUS);
15796
4153577a
JP		 15797 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
15798 tg3_asic_rev(tp) == ASIC_REV_57766)
42b123b1
MC		 15799 tg3_flag_set(tp, 57765_CLASS);
15800
c65a17f4 15801 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
4153577a 15802 tg3_asic_rev(tp) == ASIC_REV_5762)
42b123b1
MC		 15803 tg3_flag_set(tp, 57765_PLUS);
15804
15805 /* Intentionally exclude ASIC_REV_5906 */
4153577a
JP		 15806 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
15807 tg3_asic_rev(tp) == ASIC_REV_5787 ||
15808 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15809 tg3_asic_rev(tp) == ASIC_REV_5761 ||
15810 tg3_asic_rev(tp) == ASIC_REV_5785 ||
15811 tg3_asic_rev(tp) == ASIC_REV_57780 ||
42b123b1
MC		 15812 tg3_flag(tp, 57765_PLUS))
15813 tg3_flag_set(tp, 5755_PLUS);
15814
4153577a
JP		 15815 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
15816 tg3_asic_rev(tp) == ASIC_REV_5714)
42b123b1
MC		 15817 tg3_flag_set(tp, 5780_CLASS);
15818
4153577a
JP		 15819 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
15820 tg3_asic_rev(tp) == ASIC_REV_5752 ||
15821 tg3_asic_rev(tp) == ASIC_REV_5906 ||
42b123b1
MC		 15822 tg3_flag(tp, 5755_PLUS) ||
15823 tg3_flag(tp, 5780_CLASS))
15824 tg3_flag_set(tp, 5750_PLUS);
15825
4153577a 15826 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
42b123b1
MC		 15827 tg3_flag(tp, 5750_PLUS))
15828 tg3_flag_set(tp, 5705_PLUS);
15829}
15830
3d567e0e
NNS		 15831static bool tg3_10_100_only_device(struct tg3 *tp,
15832 const struct pci_device_id *ent)
15833{
15834 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
15835
4153577a
JP		 15836 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
15837 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
3d567e0e
NNS		 15838 (tp->phy_flags & TG3_PHYFLG_IS_FET))
15839 return true;
15840
15841 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
4153577a 15842 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3d567e0e
NNS		 15843 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
15844 return true;
15845 } else {
15846 return true;
15847 }
15848 }
15849
15850 return false;
15851}
15852
1dd06ae8 15853static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
1da177e4 15854{
1da177e4 15855 u32 misc_ctrl_reg;
1da177e4
LT		 15856 u32 pci_state_reg, grc_misc_cfg;
15857 u32 val;
15858 u16 pci_cmd;
5e7dfd0f 15859 int err;
1da177e4 15860
1da177e4
LT		 15861 /* Force memory write invalidate off. If we leave it on,
15862 * then on 5700_BX chips we have to enable a workaround.
15863 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
15864 * to match the cacheline size. The Broadcom driver have this
15865 * workaround but turns MWI off all the times so never uses
15866 * it. This seems to suggest that the workaround is insufficient.
15867 */
15868 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
15869 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
15870 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
15871
16821285
MC		 15872 /* Important! -- Make sure register accesses are byteswapped
15873 * correctly. Also, for those chips that require it, make
15874 * sure that indirect register accesses are enabled before
15875 * the first operation.
1da177e4
LT		 15876 */
15877 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15878 &misc_ctrl_reg);
16821285
MC		 15879 tp->misc_host_ctrl |= (misc_ctrl_reg &
15880 MISC_HOST_CTRL_CHIPREV);
15881 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15882 tp->misc_host_ctrl);
1da177e4 15883
42b123b1 15884 tg3_detect_asic_rev(tp, misc_ctrl_reg);
ff645bec 15885
6892914f
MC		 15886 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
15887 * we need to disable memory and use config. cycles
15888 * only to access all registers. The 5702/03 chips
15889 * can mistakenly decode the special cycles from the
15890 * ICH chipsets as memory write cycles, causing corruption
15891 * of register and memory space. Only certain ICH bridges
15892 * will drive special cycles with non-zero data during the
15893 * address phase which can fall within the 5703's address
15894 * range. This is not an ICH bug as the PCI spec allows
15895 * non-zero address during special cycles. However, only
15896 * these ICH bridges are known to drive non-zero addresses
15897 * during special cycles.
15898 *
15899 * Since special cycles do not cross PCI bridges, we only
15900 * enable this workaround if the 5703 is on the secondary
15901 * bus of these ICH bridges.
15902 */
4153577a
JP		 15903 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
15904 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
6892914f
MC		 15905 static struct tg3_dev_id {
15906 u32 vendor;
15907 u32 device;
15908 u32 rev;
15909 } ich_chipsets[] = {
15910 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
15911 PCI_ANY_ID },
15912 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
15913 PCI_ANY_ID },
15914 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
15915 0xa },
15916 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
15917 PCI_ANY_ID },
15918 { },
15919 };
15920 struct tg3_dev_id *pci_id = &ich_chipsets[0];
15921 struct pci_dev *bridge = NULL;
15922
15923 while (pci_id->vendor != 0) {
15924 bridge = pci_get_device(pci_id->vendor, pci_id->device,
15925 bridge);
15926 if (!bridge) {
15927 pci_id++;
15928 continue;
15929 }
15930 if (pci_id->rev != PCI_ANY_ID) {
44c10138 15931 if (bridge->revision > pci_id->rev)
6892914f
MC		 15932 continue;
15933 }
15934 if (bridge->subordinate &&
15935 (bridge->subordinate->number ==
15936 tp->pdev->bus->number)) {
63c3a66f 15937 tg3_flag_set(tp, ICH_WORKAROUND);
6892914f
MC		 15938 pci_dev_put(bridge);
15939 break;
15940 }
15941 }
15942 }
15943
4153577a 15944 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
41588ba1
MC		 15945 static struct tg3_dev_id {
15946 u32 vendor;
15947 u32 device;
15948 } bridge_chipsets[] = {
15949 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
15950 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
15951 { },
15952 };
15953 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
15954 struct pci_dev *bridge = NULL;
15955
15956 while (pci_id->vendor != 0) {
15957 bridge = pci_get_device(pci_id->vendor,
15958 pci_id->device,
15959 bridge);
15960 if (!bridge) {
15961 pci_id++;
15962 continue;
15963 }
15964 if (bridge->subordinate &&
15965 (bridge->subordinate->number <=
15966 tp->pdev->bus->number) &&
b918c62e 15967 (bridge->subordinate->busn_res.end >=
41588ba1 15968 tp->pdev->bus->number)) {
63c3a66f 15969 tg3_flag_set(tp, 5701_DMA_BUG);
41588ba1
MC		 15970 pci_dev_put(bridge);
15971 break;
15972 }
15973 }
15974 }
15975
4a29cc2e
MC		 15976 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
15977 * DMA addresses > 40-bit. This bridge may have other additional
15978 * 57xx devices behind it in some 4-port NIC designs for example.
15979 * Any tg3 device found behind the bridge will also need the 40-bit
15980 * DMA workaround.
15981 */
42b123b1 15982 if (tg3_flag(tp, 5780_CLASS)) {
63c3a66f 15983 tg3_flag_set(tp, 40BIT_DMA_BUG);
0f847584 15984 tp->msi_cap = tp->pdev->msi_cap;
859a5887 15985 } else {
4a29cc2e
MC		 15986 struct pci_dev *bridge = NULL;
15987
15988 do {
15989 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
15990 PCI_DEVICE_ID_SERVERWORKS_EPB,
15991 bridge);
15992 if (bridge && bridge->subordinate &&
15993 (bridge->subordinate->number <=
15994 tp->pdev->bus->number) &&
b918c62e 15995 (bridge->subordinate->busn_res.end >=
4a29cc2e 15996 tp->pdev->bus->number)) {
63c3a66f 15997 tg3_flag_set(tp, 40BIT_DMA_BUG);
4a29cc2e
MC		 15998 pci_dev_put(bridge);
15999 break;
16000 }
16001 } while (bridge);
16002 }
4cf78e4f 16003
4153577a
JP		 16004 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16005 tg3_asic_rev(tp) == ASIC_REV_5714)
7544b097
MC		 16006 tp->pdev_peer = tg3_find_peer(tp);
16007
507399f1 16008 /* Determine TSO capabilities */
4153577a 16009 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
4d163b75 16010 ; /* Do nothing. HW bug. */
63c3a66f
JP		 16011 else if (tg3_flag(tp, 57765_PLUS))
16012 tg3_flag_set(tp, HW_TSO_3);
16013 else if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16014 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f
JP		 16015 tg3_flag_set(tp, HW_TSO_2);
16016 else if (tg3_flag(tp, 5750_PLUS)) {
16017 tg3_flag_set(tp, HW_TSO_1);
16018 tg3_flag_set(tp, TSO_BUG);
4153577a
JP		 16019 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16020 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
63c3a66f 16021 tg3_flag_clear(tp, TSO_BUG);
4153577a
JP		 16022 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16023 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16024 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
1caf13eb
MC		 16025 tg3_flag_set(tp, FW_TSO);
16026 tg3_flag_set(tp, TSO_BUG);
4153577a 16027 if (tg3_asic_rev(tp) == ASIC_REV_5705)
507399f1
MC		 16028 tp->fw_needed = FIRMWARE_TG3TSO5;
16029 else
16030 tp->fw_needed = FIRMWARE_TG3TSO;
16031 }
16032
dabc5c67 16033 /* Selectively allow TSO based on operating conditions */
6ff6f81d
MC		 16034 if (tg3_flag(tp, HW_TSO_1) ||
16035 tg3_flag(tp, HW_TSO_2) ||
16036 tg3_flag(tp, HW_TSO_3) ||
1caf13eb 16037 tg3_flag(tp, FW_TSO)) {
cf9ecf4b
MC		 16038 /* For firmware TSO, assume ASF is disabled.
16039 * We'll disable TSO later if we discover ASF
16040 * is enabled in tg3_get_eeprom_hw_cfg().
16041 */
dabc5c67 16042 tg3_flag_set(tp, TSO_CAPABLE);
cf9ecf4b 16043 } else {
dabc5c67
MC		 16044 tg3_flag_clear(tp, TSO_CAPABLE);
16045 tg3_flag_clear(tp, TSO_BUG);
16046 tp->fw_needed = NULL;
16047 }
16048
4153577a 16049 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
dabc5c67
MC		 16050 tp->fw_needed = FIRMWARE_TG3;
16051
c4dab506
NS		 16052 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16053 tp->fw_needed = FIRMWARE_TG357766;
16054
507399f1
MC		 16055 tp->irq_max = 1;
16056
63c3a66f
JP		 16057 if (tg3_flag(tp, 5750_PLUS)) {
16058 tg3_flag_set(tp, SUPPORT_MSI);
4153577a
JP		 16059 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16060 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16061 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16062 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
7544b097 16063 tp->pdev_peer == tp->pdev))
63c3a66f 16064 tg3_flag_clear(tp, SUPPORT_MSI);
7544b097 16065
63c3a66f 16066 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16067 tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16068 tg3_flag_set(tp, 1SHOT_MSI);
52c0fd83 16069 }
4f125f42 16070
63c3a66f
JP		 16071 if (tg3_flag(tp, 57765_PLUS)) {
16072 tg3_flag_set(tp, SUPPORT_MSIX);
507399f1
MC		 16073 tp->irq_max = TG3_IRQ_MAX_VECS;
16074 }
f6eb9b1f 16075 }
0e1406dd 16076
9102426a
MC		 16077 tp->txq_max = 1;
16078 tp->rxq_max = 1;
16079 if (tp->irq_max > 1) {
16080 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16081 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16082
4153577a
JP		 16083 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16084 tg3_asic_rev(tp) == ASIC_REV_5720)
9102426a
MC		 16085 tp->txq_max = tp->irq_max - 1;
16086 }
16087
b7abee6e 16088 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16089 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f 16090 tg3_flag_set(tp, SHORT_DMA_BUG);
f6eb9b1f 16091
4153577a 16092 if (tg3_asic_rev(tp) == ASIC_REV_5719)
a4cb428d 16093 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
e31aa987 16094
4153577a
JP		 16095 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16096 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16097 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16098 tg3_asic_rev(tp) == ASIC_REV_5762)
63c3a66f 16099 tg3_flag_set(tp, LRG_PROD_RING_CAP);
de9f5230 16100
63c3a66f 16101 if (tg3_flag(tp, 57765_PLUS) &&
4153577a 16102 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
63c3a66f 16103 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
b703df6f 16104
63c3a66f
JP		 16105 if (!tg3_flag(tp, 5705_PLUS) ||
16106 tg3_flag(tp, 5780_CLASS) ||
16107 tg3_flag(tp, USE_JUMBO_BDFLAG))
16108 tg3_flag_set(tp, JUMBO_CAPABLE);
0f893dc6 16109
52f4490c
MC		 16110 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16111 &pci_state_reg);
16112
708ebb3a 16113 if (pci_is_pcie(tp->pdev)) {
5e7dfd0f
MC		 16114 u16 lnkctl;
16115
63c3a66f 16116 tg3_flag_set(tp, PCI_EXPRESS);
5f5c51e3 16117
0f49bfbd 16118 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
5e7dfd0f 16119 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
4153577a 16120 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16121 tg3_flag_clear(tp, HW_TSO_2);
dabc5c67 16122 tg3_flag_clear(tp, TSO_CAPABLE);
7196cd6c 16123 }
4153577a
JP		 16124 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16125 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16126 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16127 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
63c3a66f 16128 tg3_flag_set(tp, CLKREQ_BUG);
4153577a 16129 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
63c3a66f 16130 tg3_flag_set(tp, L1PLLPD_EN);
c7835a77 16131 }
4153577a 16132 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
708ebb3a
JM		 16133 /* BCM5785 devices are effectively PCIe devices, and should
16134 * follow PCIe codepaths, but do not have a PCIe capabilities
16135 * section.
93a700a9 16136 */
63c3a66f
JP		 16137 tg3_flag_set(tp, PCI_EXPRESS);
16138 } else if (!tg3_flag(tp, 5705_PLUS) ||
16139 tg3_flag(tp, 5780_CLASS)) {
52f4490c
MC		 16140 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16141 if (!tp->pcix_cap) {
2445e461
MC		 16142 dev_err(&tp->pdev->dev,
16143 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 16144 return -EIO;
16145 }
16146
16147 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
63c3a66f 16148 tg3_flag_set(tp, PCIX_MODE);
52f4490c 16149 }
1da177e4 16150
399de50b
MC		 16151 /* If we have an AMD 762 or VIA K8T800 chipset, write
16152 * reordering to the mailbox registers done by the host
16153 * controller can cause major troubles. We read back from
16154 * every mailbox register write to force the writes to be
16155 * posted to the chip in order.
16156 */
4143470c 16157 if (pci_dev_present(tg3_write_reorder_chipsets) &&
63c3a66f
JP		 16158 !tg3_flag(tp, PCI_EXPRESS))
16159 tg3_flag_set(tp, MBOX_WRITE_REORDER);
399de50b 16160
69fc4053
MC		 16161 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16162 &tp->pci_cacheline_sz);
16163 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16164 &tp->pci_lat_timer);
4153577a 16165 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
1da177e4
LT		 16166 tp->pci_lat_timer < 64) {
16167 tp->pci_lat_timer = 64;
69fc4053
MC		 16168 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16169 tp->pci_lat_timer);
1da177e4
LT		 16170 }
16171
16821285
MC		 16172 /* Important! -- It is critical that the PCI-X hw workaround
16173 * situation is decided before the first MMIO register access.
16174 */
4153577a 16175 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
52f4490c
MC		 16176 /* 5700 BX chips need to have their TX producer index
16177 * mailboxes written twice to workaround a bug.
16178 */
63c3a66f 16179 tg3_flag_set(tp, TXD_MBOX_HWBUG);
1da177e4 16180
52f4490c 16181 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 16182 *
16183 * The workaround is to use indirect register accesses
16184 * for all chip writes not to mailbox registers.
16185 */
63c3a66f 16186 if (tg3_flag(tp, PCIX_MODE)) {
1da177e4 16187 u32 pm_reg;
1da177e4 16188
63c3a66f 16189 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16190
16191 /* The chip can have it's power management PCI config
16192 * space registers clobbered due to this bug.
16193 * So explicitly force the chip into D0 here.
16194 */
9974a356 16195 pci_read_config_dword(tp->pdev,
0319f30e 16196 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16197 &pm_reg);
16198 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16199 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356 16200 pci_write_config_dword(tp->pdev,
0319f30e 16201 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16202 pm_reg);
16203
16204 /* Also, force SERR#/PERR# in PCI command. */
16205 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16206 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16207 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16208 }
16209 }
16210
1da177e4 16211 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
63c3a66f 16212 tg3_flag_set(tp, PCI_HIGH_SPEED);
1da177e4 16213 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
63c3a66f 16214 tg3_flag_set(tp, PCI_32BIT);
1da177e4
LT		 16215
16216 /* Chip-specific fixup from Broadcom driver */
4153577a 16217 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
1da177e4
LT		 16218 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16219 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16220 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16221 }
16222
1ee582d8 16223 /* Default fast path register access methods */
20094930 16224 tp->read32 = tg3_read32;
1ee582d8 16225 tp->write32 = tg3_write32;
09ee929c 16226 tp->read32_mbox = tg3_read32;
20094930 16227 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 16228 tp->write32_tx_mbox = tg3_write32;
16229 tp->write32_rx_mbox = tg3_write32;
16230
16231 /* Various workaround register access methods */
63c3a66f 16232 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
1ee582d8 16233 tp->write32 = tg3_write_indirect_reg32;
4153577a 16234 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
63c3a66f 16235 (tg3_flag(tp, PCI_EXPRESS) &&
4153577a 16236 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
98efd8a6
MC		 16237 /*
16238 * Back to back register writes can cause problems on these
16239 * chips, the workaround is to read back all reg writes
16240 * except those to mailbox regs.
16241 *
16242 * See tg3_write_indirect_reg32().
16243 */
1ee582d8 16244 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 16245 }
16246
63c3a66f 16247 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
1ee582d8 16248 tp->write32_tx_mbox = tg3_write32_tx_mbox;
63c3a66f 16249 if (tg3_flag(tp, MBOX_WRITE_REORDER))
1ee582d8
MC		 16250 tp->write32_rx_mbox = tg3_write_flush_reg32;
16251 }
20094930 16252
63c3a66f 16253 if (tg3_flag(tp, ICH_WORKAROUND)) {
6892914f
MC		 16254 tp->read32 = tg3_read_indirect_reg32;
16255 tp->write32 = tg3_write_indirect_reg32;
16256 tp->read32_mbox = tg3_read_indirect_mbox;
16257 tp->write32_mbox = tg3_write_indirect_mbox;
16258 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16259 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16260
16261 iounmap(tp->regs);
22abe310 16262 tp->regs = NULL;
6892914f
MC		 16263
16264 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16265 pci_cmd &= ~PCI_COMMAND_MEMORY;
16266 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16267 }
4153577a 16268 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 16269 tp->read32_mbox = tg3_read32_mbox_5906;
16270 tp->write32_mbox = tg3_write32_mbox_5906;
16271 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16272 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16273 }
6892914f 16274
bbadf503 16275 if (tp->write32 == tg3_write_indirect_reg32 ||
63c3a66f 16276 (tg3_flag(tp, PCIX_MODE) &&
4153577a
JP		 16277 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16278 tg3_asic_rev(tp) == ASIC_REV_5701)))
63c3a66f 16279 tg3_flag_set(tp, SRAM_USE_CONFIG);
bbadf503 16280
16821285
MC		 16281 /* The memory arbiter has to be enabled in order for SRAM accesses
16282 * to succeed. Normally on powerup the tg3 chip firmware will make
16283 * sure it is enabled, but other entities such as system netboot
16284 * code might disable it.
16285 */
16286 val = tr32(MEMARB_MODE);
16287 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16288
9dc5e342 16289 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
4153577a 16290 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
9dc5e342
MC		 16291 tg3_flag(tp, 5780_CLASS)) {
16292 if (tg3_flag(tp, PCIX_MODE)) {
16293 pci_read_config_dword(tp->pdev,
16294 tp->pcix_cap + PCI_X_STATUS,
16295 &val);
16296 tp->pci_fn = val & 0x7;
16297 }
4153577a
JP		 16298 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16299 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16300 tg3_asic_rev(tp) == ASIC_REV_5720) {
9dc5e342 16301 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
857001f0
MC		 16302 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16303 val = tr32(TG3_CPMU_STATUS);
16304
4153577a 16305 if (tg3_asic_rev(tp) == ASIC_REV_5717)
857001f0
MC		 16306 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16307 else
9dc5e342
MC		 16308 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16309 TG3_CPMU_STATUS_FSHFT_5719;
69f11c99
MC		 16310 }
16311
7e6c63f0
HM		 16312 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16313 tp->write32_tx_mbox = tg3_write_flush_reg32;
16314 tp->write32_rx_mbox = tg3_write_flush_reg32;
16315 }
16316
7d0c41ef 16317 /* Get eeprom hw config before calling tg3_set_power_state().
63c3a66f 16318 * In particular, the TG3_FLAG_IS_NIC flag must be
7d0c41ef
MC		 16319 * determined before calling tg3_set_power_state() so that
16320 * we know whether or not to switch out of Vaux power.
16321 * When the flag is set, it means that GPIO1 is used for eeprom
16322 * write protect and also implies that it is a LOM where GPIOs
16323 * are not used to switch power.
6aa20a22 16324 */
7d0c41ef
MC		 16325 tg3_get_eeprom_hw_cfg(tp);
16326
1caf13eb 16327 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
cf9ecf4b
MC		 16328 tg3_flag_clear(tp, TSO_CAPABLE);
16329 tg3_flag_clear(tp, TSO_BUG);
16330 tp->fw_needed = NULL;
16331 }
16332
63c3a66f 16333 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 16334 /* Allow reads and writes to the
16335 * APE register and memory space.
16336 */
16337 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 16338 PCISTATE_ALLOW_APE_SHMEM_WR |
16339 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 16340 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16341 pci_state_reg);
c9cab24e
MC		 16342
16343 tg3_ape_lock_init(tp);
0d3031d9
MC		 16344 }
16345
16821285
MC		 16346 /* Set up tp->grc_local_ctrl before calling
16347 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16348 * will bring 5700's external PHY out of reset.
314fba34
MC		 16349 * It is also used as eeprom write protect on LOMs.
16350 */
16351 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
4153577a 16352 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
63c3a66f 16353 tg3_flag(tp, EEPROM_WRITE_PROT))
314fba34
MC		 16354 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16355 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 16356 /* Unused GPIO3 must be driven as output on 5752 because there
16357 * are no pull-up resistors on unused GPIO pins.
16358 */
4153577a 16359 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc 16360 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 16361
4153577a
JP		 16362 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16363 tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 16364 tg3_flag(tp, 57765_CLASS))
af36e6b6
MC		 16365 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16366
8d519ab2
MC		 16367 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16368 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 16369 /* Turn off the debug UART. */
16370 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
63c3a66f 16371 if (tg3_flag(tp, IS_NIC))
5f0c4a3c
MC		 16372 /* Keep VMain power. */
16373 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16374 GRC_LCLCTRL_GPIO_OUTPUT0;
16375 }
16376
4153577a 16377 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c86a8560
MC		 16378 tp->grc_local_ctrl |=
16379 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16380
16821285
MC		 16381 /* Switch out of Vaux if it is a NIC */
16382 tg3_pwrsrc_switch_to_vmain(tp);
1da177e4 16383
1da177e4
LT		 16384 /* Derive initial jumbo mode from MTU assigned in
16385 * ether_setup() via the alloc_etherdev() call
16386 */
63c3a66f
JP		 16387 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16388 tg3_flag_set(tp, JUMBO_RING_ENABLE);
1da177e4
LT		 16389
16390 /* Determine WakeOnLan speed to use. */
4153577a
JP		 16391 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16392 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16393 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16394 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
63c3a66f 16395 tg3_flag_clear(tp, WOL_SPEED_100MB);
1da177e4 16396 } else {
63c3a66f 16397 tg3_flag_set(tp, WOL_SPEED_100MB);
1da177e4
LT		 16398 }
16399
4153577a 16400 if (tg3_asic_rev(tp) == ASIC_REV_5906)
f07e9af3 16401 tp->phy_flags |= TG3_PHYFLG_IS_FET;
7f97a4bd 16402
1da177e4 16403 /* A few boards don't want Ethernet@WireSpeed phy feature */
4153577a
JP		 16404 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16405 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16406 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16407 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
f07e9af3
MC		 16408 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16409 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16410 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
1da177e4 16411
4153577a
JP		 16412 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16413 tg3_chip_rev(tp) == CHIPREV_5704_AX)
f07e9af3 16414 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
4153577a 16415 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
f07e9af3 16416 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
1da177e4 16417
63c3a66f 16418 if (tg3_flag(tp, 5705_PLUS) &&
f07e9af3 16419 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a
JP		 16420 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16421 tg3_asic_rev(tp) != ASIC_REV_57780 &&
63c3a66f 16422 !tg3_flag(tp, 57765_PLUS)) {
4153577a
JP		 16423 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16424 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16425 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16426 tg3_asic_rev(tp) == ASIC_REV_5761) {
d4011ada
MC		 16427 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16428 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
f07e9af3 16429 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
c1d2a196 16430 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
f07e9af3 16431 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
321d32a0 16432 } else
f07e9af3 16433 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
c424cb24 16434 }
1da177e4 16435
4153577a
JP		 16436 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16437 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 16438 tp->phy_otp = tg3_read_otp_phycfg(tp);
16439 if (tp->phy_otp == 0)
16440 tp->phy_otp = TG3_OTP_DEFAULT;
16441 }
16442
63c3a66f 16443 if (tg3_flag(tp, CPMU_PRESENT))
8ef21428
MC		 16444 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16445 else
16446 tp->mi_mode = MAC_MI_MODE_BASE;
16447
1da177e4 16448 tp->coalesce_mode = 0;
4153577a
JP		 16449 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16450 tg3_chip_rev(tp) != CHIPREV_5700_BX)
1da177e4
LT		 16451 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16452
4d958473 16453 /* Set these bits to enable statistics workaround. */
4153577a
JP		 16454 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16455 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16456 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
4d958473
MC		 16457 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16458 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16459 }
16460
4153577a
JP		 16461 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16462 tg3_asic_rev(tp) == ASIC_REV_57780)
63c3a66f 16463 tg3_flag_set(tp, USE_PHYLIB);
57e6983c 16464
158d7abd
MC		 16465 err = tg3_mdio_init(tp);
16466 if (err)
16467 return err;
1da177e4
LT		 16468
16469 /* Initialize data/descriptor byte/word swapping. */
16470 val = tr32(GRC_MODE);
4153577a
JP		 16471 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16472 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 16473 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16474 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16475 GRC_MODE_B2HRX_ENABLE |
16476 GRC_MODE_HTX2B_ENABLE |
16477 GRC_MODE_HOST_STACKUP);
16478 else
16479 val &= GRC_MODE_HOST_STACKUP;
16480
1da177e4
LT		 16481 tw32(GRC_MODE, val | tp->grc_mode);
16482
16483 tg3_switch_clocks(tp);
16484
16485 /* Clear this out for sanity. */
16486 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16487
16488 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16489 &pci_state_reg);
16490 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
63c3a66f 16491 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
4153577a
JP		 16492 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16493 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16494 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16495 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
1da177e4
LT		 16496 void __iomem *sram_base;
16497
16498 /* Write some dummy words into the SRAM status block
16499 * area, see if it reads back correctly. If the return
16500 * value is bad, force enable the PCIX workaround.
16501 */
16502 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16503
16504 writel(0x00000000, sram_base);
16505 writel(0x00000000, sram_base + 4);
16506 writel(0xffffffff, sram_base + 4);
16507 if (readl(sram_base) != 0x00000000)
63c3a66f 16508 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16509 }
16510 }
16511
16512 udelay(50);
16513 tg3_nvram_init(tp);
16514
c4dab506
NS		 16515 /* If the device has an NVRAM, no need to load patch firmware */
16516 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16517 !tg3_flag(tp, NO_NVRAM))
16518 tp->fw_needed = NULL;
16519
1da177e4
LT		 16520 grc_misc_cfg = tr32(GRC_MISC_CFG);
16521 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16522
4153577a 16523 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
1da177e4
LT		 16524 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16525 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
63c3a66f 16526 tg3_flag_set(tp, IS_5788);
1da177e4 16527
63c3a66f 16528 if (!tg3_flag(tp, IS_5788) &&
4153577a 16529 tg3_asic_rev(tp) != ASIC_REV_5700)
63c3a66f
JP		 16530 tg3_flag_set(tp, TAGGED_STATUS);
16531 if (tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 16532 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16533 HOSTCC_MODE_CLRTICK_TXBD);
16534
16535 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16536 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16537 tp->misc_host_ctrl);
16538 }
16539
3bda1258 16540 /* Preserve the APE MAC_MODE bits */
63c3a66f 16541 if (tg3_flag(tp, ENABLE_APE))
d2394e6b 16542 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
3bda1258 16543 else
6e01b20b 16544 tp->mac_mode = 0;
3bda1258 16545
3d567e0e 16546 if (tg3_10_100_only_device(tp, ent))
f07e9af3 16547 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
1da177e4
LT		 16548
16549 err = tg3_phy_probe(tp);
16550 if (err) {
2445e461 16551 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 16552 /* ... but do not return immediately ... */
b02fd9e3 16553 tg3_mdio_fini(tp);
1da177e4
LT		 16554 }
16555
184b8904 16556 tg3_read_vpd(tp);
c4e6575c 16557 tg3_read_fw_ver(tp);
1da177e4 16558
f07e9af3
MC		 16559 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16560 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16561 } else {
4153577a 16562 if (tg3_asic_rev(tp) == ASIC_REV_5700)
f07e9af3 16563 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16564 else
f07e9af3 16565 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4
LT		 16566 }
16567
16568 /* 5700 {AX,BX} chips have a broken status block link
16569 * change bit implementation, so we must use the
16570 * status register in those cases.
16571 */
4153577a 16572 if (tg3_asic_rev(tp) == ASIC_REV_5700)
63c3a66f 16573 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4 16574 else
63c3a66f 16575 tg3_flag_clear(tp, USE_LINKCHG_REG);
1da177e4
LT		 16576
16577 /* The led_ctrl is set during tg3_phy_probe, here we might
16578 * have to force the link status polling mechanism based
16579 * upon subsystem IDs.
16580 */
16581 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
4153577a 16582 tg3_asic_rev(tp) == ASIC_REV_5701 &&
f07e9af3
MC		 16583 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16584 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
63c3a66f 16585 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4
LT		 16586 }
16587
16588 /* For all SERDES we poll the MAC status register. */
f07e9af3 16589 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
63c3a66f 16590 tg3_flag_set(tp, POLL_SERDES);
1da177e4 16591 else
63c3a66f 16592 tg3_flag_clear(tp, POLL_SERDES);
1da177e4 16593
9205fd9c 16594 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
d2757fc4 16595 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
4153577a 16596 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
63c3a66f 16597 tg3_flag(tp, PCIX_MODE)) {
9205fd9c 16598 tp->rx_offset = NET_SKB_PAD;
d2757fc4 16599#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
9dc7a113 16600 tp->rx_copy_thresh = ~(u16)0;
d2757fc4
MC		 16601#endif
16602 }
1da177e4 16603
2c49a44d
MC		 16604 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16605 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
7cb32cf2
MC		 16606 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16607
2c49a44d 16608 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
f92905de
MC		 16609
16610 /* Increment the rx prod index on the rx std ring by at most
16611 * 8 for these chips to workaround hw errata.
16612 */
4153577a
JP		 16613 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16614 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16615 tg3_asic_rev(tp) == ASIC_REV_5755)
f92905de
MC		 16616 tp->rx_std_max_post = 8;
16617
63c3a66f 16618 if (tg3_flag(tp, ASPM_WORKAROUND))
8ed5d97e
MC		 16619 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16620 PCIE_PWR_MGMT_L1_THRESH_MSK;
16621
1da177e4
LT		 16622 return err;
16623}
16624
49b6e95f 16625#ifdef CONFIG_SPARC
229b1ad1 16626static int tg3_get_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16627{
16628 struct net_device *dev = tp->dev;
16629 struct pci_dev *pdev = tp->pdev;
49b6e95f 16630 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 16631 const unsigned char *addr;
49b6e95f
DM		 16632 int len;
16633
16634 addr = of_get_property(dp, "local-mac-address", &len);
16635 if (addr && len == 6) {
16636 memcpy(dev->dev_addr, addr, 6);
49b6e95f 16637 return 0;
1da177e4
LT		 16638 }
16639 return -ENODEV;
16640}
16641
229b1ad1 16642static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16643{
16644 struct net_device *dev = tp->dev;
16645
16646 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
16647 return 0;
16648}
16649#endif
16650
229b1ad1 16651static int tg3_get_device_address(struct tg3 *tp)
1da177e4
LT		 16652{
16653 struct net_device *dev = tp->dev;
16654 u32 hi, lo, mac_offset;
008652b3 16655 int addr_ok = 0;
7e6c63f0 16656 int err;
1da177e4 16657
49b6e95f 16658#ifdef CONFIG_SPARC
1da177e4
LT		 16659 if (!tg3_get_macaddr_sparc(tp))
16660 return 0;
16661#endif
16662
7e6c63f0
HM		 16663 if (tg3_flag(tp, IS_SSB_CORE)) {
16664 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16665 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16666 return 0;
16667 }
16668
1da177e4 16669 mac_offset = 0x7c;
4153577a 16670 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
63c3a66f 16671 tg3_flag(tp, 5780_CLASS)) {
1da177e4
LT		 16672 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16673 mac_offset = 0xcc;
16674 if (tg3_nvram_lock(tp))
16675 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16676 else
16677 tg3_nvram_unlock(tp);
63c3a66f 16678 } else if (tg3_flag(tp, 5717_PLUS)) {
69f11c99 16679 if (tp->pci_fn & 1)
a1b950d5 16680 mac_offset = 0xcc;
69f11c99 16681 if (tp->pci_fn > 1)
a50d0796 16682 mac_offset += 0x18c;
4153577a 16683 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 16684 mac_offset = 0x10;
1da177e4
LT		 16685
16686 /* First try to get it from MAC address mailbox. */
16687 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16688 if ((hi >> 16) == 0x484b) {
16689 dev->dev_addr[0] = (hi >> 8) & 0xff;
16690 dev->dev_addr[1] = (hi >> 0) & 0xff;
16691
16692 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16693 dev->dev_addr[2] = (lo >> 24) & 0xff;
16694 dev->dev_addr[3] = (lo >> 16) & 0xff;
16695 dev->dev_addr[4] = (lo >> 8) & 0xff;
16696 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 16697
008652b3
MC		 16698 /* Some old bootcode may report a 0 MAC address in SRAM */
16699 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16700 }
16701 if (!addr_ok) {
16702 /* Next, try NVRAM. */
63c3a66f 16703 if (!tg3_flag(tp, NO_NVRAM) &&
df259d8c 16704 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 16705 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 16706 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16707 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 16708 }
16709 /* Finally just fetch it out of the MAC control regs. */
16710 else {
16711 hi = tr32(MAC_ADDR_0_HIGH);
16712 lo = tr32(MAC_ADDR_0_LOW);
16713
16714 dev->dev_addr[5] = lo & 0xff;
16715 dev->dev_addr[4] = (lo >> 8) & 0xff;
16716 dev->dev_addr[3] = (lo >> 16) & 0xff;
16717 dev->dev_addr[2] = (lo >> 24) & 0xff;
16718 dev->dev_addr[1] = hi & 0xff;
16719 dev->dev_addr[0] = (hi >> 8) & 0xff;
16720 }
1da177e4
LT		 16721 }
16722
16723 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 16724#ifdef CONFIG_SPARC
1da177e4
LT		 16725 if (!tg3_get_default_macaddr_sparc(tp))
16726 return 0;
16727#endif
16728 return -EINVAL;
16729 }
16730 return 0;
16731}
16732
59e6b434
DM		 16733#define BOUNDARY_SINGLE_CACHELINE 1
16734#define BOUNDARY_MULTI_CACHELINE 2
16735
229b1ad1 16736static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
59e6b434
DM		 16737{
16738 int cacheline_size;
16739 u8 byte;
16740 int goal;
16741
16742 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
16743 if (byte == 0)
16744 cacheline_size = 1024;
16745 else
16746 cacheline_size = (int) byte * 4;
16747
16748 /* On 5703 and later chips, the boundary bits have no
16749 * effect.
16750 */
4153577a
JP		 16751 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16752 tg3_asic_rev(tp) != ASIC_REV_5701 &&
63c3a66f 16753 !tg3_flag(tp, PCI_EXPRESS))
59e6b434
DM		 16754 goto out;
16755
16756#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
16757 goal = BOUNDARY_MULTI_CACHELINE;
16758#else
16759#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
16760 goal = BOUNDARY_SINGLE_CACHELINE;
16761#else
16762 goal = 0;
16763#endif
16764#endif
16765
63c3a66f 16766 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 16767 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
16768 goto out;
16769 }
16770
59e6b434
DM		 16771 if (!goal)
16772 goto out;
16773
16774 /* PCI controllers on most RISC systems tend to disconnect
16775 * when a device tries to burst across a cache-line boundary.
16776 * Therefore, letting tg3 do so just wastes PCI bandwidth.
16777 *
16778 * Unfortunately, for PCI-E there are only limited
16779 * write-side controls for this, and thus for reads
16780 * we will still get the disconnects. We'll also waste
16781 * these PCI cycles for both read and write for chips
16782 * other than 5700 and 5701 which do not implement the
16783 * boundary bits.
16784 */
63c3a66f 16785 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16786 switch (cacheline_size) {
16787 case 16:
16788 case 32:
16789 case 64:
16790 case 128:
16791 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16792 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
16793 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
16794 } else {
16795 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16796 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16797 }
16798 break;
16799
16800 case 256:
16801 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
16802 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
16803 break;
16804
16805 default:
16806 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16807 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16808 break;
855e1111 16809 }
63c3a66f 16810 } else if (tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16811 switch (cacheline_size) {
16812 case 16:
16813 case 32:
16814 case 64:
16815 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16816 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16817 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
16818 break;
16819 }
16820 /* fallthrough */
16821 case 128:
16822 default:
16823 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16824 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
16825 break;
855e1111 16826 }
59e6b434
DM		 16827 } else {
16828 switch (cacheline_size) {
16829 case 16:
16830 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16831 val |= (DMA_RWCTRL_READ_BNDRY_16 |
16832 DMA_RWCTRL_WRITE_BNDRY_16);
16833 break;
16834 }
16835 /* fallthrough */
16836 case 32:
16837 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16838 val |= (DMA_RWCTRL_READ_BNDRY_32 |
16839 DMA_RWCTRL_WRITE_BNDRY_32);
16840 break;
16841 }
16842 /* fallthrough */
16843 case 64:
16844 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16845 val |= (DMA_RWCTRL_READ_BNDRY_64 |
16846 DMA_RWCTRL_WRITE_BNDRY_64);
16847 break;
16848 }
16849 /* fallthrough */
16850 case 128:
16851 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16852 val |= (DMA_RWCTRL_READ_BNDRY_128 |
16853 DMA_RWCTRL_WRITE_BNDRY_128);
16854 break;
16855 }
16856 /* fallthrough */
16857 case 256:
16858 val |= (DMA_RWCTRL_READ_BNDRY_256 |
16859 DMA_RWCTRL_WRITE_BNDRY_256);
16860 break;
16861 case 512:
16862 val |= (DMA_RWCTRL_READ_BNDRY_512 |
16863 DMA_RWCTRL_WRITE_BNDRY_512);
16864 break;
16865 case 1024:
16866 default:
16867 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
16868 DMA_RWCTRL_WRITE_BNDRY_1024);
16869 break;
855e1111 16870 }
59e6b434
DM		 16871 }
16872
16873out:
16874 return val;
16875}
16876
229b1ad1 16877static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
953c96e0 16878 int size, bool to_device)
1da177e4
LT		 16879{
16880 struct tg3_internal_buffer_desc test_desc;
16881 u32 sram_dma_descs;
16882 int i, ret;
16883
16884 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
16885
16886 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
16887 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
16888 tw32(RDMAC_STATUS, 0);
16889 tw32(WDMAC_STATUS, 0);
16890
16891 tw32(BUFMGR_MODE, 0);
16892 tw32(FTQ_RESET, 0);
16893
16894 test_desc.addr_hi = ((u64) buf_dma) >> 32;
16895 test_desc.addr_lo = buf_dma & 0xffffffff;
16896 test_desc.nic_mbuf = 0x00002100;
16897 test_desc.len = size;
16898
16899 /*
16900 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
16901 * the *second* time the tg3 driver was getting loaded after an
16902 * initial scan.
16903 *
16904 * Broadcom tells me:
16905 * ...the DMA engine is connected to the GRC block and a DMA
16906 * reset may affect the GRC block in some unpredictable way...
16907 * The behavior of resets to individual blocks has not been tested.
16908 *
16909 * Broadcom noted the GRC reset will also reset all sub-components.
16910 */
16911 if (to_device) {
16912 test_desc.cqid_sqid = (13 << 8) | 2;
16913
16914 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
16915 udelay(40);
16916 } else {
16917 test_desc.cqid_sqid = (16 << 8) | 7;
16918
16919 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
16920 udelay(40);
16921 }
16922 test_desc.flags = 0x00000005;
16923
16924 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
16925 u32 val;
16926
16927 val = *(((u32 *)&test_desc) + i);
16928 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
16929 sram_dma_descs + (i * sizeof(u32)));
16930 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
16931 }
16932 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
16933
859a5887 16934 if (to_device)
1da177e4 16935 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
859a5887 16936 else
1da177e4 16937 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
1da177e4
LT		 16938
16939 ret = -ENODEV;
16940 for (i = 0; i < 40; i++) {
16941 u32 val;
16942
16943 if (to_device)
16944 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
16945 else
16946 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
16947 if ((val & 0xffff) == sram_dma_descs) {
16948 ret = 0;
16949 break;
16950 }
16951
16952 udelay(100);
16953 }
16954
16955 return ret;
16956}
16957
ded7340d 16958#define TEST_BUFFER_SIZE 0x2000
1da177e4 16959
4143470c 16960static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
895950c2
JP		 16961 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
16962 { },
16963};
16964
229b1ad1 16965static int tg3_test_dma(struct tg3 *tp)
1da177e4
LT		 16966{
16967 dma_addr_t buf_dma;
59e6b434 16968 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 16969 int ret = 0;
1da177e4 16970
4bae65c8
MC		 16971 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
16972 &buf_dma, GFP_KERNEL);
1da177e4
LT		 16973 if (!buf) {
16974 ret = -ENOMEM;
16975 goto out_nofree;
16976 }
16977
16978 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
16979 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
16980
59e6b434 16981 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 16982
63c3a66f 16983 if (tg3_flag(tp, 57765_PLUS))
cbf9ca6c
MC		 16984 goto out;
16985
63c3a66f 16986 if (tg3_flag(tp, PCI_EXPRESS)) {
1da177e4
LT		 16987 /* DMA read watermark not used on PCIE */
16988 tp->dma_rwctrl |= 0x00180000;
63c3a66f 16989 } else if (!tg3_flag(tp, PCIX_MODE)) {
4153577a
JP		 16990 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
16991 tg3_asic_rev(tp) == ASIC_REV_5750)
1da177e4
LT		 16992 tp->dma_rwctrl |= 0x003f0000;
16993 else
16994 tp->dma_rwctrl |= 0x003f000f;
16995 } else {
4153577a
JP		 16996 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
16997 tg3_asic_rev(tp) == ASIC_REV_5704) {
1da177e4 16998 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 16999 u32 read_water = 0x7;
1da177e4 17000
4a29cc2e
MC		 17001 /* If the 5704 is behind the EPB bridge, we can
17002 * do the less restrictive ONE_DMA workaround for
17003 * better performance.
17004 */
63c3a66f 17005 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
4153577a 17006 tg3_asic_rev(tp) == ASIC_REV_5704)
4a29cc2e
MC		 17007 tp->dma_rwctrl |= 0x8000;
17008 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 17009 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17010
4153577a 17011 if (tg3_asic_rev(tp) == ASIC_REV_5703)
49afdeb6 17012 read_water = 4;
59e6b434 17013 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 17014 tp->dma_rwctrl |=
17015 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17016 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17017 (1 << 23);
4153577a 17018 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
4cf78e4f
MC		 17019 /* 5780 always in PCIX mode */
17020 tp->dma_rwctrl |= 0x00144000;
4153577a 17021 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
a4e2b347
MC		 17022 /* 5714 always in PCIX mode */
17023 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 17024 } else {
17025 tp->dma_rwctrl |= 0x001b000f;
17026 }
17027 }
7e6c63f0
HM		 17028 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17029 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
1da177e4 17030
4153577a
JP		 17031 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17032 tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 17033 tp->dma_rwctrl &= 0xfffffff0;
17034
4153577a
JP		 17035 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17036 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 17037 /* Remove this if it causes problems for some boards. */
17038 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17039
17040 /* On 5700/5701 chips, we need to set this bit.
17041 * Otherwise the chip will issue cacheline transactions
17042 * to streamable DMA memory with not all the byte
17043 * enables turned on. This is an error on several
17044 * RISC PCI controllers, in particular sparc64.
17045 *
17046 * On 5703/5704 chips, this bit has been reassigned
17047 * a different meaning. In particular, it is used
17048 * on those chips to enable a PCI-X workaround.
17049 */
17050 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17051 }
17052
17053 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17054
17055#if 0
17056 /* Unneeded, already done by tg3_get_invariants. */
17057 tg3_switch_clocks(tp);
17058#endif
17059
4153577a
JP		 17060 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17061 tg3_asic_rev(tp) != ASIC_REV_5701)
1da177e4
LT		 17062 goto out;
17063
59e6b434
DM		 17064 /* It is best to perform DMA test with maximum write burst size
17065 * to expose the 5700/5701 write DMA bug.
17066 */
17067 saved_dma_rwctrl = tp->dma_rwctrl;
17068 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17069 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17070
1da177e4
LT		 17071 while (1) {
17072 u32 *p = buf, i;
17073
17074 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17075 p[i] = i;
17076
17077 /* Send the buffer to the chip. */
953c96e0 17078 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
1da177e4 17079 if (ret) {
2445e461
MC		 17080 dev_err(&tp->pdev->dev,
17081 "%s: Buffer write failed. err = %d\n",
17082 __func__, ret);
1da177e4
LT		 17083 break;
17084 }
17085
17086#if 0
17087 /* validate data reached card RAM correctly. */
17088 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17089 u32 val;
17090 tg3_read_mem(tp, 0x2100 + (i*4), &val);
17091 if (le32_to_cpu(val) != p[i]) {
2445e461
MC		 17092 dev_err(&tp->pdev->dev,
17093 "%s: Buffer corrupted on device! "
17094 "(%d != %d)\n", __func__, val, i);
1da177e4
LT		 17095 /* ret = -ENODEV here? */
17096 }
17097 p[i] = 0;
17098 }
17099#endif
17100 /* Now read it back. */
953c96e0 17101 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
1da177e4 17102 if (ret) {
5129c3a3
MC		 17103 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17104 "err = %d\n", __func__, ret);
1da177e4
LT		 17105 break;
17106 }
17107
17108 /* Verify it. */
17109 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17110 if (p[i] == i)
17111 continue;
17112
59e6b434
DM		 17113 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17114 DMA_RWCTRL_WRITE_BNDRY_16) {
17115 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 17116 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17117 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17118 break;
17119 } else {
2445e461
MC		 17120 dev_err(&tp->pdev->dev,
17121 "%s: Buffer corrupted on read back! "
17122 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 17123 ret = -ENODEV;
17124 goto out;
17125 }
17126 }
17127
17128 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17129 /* Success. */
17130 ret = 0;
17131 break;
17132 }
17133 }
59e6b434
DM		 17134 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17135 DMA_RWCTRL_WRITE_BNDRY_16) {
17136 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 17137 * now look for chipsets that are known to expose the
17138 * DMA bug without failing the test.
59e6b434 17139 */
4143470c 17140 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
6d1cfbab
MC		 17141 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17142 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
859a5887 17143 } else {
6d1cfbab
MC		 17144 /* Safe to use the calculated DMA boundary. */
17145 tp->dma_rwctrl = saved_dma_rwctrl;
859a5887 17146 }
6d1cfbab 17147
59e6b434
DM		 17148 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17149 }
1da177e4
LT		 17150
17151out:
4bae65c8 17152 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
1da177e4
LT		 17153out_nofree:
17154 return ret;
17155}
17156
229b1ad1 17157static void tg3_init_bufmgr_config(struct tg3 *tp)
1da177e4 17158{
63c3a66f 17159 if (tg3_flag(tp, 57765_PLUS)) {
666bc831
MC		 17160 tp->bufmgr_config.mbuf_read_dma_low_water =
17161 DEFAULT_MB_RDMA_LOW_WATER_5705;
17162 tp->bufmgr_config.mbuf_mac_rx_low_water =
17163 DEFAULT_MB_MACRX_LOW_WATER_57765;
17164 tp->bufmgr_config.mbuf_high_water =
17165 DEFAULT_MB_HIGH_WATER_57765;
17166
17167 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17168 DEFAULT_MB_RDMA_LOW_WATER_5705;
17169 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17170 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17171 tp->bufmgr_config.mbuf_high_water_jumbo =
17172 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
63c3a66f 17173 } else if (tg3_flag(tp, 5705_PLUS)) {
fdfec172
MC		 17174 tp->bufmgr_config.mbuf_read_dma_low_water =
17175 DEFAULT_MB_RDMA_LOW_WATER_5705;
17176 tp->bufmgr_config.mbuf_mac_rx_low_water =
17177 DEFAULT_MB_MACRX_LOW_WATER_5705;
17178 tp->bufmgr_config.mbuf_high_water =
17179 DEFAULT_MB_HIGH_WATER_5705;
4153577a 17180 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 17181 tp->bufmgr_config.mbuf_mac_rx_low_water =
17182 DEFAULT_MB_MACRX_LOW_WATER_5906;
17183 tp->bufmgr_config.mbuf_high_water =
17184 DEFAULT_MB_HIGH_WATER_5906;
17185 }
fdfec172
MC		 17186
17187 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17188 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17189 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17190 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17191 tp->bufmgr_config.mbuf_high_water_jumbo =
17192 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17193 } else {
17194 tp->bufmgr_config.mbuf_read_dma_low_water =
17195 DEFAULT_MB_RDMA_LOW_WATER;
17196 tp->bufmgr_config.mbuf_mac_rx_low_water =
17197 DEFAULT_MB_MACRX_LOW_WATER;
17198 tp->bufmgr_config.mbuf_high_water =
17199 DEFAULT_MB_HIGH_WATER;
17200
17201 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17202 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17203 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17204 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17205 tp->bufmgr_config.mbuf_high_water_jumbo =
17206 DEFAULT_MB_HIGH_WATER_JUMBO;
17207 }
1da177e4
LT		 17208
17209 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17210 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17211}
17212
229b1ad1 17213static char *tg3_phy_string(struct tg3 *tp)
1da177e4 17214{
79eb6904
MC		 17215 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17216 case TG3_PHY_ID_BCM5400: return "5400";
17217 case TG3_PHY_ID_BCM5401: return "5401";
17218 case TG3_PHY_ID_BCM5411: return "5411";
17219 case TG3_PHY_ID_BCM5701: return "5701";
17220 case TG3_PHY_ID_BCM5703: return "5703";
17221 case TG3_PHY_ID_BCM5704: return "5704";
17222 case TG3_PHY_ID_BCM5705: return "5705";
17223 case TG3_PHY_ID_BCM5750: return "5750";
17224 case TG3_PHY_ID_BCM5752: return "5752";
17225 case TG3_PHY_ID_BCM5714: return "5714";
17226 case TG3_PHY_ID_BCM5780: return "5780";
17227 case TG3_PHY_ID_BCM5755: return "5755";
17228 case TG3_PHY_ID_BCM5787: return "5787";
17229 case TG3_PHY_ID_BCM5784: return "5784";
17230 case TG3_PHY_ID_BCM5756: return "5722/5756";
17231 case TG3_PHY_ID_BCM5906: return "5906";
17232 case TG3_PHY_ID_BCM5761: return "5761";
17233 case TG3_PHY_ID_BCM5718C: return "5718C";
17234 case TG3_PHY_ID_BCM5718S: return "5718S";
17235 case TG3_PHY_ID_BCM57765: return "57765";
302b500b 17236 case TG3_PHY_ID_BCM5719C: return "5719C";
6418f2c1 17237 case TG3_PHY_ID_BCM5720C: return "5720C";
c65a17f4 17238 case TG3_PHY_ID_BCM5762: return "5762C";
79eb6904 17239 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 17240 case 0: return "serdes";
17241 default: return "unknown";
855e1111 17242 }
1da177e4
LT		 17243}
17244
229b1ad1 17245static char *tg3_bus_string(struct tg3 *tp, char *str)
f9804ddb 17246{
63c3a66f 17247 if (tg3_flag(tp, PCI_EXPRESS)) {
f9804ddb
MC		 17248 strcpy(str, "PCI Express");
17249 return str;
63c3a66f 17250 } else if (tg3_flag(tp, PCIX_MODE)) {
f9804ddb
MC		 17251 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17252
17253 strcpy(str, "PCIX:");
17254
17255 if ((clock_ctrl == 7) ||
17256 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17257 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17258 strcat(str, "133MHz");
17259 else if (clock_ctrl == 0)
17260 strcat(str, "33MHz");
17261 else if (clock_ctrl == 2)
17262 strcat(str, "50MHz");
17263 else if (clock_ctrl == 4)
17264 strcat(str, "66MHz");
17265 else if (clock_ctrl == 6)
17266 strcat(str, "100MHz");
f9804ddb
MC		 17267 } else {
17268 strcpy(str, "PCI:");
63c3a66f 17269 if (tg3_flag(tp, PCI_HIGH_SPEED))
f9804ddb
MC		 17270 strcat(str, "66MHz");
17271 else
17272 strcat(str, "33MHz");
17273 }
63c3a66f 17274 if (tg3_flag(tp, PCI_32BIT))
f9804ddb
MC		 17275 strcat(str, ":32-bit");
17276 else
17277 strcat(str, ":64-bit");
17278 return str;
17279}
17280
229b1ad1 17281static void tg3_init_coal(struct tg3 *tp)
15f9850d
DM		 17282{
17283 struct ethtool_coalesce *ec = &tp->coal;
17284
17285 memset(ec, 0, sizeof(*ec));
17286 ec->cmd = ETHTOOL_GCOALESCE;
17287 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17288 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17289 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17290 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17291 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17292 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17293 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17294 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17295 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17296
17297 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17298 HOSTCC_MODE_CLRTICK_TXBD)) {
17299 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17300 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17301 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17302 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17303 }
d244c892 17304
63c3a66f 17305 if (tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 17306 ec->rx_coalesce_usecs_irq = 0;
17307 ec->tx_coalesce_usecs_irq = 0;
17308 ec->stats_block_coalesce_usecs = 0;
17309 }
15f9850d
DM		 17310}
17311
229b1ad1 17312static int tg3_init_one(struct pci_dev *pdev,
1da177e4
LT		 17313 const struct pci_device_id *ent)
17314{
1da177e4
LT		 17315 struct net_device *dev;
17316 struct tg3 *tp;
5865fc1b 17317 int i, err;
646c9edd 17318 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 17319 char str[40];
72f2afb8 17320 u64 dma_mask, persist_dma_mask;
c8f44aff 17321 netdev_features_t features = 0;
1da177e4 17322
05dbe005 17323 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 17324
17325 err = pci_enable_device(pdev);
17326 if (err) {
2445e461 17327 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 17328 return err;
17329 }
17330
1da177e4
LT		 17331 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17332 if (err) {
2445e461 17333 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 17334 goto err_out_disable_pdev;
17335 }
17336
17337 pci_set_master(pdev);
17338
fe5f5787 17339 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 17340 if (!dev) {
1da177e4 17341 err = -ENOMEM;
5865fc1b 17342 goto err_out_free_res;
1da177e4
LT		 17343 }
17344
1da177e4
LT		 17345 SET_NETDEV_DEV(dev, &pdev->dev);
17346
1da177e4
LT		 17347 tp = netdev_priv(dev);
17348 tp->pdev = pdev;
17349 tp->dev = dev;
1da177e4
LT		 17350 tp->rx_mode = TG3_DEF_RX_MODE;
17351 tp->tx_mode = TG3_DEF_TX_MODE;
9c13cb8b 17352 tp->irq_sync = 1;
8ef21428 17353
1da177e4
LT		 17354 if (tg3_debug > 0)
17355 tp->msg_enable = tg3_debug;
17356 else
17357 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17358
7e6c63f0
HM		 17359 if (pdev_is_ssb_gige_core(pdev)) {
17360 tg3_flag_set(tp, IS_SSB_CORE);
17361 if (ssb_gige_must_flush_posted_writes(pdev))
17362 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17363 if (ssb_gige_one_dma_at_once(pdev))
17364 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17365 if (ssb_gige_have_roboswitch(pdev))
17366 tg3_flag_set(tp, ROBOSWITCH);
17367 if (ssb_gige_is_rgmii(pdev))
17368 tg3_flag_set(tp, RGMII_MODE);
17369 }
17370
1da177e4
LT		 17371 /* The word/byte swap controls here control register access byte
17372 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17373 * setting below.
17374 */
17375 tp->misc_host_ctrl =
17376 MISC_HOST_CTRL_MASK_PCI_INT |
17377 MISC_HOST_CTRL_WORD_SWAP |
17378 MISC_HOST_CTRL_INDIR_ACCESS |
17379 MISC_HOST_CTRL_PCISTATE_RW;
17380
17381 /* The NONFRM (non-frame) byte/word swap controls take effect
17382 * on descriptor entries, anything which isn't packet data.
17383 *
17384 * The StrongARM chips on the board (one for tx, one for rx)
17385 * are running in big-endian mode.
17386 */
17387 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17388 GRC_MODE_WSWAP_NONFRM_DATA);
17389#ifdef __BIG_ENDIAN
17390 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17391#endif
17392 spin_lock_init(&tp->lock);
1da177e4 17393 spin_lock_init(&tp->indirect_lock);
c4028958 17394 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 17395
d5fe488a 17396 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 17397 if (!tp->regs) {
ab96b241 17398 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 17399 err = -ENOMEM;
17400 goto err_out_free_dev;
17401 }
17402
c9cab24e
MC		 17403 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17404 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17405 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17406 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17407 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 17408 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
c9cab24e
MC		 17409 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17410 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4
MC		 17411 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17412 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17413 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17414 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727) {
c9cab24e
MC		 17415 tg3_flag_set(tp, ENABLE_APE);
17416 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17417 if (!tp->aperegs) {
17418 dev_err(&pdev->dev,
17419 "Cannot map APE registers, aborting\n");
17420 err = -ENOMEM;
17421 goto err_out_iounmap;
17422 }
17423 }
17424
1da177e4
LT		 17425 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17426 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 17427
1da177e4 17428 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 17429 dev->watchdog_timeo = TG3_TX_TIMEOUT;
2ffcc981 17430 dev->netdev_ops = &tg3_netdev_ops;
1da177e4 17431 dev->irq = pdev->irq;
1da177e4 17432
3d567e0e 17433 err = tg3_get_invariants(tp, ent);
1da177e4 17434 if (err) {
ab96b241
MC		 17435 dev_err(&pdev->dev,
17436 "Problem fetching invariants of chip, aborting\n");
c9cab24e 17437 goto err_out_apeunmap;
1da177e4
LT		 17438 }
17439
4a29cc2e
MC		 17440 /* The EPB bridge inside 5714, 5715, and 5780 and any
17441 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 17442 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17443 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17444 * do DMA address check in tg3_start_xmit().
17445 */
63c3a66f 17446 if (tg3_flag(tp, IS_5788))
284901a9 17447 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
63c3a66f 17448 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
50cf156a 17449 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 17450#ifdef CONFIG_HIGHMEM
6a35528a 17451 dma_mask = DMA_BIT_MASK(64);
72f2afb8 17452#endif
4a29cc2e 17453 } else
6a35528a 17454 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 17455
17456 /* Configure DMA attributes. */
284901a9 17457 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 17458 err = pci_set_dma_mask(pdev, dma_mask);
17459 if (!err) {
0da0606f 17460 features |= NETIF_F_HIGHDMA;
72f2afb8
MC		 17461 err = pci_set_consistent_dma_mask(pdev,
17462 persist_dma_mask);
17463 if (err < 0) {
ab96b241
MC		 17464 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17465 "DMA for consistent allocations\n");
c9cab24e 17466 goto err_out_apeunmap;
72f2afb8
MC		 17467 }
17468 }
17469 }
284901a9
YH		 17470 if (err || dma_mask == DMA_BIT_MASK(32)) {
17471 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 17472 if (err) {
ab96b241
MC		 17473 dev_err(&pdev->dev,
17474 "No usable DMA configuration, aborting\n");
c9cab24e 17475 goto err_out_apeunmap;
72f2afb8
MC		 17476 }
17477 }
17478
fdfec172 17479 tg3_init_bufmgr_config(tp);
1da177e4 17480
f646968f 17481 features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
0da0606f
MC		 17482
17483 /* 5700 B0 chips do not support checksumming correctly due
17484 * to hardware bugs.
17485 */
4153577a 17486 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
0da0606f
MC		 17487 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17488
17489 if (tg3_flag(tp, 5755_PLUS))
17490 features |= NETIF_F_IPV6_CSUM;
17491 }
17492
4e3a7aaa
MC		 17493 /* TSO is on by default on chips that support hardware TSO.
17494 * Firmware TSO on older chips gives lower performance, so it
17495 * is off by default, but can be enabled using ethtool.
17496 */
63c3a66f
JP		 17497 if ((tg3_flag(tp, HW_TSO_1) ||
17498 tg3_flag(tp, HW_TSO_2) ||
17499 tg3_flag(tp, HW_TSO_3)) &&
0da0606f
MC		 17500 (features & NETIF_F_IP_CSUM))
17501 features |= NETIF_F_TSO;
63c3a66f 17502 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
0da0606f
MC		 17503 if (features & NETIF_F_IPV6_CSUM)
17504 features |= NETIF_F_TSO6;
63c3a66f 17505 if (tg3_flag(tp, HW_TSO_3) ||
4153577a
JP		 17506 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17507 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17508 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17509 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17510 tg3_asic_rev(tp) == ASIC_REV_57780)
0da0606f 17511 features |= NETIF_F_TSO_ECN;
b0026624 17512 }
1da177e4 17513
d542fe27
MC		 17514 dev->features |= features;
17515 dev->vlan_features |= features;
17516
06c03c02
MB		 17517 /*
17518 * Add loopback capability only for a subset of devices that support
17519 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17520 * loopback for the remaining devices.
17521 */
4153577a 17522 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
06c03c02
MB		 17523 !tg3_flag(tp, CPMU_PRESENT))
17524 /* Add the loopback capability */
0da0606f
MC		 17525 features |= NETIF_F_LOOPBACK;
17526
0da0606f 17527 dev->hw_features |= features;
06c03c02 17528
4153577a 17529 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
63c3a66f 17530 !tg3_flag(tp, TSO_CAPABLE) &&
1da177e4 17531 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
63c3a66f 17532 tg3_flag_set(tp, MAX_RXPEND_64);
1da177e4
LT		 17533 tp->rx_pending = 63;
17534 }
17535
1da177e4
LT		 17536 err = tg3_get_device_address(tp);
17537 if (err) {
ab96b241
MC		 17538 dev_err(&pdev->dev,
17539 "Could not obtain valid ethernet address, aborting\n");
c9cab24e 17540 goto err_out_apeunmap;
c88864df
MC		 17541 }
17542
1da177e4
LT		 17543 /*
17544 * Reset chip in case UNDI or EFI driver did not shutdown
17545 * DMA self test will enable WDMAC and we'll see (spurious)
17546 * pending DMA on the PCI bus at that point.
17547 */
17548 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17549 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 17550 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 17551 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 17552 }
17553
17554 err = tg3_test_dma(tp);
17555 if (err) {
ab96b241 17556 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
c88864df 17557 goto err_out_apeunmap;
1da177e4
LT		 17558 }
17559
78f90dcf
MC		 17560 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17561 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17562 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6fd45cb8 17563 for (i = 0; i < tp->irq_max; i++) {
78f90dcf
MC		 17564 struct tg3_napi *tnapi = &tp->napi[i];
17565
17566 tnapi->tp = tp;
17567 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17568
17569 tnapi->int_mbox = intmbx;
93a700a9 17570 if (i <= 4)
78f90dcf
MC		 17571 intmbx += 0x8;
17572 else
17573 intmbx += 0x4;
17574
17575 tnapi->consmbox = rcvmbx;
17576 tnapi->prodmbox = sndmbx;
17577
66cfd1bd 17578 if (i)
78f90dcf 17579 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
66cfd1bd 17580 else
78f90dcf 17581 tnapi->coal_now = HOSTCC_MODE_NOW;
78f90dcf 17582
63c3a66f 17583 if (!tg3_flag(tp, SUPPORT_MSIX))
78f90dcf
MC		 17584 break;
17585
17586 /*
17587 * If we support MSIX, we'll be using RSS. If we're using
17588 * RSS, the first vector only handles link interrupts and the
17589 * remaining vectors handle rx and tx interrupts. Reuse the
17590 * mailbox values for the next iteration. The values we setup
17591 * above are still useful for the single vectored mode.
17592 */
17593 if (!i)
17594 continue;
17595
17596 rcvmbx += 0x8;
17597
17598 if (sndmbx & 0x4)
17599 sndmbx -= 0x4;
17600 else
17601 sndmbx += 0xc;
17602 }
17603
15f9850d
DM		 17604 tg3_init_coal(tp);
17605
c49a1561
MC		 17606 pci_set_drvdata(pdev, dev);
17607
4153577a
JP		 17608 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17609 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17610 tg3_asic_rev(tp) == ASIC_REV_5762)
fb4ce8ad
MC		 17611 tg3_flag_set(tp, PTP_CAPABLE);
17612
21f7638e
MC		 17613 tg3_timer_init(tp);
17614
402e1398
MC		 17615 tg3_carrier_off(tp);
17616
1da177e4
LT		 17617 err = register_netdev(dev);
17618 if (err) {
ab96b241 17619 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 17620 goto err_out_apeunmap;
1da177e4
LT		 17621 }
17622
05dbe005
JP		 17623 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17624 tp->board_part_number,
4153577a 17625 tg3_chip_rev_id(tp),
05dbe005
JP		 17626 tg3_bus_string(tp, str),
17627 dev->dev_addr);
1da177e4 17628
f07e9af3 17629 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7
MC		 17630 struct phy_device *phydev;
17631 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
5129c3a3
MC		 17632 netdev_info(dev,
17633 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
05dbe005 17634 phydev->drv->name, dev_name(&phydev->dev));
f07e9af3
MC		 17635 } else {
17636 char *ethtype;
17637
17638 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17639 ethtype = "10/100Base-TX";
17640 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17641 ethtype = "1000Base-SX";
17642 else
17643 ethtype = "10/100/1000Base-T";
17644
5129c3a3 17645 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
47007831
MC		 17646 "(WireSpeed[%d], EEE[%d])\n",
17647 tg3_phy_string(tp), ethtype,
17648 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17649 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
f07e9af3 17650 }
05dbe005
JP		 17651
17652 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
dc668910 17653 (dev->features & NETIF_F_RXCSUM) != 0,
63c3a66f 17654 tg3_flag(tp, USE_LINKCHG_REG) != 0,
f07e9af3 17655 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
63c3a66f
JP		 17656 tg3_flag(tp, ENABLE_ASF) != 0,
17657 tg3_flag(tp, TSO_CAPABLE) != 0);
05dbe005
JP		 17658 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17659 tp->dma_rwctrl,
17660 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17661 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4 17662
b45aa2f6
MC		 17663 pci_save_state(pdev);
17664
1da177e4
LT		 17665 return 0;
17666
0d3031d9
MC		 17667err_out_apeunmap:
17668 if (tp->aperegs) {
17669 iounmap(tp->aperegs);
17670 tp->aperegs = NULL;
17671 }
17672
1da177e4 17673err_out_iounmap:
6892914f
MC		 17674 if (tp->regs) {
17675 iounmap(tp->regs);
22abe310 17676 tp->regs = NULL;
6892914f 17677 }
1da177e4
LT		 17678
17679err_out_free_dev:
17680 free_netdev(dev);
17681
17682err_out_free_res:
17683 pci_release_regions(pdev);
17684
17685err_out_disable_pdev:
c80dc13d
GS		 17686 if (pci_is_enabled(pdev))
17687 pci_disable_device(pdev);
1da177e4
LT		 17688 pci_set_drvdata(pdev, NULL);
17689 return err;
17690}
17691
229b1ad1 17692static void tg3_remove_one(struct pci_dev *pdev)
1da177e4
LT		 17693{
17694 struct net_device *dev = pci_get_drvdata(pdev);
17695
17696 if (dev) {
17697 struct tg3 *tp = netdev_priv(dev);
17698
e3c5530b 17699 release_firmware(tp->fw);
077f849d 17700
db219973 17701 tg3_reset_task_cancel(tp);
158d7abd 17702
e730c823 17703 if (tg3_flag(tp, USE_PHYLIB)) {
b02fd9e3 17704 tg3_phy_fini(tp);
158d7abd 17705 tg3_mdio_fini(tp);
b02fd9e3 17706 }
158d7abd 17707
1da177e4 17708 unregister_netdev(dev);
0d3031d9
MC		 17709 if (tp->aperegs) {
17710 iounmap(tp->aperegs);
17711 tp->aperegs = NULL;
17712 }
6892914f
MC		 17713 if (tp->regs) {
17714 iounmap(tp->regs);
22abe310 17715 tp->regs = NULL;
6892914f 17716 }
1da177e4
LT		 17717 free_netdev(dev);
17718 pci_release_regions(pdev);
17719 pci_disable_device(pdev);
17720 pci_set_drvdata(pdev, NULL);
17721 }
17722}
17723
aa6027ca 17724#ifdef CONFIG_PM_SLEEP
c866b7ea 17725static int tg3_suspend(struct device *device)
1da177e4 17726{
c866b7ea 17727 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17728 struct net_device *dev = pci_get_drvdata(pdev);
17729 struct tg3 *tp = netdev_priv(dev);
17730 int err;
17731
17732 if (!netif_running(dev))
17733 return 0;
17734
db219973 17735 tg3_reset_task_cancel(tp);
b02fd9e3 17736 tg3_phy_stop(tp);
1da177e4
LT		 17737 tg3_netif_stop(tp);
17738
21f7638e 17739 tg3_timer_stop(tp);
1da177e4 17740
f47c11ee 17741 tg3_full_lock(tp, 1);
1da177e4 17742 tg3_disable_ints(tp);
f47c11ee 17743 tg3_full_unlock(tp);
1da177e4
LT		 17744
17745 netif_device_detach(dev);
17746
f47c11ee 17747 tg3_full_lock(tp, 0);
944d980e 17748 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
63c3a66f 17749 tg3_flag_clear(tp, INIT_COMPLETE);
f47c11ee 17750 tg3_full_unlock(tp);
1da177e4 17751
c866b7ea 17752 err = tg3_power_down_prepare(tp);
1da177e4 17753 if (err) {
b02fd9e3
MC		 17754 int err2;
17755
f47c11ee 17756 tg3_full_lock(tp, 0);
1da177e4 17757
63c3a66f 17758 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 17759 err2 = tg3_restart_hw(tp, true);
b02fd9e3 17760 if (err2)
b9ec6c1b 17761 goto out;
1da177e4 17762
21f7638e 17763 tg3_timer_start(tp);
1da177e4
LT		 17764
17765 netif_device_attach(dev);
17766 tg3_netif_start(tp);
17767
b9ec6c1b 17768out:
f47c11ee 17769 tg3_full_unlock(tp);
b02fd9e3
MC		 17770
17771 if (!err2)
17772 tg3_phy_start(tp);
1da177e4
LT		 17773 }
17774
17775 return err;
17776}
17777
c866b7ea 17778static int tg3_resume(struct device *device)
1da177e4 17779{
c866b7ea 17780 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17781 struct net_device *dev = pci_get_drvdata(pdev);
17782 struct tg3 *tp = netdev_priv(dev);
17783 int err;
17784
17785 if (!netif_running(dev))
17786 return 0;
17787
1da177e4
LT		 17788 netif_device_attach(dev);
17789
f47c11ee 17790 tg3_full_lock(tp, 0);
1da177e4 17791
2e460fc0
NS		 17792 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
17793
63c3a66f 17794 tg3_flag_set(tp, INIT_COMPLETE);
942d1af0
NS		 17795 err = tg3_restart_hw(tp,
17796 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
b9ec6c1b
MC		 17797 if (err)
17798 goto out;
1da177e4 17799
21f7638e 17800 tg3_timer_start(tp);
1da177e4 17801
1da177e4
LT		 17802 tg3_netif_start(tp);
17803
b9ec6c1b 17804out:
f47c11ee 17805 tg3_full_unlock(tp);
1da177e4 17806
b02fd9e3
MC		 17807 if (!err)
17808 tg3_phy_start(tp);
17809
b9ec6c1b 17810 return err;
1da177e4 17811}
42df36a6 17812#endif /* CONFIG_PM_SLEEP */
1da177e4 17813
c866b7ea
RW		 17814static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
17815
4c305fa2
NS		 17816static void tg3_shutdown(struct pci_dev *pdev)
17817{
17818 struct net_device *dev = pci_get_drvdata(pdev);
17819 struct tg3 *tp = netdev_priv(dev);
17820
17821 rtnl_lock();
17822 netif_device_detach(dev);
17823
17824 if (netif_running(dev))
17825 dev_close(dev);
17826
17827 if (system_state == SYSTEM_POWER_OFF)
17828 tg3_power_down(tp);
17829
17830 rtnl_unlock();
17831}
17832
b45aa2f6
MC		 17833/**
17834 * tg3_io_error_detected - called when PCI error is detected
17835 * @pdev: Pointer to PCI device
17836 * @state: The current pci connection state
17837 *
17838 * This function is called after a PCI bus error affecting
17839 * this device has been detected.
17840 */
17841static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
17842 pci_channel_state_t state)
17843{
17844 struct net_device *netdev = pci_get_drvdata(pdev);
17845 struct tg3 *tp = netdev_priv(netdev);
17846 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
17847
17848 netdev_info(netdev, "PCI I/O error detected\n");
17849
17850 rtnl_lock();
17851
d8af4dfd
GS		 17852 /* We probably don't have netdev yet */
17853 if (!netdev || !netif_running(netdev))
b45aa2f6
MC		 17854 goto done;
17855
17856 tg3_phy_stop(tp);
17857
17858 tg3_netif_stop(tp);
17859
21f7638e 17860 tg3_timer_stop(tp);
b45aa2f6
MC		 17861
17862 /* Want to make sure that the reset task doesn't run */
db219973 17863 tg3_reset_task_cancel(tp);
b45aa2f6
MC		 17864
17865 netif_device_detach(netdev);
17866
17867 /* Clean up software state, even if MMIO is blocked */
17868 tg3_full_lock(tp, 0);
17869 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
17870 tg3_full_unlock(tp);
17871
17872done:
72bb72b0 17873 if (state == pci_channel_io_perm_failure) {
68293099
DB		 17874 if (netdev) {
17875 tg3_napi_enable(tp);
17876 dev_close(netdev);
17877 }
b45aa2f6 17878 err = PCI_ERS_RESULT_DISCONNECT;
72bb72b0 17879 } else {
b45aa2f6 17880 pci_disable_device(pdev);
72bb72b0 17881 }
b45aa2f6
MC		 17882
17883 rtnl_unlock();
17884
17885 return err;
17886}
17887
17888/**
17889 * tg3_io_slot_reset - called after the pci bus has been reset.
17890 * @pdev: Pointer to PCI device
17891 *
17892 * Restart the card from scratch, as if from a cold-boot.
17893 * At this point, the card has exprienced a hard reset,
17894 * followed by fixups by BIOS, and has its config space
17895 * set up identically to what it was at cold boot.
17896 */
17897static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
17898{
17899 struct net_device *netdev = pci_get_drvdata(pdev);
17900 struct tg3 *tp = netdev_priv(netdev);
17901 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
17902 int err;
17903
17904 rtnl_lock();
17905
17906 if (pci_enable_device(pdev)) {
68293099
DB		 17907 dev_err(&pdev->dev,
17908 "Cannot re-enable PCI device after reset.\n");
b45aa2f6
MC		 17909 goto done;
17910 }
17911
17912 pci_set_master(pdev);
17913 pci_restore_state(pdev);
17914 pci_save_state(pdev);
17915
68293099 17916 if (!netdev || !netif_running(netdev)) {
b45aa2f6
MC		 17917 rc = PCI_ERS_RESULT_RECOVERED;
17918 goto done;
17919 }
17920
17921 err = tg3_power_up(tp);
bed9829f 17922 if (err)
b45aa2f6 17923 goto done;
b45aa2f6
MC		 17924
17925 rc = PCI_ERS_RESULT_RECOVERED;
17926
17927done:
68293099 17928 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
72bb72b0
MC		 17929 tg3_napi_enable(tp);
17930 dev_close(netdev);
17931 }
b45aa2f6
MC		 17932 rtnl_unlock();
17933
17934 return rc;
17935}
17936
17937/**
17938 * tg3_io_resume - called when traffic can start flowing again.
17939 * @pdev: Pointer to PCI device
17940 *
17941 * This callback is called when the error recovery driver tells
17942 * us that its OK to resume normal operation.
17943 */
17944static void tg3_io_resume(struct pci_dev *pdev)
17945{
17946 struct net_device *netdev = pci_get_drvdata(pdev);
17947 struct tg3 *tp = netdev_priv(netdev);
17948 int err;
17949
17950 rtnl_lock();
17951
17952 if (!netif_running(netdev))
17953 goto done;
17954
17955 tg3_full_lock(tp, 0);
2e460fc0 17956 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
63c3a66f 17957 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 17958 err = tg3_restart_hw(tp, true);
b45aa2f6 17959 if (err) {
35763066 17960 tg3_full_unlock(tp);
b45aa2f6
MC		 17961 netdev_err(netdev, "Cannot restart hardware after reset.\n");
17962 goto done;
17963 }
17964
17965 netif_device_attach(netdev);
17966
21f7638e 17967 tg3_timer_start(tp);
b45aa2f6
MC		 17968
17969 tg3_netif_start(tp);
17970
35763066
NNS		 17971 tg3_full_unlock(tp);
17972
b45aa2f6
MC		 17973 tg3_phy_start(tp);
17974
17975done:
17976 rtnl_unlock();
17977}
17978
3646f0e5 17979static const struct pci_error_handlers tg3_err_handler = {
b45aa2f6
MC		 17980 .error_detected = tg3_io_error_detected,
17981 .slot_reset = tg3_io_slot_reset,
17982 .resume = tg3_io_resume
17983};
17984
1da177e4
LT		 17985static struct pci_driver tg3_driver = {
17986 .name = DRV_MODULE_NAME,
17987 .id_table = tg3_pci_tbl,
17988 .probe = tg3_init_one,
229b1ad1 17989 .remove = tg3_remove_one,
b45aa2f6 17990 .err_handler = &tg3_err_handler,
42df36a6 17991 .driver.pm = &tg3_pm_ops,
4c305fa2 17992 .shutdown = tg3_shutdown,
1da177e4
LT		 17993};
17994
8dbb0dc2 17995module_pci_driver(tg3_driver);
Linux kernel - Deliverables
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