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tg3: cleanup an error path in tg3_phy_reset_5703_4_5()
[deliverable/linux.git] / drivers / net / ethernet / broadcom / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
b681b65d 7 * Copyright (C) 2005-2013 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
6867c843 21#include <linux/stringify.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
14c85021 27#include <linux/in.h>
a6b7a407 28#include <linux/interrupt.h>
1da177e4
LT		 29#include <linux/ioport.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/ethtool.h>
3110f5f5 35#include <linux/mdio.h>
1da177e4 36#include <linux/mii.h>
158d7abd 37#include <linux/phy.h>
a9daf367 38#include <linux/brcmphy.h>
e565eec3 39#include <linux/if.h>
1da177e4
LT		 40#include <linux/if_vlan.h>
41#include <linux/ip.h>
42#include <linux/tcp.h>
43#include <linux/workqueue.h>
61487480 44#include <linux/prefetch.h>
f9a5f7d3 45#include <linux/dma-mapping.h>
077f849d 46#include <linux/firmware.h>
7e6c63f0 47#include <linux/ssb/ssb_driver_gige.h>
aed93e0b
MC		 48#include <linux/hwmon.h>
49#include <linux/hwmon-sysfs.h>
1da177e4
LT		 50
51#include <net/checksum.h>
c9bdd4b5 52#include <net/ip.h>
1da177e4 53
27fd9de8 54#include <linux/io.h>
1da177e4 55#include <asm/byteorder.h>
27fd9de8 56#include <linux/uaccess.h>
1da177e4 57
be947307
MC		 58#include <uapi/linux/net_tstamp.h>
59#include <linux/ptp_clock_kernel.h>
60
49b6e95f 61#ifdef CONFIG_SPARC
1da177e4 62#include <asm/idprom.h>
49b6e95f 63#include <asm/prom.h>
1da177e4
LT		 64#endif
65
63532394
MC		 66#define BAR_0 0
67#define BAR_2 2
68
1da177e4
LT		 69#include "tg3.h"
70
63c3a66f
JP		 71/* Functions & macros to verify TG3_FLAGS types */
72
73static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
74{
75 return test_bit(flag, bits);
76}
77
78static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
79{
80 set_bit(flag, bits);
81}
82
83static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
84{
85 clear_bit(flag, bits);
86}
87
88#define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90#define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92#define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
94
1da177e4 95#define DRV_MODULE_NAME "tg3"
6867c843 96#define TG3_MAJ_NUM 3
20170e77 97#define TG3_MIN_NUM 136
6867c843
MC		 98#define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
20170e77 100#define DRV_MODULE_RELDATE "Jan 03, 2014"
1da177e4 101
fd6d3f0e
MC		 102#define RESET_KIND_SHUTDOWN 0
103#define RESET_KIND_INIT 1
104#define RESET_KIND_SUSPEND 2
105
1da177e4
LT		 106#define TG3_DEF_RX_MODE 0
107#define TG3_DEF_TX_MODE 0
108#define TG3_DEF_MSG_ENABLE \
109 (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK | \
112 NETIF_MSG_TIMER | \
113 NETIF_MSG_IFDOWN | \
114 NETIF_MSG_IFUP | \
115 NETIF_MSG_RX_ERR | \
116 NETIF_MSG_TX_ERR)
117
520b2756
MC		 118#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
119
1da177e4
LT		 120/* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
122 */
63c3a66f 123
1da177e4
LT		 124#define TG3_TX_TIMEOUT (5 * HZ)
125
126/* hardware minimum and maximum for a single frame's data payload */
127#define TG3_MIN_MTU 60
128#define TG3_MAX_MTU(tp) \
63c3a66f 129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 130
131/* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
134 */
7cb32cf2 135#define TG3_RX_STD_RING_SIZE(tp) \
63c3a66f 136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
1da177e4 138#define TG3_DEF_RX_RING_PENDING 200
7cb32cf2 139#define TG3_RX_JMB_RING_SIZE(tp) \
63c3a66f 140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
1da177e4
LT		 142#define TG3_DEF_RX_JUMBO_RING_PENDING 100
143
144/* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
149 */
1da177e4
LT		 150
151#define TG3_TX_RING_SIZE 512
152#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
153
2c49a44d
MC		 154#define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156#define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158#define TG3_RX_RCB_RING_BYTES(tp) \
7cb32cf2 159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
1da177e4
LT		 160#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
161 TG3_TX_RING_SIZE)
1da177e4
LT		 162#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
163
287be12e
MC		 164#define TG3_DMA_BYTE_ENAB 64
165
166#define TG3_RX_STD_DMA_SZ 1536
167#define TG3_RX_JMB_DMA_SZ 9046
168
169#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
170
171#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 173
2c49a44d
MC		 174#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
2b2cdb65 176
2c49a44d
MC		 177#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
2b2cdb65 179
d2757fc4
MC		 180/* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
184 *
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
190 */
191#define TG3_RX_COPY_THRESHOLD 256
192#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
194#else
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
196#endif
197
81389f57
MC		 198#if (NET_IP_ALIGN != 0)
199#define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
200#else
9205fd9c 201#define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
81389f57
MC		 202#endif
203
1da177e4 204/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 205#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
55086ad9 206#define TG3_TX_BD_DMA_MAX_2K 2048
a4cb428d 207#define TG3_TX_BD_DMA_MAX_4K 4096
1da177e4 208
ad829268
MC		 209#define TG3_RAW_IP_ALIGN 2
210
e565eec3
MC		 211#define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
212#define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
213
c6cdf436 214#define TG3_FW_UPDATE_TIMEOUT_SEC 5
21f7638e 215#define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
c6cdf436 216
077f849d 217#define FIRMWARE_TG3 "tigon/tg3.bin"
c4dab506 218#define FIRMWARE_TG357766 "tigon/tg357766.bin"
077f849d
JSR		 219#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
220#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
221
229b1ad1 222static char version[] =
05dbe005 223 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 224
225MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
226MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
227MODULE_LICENSE("GPL");
228MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 229MODULE_FIRMWARE(FIRMWARE_TG3);
230MODULE_FIRMWARE(FIRMWARE_TG3TSO);
231MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
232
1da177e4
LT		 233static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
234module_param(tg3_debug, int, 0);
235MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
236
3d567e0e
NNS		 237#define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238#define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
239
a3aa1884 240static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
3d567e0e
NNS		 259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
263 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
264 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
3d567e0e
NNS		 266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
267 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
268 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
7e6c63f0 271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
13185217 272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
13185217 273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
3d567e0e
NNS		 274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
275 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
3d567e0e
NNS		 280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
281 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
3d567e0e
NNS		 289 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
290 PCI_VENDOR_ID_LENOVO,
291 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217 293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
3d567e0e
NNS		 294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
295 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
3d567e0e
NNS		 314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
318 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
319 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321d32a0
MC		 320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
3d567e0e
NNS		 322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
323 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
5e7ccf20 324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6 325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
79d49695 326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
5001e2f6 327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
b0f75221
MC		 328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
3d567e0e
NNS		 332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
333 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
335 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
302b500b 336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
ba1f3c76 337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
02eca3f5 338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
d3f677af 339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
c86a8560
MC		 340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
68273712
NS		 343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
13185217
HK		 348 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
349 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
353 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
354 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
1dcb14d9 355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
13185217 356 {}
1da177e4
LT		 357};
358
359MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
360
50da859d 361static const struct {
1da177e4 362 const char string[ETH_GSTRING_LEN];
48fa55a0 363} ethtool_stats_keys[] = {
1da177e4
LT		 364 { "rx_octets" },
365 { "rx_fragments" },
366 { "rx_ucast_packets" },
367 { "rx_mcast_packets" },
368 { "rx_bcast_packets" },
369 { "rx_fcs_errors" },
370 { "rx_align_errors" },
371 { "rx_xon_pause_rcvd" },
372 { "rx_xoff_pause_rcvd" },
373 { "rx_mac_ctrl_rcvd" },
374 { "rx_xoff_entered" },
375 { "rx_frame_too_long_errors" },
376 { "rx_jabbers" },
377 { "rx_undersize_packets" },
378 { "rx_in_length_errors" },
379 { "rx_out_length_errors" },
380 { "rx_64_or_less_octet_packets" },
381 { "rx_65_to_127_octet_packets" },
382 { "rx_128_to_255_octet_packets" },
383 { "rx_256_to_511_octet_packets" },
384 { "rx_512_to_1023_octet_packets" },
385 { "rx_1024_to_1522_octet_packets" },
386 { "rx_1523_to_2047_octet_packets" },
387 { "rx_2048_to_4095_octet_packets" },
388 { "rx_4096_to_8191_octet_packets" },
389 { "rx_8192_to_9022_octet_packets" },
390
391 { "tx_octets" },
392 { "tx_collisions" },
393
394 { "tx_xon_sent" },
395 { "tx_xoff_sent" },
396 { "tx_flow_control" },
397 { "tx_mac_errors" },
398 { "tx_single_collisions" },
399 { "tx_mult_collisions" },
400 { "tx_deferred" },
401 { "tx_excessive_collisions" },
402 { "tx_late_collisions" },
403 { "tx_collide_2times" },
404 { "tx_collide_3times" },
405 { "tx_collide_4times" },
406 { "tx_collide_5times" },
407 { "tx_collide_6times" },
408 { "tx_collide_7times" },
409 { "tx_collide_8times" },
410 { "tx_collide_9times" },
411 { "tx_collide_10times" },
412 { "tx_collide_11times" },
413 { "tx_collide_12times" },
414 { "tx_collide_13times" },
415 { "tx_collide_14times" },
416 { "tx_collide_15times" },
417 { "tx_ucast_packets" },
418 { "tx_mcast_packets" },
419 { "tx_bcast_packets" },
420 { "tx_carrier_sense_errors" },
421 { "tx_discards" },
422 { "tx_errors" },
423
424 { "dma_writeq_full" },
425 { "dma_write_prioq_full" },
426 { "rxbds_empty" },
427 { "rx_discards" },
428 { "rx_errors" },
429 { "rx_threshold_hit" },
430
431 { "dma_readq_full" },
432 { "dma_read_prioq_full" },
433 { "tx_comp_queue_full" },
434
435 { "ring_set_send_prod_index" },
436 { "ring_status_update" },
437 { "nic_irqs" },
438 { "nic_avoided_irqs" },
4452d099
MC		 439 { "nic_tx_threshold_hit" },
440
441 { "mbuf_lwm_thresh_hit" },
1da177e4
LT		 442};
443
48fa55a0 444#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
93df8b8f
NNS		 445#define TG3_NVRAM_TEST 0
446#define TG3_LINK_TEST 1
447#define TG3_REGISTER_TEST 2
448#define TG3_MEMORY_TEST 3
449#define TG3_MAC_LOOPB_TEST 4
450#define TG3_PHY_LOOPB_TEST 5
451#define TG3_EXT_LOOPB_TEST 6
452#define TG3_INTERRUPT_TEST 7
48fa55a0
MC		 453
454
50da859d 455static const struct {
4cafd3f5 456 const char string[ETH_GSTRING_LEN];
48fa55a0 457} ethtool_test_keys[] = {
93df8b8f
NNS		 458 [TG3_NVRAM_TEST] = { "nvram test (online) " },
459 [TG3_LINK_TEST] = { "link test (online) " },
460 [TG3_REGISTER_TEST] = { "register test (offline)" },
461 [TG3_MEMORY_TEST] = { "memory test (offline)" },
462 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
463 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
464 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
465 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
4cafd3f5
MC		 466};
467
48fa55a0
MC		 468#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
469
470
b401e9e2
MC		 471static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
472{
473 writel(val, tp->regs + off);
474}
475
476static u32 tg3_read32(struct tg3 *tp, u32 off)
477{
de6f31eb 478 return readl(tp->regs + off);
b401e9e2
MC		 479}
480
0d3031d9
MC		 481static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
482{
483 writel(val, tp->aperegs + off);
484}
485
486static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
487{
de6f31eb 488 return readl(tp->aperegs + off);
0d3031d9
MC		 489}
490
1da177e4
LT		 491static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
492{
6892914f
MC		 493 unsigned long flags;
494
495 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 499}
500
501static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
502{
503 writel(val, tp->regs + off);
504 readl(tp->regs + off);
1da177e4
LT		 505}
506
6892914f 507static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 508{
6892914f
MC		 509 unsigned long flags;
510 u32 val;
511
512 spin_lock_irqsave(&tp->indirect_lock, flags);
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
516 return val;
517}
518
519static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
520{
521 unsigned long flags;
522
523 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
525 TG3_64BIT_REG_LOW, val);
526 return;
527 }
66711e66 528 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
530 TG3_64BIT_REG_LOW, val);
531 return;
1da177e4 532 }
6892914f
MC		 533
534 spin_lock_irqsave(&tp->indirect_lock, flags);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
537 spin_unlock_irqrestore(&tp->indirect_lock, flags);
538
539 /* In indirect mode when disabling interrupts, we also need
540 * to clear the interrupt bit in the GRC local ctrl register.
541 */
542 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
543 (val == 0x1)) {
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
546 }
547}
548
549static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
550{
551 unsigned long flags;
552 u32 val;
553
554 spin_lock_irqsave(&tp->indirect_lock, flags);
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
557 spin_unlock_irqrestore(&tp->indirect_lock, flags);
558 return val;
559}
560
b401e9e2
MC		 561/* usec_wait specifies the wait time in usec when writing to certain registers
562 * where it is unsafe to read back the register without some delay.
563 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
564 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
565 */
566static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 567{
63c3a66f 568 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
b401e9e2
MC		 569 /* Non-posted methods */
570 tp->write32(tp, off, val);
571 else {
572 /* Posted method */
573 tg3_write32(tp, off, val);
574 if (usec_wait)
575 udelay(usec_wait);
576 tp->read32(tp, off);
577 }
578 /* Wait again after the read for the posted method to guarantee that
579 * the wait time is met.
580 */
581 if (usec_wait)
582 udelay(usec_wait);
1da177e4
LT		 583}
584
09ee929c
MC		 585static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
586{
587 tp->write32_mbox(tp, off, val);
7e6c63f0
HM		 588 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
589 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
590 !tg3_flag(tp, ICH_WORKAROUND)))
6892914f 591 tp->read32_mbox(tp, off);
09ee929c
MC		 592}
593
20094930 594static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 595{
596 void __iomem *mbox = tp->regs + off;
597 writel(val, mbox);
63c3a66f 598 if (tg3_flag(tp, TXD_MBOX_HWBUG))
1da177e4 599 writel(val, mbox);
7e6c63f0
HM		 600 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
601 tg3_flag(tp, FLUSH_POSTED_WRITES))
1da177e4
LT		 602 readl(mbox);
603}
604
b5d3772c
MC		 605static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
606{
de6f31eb 607 return readl(tp->regs + off + GRCMBOX_BASE);
b5d3772c
MC		 608}
609
610static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
611{
612 writel(val, tp->regs + off + GRCMBOX_BASE);
613}
614
c6cdf436 615#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 616#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
c6cdf436
MC		 617#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930 620
c6cdf436
MC		 621#define tw32(reg, val) tp->write32(tp, reg, val)
622#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
623#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
624#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 625
626static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
627{
6892914f
MC		 628 unsigned long flags;
629
4153577a 630 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 631 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
632 return;
633
6892914f 634 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 635 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 638
bbadf503
MC		 639 /* Always leave this as zero. */
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
641 } else {
642 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
643 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 644
bbadf503
MC		 645 /* Always leave this as zero. */
646 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
647 }
648 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 649}
650
1da177e4
LT		 651static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
652{
6892914f
MC		 653 unsigned long flags;
654
4153577a 655 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 656 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
657 *val = 0;
658 return;
659 }
660
6892914f 661 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 662 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 665
bbadf503
MC		 666 /* Always leave this as zero. */
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
668 } else {
669 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
670 *val = tr32(TG3PCI_MEM_WIN_DATA);
671
672 /* Always leave this as zero. */
673 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
674 }
6892914f 675 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 676}
677
0d3031d9
MC		 678static void tg3_ape_lock_init(struct tg3 *tp)
679{
680 int i;
6f5c8f83 681 u32 regbase, bit;
f92d9dc1 682
4153577a 683 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 684 regbase = TG3_APE_LOCK_GRANT;
685 else
686 regbase = TG3_APE_PER_LOCK_GRANT;
0d3031d9
MC		 687
688 /* Make sure the driver hasn't any stale locks. */
78f94dc7
MC		 689 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
690 switch (i) {
691 case TG3_APE_LOCK_PHY0:
692 case TG3_APE_LOCK_PHY1:
693 case TG3_APE_LOCK_PHY2:
694 case TG3_APE_LOCK_PHY3:
695 bit = APE_LOCK_GRANT_DRIVER;
696 break;
697 default:
698 if (!tp->pci_fn)
699 bit = APE_LOCK_GRANT_DRIVER;
700 else
701 bit = 1 << tp->pci_fn;
702 }
703 tg3_ape_write32(tp, regbase + 4 * i, bit);
6f5c8f83
MC		 704 }
705
0d3031d9
MC		 706}
707
708static int tg3_ape_lock(struct tg3 *tp, int locknum)
709{
710 int i, off;
711 int ret = 0;
6f5c8f83 712 u32 status, req, gnt, bit;
0d3031d9 713
63c3a66f 714 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 715 return 0;
716
717 switch (locknum) {
6f5c8f83 718 case TG3_APE_LOCK_GPIO:
4153577a 719 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 720 return 0;
33f401ae
MC		 721 case TG3_APE_LOCK_GRC:
722 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 723 if (!tp->pci_fn)
724 bit = APE_LOCK_REQ_DRIVER;
725 else
726 bit = 1 << tp->pci_fn;
33f401ae 727 break;
8151ad57
MC		 728 case TG3_APE_LOCK_PHY0:
729 case TG3_APE_LOCK_PHY1:
730 case TG3_APE_LOCK_PHY2:
731 case TG3_APE_LOCK_PHY3:
732 bit = APE_LOCK_REQ_DRIVER;
733 break;
33f401ae
MC		 734 default:
735 return -EINVAL;
0d3031d9
MC		 736 }
737
4153577a 738 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
f92d9dc1
MC		 739 req = TG3_APE_LOCK_REQ;
740 gnt = TG3_APE_LOCK_GRANT;
741 } else {
742 req = TG3_APE_PER_LOCK_REQ;
743 gnt = TG3_APE_PER_LOCK_GRANT;
744 }
745
0d3031d9
MC		 746 off = 4 * locknum;
747
6f5c8f83 748 tg3_ape_write32(tp, req + off, bit);
0d3031d9
MC		 749
750 /* Wait for up to 1 millisecond to acquire lock. */
751 for (i = 0; i < 100; i++) {
f92d9dc1 752 status = tg3_ape_read32(tp, gnt + off);
6f5c8f83 753 if (status == bit)
0d3031d9 754 break;
6d446ec3
GS		 755 if (pci_channel_offline(tp->pdev))
756 break;
757
0d3031d9
MC		 758 udelay(10);
759 }
760
6f5c8f83 761 if (status != bit) {
0d3031d9 762 /* Revoke the lock request. */
6f5c8f83 763 tg3_ape_write32(tp, gnt + off, bit);
0d3031d9
MC		 764 ret = -EBUSY;
765 }
766
767 return ret;
768}
769
770static void tg3_ape_unlock(struct tg3 *tp, int locknum)
771{
6f5c8f83 772 u32 gnt, bit;
0d3031d9 773
63c3a66f 774 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 775 return;
776
777 switch (locknum) {
6f5c8f83 778 case TG3_APE_LOCK_GPIO:
4153577a 779 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 780 return;
33f401ae
MC		 781 case TG3_APE_LOCK_GRC:
782 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 783 if (!tp->pci_fn)
784 bit = APE_LOCK_GRANT_DRIVER;
785 else
786 bit = 1 << tp->pci_fn;
33f401ae 787 break;
8151ad57
MC		 788 case TG3_APE_LOCK_PHY0:
789 case TG3_APE_LOCK_PHY1:
790 case TG3_APE_LOCK_PHY2:
791 case TG3_APE_LOCK_PHY3:
792 bit = APE_LOCK_GRANT_DRIVER;
793 break;
33f401ae
MC		 794 default:
795 return;
0d3031d9
MC		 796 }
797
4153577a 798 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 799 gnt = TG3_APE_LOCK_GRANT;
800 else
801 gnt = TG3_APE_PER_LOCK_GRANT;
802
6f5c8f83 803 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
0d3031d9
MC		 804}
805
b65a372b 806static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
fd6d3f0e 807{
fd6d3f0e
MC		 808 u32 apedata;
809
b65a372b
MC		 810 while (timeout_us) {
811 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
812 return -EBUSY;
813
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
815 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
816 break;
817
818 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
819
820 udelay(10);
821 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
822 }
823
824 return timeout_us ? 0 : -EBUSY;
825}
826
cf8d55ae
MC		 827static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
828{
829 u32 i, apedata;
830
831 for (i = 0; i < timeout_us / 10; i++) {
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
833
834 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
835 break;
836
837 udelay(10);
838 }
839
840 return i == timeout_us / 10;
841}
842
86449944
MC		 843static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
844 u32 len)
cf8d55ae
MC		 845{
846 int err;
847 u32 i, bufoff, msgoff, maxlen, apedata;
848
849 if (!tg3_flag(tp, APE_HAS_NCSI))
850 return 0;
851
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
853 if (apedata != APE_SEG_SIG_MAGIC)
854 return -ENODEV;
855
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
857 if (!(apedata & APE_FW_STATUS_READY))
858 return -EAGAIN;
859
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
861 TG3_APE_SHMEM_BASE;
862 msgoff = bufoff + 2 * sizeof(u32);
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
864
865 while (len) {
866 u32 length;
867
868 /* Cap xfer sizes to scratchpad limits. */
869 length = (len > maxlen) ? maxlen : len;
870 len -= length;
871
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
873 if (!(apedata & APE_FW_STATUS_READY))
874 return -EAGAIN;
875
876 /* Wait for up to 1 msec for APE to service previous event. */
877 err = tg3_ape_event_lock(tp, 1000);
878 if (err)
879 return err;
880
881 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
882 APE_EVENT_STATUS_SCRTCHPD_READ |
883 APE_EVENT_STATUS_EVENT_PENDING;
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
885
886 tg3_ape_write32(tp, bufoff, base_off);
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
888
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
891
892 base_off += length;
893
894 if (tg3_ape_wait_for_event(tp, 30000))
895 return -EAGAIN;
896
897 for (i = 0; length; i += 4, length -= 4) {
898 u32 val = tg3_ape_read32(tp, msgoff + i);
899 memcpy(data, &val, sizeof(u32));
900 data++;
901 }
902 }
903
904 return 0;
905}
906
b65a372b
MC		 907static int tg3_ape_send_event(struct tg3 *tp, u32 event)
908{
909 int err;
910 u32 apedata;
fd6d3f0e
MC		 911
912 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
913 if (apedata != APE_SEG_SIG_MAGIC)
b65a372b 914 return -EAGAIN;
fd6d3f0e
MC		 915
916 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
917 if (!(apedata & APE_FW_STATUS_READY))
b65a372b 918 return -EAGAIN;
fd6d3f0e
MC		 919
920 /* Wait for up to 1 millisecond for APE to service previous event. */
b65a372b
MC		 921 err = tg3_ape_event_lock(tp, 1000);
922 if (err)
923 return err;
fd6d3f0e 924
b65a372b
MC		 925 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
926 event | APE_EVENT_STATUS_EVENT_PENDING);
fd6d3f0e 927
b65a372b
MC		 928 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
929 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
fd6d3f0e 930
b65a372b 931 return 0;
fd6d3f0e
MC		 932}
933
934static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
935{
936 u32 event;
937 u32 apedata;
938
939 if (!tg3_flag(tp, ENABLE_APE))
940 return;
941
942 switch (kind) {
943 case RESET_KIND_INIT:
944 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
945 APE_HOST_SEG_SIG_MAGIC);
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
947 APE_HOST_SEG_LEN_MAGIC);
948 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
949 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
950 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
951 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
952 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
953 APE_HOST_BEHAV_NO_PHYLOCK);
954 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
955 TG3_APE_HOST_DRVR_STATE_START);
956
957 event = APE_EVENT_STATUS_STATE_START;
958 break;
959 case RESET_KIND_SHUTDOWN:
960 /* With the interface we are currently using,
961 * APE does not track driver state. Wiping
962 * out the HOST SEGMENT SIGNATURE forces
963 * the APE to assume OS absent status.
964 */
965 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
966
967 if (device_may_wakeup(&tp->pdev->dev) &&
968 tg3_flag(tp, WOL_ENABLE)) {
969 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
970 TG3_APE_HOST_WOL_SPEED_AUTO);
971 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
972 } else
973 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
974
975 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
976
977 event = APE_EVENT_STATUS_STATE_UNLOAD;
978 break;
fd6d3f0e
MC		 979 default:
980 return;
981 }
982
983 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
984
985 tg3_ape_send_event(tp, event);
986}
987
1da177e4
LT		 988static void tg3_disable_ints(struct tg3 *tp)
989{
89aeb3bc
MC		 990 int i;
991
1da177e4
LT		 992 tw32(TG3PCI_MISC_HOST_CTRL,
993 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 994 for (i = 0; i < tp->irq_max; i++)
995 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 996}
997
1da177e4
LT		 998static void tg3_enable_ints(struct tg3 *tp)
999{
89aeb3bc 1000 int i;
89aeb3bc 1001
bbe832c0
MC		 1002 tp->irq_sync = 0;
1003 wmb();
1004
1da177e4
LT		 1005 tw32(TG3PCI_MISC_HOST_CTRL,
1006 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 1007
f89f38b8 1008 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 1009 for (i = 0; i < tp->irq_cnt; i++) {
1010 struct tg3_napi *tnapi = &tp->napi[i];
c6cdf436 1011
898a56f8 1012 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
63c3a66f 1013 if (tg3_flag(tp, 1SHOT_MSI))
89aeb3bc 1014 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 1015
f89f38b8 1016 tp->coal_now |= tnapi->coal_now;
89aeb3bc 1017 }
f19af9c2
MC		 1018
1019 /* Force an initial interrupt */
63c3a66f 1020 if (!tg3_flag(tp, TAGGED_STATUS) &&
f19af9c2
MC		 1021 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1022 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1023 else
f89f38b8
MC		 1024 tw32(HOSTCC_MODE, tp->coal_now);
1025
1026 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 1027}
1028
17375d25 1029static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 1030{
17375d25 1031 struct tg3 *tp = tnapi->tp;
898a56f8 1032 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 1033 unsigned int work_exists = 0;
1034
1035 /* check for phy events */
63c3a66f 1036 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
04237ddd
MC		 1037 if (sblk->status & SD_STATUS_LINK_CHG)
1038 work_exists = 1;
1039 }
f891ea16
MC		 1040
1041 /* check for TX work to do */
1042 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1043 work_exists = 1;
1044
1045 /* check for RX work to do */
1046 if (tnapi->rx_rcb_prod_idx &&
8d9d7cfc 1047 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 1048 work_exists = 1;
1049
1050 return work_exists;
1051}
1052
17375d25 1053/* tg3_int_reenable
04237ddd
MC		 1054 * similar to tg3_enable_ints, but it accurately determines whether there
1055 * is new work pending and can return without flushing the PIO write
6aa20a22 1056 * which reenables interrupts
1da177e4 1057 */
17375d25 1058static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 1059{
17375d25
MC		 1060 struct tg3 *tp = tnapi->tp;
1061
898a56f8 1062 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 1063 mmiowb();
1064
fac9b83e
DM		 1065 /* When doing tagged status, this work check is unnecessary.
1066 * The last_tag we write above tells the chip which piece of
1067 * work we've completed.
1068 */
63c3a66f 1069 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
04237ddd 1070 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 1071 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 1072}
1073
1da177e4
LT		 1074static void tg3_switch_clocks(struct tg3 *tp)
1075{
f6eb9b1f 1076 u32 clock_ctrl;
1da177e4
LT		 1077 u32 orig_clock_ctrl;
1078
63c3a66f 1079 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
4cf78e4f
MC		 1080 return;
1081
f6eb9b1f
MC		 1082 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1083
1da177e4
LT		 1084 orig_clock_ctrl = clock_ctrl;
1085 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1086 CLOCK_CTRL_CLKRUN_OENABLE |
1087 0x1f);
1088 tp->pci_clock_ctrl = clock_ctrl;
1089
63c3a66f 1090 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4 1091 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 1094 }
1095 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 1096 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1097 clock_ctrl |
1098 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1099 40);
1100 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1101 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1102 40);
1da177e4 1103 }
b401e9e2 1104 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 1105}
1106
1107#define PHY_BUSY_LOOPS 5000
1108
5c358045
HM		 1109static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1110 u32 *val)
1da177e4
LT		 1111{
1112 u32 frame_val;
1113 unsigned int loops;
1114 int ret;
1115
1116 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1117 tw32_f(MAC_MI_MODE,
1118 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1119 udelay(80);
1120 }
1121
8151ad57
MC		 1122 tg3_ape_lock(tp, tp->phy_ape_lock);
1123
1da177e4
LT		 1124 *val = 0x0;
1125
5c358045 1126 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 1131
1da177e4
LT		 1132 tw32_f(MAC_MI_COM, frame_val);
1133
1134 loops = PHY_BUSY_LOOPS;
1135 while (loops != 0) {
1136 udelay(10);
1137 frame_val = tr32(MAC_MI_COM);
1138
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1140 udelay(5);
1141 frame_val = tr32(MAC_MI_COM);
1142 break;
1143 }
1144 loops -= 1;
1145 }
1146
1147 ret = -EBUSY;
1148 if (loops != 0) {
1149 *val = frame_val & MI_COM_DATA_MASK;
1150 ret = 0;
1151 }
1152
1153 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1154 tw32_f(MAC_MI_MODE, tp->mi_mode);
1155 udelay(80);
1156 }
1157
8151ad57
MC		 1158 tg3_ape_unlock(tp, tp->phy_ape_lock);
1159
1da177e4
LT		 1160 return ret;
1161}
1162
5c358045
HM		 1163static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1164{
1165 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1166}
1167
1168static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1169 u32 val)
1da177e4
LT		 1170{
1171 u32 frame_val;
1172 unsigned int loops;
1173 int ret;
1174
f07e9af3 1175 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
221c5637 1176 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
b5d3772c
MC		 1177 return 0;
1178
1da177e4
LT		 1179 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1180 tw32_f(MAC_MI_MODE,
1181 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1182 udelay(80);
1183 }
1184
8151ad57
MC		 1185 tg3_ape_lock(tp, tp->phy_ape_lock);
1186
5c358045 1187 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1188 MI_COM_PHY_ADDR_MASK);
1189 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1190 MI_COM_REG_ADDR_MASK);
1191 frame_val |= (val & MI_COM_DATA_MASK);
1192 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 1193
1da177e4
LT		 1194 tw32_f(MAC_MI_COM, frame_val);
1195
1196 loops = PHY_BUSY_LOOPS;
1197 while (loops != 0) {
1198 udelay(10);
1199 frame_val = tr32(MAC_MI_COM);
1200 if ((frame_val & MI_COM_BUSY) == 0) {
1201 udelay(5);
1202 frame_val = tr32(MAC_MI_COM);
1203 break;
1204 }
1205 loops -= 1;
1206 }
1207
1208 ret = -EBUSY;
1209 if (loops != 0)
1210 ret = 0;
1211
1212 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1213 tw32_f(MAC_MI_MODE, tp->mi_mode);
1214 udelay(80);
1215 }
1216
8151ad57
MC		 1217 tg3_ape_unlock(tp, tp->phy_ape_lock);
1218
1da177e4
LT		 1219 return ret;
1220}
1221
5c358045
HM		 1222static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1223{
1224 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1225}
1226
b0988c15
MC		 1227static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1228{
1229 int err;
1230
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1232 if (err)
1233 goto done;
1234
1235 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1236 if (err)
1237 goto done;
1238
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1240 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1241 if (err)
1242 goto done;
1243
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1245
1246done:
1247 return err;
1248}
1249
1250static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1251{
1252 int err;
1253
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1255 if (err)
1256 goto done;
1257
1258 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1259 if (err)
1260 goto done;
1261
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1263 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1264 if (err)
1265 goto done;
1266
1267 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1268
1269done:
1270 return err;
1271}
1272
1273static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1274{
1275 int err;
1276
1277 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1278 if (!err)
1279 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1280
1281 return err;
1282}
1283
1284static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1285{
1286 int err;
1287
1288 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1289 if (!err)
1290 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1291
1292 return err;
1293}
1294
15ee95c3
MC		 1295static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1296{
1297 int err;
1298
1299 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1300 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1301 MII_TG3_AUXCTL_SHDWSEL_MISC);
1302 if (!err)
1303 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1304
1305 return err;
1306}
1307
b4bd2929
MC		 1308static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1309{
1310 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1311 set |= MII_TG3_AUXCTL_MISC_WREN;
1312
1313 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1314}
1315
daf3ec68
NNS		 1316static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1317{
1318 u32 val;
1319 int err;
1d36ba45 1320
daf3ec68 1321 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1d36ba45 1322
daf3ec68
NNS		 1323 if (err)
1324 return err;
daf3ec68 1325
7c10ee32 1326 if (enable)
daf3ec68
NNS		 1327 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1328 else
1329 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1330
1331 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1332 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1333
1334 return err;
1335}
1d36ba45 1336
3ab71071
NS		 1337static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1338{
1339 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1340 reg | val | MII_TG3_MISC_SHDW_WREN);
1341}
1342
95e2869a
MC		 1343static int tg3_bmcr_reset(struct tg3 *tp)
1344{
1345 u32 phy_control;
1346 int limit, err;
1347
1348 /* OK, reset it, and poll the BMCR_RESET bit until it
1349 * clears or we time out.
1350 */
1351 phy_control = BMCR_RESET;
1352 err = tg3_writephy(tp, MII_BMCR, phy_control);
1353 if (err != 0)
1354 return -EBUSY;
1355
1356 limit = 5000;
1357 while (limit--) {
1358 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1359 if (err != 0)
1360 return -EBUSY;
1361
1362 if ((phy_control & BMCR_RESET) == 0) {
1363 udelay(40);
1364 break;
1365 }
1366 udelay(10);
1367 }
d4675b52 1368 if (limit < 0)
95e2869a
MC		 1369 return -EBUSY;
1370
1371 return 0;
1372}
1373
158d7abd
MC		 1374static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1375{
3d16543d 1376 struct tg3 *tp = bp->priv;
158d7abd
MC		 1377 u32 val;
1378
24bb4fb6 1379 spin_lock_bh(&tp->lock);
158d7abd 1380
ead2402c 1381 if (__tg3_readphy(tp, mii_id, reg, &val))
24bb4fb6
MC		 1382 val = -EIO;
1383
1384 spin_unlock_bh(&tp->lock);
158d7abd
MC		 1385
1386 return val;
1387}
1388
1389static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1390{
3d16543d 1391 struct tg3 *tp = bp->priv;
24bb4fb6 1392 u32 ret = 0;
158d7abd 1393
24bb4fb6 1394 spin_lock_bh(&tp->lock);
158d7abd 1395
ead2402c 1396 if (__tg3_writephy(tp, mii_id, reg, val))
24bb4fb6 1397 ret = -EIO;
158d7abd 1398
24bb4fb6
MC		 1399 spin_unlock_bh(&tp->lock);
1400
1401 return ret;
158d7abd
MC		 1402}
1403
1404static int tg3_mdio_reset(struct mii_bus *bp)
1405{
1406 return 0;
1407}
1408
9c61d6bc 1409static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 1410{
1411 u32 val;
fcb389df 1412 struct phy_device *phydev;
a9daf367 1413
ead2402c 1414 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
fcb389df 1415 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 1416 case PHY_ID_BCM50610:
1417 case PHY_ID_BCM50610M:
fcb389df
MC		 1418 val = MAC_PHYCFG2_50610_LED_MODES;
1419 break;
6a443a0f 1420 case PHY_ID_BCMAC131:
fcb389df
MC		 1421 val = MAC_PHYCFG2_AC131_LED_MODES;
1422 break;
6a443a0f 1423 case PHY_ID_RTL8211C:
fcb389df
MC		 1424 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1425 break;
6a443a0f 1426 case PHY_ID_RTL8201E:
fcb389df
MC		 1427 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1428 break;
1429 default:
a9daf367 1430 return;
fcb389df
MC		 1431 }
1432
1433 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1434 tw32(MAC_PHYCFG2, val);
1435
1436 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 1437 val &= ~(MAC_PHYCFG1_RGMII_INT |
1438 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1439 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 1440 tw32(MAC_PHYCFG1, val);
1441
1442 return;
1443 }
1444
63c3a66f 1445 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
fcb389df
MC		 1446 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1447 MAC_PHYCFG2_FMODE_MASK_MASK |
1448 MAC_PHYCFG2_GMODE_MASK_MASK |
1449 MAC_PHYCFG2_ACT_MASK_MASK |
1450 MAC_PHYCFG2_QUAL_MASK_MASK |
1451 MAC_PHYCFG2_INBAND_ENABLE;
1452
1453 tw32(MAC_PHYCFG2, val);
a9daf367 1454
bb85fbb6
MC		 1455 val = tr32(MAC_PHYCFG1);
1456 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1457 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
63c3a66f
JP		 1458 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1459 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1460 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
63c3a66f 1461 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1462 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1463 }
bb85fbb6
MC		 1464 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1465 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1466 tw32(MAC_PHYCFG1, val);
a9daf367 1467
a9daf367
MC		 1468 val = tr32(MAC_EXT_RGMII_MODE);
1469 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1470 MAC_RGMII_MODE_RX_QUALITY |
1471 MAC_RGMII_MODE_RX_ACTIVITY |
1472 MAC_RGMII_MODE_RX_ENG_DET |
1473 MAC_RGMII_MODE_TX_ENABLE |
1474 MAC_RGMII_MODE_TX_LOWPWR |
1475 MAC_RGMII_MODE_TX_RESET);
63c3a66f
JP		 1476 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1477 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367
MC		 1478 val |= MAC_RGMII_MODE_RX_INT_B |
1479 MAC_RGMII_MODE_RX_QUALITY |
1480 MAC_RGMII_MODE_RX_ACTIVITY |
1481 MAC_RGMII_MODE_RX_ENG_DET;
63c3a66f 1482 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1483 val |= MAC_RGMII_MODE_TX_ENABLE |
1484 MAC_RGMII_MODE_TX_LOWPWR |
1485 MAC_RGMII_MODE_TX_RESET;
1486 }
1487 tw32(MAC_EXT_RGMII_MODE, val);
1488}
1489
158d7abd
MC		 1490static void tg3_mdio_start(struct tg3 *tp)
1491{
158d7abd
MC		 1492 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1493 tw32_f(MAC_MI_MODE, tp->mi_mode);
1494 udelay(80);
a9daf367 1495
63c3a66f 1496 if (tg3_flag(tp, MDIOBUS_INITED) &&
4153577a 1497 tg3_asic_rev(tp) == ASIC_REV_5785)
9ea4818d
MC		 1498 tg3_mdio_config_5785(tp);
1499}
1500
1501static int tg3_mdio_init(struct tg3 *tp)
1502{
1503 int i;
1504 u32 reg;
1505 struct phy_device *phydev;
1506
63c3a66f 1507 if (tg3_flag(tp, 5717_PLUS)) {
9c7df915 1508 u32 is_serdes;
882e9793 1509
69f11c99 1510 tp->phy_addr = tp->pci_fn + 1;
882e9793 1511
4153577a 1512 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
d1ec96af
MC		 1513 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1514 else
1515 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1516 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1517 if (is_serdes)
1518 tp->phy_addr += 7;
ee002b64
HM		 1519 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1520 int addr;
1521
1522 addr = ssb_gige_get_phyaddr(tp->pdev);
1523 if (addr < 0)
1524 return addr;
1525 tp->phy_addr = addr;
882e9793 1526 } else
3f0e3ad7 1527 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1528
158d7abd
MC		 1529 tg3_mdio_start(tp);
1530
63c3a66f 1531 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
158d7abd
MC		 1532 return 0;
1533
298cf9be
LB		 1534 tp->mdio_bus = mdiobus_alloc();
1535 if (tp->mdio_bus == NULL)
1536 return -ENOMEM;
158d7abd 1537
298cf9be
LB		 1538 tp->mdio_bus->name = "tg3 mdio bus";
1539 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1540 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1541 tp->mdio_bus->priv = tp;
1542 tp->mdio_bus->parent = &tp->pdev->dev;
1543 tp->mdio_bus->read = &tg3_mdio_read;
1544 tp->mdio_bus->write = &tg3_mdio_write;
1545 tp->mdio_bus->reset = &tg3_mdio_reset;
ead2402c 1546 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
298cf9be 1547 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1548
1549 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1550 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1551
1552 /* The bus registration will look for all the PHYs on the mdio bus.
1553 * Unfortunately, it does not ensure the PHY is powered up before
1554 * accessing the PHY ID registers. A chip reset is the
1555 * quickest way to bring the device back to an operational state..
1556 */
1557 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1558 tg3_bmcr_reset(tp);
1559
298cf9be 1560 i = mdiobus_register(tp->mdio_bus);
a9daf367 1561 if (i) {
ab96b241 1562 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1563 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1564 return i;
1565 }
158d7abd 1566
ead2402c 1567 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
a9daf367 1568
9c61d6bc 1569 if (!phydev || !phydev->drv) {
ab96b241 1570 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1571 mdiobus_unregister(tp->mdio_bus);
1572 mdiobus_free(tp->mdio_bus);
1573 return -ENODEV;
1574 }
1575
1576 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1577 case PHY_ID_BCM57780:
321d32a0 1578 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1579 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1580 break;
6a443a0f
MC		 1581 case PHY_ID_BCM50610:
1582 case PHY_ID_BCM50610M:
32e5a8d6 1583 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1584 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1585 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1586 PHY_BRCM_AUTO_PWRDWN_ENABLE;
63c3a66f 1587 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
a9daf367 1588 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
63c3a66f 1589 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1590 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
63c3a66f 1591 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367 1592 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1593 /* fallthru */
6a443a0f 1594 case PHY_ID_RTL8211C:
fcb389df 1595 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1596 break;
6a443a0f
MC		 1597 case PHY_ID_RTL8201E:
1598 case PHY_ID_BCMAC131:
a9daf367 1599 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1600 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
f07e9af3 1601 tp->phy_flags |= TG3_PHYFLG_IS_FET;
a9daf367
MC		 1602 break;
1603 }
1604
63c3a66f 1605 tg3_flag_set(tp, MDIOBUS_INITED);
9c61d6bc 1606
4153577a 1607 if (tg3_asic_rev(tp) == ASIC_REV_5785)
9c61d6bc 1608 tg3_mdio_config_5785(tp);
a9daf367
MC		 1609
1610 return 0;
158d7abd
MC		 1611}
1612
1613static void tg3_mdio_fini(struct tg3 *tp)
1614{
63c3a66f
JP		 1615 if (tg3_flag(tp, MDIOBUS_INITED)) {
1616 tg3_flag_clear(tp, MDIOBUS_INITED);
298cf9be
LB		 1617 mdiobus_unregister(tp->mdio_bus);
1618 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1619 }
1620}
1621
4ba526ce
MC		 1622/* tp->lock is held. */
1623static inline void tg3_generate_fw_event(struct tg3 *tp)
1624{
1625 u32 val;
1626
1627 val = tr32(GRC_RX_CPU_EVENT);
1628 val |= GRC_RX_CPU_DRIVER_EVENT;
1629 tw32_f(GRC_RX_CPU_EVENT, val);
1630
1631 tp->last_event_jiffies = jiffies;
1632}
1633
1634#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1635
95e2869a
MC		 1636/* tp->lock is held. */
1637static void tg3_wait_for_event_ack(struct tg3 *tp)
1638{
1639 int i;
4ba526ce
MC		 1640 unsigned int delay_cnt;
1641 long time_remain;
1642
1643 /* If enough time has passed, no wait is necessary. */
1644 time_remain = (long)(tp->last_event_jiffies + 1 +
1645 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1646 (long)jiffies;
1647 if (time_remain < 0)
1648 return;
1649
1650 /* Check if we can shorten the wait time. */
1651 delay_cnt = jiffies_to_usecs(time_remain);
1652 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1653 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1654 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1655
4ba526ce 1656 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1657 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1658 break;
6d446ec3
GS		 1659 if (pci_channel_offline(tp->pdev))
1660 break;
1661
4ba526ce 1662 udelay(8);
95e2869a
MC		 1663 }
1664}
1665
1666/* tp->lock is held. */
b28f389d 1667static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
95e2869a 1668{
b28f389d 1669 u32 reg, val;
95e2869a
MC		 1670
1671 val = 0;
1672 if (!tg3_readphy(tp, MII_BMCR, &reg))
1673 val = reg << 16;
1674 if (!tg3_readphy(tp, MII_BMSR, &reg))
1675 val |= (reg & 0xffff);
b28f389d 1676 *data++ = val;
95e2869a
MC		 1677
1678 val = 0;
1679 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1680 val = reg << 16;
1681 if (!tg3_readphy(tp, MII_LPA, &reg))
1682 val |= (reg & 0xffff);
b28f389d 1683 *data++ = val;
95e2869a
MC		 1684
1685 val = 0;
f07e9af3 1686 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
95e2869a
MC		 1687 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1688 val = reg << 16;
1689 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1690 val |= (reg & 0xffff);
1691 }
b28f389d 1692 *data++ = val;
95e2869a
MC		 1693
1694 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1695 val = reg << 16;
1696 else
1697 val = 0;
b28f389d
MC		 1698 *data++ = val;
1699}
1700
1701/* tp->lock is held. */
1702static void tg3_ump_link_report(struct tg3 *tp)
1703{
1704 u32 data[4];
1705
1706 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1707 return;
1708
1709 tg3_phy_gather_ump_data(tp, data);
1710
1711 tg3_wait_for_event_ack(tp);
1712
1713 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1714 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1715 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1716 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1717 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1718 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
95e2869a 1719
4ba526ce 1720 tg3_generate_fw_event(tp);
95e2869a
MC		 1721}
1722
8d5a89b3
MC		 1723/* tp->lock is held. */
1724static void tg3_stop_fw(struct tg3 *tp)
1725{
1726 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1727 /* Wait for RX cpu to ACK the previous event. */
1728 tg3_wait_for_event_ack(tp);
1729
1730 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1731
1732 tg3_generate_fw_event(tp);
1733
1734 /* Wait for RX cpu to ACK this event. */
1735 tg3_wait_for_event_ack(tp);
1736 }
1737}
1738
fd6d3f0e
MC		 1739/* tp->lock is held. */
1740static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1741{
1742 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1743 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1744
1745 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1746 switch (kind) {
1747 case RESET_KIND_INIT:
1748 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1749 DRV_STATE_START);
1750 break;
1751
1752 case RESET_KIND_SHUTDOWN:
1753 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1754 DRV_STATE_UNLOAD);
1755 break;
1756
1757 case RESET_KIND_SUSPEND:
1758 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1759 DRV_STATE_SUSPEND);
1760 break;
1761
1762 default:
1763 break;
1764 }
1765 }
fd6d3f0e
MC		 1766}
1767
1768/* tp->lock is held. */
1769static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1770{
1771 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1772 switch (kind) {
1773 case RESET_KIND_INIT:
1774 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1775 DRV_STATE_START_DONE);
1776 break;
1777
1778 case RESET_KIND_SHUTDOWN:
1779 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1780 DRV_STATE_UNLOAD_DONE);
1781 break;
1782
1783 default:
1784 break;
1785 }
1786 }
fd6d3f0e
MC		 1787}
1788
1789/* tp->lock is held. */
1790static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1791{
1792 if (tg3_flag(tp, ENABLE_ASF)) {
1793 switch (kind) {
1794 case RESET_KIND_INIT:
1795 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1796 DRV_STATE_START);
1797 break;
1798
1799 case RESET_KIND_SHUTDOWN:
1800 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1801 DRV_STATE_UNLOAD);
1802 break;
1803
1804 case RESET_KIND_SUSPEND:
1805 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1806 DRV_STATE_SUSPEND);
1807 break;
1808
1809 default:
1810 break;
1811 }
1812 }
1813}
1814
1815static int tg3_poll_fw(struct tg3 *tp)
1816{
1817 int i;
1818 u32 val;
1819
df465abf
NS		 1820 if (tg3_flag(tp, NO_FWARE_REPORTED))
1821 return 0;
1822
7e6c63f0
HM		 1823 if (tg3_flag(tp, IS_SSB_CORE)) {
1824 /* We don't use firmware. */
1825 return 0;
1826 }
1827
4153577a 1828 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
fd6d3f0e
MC		 1829 /* Wait up to 20ms for init done. */
1830 for (i = 0; i < 200; i++) {
1831 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1832 return 0;
6d446ec3
GS		 1833 if (pci_channel_offline(tp->pdev))
1834 return -ENODEV;
1835
fd6d3f0e
MC		 1836 udelay(100);
1837 }
1838 return -ENODEV;
1839 }
1840
1841 /* Wait for firmware initialization to complete. */
1842 for (i = 0; i < 100000; i++) {
1843 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1844 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1845 break;
6d446ec3
GS		 1846 if (pci_channel_offline(tp->pdev)) {
1847 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1848 tg3_flag_set(tp, NO_FWARE_REPORTED);
1849 netdev_info(tp->dev, "No firmware running\n");
1850 }
1851
1852 break;
1853 }
1854
fd6d3f0e
MC		 1855 udelay(10);
1856 }
1857
1858 /* Chip might not be fitted with firmware. Some Sun onboard
1859 * parts are configured like that. So don't signal the timeout
1860 * of the above loop as an error, but do report the lack of
1861 * running firmware once.
1862 */
1863 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1864 tg3_flag_set(tp, NO_FWARE_REPORTED);
1865
1866 netdev_info(tp->dev, "No firmware running\n");
1867 }
1868
4153577a 1869 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
fd6d3f0e
MC		 1870 /* The 57765 A0 needs a little more
1871 * time to do some important work.
1872 */
1873 mdelay(10);
1874 }
1875
1876 return 0;
1877}
1878
95e2869a
MC		 1879static void tg3_link_report(struct tg3 *tp)
1880{
1881 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1882 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1883 tg3_ump_link_report(tp);
1884 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1885 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1886 (tp->link_config.active_speed == SPEED_1000 ?
1887 1000 :
1888 (tp->link_config.active_speed == SPEED_100 ?
1889 100 : 10)),
1890 (tp->link_config.active_duplex == DUPLEX_FULL ?
1891 "full" : "half"));
1892
1893 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1894 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1895 "on" : "off",
1896 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1897 "on" : "off");
47007831
MC		 1898
1899 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1900 netdev_info(tp->dev, "EEE is %s\n",
1901 tp->setlpicnt ? "enabled" : "disabled");
1902
95e2869a
MC		 1903 tg3_ump_link_report(tp);
1904 }
84421b99
NS		 1905
1906 tp->link_up = netif_carrier_ok(tp->dev);
95e2869a
MC		 1907}
1908
fdad8de4
NS		 1909static u32 tg3_decode_flowctrl_1000T(u32 adv)
1910{
1911 u32 flowctrl = 0;
1912
1913 if (adv & ADVERTISE_PAUSE_CAP) {
1914 flowctrl |= FLOW_CTRL_RX;
1915 if (!(adv & ADVERTISE_PAUSE_ASYM))
1916 flowctrl |= FLOW_CTRL_TX;
1917 } else if (adv & ADVERTISE_PAUSE_ASYM)
1918 flowctrl |= FLOW_CTRL_TX;
1919
1920 return flowctrl;
1921}
1922
95e2869a
MC		 1923static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1924{
1925 u16 miireg;
1926
e18ce346 1927 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1928 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1929 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1930 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1931 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1932 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1933 else
1934 miireg = 0;
1935
1936 return miireg;
1937}
1938
fdad8de4
NS		 1939static u32 tg3_decode_flowctrl_1000X(u32 adv)
1940{
1941 u32 flowctrl = 0;
1942
1943 if (adv & ADVERTISE_1000XPAUSE) {
1944 flowctrl |= FLOW_CTRL_RX;
1945 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1946 flowctrl |= FLOW_CTRL_TX;
1947 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1948 flowctrl |= FLOW_CTRL_TX;
1949
1950 return flowctrl;
1951}
1952
95e2869a
MC		 1953static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1954{
1955 u8 cap = 0;
1956
f3791cdf
MC		 1957 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1958 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1959 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1960 if (lcladv & ADVERTISE_1000XPAUSE)
1961 cap = FLOW_CTRL_RX;
1962 if (rmtadv & ADVERTISE_1000XPAUSE)
e18ce346 1963 cap = FLOW_CTRL_TX;
95e2869a
MC		 1964 }
1965
1966 return cap;
1967}
1968
f51f3562 1969static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1970{
b02fd9e3 1971 u8 autoneg;
f51f3562 1972 u8 flowctrl = 0;
95e2869a
MC		 1973 u32 old_rx_mode = tp->rx_mode;
1974 u32 old_tx_mode = tp->tx_mode;
1975
63c3a66f 1976 if (tg3_flag(tp, USE_PHYLIB))
ead2402c 1977 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg;
b02fd9e3
MC		 1978 else
1979 autoneg = tp->link_config.autoneg;
1980
63c3a66f 1981 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
f07e9af3 1982 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
f51f3562 1983 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1984 else
bc02ff95 1985 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1986 } else
1987 flowctrl = tp->link_config.flowctrl;
95e2869a 1988
f51f3562 1989 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1990
e18ce346 1991 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1992 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1993 else
1994 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1995
f51f3562 1996 if (old_rx_mode != tp->rx_mode)
95e2869a 1997 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1998
e18ce346 1999 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 2000 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
2001 else
2002 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
2003
f51f3562 2004 if (old_tx_mode != tp->tx_mode)
95e2869a 2005 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 2006}
2007
b02fd9e3
MC		 2008static void tg3_adjust_link(struct net_device *dev)
2009{
2010 u8 oldflowctrl, linkmesg = 0;
2011 u32 mac_mode, lcl_adv, rmt_adv;
2012 struct tg3 *tp = netdev_priv(dev);
ead2402c 2013 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 2014
24bb4fb6 2015 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 2016
2017 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2018 MAC_MODE_HALF_DUPLEX);
2019
2020 oldflowctrl = tp->link_config.active_flowctrl;
2021
2022 if (phydev->link) {
2023 lcl_adv = 0;
2024 rmt_adv = 0;
2025
2026 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2027 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748 2028 else if (phydev->speed == SPEED_1000 ||
4153577a 2029 tg3_asic_rev(tp) != ASIC_REV_5785)
b02fd9e3 2030 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 2031 else
2032 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 2033
2034 if (phydev->duplex == DUPLEX_HALF)
2035 mac_mode |= MAC_MODE_HALF_DUPLEX;
2036 else {
f88788f0 2037 lcl_adv = mii_advertise_flowctrl(
b02fd9e3
MC		 2038 tp->link_config.flowctrl);
2039
2040 if (phydev->pause)
2041 rmt_adv = LPA_PAUSE_CAP;
2042 if (phydev->asym_pause)
2043 rmt_adv |= LPA_PAUSE_ASYM;
2044 }
2045
2046 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2047 } else
2048 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2049
2050 if (mac_mode != tp->mac_mode) {
2051 tp->mac_mode = mac_mode;
2052 tw32_f(MAC_MODE, tp->mac_mode);
2053 udelay(40);
2054 }
2055
4153577a 2056 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
fcb389df
MC		 2057 if (phydev->speed == SPEED_10)
2058 tw32(MAC_MI_STAT,
2059 MAC_MI_STAT_10MBPS_MODE |
2060 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2061 else
2062 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2063 }
2064
b02fd9e3
MC		 2065 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2066 tw32(MAC_TX_LENGTHS,
2067 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2068 (6 << TX_LENGTHS_IPG_SHIFT) |
2069 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2070 else
2071 tw32(MAC_TX_LENGTHS,
2072 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2073 (6 << TX_LENGTHS_IPG_SHIFT) |
2074 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2075
34655ad6 2076 if (phydev->link != tp->old_link ||
b02fd9e3
MC		 2077 phydev->speed != tp->link_config.active_speed ||
2078 phydev->duplex != tp->link_config.active_duplex ||
2079 oldflowctrl != tp->link_config.active_flowctrl)
c6cdf436 2080 linkmesg = 1;
b02fd9e3 2081
34655ad6 2082 tp->old_link = phydev->link;
b02fd9e3
MC		 2083 tp->link_config.active_speed = phydev->speed;
2084 tp->link_config.active_duplex = phydev->duplex;
2085
24bb4fb6 2086 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 2087
2088 if (linkmesg)
2089 tg3_link_report(tp);
2090}
2091
2092static int tg3_phy_init(struct tg3 *tp)
2093{
2094 struct phy_device *phydev;
2095
f07e9af3 2096 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
b02fd9e3
MC		 2097 return 0;
2098
2099 /* Bring the PHY back to a known state. */
2100 tg3_bmcr_reset(tp);
2101
ead2402c 2102 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3
MC		 2103
2104 /* Attach the MAC to the PHY. */
f9a8f83b
FF		 2105 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2106 tg3_adjust_link, phydev->interface);
b02fd9e3 2107 if (IS_ERR(phydev)) {
ab96b241 2108 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 2109 return PTR_ERR(phydev);
2110 }
2111
b02fd9e3 2112 /* Mask with MAC supported features. */
9c61d6bc
MC		 2113 switch (phydev->interface) {
2114 case PHY_INTERFACE_MODE_GMII:
2115 case PHY_INTERFACE_MODE_RGMII:
f07e9af3 2116 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
321d32a0
MC		 2117 phydev->supported &= (PHY_GBIT_FEATURES |
2118 SUPPORTED_Pause |
2119 SUPPORTED_Asym_Pause);
2120 break;
2121 }
2122 /* fallthru */
9c61d6bc
MC		 2123 case PHY_INTERFACE_MODE_MII:
2124 phydev->supported &= (PHY_BASIC_FEATURES |
2125 SUPPORTED_Pause |
2126 SUPPORTED_Asym_Pause);
2127 break;
2128 default:
ead2402c 2129 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
9c61d6bc
MC		 2130 return -EINVAL;
2131 }
2132
f07e9af3 2133 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2134
2135 phydev->advertising = phydev->supported;
2136
b02fd9e3
MC		 2137 return 0;
2138}
2139
2140static void tg3_phy_start(struct tg3 *tp)
2141{
2142 struct phy_device *phydev;
2143
f07e9af3 2144 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2145 return;
2146
ead2402c 2147 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 2148
80096068
MC		 2149 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2150 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
c6700ce2
MC		 2151 phydev->speed = tp->link_config.speed;
2152 phydev->duplex = tp->link_config.duplex;
2153 phydev->autoneg = tp->link_config.autoneg;
2154 phydev->advertising = tp->link_config.advertising;
b02fd9e3
MC		 2155 }
2156
2157 phy_start(phydev);
2158
2159 phy_start_aneg(phydev);
2160}
2161
2162static void tg3_phy_stop(struct tg3 *tp)
2163{
f07e9af3 2164 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2165 return;
2166
ead2402c 2167 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]);
b02fd9e3
MC		 2168}
2169
2170static void tg3_phy_fini(struct tg3 *tp)
2171{
f07e9af3 2172 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
ead2402c 2173 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
f07e9af3 2174 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2175 }
2176}
2177
941ec90f
MC		 2178static int tg3_phy_set_extloopbk(struct tg3 *tp)
2179{
2180 int err;
2181 u32 val;
2182
2183 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2184 return 0;
2185
2186 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2187 /* Cannot do read-modify-write on 5401 */
2188 err = tg3_phy_auxctl_write(tp,
2189 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2190 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2191 0x4c20);
2192 goto done;
2193 }
2194
2195 err = tg3_phy_auxctl_read(tp,
2196 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2197 if (err)
2198 return err;
2199
2200 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2201 err = tg3_phy_auxctl_write(tp,
2202 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2203
2204done:
2205 return err;
2206}
2207
7f97a4bd
MC		 2208static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2209{
2210 u32 phytest;
2211
2212 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2213 u32 phy;
2214
2215 tg3_writephy(tp, MII_TG3_FET_TEST,
2216 phytest | MII_TG3_FET_SHADOW_EN);
2217 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2218 if (enable)
2219 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2220 else
2221 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2222 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2223 }
2224 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2225 }
2226}
2227
6833c043
MC		 2228static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2229{
2230 u32 reg;
2231
63c3a66f
JP		 2232 if (!tg3_flag(tp, 5705_PLUS) ||
2233 (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2234 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
6833c043
MC		 2235 return;
2236
f07e9af3 2237 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7f97a4bd
MC		 2238 tg3_phy_fet_toggle_apd(tp, enable);
2239 return;
2240 }
2241
3ab71071 2242 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
6833c043
MC		 2243 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2244 MII_TG3_MISC_SHDW_SCR5_SDTL |
2245 MII_TG3_MISC_SHDW_SCR5_C125OE;
4153577a 2246 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
6833c043
MC		 2247 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2248
3ab71071 2249 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
6833c043
MC		 2250
2251
3ab71071 2252 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
6833c043
MC		 2253 if (enable)
2254 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2255
3ab71071 2256 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
6833c043
MC		 2257}
2258
953c96e0 2259static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
9ef8ca99
MC		 2260{
2261 u32 phy;
2262
63c3a66f 2263 if (!tg3_flag(tp, 5705_PLUS) ||
f07e9af3 2264 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9ef8ca99
MC		 2265 return;
2266
f07e9af3 2267 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
9ef8ca99
MC		 2268 u32 ephy;
2269
535ef6e1
MC		 2270 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2271 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2272
2273 tg3_writephy(tp, MII_TG3_FET_TEST,
2274 ephy | MII_TG3_FET_SHADOW_EN);
2275 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 2276 if (enable)
535ef6e1 2277 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 2278 else
535ef6e1
MC		 2279 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2280 tg3_writephy(tp, reg, phy);
9ef8ca99 2281 }
535ef6e1 2282 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 2283 }
2284 } else {
15ee95c3
MC		 2285 int ret;
2286
2287 ret = tg3_phy_auxctl_read(tp,
2288 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2289 if (!ret) {
9ef8ca99
MC		 2290 if (enable)
2291 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2292 else
2293 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
b4bd2929
MC		 2294 tg3_phy_auxctl_write(tp,
2295 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
9ef8ca99
MC		 2296 }
2297 }
2298}
2299
1da177e4
LT		 2300static void tg3_phy_set_wirespeed(struct tg3 *tp)
2301{
15ee95c3 2302 int ret;
1da177e4
LT		 2303 u32 val;
2304
f07e9af3 2305 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1da177e4
LT		 2306 return;
2307
15ee95c3
MC		 2308 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2309 if (!ret)
b4bd2929
MC		 2310 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2311 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1da177e4
LT		 2312}
2313
b2a5c19c
MC		 2314static void tg3_phy_apply_otp(struct tg3 *tp)
2315{
2316 u32 otp, phy;
2317
2318 if (!tp->phy_otp)
2319 return;
2320
2321 otp = tp->phy_otp;
2322
daf3ec68 2323 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
1d36ba45 2324 return;
b2a5c19c
MC		 2325
2326 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2327 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2328 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2329
2330 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2331 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2332 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2333
2334 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2335 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2336 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2337
2338 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2339 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2340
2341 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2342 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2343
2344 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2345 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2346 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2347
daf3ec68 2348 tg3_phy_toggle_auxctl_smdsp(tp, false);
b2a5c19c
MC		 2349}
2350
400dfbaa
NS		 2351static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2352{
2353 u32 val;
2354 struct ethtool_eee *dest = &tp->eee;
2355
2356 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2357 return;
2358
2359 if (eee)
2360 dest = eee;
2361
2362 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2363 return;
2364
2365 /* Pull eee_active */
2366 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2367 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2368 dest->eee_active = 1;
2369 } else
2370 dest->eee_active = 0;
2371
2372 /* Pull lp advertised settings */
2373 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2374 return;
2375 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2376
2377 /* Pull advertised and eee_enabled settings */
2378 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2379 return;
2380 dest->eee_enabled = !!val;
2381 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2382
2383 /* Pull tx_lpi_enabled */
2384 val = tr32(TG3_CPMU_EEE_MODE);
2385 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2386
2387 /* Pull lpi timer value */
2388 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2389}
2390
953c96e0 2391static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
52b02d04
MC		 2392{
2393 u32 val;
2394
2395 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2396 return;
2397
2398 tp->setlpicnt = 0;
2399
2400 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
953c96e0 2401 current_link_up &&
a6b68dab
MC		 2402 tp->link_config.active_duplex == DUPLEX_FULL &&
2403 (tp->link_config.active_speed == SPEED_100 ||
2404 tp->link_config.active_speed == SPEED_1000)) {
52b02d04
MC		 2405 u32 eeectl;
2406
2407 if (tp->link_config.active_speed == SPEED_1000)
2408 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2409 else
2410 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2411
2412 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2413
400dfbaa
NS		 2414 tg3_eee_pull_config(tp, NULL);
2415 if (tp->eee.eee_active)
52b02d04
MC		 2416 tp->setlpicnt = 2;
2417 }
2418
2419 if (!tp->setlpicnt) {
953c96e0 2420 if (current_link_up &&
daf3ec68 2421 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94 2422 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
daf3ec68 2423 tg3_phy_toggle_auxctl_smdsp(tp, false);
b715ce94
MC		 2424 }
2425
52b02d04
MC		 2426 val = tr32(TG3_CPMU_EEE_MODE);
2427 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2428 }
2429}
2430
b0c5943f
MC		 2431static void tg3_phy_eee_enable(struct tg3 *tp)
2432{
2433 u32 val;
2434
2435 if (tp->link_config.active_speed == SPEED_1000 &&
4153577a
JP		 2436 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2437 tg3_asic_rev(tp) == ASIC_REV_5719 ||
55086ad9 2438 tg3_flag(tp, 57765_CLASS)) &&
daf3ec68 2439 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94
MC		 2440 val = MII_TG3_DSP_TAP26_ALNOKO |
2441 MII_TG3_DSP_TAP26_RMRXSTO;
2442 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
daf3ec68 2443 tg3_phy_toggle_auxctl_smdsp(tp, false);
b0c5943f
MC		 2444 }
2445
2446 val = tr32(TG3_CPMU_EEE_MODE);
2447 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2448}
2449
1da177e4
LT		 2450static int tg3_wait_macro_done(struct tg3 *tp)
2451{
2452 int limit = 100;
2453
2454 while (limit--) {
2455 u32 tmp32;
2456
f08aa1a8 2457 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1da177e4
LT		 2458 if ((tmp32 & 0x1000) == 0)
2459 break;
2460 }
2461 }
d4675b52 2462 if (limit < 0)
1da177e4
LT		 2463 return -EBUSY;
2464
2465 return 0;
2466}
2467
2468static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2469{
2470 static const u32 test_pat[4][6] = {
2471 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2472 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2473 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2474 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2475 };
2476 int chan;
2477
2478 for (chan = 0; chan < 4; chan++) {
2479 int i;
2480
2481 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2482 (chan * 0x2000) | 0x0200);
f08aa1a8 2483 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2484
2485 for (i = 0; i < 6; i++)
2486 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2487 test_pat[chan][i]);
2488
f08aa1a8 2489 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2490 if (tg3_wait_macro_done(tp)) {
2491 *resetp = 1;
2492 return -EBUSY;
2493 }
2494
2495 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2496 (chan * 0x2000) | 0x0200);
f08aa1a8 2497 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1da177e4
LT		 2498 if (tg3_wait_macro_done(tp)) {
2499 *resetp = 1;
2500 return -EBUSY;
2501 }
2502
f08aa1a8 2503 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1da177e4
LT		 2504 if (tg3_wait_macro_done(tp)) {
2505 *resetp = 1;
2506 return -EBUSY;
2507 }
2508
2509 for (i = 0; i < 6; i += 2) {
2510 u32 low, high;
2511
2512 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2513 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2514 tg3_wait_macro_done(tp)) {
2515 *resetp = 1;
2516 return -EBUSY;
2517 }
2518 low &= 0x7fff;
2519 high &= 0x000f;
2520 if (low != test_pat[chan][i] ||
2521 high != test_pat[chan][i+1]) {
2522 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2523 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2524 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2525
2526 return -EBUSY;
2527 }
2528 }
2529 }
2530
2531 return 0;
2532}
2533
2534static int tg3_phy_reset_chanpat(struct tg3 *tp)
2535{
2536 int chan;
2537
2538 for (chan = 0; chan < 4; chan++) {
2539 int i;
2540
2541 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2542 (chan * 0x2000) | 0x0200);
f08aa1a8 2543 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2544 for (i = 0; i < 6; i++)
2545 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
f08aa1a8 2546 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2547 if (tg3_wait_macro_done(tp))
2548 return -EBUSY;
2549 }
2550
2551 return 0;
2552}
2553
2554static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2555{
2556 u32 reg32, phy9_orig;
2557 int retries, do_phy_reset, err;
2558
2559 retries = 10;
2560 do_phy_reset = 1;
2561 do {
2562 if (do_phy_reset) {
2563 err = tg3_bmcr_reset(tp);
2564 if (err)
2565 return err;
2566 do_phy_reset = 0;
2567 }
2568
2569 /* Disable transmitter and interrupt. */
2570 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2571 continue;
2572
2573 reg32 |= 0x3000;
2574 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2575
2576 /* Set full-duplex, 1000 mbps. */
2577 tg3_writephy(tp, MII_BMCR,
221c5637 2578 BMCR_FULLDPLX | BMCR_SPEED1000);
1da177e4
LT		 2579
2580 /* Set to master mode. */
221c5637 2581 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
1da177e4
LT		 2582 continue;
2583
221c5637
MC		 2584 tg3_writephy(tp, MII_CTRL1000,
2585 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
1da177e4 2586
daf3ec68 2587 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
1d36ba45
MC		 2588 if (err)
2589 return err;
1da177e4
LT		 2590
2591 /* Block the PHY control access. */
6ee7c0a0 2592 tg3_phydsp_write(tp, 0x8005, 0x0800);
1da177e4
LT		 2593
2594 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2595 if (!err)
2596 break;
2597 } while (--retries);
2598
2599 err = tg3_phy_reset_chanpat(tp);
2600 if (err)
2601 return err;
2602
6ee7c0a0 2603 tg3_phydsp_write(tp, 0x8005, 0x0000);
1da177e4
LT		 2604
2605 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
f08aa1a8 2606 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1da177e4 2607
daf3ec68 2608 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2609
221c5637 2610 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
1da177e4 2611
c6e27f2f
DC		 2612 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
2613 if (err)
2614 return err;
1da177e4 2615
c6e27f2f
DC		 2616 reg32 &= ~0x3000;
2617 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2618
2619 return 0;
1da177e4
LT		 2620}
2621
f4a46d1f
NNS		 2622static void tg3_carrier_off(struct tg3 *tp)
2623{
2624 netif_carrier_off(tp->dev);
2625 tp->link_up = false;
2626}
2627
ce20f161
NS		 2628static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2629{
2630 if (tg3_flag(tp, ENABLE_ASF))
2631 netdev_warn(tp->dev,
2632 "Management side-band traffic will be interrupted during phy settings change\n");
2633}
2634
1da177e4
LT		 2635/* This will reset the tigon3 PHY if there is no valid
2636 * link unless the FORCE argument is non-zero.
2637 */
2638static int tg3_phy_reset(struct tg3 *tp)
2639{
f833c4c1 2640 u32 val, cpmuctrl;
1da177e4
LT		 2641 int err;
2642
4153577a 2643 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 2644 val = tr32(GRC_MISC_CFG);
2645 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2646 udelay(40);
2647 }
f833c4c1
MC		 2648 err = tg3_readphy(tp, MII_BMSR, &val);
2649 err |= tg3_readphy(tp, MII_BMSR, &val);
1da177e4
LT		 2650 if (err != 0)
2651 return -EBUSY;
2652
f4a46d1f 2653 if (netif_running(tp->dev) && tp->link_up) {
84421b99 2654 netif_carrier_off(tp->dev);
c8e1e82b
MC		 2655 tg3_link_report(tp);
2656 }
2657
4153577a
JP		 2658 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2659 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2660 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 2661 err = tg3_phy_reset_5703_4_5(tp);
2662 if (err)
2663 return err;
2664 goto out;
2665 }
2666
b2a5c19c 2667 cpmuctrl = 0;
4153577a
JP		 2668 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2669 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 2670 cpmuctrl = tr32(TG3_CPMU_CTRL);
2671 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2672 tw32(TG3_CPMU_CTRL,
2673 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2674 }
2675
1da177e4
LT		 2676 err = tg3_bmcr_reset(tp);
2677 if (err)
2678 return err;
2679
b2a5c19c 2680 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
f833c4c1
MC		 2681 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2682 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
b2a5c19c
MC		 2683
2684 tw32(TG3_CPMU_CTRL, cpmuctrl);
2685 }
2686
4153577a
JP		 2687 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2688 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 2689 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2690 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2691 CPMU_LSPD_1000MB_MACCLK_12_5) {
2692 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2693 udelay(40);
2694 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2695 }
2696 }
2697
63c3a66f 2698 if (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2699 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
ecf1410b
MC		 2700 return 0;
2701
b2a5c19c
MC		 2702 tg3_phy_apply_otp(tp);
2703
f07e9af3 2704 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
6833c043
MC		 2705 tg3_phy_toggle_apd(tp, true);
2706 else
2707 tg3_phy_toggle_apd(tp, false);
2708
1da177e4 2709out:
1d36ba45 2710 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
daf3ec68 2711 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
6ee7c0a0
MC		 2712 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2713 tg3_phydsp_write(tp, 0x000a, 0x0323);
daf3ec68 2714 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2715 }
1d36ba45 2716
f07e9af3 2717 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
f08aa1a8
MC		 2718 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2719 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1da177e4 2720 }
1d36ba45 2721
f07e9af3 2722 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
daf3ec68 2723 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2724 tg3_phydsp_write(tp, 0x000a, 0x310b);
2725 tg3_phydsp_write(tp, 0x201f, 0x9506);
2726 tg3_phydsp_write(tp, 0x401f, 0x14e2);
daf3ec68 2727 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2728 }
f07e9af3 2729 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
daf3ec68 2730 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2731 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2732 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2733 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2734 tg3_writephy(tp, MII_TG3_TEST1,
2735 MII_TG3_TEST1_TRIM_EN | 0x4);
2736 } else
2737 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2738
daf3ec68 2739 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2740 }
c424cb24 2741 }
1d36ba45 2742
1da177e4
LT		 2743 /* Set Extended packet length bit (bit 14) on all chips that */
2744 /* support jumbo frames */
79eb6904 2745 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4 2746 /* Cannot do read-modify-write on 5401 */
b4bd2929 2747 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
63c3a66f 2748 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
1da177e4 2749 /* Set bit 14 with read-modify-write to preserve other bits */
15ee95c3
MC		 2750 err = tg3_phy_auxctl_read(tp,
2751 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2752 if (!err)
b4bd2929
MC		 2753 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2754 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
1da177e4
LT		 2755 }
2756
2757 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2758 * jumbo frames transmission.
2759 */
63c3a66f 2760 if (tg3_flag(tp, JUMBO_CAPABLE)) {
f833c4c1 2761 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
c6cdf436 2762 tg3_writephy(tp, MII_TG3_EXT_CTRL,
f833c4c1 2763 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1da177e4
LT		 2764 }
2765
4153577a 2766 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
715116a1 2767 /* adjust output voltage */
535ef6e1 2768 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2769 }
2770
4153577a 2771 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
c65a17f4
MC		 2772 tg3_phydsp_write(tp, 0xffb, 0x4000);
2773
953c96e0 2774 tg3_phy_toggle_automdix(tp, true);
1da177e4
LT		 2775 tg3_phy_set_wirespeed(tp);
2776 return 0;
2777}
2778
3a1e19d3
MC		 2779#define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2780#define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2781#define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2782 TG3_GPIO_MSG_NEED_VAUX)
2783#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2784 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2785 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2786 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2787 (TG3_GPIO_MSG_DRVR_PRES << 12))
2788
2789#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2790 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2791 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2792 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2793 (TG3_GPIO_MSG_NEED_VAUX << 12))
2794
2795static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2796{
2797 u32 status, shift;
2798
4153577a
JP		 2799 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2800 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2801 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2802 else
2803 status = tr32(TG3_CPMU_DRV_STATUS);
2804
2805 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2806 status &= ~(TG3_GPIO_MSG_MASK << shift);
2807 status |= (newstat << shift);
2808
4153577a
JP		 2809 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2810 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2811 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2812 else
2813 tw32(TG3_CPMU_DRV_STATUS, status);
2814
2815 return status >> TG3_APE_GPIO_MSG_SHIFT;
2816}
2817
520b2756
MC		 2818static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2819{
2820 if (!tg3_flag(tp, IS_NIC))
2821 return 0;
2822
4153577a
JP		 2823 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2824 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2825 tg3_asic_rev(tp) == ASIC_REV_5720) {
3a1e19d3
MC		 2826 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2827 return -EIO;
520b2756 2828
3a1e19d3
MC		 2829 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2830
2831 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2832 TG3_GRC_LCLCTL_PWRSW_DELAY);
2833
2834 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2835 } else {
2836 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2837 TG3_GRC_LCLCTL_PWRSW_DELAY);
2838 }
6f5c8f83 2839
520b2756
MC		 2840 return 0;
2841}
2842
2843static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2844{
2845 u32 grc_local_ctrl;
2846
2847 if (!tg3_flag(tp, IS_NIC) ||
4153577a
JP		 2848 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2849 tg3_asic_rev(tp) == ASIC_REV_5701)
520b2756
MC		 2850 return;
2851
2852 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2853
2854 tw32_wait_f(GRC_LOCAL_CTRL,
2855 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2856 TG3_GRC_LCLCTL_PWRSW_DELAY);
2857
2858 tw32_wait_f(GRC_LOCAL_CTRL,
2859 grc_local_ctrl,
2860 TG3_GRC_LCLCTL_PWRSW_DELAY);
2861
2862 tw32_wait_f(GRC_LOCAL_CTRL,
2863 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2864 TG3_GRC_LCLCTL_PWRSW_DELAY);
2865}
2866
2867static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2868{
2869 if (!tg3_flag(tp, IS_NIC))
2870 return;
2871
4153577a
JP		 2872 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2873 tg3_asic_rev(tp) == ASIC_REV_5701) {
520b2756
MC		 2874 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2875 (GRC_LCLCTRL_GPIO_OE0 |
2876 GRC_LCLCTRL_GPIO_OE1 |
2877 GRC_LCLCTRL_GPIO_OE2 |
2878 GRC_LCLCTRL_GPIO_OUTPUT0 |
2879 GRC_LCLCTRL_GPIO_OUTPUT1),
2880 TG3_GRC_LCLCTL_PWRSW_DELAY);
2881 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2882 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2883 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2884 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2885 GRC_LCLCTRL_GPIO_OE1 |
2886 GRC_LCLCTRL_GPIO_OE2 |
2887 GRC_LCLCTRL_GPIO_OUTPUT0 |
2888 GRC_LCLCTRL_GPIO_OUTPUT1 |
2889 tp->grc_local_ctrl;
2890 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2891 TG3_GRC_LCLCTL_PWRSW_DELAY);
2892
2893 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2894 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2895 TG3_GRC_LCLCTL_PWRSW_DELAY);
2896
2897 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2898 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2899 TG3_GRC_LCLCTL_PWRSW_DELAY);
2900 } else {
2901 u32 no_gpio2;
2902 u32 grc_local_ctrl = 0;
2903
2904 /* Workaround to prevent overdrawing Amps. */
4153577a 2905 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
520b2756
MC		 2906 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2907 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2908 grc_local_ctrl,
2909 TG3_GRC_LCLCTL_PWRSW_DELAY);
2910 }
2911
2912 /* On 5753 and variants, GPIO2 cannot be used. */
2913 no_gpio2 = tp->nic_sram_data_cfg &
2914 NIC_SRAM_DATA_CFG_NO_GPIO2;
2915
2916 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2917 GRC_LCLCTRL_GPIO_OE1 |
2918 GRC_LCLCTRL_GPIO_OE2 |
2919 GRC_LCLCTRL_GPIO_OUTPUT1 |
2920 GRC_LCLCTRL_GPIO_OUTPUT2;
2921 if (no_gpio2) {
2922 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2923 GRC_LCLCTRL_GPIO_OUTPUT2);
2924 }
2925 tw32_wait_f(GRC_LOCAL_CTRL,
2926 tp->grc_local_ctrl | grc_local_ctrl,
2927 TG3_GRC_LCLCTL_PWRSW_DELAY);
2928
2929 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2930
2931 tw32_wait_f(GRC_LOCAL_CTRL,
2932 tp->grc_local_ctrl | grc_local_ctrl,
2933 TG3_GRC_LCLCTL_PWRSW_DELAY);
2934
2935 if (!no_gpio2) {
2936 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2937 tw32_wait_f(GRC_LOCAL_CTRL,
2938 tp->grc_local_ctrl | grc_local_ctrl,
2939 TG3_GRC_LCLCTL_PWRSW_DELAY);
2940 }
2941 }
3a1e19d3
MC		 2942}
2943
cd0d7228 2944static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
3a1e19d3
MC		 2945{
2946 u32 msg = 0;
2947
2948 /* Serialize power state transitions */
2949 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2950 return;
2951
cd0d7228 2952 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
3a1e19d3
MC		 2953 msg = TG3_GPIO_MSG_NEED_VAUX;
2954
2955 msg = tg3_set_function_status(tp, msg);
2956
2957 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2958 goto done;
6f5c8f83 2959
3a1e19d3
MC		 2960 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2961 tg3_pwrsrc_switch_to_vaux(tp);
2962 else
2963 tg3_pwrsrc_die_with_vmain(tp);
2964
2965done:
6f5c8f83 2966 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
520b2756
MC		 2967}
2968
cd0d7228 2969static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
1da177e4 2970{
683644b7 2971 bool need_vaux = false;
1da177e4 2972
334355aa 2973 /* The GPIOs do something completely different on 57765. */
55086ad9 2974 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
1da177e4
LT		 2975 return;
2976
4153577a
JP		 2977 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2978 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2979 tg3_asic_rev(tp) == ASIC_REV_5720) {
cd0d7228
MC		 2980 tg3_frob_aux_power_5717(tp, include_wol ?
2981 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
3a1e19d3
MC		 2982 return;
2983 }
2984
2985 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
8c2dc7e1
MC		 2986 struct net_device *dev_peer;
2987
2988 dev_peer = pci_get_drvdata(tp->pdev_peer);
683644b7 2989
bc1c7567 2990 /* remove_one() may have been run on the peer. */
683644b7
MC		 2991 if (dev_peer) {
2992 struct tg3 *tp_peer = netdev_priv(dev_peer);
2993
63c3a66f 2994 if (tg3_flag(tp_peer, INIT_COMPLETE))
683644b7
MC		 2995 return;
2996
cd0d7228 2997 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
63c3a66f 2998 tg3_flag(tp_peer, ENABLE_ASF))
683644b7
MC		 2999 need_vaux = true;
3000 }
1da177e4
LT		 3001 }
3002
cd0d7228
MC		 3003 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
3004 tg3_flag(tp, ENABLE_ASF))
683644b7
MC		 3005 need_vaux = true;
3006
520b2756
MC		 3007 if (need_vaux)
3008 tg3_pwrsrc_switch_to_vaux(tp);
3009 else
3010 tg3_pwrsrc_die_with_vmain(tp);
1da177e4
LT		 3011}
3012
e8f3f6ca
MC		 3013static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3014{
3015 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3016 return 1;
79eb6904 3017 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 3018 if (speed != SPEED_10)
3019 return 1;
3020 } else if (speed == SPEED_10)
3021 return 1;
3022
3023 return 0;
3024}
3025
44f3b503
NS		 3026static bool tg3_phy_power_bug(struct tg3 *tp)
3027{
3028 switch (tg3_asic_rev(tp)) {
3029 case ASIC_REV_5700:
3030 case ASIC_REV_5704:
3031 return true;
3032 case ASIC_REV_5780:
3033 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3034 return true;
3035 return false;
3036 case ASIC_REV_5717:
3037 if (!tp->pci_fn)
3038 return true;
3039 return false;
3040 case ASIC_REV_5719:
3041 case ASIC_REV_5720:
3042 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3043 !tp->pci_fn)
3044 return true;
3045 return false;
3046 }
3047
3048 return false;
3049}
3050
989038e2
NS		 3051static bool tg3_phy_led_bug(struct tg3 *tp)
3052{
3053 switch (tg3_asic_rev(tp)) {
3054 case ASIC_REV_5719:
300cf9b9 3055 case ASIC_REV_5720:
989038e2
NS		 3056 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3057 !tp->pci_fn)
3058 return true;
3059 return false;
3060 }
3061
3062 return false;
3063}
3064
0a459aac 3065static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 3066{
ce057f01
MC		 3067 u32 val;
3068
942d1af0
NS		 3069 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3070 return;
3071
f07e9af3 3072 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a 3073 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
5129724a
MC		 3074 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3075 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3076
3077 sg_dig_ctrl |=
3078 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3079 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3080 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3081 }
3f7045c1 3082 return;
5129724a 3083 }
3f7045c1 3084
4153577a 3085 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 3086 tg3_bmcr_reset(tp);
3087 val = tr32(GRC_MISC_CFG);
3088 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3089 udelay(40);
3090 return;
f07e9af3 3091 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
0e5f784c
MC		 3092 u32 phytest;
3093 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3094 u32 phy;
3095
3096 tg3_writephy(tp, MII_ADVERTISE, 0);
3097 tg3_writephy(tp, MII_BMCR,
3098 BMCR_ANENABLE | BMCR_ANRESTART);
3099
3100 tg3_writephy(tp, MII_TG3_FET_TEST,
3101 phytest | MII_TG3_FET_SHADOW_EN);
3102 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3103 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3104 tg3_writephy(tp,
3105 MII_TG3_FET_SHDW_AUXMODE4,
3106 phy);
3107 }
3108 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3109 }
3110 return;
0a459aac 3111 } else if (do_low_power) {
989038e2
NS		 3112 if (!tg3_phy_led_bug(tp))
3113 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3114 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac 3115
b4bd2929
MC		 3116 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3117 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3118 MII_TG3_AUXCTL_PCTL_VREG_11V;
3119 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
715116a1 3120 }
3f7045c1 3121
15c3b696
MC		 3122 /* The PHY should not be powered down on some chips because
3123 * of bugs.
3124 */
44f3b503 3125 if (tg3_phy_power_bug(tp))
15c3b696 3126 return;
ce057f01 3127
4153577a
JP		 3128 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3129 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 3130 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3131 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3132 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3133 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3134 }
3135
15c3b696
MC		 3136 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3137}
3138
ffbcfed4
MC		 3139/* tp->lock is held. */
3140static int tg3_nvram_lock(struct tg3 *tp)
3141{
63c3a66f 3142 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3143 int i;
3144
3145 if (tp->nvram_lock_cnt == 0) {
3146 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3147 for (i = 0; i < 8000; i++) {
3148 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3149 break;
3150 udelay(20);
3151 }
3152 if (i == 8000) {
3153 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3154 return -ENODEV;
3155 }
3156 }
3157 tp->nvram_lock_cnt++;
3158 }
3159 return 0;
3160}
3161
3162/* tp->lock is held. */
3163static void tg3_nvram_unlock(struct tg3 *tp)
3164{
63c3a66f 3165 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3166 if (tp->nvram_lock_cnt > 0)
3167 tp->nvram_lock_cnt--;
3168 if (tp->nvram_lock_cnt == 0)
3169 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3170 }
3171}
3172
3173/* tp->lock is held. */
3174static void tg3_enable_nvram_access(struct tg3 *tp)
3175{
63c3a66f 3176 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3177 u32 nvaccess = tr32(NVRAM_ACCESS);
3178
3179 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3180 }
3181}
3182
3183/* tp->lock is held. */
3184static void tg3_disable_nvram_access(struct tg3 *tp)
3185{
63c3a66f 3186 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3187 u32 nvaccess = tr32(NVRAM_ACCESS);
3188
3189 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3190 }
3191}
3192
3193static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3194 u32 offset, u32 *val)
3195{
3196 u32 tmp;
3197 int i;
3198
3199 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3200 return -EINVAL;
3201
3202 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3203 EEPROM_ADDR_DEVID_MASK |
3204 EEPROM_ADDR_READ);
3205 tw32(GRC_EEPROM_ADDR,
3206 tmp |
3207 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3208 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3209 EEPROM_ADDR_ADDR_MASK) |
3210 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3211
3212 for (i = 0; i < 1000; i++) {
3213 tmp = tr32(GRC_EEPROM_ADDR);
3214
3215 if (tmp & EEPROM_ADDR_COMPLETE)
3216 break;
3217 msleep(1);
3218 }
3219 if (!(tmp & EEPROM_ADDR_COMPLETE))
3220 return -EBUSY;
3221
62cedd11
MC		 3222 tmp = tr32(GRC_EEPROM_DATA);
3223
3224 /*
3225 * The data will always be opposite the native endian
3226 * format. Perform a blind byteswap to compensate.
3227 */
3228 *val = swab32(tmp);
3229
ffbcfed4
MC		 3230 return 0;
3231}
3232
3233#define NVRAM_CMD_TIMEOUT 10000
3234
3235static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3236{
3237 int i;
3238
3239 tw32(NVRAM_CMD, nvram_cmd);
3240 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3241 udelay(10);
3242 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3243 udelay(10);
3244 break;
3245 }
3246 }
3247
3248 if (i == NVRAM_CMD_TIMEOUT)
3249 return -EBUSY;
3250
3251 return 0;
3252}
3253
3254static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3255{
63c3a66f
JP		 3256 if (tg3_flag(tp, NVRAM) &&
3257 tg3_flag(tp, NVRAM_BUFFERED) &&
3258 tg3_flag(tp, FLASH) &&
3259 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3260 (tp->nvram_jedecnum == JEDEC_ATMEL))
3261
3262 addr = ((addr / tp->nvram_pagesize) <<
3263 ATMEL_AT45DB0X1B_PAGE_POS) +
3264 (addr % tp->nvram_pagesize);
3265
3266 return addr;
3267}
3268
3269static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3270{
63c3a66f
JP		 3271 if (tg3_flag(tp, NVRAM) &&
3272 tg3_flag(tp, NVRAM_BUFFERED) &&
3273 tg3_flag(tp, FLASH) &&
3274 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3275 (tp->nvram_jedecnum == JEDEC_ATMEL))
3276
3277 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3278 tp->nvram_pagesize) +
3279 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3280
3281 return addr;
3282}
3283
e4f34110
MC		 3284/* NOTE: Data read in from NVRAM is byteswapped according to
3285 * the byteswapping settings for all other register accesses.
3286 * tg3 devices are BE devices, so on a BE machine, the data
3287 * returned will be exactly as it is seen in NVRAM. On a LE
3288 * machine, the 32-bit value will be byteswapped.
3289 */
ffbcfed4
MC		 3290static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3291{
3292 int ret;
3293
63c3a66f 3294 if (!tg3_flag(tp, NVRAM))
ffbcfed4
MC		 3295 return tg3_nvram_read_using_eeprom(tp, offset, val);
3296
3297 offset = tg3_nvram_phys_addr(tp, offset);
3298
3299 if (offset > NVRAM_ADDR_MSK)
3300 return -EINVAL;
3301
3302 ret = tg3_nvram_lock(tp);
3303 if (ret)
3304 return ret;
3305
3306 tg3_enable_nvram_access(tp);
3307
3308 tw32(NVRAM_ADDR, offset);
3309 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3310 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3311
3312 if (ret == 0)
e4f34110 3313 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 3314
3315 tg3_disable_nvram_access(tp);
3316
3317 tg3_nvram_unlock(tp);
3318
3319 return ret;
3320}
3321
a9dc529d
MC		 3322/* Ensures NVRAM data is in bytestream format. */
3323static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 3324{
3325 u32 v;
a9dc529d 3326 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 3327 if (!res)
a9dc529d 3328 *val = cpu_to_be32(v);
ffbcfed4
MC		 3329 return res;
3330}
3331
dbe9b92a
MC		 3332static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3333 u32 offset, u32 len, u8 *buf)
3334{
3335 int i, j, rc = 0;
3336 u32 val;
3337
3338 for (i = 0; i < len; i += 4) {
3339 u32 addr;
3340 __be32 data;
3341
3342 addr = offset + i;
3343
3344 memcpy(&data, buf + i, 4);
3345
3346 /*
3347 * The SEEPROM interface expects the data to always be opposite
3348 * the native endian format. We accomplish this by reversing
3349 * all the operations that would have been performed on the
3350 * data from a call to tg3_nvram_read_be32().
3351 */
3352 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3353
3354 val = tr32(GRC_EEPROM_ADDR);
3355 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3356
3357 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3358 EEPROM_ADDR_READ);
3359 tw32(GRC_EEPROM_ADDR, val |
3360 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3361 (addr & EEPROM_ADDR_ADDR_MASK) |
3362 EEPROM_ADDR_START |
3363 EEPROM_ADDR_WRITE);
3364
3365 for (j = 0; j < 1000; j++) {
3366 val = tr32(GRC_EEPROM_ADDR);
3367
3368 if (val & EEPROM_ADDR_COMPLETE)
3369 break;
3370 msleep(1);
3371 }
3372 if (!(val & EEPROM_ADDR_COMPLETE)) {
3373 rc = -EBUSY;
3374 break;
3375 }
3376 }
3377
3378 return rc;
3379}
3380
3381/* offset and length are dword aligned */
3382static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3383 u8 *buf)
3384{
3385 int ret = 0;
3386 u32 pagesize = tp->nvram_pagesize;
3387 u32 pagemask = pagesize - 1;
3388 u32 nvram_cmd;
3389 u8 *tmp;
3390
3391 tmp = kmalloc(pagesize, GFP_KERNEL);
3392 if (tmp == NULL)
3393 return -ENOMEM;
3394
3395 while (len) {
3396 int j;
3397 u32 phy_addr, page_off, size;
3398
3399 phy_addr = offset & ~pagemask;
3400
3401 for (j = 0; j < pagesize; j += 4) {
3402 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3403 (__be32 *) (tmp + j));
3404 if (ret)
3405 break;
3406 }
3407 if (ret)
3408 break;
3409
3410 page_off = offset & pagemask;
3411 size = pagesize;
3412 if (len < size)
3413 size = len;
3414
3415 len -= size;
3416
3417 memcpy(tmp + page_off, buf, size);
3418
3419 offset = offset + (pagesize - page_off);
3420
3421 tg3_enable_nvram_access(tp);
3422
3423 /*
3424 * Before we can erase the flash page, we need
3425 * to issue a special "write enable" command.
3426 */
3427 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3428
3429 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3430 break;
3431
3432 /* Erase the target page */
3433 tw32(NVRAM_ADDR, phy_addr);
3434
3435 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3436 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3437
3438 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3439 break;
3440
3441 /* Issue another write enable to start the write. */
3442 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3443
3444 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3445 break;
3446
3447 for (j = 0; j < pagesize; j += 4) {
3448 __be32 data;
3449
3450 data = *((__be32 *) (tmp + j));
3451
3452 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3453
3454 tw32(NVRAM_ADDR, phy_addr + j);
3455
3456 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3457 NVRAM_CMD_WR;
3458
3459 if (j == 0)
3460 nvram_cmd |= NVRAM_CMD_FIRST;
3461 else if (j == (pagesize - 4))
3462 nvram_cmd |= NVRAM_CMD_LAST;
3463
3464 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3465 if (ret)
3466 break;
3467 }
3468 if (ret)
3469 break;
3470 }
3471
3472 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3473 tg3_nvram_exec_cmd(tp, nvram_cmd);
3474
3475 kfree(tmp);
3476
3477 return ret;
3478}
3479
3480/* offset and length are dword aligned */
3481static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3482 u8 *buf)
3483{
3484 int i, ret = 0;
3485
3486 for (i = 0; i < len; i += 4, offset += 4) {
3487 u32 page_off, phy_addr, nvram_cmd;
3488 __be32 data;
3489
3490 memcpy(&data, buf + i, 4);
3491 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3492
3493 page_off = offset % tp->nvram_pagesize;
3494
3495 phy_addr = tg3_nvram_phys_addr(tp, offset);
3496
dbe9b92a
MC		 3497 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3498
3499 if (page_off == 0 || i == 0)
3500 nvram_cmd |= NVRAM_CMD_FIRST;
3501 if (page_off == (tp->nvram_pagesize - 4))
3502 nvram_cmd |= NVRAM_CMD_LAST;
3503
3504 if (i == (len - 4))
3505 nvram_cmd |= NVRAM_CMD_LAST;
3506
42278224
MC		 3507 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3508 !tg3_flag(tp, FLASH) ||
3509 !tg3_flag(tp, 57765_PLUS))
3510 tw32(NVRAM_ADDR, phy_addr);
3511
4153577a 3512 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
dbe9b92a
MC		 3513 !tg3_flag(tp, 5755_PLUS) &&
3514 (tp->nvram_jedecnum == JEDEC_ST) &&
3515 (nvram_cmd & NVRAM_CMD_FIRST)) {
3516 u32 cmd;
3517
3518 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3519 ret = tg3_nvram_exec_cmd(tp, cmd);
3520 if (ret)
3521 break;
3522 }
3523 if (!tg3_flag(tp, FLASH)) {
3524 /* We always do complete word writes to eeprom. */
3525 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3526 }
3527
3528 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3529 if (ret)
3530 break;
3531 }
3532 return ret;
3533}
3534
3535/* offset and length are dword aligned */
3536static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3537{
3538 int ret;
3539
3540 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3541 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3542 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3543 udelay(40);
3544 }
3545
3546 if (!tg3_flag(tp, NVRAM)) {
3547 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3548 } else {
3549 u32 grc_mode;
3550
3551 ret = tg3_nvram_lock(tp);
3552 if (ret)
3553 return ret;
3554
3555 tg3_enable_nvram_access(tp);
3556 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3557 tw32(NVRAM_WRITE1, 0x406);
3558
3559 grc_mode = tr32(GRC_MODE);
3560 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3561
3562 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3563 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3564 buf);
3565 } else {
3566 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3567 buf);
3568 }
3569
3570 grc_mode = tr32(GRC_MODE);
3571 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3572
3573 tg3_disable_nvram_access(tp);
3574 tg3_nvram_unlock(tp);
3575 }
3576
3577 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3578 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3579 udelay(40);
3580 }
3581
3582 return ret;
3583}
3584
997b4f13
MC		 3585#define RX_CPU_SCRATCH_BASE 0x30000
3586#define RX_CPU_SCRATCH_SIZE 0x04000
3587#define TX_CPU_SCRATCH_BASE 0x34000
3588#define TX_CPU_SCRATCH_SIZE 0x04000
3589
3590/* tp->lock is held. */
837c45bb 3591static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
997b4f13
MC		 3592{
3593 int i;
837c45bb 3594 const int iters = 10000;
997b4f13 3595
837c45bb
NS		 3596 for (i = 0; i < iters; i++) {
3597 tw32(cpu_base + CPU_STATE, 0xffffffff);
3598 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3599 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3600 break;
6d446ec3
GS		 3601 if (pci_channel_offline(tp->pdev))
3602 return -EBUSY;
837c45bb
NS		 3603 }
3604
3605 return (i == iters) ? -EBUSY : 0;
3606}
3607
3608/* tp->lock is held. */
3609static int tg3_rxcpu_pause(struct tg3 *tp)
3610{
3611 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3612
3613 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3614 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3615 udelay(10);
3616
3617 return rc;
3618}
3619
3620/* tp->lock is held. */
3621static int tg3_txcpu_pause(struct tg3 *tp)
3622{
3623 return tg3_pause_cpu(tp, TX_CPU_BASE);
3624}
3625
3626/* tp->lock is held. */
3627static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3628{
3629 tw32(cpu_base + CPU_STATE, 0xffffffff);
3630 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3631}
3632
3633/* tp->lock is held. */
3634static void tg3_rxcpu_resume(struct tg3 *tp)
3635{
3636 tg3_resume_cpu(tp, RX_CPU_BASE);
3637}
3638
3639/* tp->lock is held. */
3640static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3641{
3642 int rc;
3643
3644 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
997b4f13 3645
4153577a 3646 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
997b4f13
MC		 3647 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3648
3649 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3650 return 0;
3651 }
837c45bb
NS		 3652 if (cpu_base == RX_CPU_BASE) {
3653 rc = tg3_rxcpu_pause(tp);
997b4f13 3654 } else {
7e6c63f0
HM		 3655 /*
3656 * There is only an Rx CPU for the 5750 derivative in the
3657 * BCM4785.
3658 */
3659 if (tg3_flag(tp, IS_SSB_CORE))
3660 return 0;
3661
837c45bb 3662 rc = tg3_txcpu_pause(tp);
997b4f13
MC		 3663 }
3664
837c45bb 3665 if (rc) {
997b4f13 3666 netdev_err(tp->dev, "%s timed out, %s CPU\n",
837c45bb 3667 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
997b4f13
MC		 3668 return -ENODEV;
3669 }
3670
3671 /* Clear firmware's nvram arbitration. */
3672 if (tg3_flag(tp, NVRAM))
3673 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3674 return 0;
3675}
3676
31f11a95
NS		 3677static int tg3_fw_data_len(struct tg3 *tp,
3678 const struct tg3_firmware_hdr *fw_hdr)
3679{
3680 int fw_len;
3681
3682 /* Non fragmented firmware have one firmware header followed by a
3683 * contiguous chunk of data to be written. The length field in that
3684 * header is not the length of data to be written but the complete
3685 * length of the bss. The data length is determined based on
3686 * tp->fw->size minus headers.
3687 *
3688 * Fragmented firmware have a main header followed by multiple
3689 * fragments. Each fragment is identical to non fragmented firmware
3690 * with a firmware header followed by a contiguous chunk of data. In
3691 * the main header, the length field is unused and set to 0xffffffff.
3692 * In each fragment header the length is the entire size of that
3693 * fragment i.e. fragment data + header length. Data length is
3694 * therefore length field in the header minus TG3_FW_HDR_LEN.
3695 */
3696 if (tp->fw_len == 0xffffffff)
3697 fw_len = be32_to_cpu(fw_hdr->len);
3698 else
3699 fw_len = tp->fw->size;
3700
3701 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3702}
3703
997b4f13
MC		 3704/* tp->lock is held. */
3705static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3706 u32 cpu_scratch_base, int cpu_scratch_size,
77997ea3 3707 const struct tg3_firmware_hdr *fw_hdr)
997b4f13 3708{
c4dab506 3709 int err, i;
997b4f13 3710 void (*write_op)(struct tg3 *, u32, u32);
31f11a95 3711 int total_len = tp->fw->size;
997b4f13
MC		 3712
3713 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3714 netdev_err(tp->dev,
3715 "%s: Trying to load TX cpu firmware which is 5705\n",
3716 __func__);
3717 return -EINVAL;
3718 }
3719
c4dab506 3720 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
997b4f13
MC		 3721 write_op = tg3_write_mem;
3722 else
3723 write_op = tg3_write_indirect_reg32;
3724
c4dab506
NS		 3725 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3726 /* It is possible that bootcode is still loading at this point.
3727 * Get the nvram lock first before halting the cpu.
3728 */
3729 int lock_err = tg3_nvram_lock(tp);
3730 err = tg3_halt_cpu(tp, cpu_base);
3731 if (!lock_err)
3732 tg3_nvram_unlock(tp);
3733 if (err)
3734 goto out;
997b4f13 3735
c4dab506
NS		 3736 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3737 write_op(tp, cpu_scratch_base + i, 0);
3738 tw32(cpu_base + CPU_STATE, 0xffffffff);
3739 tw32(cpu_base + CPU_MODE,
3740 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3741 } else {
3742 /* Subtract additional main header for fragmented firmware and
3743 * advance to the first fragment
3744 */
3745 total_len -= TG3_FW_HDR_LEN;
3746 fw_hdr++;
3747 }
77997ea3 3748
31f11a95
NS		 3749 do {
3750 u32 *fw_data = (u32 *)(fw_hdr + 1);
3751 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3752 write_op(tp, cpu_scratch_base +
3753 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3754 (i * sizeof(u32)),
3755 be32_to_cpu(fw_data[i]));
3756
3757 total_len -= be32_to_cpu(fw_hdr->len);
3758
3759 /* Advance to next fragment */
3760 fw_hdr = (struct tg3_firmware_hdr *)
3761 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3762 } while (total_len > 0);
997b4f13
MC		 3763
3764 err = 0;
3765
3766out:
3767 return err;
3768}
3769
f4bffb28
NS		 3770/* tp->lock is held. */
3771static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3772{
3773 int i;
3774 const int iters = 5;
3775
3776 tw32(cpu_base + CPU_STATE, 0xffffffff);
3777 tw32_f(cpu_base + CPU_PC, pc);
3778
3779 for (i = 0; i < iters; i++) {
3780 if (tr32(cpu_base + CPU_PC) == pc)
3781 break;
3782 tw32(cpu_base + CPU_STATE, 0xffffffff);
3783 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3784 tw32_f(cpu_base + CPU_PC, pc);
3785 udelay(1000);
3786 }
3787
3788 return (i == iters) ? -EBUSY : 0;
3789}
3790
997b4f13
MC		 3791/* tp->lock is held. */
3792static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3793{
77997ea3 3794 const struct tg3_firmware_hdr *fw_hdr;
f4bffb28 3795 int err;
997b4f13 3796
77997ea3 3797 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3798
3799 /* Firmware blob starts with version numbers, followed by
3800 start address and length. We are setting complete length.
3801 length = end_address_of_bss - start_address_of_text.
3802 Remainder is the blob to be loaded contiguously
3803 from start address. */
3804
997b4f13
MC		 3805 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3806 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
77997ea3 3807 fw_hdr);
997b4f13
MC		 3808 if (err)
3809 return err;
3810
3811 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3812 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
77997ea3 3813 fw_hdr);
997b4f13
MC		 3814 if (err)
3815 return err;
3816
3817 /* Now startup only the RX cpu. */
77997ea3
NS		 3818 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3819 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3820 if (err) {
997b4f13
MC		 3821 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3822 "should be %08x\n", __func__,
77997ea3
NS		 3823 tr32(RX_CPU_BASE + CPU_PC),
3824 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3825 return -ENODEV;
3826 }
837c45bb
NS		 3827
3828 tg3_rxcpu_resume(tp);
997b4f13
MC		 3829
3830 return 0;
3831}
3832
c4dab506
NS		 3833static int tg3_validate_rxcpu_state(struct tg3 *tp)
3834{
3835 const int iters = 1000;
3836 int i;
3837 u32 val;
3838
3839 /* Wait for boot code to complete initialization and enter service
3840 * loop. It is then safe to download service patches
3841 */
3842 for (i = 0; i < iters; i++) {
3843 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3844 break;
3845
3846 udelay(10);
3847 }
3848
3849 if (i == iters) {
3850 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3851 return -EBUSY;
3852 }
3853
3854 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3855 if (val & 0xff) {
3856 netdev_warn(tp->dev,
3857 "Other patches exist. Not downloading EEE patch\n");
3858 return -EEXIST;
3859 }
3860
3861 return 0;
3862}
3863
3864/* tp->lock is held. */
3865static void tg3_load_57766_firmware(struct tg3 *tp)
3866{
3867 struct tg3_firmware_hdr *fw_hdr;
3868
3869 if (!tg3_flag(tp, NO_NVRAM))
3870 return;
3871
3872 if (tg3_validate_rxcpu_state(tp))
3873 return;
3874
3875 if (!tp->fw)
3876 return;
3877
3878 /* This firmware blob has a different format than older firmware
3879 * releases as given below. The main difference is we have fragmented
3880 * data to be written to non-contiguous locations.
3881 *
3882 * In the beginning we have a firmware header identical to other
3883 * firmware which consists of version, base addr and length. The length
3884 * here is unused and set to 0xffffffff.
3885 *
3886 * This is followed by a series of firmware fragments which are
3887 * individually identical to previous firmware. i.e. they have the
3888 * firmware header and followed by data for that fragment. The version
3889 * field of the individual fragment header is unused.
3890 */
3891
3892 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3893 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3894 return;
3895
3896 if (tg3_rxcpu_pause(tp))
3897 return;
3898
3899 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3900 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3901
3902 tg3_rxcpu_resume(tp);
3903}
3904
997b4f13
MC		 3905/* tp->lock is held. */
3906static int tg3_load_tso_firmware(struct tg3 *tp)
3907{
77997ea3 3908 const struct tg3_firmware_hdr *fw_hdr;
997b4f13 3909 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
f4bffb28 3910 int err;
997b4f13 3911
1caf13eb 3912 if (!tg3_flag(tp, FW_TSO))
997b4f13
MC		 3913 return 0;
3914
77997ea3 3915 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3916
3917 /* Firmware blob starts with version numbers, followed by
3918 start address and length. We are setting complete length.
3919 length = end_address_of_bss - start_address_of_text.
3920 Remainder is the blob to be loaded contiguously
3921 from start address. */
3922
997b4f13 3923 cpu_scratch_size = tp->fw_len;
997b4f13 3924
4153577a 3925 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
997b4f13
MC		 3926 cpu_base = RX_CPU_BASE;
3927 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3928 } else {
3929 cpu_base = TX_CPU_BASE;
3930 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3931 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3932 }
3933
3934 err = tg3_load_firmware_cpu(tp, cpu_base,
3935 cpu_scratch_base, cpu_scratch_size,
77997ea3 3936 fw_hdr);
997b4f13
MC		 3937 if (err)
3938 return err;
3939
3940 /* Now startup the cpu. */
77997ea3
NS		 3941 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3942 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3943 if (err) {
997b4f13
MC		 3944 netdev_err(tp->dev,
3945 "%s fails to set CPU PC, is %08x should be %08x\n",
77997ea3
NS		 3946 __func__, tr32(cpu_base + CPU_PC),
3947 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3948 return -ENODEV;
3949 }
837c45bb
NS		 3950
3951 tg3_resume_cpu(tp, cpu_base);
997b4f13
MC		 3952 return 0;
3953}
3954
f022ae62
MC		 3955/* tp->lock is held. */
3956static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3957{
3958 u32 addr_high, addr_low;
3959
3960 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3961 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3962 (mac_addr[4] << 8) | mac_addr[5]);
3963
3964 if (index < 4) {
3965 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3966 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3967 } else {
3968 index -= 4;
3969 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3970 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3971 }
3972}
997b4f13 3973
3f007891 3974/* tp->lock is held. */
953c96e0 3975static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3f007891 3976{
f022ae62 3977 u32 addr_high;
3f007891
MC		 3978 int i;
3979
3f007891
MC		 3980 for (i = 0; i < 4; i++) {
3981 if (i == 1 && skip_mac_1)
3982 continue;
f022ae62 3983 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3f007891
MC		 3984 }
3985
4153577a
JP		 3986 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3987 tg3_asic_rev(tp) == ASIC_REV_5704) {
f022ae62
MC		 3988 for (i = 4; i < 16; i++)
3989 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3f007891
MC		 3990 }
3991
3992 addr_high = (tp->dev->dev_addr[0] +
3993 tp->dev->dev_addr[1] +
3994 tp->dev->dev_addr[2] +
3995 tp->dev->dev_addr[3] +
3996 tp->dev->dev_addr[4] +
3997 tp->dev->dev_addr[5]) &
3998 TX_BACKOFF_SEED_MASK;
3999 tw32(MAC_TX_BACKOFF_SEED, addr_high);
4000}
4001
c866b7ea 4002static void tg3_enable_register_access(struct tg3 *tp)
1da177e4 4003{
c866b7ea
RW		 4004 /*
4005 * Make sure register accesses (indirect or otherwise) will function
4006 * correctly.
1da177e4
LT		 4007 */
4008 pci_write_config_dword(tp->pdev,
c866b7ea
RW		 4009 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4010}
1da177e4 4011
c866b7ea
RW		 4012static int tg3_power_up(struct tg3 *tp)
4013{
bed9829f 4014 int err;
8c6bda1a 4015
bed9829f 4016 tg3_enable_register_access(tp);
1da177e4 4017
bed9829f
MC		 4018 err = pci_set_power_state(tp->pdev, PCI_D0);
4019 if (!err) {
4020 /* Switch out of Vaux if it is a NIC */
4021 tg3_pwrsrc_switch_to_vmain(tp);
4022 } else {
4023 netdev_err(tp->dev, "Transition to D0 failed\n");
4024 }
1da177e4 4025
bed9829f 4026 return err;
c866b7ea 4027}
1da177e4 4028
953c96e0 4029static int tg3_setup_phy(struct tg3 *, bool);
4b409522 4030
c866b7ea
RW		 4031static int tg3_power_down_prepare(struct tg3 *tp)
4032{
4033 u32 misc_host_ctrl;
4034 bool device_should_wake, do_low_power;
4035
4036 tg3_enable_register_access(tp);
5e7dfd0f
MC		 4037
4038 /* Restore the CLKREQ setting. */
0f49bfbd
JL		 4039 if (tg3_flag(tp, CLKREQ_BUG))
4040 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4041 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 4042
1da177e4
LT		 4043 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4044 tw32(TG3PCI_MISC_HOST_CTRL,
4045 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4046
c866b7ea 4047 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
63c3a66f 4048 tg3_flag(tp, WOL_ENABLE);
05ac4cb7 4049
63c3a66f 4050 if (tg3_flag(tp, USE_PHYLIB)) {
0a459aac 4051 do_low_power = false;
f07e9af3 4052 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
80096068 4053 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
b02fd9e3 4054 struct phy_device *phydev;
0a459aac 4055 u32 phyid, advertising;
b02fd9e3 4056
ead2402c 4057 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 4058
80096068 4059 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
b02fd9e3 4060
c6700ce2
MC		 4061 tp->link_config.speed = phydev->speed;
4062 tp->link_config.duplex = phydev->duplex;
4063 tp->link_config.autoneg = phydev->autoneg;
4064 tp->link_config.advertising = phydev->advertising;
b02fd9e3
MC		 4065
4066 advertising = ADVERTISED_TP |
4067 ADVERTISED_Pause |
4068 ADVERTISED_Autoneg |
4069 ADVERTISED_10baseT_Half;
4070
63c3a66f
JP		 4071 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4072 if (tg3_flag(tp, WOL_SPEED_100MB))
b02fd9e3
MC		 4073 advertising |=
4074 ADVERTISED_100baseT_Half |
4075 ADVERTISED_100baseT_Full |
4076 ADVERTISED_10baseT_Full;
4077 else
4078 advertising |= ADVERTISED_10baseT_Full;
4079 }
4080
4081 phydev->advertising = advertising;
4082
4083 phy_start_aneg(phydev);
0a459aac
MC		 4084
4085 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 4086 if (phyid != PHY_ID_BCMAC131) {
4087 phyid &= PHY_BCM_OUI_MASK;
4088 if (phyid == PHY_BCM_OUI_1 ||
4089 phyid == PHY_BCM_OUI_2 ||
4090 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 4091 do_low_power = true;
4092 }
b02fd9e3 4093 }
dd477003 4094 } else {
2023276e 4095 do_low_power = true;
0a459aac 4096
c6700ce2 4097 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
80096068 4098 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
1da177e4 4099
2855b9fe 4100 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
953c96e0 4101 tg3_setup_phy(tp, false);
1da177e4
LT		 4102 }
4103
4153577a 4104 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 4105 u32 val;
4106
4107 val = tr32(GRC_VCPU_EXT_CTRL);
4108 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
63c3a66f 4109 } else if (!tg3_flag(tp, ENABLE_ASF)) {
6921d201
MC		 4110 int i;
4111 u32 val;
4112
4113 for (i = 0; i < 200; i++) {
4114 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4115 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4116 break;
4117 msleep(1);
4118 }
4119 }
63c3a66f 4120 if (tg3_flag(tp, WOL_CAP))
a85feb8c
GZ		 4121 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4122 WOL_DRV_STATE_SHUTDOWN |
4123 WOL_DRV_WOL |
4124 WOL_SET_MAGIC_PKT);
6921d201 4125
05ac4cb7 4126 if (device_should_wake) {
1da177e4
LT		 4127 u32 mac_mode;
4128
f07e9af3 4129 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
b4bd2929
MC		 4130 if (do_low_power &&
4131 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4132 tg3_phy_auxctl_write(tp,
4133 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4134 MII_TG3_AUXCTL_PCTL_WOL_EN |
4135 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4136 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
dd477003
MC		 4137 udelay(40);
4138 }
1da177e4 4139
f07e9af3 4140 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3f7045c1 4141 mac_mode = MAC_MODE_PORT_MODE_GMII;
942d1af0
NS		 4142 else if (tp->phy_flags &
4143 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4144 if (tp->link_config.active_speed == SPEED_1000)
4145 mac_mode = MAC_MODE_PORT_MODE_GMII;
4146 else
4147 mac_mode = MAC_MODE_PORT_MODE_MII;
4148 } else
3f7045c1 4149 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 4150
e8f3f6ca 4151 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4153577a 4152 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
63c3a66f 4153 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
e8f3f6ca
MC		 4154 SPEED_100 : SPEED_10;
4155 if (tg3_5700_link_polarity(tp, speed))
4156 mac_mode |= MAC_MODE_LINK_POLARITY;
4157 else
4158 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4159 }
1da177e4
LT		 4160 } else {
4161 mac_mode = MAC_MODE_PORT_MODE_TBI;
4162 }
4163
63c3a66f 4164 if (!tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 4165 tw32(MAC_LED_CTRL, tp->led_ctrl);
4166
05ac4cb7 4167 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
63c3a66f
JP		 4168 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4169 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
05ac4cb7 4170 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 4171
63c3a66f 4172 if (tg3_flag(tp, ENABLE_APE))
d2394e6b
MC		 4173 mac_mode |= MAC_MODE_APE_TX_EN |
4174 MAC_MODE_APE_RX_EN |
4175 MAC_MODE_TDE_ENABLE;
3bda1258 4176
1da177e4
LT		 4177 tw32_f(MAC_MODE, mac_mode);
4178 udelay(100);
4179
4180 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4181 udelay(10);
4182 }
4183
63c3a66f 4184 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4153577a
JP		 4185 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4186 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 4187 u32 base_val;
4188
4189 base_val = tp->pci_clock_ctrl;
4190 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4191 CLOCK_CTRL_TXCLK_DISABLE);
4192
b401e9e2
MC		 4193 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4194 CLOCK_CTRL_PWRDOWN_PLL133, 40);
63c3a66f
JP		 4195 } else if (tg3_flag(tp, 5780_CLASS) ||
4196 tg3_flag(tp, CPMU_PRESENT) ||
4153577a 4197 tg3_asic_rev(tp) == ASIC_REV_5906) {
4cf78e4f 4198 /* do nothing */
63c3a66f 4199 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
1da177e4
LT		 4200 u32 newbits1, newbits2;
4201
4153577a
JP		 4202 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4203 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4204 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4205 CLOCK_CTRL_TXCLK_DISABLE |
4206 CLOCK_CTRL_ALTCLK);
4207 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
63c3a66f 4208 } else if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4209 newbits1 = CLOCK_CTRL_625_CORE;
4210 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4211 } else {
4212 newbits1 = CLOCK_CTRL_ALTCLK;
4213 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4214 }
4215
b401e9e2
MC		 4216 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4217 40);
1da177e4 4218
b401e9e2
MC		 4219 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4220 40);
1da177e4 4221
63c3a66f 4222 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4223 u32 newbits3;
4224
4153577a
JP		 4225 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4226 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4227 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4228 CLOCK_CTRL_TXCLK_DISABLE |
4229 CLOCK_CTRL_44MHZ_CORE);
4230 } else {
4231 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4232 }
4233
b401e9e2
MC		 4234 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4235 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 4236 }
4237 }
4238
63c3a66f 4239 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
0a459aac 4240 tg3_power_down_phy(tp, do_low_power);
6921d201 4241
cd0d7228 4242 tg3_frob_aux_power(tp, true);
1da177e4
LT		 4243
4244 /* Workaround for unstable PLL clock */
7e6c63f0 4245 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4153577a
JP		 4246 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4247 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
1da177e4
LT		 4248 u32 val = tr32(0x7d00);
4249
4250 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4251 tw32(0x7d00, val);
63c3a66f 4252 if (!tg3_flag(tp, ENABLE_ASF)) {
ec41c7df
MC		 4253 int err;
4254
4255 err = tg3_nvram_lock(tp);
1da177e4 4256 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 4257 if (!err)
4258 tg3_nvram_unlock(tp);
6921d201 4259 }
1da177e4
LT		 4260 }
4261
bbadf503
MC		 4262 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4263
2e460fc0
NS		 4264 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4265
c866b7ea
RW		 4266 return 0;
4267}
12dac075 4268
c866b7ea
RW		 4269static void tg3_power_down(struct tg3 *tp)
4270{
63c3a66f 4271 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
c866b7ea 4272 pci_set_power_state(tp->pdev, PCI_D3hot);
1da177e4
LT		 4273}
4274
1da177e4
LT		 4275static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4276{
4277 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4278 case MII_TG3_AUX_STAT_10HALF:
4279 *speed = SPEED_10;
4280 *duplex = DUPLEX_HALF;
4281 break;
4282
4283 case MII_TG3_AUX_STAT_10FULL:
4284 *speed = SPEED_10;
4285 *duplex = DUPLEX_FULL;
4286 break;
4287
4288 case MII_TG3_AUX_STAT_100HALF:
4289 *speed = SPEED_100;
4290 *duplex = DUPLEX_HALF;
4291 break;
4292
4293 case MII_TG3_AUX_STAT_100FULL:
4294 *speed = SPEED_100;
4295 *duplex = DUPLEX_FULL;
4296 break;
4297
4298 case MII_TG3_AUX_STAT_1000HALF:
4299 *speed = SPEED_1000;
4300 *duplex = DUPLEX_HALF;
4301 break;
4302
4303 case MII_TG3_AUX_STAT_1000FULL:
4304 *speed = SPEED_1000;
4305 *duplex = DUPLEX_FULL;
4306 break;
4307
4308 default:
f07e9af3 4309 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
715116a1
MC		 4310 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4311 SPEED_10;
4312 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4313 DUPLEX_HALF;
4314 break;
4315 }
e740522e
MC		 4316 *speed = SPEED_UNKNOWN;
4317 *duplex = DUPLEX_UNKNOWN;
1da177e4 4318 break;
855e1111 4319 }
1da177e4
LT		 4320}
4321
42b64a45 4322static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
1da177e4 4323{
42b64a45
MC		 4324 int err = 0;
4325 u32 val, new_adv;
1da177e4 4326
42b64a45 4327 new_adv = ADVERTISE_CSMA;
202ff1c2 4328 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
f88788f0 4329 new_adv |= mii_advertise_flowctrl(flowctrl);
1da177e4 4330
42b64a45
MC		 4331 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4332 if (err)
4333 goto done;
ba4d07a8 4334
4f272096
MC		 4335 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4336 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
ba4d07a8 4337
4153577a
JP		 4338 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4339 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4f272096 4340 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
ba4d07a8 4341
4f272096
MC		 4342 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4343 if (err)
4344 goto done;
4345 }
1da177e4 4346
42b64a45
MC		 4347 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4348 goto done;
52b02d04 4349
42b64a45
MC		 4350 tw32(TG3_CPMU_EEE_MODE,
4351 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
52b02d04 4352
daf3ec68 4353 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
42b64a45
MC		 4354 if (!err) {
4355 u32 err2;
52b02d04 4356
b715ce94
MC		 4357 val = 0;
4358 /* Advertise 100-BaseTX EEE ability */
4359 if (advertise & ADVERTISED_100baseT_Full)
4360 val |= MDIO_AN_EEE_ADV_100TX;
4361 /* Advertise 1000-BaseT EEE ability */
4362 if (advertise & ADVERTISED_1000baseT_Full)
4363 val |= MDIO_AN_EEE_ADV_1000T;
9e2ecbeb
NS		 4364
4365 if (!tp->eee.eee_enabled) {
4366 val = 0;
4367 tp->eee.advertised = 0;
4368 } else {
4369 tp->eee.advertised = advertise &
4370 (ADVERTISED_100baseT_Full |
4371 ADVERTISED_1000baseT_Full);
4372 }
4373
b715ce94
MC		 4374 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4375 if (err)
4376 val = 0;
4377
4153577a 4378 switch (tg3_asic_rev(tp)) {
21a00ab2
MC		 4379 case ASIC_REV_5717:
4380 case ASIC_REV_57765:
55086ad9 4381 case ASIC_REV_57766:
21a00ab2 4382 case ASIC_REV_5719:
b715ce94
MC		 4383 /* If we advertised any eee advertisements above... */
4384 if (val)
4385 val = MII_TG3_DSP_TAP26_ALNOKO |
4386 MII_TG3_DSP_TAP26_RMRXSTO |
4387 MII_TG3_DSP_TAP26_OPCSINPT;
21a00ab2 4388 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
be671947
MC		 4389 /* Fall through */
4390 case ASIC_REV_5720:
c65a17f4 4391 case ASIC_REV_5762:
be671947
MC		 4392 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4393 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4394 MII_TG3_DSP_CH34TP2_HIBW01);
21a00ab2 4395 }
52b02d04 4396
daf3ec68 4397 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
42b64a45
MC		 4398 if (!err)
4399 err = err2;
4400 }
4401
4402done:
4403 return err;
4404}
4405
4406static void tg3_phy_copper_begin(struct tg3 *tp)
4407{
d13ba512
MC		 4408 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4409 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4410 u32 adv, fc;
4411
942d1af0
NS		 4412 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4413 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
d13ba512
MC		 4414 adv = ADVERTISED_10baseT_Half |
4415 ADVERTISED_10baseT_Full;
4416 if (tg3_flag(tp, WOL_SPEED_100MB))
4417 adv |= ADVERTISED_100baseT_Half |
4418 ADVERTISED_100baseT_Full;
7c786065
NS		 4419 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4420 if (!(tp->phy_flags &
4421 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4422 adv |= ADVERTISED_1000baseT_Half;
4423 adv |= ADVERTISED_1000baseT_Full;
4424 }
d13ba512
MC		 4425
4426 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
42b64a45 4427 } else {
d13ba512
MC		 4428 adv = tp->link_config.advertising;
4429 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4430 adv &= ~(ADVERTISED_1000baseT_Half |
4431 ADVERTISED_1000baseT_Full);
4432
4433 fc = tp->link_config.flowctrl;
52b02d04 4434 }
52b02d04 4435
d13ba512 4436 tg3_phy_autoneg_cfg(tp, adv, fc);
52b02d04 4437
942d1af0
NS		 4438 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4439 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4440 /* Normally during power down we want to autonegotiate
4441 * the lowest possible speed for WOL. However, to avoid
4442 * link flap, we leave it untouched.
4443 */
4444 return;
4445 }
4446
d13ba512
MC		 4447 tg3_writephy(tp, MII_BMCR,
4448 BMCR_ANENABLE | BMCR_ANRESTART);
4449 } else {
4450 int i;
1da177e4
LT		 4451 u32 bmcr, orig_bmcr;
4452
4453 tp->link_config.active_speed = tp->link_config.speed;
4454 tp->link_config.active_duplex = tp->link_config.duplex;
4455
7c6cdead
NS		 4456 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4457 /* With autoneg disabled, 5715 only links up when the
4458 * advertisement register has the configured speed
4459 * enabled.
4460 */
4461 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4462 }
4463
1da177e4
LT		 4464 bmcr = 0;
4465 switch (tp->link_config.speed) {
4466 default:
4467 case SPEED_10:
4468 break;
4469
4470 case SPEED_100:
4471 bmcr |= BMCR_SPEED100;
4472 break;
4473
4474 case SPEED_1000:
221c5637 4475 bmcr |= BMCR_SPEED1000;
1da177e4 4476 break;
855e1111 4477 }
1da177e4
LT		 4478
4479 if (tp->link_config.duplex == DUPLEX_FULL)
4480 bmcr |= BMCR_FULLDPLX;
4481
4482 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4483 (bmcr != orig_bmcr)) {
4484 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4485 for (i = 0; i < 1500; i++) {
4486 u32 tmp;
4487
4488 udelay(10);
4489 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4490 tg3_readphy(tp, MII_BMSR, &tmp))
4491 continue;
4492 if (!(tmp & BMSR_LSTATUS)) {
4493 udelay(40);
4494 break;
4495 }
4496 }
4497 tg3_writephy(tp, MII_BMCR, bmcr);
4498 udelay(40);
4499 }
1da177e4
LT		 4500 }
4501}
4502
fdad8de4
NS		 4503static int tg3_phy_pull_config(struct tg3 *tp)
4504{
4505 int err;
4506 u32 val;
4507
4508 err = tg3_readphy(tp, MII_BMCR, &val);
4509 if (err)
4510 goto done;
4511
4512 if (!(val & BMCR_ANENABLE)) {
4513 tp->link_config.autoneg = AUTONEG_DISABLE;
4514 tp->link_config.advertising = 0;
4515 tg3_flag_clear(tp, PAUSE_AUTONEG);
4516
4517 err = -EIO;
4518
4519 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4520 case 0:
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4522 goto done;
4523
4524 tp->link_config.speed = SPEED_10;
4525 break;
4526 case BMCR_SPEED100:
4527 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4528 goto done;
4529
4530 tp->link_config.speed = SPEED_100;
4531 break;
4532 case BMCR_SPEED1000:
4533 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4534 tp->link_config.speed = SPEED_1000;
4535 break;
4536 }
4537 /* Fall through */
4538 default:
4539 goto done;
4540 }
4541
4542 if (val & BMCR_FULLDPLX)
4543 tp->link_config.duplex = DUPLEX_FULL;
4544 else
4545 tp->link_config.duplex = DUPLEX_HALF;
4546
4547 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4548
4549 err = 0;
4550 goto done;
4551 }
4552
4553 tp->link_config.autoneg = AUTONEG_ENABLE;
4554 tp->link_config.advertising = ADVERTISED_Autoneg;
4555 tg3_flag_set(tp, PAUSE_AUTONEG);
4556
4557 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4558 u32 adv;
4559
4560 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4561 if (err)
4562 goto done;
4563
4564 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4565 tp->link_config.advertising |= adv | ADVERTISED_TP;
4566
4567 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4568 } else {
4569 tp->link_config.advertising |= ADVERTISED_FIBRE;
4570 }
4571
4572 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4573 u32 adv;
4574
4575 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4576 err = tg3_readphy(tp, MII_CTRL1000, &val);
4577 if (err)
4578 goto done;
4579
4580 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4581 } else {
4582 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4583 if (err)
4584 goto done;
4585
4586 adv = tg3_decode_flowctrl_1000X(val);
4587 tp->link_config.flowctrl = adv;
4588
4589 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4590 adv = mii_adv_to_ethtool_adv_x(val);
4591 }
4592
4593 tp->link_config.advertising |= adv;
4594 }
4595
4596done:
4597 return err;
4598}
4599
1da177e4
LT		 4600static int tg3_init_5401phy_dsp(struct tg3 *tp)
4601{
4602 int err;
4603
4604 /* Turn off tap power management. */
4605 /* Set Extended packet length bit */
b4bd2929 4606 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
1da177e4 4607
6ee7c0a0
MC		 4608 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4609 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4610 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4611 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4612 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
1da177e4
LT		 4613
4614 udelay(40);
4615
4616 return err;
4617}
4618
ed1ff5c3
NS		 4619static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4620{
5b6c273a 4621 struct ethtool_eee eee;
ed1ff5c3
NS		 4622
4623 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4624 return true;
4625
5b6c273a 4626 tg3_eee_pull_config(tp, &eee);
ed1ff5c3 4627
5b6c273a
NS		 4628 if (tp->eee.eee_enabled) {
4629 if (tp->eee.advertised != eee.advertised ||
4630 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4631 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4632 return false;
4633 } else {
4634 /* EEE is disabled but we're advertising */
4635 if (eee.advertised)
4636 return false;
4637 }
ed1ff5c3
NS		 4638
4639 return true;
4640}
4641
e2bf73e7 4642static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
1da177e4 4643{
e2bf73e7 4644 u32 advmsk, tgtadv, advertising;
3600d918 4645
e2bf73e7
MC		 4646 advertising = tp->link_config.advertising;
4647 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
1da177e4 4648
e2bf73e7
MC		 4649 advmsk = ADVERTISE_ALL;
4650 if (tp->link_config.active_duplex == DUPLEX_FULL) {
f88788f0 4651 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
e2bf73e7
MC		 4652 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4653 }
1da177e4 4654
e2bf73e7
MC		 4655 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4656 return false;
4657
4658 if ((*lcladv & advmsk) != tgtadv)
4659 return false;
b99d2a57 4660
f07e9af3 4661 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1da177e4
LT		 4662 u32 tg3_ctrl;
4663
e2bf73e7 4664 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
3600d918 4665
221c5637 4666 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
e2bf73e7 4667 return false;
1da177e4 4668
3198e07f 4669 if (tgtadv &&
4153577a
JP		 4670 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4671 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
3198e07f
MC		 4672 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4673 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4674 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4675 } else {
4676 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4677 }
4678
e2bf73e7
MC		 4679 if (tg3_ctrl != tgtadv)
4680 return false;
ef167e27
MC		 4681 }
4682
e2bf73e7 4683 return true;
ef167e27
MC		 4684}
4685
859edb26
MC		 4686static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4687{
4688 u32 lpeth = 0;
4689
4690 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4691 u32 val;
4692
4693 if (tg3_readphy(tp, MII_STAT1000, &val))
4694 return false;
4695
4696 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4697 }
4698
4699 if (tg3_readphy(tp, MII_LPA, rmtadv))
4700 return false;
4701
4702 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4703 tp->link_config.rmt_adv = lpeth;
4704
4705 return true;
4706}
4707
953c96e0 4708static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
f4a46d1f
NNS		 4709{
4710 if (curr_link_up != tp->link_up) {
4711 if (curr_link_up) {
84421b99 4712 netif_carrier_on(tp->dev);
f4a46d1f 4713 } else {
84421b99 4714 netif_carrier_off(tp->dev);
f4a46d1f
NNS		 4715 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4716 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4717 }
4718
4719 tg3_link_report(tp);
4720 return true;
4721 }
4722
4723 return false;
4724}
4725
3310e248
MC		 4726static void tg3_clear_mac_status(struct tg3 *tp)
4727{
4728 tw32(MAC_EVENT, 0);
4729
4730 tw32_f(MAC_STATUS,
4731 MAC_STATUS_SYNC_CHANGED |
4732 MAC_STATUS_CFG_CHANGED |
4733 MAC_STATUS_MI_COMPLETION |
4734 MAC_STATUS_LNKSTATE_CHANGED);
4735 udelay(40);
4736}
4737
9e2ecbeb
NS		 4738static void tg3_setup_eee(struct tg3 *tp)
4739{
4740 u32 val;
4741
4742 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4743 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4744 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4745 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4746
4747 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4748
4749 tw32_f(TG3_CPMU_EEE_CTRL,
4750 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4751
4752 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4753 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4754 TG3_CPMU_EEEMD_LPI_IN_RX |
4755 TG3_CPMU_EEEMD_EEE_ENABLE;
4756
4757 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4758 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4759
4760 if (tg3_flag(tp, ENABLE_APE))
4761 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4762
4763 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4764
4765 tw32_f(TG3_CPMU_EEE_DBTMR1,
4766 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4767 (tp->eee.tx_lpi_timer & 0xffff));
4768
4769 tw32_f(TG3_CPMU_EEE_DBTMR2,
4770 TG3_CPMU_DBTMR2_APE_TX_2047US |
4771 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4772}
4773
953c96e0 4774static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
1da177e4 4775{
953c96e0 4776 bool current_link_up;
f833c4c1 4777 u32 bmsr, val;
ef167e27 4778 u32 lcl_adv, rmt_adv;
1da177e4
LT		 4779 u16 current_speed;
4780 u8 current_duplex;
4781 int i, err;
4782
3310e248 4783 tg3_clear_mac_status(tp);
1da177e4 4784
8ef21428
MC		 4785 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4786 tw32_f(MAC_MI_MODE,
4787 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4788 udelay(80);
4789 }
1da177e4 4790
b4bd2929 4791 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
1da177e4
LT		 4792
4793 /* Some third-party PHYs need to be reset on link going
4794 * down.
4795 */
4153577a
JP		 4796 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4797 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4798 tg3_asic_rev(tp) == ASIC_REV_5705) &&
f4a46d1f 4799 tp->link_up) {
1da177e4
LT		 4800 tg3_readphy(tp, MII_BMSR, &bmsr);
4801 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4802 !(bmsr & BMSR_LSTATUS))
953c96e0 4803 force_reset = true;
1da177e4
LT		 4804 }
4805 if (force_reset)
4806 tg3_phy_reset(tp);
4807
79eb6904 4808 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 4809 tg3_readphy(tp, MII_BMSR, &bmsr);
4810 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
63c3a66f 4811 !tg3_flag(tp, INIT_COMPLETE))
1da177e4
LT		 4812 bmsr = 0;
4813
4814 if (!(bmsr & BMSR_LSTATUS)) {
4815 err = tg3_init_5401phy_dsp(tp);
4816 if (err)
4817 return err;
4818
4819 tg3_readphy(tp, MII_BMSR, &bmsr);
4820 for (i = 0; i < 1000; i++) {
4821 udelay(10);
4822 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4823 (bmsr & BMSR_LSTATUS)) {
4824 udelay(40);
4825 break;
4826 }
4827 }
4828
79eb6904
MC		 4829 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4830 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 4831 !(bmsr & BMSR_LSTATUS) &&
4832 tp->link_config.active_speed == SPEED_1000) {
4833 err = tg3_phy_reset(tp);
4834 if (!err)
4835 err = tg3_init_5401phy_dsp(tp);
4836 if (err)
4837 return err;
4838 }
4839 }
4153577a
JP		 4840 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4841 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
1da177e4
LT		 4842 /* 5701 {A0,B0} CRC bug workaround */
4843 tg3_writephy(tp, 0x15, 0x0a75);
f08aa1a8
MC		 4844 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4845 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4846 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
1da177e4
LT		 4847 }
4848
4849 /* Clear pending interrupts... */
f833c4c1
MC		 4850 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4851 tg3_readphy(tp, MII_TG3_ISTAT, &val);
1da177e4 4852
f07e9af3 4853 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
1da177e4 4854 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
f07e9af3 4855 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
1da177e4
LT		 4856 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4857
4153577a
JP		 4858 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4859 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4860 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4861 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4862 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4863 else
4864 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4865 }
4866
953c96e0 4867 current_link_up = false;
e740522e
MC		 4868 current_speed = SPEED_UNKNOWN;
4869 current_duplex = DUPLEX_UNKNOWN;
e348c5e7 4870 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
859edb26 4871 tp->link_config.rmt_adv = 0;
1da177e4 4872
f07e9af3 4873 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
15ee95c3
MC		 4874 err = tg3_phy_auxctl_read(tp,
4875 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4876 &val);
4877 if (!err && !(val & (1 << 10))) {
b4bd2929
MC		 4878 tg3_phy_auxctl_write(tp,
4879 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4880 val | (1 << 10));
1da177e4
LT		 4881 goto relink;
4882 }
4883 }
4884
4885 bmsr = 0;
4886 for (i = 0; i < 100; i++) {
4887 tg3_readphy(tp, MII_BMSR, &bmsr);
4888 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4889 (bmsr & BMSR_LSTATUS))
4890 break;
4891 udelay(40);
4892 }
4893
4894 if (bmsr & BMSR_LSTATUS) {
4895 u32 aux_stat, bmcr;
4896
4897 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4898 for (i = 0; i < 2000; i++) {
4899 udelay(10);
4900 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4901 aux_stat)
4902 break;
4903 }
4904
4905 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4906 &current_speed,
4907 &current_duplex);
4908
4909 bmcr = 0;
4910 for (i = 0; i < 200; i++) {
4911 tg3_readphy(tp, MII_BMCR, &bmcr);
4912 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4913 continue;
4914 if (bmcr && bmcr != 0x7fff)
4915 break;
4916 udelay(10);
4917 }
4918
ef167e27
MC		 4919 lcl_adv = 0;
4920 rmt_adv = 0;
1da177e4 4921
ef167e27
MC		 4922 tp->link_config.active_speed = current_speed;
4923 tp->link_config.active_duplex = current_duplex;
4924
4925 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
ed1ff5c3
NS		 4926 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4927
ef167e27 4928 if ((bmcr & BMCR_ANENABLE) &&
ed1ff5c3 4929 eee_config_ok &&
e2bf73e7 4930 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
859edb26 4931 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
953c96e0 4932 current_link_up = true;
ed1ff5c3
NS		 4933
4934 /* EEE settings changes take effect only after a phy
4935 * reset. If we have skipped a reset due to Link Flap
4936 * Avoidance being enabled, do it now.
4937 */
4938 if (!eee_config_ok &&
4939 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
5b6c273a
NS		 4940 !force_reset) {
4941 tg3_setup_eee(tp);
ed1ff5c3 4942 tg3_phy_reset(tp);
5b6c273a 4943 }
1da177e4
LT		 4944 } else {
4945 if (!(bmcr & BMCR_ANENABLE) &&
4946 tp->link_config.speed == current_speed &&
f0fcd7a9 4947 tp->link_config.duplex == current_duplex) {
953c96e0 4948 current_link_up = true;
1da177e4
LT		 4949 }
4950 }
4951
953c96e0 4952 if (current_link_up &&
e348c5e7
MC		 4953 tp->link_config.active_duplex == DUPLEX_FULL) {
4954 u32 reg, bit;
4955
4956 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4957 reg = MII_TG3_FET_GEN_STAT;
4958 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4959 } else {
4960 reg = MII_TG3_EXT_STAT;
4961 bit = MII_TG3_EXT_STAT_MDIX;
4962 }
4963
4964 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4965 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4966
ef167e27 4967 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
e348c5e7 4968 }
1da177e4
LT		 4969 }
4970
1da177e4 4971relink:
953c96e0 4972 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
1da177e4
LT		 4973 tg3_phy_copper_begin(tp);
4974
7e6c63f0 4975 if (tg3_flag(tp, ROBOSWITCH)) {
953c96e0 4976 current_link_up = true;
7e6c63f0
HM		 4977 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4978 current_speed = SPEED_1000;
4979 current_duplex = DUPLEX_FULL;
4980 tp->link_config.active_speed = current_speed;
4981 tp->link_config.active_duplex = current_duplex;
4982 }
4983
f833c4c1 4984 tg3_readphy(tp, MII_BMSR, &bmsr);
06c03c02
MB		 4985 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4986 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
953c96e0 4987 current_link_up = true;
1da177e4
LT		 4988 }
4989
4990 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
953c96e0 4991 if (current_link_up) {
1da177e4
LT		 4992 if (tp->link_config.active_speed == SPEED_100 ||
4993 tp->link_config.active_speed == SPEED_10)
4994 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4995 else
4996 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
f07e9af3 4997 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7f97a4bd
MC		 4998 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4999 else
1da177e4
LT		 5000 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5001
7e6c63f0
HM		 5002 /* In order for the 5750 core in BCM4785 chip to work properly
5003 * in RGMII mode, the Led Control Register must be set up.
5004 */
5005 if (tg3_flag(tp, RGMII_MODE)) {
5006 u32 led_ctrl = tr32(MAC_LED_CTRL);
5007 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5008
5009 if (tp->link_config.active_speed == SPEED_10)
5010 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5011 else if (tp->link_config.active_speed == SPEED_100)
5012 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5013 LED_CTRL_100MBPS_ON);
5014 else if (tp->link_config.active_speed == SPEED_1000)
5015 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5016 LED_CTRL_1000MBPS_ON);
5017
5018 tw32(MAC_LED_CTRL, led_ctrl);
5019 udelay(40);
5020 }
5021
1da177e4
LT		 5022 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5023 if (tp->link_config.active_duplex == DUPLEX_HALF)
5024 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5025
4153577a 5026 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
953c96e0 5027 if (current_link_up &&
e8f3f6ca 5028 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 5029 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 5030 else
5031 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 5032 }
5033
5034 /* ??? Without this setting Netgear GA302T PHY does not
5035 * ??? send/receive packets...
5036 */
79eb6904 5037 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4153577a 5038 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
1da177e4
LT		 5039 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5040 tw32_f(MAC_MI_MODE, tp->mi_mode);
5041 udelay(80);
5042 }
5043
5044 tw32_f(MAC_MODE, tp->mac_mode);
5045 udelay(40);
5046
52b02d04
MC		 5047 tg3_phy_eee_adjust(tp, current_link_up);
5048
63c3a66f 5049 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 5050 /* Polled via timer. */
5051 tw32_f(MAC_EVENT, 0);
5052 } else {
5053 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5054 }
5055 udelay(40);
5056
4153577a 5057 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
953c96e0 5058 current_link_up &&
1da177e4 5059 tp->link_config.active_speed == SPEED_1000 &&
63c3a66f 5060 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
1da177e4
LT		 5061 udelay(120);
5062 tw32_f(MAC_STATUS,
5063 (MAC_STATUS_SYNC_CHANGED |
5064 MAC_STATUS_CFG_CHANGED));
5065 udelay(40);
5066 tg3_write_mem(tp,
5067 NIC_SRAM_FIRMWARE_MBOX,
5068 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5069 }
5070
5e7dfd0f 5071 /* Prevent send BD corruption. */
63c3a66f 5072 if (tg3_flag(tp, CLKREQ_BUG)) {
5e7dfd0f
MC		 5073 if (tp->link_config.active_speed == SPEED_100 ||
5074 tp->link_config.active_speed == SPEED_10)
0f49bfbd
JL		 5075 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5076 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 5077 else
0f49bfbd
JL		 5078 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5079 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f
MC		 5080 }
5081
f4a46d1f 5082 tg3_test_and_report_link_chg(tp, current_link_up);
1da177e4
LT		 5083
5084 return 0;
5085}
5086
5087struct tg3_fiber_aneginfo {
5088 int state;
5089#define ANEG_STATE_UNKNOWN 0
5090#define ANEG_STATE_AN_ENABLE 1
5091#define ANEG_STATE_RESTART_INIT 2
5092#define ANEG_STATE_RESTART 3
5093#define ANEG_STATE_DISABLE_LINK_OK 4
5094#define ANEG_STATE_ABILITY_DETECT_INIT 5
5095#define ANEG_STATE_ABILITY_DETECT 6
5096#define ANEG_STATE_ACK_DETECT_INIT 7
5097#define ANEG_STATE_ACK_DETECT 8
5098#define ANEG_STATE_COMPLETE_ACK_INIT 9
5099#define ANEG_STATE_COMPLETE_ACK 10
5100#define ANEG_STATE_IDLE_DETECT_INIT 11
5101#define ANEG_STATE_IDLE_DETECT 12
5102#define ANEG_STATE_LINK_OK 13
5103#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5104#define ANEG_STATE_NEXT_PAGE_WAIT 15
5105
5106 u32 flags;
5107#define MR_AN_ENABLE 0x00000001
5108#define MR_RESTART_AN 0x00000002
5109#define MR_AN_COMPLETE 0x00000004
5110#define MR_PAGE_RX 0x00000008
5111#define MR_NP_LOADED 0x00000010
5112#define MR_TOGGLE_TX 0x00000020
5113#define MR_LP_ADV_FULL_DUPLEX 0x00000040
5114#define MR_LP_ADV_HALF_DUPLEX 0x00000080
5115#define MR_LP_ADV_SYM_PAUSE 0x00000100
5116#define MR_LP_ADV_ASYM_PAUSE 0x00000200
5117#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5118#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5119#define MR_LP_ADV_NEXT_PAGE 0x00001000
5120#define MR_TOGGLE_RX 0x00002000
5121#define MR_NP_RX 0x00004000
5122
5123#define MR_LINK_OK 0x80000000
5124
5125 unsigned long link_time, cur_time;
5126
5127 u32 ability_match_cfg;
5128 int ability_match_count;
5129
5130 char ability_match, idle_match, ack_match;
5131
5132 u32 txconfig, rxconfig;
5133#define ANEG_CFG_NP 0x00000080
5134#define ANEG_CFG_ACK 0x00000040
5135#define ANEG_CFG_RF2 0x00000020
5136#define ANEG_CFG_RF1 0x00000010
5137#define ANEG_CFG_PS2 0x00000001
5138#define ANEG_CFG_PS1 0x00008000
5139#define ANEG_CFG_HD 0x00004000
5140#define ANEG_CFG_FD 0x00002000
5141#define ANEG_CFG_INVAL 0x00001f06
5142
5143};
5144#define ANEG_OK 0
5145#define ANEG_DONE 1
5146#define ANEG_TIMER_ENAB 2
5147#define ANEG_FAILED -1
5148
5149#define ANEG_STATE_SETTLE_TIME 10000
5150
5151static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5152 struct tg3_fiber_aneginfo *ap)
5153{
5be73b47 5154 u16 flowctrl;
1da177e4
LT		 5155 unsigned long delta;
5156 u32 rx_cfg_reg;
5157 int ret;
5158
5159 if (ap->state == ANEG_STATE_UNKNOWN) {
5160 ap->rxconfig = 0;
5161 ap->link_time = 0;
5162 ap->cur_time = 0;
5163 ap->ability_match_cfg = 0;
5164 ap->ability_match_count = 0;
5165 ap->ability_match = 0;
5166 ap->idle_match = 0;
5167 ap->ack_match = 0;
5168 }
5169 ap->cur_time++;
5170
5171 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5172 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5173
5174 if (rx_cfg_reg != ap->ability_match_cfg) {
5175 ap->ability_match_cfg = rx_cfg_reg;
5176 ap->ability_match = 0;
5177 ap->ability_match_count = 0;
5178 } else {
5179 if (++ap->ability_match_count > 1) {
5180 ap->ability_match = 1;
5181 ap->ability_match_cfg = rx_cfg_reg;
5182 }
5183 }
5184 if (rx_cfg_reg & ANEG_CFG_ACK)
5185 ap->ack_match = 1;
5186 else
5187 ap->ack_match = 0;
5188
5189 ap->idle_match = 0;
5190 } else {
5191 ap->idle_match = 1;
5192 ap->ability_match_cfg = 0;
5193 ap->ability_match_count = 0;
5194 ap->ability_match = 0;
5195 ap->ack_match = 0;
5196
5197 rx_cfg_reg = 0;
5198 }
5199
5200 ap->rxconfig = rx_cfg_reg;
5201 ret = ANEG_OK;
5202
33f401ae 5203 switch (ap->state) {
1da177e4
LT		 5204 case ANEG_STATE_UNKNOWN:
5205 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5206 ap->state = ANEG_STATE_AN_ENABLE;
5207
5208 /* fallthru */
5209 case ANEG_STATE_AN_ENABLE:
5210 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5211 if (ap->flags & MR_AN_ENABLE) {
5212 ap->link_time = 0;
5213 ap->cur_time = 0;
5214 ap->ability_match_cfg = 0;
5215 ap->ability_match_count = 0;
5216 ap->ability_match = 0;
5217 ap->idle_match = 0;
5218 ap->ack_match = 0;
5219
5220 ap->state = ANEG_STATE_RESTART_INIT;
5221 } else {
5222 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5223 }
5224 break;
5225
5226 case ANEG_STATE_RESTART_INIT:
5227 ap->link_time = ap->cur_time;
5228 ap->flags &= ~(MR_NP_LOADED);
5229 ap->txconfig = 0;
5230 tw32(MAC_TX_AUTO_NEG, 0);
5231 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5232 tw32_f(MAC_MODE, tp->mac_mode);
5233 udelay(40);
5234
5235 ret = ANEG_TIMER_ENAB;
5236 ap->state = ANEG_STATE_RESTART;
5237
5238 /* fallthru */
5239 case ANEG_STATE_RESTART:
5240 delta = ap->cur_time - ap->link_time;
859a5887 5241 if (delta > ANEG_STATE_SETTLE_TIME)
1da177e4 5242 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
859a5887 5243 else
1da177e4 5244 ret = ANEG_TIMER_ENAB;
1da177e4
LT		 5245 break;
5246
5247 case ANEG_STATE_DISABLE_LINK_OK:
5248 ret = ANEG_DONE;
5249 break;
5250
5251 case ANEG_STATE_ABILITY_DETECT_INIT:
5252 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 5253 ap->txconfig = ANEG_CFG_FD;
5254 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5255 if (flowctrl & ADVERTISE_1000XPAUSE)
5256 ap->txconfig |= ANEG_CFG_PS1;
5257 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5258 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 5259 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5260 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5261 tw32_f(MAC_MODE, tp->mac_mode);
5262 udelay(40);
5263
5264 ap->state = ANEG_STATE_ABILITY_DETECT;
5265 break;
5266
5267 case ANEG_STATE_ABILITY_DETECT:
859a5887 5268 if (ap->ability_match != 0 && ap->rxconfig != 0)
1da177e4 5269 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1da177e4
LT		 5270 break;
5271
5272 case ANEG_STATE_ACK_DETECT_INIT:
5273 ap->txconfig |= ANEG_CFG_ACK;
5274 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5275 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5276 tw32_f(MAC_MODE, tp->mac_mode);
5277 udelay(40);
5278
5279 ap->state = ANEG_STATE_ACK_DETECT;
5280
5281 /* fallthru */
5282 case ANEG_STATE_ACK_DETECT:
5283 if (ap->ack_match != 0) {
5284 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5285 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5286 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5287 } else {
5288 ap->state = ANEG_STATE_AN_ENABLE;
5289 }
5290 } else if (ap->ability_match != 0 &&
5291 ap->rxconfig == 0) {
5292 ap->state = ANEG_STATE_AN_ENABLE;
5293 }
5294 break;
5295
5296 case ANEG_STATE_COMPLETE_ACK_INIT:
5297 if (ap->rxconfig & ANEG_CFG_INVAL) {
5298 ret = ANEG_FAILED;
5299 break;
5300 }
5301 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5302 MR_LP_ADV_HALF_DUPLEX |
5303 MR_LP_ADV_SYM_PAUSE |
5304 MR_LP_ADV_ASYM_PAUSE |
5305 MR_LP_ADV_REMOTE_FAULT1 |
5306 MR_LP_ADV_REMOTE_FAULT2 |
5307 MR_LP_ADV_NEXT_PAGE |
5308 MR_TOGGLE_RX |
5309 MR_NP_RX);
5310 if (ap->rxconfig & ANEG_CFG_FD)
5311 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5312 if (ap->rxconfig & ANEG_CFG_HD)
5313 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5314 if (ap->rxconfig & ANEG_CFG_PS1)
5315 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5316 if (ap->rxconfig & ANEG_CFG_PS2)
5317 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5318 if (ap->rxconfig & ANEG_CFG_RF1)
5319 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5320 if (ap->rxconfig & ANEG_CFG_RF2)
5321 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5322 if (ap->rxconfig & ANEG_CFG_NP)
5323 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5324
5325 ap->link_time = ap->cur_time;
5326
5327 ap->flags ^= (MR_TOGGLE_TX);
5328 if (ap->rxconfig & 0x0008)
5329 ap->flags |= MR_TOGGLE_RX;
5330 if (ap->rxconfig & ANEG_CFG_NP)
5331 ap->flags |= MR_NP_RX;
5332 ap->flags |= MR_PAGE_RX;
5333
5334 ap->state = ANEG_STATE_COMPLETE_ACK;
5335 ret = ANEG_TIMER_ENAB;
5336 break;
5337
5338 case ANEG_STATE_COMPLETE_ACK:
5339 if (ap->ability_match != 0 &&
5340 ap->rxconfig == 0) {
5341 ap->state = ANEG_STATE_AN_ENABLE;
5342 break;
5343 }
5344 delta = ap->cur_time - ap->link_time;
5345 if (delta > ANEG_STATE_SETTLE_TIME) {
5346 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5347 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5348 } else {
5349 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5350 !(ap->flags & MR_NP_RX)) {
5351 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5352 } else {
5353 ret = ANEG_FAILED;
5354 }
5355 }
5356 }
5357 break;
5358
5359 case ANEG_STATE_IDLE_DETECT_INIT:
5360 ap->link_time = ap->cur_time;
5361 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5362 tw32_f(MAC_MODE, tp->mac_mode);
5363 udelay(40);
5364
5365 ap->state = ANEG_STATE_IDLE_DETECT;
5366 ret = ANEG_TIMER_ENAB;
5367 break;
5368
5369 case ANEG_STATE_IDLE_DETECT:
5370 if (ap->ability_match != 0 &&
5371 ap->rxconfig == 0) {
5372 ap->state = ANEG_STATE_AN_ENABLE;
5373 break;
5374 }
5375 delta = ap->cur_time - ap->link_time;
5376 if (delta > ANEG_STATE_SETTLE_TIME) {
5377 /* XXX another gem from the Broadcom driver :( */
5378 ap->state = ANEG_STATE_LINK_OK;
5379 }
5380 break;
5381
5382 case ANEG_STATE_LINK_OK:
5383 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5384 ret = ANEG_DONE;
5385 break;
5386
5387 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5388 /* ??? unimplemented */
5389 break;
5390
5391 case ANEG_STATE_NEXT_PAGE_WAIT:
5392 /* ??? unimplemented */
5393 break;
5394
5395 default:
5396 ret = ANEG_FAILED;
5397 break;
855e1111 5398 }
1da177e4
LT		 5399
5400 return ret;
5401}
5402
5be73b47 5403static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 5404{
5405 int res = 0;
5406 struct tg3_fiber_aneginfo aninfo;
5407 int status = ANEG_FAILED;
5408 unsigned int tick;
5409 u32 tmp;
5410
5411 tw32_f(MAC_TX_AUTO_NEG, 0);
5412
5413 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5414 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5415 udelay(40);
5416
5417 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5418 udelay(40);
5419
5420 memset(&aninfo, 0, sizeof(aninfo));
5421 aninfo.flags |= MR_AN_ENABLE;
5422 aninfo.state = ANEG_STATE_UNKNOWN;
5423 aninfo.cur_time = 0;
5424 tick = 0;
5425 while (++tick < 195000) {
5426 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5427 if (status == ANEG_DONE || status == ANEG_FAILED)
5428 break;
5429
5430 udelay(1);
5431 }
5432
5433 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5434 tw32_f(MAC_MODE, tp->mac_mode);
5435 udelay(40);
5436
5be73b47
MC		 5437 *txflags = aninfo.txconfig;
5438 *rxflags = aninfo.flags;
1da177e4
LT		 5439
5440 if (status == ANEG_DONE &&
5441 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5442 MR_LP_ADV_FULL_DUPLEX)))
5443 res = 1;
5444
5445 return res;
5446}
5447
5448static void tg3_init_bcm8002(struct tg3 *tp)
5449{
5450 u32 mac_status = tr32(MAC_STATUS);
5451 int i;
5452
5453 /* Reset when initting first time or we have a link. */
63c3a66f 5454 if (tg3_flag(tp, INIT_COMPLETE) &&
1da177e4
LT		 5455 !(mac_status & MAC_STATUS_PCS_SYNCED))
5456 return;
5457
5458 /* Set PLL lock range. */
5459 tg3_writephy(tp, 0x16, 0x8007);
5460
5461 /* SW reset */
5462 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5463
5464 /* Wait for reset to complete. */
5465 /* XXX schedule_timeout() ... */
5466 for (i = 0; i < 500; i++)
5467 udelay(10);
5468
5469 /* Config mode; select PMA/Ch 1 regs. */
5470 tg3_writephy(tp, 0x10, 0x8411);
5471
5472 /* Enable auto-lock and comdet, select txclk for tx. */
5473 tg3_writephy(tp, 0x11, 0x0a10);
5474
5475 tg3_writephy(tp, 0x18, 0x00a0);
5476 tg3_writephy(tp, 0x16, 0x41ff);
5477
5478 /* Assert and deassert POR. */
5479 tg3_writephy(tp, 0x13, 0x0400);
5480 udelay(40);
5481 tg3_writephy(tp, 0x13, 0x0000);
5482
5483 tg3_writephy(tp, 0x11, 0x0a50);
5484 udelay(40);
5485 tg3_writephy(tp, 0x11, 0x0a10);
5486
5487 /* Wait for signal to stabilize */
5488 /* XXX schedule_timeout() ... */
5489 for (i = 0; i < 15000; i++)
5490 udelay(10);
5491
5492 /* Deselect the channel register so we can read the PHYID
5493 * later.
5494 */
5495 tg3_writephy(tp, 0x10, 0x8011);
5496}
5497
953c96e0 5498static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
1da177e4 5499{
82cd3d11 5500 u16 flowctrl;
953c96e0 5501 bool current_link_up;
1da177e4
LT		 5502 u32 sg_dig_ctrl, sg_dig_status;
5503 u32 serdes_cfg, expected_sg_dig_ctrl;
5504 int workaround, port_a;
1da177e4
LT		 5505
5506 serdes_cfg = 0;
5507 expected_sg_dig_ctrl = 0;
5508 workaround = 0;
5509 port_a = 1;
953c96e0 5510 current_link_up = false;
1da177e4 5511
4153577a
JP		 5512 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5513 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
1da177e4
LT		 5514 workaround = 1;
5515 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5516 port_a = 0;
5517
5518 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5519 /* preserve bits 20-23 for voltage regulator */
5520 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5521 }
5522
5523 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5524
5525 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 5526 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 5527 if (workaround) {
5528 u32 val = serdes_cfg;
5529
5530 if (port_a)
5531 val |= 0xc010000;
5532 else
5533 val |= 0x4010000;
5534 tw32_f(MAC_SERDES_CFG, val);
5535 }
c98f6e3b
MC		 5536
5537 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5538 }
5539 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5540 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5541 current_link_up = true;
1da177e4
LT		 5542 }
5543 goto out;
5544 }
5545
5546 /* Want auto-negotiation. */
c98f6e3b 5547 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 5548
82cd3d11
MC		 5549 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5550 if (flowctrl & ADVERTISE_1000XPAUSE)
5551 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5552 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5553 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 5554
5555 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
f07e9af3 5556 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3d3ebe74
MC		 5557 tp->serdes_counter &&
5558 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5559 MAC_STATUS_RCVD_CFG)) ==
5560 MAC_STATUS_PCS_SYNCED)) {
5561 tp->serdes_counter--;
953c96e0 5562 current_link_up = true;
3d3ebe74
MC		 5563 goto out;
5564 }
5565restart_autoneg:
1da177e4
LT		 5566 if (workaround)
5567 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 5568 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 5569 udelay(5);
5570 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5571
3d3ebe74 5572 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5573 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5574 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5575 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 5576 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 5577 mac_status = tr32(MAC_STATUS);
5578
c98f6e3b 5579 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 5580 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 5581 u32 local_adv = 0, remote_adv = 0;
5582
5583 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5584 local_adv |= ADVERTISE_1000XPAUSE;
5585 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5586 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 5587
c98f6e3b 5588 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 5589 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 5590 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 5591 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5592
859edb26
MC		 5593 tp->link_config.rmt_adv =
5594 mii_adv_to_ethtool_adv_x(remote_adv);
5595
1da177e4 5596 tg3_setup_flow_control(tp, local_adv, remote_adv);
953c96e0 5597 current_link_up = true;
3d3ebe74 5598 tp->serdes_counter = 0;
f07e9af3 5599 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c98f6e3b 5600 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 5601 if (tp->serdes_counter)
5602 tp->serdes_counter--;
1da177e4
LT		 5603 else {
5604 if (workaround) {
5605 u32 val = serdes_cfg;
5606
5607 if (port_a)
5608 val |= 0xc010000;
5609 else
5610 val |= 0x4010000;
5611
5612 tw32_f(MAC_SERDES_CFG, val);
5613 }
5614
c98f6e3b 5615 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5616 udelay(40);
5617
5618 /* Link parallel detection - link is up */
5619 /* only if we have PCS_SYNC and not */
5620 /* receiving config code words */
5621 mac_status = tr32(MAC_STATUS);
5622 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5623 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5624 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5625 current_link_up = true;
f07e9af3
MC		 5626 tp->phy_flags |=
5627 TG3_PHYFLG_PARALLEL_DETECT;
3d3ebe74
MC		 5628 tp->serdes_counter =
5629 SERDES_PARALLEL_DET_TIMEOUT;
5630 } else
5631 goto restart_autoneg;
1da177e4
LT		 5632 }
5633 }
3d3ebe74
MC		 5634 } else {
5635 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5636 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5637 }
5638
5639out:
5640 return current_link_up;
5641}
5642
953c96e0 5643static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
1da177e4 5644{
953c96e0 5645 bool current_link_up = false;
1da177e4 5646
5cf64b8a 5647 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 5648 goto out;
1da177e4
LT		 5649
5650 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 5651 u32 txflags, rxflags;
1da177e4 5652 int i;
6aa20a22 5653
5be73b47
MC		 5654 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5655 u32 local_adv = 0, remote_adv = 0;
1da177e4 5656
5be73b47
MC		 5657 if (txflags & ANEG_CFG_PS1)
5658 local_adv |= ADVERTISE_1000XPAUSE;
5659 if (txflags & ANEG_CFG_PS2)
5660 local_adv |= ADVERTISE_1000XPSE_ASYM;
5661
5662 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5663 remote_adv |= LPA_1000XPAUSE;
5664 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5665 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5666
859edb26
MC		 5667 tp->link_config.rmt_adv =
5668 mii_adv_to_ethtool_adv_x(remote_adv);
5669
1da177e4
LT		 5670 tg3_setup_flow_control(tp, local_adv, remote_adv);
5671
953c96e0 5672 current_link_up = true;
1da177e4
LT		 5673 }
5674 for (i = 0; i < 30; i++) {
5675 udelay(20);
5676 tw32_f(MAC_STATUS,
5677 (MAC_STATUS_SYNC_CHANGED |
5678 MAC_STATUS_CFG_CHANGED));
5679 udelay(40);
5680 if ((tr32(MAC_STATUS) &
5681 (MAC_STATUS_SYNC_CHANGED |
5682 MAC_STATUS_CFG_CHANGED)) == 0)
5683 break;
5684 }
5685
5686 mac_status = tr32(MAC_STATUS);
953c96e0 5687 if (!current_link_up &&
1da177e4
LT		 5688 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5689 !(mac_status & MAC_STATUS_RCVD_CFG))
953c96e0 5690 current_link_up = true;
1da177e4 5691 } else {
5be73b47
MC		 5692 tg3_setup_flow_control(tp, 0, 0);
5693
1da177e4 5694 /* Forcing 1000FD link up. */
953c96e0 5695 current_link_up = true;
1da177e4
LT		 5696
5697 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5698 udelay(40);
e8f3f6ca
MC		 5699
5700 tw32_f(MAC_MODE, tp->mac_mode);
5701 udelay(40);
1da177e4
LT		 5702 }
5703
5704out:
5705 return current_link_up;
5706}
5707
953c96e0 5708static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
1da177e4
LT		 5709{
5710 u32 orig_pause_cfg;
5711 u16 orig_active_speed;
5712 u8 orig_active_duplex;
5713 u32 mac_status;
953c96e0 5714 bool current_link_up;
1da177e4
LT		 5715 int i;
5716
8d018621 5717 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5718 orig_active_speed = tp->link_config.active_speed;
5719 orig_active_duplex = tp->link_config.active_duplex;
5720
63c3a66f 5721 if (!tg3_flag(tp, HW_AUTONEG) &&
f4a46d1f 5722 tp->link_up &&
63c3a66f 5723 tg3_flag(tp, INIT_COMPLETE)) {
1da177e4
LT		 5724 mac_status = tr32(MAC_STATUS);
5725 mac_status &= (MAC_STATUS_PCS_SYNCED |
5726 MAC_STATUS_SIGNAL_DET |
5727 MAC_STATUS_CFG_CHANGED |
5728 MAC_STATUS_RCVD_CFG);
5729 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5730 MAC_STATUS_SIGNAL_DET)) {
5731 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5732 MAC_STATUS_CFG_CHANGED));
5733 return 0;
5734 }
5735 }
5736
5737 tw32_f(MAC_TX_AUTO_NEG, 0);
5738
5739 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5740 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5741 tw32_f(MAC_MODE, tp->mac_mode);
5742 udelay(40);
5743
79eb6904 5744 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 5745 tg3_init_bcm8002(tp);
5746
5747 /* Enable link change event even when serdes polling. */
5748 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5749 udelay(40);
5750
953c96e0 5751 current_link_up = false;
859edb26 5752 tp->link_config.rmt_adv = 0;
1da177e4
LT		 5753 mac_status = tr32(MAC_STATUS);
5754
63c3a66f 5755 if (tg3_flag(tp, HW_AUTONEG))
1da177e4
LT		 5756 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5757 else
5758 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5759
898a56f8 5760 tp->napi[0].hw_status->status =
1da177e4 5761 (SD_STATUS_UPDATED |
898a56f8 5762 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 5763
5764 for (i = 0; i < 100; i++) {
5765 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5766 MAC_STATUS_CFG_CHANGED));
5767 udelay(5);
5768 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 5769 MAC_STATUS_CFG_CHANGED |
5770 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 5771 break;
5772 }
5773
5774 mac_status = tr32(MAC_STATUS);
5775 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
953c96e0 5776 current_link_up = false;
3d3ebe74
MC		 5777 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5778 tp->serdes_counter == 0) {
1da177e4
LT		 5779 tw32_f(MAC_MODE, (tp->mac_mode |
5780 MAC_MODE_SEND_CONFIGS));
5781 udelay(1);
5782 tw32_f(MAC_MODE, tp->mac_mode);
5783 }
5784 }
5785
953c96e0 5786 if (current_link_up) {
1da177e4
LT		 5787 tp->link_config.active_speed = SPEED_1000;
5788 tp->link_config.active_duplex = DUPLEX_FULL;
5789 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5790 LED_CTRL_LNKLED_OVERRIDE |
5791 LED_CTRL_1000MBPS_ON));
5792 } else {
e740522e
MC		 5793 tp->link_config.active_speed = SPEED_UNKNOWN;
5794 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 5795 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5796 LED_CTRL_LNKLED_OVERRIDE |
5797 LED_CTRL_TRAFFIC_OVERRIDE));
5798 }
5799
f4a46d1f 5800 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
8d018621 5801 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5802 if (orig_pause_cfg != now_pause_cfg ||
5803 orig_active_speed != tp->link_config.active_speed ||
5804 orig_active_duplex != tp->link_config.active_duplex)
5805 tg3_link_report(tp);
5806 }
5807
5808 return 0;
5809}
5810
953c96e0 5811static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
747e8f8b 5812{
953c96e0 5813 int err = 0;
747e8f8b 5814 u32 bmsr, bmcr;
85730a63
MC		 5815 u16 current_speed = SPEED_UNKNOWN;
5816 u8 current_duplex = DUPLEX_UNKNOWN;
953c96e0 5817 bool current_link_up = false;
85730a63
MC		 5818 u32 local_adv, remote_adv, sgsr;
5819
5820 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5821 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5822 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5823 (sgsr & SERDES_TG3_SGMII_MODE)) {
5824
5825 if (force_reset)
5826 tg3_phy_reset(tp);
5827
5828 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5829
5830 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5831 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5832 } else {
953c96e0 5833 current_link_up = true;
85730a63
MC		 5834 if (sgsr & SERDES_TG3_SPEED_1000) {
5835 current_speed = SPEED_1000;
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5837 } else if (sgsr & SERDES_TG3_SPEED_100) {
5838 current_speed = SPEED_100;
5839 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5840 } else {
5841 current_speed = SPEED_10;
5842 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5843 }
5844
5845 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5846 current_duplex = DUPLEX_FULL;
5847 else
5848 current_duplex = DUPLEX_HALF;
5849 }
5850
5851 tw32_f(MAC_MODE, tp->mac_mode);
5852 udelay(40);
5853
5854 tg3_clear_mac_status(tp);
5855
5856 goto fiber_setup_done;
5857 }
747e8f8b
MC		 5858
5859 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5860 tw32_f(MAC_MODE, tp->mac_mode);
5861 udelay(40);
5862
3310e248 5863 tg3_clear_mac_status(tp);
747e8f8b
MC		 5864
5865 if (force_reset)
5866 tg3_phy_reset(tp);
5867
859edb26 5868 tp->link_config.rmt_adv = 0;
747e8f8b
MC		 5869
5870 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5871 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5872 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5873 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5874 bmsr |= BMSR_LSTATUS;
5875 else
5876 bmsr &= ~BMSR_LSTATUS;
5877 }
747e8f8b
MC		 5878
5879 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5880
5881 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
f07e9af3 5882 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 5883 /* do nothing, just check for link up at the end */
5884 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
28011cf1 5885 u32 adv, newadv;
747e8f8b
MC		 5886
5887 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
28011cf1
MC		 5888 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5889 ADVERTISE_1000XPAUSE |
5890 ADVERTISE_1000XPSE_ASYM |
5891 ADVERTISE_SLCT);
747e8f8b 5892
28011cf1 5893 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
37f07023 5894 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
747e8f8b 5895
28011cf1
MC		 5896 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5897 tg3_writephy(tp, MII_ADVERTISE, newadv);
747e8f8b
MC		 5898 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5899 tg3_writephy(tp, MII_BMCR, bmcr);
5900
5901 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 5902 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
f07e9af3 5903 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5904
5905 return err;
5906 }
5907 } else {
5908 u32 new_bmcr;
5909
5910 bmcr &= ~BMCR_SPEED1000;
5911 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5912
5913 if (tp->link_config.duplex == DUPLEX_FULL)
5914 new_bmcr |= BMCR_FULLDPLX;
5915
5916 if (new_bmcr != bmcr) {
5917 /* BMCR_SPEED1000 is a reserved bit that needs
5918 * to be set on write.
5919 */
5920 new_bmcr |= BMCR_SPEED1000;
5921
5922 /* Force a linkdown */
f4a46d1f 5923 if (tp->link_up) {
747e8f8b
MC		 5924 u32 adv;
5925
5926 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5927 adv &= ~(ADVERTISE_1000XFULL |
5928 ADVERTISE_1000XHALF |
5929 ADVERTISE_SLCT);
5930 tg3_writephy(tp, MII_ADVERTISE, adv);
5931 tg3_writephy(tp, MII_BMCR, bmcr |
5932 BMCR_ANRESTART |
5933 BMCR_ANENABLE);
5934 udelay(10);
f4a46d1f 5935 tg3_carrier_off(tp);
747e8f8b
MC		 5936 }
5937 tg3_writephy(tp, MII_BMCR, new_bmcr);
5938 bmcr = new_bmcr;
5939 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5940 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5941 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5942 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5943 bmsr |= BMSR_LSTATUS;
5944 else
5945 bmsr &= ~BMSR_LSTATUS;
5946 }
f07e9af3 5947 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5948 }
5949 }
5950
5951 if (bmsr & BMSR_LSTATUS) {
5952 current_speed = SPEED_1000;
953c96e0 5953 current_link_up = true;
747e8f8b
MC		 5954 if (bmcr & BMCR_FULLDPLX)
5955 current_duplex = DUPLEX_FULL;
5956 else
5957 current_duplex = DUPLEX_HALF;
5958
ef167e27
MC		 5959 local_adv = 0;
5960 remote_adv = 0;
5961
747e8f8b 5962 if (bmcr & BMCR_ANENABLE) {
ef167e27 5963 u32 common;
747e8f8b
MC		 5964
5965 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5966 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5967 common = local_adv & remote_adv;
5968 if (common & (ADVERTISE_1000XHALF |
5969 ADVERTISE_1000XFULL)) {
5970 if (common & ADVERTISE_1000XFULL)
5971 current_duplex = DUPLEX_FULL;
5972 else
5973 current_duplex = DUPLEX_HALF;
859edb26
MC		 5974
5975 tp->link_config.rmt_adv =
5976 mii_adv_to_ethtool_adv_x(remote_adv);
63c3a66f 5977 } else if (!tg3_flag(tp, 5780_CLASS)) {
57d8b880 5978 /* Link is up via parallel detect */
859a5887 5979 } else {
953c96e0 5980 current_link_up = false;
859a5887 5981 }
747e8f8b
MC		 5982 }
5983 }
5984
85730a63 5985fiber_setup_done:
953c96e0 5986 if (current_link_up && current_duplex == DUPLEX_FULL)
ef167e27
MC		 5987 tg3_setup_flow_control(tp, local_adv, remote_adv);
5988
747e8f8b
MC		 5989 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5990 if (tp->link_config.active_duplex == DUPLEX_HALF)
5991 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5992
5993 tw32_f(MAC_MODE, tp->mac_mode);
5994 udelay(40);
5995
5996 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5997
5998 tp->link_config.active_speed = current_speed;
5999 tp->link_config.active_duplex = current_duplex;
6000
f4a46d1f 6001 tg3_test_and_report_link_chg(tp, current_link_up);
747e8f8b
MC		 6002 return err;
6003}
6004
6005static void tg3_serdes_parallel_detect(struct tg3 *tp)
6006{
3d3ebe74 6007 if (tp->serdes_counter) {
747e8f8b 6008 /* Give autoneg time to complete. */
3d3ebe74 6009 tp->serdes_counter--;
747e8f8b
MC		 6010 return;
6011 }
c6cdf436 6012
f4a46d1f 6013 if (!tp->link_up &&
747e8f8b
MC		 6014 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6015 u32 bmcr;
6016
6017 tg3_readphy(tp, MII_BMCR, &bmcr);
6018 if (bmcr & BMCR_ANENABLE) {
6019 u32 phy1, phy2;
6020
6021 /* Select shadow register 0x1f */
f08aa1a8
MC		 6022 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6023 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
747e8f8b
MC		 6024
6025 /* Select expansion interrupt status register */
f08aa1a8
MC		 6026 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6027 MII_TG3_DSP_EXP1_INT_STAT);
6028 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6029 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6030
6031 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6032 /* We have signal detect and not receiving
6033 * config code words, link is up by parallel
6034 * detection.
6035 */
6036
6037 bmcr &= ~BMCR_ANENABLE;
6038 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6039 tg3_writephy(tp, MII_BMCR, bmcr);
f07e9af3 6040 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6041 }
6042 }
f4a46d1f 6043 } else if (tp->link_up &&
859a5887 6044 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
f07e9af3 6045 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 6046 u32 phy2;
6047
6048 /* Select expansion interrupt status register */
f08aa1a8
MC		 6049 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6050 MII_TG3_DSP_EXP1_INT_STAT);
6051 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6052 if (phy2 & 0x20) {
6053 u32 bmcr;
6054
6055 /* Config code words received, turn on autoneg. */
6056 tg3_readphy(tp, MII_BMCR, &bmcr);
6057 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6058
f07e9af3 6059 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6060
6061 }
6062 }
6063}
6064
953c96e0 6065static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
1da177e4 6066{
f2096f94 6067 u32 val;
1da177e4
LT		 6068 int err;
6069
f07e9af3 6070 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4 6071 err = tg3_setup_fiber_phy(tp, force_reset);
f07e9af3 6072 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
747e8f8b 6073 err = tg3_setup_fiber_mii_phy(tp, force_reset);
859a5887 6074 else
1da177e4 6075 err = tg3_setup_copper_phy(tp, force_reset);
1da177e4 6076
4153577a 6077 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
f2096f94 6078 u32 scale;
aa6c91fe
MC		 6079
6080 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6081 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6082 scale = 65;
6083 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6084 scale = 6;
6085 else
6086 scale = 12;
6087
6088 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6089 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6090 tw32(GRC_MISC_CFG, val);
6091 }
6092
f2096f94
MC		 6093 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6094 (6 << TX_LENGTHS_IPG_SHIFT);
4153577a
JP		 6095 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6096 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 6097 val |= tr32(MAC_TX_LENGTHS) &
6098 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6099 TX_LENGTHS_CNT_DWN_VAL_MSK);
6100
1da177e4
LT		 6101 if (tp->link_config.active_speed == SPEED_1000 &&
6102 tp->link_config.active_duplex == DUPLEX_HALF)
f2096f94
MC		 6103 tw32(MAC_TX_LENGTHS, val |
6104 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6105 else
f2096f94
MC		 6106 tw32(MAC_TX_LENGTHS, val |
6107 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6108
63c3a66f 6109 if (!tg3_flag(tp, 5705_PLUS)) {
f4a46d1f 6110 if (tp->link_up) {
1da177e4 6111 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 6112 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 6113 } else {
6114 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6115 }
6116 }
6117
63c3a66f 6118 if (tg3_flag(tp, ASPM_WORKAROUND)) {
f2096f94 6119 val = tr32(PCIE_PWR_MGMT_THRESH);
f4a46d1f 6120 if (!tp->link_up)
8ed5d97e
MC		 6121 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6122 tp->pwrmgmt_thresh;
6123 else
6124 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6125 tw32(PCIE_PWR_MGMT_THRESH, val);
6126 }
6127
1da177e4
LT		 6128 return err;
6129}
6130
7d41e49a
MC		 6131/* tp->lock must be held */
6132static u64 tg3_refclk_read(struct tg3 *tp)
6133{
6134 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6135 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6136}
6137
be947307
MC		 6138/* tp->lock must be held */
6139static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6140{
92e6457d
NS		 6141 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6142
6143 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
be947307
MC		 6144 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6145 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
92e6457d 6146 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
be947307
MC		 6147}
6148
7d41e49a
MC		 6149static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6150static inline void tg3_full_unlock(struct tg3 *tp);
6151static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6152{
6153 struct tg3 *tp = netdev_priv(dev);
6154
6155 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6156 SOF_TIMESTAMPING_RX_SOFTWARE |
f233a976
FL		 6157 SOF_TIMESTAMPING_SOFTWARE;
6158
6159 if (tg3_flag(tp, PTP_CAPABLE)) {
32e19272 6160 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
f233a976
FL		 6161 SOF_TIMESTAMPING_RX_HARDWARE |
6162 SOF_TIMESTAMPING_RAW_HARDWARE;
6163 }
7d41e49a
MC		 6164
6165 if (tp->ptp_clock)
6166 info->phc_index = ptp_clock_index(tp->ptp_clock);
6167 else
6168 info->phc_index = -1;
6169
6170 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6171
6172 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6173 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6174 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6175 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6176 return 0;
6177}
6178
6179static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6180{
6181 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6182 bool neg_adj = false;
6183 u32 correction = 0;
6184
6185 if (ppb < 0) {
6186 neg_adj = true;
6187 ppb = -ppb;
6188 }
6189
6190 /* Frequency adjustment is performed using hardware with a 24 bit
6191 * accumulator and a programmable correction value. On each clk, the
6192 * correction value gets added to the accumulator and when it
6193 * overflows, the time counter is incremented/decremented.
6194 *
6195 * So conversion from ppb to correction value is
6196 * ppb * (1 << 24) / 1000000000
6197 */
6198 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6199 TG3_EAV_REF_CLK_CORRECT_MASK;
6200
6201 tg3_full_lock(tp, 0);
6202
6203 if (correction)
6204 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6205 TG3_EAV_REF_CLK_CORRECT_EN |
6206 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6207 else
6208 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6209
6210 tg3_full_unlock(tp);
6211
6212 return 0;
6213}
6214
6215static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6216{
6217 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6218
6219 tg3_full_lock(tp, 0);
6220 tp->ptp_adjust += delta;
6221 tg3_full_unlock(tp);
6222
6223 return 0;
6224}
6225
6226static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6227{
6228 u64 ns;
6229 u32 remainder;
6230 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6231
6232 tg3_full_lock(tp, 0);
6233 ns = tg3_refclk_read(tp);
6234 ns += tp->ptp_adjust;
6235 tg3_full_unlock(tp);
6236
6237 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6238 ts->tv_nsec = remainder;
6239
6240 return 0;
6241}
6242
6243static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6244 const struct timespec *ts)
6245{
6246 u64 ns;
6247 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6248
6249 ns = timespec_to_ns(ts);
6250
6251 tg3_full_lock(tp, 0);
6252 tg3_refclk_write(tp, ns);
6253 tp->ptp_adjust = 0;
6254 tg3_full_unlock(tp);
6255
6256 return 0;
6257}
6258
6259static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6260 struct ptp_clock_request *rq, int on)
6261{
92e6457d
NS		 6262 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6263 u32 clock_ctl;
6264 int rval = 0;
6265
6266 switch (rq->type) {
6267 case PTP_CLK_REQ_PEROUT:
6268 if (rq->perout.index != 0)
6269 return -EINVAL;
6270
6271 tg3_full_lock(tp, 0);
6272 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6273 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6274
6275 if (on) {
6276 u64 nsec;
6277
6278 nsec = rq->perout.start.sec * 1000000000ULL +
6279 rq->perout.start.nsec;
6280
6281 if (rq->perout.period.sec || rq->perout.period.nsec) {
6282 netdev_warn(tp->dev,
6283 "Device supports only a one-shot timesync output, period must be 0\n");
6284 rval = -EINVAL;
6285 goto err_out;
6286 }
6287
6288 if (nsec & (1ULL << 63)) {
6289 netdev_warn(tp->dev,
6290 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6291 rval = -EINVAL;
6292 goto err_out;
6293 }
6294
6295 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6296 tw32(TG3_EAV_WATCHDOG0_MSB,
6297 TG3_EAV_WATCHDOG0_EN |
6298 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6299
6300 tw32(TG3_EAV_REF_CLCK_CTL,
6301 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6302 } else {
6303 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6304 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6305 }
6306
6307err_out:
6308 tg3_full_unlock(tp);
6309 return rval;
6310
6311 default:
6312 break;
6313 }
6314
7d41e49a
MC		 6315 return -EOPNOTSUPP;
6316}
6317
6318static const struct ptp_clock_info tg3_ptp_caps = {
6319 .owner = THIS_MODULE,
6320 .name = "tg3 clock",
6321 .max_adj = 250000000,
6322 .n_alarm = 0,
6323 .n_ext_ts = 0,
92e6457d 6324 .n_per_out = 1,
7d41e49a
MC		 6325 .pps = 0,
6326 .adjfreq = tg3_ptp_adjfreq,
6327 .adjtime = tg3_ptp_adjtime,
6328 .gettime = tg3_ptp_gettime,
6329 .settime = tg3_ptp_settime,
6330 .enable = tg3_ptp_enable,
6331};
6332
fb4ce8ad
MC		 6333static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6334 struct skb_shared_hwtstamps *timestamp)
6335{
6336 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6337 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6338 tp->ptp_adjust);
6339}
6340
be947307
MC		 6341/* tp->lock must be held */
6342static void tg3_ptp_init(struct tg3 *tp)
6343{
6344 if (!tg3_flag(tp, PTP_CAPABLE))
6345 return;
6346
6347 /* Initialize the hardware clock to the system time. */
6348 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6349 tp->ptp_adjust = 0;
7d41e49a 6350 tp->ptp_info = tg3_ptp_caps;
be947307
MC		 6351}
6352
6353/* tp->lock must be held */
6354static void tg3_ptp_resume(struct tg3 *tp)
6355{
6356 if (!tg3_flag(tp, PTP_CAPABLE))
6357 return;
6358
6359 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6360 tp->ptp_adjust = 0;
6361}
6362
6363static void tg3_ptp_fini(struct tg3 *tp)
6364{
6365 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6366 return;
6367
7d41e49a 6368 ptp_clock_unregister(tp->ptp_clock);
be947307
MC		 6369 tp->ptp_clock = NULL;
6370 tp->ptp_adjust = 0;
6371}
6372
66cfd1bd
MC		 6373static inline int tg3_irq_sync(struct tg3 *tp)
6374{
6375 return tp->irq_sync;
6376}
6377
97bd8e49
MC		 6378static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6379{
6380 int i;
6381
6382 dst = (u32 *)((u8 *)dst + off);
6383 for (i = 0; i < len; i += sizeof(u32))
6384 *dst++ = tr32(off + i);
6385}
6386
6387static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6388{
6389 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6390 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6391 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6392 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6393 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6394 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6395 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6396 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6397 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6398 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6399 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6400 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6401 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6402 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6403 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6404 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6405 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6406 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6407 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6408
63c3a66f 6409 if (tg3_flag(tp, SUPPORT_MSIX))
97bd8e49
MC		 6410 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6411
6412 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6413 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6414 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6415 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6416 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6417 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6418 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6419 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6420
63c3a66f 6421 if (!tg3_flag(tp, 5705_PLUS)) {
97bd8e49
MC		 6422 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6423 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6424 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6425 }
6426
6427 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6428 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6429 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6430 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6431 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6432
63c3a66f 6433 if (tg3_flag(tp, NVRAM))
97bd8e49
MC		 6434 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6435}
6436
6437static void tg3_dump_state(struct tg3 *tp)
6438{
6439 int i;
6440 u32 *regs;
6441
6442 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
b2adaca9 6443 if (!regs)
97bd8e49 6444 return;
97bd8e49 6445
63c3a66f 6446 if (tg3_flag(tp, PCI_EXPRESS)) {
97bd8e49
MC		 6447 /* Read up to but not including private PCI registers */
6448 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6449 regs[i / sizeof(u32)] = tr32(i);
6450 } else
6451 tg3_dump_legacy_regs(tp, regs);
6452
6453 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6454 if (!regs[i + 0] && !regs[i + 1] &&
6455 !regs[i + 2] && !regs[i + 3])
6456 continue;
6457
6458 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6459 i * 4,
6460 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6461 }
6462
6463 kfree(regs);
6464
6465 for (i = 0; i < tp->irq_cnt; i++) {
6466 struct tg3_napi *tnapi = &tp->napi[i];
6467
6468 /* SW status block */
6469 netdev_err(tp->dev,
6470 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6471 i,
6472 tnapi->hw_status->status,
6473 tnapi->hw_status->status_tag,
6474 tnapi->hw_status->rx_jumbo_consumer,
6475 tnapi->hw_status->rx_consumer,
6476 tnapi->hw_status->rx_mini_consumer,
6477 tnapi->hw_status->idx[0].rx_producer,
6478 tnapi->hw_status->idx[0].tx_consumer);
6479
6480 netdev_err(tp->dev,
6481 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6482 i,
6483 tnapi->last_tag, tnapi->last_irq_tag,
6484 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6485 tnapi->rx_rcb_ptr,
6486 tnapi->prodring.rx_std_prod_idx,
6487 tnapi->prodring.rx_std_cons_idx,
6488 tnapi->prodring.rx_jmb_prod_idx,
6489 tnapi->prodring.rx_jmb_cons_idx);
6490 }
6491}
6492
df3e6548
MC		 6493/* This is called whenever we suspect that the system chipset is re-
6494 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6495 * is bogus tx completions. We try to recover by setting the
6496 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6497 * in the workqueue.
6498 */
6499static void tg3_tx_recover(struct tg3 *tp)
6500{
63c3a66f 6501 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
df3e6548
MC		 6502 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6503
5129c3a3
MC		 6504 netdev_warn(tp->dev,
6505 "The system may be re-ordering memory-mapped I/O "
6506 "cycles to the network device, attempting to recover. "
6507 "Please report the problem to the driver maintainer "
6508 "and include system chipset information.\n");
df3e6548 6509
63c3a66f 6510 tg3_flag_set(tp, TX_RECOVERY_PENDING);
df3e6548
MC		 6511}
6512
f3f3f27e 6513static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205 6514{
f65aac16
MC		 6515 /* Tell compiler to fetch tx indices from memory. */
6516 barrier();
f3f3f27e
MC		 6517 return tnapi->tx_pending -
6518 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 6519}
6520
1da177e4
LT		 6521/* Tigon3 never reports partial packet sends. So we do not
6522 * need special logic to handle SKBs that have not had all
6523 * of their frags sent yet, like SunGEM does.
6524 */
17375d25 6525static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 6526{
17375d25 6527 struct tg3 *tp = tnapi->tp;
898a56f8 6528 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 6529 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 6530 struct netdev_queue *txq;
6531 int index = tnapi - tp->napi;
298376d3 6532 unsigned int pkts_compl = 0, bytes_compl = 0;
fe5f5787 6533
63c3a66f 6534 if (tg3_flag(tp, ENABLE_TSS))
fe5f5787
MC		 6535 index--;
6536
6537 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 6538
6539 while (sw_idx != hw_idx) {
df8944cf 6540 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 6541 struct sk_buff *skb = ri->skb;
df3e6548
MC		 6542 int i, tx_bug = 0;
6543
6544 if (unlikely(skb == NULL)) {
6545 tg3_tx_recover(tp);
6546 return;
6547 }
1da177e4 6548
fb4ce8ad
MC		 6549 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6550 struct skb_shared_hwtstamps timestamp;
6551 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6552 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6553
6554 tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);
6555
6556 skb_tstamp_tx(skb, &timestamp);
6557 }
6558
f4188d8a 6559 pci_unmap_single(tp->pdev,
4e5e4f0d 6560 dma_unmap_addr(ri, mapping),
f4188d8a
AD		 6561 skb_headlen(skb),
6562 PCI_DMA_TODEVICE);
1da177e4
LT		 6563
6564 ri->skb = NULL;
6565
e01ee14d
MC		 6566 while (ri->fragmented) {
6567 ri->fragmented = false;
6568 sw_idx = NEXT_TX(sw_idx);
6569 ri = &tnapi->tx_buffers[sw_idx];
6570 }
6571
1da177e4
LT		 6572 sw_idx = NEXT_TX(sw_idx);
6573
6574 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 6575 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 6576 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6577 tx_bug = 1;
f4188d8a
AD		 6578
6579 pci_unmap_page(tp->pdev,
4e5e4f0d 6580 dma_unmap_addr(ri, mapping),
9e903e08 6581 skb_frag_size(&skb_shinfo(skb)->frags[i]),
f4188d8a 6582 PCI_DMA_TODEVICE);
e01ee14d
MC		 6583
6584 while (ri->fragmented) {
6585 ri->fragmented = false;
6586 sw_idx = NEXT_TX(sw_idx);
6587 ri = &tnapi->tx_buffers[sw_idx];
6588 }
6589
1da177e4
LT		 6590 sw_idx = NEXT_TX(sw_idx);
6591 }
6592
298376d3
TH		 6593 pkts_compl++;
6594 bytes_compl += skb->len;
6595
f47c11ee 6596 dev_kfree_skb(skb);
df3e6548
MC		 6597
6598 if (unlikely(tx_bug)) {
6599 tg3_tx_recover(tp);
6600 return;
6601 }
1da177e4
LT		 6602 }
6603
5cb917bc 6604 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
298376d3 6605
f3f3f27e 6606 tnapi->tx_cons = sw_idx;
1da177e4 6607
1b2a7205
MC		 6608 /* Need to make the tx_cons update visible to tg3_start_xmit()
6609 * before checking for netif_queue_stopped(). Without the
6610 * memory barrier, there is a small possibility that tg3_start_xmit()
6611 * will miss it and cause the queue to be stopped forever.
6612 */
6613 smp_mb();
6614
fe5f5787 6615 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 6616 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 6617 __netif_tx_lock(txq, smp_processor_id());
6618 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 6619 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 6620 netif_tx_wake_queue(txq);
6621 __netif_tx_unlock(txq);
51b91468 6622 }
1da177e4
LT		 6623}
6624
8d4057a9
ED		 6625static void tg3_frag_free(bool is_frag, void *data)
6626{
6627 if (is_frag)
6628 put_page(virt_to_head_page(data));
6629 else
6630 kfree(data);
6631}
6632
9205fd9c 6633static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
2b2cdb65 6634{
8d4057a9
ED		 6635 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6636 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6637
9205fd9c 6638 if (!ri->data)
2b2cdb65
MC		 6639 return;
6640
4e5e4f0d 6641 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
2b2cdb65 6642 map_sz, PCI_DMA_FROMDEVICE);
a1e8b307 6643 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
9205fd9c 6644 ri->data = NULL;
2b2cdb65
MC		 6645}
6646
8d4057a9 6647
1da177e4
LT		 6648/* Returns size of skb allocated or < 0 on error.
6649 *
6650 * We only need to fill in the address because the other members
6651 * of the RX descriptor are invariant, see tg3_init_rings.
6652 *
6653 * Note the purposeful assymetry of cpu vs. chip accesses. For
6654 * posting buffers we only dirty the first cache line of the RX
6655 * descriptor (containing the address). Whereas for the RX status
6656 * buffers the cpu only reads the last cacheline of the RX descriptor
6657 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6658 */
9205fd9c 6659static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
8d4057a9
ED		 6660 u32 opaque_key, u32 dest_idx_unmasked,
6661 unsigned int *frag_size)
1da177e4
LT		 6662{
6663 struct tg3_rx_buffer_desc *desc;
f94e290e 6664 struct ring_info *map;
9205fd9c 6665 u8 *data;
1da177e4 6666 dma_addr_t mapping;
9205fd9c 6667 int skb_size, data_size, dest_idx;
1da177e4 6668
1da177e4
LT		 6669 switch (opaque_key) {
6670 case RXD_OPAQUE_RING_STD:
2c49a44d 6671 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
21f581a5
MC		 6672 desc = &tpr->rx_std[dest_idx];
6673 map = &tpr->rx_std_buffers[dest_idx];
9205fd9c 6674 data_size = tp->rx_pkt_map_sz;
1da177e4
LT		 6675 break;
6676
6677 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6678 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
79ed5ac7 6679 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 6680 map = &tpr->rx_jmb_buffers[dest_idx];
9205fd9c 6681 data_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 6682 break;
6683
6684 default:
6685 return -EINVAL;
855e1111 6686 }
1da177e4
LT		 6687
6688 /* Do not overwrite any of the map or rp information
6689 * until we are sure we can commit to a new buffer.
6690 *
6691 * Callers depend upon this behavior and assume that
6692 * we leave everything unchanged if we fail.
6693 */
9205fd9c
ED		 6694 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6695 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
a1e8b307
ED		 6696 if (skb_size <= PAGE_SIZE) {
6697 data = netdev_alloc_frag(skb_size);
6698 *frag_size = skb_size;
8d4057a9
ED		 6699 } else {
6700 data = kmalloc(skb_size, GFP_ATOMIC);
6701 *frag_size = 0;
6702 }
9205fd9c 6703 if (!data)
1da177e4
LT		 6704 return -ENOMEM;
6705
9205fd9c
ED		 6706 mapping = pci_map_single(tp->pdev,
6707 data + TG3_RX_OFFSET(tp),
6708 data_size,
1da177e4 6709 PCI_DMA_FROMDEVICE);
8d4057a9 6710 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
a1e8b307 6711 tg3_frag_free(skb_size <= PAGE_SIZE, data);
a21771dd
MC		 6712 return -EIO;
6713 }
1da177e4 6714
9205fd9c 6715 map->data = data;
4e5e4f0d 6716 dma_unmap_addr_set(map, mapping, mapping);
1da177e4 6717
1da177e4
LT		 6718 desc->addr_hi = ((u64)mapping >> 32);
6719 desc->addr_lo = ((u64)mapping & 0xffffffff);
6720
9205fd9c 6721 return data_size;
1da177e4
LT		 6722}
6723
6724/* We only need to move over in the address because the other
6725 * members of the RX descriptor are invariant. See notes above
9205fd9c 6726 * tg3_alloc_rx_data for full details.
1da177e4 6727 */
a3896167
MC		 6728static void tg3_recycle_rx(struct tg3_napi *tnapi,
6729 struct tg3_rx_prodring_set *dpr,
6730 u32 opaque_key, int src_idx,
6731 u32 dest_idx_unmasked)
1da177e4 6732{
17375d25 6733 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 6734 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6735 struct ring_info *src_map, *dest_map;
8fea32b9 6736 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
c6cdf436 6737 int dest_idx;
1da177e4
LT		 6738
6739 switch (opaque_key) {
6740 case RXD_OPAQUE_RING_STD:
2c49a44d 6741 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
a3896167
MC		 6742 dest_desc = &dpr->rx_std[dest_idx];
6743 dest_map = &dpr->rx_std_buffers[dest_idx];
6744 src_desc = &spr->rx_std[src_idx];
6745 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 6746 break;
6747
6748 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6749 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
a3896167
MC		 6750 dest_desc = &dpr->rx_jmb[dest_idx].std;
6751 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6752 src_desc = &spr->rx_jmb[src_idx].std;
6753 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 6754 break;
6755
6756 default:
6757 return;
855e1111 6758 }
1da177e4 6759
9205fd9c 6760 dest_map->data = src_map->data;
4e5e4f0d
FT		 6761 dma_unmap_addr_set(dest_map, mapping,
6762 dma_unmap_addr(src_map, mapping));
1da177e4
LT		 6763 dest_desc->addr_hi = src_desc->addr_hi;
6764 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 6765
6766 /* Ensure that the update to the skb happens after the physical
6767 * addresses have been transferred to the new BD location.
6768 */
6769 smp_wmb();
6770
9205fd9c 6771 src_map->data = NULL;
1da177e4
LT		 6772}
6773
1da177e4
LT		 6774/* The RX ring scheme is composed of multiple rings which post fresh
6775 * buffers to the chip, and one special ring the chip uses to report
6776 * status back to the host.
6777 *
6778 * The special ring reports the status of received packets to the
6779 * host. The chip does not write into the original descriptor the
6780 * RX buffer was obtained from. The chip simply takes the original
6781 * descriptor as provided by the host, updates the status and length
6782 * field, then writes this into the next status ring entry.
6783 *
6784 * Each ring the host uses to post buffers to the chip is described
6785 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6786 * it is first placed into the on-chip ram. When the packet's length
6787 * is known, it walks down the TG3_BDINFO entries to select the ring.
6788 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6789 * which is within the range of the new packet's length is chosen.
6790 *
6791 * The "separate ring for rx status" scheme may sound queer, but it makes
6792 * sense from a cache coherency perspective. If only the host writes
6793 * to the buffer post rings, and only the chip writes to the rx status
6794 * rings, then cache lines never move beyond shared-modified state.
6795 * If both the host and chip were to write into the same ring, cache line
6796 * eviction could occur since both entities want it in an exclusive state.
6797 */
17375d25 6798static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 6799{
17375d25 6800 struct tg3 *tp = tnapi->tp;
f92905de 6801 u32 work_mask, rx_std_posted = 0;
4361935a 6802 u32 std_prod_idx, jmb_prod_idx;
72334482 6803 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 6804 u16 hw_idx;
1da177e4 6805 int received;
8fea32b9 6806 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
1da177e4 6807
8d9d7cfc 6808 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 6809 /*
6810 * We need to order the read of hw_idx and the read of
6811 * the opaque cookie.
6812 */
6813 rmb();
1da177e4
LT		 6814 work_mask = 0;
6815 received = 0;
4361935a
MC		 6816 std_prod_idx = tpr->rx_std_prod_idx;
6817 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 6818 while (sw_idx != hw_idx && budget > 0) {
afc081f8 6819 struct ring_info *ri;
72334482 6820 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 6821 unsigned int len;
6822 struct sk_buff *skb;
6823 dma_addr_t dma_addr;
6824 u32 opaque_key, desc_idx, *post_ptr;
9205fd9c 6825 u8 *data;
fb4ce8ad 6826 u64 tstamp = 0;
1da177e4
LT		 6827
6828 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6829 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6830 if (opaque_key == RXD_OPAQUE_RING_STD) {
8fea32b9 6831 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4e5e4f0d 6832 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6833 data = ri->data;
4361935a 6834 post_ptr = &std_prod_idx;
f92905de 6835 rx_std_posted++;
1da177e4 6836 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
8fea32b9 6837 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4e5e4f0d 6838 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6839 data = ri->data;
4361935a 6840 post_ptr = &jmb_prod_idx;
21f581a5 6841 } else
1da177e4 6842 goto next_pkt_nopost;
1da177e4
LT		 6843
6844 work_mask |= opaque_key;
6845
6846 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
6847 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
6848 drop_it:
a3896167 6849 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6850 desc_idx, *post_ptr);
6851 drop_it_no_recycle:
6852 /* Other statistics kept track of by card. */
b0057c51 6853 tp->rx_dropped++;
1da177e4
LT		 6854 goto next_pkt;
6855 }
6856
9205fd9c 6857 prefetch(data + TG3_RX_OFFSET(tp));
ad829268
MC		 6858 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6859 ETH_FCS_LEN;
1da177e4 6860
fb4ce8ad
MC		 6861 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6862 RXD_FLAG_PTPSTAT_PTPV1 ||
6863 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6864 RXD_FLAG_PTPSTAT_PTPV2) {
6865 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6866 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6867 }
6868
d2757fc4 6869 if (len > TG3_RX_COPY_THRESH(tp)) {
1da177e4 6870 int skb_size;
8d4057a9 6871 unsigned int frag_size;
1da177e4 6872
9205fd9c 6873 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
8d4057a9 6874 *post_ptr, &frag_size);
1da177e4
LT		 6875 if (skb_size < 0)
6876 goto drop_it;
6877
287be12e 6878 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 6879 PCI_DMA_FROMDEVICE);
6880
9205fd9c 6881 /* Ensure that the update to the data happens
61e800cf
MC		 6882 * after the usage of the old DMA mapping.
6883 */
6884 smp_wmb();
6885
9205fd9c 6886 ri->data = NULL;
61e800cf 6887
85aec73d
IV		 6888 skb = build_skb(data, frag_size);
6889 if (!skb) {
6890 tg3_frag_free(frag_size != 0, data);
6891 goto drop_it_no_recycle;
6892 }
6893 skb_reserve(skb, TG3_RX_OFFSET(tp));
1da177e4 6894 } else {
a3896167 6895 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6896 desc_idx, *post_ptr);
6897
9205fd9c
ED		 6898 skb = netdev_alloc_skb(tp->dev,
6899 len + TG3_RAW_IP_ALIGN);
6900 if (skb == NULL)
1da177e4
LT		 6901 goto drop_it_no_recycle;
6902
9205fd9c 6903 skb_reserve(skb, TG3_RAW_IP_ALIGN);
1da177e4 6904 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
9205fd9c
ED		 6905 memcpy(skb->data,
6906 data + TG3_RX_OFFSET(tp),
6907 len);
1da177e4 6908 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
1da177e4
LT		 6909 }
6910
9205fd9c 6911 skb_put(skb, len);
fb4ce8ad
MC		 6912 if (tstamp)
6913 tg3_hwclock_to_timestamp(tp, tstamp,
6914 skb_hwtstamps(skb));
6915
dc668910 6916 if ((tp->dev->features & NETIF_F_RXCSUM) &&
1da177e4
LT		 6917 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6918 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6919 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6920 skb->ip_summed = CHECKSUM_UNNECESSARY;
6921 else
bc8acf2c 6922 skb_checksum_none_assert(skb);
1da177e4
LT		 6923
6924 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 6925
6926 if (len > (tp->dev->mtu + ETH_HLEN) &&
6927 skb->protocol != htons(ETH_P_8021Q)) {
6928 dev_kfree_skb(skb);
b0057c51 6929 goto drop_it_no_recycle;
f7b493e0
MC		 6930 }
6931
9dc7a113 6932 if (desc->type_flags & RXD_FLAG_VLAN &&
bf933c80 6933 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
86a9bad3 6934 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
bf933c80 6935 desc->err_vlan & RXD_VLAN_MASK);
9dc7a113 6936
bf933c80 6937 napi_gro_receive(&tnapi->napi, skb);
1da177e4 6938
1da177e4
LT		 6939 received++;
6940 budget--;
6941
6942next_pkt:
6943 (*post_ptr)++;
f92905de
MC		 6944
6945 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
2c49a44d
MC		 6946 tpr->rx_std_prod_idx = std_prod_idx &
6947 tp->rx_std_ring_mask;
86cfe4ff
MC		 6948 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6949 tpr->rx_std_prod_idx);
f92905de
MC		 6950 work_mask &= ~RXD_OPAQUE_RING_STD;
6951 rx_std_posted = 0;
6952 }
1da177e4 6953next_pkt_nopost:
483ba50b 6954 sw_idx++;
7cb32cf2 6955 sw_idx &= tp->rx_ret_ring_mask;
52f6d697
MC		 6956
6957 /* Refresh hw_idx to see if there is new work */
6958 if (sw_idx == hw_idx) {
8d9d7cfc 6959 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 6960 rmb();
6961 }
1da177e4
LT		 6962 }
6963
6964 /* ACK the status ring. */
72334482
MC		 6965 tnapi->rx_rcb_ptr = sw_idx;
6966 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 6967
6968 /* Refill RX ring(s). */
63c3a66f 6969 if (!tg3_flag(tp, ENABLE_RSS)) {
6541b806
MC		 6970 /* Sync BD data before updating mailbox */
6971 wmb();
6972
b196c7e4 6973 if (work_mask & RXD_OPAQUE_RING_STD) {
2c49a44d
MC		 6974 tpr->rx_std_prod_idx = std_prod_idx &
6975 tp->rx_std_ring_mask;
b196c7e4
MC		 6976 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6977 tpr->rx_std_prod_idx);
6978 }
6979 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2c49a44d
MC		 6980 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6981 tp->rx_jmb_ring_mask;
b196c7e4
MC		 6982 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6983 tpr->rx_jmb_prod_idx);
6984 }
6985 mmiowb();
6986 } else if (work_mask) {
6987 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6988 * updated before the producer indices can be updated.
6989 */
6990 smp_wmb();
6991
2c49a44d
MC		 6992 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6993 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
b196c7e4 6994
7ae52890
MC		 6995 if (tnapi != &tp->napi[1]) {
6996 tp->rx_refill = true;
e4af1af9 6997 napi_schedule(&tp->napi[1].napi);
7ae52890 6998 }
1da177e4 6999 }
1da177e4
LT		 7000
7001 return received;
7002}
7003
35f2d7d0 7004static void tg3_poll_link(struct tg3 *tp)
1da177e4 7005{
1da177e4 7006 /* handle link change and other phy events */
63c3a66f 7007 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
35f2d7d0
MC		 7008 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7009
1da177e4
LT		 7010 if (sblk->status & SD_STATUS_LINK_CHG) {
7011 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 7012 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 7013 spin_lock(&tp->lock);
63c3a66f 7014 if (tg3_flag(tp, USE_PHYLIB)) {
dd477003
MC		 7015 tw32_f(MAC_STATUS,
7016 (MAC_STATUS_SYNC_CHANGED |
7017 MAC_STATUS_CFG_CHANGED |
7018 MAC_STATUS_MI_COMPLETION |
7019 MAC_STATUS_LNKSTATE_CHANGED));
7020 udelay(40);
7021 } else
953c96e0 7022 tg3_setup_phy(tp, false);
f47c11ee 7023 spin_unlock(&tp->lock);
1da177e4
LT		 7024 }
7025 }
35f2d7d0
MC		 7026}
7027
f89f38b8
MC		 7028static int tg3_rx_prodring_xfer(struct tg3 *tp,
7029 struct tg3_rx_prodring_set *dpr,
7030 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 7031{
7032 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 7033 int i, err = 0;
b196c7e4
MC		 7034
7035 while (1) {
7036 src_prod_idx = spr->rx_std_prod_idx;
7037
7038 /* Make sure updates to the rx_std_buffers[] entries and the
7039 * standard producer index are seen in the correct order.
7040 */
7041 smp_rmb();
7042
7043 if (spr->rx_std_cons_idx == src_prod_idx)
7044 break;
7045
7046 if (spr->rx_std_cons_idx < src_prod_idx)
7047 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7048 else
2c49a44d
MC		 7049 cpycnt = tp->rx_std_ring_mask + 1 -
7050 spr->rx_std_cons_idx;
b196c7e4 7051
2c49a44d
MC		 7052 cpycnt = min(cpycnt,
7053 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
b196c7e4
MC		 7054
7055 si = spr->rx_std_cons_idx;
7056 di = dpr->rx_std_prod_idx;
7057
e92967bf 7058 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7059 if (dpr->rx_std_buffers[i].data) {
e92967bf 7060 cpycnt = i - di;
f89f38b8 7061 err = -ENOSPC;
e92967bf
MC		 7062 break;
7063 }
7064 }
7065
7066 if (!cpycnt)
7067 break;
7068
7069 /* Ensure that updates to the rx_std_buffers ring and the
7070 * shadowed hardware producer ring from tg3_recycle_skb() are
7071 * ordered correctly WRT the skb check above.
7072 */
7073 smp_rmb();
7074
b196c7e4
MC		 7075 memcpy(&dpr->rx_std_buffers[di],
7076 &spr->rx_std_buffers[si],
7077 cpycnt * sizeof(struct ring_info));
7078
7079 for (i = 0; i < cpycnt; i++, di++, si++) {
7080 struct tg3_rx_buffer_desc *sbd, *dbd;
7081 sbd = &spr->rx_std[si];
7082 dbd = &dpr->rx_std[di];
7083 dbd->addr_hi = sbd->addr_hi;
7084 dbd->addr_lo = sbd->addr_lo;
7085 }
7086
2c49a44d
MC		 7087 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7088 tp->rx_std_ring_mask;
7089 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7090 tp->rx_std_ring_mask;
b196c7e4
MC		 7091 }
7092
7093 while (1) {
7094 src_prod_idx = spr->rx_jmb_prod_idx;
7095
7096 /* Make sure updates to the rx_jmb_buffers[] entries and
7097 * the jumbo producer index are seen in the correct order.
7098 */
7099 smp_rmb();
7100
7101 if (spr->rx_jmb_cons_idx == src_prod_idx)
7102 break;
7103
7104 if (spr->rx_jmb_cons_idx < src_prod_idx)
7105 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7106 else
2c49a44d
MC		 7107 cpycnt = tp->rx_jmb_ring_mask + 1 -
7108 spr->rx_jmb_cons_idx;
b196c7e4
MC		 7109
7110 cpycnt = min(cpycnt,
2c49a44d 7111 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7112
7113 si = spr->rx_jmb_cons_idx;
7114 di = dpr->rx_jmb_prod_idx;
7115
e92967bf 7116 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7117 if (dpr->rx_jmb_buffers[i].data) {
e92967bf 7118 cpycnt = i - di;
f89f38b8 7119 err = -ENOSPC;
e92967bf
MC		 7120 break;
7121 }
7122 }
7123
7124 if (!cpycnt)
7125 break;
7126
7127 /* Ensure that updates to the rx_jmb_buffers ring and the
7128 * shadowed hardware producer ring from tg3_recycle_skb() are
7129 * ordered correctly WRT the skb check above.
7130 */
7131 smp_rmb();
7132
b196c7e4
MC		 7133 memcpy(&dpr->rx_jmb_buffers[di],
7134 &spr->rx_jmb_buffers[si],
7135 cpycnt * sizeof(struct ring_info));
7136
7137 for (i = 0; i < cpycnt; i++, di++, si++) {
7138 struct tg3_rx_buffer_desc *sbd, *dbd;
7139 sbd = &spr->rx_jmb[si].std;
7140 dbd = &dpr->rx_jmb[di].std;
7141 dbd->addr_hi = sbd->addr_hi;
7142 dbd->addr_lo = sbd->addr_lo;
7143 }
7144
2c49a44d
MC		 7145 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7146 tp->rx_jmb_ring_mask;
7147 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7148 tp->rx_jmb_ring_mask;
b196c7e4 7149 }
f89f38b8
MC		 7150
7151 return err;
b196c7e4
MC		 7152}
7153
35f2d7d0
MC		 7154static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7155{
7156 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 7157
7158 /* run TX completion thread */
f3f3f27e 7159 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 7160 tg3_tx(tnapi);
63c3a66f 7161 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
4fd7ab59 7162 return work_done;
1da177e4
LT		 7163 }
7164
f891ea16
MC		 7165 if (!tnapi->rx_rcb_prod_idx)
7166 return work_done;
7167
1da177e4
LT		 7168 /* run RX thread, within the bounds set by NAPI.
7169 * All RX "locking" is done by ensuring outside
bea3348e 7170 * code synchronizes with tg3->napi.poll()
1da177e4 7171 */
8d9d7cfc 7172 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 7173 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 7174
63c3a66f 7175 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
8fea32b9 7176 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
f89f38b8 7177 int i, err = 0;
e4af1af9
MC		 7178 u32 std_prod_idx = dpr->rx_std_prod_idx;
7179 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 7180
7ae52890 7181 tp->rx_refill = false;
9102426a 7182 for (i = 1; i <= tp->rxq_cnt; i++)
f89f38b8 7183 err |= tg3_rx_prodring_xfer(tp, dpr,
8fea32b9 7184 &tp->napi[i].prodring);
b196c7e4
MC		 7185
7186 wmb();
7187
e4af1af9
MC		 7188 if (std_prod_idx != dpr->rx_std_prod_idx)
7189 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7190 dpr->rx_std_prod_idx);
b196c7e4 7191
e4af1af9
MC		 7192 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7193 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7194 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7195
7196 mmiowb();
f89f38b8
MC		 7197
7198 if (err)
7199 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 7200 }
7201
6f535763
DM		 7202 return work_done;
7203}
7204
db219973
MC		 7205static inline void tg3_reset_task_schedule(struct tg3 *tp)
7206{
7207 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7208 schedule_work(&tp->reset_task);
7209}
7210
7211static inline void tg3_reset_task_cancel(struct tg3 *tp)
7212{
7213 cancel_work_sync(&tp->reset_task);
7214 tg3_flag_clear(tp, RESET_TASK_PENDING);
c7101359 7215 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
db219973
MC		 7216}
7217
35f2d7d0
MC		 7218static int tg3_poll_msix(struct napi_struct *napi, int budget)
7219{
7220 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7221 struct tg3 *tp = tnapi->tp;
7222 int work_done = 0;
7223 struct tg3_hw_status *sblk = tnapi->hw_status;
7224
7225 while (1) {
7226 work_done = tg3_poll_work(tnapi, work_done, budget);
7227
63c3a66f 7228 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
35f2d7d0
MC		 7229 goto tx_recovery;
7230
7231 if (unlikely(work_done >= budget))
7232 break;
7233
c6cdf436 7234 /* tp->last_tag is used in tg3_int_reenable() below
35f2d7d0
MC		 7235 * to tell the hw how much work has been processed,
7236 * so we must read it before checking for more work.
7237 */
7238 tnapi->last_tag = sblk->status_tag;
7239 tnapi->last_irq_tag = tnapi->last_tag;
7240 rmb();
7241
7242 /* check for RX/TX work to do */
6d40db7b
MC		 7243 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7244 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7ae52890
MC		 7245
7246 /* This test here is not race free, but will reduce
7247 * the number of interrupts by looping again.
7248 */
7249 if (tnapi == &tp->napi[1] && tp->rx_refill)
7250 continue;
7251
35f2d7d0
MC		 7252 napi_complete(napi);
7253 /* Reenable interrupts. */
7254 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7ae52890
MC		 7255
7256 /* This test here is synchronized by napi_schedule()
7257 * and napi_complete() to close the race condition.
7258 */
7259 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7260 tw32(HOSTCC_MODE, tp->coalesce_mode |
7261 HOSTCC_MODE_ENABLE |
7262 tnapi->coal_now);
7263 }
35f2d7d0
MC		 7264 mmiowb();
7265 break;
7266 }
7267 }
7268
7269 return work_done;
7270
7271tx_recovery:
7272 /* work_done is guaranteed to be less than budget. */
7273 napi_complete(napi);
db219973 7274 tg3_reset_task_schedule(tp);
35f2d7d0
MC		 7275 return work_done;
7276}
7277
e64de4e6
MC		 7278static void tg3_process_error(struct tg3 *tp)
7279{
7280 u32 val;
7281 bool real_error = false;
7282
63c3a66f 7283 if (tg3_flag(tp, ERROR_PROCESSED))
e64de4e6
MC		 7284 return;
7285
7286 /* Check Flow Attention register */
7287 val = tr32(HOSTCC_FLOW_ATTN);
7288 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7289 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7290 real_error = true;
7291 }
7292
7293 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7294 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7295 real_error = true;
7296 }
7297
7298 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7299 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7300 real_error = true;
7301 }
7302
7303 if (!real_error)
7304 return;
7305
7306 tg3_dump_state(tp);
7307
63c3a66f 7308 tg3_flag_set(tp, ERROR_PROCESSED);
db219973 7309 tg3_reset_task_schedule(tp);
e64de4e6
MC		 7310}
7311
6f535763
DM		 7312static int tg3_poll(struct napi_struct *napi, int budget)
7313{
8ef0442f
MC		 7314 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7315 struct tg3 *tp = tnapi->tp;
6f535763 7316 int work_done = 0;
898a56f8 7317 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 7318
7319 while (1) {
e64de4e6
MC		 7320 if (sblk->status & SD_STATUS_ERROR)
7321 tg3_process_error(tp);
7322
35f2d7d0
MC		 7323 tg3_poll_link(tp);
7324
17375d25 7325 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763 7326
63c3a66f 7327 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6f535763
DM		 7328 goto tx_recovery;
7329
7330 if (unlikely(work_done >= budget))
7331 break;
7332
63c3a66f 7333 if (tg3_flag(tp, TAGGED_STATUS)) {
17375d25 7334 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 7335 * to tell the hw how much work has been processed,
7336 * so we must read it before checking for more work.
7337 */
898a56f8
MC		 7338 tnapi->last_tag = sblk->status_tag;
7339 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 7340 rmb();
7341 } else
7342 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 7343
17375d25 7344 if (likely(!tg3_has_work(tnapi))) {
288379f0 7345 napi_complete(napi);
17375d25 7346 tg3_int_reenable(tnapi);
6f535763
DM		 7347 break;
7348 }
1da177e4
LT		 7349 }
7350
bea3348e 7351 return work_done;
6f535763
DM		 7352
7353tx_recovery:
4fd7ab59 7354 /* work_done is guaranteed to be less than budget. */
288379f0 7355 napi_complete(napi);
db219973 7356 tg3_reset_task_schedule(tp);
4fd7ab59 7357 return work_done;
1da177e4
LT		 7358}
7359
66cfd1bd
MC		 7360static void tg3_napi_disable(struct tg3 *tp)
7361{
7362 int i;
7363
7364 for (i = tp->irq_cnt - 1; i >= 0; i--)
7365 napi_disable(&tp->napi[i].napi);
7366}
7367
7368static void tg3_napi_enable(struct tg3 *tp)
7369{
7370 int i;
7371
7372 for (i = 0; i < tp->irq_cnt; i++)
7373 napi_enable(&tp->napi[i].napi);
7374}
7375
7376static void tg3_napi_init(struct tg3 *tp)
7377{
7378 int i;
7379
7380 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7381 for (i = 1; i < tp->irq_cnt; i++)
7382 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7383}
7384
7385static void tg3_napi_fini(struct tg3 *tp)
7386{
7387 int i;
7388
7389 for (i = 0; i < tp->irq_cnt; i++)
7390 netif_napi_del(&tp->napi[i].napi);
7391}
7392
7393static inline void tg3_netif_stop(struct tg3 *tp)
7394{
7395 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7396 tg3_napi_disable(tp);
f4a46d1f 7397 netif_carrier_off(tp->dev);
66cfd1bd
MC		 7398 netif_tx_disable(tp->dev);
7399}
7400
35763066 7401/* tp->lock must be held */
66cfd1bd
MC		 7402static inline void tg3_netif_start(struct tg3 *tp)
7403{
be947307
MC		 7404 tg3_ptp_resume(tp);
7405
66cfd1bd
MC		 7406 /* NOTE: unconditional netif_tx_wake_all_queues is only
7407 * appropriate so long as all callers are assured to
7408 * have free tx slots (such as after tg3_init_hw)
7409 */
7410 netif_tx_wake_all_queues(tp->dev);
7411
f4a46d1f
NNS		 7412 if (tp->link_up)
7413 netif_carrier_on(tp->dev);
7414
66cfd1bd
MC		 7415 tg3_napi_enable(tp);
7416 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7417 tg3_enable_ints(tp);
7418}
7419
f47c11ee
DM		 7420static void tg3_irq_quiesce(struct tg3 *tp)
7421{
4f125f42
MC		 7422 int i;
7423
f47c11ee
DM		 7424 BUG_ON(tp->irq_sync);
7425
7426 tp->irq_sync = 1;
7427 smp_mb();
7428
4f125f42
MC		 7429 for (i = 0; i < tp->irq_cnt; i++)
7430 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 7431}
7432
f47c11ee
DM		 7433/* Fully shutdown all tg3 driver activity elsewhere in the system.
7434 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7435 * with as well. Most of the time, this is not necessary except when
7436 * shutting down the device.
7437 */
7438static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7439{
46966545 7440 spin_lock_bh(&tp->lock);
f47c11ee
DM		 7441 if (irq_sync)
7442 tg3_irq_quiesce(tp);
f47c11ee
DM		 7443}
7444
7445static inline void tg3_full_unlock(struct tg3 *tp)
7446{
f47c11ee
DM		 7447 spin_unlock_bh(&tp->lock);
7448}
7449
fcfa0a32
MC		 7450/* One-shot MSI handler - Chip automatically disables interrupt
7451 * after sending MSI so driver doesn't have to do it.
7452 */
7d12e780 7453static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 7454{
09943a18
MC		 7455 struct tg3_napi *tnapi = dev_id;
7456 struct tg3 *tp = tnapi->tp;
fcfa0a32 7457
898a56f8 7458 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7459 if (tnapi->rx_rcb)
7460 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 7461
7462 if (likely(!tg3_irq_sync(tp)))
09943a18 7463 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 7464
7465 return IRQ_HANDLED;
7466}
7467
88b06bc2
MC		 7468/* MSI ISR - No need to check for interrupt sharing and no need to
7469 * flush status block and interrupt mailbox. PCI ordering rules
7470 * guarantee that MSI will arrive after the status block.
7471 */
7d12e780 7472static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 7473{
09943a18
MC		 7474 struct tg3_napi *tnapi = dev_id;
7475 struct tg3 *tp = tnapi->tp;
88b06bc2 7476
898a56f8 7477 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7478 if (tnapi->rx_rcb)
7479 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 7480 /*
fac9b83e 7481 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 7482 * chip-internal interrupt pending events.
fac9b83e 7483 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 7484 * NIC to stop sending us irqs, engaging "in-intr-handler"
7485 * event coalescing.
7486 */
5b39de91 7487 tw32_mailbox(tnapi->int_mbox, 0x00000001);
61487480 7488 if (likely(!tg3_irq_sync(tp)))
09943a18 7489 napi_schedule(&tnapi->napi);
61487480 7490
88b06bc2
MC		 7491 return IRQ_RETVAL(1);
7492}
7493
7d12e780 7494static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 7495{
09943a18
MC		 7496 struct tg3_napi *tnapi = dev_id;
7497 struct tg3 *tp = tnapi->tp;
898a56f8 7498 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 7499 unsigned int handled = 1;
7500
1da177e4
LT		 7501 /* In INTx mode, it is possible for the interrupt to arrive at
7502 * the CPU before the status block posted prior to the interrupt.
7503 * Reading the PCI State register will confirm whether the
7504 * interrupt is ours and will flush the status block.
7505 */
d18edcb2 7506 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
63c3a66f 7507 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7508 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7509 handled = 0;
f47c11ee 7510 goto out;
fac9b83e 7511 }
d18edcb2
MC		 7512 }
7513
7514 /*
7515 * Writing any value to intr-mbox-0 clears PCI INTA# and
7516 * chip-internal interrupt pending events.
7517 * Writing non-zero to intr-mbox-0 additional tells the
7518 * NIC to stop sending us irqs, engaging "in-intr-handler"
7519 * event coalescing.
c04cb347
MC		 7520 *
7521 * Flush the mailbox to de-assert the IRQ immediately to prevent
7522 * spurious interrupts. The flush impacts performance but
7523 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7524 */
c04cb347 7525 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 7526 if (tg3_irq_sync(tp))
7527 goto out;
7528 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 7529 if (likely(tg3_has_work(tnapi))) {
72334482 7530 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 7531 napi_schedule(&tnapi->napi);
d18edcb2
MC		 7532 } else {
7533 /* No work, shared interrupt perhaps? re-enable
7534 * interrupts, and flush that PCI write
7535 */
7536 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7537 0x00000000);
fac9b83e 7538 }
f47c11ee 7539out:
fac9b83e
DM		 7540 return IRQ_RETVAL(handled);
7541}
7542
7d12e780 7543static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 7544{
09943a18
MC		 7545 struct tg3_napi *tnapi = dev_id;
7546 struct tg3 *tp = tnapi->tp;
898a56f8 7547 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 7548 unsigned int handled = 1;
7549
fac9b83e
DM		 7550 /* In INTx mode, it is possible for the interrupt to arrive at
7551 * the CPU before the status block posted prior to the interrupt.
7552 * Reading the PCI State register will confirm whether the
7553 * interrupt is ours and will flush the status block.
7554 */
898a56f8 7555 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
63c3a66f 7556 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7557 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7558 handled = 0;
f47c11ee 7559 goto out;
1da177e4 7560 }
d18edcb2
MC		 7561 }
7562
7563 /*
7564 * writing any value to intr-mbox-0 clears PCI INTA# and
7565 * chip-internal interrupt pending events.
7566 * writing non-zero to intr-mbox-0 additional tells the
7567 * NIC to stop sending us irqs, engaging "in-intr-handler"
7568 * event coalescing.
c04cb347
MC		 7569 *
7570 * Flush the mailbox to de-assert the IRQ immediately to prevent
7571 * spurious interrupts. The flush impacts performance but
7572 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7573 */
c04cb347 7574 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 7575
7576 /*
7577 * In a shared interrupt configuration, sometimes other devices'
7578 * interrupts will scream. We record the current status tag here
7579 * so that the above check can report that the screaming interrupts
7580 * are unhandled. Eventually they will be silenced.
7581 */
898a56f8 7582 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 7583
d18edcb2
MC		 7584 if (tg3_irq_sync(tp))
7585 goto out;
624f8e50 7586
72334482 7587 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 7588
09943a18 7589 napi_schedule(&tnapi->napi);
624f8e50 7590
f47c11ee 7591out:
1da177e4
LT		 7592 return IRQ_RETVAL(handled);
7593}
7594
7938109f 7595/* ISR for interrupt test */
7d12e780 7596static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 7597{
09943a18
MC		 7598 struct tg3_napi *tnapi = dev_id;
7599 struct tg3 *tp = tnapi->tp;
898a56f8 7600 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 7601
f9804ddb
MC		 7602 if ((sblk->status & SD_STATUS_UPDATED) ||
7603 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 7604 tg3_disable_ints(tp);
7938109f
MC		 7605 return IRQ_RETVAL(1);
7606 }
7607 return IRQ_RETVAL(0);
7608}
7609
1da177e4
LT		 7610#ifdef CONFIG_NET_POLL_CONTROLLER
7611static void tg3_poll_controller(struct net_device *dev)
7612{
4f125f42 7613 int i;
88b06bc2
MC		 7614 struct tg3 *tp = netdev_priv(dev);
7615
9c13cb8b
NNS		 7616 if (tg3_irq_sync(tp))
7617 return;
7618
4f125f42 7619 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 7620 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 7621}
7622#endif
7623
1da177e4
LT		 7624static void tg3_tx_timeout(struct net_device *dev)
7625{
7626 struct tg3 *tp = netdev_priv(dev);
7627
b0408751 7628 if (netif_msg_tx_err(tp)) {
05dbe005 7629 netdev_err(dev, "transmit timed out, resetting\n");
97bd8e49 7630 tg3_dump_state(tp);
b0408751 7631 }
1da177e4 7632
db219973 7633 tg3_reset_task_schedule(tp);
1da177e4
LT		 7634}
7635
c58ec932
MC		 7636/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7637static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7638{
7639 u32 base = (u32) mapping & 0xffffffff;
7640
37567910 7641 return base + len + 8 < base;
c58ec932
MC		 7642}
7643
0f0d1510
MC		 7644/* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7645 * of any 4GB boundaries: 4G, 8G, etc
7646 */
7647static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7648 u32 len, u32 mss)
7649{
7650 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7651 u32 base = (u32) mapping & 0xffffffff;
7652
7653 return ((base + len + (mss & 0x3fff)) < base);
7654 }
7655 return 0;
7656}
7657
72f2afb8
MC		 7658/* Test for DMA addresses > 40-bit */
7659static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7660 int len)
7661{
7662#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
63c3a66f 7663 if (tg3_flag(tp, 40BIT_DMA_BUG))
807540ba 7664 return ((u64) mapping + len) > DMA_BIT_MASK(40);
72f2afb8
MC		 7665 return 0;
7666#else
7667 return 0;
7668#endif
7669}
7670
d1a3b737 7671static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
92cd3a17
MC		 7672 dma_addr_t mapping, u32 len, u32 flags,
7673 u32 mss, u32 vlan)
2ffcc981 7674{
92cd3a17
MC		 7675 txbd->addr_hi = ((u64) mapping >> 32);
7676 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7677 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7678 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
2ffcc981 7679}
1da177e4 7680
84b67b27 7681static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
d1a3b737
MC		 7682 dma_addr_t map, u32 len, u32 flags,
7683 u32 mss, u32 vlan)
7684{
7685 struct tg3 *tp = tnapi->tp;
7686 bool hwbug = false;
7687
7688 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
3db1cd5c 7689 hwbug = true;
d1a3b737
MC		 7690
7691 if (tg3_4g_overflow_test(map, len))
3db1cd5c 7692 hwbug = true;
d1a3b737 7693
0f0d1510
MC		 7694 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7695 hwbug = true;
7696
d1a3b737 7697 if (tg3_40bit_overflow_test(tp, map, len))
3db1cd5c 7698 hwbug = true;
d1a3b737 7699
a4cb428d 7700 if (tp->dma_limit) {
b9e45482 7701 u32 prvidx = *entry;
e31aa987 7702 u32 tmp_flag = flags & ~TXD_FLAG_END;
a4cb428d
MC		 7703 while (len > tp->dma_limit && *budget) {
7704 u32 frag_len = tp->dma_limit;
7705 len -= tp->dma_limit;
e31aa987 7706
b9e45482
MC		 7707 /* Avoid the 8byte DMA problem */
7708 if (len <= 8) {
a4cb428d
MC		 7709 len += tp->dma_limit / 2;
7710 frag_len = tp->dma_limit / 2;
e31aa987
MC		 7711 }
7712
b9e45482
MC		 7713 tnapi->tx_buffers[*entry].fragmented = true;
7714
7715 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7716 frag_len, tmp_flag, mss, vlan);
7717 *budget -= 1;
7718 prvidx = *entry;
7719 *entry = NEXT_TX(*entry);
7720
e31aa987
MC		 7721 map += frag_len;
7722 }
7723
7724 if (len) {
7725 if (*budget) {
7726 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7727 len, flags, mss, vlan);
b9e45482 7728 *budget -= 1;
e31aa987
MC		 7729 *entry = NEXT_TX(*entry);
7730 } else {
3db1cd5c 7731 hwbug = true;
b9e45482 7732 tnapi->tx_buffers[prvidx].fragmented = false;
e31aa987
MC		 7733 }
7734 }
7735 } else {
84b67b27
MC		 7736 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7737 len, flags, mss, vlan);
e31aa987
MC		 7738 *entry = NEXT_TX(*entry);
7739 }
d1a3b737
MC		 7740
7741 return hwbug;
7742}
7743
0d681b27 7744static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
432aa7ed
MC		 7745{
7746 int i;
0d681b27 7747 struct sk_buff *skb;
df8944cf 7748 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
432aa7ed 7749
0d681b27
MC		 7750 skb = txb->skb;
7751 txb->skb = NULL;
7752
432aa7ed
MC		 7753 pci_unmap_single(tnapi->tp->pdev,
7754 dma_unmap_addr(txb, mapping),
7755 skb_headlen(skb),
7756 PCI_DMA_TODEVICE);
e01ee14d
MC		 7757
7758 while (txb->fragmented) {
7759 txb->fragmented = false;
7760 entry = NEXT_TX(entry);
7761 txb = &tnapi->tx_buffers[entry];
7762 }
7763
ba1142e4 7764 for (i = 0; i <= last; i++) {
9e903e08 7765 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
432aa7ed
MC		 7766
7767 entry = NEXT_TX(entry);
7768 txb = &tnapi->tx_buffers[entry];
7769
7770 pci_unmap_page(tnapi->tp->pdev,
7771 dma_unmap_addr(txb, mapping),
9e903e08 7772 skb_frag_size(frag), PCI_DMA_TODEVICE);
e01ee14d
MC		 7773
7774 while (txb->fragmented) {
7775 txb->fragmented = false;
7776 entry = NEXT_TX(entry);
7777 txb = &tnapi->tx_buffers[entry];
7778 }
432aa7ed
MC		 7779 }
7780}
7781
72f2afb8 7782/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4 7783static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
f7ff1987 7784 struct sk_buff **pskb,
84b67b27 7785 u32 *entry, u32 *budget,
92cd3a17 7786 u32 base_flags, u32 mss, u32 vlan)
1da177e4 7787{
24f4efd4 7788 struct tg3 *tp = tnapi->tp;
f7ff1987 7789 struct sk_buff *new_skb, *skb = *pskb;
c58ec932 7790 dma_addr_t new_addr = 0;
432aa7ed 7791 int ret = 0;
1da177e4 7792
4153577a 7793 if (tg3_asic_rev(tp) != ASIC_REV_5701)
41588ba1
MC		 7794 new_skb = skb_copy(skb, GFP_ATOMIC);
7795 else {
7796 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7797
7798 new_skb = skb_copy_expand(skb,
7799 skb_headroom(skb) + more_headroom,
7800 skb_tailroom(skb), GFP_ATOMIC);
7801 }
7802
1da177e4 7803 if (!new_skb) {
c58ec932
MC		 7804 ret = -1;
7805 } else {
7806 /* New SKB is guaranteed to be linear. */
f4188d8a
AD		 7807 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7808 PCI_DMA_TODEVICE);
7809 /* Make sure the mapping succeeded */
7810 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
f4188d8a 7811 dev_kfree_skb(new_skb);
c58ec932 7812 ret = -1;
c58ec932 7813 } else {
b9e45482
MC		 7814 u32 save_entry = *entry;
7815
92cd3a17
MC		 7816 base_flags |= TXD_FLAG_END;
7817
84b67b27
MC		 7818 tnapi->tx_buffers[*entry].skb = new_skb;
7819 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
432aa7ed
MC		 7820 mapping, new_addr);
7821
84b67b27 7822 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
d1a3b737
MC		 7823 new_skb->len, base_flags,
7824 mss, vlan)) {
ba1142e4 7825 tg3_tx_skb_unmap(tnapi, save_entry, -1);
d1a3b737
MC		 7826 dev_kfree_skb(new_skb);
7827 ret = -1;
7828 }
f4188d8a 7829 }
1da177e4
LT		 7830 }
7831
7832 dev_kfree_skb(skb);
f7ff1987 7833 *pskb = new_skb;
c58ec932 7834 return ret;
1da177e4
LT		 7835}
7836
2ffcc981 7837static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
52c0fd83
MC		 7838
7839/* Use GSO to workaround a rare TSO bug that may be triggered when the
7840 * TSO header is greater than 80 bytes.
7841 */
7842static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
7843{
7844 struct sk_buff *segs, *nskb;
f3f3f27e 7845 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 7846
7847 /* Estimate the number of fragments in the worst case */
f3f3f27e 7848 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 7849 netif_stop_queue(tp->dev);
f65aac16
MC		 7850
7851 /* netif_tx_stop_queue() must be done before checking
7852 * checking tx index in tg3_tx_avail() below, because in
7853 * tg3_tx(), we update tx index before checking for
7854 * netif_tx_queue_stopped().
7855 */
7856 smp_mb();
f3f3f27e 7857 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 7858 return NETDEV_TX_BUSY;
7859
7860 netif_wake_queue(tp->dev);
52c0fd83
MC		 7861 }
7862
7863 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 7864 if (IS_ERR(segs))
52c0fd83
MC		 7865 goto tg3_tso_bug_end;
7866
7867 do {
7868 nskb = segs;
7869 segs = segs->next;
7870 nskb->next = NULL;
2ffcc981 7871 tg3_start_xmit(nskb, tp->dev);
52c0fd83
MC		 7872 } while (segs);
7873
7874tg3_tso_bug_end:
7875 dev_kfree_skb(skb);
7876
7877 return NETDEV_TX_OK;
7878}
52c0fd83 7879
5a6f3074 7880/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
63c3a66f 7881 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
5a6f3074 7882 */
2ffcc981 7883static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 7884{
7885 struct tg3 *tp = netdev_priv(dev);
92cd3a17 7886 u32 len, entry, base_flags, mss, vlan = 0;
84b67b27 7887 u32 budget;
432aa7ed 7888 int i = -1, would_hit_hwbug;
90079ce8 7889 dma_addr_t mapping;
24f4efd4
MC		 7890 struct tg3_napi *tnapi;
7891 struct netdev_queue *txq;
432aa7ed 7892 unsigned int last;
f4188d8a 7893
24f4efd4
MC		 7894 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7895 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
63c3a66f 7896 if (tg3_flag(tp, ENABLE_TSS))
24f4efd4 7897 tnapi++;
1da177e4 7898
84b67b27
MC		 7899 budget = tg3_tx_avail(tnapi);
7900
00b70504 7901 /* We are running in BH disabled context with netif_tx_lock
bea3348e 7902 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 7903 * interrupt. Furthermore, IRQ processing runs lockless so we have
7904 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 7905 */
84b67b27 7906 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 7907 if (!netif_tx_queue_stopped(txq)) {
7908 netif_tx_stop_queue(txq);
1f064a87
SH		 7909
7910 /* This is a hard error, log it. */
5129c3a3
MC		 7911 netdev_err(dev,
7912 "BUG! Tx Ring full when queue awake!\n");
1f064a87 7913 }
1da177e4
LT		 7914 return NETDEV_TX_BUSY;
7915 }
7916
f3f3f27e 7917 entry = tnapi->tx_prod;
1da177e4 7918 base_flags = 0;
84fa7933 7919 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 7920 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 7921
be98da6a
MC		 7922 mss = skb_shinfo(skb)->gso_size;
7923 if (mss) {
eddc9ec5 7924 struct iphdr *iph;
34195c3d 7925 u32 tcp_opt_len, hdr_len;
1da177e4
LT		 7926
7927 if (skb_header_cloned(skb) &&
48855432
ED		 7928 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7929 goto drop;
1da177e4 7930
34195c3d 7931 iph = ip_hdr(skb);
ab6a5bb6 7932 tcp_opt_len = tcp_optlen(skb);
1da177e4 7933
a5a11955 7934 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
34195c3d 7935
a5a11955 7936 if (!skb_is_gso_v6(skb)) {
34195c3d
MC		 7937 iph->check = 0;
7938 iph->tot_len = htons(mss + hdr_len);
7939 }
7940
52c0fd83 7941 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
63c3a66f 7942 tg3_flag(tp, TSO_BUG))
de6f31eb 7943 return tg3_tso_bug(tp, skb);
52c0fd83 7944
1da177e4
LT		 7945 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7946 TXD_FLAG_CPU_POST_DMA);
7947
63c3a66f
JP		 7948 if (tg3_flag(tp, HW_TSO_1) ||
7949 tg3_flag(tp, HW_TSO_2) ||
7950 tg3_flag(tp, HW_TSO_3)) {
aa8223c7 7951 tcp_hdr(skb)->check = 0;
1da177e4 7952 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 7953 } else
7954 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7955 iph->daddr, 0,
7956 IPPROTO_TCP,
7957 0);
1da177e4 7958
63c3a66f 7959 if (tg3_flag(tp, HW_TSO_3)) {
615774fe
MC		 7960 mss |= (hdr_len & 0xc) << 12;
7961 if (hdr_len & 0x10)
7962 base_flags |= 0x00000010;
7963 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 7964 } else if (tg3_flag(tp, HW_TSO_2))
92c6b8d1 7965 mss |= hdr_len << 9;
63c3a66f 7966 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 7967 tg3_asic_rev(tp) == ASIC_REV_5705) {
eddc9ec5 7968 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7969 int tsflags;
7970
eddc9ec5 7971 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7972 mss |= (tsflags << 11);
7973 }
7974 } else {
eddc9ec5 7975 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7976 int tsflags;
7977
eddc9ec5 7978 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7979 base_flags |= tsflags << 12;
7980 }
7981 }
7982 }
bf933c80 7983
93a700a9
MC		 7984 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7985 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7986 base_flags |= TXD_FLAG_JMB_PKT;
7987
92cd3a17
MC		 7988 if (vlan_tx_tag_present(skb)) {
7989 base_flags |= TXD_FLAG_VLAN;
7990 vlan = vlan_tx_tag_get(skb);
7991 }
1da177e4 7992
fb4ce8ad
MC		 7993 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
7994 tg3_flag(tp, TX_TSTAMP_EN)) {
7995 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7996 base_flags |= TXD_FLAG_HWTSTAMP;
7997 }
7998
f4188d8a
AD		 7999 len = skb_headlen(skb);
8000
8001 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
48855432
ED		 8002 if (pci_dma_mapping_error(tp->pdev, mapping))
8003 goto drop;
8004
90079ce8 8005
f3f3f27e 8006 tnapi->tx_buffers[entry].skb = skb;
4e5e4f0d 8007 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 8008
8009 would_hit_hwbug = 0;
8010
63c3a66f 8011 if (tg3_flag(tp, 5701_DMA_BUG))
c58ec932 8012 would_hit_hwbug = 1;
1da177e4 8013
84b67b27 8014 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
d1a3b737 8015 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
ba1142e4 8016 mss, vlan)) {
d1a3b737 8017 would_hit_hwbug = 1;
ba1142e4 8018 } else if (skb_shinfo(skb)->nr_frags > 0) {
92cd3a17
MC		 8019 u32 tmp_mss = mss;
8020
8021 if (!tg3_flag(tp, HW_TSO_1) &&
8022 !tg3_flag(tp, HW_TSO_2) &&
8023 !tg3_flag(tp, HW_TSO_3))
8024 tmp_mss = 0;
8025
c5665a53
MC		 8026 /* Now loop through additional data
8027 * fragments, and queue them.
8028 */
1da177e4
LT		 8029 last = skb_shinfo(skb)->nr_frags - 1;
8030 for (i = 0; i <= last; i++) {
8031 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8032
9e903e08 8033 len = skb_frag_size(frag);
dc234d0b 8034 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
5d6bcdfe 8035 len, DMA_TO_DEVICE);
1da177e4 8036
f3f3f27e 8037 tnapi->tx_buffers[entry].skb = NULL;
4e5e4f0d 8038 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
f4188d8a 8039 mapping);
5d6bcdfe 8040 if (dma_mapping_error(&tp->pdev->dev, mapping))
f4188d8a 8041 goto dma_error;
1da177e4 8042
b9e45482
MC		 8043 if (!budget ||
8044 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
84b67b27
MC		 8045 len, base_flags |
8046 ((i == last) ? TXD_FLAG_END : 0),
b9e45482 8047 tmp_mss, vlan)) {
72f2afb8 8048 would_hit_hwbug = 1;
b9e45482
MC		 8049 break;
8050 }
1da177e4
LT		 8051 }
8052 }
8053
8054 if (would_hit_hwbug) {
0d681b27 8055 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
1da177e4
LT		 8056
8057 /* If the workaround fails due to memory/mapping
8058 * failure, silently drop this packet.
8059 */
84b67b27
MC		 8060 entry = tnapi->tx_prod;
8061 budget = tg3_tx_avail(tnapi);
f7ff1987 8062 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
84b67b27 8063 base_flags, mss, vlan))
48855432 8064 goto drop_nofree;
1da177e4
LT		 8065 }
8066
d515b450 8067 skb_tx_timestamp(skb);
5cb917bc 8068 netdev_tx_sent_queue(txq, skb->len);
d515b450 8069
6541b806
MC		 8070 /* Sync BD data before updating mailbox */
8071 wmb();
8072
1da177e4 8073 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 8074 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 8075
f3f3f27e
MC		 8076 tnapi->tx_prod = entry;
8077 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 8078 netif_tx_stop_queue(txq);
f65aac16
MC		 8079
8080 /* netif_tx_stop_queue() must be done before checking
8081 * checking tx index in tg3_tx_avail() below, because in
8082 * tg3_tx(), we update tx index before checking for
8083 * netif_tx_queue_stopped().
8084 */
8085 smp_mb();
f3f3f27e 8086 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 8087 netif_tx_wake_queue(txq);
51b91468 8088 }
1da177e4 8089
cdd0db05 8090 mmiowb();
1da177e4 8091 return NETDEV_TX_OK;
f4188d8a
AD		 8092
8093dma_error:
ba1142e4 8094 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
432aa7ed 8095 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
48855432
ED		 8096drop:
8097 dev_kfree_skb(skb);
8098drop_nofree:
8099 tp->tx_dropped++;
f4188d8a 8100 return NETDEV_TX_OK;
1da177e4
LT		 8101}
8102
6e01b20b
MC		 8103static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8104{
8105 if (enable) {
8106 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8107 MAC_MODE_PORT_MODE_MASK);
8108
8109 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8110
8111 if (!tg3_flag(tp, 5705_PLUS))
8112 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8113
8114 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8115 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8116 else
8117 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8118 } else {
8119 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8120
8121 if (tg3_flag(tp, 5705_PLUS) ||
8122 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
4153577a 8123 tg3_asic_rev(tp) == ASIC_REV_5700)
6e01b20b
MC		 8124 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8125 }
8126
8127 tw32(MAC_MODE, tp->mac_mode);
8128 udelay(40);
8129}
8130
941ec90f 8131static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
5e5a7f37 8132{
941ec90f 8133 u32 val, bmcr, mac_mode, ptest = 0;
5e5a7f37
MC		 8134
8135 tg3_phy_toggle_apd(tp, false);
953c96e0 8136 tg3_phy_toggle_automdix(tp, false);
5e5a7f37 8137
941ec90f
MC		 8138 if (extlpbk && tg3_phy_set_extloopbk(tp))
8139 return -EIO;
8140
8141 bmcr = BMCR_FULLDPLX;
5e5a7f37
MC		 8142 switch (speed) {
8143 case SPEED_10:
8144 break;
8145 case SPEED_100:
8146 bmcr |= BMCR_SPEED100;
8147 break;
8148 case SPEED_1000:
8149 default:
8150 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8151 speed = SPEED_100;
8152 bmcr |= BMCR_SPEED100;
8153 } else {
8154 speed = SPEED_1000;
8155 bmcr |= BMCR_SPEED1000;
8156 }
8157 }
8158
941ec90f
MC		 8159 if (extlpbk) {
8160 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8161 tg3_readphy(tp, MII_CTRL1000, &val);
8162 val |= CTL1000_AS_MASTER |
8163 CTL1000_ENABLE_MASTER;
8164 tg3_writephy(tp, MII_CTRL1000, val);
8165 } else {
8166 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8167 MII_TG3_FET_PTEST_TRIM_2;
8168 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8169 }
8170 } else
8171 bmcr |= BMCR_LOOPBACK;
8172
5e5a7f37
MC		 8173 tg3_writephy(tp, MII_BMCR, bmcr);
8174
8175 /* The write needs to be flushed for the FETs */
8176 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8177 tg3_readphy(tp, MII_BMCR, &bmcr);
8178
8179 udelay(40);
8180
8181 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a 8182 tg3_asic_rev(tp) == ASIC_REV_5785) {
941ec90f 8183 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
5e5a7f37
MC		 8184 MII_TG3_FET_PTEST_FRC_TX_LINK |
8185 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8186
8187 /* The write needs to be flushed for the AC131 */
8188 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8189 }
8190
8191 /* Reset to prevent losing 1st rx packet intermittently */
8192 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8193 tg3_flag(tp, 5780_CLASS)) {
8194 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8195 udelay(10);
8196 tw32_f(MAC_RX_MODE, tp->rx_mode);
8197 }
8198
8199 mac_mode = tp->mac_mode &
8200 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8201 if (speed == SPEED_1000)
8202 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8203 else
8204 mac_mode |= MAC_MODE_PORT_MODE_MII;
8205
4153577a 8206 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5e5a7f37
MC		 8207 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8208
8209 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8210 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8211 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8212 mac_mode |= MAC_MODE_LINK_POLARITY;
8213
8214 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8215 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8216 }
8217
8218 tw32(MAC_MODE, mac_mode);
8219 udelay(40);
941ec90f
MC		 8220
8221 return 0;
5e5a7f37
MC		 8222}
8223
c8f44aff 8224static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
06c03c02
MB		 8225{
8226 struct tg3 *tp = netdev_priv(dev);
8227
8228 if (features & NETIF_F_LOOPBACK) {
8229 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8230 return;
8231
06c03c02 8232 spin_lock_bh(&tp->lock);
6e01b20b 8233 tg3_mac_loopback(tp, true);
06c03c02
MB		 8234 netif_carrier_on(tp->dev);
8235 spin_unlock_bh(&tp->lock);
8236 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8237 } else {
8238 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8239 return;
8240
06c03c02 8241 spin_lock_bh(&tp->lock);
6e01b20b 8242 tg3_mac_loopback(tp, false);
06c03c02 8243 /* Force link status check */
953c96e0 8244 tg3_setup_phy(tp, true);
06c03c02
MB		 8245 spin_unlock_bh(&tp->lock);
8246 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8247 }
8248}
8249
c8f44aff
MM		 8250static netdev_features_t tg3_fix_features(struct net_device *dev,
8251 netdev_features_t features)
dc668910
MM		 8252{
8253 struct tg3 *tp = netdev_priv(dev);
8254
63c3a66f 8255 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
dc668910
MM		 8256 features &= ~NETIF_F_ALL_TSO;
8257
8258 return features;
8259}
8260
c8f44aff 8261static int tg3_set_features(struct net_device *dev, netdev_features_t features)
06c03c02 8262{
c8f44aff 8263 netdev_features_t changed = dev->features ^ features;
06c03c02
MB		 8264
8265 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8266 tg3_set_loopback(dev, features);
8267
8268 return 0;
8269}
8270
21f581a5
MC		 8271static void tg3_rx_prodring_free(struct tg3 *tp,
8272 struct tg3_rx_prodring_set *tpr)
1da177e4 8273{
1da177e4
LT		 8274 int i;
8275
8fea32b9 8276 if (tpr != &tp->napi[0].prodring) {
b196c7e4 8277 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
2c49a44d 8278 i = (i + 1) & tp->rx_std_ring_mask)
9205fd9c 8279 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
b196c7e4
MC		 8280 tp->rx_pkt_map_sz);
8281
63c3a66f 8282 if (tg3_flag(tp, JUMBO_CAPABLE)) {
b196c7e4
MC		 8283 for (i = tpr->rx_jmb_cons_idx;
8284 i != tpr->rx_jmb_prod_idx;
2c49a44d 8285 i = (i + 1) & tp->rx_jmb_ring_mask) {
9205fd9c 8286 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
b196c7e4
MC		 8287 TG3_RX_JMB_MAP_SZ);
8288 }
8289 }
8290
2b2cdb65 8291 return;
b196c7e4 8292 }
1da177e4 8293
2c49a44d 8294 for (i = 0; i <= tp->rx_std_ring_mask; i++)
9205fd9c 8295 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
2b2cdb65 8296 tp->rx_pkt_map_sz);
1da177e4 8297
63c3a66f 8298 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8299 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
9205fd9c 8300 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
2b2cdb65 8301 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 8302 }
8303}
8304
c6cdf436 8305/* Initialize rx rings for packet processing.
1da177e4
LT		 8306 *
8307 * The chip has been shut down and the driver detached from
8308 * the networking, so no interrupts or new tx packets will
8309 * end up in the driver. tp->{tx,}lock are held and thus
8310 * we may not sleep.
8311 */
21f581a5
MC		 8312static int tg3_rx_prodring_alloc(struct tg3 *tp,
8313 struct tg3_rx_prodring_set *tpr)
1da177e4 8314{
287be12e 8315 u32 i, rx_pkt_dma_sz;
1da177e4 8316
b196c7e4
MC		 8317 tpr->rx_std_cons_idx = 0;
8318 tpr->rx_std_prod_idx = 0;
8319 tpr->rx_jmb_cons_idx = 0;
8320 tpr->rx_jmb_prod_idx = 0;
8321
8fea32b9 8322 if (tpr != &tp->napi[0].prodring) {
2c49a44d
MC		 8323 memset(&tpr->rx_std_buffers[0], 0,
8324 TG3_RX_STD_BUFF_RING_SIZE(tp));
48035728 8325 if (tpr->rx_jmb_buffers)
2b2cdb65 8326 memset(&tpr->rx_jmb_buffers[0], 0,
2c49a44d 8327 TG3_RX_JMB_BUFF_RING_SIZE(tp));
2b2cdb65
MC		 8328 goto done;
8329 }
8330
1da177e4 8331 /* Zero out all descriptors. */
2c49a44d 8332 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
1da177e4 8333
287be12e 8334 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
63c3a66f 8335 if (tg3_flag(tp, 5780_CLASS) &&
287be12e
MC		 8336 tp->dev->mtu > ETH_DATA_LEN)
8337 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8338 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 8339
1da177e4
LT		 8340 /* Initialize invariants of the rings, we only set this
8341 * stuff once. This works because the card does not
8342 * write into the rx buffer posting rings.
8343 */
2c49a44d 8344 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
1da177e4
LT		 8345 struct tg3_rx_buffer_desc *rxd;
8346
21f581a5 8347 rxd = &tpr->rx_std[i];
287be12e 8348 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 8349 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8350 rxd->opaque = (RXD_OPAQUE_RING_STD |
8351 (i << RXD_OPAQUE_INDEX_SHIFT));
8352 }
8353
1da177e4
LT		 8354 /* Now allocate fresh SKBs for each rx ring. */
8355 for (i = 0; i < tp->rx_pending; i++) {
8d4057a9
ED		 8356 unsigned int frag_size;
8357
8358 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8359 &frag_size) < 0) {
5129c3a3
MC		 8360 netdev_warn(tp->dev,
8361 "Using a smaller RX standard ring. Only "
8362 "%d out of %d buffers were allocated "
8363 "successfully\n", i, tp->rx_pending);
32d8c572 8364 if (i == 0)
cf7a7298 8365 goto initfail;
32d8c572 8366 tp->rx_pending = i;
1da177e4 8367 break;
32d8c572 8368 }
1da177e4
LT		 8369 }
8370
63c3a66f 8371 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
cf7a7298
MC		 8372 goto done;
8373
2c49a44d 8374 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
cf7a7298 8375
63c3a66f 8376 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
0d86df80 8377 goto done;
cf7a7298 8378
2c49a44d 8379 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
0d86df80
MC		 8380 struct tg3_rx_buffer_desc *rxd;
8381
8382 rxd = &tpr->rx_jmb[i].std;
8383 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8384 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8385 RXD_FLAG_JUMBO;
8386 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8387 (i << RXD_OPAQUE_INDEX_SHIFT));
8388 }
8389
8390 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8d4057a9
ED		 8391 unsigned int frag_size;
8392
8393 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8394 &frag_size) < 0) {
5129c3a3
MC		 8395 netdev_warn(tp->dev,
8396 "Using a smaller RX jumbo ring. Only %d "
8397 "out of %d buffers were allocated "
8398 "successfully\n", i, tp->rx_jumbo_pending);
0d86df80
MC		 8399 if (i == 0)
8400 goto initfail;
8401 tp->rx_jumbo_pending = i;
8402 break;
1da177e4
LT		 8403 }
8404 }
cf7a7298
MC		 8405
8406done:
32d8c572 8407 return 0;
cf7a7298
MC		 8408
8409initfail:
21f581a5 8410 tg3_rx_prodring_free(tp, tpr);
cf7a7298 8411 return -ENOMEM;
1da177e4
LT		 8412}
8413
21f581a5
MC		 8414static void tg3_rx_prodring_fini(struct tg3 *tp,
8415 struct tg3_rx_prodring_set *tpr)
1da177e4 8416{
21f581a5
MC		 8417 kfree(tpr->rx_std_buffers);
8418 tpr->rx_std_buffers = NULL;
8419 kfree(tpr->rx_jmb_buffers);
8420 tpr->rx_jmb_buffers = NULL;
8421 if (tpr->rx_std) {
4bae65c8
MC		 8422 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8423 tpr->rx_std, tpr->rx_std_mapping);
21f581a5 8424 tpr->rx_std = NULL;
1da177e4 8425 }
21f581a5 8426 if (tpr->rx_jmb) {
4bae65c8
MC		 8427 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8428 tpr->rx_jmb, tpr->rx_jmb_mapping);
21f581a5 8429 tpr->rx_jmb = NULL;
1da177e4 8430 }
cf7a7298
MC		 8431}
8432
21f581a5
MC		 8433static int tg3_rx_prodring_init(struct tg3 *tp,
8434 struct tg3_rx_prodring_set *tpr)
cf7a7298 8435{
2c49a44d
MC		 8436 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8437 GFP_KERNEL);
21f581a5 8438 if (!tpr->rx_std_buffers)
cf7a7298
MC		 8439 return -ENOMEM;
8440
4bae65c8
MC		 8441 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8442 TG3_RX_STD_RING_BYTES(tp),
8443 &tpr->rx_std_mapping,
8444 GFP_KERNEL);
21f581a5 8445 if (!tpr->rx_std)
cf7a7298
MC		 8446 goto err_out;
8447
63c3a66f 8448 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8449 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
21f581a5
MC		 8450 GFP_KERNEL);
8451 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 8452 goto err_out;
8453
4bae65c8
MC		 8454 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8455 TG3_RX_JMB_RING_BYTES(tp),
8456 &tpr->rx_jmb_mapping,
8457 GFP_KERNEL);
21f581a5 8458 if (!tpr->rx_jmb)
cf7a7298
MC		 8459 goto err_out;
8460 }
8461
8462 return 0;
8463
8464err_out:
21f581a5 8465 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 8466 return -ENOMEM;
8467}
8468
8469/* Free up pending packets in all rx/tx rings.
8470 *
8471 * The chip has been shut down and the driver detached from
8472 * the networking, so no interrupts or new tx packets will
8473 * end up in the driver. tp->{tx,}lock is not held and we are not
8474 * in an interrupt context and thus may sleep.
8475 */
8476static void tg3_free_rings(struct tg3 *tp)
8477{
f77a6a8e 8478 int i, j;
cf7a7298 8479
f77a6a8e
MC		 8480 for (j = 0; j < tp->irq_cnt; j++) {
8481 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 8482
8fea32b9 8483 tg3_rx_prodring_free(tp, &tnapi->prodring);
b28f6428 8484
0c1d0e2b
MC		 8485 if (!tnapi->tx_buffers)
8486 continue;
8487
0d681b27
MC		 8488 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8489 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
cf7a7298 8490
0d681b27 8491 if (!skb)
f77a6a8e 8492 continue;
cf7a7298 8493
ba1142e4
MC		 8494 tg3_tx_skb_unmap(tnapi, i,
8495 skb_shinfo(skb)->nr_frags - 1);
f77a6a8e
MC		 8496
8497 dev_kfree_skb_any(skb);
8498 }
5cb917bc 8499 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
2b2cdb65 8500 }
cf7a7298
MC		 8501}
8502
8503/* Initialize tx/rx rings for packet processing.
8504 *
8505 * The chip has been shut down and the driver detached from
8506 * the networking, so no interrupts or new tx packets will
8507 * end up in the driver. tp->{tx,}lock are held and thus
8508 * we may not sleep.
8509 */
8510static int tg3_init_rings(struct tg3 *tp)
8511{
f77a6a8e 8512 int i;
72334482 8513
cf7a7298
MC		 8514 /* Free up all the SKBs. */
8515 tg3_free_rings(tp);
8516
f77a6a8e
MC		 8517 for (i = 0; i < tp->irq_cnt; i++) {
8518 struct tg3_napi *tnapi = &tp->napi[i];
8519
8520 tnapi->last_tag = 0;
8521 tnapi->last_irq_tag = 0;
8522 tnapi->hw_status->status = 0;
8523 tnapi->hw_status->status_tag = 0;
8524 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 8525
f77a6a8e
MC		 8526 tnapi->tx_prod = 0;
8527 tnapi->tx_cons = 0;
0c1d0e2b
MC		 8528 if (tnapi->tx_ring)
8529 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 8530
8531 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 8532 if (tnapi->rx_rcb)
8533 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 8534
8fea32b9 8535 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
e4af1af9 8536 tg3_free_rings(tp);
2b2cdb65 8537 return -ENOMEM;
e4af1af9 8538 }
f77a6a8e 8539 }
72334482 8540
2b2cdb65 8541 return 0;
cf7a7298
MC		 8542}
8543
49a359e3 8544static void tg3_mem_tx_release(struct tg3 *tp)
cf7a7298 8545{
f77a6a8e 8546 int i;
898a56f8 8547
49a359e3 8548 for (i = 0; i < tp->irq_max; i++) {
f77a6a8e
MC		 8549 struct tg3_napi *tnapi = &tp->napi[i];
8550
8551 if (tnapi->tx_ring) {
4bae65c8 8552 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
f77a6a8e
MC		 8553 tnapi->tx_ring, tnapi->tx_desc_mapping);
8554 tnapi->tx_ring = NULL;
8555 }
8556
8557 kfree(tnapi->tx_buffers);
8558 tnapi->tx_buffers = NULL;
49a359e3
MC		 8559 }
8560}
f77a6a8e 8561
49a359e3
MC		 8562static int tg3_mem_tx_acquire(struct tg3 *tp)
8563{
8564 int i;
8565 struct tg3_napi *tnapi = &tp->napi[0];
8566
8567 /* If multivector TSS is enabled, vector 0 does not handle
8568 * tx interrupts. Don't allocate any resources for it.
8569 */
8570 if (tg3_flag(tp, ENABLE_TSS))
8571 tnapi++;
8572
8573 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8574 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8575 TG3_TX_RING_SIZE, GFP_KERNEL);
8576 if (!tnapi->tx_buffers)
8577 goto err_out;
8578
8579 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8580 TG3_TX_RING_BYTES,
8581 &tnapi->tx_desc_mapping,
8582 GFP_KERNEL);
8583 if (!tnapi->tx_ring)
8584 goto err_out;
8585 }
8586
8587 return 0;
8588
8589err_out:
8590 tg3_mem_tx_release(tp);
8591 return -ENOMEM;
8592}
8593
8594static void tg3_mem_rx_release(struct tg3 *tp)
8595{
8596 int i;
8597
8598 for (i = 0; i < tp->irq_max; i++) {
8599 struct tg3_napi *tnapi = &tp->napi[i];
f77a6a8e 8600
8fea32b9
MC		 8601 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8602
49a359e3
MC		 8603 if (!tnapi->rx_rcb)
8604 continue;
8605
8606 dma_free_coherent(&tp->pdev->dev,
8607 TG3_RX_RCB_RING_BYTES(tp),
8608 tnapi->rx_rcb,
8609 tnapi->rx_rcb_mapping);
8610 tnapi->rx_rcb = NULL;
8611 }
8612}
8613
8614static int tg3_mem_rx_acquire(struct tg3 *tp)
8615{
8616 unsigned int i, limit;
8617
8618 limit = tp->rxq_cnt;
8619
8620 /* If RSS is enabled, we need a (dummy) producer ring
8621 * set on vector zero. This is the true hw prodring.
8622 */
8623 if (tg3_flag(tp, ENABLE_RSS))
8624 limit++;
8625
8626 for (i = 0; i < limit; i++) {
8627 struct tg3_napi *tnapi = &tp->napi[i];
8628
8629 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8630 goto err_out;
8631
8632 /* If multivector RSS is enabled, vector 0
8633 * does not handle rx or tx interrupts.
8634 * Don't allocate any resources for it.
8635 */
8636 if (!i && tg3_flag(tp, ENABLE_RSS))
8637 continue;
8638
ede23fa8
JP		 8639 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8640 TG3_RX_RCB_RING_BYTES(tp),
8641 &tnapi->rx_rcb_mapping,
8642 GFP_KERNEL);
49a359e3
MC		 8643 if (!tnapi->rx_rcb)
8644 goto err_out;
49a359e3
MC		 8645 }
8646
8647 return 0;
8648
8649err_out:
8650 tg3_mem_rx_release(tp);
8651 return -ENOMEM;
8652}
8653
8654/*
8655 * Must not be invoked with interrupt sources disabled and
8656 * the hardware shutdown down.
8657 */
8658static void tg3_free_consistent(struct tg3 *tp)
8659{
8660 int i;
8661
8662 for (i = 0; i < tp->irq_cnt; i++) {
8663 struct tg3_napi *tnapi = &tp->napi[i];
8664
f77a6a8e 8665 if (tnapi->hw_status) {
4bae65c8
MC		 8666 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8667 tnapi->hw_status,
8668 tnapi->status_mapping);
f77a6a8e
MC		 8669 tnapi->hw_status = NULL;
8670 }
1da177e4 8671 }
f77a6a8e 8672
49a359e3
MC		 8673 tg3_mem_rx_release(tp);
8674 tg3_mem_tx_release(tp);
8675
1da177e4 8676 if (tp->hw_stats) {
4bae65c8
MC		 8677 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8678 tp->hw_stats, tp->stats_mapping);
1da177e4
LT		 8679 tp->hw_stats = NULL;
8680 }
8681}
8682
8683/*
8684 * Must not be invoked with interrupt sources disabled and
8685 * the hardware shutdown down. Can sleep.
8686 */
8687static int tg3_alloc_consistent(struct tg3 *tp)
8688{
f77a6a8e 8689 int i;
898a56f8 8690
ede23fa8
JP		 8691 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8692 sizeof(struct tg3_hw_stats),
8693 &tp->stats_mapping, GFP_KERNEL);
f77a6a8e 8694 if (!tp->hw_stats)
1da177e4
LT		 8695 goto err_out;
8696
f77a6a8e
MC		 8697 for (i = 0; i < tp->irq_cnt; i++) {
8698 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 8699 struct tg3_hw_status *sblk;
1da177e4 8700
ede23fa8
JP		 8701 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8702 TG3_HW_STATUS_SIZE,
8703 &tnapi->status_mapping,
8704 GFP_KERNEL);
f77a6a8e
MC		 8705 if (!tnapi->hw_status)
8706 goto err_out;
898a56f8 8707
8d9d7cfc
MC		 8708 sblk = tnapi->hw_status;
8709
49a359e3 8710 if (tg3_flag(tp, ENABLE_RSS)) {
86449944 8711 u16 *prodptr = NULL;
8fea32b9 8712
49a359e3
MC		 8713 /*
8714 * When RSS is enabled, the status block format changes
8715 * slightly. The "rx_jumbo_consumer", "reserved",
8716 * and "rx_mini_consumer" members get mapped to the
8717 * other three rx return ring producer indexes.
8718 */
8719 switch (i) {
8720 case 1:
8721 prodptr = &sblk->idx[0].rx_producer;
8722 break;
8723 case 2:
8724 prodptr = &sblk->rx_jumbo_consumer;
8725 break;
8726 case 3:
8727 prodptr = &sblk->reserved;
8728 break;
8729 case 4:
8730 prodptr = &sblk->rx_mini_consumer;
f891ea16
MC		 8731 break;
8732 }
49a359e3
MC		 8733 tnapi->rx_rcb_prod_idx = prodptr;
8734 } else {
8d9d7cfc 8735 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8d9d7cfc 8736 }
f77a6a8e 8737 }
1da177e4 8738
49a359e3
MC		 8739 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8740 goto err_out;
8741
1da177e4
LT		 8742 return 0;
8743
8744err_out:
8745 tg3_free_consistent(tp);
8746 return -ENOMEM;
8747}
8748
8749#define MAX_WAIT_CNT 1000
8750
8751/* To stop a block, clear the enable bit and poll till it
8752 * clears. tp->lock is held.
8753 */
953c96e0 8754static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
1da177e4
LT		 8755{
8756 unsigned int i;
8757 u32 val;
8758
63c3a66f 8759 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 8760 switch (ofs) {
8761 case RCVLSC_MODE:
8762 case DMAC_MODE:
8763 case MBFREE_MODE:
8764 case BUFMGR_MODE:
8765 case MEMARB_MODE:
8766 /* We can't enable/disable these bits of the
8767 * 5705/5750, just say success.
8768 */
8769 return 0;
8770
8771 default:
8772 break;
855e1111 8773 }
1da177e4
LT		 8774 }
8775
8776 val = tr32(ofs);
8777 val &= ~enable_bit;
8778 tw32_f(ofs, val);
8779
8780 for (i = 0; i < MAX_WAIT_CNT; i++) {
6d446ec3
GS		 8781 if (pci_channel_offline(tp->pdev)) {
8782 dev_err(&tp->pdev->dev,
8783 "tg3_stop_block device offline, "
8784 "ofs=%lx enable_bit=%x\n",
8785 ofs, enable_bit);
8786 return -ENODEV;
8787 }
8788
1da177e4
LT		 8789 udelay(100);
8790 val = tr32(ofs);
8791 if ((val & enable_bit) == 0)
8792 break;
8793 }
8794
b3b7d6be 8795 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 8796 dev_err(&tp->pdev->dev,
8797 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8798 ofs, enable_bit);
1da177e4
LT		 8799 return -ENODEV;
8800 }
8801
8802 return 0;
8803}
8804
8805/* tp->lock is held. */
953c96e0 8806static int tg3_abort_hw(struct tg3 *tp, bool silent)
1da177e4
LT		 8807{
8808 int i, err;
8809
8810 tg3_disable_ints(tp);
8811
6d446ec3
GS		 8812 if (pci_channel_offline(tp->pdev)) {
8813 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8814 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8815 err = -ENODEV;
8816 goto err_no_dev;
8817 }
8818
1da177e4
LT		 8819 tp->rx_mode &= ~RX_MODE_ENABLE;
8820 tw32_f(MAC_RX_MODE, tp->rx_mode);
8821 udelay(10);
8822
b3b7d6be
DM		 8823 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8824 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8825 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8826 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8827 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8828 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8829
8830 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8831 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8832 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8833 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8834 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8835 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8836 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 8837
8838 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8839 tw32_f(MAC_MODE, tp->mac_mode);
8840 udelay(40);
8841
8842 tp->tx_mode &= ~TX_MODE_ENABLE;
8843 tw32_f(MAC_TX_MODE, tp->tx_mode);
8844
8845 for (i = 0; i < MAX_WAIT_CNT; i++) {
8846 udelay(100);
8847 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8848 break;
8849 }
8850 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 8851 dev_err(&tp->pdev->dev,
8852 "%s timed out, TX_MODE_ENABLE will not clear "
8853 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 8854 err |= -ENODEV;
1da177e4
LT		 8855 }
8856
e6de8ad1 8857 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 8858 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8859 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 8860
8861 tw32(FTQ_RESET, 0xffffffff);
8862 tw32(FTQ_RESET, 0x00000000);
8863
b3b7d6be
DM		 8864 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8865 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 8866
6d446ec3 8867err_no_dev:
f77a6a8e
MC		 8868 for (i = 0; i < tp->irq_cnt; i++) {
8869 struct tg3_napi *tnapi = &tp->napi[i];
8870 if (tnapi->hw_status)
8871 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8872 }
1da177e4 8873
1da177e4
LT		 8874 return err;
8875}
8876
ee6a99b5
MC		 8877/* Save PCI command register before chip reset */
8878static void tg3_save_pci_state(struct tg3 *tp)
8879{
8a6eac90 8880 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 8881}
8882
8883/* Restore PCI state after chip reset */
8884static void tg3_restore_pci_state(struct tg3 *tp)
8885{
8886 u32 val;
8887
8888 /* Re-enable indirect register accesses. */
8889 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8890 tp->misc_host_ctrl);
8891
8892 /* Set MAX PCI retry to zero. */
8893 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4153577a 8894 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 8895 tg3_flag(tp, PCIX_MODE))
ee6a99b5 8896 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9 8897 /* Allow reads and writes to the APE register and memory space. */
63c3a66f 8898 if (tg3_flag(tp, ENABLE_APE))
0d3031d9 8899 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 8900 PCISTATE_ALLOW_APE_SHMEM_WR |
8901 PCISTATE_ALLOW_APE_PSPACE_WR;
ee6a99b5
MC		 8902 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8903
8a6eac90 8904 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 8905
2c55a3d0
MC		 8906 if (!tg3_flag(tp, PCI_EXPRESS)) {
8907 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8908 tp->pci_cacheline_sz);
8909 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8910 tp->pci_lat_timer);
114342f2 8911 }
5f5c51e3 8912
ee6a99b5 8913 /* Make sure PCI-X relaxed ordering bit is clear. */
63c3a66f 8914 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 8915 u16 pcix_cmd;
8916
8917 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8918 &pcix_cmd);
8919 pcix_cmd &= ~PCI_X_CMD_ERO;
8920 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8921 pcix_cmd);
8922 }
ee6a99b5 8923
63c3a66f 8924 if (tg3_flag(tp, 5780_CLASS)) {
ee6a99b5
MC		 8925
8926 /* Chip reset on 5780 will reset MSI enable bit,
8927 * so need to restore it.
8928 */
63c3a66f 8929 if (tg3_flag(tp, USING_MSI)) {
ee6a99b5
MC		 8930 u16 ctrl;
8931
8932 pci_read_config_word(tp->pdev,
8933 tp->msi_cap + PCI_MSI_FLAGS,
8934 &ctrl);
8935 pci_write_config_word(tp->pdev,
8936 tp->msi_cap + PCI_MSI_FLAGS,
8937 ctrl | PCI_MSI_FLAGS_ENABLE);
8938 val = tr32(MSGINT_MODE);
8939 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8940 }
8941 }
8942}
8943
f82995b6
NS		 8944static void tg3_override_clk(struct tg3 *tp)
8945{
8946 u32 val;
8947
8948 switch (tg3_asic_rev(tp)) {
8949 case ASIC_REV_5717:
8950 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8951 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
8952 TG3_CPMU_MAC_ORIDE_ENABLE);
8953 break;
8954
8955 case ASIC_REV_5719:
8956 case ASIC_REV_5720:
8957 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8958 break;
8959
8960 default:
8961 return;
8962 }
8963}
8964
8965static void tg3_restore_clk(struct tg3 *tp)
8966{
8967 u32 val;
8968
8969 switch (tg3_asic_rev(tp)) {
8970 case ASIC_REV_5717:
8971 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8972 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
8973 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
8974 break;
8975
8976 case ASIC_REV_5719:
8977 case ASIC_REV_5720:
8978 val = tr32(TG3_CPMU_CLCK_ORIDE);
8979 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8980 break;
8981
8982 default:
8983 return;
8984 }
8985}
8986
1da177e4
LT		 8987/* tp->lock is held. */
8988static int tg3_chip_reset(struct tg3 *tp)
8989{
8990 u32 val;
1ee582d8 8991 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 8992 int i, err;
1da177e4 8993
8496e85c
RW		 8994 if (!pci_device_is_present(tp->pdev))
8995 return -ENODEV;
8996
f49639e6
DM		 8997 tg3_nvram_lock(tp);
8998
77b483f1
MC		 8999 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9000
f49639e6
DM		 9001 /* No matching tg3_nvram_unlock() after this because
9002 * chip reset below will undo the nvram lock.
9003 */
9004 tp->nvram_lock_cnt = 0;
1da177e4 9005
ee6a99b5
MC		 9006 /* GRC_MISC_CFG core clock reset will clear the memory
9007 * enable bit in PCI register 4 and the MSI enable bit
9008 * on some chips, so we save relevant registers here.
9009 */
9010 tg3_save_pci_state(tp);
9011
4153577a 9012 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
63c3a66f 9013 tg3_flag(tp, 5755_PLUS))
d9ab5ad1
MC		 9014 tw32(GRC_FASTBOOT_PC, 0);
9015
1da177e4
LT		 9016 /*
9017 * We must avoid the readl() that normally takes place.
9018 * It locks machines, causes machine checks, and other
9019 * fun things. So, temporarily disable the 5701
9020 * hardware workaround, while we do the reset.
9021 */
1ee582d8
MC		 9022 write_op = tp->write32;
9023 if (write_op == tg3_write_flush_reg32)
9024 tp->write32 = tg3_write32;
1da177e4 9025
d18edcb2
MC		 9026 /* Prevent the irq handler from reading or writing PCI registers
9027 * during chip reset when the memory enable bit in the PCI command
9028 * register may be cleared. The chip does not generate interrupt
9029 * at this time, but the irq handler may still be called due to irq
9030 * sharing or irqpoll.
9031 */
63c3a66f 9032 tg3_flag_set(tp, CHIP_RESETTING);
f77a6a8e
MC		 9033 for (i = 0; i < tp->irq_cnt; i++) {
9034 struct tg3_napi *tnapi = &tp->napi[i];
9035 if (tnapi->hw_status) {
9036 tnapi->hw_status->status = 0;
9037 tnapi->hw_status->status_tag = 0;
9038 }
9039 tnapi->last_tag = 0;
9040 tnapi->last_irq_tag = 0;
b8fa2f3a 9041 }
d18edcb2 9042 smp_mb();
4f125f42
MC		 9043
9044 for (i = 0; i < tp->irq_cnt; i++)
9045 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 9046
4153577a 9047 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
255ca311
MC		 9048 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9049 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9050 }
9051
1da177e4
LT		 9052 /* do the reset */
9053 val = GRC_MISC_CFG_CORECLK_RESET;
9054
63c3a66f 9055 if (tg3_flag(tp, PCI_EXPRESS)) {
88075d91 9056 /* Force PCIe 1.0a mode */
4153577a 9057 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9058 !tg3_flag(tp, 57765_PLUS) &&
88075d91
MC		 9059 tr32(TG3_PCIE_PHY_TSTCTL) ==
9060 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9061 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9062
4153577a 9063 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
1da177e4
LT		 9064 tw32(GRC_MISC_CFG, (1 << 29));
9065 val |= (1 << 29);
9066 }
9067 }
9068
4153577a 9069 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 9070 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9071 tw32(GRC_VCPU_EXT_CTRL,
9072 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9073 }
9074
f82995b6
NS		 9075 /* Set the clock to the highest frequency to avoid timeouts. With link
9076 * aware mode, the clock speed could be slow and bootcode does not
9077 * complete within the expected time. Override the clock to allow the
9078 * bootcode to finish sooner and then restore it.
9079 */
9080 tg3_override_clk(tp);
9081
f37500d3 9082 /* Manage gphy power for all CPMU absent PCIe devices. */
63c3a66f 9083 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
1da177e4 9084 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
f37500d3 9085
1da177e4
LT		 9086 tw32(GRC_MISC_CFG, val);
9087
1ee582d8
MC		 9088 /* restore 5701 hardware bug workaround write method */
9089 tp->write32 = write_op;
1da177e4
LT		 9090
9091 /* Unfortunately, we have to delay before the PCI read back.
9092 * Some 575X chips even will not respond to a PCI cfg access
9093 * when the reset command is given to the chip.
9094 *
9095 * How do these hardware designers expect things to work
9096 * properly if the PCI write is posted for a long period
9097 * of time? It is always necessary to have some method by
9098 * which a register read back can occur to push the write
9099 * out which does the reset.
9100 *
9101 * For most tg3 variants the trick below was working.
9102 * Ho hum...
9103 */
9104 udelay(120);
9105
9106 /* Flush PCI posted writes. The normal MMIO registers
9107 * are inaccessible at this time so this is the only
9108 * way to make this reliably (actually, this is no longer
9109 * the case, see above). I tried to use indirect
9110 * register read/write but this upset some 5701 variants.
9111 */
9112 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9113
9114 udelay(120);
9115
0f49bfbd 9116 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
e7126997
MC		 9117 u16 val16;
9118
4153577a 9119 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
86449944 9120 int j;
1da177e4
LT		 9121 u32 cfg_val;
9122
9123 /* Wait for link training to complete. */
86449944 9124 for (j = 0; j < 5000; j++)
1da177e4
LT		 9125 udelay(100);
9126
9127 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9128 pci_write_config_dword(tp->pdev, 0xc4,
9129 cfg_val | (1 << 15));
9130 }
5e7dfd0f 9131
e7126997 9132 /* Clear the "no snoop" and "relaxed ordering" bits. */
0f49bfbd 9133 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
e7126997
MC		 9134 /*
9135 * Older PCIe devices only support the 128 byte
9136 * MPS setting. Enforce the restriction.
5e7dfd0f 9137 */
63c3a66f 9138 if (!tg3_flag(tp, CPMU_PRESENT))
0f49bfbd
JL		 9139 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9140 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
5e7dfd0f 9141
5e7dfd0f 9142 /* Clear error status */
0f49bfbd 9143 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
5e7dfd0f
MC		 9144 PCI_EXP_DEVSTA_CED |
9145 PCI_EXP_DEVSTA_NFED |
9146 PCI_EXP_DEVSTA_FED |
9147 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 9148 }
9149
ee6a99b5 9150 tg3_restore_pci_state(tp);
1da177e4 9151
63c3a66f
JP		 9152 tg3_flag_clear(tp, CHIP_RESETTING);
9153 tg3_flag_clear(tp, ERROR_PROCESSED);
d18edcb2 9154
ee6a99b5 9155 val = 0;
63c3a66f 9156 if (tg3_flag(tp, 5780_CLASS))
4cf78e4f 9157 val = tr32(MEMARB_MODE);
ee6a99b5 9158 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4 9159
4153577a 9160 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
1da177e4
LT		 9161 tg3_stop_fw(tp);
9162 tw32(0x5000, 0x400);
9163 }
9164
7e6c63f0
HM		 9165 if (tg3_flag(tp, IS_SSB_CORE)) {
9166 /*
9167 * BCM4785: In order to avoid repercussions from using
9168 * potentially defective internal ROM, stop the Rx RISC CPU,
9169 * which is not required.
9170 */
9171 tg3_stop_fw(tp);
9172 tg3_halt_cpu(tp, RX_CPU_BASE);
9173 }
9174
fb03a43f
NS		 9175 err = tg3_poll_fw(tp);
9176 if (err)
9177 return err;
9178
1da177e4
LT		 9179 tw32(GRC_MODE, tp->grc_mode);
9180
4153577a 9181 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
ab0049b4 9182 val = tr32(0xc4);
1da177e4
LT		 9183
9184 tw32(0xc4, val | (1 << 15));
9185 }
9186
9187 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4153577a 9188 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4 9189 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4153577a 9190 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
1da177e4
LT		 9191 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9192 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9193 }
9194
f07e9af3 9195 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9e975cc2 9196 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
d2394e6b 9197 val = tp->mac_mode;
f07e9af3 9198 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9e975cc2 9199 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
d2394e6b 9200 val = tp->mac_mode;
1da177e4 9201 } else
d2394e6b
MC		 9202 val = 0;
9203
9204 tw32_f(MAC_MODE, val);
1da177e4
LT		 9205 udelay(40);
9206
77b483f1
MC		 9207 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9208
0a9140cf
MC		 9209 tg3_mdio_start(tp);
9210
63c3a66f 9211 if (tg3_flag(tp, PCI_EXPRESS) &&
4153577a
JP		 9212 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9213 tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9214 !tg3_flag(tp, 57765_PLUS)) {
ab0049b4 9215 val = tr32(0x7c00);
1da177e4
LT		 9216
9217 tw32(0x7c00, val | (1 << 25));
9218 }
9219
f82995b6 9220 tg3_restore_clk(tp);
d78b59f5 9221
1da177e4 9222 /* Reprobe ASF enable state. */
63c3a66f 9223 tg3_flag_clear(tp, ENABLE_ASF);
942d1af0
NS		 9224 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9225 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9226
63c3a66f 9227 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
1da177e4
LT		 9228 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9229 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9230 u32 nic_cfg;
9231
9232 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9233 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f 9234 tg3_flag_set(tp, ENABLE_ASF);
4ba526ce 9235 tp->last_event_jiffies = jiffies;
63c3a66f
JP		 9236 if (tg3_flag(tp, 5750_PLUS))
9237 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
942d1af0
NS		 9238
9239 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9240 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9241 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9242 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9243 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
1da177e4
LT		 9244 }
9245 }
9246
9247 return 0;
9248}
9249
65ec698d
MC		 9250static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9251static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
e565eec3 9252static void __tg3_set_rx_mode(struct net_device *);
92feeabf 9253
1da177e4 9254/* tp->lock is held. */
953c96e0 9255static int tg3_halt(struct tg3 *tp, int kind, bool silent)
1da177e4
LT		 9256{
9257 int err;
9258
9259 tg3_stop_fw(tp);
9260
944d980e 9261 tg3_write_sig_pre_reset(tp, kind);
1da177e4 9262
b3b7d6be 9263 tg3_abort_hw(tp, silent);
1da177e4
LT		 9264 err = tg3_chip_reset(tp);
9265
953c96e0 9266 __tg3_set_mac_addr(tp, false);
daba2a63 9267
944d980e
MC		 9268 tg3_write_sig_legacy(tp, kind);
9269 tg3_write_sig_post_reset(tp, kind);
1da177e4 9270
92feeabf
MC		 9271 if (tp->hw_stats) {
9272 /* Save the stats across chip resets... */
b4017c53 9273 tg3_get_nstats(tp, &tp->net_stats_prev);
92feeabf
MC		 9274 tg3_get_estats(tp, &tp->estats_prev);
9275
9276 /* And make sure the next sample is new data */
9277 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9278 }
9279
4bc814ab 9280 return err;
1da177e4
LT		 9281}
9282
1da177e4
LT		 9283static int tg3_set_mac_addr(struct net_device *dev, void *p)
9284{
9285 struct tg3 *tp = netdev_priv(dev);
9286 struct sockaddr *addr = p;
953c96e0
JP		 9287 int err = 0;
9288 bool skip_mac_1 = false;
1da177e4 9289
f9804ddb 9290 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 9291 return -EADDRNOTAVAIL;
f9804ddb 9292
1da177e4
LT		 9293 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9294
e75f7c90
MC		 9295 if (!netif_running(dev))
9296 return 0;
9297
63c3a66f 9298 if (tg3_flag(tp, ENABLE_ASF)) {
986e0aeb 9299 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 9300
986e0aeb
MC		 9301 addr0_high = tr32(MAC_ADDR_0_HIGH);
9302 addr0_low = tr32(MAC_ADDR_0_LOW);
9303 addr1_high = tr32(MAC_ADDR_1_HIGH);
9304 addr1_low = tr32(MAC_ADDR_1_LOW);
9305
9306 /* Skip MAC addr 1 if ASF is using it. */
9307 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9308 !(addr1_high == 0 && addr1_low == 0))
953c96e0 9309 skip_mac_1 = true;
58712ef9 9310 }
986e0aeb
MC		 9311 spin_lock_bh(&tp->lock);
9312 __tg3_set_mac_addr(tp, skip_mac_1);
e565eec3 9313 __tg3_set_rx_mode(dev);
986e0aeb 9314 spin_unlock_bh(&tp->lock);
1da177e4 9315
b9ec6c1b 9316 return err;
1da177e4
LT		 9317}
9318
9319/* tp->lock is held. */
9320static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9321 dma_addr_t mapping, u32 maxlen_flags,
9322 u32 nic_addr)
9323{
9324 tg3_write_mem(tp,
9325 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9326 ((u64) mapping >> 32));
9327 tg3_write_mem(tp,
9328 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9329 ((u64) mapping & 0xffffffff));
9330 tg3_write_mem(tp,
9331 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9332 maxlen_flags);
9333
63c3a66f 9334 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 9335 tg3_write_mem(tp,
9336 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9337 nic_addr);
9338}
9339
a489b6d9
MC		 9340
9341static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 9342{
a489b6d9 9343 int i = 0;
b6080e12 9344
63c3a66f 9345 if (!tg3_flag(tp, ENABLE_TSS)) {
b6080e12
MC		 9346 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9347 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9348 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 9349 } else {
9350 tw32(HOSTCC_TXCOL_TICKS, 0);
9351 tw32(HOSTCC_TXMAX_FRAMES, 0);
9352 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
a489b6d9
MC		 9353
9354 for (; i < tp->txq_cnt; i++) {
9355 u32 reg;
9356
9357 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9358 tw32(reg, ec->tx_coalesce_usecs);
9359 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9360 tw32(reg, ec->tx_max_coalesced_frames);
9361 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9362 tw32(reg, ec->tx_max_coalesced_frames_irq);
9363 }
19cfaecc 9364 }
b6080e12 9365
a489b6d9
MC		 9366 for (; i < tp->irq_max - 1; i++) {
9367 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9368 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9369 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9370 }
9371}
9372
9373static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9374{
9375 int i = 0;
9376 u32 limit = tp->rxq_cnt;
9377
63c3a66f 9378 if (!tg3_flag(tp, ENABLE_RSS)) {
19cfaecc
MC		 9379 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9380 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9381 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
a489b6d9 9382 limit--;
19cfaecc 9383 } else {
b6080e12
MC		 9384 tw32(HOSTCC_RXCOL_TICKS, 0);
9385 tw32(HOSTCC_RXMAX_FRAMES, 0);
9386 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 9387 }
b6080e12 9388
a489b6d9 9389 for (; i < limit; i++) {
b6080e12
MC		 9390 u32 reg;
9391
9392 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9393 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 9394 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9395 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 9396 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9397 tw32(reg, ec->rx_max_coalesced_frames_irq);
b6080e12
MC		 9398 }
9399
9400 for (; i < tp->irq_max - 1; i++) {
9401 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 9402 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 9403 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
a489b6d9
MC		 9404 }
9405}
19cfaecc 9406
a489b6d9
MC		 9407static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9408{
9409 tg3_coal_tx_init(tp, ec);
9410 tg3_coal_rx_init(tp, ec);
9411
9412 if (!tg3_flag(tp, 5705_PLUS)) {
9413 u32 val = ec->stats_block_coalesce_usecs;
9414
9415 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9416 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9417
f4a46d1f 9418 if (!tp->link_up)
a489b6d9
MC		 9419 val = 0;
9420
9421 tw32(HOSTCC_STAT_COAL_TICKS, val);
b6080e12 9422 }
15f9850d 9423}
1da177e4 9424
328947ff
NS		 9425/* tp->lock is held. */
9426static void tg3_tx_rcbs_disable(struct tg3 *tp)
9427{
9428 u32 txrcb, limit;
9429
9430 /* Disable all transmit rings but the first. */
9431 if (!tg3_flag(tp, 5705_PLUS))
9432 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9433 else if (tg3_flag(tp, 5717_PLUS))
9434 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9435 else if (tg3_flag(tp, 57765_CLASS) ||
9436 tg3_asic_rev(tp) == ASIC_REV_5762)
9437 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9438 else
9439 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9440
9441 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9442 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9443 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9444 BDINFO_FLAGS_DISABLED);
9445}
9446
32ba19ef
NS		 9447/* tp->lock is held. */
9448static void tg3_tx_rcbs_init(struct tg3 *tp)
9449{
9450 int i = 0;
9451 u32 txrcb = NIC_SRAM_SEND_RCB;
9452
9453 if (tg3_flag(tp, ENABLE_TSS))
9454 i++;
9455
9456 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9457 struct tg3_napi *tnapi = &tp->napi[i];
9458
9459 if (!tnapi->tx_ring)
9460 continue;
9461
9462 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9463 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9464 NIC_SRAM_TX_BUFFER_DESC);
9465 }
9466}
9467
328947ff
NS		 9468/* tp->lock is held. */
9469static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9470{
9471 u32 rxrcb, limit;
9472
9473 /* Disable all receive return rings but the first. */
9474 if (tg3_flag(tp, 5717_PLUS))
9475 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9476 else if (!tg3_flag(tp, 5705_PLUS))
9477 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9478 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9479 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9480 tg3_flag(tp, 57765_CLASS))
9481 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9482 else
9483 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9484
9485 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9486 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9487 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9488 BDINFO_FLAGS_DISABLED);
9489}
9490
32ba19ef
NS		 9491/* tp->lock is held. */
9492static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9493{
9494 int i = 0;
9495 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9496
9497 if (tg3_flag(tp, ENABLE_RSS))
9498 i++;
9499
9500 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9501 struct tg3_napi *tnapi = &tp->napi[i];
9502
9503 if (!tnapi->rx_rcb)
9504 continue;
9505
9506 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9507 (tp->rx_ret_ring_mask + 1) <<
9508 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9509 }
9510}
9511
2d31ecaf
MC		 9512/* tp->lock is held. */
9513static void tg3_rings_reset(struct tg3 *tp)
9514{
9515 int i;
328947ff 9516 u32 stblk;
2d31ecaf
MC		 9517 struct tg3_napi *tnapi = &tp->napi[0];
9518
328947ff 9519 tg3_tx_rcbs_disable(tp);
2d31ecaf 9520
328947ff 9521 tg3_rx_ret_rcbs_disable(tp);
2d31ecaf
MC		 9522
9523 /* Disable interrupts */
9524 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
0e6cf6a9
MC		 9525 tp->napi[0].chk_msi_cnt = 0;
9526 tp->napi[0].last_rx_cons = 0;
9527 tp->napi[0].last_tx_cons = 0;
2d31ecaf
MC		 9528
9529 /* Zero mailbox registers. */
63c3a66f 9530 if (tg3_flag(tp, SUPPORT_MSIX)) {
6fd45cb8 9531 for (i = 1; i < tp->irq_max; i++) {
f77a6a8e
MC		 9532 tp->napi[i].tx_prod = 0;
9533 tp->napi[i].tx_cons = 0;
63c3a66f 9534 if (tg3_flag(tp, ENABLE_TSS))
c2353a32 9535 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 9536 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9537 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7f230735 9538 tp->napi[i].chk_msi_cnt = 0;
0e6cf6a9
MC		 9539 tp->napi[i].last_rx_cons = 0;
9540 tp->napi[i].last_tx_cons = 0;
f77a6a8e 9541 }
63c3a66f 9542 if (!tg3_flag(tp, ENABLE_TSS))
c2353a32 9543 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 9544 } else {
9545 tp->napi[0].tx_prod = 0;
9546 tp->napi[0].tx_cons = 0;
9547 tw32_mailbox(tp->napi[0].prodmbox, 0);
9548 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9549 }
2d31ecaf
MC		 9550
9551 /* Make sure the NIC-based send BD rings are disabled. */
63c3a66f 9552 if (!tg3_flag(tp, 5705_PLUS)) {
2d31ecaf
MC		 9553 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9554 for (i = 0; i < 16; i++)
9555 tw32_tx_mbox(mbox + i * 8, 0);
9556 }
9557
2d31ecaf
MC		 9558 /* Clear status block in ram. */
9559 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9560
9561 /* Set status block DMA address */
9562 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9563 ((u64) tnapi->status_mapping >> 32));
9564 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9565 ((u64) tnapi->status_mapping & 0xffffffff));
9566
f77a6a8e 9567 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 9568
f77a6a8e
MC		 9569 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9570 u64 mapping = (u64)tnapi->status_mapping;
9571 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9572 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
32ba19ef 9573 stblk += 8;
f77a6a8e
MC		 9574
9575 /* Clear status block in ram. */
9576 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
f77a6a8e 9577 }
32ba19ef
NS		 9578
9579 tg3_tx_rcbs_init(tp);
9580 tg3_rx_ret_rcbs_init(tp);
2d31ecaf
MC		 9581}
9582
eb07a940
MC		 9583static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9584{
9585 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9586
63c3a66f
JP		 9587 if (!tg3_flag(tp, 5750_PLUS) ||
9588 tg3_flag(tp, 5780_CLASS) ||
4153577a
JP		 9589 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9590 tg3_asic_rev(tp) == ASIC_REV_5752 ||
513aa6ea 9591 tg3_flag(tp, 57765_PLUS))
eb07a940 9592 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
4153577a
JP		 9593 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9594 tg3_asic_rev(tp) == ASIC_REV_5787)
eb07a940
MC		 9595 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9596 else
9597 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9598
9599 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9600 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9601
9602 val = min(nic_rep_thresh, host_rep_thresh);
9603 tw32(RCVBDI_STD_THRESH, val);
9604
63c3a66f 9605 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9606 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9607
63c3a66f 9608 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
eb07a940
MC		 9609 return;
9610
513aa6ea 9611 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
eb07a940
MC		 9612
9613 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9614
9615 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9616 tw32(RCVBDI_JUMBO_THRESH, val);
9617
63c3a66f 9618 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9619 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9620}
9621
ccd5ba9d
MC		 9622static inline u32 calc_crc(unsigned char *buf, int len)
9623{
9624 u32 reg;
9625 u32 tmp;
9626 int j, k;
9627
9628 reg = 0xffffffff;
9629
9630 for (j = 0; j < len; j++) {
9631 reg ^= buf[j];
9632
9633 for (k = 0; k < 8; k++) {
9634 tmp = reg & 0x01;
9635
9636 reg >>= 1;
9637
9638 if (tmp)
9639 reg ^= 0xedb88320;
9640 }
9641 }
9642
9643 return ~reg;
9644}
9645
9646static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9647{
9648 /* accept or reject all multicast frames */
9649 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9650 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9651 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9652 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9653}
9654
9655static void __tg3_set_rx_mode(struct net_device *dev)
9656{
9657 struct tg3 *tp = netdev_priv(dev);
9658 u32 rx_mode;
9659
9660 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9661 RX_MODE_KEEP_VLAN_TAG);
9662
9663#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9664 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9665 * flag clear.
9666 */
9667 if (!tg3_flag(tp, ENABLE_ASF))
9668 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9669#endif
9670
9671 if (dev->flags & IFF_PROMISC) {
9672 /* Promiscuous mode. */
9673 rx_mode |= RX_MODE_PROMISC;
9674 } else if (dev->flags & IFF_ALLMULTI) {
9675 /* Accept all multicast. */
9676 tg3_set_multi(tp, 1);
9677 } else if (netdev_mc_empty(dev)) {
9678 /* Reject all multicast. */
9679 tg3_set_multi(tp, 0);
9680 } else {
9681 /* Accept one or more multicast(s). */
9682 struct netdev_hw_addr *ha;
9683 u32 mc_filter[4] = { 0, };
9684 u32 regidx;
9685 u32 bit;
9686 u32 crc;
9687
9688 netdev_for_each_mc_addr(ha, dev) {
9689 crc = calc_crc(ha->addr, ETH_ALEN);
9690 bit = ~crc & 0x7f;
9691 regidx = (bit & 0x60) >> 5;
9692 bit &= 0x1f;
9693 mc_filter[regidx] |= (1 << bit);
9694 }
9695
9696 tw32(MAC_HASH_REG_0, mc_filter[0]);
9697 tw32(MAC_HASH_REG_1, mc_filter[1]);
9698 tw32(MAC_HASH_REG_2, mc_filter[2]);
9699 tw32(MAC_HASH_REG_3, mc_filter[3]);
9700 }
9701
e565eec3
MC		 9702 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9703 rx_mode |= RX_MODE_PROMISC;
9704 } else if (!(dev->flags & IFF_PROMISC)) {
9705 /* Add all entries into to the mac addr filter list */
9706 int i = 0;
9707 struct netdev_hw_addr *ha;
9708
9709 netdev_for_each_uc_addr(ha, dev) {
9710 __tg3_set_one_mac_addr(tp, ha->addr,
9711 i + TG3_UCAST_ADDR_IDX(tp));
9712 i++;
9713 }
9714 }
9715
ccd5ba9d
MC		 9716 if (rx_mode != tp->rx_mode) {
9717 tp->rx_mode = rx_mode;
9718 tw32_f(MAC_RX_MODE, rx_mode);
9719 udelay(10);
9720 }
9721}
9722
9102426a 9723static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
90415477
MC		 9724{
9725 int i;
9726
9727 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9102426a 9728 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
90415477
MC		 9729}
9730
9731static void tg3_rss_check_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9732{
9733 int i;
9734
9735 if (!tg3_flag(tp, SUPPORT_MSIX))
9736 return;
9737
0b3ba055 9738 if (tp->rxq_cnt == 1) {
bcebcc46 9739 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
90415477
MC		 9740 return;
9741 }
9742
9743 /* Validate table against current IRQ count */
9744 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
0b3ba055 9745 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
90415477
MC		 9746 break;
9747 }
9748
9749 if (i != TG3_RSS_INDIR_TBL_SIZE)
9102426a 9750 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
bcebcc46
MC		 9751}
9752
90415477 9753static void tg3_rss_write_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9754{
9755 int i = 0;
9756 u32 reg = MAC_RSS_INDIR_TBL_0;
9757
9758 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9759 u32 val = tp->rss_ind_tbl[i];
9760 i++;
9761 for (; i % 8; i++) {
9762 val <<= 4;
9763 val |= tp->rss_ind_tbl[i];
9764 }
9765 tw32(reg, val);
9766 reg += 4;
9767 }
9768}
9769
9bc297ea
NS		 9770static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9771{
9772 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9773 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9774 else
9775 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9776}
9777
1da177e4 9778/* tp->lock is held. */
953c96e0 9779static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
1da177e4
LT		 9780{
9781 u32 val, rdmac_mode;
9782 int i, err, limit;
8fea32b9 9783 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
1da177e4
LT		 9784
9785 tg3_disable_ints(tp);
9786
9787 tg3_stop_fw(tp);
9788
9789 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9790
63c3a66f 9791 if (tg3_flag(tp, INIT_COMPLETE))
e6de8ad1 9792 tg3_abort_hw(tp, 1);
1da177e4 9793
fdad8de4
NS		 9794 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9795 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9796 tg3_phy_pull_config(tp);
400dfbaa 9797 tg3_eee_pull_config(tp, NULL);
fdad8de4
NS		 9798 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9799 }
9800
400dfbaa
NS		 9801 /* Enable MAC control of LPI */
9802 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9803 tg3_setup_eee(tp);
9804
603f1173 9805 if (reset_phy)
d4d2c558
MC		 9806 tg3_phy_reset(tp);
9807
1da177e4
LT		 9808 err = tg3_chip_reset(tp);
9809 if (err)
9810 return err;
9811
9812 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9813
4153577a 9814 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
d30cdd28
MC		 9815 val = tr32(TG3_CPMU_CTRL);
9816 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9817 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 9818
9819 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9820 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9821 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9822 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9823
9824 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9825 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9826 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9827 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9828
9829 val = tr32(TG3_CPMU_HST_ACC);
9830 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9831 val |= CPMU_HST_ACC_MACCLK_6_25;
9832 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 9833 }
9834
4153577a 9835 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
33466d93
MC		 9836 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9837 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9838 PCIE_PWR_MGMT_L1_THRESH_4MS;
9839 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 9840
9841 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9842 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9843
9844 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 9845
f40386c8
MC		 9846 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9847 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 9848 }
9849
63c3a66f 9850 if (tg3_flag(tp, L1PLLPD_EN)) {
614b0590
MC		 9851 u32 grc_mode = tr32(GRC_MODE);
9852
9853 /* Access the lower 1K of PL PCIE block registers. */
9854 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9855 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9856
9857 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9858 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9859 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9860
9861 tw32(GRC_MODE, grc_mode);
9862 }
9863
55086ad9 9864 if (tg3_flag(tp, 57765_CLASS)) {
4153577a 9865 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
5093eedc 9866 u32 grc_mode = tr32(GRC_MODE);
cea46462 9867
5093eedc
MC		 9868 /* Access the lower 1K of PL PCIE block registers. */
9869 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9870 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
cea46462 9871
5093eedc
MC		 9872 val = tr32(TG3_PCIE_TLDLPL_PORT +
9873 TG3_PCIE_PL_LO_PHYCTL5);
9874 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9875 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
cea46462 9876
5093eedc
MC		 9877 tw32(GRC_MODE, grc_mode);
9878 }
a977dbe8 9879
4153577a 9880 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
d3f677af
MC		 9881 u32 grc_mode;
9882
9883 /* Fix transmit hangs */
9884 val = tr32(TG3_CPMU_PADRNG_CTL);
9885 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9886 tw32(TG3_CPMU_PADRNG_CTL, val);
9887
9888 grc_mode = tr32(GRC_MODE);
1ff30a59
MC		 9889
9890 /* Access the lower 1K of DL PCIE block registers. */
9891 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9892 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9893
9894 val = tr32(TG3_PCIE_TLDLPL_PORT +
9895 TG3_PCIE_DL_LO_FTSMAX);
9896 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9897 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9898 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9899
9900 tw32(GRC_MODE, grc_mode);
9901 }
9902
a977dbe8
MC		 9903 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9904 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9905 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9906 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
cea46462
MC		 9907 }
9908
1da177e4
LT		 9909 /* This works around an issue with Athlon chipsets on
9910 * B3 tigon3 silicon. This bit has no effect on any
9911 * other revision. But do not set this on PCI Express
795d01c5 9912 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 9913 */
63c3a66f
JP		 9914 if (!tg3_flag(tp, CPMU_PRESENT)) {
9915 if (!tg3_flag(tp, PCI_EXPRESS))
795d01c5
MC		 9916 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9917 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9918 }
1da177e4 9919
4153577a 9920 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 9921 tg3_flag(tp, PCIX_MODE)) {
1da177e4
LT		 9922 val = tr32(TG3PCI_PCISTATE);
9923 val |= PCISTATE_RETRY_SAME_DMA;
9924 tw32(TG3PCI_PCISTATE, val);
9925 }
9926
63c3a66f 9927 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 9928 /* Allow reads and writes to the
9929 * APE register and memory space.
9930 */
9931 val = tr32(TG3PCI_PCISTATE);
9932 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 9933 PCISTATE_ALLOW_APE_SHMEM_WR |
9934 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 9935 tw32(TG3PCI_PCISTATE, val);
9936 }
9937
4153577a 9938 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
1da177e4
LT		 9939 /* Enable some hw fixes. */
9940 val = tr32(TG3PCI_MSI_DATA);
9941 val |= (1 << 26) | (1 << 28) | (1 << 29);
9942 tw32(TG3PCI_MSI_DATA, val);
9943 }
9944
9945 /* Descriptor ring init may make accesses to the
9946 * NIC SRAM area to setup the TX descriptors, so we
9947 * can only do this after the hardware has been
9948 * successfully reset.
9949 */
32d8c572
MC		 9950 err = tg3_init_rings(tp);
9951 if (err)
9952 return err;
1da177e4 9953
63c3a66f 9954 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 9955 val = tr32(TG3PCI_DMA_RW_CTRL) &
9956 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
4153577a 9957 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
1a319025 9958 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
55086ad9 9959 if (!tg3_flag(tp, 57765_CLASS) &&
4153577a
JP		 9960 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9961 tg3_asic_rev(tp) != ASIC_REV_5762)
0aebff48 9962 val |= DMA_RWCTRL_TAGGED_STAT_WA;
cbf9ca6c 9963 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
4153577a
JP		 9964 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9965 tg3_asic_rev(tp) != ASIC_REV_5761) {
d30cdd28
MC		 9966 /* This value is determined during the probe time DMA
9967 * engine test, tg3_test_dma.
9968 */
9969 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9970 }
1da177e4
LT		 9971
9972 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
9973 GRC_MODE_4X_NIC_SEND_RINGS |
9974 GRC_MODE_NO_TX_PHDR_CSUM |
9975 GRC_MODE_NO_RX_PHDR_CSUM);
9976 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 9977
9978 /* Pseudo-header checksum is done by hardware logic and not
9979 * the offload processers, so make the chip do the pseudo-
9980 * header checksums on receive. For transmit it is more
9981 * convenient to do the pseudo-header checksum in software
9982 * as Linux does that on transmit for us in all cases.
9983 */
9984 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4 9985
fb4ce8ad
MC		 9986 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
9987 if (tp->rxptpctl)
9988 tw32(TG3_RX_PTP_CTL,
9989 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
9990
9991 if (tg3_flag(tp, PTP_CAPABLE))
9992 val |= GRC_MODE_TIME_SYNC_ENABLE;
9993
9994 tw32(GRC_MODE, tp->grc_mode | val);
1da177e4
LT		 9995
9996 /* Setup the timer prescalar register. Clock is always 66Mhz. */
9997 val = tr32(GRC_MISC_CFG);
9998 val &= ~0xff;
9999 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
10000 tw32(GRC_MISC_CFG, val);
10001
10002 /* Initialize MBUF/DESC pool. */
63c3a66f 10003 if (tg3_flag(tp, 5750_PLUS)) {
1da177e4 10004 /* Do nothing. */
4153577a 10005 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
1da177e4 10006 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
4153577a 10007 if (tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 10008 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10009 else
10010 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10011 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10012 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
63c3a66f 10013 } else if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10014 int fw_len;
10015
077f849d 10016 fw_len = tp->fw_len;
1da177e4
LT		 10017 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10018 tw32(BUFMGR_MB_POOL_ADDR,
10019 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10020 tw32(BUFMGR_MB_POOL_SIZE,
10021 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10022 }
1da177e4 10023
0f893dc6 10024 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 10025 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10026 tp->bufmgr_config.mbuf_read_dma_low_water);
10027 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10028 tp->bufmgr_config.mbuf_mac_rx_low_water);
10029 tw32(BUFMGR_MB_HIGH_WATER,
10030 tp->bufmgr_config.mbuf_high_water);
10031 } else {
10032 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10033 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10034 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10035 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10036 tw32(BUFMGR_MB_HIGH_WATER,
10037 tp->bufmgr_config.mbuf_high_water_jumbo);
10038 }
10039 tw32(BUFMGR_DMA_LOW_WATER,
10040 tp->bufmgr_config.dma_low_water);
10041 tw32(BUFMGR_DMA_HIGH_WATER,
10042 tp->bufmgr_config.dma_high_water);
10043
d309a46e 10044 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
4153577a 10045 if (tg3_asic_rev(tp) == ASIC_REV_5719)
d309a46e 10046 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
4153577a 10047 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
94962f7f 10048 tg3_asic_rev(tp) == ASIC_REV_5762 ||
4153577a
JP		 10049 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10050 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
4d958473 10051 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
d309a46e 10052 tw32(BUFMGR_MODE, val);
1da177e4
LT		 10053 for (i = 0; i < 2000; i++) {
10054 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10055 break;
10056 udelay(10);
10057 }
10058 if (i >= 2000) {
05dbe005 10059 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 10060 return -ENODEV;
10061 }
10062
4153577a 10063 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
eb07a940 10064 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
b5d3772c 10065
eb07a940 10066 tg3_setup_rxbd_thresholds(tp);
1da177e4
LT		 10067
10068 /* Initialize TG3_BDINFO's at:
10069 * RCVDBDI_STD_BD: standard eth size rx ring
10070 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10071 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10072 *
10073 * like so:
10074 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10075 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10076 * ring attribute flags
10077 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10078 *
10079 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10080 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10081 *
10082 * The size of each ring is fixed in the firmware, but the location is
10083 * configurable.
10084 */
10085 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10086 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 10087 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10088 ((u64) tpr->rx_std_mapping & 0xffffffff));
63c3a66f 10089 if (!tg3_flag(tp, 5717_PLUS))
87668d35
MC		 10090 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10091 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 10092
fdb72b38 10093 /* Disable the mini ring */
63c3a66f 10094 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10095 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10096 BDINFO_FLAGS_DISABLED);
10097
fdb72b38
MC		 10098 /* Program the jumbo buffer descriptor ring control
10099 * blocks on those devices that have them.
10100 */
4153577a 10101 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
63c3a66f 10102 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
1da177e4 10103
63c3a66f 10104 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
1da177e4 10105 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10106 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 10107 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10108 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
de9f5230
MC		 10109 val = TG3_RX_JMB_RING_SIZE(tp) <<
10110 BDINFO_FLAGS_MAXLEN_SHIFT;
1da177e4 10111 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
de9f5230 10112 val | BDINFO_FLAGS_USE_EXT_RECV);
63c3a66f 10113 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
c65a17f4 10114 tg3_flag(tp, 57765_CLASS) ||
4153577a 10115 tg3_asic_rev(tp) == ASIC_REV_5762)
87668d35
MC		 10116 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10117 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 10118 } else {
10119 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10120 BDINFO_FLAGS_DISABLED);
10121 }
10122
63c3a66f 10123 if (tg3_flag(tp, 57765_PLUS)) {
fa6b2aae 10124 val = TG3_RX_STD_RING_SIZE(tp);
7cb32cf2
MC		 10125 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10126 val |= (TG3_RX_STD_DMA_SZ << 2);
10127 } else
04380d40 10128 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38 10129 } else
de9f5230 10130 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 10131
10132 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 10133
411da640 10134 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 10135 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 10136
63c3a66f
JP		 10137 tpr->rx_jmb_prod_idx =
10138 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
66711e66 10139 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 10140
2d31ecaf
MC		 10141 tg3_rings_reset(tp);
10142
1da177e4 10143 /* Initialize MAC address and backoff seed. */
953c96e0 10144 __tg3_set_mac_addr(tp, false);
1da177e4
LT		 10145
10146 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 10147 tw32(MAC_RX_MTU_SIZE,
10148 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 10149
10150 /* The slot time is changed by tg3_setup_phy if we
10151 * run at gigabit with half duplex.
10152 */
f2096f94
MC		 10153 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10154 (6 << TX_LENGTHS_IPG_SHIFT) |
10155 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10156
4153577a
JP		 10157 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10158 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10159 val |= tr32(MAC_TX_LENGTHS) &
10160 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10161 TX_LENGTHS_CNT_DWN_VAL_MSK);
10162
10163 tw32(MAC_TX_LENGTHS, val);
1da177e4
LT		 10164
10165 /* Receive rules. */
10166 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10167 tw32(RCVLPC_CONFIG, 0x0181);
10168
10169 /* Calculate RDMAC_MODE setting early, we need it to determine
10170 * the RCVLPC_STATE_ENABLE mask.
10171 */
10172 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10173 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10174 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10175 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10176 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 10177
4153577a 10178 if (tg3_asic_rev(tp) == ASIC_REV_5717)
0339e4e3
MC		 10179 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10180
4153577a
JP		 10181 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10182 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10183 tg3_asic_rev(tp) == ASIC_REV_57780)
d30cdd28
MC		 10184 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10185 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10186 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10187
4153577a
JP		 10188 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10189 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10190 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a 10191 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 10192 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10193 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10194 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10195 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10196 }
10197 }
10198
63c3a66f 10199 if (tg3_flag(tp, PCI_EXPRESS))
85e94ced
MC		 10200 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10201
4153577a 10202 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
d3f677af
MC		 10203 tp->dma_limit = 0;
10204 if (tp->dev->mtu <= ETH_DATA_LEN) {
10205 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10206 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10207 }
10208 }
10209
63c3a66f
JP		 10210 if (tg3_flag(tp, HW_TSO_1) ||
10211 tg3_flag(tp, HW_TSO_2) ||
10212 tg3_flag(tp, HW_TSO_3))
027455ad
MC		 10213 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10214
108a6c16 10215 if (tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 10216 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10217 tg3_asic_rev(tp) == ASIC_REV_57780)
027455ad 10218 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4 10219
4153577a
JP		 10220 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10221 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10222 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10223
4153577a
JP		 10224 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10225 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10226 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10227 tg3_asic_rev(tp) == ASIC_REV_57780 ||
63c3a66f 10228 tg3_flag(tp, 57765_PLUS)) {
c65a17f4
MC		 10229 u32 tgtreg;
10230
4153577a 10231 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10232 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10233 else
10234 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10235
10236 val = tr32(tgtreg);
4153577a
JP		 10237 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10238 tg3_asic_rev(tp) == ASIC_REV_5762) {
b4495ed8
MC		 10239 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10240 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10241 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10242 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10243 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10244 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
b75cc0e4 10245 }
c65a17f4 10246 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
41a8a7ee
MC		 10247 }
10248
4153577a
JP		 10249 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10250 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10251 tg3_asic_rev(tp) == ASIC_REV_5762) {
c65a17f4
MC		 10252 u32 tgtreg;
10253
4153577a 10254 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10255 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10256 else
10257 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10258
10259 val = tr32(tgtreg);
10260 tw32(tgtreg, val |
d309a46e
MC		 10261 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10262 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10263 }
10264
1da177e4 10265 /* Receive/send statistics. */
63c3a66f 10266 if (tg3_flag(tp, 5750_PLUS)) {
1661394e
MC		 10267 val = tr32(RCVLPC_STATS_ENABLE);
10268 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10269 tw32(RCVLPC_STATS_ENABLE, val);
10270 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
63c3a66f 10271 tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10272 val = tr32(RCVLPC_STATS_ENABLE);
10273 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10274 tw32(RCVLPC_STATS_ENABLE, val);
10275 } else {
10276 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10277 }
10278 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10279 tw32(SNDDATAI_STATSENAB, 0xffffff);
10280 tw32(SNDDATAI_STATSCTRL,
10281 (SNDDATAI_SCTRL_ENABLE |
10282 SNDDATAI_SCTRL_FASTUPD));
10283
10284 /* Setup host coalescing engine. */
10285 tw32(HOSTCC_MODE, 0);
10286 for (i = 0; i < 2000; i++) {
10287 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10288 break;
10289 udelay(10);
10290 }
10291
d244c892 10292 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 10293
63c3a66f 10294 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10295 /* Status/statistics block address. See tg3_timer,
10296 * the tg3_periodic_fetch_stats call there, and
10297 * tg3_get_stats to see how this works for 5705/5750 chips.
10298 */
1da177e4
LT		 10299 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10300 ((u64) tp->stats_mapping >> 32));
10301 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10302 ((u64) tp->stats_mapping & 0xffffffff));
10303 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 10304
1da177e4 10305 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 10306
10307 /* Clear statistics and status block memory areas */
10308 for (i = NIC_SRAM_STATS_BLK;
10309 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10310 i += sizeof(u32)) {
10311 tg3_write_mem(tp, i, 0);
10312 udelay(40);
10313 }
1da177e4
LT		 10314 }
10315
10316 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10317
10318 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10319 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
63c3a66f 10320 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10321 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10322
f07e9af3
MC		 10323 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10324 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c94e3941
MC		 10325 /* reset to prevent losing 1st rx packet intermittently */
10326 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10327 udelay(10);
10328 }
10329
3bda1258 10330 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9e975cc2
MC		 10331 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10332 MAC_MODE_FHDE_ENABLE;
10333 if (tg3_flag(tp, ENABLE_APE))
10334 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
63c3a66f 10335 if (!tg3_flag(tp, 5705_PLUS) &&
f07e9af3 10336 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a 10337 tg3_asic_rev(tp) != ASIC_REV_5700)
e8f3f6ca 10338 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 10339 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10340 udelay(40);
10341
314fba34 10342 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
63c3a66f 10343 * If TG3_FLAG_IS_NIC is zero, we should read the
314fba34
MC		 10344 * register to preserve the GPIO settings for LOMs. The GPIOs,
10345 * whether used as inputs or outputs, are set by boot code after
10346 * reset.
10347 */
63c3a66f 10348 if (!tg3_flag(tp, IS_NIC)) {
314fba34
MC		 10349 u32 gpio_mask;
10350
9d26e213
MC		 10351 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10352 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10353 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc 10354
4153577a 10355 if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc
MC		 10356 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10357 GRC_LCLCTRL_GPIO_OUTPUT3;
10358
4153577a 10359 if (tg3_asic_rev(tp) == ASIC_REV_5755)
af36e6b6
MC		 10360 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10361
aaf84465 10362 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 10363 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10364
10365 /* GPIO1 must be driven high for eeprom write protect */
63c3a66f 10366 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9d26e213
MC		 10367 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10368 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 10369 }
1da177e4
LT		 10370 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10371 udelay(100);
10372
c3b5003b 10373 if (tg3_flag(tp, USING_MSIX)) {
baf8a94a 10374 val = tr32(MSGINT_MODE);
c3b5003b
MC		 10375 val |= MSGINT_MODE_ENABLE;
10376 if (tp->irq_cnt > 1)
10377 val |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 10378 if (!tg3_flag(tp, 1SHOT_MSI))
10379 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
baf8a94a
MC		 10380 tw32(MSGINT_MODE, val);
10381 }
10382
63c3a66f 10383 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10384 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10385 udelay(40);
10386 }
10387
10388 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10389 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10390 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10391 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10392 WDMAC_MODE_LNGREAD_ENAB);
10393
4153577a
JP		 10394 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10395 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10396 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a
JP		 10397 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10398 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
1da177e4
LT		 10399 /* nothing */
10400 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10401 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10402 val |= WDMAC_MODE_RX_ACCEL;
10403 }
10404 }
10405
d9ab5ad1 10406 /* Enable host coalescing bug fix */
63c3a66f 10407 if (tg3_flag(tp, 5755_PLUS))
f51f3562 10408 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 10409
4153577a 10410 if (tg3_asic_rev(tp) == ASIC_REV_5785)
788a035e
MC		 10411 val |= WDMAC_MODE_BURST_ALL_DATA;
10412
1da177e4
LT		 10413 tw32_f(WDMAC_MODE, val);
10414 udelay(40);
10415
63c3a66f 10416 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 10417 u16 pcix_cmd;
10418
10419 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10420 &pcix_cmd);
4153577a 10421 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
9974a356
MC		 10422 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10423 pcix_cmd |= PCI_X_CMD_READ_2K;
4153577a 10424 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
9974a356
MC		 10425 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10426 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 10427 }
9974a356
MC		 10428 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10429 pcix_cmd);
1da177e4
LT		 10430 }
10431
10432 tw32_f(RDMAC_MODE, rdmac_mode);
10433 udelay(40);
10434
9bc297ea
NS		 10435 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10436 tg3_asic_rev(tp) == ASIC_REV_5720) {
091f0ea3
MC		 10437 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10438 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10439 break;
10440 }
10441 if (i < TG3_NUM_RDMA_CHANNELS) {
10442 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10443 val |= tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10444 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10445 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
091f0ea3
MC		 10446 }
10447 }
10448
1da177e4 10449 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
63c3a66f 10450 if (!tg3_flag(tp, 5705_PLUS))
1da177e4 10451 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6 10452
4153577a 10453 if (tg3_asic_rev(tp) == ASIC_REV_5761)
9936bcf6
MC		 10454 tw32(SNDDATAC_MODE,
10455 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10456 else
10457 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10458
1da177e4
LT		 10459 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10460 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7cb32cf2 10461 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
63c3a66f 10462 if (tg3_flag(tp, LRG_PROD_RING_CAP))
7cb32cf2
MC		 10463 val |= RCVDBDI_MODE_LRG_RING_SZ;
10464 tw32(RCVDBDI_MODE, val);
1da177e4 10465 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
63c3a66f
JP		 10466 if (tg3_flag(tp, HW_TSO_1) ||
10467 tg3_flag(tp, HW_TSO_2) ||
10468 tg3_flag(tp, HW_TSO_3))
1da177e4 10469 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 10470 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
63c3a66f 10471 if (tg3_flag(tp, ENABLE_TSS))
baf8a94a
MC		 10472 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10473 tw32(SNDBDI_MODE, val);
1da177e4
LT		 10474 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10475
4153577a 10476 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
1da177e4
LT		 10477 err = tg3_load_5701_a0_firmware_fix(tp);
10478 if (err)
10479 return err;
10480 }
10481
c4dab506
NS		 10482 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10483 /* Ignore any errors for the firmware download. If download
10484 * fails, the device will operate with EEE disabled
10485 */
10486 tg3_load_57766_firmware(tp);
10487 }
10488
63c3a66f 10489 if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10490 err = tg3_load_tso_firmware(tp);
10491 if (err)
10492 return err;
10493 }
1da177e4
LT		 10494
10495 tp->tx_mode = TX_MODE_ENABLE;
f2096f94 10496
63c3a66f 10497 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 10498 tg3_asic_rev(tp) == ASIC_REV_5906)
b1d05210 10499 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
f2096f94 10500
4153577a
JP		 10501 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10502 tg3_asic_rev(tp) == ASIC_REV_5762) {
f2096f94
MC		 10503 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10504 tp->tx_mode &= ~val;
10505 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10506 }
10507
1da177e4
LT		 10508 tw32_f(MAC_TX_MODE, tp->tx_mode);
10509 udelay(100);
10510
63c3a66f 10511 if (tg3_flag(tp, ENABLE_RSS)) {
bcebcc46 10512 tg3_rss_write_indir_tbl(tp);
baf8a94a
MC		 10513
10514 /* Setup the "secret" hash key. */
10515 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10516 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10517 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10518 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10519 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10520 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10521 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10522 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10523 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10524 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10525 }
10526
1da177e4 10527 tp->rx_mode = RX_MODE_ENABLE;
63c3a66f 10528 if (tg3_flag(tp, 5755_PLUS))
af36e6b6
MC		 10529 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10530
378b72c8
NS		 10531 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10532 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10533
63c3a66f 10534 if (tg3_flag(tp, ENABLE_RSS))
baf8a94a
MC		 10535 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10536 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10537 RX_MODE_RSS_IPV6_HASH_EN |
10538 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10539 RX_MODE_RSS_IPV4_HASH_EN |
10540 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10541
1da177e4
LT		 10542 tw32_f(MAC_RX_MODE, tp->rx_mode);
10543 udelay(10);
10544
1da177e4
LT		 10545 tw32(MAC_LED_CTRL, tp->led_ctrl);
10546
10547 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
f07e9af3 10548 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
1da177e4
LT		 10549 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10550 udelay(10);
10551 }
10552 tw32_f(MAC_RX_MODE, tp->rx_mode);
10553 udelay(10);
10554
f07e9af3 10555 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a
JP		 10556 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10557 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
1da177e4
LT		 10558 /* Set drive transmission level to 1.2V */
10559 /* only if the signal pre-emphasis bit is not set */
10560 val = tr32(MAC_SERDES_CFG);
10561 val &= 0xfffff000;
10562 val |= 0x880;
10563 tw32(MAC_SERDES_CFG, val);
10564 }
4153577a 10565 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
1da177e4
LT		 10566 tw32(MAC_SERDES_CFG, 0x616000);
10567 }
10568
10569 /* Prevent chip from dropping frames when flow control
10570 * is enabled.
10571 */
55086ad9 10572 if (tg3_flag(tp, 57765_CLASS))
666bc831
MC		 10573 val = 1;
10574 else
10575 val = 2;
10576 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4 10577
4153577a 10578 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
f07e9af3 10579 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
1da177e4 10580 /* Use hardware link auto-negotiation */
63c3a66f 10581 tg3_flag_set(tp, HW_AUTONEG);
1da177e4
LT		 10582 }
10583
f07e9af3 10584 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
4153577a 10585 tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 10586 u32 tmp;
10587
10588 tmp = tr32(SERDES_RX_CTRL);
10589 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10590 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10591 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10592 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10593 }
10594
63c3a66f 10595 if (!tg3_flag(tp, USE_PHYLIB)) {
c6700ce2 10596 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
80096068 10597 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1da177e4 10598
953c96e0 10599 err = tg3_setup_phy(tp, false);
dd477003
MC		 10600 if (err)
10601 return err;
1da177e4 10602
f07e9af3
MC		 10603 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10604 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
dd477003
MC		 10605 u32 tmp;
10606
10607 /* Clear CRC stats. */
10608 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10609 tg3_writephy(tp, MII_TG3_TEST1,
10610 tmp | MII_TG3_TEST1_CRC_EN);
f08aa1a8 10611 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
dd477003 10612 }
1da177e4
LT		 10613 }
10614 }
10615
10616 __tg3_set_rx_mode(tp->dev);
10617
10618 /* Initialize receive rules. */
10619 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10620 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10621 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10622 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10623
63c3a66f 10624 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
1da177e4
LT		 10625 limit = 8;
10626 else
10627 limit = 16;
63c3a66f 10628 if (tg3_flag(tp, ENABLE_ASF))
1da177e4
LT		 10629 limit -= 4;
10630 switch (limit) {
10631 case 16:
10632 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10633 case 15:
10634 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10635 case 14:
10636 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10637 case 13:
10638 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10639 case 12:
10640 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10641 case 11:
10642 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10643 case 10:
10644 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10645 case 9:
10646 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10647 case 8:
10648 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10649 case 7:
10650 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10651 case 6:
10652 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10653 case 5:
10654 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10655 case 4:
10656 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10657 case 3:
10658 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10659 case 2:
10660 case 1:
10661
10662 default:
10663 break;
855e1111 10664 }
1da177e4 10665
63c3a66f 10666 if (tg3_flag(tp, ENABLE_APE))
9ce768ea
MC		 10667 /* Write our heartbeat update interval to APE. */
10668 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10669 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 10670
1da177e4
LT		 10671 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10672
1da177e4
LT		 10673 return 0;
10674}
10675
10676/* Called at device open time to get the chip ready for
10677 * packet processing. Invoked with tp->lock held.
10678 */
953c96e0 10679static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
1da177e4 10680{
df465abf
NS		 10681 /* Chip may have been just powered on. If so, the boot code may still
10682 * be running initialization. Wait for it to finish to avoid races in
10683 * accessing the hardware.
10684 */
10685 tg3_enable_register_access(tp);
10686 tg3_poll_fw(tp);
10687
1da177e4
LT		 10688 tg3_switch_clocks(tp);
10689
10690 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10691
2f751b67 10692 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 10693}
10694
aed93e0b
MC		 10695static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10696{
10697 int i;
10698
10699 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10700 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10701
10702 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10703 off += len;
10704
10705 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10706 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10707 memset(ocir, 0, TG3_OCIR_LEN);
10708 }
10709}
10710
10711/* sysfs attributes for hwmon */
10712static ssize_t tg3_show_temp(struct device *dev,
10713 struct device_attribute *devattr, char *buf)
10714{
aed93e0b 10715 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
a2f4dfba 10716 struct tg3 *tp = dev_get_drvdata(dev);
aed93e0b
MC		 10717 u32 temperature;
10718
10719 spin_lock_bh(&tp->lock);
10720 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10721 sizeof(temperature));
10722 spin_unlock_bh(&tp->lock);
10723 return sprintf(buf, "%u\n", temperature);
10724}
10725
10726
10727static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10728 TG3_TEMP_SENSOR_OFFSET);
10729static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10730 TG3_TEMP_CAUTION_OFFSET);
10731static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10732 TG3_TEMP_MAX_OFFSET);
10733
a2f4dfba 10734static struct attribute *tg3_attrs[] = {
aed93e0b
MC		 10735 &sensor_dev_attr_temp1_input.dev_attr.attr,
10736 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10737 &sensor_dev_attr_temp1_max.dev_attr.attr,
10738 NULL
10739};
a2f4dfba 10740ATTRIBUTE_GROUPS(tg3);
aed93e0b 10741
aed93e0b
MC		 10742static void tg3_hwmon_close(struct tg3 *tp)
10743{
aed93e0b
MC		 10744 if (tp->hwmon_dev) {
10745 hwmon_device_unregister(tp->hwmon_dev);
10746 tp->hwmon_dev = NULL;
aed93e0b 10747 }
aed93e0b
MC		 10748}
10749
10750static void tg3_hwmon_open(struct tg3 *tp)
10751{
a2f4dfba 10752 int i;
aed93e0b
MC		 10753 u32 size = 0;
10754 struct pci_dev *pdev = tp->pdev;
10755 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10756
10757 tg3_sd_scan_scratchpad(tp, ocirs);
10758
10759 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10760 if (!ocirs[i].src_data_length)
10761 continue;
10762
10763 size += ocirs[i].src_hdr_length;
10764 size += ocirs[i].src_data_length;
10765 }
10766
10767 if (!size)
10768 return;
10769
a2f4dfba
GR		 10770 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10771 tp, tg3_groups);
aed93e0b
MC		 10772 if (IS_ERR(tp->hwmon_dev)) {
10773 tp->hwmon_dev = NULL;
10774 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
aed93e0b 10775 }
aed93e0b
MC		 10776}
10777
10778
1da177e4
LT		 10779#define TG3_STAT_ADD32(PSTAT, REG) \
10780do { u32 __val = tr32(REG); \
10781 (PSTAT)->low += __val; \
10782 if ((PSTAT)->low < __val) \
10783 (PSTAT)->high += 1; \
10784} while (0)
10785
10786static void tg3_periodic_fetch_stats(struct tg3 *tp)
10787{
10788 struct tg3_hw_stats *sp = tp->hw_stats;
10789
f4a46d1f 10790 if (!tp->link_up)
1da177e4
LT		 10791 return;
10792
10793 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10794 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10795 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10796 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10797 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10798 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10799 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10800 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10801 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10802 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10803 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10804 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10805 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9bc297ea 10806 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
091f0ea3
MC		 10807 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10808 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10809 u32 val;
10810
10811 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10812 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10813 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10814 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
091f0ea3 10815 }
1da177e4
LT		 10816
10817 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10818 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10819 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10820 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10821 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10822 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10823 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10824 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10825 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10826 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10827 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10828 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10829 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10830 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 10831
10832 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
4153577a 10833 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
94962f7f 10834 tg3_asic_rev(tp) != ASIC_REV_5762 &&
4153577a
JP		 10835 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10836 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
4d958473
MC		 10837 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10838 } else {
10839 u32 val = tr32(HOSTCC_FLOW_ATTN);
10840 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10841 if (val) {
10842 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10843 sp->rx_discards.low += val;
10844 if (sp->rx_discards.low < val)
10845 sp->rx_discards.high += 1;
10846 }
10847 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10848 }
463d305b 10849 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 10850}
10851
0e6cf6a9
MC		 10852static void tg3_chk_missed_msi(struct tg3 *tp)
10853{
10854 u32 i;
10855
10856 for (i = 0; i < tp->irq_cnt; i++) {
10857 struct tg3_napi *tnapi = &tp->napi[i];
10858
10859 if (tg3_has_work(tnapi)) {
10860 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10861 tnapi->last_tx_cons == tnapi->tx_cons) {
10862 if (tnapi->chk_msi_cnt < 1) {
10863 tnapi->chk_msi_cnt++;
10864 return;
10865 }
7f230735 10866 tg3_msi(0, tnapi);
0e6cf6a9
MC		 10867 }
10868 }
10869 tnapi->chk_msi_cnt = 0;
10870 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10871 tnapi->last_tx_cons = tnapi->tx_cons;
10872 }
10873}
10874
1da177e4
LT		 10875static void tg3_timer(unsigned long __opaque)
10876{
10877 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 10878
5b190624 10879 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
f475f163
MC		 10880 goto restart_timer;
10881
f47c11ee 10882 spin_lock(&tp->lock);
1da177e4 10883
4153577a 10884 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
55086ad9 10885 tg3_flag(tp, 57765_CLASS))
0e6cf6a9
MC		 10886 tg3_chk_missed_msi(tp);
10887
7e6c63f0
HM		 10888 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10889 /* BCM4785: Flush posted writes from GbE to host memory. */
10890 tr32(HOSTCC_MODE);
10891 }
10892
63c3a66f 10893 if (!tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 10894 /* All of this garbage is because when using non-tagged
10895 * IRQ status the mailbox/status_block protocol the chip
10896 * uses with the cpu is race prone.
10897 */
898a56f8 10898 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 10899 tw32(GRC_LOCAL_CTRL,
10900 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10901 } else {
10902 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 10903 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 10904 }
1da177e4 10905
fac9b83e 10906 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
f47c11ee 10907 spin_unlock(&tp->lock);
db219973 10908 tg3_reset_task_schedule(tp);
5b190624 10909 goto restart_timer;
fac9b83e 10910 }
1da177e4
LT		 10911 }
10912
1da177e4
LT		 10913 /* This part only runs once per second. */
10914 if (!--tp->timer_counter) {
63c3a66f 10915 if (tg3_flag(tp, 5705_PLUS))
fac9b83e
DM		 10916 tg3_periodic_fetch_stats(tp);
10917
b0c5943f
MC		 10918 if (tp->setlpicnt && !--tp->setlpicnt)
10919 tg3_phy_eee_enable(tp);
52b02d04 10920
63c3a66f 10921 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 10922 u32 mac_stat;
10923 int phy_event;
10924
10925 mac_stat = tr32(MAC_STATUS);
10926
10927 phy_event = 0;
f07e9af3 10928 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
1da177e4
LT		 10929 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10930 phy_event = 1;
10931 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10932 phy_event = 1;
10933
10934 if (phy_event)
953c96e0 10935 tg3_setup_phy(tp, false);
63c3a66f 10936 } else if (tg3_flag(tp, POLL_SERDES)) {
1da177e4
LT		 10937 u32 mac_stat = tr32(MAC_STATUS);
10938 int need_setup = 0;
10939
f4a46d1f 10940 if (tp->link_up &&
1da177e4
LT		 10941 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10942 need_setup = 1;
10943 }
f4a46d1f 10944 if (!tp->link_up &&
1da177e4
LT		 10945 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10946 MAC_STATUS_SIGNAL_DET))) {
10947 need_setup = 1;
10948 }
10949 if (need_setup) {
3d3ebe74
MC		 10950 if (!tp->serdes_counter) {
10951 tw32_f(MAC_MODE,
10952 (tp->mac_mode &
10953 ~MAC_MODE_PORT_MODE_MASK));
10954 udelay(40);
10955 tw32_f(MAC_MODE, tp->mac_mode);
10956 udelay(40);
10957 }
953c96e0 10958 tg3_setup_phy(tp, false);
1da177e4 10959 }
f07e9af3 10960 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
63c3a66f 10961 tg3_flag(tp, 5780_CLASS)) {
747e8f8b 10962 tg3_serdes_parallel_detect(tp);
1743b83c
NS		 10963 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
10964 u32 cpmu = tr32(TG3_CPMU_STATUS);
10965 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
10966 TG3_CPMU_STATUS_LINK_MASK);
10967
10968 if (link_up != tp->link_up)
10969 tg3_setup_phy(tp, false);
57d8b880 10970 }
1da177e4
LT		 10971
10972 tp->timer_counter = tp->timer_multiplier;
10973 }
10974
130b8e4d
MC		 10975 /* Heartbeat is only sent once every 2 seconds.
10976 *
10977 * The heartbeat is to tell the ASF firmware that the host
10978 * driver is still alive. In the event that the OS crashes,
10979 * ASF needs to reset the hardware to free up the FIFO space
10980 * that may be filled with rx packets destined for the host.
10981 * If the FIFO is full, ASF will no longer function properly.
10982 *
10983 * Unintended resets have been reported on real time kernels
10984 * where the timer doesn't run on time. Netpoll will also have
10985 * same problem.
10986 *
10987 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
10988 * to check the ring condition when the heartbeat is expiring
10989 * before doing the reset. This will prevent most unintended
10990 * resets.
10991 */
1da177e4 10992 if (!--tp->asf_counter) {
63c3a66f 10993 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7c5026aa
MC		 10994 tg3_wait_for_event_ack(tp);
10995
bbadf503 10996 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 10997 FWCMD_NICDRV_ALIVE3);
bbadf503 10998 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
c6cdf436
MC		 10999 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
11000 TG3_FW_UPDATE_TIMEOUT_SEC);
4ba526ce
MC		 11001
11002 tg3_generate_fw_event(tp);
1da177e4
LT		 11003 }
11004 tp->asf_counter = tp->asf_multiplier;
11005 }
11006
f47c11ee 11007 spin_unlock(&tp->lock);
1da177e4 11008
f475f163 11009restart_timer:
1da177e4
LT		 11010 tp->timer.expires = jiffies + tp->timer_offset;
11011 add_timer(&tp->timer);
11012}
11013
229b1ad1 11014static void tg3_timer_init(struct tg3 *tp)
21f7638e
MC		 11015{
11016 if (tg3_flag(tp, TAGGED_STATUS) &&
4153577a 11017 tg3_asic_rev(tp) != ASIC_REV_5717 &&
21f7638e
MC		 11018 !tg3_flag(tp, 57765_CLASS))
11019 tp->timer_offset = HZ;
11020 else
11021 tp->timer_offset = HZ / 10;
11022
11023 BUG_ON(tp->timer_offset > HZ);
11024
11025 tp->timer_multiplier = (HZ / tp->timer_offset);
11026 tp->asf_multiplier = (HZ / tp->timer_offset) *
11027 TG3_FW_UPDATE_FREQ_SEC;
11028
11029 init_timer(&tp->timer);
11030 tp->timer.data = (unsigned long) tp;
11031 tp->timer.function = tg3_timer;
11032}
11033
11034static void tg3_timer_start(struct tg3 *tp)
11035{
11036 tp->asf_counter = tp->asf_multiplier;
11037 tp->timer_counter = tp->timer_multiplier;
11038
11039 tp->timer.expires = jiffies + tp->timer_offset;
11040 add_timer(&tp->timer);
11041}
11042
11043static void tg3_timer_stop(struct tg3 *tp)
11044{
11045 del_timer_sync(&tp->timer);
11046}
11047
11048/* Restart hardware after configuration changes, self-test, etc.
11049 * Invoked with tp->lock held.
11050 */
953c96e0 11051static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
21f7638e
MC		 11052 __releases(tp->lock)
11053 __acquires(tp->lock)
11054{
11055 int err;
11056
11057 err = tg3_init_hw(tp, reset_phy);
11058 if (err) {
11059 netdev_err(tp->dev,
11060 "Failed to re-initialize device, aborting\n");
11061 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11062 tg3_full_unlock(tp);
11063 tg3_timer_stop(tp);
11064 tp->irq_sync = 0;
11065 tg3_napi_enable(tp);
11066 dev_close(tp->dev);
11067 tg3_full_lock(tp, 0);
11068 }
11069 return err;
11070}
11071
11072static void tg3_reset_task(struct work_struct *work)
11073{
11074 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11075 int err;
11076
11077 tg3_full_lock(tp, 0);
11078
11079 if (!netif_running(tp->dev)) {
11080 tg3_flag_clear(tp, RESET_TASK_PENDING);
11081 tg3_full_unlock(tp);
11082 return;
11083 }
11084
11085 tg3_full_unlock(tp);
11086
11087 tg3_phy_stop(tp);
11088
11089 tg3_netif_stop(tp);
11090
11091 tg3_full_lock(tp, 1);
11092
11093 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11094 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11095 tp->write32_rx_mbox = tg3_write_flush_reg32;
11096 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11097 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11098 }
11099
11100 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
953c96e0 11101 err = tg3_init_hw(tp, true);
21f7638e
MC		 11102 if (err)
11103 goto out;
11104
11105 tg3_netif_start(tp);
11106
11107out:
11108 tg3_full_unlock(tp);
11109
11110 if (!err)
11111 tg3_phy_start(tp);
11112
11113 tg3_flag_clear(tp, RESET_TASK_PENDING);
11114}
11115
4f125f42 11116static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 11117{
7d12e780 11118 irq_handler_t fn;
fcfa0a32 11119 unsigned long flags;
4f125f42
MC		 11120 char *name;
11121 struct tg3_napi *tnapi = &tp->napi[irq_num];
11122
11123 if (tp->irq_cnt == 1)
11124 name = tp->dev->name;
11125 else {
11126 name = &tnapi->irq_lbl[0];
21e315e1
NS		 11127 if (tnapi->tx_buffers && tnapi->rx_rcb)
11128 snprintf(name, IFNAMSIZ,
11129 "%s-txrx-%d", tp->dev->name, irq_num);
11130 else if (tnapi->tx_buffers)
11131 snprintf(name, IFNAMSIZ,
11132 "%s-tx-%d", tp->dev->name, irq_num);
11133 else if (tnapi->rx_rcb)
11134 snprintf(name, IFNAMSIZ,
11135 "%s-rx-%d", tp->dev->name, irq_num);
11136 else
11137 snprintf(name, IFNAMSIZ,
11138 "%s-%d", tp->dev->name, irq_num);
4f125f42
MC		 11139 name[IFNAMSIZ-1] = 0;
11140 }
fcfa0a32 11141
63c3a66f 11142 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
fcfa0a32 11143 fn = tg3_msi;
63c3a66f 11144 if (tg3_flag(tp, 1SHOT_MSI))
fcfa0a32 11145 fn = tg3_msi_1shot;
ab392d2d 11146 flags = 0;
fcfa0a32
MC		 11147 } else {
11148 fn = tg3_interrupt;
63c3a66f 11149 if (tg3_flag(tp, TAGGED_STATUS))
fcfa0a32 11150 fn = tg3_interrupt_tagged;
ab392d2d 11151 flags = IRQF_SHARED;
fcfa0a32 11152 }
4f125f42
MC		 11153
11154 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 11155}
11156
7938109f
MC		 11157static int tg3_test_interrupt(struct tg3 *tp)
11158{
09943a18 11159 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 11160 struct net_device *dev = tp->dev;
b16250e3 11161 int err, i, intr_ok = 0;
f6eb9b1f 11162 u32 val;
7938109f 11163
d4bc3927
MC		 11164 if (!netif_running(dev))
11165 return -ENODEV;
11166
7938109f
MC		 11167 tg3_disable_ints(tp);
11168
4f125f42 11169 free_irq(tnapi->irq_vec, tnapi);
7938109f 11170
f6eb9b1f
MC		 11171 /*
11172 * Turn off MSI one shot mode. Otherwise this test has no
11173 * observable way to know whether the interrupt was delivered.
11174 */
3aa1cdf8 11175 if (tg3_flag(tp, 57765_PLUS)) {
f6eb9b1f
MC		 11176 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11177 tw32(MSGINT_MODE, val);
11178 }
11179
4f125f42 11180 err = request_irq(tnapi->irq_vec, tg3_test_isr,
f274fd9a 11181 IRQF_SHARED, dev->name, tnapi);
7938109f
MC		 11182 if (err)
11183 return err;
11184
898a56f8 11185 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 11186 tg3_enable_ints(tp);
11187
11188 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 11189 tnapi->coal_now);
7938109f
MC		 11190
11191 for (i = 0; i < 5; i++) {
b16250e3
MC		 11192 u32 int_mbox, misc_host_ctrl;
11193
898a56f8 11194 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 11195 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11196
11197 if ((int_mbox != 0) ||
11198 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11199 intr_ok = 1;
7938109f 11200 break;
b16250e3
MC		 11201 }
11202
3aa1cdf8
MC		 11203 if (tg3_flag(tp, 57765_PLUS) &&
11204 tnapi->hw_status->status_tag != tnapi->last_tag)
11205 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11206
7938109f
MC		 11207 msleep(10);
11208 }
11209
11210 tg3_disable_ints(tp);
11211
4f125f42 11212 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 11213
4f125f42 11214 err = tg3_request_irq(tp, 0);
7938109f
MC		 11215
11216 if (err)
11217 return err;
11218
f6eb9b1f
MC		 11219 if (intr_ok) {
11220 /* Reenable MSI one shot mode. */
5b39de91 11221 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
f6eb9b1f
MC		 11222 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11223 tw32(MSGINT_MODE, val);
11224 }
7938109f 11225 return 0;
f6eb9b1f 11226 }
7938109f
MC		 11227
11228 return -EIO;
11229}
11230
11231/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11232 * successfully restored
11233 */
11234static int tg3_test_msi(struct tg3 *tp)
11235{
7938109f
MC		 11236 int err;
11237 u16 pci_cmd;
11238
63c3a66f 11239 if (!tg3_flag(tp, USING_MSI))
7938109f
MC		 11240 return 0;
11241
11242 /* Turn off SERR reporting in case MSI terminates with Master
11243 * Abort.
11244 */
11245 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11246 pci_write_config_word(tp->pdev, PCI_COMMAND,
11247 pci_cmd & ~PCI_COMMAND_SERR);
11248
11249 err = tg3_test_interrupt(tp);
11250
11251 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11252
11253 if (!err)
11254 return 0;
11255
11256 /* other failures */
11257 if (err != -EIO)
11258 return err;
11259
11260 /* MSI test failed, go back to INTx mode */
5129c3a3
MC		 11261 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11262 "to INTx mode. Please report this failure to the PCI "
11263 "maintainer and include system chipset information\n");
7938109f 11264
4f125f42 11265 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 11266
7938109f
MC		 11267 pci_disable_msi(tp->pdev);
11268
63c3a66f 11269 tg3_flag_clear(tp, USING_MSI);
dc8bf1b1 11270 tp->napi[0].irq_vec = tp->pdev->irq;
7938109f 11271
4f125f42 11272 err = tg3_request_irq(tp, 0);
7938109f
MC		 11273 if (err)
11274 return err;
11275
11276 /* Need to reset the chip because the MSI cycle may have terminated
11277 * with Master Abort.
11278 */
f47c11ee 11279 tg3_full_lock(tp, 1);
7938109f 11280
944d980e 11281 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 11282 err = tg3_init_hw(tp, true);
7938109f 11283
f47c11ee 11284 tg3_full_unlock(tp);
7938109f
MC		 11285
11286 if (err)
4f125f42 11287 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 11288
11289 return err;
11290}
11291
9e9fd12d
MC		 11292static int tg3_request_firmware(struct tg3 *tp)
11293{
77997ea3 11294 const struct tg3_firmware_hdr *fw_hdr;
9e9fd12d
MC		 11295
11296 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 11297 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11298 tp->fw_needed);
9e9fd12d
MC		 11299 return -ENOENT;
11300 }
11301
77997ea3 11302 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
9e9fd12d
MC		 11303
11304 /* Firmware blob starts with version numbers, followed by
11305 * start address and _full_ length including BSS sections
11306 * (which must be longer than the actual data, of course
11307 */
11308
77997ea3
NS		 11309 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11310 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
05dbe005
JP		 11311 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11312 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 11313 release_firmware(tp->fw);
11314 tp->fw = NULL;
11315 return -EINVAL;
11316 }
11317
11318 /* We no longer need firmware; we have it. */
11319 tp->fw_needed = NULL;
11320 return 0;
11321}
11322
9102426a 11323static u32 tg3_irq_count(struct tg3 *tp)
679563f4 11324{
9102426a 11325 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
679563f4 11326
9102426a 11327 if (irq_cnt > 1) {
c3b5003b
MC		 11328 /* We want as many rx rings enabled as there are cpus.
11329 * In multiqueue MSI-X mode, the first MSI-X vector
11330 * only deals with link interrupts, etc, so we add
11331 * one to the number of vectors we are requesting.
11332 */
9102426a 11333 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
c3b5003b 11334 }
679563f4 11335
9102426a
MC		 11336 return irq_cnt;
11337}
11338
11339static bool tg3_enable_msix(struct tg3 *tp)
11340{
11341 int i, rc;
86449944 11342 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
9102426a 11343
0968169c
MC		 11344 tp->txq_cnt = tp->txq_req;
11345 tp->rxq_cnt = tp->rxq_req;
11346 if (!tp->rxq_cnt)
11347 tp->rxq_cnt = netif_get_num_default_rss_queues();
9102426a
MC		 11348 if (tp->rxq_cnt > tp->rxq_max)
11349 tp->rxq_cnt = tp->rxq_max;
cf6d6ea6
MC		 11350
11351 /* Disable multiple TX rings by default. Simple round-robin hardware
11352 * scheduling of the TX rings can cause starvation of rings with
11353 * small packets when other rings have TSO or jumbo packets.
11354 */
11355 if (!tp->txq_req)
11356 tp->txq_cnt = 1;
9102426a
MC		 11357
11358 tp->irq_cnt = tg3_irq_count(tp);
11359
679563f4
MC		 11360 for (i = 0; i < tp->irq_max; i++) {
11361 msix_ent[i].entry = i;
11362 msix_ent[i].vector = 0;
11363 }
11364
11365 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
2430b031
MC		 11366 if (rc < 0) {
11367 return false;
11368 } else if (rc != 0) {
679563f4
MC		 11369 if (pci_enable_msix(tp->pdev, msix_ent, rc))
11370 return false;
05dbe005
JP		 11371 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11372 tp->irq_cnt, rc);
679563f4 11373 tp->irq_cnt = rc;
49a359e3 11374 tp->rxq_cnt = max(rc - 1, 1);
9102426a
MC		 11375 if (tp->txq_cnt)
11376 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
679563f4
MC		 11377 }
11378
11379 for (i = 0; i < tp->irq_max; i++)
11380 tp->napi[i].irq_vec = msix_ent[i].vector;
11381
49a359e3 11382 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
2ddaad39
BH		 11383 pci_disable_msix(tp->pdev);
11384 return false;
11385 }
b92b9040 11386
9102426a
MC		 11387 if (tp->irq_cnt == 1)
11388 return true;
d78b59f5 11389
9102426a
MC		 11390 tg3_flag_set(tp, ENABLE_RSS);
11391
11392 if (tp->txq_cnt > 1)
11393 tg3_flag_set(tp, ENABLE_TSS);
11394
11395 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
2430b031 11396
679563f4
MC		 11397 return true;
11398}
11399
07b0173c
MC		 11400static void tg3_ints_init(struct tg3 *tp)
11401{
63c3a66f
JP		 11402 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11403 !tg3_flag(tp, TAGGED_STATUS)) {
07b0173c
MC		 11404 /* All MSI supporting chips should support tagged
11405 * status. Assert that this is the case.
11406 */
5129c3a3
MC		 11407 netdev_warn(tp->dev,
11408 "MSI without TAGGED_STATUS? Not using MSI\n");
679563f4 11409 goto defcfg;
07b0173c 11410 }
4f125f42 11411
63c3a66f
JP		 11412 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11413 tg3_flag_set(tp, USING_MSIX);
11414 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11415 tg3_flag_set(tp, USING_MSI);
679563f4 11416
63c3a66f 11417 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
679563f4 11418 u32 msi_mode = tr32(MSGINT_MODE);
63c3a66f 11419 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
baf8a94a 11420 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 11421 if (!tg3_flag(tp, 1SHOT_MSI))
11422 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
679563f4
MC		 11423 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11424 }
11425defcfg:
63c3a66f 11426 if (!tg3_flag(tp, USING_MSIX)) {
679563f4
MC		 11427 tp->irq_cnt = 1;
11428 tp->napi[0].irq_vec = tp->pdev->irq;
49a359e3
MC		 11429 }
11430
11431 if (tp->irq_cnt == 1) {
11432 tp->txq_cnt = 1;
11433 tp->rxq_cnt = 1;
2ddaad39 11434 netif_set_real_num_tx_queues(tp->dev, 1);
85407885 11435 netif_set_real_num_rx_queues(tp->dev, 1);
679563f4 11436 }
07b0173c
MC		 11437}
11438
11439static void tg3_ints_fini(struct tg3 *tp)
11440{
63c3a66f 11441 if (tg3_flag(tp, USING_MSIX))
679563f4 11442 pci_disable_msix(tp->pdev);
63c3a66f 11443 else if (tg3_flag(tp, USING_MSI))
679563f4 11444 pci_disable_msi(tp->pdev);
63c3a66f
JP		 11445 tg3_flag_clear(tp, USING_MSI);
11446 tg3_flag_clear(tp, USING_MSIX);
11447 tg3_flag_clear(tp, ENABLE_RSS);
11448 tg3_flag_clear(tp, ENABLE_TSS);
07b0173c
MC		 11449}
11450
be947307
MC		 11451static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11452 bool init)
1da177e4 11453{
d8f4cd38 11454 struct net_device *dev = tp->dev;
4f125f42 11455 int i, err;
1da177e4 11456
679563f4
MC		 11457 /*
11458 * Setup interrupts first so we know how
11459 * many NAPI resources to allocate
11460 */
11461 tg3_ints_init(tp);
11462
90415477 11463 tg3_rss_check_indir_tbl(tp);
bcebcc46 11464
1da177e4
LT		 11465 /* The placement of this call is tied
11466 * to the setup and use of Host TX descriptors.
11467 */
11468 err = tg3_alloc_consistent(tp);
11469 if (err)
4a5f46f2 11470 goto out_ints_fini;
88b06bc2 11471
66cfd1bd
MC		 11472 tg3_napi_init(tp);
11473
fed97810 11474 tg3_napi_enable(tp);
1da177e4 11475
4f125f42
MC		 11476 for (i = 0; i < tp->irq_cnt; i++) {
11477 struct tg3_napi *tnapi = &tp->napi[i];
11478 err = tg3_request_irq(tp, i);
11479 if (err) {
5bc09186
MC		 11480 for (i--; i >= 0; i--) {
11481 tnapi = &tp->napi[i];
4f125f42 11482 free_irq(tnapi->irq_vec, tnapi);
5bc09186 11483 }
4a5f46f2 11484 goto out_napi_fini;
4f125f42
MC		 11485 }
11486 }
1da177e4 11487
f47c11ee 11488 tg3_full_lock(tp, 0);
1da177e4 11489
2e460fc0
NS		 11490 if (init)
11491 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11492
d8f4cd38 11493 err = tg3_init_hw(tp, reset_phy);
1da177e4 11494 if (err) {
944d980e 11495 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11496 tg3_free_rings(tp);
1da177e4
LT		 11497 }
11498
f47c11ee 11499 tg3_full_unlock(tp);
1da177e4 11500
07b0173c 11501 if (err)
4a5f46f2 11502 goto out_free_irq;
1da177e4 11503
d8f4cd38 11504 if (test_irq && tg3_flag(tp, USING_MSI)) {
7938109f 11505 err = tg3_test_msi(tp);
fac9b83e 11506
7938109f 11507 if (err) {
f47c11ee 11508 tg3_full_lock(tp, 0);
944d980e 11509 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 11510 tg3_free_rings(tp);
f47c11ee 11511 tg3_full_unlock(tp);
7938109f 11512
4a5f46f2 11513 goto out_napi_fini;
7938109f 11514 }
fcfa0a32 11515
63c3a66f 11516 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
f6eb9b1f 11517 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 11518
f6eb9b1f
MC		 11519 tw32(PCIE_TRANSACTION_CFG,
11520 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 11521 }
7938109f
MC		 11522 }
11523
b02fd9e3
MC		 11524 tg3_phy_start(tp);
11525
aed93e0b
MC		 11526 tg3_hwmon_open(tp);
11527
f47c11ee 11528 tg3_full_lock(tp, 0);
1da177e4 11529
21f7638e 11530 tg3_timer_start(tp);
63c3a66f 11531 tg3_flag_set(tp, INIT_COMPLETE);
1da177e4
LT		 11532 tg3_enable_ints(tp);
11533
be947307
MC		 11534 if (init)
11535 tg3_ptp_init(tp);
11536 else
11537 tg3_ptp_resume(tp);
11538
11539
f47c11ee 11540 tg3_full_unlock(tp);
1da177e4 11541
fe5f5787 11542 netif_tx_start_all_queues(dev);
1da177e4 11543
06c03c02
MB		 11544 /*
11545 * Reset loopback feature if it was turned on while the device was down
11546 * make sure that it's installed properly now.
11547 */
11548 if (dev->features & NETIF_F_LOOPBACK)
11549 tg3_set_loopback(dev, dev->features);
11550
1da177e4 11551 return 0;
07b0173c 11552
4a5f46f2 11553out_free_irq:
4f125f42
MC		 11554 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11555 struct tg3_napi *tnapi = &tp->napi[i];
11556 free_irq(tnapi->irq_vec, tnapi);
11557 }
07b0173c 11558
4a5f46f2 11559out_napi_fini:
fed97810 11560 tg3_napi_disable(tp);
66cfd1bd 11561 tg3_napi_fini(tp);
07b0173c 11562 tg3_free_consistent(tp);
679563f4 11563
4a5f46f2 11564out_ints_fini:
679563f4 11565 tg3_ints_fini(tp);
d8f4cd38 11566
07b0173c 11567 return err;
1da177e4
LT		 11568}
11569
65138594 11570static void tg3_stop(struct tg3 *tp)
1da177e4 11571{
4f125f42 11572 int i;
1da177e4 11573
db219973 11574 tg3_reset_task_cancel(tp);
bd473da3 11575 tg3_netif_stop(tp);
1da177e4 11576
21f7638e 11577 tg3_timer_stop(tp);
1da177e4 11578
aed93e0b
MC		 11579 tg3_hwmon_close(tp);
11580
24bb4fb6
MC		 11581 tg3_phy_stop(tp);
11582
f47c11ee 11583 tg3_full_lock(tp, 1);
1da177e4
LT		 11584
11585 tg3_disable_ints(tp);
11586
944d980e 11587 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11588 tg3_free_rings(tp);
63c3a66f 11589 tg3_flag_clear(tp, INIT_COMPLETE);
1da177e4 11590
f47c11ee 11591 tg3_full_unlock(tp);
1da177e4 11592
4f125f42
MC		 11593 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11594 struct tg3_napi *tnapi = &tp->napi[i];
11595 free_irq(tnapi->irq_vec, tnapi);
11596 }
07b0173c
MC		 11597
11598 tg3_ints_fini(tp);
1da177e4 11599
66cfd1bd
MC		 11600 tg3_napi_fini(tp);
11601
1da177e4 11602 tg3_free_consistent(tp);
65138594
MC		 11603}
11604
d8f4cd38
MC		 11605static int tg3_open(struct net_device *dev)
11606{
11607 struct tg3 *tp = netdev_priv(dev);
11608 int err;
11609
11610 if (tp->fw_needed) {
11611 err = tg3_request_firmware(tp);
c4dab506
NS		 11612 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11613 if (err) {
11614 netdev_warn(tp->dev, "EEE capability disabled\n");
11615 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11616 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11617 netdev_warn(tp->dev, "EEE capability restored\n");
11618 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11619 }
11620 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
d8f4cd38
MC		 11621 if (err)
11622 return err;
11623 } else if (err) {
11624 netdev_warn(tp->dev, "TSO capability disabled\n");
11625 tg3_flag_clear(tp, TSO_CAPABLE);
11626 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11627 netdev_notice(tp->dev, "TSO capability restored\n");
11628 tg3_flag_set(tp, TSO_CAPABLE);
11629 }
11630 }
11631
f4a46d1f 11632 tg3_carrier_off(tp);
d8f4cd38
MC		 11633
11634 err = tg3_power_up(tp);
11635 if (err)
11636 return err;
11637
11638 tg3_full_lock(tp, 0);
11639
11640 tg3_disable_ints(tp);
11641 tg3_flag_clear(tp, INIT_COMPLETE);
11642
11643 tg3_full_unlock(tp);
11644
942d1af0
NS		 11645 err = tg3_start(tp,
11646 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11647 true, true);
d8f4cd38
MC		 11648 if (err) {
11649 tg3_frob_aux_power(tp, false);
11650 pci_set_power_state(tp->pdev, PCI_D3hot);
11651 }
be947307 11652
7d41e49a
MC		 11653 if (tg3_flag(tp, PTP_CAPABLE)) {
11654 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11655 &tp->pdev->dev);
11656 if (IS_ERR(tp->ptp_clock))
11657 tp->ptp_clock = NULL;
11658 }
11659
07b0173c 11660 return err;
1da177e4
LT		 11661}
11662
1da177e4
LT		 11663static int tg3_close(struct net_device *dev)
11664{
11665 struct tg3 *tp = netdev_priv(dev);
11666
be947307
MC		 11667 tg3_ptp_fini(tp);
11668
65138594 11669 tg3_stop(tp);
1da177e4 11670
92feeabf
MC		 11671 /* Clear stats across close / open calls */
11672 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11673 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
1da177e4 11674
8496e85c
RW		 11675 if (pci_device_is_present(tp->pdev)) {
11676 tg3_power_down_prepare(tp);
bc1c7567 11677
8496e85c
RW		 11678 tg3_carrier_off(tp);
11679 }
1da177e4
LT		 11680 return 0;
11681}
11682
511d2224 11683static inline u64 get_stat64(tg3_stat64_t *val)
816f8b86
SB		 11684{
11685 return ((u64)val->high << 32) | ((u64)val->low);
11686}
11687
65ec698d 11688static u64 tg3_calc_crc_errors(struct tg3 *tp)
1da177e4
LT		 11689{
11690 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11691
f07e9af3 11692 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a
JP		 11693 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11694 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 11695 u32 val;
11696
569a5df8
MC		 11697 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11698 tg3_writephy(tp, MII_TG3_TEST1,
11699 val | MII_TG3_TEST1_CRC_EN);
f08aa1a8 11700 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
1da177e4
LT		 11701 } else
11702 val = 0;
1da177e4
LT		 11703
11704 tp->phy_crc_errors += val;
11705
11706 return tp->phy_crc_errors;
11707 }
11708
11709 return get_stat64(&hw_stats->rx_fcs_errors);
11710}
11711
11712#define ESTAT_ADD(member) \
11713 estats->member = old_estats->member + \
511d2224 11714 get_stat64(&hw_stats->member)
1da177e4 11715
65ec698d 11716static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
1da177e4 11717{
1da177e4
LT		 11718 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11719 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11720
1da177e4
LT		 11721 ESTAT_ADD(rx_octets);
11722 ESTAT_ADD(rx_fragments);
11723 ESTAT_ADD(rx_ucast_packets);
11724 ESTAT_ADD(rx_mcast_packets);
11725 ESTAT_ADD(rx_bcast_packets);
11726 ESTAT_ADD(rx_fcs_errors);
11727 ESTAT_ADD(rx_align_errors);
11728 ESTAT_ADD(rx_xon_pause_rcvd);
11729 ESTAT_ADD(rx_xoff_pause_rcvd);
11730 ESTAT_ADD(rx_mac_ctrl_rcvd);
11731 ESTAT_ADD(rx_xoff_entered);
11732 ESTAT_ADD(rx_frame_too_long_errors);
11733 ESTAT_ADD(rx_jabbers);
11734 ESTAT_ADD(rx_undersize_packets);
11735 ESTAT_ADD(rx_in_length_errors);
11736 ESTAT_ADD(rx_out_length_errors);
11737 ESTAT_ADD(rx_64_or_less_octet_packets);
11738 ESTAT_ADD(rx_65_to_127_octet_packets);
11739 ESTAT_ADD(rx_128_to_255_octet_packets);
11740 ESTAT_ADD(rx_256_to_511_octet_packets);
11741 ESTAT_ADD(rx_512_to_1023_octet_packets);
11742 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11743 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11744 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11745 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11746 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11747
11748 ESTAT_ADD(tx_octets);
11749 ESTAT_ADD(tx_collisions);
11750 ESTAT_ADD(tx_xon_sent);
11751 ESTAT_ADD(tx_xoff_sent);
11752 ESTAT_ADD(tx_flow_control);
11753 ESTAT_ADD(tx_mac_errors);
11754 ESTAT_ADD(tx_single_collisions);
11755 ESTAT_ADD(tx_mult_collisions);
11756 ESTAT_ADD(tx_deferred);
11757 ESTAT_ADD(tx_excessive_collisions);
11758 ESTAT_ADD(tx_late_collisions);
11759 ESTAT_ADD(tx_collide_2times);
11760 ESTAT_ADD(tx_collide_3times);
11761 ESTAT_ADD(tx_collide_4times);
11762 ESTAT_ADD(tx_collide_5times);
11763 ESTAT_ADD(tx_collide_6times);
11764 ESTAT_ADD(tx_collide_7times);
11765 ESTAT_ADD(tx_collide_8times);
11766 ESTAT_ADD(tx_collide_9times);
11767 ESTAT_ADD(tx_collide_10times);
11768 ESTAT_ADD(tx_collide_11times);
11769 ESTAT_ADD(tx_collide_12times);
11770 ESTAT_ADD(tx_collide_13times);
11771 ESTAT_ADD(tx_collide_14times);
11772 ESTAT_ADD(tx_collide_15times);
11773 ESTAT_ADD(tx_ucast_packets);
11774 ESTAT_ADD(tx_mcast_packets);
11775 ESTAT_ADD(tx_bcast_packets);
11776 ESTAT_ADD(tx_carrier_sense_errors);
11777 ESTAT_ADD(tx_discards);
11778 ESTAT_ADD(tx_errors);
11779
11780 ESTAT_ADD(dma_writeq_full);
11781 ESTAT_ADD(dma_write_prioq_full);
11782 ESTAT_ADD(rxbds_empty);
11783 ESTAT_ADD(rx_discards);
11784 ESTAT_ADD(rx_errors);
11785 ESTAT_ADD(rx_threshold_hit);
11786
11787 ESTAT_ADD(dma_readq_full);
11788 ESTAT_ADD(dma_read_prioq_full);
11789 ESTAT_ADD(tx_comp_queue_full);
11790
11791 ESTAT_ADD(ring_set_send_prod_index);
11792 ESTAT_ADD(ring_status_update);
11793 ESTAT_ADD(nic_irqs);
11794 ESTAT_ADD(nic_avoided_irqs);
11795 ESTAT_ADD(nic_tx_threshold_hit);
11796
4452d099 11797 ESTAT_ADD(mbuf_lwm_thresh_hit);
1da177e4
LT		 11798}
11799
65ec698d 11800static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
1da177e4 11801{
511d2224 11802 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
1da177e4
LT		 11803 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11804
1da177e4
LT		 11805 stats->rx_packets = old_stats->rx_packets +
11806 get_stat64(&hw_stats->rx_ucast_packets) +
11807 get_stat64(&hw_stats->rx_mcast_packets) +
11808 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 11809
1da177e4
LT		 11810 stats->tx_packets = old_stats->tx_packets +
11811 get_stat64(&hw_stats->tx_ucast_packets) +
11812 get_stat64(&hw_stats->tx_mcast_packets) +
11813 get_stat64(&hw_stats->tx_bcast_packets);
11814
11815 stats->rx_bytes = old_stats->rx_bytes +
11816 get_stat64(&hw_stats->rx_octets);
11817 stats->tx_bytes = old_stats->tx_bytes +
11818 get_stat64(&hw_stats->tx_octets);
11819
11820 stats->rx_errors = old_stats->rx_errors +
4f63b877 11821 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 11822 stats->tx_errors = old_stats->tx_errors +
11823 get_stat64(&hw_stats->tx_errors) +
11824 get_stat64(&hw_stats->tx_mac_errors) +
11825 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11826 get_stat64(&hw_stats->tx_discards);
11827
11828 stats->multicast = old_stats->multicast +
11829 get_stat64(&hw_stats->rx_mcast_packets);
11830 stats->collisions = old_stats->collisions +
11831 get_stat64(&hw_stats->tx_collisions);
11832
11833 stats->rx_length_errors = old_stats->rx_length_errors +
11834 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11835 get_stat64(&hw_stats->rx_undersize_packets);
11836
1da177e4
LT		 11837 stats->rx_frame_errors = old_stats->rx_frame_errors +
11838 get_stat64(&hw_stats->rx_align_errors);
11839 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11840 get_stat64(&hw_stats->tx_discards);
11841 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11842 get_stat64(&hw_stats->tx_carrier_sense_errors);
11843
11844 stats->rx_crc_errors = old_stats->rx_crc_errors +
65ec698d 11845 tg3_calc_crc_errors(tp);
1da177e4 11846
4f63b877
JL		 11847 stats->rx_missed_errors = old_stats->rx_missed_errors +
11848 get_stat64(&hw_stats->rx_discards);
11849
b0057c51 11850 stats->rx_dropped = tp->rx_dropped;
48855432 11851 stats->tx_dropped = tp->tx_dropped;
1da177e4
LT		 11852}
11853
1da177e4
LT		 11854static int tg3_get_regs_len(struct net_device *dev)
11855{
97bd8e49 11856 return TG3_REG_BLK_SIZE;
1da177e4
LT		 11857}
11858
11859static void tg3_get_regs(struct net_device *dev,
11860 struct ethtool_regs *regs, void *_p)
11861{
1da177e4 11862 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 11863
11864 regs->version = 0;
11865
97bd8e49 11866 memset(_p, 0, TG3_REG_BLK_SIZE);
1da177e4 11867
80096068 11868 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
bc1c7567
MC		 11869 return;
11870
f47c11ee 11871 tg3_full_lock(tp, 0);
1da177e4 11872
97bd8e49 11873 tg3_dump_legacy_regs(tp, (u32 *)_p);
1da177e4 11874
f47c11ee 11875 tg3_full_unlock(tp);
1da177e4
LT		 11876}
11877
11878static int tg3_get_eeprom_len(struct net_device *dev)
11879{
11880 struct tg3 *tp = netdev_priv(dev);
11881
11882 return tp->nvram_size;
11883}
11884
1da177e4
LT		 11885static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11886{
11887 struct tg3 *tp = netdev_priv(dev);
11888 int ret;
11889 u8 *pd;
b9fc7dc5 11890 u32 i, offset, len, b_offset, b_count;
a9dc529d 11891 __be32 val;
1da177e4 11892
63c3a66f 11893 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 11894 return -EINVAL;
11895
1da177e4
LT		 11896 offset = eeprom->offset;
11897 len = eeprom->len;
11898 eeprom->len = 0;
11899
11900 eeprom->magic = TG3_EEPROM_MAGIC;
11901
11902 if (offset & 3) {
11903 /* adjustments to start on required 4 byte boundary */
11904 b_offset = offset & 3;
11905 b_count = 4 - b_offset;
11906 if (b_count > len) {
11907 /* i.e. offset=1 len=2 */
11908 b_count = len;
11909 }
a9dc529d 11910 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 11911 if (ret)
11912 return ret;
be98da6a 11913 memcpy(data, ((char *)&val) + b_offset, b_count);
1da177e4
LT		 11914 len -= b_count;
11915 offset += b_count;
c6cdf436 11916 eeprom->len += b_count;
1da177e4
LT		 11917 }
11918
25985edc 11919 /* read bytes up to the last 4 byte boundary */
1da177e4
LT		 11920 pd = &data[eeprom->len];
11921 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 11922 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 11923 if (ret) {
11924 eeprom->len += i;
11925 return ret;
11926 }
1da177e4
LT		 11927 memcpy(pd + i, &val, 4);
11928 }
11929 eeprom->len += i;
11930
11931 if (len & 3) {
11932 /* read last bytes not ending on 4 byte boundary */
11933 pd = &data[eeprom->len];
11934 b_count = len & 3;
11935 b_offset = offset + len - b_count;
a9dc529d 11936 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 11937 if (ret)
11938 return ret;
b9fc7dc5 11939 memcpy(pd, &val, b_count);
1da177e4
LT		 11940 eeprom->len += b_count;
11941 }
11942 return 0;
11943}
11944
1da177e4
LT		 11945static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11946{
11947 struct tg3 *tp = netdev_priv(dev);
11948 int ret;
b9fc7dc5 11949 u32 offset, len, b_offset, odd_len;
1da177e4 11950 u8 *buf;
a9dc529d 11951 __be32 start, end;
1da177e4 11952
63c3a66f 11953 if (tg3_flag(tp, NO_NVRAM) ||
df259d8c 11954 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 11955 return -EINVAL;
11956
11957 offset = eeprom->offset;
11958 len = eeprom->len;
11959
11960 if ((b_offset = (offset & 3))) {
11961 /* adjustments to start on required 4 byte boundary */
a9dc529d 11962 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 11963 if (ret)
11964 return ret;
1da177e4
LT		 11965 len += b_offset;
11966 offset &= ~3;
1c8594b4
MC		 11967 if (len < 4)
11968 len = 4;
1da177e4
LT		 11969 }
11970
11971 odd_len = 0;
1c8594b4 11972 if (len & 3) {
1da177e4
LT		 11973 /* adjustments to end on required 4 byte boundary */
11974 odd_len = 1;
11975 len = (len + 3) & ~3;
a9dc529d 11976 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 11977 if (ret)
11978 return ret;
1da177e4
LT		 11979 }
11980
11981 buf = data;
11982 if (b_offset || odd_len) {
11983 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 11984 if (!buf)
1da177e4
LT		 11985 return -ENOMEM;
11986 if (b_offset)
11987 memcpy(buf, &start, 4);
11988 if (odd_len)
11989 memcpy(buf+len-4, &end, 4);
11990 memcpy(buf + b_offset, data, eeprom->len);
11991 }
11992
11993 ret = tg3_nvram_write_block(tp, offset, len, buf);
11994
11995 if (buf != data)
11996 kfree(buf);
11997
11998 return ret;
11999}
12000
12001static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12002{
b02fd9e3
MC		 12003 struct tg3 *tp = netdev_priv(dev);
12004
63c3a66f 12005 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 12006 struct phy_device *phydev;
f07e9af3 12007 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12008 return -EAGAIN;
ead2402c 12009 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
3f0e3ad7 12010 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 12011 }
6aa20a22 12012
1da177e4
LT		 12013 cmd->supported = (SUPPORTED_Autoneg);
12014
f07e9af3 12015 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
1da177e4
LT		 12016 cmd->supported |= (SUPPORTED_1000baseT_Half |
12017 SUPPORTED_1000baseT_Full);
12018
f07e9af3 12019 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
1da177e4
LT		 12020 cmd->supported |= (SUPPORTED_100baseT_Half |
12021 SUPPORTED_100baseT_Full |
12022 SUPPORTED_10baseT_Half |
12023 SUPPORTED_10baseT_Full |
3bebab59 12024 SUPPORTED_TP);
ef348144
KK		 12025 cmd->port = PORT_TP;
12026 } else {
1da177e4 12027 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 12028 cmd->port = PORT_FIBRE;
12029 }
6aa20a22 12030
1da177e4 12031 cmd->advertising = tp->link_config.advertising;
5bb09778
MC		 12032 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12033 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12034 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12035 cmd->advertising |= ADVERTISED_Pause;
12036 } else {
12037 cmd->advertising |= ADVERTISED_Pause |
12038 ADVERTISED_Asym_Pause;
12039 }
12040 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12041 cmd->advertising |= ADVERTISED_Asym_Pause;
12042 }
12043 }
f4a46d1f 12044 if (netif_running(dev) && tp->link_up) {
70739497 12045 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
1da177e4 12046 cmd->duplex = tp->link_config.active_duplex;
859edb26 12047 cmd->lp_advertising = tp->link_config.rmt_adv;
e348c5e7
MC		 12048 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12049 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12050 cmd->eth_tp_mdix = ETH_TP_MDI_X;
12051 else
12052 cmd->eth_tp_mdix = ETH_TP_MDI;
12053 }
64c22182 12054 } else {
e740522e
MC		 12055 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
12056 cmd->duplex = DUPLEX_UNKNOWN;
e348c5e7 12057 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
1da177e4 12058 }
882e9793 12059 cmd->phy_address = tp->phy_addr;
7e5856bd 12060 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 12061 cmd->autoneg = tp->link_config.autoneg;
12062 cmd->maxtxpkt = 0;
12063 cmd->maxrxpkt = 0;
12064 return 0;
12065}
6aa20a22 12066
1da177e4
LT		 12067static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12068{
12069 struct tg3 *tp = netdev_priv(dev);
25db0338 12070 u32 speed = ethtool_cmd_speed(cmd);
6aa20a22 12071
63c3a66f 12072 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 12073 struct phy_device *phydev;
f07e9af3 12074 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12075 return -EAGAIN;
ead2402c 12076 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
3f0e3ad7 12077 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 12078 }
12079
7e5856bd
MC		 12080 if (cmd->autoneg != AUTONEG_ENABLE &&
12081 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 12082 return -EINVAL;
7e5856bd
MC		 12083
12084 if (cmd->autoneg == AUTONEG_DISABLE &&
12085 cmd->duplex != DUPLEX_FULL &&
12086 cmd->duplex != DUPLEX_HALF)
37ff238d 12087 return -EINVAL;
1da177e4 12088
7e5856bd
MC		 12089 if (cmd->autoneg == AUTONEG_ENABLE) {
12090 u32 mask = ADVERTISED_Autoneg |
12091 ADVERTISED_Pause |
12092 ADVERTISED_Asym_Pause;
12093
f07e9af3 12094 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
7e5856bd
MC		 12095 mask |= ADVERTISED_1000baseT_Half |
12096 ADVERTISED_1000baseT_Full;
12097
f07e9af3 12098 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
7e5856bd
MC		 12099 mask |= ADVERTISED_100baseT_Half |
12100 ADVERTISED_100baseT_Full |
12101 ADVERTISED_10baseT_Half |
12102 ADVERTISED_10baseT_Full |
12103 ADVERTISED_TP;
12104 else
12105 mask |= ADVERTISED_FIBRE;
12106
12107 if (cmd->advertising & ~mask)
12108 return -EINVAL;
12109
12110 mask &= (ADVERTISED_1000baseT_Half |
12111 ADVERTISED_1000baseT_Full |
12112 ADVERTISED_100baseT_Half |
12113 ADVERTISED_100baseT_Full |
12114 ADVERTISED_10baseT_Half |
12115 ADVERTISED_10baseT_Full);
12116
12117 cmd->advertising &= mask;
12118 } else {
f07e9af3 12119 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
25db0338 12120 if (speed != SPEED_1000)
7e5856bd
MC		 12121 return -EINVAL;
12122
12123 if (cmd->duplex != DUPLEX_FULL)
12124 return -EINVAL;
12125 } else {
25db0338
DD		 12126 if (speed != SPEED_100 &&
12127 speed != SPEED_10)
7e5856bd
MC		 12128 return -EINVAL;
12129 }
12130 }
12131
f47c11ee 12132 tg3_full_lock(tp, 0);
1da177e4
LT		 12133
12134 tp->link_config.autoneg = cmd->autoneg;
12135 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 12136 tp->link_config.advertising = (cmd->advertising |
12137 ADVERTISED_Autoneg);
e740522e
MC		 12138 tp->link_config.speed = SPEED_UNKNOWN;
12139 tp->link_config.duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 12140 } else {
12141 tp->link_config.advertising = 0;
25db0338 12142 tp->link_config.speed = speed;
1da177e4 12143 tp->link_config.duplex = cmd->duplex;
b02fd9e3 12144 }
6aa20a22 12145
fdad8de4
NS		 12146 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12147
ce20f161
NS		 12148 tg3_warn_mgmt_link_flap(tp);
12149
1da177e4 12150 if (netif_running(dev))
953c96e0 12151 tg3_setup_phy(tp, true);
1da177e4 12152
f47c11ee 12153 tg3_full_unlock(tp);
6aa20a22 12154
1da177e4
LT		 12155 return 0;
12156}
6aa20a22 12157
1da177e4
LT		 12158static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12159{
12160 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12161
68aad78c
RJ		 12162 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12163 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12164 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12165 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
1da177e4 12166}
6aa20a22 12167
1da177e4
LT		 12168static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12169{
12170 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12171
63c3a66f 12172 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 12173 wol->supported = WAKE_MAGIC;
12174 else
12175 wol->supported = 0;
1da177e4 12176 wol->wolopts = 0;
63c3a66f 12177 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 12178 wol->wolopts = WAKE_MAGIC;
12179 memset(&wol->sopass, 0, sizeof(wol->sopass));
12180}
6aa20a22 12181
1da177e4
LT		 12182static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12183{
12184 struct tg3 *tp = netdev_priv(dev);
12dac075 12185 struct device *dp = &tp->pdev->dev;
6aa20a22 12186
1da177e4
LT		 12187 if (wol->wolopts & ~WAKE_MAGIC)
12188 return -EINVAL;
12189 if ((wol->wolopts & WAKE_MAGIC) &&
63c3a66f 12190 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
1da177e4 12191 return -EINVAL;
6aa20a22 12192
f2dc0d18
RW		 12193 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12194
f2dc0d18 12195 if (device_may_wakeup(dp))
63c3a66f 12196 tg3_flag_set(tp, WOL_ENABLE);
f2dc0d18 12197 else
63c3a66f 12198 tg3_flag_clear(tp, WOL_ENABLE);
6aa20a22 12199
1da177e4
LT		 12200 return 0;
12201}
6aa20a22 12202
1da177e4
LT		 12203static u32 tg3_get_msglevel(struct net_device *dev)
12204{
12205 struct tg3 *tp = netdev_priv(dev);
12206 return tp->msg_enable;
12207}
6aa20a22 12208
1da177e4
LT		 12209static void tg3_set_msglevel(struct net_device *dev, u32 value)
12210{
12211 struct tg3 *tp = netdev_priv(dev);
12212 tp->msg_enable = value;
12213}
6aa20a22 12214
1da177e4
LT		 12215static int tg3_nway_reset(struct net_device *dev)
12216{
12217 struct tg3 *tp = netdev_priv(dev);
1da177e4 12218 int r;
6aa20a22 12219
1da177e4
LT		 12220 if (!netif_running(dev))
12221 return -EAGAIN;
12222
f07e9af3 12223 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
c94e3941
MC		 12224 return -EINVAL;
12225
ce20f161
NS		 12226 tg3_warn_mgmt_link_flap(tp);
12227
63c3a66f 12228 if (tg3_flag(tp, USE_PHYLIB)) {
f07e9af3 12229 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12230 return -EAGAIN;
ead2402c 12231 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]);
b02fd9e3
MC		 12232 } else {
12233 u32 bmcr;
12234
12235 spin_lock_bh(&tp->lock);
12236 r = -EINVAL;
12237 tg3_readphy(tp, MII_BMCR, &bmcr);
12238 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12239 ((bmcr & BMCR_ANENABLE) ||
f07e9af3 12240 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
b02fd9e3
MC		 12241 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12242 BMCR_ANENABLE);
12243 r = 0;
12244 }
12245 spin_unlock_bh(&tp->lock);
1da177e4 12246 }
6aa20a22 12247
1da177e4
LT		 12248 return r;
12249}
6aa20a22 12250
1da177e4
LT		 12251static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12252{
12253 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12254
2c49a44d 12255 ering->rx_max_pending = tp->rx_std_ring_mask;
63c3a66f 12256 if (tg3_flag(tp, JUMBO_RING_ENABLE))
2c49a44d 12257 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
4f81c32b
MC		 12258 else
12259 ering->rx_jumbo_max_pending = 0;
12260
12261 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 12262
12263 ering->rx_pending = tp->rx_pending;
63c3a66f 12264 if (tg3_flag(tp, JUMBO_RING_ENABLE))
4f81c32b
MC		 12265 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12266 else
12267 ering->rx_jumbo_pending = 0;
12268
f3f3f27e 12269 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 12270}
6aa20a22 12271
1da177e4
LT		 12272static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12273{
12274 struct tg3 *tp = netdev_priv(dev);
646c9edd 12275 int i, irq_sync = 0, err = 0;
6aa20a22 12276
2c49a44d
MC		 12277 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12278 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
bc3a9254
MC		 12279 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12280 (ering->tx_pending <= MAX_SKB_FRAGS) ||
63c3a66f 12281 (tg3_flag(tp, TSO_BUG) &&
bc3a9254 12282 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 12283 return -EINVAL;
6aa20a22 12284
bbe832c0 12285 if (netif_running(dev)) {
b02fd9e3 12286 tg3_phy_stop(tp);
1da177e4 12287 tg3_netif_stop(tp);
bbe832c0
MC		 12288 irq_sync = 1;
12289 }
1da177e4 12290
bbe832c0 12291 tg3_full_lock(tp, irq_sync);
6aa20a22 12292
1da177e4
LT		 12293 tp->rx_pending = ering->rx_pending;
12294
63c3a66f 12295 if (tg3_flag(tp, MAX_RXPEND_64) &&
1da177e4
LT		 12296 tp->rx_pending > 63)
12297 tp->rx_pending = 63;
12298 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd 12299
6fd45cb8 12300 for (i = 0; i < tp->irq_max; i++)
646c9edd 12301 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 12302
12303 if (netif_running(dev)) {
944d980e 12304 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12305 err = tg3_restart_hw(tp, false);
b9ec6c1b
MC		 12306 if (!err)
12307 tg3_netif_start(tp);
1da177e4
LT		 12308 }
12309
f47c11ee 12310 tg3_full_unlock(tp);
6aa20a22 12311
b02fd9e3
MC		 12312 if (irq_sync && !err)
12313 tg3_phy_start(tp);
12314
b9ec6c1b 12315 return err;
1da177e4 12316}
6aa20a22 12317
1da177e4
LT		 12318static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12319{
12320 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12321
63c3a66f 12322 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
8d018621 12323
4a2db503 12324 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
8d018621
MC		 12325 epause->rx_pause = 1;
12326 else
12327 epause->rx_pause = 0;
12328
4a2db503 12329 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
8d018621
MC		 12330 epause->tx_pause = 1;
12331 else
12332 epause->tx_pause = 0;
1da177e4 12333}
6aa20a22 12334
1da177e4
LT		 12335static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12336{
12337 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 12338 int err = 0;
6aa20a22 12339
ce20f161
NS		 12340 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12341 tg3_warn_mgmt_link_flap(tp);
12342
63c3a66f 12343 if (tg3_flag(tp, USE_PHYLIB)) {
2712168f
MC		 12344 u32 newadv;
12345 struct phy_device *phydev;
1da177e4 12346
ead2402c 12347 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
f47c11ee 12348
2712168f
MC		 12349 if (!(phydev->supported & SUPPORTED_Pause) ||
12350 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
2259dca3 12351 (epause->rx_pause != epause->tx_pause)))
2712168f 12352 return -EINVAL;
1da177e4 12353
2712168f
MC		 12354 tp->link_config.flowctrl = 0;
12355 if (epause->rx_pause) {
12356 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12357
12358 if (epause->tx_pause) {
12359 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12360 newadv = ADVERTISED_Pause;
b02fd9e3 12361 } else
2712168f
MC		 12362 newadv = ADVERTISED_Pause |
12363 ADVERTISED_Asym_Pause;
12364 } else if (epause->tx_pause) {
12365 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12366 newadv = ADVERTISED_Asym_Pause;
12367 } else
12368 newadv = 0;
12369
12370 if (epause->autoneg)
63c3a66f 12371 tg3_flag_set(tp, PAUSE_AUTONEG);
2712168f 12372 else
63c3a66f 12373 tg3_flag_clear(tp, PAUSE_AUTONEG);
2712168f 12374
f07e9af3 12375 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2712168f
MC		 12376 u32 oldadv = phydev->advertising &
12377 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12378 if (oldadv != newadv) {
12379 phydev->advertising &=
12380 ~(ADVERTISED_Pause |
12381 ADVERTISED_Asym_Pause);
12382 phydev->advertising |= newadv;
12383 if (phydev->autoneg) {
12384 /*
12385 * Always renegotiate the link to
12386 * inform our link partner of our
12387 * flow control settings, even if the
12388 * flow control is forced. Let
12389 * tg3_adjust_link() do the final
12390 * flow control setup.
12391 */
12392 return phy_start_aneg(phydev);
b02fd9e3 12393 }
b02fd9e3 12394 }
b02fd9e3 12395
2712168f 12396 if (!epause->autoneg)
b02fd9e3 12397 tg3_setup_flow_control(tp, 0, 0);
2712168f 12398 } else {
c6700ce2 12399 tp->link_config.advertising &=
2712168f
MC		 12400 ~(ADVERTISED_Pause |
12401 ADVERTISED_Asym_Pause);
c6700ce2 12402 tp->link_config.advertising |= newadv;
b02fd9e3
MC		 12403 }
12404 } else {
12405 int irq_sync = 0;
12406
12407 if (netif_running(dev)) {
12408 tg3_netif_stop(tp);
12409 irq_sync = 1;
12410 }
12411
12412 tg3_full_lock(tp, irq_sync);
12413
12414 if (epause->autoneg)
63c3a66f 12415 tg3_flag_set(tp, PAUSE_AUTONEG);
b02fd9e3 12416 else
63c3a66f 12417 tg3_flag_clear(tp, PAUSE_AUTONEG);
b02fd9e3 12418 if (epause->rx_pause)
e18ce346 12419 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 12420 else
e18ce346 12421 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 12422 if (epause->tx_pause)
e18ce346 12423 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 12424 else
e18ce346 12425 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 12426
12427 if (netif_running(dev)) {
12428 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12429 err = tg3_restart_hw(tp, false);
b02fd9e3
MC		 12430 if (!err)
12431 tg3_netif_start(tp);
12432 }
12433
12434 tg3_full_unlock(tp);
12435 }
6aa20a22 12436
fdad8de4
NS		 12437 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12438
b9ec6c1b 12439 return err;
1da177e4 12440}
6aa20a22 12441
de6f31eb 12442static int tg3_get_sset_count(struct net_device *dev, int sset)
1da177e4 12443{
b9f2c044
JG		 12444 switch (sset) {
12445 case ETH_SS_TEST:
12446 return TG3_NUM_TEST;
12447 case ETH_SS_STATS:
12448 return TG3_NUM_STATS;
12449 default:
12450 return -EOPNOTSUPP;
12451 }
4cafd3f5
MC		 12452}
12453
90415477
MC		 12454static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12455 u32 *rules __always_unused)
12456{
12457 struct tg3 *tp = netdev_priv(dev);
12458
12459 if (!tg3_flag(tp, SUPPORT_MSIX))
12460 return -EOPNOTSUPP;
12461
12462 switch (info->cmd) {
12463 case ETHTOOL_GRXRINGS:
12464 if (netif_running(tp->dev))
9102426a 12465 info->data = tp->rxq_cnt;
90415477
MC		 12466 else {
12467 info->data = num_online_cpus();
9102426a
MC		 12468 if (info->data > TG3_RSS_MAX_NUM_QS)
12469 info->data = TG3_RSS_MAX_NUM_QS;
90415477
MC		 12470 }
12471
12472 /* The first interrupt vector only
12473 * handles link interrupts.
12474 */
12475 info->data -= 1;
12476 return 0;
12477
12478 default:
12479 return -EOPNOTSUPP;
12480 }
12481}
12482
12483static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12484{
12485 u32 size = 0;
12486 struct tg3 *tp = netdev_priv(dev);
12487
12488 if (tg3_flag(tp, SUPPORT_MSIX))
12489 size = TG3_RSS_INDIR_TBL_SIZE;
12490
12491 return size;
12492}
12493
12494static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
12495{
12496 struct tg3 *tp = netdev_priv(dev);
12497 int i;
12498
12499 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12500 indir[i] = tp->rss_ind_tbl[i];
12501
12502 return 0;
12503}
12504
12505static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
12506{
12507 struct tg3 *tp = netdev_priv(dev);
12508 size_t i;
12509
12510 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12511 tp->rss_ind_tbl[i] = indir[i];
12512
12513 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12514 return 0;
12515
12516 /* It is legal to write the indirection
12517 * table while the device is running.
12518 */
12519 tg3_full_lock(tp, 0);
12520 tg3_rss_write_indir_tbl(tp);
12521 tg3_full_unlock(tp);
12522
12523 return 0;
12524}
12525
0968169c
MC		 12526static void tg3_get_channels(struct net_device *dev,
12527 struct ethtool_channels *channel)
12528{
12529 struct tg3 *tp = netdev_priv(dev);
12530 u32 deflt_qs = netif_get_num_default_rss_queues();
12531
12532 channel->max_rx = tp->rxq_max;
12533 channel->max_tx = tp->txq_max;
12534
12535 if (netif_running(dev)) {
12536 channel->rx_count = tp->rxq_cnt;
12537 channel->tx_count = tp->txq_cnt;
12538 } else {
12539 if (tp->rxq_req)
12540 channel->rx_count = tp->rxq_req;
12541 else
12542 channel->rx_count = min(deflt_qs, tp->rxq_max);
12543
12544 if (tp->txq_req)
12545 channel->tx_count = tp->txq_req;
12546 else
12547 channel->tx_count = min(deflt_qs, tp->txq_max);
12548 }
12549}
12550
12551static int tg3_set_channels(struct net_device *dev,
12552 struct ethtool_channels *channel)
12553{
12554 struct tg3 *tp = netdev_priv(dev);
12555
12556 if (!tg3_flag(tp, SUPPORT_MSIX))
12557 return -EOPNOTSUPP;
12558
12559 if (channel->rx_count > tp->rxq_max ||
12560 channel->tx_count > tp->txq_max)
12561 return -EINVAL;
12562
12563 tp->rxq_req = channel->rx_count;
12564 tp->txq_req = channel->tx_count;
12565
12566 if (!netif_running(dev))
12567 return 0;
12568
12569 tg3_stop(tp);
12570
f4a46d1f 12571 tg3_carrier_off(tp);
0968169c 12572
be947307 12573 tg3_start(tp, true, false, false);
0968169c
MC		 12574
12575 return 0;
12576}
12577
de6f31eb 12578static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1da177e4
LT		 12579{
12580 switch (stringset) {
12581 case ETH_SS_STATS:
12582 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
12583 break;
4cafd3f5
MC		 12584 case ETH_SS_TEST:
12585 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
12586 break;
1da177e4
LT		 12587 default:
12588 WARN_ON(1); /* we need a WARN() */
12589 break;
12590 }
12591}
12592
81b8709c 12593static int tg3_set_phys_id(struct net_device *dev,
12594 enum ethtool_phys_id_state state)
4009a93d
MC		 12595{
12596 struct tg3 *tp = netdev_priv(dev);
4009a93d
MC		 12597
12598 if (!netif_running(tp->dev))
12599 return -EAGAIN;
12600
81b8709c 12601 switch (state) {
12602 case ETHTOOL_ID_ACTIVE:
fce55922 12603 return 1; /* cycle on/off once per second */
4009a93d 12604
81b8709c 12605 case ETHTOOL_ID_ON:
12606 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12607 LED_CTRL_1000MBPS_ON |
12608 LED_CTRL_100MBPS_ON |
12609 LED_CTRL_10MBPS_ON |
12610 LED_CTRL_TRAFFIC_OVERRIDE |
12611 LED_CTRL_TRAFFIC_BLINK |
12612 LED_CTRL_TRAFFIC_LED);
12613 break;
6aa20a22 12614
81b8709c 12615 case ETHTOOL_ID_OFF:
12616 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12617 LED_CTRL_TRAFFIC_OVERRIDE);
12618 break;
4009a93d 12619
81b8709c 12620 case ETHTOOL_ID_INACTIVE:
12621 tw32(MAC_LED_CTRL, tp->led_ctrl);
12622 break;
4009a93d 12623 }
81b8709c 12624
4009a93d
MC		 12625 return 0;
12626}
12627
de6f31eb 12628static void tg3_get_ethtool_stats(struct net_device *dev,
1da177e4
LT		 12629 struct ethtool_stats *estats, u64 *tmp_stats)
12630{
12631 struct tg3 *tp = netdev_priv(dev);
0e6c9da3 12632
b546e46f
MC		 12633 if (tp->hw_stats)
12634 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12635 else
12636 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
1da177e4
LT		 12637}
12638
535a490e 12639static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
c3e94500
MC		 12640{
12641 int i;
12642 __be32 *buf;
12643 u32 offset = 0, len = 0;
12644 u32 magic, val;
12645
63c3a66f 12646 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
c3e94500
MC		 12647 return NULL;
12648
12649 if (magic == TG3_EEPROM_MAGIC) {
12650 for (offset = TG3_NVM_DIR_START;
12651 offset < TG3_NVM_DIR_END;
12652 offset += TG3_NVM_DIRENT_SIZE) {
12653 if (tg3_nvram_read(tp, offset, &val))
12654 return NULL;
12655
12656 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12657 TG3_NVM_DIRTYPE_EXTVPD)
12658 break;
12659 }
12660
12661 if (offset != TG3_NVM_DIR_END) {
12662 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12663 if (tg3_nvram_read(tp, offset + 4, &offset))
12664 return NULL;
12665
12666 offset = tg3_nvram_logical_addr(tp, offset);
12667 }
12668 }
12669
12670 if (!offset || !len) {
12671 offset = TG3_NVM_VPD_OFF;
12672 len = TG3_NVM_VPD_LEN;
12673 }
12674
12675 buf = kmalloc(len, GFP_KERNEL);
12676 if (buf == NULL)
12677 return NULL;
12678
12679 if (magic == TG3_EEPROM_MAGIC) {
12680 for (i = 0; i < len; i += 4) {
12681 /* The data is in little-endian format in NVRAM.
12682 * Use the big-endian read routines to preserve
12683 * the byte order as it exists in NVRAM.
12684 */
12685 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12686 goto error;
12687 }
12688 } else {
12689 u8 *ptr;
12690 ssize_t cnt;
12691 unsigned int pos = 0;
12692
12693 ptr = (u8 *)&buf[0];
12694 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12695 cnt = pci_read_vpd(tp->pdev, pos,
12696 len - pos, ptr);
12697 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12698 cnt = 0;
12699 else if (cnt < 0)
12700 goto error;
12701 }
12702 if (pos != len)
12703 goto error;
12704 }
12705
535a490e
MC		 12706 *vpdlen = len;
12707
c3e94500
MC		 12708 return buf;
12709
12710error:
12711 kfree(buf);
12712 return NULL;
12713}
12714
566f86ad 12715#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 12716#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12717#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12718#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
727a6d9f
MC		 12719#define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12720#define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
bda18faf 12721#define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
b16250e3
MC		 12722#define NVRAM_SELFBOOT_HW_SIZE 0x20
12723#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 12724
12725static int tg3_test_nvram(struct tg3 *tp)
12726{
535a490e 12727 u32 csum, magic, len;
a9dc529d 12728 __be32 *buf;
ab0049b4 12729 int i, j, k, err = 0, size;
566f86ad 12730
63c3a66f 12731 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 12732 return 0;
12733
e4f34110 12734 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 12735 return -EIO;
12736
1b27777a
MC		 12737 if (magic == TG3_EEPROM_MAGIC)
12738 size = NVRAM_TEST_SIZE;
b16250e3 12739 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 12740 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12741 TG3_EEPROM_SB_FORMAT_1) {
12742 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12743 case TG3_EEPROM_SB_REVISION_0:
12744 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12745 break;
12746 case TG3_EEPROM_SB_REVISION_2:
12747 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12748 break;
12749 case TG3_EEPROM_SB_REVISION_3:
12750 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12751 break;
727a6d9f
MC		 12752 case TG3_EEPROM_SB_REVISION_4:
12753 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12754 break;
12755 case TG3_EEPROM_SB_REVISION_5:
12756 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12757 break;
12758 case TG3_EEPROM_SB_REVISION_6:
12759 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12760 break;
a5767dec 12761 default:
727a6d9f 12762 return -EIO;
a5767dec
MC		 12763 }
12764 } else
1b27777a 12765 return 0;
b16250e3
MC		 12766 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12767 size = NVRAM_SELFBOOT_HW_SIZE;
12768 else
1b27777a
MC		 12769 return -EIO;
12770
12771 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 12772 if (buf == NULL)
12773 return -ENOMEM;
12774
1b27777a
MC		 12775 err = -EIO;
12776 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 12777 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12778 if (err)
566f86ad 12779 break;
566f86ad 12780 }
1b27777a 12781 if (i < size)
566f86ad
MC		 12782 goto out;
12783
1b27777a 12784 /* Selfboot format */
a9dc529d 12785 magic = be32_to_cpu(buf[0]);
b9fc7dc5 12786 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 12787 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 12788 u8 *buf8 = (u8 *) buf, csum8 = 0;
12789
b9fc7dc5 12790 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 12791 TG3_EEPROM_SB_REVISION_2) {
12792 /* For rev 2, the csum doesn't include the MBA. */
12793 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12794 csum8 += buf8[i];
12795 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12796 csum8 += buf8[i];
12797 } else {
12798 for (i = 0; i < size; i++)
12799 csum8 += buf8[i];
12800 }
1b27777a 12801
ad96b485
AB		 12802 if (csum8 == 0) {
12803 err = 0;
12804 goto out;
12805 }
12806
12807 err = -EIO;
12808 goto out;
1b27777a 12809 }
566f86ad 12810
b9fc7dc5 12811 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 12812 TG3_EEPROM_MAGIC_HW) {
12813 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 12814 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 12815 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 12816
12817 /* Separate the parity bits and the data bytes. */
12818 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12819 if ((i == 0) || (i == 8)) {
12820 int l;
12821 u8 msk;
12822
12823 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12824 parity[k++] = buf8[i] & msk;
12825 i++;
859a5887 12826 } else if (i == 16) {
b16250e3
MC		 12827 int l;
12828 u8 msk;
12829
12830 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12831 parity[k++] = buf8[i] & msk;
12832 i++;
12833
12834 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12835 parity[k++] = buf8[i] & msk;
12836 i++;
12837 }
12838 data[j++] = buf8[i];
12839 }
12840
12841 err = -EIO;
12842 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12843 u8 hw8 = hweight8(data[i]);
12844
12845 if ((hw8 & 0x1) && parity[i])
12846 goto out;
12847 else if (!(hw8 & 0x1) && !parity[i])
12848 goto out;
12849 }
12850 err = 0;
12851 goto out;
12852 }
12853
01c3a392
MC		 12854 err = -EIO;
12855
566f86ad
MC		 12856 /* Bootstrap checksum at offset 0x10 */
12857 csum = calc_crc((unsigned char *) buf, 0x10);
01c3a392 12858 if (csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 12859 goto out;
12860
12861 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12862 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
01c3a392 12863 if (csum != le32_to_cpu(buf[0xfc/4]))
a9dc529d 12864 goto out;
566f86ad 12865
c3e94500
MC		 12866 kfree(buf);
12867
535a490e 12868 buf = tg3_vpd_readblock(tp, &len);
c3e94500
MC		 12869 if (!buf)
12870 return -ENOMEM;
d4894f3e 12871
535a490e 12872 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
d4894f3e
MC		 12873 if (i > 0) {
12874 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12875 if (j < 0)
12876 goto out;
12877
535a490e 12878 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
d4894f3e
MC		 12879 goto out;
12880
12881 i += PCI_VPD_LRDT_TAG_SIZE;
12882 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12883 PCI_VPD_RO_KEYWORD_CHKSUM);
12884 if (j > 0) {
12885 u8 csum8 = 0;
12886
12887 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12888
12889 for (i = 0; i <= j; i++)
12890 csum8 += ((u8 *)buf)[i];
12891
12892 if (csum8)
12893 goto out;
12894 }
12895 }
12896
566f86ad
MC		 12897 err = 0;
12898
12899out:
12900 kfree(buf);
12901 return err;
12902}
12903
ca43007a
MC		 12904#define TG3_SERDES_TIMEOUT_SEC 2
12905#define TG3_COPPER_TIMEOUT_SEC 6
12906
12907static int tg3_test_link(struct tg3 *tp)
12908{
12909 int i, max;
12910
12911 if (!netif_running(tp->dev))
12912 return -ENODEV;
12913
f07e9af3 12914 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
ca43007a
MC		 12915 max = TG3_SERDES_TIMEOUT_SEC;
12916 else
12917 max = TG3_COPPER_TIMEOUT_SEC;
12918
12919 for (i = 0; i < max; i++) {
f4a46d1f 12920 if (tp->link_up)
ca43007a
MC		 12921 return 0;
12922
12923 if (msleep_interruptible(1000))
12924 break;
12925 }
12926
12927 return -EIO;
12928}
12929
a71116d1 12930/* Only test the commonly used registers */
30ca3e37 12931static int tg3_test_registers(struct tg3 *tp)
a71116d1 12932{
b16250e3 12933 int i, is_5705, is_5750;
a71116d1
MC		 12934 u32 offset, read_mask, write_mask, val, save_val, read_val;
12935 static struct {
12936 u16 offset;
12937 u16 flags;
12938#define TG3_FL_5705 0x1
12939#define TG3_FL_NOT_5705 0x2
12940#define TG3_FL_NOT_5788 0x4
b16250e3 12941#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 12942 u32 read_mask;
12943 u32 write_mask;
12944 } reg_tbl[] = {
12945 /* MAC Control Registers */
12946 { MAC_MODE, TG3_FL_NOT_5705,
12947 0x00000000, 0x00ef6f8c },
12948 { MAC_MODE, TG3_FL_5705,
12949 0x00000000, 0x01ef6b8c },
12950 { MAC_STATUS, TG3_FL_NOT_5705,
12951 0x03800107, 0x00000000 },
12952 { MAC_STATUS, TG3_FL_5705,
12953 0x03800100, 0x00000000 },
12954 { MAC_ADDR_0_HIGH, 0x0000,
12955 0x00000000, 0x0000ffff },
12956 { MAC_ADDR_0_LOW, 0x0000,
c6cdf436 12957 0x00000000, 0xffffffff },
a71116d1
MC		 12958 { MAC_RX_MTU_SIZE, 0x0000,
12959 0x00000000, 0x0000ffff },
12960 { MAC_TX_MODE, 0x0000,
12961 0x00000000, 0x00000070 },
12962 { MAC_TX_LENGTHS, 0x0000,
12963 0x00000000, 0x00003fff },
12964 { MAC_RX_MODE, TG3_FL_NOT_5705,
12965 0x00000000, 0x000007fc },
12966 { MAC_RX_MODE, TG3_FL_5705,
12967 0x00000000, 0x000007dc },
12968 { MAC_HASH_REG_0, 0x0000,
12969 0x00000000, 0xffffffff },
12970 { MAC_HASH_REG_1, 0x0000,
12971 0x00000000, 0xffffffff },
12972 { MAC_HASH_REG_2, 0x0000,
12973 0x00000000, 0xffffffff },
12974 { MAC_HASH_REG_3, 0x0000,
12975 0x00000000, 0xffffffff },
12976
12977 /* Receive Data and Receive BD Initiator Control Registers. */
12978 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
12979 0x00000000, 0xffffffff },
12980 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
12981 0x00000000, 0xffffffff },
12982 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
12983 0x00000000, 0x00000003 },
12984 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
12985 0x00000000, 0xffffffff },
12986 { RCVDBDI_STD_BD+0, 0x0000,
12987 0x00000000, 0xffffffff },
12988 { RCVDBDI_STD_BD+4, 0x0000,
12989 0x00000000, 0xffffffff },
12990 { RCVDBDI_STD_BD+8, 0x0000,
12991 0x00000000, 0xffff0002 },
12992 { RCVDBDI_STD_BD+0xc, 0x0000,
12993 0x00000000, 0xffffffff },
6aa20a22 12994
a71116d1
MC		 12995 /* Receive BD Initiator Control Registers. */
12996 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
12997 0x00000000, 0xffffffff },
12998 { RCVBDI_STD_THRESH, TG3_FL_5705,
12999 0x00000000, 0x000003ff },
13000 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
13001 0x00000000, 0xffffffff },
6aa20a22 13002
a71116d1
MC		 13003 /* Host Coalescing Control Registers. */
13004 { HOSTCC_MODE, TG3_FL_NOT_5705,
13005 0x00000000, 0x00000004 },
13006 { HOSTCC_MODE, TG3_FL_5705,
13007 0x00000000, 0x000000f6 },
13008 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13009 0x00000000, 0xffffffff },
13010 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13011 0x00000000, 0x000003ff },
13012 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13013 0x00000000, 0xffffffff },
13014 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13015 0x00000000, 0x000003ff },
13016 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13017 0x00000000, 0xffffffff },
13018 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13019 0x00000000, 0x000000ff },
13020 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13021 0x00000000, 0xffffffff },
13022 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13023 0x00000000, 0x000000ff },
13024 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13025 0x00000000, 0xffffffff },
13026 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13027 0x00000000, 0xffffffff },
13028 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13029 0x00000000, 0xffffffff },
13030 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13031 0x00000000, 0x000000ff },
13032 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13033 0x00000000, 0xffffffff },
13034 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13035 0x00000000, 0x000000ff },
13036 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13037 0x00000000, 0xffffffff },
13038 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13039 0x00000000, 0xffffffff },
13040 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13041 0x00000000, 0xffffffff },
13042 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13043 0x00000000, 0xffffffff },
13044 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13045 0x00000000, 0xffffffff },
13046 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13047 0xffffffff, 0x00000000 },
13048 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13049 0xffffffff, 0x00000000 },
13050
13051 /* Buffer Manager Control Registers. */
b16250e3 13052 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 13053 0x00000000, 0x007fff80 },
b16250e3 13054 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 13055 0x00000000, 0x007fffff },
13056 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13057 0x00000000, 0x0000003f },
13058 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13059 0x00000000, 0x000001ff },
13060 { BUFMGR_MB_HIGH_WATER, 0x0000,
13061 0x00000000, 0x000001ff },
13062 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13063 0xffffffff, 0x00000000 },
13064 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13065 0xffffffff, 0x00000000 },
6aa20a22 13066
a71116d1
MC		 13067 /* Mailbox Registers */
13068 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13069 0x00000000, 0x000001ff },
13070 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13071 0x00000000, 0x000001ff },
13072 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13073 0x00000000, 0x000007ff },
13074 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13075 0x00000000, 0x000001ff },
13076
13077 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13078 };
13079
b16250e3 13080 is_5705 = is_5750 = 0;
63c3a66f 13081 if (tg3_flag(tp, 5705_PLUS)) {
a71116d1 13082 is_5705 = 1;
63c3a66f 13083 if (tg3_flag(tp, 5750_PLUS))
b16250e3
MC		 13084 is_5750 = 1;
13085 }
a71116d1
MC		 13086
13087 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13088 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13089 continue;
13090
13091 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13092 continue;
13093
63c3a66f 13094 if (tg3_flag(tp, IS_5788) &&
a71116d1
MC		 13095 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13096 continue;
13097
b16250e3
MC		 13098 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13099 continue;
13100
a71116d1
MC		 13101 offset = (u32) reg_tbl[i].offset;
13102 read_mask = reg_tbl[i].read_mask;
13103 write_mask = reg_tbl[i].write_mask;
13104
13105 /* Save the original register content */
13106 save_val = tr32(offset);
13107
13108 /* Determine the read-only value. */
13109 read_val = save_val & read_mask;
13110
13111 /* Write zero to the register, then make sure the read-only bits
13112 * are not changed and the read/write bits are all zeros.
13113 */
13114 tw32(offset, 0);
13115
13116 val = tr32(offset);
13117
13118 /* Test the read-only and read/write bits. */
13119 if (((val & read_mask) != read_val) || (val & write_mask))
13120 goto out;
13121
13122 /* Write ones to all the bits defined by RdMask and WrMask, then
13123 * make sure the read-only bits are not changed and the
13124 * read/write bits are all ones.
13125 */
13126 tw32(offset, read_mask | write_mask);
13127
13128 val = tr32(offset);
13129
13130 /* Test the read-only bits. */
13131 if ((val & read_mask) != read_val)
13132 goto out;
13133
13134 /* Test the read/write bits. */
13135 if ((val & write_mask) != write_mask)
13136 goto out;
13137
13138 tw32(offset, save_val);
13139 }
13140
13141 return 0;
13142
13143out:
9f88f29f 13144 if (netif_msg_hw(tp))
2445e461
MC		 13145 netdev_err(tp->dev,
13146 "Register test failed at offset %x\n", offset);
a71116d1
MC		 13147 tw32(offset, save_val);
13148 return -EIO;
13149}
13150
7942e1db
MC		 13151static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13152{
f71e1309 13153 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 13154 int i;
13155 u32 j;
13156
e9edda69 13157 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 13158 for (j = 0; j < len; j += 4) {
13159 u32 val;
13160
13161 tg3_write_mem(tp, offset + j, test_pattern[i]);
13162 tg3_read_mem(tp, offset + j, &val);
13163 if (val != test_pattern[i])
13164 return -EIO;
13165 }
13166 }
13167 return 0;
13168}
13169
13170static int tg3_test_memory(struct tg3 *tp)
13171{
13172 static struct mem_entry {
13173 u32 offset;
13174 u32 len;
13175 } mem_tbl_570x[] = {
38690194 13176 { 0x00000000, 0x00b50},
7942e1db
MC		 13177 { 0x00002000, 0x1c000},
13178 { 0xffffffff, 0x00000}
13179 }, mem_tbl_5705[] = {
13180 { 0x00000100, 0x0000c},
13181 { 0x00000200, 0x00008},
7942e1db
MC		 13182 { 0x00004000, 0x00800},
13183 { 0x00006000, 0x01000},
13184 { 0x00008000, 0x02000},
13185 { 0x00010000, 0x0e000},
13186 { 0xffffffff, 0x00000}
79f4d13a
MC		 13187 }, mem_tbl_5755[] = {
13188 { 0x00000200, 0x00008},
13189 { 0x00004000, 0x00800},
13190 { 0x00006000, 0x00800},
13191 { 0x00008000, 0x02000},
13192 { 0x00010000, 0x0c000},
13193 { 0xffffffff, 0x00000}
b16250e3
MC		 13194 }, mem_tbl_5906[] = {
13195 { 0x00000200, 0x00008},
13196 { 0x00004000, 0x00400},
13197 { 0x00006000, 0x00400},
13198 { 0x00008000, 0x01000},
13199 { 0x00010000, 0x01000},
13200 { 0xffffffff, 0x00000}
8b5a6c42
MC		 13201 }, mem_tbl_5717[] = {
13202 { 0x00000200, 0x00008},
13203 { 0x00010000, 0x0a000},
13204 { 0x00020000, 0x13c00},
13205 { 0xffffffff, 0x00000}
13206 }, mem_tbl_57765[] = {
13207 { 0x00000200, 0x00008},
13208 { 0x00004000, 0x00800},
13209 { 0x00006000, 0x09800},
13210 { 0x00010000, 0x0a000},
13211 { 0xffffffff, 0x00000}
7942e1db
MC		 13212 };
13213 struct mem_entry *mem_tbl;
13214 int err = 0;
13215 int i;
13216
63c3a66f 13217 if (tg3_flag(tp, 5717_PLUS))
8b5a6c42 13218 mem_tbl = mem_tbl_5717;
c65a17f4 13219 else if (tg3_flag(tp, 57765_CLASS) ||
4153577a 13220 tg3_asic_rev(tp) == ASIC_REV_5762)
8b5a6c42 13221 mem_tbl = mem_tbl_57765;
63c3a66f 13222 else if (tg3_flag(tp, 5755_PLUS))
321d32a0 13223 mem_tbl = mem_tbl_5755;
4153577a 13224 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
321d32a0 13225 mem_tbl = mem_tbl_5906;
63c3a66f 13226 else if (tg3_flag(tp, 5705_PLUS))
321d32a0
MC		 13227 mem_tbl = mem_tbl_5705;
13228 else
7942e1db
MC		 13229 mem_tbl = mem_tbl_570x;
13230
13231 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
be98da6a
MC		 13232 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13233 if (err)
7942e1db
MC		 13234 break;
13235 }
6aa20a22 13236
7942e1db
MC		 13237 return err;
13238}
13239
bb158d69
MC		 13240#define TG3_TSO_MSS 500
13241
13242#define TG3_TSO_IP_HDR_LEN 20
13243#define TG3_TSO_TCP_HDR_LEN 20
13244#define TG3_TSO_TCP_OPT_LEN 12
13245
13246static const u8 tg3_tso_header[] = {
132470x08, 0x00,
132480x45, 0x00, 0x00, 0x00,
132490x00, 0x00, 0x40, 0x00,
132500x40, 0x06, 0x00, 0x00,
132510x0a, 0x00, 0x00, 0x01,
132520x0a, 0x00, 0x00, 0x02,
132530x0d, 0x00, 0xe0, 0x00,
132540x00, 0x00, 0x01, 0x00,
132550x00, 0x00, 0x02, 0x00,
132560x80, 0x10, 0x10, 0x00,
132570x14, 0x09, 0x00, 0x00,
132580x01, 0x01, 0x08, 0x0a,
132590x11, 0x11, 0x11, 0x11,
132600x11, 0x11, 0x11, 0x11,
13261};
9f40dead 13262
28a45957 13263static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
c76949a6 13264{
5e5a7f37 13265 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
bb158d69 13266 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
84b67b27 13267 u32 budget;
9205fd9c
ED		 13268 struct sk_buff *skb;
13269 u8 *tx_data, *rx_data;
c76949a6
MC		 13270 dma_addr_t map;
13271 int num_pkts, tx_len, rx_len, i, err;
13272 struct tg3_rx_buffer_desc *desc;
898a56f8 13273 struct tg3_napi *tnapi, *rnapi;
8fea32b9 13274 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
c76949a6 13275
c8873405
MC		 13276 tnapi = &tp->napi[0];
13277 rnapi = &tp->napi[0];
0c1d0e2b 13278 if (tp->irq_cnt > 1) {
63c3a66f 13279 if (tg3_flag(tp, ENABLE_RSS))
1da85aa3 13280 rnapi = &tp->napi[1];
63c3a66f 13281 if (tg3_flag(tp, ENABLE_TSS))
c8873405 13282 tnapi = &tp->napi[1];
0c1d0e2b 13283 }
fd2ce37f 13284 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 13285
c76949a6
MC		 13286 err = -EIO;
13287
4852a861 13288 tx_len = pktsz;
a20e9c62 13289 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 13290 if (!skb)
13291 return -ENOMEM;
13292
c76949a6 13293 tx_data = skb_put(skb, tx_len);
d458cdf7
JP		 13294 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13295 memset(tx_data + ETH_ALEN, 0x0, 8);
c76949a6 13296
4852a861 13297 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
c76949a6 13298
28a45957 13299 if (tso_loopback) {
bb158d69
MC		 13300 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13301
13302 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13303 TG3_TSO_TCP_OPT_LEN;
13304
13305 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13306 sizeof(tg3_tso_header));
13307 mss = TG3_TSO_MSS;
13308
13309 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13310 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13311
13312 /* Set the total length field in the IP header */
13313 iph->tot_len = htons((u16)(mss + hdr_len));
13314
13315 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13316 TXD_FLAG_CPU_POST_DMA);
13317
63c3a66f
JP		 13318 if (tg3_flag(tp, HW_TSO_1) ||
13319 tg3_flag(tp, HW_TSO_2) ||
13320 tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13321 struct tcphdr *th;
13322 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13323 th = (struct tcphdr *)&tx_data[val];
13324 th->check = 0;
13325 } else
13326 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13327
63c3a66f 13328 if (tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13329 mss |= (hdr_len & 0xc) << 12;
13330 if (hdr_len & 0x10)
13331 base_flags |= 0x00000010;
13332 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 13333 } else if (tg3_flag(tp, HW_TSO_2))
bb158d69 13334 mss |= hdr_len << 9;
63c3a66f 13335 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 13336 tg3_asic_rev(tp) == ASIC_REV_5705) {
bb158d69
MC		 13337 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13338 } else {
13339 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13340 }
13341
13342 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13343 } else {
13344 num_pkts = 1;
13345 data_off = ETH_HLEN;
c441b456
MC		 13346
13347 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13348 tx_len > VLAN_ETH_FRAME_LEN)
13349 base_flags |= TXD_FLAG_JMB_PKT;
bb158d69
MC		 13350 }
13351
13352 for (i = data_off; i < tx_len; i++)
c76949a6
MC		 13353 tx_data[i] = (u8) (i & 0xff);
13354
f4188d8a
AD		 13355 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13356 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 13357 dev_kfree_skb(skb);
13358 return -EIO;
13359 }
c76949a6 13360
0d681b27
MC		 13361 val = tnapi->tx_prod;
13362 tnapi->tx_buffers[val].skb = skb;
13363 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13364
c76949a6 13365 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13366 rnapi->coal_now);
c76949a6
MC		 13367
13368 udelay(10);
13369
898a56f8 13370 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 13371
84b67b27
MC		 13372 budget = tg3_tx_avail(tnapi);
13373 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
d1a3b737
MC		 13374 base_flags | TXD_FLAG_END, mss, 0)) {
13375 tnapi->tx_buffers[val].skb = NULL;
13376 dev_kfree_skb(skb);
13377 return -EIO;
13378 }
c76949a6 13379
f3f3f27e 13380 tnapi->tx_prod++;
c76949a6 13381
6541b806
MC		 13382 /* Sync BD data before updating mailbox */
13383 wmb();
13384
f3f3f27e
MC		 13385 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13386 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 13387
13388 udelay(10);
13389
303fc921
MC		 13390 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13391 for (i = 0; i < 35; i++) {
c76949a6 13392 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13393 coal_now);
c76949a6
MC		 13394
13395 udelay(10);
13396
898a56f8
MC		 13397 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13398 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 13399 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 13400 (rx_idx == (rx_start_idx + num_pkts)))
13401 break;
13402 }
13403
ba1142e4 13404 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
c76949a6
MC		 13405 dev_kfree_skb(skb);
13406
f3f3f27e 13407 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 13408 goto out;
13409
13410 if (rx_idx != rx_start_idx + num_pkts)
13411 goto out;
13412
bb158d69
MC		 13413 val = data_off;
13414 while (rx_idx != rx_start_idx) {
13415 desc = &rnapi->rx_rcb[rx_start_idx++];
13416 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13417 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
c76949a6 13418
bb158d69
MC		 13419 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13420 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13421 goto out;
c76949a6 13422
bb158d69
MC		 13423 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13424 - ETH_FCS_LEN;
c76949a6 13425
28a45957 13426 if (!tso_loopback) {
bb158d69
MC		 13427 if (rx_len != tx_len)
13428 goto out;
4852a861 13429
bb158d69
MC		 13430 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13431 if (opaque_key != RXD_OPAQUE_RING_STD)
13432 goto out;
13433 } else {
13434 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13435 goto out;
13436 }
13437 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13438 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
54e0a67f 13439 >> RXD_TCPCSUM_SHIFT != 0xffff) {
4852a861 13440 goto out;
bb158d69 13441 }
4852a861 13442
bb158d69 13443 if (opaque_key == RXD_OPAQUE_RING_STD) {
9205fd9c 13444 rx_data = tpr->rx_std_buffers[desc_idx].data;
bb158d69
MC		 13445 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13446 mapping);
13447 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
9205fd9c 13448 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
bb158d69
MC		 13449 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13450 mapping);
13451 } else
13452 goto out;
c76949a6 13453
bb158d69
MC		 13454 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13455 PCI_DMA_FROMDEVICE);
c76949a6 13456
9205fd9c 13457 rx_data += TG3_RX_OFFSET(tp);
bb158d69 13458 for (i = data_off; i < rx_len; i++, val++) {
9205fd9c 13459 if (*(rx_data + i) != (u8) (val & 0xff))
bb158d69
MC		 13460 goto out;
13461 }
c76949a6 13462 }
bb158d69 13463
c76949a6 13464 err = 0;
6aa20a22 13465
9205fd9c 13466 /* tg3_free_rings will unmap and free the rx_data */
c76949a6
MC		 13467out:
13468 return err;
13469}
13470
00c266b7
MC		 13471#define TG3_STD_LOOPBACK_FAILED 1
13472#define TG3_JMB_LOOPBACK_FAILED 2
bb158d69 13473#define TG3_TSO_LOOPBACK_FAILED 4
28a45957
MC		 13474#define TG3_LOOPBACK_FAILED \
13475 (TG3_STD_LOOPBACK_FAILED | \
13476 TG3_JMB_LOOPBACK_FAILED | \
13477 TG3_TSO_LOOPBACK_FAILED)
00c266b7 13478
941ec90f 13479static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
9f40dead 13480{
28a45957 13481 int err = -EIO;
2215e24c 13482 u32 eee_cap;
c441b456
MC		 13483 u32 jmb_pkt_sz = 9000;
13484
13485 if (tp->dma_limit)
13486 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
9f40dead 13487
ab789046
MC		 13488 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13489 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13490
28a45957 13491 if (!netif_running(tp->dev)) {
93df8b8f
NNS		 13492 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13493 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13494 if (do_extlpbk)
93df8b8f 13495 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
28a45957
MC		 13496 goto done;
13497 }
13498
953c96e0 13499 err = tg3_reset_hw(tp, true);
ab789046 13500 if (err) {
93df8b8f
NNS		 13501 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13502 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13503 if (do_extlpbk)
93df8b8f 13504 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
ab789046
MC		 13505 goto done;
13506 }
9f40dead 13507
63c3a66f 13508 if (tg3_flag(tp, ENABLE_RSS)) {
4a85f098
MC		 13509 int i;
13510
13511 /* Reroute all rx packets to the 1st queue */
13512 for (i = MAC_RSS_INDIR_TBL_0;
13513 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13514 tw32(i, 0x0);
13515 }
13516
6e01b20b
MC		 13517 /* HW errata - mac loopback fails in some cases on 5780.
13518 * Normal traffic and PHY loopback are not affected by
13519 * errata. Also, the MAC loopback test is deprecated for
13520 * all newer ASIC revisions.
13521 */
4153577a 13522 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
6e01b20b
MC		 13523 !tg3_flag(tp, CPMU_PRESENT)) {
13524 tg3_mac_loopback(tp, true);
9936bcf6 13525
28a45957 13526 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13527 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
6e01b20b
MC		 13528
13529 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13530 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13531 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
6e01b20b
MC		 13532
13533 tg3_mac_loopback(tp, false);
13534 }
4852a861 13535
f07e9af3 13536 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
63c3a66f 13537 !tg3_flag(tp, USE_PHYLIB)) {
5e5a7f37
MC		 13538 int i;
13539
941ec90f 13540 tg3_phy_lpbk_set(tp, 0, false);
5e5a7f37
MC		 13541
13542 /* Wait for link */
13543 for (i = 0; i < 100; i++) {
13544 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13545 break;
13546 mdelay(1);
13547 }
13548
28a45957 13549 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13550 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
63c3a66f 13551 if (tg3_flag(tp, TSO_CAPABLE) &&
28a45957 13552 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f 13553 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
63c3a66f 13554 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13555 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13556 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
9f40dead 13557
941ec90f
MC		 13558 if (do_extlpbk) {
13559 tg3_phy_lpbk_set(tp, 0, true);
13560
13561 /* All link indications report up, but the hardware
13562 * isn't really ready for about 20 msec. Double it
13563 * to be sure.
13564 */
13565 mdelay(40);
13566
13567 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f
NNS		 13568 data[TG3_EXT_LOOPB_TEST] |=
13569 TG3_STD_LOOPBACK_FAILED;
941ec90f
MC		 13570 if (tg3_flag(tp, TSO_CAPABLE) &&
13571 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f
NNS		 13572 data[TG3_EXT_LOOPB_TEST] |=
13573 TG3_TSO_LOOPBACK_FAILED;
941ec90f 13574 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13575 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f
NNS		 13576 data[TG3_EXT_LOOPB_TEST] |=
13577 TG3_JMB_LOOPBACK_FAILED;
941ec90f
MC		 13578 }
13579
5e5a7f37
MC		 13580 /* Re-enable gphy autopowerdown. */
13581 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13582 tg3_phy_toggle_apd(tp, true);
13583 }
6833c043 13584
93df8b8f
NNS		 13585 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13586 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
28a45957 13587
ab789046
MC		 13588done:
13589 tp->phy_flags |= eee_cap;
13590
9f40dead
MC		 13591 return err;
13592}
13593
4cafd3f5
MC		 13594static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13595 u64 *data)
13596{
566f86ad 13597 struct tg3 *tp = netdev_priv(dev);
941ec90f 13598 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
566f86ad 13599
2e460fc0
NS		 13600 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13601 if (tg3_power_up(tp)) {
13602 etest->flags |= ETH_TEST_FL_FAILED;
13603 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13604 return;
13605 }
13606 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
bed9829f 13607 }
bc1c7567 13608
566f86ad
MC		 13609 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13610
13611 if (tg3_test_nvram(tp) != 0) {
13612 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13613 data[TG3_NVRAM_TEST] = 1;
566f86ad 13614 }
941ec90f 13615 if (!doextlpbk && tg3_test_link(tp)) {
ca43007a 13616 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13617 data[TG3_LINK_TEST] = 1;
ca43007a 13618 }
a71116d1 13619 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 13620 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 13621
13622 if (netif_running(dev)) {
b02fd9e3 13623 tg3_phy_stop(tp);
a71116d1 13624 tg3_netif_stop(tp);
bbe832c0
MC		 13625 irq_sync = 1;
13626 }
a71116d1 13627
bbe832c0 13628 tg3_full_lock(tp, irq_sync);
a71116d1 13629 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 13630 err = tg3_nvram_lock(tp);
a71116d1 13631 tg3_halt_cpu(tp, RX_CPU_BASE);
63c3a66f 13632 if (!tg3_flag(tp, 5705_PLUS))
a71116d1 13633 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 13634 if (!err)
13635 tg3_nvram_unlock(tp);
a71116d1 13636
f07e9af3 13637 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
d9ab5ad1
MC		 13638 tg3_phy_reset(tp);
13639
a71116d1
MC		 13640 if (tg3_test_registers(tp) != 0) {
13641 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13642 data[TG3_REGISTER_TEST] = 1;
a71116d1 13643 }
28a45957 13644
7942e1db
MC		 13645 if (tg3_test_memory(tp) != 0) {
13646 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13647 data[TG3_MEMORY_TEST] = 1;
7942e1db 13648 }
28a45957 13649
941ec90f
MC		 13650 if (doextlpbk)
13651 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13652
93df8b8f 13653 if (tg3_test_loopback(tp, data, doextlpbk))
c76949a6 13654 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 13655
f47c11ee
DM		 13656 tg3_full_unlock(tp);
13657
d4bc3927
MC		 13658 if (tg3_test_interrupt(tp) != 0) {
13659 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13660 data[TG3_INTERRUPT_TEST] = 1;
d4bc3927 13661 }
f47c11ee
DM		 13662
13663 tg3_full_lock(tp, 0);
d4bc3927 13664
a71116d1
MC		 13665 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13666 if (netif_running(dev)) {
63c3a66f 13667 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 13668 err2 = tg3_restart_hw(tp, true);
b02fd9e3 13669 if (!err2)
b9ec6c1b 13670 tg3_netif_start(tp);
a71116d1 13671 }
f47c11ee
DM		 13672
13673 tg3_full_unlock(tp);
b02fd9e3
MC		 13674
13675 if (irq_sync && !err2)
13676 tg3_phy_start(tp);
a71116d1 13677 }
80096068 13678 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
5137a2ee 13679 tg3_power_down_prepare(tp);
bc1c7567 13680
4cafd3f5
MC		 13681}
13682
7260899b 13683static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
0a633ac2
MC		 13684{
13685 struct tg3 *tp = netdev_priv(dev);
13686 struct hwtstamp_config stmpconf;
13687
13688 if (!tg3_flag(tp, PTP_CAPABLE))
7260899b 13689 return -EOPNOTSUPP;
0a633ac2
MC		 13690
13691 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13692 return -EFAULT;
13693
13694 if (stmpconf.flags)
13695 return -EINVAL;
13696
58b187c6
BH		 13697 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13698 stmpconf.tx_type != HWTSTAMP_TX_OFF)
0a633ac2 13699 return -ERANGE;
0a633ac2
MC		 13700
13701 switch (stmpconf.rx_filter) {
13702 case HWTSTAMP_FILTER_NONE:
13703 tp->rxptpctl = 0;
13704 break;
13705 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13706 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13707 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13708 break;
13709 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13710 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13711 TG3_RX_PTP_CTL_SYNC_EVNT;
13712 break;
13713 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13714 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13715 TG3_RX_PTP_CTL_DELAY_REQ;
13716 break;
13717 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13718 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13719 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13720 break;
13721 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13722 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13723 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13724 break;
13725 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13726 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13727 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13728 break;
13729 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13730 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13731 TG3_RX_PTP_CTL_SYNC_EVNT;
13732 break;
13733 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13734 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13735 TG3_RX_PTP_CTL_SYNC_EVNT;
13736 break;
13737 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13738 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13739 TG3_RX_PTP_CTL_SYNC_EVNT;
13740 break;
13741 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13742 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13743 TG3_RX_PTP_CTL_DELAY_REQ;
13744 break;
13745 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13746 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13747 TG3_RX_PTP_CTL_DELAY_REQ;
13748 break;
13749 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13750 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13751 TG3_RX_PTP_CTL_DELAY_REQ;
13752 break;
13753 default:
13754 return -ERANGE;
13755 }
13756
13757 if (netif_running(dev) && tp->rxptpctl)
13758 tw32(TG3_RX_PTP_CTL,
13759 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13760
58b187c6
BH		 13761 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13762 tg3_flag_set(tp, TX_TSTAMP_EN);
13763 else
13764 tg3_flag_clear(tp, TX_TSTAMP_EN);
13765
0a633ac2
MC		 13766 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13767 -EFAULT : 0;
13768}
13769
7260899b
BH		 13770static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13771{
13772 struct tg3 *tp = netdev_priv(dev);
13773 struct hwtstamp_config stmpconf;
13774
13775 if (!tg3_flag(tp, PTP_CAPABLE))
13776 return -EOPNOTSUPP;
13777
13778 stmpconf.flags = 0;
13779 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13780 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13781
13782 switch (tp->rxptpctl) {
13783 case 0:
13784 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13785 break;
13786 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13787 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13788 break;
13789 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13790 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13791 break;
13792 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13793 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13794 break;
13795 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13796 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13797 break;
13798 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13799 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13800 break;
13801 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13802 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13803 break;
13804 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13805 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13806 break;
13807 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13808 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13809 break;
13810 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13811 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13812 break;
13813 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13814 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13815 break;
13816 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13817 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13818 break;
13819 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13820 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13821 break;
13822 default:
13823 WARN_ON_ONCE(1);
13824 return -ERANGE;
13825 }
13826
13827 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13828 -EFAULT : 0;
13829}
13830
1da177e4
LT		 13831static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13832{
13833 struct mii_ioctl_data *data = if_mii(ifr);
13834 struct tg3 *tp = netdev_priv(dev);
13835 int err;
13836
63c3a66f 13837 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 13838 struct phy_device *phydev;
f07e9af3 13839 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 13840 return -EAGAIN;
ead2402c 13841 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
28b04113 13842 return phy_mii_ioctl(phydev, ifr, cmd);
b02fd9e3
MC		 13843 }
13844
33f401ae 13845 switch (cmd) {
1da177e4 13846 case SIOCGMIIPHY:
882e9793 13847 data->phy_id = tp->phy_addr;
1da177e4
LT		 13848
13849 /* fallthru */
13850 case SIOCGMIIREG: {
13851 u32 mii_regval;
13852
f07e9af3 13853 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13854 break; /* We have no PHY */
13855
34eea5ac 13856 if (!netif_running(dev))
bc1c7567
MC		 13857 return -EAGAIN;
13858
f47c11ee 13859 spin_lock_bh(&tp->lock);
5c358045
HM		 13860 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13861 data->reg_num & 0x1f, &mii_regval);
f47c11ee 13862 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13863
13864 data->val_out = mii_regval;
13865
13866 return err;
13867 }
13868
13869 case SIOCSMIIREG:
f07e9af3 13870 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13871 break; /* We have no PHY */
13872
34eea5ac 13873 if (!netif_running(dev))
bc1c7567
MC		 13874 return -EAGAIN;
13875
f47c11ee 13876 spin_lock_bh(&tp->lock);
5c358045
HM		 13877 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13878 data->reg_num & 0x1f, data->val_in);
f47c11ee 13879 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13880
13881 return err;
13882
0a633ac2 13883 case SIOCSHWTSTAMP:
7260899b
BH		 13884 return tg3_hwtstamp_set(dev, ifr);
13885
13886 case SIOCGHWTSTAMP:
13887 return tg3_hwtstamp_get(dev, ifr);
0a633ac2 13888
1da177e4
LT		 13889 default:
13890 /* do nothing */
13891 break;
13892 }
13893 return -EOPNOTSUPP;
13894}
13895
15f9850d
DM		 13896static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13897{
13898 struct tg3 *tp = netdev_priv(dev);
13899
13900 memcpy(ec, &tp->coal, sizeof(*ec));
13901 return 0;
13902}
13903
d244c892
MC		 13904static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13905{
13906 struct tg3 *tp = netdev_priv(dev);
13907 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13908 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13909
63c3a66f 13910 if (!tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 13911 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13912 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13913 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13914 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13915 }
13916
13917 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13918 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13919 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13920 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13921 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13922 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13923 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13924 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13925 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13926 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13927 return -EINVAL;
13928
13929 /* No rx interrupts will be generated if both are zero */
13930 if ((ec->rx_coalesce_usecs == 0) &&
13931 (ec->rx_max_coalesced_frames == 0))
13932 return -EINVAL;
13933
13934 /* No tx interrupts will be generated if both are zero */
13935 if ((ec->tx_coalesce_usecs == 0) &&
13936 (ec->tx_max_coalesced_frames == 0))
13937 return -EINVAL;
13938
13939 /* Only copy relevant parameters, ignore all others. */
13940 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
13941 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
13942 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
13943 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
13944 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
13945 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
13946 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
13947 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
13948 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
13949
13950 if (netif_running(dev)) {
13951 tg3_full_lock(tp, 0);
13952 __tg3_set_coalesce(tp, &tp->coal);
13953 tg3_full_unlock(tp);
13954 }
13955 return 0;
13956}
13957
1cbf9eb8
NS		 13958static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
13959{
13960 struct tg3 *tp = netdev_priv(dev);
13961
13962 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13963 netdev_warn(tp->dev, "Board does not support EEE!\n");
13964 return -EOPNOTSUPP;
13965 }
13966
13967 if (edata->advertised != tp->eee.advertised) {
13968 netdev_warn(tp->dev,
13969 "Direct manipulation of EEE advertisement is not supported\n");
13970 return -EINVAL;
13971 }
13972
13973 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
13974 netdev_warn(tp->dev,
13975 "Maximal Tx Lpi timer supported is %#x(u)\n",
13976 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
13977 return -EINVAL;
13978 }
13979
13980 tp->eee = *edata;
13981
13982 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
13983 tg3_warn_mgmt_link_flap(tp);
13984
13985 if (netif_running(tp->dev)) {
13986 tg3_full_lock(tp, 0);
13987 tg3_setup_eee(tp);
13988 tg3_phy_reset(tp);
13989 tg3_full_unlock(tp);
13990 }
13991
13992 return 0;
13993}
13994
13995static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
13996{
13997 struct tg3 *tp = netdev_priv(dev);
13998
13999 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14000 netdev_warn(tp->dev,
14001 "Board does not support EEE!\n");
14002 return -EOPNOTSUPP;
14003 }
14004
14005 *edata = tp->eee;
14006 return 0;
14007}
14008
7282d491 14009static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 14010 .get_settings = tg3_get_settings,
14011 .set_settings = tg3_set_settings,
14012 .get_drvinfo = tg3_get_drvinfo,
14013 .get_regs_len = tg3_get_regs_len,
14014 .get_regs = tg3_get_regs,
14015 .get_wol = tg3_get_wol,
14016 .set_wol = tg3_set_wol,
14017 .get_msglevel = tg3_get_msglevel,
14018 .set_msglevel = tg3_set_msglevel,
14019 .nway_reset = tg3_nway_reset,
14020 .get_link = ethtool_op_get_link,
14021 .get_eeprom_len = tg3_get_eeprom_len,
14022 .get_eeprom = tg3_get_eeprom,
14023 .set_eeprom = tg3_set_eeprom,
14024 .get_ringparam = tg3_get_ringparam,
14025 .set_ringparam = tg3_set_ringparam,
14026 .get_pauseparam = tg3_get_pauseparam,
14027 .set_pauseparam = tg3_set_pauseparam,
4cafd3f5 14028 .self_test = tg3_self_test,
1da177e4 14029 .get_strings = tg3_get_strings,
81b8709c 14030 .set_phys_id = tg3_set_phys_id,
1da177e4 14031 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 14032 .get_coalesce = tg3_get_coalesce,
d244c892 14033 .set_coalesce = tg3_set_coalesce,
b9f2c044 14034 .get_sset_count = tg3_get_sset_count,
90415477
MC		 14035 .get_rxnfc = tg3_get_rxnfc,
14036 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
14037 .get_rxfh_indir = tg3_get_rxfh_indir,
14038 .set_rxfh_indir = tg3_set_rxfh_indir,
0968169c
MC		 14039 .get_channels = tg3_get_channels,
14040 .set_channels = tg3_set_channels,
7d41e49a 14041 .get_ts_info = tg3_get_ts_info,
1cbf9eb8
NS		 14042 .get_eee = tg3_get_eee,
14043 .set_eee = tg3_set_eee,
1da177e4
LT		 14044};
14045
b4017c53
DM		 14046static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
14047 struct rtnl_link_stats64 *stats)
14048{
14049 struct tg3 *tp = netdev_priv(dev);
14050
0f566b20
MC		 14051 spin_lock_bh(&tp->lock);
14052 if (!tp->hw_stats) {
14053 spin_unlock_bh(&tp->lock);
b4017c53 14054 return &tp->net_stats_prev;
0f566b20 14055 }
b4017c53 14056
b4017c53
DM		 14057 tg3_get_nstats(tp, stats);
14058 spin_unlock_bh(&tp->lock);
14059
14060 return stats;
14061}
14062
ccd5ba9d
MC		 14063static void tg3_set_rx_mode(struct net_device *dev)
14064{
14065 struct tg3 *tp = netdev_priv(dev);
14066
14067 if (!netif_running(dev))
14068 return;
14069
14070 tg3_full_lock(tp, 0);
14071 __tg3_set_rx_mode(dev);
14072 tg3_full_unlock(tp);
14073}
14074
faf1627a
MC		 14075static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14076 int new_mtu)
14077{
14078 dev->mtu = new_mtu;
14079
14080 if (new_mtu > ETH_DATA_LEN) {
14081 if (tg3_flag(tp, 5780_CLASS)) {
14082 netdev_update_features(dev);
14083 tg3_flag_clear(tp, TSO_CAPABLE);
14084 } else {
14085 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14086 }
14087 } else {
14088 if (tg3_flag(tp, 5780_CLASS)) {
14089 tg3_flag_set(tp, TSO_CAPABLE);
14090 netdev_update_features(dev);
14091 }
14092 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14093 }
14094}
14095
14096static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14097{
14098 struct tg3 *tp = netdev_priv(dev);
953c96e0
JP		 14099 int err;
14100 bool reset_phy = false;
faf1627a
MC		 14101
14102 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
14103 return -EINVAL;
14104
14105 if (!netif_running(dev)) {
14106 /* We'll just catch it later when the
14107 * device is up'd.
14108 */
14109 tg3_set_mtu(dev, tp, new_mtu);
14110 return 0;
14111 }
14112
14113 tg3_phy_stop(tp);
14114
14115 tg3_netif_stop(tp);
14116
14117 tg3_full_lock(tp, 1);
14118
14119 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14120
14121 tg3_set_mtu(dev, tp, new_mtu);
14122
2fae5e36
MC		 14123 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14124 * breaks all requests to 256 bytes.
14125 */
4153577a 14126 if (tg3_asic_rev(tp) == ASIC_REV_57766)
953c96e0 14127 reset_phy = true;
2fae5e36
MC		 14128
14129 err = tg3_restart_hw(tp, reset_phy);
faf1627a
MC		 14130
14131 if (!err)
14132 tg3_netif_start(tp);
14133
14134 tg3_full_unlock(tp);
14135
14136 if (!err)
14137 tg3_phy_start(tp);
14138
14139 return err;
14140}
14141
14142static const struct net_device_ops tg3_netdev_ops = {
14143 .ndo_open = tg3_open,
14144 .ndo_stop = tg3_close,
14145 .ndo_start_xmit = tg3_start_xmit,
14146 .ndo_get_stats64 = tg3_get_stats64,
14147 .ndo_validate_addr = eth_validate_addr,
14148 .ndo_set_rx_mode = tg3_set_rx_mode,
14149 .ndo_set_mac_address = tg3_set_mac_addr,
14150 .ndo_do_ioctl = tg3_ioctl,
14151 .ndo_tx_timeout = tg3_tx_timeout,
14152 .ndo_change_mtu = tg3_change_mtu,
14153 .ndo_fix_features = tg3_fix_features,
14154 .ndo_set_features = tg3_set_features,
14155#ifdef CONFIG_NET_POLL_CONTROLLER
14156 .ndo_poll_controller = tg3_poll_controller,
14157#endif
14158};
14159
229b1ad1 14160static void tg3_get_eeprom_size(struct tg3 *tp)
1da177e4 14161{
1b27777a 14162 u32 cursize, val, magic;
1da177e4
LT		 14163
14164 tp->nvram_size = EEPROM_CHIP_SIZE;
14165
e4f34110 14166 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 14167 return;
14168
b16250e3
MC		 14169 if ((magic != TG3_EEPROM_MAGIC) &&
14170 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14171 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 14172 return;
14173
14174 /*
14175 * Size the chip by reading offsets at increasing powers of two.
14176 * When we encounter our validation signature, we know the addressing
14177 * has wrapped around, and thus have our chip size.
14178 */
1b27777a 14179 cursize = 0x10;
1da177e4
LT		 14180
14181 while (cursize < tp->nvram_size) {
e4f34110 14182 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 14183 return;
14184
1820180b 14185 if (val == magic)
1da177e4
LT		 14186 break;
14187
14188 cursize <<= 1;
14189 }
14190
14191 tp->nvram_size = cursize;
14192}
6aa20a22 14193
229b1ad1 14194static void tg3_get_nvram_size(struct tg3 *tp)
1da177e4
LT		 14195{
14196 u32 val;
14197
63c3a66f 14198 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 14199 return;
14200
14201 /* Selfboot format */
1820180b 14202 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 14203 tg3_get_eeprom_size(tp);
14204 return;
14205 }
14206
6d348f2c 14207 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 14208 if (val != 0) {
6d348f2c
MC		 14209 /* This is confusing. We want to operate on the
14210 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14211 * call will read from NVRAM and byteswap the data
14212 * according to the byteswapping settings for all
14213 * other register accesses. This ensures the data we
14214 * want will always reside in the lower 16-bits.
14215 * However, the data in NVRAM is in LE format, which
14216 * means the data from the NVRAM read will always be
14217 * opposite the endianness of the CPU. The 16-bit
14218 * byteswap then brings the data to CPU endianness.
14219 */
14220 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 14221 return;
14222 }
14223 }
fd1122a2 14224 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 14225}
14226
229b1ad1 14227static void tg3_get_nvram_info(struct tg3 *tp)
1da177e4
LT		 14228{
14229 u32 nvcfg1;
14230
14231 nvcfg1 = tr32(NVRAM_CFG1);
14232 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
63c3a66f 14233 tg3_flag_set(tp, FLASH);
8590a603 14234 } else {
1da177e4
LT		 14235 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14236 tw32(NVRAM_CFG1, nvcfg1);
14237 }
14238
4153577a 14239 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
63c3a66f 14240 tg3_flag(tp, 5780_CLASS)) {
1da177e4 14241 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 14242 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14243 tp->nvram_jedecnum = JEDEC_ATMEL;
14244 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14245 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14246 break;
14247 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14248 tp->nvram_jedecnum = JEDEC_ATMEL;
14249 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14250 break;
14251 case FLASH_VENDOR_ATMEL_EEPROM:
14252 tp->nvram_jedecnum = JEDEC_ATMEL;
14253 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
63c3a66f 14254 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14255 break;
14256 case FLASH_VENDOR_ST:
14257 tp->nvram_jedecnum = JEDEC_ST;
14258 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
63c3a66f 14259 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14260 break;
14261 case FLASH_VENDOR_SAIFUN:
14262 tp->nvram_jedecnum = JEDEC_SAIFUN;
14263 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14264 break;
14265 case FLASH_VENDOR_SST_SMALL:
14266 case FLASH_VENDOR_SST_LARGE:
14267 tp->nvram_jedecnum = JEDEC_SST;
14268 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14269 break;
1da177e4 14270 }
8590a603 14271 } else {
1da177e4
LT		 14272 tp->nvram_jedecnum = JEDEC_ATMEL;
14273 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14274 tg3_flag_set(tp, NVRAM_BUFFERED);
1da177e4
LT		 14275 }
14276}
14277
229b1ad1 14278static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
a1b950d5
MC		 14279{
14280 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14281 case FLASH_5752PAGE_SIZE_256:
14282 tp->nvram_pagesize = 256;
14283 break;
14284 case FLASH_5752PAGE_SIZE_512:
14285 tp->nvram_pagesize = 512;
14286 break;
14287 case FLASH_5752PAGE_SIZE_1K:
14288 tp->nvram_pagesize = 1024;
14289 break;
14290 case FLASH_5752PAGE_SIZE_2K:
14291 tp->nvram_pagesize = 2048;
14292 break;
14293 case FLASH_5752PAGE_SIZE_4K:
14294 tp->nvram_pagesize = 4096;
14295 break;
14296 case FLASH_5752PAGE_SIZE_264:
14297 tp->nvram_pagesize = 264;
14298 break;
14299 case FLASH_5752PAGE_SIZE_528:
14300 tp->nvram_pagesize = 528;
14301 break;
14302 }
14303}
14304
229b1ad1 14305static void tg3_get_5752_nvram_info(struct tg3 *tp)
361b4ac2
MC		 14306{
14307 u32 nvcfg1;
14308
14309 nvcfg1 = tr32(NVRAM_CFG1);
14310
e6af301b
MC		 14311 /* NVRAM protection for TPM */
14312 if (nvcfg1 & (1 << 27))
63c3a66f 14313 tg3_flag_set(tp, PROTECTED_NVRAM);
e6af301b 14314
361b4ac2 14315 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14316 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14317 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14318 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14319 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14320 break;
14321 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14322 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14323 tg3_flag_set(tp, NVRAM_BUFFERED);
14324 tg3_flag_set(tp, FLASH);
8590a603
MC		 14325 break;
14326 case FLASH_5752VENDOR_ST_M45PE10:
14327 case FLASH_5752VENDOR_ST_M45PE20:
14328 case FLASH_5752VENDOR_ST_M45PE40:
14329 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14330 tg3_flag_set(tp, NVRAM_BUFFERED);
14331 tg3_flag_set(tp, FLASH);
8590a603 14332 break;
361b4ac2
MC		 14333 }
14334
63c3a66f 14335 if (tg3_flag(tp, FLASH)) {
a1b950d5 14336 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 14337 } else {
361b4ac2
MC		 14338 /* For eeprom, set pagesize to maximum eeprom size */
14339 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14340
14341 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14342 tw32(NVRAM_CFG1, nvcfg1);
14343 }
14344}
14345
229b1ad1 14346static void tg3_get_5755_nvram_info(struct tg3 *tp)
d3c7b886 14347{
989a9d23 14348 u32 nvcfg1, protect = 0;
d3c7b886
MC		 14349
14350 nvcfg1 = tr32(NVRAM_CFG1);
14351
14352 /* NVRAM protection for TPM */
989a9d23 14353 if (nvcfg1 & (1 << 27)) {
63c3a66f 14354 tg3_flag_set(tp, PROTECTED_NVRAM);
989a9d23
MC		 14355 protect = 1;
14356 }
d3c7b886 14357
989a9d23
MC		 14358 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14359 switch (nvcfg1) {
8590a603
MC		 14360 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14361 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14362 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14363 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14364 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14365 tg3_flag_set(tp, NVRAM_BUFFERED);
14366 tg3_flag_set(tp, FLASH);
8590a603
MC		 14367 tp->nvram_pagesize = 264;
14368 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14369 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14370 tp->nvram_size = (protect ? 0x3e200 :
14371 TG3_NVRAM_SIZE_512KB);
14372 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14373 tp->nvram_size = (protect ? 0x1f200 :
14374 TG3_NVRAM_SIZE_256KB);
14375 else
14376 tp->nvram_size = (protect ? 0x1f200 :
14377 TG3_NVRAM_SIZE_128KB);
14378 break;
14379 case FLASH_5752VENDOR_ST_M45PE10:
14380 case FLASH_5752VENDOR_ST_M45PE20:
14381 case FLASH_5752VENDOR_ST_M45PE40:
14382 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14383 tg3_flag_set(tp, NVRAM_BUFFERED);
14384 tg3_flag_set(tp, FLASH);
8590a603
MC		 14385 tp->nvram_pagesize = 256;
14386 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14387 tp->nvram_size = (protect ?
14388 TG3_NVRAM_SIZE_64KB :
14389 TG3_NVRAM_SIZE_128KB);
14390 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14391 tp->nvram_size = (protect ?
14392 TG3_NVRAM_SIZE_64KB :
14393 TG3_NVRAM_SIZE_256KB);
14394 else
14395 tp->nvram_size = (protect ?
14396 TG3_NVRAM_SIZE_128KB :
14397 TG3_NVRAM_SIZE_512KB);
14398 break;
d3c7b886
MC		 14399 }
14400}
14401
229b1ad1 14402static void tg3_get_5787_nvram_info(struct tg3 *tp)
1b27777a
MC		 14403{
14404 u32 nvcfg1;
14405
14406 nvcfg1 = tr32(NVRAM_CFG1);
14407
14408 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14409 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14410 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14411 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14412 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14413 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14414 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603 14415 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 14416
8590a603
MC		 14417 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14418 tw32(NVRAM_CFG1, nvcfg1);
14419 break;
14420 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14421 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14422 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14423 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14424 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14425 tg3_flag_set(tp, NVRAM_BUFFERED);
14426 tg3_flag_set(tp, FLASH);
8590a603
MC		 14427 tp->nvram_pagesize = 264;
14428 break;
14429 case FLASH_5752VENDOR_ST_M45PE10:
14430 case FLASH_5752VENDOR_ST_M45PE20:
14431 case FLASH_5752VENDOR_ST_M45PE40:
14432 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14433 tg3_flag_set(tp, NVRAM_BUFFERED);
14434 tg3_flag_set(tp, FLASH);
8590a603
MC		 14435 tp->nvram_pagesize = 256;
14436 break;
1b27777a
MC		 14437 }
14438}
14439
229b1ad1 14440static void tg3_get_5761_nvram_info(struct tg3 *tp)
6b91fa02
MC		 14441{
14442 u32 nvcfg1, protect = 0;
14443
14444 nvcfg1 = tr32(NVRAM_CFG1);
14445
14446 /* NVRAM protection for TPM */
14447 if (nvcfg1 & (1 << 27)) {
63c3a66f 14448 tg3_flag_set(tp, PROTECTED_NVRAM);
6b91fa02
MC		 14449 protect = 1;
14450 }
14451
14452 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14453 switch (nvcfg1) {
8590a603
MC		 14454 case FLASH_5761VENDOR_ATMEL_ADB021D:
14455 case FLASH_5761VENDOR_ATMEL_ADB041D:
14456 case FLASH_5761VENDOR_ATMEL_ADB081D:
14457 case FLASH_5761VENDOR_ATMEL_ADB161D:
14458 case FLASH_5761VENDOR_ATMEL_MDB021D:
14459 case FLASH_5761VENDOR_ATMEL_MDB041D:
14460 case FLASH_5761VENDOR_ATMEL_MDB081D:
14461 case FLASH_5761VENDOR_ATMEL_MDB161D:
14462 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14463 tg3_flag_set(tp, NVRAM_BUFFERED);
14464 tg3_flag_set(tp, FLASH);
14465 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
8590a603
MC		 14466 tp->nvram_pagesize = 256;
14467 break;
14468 case FLASH_5761VENDOR_ST_A_M45PE20:
14469 case FLASH_5761VENDOR_ST_A_M45PE40:
14470 case FLASH_5761VENDOR_ST_A_M45PE80:
14471 case FLASH_5761VENDOR_ST_A_M45PE16:
14472 case FLASH_5761VENDOR_ST_M_M45PE20:
14473 case FLASH_5761VENDOR_ST_M_M45PE40:
14474 case FLASH_5761VENDOR_ST_M_M45PE80:
14475 case FLASH_5761VENDOR_ST_M_M45PE16:
14476 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14477 tg3_flag_set(tp, NVRAM_BUFFERED);
14478 tg3_flag_set(tp, FLASH);
8590a603
MC		 14479 tp->nvram_pagesize = 256;
14480 break;
6b91fa02
MC		 14481 }
14482
14483 if (protect) {
14484 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14485 } else {
14486 switch (nvcfg1) {
8590a603
MC		 14487 case FLASH_5761VENDOR_ATMEL_ADB161D:
14488 case FLASH_5761VENDOR_ATMEL_MDB161D:
14489 case FLASH_5761VENDOR_ST_A_M45PE16:
14490 case FLASH_5761VENDOR_ST_M_M45PE16:
14491 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14492 break;
14493 case FLASH_5761VENDOR_ATMEL_ADB081D:
14494 case FLASH_5761VENDOR_ATMEL_MDB081D:
14495 case FLASH_5761VENDOR_ST_A_M45PE80:
14496 case FLASH_5761VENDOR_ST_M_M45PE80:
14497 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14498 break;
14499 case FLASH_5761VENDOR_ATMEL_ADB041D:
14500 case FLASH_5761VENDOR_ATMEL_MDB041D:
14501 case FLASH_5761VENDOR_ST_A_M45PE40:
14502 case FLASH_5761VENDOR_ST_M_M45PE40:
14503 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14504 break;
14505 case FLASH_5761VENDOR_ATMEL_ADB021D:
14506 case FLASH_5761VENDOR_ATMEL_MDB021D:
14507 case FLASH_5761VENDOR_ST_A_M45PE20:
14508 case FLASH_5761VENDOR_ST_M_M45PE20:
14509 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14510 break;
6b91fa02
MC		 14511 }
14512 }
14513}
14514
229b1ad1 14515static void tg3_get_5906_nvram_info(struct tg3 *tp)
b5d3772c
MC		 14516{
14517 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14518 tg3_flag_set(tp, NVRAM_BUFFERED);
b5d3772c
MC		 14519 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14520}
14521
229b1ad1 14522static void tg3_get_57780_nvram_info(struct tg3 *tp)
321d32a0
MC		 14523{
14524 u32 nvcfg1;
14525
14526 nvcfg1 = tr32(NVRAM_CFG1);
14527
14528 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14529 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14530 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14531 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14532 tg3_flag_set(tp, NVRAM_BUFFERED);
321d32a0
MC		 14533 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14534
14535 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14536 tw32(NVRAM_CFG1, nvcfg1);
14537 return;
14538 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14539 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14540 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14541 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14542 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14543 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14544 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14545 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14546 tg3_flag_set(tp, NVRAM_BUFFERED);
14547 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14548
14549 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14550 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14551 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14552 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14553 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14554 break;
14555 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14556 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14557 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14558 break;
14559 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14560 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14561 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14562 break;
14563 }
14564 break;
14565 case FLASH_5752VENDOR_ST_M45PE10:
14566 case FLASH_5752VENDOR_ST_M45PE20:
14567 case FLASH_5752VENDOR_ST_M45PE40:
14568 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14569 tg3_flag_set(tp, NVRAM_BUFFERED);
14570 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14571
14572 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14573 case FLASH_5752VENDOR_ST_M45PE10:
14574 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14575 break;
14576 case FLASH_5752VENDOR_ST_M45PE20:
14577 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14578 break;
14579 case FLASH_5752VENDOR_ST_M45PE40:
14580 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14581 break;
14582 }
14583 break;
14584 default:
63c3a66f 14585 tg3_flag_set(tp, NO_NVRAM);
321d32a0
MC		 14586 return;
14587 }
14588
a1b950d5
MC		 14589 tg3_nvram_get_pagesize(tp, nvcfg1);
14590 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14591 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
a1b950d5
MC		 14592}
14593
14594
229b1ad1 14595static void tg3_get_5717_nvram_info(struct tg3 *tp)
a1b950d5
MC		 14596{
14597 u32 nvcfg1;
14598
14599 nvcfg1 = tr32(NVRAM_CFG1);
14600
14601 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14602 case FLASH_5717VENDOR_ATMEL_EEPROM:
14603 case FLASH_5717VENDOR_MICRO_EEPROM:
14604 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14605 tg3_flag_set(tp, NVRAM_BUFFERED);
a1b950d5
MC		 14606 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14607
14608 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14609 tw32(NVRAM_CFG1, nvcfg1);
14610 return;
14611 case FLASH_5717VENDOR_ATMEL_MDB011D:
14612 case FLASH_5717VENDOR_ATMEL_ADB011B:
14613 case FLASH_5717VENDOR_ATMEL_ADB011D:
14614 case FLASH_5717VENDOR_ATMEL_MDB021D:
14615 case FLASH_5717VENDOR_ATMEL_ADB021B:
14616 case FLASH_5717VENDOR_ATMEL_ADB021D:
14617 case FLASH_5717VENDOR_ATMEL_45USPT:
14618 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14619 tg3_flag_set(tp, NVRAM_BUFFERED);
14620 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14621
14622 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14623 case FLASH_5717VENDOR_ATMEL_MDB021D:
66ee33bf
MC		 14624 /* Detect size with tg3_nvram_get_size() */
14625 break;
a1b950d5
MC		 14626 case FLASH_5717VENDOR_ATMEL_ADB021B:
14627 case FLASH_5717VENDOR_ATMEL_ADB021D:
14628 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14629 break;
14630 default:
14631 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14632 break;
14633 }
321d32a0 14634 break;
a1b950d5
MC		 14635 case FLASH_5717VENDOR_ST_M_M25PE10:
14636 case FLASH_5717VENDOR_ST_A_M25PE10:
14637 case FLASH_5717VENDOR_ST_M_M45PE10:
14638 case FLASH_5717VENDOR_ST_A_M45PE10:
14639 case FLASH_5717VENDOR_ST_M_M25PE20:
14640 case FLASH_5717VENDOR_ST_A_M25PE20:
14641 case FLASH_5717VENDOR_ST_M_M45PE20:
14642 case FLASH_5717VENDOR_ST_A_M45PE20:
14643 case FLASH_5717VENDOR_ST_25USPT:
14644 case FLASH_5717VENDOR_ST_45USPT:
14645 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14646 tg3_flag_set(tp, NVRAM_BUFFERED);
14647 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14648
14649 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14650 case FLASH_5717VENDOR_ST_M_M25PE20:
a1b950d5 14651 case FLASH_5717VENDOR_ST_M_M45PE20:
66ee33bf
MC		 14652 /* Detect size with tg3_nvram_get_size() */
14653 break;
14654 case FLASH_5717VENDOR_ST_A_M25PE20:
a1b950d5
MC		 14655 case FLASH_5717VENDOR_ST_A_M45PE20:
14656 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14657 break;
14658 default:
14659 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14660 break;
14661 }
321d32a0 14662 break;
a1b950d5 14663 default:
63c3a66f 14664 tg3_flag_set(tp, NO_NVRAM);
a1b950d5 14665 return;
321d32a0 14666 }
a1b950d5
MC		 14667
14668 tg3_nvram_get_pagesize(tp, nvcfg1);
14669 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14670 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
321d32a0
MC		 14671}
14672
229b1ad1 14673static void tg3_get_5720_nvram_info(struct tg3 *tp)
9b91b5f1
MC		 14674{
14675 u32 nvcfg1, nvmpinstrp;
14676
14677 nvcfg1 = tr32(NVRAM_CFG1);
14678 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14679
4153577a 14680 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14681 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14682 tg3_flag_set(tp, NO_NVRAM);
14683 return;
14684 }
14685
14686 switch (nvmpinstrp) {
14687 case FLASH_5762_EEPROM_HD:
14688 nvmpinstrp = FLASH_5720_EEPROM_HD;
17e1a42f 14689 break;
c86a8560
MC		 14690 case FLASH_5762_EEPROM_LD:
14691 nvmpinstrp = FLASH_5720_EEPROM_LD;
17e1a42f 14692 break;
f6334bb8
MC		 14693 case FLASH_5720VENDOR_M_ST_M45PE20:
14694 /* This pinstrap supports multiple sizes, so force it
14695 * to read the actual size from location 0xf0.
14696 */
14697 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14698 break;
c86a8560
MC		 14699 }
14700 }
14701
9b91b5f1
MC		 14702 switch (nvmpinstrp) {
14703 case FLASH_5720_EEPROM_HD:
14704 case FLASH_5720_EEPROM_LD:
14705 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14706 tg3_flag_set(tp, NVRAM_BUFFERED);
9b91b5f1
MC		 14707
14708 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14709 tw32(NVRAM_CFG1, nvcfg1);
14710 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14711 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14712 else
14713 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14714 return;
14715 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14716 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14717 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14718 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14719 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14720 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14721 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14722 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14723 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14724 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14725 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14726 case FLASH_5720VENDOR_ATMEL_45USPT:
14727 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14728 tg3_flag_set(tp, NVRAM_BUFFERED);
14729 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14730
14731 switch (nvmpinstrp) {
14732 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14733 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14734 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14735 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14736 break;
14737 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14738 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14739 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14740 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14741 break;
14742 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14743 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14744 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14745 break;
14746 default:
4153577a 14747 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14748 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14749 break;
14750 }
14751 break;
14752 case FLASH_5720VENDOR_M_ST_M25PE10:
14753 case FLASH_5720VENDOR_M_ST_M45PE10:
14754 case FLASH_5720VENDOR_A_ST_M25PE10:
14755 case FLASH_5720VENDOR_A_ST_M45PE10:
14756 case FLASH_5720VENDOR_M_ST_M25PE20:
14757 case FLASH_5720VENDOR_M_ST_M45PE20:
14758 case FLASH_5720VENDOR_A_ST_M25PE20:
14759 case FLASH_5720VENDOR_A_ST_M45PE20:
14760 case FLASH_5720VENDOR_M_ST_M25PE40:
14761 case FLASH_5720VENDOR_M_ST_M45PE40:
14762 case FLASH_5720VENDOR_A_ST_M25PE40:
14763 case FLASH_5720VENDOR_A_ST_M45PE40:
14764 case FLASH_5720VENDOR_M_ST_M25PE80:
14765 case FLASH_5720VENDOR_M_ST_M45PE80:
14766 case FLASH_5720VENDOR_A_ST_M25PE80:
14767 case FLASH_5720VENDOR_A_ST_M45PE80:
14768 case FLASH_5720VENDOR_ST_25USPT:
14769 case FLASH_5720VENDOR_ST_45USPT:
14770 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14771 tg3_flag_set(tp, NVRAM_BUFFERED);
14772 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14773
14774 switch (nvmpinstrp) {
14775 case FLASH_5720VENDOR_M_ST_M25PE20:
14776 case FLASH_5720VENDOR_M_ST_M45PE20:
14777 case FLASH_5720VENDOR_A_ST_M25PE20:
14778 case FLASH_5720VENDOR_A_ST_M45PE20:
14779 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14780 break;
14781 case FLASH_5720VENDOR_M_ST_M25PE40:
14782 case FLASH_5720VENDOR_M_ST_M45PE40:
14783 case FLASH_5720VENDOR_A_ST_M25PE40:
14784 case FLASH_5720VENDOR_A_ST_M45PE40:
14785 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14786 break;
14787 case FLASH_5720VENDOR_M_ST_M25PE80:
14788 case FLASH_5720VENDOR_M_ST_M45PE80:
14789 case FLASH_5720VENDOR_A_ST_M25PE80:
14790 case FLASH_5720VENDOR_A_ST_M45PE80:
14791 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14792 break;
14793 default:
4153577a 14794 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14795 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14796 break;
14797 }
14798 break;
14799 default:
63c3a66f 14800 tg3_flag_set(tp, NO_NVRAM);
9b91b5f1
MC		 14801 return;
14802 }
14803
14804 tg3_nvram_get_pagesize(tp, nvcfg1);
14805 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14806 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
c86a8560 14807
4153577a 14808 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14809 u32 val;
14810
14811 if (tg3_nvram_read(tp, 0, &val))
14812 return;
14813
14814 if (val != TG3_EEPROM_MAGIC &&
14815 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14816 tg3_flag_set(tp, NO_NVRAM);
14817 }
9b91b5f1
MC		 14818}
14819
1da177e4 14820/* Chips other than 5700/5701 use the NVRAM for fetching info. */
229b1ad1 14821static void tg3_nvram_init(struct tg3 *tp)
1da177e4 14822{
7e6c63f0
HM		 14823 if (tg3_flag(tp, IS_SSB_CORE)) {
14824 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14825 tg3_flag_clear(tp, NVRAM);
14826 tg3_flag_clear(tp, NVRAM_BUFFERED);
14827 tg3_flag_set(tp, NO_NVRAM);
14828 return;
14829 }
14830
1da177e4
LT		 14831 tw32_f(GRC_EEPROM_ADDR,
14832 (EEPROM_ADDR_FSM_RESET |
14833 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14834 EEPROM_ADDR_CLKPERD_SHIFT)));
14835
9d57f01c 14836 msleep(1);
1da177e4
LT		 14837
14838 /* Enable seeprom accesses. */
14839 tw32_f(GRC_LOCAL_CTRL,
14840 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14841 udelay(100);
14842
4153577a
JP		 14843 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14844 tg3_asic_rev(tp) != ASIC_REV_5701) {
63c3a66f 14845 tg3_flag_set(tp, NVRAM);
1da177e4 14846
ec41c7df 14847 if (tg3_nvram_lock(tp)) {
5129c3a3
MC		 14848 netdev_warn(tp->dev,
14849 "Cannot get nvram lock, %s failed\n",
05dbe005 14850 __func__);
ec41c7df
MC		 14851 return;
14852 }
e6af301b 14853 tg3_enable_nvram_access(tp);
1da177e4 14854
989a9d23
MC		 14855 tp->nvram_size = 0;
14856
4153577a 14857 if (tg3_asic_rev(tp) == ASIC_REV_5752)
361b4ac2 14858 tg3_get_5752_nvram_info(tp);
4153577a 14859 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
d3c7b886 14860 tg3_get_5755_nvram_info(tp);
4153577a
JP		 14861 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14862 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14863 tg3_asic_rev(tp) == ASIC_REV_5785)
1b27777a 14864 tg3_get_5787_nvram_info(tp);
4153577a 14865 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
6b91fa02 14866 tg3_get_5761_nvram_info(tp);
4153577a 14867 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 14868 tg3_get_5906_nvram_info(tp);
4153577a 14869 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 14870 tg3_flag(tp, 57765_CLASS))
321d32a0 14871 tg3_get_57780_nvram_info(tp);
4153577a
JP		 14872 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14873 tg3_asic_rev(tp) == ASIC_REV_5719)
a1b950d5 14874 tg3_get_5717_nvram_info(tp);
4153577a
JP		 14875 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14876 tg3_asic_rev(tp) == ASIC_REV_5762)
9b91b5f1 14877 tg3_get_5720_nvram_info(tp);
361b4ac2
MC		 14878 else
14879 tg3_get_nvram_info(tp);
14880
989a9d23
MC		 14881 if (tp->nvram_size == 0)
14882 tg3_get_nvram_size(tp);
1da177e4 14883
e6af301b 14884 tg3_disable_nvram_access(tp);
381291b7 14885 tg3_nvram_unlock(tp);
1da177e4
LT		 14886
14887 } else {
63c3a66f
JP		 14888 tg3_flag_clear(tp, NVRAM);
14889 tg3_flag_clear(tp, NVRAM_BUFFERED);
1da177e4
LT		 14890
14891 tg3_get_eeprom_size(tp);
14892 }
14893}
14894
1da177e4
LT		 14895struct subsys_tbl_ent {
14896 u16 subsys_vendor, subsys_devid;
14897 u32 phy_id;
14898};
14899
229b1ad1 14900static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
1da177e4 14901 /* Broadcom boards. */
24daf2b0 14902 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14903 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 14904 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14905 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 14906 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14907 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 14908 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14909 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14910 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14911 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 14912 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14913 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14914 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14915 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14916 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14917 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 14918 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14919 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 14920 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14921 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 14922 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14923 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 14924
14925 /* 3com boards. */
24daf2b0 14926 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14927 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 14928 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14929 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14930 { TG3PCI_SUBVENDOR_ID_3COM,
14931 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
14932 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14933 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 14934 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14935 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14936
14937 /* DELL boards. */
24daf2b0 14938 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14939 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 14940 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14941 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 14942 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14943 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 14944 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14945 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 14946
14947 /* Compaq boards. */
24daf2b0 14948 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14949 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 14950 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14951 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14952 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14953 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
14954 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14955 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 14956 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14957 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14958
14959 /* IBM boards. */
24daf2b0
MC		 14960 { TG3PCI_SUBVENDOR_ID_IBM,
14961 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 14962};
14963
229b1ad1 14964static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 14965{
14966 int i;
14967
14968 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
14969 if ((subsys_id_to_phy_id[i].subsys_vendor ==
14970 tp->pdev->subsystem_vendor) &&
14971 (subsys_id_to_phy_id[i].subsys_devid ==
14972 tp->pdev->subsystem_device))
14973 return &subsys_id_to_phy_id[i];
14974 }
14975 return NULL;
14976}
14977
229b1ad1 14978static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 14979{
1da177e4 14980 u32 val;
f49639e6 14981
79eb6904 14982 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 14983 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14984
a85feb8c 14985 /* Assume an onboard device and WOL capable by default. */
63c3a66f
JP		 14986 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14987 tg3_flag_set(tp, WOL_CAP);
72b845e0 14988
4153577a 14989 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9d26e213 14990 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
63c3a66f
JP		 14991 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14992 tg3_flag_set(tp, IS_NIC);
9d26e213 14993 }
0527ba35
MC		 14994 val = tr32(VCPU_CFGSHDW);
14995 if (val & VCPU_CFGSHDW_ASPM_DBNC)
63c3a66f 14996 tg3_flag_set(tp, ASPM_WORKAROUND);
0527ba35 14997 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
6fdbab9d 14998 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
63c3a66f 14999 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 15000 device_set_wakeup_enable(&tp->pdev->dev, true);
15001 }
05ac4cb7 15002 goto done;
b5d3772c
MC		 15003 }
15004
1da177e4
LT		 15005 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15006 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15007 u32 nic_cfg, led_cfg;
7c786065
NS		 15008 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15009 u32 nic_phy_id, ver, eeprom_phy_id;
7d0c41ef 15010 int eeprom_phy_serdes = 0;
1da177e4
LT		 15011
15012 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15013 tp->nic_sram_data_cfg = nic_cfg;
15014
15015 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15016 ver >>= NIC_SRAM_DATA_VER_SHIFT;
4153577a
JP		 15017 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15018 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15019 tg3_asic_rev(tp) != ASIC_REV_5703 &&
1da177e4
LT		 15020 (ver > 0) && (ver < 0x100))
15021 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15022
4153577a 15023 if (tg3_asic_rev(tp) == ASIC_REV_5785)
a9daf367
MC		 15024 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15025
7c786065
NS		 15026 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15027 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15028 tg3_asic_rev(tp) == ASIC_REV_5720)
15029 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15030
1da177e4
LT		 15031 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15032 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15033 eeprom_phy_serdes = 1;
15034
15035 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15036 if (nic_phy_id != 0) {
15037 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15038 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15039
15040 eeprom_phy_id = (id1 >> 16) << 10;
15041 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15042 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15043 } else
15044 eeprom_phy_id = 0;
15045
7d0c41ef 15046 tp->phy_id = eeprom_phy_id;
747e8f8b 15047 if (eeprom_phy_serdes) {
63c3a66f 15048 if (!tg3_flag(tp, 5705_PLUS))
f07e9af3 15049 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
a50d0796 15050 else
f07e9af3 15051 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
747e8f8b 15052 }
7d0c41ef 15053
63c3a66f 15054 if (tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 15055 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15056 SHASTA_EXT_LED_MODE_MASK);
cbf46853 15057 else
1da177e4
LT		 15058 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15059
15060 switch (led_cfg) {
15061 default:
15062 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15063 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15064 break;
15065
15066 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15067 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15068 break;
15069
15070 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15071 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 15072
15073 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15074 * read on some older 5700/5701 bootcode.
15075 */
4153577a
JP		 15076 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15077 tg3_asic_rev(tp) == ASIC_REV_5701)
9ba27794
MC		 15078 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15079
1da177e4
LT		 15080 break;
15081
15082 case SHASTA_EXT_LED_SHARED:
15083 tp->led_ctrl = LED_CTRL_MODE_SHARED;
4153577a
JP		 15084 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15085 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
1da177e4
LT		 15086 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15087 LED_CTRL_MODE_PHY_2);
89f67978
NS		 15088
15089 if (tg3_flag(tp, 5717_PLUS) ||
15090 tg3_asic_rev(tp) == ASIC_REV_5762)
15091 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15092 LED_CTRL_BLINK_RATE_MASK;
15093
1da177e4
LT		 15094 break;
15095
15096 case SHASTA_EXT_LED_MAC:
15097 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15098 break;
15099
15100 case SHASTA_EXT_LED_COMBO:
15101 tp->led_ctrl = LED_CTRL_MODE_COMBO;
4153577a 15102 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
1da177e4
LT		 15103 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15104 LED_CTRL_MODE_PHY_2);
15105 break;
15106
855e1111 15107 }
1da177e4 15108
4153577a
JP		 15109 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15110 tg3_asic_rev(tp) == ASIC_REV_5701) &&
1da177e4
LT		 15111 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15112 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15113
4153577a 15114 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
b2a5c19c 15115 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 15116
9d26e213 15117 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
63c3a66f 15118 tg3_flag_set(tp, EEPROM_WRITE_PROT);
9d26e213
MC		 15119 if ((tp->pdev->subsystem_vendor ==
15120 PCI_VENDOR_ID_ARIMA) &&
15121 (tp->pdev->subsystem_device == 0x205a ||
15122 tp->pdev->subsystem_device == 0x2063))
63c3a66f 15123 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
9d26e213 15124 } else {
63c3a66f
JP		 15125 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15126 tg3_flag_set(tp, IS_NIC);
9d26e213 15127 }
1da177e4
LT		 15128
15129 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f
JP		 15130 tg3_flag_set(tp, ENABLE_ASF);
15131 if (tg3_flag(tp, 5750_PLUS))
15132 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
1da177e4 15133 }
b2b98d4a
MC		 15134
15135 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
63c3a66f
JP		 15136 tg3_flag(tp, 5750_PLUS))
15137 tg3_flag_set(tp, ENABLE_APE);
b2b98d4a 15138
f07e9af3 15139 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
a85feb8c 15140 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
63c3a66f 15141 tg3_flag_clear(tp, WOL_CAP);
1da177e4 15142
63c3a66f 15143 if (tg3_flag(tp, WOL_CAP) &&
6fdbab9d 15144 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
63c3a66f 15145 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 15146 device_set_wakeup_enable(&tp->pdev->dev, true);
15147 }
0527ba35 15148
1da177e4 15149 if (cfg2 & (1 << 17))
f07e9af3 15150 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
1da177e4
LT		 15151
15152 /* serdes signal pre-emphasis in register 0x590 set by */
15153 /* bootcode if bit 18 is set */
15154 if (cfg2 & (1 << 18))
f07e9af3 15155 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
8ed5d97e 15156
63c3a66f 15157 if ((tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 15158 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15159 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
6833c043 15160 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
f07e9af3 15161 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
6833c043 15162
942d1af0 15163 if (tg3_flag(tp, PCI_EXPRESS)) {
8ed5d97e
MC		 15164 u32 cfg3;
15165
15166 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
942d1af0
NS		 15167 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15168 !tg3_flag(tp, 57765_PLUS) &&
15169 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
63c3a66f 15170 tg3_flag_set(tp, ASPM_WORKAROUND);
942d1af0
NS		 15171 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15172 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15173 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15174 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
8ed5d97e 15175 }
a9daf367 15176
14417063 15177 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
63c3a66f 15178 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
a9daf367 15179 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
63c3a66f 15180 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
a9daf367 15181 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
63c3a66f 15182 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
7c786065
NS		 15183
15184 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15185 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
1da177e4 15186 }
05ac4cb7 15187done:
63c3a66f 15188 if (tg3_flag(tp, WOL_CAP))
43067ed8 15189 device_set_wakeup_enable(&tp->pdev->dev,
63c3a66f 15190 tg3_flag(tp, WOL_ENABLE));
43067ed8
RW		 15191 else
15192 device_set_wakeup_capable(&tp->pdev->dev, false);
7d0c41ef
MC		 15193}
15194
c86a8560
MC		 15195static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15196{
15197 int i, err;
15198 u32 val2, off = offset * 8;
15199
15200 err = tg3_nvram_lock(tp);
15201 if (err)
15202 return err;
15203
15204 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15205 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15206 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15207 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15208 udelay(10);
15209
15210 for (i = 0; i < 100; i++) {
15211 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15212 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15213 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15214 break;
15215 }
15216 udelay(10);
15217 }
15218
15219 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15220
15221 tg3_nvram_unlock(tp);
15222 if (val2 & APE_OTP_STATUS_CMD_DONE)
15223 return 0;
15224
15225 return -EBUSY;
15226}
15227
229b1ad1 15228static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
b2a5c19c
MC		 15229{
15230 int i;
15231 u32 val;
15232
15233 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15234 tw32(OTP_CTRL, cmd);
15235
15236 /* Wait for up to 1 ms for command to execute. */
15237 for (i = 0; i < 100; i++) {
15238 val = tr32(OTP_STATUS);
15239 if (val & OTP_STATUS_CMD_DONE)
15240 break;
15241 udelay(10);
15242 }
15243
15244 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15245}
15246
15247/* Read the gphy configuration from the OTP region of the chip. The gphy
15248 * configuration is a 32-bit value that straddles the alignment boundary.
15249 * We do two 32-bit reads and then shift and merge the results.
15250 */
229b1ad1 15251static u32 tg3_read_otp_phycfg(struct tg3 *tp)
b2a5c19c
MC		 15252{
15253 u32 bhalf_otp, thalf_otp;
15254
15255 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15256
15257 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15258 return 0;
15259
15260 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15261
15262 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15263 return 0;
15264
15265 thalf_otp = tr32(OTP_READ_DATA);
15266
15267 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15268
15269 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15270 return 0;
15271
15272 bhalf_otp = tr32(OTP_READ_DATA);
15273
15274 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15275}
15276
229b1ad1 15277static void tg3_phy_init_link_config(struct tg3 *tp)
e256f8a3 15278{
202ff1c2 15279 u32 adv = ADVERTISED_Autoneg;
e256f8a3 15280
7c786065
NS		 15281 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15282 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15283 adv |= ADVERTISED_1000baseT_Half;
15284 adv |= ADVERTISED_1000baseT_Full;
15285 }
e256f8a3
MC		 15286
15287 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15288 adv |= ADVERTISED_100baseT_Half |
15289 ADVERTISED_100baseT_Full |
15290 ADVERTISED_10baseT_Half |
15291 ADVERTISED_10baseT_Full |
15292 ADVERTISED_TP;
15293 else
15294 adv |= ADVERTISED_FIBRE;
15295
15296 tp->link_config.advertising = adv;
e740522e
MC		 15297 tp->link_config.speed = SPEED_UNKNOWN;
15298 tp->link_config.duplex = DUPLEX_UNKNOWN;
e256f8a3 15299 tp->link_config.autoneg = AUTONEG_ENABLE;
e740522e
MC		 15300 tp->link_config.active_speed = SPEED_UNKNOWN;
15301 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
34655ad6
MC		 15302
15303 tp->old_link = -1;
e256f8a3
MC		 15304}
15305
229b1ad1 15306static int tg3_phy_probe(struct tg3 *tp)
7d0c41ef
MC		 15307{
15308 u32 hw_phy_id_1, hw_phy_id_2;
15309 u32 hw_phy_id, hw_phy_id_masked;
15310 int err;
1da177e4 15311
e256f8a3 15312 /* flow control autonegotiation is default behavior */
63c3a66f 15313 tg3_flag_set(tp, PAUSE_AUTONEG);
e256f8a3
MC		 15314 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15315
8151ad57
MC		 15316 if (tg3_flag(tp, ENABLE_APE)) {
15317 switch (tp->pci_fn) {
15318 case 0:
15319 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15320 break;
15321 case 1:
15322 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15323 break;
15324 case 2:
15325 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15326 break;
15327 case 3:
15328 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15329 break;
15330 }
15331 }
15332
942d1af0
NS		 15333 if (!tg3_flag(tp, ENABLE_ASF) &&
15334 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15335 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15336 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15337 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15338
63c3a66f 15339 if (tg3_flag(tp, USE_PHYLIB))
b02fd9e3
MC		 15340 return tg3_phy_init(tp);
15341
1da177e4 15342 /* Reading the PHY ID register can conflict with ASF
877d0310 15343 * firmware access to the PHY hardware.
1da177e4
LT		 15344 */
15345 err = 0;
63c3a66f 15346 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
79eb6904 15347 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 15348 } else {
15349 /* Now read the physical PHY_ID from the chip and verify
15350 * that it is sane. If it doesn't look good, we fall back
15351 * to either the hard-coded table based PHY_ID and failing
15352 * that the value found in the eeprom area.
15353 */
15354 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15355 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15356
15357 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15358 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15359 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15360
79eb6904 15361 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 15362 }
15363
79eb6904 15364 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 15365 tp->phy_id = hw_phy_id;
79eb6904 15366 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
f07e9af3 15367 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
da6b2d01 15368 else
f07e9af3 15369 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
1da177e4 15370 } else {
79eb6904 15371 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 15372 /* Do nothing, phy ID already set up in
15373 * tg3_get_eeprom_hw_cfg().
15374 */
1da177e4
LT		 15375 } else {
15376 struct subsys_tbl_ent *p;
15377
15378 /* No eeprom signature? Try the hardcoded
15379 * subsys device table.
15380 */
24daf2b0 15381 p = tg3_lookup_by_subsys(tp);
7e6c63f0
HM		 15382 if (p) {
15383 tp->phy_id = p->phy_id;
15384 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15385 /* For now we saw the IDs 0xbc050cd0,
15386 * 0xbc050f80 and 0xbc050c30 on devices
15387 * connected to an BCM4785 and there are
15388 * probably more. Just assume that the phy is
15389 * supported when it is connected to a SSB core
15390 * for now.
15391 */
1da177e4 15392 return -ENODEV;
7e6c63f0 15393 }
1da177e4 15394
1da177e4 15395 if (!tp->phy_id ||
79eb6904 15396 tp->phy_id == TG3_PHY_ID_BCM8002)
f07e9af3 15397 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
1da177e4
LT		 15398 }
15399 }
15400
a6b68dab 15401 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
4153577a
JP		 15402 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15403 tg3_asic_rev(tp) == ASIC_REV_5720 ||
c4dab506 15404 tg3_asic_rev(tp) == ASIC_REV_57766 ||
4153577a
JP		 15405 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15406 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15407 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15408 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
9e2ecbeb 15409 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
52b02d04
MC		 15410 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15411
9e2ecbeb
NS		 15412 tp->eee.supported = SUPPORTED_100baseT_Full |
15413 SUPPORTED_1000baseT_Full;
15414 tp->eee.advertised = ADVERTISED_100baseT_Full |
15415 ADVERTISED_1000baseT_Full;
15416 tp->eee.eee_enabled = 1;
15417 tp->eee.tx_lpi_enabled = 1;
15418 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15419 }
15420
e256f8a3
MC		 15421 tg3_phy_init_link_config(tp);
15422
942d1af0
NS		 15423 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15424 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
63c3a66f
JP		 15425 !tg3_flag(tp, ENABLE_APE) &&
15426 !tg3_flag(tp, ENABLE_ASF)) {
e2bf73e7 15427 u32 bmsr, dummy;
1da177e4
LT		 15428
15429 tg3_readphy(tp, MII_BMSR, &bmsr);
15430 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15431 (bmsr & BMSR_LSTATUS))
15432 goto skip_phy_reset;
6aa20a22 15433
1da177e4
LT		 15434 err = tg3_phy_reset(tp);
15435 if (err)
15436 return err;
15437
42b64a45 15438 tg3_phy_set_wirespeed(tp);
1da177e4 15439
e2bf73e7 15440 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
42b64a45
MC		 15441 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15442 tp->link_config.flowctrl);
1da177e4
LT		 15443
15444 tg3_writephy(tp, MII_BMCR,
15445 BMCR_ANENABLE | BMCR_ANRESTART);
15446 }
1da177e4
LT		 15447 }
15448
15449skip_phy_reset:
79eb6904 15450 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 15451 err = tg3_init_5401phy_dsp(tp);
15452 if (err)
15453 return err;
1da177e4 15454
1da177e4
LT		 15455 err = tg3_init_5401phy_dsp(tp);
15456 }
15457
1da177e4
LT		 15458 return err;
15459}
15460
229b1ad1 15461static void tg3_read_vpd(struct tg3 *tp)
1da177e4 15462{
a4a8bb15 15463 u8 *vpd_data;
4181b2c8 15464 unsigned int block_end, rosize, len;
535a490e 15465 u32 vpdlen;
184b8904 15466 int j, i = 0;
a4a8bb15 15467
535a490e 15468 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
a4a8bb15
MC		 15469 if (!vpd_data)
15470 goto out_no_vpd;
1da177e4 15471
535a490e 15472 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
4181b2c8
MC		 15473 if (i < 0)
15474 goto out_not_found;
1da177e4 15475
4181b2c8
MC		 15476 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15477 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15478 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 15479
535a490e 15480 if (block_end > vpdlen)
4181b2c8 15481 goto out_not_found;
af2c6a4a 15482
184b8904
MC		 15483 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15484 PCI_VPD_RO_KEYWORD_MFR_ID);
15485 if (j > 0) {
15486 len = pci_vpd_info_field_size(&vpd_data[j]);
15487
15488 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15489 if (j + len > block_end || len != 4 ||
15490 memcmp(&vpd_data[j], "1028", 4))
15491 goto partno;
15492
15493 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15494 PCI_VPD_RO_KEYWORD_VENDOR0);
15495 if (j < 0)
15496 goto partno;
15497
15498 len = pci_vpd_info_field_size(&vpd_data[j]);
15499
15500 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15501 if (j + len > block_end)
15502 goto partno;
15503
715230a4
KC		 15504 if (len >= sizeof(tp->fw_ver))
15505 len = sizeof(tp->fw_ver) - 1;
15506 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15507 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15508 &vpd_data[j]);
184b8904
MC		 15509 }
15510
15511partno:
4181b2c8
MC		 15512 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15513 PCI_VPD_RO_KEYWORD_PARTNO);
15514 if (i < 0)
15515 goto out_not_found;
af2c6a4a 15516
4181b2c8 15517 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 15518
4181b2c8
MC		 15519 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15520 if (len > TG3_BPN_SIZE ||
535a490e 15521 (len + i) > vpdlen)
4181b2c8 15522 goto out_not_found;
1da177e4 15523
4181b2c8 15524 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 15525
1da177e4 15526out_not_found:
a4a8bb15 15527 kfree(vpd_data);
37a949c5 15528 if (tp->board_part_number[0])
a4a8bb15
MC		 15529 return;
15530
15531out_no_vpd:
4153577a 15532 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
79d49695
MC		 15533 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15534 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
37a949c5
MC		 15535 strcpy(tp->board_part_number, "BCM5717");
15536 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15537 strcpy(tp->board_part_number, "BCM5718");
15538 else
15539 goto nomatch;
4153577a 15540 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
37a949c5
MC		 15541 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15542 strcpy(tp->board_part_number, "BCM57780");
15543 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15544 strcpy(tp->board_part_number, "BCM57760");
15545 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15546 strcpy(tp->board_part_number, "BCM57790");
15547 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15548 strcpy(tp->board_part_number, "BCM57788");
15549 else
15550 goto nomatch;
4153577a 15551 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
37a949c5
MC		 15552 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15553 strcpy(tp->board_part_number, "BCM57761");
15554 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15555 strcpy(tp->board_part_number, "BCM57765");
15556 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15557 strcpy(tp->board_part_number, "BCM57781");
15558 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15559 strcpy(tp->board_part_number, "BCM57785");
15560 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15561 strcpy(tp->board_part_number, "BCM57791");
15562 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15563 strcpy(tp->board_part_number, "BCM57795");
15564 else
15565 goto nomatch;
4153577a 15566 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
55086ad9
MC		 15567 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15568 strcpy(tp->board_part_number, "BCM57762");
15569 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15570 strcpy(tp->board_part_number, "BCM57766");
15571 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15572 strcpy(tp->board_part_number, "BCM57782");
15573 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15574 strcpy(tp->board_part_number, "BCM57786");
15575 else
15576 goto nomatch;
4153577a 15577 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c 15578 strcpy(tp->board_part_number, "BCM95906");
37a949c5
MC		 15579 } else {
15580nomatch:
b5d3772c 15581 strcpy(tp->board_part_number, "none");
37a949c5 15582 }
1da177e4
LT		 15583}
15584
229b1ad1 15585static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
9c8a620e
MC		 15586{
15587 u32 val;
15588
e4f34110 15589 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 15590 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 15591 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 15592 val != 0)
15593 return 0;
15594
15595 return 1;
15596}
15597
229b1ad1 15598static void tg3_read_bc_ver(struct tg3 *tp)
acd9c119 15599{
ff3a7cb2 15600 u32 val, offset, start, ver_offset;
75f9936e 15601 int i, dst_off;
ff3a7cb2 15602 bool newver = false;
acd9c119
MC		 15603
15604 if (tg3_nvram_read(tp, 0xc, &offset) ||
15605 tg3_nvram_read(tp, 0x4, &start))
15606 return;
15607
15608 offset = tg3_nvram_logical_addr(tp, offset);
15609
ff3a7cb2 15610 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 15611 return;
15612
ff3a7cb2
MC		 15613 if ((val & 0xfc000000) == 0x0c000000) {
15614 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 15615 return;
15616
ff3a7cb2
MC		 15617 if (val == 0)
15618 newver = true;
15619 }
15620
75f9936e
MC		 15621 dst_off = strlen(tp->fw_ver);
15622
ff3a7cb2 15623 if (newver) {
75f9936e
MC		 15624 if (TG3_VER_SIZE - dst_off < 16 ||
15625 tg3_nvram_read(tp, offset + 8, &ver_offset))
ff3a7cb2
MC		 15626 return;
15627
15628 offset = offset + ver_offset - start;
15629 for (i = 0; i < 16; i += 4) {
15630 __be32 v;
15631 if (tg3_nvram_read_be32(tp, offset + i, &v))
15632 return;
15633
75f9936e 15634 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
ff3a7cb2
MC		 15635 }
15636 } else {
15637 u32 major, minor;
15638
15639 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15640 return;
15641
15642 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15643 TG3_NVM_BCVER_MAJSFT;
15644 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
75f9936e
MC		 15645 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15646 "v%d.%02d", major, minor);
acd9c119
MC		 15647 }
15648}
15649
229b1ad1 15650static void tg3_read_hwsb_ver(struct tg3 *tp)
a6f6cb1c
MC		 15651{
15652 u32 val, major, minor;
15653
15654 /* Use native endian representation */
15655 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15656 return;
15657
15658 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15659 TG3_NVM_HWSB_CFG1_MAJSFT;
15660 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15661 TG3_NVM_HWSB_CFG1_MINSFT;
15662
15663 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15664}
15665
229b1ad1 15666static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
dfe00d7d
MC		 15667{
15668 u32 offset, major, minor, build;
15669
75f9936e 15670 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
dfe00d7d
MC		 15671
15672 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15673 return;
15674
15675 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15676 case TG3_EEPROM_SB_REVISION_0:
15677 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15678 break;
15679 case TG3_EEPROM_SB_REVISION_2:
15680 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15681 break;
15682 case TG3_EEPROM_SB_REVISION_3:
15683 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15684 break;
a4153d40
MC		 15685 case TG3_EEPROM_SB_REVISION_4:
15686 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15687 break;
15688 case TG3_EEPROM_SB_REVISION_5:
15689 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15690 break;
bba226ac
MC		 15691 case TG3_EEPROM_SB_REVISION_6:
15692 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15693 break;
dfe00d7d
MC		 15694 default:
15695 return;
15696 }
15697
e4f34110 15698 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 15699 return;
15700
15701 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15702 TG3_EEPROM_SB_EDH_BLD_SHFT;
15703 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15704 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15705 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15706
15707 if (minor > 99 || build > 26)
15708 return;
15709
75f9936e
MC		 15710 offset = strlen(tp->fw_ver);
15711 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15712 " v%d.%02d", major, minor);
dfe00d7d
MC		 15713
15714 if (build > 0) {
75f9936e
MC		 15715 offset = strlen(tp->fw_ver);
15716 if (offset < TG3_VER_SIZE - 1)
15717 tp->fw_ver[offset] = 'a' + build - 1;
dfe00d7d
MC		 15718 }
15719}
15720
229b1ad1 15721static void tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 15722{
15723 u32 val, offset, start;
acd9c119 15724 int i, vlen;
9c8a620e
MC		 15725
15726 for (offset = TG3_NVM_DIR_START;
15727 offset < TG3_NVM_DIR_END;
15728 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 15729 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 15730 return;
15731
9c8a620e
MC		 15732 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15733 break;
15734 }
15735
15736 if (offset == TG3_NVM_DIR_END)
15737 return;
15738
63c3a66f 15739 if (!tg3_flag(tp, 5705_PLUS))
9c8a620e 15740 start = 0x08000000;
e4f34110 15741 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 15742 return;
15743
e4f34110 15744 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 15745 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 15746 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 15747 return;
15748
15749 offset += val - start;
15750
acd9c119 15751 vlen = strlen(tp->fw_ver);
9c8a620e 15752
acd9c119
MC		 15753 tp->fw_ver[vlen++] = ',';
15754 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 15755
15756 for (i = 0; i < 4; i++) {
a9dc529d
MC		 15757 __be32 v;
15758 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 15759 return;
15760
b9fc7dc5 15761 offset += sizeof(v);
c4e6575c 15762
acd9c119
MC		 15763 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15764 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 15765 break;
c4e6575c 15766 }
9c8a620e 15767
acd9c119
MC		 15768 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15769 vlen += sizeof(v);
c4e6575c 15770 }
acd9c119
MC		 15771}
15772
229b1ad1 15773static void tg3_probe_ncsi(struct tg3 *tp)
7fd76445 15774{
7fd76445 15775 u32 apedata;
7fd76445
MC		 15776
15777 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15778 if (apedata != APE_SEG_SIG_MAGIC)
15779 return;
15780
15781 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15782 if (!(apedata & APE_FW_STATUS_READY))
15783 return;
15784
165f4d1c
MC		 15785 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15786 tg3_flag_set(tp, APE_HAS_NCSI);
15787}
15788
229b1ad1 15789static void tg3_read_dash_ver(struct tg3 *tp)
165f4d1c
MC		 15790{
15791 int vlen;
15792 u32 apedata;
15793 char *fwtype;
15794
7fd76445
MC		 15795 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15796
165f4d1c 15797 if (tg3_flag(tp, APE_HAS_NCSI))
ecc79648 15798 fwtype = "NCSI";
c86a8560
MC		 15799 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15800 fwtype = "SMASH";
165f4d1c 15801 else
ecc79648
MC		 15802 fwtype = "DASH";
15803
7fd76445
MC		 15804 vlen = strlen(tp->fw_ver);
15805
ecc79648
MC		 15806 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15807 fwtype,
7fd76445
MC		 15808 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15809 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15810 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15811 (apedata & APE_FW_VERSION_BLDMSK));
15812}
15813
c86a8560
MC		 15814static void tg3_read_otp_ver(struct tg3 *tp)
15815{
15816 u32 val, val2;
15817
4153577a 15818 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c86a8560
MC		 15819 return;
15820
15821 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15822 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15823 TG3_OTP_MAGIC0_VALID(val)) {
15824 u64 val64 = (u64) val << 32 | val2;
15825 u32 ver = 0;
15826 int i, vlen;
15827
15828 for (i = 0; i < 7; i++) {
15829 if ((val64 & 0xff) == 0)
15830 break;
15831 ver = val64 & 0xff;
15832 val64 >>= 8;
15833 }
15834 vlen = strlen(tp->fw_ver);
15835 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15836 }
15837}
15838
229b1ad1 15839static void tg3_read_fw_ver(struct tg3 *tp)
acd9c119
MC		 15840{
15841 u32 val;
75f9936e 15842 bool vpd_vers = false;
acd9c119 15843
75f9936e
MC		 15844 if (tp->fw_ver[0] != 0)
15845 vpd_vers = true;
df259d8c 15846
63c3a66f 15847 if (tg3_flag(tp, NO_NVRAM)) {
75f9936e 15848 strcat(tp->fw_ver, "sb");
c86a8560 15849 tg3_read_otp_ver(tp);
df259d8c
MC		 15850 return;
15851 }
15852
acd9c119
MC		 15853 if (tg3_nvram_read(tp, 0, &val))
15854 return;
15855
15856 if (val == TG3_EEPROM_MAGIC)
15857 tg3_read_bc_ver(tp);
15858 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15859 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 15860 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15861 tg3_read_hwsb_ver(tp);
acd9c119 15862
165f4d1c
MC		 15863 if (tg3_flag(tp, ENABLE_ASF)) {
15864 if (tg3_flag(tp, ENABLE_APE)) {
15865 tg3_probe_ncsi(tp);
15866 if (!vpd_vers)
15867 tg3_read_dash_ver(tp);
15868 } else if (!vpd_vers) {
15869 tg3_read_mgmtfw_ver(tp);
15870 }
c9cab24e 15871 }
9c8a620e
MC		 15872
15873 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 15874}
15875
7cb32cf2
MC		 15876static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15877{
63c3a66f 15878 if (tg3_flag(tp, LRG_PROD_RING_CAP))
de9f5230 15879 return TG3_RX_RET_MAX_SIZE_5717;
63c3a66f 15880 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
de9f5230 15881 return TG3_RX_RET_MAX_SIZE_5700;
7cb32cf2 15882 else
de9f5230 15883 return TG3_RX_RET_MAX_SIZE_5705;
7cb32cf2
MC		 15884}
15885
4143470c 15886static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
895950c2
JP		 15887 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15888 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15889 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15890 { },
15891};
15892
229b1ad1 15893static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16c7fa7d
MC		 15894{
15895 struct pci_dev *peer;
15896 unsigned int func, devnr = tp->pdev->devfn & ~7;
15897
15898 for (func = 0; func < 8; func++) {
15899 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15900 if (peer && peer != tp->pdev)
15901 break;
15902 pci_dev_put(peer);
15903 }
15904 /* 5704 can be configured in single-port mode, set peer to
15905 * tp->pdev in that case.
15906 */
15907 if (!peer) {
15908 peer = tp->pdev;
15909 return peer;
15910 }
15911
15912 /*
15913 * We don't need to keep the refcount elevated; there's no way
15914 * to remove one half of this device without removing the other
15915 */
15916 pci_dev_put(peer);
15917
15918 return peer;
15919}
15920
229b1ad1 15921static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
42b123b1
MC		 15922{
15923 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
4153577a 15924 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
42b123b1
MC		 15925 u32 reg;
15926
15927 /* All devices that use the alternate
15928 * ASIC REV location have a CPMU.
15929 */
15930 tg3_flag_set(tp, CPMU_PRESENT);
15931
15932 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 15933 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
42b123b1
MC		 15934 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15935 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 15936 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 15937 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
15938 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 15939 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
15940 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 15941 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
15942 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
42b123b1
MC		 15943 reg = TG3PCI_GEN2_PRODID_ASICREV;
15944 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
15945 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
15946 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
15947 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
15948 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15949 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
15950 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
15951 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
15952 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
15953 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15954 reg = TG3PCI_GEN15_PRODID_ASICREV;
15955 else
15956 reg = TG3PCI_PRODID_ASICREV;
15957
15958 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
15959 }
15960
15961 /* Wrong chip ID in 5752 A0. This code can be removed later
15962 * as A0 is not in production.
15963 */
4153577a 15964 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
42b123b1
MC		 15965 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
15966
4153577a 15967 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
79d49695
MC		 15968 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
15969
4153577a
JP		 15970 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15971 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15972 tg3_asic_rev(tp) == ASIC_REV_5720)
42b123b1
MC		 15973 tg3_flag_set(tp, 5717_PLUS);
15974
4153577a
JP		 15975 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
15976 tg3_asic_rev(tp) == ASIC_REV_57766)
42b123b1
MC		 15977 tg3_flag_set(tp, 57765_CLASS);
15978
c65a17f4 15979 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
4153577a 15980 tg3_asic_rev(tp) == ASIC_REV_5762)
42b123b1
MC		 15981 tg3_flag_set(tp, 57765_PLUS);
15982
15983 /* Intentionally exclude ASIC_REV_5906 */
4153577a
JP		 15984 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
15985 tg3_asic_rev(tp) == ASIC_REV_5787 ||
15986 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15987 tg3_asic_rev(tp) == ASIC_REV_5761 ||
15988 tg3_asic_rev(tp) == ASIC_REV_5785 ||
15989 tg3_asic_rev(tp) == ASIC_REV_57780 ||
42b123b1
MC		 15990 tg3_flag(tp, 57765_PLUS))
15991 tg3_flag_set(tp, 5755_PLUS);
15992
4153577a
JP		 15993 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
15994 tg3_asic_rev(tp) == ASIC_REV_5714)
42b123b1
MC		 15995 tg3_flag_set(tp, 5780_CLASS);
15996
4153577a
JP		 15997 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
15998 tg3_asic_rev(tp) == ASIC_REV_5752 ||
15999 tg3_asic_rev(tp) == ASIC_REV_5906 ||
42b123b1
MC		 16000 tg3_flag(tp, 5755_PLUS) ||
16001 tg3_flag(tp, 5780_CLASS))
16002 tg3_flag_set(tp, 5750_PLUS);
16003
4153577a 16004 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
42b123b1
MC		 16005 tg3_flag(tp, 5750_PLUS))
16006 tg3_flag_set(tp, 5705_PLUS);
16007}
16008
3d567e0e
NNS		 16009static bool tg3_10_100_only_device(struct tg3 *tp,
16010 const struct pci_device_id *ent)
16011{
16012 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16013
4153577a
JP		 16014 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16015 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
3d567e0e
NNS		 16016 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16017 return true;
16018
16019 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
4153577a 16020 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3d567e0e
NNS		 16021 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16022 return true;
16023 } else {
16024 return true;
16025 }
16026 }
16027
16028 return false;
16029}
16030
1dd06ae8 16031static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
1da177e4 16032{
1da177e4 16033 u32 misc_ctrl_reg;
1da177e4
LT		 16034 u32 pci_state_reg, grc_misc_cfg;
16035 u32 val;
16036 u16 pci_cmd;
5e7dfd0f 16037 int err;
1da177e4 16038
1da177e4
LT		 16039 /* Force memory write invalidate off. If we leave it on,
16040 * then on 5700_BX chips we have to enable a workaround.
16041 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16042 * to match the cacheline size. The Broadcom driver have this
16043 * workaround but turns MWI off all the times so never uses
16044 * it. This seems to suggest that the workaround is insufficient.
16045 */
16046 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16047 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16048 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16049
16821285
MC		 16050 /* Important! -- Make sure register accesses are byteswapped
16051 * correctly. Also, for those chips that require it, make
16052 * sure that indirect register accesses are enabled before
16053 * the first operation.
1da177e4
LT		 16054 */
16055 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16056 &misc_ctrl_reg);
16821285
MC		 16057 tp->misc_host_ctrl |= (misc_ctrl_reg &
16058 MISC_HOST_CTRL_CHIPREV);
16059 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16060 tp->misc_host_ctrl);
1da177e4 16061
42b123b1 16062 tg3_detect_asic_rev(tp, misc_ctrl_reg);
ff645bec 16063
6892914f
MC		 16064 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16065 * we need to disable memory and use config. cycles
16066 * only to access all registers. The 5702/03 chips
16067 * can mistakenly decode the special cycles from the
16068 * ICH chipsets as memory write cycles, causing corruption
16069 * of register and memory space. Only certain ICH bridges
16070 * will drive special cycles with non-zero data during the
16071 * address phase which can fall within the 5703's address
16072 * range. This is not an ICH bug as the PCI spec allows
16073 * non-zero address during special cycles. However, only
16074 * these ICH bridges are known to drive non-zero addresses
16075 * during special cycles.
16076 *
16077 * Since special cycles do not cross PCI bridges, we only
16078 * enable this workaround if the 5703 is on the secondary
16079 * bus of these ICH bridges.
16080 */
4153577a
JP		 16081 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16082 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
6892914f
MC		 16083 static struct tg3_dev_id {
16084 u32 vendor;
16085 u32 device;
16086 u32 rev;
16087 } ich_chipsets[] = {
16088 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16089 PCI_ANY_ID },
16090 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16091 PCI_ANY_ID },
16092 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16093 0xa },
16094 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16095 PCI_ANY_ID },
16096 { },
16097 };
16098 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16099 struct pci_dev *bridge = NULL;
16100
16101 while (pci_id->vendor != 0) {
16102 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16103 bridge);
16104 if (!bridge) {
16105 pci_id++;
16106 continue;
16107 }
16108 if (pci_id->rev != PCI_ANY_ID) {
44c10138 16109 if (bridge->revision > pci_id->rev)
6892914f
MC		 16110 continue;
16111 }
16112 if (bridge->subordinate &&
16113 (bridge->subordinate->number ==
16114 tp->pdev->bus->number)) {
63c3a66f 16115 tg3_flag_set(tp, ICH_WORKAROUND);
6892914f
MC		 16116 pci_dev_put(bridge);
16117 break;
16118 }
16119 }
16120 }
16121
4153577a 16122 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
41588ba1
MC		 16123 static struct tg3_dev_id {
16124 u32 vendor;
16125 u32 device;
16126 } bridge_chipsets[] = {
16127 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16128 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16129 { },
16130 };
16131 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16132 struct pci_dev *bridge = NULL;
16133
16134 while (pci_id->vendor != 0) {
16135 bridge = pci_get_device(pci_id->vendor,
16136 pci_id->device,
16137 bridge);
16138 if (!bridge) {
16139 pci_id++;
16140 continue;
16141 }
16142 if (bridge->subordinate &&
16143 (bridge->subordinate->number <=
16144 tp->pdev->bus->number) &&
b918c62e 16145 (bridge->subordinate->busn_res.end >=
41588ba1 16146 tp->pdev->bus->number)) {
63c3a66f 16147 tg3_flag_set(tp, 5701_DMA_BUG);
41588ba1
MC		 16148 pci_dev_put(bridge);
16149 break;
16150 }
16151 }
16152 }
16153
4a29cc2e
MC		 16154 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16155 * DMA addresses > 40-bit. This bridge may have other additional
16156 * 57xx devices behind it in some 4-port NIC designs for example.
16157 * Any tg3 device found behind the bridge will also need the 40-bit
16158 * DMA workaround.
16159 */
42b123b1 16160 if (tg3_flag(tp, 5780_CLASS)) {
63c3a66f 16161 tg3_flag_set(tp, 40BIT_DMA_BUG);
0f847584 16162 tp->msi_cap = tp->pdev->msi_cap;
859a5887 16163 } else {
4a29cc2e
MC		 16164 struct pci_dev *bridge = NULL;
16165
16166 do {
16167 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16168 PCI_DEVICE_ID_SERVERWORKS_EPB,
16169 bridge);
16170 if (bridge && bridge->subordinate &&
16171 (bridge->subordinate->number <=
16172 tp->pdev->bus->number) &&
b918c62e 16173 (bridge->subordinate->busn_res.end >=
4a29cc2e 16174 tp->pdev->bus->number)) {
63c3a66f 16175 tg3_flag_set(tp, 40BIT_DMA_BUG);
4a29cc2e
MC		 16176 pci_dev_put(bridge);
16177 break;
16178 }
16179 } while (bridge);
16180 }
4cf78e4f 16181
4153577a
JP		 16182 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16183 tg3_asic_rev(tp) == ASIC_REV_5714)
7544b097
MC		 16184 tp->pdev_peer = tg3_find_peer(tp);
16185
507399f1 16186 /* Determine TSO capabilities */
4153577a 16187 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
4d163b75 16188 ; /* Do nothing. HW bug. */
63c3a66f
JP		 16189 else if (tg3_flag(tp, 57765_PLUS))
16190 tg3_flag_set(tp, HW_TSO_3);
16191 else if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16192 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f
JP		 16193 tg3_flag_set(tp, HW_TSO_2);
16194 else if (tg3_flag(tp, 5750_PLUS)) {
16195 tg3_flag_set(tp, HW_TSO_1);
16196 tg3_flag_set(tp, TSO_BUG);
4153577a
JP		 16197 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16198 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
63c3a66f 16199 tg3_flag_clear(tp, TSO_BUG);
4153577a
JP		 16200 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16201 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16202 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
1caf13eb
MC		 16203 tg3_flag_set(tp, FW_TSO);
16204 tg3_flag_set(tp, TSO_BUG);
4153577a 16205 if (tg3_asic_rev(tp) == ASIC_REV_5705)
507399f1
MC		 16206 tp->fw_needed = FIRMWARE_TG3TSO5;
16207 else
16208 tp->fw_needed = FIRMWARE_TG3TSO;
16209 }
16210
dabc5c67 16211 /* Selectively allow TSO based on operating conditions */
6ff6f81d
MC		 16212 if (tg3_flag(tp, HW_TSO_1) ||
16213 tg3_flag(tp, HW_TSO_2) ||
16214 tg3_flag(tp, HW_TSO_3) ||
1caf13eb 16215 tg3_flag(tp, FW_TSO)) {
cf9ecf4b
MC		 16216 /* For firmware TSO, assume ASF is disabled.
16217 * We'll disable TSO later if we discover ASF
16218 * is enabled in tg3_get_eeprom_hw_cfg().
16219 */
dabc5c67 16220 tg3_flag_set(tp, TSO_CAPABLE);
cf9ecf4b 16221 } else {
dabc5c67
MC		 16222 tg3_flag_clear(tp, TSO_CAPABLE);
16223 tg3_flag_clear(tp, TSO_BUG);
16224 tp->fw_needed = NULL;
16225 }
16226
4153577a 16227 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
dabc5c67
MC		 16228 tp->fw_needed = FIRMWARE_TG3;
16229
c4dab506
NS		 16230 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16231 tp->fw_needed = FIRMWARE_TG357766;
16232
507399f1
MC		 16233 tp->irq_max = 1;
16234
63c3a66f
JP		 16235 if (tg3_flag(tp, 5750_PLUS)) {
16236 tg3_flag_set(tp, SUPPORT_MSI);
4153577a
JP		 16237 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16238 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16239 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16240 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
7544b097 16241 tp->pdev_peer == tp->pdev))
63c3a66f 16242 tg3_flag_clear(tp, SUPPORT_MSI);
7544b097 16243
63c3a66f 16244 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16245 tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16246 tg3_flag_set(tp, 1SHOT_MSI);
52c0fd83 16247 }
4f125f42 16248
63c3a66f
JP		 16249 if (tg3_flag(tp, 57765_PLUS)) {
16250 tg3_flag_set(tp, SUPPORT_MSIX);
507399f1
MC		 16251 tp->irq_max = TG3_IRQ_MAX_VECS;
16252 }
f6eb9b1f 16253 }
0e1406dd 16254
9102426a
MC		 16255 tp->txq_max = 1;
16256 tp->rxq_max = 1;
16257 if (tp->irq_max > 1) {
16258 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16259 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16260
4153577a
JP		 16261 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16262 tg3_asic_rev(tp) == ASIC_REV_5720)
9102426a
MC		 16263 tp->txq_max = tp->irq_max - 1;
16264 }
16265
b7abee6e 16266 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16267 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f 16268 tg3_flag_set(tp, SHORT_DMA_BUG);
f6eb9b1f 16269
4153577a 16270 if (tg3_asic_rev(tp) == ASIC_REV_5719)
a4cb428d 16271 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
e31aa987 16272
4153577a
JP		 16273 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16274 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16275 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16276 tg3_asic_rev(tp) == ASIC_REV_5762)
63c3a66f 16277 tg3_flag_set(tp, LRG_PROD_RING_CAP);
de9f5230 16278
63c3a66f 16279 if (tg3_flag(tp, 57765_PLUS) &&
4153577a 16280 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
63c3a66f 16281 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
b703df6f 16282
63c3a66f
JP		 16283 if (!tg3_flag(tp, 5705_PLUS) ||
16284 tg3_flag(tp, 5780_CLASS) ||
16285 tg3_flag(tp, USE_JUMBO_BDFLAG))
16286 tg3_flag_set(tp, JUMBO_CAPABLE);
0f893dc6 16287
52f4490c
MC		 16288 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16289 &pci_state_reg);
16290
708ebb3a 16291 if (pci_is_pcie(tp->pdev)) {
5e7dfd0f
MC		 16292 u16 lnkctl;
16293
63c3a66f 16294 tg3_flag_set(tp, PCI_EXPRESS);
5f5c51e3 16295
0f49bfbd 16296 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
5e7dfd0f 16297 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
4153577a 16298 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16299 tg3_flag_clear(tp, HW_TSO_2);
dabc5c67 16300 tg3_flag_clear(tp, TSO_CAPABLE);
7196cd6c 16301 }
4153577a
JP		 16302 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16303 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16304 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16305 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
63c3a66f 16306 tg3_flag_set(tp, CLKREQ_BUG);
4153577a 16307 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
63c3a66f 16308 tg3_flag_set(tp, L1PLLPD_EN);
c7835a77 16309 }
4153577a 16310 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
708ebb3a
JM		 16311 /* BCM5785 devices are effectively PCIe devices, and should
16312 * follow PCIe codepaths, but do not have a PCIe capabilities
16313 * section.
93a700a9 16314 */
63c3a66f
JP		 16315 tg3_flag_set(tp, PCI_EXPRESS);
16316 } else if (!tg3_flag(tp, 5705_PLUS) ||
16317 tg3_flag(tp, 5780_CLASS)) {
52f4490c
MC		 16318 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16319 if (!tp->pcix_cap) {
2445e461
MC		 16320 dev_err(&tp->pdev->dev,
16321 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 16322 return -EIO;
16323 }
16324
16325 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
63c3a66f 16326 tg3_flag_set(tp, PCIX_MODE);
52f4490c 16327 }
1da177e4 16328
399de50b
MC		 16329 /* If we have an AMD 762 or VIA K8T800 chipset, write
16330 * reordering to the mailbox registers done by the host
16331 * controller can cause major troubles. We read back from
16332 * every mailbox register write to force the writes to be
16333 * posted to the chip in order.
16334 */
4143470c 16335 if (pci_dev_present(tg3_write_reorder_chipsets) &&
63c3a66f
JP		 16336 !tg3_flag(tp, PCI_EXPRESS))
16337 tg3_flag_set(tp, MBOX_WRITE_REORDER);
399de50b 16338
69fc4053
MC		 16339 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16340 &tp->pci_cacheline_sz);
16341 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16342 &tp->pci_lat_timer);
4153577a 16343 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
1da177e4
LT		 16344 tp->pci_lat_timer < 64) {
16345 tp->pci_lat_timer = 64;
69fc4053
MC		 16346 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16347 tp->pci_lat_timer);
1da177e4
LT		 16348 }
16349
16821285
MC		 16350 /* Important! -- It is critical that the PCI-X hw workaround
16351 * situation is decided before the first MMIO register access.
16352 */
4153577a 16353 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
52f4490c
MC		 16354 /* 5700 BX chips need to have their TX producer index
16355 * mailboxes written twice to workaround a bug.
16356 */
63c3a66f 16357 tg3_flag_set(tp, TXD_MBOX_HWBUG);
1da177e4 16358
52f4490c 16359 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 16360 *
16361 * The workaround is to use indirect register accesses
16362 * for all chip writes not to mailbox registers.
16363 */
63c3a66f 16364 if (tg3_flag(tp, PCIX_MODE)) {
1da177e4 16365 u32 pm_reg;
1da177e4 16366
63c3a66f 16367 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16368
16369 /* The chip can have it's power management PCI config
16370 * space registers clobbered due to this bug.
16371 * So explicitly force the chip into D0 here.
16372 */
9974a356 16373 pci_read_config_dword(tp->pdev,
0319f30e 16374 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16375 &pm_reg);
16376 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16377 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356 16378 pci_write_config_dword(tp->pdev,
0319f30e 16379 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16380 pm_reg);
16381
16382 /* Also, force SERR#/PERR# in PCI command. */
16383 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16384 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16385 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16386 }
16387 }
16388
1da177e4 16389 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
63c3a66f 16390 tg3_flag_set(tp, PCI_HIGH_SPEED);
1da177e4 16391 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
63c3a66f 16392 tg3_flag_set(tp, PCI_32BIT);
1da177e4
LT		 16393
16394 /* Chip-specific fixup from Broadcom driver */
4153577a 16395 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
1da177e4
LT		 16396 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16397 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16398 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16399 }
16400
1ee582d8 16401 /* Default fast path register access methods */
20094930 16402 tp->read32 = tg3_read32;
1ee582d8 16403 tp->write32 = tg3_write32;
09ee929c 16404 tp->read32_mbox = tg3_read32;
20094930 16405 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 16406 tp->write32_tx_mbox = tg3_write32;
16407 tp->write32_rx_mbox = tg3_write32;
16408
16409 /* Various workaround register access methods */
63c3a66f 16410 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
1ee582d8 16411 tp->write32 = tg3_write_indirect_reg32;
4153577a 16412 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
63c3a66f 16413 (tg3_flag(tp, PCI_EXPRESS) &&
4153577a 16414 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
98efd8a6
MC		 16415 /*
16416 * Back to back register writes can cause problems on these
16417 * chips, the workaround is to read back all reg writes
16418 * except those to mailbox regs.
16419 *
16420 * See tg3_write_indirect_reg32().
16421 */
1ee582d8 16422 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 16423 }
16424
63c3a66f 16425 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
1ee582d8 16426 tp->write32_tx_mbox = tg3_write32_tx_mbox;
63c3a66f 16427 if (tg3_flag(tp, MBOX_WRITE_REORDER))
1ee582d8
MC		 16428 tp->write32_rx_mbox = tg3_write_flush_reg32;
16429 }
20094930 16430
63c3a66f 16431 if (tg3_flag(tp, ICH_WORKAROUND)) {
6892914f
MC		 16432 tp->read32 = tg3_read_indirect_reg32;
16433 tp->write32 = tg3_write_indirect_reg32;
16434 tp->read32_mbox = tg3_read_indirect_mbox;
16435 tp->write32_mbox = tg3_write_indirect_mbox;
16436 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16437 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16438
16439 iounmap(tp->regs);
22abe310 16440 tp->regs = NULL;
6892914f
MC		 16441
16442 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16443 pci_cmd &= ~PCI_COMMAND_MEMORY;
16444 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16445 }
4153577a 16446 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 16447 tp->read32_mbox = tg3_read32_mbox_5906;
16448 tp->write32_mbox = tg3_write32_mbox_5906;
16449 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16450 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16451 }
6892914f 16452
bbadf503 16453 if (tp->write32 == tg3_write_indirect_reg32 ||
63c3a66f 16454 (tg3_flag(tp, PCIX_MODE) &&
4153577a
JP		 16455 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16456 tg3_asic_rev(tp) == ASIC_REV_5701)))
63c3a66f 16457 tg3_flag_set(tp, SRAM_USE_CONFIG);
bbadf503 16458
16821285
MC		 16459 /* The memory arbiter has to be enabled in order for SRAM accesses
16460 * to succeed. Normally on powerup the tg3 chip firmware will make
16461 * sure it is enabled, but other entities such as system netboot
16462 * code might disable it.
16463 */
16464 val = tr32(MEMARB_MODE);
16465 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16466
9dc5e342 16467 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
4153577a 16468 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
9dc5e342
MC		 16469 tg3_flag(tp, 5780_CLASS)) {
16470 if (tg3_flag(tp, PCIX_MODE)) {
16471 pci_read_config_dword(tp->pdev,
16472 tp->pcix_cap + PCI_X_STATUS,
16473 &val);
16474 tp->pci_fn = val & 0x7;
16475 }
4153577a
JP		 16476 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16477 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16478 tg3_asic_rev(tp) == ASIC_REV_5720) {
9dc5e342 16479 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
857001f0
MC		 16480 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16481 val = tr32(TG3_CPMU_STATUS);
16482
4153577a 16483 if (tg3_asic_rev(tp) == ASIC_REV_5717)
857001f0
MC		 16484 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16485 else
9dc5e342
MC		 16486 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16487 TG3_CPMU_STATUS_FSHFT_5719;
69f11c99
MC		 16488 }
16489
7e6c63f0
HM		 16490 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16491 tp->write32_tx_mbox = tg3_write_flush_reg32;
16492 tp->write32_rx_mbox = tg3_write_flush_reg32;
16493 }
16494
7d0c41ef 16495 /* Get eeprom hw config before calling tg3_set_power_state().
63c3a66f 16496 * In particular, the TG3_FLAG_IS_NIC flag must be
7d0c41ef
MC		 16497 * determined before calling tg3_set_power_state() so that
16498 * we know whether or not to switch out of Vaux power.
16499 * When the flag is set, it means that GPIO1 is used for eeprom
16500 * write protect and also implies that it is a LOM where GPIOs
16501 * are not used to switch power.
6aa20a22 16502 */
7d0c41ef
MC		 16503 tg3_get_eeprom_hw_cfg(tp);
16504
1caf13eb 16505 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
cf9ecf4b
MC		 16506 tg3_flag_clear(tp, TSO_CAPABLE);
16507 tg3_flag_clear(tp, TSO_BUG);
16508 tp->fw_needed = NULL;
16509 }
16510
63c3a66f 16511 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 16512 /* Allow reads and writes to the
16513 * APE register and memory space.
16514 */
16515 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 16516 PCISTATE_ALLOW_APE_SHMEM_WR |
16517 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 16518 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16519 pci_state_reg);
c9cab24e
MC		 16520
16521 tg3_ape_lock_init(tp);
0d3031d9
MC		 16522 }
16523
16821285
MC		 16524 /* Set up tp->grc_local_ctrl before calling
16525 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16526 * will bring 5700's external PHY out of reset.
314fba34
MC		 16527 * It is also used as eeprom write protect on LOMs.
16528 */
16529 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
4153577a 16530 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
63c3a66f 16531 tg3_flag(tp, EEPROM_WRITE_PROT))
314fba34
MC		 16532 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16533 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 16534 /* Unused GPIO3 must be driven as output on 5752 because there
16535 * are no pull-up resistors on unused GPIO pins.
16536 */
4153577a 16537 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc 16538 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 16539
4153577a
JP		 16540 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16541 tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 16542 tg3_flag(tp, 57765_CLASS))
af36e6b6
MC		 16543 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16544
8d519ab2
MC		 16545 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16546 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 16547 /* Turn off the debug UART. */
16548 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
63c3a66f 16549 if (tg3_flag(tp, IS_NIC))
5f0c4a3c
MC		 16550 /* Keep VMain power. */
16551 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16552 GRC_LCLCTRL_GPIO_OUTPUT0;
16553 }
16554
4153577a 16555 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c86a8560
MC		 16556 tp->grc_local_ctrl |=
16557 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16558
16821285
MC		 16559 /* Switch out of Vaux if it is a NIC */
16560 tg3_pwrsrc_switch_to_vmain(tp);
1da177e4 16561
1da177e4
LT		 16562 /* Derive initial jumbo mode from MTU assigned in
16563 * ether_setup() via the alloc_etherdev() call
16564 */
63c3a66f
JP		 16565 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16566 tg3_flag_set(tp, JUMBO_RING_ENABLE);
1da177e4
LT		 16567
16568 /* Determine WakeOnLan speed to use. */
4153577a
JP		 16569 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16570 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16571 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16572 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
63c3a66f 16573 tg3_flag_clear(tp, WOL_SPEED_100MB);
1da177e4 16574 } else {
63c3a66f 16575 tg3_flag_set(tp, WOL_SPEED_100MB);
1da177e4
LT		 16576 }
16577
4153577a 16578 if (tg3_asic_rev(tp) == ASIC_REV_5906)
f07e9af3 16579 tp->phy_flags |= TG3_PHYFLG_IS_FET;
7f97a4bd 16580
1da177e4 16581 /* A few boards don't want Ethernet@WireSpeed phy feature */
4153577a
JP		 16582 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16583 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16584 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16585 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
f07e9af3
MC		 16586 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16587 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16588 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
1da177e4 16589
4153577a
JP		 16590 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16591 tg3_chip_rev(tp) == CHIPREV_5704_AX)
f07e9af3 16592 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
4153577a 16593 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
f07e9af3 16594 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
1da177e4 16595
63c3a66f 16596 if (tg3_flag(tp, 5705_PLUS) &&
f07e9af3 16597 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a
JP		 16598 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16599 tg3_asic_rev(tp) != ASIC_REV_57780 &&
63c3a66f 16600 !tg3_flag(tp, 57765_PLUS)) {
4153577a
JP		 16601 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16602 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16603 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16604 tg3_asic_rev(tp) == ASIC_REV_5761) {
d4011ada
MC		 16605 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16606 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
f07e9af3 16607 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
c1d2a196 16608 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
f07e9af3 16609 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
321d32a0 16610 } else
f07e9af3 16611 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
c424cb24 16612 }
1da177e4 16613
4153577a
JP		 16614 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16615 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 16616 tp->phy_otp = tg3_read_otp_phycfg(tp);
16617 if (tp->phy_otp == 0)
16618 tp->phy_otp = TG3_OTP_DEFAULT;
16619 }
16620
63c3a66f 16621 if (tg3_flag(tp, CPMU_PRESENT))
8ef21428
MC		 16622 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16623 else
16624 tp->mi_mode = MAC_MI_MODE_BASE;
16625
1da177e4 16626 tp->coalesce_mode = 0;
4153577a
JP		 16627 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16628 tg3_chip_rev(tp) != CHIPREV_5700_BX)
1da177e4
LT		 16629 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16630
4d958473 16631 /* Set these bits to enable statistics workaround. */
4153577a 16632 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
94962f7f 16633 tg3_asic_rev(tp) == ASIC_REV_5762 ||
4153577a
JP		 16634 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16635 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
4d958473
MC		 16636 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16637 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16638 }
16639
4153577a
JP		 16640 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16641 tg3_asic_rev(tp) == ASIC_REV_57780)
63c3a66f 16642 tg3_flag_set(tp, USE_PHYLIB);
57e6983c 16643
158d7abd
MC		 16644 err = tg3_mdio_init(tp);
16645 if (err)
16646 return err;
1da177e4
LT		 16647
16648 /* Initialize data/descriptor byte/word swapping. */
16649 val = tr32(GRC_MODE);
4153577a
JP		 16650 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16651 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 16652 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16653 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16654 GRC_MODE_B2HRX_ENABLE |
16655 GRC_MODE_HTX2B_ENABLE |
16656 GRC_MODE_HOST_STACKUP);
16657 else
16658 val &= GRC_MODE_HOST_STACKUP;
16659
1da177e4
LT		 16660 tw32(GRC_MODE, val | tp->grc_mode);
16661
16662 tg3_switch_clocks(tp);
16663
16664 /* Clear this out for sanity. */
16665 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16666
388d3335
NG		 16667 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16668 tw32(TG3PCI_REG_BASE_ADDR, 0);
16669
1da177e4
LT		 16670 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16671 &pci_state_reg);
16672 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
63c3a66f 16673 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
4153577a
JP		 16674 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16675 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16676 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16677 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
1da177e4
LT		 16678 void __iomem *sram_base;
16679
16680 /* Write some dummy words into the SRAM status block
16681 * area, see if it reads back correctly. If the return
16682 * value is bad, force enable the PCIX workaround.
16683 */
16684 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16685
16686 writel(0x00000000, sram_base);
16687 writel(0x00000000, sram_base + 4);
16688 writel(0xffffffff, sram_base + 4);
16689 if (readl(sram_base) != 0x00000000)
63c3a66f 16690 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16691 }
16692 }
16693
16694 udelay(50);
16695 tg3_nvram_init(tp);
16696
c4dab506
NS		 16697 /* If the device has an NVRAM, no need to load patch firmware */
16698 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16699 !tg3_flag(tp, NO_NVRAM))
16700 tp->fw_needed = NULL;
16701
1da177e4
LT		 16702 grc_misc_cfg = tr32(GRC_MISC_CFG);
16703 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16704
4153577a 16705 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
1da177e4
LT		 16706 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16707 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
63c3a66f 16708 tg3_flag_set(tp, IS_5788);
1da177e4 16709
63c3a66f 16710 if (!tg3_flag(tp, IS_5788) &&
4153577a 16711 tg3_asic_rev(tp) != ASIC_REV_5700)
63c3a66f
JP		 16712 tg3_flag_set(tp, TAGGED_STATUS);
16713 if (tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 16714 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16715 HOSTCC_MODE_CLRTICK_TXBD);
16716
16717 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16718 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16719 tp->misc_host_ctrl);
16720 }
16721
3bda1258 16722 /* Preserve the APE MAC_MODE bits */
63c3a66f 16723 if (tg3_flag(tp, ENABLE_APE))
d2394e6b 16724 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
3bda1258 16725 else
6e01b20b 16726 tp->mac_mode = 0;
3bda1258 16727
3d567e0e 16728 if (tg3_10_100_only_device(tp, ent))
f07e9af3 16729 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
1da177e4
LT		 16730
16731 err = tg3_phy_probe(tp);
16732 if (err) {
2445e461 16733 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 16734 /* ... but do not return immediately ... */
b02fd9e3 16735 tg3_mdio_fini(tp);
1da177e4
LT		 16736 }
16737
184b8904 16738 tg3_read_vpd(tp);
c4e6575c 16739 tg3_read_fw_ver(tp);
1da177e4 16740
f07e9af3
MC		 16741 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16742 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16743 } else {
4153577a 16744 if (tg3_asic_rev(tp) == ASIC_REV_5700)
f07e9af3 16745 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16746 else
f07e9af3 16747 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4
LT		 16748 }
16749
16750 /* 5700 {AX,BX} chips have a broken status block link
16751 * change bit implementation, so we must use the
16752 * status register in those cases.
16753 */
4153577a 16754 if (tg3_asic_rev(tp) == ASIC_REV_5700)
63c3a66f 16755 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4 16756 else
63c3a66f 16757 tg3_flag_clear(tp, USE_LINKCHG_REG);
1da177e4
LT		 16758
16759 /* The led_ctrl is set during tg3_phy_probe, here we might
16760 * have to force the link status polling mechanism based
16761 * upon subsystem IDs.
16762 */
16763 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
4153577a 16764 tg3_asic_rev(tp) == ASIC_REV_5701 &&
f07e9af3
MC		 16765 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16766 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
63c3a66f 16767 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4
LT		 16768 }
16769
16770 /* For all SERDES we poll the MAC status register. */
f07e9af3 16771 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
63c3a66f 16772 tg3_flag_set(tp, POLL_SERDES);
1da177e4 16773 else
63c3a66f 16774 tg3_flag_clear(tp, POLL_SERDES);
1da177e4 16775
1743b83c
NS		 16776 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16777 tg3_flag_set(tp, POLL_CPMU_LINK);
16778
9205fd9c 16779 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
d2757fc4 16780 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
4153577a 16781 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
63c3a66f 16782 tg3_flag(tp, PCIX_MODE)) {
9205fd9c 16783 tp->rx_offset = NET_SKB_PAD;
d2757fc4 16784#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
9dc7a113 16785 tp->rx_copy_thresh = ~(u16)0;
d2757fc4
MC		 16786#endif
16787 }
1da177e4 16788
2c49a44d
MC		 16789 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16790 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
7cb32cf2
MC		 16791 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16792
2c49a44d 16793 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
f92905de
MC		 16794
16795 /* Increment the rx prod index on the rx std ring by at most
16796 * 8 for these chips to workaround hw errata.
16797 */
4153577a
JP		 16798 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16799 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16800 tg3_asic_rev(tp) == ASIC_REV_5755)
f92905de
MC		 16801 tp->rx_std_max_post = 8;
16802
63c3a66f 16803 if (tg3_flag(tp, ASPM_WORKAROUND))
8ed5d97e
MC		 16804 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16805 PCIE_PWR_MGMT_L1_THRESH_MSK;
16806
1da177e4
LT		 16807 return err;
16808}
16809
49b6e95f 16810#ifdef CONFIG_SPARC
229b1ad1 16811static int tg3_get_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16812{
16813 struct net_device *dev = tp->dev;
16814 struct pci_dev *pdev = tp->pdev;
49b6e95f 16815 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 16816 const unsigned char *addr;
49b6e95f
DM		 16817 int len;
16818
16819 addr = of_get_property(dp, "local-mac-address", &len);
d458cdf7
JP		 16820 if (addr && len == ETH_ALEN) {
16821 memcpy(dev->dev_addr, addr, ETH_ALEN);
49b6e95f 16822 return 0;
1da177e4
LT		 16823 }
16824 return -ENODEV;
16825}
16826
229b1ad1 16827static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16828{
16829 struct net_device *dev = tp->dev;
16830
d458cdf7 16831 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
1da177e4
LT		 16832 return 0;
16833}
16834#endif
16835
229b1ad1 16836static int tg3_get_device_address(struct tg3 *tp)
1da177e4
LT		 16837{
16838 struct net_device *dev = tp->dev;
16839 u32 hi, lo, mac_offset;
008652b3 16840 int addr_ok = 0;
7e6c63f0 16841 int err;
1da177e4 16842
49b6e95f 16843#ifdef CONFIG_SPARC
1da177e4
LT		 16844 if (!tg3_get_macaddr_sparc(tp))
16845 return 0;
16846#endif
16847
7e6c63f0
HM		 16848 if (tg3_flag(tp, IS_SSB_CORE)) {
16849 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16850 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16851 return 0;
16852 }
16853
1da177e4 16854 mac_offset = 0x7c;
4153577a 16855 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
63c3a66f 16856 tg3_flag(tp, 5780_CLASS)) {
1da177e4
LT		 16857 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16858 mac_offset = 0xcc;
16859 if (tg3_nvram_lock(tp))
16860 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16861 else
16862 tg3_nvram_unlock(tp);
63c3a66f 16863 } else if (tg3_flag(tp, 5717_PLUS)) {
69f11c99 16864 if (tp->pci_fn & 1)
a1b950d5 16865 mac_offset = 0xcc;
69f11c99 16866 if (tp->pci_fn > 1)
a50d0796 16867 mac_offset += 0x18c;
4153577a 16868 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 16869 mac_offset = 0x10;
1da177e4
LT		 16870
16871 /* First try to get it from MAC address mailbox. */
16872 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16873 if ((hi >> 16) == 0x484b) {
16874 dev->dev_addr[0] = (hi >> 8) & 0xff;
16875 dev->dev_addr[1] = (hi >> 0) & 0xff;
16876
16877 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16878 dev->dev_addr[2] = (lo >> 24) & 0xff;
16879 dev->dev_addr[3] = (lo >> 16) & 0xff;
16880 dev->dev_addr[4] = (lo >> 8) & 0xff;
16881 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 16882
008652b3
MC		 16883 /* Some old bootcode may report a 0 MAC address in SRAM */
16884 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16885 }
16886 if (!addr_ok) {
16887 /* Next, try NVRAM. */
63c3a66f 16888 if (!tg3_flag(tp, NO_NVRAM) &&
df259d8c 16889 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 16890 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 16891 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16892 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 16893 }
16894 /* Finally just fetch it out of the MAC control regs. */
16895 else {
16896 hi = tr32(MAC_ADDR_0_HIGH);
16897 lo = tr32(MAC_ADDR_0_LOW);
16898
16899 dev->dev_addr[5] = lo & 0xff;
16900 dev->dev_addr[4] = (lo >> 8) & 0xff;
16901 dev->dev_addr[3] = (lo >> 16) & 0xff;
16902 dev->dev_addr[2] = (lo >> 24) & 0xff;
16903 dev->dev_addr[1] = hi & 0xff;
16904 dev->dev_addr[0] = (hi >> 8) & 0xff;
16905 }
1da177e4
LT		 16906 }
16907
16908 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 16909#ifdef CONFIG_SPARC
1da177e4
LT		 16910 if (!tg3_get_default_macaddr_sparc(tp))
16911 return 0;
16912#endif
16913 return -EINVAL;
16914 }
16915 return 0;
16916}
16917
59e6b434
DM		 16918#define BOUNDARY_SINGLE_CACHELINE 1
16919#define BOUNDARY_MULTI_CACHELINE 2
16920
229b1ad1 16921static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
59e6b434
DM		 16922{
16923 int cacheline_size;
16924 u8 byte;
16925 int goal;
16926
16927 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
16928 if (byte == 0)
16929 cacheline_size = 1024;
16930 else
16931 cacheline_size = (int) byte * 4;
16932
16933 /* On 5703 and later chips, the boundary bits have no
16934 * effect.
16935 */
4153577a
JP		 16936 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16937 tg3_asic_rev(tp) != ASIC_REV_5701 &&
63c3a66f 16938 !tg3_flag(tp, PCI_EXPRESS))
59e6b434
DM		 16939 goto out;
16940
16941#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
16942 goal = BOUNDARY_MULTI_CACHELINE;
16943#else
16944#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
16945 goal = BOUNDARY_SINGLE_CACHELINE;
16946#else
16947 goal = 0;
16948#endif
16949#endif
16950
63c3a66f 16951 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 16952 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
16953 goto out;
16954 }
16955
59e6b434
DM		 16956 if (!goal)
16957 goto out;
16958
16959 /* PCI controllers on most RISC systems tend to disconnect
16960 * when a device tries to burst across a cache-line boundary.
16961 * Therefore, letting tg3 do so just wastes PCI bandwidth.
16962 *
16963 * Unfortunately, for PCI-E there are only limited
16964 * write-side controls for this, and thus for reads
16965 * we will still get the disconnects. We'll also waste
16966 * these PCI cycles for both read and write for chips
16967 * other than 5700 and 5701 which do not implement the
16968 * boundary bits.
16969 */
63c3a66f 16970 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16971 switch (cacheline_size) {
16972 case 16:
16973 case 32:
16974 case 64:
16975 case 128:
16976 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16977 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
16978 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
16979 } else {
16980 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16981 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16982 }
16983 break;
16984
16985 case 256:
16986 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
16987 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
16988 break;
16989
16990 default:
16991 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16992 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16993 break;
855e1111 16994 }
63c3a66f 16995 } else if (tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16996 switch (cacheline_size) {
16997 case 16:
16998 case 32:
16999 case 64:
17000 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17001 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17002 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17003 break;
17004 }
17005 /* fallthrough */
17006 case 128:
17007 default:
17008 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17009 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17010 break;
855e1111 17011 }
59e6b434
DM		 17012 } else {
17013 switch (cacheline_size) {
17014 case 16:
17015 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17016 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17017 DMA_RWCTRL_WRITE_BNDRY_16);
17018 break;
17019 }
17020 /* fallthrough */
17021 case 32:
17022 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17023 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17024 DMA_RWCTRL_WRITE_BNDRY_32);
17025 break;
17026 }
17027 /* fallthrough */
17028 case 64:
17029 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17030 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17031 DMA_RWCTRL_WRITE_BNDRY_64);
17032 break;
17033 }
17034 /* fallthrough */
17035 case 128:
17036 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17037 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17038 DMA_RWCTRL_WRITE_BNDRY_128);
17039 break;
17040 }
17041 /* fallthrough */
17042 case 256:
17043 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17044 DMA_RWCTRL_WRITE_BNDRY_256);
17045 break;
17046 case 512:
17047 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17048 DMA_RWCTRL_WRITE_BNDRY_512);
17049 break;
17050 case 1024:
17051 default:
17052 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17053 DMA_RWCTRL_WRITE_BNDRY_1024);
17054 break;
855e1111 17055 }
59e6b434
DM		 17056 }
17057
17058out:
17059 return val;
17060}
17061
229b1ad1 17062static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
953c96e0 17063 int size, bool to_device)
1da177e4
LT		 17064{
17065 struct tg3_internal_buffer_desc test_desc;
17066 u32 sram_dma_descs;
17067 int i, ret;
17068
17069 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17070
17071 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17072 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17073 tw32(RDMAC_STATUS, 0);
17074 tw32(WDMAC_STATUS, 0);
17075
17076 tw32(BUFMGR_MODE, 0);
17077 tw32(FTQ_RESET, 0);
17078
17079 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17080 test_desc.addr_lo = buf_dma & 0xffffffff;
17081 test_desc.nic_mbuf = 0x00002100;
17082 test_desc.len = size;
17083
17084 /*
17085 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17086 * the *second* time the tg3 driver was getting loaded after an
17087 * initial scan.
17088 *
17089 * Broadcom tells me:
17090 * ...the DMA engine is connected to the GRC block and a DMA
17091 * reset may affect the GRC block in some unpredictable way...
17092 * The behavior of resets to individual blocks has not been tested.
17093 *
17094 * Broadcom noted the GRC reset will also reset all sub-components.
17095 */
17096 if (to_device) {
17097 test_desc.cqid_sqid = (13 << 8) | 2;
17098
17099 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17100 udelay(40);
17101 } else {
17102 test_desc.cqid_sqid = (16 << 8) | 7;
17103
17104 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17105 udelay(40);
17106 }
17107 test_desc.flags = 0x00000005;
17108
17109 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17110 u32 val;
17111
17112 val = *(((u32 *)&test_desc) + i);
17113 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17114 sram_dma_descs + (i * sizeof(u32)));
17115 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17116 }
17117 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17118
859a5887 17119 if (to_device)
1da177e4 17120 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
859a5887 17121 else
1da177e4 17122 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
1da177e4
LT		 17123
17124 ret = -ENODEV;
17125 for (i = 0; i < 40; i++) {
17126 u32 val;
17127
17128 if (to_device)
17129 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17130 else
17131 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17132 if ((val & 0xffff) == sram_dma_descs) {
17133 ret = 0;
17134 break;
17135 }
17136
17137 udelay(100);
17138 }
17139
17140 return ret;
17141}
17142
ded7340d 17143#define TEST_BUFFER_SIZE 0x2000
1da177e4 17144
4143470c 17145static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
895950c2
JP		 17146 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17147 { },
17148};
17149
229b1ad1 17150static int tg3_test_dma(struct tg3 *tp)
1da177e4
LT		 17151{
17152 dma_addr_t buf_dma;
59e6b434 17153 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 17154 int ret = 0;
1da177e4 17155
4bae65c8
MC		 17156 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17157 &buf_dma, GFP_KERNEL);
1da177e4
LT		 17158 if (!buf) {
17159 ret = -ENOMEM;
17160 goto out_nofree;
17161 }
17162
17163 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17164 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17165
59e6b434 17166 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 17167
63c3a66f 17168 if (tg3_flag(tp, 57765_PLUS))
cbf9ca6c
MC		 17169 goto out;
17170
63c3a66f 17171 if (tg3_flag(tp, PCI_EXPRESS)) {
1da177e4
LT		 17172 /* DMA read watermark not used on PCIE */
17173 tp->dma_rwctrl |= 0x00180000;
63c3a66f 17174 } else if (!tg3_flag(tp, PCIX_MODE)) {
4153577a
JP		 17175 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17176 tg3_asic_rev(tp) == ASIC_REV_5750)
1da177e4
LT		 17177 tp->dma_rwctrl |= 0x003f0000;
17178 else
17179 tp->dma_rwctrl |= 0x003f000f;
17180 } else {
4153577a
JP		 17181 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17182 tg3_asic_rev(tp) == ASIC_REV_5704) {
1da177e4 17183 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 17184 u32 read_water = 0x7;
1da177e4 17185
4a29cc2e
MC		 17186 /* If the 5704 is behind the EPB bridge, we can
17187 * do the less restrictive ONE_DMA workaround for
17188 * better performance.
17189 */
63c3a66f 17190 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
4153577a 17191 tg3_asic_rev(tp) == ASIC_REV_5704)
4a29cc2e
MC		 17192 tp->dma_rwctrl |= 0x8000;
17193 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 17194 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17195
4153577a 17196 if (tg3_asic_rev(tp) == ASIC_REV_5703)
49afdeb6 17197 read_water = 4;
59e6b434 17198 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 17199 tp->dma_rwctrl |=
17200 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17201 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17202 (1 << 23);
4153577a 17203 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
4cf78e4f
MC		 17204 /* 5780 always in PCIX mode */
17205 tp->dma_rwctrl |= 0x00144000;
4153577a 17206 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
a4e2b347
MC		 17207 /* 5714 always in PCIX mode */
17208 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 17209 } else {
17210 tp->dma_rwctrl |= 0x001b000f;
17211 }
17212 }
7e6c63f0
HM		 17213 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17214 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
1da177e4 17215
4153577a
JP		 17216 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17217 tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 17218 tp->dma_rwctrl &= 0xfffffff0;
17219
4153577a
JP		 17220 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17221 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 17222 /* Remove this if it causes problems for some boards. */
17223 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17224
17225 /* On 5700/5701 chips, we need to set this bit.
17226 * Otherwise the chip will issue cacheline transactions
17227 * to streamable DMA memory with not all the byte
17228 * enables turned on. This is an error on several
17229 * RISC PCI controllers, in particular sparc64.
17230 *
17231 * On 5703/5704 chips, this bit has been reassigned
17232 * a different meaning. In particular, it is used
17233 * on those chips to enable a PCI-X workaround.
17234 */
17235 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17236 }
17237
17238 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17239
1da177e4 17240
4153577a
JP		 17241 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17242 tg3_asic_rev(tp) != ASIC_REV_5701)
1da177e4
LT		 17243 goto out;
17244
59e6b434
DM		 17245 /* It is best to perform DMA test with maximum write burst size
17246 * to expose the 5700/5701 write DMA bug.
17247 */
17248 saved_dma_rwctrl = tp->dma_rwctrl;
17249 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17250 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17251
1da177e4
LT		 17252 while (1) {
17253 u32 *p = buf, i;
17254
17255 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17256 p[i] = i;
17257
17258 /* Send the buffer to the chip. */
953c96e0 17259 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
1da177e4 17260 if (ret) {
2445e461
MC		 17261 dev_err(&tp->pdev->dev,
17262 "%s: Buffer write failed. err = %d\n",
17263 __func__, ret);
1da177e4
LT		 17264 break;
17265 }
17266
1da177e4 17267 /* Now read it back. */
953c96e0 17268 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
1da177e4 17269 if (ret) {
5129c3a3
MC		 17270 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17271 "err = %d\n", __func__, ret);
1da177e4
LT		 17272 break;
17273 }
17274
17275 /* Verify it. */
17276 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17277 if (p[i] == i)
17278 continue;
17279
59e6b434
DM		 17280 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17281 DMA_RWCTRL_WRITE_BNDRY_16) {
17282 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 17283 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17284 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17285 break;
17286 } else {
2445e461
MC		 17287 dev_err(&tp->pdev->dev,
17288 "%s: Buffer corrupted on read back! "
17289 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 17290 ret = -ENODEV;
17291 goto out;
17292 }
17293 }
17294
17295 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17296 /* Success. */
17297 ret = 0;
17298 break;
17299 }
17300 }
59e6b434
DM		 17301 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17302 DMA_RWCTRL_WRITE_BNDRY_16) {
17303 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 17304 * now look for chipsets that are known to expose the
17305 * DMA bug without failing the test.
59e6b434 17306 */
4143470c 17307 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
6d1cfbab
MC		 17308 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17309 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
859a5887 17310 } else {
6d1cfbab
MC		 17311 /* Safe to use the calculated DMA boundary. */
17312 tp->dma_rwctrl = saved_dma_rwctrl;
859a5887 17313 }
6d1cfbab 17314
59e6b434
DM		 17315 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17316 }
1da177e4
LT		 17317
17318out:
4bae65c8 17319 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
1da177e4
LT		 17320out_nofree:
17321 return ret;
17322}
17323
229b1ad1 17324static void tg3_init_bufmgr_config(struct tg3 *tp)
1da177e4 17325{
63c3a66f 17326 if (tg3_flag(tp, 57765_PLUS)) {
666bc831
MC		 17327 tp->bufmgr_config.mbuf_read_dma_low_water =
17328 DEFAULT_MB_RDMA_LOW_WATER_5705;
17329 tp->bufmgr_config.mbuf_mac_rx_low_water =
17330 DEFAULT_MB_MACRX_LOW_WATER_57765;
17331 tp->bufmgr_config.mbuf_high_water =
17332 DEFAULT_MB_HIGH_WATER_57765;
17333
17334 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17335 DEFAULT_MB_RDMA_LOW_WATER_5705;
17336 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17337 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17338 tp->bufmgr_config.mbuf_high_water_jumbo =
17339 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
63c3a66f 17340 } else if (tg3_flag(tp, 5705_PLUS)) {
fdfec172
MC		 17341 tp->bufmgr_config.mbuf_read_dma_low_water =
17342 DEFAULT_MB_RDMA_LOW_WATER_5705;
17343 tp->bufmgr_config.mbuf_mac_rx_low_water =
17344 DEFAULT_MB_MACRX_LOW_WATER_5705;
17345 tp->bufmgr_config.mbuf_high_water =
17346 DEFAULT_MB_HIGH_WATER_5705;
4153577a 17347 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 17348 tp->bufmgr_config.mbuf_mac_rx_low_water =
17349 DEFAULT_MB_MACRX_LOW_WATER_5906;
17350 tp->bufmgr_config.mbuf_high_water =
17351 DEFAULT_MB_HIGH_WATER_5906;
17352 }
fdfec172
MC		 17353
17354 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17355 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17356 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17357 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17358 tp->bufmgr_config.mbuf_high_water_jumbo =
17359 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17360 } else {
17361 tp->bufmgr_config.mbuf_read_dma_low_water =
17362 DEFAULT_MB_RDMA_LOW_WATER;
17363 tp->bufmgr_config.mbuf_mac_rx_low_water =
17364 DEFAULT_MB_MACRX_LOW_WATER;
17365 tp->bufmgr_config.mbuf_high_water =
17366 DEFAULT_MB_HIGH_WATER;
17367
17368 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17369 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17370 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17371 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17372 tp->bufmgr_config.mbuf_high_water_jumbo =
17373 DEFAULT_MB_HIGH_WATER_JUMBO;
17374 }
1da177e4
LT		 17375
17376 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17377 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17378}
17379
229b1ad1 17380static char *tg3_phy_string(struct tg3 *tp)
1da177e4 17381{
79eb6904
MC		 17382 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17383 case TG3_PHY_ID_BCM5400: return "5400";
17384 case TG3_PHY_ID_BCM5401: return "5401";
17385 case TG3_PHY_ID_BCM5411: return "5411";
17386 case TG3_PHY_ID_BCM5701: return "5701";
17387 case TG3_PHY_ID_BCM5703: return "5703";
17388 case TG3_PHY_ID_BCM5704: return "5704";
17389 case TG3_PHY_ID_BCM5705: return "5705";
17390 case TG3_PHY_ID_BCM5750: return "5750";
17391 case TG3_PHY_ID_BCM5752: return "5752";
17392 case TG3_PHY_ID_BCM5714: return "5714";
17393 case TG3_PHY_ID_BCM5780: return "5780";
17394 case TG3_PHY_ID_BCM5755: return "5755";
17395 case TG3_PHY_ID_BCM5787: return "5787";
17396 case TG3_PHY_ID_BCM5784: return "5784";
17397 case TG3_PHY_ID_BCM5756: return "5722/5756";
17398 case TG3_PHY_ID_BCM5906: return "5906";
17399 case TG3_PHY_ID_BCM5761: return "5761";
17400 case TG3_PHY_ID_BCM5718C: return "5718C";
17401 case TG3_PHY_ID_BCM5718S: return "5718S";
17402 case TG3_PHY_ID_BCM57765: return "57765";
302b500b 17403 case TG3_PHY_ID_BCM5719C: return "5719C";
6418f2c1 17404 case TG3_PHY_ID_BCM5720C: return "5720C";
c65a17f4 17405 case TG3_PHY_ID_BCM5762: return "5762C";
79eb6904 17406 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 17407 case 0: return "serdes";
17408 default: return "unknown";
855e1111 17409 }
1da177e4
LT		 17410}
17411
229b1ad1 17412static char *tg3_bus_string(struct tg3 *tp, char *str)
f9804ddb 17413{
63c3a66f 17414 if (tg3_flag(tp, PCI_EXPRESS)) {
f9804ddb
MC		 17415 strcpy(str, "PCI Express");
17416 return str;
63c3a66f 17417 } else if (tg3_flag(tp, PCIX_MODE)) {
f9804ddb
MC		 17418 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17419
17420 strcpy(str, "PCIX:");
17421
17422 if ((clock_ctrl == 7) ||
17423 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17424 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17425 strcat(str, "133MHz");
17426 else if (clock_ctrl == 0)
17427 strcat(str, "33MHz");
17428 else if (clock_ctrl == 2)
17429 strcat(str, "50MHz");
17430 else if (clock_ctrl == 4)
17431 strcat(str, "66MHz");
17432 else if (clock_ctrl == 6)
17433 strcat(str, "100MHz");
f9804ddb
MC		 17434 } else {
17435 strcpy(str, "PCI:");
63c3a66f 17436 if (tg3_flag(tp, PCI_HIGH_SPEED))
f9804ddb
MC		 17437 strcat(str, "66MHz");
17438 else
17439 strcat(str, "33MHz");
17440 }
63c3a66f 17441 if (tg3_flag(tp, PCI_32BIT))
f9804ddb
MC		 17442 strcat(str, ":32-bit");
17443 else
17444 strcat(str, ":64-bit");
17445 return str;
17446}
17447
229b1ad1 17448static void tg3_init_coal(struct tg3 *tp)
15f9850d
DM		 17449{
17450 struct ethtool_coalesce *ec = &tp->coal;
17451
17452 memset(ec, 0, sizeof(*ec));
17453 ec->cmd = ETHTOOL_GCOALESCE;
17454 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17455 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17456 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17457 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17458 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17459 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17460 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17461 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17462 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17463
17464 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17465 HOSTCC_MODE_CLRTICK_TXBD)) {
17466 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17467 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17468 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17469 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17470 }
d244c892 17471
63c3a66f 17472 if (tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 17473 ec->rx_coalesce_usecs_irq = 0;
17474 ec->tx_coalesce_usecs_irq = 0;
17475 ec->stats_block_coalesce_usecs = 0;
17476 }
15f9850d
DM		 17477}
17478
229b1ad1 17479static int tg3_init_one(struct pci_dev *pdev,
1da177e4
LT		 17480 const struct pci_device_id *ent)
17481{
1da177e4
LT		 17482 struct net_device *dev;
17483 struct tg3 *tp;
5865fc1b 17484 int i, err;
646c9edd 17485 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 17486 char str[40];
72f2afb8 17487 u64 dma_mask, persist_dma_mask;
c8f44aff 17488 netdev_features_t features = 0;
1da177e4 17489
05dbe005 17490 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 17491
17492 err = pci_enable_device(pdev);
17493 if (err) {
2445e461 17494 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 17495 return err;
17496 }
17497
1da177e4
LT		 17498 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17499 if (err) {
2445e461 17500 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 17501 goto err_out_disable_pdev;
17502 }
17503
17504 pci_set_master(pdev);
17505
fe5f5787 17506 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 17507 if (!dev) {
1da177e4 17508 err = -ENOMEM;
5865fc1b 17509 goto err_out_free_res;
1da177e4
LT		 17510 }
17511
1da177e4
LT		 17512 SET_NETDEV_DEV(dev, &pdev->dev);
17513
1da177e4
LT		 17514 tp = netdev_priv(dev);
17515 tp->pdev = pdev;
17516 tp->dev = dev;
1da177e4
LT		 17517 tp->rx_mode = TG3_DEF_RX_MODE;
17518 tp->tx_mode = TG3_DEF_TX_MODE;
9c13cb8b 17519 tp->irq_sync = 1;
8ef21428 17520
1da177e4
LT		 17521 if (tg3_debug > 0)
17522 tp->msg_enable = tg3_debug;
17523 else
17524 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17525
7e6c63f0
HM		 17526 if (pdev_is_ssb_gige_core(pdev)) {
17527 tg3_flag_set(tp, IS_SSB_CORE);
17528 if (ssb_gige_must_flush_posted_writes(pdev))
17529 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17530 if (ssb_gige_one_dma_at_once(pdev))
17531 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
ee002b64
HM		 17532 if (ssb_gige_have_roboswitch(pdev)) {
17533 tg3_flag_set(tp, USE_PHYLIB);
7e6c63f0 17534 tg3_flag_set(tp, ROBOSWITCH);
ee002b64 17535 }
7e6c63f0
HM		 17536 if (ssb_gige_is_rgmii(pdev))
17537 tg3_flag_set(tp, RGMII_MODE);
17538 }
17539
1da177e4
LT		 17540 /* The word/byte swap controls here control register access byte
17541 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17542 * setting below.
17543 */
17544 tp->misc_host_ctrl =
17545 MISC_HOST_CTRL_MASK_PCI_INT |
17546 MISC_HOST_CTRL_WORD_SWAP |
17547 MISC_HOST_CTRL_INDIR_ACCESS |
17548 MISC_HOST_CTRL_PCISTATE_RW;
17549
17550 /* The NONFRM (non-frame) byte/word swap controls take effect
17551 * on descriptor entries, anything which isn't packet data.
17552 *
17553 * The StrongARM chips on the board (one for tx, one for rx)
17554 * are running in big-endian mode.
17555 */
17556 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17557 GRC_MODE_WSWAP_NONFRM_DATA);
17558#ifdef __BIG_ENDIAN
17559 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17560#endif
17561 spin_lock_init(&tp->lock);
1da177e4 17562 spin_lock_init(&tp->indirect_lock);
c4028958 17563 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 17564
d5fe488a 17565 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 17566 if (!tp->regs) {
ab96b241 17567 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 17568 err = -ENOMEM;
17569 goto err_out_free_dev;
17570 }
17571
c9cab24e
MC		 17572 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17573 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17574 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17575 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17576 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 17577 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
c9cab24e
MC		 17578 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17579 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 17580 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 17581 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17582 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 17583 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17584 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 17585 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17586 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
c9cab24e
MC		 17587 tg3_flag_set(tp, ENABLE_APE);
17588 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17589 if (!tp->aperegs) {
17590 dev_err(&pdev->dev,
17591 "Cannot map APE registers, aborting\n");
17592 err = -ENOMEM;
17593 goto err_out_iounmap;
17594 }
17595 }
17596
1da177e4
LT		 17597 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17598 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 17599
1da177e4 17600 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 17601 dev->watchdog_timeo = TG3_TX_TIMEOUT;
2ffcc981 17602 dev->netdev_ops = &tg3_netdev_ops;
1da177e4 17603 dev->irq = pdev->irq;
1da177e4 17604
3d567e0e 17605 err = tg3_get_invariants(tp, ent);
1da177e4 17606 if (err) {
ab96b241
MC		 17607 dev_err(&pdev->dev,
17608 "Problem fetching invariants of chip, aborting\n");
c9cab24e 17609 goto err_out_apeunmap;
1da177e4
LT		 17610 }
17611
4a29cc2e
MC		 17612 /* The EPB bridge inside 5714, 5715, and 5780 and any
17613 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 17614 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17615 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17616 * do DMA address check in tg3_start_xmit().
17617 */
63c3a66f 17618 if (tg3_flag(tp, IS_5788))
284901a9 17619 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
63c3a66f 17620 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
50cf156a 17621 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 17622#ifdef CONFIG_HIGHMEM
6a35528a 17623 dma_mask = DMA_BIT_MASK(64);
72f2afb8 17624#endif
4a29cc2e 17625 } else
6a35528a 17626 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 17627
17628 /* Configure DMA attributes. */
284901a9 17629 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 17630 err = pci_set_dma_mask(pdev, dma_mask);
17631 if (!err) {
0da0606f 17632 features |= NETIF_F_HIGHDMA;
72f2afb8
MC		 17633 err = pci_set_consistent_dma_mask(pdev,
17634 persist_dma_mask);
17635 if (err < 0) {
ab96b241
MC		 17636 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17637 "DMA for consistent allocations\n");
c9cab24e 17638 goto err_out_apeunmap;
72f2afb8
MC		 17639 }
17640 }
17641 }
284901a9
YH		 17642 if (err || dma_mask == DMA_BIT_MASK(32)) {
17643 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 17644 if (err) {
ab96b241
MC		 17645 dev_err(&pdev->dev,
17646 "No usable DMA configuration, aborting\n");
c9cab24e 17647 goto err_out_apeunmap;
72f2afb8
MC		 17648 }
17649 }
17650
fdfec172 17651 tg3_init_bufmgr_config(tp);
1da177e4 17652
f646968f 17653 features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
0da0606f
MC		 17654
17655 /* 5700 B0 chips do not support checksumming correctly due
17656 * to hardware bugs.
17657 */
4153577a 17658 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
0da0606f
MC		 17659 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17660
17661 if (tg3_flag(tp, 5755_PLUS))
17662 features |= NETIF_F_IPV6_CSUM;
17663 }
17664
4e3a7aaa
MC		 17665 /* TSO is on by default on chips that support hardware TSO.
17666 * Firmware TSO on older chips gives lower performance, so it
17667 * is off by default, but can be enabled using ethtool.
17668 */
63c3a66f
JP		 17669 if ((tg3_flag(tp, HW_TSO_1) ||
17670 tg3_flag(tp, HW_TSO_2) ||
17671 tg3_flag(tp, HW_TSO_3)) &&
0da0606f
MC		 17672 (features & NETIF_F_IP_CSUM))
17673 features |= NETIF_F_TSO;
63c3a66f 17674 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
0da0606f
MC		 17675 if (features & NETIF_F_IPV6_CSUM)
17676 features |= NETIF_F_TSO6;
63c3a66f 17677 if (tg3_flag(tp, HW_TSO_3) ||
4153577a
JP		 17678 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17679 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17680 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17681 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17682 tg3_asic_rev(tp) == ASIC_REV_57780)
0da0606f 17683 features |= NETIF_F_TSO_ECN;
b0026624 17684 }
1da177e4 17685
d542fe27
MC		 17686 dev->features |= features;
17687 dev->vlan_features |= features;
17688
06c03c02
MB		 17689 /*
17690 * Add loopback capability only for a subset of devices that support
17691 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17692 * loopback for the remaining devices.
17693 */
4153577a 17694 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
06c03c02
MB		 17695 !tg3_flag(tp, CPMU_PRESENT))
17696 /* Add the loopback capability */
0da0606f
MC		 17697 features |= NETIF_F_LOOPBACK;
17698
0da0606f 17699 dev->hw_features |= features;
e565eec3 17700 dev->priv_flags |= IFF_UNICAST_FLT;
06c03c02 17701
4153577a 17702 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
63c3a66f 17703 !tg3_flag(tp, TSO_CAPABLE) &&
1da177e4 17704 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
63c3a66f 17705 tg3_flag_set(tp, MAX_RXPEND_64);
1da177e4
LT		 17706 tp->rx_pending = 63;
17707 }
17708
1da177e4
LT		 17709 err = tg3_get_device_address(tp);
17710 if (err) {
ab96b241
MC		 17711 dev_err(&pdev->dev,
17712 "Could not obtain valid ethernet address, aborting\n");
c9cab24e 17713 goto err_out_apeunmap;
c88864df
MC		 17714 }
17715
1da177e4
LT		 17716 /*
17717 * Reset chip in case UNDI or EFI driver did not shutdown
17718 * DMA self test will enable WDMAC and we'll see (spurious)
17719 * pending DMA on the PCI bus at that point.
17720 */
17721 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17722 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 17723 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 17724 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 17725 }
17726
17727 err = tg3_test_dma(tp);
17728 if (err) {
ab96b241 17729 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
c88864df 17730 goto err_out_apeunmap;
1da177e4
LT		 17731 }
17732
78f90dcf
MC		 17733 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17734 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17735 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6fd45cb8 17736 for (i = 0; i < tp->irq_max; i++) {
78f90dcf
MC		 17737 struct tg3_napi *tnapi = &tp->napi[i];
17738
17739 tnapi->tp = tp;
17740 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17741
17742 tnapi->int_mbox = intmbx;
93a700a9 17743 if (i <= 4)
78f90dcf
MC		 17744 intmbx += 0x8;
17745 else
17746 intmbx += 0x4;
17747
17748 tnapi->consmbox = rcvmbx;
17749 tnapi->prodmbox = sndmbx;
17750
66cfd1bd 17751 if (i)
78f90dcf 17752 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
66cfd1bd 17753 else
78f90dcf 17754 tnapi->coal_now = HOSTCC_MODE_NOW;
78f90dcf 17755
63c3a66f 17756 if (!tg3_flag(tp, SUPPORT_MSIX))
78f90dcf
MC		 17757 break;
17758
17759 /*
17760 * If we support MSIX, we'll be using RSS. If we're using
17761 * RSS, the first vector only handles link interrupts and the
17762 * remaining vectors handle rx and tx interrupts. Reuse the
17763 * mailbox values for the next iteration. The values we setup
17764 * above are still useful for the single vectored mode.
17765 */
17766 if (!i)
17767 continue;
17768
17769 rcvmbx += 0x8;
17770
17771 if (sndmbx & 0x4)
17772 sndmbx -= 0x4;
17773 else
17774 sndmbx += 0xc;
17775 }
17776
15f9850d
DM		 17777 tg3_init_coal(tp);
17778
c49a1561
MC		 17779 pci_set_drvdata(pdev, dev);
17780
4153577a
JP		 17781 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17782 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17783 tg3_asic_rev(tp) == ASIC_REV_5762)
fb4ce8ad
MC		 17784 tg3_flag_set(tp, PTP_CAPABLE);
17785
21f7638e
MC		 17786 tg3_timer_init(tp);
17787
402e1398
MC		 17788 tg3_carrier_off(tp);
17789
1da177e4
LT		 17790 err = register_netdev(dev);
17791 if (err) {
ab96b241 17792 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 17793 goto err_out_apeunmap;
1da177e4
LT		 17794 }
17795
05dbe005
JP		 17796 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17797 tp->board_part_number,
4153577a 17798 tg3_chip_rev_id(tp),
05dbe005
JP		 17799 tg3_bus_string(tp, str),
17800 dev->dev_addr);
1da177e4 17801
f07e9af3 17802 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7 17803 struct phy_device *phydev;
ead2402c 17804 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
5129c3a3
MC		 17805 netdev_info(dev,
17806 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
05dbe005 17807 phydev->drv->name, dev_name(&phydev->dev));
f07e9af3
MC		 17808 } else {
17809 char *ethtype;
17810
17811 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17812 ethtype = "10/100Base-TX";
17813 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17814 ethtype = "1000Base-SX";
17815 else
17816 ethtype = "10/100/1000Base-T";
17817
5129c3a3 17818 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
47007831
MC		 17819 "(WireSpeed[%d], EEE[%d])\n",
17820 tg3_phy_string(tp), ethtype,
17821 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17822 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
f07e9af3 17823 }
05dbe005
JP		 17824
17825 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
dc668910 17826 (dev->features & NETIF_F_RXCSUM) != 0,
63c3a66f 17827 tg3_flag(tp, USE_LINKCHG_REG) != 0,
f07e9af3 17828 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
63c3a66f
JP		 17829 tg3_flag(tp, ENABLE_ASF) != 0,
17830 tg3_flag(tp, TSO_CAPABLE) != 0);
05dbe005
JP		 17831 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17832 tp->dma_rwctrl,
17833 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17834 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4 17835
b45aa2f6
MC		 17836 pci_save_state(pdev);
17837
1da177e4
LT		 17838 return 0;
17839
0d3031d9
MC		 17840err_out_apeunmap:
17841 if (tp->aperegs) {
17842 iounmap(tp->aperegs);
17843 tp->aperegs = NULL;
17844 }
17845
1da177e4 17846err_out_iounmap:
6892914f
MC		 17847 if (tp->regs) {
17848 iounmap(tp->regs);
22abe310 17849 tp->regs = NULL;
6892914f 17850 }
1da177e4
LT		 17851
17852err_out_free_dev:
17853 free_netdev(dev);
17854
17855err_out_free_res:
17856 pci_release_regions(pdev);
17857
17858err_out_disable_pdev:
c80dc13d
GS		 17859 if (pci_is_enabled(pdev))
17860 pci_disable_device(pdev);
1da177e4
LT		 17861 return err;
17862}
17863
229b1ad1 17864static void tg3_remove_one(struct pci_dev *pdev)
1da177e4
LT		 17865{
17866 struct net_device *dev = pci_get_drvdata(pdev);
17867
17868 if (dev) {
17869 struct tg3 *tp = netdev_priv(dev);
17870
e3c5530b 17871 release_firmware(tp->fw);
077f849d 17872
db219973 17873 tg3_reset_task_cancel(tp);
158d7abd 17874
e730c823 17875 if (tg3_flag(tp, USE_PHYLIB)) {
b02fd9e3 17876 tg3_phy_fini(tp);
158d7abd 17877 tg3_mdio_fini(tp);
b02fd9e3 17878 }
158d7abd 17879
1da177e4 17880 unregister_netdev(dev);
0d3031d9
MC		 17881 if (tp->aperegs) {
17882 iounmap(tp->aperegs);
17883 tp->aperegs = NULL;
17884 }
6892914f
MC		 17885 if (tp->regs) {
17886 iounmap(tp->regs);
22abe310 17887 tp->regs = NULL;
6892914f 17888 }
1da177e4
LT		 17889 free_netdev(dev);
17890 pci_release_regions(pdev);
17891 pci_disable_device(pdev);
1da177e4
LT		 17892 }
17893}
17894
aa6027ca 17895#ifdef CONFIG_PM_SLEEP
c866b7ea 17896static int tg3_suspend(struct device *device)
1da177e4 17897{
c866b7ea 17898 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17899 struct net_device *dev = pci_get_drvdata(pdev);
17900 struct tg3 *tp = netdev_priv(dev);
8496e85c
RW		 17901 int err = 0;
17902
17903 rtnl_lock();
1da177e4
LT		 17904
17905 if (!netif_running(dev))
8496e85c 17906 goto unlock;
1da177e4 17907
db219973 17908 tg3_reset_task_cancel(tp);
b02fd9e3 17909 tg3_phy_stop(tp);
1da177e4
LT		 17910 tg3_netif_stop(tp);
17911
21f7638e 17912 tg3_timer_stop(tp);
1da177e4 17913
f47c11ee 17914 tg3_full_lock(tp, 1);
1da177e4 17915 tg3_disable_ints(tp);
f47c11ee 17916 tg3_full_unlock(tp);
1da177e4
LT		 17917
17918 netif_device_detach(dev);
17919
f47c11ee 17920 tg3_full_lock(tp, 0);
944d980e 17921 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
63c3a66f 17922 tg3_flag_clear(tp, INIT_COMPLETE);
f47c11ee 17923 tg3_full_unlock(tp);
1da177e4 17924
c866b7ea 17925 err = tg3_power_down_prepare(tp);
1da177e4 17926 if (err) {
b02fd9e3
MC		 17927 int err2;
17928
f47c11ee 17929 tg3_full_lock(tp, 0);
1da177e4 17930
63c3a66f 17931 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 17932 err2 = tg3_restart_hw(tp, true);
b02fd9e3 17933 if (err2)
b9ec6c1b 17934 goto out;
1da177e4 17935
21f7638e 17936 tg3_timer_start(tp);
1da177e4
LT		 17937
17938 netif_device_attach(dev);
17939 tg3_netif_start(tp);
17940
b9ec6c1b 17941out:
f47c11ee 17942 tg3_full_unlock(tp);
b02fd9e3
MC		 17943
17944 if (!err2)
17945 tg3_phy_start(tp);
1da177e4
LT		 17946 }
17947
8496e85c
RW		 17948unlock:
17949 rtnl_unlock();
1da177e4
LT		 17950 return err;
17951}
17952
c866b7ea 17953static int tg3_resume(struct device *device)
1da177e4 17954{
c866b7ea 17955 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17956 struct net_device *dev = pci_get_drvdata(pdev);
17957 struct tg3 *tp = netdev_priv(dev);
8496e85c
RW		 17958 int err = 0;
17959
17960 rtnl_lock();
1da177e4
LT		 17961
17962 if (!netif_running(dev))
8496e85c 17963 goto unlock;
1da177e4 17964
1da177e4
LT		 17965 netif_device_attach(dev);
17966
f47c11ee 17967 tg3_full_lock(tp, 0);
1da177e4 17968
2e460fc0
NS		 17969 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
17970
63c3a66f 17971 tg3_flag_set(tp, INIT_COMPLETE);
942d1af0
NS		 17972 err = tg3_restart_hw(tp,
17973 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
b9ec6c1b
MC		 17974 if (err)
17975 goto out;
1da177e4 17976
21f7638e 17977 tg3_timer_start(tp);
1da177e4 17978
1da177e4
LT		 17979 tg3_netif_start(tp);
17980
b9ec6c1b 17981out:
f47c11ee 17982 tg3_full_unlock(tp);
1da177e4 17983
b02fd9e3
MC		 17984 if (!err)
17985 tg3_phy_start(tp);
17986
8496e85c
RW		 17987unlock:
17988 rtnl_unlock();
b9ec6c1b 17989 return err;
1da177e4 17990}
42df36a6 17991#endif /* CONFIG_PM_SLEEP */
1da177e4 17992
c866b7ea
RW		 17993static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
17994
4c305fa2
NS		 17995static void tg3_shutdown(struct pci_dev *pdev)
17996{
17997 struct net_device *dev = pci_get_drvdata(pdev);
17998 struct tg3 *tp = netdev_priv(dev);
17999
18000 rtnl_lock();
18001 netif_device_detach(dev);
18002
18003 if (netif_running(dev))
18004 dev_close(dev);
18005
18006 if (system_state == SYSTEM_POWER_OFF)
18007 tg3_power_down(tp);
18008
18009 rtnl_unlock();
18010}
18011
b45aa2f6
MC		 18012/**
18013 * tg3_io_error_detected - called when PCI error is detected
18014 * @pdev: Pointer to PCI device
18015 * @state: The current pci connection state
18016 *
18017 * This function is called after a PCI bus error affecting
18018 * this device has been detected.
18019 */
18020static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18021 pci_channel_state_t state)
18022{
18023 struct net_device *netdev = pci_get_drvdata(pdev);
18024 struct tg3 *tp = netdev_priv(netdev);
18025 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18026
18027 netdev_info(netdev, "PCI I/O error detected\n");
18028
18029 rtnl_lock();
18030
d8af4dfd
GS		 18031 /* We probably don't have netdev yet */
18032 if (!netdev || !netif_running(netdev))
b45aa2f6
MC		 18033 goto done;
18034
18035 tg3_phy_stop(tp);
18036
18037 tg3_netif_stop(tp);
18038
21f7638e 18039 tg3_timer_stop(tp);
b45aa2f6
MC		 18040
18041 /* Want to make sure that the reset task doesn't run */
db219973 18042 tg3_reset_task_cancel(tp);
b45aa2f6
MC		 18043
18044 netif_device_detach(netdev);
18045
18046 /* Clean up software state, even if MMIO is blocked */
18047 tg3_full_lock(tp, 0);
18048 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18049 tg3_full_unlock(tp);
18050
18051done:
72bb72b0 18052 if (state == pci_channel_io_perm_failure) {
68293099
DB		 18053 if (netdev) {
18054 tg3_napi_enable(tp);
18055 dev_close(netdev);
18056 }
b45aa2f6 18057 err = PCI_ERS_RESULT_DISCONNECT;
72bb72b0 18058 } else {
b45aa2f6 18059 pci_disable_device(pdev);
72bb72b0 18060 }
b45aa2f6
MC		 18061
18062 rtnl_unlock();
18063
18064 return err;
18065}
18066
18067/**
18068 * tg3_io_slot_reset - called after the pci bus has been reset.
18069 * @pdev: Pointer to PCI device
18070 *
18071 * Restart the card from scratch, as if from a cold-boot.
18072 * At this point, the card has exprienced a hard reset,
18073 * followed by fixups by BIOS, and has its config space
18074 * set up identically to what it was at cold boot.
18075 */
18076static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18077{
18078 struct net_device *netdev = pci_get_drvdata(pdev);
18079 struct tg3 *tp = netdev_priv(netdev);
18080 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18081 int err;
18082
18083 rtnl_lock();
18084
18085 if (pci_enable_device(pdev)) {
68293099
DB		 18086 dev_err(&pdev->dev,
18087 "Cannot re-enable PCI device after reset.\n");
b45aa2f6
MC		 18088 goto done;
18089 }
18090
18091 pci_set_master(pdev);
18092 pci_restore_state(pdev);
18093 pci_save_state(pdev);
18094
68293099 18095 if (!netdev || !netif_running(netdev)) {
b45aa2f6
MC		 18096 rc = PCI_ERS_RESULT_RECOVERED;
18097 goto done;
18098 }
18099
18100 err = tg3_power_up(tp);
bed9829f 18101 if (err)
b45aa2f6 18102 goto done;
b45aa2f6
MC		 18103
18104 rc = PCI_ERS_RESULT_RECOVERED;
18105
18106done:
68293099 18107 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
72bb72b0
MC		 18108 tg3_napi_enable(tp);
18109 dev_close(netdev);
18110 }
b45aa2f6
MC		 18111 rtnl_unlock();
18112
18113 return rc;
18114}
18115
18116/**
18117 * tg3_io_resume - called when traffic can start flowing again.
18118 * @pdev: Pointer to PCI device
18119 *
18120 * This callback is called when the error recovery driver tells
18121 * us that its OK to resume normal operation.
18122 */
18123static void tg3_io_resume(struct pci_dev *pdev)
18124{
18125 struct net_device *netdev = pci_get_drvdata(pdev);
18126 struct tg3 *tp = netdev_priv(netdev);
18127 int err;
18128
18129 rtnl_lock();
18130
18131 if (!netif_running(netdev))
18132 goto done;
18133
18134 tg3_full_lock(tp, 0);
2e460fc0 18135 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
63c3a66f 18136 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 18137 err = tg3_restart_hw(tp, true);
b45aa2f6 18138 if (err) {
35763066 18139 tg3_full_unlock(tp);
b45aa2f6
MC		 18140 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18141 goto done;
18142 }
18143
18144 netif_device_attach(netdev);
18145
21f7638e 18146 tg3_timer_start(tp);
b45aa2f6
MC		 18147
18148 tg3_netif_start(tp);
18149
35763066
NNS		 18150 tg3_full_unlock(tp);
18151
b45aa2f6
MC		 18152 tg3_phy_start(tp);
18153
18154done:
18155 rtnl_unlock();
18156}
18157
3646f0e5 18158static const struct pci_error_handlers tg3_err_handler = {
b45aa2f6
MC		 18159 .error_detected = tg3_io_error_detected,
18160 .slot_reset = tg3_io_slot_reset,
18161 .resume = tg3_io_resume
18162};
18163
1da177e4
LT		 18164static struct pci_driver tg3_driver = {
18165 .name = DRV_MODULE_NAME,
18166 .id_table = tg3_pci_tbl,
18167 .probe = tg3_init_one,
229b1ad1 18168 .remove = tg3_remove_one,
b45aa2f6 18169 .err_handler = &tg3_err_handler,
42df36a6 18170 .driver.pm = &tg3_pm_ops,
4c305fa2 18171 .shutdown = tg3_shutdown,
1da177e4
LT		 18172};
18173
8dbb0dc2 18174module_pci_driver(tg3_driver);
Linux kernel - Deliverables
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