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tg3: Add unicast filtering support.
[deliverable/linux.git] / drivers / net / ethernet / broadcom / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
b681b65d 7 * Copyright (C) 2005-2013 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
6867c843 21#include <linux/stringify.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
14c85021 27#include <linux/in.h>
1da177e4 28#include <linux/init.h>
a6b7a407 29#include <linux/interrupt.h>
1da177e4
LT		 30#include <linux/ioport.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/ethtool.h>
3110f5f5 36#include <linux/mdio.h>
1da177e4 37#include <linux/mii.h>
158d7abd 38#include <linux/phy.h>
a9daf367 39#include <linux/brcmphy.h>
e565eec3 40#include <linux/if.h>
1da177e4
LT		 41#include <linux/if_vlan.h>
42#include <linux/ip.h>
43#include <linux/tcp.h>
44#include <linux/workqueue.h>
61487480 45#include <linux/prefetch.h>
f9a5f7d3 46#include <linux/dma-mapping.h>
077f849d 47#include <linux/firmware.h>
7e6c63f0 48#include <linux/ssb/ssb_driver_gige.h>
aed93e0b
MC		 49#include <linux/hwmon.h>
50#include <linux/hwmon-sysfs.h>
1da177e4
LT		 51
52#include <net/checksum.h>
c9bdd4b5 53#include <net/ip.h>
1da177e4 54
27fd9de8 55#include <linux/io.h>
1da177e4 56#include <asm/byteorder.h>
27fd9de8 57#include <linux/uaccess.h>
1da177e4 58
be947307
MC		 59#include <uapi/linux/net_tstamp.h>
60#include <linux/ptp_clock_kernel.h>
61
49b6e95f 62#ifdef CONFIG_SPARC
1da177e4 63#include <asm/idprom.h>
49b6e95f 64#include <asm/prom.h>
1da177e4
LT		 65#endif
66
63532394
MC		 67#define BAR_0 0
68#define BAR_2 2
69
1da177e4
LT		 70#include "tg3.h"
71
63c3a66f
JP		 72/* Functions & macros to verify TG3_FLAGS types */
73
74static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
75{
76 return test_bit(flag, bits);
77}
78
79static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
80{
81 set_bit(flag, bits);
82}
83
84static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
85{
86 clear_bit(flag, bits);
87}
88
89#define tg3_flag(tp, flag) \
90 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
91#define tg3_flag_set(tp, flag) \
92 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
93#define tg3_flag_clear(tp, flag) \
94 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
95
1da177e4 96#define DRV_MODULE_NAME "tg3"
6867c843 97#define TG3_MAJ_NUM 3
941c2253 98#define TG3_MIN_NUM 135
6867c843
MC		 99#define DRV_MODULE_VERSION \
100 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
941c2253 101#define DRV_MODULE_RELDATE "Nov 14, 2013"
1da177e4 102
fd6d3f0e
MC		 103#define RESET_KIND_SHUTDOWN 0
104#define RESET_KIND_INIT 1
105#define RESET_KIND_SUSPEND 2
106
1da177e4
LT		 107#define TG3_DEF_RX_MODE 0
108#define TG3_DEF_TX_MODE 0
109#define TG3_DEF_MSG_ENABLE \
110 (NETIF_MSG_DRV | \
111 NETIF_MSG_PROBE | \
112 NETIF_MSG_LINK | \
113 NETIF_MSG_TIMER | \
114 NETIF_MSG_IFDOWN | \
115 NETIF_MSG_IFUP | \
116 NETIF_MSG_RX_ERR | \
117 NETIF_MSG_TX_ERR)
118
520b2756
MC		 119#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
120
1da177e4
LT		 121/* length of time before we decide the hardware is borked,
122 * and dev->tx_timeout() should be called to fix the problem
123 */
63c3a66f 124
1da177e4
LT		 125#define TG3_TX_TIMEOUT (5 * HZ)
126
127/* hardware minimum and maximum for a single frame's data payload */
128#define TG3_MIN_MTU 60
129#define TG3_MAX_MTU(tp) \
63c3a66f 130 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 131
132/* These numbers seem to be hard coded in the NIC firmware somehow.
133 * You can't change the ring sizes, but you can change where you place
134 * them in the NIC onboard memory.
135 */
7cb32cf2 136#define TG3_RX_STD_RING_SIZE(tp) \
63c3a66f 137 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 138 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
1da177e4 139#define TG3_DEF_RX_RING_PENDING 200
7cb32cf2 140#define TG3_RX_JMB_RING_SIZE(tp) \
63c3a66f 141 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 142 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
1da177e4
LT		 143#define TG3_DEF_RX_JUMBO_RING_PENDING 100
144
145/* Do not place this n-ring entries value into the tp struct itself,
146 * we really want to expose these constants to GCC so that modulo et
147 * al. operations are done with shifts and masks instead of with
148 * hw multiply/modulo instructions. Another solution would be to
149 * replace things like '% foo' with '& (foo - 1)'.
150 */
1da177e4
LT		 151
152#define TG3_TX_RING_SIZE 512
153#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
154
2c49a44d
MC		 155#define TG3_RX_STD_RING_BYTES(tp) \
156 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
157#define TG3_RX_JMB_RING_BYTES(tp) \
158 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
159#define TG3_RX_RCB_RING_BYTES(tp) \
7cb32cf2 160 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
1da177e4
LT		 161#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
162 TG3_TX_RING_SIZE)
1da177e4
LT		 163#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
164
287be12e
MC		 165#define TG3_DMA_BYTE_ENAB 64
166
167#define TG3_RX_STD_DMA_SZ 1536
168#define TG3_RX_JMB_DMA_SZ 9046
169
170#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
171
172#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
173#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 174
2c49a44d
MC		 175#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
176 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
2b2cdb65 177
2c49a44d
MC		 178#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
179 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
2b2cdb65 180
d2757fc4
MC		 181/* Due to a hardware bug, the 5701 can only DMA to memory addresses
182 * that are at least dword aligned when used in PCIX mode. The driver
183 * works around this bug by double copying the packet. This workaround
184 * is built into the normal double copy length check for efficiency.
185 *
186 * However, the double copy is only necessary on those architectures
187 * where unaligned memory accesses are inefficient. For those architectures
188 * where unaligned memory accesses incur little penalty, we can reintegrate
189 * the 5701 in the normal rx path. Doing so saves a device structure
190 * dereference by hardcoding the double copy threshold in place.
191 */
192#define TG3_RX_COPY_THRESHOLD 256
193#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
194 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
195#else
196 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
197#endif
198
81389f57
MC		 199#if (NET_IP_ALIGN != 0)
200#define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
201#else
9205fd9c 202#define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
81389f57
MC		 203#endif
204
1da177e4 205/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 206#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
55086ad9 207#define TG3_TX_BD_DMA_MAX_2K 2048
a4cb428d 208#define TG3_TX_BD_DMA_MAX_4K 4096
1da177e4 209
ad829268
MC		 210#define TG3_RAW_IP_ALIGN 2
211
e565eec3
MC		 212#define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
213#define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
214
c6cdf436 215#define TG3_FW_UPDATE_TIMEOUT_SEC 5
21f7638e 216#define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
c6cdf436 217
077f849d 218#define FIRMWARE_TG3 "tigon/tg3.bin"
c4dab506 219#define FIRMWARE_TG357766 "tigon/tg357766.bin"
077f849d
JSR		 220#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
221#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
222
229b1ad1 223static char version[] =
05dbe005 224 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 225
226MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
227MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
228MODULE_LICENSE("GPL");
229MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 230MODULE_FIRMWARE(FIRMWARE_TG3);
231MODULE_FIRMWARE(FIRMWARE_TG3TSO);
232MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
233
1da177e4
LT		 234static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
235module_param(tg3_debug, int, 0);
236MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
237
3d567e0e
NNS		 238#define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
239#define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
240
a3aa1884 241static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
3d567e0e
NNS		 260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
261 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
262 TG3_DRV_DATA_FLAG_5705_10_100},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
264 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
265 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
3d567e0e
NNS		 267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
268 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
269 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
7e6c63f0 272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
13185217 273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
13185217 274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
3d567e0e
NNS		 275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
276 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
3d567e0e
NNS		 281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
282 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
3d567e0e
NNS		 290 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
291 PCI_VENDOR_ID_LENOVO,
292 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
293 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217 294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
3d567e0e
NNS		 295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
296 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
314 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
3d567e0e
NNS		 315 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
316 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
317 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
318 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
319 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
320 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321d32a0
MC		 321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
3d567e0e
NNS		 323 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
324 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
5e7ccf20 325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6 326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
79d49695 327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
5001e2f6 328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
b0f75221
MC		 329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
3d567e0e
NNS		 333 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
334 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
335 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
336 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
302b500b 337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
ba1f3c76 338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
02eca3f5 339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
d3f677af 340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
c86a8560
MC		 341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
68273712
NS		 344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
348 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
13185217
HK		 349 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
350 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
353 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
354 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
355 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
1dcb14d9 356 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
13185217 357 {}
1da177e4
LT		 358};
359
360MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
361
50da859d 362static const struct {
1da177e4 363 const char string[ETH_GSTRING_LEN];
48fa55a0 364} ethtool_stats_keys[] = {
1da177e4
LT		 365 { "rx_octets" },
366 { "rx_fragments" },
367 { "rx_ucast_packets" },
368 { "rx_mcast_packets" },
369 { "rx_bcast_packets" },
370 { "rx_fcs_errors" },
371 { "rx_align_errors" },
372 { "rx_xon_pause_rcvd" },
373 { "rx_xoff_pause_rcvd" },
374 { "rx_mac_ctrl_rcvd" },
375 { "rx_xoff_entered" },
376 { "rx_frame_too_long_errors" },
377 { "rx_jabbers" },
378 { "rx_undersize_packets" },
379 { "rx_in_length_errors" },
380 { "rx_out_length_errors" },
381 { "rx_64_or_less_octet_packets" },
382 { "rx_65_to_127_octet_packets" },
383 { "rx_128_to_255_octet_packets" },
384 { "rx_256_to_511_octet_packets" },
385 { "rx_512_to_1023_octet_packets" },
386 { "rx_1024_to_1522_octet_packets" },
387 { "rx_1523_to_2047_octet_packets" },
388 { "rx_2048_to_4095_octet_packets" },
389 { "rx_4096_to_8191_octet_packets" },
390 { "rx_8192_to_9022_octet_packets" },
391
392 { "tx_octets" },
393 { "tx_collisions" },
394
395 { "tx_xon_sent" },
396 { "tx_xoff_sent" },
397 { "tx_flow_control" },
398 { "tx_mac_errors" },
399 { "tx_single_collisions" },
400 { "tx_mult_collisions" },
401 { "tx_deferred" },
402 { "tx_excessive_collisions" },
403 { "tx_late_collisions" },
404 { "tx_collide_2times" },
405 { "tx_collide_3times" },
406 { "tx_collide_4times" },
407 { "tx_collide_5times" },
408 { "tx_collide_6times" },
409 { "tx_collide_7times" },
410 { "tx_collide_8times" },
411 { "tx_collide_9times" },
412 { "tx_collide_10times" },
413 { "tx_collide_11times" },
414 { "tx_collide_12times" },
415 { "tx_collide_13times" },
416 { "tx_collide_14times" },
417 { "tx_collide_15times" },
418 { "tx_ucast_packets" },
419 { "tx_mcast_packets" },
420 { "tx_bcast_packets" },
421 { "tx_carrier_sense_errors" },
422 { "tx_discards" },
423 { "tx_errors" },
424
425 { "dma_writeq_full" },
426 { "dma_write_prioq_full" },
427 { "rxbds_empty" },
428 { "rx_discards" },
429 { "rx_errors" },
430 { "rx_threshold_hit" },
431
432 { "dma_readq_full" },
433 { "dma_read_prioq_full" },
434 { "tx_comp_queue_full" },
435
436 { "ring_set_send_prod_index" },
437 { "ring_status_update" },
438 { "nic_irqs" },
439 { "nic_avoided_irqs" },
4452d099
MC		 440 { "nic_tx_threshold_hit" },
441
442 { "mbuf_lwm_thresh_hit" },
1da177e4
LT		 443};
444
48fa55a0 445#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
93df8b8f
NNS		 446#define TG3_NVRAM_TEST 0
447#define TG3_LINK_TEST 1
448#define TG3_REGISTER_TEST 2
449#define TG3_MEMORY_TEST 3
450#define TG3_MAC_LOOPB_TEST 4
451#define TG3_PHY_LOOPB_TEST 5
452#define TG3_EXT_LOOPB_TEST 6
453#define TG3_INTERRUPT_TEST 7
48fa55a0
MC		 454
455
50da859d 456static const struct {
4cafd3f5 457 const char string[ETH_GSTRING_LEN];
48fa55a0 458} ethtool_test_keys[] = {
93df8b8f
NNS		 459 [TG3_NVRAM_TEST] = { "nvram test (online) " },
460 [TG3_LINK_TEST] = { "link test (online) " },
461 [TG3_REGISTER_TEST] = { "register test (offline)" },
462 [TG3_MEMORY_TEST] = { "memory test (offline)" },
463 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
464 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
465 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
466 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
4cafd3f5
MC		 467};
468
48fa55a0
MC		 469#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
470
471
b401e9e2
MC		 472static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
473{
474 writel(val, tp->regs + off);
475}
476
477static u32 tg3_read32(struct tg3 *tp, u32 off)
478{
de6f31eb 479 return readl(tp->regs + off);
b401e9e2
MC		 480}
481
0d3031d9
MC		 482static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
483{
484 writel(val, tp->aperegs + off);
485}
486
487static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
488{
de6f31eb 489 return readl(tp->aperegs + off);
0d3031d9
MC		 490}
491
1da177e4
LT		 492static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
493{
6892914f
MC		 494 unsigned long flags;
495
496 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 497 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
498 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 499 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 500}
501
502static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
503{
504 writel(val, tp->regs + off);
505 readl(tp->regs + off);
1da177e4
LT		 506}
507
6892914f 508static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 509{
6892914f
MC		 510 unsigned long flags;
511 u32 val;
512
513 spin_lock_irqsave(&tp->indirect_lock, flags);
514 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
515 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
516 spin_unlock_irqrestore(&tp->indirect_lock, flags);
517 return val;
518}
519
520static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
521{
522 unsigned long flags;
523
524 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
525 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
526 TG3_64BIT_REG_LOW, val);
527 return;
528 }
66711e66 529 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 530 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
531 TG3_64BIT_REG_LOW, val);
532 return;
1da177e4 533 }
6892914f
MC		 534
535 spin_lock_irqsave(&tp->indirect_lock, flags);
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
537 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
538 spin_unlock_irqrestore(&tp->indirect_lock, flags);
539
540 /* In indirect mode when disabling interrupts, we also need
541 * to clear the interrupt bit in the GRC local ctrl register.
542 */
543 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
544 (val == 0x1)) {
545 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
546 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
547 }
548}
549
550static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
551{
552 unsigned long flags;
553 u32 val;
554
555 spin_lock_irqsave(&tp->indirect_lock, flags);
556 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
557 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
558 spin_unlock_irqrestore(&tp->indirect_lock, flags);
559 return val;
560}
561
b401e9e2
MC		 562/* usec_wait specifies the wait time in usec when writing to certain registers
563 * where it is unsafe to read back the register without some delay.
564 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
565 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
566 */
567static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 568{
63c3a66f 569 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
b401e9e2
MC		 570 /* Non-posted methods */
571 tp->write32(tp, off, val);
572 else {
573 /* Posted method */
574 tg3_write32(tp, off, val);
575 if (usec_wait)
576 udelay(usec_wait);
577 tp->read32(tp, off);
578 }
579 /* Wait again after the read for the posted method to guarantee that
580 * the wait time is met.
581 */
582 if (usec_wait)
583 udelay(usec_wait);
1da177e4
LT		 584}
585
09ee929c
MC		 586static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
587{
588 tp->write32_mbox(tp, off, val);
7e6c63f0
HM		 589 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
590 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
591 !tg3_flag(tp, ICH_WORKAROUND)))
6892914f 592 tp->read32_mbox(tp, off);
09ee929c
MC		 593}
594
20094930 595static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 596{
597 void __iomem *mbox = tp->regs + off;
598 writel(val, mbox);
63c3a66f 599 if (tg3_flag(tp, TXD_MBOX_HWBUG))
1da177e4 600 writel(val, mbox);
7e6c63f0
HM		 601 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
602 tg3_flag(tp, FLUSH_POSTED_WRITES))
1da177e4
LT		 603 readl(mbox);
604}
605
b5d3772c
MC		 606static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
607{
de6f31eb 608 return readl(tp->regs + off + GRCMBOX_BASE);
b5d3772c
MC		 609}
610
611static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
612{
613 writel(val, tp->regs + off + GRCMBOX_BASE);
614}
615
c6cdf436 616#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 617#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
c6cdf436
MC		 618#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
619#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
620#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930 621
c6cdf436
MC		 622#define tw32(reg, val) tp->write32(tp, reg, val)
623#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
624#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
625#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 626
627static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
628{
6892914f
MC		 629 unsigned long flags;
630
4153577a 631 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 632 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
633 return;
634
6892914f 635 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 636 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
638 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 639
bbadf503
MC		 640 /* Always leave this as zero. */
641 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
642 } else {
643 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
644 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 645
bbadf503
MC		 646 /* Always leave this as zero. */
647 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
648 }
649 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 650}
651
1da177e4
LT		 652static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
653{
6892914f
MC		 654 unsigned long flags;
655
4153577a 656 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 657 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
658 *val = 0;
659 return;
660 }
661
6892914f 662 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 663 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 664 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
665 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 666
bbadf503
MC		 667 /* Always leave this as zero. */
668 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
669 } else {
670 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
671 *val = tr32(TG3PCI_MEM_WIN_DATA);
672
673 /* Always leave this as zero. */
674 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
675 }
6892914f 676 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 677}
678
0d3031d9
MC		 679static void tg3_ape_lock_init(struct tg3 *tp)
680{
681 int i;
6f5c8f83 682 u32 regbase, bit;
f92d9dc1 683
4153577a 684 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 685 regbase = TG3_APE_LOCK_GRANT;
686 else
687 regbase = TG3_APE_PER_LOCK_GRANT;
0d3031d9
MC		 688
689 /* Make sure the driver hasn't any stale locks. */
78f94dc7
MC		 690 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
691 switch (i) {
692 case TG3_APE_LOCK_PHY0:
693 case TG3_APE_LOCK_PHY1:
694 case TG3_APE_LOCK_PHY2:
695 case TG3_APE_LOCK_PHY3:
696 bit = APE_LOCK_GRANT_DRIVER;
697 break;
698 default:
699 if (!tp->pci_fn)
700 bit = APE_LOCK_GRANT_DRIVER;
701 else
702 bit = 1 << tp->pci_fn;
703 }
704 tg3_ape_write32(tp, regbase + 4 * i, bit);
6f5c8f83
MC		 705 }
706
0d3031d9
MC		 707}
708
709static int tg3_ape_lock(struct tg3 *tp, int locknum)
710{
711 int i, off;
712 int ret = 0;
6f5c8f83 713 u32 status, req, gnt, bit;
0d3031d9 714
63c3a66f 715 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 716 return 0;
717
718 switch (locknum) {
6f5c8f83 719 case TG3_APE_LOCK_GPIO:
4153577a 720 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 721 return 0;
33f401ae
MC		 722 case TG3_APE_LOCK_GRC:
723 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 724 if (!tp->pci_fn)
725 bit = APE_LOCK_REQ_DRIVER;
726 else
727 bit = 1 << tp->pci_fn;
33f401ae 728 break;
8151ad57
MC		 729 case TG3_APE_LOCK_PHY0:
730 case TG3_APE_LOCK_PHY1:
731 case TG3_APE_LOCK_PHY2:
732 case TG3_APE_LOCK_PHY3:
733 bit = APE_LOCK_REQ_DRIVER;
734 break;
33f401ae
MC		 735 default:
736 return -EINVAL;
0d3031d9
MC		 737 }
738
4153577a 739 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
f92d9dc1
MC		 740 req = TG3_APE_LOCK_REQ;
741 gnt = TG3_APE_LOCK_GRANT;
742 } else {
743 req = TG3_APE_PER_LOCK_REQ;
744 gnt = TG3_APE_PER_LOCK_GRANT;
745 }
746
0d3031d9
MC		 747 off = 4 * locknum;
748
6f5c8f83 749 tg3_ape_write32(tp, req + off, bit);
0d3031d9
MC		 750
751 /* Wait for up to 1 millisecond to acquire lock. */
752 for (i = 0; i < 100; i++) {
f92d9dc1 753 status = tg3_ape_read32(tp, gnt + off);
6f5c8f83 754 if (status == bit)
0d3031d9 755 break;
6d446ec3
GS		 756 if (pci_channel_offline(tp->pdev))
757 break;
758
0d3031d9
MC		 759 udelay(10);
760 }
761
6f5c8f83 762 if (status != bit) {
0d3031d9 763 /* Revoke the lock request. */
6f5c8f83 764 tg3_ape_write32(tp, gnt + off, bit);
0d3031d9
MC		 765 ret = -EBUSY;
766 }
767
768 return ret;
769}
770
771static void tg3_ape_unlock(struct tg3 *tp, int locknum)
772{
6f5c8f83 773 u32 gnt, bit;
0d3031d9 774
63c3a66f 775 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 776 return;
777
778 switch (locknum) {
6f5c8f83 779 case TG3_APE_LOCK_GPIO:
4153577a 780 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 781 return;
33f401ae
MC		 782 case TG3_APE_LOCK_GRC:
783 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 784 if (!tp->pci_fn)
785 bit = APE_LOCK_GRANT_DRIVER;
786 else
787 bit = 1 << tp->pci_fn;
33f401ae 788 break;
8151ad57
MC		 789 case TG3_APE_LOCK_PHY0:
790 case TG3_APE_LOCK_PHY1:
791 case TG3_APE_LOCK_PHY2:
792 case TG3_APE_LOCK_PHY3:
793 bit = APE_LOCK_GRANT_DRIVER;
794 break;
33f401ae
MC		 795 default:
796 return;
0d3031d9
MC		 797 }
798
4153577a 799 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 800 gnt = TG3_APE_LOCK_GRANT;
801 else
802 gnt = TG3_APE_PER_LOCK_GRANT;
803
6f5c8f83 804 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
0d3031d9
MC		 805}
806
b65a372b 807static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
fd6d3f0e 808{
fd6d3f0e
MC		 809 u32 apedata;
810
b65a372b
MC		 811 while (timeout_us) {
812 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
813 return -EBUSY;
814
815 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
816 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
817 break;
818
819 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
820
821 udelay(10);
822 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
823 }
824
825 return timeout_us ? 0 : -EBUSY;
826}
827
cf8d55ae
MC		 828static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
829{
830 u32 i, apedata;
831
832 for (i = 0; i < timeout_us / 10; i++) {
833 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
834
835 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
836 break;
837
838 udelay(10);
839 }
840
841 return i == timeout_us / 10;
842}
843
86449944
MC		 844static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
845 u32 len)
cf8d55ae
MC		 846{
847 int err;
848 u32 i, bufoff, msgoff, maxlen, apedata;
849
850 if (!tg3_flag(tp, APE_HAS_NCSI))
851 return 0;
852
853 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
854 if (apedata != APE_SEG_SIG_MAGIC)
855 return -ENODEV;
856
857 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
858 if (!(apedata & APE_FW_STATUS_READY))
859 return -EAGAIN;
860
861 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
862 TG3_APE_SHMEM_BASE;
863 msgoff = bufoff + 2 * sizeof(u32);
864 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
865
866 while (len) {
867 u32 length;
868
869 /* Cap xfer sizes to scratchpad limits. */
870 length = (len > maxlen) ? maxlen : len;
871 len -= length;
872
873 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
874 if (!(apedata & APE_FW_STATUS_READY))
875 return -EAGAIN;
876
877 /* Wait for up to 1 msec for APE to service previous event. */
878 err = tg3_ape_event_lock(tp, 1000);
879 if (err)
880 return err;
881
882 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
883 APE_EVENT_STATUS_SCRTCHPD_READ |
884 APE_EVENT_STATUS_EVENT_PENDING;
885 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
886
887 tg3_ape_write32(tp, bufoff, base_off);
888 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
889
890 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
891 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
892
893 base_off += length;
894
895 if (tg3_ape_wait_for_event(tp, 30000))
896 return -EAGAIN;
897
898 for (i = 0; length; i += 4, length -= 4) {
899 u32 val = tg3_ape_read32(tp, msgoff + i);
900 memcpy(data, &val, sizeof(u32));
901 data++;
902 }
903 }
904
905 return 0;
906}
907
b65a372b
MC		 908static int tg3_ape_send_event(struct tg3 *tp, u32 event)
909{
910 int err;
911 u32 apedata;
fd6d3f0e
MC		 912
913 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
914 if (apedata != APE_SEG_SIG_MAGIC)
b65a372b 915 return -EAGAIN;
fd6d3f0e
MC		 916
917 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
918 if (!(apedata & APE_FW_STATUS_READY))
b65a372b 919 return -EAGAIN;
fd6d3f0e
MC		 920
921 /* Wait for up to 1 millisecond for APE to service previous event. */
b65a372b
MC		 922 err = tg3_ape_event_lock(tp, 1000);
923 if (err)
924 return err;
fd6d3f0e 925
b65a372b
MC		 926 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
927 event | APE_EVENT_STATUS_EVENT_PENDING);
fd6d3f0e 928
b65a372b
MC		 929 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
930 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
fd6d3f0e 931
b65a372b 932 return 0;
fd6d3f0e
MC		 933}
934
935static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
936{
937 u32 event;
938 u32 apedata;
939
940 if (!tg3_flag(tp, ENABLE_APE))
941 return;
942
943 switch (kind) {
944 case RESET_KIND_INIT:
945 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
946 APE_HOST_SEG_SIG_MAGIC);
947 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
948 APE_HOST_SEG_LEN_MAGIC);
949 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
950 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
951 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
952 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
953 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
954 APE_HOST_BEHAV_NO_PHYLOCK);
955 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
956 TG3_APE_HOST_DRVR_STATE_START);
957
958 event = APE_EVENT_STATUS_STATE_START;
959 break;
960 case RESET_KIND_SHUTDOWN:
961 /* With the interface we are currently using,
962 * APE does not track driver state. Wiping
963 * out the HOST SEGMENT SIGNATURE forces
964 * the APE to assume OS absent status.
965 */
966 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
967
968 if (device_may_wakeup(&tp->pdev->dev) &&
969 tg3_flag(tp, WOL_ENABLE)) {
970 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
971 TG3_APE_HOST_WOL_SPEED_AUTO);
972 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
973 } else
974 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
975
976 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
977
978 event = APE_EVENT_STATUS_STATE_UNLOAD;
979 break;
fd6d3f0e
MC		 980 default:
981 return;
982 }
983
984 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
985
986 tg3_ape_send_event(tp, event);
987}
988
1da177e4
LT		 989static void tg3_disable_ints(struct tg3 *tp)
990{
89aeb3bc
MC		 991 int i;
992
1da177e4
LT		 993 tw32(TG3PCI_MISC_HOST_CTRL,
994 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 995 for (i = 0; i < tp->irq_max; i++)
996 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 997}
998
1da177e4
LT		 999static void tg3_enable_ints(struct tg3 *tp)
1000{
89aeb3bc 1001 int i;
89aeb3bc 1002
bbe832c0
MC		 1003 tp->irq_sync = 0;
1004 wmb();
1005
1da177e4
LT		 1006 tw32(TG3PCI_MISC_HOST_CTRL,
1007 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 1008
f89f38b8 1009 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 1010 for (i = 0; i < tp->irq_cnt; i++) {
1011 struct tg3_napi *tnapi = &tp->napi[i];
c6cdf436 1012
898a56f8 1013 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
63c3a66f 1014 if (tg3_flag(tp, 1SHOT_MSI))
89aeb3bc 1015 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 1016
f89f38b8 1017 tp->coal_now |= tnapi->coal_now;
89aeb3bc 1018 }
f19af9c2
MC		 1019
1020 /* Force an initial interrupt */
63c3a66f 1021 if (!tg3_flag(tp, TAGGED_STATUS) &&
f19af9c2
MC		 1022 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1023 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1024 else
f89f38b8
MC		 1025 tw32(HOSTCC_MODE, tp->coal_now);
1026
1027 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 1028}
1029
17375d25 1030static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 1031{
17375d25 1032 struct tg3 *tp = tnapi->tp;
898a56f8 1033 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 1034 unsigned int work_exists = 0;
1035
1036 /* check for phy events */
63c3a66f 1037 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
04237ddd
MC		 1038 if (sblk->status & SD_STATUS_LINK_CHG)
1039 work_exists = 1;
1040 }
f891ea16
MC		 1041
1042 /* check for TX work to do */
1043 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1044 work_exists = 1;
1045
1046 /* check for RX work to do */
1047 if (tnapi->rx_rcb_prod_idx &&
8d9d7cfc 1048 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 1049 work_exists = 1;
1050
1051 return work_exists;
1052}
1053
17375d25 1054/* tg3_int_reenable
04237ddd
MC		 1055 * similar to tg3_enable_ints, but it accurately determines whether there
1056 * is new work pending and can return without flushing the PIO write
6aa20a22 1057 * which reenables interrupts
1da177e4 1058 */
17375d25 1059static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 1060{
17375d25
MC		 1061 struct tg3 *tp = tnapi->tp;
1062
898a56f8 1063 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 1064 mmiowb();
1065
fac9b83e
DM		 1066 /* When doing tagged status, this work check is unnecessary.
1067 * The last_tag we write above tells the chip which piece of
1068 * work we've completed.
1069 */
63c3a66f 1070 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
04237ddd 1071 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 1072 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 1073}
1074
1da177e4
LT		 1075static void tg3_switch_clocks(struct tg3 *tp)
1076{
f6eb9b1f 1077 u32 clock_ctrl;
1da177e4
LT		 1078 u32 orig_clock_ctrl;
1079
63c3a66f 1080 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
4cf78e4f
MC		 1081 return;
1082
f6eb9b1f
MC		 1083 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1084
1da177e4
LT		 1085 orig_clock_ctrl = clock_ctrl;
1086 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1087 CLOCK_CTRL_CLKRUN_OENABLE |
1088 0x1f);
1089 tp->pci_clock_ctrl = clock_ctrl;
1090
63c3a66f 1091 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4 1092 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 1093 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1094 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 1095 }
1096 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 1097 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1098 clock_ctrl |
1099 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1100 40);
1101 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1102 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1103 40);
1da177e4 1104 }
b401e9e2 1105 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 1106}
1107
1108#define PHY_BUSY_LOOPS 5000
1109
5c358045
HM		 1110static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1111 u32 *val)
1da177e4
LT		 1112{
1113 u32 frame_val;
1114 unsigned int loops;
1115 int ret;
1116
1117 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1118 tw32_f(MAC_MI_MODE,
1119 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1120 udelay(80);
1121 }
1122
8151ad57
MC		 1123 tg3_ape_lock(tp, tp->phy_ape_lock);
1124
1da177e4
LT		 1125 *val = 0x0;
1126
5c358045 1127 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1128 MI_COM_PHY_ADDR_MASK);
1129 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1130 MI_COM_REG_ADDR_MASK);
1131 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 1132
1da177e4
LT		 1133 tw32_f(MAC_MI_COM, frame_val);
1134
1135 loops = PHY_BUSY_LOOPS;
1136 while (loops != 0) {
1137 udelay(10);
1138 frame_val = tr32(MAC_MI_COM);
1139
1140 if ((frame_val & MI_COM_BUSY) == 0) {
1141 udelay(5);
1142 frame_val = tr32(MAC_MI_COM);
1143 break;
1144 }
1145 loops -= 1;
1146 }
1147
1148 ret = -EBUSY;
1149 if (loops != 0) {
1150 *val = frame_val & MI_COM_DATA_MASK;
1151 ret = 0;
1152 }
1153
1154 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1155 tw32_f(MAC_MI_MODE, tp->mi_mode);
1156 udelay(80);
1157 }
1158
8151ad57
MC		 1159 tg3_ape_unlock(tp, tp->phy_ape_lock);
1160
1da177e4
LT		 1161 return ret;
1162}
1163
5c358045
HM		 1164static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1165{
1166 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1167}
1168
1169static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1170 u32 val)
1da177e4
LT		 1171{
1172 u32 frame_val;
1173 unsigned int loops;
1174 int ret;
1175
f07e9af3 1176 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
221c5637 1177 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
b5d3772c
MC		 1178 return 0;
1179
1da177e4
LT		 1180 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1181 tw32_f(MAC_MI_MODE,
1182 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1183 udelay(80);
1184 }
1185
8151ad57
MC		 1186 tg3_ape_lock(tp, tp->phy_ape_lock);
1187
5c358045 1188 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1189 MI_COM_PHY_ADDR_MASK);
1190 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1191 MI_COM_REG_ADDR_MASK);
1192 frame_val |= (val & MI_COM_DATA_MASK);
1193 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 1194
1da177e4
LT		 1195 tw32_f(MAC_MI_COM, frame_val);
1196
1197 loops = PHY_BUSY_LOOPS;
1198 while (loops != 0) {
1199 udelay(10);
1200 frame_val = tr32(MAC_MI_COM);
1201 if ((frame_val & MI_COM_BUSY) == 0) {
1202 udelay(5);
1203 frame_val = tr32(MAC_MI_COM);
1204 break;
1205 }
1206 loops -= 1;
1207 }
1208
1209 ret = -EBUSY;
1210 if (loops != 0)
1211 ret = 0;
1212
1213 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1214 tw32_f(MAC_MI_MODE, tp->mi_mode);
1215 udelay(80);
1216 }
1217
8151ad57
MC		 1218 tg3_ape_unlock(tp, tp->phy_ape_lock);
1219
1da177e4
LT		 1220 return ret;
1221}
1222
5c358045
HM		 1223static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1224{
1225 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1226}
1227
b0988c15
MC		 1228static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1229{
1230 int err;
1231
1232 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1233 if (err)
1234 goto done;
1235
1236 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1237 if (err)
1238 goto done;
1239
1240 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1241 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1242 if (err)
1243 goto done;
1244
1245 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1246
1247done:
1248 return err;
1249}
1250
1251static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1252{
1253 int err;
1254
1255 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1256 if (err)
1257 goto done;
1258
1259 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1260 if (err)
1261 goto done;
1262
1263 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1264 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1265 if (err)
1266 goto done;
1267
1268 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1269
1270done:
1271 return err;
1272}
1273
1274static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1275{
1276 int err;
1277
1278 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1279 if (!err)
1280 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1281
1282 return err;
1283}
1284
1285static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1286{
1287 int err;
1288
1289 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1290 if (!err)
1291 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1292
1293 return err;
1294}
1295
15ee95c3
MC		 1296static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1297{
1298 int err;
1299
1300 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1301 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1302 MII_TG3_AUXCTL_SHDWSEL_MISC);
1303 if (!err)
1304 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1305
1306 return err;
1307}
1308
b4bd2929
MC		 1309static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1310{
1311 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1312 set |= MII_TG3_AUXCTL_MISC_WREN;
1313
1314 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1315}
1316
daf3ec68
NNS		 1317static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1318{
1319 u32 val;
1320 int err;
1d36ba45 1321
daf3ec68 1322 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1d36ba45 1323
daf3ec68
NNS		 1324 if (err)
1325 return err;
daf3ec68 1326
7c10ee32 1327 if (enable)
daf3ec68
NNS		 1328 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1329 else
1330 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1331
1332 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1333 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1334
1335 return err;
1336}
1d36ba45 1337
3ab71071
NS		 1338static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1339{
1340 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1341 reg | val | MII_TG3_MISC_SHDW_WREN);
1342}
1343
95e2869a
MC		 1344static int tg3_bmcr_reset(struct tg3 *tp)
1345{
1346 u32 phy_control;
1347 int limit, err;
1348
1349 /* OK, reset it, and poll the BMCR_RESET bit until it
1350 * clears or we time out.
1351 */
1352 phy_control = BMCR_RESET;
1353 err = tg3_writephy(tp, MII_BMCR, phy_control);
1354 if (err != 0)
1355 return -EBUSY;
1356
1357 limit = 5000;
1358 while (limit--) {
1359 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1360 if (err != 0)
1361 return -EBUSY;
1362
1363 if ((phy_control & BMCR_RESET) == 0) {
1364 udelay(40);
1365 break;
1366 }
1367 udelay(10);
1368 }
d4675b52 1369 if (limit < 0)
95e2869a
MC		 1370 return -EBUSY;
1371
1372 return 0;
1373}
1374
158d7abd
MC		 1375static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1376{
3d16543d 1377 struct tg3 *tp = bp->priv;
158d7abd
MC		 1378 u32 val;
1379
24bb4fb6 1380 spin_lock_bh(&tp->lock);
158d7abd 1381
ead2402c 1382 if (__tg3_readphy(tp, mii_id, reg, &val))
24bb4fb6
MC		 1383 val = -EIO;
1384
1385 spin_unlock_bh(&tp->lock);
158d7abd
MC		 1386
1387 return val;
1388}
1389
1390static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1391{
3d16543d 1392 struct tg3 *tp = bp->priv;
24bb4fb6 1393 u32 ret = 0;
158d7abd 1394
24bb4fb6 1395 spin_lock_bh(&tp->lock);
158d7abd 1396
ead2402c 1397 if (__tg3_writephy(tp, mii_id, reg, val))
24bb4fb6 1398 ret = -EIO;
158d7abd 1399
24bb4fb6
MC		 1400 spin_unlock_bh(&tp->lock);
1401
1402 return ret;
158d7abd
MC		 1403}
1404
1405static int tg3_mdio_reset(struct mii_bus *bp)
1406{
1407 return 0;
1408}
1409
9c61d6bc 1410static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 1411{
1412 u32 val;
fcb389df 1413 struct phy_device *phydev;
a9daf367 1414
ead2402c 1415 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
fcb389df 1416 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 1417 case PHY_ID_BCM50610:
1418 case PHY_ID_BCM50610M:
fcb389df
MC		 1419 val = MAC_PHYCFG2_50610_LED_MODES;
1420 break;
6a443a0f 1421 case PHY_ID_BCMAC131:
fcb389df
MC		 1422 val = MAC_PHYCFG2_AC131_LED_MODES;
1423 break;
6a443a0f 1424 case PHY_ID_RTL8211C:
fcb389df
MC		 1425 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1426 break;
6a443a0f 1427 case PHY_ID_RTL8201E:
fcb389df
MC		 1428 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1429 break;
1430 default:
a9daf367 1431 return;
fcb389df
MC		 1432 }
1433
1434 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1435 tw32(MAC_PHYCFG2, val);
1436
1437 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 1438 val &= ~(MAC_PHYCFG1_RGMII_INT |
1439 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1440 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 1441 tw32(MAC_PHYCFG1, val);
1442
1443 return;
1444 }
1445
63c3a66f 1446 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
fcb389df
MC		 1447 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1448 MAC_PHYCFG2_FMODE_MASK_MASK |
1449 MAC_PHYCFG2_GMODE_MASK_MASK |
1450 MAC_PHYCFG2_ACT_MASK_MASK |
1451 MAC_PHYCFG2_QUAL_MASK_MASK |
1452 MAC_PHYCFG2_INBAND_ENABLE;
1453
1454 tw32(MAC_PHYCFG2, val);
a9daf367 1455
bb85fbb6
MC		 1456 val = tr32(MAC_PHYCFG1);
1457 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1458 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
63c3a66f
JP		 1459 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1460 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1461 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
63c3a66f 1462 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1463 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1464 }
bb85fbb6
MC		 1465 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1466 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1467 tw32(MAC_PHYCFG1, val);
a9daf367 1468
a9daf367
MC		 1469 val = tr32(MAC_EXT_RGMII_MODE);
1470 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1471 MAC_RGMII_MODE_RX_QUALITY |
1472 MAC_RGMII_MODE_RX_ACTIVITY |
1473 MAC_RGMII_MODE_RX_ENG_DET |
1474 MAC_RGMII_MODE_TX_ENABLE |
1475 MAC_RGMII_MODE_TX_LOWPWR |
1476 MAC_RGMII_MODE_TX_RESET);
63c3a66f
JP		 1477 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1478 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367
MC		 1479 val |= MAC_RGMII_MODE_RX_INT_B |
1480 MAC_RGMII_MODE_RX_QUALITY |
1481 MAC_RGMII_MODE_RX_ACTIVITY |
1482 MAC_RGMII_MODE_RX_ENG_DET;
63c3a66f 1483 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1484 val |= MAC_RGMII_MODE_TX_ENABLE |
1485 MAC_RGMII_MODE_TX_LOWPWR |
1486 MAC_RGMII_MODE_TX_RESET;
1487 }
1488 tw32(MAC_EXT_RGMII_MODE, val);
1489}
1490
158d7abd
MC		 1491static void tg3_mdio_start(struct tg3 *tp)
1492{
158d7abd
MC		 1493 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1494 tw32_f(MAC_MI_MODE, tp->mi_mode);
1495 udelay(80);
a9daf367 1496
63c3a66f 1497 if (tg3_flag(tp, MDIOBUS_INITED) &&
4153577a 1498 tg3_asic_rev(tp) == ASIC_REV_5785)
9ea4818d
MC		 1499 tg3_mdio_config_5785(tp);
1500}
1501
1502static int tg3_mdio_init(struct tg3 *tp)
1503{
1504 int i;
1505 u32 reg;
1506 struct phy_device *phydev;
1507
63c3a66f 1508 if (tg3_flag(tp, 5717_PLUS)) {
9c7df915 1509 u32 is_serdes;
882e9793 1510
69f11c99 1511 tp->phy_addr = tp->pci_fn + 1;
882e9793 1512
4153577a 1513 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
d1ec96af
MC		 1514 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1515 else
1516 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1517 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1518 if (is_serdes)
1519 tp->phy_addr += 7;
ee002b64
HM		 1520 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1521 int addr;
1522
1523 addr = ssb_gige_get_phyaddr(tp->pdev);
1524 if (addr < 0)
1525 return addr;
1526 tp->phy_addr = addr;
882e9793 1527 } else
3f0e3ad7 1528 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1529
158d7abd
MC		 1530 tg3_mdio_start(tp);
1531
63c3a66f 1532 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
158d7abd
MC		 1533 return 0;
1534
298cf9be
LB		 1535 tp->mdio_bus = mdiobus_alloc();
1536 if (tp->mdio_bus == NULL)
1537 return -ENOMEM;
158d7abd 1538
298cf9be
LB		 1539 tp->mdio_bus->name = "tg3 mdio bus";
1540 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1541 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1542 tp->mdio_bus->priv = tp;
1543 tp->mdio_bus->parent = &tp->pdev->dev;
1544 tp->mdio_bus->read = &tg3_mdio_read;
1545 tp->mdio_bus->write = &tg3_mdio_write;
1546 tp->mdio_bus->reset = &tg3_mdio_reset;
ead2402c 1547 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
298cf9be 1548 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1549
1550 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1551 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1552
1553 /* The bus registration will look for all the PHYs on the mdio bus.
1554 * Unfortunately, it does not ensure the PHY is powered up before
1555 * accessing the PHY ID registers. A chip reset is the
1556 * quickest way to bring the device back to an operational state..
1557 */
1558 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1559 tg3_bmcr_reset(tp);
1560
298cf9be 1561 i = mdiobus_register(tp->mdio_bus);
a9daf367 1562 if (i) {
ab96b241 1563 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1564 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1565 return i;
1566 }
158d7abd 1567
ead2402c 1568 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
a9daf367 1569
9c61d6bc 1570 if (!phydev || !phydev->drv) {
ab96b241 1571 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1572 mdiobus_unregister(tp->mdio_bus);
1573 mdiobus_free(tp->mdio_bus);
1574 return -ENODEV;
1575 }
1576
1577 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1578 case PHY_ID_BCM57780:
321d32a0 1579 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1580 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1581 break;
6a443a0f
MC		 1582 case PHY_ID_BCM50610:
1583 case PHY_ID_BCM50610M:
32e5a8d6 1584 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1585 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1586 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1587 PHY_BRCM_AUTO_PWRDWN_ENABLE;
63c3a66f 1588 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
a9daf367 1589 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
63c3a66f 1590 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1591 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
63c3a66f 1592 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367 1593 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1594 /* fallthru */
6a443a0f 1595 case PHY_ID_RTL8211C:
fcb389df 1596 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1597 break;
6a443a0f
MC		 1598 case PHY_ID_RTL8201E:
1599 case PHY_ID_BCMAC131:
a9daf367 1600 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1601 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
f07e9af3 1602 tp->phy_flags |= TG3_PHYFLG_IS_FET;
a9daf367
MC		 1603 break;
1604 }
1605
63c3a66f 1606 tg3_flag_set(tp, MDIOBUS_INITED);
9c61d6bc 1607
4153577a 1608 if (tg3_asic_rev(tp) == ASIC_REV_5785)
9c61d6bc 1609 tg3_mdio_config_5785(tp);
a9daf367
MC		 1610
1611 return 0;
158d7abd
MC		 1612}
1613
1614static void tg3_mdio_fini(struct tg3 *tp)
1615{
63c3a66f
JP		 1616 if (tg3_flag(tp, MDIOBUS_INITED)) {
1617 tg3_flag_clear(tp, MDIOBUS_INITED);
298cf9be
LB		 1618 mdiobus_unregister(tp->mdio_bus);
1619 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1620 }
1621}
1622
4ba526ce
MC		 1623/* tp->lock is held. */
1624static inline void tg3_generate_fw_event(struct tg3 *tp)
1625{
1626 u32 val;
1627
1628 val = tr32(GRC_RX_CPU_EVENT);
1629 val |= GRC_RX_CPU_DRIVER_EVENT;
1630 tw32_f(GRC_RX_CPU_EVENT, val);
1631
1632 tp->last_event_jiffies = jiffies;
1633}
1634
1635#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1636
95e2869a
MC		 1637/* tp->lock is held. */
1638static void tg3_wait_for_event_ack(struct tg3 *tp)
1639{
1640 int i;
4ba526ce
MC		 1641 unsigned int delay_cnt;
1642 long time_remain;
1643
1644 /* If enough time has passed, no wait is necessary. */
1645 time_remain = (long)(tp->last_event_jiffies + 1 +
1646 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1647 (long)jiffies;
1648 if (time_remain < 0)
1649 return;
1650
1651 /* Check if we can shorten the wait time. */
1652 delay_cnt = jiffies_to_usecs(time_remain);
1653 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1654 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1655 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1656
4ba526ce 1657 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1658 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1659 break;
6d446ec3
GS		 1660 if (pci_channel_offline(tp->pdev))
1661 break;
1662
4ba526ce 1663 udelay(8);
95e2869a
MC		 1664 }
1665}
1666
1667/* tp->lock is held. */
b28f389d 1668static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
95e2869a 1669{
b28f389d 1670 u32 reg, val;
95e2869a
MC		 1671
1672 val = 0;
1673 if (!tg3_readphy(tp, MII_BMCR, &reg))
1674 val = reg << 16;
1675 if (!tg3_readphy(tp, MII_BMSR, &reg))
1676 val |= (reg & 0xffff);
b28f389d 1677 *data++ = val;
95e2869a
MC		 1678
1679 val = 0;
1680 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1681 val = reg << 16;
1682 if (!tg3_readphy(tp, MII_LPA, &reg))
1683 val |= (reg & 0xffff);
b28f389d 1684 *data++ = val;
95e2869a
MC		 1685
1686 val = 0;
f07e9af3 1687 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
95e2869a
MC		 1688 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1689 val = reg << 16;
1690 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1691 val |= (reg & 0xffff);
1692 }
b28f389d 1693 *data++ = val;
95e2869a
MC		 1694
1695 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1696 val = reg << 16;
1697 else
1698 val = 0;
b28f389d
MC		 1699 *data++ = val;
1700}
1701
1702/* tp->lock is held. */
1703static void tg3_ump_link_report(struct tg3 *tp)
1704{
1705 u32 data[4];
1706
1707 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1708 return;
1709
1710 tg3_phy_gather_ump_data(tp, data);
1711
1712 tg3_wait_for_event_ack(tp);
1713
1714 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1715 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1716 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1717 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1718 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1719 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
95e2869a 1720
4ba526ce 1721 tg3_generate_fw_event(tp);
95e2869a
MC		 1722}
1723
8d5a89b3
MC		 1724/* tp->lock is held. */
1725static void tg3_stop_fw(struct tg3 *tp)
1726{
1727 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1728 /* Wait for RX cpu to ACK the previous event. */
1729 tg3_wait_for_event_ack(tp);
1730
1731 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1732
1733 tg3_generate_fw_event(tp);
1734
1735 /* Wait for RX cpu to ACK this event. */
1736 tg3_wait_for_event_ack(tp);
1737 }
1738}
1739
fd6d3f0e
MC		 1740/* tp->lock is held. */
1741static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1742{
1743 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1744 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1745
1746 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1747 switch (kind) {
1748 case RESET_KIND_INIT:
1749 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1750 DRV_STATE_START);
1751 break;
1752
1753 case RESET_KIND_SHUTDOWN:
1754 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1755 DRV_STATE_UNLOAD);
1756 break;
1757
1758 case RESET_KIND_SUSPEND:
1759 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1760 DRV_STATE_SUSPEND);
1761 break;
1762
1763 default:
1764 break;
1765 }
1766 }
fd6d3f0e
MC		 1767}
1768
1769/* tp->lock is held. */
1770static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1771{
1772 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1773 switch (kind) {
1774 case RESET_KIND_INIT:
1775 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1776 DRV_STATE_START_DONE);
1777 break;
1778
1779 case RESET_KIND_SHUTDOWN:
1780 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1781 DRV_STATE_UNLOAD_DONE);
1782 break;
1783
1784 default:
1785 break;
1786 }
1787 }
fd6d3f0e
MC		 1788}
1789
1790/* tp->lock is held. */
1791static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1792{
1793 if (tg3_flag(tp, ENABLE_ASF)) {
1794 switch (kind) {
1795 case RESET_KIND_INIT:
1796 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1797 DRV_STATE_START);
1798 break;
1799
1800 case RESET_KIND_SHUTDOWN:
1801 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1802 DRV_STATE_UNLOAD);
1803 break;
1804
1805 case RESET_KIND_SUSPEND:
1806 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1807 DRV_STATE_SUSPEND);
1808 break;
1809
1810 default:
1811 break;
1812 }
1813 }
1814}
1815
1816static int tg3_poll_fw(struct tg3 *tp)
1817{
1818 int i;
1819 u32 val;
1820
df465abf
NS		 1821 if (tg3_flag(tp, NO_FWARE_REPORTED))
1822 return 0;
1823
7e6c63f0
HM		 1824 if (tg3_flag(tp, IS_SSB_CORE)) {
1825 /* We don't use firmware. */
1826 return 0;
1827 }
1828
4153577a 1829 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
fd6d3f0e
MC		 1830 /* Wait up to 20ms for init done. */
1831 for (i = 0; i < 200; i++) {
1832 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1833 return 0;
6d446ec3
GS		 1834 if (pci_channel_offline(tp->pdev))
1835 return -ENODEV;
1836
fd6d3f0e
MC		 1837 udelay(100);
1838 }
1839 return -ENODEV;
1840 }
1841
1842 /* Wait for firmware initialization to complete. */
1843 for (i = 0; i < 100000; i++) {
1844 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1845 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1846 break;
6d446ec3
GS		 1847 if (pci_channel_offline(tp->pdev)) {
1848 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1849 tg3_flag_set(tp, NO_FWARE_REPORTED);
1850 netdev_info(tp->dev, "No firmware running\n");
1851 }
1852
1853 break;
1854 }
1855
fd6d3f0e
MC		 1856 udelay(10);
1857 }
1858
1859 /* Chip might not be fitted with firmware. Some Sun onboard
1860 * parts are configured like that. So don't signal the timeout
1861 * of the above loop as an error, but do report the lack of
1862 * running firmware once.
1863 */
1864 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1865 tg3_flag_set(tp, NO_FWARE_REPORTED);
1866
1867 netdev_info(tp->dev, "No firmware running\n");
1868 }
1869
4153577a 1870 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
fd6d3f0e
MC		 1871 /* The 57765 A0 needs a little more
1872 * time to do some important work.
1873 */
1874 mdelay(10);
1875 }
1876
1877 return 0;
1878}
1879
95e2869a
MC		 1880static void tg3_link_report(struct tg3 *tp)
1881{
1882 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1883 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1884 tg3_ump_link_report(tp);
1885 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1886 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1887 (tp->link_config.active_speed == SPEED_1000 ?
1888 1000 :
1889 (tp->link_config.active_speed == SPEED_100 ?
1890 100 : 10)),
1891 (tp->link_config.active_duplex == DUPLEX_FULL ?
1892 "full" : "half"));
1893
1894 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1895 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1896 "on" : "off",
1897 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1898 "on" : "off");
47007831
MC		 1899
1900 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1901 netdev_info(tp->dev, "EEE is %s\n",
1902 tp->setlpicnt ? "enabled" : "disabled");
1903
95e2869a
MC		 1904 tg3_ump_link_report(tp);
1905 }
84421b99
NS		 1906
1907 tp->link_up = netif_carrier_ok(tp->dev);
95e2869a
MC		 1908}
1909
fdad8de4
NS		 1910static u32 tg3_decode_flowctrl_1000T(u32 adv)
1911{
1912 u32 flowctrl = 0;
1913
1914 if (adv & ADVERTISE_PAUSE_CAP) {
1915 flowctrl |= FLOW_CTRL_RX;
1916 if (!(adv & ADVERTISE_PAUSE_ASYM))
1917 flowctrl |= FLOW_CTRL_TX;
1918 } else if (adv & ADVERTISE_PAUSE_ASYM)
1919 flowctrl |= FLOW_CTRL_TX;
1920
1921 return flowctrl;
1922}
1923
95e2869a
MC		 1924static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1925{
1926 u16 miireg;
1927
e18ce346 1928 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1929 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1930 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1931 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1932 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1933 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1934 else
1935 miireg = 0;
1936
1937 return miireg;
1938}
1939
fdad8de4
NS		 1940static u32 tg3_decode_flowctrl_1000X(u32 adv)
1941{
1942 u32 flowctrl = 0;
1943
1944 if (adv & ADVERTISE_1000XPAUSE) {
1945 flowctrl |= FLOW_CTRL_RX;
1946 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1947 flowctrl |= FLOW_CTRL_TX;
1948 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1949 flowctrl |= FLOW_CTRL_TX;
1950
1951 return flowctrl;
1952}
1953
95e2869a
MC		 1954static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1955{
1956 u8 cap = 0;
1957
f3791cdf
MC		 1958 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1959 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1960 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1961 if (lcladv & ADVERTISE_1000XPAUSE)
1962 cap = FLOW_CTRL_RX;
1963 if (rmtadv & ADVERTISE_1000XPAUSE)
e18ce346 1964 cap = FLOW_CTRL_TX;
95e2869a
MC		 1965 }
1966
1967 return cap;
1968}
1969
f51f3562 1970static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1971{
b02fd9e3 1972 u8 autoneg;
f51f3562 1973 u8 flowctrl = 0;
95e2869a
MC		 1974 u32 old_rx_mode = tp->rx_mode;
1975 u32 old_tx_mode = tp->tx_mode;
1976
63c3a66f 1977 if (tg3_flag(tp, USE_PHYLIB))
ead2402c 1978 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg;
b02fd9e3
MC		 1979 else
1980 autoneg = tp->link_config.autoneg;
1981
63c3a66f 1982 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
f07e9af3 1983 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
f51f3562 1984 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1985 else
bc02ff95 1986 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1987 } else
1988 flowctrl = tp->link_config.flowctrl;
95e2869a 1989
f51f3562 1990 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1991
e18ce346 1992 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1993 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1994 else
1995 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1996
f51f3562 1997 if (old_rx_mode != tp->rx_mode)
95e2869a 1998 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1999
e18ce346 2000 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 2001 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
2002 else
2003 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
2004
f51f3562 2005 if (old_tx_mode != tp->tx_mode)
95e2869a 2006 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 2007}
2008
b02fd9e3
MC		 2009static void tg3_adjust_link(struct net_device *dev)
2010{
2011 u8 oldflowctrl, linkmesg = 0;
2012 u32 mac_mode, lcl_adv, rmt_adv;
2013 struct tg3 *tp = netdev_priv(dev);
ead2402c 2014 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 2015
24bb4fb6 2016 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 2017
2018 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2019 MAC_MODE_HALF_DUPLEX);
2020
2021 oldflowctrl = tp->link_config.active_flowctrl;
2022
2023 if (phydev->link) {
2024 lcl_adv = 0;
2025 rmt_adv = 0;
2026
2027 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2028 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748 2029 else if (phydev->speed == SPEED_1000 ||
4153577a 2030 tg3_asic_rev(tp) != ASIC_REV_5785)
b02fd9e3 2031 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 2032 else
2033 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 2034
2035 if (phydev->duplex == DUPLEX_HALF)
2036 mac_mode |= MAC_MODE_HALF_DUPLEX;
2037 else {
f88788f0 2038 lcl_adv = mii_advertise_flowctrl(
b02fd9e3
MC		 2039 tp->link_config.flowctrl);
2040
2041 if (phydev->pause)
2042 rmt_adv = LPA_PAUSE_CAP;
2043 if (phydev->asym_pause)
2044 rmt_adv |= LPA_PAUSE_ASYM;
2045 }
2046
2047 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2048 } else
2049 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2050
2051 if (mac_mode != tp->mac_mode) {
2052 tp->mac_mode = mac_mode;
2053 tw32_f(MAC_MODE, tp->mac_mode);
2054 udelay(40);
2055 }
2056
4153577a 2057 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
fcb389df
MC		 2058 if (phydev->speed == SPEED_10)
2059 tw32(MAC_MI_STAT,
2060 MAC_MI_STAT_10MBPS_MODE |
2061 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2062 else
2063 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2064 }
2065
b02fd9e3
MC		 2066 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2067 tw32(MAC_TX_LENGTHS,
2068 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2069 (6 << TX_LENGTHS_IPG_SHIFT) |
2070 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2071 else
2072 tw32(MAC_TX_LENGTHS,
2073 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2074 (6 << TX_LENGTHS_IPG_SHIFT) |
2075 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2076
34655ad6 2077 if (phydev->link != tp->old_link ||
b02fd9e3
MC		 2078 phydev->speed != tp->link_config.active_speed ||
2079 phydev->duplex != tp->link_config.active_duplex ||
2080 oldflowctrl != tp->link_config.active_flowctrl)
c6cdf436 2081 linkmesg = 1;
b02fd9e3 2082
34655ad6 2083 tp->old_link = phydev->link;
b02fd9e3
MC		 2084 tp->link_config.active_speed = phydev->speed;
2085 tp->link_config.active_duplex = phydev->duplex;
2086
24bb4fb6 2087 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 2088
2089 if (linkmesg)
2090 tg3_link_report(tp);
2091}
2092
2093static int tg3_phy_init(struct tg3 *tp)
2094{
2095 struct phy_device *phydev;
2096
f07e9af3 2097 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
b02fd9e3
MC		 2098 return 0;
2099
2100 /* Bring the PHY back to a known state. */
2101 tg3_bmcr_reset(tp);
2102
ead2402c 2103 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3
MC		 2104
2105 /* Attach the MAC to the PHY. */
f9a8f83b
FF		 2106 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2107 tg3_adjust_link, phydev->interface);
b02fd9e3 2108 if (IS_ERR(phydev)) {
ab96b241 2109 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 2110 return PTR_ERR(phydev);
2111 }
2112
b02fd9e3 2113 /* Mask with MAC supported features. */
9c61d6bc
MC		 2114 switch (phydev->interface) {
2115 case PHY_INTERFACE_MODE_GMII:
2116 case PHY_INTERFACE_MODE_RGMII:
f07e9af3 2117 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
321d32a0
MC		 2118 phydev->supported &= (PHY_GBIT_FEATURES |
2119 SUPPORTED_Pause |
2120 SUPPORTED_Asym_Pause);
2121 break;
2122 }
2123 /* fallthru */
9c61d6bc
MC		 2124 case PHY_INTERFACE_MODE_MII:
2125 phydev->supported &= (PHY_BASIC_FEATURES |
2126 SUPPORTED_Pause |
2127 SUPPORTED_Asym_Pause);
2128 break;
2129 default:
ead2402c 2130 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
9c61d6bc
MC		 2131 return -EINVAL;
2132 }
2133
f07e9af3 2134 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2135
2136 phydev->advertising = phydev->supported;
2137
b02fd9e3
MC		 2138 return 0;
2139}
2140
2141static void tg3_phy_start(struct tg3 *tp)
2142{
2143 struct phy_device *phydev;
2144
f07e9af3 2145 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2146 return;
2147
ead2402c 2148 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 2149
80096068
MC		 2150 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2151 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
c6700ce2
MC		 2152 phydev->speed = tp->link_config.speed;
2153 phydev->duplex = tp->link_config.duplex;
2154 phydev->autoneg = tp->link_config.autoneg;
2155 phydev->advertising = tp->link_config.advertising;
b02fd9e3
MC		 2156 }
2157
2158 phy_start(phydev);
2159
2160 phy_start_aneg(phydev);
2161}
2162
2163static void tg3_phy_stop(struct tg3 *tp)
2164{
f07e9af3 2165 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2166 return;
2167
ead2402c 2168 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]);
b02fd9e3
MC		 2169}
2170
2171static void tg3_phy_fini(struct tg3 *tp)
2172{
f07e9af3 2173 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
ead2402c 2174 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
f07e9af3 2175 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2176 }
2177}
2178
941ec90f
MC		 2179static int tg3_phy_set_extloopbk(struct tg3 *tp)
2180{
2181 int err;
2182 u32 val;
2183
2184 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2185 return 0;
2186
2187 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2188 /* Cannot do read-modify-write on 5401 */
2189 err = tg3_phy_auxctl_write(tp,
2190 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2191 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2192 0x4c20);
2193 goto done;
2194 }
2195
2196 err = tg3_phy_auxctl_read(tp,
2197 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2198 if (err)
2199 return err;
2200
2201 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2202 err = tg3_phy_auxctl_write(tp,
2203 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2204
2205done:
2206 return err;
2207}
2208
7f97a4bd
MC		 2209static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2210{
2211 u32 phytest;
2212
2213 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2214 u32 phy;
2215
2216 tg3_writephy(tp, MII_TG3_FET_TEST,
2217 phytest | MII_TG3_FET_SHADOW_EN);
2218 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2219 if (enable)
2220 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2221 else
2222 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2223 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2224 }
2225 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2226 }
2227}
2228
6833c043
MC		 2229static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2230{
2231 u32 reg;
2232
63c3a66f
JP		 2233 if (!tg3_flag(tp, 5705_PLUS) ||
2234 (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2235 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
6833c043
MC		 2236 return;
2237
f07e9af3 2238 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7f97a4bd
MC		 2239 tg3_phy_fet_toggle_apd(tp, enable);
2240 return;
2241 }
2242
3ab71071 2243 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
6833c043
MC		 2244 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2245 MII_TG3_MISC_SHDW_SCR5_SDTL |
2246 MII_TG3_MISC_SHDW_SCR5_C125OE;
4153577a 2247 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
6833c043
MC		 2248 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2249
3ab71071 2250 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
6833c043
MC		 2251
2252
3ab71071 2253 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
6833c043
MC		 2254 if (enable)
2255 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2256
3ab71071 2257 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
6833c043
MC		 2258}
2259
953c96e0 2260static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
9ef8ca99
MC		 2261{
2262 u32 phy;
2263
63c3a66f 2264 if (!tg3_flag(tp, 5705_PLUS) ||
f07e9af3 2265 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9ef8ca99
MC		 2266 return;
2267
f07e9af3 2268 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
9ef8ca99
MC		 2269 u32 ephy;
2270
535ef6e1
MC		 2271 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2272 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2273
2274 tg3_writephy(tp, MII_TG3_FET_TEST,
2275 ephy | MII_TG3_FET_SHADOW_EN);
2276 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 2277 if (enable)
535ef6e1 2278 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 2279 else
535ef6e1
MC		 2280 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2281 tg3_writephy(tp, reg, phy);
9ef8ca99 2282 }
535ef6e1 2283 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 2284 }
2285 } else {
15ee95c3
MC		 2286 int ret;
2287
2288 ret = tg3_phy_auxctl_read(tp,
2289 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2290 if (!ret) {
9ef8ca99
MC		 2291 if (enable)
2292 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2293 else
2294 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
b4bd2929
MC		 2295 tg3_phy_auxctl_write(tp,
2296 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
9ef8ca99
MC		 2297 }
2298 }
2299}
2300
1da177e4
LT		 2301static void tg3_phy_set_wirespeed(struct tg3 *tp)
2302{
15ee95c3 2303 int ret;
1da177e4
LT		 2304 u32 val;
2305
f07e9af3 2306 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1da177e4
LT		 2307 return;
2308
15ee95c3
MC		 2309 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2310 if (!ret)
b4bd2929
MC		 2311 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2312 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1da177e4
LT		 2313}
2314
b2a5c19c
MC		 2315static void tg3_phy_apply_otp(struct tg3 *tp)
2316{
2317 u32 otp, phy;
2318
2319 if (!tp->phy_otp)
2320 return;
2321
2322 otp = tp->phy_otp;
2323
daf3ec68 2324 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
1d36ba45 2325 return;
b2a5c19c
MC		 2326
2327 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2328 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2329 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2330
2331 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2332 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2333 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2334
2335 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2336 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2337 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2338
2339 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2340 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2341
2342 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2343 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2344
2345 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2346 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2347 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2348
daf3ec68 2349 tg3_phy_toggle_auxctl_smdsp(tp, false);
b2a5c19c
MC		 2350}
2351
400dfbaa
NS		 2352static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2353{
2354 u32 val;
2355 struct ethtool_eee *dest = &tp->eee;
2356
2357 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2358 return;
2359
2360 if (eee)
2361 dest = eee;
2362
2363 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2364 return;
2365
2366 /* Pull eee_active */
2367 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2368 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2369 dest->eee_active = 1;
2370 } else
2371 dest->eee_active = 0;
2372
2373 /* Pull lp advertised settings */
2374 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2375 return;
2376 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2377
2378 /* Pull advertised and eee_enabled settings */
2379 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2380 return;
2381 dest->eee_enabled = !!val;
2382 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2383
2384 /* Pull tx_lpi_enabled */
2385 val = tr32(TG3_CPMU_EEE_MODE);
2386 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2387
2388 /* Pull lpi timer value */
2389 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2390}
2391
953c96e0 2392static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
52b02d04
MC		 2393{
2394 u32 val;
2395
2396 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2397 return;
2398
2399 tp->setlpicnt = 0;
2400
2401 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
953c96e0 2402 current_link_up &&
a6b68dab
MC		 2403 tp->link_config.active_duplex == DUPLEX_FULL &&
2404 (tp->link_config.active_speed == SPEED_100 ||
2405 tp->link_config.active_speed == SPEED_1000)) {
52b02d04
MC		 2406 u32 eeectl;
2407
2408 if (tp->link_config.active_speed == SPEED_1000)
2409 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2410 else
2411 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2412
2413 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2414
400dfbaa
NS		 2415 tg3_eee_pull_config(tp, NULL);
2416 if (tp->eee.eee_active)
52b02d04
MC		 2417 tp->setlpicnt = 2;
2418 }
2419
2420 if (!tp->setlpicnt) {
953c96e0 2421 if (current_link_up &&
daf3ec68 2422 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94 2423 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
daf3ec68 2424 tg3_phy_toggle_auxctl_smdsp(tp, false);
b715ce94
MC		 2425 }
2426
52b02d04
MC		 2427 val = tr32(TG3_CPMU_EEE_MODE);
2428 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2429 }
2430}
2431
b0c5943f
MC		 2432static void tg3_phy_eee_enable(struct tg3 *tp)
2433{
2434 u32 val;
2435
2436 if (tp->link_config.active_speed == SPEED_1000 &&
4153577a
JP		 2437 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2438 tg3_asic_rev(tp) == ASIC_REV_5719 ||
55086ad9 2439 tg3_flag(tp, 57765_CLASS)) &&
daf3ec68 2440 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94
MC		 2441 val = MII_TG3_DSP_TAP26_ALNOKO |
2442 MII_TG3_DSP_TAP26_RMRXSTO;
2443 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
daf3ec68 2444 tg3_phy_toggle_auxctl_smdsp(tp, false);
b0c5943f
MC		 2445 }
2446
2447 val = tr32(TG3_CPMU_EEE_MODE);
2448 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2449}
2450
1da177e4
LT		 2451static int tg3_wait_macro_done(struct tg3 *tp)
2452{
2453 int limit = 100;
2454
2455 while (limit--) {
2456 u32 tmp32;
2457
f08aa1a8 2458 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1da177e4
LT		 2459 if ((tmp32 & 0x1000) == 0)
2460 break;
2461 }
2462 }
d4675b52 2463 if (limit < 0)
1da177e4
LT		 2464 return -EBUSY;
2465
2466 return 0;
2467}
2468
2469static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2470{
2471 static const u32 test_pat[4][6] = {
2472 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2473 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2474 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2475 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2476 };
2477 int chan;
2478
2479 for (chan = 0; chan < 4; chan++) {
2480 int i;
2481
2482 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2483 (chan * 0x2000) | 0x0200);
f08aa1a8 2484 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2485
2486 for (i = 0; i < 6; i++)
2487 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2488 test_pat[chan][i]);
2489
f08aa1a8 2490 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2491 if (tg3_wait_macro_done(tp)) {
2492 *resetp = 1;
2493 return -EBUSY;
2494 }
2495
2496 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2497 (chan * 0x2000) | 0x0200);
f08aa1a8 2498 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1da177e4
LT		 2499 if (tg3_wait_macro_done(tp)) {
2500 *resetp = 1;
2501 return -EBUSY;
2502 }
2503
f08aa1a8 2504 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1da177e4
LT		 2505 if (tg3_wait_macro_done(tp)) {
2506 *resetp = 1;
2507 return -EBUSY;
2508 }
2509
2510 for (i = 0; i < 6; i += 2) {
2511 u32 low, high;
2512
2513 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2514 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2515 tg3_wait_macro_done(tp)) {
2516 *resetp = 1;
2517 return -EBUSY;
2518 }
2519 low &= 0x7fff;
2520 high &= 0x000f;
2521 if (low != test_pat[chan][i] ||
2522 high != test_pat[chan][i+1]) {
2523 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2524 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2525 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2526
2527 return -EBUSY;
2528 }
2529 }
2530 }
2531
2532 return 0;
2533}
2534
2535static int tg3_phy_reset_chanpat(struct tg3 *tp)
2536{
2537 int chan;
2538
2539 for (chan = 0; chan < 4; chan++) {
2540 int i;
2541
2542 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2543 (chan * 0x2000) | 0x0200);
f08aa1a8 2544 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2545 for (i = 0; i < 6; i++)
2546 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
f08aa1a8 2547 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2548 if (tg3_wait_macro_done(tp))
2549 return -EBUSY;
2550 }
2551
2552 return 0;
2553}
2554
2555static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2556{
2557 u32 reg32, phy9_orig;
2558 int retries, do_phy_reset, err;
2559
2560 retries = 10;
2561 do_phy_reset = 1;
2562 do {
2563 if (do_phy_reset) {
2564 err = tg3_bmcr_reset(tp);
2565 if (err)
2566 return err;
2567 do_phy_reset = 0;
2568 }
2569
2570 /* Disable transmitter and interrupt. */
2571 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2572 continue;
2573
2574 reg32 |= 0x3000;
2575 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2576
2577 /* Set full-duplex, 1000 mbps. */
2578 tg3_writephy(tp, MII_BMCR,
221c5637 2579 BMCR_FULLDPLX | BMCR_SPEED1000);
1da177e4
LT		 2580
2581 /* Set to master mode. */
221c5637 2582 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
1da177e4
LT		 2583 continue;
2584
221c5637
MC		 2585 tg3_writephy(tp, MII_CTRL1000,
2586 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
1da177e4 2587
daf3ec68 2588 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
1d36ba45
MC		 2589 if (err)
2590 return err;
1da177e4
LT		 2591
2592 /* Block the PHY control access. */
6ee7c0a0 2593 tg3_phydsp_write(tp, 0x8005, 0x0800);
1da177e4
LT		 2594
2595 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2596 if (!err)
2597 break;
2598 } while (--retries);
2599
2600 err = tg3_phy_reset_chanpat(tp);
2601 if (err)
2602 return err;
2603
6ee7c0a0 2604 tg3_phydsp_write(tp, 0x8005, 0x0000);
1da177e4
LT		 2605
2606 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
f08aa1a8 2607 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1da177e4 2608
daf3ec68 2609 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2610
221c5637 2611 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
1da177e4
LT		 2612
2613 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2614 reg32 &= ~0x3000;
2615 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2616 } else if (!err)
2617 err = -EBUSY;
2618
2619 return err;
2620}
2621
f4a46d1f
NNS		 2622static void tg3_carrier_off(struct tg3 *tp)
2623{
2624 netif_carrier_off(tp->dev);
2625 tp->link_up = false;
2626}
2627
ce20f161
NS		 2628static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2629{
2630 if (tg3_flag(tp, ENABLE_ASF))
2631 netdev_warn(tp->dev,
2632 "Management side-band traffic will be interrupted during phy settings change\n");
2633}
2634
1da177e4
LT		 2635/* This will reset the tigon3 PHY if there is no valid
2636 * link unless the FORCE argument is non-zero.
2637 */
2638static int tg3_phy_reset(struct tg3 *tp)
2639{
f833c4c1 2640 u32 val, cpmuctrl;
1da177e4
LT		 2641 int err;
2642
4153577a 2643 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 2644 val = tr32(GRC_MISC_CFG);
2645 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2646 udelay(40);
2647 }
f833c4c1
MC		 2648 err = tg3_readphy(tp, MII_BMSR, &val);
2649 err |= tg3_readphy(tp, MII_BMSR, &val);
1da177e4
LT		 2650 if (err != 0)
2651 return -EBUSY;
2652
f4a46d1f 2653 if (netif_running(tp->dev) && tp->link_up) {
84421b99 2654 netif_carrier_off(tp->dev);
c8e1e82b
MC		 2655 tg3_link_report(tp);
2656 }
2657
4153577a
JP		 2658 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2659 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2660 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 2661 err = tg3_phy_reset_5703_4_5(tp);
2662 if (err)
2663 return err;
2664 goto out;
2665 }
2666
b2a5c19c 2667 cpmuctrl = 0;
4153577a
JP		 2668 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2669 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 2670 cpmuctrl = tr32(TG3_CPMU_CTRL);
2671 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2672 tw32(TG3_CPMU_CTRL,
2673 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2674 }
2675
1da177e4
LT		 2676 err = tg3_bmcr_reset(tp);
2677 if (err)
2678 return err;
2679
b2a5c19c 2680 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
f833c4c1
MC		 2681 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2682 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
b2a5c19c
MC		 2683
2684 tw32(TG3_CPMU_CTRL, cpmuctrl);
2685 }
2686
4153577a
JP		 2687 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2688 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 2689 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2690 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2691 CPMU_LSPD_1000MB_MACCLK_12_5) {
2692 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2693 udelay(40);
2694 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2695 }
2696 }
2697
63c3a66f 2698 if (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2699 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
ecf1410b
MC		 2700 return 0;
2701
b2a5c19c
MC		 2702 tg3_phy_apply_otp(tp);
2703
f07e9af3 2704 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
6833c043
MC		 2705 tg3_phy_toggle_apd(tp, true);
2706 else
2707 tg3_phy_toggle_apd(tp, false);
2708
1da177e4 2709out:
1d36ba45 2710 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
daf3ec68 2711 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
6ee7c0a0
MC		 2712 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2713 tg3_phydsp_write(tp, 0x000a, 0x0323);
daf3ec68 2714 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2715 }
1d36ba45 2716
f07e9af3 2717 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
f08aa1a8
MC		 2718 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2719 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1da177e4 2720 }
1d36ba45 2721
f07e9af3 2722 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
daf3ec68 2723 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2724 tg3_phydsp_write(tp, 0x000a, 0x310b);
2725 tg3_phydsp_write(tp, 0x201f, 0x9506);
2726 tg3_phydsp_write(tp, 0x401f, 0x14e2);
daf3ec68 2727 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2728 }
f07e9af3 2729 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
daf3ec68 2730 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2731 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2732 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2733 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2734 tg3_writephy(tp, MII_TG3_TEST1,
2735 MII_TG3_TEST1_TRIM_EN | 0x4);
2736 } else
2737 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2738
daf3ec68 2739 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2740 }
c424cb24 2741 }
1d36ba45 2742
1da177e4
LT		 2743 /* Set Extended packet length bit (bit 14) on all chips that */
2744 /* support jumbo frames */
79eb6904 2745 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4 2746 /* Cannot do read-modify-write on 5401 */
b4bd2929 2747 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
63c3a66f 2748 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
1da177e4 2749 /* Set bit 14 with read-modify-write to preserve other bits */
15ee95c3
MC		 2750 err = tg3_phy_auxctl_read(tp,
2751 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2752 if (!err)
b4bd2929
MC		 2753 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2754 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
1da177e4
LT		 2755 }
2756
2757 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2758 * jumbo frames transmission.
2759 */
63c3a66f 2760 if (tg3_flag(tp, JUMBO_CAPABLE)) {
f833c4c1 2761 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
c6cdf436 2762 tg3_writephy(tp, MII_TG3_EXT_CTRL,
f833c4c1 2763 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1da177e4
LT		 2764 }
2765
4153577a 2766 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
715116a1 2767 /* adjust output voltage */
535ef6e1 2768 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2769 }
2770
4153577a 2771 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
c65a17f4
MC		 2772 tg3_phydsp_write(tp, 0xffb, 0x4000);
2773
953c96e0 2774 tg3_phy_toggle_automdix(tp, true);
1da177e4
LT		 2775 tg3_phy_set_wirespeed(tp);
2776 return 0;
2777}
2778
3a1e19d3
MC		 2779#define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2780#define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2781#define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2782 TG3_GPIO_MSG_NEED_VAUX)
2783#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2784 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2785 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2786 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2787 (TG3_GPIO_MSG_DRVR_PRES << 12))
2788
2789#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2790 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2791 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2792 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2793 (TG3_GPIO_MSG_NEED_VAUX << 12))
2794
2795static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2796{
2797 u32 status, shift;
2798
4153577a
JP		 2799 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2800 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2801 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2802 else
2803 status = tr32(TG3_CPMU_DRV_STATUS);
2804
2805 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2806 status &= ~(TG3_GPIO_MSG_MASK << shift);
2807 status |= (newstat << shift);
2808
4153577a
JP		 2809 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2810 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2811 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2812 else
2813 tw32(TG3_CPMU_DRV_STATUS, status);
2814
2815 return status >> TG3_APE_GPIO_MSG_SHIFT;
2816}
2817
520b2756
MC		 2818static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2819{
2820 if (!tg3_flag(tp, IS_NIC))
2821 return 0;
2822
4153577a
JP		 2823 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2824 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2825 tg3_asic_rev(tp) == ASIC_REV_5720) {
3a1e19d3
MC		 2826 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2827 return -EIO;
520b2756 2828
3a1e19d3
MC		 2829 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2830
2831 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2832 TG3_GRC_LCLCTL_PWRSW_DELAY);
2833
2834 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2835 } else {
2836 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2837 TG3_GRC_LCLCTL_PWRSW_DELAY);
2838 }
6f5c8f83 2839
520b2756
MC		 2840 return 0;
2841}
2842
2843static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2844{
2845 u32 grc_local_ctrl;
2846
2847 if (!tg3_flag(tp, IS_NIC) ||
4153577a
JP		 2848 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2849 tg3_asic_rev(tp) == ASIC_REV_5701)
520b2756
MC		 2850 return;
2851
2852 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2853
2854 tw32_wait_f(GRC_LOCAL_CTRL,
2855 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2856 TG3_GRC_LCLCTL_PWRSW_DELAY);
2857
2858 tw32_wait_f(GRC_LOCAL_CTRL,
2859 grc_local_ctrl,
2860 TG3_GRC_LCLCTL_PWRSW_DELAY);
2861
2862 tw32_wait_f(GRC_LOCAL_CTRL,
2863 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2864 TG3_GRC_LCLCTL_PWRSW_DELAY);
2865}
2866
2867static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2868{
2869 if (!tg3_flag(tp, IS_NIC))
2870 return;
2871
4153577a
JP		 2872 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2873 tg3_asic_rev(tp) == ASIC_REV_5701) {
520b2756
MC		 2874 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2875 (GRC_LCLCTRL_GPIO_OE0 |
2876 GRC_LCLCTRL_GPIO_OE1 |
2877 GRC_LCLCTRL_GPIO_OE2 |
2878 GRC_LCLCTRL_GPIO_OUTPUT0 |
2879 GRC_LCLCTRL_GPIO_OUTPUT1),
2880 TG3_GRC_LCLCTL_PWRSW_DELAY);
2881 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2882 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2883 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2884 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2885 GRC_LCLCTRL_GPIO_OE1 |
2886 GRC_LCLCTRL_GPIO_OE2 |
2887 GRC_LCLCTRL_GPIO_OUTPUT0 |
2888 GRC_LCLCTRL_GPIO_OUTPUT1 |
2889 tp->grc_local_ctrl;
2890 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2891 TG3_GRC_LCLCTL_PWRSW_DELAY);
2892
2893 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2894 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2895 TG3_GRC_LCLCTL_PWRSW_DELAY);
2896
2897 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2898 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2899 TG3_GRC_LCLCTL_PWRSW_DELAY);
2900 } else {
2901 u32 no_gpio2;
2902 u32 grc_local_ctrl = 0;
2903
2904 /* Workaround to prevent overdrawing Amps. */
4153577a 2905 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
520b2756
MC		 2906 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2907 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2908 grc_local_ctrl,
2909 TG3_GRC_LCLCTL_PWRSW_DELAY);
2910 }
2911
2912 /* On 5753 and variants, GPIO2 cannot be used. */
2913 no_gpio2 = tp->nic_sram_data_cfg &
2914 NIC_SRAM_DATA_CFG_NO_GPIO2;
2915
2916 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2917 GRC_LCLCTRL_GPIO_OE1 |
2918 GRC_LCLCTRL_GPIO_OE2 |
2919 GRC_LCLCTRL_GPIO_OUTPUT1 |
2920 GRC_LCLCTRL_GPIO_OUTPUT2;
2921 if (no_gpio2) {
2922 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2923 GRC_LCLCTRL_GPIO_OUTPUT2);
2924 }
2925 tw32_wait_f(GRC_LOCAL_CTRL,
2926 tp->grc_local_ctrl | grc_local_ctrl,
2927 TG3_GRC_LCLCTL_PWRSW_DELAY);
2928
2929 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2930
2931 tw32_wait_f(GRC_LOCAL_CTRL,
2932 tp->grc_local_ctrl | grc_local_ctrl,
2933 TG3_GRC_LCLCTL_PWRSW_DELAY);
2934
2935 if (!no_gpio2) {
2936 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2937 tw32_wait_f(GRC_LOCAL_CTRL,
2938 tp->grc_local_ctrl | grc_local_ctrl,
2939 TG3_GRC_LCLCTL_PWRSW_DELAY);
2940 }
2941 }
3a1e19d3
MC		 2942}
2943
cd0d7228 2944static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
3a1e19d3
MC		 2945{
2946 u32 msg = 0;
2947
2948 /* Serialize power state transitions */
2949 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2950 return;
2951
cd0d7228 2952 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
3a1e19d3
MC		 2953 msg = TG3_GPIO_MSG_NEED_VAUX;
2954
2955 msg = tg3_set_function_status(tp, msg);
2956
2957 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2958 goto done;
6f5c8f83 2959
3a1e19d3
MC		 2960 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2961 tg3_pwrsrc_switch_to_vaux(tp);
2962 else
2963 tg3_pwrsrc_die_with_vmain(tp);
2964
2965done:
6f5c8f83 2966 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
520b2756
MC		 2967}
2968
cd0d7228 2969static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
1da177e4 2970{
683644b7 2971 bool need_vaux = false;
1da177e4 2972
334355aa 2973 /* The GPIOs do something completely different on 57765. */
55086ad9 2974 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
1da177e4
LT		 2975 return;
2976
4153577a
JP		 2977 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2978 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2979 tg3_asic_rev(tp) == ASIC_REV_5720) {
cd0d7228
MC		 2980 tg3_frob_aux_power_5717(tp, include_wol ?
2981 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
3a1e19d3
MC		 2982 return;
2983 }
2984
2985 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
8c2dc7e1
MC		 2986 struct net_device *dev_peer;
2987
2988 dev_peer = pci_get_drvdata(tp->pdev_peer);
683644b7 2989
bc1c7567 2990 /* remove_one() may have been run on the peer. */
683644b7
MC		 2991 if (dev_peer) {
2992 struct tg3 *tp_peer = netdev_priv(dev_peer);
2993
63c3a66f 2994 if (tg3_flag(tp_peer, INIT_COMPLETE))
683644b7
MC		 2995 return;
2996
cd0d7228 2997 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
63c3a66f 2998 tg3_flag(tp_peer, ENABLE_ASF))
683644b7
MC		 2999 need_vaux = true;
3000 }
1da177e4
LT		 3001 }
3002
cd0d7228
MC		 3003 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
3004 tg3_flag(tp, ENABLE_ASF))
683644b7
MC		 3005 need_vaux = true;
3006
520b2756
MC		 3007 if (need_vaux)
3008 tg3_pwrsrc_switch_to_vaux(tp);
3009 else
3010 tg3_pwrsrc_die_with_vmain(tp);
1da177e4
LT		 3011}
3012
e8f3f6ca
MC		 3013static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3014{
3015 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3016 return 1;
79eb6904 3017 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 3018 if (speed != SPEED_10)
3019 return 1;
3020 } else if (speed == SPEED_10)
3021 return 1;
3022
3023 return 0;
3024}
3025
44f3b503
NS		 3026static bool tg3_phy_power_bug(struct tg3 *tp)
3027{
3028 switch (tg3_asic_rev(tp)) {
3029 case ASIC_REV_5700:
3030 case ASIC_REV_5704:
3031 return true;
3032 case ASIC_REV_5780:
3033 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3034 return true;
3035 return false;
3036 case ASIC_REV_5717:
3037 if (!tp->pci_fn)
3038 return true;
3039 return false;
3040 case ASIC_REV_5719:
3041 case ASIC_REV_5720:
3042 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3043 !tp->pci_fn)
3044 return true;
3045 return false;
3046 }
3047
3048 return false;
3049}
3050
989038e2
NS		 3051static bool tg3_phy_led_bug(struct tg3 *tp)
3052{
3053 switch (tg3_asic_rev(tp)) {
3054 case ASIC_REV_5719:
300cf9b9 3055 case ASIC_REV_5720:
989038e2
NS		 3056 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3057 !tp->pci_fn)
3058 return true;
3059 return false;
3060 }
3061
3062 return false;
3063}
3064
0a459aac 3065static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 3066{
ce057f01
MC		 3067 u32 val;
3068
942d1af0
NS		 3069 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3070 return;
3071
f07e9af3 3072 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a 3073 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
5129724a
MC		 3074 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3075 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3076
3077 sg_dig_ctrl |=
3078 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3079 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3080 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3081 }
3f7045c1 3082 return;
5129724a 3083 }
3f7045c1 3084
4153577a 3085 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 3086 tg3_bmcr_reset(tp);
3087 val = tr32(GRC_MISC_CFG);
3088 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3089 udelay(40);
3090 return;
f07e9af3 3091 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
0e5f784c
MC		 3092 u32 phytest;
3093 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3094 u32 phy;
3095
3096 tg3_writephy(tp, MII_ADVERTISE, 0);
3097 tg3_writephy(tp, MII_BMCR,
3098 BMCR_ANENABLE | BMCR_ANRESTART);
3099
3100 tg3_writephy(tp, MII_TG3_FET_TEST,
3101 phytest | MII_TG3_FET_SHADOW_EN);
3102 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3103 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3104 tg3_writephy(tp,
3105 MII_TG3_FET_SHDW_AUXMODE4,
3106 phy);
3107 }
3108 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3109 }
3110 return;
0a459aac 3111 } else if (do_low_power) {
989038e2
NS		 3112 if (!tg3_phy_led_bug(tp))
3113 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3114 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac 3115
b4bd2929
MC		 3116 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3117 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3118 MII_TG3_AUXCTL_PCTL_VREG_11V;
3119 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
715116a1 3120 }
3f7045c1 3121
15c3b696
MC		 3122 /* The PHY should not be powered down on some chips because
3123 * of bugs.
3124 */
44f3b503 3125 if (tg3_phy_power_bug(tp))
15c3b696 3126 return;
ce057f01 3127
4153577a
JP		 3128 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3129 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 3130 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3131 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3132 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3133 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3134 }
3135
15c3b696
MC		 3136 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3137}
3138
ffbcfed4
MC		 3139/* tp->lock is held. */
3140static int tg3_nvram_lock(struct tg3 *tp)
3141{
63c3a66f 3142 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3143 int i;
3144
3145 if (tp->nvram_lock_cnt == 0) {
3146 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3147 for (i = 0; i < 8000; i++) {
3148 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3149 break;
3150 udelay(20);
3151 }
3152 if (i == 8000) {
3153 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3154 return -ENODEV;
3155 }
3156 }
3157 tp->nvram_lock_cnt++;
3158 }
3159 return 0;
3160}
3161
3162/* tp->lock is held. */
3163static void tg3_nvram_unlock(struct tg3 *tp)
3164{
63c3a66f 3165 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3166 if (tp->nvram_lock_cnt > 0)
3167 tp->nvram_lock_cnt--;
3168 if (tp->nvram_lock_cnt == 0)
3169 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3170 }
3171}
3172
3173/* tp->lock is held. */
3174static void tg3_enable_nvram_access(struct tg3 *tp)
3175{
63c3a66f 3176 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3177 u32 nvaccess = tr32(NVRAM_ACCESS);
3178
3179 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3180 }
3181}
3182
3183/* tp->lock is held. */
3184static void tg3_disable_nvram_access(struct tg3 *tp)
3185{
63c3a66f 3186 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3187 u32 nvaccess = tr32(NVRAM_ACCESS);
3188
3189 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3190 }
3191}
3192
3193static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3194 u32 offset, u32 *val)
3195{
3196 u32 tmp;
3197 int i;
3198
3199 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3200 return -EINVAL;
3201
3202 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3203 EEPROM_ADDR_DEVID_MASK |
3204 EEPROM_ADDR_READ);
3205 tw32(GRC_EEPROM_ADDR,
3206 tmp |
3207 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3208 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3209 EEPROM_ADDR_ADDR_MASK) |
3210 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3211
3212 for (i = 0; i < 1000; i++) {
3213 tmp = tr32(GRC_EEPROM_ADDR);
3214
3215 if (tmp & EEPROM_ADDR_COMPLETE)
3216 break;
3217 msleep(1);
3218 }
3219 if (!(tmp & EEPROM_ADDR_COMPLETE))
3220 return -EBUSY;
3221
62cedd11
MC		 3222 tmp = tr32(GRC_EEPROM_DATA);
3223
3224 /*
3225 * The data will always be opposite the native endian
3226 * format. Perform a blind byteswap to compensate.
3227 */
3228 *val = swab32(tmp);
3229
ffbcfed4
MC		 3230 return 0;
3231}
3232
3233#define NVRAM_CMD_TIMEOUT 10000
3234
3235static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3236{
3237 int i;
3238
3239 tw32(NVRAM_CMD, nvram_cmd);
3240 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3241 udelay(10);
3242 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3243 udelay(10);
3244 break;
3245 }
3246 }
3247
3248 if (i == NVRAM_CMD_TIMEOUT)
3249 return -EBUSY;
3250
3251 return 0;
3252}
3253
3254static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3255{
63c3a66f
JP		 3256 if (tg3_flag(tp, NVRAM) &&
3257 tg3_flag(tp, NVRAM_BUFFERED) &&
3258 tg3_flag(tp, FLASH) &&
3259 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3260 (tp->nvram_jedecnum == JEDEC_ATMEL))
3261
3262 addr = ((addr / tp->nvram_pagesize) <<
3263 ATMEL_AT45DB0X1B_PAGE_POS) +
3264 (addr % tp->nvram_pagesize);
3265
3266 return addr;
3267}
3268
3269static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3270{
63c3a66f
JP		 3271 if (tg3_flag(tp, NVRAM) &&
3272 tg3_flag(tp, NVRAM_BUFFERED) &&
3273 tg3_flag(tp, FLASH) &&
3274 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3275 (tp->nvram_jedecnum == JEDEC_ATMEL))
3276
3277 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3278 tp->nvram_pagesize) +
3279 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3280
3281 return addr;
3282}
3283
e4f34110
MC		 3284/* NOTE: Data read in from NVRAM is byteswapped according to
3285 * the byteswapping settings for all other register accesses.
3286 * tg3 devices are BE devices, so on a BE machine, the data
3287 * returned will be exactly as it is seen in NVRAM. On a LE
3288 * machine, the 32-bit value will be byteswapped.
3289 */
ffbcfed4
MC		 3290static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3291{
3292 int ret;
3293
63c3a66f 3294 if (!tg3_flag(tp, NVRAM))
ffbcfed4
MC		 3295 return tg3_nvram_read_using_eeprom(tp, offset, val);
3296
3297 offset = tg3_nvram_phys_addr(tp, offset);
3298
3299 if (offset > NVRAM_ADDR_MSK)
3300 return -EINVAL;
3301
3302 ret = tg3_nvram_lock(tp);
3303 if (ret)
3304 return ret;
3305
3306 tg3_enable_nvram_access(tp);
3307
3308 tw32(NVRAM_ADDR, offset);
3309 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3310 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3311
3312 if (ret == 0)
e4f34110 3313 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 3314
3315 tg3_disable_nvram_access(tp);
3316
3317 tg3_nvram_unlock(tp);
3318
3319 return ret;
3320}
3321
a9dc529d
MC		 3322/* Ensures NVRAM data is in bytestream format. */
3323static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 3324{
3325 u32 v;
a9dc529d 3326 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 3327 if (!res)
a9dc529d 3328 *val = cpu_to_be32(v);
ffbcfed4
MC		 3329 return res;
3330}
3331
dbe9b92a
MC		 3332static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3333 u32 offset, u32 len, u8 *buf)
3334{
3335 int i, j, rc = 0;
3336 u32 val;
3337
3338 for (i = 0; i < len; i += 4) {
3339 u32 addr;
3340 __be32 data;
3341
3342 addr = offset + i;
3343
3344 memcpy(&data, buf + i, 4);
3345
3346 /*
3347 * The SEEPROM interface expects the data to always be opposite
3348 * the native endian format. We accomplish this by reversing
3349 * all the operations that would have been performed on the
3350 * data from a call to tg3_nvram_read_be32().
3351 */
3352 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3353
3354 val = tr32(GRC_EEPROM_ADDR);
3355 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3356
3357 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3358 EEPROM_ADDR_READ);
3359 tw32(GRC_EEPROM_ADDR, val |
3360 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3361 (addr & EEPROM_ADDR_ADDR_MASK) |
3362 EEPROM_ADDR_START |
3363 EEPROM_ADDR_WRITE);
3364
3365 for (j = 0; j < 1000; j++) {
3366 val = tr32(GRC_EEPROM_ADDR);
3367
3368 if (val & EEPROM_ADDR_COMPLETE)
3369 break;
3370 msleep(1);
3371 }
3372 if (!(val & EEPROM_ADDR_COMPLETE)) {
3373 rc = -EBUSY;
3374 break;
3375 }
3376 }
3377
3378 return rc;
3379}
3380
3381/* offset and length are dword aligned */
3382static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3383 u8 *buf)
3384{
3385 int ret = 0;
3386 u32 pagesize = tp->nvram_pagesize;
3387 u32 pagemask = pagesize - 1;
3388 u32 nvram_cmd;
3389 u8 *tmp;
3390
3391 tmp = kmalloc(pagesize, GFP_KERNEL);
3392 if (tmp == NULL)
3393 return -ENOMEM;
3394
3395 while (len) {
3396 int j;
3397 u32 phy_addr, page_off, size;
3398
3399 phy_addr = offset & ~pagemask;
3400
3401 for (j = 0; j < pagesize; j += 4) {
3402 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3403 (__be32 *) (tmp + j));
3404 if (ret)
3405 break;
3406 }
3407 if (ret)
3408 break;
3409
3410 page_off = offset & pagemask;
3411 size = pagesize;
3412 if (len < size)
3413 size = len;
3414
3415 len -= size;
3416
3417 memcpy(tmp + page_off, buf, size);
3418
3419 offset = offset + (pagesize - page_off);
3420
3421 tg3_enable_nvram_access(tp);
3422
3423 /*
3424 * Before we can erase the flash page, we need
3425 * to issue a special "write enable" command.
3426 */
3427 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3428
3429 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3430 break;
3431
3432 /* Erase the target page */
3433 tw32(NVRAM_ADDR, phy_addr);
3434
3435 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3436 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3437
3438 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3439 break;
3440
3441 /* Issue another write enable to start the write. */
3442 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3443
3444 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3445 break;
3446
3447 for (j = 0; j < pagesize; j += 4) {
3448 __be32 data;
3449
3450 data = *((__be32 *) (tmp + j));
3451
3452 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3453
3454 tw32(NVRAM_ADDR, phy_addr + j);
3455
3456 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3457 NVRAM_CMD_WR;
3458
3459 if (j == 0)
3460 nvram_cmd |= NVRAM_CMD_FIRST;
3461 else if (j == (pagesize - 4))
3462 nvram_cmd |= NVRAM_CMD_LAST;
3463
3464 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3465 if (ret)
3466 break;
3467 }
3468 if (ret)
3469 break;
3470 }
3471
3472 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3473 tg3_nvram_exec_cmd(tp, nvram_cmd);
3474
3475 kfree(tmp);
3476
3477 return ret;
3478}
3479
3480/* offset and length are dword aligned */
3481static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3482 u8 *buf)
3483{
3484 int i, ret = 0;
3485
3486 for (i = 0; i < len; i += 4, offset += 4) {
3487 u32 page_off, phy_addr, nvram_cmd;
3488 __be32 data;
3489
3490 memcpy(&data, buf + i, 4);
3491 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3492
3493 page_off = offset % tp->nvram_pagesize;
3494
3495 phy_addr = tg3_nvram_phys_addr(tp, offset);
3496
dbe9b92a
MC		 3497 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3498
3499 if (page_off == 0 || i == 0)
3500 nvram_cmd |= NVRAM_CMD_FIRST;
3501 if (page_off == (tp->nvram_pagesize - 4))
3502 nvram_cmd |= NVRAM_CMD_LAST;
3503
3504 if (i == (len - 4))
3505 nvram_cmd |= NVRAM_CMD_LAST;
3506
42278224
MC		 3507 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3508 !tg3_flag(tp, FLASH) ||
3509 !tg3_flag(tp, 57765_PLUS))
3510 tw32(NVRAM_ADDR, phy_addr);
3511
4153577a 3512 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
dbe9b92a
MC		 3513 !tg3_flag(tp, 5755_PLUS) &&
3514 (tp->nvram_jedecnum == JEDEC_ST) &&
3515 (nvram_cmd & NVRAM_CMD_FIRST)) {
3516 u32 cmd;
3517
3518 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3519 ret = tg3_nvram_exec_cmd(tp, cmd);
3520 if (ret)
3521 break;
3522 }
3523 if (!tg3_flag(tp, FLASH)) {
3524 /* We always do complete word writes to eeprom. */
3525 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3526 }
3527
3528 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3529 if (ret)
3530 break;
3531 }
3532 return ret;
3533}
3534
3535/* offset and length are dword aligned */
3536static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3537{
3538 int ret;
3539
3540 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3541 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3542 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3543 udelay(40);
3544 }
3545
3546 if (!tg3_flag(tp, NVRAM)) {
3547 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3548 } else {
3549 u32 grc_mode;
3550
3551 ret = tg3_nvram_lock(tp);
3552 if (ret)
3553 return ret;
3554
3555 tg3_enable_nvram_access(tp);
3556 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3557 tw32(NVRAM_WRITE1, 0x406);
3558
3559 grc_mode = tr32(GRC_MODE);
3560 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3561
3562 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3563 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3564 buf);
3565 } else {
3566 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3567 buf);
3568 }
3569
3570 grc_mode = tr32(GRC_MODE);
3571 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3572
3573 tg3_disable_nvram_access(tp);
3574 tg3_nvram_unlock(tp);
3575 }
3576
3577 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3578 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3579 udelay(40);
3580 }
3581
3582 return ret;
3583}
3584
997b4f13
MC		 3585#define RX_CPU_SCRATCH_BASE 0x30000
3586#define RX_CPU_SCRATCH_SIZE 0x04000
3587#define TX_CPU_SCRATCH_BASE 0x34000
3588#define TX_CPU_SCRATCH_SIZE 0x04000
3589
3590/* tp->lock is held. */
837c45bb 3591static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
997b4f13
MC		 3592{
3593 int i;
837c45bb 3594 const int iters = 10000;
997b4f13 3595
837c45bb
NS		 3596 for (i = 0; i < iters; i++) {
3597 tw32(cpu_base + CPU_STATE, 0xffffffff);
3598 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3599 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3600 break;
6d446ec3
GS		 3601 if (pci_channel_offline(tp->pdev))
3602 return -EBUSY;
837c45bb
NS		 3603 }
3604
3605 return (i == iters) ? -EBUSY : 0;
3606}
3607
3608/* tp->lock is held. */
3609static int tg3_rxcpu_pause(struct tg3 *tp)
3610{
3611 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3612
3613 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3614 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3615 udelay(10);
3616
3617 return rc;
3618}
3619
3620/* tp->lock is held. */
3621static int tg3_txcpu_pause(struct tg3 *tp)
3622{
3623 return tg3_pause_cpu(tp, TX_CPU_BASE);
3624}
3625
3626/* tp->lock is held. */
3627static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3628{
3629 tw32(cpu_base + CPU_STATE, 0xffffffff);
3630 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3631}
3632
3633/* tp->lock is held. */
3634static void tg3_rxcpu_resume(struct tg3 *tp)
3635{
3636 tg3_resume_cpu(tp, RX_CPU_BASE);
3637}
3638
3639/* tp->lock is held. */
3640static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3641{
3642 int rc;
3643
3644 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
997b4f13 3645
4153577a 3646 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
997b4f13
MC		 3647 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3648
3649 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3650 return 0;
3651 }
837c45bb
NS		 3652 if (cpu_base == RX_CPU_BASE) {
3653 rc = tg3_rxcpu_pause(tp);
997b4f13 3654 } else {
7e6c63f0
HM		 3655 /*
3656 * There is only an Rx CPU for the 5750 derivative in the
3657 * BCM4785.
3658 */
3659 if (tg3_flag(tp, IS_SSB_CORE))
3660 return 0;
3661
837c45bb 3662 rc = tg3_txcpu_pause(tp);
997b4f13
MC		 3663 }
3664
837c45bb 3665 if (rc) {
997b4f13 3666 netdev_err(tp->dev, "%s timed out, %s CPU\n",
837c45bb 3667 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
997b4f13
MC		 3668 return -ENODEV;
3669 }
3670
3671 /* Clear firmware's nvram arbitration. */
3672 if (tg3_flag(tp, NVRAM))
3673 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3674 return 0;
3675}
3676
31f11a95
NS		 3677static int tg3_fw_data_len(struct tg3 *tp,
3678 const struct tg3_firmware_hdr *fw_hdr)
3679{
3680 int fw_len;
3681
3682 /* Non fragmented firmware have one firmware header followed by a
3683 * contiguous chunk of data to be written. The length field in that
3684 * header is not the length of data to be written but the complete
3685 * length of the bss. The data length is determined based on
3686 * tp->fw->size minus headers.
3687 *
3688 * Fragmented firmware have a main header followed by multiple
3689 * fragments. Each fragment is identical to non fragmented firmware
3690 * with a firmware header followed by a contiguous chunk of data. In
3691 * the main header, the length field is unused and set to 0xffffffff.
3692 * In each fragment header the length is the entire size of that
3693 * fragment i.e. fragment data + header length. Data length is
3694 * therefore length field in the header minus TG3_FW_HDR_LEN.
3695 */
3696 if (tp->fw_len == 0xffffffff)
3697 fw_len = be32_to_cpu(fw_hdr->len);
3698 else
3699 fw_len = tp->fw->size;
3700
3701 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3702}
3703
997b4f13
MC		 3704/* tp->lock is held. */
3705static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3706 u32 cpu_scratch_base, int cpu_scratch_size,
77997ea3 3707 const struct tg3_firmware_hdr *fw_hdr)
997b4f13 3708{
c4dab506 3709 int err, i;
997b4f13 3710 void (*write_op)(struct tg3 *, u32, u32);
31f11a95 3711 int total_len = tp->fw->size;
997b4f13
MC		 3712
3713 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3714 netdev_err(tp->dev,
3715 "%s: Trying to load TX cpu firmware which is 5705\n",
3716 __func__);
3717 return -EINVAL;
3718 }
3719
c4dab506 3720 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
997b4f13
MC		 3721 write_op = tg3_write_mem;
3722 else
3723 write_op = tg3_write_indirect_reg32;
3724
c4dab506
NS		 3725 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3726 /* It is possible that bootcode is still loading at this point.
3727 * Get the nvram lock first before halting the cpu.
3728 */
3729 int lock_err = tg3_nvram_lock(tp);
3730 err = tg3_halt_cpu(tp, cpu_base);
3731 if (!lock_err)
3732 tg3_nvram_unlock(tp);
3733 if (err)
3734 goto out;
997b4f13 3735
c4dab506
NS		 3736 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3737 write_op(tp, cpu_scratch_base + i, 0);
3738 tw32(cpu_base + CPU_STATE, 0xffffffff);
3739 tw32(cpu_base + CPU_MODE,
3740 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3741 } else {
3742 /* Subtract additional main header for fragmented firmware and
3743 * advance to the first fragment
3744 */
3745 total_len -= TG3_FW_HDR_LEN;
3746 fw_hdr++;
3747 }
77997ea3 3748
31f11a95
NS		 3749 do {
3750 u32 *fw_data = (u32 *)(fw_hdr + 1);
3751 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3752 write_op(tp, cpu_scratch_base +
3753 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3754 (i * sizeof(u32)),
3755 be32_to_cpu(fw_data[i]));
3756
3757 total_len -= be32_to_cpu(fw_hdr->len);
3758
3759 /* Advance to next fragment */
3760 fw_hdr = (struct tg3_firmware_hdr *)
3761 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3762 } while (total_len > 0);
997b4f13
MC		 3763
3764 err = 0;
3765
3766out:
3767 return err;
3768}
3769
f4bffb28
NS		 3770/* tp->lock is held. */
3771static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3772{
3773 int i;
3774 const int iters = 5;
3775
3776 tw32(cpu_base + CPU_STATE, 0xffffffff);
3777 tw32_f(cpu_base + CPU_PC, pc);
3778
3779 for (i = 0; i < iters; i++) {
3780 if (tr32(cpu_base + CPU_PC) == pc)
3781 break;
3782 tw32(cpu_base + CPU_STATE, 0xffffffff);
3783 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3784 tw32_f(cpu_base + CPU_PC, pc);
3785 udelay(1000);
3786 }
3787
3788 return (i == iters) ? -EBUSY : 0;
3789}
3790
997b4f13
MC		 3791/* tp->lock is held. */
3792static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3793{
77997ea3 3794 const struct tg3_firmware_hdr *fw_hdr;
f4bffb28 3795 int err;
997b4f13 3796
77997ea3 3797 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3798
3799 /* Firmware blob starts with version numbers, followed by
3800 start address and length. We are setting complete length.
3801 length = end_address_of_bss - start_address_of_text.
3802 Remainder is the blob to be loaded contiguously
3803 from start address. */
3804
997b4f13
MC		 3805 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3806 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
77997ea3 3807 fw_hdr);
997b4f13
MC		 3808 if (err)
3809 return err;
3810
3811 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3812 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
77997ea3 3813 fw_hdr);
997b4f13
MC		 3814 if (err)
3815 return err;
3816
3817 /* Now startup only the RX cpu. */
77997ea3
NS		 3818 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3819 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3820 if (err) {
997b4f13
MC		 3821 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3822 "should be %08x\n", __func__,
77997ea3
NS		 3823 tr32(RX_CPU_BASE + CPU_PC),
3824 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3825 return -ENODEV;
3826 }
837c45bb
NS		 3827
3828 tg3_rxcpu_resume(tp);
997b4f13
MC		 3829
3830 return 0;
3831}
3832
c4dab506
NS		 3833static int tg3_validate_rxcpu_state(struct tg3 *tp)
3834{
3835 const int iters = 1000;
3836 int i;
3837 u32 val;
3838
3839 /* Wait for boot code to complete initialization and enter service
3840 * loop. It is then safe to download service patches
3841 */
3842 for (i = 0; i < iters; i++) {
3843 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3844 break;
3845
3846 udelay(10);
3847 }
3848
3849 if (i == iters) {
3850 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3851 return -EBUSY;
3852 }
3853
3854 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3855 if (val & 0xff) {
3856 netdev_warn(tp->dev,
3857 "Other patches exist. Not downloading EEE patch\n");
3858 return -EEXIST;
3859 }
3860
3861 return 0;
3862}
3863
3864/* tp->lock is held. */
3865static void tg3_load_57766_firmware(struct tg3 *tp)
3866{
3867 struct tg3_firmware_hdr *fw_hdr;
3868
3869 if (!tg3_flag(tp, NO_NVRAM))
3870 return;
3871
3872 if (tg3_validate_rxcpu_state(tp))
3873 return;
3874
3875 if (!tp->fw)
3876 return;
3877
3878 /* This firmware blob has a different format than older firmware
3879 * releases as given below. The main difference is we have fragmented
3880 * data to be written to non-contiguous locations.
3881 *
3882 * In the beginning we have a firmware header identical to other
3883 * firmware which consists of version, base addr and length. The length
3884 * here is unused and set to 0xffffffff.
3885 *
3886 * This is followed by a series of firmware fragments which are
3887 * individually identical to previous firmware. i.e. they have the
3888 * firmware header and followed by data for that fragment. The version
3889 * field of the individual fragment header is unused.
3890 */
3891
3892 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3893 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3894 return;
3895
3896 if (tg3_rxcpu_pause(tp))
3897 return;
3898
3899 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3900 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3901
3902 tg3_rxcpu_resume(tp);
3903}
3904
997b4f13
MC		 3905/* tp->lock is held. */
3906static int tg3_load_tso_firmware(struct tg3 *tp)
3907{
77997ea3 3908 const struct tg3_firmware_hdr *fw_hdr;
997b4f13 3909 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
f4bffb28 3910 int err;
997b4f13 3911
1caf13eb 3912 if (!tg3_flag(tp, FW_TSO))
997b4f13
MC		 3913 return 0;
3914
77997ea3 3915 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3916
3917 /* Firmware blob starts with version numbers, followed by
3918 start address and length. We are setting complete length.
3919 length = end_address_of_bss - start_address_of_text.
3920 Remainder is the blob to be loaded contiguously
3921 from start address. */
3922
997b4f13 3923 cpu_scratch_size = tp->fw_len;
997b4f13 3924
4153577a 3925 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
997b4f13
MC		 3926 cpu_base = RX_CPU_BASE;
3927 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3928 } else {
3929 cpu_base = TX_CPU_BASE;
3930 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3931 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3932 }
3933
3934 err = tg3_load_firmware_cpu(tp, cpu_base,
3935 cpu_scratch_base, cpu_scratch_size,
77997ea3 3936 fw_hdr);
997b4f13
MC		 3937 if (err)
3938 return err;
3939
3940 /* Now startup the cpu. */
77997ea3
NS		 3941 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3942 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3943 if (err) {
997b4f13
MC		 3944 netdev_err(tp->dev,
3945 "%s fails to set CPU PC, is %08x should be %08x\n",
77997ea3
NS		 3946 __func__, tr32(cpu_base + CPU_PC),
3947 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3948 return -ENODEV;
3949 }
837c45bb
NS		 3950
3951 tg3_resume_cpu(tp, cpu_base);
997b4f13
MC		 3952 return 0;
3953}
3954
f022ae62
MC		 3955/* tp->lock is held. */
3956static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3957{
3958 u32 addr_high, addr_low;
3959
3960 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3961 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3962 (mac_addr[4] << 8) | mac_addr[5]);
3963
3964 if (index < 4) {
3965 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3966 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3967 } else {
3968 index -= 4;
3969 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3970 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3971 }
3972}
997b4f13 3973
3f007891 3974/* tp->lock is held. */
953c96e0 3975static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3f007891 3976{
f022ae62 3977 u32 addr_high;
3f007891
MC		 3978 int i;
3979
3f007891
MC		 3980 for (i = 0; i < 4; i++) {
3981 if (i == 1 && skip_mac_1)
3982 continue;
f022ae62 3983 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3f007891
MC		 3984 }
3985
4153577a
JP		 3986 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3987 tg3_asic_rev(tp) == ASIC_REV_5704) {
f022ae62
MC		 3988 for (i = 4; i < 16; i++)
3989 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3f007891
MC		 3990 }
3991
3992 addr_high = (tp->dev->dev_addr[0] +
3993 tp->dev->dev_addr[1] +
3994 tp->dev->dev_addr[2] +
3995 tp->dev->dev_addr[3] +
3996 tp->dev->dev_addr[4] +
3997 tp->dev->dev_addr[5]) &
3998 TX_BACKOFF_SEED_MASK;
3999 tw32(MAC_TX_BACKOFF_SEED, addr_high);
4000}
4001
c866b7ea 4002static void tg3_enable_register_access(struct tg3 *tp)
1da177e4 4003{
c866b7ea
RW		 4004 /*
4005 * Make sure register accesses (indirect or otherwise) will function
4006 * correctly.
1da177e4
LT		 4007 */
4008 pci_write_config_dword(tp->pdev,
c866b7ea
RW		 4009 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4010}
1da177e4 4011
c866b7ea
RW		 4012static int tg3_power_up(struct tg3 *tp)
4013{
bed9829f 4014 int err;
8c6bda1a 4015
bed9829f 4016 tg3_enable_register_access(tp);
1da177e4 4017
bed9829f
MC		 4018 err = pci_set_power_state(tp->pdev, PCI_D0);
4019 if (!err) {
4020 /* Switch out of Vaux if it is a NIC */
4021 tg3_pwrsrc_switch_to_vmain(tp);
4022 } else {
4023 netdev_err(tp->dev, "Transition to D0 failed\n");
4024 }
1da177e4 4025
bed9829f 4026 return err;
c866b7ea 4027}
1da177e4 4028
953c96e0 4029static int tg3_setup_phy(struct tg3 *, bool);
4b409522 4030
c866b7ea
RW		 4031static int tg3_power_down_prepare(struct tg3 *tp)
4032{
4033 u32 misc_host_ctrl;
4034 bool device_should_wake, do_low_power;
4035
4036 tg3_enable_register_access(tp);
5e7dfd0f
MC		 4037
4038 /* Restore the CLKREQ setting. */
0f49bfbd
JL		 4039 if (tg3_flag(tp, CLKREQ_BUG))
4040 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4041 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 4042
1da177e4
LT		 4043 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4044 tw32(TG3PCI_MISC_HOST_CTRL,
4045 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4046
c866b7ea 4047 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
63c3a66f 4048 tg3_flag(tp, WOL_ENABLE);
05ac4cb7 4049
63c3a66f 4050 if (tg3_flag(tp, USE_PHYLIB)) {
0a459aac 4051 do_low_power = false;
f07e9af3 4052 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
80096068 4053 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
b02fd9e3 4054 struct phy_device *phydev;
0a459aac 4055 u32 phyid, advertising;
b02fd9e3 4056
ead2402c 4057 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 4058
80096068 4059 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
b02fd9e3 4060
c6700ce2
MC		 4061 tp->link_config.speed = phydev->speed;
4062 tp->link_config.duplex = phydev->duplex;
4063 tp->link_config.autoneg = phydev->autoneg;
4064 tp->link_config.advertising = phydev->advertising;
b02fd9e3
MC		 4065
4066 advertising = ADVERTISED_TP |
4067 ADVERTISED_Pause |
4068 ADVERTISED_Autoneg |
4069 ADVERTISED_10baseT_Half;
4070
63c3a66f
JP		 4071 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4072 if (tg3_flag(tp, WOL_SPEED_100MB))
b02fd9e3
MC		 4073 advertising |=
4074 ADVERTISED_100baseT_Half |
4075 ADVERTISED_100baseT_Full |
4076 ADVERTISED_10baseT_Full;
4077 else
4078 advertising |= ADVERTISED_10baseT_Full;
4079 }
4080
4081 phydev->advertising = advertising;
4082
4083 phy_start_aneg(phydev);
0a459aac
MC		 4084
4085 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 4086 if (phyid != PHY_ID_BCMAC131) {
4087 phyid &= PHY_BCM_OUI_MASK;
4088 if (phyid == PHY_BCM_OUI_1 ||
4089 phyid == PHY_BCM_OUI_2 ||
4090 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 4091 do_low_power = true;
4092 }
b02fd9e3 4093 }
dd477003 4094 } else {
2023276e 4095 do_low_power = true;
0a459aac 4096
c6700ce2 4097 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
80096068 4098 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
1da177e4 4099
2855b9fe 4100 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
953c96e0 4101 tg3_setup_phy(tp, false);
1da177e4
LT		 4102 }
4103
4153577a 4104 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 4105 u32 val;
4106
4107 val = tr32(GRC_VCPU_EXT_CTRL);
4108 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
63c3a66f 4109 } else if (!tg3_flag(tp, ENABLE_ASF)) {
6921d201
MC		 4110 int i;
4111 u32 val;
4112
4113 for (i = 0; i < 200; i++) {
4114 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4115 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4116 break;
4117 msleep(1);
4118 }
4119 }
63c3a66f 4120 if (tg3_flag(tp, WOL_CAP))
a85feb8c
GZ		 4121 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4122 WOL_DRV_STATE_SHUTDOWN |
4123 WOL_DRV_WOL |
4124 WOL_SET_MAGIC_PKT);
6921d201 4125
05ac4cb7 4126 if (device_should_wake) {
1da177e4
LT		 4127 u32 mac_mode;
4128
f07e9af3 4129 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
b4bd2929
MC		 4130 if (do_low_power &&
4131 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4132 tg3_phy_auxctl_write(tp,
4133 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4134 MII_TG3_AUXCTL_PCTL_WOL_EN |
4135 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4136 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
dd477003
MC		 4137 udelay(40);
4138 }
1da177e4 4139
f07e9af3 4140 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3f7045c1 4141 mac_mode = MAC_MODE_PORT_MODE_GMII;
942d1af0
NS		 4142 else if (tp->phy_flags &
4143 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4144 if (tp->link_config.active_speed == SPEED_1000)
4145 mac_mode = MAC_MODE_PORT_MODE_GMII;
4146 else
4147 mac_mode = MAC_MODE_PORT_MODE_MII;
4148 } else
3f7045c1 4149 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 4150
e8f3f6ca 4151 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4153577a 4152 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
63c3a66f 4153 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
e8f3f6ca
MC		 4154 SPEED_100 : SPEED_10;
4155 if (tg3_5700_link_polarity(tp, speed))
4156 mac_mode |= MAC_MODE_LINK_POLARITY;
4157 else
4158 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4159 }
1da177e4
LT		 4160 } else {
4161 mac_mode = MAC_MODE_PORT_MODE_TBI;
4162 }
4163
63c3a66f 4164 if (!tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 4165 tw32(MAC_LED_CTRL, tp->led_ctrl);
4166
05ac4cb7 4167 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
63c3a66f
JP		 4168 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4169 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
05ac4cb7 4170 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 4171
63c3a66f 4172 if (tg3_flag(tp, ENABLE_APE))
d2394e6b
MC		 4173 mac_mode |= MAC_MODE_APE_TX_EN |
4174 MAC_MODE_APE_RX_EN |
4175 MAC_MODE_TDE_ENABLE;
3bda1258 4176
1da177e4
LT		 4177 tw32_f(MAC_MODE, mac_mode);
4178 udelay(100);
4179
4180 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4181 udelay(10);
4182 }
4183
63c3a66f 4184 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4153577a
JP		 4185 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4186 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 4187 u32 base_val;
4188
4189 base_val = tp->pci_clock_ctrl;
4190 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4191 CLOCK_CTRL_TXCLK_DISABLE);
4192
b401e9e2
MC		 4193 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4194 CLOCK_CTRL_PWRDOWN_PLL133, 40);
63c3a66f
JP		 4195 } else if (tg3_flag(tp, 5780_CLASS) ||
4196 tg3_flag(tp, CPMU_PRESENT) ||
4153577a 4197 tg3_asic_rev(tp) == ASIC_REV_5906) {
4cf78e4f 4198 /* do nothing */
63c3a66f 4199 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
1da177e4
LT		 4200 u32 newbits1, newbits2;
4201
4153577a
JP		 4202 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4203 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4204 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4205 CLOCK_CTRL_TXCLK_DISABLE |
4206 CLOCK_CTRL_ALTCLK);
4207 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
63c3a66f 4208 } else if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4209 newbits1 = CLOCK_CTRL_625_CORE;
4210 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4211 } else {
4212 newbits1 = CLOCK_CTRL_ALTCLK;
4213 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4214 }
4215
b401e9e2
MC		 4216 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4217 40);
1da177e4 4218
b401e9e2
MC		 4219 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4220 40);
1da177e4 4221
63c3a66f 4222 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4223 u32 newbits3;
4224
4153577a
JP		 4225 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4226 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4227 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4228 CLOCK_CTRL_TXCLK_DISABLE |
4229 CLOCK_CTRL_44MHZ_CORE);
4230 } else {
4231 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4232 }
4233
b401e9e2
MC		 4234 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4235 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 4236 }
4237 }
4238
63c3a66f 4239 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
0a459aac 4240 tg3_power_down_phy(tp, do_low_power);
6921d201 4241
cd0d7228 4242 tg3_frob_aux_power(tp, true);
1da177e4
LT		 4243
4244 /* Workaround for unstable PLL clock */
7e6c63f0 4245 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4153577a
JP		 4246 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4247 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
1da177e4
LT		 4248 u32 val = tr32(0x7d00);
4249
4250 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4251 tw32(0x7d00, val);
63c3a66f 4252 if (!tg3_flag(tp, ENABLE_ASF)) {
ec41c7df
MC		 4253 int err;
4254
4255 err = tg3_nvram_lock(tp);
1da177e4 4256 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 4257 if (!err)
4258 tg3_nvram_unlock(tp);
6921d201 4259 }
1da177e4
LT		 4260 }
4261
bbadf503
MC		 4262 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4263
2e460fc0
NS		 4264 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4265
c866b7ea
RW		 4266 return 0;
4267}
12dac075 4268
c866b7ea
RW		 4269static void tg3_power_down(struct tg3 *tp)
4270{
63c3a66f 4271 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
c866b7ea 4272 pci_set_power_state(tp->pdev, PCI_D3hot);
1da177e4
LT		 4273}
4274
1da177e4
LT		 4275static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4276{
4277 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4278 case MII_TG3_AUX_STAT_10HALF:
4279 *speed = SPEED_10;
4280 *duplex = DUPLEX_HALF;
4281 break;
4282
4283 case MII_TG3_AUX_STAT_10FULL:
4284 *speed = SPEED_10;
4285 *duplex = DUPLEX_FULL;
4286 break;
4287
4288 case MII_TG3_AUX_STAT_100HALF:
4289 *speed = SPEED_100;
4290 *duplex = DUPLEX_HALF;
4291 break;
4292
4293 case MII_TG3_AUX_STAT_100FULL:
4294 *speed = SPEED_100;
4295 *duplex = DUPLEX_FULL;
4296 break;
4297
4298 case MII_TG3_AUX_STAT_1000HALF:
4299 *speed = SPEED_1000;
4300 *duplex = DUPLEX_HALF;
4301 break;
4302
4303 case MII_TG3_AUX_STAT_1000FULL:
4304 *speed = SPEED_1000;
4305 *duplex = DUPLEX_FULL;
4306 break;
4307
4308 default:
f07e9af3 4309 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
715116a1
MC		 4310 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4311 SPEED_10;
4312 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4313 DUPLEX_HALF;
4314 break;
4315 }
e740522e
MC		 4316 *speed = SPEED_UNKNOWN;
4317 *duplex = DUPLEX_UNKNOWN;
1da177e4 4318 break;
855e1111 4319 }
1da177e4
LT		 4320}
4321
42b64a45 4322static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
1da177e4 4323{
42b64a45
MC		 4324 int err = 0;
4325 u32 val, new_adv;
1da177e4 4326
42b64a45 4327 new_adv = ADVERTISE_CSMA;
202ff1c2 4328 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
f88788f0 4329 new_adv |= mii_advertise_flowctrl(flowctrl);
1da177e4 4330
42b64a45
MC		 4331 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4332 if (err)
4333 goto done;
ba4d07a8 4334
4f272096
MC		 4335 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4336 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
ba4d07a8 4337
4153577a
JP		 4338 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4339 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4f272096 4340 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
ba4d07a8 4341
4f272096
MC		 4342 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4343 if (err)
4344 goto done;
4345 }
1da177e4 4346
42b64a45
MC		 4347 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4348 goto done;
52b02d04 4349
42b64a45
MC		 4350 tw32(TG3_CPMU_EEE_MODE,
4351 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
52b02d04 4352
daf3ec68 4353 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
42b64a45
MC		 4354 if (!err) {
4355 u32 err2;
52b02d04 4356
b715ce94
MC		 4357 val = 0;
4358 /* Advertise 100-BaseTX EEE ability */
4359 if (advertise & ADVERTISED_100baseT_Full)
4360 val |= MDIO_AN_EEE_ADV_100TX;
4361 /* Advertise 1000-BaseT EEE ability */
4362 if (advertise & ADVERTISED_1000baseT_Full)
4363 val |= MDIO_AN_EEE_ADV_1000T;
9e2ecbeb
NS		 4364
4365 if (!tp->eee.eee_enabled) {
4366 val = 0;
4367 tp->eee.advertised = 0;
4368 } else {
4369 tp->eee.advertised = advertise &
4370 (ADVERTISED_100baseT_Full |
4371 ADVERTISED_1000baseT_Full);
4372 }
4373
b715ce94
MC		 4374 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4375 if (err)
4376 val = 0;
4377
4153577a 4378 switch (tg3_asic_rev(tp)) {
21a00ab2
MC		 4379 case ASIC_REV_5717:
4380 case ASIC_REV_57765:
55086ad9 4381 case ASIC_REV_57766:
21a00ab2 4382 case ASIC_REV_5719:
b715ce94
MC		 4383 /* If we advertised any eee advertisements above... */
4384 if (val)
4385 val = MII_TG3_DSP_TAP26_ALNOKO |
4386 MII_TG3_DSP_TAP26_RMRXSTO |
4387 MII_TG3_DSP_TAP26_OPCSINPT;
21a00ab2 4388 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
be671947
MC		 4389 /* Fall through */
4390 case ASIC_REV_5720:
c65a17f4 4391 case ASIC_REV_5762:
be671947
MC		 4392 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4393 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4394 MII_TG3_DSP_CH34TP2_HIBW01);
21a00ab2 4395 }
52b02d04 4396
daf3ec68 4397 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
42b64a45
MC		 4398 if (!err)
4399 err = err2;
4400 }
4401
4402done:
4403 return err;
4404}
4405
4406static void tg3_phy_copper_begin(struct tg3 *tp)
4407{
d13ba512
MC		 4408 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4409 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4410 u32 adv, fc;
4411
942d1af0
NS		 4412 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4413 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
d13ba512
MC		 4414 adv = ADVERTISED_10baseT_Half |
4415 ADVERTISED_10baseT_Full;
4416 if (tg3_flag(tp, WOL_SPEED_100MB))
4417 adv |= ADVERTISED_100baseT_Half |
4418 ADVERTISED_100baseT_Full;
7c786065
NS		 4419 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4420 if (!(tp->phy_flags &
4421 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4422 adv |= ADVERTISED_1000baseT_Half;
4423 adv |= ADVERTISED_1000baseT_Full;
4424 }
d13ba512
MC		 4425
4426 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
42b64a45 4427 } else {
d13ba512
MC		 4428 adv = tp->link_config.advertising;
4429 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4430 adv &= ~(ADVERTISED_1000baseT_Half |
4431 ADVERTISED_1000baseT_Full);
4432
4433 fc = tp->link_config.flowctrl;
52b02d04 4434 }
52b02d04 4435
d13ba512 4436 tg3_phy_autoneg_cfg(tp, adv, fc);
52b02d04 4437
942d1af0
NS		 4438 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4439 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4440 /* Normally during power down we want to autonegotiate
4441 * the lowest possible speed for WOL. However, to avoid
4442 * link flap, we leave it untouched.
4443 */
4444 return;
4445 }
4446
d13ba512
MC		 4447 tg3_writephy(tp, MII_BMCR,
4448 BMCR_ANENABLE | BMCR_ANRESTART);
4449 } else {
4450 int i;
1da177e4
LT		 4451 u32 bmcr, orig_bmcr;
4452
4453 tp->link_config.active_speed = tp->link_config.speed;
4454 tp->link_config.active_duplex = tp->link_config.duplex;
4455
7c6cdead
NS		 4456 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4457 /* With autoneg disabled, 5715 only links up when the
4458 * advertisement register has the configured speed
4459 * enabled.
4460 */
4461 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4462 }
4463
1da177e4
LT		 4464 bmcr = 0;
4465 switch (tp->link_config.speed) {
4466 default:
4467 case SPEED_10:
4468 break;
4469
4470 case SPEED_100:
4471 bmcr |= BMCR_SPEED100;
4472 break;
4473
4474 case SPEED_1000:
221c5637 4475 bmcr |= BMCR_SPEED1000;
1da177e4 4476 break;
855e1111 4477 }
1da177e4
LT		 4478
4479 if (tp->link_config.duplex == DUPLEX_FULL)
4480 bmcr |= BMCR_FULLDPLX;
4481
4482 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4483 (bmcr != orig_bmcr)) {
4484 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4485 for (i = 0; i < 1500; i++) {
4486 u32 tmp;
4487
4488 udelay(10);
4489 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4490 tg3_readphy(tp, MII_BMSR, &tmp))
4491 continue;
4492 if (!(tmp & BMSR_LSTATUS)) {
4493 udelay(40);
4494 break;
4495 }
4496 }
4497 tg3_writephy(tp, MII_BMCR, bmcr);
4498 udelay(40);
4499 }
1da177e4
LT		 4500 }
4501}
4502
fdad8de4
NS		 4503static int tg3_phy_pull_config(struct tg3 *tp)
4504{
4505 int err;
4506 u32 val;
4507
4508 err = tg3_readphy(tp, MII_BMCR, &val);
4509 if (err)
4510 goto done;
4511
4512 if (!(val & BMCR_ANENABLE)) {
4513 tp->link_config.autoneg = AUTONEG_DISABLE;
4514 tp->link_config.advertising = 0;
4515 tg3_flag_clear(tp, PAUSE_AUTONEG);
4516
4517 err = -EIO;
4518
4519 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4520 case 0:
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4522 goto done;
4523
4524 tp->link_config.speed = SPEED_10;
4525 break;
4526 case BMCR_SPEED100:
4527 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4528 goto done;
4529
4530 tp->link_config.speed = SPEED_100;
4531 break;
4532 case BMCR_SPEED1000:
4533 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4534 tp->link_config.speed = SPEED_1000;
4535 break;
4536 }
4537 /* Fall through */
4538 default:
4539 goto done;
4540 }
4541
4542 if (val & BMCR_FULLDPLX)
4543 tp->link_config.duplex = DUPLEX_FULL;
4544 else
4545 tp->link_config.duplex = DUPLEX_HALF;
4546
4547 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4548
4549 err = 0;
4550 goto done;
4551 }
4552
4553 tp->link_config.autoneg = AUTONEG_ENABLE;
4554 tp->link_config.advertising = ADVERTISED_Autoneg;
4555 tg3_flag_set(tp, PAUSE_AUTONEG);
4556
4557 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4558 u32 adv;
4559
4560 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4561 if (err)
4562 goto done;
4563
4564 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4565 tp->link_config.advertising |= adv | ADVERTISED_TP;
4566
4567 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4568 } else {
4569 tp->link_config.advertising |= ADVERTISED_FIBRE;
4570 }
4571
4572 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4573 u32 adv;
4574
4575 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4576 err = tg3_readphy(tp, MII_CTRL1000, &val);
4577 if (err)
4578 goto done;
4579
4580 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4581 } else {
4582 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4583 if (err)
4584 goto done;
4585
4586 adv = tg3_decode_flowctrl_1000X(val);
4587 tp->link_config.flowctrl = adv;
4588
4589 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4590 adv = mii_adv_to_ethtool_adv_x(val);
4591 }
4592
4593 tp->link_config.advertising |= adv;
4594 }
4595
4596done:
4597 return err;
4598}
4599
1da177e4
LT		 4600static int tg3_init_5401phy_dsp(struct tg3 *tp)
4601{
4602 int err;
4603
4604 /* Turn off tap power management. */
4605 /* Set Extended packet length bit */
b4bd2929 4606 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
1da177e4 4607
6ee7c0a0
MC		 4608 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4609 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4610 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4611 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4612 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
1da177e4
LT		 4613
4614 udelay(40);
4615
4616 return err;
4617}
4618
ed1ff5c3
NS		 4619static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4620{
5b6c273a 4621 struct ethtool_eee eee;
ed1ff5c3
NS		 4622
4623 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4624 return true;
4625
5b6c273a 4626 tg3_eee_pull_config(tp, &eee);
ed1ff5c3 4627
5b6c273a
NS		 4628 if (tp->eee.eee_enabled) {
4629 if (tp->eee.advertised != eee.advertised ||
4630 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4631 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4632 return false;
4633 } else {
4634 /* EEE is disabled but we're advertising */
4635 if (eee.advertised)
4636 return false;
4637 }
ed1ff5c3
NS		 4638
4639 return true;
4640}
4641
e2bf73e7 4642static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
1da177e4 4643{
e2bf73e7 4644 u32 advmsk, tgtadv, advertising;
3600d918 4645
e2bf73e7
MC		 4646 advertising = tp->link_config.advertising;
4647 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
1da177e4 4648
e2bf73e7
MC		 4649 advmsk = ADVERTISE_ALL;
4650 if (tp->link_config.active_duplex == DUPLEX_FULL) {
f88788f0 4651 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
e2bf73e7
MC		 4652 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4653 }
1da177e4 4654
e2bf73e7
MC		 4655 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4656 return false;
4657
4658 if ((*lcladv & advmsk) != tgtadv)
4659 return false;
b99d2a57 4660
f07e9af3 4661 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1da177e4
LT		 4662 u32 tg3_ctrl;
4663
e2bf73e7 4664 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
3600d918 4665
221c5637 4666 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
e2bf73e7 4667 return false;
1da177e4 4668
3198e07f 4669 if (tgtadv &&
4153577a
JP		 4670 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4671 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
3198e07f
MC		 4672 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4673 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4674 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4675 } else {
4676 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4677 }
4678
e2bf73e7
MC		 4679 if (tg3_ctrl != tgtadv)
4680 return false;
ef167e27
MC		 4681 }
4682
e2bf73e7 4683 return true;
ef167e27
MC		 4684}
4685
859edb26
MC		 4686static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4687{
4688 u32 lpeth = 0;
4689
4690 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4691 u32 val;
4692
4693 if (tg3_readphy(tp, MII_STAT1000, &val))
4694 return false;
4695
4696 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4697 }
4698
4699 if (tg3_readphy(tp, MII_LPA, rmtadv))
4700 return false;
4701
4702 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4703 tp->link_config.rmt_adv = lpeth;
4704
4705 return true;
4706}
4707
953c96e0 4708static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
f4a46d1f
NNS		 4709{
4710 if (curr_link_up != tp->link_up) {
4711 if (curr_link_up) {
84421b99 4712 netif_carrier_on(tp->dev);
f4a46d1f 4713 } else {
84421b99 4714 netif_carrier_off(tp->dev);
f4a46d1f
NNS		 4715 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4716 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4717 }
4718
4719 tg3_link_report(tp);
4720 return true;
4721 }
4722
4723 return false;
4724}
4725
3310e248
MC		 4726static void tg3_clear_mac_status(struct tg3 *tp)
4727{
4728 tw32(MAC_EVENT, 0);
4729
4730 tw32_f(MAC_STATUS,
4731 MAC_STATUS_SYNC_CHANGED |
4732 MAC_STATUS_CFG_CHANGED |
4733 MAC_STATUS_MI_COMPLETION |
4734 MAC_STATUS_LNKSTATE_CHANGED);
4735 udelay(40);
4736}
4737
9e2ecbeb
NS		 4738static void tg3_setup_eee(struct tg3 *tp)
4739{
4740 u32 val;
4741
4742 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4743 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4744 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4745 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4746
4747 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4748
4749 tw32_f(TG3_CPMU_EEE_CTRL,
4750 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4751
4752 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4753 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4754 TG3_CPMU_EEEMD_LPI_IN_RX |
4755 TG3_CPMU_EEEMD_EEE_ENABLE;
4756
4757 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4758 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4759
4760 if (tg3_flag(tp, ENABLE_APE))
4761 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4762
4763 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4764
4765 tw32_f(TG3_CPMU_EEE_DBTMR1,
4766 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4767 (tp->eee.tx_lpi_timer & 0xffff));
4768
4769 tw32_f(TG3_CPMU_EEE_DBTMR2,
4770 TG3_CPMU_DBTMR2_APE_TX_2047US |
4771 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4772}
4773
953c96e0 4774static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
1da177e4 4775{
953c96e0 4776 bool current_link_up;
f833c4c1 4777 u32 bmsr, val;
ef167e27 4778 u32 lcl_adv, rmt_adv;
1da177e4
LT		 4779 u16 current_speed;
4780 u8 current_duplex;
4781 int i, err;
4782
3310e248 4783 tg3_clear_mac_status(tp);
1da177e4 4784
8ef21428
MC		 4785 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4786 tw32_f(MAC_MI_MODE,
4787 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4788 udelay(80);
4789 }
1da177e4 4790
b4bd2929 4791 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
1da177e4
LT		 4792
4793 /* Some third-party PHYs need to be reset on link going
4794 * down.
4795 */
4153577a
JP		 4796 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4797 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4798 tg3_asic_rev(tp) == ASIC_REV_5705) &&
f4a46d1f 4799 tp->link_up) {
1da177e4
LT		 4800 tg3_readphy(tp, MII_BMSR, &bmsr);
4801 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4802 !(bmsr & BMSR_LSTATUS))
953c96e0 4803 force_reset = true;
1da177e4
LT		 4804 }
4805 if (force_reset)
4806 tg3_phy_reset(tp);
4807
79eb6904 4808 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 4809 tg3_readphy(tp, MII_BMSR, &bmsr);
4810 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
63c3a66f 4811 !tg3_flag(tp, INIT_COMPLETE))
1da177e4
LT		 4812 bmsr = 0;
4813
4814 if (!(bmsr & BMSR_LSTATUS)) {
4815 err = tg3_init_5401phy_dsp(tp);
4816 if (err)
4817 return err;
4818
4819 tg3_readphy(tp, MII_BMSR, &bmsr);
4820 for (i = 0; i < 1000; i++) {
4821 udelay(10);
4822 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4823 (bmsr & BMSR_LSTATUS)) {
4824 udelay(40);
4825 break;
4826 }
4827 }
4828
79eb6904
MC		 4829 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4830 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 4831 !(bmsr & BMSR_LSTATUS) &&
4832 tp->link_config.active_speed == SPEED_1000) {
4833 err = tg3_phy_reset(tp);
4834 if (!err)
4835 err = tg3_init_5401phy_dsp(tp);
4836 if (err)
4837 return err;
4838 }
4839 }
4153577a
JP		 4840 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4841 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
1da177e4
LT		 4842 /* 5701 {A0,B0} CRC bug workaround */
4843 tg3_writephy(tp, 0x15, 0x0a75);
f08aa1a8
MC		 4844 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4845 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4846 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
1da177e4
LT		 4847 }
4848
4849 /* Clear pending interrupts... */
f833c4c1
MC		 4850 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4851 tg3_readphy(tp, MII_TG3_ISTAT, &val);
1da177e4 4852
f07e9af3 4853 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
1da177e4 4854 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
f07e9af3 4855 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
1da177e4
LT		 4856 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4857
4153577a
JP		 4858 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4859 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4860 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4861 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4862 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4863 else
4864 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4865 }
4866
953c96e0 4867 current_link_up = false;
e740522e
MC		 4868 current_speed = SPEED_UNKNOWN;
4869 current_duplex = DUPLEX_UNKNOWN;
e348c5e7 4870 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
859edb26 4871 tp->link_config.rmt_adv = 0;
1da177e4 4872
f07e9af3 4873 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
15ee95c3
MC		 4874 err = tg3_phy_auxctl_read(tp,
4875 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4876 &val);
4877 if (!err && !(val & (1 << 10))) {
b4bd2929
MC		 4878 tg3_phy_auxctl_write(tp,
4879 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4880 val | (1 << 10));
1da177e4
LT		 4881 goto relink;
4882 }
4883 }
4884
4885 bmsr = 0;
4886 for (i = 0; i < 100; i++) {
4887 tg3_readphy(tp, MII_BMSR, &bmsr);
4888 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4889 (bmsr & BMSR_LSTATUS))
4890 break;
4891 udelay(40);
4892 }
4893
4894 if (bmsr & BMSR_LSTATUS) {
4895 u32 aux_stat, bmcr;
4896
4897 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4898 for (i = 0; i < 2000; i++) {
4899 udelay(10);
4900 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4901 aux_stat)
4902 break;
4903 }
4904
4905 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4906 &current_speed,
4907 &current_duplex);
4908
4909 bmcr = 0;
4910 for (i = 0; i < 200; i++) {
4911 tg3_readphy(tp, MII_BMCR, &bmcr);
4912 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4913 continue;
4914 if (bmcr && bmcr != 0x7fff)
4915 break;
4916 udelay(10);
4917 }
4918
ef167e27
MC		 4919 lcl_adv = 0;
4920 rmt_adv = 0;
1da177e4 4921
ef167e27
MC		 4922 tp->link_config.active_speed = current_speed;
4923 tp->link_config.active_duplex = current_duplex;
4924
4925 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
ed1ff5c3
NS		 4926 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4927
ef167e27 4928 if ((bmcr & BMCR_ANENABLE) &&
ed1ff5c3 4929 eee_config_ok &&
e2bf73e7 4930 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
859edb26 4931 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
953c96e0 4932 current_link_up = true;
ed1ff5c3
NS		 4933
4934 /* EEE settings changes take effect only after a phy
4935 * reset. If we have skipped a reset due to Link Flap
4936 * Avoidance being enabled, do it now.
4937 */
4938 if (!eee_config_ok &&
4939 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
5b6c273a
NS		 4940 !force_reset) {
4941 tg3_setup_eee(tp);
ed1ff5c3 4942 tg3_phy_reset(tp);
5b6c273a 4943 }
1da177e4
LT		 4944 } else {
4945 if (!(bmcr & BMCR_ANENABLE) &&
4946 tp->link_config.speed == current_speed &&
f0fcd7a9 4947 tp->link_config.duplex == current_duplex) {
953c96e0 4948 current_link_up = true;
1da177e4
LT		 4949 }
4950 }
4951
953c96e0 4952 if (current_link_up &&
e348c5e7
MC		 4953 tp->link_config.active_duplex == DUPLEX_FULL) {
4954 u32 reg, bit;
4955
4956 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4957 reg = MII_TG3_FET_GEN_STAT;
4958 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4959 } else {
4960 reg = MII_TG3_EXT_STAT;
4961 bit = MII_TG3_EXT_STAT_MDIX;
4962 }
4963
4964 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4965 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4966
ef167e27 4967 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
e348c5e7 4968 }
1da177e4
LT		 4969 }
4970
1da177e4 4971relink:
953c96e0 4972 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
1da177e4
LT		 4973 tg3_phy_copper_begin(tp);
4974
7e6c63f0 4975 if (tg3_flag(tp, ROBOSWITCH)) {
953c96e0 4976 current_link_up = true;
7e6c63f0
HM		 4977 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4978 current_speed = SPEED_1000;
4979 current_duplex = DUPLEX_FULL;
4980 tp->link_config.active_speed = current_speed;
4981 tp->link_config.active_duplex = current_duplex;
4982 }
4983
f833c4c1 4984 tg3_readphy(tp, MII_BMSR, &bmsr);
06c03c02
MB		 4985 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4986 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
953c96e0 4987 current_link_up = true;
1da177e4
LT		 4988 }
4989
4990 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
953c96e0 4991 if (current_link_up) {
1da177e4
LT		 4992 if (tp->link_config.active_speed == SPEED_100 ||
4993 tp->link_config.active_speed == SPEED_10)
4994 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4995 else
4996 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
f07e9af3 4997 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7f97a4bd
MC		 4998 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4999 else
1da177e4
LT		 5000 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5001
7e6c63f0
HM		 5002 /* In order for the 5750 core in BCM4785 chip to work properly
5003 * in RGMII mode, the Led Control Register must be set up.
5004 */
5005 if (tg3_flag(tp, RGMII_MODE)) {
5006 u32 led_ctrl = tr32(MAC_LED_CTRL);
5007 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5008
5009 if (tp->link_config.active_speed == SPEED_10)
5010 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5011 else if (tp->link_config.active_speed == SPEED_100)
5012 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5013 LED_CTRL_100MBPS_ON);
5014 else if (tp->link_config.active_speed == SPEED_1000)
5015 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5016 LED_CTRL_1000MBPS_ON);
5017
5018 tw32(MAC_LED_CTRL, led_ctrl);
5019 udelay(40);
5020 }
5021
1da177e4
LT		 5022 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5023 if (tp->link_config.active_duplex == DUPLEX_HALF)
5024 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5025
4153577a 5026 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
953c96e0 5027 if (current_link_up &&
e8f3f6ca 5028 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 5029 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 5030 else
5031 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 5032 }
5033
5034 /* ??? Without this setting Netgear GA302T PHY does not
5035 * ??? send/receive packets...
5036 */
79eb6904 5037 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4153577a 5038 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
1da177e4
LT		 5039 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5040 tw32_f(MAC_MI_MODE, tp->mi_mode);
5041 udelay(80);
5042 }
5043
5044 tw32_f(MAC_MODE, tp->mac_mode);
5045 udelay(40);
5046
52b02d04
MC		 5047 tg3_phy_eee_adjust(tp, current_link_up);
5048
63c3a66f 5049 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 5050 /* Polled via timer. */
5051 tw32_f(MAC_EVENT, 0);
5052 } else {
5053 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5054 }
5055 udelay(40);
5056
4153577a 5057 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
953c96e0 5058 current_link_up &&
1da177e4 5059 tp->link_config.active_speed == SPEED_1000 &&
63c3a66f 5060 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
1da177e4
LT		 5061 udelay(120);
5062 tw32_f(MAC_STATUS,
5063 (MAC_STATUS_SYNC_CHANGED |
5064 MAC_STATUS_CFG_CHANGED));
5065 udelay(40);
5066 tg3_write_mem(tp,
5067 NIC_SRAM_FIRMWARE_MBOX,
5068 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5069 }
5070
5e7dfd0f 5071 /* Prevent send BD corruption. */
63c3a66f 5072 if (tg3_flag(tp, CLKREQ_BUG)) {
5e7dfd0f
MC		 5073 if (tp->link_config.active_speed == SPEED_100 ||
5074 tp->link_config.active_speed == SPEED_10)
0f49bfbd
JL		 5075 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5076 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 5077 else
0f49bfbd
JL		 5078 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5079 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f
MC		 5080 }
5081
f4a46d1f 5082 tg3_test_and_report_link_chg(tp, current_link_up);
1da177e4
LT		 5083
5084 return 0;
5085}
5086
5087struct tg3_fiber_aneginfo {
5088 int state;
5089#define ANEG_STATE_UNKNOWN 0
5090#define ANEG_STATE_AN_ENABLE 1
5091#define ANEG_STATE_RESTART_INIT 2
5092#define ANEG_STATE_RESTART 3
5093#define ANEG_STATE_DISABLE_LINK_OK 4
5094#define ANEG_STATE_ABILITY_DETECT_INIT 5
5095#define ANEG_STATE_ABILITY_DETECT 6
5096#define ANEG_STATE_ACK_DETECT_INIT 7
5097#define ANEG_STATE_ACK_DETECT 8
5098#define ANEG_STATE_COMPLETE_ACK_INIT 9
5099#define ANEG_STATE_COMPLETE_ACK 10
5100#define ANEG_STATE_IDLE_DETECT_INIT 11
5101#define ANEG_STATE_IDLE_DETECT 12
5102#define ANEG_STATE_LINK_OK 13
5103#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5104#define ANEG_STATE_NEXT_PAGE_WAIT 15
5105
5106 u32 flags;
5107#define MR_AN_ENABLE 0x00000001
5108#define MR_RESTART_AN 0x00000002
5109#define MR_AN_COMPLETE 0x00000004
5110#define MR_PAGE_RX 0x00000008
5111#define MR_NP_LOADED 0x00000010
5112#define MR_TOGGLE_TX 0x00000020
5113#define MR_LP_ADV_FULL_DUPLEX 0x00000040
5114#define MR_LP_ADV_HALF_DUPLEX 0x00000080
5115#define MR_LP_ADV_SYM_PAUSE 0x00000100
5116#define MR_LP_ADV_ASYM_PAUSE 0x00000200
5117#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5118#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5119#define MR_LP_ADV_NEXT_PAGE 0x00001000
5120#define MR_TOGGLE_RX 0x00002000
5121#define MR_NP_RX 0x00004000
5122
5123#define MR_LINK_OK 0x80000000
5124
5125 unsigned long link_time, cur_time;
5126
5127 u32 ability_match_cfg;
5128 int ability_match_count;
5129
5130 char ability_match, idle_match, ack_match;
5131
5132 u32 txconfig, rxconfig;
5133#define ANEG_CFG_NP 0x00000080
5134#define ANEG_CFG_ACK 0x00000040
5135#define ANEG_CFG_RF2 0x00000020
5136#define ANEG_CFG_RF1 0x00000010
5137#define ANEG_CFG_PS2 0x00000001
5138#define ANEG_CFG_PS1 0x00008000
5139#define ANEG_CFG_HD 0x00004000
5140#define ANEG_CFG_FD 0x00002000
5141#define ANEG_CFG_INVAL 0x00001f06
5142
5143};
5144#define ANEG_OK 0
5145#define ANEG_DONE 1
5146#define ANEG_TIMER_ENAB 2
5147#define ANEG_FAILED -1
5148
5149#define ANEG_STATE_SETTLE_TIME 10000
5150
5151static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5152 struct tg3_fiber_aneginfo *ap)
5153{
5be73b47 5154 u16 flowctrl;
1da177e4
LT		 5155 unsigned long delta;
5156 u32 rx_cfg_reg;
5157 int ret;
5158
5159 if (ap->state == ANEG_STATE_UNKNOWN) {
5160 ap->rxconfig = 0;
5161 ap->link_time = 0;
5162 ap->cur_time = 0;
5163 ap->ability_match_cfg = 0;
5164 ap->ability_match_count = 0;
5165 ap->ability_match = 0;
5166 ap->idle_match = 0;
5167 ap->ack_match = 0;
5168 }
5169 ap->cur_time++;
5170
5171 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5172 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5173
5174 if (rx_cfg_reg != ap->ability_match_cfg) {
5175 ap->ability_match_cfg = rx_cfg_reg;
5176 ap->ability_match = 0;
5177 ap->ability_match_count = 0;
5178 } else {
5179 if (++ap->ability_match_count > 1) {
5180 ap->ability_match = 1;
5181 ap->ability_match_cfg = rx_cfg_reg;
5182 }
5183 }
5184 if (rx_cfg_reg & ANEG_CFG_ACK)
5185 ap->ack_match = 1;
5186 else
5187 ap->ack_match = 0;
5188
5189 ap->idle_match = 0;
5190 } else {
5191 ap->idle_match = 1;
5192 ap->ability_match_cfg = 0;
5193 ap->ability_match_count = 0;
5194 ap->ability_match = 0;
5195 ap->ack_match = 0;
5196
5197 rx_cfg_reg = 0;
5198 }
5199
5200 ap->rxconfig = rx_cfg_reg;
5201 ret = ANEG_OK;
5202
33f401ae 5203 switch (ap->state) {
1da177e4
LT		 5204 case ANEG_STATE_UNKNOWN:
5205 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5206 ap->state = ANEG_STATE_AN_ENABLE;
5207
5208 /* fallthru */
5209 case ANEG_STATE_AN_ENABLE:
5210 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5211 if (ap->flags & MR_AN_ENABLE) {
5212 ap->link_time = 0;
5213 ap->cur_time = 0;
5214 ap->ability_match_cfg = 0;
5215 ap->ability_match_count = 0;
5216 ap->ability_match = 0;
5217 ap->idle_match = 0;
5218 ap->ack_match = 0;
5219
5220 ap->state = ANEG_STATE_RESTART_INIT;
5221 } else {
5222 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5223 }
5224 break;
5225
5226 case ANEG_STATE_RESTART_INIT:
5227 ap->link_time = ap->cur_time;
5228 ap->flags &= ~(MR_NP_LOADED);
5229 ap->txconfig = 0;
5230 tw32(MAC_TX_AUTO_NEG, 0);
5231 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5232 tw32_f(MAC_MODE, tp->mac_mode);
5233 udelay(40);
5234
5235 ret = ANEG_TIMER_ENAB;
5236 ap->state = ANEG_STATE_RESTART;
5237
5238 /* fallthru */
5239 case ANEG_STATE_RESTART:
5240 delta = ap->cur_time - ap->link_time;
859a5887 5241 if (delta > ANEG_STATE_SETTLE_TIME)
1da177e4 5242 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
859a5887 5243 else
1da177e4 5244 ret = ANEG_TIMER_ENAB;
1da177e4
LT		 5245 break;
5246
5247 case ANEG_STATE_DISABLE_LINK_OK:
5248 ret = ANEG_DONE;
5249 break;
5250
5251 case ANEG_STATE_ABILITY_DETECT_INIT:
5252 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 5253 ap->txconfig = ANEG_CFG_FD;
5254 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5255 if (flowctrl & ADVERTISE_1000XPAUSE)
5256 ap->txconfig |= ANEG_CFG_PS1;
5257 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5258 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 5259 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5260 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5261 tw32_f(MAC_MODE, tp->mac_mode);
5262 udelay(40);
5263
5264 ap->state = ANEG_STATE_ABILITY_DETECT;
5265 break;
5266
5267 case ANEG_STATE_ABILITY_DETECT:
859a5887 5268 if (ap->ability_match != 0 && ap->rxconfig != 0)
1da177e4 5269 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1da177e4
LT		 5270 break;
5271
5272 case ANEG_STATE_ACK_DETECT_INIT:
5273 ap->txconfig |= ANEG_CFG_ACK;
5274 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5275 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5276 tw32_f(MAC_MODE, tp->mac_mode);
5277 udelay(40);
5278
5279 ap->state = ANEG_STATE_ACK_DETECT;
5280
5281 /* fallthru */
5282 case ANEG_STATE_ACK_DETECT:
5283 if (ap->ack_match != 0) {
5284 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5285 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5286 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5287 } else {
5288 ap->state = ANEG_STATE_AN_ENABLE;
5289 }
5290 } else if (ap->ability_match != 0 &&
5291 ap->rxconfig == 0) {
5292 ap->state = ANEG_STATE_AN_ENABLE;
5293 }
5294 break;
5295
5296 case ANEG_STATE_COMPLETE_ACK_INIT:
5297 if (ap->rxconfig & ANEG_CFG_INVAL) {
5298 ret = ANEG_FAILED;
5299 break;
5300 }
5301 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5302 MR_LP_ADV_HALF_DUPLEX |
5303 MR_LP_ADV_SYM_PAUSE |
5304 MR_LP_ADV_ASYM_PAUSE |
5305 MR_LP_ADV_REMOTE_FAULT1 |
5306 MR_LP_ADV_REMOTE_FAULT2 |
5307 MR_LP_ADV_NEXT_PAGE |
5308 MR_TOGGLE_RX |
5309 MR_NP_RX);
5310 if (ap->rxconfig & ANEG_CFG_FD)
5311 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5312 if (ap->rxconfig & ANEG_CFG_HD)
5313 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5314 if (ap->rxconfig & ANEG_CFG_PS1)
5315 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5316 if (ap->rxconfig & ANEG_CFG_PS2)
5317 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5318 if (ap->rxconfig & ANEG_CFG_RF1)
5319 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5320 if (ap->rxconfig & ANEG_CFG_RF2)
5321 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5322 if (ap->rxconfig & ANEG_CFG_NP)
5323 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5324
5325 ap->link_time = ap->cur_time;
5326
5327 ap->flags ^= (MR_TOGGLE_TX);
5328 if (ap->rxconfig & 0x0008)
5329 ap->flags |= MR_TOGGLE_RX;
5330 if (ap->rxconfig & ANEG_CFG_NP)
5331 ap->flags |= MR_NP_RX;
5332 ap->flags |= MR_PAGE_RX;
5333
5334 ap->state = ANEG_STATE_COMPLETE_ACK;
5335 ret = ANEG_TIMER_ENAB;
5336 break;
5337
5338 case ANEG_STATE_COMPLETE_ACK:
5339 if (ap->ability_match != 0 &&
5340 ap->rxconfig == 0) {
5341 ap->state = ANEG_STATE_AN_ENABLE;
5342 break;
5343 }
5344 delta = ap->cur_time - ap->link_time;
5345 if (delta > ANEG_STATE_SETTLE_TIME) {
5346 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5347 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5348 } else {
5349 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5350 !(ap->flags & MR_NP_RX)) {
5351 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5352 } else {
5353 ret = ANEG_FAILED;
5354 }
5355 }
5356 }
5357 break;
5358
5359 case ANEG_STATE_IDLE_DETECT_INIT:
5360 ap->link_time = ap->cur_time;
5361 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5362 tw32_f(MAC_MODE, tp->mac_mode);
5363 udelay(40);
5364
5365 ap->state = ANEG_STATE_IDLE_DETECT;
5366 ret = ANEG_TIMER_ENAB;
5367 break;
5368
5369 case ANEG_STATE_IDLE_DETECT:
5370 if (ap->ability_match != 0 &&
5371 ap->rxconfig == 0) {
5372 ap->state = ANEG_STATE_AN_ENABLE;
5373 break;
5374 }
5375 delta = ap->cur_time - ap->link_time;
5376 if (delta > ANEG_STATE_SETTLE_TIME) {
5377 /* XXX another gem from the Broadcom driver :( */
5378 ap->state = ANEG_STATE_LINK_OK;
5379 }
5380 break;
5381
5382 case ANEG_STATE_LINK_OK:
5383 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5384 ret = ANEG_DONE;
5385 break;
5386
5387 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5388 /* ??? unimplemented */
5389 break;
5390
5391 case ANEG_STATE_NEXT_PAGE_WAIT:
5392 /* ??? unimplemented */
5393 break;
5394
5395 default:
5396 ret = ANEG_FAILED;
5397 break;
855e1111 5398 }
1da177e4
LT		 5399
5400 return ret;
5401}
5402
5be73b47 5403static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 5404{
5405 int res = 0;
5406 struct tg3_fiber_aneginfo aninfo;
5407 int status = ANEG_FAILED;
5408 unsigned int tick;
5409 u32 tmp;
5410
5411 tw32_f(MAC_TX_AUTO_NEG, 0);
5412
5413 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5414 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5415 udelay(40);
5416
5417 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5418 udelay(40);
5419
5420 memset(&aninfo, 0, sizeof(aninfo));
5421 aninfo.flags |= MR_AN_ENABLE;
5422 aninfo.state = ANEG_STATE_UNKNOWN;
5423 aninfo.cur_time = 0;
5424 tick = 0;
5425 while (++tick < 195000) {
5426 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5427 if (status == ANEG_DONE || status == ANEG_FAILED)
5428 break;
5429
5430 udelay(1);
5431 }
5432
5433 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5434 tw32_f(MAC_MODE, tp->mac_mode);
5435 udelay(40);
5436
5be73b47
MC		 5437 *txflags = aninfo.txconfig;
5438 *rxflags = aninfo.flags;
1da177e4
LT		 5439
5440 if (status == ANEG_DONE &&
5441 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5442 MR_LP_ADV_FULL_DUPLEX)))
5443 res = 1;
5444
5445 return res;
5446}
5447
5448static void tg3_init_bcm8002(struct tg3 *tp)
5449{
5450 u32 mac_status = tr32(MAC_STATUS);
5451 int i;
5452
5453 /* Reset when initting first time or we have a link. */
63c3a66f 5454 if (tg3_flag(tp, INIT_COMPLETE) &&
1da177e4
LT		 5455 !(mac_status & MAC_STATUS_PCS_SYNCED))
5456 return;
5457
5458 /* Set PLL lock range. */
5459 tg3_writephy(tp, 0x16, 0x8007);
5460
5461 /* SW reset */
5462 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5463
5464 /* Wait for reset to complete. */
5465 /* XXX schedule_timeout() ... */
5466 for (i = 0; i < 500; i++)
5467 udelay(10);
5468
5469 /* Config mode; select PMA/Ch 1 regs. */
5470 tg3_writephy(tp, 0x10, 0x8411);
5471
5472 /* Enable auto-lock and comdet, select txclk for tx. */
5473 tg3_writephy(tp, 0x11, 0x0a10);
5474
5475 tg3_writephy(tp, 0x18, 0x00a0);
5476 tg3_writephy(tp, 0x16, 0x41ff);
5477
5478 /* Assert and deassert POR. */
5479 tg3_writephy(tp, 0x13, 0x0400);
5480 udelay(40);
5481 tg3_writephy(tp, 0x13, 0x0000);
5482
5483 tg3_writephy(tp, 0x11, 0x0a50);
5484 udelay(40);
5485 tg3_writephy(tp, 0x11, 0x0a10);
5486
5487 /* Wait for signal to stabilize */
5488 /* XXX schedule_timeout() ... */
5489 for (i = 0; i < 15000; i++)
5490 udelay(10);
5491
5492 /* Deselect the channel register so we can read the PHYID
5493 * later.
5494 */
5495 tg3_writephy(tp, 0x10, 0x8011);
5496}
5497
953c96e0 5498static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
1da177e4 5499{
82cd3d11 5500 u16 flowctrl;
953c96e0 5501 bool current_link_up;
1da177e4
LT		 5502 u32 sg_dig_ctrl, sg_dig_status;
5503 u32 serdes_cfg, expected_sg_dig_ctrl;
5504 int workaround, port_a;
1da177e4
LT		 5505
5506 serdes_cfg = 0;
5507 expected_sg_dig_ctrl = 0;
5508 workaround = 0;
5509 port_a = 1;
953c96e0 5510 current_link_up = false;
1da177e4 5511
4153577a
JP		 5512 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5513 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
1da177e4
LT		 5514 workaround = 1;
5515 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5516 port_a = 0;
5517
5518 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5519 /* preserve bits 20-23 for voltage regulator */
5520 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5521 }
5522
5523 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5524
5525 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 5526 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 5527 if (workaround) {
5528 u32 val = serdes_cfg;
5529
5530 if (port_a)
5531 val |= 0xc010000;
5532 else
5533 val |= 0x4010000;
5534 tw32_f(MAC_SERDES_CFG, val);
5535 }
c98f6e3b
MC		 5536
5537 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5538 }
5539 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5540 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5541 current_link_up = true;
1da177e4
LT		 5542 }
5543 goto out;
5544 }
5545
5546 /* Want auto-negotiation. */
c98f6e3b 5547 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 5548
82cd3d11
MC		 5549 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5550 if (flowctrl & ADVERTISE_1000XPAUSE)
5551 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5552 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5553 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 5554
5555 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
f07e9af3 5556 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3d3ebe74
MC		 5557 tp->serdes_counter &&
5558 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5559 MAC_STATUS_RCVD_CFG)) ==
5560 MAC_STATUS_PCS_SYNCED)) {
5561 tp->serdes_counter--;
953c96e0 5562 current_link_up = true;
3d3ebe74
MC		 5563 goto out;
5564 }
5565restart_autoneg:
1da177e4
LT		 5566 if (workaround)
5567 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 5568 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 5569 udelay(5);
5570 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5571
3d3ebe74 5572 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5573 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5574 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5575 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 5576 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 5577 mac_status = tr32(MAC_STATUS);
5578
c98f6e3b 5579 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 5580 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 5581 u32 local_adv = 0, remote_adv = 0;
5582
5583 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5584 local_adv |= ADVERTISE_1000XPAUSE;
5585 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5586 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 5587
c98f6e3b 5588 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 5589 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 5590 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 5591 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5592
859edb26
MC		 5593 tp->link_config.rmt_adv =
5594 mii_adv_to_ethtool_adv_x(remote_adv);
5595
1da177e4 5596 tg3_setup_flow_control(tp, local_adv, remote_adv);
953c96e0 5597 current_link_up = true;
3d3ebe74 5598 tp->serdes_counter = 0;
f07e9af3 5599 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c98f6e3b 5600 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 5601 if (tp->serdes_counter)
5602 tp->serdes_counter--;
1da177e4
LT		 5603 else {
5604 if (workaround) {
5605 u32 val = serdes_cfg;
5606
5607 if (port_a)
5608 val |= 0xc010000;
5609 else
5610 val |= 0x4010000;
5611
5612 tw32_f(MAC_SERDES_CFG, val);
5613 }
5614
c98f6e3b 5615 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5616 udelay(40);
5617
5618 /* Link parallel detection - link is up */
5619 /* only if we have PCS_SYNC and not */
5620 /* receiving config code words */
5621 mac_status = tr32(MAC_STATUS);
5622 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5623 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5624 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5625 current_link_up = true;
f07e9af3
MC		 5626 tp->phy_flags |=
5627 TG3_PHYFLG_PARALLEL_DETECT;
3d3ebe74
MC		 5628 tp->serdes_counter =
5629 SERDES_PARALLEL_DET_TIMEOUT;
5630 } else
5631 goto restart_autoneg;
1da177e4
LT		 5632 }
5633 }
3d3ebe74
MC		 5634 } else {
5635 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5636 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5637 }
5638
5639out:
5640 return current_link_up;
5641}
5642
953c96e0 5643static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
1da177e4 5644{
953c96e0 5645 bool current_link_up = false;
1da177e4 5646
5cf64b8a 5647 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 5648 goto out;
1da177e4
LT		 5649
5650 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 5651 u32 txflags, rxflags;
1da177e4 5652 int i;
6aa20a22 5653
5be73b47
MC		 5654 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5655 u32 local_adv = 0, remote_adv = 0;
1da177e4 5656
5be73b47
MC		 5657 if (txflags & ANEG_CFG_PS1)
5658 local_adv |= ADVERTISE_1000XPAUSE;
5659 if (txflags & ANEG_CFG_PS2)
5660 local_adv |= ADVERTISE_1000XPSE_ASYM;
5661
5662 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5663 remote_adv |= LPA_1000XPAUSE;
5664 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5665 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5666
859edb26
MC		 5667 tp->link_config.rmt_adv =
5668 mii_adv_to_ethtool_adv_x(remote_adv);
5669
1da177e4
LT		 5670 tg3_setup_flow_control(tp, local_adv, remote_adv);
5671
953c96e0 5672 current_link_up = true;
1da177e4
LT		 5673 }
5674 for (i = 0; i < 30; i++) {
5675 udelay(20);
5676 tw32_f(MAC_STATUS,
5677 (MAC_STATUS_SYNC_CHANGED |
5678 MAC_STATUS_CFG_CHANGED));
5679 udelay(40);
5680 if ((tr32(MAC_STATUS) &
5681 (MAC_STATUS_SYNC_CHANGED |
5682 MAC_STATUS_CFG_CHANGED)) == 0)
5683 break;
5684 }
5685
5686 mac_status = tr32(MAC_STATUS);
953c96e0 5687 if (!current_link_up &&
1da177e4
LT		 5688 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5689 !(mac_status & MAC_STATUS_RCVD_CFG))
953c96e0 5690 current_link_up = true;
1da177e4 5691 } else {
5be73b47
MC		 5692 tg3_setup_flow_control(tp, 0, 0);
5693
1da177e4 5694 /* Forcing 1000FD link up. */
953c96e0 5695 current_link_up = true;
1da177e4
LT		 5696
5697 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5698 udelay(40);
e8f3f6ca
MC		 5699
5700 tw32_f(MAC_MODE, tp->mac_mode);
5701 udelay(40);
1da177e4
LT		 5702 }
5703
5704out:
5705 return current_link_up;
5706}
5707
953c96e0 5708static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
1da177e4
LT		 5709{
5710 u32 orig_pause_cfg;
5711 u16 orig_active_speed;
5712 u8 orig_active_duplex;
5713 u32 mac_status;
953c96e0 5714 bool current_link_up;
1da177e4
LT		 5715 int i;
5716
8d018621 5717 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5718 orig_active_speed = tp->link_config.active_speed;
5719 orig_active_duplex = tp->link_config.active_duplex;
5720
63c3a66f 5721 if (!tg3_flag(tp, HW_AUTONEG) &&
f4a46d1f 5722 tp->link_up &&
63c3a66f 5723 tg3_flag(tp, INIT_COMPLETE)) {
1da177e4
LT		 5724 mac_status = tr32(MAC_STATUS);
5725 mac_status &= (MAC_STATUS_PCS_SYNCED |
5726 MAC_STATUS_SIGNAL_DET |
5727 MAC_STATUS_CFG_CHANGED |
5728 MAC_STATUS_RCVD_CFG);
5729 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5730 MAC_STATUS_SIGNAL_DET)) {
5731 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5732 MAC_STATUS_CFG_CHANGED));
5733 return 0;
5734 }
5735 }
5736
5737 tw32_f(MAC_TX_AUTO_NEG, 0);
5738
5739 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5740 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5741 tw32_f(MAC_MODE, tp->mac_mode);
5742 udelay(40);
5743
79eb6904 5744 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 5745 tg3_init_bcm8002(tp);
5746
5747 /* Enable link change event even when serdes polling. */
5748 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5749 udelay(40);
5750
953c96e0 5751 current_link_up = false;
859edb26 5752 tp->link_config.rmt_adv = 0;
1da177e4
LT		 5753 mac_status = tr32(MAC_STATUS);
5754
63c3a66f 5755 if (tg3_flag(tp, HW_AUTONEG))
1da177e4
LT		 5756 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5757 else
5758 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5759
898a56f8 5760 tp->napi[0].hw_status->status =
1da177e4 5761 (SD_STATUS_UPDATED |
898a56f8 5762 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 5763
5764 for (i = 0; i < 100; i++) {
5765 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5766 MAC_STATUS_CFG_CHANGED));
5767 udelay(5);
5768 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 5769 MAC_STATUS_CFG_CHANGED |
5770 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 5771 break;
5772 }
5773
5774 mac_status = tr32(MAC_STATUS);
5775 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
953c96e0 5776 current_link_up = false;
3d3ebe74
MC		 5777 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5778 tp->serdes_counter == 0) {
1da177e4
LT		 5779 tw32_f(MAC_MODE, (tp->mac_mode |
5780 MAC_MODE_SEND_CONFIGS));
5781 udelay(1);
5782 tw32_f(MAC_MODE, tp->mac_mode);
5783 }
5784 }
5785
953c96e0 5786 if (current_link_up) {
1da177e4
LT		 5787 tp->link_config.active_speed = SPEED_1000;
5788 tp->link_config.active_duplex = DUPLEX_FULL;
5789 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5790 LED_CTRL_LNKLED_OVERRIDE |
5791 LED_CTRL_1000MBPS_ON));
5792 } else {
e740522e
MC		 5793 tp->link_config.active_speed = SPEED_UNKNOWN;
5794 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 5795 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5796 LED_CTRL_LNKLED_OVERRIDE |
5797 LED_CTRL_TRAFFIC_OVERRIDE));
5798 }
5799
f4a46d1f 5800 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
8d018621 5801 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5802 if (orig_pause_cfg != now_pause_cfg ||
5803 orig_active_speed != tp->link_config.active_speed ||
5804 orig_active_duplex != tp->link_config.active_duplex)
5805 tg3_link_report(tp);
5806 }
5807
5808 return 0;
5809}
5810
953c96e0 5811static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
747e8f8b 5812{
953c96e0 5813 int err = 0;
747e8f8b 5814 u32 bmsr, bmcr;
85730a63
MC		 5815 u16 current_speed = SPEED_UNKNOWN;
5816 u8 current_duplex = DUPLEX_UNKNOWN;
953c96e0 5817 bool current_link_up = false;
85730a63
MC		 5818 u32 local_adv, remote_adv, sgsr;
5819
5820 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5821 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5822 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5823 (sgsr & SERDES_TG3_SGMII_MODE)) {
5824
5825 if (force_reset)
5826 tg3_phy_reset(tp);
5827
5828 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5829
5830 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5831 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5832 } else {
953c96e0 5833 current_link_up = true;
85730a63
MC		 5834 if (sgsr & SERDES_TG3_SPEED_1000) {
5835 current_speed = SPEED_1000;
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5837 } else if (sgsr & SERDES_TG3_SPEED_100) {
5838 current_speed = SPEED_100;
5839 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5840 } else {
5841 current_speed = SPEED_10;
5842 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5843 }
5844
5845 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5846 current_duplex = DUPLEX_FULL;
5847 else
5848 current_duplex = DUPLEX_HALF;
5849 }
5850
5851 tw32_f(MAC_MODE, tp->mac_mode);
5852 udelay(40);
5853
5854 tg3_clear_mac_status(tp);
5855
5856 goto fiber_setup_done;
5857 }
747e8f8b
MC		 5858
5859 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5860 tw32_f(MAC_MODE, tp->mac_mode);
5861 udelay(40);
5862
3310e248 5863 tg3_clear_mac_status(tp);
747e8f8b
MC		 5864
5865 if (force_reset)
5866 tg3_phy_reset(tp);
5867
859edb26 5868 tp->link_config.rmt_adv = 0;
747e8f8b
MC		 5869
5870 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5871 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5872 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5873 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5874 bmsr |= BMSR_LSTATUS;
5875 else
5876 bmsr &= ~BMSR_LSTATUS;
5877 }
747e8f8b
MC		 5878
5879 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5880
5881 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
f07e9af3 5882 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 5883 /* do nothing, just check for link up at the end */
5884 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
28011cf1 5885 u32 adv, newadv;
747e8f8b
MC		 5886
5887 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
28011cf1
MC		 5888 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5889 ADVERTISE_1000XPAUSE |
5890 ADVERTISE_1000XPSE_ASYM |
5891 ADVERTISE_SLCT);
747e8f8b 5892
28011cf1 5893 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
37f07023 5894 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
747e8f8b 5895
28011cf1
MC		 5896 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5897 tg3_writephy(tp, MII_ADVERTISE, newadv);
747e8f8b
MC		 5898 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5899 tg3_writephy(tp, MII_BMCR, bmcr);
5900
5901 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 5902 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
f07e9af3 5903 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5904
5905 return err;
5906 }
5907 } else {
5908 u32 new_bmcr;
5909
5910 bmcr &= ~BMCR_SPEED1000;
5911 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5912
5913 if (tp->link_config.duplex == DUPLEX_FULL)
5914 new_bmcr |= BMCR_FULLDPLX;
5915
5916 if (new_bmcr != bmcr) {
5917 /* BMCR_SPEED1000 is a reserved bit that needs
5918 * to be set on write.
5919 */
5920 new_bmcr |= BMCR_SPEED1000;
5921
5922 /* Force a linkdown */
f4a46d1f 5923 if (tp->link_up) {
747e8f8b
MC		 5924 u32 adv;
5925
5926 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5927 adv &= ~(ADVERTISE_1000XFULL |
5928 ADVERTISE_1000XHALF |
5929 ADVERTISE_SLCT);
5930 tg3_writephy(tp, MII_ADVERTISE, adv);
5931 tg3_writephy(tp, MII_BMCR, bmcr |
5932 BMCR_ANRESTART |
5933 BMCR_ANENABLE);
5934 udelay(10);
f4a46d1f 5935 tg3_carrier_off(tp);
747e8f8b
MC		 5936 }
5937 tg3_writephy(tp, MII_BMCR, new_bmcr);
5938 bmcr = new_bmcr;
5939 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5940 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5941 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5942 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5943 bmsr |= BMSR_LSTATUS;
5944 else
5945 bmsr &= ~BMSR_LSTATUS;
5946 }
f07e9af3 5947 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5948 }
5949 }
5950
5951 if (bmsr & BMSR_LSTATUS) {
5952 current_speed = SPEED_1000;
953c96e0 5953 current_link_up = true;
747e8f8b
MC		 5954 if (bmcr & BMCR_FULLDPLX)
5955 current_duplex = DUPLEX_FULL;
5956 else
5957 current_duplex = DUPLEX_HALF;
5958
ef167e27
MC		 5959 local_adv = 0;
5960 remote_adv = 0;
5961
747e8f8b 5962 if (bmcr & BMCR_ANENABLE) {
ef167e27 5963 u32 common;
747e8f8b
MC		 5964
5965 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5966 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5967 common = local_adv & remote_adv;
5968 if (common & (ADVERTISE_1000XHALF |
5969 ADVERTISE_1000XFULL)) {
5970 if (common & ADVERTISE_1000XFULL)
5971 current_duplex = DUPLEX_FULL;
5972 else
5973 current_duplex = DUPLEX_HALF;
859edb26
MC		 5974
5975 tp->link_config.rmt_adv =
5976 mii_adv_to_ethtool_adv_x(remote_adv);
63c3a66f 5977 } else if (!tg3_flag(tp, 5780_CLASS)) {
57d8b880 5978 /* Link is up via parallel detect */
859a5887 5979 } else {
953c96e0 5980 current_link_up = false;
859a5887 5981 }
747e8f8b
MC		 5982 }
5983 }
5984
85730a63 5985fiber_setup_done:
953c96e0 5986 if (current_link_up && current_duplex == DUPLEX_FULL)
ef167e27
MC		 5987 tg3_setup_flow_control(tp, local_adv, remote_adv);
5988
747e8f8b
MC		 5989 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5990 if (tp->link_config.active_duplex == DUPLEX_HALF)
5991 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5992
5993 tw32_f(MAC_MODE, tp->mac_mode);
5994 udelay(40);
5995
5996 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5997
5998 tp->link_config.active_speed = current_speed;
5999 tp->link_config.active_duplex = current_duplex;
6000
f4a46d1f 6001 tg3_test_and_report_link_chg(tp, current_link_up);
747e8f8b
MC		 6002 return err;
6003}
6004
6005static void tg3_serdes_parallel_detect(struct tg3 *tp)
6006{
3d3ebe74 6007 if (tp->serdes_counter) {
747e8f8b 6008 /* Give autoneg time to complete. */
3d3ebe74 6009 tp->serdes_counter--;
747e8f8b
MC		 6010 return;
6011 }
c6cdf436 6012
f4a46d1f 6013 if (!tp->link_up &&
747e8f8b
MC		 6014 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6015 u32 bmcr;
6016
6017 tg3_readphy(tp, MII_BMCR, &bmcr);
6018 if (bmcr & BMCR_ANENABLE) {
6019 u32 phy1, phy2;
6020
6021 /* Select shadow register 0x1f */
f08aa1a8
MC		 6022 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6023 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
747e8f8b
MC		 6024
6025 /* Select expansion interrupt status register */
f08aa1a8
MC		 6026 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6027 MII_TG3_DSP_EXP1_INT_STAT);
6028 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6029 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6030
6031 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6032 /* We have signal detect and not receiving
6033 * config code words, link is up by parallel
6034 * detection.
6035 */
6036
6037 bmcr &= ~BMCR_ANENABLE;
6038 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6039 tg3_writephy(tp, MII_BMCR, bmcr);
f07e9af3 6040 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6041 }
6042 }
f4a46d1f 6043 } else if (tp->link_up &&
859a5887 6044 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
f07e9af3 6045 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 6046 u32 phy2;
6047
6048 /* Select expansion interrupt status register */
f08aa1a8
MC		 6049 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6050 MII_TG3_DSP_EXP1_INT_STAT);
6051 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6052 if (phy2 & 0x20) {
6053 u32 bmcr;
6054
6055 /* Config code words received, turn on autoneg. */
6056 tg3_readphy(tp, MII_BMCR, &bmcr);
6057 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6058
f07e9af3 6059 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6060
6061 }
6062 }
6063}
6064
953c96e0 6065static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
1da177e4 6066{
f2096f94 6067 u32 val;
1da177e4
LT		 6068 int err;
6069
f07e9af3 6070 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4 6071 err = tg3_setup_fiber_phy(tp, force_reset);
f07e9af3 6072 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
747e8f8b 6073 err = tg3_setup_fiber_mii_phy(tp, force_reset);
859a5887 6074 else
1da177e4 6075 err = tg3_setup_copper_phy(tp, force_reset);
1da177e4 6076
4153577a 6077 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
f2096f94 6078 u32 scale;
aa6c91fe
MC		 6079
6080 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6081 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6082 scale = 65;
6083 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6084 scale = 6;
6085 else
6086 scale = 12;
6087
6088 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6089 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6090 tw32(GRC_MISC_CFG, val);
6091 }
6092
f2096f94
MC		 6093 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6094 (6 << TX_LENGTHS_IPG_SHIFT);
4153577a
JP		 6095 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6096 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 6097 val |= tr32(MAC_TX_LENGTHS) &
6098 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6099 TX_LENGTHS_CNT_DWN_VAL_MSK);
6100
1da177e4
LT		 6101 if (tp->link_config.active_speed == SPEED_1000 &&
6102 tp->link_config.active_duplex == DUPLEX_HALF)
f2096f94
MC		 6103 tw32(MAC_TX_LENGTHS, val |
6104 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6105 else
f2096f94
MC		 6106 tw32(MAC_TX_LENGTHS, val |
6107 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6108
63c3a66f 6109 if (!tg3_flag(tp, 5705_PLUS)) {
f4a46d1f 6110 if (tp->link_up) {
1da177e4 6111 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 6112 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 6113 } else {
6114 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6115 }
6116 }
6117
63c3a66f 6118 if (tg3_flag(tp, ASPM_WORKAROUND)) {
f2096f94 6119 val = tr32(PCIE_PWR_MGMT_THRESH);
f4a46d1f 6120 if (!tp->link_up)
8ed5d97e
MC		 6121 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6122 tp->pwrmgmt_thresh;
6123 else
6124 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6125 tw32(PCIE_PWR_MGMT_THRESH, val);
6126 }
6127
1da177e4
LT		 6128 return err;
6129}
6130
7d41e49a
MC		 6131/* tp->lock must be held */
6132static u64 tg3_refclk_read(struct tg3 *tp)
6133{
6134 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6135 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6136}
6137
be947307
MC		 6138/* tp->lock must be held */
6139static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6140{
92e6457d
NS		 6141 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6142
6143 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
be947307
MC		 6144 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6145 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
92e6457d 6146 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
be947307
MC		 6147}
6148
7d41e49a
MC		 6149static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6150static inline void tg3_full_unlock(struct tg3 *tp);
6151static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6152{
6153 struct tg3 *tp = netdev_priv(dev);
6154
6155 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6156 SOF_TIMESTAMPING_RX_SOFTWARE |
f233a976
FL		 6157 SOF_TIMESTAMPING_SOFTWARE;
6158
6159 if (tg3_flag(tp, PTP_CAPABLE)) {
32e19272 6160 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
f233a976
FL		 6161 SOF_TIMESTAMPING_RX_HARDWARE |
6162 SOF_TIMESTAMPING_RAW_HARDWARE;
6163 }
7d41e49a
MC		 6164
6165 if (tp->ptp_clock)
6166 info->phc_index = ptp_clock_index(tp->ptp_clock);
6167 else
6168 info->phc_index = -1;
6169
6170 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6171
6172 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6173 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6174 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6175 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6176 return 0;
6177}
6178
6179static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6180{
6181 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6182 bool neg_adj = false;
6183 u32 correction = 0;
6184
6185 if (ppb < 0) {
6186 neg_adj = true;
6187 ppb = -ppb;
6188 }
6189
6190 /* Frequency adjustment is performed using hardware with a 24 bit
6191 * accumulator and a programmable correction value. On each clk, the
6192 * correction value gets added to the accumulator and when it
6193 * overflows, the time counter is incremented/decremented.
6194 *
6195 * So conversion from ppb to correction value is
6196 * ppb * (1 << 24) / 1000000000
6197 */
6198 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6199 TG3_EAV_REF_CLK_CORRECT_MASK;
6200
6201 tg3_full_lock(tp, 0);
6202
6203 if (correction)
6204 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6205 TG3_EAV_REF_CLK_CORRECT_EN |
6206 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6207 else
6208 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6209
6210 tg3_full_unlock(tp);
6211
6212 return 0;
6213}
6214
6215static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6216{
6217 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6218
6219 tg3_full_lock(tp, 0);
6220 tp->ptp_adjust += delta;
6221 tg3_full_unlock(tp);
6222
6223 return 0;
6224}
6225
6226static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6227{
6228 u64 ns;
6229 u32 remainder;
6230 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6231
6232 tg3_full_lock(tp, 0);
6233 ns = tg3_refclk_read(tp);
6234 ns += tp->ptp_adjust;
6235 tg3_full_unlock(tp);
6236
6237 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6238 ts->tv_nsec = remainder;
6239
6240 return 0;
6241}
6242
6243static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6244 const struct timespec *ts)
6245{
6246 u64 ns;
6247 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6248
6249 ns = timespec_to_ns(ts);
6250
6251 tg3_full_lock(tp, 0);
6252 tg3_refclk_write(tp, ns);
6253 tp->ptp_adjust = 0;
6254 tg3_full_unlock(tp);
6255
6256 return 0;
6257}
6258
6259static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6260 struct ptp_clock_request *rq, int on)
6261{
92e6457d
NS		 6262 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6263 u32 clock_ctl;
6264 int rval = 0;
6265
6266 switch (rq->type) {
6267 case PTP_CLK_REQ_PEROUT:
6268 if (rq->perout.index != 0)
6269 return -EINVAL;
6270
6271 tg3_full_lock(tp, 0);
6272 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6273 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6274
6275 if (on) {
6276 u64 nsec;
6277
6278 nsec = rq->perout.start.sec * 1000000000ULL +
6279 rq->perout.start.nsec;
6280
6281 if (rq->perout.period.sec || rq->perout.period.nsec) {
6282 netdev_warn(tp->dev,
6283 "Device supports only a one-shot timesync output, period must be 0\n");
6284 rval = -EINVAL;
6285 goto err_out;
6286 }
6287
6288 if (nsec & (1ULL << 63)) {
6289 netdev_warn(tp->dev,
6290 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6291 rval = -EINVAL;
6292 goto err_out;
6293 }
6294
6295 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6296 tw32(TG3_EAV_WATCHDOG0_MSB,
6297 TG3_EAV_WATCHDOG0_EN |
6298 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6299
6300 tw32(TG3_EAV_REF_CLCK_CTL,
6301 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6302 } else {
6303 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6304 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6305 }
6306
6307err_out:
6308 tg3_full_unlock(tp);
6309 return rval;
6310
6311 default:
6312 break;
6313 }
6314
7d41e49a
MC		 6315 return -EOPNOTSUPP;
6316}
6317
6318static const struct ptp_clock_info tg3_ptp_caps = {
6319 .owner = THIS_MODULE,
6320 .name = "tg3 clock",
6321 .max_adj = 250000000,
6322 .n_alarm = 0,
6323 .n_ext_ts = 0,
92e6457d 6324 .n_per_out = 1,
7d41e49a
MC		 6325 .pps = 0,
6326 .adjfreq = tg3_ptp_adjfreq,
6327 .adjtime = tg3_ptp_adjtime,
6328 .gettime = tg3_ptp_gettime,
6329 .settime = tg3_ptp_settime,
6330 .enable = tg3_ptp_enable,
6331};
6332
fb4ce8ad
MC		 6333static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6334 struct skb_shared_hwtstamps *timestamp)
6335{
6336 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6337 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6338 tp->ptp_adjust);
6339}
6340
be947307
MC		 6341/* tp->lock must be held */
6342static void tg3_ptp_init(struct tg3 *tp)
6343{
6344 if (!tg3_flag(tp, PTP_CAPABLE))
6345 return;
6346
6347 /* Initialize the hardware clock to the system time. */
6348 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6349 tp->ptp_adjust = 0;
7d41e49a 6350 tp->ptp_info = tg3_ptp_caps;
be947307
MC		 6351}
6352
6353/* tp->lock must be held */
6354static void tg3_ptp_resume(struct tg3 *tp)
6355{
6356 if (!tg3_flag(tp, PTP_CAPABLE))
6357 return;
6358
6359 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6360 tp->ptp_adjust = 0;
6361}
6362
6363static void tg3_ptp_fini(struct tg3 *tp)
6364{
6365 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6366 return;
6367
7d41e49a 6368 ptp_clock_unregister(tp->ptp_clock);
be947307
MC		 6369 tp->ptp_clock = NULL;
6370 tp->ptp_adjust = 0;
6371}
6372
66cfd1bd
MC		 6373static inline int tg3_irq_sync(struct tg3 *tp)
6374{
6375 return tp->irq_sync;
6376}
6377
97bd8e49
MC		 6378static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6379{
6380 int i;
6381
6382 dst = (u32 *)((u8 *)dst + off);
6383 for (i = 0; i < len; i += sizeof(u32))
6384 *dst++ = tr32(off + i);
6385}
6386
6387static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6388{
6389 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6390 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6391 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6392 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6393 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6394 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6395 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6396 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6397 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6398 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6399 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6400 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6401 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6402 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6403 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6404 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6405 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6406 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6407 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6408
63c3a66f 6409 if (tg3_flag(tp, SUPPORT_MSIX))
97bd8e49
MC		 6410 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6411
6412 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6413 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6414 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6415 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6416 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6417 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6418 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6419 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6420
63c3a66f 6421 if (!tg3_flag(tp, 5705_PLUS)) {
97bd8e49
MC		 6422 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6423 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6424 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6425 }
6426
6427 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6428 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6429 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6430 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6431 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6432
63c3a66f 6433 if (tg3_flag(tp, NVRAM))
97bd8e49
MC		 6434 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6435}
6436
6437static void tg3_dump_state(struct tg3 *tp)
6438{
6439 int i;
6440 u32 *regs;
6441
6442 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
b2adaca9 6443 if (!regs)
97bd8e49 6444 return;
97bd8e49 6445
63c3a66f 6446 if (tg3_flag(tp, PCI_EXPRESS)) {
97bd8e49
MC		 6447 /* Read up to but not including private PCI registers */
6448 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6449 regs[i / sizeof(u32)] = tr32(i);
6450 } else
6451 tg3_dump_legacy_regs(tp, regs);
6452
6453 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6454 if (!regs[i + 0] && !regs[i + 1] &&
6455 !regs[i + 2] && !regs[i + 3])
6456 continue;
6457
6458 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6459 i * 4,
6460 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6461 }
6462
6463 kfree(regs);
6464
6465 for (i = 0; i < tp->irq_cnt; i++) {
6466 struct tg3_napi *tnapi = &tp->napi[i];
6467
6468 /* SW status block */
6469 netdev_err(tp->dev,
6470 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6471 i,
6472 tnapi->hw_status->status,
6473 tnapi->hw_status->status_tag,
6474 tnapi->hw_status->rx_jumbo_consumer,
6475 tnapi->hw_status->rx_consumer,
6476 tnapi->hw_status->rx_mini_consumer,
6477 tnapi->hw_status->idx[0].rx_producer,
6478 tnapi->hw_status->idx[0].tx_consumer);
6479
6480 netdev_err(tp->dev,
6481 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6482 i,
6483 tnapi->last_tag, tnapi->last_irq_tag,
6484 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6485 tnapi->rx_rcb_ptr,
6486 tnapi->prodring.rx_std_prod_idx,
6487 tnapi->prodring.rx_std_cons_idx,
6488 tnapi->prodring.rx_jmb_prod_idx,
6489 tnapi->prodring.rx_jmb_cons_idx);
6490 }
6491}
6492
df3e6548
MC		 6493/* This is called whenever we suspect that the system chipset is re-
6494 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6495 * is bogus tx completions. We try to recover by setting the
6496 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6497 * in the workqueue.
6498 */
6499static void tg3_tx_recover(struct tg3 *tp)
6500{
63c3a66f 6501 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
df3e6548
MC		 6502 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6503
5129c3a3
MC		 6504 netdev_warn(tp->dev,
6505 "The system may be re-ordering memory-mapped I/O "
6506 "cycles to the network device, attempting to recover. "
6507 "Please report the problem to the driver maintainer "
6508 "and include system chipset information.\n");
df3e6548 6509
63c3a66f 6510 tg3_flag_set(tp, TX_RECOVERY_PENDING);
df3e6548
MC		 6511}
6512
f3f3f27e 6513static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205 6514{
f65aac16
MC		 6515 /* Tell compiler to fetch tx indices from memory. */
6516 barrier();
f3f3f27e
MC		 6517 return tnapi->tx_pending -
6518 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 6519}
6520
1da177e4
LT		 6521/* Tigon3 never reports partial packet sends. So we do not
6522 * need special logic to handle SKBs that have not had all
6523 * of their frags sent yet, like SunGEM does.
6524 */
17375d25 6525static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 6526{
17375d25 6527 struct tg3 *tp = tnapi->tp;
898a56f8 6528 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 6529 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 6530 struct netdev_queue *txq;
6531 int index = tnapi - tp->napi;
298376d3 6532 unsigned int pkts_compl = 0, bytes_compl = 0;
fe5f5787 6533
63c3a66f 6534 if (tg3_flag(tp, ENABLE_TSS))
fe5f5787
MC		 6535 index--;
6536
6537 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 6538
6539 while (sw_idx != hw_idx) {
df8944cf 6540 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 6541 struct sk_buff *skb = ri->skb;
df3e6548
MC		 6542 int i, tx_bug = 0;
6543
6544 if (unlikely(skb == NULL)) {
6545 tg3_tx_recover(tp);
6546 return;
6547 }
1da177e4 6548
fb4ce8ad
MC		 6549 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6550 struct skb_shared_hwtstamps timestamp;
6551 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6552 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6553
6554 tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);
6555
6556 skb_tstamp_tx(skb, &timestamp);
6557 }
6558
f4188d8a 6559 pci_unmap_single(tp->pdev,
4e5e4f0d 6560 dma_unmap_addr(ri, mapping),
f4188d8a
AD		 6561 skb_headlen(skb),
6562 PCI_DMA_TODEVICE);
1da177e4
LT		 6563
6564 ri->skb = NULL;
6565
e01ee14d
MC		 6566 while (ri->fragmented) {
6567 ri->fragmented = false;
6568 sw_idx = NEXT_TX(sw_idx);
6569 ri = &tnapi->tx_buffers[sw_idx];
6570 }
6571
1da177e4
LT		 6572 sw_idx = NEXT_TX(sw_idx);
6573
6574 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 6575 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 6576 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6577 tx_bug = 1;
f4188d8a
AD		 6578
6579 pci_unmap_page(tp->pdev,
4e5e4f0d 6580 dma_unmap_addr(ri, mapping),
9e903e08 6581 skb_frag_size(&skb_shinfo(skb)->frags[i]),
f4188d8a 6582 PCI_DMA_TODEVICE);
e01ee14d
MC		 6583
6584 while (ri->fragmented) {
6585 ri->fragmented = false;
6586 sw_idx = NEXT_TX(sw_idx);
6587 ri = &tnapi->tx_buffers[sw_idx];
6588 }
6589
1da177e4
LT		 6590 sw_idx = NEXT_TX(sw_idx);
6591 }
6592
298376d3
TH		 6593 pkts_compl++;
6594 bytes_compl += skb->len;
6595
f47c11ee 6596 dev_kfree_skb(skb);
df3e6548
MC		 6597
6598 if (unlikely(tx_bug)) {
6599 tg3_tx_recover(tp);
6600 return;
6601 }
1da177e4
LT		 6602 }
6603
5cb917bc 6604 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
298376d3 6605
f3f3f27e 6606 tnapi->tx_cons = sw_idx;
1da177e4 6607
1b2a7205
MC		 6608 /* Need to make the tx_cons update visible to tg3_start_xmit()
6609 * before checking for netif_queue_stopped(). Without the
6610 * memory barrier, there is a small possibility that tg3_start_xmit()
6611 * will miss it and cause the queue to be stopped forever.
6612 */
6613 smp_mb();
6614
fe5f5787 6615 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 6616 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 6617 __netif_tx_lock(txq, smp_processor_id());
6618 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 6619 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 6620 netif_tx_wake_queue(txq);
6621 __netif_tx_unlock(txq);
51b91468 6622 }
1da177e4
LT		 6623}
6624
8d4057a9
ED		 6625static void tg3_frag_free(bool is_frag, void *data)
6626{
6627 if (is_frag)
6628 put_page(virt_to_head_page(data));
6629 else
6630 kfree(data);
6631}
6632
9205fd9c 6633static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
2b2cdb65 6634{
8d4057a9
ED		 6635 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6636 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6637
9205fd9c 6638 if (!ri->data)
2b2cdb65
MC		 6639 return;
6640
4e5e4f0d 6641 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
2b2cdb65 6642 map_sz, PCI_DMA_FROMDEVICE);
a1e8b307 6643 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
9205fd9c 6644 ri->data = NULL;
2b2cdb65
MC		 6645}
6646
8d4057a9 6647
1da177e4
LT		 6648/* Returns size of skb allocated or < 0 on error.
6649 *
6650 * We only need to fill in the address because the other members
6651 * of the RX descriptor are invariant, see tg3_init_rings.
6652 *
6653 * Note the purposeful assymetry of cpu vs. chip accesses. For
6654 * posting buffers we only dirty the first cache line of the RX
6655 * descriptor (containing the address). Whereas for the RX status
6656 * buffers the cpu only reads the last cacheline of the RX descriptor
6657 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6658 */
9205fd9c 6659static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
8d4057a9
ED		 6660 u32 opaque_key, u32 dest_idx_unmasked,
6661 unsigned int *frag_size)
1da177e4
LT		 6662{
6663 struct tg3_rx_buffer_desc *desc;
f94e290e 6664 struct ring_info *map;
9205fd9c 6665 u8 *data;
1da177e4 6666 dma_addr_t mapping;
9205fd9c 6667 int skb_size, data_size, dest_idx;
1da177e4 6668
1da177e4
LT		 6669 switch (opaque_key) {
6670 case RXD_OPAQUE_RING_STD:
2c49a44d 6671 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
21f581a5
MC		 6672 desc = &tpr->rx_std[dest_idx];
6673 map = &tpr->rx_std_buffers[dest_idx];
9205fd9c 6674 data_size = tp->rx_pkt_map_sz;
1da177e4
LT		 6675 break;
6676
6677 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6678 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
79ed5ac7 6679 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 6680 map = &tpr->rx_jmb_buffers[dest_idx];
9205fd9c 6681 data_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 6682 break;
6683
6684 default:
6685 return -EINVAL;
855e1111 6686 }
1da177e4
LT		 6687
6688 /* Do not overwrite any of the map or rp information
6689 * until we are sure we can commit to a new buffer.
6690 *
6691 * Callers depend upon this behavior and assume that
6692 * we leave everything unchanged if we fail.
6693 */
9205fd9c
ED		 6694 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6695 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
a1e8b307
ED		 6696 if (skb_size <= PAGE_SIZE) {
6697 data = netdev_alloc_frag(skb_size);
6698 *frag_size = skb_size;
8d4057a9
ED		 6699 } else {
6700 data = kmalloc(skb_size, GFP_ATOMIC);
6701 *frag_size = 0;
6702 }
9205fd9c 6703 if (!data)
1da177e4
LT		 6704 return -ENOMEM;
6705
9205fd9c
ED		 6706 mapping = pci_map_single(tp->pdev,
6707 data + TG3_RX_OFFSET(tp),
6708 data_size,
1da177e4 6709 PCI_DMA_FROMDEVICE);
8d4057a9 6710 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
a1e8b307 6711 tg3_frag_free(skb_size <= PAGE_SIZE, data);
a21771dd
MC		 6712 return -EIO;
6713 }
1da177e4 6714
9205fd9c 6715 map->data = data;
4e5e4f0d 6716 dma_unmap_addr_set(map, mapping, mapping);
1da177e4 6717
1da177e4
LT		 6718 desc->addr_hi = ((u64)mapping >> 32);
6719 desc->addr_lo = ((u64)mapping & 0xffffffff);
6720
9205fd9c 6721 return data_size;
1da177e4
LT		 6722}
6723
6724/* We only need to move over in the address because the other
6725 * members of the RX descriptor are invariant. See notes above
9205fd9c 6726 * tg3_alloc_rx_data for full details.
1da177e4 6727 */
a3896167
MC		 6728static void tg3_recycle_rx(struct tg3_napi *tnapi,
6729 struct tg3_rx_prodring_set *dpr,
6730 u32 opaque_key, int src_idx,
6731 u32 dest_idx_unmasked)
1da177e4 6732{
17375d25 6733 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 6734 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6735 struct ring_info *src_map, *dest_map;
8fea32b9 6736 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
c6cdf436 6737 int dest_idx;
1da177e4
LT		 6738
6739 switch (opaque_key) {
6740 case RXD_OPAQUE_RING_STD:
2c49a44d 6741 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
a3896167
MC		 6742 dest_desc = &dpr->rx_std[dest_idx];
6743 dest_map = &dpr->rx_std_buffers[dest_idx];
6744 src_desc = &spr->rx_std[src_idx];
6745 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 6746 break;
6747
6748 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6749 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
a3896167
MC		 6750 dest_desc = &dpr->rx_jmb[dest_idx].std;
6751 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6752 src_desc = &spr->rx_jmb[src_idx].std;
6753 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 6754 break;
6755
6756 default:
6757 return;
855e1111 6758 }
1da177e4 6759
9205fd9c 6760 dest_map->data = src_map->data;
4e5e4f0d
FT		 6761 dma_unmap_addr_set(dest_map, mapping,
6762 dma_unmap_addr(src_map, mapping));
1da177e4
LT		 6763 dest_desc->addr_hi = src_desc->addr_hi;
6764 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 6765
6766 /* Ensure that the update to the skb happens after the physical
6767 * addresses have been transferred to the new BD location.
6768 */
6769 smp_wmb();
6770
9205fd9c 6771 src_map->data = NULL;
1da177e4
LT		 6772}
6773
1da177e4
LT		 6774/* The RX ring scheme is composed of multiple rings which post fresh
6775 * buffers to the chip, and one special ring the chip uses to report
6776 * status back to the host.
6777 *
6778 * The special ring reports the status of received packets to the
6779 * host. The chip does not write into the original descriptor the
6780 * RX buffer was obtained from. The chip simply takes the original
6781 * descriptor as provided by the host, updates the status and length
6782 * field, then writes this into the next status ring entry.
6783 *
6784 * Each ring the host uses to post buffers to the chip is described
6785 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6786 * it is first placed into the on-chip ram. When the packet's length
6787 * is known, it walks down the TG3_BDINFO entries to select the ring.
6788 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6789 * which is within the range of the new packet's length is chosen.
6790 *
6791 * The "separate ring for rx status" scheme may sound queer, but it makes
6792 * sense from a cache coherency perspective. If only the host writes
6793 * to the buffer post rings, and only the chip writes to the rx status
6794 * rings, then cache lines never move beyond shared-modified state.
6795 * If both the host and chip were to write into the same ring, cache line
6796 * eviction could occur since both entities want it in an exclusive state.
6797 */
17375d25 6798static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 6799{
17375d25 6800 struct tg3 *tp = tnapi->tp;
f92905de 6801 u32 work_mask, rx_std_posted = 0;
4361935a 6802 u32 std_prod_idx, jmb_prod_idx;
72334482 6803 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 6804 u16 hw_idx;
1da177e4 6805 int received;
8fea32b9 6806 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
1da177e4 6807
8d9d7cfc 6808 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 6809 /*
6810 * We need to order the read of hw_idx and the read of
6811 * the opaque cookie.
6812 */
6813 rmb();
1da177e4
LT		 6814 work_mask = 0;
6815 received = 0;
4361935a
MC		 6816 std_prod_idx = tpr->rx_std_prod_idx;
6817 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 6818 while (sw_idx != hw_idx && budget > 0) {
afc081f8 6819 struct ring_info *ri;
72334482 6820 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 6821 unsigned int len;
6822 struct sk_buff *skb;
6823 dma_addr_t dma_addr;
6824 u32 opaque_key, desc_idx, *post_ptr;
9205fd9c 6825 u8 *data;
fb4ce8ad 6826 u64 tstamp = 0;
1da177e4
LT		 6827
6828 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6829 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6830 if (opaque_key == RXD_OPAQUE_RING_STD) {
8fea32b9 6831 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4e5e4f0d 6832 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6833 data = ri->data;
4361935a 6834 post_ptr = &std_prod_idx;
f92905de 6835 rx_std_posted++;
1da177e4 6836 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
8fea32b9 6837 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4e5e4f0d 6838 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6839 data = ri->data;
4361935a 6840 post_ptr = &jmb_prod_idx;
21f581a5 6841 } else
1da177e4 6842 goto next_pkt_nopost;
1da177e4
LT		 6843
6844 work_mask |= opaque_key;
6845
6846 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
6847 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
6848 drop_it:
a3896167 6849 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6850 desc_idx, *post_ptr);
6851 drop_it_no_recycle:
6852 /* Other statistics kept track of by card. */
b0057c51 6853 tp->rx_dropped++;
1da177e4
LT		 6854 goto next_pkt;
6855 }
6856
9205fd9c 6857 prefetch(data + TG3_RX_OFFSET(tp));
ad829268
MC		 6858 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6859 ETH_FCS_LEN;
1da177e4 6860
fb4ce8ad
MC		 6861 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6862 RXD_FLAG_PTPSTAT_PTPV1 ||
6863 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6864 RXD_FLAG_PTPSTAT_PTPV2) {
6865 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6866 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6867 }
6868
d2757fc4 6869 if (len > TG3_RX_COPY_THRESH(tp)) {
1da177e4 6870 int skb_size;
8d4057a9 6871 unsigned int frag_size;
1da177e4 6872
9205fd9c 6873 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
8d4057a9 6874 *post_ptr, &frag_size);
1da177e4
LT		 6875 if (skb_size < 0)
6876 goto drop_it;
6877
287be12e 6878 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 6879 PCI_DMA_FROMDEVICE);
6880
9205fd9c 6881 /* Ensure that the update to the data happens
61e800cf
MC		 6882 * after the usage of the old DMA mapping.
6883 */
6884 smp_wmb();
6885
9205fd9c 6886 ri->data = NULL;
61e800cf 6887
85aec73d
IV		 6888 skb = build_skb(data, frag_size);
6889 if (!skb) {
6890 tg3_frag_free(frag_size != 0, data);
6891 goto drop_it_no_recycle;
6892 }
6893 skb_reserve(skb, TG3_RX_OFFSET(tp));
1da177e4 6894 } else {
a3896167 6895 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6896 desc_idx, *post_ptr);
6897
9205fd9c
ED		 6898 skb = netdev_alloc_skb(tp->dev,
6899 len + TG3_RAW_IP_ALIGN);
6900 if (skb == NULL)
1da177e4
LT		 6901 goto drop_it_no_recycle;
6902
9205fd9c 6903 skb_reserve(skb, TG3_RAW_IP_ALIGN);
1da177e4 6904 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
9205fd9c
ED		 6905 memcpy(skb->data,
6906 data + TG3_RX_OFFSET(tp),
6907 len);
1da177e4 6908 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
1da177e4
LT		 6909 }
6910
9205fd9c 6911 skb_put(skb, len);
fb4ce8ad
MC		 6912 if (tstamp)
6913 tg3_hwclock_to_timestamp(tp, tstamp,
6914 skb_hwtstamps(skb));
6915
dc668910 6916 if ((tp->dev->features & NETIF_F_RXCSUM) &&
1da177e4
LT		 6917 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6918 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6919 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6920 skb->ip_summed = CHECKSUM_UNNECESSARY;
6921 else
bc8acf2c 6922 skb_checksum_none_assert(skb);
1da177e4
LT		 6923
6924 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 6925
6926 if (len > (tp->dev->mtu + ETH_HLEN) &&
6927 skb->protocol != htons(ETH_P_8021Q)) {
6928 dev_kfree_skb(skb);
b0057c51 6929 goto drop_it_no_recycle;
f7b493e0
MC		 6930 }
6931
9dc7a113 6932 if (desc->type_flags & RXD_FLAG_VLAN &&
bf933c80 6933 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
86a9bad3 6934 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
bf933c80 6935 desc->err_vlan & RXD_VLAN_MASK);
9dc7a113 6936
bf933c80 6937 napi_gro_receive(&tnapi->napi, skb);
1da177e4 6938
1da177e4
LT		 6939 received++;
6940 budget--;
6941
6942next_pkt:
6943 (*post_ptr)++;
f92905de
MC		 6944
6945 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
2c49a44d
MC		 6946 tpr->rx_std_prod_idx = std_prod_idx &
6947 tp->rx_std_ring_mask;
86cfe4ff
MC		 6948 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6949 tpr->rx_std_prod_idx);
f92905de
MC		 6950 work_mask &= ~RXD_OPAQUE_RING_STD;
6951 rx_std_posted = 0;
6952 }
1da177e4 6953next_pkt_nopost:
483ba50b 6954 sw_idx++;
7cb32cf2 6955 sw_idx &= tp->rx_ret_ring_mask;
52f6d697
MC		 6956
6957 /* Refresh hw_idx to see if there is new work */
6958 if (sw_idx == hw_idx) {
8d9d7cfc 6959 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 6960 rmb();
6961 }
1da177e4
LT		 6962 }
6963
6964 /* ACK the status ring. */
72334482
MC		 6965 tnapi->rx_rcb_ptr = sw_idx;
6966 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 6967
6968 /* Refill RX ring(s). */
63c3a66f 6969 if (!tg3_flag(tp, ENABLE_RSS)) {
6541b806
MC		 6970 /* Sync BD data before updating mailbox */
6971 wmb();
6972
b196c7e4 6973 if (work_mask & RXD_OPAQUE_RING_STD) {
2c49a44d
MC		 6974 tpr->rx_std_prod_idx = std_prod_idx &
6975 tp->rx_std_ring_mask;
b196c7e4
MC		 6976 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6977 tpr->rx_std_prod_idx);
6978 }
6979 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2c49a44d
MC		 6980 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6981 tp->rx_jmb_ring_mask;
b196c7e4
MC		 6982 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6983 tpr->rx_jmb_prod_idx);
6984 }
6985 mmiowb();
6986 } else if (work_mask) {
6987 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6988 * updated before the producer indices can be updated.
6989 */
6990 smp_wmb();
6991
2c49a44d
MC		 6992 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6993 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
b196c7e4 6994
7ae52890
MC		 6995 if (tnapi != &tp->napi[1]) {
6996 tp->rx_refill = true;
e4af1af9 6997 napi_schedule(&tp->napi[1].napi);
7ae52890 6998 }
1da177e4 6999 }
1da177e4
LT		 7000
7001 return received;
7002}
7003
35f2d7d0 7004static void tg3_poll_link(struct tg3 *tp)
1da177e4 7005{
1da177e4 7006 /* handle link change and other phy events */
63c3a66f 7007 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
35f2d7d0
MC		 7008 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7009
1da177e4
LT		 7010 if (sblk->status & SD_STATUS_LINK_CHG) {
7011 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 7012 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 7013 spin_lock(&tp->lock);
63c3a66f 7014 if (tg3_flag(tp, USE_PHYLIB)) {
dd477003
MC		 7015 tw32_f(MAC_STATUS,
7016 (MAC_STATUS_SYNC_CHANGED |
7017 MAC_STATUS_CFG_CHANGED |
7018 MAC_STATUS_MI_COMPLETION |
7019 MAC_STATUS_LNKSTATE_CHANGED));
7020 udelay(40);
7021 } else
953c96e0 7022 tg3_setup_phy(tp, false);
f47c11ee 7023 spin_unlock(&tp->lock);
1da177e4
LT		 7024 }
7025 }
35f2d7d0
MC		 7026}
7027
f89f38b8
MC		 7028static int tg3_rx_prodring_xfer(struct tg3 *tp,
7029 struct tg3_rx_prodring_set *dpr,
7030 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 7031{
7032 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 7033 int i, err = 0;
b196c7e4
MC		 7034
7035 while (1) {
7036 src_prod_idx = spr->rx_std_prod_idx;
7037
7038 /* Make sure updates to the rx_std_buffers[] entries and the
7039 * standard producer index are seen in the correct order.
7040 */
7041 smp_rmb();
7042
7043 if (spr->rx_std_cons_idx == src_prod_idx)
7044 break;
7045
7046 if (spr->rx_std_cons_idx < src_prod_idx)
7047 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7048 else
2c49a44d
MC		 7049 cpycnt = tp->rx_std_ring_mask + 1 -
7050 spr->rx_std_cons_idx;
b196c7e4 7051
2c49a44d
MC		 7052 cpycnt = min(cpycnt,
7053 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
b196c7e4
MC		 7054
7055 si = spr->rx_std_cons_idx;
7056 di = dpr->rx_std_prod_idx;
7057
e92967bf 7058 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7059 if (dpr->rx_std_buffers[i].data) {
e92967bf 7060 cpycnt = i - di;
f89f38b8 7061 err = -ENOSPC;
e92967bf
MC		 7062 break;
7063 }
7064 }
7065
7066 if (!cpycnt)
7067 break;
7068
7069 /* Ensure that updates to the rx_std_buffers ring and the
7070 * shadowed hardware producer ring from tg3_recycle_skb() are
7071 * ordered correctly WRT the skb check above.
7072 */
7073 smp_rmb();
7074
b196c7e4
MC		 7075 memcpy(&dpr->rx_std_buffers[di],
7076 &spr->rx_std_buffers[si],
7077 cpycnt * sizeof(struct ring_info));
7078
7079 for (i = 0; i < cpycnt; i++, di++, si++) {
7080 struct tg3_rx_buffer_desc *sbd, *dbd;
7081 sbd = &spr->rx_std[si];
7082 dbd = &dpr->rx_std[di];
7083 dbd->addr_hi = sbd->addr_hi;
7084 dbd->addr_lo = sbd->addr_lo;
7085 }
7086
2c49a44d
MC		 7087 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7088 tp->rx_std_ring_mask;
7089 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7090 tp->rx_std_ring_mask;
b196c7e4
MC		 7091 }
7092
7093 while (1) {
7094 src_prod_idx = spr->rx_jmb_prod_idx;
7095
7096 /* Make sure updates to the rx_jmb_buffers[] entries and
7097 * the jumbo producer index are seen in the correct order.
7098 */
7099 smp_rmb();
7100
7101 if (spr->rx_jmb_cons_idx == src_prod_idx)
7102 break;
7103
7104 if (spr->rx_jmb_cons_idx < src_prod_idx)
7105 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7106 else
2c49a44d
MC		 7107 cpycnt = tp->rx_jmb_ring_mask + 1 -
7108 spr->rx_jmb_cons_idx;
b196c7e4
MC		 7109
7110 cpycnt = min(cpycnt,
2c49a44d 7111 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7112
7113 si = spr->rx_jmb_cons_idx;
7114 di = dpr->rx_jmb_prod_idx;
7115
e92967bf 7116 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7117 if (dpr->rx_jmb_buffers[i].data) {
e92967bf 7118 cpycnt = i - di;
f89f38b8 7119 err = -ENOSPC;
e92967bf
MC		 7120 break;
7121 }
7122 }
7123
7124 if (!cpycnt)
7125 break;
7126
7127 /* Ensure that updates to the rx_jmb_buffers ring and the
7128 * shadowed hardware producer ring from tg3_recycle_skb() are
7129 * ordered correctly WRT the skb check above.
7130 */
7131 smp_rmb();
7132
b196c7e4
MC		 7133 memcpy(&dpr->rx_jmb_buffers[di],
7134 &spr->rx_jmb_buffers[si],
7135 cpycnt * sizeof(struct ring_info));
7136
7137 for (i = 0; i < cpycnt; i++, di++, si++) {
7138 struct tg3_rx_buffer_desc *sbd, *dbd;
7139 sbd = &spr->rx_jmb[si].std;
7140 dbd = &dpr->rx_jmb[di].std;
7141 dbd->addr_hi = sbd->addr_hi;
7142 dbd->addr_lo = sbd->addr_lo;
7143 }
7144
2c49a44d
MC		 7145 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7146 tp->rx_jmb_ring_mask;
7147 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7148 tp->rx_jmb_ring_mask;
b196c7e4 7149 }
f89f38b8
MC		 7150
7151 return err;
b196c7e4
MC		 7152}
7153
35f2d7d0
MC		 7154static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7155{
7156 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 7157
7158 /* run TX completion thread */
f3f3f27e 7159 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 7160 tg3_tx(tnapi);
63c3a66f 7161 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
4fd7ab59 7162 return work_done;
1da177e4
LT		 7163 }
7164
f891ea16
MC		 7165 if (!tnapi->rx_rcb_prod_idx)
7166 return work_done;
7167
1da177e4
LT		 7168 /* run RX thread, within the bounds set by NAPI.
7169 * All RX "locking" is done by ensuring outside
bea3348e 7170 * code synchronizes with tg3->napi.poll()
1da177e4 7171 */
8d9d7cfc 7172 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 7173 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 7174
63c3a66f 7175 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
8fea32b9 7176 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
f89f38b8 7177 int i, err = 0;
e4af1af9
MC		 7178 u32 std_prod_idx = dpr->rx_std_prod_idx;
7179 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 7180
7ae52890 7181 tp->rx_refill = false;
9102426a 7182 for (i = 1; i <= tp->rxq_cnt; i++)
f89f38b8 7183 err |= tg3_rx_prodring_xfer(tp, dpr,
8fea32b9 7184 &tp->napi[i].prodring);
b196c7e4
MC		 7185
7186 wmb();
7187
e4af1af9
MC		 7188 if (std_prod_idx != dpr->rx_std_prod_idx)
7189 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7190 dpr->rx_std_prod_idx);
b196c7e4 7191
e4af1af9
MC		 7192 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7193 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7194 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7195
7196 mmiowb();
f89f38b8
MC		 7197
7198 if (err)
7199 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 7200 }
7201
6f535763
DM		 7202 return work_done;
7203}
7204
db219973
MC		 7205static inline void tg3_reset_task_schedule(struct tg3 *tp)
7206{
7207 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7208 schedule_work(&tp->reset_task);
7209}
7210
7211static inline void tg3_reset_task_cancel(struct tg3 *tp)
7212{
7213 cancel_work_sync(&tp->reset_task);
7214 tg3_flag_clear(tp, RESET_TASK_PENDING);
c7101359 7215 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
db219973
MC		 7216}
7217
35f2d7d0
MC		 7218static int tg3_poll_msix(struct napi_struct *napi, int budget)
7219{
7220 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7221 struct tg3 *tp = tnapi->tp;
7222 int work_done = 0;
7223 struct tg3_hw_status *sblk = tnapi->hw_status;
7224
7225 while (1) {
7226 work_done = tg3_poll_work(tnapi, work_done, budget);
7227
63c3a66f 7228 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
35f2d7d0
MC		 7229 goto tx_recovery;
7230
7231 if (unlikely(work_done >= budget))
7232 break;
7233
c6cdf436 7234 /* tp->last_tag is used in tg3_int_reenable() below
35f2d7d0
MC		 7235 * to tell the hw how much work has been processed,
7236 * so we must read it before checking for more work.
7237 */
7238 tnapi->last_tag = sblk->status_tag;
7239 tnapi->last_irq_tag = tnapi->last_tag;
7240 rmb();
7241
7242 /* check for RX/TX work to do */
6d40db7b
MC		 7243 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7244 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7ae52890
MC		 7245
7246 /* This test here is not race free, but will reduce
7247 * the number of interrupts by looping again.
7248 */
7249 if (tnapi == &tp->napi[1] && tp->rx_refill)
7250 continue;
7251
35f2d7d0
MC		 7252 napi_complete(napi);
7253 /* Reenable interrupts. */
7254 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7ae52890
MC		 7255
7256 /* This test here is synchronized by napi_schedule()
7257 * and napi_complete() to close the race condition.
7258 */
7259 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7260 tw32(HOSTCC_MODE, tp->coalesce_mode |
7261 HOSTCC_MODE_ENABLE |
7262 tnapi->coal_now);
7263 }
35f2d7d0
MC		 7264 mmiowb();
7265 break;
7266 }
7267 }
7268
7269 return work_done;
7270
7271tx_recovery:
7272 /* work_done is guaranteed to be less than budget. */
7273 napi_complete(napi);
db219973 7274 tg3_reset_task_schedule(tp);
35f2d7d0
MC		 7275 return work_done;
7276}
7277
e64de4e6
MC		 7278static void tg3_process_error(struct tg3 *tp)
7279{
7280 u32 val;
7281 bool real_error = false;
7282
63c3a66f 7283 if (tg3_flag(tp, ERROR_PROCESSED))
e64de4e6
MC		 7284 return;
7285
7286 /* Check Flow Attention register */
7287 val = tr32(HOSTCC_FLOW_ATTN);
7288 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7289 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7290 real_error = true;
7291 }
7292
7293 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7294 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7295 real_error = true;
7296 }
7297
7298 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7299 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7300 real_error = true;
7301 }
7302
7303 if (!real_error)
7304 return;
7305
7306 tg3_dump_state(tp);
7307
63c3a66f 7308 tg3_flag_set(tp, ERROR_PROCESSED);
db219973 7309 tg3_reset_task_schedule(tp);
e64de4e6
MC		 7310}
7311
6f535763
DM		 7312static int tg3_poll(struct napi_struct *napi, int budget)
7313{
8ef0442f
MC		 7314 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7315 struct tg3 *tp = tnapi->tp;
6f535763 7316 int work_done = 0;
898a56f8 7317 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 7318
7319 while (1) {
e64de4e6
MC		 7320 if (sblk->status & SD_STATUS_ERROR)
7321 tg3_process_error(tp);
7322
35f2d7d0
MC		 7323 tg3_poll_link(tp);
7324
17375d25 7325 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763 7326
63c3a66f 7327 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6f535763
DM		 7328 goto tx_recovery;
7329
7330 if (unlikely(work_done >= budget))
7331 break;
7332
63c3a66f 7333 if (tg3_flag(tp, TAGGED_STATUS)) {
17375d25 7334 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 7335 * to tell the hw how much work has been processed,
7336 * so we must read it before checking for more work.
7337 */
898a56f8
MC		 7338 tnapi->last_tag = sblk->status_tag;
7339 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 7340 rmb();
7341 } else
7342 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 7343
17375d25 7344 if (likely(!tg3_has_work(tnapi))) {
288379f0 7345 napi_complete(napi);
17375d25 7346 tg3_int_reenable(tnapi);
6f535763
DM		 7347 break;
7348 }
1da177e4
LT		 7349 }
7350
bea3348e 7351 return work_done;
6f535763
DM		 7352
7353tx_recovery:
4fd7ab59 7354 /* work_done is guaranteed to be less than budget. */
288379f0 7355 napi_complete(napi);
db219973 7356 tg3_reset_task_schedule(tp);
4fd7ab59 7357 return work_done;
1da177e4
LT		 7358}
7359
66cfd1bd
MC		 7360static void tg3_napi_disable(struct tg3 *tp)
7361{
7362 int i;
7363
7364 for (i = tp->irq_cnt - 1; i >= 0; i--)
7365 napi_disable(&tp->napi[i].napi);
7366}
7367
7368static void tg3_napi_enable(struct tg3 *tp)
7369{
7370 int i;
7371
7372 for (i = 0; i < tp->irq_cnt; i++)
7373 napi_enable(&tp->napi[i].napi);
7374}
7375
7376static void tg3_napi_init(struct tg3 *tp)
7377{
7378 int i;
7379
7380 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7381 for (i = 1; i < tp->irq_cnt; i++)
7382 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7383}
7384
7385static void tg3_napi_fini(struct tg3 *tp)
7386{
7387 int i;
7388
7389 for (i = 0; i < tp->irq_cnt; i++)
7390 netif_napi_del(&tp->napi[i].napi);
7391}
7392
7393static inline void tg3_netif_stop(struct tg3 *tp)
7394{
7395 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7396 tg3_napi_disable(tp);
f4a46d1f 7397 netif_carrier_off(tp->dev);
66cfd1bd
MC		 7398 netif_tx_disable(tp->dev);
7399}
7400
35763066 7401/* tp->lock must be held */
66cfd1bd
MC		 7402static inline void tg3_netif_start(struct tg3 *tp)
7403{
be947307
MC		 7404 tg3_ptp_resume(tp);
7405
66cfd1bd
MC		 7406 /* NOTE: unconditional netif_tx_wake_all_queues is only
7407 * appropriate so long as all callers are assured to
7408 * have free tx slots (such as after tg3_init_hw)
7409 */
7410 netif_tx_wake_all_queues(tp->dev);
7411
f4a46d1f
NNS		 7412 if (tp->link_up)
7413 netif_carrier_on(tp->dev);
7414
66cfd1bd
MC		 7415 tg3_napi_enable(tp);
7416 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7417 tg3_enable_ints(tp);
7418}
7419
f47c11ee
DM		 7420static void tg3_irq_quiesce(struct tg3 *tp)
7421{
4f125f42
MC		 7422 int i;
7423
f47c11ee
DM		 7424 BUG_ON(tp->irq_sync);
7425
7426 tp->irq_sync = 1;
7427 smp_mb();
7428
4f125f42
MC		 7429 for (i = 0; i < tp->irq_cnt; i++)
7430 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 7431}
7432
f47c11ee
DM		 7433/* Fully shutdown all tg3 driver activity elsewhere in the system.
7434 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7435 * with as well. Most of the time, this is not necessary except when
7436 * shutting down the device.
7437 */
7438static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7439{
46966545 7440 spin_lock_bh(&tp->lock);
f47c11ee
DM		 7441 if (irq_sync)
7442 tg3_irq_quiesce(tp);
f47c11ee
DM		 7443}
7444
7445static inline void tg3_full_unlock(struct tg3 *tp)
7446{
f47c11ee
DM		 7447 spin_unlock_bh(&tp->lock);
7448}
7449
fcfa0a32
MC		 7450/* One-shot MSI handler - Chip automatically disables interrupt
7451 * after sending MSI so driver doesn't have to do it.
7452 */
7d12e780 7453static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 7454{
09943a18
MC		 7455 struct tg3_napi *tnapi = dev_id;
7456 struct tg3 *tp = tnapi->tp;
fcfa0a32 7457
898a56f8 7458 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7459 if (tnapi->rx_rcb)
7460 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 7461
7462 if (likely(!tg3_irq_sync(tp)))
09943a18 7463 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 7464
7465 return IRQ_HANDLED;
7466}
7467
88b06bc2
MC		 7468/* MSI ISR - No need to check for interrupt sharing and no need to
7469 * flush status block and interrupt mailbox. PCI ordering rules
7470 * guarantee that MSI will arrive after the status block.
7471 */
7d12e780 7472static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 7473{
09943a18
MC		 7474 struct tg3_napi *tnapi = dev_id;
7475 struct tg3 *tp = tnapi->tp;
88b06bc2 7476
898a56f8 7477 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7478 if (tnapi->rx_rcb)
7479 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 7480 /*
fac9b83e 7481 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 7482 * chip-internal interrupt pending events.
fac9b83e 7483 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 7484 * NIC to stop sending us irqs, engaging "in-intr-handler"
7485 * event coalescing.
7486 */
5b39de91 7487 tw32_mailbox(tnapi->int_mbox, 0x00000001);
61487480 7488 if (likely(!tg3_irq_sync(tp)))
09943a18 7489 napi_schedule(&tnapi->napi);
61487480 7490
88b06bc2
MC		 7491 return IRQ_RETVAL(1);
7492}
7493
7d12e780 7494static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 7495{
09943a18
MC		 7496 struct tg3_napi *tnapi = dev_id;
7497 struct tg3 *tp = tnapi->tp;
898a56f8 7498 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 7499 unsigned int handled = 1;
7500
1da177e4
LT		 7501 /* In INTx mode, it is possible for the interrupt to arrive at
7502 * the CPU before the status block posted prior to the interrupt.
7503 * Reading the PCI State register will confirm whether the
7504 * interrupt is ours and will flush the status block.
7505 */
d18edcb2 7506 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
63c3a66f 7507 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7508 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7509 handled = 0;
f47c11ee 7510 goto out;
fac9b83e 7511 }
d18edcb2
MC		 7512 }
7513
7514 /*
7515 * Writing any value to intr-mbox-0 clears PCI INTA# and
7516 * chip-internal interrupt pending events.
7517 * Writing non-zero to intr-mbox-0 additional tells the
7518 * NIC to stop sending us irqs, engaging "in-intr-handler"
7519 * event coalescing.
c04cb347
MC		 7520 *
7521 * Flush the mailbox to de-assert the IRQ immediately to prevent
7522 * spurious interrupts. The flush impacts performance but
7523 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7524 */
c04cb347 7525 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 7526 if (tg3_irq_sync(tp))
7527 goto out;
7528 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 7529 if (likely(tg3_has_work(tnapi))) {
72334482 7530 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 7531 napi_schedule(&tnapi->napi);
d18edcb2
MC		 7532 } else {
7533 /* No work, shared interrupt perhaps? re-enable
7534 * interrupts, and flush that PCI write
7535 */
7536 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7537 0x00000000);
fac9b83e 7538 }
f47c11ee 7539out:
fac9b83e
DM		 7540 return IRQ_RETVAL(handled);
7541}
7542
7d12e780 7543static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 7544{
09943a18
MC		 7545 struct tg3_napi *tnapi = dev_id;
7546 struct tg3 *tp = tnapi->tp;
898a56f8 7547 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 7548 unsigned int handled = 1;
7549
fac9b83e
DM		 7550 /* In INTx mode, it is possible for the interrupt to arrive at
7551 * the CPU before the status block posted prior to the interrupt.
7552 * Reading the PCI State register will confirm whether the
7553 * interrupt is ours and will flush the status block.
7554 */
898a56f8 7555 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
63c3a66f 7556 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7557 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7558 handled = 0;
f47c11ee 7559 goto out;
1da177e4 7560 }
d18edcb2
MC		 7561 }
7562
7563 /*
7564 * writing any value to intr-mbox-0 clears PCI INTA# and
7565 * chip-internal interrupt pending events.
7566 * writing non-zero to intr-mbox-0 additional tells the
7567 * NIC to stop sending us irqs, engaging "in-intr-handler"
7568 * event coalescing.
c04cb347
MC		 7569 *
7570 * Flush the mailbox to de-assert the IRQ immediately to prevent
7571 * spurious interrupts. The flush impacts performance but
7572 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7573 */
c04cb347 7574 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 7575
7576 /*
7577 * In a shared interrupt configuration, sometimes other devices'
7578 * interrupts will scream. We record the current status tag here
7579 * so that the above check can report that the screaming interrupts
7580 * are unhandled. Eventually they will be silenced.
7581 */
898a56f8 7582 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 7583
d18edcb2
MC		 7584 if (tg3_irq_sync(tp))
7585 goto out;
624f8e50 7586
72334482 7587 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 7588
09943a18 7589 napi_schedule(&tnapi->napi);
624f8e50 7590
f47c11ee 7591out:
1da177e4
LT		 7592 return IRQ_RETVAL(handled);
7593}
7594
7938109f 7595/* ISR for interrupt test */
7d12e780 7596static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 7597{
09943a18
MC		 7598 struct tg3_napi *tnapi = dev_id;
7599 struct tg3 *tp = tnapi->tp;
898a56f8 7600 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 7601
f9804ddb
MC		 7602 if ((sblk->status & SD_STATUS_UPDATED) ||
7603 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 7604 tg3_disable_ints(tp);
7938109f
MC		 7605 return IRQ_RETVAL(1);
7606 }
7607 return IRQ_RETVAL(0);
7608}
7609
1da177e4
LT		 7610#ifdef CONFIG_NET_POLL_CONTROLLER
7611static void tg3_poll_controller(struct net_device *dev)
7612{
4f125f42 7613 int i;
88b06bc2
MC		 7614 struct tg3 *tp = netdev_priv(dev);
7615
9c13cb8b
NNS		 7616 if (tg3_irq_sync(tp))
7617 return;
7618
4f125f42 7619 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 7620 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 7621}
7622#endif
7623
1da177e4
LT		 7624static void tg3_tx_timeout(struct net_device *dev)
7625{
7626 struct tg3 *tp = netdev_priv(dev);
7627
b0408751 7628 if (netif_msg_tx_err(tp)) {
05dbe005 7629 netdev_err(dev, "transmit timed out, resetting\n");
97bd8e49 7630 tg3_dump_state(tp);
b0408751 7631 }
1da177e4 7632
db219973 7633 tg3_reset_task_schedule(tp);
1da177e4
LT		 7634}
7635
c58ec932
MC		 7636/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7637static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7638{
7639 u32 base = (u32) mapping & 0xffffffff;
7640
807540ba 7641 return (base > 0xffffdcc0) && (base + len + 8 < base);
c58ec932
MC		 7642}
7643
0f0d1510
MC		 7644/* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7645 * of any 4GB boundaries: 4G, 8G, etc
7646 */
7647static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7648 u32 len, u32 mss)
7649{
7650 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7651 u32 base = (u32) mapping & 0xffffffff;
7652
7653 return ((base + len + (mss & 0x3fff)) < base);
7654 }
7655 return 0;
7656}
7657
72f2afb8
MC		 7658/* Test for DMA addresses > 40-bit */
7659static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7660 int len)
7661{
7662#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
63c3a66f 7663 if (tg3_flag(tp, 40BIT_DMA_BUG))
807540ba 7664 return ((u64) mapping + len) > DMA_BIT_MASK(40);
72f2afb8
MC		 7665 return 0;
7666#else
7667 return 0;
7668#endif
7669}
7670
d1a3b737 7671static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
92cd3a17
MC		 7672 dma_addr_t mapping, u32 len, u32 flags,
7673 u32 mss, u32 vlan)
2ffcc981 7674{
92cd3a17
MC		 7675 txbd->addr_hi = ((u64) mapping >> 32);
7676 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7677 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7678 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
2ffcc981 7679}
1da177e4 7680
84b67b27 7681static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
d1a3b737
MC		 7682 dma_addr_t map, u32 len, u32 flags,
7683 u32 mss, u32 vlan)
7684{
7685 struct tg3 *tp = tnapi->tp;
7686 bool hwbug = false;
7687
7688 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
3db1cd5c 7689 hwbug = true;
d1a3b737
MC		 7690
7691 if (tg3_4g_overflow_test(map, len))
3db1cd5c 7692 hwbug = true;
d1a3b737 7693
0f0d1510
MC		 7694 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7695 hwbug = true;
7696
d1a3b737 7697 if (tg3_40bit_overflow_test(tp, map, len))
3db1cd5c 7698 hwbug = true;
d1a3b737 7699
a4cb428d 7700 if (tp->dma_limit) {
b9e45482 7701 u32 prvidx = *entry;
e31aa987 7702 u32 tmp_flag = flags & ~TXD_FLAG_END;
a4cb428d
MC		 7703 while (len > tp->dma_limit && *budget) {
7704 u32 frag_len = tp->dma_limit;
7705 len -= tp->dma_limit;
e31aa987 7706
b9e45482
MC		 7707 /* Avoid the 8byte DMA problem */
7708 if (len <= 8) {
a4cb428d
MC		 7709 len += tp->dma_limit / 2;
7710 frag_len = tp->dma_limit / 2;
e31aa987
MC		 7711 }
7712
b9e45482
MC		 7713 tnapi->tx_buffers[*entry].fragmented = true;
7714
7715 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7716 frag_len, tmp_flag, mss, vlan);
7717 *budget -= 1;
7718 prvidx = *entry;
7719 *entry = NEXT_TX(*entry);
7720
e31aa987
MC		 7721 map += frag_len;
7722 }
7723
7724 if (len) {
7725 if (*budget) {
7726 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7727 len, flags, mss, vlan);
b9e45482 7728 *budget -= 1;
e31aa987
MC		 7729 *entry = NEXT_TX(*entry);
7730 } else {
3db1cd5c 7731 hwbug = true;
b9e45482 7732 tnapi->tx_buffers[prvidx].fragmented = false;
e31aa987
MC		 7733 }
7734 }
7735 } else {
84b67b27
MC		 7736 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7737 len, flags, mss, vlan);
e31aa987
MC		 7738 *entry = NEXT_TX(*entry);
7739 }
d1a3b737
MC		 7740
7741 return hwbug;
7742}
7743
0d681b27 7744static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
432aa7ed
MC		 7745{
7746 int i;
0d681b27 7747 struct sk_buff *skb;
df8944cf 7748 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
432aa7ed 7749
0d681b27
MC		 7750 skb = txb->skb;
7751 txb->skb = NULL;
7752
432aa7ed
MC		 7753 pci_unmap_single(tnapi->tp->pdev,
7754 dma_unmap_addr(txb, mapping),
7755 skb_headlen(skb),
7756 PCI_DMA_TODEVICE);
e01ee14d
MC		 7757
7758 while (txb->fragmented) {
7759 txb->fragmented = false;
7760 entry = NEXT_TX(entry);
7761 txb = &tnapi->tx_buffers[entry];
7762 }
7763
ba1142e4 7764 for (i = 0; i <= last; i++) {
9e903e08 7765 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
432aa7ed
MC		 7766
7767 entry = NEXT_TX(entry);
7768 txb = &tnapi->tx_buffers[entry];
7769
7770 pci_unmap_page(tnapi->tp->pdev,
7771 dma_unmap_addr(txb, mapping),
9e903e08 7772 skb_frag_size(frag), PCI_DMA_TODEVICE);
e01ee14d
MC		 7773
7774 while (txb->fragmented) {
7775 txb->fragmented = false;
7776 entry = NEXT_TX(entry);
7777 txb = &tnapi->tx_buffers[entry];
7778 }
432aa7ed
MC		 7779 }
7780}
7781
72f2afb8 7782/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4 7783static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
f7ff1987 7784 struct sk_buff **pskb,
84b67b27 7785 u32 *entry, u32 *budget,
92cd3a17 7786 u32 base_flags, u32 mss, u32 vlan)
1da177e4 7787{
24f4efd4 7788 struct tg3 *tp = tnapi->tp;
f7ff1987 7789 struct sk_buff *new_skb, *skb = *pskb;
c58ec932 7790 dma_addr_t new_addr = 0;
432aa7ed 7791 int ret = 0;
1da177e4 7792
4153577a 7793 if (tg3_asic_rev(tp) != ASIC_REV_5701)
41588ba1
MC		 7794 new_skb = skb_copy(skb, GFP_ATOMIC);
7795 else {
7796 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7797
7798 new_skb = skb_copy_expand(skb,
7799 skb_headroom(skb) + more_headroom,
7800 skb_tailroom(skb), GFP_ATOMIC);
7801 }
7802
1da177e4 7803 if (!new_skb) {
c58ec932
MC		 7804 ret = -1;
7805 } else {
7806 /* New SKB is guaranteed to be linear. */
f4188d8a
AD		 7807 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7808 PCI_DMA_TODEVICE);
7809 /* Make sure the mapping succeeded */
7810 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
f4188d8a 7811 dev_kfree_skb(new_skb);
c58ec932 7812 ret = -1;
c58ec932 7813 } else {
b9e45482
MC		 7814 u32 save_entry = *entry;
7815
92cd3a17
MC		 7816 base_flags |= TXD_FLAG_END;
7817
84b67b27
MC		 7818 tnapi->tx_buffers[*entry].skb = new_skb;
7819 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
432aa7ed
MC		 7820 mapping, new_addr);
7821
84b67b27 7822 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
d1a3b737
MC		 7823 new_skb->len, base_flags,
7824 mss, vlan)) {
ba1142e4 7825 tg3_tx_skb_unmap(tnapi, save_entry, -1);
d1a3b737
MC		 7826 dev_kfree_skb(new_skb);
7827 ret = -1;
7828 }
f4188d8a 7829 }
1da177e4
LT		 7830 }
7831
7832 dev_kfree_skb(skb);
f7ff1987 7833 *pskb = new_skb;
c58ec932 7834 return ret;
1da177e4
LT		 7835}
7836
2ffcc981 7837static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
52c0fd83
MC		 7838
7839/* Use GSO to workaround a rare TSO bug that may be triggered when the
7840 * TSO header is greater than 80 bytes.
7841 */
7842static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
7843{
7844 struct sk_buff *segs, *nskb;
f3f3f27e 7845 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 7846
7847 /* Estimate the number of fragments in the worst case */
f3f3f27e 7848 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 7849 netif_stop_queue(tp->dev);
f65aac16
MC		 7850
7851 /* netif_tx_stop_queue() must be done before checking
7852 * checking tx index in tg3_tx_avail() below, because in
7853 * tg3_tx(), we update tx index before checking for
7854 * netif_tx_queue_stopped().
7855 */
7856 smp_mb();
f3f3f27e 7857 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 7858 return NETDEV_TX_BUSY;
7859
7860 netif_wake_queue(tp->dev);
52c0fd83
MC		 7861 }
7862
7863 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 7864 if (IS_ERR(segs))
52c0fd83
MC		 7865 goto tg3_tso_bug_end;
7866
7867 do {
7868 nskb = segs;
7869 segs = segs->next;
7870 nskb->next = NULL;
2ffcc981 7871 tg3_start_xmit(nskb, tp->dev);
52c0fd83
MC		 7872 } while (segs);
7873
7874tg3_tso_bug_end:
7875 dev_kfree_skb(skb);
7876
7877 return NETDEV_TX_OK;
7878}
52c0fd83 7879
5a6f3074 7880/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
63c3a66f 7881 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
5a6f3074 7882 */
2ffcc981 7883static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 7884{
7885 struct tg3 *tp = netdev_priv(dev);
92cd3a17 7886 u32 len, entry, base_flags, mss, vlan = 0;
84b67b27 7887 u32 budget;
432aa7ed 7888 int i = -1, would_hit_hwbug;
90079ce8 7889 dma_addr_t mapping;
24f4efd4
MC		 7890 struct tg3_napi *tnapi;
7891 struct netdev_queue *txq;
432aa7ed 7892 unsigned int last;
f4188d8a 7893
24f4efd4
MC		 7894 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7895 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
63c3a66f 7896 if (tg3_flag(tp, ENABLE_TSS))
24f4efd4 7897 tnapi++;
1da177e4 7898
84b67b27
MC		 7899 budget = tg3_tx_avail(tnapi);
7900
00b70504 7901 /* We are running in BH disabled context with netif_tx_lock
bea3348e 7902 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 7903 * interrupt. Furthermore, IRQ processing runs lockless so we have
7904 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 7905 */
84b67b27 7906 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 7907 if (!netif_tx_queue_stopped(txq)) {
7908 netif_tx_stop_queue(txq);
1f064a87
SH		 7909
7910 /* This is a hard error, log it. */
5129c3a3
MC		 7911 netdev_err(dev,
7912 "BUG! Tx Ring full when queue awake!\n");
1f064a87 7913 }
1da177e4
LT		 7914 return NETDEV_TX_BUSY;
7915 }
7916
f3f3f27e 7917 entry = tnapi->tx_prod;
1da177e4 7918 base_flags = 0;
84fa7933 7919 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 7920 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 7921
be98da6a
MC		 7922 mss = skb_shinfo(skb)->gso_size;
7923 if (mss) {
eddc9ec5 7924 struct iphdr *iph;
34195c3d 7925 u32 tcp_opt_len, hdr_len;
1da177e4
LT		 7926
7927 if (skb_header_cloned(skb) &&
48855432
ED		 7928 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7929 goto drop;
1da177e4 7930
34195c3d 7931 iph = ip_hdr(skb);
ab6a5bb6 7932 tcp_opt_len = tcp_optlen(skb);
1da177e4 7933
a5a11955 7934 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
34195c3d 7935
a5a11955 7936 if (!skb_is_gso_v6(skb)) {
34195c3d
MC		 7937 iph->check = 0;
7938 iph->tot_len = htons(mss + hdr_len);
7939 }
7940
52c0fd83 7941 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
63c3a66f 7942 tg3_flag(tp, TSO_BUG))
de6f31eb 7943 return tg3_tso_bug(tp, skb);
52c0fd83 7944
1da177e4
LT		 7945 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7946 TXD_FLAG_CPU_POST_DMA);
7947
63c3a66f
JP		 7948 if (tg3_flag(tp, HW_TSO_1) ||
7949 tg3_flag(tp, HW_TSO_2) ||
7950 tg3_flag(tp, HW_TSO_3)) {
aa8223c7 7951 tcp_hdr(skb)->check = 0;
1da177e4 7952 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 7953 } else
7954 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7955 iph->daddr, 0,
7956 IPPROTO_TCP,
7957 0);
1da177e4 7958
63c3a66f 7959 if (tg3_flag(tp, HW_TSO_3)) {
615774fe
MC		 7960 mss |= (hdr_len & 0xc) << 12;
7961 if (hdr_len & 0x10)
7962 base_flags |= 0x00000010;
7963 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 7964 } else if (tg3_flag(tp, HW_TSO_2))
92c6b8d1 7965 mss |= hdr_len << 9;
63c3a66f 7966 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 7967 tg3_asic_rev(tp) == ASIC_REV_5705) {
eddc9ec5 7968 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7969 int tsflags;
7970
eddc9ec5 7971 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7972 mss |= (tsflags << 11);
7973 }
7974 } else {
eddc9ec5 7975 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7976 int tsflags;
7977
eddc9ec5 7978 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7979 base_flags |= tsflags << 12;
7980 }
7981 }
7982 }
bf933c80 7983
93a700a9
MC		 7984 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7985 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7986 base_flags |= TXD_FLAG_JMB_PKT;
7987
92cd3a17
MC		 7988 if (vlan_tx_tag_present(skb)) {
7989 base_flags |= TXD_FLAG_VLAN;
7990 vlan = vlan_tx_tag_get(skb);
7991 }
1da177e4 7992
fb4ce8ad
MC		 7993 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
7994 tg3_flag(tp, TX_TSTAMP_EN)) {
7995 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7996 base_flags |= TXD_FLAG_HWTSTAMP;
7997 }
7998
f4188d8a
AD		 7999 len = skb_headlen(skb);
8000
8001 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
48855432
ED		 8002 if (pci_dma_mapping_error(tp->pdev, mapping))
8003 goto drop;
8004
90079ce8 8005
f3f3f27e 8006 tnapi->tx_buffers[entry].skb = skb;
4e5e4f0d 8007 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 8008
8009 would_hit_hwbug = 0;
8010
63c3a66f 8011 if (tg3_flag(tp, 5701_DMA_BUG))
c58ec932 8012 would_hit_hwbug = 1;
1da177e4 8013
84b67b27 8014 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
d1a3b737 8015 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
ba1142e4 8016 mss, vlan)) {
d1a3b737 8017 would_hit_hwbug = 1;
ba1142e4 8018 } else if (skb_shinfo(skb)->nr_frags > 0) {
92cd3a17
MC		 8019 u32 tmp_mss = mss;
8020
8021 if (!tg3_flag(tp, HW_TSO_1) &&
8022 !tg3_flag(tp, HW_TSO_2) &&
8023 !tg3_flag(tp, HW_TSO_3))
8024 tmp_mss = 0;
8025
c5665a53
MC		 8026 /* Now loop through additional data
8027 * fragments, and queue them.
8028 */
1da177e4
LT		 8029 last = skb_shinfo(skb)->nr_frags - 1;
8030 for (i = 0; i <= last; i++) {
8031 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8032
9e903e08 8033 len = skb_frag_size(frag);
dc234d0b 8034 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
5d6bcdfe 8035 len, DMA_TO_DEVICE);
1da177e4 8036
f3f3f27e 8037 tnapi->tx_buffers[entry].skb = NULL;
4e5e4f0d 8038 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
f4188d8a 8039 mapping);
5d6bcdfe 8040 if (dma_mapping_error(&tp->pdev->dev, mapping))
f4188d8a 8041 goto dma_error;
1da177e4 8042
b9e45482
MC		 8043 if (!budget ||
8044 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
84b67b27
MC		 8045 len, base_flags |
8046 ((i == last) ? TXD_FLAG_END : 0),
b9e45482 8047 tmp_mss, vlan)) {
72f2afb8 8048 would_hit_hwbug = 1;
b9e45482
MC		 8049 break;
8050 }
1da177e4
LT		 8051 }
8052 }
8053
8054 if (would_hit_hwbug) {
0d681b27 8055 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
1da177e4
LT		 8056
8057 /* If the workaround fails due to memory/mapping
8058 * failure, silently drop this packet.
8059 */
84b67b27
MC		 8060 entry = tnapi->tx_prod;
8061 budget = tg3_tx_avail(tnapi);
f7ff1987 8062 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
84b67b27 8063 base_flags, mss, vlan))
48855432 8064 goto drop_nofree;
1da177e4
LT		 8065 }
8066
d515b450 8067 skb_tx_timestamp(skb);
5cb917bc 8068 netdev_tx_sent_queue(txq, skb->len);
d515b450 8069
6541b806
MC		 8070 /* Sync BD data before updating mailbox */
8071 wmb();
8072
1da177e4 8073 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 8074 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 8075
f3f3f27e
MC		 8076 tnapi->tx_prod = entry;
8077 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 8078 netif_tx_stop_queue(txq);
f65aac16
MC		 8079
8080 /* netif_tx_stop_queue() must be done before checking
8081 * checking tx index in tg3_tx_avail() below, because in
8082 * tg3_tx(), we update tx index before checking for
8083 * netif_tx_queue_stopped().
8084 */
8085 smp_mb();
f3f3f27e 8086 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 8087 netif_tx_wake_queue(txq);
51b91468 8088 }
1da177e4 8089
cdd0db05 8090 mmiowb();
1da177e4 8091 return NETDEV_TX_OK;
f4188d8a
AD		 8092
8093dma_error:
ba1142e4 8094 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
432aa7ed 8095 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
48855432
ED		 8096drop:
8097 dev_kfree_skb(skb);
8098drop_nofree:
8099 tp->tx_dropped++;
f4188d8a 8100 return NETDEV_TX_OK;
1da177e4
LT		 8101}
8102
6e01b20b
MC		 8103static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8104{
8105 if (enable) {
8106 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8107 MAC_MODE_PORT_MODE_MASK);
8108
8109 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8110
8111 if (!tg3_flag(tp, 5705_PLUS))
8112 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8113
8114 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8115 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8116 else
8117 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8118 } else {
8119 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8120
8121 if (tg3_flag(tp, 5705_PLUS) ||
8122 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
4153577a 8123 tg3_asic_rev(tp) == ASIC_REV_5700)
6e01b20b
MC		 8124 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8125 }
8126
8127 tw32(MAC_MODE, tp->mac_mode);
8128 udelay(40);
8129}
8130
941ec90f 8131static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
5e5a7f37 8132{
941ec90f 8133 u32 val, bmcr, mac_mode, ptest = 0;
5e5a7f37
MC		 8134
8135 tg3_phy_toggle_apd(tp, false);
953c96e0 8136 tg3_phy_toggle_automdix(tp, false);
5e5a7f37 8137
941ec90f
MC		 8138 if (extlpbk && tg3_phy_set_extloopbk(tp))
8139 return -EIO;
8140
8141 bmcr = BMCR_FULLDPLX;
5e5a7f37
MC		 8142 switch (speed) {
8143 case SPEED_10:
8144 break;
8145 case SPEED_100:
8146 bmcr |= BMCR_SPEED100;
8147 break;
8148 case SPEED_1000:
8149 default:
8150 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8151 speed = SPEED_100;
8152 bmcr |= BMCR_SPEED100;
8153 } else {
8154 speed = SPEED_1000;
8155 bmcr |= BMCR_SPEED1000;
8156 }
8157 }
8158
941ec90f
MC		 8159 if (extlpbk) {
8160 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8161 tg3_readphy(tp, MII_CTRL1000, &val);
8162 val |= CTL1000_AS_MASTER |
8163 CTL1000_ENABLE_MASTER;
8164 tg3_writephy(tp, MII_CTRL1000, val);
8165 } else {
8166 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8167 MII_TG3_FET_PTEST_TRIM_2;
8168 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8169 }
8170 } else
8171 bmcr |= BMCR_LOOPBACK;
8172
5e5a7f37
MC		 8173 tg3_writephy(tp, MII_BMCR, bmcr);
8174
8175 /* The write needs to be flushed for the FETs */
8176 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8177 tg3_readphy(tp, MII_BMCR, &bmcr);
8178
8179 udelay(40);
8180
8181 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a 8182 tg3_asic_rev(tp) == ASIC_REV_5785) {
941ec90f 8183 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
5e5a7f37
MC		 8184 MII_TG3_FET_PTEST_FRC_TX_LINK |
8185 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8186
8187 /* The write needs to be flushed for the AC131 */
8188 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8189 }
8190
8191 /* Reset to prevent losing 1st rx packet intermittently */
8192 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8193 tg3_flag(tp, 5780_CLASS)) {
8194 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8195 udelay(10);
8196 tw32_f(MAC_RX_MODE, tp->rx_mode);
8197 }
8198
8199 mac_mode = tp->mac_mode &
8200 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8201 if (speed == SPEED_1000)
8202 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8203 else
8204 mac_mode |= MAC_MODE_PORT_MODE_MII;
8205
4153577a 8206 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5e5a7f37
MC		 8207 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8208
8209 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8210 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8211 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8212 mac_mode |= MAC_MODE_LINK_POLARITY;
8213
8214 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8215 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8216 }
8217
8218 tw32(MAC_MODE, mac_mode);
8219 udelay(40);
941ec90f
MC		 8220
8221 return 0;
5e5a7f37
MC		 8222}
8223
c8f44aff 8224static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
06c03c02
MB		 8225{
8226 struct tg3 *tp = netdev_priv(dev);
8227
8228 if (features & NETIF_F_LOOPBACK) {
8229 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8230 return;
8231
06c03c02 8232 spin_lock_bh(&tp->lock);
6e01b20b 8233 tg3_mac_loopback(tp, true);
06c03c02
MB		 8234 netif_carrier_on(tp->dev);
8235 spin_unlock_bh(&tp->lock);
8236 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8237 } else {
8238 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8239 return;
8240
06c03c02 8241 spin_lock_bh(&tp->lock);
6e01b20b 8242 tg3_mac_loopback(tp, false);
06c03c02 8243 /* Force link status check */
953c96e0 8244 tg3_setup_phy(tp, true);
06c03c02
MB		 8245 spin_unlock_bh(&tp->lock);
8246 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8247 }
8248}
8249
c8f44aff
MM		 8250static netdev_features_t tg3_fix_features(struct net_device *dev,
8251 netdev_features_t features)
dc668910
MM		 8252{
8253 struct tg3 *tp = netdev_priv(dev);
8254
63c3a66f 8255 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
dc668910
MM		 8256 features &= ~NETIF_F_ALL_TSO;
8257
8258 return features;
8259}
8260
c8f44aff 8261static int tg3_set_features(struct net_device *dev, netdev_features_t features)
06c03c02 8262{
c8f44aff 8263 netdev_features_t changed = dev->features ^ features;
06c03c02
MB		 8264
8265 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8266 tg3_set_loopback(dev, features);
8267
8268 return 0;
8269}
8270
21f581a5
MC		 8271static void tg3_rx_prodring_free(struct tg3 *tp,
8272 struct tg3_rx_prodring_set *tpr)
1da177e4 8273{
1da177e4
LT		 8274 int i;
8275
8fea32b9 8276 if (tpr != &tp->napi[0].prodring) {
b196c7e4 8277 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
2c49a44d 8278 i = (i + 1) & tp->rx_std_ring_mask)
9205fd9c 8279 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
b196c7e4
MC		 8280 tp->rx_pkt_map_sz);
8281
63c3a66f 8282 if (tg3_flag(tp, JUMBO_CAPABLE)) {
b196c7e4
MC		 8283 for (i = tpr->rx_jmb_cons_idx;
8284 i != tpr->rx_jmb_prod_idx;
2c49a44d 8285 i = (i + 1) & tp->rx_jmb_ring_mask) {
9205fd9c 8286 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
b196c7e4
MC		 8287 TG3_RX_JMB_MAP_SZ);
8288 }
8289 }
8290
2b2cdb65 8291 return;
b196c7e4 8292 }
1da177e4 8293
2c49a44d 8294 for (i = 0; i <= tp->rx_std_ring_mask; i++)
9205fd9c 8295 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
2b2cdb65 8296 tp->rx_pkt_map_sz);
1da177e4 8297
63c3a66f 8298 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8299 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
9205fd9c 8300 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
2b2cdb65 8301 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 8302 }
8303}
8304
c6cdf436 8305/* Initialize rx rings for packet processing.
1da177e4
LT		 8306 *
8307 * The chip has been shut down and the driver detached from
8308 * the networking, so no interrupts or new tx packets will
8309 * end up in the driver. tp->{tx,}lock are held and thus
8310 * we may not sleep.
8311 */
21f581a5
MC		 8312static int tg3_rx_prodring_alloc(struct tg3 *tp,
8313 struct tg3_rx_prodring_set *tpr)
1da177e4 8314{
287be12e 8315 u32 i, rx_pkt_dma_sz;
1da177e4 8316
b196c7e4
MC		 8317 tpr->rx_std_cons_idx = 0;
8318 tpr->rx_std_prod_idx = 0;
8319 tpr->rx_jmb_cons_idx = 0;
8320 tpr->rx_jmb_prod_idx = 0;
8321
8fea32b9 8322 if (tpr != &tp->napi[0].prodring) {
2c49a44d
MC		 8323 memset(&tpr->rx_std_buffers[0], 0,
8324 TG3_RX_STD_BUFF_RING_SIZE(tp));
48035728 8325 if (tpr->rx_jmb_buffers)
2b2cdb65 8326 memset(&tpr->rx_jmb_buffers[0], 0,
2c49a44d 8327 TG3_RX_JMB_BUFF_RING_SIZE(tp));
2b2cdb65
MC		 8328 goto done;
8329 }
8330
1da177e4 8331 /* Zero out all descriptors. */
2c49a44d 8332 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
1da177e4 8333
287be12e 8334 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
63c3a66f 8335 if (tg3_flag(tp, 5780_CLASS) &&
287be12e
MC		 8336 tp->dev->mtu > ETH_DATA_LEN)
8337 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8338 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 8339
1da177e4
LT		 8340 /* Initialize invariants of the rings, we only set this
8341 * stuff once. This works because the card does not
8342 * write into the rx buffer posting rings.
8343 */
2c49a44d 8344 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
1da177e4
LT		 8345 struct tg3_rx_buffer_desc *rxd;
8346
21f581a5 8347 rxd = &tpr->rx_std[i];
287be12e 8348 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 8349 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8350 rxd->opaque = (RXD_OPAQUE_RING_STD |
8351 (i << RXD_OPAQUE_INDEX_SHIFT));
8352 }
8353
1da177e4
LT		 8354 /* Now allocate fresh SKBs for each rx ring. */
8355 for (i = 0; i < tp->rx_pending; i++) {
8d4057a9
ED		 8356 unsigned int frag_size;
8357
8358 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8359 &frag_size) < 0) {
5129c3a3
MC		 8360 netdev_warn(tp->dev,
8361 "Using a smaller RX standard ring. Only "
8362 "%d out of %d buffers were allocated "
8363 "successfully\n", i, tp->rx_pending);
32d8c572 8364 if (i == 0)
cf7a7298 8365 goto initfail;
32d8c572 8366 tp->rx_pending = i;
1da177e4 8367 break;
32d8c572 8368 }
1da177e4
LT		 8369 }
8370
63c3a66f 8371 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
cf7a7298
MC		 8372 goto done;
8373
2c49a44d 8374 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
cf7a7298 8375
63c3a66f 8376 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
0d86df80 8377 goto done;
cf7a7298 8378
2c49a44d 8379 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
0d86df80
MC		 8380 struct tg3_rx_buffer_desc *rxd;
8381
8382 rxd = &tpr->rx_jmb[i].std;
8383 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8384 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8385 RXD_FLAG_JUMBO;
8386 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8387 (i << RXD_OPAQUE_INDEX_SHIFT));
8388 }
8389
8390 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8d4057a9
ED		 8391 unsigned int frag_size;
8392
8393 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8394 &frag_size) < 0) {
5129c3a3
MC		 8395 netdev_warn(tp->dev,
8396 "Using a smaller RX jumbo ring. Only %d "
8397 "out of %d buffers were allocated "
8398 "successfully\n", i, tp->rx_jumbo_pending);
0d86df80
MC		 8399 if (i == 0)
8400 goto initfail;
8401 tp->rx_jumbo_pending = i;
8402 break;
1da177e4
LT		 8403 }
8404 }
cf7a7298
MC		 8405
8406done:
32d8c572 8407 return 0;
cf7a7298
MC		 8408
8409initfail:
21f581a5 8410 tg3_rx_prodring_free(tp, tpr);
cf7a7298 8411 return -ENOMEM;
1da177e4
LT		 8412}
8413
21f581a5
MC		 8414static void tg3_rx_prodring_fini(struct tg3 *tp,
8415 struct tg3_rx_prodring_set *tpr)
1da177e4 8416{
21f581a5
MC		 8417 kfree(tpr->rx_std_buffers);
8418 tpr->rx_std_buffers = NULL;
8419 kfree(tpr->rx_jmb_buffers);
8420 tpr->rx_jmb_buffers = NULL;
8421 if (tpr->rx_std) {
4bae65c8
MC		 8422 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8423 tpr->rx_std, tpr->rx_std_mapping);
21f581a5 8424 tpr->rx_std = NULL;
1da177e4 8425 }
21f581a5 8426 if (tpr->rx_jmb) {
4bae65c8
MC		 8427 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8428 tpr->rx_jmb, tpr->rx_jmb_mapping);
21f581a5 8429 tpr->rx_jmb = NULL;
1da177e4 8430 }
cf7a7298
MC		 8431}
8432
21f581a5
MC		 8433static int tg3_rx_prodring_init(struct tg3 *tp,
8434 struct tg3_rx_prodring_set *tpr)
cf7a7298 8435{
2c49a44d
MC		 8436 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8437 GFP_KERNEL);
21f581a5 8438 if (!tpr->rx_std_buffers)
cf7a7298
MC		 8439 return -ENOMEM;
8440
4bae65c8
MC		 8441 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8442 TG3_RX_STD_RING_BYTES(tp),
8443 &tpr->rx_std_mapping,
8444 GFP_KERNEL);
21f581a5 8445 if (!tpr->rx_std)
cf7a7298
MC		 8446 goto err_out;
8447
63c3a66f 8448 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8449 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
21f581a5
MC		 8450 GFP_KERNEL);
8451 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 8452 goto err_out;
8453
4bae65c8
MC		 8454 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8455 TG3_RX_JMB_RING_BYTES(tp),
8456 &tpr->rx_jmb_mapping,
8457 GFP_KERNEL);
21f581a5 8458 if (!tpr->rx_jmb)
cf7a7298
MC		 8459 goto err_out;
8460 }
8461
8462 return 0;
8463
8464err_out:
21f581a5 8465 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 8466 return -ENOMEM;
8467}
8468
8469/* Free up pending packets in all rx/tx rings.
8470 *
8471 * The chip has been shut down and the driver detached from
8472 * the networking, so no interrupts or new tx packets will
8473 * end up in the driver. tp->{tx,}lock is not held and we are not
8474 * in an interrupt context and thus may sleep.
8475 */
8476static void tg3_free_rings(struct tg3 *tp)
8477{
f77a6a8e 8478 int i, j;
cf7a7298 8479
f77a6a8e
MC		 8480 for (j = 0; j < tp->irq_cnt; j++) {
8481 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 8482
8fea32b9 8483 tg3_rx_prodring_free(tp, &tnapi->prodring);
b28f6428 8484
0c1d0e2b
MC		 8485 if (!tnapi->tx_buffers)
8486 continue;
8487
0d681b27
MC		 8488 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8489 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
cf7a7298 8490
0d681b27 8491 if (!skb)
f77a6a8e 8492 continue;
cf7a7298 8493
ba1142e4
MC		 8494 tg3_tx_skb_unmap(tnapi, i,
8495 skb_shinfo(skb)->nr_frags - 1);
f77a6a8e
MC		 8496
8497 dev_kfree_skb_any(skb);
8498 }
5cb917bc 8499 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
2b2cdb65 8500 }
cf7a7298
MC		 8501}
8502
8503/* Initialize tx/rx rings for packet processing.
8504 *
8505 * The chip has been shut down and the driver detached from
8506 * the networking, so no interrupts or new tx packets will
8507 * end up in the driver. tp->{tx,}lock are held and thus
8508 * we may not sleep.
8509 */
8510static int tg3_init_rings(struct tg3 *tp)
8511{
f77a6a8e 8512 int i;
72334482 8513
cf7a7298
MC		 8514 /* Free up all the SKBs. */
8515 tg3_free_rings(tp);
8516
f77a6a8e
MC		 8517 for (i = 0; i < tp->irq_cnt; i++) {
8518 struct tg3_napi *tnapi = &tp->napi[i];
8519
8520 tnapi->last_tag = 0;
8521 tnapi->last_irq_tag = 0;
8522 tnapi->hw_status->status = 0;
8523 tnapi->hw_status->status_tag = 0;
8524 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 8525
f77a6a8e
MC		 8526 tnapi->tx_prod = 0;
8527 tnapi->tx_cons = 0;
0c1d0e2b
MC		 8528 if (tnapi->tx_ring)
8529 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 8530
8531 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 8532 if (tnapi->rx_rcb)
8533 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 8534
8fea32b9 8535 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
e4af1af9 8536 tg3_free_rings(tp);
2b2cdb65 8537 return -ENOMEM;
e4af1af9 8538 }
f77a6a8e 8539 }
72334482 8540
2b2cdb65 8541 return 0;
cf7a7298
MC		 8542}
8543
49a359e3 8544static void tg3_mem_tx_release(struct tg3 *tp)
cf7a7298 8545{
f77a6a8e 8546 int i;
898a56f8 8547
49a359e3 8548 for (i = 0; i < tp->irq_max; i++) {
f77a6a8e
MC		 8549 struct tg3_napi *tnapi = &tp->napi[i];
8550
8551 if (tnapi->tx_ring) {
4bae65c8 8552 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
f77a6a8e
MC		 8553 tnapi->tx_ring, tnapi->tx_desc_mapping);
8554 tnapi->tx_ring = NULL;
8555 }
8556
8557 kfree(tnapi->tx_buffers);
8558 tnapi->tx_buffers = NULL;
49a359e3
MC		 8559 }
8560}
f77a6a8e 8561
49a359e3
MC		 8562static int tg3_mem_tx_acquire(struct tg3 *tp)
8563{
8564 int i;
8565 struct tg3_napi *tnapi = &tp->napi[0];
8566
8567 /* If multivector TSS is enabled, vector 0 does not handle
8568 * tx interrupts. Don't allocate any resources for it.
8569 */
8570 if (tg3_flag(tp, ENABLE_TSS))
8571 tnapi++;
8572
8573 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8574 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8575 TG3_TX_RING_SIZE, GFP_KERNEL);
8576 if (!tnapi->tx_buffers)
8577 goto err_out;
8578
8579 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8580 TG3_TX_RING_BYTES,
8581 &tnapi->tx_desc_mapping,
8582 GFP_KERNEL);
8583 if (!tnapi->tx_ring)
8584 goto err_out;
8585 }
8586
8587 return 0;
8588
8589err_out:
8590 tg3_mem_tx_release(tp);
8591 return -ENOMEM;
8592}
8593
8594static void tg3_mem_rx_release(struct tg3 *tp)
8595{
8596 int i;
8597
8598 for (i = 0; i < tp->irq_max; i++) {
8599 struct tg3_napi *tnapi = &tp->napi[i];
f77a6a8e 8600
8fea32b9
MC		 8601 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8602
49a359e3
MC		 8603 if (!tnapi->rx_rcb)
8604 continue;
8605
8606 dma_free_coherent(&tp->pdev->dev,
8607 TG3_RX_RCB_RING_BYTES(tp),
8608 tnapi->rx_rcb,
8609 tnapi->rx_rcb_mapping);
8610 tnapi->rx_rcb = NULL;
8611 }
8612}
8613
8614static int tg3_mem_rx_acquire(struct tg3 *tp)
8615{
8616 unsigned int i, limit;
8617
8618 limit = tp->rxq_cnt;
8619
8620 /* If RSS is enabled, we need a (dummy) producer ring
8621 * set on vector zero. This is the true hw prodring.
8622 */
8623 if (tg3_flag(tp, ENABLE_RSS))
8624 limit++;
8625
8626 for (i = 0; i < limit; i++) {
8627 struct tg3_napi *tnapi = &tp->napi[i];
8628
8629 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8630 goto err_out;
8631
8632 /* If multivector RSS is enabled, vector 0
8633 * does not handle rx or tx interrupts.
8634 * Don't allocate any resources for it.
8635 */
8636 if (!i && tg3_flag(tp, ENABLE_RSS))
8637 continue;
8638
ede23fa8
JP		 8639 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8640 TG3_RX_RCB_RING_BYTES(tp),
8641 &tnapi->rx_rcb_mapping,
8642 GFP_KERNEL);
49a359e3
MC		 8643 if (!tnapi->rx_rcb)
8644 goto err_out;
49a359e3
MC		 8645 }
8646
8647 return 0;
8648
8649err_out:
8650 tg3_mem_rx_release(tp);
8651 return -ENOMEM;
8652}
8653
8654/*
8655 * Must not be invoked with interrupt sources disabled and
8656 * the hardware shutdown down.
8657 */
8658static void tg3_free_consistent(struct tg3 *tp)
8659{
8660 int i;
8661
8662 for (i = 0; i < tp->irq_cnt; i++) {
8663 struct tg3_napi *tnapi = &tp->napi[i];
8664
f77a6a8e 8665 if (tnapi->hw_status) {
4bae65c8
MC		 8666 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8667 tnapi->hw_status,
8668 tnapi->status_mapping);
f77a6a8e
MC		 8669 tnapi->hw_status = NULL;
8670 }
1da177e4 8671 }
f77a6a8e 8672
49a359e3
MC		 8673 tg3_mem_rx_release(tp);
8674 tg3_mem_tx_release(tp);
8675
1da177e4 8676 if (tp->hw_stats) {
4bae65c8
MC		 8677 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8678 tp->hw_stats, tp->stats_mapping);
1da177e4
LT		 8679 tp->hw_stats = NULL;
8680 }
8681}
8682
8683/*
8684 * Must not be invoked with interrupt sources disabled and
8685 * the hardware shutdown down. Can sleep.
8686 */
8687static int tg3_alloc_consistent(struct tg3 *tp)
8688{
f77a6a8e 8689 int i;
898a56f8 8690
ede23fa8
JP		 8691 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8692 sizeof(struct tg3_hw_stats),
8693 &tp->stats_mapping, GFP_KERNEL);
f77a6a8e 8694 if (!tp->hw_stats)
1da177e4
LT		 8695 goto err_out;
8696
f77a6a8e
MC		 8697 for (i = 0; i < tp->irq_cnt; i++) {
8698 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 8699 struct tg3_hw_status *sblk;
1da177e4 8700
ede23fa8
JP		 8701 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8702 TG3_HW_STATUS_SIZE,
8703 &tnapi->status_mapping,
8704 GFP_KERNEL);
f77a6a8e
MC		 8705 if (!tnapi->hw_status)
8706 goto err_out;
898a56f8 8707
8d9d7cfc
MC		 8708 sblk = tnapi->hw_status;
8709
49a359e3 8710 if (tg3_flag(tp, ENABLE_RSS)) {
86449944 8711 u16 *prodptr = NULL;
8fea32b9 8712
49a359e3
MC		 8713 /*
8714 * When RSS is enabled, the status block format changes
8715 * slightly. The "rx_jumbo_consumer", "reserved",
8716 * and "rx_mini_consumer" members get mapped to the
8717 * other three rx return ring producer indexes.
8718 */
8719 switch (i) {
8720 case 1:
8721 prodptr = &sblk->idx[0].rx_producer;
8722 break;
8723 case 2:
8724 prodptr = &sblk->rx_jumbo_consumer;
8725 break;
8726 case 3:
8727 prodptr = &sblk->reserved;
8728 break;
8729 case 4:
8730 prodptr = &sblk->rx_mini_consumer;
f891ea16
MC		 8731 break;
8732 }
49a359e3
MC		 8733 tnapi->rx_rcb_prod_idx = prodptr;
8734 } else {
8d9d7cfc 8735 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8d9d7cfc 8736 }
f77a6a8e 8737 }
1da177e4 8738
49a359e3
MC		 8739 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8740 goto err_out;
8741
1da177e4
LT		 8742 return 0;
8743
8744err_out:
8745 tg3_free_consistent(tp);
8746 return -ENOMEM;
8747}
8748
8749#define MAX_WAIT_CNT 1000
8750
8751/* To stop a block, clear the enable bit and poll till it
8752 * clears. tp->lock is held.
8753 */
953c96e0 8754static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
1da177e4
LT		 8755{
8756 unsigned int i;
8757 u32 val;
8758
63c3a66f 8759 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 8760 switch (ofs) {
8761 case RCVLSC_MODE:
8762 case DMAC_MODE:
8763 case MBFREE_MODE:
8764 case BUFMGR_MODE:
8765 case MEMARB_MODE:
8766 /* We can't enable/disable these bits of the
8767 * 5705/5750, just say success.
8768 */
8769 return 0;
8770
8771 default:
8772 break;
855e1111 8773 }
1da177e4
LT		 8774 }
8775
8776 val = tr32(ofs);
8777 val &= ~enable_bit;
8778 tw32_f(ofs, val);
8779
8780 for (i = 0; i < MAX_WAIT_CNT; i++) {
6d446ec3
GS		 8781 if (pci_channel_offline(tp->pdev)) {
8782 dev_err(&tp->pdev->dev,
8783 "tg3_stop_block device offline, "
8784 "ofs=%lx enable_bit=%x\n",
8785 ofs, enable_bit);
8786 return -ENODEV;
8787 }
8788
1da177e4
LT		 8789 udelay(100);
8790 val = tr32(ofs);
8791 if ((val & enable_bit) == 0)
8792 break;
8793 }
8794
b3b7d6be 8795 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 8796 dev_err(&tp->pdev->dev,
8797 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8798 ofs, enable_bit);
1da177e4
LT		 8799 return -ENODEV;
8800 }
8801
8802 return 0;
8803}
8804
8805/* tp->lock is held. */
953c96e0 8806static int tg3_abort_hw(struct tg3 *tp, bool silent)
1da177e4
LT		 8807{
8808 int i, err;
8809
8810 tg3_disable_ints(tp);
8811
6d446ec3
GS		 8812 if (pci_channel_offline(tp->pdev)) {
8813 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8814 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8815 err = -ENODEV;
8816 goto err_no_dev;
8817 }
8818
1da177e4
LT		 8819 tp->rx_mode &= ~RX_MODE_ENABLE;
8820 tw32_f(MAC_RX_MODE, tp->rx_mode);
8821 udelay(10);
8822
b3b7d6be
DM		 8823 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8824 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8825 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8826 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8827 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8828 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8829
8830 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8831 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8832 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8833 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8834 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8835 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8836 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 8837
8838 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8839 tw32_f(MAC_MODE, tp->mac_mode);
8840 udelay(40);
8841
8842 tp->tx_mode &= ~TX_MODE_ENABLE;
8843 tw32_f(MAC_TX_MODE, tp->tx_mode);
8844
8845 for (i = 0; i < MAX_WAIT_CNT; i++) {
8846 udelay(100);
8847 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8848 break;
8849 }
8850 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 8851 dev_err(&tp->pdev->dev,
8852 "%s timed out, TX_MODE_ENABLE will not clear "
8853 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 8854 err |= -ENODEV;
1da177e4
LT		 8855 }
8856
e6de8ad1 8857 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 8858 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8859 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 8860
8861 tw32(FTQ_RESET, 0xffffffff);
8862 tw32(FTQ_RESET, 0x00000000);
8863
b3b7d6be
DM		 8864 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8865 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 8866
6d446ec3 8867err_no_dev:
f77a6a8e
MC		 8868 for (i = 0; i < tp->irq_cnt; i++) {
8869 struct tg3_napi *tnapi = &tp->napi[i];
8870 if (tnapi->hw_status)
8871 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8872 }
1da177e4 8873
1da177e4
LT		 8874 return err;
8875}
8876
ee6a99b5
MC		 8877/* Save PCI command register before chip reset */
8878static void tg3_save_pci_state(struct tg3 *tp)
8879{
8a6eac90 8880 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 8881}
8882
8883/* Restore PCI state after chip reset */
8884static void tg3_restore_pci_state(struct tg3 *tp)
8885{
8886 u32 val;
8887
8888 /* Re-enable indirect register accesses. */
8889 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8890 tp->misc_host_ctrl);
8891
8892 /* Set MAX PCI retry to zero. */
8893 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4153577a 8894 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 8895 tg3_flag(tp, PCIX_MODE))
ee6a99b5 8896 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9 8897 /* Allow reads and writes to the APE register and memory space. */
63c3a66f 8898 if (tg3_flag(tp, ENABLE_APE))
0d3031d9 8899 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 8900 PCISTATE_ALLOW_APE_SHMEM_WR |
8901 PCISTATE_ALLOW_APE_PSPACE_WR;
ee6a99b5
MC		 8902 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8903
8a6eac90 8904 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 8905
2c55a3d0
MC		 8906 if (!tg3_flag(tp, PCI_EXPRESS)) {
8907 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8908 tp->pci_cacheline_sz);
8909 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8910 tp->pci_lat_timer);
114342f2 8911 }
5f5c51e3 8912
ee6a99b5 8913 /* Make sure PCI-X relaxed ordering bit is clear. */
63c3a66f 8914 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 8915 u16 pcix_cmd;
8916
8917 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8918 &pcix_cmd);
8919 pcix_cmd &= ~PCI_X_CMD_ERO;
8920 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8921 pcix_cmd);
8922 }
ee6a99b5 8923
63c3a66f 8924 if (tg3_flag(tp, 5780_CLASS)) {
ee6a99b5
MC		 8925
8926 /* Chip reset on 5780 will reset MSI enable bit,
8927 * so need to restore it.
8928 */
63c3a66f 8929 if (tg3_flag(tp, USING_MSI)) {
ee6a99b5
MC		 8930 u16 ctrl;
8931
8932 pci_read_config_word(tp->pdev,
8933 tp->msi_cap + PCI_MSI_FLAGS,
8934 &ctrl);
8935 pci_write_config_word(tp->pdev,
8936 tp->msi_cap + PCI_MSI_FLAGS,
8937 ctrl | PCI_MSI_FLAGS_ENABLE);
8938 val = tr32(MSGINT_MODE);
8939 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8940 }
8941 }
8942}
8943
1da177e4
LT		 8944/* tp->lock is held. */
8945static int tg3_chip_reset(struct tg3 *tp)
8946{
8947 u32 val;
1ee582d8 8948 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 8949 int i, err;
1da177e4 8950
8496e85c
RW		 8951 if (!pci_device_is_present(tp->pdev))
8952 return -ENODEV;
8953
f49639e6
DM		 8954 tg3_nvram_lock(tp);
8955
77b483f1
MC		 8956 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
8957
f49639e6
DM		 8958 /* No matching tg3_nvram_unlock() after this because
8959 * chip reset below will undo the nvram lock.
8960 */
8961 tp->nvram_lock_cnt = 0;
1da177e4 8962
ee6a99b5
MC		 8963 /* GRC_MISC_CFG core clock reset will clear the memory
8964 * enable bit in PCI register 4 and the MSI enable bit
8965 * on some chips, so we save relevant registers here.
8966 */
8967 tg3_save_pci_state(tp);
8968
4153577a 8969 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
63c3a66f 8970 tg3_flag(tp, 5755_PLUS))
d9ab5ad1
MC		 8971 tw32(GRC_FASTBOOT_PC, 0);
8972
1da177e4
LT		 8973 /*
8974 * We must avoid the readl() that normally takes place.
8975 * It locks machines, causes machine checks, and other
8976 * fun things. So, temporarily disable the 5701
8977 * hardware workaround, while we do the reset.
8978 */
1ee582d8
MC		 8979 write_op = tp->write32;
8980 if (write_op == tg3_write_flush_reg32)
8981 tp->write32 = tg3_write32;
1da177e4 8982
d18edcb2
MC		 8983 /* Prevent the irq handler from reading or writing PCI registers
8984 * during chip reset when the memory enable bit in the PCI command
8985 * register may be cleared. The chip does not generate interrupt
8986 * at this time, but the irq handler may still be called due to irq
8987 * sharing or irqpoll.
8988 */
63c3a66f 8989 tg3_flag_set(tp, CHIP_RESETTING);
f77a6a8e
MC		 8990 for (i = 0; i < tp->irq_cnt; i++) {
8991 struct tg3_napi *tnapi = &tp->napi[i];
8992 if (tnapi->hw_status) {
8993 tnapi->hw_status->status = 0;
8994 tnapi->hw_status->status_tag = 0;
8995 }
8996 tnapi->last_tag = 0;
8997 tnapi->last_irq_tag = 0;
b8fa2f3a 8998 }
d18edcb2 8999 smp_mb();
4f125f42
MC		 9000
9001 for (i = 0; i < tp->irq_cnt; i++)
9002 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 9003
4153577a 9004 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
255ca311
MC		 9005 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9006 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9007 }
9008
1da177e4
LT		 9009 /* do the reset */
9010 val = GRC_MISC_CFG_CORECLK_RESET;
9011
63c3a66f 9012 if (tg3_flag(tp, PCI_EXPRESS)) {
88075d91 9013 /* Force PCIe 1.0a mode */
4153577a 9014 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9015 !tg3_flag(tp, 57765_PLUS) &&
88075d91
MC		 9016 tr32(TG3_PCIE_PHY_TSTCTL) ==
9017 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9018 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9019
4153577a 9020 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
1da177e4
LT		 9021 tw32(GRC_MISC_CFG, (1 << 29));
9022 val |= (1 << 29);
9023 }
9024 }
9025
4153577a 9026 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 9027 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9028 tw32(GRC_VCPU_EXT_CTRL,
9029 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9030 }
9031
f37500d3 9032 /* Manage gphy power for all CPMU absent PCIe devices. */
63c3a66f 9033 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
1da177e4 9034 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
f37500d3 9035
1da177e4
LT		 9036 tw32(GRC_MISC_CFG, val);
9037
1ee582d8
MC		 9038 /* restore 5701 hardware bug workaround write method */
9039 tp->write32 = write_op;
1da177e4
LT		 9040
9041 /* Unfortunately, we have to delay before the PCI read back.
9042 * Some 575X chips even will not respond to a PCI cfg access
9043 * when the reset command is given to the chip.
9044 *
9045 * How do these hardware designers expect things to work
9046 * properly if the PCI write is posted for a long period
9047 * of time? It is always necessary to have some method by
9048 * which a register read back can occur to push the write
9049 * out which does the reset.
9050 *
9051 * For most tg3 variants the trick below was working.
9052 * Ho hum...
9053 */
9054 udelay(120);
9055
9056 /* Flush PCI posted writes. The normal MMIO registers
9057 * are inaccessible at this time so this is the only
9058 * way to make this reliably (actually, this is no longer
9059 * the case, see above). I tried to use indirect
9060 * register read/write but this upset some 5701 variants.
9061 */
9062 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9063
9064 udelay(120);
9065
0f49bfbd 9066 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
e7126997
MC		 9067 u16 val16;
9068
4153577a 9069 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
86449944 9070 int j;
1da177e4
LT		 9071 u32 cfg_val;
9072
9073 /* Wait for link training to complete. */
86449944 9074 for (j = 0; j < 5000; j++)
1da177e4
LT		 9075 udelay(100);
9076
9077 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9078 pci_write_config_dword(tp->pdev, 0xc4,
9079 cfg_val | (1 << 15));
9080 }
5e7dfd0f 9081
e7126997 9082 /* Clear the "no snoop" and "relaxed ordering" bits. */
0f49bfbd 9083 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
e7126997
MC		 9084 /*
9085 * Older PCIe devices only support the 128 byte
9086 * MPS setting. Enforce the restriction.
5e7dfd0f 9087 */
63c3a66f 9088 if (!tg3_flag(tp, CPMU_PRESENT))
0f49bfbd
JL		 9089 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9090 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
5e7dfd0f 9091
5e7dfd0f 9092 /* Clear error status */
0f49bfbd 9093 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
5e7dfd0f
MC		 9094 PCI_EXP_DEVSTA_CED |
9095 PCI_EXP_DEVSTA_NFED |
9096 PCI_EXP_DEVSTA_FED |
9097 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 9098 }
9099
ee6a99b5 9100 tg3_restore_pci_state(tp);
1da177e4 9101
63c3a66f
JP		 9102 tg3_flag_clear(tp, CHIP_RESETTING);
9103 tg3_flag_clear(tp, ERROR_PROCESSED);
d18edcb2 9104
ee6a99b5 9105 val = 0;
63c3a66f 9106 if (tg3_flag(tp, 5780_CLASS))
4cf78e4f 9107 val = tr32(MEMARB_MODE);
ee6a99b5 9108 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4 9109
4153577a 9110 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
1da177e4
LT		 9111 tg3_stop_fw(tp);
9112 tw32(0x5000, 0x400);
9113 }
9114
7e6c63f0
HM		 9115 if (tg3_flag(tp, IS_SSB_CORE)) {
9116 /*
9117 * BCM4785: In order to avoid repercussions from using
9118 * potentially defective internal ROM, stop the Rx RISC CPU,
9119 * which is not required.
9120 */
9121 tg3_stop_fw(tp);
9122 tg3_halt_cpu(tp, RX_CPU_BASE);
9123 }
9124
fb03a43f
NS		 9125 err = tg3_poll_fw(tp);
9126 if (err)
9127 return err;
9128
1da177e4
LT		 9129 tw32(GRC_MODE, tp->grc_mode);
9130
4153577a 9131 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
ab0049b4 9132 val = tr32(0xc4);
1da177e4
LT		 9133
9134 tw32(0xc4, val | (1 << 15));
9135 }
9136
9137 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4153577a 9138 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4 9139 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4153577a 9140 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
1da177e4
LT		 9141 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9142 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9143 }
9144
f07e9af3 9145 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9e975cc2 9146 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
d2394e6b 9147 val = tp->mac_mode;
f07e9af3 9148 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9e975cc2 9149 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
d2394e6b 9150 val = tp->mac_mode;
1da177e4 9151 } else
d2394e6b
MC		 9152 val = 0;
9153
9154 tw32_f(MAC_MODE, val);
1da177e4
LT		 9155 udelay(40);
9156
77b483f1
MC		 9157 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9158
0a9140cf
MC		 9159 tg3_mdio_start(tp);
9160
63c3a66f 9161 if (tg3_flag(tp, PCI_EXPRESS) &&
4153577a
JP		 9162 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9163 tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9164 !tg3_flag(tp, 57765_PLUS)) {
ab0049b4 9165 val = tr32(0x7c00);
1da177e4
LT		 9166
9167 tw32(0x7c00, val | (1 << 25));
9168 }
9169
4153577a 9170 if (tg3_asic_rev(tp) == ASIC_REV_5720) {
d78b59f5
MC		 9171 val = tr32(TG3_CPMU_CLCK_ORIDE);
9172 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9173 }
9174
1da177e4 9175 /* Reprobe ASF enable state. */
63c3a66f 9176 tg3_flag_clear(tp, ENABLE_ASF);
942d1af0
NS		 9177 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9178 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9179
63c3a66f 9180 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
1da177e4
LT		 9181 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9182 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9183 u32 nic_cfg;
9184
9185 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9186 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f 9187 tg3_flag_set(tp, ENABLE_ASF);
4ba526ce 9188 tp->last_event_jiffies = jiffies;
63c3a66f
JP		 9189 if (tg3_flag(tp, 5750_PLUS))
9190 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
942d1af0
NS		 9191
9192 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9193 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9194 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9195 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9196 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
1da177e4
LT		 9197 }
9198 }
9199
9200 return 0;
9201}
9202
65ec698d
MC		 9203static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9204static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
e565eec3 9205static void __tg3_set_rx_mode(struct net_device *);
92feeabf 9206
1da177e4 9207/* tp->lock is held. */
953c96e0 9208static int tg3_halt(struct tg3 *tp, int kind, bool silent)
1da177e4
LT		 9209{
9210 int err;
9211
9212 tg3_stop_fw(tp);
9213
944d980e 9214 tg3_write_sig_pre_reset(tp, kind);
1da177e4 9215
b3b7d6be 9216 tg3_abort_hw(tp, silent);
1da177e4
LT		 9217 err = tg3_chip_reset(tp);
9218
953c96e0 9219 __tg3_set_mac_addr(tp, false);
daba2a63 9220
944d980e
MC		 9221 tg3_write_sig_legacy(tp, kind);
9222 tg3_write_sig_post_reset(tp, kind);
1da177e4 9223
92feeabf
MC		 9224 if (tp->hw_stats) {
9225 /* Save the stats across chip resets... */
b4017c53 9226 tg3_get_nstats(tp, &tp->net_stats_prev);
92feeabf
MC		 9227 tg3_get_estats(tp, &tp->estats_prev);
9228
9229 /* And make sure the next sample is new data */
9230 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9231 }
9232
4bc814ab 9233 return err;
1da177e4
LT		 9234}
9235
1da177e4
LT		 9236static int tg3_set_mac_addr(struct net_device *dev, void *p)
9237{
9238 struct tg3 *tp = netdev_priv(dev);
9239 struct sockaddr *addr = p;
953c96e0
JP		 9240 int err = 0;
9241 bool skip_mac_1 = false;
1da177e4 9242
f9804ddb 9243 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 9244 return -EADDRNOTAVAIL;
f9804ddb 9245
1da177e4
LT		 9246 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9247
e75f7c90
MC		 9248 if (!netif_running(dev))
9249 return 0;
9250
63c3a66f 9251 if (tg3_flag(tp, ENABLE_ASF)) {
986e0aeb 9252 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 9253
986e0aeb
MC		 9254 addr0_high = tr32(MAC_ADDR_0_HIGH);
9255 addr0_low = tr32(MAC_ADDR_0_LOW);
9256 addr1_high = tr32(MAC_ADDR_1_HIGH);
9257 addr1_low = tr32(MAC_ADDR_1_LOW);
9258
9259 /* Skip MAC addr 1 if ASF is using it. */
9260 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9261 !(addr1_high == 0 && addr1_low == 0))
953c96e0 9262 skip_mac_1 = true;
58712ef9 9263 }
986e0aeb
MC		 9264 spin_lock_bh(&tp->lock);
9265 __tg3_set_mac_addr(tp, skip_mac_1);
e565eec3 9266 __tg3_set_rx_mode(dev);
986e0aeb 9267 spin_unlock_bh(&tp->lock);
1da177e4 9268
b9ec6c1b 9269 return err;
1da177e4
LT		 9270}
9271
9272/* tp->lock is held. */
9273static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9274 dma_addr_t mapping, u32 maxlen_flags,
9275 u32 nic_addr)
9276{
9277 tg3_write_mem(tp,
9278 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9279 ((u64) mapping >> 32));
9280 tg3_write_mem(tp,
9281 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9282 ((u64) mapping & 0xffffffff));
9283 tg3_write_mem(tp,
9284 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9285 maxlen_flags);
9286
63c3a66f 9287 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 9288 tg3_write_mem(tp,
9289 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9290 nic_addr);
9291}
9292
a489b6d9
MC		 9293
9294static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 9295{
a489b6d9 9296 int i = 0;
b6080e12 9297
63c3a66f 9298 if (!tg3_flag(tp, ENABLE_TSS)) {
b6080e12
MC		 9299 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9300 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9301 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 9302 } else {
9303 tw32(HOSTCC_TXCOL_TICKS, 0);
9304 tw32(HOSTCC_TXMAX_FRAMES, 0);
9305 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
a489b6d9
MC		 9306
9307 for (; i < tp->txq_cnt; i++) {
9308 u32 reg;
9309
9310 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9311 tw32(reg, ec->tx_coalesce_usecs);
9312 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9313 tw32(reg, ec->tx_max_coalesced_frames);
9314 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9315 tw32(reg, ec->tx_max_coalesced_frames_irq);
9316 }
19cfaecc 9317 }
b6080e12 9318
a489b6d9
MC		 9319 for (; i < tp->irq_max - 1; i++) {
9320 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9321 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9322 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9323 }
9324}
9325
9326static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9327{
9328 int i = 0;
9329 u32 limit = tp->rxq_cnt;
9330
63c3a66f 9331 if (!tg3_flag(tp, ENABLE_RSS)) {
19cfaecc
MC		 9332 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9333 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9334 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
a489b6d9 9335 limit--;
19cfaecc 9336 } else {
b6080e12
MC		 9337 tw32(HOSTCC_RXCOL_TICKS, 0);
9338 tw32(HOSTCC_RXMAX_FRAMES, 0);
9339 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 9340 }
b6080e12 9341
a489b6d9 9342 for (; i < limit; i++) {
b6080e12
MC		 9343 u32 reg;
9344
9345 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9346 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 9347 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9348 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 9349 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9350 tw32(reg, ec->rx_max_coalesced_frames_irq);
b6080e12
MC		 9351 }
9352
9353 for (; i < tp->irq_max - 1; i++) {
9354 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 9355 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 9356 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
a489b6d9
MC		 9357 }
9358}
19cfaecc 9359
a489b6d9
MC		 9360static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9361{
9362 tg3_coal_tx_init(tp, ec);
9363 tg3_coal_rx_init(tp, ec);
9364
9365 if (!tg3_flag(tp, 5705_PLUS)) {
9366 u32 val = ec->stats_block_coalesce_usecs;
9367
9368 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9369 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9370
f4a46d1f 9371 if (!tp->link_up)
a489b6d9
MC		 9372 val = 0;
9373
9374 tw32(HOSTCC_STAT_COAL_TICKS, val);
b6080e12 9375 }
15f9850d 9376}
1da177e4 9377
328947ff
NS		 9378/* tp->lock is held. */
9379static void tg3_tx_rcbs_disable(struct tg3 *tp)
9380{
9381 u32 txrcb, limit;
9382
9383 /* Disable all transmit rings but the first. */
9384 if (!tg3_flag(tp, 5705_PLUS))
9385 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9386 else if (tg3_flag(tp, 5717_PLUS))
9387 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9388 else if (tg3_flag(tp, 57765_CLASS) ||
9389 tg3_asic_rev(tp) == ASIC_REV_5762)
9390 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9391 else
9392 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9393
9394 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9395 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9396 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9397 BDINFO_FLAGS_DISABLED);
9398}
9399
32ba19ef
NS		 9400/* tp->lock is held. */
9401static void tg3_tx_rcbs_init(struct tg3 *tp)
9402{
9403 int i = 0;
9404 u32 txrcb = NIC_SRAM_SEND_RCB;
9405
9406 if (tg3_flag(tp, ENABLE_TSS))
9407 i++;
9408
9409 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9410 struct tg3_napi *tnapi = &tp->napi[i];
9411
9412 if (!tnapi->tx_ring)
9413 continue;
9414
9415 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9416 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9417 NIC_SRAM_TX_BUFFER_DESC);
9418 }
9419}
9420
328947ff
NS		 9421/* tp->lock is held. */
9422static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9423{
9424 u32 rxrcb, limit;
9425
9426 /* Disable all receive return rings but the first. */
9427 if (tg3_flag(tp, 5717_PLUS))
9428 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9429 else if (!tg3_flag(tp, 5705_PLUS))
9430 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9431 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9432 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9433 tg3_flag(tp, 57765_CLASS))
9434 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9435 else
9436 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9437
9438 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9439 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9440 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9441 BDINFO_FLAGS_DISABLED);
9442}
9443
32ba19ef
NS		 9444/* tp->lock is held. */
9445static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9446{
9447 int i = 0;
9448 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9449
9450 if (tg3_flag(tp, ENABLE_RSS))
9451 i++;
9452
9453 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9454 struct tg3_napi *tnapi = &tp->napi[i];
9455
9456 if (!tnapi->rx_rcb)
9457 continue;
9458
9459 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9460 (tp->rx_ret_ring_mask + 1) <<
9461 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9462 }
9463}
9464
2d31ecaf
MC		 9465/* tp->lock is held. */
9466static void tg3_rings_reset(struct tg3 *tp)
9467{
9468 int i;
328947ff 9469 u32 stblk;
2d31ecaf
MC		 9470 struct tg3_napi *tnapi = &tp->napi[0];
9471
328947ff 9472 tg3_tx_rcbs_disable(tp);
2d31ecaf 9473
328947ff 9474 tg3_rx_ret_rcbs_disable(tp);
2d31ecaf
MC		 9475
9476 /* Disable interrupts */
9477 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
0e6cf6a9
MC		 9478 tp->napi[0].chk_msi_cnt = 0;
9479 tp->napi[0].last_rx_cons = 0;
9480 tp->napi[0].last_tx_cons = 0;
2d31ecaf
MC		 9481
9482 /* Zero mailbox registers. */
63c3a66f 9483 if (tg3_flag(tp, SUPPORT_MSIX)) {
6fd45cb8 9484 for (i = 1; i < tp->irq_max; i++) {
f77a6a8e
MC		 9485 tp->napi[i].tx_prod = 0;
9486 tp->napi[i].tx_cons = 0;
63c3a66f 9487 if (tg3_flag(tp, ENABLE_TSS))
c2353a32 9488 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 9489 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9490 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7f230735 9491 tp->napi[i].chk_msi_cnt = 0;
0e6cf6a9
MC		 9492 tp->napi[i].last_rx_cons = 0;
9493 tp->napi[i].last_tx_cons = 0;
f77a6a8e 9494 }
63c3a66f 9495 if (!tg3_flag(tp, ENABLE_TSS))
c2353a32 9496 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 9497 } else {
9498 tp->napi[0].tx_prod = 0;
9499 tp->napi[0].tx_cons = 0;
9500 tw32_mailbox(tp->napi[0].prodmbox, 0);
9501 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9502 }
2d31ecaf
MC		 9503
9504 /* Make sure the NIC-based send BD rings are disabled. */
63c3a66f 9505 if (!tg3_flag(tp, 5705_PLUS)) {
2d31ecaf
MC		 9506 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9507 for (i = 0; i < 16; i++)
9508 tw32_tx_mbox(mbox + i * 8, 0);
9509 }
9510
2d31ecaf
MC		 9511 /* Clear status block in ram. */
9512 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9513
9514 /* Set status block DMA address */
9515 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9516 ((u64) tnapi->status_mapping >> 32));
9517 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9518 ((u64) tnapi->status_mapping & 0xffffffff));
9519
f77a6a8e 9520 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 9521
f77a6a8e
MC		 9522 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9523 u64 mapping = (u64)tnapi->status_mapping;
9524 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9525 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
32ba19ef 9526 stblk += 8;
f77a6a8e
MC		 9527
9528 /* Clear status block in ram. */
9529 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
f77a6a8e 9530 }
32ba19ef
NS		 9531
9532 tg3_tx_rcbs_init(tp);
9533 tg3_rx_ret_rcbs_init(tp);
2d31ecaf
MC		 9534}
9535
eb07a940
MC		 9536static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9537{
9538 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9539
63c3a66f
JP		 9540 if (!tg3_flag(tp, 5750_PLUS) ||
9541 tg3_flag(tp, 5780_CLASS) ||
4153577a
JP		 9542 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9543 tg3_asic_rev(tp) == ASIC_REV_5752 ||
513aa6ea 9544 tg3_flag(tp, 57765_PLUS))
eb07a940 9545 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
4153577a
JP		 9546 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9547 tg3_asic_rev(tp) == ASIC_REV_5787)
eb07a940
MC		 9548 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9549 else
9550 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9551
9552 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9553 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9554
9555 val = min(nic_rep_thresh, host_rep_thresh);
9556 tw32(RCVBDI_STD_THRESH, val);
9557
63c3a66f 9558 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9559 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9560
63c3a66f 9561 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
eb07a940
MC		 9562 return;
9563
513aa6ea 9564 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
eb07a940
MC		 9565
9566 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9567
9568 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9569 tw32(RCVBDI_JUMBO_THRESH, val);
9570
63c3a66f 9571 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9572 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9573}
9574
ccd5ba9d
MC		 9575static inline u32 calc_crc(unsigned char *buf, int len)
9576{
9577 u32 reg;
9578 u32 tmp;
9579 int j, k;
9580
9581 reg = 0xffffffff;
9582
9583 for (j = 0; j < len; j++) {
9584 reg ^= buf[j];
9585
9586 for (k = 0; k < 8; k++) {
9587 tmp = reg & 0x01;
9588
9589 reg >>= 1;
9590
9591 if (tmp)
9592 reg ^= 0xedb88320;
9593 }
9594 }
9595
9596 return ~reg;
9597}
9598
9599static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9600{
9601 /* accept or reject all multicast frames */
9602 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9603 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9604 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9605 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9606}
9607
9608static void __tg3_set_rx_mode(struct net_device *dev)
9609{
9610 struct tg3 *tp = netdev_priv(dev);
9611 u32 rx_mode;
9612
9613 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9614 RX_MODE_KEEP_VLAN_TAG);
9615
9616#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9617 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9618 * flag clear.
9619 */
9620 if (!tg3_flag(tp, ENABLE_ASF))
9621 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9622#endif
9623
9624 if (dev->flags & IFF_PROMISC) {
9625 /* Promiscuous mode. */
9626 rx_mode |= RX_MODE_PROMISC;
9627 } else if (dev->flags & IFF_ALLMULTI) {
9628 /* Accept all multicast. */
9629 tg3_set_multi(tp, 1);
9630 } else if (netdev_mc_empty(dev)) {
9631 /* Reject all multicast. */
9632 tg3_set_multi(tp, 0);
9633 } else {
9634 /* Accept one or more multicast(s). */
9635 struct netdev_hw_addr *ha;
9636 u32 mc_filter[4] = { 0, };
9637 u32 regidx;
9638 u32 bit;
9639 u32 crc;
9640
9641 netdev_for_each_mc_addr(ha, dev) {
9642 crc = calc_crc(ha->addr, ETH_ALEN);
9643 bit = ~crc & 0x7f;
9644 regidx = (bit & 0x60) >> 5;
9645 bit &= 0x1f;
9646 mc_filter[regidx] |= (1 << bit);
9647 }
9648
9649 tw32(MAC_HASH_REG_0, mc_filter[0]);
9650 tw32(MAC_HASH_REG_1, mc_filter[1]);
9651 tw32(MAC_HASH_REG_2, mc_filter[2]);
9652 tw32(MAC_HASH_REG_3, mc_filter[3]);
9653 }
9654
e565eec3
MC		 9655 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9656 rx_mode |= RX_MODE_PROMISC;
9657 } else if (!(dev->flags & IFF_PROMISC)) {
9658 /* Add all entries into to the mac addr filter list */
9659 int i = 0;
9660 struct netdev_hw_addr *ha;
9661
9662 netdev_for_each_uc_addr(ha, dev) {
9663 __tg3_set_one_mac_addr(tp, ha->addr,
9664 i + TG3_UCAST_ADDR_IDX(tp));
9665 i++;
9666 }
9667 }
9668
ccd5ba9d
MC		 9669 if (rx_mode != tp->rx_mode) {
9670 tp->rx_mode = rx_mode;
9671 tw32_f(MAC_RX_MODE, rx_mode);
9672 udelay(10);
9673 }
9674}
9675
9102426a 9676static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
90415477
MC		 9677{
9678 int i;
9679
9680 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9102426a 9681 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
90415477
MC		 9682}
9683
9684static void tg3_rss_check_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9685{
9686 int i;
9687
9688 if (!tg3_flag(tp, SUPPORT_MSIX))
9689 return;
9690
0b3ba055 9691 if (tp->rxq_cnt == 1) {
bcebcc46 9692 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
90415477
MC		 9693 return;
9694 }
9695
9696 /* Validate table against current IRQ count */
9697 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
0b3ba055 9698 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
90415477
MC		 9699 break;
9700 }
9701
9702 if (i != TG3_RSS_INDIR_TBL_SIZE)
9102426a 9703 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
bcebcc46
MC		 9704}
9705
90415477 9706static void tg3_rss_write_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9707{
9708 int i = 0;
9709 u32 reg = MAC_RSS_INDIR_TBL_0;
9710
9711 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9712 u32 val = tp->rss_ind_tbl[i];
9713 i++;
9714 for (; i % 8; i++) {
9715 val <<= 4;
9716 val |= tp->rss_ind_tbl[i];
9717 }
9718 tw32(reg, val);
9719 reg += 4;
9720 }
9721}
9722
9bc297ea
NS		 9723static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9724{
9725 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9726 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9727 else
9728 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9729}
9730
1da177e4 9731/* tp->lock is held. */
953c96e0 9732static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
1da177e4
LT		 9733{
9734 u32 val, rdmac_mode;
9735 int i, err, limit;
8fea32b9 9736 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
1da177e4
LT		 9737
9738 tg3_disable_ints(tp);
9739
9740 tg3_stop_fw(tp);
9741
9742 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9743
63c3a66f 9744 if (tg3_flag(tp, INIT_COMPLETE))
e6de8ad1 9745 tg3_abort_hw(tp, 1);
1da177e4 9746
fdad8de4
NS		 9747 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9748 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9749 tg3_phy_pull_config(tp);
400dfbaa 9750 tg3_eee_pull_config(tp, NULL);
fdad8de4
NS		 9751 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9752 }
9753
400dfbaa
NS		 9754 /* Enable MAC control of LPI */
9755 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9756 tg3_setup_eee(tp);
9757
603f1173 9758 if (reset_phy)
d4d2c558
MC		 9759 tg3_phy_reset(tp);
9760
1da177e4
LT		 9761 err = tg3_chip_reset(tp);
9762 if (err)
9763 return err;
9764
9765 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9766
4153577a 9767 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
d30cdd28
MC		 9768 val = tr32(TG3_CPMU_CTRL);
9769 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9770 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 9771
9772 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9773 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9774 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9775 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9776
9777 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9778 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9779 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9780 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9781
9782 val = tr32(TG3_CPMU_HST_ACC);
9783 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9784 val |= CPMU_HST_ACC_MACCLK_6_25;
9785 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 9786 }
9787
4153577a 9788 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
33466d93
MC		 9789 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9790 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9791 PCIE_PWR_MGMT_L1_THRESH_4MS;
9792 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 9793
9794 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9795 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9796
9797 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 9798
f40386c8
MC		 9799 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9800 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 9801 }
9802
63c3a66f 9803 if (tg3_flag(tp, L1PLLPD_EN)) {
614b0590
MC		 9804 u32 grc_mode = tr32(GRC_MODE);
9805
9806 /* Access the lower 1K of PL PCIE block registers. */
9807 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9808 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9809
9810 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9811 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9812 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9813
9814 tw32(GRC_MODE, grc_mode);
9815 }
9816
55086ad9 9817 if (tg3_flag(tp, 57765_CLASS)) {
4153577a 9818 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
5093eedc 9819 u32 grc_mode = tr32(GRC_MODE);
cea46462 9820
5093eedc
MC		 9821 /* Access the lower 1K of PL PCIE block registers. */
9822 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9823 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
cea46462 9824
5093eedc
MC		 9825 val = tr32(TG3_PCIE_TLDLPL_PORT +
9826 TG3_PCIE_PL_LO_PHYCTL5);
9827 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9828 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
cea46462 9829
5093eedc
MC		 9830 tw32(GRC_MODE, grc_mode);
9831 }
a977dbe8 9832
4153577a 9833 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
d3f677af
MC		 9834 u32 grc_mode;
9835
9836 /* Fix transmit hangs */
9837 val = tr32(TG3_CPMU_PADRNG_CTL);
9838 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9839 tw32(TG3_CPMU_PADRNG_CTL, val);
9840
9841 grc_mode = tr32(GRC_MODE);
1ff30a59
MC		 9842
9843 /* Access the lower 1K of DL PCIE block registers. */
9844 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9845 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9846
9847 val = tr32(TG3_PCIE_TLDLPL_PORT +
9848 TG3_PCIE_DL_LO_FTSMAX);
9849 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9850 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9851 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9852
9853 tw32(GRC_MODE, grc_mode);
9854 }
9855
a977dbe8
MC		 9856 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9857 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9858 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9859 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
cea46462
MC		 9860 }
9861
1da177e4
LT		 9862 /* This works around an issue with Athlon chipsets on
9863 * B3 tigon3 silicon. This bit has no effect on any
9864 * other revision. But do not set this on PCI Express
795d01c5 9865 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 9866 */
63c3a66f
JP		 9867 if (!tg3_flag(tp, CPMU_PRESENT)) {
9868 if (!tg3_flag(tp, PCI_EXPRESS))
795d01c5
MC		 9869 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9870 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9871 }
1da177e4 9872
4153577a 9873 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 9874 tg3_flag(tp, PCIX_MODE)) {
1da177e4
LT		 9875 val = tr32(TG3PCI_PCISTATE);
9876 val |= PCISTATE_RETRY_SAME_DMA;
9877 tw32(TG3PCI_PCISTATE, val);
9878 }
9879
63c3a66f 9880 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 9881 /* Allow reads and writes to the
9882 * APE register and memory space.
9883 */
9884 val = tr32(TG3PCI_PCISTATE);
9885 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 9886 PCISTATE_ALLOW_APE_SHMEM_WR |
9887 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 9888 tw32(TG3PCI_PCISTATE, val);
9889 }
9890
4153577a 9891 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
1da177e4
LT		 9892 /* Enable some hw fixes. */
9893 val = tr32(TG3PCI_MSI_DATA);
9894 val |= (1 << 26) | (1 << 28) | (1 << 29);
9895 tw32(TG3PCI_MSI_DATA, val);
9896 }
9897
9898 /* Descriptor ring init may make accesses to the
9899 * NIC SRAM area to setup the TX descriptors, so we
9900 * can only do this after the hardware has been
9901 * successfully reset.
9902 */
32d8c572
MC		 9903 err = tg3_init_rings(tp);
9904 if (err)
9905 return err;
1da177e4 9906
63c3a66f 9907 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 9908 val = tr32(TG3PCI_DMA_RW_CTRL) &
9909 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
4153577a 9910 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
1a319025 9911 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
55086ad9 9912 if (!tg3_flag(tp, 57765_CLASS) &&
4153577a
JP		 9913 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9914 tg3_asic_rev(tp) != ASIC_REV_5762)
0aebff48 9915 val |= DMA_RWCTRL_TAGGED_STAT_WA;
cbf9ca6c 9916 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
4153577a
JP		 9917 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9918 tg3_asic_rev(tp) != ASIC_REV_5761) {
d30cdd28
MC		 9919 /* This value is determined during the probe time DMA
9920 * engine test, tg3_test_dma.
9921 */
9922 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9923 }
1da177e4
LT		 9924
9925 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
9926 GRC_MODE_4X_NIC_SEND_RINGS |
9927 GRC_MODE_NO_TX_PHDR_CSUM |
9928 GRC_MODE_NO_RX_PHDR_CSUM);
9929 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 9930
9931 /* Pseudo-header checksum is done by hardware logic and not
9932 * the offload processers, so make the chip do the pseudo-
9933 * header checksums on receive. For transmit it is more
9934 * convenient to do the pseudo-header checksum in software
9935 * as Linux does that on transmit for us in all cases.
9936 */
9937 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4 9938
fb4ce8ad
MC		 9939 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
9940 if (tp->rxptpctl)
9941 tw32(TG3_RX_PTP_CTL,
9942 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
9943
9944 if (tg3_flag(tp, PTP_CAPABLE))
9945 val |= GRC_MODE_TIME_SYNC_ENABLE;
9946
9947 tw32(GRC_MODE, tp->grc_mode | val);
1da177e4
LT		 9948
9949 /* Setup the timer prescalar register. Clock is always 66Mhz. */
9950 val = tr32(GRC_MISC_CFG);
9951 val &= ~0xff;
9952 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
9953 tw32(GRC_MISC_CFG, val);
9954
9955 /* Initialize MBUF/DESC pool. */
63c3a66f 9956 if (tg3_flag(tp, 5750_PLUS)) {
1da177e4 9957 /* Do nothing. */
4153577a 9958 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
1da177e4 9959 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
4153577a 9960 if (tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 9961 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
9962 else
9963 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
9964 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
9965 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
63c3a66f 9966 } else if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 9967 int fw_len;
9968
077f849d 9969 fw_len = tp->fw_len;
1da177e4
LT		 9970 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
9971 tw32(BUFMGR_MB_POOL_ADDR,
9972 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
9973 tw32(BUFMGR_MB_POOL_SIZE,
9974 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
9975 }
1da177e4 9976
0f893dc6 9977 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 9978 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9979 tp->bufmgr_config.mbuf_read_dma_low_water);
9980 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9981 tp->bufmgr_config.mbuf_mac_rx_low_water);
9982 tw32(BUFMGR_MB_HIGH_WATER,
9983 tp->bufmgr_config.mbuf_high_water);
9984 } else {
9985 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9986 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
9987 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9988 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
9989 tw32(BUFMGR_MB_HIGH_WATER,
9990 tp->bufmgr_config.mbuf_high_water_jumbo);
9991 }
9992 tw32(BUFMGR_DMA_LOW_WATER,
9993 tp->bufmgr_config.dma_low_water);
9994 tw32(BUFMGR_DMA_HIGH_WATER,
9995 tp->bufmgr_config.dma_high_water);
9996
d309a46e 9997 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
4153577a 9998 if (tg3_asic_rev(tp) == ASIC_REV_5719)
d309a46e 9999 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
4153577a 10000 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
94962f7f 10001 tg3_asic_rev(tp) == ASIC_REV_5762 ||
4153577a
JP		 10002 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10003 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
4d958473 10004 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
d309a46e 10005 tw32(BUFMGR_MODE, val);
1da177e4
LT		 10006 for (i = 0; i < 2000; i++) {
10007 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10008 break;
10009 udelay(10);
10010 }
10011 if (i >= 2000) {
05dbe005 10012 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 10013 return -ENODEV;
10014 }
10015
4153577a 10016 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
eb07a940 10017 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
b5d3772c 10018
eb07a940 10019 tg3_setup_rxbd_thresholds(tp);
1da177e4
LT		 10020
10021 /* Initialize TG3_BDINFO's at:
10022 * RCVDBDI_STD_BD: standard eth size rx ring
10023 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10024 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10025 *
10026 * like so:
10027 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10028 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10029 * ring attribute flags
10030 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10031 *
10032 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10033 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10034 *
10035 * The size of each ring is fixed in the firmware, but the location is
10036 * configurable.
10037 */
10038 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10039 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 10040 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10041 ((u64) tpr->rx_std_mapping & 0xffffffff));
63c3a66f 10042 if (!tg3_flag(tp, 5717_PLUS))
87668d35
MC		 10043 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10044 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 10045
fdb72b38 10046 /* Disable the mini ring */
63c3a66f 10047 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10048 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10049 BDINFO_FLAGS_DISABLED);
10050
fdb72b38
MC		 10051 /* Program the jumbo buffer descriptor ring control
10052 * blocks on those devices that have them.
10053 */
4153577a 10054 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
63c3a66f 10055 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
1da177e4 10056
63c3a66f 10057 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
1da177e4 10058 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10059 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 10060 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10061 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
de9f5230
MC		 10062 val = TG3_RX_JMB_RING_SIZE(tp) <<
10063 BDINFO_FLAGS_MAXLEN_SHIFT;
1da177e4 10064 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
de9f5230 10065 val | BDINFO_FLAGS_USE_EXT_RECV);
63c3a66f 10066 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
c65a17f4 10067 tg3_flag(tp, 57765_CLASS) ||
4153577a 10068 tg3_asic_rev(tp) == ASIC_REV_5762)
87668d35
MC		 10069 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10070 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 10071 } else {
10072 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10073 BDINFO_FLAGS_DISABLED);
10074 }
10075
63c3a66f 10076 if (tg3_flag(tp, 57765_PLUS)) {
fa6b2aae 10077 val = TG3_RX_STD_RING_SIZE(tp);
7cb32cf2
MC		 10078 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10079 val |= (TG3_RX_STD_DMA_SZ << 2);
10080 } else
04380d40 10081 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38 10082 } else
de9f5230 10083 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 10084
10085 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 10086
411da640 10087 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 10088 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 10089
63c3a66f
JP		 10090 tpr->rx_jmb_prod_idx =
10091 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
66711e66 10092 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 10093
2d31ecaf
MC		 10094 tg3_rings_reset(tp);
10095
1da177e4 10096 /* Initialize MAC address and backoff seed. */
953c96e0 10097 __tg3_set_mac_addr(tp, false);
1da177e4
LT		 10098
10099 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 10100 tw32(MAC_RX_MTU_SIZE,
10101 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 10102
10103 /* The slot time is changed by tg3_setup_phy if we
10104 * run at gigabit with half duplex.
10105 */
f2096f94
MC		 10106 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10107 (6 << TX_LENGTHS_IPG_SHIFT) |
10108 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10109
4153577a
JP		 10110 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10111 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10112 val |= tr32(MAC_TX_LENGTHS) &
10113 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10114 TX_LENGTHS_CNT_DWN_VAL_MSK);
10115
10116 tw32(MAC_TX_LENGTHS, val);
1da177e4
LT		 10117
10118 /* Receive rules. */
10119 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10120 tw32(RCVLPC_CONFIG, 0x0181);
10121
10122 /* Calculate RDMAC_MODE setting early, we need it to determine
10123 * the RCVLPC_STATE_ENABLE mask.
10124 */
10125 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10126 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10127 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10128 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10129 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 10130
4153577a 10131 if (tg3_asic_rev(tp) == ASIC_REV_5717)
0339e4e3
MC		 10132 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10133
4153577a
JP		 10134 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10135 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10136 tg3_asic_rev(tp) == ASIC_REV_57780)
d30cdd28
MC		 10137 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10138 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10139 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10140
4153577a
JP		 10141 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10142 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10143 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a 10144 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 10145 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10146 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10147 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10148 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10149 }
10150 }
10151
63c3a66f 10152 if (tg3_flag(tp, PCI_EXPRESS))
85e94ced
MC		 10153 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10154
4153577a 10155 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
d3f677af
MC		 10156 tp->dma_limit = 0;
10157 if (tp->dev->mtu <= ETH_DATA_LEN) {
10158 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10159 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10160 }
10161 }
10162
63c3a66f
JP		 10163 if (tg3_flag(tp, HW_TSO_1) ||
10164 tg3_flag(tp, HW_TSO_2) ||
10165 tg3_flag(tp, HW_TSO_3))
027455ad
MC		 10166 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10167
108a6c16 10168 if (tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 10169 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10170 tg3_asic_rev(tp) == ASIC_REV_57780)
027455ad 10171 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4 10172
4153577a
JP		 10173 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10174 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10175 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10176
4153577a
JP		 10177 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10178 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10179 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10180 tg3_asic_rev(tp) == ASIC_REV_57780 ||
63c3a66f 10181 tg3_flag(tp, 57765_PLUS)) {
c65a17f4
MC		 10182 u32 tgtreg;
10183
4153577a 10184 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10185 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10186 else
10187 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10188
10189 val = tr32(tgtreg);
4153577a
JP		 10190 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10191 tg3_asic_rev(tp) == ASIC_REV_5762) {
b4495ed8
MC		 10192 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10193 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10194 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10195 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10196 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10197 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
b75cc0e4 10198 }
c65a17f4 10199 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
41a8a7ee
MC		 10200 }
10201
4153577a
JP		 10202 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10203 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10204 tg3_asic_rev(tp) == ASIC_REV_5762) {
c65a17f4
MC		 10205 u32 tgtreg;
10206
4153577a 10207 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10208 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10209 else
10210 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10211
10212 val = tr32(tgtreg);
10213 tw32(tgtreg, val |
d309a46e
MC		 10214 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10215 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10216 }
10217
1da177e4 10218 /* Receive/send statistics. */
63c3a66f 10219 if (tg3_flag(tp, 5750_PLUS)) {
1661394e
MC		 10220 val = tr32(RCVLPC_STATS_ENABLE);
10221 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10222 tw32(RCVLPC_STATS_ENABLE, val);
10223 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
63c3a66f 10224 tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10225 val = tr32(RCVLPC_STATS_ENABLE);
10226 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10227 tw32(RCVLPC_STATS_ENABLE, val);
10228 } else {
10229 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10230 }
10231 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10232 tw32(SNDDATAI_STATSENAB, 0xffffff);
10233 tw32(SNDDATAI_STATSCTRL,
10234 (SNDDATAI_SCTRL_ENABLE |
10235 SNDDATAI_SCTRL_FASTUPD));
10236
10237 /* Setup host coalescing engine. */
10238 tw32(HOSTCC_MODE, 0);
10239 for (i = 0; i < 2000; i++) {
10240 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10241 break;
10242 udelay(10);
10243 }
10244
d244c892 10245 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 10246
63c3a66f 10247 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10248 /* Status/statistics block address. See tg3_timer,
10249 * the tg3_periodic_fetch_stats call there, and
10250 * tg3_get_stats to see how this works for 5705/5750 chips.
10251 */
1da177e4
LT		 10252 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10253 ((u64) tp->stats_mapping >> 32));
10254 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10255 ((u64) tp->stats_mapping & 0xffffffff));
10256 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 10257
1da177e4 10258 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 10259
10260 /* Clear statistics and status block memory areas */
10261 for (i = NIC_SRAM_STATS_BLK;
10262 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10263 i += sizeof(u32)) {
10264 tg3_write_mem(tp, i, 0);
10265 udelay(40);
10266 }
1da177e4
LT		 10267 }
10268
10269 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10270
10271 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10272 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
63c3a66f 10273 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10274 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10275
f07e9af3
MC		 10276 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10277 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c94e3941
MC		 10278 /* reset to prevent losing 1st rx packet intermittently */
10279 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10280 udelay(10);
10281 }
10282
3bda1258 10283 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9e975cc2
MC		 10284 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10285 MAC_MODE_FHDE_ENABLE;
10286 if (tg3_flag(tp, ENABLE_APE))
10287 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
63c3a66f 10288 if (!tg3_flag(tp, 5705_PLUS) &&
f07e9af3 10289 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a 10290 tg3_asic_rev(tp) != ASIC_REV_5700)
e8f3f6ca 10291 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 10292 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10293 udelay(40);
10294
314fba34 10295 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
63c3a66f 10296 * If TG3_FLAG_IS_NIC is zero, we should read the
314fba34
MC		 10297 * register to preserve the GPIO settings for LOMs. The GPIOs,
10298 * whether used as inputs or outputs, are set by boot code after
10299 * reset.
10300 */
63c3a66f 10301 if (!tg3_flag(tp, IS_NIC)) {
314fba34
MC		 10302 u32 gpio_mask;
10303
9d26e213
MC		 10304 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10305 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10306 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc 10307
4153577a 10308 if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc
MC		 10309 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10310 GRC_LCLCTRL_GPIO_OUTPUT3;
10311
4153577a 10312 if (tg3_asic_rev(tp) == ASIC_REV_5755)
af36e6b6
MC		 10313 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10314
aaf84465 10315 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 10316 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10317
10318 /* GPIO1 must be driven high for eeprom write protect */
63c3a66f 10319 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9d26e213
MC		 10320 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10321 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 10322 }
1da177e4
LT		 10323 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10324 udelay(100);
10325
c3b5003b 10326 if (tg3_flag(tp, USING_MSIX)) {
baf8a94a 10327 val = tr32(MSGINT_MODE);
c3b5003b
MC		 10328 val |= MSGINT_MODE_ENABLE;
10329 if (tp->irq_cnt > 1)
10330 val |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 10331 if (!tg3_flag(tp, 1SHOT_MSI))
10332 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
baf8a94a
MC		 10333 tw32(MSGINT_MODE, val);
10334 }
10335
63c3a66f 10336 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10337 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10338 udelay(40);
10339 }
10340
10341 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10342 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10343 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10344 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10345 WDMAC_MODE_LNGREAD_ENAB);
10346
4153577a
JP		 10347 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10348 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10349 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a
JP		 10350 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10351 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
1da177e4
LT		 10352 /* nothing */
10353 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10354 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10355 val |= WDMAC_MODE_RX_ACCEL;
10356 }
10357 }
10358
d9ab5ad1 10359 /* Enable host coalescing bug fix */
63c3a66f 10360 if (tg3_flag(tp, 5755_PLUS))
f51f3562 10361 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 10362
4153577a 10363 if (tg3_asic_rev(tp) == ASIC_REV_5785)
788a035e
MC		 10364 val |= WDMAC_MODE_BURST_ALL_DATA;
10365
1da177e4
LT		 10366 tw32_f(WDMAC_MODE, val);
10367 udelay(40);
10368
63c3a66f 10369 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 10370 u16 pcix_cmd;
10371
10372 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10373 &pcix_cmd);
4153577a 10374 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
9974a356
MC		 10375 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10376 pcix_cmd |= PCI_X_CMD_READ_2K;
4153577a 10377 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
9974a356
MC		 10378 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10379 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 10380 }
9974a356
MC		 10381 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10382 pcix_cmd);
1da177e4
LT		 10383 }
10384
10385 tw32_f(RDMAC_MODE, rdmac_mode);
10386 udelay(40);
10387
9bc297ea
NS		 10388 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10389 tg3_asic_rev(tp) == ASIC_REV_5720) {
091f0ea3
MC		 10390 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10391 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10392 break;
10393 }
10394 if (i < TG3_NUM_RDMA_CHANNELS) {
10395 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10396 val |= tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10397 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10398 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
091f0ea3
MC		 10399 }
10400 }
10401
1da177e4 10402 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
63c3a66f 10403 if (!tg3_flag(tp, 5705_PLUS))
1da177e4 10404 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6 10405
4153577a 10406 if (tg3_asic_rev(tp) == ASIC_REV_5761)
9936bcf6
MC		 10407 tw32(SNDDATAC_MODE,
10408 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10409 else
10410 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10411
1da177e4
LT		 10412 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10413 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7cb32cf2 10414 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
63c3a66f 10415 if (tg3_flag(tp, LRG_PROD_RING_CAP))
7cb32cf2
MC		 10416 val |= RCVDBDI_MODE_LRG_RING_SZ;
10417 tw32(RCVDBDI_MODE, val);
1da177e4 10418 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
63c3a66f
JP		 10419 if (tg3_flag(tp, HW_TSO_1) ||
10420 tg3_flag(tp, HW_TSO_2) ||
10421 tg3_flag(tp, HW_TSO_3))
1da177e4 10422 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 10423 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
63c3a66f 10424 if (tg3_flag(tp, ENABLE_TSS))
baf8a94a
MC		 10425 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10426 tw32(SNDBDI_MODE, val);
1da177e4
LT		 10427 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10428
4153577a 10429 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
1da177e4
LT		 10430 err = tg3_load_5701_a0_firmware_fix(tp);
10431 if (err)
10432 return err;
10433 }
10434
c4dab506
NS		 10435 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10436 /* Ignore any errors for the firmware download. If download
10437 * fails, the device will operate with EEE disabled
10438 */
10439 tg3_load_57766_firmware(tp);
10440 }
10441
63c3a66f 10442 if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10443 err = tg3_load_tso_firmware(tp);
10444 if (err)
10445 return err;
10446 }
1da177e4
LT		 10447
10448 tp->tx_mode = TX_MODE_ENABLE;
f2096f94 10449
63c3a66f 10450 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 10451 tg3_asic_rev(tp) == ASIC_REV_5906)
b1d05210 10452 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
f2096f94 10453
4153577a
JP		 10454 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10455 tg3_asic_rev(tp) == ASIC_REV_5762) {
f2096f94
MC		 10456 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10457 tp->tx_mode &= ~val;
10458 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10459 }
10460
1da177e4
LT		 10461 tw32_f(MAC_TX_MODE, tp->tx_mode);
10462 udelay(100);
10463
63c3a66f 10464 if (tg3_flag(tp, ENABLE_RSS)) {
bcebcc46 10465 tg3_rss_write_indir_tbl(tp);
baf8a94a
MC		 10466
10467 /* Setup the "secret" hash key. */
10468 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10469 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10470 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10471 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10472 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10473 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10474 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10475 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10476 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10477 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10478 }
10479
1da177e4 10480 tp->rx_mode = RX_MODE_ENABLE;
63c3a66f 10481 if (tg3_flag(tp, 5755_PLUS))
af36e6b6
MC		 10482 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10483
378b72c8
NS		 10484 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10485 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10486
63c3a66f 10487 if (tg3_flag(tp, ENABLE_RSS))
baf8a94a
MC		 10488 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10489 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10490 RX_MODE_RSS_IPV6_HASH_EN |
10491 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10492 RX_MODE_RSS_IPV4_HASH_EN |
10493 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10494
1da177e4
LT		 10495 tw32_f(MAC_RX_MODE, tp->rx_mode);
10496 udelay(10);
10497
1da177e4
LT		 10498 tw32(MAC_LED_CTRL, tp->led_ctrl);
10499
10500 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
f07e9af3 10501 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
1da177e4
LT		 10502 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10503 udelay(10);
10504 }
10505 tw32_f(MAC_RX_MODE, tp->rx_mode);
10506 udelay(10);
10507
f07e9af3 10508 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a
JP		 10509 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10510 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
1da177e4
LT		 10511 /* Set drive transmission level to 1.2V */
10512 /* only if the signal pre-emphasis bit is not set */
10513 val = tr32(MAC_SERDES_CFG);
10514 val &= 0xfffff000;
10515 val |= 0x880;
10516 tw32(MAC_SERDES_CFG, val);
10517 }
4153577a 10518 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
1da177e4
LT		 10519 tw32(MAC_SERDES_CFG, 0x616000);
10520 }
10521
10522 /* Prevent chip from dropping frames when flow control
10523 * is enabled.
10524 */
55086ad9 10525 if (tg3_flag(tp, 57765_CLASS))
666bc831
MC		 10526 val = 1;
10527 else
10528 val = 2;
10529 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4 10530
4153577a 10531 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
f07e9af3 10532 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
1da177e4 10533 /* Use hardware link auto-negotiation */
63c3a66f 10534 tg3_flag_set(tp, HW_AUTONEG);
1da177e4
LT		 10535 }
10536
f07e9af3 10537 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
4153577a 10538 tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 10539 u32 tmp;
10540
10541 tmp = tr32(SERDES_RX_CTRL);
10542 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10543 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10544 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10545 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10546 }
10547
63c3a66f 10548 if (!tg3_flag(tp, USE_PHYLIB)) {
c6700ce2 10549 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
80096068 10550 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1da177e4 10551
953c96e0 10552 err = tg3_setup_phy(tp, false);
dd477003
MC		 10553 if (err)
10554 return err;
1da177e4 10555
f07e9af3
MC		 10556 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10557 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
dd477003
MC		 10558 u32 tmp;
10559
10560 /* Clear CRC stats. */
10561 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10562 tg3_writephy(tp, MII_TG3_TEST1,
10563 tmp | MII_TG3_TEST1_CRC_EN);
f08aa1a8 10564 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
dd477003 10565 }
1da177e4
LT		 10566 }
10567 }
10568
10569 __tg3_set_rx_mode(tp->dev);
10570
10571 /* Initialize receive rules. */
10572 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10573 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10574 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10575 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10576
63c3a66f 10577 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
1da177e4
LT		 10578 limit = 8;
10579 else
10580 limit = 16;
63c3a66f 10581 if (tg3_flag(tp, ENABLE_ASF))
1da177e4
LT		 10582 limit -= 4;
10583 switch (limit) {
10584 case 16:
10585 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10586 case 15:
10587 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10588 case 14:
10589 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10590 case 13:
10591 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10592 case 12:
10593 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10594 case 11:
10595 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10596 case 10:
10597 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10598 case 9:
10599 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10600 case 8:
10601 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10602 case 7:
10603 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10604 case 6:
10605 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10606 case 5:
10607 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10608 case 4:
10609 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10610 case 3:
10611 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10612 case 2:
10613 case 1:
10614
10615 default:
10616 break;
855e1111 10617 }
1da177e4 10618
63c3a66f 10619 if (tg3_flag(tp, ENABLE_APE))
9ce768ea
MC		 10620 /* Write our heartbeat update interval to APE. */
10621 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10622 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 10623
1da177e4
LT		 10624 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10625
1da177e4
LT		 10626 return 0;
10627}
10628
10629/* Called at device open time to get the chip ready for
10630 * packet processing. Invoked with tp->lock held.
10631 */
953c96e0 10632static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
1da177e4 10633{
df465abf
NS		 10634 /* Chip may have been just powered on. If so, the boot code may still
10635 * be running initialization. Wait for it to finish to avoid races in
10636 * accessing the hardware.
10637 */
10638 tg3_enable_register_access(tp);
10639 tg3_poll_fw(tp);
10640
1da177e4
LT		 10641 tg3_switch_clocks(tp);
10642
10643 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10644
2f751b67 10645 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 10646}
10647
aed93e0b
MC		 10648static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10649{
10650 int i;
10651
10652 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10653 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10654
10655 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10656 off += len;
10657
10658 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10659 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10660 memset(ocir, 0, TG3_OCIR_LEN);
10661 }
10662}
10663
10664/* sysfs attributes for hwmon */
10665static ssize_t tg3_show_temp(struct device *dev,
10666 struct device_attribute *devattr, char *buf)
10667{
aed93e0b 10668 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
a2f4dfba 10669 struct tg3 *tp = dev_get_drvdata(dev);
aed93e0b
MC		 10670 u32 temperature;
10671
10672 spin_lock_bh(&tp->lock);
10673 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10674 sizeof(temperature));
10675 spin_unlock_bh(&tp->lock);
10676 return sprintf(buf, "%u\n", temperature);
10677}
10678
10679
10680static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10681 TG3_TEMP_SENSOR_OFFSET);
10682static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10683 TG3_TEMP_CAUTION_OFFSET);
10684static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10685 TG3_TEMP_MAX_OFFSET);
10686
a2f4dfba 10687static struct attribute *tg3_attrs[] = {
aed93e0b
MC		 10688 &sensor_dev_attr_temp1_input.dev_attr.attr,
10689 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10690 &sensor_dev_attr_temp1_max.dev_attr.attr,
10691 NULL
10692};
a2f4dfba 10693ATTRIBUTE_GROUPS(tg3);
aed93e0b 10694
aed93e0b
MC		 10695static void tg3_hwmon_close(struct tg3 *tp)
10696{
aed93e0b
MC		 10697 if (tp->hwmon_dev) {
10698 hwmon_device_unregister(tp->hwmon_dev);
10699 tp->hwmon_dev = NULL;
aed93e0b 10700 }
aed93e0b
MC		 10701}
10702
10703static void tg3_hwmon_open(struct tg3 *tp)
10704{
a2f4dfba 10705 int i;
aed93e0b
MC		 10706 u32 size = 0;
10707 struct pci_dev *pdev = tp->pdev;
10708 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10709
10710 tg3_sd_scan_scratchpad(tp, ocirs);
10711
10712 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10713 if (!ocirs[i].src_data_length)
10714 continue;
10715
10716 size += ocirs[i].src_hdr_length;
10717 size += ocirs[i].src_data_length;
10718 }
10719
10720 if (!size)
10721 return;
10722
a2f4dfba
GR		 10723 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10724 tp, tg3_groups);
aed93e0b
MC		 10725 if (IS_ERR(tp->hwmon_dev)) {
10726 tp->hwmon_dev = NULL;
10727 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
aed93e0b 10728 }
aed93e0b
MC		 10729}
10730
10731
1da177e4
LT		 10732#define TG3_STAT_ADD32(PSTAT, REG) \
10733do { u32 __val = tr32(REG); \
10734 (PSTAT)->low += __val; \
10735 if ((PSTAT)->low < __val) \
10736 (PSTAT)->high += 1; \
10737} while (0)
10738
10739static void tg3_periodic_fetch_stats(struct tg3 *tp)
10740{
10741 struct tg3_hw_stats *sp = tp->hw_stats;
10742
f4a46d1f 10743 if (!tp->link_up)
1da177e4
LT		 10744 return;
10745
10746 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10747 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10748 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10749 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10750 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10751 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10752 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10753 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10754 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10755 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10756 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10757 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10758 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9bc297ea 10759 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
091f0ea3
MC		 10760 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10761 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10762 u32 val;
10763
10764 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10765 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10766 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10767 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
091f0ea3 10768 }
1da177e4
LT		 10769
10770 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10771 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10772 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10773 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10774 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10775 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10776 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10777 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10778 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10779 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10780 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10781 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10782 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10783 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 10784
10785 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
4153577a 10786 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
94962f7f 10787 tg3_asic_rev(tp) != ASIC_REV_5762 &&
4153577a
JP		 10788 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10789 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
4d958473
MC		 10790 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10791 } else {
10792 u32 val = tr32(HOSTCC_FLOW_ATTN);
10793 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10794 if (val) {
10795 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10796 sp->rx_discards.low += val;
10797 if (sp->rx_discards.low < val)
10798 sp->rx_discards.high += 1;
10799 }
10800 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10801 }
463d305b 10802 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 10803}
10804
0e6cf6a9
MC		 10805static void tg3_chk_missed_msi(struct tg3 *tp)
10806{
10807 u32 i;
10808
10809 for (i = 0; i < tp->irq_cnt; i++) {
10810 struct tg3_napi *tnapi = &tp->napi[i];
10811
10812 if (tg3_has_work(tnapi)) {
10813 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10814 tnapi->last_tx_cons == tnapi->tx_cons) {
10815 if (tnapi->chk_msi_cnt < 1) {
10816 tnapi->chk_msi_cnt++;
10817 return;
10818 }
7f230735 10819 tg3_msi(0, tnapi);
0e6cf6a9
MC		 10820 }
10821 }
10822 tnapi->chk_msi_cnt = 0;
10823 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10824 tnapi->last_tx_cons = tnapi->tx_cons;
10825 }
10826}
10827
1da177e4
LT		 10828static void tg3_timer(unsigned long __opaque)
10829{
10830 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 10831
5b190624 10832 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
f475f163
MC		 10833 goto restart_timer;
10834
f47c11ee 10835 spin_lock(&tp->lock);
1da177e4 10836
4153577a 10837 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
55086ad9 10838 tg3_flag(tp, 57765_CLASS))
0e6cf6a9
MC		 10839 tg3_chk_missed_msi(tp);
10840
7e6c63f0
HM		 10841 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10842 /* BCM4785: Flush posted writes from GbE to host memory. */
10843 tr32(HOSTCC_MODE);
10844 }
10845
63c3a66f 10846 if (!tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 10847 /* All of this garbage is because when using non-tagged
10848 * IRQ status the mailbox/status_block protocol the chip
10849 * uses with the cpu is race prone.
10850 */
898a56f8 10851 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 10852 tw32(GRC_LOCAL_CTRL,
10853 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10854 } else {
10855 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 10856 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 10857 }
1da177e4 10858
fac9b83e 10859 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
f47c11ee 10860 spin_unlock(&tp->lock);
db219973 10861 tg3_reset_task_schedule(tp);
5b190624 10862 goto restart_timer;
fac9b83e 10863 }
1da177e4
LT		 10864 }
10865
1da177e4
LT		 10866 /* This part only runs once per second. */
10867 if (!--tp->timer_counter) {
63c3a66f 10868 if (tg3_flag(tp, 5705_PLUS))
fac9b83e
DM		 10869 tg3_periodic_fetch_stats(tp);
10870
b0c5943f
MC		 10871 if (tp->setlpicnt && !--tp->setlpicnt)
10872 tg3_phy_eee_enable(tp);
52b02d04 10873
63c3a66f 10874 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 10875 u32 mac_stat;
10876 int phy_event;
10877
10878 mac_stat = tr32(MAC_STATUS);
10879
10880 phy_event = 0;
f07e9af3 10881 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
1da177e4
LT		 10882 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10883 phy_event = 1;
10884 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10885 phy_event = 1;
10886
10887 if (phy_event)
953c96e0 10888 tg3_setup_phy(tp, false);
63c3a66f 10889 } else if (tg3_flag(tp, POLL_SERDES)) {
1da177e4
LT		 10890 u32 mac_stat = tr32(MAC_STATUS);
10891 int need_setup = 0;
10892
f4a46d1f 10893 if (tp->link_up &&
1da177e4
LT		 10894 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10895 need_setup = 1;
10896 }
f4a46d1f 10897 if (!tp->link_up &&
1da177e4
LT		 10898 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10899 MAC_STATUS_SIGNAL_DET))) {
10900 need_setup = 1;
10901 }
10902 if (need_setup) {
3d3ebe74
MC		 10903 if (!tp->serdes_counter) {
10904 tw32_f(MAC_MODE,
10905 (tp->mac_mode &
10906 ~MAC_MODE_PORT_MODE_MASK));
10907 udelay(40);
10908 tw32_f(MAC_MODE, tp->mac_mode);
10909 udelay(40);
10910 }
953c96e0 10911 tg3_setup_phy(tp, false);
1da177e4 10912 }
f07e9af3 10913 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
63c3a66f 10914 tg3_flag(tp, 5780_CLASS)) {
747e8f8b 10915 tg3_serdes_parallel_detect(tp);
57d8b880 10916 }
1da177e4
LT		 10917
10918 tp->timer_counter = tp->timer_multiplier;
10919 }
10920
130b8e4d
MC		 10921 /* Heartbeat is only sent once every 2 seconds.
10922 *
10923 * The heartbeat is to tell the ASF firmware that the host
10924 * driver is still alive. In the event that the OS crashes,
10925 * ASF needs to reset the hardware to free up the FIFO space
10926 * that may be filled with rx packets destined for the host.
10927 * If the FIFO is full, ASF will no longer function properly.
10928 *
10929 * Unintended resets have been reported on real time kernels
10930 * where the timer doesn't run on time. Netpoll will also have
10931 * same problem.
10932 *
10933 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
10934 * to check the ring condition when the heartbeat is expiring
10935 * before doing the reset. This will prevent most unintended
10936 * resets.
10937 */
1da177e4 10938 if (!--tp->asf_counter) {
63c3a66f 10939 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7c5026aa
MC		 10940 tg3_wait_for_event_ack(tp);
10941
bbadf503 10942 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 10943 FWCMD_NICDRV_ALIVE3);
bbadf503 10944 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
c6cdf436
MC		 10945 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
10946 TG3_FW_UPDATE_TIMEOUT_SEC);
4ba526ce
MC		 10947
10948 tg3_generate_fw_event(tp);
1da177e4
LT		 10949 }
10950 tp->asf_counter = tp->asf_multiplier;
10951 }
10952
f47c11ee 10953 spin_unlock(&tp->lock);
1da177e4 10954
f475f163 10955restart_timer:
1da177e4
LT		 10956 tp->timer.expires = jiffies + tp->timer_offset;
10957 add_timer(&tp->timer);
10958}
10959
229b1ad1 10960static void tg3_timer_init(struct tg3 *tp)
21f7638e
MC		 10961{
10962 if (tg3_flag(tp, TAGGED_STATUS) &&
4153577a 10963 tg3_asic_rev(tp) != ASIC_REV_5717 &&
21f7638e
MC		 10964 !tg3_flag(tp, 57765_CLASS))
10965 tp->timer_offset = HZ;
10966 else
10967 tp->timer_offset = HZ / 10;
10968
10969 BUG_ON(tp->timer_offset > HZ);
10970
10971 tp->timer_multiplier = (HZ / tp->timer_offset);
10972 tp->asf_multiplier = (HZ / tp->timer_offset) *
10973 TG3_FW_UPDATE_FREQ_SEC;
10974
10975 init_timer(&tp->timer);
10976 tp->timer.data = (unsigned long) tp;
10977 tp->timer.function = tg3_timer;
10978}
10979
10980static void tg3_timer_start(struct tg3 *tp)
10981{
10982 tp->asf_counter = tp->asf_multiplier;
10983 tp->timer_counter = tp->timer_multiplier;
10984
10985 tp->timer.expires = jiffies + tp->timer_offset;
10986 add_timer(&tp->timer);
10987}
10988
10989static void tg3_timer_stop(struct tg3 *tp)
10990{
10991 del_timer_sync(&tp->timer);
10992}
10993
10994/* Restart hardware after configuration changes, self-test, etc.
10995 * Invoked with tp->lock held.
10996 */
953c96e0 10997static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
21f7638e
MC		 10998 __releases(tp->lock)
10999 __acquires(tp->lock)
11000{
11001 int err;
11002
11003 err = tg3_init_hw(tp, reset_phy);
11004 if (err) {
11005 netdev_err(tp->dev,
11006 "Failed to re-initialize device, aborting\n");
11007 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11008 tg3_full_unlock(tp);
11009 tg3_timer_stop(tp);
11010 tp->irq_sync = 0;
11011 tg3_napi_enable(tp);
11012 dev_close(tp->dev);
11013 tg3_full_lock(tp, 0);
11014 }
11015 return err;
11016}
11017
11018static void tg3_reset_task(struct work_struct *work)
11019{
11020 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11021 int err;
11022
11023 tg3_full_lock(tp, 0);
11024
11025 if (!netif_running(tp->dev)) {
11026 tg3_flag_clear(tp, RESET_TASK_PENDING);
11027 tg3_full_unlock(tp);
11028 return;
11029 }
11030
11031 tg3_full_unlock(tp);
11032
11033 tg3_phy_stop(tp);
11034
11035 tg3_netif_stop(tp);
11036
11037 tg3_full_lock(tp, 1);
11038
11039 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11040 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11041 tp->write32_rx_mbox = tg3_write_flush_reg32;
11042 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11043 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11044 }
11045
11046 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
953c96e0 11047 err = tg3_init_hw(tp, true);
21f7638e
MC		 11048 if (err)
11049 goto out;
11050
11051 tg3_netif_start(tp);
11052
11053out:
11054 tg3_full_unlock(tp);
11055
11056 if (!err)
11057 tg3_phy_start(tp);
11058
11059 tg3_flag_clear(tp, RESET_TASK_PENDING);
11060}
11061
4f125f42 11062static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 11063{
7d12e780 11064 irq_handler_t fn;
fcfa0a32 11065 unsigned long flags;
4f125f42
MC		 11066 char *name;
11067 struct tg3_napi *tnapi = &tp->napi[irq_num];
11068
11069 if (tp->irq_cnt == 1)
11070 name = tp->dev->name;
11071 else {
11072 name = &tnapi->irq_lbl[0];
21e315e1
NS		 11073 if (tnapi->tx_buffers && tnapi->rx_rcb)
11074 snprintf(name, IFNAMSIZ,
11075 "%s-txrx-%d", tp->dev->name, irq_num);
11076 else if (tnapi->tx_buffers)
11077 snprintf(name, IFNAMSIZ,
11078 "%s-tx-%d", tp->dev->name, irq_num);
11079 else if (tnapi->rx_rcb)
11080 snprintf(name, IFNAMSIZ,
11081 "%s-rx-%d", tp->dev->name, irq_num);
11082 else
11083 snprintf(name, IFNAMSIZ,
11084 "%s-%d", tp->dev->name, irq_num);
4f125f42
MC		 11085 name[IFNAMSIZ-1] = 0;
11086 }
fcfa0a32 11087
63c3a66f 11088 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
fcfa0a32 11089 fn = tg3_msi;
63c3a66f 11090 if (tg3_flag(tp, 1SHOT_MSI))
fcfa0a32 11091 fn = tg3_msi_1shot;
ab392d2d 11092 flags = 0;
fcfa0a32
MC		 11093 } else {
11094 fn = tg3_interrupt;
63c3a66f 11095 if (tg3_flag(tp, TAGGED_STATUS))
fcfa0a32 11096 fn = tg3_interrupt_tagged;
ab392d2d 11097 flags = IRQF_SHARED;
fcfa0a32 11098 }
4f125f42
MC		 11099
11100 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 11101}
11102
7938109f
MC		 11103static int tg3_test_interrupt(struct tg3 *tp)
11104{
09943a18 11105 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 11106 struct net_device *dev = tp->dev;
b16250e3 11107 int err, i, intr_ok = 0;
f6eb9b1f 11108 u32 val;
7938109f 11109
d4bc3927
MC		 11110 if (!netif_running(dev))
11111 return -ENODEV;
11112
7938109f
MC		 11113 tg3_disable_ints(tp);
11114
4f125f42 11115 free_irq(tnapi->irq_vec, tnapi);
7938109f 11116
f6eb9b1f
MC		 11117 /*
11118 * Turn off MSI one shot mode. Otherwise this test has no
11119 * observable way to know whether the interrupt was delivered.
11120 */
3aa1cdf8 11121 if (tg3_flag(tp, 57765_PLUS)) {
f6eb9b1f
MC		 11122 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11123 tw32(MSGINT_MODE, val);
11124 }
11125
4f125f42 11126 err = request_irq(tnapi->irq_vec, tg3_test_isr,
f274fd9a 11127 IRQF_SHARED, dev->name, tnapi);
7938109f
MC		 11128 if (err)
11129 return err;
11130
898a56f8 11131 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 11132 tg3_enable_ints(tp);
11133
11134 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 11135 tnapi->coal_now);
7938109f
MC		 11136
11137 for (i = 0; i < 5; i++) {
b16250e3
MC		 11138 u32 int_mbox, misc_host_ctrl;
11139
898a56f8 11140 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 11141 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11142
11143 if ((int_mbox != 0) ||
11144 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11145 intr_ok = 1;
7938109f 11146 break;
b16250e3
MC		 11147 }
11148
3aa1cdf8
MC		 11149 if (tg3_flag(tp, 57765_PLUS) &&
11150 tnapi->hw_status->status_tag != tnapi->last_tag)
11151 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11152
7938109f
MC		 11153 msleep(10);
11154 }
11155
11156 tg3_disable_ints(tp);
11157
4f125f42 11158 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 11159
4f125f42 11160 err = tg3_request_irq(tp, 0);
7938109f
MC		 11161
11162 if (err)
11163 return err;
11164
f6eb9b1f
MC		 11165 if (intr_ok) {
11166 /* Reenable MSI one shot mode. */
5b39de91 11167 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
f6eb9b1f
MC		 11168 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11169 tw32(MSGINT_MODE, val);
11170 }
7938109f 11171 return 0;
f6eb9b1f 11172 }
7938109f
MC		 11173
11174 return -EIO;
11175}
11176
11177/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11178 * successfully restored
11179 */
11180static int tg3_test_msi(struct tg3 *tp)
11181{
7938109f
MC		 11182 int err;
11183 u16 pci_cmd;
11184
63c3a66f 11185 if (!tg3_flag(tp, USING_MSI))
7938109f
MC		 11186 return 0;
11187
11188 /* Turn off SERR reporting in case MSI terminates with Master
11189 * Abort.
11190 */
11191 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11192 pci_write_config_word(tp->pdev, PCI_COMMAND,
11193 pci_cmd & ~PCI_COMMAND_SERR);
11194
11195 err = tg3_test_interrupt(tp);
11196
11197 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11198
11199 if (!err)
11200 return 0;
11201
11202 /* other failures */
11203 if (err != -EIO)
11204 return err;
11205
11206 /* MSI test failed, go back to INTx mode */
5129c3a3
MC		 11207 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11208 "to INTx mode. Please report this failure to the PCI "
11209 "maintainer and include system chipset information\n");
7938109f 11210
4f125f42 11211 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 11212
7938109f
MC		 11213 pci_disable_msi(tp->pdev);
11214
63c3a66f 11215 tg3_flag_clear(tp, USING_MSI);
dc8bf1b1 11216 tp->napi[0].irq_vec = tp->pdev->irq;
7938109f 11217
4f125f42 11218 err = tg3_request_irq(tp, 0);
7938109f
MC		 11219 if (err)
11220 return err;
11221
11222 /* Need to reset the chip because the MSI cycle may have terminated
11223 * with Master Abort.
11224 */
f47c11ee 11225 tg3_full_lock(tp, 1);
7938109f 11226
944d980e 11227 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 11228 err = tg3_init_hw(tp, true);
7938109f 11229
f47c11ee 11230 tg3_full_unlock(tp);
7938109f
MC		 11231
11232 if (err)
4f125f42 11233 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 11234
11235 return err;
11236}
11237
9e9fd12d
MC		 11238static int tg3_request_firmware(struct tg3 *tp)
11239{
77997ea3 11240 const struct tg3_firmware_hdr *fw_hdr;
9e9fd12d
MC		 11241
11242 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 11243 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11244 tp->fw_needed);
9e9fd12d
MC		 11245 return -ENOENT;
11246 }
11247
77997ea3 11248 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
9e9fd12d
MC		 11249
11250 /* Firmware blob starts with version numbers, followed by
11251 * start address and _full_ length including BSS sections
11252 * (which must be longer than the actual data, of course
11253 */
11254
77997ea3
NS		 11255 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11256 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
05dbe005
JP		 11257 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11258 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 11259 release_firmware(tp->fw);
11260 tp->fw = NULL;
11261 return -EINVAL;
11262 }
11263
11264 /* We no longer need firmware; we have it. */
11265 tp->fw_needed = NULL;
11266 return 0;
11267}
11268
9102426a 11269static u32 tg3_irq_count(struct tg3 *tp)
679563f4 11270{
9102426a 11271 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
679563f4 11272
9102426a 11273 if (irq_cnt > 1) {
c3b5003b
MC		 11274 /* We want as many rx rings enabled as there are cpus.
11275 * In multiqueue MSI-X mode, the first MSI-X vector
11276 * only deals with link interrupts, etc, so we add
11277 * one to the number of vectors we are requesting.
11278 */
9102426a 11279 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
c3b5003b 11280 }
679563f4 11281
9102426a
MC		 11282 return irq_cnt;
11283}
11284
11285static bool tg3_enable_msix(struct tg3 *tp)
11286{
11287 int i, rc;
86449944 11288 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
9102426a 11289
0968169c
MC		 11290 tp->txq_cnt = tp->txq_req;
11291 tp->rxq_cnt = tp->rxq_req;
11292 if (!tp->rxq_cnt)
11293 tp->rxq_cnt = netif_get_num_default_rss_queues();
9102426a
MC		 11294 if (tp->rxq_cnt > tp->rxq_max)
11295 tp->rxq_cnt = tp->rxq_max;
cf6d6ea6
MC		 11296
11297 /* Disable multiple TX rings by default. Simple round-robin hardware
11298 * scheduling of the TX rings can cause starvation of rings with
11299 * small packets when other rings have TSO or jumbo packets.
11300 */
11301 if (!tp->txq_req)
11302 tp->txq_cnt = 1;
9102426a
MC		 11303
11304 tp->irq_cnt = tg3_irq_count(tp);
11305
679563f4
MC		 11306 for (i = 0; i < tp->irq_max; i++) {
11307 msix_ent[i].entry = i;
11308 msix_ent[i].vector = 0;
11309 }
11310
11311 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
2430b031
MC		 11312 if (rc < 0) {
11313 return false;
11314 } else if (rc != 0) {
679563f4
MC		 11315 if (pci_enable_msix(tp->pdev, msix_ent, rc))
11316 return false;
05dbe005
JP		 11317 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11318 tp->irq_cnt, rc);
679563f4 11319 tp->irq_cnt = rc;
49a359e3 11320 tp->rxq_cnt = max(rc - 1, 1);
9102426a
MC		 11321 if (tp->txq_cnt)
11322 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
679563f4
MC		 11323 }
11324
11325 for (i = 0; i < tp->irq_max; i++)
11326 tp->napi[i].irq_vec = msix_ent[i].vector;
11327
49a359e3 11328 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
2ddaad39
BH		 11329 pci_disable_msix(tp->pdev);
11330 return false;
11331 }
b92b9040 11332
9102426a
MC		 11333 if (tp->irq_cnt == 1)
11334 return true;
d78b59f5 11335
9102426a
MC		 11336 tg3_flag_set(tp, ENABLE_RSS);
11337
11338 if (tp->txq_cnt > 1)
11339 tg3_flag_set(tp, ENABLE_TSS);
11340
11341 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
2430b031 11342
679563f4
MC		 11343 return true;
11344}
11345
07b0173c
MC		 11346static void tg3_ints_init(struct tg3 *tp)
11347{
63c3a66f
JP		 11348 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11349 !tg3_flag(tp, TAGGED_STATUS)) {
07b0173c
MC		 11350 /* All MSI supporting chips should support tagged
11351 * status. Assert that this is the case.
11352 */
5129c3a3
MC		 11353 netdev_warn(tp->dev,
11354 "MSI without TAGGED_STATUS? Not using MSI\n");
679563f4 11355 goto defcfg;
07b0173c 11356 }
4f125f42 11357
63c3a66f
JP		 11358 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11359 tg3_flag_set(tp, USING_MSIX);
11360 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11361 tg3_flag_set(tp, USING_MSI);
679563f4 11362
63c3a66f 11363 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
679563f4 11364 u32 msi_mode = tr32(MSGINT_MODE);
63c3a66f 11365 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
baf8a94a 11366 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 11367 if (!tg3_flag(tp, 1SHOT_MSI))
11368 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
679563f4
MC		 11369 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11370 }
11371defcfg:
63c3a66f 11372 if (!tg3_flag(tp, USING_MSIX)) {
679563f4
MC		 11373 tp->irq_cnt = 1;
11374 tp->napi[0].irq_vec = tp->pdev->irq;
49a359e3
MC		 11375 }
11376
11377 if (tp->irq_cnt == 1) {
11378 tp->txq_cnt = 1;
11379 tp->rxq_cnt = 1;
2ddaad39 11380 netif_set_real_num_tx_queues(tp->dev, 1);
85407885 11381 netif_set_real_num_rx_queues(tp->dev, 1);
679563f4 11382 }
07b0173c
MC		 11383}
11384
11385static void tg3_ints_fini(struct tg3 *tp)
11386{
63c3a66f 11387 if (tg3_flag(tp, USING_MSIX))
679563f4 11388 pci_disable_msix(tp->pdev);
63c3a66f 11389 else if (tg3_flag(tp, USING_MSI))
679563f4 11390 pci_disable_msi(tp->pdev);
63c3a66f
JP		 11391 tg3_flag_clear(tp, USING_MSI);
11392 tg3_flag_clear(tp, USING_MSIX);
11393 tg3_flag_clear(tp, ENABLE_RSS);
11394 tg3_flag_clear(tp, ENABLE_TSS);
07b0173c
MC		 11395}
11396
be947307
MC		 11397static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11398 bool init)
1da177e4 11399{
d8f4cd38 11400 struct net_device *dev = tp->dev;
4f125f42 11401 int i, err;
1da177e4 11402
679563f4
MC		 11403 /*
11404 * Setup interrupts first so we know how
11405 * many NAPI resources to allocate
11406 */
11407 tg3_ints_init(tp);
11408
90415477 11409 tg3_rss_check_indir_tbl(tp);
bcebcc46 11410
1da177e4
LT		 11411 /* The placement of this call is tied
11412 * to the setup and use of Host TX descriptors.
11413 */
11414 err = tg3_alloc_consistent(tp);
11415 if (err)
4a5f46f2 11416 goto out_ints_fini;
88b06bc2 11417
66cfd1bd
MC		 11418 tg3_napi_init(tp);
11419
fed97810 11420 tg3_napi_enable(tp);
1da177e4 11421
4f125f42
MC		 11422 for (i = 0; i < tp->irq_cnt; i++) {
11423 struct tg3_napi *tnapi = &tp->napi[i];
11424 err = tg3_request_irq(tp, i);
11425 if (err) {
5bc09186
MC		 11426 for (i--; i >= 0; i--) {
11427 tnapi = &tp->napi[i];
4f125f42 11428 free_irq(tnapi->irq_vec, tnapi);
5bc09186 11429 }
4a5f46f2 11430 goto out_napi_fini;
4f125f42
MC		 11431 }
11432 }
1da177e4 11433
f47c11ee 11434 tg3_full_lock(tp, 0);
1da177e4 11435
2e460fc0
NS		 11436 if (init)
11437 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11438
d8f4cd38 11439 err = tg3_init_hw(tp, reset_phy);
1da177e4 11440 if (err) {
944d980e 11441 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11442 tg3_free_rings(tp);
1da177e4
LT		 11443 }
11444
f47c11ee 11445 tg3_full_unlock(tp);
1da177e4 11446
07b0173c 11447 if (err)
4a5f46f2 11448 goto out_free_irq;
1da177e4 11449
d8f4cd38 11450 if (test_irq && tg3_flag(tp, USING_MSI)) {
7938109f 11451 err = tg3_test_msi(tp);
fac9b83e 11452
7938109f 11453 if (err) {
f47c11ee 11454 tg3_full_lock(tp, 0);
944d980e 11455 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 11456 tg3_free_rings(tp);
f47c11ee 11457 tg3_full_unlock(tp);
7938109f 11458
4a5f46f2 11459 goto out_napi_fini;
7938109f 11460 }
fcfa0a32 11461
63c3a66f 11462 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
f6eb9b1f 11463 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 11464
f6eb9b1f
MC		 11465 tw32(PCIE_TRANSACTION_CFG,
11466 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 11467 }
7938109f
MC		 11468 }
11469
b02fd9e3
MC		 11470 tg3_phy_start(tp);
11471
aed93e0b
MC		 11472 tg3_hwmon_open(tp);
11473
f47c11ee 11474 tg3_full_lock(tp, 0);
1da177e4 11475
21f7638e 11476 tg3_timer_start(tp);
63c3a66f 11477 tg3_flag_set(tp, INIT_COMPLETE);
1da177e4
LT		 11478 tg3_enable_ints(tp);
11479
be947307
MC		 11480 if (init)
11481 tg3_ptp_init(tp);
11482 else
11483 tg3_ptp_resume(tp);
11484
11485
f47c11ee 11486 tg3_full_unlock(tp);
1da177e4 11487
fe5f5787 11488 netif_tx_start_all_queues(dev);
1da177e4 11489
06c03c02
MB		 11490 /*
11491 * Reset loopback feature if it was turned on while the device was down
11492 * make sure that it's installed properly now.
11493 */
11494 if (dev->features & NETIF_F_LOOPBACK)
11495 tg3_set_loopback(dev, dev->features);
11496
1da177e4 11497 return 0;
07b0173c 11498
4a5f46f2 11499out_free_irq:
4f125f42
MC		 11500 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11501 struct tg3_napi *tnapi = &tp->napi[i];
11502 free_irq(tnapi->irq_vec, tnapi);
11503 }
07b0173c 11504
4a5f46f2 11505out_napi_fini:
fed97810 11506 tg3_napi_disable(tp);
66cfd1bd 11507 tg3_napi_fini(tp);
07b0173c 11508 tg3_free_consistent(tp);
679563f4 11509
4a5f46f2 11510out_ints_fini:
679563f4 11511 tg3_ints_fini(tp);
d8f4cd38 11512
07b0173c 11513 return err;
1da177e4
LT		 11514}
11515
65138594 11516static void tg3_stop(struct tg3 *tp)
1da177e4 11517{
4f125f42 11518 int i;
1da177e4 11519
db219973 11520 tg3_reset_task_cancel(tp);
bd473da3 11521 tg3_netif_stop(tp);
1da177e4 11522
21f7638e 11523 tg3_timer_stop(tp);
1da177e4 11524
aed93e0b
MC		 11525 tg3_hwmon_close(tp);
11526
24bb4fb6
MC		 11527 tg3_phy_stop(tp);
11528
f47c11ee 11529 tg3_full_lock(tp, 1);
1da177e4
LT		 11530
11531 tg3_disable_ints(tp);
11532
944d980e 11533 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11534 tg3_free_rings(tp);
63c3a66f 11535 tg3_flag_clear(tp, INIT_COMPLETE);
1da177e4 11536
f47c11ee 11537 tg3_full_unlock(tp);
1da177e4 11538
4f125f42
MC		 11539 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11540 struct tg3_napi *tnapi = &tp->napi[i];
11541 free_irq(tnapi->irq_vec, tnapi);
11542 }
07b0173c
MC		 11543
11544 tg3_ints_fini(tp);
1da177e4 11545
66cfd1bd
MC		 11546 tg3_napi_fini(tp);
11547
1da177e4 11548 tg3_free_consistent(tp);
65138594
MC		 11549}
11550
d8f4cd38
MC		 11551static int tg3_open(struct net_device *dev)
11552{
11553 struct tg3 *tp = netdev_priv(dev);
11554 int err;
11555
11556 if (tp->fw_needed) {
11557 err = tg3_request_firmware(tp);
c4dab506
NS		 11558 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11559 if (err) {
11560 netdev_warn(tp->dev, "EEE capability disabled\n");
11561 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11562 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11563 netdev_warn(tp->dev, "EEE capability restored\n");
11564 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11565 }
11566 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
d8f4cd38
MC		 11567 if (err)
11568 return err;
11569 } else if (err) {
11570 netdev_warn(tp->dev, "TSO capability disabled\n");
11571 tg3_flag_clear(tp, TSO_CAPABLE);
11572 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11573 netdev_notice(tp->dev, "TSO capability restored\n");
11574 tg3_flag_set(tp, TSO_CAPABLE);
11575 }
11576 }
11577
f4a46d1f 11578 tg3_carrier_off(tp);
d8f4cd38
MC		 11579
11580 err = tg3_power_up(tp);
11581 if (err)
11582 return err;
11583
11584 tg3_full_lock(tp, 0);
11585
11586 tg3_disable_ints(tp);
11587 tg3_flag_clear(tp, INIT_COMPLETE);
11588
11589 tg3_full_unlock(tp);
11590
942d1af0
NS		 11591 err = tg3_start(tp,
11592 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11593 true, true);
d8f4cd38
MC		 11594 if (err) {
11595 tg3_frob_aux_power(tp, false);
11596 pci_set_power_state(tp->pdev, PCI_D3hot);
11597 }
be947307 11598
7d41e49a
MC		 11599 if (tg3_flag(tp, PTP_CAPABLE)) {
11600 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11601 &tp->pdev->dev);
11602 if (IS_ERR(tp->ptp_clock))
11603 tp->ptp_clock = NULL;
11604 }
11605
07b0173c 11606 return err;
1da177e4
LT		 11607}
11608
1da177e4
LT		 11609static int tg3_close(struct net_device *dev)
11610{
11611 struct tg3 *tp = netdev_priv(dev);
11612
be947307
MC		 11613 tg3_ptp_fini(tp);
11614
65138594 11615 tg3_stop(tp);
1da177e4 11616
92feeabf
MC		 11617 /* Clear stats across close / open calls */
11618 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11619 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
1da177e4 11620
8496e85c
RW		 11621 if (pci_device_is_present(tp->pdev)) {
11622 tg3_power_down_prepare(tp);
bc1c7567 11623
8496e85c
RW		 11624 tg3_carrier_off(tp);
11625 }
1da177e4
LT		 11626 return 0;
11627}
11628
511d2224 11629static inline u64 get_stat64(tg3_stat64_t *val)
816f8b86
SB		 11630{
11631 return ((u64)val->high << 32) | ((u64)val->low);
11632}
11633
65ec698d 11634static u64 tg3_calc_crc_errors(struct tg3 *tp)
1da177e4
LT		 11635{
11636 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11637
f07e9af3 11638 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a
JP		 11639 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11640 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 11641 u32 val;
11642
569a5df8
MC		 11643 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11644 tg3_writephy(tp, MII_TG3_TEST1,
11645 val | MII_TG3_TEST1_CRC_EN);
f08aa1a8 11646 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
1da177e4
LT		 11647 } else
11648 val = 0;
1da177e4
LT		 11649
11650 tp->phy_crc_errors += val;
11651
11652 return tp->phy_crc_errors;
11653 }
11654
11655 return get_stat64(&hw_stats->rx_fcs_errors);
11656}
11657
11658#define ESTAT_ADD(member) \
11659 estats->member = old_estats->member + \
511d2224 11660 get_stat64(&hw_stats->member)
1da177e4 11661
65ec698d 11662static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
1da177e4 11663{
1da177e4
LT		 11664 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11665 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11666
1da177e4
LT		 11667 ESTAT_ADD(rx_octets);
11668 ESTAT_ADD(rx_fragments);
11669 ESTAT_ADD(rx_ucast_packets);
11670 ESTAT_ADD(rx_mcast_packets);
11671 ESTAT_ADD(rx_bcast_packets);
11672 ESTAT_ADD(rx_fcs_errors);
11673 ESTAT_ADD(rx_align_errors);
11674 ESTAT_ADD(rx_xon_pause_rcvd);
11675 ESTAT_ADD(rx_xoff_pause_rcvd);
11676 ESTAT_ADD(rx_mac_ctrl_rcvd);
11677 ESTAT_ADD(rx_xoff_entered);
11678 ESTAT_ADD(rx_frame_too_long_errors);
11679 ESTAT_ADD(rx_jabbers);
11680 ESTAT_ADD(rx_undersize_packets);
11681 ESTAT_ADD(rx_in_length_errors);
11682 ESTAT_ADD(rx_out_length_errors);
11683 ESTAT_ADD(rx_64_or_less_octet_packets);
11684 ESTAT_ADD(rx_65_to_127_octet_packets);
11685 ESTAT_ADD(rx_128_to_255_octet_packets);
11686 ESTAT_ADD(rx_256_to_511_octet_packets);
11687 ESTAT_ADD(rx_512_to_1023_octet_packets);
11688 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11689 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11690 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11691 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11692 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11693
11694 ESTAT_ADD(tx_octets);
11695 ESTAT_ADD(tx_collisions);
11696 ESTAT_ADD(tx_xon_sent);
11697 ESTAT_ADD(tx_xoff_sent);
11698 ESTAT_ADD(tx_flow_control);
11699 ESTAT_ADD(tx_mac_errors);
11700 ESTAT_ADD(tx_single_collisions);
11701 ESTAT_ADD(tx_mult_collisions);
11702 ESTAT_ADD(tx_deferred);
11703 ESTAT_ADD(tx_excessive_collisions);
11704 ESTAT_ADD(tx_late_collisions);
11705 ESTAT_ADD(tx_collide_2times);
11706 ESTAT_ADD(tx_collide_3times);
11707 ESTAT_ADD(tx_collide_4times);
11708 ESTAT_ADD(tx_collide_5times);
11709 ESTAT_ADD(tx_collide_6times);
11710 ESTAT_ADD(tx_collide_7times);
11711 ESTAT_ADD(tx_collide_8times);
11712 ESTAT_ADD(tx_collide_9times);
11713 ESTAT_ADD(tx_collide_10times);
11714 ESTAT_ADD(tx_collide_11times);
11715 ESTAT_ADD(tx_collide_12times);
11716 ESTAT_ADD(tx_collide_13times);
11717 ESTAT_ADD(tx_collide_14times);
11718 ESTAT_ADD(tx_collide_15times);
11719 ESTAT_ADD(tx_ucast_packets);
11720 ESTAT_ADD(tx_mcast_packets);
11721 ESTAT_ADD(tx_bcast_packets);
11722 ESTAT_ADD(tx_carrier_sense_errors);
11723 ESTAT_ADD(tx_discards);
11724 ESTAT_ADD(tx_errors);
11725
11726 ESTAT_ADD(dma_writeq_full);
11727 ESTAT_ADD(dma_write_prioq_full);
11728 ESTAT_ADD(rxbds_empty);
11729 ESTAT_ADD(rx_discards);
11730 ESTAT_ADD(rx_errors);
11731 ESTAT_ADD(rx_threshold_hit);
11732
11733 ESTAT_ADD(dma_readq_full);
11734 ESTAT_ADD(dma_read_prioq_full);
11735 ESTAT_ADD(tx_comp_queue_full);
11736
11737 ESTAT_ADD(ring_set_send_prod_index);
11738 ESTAT_ADD(ring_status_update);
11739 ESTAT_ADD(nic_irqs);
11740 ESTAT_ADD(nic_avoided_irqs);
11741 ESTAT_ADD(nic_tx_threshold_hit);
11742
4452d099 11743 ESTAT_ADD(mbuf_lwm_thresh_hit);
1da177e4
LT		 11744}
11745
65ec698d 11746static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
1da177e4 11747{
511d2224 11748 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
1da177e4
LT		 11749 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11750
1da177e4
LT		 11751 stats->rx_packets = old_stats->rx_packets +
11752 get_stat64(&hw_stats->rx_ucast_packets) +
11753 get_stat64(&hw_stats->rx_mcast_packets) +
11754 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 11755
1da177e4
LT		 11756 stats->tx_packets = old_stats->tx_packets +
11757 get_stat64(&hw_stats->tx_ucast_packets) +
11758 get_stat64(&hw_stats->tx_mcast_packets) +
11759 get_stat64(&hw_stats->tx_bcast_packets);
11760
11761 stats->rx_bytes = old_stats->rx_bytes +
11762 get_stat64(&hw_stats->rx_octets);
11763 stats->tx_bytes = old_stats->tx_bytes +
11764 get_stat64(&hw_stats->tx_octets);
11765
11766 stats->rx_errors = old_stats->rx_errors +
4f63b877 11767 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 11768 stats->tx_errors = old_stats->tx_errors +
11769 get_stat64(&hw_stats->tx_errors) +
11770 get_stat64(&hw_stats->tx_mac_errors) +
11771 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11772 get_stat64(&hw_stats->tx_discards);
11773
11774 stats->multicast = old_stats->multicast +
11775 get_stat64(&hw_stats->rx_mcast_packets);
11776 stats->collisions = old_stats->collisions +
11777 get_stat64(&hw_stats->tx_collisions);
11778
11779 stats->rx_length_errors = old_stats->rx_length_errors +
11780 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11781 get_stat64(&hw_stats->rx_undersize_packets);
11782
1da177e4
LT		 11783 stats->rx_frame_errors = old_stats->rx_frame_errors +
11784 get_stat64(&hw_stats->rx_align_errors);
11785 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11786 get_stat64(&hw_stats->tx_discards);
11787 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11788 get_stat64(&hw_stats->tx_carrier_sense_errors);
11789
11790 stats->rx_crc_errors = old_stats->rx_crc_errors +
65ec698d 11791 tg3_calc_crc_errors(tp);
1da177e4 11792
4f63b877
JL		 11793 stats->rx_missed_errors = old_stats->rx_missed_errors +
11794 get_stat64(&hw_stats->rx_discards);
11795
b0057c51 11796 stats->rx_dropped = tp->rx_dropped;
48855432 11797 stats->tx_dropped = tp->tx_dropped;
1da177e4
LT		 11798}
11799
1da177e4
LT		 11800static int tg3_get_regs_len(struct net_device *dev)
11801{
97bd8e49 11802 return TG3_REG_BLK_SIZE;
1da177e4
LT		 11803}
11804
11805static void tg3_get_regs(struct net_device *dev,
11806 struct ethtool_regs *regs, void *_p)
11807{
1da177e4 11808 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 11809
11810 regs->version = 0;
11811
97bd8e49 11812 memset(_p, 0, TG3_REG_BLK_SIZE);
1da177e4 11813
80096068 11814 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
bc1c7567
MC		 11815 return;
11816
f47c11ee 11817 tg3_full_lock(tp, 0);
1da177e4 11818
97bd8e49 11819 tg3_dump_legacy_regs(tp, (u32 *)_p);
1da177e4 11820
f47c11ee 11821 tg3_full_unlock(tp);
1da177e4
LT		 11822}
11823
11824static int tg3_get_eeprom_len(struct net_device *dev)
11825{
11826 struct tg3 *tp = netdev_priv(dev);
11827
11828 return tp->nvram_size;
11829}
11830
1da177e4
LT		 11831static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11832{
11833 struct tg3 *tp = netdev_priv(dev);
11834 int ret;
11835 u8 *pd;
b9fc7dc5 11836 u32 i, offset, len, b_offset, b_count;
a9dc529d 11837 __be32 val;
1da177e4 11838
63c3a66f 11839 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 11840 return -EINVAL;
11841
1da177e4
LT		 11842 offset = eeprom->offset;
11843 len = eeprom->len;
11844 eeprom->len = 0;
11845
11846 eeprom->magic = TG3_EEPROM_MAGIC;
11847
11848 if (offset & 3) {
11849 /* adjustments to start on required 4 byte boundary */
11850 b_offset = offset & 3;
11851 b_count = 4 - b_offset;
11852 if (b_count > len) {
11853 /* i.e. offset=1 len=2 */
11854 b_count = len;
11855 }
a9dc529d 11856 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 11857 if (ret)
11858 return ret;
be98da6a 11859 memcpy(data, ((char *)&val) + b_offset, b_count);
1da177e4
LT		 11860 len -= b_count;
11861 offset += b_count;
c6cdf436 11862 eeprom->len += b_count;
1da177e4
LT		 11863 }
11864
25985edc 11865 /* read bytes up to the last 4 byte boundary */
1da177e4
LT		 11866 pd = &data[eeprom->len];
11867 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 11868 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 11869 if (ret) {
11870 eeprom->len += i;
11871 return ret;
11872 }
1da177e4
LT		 11873 memcpy(pd + i, &val, 4);
11874 }
11875 eeprom->len += i;
11876
11877 if (len & 3) {
11878 /* read last bytes not ending on 4 byte boundary */
11879 pd = &data[eeprom->len];
11880 b_count = len & 3;
11881 b_offset = offset + len - b_count;
a9dc529d 11882 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 11883 if (ret)
11884 return ret;
b9fc7dc5 11885 memcpy(pd, &val, b_count);
1da177e4
LT		 11886 eeprom->len += b_count;
11887 }
11888 return 0;
11889}
11890
1da177e4
LT		 11891static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11892{
11893 struct tg3 *tp = netdev_priv(dev);
11894 int ret;
b9fc7dc5 11895 u32 offset, len, b_offset, odd_len;
1da177e4 11896 u8 *buf;
a9dc529d 11897 __be32 start, end;
1da177e4 11898
63c3a66f 11899 if (tg3_flag(tp, NO_NVRAM) ||
df259d8c 11900 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 11901 return -EINVAL;
11902
11903 offset = eeprom->offset;
11904 len = eeprom->len;
11905
11906 if ((b_offset = (offset & 3))) {
11907 /* adjustments to start on required 4 byte boundary */
a9dc529d 11908 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 11909 if (ret)
11910 return ret;
1da177e4
LT		 11911 len += b_offset;
11912 offset &= ~3;
1c8594b4
MC		 11913 if (len < 4)
11914 len = 4;
1da177e4
LT		 11915 }
11916
11917 odd_len = 0;
1c8594b4 11918 if (len & 3) {
1da177e4
LT		 11919 /* adjustments to end on required 4 byte boundary */
11920 odd_len = 1;
11921 len = (len + 3) & ~3;
a9dc529d 11922 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 11923 if (ret)
11924 return ret;
1da177e4
LT		 11925 }
11926
11927 buf = data;
11928 if (b_offset || odd_len) {
11929 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 11930 if (!buf)
1da177e4
LT		 11931 return -ENOMEM;
11932 if (b_offset)
11933 memcpy(buf, &start, 4);
11934 if (odd_len)
11935 memcpy(buf+len-4, &end, 4);
11936 memcpy(buf + b_offset, data, eeprom->len);
11937 }
11938
11939 ret = tg3_nvram_write_block(tp, offset, len, buf);
11940
11941 if (buf != data)
11942 kfree(buf);
11943
11944 return ret;
11945}
11946
11947static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11948{
b02fd9e3
MC		 11949 struct tg3 *tp = netdev_priv(dev);
11950
63c3a66f 11951 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 11952 struct phy_device *phydev;
f07e9af3 11953 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 11954 return -EAGAIN;
ead2402c 11955 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
3f0e3ad7 11956 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 11957 }
6aa20a22 11958
1da177e4
LT		 11959 cmd->supported = (SUPPORTED_Autoneg);
11960
f07e9af3 11961 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
1da177e4
LT		 11962 cmd->supported |= (SUPPORTED_1000baseT_Half |
11963 SUPPORTED_1000baseT_Full);
11964
f07e9af3 11965 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
1da177e4
LT		 11966 cmd->supported |= (SUPPORTED_100baseT_Half |
11967 SUPPORTED_100baseT_Full |
11968 SUPPORTED_10baseT_Half |
11969 SUPPORTED_10baseT_Full |
3bebab59 11970 SUPPORTED_TP);
ef348144
KK		 11971 cmd->port = PORT_TP;
11972 } else {
1da177e4 11973 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 11974 cmd->port = PORT_FIBRE;
11975 }
6aa20a22 11976
1da177e4 11977 cmd->advertising = tp->link_config.advertising;
5bb09778
MC		 11978 if (tg3_flag(tp, PAUSE_AUTONEG)) {
11979 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
11980 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11981 cmd->advertising |= ADVERTISED_Pause;
11982 } else {
11983 cmd->advertising |= ADVERTISED_Pause |
11984 ADVERTISED_Asym_Pause;
11985 }
11986 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11987 cmd->advertising |= ADVERTISED_Asym_Pause;
11988 }
11989 }
f4a46d1f 11990 if (netif_running(dev) && tp->link_up) {
70739497 11991 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
1da177e4 11992 cmd->duplex = tp->link_config.active_duplex;
859edb26 11993 cmd->lp_advertising = tp->link_config.rmt_adv;
e348c5e7
MC		 11994 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
11995 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
11996 cmd->eth_tp_mdix = ETH_TP_MDI_X;
11997 else
11998 cmd->eth_tp_mdix = ETH_TP_MDI;
11999 }
64c22182 12000 } else {
e740522e
MC		 12001 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
12002 cmd->duplex = DUPLEX_UNKNOWN;
e348c5e7 12003 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
1da177e4 12004 }
882e9793 12005 cmd->phy_address = tp->phy_addr;
7e5856bd 12006 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 12007 cmd->autoneg = tp->link_config.autoneg;
12008 cmd->maxtxpkt = 0;
12009 cmd->maxrxpkt = 0;
12010 return 0;
12011}
6aa20a22 12012
1da177e4
LT		 12013static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12014{
12015 struct tg3 *tp = netdev_priv(dev);
25db0338 12016 u32 speed = ethtool_cmd_speed(cmd);
6aa20a22 12017
63c3a66f 12018 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 12019 struct phy_device *phydev;
f07e9af3 12020 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12021 return -EAGAIN;
ead2402c 12022 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
3f0e3ad7 12023 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 12024 }
12025
7e5856bd
MC		 12026 if (cmd->autoneg != AUTONEG_ENABLE &&
12027 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 12028 return -EINVAL;
7e5856bd
MC		 12029
12030 if (cmd->autoneg == AUTONEG_DISABLE &&
12031 cmd->duplex != DUPLEX_FULL &&
12032 cmd->duplex != DUPLEX_HALF)
37ff238d 12033 return -EINVAL;
1da177e4 12034
7e5856bd
MC		 12035 if (cmd->autoneg == AUTONEG_ENABLE) {
12036 u32 mask = ADVERTISED_Autoneg |
12037 ADVERTISED_Pause |
12038 ADVERTISED_Asym_Pause;
12039
f07e9af3 12040 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
7e5856bd
MC		 12041 mask |= ADVERTISED_1000baseT_Half |
12042 ADVERTISED_1000baseT_Full;
12043
f07e9af3 12044 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
7e5856bd
MC		 12045 mask |= ADVERTISED_100baseT_Half |
12046 ADVERTISED_100baseT_Full |
12047 ADVERTISED_10baseT_Half |
12048 ADVERTISED_10baseT_Full |
12049 ADVERTISED_TP;
12050 else
12051 mask |= ADVERTISED_FIBRE;
12052
12053 if (cmd->advertising & ~mask)
12054 return -EINVAL;
12055
12056 mask &= (ADVERTISED_1000baseT_Half |
12057 ADVERTISED_1000baseT_Full |
12058 ADVERTISED_100baseT_Half |
12059 ADVERTISED_100baseT_Full |
12060 ADVERTISED_10baseT_Half |
12061 ADVERTISED_10baseT_Full);
12062
12063 cmd->advertising &= mask;
12064 } else {
f07e9af3 12065 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
25db0338 12066 if (speed != SPEED_1000)
7e5856bd
MC		 12067 return -EINVAL;
12068
12069 if (cmd->duplex != DUPLEX_FULL)
12070 return -EINVAL;
12071 } else {
25db0338
DD		 12072 if (speed != SPEED_100 &&
12073 speed != SPEED_10)
7e5856bd
MC		 12074 return -EINVAL;
12075 }
12076 }
12077
f47c11ee 12078 tg3_full_lock(tp, 0);
1da177e4
LT		 12079
12080 tp->link_config.autoneg = cmd->autoneg;
12081 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 12082 tp->link_config.advertising = (cmd->advertising |
12083 ADVERTISED_Autoneg);
e740522e
MC		 12084 tp->link_config.speed = SPEED_UNKNOWN;
12085 tp->link_config.duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 12086 } else {
12087 tp->link_config.advertising = 0;
25db0338 12088 tp->link_config.speed = speed;
1da177e4 12089 tp->link_config.duplex = cmd->duplex;
b02fd9e3 12090 }
6aa20a22 12091
fdad8de4
NS		 12092 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12093
ce20f161
NS		 12094 tg3_warn_mgmt_link_flap(tp);
12095
1da177e4 12096 if (netif_running(dev))
953c96e0 12097 tg3_setup_phy(tp, true);
1da177e4 12098
f47c11ee 12099 tg3_full_unlock(tp);
6aa20a22 12100
1da177e4
LT		 12101 return 0;
12102}
6aa20a22 12103
1da177e4
LT		 12104static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12105{
12106 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12107
68aad78c
RJ		 12108 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12109 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12110 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12111 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
1da177e4 12112}
6aa20a22 12113
1da177e4
LT		 12114static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12115{
12116 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12117
63c3a66f 12118 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 12119 wol->supported = WAKE_MAGIC;
12120 else
12121 wol->supported = 0;
1da177e4 12122 wol->wolopts = 0;
63c3a66f 12123 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 12124 wol->wolopts = WAKE_MAGIC;
12125 memset(&wol->sopass, 0, sizeof(wol->sopass));
12126}
6aa20a22 12127
1da177e4
LT		 12128static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12129{
12130 struct tg3 *tp = netdev_priv(dev);
12dac075 12131 struct device *dp = &tp->pdev->dev;
6aa20a22 12132
1da177e4
LT		 12133 if (wol->wolopts & ~WAKE_MAGIC)
12134 return -EINVAL;
12135 if ((wol->wolopts & WAKE_MAGIC) &&
63c3a66f 12136 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
1da177e4 12137 return -EINVAL;
6aa20a22 12138
f2dc0d18
RW		 12139 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12140
f2dc0d18 12141 if (device_may_wakeup(dp))
63c3a66f 12142 tg3_flag_set(tp, WOL_ENABLE);
f2dc0d18 12143 else
63c3a66f 12144 tg3_flag_clear(tp, WOL_ENABLE);
6aa20a22 12145
1da177e4
LT		 12146 return 0;
12147}
6aa20a22 12148
1da177e4
LT		 12149static u32 tg3_get_msglevel(struct net_device *dev)
12150{
12151 struct tg3 *tp = netdev_priv(dev);
12152 return tp->msg_enable;
12153}
6aa20a22 12154
1da177e4
LT		 12155static void tg3_set_msglevel(struct net_device *dev, u32 value)
12156{
12157 struct tg3 *tp = netdev_priv(dev);
12158 tp->msg_enable = value;
12159}
6aa20a22 12160
1da177e4
LT		 12161static int tg3_nway_reset(struct net_device *dev)
12162{
12163 struct tg3 *tp = netdev_priv(dev);
1da177e4 12164 int r;
6aa20a22 12165
1da177e4
LT		 12166 if (!netif_running(dev))
12167 return -EAGAIN;
12168
f07e9af3 12169 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
c94e3941
MC		 12170 return -EINVAL;
12171
ce20f161
NS		 12172 tg3_warn_mgmt_link_flap(tp);
12173
63c3a66f 12174 if (tg3_flag(tp, USE_PHYLIB)) {
f07e9af3 12175 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12176 return -EAGAIN;
ead2402c 12177 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]);
b02fd9e3
MC		 12178 } else {
12179 u32 bmcr;
12180
12181 spin_lock_bh(&tp->lock);
12182 r = -EINVAL;
12183 tg3_readphy(tp, MII_BMCR, &bmcr);
12184 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12185 ((bmcr & BMCR_ANENABLE) ||
f07e9af3 12186 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
b02fd9e3
MC		 12187 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12188 BMCR_ANENABLE);
12189 r = 0;
12190 }
12191 spin_unlock_bh(&tp->lock);
1da177e4 12192 }
6aa20a22 12193
1da177e4
LT		 12194 return r;
12195}
6aa20a22 12196
1da177e4
LT		 12197static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12198{
12199 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12200
2c49a44d 12201 ering->rx_max_pending = tp->rx_std_ring_mask;
63c3a66f 12202 if (tg3_flag(tp, JUMBO_RING_ENABLE))
2c49a44d 12203 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
4f81c32b
MC		 12204 else
12205 ering->rx_jumbo_max_pending = 0;
12206
12207 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 12208
12209 ering->rx_pending = tp->rx_pending;
63c3a66f 12210 if (tg3_flag(tp, JUMBO_RING_ENABLE))
4f81c32b
MC		 12211 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12212 else
12213 ering->rx_jumbo_pending = 0;
12214
f3f3f27e 12215 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 12216}
6aa20a22 12217
1da177e4
LT		 12218static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12219{
12220 struct tg3 *tp = netdev_priv(dev);
646c9edd 12221 int i, irq_sync = 0, err = 0;
6aa20a22 12222
2c49a44d
MC		 12223 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12224 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
bc3a9254
MC		 12225 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12226 (ering->tx_pending <= MAX_SKB_FRAGS) ||
63c3a66f 12227 (tg3_flag(tp, TSO_BUG) &&
bc3a9254 12228 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 12229 return -EINVAL;
6aa20a22 12230
bbe832c0 12231 if (netif_running(dev)) {
b02fd9e3 12232 tg3_phy_stop(tp);
1da177e4 12233 tg3_netif_stop(tp);
bbe832c0
MC		 12234 irq_sync = 1;
12235 }
1da177e4 12236
bbe832c0 12237 tg3_full_lock(tp, irq_sync);
6aa20a22 12238
1da177e4
LT		 12239 tp->rx_pending = ering->rx_pending;
12240
63c3a66f 12241 if (tg3_flag(tp, MAX_RXPEND_64) &&
1da177e4
LT		 12242 tp->rx_pending > 63)
12243 tp->rx_pending = 63;
12244 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd 12245
6fd45cb8 12246 for (i = 0; i < tp->irq_max; i++)
646c9edd 12247 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 12248
12249 if (netif_running(dev)) {
944d980e 12250 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12251 err = tg3_restart_hw(tp, false);
b9ec6c1b
MC		 12252 if (!err)
12253 tg3_netif_start(tp);
1da177e4
LT		 12254 }
12255
f47c11ee 12256 tg3_full_unlock(tp);
6aa20a22 12257
b02fd9e3
MC		 12258 if (irq_sync && !err)
12259 tg3_phy_start(tp);
12260
b9ec6c1b 12261 return err;
1da177e4 12262}
6aa20a22 12263
1da177e4
LT		 12264static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12265{
12266 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12267
63c3a66f 12268 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
8d018621 12269
4a2db503 12270 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
8d018621
MC		 12271 epause->rx_pause = 1;
12272 else
12273 epause->rx_pause = 0;
12274
4a2db503 12275 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
8d018621
MC		 12276 epause->tx_pause = 1;
12277 else
12278 epause->tx_pause = 0;
1da177e4 12279}
6aa20a22 12280
1da177e4
LT		 12281static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12282{
12283 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 12284 int err = 0;
6aa20a22 12285
ce20f161
NS		 12286 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12287 tg3_warn_mgmt_link_flap(tp);
12288
63c3a66f 12289 if (tg3_flag(tp, USE_PHYLIB)) {
2712168f
MC		 12290 u32 newadv;
12291 struct phy_device *phydev;
1da177e4 12292
ead2402c 12293 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
f47c11ee 12294
2712168f
MC		 12295 if (!(phydev->supported & SUPPORTED_Pause) ||
12296 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
2259dca3 12297 (epause->rx_pause != epause->tx_pause)))
2712168f 12298 return -EINVAL;
1da177e4 12299
2712168f
MC		 12300 tp->link_config.flowctrl = 0;
12301 if (epause->rx_pause) {
12302 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12303
12304 if (epause->tx_pause) {
12305 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12306 newadv = ADVERTISED_Pause;
b02fd9e3 12307 } else
2712168f
MC		 12308 newadv = ADVERTISED_Pause |
12309 ADVERTISED_Asym_Pause;
12310 } else if (epause->tx_pause) {
12311 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12312 newadv = ADVERTISED_Asym_Pause;
12313 } else
12314 newadv = 0;
12315
12316 if (epause->autoneg)
63c3a66f 12317 tg3_flag_set(tp, PAUSE_AUTONEG);
2712168f 12318 else
63c3a66f 12319 tg3_flag_clear(tp, PAUSE_AUTONEG);
2712168f 12320
f07e9af3 12321 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2712168f
MC		 12322 u32 oldadv = phydev->advertising &
12323 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12324 if (oldadv != newadv) {
12325 phydev->advertising &=
12326 ~(ADVERTISED_Pause |
12327 ADVERTISED_Asym_Pause);
12328 phydev->advertising |= newadv;
12329 if (phydev->autoneg) {
12330 /*
12331 * Always renegotiate the link to
12332 * inform our link partner of our
12333 * flow control settings, even if the
12334 * flow control is forced. Let
12335 * tg3_adjust_link() do the final
12336 * flow control setup.
12337 */
12338 return phy_start_aneg(phydev);
b02fd9e3 12339 }
b02fd9e3 12340 }
b02fd9e3 12341
2712168f 12342 if (!epause->autoneg)
b02fd9e3 12343 tg3_setup_flow_control(tp, 0, 0);
2712168f 12344 } else {
c6700ce2 12345 tp->link_config.advertising &=
2712168f
MC		 12346 ~(ADVERTISED_Pause |
12347 ADVERTISED_Asym_Pause);
c6700ce2 12348 tp->link_config.advertising |= newadv;
b02fd9e3
MC		 12349 }
12350 } else {
12351 int irq_sync = 0;
12352
12353 if (netif_running(dev)) {
12354 tg3_netif_stop(tp);
12355 irq_sync = 1;
12356 }
12357
12358 tg3_full_lock(tp, irq_sync);
12359
12360 if (epause->autoneg)
63c3a66f 12361 tg3_flag_set(tp, PAUSE_AUTONEG);
b02fd9e3 12362 else
63c3a66f 12363 tg3_flag_clear(tp, PAUSE_AUTONEG);
b02fd9e3 12364 if (epause->rx_pause)
e18ce346 12365 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 12366 else
e18ce346 12367 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 12368 if (epause->tx_pause)
e18ce346 12369 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 12370 else
e18ce346 12371 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 12372
12373 if (netif_running(dev)) {
12374 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12375 err = tg3_restart_hw(tp, false);
b02fd9e3
MC		 12376 if (!err)
12377 tg3_netif_start(tp);
12378 }
12379
12380 tg3_full_unlock(tp);
12381 }
6aa20a22 12382
fdad8de4
NS		 12383 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12384
b9ec6c1b 12385 return err;
1da177e4 12386}
6aa20a22 12387
de6f31eb 12388static int tg3_get_sset_count(struct net_device *dev, int sset)
1da177e4 12389{
b9f2c044
JG		 12390 switch (sset) {
12391 case ETH_SS_TEST:
12392 return TG3_NUM_TEST;
12393 case ETH_SS_STATS:
12394 return TG3_NUM_STATS;
12395 default:
12396 return -EOPNOTSUPP;
12397 }
4cafd3f5
MC		 12398}
12399
90415477
MC		 12400static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12401 u32 *rules __always_unused)
12402{
12403 struct tg3 *tp = netdev_priv(dev);
12404
12405 if (!tg3_flag(tp, SUPPORT_MSIX))
12406 return -EOPNOTSUPP;
12407
12408 switch (info->cmd) {
12409 case ETHTOOL_GRXRINGS:
12410 if (netif_running(tp->dev))
9102426a 12411 info->data = tp->rxq_cnt;
90415477
MC		 12412 else {
12413 info->data = num_online_cpus();
9102426a
MC		 12414 if (info->data > TG3_RSS_MAX_NUM_QS)
12415 info->data = TG3_RSS_MAX_NUM_QS;
90415477
MC		 12416 }
12417
12418 /* The first interrupt vector only
12419 * handles link interrupts.
12420 */
12421 info->data -= 1;
12422 return 0;
12423
12424 default:
12425 return -EOPNOTSUPP;
12426 }
12427}
12428
12429static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12430{
12431 u32 size = 0;
12432 struct tg3 *tp = netdev_priv(dev);
12433
12434 if (tg3_flag(tp, SUPPORT_MSIX))
12435 size = TG3_RSS_INDIR_TBL_SIZE;
12436
12437 return size;
12438}
12439
12440static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
12441{
12442 struct tg3 *tp = netdev_priv(dev);
12443 int i;
12444
12445 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12446 indir[i] = tp->rss_ind_tbl[i];
12447
12448 return 0;
12449}
12450
12451static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
12452{
12453 struct tg3 *tp = netdev_priv(dev);
12454 size_t i;
12455
12456 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12457 tp->rss_ind_tbl[i] = indir[i];
12458
12459 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12460 return 0;
12461
12462 /* It is legal to write the indirection
12463 * table while the device is running.
12464 */
12465 tg3_full_lock(tp, 0);
12466 tg3_rss_write_indir_tbl(tp);
12467 tg3_full_unlock(tp);
12468
12469 return 0;
12470}
12471
0968169c
MC		 12472static void tg3_get_channels(struct net_device *dev,
12473 struct ethtool_channels *channel)
12474{
12475 struct tg3 *tp = netdev_priv(dev);
12476 u32 deflt_qs = netif_get_num_default_rss_queues();
12477
12478 channel->max_rx = tp->rxq_max;
12479 channel->max_tx = tp->txq_max;
12480
12481 if (netif_running(dev)) {
12482 channel->rx_count = tp->rxq_cnt;
12483 channel->tx_count = tp->txq_cnt;
12484 } else {
12485 if (tp->rxq_req)
12486 channel->rx_count = tp->rxq_req;
12487 else
12488 channel->rx_count = min(deflt_qs, tp->rxq_max);
12489
12490 if (tp->txq_req)
12491 channel->tx_count = tp->txq_req;
12492 else
12493 channel->tx_count = min(deflt_qs, tp->txq_max);
12494 }
12495}
12496
12497static int tg3_set_channels(struct net_device *dev,
12498 struct ethtool_channels *channel)
12499{
12500 struct tg3 *tp = netdev_priv(dev);
12501
12502 if (!tg3_flag(tp, SUPPORT_MSIX))
12503 return -EOPNOTSUPP;
12504
12505 if (channel->rx_count > tp->rxq_max ||
12506 channel->tx_count > tp->txq_max)
12507 return -EINVAL;
12508
12509 tp->rxq_req = channel->rx_count;
12510 tp->txq_req = channel->tx_count;
12511
12512 if (!netif_running(dev))
12513 return 0;
12514
12515 tg3_stop(tp);
12516
f4a46d1f 12517 tg3_carrier_off(tp);
0968169c 12518
be947307 12519 tg3_start(tp, true, false, false);
0968169c
MC		 12520
12521 return 0;
12522}
12523
de6f31eb 12524static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1da177e4
LT		 12525{
12526 switch (stringset) {
12527 case ETH_SS_STATS:
12528 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
12529 break;
4cafd3f5
MC		 12530 case ETH_SS_TEST:
12531 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
12532 break;
1da177e4
LT		 12533 default:
12534 WARN_ON(1); /* we need a WARN() */
12535 break;
12536 }
12537}
12538
81b8709c 12539static int tg3_set_phys_id(struct net_device *dev,
12540 enum ethtool_phys_id_state state)
4009a93d
MC		 12541{
12542 struct tg3 *tp = netdev_priv(dev);
4009a93d
MC		 12543
12544 if (!netif_running(tp->dev))
12545 return -EAGAIN;
12546
81b8709c 12547 switch (state) {
12548 case ETHTOOL_ID_ACTIVE:
fce55922 12549 return 1; /* cycle on/off once per second */
4009a93d 12550
81b8709c 12551 case ETHTOOL_ID_ON:
12552 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12553 LED_CTRL_1000MBPS_ON |
12554 LED_CTRL_100MBPS_ON |
12555 LED_CTRL_10MBPS_ON |
12556 LED_CTRL_TRAFFIC_OVERRIDE |
12557 LED_CTRL_TRAFFIC_BLINK |
12558 LED_CTRL_TRAFFIC_LED);
12559 break;
6aa20a22 12560
81b8709c 12561 case ETHTOOL_ID_OFF:
12562 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12563 LED_CTRL_TRAFFIC_OVERRIDE);
12564 break;
4009a93d 12565
81b8709c 12566 case ETHTOOL_ID_INACTIVE:
12567 tw32(MAC_LED_CTRL, tp->led_ctrl);
12568 break;
4009a93d 12569 }
81b8709c 12570
4009a93d
MC		 12571 return 0;
12572}
12573
de6f31eb 12574static void tg3_get_ethtool_stats(struct net_device *dev,
1da177e4
LT		 12575 struct ethtool_stats *estats, u64 *tmp_stats)
12576{
12577 struct tg3 *tp = netdev_priv(dev);
0e6c9da3 12578
b546e46f
MC		 12579 if (tp->hw_stats)
12580 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12581 else
12582 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
1da177e4
LT		 12583}
12584
535a490e 12585static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
c3e94500
MC		 12586{
12587 int i;
12588 __be32 *buf;
12589 u32 offset = 0, len = 0;
12590 u32 magic, val;
12591
63c3a66f 12592 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
c3e94500
MC		 12593 return NULL;
12594
12595 if (magic == TG3_EEPROM_MAGIC) {
12596 for (offset = TG3_NVM_DIR_START;
12597 offset < TG3_NVM_DIR_END;
12598 offset += TG3_NVM_DIRENT_SIZE) {
12599 if (tg3_nvram_read(tp, offset, &val))
12600 return NULL;
12601
12602 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12603 TG3_NVM_DIRTYPE_EXTVPD)
12604 break;
12605 }
12606
12607 if (offset != TG3_NVM_DIR_END) {
12608 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12609 if (tg3_nvram_read(tp, offset + 4, &offset))
12610 return NULL;
12611
12612 offset = tg3_nvram_logical_addr(tp, offset);
12613 }
12614 }
12615
12616 if (!offset || !len) {
12617 offset = TG3_NVM_VPD_OFF;
12618 len = TG3_NVM_VPD_LEN;
12619 }
12620
12621 buf = kmalloc(len, GFP_KERNEL);
12622 if (buf == NULL)
12623 return NULL;
12624
12625 if (magic == TG3_EEPROM_MAGIC) {
12626 for (i = 0; i < len; i += 4) {
12627 /* The data is in little-endian format in NVRAM.
12628 * Use the big-endian read routines to preserve
12629 * the byte order as it exists in NVRAM.
12630 */
12631 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12632 goto error;
12633 }
12634 } else {
12635 u8 *ptr;
12636 ssize_t cnt;
12637 unsigned int pos = 0;
12638
12639 ptr = (u8 *)&buf[0];
12640 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12641 cnt = pci_read_vpd(tp->pdev, pos,
12642 len - pos, ptr);
12643 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12644 cnt = 0;
12645 else if (cnt < 0)
12646 goto error;
12647 }
12648 if (pos != len)
12649 goto error;
12650 }
12651
535a490e
MC		 12652 *vpdlen = len;
12653
c3e94500
MC		 12654 return buf;
12655
12656error:
12657 kfree(buf);
12658 return NULL;
12659}
12660
566f86ad 12661#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 12662#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12663#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12664#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
727a6d9f
MC		 12665#define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12666#define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
bda18faf 12667#define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
b16250e3
MC		 12668#define NVRAM_SELFBOOT_HW_SIZE 0x20
12669#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 12670
12671static int tg3_test_nvram(struct tg3 *tp)
12672{
535a490e 12673 u32 csum, magic, len;
a9dc529d 12674 __be32 *buf;
ab0049b4 12675 int i, j, k, err = 0, size;
566f86ad 12676
63c3a66f 12677 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 12678 return 0;
12679
e4f34110 12680 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 12681 return -EIO;
12682
1b27777a
MC		 12683 if (magic == TG3_EEPROM_MAGIC)
12684 size = NVRAM_TEST_SIZE;
b16250e3 12685 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 12686 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12687 TG3_EEPROM_SB_FORMAT_1) {
12688 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12689 case TG3_EEPROM_SB_REVISION_0:
12690 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12691 break;
12692 case TG3_EEPROM_SB_REVISION_2:
12693 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12694 break;
12695 case TG3_EEPROM_SB_REVISION_3:
12696 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12697 break;
727a6d9f
MC		 12698 case TG3_EEPROM_SB_REVISION_4:
12699 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12700 break;
12701 case TG3_EEPROM_SB_REVISION_5:
12702 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12703 break;
12704 case TG3_EEPROM_SB_REVISION_6:
12705 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12706 break;
a5767dec 12707 default:
727a6d9f 12708 return -EIO;
a5767dec
MC		 12709 }
12710 } else
1b27777a 12711 return 0;
b16250e3
MC		 12712 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12713 size = NVRAM_SELFBOOT_HW_SIZE;
12714 else
1b27777a
MC		 12715 return -EIO;
12716
12717 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 12718 if (buf == NULL)
12719 return -ENOMEM;
12720
1b27777a
MC		 12721 err = -EIO;
12722 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 12723 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12724 if (err)
566f86ad 12725 break;
566f86ad 12726 }
1b27777a 12727 if (i < size)
566f86ad
MC		 12728 goto out;
12729
1b27777a 12730 /* Selfboot format */
a9dc529d 12731 magic = be32_to_cpu(buf[0]);
b9fc7dc5 12732 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 12733 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 12734 u8 *buf8 = (u8 *) buf, csum8 = 0;
12735
b9fc7dc5 12736 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 12737 TG3_EEPROM_SB_REVISION_2) {
12738 /* For rev 2, the csum doesn't include the MBA. */
12739 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12740 csum8 += buf8[i];
12741 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12742 csum8 += buf8[i];
12743 } else {
12744 for (i = 0; i < size; i++)
12745 csum8 += buf8[i];
12746 }
1b27777a 12747
ad96b485
AB		 12748 if (csum8 == 0) {
12749 err = 0;
12750 goto out;
12751 }
12752
12753 err = -EIO;
12754 goto out;
1b27777a 12755 }
566f86ad 12756
b9fc7dc5 12757 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 12758 TG3_EEPROM_MAGIC_HW) {
12759 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 12760 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 12761 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 12762
12763 /* Separate the parity bits and the data bytes. */
12764 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12765 if ((i == 0) || (i == 8)) {
12766 int l;
12767 u8 msk;
12768
12769 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12770 parity[k++] = buf8[i] & msk;
12771 i++;
859a5887 12772 } else if (i == 16) {
b16250e3
MC		 12773 int l;
12774 u8 msk;
12775
12776 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12777 parity[k++] = buf8[i] & msk;
12778 i++;
12779
12780 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12781 parity[k++] = buf8[i] & msk;
12782 i++;
12783 }
12784 data[j++] = buf8[i];
12785 }
12786
12787 err = -EIO;
12788 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12789 u8 hw8 = hweight8(data[i]);
12790
12791 if ((hw8 & 0x1) && parity[i])
12792 goto out;
12793 else if (!(hw8 & 0x1) && !parity[i])
12794 goto out;
12795 }
12796 err = 0;
12797 goto out;
12798 }
12799
01c3a392
MC		 12800 err = -EIO;
12801
566f86ad
MC		 12802 /* Bootstrap checksum at offset 0x10 */
12803 csum = calc_crc((unsigned char *) buf, 0x10);
01c3a392 12804 if (csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 12805 goto out;
12806
12807 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12808 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
01c3a392 12809 if (csum != le32_to_cpu(buf[0xfc/4]))
a9dc529d 12810 goto out;
566f86ad 12811
c3e94500
MC		 12812 kfree(buf);
12813
535a490e 12814 buf = tg3_vpd_readblock(tp, &len);
c3e94500
MC		 12815 if (!buf)
12816 return -ENOMEM;
d4894f3e 12817
535a490e 12818 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
d4894f3e
MC		 12819 if (i > 0) {
12820 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12821 if (j < 0)
12822 goto out;
12823
535a490e 12824 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
d4894f3e
MC		 12825 goto out;
12826
12827 i += PCI_VPD_LRDT_TAG_SIZE;
12828 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12829 PCI_VPD_RO_KEYWORD_CHKSUM);
12830 if (j > 0) {
12831 u8 csum8 = 0;
12832
12833 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12834
12835 for (i = 0; i <= j; i++)
12836 csum8 += ((u8 *)buf)[i];
12837
12838 if (csum8)
12839 goto out;
12840 }
12841 }
12842
566f86ad
MC		 12843 err = 0;
12844
12845out:
12846 kfree(buf);
12847 return err;
12848}
12849
ca43007a
MC		 12850#define TG3_SERDES_TIMEOUT_SEC 2
12851#define TG3_COPPER_TIMEOUT_SEC 6
12852
12853static int tg3_test_link(struct tg3 *tp)
12854{
12855 int i, max;
12856
12857 if (!netif_running(tp->dev))
12858 return -ENODEV;
12859
f07e9af3 12860 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
ca43007a
MC		 12861 max = TG3_SERDES_TIMEOUT_SEC;
12862 else
12863 max = TG3_COPPER_TIMEOUT_SEC;
12864
12865 for (i = 0; i < max; i++) {
f4a46d1f 12866 if (tp->link_up)
ca43007a
MC		 12867 return 0;
12868
12869 if (msleep_interruptible(1000))
12870 break;
12871 }
12872
12873 return -EIO;
12874}
12875
a71116d1 12876/* Only test the commonly used registers */
30ca3e37 12877static int tg3_test_registers(struct tg3 *tp)
a71116d1 12878{
b16250e3 12879 int i, is_5705, is_5750;
a71116d1
MC		 12880 u32 offset, read_mask, write_mask, val, save_val, read_val;
12881 static struct {
12882 u16 offset;
12883 u16 flags;
12884#define TG3_FL_5705 0x1
12885#define TG3_FL_NOT_5705 0x2
12886#define TG3_FL_NOT_5788 0x4
b16250e3 12887#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 12888 u32 read_mask;
12889 u32 write_mask;
12890 } reg_tbl[] = {
12891 /* MAC Control Registers */
12892 { MAC_MODE, TG3_FL_NOT_5705,
12893 0x00000000, 0x00ef6f8c },
12894 { MAC_MODE, TG3_FL_5705,
12895 0x00000000, 0x01ef6b8c },
12896 { MAC_STATUS, TG3_FL_NOT_5705,
12897 0x03800107, 0x00000000 },
12898 { MAC_STATUS, TG3_FL_5705,
12899 0x03800100, 0x00000000 },
12900 { MAC_ADDR_0_HIGH, 0x0000,
12901 0x00000000, 0x0000ffff },
12902 { MAC_ADDR_0_LOW, 0x0000,
c6cdf436 12903 0x00000000, 0xffffffff },
a71116d1
MC		 12904 { MAC_RX_MTU_SIZE, 0x0000,
12905 0x00000000, 0x0000ffff },
12906 { MAC_TX_MODE, 0x0000,
12907 0x00000000, 0x00000070 },
12908 { MAC_TX_LENGTHS, 0x0000,
12909 0x00000000, 0x00003fff },
12910 { MAC_RX_MODE, TG3_FL_NOT_5705,
12911 0x00000000, 0x000007fc },
12912 { MAC_RX_MODE, TG3_FL_5705,
12913 0x00000000, 0x000007dc },
12914 { MAC_HASH_REG_0, 0x0000,
12915 0x00000000, 0xffffffff },
12916 { MAC_HASH_REG_1, 0x0000,
12917 0x00000000, 0xffffffff },
12918 { MAC_HASH_REG_2, 0x0000,
12919 0x00000000, 0xffffffff },
12920 { MAC_HASH_REG_3, 0x0000,
12921 0x00000000, 0xffffffff },
12922
12923 /* Receive Data and Receive BD Initiator Control Registers. */
12924 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
12925 0x00000000, 0xffffffff },
12926 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
12927 0x00000000, 0xffffffff },
12928 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
12929 0x00000000, 0x00000003 },
12930 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
12931 0x00000000, 0xffffffff },
12932 { RCVDBDI_STD_BD+0, 0x0000,
12933 0x00000000, 0xffffffff },
12934 { RCVDBDI_STD_BD+4, 0x0000,
12935 0x00000000, 0xffffffff },
12936 { RCVDBDI_STD_BD+8, 0x0000,
12937 0x00000000, 0xffff0002 },
12938 { RCVDBDI_STD_BD+0xc, 0x0000,
12939 0x00000000, 0xffffffff },
6aa20a22 12940
a71116d1
MC		 12941 /* Receive BD Initiator Control Registers. */
12942 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
12943 0x00000000, 0xffffffff },
12944 { RCVBDI_STD_THRESH, TG3_FL_5705,
12945 0x00000000, 0x000003ff },
12946 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
12947 0x00000000, 0xffffffff },
6aa20a22 12948
a71116d1
MC		 12949 /* Host Coalescing Control Registers. */
12950 { HOSTCC_MODE, TG3_FL_NOT_5705,
12951 0x00000000, 0x00000004 },
12952 { HOSTCC_MODE, TG3_FL_5705,
12953 0x00000000, 0x000000f6 },
12954 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
12955 0x00000000, 0xffffffff },
12956 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
12957 0x00000000, 0x000003ff },
12958 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
12959 0x00000000, 0xffffffff },
12960 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
12961 0x00000000, 0x000003ff },
12962 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
12963 0x00000000, 0xffffffff },
12964 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12965 0x00000000, 0x000000ff },
12966 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
12967 0x00000000, 0xffffffff },
12968 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12969 0x00000000, 0x000000ff },
12970 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
12971 0x00000000, 0xffffffff },
12972 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
12973 0x00000000, 0xffffffff },
12974 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12975 0x00000000, 0xffffffff },
12976 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12977 0x00000000, 0x000000ff },
12978 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12979 0x00000000, 0xffffffff },
12980 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12981 0x00000000, 0x000000ff },
12982 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
12983 0x00000000, 0xffffffff },
12984 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
12985 0x00000000, 0xffffffff },
12986 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
12987 0x00000000, 0xffffffff },
12988 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
12989 0x00000000, 0xffffffff },
12990 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
12991 0x00000000, 0xffffffff },
12992 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
12993 0xffffffff, 0x00000000 },
12994 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
12995 0xffffffff, 0x00000000 },
12996
12997 /* Buffer Manager Control Registers. */
b16250e3 12998 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 12999 0x00000000, 0x007fff80 },
b16250e3 13000 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 13001 0x00000000, 0x007fffff },
13002 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13003 0x00000000, 0x0000003f },
13004 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13005 0x00000000, 0x000001ff },
13006 { BUFMGR_MB_HIGH_WATER, 0x0000,
13007 0x00000000, 0x000001ff },
13008 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13009 0xffffffff, 0x00000000 },
13010 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13011 0xffffffff, 0x00000000 },
6aa20a22 13012
a71116d1
MC		 13013 /* Mailbox Registers */
13014 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13015 0x00000000, 0x000001ff },
13016 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13017 0x00000000, 0x000001ff },
13018 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13019 0x00000000, 0x000007ff },
13020 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13021 0x00000000, 0x000001ff },
13022
13023 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13024 };
13025
b16250e3 13026 is_5705 = is_5750 = 0;
63c3a66f 13027 if (tg3_flag(tp, 5705_PLUS)) {
a71116d1 13028 is_5705 = 1;
63c3a66f 13029 if (tg3_flag(tp, 5750_PLUS))
b16250e3
MC		 13030 is_5750 = 1;
13031 }
a71116d1
MC		 13032
13033 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13034 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13035 continue;
13036
13037 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13038 continue;
13039
63c3a66f 13040 if (tg3_flag(tp, IS_5788) &&
a71116d1
MC		 13041 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13042 continue;
13043
b16250e3
MC		 13044 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13045 continue;
13046
a71116d1
MC		 13047 offset = (u32) reg_tbl[i].offset;
13048 read_mask = reg_tbl[i].read_mask;
13049 write_mask = reg_tbl[i].write_mask;
13050
13051 /* Save the original register content */
13052 save_val = tr32(offset);
13053
13054 /* Determine the read-only value. */
13055 read_val = save_val & read_mask;
13056
13057 /* Write zero to the register, then make sure the read-only bits
13058 * are not changed and the read/write bits are all zeros.
13059 */
13060 tw32(offset, 0);
13061
13062 val = tr32(offset);
13063
13064 /* Test the read-only and read/write bits. */
13065 if (((val & read_mask) != read_val) || (val & write_mask))
13066 goto out;
13067
13068 /* Write ones to all the bits defined by RdMask and WrMask, then
13069 * make sure the read-only bits are not changed and the
13070 * read/write bits are all ones.
13071 */
13072 tw32(offset, read_mask | write_mask);
13073
13074 val = tr32(offset);
13075
13076 /* Test the read-only bits. */
13077 if ((val & read_mask) != read_val)
13078 goto out;
13079
13080 /* Test the read/write bits. */
13081 if ((val & write_mask) != write_mask)
13082 goto out;
13083
13084 tw32(offset, save_val);
13085 }
13086
13087 return 0;
13088
13089out:
9f88f29f 13090 if (netif_msg_hw(tp))
2445e461
MC		 13091 netdev_err(tp->dev,
13092 "Register test failed at offset %x\n", offset);
a71116d1
MC		 13093 tw32(offset, save_val);
13094 return -EIO;
13095}
13096
7942e1db
MC		 13097static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13098{
f71e1309 13099 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 13100 int i;
13101 u32 j;
13102
e9edda69 13103 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 13104 for (j = 0; j < len; j += 4) {
13105 u32 val;
13106
13107 tg3_write_mem(tp, offset + j, test_pattern[i]);
13108 tg3_read_mem(tp, offset + j, &val);
13109 if (val != test_pattern[i])
13110 return -EIO;
13111 }
13112 }
13113 return 0;
13114}
13115
13116static int tg3_test_memory(struct tg3 *tp)
13117{
13118 static struct mem_entry {
13119 u32 offset;
13120 u32 len;
13121 } mem_tbl_570x[] = {
38690194 13122 { 0x00000000, 0x00b50},
7942e1db
MC		 13123 { 0x00002000, 0x1c000},
13124 { 0xffffffff, 0x00000}
13125 }, mem_tbl_5705[] = {
13126 { 0x00000100, 0x0000c},
13127 { 0x00000200, 0x00008},
7942e1db
MC		 13128 { 0x00004000, 0x00800},
13129 { 0x00006000, 0x01000},
13130 { 0x00008000, 0x02000},
13131 { 0x00010000, 0x0e000},
13132 { 0xffffffff, 0x00000}
79f4d13a
MC		 13133 }, mem_tbl_5755[] = {
13134 { 0x00000200, 0x00008},
13135 { 0x00004000, 0x00800},
13136 { 0x00006000, 0x00800},
13137 { 0x00008000, 0x02000},
13138 { 0x00010000, 0x0c000},
13139 { 0xffffffff, 0x00000}
b16250e3
MC		 13140 }, mem_tbl_5906[] = {
13141 { 0x00000200, 0x00008},
13142 { 0x00004000, 0x00400},
13143 { 0x00006000, 0x00400},
13144 { 0x00008000, 0x01000},
13145 { 0x00010000, 0x01000},
13146 { 0xffffffff, 0x00000}
8b5a6c42
MC		 13147 }, mem_tbl_5717[] = {
13148 { 0x00000200, 0x00008},
13149 { 0x00010000, 0x0a000},
13150 { 0x00020000, 0x13c00},
13151 { 0xffffffff, 0x00000}
13152 }, mem_tbl_57765[] = {
13153 { 0x00000200, 0x00008},
13154 { 0x00004000, 0x00800},
13155 { 0x00006000, 0x09800},
13156 { 0x00010000, 0x0a000},
13157 { 0xffffffff, 0x00000}
7942e1db
MC		 13158 };
13159 struct mem_entry *mem_tbl;
13160 int err = 0;
13161 int i;
13162
63c3a66f 13163 if (tg3_flag(tp, 5717_PLUS))
8b5a6c42 13164 mem_tbl = mem_tbl_5717;
c65a17f4 13165 else if (tg3_flag(tp, 57765_CLASS) ||
4153577a 13166 tg3_asic_rev(tp) == ASIC_REV_5762)
8b5a6c42 13167 mem_tbl = mem_tbl_57765;
63c3a66f 13168 else if (tg3_flag(tp, 5755_PLUS))
321d32a0 13169 mem_tbl = mem_tbl_5755;
4153577a 13170 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
321d32a0 13171 mem_tbl = mem_tbl_5906;
63c3a66f 13172 else if (tg3_flag(tp, 5705_PLUS))
321d32a0
MC		 13173 mem_tbl = mem_tbl_5705;
13174 else
7942e1db
MC		 13175 mem_tbl = mem_tbl_570x;
13176
13177 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
be98da6a
MC		 13178 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13179 if (err)
7942e1db
MC		 13180 break;
13181 }
6aa20a22 13182
7942e1db
MC		 13183 return err;
13184}
13185
bb158d69
MC		 13186#define TG3_TSO_MSS 500
13187
13188#define TG3_TSO_IP_HDR_LEN 20
13189#define TG3_TSO_TCP_HDR_LEN 20
13190#define TG3_TSO_TCP_OPT_LEN 12
13191
13192static const u8 tg3_tso_header[] = {
131930x08, 0x00,
131940x45, 0x00, 0x00, 0x00,
131950x00, 0x00, 0x40, 0x00,
131960x40, 0x06, 0x00, 0x00,
131970x0a, 0x00, 0x00, 0x01,
131980x0a, 0x00, 0x00, 0x02,
131990x0d, 0x00, 0xe0, 0x00,
132000x00, 0x00, 0x01, 0x00,
132010x00, 0x00, 0x02, 0x00,
132020x80, 0x10, 0x10, 0x00,
132030x14, 0x09, 0x00, 0x00,
132040x01, 0x01, 0x08, 0x0a,
132050x11, 0x11, 0x11, 0x11,
132060x11, 0x11, 0x11, 0x11,
13207};
9f40dead 13208
28a45957 13209static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
c76949a6 13210{
5e5a7f37 13211 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
bb158d69 13212 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
84b67b27 13213 u32 budget;
9205fd9c
ED		 13214 struct sk_buff *skb;
13215 u8 *tx_data, *rx_data;
c76949a6
MC		 13216 dma_addr_t map;
13217 int num_pkts, tx_len, rx_len, i, err;
13218 struct tg3_rx_buffer_desc *desc;
898a56f8 13219 struct tg3_napi *tnapi, *rnapi;
8fea32b9 13220 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
c76949a6 13221
c8873405
MC		 13222 tnapi = &tp->napi[0];
13223 rnapi = &tp->napi[0];
0c1d0e2b 13224 if (tp->irq_cnt > 1) {
63c3a66f 13225 if (tg3_flag(tp, ENABLE_RSS))
1da85aa3 13226 rnapi = &tp->napi[1];
63c3a66f 13227 if (tg3_flag(tp, ENABLE_TSS))
c8873405 13228 tnapi = &tp->napi[1];
0c1d0e2b 13229 }
fd2ce37f 13230 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 13231
c76949a6
MC		 13232 err = -EIO;
13233
4852a861 13234 tx_len = pktsz;
a20e9c62 13235 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 13236 if (!skb)
13237 return -ENOMEM;
13238
c76949a6 13239 tx_data = skb_put(skb, tx_len);
d458cdf7
JP		 13240 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13241 memset(tx_data + ETH_ALEN, 0x0, 8);
c76949a6 13242
4852a861 13243 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
c76949a6 13244
28a45957 13245 if (tso_loopback) {
bb158d69
MC		 13246 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13247
13248 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13249 TG3_TSO_TCP_OPT_LEN;
13250
13251 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13252 sizeof(tg3_tso_header));
13253 mss = TG3_TSO_MSS;
13254
13255 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13256 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13257
13258 /* Set the total length field in the IP header */
13259 iph->tot_len = htons((u16)(mss + hdr_len));
13260
13261 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13262 TXD_FLAG_CPU_POST_DMA);
13263
63c3a66f
JP		 13264 if (tg3_flag(tp, HW_TSO_1) ||
13265 tg3_flag(tp, HW_TSO_2) ||
13266 tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13267 struct tcphdr *th;
13268 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13269 th = (struct tcphdr *)&tx_data[val];
13270 th->check = 0;
13271 } else
13272 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13273
63c3a66f 13274 if (tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13275 mss |= (hdr_len & 0xc) << 12;
13276 if (hdr_len & 0x10)
13277 base_flags |= 0x00000010;
13278 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 13279 } else if (tg3_flag(tp, HW_TSO_2))
bb158d69 13280 mss |= hdr_len << 9;
63c3a66f 13281 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 13282 tg3_asic_rev(tp) == ASIC_REV_5705) {
bb158d69
MC		 13283 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13284 } else {
13285 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13286 }
13287
13288 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13289 } else {
13290 num_pkts = 1;
13291 data_off = ETH_HLEN;
c441b456
MC		 13292
13293 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13294 tx_len > VLAN_ETH_FRAME_LEN)
13295 base_flags |= TXD_FLAG_JMB_PKT;
bb158d69
MC		 13296 }
13297
13298 for (i = data_off; i < tx_len; i++)
c76949a6
MC		 13299 tx_data[i] = (u8) (i & 0xff);
13300
f4188d8a
AD		 13301 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13302 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 13303 dev_kfree_skb(skb);
13304 return -EIO;
13305 }
c76949a6 13306
0d681b27
MC		 13307 val = tnapi->tx_prod;
13308 tnapi->tx_buffers[val].skb = skb;
13309 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13310
c76949a6 13311 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13312 rnapi->coal_now);
c76949a6
MC		 13313
13314 udelay(10);
13315
898a56f8 13316 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 13317
84b67b27
MC		 13318 budget = tg3_tx_avail(tnapi);
13319 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
d1a3b737
MC		 13320 base_flags | TXD_FLAG_END, mss, 0)) {
13321 tnapi->tx_buffers[val].skb = NULL;
13322 dev_kfree_skb(skb);
13323 return -EIO;
13324 }
c76949a6 13325
f3f3f27e 13326 tnapi->tx_prod++;
c76949a6 13327
6541b806
MC		 13328 /* Sync BD data before updating mailbox */
13329 wmb();
13330
f3f3f27e
MC		 13331 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13332 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 13333
13334 udelay(10);
13335
303fc921
MC		 13336 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13337 for (i = 0; i < 35; i++) {
c76949a6 13338 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13339 coal_now);
c76949a6
MC		 13340
13341 udelay(10);
13342
898a56f8
MC		 13343 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13344 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 13345 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 13346 (rx_idx == (rx_start_idx + num_pkts)))
13347 break;
13348 }
13349
ba1142e4 13350 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
c76949a6
MC		 13351 dev_kfree_skb(skb);
13352
f3f3f27e 13353 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 13354 goto out;
13355
13356 if (rx_idx != rx_start_idx + num_pkts)
13357 goto out;
13358
bb158d69
MC		 13359 val = data_off;
13360 while (rx_idx != rx_start_idx) {
13361 desc = &rnapi->rx_rcb[rx_start_idx++];
13362 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13363 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
c76949a6 13364
bb158d69
MC		 13365 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13366 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13367 goto out;
c76949a6 13368
bb158d69
MC		 13369 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13370 - ETH_FCS_LEN;
c76949a6 13371
28a45957 13372 if (!tso_loopback) {
bb158d69
MC		 13373 if (rx_len != tx_len)
13374 goto out;
4852a861 13375
bb158d69
MC		 13376 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13377 if (opaque_key != RXD_OPAQUE_RING_STD)
13378 goto out;
13379 } else {
13380 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13381 goto out;
13382 }
13383 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13384 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
54e0a67f 13385 >> RXD_TCPCSUM_SHIFT != 0xffff) {
4852a861 13386 goto out;
bb158d69 13387 }
4852a861 13388
bb158d69 13389 if (opaque_key == RXD_OPAQUE_RING_STD) {
9205fd9c 13390 rx_data = tpr->rx_std_buffers[desc_idx].data;
bb158d69
MC		 13391 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13392 mapping);
13393 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
9205fd9c 13394 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
bb158d69
MC		 13395 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13396 mapping);
13397 } else
13398 goto out;
c76949a6 13399
bb158d69
MC		 13400 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13401 PCI_DMA_FROMDEVICE);
c76949a6 13402
9205fd9c 13403 rx_data += TG3_RX_OFFSET(tp);
bb158d69 13404 for (i = data_off; i < rx_len; i++, val++) {
9205fd9c 13405 if (*(rx_data + i) != (u8) (val & 0xff))
bb158d69
MC		 13406 goto out;
13407 }
c76949a6 13408 }
bb158d69 13409
c76949a6 13410 err = 0;
6aa20a22 13411
9205fd9c 13412 /* tg3_free_rings will unmap and free the rx_data */
c76949a6
MC		 13413out:
13414 return err;
13415}
13416
00c266b7
MC		 13417#define TG3_STD_LOOPBACK_FAILED 1
13418#define TG3_JMB_LOOPBACK_FAILED 2
bb158d69 13419#define TG3_TSO_LOOPBACK_FAILED 4
28a45957
MC		 13420#define TG3_LOOPBACK_FAILED \
13421 (TG3_STD_LOOPBACK_FAILED | \
13422 TG3_JMB_LOOPBACK_FAILED | \
13423 TG3_TSO_LOOPBACK_FAILED)
00c266b7 13424
941ec90f 13425static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
9f40dead 13426{
28a45957 13427 int err = -EIO;
2215e24c 13428 u32 eee_cap;
c441b456
MC		 13429 u32 jmb_pkt_sz = 9000;
13430
13431 if (tp->dma_limit)
13432 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
9f40dead 13433
ab789046
MC		 13434 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13435 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13436
28a45957 13437 if (!netif_running(tp->dev)) {
93df8b8f
NNS		 13438 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13439 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13440 if (do_extlpbk)
93df8b8f 13441 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
28a45957
MC		 13442 goto done;
13443 }
13444
953c96e0 13445 err = tg3_reset_hw(tp, true);
ab789046 13446 if (err) {
93df8b8f
NNS		 13447 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13448 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13449 if (do_extlpbk)
93df8b8f 13450 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
ab789046
MC		 13451 goto done;
13452 }
9f40dead 13453
63c3a66f 13454 if (tg3_flag(tp, ENABLE_RSS)) {
4a85f098
MC		 13455 int i;
13456
13457 /* Reroute all rx packets to the 1st queue */
13458 for (i = MAC_RSS_INDIR_TBL_0;
13459 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13460 tw32(i, 0x0);
13461 }
13462
6e01b20b
MC		 13463 /* HW errata - mac loopback fails in some cases on 5780.
13464 * Normal traffic and PHY loopback are not affected by
13465 * errata. Also, the MAC loopback test is deprecated for
13466 * all newer ASIC revisions.
13467 */
4153577a 13468 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
6e01b20b
MC		 13469 !tg3_flag(tp, CPMU_PRESENT)) {
13470 tg3_mac_loopback(tp, true);
9936bcf6 13471
28a45957 13472 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13473 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
6e01b20b
MC		 13474
13475 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13476 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13477 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
6e01b20b
MC		 13478
13479 tg3_mac_loopback(tp, false);
13480 }
4852a861 13481
f07e9af3 13482 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
63c3a66f 13483 !tg3_flag(tp, USE_PHYLIB)) {
5e5a7f37
MC		 13484 int i;
13485
941ec90f 13486 tg3_phy_lpbk_set(tp, 0, false);
5e5a7f37
MC		 13487
13488 /* Wait for link */
13489 for (i = 0; i < 100; i++) {
13490 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13491 break;
13492 mdelay(1);
13493 }
13494
28a45957 13495 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13496 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
63c3a66f 13497 if (tg3_flag(tp, TSO_CAPABLE) &&
28a45957 13498 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f 13499 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
63c3a66f 13500 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13501 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13502 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
9f40dead 13503
941ec90f
MC		 13504 if (do_extlpbk) {
13505 tg3_phy_lpbk_set(tp, 0, true);
13506
13507 /* All link indications report up, but the hardware
13508 * isn't really ready for about 20 msec. Double it
13509 * to be sure.
13510 */
13511 mdelay(40);
13512
13513 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f
NNS		 13514 data[TG3_EXT_LOOPB_TEST] |=
13515 TG3_STD_LOOPBACK_FAILED;
941ec90f
MC		 13516 if (tg3_flag(tp, TSO_CAPABLE) &&
13517 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f
NNS		 13518 data[TG3_EXT_LOOPB_TEST] |=
13519 TG3_TSO_LOOPBACK_FAILED;
941ec90f 13520 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13521 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f
NNS		 13522 data[TG3_EXT_LOOPB_TEST] |=
13523 TG3_JMB_LOOPBACK_FAILED;
941ec90f
MC		 13524 }
13525
5e5a7f37
MC		 13526 /* Re-enable gphy autopowerdown. */
13527 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13528 tg3_phy_toggle_apd(tp, true);
13529 }
6833c043 13530
93df8b8f
NNS		 13531 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13532 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
28a45957 13533
ab789046
MC		 13534done:
13535 tp->phy_flags |= eee_cap;
13536
9f40dead
MC		 13537 return err;
13538}
13539
4cafd3f5
MC		 13540static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13541 u64 *data)
13542{
566f86ad 13543 struct tg3 *tp = netdev_priv(dev);
941ec90f 13544 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
566f86ad 13545
2e460fc0
NS		 13546 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13547 if (tg3_power_up(tp)) {
13548 etest->flags |= ETH_TEST_FL_FAILED;
13549 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13550 return;
13551 }
13552 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
bed9829f 13553 }
bc1c7567 13554
566f86ad
MC		 13555 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13556
13557 if (tg3_test_nvram(tp) != 0) {
13558 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13559 data[TG3_NVRAM_TEST] = 1;
566f86ad 13560 }
941ec90f 13561 if (!doextlpbk && tg3_test_link(tp)) {
ca43007a 13562 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13563 data[TG3_LINK_TEST] = 1;
ca43007a 13564 }
a71116d1 13565 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 13566 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 13567
13568 if (netif_running(dev)) {
b02fd9e3 13569 tg3_phy_stop(tp);
a71116d1 13570 tg3_netif_stop(tp);
bbe832c0
MC		 13571 irq_sync = 1;
13572 }
a71116d1 13573
bbe832c0 13574 tg3_full_lock(tp, irq_sync);
a71116d1 13575 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 13576 err = tg3_nvram_lock(tp);
a71116d1 13577 tg3_halt_cpu(tp, RX_CPU_BASE);
63c3a66f 13578 if (!tg3_flag(tp, 5705_PLUS))
a71116d1 13579 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 13580 if (!err)
13581 tg3_nvram_unlock(tp);
a71116d1 13582
f07e9af3 13583 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
d9ab5ad1
MC		 13584 tg3_phy_reset(tp);
13585
a71116d1
MC		 13586 if (tg3_test_registers(tp) != 0) {
13587 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13588 data[TG3_REGISTER_TEST] = 1;
a71116d1 13589 }
28a45957 13590
7942e1db
MC		 13591 if (tg3_test_memory(tp) != 0) {
13592 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13593 data[TG3_MEMORY_TEST] = 1;
7942e1db 13594 }
28a45957 13595
941ec90f
MC		 13596 if (doextlpbk)
13597 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13598
93df8b8f 13599 if (tg3_test_loopback(tp, data, doextlpbk))
c76949a6 13600 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 13601
f47c11ee
DM		 13602 tg3_full_unlock(tp);
13603
d4bc3927
MC		 13604 if (tg3_test_interrupt(tp) != 0) {
13605 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13606 data[TG3_INTERRUPT_TEST] = 1;
d4bc3927 13607 }
f47c11ee
DM		 13608
13609 tg3_full_lock(tp, 0);
d4bc3927 13610
a71116d1
MC		 13611 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13612 if (netif_running(dev)) {
63c3a66f 13613 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 13614 err2 = tg3_restart_hw(tp, true);
b02fd9e3 13615 if (!err2)
b9ec6c1b 13616 tg3_netif_start(tp);
a71116d1 13617 }
f47c11ee
DM		 13618
13619 tg3_full_unlock(tp);
b02fd9e3
MC		 13620
13621 if (irq_sync && !err2)
13622 tg3_phy_start(tp);
a71116d1 13623 }
80096068 13624 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
5137a2ee 13625 tg3_power_down_prepare(tp);
bc1c7567 13626
4cafd3f5
MC		 13627}
13628
7260899b 13629static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
0a633ac2
MC		 13630{
13631 struct tg3 *tp = netdev_priv(dev);
13632 struct hwtstamp_config stmpconf;
13633
13634 if (!tg3_flag(tp, PTP_CAPABLE))
7260899b 13635 return -EOPNOTSUPP;
0a633ac2
MC		 13636
13637 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13638 return -EFAULT;
13639
13640 if (stmpconf.flags)
13641 return -EINVAL;
13642
58b187c6
BH		 13643 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13644 stmpconf.tx_type != HWTSTAMP_TX_OFF)
0a633ac2 13645 return -ERANGE;
0a633ac2
MC		 13646
13647 switch (stmpconf.rx_filter) {
13648 case HWTSTAMP_FILTER_NONE:
13649 tp->rxptpctl = 0;
13650 break;
13651 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13652 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13653 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13654 break;
13655 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13656 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13657 TG3_RX_PTP_CTL_SYNC_EVNT;
13658 break;
13659 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13660 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13661 TG3_RX_PTP_CTL_DELAY_REQ;
13662 break;
13663 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13664 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13665 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13666 break;
13667 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13668 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13669 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13670 break;
13671 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13672 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13673 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13674 break;
13675 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13676 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13677 TG3_RX_PTP_CTL_SYNC_EVNT;
13678 break;
13679 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13680 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13681 TG3_RX_PTP_CTL_SYNC_EVNT;
13682 break;
13683 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13684 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13685 TG3_RX_PTP_CTL_SYNC_EVNT;
13686 break;
13687 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13688 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13689 TG3_RX_PTP_CTL_DELAY_REQ;
13690 break;
13691 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13692 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13693 TG3_RX_PTP_CTL_DELAY_REQ;
13694 break;
13695 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13696 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13697 TG3_RX_PTP_CTL_DELAY_REQ;
13698 break;
13699 default:
13700 return -ERANGE;
13701 }
13702
13703 if (netif_running(dev) && tp->rxptpctl)
13704 tw32(TG3_RX_PTP_CTL,
13705 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13706
58b187c6
BH		 13707 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13708 tg3_flag_set(tp, TX_TSTAMP_EN);
13709 else
13710 tg3_flag_clear(tp, TX_TSTAMP_EN);
13711
0a633ac2
MC		 13712 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13713 -EFAULT : 0;
13714}
13715
7260899b
BH		 13716static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13717{
13718 struct tg3 *tp = netdev_priv(dev);
13719 struct hwtstamp_config stmpconf;
13720
13721 if (!tg3_flag(tp, PTP_CAPABLE))
13722 return -EOPNOTSUPP;
13723
13724 stmpconf.flags = 0;
13725 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13726 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13727
13728 switch (tp->rxptpctl) {
13729 case 0:
13730 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13731 break;
13732 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13733 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13734 break;
13735 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13736 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13737 break;
13738 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13739 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13740 break;
13741 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13742 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13743 break;
13744 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13745 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13746 break;
13747 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13748 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13749 break;
13750 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13751 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13752 break;
13753 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13754 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13755 break;
13756 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13757 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13758 break;
13759 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13760 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13761 break;
13762 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13763 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13764 break;
13765 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13766 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13767 break;
13768 default:
13769 WARN_ON_ONCE(1);
13770 return -ERANGE;
13771 }
13772
13773 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13774 -EFAULT : 0;
13775}
13776
1da177e4
LT		 13777static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13778{
13779 struct mii_ioctl_data *data = if_mii(ifr);
13780 struct tg3 *tp = netdev_priv(dev);
13781 int err;
13782
63c3a66f 13783 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 13784 struct phy_device *phydev;
f07e9af3 13785 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 13786 return -EAGAIN;
ead2402c 13787 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
28b04113 13788 return phy_mii_ioctl(phydev, ifr, cmd);
b02fd9e3
MC		 13789 }
13790
33f401ae 13791 switch (cmd) {
1da177e4 13792 case SIOCGMIIPHY:
882e9793 13793 data->phy_id = tp->phy_addr;
1da177e4
LT		 13794
13795 /* fallthru */
13796 case SIOCGMIIREG: {
13797 u32 mii_regval;
13798
f07e9af3 13799 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13800 break; /* We have no PHY */
13801
34eea5ac 13802 if (!netif_running(dev))
bc1c7567
MC		 13803 return -EAGAIN;
13804
f47c11ee 13805 spin_lock_bh(&tp->lock);
5c358045
HM		 13806 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13807 data->reg_num & 0x1f, &mii_regval);
f47c11ee 13808 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13809
13810 data->val_out = mii_regval;
13811
13812 return err;
13813 }
13814
13815 case SIOCSMIIREG:
f07e9af3 13816 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13817 break; /* We have no PHY */
13818
34eea5ac 13819 if (!netif_running(dev))
bc1c7567
MC		 13820 return -EAGAIN;
13821
f47c11ee 13822 spin_lock_bh(&tp->lock);
5c358045
HM		 13823 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13824 data->reg_num & 0x1f, data->val_in);
f47c11ee 13825 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13826
13827 return err;
13828
0a633ac2 13829 case SIOCSHWTSTAMP:
7260899b
BH		 13830 return tg3_hwtstamp_set(dev, ifr);
13831
13832 case SIOCGHWTSTAMP:
13833 return tg3_hwtstamp_get(dev, ifr);
0a633ac2 13834
1da177e4
LT		 13835 default:
13836 /* do nothing */
13837 break;
13838 }
13839 return -EOPNOTSUPP;
13840}
13841
15f9850d
DM		 13842static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13843{
13844 struct tg3 *tp = netdev_priv(dev);
13845
13846 memcpy(ec, &tp->coal, sizeof(*ec));
13847 return 0;
13848}
13849
d244c892
MC		 13850static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13851{
13852 struct tg3 *tp = netdev_priv(dev);
13853 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13854 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13855
63c3a66f 13856 if (!tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 13857 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13858 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13859 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13860 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13861 }
13862
13863 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13864 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13865 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13866 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13867 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13868 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13869 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13870 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13871 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13872 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13873 return -EINVAL;
13874
13875 /* No rx interrupts will be generated if both are zero */
13876 if ((ec->rx_coalesce_usecs == 0) &&
13877 (ec->rx_max_coalesced_frames == 0))
13878 return -EINVAL;
13879
13880 /* No tx interrupts will be generated if both are zero */
13881 if ((ec->tx_coalesce_usecs == 0) &&
13882 (ec->tx_max_coalesced_frames == 0))
13883 return -EINVAL;
13884
13885 /* Only copy relevant parameters, ignore all others. */
13886 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
13887 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
13888 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
13889 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
13890 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
13891 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
13892 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
13893 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
13894 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
13895
13896 if (netif_running(dev)) {
13897 tg3_full_lock(tp, 0);
13898 __tg3_set_coalesce(tp, &tp->coal);
13899 tg3_full_unlock(tp);
13900 }
13901 return 0;
13902}
13903
1cbf9eb8
NS		 13904static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
13905{
13906 struct tg3 *tp = netdev_priv(dev);
13907
13908 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13909 netdev_warn(tp->dev, "Board does not support EEE!\n");
13910 return -EOPNOTSUPP;
13911 }
13912
13913 if (edata->advertised != tp->eee.advertised) {
13914 netdev_warn(tp->dev,
13915 "Direct manipulation of EEE advertisement is not supported\n");
13916 return -EINVAL;
13917 }
13918
13919 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
13920 netdev_warn(tp->dev,
13921 "Maximal Tx Lpi timer supported is %#x(u)\n",
13922 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
13923 return -EINVAL;
13924 }
13925
13926 tp->eee = *edata;
13927
13928 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
13929 tg3_warn_mgmt_link_flap(tp);
13930
13931 if (netif_running(tp->dev)) {
13932 tg3_full_lock(tp, 0);
13933 tg3_setup_eee(tp);
13934 tg3_phy_reset(tp);
13935 tg3_full_unlock(tp);
13936 }
13937
13938 return 0;
13939}
13940
13941static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
13942{
13943 struct tg3 *tp = netdev_priv(dev);
13944
13945 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13946 netdev_warn(tp->dev,
13947 "Board does not support EEE!\n");
13948 return -EOPNOTSUPP;
13949 }
13950
13951 *edata = tp->eee;
13952 return 0;
13953}
13954
7282d491 13955static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 13956 .get_settings = tg3_get_settings,
13957 .set_settings = tg3_set_settings,
13958 .get_drvinfo = tg3_get_drvinfo,
13959 .get_regs_len = tg3_get_regs_len,
13960 .get_regs = tg3_get_regs,
13961 .get_wol = tg3_get_wol,
13962 .set_wol = tg3_set_wol,
13963 .get_msglevel = tg3_get_msglevel,
13964 .set_msglevel = tg3_set_msglevel,
13965 .nway_reset = tg3_nway_reset,
13966 .get_link = ethtool_op_get_link,
13967 .get_eeprom_len = tg3_get_eeprom_len,
13968 .get_eeprom = tg3_get_eeprom,
13969 .set_eeprom = tg3_set_eeprom,
13970 .get_ringparam = tg3_get_ringparam,
13971 .set_ringparam = tg3_set_ringparam,
13972 .get_pauseparam = tg3_get_pauseparam,
13973 .set_pauseparam = tg3_set_pauseparam,
4cafd3f5 13974 .self_test = tg3_self_test,
1da177e4 13975 .get_strings = tg3_get_strings,
81b8709c 13976 .set_phys_id = tg3_set_phys_id,
1da177e4 13977 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 13978 .get_coalesce = tg3_get_coalesce,
d244c892 13979 .set_coalesce = tg3_set_coalesce,
b9f2c044 13980 .get_sset_count = tg3_get_sset_count,
90415477
MC		 13981 .get_rxnfc = tg3_get_rxnfc,
13982 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
13983 .get_rxfh_indir = tg3_get_rxfh_indir,
13984 .set_rxfh_indir = tg3_set_rxfh_indir,
0968169c
MC		 13985 .get_channels = tg3_get_channels,
13986 .set_channels = tg3_set_channels,
7d41e49a 13987 .get_ts_info = tg3_get_ts_info,
1cbf9eb8
NS		 13988 .get_eee = tg3_get_eee,
13989 .set_eee = tg3_set_eee,
1da177e4
LT		 13990};
13991
b4017c53
DM		 13992static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
13993 struct rtnl_link_stats64 *stats)
13994{
13995 struct tg3 *tp = netdev_priv(dev);
13996
0f566b20
MC		 13997 spin_lock_bh(&tp->lock);
13998 if (!tp->hw_stats) {
13999 spin_unlock_bh(&tp->lock);
b4017c53 14000 return &tp->net_stats_prev;
0f566b20 14001 }
b4017c53 14002
b4017c53
DM		 14003 tg3_get_nstats(tp, stats);
14004 spin_unlock_bh(&tp->lock);
14005
14006 return stats;
14007}
14008
ccd5ba9d
MC		 14009static void tg3_set_rx_mode(struct net_device *dev)
14010{
14011 struct tg3 *tp = netdev_priv(dev);
14012
14013 if (!netif_running(dev))
14014 return;
14015
14016 tg3_full_lock(tp, 0);
14017 __tg3_set_rx_mode(dev);
14018 tg3_full_unlock(tp);
14019}
14020
faf1627a
MC		 14021static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14022 int new_mtu)
14023{
14024 dev->mtu = new_mtu;
14025
14026 if (new_mtu > ETH_DATA_LEN) {
14027 if (tg3_flag(tp, 5780_CLASS)) {
14028 netdev_update_features(dev);
14029 tg3_flag_clear(tp, TSO_CAPABLE);
14030 } else {
14031 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14032 }
14033 } else {
14034 if (tg3_flag(tp, 5780_CLASS)) {
14035 tg3_flag_set(tp, TSO_CAPABLE);
14036 netdev_update_features(dev);
14037 }
14038 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14039 }
14040}
14041
14042static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14043{
14044 struct tg3 *tp = netdev_priv(dev);
953c96e0
JP		 14045 int err;
14046 bool reset_phy = false;
faf1627a
MC		 14047
14048 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
14049 return -EINVAL;
14050
14051 if (!netif_running(dev)) {
14052 /* We'll just catch it later when the
14053 * device is up'd.
14054 */
14055 tg3_set_mtu(dev, tp, new_mtu);
14056 return 0;
14057 }
14058
14059 tg3_phy_stop(tp);
14060
14061 tg3_netif_stop(tp);
14062
14063 tg3_full_lock(tp, 1);
14064
14065 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14066
14067 tg3_set_mtu(dev, tp, new_mtu);
14068
2fae5e36
MC		 14069 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14070 * breaks all requests to 256 bytes.
14071 */
4153577a 14072 if (tg3_asic_rev(tp) == ASIC_REV_57766)
953c96e0 14073 reset_phy = true;
2fae5e36
MC		 14074
14075 err = tg3_restart_hw(tp, reset_phy);
faf1627a
MC		 14076
14077 if (!err)
14078 tg3_netif_start(tp);
14079
14080 tg3_full_unlock(tp);
14081
14082 if (!err)
14083 tg3_phy_start(tp);
14084
14085 return err;
14086}
14087
14088static const struct net_device_ops tg3_netdev_ops = {
14089 .ndo_open = tg3_open,
14090 .ndo_stop = tg3_close,
14091 .ndo_start_xmit = tg3_start_xmit,
14092 .ndo_get_stats64 = tg3_get_stats64,
14093 .ndo_validate_addr = eth_validate_addr,
14094 .ndo_set_rx_mode = tg3_set_rx_mode,
14095 .ndo_set_mac_address = tg3_set_mac_addr,
14096 .ndo_do_ioctl = tg3_ioctl,
14097 .ndo_tx_timeout = tg3_tx_timeout,
14098 .ndo_change_mtu = tg3_change_mtu,
14099 .ndo_fix_features = tg3_fix_features,
14100 .ndo_set_features = tg3_set_features,
14101#ifdef CONFIG_NET_POLL_CONTROLLER
14102 .ndo_poll_controller = tg3_poll_controller,
14103#endif
14104};
14105
229b1ad1 14106static void tg3_get_eeprom_size(struct tg3 *tp)
1da177e4 14107{
1b27777a 14108 u32 cursize, val, magic;
1da177e4
LT		 14109
14110 tp->nvram_size = EEPROM_CHIP_SIZE;
14111
e4f34110 14112 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 14113 return;
14114
b16250e3
MC		 14115 if ((magic != TG3_EEPROM_MAGIC) &&
14116 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14117 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 14118 return;
14119
14120 /*
14121 * Size the chip by reading offsets at increasing powers of two.
14122 * When we encounter our validation signature, we know the addressing
14123 * has wrapped around, and thus have our chip size.
14124 */
1b27777a 14125 cursize = 0x10;
1da177e4
LT		 14126
14127 while (cursize < tp->nvram_size) {
e4f34110 14128 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 14129 return;
14130
1820180b 14131 if (val == magic)
1da177e4
LT		 14132 break;
14133
14134 cursize <<= 1;
14135 }
14136
14137 tp->nvram_size = cursize;
14138}
6aa20a22 14139
229b1ad1 14140static void tg3_get_nvram_size(struct tg3 *tp)
1da177e4
LT		 14141{
14142 u32 val;
14143
63c3a66f 14144 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 14145 return;
14146
14147 /* Selfboot format */
1820180b 14148 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 14149 tg3_get_eeprom_size(tp);
14150 return;
14151 }
14152
6d348f2c 14153 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 14154 if (val != 0) {
6d348f2c
MC		 14155 /* This is confusing. We want to operate on the
14156 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14157 * call will read from NVRAM and byteswap the data
14158 * according to the byteswapping settings for all
14159 * other register accesses. This ensures the data we
14160 * want will always reside in the lower 16-bits.
14161 * However, the data in NVRAM is in LE format, which
14162 * means the data from the NVRAM read will always be
14163 * opposite the endianness of the CPU. The 16-bit
14164 * byteswap then brings the data to CPU endianness.
14165 */
14166 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 14167 return;
14168 }
14169 }
fd1122a2 14170 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 14171}
14172
229b1ad1 14173static void tg3_get_nvram_info(struct tg3 *tp)
1da177e4
LT		 14174{
14175 u32 nvcfg1;
14176
14177 nvcfg1 = tr32(NVRAM_CFG1);
14178 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
63c3a66f 14179 tg3_flag_set(tp, FLASH);
8590a603 14180 } else {
1da177e4
LT		 14181 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14182 tw32(NVRAM_CFG1, nvcfg1);
14183 }
14184
4153577a 14185 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
63c3a66f 14186 tg3_flag(tp, 5780_CLASS)) {
1da177e4 14187 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 14188 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14189 tp->nvram_jedecnum = JEDEC_ATMEL;
14190 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14191 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14192 break;
14193 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14194 tp->nvram_jedecnum = JEDEC_ATMEL;
14195 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14196 break;
14197 case FLASH_VENDOR_ATMEL_EEPROM:
14198 tp->nvram_jedecnum = JEDEC_ATMEL;
14199 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
63c3a66f 14200 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14201 break;
14202 case FLASH_VENDOR_ST:
14203 tp->nvram_jedecnum = JEDEC_ST;
14204 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
63c3a66f 14205 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14206 break;
14207 case FLASH_VENDOR_SAIFUN:
14208 tp->nvram_jedecnum = JEDEC_SAIFUN;
14209 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14210 break;
14211 case FLASH_VENDOR_SST_SMALL:
14212 case FLASH_VENDOR_SST_LARGE:
14213 tp->nvram_jedecnum = JEDEC_SST;
14214 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14215 break;
1da177e4 14216 }
8590a603 14217 } else {
1da177e4
LT		 14218 tp->nvram_jedecnum = JEDEC_ATMEL;
14219 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14220 tg3_flag_set(tp, NVRAM_BUFFERED);
1da177e4
LT		 14221 }
14222}
14223
229b1ad1 14224static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
a1b950d5
MC		 14225{
14226 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14227 case FLASH_5752PAGE_SIZE_256:
14228 tp->nvram_pagesize = 256;
14229 break;
14230 case FLASH_5752PAGE_SIZE_512:
14231 tp->nvram_pagesize = 512;
14232 break;
14233 case FLASH_5752PAGE_SIZE_1K:
14234 tp->nvram_pagesize = 1024;
14235 break;
14236 case FLASH_5752PAGE_SIZE_2K:
14237 tp->nvram_pagesize = 2048;
14238 break;
14239 case FLASH_5752PAGE_SIZE_4K:
14240 tp->nvram_pagesize = 4096;
14241 break;
14242 case FLASH_5752PAGE_SIZE_264:
14243 tp->nvram_pagesize = 264;
14244 break;
14245 case FLASH_5752PAGE_SIZE_528:
14246 tp->nvram_pagesize = 528;
14247 break;
14248 }
14249}
14250
229b1ad1 14251static void tg3_get_5752_nvram_info(struct tg3 *tp)
361b4ac2
MC		 14252{
14253 u32 nvcfg1;
14254
14255 nvcfg1 = tr32(NVRAM_CFG1);
14256
e6af301b
MC		 14257 /* NVRAM protection for TPM */
14258 if (nvcfg1 & (1 << 27))
63c3a66f 14259 tg3_flag_set(tp, PROTECTED_NVRAM);
e6af301b 14260
361b4ac2 14261 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14262 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14263 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14264 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14265 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14266 break;
14267 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14268 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14269 tg3_flag_set(tp, NVRAM_BUFFERED);
14270 tg3_flag_set(tp, FLASH);
8590a603
MC		 14271 break;
14272 case FLASH_5752VENDOR_ST_M45PE10:
14273 case FLASH_5752VENDOR_ST_M45PE20:
14274 case FLASH_5752VENDOR_ST_M45PE40:
14275 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14276 tg3_flag_set(tp, NVRAM_BUFFERED);
14277 tg3_flag_set(tp, FLASH);
8590a603 14278 break;
361b4ac2
MC		 14279 }
14280
63c3a66f 14281 if (tg3_flag(tp, FLASH)) {
a1b950d5 14282 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 14283 } else {
361b4ac2
MC		 14284 /* For eeprom, set pagesize to maximum eeprom size */
14285 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14286
14287 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14288 tw32(NVRAM_CFG1, nvcfg1);
14289 }
14290}
14291
229b1ad1 14292static void tg3_get_5755_nvram_info(struct tg3 *tp)
d3c7b886 14293{
989a9d23 14294 u32 nvcfg1, protect = 0;
d3c7b886
MC		 14295
14296 nvcfg1 = tr32(NVRAM_CFG1);
14297
14298 /* NVRAM protection for TPM */
989a9d23 14299 if (nvcfg1 & (1 << 27)) {
63c3a66f 14300 tg3_flag_set(tp, PROTECTED_NVRAM);
989a9d23
MC		 14301 protect = 1;
14302 }
d3c7b886 14303
989a9d23
MC		 14304 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14305 switch (nvcfg1) {
8590a603
MC		 14306 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14307 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14308 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14309 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14310 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14311 tg3_flag_set(tp, NVRAM_BUFFERED);
14312 tg3_flag_set(tp, FLASH);
8590a603
MC		 14313 tp->nvram_pagesize = 264;
14314 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14315 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14316 tp->nvram_size = (protect ? 0x3e200 :
14317 TG3_NVRAM_SIZE_512KB);
14318 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14319 tp->nvram_size = (protect ? 0x1f200 :
14320 TG3_NVRAM_SIZE_256KB);
14321 else
14322 tp->nvram_size = (protect ? 0x1f200 :
14323 TG3_NVRAM_SIZE_128KB);
14324 break;
14325 case FLASH_5752VENDOR_ST_M45PE10:
14326 case FLASH_5752VENDOR_ST_M45PE20:
14327 case FLASH_5752VENDOR_ST_M45PE40:
14328 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14329 tg3_flag_set(tp, NVRAM_BUFFERED);
14330 tg3_flag_set(tp, FLASH);
8590a603
MC		 14331 tp->nvram_pagesize = 256;
14332 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14333 tp->nvram_size = (protect ?
14334 TG3_NVRAM_SIZE_64KB :
14335 TG3_NVRAM_SIZE_128KB);
14336 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14337 tp->nvram_size = (protect ?
14338 TG3_NVRAM_SIZE_64KB :
14339 TG3_NVRAM_SIZE_256KB);
14340 else
14341 tp->nvram_size = (protect ?
14342 TG3_NVRAM_SIZE_128KB :
14343 TG3_NVRAM_SIZE_512KB);
14344 break;
d3c7b886
MC		 14345 }
14346}
14347
229b1ad1 14348static void tg3_get_5787_nvram_info(struct tg3 *tp)
1b27777a
MC		 14349{
14350 u32 nvcfg1;
14351
14352 nvcfg1 = tr32(NVRAM_CFG1);
14353
14354 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14355 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14356 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14357 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14358 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14359 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14360 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603 14361 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 14362
8590a603
MC		 14363 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14364 tw32(NVRAM_CFG1, nvcfg1);
14365 break;
14366 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14367 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14368 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14369 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14370 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14371 tg3_flag_set(tp, NVRAM_BUFFERED);
14372 tg3_flag_set(tp, FLASH);
8590a603
MC		 14373 tp->nvram_pagesize = 264;
14374 break;
14375 case FLASH_5752VENDOR_ST_M45PE10:
14376 case FLASH_5752VENDOR_ST_M45PE20:
14377 case FLASH_5752VENDOR_ST_M45PE40:
14378 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14379 tg3_flag_set(tp, NVRAM_BUFFERED);
14380 tg3_flag_set(tp, FLASH);
8590a603
MC		 14381 tp->nvram_pagesize = 256;
14382 break;
1b27777a
MC		 14383 }
14384}
14385
229b1ad1 14386static void tg3_get_5761_nvram_info(struct tg3 *tp)
6b91fa02
MC		 14387{
14388 u32 nvcfg1, protect = 0;
14389
14390 nvcfg1 = tr32(NVRAM_CFG1);
14391
14392 /* NVRAM protection for TPM */
14393 if (nvcfg1 & (1 << 27)) {
63c3a66f 14394 tg3_flag_set(tp, PROTECTED_NVRAM);
6b91fa02
MC		 14395 protect = 1;
14396 }
14397
14398 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14399 switch (nvcfg1) {
8590a603
MC		 14400 case FLASH_5761VENDOR_ATMEL_ADB021D:
14401 case FLASH_5761VENDOR_ATMEL_ADB041D:
14402 case FLASH_5761VENDOR_ATMEL_ADB081D:
14403 case FLASH_5761VENDOR_ATMEL_ADB161D:
14404 case FLASH_5761VENDOR_ATMEL_MDB021D:
14405 case FLASH_5761VENDOR_ATMEL_MDB041D:
14406 case FLASH_5761VENDOR_ATMEL_MDB081D:
14407 case FLASH_5761VENDOR_ATMEL_MDB161D:
14408 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14409 tg3_flag_set(tp, NVRAM_BUFFERED);
14410 tg3_flag_set(tp, FLASH);
14411 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
8590a603
MC		 14412 tp->nvram_pagesize = 256;
14413 break;
14414 case FLASH_5761VENDOR_ST_A_M45PE20:
14415 case FLASH_5761VENDOR_ST_A_M45PE40:
14416 case FLASH_5761VENDOR_ST_A_M45PE80:
14417 case FLASH_5761VENDOR_ST_A_M45PE16:
14418 case FLASH_5761VENDOR_ST_M_M45PE20:
14419 case FLASH_5761VENDOR_ST_M_M45PE40:
14420 case FLASH_5761VENDOR_ST_M_M45PE80:
14421 case FLASH_5761VENDOR_ST_M_M45PE16:
14422 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14423 tg3_flag_set(tp, NVRAM_BUFFERED);
14424 tg3_flag_set(tp, FLASH);
8590a603
MC		 14425 tp->nvram_pagesize = 256;
14426 break;
6b91fa02
MC		 14427 }
14428
14429 if (protect) {
14430 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14431 } else {
14432 switch (nvcfg1) {
8590a603
MC		 14433 case FLASH_5761VENDOR_ATMEL_ADB161D:
14434 case FLASH_5761VENDOR_ATMEL_MDB161D:
14435 case FLASH_5761VENDOR_ST_A_M45PE16:
14436 case FLASH_5761VENDOR_ST_M_M45PE16:
14437 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14438 break;
14439 case FLASH_5761VENDOR_ATMEL_ADB081D:
14440 case FLASH_5761VENDOR_ATMEL_MDB081D:
14441 case FLASH_5761VENDOR_ST_A_M45PE80:
14442 case FLASH_5761VENDOR_ST_M_M45PE80:
14443 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14444 break;
14445 case FLASH_5761VENDOR_ATMEL_ADB041D:
14446 case FLASH_5761VENDOR_ATMEL_MDB041D:
14447 case FLASH_5761VENDOR_ST_A_M45PE40:
14448 case FLASH_5761VENDOR_ST_M_M45PE40:
14449 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14450 break;
14451 case FLASH_5761VENDOR_ATMEL_ADB021D:
14452 case FLASH_5761VENDOR_ATMEL_MDB021D:
14453 case FLASH_5761VENDOR_ST_A_M45PE20:
14454 case FLASH_5761VENDOR_ST_M_M45PE20:
14455 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14456 break;
6b91fa02
MC		 14457 }
14458 }
14459}
14460
229b1ad1 14461static void tg3_get_5906_nvram_info(struct tg3 *tp)
b5d3772c
MC		 14462{
14463 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14464 tg3_flag_set(tp, NVRAM_BUFFERED);
b5d3772c
MC		 14465 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14466}
14467
229b1ad1 14468static void tg3_get_57780_nvram_info(struct tg3 *tp)
321d32a0
MC		 14469{
14470 u32 nvcfg1;
14471
14472 nvcfg1 = tr32(NVRAM_CFG1);
14473
14474 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14475 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14476 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14477 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14478 tg3_flag_set(tp, NVRAM_BUFFERED);
321d32a0
MC		 14479 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14480
14481 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14482 tw32(NVRAM_CFG1, nvcfg1);
14483 return;
14484 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14485 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14486 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14487 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14488 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14489 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14490 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14491 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14492 tg3_flag_set(tp, NVRAM_BUFFERED);
14493 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14494
14495 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14496 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14497 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14498 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14499 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14500 break;
14501 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14502 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14503 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14504 break;
14505 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14506 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14507 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14508 break;
14509 }
14510 break;
14511 case FLASH_5752VENDOR_ST_M45PE10:
14512 case FLASH_5752VENDOR_ST_M45PE20:
14513 case FLASH_5752VENDOR_ST_M45PE40:
14514 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14515 tg3_flag_set(tp, NVRAM_BUFFERED);
14516 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14517
14518 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14519 case FLASH_5752VENDOR_ST_M45PE10:
14520 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14521 break;
14522 case FLASH_5752VENDOR_ST_M45PE20:
14523 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14524 break;
14525 case FLASH_5752VENDOR_ST_M45PE40:
14526 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14527 break;
14528 }
14529 break;
14530 default:
63c3a66f 14531 tg3_flag_set(tp, NO_NVRAM);
321d32a0
MC		 14532 return;
14533 }
14534
a1b950d5
MC		 14535 tg3_nvram_get_pagesize(tp, nvcfg1);
14536 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14537 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
a1b950d5
MC		 14538}
14539
14540
229b1ad1 14541static void tg3_get_5717_nvram_info(struct tg3 *tp)
a1b950d5
MC		 14542{
14543 u32 nvcfg1;
14544
14545 nvcfg1 = tr32(NVRAM_CFG1);
14546
14547 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14548 case FLASH_5717VENDOR_ATMEL_EEPROM:
14549 case FLASH_5717VENDOR_MICRO_EEPROM:
14550 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14551 tg3_flag_set(tp, NVRAM_BUFFERED);
a1b950d5
MC		 14552 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14553
14554 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14555 tw32(NVRAM_CFG1, nvcfg1);
14556 return;
14557 case FLASH_5717VENDOR_ATMEL_MDB011D:
14558 case FLASH_5717VENDOR_ATMEL_ADB011B:
14559 case FLASH_5717VENDOR_ATMEL_ADB011D:
14560 case FLASH_5717VENDOR_ATMEL_MDB021D:
14561 case FLASH_5717VENDOR_ATMEL_ADB021B:
14562 case FLASH_5717VENDOR_ATMEL_ADB021D:
14563 case FLASH_5717VENDOR_ATMEL_45USPT:
14564 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14565 tg3_flag_set(tp, NVRAM_BUFFERED);
14566 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14567
14568 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14569 case FLASH_5717VENDOR_ATMEL_MDB021D:
66ee33bf
MC		 14570 /* Detect size with tg3_nvram_get_size() */
14571 break;
a1b950d5
MC		 14572 case FLASH_5717VENDOR_ATMEL_ADB021B:
14573 case FLASH_5717VENDOR_ATMEL_ADB021D:
14574 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14575 break;
14576 default:
14577 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14578 break;
14579 }
321d32a0 14580 break;
a1b950d5
MC		 14581 case FLASH_5717VENDOR_ST_M_M25PE10:
14582 case FLASH_5717VENDOR_ST_A_M25PE10:
14583 case FLASH_5717VENDOR_ST_M_M45PE10:
14584 case FLASH_5717VENDOR_ST_A_M45PE10:
14585 case FLASH_5717VENDOR_ST_M_M25PE20:
14586 case FLASH_5717VENDOR_ST_A_M25PE20:
14587 case FLASH_5717VENDOR_ST_M_M45PE20:
14588 case FLASH_5717VENDOR_ST_A_M45PE20:
14589 case FLASH_5717VENDOR_ST_25USPT:
14590 case FLASH_5717VENDOR_ST_45USPT:
14591 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14592 tg3_flag_set(tp, NVRAM_BUFFERED);
14593 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14594
14595 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14596 case FLASH_5717VENDOR_ST_M_M25PE20:
a1b950d5 14597 case FLASH_5717VENDOR_ST_M_M45PE20:
66ee33bf
MC		 14598 /* Detect size with tg3_nvram_get_size() */
14599 break;
14600 case FLASH_5717VENDOR_ST_A_M25PE20:
a1b950d5
MC		 14601 case FLASH_5717VENDOR_ST_A_M45PE20:
14602 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14603 break;
14604 default:
14605 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14606 break;
14607 }
321d32a0 14608 break;
a1b950d5 14609 default:
63c3a66f 14610 tg3_flag_set(tp, NO_NVRAM);
a1b950d5 14611 return;
321d32a0 14612 }
a1b950d5
MC		 14613
14614 tg3_nvram_get_pagesize(tp, nvcfg1);
14615 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14616 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
321d32a0
MC		 14617}
14618
229b1ad1 14619static void tg3_get_5720_nvram_info(struct tg3 *tp)
9b91b5f1
MC		 14620{
14621 u32 nvcfg1, nvmpinstrp;
14622
14623 nvcfg1 = tr32(NVRAM_CFG1);
14624 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14625
4153577a 14626 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14627 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14628 tg3_flag_set(tp, NO_NVRAM);
14629 return;
14630 }
14631
14632 switch (nvmpinstrp) {
14633 case FLASH_5762_EEPROM_HD:
14634 nvmpinstrp = FLASH_5720_EEPROM_HD;
17e1a42f 14635 break;
c86a8560
MC		 14636 case FLASH_5762_EEPROM_LD:
14637 nvmpinstrp = FLASH_5720_EEPROM_LD;
17e1a42f 14638 break;
f6334bb8
MC		 14639 case FLASH_5720VENDOR_M_ST_M45PE20:
14640 /* This pinstrap supports multiple sizes, so force it
14641 * to read the actual size from location 0xf0.
14642 */
14643 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14644 break;
c86a8560
MC		 14645 }
14646 }
14647
9b91b5f1
MC		 14648 switch (nvmpinstrp) {
14649 case FLASH_5720_EEPROM_HD:
14650 case FLASH_5720_EEPROM_LD:
14651 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14652 tg3_flag_set(tp, NVRAM_BUFFERED);
9b91b5f1
MC		 14653
14654 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14655 tw32(NVRAM_CFG1, nvcfg1);
14656 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14657 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14658 else
14659 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14660 return;
14661 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14662 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14663 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14664 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14665 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14666 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14667 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14668 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14669 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14670 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14671 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14672 case FLASH_5720VENDOR_ATMEL_45USPT:
14673 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14674 tg3_flag_set(tp, NVRAM_BUFFERED);
14675 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14676
14677 switch (nvmpinstrp) {
14678 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14679 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14680 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14681 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14682 break;
14683 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14684 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14685 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14686 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14687 break;
14688 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14689 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14690 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14691 break;
14692 default:
4153577a 14693 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14694 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14695 break;
14696 }
14697 break;
14698 case FLASH_5720VENDOR_M_ST_M25PE10:
14699 case FLASH_5720VENDOR_M_ST_M45PE10:
14700 case FLASH_5720VENDOR_A_ST_M25PE10:
14701 case FLASH_5720VENDOR_A_ST_M45PE10:
14702 case FLASH_5720VENDOR_M_ST_M25PE20:
14703 case FLASH_5720VENDOR_M_ST_M45PE20:
14704 case FLASH_5720VENDOR_A_ST_M25PE20:
14705 case FLASH_5720VENDOR_A_ST_M45PE20:
14706 case FLASH_5720VENDOR_M_ST_M25PE40:
14707 case FLASH_5720VENDOR_M_ST_M45PE40:
14708 case FLASH_5720VENDOR_A_ST_M25PE40:
14709 case FLASH_5720VENDOR_A_ST_M45PE40:
14710 case FLASH_5720VENDOR_M_ST_M25PE80:
14711 case FLASH_5720VENDOR_M_ST_M45PE80:
14712 case FLASH_5720VENDOR_A_ST_M25PE80:
14713 case FLASH_5720VENDOR_A_ST_M45PE80:
14714 case FLASH_5720VENDOR_ST_25USPT:
14715 case FLASH_5720VENDOR_ST_45USPT:
14716 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14717 tg3_flag_set(tp, NVRAM_BUFFERED);
14718 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14719
14720 switch (nvmpinstrp) {
14721 case FLASH_5720VENDOR_M_ST_M25PE20:
14722 case FLASH_5720VENDOR_M_ST_M45PE20:
14723 case FLASH_5720VENDOR_A_ST_M25PE20:
14724 case FLASH_5720VENDOR_A_ST_M45PE20:
14725 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14726 break;
14727 case FLASH_5720VENDOR_M_ST_M25PE40:
14728 case FLASH_5720VENDOR_M_ST_M45PE40:
14729 case FLASH_5720VENDOR_A_ST_M25PE40:
14730 case FLASH_5720VENDOR_A_ST_M45PE40:
14731 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14732 break;
14733 case FLASH_5720VENDOR_M_ST_M25PE80:
14734 case FLASH_5720VENDOR_M_ST_M45PE80:
14735 case FLASH_5720VENDOR_A_ST_M25PE80:
14736 case FLASH_5720VENDOR_A_ST_M45PE80:
14737 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14738 break;
14739 default:
4153577a 14740 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14741 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14742 break;
14743 }
14744 break;
14745 default:
63c3a66f 14746 tg3_flag_set(tp, NO_NVRAM);
9b91b5f1
MC		 14747 return;
14748 }
14749
14750 tg3_nvram_get_pagesize(tp, nvcfg1);
14751 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14752 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
c86a8560 14753
4153577a 14754 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14755 u32 val;
14756
14757 if (tg3_nvram_read(tp, 0, &val))
14758 return;
14759
14760 if (val != TG3_EEPROM_MAGIC &&
14761 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14762 tg3_flag_set(tp, NO_NVRAM);
14763 }
9b91b5f1
MC		 14764}
14765
1da177e4 14766/* Chips other than 5700/5701 use the NVRAM for fetching info. */
229b1ad1 14767static void tg3_nvram_init(struct tg3 *tp)
1da177e4 14768{
7e6c63f0
HM		 14769 if (tg3_flag(tp, IS_SSB_CORE)) {
14770 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14771 tg3_flag_clear(tp, NVRAM);
14772 tg3_flag_clear(tp, NVRAM_BUFFERED);
14773 tg3_flag_set(tp, NO_NVRAM);
14774 return;
14775 }
14776
1da177e4
LT		 14777 tw32_f(GRC_EEPROM_ADDR,
14778 (EEPROM_ADDR_FSM_RESET |
14779 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14780 EEPROM_ADDR_CLKPERD_SHIFT)));
14781
9d57f01c 14782 msleep(1);
1da177e4
LT		 14783
14784 /* Enable seeprom accesses. */
14785 tw32_f(GRC_LOCAL_CTRL,
14786 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14787 udelay(100);
14788
4153577a
JP		 14789 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14790 tg3_asic_rev(tp) != ASIC_REV_5701) {
63c3a66f 14791 tg3_flag_set(tp, NVRAM);
1da177e4 14792
ec41c7df 14793 if (tg3_nvram_lock(tp)) {
5129c3a3
MC		 14794 netdev_warn(tp->dev,
14795 "Cannot get nvram lock, %s failed\n",
05dbe005 14796 __func__);
ec41c7df
MC		 14797 return;
14798 }
e6af301b 14799 tg3_enable_nvram_access(tp);
1da177e4 14800
989a9d23
MC		 14801 tp->nvram_size = 0;
14802
4153577a 14803 if (tg3_asic_rev(tp) == ASIC_REV_5752)
361b4ac2 14804 tg3_get_5752_nvram_info(tp);
4153577a 14805 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
d3c7b886 14806 tg3_get_5755_nvram_info(tp);
4153577a
JP		 14807 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14808 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14809 tg3_asic_rev(tp) == ASIC_REV_5785)
1b27777a 14810 tg3_get_5787_nvram_info(tp);
4153577a 14811 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
6b91fa02 14812 tg3_get_5761_nvram_info(tp);
4153577a 14813 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 14814 tg3_get_5906_nvram_info(tp);
4153577a 14815 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 14816 tg3_flag(tp, 57765_CLASS))
321d32a0 14817 tg3_get_57780_nvram_info(tp);
4153577a
JP		 14818 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14819 tg3_asic_rev(tp) == ASIC_REV_5719)
a1b950d5 14820 tg3_get_5717_nvram_info(tp);
4153577a
JP		 14821 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14822 tg3_asic_rev(tp) == ASIC_REV_5762)
9b91b5f1 14823 tg3_get_5720_nvram_info(tp);
361b4ac2
MC		 14824 else
14825 tg3_get_nvram_info(tp);
14826
989a9d23
MC		 14827 if (tp->nvram_size == 0)
14828 tg3_get_nvram_size(tp);
1da177e4 14829
e6af301b 14830 tg3_disable_nvram_access(tp);
381291b7 14831 tg3_nvram_unlock(tp);
1da177e4
LT		 14832
14833 } else {
63c3a66f
JP		 14834 tg3_flag_clear(tp, NVRAM);
14835 tg3_flag_clear(tp, NVRAM_BUFFERED);
1da177e4
LT		 14836
14837 tg3_get_eeprom_size(tp);
14838 }
14839}
14840
1da177e4
LT		 14841struct subsys_tbl_ent {
14842 u16 subsys_vendor, subsys_devid;
14843 u32 phy_id;
14844};
14845
229b1ad1 14846static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
1da177e4 14847 /* Broadcom boards. */
24daf2b0 14848 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14849 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 14850 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14851 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 14852 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14853 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 14854 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14855 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14856 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14857 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 14858 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14859 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14860 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14861 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14862 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14863 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 14864 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14865 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 14866 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14867 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 14868 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14869 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 14870
14871 /* 3com boards. */
24daf2b0 14872 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14873 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 14874 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14875 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14876 { TG3PCI_SUBVENDOR_ID_3COM,
14877 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
14878 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14879 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 14880 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14881 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14882
14883 /* DELL boards. */
24daf2b0 14884 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14885 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 14886 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14887 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 14888 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14889 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 14890 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14891 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 14892
14893 /* Compaq boards. */
24daf2b0 14894 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14895 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 14896 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14897 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14898 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14899 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
14900 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14901 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 14902 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14903 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14904
14905 /* IBM boards. */
24daf2b0
MC		 14906 { TG3PCI_SUBVENDOR_ID_IBM,
14907 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 14908};
14909
229b1ad1 14910static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 14911{
14912 int i;
14913
14914 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
14915 if ((subsys_id_to_phy_id[i].subsys_vendor ==
14916 tp->pdev->subsystem_vendor) &&
14917 (subsys_id_to_phy_id[i].subsys_devid ==
14918 tp->pdev->subsystem_device))
14919 return &subsys_id_to_phy_id[i];
14920 }
14921 return NULL;
14922}
14923
229b1ad1 14924static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 14925{
1da177e4 14926 u32 val;
f49639e6 14927
79eb6904 14928 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 14929 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14930
a85feb8c 14931 /* Assume an onboard device and WOL capable by default. */
63c3a66f
JP		 14932 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14933 tg3_flag_set(tp, WOL_CAP);
72b845e0 14934
4153577a 14935 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9d26e213 14936 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
63c3a66f
JP		 14937 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14938 tg3_flag_set(tp, IS_NIC);
9d26e213 14939 }
0527ba35
MC		 14940 val = tr32(VCPU_CFGSHDW);
14941 if (val & VCPU_CFGSHDW_ASPM_DBNC)
63c3a66f 14942 tg3_flag_set(tp, ASPM_WORKAROUND);
0527ba35 14943 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
6fdbab9d 14944 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
63c3a66f 14945 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 14946 device_set_wakeup_enable(&tp->pdev->dev, true);
14947 }
05ac4cb7 14948 goto done;
b5d3772c
MC		 14949 }
14950
1da177e4
LT		 14951 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
14952 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
14953 u32 nic_cfg, led_cfg;
7c786065
NS		 14954 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
14955 u32 nic_phy_id, ver, eeprom_phy_id;
7d0c41ef 14956 int eeprom_phy_serdes = 0;
1da177e4
LT		 14957
14958 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
14959 tp->nic_sram_data_cfg = nic_cfg;
14960
14961 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
14962 ver >>= NIC_SRAM_DATA_VER_SHIFT;
4153577a
JP		 14963 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14964 tg3_asic_rev(tp) != ASIC_REV_5701 &&
14965 tg3_asic_rev(tp) != ASIC_REV_5703 &&
1da177e4
LT		 14966 (ver > 0) && (ver < 0x100))
14967 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
14968
4153577a 14969 if (tg3_asic_rev(tp) == ASIC_REV_5785)
a9daf367
MC		 14970 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
14971
7c786065
NS		 14972 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14973 tg3_asic_rev(tp) == ASIC_REV_5719 ||
14974 tg3_asic_rev(tp) == ASIC_REV_5720)
14975 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
14976
1da177e4
LT		 14977 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
14978 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
14979 eeprom_phy_serdes = 1;
14980
14981 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
14982 if (nic_phy_id != 0) {
14983 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
14984 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
14985
14986 eeprom_phy_id = (id1 >> 16) << 10;
14987 eeprom_phy_id |= (id2 & 0xfc00) << 16;
14988 eeprom_phy_id |= (id2 & 0x03ff) << 0;
14989 } else
14990 eeprom_phy_id = 0;
14991
7d0c41ef 14992 tp->phy_id = eeprom_phy_id;
747e8f8b 14993 if (eeprom_phy_serdes) {
63c3a66f 14994 if (!tg3_flag(tp, 5705_PLUS))
f07e9af3 14995 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
a50d0796 14996 else
f07e9af3 14997 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
747e8f8b 14998 }
7d0c41ef 14999
63c3a66f 15000 if (tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 15001 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15002 SHASTA_EXT_LED_MODE_MASK);
cbf46853 15003 else
1da177e4
LT		 15004 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15005
15006 switch (led_cfg) {
15007 default:
15008 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15009 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15010 break;
15011
15012 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15013 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15014 break;
15015
15016 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15017 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 15018
15019 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15020 * read on some older 5700/5701 bootcode.
15021 */
4153577a
JP		 15022 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15023 tg3_asic_rev(tp) == ASIC_REV_5701)
9ba27794
MC		 15024 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15025
1da177e4
LT		 15026 break;
15027
15028 case SHASTA_EXT_LED_SHARED:
15029 tp->led_ctrl = LED_CTRL_MODE_SHARED;
4153577a
JP		 15030 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15031 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
1da177e4
LT		 15032 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15033 LED_CTRL_MODE_PHY_2);
89f67978
NS		 15034
15035 if (tg3_flag(tp, 5717_PLUS) ||
15036 tg3_asic_rev(tp) == ASIC_REV_5762)
15037 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15038 LED_CTRL_BLINK_RATE_MASK;
15039
1da177e4
LT		 15040 break;
15041
15042 case SHASTA_EXT_LED_MAC:
15043 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15044 break;
15045
15046 case SHASTA_EXT_LED_COMBO:
15047 tp->led_ctrl = LED_CTRL_MODE_COMBO;
4153577a 15048 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
1da177e4
LT		 15049 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15050 LED_CTRL_MODE_PHY_2);
15051 break;
15052
855e1111 15053 }
1da177e4 15054
4153577a
JP		 15055 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15056 tg3_asic_rev(tp) == ASIC_REV_5701) &&
1da177e4
LT		 15057 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15058 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15059
4153577a 15060 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
b2a5c19c 15061 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 15062
9d26e213 15063 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
63c3a66f 15064 tg3_flag_set(tp, EEPROM_WRITE_PROT);
9d26e213
MC		 15065 if ((tp->pdev->subsystem_vendor ==
15066 PCI_VENDOR_ID_ARIMA) &&
15067 (tp->pdev->subsystem_device == 0x205a ||
15068 tp->pdev->subsystem_device == 0x2063))
63c3a66f 15069 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
9d26e213 15070 } else {
63c3a66f
JP		 15071 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15072 tg3_flag_set(tp, IS_NIC);
9d26e213 15073 }
1da177e4
LT		 15074
15075 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f
JP		 15076 tg3_flag_set(tp, ENABLE_ASF);
15077 if (tg3_flag(tp, 5750_PLUS))
15078 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
1da177e4 15079 }
b2b98d4a
MC		 15080
15081 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
63c3a66f
JP		 15082 tg3_flag(tp, 5750_PLUS))
15083 tg3_flag_set(tp, ENABLE_APE);
b2b98d4a 15084
f07e9af3 15085 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
a85feb8c 15086 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
63c3a66f 15087 tg3_flag_clear(tp, WOL_CAP);
1da177e4 15088
63c3a66f 15089 if (tg3_flag(tp, WOL_CAP) &&
6fdbab9d 15090 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
63c3a66f 15091 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 15092 device_set_wakeup_enable(&tp->pdev->dev, true);
15093 }
0527ba35 15094
1da177e4 15095 if (cfg2 & (1 << 17))
f07e9af3 15096 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
1da177e4
LT		 15097
15098 /* serdes signal pre-emphasis in register 0x590 set by */
15099 /* bootcode if bit 18 is set */
15100 if (cfg2 & (1 << 18))
f07e9af3 15101 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
8ed5d97e 15102
63c3a66f 15103 if ((tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 15104 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15105 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
6833c043 15106 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
f07e9af3 15107 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
6833c043 15108
942d1af0 15109 if (tg3_flag(tp, PCI_EXPRESS)) {
8ed5d97e
MC		 15110 u32 cfg3;
15111
15112 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
942d1af0
NS		 15113 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15114 !tg3_flag(tp, 57765_PLUS) &&
15115 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
63c3a66f 15116 tg3_flag_set(tp, ASPM_WORKAROUND);
942d1af0
NS		 15117 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15118 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15119 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15120 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
8ed5d97e 15121 }
a9daf367 15122
14417063 15123 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
63c3a66f 15124 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
a9daf367 15125 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
63c3a66f 15126 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
a9daf367 15127 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
63c3a66f 15128 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
7c786065
NS		 15129
15130 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15131 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
1da177e4 15132 }
05ac4cb7 15133done:
63c3a66f 15134 if (tg3_flag(tp, WOL_CAP))
43067ed8 15135 device_set_wakeup_enable(&tp->pdev->dev,
63c3a66f 15136 tg3_flag(tp, WOL_ENABLE));
43067ed8
RW		 15137 else
15138 device_set_wakeup_capable(&tp->pdev->dev, false);
7d0c41ef
MC		 15139}
15140
c86a8560
MC		 15141static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15142{
15143 int i, err;
15144 u32 val2, off = offset * 8;
15145
15146 err = tg3_nvram_lock(tp);
15147 if (err)
15148 return err;
15149
15150 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15151 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15152 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15153 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15154 udelay(10);
15155
15156 for (i = 0; i < 100; i++) {
15157 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15158 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15159 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15160 break;
15161 }
15162 udelay(10);
15163 }
15164
15165 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15166
15167 tg3_nvram_unlock(tp);
15168 if (val2 & APE_OTP_STATUS_CMD_DONE)
15169 return 0;
15170
15171 return -EBUSY;
15172}
15173
229b1ad1 15174static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
b2a5c19c
MC		 15175{
15176 int i;
15177 u32 val;
15178
15179 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15180 tw32(OTP_CTRL, cmd);
15181
15182 /* Wait for up to 1 ms for command to execute. */
15183 for (i = 0; i < 100; i++) {
15184 val = tr32(OTP_STATUS);
15185 if (val & OTP_STATUS_CMD_DONE)
15186 break;
15187 udelay(10);
15188 }
15189
15190 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15191}
15192
15193/* Read the gphy configuration from the OTP region of the chip. The gphy
15194 * configuration is a 32-bit value that straddles the alignment boundary.
15195 * We do two 32-bit reads and then shift and merge the results.
15196 */
229b1ad1 15197static u32 tg3_read_otp_phycfg(struct tg3 *tp)
b2a5c19c
MC		 15198{
15199 u32 bhalf_otp, thalf_otp;
15200
15201 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15202
15203 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15204 return 0;
15205
15206 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15207
15208 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15209 return 0;
15210
15211 thalf_otp = tr32(OTP_READ_DATA);
15212
15213 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15214
15215 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15216 return 0;
15217
15218 bhalf_otp = tr32(OTP_READ_DATA);
15219
15220 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15221}
15222
229b1ad1 15223static void tg3_phy_init_link_config(struct tg3 *tp)
e256f8a3 15224{
202ff1c2 15225 u32 adv = ADVERTISED_Autoneg;
e256f8a3 15226
7c786065
NS		 15227 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15228 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15229 adv |= ADVERTISED_1000baseT_Half;
15230 adv |= ADVERTISED_1000baseT_Full;
15231 }
e256f8a3
MC		 15232
15233 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15234 adv |= ADVERTISED_100baseT_Half |
15235 ADVERTISED_100baseT_Full |
15236 ADVERTISED_10baseT_Half |
15237 ADVERTISED_10baseT_Full |
15238 ADVERTISED_TP;
15239 else
15240 adv |= ADVERTISED_FIBRE;
15241
15242 tp->link_config.advertising = adv;
e740522e
MC		 15243 tp->link_config.speed = SPEED_UNKNOWN;
15244 tp->link_config.duplex = DUPLEX_UNKNOWN;
e256f8a3 15245 tp->link_config.autoneg = AUTONEG_ENABLE;
e740522e
MC		 15246 tp->link_config.active_speed = SPEED_UNKNOWN;
15247 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
34655ad6
MC		 15248
15249 tp->old_link = -1;
e256f8a3
MC		 15250}
15251
229b1ad1 15252static int tg3_phy_probe(struct tg3 *tp)
7d0c41ef
MC		 15253{
15254 u32 hw_phy_id_1, hw_phy_id_2;
15255 u32 hw_phy_id, hw_phy_id_masked;
15256 int err;
1da177e4 15257
e256f8a3 15258 /* flow control autonegotiation is default behavior */
63c3a66f 15259 tg3_flag_set(tp, PAUSE_AUTONEG);
e256f8a3
MC		 15260 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15261
8151ad57
MC		 15262 if (tg3_flag(tp, ENABLE_APE)) {
15263 switch (tp->pci_fn) {
15264 case 0:
15265 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15266 break;
15267 case 1:
15268 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15269 break;
15270 case 2:
15271 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15272 break;
15273 case 3:
15274 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15275 break;
15276 }
15277 }
15278
942d1af0
NS		 15279 if (!tg3_flag(tp, ENABLE_ASF) &&
15280 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15281 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15282 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15283 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15284
63c3a66f 15285 if (tg3_flag(tp, USE_PHYLIB))
b02fd9e3
MC		 15286 return tg3_phy_init(tp);
15287
1da177e4 15288 /* Reading the PHY ID register can conflict with ASF
877d0310 15289 * firmware access to the PHY hardware.
1da177e4
LT		 15290 */
15291 err = 0;
63c3a66f 15292 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
79eb6904 15293 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 15294 } else {
15295 /* Now read the physical PHY_ID from the chip and verify
15296 * that it is sane. If it doesn't look good, we fall back
15297 * to either the hard-coded table based PHY_ID and failing
15298 * that the value found in the eeprom area.
15299 */
15300 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15301 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15302
15303 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15304 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15305 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15306
79eb6904 15307 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 15308 }
15309
79eb6904 15310 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 15311 tp->phy_id = hw_phy_id;
79eb6904 15312 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
f07e9af3 15313 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
da6b2d01 15314 else
f07e9af3 15315 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
1da177e4 15316 } else {
79eb6904 15317 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 15318 /* Do nothing, phy ID already set up in
15319 * tg3_get_eeprom_hw_cfg().
15320 */
1da177e4
LT		 15321 } else {
15322 struct subsys_tbl_ent *p;
15323
15324 /* No eeprom signature? Try the hardcoded
15325 * subsys device table.
15326 */
24daf2b0 15327 p = tg3_lookup_by_subsys(tp);
7e6c63f0
HM		 15328 if (p) {
15329 tp->phy_id = p->phy_id;
15330 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15331 /* For now we saw the IDs 0xbc050cd0,
15332 * 0xbc050f80 and 0xbc050c30 on devices
15333 * connected to an BCM4785 and there are
15334 * probably more. Just assume that the phy is
15335 * supported when it is connected to a SSB core
15336 * for now.
15337 */
1da177e4 15338 return -ENODEV;
7e6c63f0 15339 }
1da177e4 15340
1da177e4 15341 if (!tp->phy_id ||
79eb6904 15342 tp->phy_id == TG3_PHY_ID_BCM8002)
f07e9af3 15343 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
1da177e4
LT		 15344 }
15345 }
15346
a6b68dab 15347 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
4153577a
JP		 15348 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15349 tg3_asic_rev(tp) == ASIC_REV_5720 ||
c4dab506 15350 tg3_asic_rev(tp) == ASIC_REV_57766 ||
4153577a
JP		 15351 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15352 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15353 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15354 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
9e2ecbeb 15355 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
52b02d04
MC		 15356 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15357
9e2ecbeb
NS		 15358 tp->eee.supported = SUPPORTED_100baseT_Full |
15359 SUPPORTED_1000baseT_Full;
15360 tp->eee.advertised = ADVERTISED_100baseT_Full |
15361 ADVERTISED_1000baseT_Full;
15362 tp->eee.eee_enabled = 1;
15363 tp->eee.tx_lpi_enabled = 1;
15364 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15365 }
15366
e256f8a3
MC		 15367 tg3_phy_init_link_config(tp);
15368
942d1af0
NS		 15369 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15370 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
63c3a66f
JP		 15371 !tg3_flag(tp, ENABLE_APE) &&
15372 !tg3_flag(tp, ENABLE_ASF)) {
e2bf73e7 15373 u32 bmsr, dummy;
1da177e4
LT		 15374
15375 tg3_readphy(tp, MII_BMSR, &bmsr);
15376 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15377 (bmsr & BMSR_LSTATUS))
15378 goto skip_phy_reset;
6aa20a22 15379
1da177e4
LT		 15380 err = tg3_phy_reset(tp);
15381 if (err)
15382 return err;
15383
42b64a45 15384 tg3_phy_set_wirespeed(tp);
1da177e4 15385
e2bf73e7 15386 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
42b64a45
MC		 15387 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15388 tp->link_config.flowctrl);
1da177e4
LT		 15389
15390 tg3_writephy(tp, MII_BMCR,
15391 BMCR_ANENABLE | BMCR_ANRESTART);
15392 }
1da177e4
LT		 15393 }
15394
15395skip_phy_reset:
79eb6904 15396 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 15397 err = tg3_init_5401phy_dsp(tp);
15398 if (err)
15399 return err;
1da177e4 15400
1da177e4
LT		 15401 err = tg3_init_5401phy_dsp(tp);
15402 }
15403
1da177e4
LT		 15404 return err;
15405}
15406
229b1ad1 15407static void tg3_read_vpd(struct tg3 *tp)
1da177e4 15408{
a4a8bb15 15409 u8 *vpd_data;
4181b2c8 15410 unsigned int block_end, rosize, len;
535a490e 15411 u32 vpdlen;
184b8904 15412 int j, i = 0;
a4a8bb15 15413
535a490e 15414 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
a4a8bb15
MC		 15415 if (!vpd_data)
15416 goto out_no_vpd;
1da177e4 15417
535a490e 15418 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
4181b2c8
MC		 15419 if (i < 0)
15420 goto out_not_found;
1da177e4 15421
4181b2c8
MC		 15422 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15423 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15424 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 15425
535a490e 15426 if (block_end > vpdlen)
4181b2c8 15427 goto out_not_found;
af2c6a4a 15428
184b8904
MC		 15429 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15430 PCI_VPD_RO_KEYWORD_MFR_ID);
15431 if (j > 0) {
15432 len = pci_vpd_info_field_size(&vpd_data[j]);
15433
15434 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15435 if (j + len > block_end || len != 4 ||
15436 memcmp(&vpd_data[j], "1028", 4))
15437 goto partno;
15438
15439 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15440 PCI_VPD_RO_KEYWORD_VENDOR0);
15441 if (j < 0)
15442 goto partno;
15443
15444 len = pci_vpd_info_field_size(&vpd_data[j]);
15445
15446 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15447 if (j + len > block_end)
15448 goto partno;
15449
715230a4
KC		 15450 if (len >= sizeof(tp->fw_ver))
15451 len = sizeof(tp->fw_ver) - 1;
15452 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15453 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15454 &vpd_data[j]);
184b8904
MC		 15455 }
15456
15457partno:
4181b2c8
MC		 15458 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15459 PCI_VPD_RO_KEYWORD_PARTNO);
15460 if (i < 0)
15461 goto out_not_found;
af2c6a4a 15462
4181b2c8 15463 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 15464
4181b2c8
MC		 15465 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15466 if (len > TG3_BPN_SIZE ||
535a490e 15467 (len + i) > vpdlen)
4181b2c8 15468 goto out_not_found;
1da177e4 15469
4181b2c8 15470 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 15471
1da177e4 15472out_not_found:
a4a8bb15 15473 kfree(vpd_data);
37a949c5 15474 if (tp->board_part_number[0])
a4a8bb15
MC		 15475 return;
15476
15477out_no_vpd:
4153577a 15478 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
79d49695
MC		 15479 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15480 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
37a949c5
MC		 15481 strcpy(tp->board_part_number, "BCM5717");
15482 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15483 strcpy(tp->board_part_number, "BCM5718");
15484 else
15485 goto nomatch;
4153577a 15486 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
37a949c5
MC		 15487 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15488 strcpy(tp->board_part_number, "BCM57780");
15489 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15490 strcpy(tp->board_part_number, "BCM57760");
15491 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15492 strcpy(tp->board_part_number, "BCM57790");
15493 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15494 strcpy(tp->board_part_number, "BCM57788");
15495 else
15496 goto nomatch;
4153577a 15497 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
37a949c5
MC		 15498 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15499 strcpy(tp->board_part_number, "BCM57761");
15500 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15501 strcpy(tp->board_part_number, "BCM57765");
15502 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15503 strcpy(tp->board_part_number, "BCM57781");
15504 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15505 strcpy(tp->board_part_number, "BCM57785");
15506 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15507 strcpy(tp->board_part_number, "BCM57791");
15508 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15509 strcpy(tp->board_part_number, "BCM57795");
15510 else
15511 goto nomatch;
4153577a 15512 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
55086ad9
MC		 15513 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15514 strcpy(tp->board_part_number, "BCM57762");
15515 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15516 strcpy(tp->board_part_number, "BCM57766");
15517 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15518 strcpy(tp->board_part_number, "BCM57782");
15519 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15520 strcpy(tp->board_part_number, "BCM57786");
15521 else
15522 goto nomatch;
4153577a 15523 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c 15524 strcpy(tp->board_part_number, "BCM95906");
37a949c5
MC		 15525 } else {
15526nomatch:
b5d3772c 15527 strcpy(tp->board_part_number, "none");
37a949c5 15528 }
1da177e4
LT		 15529}
15530
229b1ad1 15531static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
9c8a620e
MC		 15532{
15533 u32 val;
15534
e4f34110 15535 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 15536 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 15537 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 15538 val != 0)
15539 return 0;
15540
15541 return 1;
15542}
15543
229b1ad1 15544static void tg3_read_bc_ver(struct tg3 *tp)
acd9c119 15545{
ff3a7cb2 15546 u32 val, offset, start, ver_offset;
75f9936e 15547 int i, dst_off;
ff3a7cb2 15548 bool newver = false;
acd9c119
MC		 15549
15550 if (tg3_nvram_read(tp, 0xc, &offset) ||
15551 tg3_nvram_read(tp, 0x4, &start))
15552 return;
15553
15554 offset = tg3_nvram_logical_addr(tp, offset);
15555
ff3a7cb2 15556 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 15557 return;
15558
ff3a7cb2
MC		 15559 if ((val & 0xfc000000) == 0x0c000000) {
15560 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 15561 return;
15562
ff3a7cb2
MC		 15563 if (val == 0)
15564 newver = true;
15565 }
15566
75f9936e
MC		 15567 dst_off = strlen(tp->fw_ver);
15568
ff3a7cb2 15569 if (newver) {
75f9936e
MC		 15570 if (TG3_VER_SIZE - dst_off < 16 ||
15571 tg3_nvram_read(tp, offset + 8, &ver_offset))
ff3a7cb2
MC		 15572 return;
15573
15574 offset = offset + ver_offset - start;
15575 for (i = 0; i < 16; i += 4) {
15576 __be32 v;
15577 if (tg3_nvram_read_be32(tp, offset + i, &v))
15578 return;
15579
75f9936e 15580 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
ff3a7cb2
MC		 15581 }
15582 } else {
15583 u32 major, minor;
15584
15585 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15586 return;
15587
15588 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15589 TG3_NVM_BCVER_MAJSFT;
15590 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
75f9936e
MC		 15591 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15592 "v%d.%02d", major, minor);
acd9c119
MC		 15593 }
15594}
15595
229b1ad1 15596static void tg3_read_hwsb_ver(struct tg3 *tp)
a6f6cb1c
MC		 15597{
15598 u32 val, major, minor;
15599
15600 /* Use native endian representation */
15601 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15602 return;
15603
15604 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15605 TG3_NVM_HWSB_CFG1_MAJSFT;
15606 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15607 TG3_NVM_HWSB_CFG1_MINSFT;
15608
15609 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15610}
15611
229b1ad1 15612static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
dfe00d7d
MC		 15613{
15614 u32 offset, major, minor, build;
15615
75f9936e 15616 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
dfe00d7d
MC		 15617
15618 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15619 return;
15620
15621 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15622 case TG3_EEPROM_SB_REVISION_0:
15623 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15624 break;
15625 case TG3_EEPROM_SB_REVISION_2:
15626 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15627 break;
15628 case TG3_EEPROM_SB_REVISION_3:
15629 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15630 break;
a4153d40
MC		 15631 case TG3_EEPROM_SB_REVISION_4:
15632 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15633 break;
15634 case TG3_EEPROM_SB_REVISION_5:
15635 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15636 break;
bba226ac
MC		 15637 case TG3_EEPROM_SB_REVISION_6:
15638 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15639 break;
dfe00d7d
MC		 15640 default:
15641 return;
15642 }
15643
e4f34110 15644 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 15645 return;
15646
15647 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15648 TG3_EEPROM_SB_EDH_BLD_SHFT;
15649 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15650 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15651 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15652
15653 if (minor > 99 || build > 26)
15654 return;
15655
75f9936e
MC		 15656 offset = strlen(tp->fw_ver);
15657 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15658 " v%d.%02d", major, minor);
dfe00d7d
MC		 15659
15660 if (build > 0) {
75f9936e
MC		 15661 offset = strlen(tp->fw_ver);
15662 if (offset < TG3_VER_SIZE - 1)
15663 tp->fw_ver[offset] = 'a' + build - 1;
dfe00d7d
MC		 15664 }
15665}
15666
229b1ad1 15667static void tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 15668{
15669 u32 val, offset, start;
acd9c119 15670 int i, vlen;
9c8a620e
MC		 15671
15672 for (offset = TG3_NVM_DIR_START;
15673 offset < TG3_NVM_DIR_END;
15674 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 15675 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 15676 return;
15677
9c8a620e
MC		 15678 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15679 break;
15680 }
15681
15682 if (offset == TG3_NVM_DIR_END)
15683 return;
15684
63c3a66f 15685 if (!tg3_flag(tp, 5705_PLUS))
9c8a620e 15686 start = 0x08000000;
e4f34110 15687 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 15688 return;
15689
e4f34110 15690 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 15691 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 15692 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 15693 return;
15694
15695 offset += val - start;
15696
acd9c119 15697 vlen = strlen(tp->fw_ver);
9c8a620e 15698
acd9c119
MC		 15699 tp->fw_ver[vlen++] = ',';
15700 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 15701
15702 for (i = 0; i < 4; i++) {
a9dc529d
MC		 15703 __be32 v;
15704 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 15705 return;
15706
b9fc7dc5 15707 offset += sizeof(v);
c4e6575c 15708
acd9c119
MC		 15709 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15710 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 15711 break;
c4e6575c 15712 }
9c8a620e 15713
acd9c119
MC		 15714 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15715 vlen += sizeof(v);
c4e6575c 15716 }
acd9c119
MC		 15717}
15718
229b1ad1 15719static void tg3_probe_ncsi(struct tg3 *tp)
7fd76445 15720{
7fd76445 15721 u32 apedata;
7fd76445
MC		 15722
15723 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15724 if (apedata != APE_SEG_SIG_MAGIC)
15725 return;
15726
15727 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15728 if (!(apedata & APE_FW_STATUS_READY))
15729 return;
15730
165f4d1c
MC		 15731 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15732 tg3_flag_set(tp, APE_HAS_NCSI);
15733}
15734
229b1ad1 15735static void tg3_read_dash_ver(struct tg3 *tp)
165f4d1c
MC		 15736{
15737 int vlen;
15738 u32 apedata;
15739 char *fwtype;
15740
7fd76445
MC		 15741 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15742
165f4d1c 15743 if (tg3_flag(tp, APE_HAS_NCSI))
ecc79648 15744 fwtype = "NCSI";
c86a8560
MC		 15745 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15746 fwtype = "SMASH";
165f4d1c 15747 else
ecc79648
MC		 15748 fwtype = "DASH";
15749
7fd76445
MC		 15750 vlen = strlen(tp->fw_ver);
15751
ecc79648
MC		 15752 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15753 fwtype,
7fd76445
MC		 15754 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15755 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15756 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15757 (apedata & APE_FW_VERSION_BLDMSK));
15758}
15759
c86a8560
MC		 15760static void tg3_read_otp_ver(struct tg3 *tp)
15761{
15762 u32 val, val2;
15763
4153577a 15764 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c86a8560
MC		 15765 return;
15766
15767 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15768 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15769 TG3_OTP_MAGIC0_VALID(val)) {
15770 u64 val64 = (u64) val << 32 | val2;
15771 u32 ver = 0;
15772 int i, vlen;
15773
15774 for (i = 0; i < 7; i++) {
15775 if ((val64 & 0xff) == 0)
15776 break;
15777 ver = val64 & 0xff;
15778 val64 >>= 8;
15779 }
15780 vlen = strlen(tp->fw_ver);
15781 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15782 }
15783}
15784
229b1ad1 15785static void tg3_read_fw_ver(struct tg3 *tp)
acd9c119
MC		 15786{
15787 u32 val;
75f9936e 15788 bool vpd_vers = false;
acd9c119 15789
75f9936e
MC		 15790 if (tp->fw_ver[0] != 0)
15791 vpd_vers = true;
df259d8c 15792
63c3a66f 15793 if (tg3_flag(tp, NO_NVRAM)) {
75f9936e 15794 strcat(tp->fw_ver, "sb");
c86a8560 15795 tg3_read_otp_ver(tp);
df259d8c
MC		 15796 return;
15797 }
15798
acd9c119
MC		 15799 if (tg3_nvram_read(tp, 0, &val))
15800 return;
15801
15802 if (val == TG3_EEPROM_MAGIC)
15803 tg3_read_bc_ver(tp);
15804 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15805 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 15806 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15807 tg3_read_hwsb_ver(tp);
acd9c119 15808
165f4d1c
MC		 15809 if (tg3_flag(tp, ENABLE_ASF)) {
15810 if (tg3_flag(tp, ENABLE_APE)) {
15811 tg3_probe_ncsi(tp);
15812 if (!vpd_vers)
15813 tg3_read_dash_ver(tp);
15814 } else if (!vpd_vers) {
15815 tg3_read_mgmtfw_ver(tp);
15816 }
c9cab24e 15817 }
9c8a620e
MC		 15818
15819 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 15820}
15821
7cb32cf2
MC		 15822static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15823{
63c3a66f 15824 if (tg3_flag(tp, LRG_PROD_RING_CAP))
de9f5230 15825 return TG3_RX_RET_MAX_SIZE_5717;
63c3a66f 15826 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
de9f5230 15827 return TG3_RX_RET_MAX_SIZE_5700;
7cb32cf2 15828 else
de9f5230 15829 return TG3_RX_RET_MAX_SIZE_5705;
7cb32cf2
MC		 15830}
15831
4143470c 15832static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
895950c2
JP		 15833 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15834 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15835 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15836 { },
15837};
15838
229b1ad1 15839static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16c7fa7d
MC		 15840{
15841 struct pci_dev *peer;
15842 unsigned int func, devnr = tp->pdev->devfn & ~7;
15843
15844 for (func = 0; func < 8; func++) {
15845 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15846 if (peer && peer != tp->pdev)
15847 break;
15848 pci_dev_put(peer);
15849 }
15850 /* 5704 can be configured in single-port mode, set peer to
15851 * tp->pdev in that case.
15852 */
15853 if (!peer) {
15854 peer = tp->pdev;
15855 return peer;
15856 }
15857
15858 /*
15859 * We don't need to keep the refcount elevated; there's no way
15860 * to remove one half of this device without removing the other
15861 */
15862 pci_dev_put(peer);
15863
15864 return peer;
15865}
15866
229b1ad1 15867static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
42b123b1
MC		 15868{
15869 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
4153577a 15870 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
42b123b1
MC		 15871 u32 reg;
15872
15873 /* All devices that use the alternate
15874 * ASIC REV location have a CPMU.
15875 */
15876 tg3_flag_set(tp, CPMU_PRESENT);
15877
15878 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 15879 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
42b123b1
MC		 15880 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15881 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 15882 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 15883 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
15884 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 15885 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
15886 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 15887 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
15888 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
42b123b1
MC		 15889 reg = TG3PCI_GEN2_PRODID_ASICREV;
15890 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
15891 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
15892 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
15893 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
15894 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15895 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
15896 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
15897 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
15898 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
15899 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15900 reg = TG3PCI_GEN15_PRODID_ASICREV;
15901 else
15902 reg = TG3PCI_PRODID_ASICREV;
15903
15904 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
15905 }
15906
15907 /* Wrong chip ID in 5752 A0. This code can be removed later
15908 * as A0 is not in production.
15909 */
4153577a 15910 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
42b123b1
MC		 15911 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
15912
4153577a 15913 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
79d49695
MC		 15914 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
15915
4153577a
JP		 15916 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15917 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15918 tg3_asic_rev(tp) == ASIC_REV_5720)
42b123b1
MC		 15919 tg3_flag_set(tp, 5717_PLUS);
15920
4153577a
JP		 15921 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
15922 tg3_asic_rev(tp) == ASIC_REV_57766)
42b123b1
MC		 15923 tg3_flag_set(tp, 57765_CLASS);
15924
c65a17f4 15925 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
4153577a 15926 tg3_asic_rev(tp) == ASIC_REV_5762)
42b123b1
MC		 15927 tg3_flag_set(tp, 57765_PLUS);
15928
15929 /* Intentionally exclude ASIC_REV_5906 */
4153577a
JP		 15930 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
15931 tg3_asic_rev(tp) == ASIC_REV_5787 ||
15932 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15933 tg3_asic_rev(tp) == ASIC_REV_5761 ||
15934 tg3_asic_rev(tp) == ASIC_REV_5785 ||
15935 tg3_asic_rev(tp) == ASIC_REV_57780 ||
42b123b1
MC		 15936 tg3_flag(tp, 57765_PLUS))
15937 tg3_flag_set(tp, 5755_PLUS);
15938
4153577a
JP		 15939 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
15940 tg3_asic_rev(tp) == ASIC_REV_5714)
42b123b1
MC		 15941 tg3_flag_set(tp, 5780_CLASS);
15942
4153577a
JP		 15943 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
15944 tg3_asic_rev(tp) == ASIC_REV_5752 ||
15945 tg3_asic_rev(tp) == ASIC_REV_5906 ||
42b123b1
MC		 15946 tg3_flag(tp, 5755_PLUS) ||
15947 tg3_flag(tp, 5780_CLASS))
15948 tg3_flag_set(tp, 5750_PLUS);
15949
4153577a 15950 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
42b123b1
MC		 15951 tg3_flag(tp, 5750_PLUS))
15952 tg3_flag_set(tp, 5705_PLUS);
15953}
15954
3d567e0e
NNS		 15955static bool tg3_10_100_only_device(struct tg3 *tp,
15956 const struct pci_device_id *ent)
15957{
15958 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
15959
4153577a
JP		 15960 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
15961 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
3d567e0e
NNS		 15962 (tp->phy_flags & TG3_PHYFLG_IS_FET))
15963 return true;
15964
15965 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
4153577a 15966 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3d567e0e
NNS		 15967 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
15968 return true;
15969 } else {
15970 return true;
15971 }
15972 }
15973
15974 return false;
15975}
15976
1dd06ae8 15977static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
1da177e4 15978{
1da177e4 15979 u32 misc_ctrl_reg;
1da177e4
LT		 15980 u32 pci_state_reg, grc_misc_cfg;
15981 u32 val;
15982 u16 pci_cmd;
5e7dfd0f 15983 int err;
1da177e4 15984
1da177e4
LT		 15985 /* Force memory write invalidate off. If we leave it on,
15986 * then on 5700_BX chips we have to enable a workaround.
15987 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
15988 * to match the cacheline size. The Broadcom driver have this
15989 * workaround but turns MWI off all the times so never uses
15990 * it. This seems to suggest that the workaround is insufficient.
15991 */
15992 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
15993 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
15994 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
15995
16821285
MC		 15996 /* Important! -- Make sure register accesses are byteswapped
15997 * correctly. Also, for those chips that require it, make
15998 * sure that indirect register accesses are enabled before
15999 * the first operation.
1da177e4
LT		 16000 */
16001 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16002 &misc_ctrl_reg);
16821285
MC		 16003 tp->misc_host_ctrl |= (misc_ctrl_reg &
16004 MISC_HOST_CTRL_CHIPREV);
16005 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16006 tp->misc_host_ctrl);
1da177e4 16007
42b123b1 16008 tg3_detect_asic_rev(tp, misc_ctrl_reg);
ff645bec 16009
6892914f
MC		 16010 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16011 * we need to disable memory and use config. cycles
16012 * only to access all registers. The 5702/03 chips
16013 * can mistakenly decode the special cycles from the
16014 * ICH chipsets as memory write cycles, causing corruption
16015 * of register and memory space. Only certain ICH bridges
16016 * will drive special cycles with non-zero data during the
16017 * address phase which can fall within the 5703's address
16018 * range. This is not an ICH bug as the PCI spec allows
16019 * non-zero address during special cycles. However, only
16020 * these ICH bridges are known to drive non-zero addresses
16021 * during special cycles.
16022 *
16023 * Since special cycles do not cross PCI bridges, we only
16024 * enable this workaround if the 5703 is on the secondary
16025 * bus of these ICH bridges.
16026 */
4153577a
JP		 16027 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16028 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
6892914f
MC		 16029 static struct tg3_dev_id {
16030 u32 vendor;
16031 u32 device;
16032 u32 rev;
16033 } ich_chipsets[] = {
16034 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16035 PCI_ANY_ID },
16036 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16037 PCI_ANY_ID },
16038 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16039 0xa },
16040 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16041 PCI_ANY_ID },
16042 { },
16043 };
16044 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16045 struct pci_dev *bridge = NULL;
16046
16047 while (pci_id->vendor != 0) {
16048 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16049 bridge);
16050 if (!bridge) {
16051 pci_id++;
16052 continue;
16053 }
16054 if (pci_id->rev != PCI_ANY_ID) {
44c10138 16055 if (bridge->revision > pci_id->rev)
6892914f
MC		 16056 continue;
16057 }
16058 if (bridge->subordinate &&
16059 (bridge->subordinate->number ==
16060 tp->pdev->bus->number)) {
63c3a66f 16061 tg3_flag_set(tp, ICH_WORKAROUND);
6892914f
MC		 16062 pci_dev_put(bridge);
16063 break;
16064 }
16065 }
16066 }
16067
4153577a 16068 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
41588ba1
MC		 16069 static struct tg3_dev_id {
16070 u32 vendor;
16071 u32 device;
16072 } bridge_chipsets[] = {
16073 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16074 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16075 { },
16076 };
16077 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16078 struct pci_dev *bridge = NULL;
16079
16080 while (pci_id->vendor != 0) {
16081 bridge = pci_get_device(pci_id->vendor,
16082 pci_id->device,
16083 bridge);
16084 if (!bridge) {
16085 pci_id++;
16086 continue;
16087 }
16088 if (bridge->subordinate &&
16089 (bridge->subordinate->number <=
16090 tp->pdev->bus->number) &&
b918c62e 16091 (bridge->subordinate->busn_res.end >=
41588ba1 16092 tp->pdev->bus->number)) {
63c3a66f 16093 tg3_flag_set(tp, 5701_DMA_BUG);
41588ba1
MC		 16094 pci_dev_put(bridge);
16095 break;
16096 }
16097 }
16098 }
16099
4a29cc2e
MC		 16100 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16101 * DMA addresses > 40-bit. This bridge may have other additional
16102 * 57xx devices behind it in some 4-port NIC designs for example.
16103 * Any tg3 device found behind the bridge will also need the 40-bit
16104 * DMA workaround.
16105 */
42b123b1 16106 if (tg3_flag(tp, 5780_CLASS)) {
63c3a66f 16107 tg3_flag_set(tp, 40BIT_DMA_BUG);
0f847584 16108 tp->msi_cap = tp->pdev->msi_cap;
859a5887 16109 } else {
4a29cc2e
MC		 16110 struct pci_dev *bridge = NULL;
16111
16112 do {
16113 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16114 PCI_DEVICE_ID_SERVERWORKS_EPB,
16115 bridge);
16116 if (bridge && bridge->subordinate &&
16117 (bridge->subordinate->number <=
16118 tp->pdev->bus->number) &&
b918c62e 16119 (bridge->subordinate->busn_res.end >=
4a29cc2e 16120 tp->pdev->bus->number)) {
63c3a66f 16121 tg3_flag_set(tp, 40BIT_DMA_BUG);
4a29cc2e
MC		 16122 pci_dev_put(bridge);
16123 break;
16124 }
16125 } while (bridge);
16126 }
4cf78e4f 16127
4153577a
JP		 16128 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16129 tg3_asic_rev(tp) == ASIC_REV_5714)
7544b097
MC		 16130 tp->pdev_peer = tg3_find_peer(tp);
16131
507399f1 16132 /* Determine TSO capabilities */
4153577a 16133 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
4d163b75 16134 ; /* Do nothing. HW bug. */
63c3a66f
JP		 16135 else if (tg3_flag(tp, 57765_PLUS))
16136 tg3_flag_set(tp, HW_TSO_3);
16137 else if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16138 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f
JP		 16139 tg3_flag_set(tp, HW_TSO_2);
16140 else if (tg3_flag(tp, 5750_PLUS)) {
16141 tg3_flag_set(tp, HW_TSO_1);
16142 tg3_flag_set(tp, TSO_BUG);
4153577a
JP		 16143 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16144 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
63c3a66f 16145 tg3_flag_clear(tp, TSO_BUG);
4153577a
JP		 16146 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16147 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16148 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
1caf13eb
MC		 16149 tg3_flag_set(tp, FW_TSO);
16150 tg3_flag_set(tp, TSO_BUG);
4153577a 16151 if (tg3_asic_rev(tp) == ASIC_REV_5705)
507399f1
MC		 16152 tp->fw_needed = FIRMWARE_TG3TSO5;
16153 else
16154 tp->fw_needed = FIRMWARE_TG3TSO;
16155 }
16156
dabc5c67 16157 /* Selectively allow TSO based on operating conditions */
6ff6f81d
MC		 16158 if (tg3_flag(tp, HW_TSO_1) ||
16159 tg3_flag(tp, HW_TSO_2) ||
16160 tg3_flag(tp, HW_TSO_3) ||
1caf13eb 16161 tg3_flag(tp, FW_TSO)) {
cf9ecf4b
MC		 16162 /* For firmware TSO, assume ASF is disabled.
16163 * We'll disable TSO later if we discover ASF
16164 * is enabled in tg3_get_eeprom_hw_cfg().
16165 */
dabc5c67 16166 tg3_flag_set(tp, TSO_CAPABLE);
cf9ecf4b 16167 } else {
dabc5c67
MC		 16168 tg3_flag_clear(tp, TSO_CAPABLE);
16169 tg3_flag_clear(tp, TSO_BUG);
16170 tp->fw_needed = NULL;
16171 }
16172
4153577a 16173 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
dabc5c67
MC		 16174 tp->fw_needed = FIRMWARE_TG3;
16175
c4dab506
NS		 16176 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16177 tp->fw_needed = FIRMWARE_TG357766;
16178
507399f1
MC		 16179 tp->irq_max = 1;
16180
63c3a66f
JP		 16181 if (tg3_flag(tp, 5750_PLUS)) {
16182 tg3_flag_set(tp, SUPPORT_MSI);
4153577a
JP		 16183 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16184 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16185 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16186 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
7544b097 16187 tp->pdev_peer == tp->pdev))
63c3a66f 16188 tg3_flag_clear(tp, SUPPORT_MSI);
7544b097 16189
63c3a66f 16190 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16191 tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16192 tg3_flag_set(tp, 1SHOT_MSI);
52c0fd83 16193 }
4f125f42 16194
63c3a66f
JP		 16195 if (tg3_flag(tp, 57765_PLUS)) {
16196 tg3_flag_set(tp, SUPPORT_MSIX);
507399f1
MC		 16197 tp->irq_max = TG3_IRQ_MAX_VECS;
16198 }
f6eb9b1f 16199 }
0e1406dd 16200
9102426a
MC		 16201 tp->txq_max = 1;
16202 tp->rxq_max = 1;
16203 if (tp->irq_max > 1) {
16204 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16205 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16206
4153577a
JP		 16207 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16208 tg3_asic_rev(tp) == ASIC_REV_5720)
9102426a
MC		 16209 tp->txq_max = tp->irq_max - 1;
16210 }
16211
b7abee6e 16212 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16213 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f 16214 tg3_flag_set(tp, SHORT_DMA_BUG);
f6eb9b1f 16215
4153577a 16216 if (tg3_asic_rev(tp) == ASIC_REV_5719)
a4cb428d 16217 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
e31aa987 16218
4153577a
JP		 16219 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16220 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16221 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16222 tg3_asic_rev(tp) == ASIC_REV_5762)
63c3a66f 16223 tg3_flag_set(tp, LRG_PROD_RING_CAP);
de9f5230 16224
63c3a66f 16225 if (tg3_flag(tp, 57765_PLUS) &&
4153577a 16226 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
63c3a66f 16227 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
b703df6f 16228
63c3a66f
JP		 16229 if (!tg3_flag(tp, 5705_PLUS) ||
16230 tg3_flag(tp, 5780_CLASS) ||
16231 tg3_flag(tp, USE_JUMBO_BDFLAG))
16232 tg3_flag_set(tp, JUMBO_CAPABLE);
0f893dc6 16233
52f4490c
MC		 16234 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16235 &pci_state_reg);
16236
708ebb3a 16237 if (pci_is_pcie(tp->pdev)) {
5e7dfd0f
MC		 16238 u16 lnkctl;
16239
63c3a66f 16240 tg3_flag_set(tp, PCI_EXPRESS);
5f5c51e3 16241
0f49bfbd 16242 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
5e7dfd0f 16243 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
4153577a 16244 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16245 tg3_flag_clear(tp, HW_TSO_2);
dabc5c67 16246 tg3_flag_clear(tp, TSO_CAPABLE);
7196cd6c 16247 }
4153577a
JP		 16248 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16249 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16250 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16251 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
63c3a66f 16252 tg3_flag_set(tp, CLKREQ_BUG);
4153577a 16253 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
63c3a66f 16254 tg3_flag_set(tp, L1PLLPD_EN);
c7835a77 16255 }
4153577a 16256 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
708ebb3a
JM		 16257 /* BCM5785 devices are effectively PCIe devices, and should
16258 * follow PCIe codepaths, but do not have a PCIe capabilities
16259 * section.
93a700a9 16260 */
63c3a66f
JP		 16261 tg3_flag_set(tp, PCI_EXPRESS);
16262 } else if (!tg3_flag(tp, 5705_PLUS) ||
16263 tg3_flag(tp, 5780_CLASS)) {
52f4490c
MC		 16264 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16265 if (!tp->pcix_cap) {
2445e461
MC		 16266 dev_err(&tp->pdev->dev,
16267 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 16268 return -EIO;
16269 }
16270
16271 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
63c3a66f 16272 tg3_flag_set(tp, PCIX_MODE);
52f4490c 16273 }
1da177e4 16274
399de50b
MC		 16275 /* If we have an AMD 762 or VIA K8T800 chipset, write
16276 * reordering to the mailbox registers done by the host
16277 * controller can cause major troubles. We read back from
16278 * every mailbox register write to force the writes to be
16279 * posted to the chip in order.
16280 */
4143470c 16281 if (pci_dev_present(tg3_write_reorder_chipsets) &&
63c3a66f
JP		 16282 !tg3_flag(tp, PCI_EXPRESS))
16283 tg3_flag_set(tp, MBOX_WRITE_REORDER);
399de50b 16284
69fc4053
MC		 16285 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16286 &tp->pci_cacheline_sz);
16287 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16288 &tp->pci_lat_timer);
4153577a 16289 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
1da177e4
LT		 16290 tp->pci_lat_timer < 64) {
16291 tp->pci_lat_timer = 64;
69fc4053
MC		 16292 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16293 tp->pci_lat_timer);
1da177e4
LT		 16294 }
16295
16821285
MC		 16296 /* Important! -- It is critical that the PCI-X hw workaround
16297 * situation is decided before the first MMIO register access.
16298 */
4153577a 16299 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
52f4490c
MC		 16300 /* 5700 BX chips need to have their TX producer index
16301 * mailboxes written twice to workaround a bug.
16302 */
63c3a66f 16303 tg3_flag_set(tp, TXD_MBOX_HWBUG);
1da177e4 16304
52f4490c 16305 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 16306 *
16307 * The workaround is to use indirect register accesses
16308 * for all chip writes not to mailbox registers.
16309 */
63c3a66f 16310 if (tg3_flag(tp, PCIX_MODE)) {
1da177e4 16311 u32 pm_reg;
1da177e4 16312
63c3a66f 16313 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16314
16315 /* The chip can have it's power management PCI config
16316 * space registers clobbered due to this bug.
16317 * So explicitly force the chip into D0 here.
16318 */
9974a356 16319 pci_read_config_dword(tp->pdev,
0319f30e 16320 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16321 &pm_reg);
16322 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16323 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356 16324 pci_write_config_dword(tp->pdev,
0319f30e 16325 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16326 pm_reg);
16327
16328 /* Also, force SERR#/PERR# in PCI command. */
16329 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16330 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16331 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16332 }
16333 }
16334
1da177e4 16335 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
63c3a66f 16336 tg3_flag_set(tp, PCI_HIGH_SPEED);
1da177e4 16337 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
63c3a66f 16338 tg3_flag_set(tp, PCI_32BIT);
1da177e4
LT		 16339
16340 /* Chip-specific fixup from Broadcom driver */
4153577a 16341 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
1da177e4
LT		 16342 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16343 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16344 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16345 }
16346
1ee582d8 16347 /* Default fast path register access methods */
20094930 16348 tp->read32 = tg3_read32;
1ee582d8 16349 tp->write32 = tg3_write32;
09ee929c 16350 tp->read32_mbox = tg3_read32;
20094930 16351 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 16352 tp->write32_tx_mbox = tg3_write32;
16353 tp->write32_rx_mbox = tg3_write32;
16354
16355 /* Various workaround register access methods */
63c3a66f 16356 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
1ee582d8 16357 tp->write32 = tg3_write_indirect_reg32;
4153577a 16358 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
63c3a66f 16359 (tg3_flag(tp, PCI_EXPRESS) &&
4153577a 16360 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
98efd8a6
MC		 16361 /*
16362 * Back to back register writes can cause problems on these
16363 * chips, the workaround is to read back all reg writes
16364 * except those to mailbox regs.
16365 *
16366 * See tg3_write_indirect_reg32().
16367 */
1ee582d8 16368 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 16369 }
16370
63c3a66f 16371 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
1ee582d8 16372 tp->write32_tx_mbox = tg3_write32_tx_mbox;
63c3a66f 16373 if (tg3_flag(tp, MBOX_WRITE_REORDER))
1ee582d8
MC		 16374 tp->write32_rx_mbox = tg3_write_flush_reg32;
16375 }
20094930 16376
63c3a66f 16377 if (tg3_flag(tp, ICH_WORKAROUND)) {
6892914f
MC		 16378 tp->read32 = tg3_read_indirect_reg32;
16379 tp->write32 = tg3_write_indirect_reg32;
16380 tp->read32_mbox = tg3_read_indirect_mbox;
16381 tp->write32_mbox = tg3_write_indirect_mbox;
16382 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16383 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16384
16385 iounmap(tp->regs);
22abe310 16386 tp->regs = NULL;
6892914f
MC		 16387
16388 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16389 pci_cmd &= ~PCI_COMMAND_MEMORY;
16390 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16391 }
4153577a 16392 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 16393 tp->read32_mbox = tg3_read32_mbox_5906;
16394 tp->write32_mbox = tg3_write32_mbox_5906;
16395 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16396 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16397 }
6892914f 16398
bbadf503 16399 if (tp->write32 == tg3_write_indirect_reg32 ||
63c3a66f 16400 (tg3_flag(tp, PCIX_MODE) &&
4153577a
JP		 16401 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16402 tg3_asic_rev(tp) == ASIC_REV_5701)))
63c3a66f 16403 tg3_flag_set(tp, SRAM_USE_CONFIG);
bbadf503 16404
16821285
MC		 16405 /* The memory arbiter has to be enabled in order for SRAM accesses
16406 * to succeed. Normally on powerup the tg3 chip firmware will make
16407 * sure it is enabled, but other entities such as system netboot
16408 * code might disable it.
16409 */
16410 val = tr32(MEMARB_MODE);
16411 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16412
9dc5e342 16413 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
4153577a 16414 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
9dc5e342
MC		 16415 tg3_flag(tp, 5780_CLASS)) {
16416 if (tg3_flag(tp, PCIX_MODE)) {
16417 pci_read_config_dword(tp->pdev,
16418 tp->pcix_cap + PCI_X_STATUS,
16419 &val);
16420 tp->pci_fn = val & 0x7;
16421 }
4153577a
JP		 16422 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16423 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16424 tg3_asic_rev(tp) == ASIC_REV_5720) {
9dc5e342 16425 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
857001f0
MC		 16426 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16427 val = tr32(TG3_CPMU_STATUS);
16428
4153577a 16429 if (tg3_asic_rev(tp) == ASIC_REV_5717)
857001f0
MC		 16430 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16431 else
9dc5e342
MC		 16432 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16433 TG3_CPMU_STATUS_FSHFT_5719;
69f11c99
MC		 16434 }
16435
7e6c63f0
HM		 16436 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16437 tp->write32_tx_mbox = tg3_write_flush_reg32;
16438 tp->write32_rx_mbox = tg3_write_flush_reg32;
16439 }
16440
7d0c41ef 16441 /* Get eeprom hw config before calling tg3_set_power_state().
63c3a66f 16442 * In particular, the TG3_FLAG_IS_NIC flag must be
7d0c41ef
MC		 16443 * determined before calling tg3_set_power_state() so that
16444 * we know whether or not to switch out of Vaux power.
16445 * When the flag is set, it means that GPIO1 is used for eeprom
16446 * write protect and also implies that it is a LOM where GPIOs
16447 * are not used to switch power.
6aa20a22 16448 */
7d0c41ef
MC		 16449 tg3_get_eeprom_hw_cfg(tp);
16450
1caf13eb 16451 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
cf9ecf4b
MC		 16452 tg3_flag_clear(tp, TSO_CAPABLE);
16453 tg3_flag_clear(tp, TSO_BUG);
16454 tp->fw_needed = NULL;
16455 }
16456
63c3a66f 16457 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 16458 /* Allow reads and writes to the
16459 * APE register and memory space.
16460 */
16461 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 16462 PCISTATE_ALLOW_APE_SHMEM_WR |
16463 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 16464 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16465 pci_state_reg);
c9cab24e
MC		 16466
16467 tg3_ape_lock_init(tp);
0d3031d9
MC		 16468 }
16469
16821285
MC		 16470 /* Set up tp->grc_local_ctrl before calling
16471 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16472 * will bring 5700's external PHY out of reset.
314fba34
MC		 16473 * It is also used as eeprom write protect on LOMs.
16474 */
16475 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
4153577a 16476 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
63c3a66f 16477 tg3_flag(tp, EEPROM_WRITE_PROT))
314fba34
MC		 16478 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16479 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 16480 /* Unused GPIO3 must be driven as output on 5752 because there
16481 * are no pull-up resistors on unused GPIO pins.
16482 */
4153577a 16483 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc 16484 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 16485
4153577a
JP		 16486 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16487 tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 16488 tg3_flag(tp, 57765_CLASS))
af36e6b6
MC		 16489 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16490
8d519ab2
MC		 16491 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16492 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 16493 /* Turn off the debug UART. */
16494 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
63c3a66f 16495 if (tg3_flag(tp, IS_NIC))
5f0c4a3c
MC		 16496 /* Keep VMain power. */
16497 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16498 GRC_LCLCTRL_GPIO_OUTPUT0;
16499 }
16500
4153577a 16501 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c86a8560
MC		 16502 tp->grc_local_ctrl |=
16503 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16504
16821285
MC		 16505 /* Switch out of Vaux if it is a NIC */
16506 tg3_pwrsrc_switch_to_vmain(tp);
1da177e4 16507
1da177e4
LT		 16508 /* Derive initial jumbo mode from MTU assigned in
16509 * ether_setup() via the alloc_etherdev() call
16510 */
63c3a66f
JP		 16511 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16512 tg3_flag_set(tp, JUMBO_RING_ENABLE);
1da177e4
LT		 16513
16514 /* Determine WakeOnLan speed to use. */
4153577a
JP		 16515 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16516 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16517 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16518 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
63c3a66f 16519 tg3_flag_clear(tp, WOL_SPEED_100MB);
1da177e4 16520 } else {
63c3a66f 16521 tg3_flag_set(tp, WOL_SPEED_100MB);
1da177e4
LT		 16522 }
16523
4153577a 16524 if (tg3_asic_rev(tp) == ASIC_REV_5906)
f07e9af3 16525 tp->phy_flags |= TG3_PHYFLG_IS_FET;
7f97a4bd 16526
1da177e4 16527 /* A few boards don't want Ethernet@WireSpeed phy feature */
4153577a
JP		 16528 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16529 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16530 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16531 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
f07e9af3
MC		 16532 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16533 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16534 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
1da177e4 16535
4153577a
JP		 16536 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16537 tg3_chip_rev(tp) == CHIPREV_5704_AX)
f07e9af3 16538 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
4153577a 16539 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
f07e9af3 16540 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
1da177e4 16541
63c3a66f 16542 if (tg3_flag(tp, 5705_PLUS) &&
f07e9af3 16543 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a
JP		 16544 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16545 tg3_asic_rev(tp) != ASIC_REV_57780 &&
63c3a66f 16546 !tg3_flag(tp, 57765_PLUS)) {
4153577a
JP		 16547 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16548 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16549 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16550 tg3_asic_rev(tp) == ASIC_REV_5761) {
d4011ada
MC		 16551 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16552 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
f07e9af3 16553 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
c1d2a196 16554 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
f07e9af3 16555 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
321d32a0 16556 } else
f07e9af3 16557 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
c424cb24 16558 }
1da177e4 16559
4153577a
JP		 16560 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16561 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 16562 tp->phy_otp = tg3_read_otp_phycfg(tp);
16563 if (tp->phy_otp == 0)
16564 tp->phy_otp = TG3_OTP_DEFAULT;
16565 }
16566
63c3a66f 16567 if (tg3_flag(tp, CPMU_PRESENT))
8ef21428
MC		 16568 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16569 else
16570 tp->mi_mode = MAC_MI_MODE_BASE;
16571
1da177e4 16572 tp->coalesce_mode = 0;
4153577a
JP		 16573 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16574 tg3_chip_rev(tp) != CHIPREV_5700_BX)
1da177e4
LT		 16575 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16576
4d958473 16577 /* Set these bits to enable statistics workaround. */
4153577a 16578 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
94962f7f 16579 tg3_asic_rev(tp) == ASIC_REV_5762 ||
4153577a
JP		 16580 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16581 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
4d958473
MC		 16582 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16583 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16584 }
16585
4153577a
JP		 16586 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16587 tg3_asic_rev(tp) == ASIC_REV_57780)
63c3a66f 16588 tg3_flag_set(tp, USE_PHYLIB);
57e6983c 16589
158d7abd
MC		 16590 err = tg3_mdio_init(tp);
16591 if (err)
16592 return err;
1da177e4
LT		 16593
16594 /* Initialize data/descriptor byte/word swapping. */
16595 val = tr32(GRC_MODE);
4153577a
JP		 16596 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16597 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 16598 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16599 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16600 GRC_MODE_B2HRX_ENABLE |
16601 GRC_MODE_HTX2B_ENABLE |
16602 GRC_MODE_HOST_STACKUP);
16603 else
16604 val &= GRC_MODE_HOST_STACKUP;
16605
1da177e4
LT		 16606 tw32(GRC_MODE, val | tp->grc_mode);
16607
16608 tg3_switch_clocks(tp);
16609
16610 /* Clear this out for sanity. */
16611 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16612
388d3335
NG		 16613 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16614 tw32(TG3PCI_REG_BASE_ADDR, 0);
16615
1da177e4
LT		 16616 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16617 &pci_state_reg);
16618 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
63c3a66f 16619 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
4153577a
JP		 16620 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16621 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16622 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16623 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
1da177e4
LT		 16624 void __iomem *sram_base;
16625
16626 /* Write some dummy words into the SRAM status block
16627 * area, see if it reads back correctly. If the return
16628 * value is bad, force enable the PCIX workaround.
16629 */
16630 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16631
16632 writel(0x00000000, sram_base);
16633 writel(0x00000000, sram_base + 4);
16634 writel(0xffffffff, sram_base + 4);
16635 if (readl(sram_base) != 0x00000000)
63c3a66f 16636 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16637 }
16638 }
16639
16640 udelay(50);
16641 tg3_nvram_init(tp);
16642
c4dab506
NS		 16643 /* If the device has an NVRAM, no need to load patch firmware */
16644 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16645 !tg3_flag(tp, NO_NVRAM))
16646 tp->fw_needed = NULL;
16647
1da177e4
LT		 16648 grc_misc_cfg = tr32(GRC_MISC_CFG);
16649 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16650
4153577a 16651 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
1da177e4
LT		 16652 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16653 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
63c3a66f 16654 tg3_flag_set(tp, IS_5788);
1da177e4 16655
63c3a66f 16656 if (!tg3_flag(tp, IS_5788) &&
4153577a 16657 tg3_asic_rev(tp) != ASIC_REV_5700)
63c3a66f
JP		 16658 tg3_flag_set(tp, TAGGED_STATUS);
16659 if (tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 16660 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16661 HOSTCC_MODE_CLRTICK_TXBD);
16662
16663 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16664 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16665 tp->misc_host_ctrl);
16666 }
16667
3bda1258 16668 /* Preserve the APE MAC_MODE bits */
63c3a66f 16669 if (tg3_flag(tp, ENABLE_APE))
d2394e6b 16670 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
3bda1258 16671 else
6e01b20b 16672 tp->mac_mode = 0;
3bda1258 16673
3d567e0e 16674 if (tg3_10_100_only_device(tp, ent))
f07e9af3 16675 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
1da177e4
LT		 16676
16677 err = tg3_phy_probe(tp);
16678 if (err) {
2445e461 16679 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 16680 /* ... but do not return immediately ... */
b02fd9e3 16681 tg3_mdio_fini(tp);
1da177e4
LT		 16682 }
16683
184b8904 16684 tg3_read_vpd(tp);
c4e6575c 16685 tg3_read_fw_ver(tp);
1da177e4 16686
f07e9af3
MC		 16687 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16688 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16689 } else {
4153577a 16690 if (tg3_asic_rev(tp) == ASIC_REV_5700)
f07e9af3 16691 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16692 else
f07e9af3 16693 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4
LT		 16694 }
16695
16696 /* 5700 {AX,BX} chips have a broken status block link
16697 * change bit implementation, so we must use the
16698 * status register in those cases.
16699 */
4153577a 16700 if (tg3_asic_rev(tp) == ASIC_REV_5700)
63c3a66f 16701 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4 16702 else
63c3a66f 16703 tg3_flag_clear(tp, USE_LINKCHG_REG);
1da177e4
LT		 16704
16705 /* The led_ctrl is set during tg3_phy_probe, here we might
16706 * have to force the link status polling mechanism based
16707 * upon subsystem IDs.
16708 */
16709 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
4153577a 16710 tg3_asic_rev(tp) == ASIC_REV_5701 &&
f07e9af3
MC		 16711 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16712 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
63c3a66f 16713 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4
LT		 16714 }
16715
16716 /* For all SERDES we poll the MAC status register. */
f07e9af3 16717 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
63c3a66f 16718 tg3_flag_set(tp, POLL_SERDES);
1da177e4 16719 else
63c3a66f 16720 tg3_flag_clear(tp, POLL_SERDES);
1da177e4 16721
9205fd9c 16722 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
d2757fc4 16723 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
4153577a 16724 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
63c3a66f 16725 tg3_flag(tp, PCIX_MODE)) {
9205fd9c 16726 tp->rx_offset = NET_SKB_PAD;
d2757fc4 16727#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
9dc7a113 16728 tp->rx_copy_thresh = ~(u16)0;
d2757fc4
MC		 16729#endif
16730 }
1da177e4 16731
2c49a44d
MC		 16732 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16733 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
7cb32cf2
MC		 16734 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16735
2c49a44d 16736 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
f92905de
MC		 16737
16738 /* Increment the rx prod index on the rx std ring by at most
16739 * 8 for these chips to workaround hw errata.
16740 */
4153577a
JP		 16741 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16742 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16743 tg3_asic_rev(tp) == ASIC_REV_5755)
f92905de
MC		 16744 tp->rx_std_max_post = 8;
16745
63c3a66f 16746 if (tg3_flag(tp, ASPM_WORKAROUND))
8ed5d97e
MC		 16747 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16748 PCIE_PWR_MGMT_L1_THRESH_MSK;
16749
1da177e4
LT		 16750 return err;
16751}
16752
49b6e95f 16753#ifdef CONFIG_SPARC
229b1ad1 16754static int tg3_get_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16755{
16756 struct net_device *dev = tp->dev;
16757 struct pci_dev *pdev = tp->pdev;
49b6e95f 16758 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 16759 const unsigned char *addr;
49b6e95f
DM		 16760 int len;
16761
16762 addr = of_get_property(dp, "local-mac-address", &len);
d458cdf7
JP		 16763 if (addr && len == ETH_ALEN) {
16764 memcpy(dev->dev_addr, addr, ETH_ALEN);
49b6e95f 16765 return 0;
1da177e4
LT		 16766 }
16767 return -ENODEV;
16768}
16769
229b1ad1 16770static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16771{
16772 struct net_device *dev = tp->dev;
16773
d458cdf7 16774 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
1da177e4
LT		 16775 return 0;
16776}
16777#endif
16778
229b1ad1 16779static int tg3_get_device_address(struct tg3 *tp)
1da177e4
LT		 16780{
16781 struct net_device *dev = tp->dev;
16782 u32 hi, lo, mac_offset;
008652b3 16783 int addr_ok = 0;
7e6c63f0 16784 int err;
1da177e4 16785
49b6e95f 16786#ifdef CONFIG_SPARC
1da177e4
LT		 16787 if (!tg3_get_macaddr_sparc(tp))
16788 return 0;
16789#endif
16790
7e6c63f0
HM		 16791 if (tg3_flag(tp, IS_SSB_CORE)) {
16792 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16793 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16794 return 0;
16795 }
16796
1da177e4 16797 mac_offset = 0x7c;
4153577a 16798 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
63c3a66f 16799 tg3_flag(tp, 5780_CLASS)) {
1da177e4
LT		 16800 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16801 mac_offset = 0xcc;
16802 if (tg3_nvram_lock(tp))
16803 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16804 else
16805 tg3_nvram_unlock(tp);
63c3a66f 16806 } else if (tg3_flag(tp, 5717_PLUS)) {
69f11c99 16807 if (tp->pci_fn & 1)
a1b950d5 16808 mac_offset = 0xcc;
69f11c99 16809 if (tp->pci_fn > 1)
a50d0796 16810 mac_offset += 0x18c;
4153577a 16811 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 16812 mac_offset = 0x10;
1da177e4
LT		 16813
16814 /* First try to get it from MAC address mailbox. */
16815 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16816 if ((hi >> 16) == 0x484b) {
16817 dev->dev_addr[0] = (hi >> 8) & 0xff;
16818 dev->dev_addr[1] = (hi >> 0) & 0xff;
16819
16820 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16821 dev->dev_addr[2] = (lo >> 24) & 0xff;
16822 dev->dev_addr[3] = (lo >> 16) & 0xff;
16823 dev->dev_addr[4] = (lo >> 8) & 0xff;
16824 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 16825
008652b3
MC		 16826 /* Some old bootcode may report a 0 MAC address in SRAM */
16827 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16828 }
16829 if (!addr_ok) {
16830 /* Next, try NVRAM. */
63c3a66f 16831 if (!tg3_flag(tp, NO_NVRAM) &&
df259d8c 16832 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 16833 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 16834 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16835 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 16836 }
16837 /* Finally just fetch it out of the MAC control regs. */
16838 else {
16839 hi = tr32(MAC_ADDR_0_HIGH);
16840 lo = tr32(MAC_ADDR_0_LOW);
16841
16842 dev->dev_addr[5] = lo & 0xff;
16843 dev->dev_addr[4] = (lo >> 8) & 0xff;
16844 dev->dev_addr[3] = (lo >> 16) & 0xff;
16845 dev->dev_addr[2] = (lo >> 24) & 0xff;
16846 dev->dev_addr[1] = hi & 0xff;
16847 dev->dev_addr[0] = (hi >> 8) & 0xff;
16848 }
1da177e4
LT		 16849 }
16850
16851 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 16852#ifdef CONFIG_SPARC
1da177e4
LT		 16853 if (!tg3_get_default_macaddr_sparc(tp))
16854 return 0;
16855#endif
16856 return -EINVAL;
16857 }
16858 return 0;
16859}
16860
59e6b434
DM		 16861#define BOUNDARY_SINGLE_CACHELINE 1
16862#define BOUNDARY_MULTI_CACHELINE 2
16863
229b1ad1 16864static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
59e6b434
DM		 16865{
16866 int cacheline_size;
16867 u8 byte;
16868 int goal;
16869
16870 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
16871 if (byte == 0)
16872 cacheline_size = 1024;
16873 else
16874 cacheline_size = (int) byte * 4;
16875
16876 /* On 5703 and later chips, the boundary bits have no
16877 * effect.
16878 */
4153577a
JP		 16879 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16880 tg3_asic_rev(tp) != ASIC_REV_5701 &&
63c3a66f 16881 !tg3_flag(tp, PCI_EXPRESS))
59e6b434
DM		 16882 goto out;
16883
16884#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
16885 goal = BOUNDARY_MULTI_CACHELINE;
16886#else
16887#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
16888 goal = BOUNDARY_SINGLE_CACHELINE;
16889#else
16890 goal = 0;
16891#endif
16892#endif
16893
63c3a66f 16894 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 16895 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
16896 goto out;
16897 }
16898
59e6b434
DM		 16899 if (!goal)
16900 goto out;
16901
16902 /* PCI controllers on most RISC systems tend to disconnect
16903 * when a device tries to burst across a cache-line boundary.
16904 * Therefore, letting tg3 do so just wastes PCI bandwidth.
16905 *
16906 * Unfortunately, for PCI-E there are only limited
16907 * write-side controls for this, and thus for reads
16908 * we will still get the disconnects. We'll also waste
16909 * these PCI cycles for both read and write for chips
16910 * other than 5700 and 5701 which do not implement the
16911 * boundary bits.
16912 */
63c3a66f 16913 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16914 switch (cacheline_size) {
16915 case 16:
16916 case 32:
16917 case 64:
16918 case 128:
16919 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16920 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
16921 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
16922 } else {
16923 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16924 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16925 }
16926 break;
16927
16928 case 256:
16929 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
16930 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
16931 break;
16932
16933 default:
16934 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16935 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16936 break;
855e1111 16937 }
63c3a66f 16938 } else if (tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16939 switch (cacheline_size) {
16940 case 16:
16941 case 32:
16942 case 64:
16943 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16944 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16945 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
16946 break;
16947 }
16948 /* fallthrough */
16949 case 128:
16950 default:
16951 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16952 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
16953 break;
855e1111 16954 }
59e6b434
DM		 16955 } else {
16956 switch (cacheline_size) {
16957 case 16:
16958 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16959 val |= (DMA_RWCTRL_READ_BNDRY_16 |
16960 DMA_RWCTRL_WRITE_BNDRY_16);
16961 break;
16962 }
16963 /* fallthrough */
16964 case 32:
16965 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16966 val |= (DMA_RWCTRL_READ_BNDRY_32 |
16967 DMA_RWCTRL_WRITE_BNDRY_32);
16968 break;
16969 }
16970 /* fallthrough */
16971 case 64:
16972 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16973 val |= (DMA_RWCTRL_READ_BNDRY_64 |
16974 DMA_RWCTRL_WRITE_BNDRY_64);
16975 break;
16976 }
16977 /* fallthrough */
16978 case 128:
16979 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16980 val |= (DMA_RWCTRL_READ_BNDRY_128 |
16981 DMA_RWCTRL_WRITE_BNDRY_128);
16982 break;
16983 }
16984 /* fallthrough */
16985 case 256:
16986 val |= (DMA_RWCTRL_READ_BNDRY_256 |
16987 DMA_RWCTRL_WRITE_BNDRY_256);
16988 break;
16989 case 512:
16990 val |= (DMA_RWCTRL_READ_BNDRY_512 |
16991 DMA_RWCTRL_WRITE_BNDRY_512);
16992 break;
16993 case 1024:
16994 default:
16995 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
16996 DMA_RWCTRL_WRITE_BNDRY_1024);
16997 break;
855e1111 16998 }
59e6b434
DM		 16999 }
17000
17001out:
17002 return val;
17003}
17004
229b1ad1 17005static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
953c96e0 17006 int size, bool to_device)
1da177e4
LT		 17007{
17008 struct tg3_internal_buffer_desc test_desc;
17009 u32 sram_dma_descs;
17010 int i, ret;
17011
17012 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17013
17014 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17015 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17016 tw32(RDMAC_STATUS, 0);
17017 tw32(WDMAC_STATUS, 0);
17018
17019 tw32(BUFMGR_MODE, 0);
17020 tw32(FTQ_RESET, 0);
17021
17022 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17023 test_desc.addr_lo = buf_dma & 0xffffffff;
17024 test_desc.nic_mbuf = 0x00002100;
17025 test_desc.len = size;
17026
17027 /*
17028 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17029 * the *second* time the tg3 driver was getting loaded after an
17030 * initial scan.
17031 *
17032 * Broadcom tells me:
17033 * ...the DMA engine is connected to the GRC block and a DMA
17034 * reset may affect the GRC block in some unpredictable way...
17035 * The behavior of resets to individual blocks has not been tested.
17036 *
17037 * Broadcom noted the GRC reset will also reset all sub-components.
17038 */
17039 if (to_device) {
17040 test_desc.cqid_sqid = (13 << 8) | 2;
17041
17042 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17043 udelay(40);
17044 } else {
17045 test_desc.cqid_sqid = (16 << 8) | 7;
17046
17047 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17048 udelay(40);
17049 }
17050 test_desc.flags = 0x00000005;
17051
17052 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17053 u32 val;
17054
17055 val = *(((u32 *)&test_desc) + i);
17056 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17057 sram_dma_descs + (i * sizeof(u32)));
17058 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17059 }
17060 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17061
859a5887 17062 if (to_device)
1da177e4 17063 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
859a5887 17064 else
1da177e4 17065 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
1da177e4
LT		 17066
17067 ret = -ENODEV;
17068 for (i = 0; i < 40; i++) {
17069 u32 val;
17070
17071 if (to_device)
17072 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17073 else
17074 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17075 if ((val & 0xffff) == sram_dma_descs) {
17076 ret = 0;
17077 break;
17078 }
17079
17080 udelay(100);
17081 }
17082
17083 return ret;
17084}
17085
ded7340d 17086#define TEST_BUFFER_SIZE 0x2000
1da177e4 17087
4143470c 17088static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
895950c2
JP		 17089 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17090 { },
17091};
17092
229b1ad1 17093static int tg3_test_dma(struct tg3 *tp)
1da177e4
LT		 17094{
17095 dma_addr_t buf_dma;
59e6b434 17096 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 17097 int ret = 0;
1da177e4 17098
4bae65c8
MC		 17099 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17100 &buf_dma, GFP_KERNEL);
1da177e4
LT		 17101 if (!buf) {
17102 ret = -ENOMEM;
17103 goto out_nofree;
17104 }
17105
17106 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17107 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17108
59e6b434 17109 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 17110
63c3a66f 17111 if (tg3_flag(tp, 57765_PLUS))
cbf9ca6c
MC		 17112 goto out;
17113
63c3a66f 17114 if (tg3_flag(tp, PCI_EXPRESS)) {
1da177e4
LT		 17115 /* DMA read watermark not used on PCIE */
17116 tp->dma_rwctrl |= 0x00180000;
63c3a66f 17117 } else if (!tg3_flag(tp, PCIX_MODE)) {
4153577a
JP		 17118 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17119 tg3_asic_rev(tp) == ASIC_REV_5750)
1da177e4
LT		 17120 tp->dma_rwctrl |= 0x003f0000;
17121 else
17122 tp->dma_rwctrl |= 0x003f000f;
17123 } else {
4153577a
JP		 17124 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17125 tg3_asic_rev(tp) == ASIC_REV_5704) {
1da177e4 17126 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 17127 u32 read_water = 0x7;
1da177e4 17128
4a29cc2e
MC		 17129 /* If the 5704 is behind the EPB bridge, we can
17130 * do the less restrictive ONE_DMA workaround for
17131 * better performance.
17132 */
63c3a66f 17133 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
4153577a 17134 tg3_asic_rev(tp) == ASIC_REV_5704)
4a29cc2e
MC		 17135 tp->dma_rwctrl |= 0x8000;
17136 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 17137 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17138
4153577a 17139 if (tg3_asic_rev(tp) == ASIC_REV_5703)
49afdeb6 17140 read_water = 4;
59e6b434 17141 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 17142 tp->dma_rwctrl |=
17143 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17144 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17145 (1 << 23);
4153577a 17146 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
4cf78e4f
MC		 17147 /* 5780 always in PCIX mode */
17148 tp->dma_rwctrl |= 0x00144000;
4153577a 17149 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
a4e2b347
MC		 17150 /* 5714 always in PCIX mode */
17151 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 17152 } else {
17153 tp->dma_rwctrl |= 0x001b000f;
17154 }
17155 }
7e6c63f0
HM		 17156 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17157 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
1da177e4 17158
4153577a
JP		 17159 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17160 tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 17161 tp->dma_rwctrl &= 0xfffffff0;
17162
4153577a
JP		 17163 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17164 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 17165 /* Remove this if it causes problems for some boards. */
17166 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17167
17168 /* On 5700/5701 chips, we need to set this bit.
17169 * Otherwise the chip will issue cacheline transactions
17170 * to streamable DMA memory with not all the byte
17171 * enables turned on. This is an error on several
17172 * RISC PCI controllers, in particular sparc64.
17173 *
17174 * On 5703/5704 chips, this bit has been reassigned
17175 * a different meaning. In particular, it is used
17176 * on those chips to enable a PCI-X workaround.
17177 */
17178 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17179 }
17180
17181 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17182
1da177e4 17183
4153577a
JP		 17184 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17185 tg3_asic_rev(tp) != ASIC_REV_5701)
1da177e4
LT		 17186 goto out;
17187
59e6b434
DM		 17188 /* It is best to perform DMA test with maximum write burst size
17189 * to expose the 5700/5701 write DMA bug.
17190 */
17191 saved_dma_rwctrl = tp->dma_rwctrl;
17192 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17193 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17194
1da177e4
LT		 17195 while (1) {
17196 u32 *p = buf, i;
17197
17198 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17199 p[i] = i;
17200
17201 /* Send the buffer to the chip. */
953c96e0 17202 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
1da177e4 17203 if (ret) {
2445e461
MC		 17204 dev_err(&tp->pdev->dev,
17205 "%s: Buffer write failed. err = %d\n",
17206 __func__, ret);
1da177e4
LT		 17207 break;
17208 }
17209
1da177e4 17210 /* Now read it back. */
953c96e0 17211 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
1da177e4 17212 if (ret) {
5129c3a3
MC		 17213 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17214 "err = %d\n", __func__, ret);
1da177e4
LT		 17215 break;
17216 }
17217
17218 /* Verify it. */
17219 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17220 if (p[i] == i)
17221 continue;
17222
59e6b434
DM		 17223 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17224 DMA_RWCTRL_WRITE_BNDRY_16) {
17225 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 17226 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17227 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17228 break;
17229 } else {
2445e461
MC		 17230 dev_err(&tp->pdev->dev,
17231 "%s: Buffer corrupted on read back! "
17232 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 17233 ret = -ENODEV;
17234 goto out;
17235 }
17236 }
17237
17238 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17239 /* Success. */
17240 ret = 0;
17241 break;
17242 }
17243 }
59e6b434
DM		 17244 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17245 DMA_RWCTRL_WRITE_BNDRY_16) {
17246 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 17247 * now look for chipsets that are known to expose the
17248 * DMA bug without failing the test.
59e6b434 17249 */
4143470c 17250 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
6d1cfbab
MC		 17251 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17252 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
859a5887 17253 } else {
6d1cfbab
MC		 17254 /* Safe to use the calculated DMA boundary. */
17255 tp->dma_rwctrl = saved_dma_rwctrl;
859a5887 17256 }
6d1cfbab 17257
59e6b434
DM		 17258 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17259 }
1da177e4
LT		 17260
17261out:
4bae65c8 17262 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
1da177e4
LT		 17263out_nofree:
17264 return ret;
17265}
17266
229b1ad1 17267static void tg3_init_bufmgr_config(struct tg3 *tp)
1da177e4 17268{
63c3a66f 17269 if (tg3_flag(tp, 57765_PLUS)) {
666bc831
MC		 17270 tp->bufmgr_config.mbuf_read_dma_low_water =
17271 DEFAULT_MB_RDMA_LOW_WATER_5705;
17272 tp->bufmgr_config.mbuf_mac_rx_low_water =
17273 DEFAULT_MB_MACRX_LOW_WATER_57765;
17274 tp->bufmgr_config.mbuf_high_water =
17275 DEFAULT_MB_HIGH_WATER_57765;
17276
17277 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17278 DEFAULT_MB_RDMA_LOW_WATER_5705;
17279 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17280 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17281 tp->bufmgr_config.mbuf_high_water_jumbo =
17282 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
63c3a66f 17283 } else if (tg3_flag(tp, 5705_PLUS)) {
fdfec172
MC		 17284 tp->bufmgr_config.mbuf_read_dma_low_water =
17285 DEFAULT_MB_RDMA_LOW_WATER_5705;
17286 tp->bufmgr_config.mbuf_mac_rx_low_water =
17287 DEFAULT_MB_MACRX_LOW_WATER_5705;
17288 tp->bufmgr_config.mbuf_high_water =
17289 DEFAULT_MB_HIGH_WATER_5705;
4153577a 17290 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 17291 tp->bufmgr_config.mbuf_mac_rx_low_water =
17292 DEFAULT_MB_MACRX_LOW_WATER_5906;
17293 tp->bufmgr_config.mbuf_high_water =
17294 DEFAULT_MB_HIGH_WATER_5906;
17295 }
fdfec172
MC		 17296
17297 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17298 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17299 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17300 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17301 tp->bufmgr_config.mbuf_high_water_jumbo =
17302 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17303 } else {
17304 tp->bufmgr_config.mbuf_read_dma_low_water =
17305 DEFAULT_MB_RDMA_LOW_WATER;
17306 tp->bufmgr_config.mbuf_mac_rx_low_water =
17307 DEFAULT_MB_MACRX_LOW_WATER;
17308 tp->bufmgr_config.mbuf_high_water =
17309 DEFAULT_MB_HIGH_WATER;
17310
17311 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17312 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17313 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17314 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17315 tp->bufmgr_config.mbuf_high_water_jumbo =
17316 DEFAULT_MB_HIGH_WATER_JUMBO;
17317 }
1da177e4
LT		 17318
17319 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17320 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17321}
17322
229b1ad1 17323static char *tg3_phy_string(struct tg3 *tp)
1da177e4 17324{
79eb6904
MC		 17325 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17326 case TG3_PHY_ID_BCM5400: return "5400";
17327 case TG3_PHY_ID_BCM5401: return "5401";
17328 case TG3_PHY_ID_BCM5411: return "5411";
17329 case TG3_PHY_ID_BCM5701: return "5701";
17330 case TG3_PHY_ID_BCM5703: return "5703";
17331 case TG3_PHY_ID_BCM5704: return "5704";
17332 case TG3_PHY_ID_BCM5705: return "5705";
17333 case TG3_PHY_ID_BCM5750: return "5750";
17334 case TG3_PHY_ID_BCM5752: return "5752";
17335 case TG3_PHY_ID_BCM5714: return "5714";
17336 case TG3_PHY_ID_BCM5780: return "5780";
17337 case TG3_PHY_ID_BCM5755: return "5755";
17338 case TG3_PHY_ID_BCM5787: return "5787";
17339 case TG3_PHY_ID_BCM5784: return "5784";
17340 case TG3_PHY_ID_BCM5756: return "5722/5756";
17341 case TG3_PHY_ID_BCM5906: return "5906";
17342 case TG3_PHY_ID_BCM5761: return "5761";
17343 case TG3_PHY_ID_BCM5718C: return "5718C";
17344 case TG3_PHY_ID_BCM5718S: return "5718S";
17345 case TG3_PHY_ID_BCM57765: return "57765";
302b500b 17346 case TG3_PHY_ID_BCM5719C: return "5719C";
6418f2c1 17347 case TG3_PHY_ID_BCM5720C: return "5720C";
c65a17f4 17348 case TG3_PHY_ID_BCM5762: return "5762C";
79eb6904 17349 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 17350 case 0: return "serdes";
17351 default: return "unknown";
855e1111 17352 }
1da177e4
LT		 17353}
17354
229b1ad1 17355static char *tg3_bus_string(struct tg3 *tp, char *str)
f9804ddb 17356{
63c3a66f 17357 if (tg3_flag(tp, PCI_EXPRESS)) {
f9804ddb
MC		 17358 strcpy(str, "PCI Express");
17359 return str;
63c3a66f 17360 } else if (tg3_flag(tp, PCIX_MODE)) {
f9804ddb
MC		 17361 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17362
17363 strcpy(str, "PCIX:");
17364
17365 if ((clock_ctrl == 7) ||
17366 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17367 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17368 strcat(str, "133MHz");
17369 else if (clock_ctrl == 0)
17370 strcat(str, "33MHz");
17371 else if (clock_ctrl == 2)
17372 strcat(str, "50MHz");
17373 else if (clock_ctrl == 4)
17374 strcat(str, "66MHz");
17375 else if (clock_ctrl == 6)
17376 strcat(str, "100MHz");
f9804ddb
MC		 17377 } else {
17378 strcpy(str, "PCI:");
63c3a66f 17379 if (tg3_flag(tp, PCI_HIGH_SPEED))
f9804ddb
MC		 17380 strcat(str, "66MHz");
17381 else
17382 strcat(str, "33MHz");
17383 }
63c3a66f 17384 if (tg3_flag(tp, PCI_32BIT))
f9804ddb
MC		 17385 strcat(str, ":32-bit");
17386 else
17387 strcat(str, ":64-bit");
17388 return str;
17389}
17390
229b1ad1 17391static void tg3_init_coal(struct tg3 *tp)
15f9850d
DM		 17392{
17393 struct ethtool_coalesce *ec = &tp->coal;
17394
17395 memset(ec, 0, sizeof(*ec));
17396 ec->cmd = ETHTOOL_GCOALESCE;
17397 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17398 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17399 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17400 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17401 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17402 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17403 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17404 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17405 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17406
17407 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17408 HOSTCC_MODE_CLRTICK_TXBD)) {
17409 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17410 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17411 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17412 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17413 }
d244c892 17414
63c3a66f 17415 if (tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 17416 ec->rx_coalesce_usecs_irq = 0;
17417 ec->tx_coalesce_usecs_irq = 0;
17418 ec->stats_block_coalesce_usecs = 0;
17419 }
15f9850d
DM		 17420}
17421
229b1ad1 17422static int tg3_init_one(struct pci_dev *pdev,
1da177e4
LT		 17423 const struct pci_device_id *ent)
17424{
1da177e4
LT		 17425 struct net_device *dev;
17426 struct tg3 *tp;
5865fc1b 17427 int i, err;
646c9edd 17428 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 17429 char str[40];
72f2afb8 17430 u64 dma_mask, persist_dma_mask;
c8f44aff 17431 netdev_features_t features = 0;
1da177e4 17432
05dbe005 17433 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 17434
17435 err = pci_enable_device(pdev);
17436 if (err) {
2445e461 17437 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 17438 return err;
17439 }
17440
1da177e4
LT		 17441 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17442 if (err) {
2445e461 17443 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 17444 goto err_out_disable_pdev;
17445 }
17446
17447 pci_set_master(pdev);
17448
fe5f5787 17449 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 17450 if (!dev) {
1da177e4 17451 err = -ENOMEM;
5865fc1b 17452 goto err_out_free_res;
1da177e4
LT		 17453 }
17454
1da177e4
LT		 17455 SET_NETDEV_DEV(dev, &pdev->dev);
17456
1da177e4
LT		 17457 tp = netdev_priv(dev);
17458 tp->pdev = pdev;
17459 tp->dev = dev;
1da177e4
LT		 17460 tp->rx_mode = TG3_DEF_RX_MODE;
17461 tp->tx_mode = TG3_DEF_TX_MODE;
9c13cb8b 17462 tp->irq_sync = 1;
8ef21428 17463
1da177e4
LT		 17464 if (tg3_debug > 0)
17465 tp->msg_enable = tg3_debug;
17466 else
17467 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17468
7e6c63f0
HM		 17469 if (pdev_is_ssb_gige_core(pdev)) {
17470 tg3_flag_set(tp, IS_SSB_CORE);
17471 if (ssb_gige_must_flush_posted_writes(pdev))
17472 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17473 if (ssb_gige_one_dma_at_once(pdev))
17474 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
ee002b64
HM		 17475 if (ssb_gige_have_roboswitch(pdev)) {
17476 tg3_flag_set(tp, USE_PHYLIB);
7e6c63f0 17477 tg3_flag_set(tp, ROBOSWITCH);
ee002b64 17478 }
7e6c63f0
HM		 17479 if (ssb_gige_is_rgmii(pdev))
17480 tg3_flag_set(tp, RGMII_MODE);
17481 }
17482
1da177e4
LT		 17483 /* The word/byte swap controls here control register access byte
17484 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17485 * setting below.
17486 */
17487 tp->misc_host_ctrl =
17488 MISC_HOST_CTRL_MASK_PCI_INT |
17489 MISC_HOST_CTRL_WORD_SWAP |
17490 MISC_HOST_CTRL_INDIR_ACCESS |
17491 MISC_HOST_CTRL_PCISTATE_RW;
17492
17493 /* The NONFRM (non-frame) byte/word swap controls take effect
17494 * on descriptor entries, anything which isn't packet data.
17495 *
17496 * The StrongARM chips on the board (one for tx, one for rx)
17497 * are running in big-endian mode.
17498 */
17499 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17500 GRC_MODE_WSWAP_NONFRM_DATA);
17501#ifdef __BIG_ENDIAN
17502 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17503#endif
17504 spin_lock_init(&tp->lock);
1da177e4 17505 spin_lock_init(&tp->indirect_lock);
c4028958 17506 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 17507
d5fe488a 17508 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 17509 if (!tp->regs) {
ab96b241 17510 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 17511 err = -ENOMEM;
17512 goto err_out_free_dev;
17513 }
17514
c9cab24e
MC		 17515 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17516 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17517 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17518 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17519 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 17520 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
c9cab24e
MC		 17521 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17522 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 17523 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 17524 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17525 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 17526 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17527 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 17528 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17529 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
c9cab24e
MC		 17530 tg3_flag_set(tp, ENABLE_APE);
17531 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17532 if (!tp->aperegs) {
17533 dev_err(&pdev->dev,
17534 "Cannot map APE registers, aborting\n");
17535 err = -ENOMEM;
17536 goto err_out_iounmap;
17537 }
17538 }
17539
1da177e4
LT		 17540 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17541 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 17542
1da177e4 17543 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 17544 dev->watchdog_timeo = TG3_TX_TIMEOUT;
2ffcc981 17545 dev->netdev_ops = &tg3_netdev_ops;
1da177e4 17546 dev->irq = pdev->irq;
1da177e4 17547
3d567e0e 17548 err = tg3_get_invariants(tp, ent);
1da177e4 17549 if (err) {
ab96b241
MC		 17550 dev_err(&pdev->dev,
17551 "Problem fetching invariants of chip, aborting\n");
c9cab24e 17552 goto err_out_apeunmap;
1da177e4
LT		 17553 }
17554
4a29cc2e
MC		 17555 /* The EPB bridge inside 5714, 5715, and 5780 and any
17556 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 17557 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17558 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17559 * do DMA address check in tg3_start_xmit().
17560 */
63c3a66f 17561 if (tg3_flag(tp, IS_5788))
284901a9 17562 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
63c3a66f 17563 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
50cf156a 17564 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 17565#ifdef CONFIG_HIGHMEM
6a35528a 17566 dma_mask = DMA_BIT_MASK(64);
72f2afb8 17567#endif
4a29cc2e 17568 } else
6a35528a 17569 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 17570
17571 /* Configure DMA attributes. */
284901a9 17572 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 17573 err = pci_set_dma_mask(pdev, dma_mask);
17574 if (!err) {
0da0606f 17575 features |= NETIF_F_HIGHDMA;
72f2afb8
MC		 17576 err = pci_set_consistent_dma_mask(pdev,
17577 persist_dma_mask);
17578 if (err < 0) {
ab96b241
MC		 17579 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17580 "DMA for consistent allocations\n");
c9cab24e 17581 goto err_out_apeunmap;
72f2afb8
MC		 17582 }
17583 }
17584 }
284901a9
YH		 17585 if (err || dma_mask == DMA_BIT_MASK(32)) {
17586 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 17587 if (err) {
ab96b241
MC		 17588 dev_err(&pdev->dev,
17589 "No usable DMA configuration, aborting\n");
c9cab24e 17590 goto err_out_apeunmap;
72f2afb8
MC		 17591 }
17592 }
17593
fdfec172 17594 tg3_init_bufmgr_config(tp);
1da177e4 17595
f646968f 17596 features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
0da0606f
MC		 17597
17598 /* 5700 B0 chips do not support checksumming correctly due
17599 * to hardware bugs.
17600 */
4153577a 17601 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
0da0606f
MC		 17602 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17603
17604 if (tg3_flag(tp, 5755_PLUS))
17605 features |= NETIF_F_IPV6_CSUM;
17606 }
17607
4e3a7aaa
MC		 17608 /* TSO is on by default on chips that support hardware TSO.
17609 * Firmware TSO on older chips gives lower performance, so it
17610 * is off by default, but can be enabled using ethtool.
17611 */
63c3a66f
JP		 17612 if ((tg3_flag(tp, HW_TSO_1) ||
17613 tg3_flag(tp, HW_TSO_2) ||
17614 tg3_flag(tp, HW_TSO_3)) &&
0da0606f
MC		 17615 (features & NETIF_F_IP_CSUM))
17616 features |= NETIF_F_TSO;
63c3a66f 17617 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
0da0606f
MC		 17618 if (features & NETIF_F_IPV6_CSUM)
17619 features |= NETIF_F_TSO6;
63c3a66f 17620 if (tg3_flag(tp, HW_TSO_3) ||
4153577a
JP		 17621 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17622 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17623 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17624 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17625 tg3_asic_rev(tp) == ASIC_REV_57780)
0da0606f 17626 features |= NETIF_F_TSO_ECN;
b0026624 17627 }
1da177e4 17628
d542fe27
MC		 17629 dev->features |= features;
17630 dev->vlan_features |= features;
17631
06c03c02
MB		 17632 /*
17633 * Add loopback capability only for a subset of devices that support
17634 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17635 * loopback for the remaining devices.
17636 */
4153577a 17637 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
06c03c02
MB		 17638 !tg3_flag(tp, CPMU_PRESENT))
17639 /* Add the loopback capability */
0da0606f
MC		 17640 features |= NETIF_F_LOOPBACK;
17641
0da0606f 17642 dev->hw_features |= features;
e565eec3 17643 dev->priv_flags |= IFF_UNICAST_FLT;
06c03c02 17644
4153577a 17645 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
63c3a66f 17646 !tg3_flag(tp, TSO_CAPABLE) &&
1da177e4 17647 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
63c3a66f 17648 tg3_flag_set(tp, MAX_RXPEND_64);
1da177e4
LT		 17649 tp->rx_pending = 63;
17650 }
17651
1da177e4
LT		 17652 err = tg3_get_device_address(tp);
17653 if (err) {
ab96b241
MC		 17654 dev_err(&pdev->dev,
17655 "Could not obtain valid ethernet address, aborting\n");
c9cab24e 17656 goto err_out_apeunmap;
c88864df
MC		 17657 }
17658
1da177e4
LT		 17659 /*
17660 * Reset chip in case UNDI or EFI driver did not shutdown
17661 * DMA self test will enable WDMAC and we'll see (spurious)
17662 * pending DMA on the PCI bus at that point.
17663 */
17664 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17665 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 17666 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 17667 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 17668 }
17669
17670 err = tg3_test_dma(tp);
17671 if (err) {
ab96b241 17672 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
c88864df 17673 goto err_out_apeunmap;
1da177e4
LT		 17674 }
17675
78f90dcf
MC		 17676 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17677 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17678 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6fd45cb8 17679 for (i = 0; i < tp->irq_max; i++) {
78f90dcf
MC		 17680 struct tg3_napi *tnapi = &tp->napi[i];
17681
17682 tnapi->tp = tp;
17683 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17684
17685 tnapi->int_mbox = intmbx;
93a700a9 17686 if (i <= 4)
78f90dcf
MC		 17687 intmbx += 0x8;
17688 else
17689 intmbx += 0x4;
17690
17691 tnapi->consmbox = rcvmbx;
17692 tnapi->prodmbox = sndmbx;
17693
66cfd1bd 17694 if (i)
78f90dcf 17695 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
66cfd1bd 17696 else
78f90dcf 17697 tnapi->coal_now = HOSTCC_MODE_NOW;
78f90dcf 17698
63c3a66f 17699 if (!tg3_flag(tp, SUPPORT_MSIX))
78f90dcf
MC		 17700 break;
17701
17702 /*
17703 * If we support MSIX, we'll be using RSS. If we're using
17704 * RSS, the first vector only handles link interrupts and the
17705 * remaining vectors handle rx and tx interrupts. Reuse the
17706 * mailbox values for the next iteration. The values we setup
17707 * above are still useful for the single vectored mode.
17708 */
17709 if (!i)
17710 continue;
17711
17712 rcvmbx += 0x8;
17713
17714 if (sndmbx & 0x4)
17715 sndmbx -= 0x4;
17716 else
17717 sndmbx += 0xc;
17718 }
17719
15f9850d
DM		 17720 tg3_init_coal(tp);
17721
c49a1561
MC		 17722 pci_set_drvdata(pdev, dev);
17723
4153577a
JP		 17724 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17725 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17726 tg3_asic_rev(tp) == ASIC_REV_5762)
fb4ce8ad
MC		 17727 tg3_flag_set(tp, PTP_CAPABLE);
17728
21f7638e
MC		 17729 tg3_timer_init(tp);
17730
402e1398
MC		 17731 tg3_carrier_off(tp);
17732
1da177e4
LT		 17733 err = register_netdev(dev);
17734 if (err) {
ab96b241 17735 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 17736 goto err_out_apeunmap;
1da177e4
LT		 17737 }
17738
05dbe005
JP		 17739 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17740 tp->board_part_number,
4153577a 17741 tg3_chip_rev_id(tp),
05dbe005
JP		 17742 tg3_bus_string(tp, str),
17743 dev->dev_addr);
1da177e4 17744
f07e9af3 17745 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7 17746 struct phy_device *phydev;
ead2402c 17747 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
5129c3a3
MC		 17748 netdev_info(dev,
17749 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
05dbe005 17750 phydev->drv->name, dev_name(&phydev->dev));
f07e9af3
MC		 17751 } else {
17752 char *ethtype;
17753
17754 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17755 ethtype = "10/100Base-TX";
17756 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17757 ethtype = "1000Base-SX";
17758 else
17759 ethtype = "10/100/1000Base-T";
17760
5129c3a3 17761 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
47007831
MC		 17762 "(WireSpeed[%d], EEE[%d])\n",
17763 tg3_phy_string(tp), ethtype,
17764 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17765 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
f07e9af3 17766 }
05dbe005
JP		 17767
17768 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
dc668910 17769 (dev->features & NETIF_F_RXCSUM) != 0,
63c3a66f 17770 tg3_flag(tp, USE_LINKCHG_REG) != 0,
f07e9af3 17771 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
63c3a66f
JP		 17772 tg3_flag(tp, ENABLE_ASF) != 0,
17773 tg3_flag(tp, TSO_CAPABLE) != 0);
05dbe005
JP		 17774 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17775 tp->dma_rwctrl,
17776 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17777 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4 17778
b45aa2f6
MC		 17779 pci_save_state(pdev);
17780
1da177e4
LT		 17781 return 0;
17782
0d3031d9
MC		 17783err_out_apeunmap:
17784 if (tp->aperegs) {
17785 iounmap(tp->aperegs);
17786 tp->aperegs = NULL;
17787 }
17788
1da177e4 17789err_out_iounmap:
6892914f
MC		 17790 if (tp->regs) {
17791 iounmap(tp->regs);
22abe310 17792 tp->regs = NULL;
6892914f 17793 }
1da177e4
LT		 17794
17795err_out_free_dev:
17796 free_netdev(dev);
17797
17798err_out_free_res:
17799 pci_release_regions(pdev);
17800
17801err_out_disable_pdev:
c80dc13d
GS		 17802 if (pci_is_enabled(pdev))
17803 pci_disable_device(pdev);
1da177e4
LT		 17804 return err;
17805}
17806
229b1ad1 17807static void tg3_remove_one(struct pci_dev *pdev)
1da177e4
LT		 17808{
17809 struct net_device *dev = pci_get_drvdata(pdev);
17810
17811 if (dev) {
17812 struct tg3 *tp = netdev_priv(dev);
17813
e3c5530b 17814 release_firmware(tp->fw);
077f849d 17815
db219973 17816 tg3_reset_task_cancel(tp);
158d7abd 17817
e730c823 17818 if (tg3_flag(tp, USE_PHYLIB)) {
b02fd9e3 17819 tg3_phy_fini(tp);
158d7abd 17820 tg3_mdio_fini(tp);
b02fd9e3 17821 }
158d7abd 17822
1da177e4 17823 unregister_netdev(dev);
0d3031d9
MC		 17824 if (tp->aperegs) {
17825 iounmap(tp->aperegs);
17826 tp->aperegs = NULL;
17827 }
6892914f
MC		 17828 if (tp->regs) {
17829 iounmap(tp->regs);
22abe310 17830 tp->regs = NULL;
6892914f 17831 }
1da177e4
LT		 17832 free_netdev(dev);
17833 pci_release_regions(pdev);
17834 pci_disable_device(pdev);
1da177e4
LT		 17835 }
17836}
17837
aa6027ca 17838#ifdef CONFIG_PM_SLEEP
c866b7ea 17839static int tg3_suspend(struct device *device)
1da177e4 17840{
c866b7ea 17841 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17842 struct net_device *dev = pci_get_drvdata(pdev);
17843 struct tg3 *tp = netdev_priv(dev);
8496e85c
RW		 17844 int err = 0;
17845
17846 rtnl_lock();
1da177e4
LT		 17847
17848 if (!netif_running(dev))
8496e85c 17849 goto unlock;
1da177e4 17850
db219973 17851 tg3_reset_task_cancel(tp);
b02fd9e3 17852 tg3_phy_stop(tp);
1da177e4
LT		 17853 tg3_netif_stop(tp);
17854
21f7638e 17855 tg3_timer_stop(tp);
1da177e4 17856
f47c11ee 17857 tg3_full_lock(tp, 1);
1da177e4 17858 tg3_disable_ints(tp);
f47c11ee 17859 tg3_full_unlock(tp);
1da177e4
LT		 17860
17861 netif_device_detach(dev);
17862
f47c11ee 17863 tg3_full_lock(tp, 0);
944d980e 17864 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
63c3a66f 17865 tg3_flag_clear(tp, INIT_COMPLETE);
f47c11ee 17866 tg3_full_unlock(tp);
1da177e4 17867
c866b7ea 17868 err = tg3_power_down_prepare(tp);
1da177e4 17869 if (err) {
b02fd9e3
MC		 17870 int err2;
17871
f47c11ee 17872 tg3_full_lock(tp, 0);
1da177e4 17873
63c3a66f 17874 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 17875 err2 = tg3_restart_hw(tp, true);
b02fd9e3 17876 if (err2)
b9ec6c1b 17877 goto out;
1da177e4 17878
21f7638e 17879 tg3_timer_start(tp);
1da177e4
LT		 17880
17881 netif_device_attach(dev);
17882 tg3_netif_start(tp);
17883
b9ec6c1b 17884out:
f47c11ee 17885 tg3_full_unlock(tp);
b02fd9e3
MC		 17886
17887 if (!err2)
17888 tg3_phy_start(tp);
1da177e4
LT		 17889 }
17890
8496e85c
RW		 17891unlock:
17892 rtnl_unlock();
1da177e4
LT		 17893 return err;
17894}
17895
c866b7ea 17896static int tg3_resume(struct device *device)
1da177e4 17897{
c866b7ea 17898 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17899 struct net_device *dev = pci_get_drvdata(pdev);
17900 struct tg3 *tp = netdev_priv(dev);
8496e85c
RW		 17901 int err = 0;
17902
17903 rtnl_lock();
1da177e4
LT		 17904
17905 if (!netif_running(dev))
8496e85c 17906 goto unlock;
1da177e4 17907
1da177e4
LT		 17908 netif_device_attach(dev);
17909
f47c11ee 17910 tg3_full_lock(tp, 0);
1da177e4 17911
2e460fc0
NS		 17912 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
17913
63c3a66f 17914 tg3_flag_set(tp, INIT_COMPLETE);
942d1af0
NS		 17915 err = tg3_restart_hw(tp,
17916 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
b9ec6c1b
MC		 17917 if (err)
17918 goto out;
1da177e4 17919
21f7638e 17920 tg3_timer_start(tp);
1da177e4 17921
1da177e4
LT		 17922 tg3_netif_start(tp);
17923
b9ec6c1b 17924out:
f47c11ee 17925 tg3_full_unlock(tp);
1da177e4 17926
b02fd9e3
MC		 17927 if (!err)
17928 tg3_phy_start(tp);
17929
8496e85c
RW		 17930unlock:
17931 rtnl_unlock();
b9ec6c1b 17932 return err;
1da177e4 17933}
42df36a6 17934#endif /* CONFIG_PM_SLEEP */
1da177e4 17935
c866b7ea
RW		 17936static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
17937
4c305fa2
NS		 17938static void tg3_shutdown(struct pci_dev *pdev)
17939{
17940 struct net_device *dev = pci_get_drvdata(pdev);
17941 struct tg3 *tp = netdev_priv(dev);
17942
17943 rtnl_lock();
17944 netif_device_detach(dev);
17945
17946 if (netif_running(dev))
17947 dev_close(dev);
17948
17949 if (system_state == SYSTEM_POWER_OFF)
17950 tg3_power_down(tp);
17951
17952 rtnl_unlock();
17953}
17954
b45aa2f6
MC		 17955/**
17956 * tg3_io_error_detected - called when PCI error is detected
17957 * @pdev: Pointer to PCI device
17958 * @state: The current pci connection state
17959 *
17960 * This function is called after a PCI bus error affecting
17961 * this device has been detected.
17962 */
17963static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
17964 pci_channel_state_t state)
17965{
17966 struct net_device *netdev = pci_get_drvdata(pdev);
17967 struct tg3 *tp = netdev_priv(netdev);
17968 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
17969
17970 netdev_info(netdev, "PCI I/O error detected\n");
17971
17972 rtnl_lock();
17973
d8af4dfd
GS		 17974 /* We probably don't have netdev yet */
17975 if (!netdev || !netif_running(netdev))
b45aa2f6
MC		 17976 goto done;
17977
17978 tg3_phy_stop(tp);
17979
17980 tg3_netif_stop(tp);
17981
21f7638e 17982 tg3_timer_stop(tp);
b45aa2f6
MC		 17983
17984 /* Want to make sure that the reset task doesn't run */
db219973 17985 tg3_reset_task_cancel(tp);
b45aa2f6
MC		 17986
17987 netif_device_detach(netdev);
17988
17989 /* Clean up software state, even if MMIO is blocked */
17990 tg3_full_lock(tp, 0);
17991 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
17992 tg3_full_unlock(tp);
17993
17994done:
72bb72b0 17995 if (state == pci_channel_io_perm_failure) {
68293099
DB		 17996 if (netdev) {
17997 tg3_napi_enable(tp);
17998 dev_close(netdev);
17999 }
b45aa2f6 18000 err = PCI_ERS_RESULT_DISCONNECT;
72bb72b0 18001 } else {
b45aa2f6 18002 pci_disable_device(pdev);
72bb72b0 18003 }
b45aa2f6
MC		 18004
18005 rtnl_unlock();
18006
18007 return err;
18008}
18009
18010/**
18011 * tg3_io_slot_reset - called after the pci bus has been reset.
18012 * @pdev: Pointer to PCI device
18013 *
18014 * Restart the card from scratch, as if from a cold-boot.
18015 * At this point, the card has exprienced a hard reset,
18016 * followed by fixups by BIOS, and has its config space
18017 * set up identically to what it was at cold boot.
18018 */
18019static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18020{
18021 struct net_device *netdev = pci_get_drvdata(pdev);
18022 struct tg3 *tp = netdev_priv(netdev);
18023 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18024 int err;
18025
18026 rtnl_lock();
18027
18028 if (pci_enable_device(pdev)) {
68293099
DB		 18029 dev_err(&pdev->dev,
18030 "Cannot re-enable PCI device after reset.\n");
b45aa2f6
MC		 18031 goto done;
18032 }
18033
18034 pci_set_master(pdev);
18035 pci_restore_state(pdev);
18036 pci_save_state(pdev);
18037
68293099 18038 if (!netdev || !netif_running(netdev)) {
b45aa2f6
MC		 18039 rc = PCI_ERS_RESULT_RECOVERED;
18040 goto done;
18041 }
18042
18043 err = tg3_power_up(tp);
bed9829f 18044 if (err)
b45aa2f6 18045 goto done;
b45aa2f6
MC		 18046
18047 rc = PCI_ERS_RESULT_RECOVERED;
18048
18049done:
68293099 18050 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
72bb72b0
MC		 18051 tg3_napi_enable(tp);
18052 dev_close(netdev);
18053 }
b45aa2f6
MC		 18054 rtnl_unlock();
18055
18056 return rc;
18057}
18058
18059/**
18060 * tg3_io_resume - called when traffic can start flowing again.
18061 * @pdev: Pointer to PCI device
18062 *
18063 * This callback is called when the error recovery driver tells
18064 * us that its OK to resume normal operation.
18065 */
18066static void tg3_io_resume(struct pci_dev *pdev)
18067{
18068 struct net_device *netdev = pci_get_drvdata(pdev);
18069 struct tg3 *tp = netdev_priv(netdev);
18070 int err;
18071
18072 rtnl_lock();
18073
18074 if (!netif_running(netdev))
18075 goto done;
18076
18077 tg3_full_lock(tp, 0);
2e460fc0 18078 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
63c3a66f 18079 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 18080 err = tg3_restart_hw(tp, true);
b45aa2f6 18081 if (err) {
35763066 18082 tg3_full_unlock(tp);
b45aa2f6
MC		 18083 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18084 goto done;
18085 }
18086
18087 netif_device_attach(netdev);
18088
21f7638e 18089 tg3_timer_start(tp);
b45aa2f6
MC		 18090
18091 tg3_netif_start(tp);
18092
35763066
NNS		 18093 tg3_full_unlock(tp);
18094
b45aa2f6
MC		 18095 tg3_phy_start(tp);
18096
18097done:
18098 rtnl_unlock();
18099}
18100
3646f0e5 18101static const struct pci_error_handlers tg3_err_handler = {
b45aa2f6
MC		 18102 .error_detected = tg3_io_error_detected,
18103 .slot_reset = tg3_io_slot_reset,
18104 .resume = tg3_io_resume
18105};
18106
1da177e4
LT		 18107static struct pci_driver tg3_driver = {
18108 .name = DRV_MODULE_NAME,
18109 .id_table = tg3_pci_tbl,
18110 .probe = tg3_init_one,
229b1ad1 18111 .remove = tg3_remove_one,
b45aa2f6 18112 .err_handler = &tg3_err_handler,
42df36a6 18113 .driver.pm = &tg3_pm_ops,
4c305fa2 18114 .shutdown = tg3_shutdown,
1da177e4
LT		 18115};
18116
8dbb0dc2 18117module_pci_driver(tg3_driver);
Linux kernel - Deliverables
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